aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/include
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/amd/include')
-rw-r--r--drivers/gpu/drm/amd/include/amd_shared.h81
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h921
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h10250
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h1068
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_enum.h1198
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h11494
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_d.h3577
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_enum.h1068
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h33080
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h7350
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h1773
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h16647
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h7648
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h6129
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h17557
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h5703
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h13109
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h2532
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h2557
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_enum.h6274
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h18444
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h2811
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_enum.h6858
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h20776
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_d.h657
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h6116
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_d.h1464
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h14416
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_d.h1708
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_enum.h1198
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h15682
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_d.h910
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_enum.h1068
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h7850
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h642
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h2476
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h471
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_enum.h1340
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h2544
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_d.h593
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_enum.h1464
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h3558
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h688
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_enum.h1497
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h3660
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_d.h741
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h3842
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h1314
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h5456
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_d.h1344
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_enum.h1191
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h5648
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h1123
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_enum.h1205
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h4864
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h1273
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_enum.h1246
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h5834
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_d.h671
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_enum.h1072
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_sh_mask.h2964
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h95
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h800
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h114
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_enum.h1211
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h1046
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h115
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_enum.h1081
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h1034
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_d.h68
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_sh_mask.h104
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_d.h73
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_sh_mask.h120
-rw-r--r--drivers/gpu/drm/amd/include/kgd_kfd_interface.h23
74 files changed, 314579 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
new file mode 100644
index 000000000000..5bdf1b4397a0
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __AMD_SHARED_H__
+#define __AMD_SHARED_H__
+
+enum amd_ip_block_type {
+ AMD_IP_BLOCK_TYPE_COMMON,
+ AMD_IP_BLOCK_TYPE_GMC,
+ AMD_IP_BLOCK_TYPE_IH,
+ AMD_IP_BLOCK_TYPE_SMC,
+ AMD_IP_BLOCK_TYPE_DCE,
+ AMD_IP_BLOCK_TYPE_GFX,
+ AMD_IP_BLOCK_TYPE_SDMA,
+ AMD_IP_BLOCK_TYPE_UVD,
+ AMD_IP_BLOCK_TYPE_VCE,
+};
+
+enum amd_clockgating_state {
+ AMD_CG_STATE_GATE = 0,
+ AMD_CG_STATE_UNGATE,
+};
+
+enum amd_powergating_state {
+ AMD_PG_STATE_GATE = 0,
+ AMD_PG_STATE_UNGATE,
+};
+
+struct amd_ip_funcs {
+ /* sets up early driver state (pre sw_init), does not configure hw - Optional */
+ int (*early_init)(void *handle);
+ /* sets up late driver/hw state (post hw_init) - Optional */
+ int (*late_init)(void *handle);
+ /* sets up driver state, does not configure hw */
+ int (*sw_init)(void *handle);
+ /* tears down driver state, does not configure hw */
+ int (*sw_fini)(void *handle);
+ /* sets up the hw state */
+ int (*hw_init)(void *handle);
+ /* tears down the hw state */
+ int (*hw_fini)(void *handle);
+ /* handles IP specific hw/sw changes for suspend */
+ int (*suspend)(void *handle);
+ /* handles IP specific hw/sw changes for resume */
+ int (*resume)(void *handle);
+ /* returns current IP block idle status */
+ bool (*is_idle)(void *handle);
+ /* poll for idle */
+ int (*wait_for_idle)(void *handle);
+ /* soft reset the IP block */
+ int (*soft_reset)(void *handle);
+ /* dump the IP block status registers */
+ void (*print_status)(void *handle);
+ /* enable/disable cg for the IP block */
+ int (*set_clockgating_state)(void *handle,
+ enum amd_clockgating_state state);
+ /* enable/disable pg for the IP block */
+ int (*set_powergating_state)(void *handle,
+ enum amd_powergating_state state);
+};
+
+#endif /* __AMD_SHARED_H__ */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h
new file mode 100644
index 000000000000..a761ba07f937
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h
@@ -0,0 +1,921 @@
+/*
+ * BIF_4_1 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef BIF_4_1_D_H
+#define BIF_4_1_D_H
+
+#define mmMM_INDEX 0x0
+#define mmMM_INDEX_HI 0x6
+#define mmMM_DATA 0x1
+#define mmBUS_CNTL 0x1508
+#define mmCONFIG_CNTL 0x1509
+#define mmCONFIG_MEMSIZE 0x150a
+#define mmCONFIG_F0_BASE 0x150b
+#define mmCONFIG_APER_SIZE 0x150c
+#define mmCONFIG_REG_APER_SIZE 0x150d
+#define mmBIF_SCRATCH0 0x150e
+#define mmBIF_SCRATCH1 0x150f
+#define mmBX_RESET_EN 0x1514
+#define mmMM_CFGREGS_CNTL 0x1513
+#define mmHW_DEBUG 0x1515
+#define mmMASTER_CREDIT_CNTL 0x1516
+#define mmSLAVE_REQ_CREDIT_CNTL 0x1517
+#define mmBX_RESET_CNTL 0x1518
+#define mmINTERRUPT_CNTL 0x151a
+#define mmINTERRUPT_CNTL2 0x151b
+#define mmBIF_DEBUG_CNTL 0x151c
+#define mmBIF_DEBUG_MUX 0x151d
+#define mmBIF_DEBUG_OUT 0x151e
+#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528
+#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520
+#define mmCLKREQB_PAD_CNTL 0x1521
+#define mmSMBUS_SLV_CNTL 0x14fd
+#define mmSMBUS_SLV_CNTL1 0x14fe
+#define mmSMBDAT_PAD_CNTL 0x1522
+#define mmSMBCLK_PAD_CNTL 0x1523
+#define mmBIF_XDMA_LO 0x14c0
+#define mmBIF_XDMA_HI 0x14c1
+#define mmBIF_FEATURES_CONTROL_MISC 0x14c2
+#define mmBIF_DOORBELL_CNTL 0x14c3
+#define mmBIF_SLVARB_MODE 0x14c4
+#define mmBIF_FB_EN 0x1524
+#define mmBIF_BUSNUM_CNTL1 0x1525
+#define mmBIF_BUSNUM_LIST0 0x1526
+#define mmBIF_BUSNUM_LIST1 0x1527
+#define mmBIF_BUSNUM_CNTL2 0x152b
+#define mmBIF_BUSY_DELAY_CNTR 0x1529
+#define mmBIF_PERFMON_CNTL 0x152c
+#define mmBIF_PERFCOUNTER0_RESULT 0x152d
+#define mmBIF_PERFCOUNTER1_RESULT 0x152e
+#define mmSLAVE_HANG_PROTECTION_CNTL 0x1536
+#define mmGPU_HDP_FLUSH_REQ 0x1537
+#define mmGPU_HDP_FLUSH_DONE 0x1538
+#define mmSLAVE_HANG_ERROR 0x153b
+#define mmCAPTURE_HOST_BUSNUM 0x153c
+#define mmHOST_BUSNUM 0x153d
+#define mmPEER_REG_RANGE0 0x153e
+#define mmPEER_REG_RANGE1 0x153f
+#define mmPEER0_FB_OFFSET_HI 0x14f3
+#define mmPEER0_FB_OFFSET_LO 0x14f2
+#define mmPEER1_FB_OFFSET_HI 0x14f1
+#define mmPEER1_FB_OFFSET_LO 0x14f0
+#define mmPEER2_FB_OFFSET_HI 0x14ef
+#define mmPEER2_FB_OFFSET_LO 0x14ee
+#define mmPEER3_FB_OFFSET_HI 0x14ed
+#define mmPEER3_FB_OFFSET_LO 0x14ec
+#define mmDBG_BYPASS_SRBM_ACCESS 0x14eb
+#define mmSMBUS_BACO_DUMMY 0x14c6
+#define mmBIF_DEVFUNCNUM_LIST0 0x14e8
+#define mmBIF_DEVFUNCNUM_LIST1 0x14e7
+#define mmBACO_CNTL 0x14e5
+#define mmBF_ANA_ISO_CNTL 0x14c7
+#define mmMEM_TYPE_CNTL 0x14e4
+#define mmBIF_BACO_DEBUG 0x14df
+#define mmBIF_BACO_DEBUG_LATCH 0x14dc
+#define mmBACO_CNTL_MISC 0x14db
+#define mmBIF_SSA_PWR_STATUS 0x14c8
+#define mmBIF_SSA_GFX0_LOWER 0x14ca
+#define mmBIF_SSA_GFX0_UPPER 0x14cb
+#define mmBIF_SSA_GFX1_LOWER 0x14cc
+#define mmBIF_SSA_GFX1_UPPER 0x14cd
+#define mmBIF_SSA_GFX2_LOWER 0x14ce
+#define mmBIF_SSA_GFX2_UPPER 0x14cf
+#define mmBIF_SSA_GFX3_LOWER 0x14d0
+#define mmBIF_SSA_GFX3_UPPER 0x14d1
+#define mmBIF_SSA_DISP_LOWER 0x14d2
+#define mmBIF_SSA_DISP_UPPER 0x14d3
+#define mmBIF_SSA_MC_LOWER 0x14d4
+#define mmBIF_SSA_MC_UPPER 0x14d5
+#define mmIMPCTL_RESET 0x14f5
+#define mmGARLIC_FLUSH_CNTL 0x1401
+#define mmGARLIC_FLUSH_ADDR_START_0 0x1402
+#define mmGARLIC_FLUSH_ADDR_START_1 0x1404
+#define mmGARLIC_FLUSH_ADDR_START_2 0x1406
+#define mmGARLIC_FLUSH_ADDR_START_3 0x1408
+#define mmGARLIC_FLUSH_ADDR_START_4 0x140a
+#define mmGARLIC_FLUSH_ADDR_START_5 0x140c
+#define mmGARLIC_FLUSH_ADDR_START_6 0x140e
+#define mmGARLIC_FLUSH_ADDR_START_7 0x1410
+#define mmGARLIC_FLUSH_ADDR_END_0 0x1403
+#define mmGARLIC_FLUSH_ADDR_END_1 0x1405
+#define mmGARLIC_FLUSH_ADDR_END_2 0x1407
+#define mmGARLIC_FLUSH_ADDR_END_3 0x1409
+#define mmGARLIC_FLUSH_ADDR_END_4 0x140b
+#define mmGARLIC_FLUSH_ADDR_END_5 0x140d
+#define mmGARLIC_FLUSH_ADDR_END_6 0x140f
+#define mmGARLIC_FLUSH_ADDR_END_7 0x1411
+#define mmGARLIC_FLUSH_REQ 0x1412
+#define mmGPU_GARLIC_FLUSH_REQ 0x1413
+#define mmGPU_GARLIC_FLUSH_DONE 0x1414
+#define mmGARLIC_COHE_CP_RB0_WPTR 0x1415
+#define mmGARLIC_COHE_CP_RB1_WPTR 0x1416
+#define mmGARLIC_COHE_CP_RB2_WPTR 0x1417
+#define mmGARLIC_COHE_UVD_RBC_RB_WPTR 0x1418
+#define mmGARLIC_COHE_SDMA0_GFX_RB_WPTR 0x1419
+#define mmGARLIC_COHE_SDMA1_GFX_RB_WPTR 0x141a
+#define mmGARLIC_COHE_CP_DMA_ME_COMMAND 0x141b
+#define mmGARLIC_COHE_CP_DMA_PFP_COMMAND 0x141c
+#define mmGARLIC_COHE_SAM_SAB_RBI_WPTR 0x141d
+#define mmGARLIC_COHE_SAM_SAB_RBO_WPTR 0x141e
+#define mmGARLIC_COHE_VCE_OUT_RB_WPTR 0x141f
+#define mmGARLIC_COHE_VCE_RB_WPTR2 0x1420
+#define mmGARLIC_COHE_VCE_RB_WPTR 0x1421
+#define mmBIOS_SCRATCH_0 0x5c9
+#define mmBIOS_SCRATCH_1 0x5ca
+#define mmBIOS_SCRATCH_2 0x5cb
+#define mmBIOS_SCRATCH_3 0x5cc
+#define mmBIOS_SCRATCH_4 0x5cd
+#define mmBIOS_SCRATCH_5 0x5ce
+#define mmBIOS_SCRATCH_6 0x5cf
+#define mmBIOS_SCRATCH_7 0x5d0
+#define mmBIOS_SCRATCH_8 0x5d1
+#define mmBIOS_SCRATCH_9 0x5d2
+#define mmBIOS_SCRATCH_10 0x5d3
+#define mmBIOS_SCRATCH_11 0x5d4
+#define mmBIOS_SCRATCH_12 0x5d5
+#define mmBIOS_SCRATCH_13 0x5d6
+#define mmBIOS_SCRATCH_14 0x5d7
+#define mmBIOS_SCRATCH_15 0x5d8
+#define mmVENDOR_ID 0x0
+#define mmDEVICE_ID 0x0
+#define mmCOMMAND 0x1
+#define mmSTATUS 0x1
+#define mmREVISION_ID 0x2
+#define mmPROG_INTERFACE 0x2
+#define mmSUB_CLASS 0x2
+#define mmBASE_CLASS 0x2
+#define mmCACHE_LINE 0x3
+#define mmLATENCY 0x3
+#define mmHEADER 0x3
+#define mmBIST 0x3
+#define mmBASE_ADDR_1 0x4
+#define mmBASE_ADDR_2 0x5
+#define mmBASE_ADDR_3 0x6
+#define mmBASE_ADDR_4 0x7
+#define mmBASE_ADDR_5 0x8
+#define mmBASE_ADDR_6 0x9
+#define mmROM_BASE_ADDR 0xc
+#define mmCAP_PTR 0xd
+#define mmINTERRUPT_LINE 0xf
+#define mmINTERRUPT_PIN 0xf
+#define mmADAPTER_ID 0xb
+#define mmMIN_GRANT 0xf
+#define mmMAX_LATENCY 0xf
+#define mmVENDOR_CAP_LIST 0x12
+#define mmADAPTER_ID_W 0x13
+#define mmPMI_CAP_LIST 0x14
+#define mmPMI_CAP 0x14
+#define mmPMI_STATUS_CNTL 0x15
+#define mmPCIE_CAP_LIST 0x16
+#define mmPCIE_CAP 0x16
+#define mmDEVICE_CAP 0x17
+#define mmDEVICE_CNTL 0x18
+#define mmDEVICE_STATUS 0x18
+#define mmLINK_CAP 0x19
+#define mmLINK_CNTL 0x1a
+#define mmLINK_STATUS 0x1a
+#define mmDEVICE_CAP2 0x1f
+#define mmDEVICE_CNTL2 0x20
+#define mmDEVICE_STATUS2 0x20
+#define mmLINK_CAP2 0x21
+#define mmLINK_CNTL2 0x22
+#define mmLINK_STATUS2 0x22
+#define mmMSI_CAP_LIST 0x28
+#define mmMSI_MSG_CNTL 0x28
+#define mmMSI_MSG_ADDR_LO 0x29
+#define mmMSI_MSG_ADDR_HI 0x2a
+#define mmMSI_MSG_DATA_64 0x2b
+#define mmMSI_MSG_DATA 0x2a
+#define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x40
+#define mmPCIE_VENDOR_SPECIFIC_HDR 0x41
+#define mmPCIE_VENDOR_SPECIFIC1 0x42
+#define mmPCIE_VENDOR_SPECIFIC2 0x43
+#define mmPCIE_VC_ENH_CAP_LIST 0x44
+#define mmPCIE_PORT_VC_CAP_REG1 0x45
+#define mmPCIE_PORT_VC_CAP_REG2 0x46
+#define mmPCIE_PORT_VC_CNTL 0x47
+#define mmPCIE_PORT_VC_STATUS 0x47
+#define mmPCIE_VC0_RESOURCE_CAP 0x48
+#define mmPCIE_VC0_RESOURCE_CNTL 0x49
+#define mmPCIE_VC0_RESOURCE_STATUS 0x4a
+#define mmPCIE_VC1_RESOURCE_CAP 0x4b
+#define mmPCIE_VC1_RESOURCE_CNTL 0x4c
+#define mmPCIE_VC1_RESOURCE_STATUS 0x4d
+#define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x50
+#define mmPCIE_DEV_SERIAL_NUM_DW1 0x51
+#define mmPCIE_DEV_SERIAL_NUM_DW2 0x52
+#define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x54
+#define mmPCIE_UNCORR_ERR_STATUS 0x55
+#define mmPCIE_UNCORR_ERR_MASK 0x56
+#define mmPCIE_UNCORR_ERR_SEVERITY 0x57
+#define mmPCIE_CORR_ERR_STATUS 0x58
+#define mmPCIE_CORR_ERR_MASK 0x59
+#define mmPCIE_ADV_ERR_CAP_CNTL 0x5a
+#define mmPCIE_HDR_LOG0 0x5b
+#define mmPCIE_HDR_LOG1 0x5c
+#define mmPCIE_HDR_LOG2 0x5d
+#define mmPCIE_HDR_LOG3 0x5e
+#define mmPCIE_TLP_PREFIX_LOG0 0x62
+#define mmPCIE_TLP_PREFIX_LOG1 0x63
+#define mmPCIE_TLP_PREFIX_LOG2 0x64
+#define mmPCIE_TLP_PREFIX_LOG3 0x65
+#define mmPCIE_BAR_ENH_CAP_LIST 0x80
+#define mmPCIE_BAR1_CAP 0x81
+#define mmPCIE_BAR1_CNTL 0x82
+#define mmPCIE_BAR2_CAP 0x83
+#define mmPCIE_BAR2_CNTL 0x84
+#define mmPCIE_BAR3_CAP 0x85
+#define mmPCIE_BAR3_CNTL 0x86
+#define mmPCIE_BAR4_CAP 0x87
+#define mmPCIE_BAR4_CNTL 0x88
+#define mmPCIE_BAR5_CAP 0x89
+#define mmPCIE_BAR5_CNTL 0x8a
+#define mmPCIE_BAR6_CAP 0x8b
+#define mmPCIE_BAR6_CNTL 0x8c
+#define mmPCIE_PWR_BUDGET_ENH_CAP_LIST 0x90
+#define mmPCIE_PWR_BUDGET_DATA_SELECT 0x91
+#define mmPCIE_PWR_BUDGET_DATA 0x92
+#define mmPCIE_PWR_BUDGET_CAP 0x93
+#define mmPCIE_DPA_ENH_CAP_LIST 0x94
+#define mmPCIE_DPA_CAP 0x95
+#define mmPCIE_DPA_LATENCY_INDICATOR 0x96
+#define mmPCIE_DPA_STATUS 0x97
+#define mmPCIE_DPA_CNTL 0x97
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x98
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x98
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x98
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x98
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x99
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x99
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x99
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x99
+#define mmPCIE_SECONDARY_ENH_CAP_LIST 0x9c
+#define mmPCIE_LINK_CNTL3 0x9d
+#define mmPCIE_LANE_ERROR_STATUS 0x9e
+#define mmPCIE_LANE_0_EQUALIZATION_CNTL 0x9f
+#define mmPCIE_LANE_1_EQUALIZATION_CNTL 0x9f
+#define mmPCIE_LANE_2_EQUALIZATION_CNTL 0xa0
+#define mmPCIE_LANE_3_EQUALIZATION_CNTL 0xa0
+#define mmPCIE_LANE_4_EQUALIZATION_CNTL 0xa1
+#define mmPCIE_LANE_5_EQUALIZATION_CNTL 0xa1
+#define mmPCIE_LANE_6_EQUALIZATION_CNTL 0xa2
+#define mmPCIE_LANE_7_EQUALIZATION_CNTL 0xa2
+#define mmPCIE_LANE_8_EQUALIZATION_CNTL 0xa3
+#define mmPCIE_LANE_9_EQUALIZATION_CNTL 0xa3
+#define mmPCIE_LANE_10_EQUALIZATION_CNTL 0xa4
+#define mmPCIE_LANE_11_EQUALIZATION_CNTL 0xa4
+#define mmPCIE_LANE_12_EQUALIZATION_CNTL 0xa5
+#define mmPCIE_LANE_13_EQUALIZATION_CNTL 0xa5
+#define mmPCIE_LANE_14_EQUALIZATION_CNTL 0xa6
+#define mmPCIE_LANE_15_EQUALIZATION_CNTL 0xa6
+#define mmPCIE_ACS_ENH_CAP_LIST 0xa8
+#define mmPCIE_ACS_CAP 0xa9
+#define mmPCIE_ACS_CNTL 0xa9
+#define mmPCIE_ATS_ENH_CAP_LIST 0xac
+#define mmPCIE_ATS_CAP 0xad
+#define mmPCIE_ATS_CNTL 0xad
+#define mmPCIE_PAGE_REQ_ENH_CAP_LIST 0xb0
+#define mmPCIE_PAGE_REQ_CNTL 0xb1
+#define mmPCIE_PAGE_REQ_STATUS 0xb1
+#define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xb2
+#define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC 0xb3
+#define mmPCIE_PASID_ENH_CAP_LIST 0xb4
+#define mmPCIE_PASID_CAP 0xb5
+#define mmPCIE_PASID_CNTL 0xb5
+#define mmPCIE_TPH_REQR_ENH_CAP_LIST 0xb8
+#define mmPCIE_TPH_REQR_CAP 0xb9
+#define mmPCIE_TPH_REQR_CNTL 0xba
+#define mmPCIE_MC_ENH_CAP_LIST 0xbc
+#define mmPCIE_MC_CAP 0xbd
+#define mmPCIE_MC_CNTL 0xbd
+#define mmPCIE_MC_ADDR0 0xbe
+#define mmPCIE_MC_ADDR1 0xbf
+#define mmPCIE_MC_RCV0 0xc0
+#define mmPCIE_MC_RCV1 0xc1
+#define mmPCIE_MC_BLOCK_ALL0 0xc2
+#define mmPCIE_MC_BLOCK_ALL1 0xc3
+#define mmPCIE_MC_BLOCK_UNTRANSLATED_0 0xc4
+#define mmPCIE_MC_BLOCK_UNTRANSLATED_1 0xc5
+#define mmPCIE_LTR_ENH_CAP_LIST 0xc8
+#define mmPCIE_LTR_CAP 0xc9
+#define mmPCIE_INDEX 0xe
+#define mmPCIE_DATA 0xf
+#define mmPCIE_INDEX_2 0xc
+#define mmPCIE_DATA_2 0xd
+#define ixPCIE_RESERVED 0x1400000
+#define ixPCIE_SCRATCH 0x1400001
+#define ixPCIE_HW_DEBUG 0x1400002
+#define ixPCIE_RX_NUM_NAK 0x140000e
+#define ixPCIE_RX_NUM_NAK_GENERATED 0x140000f
+#define ixPCIE_CNTL 0x1400010
+#define ixPCIE_CONFIG_CNTL 0x1400011
+#define ixPCIE_DEBUG_CNTL 0x1400012
+#define ixPCIE_INT_CNTL 0x140001a
+#define ixPCIE_INT_STATUS 0x140001b
+#define ixPCIE_CNTL2 0x140001c
+#define ixPCIE_RX_CNTL2 0x140001d
+#define ixPCIE_TX_F0_ATTR_CNTL 0x140001e
+#define ixPCIE_TX_F1_F2_ATTR_CNTL 0x140001f
+#define ixPCIE_CI_CNTL 0x1400020
+#define ixPCIE_BUS_CNTL 0x1400021
+#define ixPCIE_LC_STATE6 0x1400022
+#define ixPCIE_LC_STATE7 0x1400023
+#define ixPCIE_LC_STATE8 0x1400024
+#define ixPCIE_LC_STATE9 0x1400025
+#define ixPCIE_LC_STATE10 0x1400026
+#define ixPCIE_LC_STATE11 0x1400027
+#define ixPCIE_LC_STATUS1 0x1400028
+#define ixPCIE_LC_STATUS2 0x1400029
+#define ixPCIE_WPR_CNTL 0x1400030
+#define ixPCIE_RX_LAST_TLP0 0x1400031
+#define ixPCIE_RX_LAST_TLP1 0x1400032
+#define ixPCIE_RX_LAST_TLP2 0x1400033
+#define ixPCIE_RX_LAST_TLP3 0x1400034
+#define ixPCIE_TX_LAST_TLP0 0x1400035
+#define ixPCIE_TX_LAST_TLP1 0x1400036
+#define ixPCIE_TX_LAST_TLP2 0x1400037
+#define ixPCIE_TX_LAST_TLP3 0x1400038
+#define ixPCIE_I2C_REG_ADDR_EXPAND 0x140003a
+#define ixPCIE_I2C_REG_DATA 0x140003b
+#define ixPCIE_CFG_CNTL 0x140003c
+#define ixPCIE_P_CNTL 0x1400040
+#define ixPCIE_P_BUF_STATUS 0x1400041
+#define ixPCIE_P_DECODER_STATUS 0x1400042
+#define ixPCIE_P_MISC_STATUS 0x1400043
+#define ixPCIE_P_RCV_L0S_FTS_DET 0x1400050
+#define ixPCIE_OBFF_CNTL 0x1400061
+#define ixPCIE_TX_LTR_CNTL 0x1400060
+#define ixPCIE_PERF_COUNT_CNTL 0x1400080
+#define ixPCIE_PERF_CNTL_TXCLK 0x1400081
+#define ixPCIE_PERF_COUNT0_TXCLK 0x1400082
+#define ixPCIE_PERF_COUNT1_TXCLK 0x1400083
+#define ixPCIE_PERF_CNTL_MST_R_CLK 0x1400084
+#define ixPCIE_PERF_COUNT0_MST_R_CLK 0x1400085
+#define ixPCIE_PERF_COUNT1_MST_R_CLK 0x1400086
+#define ixPCIE_PERF_CNTL_MST_C_CLK 0x1400087
+#define ixPCIE_PERF_COUNT0_MST_C_CLK 0x1400088
+#define ixPCIE_PERF_COUNT1_MST_C_CLK 0x1400089
+#define ixPCIE_PERF_CNTL_SLV_R_CLK 0x140008a
+#define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x140008b
+#define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x140008c
+#define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d
+#define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e
+#define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f
+#define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090
+#define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091
+#define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092
+#define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093
+#define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094
+#define ixPCIE_PERF_CNTL_TXCLK2 0x1400095
+#define ixPCIE_PERF_COUNT0_TXCLK2 0x1400096
+#define ixPCIE_PERF_COUNT1_TXCLK2 0x1400097
+#define ixPCIE_STRAP_F0 0x14000b0
+#define ixPCIE_STRAP_F1 0x14000b1
+#define ixPCIE_STRAP_F2 0x14000b2
+#define ixPCIE_STRAP_F3 0x14000b3
+#define ixPCIE_STRAP_F4 0x14000b4
+#define ixPCIE_STRAP_F5 0x14000b5
+#define ixPCIE_STRAP_F6 0x14000b6
+#define ixPCIE_STRAP_F7 0x14000b7
+#define ixPCIE_STRAP_MISC 0x14000c0
+#define ixPCIE_STRAP_MISC2 0x14000c1
+#define ixPCIE_STRAP_PI 0x14000c2
+#define ixPCIE_STRAP_I2C_BD 0x14000c4
+#define ixPCIE_PRBS_CLR 0x14000c8
+#define ixPCIE_PRBS_STATUS1 0x14000c9
+#define ixPCIE_PRBS_STATUS2 0x14000ca
+#define ixPCIE_PRBS_FREERUN 0x14000cb
+#define ixPCIE_PRBS_MISC 0x14000cc
+#define ixPCIE_PRBS_USER_PATTERN 0x14000cd
+#define ixPCIE_PRBS_LO_BITCNT 0x14000ce
+#define ixPCIE_PRBS_HI_BITCNT 0x14000cf
+#define ixPCIE_PRBS_ERRCNT_0 0x14000d0
+#define ixPCIE_PRBS_ERRCNT_1 0x14000d1
+#define ixPCIE_PRBS_ERRCNT_2 0x14000d2
+#define ixPCIE_PRBS_ERRCNT_3 0x14000d3
+#define ixPCIE_PRBS_ERRCNT_4 0x14000d4
+#define ixPCIE_PRBS_ERRCNT_5 0x14000d5
+#define ixPCIE_PRBS_ERRCNT_6 0x14000d6
+#define ixPCIE_PRBS_ERRCNT_7 0x14000d7
+#define ixPCIE_PRBS_ERRCNT_8 0x14000d8
+#define ixPCIE_PRBS_ERRCNT_9 0x14000d9
+#define ixPCIE_PRBS_ERRCNT_10 0x14000da
+#define ixPCIE_PRBS_ERRCNT_11 0x14000db
+#define ixPCIE_PRBS_ERRCNT_12 0x14000dc
+#define ixPCIE_PRBS_ERRCNT_13 0x14000dd
+#define ixPCIE_PRBS_ERRCNT_14 0x14000de
+#define ixPCIE_PRBS_ERRCNT_15 0x14000df
+#define ixPCIE_F0_DPA_CAP 0x14000e0
+#define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x14000e4
+#define ixPCIE_F0_DPA_CNTL 0x14000e5
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x14000e7
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x14000e8
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x14000e9
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x14000ea
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x14000eb
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x14000ec
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x14000ed
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x14000ee
+#define ixPCIEP_RESERVED 0x10010000
+#define ixPCIEP_SCRATCH 0x10010001
+#define ixPCIEP_HW_DEBUG 0x10010002
+#define ixPCIEP_PORT_CNTL 0x10010010
+#define ixPCIE_TX_CNTL 0x10010020
+#define ixPCIE_TX_REQUESTER_ID 0x10010021
+#define ixPCIE_TX_VENDOR_SPECIFIC 0x10010022
+#define ixPCIE_TX_REQUEST_NUM_CNTL 0x10010023
+#define ixPCIE_TX_SEQ 0x10010024
+#define ixPCIE_TX_REPLAY 0x10010025
+#define ixPCIE_TX_ACK_LATENCY_LIMIT 0x10010026
+#define ixPCIE_TX_CREDITS_ADVT_P 0x10010030
+#define ixPCIE_TX_CREDITS_ADVT_NP 0x10010031
+#define ixPCIE_TX_CREDITS_ADVT_CPL 0x10010032
+#define ixPCIE_TX_CREDITS_INIT_P 0x10010033
+#define ixPCIE_TX_CREDITS_INIT_NP 0x10010034
+#define ixPCIE_TX_CREDITS_INIT_CPL 0x10010035
+#define ixPCIE_TX_CREDITS_STATUS 0x10010036
+#define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x10010037
+#define ixPCIE_P_PORT_LANE_STATUS 0x10010050
+#define ixPCIE_FC_P 0x10010060
+#define ixPCIE_FC_NP 0x10010061
+#define ixPCIE_FC_CPL 0x10010062
+#define ixPCIE_ERR_CNTL 0x1001006a
+#define ixPCIE_RX_CNTL 0x10010070
+#define ixPCIE_RX_EXPECTED_SEQNUM 0x10010071
+#define ixPCIE_RX_VENDOR_SPECIFIC 0x10010072
+#define ixPCIE_RX_CNTL3 0x10010074
+#define ixPCIE_RX_CREDITS_ALLOCATED_P 0x10010080
+#define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x10010081
+#define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x10010082
+#define ixPCIE_LC_CNTL 0x100100a0
+#define ixPCIE_LC_CNTL2 0x100100b1
+#define ixPCIE_LC_CNTL3 0x100100b5
+#define ixPCIE_LC_CNTL4 0x100100b6
+#define ixPCIE_LC_CNTL5 0x100100b7
+#define ixPCIE_LC_BW_CHANGE_CNTL 0x100100b2
+#define ixPCIE_LC_TRAINING_CNTL 0x100100a1
+#define ixPCIE_LC_LINK_WIDTH_CNTL 0x100100a2
+#define ixPCIE_LC_N_FTS_CNTL 0x100100a3
+#define ixPCIE_LC_SPEED_CNTL 0x100100a4
+#define ixPCIE_LC_CDR_CNTL 0x100100b3
+#define ixPCIE_LC_LANE_CNTL 0x100100b4
+#define ixPCIE_LC_FORCE_COEFF 0x100100b8
+#define ixPCIE_LC_BEST_EQ_SETTINGS 0x100100b9
+#define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x100100ba
+#define ixPCIE_LC_STATE0 0x100100a5
+#define ixPCIE_LC_STATE1 0x100100a6
+#define ixPCIE_LC_STATE2 0x100100a7
+#define ixPCIE_LC_STATE3 0x100100a8
+#define ixPCIE_LC_STATE4 0x100100a9
+#define ixPCIE_LC_STATE5 0x100100aa
+#define ixPCIEP_STRAP_LC 0x100100c0
+#define ixPCIEP_STRAP_MISC 0x100100c1
+#define ixPCIEP_BCH_ECC_CNTL 0x100100d0
+#define ixPB0_GLB_CTRL_REG0 0x1200004
+#define ixPB0_GLB_CTRL_REG1 0x1200008
+#define ixPB0_GLB_CTRL_REG2 0x120000c
+#define ixPB0_GLB_CTRL_REG3 0x1200010
+#define ixPB0_GLB_CTRL_REG4 0x1200014
+#define ixPB0_GLB_CTRL_REG5 0x1200018
+#define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x120001c
+#define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x1200020
+#define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x1200024
+#define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x1200028
+#define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x120002c
+#define ixPB0_GLB_OVRD_REG0 0x1200030
+#define ixPB0_GLB_OVRD_REG1 0x1200034
+#define ixPB0_GLB_OVRD_REG2 0x1200038
+#define ixPB0_HW_DEBUG 0x1202004
+#define ixPB0_STRAP_GLB_REG0 0x1202020
+#define ixPB0_STRAP_TX_REG0 0x1202024
+#define ixPB0_STRAP_RX_REG0 0x1202028
+#define ixPB0_STRAP_RX_REG1 0x120202c
+#define ixPB0_STRAP_PLL_REG0 0x1202030
+#define ixPB0_STRAP_PIN_REG0 0x1202034
+#define ixPB0_DFT_JIT_INJ_REG0 0x1203000
+#define ixPB0_DFT_JIT_INJ_REG1 0x1203004
+#define ixPB0_DFT_JIT_INJ_REG2 0x1203008
+#define ixPB0_DFT_DEBUG_CTRL_REG0 0x120300c
+#define ixPB0_DFT_JIT_INJ_STAT_REG0 0x1203010
+#define ixPB0_PLL_RO_GLB_CTRL_REG0 0x1204000
+#define ixPB0_PLL_RO_GLB_OVRD_REG0 0x1204010
+#define ixPB0_PLL_RO0_CTRL_REG0 0x1204440
+#define ixPB0_PLL_RO0_OVRD_REG0 0x1204450
+#define ixPB0_PLL_RO0_OVRD_REG1 0x1204454
+#define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x1204460
+#define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x1204464
+#define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x1204468
+#define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x120446c
+#define ixPB0_PLL_LC0_CTRL_REG0 0x1204480
+#define ixPB0_PLL_LC0_OVRD_REG0 0x1204490
+#define ixPB0_PLL_LC0_OVRD_REG1 0x1204494
+#define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x1204500
+#define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x1204504
+#define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x1204508
+#define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x120450c
+#define ixPB0_RX_GLB_CTRL_REG0 0x1206000
+#define ixPB0_RX_GLB_CTRL_REG1 0x1206004
+#define ixPB0_RX_GLB_CTRL_REG2 0x1206008
+#define ixPB0_RX_GLB_CTRL_REG3 0x120600c
+#define ixPB0_RX_GLB_CTRL_REG4 0x1206010
+#define ixPB0_RX_GLB_CTRL_REG5 0x1206014
+#define ixPB0_RX_GLB_CTRL_REG6 0x1206018
+#define ixPB0_RX_GLB_CTRL_REG7 0x120601c
+#define ixPB0_RX_GLB_CTRL_REG8 0x1206020
+#define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 0x1206028
+#define ixPB0_RX_GLB_OVRD_REG0 0x1206030
+#define ixPB0_RX_GLB_OVRD_REG1 0x1206034
+#define ixPB0_RX_LANE0_CTRL_REG0 0x1206440
+#define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 0x1206448
+#define ixPB0_RX_LANE1_CTRL_REG0 0x1206480
+#define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 0x1206488
+#define ixPB0_RX_LANE2_CTRL_REG0 0x1206500
+#define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 0x1206508
+#define ixPB0_RX_LANE3_CTRL_REG0 0x1206600
+#define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 0x1206608
+#define ixPB0_RX_LANE4_CTRL_REG0 0x1206800
+#define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 0x1206848
+#define ixPB0_RX_LANE5_CTRL_REG0 0x1206880
+#define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 0x1206888
+#define ixPB0_RX_LANE6_CTRL_REG0 0x1206900
+#define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 0x1206908
+#define ixPB0_RX_LANE7_CTRL_REG0 0x1206a00
+#define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 0x1206a08
+#define ixPB0_RX_LANE8_CTRL_REG0 0x1207440
+#define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 0x1207448
+#define ixPB0_RX_LANE9_CTRL_REG0 0x1207480
+#define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 0x1207488
+#define ixPB0_RX_LANE10_CTRL_REG0 0x1207500
+#define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 0x1207508
+#define ixPB0_RX_LANE11_CTRL_REG0 0x1207600
+#define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 0x1207608
+#define ixPB0_RX_LANE12_CTRL_REG0 0x1207840
+#define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 0x1207848
+#define ixPB0_RX_LANE13_CTRL_REG0 0x1207880
+#define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 0x1207888
+#define ixPB0_RX_LANE14_CTRL_REG0 0x1207900
+#define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 0x1207908
+#define ixPB0_RX_LANE15_CTRL_REG0 0x1207a00
+#define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 0x1207a08
+#define ixPB0_TX_GLB_CTRL_REG0 0x1208000
+#define ixPB0_TX_GLB_LANE_SKEW_CTRL 0x1208004
+#define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 0x1208010
+#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x1208014
+#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x1208018
+#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x120801c
+#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x1208020
+#define ixPB0_TX_GLB_OVRD_REG0 0x1208030
+#define ixPB0_TX_GLB_OVRD_REG1 0x1208034
+#define ixPB0_TX_GLB_OVRD_REG2 0x1208038
+#define ixPB0_TX_GLB_OVRD_REG3 0x120803c
+#define ixPB0_TX_GLB_OVRD_REG4 0x1208040
+#define ixPB0_TX_LANE0_CTRL_REG0 0x1208440
+#define ixPB0_TX_LANE0_OVRD_REG0 0x1208444
+#define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 0x1208448
+#define ixPB0_TX_LANE1_CTRL_REG0 0x1208480
+#define ixPB0_TX_LANE1_OVRD_REG0 0x1208484
+#define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 0x1208488
+#define ixPB0_TX_LANE2_CTRL_REG0 0x1208500
+#define ixPB0_TX_LANE2_OVRD_REG0 0x1208504
+#define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 0x1208508
+#define ixPB0_TX_LANE3_CTRL_REG0 0x1208600
+#define ixPB0_TX_LANE3_OVRD_REG0 0x1208604
+#define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 0x1208608
+#define ixPB0_TX_LANE4_CTRL_REG0 0x1208840
+#define ixPB0_TX_LANE4_OVRD_REG0 0x1208844
+#define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 0x1208848
+#define ixPB0_TX_LANE5_CTRL_REG0 0x1208880
+#define ixPB0_TX_LANE5_OVRD_REG0 0x1208884
+#define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 0x1208888
+#define ixPB0_TX_LANE6_CTRL_REG0 0x1208900
+#define ixPB0_TX_LANE6_OVRD_REG0 0x1208904
+#define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 0x1208908
+#define ixPB0_TX_LANE7_CTRL_REG0 0x1208a00
+#define ixPB0_TX_LANE7_OVRD_REG0 0x1208a04
+#define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 0x1208a08
+#define ixPB0_TX_LANE8_CTRL_REG0 0x1209440
+#define ixPB0_TX_LANE8_OVRD_REG0 0x1209444
+#define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 0x1209448
+#define ixPB0_TX_LANE9_CTRL_REG0 0x1209480
+#define ixPB0_TX_LANE9_OVRD_REG0 0x1209484
+#define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 0x1209488
+#define ixPB0_TX_LANE10_CTRL_REG0 0x1209500
+#define ixPB0_TX_LANE10_OVRD_REG0 0x1209504
+#define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 0x1209508
+#define ixPB0_TX_LANE11_CTRL_REG0 0x1209600
+#define ixPB0_TX_LANE11_OVRD_REG0 0x1209604
+#define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 0x1209608
+#define ixPB0_TX_LANE12_CTRL_REG0 0x1209840
+#define ixPB0_TX_LANE12_OVRD_REG0 0x1209844
+#define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 0x1209848
+#define ixPB0_TX_LANE13_CTRL_REG0 0x1209880
+#define ixPB0_TX_LANE13_OVRD_REG0 0x1209884
+#define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 0x1209888
+#define ixPB0_TX_LANE14_CTRL_REG0 0x1209900
+#define ixPB0_TX_LANE14_OVRD_REG0 0x1209904
+#define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 0x1209908
+#define ixPB0_TX_LANE15_CTRL_REG0 0x1209a00
+#define ixPB0_TX_LANE15_OVRD_REG0 0x1209a04
+#define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 0x1209a08
+#define ixPB1_GLB_CTRL_REG0 0x2200004
+#define ixPB1_GLB_CTRL_REG1 0x2200008
+#define ixPB1_GLB_CTRL_REG2 0x220000c
+#define ixPB1_GLB_CTRL_REG3 0x2200010
+#define ixPB1_GLB_CTRL_REG4 0x2200014
+#define ixPB1_GLB_CTRL_REG5 0x2200018
+#define ixPB1_GLB_SCI_STAT_OVRD_REG0 0x220001c
+#define ixPB1_GLB_SCI_STAT_OVRD_REG1 0x2200020
+#define ixPB1_GLB_SCI_STAT_OVRD_REG2 0x2200024
+#define ixPB1_GLB_SCI_STAT_OVRD_REG3 0x2200028
+#define ixPB1_GLB_SCI_STAT_OVRD_REG4 0x220002c
+#define ixPB1_GLB_OVRD_REG0 0x2200030
+#define ixPB1_GLB_OVRD_REG1 0x2200034
+#define ixPB1_GLB_OVRD_REG2 0x2200038
+#define ixPB1_HW_DEBUG 0x2202004
+#define ixPB1_STRAP_GLB_REG0 0x2202020
+#define ixPB1_STRAP_TX_REG0 0x2202024
+#define ixPB1_STRAP_RX_REG0 0x2202028
+#define ixPB1_STRAP_RX_REG1 0x220202c
+#define ixPB1_STRAP_PLL_REG0 0x2202030
+#define ixPB1_STRAP_PIN_REG0 0x2202034
+#define ixPB1_DFT_JIT_INJ_REG0 0x2203000
+#define ixPB1_DFT_JIT_INJ_REG1 0x2203004
+#define ixPB1_DFT_JIT_INJ_REG2 0x2203008
+#define ixPB1_DFT_DEBUG_CTRL_REG0 0x220300c
+#define ixPB1_DFT_JIT_INJ_STAT_REG0 0x2203010
+#define ixPB1_PLL_RO_GLB_CTRL_REG0 0x2204000
+#define ixPB1_PLL_RO_GLB_OVRD_REG0 0x2204010
+#define ixPB1_PLL_RO0_CTRL_REG0 0x2204440
+#define ixPB1_PLL_RO0_OVRD_REG0 0x2204450
+#define ixPB1_PLL_RO0_OVRD_REG1 0x2204454
+#define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 0x2204460
+#define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 0x2204464
+#define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 0x2204468
+#define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 0x220446c
+#define ixPB1_PLL_LC0_CTRL_REG0 0x2204480
+#define ixPB1_PLL_LC0_OVRD_REG0 0x2204490
+#define ixPB1_PLL_LC0_OVRD_REG1 0x2204494
+#define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 0x2204500
+#define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 0x2204504
+#define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 0x2204508
+#define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 0x220450c
+#define ixPB1_RX_GLB_CTRL_REG0 0x2206000
+#define ixPB1_RX_GLB_CTRL_REG1 0x2206004
+#define ixPB1_RX_GLB_CTRL_REG2 0x2206008
+#define ixPB1_RX_GLB_CTRL_REG3 0x220600c
+#define ixPB1_RX_GLB_CTRL_REG4 0x2206010
+#define ixPB1_RX_GLB_CTRL_REG5 0x2206014
+#define ixPB1_RX_GLB_CTRL_REG6 0x2206018
+#define ixPB1_RX_GLB_CTRL_REG7 0x220601c
+#define ixPB1_RX_GLB_CTRL_REG8 0x2206020
+#define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 0x2206028
+#define ixPB1_RX_GLB_OVRD_REG0 0x2206030
+#define ixPB1_RX_GLB_OVRD_REG1 0x2206034
+#define ixPB1_RX_LANE0_CTRL_REG0 0x2206440
+#define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 0x2206448
+#define ixPB1_RX_LANE1_CTRL_REG0 0x2206480
+#define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 0x2206488
+#define ixPB1_RX_LANE2_CTRL_REG0 0x2206500
+#define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 0x2206508
+#define ixPB1_RX_LANE3_CTRL_REG0 0x2206600
+#define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 0x2206608
+#define ixPB1_RX_LANE4_CTRL_REG0 0x2206800
+#define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 0x2206848
+#define ixPB1_RX_LANE5_CTRL_REG0 0x2206880
+#define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 0x2206888
+#define ixPB1_RX_LANE6_CTRL_REG0 0x2206900
+#define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 0x2206908
+#define ixPB1_RX_LANE7_CTRL_REG0 0x2206a00
+#define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 0x2206a08
+#define ixPB1_RX_LANE8_CTRL_REG0 0x2207440
+#define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 0x2207448
+#define ixPB1_RX_LANE9_CTRL_REG0 0x2207480
+#define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 0x2207488
+#define ixPB1_RX_LANE10_CTRL_REG0 0x2207500
+#define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 0x2207508
+#define ixPB1_RX_LANE11_CTRL_REG0 0x2207600
+#define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 0x2207608
+#define ixPB1_RX_LANE12_CTRL_REG0 0x2207840
+#define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 0x2207848
+#define ixPB1_RX_LANE13_CTRL_REG0 0x2207880
+#define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 0x2207888
+#define ixPB1_RX_LANE14_CTRL_REG0 0x2207900
+#define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 0x2207908
+#define ixPB1_RX_LANE15_CTRL_REG0 0x2207a00
+#define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 0x2207a08
+#define ixPB1_TX_GLB_CTRL_REG0 0x2208000
+#define ixPB1_TX_GLB_LANE_SKEW_CTRL 0x2208004
+#define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 0x2208010
+#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x2208014
+#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x2208018
+#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x220801c
+#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x2208020
+#define ixPB1_TX_GLB_OVRD_REG0 0x2208030
+#define ixPB1_TX_GLB_OVRD_REG1 0x2208034
+#define ixPB1_TX_GLB_OVRD_REG2 0x2208038
+#define ixPB1_TX_GLB_OVRD_REG3 0x220803c
+#define ixPB1_TX_GLB_OVRD_REG4 0x2208040
+#define ixPB1_TX_LANE0_CTRL_REG0 0x2208440
+#define ixPB1_TX_LANE0_OVRD_REG0 0x2208444
+#define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 0x2208448
+#define ixPB1_TX_LANE1_CTRL_REG0 0x2208480
+#define ixPB1_TX_LANE1_OVRD_REG0 0x2208484
+#define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 0x2208488
+#define ixPB1_TX_LANE2_CTRL_REG0 0x2208500
+#define ixPB1_TX_LANE2_OVRD_REG0 0x2208504
+#define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 0x2208508
+#define ixPB1_TX_LANE3_CTRL_REG0 0x2208600
+#define ixPB1_TX_LANE3_OVRD_REG0 0x2208604
+#define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 0x2208608
+#define ixPB1_TX_LANE4_CTRL_REG0 0x2208840
+#define ixPB1_TX_LANE4_OVRD_REG0 0x2208844
+#define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 0x2208848
+#define ixPB1_TX_LANE5_CTRL_REG0 0x2208880
+#define ixPB1_TX_LANE5_OVRD_REG0 0x2208884
+#define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 0x2208888
+#define ixPB1_TX_LANE6_CTRL_REG0 0x2208900
+#define ixPB1_TX_LANE6_OVRD_REG0 0x2208904
+#define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 0x2208908
+#define ixPB1_TX_LANE7_CTRL_REG0 0x2208a00
+#define ixPB1_TX_LANE7_OVRD_REG0 0x2208a04
+#define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 0x2208a08
+#define ixPB1_TX_LANE8_CTRL_REG0 0x2209440
+#define ixPB1_TX_LANE8_OVRD_REG0 0x2209444
+#define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 0x2209448
+#define ixPB1_TX_LANE9_CTRL_REG0 0x2209480
+#define ixPB1_TX_LANE9_OVRD_REG0 0x2209484
+#define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 0x2209488
+#define ixPB1_TX_LANE10_CTRL_REG0 0x2209500
+#define ixPB1_TX_LANE10_OVRD_REG0 0x2209504
+#define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 0x2209508
+#define ixPB1_TX_LANE11_CTRL_REG0 0x2209600
+#define ixPB1_TX_LANE11_OVRD_REG0 0x2209604
+#define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 0x2209608
+#define ixPB1_TX_LANE12_CTRL_REG0 0x2209840
+#define ixPB1_TX_LANE12_OVRD_REG0 0x2209844
+#define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 0x2209848
+#define ixPB1_TX_LANE13_CTRL_REG0 0x2209880
+#define ixPB1_TX_LANE13_OVRD_REG0 0x2209884
+#define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 0x2209888
+#define ixPB1_TX_LANE14_CTRL_REG0 0x2209900
+#define ixPB1_TX_LANE14_OVRD_REG0 0x2209904
+#define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 0x2209908
+#define ixPB1_TX_LANE15_CTRL_REG0 0x2209a00
+#define ixPB1_TX_LANE15_OVRD_REG0 0x2209a04
+#define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 0x2209a08
+#define ixPB0_PIF_SCRATCH 0x1100001
+#define ixPB0_PIF_HW_DEBUG 0x1100002
+#define ixPB0_PIF_PRG6 0x1100003
+#define ixPB0_PIF_PRG7 0x1100004
+#define ixPB0_PIF_CNTL 0x1100010
+#define ixPB0_PIF_PAIRING 0x1100011
+#define ixPB0_PIF_PWRDOWN_0 0x1100012
+#define ixPB0_PIF_PWRDOWN_1 0x1100013
+#define ixPB0_PIF_CNTL2 0x1100014
+#define ixPB0_PIF_TXPHYSTATUS 0x1100015
+#define ixPB0_PIF_SC_CTL 0x1100016
+#define ixPB0_PIF_PWRDOWN_2 0x1100017
+#define ixPB0_PIF_PWRDOWN_3 0x1100018
+#define ixPB0_PIF_SC_CTL2 0x1100019
+#define ixPB0_PIF_PRG0 0x110001a
+#define ixPB0_PIF_PRG1 0x110001b
+#define ixPB0_PIF_PRG2 0x110001c
+#define ixPB0_PIF_PRG3 0x110001d
+#define ixPB0_PIF_PRG4 0x110001e
+#define ixPB0_PIF_PRG5 0x110001f
+#define ixPB0_PIF_PDNB_OVERRIDE_0 0x1100020
+#define ixPB0_PIF_PDNB_OVERRIDE_1 0x1100021
+#define ixPB0_PIF_PDNB_OVERRIDE_2 0x1100022
+#define ixPB0_PIF_PDNB_OVERRIDE_3 0x1100023
+#define ixPB0_PIF_PDNB_OVERRIDE_4 0x1100024
+#define ixPB0_PIF_PDNB_OVERRIDE_5 0x1100025
+#define ixPB0_PIF_PDNB_OVERRIDE_6 0x1100026
+#define ixPB0_PIF_PDNB_OVERRIDE_7 0x1100027
+#define ixPB0_PIF_SEQ_STATUS_0 0x1100028
+#define ixPB0_PIF_SEQ_STATUS_1 0x1100029
+#define ixPB0_PIF_SEQ_STATUS_2 0x110002a
+#define ixPB0_PIF_SEQ_STATUS_3 0x110002b
+#define ixPB0_PIF_SEQ_STATUS_4 0x110002c
+#define ixPB0_PIF_SEQ_STATUS_5 0x110002d
+#define ixPB0_PIF_SEQ_STATUS_6 0x110002e
+#define ixPB0_PIF_SEQ_STATUS_7 0x110002f
+#define ixPB0_PIF_PDNB_OVERRIDE_8 0x1100030
+#define ixPB0_PIF_PDNB_OVERRIDE_9 0x1100031
+#define ixPB0_PIF_PDNB_OVERRIDE_10 0x1100032
+#define ixPB0_PIF_PDNB_OVERRIDE_11 0x1100033
+#define ixPB0_PIF_PDNB_OVERRIDE_12 0x1100034
+#define ixPB0_PIF_PDNB_OVERRIDE_13 0x1100035
+#define ixPB0_PIF_PDNB_OVERRIDE_14 0x1100036
+#define ixPB0_PIF_PDNB_OVERRIDE_15 0x1100037
+#define ixPB0_PIF_SEQ_STATUS_8 0x1100038
+#define ixPB0_PIF_SEQ_STATUS_9 0x1100039
+#define ixPB0_PIF_SEQ_STATUS_10 0x110003a
+#define ixPB0_PIF_SEQ_STATUS_11 0x110003b
+#define ixPB0_PIF_SEQ_STATUS_12 0x110003c
+#define ixPB0_PIF_SEQ_STATUS_13 0x110003d
+#define ixPB0_PIF_SEQ_STATUS_14 0x110003e
+#define ixPB0_PIF_SEQ_STATUS_15 0x110003f
+#define ixPB1_PIF_SCRATCH 0x2100001
+#define ixPB1_PIF_HW_DEBUG 0x2100002
+#define ixPB1_PIF_PRG6 0x2100003
+#define ixPB1_PIF_PRG7 0x2100004
+#define ixPB1_PIF_CNTL 0x2100010
+#define ixPB1_PIF_PAIRING 0x2100011
+#define ixPB1_PIF_PWRDOWN_0 0x2100012
+#define ixPB1_PIF_PWRDOWN_1 0x2100013
+#define ixPB1_PIF_CNTL2 0x2100014
+#define ixPB1_PIF_TXPHYSTATUS 0x2100015
+#define ixPB1_PIF_SC_CTL 0x2100016
+#define ixPB1_PIF_PWRDOWN_2 0x2100017
+#define ixPB1_PIF_PWRDOWN_3 0x2100018
+#define ixPB1_PIF_SC_CTL2 0x2100019
+#define ixPB1_PIF_PRG0 0x210001a
+#define ixPB1_PIF_PRG1 0x210001b
+#define ixPB1_PIF_PRG2 0x210001c
+#define ixPB1_PIF_PRG3 0x210001d
+#define ixPB1_PIF_PRG4 0x210001e
+#define ixPB1_PIF_PRG5 0x210001f
+#define ixPB1_PIF_PDNB_OVERRIDE_0 0x2100020
+#define ixPB1_PIF_PDNB_OVERRIDE_1 0x2100021
+#define ixPB1_PIF_PDNB_OVERRIDE_2 0x2100022
+#define ixPB1_PIF_PDNB_OVERRIDE_3 0x2100023
+#define ixPB1_PIF_PDNB_OVERRIDE_4 0x2100024
+#define ixPB1_PIF_PDNB_OVERRIDE_5 0x2100025
+#define ixPB1_PIF_PDNB_OVERRIDE_6 0x2100026
+#define ixPB1_PIF_PDNB_OVERRIDE_7 0x2100027
+#define ixPB1_PIF_SEQ_STATUS_0 0x2100028
+#define ixPB1_PIF_SEQ_STATUS_1 0x2100029
+#define ixPB1_PIF_SEQ_STATUS_2 0x210002a
+#define ixPB1_PIF_SEQ_STATUS_3 0x210002b
+#define ixPB1_PIF_SEQ_STATUS_4 0x210002c
+#define ixPB1_PIF_SEQ_STATUS_5 0x210002d
+#define ixPB1_PIF_SEQ_STATUS_6 0x210002e
+#define ixPB1_PIF_SEQ_STATUS_7 0x210002f
+#define ixPB1_PIF_PDNB_OVERRIDE_8 0x2100030
+#define ixPB1_PIF_PDNB_OVERRIDE_9 0x2100031
+#define ixPB1_PIF_PDNB_OVERRIDE_10 0x2100032
+#define ixPB1_PIF_PDNB_OVERRIDE_11 0x2100033
+#define ixPB1_PIF_PDNB_OVERRIDE_12 0x2100034
+#define ixPB1_PIF_PDNB_OVERRIDE_13 0x2100035
+#define ixPB1_PIF_PDNB_OVERRIDE_14 0x2100036
+#define ixPB1_PIF_PDNB_OVERRIDE_15 0x2100037
+#define ixPB1_PIF_SEQ_STATUS_8 0x2100038
+#define ixPB1_PIF_SEQ_STATUS_9 0x2100039
+#define ixPB1_PIF_SEQ_STATUS_10 0x210003a
+#define ixPB1_PIF_SEQ_STATUS_11 0x210003b
+#define ixPB1_PIF_SEQ_STATUS_12 0x210003c
+#define ixPB1_PIF_SEQ_STATUS_13 0x210003d
+#define ixPB1_PIF_SEQ_STATUS_14 0x210003e
+#define ixPB1_PIF_SEQ_STATUS_15 0x210003f
+#define mmBIF_RFE_SNOOP_REG 0x27
+#define mmBIF_RFE_WARMRST_CNTL 0x1459
+#define mmBIF_RFE_SOFTRST_CNTL 0x1441
+#define mmBIF_RFE_IMPRST_CNTL 0x1458
+#define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER 0x1442
+#define mmBIF_RFE_MASTER_SOFTRST_TRIGGER 0x1443
+#define mmBIF_PWDN_COMMAND 0x1444
+#define mmBIF_PWDN_STATUS 0x1445
+#define mmBIF_RFE_MST_BU_CMDSTATUS 0x1446
+#define mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS 0x1447
+#define mmBIF_RFE_MST_BX_CMDSTATUS 0x1448
+#define mmBIF_RFE_MST_TMOUT_STATUS 0x144b
+#define mmBIF_RFE_MMCFG_CNTL 0x144c
+#define mmBIF_CC_RFE_IMP_OVERRIDECNTL 0x1455
+#define mmBIF_IMPCTL_SMPLCNTL 0x1450
+#define mmBIF_IMPCTL_RXCNTL 0x1451
+#define mmBIF_IMPCTL_TXCNTL_pd 0x1452
+#define mmBIF_IMPCTL_TXCNTL_pu 0x1453
+#define mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD 0x1454
+#define mmBIF_CLOCKS_BITS 0x1489
+#define mmBIF_LNCNT_RESET 0x1488
+#define mmLNCNT_CONTROL 0x1487
+#define mmNEW_REFCLKB_TIMER 0x1485
+#define mmNEW_REFCLKB_TIMER_1 0x1484
+#define mmBIF_CLK_PDWN_DELAY_TIMER 0x1483
+#define mmBIF_RESET_EN 0x1482
+#define mmBIF_PIF_TXCLK_SWITCH_TIMER 0x1481
+#define mmBIF_BACO_MSIC 0x1480
+#define mmBIF_RESET_CNTL 0x1486
+#define mmBIF_RFE_CNTL_MISC 0x148c
+
+#endif /* BIF_4_1_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h
new file mode 100644
index 000000000000..8fbfd0261d27
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h
@@ -0,0 +1,10250 @@
+/*
+ * BIF_4_1 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef BIF_4_1_SH_MASK_H
+#define BIF_4_1_SH_MASK_H
+
+#define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
+#define MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define MM_INDEX__MM_APER_MASK 0x80000000
+#define MM_INDEX__MM_APER__SHIFT 0x1f
+#define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
+#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define MM_DATA__MM_DATA_MASK 0xffffffff
+#define MM_DATA__MM_DATA__SHIFT 0x0
+#define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x1
+#define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x0
+#define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2
+#define BUS_CNTL__BIOS_ROM_DIS__SHIFT 0x1
+#define BUS_CNTL__PMI_IO_DIS_MASK 0x4
+#define BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
+#define BUS_CNTL__PMI_MEM_DIS_MASK 0x8
+#define BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
+#define BUS_CNTL__PMI_BM_DIS_MASK 0x10
+#define BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
+#define BUS_CNTL__PMI_INT_DIS_MASK 0x20
+#define BUS_CNTL__PMI_INT_DIS__SHIFT 0x5
+#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x40
+#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6
+#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x80
+#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
+#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100
+#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8
+#define BUS_CNTL__SET_AZ_TC_MASK 0x1c00
+#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa
+#define BUS_CNTL__SET_MC_TC_MASK 0xe000
+#define BUS_CNTL__SET_MC_TC__SHIFT 0xd
+#define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x10000
+#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
+#define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x20000
+#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11
+#define BUS_CNTL__RD_STALL_IO_WR_MASK 0x40000
+#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12
+#define CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x1
+#define CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0
+#define CONFIG_CNTL__VGA_DIS_MASK 0x2
+#define CONFIG_CNTL__VGA_DIS__SHIFT 0x1
+#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x4
+#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2
+#define CONFIG_CNTL__GRPH_ADRSEL_MASK 0x18
+#define CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3
+#define CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xffffffff
+#define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define CONFIG_F0_BASE__F0_BASE_MASK 0xffffffff
+#define CONFIG_F0_BASE__F0_BASE__SHIFT 0x0
+#define CONFIG_APER_SIZE__APER_SIZE_MASK 0xffffffff
+#define CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0
+#define CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0xfffff
+#define CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0
+#define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xffffffff
+#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0
+#define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xffffffff
+#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0
+#define BX_RESET_EN__COR_RESET_EN_MASK 0x1
+#define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0
+#define BX_RESET_EN__REG_RESET_EN_MASK 0x2
+#define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1
+#define BX_RESET_EN__STY_RESET_EN_MASK 0x4
+#define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2
+#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x7
+#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0
+#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x8
+#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x3
+#define HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define HW_DEBUG__HW_16_DEBUG_MASK 0x10000
+#define HW_DEBUG__HW_16_DEBUG__SHIFT 0x10
+#define HW_DEBUG__HW_17_DEBUG_MASK 0x20000
+#define HW_DEBUG__HW_17_DEBUG__SHIFT 0x11
+#define HW_DEBUG__HW_18_DEBUG_MASK 0x40000
+#define HW_DEBUG__HW_18_DEBUG__SHIFT 0x12
+#define HW_DEBUG__HW_19_DEBUG_MASK 0x80000
+#define HW_DEBUG__HW_19_DEBUG__SHIFT 0x13
+#define HW_DEBUG__HW_20_DEBUG_MASK 0x100000
+#define HW_DEBUG__HW_20_DEBUG__SHIFT 0x14
+#define HW_DEBUG__HW_21_DEBUG_MASK 0x200000
+#define HW_DEBUG__HW_21_DEBUG__SHIFT 0x15
+#define HW_DEBUG__HW_22_DEBUG_MASK 0x400000
+#define HW_DEBUG__HW_22_DEBUG__SHIFT 0x16
+#define HW_DEBUG__HW_23_DEBUG_MASK 0x800000
+#define HW_DEBUG__HW_23_DEBUG__SHIFT 0x17
+#define HW_DEBUG__HW_24_DEBUG_MASK 0x1000000
+#define HW_DEBUG__HW_24_DEBUG__SHIFT 0x18
+#define HW_DEBUG__HW_25_DEBUG_MASK 0x2000000
+#define HW_DEBUG__HW_25_DEBUG__SHIFT 0x19
+#define HW_DEBUG__HW_26_DEBUG_MASK 0x4000000
+#define HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a
+#define HW_DEBUG__HW_27_DEBUG_MASK 0x8000000
+#define HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b
+#define HW_DEBUG__HW_28_DEBUG_MASK 0x10000000
+#define HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c
+#define HW_DEBUG__HW_29_DEBUG_MASK 0x20000000
+#define HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d
+#define HW_DEBUG__HW_30_DEBUG_MASK 0x40000000
+#define HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e
+#define HW_DEBUG__HW_31_DEBUG_MASK 0x80000000
+#define HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f
+#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT_MASK 0x7f
+#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT__SHIFT 0x0
+#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT_MASK 0x3f0000
+#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT__SHIFT 0x10
+#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT_MASK 0x1f
+#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT__SHIFT 0x0
+#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT_MASK 0x1e0
+#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT__SHIFT 0x5
+#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT_MASK 0x7c00
+#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT__SHIFT 0xa
+#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT_MASK 0x8000
+#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT__SHIFT 0xf
+#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT_MASK 0x100000
+#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT__SHIFT 0x14
+#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT_MASK 0x7e000000
+#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT__SHIFT 0x19
+#define BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x1
+#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0
+#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x1
+#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
+#define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x2
+#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1
+#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x8
+#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3
+#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0xf0
+#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
+#define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x100
+#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8
+#define INTERRUPT_CNTL__GEN_GPIO_INT_EN_MASK 0x1e00
+#define INTERRUPT_CNTL__GEN_GPIO_INT_EN__SHIFT 0x9
+#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT_MASK 0x6000
+#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT__SHIFT 0xd
+#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xffffffff
+#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0
+#define BIF_DEBUG_CNTL__DEBUG_EN_MASK 0x1
+#define BIF_DEBUG_CNTL__DEBUG_EN__SHIFT 0x0
+#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x2
+#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN__SHIFT 0x1
+#define BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK 0x4
+#define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x2
+#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x8
+#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL__SHIFT 0x3
+#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1_MASK 0x10
+#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT 0x4
+#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2_MASK 0x20
+#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2__SHIFT 0x5
+#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN_MASK 0x40
+#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN__SHIFT 0x6
+#define BIF_DEBUG_CNTL__DEBUG_SWAP_MASK 0x80
+#define BIF_DEBUG_CNTL__DEBUG_SWAP__SHIFT 0x7
+#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1_MASK 0x1f00
+#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x8
+#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2_MASK 0x1f0000
+#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2__SHIFT 0x10
+#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP_MASK 0x1000000
+#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP__SHIFT 0x18
+#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL_MASK 0xc0000000
+#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL__SHIFT 0x1e
+#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1_MASK 0x3f
+#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1__SHIFT 0x0
+#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2_MASK 0x3f00
+#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT 0x8
+#define BIF_DEBUG_OUT__DEBUG_OUTPUT_MASK 0x1ffff
+#define BIF_DEBUG_OUT__DEBUG_OUTPUT__SHIFT 0x0
+#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x1
+#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x1
+#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x1
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x2
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x4
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x18
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x20
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x40
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x80
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x100
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x200
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x400
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x800
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x1000
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
+#define SMBUS_SLV_CNTL__SMB_SOFT_RESET_MASK 0x1
+#define SMBUS_SLV_CNTL__SMB_SOFT_RESET__SHIFT 0x0
+#define SMBUS_SLV_CNTL__SMB_SLV_ADR_MASK 0xfe
+#define SMBUS_SLV_CNTL__SMB_SLV_ADR__SHIFT 0x1
+#define SMBUS_SLV_CNTL1__SMB_TIMEOUT_THRESHOLD_MASK 0x3fffff
+#define SMBUS_SLV_CNTL1__SMB_TIMEOUT_THRESHOLD__SHIFT 0x0
+#define SMBUS_SLV_CNTL1__SMB_XTALIN_FREQUENCY_SEL_MASK 0x1000000
+#define SMBUS_SLV_CNTL1__SMB_XTALIN_FREQUENCY_SEL__SHIFT 0x18
+#define SMBUS_SLV_CNTL1__SMB_TIMEOUT_DIS_MASK 0x2000000
+#define SMBUS_SLV_CNTL1__SMB_TIMEOUT_DIS__SHIFT 0x19
+#define SMBUS_SLV_CNTL1__SMB_DAT_HOLD_TIME_MARGIN_MASK 0xfc000000
+#define SMBUS_SLV_CNTL1__SMB_DAT_HOLD_TIME_MARGIN__SHIFT 0x1a
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A_MASK 0x1
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A__SHIFT 0x0
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL_MASK 0x2
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL__SHIFT 0x1
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE_MASK 0x4
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE__SHIFT 0x2
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE_MASK 0x18
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE__SHIFT 0x3
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0_MASK 0x20
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0__SHIFT 0x5
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1_MASK 0x40
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1__SHIFT 0x6
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2_MASK 0x80
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2__SHIFT 0x7
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3_MASK 0x100
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3__SHIFT 0x8
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN_MASK 0x200
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN__SHIFT 0x9
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE_MASK 0x400
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE__SHIFT 0xa
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN_MASK 0x800
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN__SHIFT 0xb
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN_MASK 0x1000
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN__SHIFT 0xc
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A_MASK 0x1
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A__SHIFT 0x0
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL_MASK 0x2
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL__SHIFT 0x1
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE_MASK 0x4
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE__SHIFT 0x2
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE_MASK 0x18
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE__SHIFT 0x3
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0_MASK 0x20
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0__SHIFT 0x5
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1_MASK 0x40
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1__SHIFT 0x6
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2_MASK 0x80
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2__SHIFT 0x7
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3_MASK 0x100
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3__SHIFT 0x8
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN_MASK 0x200
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN__SHIFT 0x9
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE_MASK 0x400
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE__SHIFT 0xa
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN_MASK 0x800
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN__SHIFT 0xb
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN_MASK 0x1000
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN__SHIFT 0xc
+#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffff
+#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0
+#define BIF_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000
+#define BIF_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f
+#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffff
+#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0
+#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x1
+#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0
+#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x2
+#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
+#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x4
+#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
+#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x8
+#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3
+#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x10
+#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4
+#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x20
+#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5
+#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x40
+#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6
+#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x80
+#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x7
+#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x100
+#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x8
+#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS_MASK 0x200
+#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9
+#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS_MASK 0x400
+#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa
+#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x800
+#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb
+#define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x1
+#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0
+#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x2
+#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1
+#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x4
+#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
+#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x8
+#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
+#define BIF_SLVARB_MODE__SLVARB_MODE_MASK 0x3
+#define BIF_SLVARB_MODE__SLVARB_MODE__SHIFT 0x0
+#define BIF_FB_EN__FB_READ_EN_MASK 0x1
+#define BIF_FB_EN__FB_READ_EN__SHIFT 0x0
+#define BIF_FB_EN__FB_WRITE_EN_MASK 0x2
+#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
+#define BIF_BUSNUM_CNTL1__ID_MASK_MASK 0xff
+#define BIF_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0
+#define BIF_BUSNUM_LIST0__ID0_MASK 0xff
+#define BIF_BUSNUM_LIST0__ID0__SHIFT 0x0
+#define BIF_BUSNUM_LIST0__ID1_MASK 0xff00
+#define BIF_BUSNUM_LIST0__ID1__SHIFT 0x8
+#define BIF_BUSNUM_LIST0__ID2_MASK 0xff0000
+#define BIF_BUSNUM_LIST0__ID2__SHIFT 0x10
+#define BIF_BUSNUM_LIST0__ID3_MASK 0xff000000
+#define BIF_BUSNUM_LIST0__ID3__SHIFT 0x18
+#define BIF_BUSNUM_LIST1__ID4_MASK 0xff
+#define BIF_BUSNUM_LIST1__ID4__SHIFT 0x0
+#define BIF_BUSNUM_LIST1__ID5_MASK 0xff00
+#define BIF_BUSNUM_LIST1__ID5__SHIFT 0x8
+#define BIF_BUSNUM_LIST1__ID6_MASK 0xff0000
+#define BIF_BUSNUM_LIST1__ID6__SHIFT 0x10
+#define BIF_BUSNUM_LIST1__ID7_MASK 0xff000000
+#define BIF_BUSNUM_LIST1__ID7__SHIFT 0x18
+#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0xff
+#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0
+#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x100
+#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8
+#define BIF_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x10000
+#define BIF_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10
+#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x20000
+#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11
+#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x3f
+#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0
+#define BIF_PERFMON_CNTL__PERFCOUNTER_EN_MASK 0x1
+#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x0
+#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK 0x2
+#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x1
+#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1_MASK 0x4
+#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2
+#define BIF_PERFMON_CNTL__PERF_SEL0_MASK 0x1f00
+#define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x8
+#define BIF_PERFMON_CNTL__PERF_SEL1_MASK 0x3e000
+#define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0xd
+#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff
+#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0
+#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff
+#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0
+#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL_MASK 0xe
+#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL__SHIFT 0x1
+#define GPU_HDP_FLUSH_REQ__CP0_MASK 0x1
+#define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define GPU_HDP_FLUSH_REQ__CP1_MASK 0x2
+#define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define GPU_HDP_FLUSH_REQ__CP2_MASK 0x4
+#define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define GPU_HDP_FLUSH_REQ__CP3_MASK 0x8
+#define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define GPU_HDP_FLUSH_REQ__CP4_MASK 0x10
+#define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define GPU_HDP_FLUSH_REQ__CP5_MASK 0x20
+#define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define GPU_HDP_FLUSH_REQ__CP6_MASK 0x40
+#define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define GPU_HDP_FLUSH_REQ__CP7_MASK 0x80
+#define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define GPU_HDP_FLUSH_REQ__CP8_MASK 0x100
+#define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define GPU_HDP_FLUSH_REQ__CP9_MASK 0x200
+#define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x400
+#define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x800
+#define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define GPU_HDP_FLUSH_DONE__CP0_MASK 0x1
+#define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define GPU_HDP_FLUSH_DONE__CP1_MASK 0x2
+#define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define GPU_HDP_FLUSH_DONE__CP2_MASK 0x4
+#define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define GPU_HDP_FLUSH_DONE__CP3_MASK 0x8
+#define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define GPU_HDP_FLUSH_DONE__CP4_MASK 0x10
+#define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define GPU_HDP_FLUSH_DONE__CP5_MASK 0x20
+#define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define GPU_HDP_FLUSH_DONE__CP6_MASK 0x40
+#define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define GPU_HDP_FLUSH_DONE__CP7_MASK 0x80
+#define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define GPU_HDP_FLUSH_DONE__CP8_MASK 0x100
+#define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define GPU_HDP_FLUSH_DONE__CP9_MASK 0x200
+#define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x400
+#define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x800
+#define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR_MASK 0x1
+#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR__SHIFT 0x0
+#define SLAVE_HANG_ERROR__HDP_HANG_ERROR_MASK 0x2
+#define SLAVE_HANG_ERROR__HDP_HANG_ERROR__SHIFT 0x1
+#define SLAVE_HANG_ERROR__VGA_HANG_ERROR_MASK 0x4
+#define SLAVE_HANG_ERROR__VGA_HANG_ERROR__SHIFT 0x2
+#define SLAVE_HANG_ERROR__ROM_HANG_ERROR_MASK 0x8
+#define SLAVE_HANG_ERROR__ROM_HANG_ERROR__SHIFT 0x3
+#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR_MASK 0x10
+#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR__SHIFT 0x4
+#define SLAVE_HANG_ERROR__CEC_HANG_ERROR_MASK 0x20
+#define SLAVE_HANG_ERROR__CEC_HANG_ERROR__SHIFT 0x5
+#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR_MASK 0x80
+#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR__SHIFT 0x7
+#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR_MASK 0x100
+#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR__SHIFT 0x8
+#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR_MASK 0x200
+#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR__SHIFT 0x9
+#define CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x1
+#define CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0
+#define HOST_BUSNUM__HOST_ID_MASK 0xffff
+#define HOST_BUSNUM__HOST_ID__SHIFT 0x0
+#define PEER_REG_RANGE0__START_ADDR_MASK 0xffff
+#define PEER_REG_RANGE0__START_ADDR__SHIFT 0x0
+#define PEER_REG_RANGE0__END_ADDR_MASK 0xffff0000
+#define PEER_REG_RANGE0__END_ADDR__SHIFT 0x10
+#define PEER_REG_RANGE1__START_ADDR_MASK 0xffff
+#define PEER_REG_RANGE1__START_ADDR__SHIFT 0x0
+#define PEER_REG_RANGE1__END_ADDR_MASK 0xffff0000
+#define PEER_REG_RANGE1__END_ADDR__SHIFT 0x10
+#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0xfffff
+#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0
+#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0xfffff
+#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0
+#define PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000
+#define PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f
+#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0xfffff
+#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0
+#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0xfffff
+#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0
+#define PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000
+#define PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f
+#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0xfffff
+#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0
+#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0xfffff
+#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0
+#define PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000
+#define PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f
+#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0xfffff
+#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0
+#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0xfffff
+#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0
+#define PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000
+#define PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f
+#define DBG_BYPASS_SRBM_ACCESS__DBG_BYPASS_SRBM_ACCESS_EN_MASK 0x1
+#define DBG_BYPASS_SRBM_ACCESS__DBG_BYPASS_SRBM_ACCESS_EN__SHIFT 0x0
+#define DBG_BYPASS_SRBM_ACCESS__DBG_APER_AD_MASK 0x1e
+#define DBG_BYPASS_SRBM_ACCESS__DBG_APER_AD__SHIFT 0x1
+#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA_MASK 0xffffffff
+#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA__SHIFT 0x0
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0xff
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0xff00
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0xff0000
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xff000000
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0xff
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0xff00
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0xff0000
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xff000000
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18
+#define BACO_CNTL__BACO_EN_MASK 0x1
+#define BACO_CNTL__BACO_EN__SHIFT 0x0
+#define BACO_CNTL__BACO_BCLK_OFF_MASK 0x2
+#define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x1
+#define BACO_CNTL__BACO_ISO_DIS_MASK 0x4
+#define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x2
+#define BACO_CNTL__BACO_POWER_OFF_MASK 0x8
+#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3
+#define BACO_CNTL__BACO_RESET_EN_MASK 0x10
+#define BACO_CNTL__BACO_RESET_EN__SHIFT 0x4
+#define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x20
+#define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x5
+#define BACO_CNTL__BACO_MODE_MASK 0x40
+#define BACO_CNTL__BACO_MODE__SHIFT 0x6
+#define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x80
+#define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x7
+#define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x100
+#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x8
+#define BACO_CNTL__PWRGOOD_BF_MASK 0x200
+#define BACO_CNTL__PWRGOOD_BF__SHIFT 0x9
+#define BACO_CNTL__PWRGOOD_GPIO_MASK 0x400
+#define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0xa
+#define BACO_CNTL__PWRGOOD_MEM_MASK 0x800
+#define BACO_CNTL__PWRGOOD_MEM__SHIFT 0xb
+#define BACO_CNTL__PWRGOOD_DVO_MASK 0x1000
+#define BACO_CNTL__PWRGOOD_DVO__SHIFT 0xc
+#define BACO_CNTL__PWRGOOD_IDSC_MASK 0x2000
+#define BACO_CNTL__PWRGOOD_IDSC__SHIFT 0xd
+#define BACO_CNTL__BACO_POWER_OFF_DRAM_MASK 0x10000
+#define BACO_CNTL__BACO_POWER_OFF_DRAM__SHIFT 0x10
+#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL_MASK 0x20000
+#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL__SHIFT 0x11
+#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK_MASK 0x1
+#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK__SHIFT 0x0
+#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK 0x2
+#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK__SHIFT 0x1
+#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x1
+#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0
+#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG_MASK 0x1
+#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG__SHIFT 0x0
+#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG_MASK 0x1
+#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG__SHIFT 0x0
+#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x1
+#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0
+#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x2
+#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1
+#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL_MASK 0xc
+#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2
+#define BIF_SSA_PWR_STATUS__SSA_GFX_PWR_STATUS_MASK 0x1
+#define BIF_SSA_PWR_STATUS__SSA_GFX_PWR_STATUS__SHIFT 0x0
+#define BIF_SSA_PWR_STATUS__SSA_DISP_PWR_STATUS_MASK 0x2
+#define BIF_SSA_PWR_STATUS__SSA_DISP_PWR_STATUS__SHIFT 0x1
+#define BIF_SSA_PWR_STATUS__SSA_MC_PWR_STATUS_MASK 0x4
+#define BIF_SSA_PWR_STATUS__SSA_MC_PWR_STATUS__SHIFT 0x2
+#define BIF_SSA_GFX0_LOWER__SSA_GFX0_LOWER_MASK 0x3fffc
+#define BIF_SSA_GFX0_LOWER__SSA_GFX0_LOWER__SHIFT 0x2
+#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_CMP_EN_MASK 0x40000000
+#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_CMP_EN__SHIFT 0x1e
+#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_STALL_EN_MASK 0x80000000
+#define BIF_SSA_GFX0_LOWER__SSA_GFX0_REG_STALL_EN__SHIFT 0x1f
+#define BIF_SSA_GFX0_UPPER__SSA_GFX0_UPPER_MASK 0x3fffc
+#define BIF_SSA_GFX0_UPPER__SSA_GFX0_UPPER__SHIFT 0x2
+#define BIF_SSA_GFX1_LOWER__SSA_GFX1_LOWER_MASK 0x3fffc
+#define BIF_SSA_GFX1_LOWER__SSA_GFX1_LOWER__SHIFT 0x2
+#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_CMP_EN_MASK 0x40000000
+#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_CMP_EN__SHIFT 0x1e
+#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_STALL_EN_MASK 0x80000000
+#define BIF_SSA_GFX1_LOWER__SSA_GFX1_REG_STALL_EN__SHIFT 0x1f
+#define BIF_SSA_GFX1_UPPER__SSA_GFX1_UPPER_MASK 0x3fffc
+#define BIF_SSA_GFX1_UPPER__SSA_GFX1_UPPER__SHIFT 0x2
+#define BIF_SSA_GFX2_LOWER__SSA_GFX2_LOWER_MASK 0x3fffc
+#define BIF_SSA_GFX2_LOWER__SSA_GFX2_LOWER__SHIFT 0x2
+#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_CMP_EN_MASK 0x40000000
+#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_CMP_EN__SHIFT 0x1e
+#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_STALL_EN_MASK 0x80000000
+#define BIF_SSA_GFX2_LOWER__SSA_GFX2_REG_STALL_EN__SHIFT 0x1f
+#define BIF_SSA_GFX2_UPPER__SSA_GFX2_UPPER_MASK 0x3fffc
+#define BIF_SSA_GFX2_UPPER__SSA_GFX2_UPPER__SHIFT 0x2
+#define BIF_SSA_GFX3_LOWER__SSA_GFX3_LOWER_MASK 0x3fffc
+#define BIF_SSA_GFX3_LOWER__SSA_GFX3_LOWER__SHIFT 0x2
+#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_CMP_EN_MASK 0x40000000
+#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_CMP_EN__SHIFT 0x1e
+#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_STALL_EN_MASK 0x80000000
+#define BIF_SSA_GFX3_LOWER__SSA_GFX3_REG_STALL_EN__SHIFT 0x1f
+#define BIF_SSA_GFX3_UPPER__SSA_GFX3_UPPER_MASK 0x3fffc
+#define BIF_SSA_GFX3_UPPER__SSA_GFX3_UPPER__SHIFT 0x2
+#define BIF_SSA_DISP_LOWER__SSA_DISP_LOWER_MASK 0x3fffc
+#define BIF_SSA_DISP_LOWER__SSA_DISP_LOWER__SHIFT 0x2
+#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_CMP_EN_MASK 0x40000000
+#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_CMP_EN__SHIFT 0x1e
+#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_STALL_EN_MASK 0x80000000
+#define BIF_SSA_DISP_LOWER__SSA_DISP_REG_STALL_EN__SHIFT 0x1f
+#define BIF_SSA_DISP_UPPER__SSA_DISP_UPPER_MASK 0x3fffc
+#define BIF_SSA_DISP_UPPER__SSA_DISP_UPPER__SHIFT 0x2
+#define BIF_SSA_MC_LOWER__SSA_MC_LOWER_MASK 0x3fffc
+#define BIF_SSA_MC_LOWER__SSA_MC_LOWER__SHIFT 0x2
+#define BIF_SSA_MC_LOWER__SSA_MC_FB_STALL_EN_MASK 0x20000000
+#define BIF_SSA_MC_LOWER__SSA_MC_FB_STALL_EN__SHIFT 0x1d
+#define BIF_SSA_MC_LOWER__SSA_MC_REG_CMP_EN_MASK 0x40000000
+#define BIF_SSA_MC_LOWER__SSA_MC_REG_CMP_EN__SHIFT 0x1e
+#define BIF_SSA_MC_LOWER__SSA_MC_REG_STALL_EN_MASK 0x80000000
+#define BIF_SSA_MC_LOWER__SSA_MC_REG_STALL_EN__SHIFT 0x1f
+#define BIF_SSA_MC_UPPER__SSA_MC_UPPER_MASK 0x3fffc
+#define BIF_SSA_MC_UPPER__SSA_MC_UPPER__SHIFT 0x2
+#define IMPCTL_RESET__IMP_SW_RESET_MASK 0x1
+#define IMPCTL_RESET__IMP_SW_RESET__SHIFT 0x0
+#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR_MASK 0x1
+#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR__SHIFT 0x0
+#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR_MASK 0x2
+#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR__SHIFT 0x1
+#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR_MASK 0x4
+#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR__SHIFT 0x2
+#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR_MASK 0x8
+#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR__SHIFT 0x3
+#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR_MASK 0x10
+#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR__SHIFT 0x4
+#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR_MASK 0x20
+#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR__SHIFT 0x5
+#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND_MASK 0x40
+#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND__SHIFT 0x6
+#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND_MASK 0x80
+#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND__SHIFT 0x7
+#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR_MASK 0x100
+#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR__SHIFT 0x8
+#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR_MASK 0x200
+#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR__SHIFT 0x9
+#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR_MASK 0x400
+#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR__SHIFT 0xa
+#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2_MASK 0x800
+#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2__SHIFT 0xb
+#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR_MASK 0x1000
+#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR__SHIFT 0xc
+#define GARLIC_FLUSH_CNTL__HOST_DOORBELL_MASK 0x2000
+#define GARLIC_FLUSH_CNTL__HOST_DOORBELL__SHIFT 0xd
+#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL_MASK 0x4000
+#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL__SHIFT 0xe
+#define GARLIC_FLUSH_CNTL__DISPLAY_MASK 0x10000
+#define GARLIC_FLUSH_CNTL__DISPLAY__SHIFT 0x10
+#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE_MASK 0x40000000
+#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE__SHIFT 0x1e
+#define GARLIC_FLUSH_CNTL__DISABLE_ALL_MASK 0x80000000
+#define GARLIC_FLUSH_CNTL__DISABLE_ALL__SHIFT 0x1f
+#define GARLIC_FLUSH_ADDR_START_0__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_0__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_0__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_0__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_0__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_0__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_START_1__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_1__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_1__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_1__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_1__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_1__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_START_2__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_2__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_2__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_2__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_2__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_2__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_START_3__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_3__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_3__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_3__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_3__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_3__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_START_4__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_4__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_4__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_4__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_4__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_4__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_START_5__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_5__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_5__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_5__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_5__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_5__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_START_6__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_6__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_6__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_6__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_6__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_6__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_START_7__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_7__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_7__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_7__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_7__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_7__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_0__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_0__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_1__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_1__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_2__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_2__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_3__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_3__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_4__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_4__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_5__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_5__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_6__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_6__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_7__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_7__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_REQ__FLUSH_REQ_MASK 0x1
+#define GARLIC_FLUSH_REQ__FLUSH_REQ__SHIFT 0x0
+#define GPU_GARLIC_FLUSH_REQ__CP0_MASK 0x1
+#define GPU_GARLIC_FLUSH_REQ__CP0__SHIFT 0x0
+#define GPU_GARLIC_FLUSH_REQ__CP1_MASK 0x2
+#define GPU_GARLIC_FLUSH_REQ__CP1__SHIFT 0x1
+#define GPU_GARLIC_FLUSH_REQ__CP2_MASK 0x4
+#define GPU_GARLIC_FLUSH_REQ__CP2__SHIFT 0x2
+#define GPU_GARLIC_FLUSH_REQ__CP3_MASK 0x8
+#define GPU_GARLIC_FLUSH_REQ__CP3__SHIFT 0x3
+#define GPU_GARLIC_FLUSH_REQ__CP4_MASK 0x10
+#define GPU_GARLIC_FLUSH_REQ__CP4__SHIFT 0x4
+#define GPU_GARLIC_FLUSH_REQ__CP5_MASK 0x20
+#define GPU_GARLIC_FLUSH_REQ__CP5__SHIFT 0x5
+#define GPU_GARLIC_FLUSH_REQ__CP6_MASK 0x40
+#define GPU_GARLIC_FLUSH_REQ__CP6__SHIFT 0x6
+#define GPU_GARLIC_FLUSH_REQ__CP7_MASK 0x80
+#define GPU_GARLIC_FLUSH_REQ__CP7__SHIFT 0x7
+#define GPU_GARLIC_FLUSH_REQ__CP8_MASK 0x100
+#define GPU_GARLIC_FLUSH_REQ__CP8__SHIFT 0x8
+#define GPU_GARLIC_FLUSH_REQ__CP9_MASK 0x200
+#define GPU_GARLIC_FLUSH_REQ__CP9__SHIFT 0x9
+#define GPU_GARLIC_FLUSH_REQ__SDMA0_MASK 0x400
+#define GPU_GARLIC_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define GPU_GARLIC_FLUSH_REQ__SDMA1_MASK 0x800
+#define GPU_GARLIC_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define GPU_GARLIC_FLUSH_DONE__CP0_MASK 0x1
+#define GPU_GARLIC_FLUSH_DONE__CP0__SHIFT 0x0
+#define GPU_GARLIC_FLUSH_DONE__CP1_MASK 0x2
+#define GPU_GARLIC_FLUSH_DONE__CP1__SHIFT 0x1
+#define GPU_GARLIC_FLUSH_DONE__CP2_MASK 0x4
+#define GPU_GARLIC_FLUSH_DONE__CP2__SHIFT 0x2
+#define GPU_GARLIC_FLUSH_DONE__CP3_MASK 0x8
+#define GPU_GARLIC_FLUSH_DONE__CP3__SHIFT 0x3
+#define GPU_GARLIC_FLUSH_DONE__CP4_MASK 0x10
+#define GPU_GARLIC_FLUSH_DONE__CP4__SHIFT 0x4
+#define GPU_GARLIC_FLUSH_DONE__CP5_MASK 0x20
+#define GPU_GARLIC_FLUSH_DONE__CP5__SHIFT 0x5
+#define GPU_GARLIC_FLUSH_DONE__CP6_MASK 0x40
+#define GPU_GARLIC_FLUSH_DONE__CP6__SHIFT 0x6
+#define GPU_GARLIC_FLUSH_DONE__CP7_MASK 0x80
+#define GPU_GARLIC_FLUSH_DONE__CP7__SHIFT 0x7
+#define GPU_GARLIC_FLUSH_DONE__CP8_MASK 0x100
+#define GPU_GARLIC_FLUSH_DONE__CP8__SHIFT 0x8
+#define GPU_GARLIC_FLUSH_DONE__CP9_MASK 0x200
+#define GPU_GARLIC_FLUSH_DONE__CP9__SHIFT 0x9
+#define GPU_GARLIC_FLUSH_DONE__SDMA0_MASK 0x400
+#define GPU_GARLIC_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define GPU_GARLIC_FLUSH_DONE__SDMA1_MASK 0x800
+#define GPU_GARLIC_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define GARLIC_COHE_CP_RB0_WPTR__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_CP_RB0_WPTR__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_CP_RB1_WPTR__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_CP_RB1_WPTR__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_CP_RB2_WPTR__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_CP_RB2_WPTR__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_VCE_RB_WPTR2__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_VCE_RB_WPTR2__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_VCE_RB_WPTR__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_VCE_RB_WPTR__ADDRESS__SHIFT 0x2
+#define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xffffffff
+#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0
+#define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xffffffff
+#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0
+#define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xffffffff
+#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0
+#define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xffffffff
+#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0
+#define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xffffffff
+#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0
+#define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xffffffff
+#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0
+#define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xffffffff
+#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0
+#define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xffffffff
+#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0
+#define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xffffffff
+#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0
+#define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xffffffff
+#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0
+#define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xffffffff
+#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0
+#define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xffffffff
+#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0
+#define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xffffffff
+#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0
+#define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xffffffff
+#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0
+#define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xffffffff
+#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0
+#define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xffffffff
+#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0
+#define VENDOR_ID__VENDOR_ID_MASK 0xffff
+#define VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define DEVICE_ID__DEVICE_ID_MASK 0xffff
+#define DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define COMMAND__IO_ACCESS_EN_MASK 0x1
+#define COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define COMMAND__MEM_ACCESS_EN_MASK 0x2
+#define COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define COMMAND__BUS_MASTER_EN_MASK 0x4
+#define COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
+#define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
+#define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define COMMAND__PAL_SNOOP_EN_MASK 0x20
+#define COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
+#define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define COMMAND__AD_STEPPING_MASK 0x80
+#define COMMAND__AD_STEPPING__SHIFT 0x7
+#define COMMAND__SERR_EN_MASK 0x100
+#define COMMAND__SERR_EN__SHIFT 0x8
+#define COMMAND__FAST_B2B_EN_MASK 0x200
+#define COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define COMMAND__INT_DIS_MASK 0x400
+#define COMMAND__INT_DIS__SHIFT 0xa
+#define STATUS__INT_STATUS_MASK 0x8
+#define STATUS__INT_STATUS__SHIFT 0x3
+#define STATUS__CAP_LIST_MASK 0x10
+#define STATUS__CAP_LIST__SHIFT 0x4
+#define STATUS__PCI_66_EN_MASK 0x20
+#define STATUS__PCI_66_EN__SHIFT 0x5
+#define STATUS__FAST_BACK_CAPABLE_MASK 0x80
+#define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x100
+#define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define STATUS__DEVSEL_TIMING_MASK 0x600
+#define STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define STATUS__SIGNAL_TARGET_ABORT_MASK 0x800
+#define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000
+#define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000
+#define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000
+#define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define STATUS__PARITY_ERROR_DETECTED_MASK 0x8000
+#define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define REVISION_ID__MINOR_REV_ID_MASK 0xf
+#define REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define REVISION_ID__MAJOR_REV_ID_MASK 0xf0
+#define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define PROG_INTERFACE__PROG_INTERFACE_MASK 0xff
+#define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define SUB_CLASS__SUB_CLASS_MASK 0xff
+#define SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BASE_CLASS__BASE_CLASS_MASK 0xff
+#define BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
+#define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define LATENCY__LATENCY_TIMER_MASK 0xff
+#define LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define HEADER__HEADER_TYPE_MASK 0x7f
+#define HEADER__HEADER_TYPE__SHIFT 0x0
+#define HEADER__DEVICE_TYPE_MASK 0x80
+#define HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIST__BIST_COMP_MASK 0xf
+#define BIST__BIST_COMP__SHIFT 0x0
+#define BIST__BIST_STRT_MASK 0x40
+#define BIST__BIST_STRT__SHIFT 0x6
+#define BIST__BIST_CAP_MASK 0x80
+#define BIST__BIST_CAP__SHIFT 0x7
+#define BASE_ADDR_1__BASE_ADDR_MASK 0xffffffff
+#define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BASE_ADDR_2__BASE_ADDR_MASK 0xffffffff
+#define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BASE_ADDR_3__BASE_ADDR_MASK 0xffffffff
+#define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BASE_ADDR_4__BASE_ADDR_MASK 0xffffffff
+#define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BASE_ADDR_5__BASE_ADDR_MASK 0xffffffff
+#define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BASE_ADDR_6__BASE_ADDR_MASK 0xffffffff
+#define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define ROM_BASE_ADDR__BASE_ADDR_MASK 0xffffffff
+#define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define CAP_PTR__CAP_PTR_MASK 0xff
+#define CAP_PTR__CAP_PTR__SHIFT 0x0
+#define INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
+#define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff
+#define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0xffff
+#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define ADAPTER_ID__SUBSYSTEM_ID_MASK 0xffff0000
+#define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define MIN_GRANT__MIN_GNT_MASK 0xff
+#define MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define MAX_LATENCY__MAX_LAT_MASK 0xff
+#define MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define VENDOR_CAP_LIST__CAP_ID_MASK 0xff
+#define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define VENDOR_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define VENDOR_CAP_LIST__LENGTH_MASK 0xff0000
+#define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0xffff
+#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xffff0000
+#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define PMI_CAP_LIST__CAP_ID_MASK 0xff
+#define PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PMI_CAP__VERSION_MASK 0x7
+#define PMI_CAP__VERSION__SHIFT 0x0
+#define PMI_CAP__PME_CLOCK_MASK 0x8
+#define PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x20
+#define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define PMI_CAP__AUX_CURRENT_MASK 0x1c0
+#define PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define PMI_CAP__D1_SUPPORT_MASK 0x200
+#define PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define PMI_CAP__D2_SUPPORT_MASK 0x400
+#define PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define PMI_CAP__PME_SUPPORT_MASK 0xf800
+#define PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
+#define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
+#define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define PMI_STATUS_CNTL__PME_EN_MASK 0x100
+#define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
+#define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
+#define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
+#define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
+#define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
+#define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
+#define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define PCIE_CAP_LIST__CAP_ID_MASK 0xff
+#define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PCIE_CAP__VERSION_MASK 0xf
+#define PCIE_CAP__VERSION__SHIFT 0x0
+#define PCIE_CAP__DEVICE_TYPE_MASK 0xf0
+#define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x100
+#define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e00
+#define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
+#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
+#define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define DEVICE_CAP__EXTENDED_TAG_MASK 0x20
+#define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
+#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
+#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
+#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
+#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
+#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
+#define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
+#define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
+#define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
+#define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
+#define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
+#define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
+#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
+#define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
+#define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
+#define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
+#define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
+#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define DEVICE_CNTL__INITIATE_FLR_MASK 0x8000
+#define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define DEVICE_STATUS__CORR_ERR_MASK 0x1
+#define DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define DEVICE_STATUS__NON_FATAL_ERR_MASK 0x2
+#define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define DEVICE_STATUS__FATAL_ERR_MASK 0x4
+#define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define DEVICE_STATUS__USR_DETECTED_MASK 0x8
+#define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define DEVICE_STATUS__AUX_PWR_MASK 0x10
+#define DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x20
+#define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define LINK_CAP__LINK_SPEED_MASK 0xf
+#define LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define LINK_CAP__LINK_WIDTH_MASK 0x3f0
+#define LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define LINK_CAP__PM_SUPPORT_MASK 0xc00
+#define LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
+#define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
+#define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
+#define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
+#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
+#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
+#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
+#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define LINK_CAP__PORT_NUMBER_MASK 0xff000000
+#define LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define LINK_CNTL__PM_CONTROL_MASK 0x3
+#define LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
+#define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define LINK_CNTL__LINK_DIS_MASK 0x10
+#define LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define LINK_CNTL__RETRAIN_LINK_MASK 0x20
+#define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
+#define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define LINK_CNTL__EXTENDED_SYNC_MASK 0x80
+#define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
+#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
+#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
+#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
+#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf
+#define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f0
+#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define LINK_STATUS__LINK_TRAINING_MASK 0x800
+#define LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000
+#define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define LINK_STATUS__DL_ACTIVE_MASK 0x2000
+#define LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000
+#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000
+#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
+#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
+#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
+#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
+#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
+#define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
+#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
+#define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
+#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
+#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
+#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
+#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
+#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
+#define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
+#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
+#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define DEVICE_CNTL2__LTR_EN_MASK 0x400
+#define DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define DEVICE_CNTL2__OBFF_EN_MASK 0x6000
+#define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
+#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define DEVICE_STATUS2__RESERVED_MASK 0xffff
+#define DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
+#define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
+#define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define LINK_CAP2__RESERVED_MASK 0xfffffe00
+#define LINK_CAP2__RESERVED__SHIFT 0x9
+#define LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
+#define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
+#define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
+#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
+#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define LINK_CNTL2__XMIT_MARGIN_MASK 0x380
+#define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
+#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
+#define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
+#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x1
+#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x2
+#define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x4
+#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x8
+#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x10
+#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x20
+#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define MSI_CAP_LIST__CAP_ID_MASK 0xff
+#define MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define MSI_MSG_CNTL__MSI_EN_MASK 0x1
+#define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe
+#define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x70
+#define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define MSI_MSG_CNTL__MSI_64BIT_MASK 0x80
+#define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
+#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
+#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
+#define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define MSI_MSG_DATA__MSI_DATA_MASK 0xffff
+#define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
+#define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
+#define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
+#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
+#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
+#define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
+#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
+#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
+#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
+#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
+#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x1
+#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1
+#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2
+#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1
+#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2
+#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
+#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
+#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
+#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
+#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
+#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
+#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
+#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
+#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
+#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
+#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
+#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
+#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
+#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
+#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
+#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
+#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
+#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
+#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
+#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
+#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
+#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
+#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
+#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
+#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
+#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
+#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
+#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
+#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
+#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
+#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
+#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
+#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
+#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
+#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
+#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
+#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
+#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
+#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
+#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
+#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
+#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
+#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
+#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
+#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
+#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
+#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
+#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
+#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
+#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
+#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
+#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
+#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
+#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
+#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
+#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
+#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
+#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
+#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
+#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
+#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
+#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
+#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
+#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
+#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
+#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
+#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
+#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
+#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
+#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
+#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
+#define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
+#define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
+#define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
+#define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
+#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
+#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
+#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
+#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
+#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x7
+#define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0xe0
+#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1f00
+#define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
+#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x7
+#define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0xe0
+#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1f00
+#define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
+#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x7
+#define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0xe0
+#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1f00
+#define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
+#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x7
+#define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0xe0
+#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1f00
+#define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
+#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x7
+#define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0xe0
+#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1f00
+#define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
+#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x7
+#define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0xe0
+#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1f00
+#define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xff
+#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0xff
+#define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x300
+#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x1c00
+#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x6000
+#define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x38000
+#define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x1c0000
+#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x1
+#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x1f
+#define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300
+#define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000
+#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff
+#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x1f
+#define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x100
+#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1f
+#define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
+#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
+#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
+#define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
+#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
+#define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
+#define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
+#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
+#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
+#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
+#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
+#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
+#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
+#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x1
+#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x2
+#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x4
+#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x8
+#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x10
+#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x20
+#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x40
+#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x1f
+#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x20
+#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x40
+#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define PCIE_ATS_CNTL__STU_MASK 0x1f
+#define PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000
+#define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x1
+#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x2
+#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x1
+#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x2
+#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x100
+#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000
+#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xffffffff
+#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xffffffff
+#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2
+#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x4
+#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1f00
+#define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x1
+#define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x2
+#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x4
+#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x1
+#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x2
+#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x4
+#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x100
+#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x600
+#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x7ff0000
+#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x7
+#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x300
+#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
+#define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3f00
+#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
+#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f
+#define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000
+#define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
+#define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
+#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
+#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
+#define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
+#define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
+#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
+#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
+#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
+#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x3ff
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x1c00
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x3ff0000
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1c000000
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define PCIE_INDEX__PCIE_INDEX_MASK 0xffffffff
+#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
+#define PCIE_DATA__PCIE_DATA_MASK 0xffffffff
+#define PCIE_DATA__PCIE_DATA__SHIFT 0x0
+#define PCIE_INDEX_2__PCIE_INDEX_MASK 0xffffffff
+#define PCIE_INDEX_2__PCIE_INDEX__SHIFT 0x0
+#define PCIE_DATA_2__PCIE_DATA_MASK 0xffffffff
+#define PCIE_DATA_2__PCIE_DATA__SHIFT 0x0
+#define PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff
+#define PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff
+#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff
+#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0
+#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff
+#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0
+#define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1
+#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe
+#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1
+#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80
+#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100
+#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200
+#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9
+#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00
+#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa
+#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000
+#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf
+#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000
+#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10
+#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000
+#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11
+#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000
+#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12
+#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000
+#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13
+#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING_MASK 0x100000
+#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING__SHIFT 0x14
+#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000
+#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15
+#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000
+#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16
+#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000
+#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17
+#define PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000
+#define PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18
+#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000
+#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000
+#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f
+#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf
+#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0
+#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000
+#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18
+#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000
+#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff
+#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0
+#define PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100
+#define PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8
+#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000
+#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10
+#define PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x1
+#define PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
+#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x2
+#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
+#define PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x4
+#define PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
+#define PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x8
+#define PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
+#define PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x10
+#define PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
+#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x40
+#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
+#define PCIE_INT_CNTL__LINK_BW_INT_EN_MASK 0x80
+#define PCIE_INT_CNTL__LINK_BW_INT_EN__SHIFT 0x7
+#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN_MASK 0x100
+#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN__SHIFT 0x8
+#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x1
+#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
+#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x2
+#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
+#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x4
+#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
+#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x8
+#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
+#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x10
+#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
+#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x40
+#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
+#define PCIE_INT_STATUS__LINK_BW_INT_STATUS_MASK 0x80
+#define PCIE_INT_STATUS__LINK_BW_INT_STATUS__SHIFT 0x7
+#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS_MASK 0x100
+#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS__SHIFT 0x8
+#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1
+#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0
+#define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e
+#define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1
+#define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0
+#define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6
+#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800
+#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb
+#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000
+#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11
+#define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000
+#define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12
+#define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000
+#define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13
+#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000
+#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15
+#define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000
+#define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16
+#define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000
+#define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17
+#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000
+#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P_MASK 0x3
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P__SHIFT 0x0
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP_MASK 0xc
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP__SHIFT 0x2
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL_MASK 0x30
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL__SHIFT 0x4
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P_MASK 0xc0
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P__SHIFT 0x6
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP_MASK 0x300
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP__SHIFT 0x8
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P_MASK 0xc00
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P__SHIFT 0xa
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP_MASK 0x3000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP__SHIFT 0xc
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P_MASK 0x30000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P__SHIFT 0x10
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP_MASK 0xc0000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP__SHIFT 0x12
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL_MASK 0x300000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL__SHIFT 0x14
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P_MASK 0xc00000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P__SHIFT 0x16
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP_MASK 0x3000000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP__SHIFT 0x18
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P_MASK 0xc000000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P__SHIFT 0x1a
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP_MASK 0x30000000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP__SHIFT 0x1c
+#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4
+#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2
+#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8
+#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3
+#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10
+#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4
+#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0
+#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6
+#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100
+#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8
+#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200
+#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc
+#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST_MASK 0x2000
+#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST__SHIFT 0xd
+#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40
+#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6
+#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80
+#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000
+#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc
+#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f
+#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0
+#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00
+#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8
+#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000
+#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10
+#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000
+#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18
+#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f
+#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0
+#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00
+#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8
+#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000
+#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10
+#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000
+#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18
+#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f
+#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0
+#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00
+#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8
+#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000
+#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10
+#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000
+#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18
+#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f
+#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0
+#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00
+#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8
+#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000
+#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10
+#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000
+#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18
+#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f
+#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0
+#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00
+#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8
+#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000
+#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10
+#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000
+#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18
+#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f
+#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0
+#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00
+#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8
+#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000
+#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10
+#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000
+#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18
+#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1
+#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0
+#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2
+#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1
+#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c
+#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2
+#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0
+#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5
+#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff
+#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0
+#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000
+#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10
+#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1
+#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2
+#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8
+#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3
+#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10
+#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4
+#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20
+#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5
+#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40
+#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6
+#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff
+#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0
+#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff
+#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0
+#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff
+#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0
+#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff
+#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0
+#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff
+#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0
+#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff
+#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0
+#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff
+#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0
+#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff
+#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0
+#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff
+#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0
+#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff
+#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1
+#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0
+#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2
+#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1
+#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4
+#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2
+#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8
+#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3
+#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10
+#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4
+#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20
+#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5
+#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40
+#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6
+#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80
+#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7
+#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100
+#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8
+#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000
+#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc
+#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000
+#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd
+#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000
+#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe
+#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000
+#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10
+#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff
+#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0
+#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000
+#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10
+#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff
+#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0
+#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff
+#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0
+#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000
+#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8
+#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE_MASK 0x1
+#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT 0x0
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN_MASK 0x2
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT 0x1
+#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE_MASK 0x4
+#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2
+#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE_MASK 0x8
+#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT 0x3
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH_MASK 0xf0
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT 0x4
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH_MASK 0xf00
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT 0x8
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD_MASK 0xf000
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT 0xc
+#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE_MASK 0x10000
+#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT 0x10
+#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE_MASK 0x20000
+#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT 0x11
+#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE_MASK 0x40000
+#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT 0x12
+#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE_MASK 0xf00000
+#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT 0x14
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x7
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x38
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x40
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x380
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x1c00
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x2000
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x4000
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x8000
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2
+#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff
+#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00
+#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000
+#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000
+#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff
+#define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff
+#define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff
+#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00
+#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff
+#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff
+#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff
+#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00
+#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff
+#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff
+#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff
+#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00
+#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff
+#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff
+#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff
+#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff
+#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff
+#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff
+#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18
+#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff
+#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00
+#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff
+#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff
+#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0
+#define PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1
+#define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
+#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2
+#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
+#define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4
+#define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2
+#define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8
+#define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3
+#define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10
+#define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4
+#define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20
+#define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5
+#define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40
+#define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6
+#define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80
+#define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7
+#define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100
+#define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8
+#define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200
+#define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9
+#define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400
+#define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa
+#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800
+#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb
+#define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000
+#define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc
+#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000
+#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd
+#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000
+#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe
+#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000
+#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf
+#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000
+#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
+#define PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000
+#define PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
+#define PCIE_STRAP_F1__STRAP_F1_EN_MASK 0x1
+#define PCIE_STRAP_F1__STRAP_F1_EN__SHIFT 0x0
+#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK 0x2
+#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
+#define PCIE_STRAP_F1__STRAP_F1_MSI_EN_MASK 0x4
+#define PCIE_STRAP_F1__STRAP_F1_MSI_EN__SHIFT 0x2
+#define PCIE_STRAP_F1__STRAP_F1_VC_EN_MASK 0x8
+#define PCIE_STRAP_F1__STRAP_F1_VC_EN__SHIFT 0x3
+#define PCIE_STRAP_F1__STRAP_F1_DSN_EN_MASK 0x10
+#define PCIE_STRAP_F1__STRAP_F1_DSN_EN__SHIFT 0x4
+#define PCIE_STRAP_F1__STRAP_F1_AER_EN_MASK 0x20
+#define PCIE_STRAP_F1__STRAP_F1_AER_EN__SHIFT 0x5
+#define PCIE_STRAP_F1__STRAP_F1_ACS_EN_MASK 0x40
+#define PCIE_STRAP_F1__STRAP_F1_ACS_EN__SHIFT 0x6
+#define PCIE_STRAP_F1__STRAP_F1_BAR_EN_MASK 0x80
+#define PCIE_STRAP_F1__STRAP_F1_BAR_EN__SHIFT 0x7
+#define PCIE_STRAP_F1__STRAP_F1_PWR_EN_MASK 0x100
+#define PCIE_STRAP_F1__STRAP_F1_PWR_EN__SHIFT 0x8
+#define PCIE_STRAP_F1__STRAP_F1_DPA_EN_MASK 0x200
+#define PCIE_STRAP_F1__STRAP_F1_DPA_EN__SHIFT 0x9
+#define PCIE_STRAP_F1__STRAP_F1_ATS_EN_MASK 0x400
+#define PCIE_STRAP_F1__STRAP_F1_ATS_EN__SHIFT 0xa
+#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN_MASK 0x800
+#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN__SHIFT 0xb
+#define PCIE_STRAP_F1__STRAP_F1_PASID_EN_MASK 0x1000
+#define PCIE_STRAP_F1__STRAP_F1_PASID_EN__SHIFT 0xc
+#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN_MASK 0x2000
+#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN__SHIFT 0xd
+#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN_MASK 0x4000
+#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN__SHIFT 0xe
+#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN_MASK 0x8000
+#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN__SHIFT 0xf
+#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL_MASK 0x10000
+#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
+#define PCIE_STRAP_F2__STRAP_F2_EN_MASK 0x1
+#define PCIE_STRAP_F2__STRAP_F2_EN__SHIFT 0x0
+#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK 0x2
+#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
+#define PCIE_STRAP_F2__STRAP_F2_MSI_EN_MASK 0x4
+#define PCIE_STRAP_F2__STRAP_F2_MSI_EN__SHIFT 0x2
+#define PCIE_STRAP_F2__STRAP_F2_VC_EN_MASK 0x8
+#define PCIE_STRAP_F2__STRAP_F2_VC_EN__SHIFT 0x3
+#define PCIE_STRAP_F2__STRAP_F2_DSN_EN_MASK 0x10
+#define PCIE_STRAP_F2__STRAP_F2_DSN_EN__SHIFT 0x4
+#define PCIE_STRAP_F2__STRAP_F2_AER_EN_MASK 0x20
+#define PCIE_STRAP_F2__STRAP_F2_AER_EN__SHIFT 0x5
+#define PCIE_STRAP_F2__STRAP_F2_ACS_EN_MASK 0x40
+#define PCIE_STRAP_F2__STRAP_F2_ACS_EN__SHIFT 0x6
+#define PCIE_STRAP_F2__STRAP_F2_BAR_EN_MASK 0x80
+#define PCIE_STRAP_F2__STRAP_F2_BAR_EN__SHIFT 0x7
+#define PCIE_STRAP_F2__STRAP_F2_PWR_EN_MASK 0x100
+#define PCIE_STRAP_F2__STRAP_F2_PWR_EN__SHIFT 0x8
+#define PCIE_STRAP_F2__STRAP_F2_DPA_EN_MASK 0x200
+#define PCIE_STRAP_F2__STRAP_F2_DPA_EN__SHIFT 0x9
+#define PCIE_STRAP_F2__STRAP_F2_ATS_EN_MASK 0x400
+#define PCIE_STRAP_F2__STRAP_F2_ATS_EN__SHIFT 0xa
+#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN_MASK 0x800
+#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN__SHIFT 0xb
+#define PCIE_STRAP_F2__STRAP_F2_PASID_EN_MASK 0x1000
+#define PCIE_STRAP_F2__STRAP_F2_PASID_EN__SHIFT 0xc
+#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN_MASK 0x2000
+#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN__SHIFT 0xd
+#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN_MASK 0x4000
+#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN__SHIFT 0xe
+#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN_MASK 0x8000
+#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN__SHIFT 0xf
+#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL_MASK 0x10000
+#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
+#define PCIE_STRAP_F3__RESERVED_MASK 0xffffffff
+#define PCIE_STRAP_F3__RESERVED__SHIFT 0x0
+#define PCIE_STRAP_F4__RESERVED_MASK 0xffffffff
+#define PCIE_STRAP_F4__RESERVED__SHIFT 0x0
+#define PCIE_STRAP_F5__RESERVED_MASK 0xffffffff
+#define PCIE_STRAP_F5__RESERVED__SHIFT 0x0
+#define PCIE_STRAP_F6__RESERVED_MASK 0xffffffff
+#define PCIE_STRAP_F6__RESERVED__SHIFT 0x0
+#define PCIE_STRAP_F7__RESERVED_MASK 0xffffffff
+#define PCIE_STRAP_F7__RESERVED__SHIFT 0x0
+#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG_MASK 0xf
+#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG__SHIFT 0x0
+#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10
+#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4
+#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH_MASK 0x1f00
+#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH__SHIFT 0x8
+#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2000
+#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0xd
+#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED_MASK 0x4000
+#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED__SHIFT 0xe
+#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_MASK 0x8000
+#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0xf
+#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000
+#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
+#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000
+#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19
+#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000
+#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a
+#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000
+#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c
+#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000
+#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000
+#define PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e
+#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000
+#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f
+#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2
+#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1
+#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4
+#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
+#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8
+#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3
+#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10
+#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
+#define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1
+#define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d
+#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f
+#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0
+#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80
+#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7
+#define PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff
+#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0
+#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000
+#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10
+#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff
+#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0
+#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000
+#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10
+#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff
+#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0
+#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff
+#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0
+#define PCIE_PRBS_MISC__PRBS_EN_MASK 0x1
+#define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0
+#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0x6
+#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1
+#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x8
+#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x3
+#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x10
+#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x4
+#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0x60
+#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x5
+#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0xf80
+#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x7
+#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000
+#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe
+#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000
+#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10
+#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff
+#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0
+#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff
+#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0
+#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff
+#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0
+#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300
+#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000
+#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000
+#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000
+#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff
+#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x1f
+#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
+#define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
+#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
+#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
+#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
+#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
+#define PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
+#define PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
+#define PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
+#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
+#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
+#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
+#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
+#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
+#define PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
+#define PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
+#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
+#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
+#define PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
+#define PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
+#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
+#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x1000000
+#define PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x2000000
+#define PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x4000000
+#define PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
+#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
+#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
+#define PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
+#define PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
+#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
+#define PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
+#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
+#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
+#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
+#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
+#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
+#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
+#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
+#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
+#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
+#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
+#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
+#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
+#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
+#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
+#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
+#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define PCIE_FC_P__PD_CREDITS_MASK 0xff
+#define PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define PCIE_FC_P__PH_CREDITS_MASK 0xff00
+#define PCIE_FC_P__PH_CREDITS__SHIFT 0x8
+#define PCIE_FC_NP__NPD_CREDITS_MASK 0xff
+#define PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
+#define PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
+#define PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
+#define PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
+#define PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
+#define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
+#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
+#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
+#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
+#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
+#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
+#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
+#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
+#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x1000
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0xc
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x2000
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0xd
+#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
+#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
+#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
+#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
+#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
+#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
+#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
+#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
+#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
+#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
+#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
+#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
+#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
+#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
+#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
+#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
+#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
+#define PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
+#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
+#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
+#define PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
+#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
+#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
+#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
+#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
+#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
+#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
+#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
+#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
+#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
+#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
+#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
+#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
+#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
+#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
+#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
+#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
+#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
+#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
+#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
+#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
+#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
+#define PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
+#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
+#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
+#define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
+#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
+#define PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
+#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
+#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
+#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
+#define PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
+#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
+#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
+#define PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
+#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
+#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
+#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
+#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
+#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
+#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
+#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
+#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
+#define PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
+#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
+#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
+#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
+#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
+#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
+#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
+#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
+#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
+#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
+#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
+#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
+#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
+#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
+#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
+#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
+#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
+#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
+#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
+#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
+#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
+#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
+#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
+#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
+#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
+#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
+#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
+#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
+#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
+#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
+#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
+#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
+#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
+#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
+#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
+#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
+#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
+#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
+#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
+#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
+#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
+#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
+#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
+#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
+#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
+#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
+#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
+#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
+#define PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
+#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
+#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
+#define PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
+#define PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
+#define PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
+#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
+#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
+#define PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
+#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
+#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
+#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
+#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
+#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
+#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
+#define PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
+#define PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
+#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
+#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
+#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
+#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
+#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
+#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
+#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
+#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
+#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
+#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
+#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
+#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
+#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
+#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
+#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
+#define PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
+#define PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
+#define PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
+#define PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
+#define PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
+#define PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
+#define PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
+#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
+#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
+#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
+#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
+#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
+#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
+#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
+#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
+#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
+#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
+#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
+#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
+#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
+#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
+#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
+#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
+#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
+#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
+#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
+#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
+#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
+#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
+#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
+#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
+#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
+#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
+#define PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
+#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
+#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
+#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
+#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
+#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
+#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
+#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
+#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
+#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
+#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
+#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
+#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
+#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
+#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
+#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
+#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
+#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
+#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
+#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
+#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
+#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
+#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
+#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
+#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
+#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
+#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
+#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
+#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
+#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
+#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
+#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
+#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
+#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
+#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
+#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
+#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
+#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
+#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
+#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
+#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
+#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
+#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
+#define PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
+#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
+#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
+#define PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
+#define PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
+#define PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
+#define PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
+#define PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
+#define PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
+#define PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
+#define PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
+#define PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
+#define PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
+#define PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
+#define PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
+#define PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
+#define PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
+#define PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
+#define PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
+#define PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
+#define PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
+#define PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
+#define PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
+#define PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
+#define PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
+#define PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
+#define PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
+#define PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
+#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
+#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
+#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
+#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
+#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
+#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
+#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
+#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
+#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
+#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
+#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
+#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
+#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
+#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
+#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
+#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
+#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
+#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
+#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define PB0_GLB_CTRL_REG0__BACKUP_MASK 0xffff
+#define PB0_GLB_CTRL_REG0__BACKUP__SHIFT 0x0
+#define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x30000
+#define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x10
+#define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x700000
+#define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x14
+#define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x800000
+#define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x17
+#define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x1000000
+#define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x18
+#define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x2000000
+#define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x19
+#define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x4000000
+#define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x1a
+#define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000
+#define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x1e
+#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x1
+#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x0
+#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x7e
+#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x1
+#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x80
+#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x7
+#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x3f00
+#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x8
+#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x4000
+#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0xe
+#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x3f8000
+#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0xf
+#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x400000
+#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x16
+#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000
+#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x17
+#define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000
+#define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x1e
+#define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000
+#define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x1f
+#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x1
+#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x0
+#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0xfe
+#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x1
+#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x100
+#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x8
+#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0xfe00
+#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x9
+#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x10000
+#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x10
+#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0xfe0000
+#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x11
+#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x1000000
+#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x18
+#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000
+#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x19
+#define PB0_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x1f
+#define PB0_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x0
+#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x60
+#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x5
+#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x180
+#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x7
+#define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x600
+#define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x9
+#define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x800
+#define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0xb
+#define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x1000
+#define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0xc
+#define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x1c000
+#define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0xe
+#define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x1c0000
+#define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x12
+#define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x200000
+#define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x15
+#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x400000
+#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x16
+#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x7800000
+#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x17
+#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x8000000
+#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x1b
+#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000
+#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x1c
+#define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000
+#define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x1f
+#define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0xffff
+#define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x0
+#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x30000
+#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x10
+#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x40000
+#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x12
+#define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x3c00000
+#define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x16
+#define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x4000000
+#define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x1a
+#define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x8000000
+#define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x1b
+#define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000
+#define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x1c
+#define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0xff
+#define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x0
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3_MASK 0x1
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3__SHIFT 0x0
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7_MASK 0x2
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7__SHIFT 0x1
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11_MASK 0x4
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11__SHIFT 0x2
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15_MASK 0x8
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15__SHIFT 0x3
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT_MASK 0x10
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT__SHIFT 0x4
+#define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0xf00
+#define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x8
+#define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0xf000
+#define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0xc
+#define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0xf0000
+#define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x10
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x100000
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x14
+#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3_MASK 0x1
+#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3__SHIFT 0x0
+#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3_MASK 0x2
+#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3__SHIFT 0x1
+#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3_MASK 0x4
+#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3__SHIFT 0x2
+#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x1000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0xc
+#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x2000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0xd
+#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x4000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0xe
+#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x8000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0xf
+#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK 0x30000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT 0x10
+#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0xc0000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x12
+#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK 0x300000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1__SHIFT 0x14
+#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0xc00000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x16
+#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_2_MASK 0x3000000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_2__SHIFT 0x18
+#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0xc000000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x1a
+#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_3_MASK 0x30000000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_3__SHIFT 0x1c
+#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x1e
+#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7_MASK 0x1
+#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7__SHIFT 0x0
+#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7_MASK 0x2
+#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7__SHIFT 0x1
+#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7_MASK 0x4
+#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7__SHIFT 0x2
+#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x1000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0xc
+#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x2000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0xd
+#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x4000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0xe
+#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x8000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0xf
+#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_4_MASK 0x30000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_4__SHIFT 0x10
+#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0xc0000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x12
+#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK 0x300000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_5__SHIFT 0x14
+#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0xc00000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x16
+#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_6_MASK 0x3000000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_6__SHIFT 0x18
+#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0xc000000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x1a
+#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_7_MASK 0x30000000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__MODE_7__SHIFT 0x1c
+#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x1e
+#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11_MASK 0x1
+#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11__SHIFT 0x0
+#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11_MASK 0x2
+#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11__SHIFT 0x1
+#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11_MASK 0x4
+#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11__SHIFT 0x2
+#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x1000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0xc
+#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x2000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0xd
+#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x4000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0xe
+#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x8000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0xf
+#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_8_MASK 0x30000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_8__SHIFT 0x10
+#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0xc0000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x12
+#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_9_MASK 0x300000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_9__SHIFT 0x14
+#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0xc00000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x16
+#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_10_MASK 0x3000000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT 0x18
+#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0xc000000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x1a
+#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_11_MASK 0x30000000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__MODE_11__SHIFT 0x1c
+#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x1e
+#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15_MASK 0x1
+#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15__SHIFT 0x0
+#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15_MASK 0x2
+#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15__SHIFT 0x1
+#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15_MASK 0x4
+#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15__SHIFT 0x2
+#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x1000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0xc
+#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x2000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0xd
+#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x4000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0xe
+#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x8000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0xf
+#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_12_MASK 0x30000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_12__SHIFT 0x10
+#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0xc0000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x12
+#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_13_MASK 0x300000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_13__SHIFT 0x14
+#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0xc00000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x16
+#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_14_MASK 0x3000000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_14__SHIFT 0x18
+#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0xc000000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x1a
+#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_15_MASK 0x30000000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__MODE_15__SHIFT 0x1c
+#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x1e
+#define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0xffff
+#define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x0
+#define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000
+#define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x10
+#define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x1
+#define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x0
+#define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x2
+#define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x1
+#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x4
+#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x2
+#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x8
+#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x3
+#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x8000
+#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0xf
+#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000
+#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x10
+#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x1
+#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x0
+#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x2
+#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x1
+#define PB0_HW_DEBUG__PB0_HW_00_DEBUG_MASK 0x1
+#define PB0_HW_DEBUG__PB0_HW_00_DEBUG__SHIFT 0x0
+#define PB0_HW_DEBUG__PB0_HW_01_DEBUG_MASK 0x2
+#define PB0_HW_DEBUG__PB0_HW_01_DEBUG__SHIFT 0x1
+#define PB0_HW_DEBUG__PB0_HW_02_DEBUG_MASK 0x4
+#define PB0_HW_DEBUG__PB0_HW_02_DEBUG__SHIFT 0x2
+#define PB0_HW_DEBUG__PB0_HW_03_DEBUG_MASK 0x8
+#define PB0_HW_DEBUG__PB0_HW_03_DEBUG__SHIFT 0x3
+#define PB0_HW_DEBUG__PB0_HW_04_DEBUG_MASK 0x10
+#define PB0_HW_DEBUG__PB0_HW_04_DEBUG__SHIFT 0x4
+#define PB0_HW_DEBUG__PB0_HW_05_DEBUG_MASK 0x20
+#define PB0_HW_DEBUG__PB0_HW_05_DEBUG__SHIFT 0x5
+#define PB0_HW_DEBUG__PB0_HW_06_DEBUG_MASK 0x40
+#define PB0_HW_DEBUG__PB0_HW_06_DEBUG__SHIFT 0x6
+#define PB0_HW_DEBUG__PB0_HW_07_DEBUG_MASK 0x80
+#define PB0_HW_DEBUG__PB0_HW_07_DEBUG__SHIFT 0x7
+#define PB0_HW_DEBUG__PB0_HW_08_DEBUG_MASK 0x100
+#define PB0_HW_DEBUG__PB0_HW_08_DEBUG__SHIFT 0x8
+#define PB0_HW_DEBUG__PB0_HW_09_DEBUG_MASK 0x200
+#define PB0_HW_DEBUG__PB0_HW_09_DEBUG__SHIFT 0x9
+#define PB0_HW_DEBUG__PB0_HW_10_DEBUG_MASK 0x400
+#define PB0_HW_DEBUG__PB0_HW_10_DEBUG__SHIFT 0xa
+#define PB0_HW_DEBUG__PB0_HW_11_DEBUG_MASK 0x800
+#define PB0_HW_DEBUG__PB0_HW_11_DEBUG__SHIFT 0xb
+#define PB0_HW_DEBUG__PB0_HW_12_DEBUG_MASK 0x1000
+#define PB0_HW_DEBUG__PB0_HW_12_DEBUG__SHIFT 0xc
+#define PB0_HW_DEBUG__PB0_HW_13_DEBUG_MASK 0x2000
+#define PB0_HW_DEBUG__PB0_HW_13_DEBUG__SHIFT 0xd
+#define PB0_HW_DEBUG__PB0_HW_14_DEBUG_MASK 0x4000
+#define PB0_HW_DEBUG__PB0_HW_14_DEBUG__SHIFT 0xe
+#define PB0_HW_DEBUG__PB0_HW_15_DEBUG_MASK 0x8000
+#define PB0_HW_DEBUG__PB0_HW_15_DEBUG__SHIFT 0xf
+#define PB0_HW_DEBUG__PB0_HW_16_DEBUG_MASK 0x10000
+#define PB0_HW_DEBUG__PB0_HW_16_DEBUG__SHIFT 0x10
+#define PB0_HW_DEBUG__PB0_HW_17_DEBUG_MASK 0x20000
+#define PB0_HW_DEBUG__PB0_HW_17_DEBUG__SHIFT 0x11
+#define PB0_HW_DEBUG__PB0_HW_18_DEBUG_MASK 0x40000
+#define PB0_HW_DEBUG__PB0_HW_18_DEBUG__SHIFT 0x12
+#define PB0_HW_DEBUG__PB0_HW_19_DEBUG_MASK 0x80000
+#define PB0_HW_DEBUG__PB0_HW_19_DEBUG__SHIFT 0x13
+#define PB0_HW_DEBUG__PB0_HW_20_DEBUG_MASK 0x100000
+#define PB0_HW_DEBUG__PB0_HW_20_DEBUG__SHIFT 0x14
+#define PB0_HW_DEBUG__PB0_HW_21_DEBUG_MASK 0x200000
+#define PB0_HW_DEBUG__PB0_HW_21_DEBUG__SHIFT 0x15
+#define PB0_HW_DEBUG__PB0_HW_22_DEBUG_MASK 0x400000
+#define PB0_HW_DEBUG__PB0_HW_22_DEBUG__SHIFT 0x16
+#define PB0_HW_DEBUG__PB0_HW_23_DEBUG_MASK 0x800000
+#define PB0_HW_DEBUG__PB0_HW_23_DEBUG__SHIFT 0x17
+#define PB0_HW_DEBUG__PB0_HW_24_DEBUG_MASK 0x1000000
+#define PB0_HW_DEBUG__PB0_HW_24_DEBUG__SHIFT 0x18
+#define PB0_HW_DEBUG__PB0_HW_25_DEBUG_MASK 0x2000000
+#define PB0_HW_DEBUG__PB0_HW_25_DEBUG__SHIFT 0x19
+#define PB0_HW_DEBUG__PB0_HW_26_DEBUG_MASK 0x4000000
+#define PB0_HW_DEBUG__PB0_HW_26_DEBUG__SHIFT 0x1a
+#define PB0_HW_DEBUG__PB0_HW_27_DEBUG_MASK 0x8000000
+#define PB0_HW_DEBUG__PB0_HW_27_DEBUG__SHIFT 0x1b
+#define PB0_HW_DEBUG__PB0_HW_28_DEBUG_MASK 0x10000000
+#define PB0_HW_DEBUG__PB0_HW_28_DEBUG__SHIFT 0x1c
+#define PB0_HW_DEBUG__PB0_HW_29_DEBUG_MASK 0x20000000
+#define PB0_HW_DEBUG__PB0_HW_29_DEBUG__SHIFT 0x1d
+#define PB0_HW_DEBUG__PB0_HW_30_DEBUG_MASK 0x40000000
+#define PB0_HW_DEBUG__PB0_HW_30_DEBUG__SHIFT 0x1e
+#define PB0_HW_DEBUG__PB0_HW_31_DEBUG_MASK 0x80000000
+#define PB0_HW_DEBUG__PB0_HW_31_DEBUG__SHIFT 0x1f
+#define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK 0x2
+#define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START__SHIFT 0x1
+#define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL_MASK 0x4
+#define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT 0x2
+#define PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS_MASK 0x8
+#define PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS__SHIFT 0x3
+#define PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH_MASK 0x60
+#define PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH__SHIFT 0x5
+#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL_MASK 0xf80
+#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL__SHIFT 0x7
+#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF_MASK 0x1000
+#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF__SHIFT 0xc
+#define PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0__MASK 0x2000
+#define PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0___SHIFT 0xd
+#define PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD_MASK 0x4000
+#define PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD__SHIFT 0xe
+#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x8000
+#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0xf
+#define PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE_MASK 0xf0000
+#define PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE__SHIFT 0x10
+#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE_MASK 0x100000
+#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE__SHIFT 0x14
+#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL_MASK 0x1e00000
+#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x15
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN_MASK 0x1e
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN__SHIFT 0x1
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL_MASK 0x1e0
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL__SHIFT 0x5
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN_MASK 0x3e00
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN__SHIFT 0x9
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL_MASK 0x7c000
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL__SHIFT 0xe
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN_MASK 0x780000
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN__SHIFT 0x13
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL_MASK 0x7800000
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL__SHIFT 0x17
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN_MASK 0x8000000
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN__SHIFT 0x1b
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL_MASK 0x10000000
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL__SHIFT 0x1c
+#define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1__MASK 0x20000000
+#define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT 0x1d
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN_MASK 0x40000000
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN__SHIFT 0x1e
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN_MASK 0x1e
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN__SHIFT 0x1
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE_MASK 0x20
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE__SHIFT 0x5
+#define PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN_MASK 0x40
+#define PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x6
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS_MASK 0x80
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS__SHIFT 0x7
+#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL_MASK 0x300
+#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x8
+#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL_MASK 0xc00
+#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL__SHIFT 0xa
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME_MASK 0xf000
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME__SHIFT 0xc
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME_MASK 0xf0000
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME__SHIFT 0x10
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME_MASK 0xf00000
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME__SHIFT 0x14
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME_MASK 0xf000000
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME__SHIFT 0x18
+#define PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL_MASK 0x70000000
+#define PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL__SHIFT 0x1c
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE_MASK 0x80000000
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE__SHIFT 0x1f
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK 0x2
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ__SHIFT 0x1
+#define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG_MASK 0x1c
+#define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT 0x2
+#define PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL_MASK 0x60
+#define PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL__SHIFT 0x5
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS_MASK 0x80
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS__SHIFT 0x7
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL_MASK 0x700
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL__SHIFT 0x8
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN_MASK 0x7800
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN__SHIFT 0xb
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE_MASK 0x1ff8000
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE__SHIFT 0xf
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME_MASK 0x1e000000
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT 0x19
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN_MASK 0x60000000
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN__SHIFT 0x1d
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS_MASK 0x80000000
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS__SHIFT 0x1f
+#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL_MASK 0xe
+#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL__SHIFT 0x1
+#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL_MASK 0x1ff0
+#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL__SHIFT 0x4
+#define PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF_MASK 0x2000
+#define PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF__SHIFT 0xd
+#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS_MASK 0x8000
+#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS__SHIFT 0xf
+#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL_MASK 0xff0000
+#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL__SHIFT 0x10
+#define PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL_MASK 0x1000000
+#define PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL__SHIFT 0x18
+#define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK 0x2
+#define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN__SHIFT 0x1
+#define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING_MASK 0x4
+#define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT 0x2
+#define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x3f
+#define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x0
+#define PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR_MASK 0x80
+#define PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR__SHIFT 0x7
+#define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0xf00
+#define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x8
+#define PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN_MASK 0x100000
+#define PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN__SHIFT 0x14
+#define PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY_MASK 0x200000
+#define PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY__SHIFT 0x15
+#define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x400000
+#define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x16
+#define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x800000
+#define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x17
+#define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000
+#define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x18
+#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0xff
+#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x0
+#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x100
+#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x8
+#define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x10000
+#define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x10
+#define PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS_MASK 0xe0000
+#define PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS__SHIFT 0x11
+#define PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME_MASK 0xf00000
+#define PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME__SHIFT 0x14
+#define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0xffff
+#define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x0
+#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x1
+#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x0
+#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x3e
+#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x1
+#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR_MASK 0xff
+#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR__SHIFT 0x0
+#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR_MASK 0xff00
+#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR__SHIFT 0x8
+#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED_MASK 0x10000
+#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED__SHIFT 0x10
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x1
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x0
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x2
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x1
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x4
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x2
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x8
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x3
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x10
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x4
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x20
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x5
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x40
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x6
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x80
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x7
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x100
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x8
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x200
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x9
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x400
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0xa
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x800
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0xb
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x1000
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0xc
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x2000
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0xd
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x4000
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0xe
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x10000
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x10
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x20000
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x11
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x40000
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x12
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x80000
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x13
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x100000
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x14
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x200000
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x15
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x400000
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x16
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x800000
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x17
+#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x3
+#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x0
+#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x4
+#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x2
+#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x8
+#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x3
+#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x7f0
+#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x4
+#define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x800
+#define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0xb
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0xff
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x100
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x8
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0xe00
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x9
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x1000
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0xc
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x2000
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0xd
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x4000
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0xe
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0xfff8000
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0xf
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x1c
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x1e
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x1f
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x1f
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x0
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x20
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x5
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0xc0
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x6
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x100
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x8
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x200
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x9
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x400
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0xa
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x800
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0xb
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x1000
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0xc
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x2000
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0xd
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x4000
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0xe
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x380000
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x13
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x400000
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x16
+#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
+#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
+#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
+#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
+#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x70
+#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x4
+#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE_MASK 0x300
+#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE__SHIFT 0x8
+#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
+#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
+#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
+#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
+#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x70
+#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x4
+#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE_MASK 0x300
+#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE__SHIFT 0x8
+#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
+#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
+#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
+#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
+#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x70
+#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x4
+#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE_MASK 0x300
+#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE__SHIFT 0x8
+#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
+#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
+#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
+#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
+#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x70
+#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x4
+#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE_MASK 0x300
+#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE__SHIFT 0x8
+#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x3
+#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x0
+#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x4
+#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x2
+#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x8
+#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x3
+#define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x10
+#define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x4
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x7
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x8
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x3
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x70
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x4
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x80
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x7
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x100
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x8
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x200
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x9
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x3fc00
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0xa
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x40000
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x12
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0xff80000
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x13
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x1c
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x1d
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x1f
+#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x7
+#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x0
+#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x8
+#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x3
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x10
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x4
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x20
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x5
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x40
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x6
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x80
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x7
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x100
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x8
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x200
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x9
+#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x3c000
+#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0xe
+#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x40000
+#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x12
+#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
+#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
+#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
+#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
+#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x70
+#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x4
+#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE_MASK 0x300
+#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE__SHIFT 0x8
+#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
+#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
+#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
+#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
+#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x70
+#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x4
+#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE_MASK 0x300
+#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE__SHIFT 0x8
+#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
+#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
+#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
+#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
+#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x70
+#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x4
+#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE_MASK 0x300
+#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE__SHIFT 0x8
+#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
+#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
+#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
+#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
+#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x70
+#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x4
+#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE_MASK 0x300
+#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE__SHIFT 0x8
+#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x3ff
+#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x0
+#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0xffc00
+#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0xa
+#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000
+#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x14
+#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE_MASK 0xc0000000
+#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE__SHIFT 0x1e
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0xf
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x0
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0xf0
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x4
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0xf00
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x8
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0xf000
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0xc
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0xf0000
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x10
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0xf00000
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x14
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x1000000
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x18
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x2000000
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x19
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x4000000
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x1a
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x8000000
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x1b
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x1c
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x1d
+#define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000
+#define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x1e
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0xf000
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0xc
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0xf0000
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x10
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0xf00000
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x14
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x3000000
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x18
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0xc000000
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x1a
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x1c
+#define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000
+#define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x1e
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x1
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x0
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x2
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x1
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x4
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x2
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0xf00000
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x14
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0xf000000
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x18
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x1c
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x7
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x0
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x38
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x3
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x1c0
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x6
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0xe00
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x9
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x7000
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0xc
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x38000
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0xf
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0xf00000
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x14
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0xf000000
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x18
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x1c
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x1f
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x0
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x3e0
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x5
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x7c00
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0xa
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x8000
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0xf
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x10000
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x10
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x20000
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x11
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x40000
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x12
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x80000
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x13
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x100000
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x14
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x8000000
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x1b
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x1c
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x1d
+#define PB0_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0_MASK 0x40000000
+#define PB0_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0__SHIFT 0x1e
+#define PB0_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE_MASK 0x80000000
+#define PB0_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE__SHIFT 0x1f
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0xf
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x0
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0xf0
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x4
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0xf00
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x8
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0xf000
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0xc
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0xf0000
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x10
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0xf00000
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x14
+#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000000
+#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x18
+#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x4000000
+#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x1a
+#define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x8000000
+#define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x1b
+#define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS_MASK 0x10000000
+#define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__SHIFT 0x1c
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0xf
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x0
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0xf0
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x4
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0xf00
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x8
+#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000
+#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0xc
+#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x2000
+#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0xd
+#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2_MASK 0x20000
+#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2__SHIFT 0x11
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x1c0000
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x12
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0xe00000
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x15
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x7000000
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x18
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x8000000
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x1b
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x1c
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x1d
+#define PB0_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME_MASK 0x3
+#define PB0_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME__SHIFT 0x0
+#define PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME_MASK 0xc
+#define PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT 0x2
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3_MASK 0x1
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3__SHIFT 0x0
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7_MASK 0x2
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7__SHIFT 0x1
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11_MASK 0x4
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11__SHIFT 0x2
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15_MASK 0x8
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15__SHIFT 0x3
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3_MASK 0x10
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3__SHIFT 0x4
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7_MASK 0x20
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7__SHIFT 0x5
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11_MASK 0x40
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11__SHIFT 0x6
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15_MASK 0x80
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15__SHIFT 0x7
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3_MASK 0x100
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3__SHIFT 0x8
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7_MASK 0x200
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7__SHIFT 0x9
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11_MASK 0x400
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11__SHIFT 0xa
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15_MASK 0x800
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15__SHIFT 0xb
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3_MASK 0x1000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3__SHIFT 0xc
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7_MASK 0x2000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7__SHIFT 0xd
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11_MASK 0x4000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11__SHIFT 0xe
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15_MASK 0x8000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15__SHIFT 0xf
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3_MASK 0x10000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3__SHIFT 0x10
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7_MASK 0x20000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7__SHIFT 0x11
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11_MASK 0x40000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11__SHIFT 0x12
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15_MASK 0x80000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15__SHIFT 0x13
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3_MASK 0x100000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3__SHIFT 0x14
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7_MASK 0x200000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7__SHIFT 0x15
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11_MASK 0x400000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11__SHIFT 0x16
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15_MASK 0x800000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15__SHIFT 0x17
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x1
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x0
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x2
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x1
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x4
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x2
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x8
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x3
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0xc0
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x6
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x100
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x8
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x200
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x9
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x400
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0xa
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x800
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0xb
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x1000
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xc
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x2000
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0xd
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x4000
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0xe
+#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x8000
+#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0xf
+#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x10000
+#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x10
+#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x20000
+#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x11
+#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x40000
+#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x12
+#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x80000
+#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x13
+#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x100000
+#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x14
+#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x200000
+#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x15
+#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x400000
+#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x16
+#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL_MASK 0x800000
+#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL__SHIFT 0x17
+#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN_MASK 0x1000000
+#define PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN__SHIFT 0x18
+#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000
+#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x1c
+#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000
+#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x1d
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x1e
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x1f
+#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x1
+#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x0
+#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x2
+#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x1
+#define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0xff
+#define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x0
+#define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0xc00
+#define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0xa
+#define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x1000
+#define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0xc
+#define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x2000
+#define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0xd
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x7
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x0
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x8
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x3
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0_MASK 0x70
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0__SHIFT 0x4
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x80
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x7
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x100
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x8
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x200
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x9
+#define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0xff
+#define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x0
+#define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0xc00
+#define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0xa
+#define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x1000
+#define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0xc
+#define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x2000
+#define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0xd
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x7
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x0
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x8
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x3
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1_MASK 0x70
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1__SHIFT 0x4
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x80
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x7
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x100
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x8
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x200
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x9
+#define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0xff
+#define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x0
+#define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0xc00
+#define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0xa
+#define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x1000
+#define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0xc
+#define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x2000
+#define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0xd
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x7
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x0
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x8
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x3
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2_MASK 0x70
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2__SHIFT 0x4
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x80
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x7
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x100
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x8
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x200
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x9
+#define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0xff
+#define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x0
+#define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0xc00
+#define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0xa
+#define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x1000
+#define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0xc
+#define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x2000
+#define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0xd
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x7
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x0
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x8
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x3
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3_MASK 0x70
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3__SHIFT 0x4
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x80
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x7
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x100
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x8
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x200
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x9
+#define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0xff
+#define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x0
+#define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0xc00
+#define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0xa
+#define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x1000
+#define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0xc
+#define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x2000
+#define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0xd
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x7
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x0
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x8
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x3
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4_MASK 0x70
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4__SHIFT 0x4
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x80
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x7
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x100
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x8
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x200
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x9
+#define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0xff
+#define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x0
+#define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0xc00
+#define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0xa
+#define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x1000
+#define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0xc
+#define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x2000
+#define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0xd
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x7
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x0
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x8
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x3
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5_MASK 0x70
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5__SHIFT 0x4
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x80
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x7
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x100
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x8
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x200
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x9
+#define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0xff
+#define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x0
+#define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0xc00
+#define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0xa
+#define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x1000
+#define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0xc
+#define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x2000
+#define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0xd
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x7
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x0
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x8
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x3
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6_MASK 0x70
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6__SHIFT 0x4
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x80
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x7
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x100
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x8
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x200
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x9
+#define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0xff
+#define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x0
+#define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0xc00
+#define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0xa
+#define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x1000
+#define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0xc
+#define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x2000
+#define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0xd
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x7
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x0
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x8
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x3
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7_MASK 0x70
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7__SHIFT 0x4
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x80
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x7
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x100
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x8
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x200
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x9
+#define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0xff
+#define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x0
+#define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0xc00
+#define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0xa
+#define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x1000
+#define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0xc
+#define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x2000
+#define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0xd
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x7
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x0
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x8
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x3
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8_MASK 0x70
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8__SHIFT 0x4
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x80
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x7
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x100
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x8
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x200
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x9
+#define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0xff
+#define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x0
+#define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0xc00
+#define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0xa
+#define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x1000
+#define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0xc
+#define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x2000
+#define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0xd
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x7
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x0
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x8
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x3
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9_MASK 0x70
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9__SHIFT 0x4
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x80
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x7
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x100
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x8
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x200
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x9
+#define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0xff
+#define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x0
+#define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0xc00
+#define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0xa
+#define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x1000
+#define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0xc
+#define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x2000
+#define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0xd
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x7
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x0
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x8
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x3
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10_MASK 0x70
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10__SHIFT 0x4
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x80
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x7
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x100
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x8
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x200
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x9
+#define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0xff
+#define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x0
+#define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0xc00
+#define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0xa
+#define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x1000
+#define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0xc
+#define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x2000
+#define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0xd
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x7
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x0
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x8
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x3
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11_MASK 0x70
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11__SHIFT 0x4
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x80
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x7
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x100
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x8
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x200
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x9
+#define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0xff
+#define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x0
+#define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0xc00
+#define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0xa
+#define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x1000
+#define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0xc
+#define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x2000
+#define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0xd
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x7
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x0
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x8
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x3
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12_MASK 0x70
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12__SHIFT 0x4
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x80
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x7
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x100
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x8
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x200
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x9
+#define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0xff
+#define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x0
+#define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0xc00
+#define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0xa
+#define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x1000
+#define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0xc
+#define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x2000
+#define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0xd
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x7
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x0
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x8
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x3
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13_MASK 0x70
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13__SHIFT 0x4
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x80
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x7
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x100
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x8
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x200
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x9
+#define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0xff
+#define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x0
+#define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0xc00
+#define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0xa
+#define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x1000
+#define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0xc
+#define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x2000
+#define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0xd
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x7
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x0
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x8
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x3
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14_MASK 0x70
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14__SHIFT 0x4
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x80
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x7
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x100
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x8
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x200
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x9
+#define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0xff
+#define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x0
+#define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0xc00
+#define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0xa
+#define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x1000
+#define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0xc
+#define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x2000
+#define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0xd
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x7
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x0
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x8
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x3
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15_MASK 0x70
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15__SHIFT 0x4
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x80
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x7
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x100
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x8
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x200
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x9
+#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x7
+#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x0
+#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x38
+#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x3
+#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x700
+#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x8
+#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x3800
+#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0xb
+#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x1c000
+#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0xe
+#define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x60000
+#define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x11
+#define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x80000
+#define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x13
+#define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x100000
+#define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x14
+#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x200000
+#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x15
+#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x400000
+#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x16
+#define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x800000
+#define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x17
+#define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF_MASK 0x1000000
+#define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF__SHIFT 0x18
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x1
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x0
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x2
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x1
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x4
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x2
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x8
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x3
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x10
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x4
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x20
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x5
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x40
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x6
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x80
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x7
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x100
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x8
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x200
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x9
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x400
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0xa
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x800
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0xb
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x1000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0xc
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x2000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0xd
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x4000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0xe
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x8000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0xf
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x10000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x10
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x20000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x11
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x40000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x12
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x80000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x13
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x100000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x14
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x200000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x15
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x400000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x16
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x800000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x17
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x1000000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x18
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x2000000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x19
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x4000000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x1a
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x8000000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x1b
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x1c
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x1d
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x1e
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3_MASK 0x1
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3__SHIFT 0x0
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7_MASK 0x2
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7__SHIFT 0x1
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11_MASK 0x4
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11__SHIFT 0x2
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15_MASK 0x8
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15__SHIFT 0x3
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3_MASK 0x10
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3__SHIFT 0x4
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7_MASK 0x20
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7__SHIFT 0x5
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11_MASK 0x40
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11__SHIFT 0x6
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15_MASK 0x80
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15__SHIFT 0x7
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3_MASK 0x100
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3__SHIFT 0x8
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7_MASK 0x200
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7__SHIFT 0x9
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11_MASK 0x400
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11__SHIFT 0xa
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15_MASK 0x800
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15__SHIFT 0xb
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3_MASK 0x1000
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3__SHIFT 0xc
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7_MASK 0x2000
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7__SHIFT 0xd
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11_MASK 0x4000
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11__SHIFT 0xe
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15_MASK 0x8000
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15__SHIFT 0xf
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x1
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x0
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x2
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x1
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x4
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x2
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x8
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x3
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x10
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x4
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x20
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x5
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x40
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x6
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x80
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x7
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x100
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x8
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x200
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x9
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x400
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0xa
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x800
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0xb
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x1000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0xc
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x2000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0xd
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x4000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0xe
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x8000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0xf
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x10000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x10
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x20000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x11
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x40000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x12
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x80000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x13
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x100000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x14
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x200000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x15
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x400000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x16
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x800000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x17
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x1000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x18
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x2000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x19
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x4000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x1a
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x8000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x1b
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x1c
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x1d
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x1e
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x1f
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x1
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x0
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x2
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x1
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x4
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x2
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x8
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x3
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x10
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x4
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x20
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x5
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x40
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x6
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x80
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x7
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x100
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x8
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x200
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x9
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x400
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0xa
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x800
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0xb
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x1000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0xc
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x2000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0xd
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x4000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0xe
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x8000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0xf
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x10000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x10
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x20000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x11
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x40000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x12
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x80000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x13
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x100000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x14
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x200000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x15
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x400000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x16
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x800000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x17
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x1000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x18
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x2000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x19
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x4000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x1a
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x8000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x1b
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x1c
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x1d
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x1e
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x1f
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x1
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x0
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x2
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x1
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x4
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x2
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x8
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x3
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x10
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x4
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x20
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x5
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x40
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x6
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x80
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x7
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x100
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x8
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x200
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x9
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x400
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0xa
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x800
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0xb
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x1000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0xc
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x2000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0xd
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x4000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0xe
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x8000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0xf
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x10000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x10
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x20000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x11
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x40000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x12
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x80000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x13
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x100000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x14
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x200000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x15
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x400000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x16
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x800000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x17
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x1000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x18
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x2000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x19
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x4000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x1a
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x8000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x1b
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x1c
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x1d
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x1e
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x1f
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x1
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x0
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x2
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x1
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x4
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x2
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x8
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x3
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x10
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x4
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x20
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x5
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x40
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x6
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x80
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x7
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x100
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x8
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x200
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x9
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x400
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0xa
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x800
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0xb
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x1000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0xc
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x2000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0xd
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x7
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x0
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x8
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x3
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0xf0
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x4
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x100
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x8
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1e00
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x9
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x2000
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0xd
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x7c000
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0xe
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x80000
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x13
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1f00000
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x14
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x2000000
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x19
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x1a
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x1e
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0xf
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x0
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x10
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x4
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x20
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x5
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x40
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x6
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x80
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x7
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x100
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x8
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x200
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x9
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x400
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xa
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x800
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0xb
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x1000
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0xc
+#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x2000
+#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0xd
+#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x4000
+#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0xe
+#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x1ff8000
+#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0xf
+#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x2000000
+#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x19
+#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x4000000
+#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x1a
+#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x8000000
+#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x1b
+#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000
+#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x1c
+#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000
+#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x1d
+#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000
+#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x1e
+#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000
+#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x1f
+#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x1
+#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x0
+#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x2
+#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x1
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x4
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x2
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x8
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x3
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x10
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x4
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x20
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x5
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x40
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x6
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x80
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x7
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x100
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x8
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x200
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x9
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x400
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0xa
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x800
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0xb
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0xf000
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0xc
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0000
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x10
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x1f00000
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x14
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x19
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0xf
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x0
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x4
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x100
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x8
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x200
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x9
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x3c00
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0xa
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x3c000
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0xe
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x7c0000
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x12
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf800000
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x17
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x1c
+#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf
+#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0
+#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x10
+#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x4
+#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x20
+#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x5
+#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x1
+#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x0
+#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x2
+#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x1
+#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x4
+#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x2
+#define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x8
+#define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x3
+#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x1
+#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x0
+#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x2
+#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x1
+#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x4
+#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x2
+#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x8
+#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x3
+#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x10
+#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x4
+#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x20
+#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x5
+#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x40
+#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x6
+#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x80
+#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x7
+#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x7
+#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x0
+#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0_MASK 0x8
+#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0__SHIFT 0x3
+#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x70
+#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x4
+#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x80
+#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x7
+#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x300
+#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x8
+#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0xfc00
+#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0xa
+#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x1
+#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x0
+#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x2
+#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x1
+#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x4
+#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x2
+#define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x8
+#define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x3
+#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x1
+#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x0
+#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x2
+#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x1
+#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x4
+#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x2
+#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x8
+#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x3
+#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x10
+#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x4
+#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x20
+#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x5
+#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x40
+#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x6
+#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x80
+#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x7
+#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x7
+#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x0
+#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1_MASK 0x8
+#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1__SHIFT 0x3
+#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x70
+#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x4
+#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x80
+#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x7
+#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x300
+#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x8
+#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0xfc00
+#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0xa
+#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x1
+#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x0
+#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x2
+#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x1
+#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x4
+#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x2
+#define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x8
+#define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x3
+#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x1
+#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x0
+#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x2
+#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x1
+#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x4
+#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x2
+#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x8
+#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x3
+#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x10
+#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x4
+#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x20
+#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x5
+#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x40
+#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x6
+#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x80
+#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x7
+#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x7
+#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x0
+#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2_MASK 0x8
+#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2__SHIFT 0x3
+#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x70
+#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x4
+#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x80
+#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x7
+#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x300
+#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x8
+#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0xfc00
+#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0xa
+#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x1
+#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x0
+#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x2
+#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x1
+#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x4
+#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x2
+#define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x8
+#define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x3
+#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x1
+#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x0
+#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x2
+#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x1
+#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x4
+#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x2
+#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x8
+#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x3
+#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x10
+#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x4
+#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x20
+#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x5
+#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x40
+#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x6
+#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x80
+#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x7
+#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x7
+#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x0
+#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3_MASK 0x8
+#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3__SHIFT 0x3
+#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x70
+#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x4
+#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x80
+#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x7
+#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x300
+#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x8
+#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0xfc00
+#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0xa
+#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x1
+#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x0
+#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x2
+#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x1
+#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x4
+#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x2
+#define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x8
+#define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x3
+#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x1
+#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x0
+#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x2
+#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x1
+#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x4
+#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x2
+#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x8
+#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x3
+#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x10
+#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x4
+#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x20
+#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x5
+#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x40
+#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x6
+#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x80
+#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x7
+#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x7
+#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x0
+#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4_MASK 0x8
+#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4__SHIFT 0x3
+#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x70
+#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x4
+#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x80
+#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x7
+#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x300
+#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x8
+#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0xfc00
+#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0xa
+#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x1
+#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x0
+#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x2
+#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x1
+#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x4
+#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x2
+#define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x8
+#define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x3
+#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x1
+#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x0
+#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x2
+#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x1
+#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x4
+#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x2
+#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x8
+#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x3
+#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x10
+#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x4
+#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x20
+#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x5
+#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x40
+#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x6
+#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x80
+#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x7
+#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x7
+#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x0
+#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5_MASK 0x8
+#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5__SHIFT 0x3
+#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x70
+#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x4
+#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x80
+#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x7
+#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x300
+#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x8
+#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0xfc00
+#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0xa
+#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x1
+#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x0
+#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x2
+#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x1
+#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x4
+#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x2
+#define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x8
+#define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x3
+#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x1
+#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x0
+#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x2
+#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x1
+#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x4
+#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x2
+#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x8
+#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x3
+#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x10
+#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x4
+#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x20
+#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x5
+#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x40
+#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x6
+#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x80
+#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x7
+#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x7
+#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x0
+#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6_MASK 0x8
+#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6__SHIFT 0x3
+#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x70
+#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x4
+#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x80
+#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x7
+#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x300
+#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x8
+#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0xfc00
+#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0xa
+#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x1
+#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x0
+#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x2
+#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x1
+#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x4
+#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x2
+#define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x8
+#define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x3
+#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x1
+#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x0
+#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x2
+#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x1
+#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x4
+#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x2
+#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x8
+#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x3
+#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x10
+#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x4
+#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x20
+#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x5
+#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x40
+#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x6
+#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x80
+#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x7
+#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x7
+#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x0
+#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7_MASK 0x8
+#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7__SHIFT 0x3
+#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x70
+#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x4
+#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x80
+#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x7
+#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x300
+#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x8
+#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0xfc00
+#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0xa
+#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x1
+#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x0
+#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x2
+#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x1
+#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x4
+#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x2
+#define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x8
+#define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x3
+#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x1
+#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x0
+#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x2
+#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x1
+#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x4
+#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x2
+#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x8
+#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x3
+#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x10
+#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x4
+#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x20
+#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x5
+#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x40
+#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x6
+#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x80
+#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x7
+#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x7
+#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x0
+#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8_MASK 0x8
+#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8__SHIFT 0x3
+#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x70
+#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x4
+#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x80
+#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x7
+#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x300
+#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x8
+#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0xfc00
+#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0xa
+#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x1
+#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x0
+#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x2
+#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x1
+#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x4
+#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x2
+#define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x8
+#define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x3
+#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x1
+#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x0
+#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x2
+#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x1
+#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x4
+#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x2
+#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x8
+#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x3
+#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x10
+#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x4
+#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x20
+#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x5
+#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x40
+#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x6
+#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x80
+#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x7
+#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x7
+#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x0
+#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9_MASK 0x8
+#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9__SHIFT 0x3
+#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x70
+#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x4
+#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x80
+#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x7
+#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x300
+#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x8
+#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0xfc00
+#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0xa
+#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x1
+#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x0
+#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x2
+#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x1
+#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x4
+#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x2
+#define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x8
+#define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x3
+#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x1
+#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x0
+#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x2
+#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x1
+#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x4
+#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x2
+#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x8
+#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x3
+#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x10
+#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x4
+#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x20
+#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x5
+#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x40
+#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x6
+#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x80
+#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x7
+#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x7
+#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x0
+#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10_MASK 0x8
+#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10__SHIFT 0x3
+#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x70
+#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x4
+#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x80
+#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x7
+#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x300
+#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x8
+#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0xfc00
+#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0xa
+#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x1
+#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x0
+#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x2
+#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x1
+#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x4
+#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x2
+#define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x8
+#define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x3
+#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x1
+#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x0
+#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x2
+#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x1
+#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x4
+#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x2
+#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x8
+#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x3
+#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x10
+#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x4
+#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x20
+#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x5
+#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x40
+#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x6
+#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x80
+#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x7
+#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x7
+#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x0
+#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11_MASK 0x8
+#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11__SHIFT 0x3
+#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x70
+#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x4
+#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x80
+#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x7
+#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x300
+#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x8
+#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0xfc00
+#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0xa
+#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x1
+#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x0
+#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x2
+#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x1
+#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x4
+#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x2
+#define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x8
+#define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x3
+#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x1
+#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x0
+#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x2
+#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x1
+#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x4
+#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x2
+#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x8
+#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x3
+#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x10
+#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x4
+#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x20
+#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x5
+#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x40
+#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x6
+#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x80
+#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x7
+#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x7
+#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x0
+#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12_MASK 0x8
+#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12__SHIFT 0x3
+#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x70
+#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x4
+#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x80
+#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x7
+#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x300
+#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x8
+#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0xfc00
+#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0xa
+#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x1
+#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x0
+#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x2
+#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x1
+#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x4
+#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x2
+#define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x8
+#define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x3
+#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x1
+#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x0
+#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x2
+#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x1
+#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x4
+#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x2
+#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x8
+#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x3
+#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x10
+#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x4
+#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x20
+#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x5
+#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x40
+#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x6
+#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x80
+#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x7
+#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x7
+#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x0
+#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13_MASK 0x8
+#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13__SHIFT 0x3
+#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x70
+#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x4
+#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x80
+#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x7
+#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x300
+#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x8
+#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0xfc00
+#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0xa
+#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x1
+#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x0
+#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x2
+#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x1
+#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x4
+#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x2
+#define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x8
+#define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x3
+#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x1
+#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x0
+#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x2
+#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x1
+#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x4
+#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x2
+#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x8
+#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x3
+#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x10
+#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x4
+#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x20
+#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x5
+#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x40
+#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x6
+#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x80
+#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x7
+#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x7
+#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x0
+#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14_MASK 0x8
+#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14__SHIFT 0x3
+#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x70
+#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x4
+#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x80
+#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x7
+#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x300
+#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x8
+#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0xfc00
+#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0xa
+#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x1
+#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x0
+#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x2
+#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x1
+#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x4
+#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x2
+#define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x8
+#define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x3
+#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x1
+#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x0
+#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x2
+#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x1
+#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x4
+#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x2
+#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x8
+#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x3
+#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x10
+#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x4
+#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x20
+#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x5
+#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x40
+#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x6
+#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x80
+#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x7
+#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x7
+#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x0
+#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15_MASK 0x8
+#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15__SHIFT 0x3
+#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x70
+#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x4
+#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x80
+#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x7
+#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x300
+#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x8
+#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0xfc00
+#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0xa
+#define PB1_GLB_CTRL_REG0__BACKUP_MASK 0xffff
+#define PB1_GLB_CTRL_REG0__BACKUP__SHIFT 0x0
+#define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x30000
+#define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x10
+#define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x700000
+#define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x14
+#define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x800000
+#define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x17
+#define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x1000000
+#define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x18
+#define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x2000000
+#define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x19
+#define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x4000000
+#define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x1a
+#define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000
+#define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x1e
+#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x1
+#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x0
+#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x7e
+#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x1
+#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x80
+#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x7
+#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x3f00
+#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x8
+#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x4000
+#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0xe
+#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x3f8000
+#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0xf
+#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x400000
+#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x16
+#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000
+#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x17
+#define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000
+#define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x1e
+#define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000
+#define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x1f
+#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x1
+#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x0
+#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0xfe
+#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x1
+#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x100
+#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x8
+#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0xfe00
+#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x9
+#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x10000
+#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x10
+#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0xfe0000
+#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x11
+#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x1000000
+#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x18
+#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000
+#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x19
+#define PB1_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x1f
+#define PB1_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x0
+#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x60
+#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x5
+#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x180
+#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x7
+#define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x600
+#define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x9
+#define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x800
+#define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0xb
+#define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x1000
+#define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0xc
+#define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x1c000
+#define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0xe
+#define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x1c0000
+#define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x12
+#define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x200000
+#define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x15
+#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x400000
+#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x16
+#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x7800000
+#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x17
+#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x8000000
+#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x1b
+#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000
+#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x1c
+#define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000
+#define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x1f
+#define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0xffff
+#define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x0
+#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x30000
+#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x10
+#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x40000
+#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x12
+#define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x3c00000
+#define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x16
+#define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x4000000
+#define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x1a
+#define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x8000000
+#define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x1b
+#define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000
+#define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x1c
+#define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0xff
+#define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x0
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3_MASK 0x1
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3__SHIFT 0x0
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7_MASK 0x2
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7__SHIFT 0x1
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11_MASK 0x4
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11__SHIFT 0x2
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15_MASK 0x8
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15__SHIFT 0x3
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT_MASK 0x10
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT__SHIFT 0x4
+#define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0xf00
+#define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x8
+#define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0xf000
+#define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0xc
+#define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0xf0000
+#define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x10
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x100000
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x14
+#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3_MASK 0x1
+#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3__SHIFT 0x0
+#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3_MASK 0x2
+#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3__SHIFT 0x1
+#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3_MASK 0x4
+#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3__SHIFT 0x2
+#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x1000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0xc
+#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x2000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0xd
+#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x4000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0xe
+#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x8000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0xf
+#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK 0x30000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT 0x10
+#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0xc0000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x12
+#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK 0x300000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_1__SHIFT 0x14
+#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0xc00000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x16
+#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_2_MASK 0x3000000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_2__SHIFT 0x18
+#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0xc000000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x1a
+#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_3_MASK 0x30000000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_3__SHIFT 0x1c
+#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x1e
+#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7_MASK 0x1
+#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7__SHIFT 0x0
+#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7_MASK 0x2
+#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7__SHIFT 0x1
+#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7_MASK 0x4
+#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7__SHIFT 0x2
+#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x1000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0xc
+#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x2000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0xd
+#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x4000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0xe
+#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x8000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0xf
+#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_4_MASK 0x30000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_4__SHIFT 0x10
+#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0xc0000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x12
+#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK 0x300000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5__SHIFT 0x14
+#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0xc00000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x16
+#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_6_MASK 0x3000000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_6__SHIFT 0x18
+#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0xc000000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x1a
+#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_7_MASK 0x30000000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_7__SHIFT 0x1c
+#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x1e
+#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11_MASK 0x1
+#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11__SHIFT 0x0
+#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11_MASK 0x2
+#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11__SHIFT 0x1
+#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11_MASK 0x4
+#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11__SHIFT 0x2
+#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x1000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0xc
+#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x2000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0xd
+#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x4000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0xe
+#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x8000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0xf
+#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_8_MASK 0x30000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_8__SHIFT 0x10
+#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0xc0000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x12
+#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_9_MASK 0x300000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_9__SHIFT 0x14
+#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0xc00000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x16
+#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10_MASK 0x3000000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT 0x18
+#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0xc000000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x1a
+#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_11_MASK 0x30000000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_11__SHIFT 0x1c
+#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x1e
+#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15_MASK 0x1
+#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15__SHIFT 0x0
+#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15_MASK 0x2
+#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15__SHIFT 0x1
+#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15_MASK 0x4
+#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15__SHIFT 0x2
+#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x1000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0xc
+#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x2000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0xd
+#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x4000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0xe
+#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x8000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0xf
+#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_12_MASK 0x30000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_12__SHIFT 0x10
+#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0xc0000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x12
+#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_13_MASK 0x300000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_13__SHIFT 0x14
+#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0xc00000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x16
+#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_14_MASK 0x3000000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_14__SHIFT 0x18
+#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0xc000000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x1a
+#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_15_MASK 0x30000000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__MODE_15__SHIFT 0x1c
+#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x1e
+#define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0xffff
+#define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x0
+#define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000
+#define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x10
+#define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x1
+#define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x0
+#define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x2
+#define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x1
+#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x4
+#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x2
+#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x8
+#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x3
+#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x8000
+#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0xf
+#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000
+#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x10
+#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x1
+#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x0
+#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x2
+#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x1
+#define PB1_HW_DEBUG__PB1_HW_00_DEBUG_MASK 0x1
+#define PB1_HW_DEBUG__PB1_HW_00_DEBUG__SHIFT 0x0
+#define PB1_HW_DEBUG__PB1_HW_01_DEBUG_MASK 0x2
+#define PB1_HW_DEBUG__PB1_HW_01_DEBUG__SHIFT 0x1
+#define PB1_HW_DEBUG__PB1_HW_02_DEBUG_MASK 0x4
+#define PB1_HW_DEBUG__PB1_HW_02_DEBUG__SHIFT 0x2
+#define PB1_HW_DEBUG__PB1_HW_03_DEBUG_MASK 0x8
+#define PB1_HW_DEBUG__PB1_HW_03_DEBUG__SHIFT 0x3
+#define PB1_HW_DEBUG__PB1_HW_04_DEBUG_MASK 0x10
+#define PB1_HW_DEBUG__PB1_HW_04_DEBUG__SHIFT 0x4
+#define PB1_HW_DEBUG__PB1_HW_05_DEBUG_MASK 0x20
+#define PB1_HW_DEBUG__PB1_HW_05_DEBUG__SHIFT 0x5
+#define PB1_HW_DEBUG__PB1_HW_06_DEBUG_MASK 0x40
+#define PB1_HW_DEBUG__PB1_HW_06_DEBUG__SHIFT 0x6
+#define PB1_HW_DEBUG__PB1_HW_07_DEBUG_MASK 0x80
+#define PB1_HW_DEBUG__PB1_HW_07_DEBUG__SHIFT 0x7
+#define PB1_HW_DEBUG__PB1_HW_08_DEBUG_MASK 0x100
+#define PB1_HW_DEBUG__PB1_HW_08_DEBUG__SHIFT 0x8
+#define PB1_HW_DEBUG__PB1_HW_09_DEBUG_MASK 0x200
+#define PB1_HW_DEBUG__PB1_HW_09_DEBUG__SHIFT 0x9
+#define PB1_HW_DEBUG__PB1_HW_10_DEBUG_MASK 0x400
+#define PB1_HW_DEBUG__PB1_HW_10_DEBUG__SHIFT 0xa
+#define PB1_HW_DEBUG__PB1_HW_11_DEBUG_MASK 0x800
+#define PB1_HW_DEBUG__PB1_HW_11_DEBUG__SHIFT 0xb
+#define PB1_HW_DEBUG__PB1_HW_12_DEBUG_MASK 0x1000
+#define PB1_HW_DEBUG__PB1_HW_12_DEBUG__SHIFT 0xc
+#define PB1_HW_DEBUG__PB1_HW_13_DEBUG_MASK 0x2000
+#define PB1_HW_DEBUG__PB1_HW_13_DEBUG__SHIFT 0xd
+#define PB1_HW_DEBUG__PB1_HW_14_DEBUG_MASK 0x4000
+#define PB1_HW_DEBUG__PB1_HW_14_DEBUG__SHIFT 0xe
+#define PB1_HW_DEBUG__PB1_HW_15_DEBUG_MASK 0x8000
+#define PB1_HW_DEBUG__PB1_HW_15_DEBUG__SHIFT 0xf
+#define PB1_HW_DEBUG__PB1_HW_16_DEBUG_MASK 0x10000
+#define PB1_HW_DEBUG__PB1_HW_16_DEBUG__SHIFT 0x10
+#define PB1_HW_DEBUG__PB1_HW_17_DEBUG_MASK 0x20000
+#define PB1_HW_DEBUG__PB1_HW_17_DEBUG__SHIFT 0x11
+#define PB1_HW_DEBUG__PB1_HW_18_DEBUG_MASK 0x40000
+#define PB1_HW_DEBUG__PB1_HW_18_DEBUG__SHIFT 0x12
+#define PB1_HW_DEBUG__PB1_HW_19_DEBUG_MASK 0x80000
+#define PB1_HW_DEBUG__PB1_HW_19_DEBUG__SHIFT 0x13
+#define PB1_HW_DEBUG__PB1_HW_20_DEBUG_MASK 0x100000
+#define PB1_HW_DEBUG__PB1_HW_20_DEBUG__SHIFT 0x14
+#define PB1_HW_DEBUG__PB1_HW_21_DEBUG_MASK 0x200000
+#define PB1_HW_DEBUG__PB1_HW_21_DEBUG__SHIFT 0x15
+#define PB1_HW_DEBUG__PB1_HW_22_DEBUG_MASK 0x400000
+#define PB1_HW_DEBUG__PB1_HW_22_DEBUG__SHIFT 0x16
+#define PB1_HW_DEBUG__PB1_HW_23_DEBUG_MASK 0x800000
+#define PB1_HW_DEBUG__PB1_HW_23_DEBUG__SHIFT 0x17
+#define PB1_HW_DEBUG__PB1_HW_24_DEBUG_MASK 0x1000000
+#define PB1_HW_DEBUG__PB1_HW_24_DEBUG__SHIFT 0x18
+#define PB1_HW_DEBUG__PB1_HW_25_DEBUG_MASK 0x2000000
+#define PB1_HW_DEBUG__PB1_HW_25_DEBUG__SHIFT 0x19
+#define PB1_HW_DEBUG__PB1_HW_26_DEBUG_MASK 0x4000000
+#define PB1_HW_DEBUG__PB1_HW_26_DEBUG__SHIFT 0x1a
+#define PB1_HW_DEBUG__PB1_HW_27_DEBUG_MASK 0x8000000
+#define PB1_HW_DEBUG__PB1_HW_27_DEBUG__SHIFT 0x1b
+#define PB1_HW_DEBUG__PB1_HW_28_DEBUG_MASK 0x10000000
+#define PB1_HW_DEBUG__PB1_HW_28_DEBUG__SHIFT 0x1c
+#define PB1_HW_DEBUG__PB1_HW_29_DEBUG_MASK 0x20000000
+#define PB1_HW_DEBUG__PB1_HW_29_DEBUG__SHIFT 0x1d
+#define PB1_HW_DEBUG__PB1_HW_30_DEBUG_MASK 0x40000000
+#define PB1_HW_DEBUG__PB1_HW_30_DEBUG__SHIFT 0x1e
+#define PB1_HW_DEBUG__PB1_HW_31_DEBUG_MASK 0x80000000
+#define PB1_HW_DEBUG__PB1_HW_31_DEBUG__SHIFT 0x1f
+#define PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK 0x2
+#define PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START__SHIFT 0x1
+#define PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL_MASK 0x4
+#define PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT 0x2
+#define PB1_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS_MASK 0x8
+#define PB1_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS__SHIFT 0x3
+#define PB1_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH_MASK 0x60
+#define PB1_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH__SHIFT 0x5
+#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL_MASK 0xf80
+#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL__SHIFT 0x7
+#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF_MASK 0x1000
+#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF__SHIFT 0xc
+#define PB1_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0__MASK 0x2000
+#define PB1_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0___SHIFT 0xd
+#define PB1_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD_MASK 0x4000
+#define PB1_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD__SHIFT 0xe
+#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x8000
+#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0xf
+#define PB1_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE_MASK 0xf0000
+#define PB1_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE__SHIFT 0x10
+#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE_MASK 0x100000
+#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE__SHIFT 0x14
+#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL_MASK 0x1e00000
+#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x15
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN_MASK 0x1e
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN__SHIFT 0x1
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL_MASK 0x1e0
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL__SHIFT 0x5
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN_MASK 0x3e00
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN__SHIFT 0x9
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL_MASK 0x7c000
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL__SHIFT 0xe
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN_MASK 0x780000
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN__SHIFT 0x13
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL_MASK 0x7800000
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL__SHIFT 0x17
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN_MASK 0x8000000
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN__SHIFT 0x1b
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL_MASK 0x10000000
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL__SHIFT 0x1c
+#define PB1_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1__MASK 0x20000000
+#define PB1_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT 0x1d
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN_MASK 0x40000000
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN__SHIFT 0x1e
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN_MASK 0x1e
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN__SHIFT 0x1
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE_MASK 0x20
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE__SHIFT 0x5
+#define PB1_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN_MASK 0x40
+#define PB1_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x6
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS_MASK 0x80
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS__SHIFT 0x7
+#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL_MASK 0x300
+#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x8
+#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL_MASK 0xc00
+#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL__SHIFT 0xa
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME_MASK 0xf000
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME__SHIFT 0xc
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME_MASK 0xf0000
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME__SHIFT 0x10
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME_MASK 0xf00000
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME__SHIFT 0x14
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME_MASK 0xf000000
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME__SHIFT 0x18
+#define PB1_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL_MASK 0x70000000
+#define PB1_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL__SHIFT 0x1c
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE_MASK 0x80000000
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE__SHIFT 0x1f
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK 0x2
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ__SHIFT 0x1
+#define PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG_MASK 0x1c
+#define PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT 0x2
+#define PB1_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL_MASK 0x60
+#define PB1_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL__SHIFT 0x5
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS_MASK 0x80
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS__SHIFT 0x7
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL_MASK 0x700
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL__SHIFT 0x8
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN_MASK 0x7800
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN__SHIFT 0xb
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE_MASK 0x1ff8000
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE__SHIFT 0xf
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME_MASK 0x1e000000
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT 0x19
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN_MASK 0x60000000
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN__SHIFT 0x1d
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS_MASK 0x80000000
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS__SHIFT 0x1f
+#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL_MASK 0xe
+#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL__SHIFT 0x1
+#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL_MASK 0x1ff0
+#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL__SHIFT 0x4
+#define PB1_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF_MASK 0x2000
+#define PB1_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF__SHIFT 0xd
+#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS_MASK 0x8000
+#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS__SHIFT 0xf
+#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL_MASK 0xff0000
+#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL__SHIFT 0x10
+#define PB1_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL_MASK 0x1000000
+#define PB1_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL__SHIFT 0x18
+#define PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK 0x2
+#define PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN__SHIFT 0x1
+#define PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING_MASK 0x4
+#define PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT 0x2
+#define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x3f
+#define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x0
+#define PB1_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR_MASK 0x80
+#define PB1_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR__SHIFT 0x7
+#define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0xf00
+#define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x8
+#define PB1_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN_MASK 0x100000
+#define PB1_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN__SHIFT 0x14
+#define PB1_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY_MASK 0x200000
+#define PB1_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY__SHIFT 0x15
+#define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x400000
+#define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x16
+#define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x800000
+#define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x17
+#define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000
+#define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x18
+#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0xff
+#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x0
+#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x100
+#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x8
+#define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x10000
+#define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x10
+#define PB1_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS_MASK 0xe0000
+#define PB1_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS__SHIFT 0x11
+#define PB1_DFT_JIT_INJ_REG1__DFT_CHECK_TIME_MASK 0xf00000
+#define PB1_DFT_JIT_INJ_REG1__DFT_CHECK_TIME__SHIFT 0x14
+#define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0xffff
+#define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x0
+#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x1
+#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x0
+#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x3e
+#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x1
+#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR_MASK 0xff
+#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR__SHIFT 0x0
+#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR_MASK 0xff00
+#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR__SHIFT 0x8
+#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED_MASK 0x10000
+#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED__SHIFT 0x10
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x1
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x0
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x2
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x1
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x4
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x2
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x8
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x3
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x10
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x4
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x20
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x5
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x40
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x6
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x80
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x7
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x100
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x8
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x200
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x9
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x400
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0xa
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x800
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0xb
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x1000
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0xc
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x2000
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0xd
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x4000
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0xe
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x10000
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x10
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x20000
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x11
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x40000
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x12
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x80000
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x13
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK 0x100000
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT 0x14
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK 0x200000
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT 0x15
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK 0x400000
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT 0x16
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK 0x800000
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT 0x17
+#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x3
+#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x0
+#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x4
+#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x2
+#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x8
+#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x3
+#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x7f0
+#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x4
+#define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x800
+#define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0xb
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0xff
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x100
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x8
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0xe00
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x9
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x1000
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0xc
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x2000
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0xd
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x4000
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0xe
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0xfff8000
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0xf
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x1c
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x1e
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x1f
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x1f
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x0
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x20
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x5
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0xc0
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x6
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x100
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x8
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x200
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x9
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x400
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0xa
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x800
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0xb
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x1000
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0xc
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x2000
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0xd
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x4000
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0xe
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x380000
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x13
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x400000
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x16
+#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
+#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
+#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
+#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
+#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x70
+#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x4
+#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE_MASK 0x300
+#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE__SHIFT 0x8
+#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
+#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
+#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
+#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
+#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x70
+#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x4
+#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE_MASK 0x300
+#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE__SHIFT 0x8
+#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
+#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
+#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
+#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
+#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x70
+#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x4
+#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE_MASK 0x300
+#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE__SHIFT 0x8
+#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
+#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
+#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
+#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
+#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x70
+#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x4
+#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE_MASK 0x300
+#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE__SHIFT 0x8
+#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x3
+#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x0
+#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x4
+#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x2
+#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x8
+#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x3
+#define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x10
+#define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x4
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x7
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x8
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x3
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x70
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x4
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x80
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x7
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x100
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x8
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x200
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x9
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x3fc00
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0xa
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x40000
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x12
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0xff80000
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x13
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x1c
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x1d
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x1f
+#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x7
+#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x0
+#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x8
+#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x3
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x10
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x4
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x20
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x5
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x40
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x6
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x80
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x7
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x100
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x8
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x200
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x9
+#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x3c000
+#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0xe
+#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x40000
+#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x12
+#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
+#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
+#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
+#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
+#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x70
+#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x4
+#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE_MASK 0x300
+#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE__SHIFT 0x8
+#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
+#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
+#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
+#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
+#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x70
+#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x4
+#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE_MASK 0x300
+#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE__SHIFT 0x8
+#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
+#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
+#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
+#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
+#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x70
+#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x4
+#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE_MASK 0x300
+#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE__SHIFT 0x8
+#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT_MASK 0x1
+#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT__SHIFT 0x0
+#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT_MASK 0x2
+#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT__SHIFT 0x1
+#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x70
+#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x4
+#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE_MASK 0x300
+#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE__SHIFT 0x8
+#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x3ff
+#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x0
+#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0xffc00
+#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0xa
+#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000
+#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x14
+#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE_MASK 0xc0000000
+#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE__SHIFT 0x1e
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0xf
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x0
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0xf0
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x4
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0xf00
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x8
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0xf000
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0xc
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0xf0000
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x10
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0xf00000
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x14
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x1000000
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x18
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x2000000
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x19
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x4000000
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x1a
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x8000000
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x1b
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x1c
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x1d
+#define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000
+#define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x1e
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0xf000
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0xc
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0xf0000
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x10
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0xf00000
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x14
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x3000000
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x18
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0xc000000
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x1a
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x1c
+#define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000
+#define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x1e
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x1
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x0
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x2
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x1
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x4
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x2
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0xf00000
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x14
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0xf000000
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x18
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x1c
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x7
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x0
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x38
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x3
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x1c0
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x6
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0xe00
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x9
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x7000
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0xc
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x38000
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0xf
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0xf00000
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x14
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0xf000000
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x18
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x1c
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x1f
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x0
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x3e0
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x5
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x7c00
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0xa
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x8000
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0xf
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x10000
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x10
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x20000
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x11
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x40000
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x12
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x80000
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x13
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x100000
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x14
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x8000000
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x1b
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x1c
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x1d
+#define PB1_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0_MASK 0x40000000
+#define PB1_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0__SHIFT 0x1e
+#define PB1_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE_MASK 0x80000000
+#define PB1_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE__SHIFT 0x1f
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0xf
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x0
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0xf0
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x4
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0xf00
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x8
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0xf000
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0xc
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0xf0000
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x10
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0xf00000
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x14
+#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000000
+#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x18
+#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x4000000
+#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x1a
+#define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x8000000
+#define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x1b
+#define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS_MASK 0x10000000
+#define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__SHIFT 0x1c
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0xf
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x0
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0xf0
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x4
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0xf00
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x8
+#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000
+#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0xc
+#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x2000
+#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0xd
+#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2_MASK 0x20000
+#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2__SHIFT 0x11
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x1c0000
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x12
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0xe00000
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x15
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x7000000
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x18
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x8000000
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x1b
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x1c
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x1d
+#define PB1_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME_MASK 0x3
+#define PB1_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME__SHIFT 0x0
+#define PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME_MASK 0xc
+#define PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT 0x2
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3_MASK 0x1
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3__SHIFT 0x0
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7_MASK 0x2
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7__SHIFT 0x1
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11_MASK 0x4
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11__SHIFT 0x2
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15_MASK 0x8
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15__SHIFT 0x3
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3_MASK 0x10
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3__SHIFT 0x4
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7_MASK 0x20
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7__SHIFT 0x5
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11_MASK 0x40
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11__SHIFT 0x6
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15_MASK 0x80
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15__SHIFT 0x7
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3_MASK 0x100
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3__SHIFT 0x8
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7_MASK 0x200
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7__SHIFT 0x9
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11_MASK 0x400
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11__SHIFT 0xa
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15_MASK 0x800
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15__SHIFT 0xb
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3_MASK 0x1000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3__SHIFT 0xc
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7_MASK 0x2000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7__SHIFT 0xd
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11_MASK 0x4000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11__SHIFT 0xe
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15_MASK 0x8000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15__SHIFT 0xf
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3_MASK 0x10000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3__SHIFT 0x10
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7_MASK 0x20000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7__SHIFT 0x11
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11_MASK 0x40000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11__SHIFT 0x12
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15_MASK 0x80000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15__SHIFT 0x13
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3_MASK 0x100000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3__SHIFT 0x14
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7_MASK 0x200000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7__SHIFT 0x15
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11_MASK 0x400000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11__SHIFT 0x16
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15_MASK 0x800000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15__SHIFT 0x17
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x1
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x0
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x2
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x1
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x4
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x2
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x8
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x3
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0xc0
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x6
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x100
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x8
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x200
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x9
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x400
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0xa
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x800
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0xb
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x1000
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xc
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x2000
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0xd
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x4000
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0xe
+#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x8000
+#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0xf
+#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x10000
+#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x10
+#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x20000
+#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x11
+#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x40000
+#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x12
+#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x80000
+#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x13
+#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x100000
+#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x14
+#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x200000
+#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x15
+#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x400000
+#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x16
+#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL_MASK 0x800000
+#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL__SHIFT 0x17
+#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN_MASK 0x1000000
+#define PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN__SHIFT 0x18
+#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000
+#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x1c
+#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000
+#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x1d
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x1e
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x1f
+#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x1
+#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x0
+#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x2
+#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x1
+#define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0xff
+#define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x0
+#define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0xc00
+#define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0xa
+#define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x1000
+#define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0xc
+#define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x2000
+#define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0xd
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x7
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x0
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x8
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x3
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0_MASK 0x70
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0__SHIFT 0x4
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x80
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x7
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x100
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x8
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x200
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x9
+#define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0xff
+#define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x0
+#define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0xc00
+#define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0xa
+#define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x1000
+#define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0xc
+#define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x2000
+#define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0xd
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x7
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x0
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x8
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x3
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1_MASK 0x70
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1__SHIFT 0x4
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x80
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x7
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x100
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x8
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x200
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x9
+#define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0xff
+#define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x0
+#define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0xc00
+#define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0xa
+#define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x1000
+#define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0xc
+#define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x2000
+#define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0xd
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x7
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x0
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x8
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x3
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2_MASK 0x70
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2__SHIFT 0x4
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x80
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x7
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x100
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x8
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x200
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x9
+#define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0xff
+#define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x0
+#define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0xc00
+#define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0xa
+#define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x1000
+#define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0xc
+#define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x2000
+#define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0xd
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x7
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x0
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x8
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x3
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3_MASK 0x70
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3__SHIFT 0x4
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x80
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x7
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x100
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x8
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x200
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x9
+#define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0xff
+#define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x0
+#define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0xc00
+#define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0xa
+#define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x1000
+#define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0xc
+#define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x2000
+#define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0xd
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x7
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x0
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x8
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x3
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4_MASK 0x70
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4__SHIFT 0x4
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x80
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x7
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x100
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x8
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x200
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x9
+#define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0xff
+#define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x0
+#define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0xc00
+#define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0xa
+#define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x1000
+#define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0xc
+#define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x2000
+#define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0xd
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x7
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x0
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x8
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x3
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5_MASK 0x70
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5__SHIFT 0x4
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x80
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x7
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x100
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x8
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x200
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x9
+#define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0xff
+#define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x0
+#define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0xc00
+#define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0xa
+#define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x1000
+#define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0xc
+#define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x2000
+#define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0xd
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x7
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x0
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x8
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x3
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6_MASK 0x70
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6__SHIFT 0x4
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x80
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x7
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x100
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x8
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x200
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x9
+#define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0xff
+#define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x0
+#define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0xc00
+#define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0xa
+#define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x1000
+#define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0xc
+#define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x2000
+#define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0xd
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x7
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x0
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x8
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x3
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7_MASK 0x70
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7__SHIFT 0x4
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x80
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x7
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x100
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x8
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x200
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x9
+#define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0xff
+#define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x0
+#define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0xc00
+#define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0xa
+#define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x1000
+#define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0xc
+#define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x2000
+#define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0xd
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x7
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x0
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x8
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x3
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8_MASK 0x70
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8__SHIFT 0x4
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x80
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x7
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x100
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x8
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x200
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x9
+#define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0xff
+#define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x0
+#define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0xc00
+#define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0xa
+#define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x1000
+#define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0xc
+#define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x2000
+#define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0xd
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x7
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x0
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x8
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x3
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9_MASK 0x70
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9__SHIFT 0x4
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x80
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x7
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x100
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x8
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x200
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x9
+#define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0xff
+#define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x0
+#define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0xc00
+#define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0xa
+#define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x1000
+#define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0xc
+#define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x2000
+#define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0xd
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x7
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x0
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x8
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x3
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10_MASK 0x70
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10__SHIFT 0x4
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x80
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x7
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x100
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x8
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x200
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x9
+#define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0xff
+#define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x0
+#define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0xc00
+#define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0xa
+#define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x1000
+#define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0xc
+#define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x2000
+#define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0xd
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x7
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x0
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x8
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x3
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11_MASK 0x70
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11__SHIFT 0x4
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x80
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x7
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x100
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x8
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x200
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x9
+#define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0xff
+#define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x0
+#define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0xc00
+#define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0xa
+#define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x1000
+#define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0xc
+#define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x2000
+#define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0xd
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x7
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x0
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x8
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x3
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12_MASK 0x70
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12__SHIFT 0x4
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x80
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x7
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x100
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x8
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x200
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x9
+#define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0xff
+#define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x0
+#define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0xc00
+#define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0xa
+#define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x1000
+#define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0xc
+#define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x2000
+#define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0xd
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x7
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x0
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x8
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x3
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13_MASK 0x70
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13__SHIFT 0x4
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x80
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x7
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x100
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x8
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x200
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x9
+#define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0xff
+#define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x0
+#define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0xc00
+#define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0xa
+#define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x1000
+#define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0xc
+#define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x2000
+#define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0xd
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x7
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x0
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x8
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x3
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14_MASK 0x70
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14__SHIFT 0x4
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x80
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x7
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x100
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x8
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x200
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x9
+#define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0xff
+#define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x0
+#define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0xc00
+#define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0xa
+#define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x1000
+#define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0xc
+#define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x2000
+#define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0xd
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x7
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x0
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x8
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x3
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15_MASK 0x70
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15__SHIFT 0x4
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x80
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x7
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x100
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x8
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x200
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x9
+#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x7
+#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x0
+#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x38
+#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x3
+#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x700
+#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x8
+#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x3800
+#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0xb
+#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x1c000
+#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0xe
+#define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x60000
+#define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x11
+#define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x80000
+#define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x13
+#define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x100000
+#define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x14
+#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x200000
+#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x15
+#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x400000
+#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x16
+#define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x800000
+#define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x17
+#define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF_MASK 0x1000000
+#define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF__SHIFT 0x18
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x1
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x0
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x2
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x1
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x4
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x2
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x8
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x3
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x10
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x4
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x20
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x5
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x40
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x6
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x80
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x7
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x100
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x8
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x200
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x9
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x400
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0xa
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x800
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0xb
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x1000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0xc
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x2000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0xd
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x4000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0xe
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x8000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0xf
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x10000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x10
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x20000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x11
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x40000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x12
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x80000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x13
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x100000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x14
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x200000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x15
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x400000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x16
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x800000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x17
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x1000000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x18
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x2000000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x19
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x4000000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x1a
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x8000000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x1b
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x1c
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x1d
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x1e
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3_MASK 0x1
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3__SHIFT 0x0
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7_MASK 0x2
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7__SHIFT 0x1
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11_MASK 0x4
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11__SHIFT 0x2
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15_MASK 0x8
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15__SHIFT 0x3
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3_MASK 0x10
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3__SHIFT 0x4
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7_MASK 0x20
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7__SHIFT 0x5
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11_MASK 0x40
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11__SHIFT 0x6
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15_MASK 0x80
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15__SHIFT 0x7
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3_MASK 0x100
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3__SHIFT 0x8
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7_MASK 0x200
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7__SHIFT 0x9
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11_MASK 0x400
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11__SHIFT 0xa
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15_MASK 0x800
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15__SHIFT 0xb
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3_MASK 0x1000
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3__SHIFT 0xc
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7_MASK 0x2000
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7__SHIFT 0xd
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11_MASK 0x4000
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11__SHIFT 0xe
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15_MASK 0x8000
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15__SHIFT 0xf
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x1
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x0
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x2
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x1
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x4
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x2
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x8
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x3
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x10
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x4
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x20
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x5
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x40
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x6
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x80
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x7
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x100
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x8
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x200
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x9
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x400
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0xa
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x800
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0xb
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x1000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0xc
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x2000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0xd
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x4000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0xe
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x8000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0xf
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x10000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x10
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x20000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x11
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x40000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x12
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x80000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x13
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x100000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x14
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x200000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x15
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x400000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x16
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x800000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x17
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x1000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x18
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x2000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x19
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x4000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x1a
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x8000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x1b
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x1c
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x1d
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x1e
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x1f
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x1
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x0
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x2
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x1
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x4
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x2
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x8
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x3
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x10
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x4
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x20
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x5
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x40
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x6
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x80
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x7
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x100
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x8
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x200
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x9
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x400
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0xa
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x800
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0xb
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x1000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0xc
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x2000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0xd
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x4000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0xe
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x8000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0xf
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x10000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x10
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x20000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x11
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x40000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x12
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x80000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x13
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x100000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x14
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x200000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x15
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x400000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x16
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x800000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x17
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x1000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x18
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x2000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x19
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x4000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x1a
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x8000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x1b
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x1c
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x1d
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x1e
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x1f
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x1
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x0
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x2
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x1
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x4
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x2
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x8
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x3
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x10
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x4
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x20
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x5
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x40
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x6
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x80
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x7
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x100
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x8
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x200
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x9
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x400
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0xa
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x800
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0xb
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x1000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0xc
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x2000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0xd
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x4000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0xe
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x8000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0xf
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x10000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x10
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x20000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x11
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x40000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x12
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x80000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x13
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x100000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x14
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x200000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x15
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x400000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x16
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x800000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x17
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x1000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x18
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x2000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x19
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x4000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x1a
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x8000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x1b
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x1c
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x1d
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x1e
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x1f
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x1
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x0
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x2
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x1
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x4
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x2
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x8
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x3
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x10
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x4
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x20
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x5
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x40
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x6
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x80
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x7
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x100
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x8
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x200
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x9
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x400
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0xa
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x800
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0xb
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x1000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0xc
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x2000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0xd
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x7
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x0
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x8
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x3
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0xf0
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x4
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x100
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x8
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1e00
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x9
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x2000
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0xd
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x7c000
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0xe
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x80000
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x13
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1f00000
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x14
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x2000000
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x19
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x1a
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x1e
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0xf
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x0
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x10
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x4
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x20
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x5
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x40
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x6
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x80
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x7
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x100
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x8
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x200
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x9
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x400
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xa
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x800
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0xb
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x1000
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0xc
+#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x2000
+#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0xd
+#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x4000
+#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0xe
+#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x1ff8000
+#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0xf
+#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x2000000
+#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x19
+#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x4000000
+#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x1a
+#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x8000000
+#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x1b
+#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000
+#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x1c
+#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000
+#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x1d
+#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000
+#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x1e
+#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000
+#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x1f
+#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x1
+#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x0
+#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x2
+#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x1
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x4
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x2
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x8
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x3
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x10
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x4
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x20
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x5
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x40
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x6
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x80
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x7
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x100
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x8
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x200
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x9
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x400
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0xa
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x800
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0xb
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0xf000
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0xc
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0000
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x10
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x1f00000
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x14
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x19
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0xf
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x0
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x4
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x100
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x8
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x200
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x9
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x3c00
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0xa
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x3c000
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0xe
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x7c0000
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x12
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf800000
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x17
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x1c
+#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf
+#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0
+#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x10
+#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x4
+#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x20
+#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x5
+#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x1
+#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x0
+#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x2
+#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x1
+#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x4
+#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x2
+#define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x8
+#define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x3
+#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x1
+#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x0
+#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x2
+#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x1
+#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x4
+#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x2
+#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x8
+#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x3
+#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x10
+#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x4
+#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x20
+#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x5
+#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x40
+#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x6
+#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x80
+#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x7
+#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x7
+#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x0
+#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0_MASK 0x8
+#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0__SHIFT 0x3
+#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x70
+#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x4
+#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x80
+#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x7
+#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x300
+#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x8
+#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0xfc00
+#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0xa
+#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x1
+#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x0
+#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x2
+#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x1
+#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x4
+#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x2
+#define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x8
+#define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x3
+#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x1
+#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x0
+#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x2
+#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x1
+#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x4
+#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x2
+#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x8
+#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x3
+#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x10
+#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x4
+#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x20
+#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x5
+#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x40
+#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x6
+#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x80
+#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x7
+#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x7
+#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x0
+#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1_MASK 0x8
+#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1__SHIFT 0x3
+#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x70
+#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x4
+#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x80
+#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x7
+#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x300
+#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x8
+#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0xfc00
+#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0xa
+#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x1
+#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x0
+#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x2
+#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x1
+#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x4
+#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x2
+#define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x8
+#define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x3
+#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x1
+#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x0
+#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x2
+#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x1
+#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x4
+#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x2
+#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x8
+#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x3
+#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x10
+#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x4
+#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x20
+#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x5
+#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x40
+#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x6
+#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x80
+#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x7
+#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x7
+#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x0
+#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2_MASK 0x8
+#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2__SHIFT 0x3
+#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x70
+#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x4
+#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x80
+#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x7
+#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x300
+#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x8
+#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0xfc00
+#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0xa
+#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x1
+#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x0
+#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x2
+#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x1
+#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x4
+#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x2
+#define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x8
+#define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x3
+#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x1
+#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x0
+#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x2
+#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x1
+#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x4
+#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x2
+#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x8
+#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x3
+#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x10
+#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x4
+#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x20
+#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x5
+#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x40
+#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x6
+#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x80
+#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x7
+#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x7
+#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x0
+#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3_MASK 0x8
+#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3__SHIFT 0x3
+#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x70
+#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x4
+#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x80
+#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x7
+#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x300
+#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x8
+#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0xfc00
+#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0xa
+#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x1
+#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x0
+#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x2
+#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x1
+#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x4
+#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x2
+#define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x8
+#define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x3
+#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x1
+#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x0
+#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x2
+#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x1
+#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x4
+#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x2
+#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x8
+#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x3
+#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x10
+#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x4
+#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x20
+#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x5
+#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x40
+#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x6
+#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x80
+#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x7
+#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x7
+#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x0
+#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4_MASK 0x8
+#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4__SHIFT 0x3
+#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x70
+#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x4
+#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x80
+#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x7
+#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x300
+#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x8
+#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0xfc00
+#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0xa
+#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x1
+#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x0
+#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x2
+#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x1
+#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x4
+#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x2
+#define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x8
+#define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x3
+#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x1
+#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x0
+#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x2
+#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x1
+#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x4
+#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x2
+#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x8
+#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x3
+#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x10
+#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x4
+#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x20
+#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x5
+#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x40
+#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x6
+#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x80
+#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x7
+#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x7
+#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x0
+#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5_MASK 0x8
+#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5__SHIFT 0x3
+#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x70
+#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x4
+#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x80
+#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x7
+#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x300
+#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x8
+#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0xfc00
+#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0xa
+#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x1
+#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x0
+#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x2
+#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x1
+#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x4
+#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x2
+#define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x8
+#define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x3
+#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x1
+#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x0
+#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x2
+#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x1
+#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x4
+#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x2
+#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x8
+#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x3
+#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x10
+#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x4
+#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x20
+#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x5
+#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x40
+#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x6
+#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x80
+#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x7
+#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x7
+#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x0
+#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6_MASK 0x8
+#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6__SHIFT 0x3
+#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x70
+#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x4
+#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x80
+#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x7
+#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x300
+#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x8
+#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0xfc00
+#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0xa
+#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x1
+#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x0
+#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x2
+#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x1
+#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x4
+#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x2
+#define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x8
+#define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x3
+#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x1
+#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x0
+#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x2
+#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x1
+#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x4
+#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x2
+#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x8
+#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x3
+#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x10
+#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x4
+#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x20
+#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x5
+#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x40
+#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x6
+#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x80
+#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x7
+#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x7
+#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x0
+#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7_MASK 0x8
+#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7__SHIFT 0x3
+#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x70
+#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x4
+#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x80
+#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x7
+#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x300
+#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x8
+#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0xfc00
+#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0xa
+#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x1
+#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x0
+#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x2
+#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x1
+#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x4
+#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x2
+#define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x8
+#define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x3
+#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x1
+#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x0
+#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x2
+#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x1
+#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x4
+#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x2
+#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x8
+#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x3
+#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x10
+#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x4
+#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x20
+#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x5
+#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x40
+#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x6
+#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x80
+#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x7
+#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x7
+#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x0
+#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8_MASK 0x8
+#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8__SHIFT 0x3
+#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x70
+#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x4
+#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x80
+#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x7
+#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x300
+#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x8
+#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0xfc00
+#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0xa
+#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x1
+#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x0
+#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x2
+#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x1
+#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x4
+#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x2
+#define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x8
+#define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x3
+#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x1
+#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x0
+#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x2
+#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x1
+#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x4
+#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x2
+#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x8
+#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x3
+#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x10
+#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x4
+#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x20
+#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x5
+#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x40
+#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x6
+#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x80
+#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x7
+#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x7
+#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x0
+#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9_MASK 0x8
+#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9__SHIFT 0x3
+#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x70
+#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x4
+#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x80
+#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x7
+#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x300
+#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x8
+#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0xfc00
+#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0xa
+#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x1
+#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x0
+#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x2
+#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x1
+#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x4
+#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x2
+#define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x8
+#define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x3
+#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x1
+#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x0
+#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x2
+#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x1
+#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x4
+#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x2
+#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x8
+#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x3
+#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x10
+#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x4
+#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x20
+#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x5
+#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x40
+#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x6
+#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x80
+#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x7
+#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x7
+#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x0
+#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10_MASK 0x8
+#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10__SHIFT 0x3
+#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x70
+#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x4
+#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x80
+#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x7
+#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x300
+#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x8
+#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0xfc00
+#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0xa
+#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x1
+#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x0
+#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x2
+#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x1
+#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x4
+#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x2
+#define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x8
+#define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x3
+#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x1
+#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x0
+#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x2
+#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x1
+#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x4
+#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x2
+#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x8
+#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x3
+#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x10
+#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x4
+#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x20
+#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x5
+#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x40
+#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x6
+#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x80
+#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x7
+#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x7
+#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x0
+#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11_MASK 0x8
+#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11__SHIFT 0x3
+#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x70
+#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x4
+#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x80
+#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x7
+#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x300
+#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x8
+#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0xfc00
+#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0xa
+#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x1
+#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x0
+#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x2
+#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x1
+#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x4
+#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x2
+#define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x8
+#define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x3
+#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x1
+#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x0
+#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x2
+#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x1
+#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x4
+#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x2
+#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x8
+#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x3
+#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x10
+#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x4
+#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x20
+#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x5
+#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x40
+#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x6
+#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x80
+#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x7
+#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x7
+#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x0
+#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12_MASK 0x8
+#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12__SHIFT 0x3
+#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x70
+#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x4
+#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x80
+#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x7
+#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x300
+#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x8
+#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0xfc00
+#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0xa
+#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x1
+#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x0
+#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x2
+#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x1
+#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x4
+#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x2
+#define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x8
+#define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x3
+#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x1
+#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x0
+#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x2
+#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x1
+#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x4
+#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x2
+#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x8
+#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x3
+#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x10
+#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x4
+#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x20
+#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x5
+#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x40
+#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x6
+#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x80
+#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x7
+#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x7
+#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x0
+#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13_MASK 0x8
+#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13__SHIFT 0x3
+#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x70
+#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x4
+#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x80
+#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x7
+#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x300
+#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x8
+#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0xfc00
+#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0xa
+#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x1
+#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x0
+#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x2
+#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x1
+#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x4
+#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x2
+#define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x8
+#define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x3
+#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x1
+#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x0
+#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x2
+#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x1
+#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x4
+#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x2
+#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x8
+#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x3
+#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x10
+#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x4
+#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x20
+#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x5
+#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x40
+#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x6
+#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x80
+#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x7
+#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x7
+#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x0
+#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14_MASK 0x8
+#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14__SHIFT 0x3
+#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x70
+#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x4
+#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x80
+#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x7
+#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x300
+#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x8
+#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0xfc00
+#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0xa
+#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x1
+#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x0
+#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x2
+#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x1
+#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x4
+#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x2
+#define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x8
+#define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x3
+#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x1
+#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x0
+#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x2
+#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x1
+#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x4
+#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x2
+#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x8
+#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x3
+#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x10
+#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x4
+#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x20
+#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x5
+#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x40
+#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x6
+#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x80
+#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x7
+#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x7
+#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x0
+#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15_MASK 0x8
+#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15__SHIFT 0x3
+#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x70
+#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x4
+#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x80
+#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x7
+#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x300
+#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x8
+#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0xfc00
+#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0xa
+#define PB0_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffff
+#define PB0_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x0
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_00_DEBUG_MASK 0x1
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_00_DEBUG__SHIFT 0x0
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_01_DEBUG_MASK 0x2
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_01_DEBUG__SHIFT 0x1
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_02_DEBUG_MASK 0x4
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_02_DEBUG__SHIFT 0x2
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_03_DEBUG_MASK 0x8
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_03_DEBUG__SHIFT 0x3
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_04_DEBUG_MASK 0x10
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_04_DEBUG__SHIFT 0x4
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_05_DEBUG_MASK 0x20
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_05_DEBUG__SHIFT 0x5
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_06_DEBUG_MASK 0x40
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_06_DEBUG__SHIFT 0x6
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_07_DEBUG_MASK 0x80
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_07_DEBUG__SHIFT 0x7
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_08_DEBUG_MASK 0x100
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_08_DEBUG__SHIFT 0x8
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_09_DEBUG_MASK 0x200
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_09_DEBUG__SHIFT 0x9
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_10_DEBUG_MASK 0x400
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_10_DEBUG__SHIFT 0xa
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_11_DEBUG_MASK 0x800
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_11_DEBUG__SHIFT 0xb
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_12_DEBUG_MASK 0x1000
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_12_DEBUG__SHIFT 0xc
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_13_DEBUG_MASK 0x2000
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_13_DEBUG__SHIFT 0xd
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_14_DEBUG_MASK 0x4000
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_14_DEBUG__SHIFT 0xe
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_15_DEBUG_MASK 0x8000
+#define PB0_PIF_HW_DEBUG__PB0_PIF_HW_15_DEBUG__SHIFT 0xf
+#define PB0_PIF_PRG6__PRG_SPEEDCHANGE_STEP4_DELAY_MASK 0x3ffff
+#define PB0_PIF_PRG6__PRG_SPEEDCHANGE_STEP4_DELAY__SHIFT 0x0
+#define PB0_PIF_PRG7__PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY_MASK 0x3ffff
+#define PB0_PIF_PRG7__PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY__SHIFT 0x0
+#define PB0_PIF_CNTL__SERIAL_CFG_ENABLE_MASK 0x1
+#define PB0_PIF_CNTL__SERIAL_CFG_ENABLE__SHIFT 0x0
+#define PB0_PIF_CNTL__DA_FIFO_RESET_0_MASK 0x2
+#define PB0_PIF_CNTL__DA_FIFO_RESET_0__SHIFT 0x1
+#define PB0_PIF_CNTL__PHY_CR_EN_MODE_MASK 0x4
+#define PB0_PIF_CNTL__PHY_CR_EN_MODE__SHIFT 0x2
+#define PB0_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK 0x8
+#define PB0_PIF_CNTL__PHYCMD_CR_EN_MODE__SHIFT 0x3
+#define PB0_PIF_CNTL__EI_DET_CYCLE_MODE_MASK 0x10
+#define PB0_PIF_CNTL__EI_DET_CYCLE_MODE__SHIFT 0x4
+#define PB0_PIF_CNTL__DA_FIFO_RESET_1_MASK 0x20
+#define PB0_PIF_CNTL__DA_FIFO_RESET_1__SHIFT 0x5
+#define PB0_PIF_CNTL__RXDETECT_FIFO_RESET_MODE_MASK 0x40
+#define PB0_PIF_CNTL__RXDETECT_FIFO_RESET_MODE__SHIFT 0x6
+#define PB0_PIF_CNTL__RXDETECT_TX_PWR_MODE_MASK 0x80
+#define PB0_PIF_CNTL__RXDETECT_TX_PWR_MODE__SHIFT 0x7
+#define PB0_PIF_CNTL__DIVINIT_MODE_MASK 0x100
+#define PB0_PIF_CNTL__DIVINIT_MODE__SHIFT 0x8
+#define PB0_PIF_CNTL__DA_FIFO_RESET_2_MASK 0x200
+#define PB0_PIF_CNTL__DA_FIFO_RESET_2__SHIFT 0x9
+#define PB0_PIF_CNTL__PLL_BINDING_ENABLE_MASK 0x400
+#define PB0_PIF_CNTL__PLL_BINDING_ENABLE__SHIFT 0xa
+#define PB0_PIF_CNTL__SC_CALIB_DONE_CNTL_MASK 0x800
+#define PB0_PIF_CNTL__SC_CALIB_DONE_CNTL__SHIFT 0xb
+#define PB0_PIF_CNTL__DIVINIT_ENABLE_MASK 0x1000
+#define PB0_PIF_CNTL__DIVINIT_ENABLE__SHIFT 0xc
+#define PB0_PIF_CNTL__DA_FIFO_RESET_3_MASK 0x2000
+#define PB0_PIF_CNTL__DA_FIFO_RESET_3__SHIFT 0xd
+#define PB0_PIF_CNTL__PLL0_IN_GEN3_MODE_MASK 0x4000
+#define PB0_PIF_CNTL__PLL0_IN_GEN3_MODE__SHIFT 0xe
+#define PB0_PIF_CNTL__FORCE_TxFreqEquZeroinDTM_EN_MASK 0x8000
+#define PB0_PIF_CNTL__FORCE_TxFreqEquZeroinDTM_EN__SHIFT 0xf
+#define PB0_PIF_CNTL__TXGND_TIME_MASK 0x10000
+#define PB0_PIF_CNTL__TXGND_TIME__SHIFT 0x10
+#define PB0_PIF_CNTL__LS2_EXIT_TIME_MASK 0xe0000
+#define PB0_PIF_CNTL__LS2_EXIT_TIME__SHIFT 0x11
+#define PB0_PIF_CNTL__EI_CYCLE_OFF_TIME_MASK 0x700000
+#define PB0_PIF_CNTL__EI_CYCLE_OFF_TIME__SHIFT 0x14
+#define PB0_PIF_CNTL__EXIT_L0S_INIT_DIS_MASK 0x800000
+#define PB0_PIF_CNTL__EXIT_L0S_INIT_DIS__SHIFT 0x17
+#define PB0_PIF_CNTL__RXEN_GATER_MASK 0xf000000
+#define PB0_PIF_CNTL__RXEN_GATER__SHIFT 0x18
+#define PB0_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP_MASK 0x10000000
+#define PB0_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP__SHIFT 0x1c
+#define PB0_PIF_CNTL__IGNORE_TxDataValid_EP_DIS_MASK 0x20000000
+#define PB0_PIF_CNTL__IGNORE_TxDataValid_EP_DIS__SHIFT 0x1d
+#define PB0_PIF_CNTL__PHYRESPONSEMODE_ON_RXDET_EN_MASK 0x40000000
+#define PB0_PIF_CNTL__PHYRESPONSEMODE_ON_RXDET_EN__SHIFT 0x1e
+#define PB0_PIF_PAIRING__X2_LANE_1_0_MASK 0x1
+#define PB0_PIF_PAIRING__X2_LANE_1_0__SHIFT 0x0
+#define PB0_PIF_PAIRING__X2_LANE_3_2_MASK 0x2
+#define PB0_PIF_PAIRING__X2_LANE_3_2__SHIFT 0x1
+#define PB0_PIF_PAIRING__X2_LANE_5_4_MASK 0x4
+#define PB0_PIF_PAIRING__X2_LANE_5_4__SHIFT 0x2
+#define PB0_PIF_PAIRING__X2_LANE_7_6_MASK 0x8
+#define PB0_PIF_PAIRING__X2_LANE_7_6__SHIFT 0x3
+#define PB0_PIF_PAIRING__X2_LANE_9_8_MASK 0x10
+#define PB0_PIF_PAIRING__X2_LANE_9_8__SHIFT 0x4
+#define PB0_PIF_PAIRING__X2_LANE_11_10_MASK 0x20
+#define PB0_PIF_PAIRING__X2_LANE_11_10__SHIFT 0x5
+#define PB0_PIF_PAIRING__X2_LANE_13_12_MASK 0x40
+#define PB0_PIF_PAIRING__X2_LANE_13_12__SHIFT 0x6
+#define PB0_PIF_PAIRING__X2_LANE_15_14_MASK 0x80
+#define PB0_PIF_PAIRING__X2_LANE_15_14__SHIFT 0x7
+#define PB0_PIF_PAIRING__X4_LANE_3_0_MASK 0x100
+#define PB0_PIF_PAIRING__X4_LANE_3_0__SHIFT 0x8
+#define PB0_PIF_PAIRING__X4_LANE_7_4_MASK 0x200
+#define PB0_PIF_PAIRING__X4_LANE_7_4__SHIFT 0x9
+#define PB0_PIF_PAIRING__X4_LANE_11_8_MASK 0x400
+#define PB0_PIF_PAIRING__X4_LANE_11_8__SHIFT 0xa
+#define PB0_PIF_PAIRING__X4_LANE_15_12_MASK 0x800
+#define PB0_PIF_PAIRING__X4_LANE_15_12__SHIFT 0xb
+#define PB0_PIF_PAIRING__X8_LANE_7_0_MASK 0x10000
+#define PB0_PIF_PAIRING__X8_LANE_7_0__SHIFT 0x10
+#define PB0_PIF_PAIRING__X8_LANE_15_8_MASK 0x20000
+#define PB0_PIF_PAIRING__X8_LANE_15_8__SHIFT 0x11
+#define PB0_PIF_PAIRING__X16_LANE_15_0_MASK 0x100000
+#define PB0_PIF_PAIRING__X16_LANE_15_0__SHIFT 0x14
+#define PB0_PIF_PAIRING__MULTI_PIF_MASK 0x2000000
+#define PB0_PIF_PAIRING__MULTI_PIF__SHIFT 0x19
+#define PB0_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0_MASK 0x7
+#define PB0_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0__SHIFT 0x0
+#define PB0_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0_MASK 0x8
+#define PB0_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0__SHIFT 0x3
+#define PB0_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0_MASK 0x70
+#define PB0_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0__SHIFT 0x4
+#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK 0x380
+#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT 0x7
+#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK 0x1c00
+#define PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT 0xa
+#define PB0_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0_MASK 0x10000
+#define PB0_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0__SHIFT 0x10
+#define PB0_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK 0x7000000
+#define PB0_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0__SHIFT 0x18
+#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0_MASK 0x10000000
+#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0__SHIFT 0x1c
+#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0_MASK 0xe0000000
+#define PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0__SHIFT 0x1d
+#define PB0_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1_MASK 0x7
+#define PB0_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1__SHIFT 0x0
+#define PB0_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1_MASK 0x8
+#define PB0_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1__SHIFT 0x3
+#define PB0_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1_MASK 0x70
+#define PB0_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1__SHIFT 0x4
+#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK 0x380
+#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT 0x7
+#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK 0x1c00
+#define PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT 0xa
+#define PB0_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1_MASK 0x10000
+#define PB0_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1__SHIFT 0x10
+#define PB0_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK 0x7000000
+#define PB0_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1__SHIFT 0x18
+#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1_MASK 0x10000000
+#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1__SHIFT 0x1c
+#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1_MASK 0xe0000000
+#define PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1__SHIFT 0x1d
+#define PB0_PIF_CNTL2__RXDETECT_PRG_EN_MASK 0x1
+#define PB0_PIF_CNTL2__RXDETECT_PRG_EN__SHIFT 0x0
+#define PB0_PIF_CNTL2__RXDETECT_SAMPL_TIME_MASK 0x6
+#define PB0_PIF_CNTL2__RXDETECT_SAMPL_TIME__SHIFT 0x1
+#define PB0_PIF_CNTL2__PLL_RAMP_UP_TIME_PRG_EN_MASK 0x8
+#define PB0_PIF_CNTL2__PLL_RAMP_UP_TIME_PRG_EN__SHIFT 0x3
+#define PB0_PIF_CNTL2__LS2_EXIT_TIME_PRG_EN_MASK 0x10
+#define PB0_PIF_CNTL2__LS2_EXIT_TIME_PRG_EN__SHIFT 0x4
+#define PB0_PIF_CNTL2__SERVICE2_STEP4_DELAY_PRG_EN_MASK 0x20
+#define PB0_PIF_CNTL2__SERVICE2_STEP4_DELAY_PRG_EN__SHIFT 0x5
+#define PB0_PIF_CNTL2__SERVICE3_STEP4_DELAY_PRG_EN_MASK 0x40
+#define PB0_PIF_CNTL2__SERVICE3_STEP4_DELAY_PRG_EN__SHIFT 0x6
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_EN_MASK 0x80
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_EN__SHIFT 0x7
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0_MASK 0x100
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x8
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1_MASK 0x200
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x9
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2_MASK 0x400
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2__SHIFT 0xa
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3_MASK 0x800
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3__SHIFT 0xb
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4_MASK 0x1000
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4__SHIFT 0xc
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5_MASK 0x2000
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5__SHIFT 0xd
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6_MASK 0x4000
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6__SHIFT 0xe
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7_MASK 0x8000
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7__SHIFT 0xf
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8_MASK 0x10000
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8__SHIFT 0x10
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9_MASK 0x20000
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9__SHIFT 0x11
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10_MASK 0x40000
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10__SHIFT 0x12
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11_MASK 0x80000
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11__SHIFT 0x13
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12_MASK 0x100000
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12__SHIFT 0x14
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13_MASK 0x200000
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13__SHIFT 0x15
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14_MASK 0x400000
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14__SHIFT 0x16
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15_MASK 0x800000
+#define PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15__SHIFT 0x17
+#define PB0_PIF_CNTL2__RXPHYSTATUS_DELAY_MASK 0x7000000
+#define PB0_PIF_CNTL2__RXPHYSTATUS_DELAY__SHIFT 0x18
+#define PB0_PIF_CNTL2__RX_STAGGERING_MODE_MASK 0x8000000
+#define PB0_PIF_CNTL2__RX_STAGGERING_MODE__SHIFT 0x1b
+#define PB0_PIF_CNTL2__SPEEDCHANGE_STEP2_DELAY_PRG_EN_MASK 0x10000000
+#define PB0_PIF_CNTL2__SPEEDCHANGE_STEP2_DELAY_PRG_EN__SHIFT 0x1c
+#define PB0_PIF_CNTL2__RX_STAGGERING_DISABLE_MASK 0x20000000
+#define PB0_PIF_CNTL2__RX_STAGGERING_DISABLE__SHIFT 0x1d
+#define PB0_PIF_CNTL2__PLL1_ALWAYS_ON_EN_MASK 0x40000000
+#define PB0_PIF_CNTL2__PLL1_ALWAYS_ON_EN__SHIFT 0x1e
+#define PB0_PIF_CNTL2__SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN_MASK 0x80000000
+#define PB0_PIF_CNTL2__SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN__SHIFT 0x1f
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_0_MASK 0x1
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_0__SHIFT 0x0
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_1_MASK 0x2
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_1__SHIFT 0x1
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_2_MASK 0x4
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_2__SHIFT 0x2
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_3_MASK 0x8
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_3__SHIFT 0x3
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_4_MASK 0x10
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_4__SHIFT 0x4
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_5_MASK 0x20
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_5__SHIFT 0x5
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_6_MASK 0x40
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_6__SHIFT 0x6
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_7_MASK 0x80
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_7__SHIFT 0x7
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_8_MASK 0x100
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_8__SHIFT 0x8
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_9_MASK 0x200
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_9__SHIFT 0x9
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_10_MASK 0x400
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_10__SHIFT 0xa
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_11_MASK 0x800
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_11__SHIFT 0xb
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_12_MASK 0x1000
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_12__SHIFT 0xc
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_13_MASK 0x2000
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_13__SHIFT 0xd
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_14_MASK 0x4000
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_14__SHIFT 0xe
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_15_MASK 0x8000
+#define PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_15__SHIFT 0xf
+#define PB0_PIF_SC_CTL__SC_CALIBRATION_MASK 0x1
+#define PB0_PIF_SC_CTL__SC_CALIBRATION__SHIFT 0x0
+#define PB0_PIF_SC_CTL__SC_RXDETECT_MASK 0x2
+#define PB0_PIF_SC_CTL__SC_RXDETECT__SHIFT 0x1
+#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0S_MASK 0x4
+#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0S__SHIFT 0x2
+#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0_MASK 0x8
+#define PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0__SHIFT 0x3
+#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S_MASK 0x10
+#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S__SHIFT 0x4
+#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK 0x20
+#define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0__SHIFT 0x5
+#define PB0_PIF_SC_CTL__SC_SPEED_CHANGE_MASK 0x40
+#define PB0_PIF_SC_CTL__SC_SPEED_CHANGE__SHIFT 0x6
+#define PB0_PIF_SC_CTL__SC_PHASE_1_MASK 0x100
+#define PB0_PIF_SC_CTL__SC_PHASE_1__SHIFT 0x8
+#define PB0_PIF_SC_CTL__SC_PHASE_2_MASK 0x200
+#define PB0_PIF_SC_CTL__SC_PHASE_2__SHIFT 0x9
+#define PB0_PIF_SC_CTL__SC_PHASE_3_MASK 0x400
+#define PB0_PIF_SC_CTL__SC_PHASE_3__SHIFT 0xa
+#define PB0_PIF_SC_CTL__SC_PHASE_4_MASK 0x800
+#define PB0_PIF_SC_CTL__SC_PHASE_4__SHIFT 0xb
+#define PB0_PIF_SC_CTL__SC_PHASE_5_MASK 0x1000
+#define PB0_PIF_SC_CTL__SC_PHASE_5__SHIFT 0xc
+#define PB0_PIF_SC_CTL__SC_PHASE_6_MASK 0x2000
+#define PB0_PIF_SC_CTL__SC_PHASE_6__SHIFT 0xd
+#define PB0_PIF_SC_CTL__SC_PHASE_7_MASK 0x4000
+#define PB0_PIF_SC_CTL__SC_PHASE_7__SHIFT 0xe
+#define PB0_PIF_SC_CTL__SC_PHASE_8_MASK 0x8000
+#define PB0_PIF_SC_CTL__SC_PHASE_8__SHIFT 0xf
+#define PB0_PIF_SC_CTL__SC_LANE_0_RESUME_MASK 0x10000
+#define PB0_PIF_SC_CTL__SC_LANE_0_RESUME__SHIFT 0x10
+#define PB0_PIF_SC_CTL__SC_LANE_1_RESUME_MASK 0x20000
+#define PB0_PIF_SC_CTL__SC_LANE_1_RESUME__SHIFT 0x11
+#define PB0_PIF_SC_CTL__SC_LANE_2_RESUME_MASK 0x40000
+#define PB0_PIF_SC_CTL__SC_LANE_2_RESUME__SHIFT 0x12
+#define PB0_PIF_SC_CTL__SC_LANE_3_RESUME_MASK 0x80000
+#define PB0_PIF_SC_CTL__SC_LANE_3_RESUME__SHIFT 0x13
+#define PB0_PIF_SC_CTL__SC_LANE_4_RESUME_MASK 0x100000
+#define PB0_PIF_SC_CTL__SC_LANE_4_RESUME__SHIFT 0x14
+#define PB0_PIF_SC_CTL__SC_LANE_5_RESUME_MASK 0x200000
+#define PB0_PIF_SC_CTL__SC_LANE_5_RESUME__SHIFT 0x15
+#define PB0_PIF_SC_CTL__SC_LANE_6_RESUME_MASK 0x400000
+#define PB0_PIF_SC_CTL__SC_LANE_6_RESUME__SHIFT 0x16
+#define PB0_PIF_SC_CTL__SC_LANE_7_RESUME_MASK 0x800000
+#define PB0_PIF_SC_CTL__SC_LANE_7_RESUME__SHIFT 0x17
+#define PB0_PIF_SC_CTL__SC_LANE_8_RESUME_MASK 0x1000000
+#define PB0_PIF_SC_CTL__SC_LANE_8_RESUME__SHIFT 0x18
+#define PB0_PIF_SC_CTL__SC_LANE_9_RESUME_MASK 0x2000000
+#define PB0_PIF_SC_CTL__SC_LANE_9_RESUME__SHIFT 0x19
+#define PB0_PIF_SC_CTL__SC_LANE_10_RESUME_MASK 0x4000000
+#define PB0_PIF_SC_CTL__SC_LANE_10_RESUME__SHIFT 0x1a
+#define PB0_PIF_SC_CTL__SC_LANE_11_RESUME_MASK 0x8000000
+#define PB0_PIF_SC_CTL__SC_LANE_11_RESUME__SHIFT 0x1b
+#define PB0_PIF_SC_CTL__SC_LANE_12_RESUME_MASK 0x10000000
+#define PB0_PIF_SC_CTL__SC_LANE_12_RESUME__SHIFT 0x1c
+#define PB0_PIF_SC_CTL__SC_LANE_13_RESUME_MASK 0x20000000
+#define PB0_PIF_SC_CTL__SC_LANE_13_RESUME__SHIFT 0x1d
+#define PB0_PIF_SC_CTL__SC_LANE_14_RESUME_MASK 0x40000000
+#define PB0_PIF_SC_CTL__SC_LANE_14_RESUME__SHIFT 0x1e
+#define PB0_PIF_SC_CTL__SC_LANE_15_RESUME_MASK 0x80000000
+#define PB0_PIF_SC_CTL__SC_LANE_15_RESUME__SHIFT 0x1f
+#define PB0_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2_MASK 0x7
+#define PB0_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2__SHIFT 0x0
+#define PB0_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2_MASK 0x8
+#define PB0_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2__SHIFT 0x3
+#define PB0_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2_MASK 0x70
+#define PB0_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2__SHIFT 0x4
+#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2_MASK 0x380
+#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2__SHIFT 0x7
+#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2_MASK 0x1c00
+#define PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2__SHIFT 0xa
+#define PB0_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2_MASK 0x10000
+#define PB0_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2__SHIFT 0x10
+#define PB0_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK 0x7000000
+#define PB0_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2__SHIFT 0x18
+#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2_MASK 0x10000000
+#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2__SHIFT 0x1c
+#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2_MASK 0xe0000000
+#define PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2__SHIFT 0x1d
+#define PB0_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3_MASK 0x7
+#define PB0_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3__SHIFT 0x0
+#define PB0_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3_MASK 0x8
+#define PB0_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3__SHIFT 0x3
+#define PB0_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3_MASK 0x70
+#define PB0_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3__SHIFT 0x4
+#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3_MASK 0x380
+#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3__SHIFT 0x7
+#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3_MASK 0x1c00
+#define PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3__SHIFT 0xa
+#define PB0_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3_MASK 0x10000
+#define PB0_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3__SHIFT 0x10
+#define PB0_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK 0x7000000
+#define PB0_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3__SHIFT 0x18
+#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3_MASK 0x10000000
+#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3__SHIFT 0x1c
+#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3_MASK 0xe0000000
+#define PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3__SHIFT 0x1d
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_0_MASK 0x1
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_0__SHIFT 0x0
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_1_MASK 0x2
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_1__SHIFT 0x1
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_2_MASK 0x4
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_2__SHIFT 0x2
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_3_MASK 0x8
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_3__SHIFT 0x3
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_4_MASK 0x10
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_4__SHIFT 0x4
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_5_MASK 0x20
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_5__SHIFT 0x5
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_6_MASK 0x40
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_6__SHIFT 0x6
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_7_MASK 0x80
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_7__SHIFT 0x7
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_8_MASK 0x100
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_8__SHIFT 0x8
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_9_MASK 0x200
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_9__SHIFT 0x9
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_10_MASK 0x400
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_10__SHIFT 0xa
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_11_MASK 0x800
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_11__SHIFT 0xb
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_12_MASK 0x1000
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_12__SHIFT 0xc
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_13_MASK 0x2000
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_13__SHIFT 0xd
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_14_MASK 0x4000
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_14__SHIFT 0xe
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_15_MASK 0x8000
+#define PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_15__SHIFT 0xf
+#define PB0_PIF_PRG0__PRG_RXDETECT_SAMPL_TIME_MASK 0x3ffff
+#define PB0_PIF_PRG0__PRG_RXDETECT_SAMPL_TIME__SHIFT 0x0
+#define PB0_PIF_PRG1__PRG_PLL_RAMP_UP_TIME_MASK 0x3ffff
+#define PB0_PIF_PRG1__PRG_PLL_RAMP_UP_TIME__SHIFT 0x0
+#define PB0_PIF_PRG2__PRG_SERVICE2_STEP4_DELAY_MASK 0x3ffff
+#define PB0_PIF_PRG2__PRG_SERVICE2_STEP4_DELAY__SHIFT 0x0
+#define PB0_PIF_PRG3__PRG_SERVICE3_STEP4_DELAY_MASK 0x3ffff
+#define PB0_PIF_PRG3__PRG_SERVICE3_STEP4_DELAY__SHIFT 0x0
+#define PB0_PIF_PRG4__PRG_SPEEDCHANGE_STEP2_DELAY_MASK 0x3ffff
+#define PB0_PIF_PRG4__PRG_SPEEDCHANGE_STEP2_DELAY__SHIFT 0x0
+#define PB0_PIF_PRG5__PRG_LS2_EXIT_TIME_MASK 0x3ffff
+#define PB0_PIF_PRG5__PRG_LS2_EXIT_TIME__SHIFT 0x0
+#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0_MASK 0x1
+#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0__SHIFT 0x0
+#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0_MASK 0xe
+#define PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0__SHIFT 0x1
+#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0_MASK 0x10
+#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0__SHIFT 0x4
+#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0_MASK 0xe0
+#define PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0__SHIFT 0x5
+#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0_MASK 0x100
+#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0__SHIFT 0x8
+#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0_MASK 0x200
+#define PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0__SHIFT 0x9
+#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0_MASK 0x400
+#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0__SHIFT 0xa
+#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0_MASK 0x3800
+#define PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0__SHIFT 0xb
+#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0_MASK 0x4000
+#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0__SHIFT 0xe
+#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0_MASK 0x38000
+#define PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0__SHIFT 0xf
+#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1_MASK 0x1
+#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1__SHIFT 0x0
+#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1_MASK 0xe
+#define PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1__SHIFT 0x1
+#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1_MASK 0x10
+#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1__SHIFT 0x4
+#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1_MASK 0xe0
+#define PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1__SHIFT 0x5
+#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1_MASK 0x100
+#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1__SHIFT 0x8
+#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1_MASK 0x200
+#define PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1__SHIFT 0x9
+#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1_MASK 0x400
+#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1__SHIFT 0xa
+#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1_MASK 0x3800
+#define PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1__SHIFT 0xb
+#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1_MASK 0x4000
+#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1__SHIFT 0xe
+#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1_MASK 0x38000
+#define PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1__SHIFT 0xf
+#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2_MASK 0x1
+#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2__SHIFT 0x0
+#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2_MASK 0xe
+#define PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2__SHIFT 0x1
+#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2_MASK 0x10
+#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2__SHIFT 0x4
+#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2_MASK 0xe0
+#define PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2__SHIFT 0x5
+#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2_MASK 0x100
+#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2__SHIFT 0x8
+#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2_MASK 0x200
+#define PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2__SHIFT 0x9
+#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2_MASK 0x400
+#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2__SHIFT 0xa
+#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2_MASK 0x3800
+#define PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2__SHIFT 0xb
+#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2_MASK 0x4000
+#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2__SHIFT 0xe
+#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2_MASK 0x38000
+#define PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2__SHIFT 0xf
+#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3_MASK 0x1
+#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3__SHIFT 0x0
+#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3_MASK 0xe
+#define PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3__SHIFT 0x1
+#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3_MASK 0x10
+#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3__SHIFT 0x4
+#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3_MASK 0xe0
+#define PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3__SHIFT 0x5
+#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3_MASK 0x100
+#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3__SHIFT 0x8
+#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3_MASK 0x200
+#define PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3__SHIFT 0x9
+#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3_MASK 0x400
+#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3__SHIFT 0xa
+#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3_MASK 0x3800
+#define PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3__SHIFT 0xb
+#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3_MASK 0x4000
+#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3__SHIFT 0xe
+#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3_MASK 0x38000
+#define PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3__SHIFT 0xf
+#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4_MASK 0x1
+#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4__SHIFT 0x0
+#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4_MASK 0xe
+#define PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4__SHIFT 0x1
+#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4_MASK 0x10
+#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4__SHIFT 0x4
+#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4_MASK 0xe0
+#define PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4__SHIFT 0x5
+#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4_MASK 0x100
+#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4__SHIFT 0x8
+#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4_MASK 0x200
+#define PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4__SHIFT 0x9
+#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4_MASK 0x400
+#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4__SHIFT 0xa
+#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4_MASK 0x3800
+#define PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4__SHIFT 0xb
+#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4_MASK 0x4000
+#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4__SHIFT 0xe
+#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4_MASK 0x38000
+#define PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4__SHIFT 0xf
+#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5_MASK 0x1
+#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5__SHIFT 0x0
+#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5_MASK 0xe
+#define PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5__SHIFT 0x1
+#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5_MASK 0x10
+#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5__SHIFT 0x4
+#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5_MASK 0xe0
+#define PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5__SHIFT 0x5
+#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5_MASK 0x100
+#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5__SHIFT 0x8
+#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5_MASK 0x200
+#define PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5__SHIFT 0x9
+#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5_MASK 0x400
+#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5__SHIFT 0xa
+#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5_MASK 0x3800
+#define PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5__SHIFT 0xb
+#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5_MASK 0x4000
+#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5__SHIFT 0xe
+#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5_MASK 0x38000
+#define PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5__SHIFT 0xf
+#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6_MASK 0x1
+#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6__SHIFT 0x0
+#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6_MASK 0xe
+#define PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6__SHIFT 0x1
+#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6_MASK 0x10
+#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6__SHIFT 0x4
+#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6_MASK 0xe0
+#define PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6__SHIFT 0x5
+#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6_MASK 0x100
+#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6__SHIFT 0x8
+#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6_MASK 0x200
+#define PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6__SHIFT 0x9
+#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6_MASK 0x400
+#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6__SHIFT 0xa
+#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6_MASK 0x3800
+#define PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6__SHIFT 0xb
+#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6_MASK 0x4000
+#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6__SHIFT 0xe
+#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6_MASK 0x38000
+#define PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6__SHIFT 0xf
+#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7_MASK 0x1
+#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7__SHIFT 0x0
+#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7_MASK 0xe
+#define PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7__SHIFT 0x1
+#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7_MASK 0x10
+#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7__SHIFT 0x4
+#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7_MASK 0xe0
+#define PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7__SHIFT 0x5
+#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7_MASK 0x100
+#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7__SHIFT 0x8
+#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7_MASK 0x200
+#define PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7__SHIFT 0x9
+#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7_MASK 0x400
+#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7__SHIFT 0xa
+#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7_MASK 0x3800
+#define PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7__SHIFT 0xb
+#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7_MASK 0x4000
+#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7__SHIFT 0xe
+#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7_MASK 0x38000
+#define PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7__SHIFT 0xf
+#define PB0_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0_MASK 0x1
+#define PB0_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0__SHIFT 0x0
+#define PB0_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0_MASK 0x2
+#define PB0_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0__SHIFT 0x1
+#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0_MASK 0x4
+#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0__SHIFT 0x2
+#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0_MASK 0x8
+#define PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0__SHIFT 0x3
+#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0_MASK 0x10
+#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0__SHIFT 0x4
+#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0_MASK 0x20
+#define PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0__SHIFT 0x5
+#define PB0_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0_MASK 0x40
+#define PB0_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0__SHIFT 0x6
+#define PB0_PIF_SEQ_STATUS_0__SEQ_PHASE_0_MASK 0x700
+#define PB0_PIF_SEQ_STATUS_0__SEQ_PHASE_0__SHIFT 0x8
+#define PB0_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1_MASK 0x1
+#define PB0_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1__SHIFT 0x0
+#define PB0_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1_MASK 0x2
+#define PB0_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1__SHIFT 0x1
+#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1_MASK 0x4
+#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1__SHIFT 0x2
+#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1_MASK 0x8
+#define PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1__SHIFT 0x3
+#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1_MASK 0x10
+#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1__SHIFT 0x4
+#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1_MASK 0x20
+#define PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1__SHIFT 0x5
+#define PB0_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1_MASK 0x40
+#define PB0_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1__SHIFT 0x6
+#define PB0_PIF_SEQ_STATUS_1__SEQ_PHASE_1_MASK 0x700
+#define PB0_PIF_SEQ_STATUS_1__SEQ_PHASE_1__SHIFT 0x8
+#define PB0_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2_MASK 0x1
+#define PB0_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2__SHIFT 0x0
+#define PB0_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2_MASK 0x2
+#define PB0_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2__SHIFT 0x1
+#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2_MASK 0x4
+#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2__SHIFT 0x2
+#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2_MASK 0x8
+#define PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2__SHIFT 0x3
+#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2_MASK 0x10
+#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2__SHIFT 0x4
+#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2_MASK 0x20
+#define PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2__SHIFT 0x5
+#define PB0_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2_MASK 0x40
+#define PB0_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2__SHIFT 0x6
+#define PB0_PIF_SEQ_STATUS_2__SEQ_PHASE_2_MASK 0x700
+#define PB0_PIF_SEQ_STATUS_2__SEQ_PHASE_2__SHIFT 0x8
+#define PB0_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3_MASK 0x1
+#define PB0_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3__SHIFT 0x0
+#define PB0_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3_MASK 0x2
+#define PB0_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3__SHIFT 0x1
+#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3_MASK 0x4
+#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3__SHIFT 0x2
+#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3_MASK 0x8
+#define PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3__SHIFT 0x3
+#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3_MASK 0x10
+#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3__SHIFT 0x4
+#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3_MASK 0x20
+#define PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3__SHIFT 0x5
+#define PB0_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3_MASK 0x40
+#define PB0_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3__SHIFT 0x6
+#define PB0_PIF_SEQ_STATUS_3__SEQ_PHASE_3_MASK 0x700
+#define PB0_PIF_SEQ_STATUS_3__SEQ_PHASE_3__SHIFT 0x8
+#define PB0_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4_MASK 0x1
+#define PB0_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4__SHIFT 0x0
+#define PB0_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4_MASK 0x2
+#define PB0_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4__SHIFT 0x1
+#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4_MASK 0x4
+#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4__SHIFT 0x2
+#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4_MASK 0x8
+#define PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4__SHIFT 0x3
+#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4_MASK 0x10
+#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4__SHIFT 0x4
+#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4_MASK 0x20
+#define PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4__SHIFT 0x5
+#define PB0_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4_MASK 0x40
+#define PB0_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4__SHIFT 0x6
+#define PB0_PIF_SEQ_STATUS_4__SEQ_PHASE_4_MASK 0x700
+#define PB0_PIF_SEQ_STATUS_4__SEQ_PHASE_4__SHIFT 0x8
+#define PB0_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5_MASK 0x1
+#define PB0_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5__SHIFT 0x0
+#define PB0_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5_MASK 0x2
+#define PB0_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5__SHIFT 0x1
+#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5_MASK 0x4
+#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5__SHIFT 0x2
+#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5_MASK 0x8
+#define PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5__SHIFT 0x3
+#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5_MASK 0x10
+#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5__SHIFT 0x4
+#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5_MASK 0x20
+#define PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5__SHIFT 0x5
+#define PB0_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5_MASK 0x40
+#define PB0_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5__SHIFT 0x6
+#define PB0_PIF_SEQ_STATUS_5__SEQ_PHASE_5_MASK 0x700
+#define PB0_PIF_SEQ_STATUS_5__SEQ_PHASE_5__SHIFT 0x8
+#define PB0_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6_MASK 0x1
+#define PB0_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6__SHIFT 0x0
+#define PB0_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6_MASK 0x2
+#define PB0_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6__SHIFT 0x1
+#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6_MASK 0x4
+#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6__SHIFT 0x2
+#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6_MASK 0x8
+#define PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6__SHIFT 0x3
+#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6_MASK 0x10
+#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6__SHIFT 0x4
+#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6_MASK 0x20
+#define PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6__SHIFT 0x5
+#define PB0_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6_MASK 0x40
+#define PB0_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6__SHIFT 0x6
+#define PB0_PIF_SEQ_STATUS_6__SEQ_PHASE_6_MASK 0x700
+#define PB0_PIF_SEQ_STATUS_6__SEQ_PHASE_6__SHIFT 0x8
+#define PB0_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7_MASK 0x1
+#define PB0_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7__SHIFT 0x0
+#define PB0_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7_MASK 0x2
+#define PB0_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7__SHIFT 0x1
+#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7_MASK 0x4
+#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7__SHIFT 0x2
+#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7_MASK 0x8
+#define PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7__SHIFT 0x3
+#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7_MASK 0x10
+#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7__SHIFT 0x4
+#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7_MASK 0x20
+#define PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7__SHIFT 0x5
+#define PB0_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7_MASK 0x40
+#define PB0_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7__SHIFT 0x6
+#define PB0_PIF_SEQ_STATUS_7__SEQ_PHASE_7_MASK 0x700
+#define PB0_PIF_SEQ_STATUS_7__SEQ_PHASE_7__SHIFT 0x8
+#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8_MASK 0x1
+#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8__SHIFT 0x0
+#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8_MASK 0xe
+#define PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8__SHIFT 0x1
+#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8_MASK 0x10
+#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8__SHIFT 0x4
+#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8_MASK 0xe0
+#define PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8__SHIFT 0x5
+#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8_MASK 0x100
+#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8__SHIFT 0x8
+#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8_MASK 0x200
+#define PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8__SHIFT 0x9
+#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8_MASK 0x400
+#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8__SHIFT 0xa
+#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8_MASK 0x3800
+#define PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8__SHIFT 0xb
+#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8_MASK 0x4000
+#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8__SHIFT 0xe
+#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8_MASK 0x38000
+#define PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8__SHIFT 0xf
+#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9_MASK 0x1
+#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9__SHIFT 0x0
+#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9_MASK 0xe
+#define PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9__SHIFT 0x1
+#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9_MASK 0x10
+#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9__SHIFT 0x4
+#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9_MASK 0xe0
+#define PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9__SHIFT 0x5
+#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9_MASK 0x100
+#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9__SHIFT 0x8
+#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9_MASK 0x200
+#define PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9__SHIFT 0x9
+#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9_MASK 0x400
+#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9__SHIFT 0xa
+#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9_MASK 0x3800
+#define PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9__SHIFT 0xb
+#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9_MASK 0x4000
+#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9__SHIFT 0xe
+#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9_MASK 0x38000
+#define PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9__SHIFT 0xf
+#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10_MASK 0x1
+#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10__SHIFT 0x0
+#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10_MASK 0xe
+#define PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10__SHIFT 0x1
+#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10_MASK 0x10
+#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10__SHIFT 0x4
+#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10_MASK 0xe0
+#define PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10__SHIFT 0x5
+#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10_MASK 0x100
+#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10__SHIFT 0x8
+#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10_MASK 0x200
+#define PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10__SHIFT 0x9
+#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10_MASK 0x400
+#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10__SHIFT 0xa
+#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10_MASK 0x3800
+#define PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10__SHIFT 0xb
+#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10_MASK 0x4000
+#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10__SHIFT 0xe
+#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10_MASK 0x38000
+#define PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10__SHIFT 0xf
+#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11_MASK 0x1
+#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11__SHIFT 0x0
+#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11_MASK 0xe
+#define PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11__SHIFT 0x1
+#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11_MASK 0x10
+#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11__SHIFT 0x4
+#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11_MASK 0xe0
+#define PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11__SHIFT 0x5
+#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11_MASK 0x100
+#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11__SHIFT 0x8
+#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11_MASK 0x200
+#define PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11__SHIFT 0x9
+#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11_MASK 0x400
+#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11__SHIFT 0xa
+#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11_MASK 0x3800
+#define PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11__SHIFT 0xb
+#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11_MASK 0x4000
+#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11__SHIFT 0xe
+#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11_MASK 0x38000
+#define PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11__SHIFT 0xf
+#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12_MASK 0x1
+#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12__SHIFT 0x0
+#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12_MASK 0xe
+#define PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12__SHIFT 0x1
+#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12_MASK 0x10
+#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12__SHIFT 0x4
+#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12_MASK 0xe0
+#define PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12__SHIFT 0x5
+#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12_MASK 0x100
+#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12__SHIFT 0x8
+#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12_MASK 0x200
+#define PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12__SHIFT 0x9
+#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12_MASK 0x400
+#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12__SHIFT 0xa
+#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12_MASK 0x3800
+#define PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12__SHIFT 0xb
+#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12_MASK 0x4000
+#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12__SHIFT 0xe
+#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12_MASK 0x38000
+#define PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12__SHIFT 0xf
+#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13_MASK 0x1
+#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13__SHIFT 0x0
+#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13_MASK 0xe
+#define PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13__SHIFT 0x1
+#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13_MASK 0x10
+#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13__SHIFT 0x4
+#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13_MASK 0xe0
+#define PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13__SHIFT 0x5
+#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13_MASK 0x100
+#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13__SHIFT 0x8
+#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13_MASK 0x200
+#define PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13__SHIFT 0x9
+#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13_MASK 0x400
+#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13__SHIFT 0xa
+#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13_MASK 0x3800
+#define PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13__SHIFT 0xb
+#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13_MASK 0x4000
+#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13__SHIFT 0xe
+#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13_MASK 0x38000
+#define PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13__SHIFT 0xf
+#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14_MASK 0x1
+#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14__SHIFT 0x0
+#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14_MASK 0xe
+#define PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14__SHIFT 0x1
+#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14_MASK 0x10
+#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14__SHIFT 0x4
+#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14_MASK 0xe0
+#define PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14__SHIFT 0x5
+#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14_MASK 0x100
+#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14__SHIFT 0x8
+#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14_MASK 0x200
+#define PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14__SHIFT 0x9
+#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14_MASK 0x400
+#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14__SHIFT 0xa
+#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14_MASK 0x3800
+#define PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14__SHIFT 0xb
+#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14_MASK 0x4000
+#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14__SHIFT 0xe
+#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14_MASK 0x38000
+#define PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14__SHIFT 0xf
+#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15_MASK 0x1
+#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15__SHIFT 0x0
+#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15_MASK 0xe
+#define PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15__SHIFT 0x1
+#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15_MASK 0x10
+#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15__SHIFT 0x4
+#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15_MASK 0xe0
+#define PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15__SHIFT 0x5
+#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15_MASK 0x100
+#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15__SHIFT 0x8
+#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15_MASK 0x200
+#define PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15__SHIFT 0x9
+#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15_MASK 0x400
+#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15__SHIFT 0xa
+#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15_MASK 0x3800
+#define PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15__SHIFT 0xb
+#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15_MASK 0x4000
+#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15__SHIFT 0xe
+#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15_MASK 0x38000
+#define PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15__SHIFT 0xf
+#define PB0_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8_MASK 0x1
+#define PB0_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8__SHIFT 0x0
+#define PB0_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8_MASK 0x2
+#define PB0_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8__SHIFT 0x1
+#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8_MASK 0x4
+#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8__SHIFT 0x2
+#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8_MASK 0x8
+#define PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8__SHIFT 0x3
+#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8_MASK 0x10
+#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8__SHIFT 0x4
+#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8_MASK 0x20
+#define PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8__SHIFT 0x5
+#define PB0_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8_MASK 0x40
+#define PB0_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8__SHIFT 0x6
+#define PB0_PIF_SEQ_STATUS_8__SEQ_PHASE_8_MASK 0x700
+#define PB0_PIF_SEQ_STATUS_8__SEQ_PHASE_8__SHIFT 0x8
+#define PB0_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9_MASK 0x1
+#define PB0_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9__SHIFT 0x0
+#define PB0_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9_MASK 0x2
+#define PB0_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9__SHIFT 0x1
+#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9_MASK 0x4
+#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9__SHIFT 0x2
+#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9_MASK 0x8
+#define PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9__SHIFT 0x3
+#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9_MASK 0x10
+#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9__SHIFT 0x4
+#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9_MASK 0x20
+#define PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9__SHIFT 0x5
+#define PB0_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9_MASK 0x40
+#define PB0_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9__SHIFT 0x6
+#define PB0_PIF_SEQ_STATUS_9__SEQ_PHASE_9_MASK 0x700
+#define PB0_PIF_SEQ_STATUS_9__SEQ_PHASE_9__SHIFT 0x8
+#define PB0_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10_MASK 0x1
+#define PB0_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10__SHIFT 0x0
+#define PB0_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10_MASK 0x2
+#define PB0_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10__SHIFT 0x1
+#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10_MASK 0x4
+#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10__SHIFT 0x2
+#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10_MASK 0x8
+#define PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10__SHIFT 0x3
+#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10_MASK 0x10
+#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10__SHIFT 0x4
+#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10_MASK 0x20
+#define PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10__SHIFT 0x5
+#define PB0_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10_MASK 0x40
+#define PB0_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10__SHIFT 0x6
+#define PB0_PIF_SEQ_STATUS_10__SEQ_PHASE_10_MASK 0x700
+#define PB0_PIF_SEQ_STATUS_10__SEQ_PHASE_10__SHIFT 0x8
+#define PB0_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11_MASK 0x1
+#define PB0_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11__SHIFT 0x0
+#define PB0_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11_MASK 0x2
+#define PB0_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11__SHIFT 0x1
+#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11_MASK 0x4
+#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11__SHIFT 0x2
+#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11_MASK 0x8
+#define PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11__SHIFT 0x3
+#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11_MASK 0x10
+#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11__SHIFT 0x4
+#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11_MASK 0x20
+#define PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11__SHIFT 0x5
+#define PB0_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11_MASK 0x40
+#define PB0_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11__SHIFT 0x6
+#define PB0_PIF_SEQ_STATUS_11__SEQ_PHASE_11_MASK 0x700
+#define PB0_PIF_SEQ_STATUS_11__SEQ_PHASE_11__SHIFT 0x8
+#define PB0_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12_MASK 0x1
+#define PB0_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12__SHIFT 0x0
+#define PB0_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12_MASK 0x2
+#define PB0_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12__SHIFT 0x1
+#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12_MASK 0x4
+#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12__SHIFT 0x2
+#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12_MASK 0x8
+#define PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12__SHIFT 0x3
+#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12_MASK 0x10
+#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12__SHIFT 0x4
+#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12_MASK 0x20
+#define PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12__SHIFT 0x5
+#define PB0_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12_MASK 0x40
+#define PB0_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12__SHIFT 0x6
+#define PB0_PIF_SEQ_STATUS_12__SEQ_PHASE_12_MASK 0x700
+#define PB0_PIF_SEQ_STATUS_12__SEQ_PHASE_12__SHIFT 0x8
+#define PB0_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13_MASK 0x1
+#define PB0_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13__SHIFT 0x0
+#define PB0_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13_MASK 0x2
+#define PB0_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13__SHIFT 0x1
+#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13_MASK 0x4
+#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13__SHIFT 0x2
+#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13_MASK 0x8
+#define PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13__SHIFT 0x3
+#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13_MASK 0x10
+#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13__SHIFT 0x4
+#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13_MASK 0x20
+#define PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13__SHIFT 0x5
+#define PB0_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13_MASK 0x40
+#define PB0_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13__SHIFT 0x6
+#define PB0_PIF_SEQ_STATUS_13__SEQ_PHASE_13_MASK 0x700
+#define PB0_PIF_SEQ_STATUS_13__SEQ_PHASE_13__SHIFT 0x8
+#define PB0_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14_MASK 0x1
+#define PB0_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14__SHIFT 0x0
+#define PB0_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14_MASK 0x2
+#define PB0_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14__SHIFT 0x1
+#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14_MASK 0x4
+#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14__SHIFT 0x2
+#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14_MASK 0x8
+#define PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14__SHIFT 0x3
+#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14_MASK 0x10
+#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14__SHIFT 0x4
+#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14_MASK 0x20
+#define PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14__SHIFT 0x5
+#define PB0_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14_MASK 0x40
+#define PB0_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14__SHIFT 0x6
+#define PB0_PIF_SEQ_STATUS_14__SEQ_PHASE_14_MASK 0x700
+#define PB0_PIF_SEQ_STATUS_14__SEQ_PHASE_14__SHIFT 0x8
+#define PB0_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15_MASK 0x1
+#define PB0_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15__SHIFT 0x0
+#define PB0_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15_MASK 0x2
+#define PB0_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15__SHIFT 0x1
+#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15_MASK 0x4
+#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15__SHIFT 0x2
+#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15_MASK 0x8
+#define PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15__SHIFT 0x3
+#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15_MASK 0x10
+#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15__SHIFT 0x4
+#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15_MASK 0x20
+#define PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15__SHIFT 0x5
+#define PB0_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15_MASK 0x40
+#define PB0_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15__SHIFT 0x6
+#define PB0_PIF_SEQ_STATUS_15__SEQ_PHASE_15_MASK 0x700
+#define PB0_PIF_SEQ_STATUS_15__SEQ_PHASE_15__SHIFT 0x8
+#define PB1_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffff
+#define PB1_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x0
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_00_DEBUG_MASK 0x1
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_00_DEBUG__SHIFT 0x0
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_01_DEBUG_MASK 0x2
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_01_DEBUG__SHIFT 0x1
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_02_DEBUG_MASK 0x4
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_02_DEBUG__SHIFT 0x2
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_03_DEBUG_MASK 0x8
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_03_DEBUG__SHIFT 0x3
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_04_DEBUG_MASK 0x10
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_04_DEBUG__SHIFT 0x4
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_05_DEBUG_MASK 0x20
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_05_DEBUG__SHIFT 0x5
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_06_DEBUG_MASK 0x40
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_06_DEBUG__SHIFT 0x6
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_07_DEBUG_MASK 0x80
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_07_DEBUG__SHIFT 0x7
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_08_DEBUG_MASK 0x100
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_08_DEBUG__SHIFT 0x8
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_09_DEBUG_MASK 0x200
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_09_DEBUG__SHIFT 0x9
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_10_DEBUG_MASK 0x400
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_10_DEBUG__SHIFT 0xa
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_11_DEBUG_MASK 0x800
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_11_DEBUG__SHIFT 0xb
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_12_DEBUG_MASK 0x1000
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_12_DEBUG__SHIFT 0xc
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_13_DEBUG_MASK 0x2000
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_13_DEBUG__SHIFT 0xd
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_14_DEBUG_MASK 0x4000
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_14_DEBUG__SHIFT 0xe
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_15_DEBUG_MASK 0x8000
+#define PB1_PIF_HW_DEBUG__PB1_PIF_HW_15_DEBUG__SHIFT 0xf
+#define PB1_PIF_PRG6__PRG_SPEEDCHANGE_STEP4_DELAY_MASK 0x3ffff
+#define PB1_PIF_PRG6__PRG_SPEEDCHANGE_STEP4_DELAY__SHIFT 0x0
+#define PB1_PIF_PRG7__PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY_MASK 0x3ffff
+#define PB1_PIF_PRG7__PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY__SHIFT 0x0
+#define PB1_PIF_CNTL__SERIAL_CFG_ENABLE_MASK 0x1
+#define PB1_PIF_CNTL__SERIAL_CFG_ENABLE__SHIFT 0x0
+#define PB1_PIF_CNTL__DA_FIFO_RESET_0_MASK 0x2
+#define PB1_PIF_CNTL__DA_FIFO_RESET_0__SHIFT 0x1
+#define PB1_PIF_CNTL__PHY_CR_EN_MODE_MASK 0x4
+#define PB1_PIF_CNTL__PHY_CR_EN_MODE__SHIFT 0x2
+#define PB1_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK 0x8
+#define PB1_PIF_CNTL__PHYCMD_CR_EN_MODE__SHIFT 0x3
+#define PB1_PIF_CNTL__EI_DET_CYCLE_MODE_MASK 0x10
+#define PB1_PIF_CNTL__EI_DET_CYCLE_MODE__SHIFT 0x4
+#define PB1_PIF_CNTL__DA_FIFO_RESET_1_MASK 0x20
+#define PB1_PIF_CNTL__DA_FIFO_RESET_1__SHIFT 0x5
+#define PB1_PIF_CNTL__RXDETECT_FIFO_RESET_MODE_MASK 0x40
+#define PB1_PIF_CNTL__RXDETECT_FIFO_RESET_MODE__SHIFT 0x6
+#define PB1_PIF_CNTL__RXDETECT_TX_PWR_MODE_MASK 0x80
+#define PB1_PIF_CNTL__RXDETECT_TX_PWR_MODE__SHIFT 0x7
+#define PB1_PIF_CNTL__DIVINIT_MODE_MASK 0x100
+#define PB1_PIF_CNTL__DIVINIT_MODE__SHIFT 0x8
+#define PB1_PIF_CNTL__DA_FIFO_RESET_2_MASK 0x200
+#define PB1_PIF_CNTL__DA_FIFO_RESET_2__SHIFT 0x9
+#define PB1_PIF_CNTL__PLL_BINDING_ENABLE_MASK 0x400
+#define PB1_PIF_CNTL__PLL_BINDING_ENABLE__SHIFT 0xa
+#define PB1_PIF_CNTL__SC_CALIB_DONE_CNTL_MASK 0x800
+#define PB1_PIF_CNTL__SC_CALIB_DONE_CNTL__SHIFT 0xb
+#define PB1_PIF_CNTL__DIVINIT_ENABLE_MASK 0x1000
+#define PB1_PIF_CNTL__DIVINIT_ENABLE__SHIFT 0xc
+#define PB1_PIF_CNTL__DA_FIFO_RESET_3_MASK 0x2000
+#define PB1_PIF_CNTL__DA_FIFO_RESET_3__SHIFT 0xd
+#define PB1_PIF_CNTL__PLL0_IN_GEN3_MODE_MASK 0x4000
+#define PB1_PIF_CNTL__PLL0_IN_GEN3_MODE__SHIFT 0xe
+#define PB1_PIF_CNTL__FORCE_TxFreqEquZeroinDTM_EN_MASK 0x8000
+#define PB1_PIF_CNTL__FORCE_TxFreqEquZeroinDTM_EN__SHIFT 0xf
+#define PB1_PIF_CNTL__TXGND_TIME_MASK 0x10000
+#define PB1_PIF_CNTL__TXGND_TIME__SHIFT 0x10
+#define PB1_PIF_CNTL__LS2_EXIT_TIME_MASK 0xe0000
+#define PB1_PIF_CNTL__LS2_EXIT_TIME__SHIFT 0x11
+#define PB1_PIF_CNTL__EI_CYCLE_OFF_TIME_MASK 0x700000
+#define PB1_PIF_CNTL__EI_CYCLE_OFF_TIME__SHIFT 0x14
+#define PB1_PIF_CNTL__EXIT_L0S_INIT_DIS_MASK 0x800000
+#define PB1_PIF_CNTL__EXIT_L0S_INIT_DIS__SHIFT 0x17
+#define PB1_PIF_CNTL__RXEN_GATER_MASK 0xf000000
+#define PB1_PIF_CNTL__RXEN_GATER__SHIFT 0x18
+#define PB1_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP_MASK 0x10000000
+#define PB1_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP__SHIFT 0x1c
+#define PB1_PIF_CNTL__IGNORE_TxDataValid_EP_DIS_MASK 0x20000000
+#define PB1_PIF_CNTL__IGNORE_TxDataValid_EP_DIS__SHIFT 0x1d
+#define PB1_PIF_CNTL__PHYRESPONSEMODE_ON_RXDET_EN_MASK 0x40000000
+#define PB1_PIF_CNTL__PHYRESPONSEMODE_ON_RXDET_EN__SHIFT 0x1e
+#define PB1_PIF_PAIRING__X2_LANE_1_0_MASK 0x1
+#define PB1_PIF_PAIRING__X2_LANE_1_0__SHIFT 0x0
+#define PB1_PIF_PAIRING__X2_LANE_3_2_MASK 0x2
+#define PB1_PIF_PAIRING__X2_LANE_3_2__SHIFT 0x1
+#define PB1_PIF_PAIRING__X2_LANE_5_4_MASK 0x4
+#define PB1_PIF_PAIRING__X2_LANE_5_4__SHIFT 0x2
+#define PB1_PIF_PAIRING__X2_LANE_7_6_MASK 0x8
+#define PB1_PIF_PAIRING__X2_LANE_7_6__SHIFT 0x3
+#define PB1_PIF_PAIRING__X2_LANE_9_8_MASK 0x10
+#define PB1_PIF_PAIRING__X2_LANE_9_8__SHIFT 0x4
+#define PB1_PIF_PAIRING__X2_LANE_11_10_MASK 0x20
+#define PB1_PIF_PAIRING__X2_LANE_11_10__SHIFT 0x5
+#define PB1_PIF_PAIRING__X2_LANE_13_12_MASK 0x40
+#define PB1_PIF_PAIRING__X2_LANE_13_12__SHIFT 0x6
+#define PB1_PIF_PAIRING__X2_LANE_15_14_MASK 0x80
+#define PB1_PIF_PAIRING__X2_LANE_15_14__SHIFT 0x7
+#define PB1_PIF_PAIRING__X4_LANE_3_0_MASK 0x100
+#define PB1_PIF_PAIRING__X4_LANE_3_0__SHIFT 0x8
+#define PB1_PIF_PAIRING__X4_LANE_7_4_MASK 0x200
+#define PB1_PIF_PAIRING__X4_LANE_7_4__SHIFT 0x9
+#define PB1_PIF_PAIRING__X4_LANE_11_8_MASK 0x400
+#define PB1_PIF_PAIRING__X4_LANE_11_8__SHIFT 0xa
+#define PB1_PIF_PAIRING__X4_LANE_15_12_MASK 0x800
+#define PB1_PIF_PAIRING__X4_LANE_15_12__SHIFT 0xb
+#define PB1_PIF_PAIRING__X8_LANE_7_0_MASK 0x10000
+#define PB1_PIF_PAIRING__X8_LANE_7_0__SHIFT 0x10
+#define PB1_PIF_PAIRING__X8_LANE_15_8_MASK 0x20000
+#define PB1_PIF_PAIRING__X8_LANE_15_8__SHIFT 0x11
+#define PB1_PIF_PAIRING__X16_LANE_15_0_MASK 0x100000
+#define PB1_PIF_PAIRING__X16_LANE_15_0__SHIFT 0x14
+#define PB1_PIF_PAIRING__MULTI_PIF_MASK 0x2000000
+#define PB1_PIF_PAIRING__MULTI_PIF__SHIFT 0x19
+#define PB1_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0_MASK 0x7
+#define PB1_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0__SHIFT 0x0
+#define PB1_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0_MASK 0x8
+#define PB1_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0__SHIFT 0x3
+#define PB1_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0_MASK 0x70
+#define PB1_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0__SHIFT 0x4
+#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK 0x380
+#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT 0x7
+#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK 0x1c00
+#define PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT 0xa
+#define PB1_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0_MASK 0x10000
+#define PB1_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0__SHIFT 0x10
+#define PB1_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK 0x7000000
+#define PB1_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0__SHIFT 0x18
+#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0_MASK 0x10000000
+#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0__SHIFT 0x1c
+#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0_MASK 0xe0000000
+#define PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0__SHIFT 0x1d
+#define PB1_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1_MASK 0x7
+#define PB1_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1__SHIFT 0x0
+#define PB1_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1_MASK 0x8
+#define PB1_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1__SHIFT 0x3
+#define PB1_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1_MASK 0x70
+#define PB1_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1__SHIFT 0x4
+#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK 0x380
+#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT 0x7
+#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK 0x1c00
+#define PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT 0xa
+#define PB1_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1_MASK 0x10000
+#define PB1_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1__SHIFT 0x10
+#define PB1_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK 0x7000000
+#define PB1_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1__SHIFT 0x18
+#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1_MASK 0x10000000
+#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1__SHIFT 0x1c
+#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1_MASK 0xe0000000
+#define PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1__SHIFT 0x1d
+#define PB1_PIF_CNTL2__RXDETECT_PRG_EN_MASK 0x1
+#define PB1_PIF_CNTL2__RXDETECT_PRG_EN__SHIFT 0x0
+#define PB1_PIF_CNTL2__RXDETECT_SAMPL_TIME_MASK 0x6
+#define PB1_PIF_CNTL2__RXDETECT_SAMPL_TIME__SHIFT 0x1
+#define PB1_PIF_CNTL2__PLL_RAMP_UP_TIME_PRG_EN_MASK 0x8
+#define PB1_PIF_CNTL2__PLL_RAMP_UP_TIME_PRG_EN__SHIFT 0x3
+#define PB1_PIF_CNTL2__LS2_EXIT_TIME_PRG_EN_MASK 0x10
+#define PB1_PIF_CNTL2__LS2_EXIT_TIME_PRG_EN__SHIFT 0x4
+#define PB1_PIF_CNTL2__SERVICE2_STEP4_DELAY_PRG_EN_MASK 0x20
+#define PB1_PIF_CNTL2__SERVICE2_STEP4_DELAY_PRG_EN__SHIFT 0x5
+#define PB1_PIF_CNTL2__SERVICE3_STEP4_DELAY_PRG_EN_MASK 0x40
+#define PB1_PIF_CNTL2__SERVICE3_STEP4_DELAY_PRG_EN__SHIFT 0x6
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_EN_MASK 0x80
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_EN__SHIFT 0x7
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0_MASK 0x100
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x8
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1_MASK 0x200
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x9
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2_MASK 0x400
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2__SHIFT 0xa
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3_MASK 0x800
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3__SHIFT 0xb
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4_MASK 0x1000
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4__SHIFT 0xc
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5_MASK 0x2000
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5__SHIFT 0xd
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6_MASK 0x4000
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6__SHIFT 0xe
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7_MASK 0x8000
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7__SHIFT 0xf
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8_MASK 0x10000
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8__SHIFT 0x10
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9_MASK 0x20000
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9__SHIFT 0x11
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10_MASK 0x40000
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10__SHIFT 0x12
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11_MASK 0x80000
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11__SHIFT 0x13
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12_MASK 0x100000
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12__SHIFT 0x14
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13_MASK 0x200000
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13__SHIFT 0x15
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14_MASK 0x400000
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14__SHIFT 0x16
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15_MASK 0x800000
+#define PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15__SHIFT 0x17
+#define PB1_PIF_CNTL2__RXPHYSTATUS_DELAY_MASK 0x7000000
+#define PB1_PIF_CNTL2__RXPHYSTATUS_DELAY__SHIFT 0x18
+#define PB1_PIF_CNTL2__RX_STAGGERING_MODE_MASK 0x8000000
+#define PB1_PIF_CNTL2__RX_STAGGERING_MODE__SHIFT 0x1b
+#define PB1_PIF_CNTL2__SPEEDCHANGE_STEP2_DELAY_PRG_EN_MASK 0x10000000
+#define PB1_PIF_CNTL2__SPEEDCHANGE_STEP2_DELAY_PRG_EN__SHIFT 0x1c
+#define PB1_PIF_CNTL2__RX_STAGGERING_DISABLE_MASK 0x20000000
+#define PB1_PIF_CNTL2__RX_STAGGERING_DISABLE__SHIFT 0x1d
+#define PB1_PIF_CNTL2__PLL1_ALWAYS_ON_EN_MASK 0x40000000
+#define PB1_PIF_CNTL2__PLL1_ALWAYS_ON_EN__SHIFT 0x1e
+#define PB1_PIF_CNTL2__SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN_MASK 0x80000000
+#define PB1_PIF_CNTL2__SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN__SHIFT 0x1f
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_0_MASK 0x1
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_0__SHIFT 0x0
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_1_MASK 0x2
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_1__SHIFT 0x1
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_2_MASK 0x4
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_2__SHIFT 0x2
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_3_MASK 0x8
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_3__SHIFT 0x3
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_4_MASK 0x10
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_4__SHIFT 0x4
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_5_MASK 0x20
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_5__SHIFT 0x5
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_6_MASK 0x40
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_6__SHIFT 0x6
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_7_MASK 0x80
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_7__SHIFT 0x7
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_8_MASK 0x100
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_8__SHIFT 0x8
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_9_MASK 0x200
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_9__SHIFT 0x9
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_10_MASK 0x400
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_10__SHIFT 0xa
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_11_MASK 0x800
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_11__SHIFT 0xb
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_12_MASK 0x1000
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_12__SHIFT 0xc
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_13_MASK 0x2000
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_13__SHIFT 0xd
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_14_MASK 0x4000
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_14__SHIFT 0xe
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_15_MASK 0x8000
+#define PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_15__SHIFT 0xf
+#define PB1_PIF_SC_CTL__SC_CALIBRATION_MASK 0x1
+#define PB1_PIF_SC_CTL__SC_CALIBRATION__SHIFT 0x0
+#define PB1_PIF_SC_CTL__SC_RXDETECT_MASK 0x2
+#define PB1_PIF_SC_CTL__SC_RXDETECT__SHIFT 0x1
+#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0S_MASK 0x4
+#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0S__SHIFT 0x2
+#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0_MASK 0x8
+#define PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0__SHIFT 0x3
+#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S_MASK 0x10
+#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S__SHIFT 0x4
+#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK 0x20
+#define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0__SHIFT 0x5
+#define PB1_PIF_SC_CTL__SC_SPEED_CHANGE_MASK 0x40
+#define PB1_PIF_SC_CTL__SC_SPEED_CHANGE__SHIFT 0x6
+#define PB1_PIF_SC_CTL__SC_PHASE_1_MASK 0x100
+#define PB1_PIF_SC_CTL__SC_PHASE_1__SHIFT 0x8
+#define PB1_PIF_SC_CTL__SC_PHASE_2_MASK 0x200
+#define PB1_PIF_SC_CTL__SC_PHASE_2__SHIFT 0x9
+#define PB1_PIF_SC_CTL__SC_PHASE_3_MASK 0x400
+#define PB1_PIF_SC_CTL__SC_PHASE_3__SHIFT 0xa
+#define PB1_PIF_SC_CTL__SC_PHASE_4_MASK 0x800
+#define PB1_PIF_SC_CTL__SC_PHASE_4__SHIFT 0xb
+#define PB1_PIF_SC_CTL__SC_PHASE_5_MASK 0x1000
+#define PB1_PIF_SC_CTL__SC_PHASE_5__SHIFT 0xc
+#define PB1_PIF_SC_CTL__SC_PHASE_6_MASK 0x2000
+#define PB1_PIF_SC_CTL__SC_PHASE_6__SHIFT 0xd
+#define PB1_PIF_SC_CTL__SC_PHASE_7_MASK 0x4000
+#define PB1_PIF_SC_CTL__SC_PHASE_7__SHIFT 0xe
+#define PB1_PIF_SC_CTL__SC_PHASE_8_MASK 0x8000
+#define PB1_PIF_SC_CTL__SC_PHASE_8__SHIFT 0xf
+#define PB1_PIF_SC_CTL__SC_LANE_0_RESUME_MASK 0x10000
+#define PB1_PIF_SC_CTL__SC_LANE_0_RESUME__SHIFT 0x10
+#define PB1_PIF_SC_CTL__SC_LANE_1_RESUME_MASK 0x20000
+#define PB1_PIF_SC_CTL__SC_LANE_1_RESUME__SHIFT 0x11
+#define PB1_PIF_SC_CTL__SC_LANE_2_RESUME_MASK 0x40000
+#define PB1_PIF_SC_CTL__SC_LANE_2_RESUME__SHIFT 0x12
+#define PB1_PIF_SC_CTL__SC_LANE_3_RESUME_MASK 0x80000
+#define PB1_PIF_SC_CTL__SC_LANE_3_RESUME__SHIFT 0x13
+#define PB1_PIF_SC_CTL__SC_LANE_4_RESUME_MASK 0x100000
+#define PB1_PIF_SC_CTL__SC_LANE_4_RESUME__SHIFT 0x14
+#define PB1_PIF_SC_CTL__SC_LANE_5_RESUME_MASK 0x200000
+#define PB1_PIF_SC_CTL__SC_LANE_5_RESUME__SHIFT 0x15
+#define PB1_PIF_SC_CTL__SC_LANE_6_RESUME_MASK 0x400000
+#define PB1_PIF_SC_CTL__SC_LANE_6_RESUME__SHIFT 0x16
+#define PB1_PIF_SC_CTL__SC_LANE_7_RESUME_MASK 0x800000
+#define PB1_PIF_SC_CTL__SC_LANE_7_RESUME__SHIFT 0x17
+#define PB1_PIF_SC_CTL__SC_LANE_8_RESUME_MASK 0x1000000
+#define PB1_PIF_SC_CTL__SC_LANE_8_RESUME__SHIFT 0x18
+#define PB1_PIF_SC_CTL__SC_LANE_9_RESUME_MASK 0x2000000
+#define PB1_PIF_SC_CTL__SC_LANE_9_RESUME__SHIFT 0x19
+#define PB1_PIF_SC_CTL__SC_LANE_10_RESUME_MASK 0x4000000
+#define PB1_PIF_SC_CTL__SC_LANE_10_RESUME__SHIFT 0x1a
+#define PB1_PIF_SC_CTL__SC_LANE_11_RESUME_MASK 0x8000000
+#define PB1_PIF_SC_CTL__SC_LANE_11_RESUME__SHIFT 0x1b
+#define PB1_PIF_SC_CTL__SC_LANE_12_RESUME_MASK 0x10000000
+#define PB1_PIF_SC_CTL__SC_LANE_12_RESUME__SHIFT 0x1c
+#define PB1_PIF_SC_CTL__SC_LANE_13_RESUME_MASK 0x20000000
+#define PB1_PIF_SC_CTL__SC_LANE_13_RESUME__SHIFT 0x1d
+#define PB1_PIF_SC_CTL__SC_LANE_14_RESUME_MASK 0x40000000
+#define PB1_PIF_SC_CTL__SC_LANE_14_RESUME__SHIFT 0x1e
+#define PB1_PIF_SC_CTL__SC_LANE_15_RESUME_MASK 0x80000000
+#define PB1_PIF_SC_CTL__SC_LANE_15_RESUME__SHIFT 0x1f
+#define PB1_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2_MASK 0x7
+#define PB1_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2__SHIFT 0x0
+#define PB1_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2_MASK 0x8
+#define PB1_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2__SHIFT 0x3
+#define PB1_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2_MASK 0x70
+#define PB1_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2__SHIFT 0x4
+#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2_MASK 0x380
+#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2__SHIFT 0x7
+#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2_MASK 0x1c00
+#define PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2__SHIFT 0xa
+#define PB1_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2_MASK 0x10000
+#define PB1_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2__SHIFT 0x10
+#define PB1_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK 0x7000000
+#define PB1_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2__SHIFT 0x18
+#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2_MASK 0x10000000
+#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2__SHIFT 0x1c
+#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2_MASK 0xe0000000
+#define PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2__SHIFT 0x1d
+#define PB1_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3_MASK 0x7
+#define PB1_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3__SHIFT 0x0
+#define PB1_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3_MASK 0x8
+#define PB1_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3__SHIFT 0x3
+#define PB1_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3_MASK 0x70
+#define PB1_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3__SHIFT 0x4
+#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3_MASK 0x380
+#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3__SHIFT 0x7
+#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3_MASK 0x1c00
+#define PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3__SHIFT 0xa
+#define PB1_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3_MASK 0x10000
+#define PB1_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3__SHIFT 0x10
+#define PB1_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK 0x7000000
+#define PB1_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3__SHIFT 0x18
+#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3_MASK 0x10000000
+#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3__SHIFT 0x1c
+#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3_MASK 0xe0000000
+#define PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3__SHIFT 0x1d
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_0_MASK 0x1
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_0__SHIFT 0x0
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_1_MASK 0x2
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_1__SHIFT 0x1
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_2_MASK 0x4
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_2__SHIFT 0x2
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_3_MASK 0x8
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_3__SHIFT 0x3
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_4_MASK 0x10
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_4__SHIFT 0x4
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_5_MASK 0x20
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_5__SHIFT 0x5
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_6_MASK 0x40
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_6__SHIFT 0x6
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_7_MASK 0x80
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_7__SHIFT 0x7
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_8_MASK 0x100
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_8__SHIFT 0x8
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_9_MASK 0x200
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_9__SHIFT 0x9
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_10_MASK 0x400
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_10__SHIFT 0xa
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_11_MASK 0x800
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_11__SHIFT 0xb
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_12_MASK 0x1000
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_12__SHIFT 0xc
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_13_MASK 0x2000
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_13__SHIFT 0xd
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_14_MASK 0x4000
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_14__SHIFT 0xe
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_15_MASK 0x8000
+#define PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_15__SHIFT 0xf
+#define PB1_PIF_PRG0__PRG_RXDETECT_SAMPL_TIME_MASK 0x3ffff
+#define PB1_PIF_PRG0__PRG_RXDETECT_SAMPL_TIME__SHIFT 0x0
+#define PB1_PIF_PRG1__PRG_PLL_RAMP_UP_TIME_MASK 0x3ffff
+#define PB1_PIF_PRG1__PRG_PLL_RAMP_UP_TIME__SHIFT 0x0
+#define PB1_PIF_PRG2__PRG_SERVICE2_STEP4_DELAY_MASK 0x3ffff
+#define PB1_PIF_PRG2__PRG_SERVICE2_STEP4_DELAY__SHIFT 0x0
+#define PB1_PIF_PRG3__PRG_SERVICE3_STEP4_DELAY_MASK 0x3ffff
+#define PB1_PIF_PRG3__PRG_SERVICE3_STEP4_DELAY__SHIFT 0x0
+#define PB1_PIF_PRG4__PRG_SPEEDCHANGE_STEP2_DELAY_MASK 0x3ffff
+#define PB1_PIF_PRG4__PRG_SPEEDCHANGE_STEP2_DELAY__SHIFT 0x0
+#define PB1_PIF_PRG5__PRG_LS2_EXIT_TIME_MASK 0x3ffff
+#define PB1_PIF_PRG5__PRG_LS2_EXIT_TIME__SHIFT 0x0
+#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0_MASK 0x1
+#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0__SHIFT 0x0
+#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0_MASK 0xe
+#define PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0__SHIFT 0x1
+#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0_MASK 0x10
+#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0__SHIFT 0x4
+#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0_MASK 0xe0
+#define PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0__SHIFT 0x5
+#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0_MASK 0x100
+#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0__SHIFT 0x8
+#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0_MASK 0x200
+#define PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0__SHIFT 0x9
+#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0_MASK 0x400
+#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0__SHIFT 0xa
+#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0_MASK 0x3800
+#define PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0__SHIFT 0xb
+#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0_MASK 0x4000
+#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0__SHIFT 0xe
+#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0_MASK 0x38000
+#define PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0__SHIFT 0xf
+#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1_MASK 0x1
+#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1__SHIFT 0x0
+#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1_MASK 0xe
+#define PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1__SHIFT 0x1
+#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1_MASK 0x10
+#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1__SHIFT 0x4
+#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1_MASK 0xe0
+#define PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1__SHIFT 0x5
+#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1_MASK 0x100
+#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1__SHIFT 0x8
+#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1_MASK 0x200
+#define PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1__SHIFT 0x9
+#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1_MASK 0x400
+#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1__SHIFT 0xa
+#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1_MASK 0x3800
+#define PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1__SHIFT 0xb
+#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1_MASK 0x4000
+#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1__SHIFT 0xe
+#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1_MASK 0x38000
+#define PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1__SHIFT 0xf
+#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2_MASK 0x1
+#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2__SHIFT 0x0
+#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2_MASK 0xe
+#define PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2__SHIFT 0x1
+#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2_MASK 0x10
+#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2__SHIFT 0x4
+#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2_MASK 0xe0
+#define PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2__SHIFT 0x5
+#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2_MASK 0x100
+#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2__SHIFT 0x8
+#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2_MASK 0x200
+#define PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2__SHIFT 0x9
+#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2_MASK 0x400
+#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2__SHIFT 0xa
+#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2_MASK 0x3800
+#define PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2__SHIFT 0xb
+#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2_MASK 0x4000
+#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2__SHIFT 0xe
+#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2_MASK 0x38000
+#define PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2__SHIFT 0xf
+#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3_MASK 0x1
+#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3__SHIFT 0x0
+#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3_MASK 0xe
+#define PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3__SHIFT 0x1
+#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3_MASK 0x10
+#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3__SHIFT 0x4
+#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3_MASK 0xe0
+#define PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3__SHIFT 0x5
+#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3_MASK 0x100
+#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3__SHIFT 0x8
+#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3_MASK 0x200
+#define PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3__SHIFT 0x9
+#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3_MASK 0x400
+#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3__SHIFT 0xa
+#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3_MASK 0x3800
+#define PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3__SHIFT 0xb
+#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3_MASK 0x4000
+#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3__SHIFT 0xe
+#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3_MASK 0x38000
+#define PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3__SHIFT 0xf
+#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4_MASK 0x1
+#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4__SHIFT 0x0
+#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4_MASK 0xe
+#define PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4__SHIFT 0x1
+#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4_MASK 0x10
+#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4__SHIFT 0x4
+#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4_MASK 0xe0
+#define PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4__SHIFT 0x5
+#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4_MASK 0x100
+#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4__SHIFT 0x8
+#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4_MASK 0x200
+#define PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4__SHIFT 0x9
+#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4_MASK 0x400
+#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4__SHIFT 0xa
+#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4_MASK 0x3800
+#define PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4__SHIFT 0xb
+#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4_MASK 0x4000
+#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4__SHIFT 0xe
+#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4_MASK 0x38000
+#define PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4__SHIFT 0xf
+#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5_MASK 0x1
+#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5__SHIFT 0x0
+#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5_MASK 0xe
+#define PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5__SHIFT 0x1
+#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5_MASK 0x10
+#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5__SHIFT 0x4
+#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5_MASK 0xe0
+#define PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5__SHIFT 0x5
+#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5_MASK 0x100
+#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5__SHIFT 0x8
+#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5_MASK 0x200
+#define PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5__SHIFT 0x9
+#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5_MASK 0x400
+#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5__SHIFT 0xa
+#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5_MASK 0x3800
+#define PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5__SHIFT 0xb
+#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5_MASK 0x4000
+#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5__SHIFT 0xe
+#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5_MASK 0x38000
+#define PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5__SHIFT 0xf
+#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6_MASK 0x1
+#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6__SHIFT 0x0
+#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6_MASK 0xe
+#define PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6__SHIFT 0x1
+#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6_MASK 0x10
+#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6__SHIFT 0x4
+#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6_MASK 0xe0
+#define PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6__SHIFT 0x5
+#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6_MASK 0x100
+#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6__SHIFT 0x8
+#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6_MASK 0x200
+#define PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6__SHIFT 0x9
+#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6_MASK 0x400
+#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6__SHIFT 0xa
+#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6_MASK 0x3800
+#define PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6__SHIFT 0xb
+#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6_MASK 0x4000
+#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6__SHIFT 0xe
+#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6_MASK 0x38000
+#define PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6__SHIFT 0xf
+#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7_MASK 0x1
+#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7__SHIFT 0x0
+#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7_MASK 0xe
+#define PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7__SHIFT 0x1
+#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7_MASK 0x10
+#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7__SHIFT 0x4
+#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7_MASK 0xe0
+#define PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7__SHIFT 0x5
+#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7_MASK 0x100
+#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7__SHIFT 0x8
+#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7_MASK 0x200
+#define PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7__SHIFT 0x9
+#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7_MASK 0x400
+#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7__SHIFT 0xa
+#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7_MASK 0x3800
+#define PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7__SHIFT 0xb
+#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7_MASK 0x4000
+#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7__SHIFT 0xe
+#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7_MASK 0x38000
+#define PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7__SHIFT 0xf
+#define PB1_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0_MASK 0x1
+#define PB1_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0__SHIFT 0x0
+#define PB1_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0_MASK 0x2
+#define PB1_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0__SHIFT 0x1
+#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0_MASK 0x4
+#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0__SHIFT 0x2
+#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0_MASK 0x8
+#define PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0__SHIFT 0x3
+#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0_MASK 0x10
+#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0__SHIFT 0x4
+#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0_MASK 0x20
+#define PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0__SHIFT 0x5
+#define PB1_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0_MASK 0x40
+#define PB1_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0__SHIFT 0x6
+#define PB1_PIF_SEQ_STATUS_0__SEQ_PHASE_0_MASK 0x700
+#define PB1_PIF_SEQ_STATUS_0__SEQ_PHASE_0__SHIFT 0x8
+#define PB1_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1_MASK 0x1
+#define PB1_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1__SHIFT 0x0
+#define PB1_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1_MASK 0x2
+#define PB1_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1__SHIFT 0x1
+#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1_MASK 0x4
+#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1__SHIFT 0x2
+#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1_MASK 0x8
+#define PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1__SHIFT 0x3
+#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1_MASK 0x10
+#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1__SHIFT 0x4
+#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1_MASK 0x20
+#define PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1__SHIFT 0x5
+#define PB1_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1_MASK 0x40
+#define PB1_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1__SHIFT 0x6
+#define PB1_PIF_SEQ_STATUS_1__SEQ_PHASE_1_MASK 0x700
+#define PB1_PIF_SEQ_STATUS_1__SEQ_PHASE_1__SHIFT 0x8
+#define PB1_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2_MASK 0x1
+#define PB1_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2__SHIFT 0x0
+#define PB1_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2_MASK 0x2
+#define PB1_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2__SHIFT 0x1
+#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2_MASK 0x4
+#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2__SHIFT 0x2
+#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2_MASK 0x8
+#define PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2__SHIFT 0x3
+#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2_MASK 0x10
+#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2__SHIFT 0x4
+#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2_MASK 0x20
+#define PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2__SHIFT 0x5
+#define PB1_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2_MASK 0x40
+#define PB1_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2__SHIFT 0x6
+#define PB1_PIF_SEQ_STATUS_2__SEQ_PHASE_2_MASK 0x700
+#define PB1_PIF_SEQ_STATUS_2__SEQ_PHASE_2__SHIFT 0x8
+#define PB1_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3_MASK 0x1
+#define PB1_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3__SHIFT 0x0
+#define PB1_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3_MASK 0x2
+#define PB1_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3__SHIFT 0x1
+#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3_MASK 0x4
+#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3__SHIFT 0x2
+#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3_MASK 0x8
+#define PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3__SHIFT 0x3
+#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3_MASK 0x10
+#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3__SHIFT 0x4
+#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3_MASK 0x20
+#define PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3__SHIFT 0x5
+#define PB1_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3_MASK 0x40
+#define PB1_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3__SHIFT 0x6
+#define PB1_PIF_SEQ_STATUS_3__SEQ_PHASE_3_MASK 0x700
+#define PB1_PIF_SEQ_STATUS_3__SEQ_PHASE_3__SHIFT 0x8
+#define PB1_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4_MASK 0x1
+#define PB1_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4__SHIFT 0x0
+#define PB1_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4_MASK 0x2
+#define PB1_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4__SHIFT 0x1
+#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4_MASK 0x4
+#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4__SHIFT 0x2
+#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4_MASK 0x8
+#define PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4__SHIFT 0x3
+#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4_MASK 0x10
+#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4__SHIFT 0x4
+#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4_MASK 0x20
+#define PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4__SHIFT 0x5
+#define PB1_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4_MASK 0x40
+#define PB1_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4__SHIFT 0x6
+#define PB1_PIF_SEQ_STATUS_4__SEQ_PHASE_4_MASK 0x700
+#define PB1_PIF_SEQ_STATUS_4__SEQ_PHASE_4__SHIFT 0x8
+#define PB1_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5_MASK 0x1
+#define PB1_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5__SHIFT 0x0
+#define PB1_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5_MASK 0x2
+#define PB1_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5__SHIFT 0x1
+#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5_MASK 0x4
+#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5__SHIFT 0x2
+#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5_MASK 0x8
+#define PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5__SHIFT 0x3
+#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5_MASK 0x10
+#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5__SHIFT 0x4
+#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5_MASK 0x20
+#define PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5__SHIFT 0x5
+#define PB1_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5_MASK 0x40
+#define PB1_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5__SHIFT 0x6
+#define PB1_PIF_SEQ_STATUS_5__SEQ_PHASE_5_MASK 0x700
+#define PB1_PIF_SEQ_STATUS_5__SEQ_PHASE_5__SHIFT 0x8
+#define PB1_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6_MASK 0x1
+#define PB1_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6__SHIFT 0x0
+#define PB1_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6_MASK 0x2
+#define PB1_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6__SHIFT 0x1
+#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6_MASK 0x4
+#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6__SHIFT 0x2
+#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6_MASK 0x8
+#define PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6__SHIFT 0x3
+#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6_MASK 0x10
+#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6__SHIFT 0x4
+#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6_MASK 0x20
+#define PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6__SHIFT 0x5
+#define PB1_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6_MASK 0x40
+#define PB1_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6__SHIFT 0x6
+#define PB1_PIF_SEQ_STATUS_6__SEQ_PHASE_6_MASK 0x700
+#define PB1_PIF_SEQ_STATUS_6__SEQ_PHASE_6__SHIFT 0x8
+#define PB1_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7_MASK 0x1
+#define PB1_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7__SHIFT 0x0
+#define PB1_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7_MASK 0x2
+#define PB1_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7__SHIFT 0x1
+#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7_MASK 0x4
+#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7__SHIFT 0x2
+#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7_MASK 0x8
+#define PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7__SHIFT 0x3
+#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7_MASK 0x10
+#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7__SHIFT 0x4
+#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7_MASK 0x20
+#define PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7__SHIFT 0x5
+#define PB1_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7_MASK 0x40
+#define PB1_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7__SHIFT 0x6
+#define PB1_PIF_SEQ_STATUS_7__SEQ_PHASE_7_MASK 0x700
+#define PB1_PIF_SEQ_STATUS_7__SEQ_PHASE_7__SHIFT 0x8
+#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8_MASK 0x1
+#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8__SHIFT 0x0
+#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8_MASK 0xe
+#define PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8__SHIFT 0x1
+#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8_MASK 0x10
+#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8__SHIFT 0x4
+#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8_MASK 0xe0
+#define PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8__SHIFT 0x5
+#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8_MASK 0x100
+#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8__SHIFT 0x8
+#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8_MASK 0x200
+#define PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8__SHIFT 0x9
+#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8_MASK 0x400
+#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8__SHIFT 0xa
+#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8_MASK 0x3800
+#define PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8__SHIFT 0xb
+#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8_MASK 0x4000
+#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8__SHIFT 0xe
+#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8_MASK 0x38000
+#define PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8__SHIFT 0xf
+#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9_MASK 0x1
+#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9__SHIFT 0x0
+#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9_MASK 0xe
+#define PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9__SHIFT 0x1
+#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9_MASK 0x10
+#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9__SHIFT 0x4
+#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9_MASK 0xe0
+#define PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9__SHIFT 0x5
+#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9_MASK 0x100
+#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9__SHIFT 0x8
+#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9_MASK 0x200
+#define PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9__SHIFT 0x9
+#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9_MASK 0x400
+#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9__SHIFT 0xa
+#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9_MASK 0x3800
+#define PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9__SHIFT 0xb
+#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9_MASK 0x4000
+#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9__SHIFT 0xe
+#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9_MASK 0x38000
+#define PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9__SHIFT 0xf
+#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10_MASK 0x1
+#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10__SHIFT 0x0
+#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10_MASK 0xe
+#define PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10__SHIFT 0x1
+#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10_MASK 0x10
+#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10__SHIFT 0x4
+#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10_MASK 0xe0
+#define PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10__SHIFT 0x5
+#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10_MASK 0x100
+#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10__SHIFT 0x8
+#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10_MASK 0x200
+#define PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10__SHIFT 0x9
+#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10_MASK 0x400
+#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10__SHIFT 0xa
+#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10_MASK 0x3800
+#define PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10__SHIFT 0xb
+#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10_MASK 0x4000
+#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10__SHIFT 0xe
+#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10_MASK 0x38000
+#define PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10__SHIFT 0xf
+#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11_MASK 0x1
+#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11__SHIFT 0x0
+#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11_MASK 0xe
+#define PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11__SHIFT 0x1
+#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11_MASK 0x10
+#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11__SHIFT 0x4
+#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11_MASK 0xe0
+#define PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11__SHIFT 0x5
+#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11_MASK 0x100
+#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11__SHIFT 0x8
+#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11_MASK 0x200
+#define PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11__SHIFT 0x9
+#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11_MASK 0x400
+#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11__SHIFT 0xa
+#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11_MASK 0x3800
+#define PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11__SHIFT 0xb
+#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11_MASK 0x4000
+#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11__SHIFT 0xe
+#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11_MASK 0x38000
+#define PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11__SHIFT 0xf
+#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12_MASK 0x1
+#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12__SHIFT 0x0
+#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12_MASK 0xe
+#define PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12__SHIFT 0x1
+#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12_MASK 0x10
+#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12__SHIFT 0x4
+#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12_MASK 0xe0
+#define PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12__SHIFT 0x5
+#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12_MASK 0x100
+#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12__SHIFT 0x8
+#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12_MASK 0x200
+#define PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12__SHIFT 0x9
+#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12_MASK 0x400
+#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12__SHIFT 0xa
+#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12_MASK 0x3800
+#define PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12__SHIFT 0xb
+#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12_MASK 0x4000
+#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12__SHIFT 0xe
+#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12_MASK 0x38000
+#define PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12__SHIFT 0xf
+#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13_MASK 0x1
+#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13__SHIFT 0x0
+#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13_MASK 0xe
+#define PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13__SHIFT 0x1
+#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13_MASK 0x10
+#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13__SHIFT 0x4
+#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13_MASK 0xe0
+#define PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13__SHIFT 0x5
+#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13_MASK 0x100
+#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13__SHIFT 0x8
+#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13_MASK 0x200
+#define PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13__SHIFT 0x9
+#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13_MASK 0x400
+#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13__SHIFT 0xa
+#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13_MASK 0x3800
+#define PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13__SHIFT 0xb
+#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13_MASK 0x4000
+#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13__SHIFT 0xe
+#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13_MASK 0x38000
+#define PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13__SHIFT 0xf
+#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14_MASK 0x1
+#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14__SHIFT 0x0
+#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14_MASK 0xe
+#define PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14__SHIFT 0x1
+#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14_MASK 0x10
+#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14__SHIFT 0x4
+#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14_MASK 0xe0
+#define PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14__SHIFT 0x5
+#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14_MASK 0x100
+#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14__SHIFT 0x8
+#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14_MASK 0x200
+#define PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14__SHIFT 0x9
+#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14_MASK 0x400
+#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14__SHIFT 0xa
+#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14_MASK 0x3800
+#define PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14__SHIFT 0xb
+#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14_MASK 0x4000
+#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14__SHIFT 0xe
+#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14_MASK 0x38000
+#define PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14__SHIFT 0xf
+#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15_MASK 0x1
+#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15__SHIFT 0x0
+#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15_MASK 0xe
+#define PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15__SHIFT 0x1
+#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15_MASK 0x10
+#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15__SHIFT 0x4
+#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15_MASK 0xe0
+#define PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15__SHIFT 0x5
+#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15_MASK 0x100
+#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15__SHIFT 0x8
+#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15_MASK 0x200
+#define PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15__SHIFT 0x9
+#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15_MASK 0x400
+#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15__SHIFT 0xa
+#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15_MASK 0x3800
+#define PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15__SHIFT 0xb
+#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15_MASK 0x4000
+#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15__SHIFT 0xe
+#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15_MASK 0x38000
+#define PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15__SHIFT 0xf
+#define PB1_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8_MASK 0x1
+#define PB1_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8__SHIFT 0x0
+#define PB1_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8_MASK 0x2
+#define PB1_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8__SHIFT 0x1
+#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8_MASK 0x4
+#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8__SHIFT 0x2
+#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8_MASK 0x8
+#define PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8__SHIFT 0x3
+#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8_MASK 0x10
+#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8__SHIFT 0x4
+#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8_MASK 0x20
+#define PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8__SHIFT 0x5
+#define PB1_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8_MASK 0x40
+#define PB1_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8__SHIFT 0x6
+#define PB1_PIF_SEQ_STATUS_8__SEQ_PHASE_8_MASK 0x700
+#define PB1_PIF_SEQ_STATUS_8__SEQ_PHASE_8__SHIFT 0x8
+#define PB1_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9_MASK 0x1
+#define PB1_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9__SHIFT 0x0
+#define PB1_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9_MASK 0x2
+#define PB1_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9__SHIFT 0x1
+#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9_MASK 0x4
+#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9__SHIFT 0x2
+#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9_MASK 0x8
+#define PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9__SHIFT 0x3
+#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9_MASK 0x10
+#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9__SHIFT 0x4
+#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9_MASK 0x20
+#define PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9__SHIFT 0x5
+#define PB1_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9_MASK 0x40
+#define PB1_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9__SHIFT 0x6
+#define PB1_PIF_SEQ_STATUS_9__SEQ_PHASE_9_MASK 0x700
+#define PB1_PIF_SEQ_STATUS_9__SEQ_PHASE_9__SHIFT 0x8
+#define PB1_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10_MASK 0x1
+#define PB1_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10__SHIFT 0x0
+#define PB1_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10_MASK 0x2
+#define PB1_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10__SHIFT 0x1
+#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10_MASK 0x4
+#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10__SHIFT 0x2
+#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10_MASK 0x8
+#define PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10__SHIFT 0x3
+#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10_MASK 0x10
+#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10__SHIFT 0x4
+#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10_MASK 0x20
+#define PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10__SHIFT 0x5
+#define PB1_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10_MASK 0x40
+#define PB1_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10__SHIFT 0x6
+#define PB1_PIF_SEQ_STATUS_10__SEQ_PHASE_10_MASK 0x700
+#define PB1_PIF_SEQ_STATUS_10__SEQ_PHASE_10__SHIFT 0x8
+#define PB1_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11_MASK 0x1
+#define PB1_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11__SHIFT 0x0
+#define PB1_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11_MASK 0x2
+#define PB1_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11__SHIFT 0x1
+#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11_MASK 0x4
+#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11__SHIFT 0x2
+#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11_MASK 0x8
+#define PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11__SHIFT 0x3
+#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11_MASK 0x10
+#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11__SHIFT 0x4
+#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11_MASK 0x20
+#define PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11__SHIFT 0x5
+#define PB1_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11_MASK 0x40
+#define PB1_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11__SHIFT 0x6
+#define PB1_PIF_SEQ_STATUS_11__SEQ_PHASE_11_MASK 0x700
+#define PB1_PIF_SEQ_STATUS_11__SEQ_PHASE_11__SHIFT 0x8
+#define PB1_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12_MASK 0x1
+#define PB1_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12__SHIFT 0x0
+#define PB1_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12_MASK 0x2
+#define PB1_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12__SHIFT 0x1
+#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12_MASK 0x4
+#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12__SHIFT 0x2
+#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12_MASK 0x8
+#define PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12__SHIFT 0x3
+#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12_MASK 0x10
+#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12__SHIFT 0x4
+#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12_MASK 0x20
+#define PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12__SHIFT 0x5
+#define PB1_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12_MASK 0x40
+#define PB1_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12__SHIFT 0x6
+#define PB1_PIF_SEQ_STATUS_12__SEQ_PHASE_12_MASK 0x700
+#define PB1_PIF_SEQ_STATUS_12__SEQ_PHASE_12__SHIFT 0x8
+#define PB1_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13_MASK 0x1
+#define PB1_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13__SHIFT 0x0
+#define PB1_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13_MASK 0x2
+#define PB1_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13__SHIFT 0x1
+#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13_MASK 0x4
+#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13__SHIFT 0x2
+#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13_MASK 0x8
+#define PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13__SHIFT 0x3
+#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13_MASK 0x10
+#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13__SHIFT 0x4
+#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13_MASK 0x20
+#define PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13__SHIFT 0x5
+#define PB1_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13_MASK 0x40
+#define PB1_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13__SHIFT 0x6
+#define PB1_PIF_SEQ_STATUS_13__SEQ_PHASE_13_MASK 0x700
+#define PB1_PIF_SEQ_STATUS_13__SEQ_PHASE_13__SHIFT 0x8
+#define PB1_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14_MASK 0x1
+#define PB1_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14__SHIFT 0x0
+#define PB1_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14_MASK 0x2
+#define PB1_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14__SHIFT 0x1
+#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14_MASK 0x4
+#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14__SHIFT 0x2
+#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14_MASK 0x8
+#define PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14__SHIFT 0x3
+#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14_MASK 0x10
+#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14__SHIFT 0x4
+#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14_MASK 0x20
+#define PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14__SHIFT 0x5
+#define PB1_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14_MASK 0x40
+#define PB1_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14__SHIFT 0x6
+#define PB1_PIF_SEQ_STATUS_14__SEQ_PHASE_14_MASK 0x700
+#define PB1_PIF_SEQ_STATUS_14__SEQ_PHASE_14__SHIFT 0x8
+#define PB1_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15_MASK 0x1
+#define PB1_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15__SHIFT 0x0
+#define PB1_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15_MASK 0x2
+#define PB1_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15__SHIFT 0x1
+#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15_MASK 0x4
+#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15__SHIFT 0x2
+#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15_MASK 0x8
+#define PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15__SHIFT 0x3
+#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15_MASK 0x10
+#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15__SHIFT 0x4
+#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15_MASK 0x20
+#define PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15__SHIFT 0x5
+#define PB1_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15_MASK 0x40
+#define PB1_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15__SHIFT 0x6
+#define PB1_PIF_SEQ_STATUS_15__SEQ_PHASE_15_MASK 0x700
+#define PB1_PIF_SEQ_STATUS_15__SEQ_PHASE_15__SHIFT 0x8
+#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER_MASK 0x1
+#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER__SHIFT 0x0
+#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER_MASK 0x2
+#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER__SHIFT 0x1
+#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn_MASK 0x1
+#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn__SHIFT 0x0
+#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstImpEn_MASK 0x2
+#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstImpEn__SHIFT 0x1
+#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer_MASK 0xffff
+#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer__SHIFT 0x0
+#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn_MASK 0x40000000
+#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn__SHIFT 0x1e
+#define BIF_RFE_SOFTRST_CNTL__SoftRstReg_MASK 0x80000000
+#define BIF_RFE_SOFTRST_CNTL__SoftRstReg__SHIFT 0x1f
+#define BIF_RFE_IMPRST_CNTL__REG_RST_impEn_MASK 0x1
+#define BIF_RFE_IMPRST_CNTL__REG_RST_impEn__SHIFT 0x0
+#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWDBIF_rst_MASK 0x1
+#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWDBIF_rst__SHIFT 0x0
+#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWDBIF_rst_MASK 0x2
+#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWDBIF_rst__SHIFT 0x1
+#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BU_rst_MASK 0x1
+#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BU_rst__SHIFT 0x0
+#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWDBIF_rst_MASK 0x2
+#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWDBIF_rst__SHIFT 0x1
+#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst_MASK 0x4
+#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst__SHIFT 0x2
+#define BIF_PWDN_COMMAND__REG_BU_pw_cmd_MASK 0x1
+#define BIF_PWDN_COMMAND__REG_BU_pw_cmd__SHIFT 0x0
+#define BIF_PWDN_COMMAND__REG_RWREG_RFEWDBIF_pw_cmd_MASK 0x2
+#define BIF_PWDN_COMMAND__REG_RWREG_RFEWDBIF_pw_cmd__SHIFT 0x1
+#define BIF_PWDN_COMMAND__REG_BX_pw_cmd_MASK 0x4
+#define BIF_PWDN_COMMAND__REG_BX_pw_cmd__SHIFT 0x2
+#define BIF_PWDN_STATUS__BU_REG_pw_status_MASK 0x1
+#define BIF_PWDN_STATUS__BU_REG_pw_status__SHIFT 0x0
+#define BIF_PWDN_STATUS__RWREG_RFEWDBIF_REG_pw_status_MASK 0x2
+#define BIF_PWDN_STATUS__RWREG_RFEWDBIF_REG_pw_status__SHIFT 0x1
+#define BIF_PWDN_STATUS__BX_REG_pw_status_MASK 0x4
+#define BIF_PWDN_STATUS__BX_REG_pw_status__SHIFT 0x2
+#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkGate_timer_MASK 0xff
+#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkGate_timer__SHIFT 0x0
+#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkSetup_timer_MASK 0xf00
+#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkSetup_timer__SHIFT 0x8
+#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_timeout_timer_MASK 0xff0000
+#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_timeout_timer__SHIFT 0x10
+#define BIF_RFE_MST_BU_CMDSTATUS__BU_RFE_mstTimeout_MASK 0x1000000
+#define BIF_RFE_MST_BU_CMDSTATUS__BU_RFE_mstTimeout__SHIFT 0x18
+#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkGate_timer_MASK 0xff
+#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkGate_timer__SHIFT 0x0
+#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkSetup_timer_MASK 0xf00
+#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkSetup_timer__SHIFT 0x8
+#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_timeout_timer_MASK 0xff0000
+#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_timeout_timer__SHIFT 0x10
+#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__RWREG_RFEWDBIF_RFE_mstTimeout_MASK 0x1000000
+#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__RWREG_RFEWDBIF_RFE_mstTimeout__SHIFT 0x18
+#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer_MASK 0xff
+#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer__SHIFT 0x0
+#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer_MASK 0xf00
+#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer__SHIFT 0x8
+#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer_MASK 0xff0000
+#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer__SHIFT 0x10
+#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout_MASK 0x1000000
+#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout__SHIFT 0x18
+#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus_MASK 0x1
+#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus__SHIFT 0x0
+#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN_MASK 0x1
+#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN__SHIFT 0x0
+#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL_MASK 0xe
+#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL__SHIFT 0x1
+#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN_MASK 0x10
+#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN__SHIFT 0x4
+#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL_MASK 0xe0
+#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL__SHIFT 0x5
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_MASK 0x1e
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL__SHIFT 0x1
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_EN_MASK 0x20
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_EN__SHIFT 0x5
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PD_MASK 0x3c0
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PD__SHIFT 0x6
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PD_MASK 0x400
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PD__SHIFT 0xa
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PU_MASK 0x7800
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PU__SHIFT 0xb
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PU_MASK 0x8000
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PU__SHIFT 0xf
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_DBG_ANALOG_EN_MASK 0x10000
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_DBG_ANALOG_EN__SHIFT 0x10
+#define BIF_IMPCTL_SMPLCNTL__FORCE_DONE_MASK 0x1
+#define BIF_IMPCTL_SMPLCNTL__FORCE_DONE__SHIFT 0x0
+#define BIF_IMPCTL_SMPLCNTL__RxPDNB_MASK 0x2
+#define BIF_IMPCTL_SMPLCNTL__RxPDNB__SHIFT 0x1
+#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pd_MASK 0x4
+#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pd__SHIFT 0x2
+#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pu_MASK 0x8
+#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pu__SHIFT 0x3
+#define BIF_IMPCTL_SMPLCNTL__SAMPLE_PERIOD_MASK 0x1f00
+#define BIF_IMPCTL_SMPLCNTL__SAMPLE_PERIOD__SHIFT 0x8
+#define BIF_IMPCTL_SMPLCNTL__EXTEND_SAMPLES_MASK 0x2000
+#define BIF_IMPCTL_SMPLCNTL__EXTEND_SAMPLES__SHIFT 0xd
+#define BIF_IMPCTL_SMPLCNTL__FORCE_ENABLE_MASK 0x4000
+#define BIF_IMPCTL_SMPLCNTL__FORCE_ENABLE__SHIFT 0xe
+#define BIF_IMPCTL_SMPLCNTL__SETUP_TIME_MASK 0xf8000
+#define BIF_IMPCTL_SMPLCNTL__SETUP_TIME__SHIFT 0xf
+#define BIF_IMPCTL_SMPLCNTL__LOWER_SAMPLE_THRESH_MASK 0x3f00000
+#define BIF_IMPCTL_SMPLCNTL__LOWER_SAMPLE_THRESH__SHIFT 0x14
+#define BIF_IMPCTL_SMPLCNTL__UPPER_SAMPLE_THRESH_MASK 0xfc000000
+#define BIF_IMPCTL_SMPLCNTL__UPPER_SAMPLE_THRESH__SHIFT 0x1a
+#define BIF_IMPCTL_RXCNTL__RX_ADJUST_MASK 0x7
+#define BIF_IMPCTL_RXCNTL__RX_ADJUST__SHIFT 0x0
+#define BIF_IMPCTL_RXCNTL__RX_BIAS_HIGH_MASK 0x8
+#define BIF_IMPCTL_RXCNTL__RX_BIAS_HIGH__SHIFT 0x3
+#define BIF_IMPCTL_RXCNTL__CONT_AFTER_RX_DECT_MASK 0x10
+#define BIF_IMPCTL_RXCNTL__CONT_AFTER_RX_DECT__SHIFT 0x4
+#define BIF_IMPCTL_RXCNTL__SUSPEND_MASK 0x40
+#define BIF_IMPCTL_RXCNTL__SUSPEND__SHIFT 0x6
+#define BIF_IMPCTL_RXCNTL__FORCE_RST_MASK 0x80
+#define BIF_IMPCTL_RXCNTL__FORCE_RST__SHIFT 0x7
+#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_THRESH_MASK 0xf00
+#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_THRESH__SHIFT 0x8
+#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_MASK 0x1000
+#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ__SHIFT 0xc
+#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_THRESH_MASK 0x1e000
+#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_THRESH__SHIFT 0xd
+#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_MASK 0x20000
+#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ__SHIFT 0x11
+#define BIF_IMPCTL_RXCNTL__RX_IMP_LOCKED_MASK 0x40000
+#define BIF_IMPCTL_RXCNTL__RX_IMP_LOCKED__SHIFT 0x12
+#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_SEL_MASK 0x80000
+#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_SEL__SHIFT 0x13
+#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_MASK 0xf00000
+#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK__SHIFT 0x14
+#define BIF_IMPCTL_RXCNTL__RX_CMP_AMBIG_MASK 0x10000000
+#define BIF_IMPCTL_RXCNTL__RX_CMP_AMBIG__SHIFT 0x1c
+#define BIF_IMPCTL_RXCNTL__CAL_DONE_MASK 0x20000000
+#define BIF_IMPCTL_RXCNTL__CAL_DONE__SHIFT 0x1d
+#define BIF_IMPCTL_TXCNTL_pd__TX_ADJUST_pd_MASK 0x7
+#define BIF_IMPCTL_TXCNTL_pd__TX_ADJUST_pd__SHIFT 0x0
+#define BIF_IMPCTL_TXCNTL_pd__TX_BIAS_HIGH_pd_MASK 0x8
+#define BIF_IMPCTL_TXCNTL_pd__TX_BIAS_HIGH_pd__SHIFT 0x3
+#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_THRESH_pd_MASK 0xf00
+#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_THRESH_pd__SHIFT 0x8
+#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_pd_MASK 0x1000
+#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_pd__SHIFT 0xc
+#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_THRESH_pd_MASK 0x1e000
+#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_THRESH_pd__SHIFT 0xd
+#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_pd_MASK 0x20000
+#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_pd__SHIFT 0x11
+#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_LOCKED_pd_MASK 0x40000
+#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_LOCKED_pd__SHIFT 0x12
+#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_SEL_pd_MASK 0x80000
+#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_SEL_pd__SHIFT 0x13
+#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_pd_MASK 0xf00000
+#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_pd__SHIFT 0x14
+#define BIF_IMPCTL_TXCNTL_pd__TX_CMP_AMBIG_pd_MASK 0x10000000
+#define BIF_IMPCTL_TXCNTL_pd__TX_CMP_AMBIG_pd__SHIFT 0x1c
+#define BIF_IMPCTL_TXCNTL_pu__TX_ADJUST_pu_MASK 0x7
+#define BIF_IMPCTL_TXCNTL_pu__TX_ADJUST_pu__SHIFT 0x0
+#define BIF_IMPCTL_TXCNTL_pu__TX_BIAS_HIGH_pu_MASK 0x8
+#define BIF_IMPCTL_TXCNTL_pu__TX_BIAS_HIGH_pu__SHIFT 0x3
+#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_THRESH_pu_MASK 0xf00
+#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_THRESH_pu__SHIFT 0x8
+#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_pu_MASK 0x1000
+#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_pu__SHIFT 0xc
+#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_THRESH_pu_MASK 0x1e000
+#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_THRESH_pu__SHIFT 0xd
+#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_pu_MASK 0x20000
+#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_pu__SHIFT 0x11
+#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_LOCKED_pu_MASK 0x40000
+#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_LOCKED_pu__SHIFT 0x12
+#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_SEL_pu_MASK 0x80000
+#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_SEL_pu__SHIFT 0x13
+#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_pu_MASK 0xf00000
+#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_pu__SHIFT 0x14
+#define BIF_IMPCTL_TXCNTL_pu__TX_CMP_AMBIG_pu_MASK 0x10000000
+#define BIF_IMPCTL_TXCNTL_pu__TX_CMP_AMBIG_pu__SHIFT 0x1c
+#define BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__UPDATE_PERIOD_MASK 0xffffffff
+#define BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__UPDATE_PERIOD__SHIFT 0x0
+#define BIF_CLOCKS_BITS__OBFF_XSL_FORCE_REFCLK_MASK 0x1
+#define BIF_CLOCKS_BITS__OBFF_XSL_FORCE_REFCLK__SHIFT 0x0
+#define BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK 0x1
+#define BIF_LNCNT_RESET__RESET_LNCNT_EN__SHIFT 0x0
+#define LNCNT_CONTROL__LNCNT_ACC_MODE_MASK 0x1
+#define LNCNT_CONTROL__LNCNT_ACC_MODE__SHIFT 0x0
+#define LNCNT_CONTROL__LNCNT_REF_TIMEBASE_MASK 0x6
+#define LNCNT_CONTROL__LNCNT_REF_TIMEBASE__SHIFT 0x1
+#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN_MASK 0x1
+#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN__SHIFT 0x0
+#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER_MASK 0x1ffffe
+#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER__SHIFT 0x1
+#define NEW_REFCLKB_TIMER__REFCLK_ON_MASK 0x200000
+#define NEW_REFCLKB_TIMER__REFCLK_ON__SHIFT 0x15
+#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER_MASK 0x3ff
+#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER__SHIFT 0x0
+#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN_MASK 0x400
+#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN__SHIFT 0xa
+#define BIF_CLK_PDWN_DELAY_TIMER__TIMER_MASK 0x3ff
+#define BIF_CLK_PDWN_DELAY_TIMER__TIMER__SHIFT 0x0
+#define BIF_RESET_EN__SOFT_RST_MODE_MASK 0x2
+#define BIF_RESET_EN__SOFT_RST_MODE__SHIFT 0x1
+#define BIF_RESET_EN__PHY_RESET_EN_MASK 0x4
+#define BIF_RESET_EN__PHY_RESET_EN__SHIFT 0x2
+#define BIF_RESET_EN__COR_RESET_EN_MASK 0x8
+#define BIF_RESET_EN__COR_RESET_EN__SHIFT 0x3
+#define BIF_RESET_EN__REG_RESET_EN_MASK 0x10
+#define BIF_RESET_EN__REG_RESET_EN__SHIFT 0x4
+#define BIF_RESET_EN__STY_RESET_EN_MASK 0x20
+#define BIF_RESET_EN__STY_RESET_EN__SHIFT 0x5
+#define BIF_RESET_EN__CFG_RESET_EN_MASK 0x40
+#define BIF_RESET_EN__CFG_RESET_EN__SHIFT 0x6
+#define BIF_RESET_EN__DRV_RESET_EN_MASK 0x80
+#define BIF_RESET_EN__DRV_RESET_EN__SHIFT 0x7
+#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN_MASK 0x100
+#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN__SHIFT 0x8
+#define BIF_RESET_EN__HOT_RESET_EN_MASK 0x200
+#define BIF_RESET_EN__HOT_RESET_EN__SHIFT 0x9
+#define BIF_RESET_EN__LINK_DISABLE_RESET_EN_MASK 0x400
+#define BIF_RESET_EN__LINK_DISABLE_RESET_EN__SHIFT 0xa
+#define BIF_RESET_EN__LINK_DOWN_RESET_EN_MASK 0x800
+#define BIF_RESET_EN__LINK_DOWN_RESET_EN__SHIFT 0xb
+#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH_MASK 0x3f000
+#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH__SHIFT 0xc
+#define BIF_RESET_EN__DRV_RESET_DELAY_SEL_MASK 0xc0000
+#define BIF_RESET_EN__DRV_RESET_DELAY_SEL__SHIFT 0x12
+#define BIF_RESET_EN__PIF_RSTB_EN_MASK 0x100000
+#define BIF_RESET_EN__PIF_RSTB_EN__SHIFT 0x14
+#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN_MASK 0x200000
+#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN__SHIFT 0x15
+#define BIF_RESET_EN__BIF_COR_RESET_EN_MASK 0x400000
+#define BIF_RESET_EN__BIF_COR_RESET_EN__SHIFT 0x16
+#define BIF_RESET_EN__FUNC0_FLR_EN_MASK 0x800000
+#define BIF_RESET_EN__FUNC0_FLR_EN__SHIFT 0x17
+#define BIF_RESET_EN__FUNC1_FLR_EN_MASK 0x1000000
+#define BIF_RESET_EN__FUNC1_FLR_EN__SHIFT 0x18
+#define BIF_RESET_EN__FUNC2_FLR_EN_MASK 0x2000000
+#define BIF_RESET_EN__FUNC2_FLR_EN__SHIFT 0x19
+#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL_MASK 0xc000000
+#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL__SHIFT 0x1a
+#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL_MASK 0x30000000
+#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL__SHIFT 0x1c
+#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL_MASK 0xc0000000
+#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL__SHIFT 0x1e
+#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER_MASK 0x7
+#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER__SHIFT 0x0
+#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER_MASK 0x38
+#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER__SHIFT 0x3
+#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER_MASK 0x3c0
+#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER__SHIFT 0x6
+#define BIF_BACO_MSIC__BIF_XTALIN_SEL_MASK 0x1
+#define BIF_BACO_MSIC__BIF_XTALIN_SEL__SHIFT 0x0
+#define BIF_BACO_MSIC__BACO_LINK_RST_SEL_MASK 0x6
+#define BIF_BACO_MSIC__BACO_LINK_RST_SEL__SHIFT 0x1
+#define BIF_RESET_CNTL__STRAP_EN_MASK 0x1
+#define BIF_RESET_CNTL__STRAP_EN__SHIFT 0x0
+#define BIF_RESET_CNTL__RST_DONE_MASK 0x2
+#define BIF_RESET_CNTL__RST_DONE__SHIFT 0x1
+#define BIF_RESET_CNTL__LINK_TRAIN_EN_MASK 0x4
+#define BIF_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x2
+#define BIF_RESET_CNTL__STRAP_ALL_VALID_MASK 0x8
+#define BIF_RESET_CNTL__STRAP_ALL_VALID__SHIFT 0x3
+#define BIF_RESET_CNTL__RECAP_STRAP_WARMRST_MASK 0x100
+#define BIF_RESET_CNTL__RECAP_STRAP_WARMRST__SHIFT 0x8
+#define BIF_RESET_CNTL__HOLD_LKTRN_WARMRST_DIS_MASK 0x200
+#define BIF_RESET_CNTL__HOLD_LKTRN_WARMRST_DIS__SHIFT 0x9
+#define BIF_RFE_CNTL_MISC__ADAPT_pif0_bu_reg_accessMode_MASK 0x1
+#define BIF_RFE_CNTL_MISC__ADAPT_pif0_bu_reg_accessMode__SHIFT 0x0
+#define BIF_RFE_CNTL_MISC__ADAPT_pif1_bu_reg_accessMode_MASK 0x2
+#define BIF_RFE_CNTL_MISC__ADAPT_pif1_bu_reg_accessMode__SHIFT 0x1
+#define BIF_RFE_CNTL_MISC__ADAPT_pwreg_bu_reg_accessMode_MASK 0x4
+#define BIF_RFE_CNTL_MISC__ADAPT_pwreg_bu_reg_accessMode__SHIFT 0x2
+#define BIF_RFE_CNTL_MISC__ADAPT_pciecore0_bu_reg_accessMode_MASK 0x8
+#define BIF_RFE_CNTL_MISC__ADAPT_pciecore0_bu_reg_accessMode__SHIFT 0x3
+
+#endif /* BIF_4_1_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h
new file mode 100644
index 000000000000..92b6ba0047af
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_d.h
@@ -0,0 +1,1068 @@
+/*
+ * BIF_5_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef BIF_5_0_D_H
+#define BIF_5_0_D_H
+
+#define mmMM_INDEX 0x0
+#define mmMM_INDEX_HI 0x6
+#define mmMM_DATA 0x1
+#define mmBIF_MM_INDACCESS_CNTL 0x1500
+#define mmBIF_DOORBELL_APER_EN 0x1501
+#define mmBUS_CNTL 0x1508
+#define mmCONFIG_CNTL 0x1509
+#define mmCONFIG_MEMSIZE 0x150a
+#define mmCONFIG_RESERVED 0x1502
+#define mmBIF_IOV_FUNC_IDENTIFIER 0x1503
+#define mmCONFIG_F0_BASE 0x150b
+#define mmCONFIG_APER_SIZE 0x150c
+#define mmCONFIG_REG_APER_SIZE 0x150d
+#define mmBIF_SCRATCH0 0x150e
+#define mmBIF_SCRATCH1 0x150f
+#define mmBIF_RLC_INTR_CNTL 0x1510
+#define mmBIF_BME_STATUS 0x1511
+#define mmBIF_ATOMIC_ERR_LOG 0x1512
+#define mmBX_RESET_EN 0x1514
+#define mmMM_CFGREGS_CNTL 0x1513
+#define mmHW_DEBUG 0x1515
+#define mmMASTER_CREDIT_CNTL 0x1516
+#define mmSLAVE_REQ_CREDIT_CNTL 0x1517
+#define mmBX_RESET_CNTL 0x1518
+#define mmINTERRUPT_CNTL 0x151a
+#define mmINTERRUPT_CNTL2 0x151b
+#define mmBIF_DEBUG_CNTL 0x151c
+#define mmBIF_DEBUG_MUX 0x151d
+#define mmBIF_DEBUG_OUT 0x151e
+#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528
+#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520
+#define mmCLKREQB_PAD_CNTL 0x1521
+#define mmCLKREQB_PERF_COUNTER 0x1522
+#define mmBIF_XDMA_LO 0x14c0
+#define mmBIF_XDMA_HI 0x14c1
+#define mmBIF_FEATURES_CONTROL_MISC 0x14c2
+#define mmBIF_DOORBELL_CNTL 0x14c3
+#define mmBIF_SLVARB_MODE 0x14c4
+#define mmBIF_CLK_CTRL 0x14c5
+#define mmBIF_FB_EN 0x1524
+#define mmBIF_BUSNUM_CNTL1 0x1525
+#define mmBIF_BUSNUM_LIST0 0x1526
+#define mmBIF_BUSNUM_LIST1 0x1527
+#define mmBIF_BUSNUM_CNTL2 0x152b
+#define mmBIF_BUSY_DELAY_CNTR 0x1529
+#define mmBIF_PERFMON_CNTL 0x152c
+#define mmBIF_PERFCOUNTER0_RESULT 0x152d
+#define mmBIF_PERFCOUNTER1_RESULT 0x152e
+#define mmSLAVE_HANG_PROTECTION_CNTL 0x1536
+#define mmGPU_HDP_FLUSH_REQ 0x1537
+#define mmGPU_HDP_FLUSH_DONE 0x1538
+#define mmSLAVE_HANG_ERROR 0x153b
+#define mmCAPTURE_HOST_BUSNUM 0x153c
+#define mmHOST_BUSNUM 0x153d
+#define mmPEER_REG_RANGE0 0x153e
+#define mmPEER_REG_RANGE1 0x153f
+#define mmPEER0_FB_OFFSET_HI 0x14f3
+#define mmPEER0_FB_OFFSET_LO 0x14f2
+#define mmPEER1_FB_OFFSET_HI 0x14f1
+#define mmPEER1_FB_OFFSET_LO 0x14f0
+#define mmPEER2_FB_OFFSET_HI 0x14ef
+#define mmPEER2_FB_OFFSET_LO 0x14ee
+#define mmPEER3_FB_OFFSET_HI 0x14ed
+#define mmPEER3_FB_OFFSET_LO 0x14ec
+#define mmDBG_SMB_BYPASS_SRBM_ACCESS 0x14eb
+#define mmBIF_MST_TRANS_PENDING 0x14ea
+#define mmBIF_SLV_TRANS_PENDING 0x14e9
+#define mmBIF_DEVFUNCNUM_LIST0 0x14e8
+#define mmBIF_DEVFUNCNUM_LIST1 0x14e7
+#define mmBACO_CNTL 0x14e5
+#define mmBF_ANA_ISO_CNTL 0x14c7
+#define mmMEM_TYPE_CNTL 0x14e4
+#define mmBIF_BACO_DEBUG 0x14df
+#define mmBIF_BACO_DEBUG_LATCH 0x14dc
+#define mmBACO_CNTL_MISC 0x14db
+#define mmSMU_BIF_VDDGFX_PWR_STATUS 0x14f8
+#define mmBIF_VDDGFX_GFX0_LOWER 0x1428
+#define mmBIF_VDDGFX_GFX0_UPPER 0x1429
+#define mmBIF_VDDGFX_GFX1_LOWER 0x142a
+#define mmBIF_VDDGFX_GFX1_UPPER 0x142b
+#define mmBIF_VDDGFX_GFX2_LOWER 0x142c
+#define mmBIF_VDDGFX_GFX2_UPPER 0x142d
+#define mmBIF_VDDGFX_GFX3_LOWER 0x142e
+#define mmBIF_VDDGFX_GFX3_UPPER 0x142f
+#define mmBIF_VDDGFX_GFX4_LOWER 0x1430
+#define mmBIF_VDDGFX_GFX4_UPPER 0x1431
+#define mmBIF_VDDGFX_GFX5_LOWER 0x1432
+#define mmBIF_VDDGFX_GFX5_UPPER 0x1433
+#define mmBIF_VDDGFX_RSV1_LOWER 0x1434
+#define mmBIF_VDDGFX_RSV1_UPPER 0x1435
+#define mmBIF_VDDGFX_RSV2_LOWER 0x1436
+#define mmBIF_VDDGFX_RSV2_UPPER 0x1437
+#define mmBIF_VDDGFX_RSV3_LOWER 0x1438
+#define mmBIF_VDDGFX_RSV3_UPPER 0x1439
+#define mmBIF_VDDGFX_RSV4_LOWER 0x143a
+#define mmBIF_VDDGFX_RSV4_UPPER 0x143b
+#define mmBIF_VDDGFX_FB_CMP 0x143c
+#define mmBIF_SMU_INDEX 0x143d
+#define mmBIF_SMU_DATA 0x143e
+#define mmBIF_DOORBELL_GBLAPER1_LOWER 0x14fc
+#define mmBIF_DOORBELL_GBLAPER1_UPPER 0x14fd
+#define mmBIF_DOORBELL_GBLAPER2_LOWER 0x14fe
+#define mmBIF_DOORBELL_GBLAPER2_UPPER 0x14ff
+#define mmIMPCTL_RESET 0x14f5
+#define mmGARLIC_FLUSH_CNTL 0x1401
+#define mmGARLIC_FLUSH_ADDR_START_0 0x1402
+#define mmGARLIC_FLUSH_ADDR_START_1 0x1404
+#define mmGARLIC_FLUSH_ADDR_START_2 0x1406
+#define mmGARLIC_FLUSH_ADDR_START_3 0x1408
+#define mmGARLIC_FLUSH_ADDR_START_4 0x140a
+#define mmGARLIC_FLUSH_ADDR_START_5 0x140c
+#define mmGARLIC_FLUSH_ADDR_START_6 0x140e
+#define mmGARLIC_FLUSH_ADDR_START_7 0x1410
+#define mmGARLIC_FLUSH_ADDR_END_0 0x1403
+#define mmGARLIC_FLUSH_ADDR_END_1 0x1405
+#define mmGARLIC_FLUSH_ADDR_END_2 0x1407
+#define mmGARLIC_FLUSH_ADDR_END_3 0x1409
+#define mmGARLIC_FLUSH_ADDR_END_4 0x140b
+#define mmGARLIC_FLUSH_ADDR_END_5 0x140d
+#define mmGARLIC_FLUSH_ADDR_END_6 0x140f
+#define mmGARLIC_FLUSH_ADDR_END_7 0x1411
+#define mmGARLIC_FLUSH_REQ 0x1412
+#define mmGPU_GARLIC_FLUSH_REQ 0x1413
+#define mmGPU_GARLIC_FLUSH_DONE 0x1414
+#define mmREMAP_HDP_MEM_FLUSH_CNTL 0x1426
+#define mmREMAP_HDP_REG_FLUSH_CNTL 0x1427
+#define mmBIOS_SCRATCH_0 0x5c9
+#define mmBIOS_SCRATCH_1 0x5ca
+#define mmBIOS_SCRATCH_2 0x5cb
+#define mmBIOS_SCRATCH_3 0x5cc
+#define mmBIOS_SCRATCH_4 0x5cd
+#define mmBIOS_SCRATCH_5 0x5ce
+#define mmBIOS_SCRATCH_6 0x5cf
+#define mmBIOS_SCRATCH_7 0x5d0
+#define mmBIOS_SCRATCH_8 0x5d1
+#define mmBIOS_SCRATCH_9 0x5d2
+#define mmBIOS_SCRATCH_10 0x5d3
+#define mmBIOS_SCRATCH_11 0x5d4
+#define mmBIOS_SCRATCH_12 0x5d5
+#define mmBIOS_SCRATCH_13 0x5d6
+#define mmBIOS_SCRATCH_14 0x5d7
+#define mmBIOS_SCRATCH_15 0x5d8
+#define mmBIF_RB_CNTL 0x1530
+#define mmBIF_RB_BASE 0x1531
+#define mmBIF_RB_RPTR 0x1532
+#define mmBIF_RB_WPTR 0x1533
+#define mmBIF_RB_WPTR_ADDR_HI 0x1534
+#define mmBIF_RB_WPTR_ADDR_LO 0x1535
+#define mmMAILBOX_INDEX 0x14c6
+#define mmMAILBOX_MSGBUF_TRN_DW0 0x14c8
+#define mmMAILBOX_MSGBUF_TRN_DW1 0x14c9
+#define mmMAILBOX_MSGBUF_TRN_DW2 0x14ca
+#define mmMAILBOX_MSGBUF_TRN_DW3 0x14cb
+#define mmMAILBOX_MSGBUF_RCV_DW0 0x14cc
+#define mmMAILBOX_MSGBUF_RCV_DW1 0x14cd
+#define mmMAILBOX_MSGBUF_RCV_DW2 0x14ce
+#define mmMAILBOX_MSGBUF_RCV_DW3 0x14cf
+#define mmMAILBOX_CONTROL 0x14d0
+#define mmMAILBOX_INT_CNTL 0x14d1
+#define mmBIF_VIRT_RESET_REQ 0x14d2
+#define mmVM_INIT_STATUS 0x14d3
+#define mmBIF_GPUIOV_RESET_NOTIFICATION 0x14d5
+#define mmBIF_GPUIOV_VM_INIT_STATUS 0x14d6
+#define mmBIF_GPUIOV_FB_TOTAL_FB_INFO 0x14d8
+#define mmBIF_GPUIOV_GPU_IDLE_LATENCY 0x141c
+#define mmBIF_GPUIOV_MMIO_MAP_RANGE0 0x141d
+#define mmBIF_GPUIOV_MMIO_MAP_RANGE1 0x141e
+#define mmBIF_GPUIOV_MMIO_MAP_RANGE2 0x141f
+#define mmBIF_GPUIOV_MMIO_MAP_RANGE3 0x1420
+#define mmBIF_GPUIOV_MMIO_MAP_RANGE4 0x1421
+#define mmBIF_GPUIOV_MMIO_MAP_RANGE5 0x1422
+#define mmBIF_GPU_IDLE_LATENCY 0x1415
+#define mmBIF_MMIO_MAP_RANGE0 0x1416
+#define mmBIF_MMIO_MAP_RANGE1 0x1417
+#define mmBIF_MMIO_MAP_RANGE2 0x1418
+#define mmBIF_MMIO_MAP_RANGE3 0x1419
+#define mmBIF_MMIO_MAP_RANGE4 0x141a
+#define mmBIF_MMIO_MAP_RANGE5 0x141b
+#define mmVENDOR_ID 0x0
+#define mmDEVICE_ID 0x0
+#define mmCOMMAND 0x1
+#define mmSTATUS 0x1
+#define mmREVISION_ID 0x2
+#define mmPROG_INTERFACE 0x2
+#define mmSUB_CLASS 0x2
+#define mmBASE_CLASS 0x2
+#define mmCACHE_LINE 0x3
+#define mmLATENCY 0x3
+#define mmHEADER 0x3
+#define mmBIST 0x3
+#define mmBASE_ADDR_1 0x4
+#define mmBASE_ADDR_2 0x5
+#define mmBASE_ADDR_3 0x6
+#define mmBASE_ADDR_4 0x7
+#define mmBASE_ADDR_5 0x8
+#define mmBASE_ADDR_6 0x9
+#define mmROM_BASE_ADDR 0xc
+#define mmCAP_PTR 0xd
+#define mmINTERRUPT_LINE 0xf
+#define mmINTERRUPT_PIN 0xf
+#define mmADAPTER_ID 0xb
+#define mmMIN_GRANT 0xf
+#define mmMAX_LATENCY 0xf
+#define mmVENDOR_CAP_LIST 0x12
+#define mmADAPTER_ID_W 0x13
+#define mmPMI_CAP_LIST 0x14
+#define mmPMI_CAP 0x14
+#define mmPMI_STATUS_CNTL 0x15
+#define mmPCIE_CAP_LIST 0x16
+#define mmPCIE_CAP 0x16
+#define mmDEVICE_CAP 0x17
+#define mmDEVICE_CNTL 0x18
+#define mmDEVICE_STATUS 0x18
+#define mmLINK_CAP 0x19
+#define mmLINK_CNTL 0x1a
+#define mmLINK_STATUS 0x1a
+#define mmDEVICE_CAP2 0x1f
+#define mmDEVICE_CNTL2 0x20
+#define mmDEVICE_STATUS2 0x20
+#define mmLINK_CAP2 0x21
+#define mmLINK_CNTL2 0x22
+#define mmLINK_STATUS2 0x22
+#define mmMSI_CAP_LIST 0x28
+#define mmMSI_MSG_CNTL 0x28
+#define mmMSI_MSG_ADDR_LO 0x29
+#define mmMSI_MSG_ADDR_HI 0x2a
+#define mmMSI_MSG_DATA_64 0x2b
+#define mmMSI_MSG_DATA 0x2a
+#define mmMSI_MASK 0x2b
+#define mmMSI_PENDING 0x2c
+#define mmMSI_MASK_64 0x2c
+#define mmMSI_PENDING_64 0x2d
+#define mmMSIX_CAP_LIST 0x30
+#define mmMSIX_MSG_CNTL 0x30
+#define mmMSIX_TABLE 0x31
+#define mmMSIX_PBA 0x32
+#define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x40
+#define mmPCIE_VENDOR_SPECIFIC_HDR 0x41
+#define mmPCIE_VENDOR_SPECIFIC1 0x42
+#define mmPCIE_VENDOR_SPECIFIC2 0x43
+#define mmPCIE_VC_ENH_CAP_LIST 0x44
+#define mmPCIE_PORT_VC_CAP_REG1 0x45
+#define mmPCIE_PORT_VC_CAP_REG2 0x46
+#define mmPCIE_PORT_VC_CNTL 0x47
+#define mmPCIE_PORT_VC_STATUS 0x47
+#define mmPCIE_VC0_RESOURCE_CAP 0x48
+#define mmPCIE_VC0_RESOURCE_CNTL 0x49
+#define mmPCIE_VC0_RESOURCE_STATUS 0x4a
+#define mmPCIE_VC1_RESOURCE_CAP 0x4b
+#define mmPCIE_VC1_RESOURCE_CNTL 0x4c
+#define mmPCIE_VC1_RESOURCE_STATUS 0x4d
+#define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x50
+#define mmPCIE_DEV_SERIAL_NUM_DW1 0x51
+#define mmPCIE_DEV_SERIAL_NUM_DW2 0x52
+#define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x54
+#define mmPCIE_UNCORR_ERR_STATUS 0x55
+#define mmPCIE_UNCORR_ERR_MASK 0x56
+#define mmPCIE_UNCORR_ERR_SEVERITY 0x57
+#define mmPCIE_CORR_ERR_STATUS 0x58
+#define mmPCIE_CORR_ERR_MASK 0x59
+#define mmPCIE_ADV_ERR_CAP_CNTL 0x5a
+#define mmPCIE_HDR_LOG0 0x5b
+#define mmPCIE_HDR_LOG1 0x5c
+#define mmPCIE_HDR_LOG2 0x5d
+#define mmPCIE_HDR_LOG3 0x5e
+#define mmPCIE_TLP_PREFIX_LOG0 0x62
+#define mmPCIE_TLP_PREFIX_LOG1 0x63
+#define mmPCIE_TLP_PREFIX_LOG2 0x64
+#define mmPCIE_TLP_PREFIX_LOG3 0x65
+#define mmPCIE_BAR_ENH_CAP_LIST 0x80
+#define mmPCIE_BAR1_CAP 0x81
+#define mmPCIE_BAR1_CNTL 0x82
+#define mmPCIE_BAR2_CAP 0x83
+#define mmPCIE_BAR2_CNTL 0x84
+#define mmPCIE_BAR3_CAP 0x85
+#define mmPCIE_BAR3_CNTL 0x86
+#define mmPCIE_BAR4_CAP 0x87
+#define mmPCIE_BAR4_CNTL 0x88
+#define mmPCIE_BAR5_CAP 0x89
+#define mmPCIE_BAR5_CNTL 0x8a
+#define mmPCIE_BAR6_CAP 0x8b
+#define mmPCIE_BAR6_CNTL 0x8c
+#define mmPCIE_PWR_BUDGET_ENH_CAP_LIST 0x90
+#define mmPCIE_PWR_BUDGET_DATA_SELECT 0x91
+#define mmPCIE_PWR_BUDGET_DATA 0x92
+#define mmPCIE_PWR_BUDGET_CAP 0x93
+#define mmPCIE_DPA_ENH_CAP_LIST 0x94
+#define mmPCIE_DPA_CAP 0x95
+#define mmPCIE_DPA_LATENCY_INDICATOR 0x96
+#define mmPCIE_DPA_STATUS 0x97
+#define mmPCIE_DPA_CNTL 0x97
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x98
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x98
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x98
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x98
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x99
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x99
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x99
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x99
+#define mmPCIE_SECONDARY_ENH_CAP_LIST 0x9c
+#define mmPCIE_LINK_CNTL3 0x9d
+#define mmPCIE_LANE_ERROR_STATUS 0x9e
+#define mmPCIE_LANE_0_EQUALIZATION_CNTL 0x9f
+#define mmPCIE_LANE_1_EQUALIZATION_CNTL 0x9f
+#define mmPCIE_LANE_2_EQUALIZATION_CNTL 0xa0
+#define mmPCIE_LANE_3_EQUALIZATION_CNTL 0xa0
+#define mmPCIE_LANE_4_EQUALIZATION_CNTL 0xa1
+#define mmPCIE_LANE_5_EQUALIZATION_CNTL 0xa1
+#define mmPCIE_LANE_6_EQUALIZATION_CNTL 0xa2
+#define mmPCIE_LANE_7_EQUALIZATION_CNTL 0xa2
+#define mmPCIE_LANE_8_EQUALIZATION_CNTL 0xa3
+#define mmPCIE_LANE_9_EQUALIZATION_CNTL 0xa3
+#define mmPCIE_LANE_10_EQUALIZATION_CNTL 0xa4
+#define mmPCIE_LANE_11_EQUALIZATION_CNTL 0xa4
+#define mmPCIE_LANE_12_EQUALIZATION_CNTL 0xa5
+#define mmPCIE_LANE_13_EQUALIZATION_CNTL 0xa5
+#define mmPCIE_LANE_14_EQUALIZATION_CNTL 0xa6
+#define mmPCIE_LANE_15_EQUALIZATION_CNTL 0xa6
+#define mmPCIE_ACS_ENH_CAP_LIST 0xa8
+#define mmPCIE_ACS_CAP 0xa9
+#define mmPCIE_ACS_CNTL 0xa9
+#define mmPCIE_ATS_ENH_CAP_LIST 0xac
+#define mmPCIE_ATS_CAP 0xad
+#define mmPCIE_ATS_CNTL 0xad
+#define mmPCIE_PAGE_REQ_ENH_CAP_LIST 0xb0
+#define mmPCIE_PAGE_REQ_CNTL 0xb1
+#define mmPCIE_PAGE_REQ_STATUS 0xb1
+#define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xb2
+#define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC 0xb3
+#define mmPCIE_PASID_ENH_CAP_LIST 0xb4
+#define mmPCIE_PASID_CAP 0xb5
+#define mmPCIE_PASID_CNTL 0xb5
+#define mmPCIE_TPH_REQR_ENH_CAP_LIST 0xb8
+#define mmPCIE_TPH_REQR_CAP 0xb9
+#define mmPCIE_TPH_REQR_CNTL 0xba
+#define mmPCIE_MC_ENH_CAP_LIST 0xbc
+#define mmPCIE_MC_CAP 0xbd
+#define mmPCIE_MC_CNTL 0xbd
+#define mmPCIE_MC_ADDR0 0xbe
+#define mmPCIE_MC_ADDR1 0xbf
+#define mmPCIE_MC_RCV0 0xc0
+#define mmPCIE_MC_RCV1 0xc1
+#define mmPCIE_MC_BLOCK_ALL0 0xc2
+#define mmPCIE_MC_BLOCK_ALL1 0xc3
+#define mmPCIE_MC_BLOCK_UNTRANSLATED_0 0xc4
+#define mmPCIE_MC_BLOCK_UNTRANSLATED_1 0xc5
+#define mmPCIE_LTR_ENH_CAP_LIST 0xc8
+#define mmPCIE_LTR_CAP 0xc9
+#define mmPCIE_ARI_ENH_CAP_LIST 0xca
+#define mmPCIE_ARI_CAP 0xcb
+#define mmPCIE_ARI_CNTL 0xcb
+#define mmPCIE_SRIOV_ENH_CAP_LIST 0xcc
+#define mmPCIE_SRIOV_CAP 0xcd
+#define mmPCIE_SRIOV_CONTROL 0xce
+#define mmPCIE_SRIOV_STATUS 0xce
+#define mmPCIE_SRIOV_INITIAL_VFS 0xcf
+#define mmPCIE_SRIOV_TOTAL_VFS 0xcf
+#define mmPCIE_SRIOV_NUM_VFS 0xd0
+#define mmPCIE_SRIOV_FUNC_DEP_LINK 0xd0
+#define mmPCIE_SRIOV_FIRST_VF_OFFSET 0xd1
+#define mmPCIE_SRIOV_VF_STRIDE 0xd1
+#define mmPCIE_SRIOV_VF_DEVICE_ID 0xd2
+#define mmPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0xd3
+#define mmPCIE_SRIOV_SYSTEM_PAGE_SIZE 0xd4
+#define mmPCIE_SRIOV_VF_BASE_ADDR_0 0xd5
+#define mmPCIE_SRIOV_VF_BASE_ADDR_1 0xd6
+#define mmPCIE_SRIOV_VF_BASE_ADDR_2 0xd7
+#define mmPCIE_SRIOV_VF_BASE_ADDR_3 0xd8
+#define mmPCIE_SRIOV_VF_BASE_ADDR_4 0xd9
+#define mmPCIE_SRIOV_VF_BASE_ADDR_5 0xda
+#define mmPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0xdb
+#define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x100
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x101
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x102
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC 0x103
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS 0x104
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x105
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION 0x106
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS 0x107
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x108
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x109
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS 0x10a
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x10b
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x10c
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x10d
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x10e
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x10f
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x110
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x111
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x112
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x113
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x114
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x115
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x116
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x117
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x118
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x119
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x11a
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x11b
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT 0x11c
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0 0x11d
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1 0x11e
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2 0x11f
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3 0x120
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4 0x121
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5 0x122
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0 0x124
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1 0x125
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2 0x126
+#define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3 0x127
+#define mmPCIE_INDEX 0xe
+#define mmPCIE_DATA 0xf
+#define mmPCIE_INDEX_2 0xc
+#define mmPCIE_DATA_2 0xd
+#define ixPCIE_HOLD_TRAINING_A 0x1500820
+#define ixLNCNT_CONTROL 0x1508030
+#define ixCFG_LNC_WINDOW 0x1508031
+#define ixLNCNT_QUAN_THRD 0x1508032
+#define ixLNCNT_WEIGHT 0x1508033
+#define ixLNC_TOTAL_WACC 0x1508034
+#define ixLNC_BW_WACC 0x1508035
+#define ixLNC_CMN_WACC 0x1508036
+#define mmPCIE_EFUSE 0xfc0
+#define mmPCIE_EFUSE2 0xfc1
+#define mmPCIE_EFUSE3 0xfc2
+#define mmPCIE_EFUSE4 0xfc3
+#define mmPCIE_EFUSE5 0xfc4
+#define mmPCIE_EFUSE6 0xfc5
+#define mmPCIE_EFUSE7 0xfc6
+#define ixPCIE_WRAP_SCRATCH1 0x1308001
+#define ixPCIE_WRAP_SCRATCH2 0x1308002
+#define ixPCIE_WRAP_REG_TARG_MISC 0x1308005
+#define ixPCIE_WRAP_DTM_MISC 0x1308006
+#define ixPCIE_WRAP_TURNAROUND_DAISYCHAIN 0x1308007
+#define ixPCIE_WRAP_MISC 0x1308008
+#define ixPCIE_WRAP_PIF_MISC 0x1308009
+#define ixPCIE_RXDET_OVERRIDE 0x130800a
+#define ixREG_ADAPT_pciecore0_CONTROL 0x1308090
+#define ixREG_ADAPT_pwregt_CONTROL 0x1308096
+#define ixREG_ADAPT_pwregr_CONTROL 0x1308097
+#define ixREG_ADAPT_pif0_CONTROL 0x1308098
+#define ixPCIE_RESERVED 0x1400000
+#define ixPCIE_SCRATCH 0x1400001
+#define ixPCIE_HW_DEBUG 0x1400002
+#define ixPCIE_RX_NUM_NAK 0x140000e
+#define ixPCIE_RX_NUM_NAK_GENERATED 0x140000f
+#define ixPCIE_CNTL 0x1400010
+#define ixPCIE_CONFIG_CNTL 0x1400011
+#define ixPCIE_DEBUG_CNTL 0x1400012
+#define ixPCIE_INT_CNTL 0x140001a
+#define ixPCIE_INT_STATUS 0x140001b
+#define ixPCIE_CNTL2 0x140001c
+#define ixPCIE_RX_CNTL2 0x140001d
+#define ixPCIE_TX_F0_ATTR_CNTL 0x140001e
+#define ixPCIE_TX_F1_F2_ATTR_CNTL 0x140001f
+#define ixPCIE_CI_CNTL 0x1400020
+#define ixPCIE_BUS_CNTL 0x1400021
+#define ixPCIE_LC_STATE6 0x1400022
+#define ixPCIE_LC_STATE7 0x1400023
+#define ixPCIE_LC_STATE8 0x1400024
+#define ixPCIE_LC_STATE9 0x1400025
+#define ixPCIE_LC_STATE10 0x1400026
+#define ixPCIE_LC_STATE11 0x1400027
+#define ixPCIE_LC_STATUS1 0x1400028
+#define ixPCIE_LC_STATUS2 0x1400029
+#define ixPCIE_WPR_CNTL 0x1400030
+#define ixPCIE_RX_LAST_TLP0 0x1400031
+#define ixPCIE_RX_LAST_TLP1 0x1400032
+#define ixPCIE_RX_LAST_TLP2 0x1400033
+#define ixPCIE_RX_LAST_TLP3 0x1400034
+#define ixPCIE_TX_LAST_TLP0 0x1400035
+#define ixPCIE_TX_LAST_TLP1 0x1400036
+#define ixPCIE_TX_LAST_TLP2 0x1400037
+#define ixPCIE_TX_LAST_TLP3 0x1400038
+#define ixPCIE_I2C_REG_ADDR_EXPAND 0x140003a
+#define ixPCIE_I2C_REG_DATA 0x140003b
+#define ixPCIE_CFG_CNTL 0x140003c
+#define ixPCIE_LC_PM_CNTL 0x140003d
+#define ixPCIE_P_CNTL 0x1400040
+#define ixPCIE_P_BUF_STATUS 0x1400041
+#define ixPCIE_P_DECODER_STATUS 0x1400042
+#define ixPCIE_P_MISC_STATUS 0x1400043
+#define ixPCIE_P_RCV_L0S_FTS_DET 0x1400050
+#define ixPCIE_OBFF_CNTL 0x1400061
+#define ixPCIE_TX_LTR_CNTL 0x1400060
+#define ixPCIE_IDLE_STATUS 0x1400062
+#define ixPCIE_PERF_COUNT_CNTL 0x1400080
+#define ixPCIE_PERF_CNTL_TXCLK 0x1400081
+#define ixPCIE_PERF_COUNT0_TXCLK 0x1400082
+#define ixPCIE_PERF_COUNT1_TXCLK 0x1400083
+#define ixPCIE_PERF_CNTL_MST_R_CLK 0x1400084
+#define ixPCIE_PERF_COUNT0_MST_R_CLK 0x1400085
+#define ixPCIE_PERF_COUNT1_MST_R_CLK 0x1400086
+#define ixPCIE_PERF_CNTL_MST_C_CLK 0x1400087
+#define ixPCIE_PERF_COUNT0_MST_C_CLK 0x1400088
+#define ixPCIE_PERF_COUNT1_MST_C_CLK 0x1400089
+#define ixPCIE_PERF_CNTL_SLV_R_CLK 0x140008a
+#define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x140008b
+#define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x140008c
+#define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d
+#define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e
+#define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f
+#define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090
+#define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091
+#define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092
+#define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093
+#define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094
+#define ixPCIE_PERF_CNTL_TXCLK2 0x1400095
+#define ixPCIE_PERF_COUNT0_TXCLK2 0x1400096
+#define ixPCIE_PERF_COUNT1_TXCLK2 0x1400097
+#define ixPCIE_STRAP_F0 0x14000b0
+#define ixPCIE_STRAP_F1 0x14000b1
+#define ixPCIE_STRAP_F2 0x14000b2
+#define ixPCIE_STRAP_F3 0x14000b3
+#define ixPCIE_STRAP_F4 0x14000b4
+#define ixPCIE_STRAP_F5 0x14000b5
+#define ixPCIE_STRAP_F6 0x14000b6
+#define ixPCIE_STRAP_MSIX 0x14000b7
+#define ixPCIE_STRAP_MISC 0x14000c0
+#define ixPCIE_STRAP_MISC2 0x14000c1
+#define ixPCIE_STRAP_PI 0x14000c2
+#define ixPCIE_STRAP_I2C_BD 0x14000c4
+#define ixPCIE_PRBS_CLR 0x14000c8
+#define ixPCIE_PRBS_STATUS1 0x14000c9
+#define ixPCIE_PRBS_STATUS2 0x14000ca
+#define ixPCIE_PRBS_FREERUN 0x14000cb
+#define ixPCIE_PRBS_MISC 0x14000cc
+#define ixPCIE_PRBS_USER_PATTERN 0x14000cd
+#define ixPCIE_PRBS_LO_BITCNT 0x14000ce
+#define ixPCIE_PRBS_HI_BITCNT 0x14000cf
+#define ixPCIE_PRBS_ERRCNT_0 0x14000d0
+#define ixPCIE_PRBS_ERRCNT_1 0x14000d1
+#define ixPCIE_PRBS_ERRCNT_2 0x14000d2
+#define ixPCIE_PRBS_ERRCNT_3 0x14000d3
+#define ixPCIE_PRBS_ERRCNT_4 0x14000d4
+#define ixPCIE_PRBS_ERRCNT_5 0x14000d5
+#define ixPCIE_PRBS_ERRCNT_6 0x14000d6
+#define ixPCIE_PRBS_ERRCNT_7 0x14000d7
+#define ixPCIE_PRBS_ERRCNT_8 0x14000d8
+#define ixPCIE_PRBS_ERRCNT_9 0x14000d9
+#define ixPCIE_PRBS_ERRCNT_10 0x14000da
+#define ixPCIE_PRBS_ERRCNT_11 0x14000db
+#define ixPCIE_PRBS_ERRCNT_12 0x14000dc
+#define ixPCIE_PRBS_ERRCNT_13 0x14000dd
+#define ixPCIE_PRBS_ERRCNT_14 0x14000de
+#define ixPCIE_PRBS_ERRCNT_15 0x14000df
+#define ixPCIE_F0_DPA_CAP 0x14000e0
+#define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x14000e4
+#define ixPCIE_F0_DPA_CNTL 0x14000e5
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x14000e7
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x14000e8
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x14000e9
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x14000ea
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x14000eb
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x14000ec
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x14000ed
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x14000ee
+#define mmSWRST_COMMAND_STATUS 0x14a0
+#define mmSWRST_GENERAL_CONTROL 0x14a1
+#define mmSWRST_COMMAND_0 0x14a2
+#define mmSWRST_COMMAND_1 0x14a3
+#define mmSWRST_CONTROL_0 0x14a4
+#define mmSWRST_CONTROL_1 0x14a5
+#define mmSWRST_CONTROL_2 0x14a6
+#define mmSWRST_CONTROL_3 0x14a7
+#define mmSWRST_CONTROL_4 0x14a8
+#define mmSWRST_CONTROL_5 0x14a9
+#define mmSWRST_CONTROL_6 0x14aa
+#define mmSWRST_EP_COMMAND_0 0x14ab
+#define mmSWRST_EP_CONTROL_0 0x14ac
+#define mmCPM_CONTROL 0x14b8
+#define mmGSKT_CONTROL 0x14bf
+#define ixLM_CONTROL 0x1400120
+#define ixLM_PCIETXMUX0 0x1400121
+#define ixLM_PCIETXMUX1 0x1400122
+#define ixLM_PCIETXMUX2 0x1400123
+#define ixLM_PCIETXMUX3 0x1400124
+#define ixLM_PCIERXMUX0 0x1400125
+#define ixLM_PCIERXMUX1 0x1400126
+#define ixLM_PCIERXMUX2 0x1400127
+#define ixLM_PCIERXMUX3 0x1400128
+#define ixLM_LANEENABLE 0x1400129
+#define ixLM_PRBSCONTROL 0x140012a
+#define ixLM_POWERCONTROL 0x140012b
+#define ixLM_POWERCONTROL1 0x140012c
+#define ixLM_POWERCONTROL2 0x140012d
+#define ixLM_POWERCONTROL3 0x140012e
+#define ixLM_POWERCONTROL4 0x140012f
+#define ixPB0_GLB_CTRL_REG0 0x1200004
+#define ixPB0_GLB_CTRL_REG1 0x1200008
+#define ixPB0_GLB_CTRL_REG2 0x120000c
+#define ixPB0_GLB_CTRL_REG3 0x1200010
+#define ixPB0_GLB_CTRL_REG4 0x1200014
+#define ixPB0_GLB_CTRL_REG5 0x1200018
+#define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x120001c
+#define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x1200020
+#define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x1200024
+#define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x1200028
+#define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x120002c
+#define ixPB0_GLB_OVRD_REG0 0x1200030
+#define ixPB0_GLB_OVRD_REG1 0x1200034
+#define ixPB0_GLB_OVRD_REG2 0x1200038
+#define ixPB0_HW_DEBUG 0x1202004
+#define ixPB0_STRAP_GLB_REG0 0x1202020
+#define ixPB0_STRAP_TX_REG0 0x1202024
+#define ixPB0_STRAP_RX_REG0 0x1202028
+#define ixPB0_STRAP_RX_REG1 0x120202c
+#define ixPB0_STRAP_PLL_REG0 0x1202030
+#define ixPB0_STRAP_PIN_REG0 0x1202034
+#define ixPB0_STRAP_GLB_REG1 0x1202038
+#define ixPB0_STRAP_GLB_REG2 0x120203c
+#define ixPB0_DFT_JIT_INJ_REG0 0x1203000
+#define ixPB0_DFT_JIT_INJ_REG1 0x1203004
+#define ixPB0_DFT_JIT_INJ_REG2 0x1203008
+#define ixPB0_DFT_DEBUG_CTRL_REG0 0x120300c
+#define ixPB0_DFT_JIT_INJ_STAT_REG0 0x1203010
+#define ixPB0_PLL_RO_GLB_CTRL_REG0 0x1204000
+#define ixPB0_PLL_RO_GLB_OVRD_REG0 0x1204010
+#define ixPB0_PLL_RO0_CTRL_REG0 0x1204440
+#define ixPB0_PLL_RO0_OVRD_REG0 0x1204450
+#define ixPB0_PLL_RO0_OVRD_REG1 0x1204454
+#define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x1204460
+#define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x1204464
+#define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x1204468
+#define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x120446c
+#define ixPB0_PLL_LC0_CTRL_REG0 0x1204480
+#define ixPB0_PLL_LC0_OVRD_REG0 0x1204490
+#define ixPB0_PLL_LC0_OVRD_REG1 0x1204494
+#define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x1204500
+#define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x1204504
+#define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x1204508
+#define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x120450c
+#define ixPB0_RX_GLB_CTRL_REG0 0x1206000
+#define ixPB0_RX_GLB_CTRL_REG1 0x1206004
+#define ixPB0_RX_GLB_CTRL_REG2 0x1206008
+#define ixPB0_RX_GLB_CTRL_REG3 0x120600c
+#define ixPB0_RX_GLB_CTRL_REG4 0x1206010
+#define ixPB0_RX_GLB_CTRL_REG5 0x1206014
+#define ixPB0_RX_GLB_CTRL_REG6 0x1206018
+#define ixPB0_RX_GLB_CTRL_REG7 0x120601c
+#define ixPB0_RX_GLB_CTRL_REG8 0x1206020
+#define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 0x1206028
+#define ixPB0_RX_GLB_OVRD_REG0 0x1206030
+#define ixPB0_RX_GLB_OVRD_REG1 0x1206034
+#define ixPB0_RX_LANE0_CTRL_REG0 0x1206440
+#define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 0x1206448
+#define ixPB0_RX_LANE1_CTRL_REG0 0x1206480
+#define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 0x1206488
+#define ixPB0_RX_LANE2_CTRL_REG0 0x1206500
+#define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 0x1206508
+#define ixPB0_RX_LANE3_CTRL_REG0 0x1206600
+#define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 0x1206608
+#define ixPB0_RX_LANE4_CTRL_REG0 0x1206800
+#define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 0x1206848
+#define ixPB0_RX_LANE5_CTRL_REG0 0x1206880
+#define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 0x1206888
+#define ixPB0_RX_LANE6_CTRL_REG0 0x1206900
+#define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 0x1206908
+#define ixPB0_RX_LANE7_CTRL_REG0 0x1206a00
+#define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 0x1206a08
+#define ixPB0_RX_LANE8_CTRL_REG0 0x1207440
+#define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 0x1207448
+#define ixPB0_RX_LANE9_CTRL_REG0 0x1207480
+#define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 0x1207488
+#define ixPB0_RX_LANE10_CTRL_REG0 0x1207500
+#define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 0x1207508
+#define ixPB0_RX_LANE11_CTRL_REG0 0x1207600
+#define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 0x1207608
+#define ixPB0_RX_LANE12_CTRL_REG0 0x1207840
+#define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 0x1207848
+#define ixPB0_RX_LANE13_CTRL_REG0 0x1207880
+#define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 0x1207888
+#define ixPB0_RX_LANE14_CTRL_REG0 0x1207900
+#define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 0x1207908
+#define ixPB0_RX_LANE15_CTRL_REG0 0x1207a00
+#define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 0x1207a08
+#define ixPB0_TX_GLB_CTRL_REG0 0x1208000
+#define ixPB0_TX_GLB_LANE_SKEW_CTRL 0x1208004
+#define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 0x1208010
+#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x1208014
+#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x1208018
+#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x120801c
+#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x1208020
+#define ixPB0_TX_GLB_OVRD_REG0 0x1208030
+#define ixPB0_TX_GLB_OVRD_REG1 0x1208034
+#define ixPB0_TX_GLB_OVRD_REG2 0x1208038
+#define ixPB0_TX_GLB_OVRD_REG3 0x120803c
+#define ixPB0_TX_GLB_OVRD_REG4 0x1208040
+#define ixPB0_TX_LANE0_CTRL_REG0 0x1208440
+#define ixPB0_TX_LANE0_OVRD_REG0 0x1208444
+#define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 0x1208448
+#define ixPB0_TX_LANE1_CTRL_REG0 0x1208480
+#define ixPB0_TX_LANE1_OVRD_REG0 0x1208484
+#define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 0x1208488
+#define ixPB0_TX_LANE2_CTRL_REG0 0x1208500
+#define ixPB0_TX_LANE2_OVRD_REG0 0x1208504
+#define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 0x1208508
+#define ixPB0_TX_LANE3_CTRL_REG0 0x1208600
+#define ixPB0_TX_LANE3_OVRD_REG0 0x1208604
+#define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 0x1208608
+#define ixPB0_TX_LANE4_CTRL_REG0 0x1208840
+#define ixPB0_TX_LANE4_OVRD_REG0 0x1208844
+#define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 0x1208848
+#define ixPB0_TX_LANE5_CTRL_REG0 0x1208880
+#define ixPB0_TX_LANE5_OVRD_REG0 0x1208884
+#define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 0x1208888
+#define ixPB0_TX_LANE6_CTRL_REG0 0x1208900
+#define ixPB0_TX_LANE6_OVRD_REG0 0x1208904
+#define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 0x1208908
+#define ixPB0_TX_LANE7_CTRL_REG0 0x1208a00
+#define ixPB0_TX_LANE7_OVRD_REG0 0x1208a04
+#define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 0x1208a08
+#define ixPB0_TX_LANE8_CTRL_REG0 0x1209440
+#define ixPB0_TX_LANE8_OVRD_REG0 0x1209444
+#define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 0x1209448
+#define ixPB0_TX_LANE9_CTRL_REG0 0x1209480
+#define ixPB0_TX_LANE9_OVRD_REG0 0x1209484
+#define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 0x1209488
+#define ixPB0_TX_LANE10_CTRL_REG0 0x1209500
+#define ixPB0_TX_LANE10_OVRD_REG0 0x1209504
+#define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 0x1209508
+#define ixPB0_TX_LANE11_CTRL_REG0 0x1209600
+#define ixPB0_TX_LANE11_OVRD_REG0 0x1209604
+#define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 0x1209608
+#define ixPB0_TX_LANE12_CTRL_REG0 0x1209840
+#define ixPB0_TX_LANE12_OVRD_REG0 0x1209844
+#define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 0x1209848
+#define ixPB0_TX_LANE13_CTRL_REG0 0x1209880
+#define ixPB0_TX_LANE13_OVRD_REG0 0x1209884
+#define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 0x1209888
+#define ixPB0_TX_LANE14_CTRL_REG0 0x1209900
+#define ixPB0_TX_LANE14_OVRD_REG0 0x1209904
+#define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 0x1209908
+#define ixPB0_TX_LANE15_CTRL_REG0 0x1209a00
+#define ixPB0_TX_LANE15_OVRD_REG0 0x1209a04
+#define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 0x1209a08
+#define ixPB1_GLB_CTRL_REG0 0x2200004
+#define ixPB1_GLB_CTRL_REG1 0x2200008
+#define ixPB1_GLB_CTRL_REG2 0x220000c
+#define ixPB1_GLB_CTRL_REG3 0x2200010
+#define ixPB1_GLB_CTRL_REG4 0x2200014
+#define ixPB1_GLB_CTRL_REG5 0x2200018
+#define ixPB1_GLB_SCI_STAT_OVRD_REG0 0x220001c
+#define ixPB1_GLB_SCI_STAT_OVRD_REG1 0x2200020
+#define ixPB1_GLB_SCI_STAT_OVRD_REG2 0x2200024
+#define ixPB1_GLB_SCI_STAT_OVRD_REG3 0x2200028
+#define ixPB1_GLB_SCI_STAT_OVRD_REG4 0x220002c
+#define ixPB1_GLB_OVRD_REG0 0x2200030
+#define ixPB1_GLB_OVRD_REG1 0x2200034
+#define ixPB1_GLB_OVRD_REG2 0x2200038
+#define ixPB1_HW_DEBUG 0x2202004
+#define ixPB1_STRAP_GLB_REG0 0x2202020
+#define ixPB1_STRAP_TX_REG0 0x2202024
+#define ixPB1_STRAP_RX_REG0 0x2202028
+#define ixPB1_STRAP_RX_REG1 0x220202c
+#define ixPB1_STRAP_PLL_REG0 0x2202030
+#define ixPB1_STRAP_PIN_REG0 0x2202034
+#define ixPB1_STRAP_GLB_REG1 0x2202038
+#define ixPB1_STRAP_GLB_REG2 0x220203c
+#define ixPB1_DFT_JIT_INJ_REG0 0x2203000
+#define ixPB1_DFT_JIT_INJ_REG1 0x2203004
+#define ixPB1_DFT_JIT_INJ_REG2 0x2203008
+#define ixPB1_DFT_DEBUG_CTRL_REG0 0x220300c
+#define ixPB1_DFT_JIT_INJ_STAT_REG0 0x2203010
+#define ixPB1_PLL_RO_GLB_CTRL_REG0 0x2204000
+#define ixPB1_PLL_RO_GLB_OVRD_REG0 0x2204010
+#define ixPB1_PLL_RO0_CTRL_REG0 0x2204440
+#define ixPB1_PLL_RO0_OVRD_REG0 0x2204450
+#define ixPB1_PLL_RO0_OVRD_REG1 0x2204454
+#define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 0x2204460
+#define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 0x2204464
+#define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 0x2204468
+#define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 0x220446c
+#define ixPB1_PLL_LC0_CTRL_REG0 0x2204480
+#define ixPB1_PLL_LC0_OVRD_REG0 0x2204490
+#define ixPB1_PLL_LC0_OVRD_REG1 0x2204494
+#define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 0x2204500
+#define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 0x2204504
+#define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 0x2204508
+#define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 0x220450c
+#define ixPB1_RX_GLB_CTRL_REG0 0x2206000
+#define ixPB1_RX_GLB_CTRL_REG1 0x2206004
+#define ixPB1_RX_GLB_CTRL_REG2 0x2206008
+#define ixPB1_RX_GLB_CTRL_REG3 0x220600c
+#define ixPB1_RX_GLB_CTRL_REG4 0x2206010
+#define ixPB1_RX_GLB_CTRL_REG5 0x2206014
+#define ixPB1_RX_GLB_CTRL_REG6 0x2206018
+#define ixPB1_RX_GLB_CTRL_REG7 0x220601c
+#define ixPB1_RX_GLB_CTRL_REG8 0x2206020
+#define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 0x2206028
+#define ixPB1_RX_GLB_OVRD_REG0 0x2206030
+#define ixPB1_RX_GLB_OVRD_REG1 0x2206034
+#define ixPB1_RX_LANE0_CTRL_REG0 0x2206440
+#define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 0x2206448
+#define ixPB1_RX_LANE1_CTRL_REG0 0x2206480
+#define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 0x2206488
+#define ixPB1_RX_LANE2_CTRL_REG0 0x2206500
+#define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 0x2206508
+#define ixPB1_RX_LANE3_CTRL_REG0 0x2206600
+#define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 0x2206608
+#define ixPB1_RX_LANE4_CTRL_REG0 0x2206800
+#define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 0x2206848
+#define ixPB1_RX_LANE5_CTRL_REG0 0x2206880
+#define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 0x2206888
+#define ixPB1_RX_LANE6_CTRL_REG0 0x2206900
+#define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 0x2206908
+#define ixPB1_RX_LANE7_CTRL_REG0 0x2206a00
+#define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 0x2206a08
+#define ixPB1_RX_LANE8_CTRL_REG0 0x2207440
+#define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 0x2207448
+#define ixPB1_RX_LANE9_CTRL_REG0 0x2207480
+#define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 0x2207488
+#define ixPB1_RX_LANE10_CTRL_REG0 0x2207500
+#define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 0x2207508
+#define ixPB1_RX_LANE11_CTRL_REG0 0x2207600
+#define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 0x2207608
+#define ixPB1_RX_LANE12_CTRL_REG0 0x2207840
+#define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 0x2207848
+#define ixPB1_RX_LANE13_CTRL_REG0 0x2207880
+#define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 0x2207888
+#define ixPB1_RX_LANE14_CTRL_REG0 0x2207900
+#define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 0x2207908
+#define ixPB1_RX_LANE15_CTRL_REG0 0x2207a00
+#define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 0x2207a08
+#define ixPB1_TX_GLB_CTRL_REG0 0x2208000
+#define ixPB1_TX_GLB_LANE_SKEW_CTRL 0x2208004
+#define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 0x2208010
+#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x2208014
+#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x2208018
+#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x220801c
+#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x2208020
+#define ixPB1_TX_GLB_OVRD_REG0 0x2208030
+#define ixPB1_TX_GLB_OVRD_REG1 0x2208034
+#define ixPB1_TX_GLB_OVRD_REG2 0x2208038
+#define ixPB1_TX_GLB_OVRD_REG3 0x220803c
+#define ixPB1_TX_GLB_OVRD_REG4 0x2208040
+#define ixPB1_TX_LANE0_CTRL_REG0 0x2208440
+#define ixPB1_TX_LANE0_OVRD_REG0 0x2208444
+#define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 0x2208448
+#define ixPB1_TX_LANE1_CTRL_REG0 0x2208480
+#define ixPB1_TX_LANE1_OVRD_REG0 0x2208484
+#define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 0x2208488
+#define ixPB1_TX_LANE2_CTRL_REG0 0x2208500
+#define ixPB1_TX_LANE2_OVRD_REG0 0x2208504
+#define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 0x2208508
+#define ixPB1_TX_LANE3_CTRL_REG0 0x2208600
+#define ixPB1_TX_LANE3_OVRD_REG0 0x2208604
+#define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 0x2208608
+#define ixPB1_TX_LANE4_CTRL_REG0 0x2208840
+#define ixPB1_TX_LANE4_OVRD_REG0 0x2208844
+#define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 0x2208848
+#define ixPB1_TX_LANE5_CTRL_REG0 0x2208880
+#define ixPB1_TX_LANE5_OVRD_REG0 0x2208884
+#define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 0x2208888
+#define ixPB1_TX_LANE6_CTRL_REG0 0x2208900
+#define ixPB1_TX_LANE6_OVRD_REG0 0x2208904
+#define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 0x2208908
+#define ixPB1_TX_LANE7_CTRL_REG0 0x2208a00
+#define ixPB1_TX_LANE7_OVRD_REG0 0x2208a04
+#define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 0x2208a08
+#define ixPB1_TX_LANE8_CTRL_REG0 0x2209440
+#define ixPB1_TX_LANE8_OVRD_REG0 0x2209444
+#define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 0x2209448
+#define ixPB1_TX_LANE9_CTRL_REG0 0x2209480
+#define ixPB1_TX_LANE9_OVRD_REG0 0x2209484
+#define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 0x2209488
+#define ixPB1_TX_LANE10_CTRL_REG0 0x2209500
+#define ixPB1_TX_LANE10_OVRD_REG0 0x2209504
+#define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 0x2209508
+#define ixPB1_TX_LANE11_CTRL_REG0 0x2209600
+#define ixPB1_TX_LANE11_OVRD_REG0 0x2209604
+#define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 0x2209608
+#define ixPB1_TX_LANE12_CTRL_REG0 0x2209840
+#define ixPB1_TX_LANE12_OVRD_REG0 0x2209844
+#define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 0x2209848
+#define ixPB1_TX_LANE13_CTRL_REG0 0x2209880
+#define ixPB1_TX_LANE13_OVRD_REG0 0x2209884
+#define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 0x2209888
+#define ixPB1_TX_LANE14_CTRL_REG0 0x2209900
+#define ixPB1_TX_LANE14_OVRD_REG0 0x2209904
+#define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 0x2209908
+#define ixPB1_TX_LANE15_CTRL_REG0 0x2209a00
+#define ixPB1_TX_LANE15_OVRD_REG0 0x2209a04
+#define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 0x2209a08
+#define ixPB0_PIF_SCRATCH 0x1100001
+#define ixPB0_PIF_HW_DEBUG 0x1100002
+#define ixPB0_PIF_STRAP_0 0x1100003
+#define ixPB0_PIF_CTRL 0x1100004
+#define ixPB0_PIF_TX_CTRL 0x1100008
+#define ixPB0_PIF_TX_CTRL2 0x1100009
+#define ixPB0_PIF_RX_CTRL 0x110000a
+#define ixPB0_PIF_RX_CTRL2 0x110000b
+#define ixPB0_PIF_GLB_OVRD 0x110000c
+#define ixPB0_PIF_GLB_OVRD2 0x110000d
+#define ixPB0_PIF_BIF_CMD_STATUS 0x1100010
+#define ixPB0_PIF_CMD_BUS_CTRL 0x1100011
+#define ixPB0_PIF_CMD_BUS_GLB_OVRD 0x1100013
+#define ixPB0_PIF_LANE0_OVRD 0x1100014
+#define ixPB0_PIF_LANE0_OVRD2 0x1100015
+#define ixPB0_PIF_LANE1_OVRD 0x1100016
+#define ixPB0_PIF_LANE1_OVRD2 0x1100017
+#define ixPB0_PIF_LANE2_OVRD 0x1100018
+#define ixPB0_PIF_LANE2_OVRD2 0x1100019
+#define ixPB0_PIF_LANE3_OVRD 0x110001a
+#define ixPB0_PIF_LANE3_OVRD2 0x110001b
+#define ixPB0_PIF_LANE4_OVRD 0x110001c
+#define ixPB0_PIF_LANE4_OVRD2 0x110001d
+#define ixPB0_PIF_LANE5_OVRD 0x110001e
+#define ixPB0_PIF_LANE5_OVRD2 0x110001f
+#define ixPB0_PIF_LANE6_OVRD 0x1100020
+#define ixPB0_PIF_LANE6_OVRD2 0x1100021
+#define ixPB0_PIF_LANE7_OVRD 0x1100022
+#define ixPB0_PIF_LANE7_OVRD2 0x1100023
+#define ixPB1_PIF_SCRATCH 0x2100001
+#define ixPB1_PIF_HW_DEBUG 0x2100002
+#define ixPB1_PIF_STRAP_0 0x2100003
+#define ixPB1_PIF_CTRL 0x2100004
+#define ixPB1_PIF_TX_CTRL 0x2100008
+#define ixPB1_PIF_TX_CTRL2 0x2100009
+#define ixPB1_PIF_RX_CTRL 0x210000a
+#define ixPB1_PIF_RX_CTRL2 0x210000b
+#define ixPB1_PIF_GLB_OVRD 0x210000c
+#define ixPB1_PIF_GLB_OVRD2 0x210000d
+#define ixPB1_PIF_BIF_CMD_STATUS 0x2100010
+#define ixPB1_PIF_CMD_BUS_CTRL 0x2100011
+#define ixPB1_PIF_CMD_BUS_GLB_OVRD 0x2100013
+#define ixPB1_PIF_LANE0_OVRD 0x2100014
+#define ixPB1_PIF_LANE0_OVRD2 0x2100015
+#define ixPB1_PIF_LANE1_OVRD 0x2100016
+#define ixPB1_PIF_LANE1_OVRD2 0x2100017
+#define ixPB1_PIF_LANE2_OVRD 0x2100018
+#define ixPB1_PIF_LANE2_OVRD2 0x2100019
+#define ixPB1_PIF_LANE3_OVRD 0x210001a
+#define ixPB1_PIF_LANE3_OVRD2 0x210001b
+#define ixPB1_PIF_LANE4_OVRD 0x210001c
+#define ixPB1_PIF_LANE4_OVRD2 0x210001d
+#define ixPB1_PIF_LANE5_OVRD 0x210001e
+#define ixPB1_PIF_LANE5_OVRD2 0x210001f
+#define ixPB1_PIF_LANE6_OVRD 0x2100020
+#define ixPB1_PIF_LANE6_OVRD2 0x2100021
+#define ixPB1_PIF_LANE7_OVRD 0x2100022
+#define ixPB1_PIF_LANE7_OVRD2 0x2100023
+#define ixPCIEP_RESERVED 0x10010000
+#define ixPCIEP_SCRATCH 0x10010001
+#define ixPCIEP_HW_DEBUG 0x10010002
+#define ixPCIEP_PORT_CNTL 0x10010010
+#define ixPCIE_TX_CNTL 0x10010020
+#define ixPCIE_TX_REQUESTER_ID 0x10010021
+#define ixPCIE_TX_VENDOR_SPECIFIC 0x10010022
+#define ixPCIE_TX_REQUEST_NUM_CNTL 0x10010023
+#define ixPCIE_TX_SEQ 0x10010024
+#define ixPCIE_TX_REPLAY 0x10010025
+#define ixPCIE_TX_ACK_LATENCY_LIMIT 0x10010026
+#define ixPCIE_TX_CREDITS_ADVT_P 0x10010030
+#define ixPCIE_TX_CREDITS_ADVT_NP 0x10010031
+#define ixPCIE_TX_CREDITS_ADVT_CPL 0x10010032
+#define ixPCIE_TX_CREDITS_INIT_P 0x10010033
+#define ixPCIE_TX_CREDITS_INIT_NP 0x10010034
+#define ixPCIE_TX_CREDITS_INIT_CPL 0x10010035
+#define ixPCIE_TX_CREDITS_STATUS 0x10010036
+#define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x10010037
+#define ixPCIE_P_PORT_LANE_STATUS 0x10010050
+#define ixPCIE_FC_P 0x10010060
+#define ixPCIE_FC_NP 0x10010061
+#define ixPCIE_FC_CPL 0x10010062
+#define ixPCIE_ERR_CNTL 0x1001006a
+#define ixPCIE_RX_CNTL 0x10010070
+#define ixPCIE_RX_EXPECTED_SEQNUM 0x10010071
+#define ixPCIE_RX_VENDOR_SPECIFIC 0x10010072
+#define ixPCIE_RX_CNTL3 0x10010074
+#define ixPCIE_RX_CREDITS_ALLOCATED_P 0x10010080
+#define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x10010081
+#define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x10010082
+#define ixPCIEP_ERROR_INJECT_PHYSICAL 0x10010083
+#define ixPCIEP_ERROR_INJECT_TRANSACTION 0x10010084
+#define ixPCIEP_SRIOV_PRIV_CTRL 0x10010085
+#define ixPCIE_LC_CNTL 0x100100a0
+#define ixPCIE_LC_CNTL2 0x100100b1
+#define ixPCIE_LC_CNTL3 0x100100b5
+#define ixPCIE_LC_CNTL4 0x100100b6
+#define ixPCIE_LC_CNTL5 0x100100b7
+#define ixPCIE_LC_CNTL6 0x100100bb
+#define ixPCIE_LC_BW_CHANGE_CNTL 0x100100b2
+#define ixPCIE_LC_TRAINING_CNTL 0x100100a1
+#define ixPCIE_LC_LINK_WIDTH_CNTL 0x100100a2
+#define ixPCIE_LC_N_FTS_CNTL 0x100100a3
+#define ixPCIE_LC_SPEED_CNTL 0x100100a4
+#define ixPCIE_LC_CDR_CNTL 0x100100b3
+#define ixPCIE_LC_LANE_CNTL 0x100100b4
+#define ixPCIE_LC_FORCE_COEFF 0x100100b8
+#define ixPCIE_LC_BEST_EQ_SETTINGS 0x100100b9
+#define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x100100ba
+#define ixPCIE_LC_STATE0 0x100100a5
+#define ixPCIE_LC_STATE1 0x100100a6
+#define ixPCIE_LC_STATE2 0x100100a7
+#define ixPCIE_LC_STATE3 0x100100a8
+#define ixPCIE_LC_STATE4 0x100100a9
+#define ixPCIE_LC_STATE5 0x100100aa
+#define ixPCIEP_STRAP_LC 0x100100c0
+#define ixPCIEP_STRAP_MISC 0x100100c1
+#define ixPCIEP_BCH_ECC_CNTL 0x100100d0
+#define ixPCIEP_HPGI_PRIVATE 0x100100d2
+#define ixPCIEP_HPGI 0x100100da
+#define mmPCIEMSIX_VECT0_ADDR_LO 0x6000
+#define mmPCIEMSIX_VECT0_ADDR_HI 0x6001
+#define mmPCIEMSIX_VECT0_MSG_DATA 0x6002
+#define mmPCIEMSIX_VECT0_CONTROL 0x6003
+#define mmPCIEMSIX_VECT1_ADDR_LO 0x6004
+#define mmPCIEMSIX_VECT1_ADDR_HI 0x6005
+#define mmPCIEMSIX_VECT1_MSG_DATA 0x6006
+#define mmPCIEMSIX_VECT1_CONTROL 0x6007
+#define mmPCIEMSIX_VECT2_ADDR_LO 0x6008
+#define mmPCIEMSIX_VECT2_ADDR_HI 0x6009
+#define mmPCIEMSIX_VECT2_MSG_DATA 0x600a
+#define mmPCIEMSIX_VECT2_CONTROL 0x600b
+#define mmPCIEMSIX_VECT3_ADDR_LO 0x600c
+#define mmPCIEMSIX_VECT3_ADDR_HI 0x600d
+#define mmPCIEMSIX_VECT3_MSG_DATA 0x600e
+#define mmPCIEMSIX_VECT3_CONTROL 0x600f
+#define mmPCIEMSIX_PBA 0x6200
+#define mmBIF_RFE_SNOOP_REG 0x27
+#define mmBIF_RFE_WARMRST_CNTL 0x1459
+#define mmBIF_RFE_SOFTRST_CNTL 0x1441
+#define mmBIF_RFE_IMPRST_CNTL 0x1458
+#define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER 0x1442
+#define mmBIF_RFE_MASTER_SOFTRST_TRIGGER 0x1443
+#define mmBIF_PWDN_COMMAND 0x1444
+#define mmBIF_PWDN_STATUS 0x1445
+#define mmBIF_RFE_MST_BU_CMDSTATUS 0x1446
+#define mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS 0x1447
+#define mmBIF_RFE_MST_SMBUS_CMDSTATUS 0x1448
+#define mmBIF_RFE_MST_BX_CMDSTATUS 0x1449
+#define mmBIF_RFE_MST_TMOUT_STATUS 0x144b
+#define mmBIF_RFE_MMCFG_CNTL 0x144c
+#define mmBIF_CC_RFE_IMP_OVERRIDECNTL 0x1455
+#define mmBIF_IMPCTL_SMPLCNTL 0x1450
+#define mmBIF_IMPCTL_RXCNTL 0x1451
+#define mmBIF_IMPCTL_TXCNTL_pd 0x1452
+#define mmBIF_IMPCTL_TXCNTL_pu 0x1453
+#define mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD 0x1454
+
+#endif /* BIF_5_0_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_enum.h
new file mode 100644
index 000000000000..46b75f4bbc36
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_enum.h
@@ -0,0 +1,1198 @@
+/*
+ * BIF_5_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef BIF_5_0_ENUM_H
+#define BIF_5_0_ENUM_H
+
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0x0,
+ ENDIAN_8IN16 = 0x1,
+ ENDIAN_8IN32 = 0x2,
+ ENDIAN_8IN64 = 0x3,
+} SurfaceEndian;
+typedef enum ArrayMode {
+ ARRAY_LINEAR_GENERAL = 0x0,
+ ARRAY_LINEAR_ALIGNED = 0x1,
+ ARRAY_1D_TILED_THIN1 = 0x2,
+ ARRAY_1D_TILED_THICK = 0x3,
+ ARRAY_2D_TILED_THIN1 = 0x4,
+ ARRAY_PRT_TILED_THIN1 = 0x5,
+ ARRAY_PRT_2D_TILED_THIN1 = 0x6,
+ ARRAY_2D_TILED_THICK = 0x7,
+ ARRAY_2D_TILED_XTHICK = 0x8,
+ ARRAY_PRT_TILED_THICK = 0x9,
+ ARRAY_PRT_2D_TILED_THICK = 0xa,
+ ARRAY_PRT_3D_TILED_THIN1 = 0xb,
+ ARRAY_3D_TILED_THIN1 = 0xc,
+ ARRAY_3D_TILED_THICK = 0xd,
+ ARRAY_3D_TILED_XTHICK = 0xe,
+ ARRAY_PRT_3D_TILED_THICK = 0xf,
+} ArrayMode;
+typedef enum PipeTiling {
+ CONFIG_1_PIPE = 0x0,
+ CONFIG_2_PIPE = 0x1,
+ CONFIG_4_PIPE = 0x2,
+ CONFIG_8_PIPE = 0x3,
+} PipeTiling;
+typedef enum BankTiling {
+ CONFIG_4_BANK = 0x0,
+ CONFIG_8_BANK = 0x1,
+} BankTiling;
+typedef enum GroupInterleave {
+ CONFIG_256B_GROUP = 0x0,
+ CONFIG_512B_GROUP = 0x1,
+} GroupInterleave;
+typedef enum RowTiling {
+ CONFIG_1KB_ROW = 0x0,
+ CONFIG_2KB_ROW = 0x1,
+ CONFIG_4KB_ROW = 0x2,
+ CONFIG_8KB_ROW = 0x3,
+ CONFIG_1KB_ROW_OPT = 0x4,
+ CONFIG_2KB_ROW_OPT = 0x5,
+ CONFIG_4KB_ROW_OPT = 0x6,
+ CONFIG_8KB_ROW_OPT = 0x7,
+} RowTiling;
+typedef enum BankSwapBytes {
+ CONFIG_128B_SWAPS = 0x0,
+ CONFIG_256B_SWAPS = 0x1,
+ CONFIG_512B_SWAPS = 0x2,
+ CONFIG_1KB_SWAPS = 0x3,
+} BankSwapBytes;
+typedef enum SampleSplitBytes {
+ CONFIG_1KB_SPLIT = 0x0,
+ CONFIG_2KB_SPLIT = 0x1,
+ CONFIG_4KB_SPLIT = 0x2,
+ CONFIG_8KB_SPLIT = 0x3,
+} SampleSplitBytes;
+typedef enum NumPipes {
+ ADDR_CONFIG_1_PIPE = 0x0,
+ ADDR_CONFIG_2_PIPE = 0x1,
+ ADDR_CONFIG_4_PIPE = 0x2,
+ ADDR_CONFIG_8_PIPE = 0x3,
+} NumPipes;
+typedef enum PipeInterleaveSize {
+ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
+ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
+} PipeInterleaveSize;
+typedef enum BankInterleaveSize {
+ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
+ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
+ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
+ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
+} BankInterleaveSize;
+typedef enum NumShaderEngines {
+ ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
+ ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
+} NumShaderEngines;
+typedef enum ShaderEngineTileSize {
+ ADDR_CONFIG_SE_TILE_16 = 0x0,
+ ADDR_CONFIG_SE_TILE_32 = 0x1,
+} ShaderEngineTileSize;
+typedef enum NumGPUs {
+ ADDR_CONFIG_1_GPU = 0x0,
+ ADDR_CONFIG_2_GPU = 0x1,
+ ADDR_CONFIG_4_GPU = 0x2,
+} NumGPUs;
+typedef enum MultiGPUTileSize {
+ ADDR_CONFIG_GPU_TILE_16 = 0x0,
+ ADDR_CONFIG_GPU_TILE_32 = 0x1,
+ ADDR_CONFIG_GPU_TILE_64 = 0x2,
+ ADDR_CONFIG_GPU_TILE_128 = 0x3,
+} MultiGPUTileSize;
+typedef enum RowSize {
+ ADDR_CONFIG_1KB_ROW = 0x0,
+ ADDR_CONFIG_2KB_ROW = 0x1,
+ ADDR_CONFIG_4KB_ROW = 0x2,
+} RowSize;
+typedef enum NumLowerPipes {
+ ADDR_CONFIG_1_LOWER_PIPES = 0x0,
+ ADDR_CONFIG_2_LOWER_PIPES = 0x1,
+} NumLowerPipes;
+typedef enum DebugBlockId {
+ DBG_CLIENT_BLKID_RESERVED = 0x0,
+ DBG_CLIENT_BLKID_dbg = 0x1,
+ DBG_CLIENT_BLKID_scf2 = 0x2,
+ DBG_CLIENT_BLKID_mcd5 = 0x3,
+ DBG_CLIENT_BLKID_vmc = 0x4,
+ DBG_CLIENT_BLKID_sx30 = 0x5,
+ DBG_CLIENT_BLKID_mcd2 = 0x6,
+ DBG_CLIENT_BLKID_bci1 = 0x7,
+ DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8,
+ DBG_CLIENT_BLKID_mcc0 = 0x9,
+ DBG_CLIENT_BLKID_uvdf_0 = 0xa,
+ DBG_CLIENT_BLKID_uvdf_1 = 0xb,
+ DBG_CLIENT_BLKID_uvdf_2 = 0xc,
+ DBG_CLIENT_BLKID_uvdi_0 = 0xd,
+ DBG_CLIENT_BLKID_bci0 = 0xe,
+ DBG_CLIENT_BLKID_vcec0_0 = 0xf,
+ DBG_CLIENT_BLKID_cb100 = 0x10,
+ DBG_CLIENT_BLKID_cb001 = 0x11,
+ DBG_CLIENT_BLKID_mcd4 = 0x12,
+ DBG_CLIENT_BLKID_tmonw00 = 0x13,
+ DBG_CLIENT_BLKID_cb101 = 0x14,
+ DBG_CLIENT_BLKID_sx10 = 0x15,
+ DBG_CLIENT_BLKID_cb301 = 0x16,
+ DBG_CLIENT_BLKID_tmonw01 = 0x17,
+ DBG_CLIENT_BLKID_vcea0_0 = 0x18,
+ DBG_CLIENT_BLKID_vcea0_1 = 0x19,
+ DBG_CLIENT_BLKID_vcea0_2 = 0x1a,
+ DBG_CLIENT_BLKID_vcea0_3 = 0x1b,
+ DBG_CLIENT_BLKID_scf1 = 0x1c,
+ DBG_CLIENT_BLKID_sx20 = 0x1d,
+ DBG_CLIENT_BLKID_spim1 = 0x1e,
+ DBG_CLIENT_BLKID_pa10 = 0x1f,
+ DBG_CLIENT_BLKID_pa00 = 0x20,
+ DBG_CLIENT_BLKID_gmcon = 0x21,
+ DBG_CLIENT_BLKID_mcb = 0x22,
+ DBG_CLIENT_BLKID_vgt0 = 0x23,
+ DBG_CLIENT_BLKID_pc0 = 0x24,
+ DBG_CLIENT_BLKID_bci2 = 0x25,
+ DBG_CLIENT_BLKID_uvdb_0 = 0x26,
+ DBG_CLIENT_BLKID_spim3 = 0x27,
+ DBG_CLIENT_BLKID_cpc_0 = 0x28,
+ DBG_CLIENT_BLKID_cpc_1 = 0x29,
+ DBG_CLIENT_BLKID_uvdm_0 = 0x2a,
+ DBG_CLIENT_BLKID_uvdm_1 = 0x2b,
+ DBG_CLIENT_BLKID_uvdm_2 = 0x2c,
+ DBG_CLIENT_BLKID_uvdm_3 = 0x2d,
+ DBG_CLIENT_BLKID_cb000 = 0x2e,
+ DBG_CLIENT_BLKID_spim0 = 0x2f,
+ DBG_CLIENT_BLKID_mcc2 = 0x30,
+ DBG_CLIENT_BLKID_ds0 = 0x31,
+ DBG_CLIENT_BLKID_srbm = 0x32,
+ DBG_CLIENT_BLKID_ih = 0x33,
+ DBG_CLIENT_BLKID_sem = 0x34,
+ DBG_CLIENT_BLKID_sdma_0 = 0x35,
+ DBG_CLIENT_BLKID_sdma_1 = 0x36,
+ DBG_CLIENT_BLKID_hdp = 0x37,
+ DBG_CLIENT_BLKID_acp_0 = 0x38,
+ DBG_CLIENT_BLKID_acp_1 = 0x39,
+ DBG_CLIENT_BLKID_cb200 = 0x3a,
+ DBG_CLIENT_BLKID_scf3 = 0x3b,
+ DBG_CLIENT_BLKID_vceb1_0 = 0x3c,
+ DBG_CLIENT_BLKID_vcea1_0 = 0x3d,
+ DBG_CLIENT_BLKID_vcea1_1 = 0x3e,
+ DBG_CLIENT_BLKID_vcea1_2 = 0x3f,
+ DBG_CLIENT_BLKID_vcea1_3 = 0x40,
+ DBG_CLIENT_BLKID_bci3 = 0x41,
+ DBG_CLIENT_BLKID_mcd0 = 0x42,
+ DBG_CLIENT_BLKID_pa11 = 0x43,
+ DBG_CLIENT_BLKID_pa01 = 0x44,
+ DBG_CLIENT_BLKID_cb201 = 0x45,
+ DBG_CLIENT_BLKID_spim2 = 0x46,
+ DBG_CLIENT_BLKID_vgt2 = 0x47,
+ DBG_CLIENT_BLKID_pc2 = 0x48,
+ DBG_CLIENT_BLKID_smu_0 = 0x49,
+ DBG_CLIENT_BLKID_smu_1 = 0x4a,
+ DBG_CLIENT_BLKID_smu_2 = 0x4b,
+ DBG_CLIENT_BLKID_cb1 = 0x4c,
+ DBG_CLIENT_BLKID_ia0 = 0x4d,
+ DBG_CLIENT_BLKID_wd = 0x4e,
+ DBG_CLIENT_BLKID_ia1 = 0x4f,
+ DBG_CLIENT_BLKID_vcec1_0 = 0x50,
+ DBG_CLIENT_BLKID_scf0 = 0x51,
+ DBG_CLIENT_BLKID_vgt1 = 0x52,
+ DBG_CLIENT_BLKID_pc1 = 0x53,
+ DBG_CLIENT_BLKID_cb0 = 0x54,
+ DBG_CLIENT_BLKID_gdc_one_0 = 0x55,
+ DBG_CLIENT_BLKID_gdc_one_1 = 0x56,
+ DBG_CLIENT_BLKID_gdc_one_2 = 0x57,
+ DBG_CLIENT_BLKID_gdc_one_3 = 0x58,
+ DBG_CLIENT_BLKID_gdc_one_4 = 0x59,
+ DBG_CLIENT_BLKID_gdc_one_5 = 0x5a,
+ DBG_CLIENT_BLKID_gdc_one_6 = 0x5b,
+ DBG_CLIENT_BLKID_gdc_one_7 = 0x5c,
+ DBG_CLIENT_BLKID_gdc_one_8 = 0x5d,
+ DBG_CLIENT_BLKID_gdc_one_9 = 0x5e,
+ DBG_CLIENT_BLKID_gdc_one_10 = 0x5f,
+ DBG_CLIENT_BLKID_gdc_one_11 = 0x60,
+ DBG_CLIENT_BLKID_gdc_one_12 = 0x61,
+ DBG_CLIENT_BLKID_gdc_one_13 = 0x62,
+ DBG_CLIENT_BLKID_gdc_one_14 = 0x63,
+ DBG_CLIENT_BLKID_gdc_one_15 = 0x64,
+ DBG_CLIENT_BLKID_gdc_one_16 = 0x65,
+ DBG_CLIENT_BLKID_gdc_one_17 = 0x66,
+ DBG_CLIENT_BLKID_gdc_one_18 = 0x67,
+ DBG_CLIENT_BLKID_gdc_one_19 = 0x68,
+ DBG_CLIENT_BLKID_gdc_one_20 = 0x69,
+ DBG_CLIENT_BLKID_gdc_one_21 = 0x6a,
+ DBG_CLIENT_BLKID_gdc_one_22 = 0x6b,
+ DBG_CLIENT_BLKID_gdc_one_23 = 0x6c,
+ DBG_CLIENT_BLKID_gdc_one_24 = 0x6d,
+ DBG_CLIENT_BLKID_gdc_one_25 = 0x6e,
+ DBG_CLIENT_BLKID_gdc_one_26 = 0x6f,
+ DBG_CLIENT_BLKID_gdc_one_27 = 0x70,
+ DBG_CLIENT_BLKID_gdc_one_28 = 0x71,
+ DBG_CLIENT_BLKID_gdc_one_29 = 0x72,
+ DBG_CLIENT_BLKID_gdc_one_30 = 0x73,
+ DBG_CLIENT_BLKID_gdc_one_31 = 0x74,
+ DBG_CLIENT_BLKID_gdc_one_32 = 0x75,
+ DBG_CLIENT_BLKID_gdc_one_33 = 0x76,
+ DBG_CLIENT_BLKID_gdc_one_34 = 0x77,
+ DBG_CLIENT_BLKID_gdc_one_35 = 0x78,
+ DBG_CLIENT_BLKID_vceb0_0 = 0x79,
+ DBG_CLIENT_BLKID_vgt3 = 0x7a,
+ DBG_CLIENT_BLKID_pc3 = 0x7b,
+ DBG_CLIENT_BLKID_mcd3 = 0x7c,
+ DBG_CLIENT_BLKID_uvdu_0 = 0x7d,
+ DBG_CLIENT_BLKID_uvdu_1 = 0x7e,
+ DBG_CLIENT_BLKID_uvdu_2 = 0x7f,
+ DBG_CLIENT_BLKID_uvdu_3 = 0x80,
+ DBG_CLIENT_BLKID_uvdu_4 = 0x81,
+ DBG_CLIENT_BLKID_uvdu_5 = 0x82,
+ DBG_CLIENT_BLKID_uvdu_6 = 0x83,
+ DBG_CLIENT_BLKID_cb300 = 0x84,
+ DBG_CLIENT_BLKID_mcd1 = 0x85,
+ DBG_CLIENT_BLKID_sx00 = 0x86,
+ DBG_CLIENT_BLKID_uvdc_0 = 0x87,
+ DBG_CLIENT_BLKID_uvdc_1 = 0x88,
+ DBG_CLIENT_BLKID_mcc3 = 0x89,
+ DBG_CLIENT_BLKID_cpg_0 = 0x8a,
+ DBG_CLIENT_BLKID_cpg_1 = 0x8b,
+ DBG_CLIENT_BLKID_gck = 0x8c,
+ DBG_CLIENT_BLKID_mcc1 = 0x8d,
+ DBG_CLIENT_BLKID_cpf_0 = 0x8e,
+ DBG_CLIENT_BLKID_cpf_1 = 0x8f,
+ DBG_CLIENT_BLKID_rlc = 0x90,
+ DBG_CLIENT_BLKID_grbm = 0x91,
+ DBG_CLIENT_BLKID_sammsp = 0x92,
+ DBG_CLIENT_BLKID_dci_pg = 0x93,
+ DBG_CLIENT_BLKID_dci_0 = 0x94,
+ DBG_CLIENT_BLKID_dccg0_0 = 0x95,
+ DBG_CLIENT_BLKID_dccg0_1 = 0x96,
+ DBG_CLIENT_BLKID_dcfe01_0 = 0x97,
+ DBG_CLIENT_BLKID_dcfe02_0 = 0x98,
+ DBG_CLIENT_BLKID_dcfe03_0 = 0x99,
+ DBG_CLIENT_BLKID_dcfe04_0 = 0x9a,
+ DBG_CLIENT_BLKID_dcfe05_0 = 0x9b,
+ DBG_CLIENT_BLKID_dcfe06_0 = 0x9c,
+ DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d,
+} DebugBlockId;
+typedef enum DebugBlockId_OLD {
+ DBG_BLOCK_ID_RESERVED = 0x0,
+ DBG_BLOCK_ID_DBG = 0x1,
+ DBG_BLOCK_ID_VMC = 0x2,
+ DBG_BLOCK_ID_PDMA = 0x3,
+ DBG_BLOCK_ID_CG = 0x4,
+ DBG_BLOCK_ID_SRBM = 0x5,
+ DBG_BLOCK_ID_GRBM = 0x6,
+ DBG_BLOCK_ID_RLC = 0x7,
+ DBG_BLOCK_ID_CSC = 0x8,
+ DBG_BLOCK_ID_SEM = 0x9,
+ DBG_BLOCK_ID_IH = 0xa,
+ DBG_BLOCK_ID_SC = 0xb,
+ DBG_BLOCK_ID_SQ = 0xc,
+ DBG_BLOCK_ID_AVP = 0xd,
+ DBG_BLOCK_ID_GMCON = 0xe,
+ DBG_BLOCK_ID_SMU = 0xf,
+ DBG_BLOCK_ID_DMA0 = 0x10,
+ DBG_BLOCK_ID_DMA1 = 0x11,
+ DBG_BLOCK_ID_SPIM = 0x12,
+ DBG_BLOCK_ID_GDS = 0x13,
+ DBG_BLOCK_ID_SPIS = 0x14,
+ DBG_BLOCK_ID_UNUSED0 = 0x15,
+ DBG_BLOCK_ID_PA0 = 0x16,
+ DBG_BLOCK_ID_PA1 = 0x17,
+ DBG_BLOCK_ID_CP0 = 0x18,
+ DBG_BLOCK_ID_CP1 = 0x19,
+ DBG_BLOCK_ID_CP2 = 0x1a,
+ DBG_BLOCK_ID_UNUSED1 = 0x1b,
+ DBG_BLOCK_ID_UVDU = 0x1c,
+ DBG_BLOCK_ID_UVDM = 0x1d,
+ DBG_BLOCK_ID_VCE = 0x1e,
+ DBG_BLOCK_ID_UNUSED2 = 0x1f,
+ DBG_BLOCK_ID_VGT0 = 0x20,
+ DBG_BLOCK_ID_VGT1 = 0x21,
+ DBG_BLOCK_ID_IA = 0x22,
+ DBG_BLOCK_ID_UNUSED3 = 0x23,
+ DBG_BLOCK_ID_SCT0 = 0x24,
+ DBG_BLOCK_ID_SCT1 = 0x25,
+ DBG_BLOCK_ID_SPM0 = 0x26,
+ DBG_BLOCK_ID_SPM1 = 0x27,
+ DBG_BLOCK_ID_TCAA = 0x28,
+ DBG_BLOCK_ID_TCAB = 0x29,
+ DBG_BLOCK_ID_TCCA = 0x2a,
+ DBG_BLOCK_ID_TCCB = 0x2b,
+ DBG_BLOCK_ID_MCC0 = 0x2c,
+ DBG_BLOCK_ID_MCC1 = 0x2d,
+ DBG_BLOCK_ID_MCC2 = 0x2e,
+ DBG_BLOCK_ID_MCC3 = 0x2f,
+ DBG_BLOCK_ID_SX0 = 0x30,
+ DBG_BLOCK_ID_SX1 = 0x31,
+ DBG_BLOCK_ID_SX2 = 0x32,
+ DBG_BLOCK_ID_SX3 = 0x33,
+ DBG_BLOCK_ID_UNUSED4 = 0x34,
+ DBG_BLOCK_ID_UNUSED5 = 0x35,
+ DBG_BLOCK_ID_UNUSED6 = 0x36,
+ DBG_BLOCK_ID_UNUSED7 = 0x37,
+ DBG_BLOCK_ID_PC0 = 0x38,
+ DBG_BLOCK_ID_PC1 = 0x39,
+ DBG_BLOCK_ID_UNUSED8 = 0x3a,
+ DBG_BLOCK_ID_UNUSED9 = 0x3b,
+ DBG_BLOCK_ID_UNUSED10 = 0x3c,
+ DBG_BLOCK_ID_UNUSED11 = 0x3d,
+ DBG_BLOCK_ID_MCB = 0x3e,
+ DBG_BLOCK_ID_UNUSED12 = 0x3f,
+ DBG_BLOCK_ID_SCB0 = 0x40,
+ DBG_BLOCK_ID_SCB1 = 0x41,
+ DBG_BLOCK_ID_UNUSED13 = 0x42,
+ DBG_BLOCK_ID_UNUSED14 = 0x43,
+ DBG_BLOCK_ID_SCF0 = 0x44,
+ DBG_BLOCK_ID_SCF1 = 0x45,
+ DBG_BLOCK_ID_UNUSED15 = 0x46,
+ DBG_BLOCK_ID_UNUSED16 = 0x47,
+ DBG_BLOCK_ID_BCI0 = 0x48,
+ DBG_BLOCK_ID_BCI1 = 0x49,
+ DBG_BLOCK_ID_BCI2 = 0x4a,
+ DBG_BLOCK_ID_BCI3 = 0x4b,
+ DBG_BLOCK_ID_UNUSED17 = 0x4c,
+ DBG_BLOCK_ID_UNUSED18 = 0x4d,
+ DBG_BLOCK_ID_UNUSED19 = 0x4e,
+ DBG_BLOCK_ID_UNUSED20 = 0x4f,
+ DBG_BLOCK_ID_CB00 = 0x50,
+ DBG_BLOCK_ID_CB01 = 0x51,
+ DBG_BLOCK_ID_CB02 = 0x52,
+ DBG_BLOCK_ID_CB03 = 0x53,
+ DBG_BLOCK_ID_CB04 = 0x54,
+ DBG_BLOCK_ID_UNUSED21 = 0x55,
+ DBG_BLOCK_ID_UNUSED22 = 0x56,
+ DBG_BLOCK_ID_UNUSED23 = 0x57,
+ DBG_BLOCK_ID_CB10 = 0x58,
+ DBG_BLOCK_ID_CB11 = 0x59,
+ DBG_BLOCK_ID_CB12 = 0x5a,
+ DBG_BLOCK_ID_CB13 = 0x5b,
+ DBG_BLOCK_ID_CB14 = 0x5c,
+ DBG_BLOCK_ID_UNUSED24 = 0x5d,
+ DBG_BLOCK_ID_UNUSED25 = 0x5e,
+ DBG_BLOCK_ID_UNUSED26 = 0x5f,
+ DBG_BLOCK_ID_TCP0 = 0x60,
+ DBG_BLOCK_ID_TCP1 = 0x61,
+ DBG_BLOCK_ID_TCP2 = 0x62,
+ DBG_BLOCK_ID_TCP3 = 0x63,
+ DBG_BLOCK_ID_TCP4 = 0x64,
+ DBG_BLOCK_ID_TCP5 = 0x65,
+ DBG_BLOCK_ID_TCP6 = 0x66,
+ DBG_BLOCK_ID_TCP7 = 0x67,
+ DBG_BLOCK_ID_TCP8 = 0x68,
+ DBG_BLOCK_ID_TCP9 = 0x69,
+ DBG_BLOCK_ID_TCP10 = 0x6a,
+ DBG_BLOCK_ID_TCP11 = 0x6b,
+ DBG_BLOCK_ID_TCP12 = 0x6c,
+ DBG_BLOCK_ID_TCP13 = 0x6d,
+ DBG_BLOCK_ID_TCP14 = 0x6e,
+ DBG_BLOCK_ID_TCP15 = 0x6f,
+ DBG_BLOCK_ID_TCP16 = 0x70,
+ DBG_BLOCK_ID_TCP17 = 0x71,
+ DBG_BLOCK_ID_TCP18 = 0x72,
+ DBG_BLOCK_ID_TCP19 = 0x73,
+ DBG_BLOCK_ID_TCP20 = 0x74,
+ DBG_BLOCK_ID_TCP21 = 0x75,
+ DBG_BLOCK_ID_TCP22 = 0x76,
+ DBG_BLOCK_ID_TCP23 = 0x77,
+ DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
+ DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
+ DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
+ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
+ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
+ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
+ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
+ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
+ DBG_BLOCK_ID_DB00 = 0x80,
+ DBG_BLOCK_ID_DB01 = 0x81,
+ DBG_BLOCK_ID_DB02 = 0x82,
+ DBG_BLOCK_ID_DB03 = 0x83,
+ DBG_BLOCK_ID_DB04 = 0x84,
+ DBG_BLOCK_ID_UNUSED27 = 0x85,
+ DBG_BLOCK_ID_UNUSED28 = 0x86,
+ DBG_BLOCK_ID_UNUSED29 = 0x87,
+ DBG_BLOCK_ID_DB10 = 0x88,
+ DBG_BLOCK_ID_DB11 = 0x89,
+ DBG_BLOCK_ID_DB12 = 0x8a,
+ DBG_BLOCK_ID_DB13 = 0x8b,
+ DBG_BLOCK_ID_DB14 = 0x8c,
+ DBG_BLOCK_ID_UNUSED30 = 0x8d,
+ DBG_BLOCK_ID_UNUSED31 = 0x8e,
+ DBG_BLOCK_ID_UNUSED32 = 0x8f,
+ DBG_BLOCK_ID_TCC0 = 0x90,
+ DBG_BLOCK_ID_TCC1 = 0x91,
+ DBG_BLOCK_ID_TCC2 = 0x92,
+ DBG_BLOCK_ID_TCC3 = 0x93,
+ DBG_BLOCK_ID_TCC4 = 0x94,
+ DBG_BLOCK_ID_TCC5 = 0x95,
+ DBG_BLOCK_ID_TCC6 = 0x96,
+ DBG_BLOCK_ID_TCC7 = 0x97,
+ DBG_BLOCK_ID_SPS00 = 0x98,
+ DBG_BLOCK_ID_SPS01 = 0x99,
+ DBG_BLOCK_ID_SPS02 = 0x9a,
+ DBG_BLOCK_ID_SPS10 = 0x9b,
+ DBG_BLOCK_ID_SPS11 = 0x9c,
+ DBG_BLOCK_ID_SPS12 = 0x9d,
+ DBG_BLOCK_ID_UNUSED33 = 0x9e,
+ DBG_BLOCK_ID_UNUSED34 = 0x9f,
+ DBG_BLOCK_ID_TA00 = 0xa0,
+ DBG_BLOCK_ID_TA01 = 0xa1,
+ DBG_BLOCK_ID_TA02 = 0xa2,
+ DBG_BLOCK_ID_TA03 = 0xa3,
+ DBG_BLOCK_ID_TA04 = 0xa4,
+ DBG_BLOCK_ID_TA05 = 0xa5,
+ DBG_BLOCK_ID_TA06 = 0xa6,
+ DBG_BLOCK_ID_TA07 = 0xa7,
+ DBG_BLOCK_ID_TA08 = 0xa8,
+ DBG_BLOCK_ID_TA09 = 0xa9,
+ DBG_BLOCK_ID_TA0A = 0xaa,
+ DBG_BLOCK_ID_TA0B = 0xab,
+ DBG_BLOCK_ID_UNUSED35 = 0xac,
+ DBG_BLOCK_ID_UNUSED36 = 0xad,
+ DBG_BLOCK_ID_UNUSED37 = 0xae,
+ DBG_BLOCK_ID_UNUSED38 = 0xaf,
+ DBG_BLOCK_ID_TA10 = 0xb0,
+ DBG_BLOCK_ID_TA11 = 0xb1,
+ DBG_BLOCK_ID_TA12 = 0xb2,
+ DBG_BLOCK_ID_TA13 = 0xb3,
+ DBG_BLOCK_ID_TA14 = 0xb4,
+ DBG_BLOCK_ID_TA15 = 0xb5,
+ DBG_BLOCK_ID_TA16 = 0xb6,
+ DBG_BLOCK_ID_TA17 = 0xb7,
+ DBG_BLOCK_ID_TA18 = 0xb8,
+ DBG_BLOCK_ID_TA19 = 0xb9,
+ DBG_BLOCK_ID_TA1A = 0xba,
+ DBG_BLOCK_ID_TA1B = 0xbb,
+ DBG_BLOCK_ID_UNUSED39 = 0xbc,
+ DBG_BLOCK_ID_UNUSED40 = 0xbd,
+ DBG_BLOCK_ID_UNUSED41 = 0xbe,
+ DBG_BLOCK_ID_UNUSED42 = 0xbf,
+ DBG_BLOCK_ID_TD00 = 0xc0,
+ DBG_BLOCK_ID_TD01 = 0xc1,
+ DBG_BLOCK_ID_TD02 = 0xc2,
+ DBG_BLOCK_ID_TD03 = 0xc3,
+ DBG_BLOCK_ID_TD04 = 0xc4,
+ DBG_BLOCK_ID_TD05 = 0xc5,
+ DBG_BLOCK_ID_TD06 = 0xc6,
+ DBG_BLOCK_ID_TD07 = 0xc7,
+ DBG_BLOCK_ID_TD08 = 0xc8,
+ DBG_BLOCK_ID_TD09 = 0xc9,
+ DBG_BLOCK_ID_TD0A = 0xca,
+ DBG_BLOCK_ID_TD0B = 0xcb,
+ DBG_BLOCK_ID_UNUSED43 = 0xcc,
+ DBG_BLOCK_ID_UNUSED44 = 0xcd,
+ DBG_BLOCK_ID_UNUSED45 = 0xce,
+ DBG_BLOCK_ID_UNUSED46 = 0xcf,
+ DBG_BLOCK_ID_TD10 = 0xd0,
+ DBG_BLOCK_ID_TD11 = 0xd1,
+ DBG_BLOCK_ID_TD12 = 0xd2,
+ DBG_BLOCK_ID_TD13 = 0xd3,
+ DBG_BLOCK_ID_TD14 = 0xd4,
+ DBG_BLOCK_ID_TD15 = 0xd5,
+ DBG_BLOCK_ID_TD16 = 0xd6,
+ DBG_BLOCK_ID_TD17 = 0xd7,
+ DBG_BLOCK_ID_TD18 = 0xd8,
+ DBG_BLOCK_ID_TD19 = 0xd9,
+ DBG_BLOCK_ID_TD1A = 0xda,
+ DBG_BLOCK_ID_TD1B = 0xdb,
+ DBG_BLOCK_ID_UNUSED47 = 0xdc,
+ DBG_BLOCK_ID_UNUSED48 = 0xdd,
+ DBG_BLOCK_ID_UNUSED49 = 0xde,
+ DBG_BLOCK_ID_UNUSED50 = 0xdf,
+ DBG_BLOCK_ID_MCD0 = 0xe0,
+ DBG_BLOCK_ID_MCD1 = 0xe1,
+ DBG_BLOCK_ID_MCD2 = 0xe2,
+ DBG_BLOCK_ID_MCD3 = 0xe3,
+ DBG_BLOCK_ID_MCD4 = 0xe4,
+ DBG_BLOCK_ID_MCD5 = 0xe5,
+ DBG_BLOCK_ID_UNUSED51 = 0xe6,
+ DBG_BLOCK_ID_UNUSED52 = 0xe7,
+} DebugBlockId_OLD;
+typedef enum DebugBlockId_BY2 {
+ DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
+ DBG_BLOCK_ID_VMC_BY2 = 0x1,
+ DBG_BLOCK_ID_CG_BY2 = 0x2,
+ DBG_BLOCK_ID_GRBM_BY2 = 0x3,
+ DBG_BLOCK_ID_CSC_BY2 = 0x4,
+ DBG_BLOCK_ID_IH_BY2 = 0x5,
+ DBG_BLOCK_ID_SQ_BY2 = 0x6,
+ DBG_BLOCK_ID_GMCON_BY2 = 0x7,
+ DBG_BLOCK_ID_DMA0_BY2 = 0x8,
+ DBG_BLOCK_ID_SPIM_BY2 = 0x9,
+ DBG_BLOCK_ID_SPIS_BY2 = 0xa,
+ DBG_BLOCK_ID_PA0_BY2 = 0xb,
+ DBG_BLOCK_ID_CP0_BY2 = 0xc,
+ DBG_BLOCK_ID_CP2_BY2 = 0xd,
+ DBG_BLOCK_ID_UVDU_BY2 = 0xe,
+ DBG_BLOCK_ID_VCE_BY2 = 0xf,
+ DBG_BLOCK_ID_VGT0_BY2 = 0x10,
+ DBG_BLOCK_ID_IA_BY2 = 0x11,
+ DBG_BLOCK_ID_SCT0_BY2 = 0x12,
+ DBG_BLOCK_ID_SPM0_BY2 = 0x13,
+ DBG_BLOCK_ID_TCAA_BY2 = 0x14,
+ DBG_BLOCK_ID_TCCA_BY2 = 0x15,
+ DBG_BLOCK_ID_MCC0_BY2 = 0x16,
+ DBG_BLOCK_ID_MCC2_BY2 = 0x17,
+ DBG_BLOCK_ID_SX0_BY2 = 0x18,
+ DBG_BLOCK_ID_SX2_BY2 = 0x19,
+ DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
+ DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
+ DBG_BLOCK_ID_PC0_BY2 = 0x1c,
+ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
+ DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
+ DBG_BLOCK_ID_MCB_BY2 = 0x1f,
+ DBG_BLOCK_ID_SCB0_BY2 = 0x20,
+ DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
+ DBG_BLOCK_ID_SCF0_BY2 = 0x22,
+ DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
+ DBG_BLOCK_ID_BCI0_BY2 = 0x24,
+ DBG_BLOCK_ID_BCI2_BY2 = 0x25,
+ DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
+ DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
+ DBG_BLOCK_ID_CB00_BY2 = 0x28,
+ DBG_BLOCK_ID_CB02_BY2 = 0x29,
+ DBG_BLOCK_ID_CB04_BY2 = 0x2a,
+ DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
+ DBG_BLOCK_ID_CB10_BY2 = 0x2c,
+ DBG_BLOCK_ID_CB12_BY2 = 0x2d,
+ DBG_BLOCK_ID_CB14_BY2 = 0x2e,
+ DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
+ DBG_BLOCK_ID_TCP0_BY2 = 0x30,
+ DBG_BLOCK_ID_TCP2_BY2 = 0x31,
+ DBG_BLOCK_ID_TCP4_BY2 = 0x32,
+ DBG_BLOCK_ID_TCP6_BY2 = 0x33,
+ DBG_BLOCK_ID_TCP8_BY2 = 0x34,
+ DBG_BLOCK_ID_TCP10_BY2 = 0x35,
+ DBG_BLOCK_ID_TCP12_BY2 = 0x36,
+ DBG_BLOCK_ID_TCP14_BY2 = 0x37,
+ DBG_BLOCK_ID_TCP16_BY2 = 0x38,
+ DBG_BLOCK_ID_TCP18_BY2 = 0x39,
+ DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
+ DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
+ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
+ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
+ DBG_BLOCK_ID_DB00_BY2 = 0x40,
+ DBG_BLOCK_ID_DB02_BY2 = 0x41,
+ DBG_BLOCK_ID_DB04_BY2 = 0x42,
+ DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
+ DBG_BLOCK_ID_DB10_BY2 = 0x44,
+ DBG_BLOCK_ID_DB12_BY2 = 0x45,
+ DBG_BLOCK_ID_DB14_BY2 = 0x46,
+ DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
+ DBG_BLOCK_ID_TCC0_BY2 = 0x48,
+ DBG_BLOCK_ID_TCC2_BY2 = 0x49,
+ DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
+ DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
+ DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
+ DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
+ DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
+ DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
+ DBG_BLOCK_ID_TA00_BY2 = 0x50,
+ DBG_BLOCK_ID_TA02_BY2 = 0x51,
+ DBG_BLOCK_ID_TA04_BY2 = 0x52,
+ DBG_BLOCK_ID_TA06_BY2 = 0x53,
+ DBG_BLOCK_ID_TA08_BY2 = 0x54,
+ DBG_BLOCK_ID_TA0A_BY2 = 0x55,
+ DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
+ DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
+ DBG_BLOCK_ID_TA10_BY2 = 0x58,
+ DBG_BLOCK_ID_TA12_BY2 = 0x59,
+ DBG_BLOCK_ID_TA14_BY2 = 0x5a,
+ DBG_BLOCK_ID_TA16_BY2 = 0x5b,
+ DBG_BLOCK_ID_TA18_BY2 = 0x5c,
+ DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
+ DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
+ DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
+ DBG_BLOCK_ID_TD00_BY2 = 0x60,
+ DBG_BLOCK_ID_TD02_BY2 = 0x61,
+ DBG_BLOCK_ID_TD04_BY2 = 0x62,
+ DBG_BLOCK_ID_TD06_BY2 = 0x63,
+ DBG_BLOCK_ID_TD08_BY2 = 0x64,
+ DBG_BLOCK_ID_TD0A_BY2 = 0x65,
+ DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
+ DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
+ DBG_BLOCK_ID_TD10_BY2 = 0x68,
+ DBG_BLOCK_ID_TD12_BY2 = 0x69,
+ DBG_BLOCK_ID_TD14_BY2 = 0x6a,
+ DBG_BLOCK_ID_TD16_BY2 = 0x6b,
+ DBG_BLOCK_ID_TD18_BY2 = 0x6c,
+ DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
+ DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
+ DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
+ DBG_BLOCK_ID_MCD0_BY2 = 0x70,
+ DBG_BLOCK_ID_MCD2_BY2 = 0x71,
+ DBG_BLOCK_ID_MCD4_BY2 = 0x72,
+ DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
+} DebugBlockId_BY2;
+typedef enum DebugBlockId_BY4 {
+ DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
+ DBG_BLOCK_ID_CG_BY4 = 0x1,
+ DBG_BLOCK_ID_CSC_BY4 = 0x2,
+ DBG_BLOCK_ID_SQ_BY4 = 0x3,
+ DBG_BLOCK_ID_DMA0_BY4 = 0x4,
+ DBG_BLOCK_ID_SPIS_BY4 = 0x5,
+ DBG_BLOCK_ID_CP0_BY4 = 0x6,
+ DBG_BLOCK_ID_UVDU_BY4 = 0x7,
+ DBG_BLOCK_ID_VGT0_BY4 = 0x8,
+ DBG_BLOCK_ID_SCT0_BY4 = 0x9,
+ DBG_BLOCK_ID_TCAA_BY4 = 0xa,
+ DBG_BLOCK_ID_MCC0_BY4 = 0xb,
+ DBG_BLOCK_ID_SX0_BY4 = 0xc,
+ DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
+ DBG_BLOCK_ID_PC0_BY4 = 0xe,
+ DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
+ DBG_BLOCK_ID_SCB0_BY4 = 0x10,
+ DBG_BLOCK_ID_SCF0_BY4 = 0x11,
+ DBG_BLOCK_ID_BCI0_BY4 = 0x12,
+ DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
+ DBG_BLOCK_ID_CB00_BY4 = 0x14,
+ DBG_BLOCK_ID_CB04_BY4 = 0x15,
+ DBG_BLOCK_ID_CB10_BY4 = 0x16,
+ DBG_BLOCK_ID_CB14_BY4 = 0x17,
+ DBG_BLOCK_ID_TCP0_BY4 = 0x18,
+ DBG_BLOCK_ID_TCP4_BY4 = 0x19,
+ DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
+ DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
+ DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
+ DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
+ DBG_BLOCK_ID_DB_BY4 = 0x20,
+ DBG_BLOCK_ID_DB04_BY4 = 0x21,
+ DBG_BLOCK_ID_DB10_BY4 = 0x22,
+ DBG_BLOCK_ID_DB14_BY4 = 0x23,
+ DBG_BLOCK_ID_TCC0_BY4 = 0x24,
+ DBG_BLOCK_ID_TCC4_BY4 = 0x25,
+ DBG_BLOCK_ID_SPS00_BY4 = 0x26,
+ DBG_BLOCK_ID_SPS11_BY4 = 0x27,
+ DBG_BLOCK_ID_TA00_BY4 = 0x28,
+ DBG_BLOCK_ID_TA04_BY4 = 0x29,
+ DBG_BLOCK_ID_TA08_BY4 = 0x2a,
+ DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
+ DBG_BLOCK_ID_TA10_BY4 = 0x2c,
+ DBG_BLOCK_ID_TA14_BY4 = 0x2d,
+ DBG_BLOCK_ID_TA18_BY4 = 0x2e,
+ DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
+ DBG_BLOCK_ID_TD00_BY4 = 0x30,
+ DBG_BLOCK_ID_TD04_BY4 = 0x31,
+ DBG_BLOCK_ID_TD08_BY4 = 0x32,
+ DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
+ DBG_BLOCK_ID_TD10_BY4 = 0x34,
+ DBG_BLOCK_ID_TD14_BY4 = 0x35,
+ DBG_BLOCK_ID_TD18_BY4 = 0x36,
+ DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
+ DBG_BLOCK_ID_MCD0_BY4 = 0x38,
+ DBG_BLOCK_ID_MCD4_BY4 = 0x39,
+} DebugBlockId_BY4;
+typedef enum DebugBlockId_BY8 {
+ DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
+ DBG_BLOCK_ID_CSC_BY8 = 0x1,
+ DBG_BLOCK_ID_DMA0_BY8 = 0x2,
+ DBG_BLOCK_ID_CP0_BY8 = 0x3,
+ DBG_BLOCK_ID_VGT0_BY8 = 0x4,
+ DBG_BLOCK_ID_TCAA_BY8 = 0x5,
+ DBG_BLOCK_ID_SX0_BY8 = 0x6,
+ DBG_BLOCK_ID_PC0_BY8 = 0x7,
+ DBG_BLOCK_ID_SCB0_BY8 = 0x8,
+ DBG_BLOCK_ID_BCI0_BY8 = 0x9,
+ DBG_BLOCK_ID_CB00_BY8 = 0xa,
+ DBG_BLOCK_ID_CB10_BY8 = 0xb,
+ DBG_BLOCK_ID_TCP0_BY8 = 0xc,
+ DBG_BLOCK_ID_TCP8_BY8 = 0xd,
+ DBG_BLOCK_ID_TCP16_BY8 = 0xe,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
+ DBG_BLOCK_ID_DB00_BY8 = 0x10,
+ DBG_BLOCK_ID_DB10_BY8 = 0x11,
+ DBG_BLOCK_ID_TCC0_BY8 = 0x12,
+ DBG_BLOCK_ID_SPS00_BY8 = 0x13,
+ DBG_BLOCK_ID_TA00_BY8 = 0x14,
+ DBG_BLOCK_ID_TA08_BY8 = 0x15,
+ DBG_BLOCK_ID_TA10_BY8 = 0x16,
+ DBG_BLOCK_ID_TA18_BY8 = 0x17,
+ DBG_BLOCK_ID_TD00_BY8 = 0x18,
+ DBG_BLOCK_ID_TD08_BY8 = 0x19,
+ DBG_BLOCK_ID_TD10_BY8 = 0x1a,
+ DBG_BLOCK_ID_TD18_BY8 = 0x1b,
+ DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
+} DebugBlockId_BY8;
+typedef enum DebugBlockId_BY16 {
+ DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
+ DBG_BLOCK_ID_DMA0_BY16 = 0x1,
+ DBG_BLOCK_ID_VGT0_BY16 = 0x2,
+ DBG_BLOCK_ID_SX0_BY16 = 0x3,
+ DBG_BLOCK_ID_SCB0_BY16 = 0x4,
+ DBG_BLOCK_ID_CB00_BY16 = 0x5,
+ DBG_BLOCK_ID_TCP0_BY16 = 0x6,
+ DBG_BLOCK_ID_TCP16_BY16 = 0x7,
+ DBG_BLOCK_ID_DB00_BY16 = 0x8,
+ DBG_BLOCK_ID_TCC0_BY16 = 0x9,
+ DBG_BLOCK_ID_TA00_BY16 = 0xa,
+ DBG_BLOCK_ID_TA10_BY16 = 0xb,
+ DBG_BLOCK_ID_TD00_BY16 = 0xc,
+ DBG_BLOCK_ID_TD10_BY16 = 0xd,
+ DBG_BLOCK_ID_MCD0_BY16 = 0xe,
+} DebugBlockId_BY16;
+typedef enum ColorTransform {
+ DCC_CT_AUTO = 0x0,
+ DCC_CT_NONE = 0x1,
+ ABGR_TO_A_BG_G_RB = 0x2,
+ BGRA_TO_BG_G_RB_A = 0x3,
+} ColorTransform;
+typedef enum CompareRef {
+ REF_NEVER = 0x0,
+ REF_LESS = 0x1,
+ REF_EQUAL = 0x2,
+ REF_LEQUAL = 0x3,
+ REF_GREATER = 0x4,
+ REF_NOTEQUAL = 0x5,
+ REF_GEQUAL = 0x6,
+ REF_ALWAYS = 0x7,
+} CompareRef;
+typedef enum ReadSize {
+ READ_256_BITS = 0x0,
+ READ_512_BITS = 0x1,
+} ReadSize;
+typedef enum DepthFormat {
+ DEPTH_INVALID = 0x0,
+ DEPTH_16 = 0x1,
+ DEPTH_X8_24 = 0x2,
+ DEPTH_8_24 = 0x3,
+ DEPTH_X8_24_FLOAT = 0x4,
+ DEPTH_8_24_FLOAT = 0x5,
+ DEPTH_32_FLOAT = 0x6,
+ DEPTH_X24_8_32_FLOAT = 0x7,
+} DepthFormat;
+typedef enum ZFormat {
+ Z_INVALID = 0x0,
+ Z_16 = 0x1,
+ Z_24 = 0x2,
+ Z_32_FLOAT = 0x3,
+} ZFormat;
+typedef enum StencilFormat {
+ STENCIL_INVALID = 0x0,
+ STENCIL_8 = 0x1,
+} StencilFormat;
+typedef enum CmaskMode {
+ CMASK_CLEAR_NONE = 0x0,
+ CMASK_CLEAR_ONE = 0x1,
+ CMASK_CLEAR_ALL = 0x2,
+ CMASK_ANY_EXPANDED = 0x3,
+ CMASK_ALPHA0_FRAG1 = 0x4,
+ CMASK_ALPHA0_FRAG2 = 0x5,
+ CMASK_ALPHA0_FRAG4 = 0x6,
+ CMASK_ALPHA0_FRAGS = 0x7,
+ CMASK_ALPHA1_FRAG1 = 0x8,
+ CMASK_ALPHA1_FRAG2 = 0x9,
+ CMASK_ALPHA1_FRAG4 = 0xa,
+ CMASK_ALPHA1_FRAGS = 0xb,
+ CMASK_ALPHAX_FRAG1 = 0xc,
+ CMASK_ALPHAX_FRAG2 = 0xd,
+ CMASK_ALPHAX_FRAG4 = 0xe,
+ CMASK_ALPHAX_FRAGS = 0xf,
+} CmaskMode;
+typedef enum QuadExportFormat {
+ EXPORT_UNUSED = 0x0,
+ EXPORT_32_R = 0x1,
+ EXPORT_32_GR = 0x2,
+ EXPORT_32_AR = 0x3,
+ EXPORT_FP16_ABGR = 0x4,
+ EXPORT_UNSIGNED16_ABGR = 0x5,
+ EXPORT_SIGNED16_ABGR = 0x6,
+ EXPORT_32_ABGR = 0x7,
+} QuadExportFormat;
+typedef enum QuadExportFormatOld {
+ EXPORT_4P_32BPC_ABGR = 0x0,
+ EXPORT_4P_16BPC_ABGR = 0x1,
+ EXPORT_4P_32BPC_GR = 0x2,
+ EXPORT_4P_32BPC_AR = 0x3,
+ EXPORT_2P_32BPC_ABGR = 0x4,
+ EXPORT_8P_32BPC_R = 0x5,
+} QuadExportFormatOld;
+typedef enum ColorFormat {
+ COLOR_INVALID = 0x0,
+ COLOR_8 = 0x1,
+ COLOR_16 = 0x2,
+ COLOR_8_8 = 0x3,
+ COLOR_32 = 0x4,
+ COLOR_16_16 = 0x5,
+ COLOR_10_11_11 = 0x6,
+ COLOR_11_11_10 = 0x7,
+ COLOR_10_10_10_2 = 0x8,
+ COLOR_2_10_10_10 = 0x9,
+ COLOR_8_8_8_8 = 0xa,
+ COLOR_32_32 = 0xb,
+ COLOR_16_16_16_16 = 0xc,
+ COLOR_RESERVED_13 = 0xd,
+ COLOR_32_32_32_32 = 0xe,
+ COLOR_RESERVED_15 = 0xf,
+ COLOR_5_6_5 = 0x10,
+ COLOR_1_5_5_5 = 0x11,
+ COLOR_5_5_5_1 = 0x12,
+ COLOR_4_4_4_4 = 0x13,
+ COLOR_8_24 = 0x14,
+ COLOR_24_8 = 0x15,
+ COLOR_X24_8_32_FLOAT = 0x16,
+ COLOR_RESERVED_23 = 0x17,
+} ColorFormat;
+typedef enum SurfaceFormat {
+ FMT_INVALID = 0x0,
+ FMT_8 = 0x1,
+ FMT_16 = 0x2,
+ FMT_8_8 = 0x3,
+ FMT_32 = 0x4,
+ FMT_16_16 = 0x5,
+ FMT_10_11_11 = 0x6,
+ FMT_11_11_10 = 0x7,
+ FMT_10_10_10_2 = 0x8,
+ FMT_2_10_10_10 = 0x9,
+ FMT_8_8_8_8 = 0xa,
+ FMT_32_32 = 0xb,
+ FMT_16_16_16_16 = 0xc,
+ FMT_32_32_32 = 0xd,
+ FMT_32_32_32_32 = 0xe,
+ FMT_RESERVED_4 = 0xf,
+ FMT_5_6_5 = 0x10,
+ FMT_1_5_5_5 = 0x11,
+ FMT_5_5_5_1 = 0x12,
+ FMT_4_4_4_4 = 0x13,
+ FMT_8_24 = 0x14,
+ FMT_24_8 = 0x15,
+ FMT_X24_8_32_FLOAT = 0x16,
+ FMT_RESERVED_33 = 0x17,
+ FMT_11_11_10_FLOAT = 0x18,
+ FMT_16_FLOAT = 0x19,
+ FMT_32_FLOAT = 0x1a,
+ FMT_16_16_FLOAT = 0x1b,
+ FMT_8_24_FLOAT = 0x1c,
+ FMT_24_8_FLOAT = 0x1d,
+ FMT_32_32_FLOAT = 0x1e,
+ FMT_10_11_11_FLOAT = 0x1f,
+ FMT_16_16_16_16_FLOAT = 0x20,
+ FMT_3_3_2 = 0x21,
+ FMT_6_5_5 = 0x22,
+ FMT_32_32_32_32_FLOAT = 0x23,
+ FMT_RESERVED_36 = 0x24,
+ FMT_1 = 0x25,
+ FMT_1_REVERSED = 0x26,
+ FMT_GB_GR = 0x27,
+ FMT_BG_RG = 0x28,
+ FMT_32_AS_8 = 0x29,
+ FMT_32_AS_8_8 = 0x2a,
+ FMT_5_9_9_9_SHAREDEXP = 0x2b,
+ FMT_8_8_8 = 0x2c,
+ FMT_16_16_16 = 0x2d,
+ FMT_16_16_16_FLOAT = 0x2e,
+ FMT_4_4 = 0x2f,
+ FMT_32_32_32_FLOAT = 0x30,
+ FMT_BC1 = 0x31,
+ FMT_BC2 = 0x32,
+ FMT_BC3 = 0x33,
+ FMT_BC4 = 0x34,
+ FMT_BC5 = 0x35,
+ FMT_BC6 = 0x36,
+ FMT_BC7 = 0x37,
+ FMT_32_AS_32_32_32_32 = 0x38,
+ FMT_APC3 = 0x39,
+ FMT_APC4 = 0x3a,
+ FMT_APC5 = 0x3b,
+ FMT_APC6 = 0x3c,
+ FMT_APC7 = 0x3d,
+ FMT_CTX1 = 0x3e,
+ FMT_RESERVED_63 = 0x3f,
+} SurfaceFormat;
+typedef enum BUF_DATA_FORMAT {
+ BUF_DATA_FORMAT_INVALID = 0x0,
+ BUF_DATA_FORMAT_8 = 0x1,
+ BUF_DATA_FORMAT_16 = 0x2,
+ BUF_DATA_FORMAT_8_8 = 0x3,
+ BUF_DATA_FORMAT_32 = 0x4,
+ BUF_DATA_FORMAT_16_16 = 0x5,
+ BUF_DATA_FORMAT_10_11_11 = 0x6,
+ BUF_DATA_FORMAT_11_11_10 = 0x7,
+ BUF_DATA_FORMAT_10_10_10_2 = 0x8,
+ BUF_DATA_FORMAT_2_10_10_10 = 0x9,
+ BUF_DATA_FORMAT_8_8_8_8 = 0xa,
+ BUF_DATA_FORMAT_32_32 = 0xb,
+ BUF_DATA_FORMAT_16_16_16_16 = 0xc,
+ BUF_DATA_FORMAT_32_32_32 = 0xd,
+ BUF_DATA_FORMAT_32_32_32_32 = 0xe,
+ BUF_DATA_FORMAT_RESERVED_15 = 0xf,
+} BUF_DATA_FORMAT;
+typedef enum IMG_DATA_FORMAT {
+ IMG_DATA_FORMAT_INVALID = 0x0,
+ IMG_DATA_FORMAT_8 = 0x1,
+ IMG_DATA_FORMAT_16 = 0x2,
+ IMG_DATA_FORMAT_8_8 = 0x3,
+ IMG_DATA_FORMAT_32 = 0x4,
+ IMG_DATA_FORMAT_16_16 = 0x5,
+ IMG_DATA_FORMAT_10_11_11 = 0x6,
+ IMG_DATA_FORMAT_11_11_10 = 0x7,
+ IMG_DATA_FORMAT_10_10_10_2 = 0x8,
+ IMG_DATA_FORMAT_2_10_10_10 = 0x9,
+ IMG_DATA_FORMAT_8_8_8_8 = 0xa,
+ IMG_DATA_FORMAT_32_32 = 0xb,
+ IMG_DATA_FORMAT_16_16_16_16 = 0xc,
+ IMG_DATA_FORMAT_32_32_32 = 0xd,
+ IMG_DATA_FORMAT_32_32_32_32 = 0xe,
+ IMG_DATA_FORMAT_RESERVED_15 = 0xf,
+ IMG_DATA_FORMAT_5_6_5 = 0x10,
+ IMG_DATA_FORMAT_1_5_5_5 = 0x11,
+ IMG_DATA_FORMAT_5_5_5_1 = 0x12,
+ IMG_DATA_FORMAT_4_4_4_4 = 0x13,
+ IMG_DATA_FORMAT_8_24 = 0x14,
+ IMG_DATA_FORMAT_24_8 = 0x15,
+ IMG_DATA_FORMAT_X24_8_32 = 0x16,
+ IMG_DATA_FORMAT_RESERVED_23 = 0x17,
+ IMG_DATA_FORMAT_RESERVED_24 = 0x18,
+ IMG_DATA_FORMAT_RESERVED_25 = 0x19,
+ IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
+ IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
+ IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
+ IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
+ IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
+ IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
+ IMG_DATA_FORMAT_GB_GR = 0x20,
+ IMG_DATA_FORMAT_BG_RG = 0x21,
+ IMG_DATA_FORMAT_5_9_9_9 = 0x22,
+ IMG_DATA_FORMAT_BC1 = 0x23,
+ IMG_DATA_FORMAT_BC2 = 0x24,
+ IMG_DATA_FORMAT_BC3 = 0x25,
+ IMG_DATA_FORMAT_BC4 = 0x26,
+ IMG_DATA_FORMAT_BC5 = 0x27,
+ IMG_DATA_FORMAT_BC6 = 0x28,
+ IMG_DATA_FORMAT_BC7 = 0x29,
+ IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
+ IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
+ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
+ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
+ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
+ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
+ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
+ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
+ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
+ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
+ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
+ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
+ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
+ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
+ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
+ IMG_DATA_FORMAT_4_4 = 0x39,
+ IMG_DATA_FORMAT_6_5_5 = 0x3a,
+ IMG_DATA_FORMAT_1 = 0x3b,
+ IMG_DATA_FORMAT_1_REVERSED = 0x3c,
+ IMG_DATA_FORMAT_32_AS_8 = 0x3d,
+ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
+ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
+} IMG_DATA_FORMAT;
+typedef enum BUF_NUM_FORMAT {
+ BUF_NUM_FORMAT_UNORM = 0x0,
+ BUF_NUM_FORMAT_SNORM = 0x1,
+ BUF_NUM_FORMAT_USCALED = 0x2,
+ BUF_NUM_FORMAT_SSCALED = 0x3,
+ BUF_NUM_FORMAT_UINT = 0x4,
+ BUF_NUM_FORMAT_SINT = 0x5,
+ BUF_NUM_FORMAT_RESERVED_6 = 0x6,
+ BUF_NUM_FORMAT_FLOAT = 0x7,
+} BUF_NUM_FORMAT;
+typedef enum IMG_NUM_FORMAT {
+ IMG_NUM_FORMAT_UNORM = 0x0,
+ IMG_NUM_FORMAT_SNORM = 0x1,
+ IMG_NUM_FORMAT_USCALED = 0x2,
+ IMG_NUM_FORMAT_SSCALED = 0x3,
+ IMG_NUM_FORMAT_UINT = 0x4,
+ IMG_NUM_FORMAT_SINT = 0x5,
+ IMG_NUM_FORMAT_RESERVED_6 = 0x6,
+ IMG_NUM_FORMAT_FLOAT = 0x7,
+ IMG_NUM_FORMAT_RESERVED_8 = 0x8,
+ IMG_NUM_FORMAT_SRGB = 0x9,
+ IMG_NUM_FORMAT_RESERVED_10 = 0xa,
+ IMG_NUM_FORMAT_RESERVED_11 = 0xb,
+ IMG_NUM_FORMAT_RESERVED_12 = 0xc,
+ IMG_NUM_FORMAT_RESERVED_13 = 0xd,
+ IMG_NUM_FORMAT_RESERVED_14 = 0xe,
+ IMG_NUM_FORMAT_RESERVED_15 = 0xf,
+} IMG_NUM_FORMAT;
+typedef enum TileType {
+ ARRAY_COLOR_TILE = 0x0,
+ ARRAY_DEPTH_TILE = 0x1,
+} TileType;
+typedef enum NonDispTilingOrder {
+ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
+ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
+} NonDispTilingOrder;
+typedef enum MicroTileMode {
+ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
+ ADDR_SURF_THIN_MICRO_TILING = 0x1,
+ ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
+ ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
+ ADDR_SURF_THICK_MICRO_TILING = 0x4,
+} MicroTileMode;
+typedef enum TileSplit {
+ ADDR_SURF_TILE_SPLIT_64B = 0x0,
+ ADDR_SURF_TILE_SPLIT_128B = 0x1,
+ ADDR_SURF_TILE_SPLIT_256B = 0x2,
+ ADDR_SURF_TILE_SPLIT_512B = 0x3,
+ ADDR_SURF_TILE_SPLIT_1KB = 0x4,
+ ADDR_SURF_TILE_SPLIT_2KB = 0x5,
+ ADDR_SURF_TILE_SPLIT_4KB = 0x6,
+} TileSplit;
+typedef enum SampleSplit {
+ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
+ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
+ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
+ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
+} SampleSplit;
+typedef enum PipeConfig {
+ ADDR_SURF_P2 = 0x0,
+ ADDR_SURF_P2_RESERVED0 = 0x1,
+ ADDR_SURF_P2_RESERVED1 = 0x2,
+ ADDR_SURF_P2_RESERVED2 = 0x3,
+ ADDR_SURF_P4_8x16 = 0x4,
+ ADDR_SURF_P4_16x16 = 0x5,
+ ADDR_SURF_P4_16x32 = 0x6,
+ ADDR_SURF_P4_32x32 = 0x7,
+ ADDR_SURF_P8_16x16_8x16 = 0x8,
+ ADDR_SURF_P8_16x32_8x16 = 0x9,
+ ADDR_SURF_P8_32x32_8x16 = 0xa,
+ ADDR_SURF_P8_16x32_16x16 = 0xb,
+ ADDR_SURF_P8_32x32_16x16 = 0xc,
+ ADDR_SURF_P8_32x32_16x32 = 0xd,
+ ADDR_SURF_P8_32x64_32x32 = 0xe,
+ ADDR_SURF_P8_RESERVED0 = 0xf,
+ ADDR_SURF_P16_32x32_8x16 = 0x10,
+ ADDR_SURF_P16_32x32_16x16 = 0x11,
+} PipeConfig;
+typedef enum NumBanks {
+ ADDR_SURF_2_BANK = 0x0,
+ ADDR_SURF_4_BANK = 0x1,
+ ADDR_SURF_8_BANK = 0x2,
+ ADDR_SURF_16_BANK = 0x3,
+} NumBanks;
+typedef enum BankWidth {
+ ADDR_SURF_BANK_WIDTH_1 = 0x0,
+ ADDR_SURF_BANK_WIDTH_2 = 0x1,
+ ADDR_SURF_BANK_WIDTH_4 = 0x2,
+ ADDR_SURF_BANK_WIDTH_8 = 0x3,
+} BankWidth;
+typedef enum BankHeight {
+ ADDR_SURF_BANK_HEIGHT_1 = 0x0,
+ ADDR_SURF_BANK_HEIGHT_2 = 0x1,
+ ADDR_SURF_BANK_HEIGHT_4 = 0x2,
+ ADDR_SURF_BANK_HEIGHT_8 = 0x3,
+} BankHeight;
+typedef enum BankWidthHeight {
+ ADDR_SURF_BANK_WH_1 = 0x0,
+ ADDR_SURF_BANK_WH_2 = 0x1,
+ ADDR_SURF_BANK_WH_4 = 0x2,
+ ADDR_SURF_BANK_WH_8 = 0x3,
+} BankWidthHeight;
+typedef enum MacroTileAspect {
+ ADDR_SURF_MACRO_ASPECT_1 = 0x0,
+ ADDR_SURF_MACRO_ASPECT_2 = 0x1,
+ ADDR_SURF_MACRO_ASPECT_4 = 0x2,
+ ADDR_SURF_MACRO_ASPECT_8 = 0x3,
+} MacroTileAspect;
+typedef enum GATCL1RequestType {
+ GATCL1_TYPE_NORMAL = 0x0,
+ GATCL1_TYPE_SHOOTDOWN = 0x1,
+ GATCL1_TYPE_BYPASS = 0x2,
+} GATCL1RequestType;
+typedef enum TCC_CACHE_POLICIES {
+ TCC_CACHE_POLICY_LRU = 0x0,
+ TCC_CACHE_POLICY_STREAM = 0x1,
+} TCC_CACHE_POLICIES;
+typedef enum MTYPE {
+ MTYPE_NC_NV = 0x0,
+ MTYPE_NC = 0x1,
+ MTYPE_CC = 0x2,
+ MTYPE_UC = 0x3,
+} MTYPE;
+typedef enum PERFMON_COUNTER_MODE {
+ PERFMON_COUNTER_MODE_ACCUM = 0x0,
+ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
+ PERFMON_COUNTER_MODE_MAX = 0x2,
+ PERFMON_COUNTER_MODE_DIRTY = 0x3,
+ PERFMON_COUNTER_MODE_SAMPLE = 0x4,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
+ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
+ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
+ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
+ PERFMON_COUNTER_MODE_RESERVED = 0xf,
+} PERFMON_COUNTER_MODE;
+typedef enum PERFMON_SPM_MODE {
+ PERFMON_SPM_MODE_OFF = 0x0,
+ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
+ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
+ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
+ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
+ PERFMON_SPM_MODE_RESERVED_5 = 0x5,
+ PERFMON_SPM_MODE_RESERVED_6 = 0x6,
+ PERFMON_SPM_MODE_RESERVED_7 = 0x7,
+ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
+ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
+ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
+} PERFMON_SPM_MODE;
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0x0,
+ ARRAY_TILED = 0x1,
+} SurfaceTiling;
+typedef enum SurfaceArray {
+ ARRAY_1D = 0x0,
+ ARRAY_2D = 0x1,
+ ARRAY_3D = 0x2,
+ ARRAY_3D_SLICE = 0x3,
+} SurfaceArray;
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0x0,
+ ARRAY_2D_COLOR = 0x1,
+ ARRAY_3D_SLICE_COLOR = 0x3,
+} ColorArray;
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0x0,
+ ARRAY_2D_DEPTH = 0x1,
+} DepthArray;
+typedef enum ENUM_NUM_SIMD_PER_CU {
+ NUM_SIMD_PER_CU = 0x4,
+} ENUM_NUM_SIMD_PER_CU;
+typedef enum MEM_PWR_FORCE_CTRL {
+ NO_FORCE_REQUEST = 0x0,
+ FORCE_LIGHT_SLEEP_REQUEST = 0x1,
+ FORCE_DEEP_SLEEP_REQUEST = 0x2,
+ FORCE_SHUT_DOWN_REQUEST = 0x3,
+} MEM_PWR_FORCE_CTRL;
+typedef enum MEM_PWR_FORCE_CTRL2 {
+ NO_FORCE_REQ = 0x0,
+ FORCE_LIGHT_SLEEP_REQ = 0x1,
+} MEM_PWR_FORCE_CTRL2;
+typedef enum MEM_PWR_DIS_CTRL {
+ ENABLE_MEM_PWR_CTRL = 0x0,
+ DISABLE_MEM_PWR_CTRL = 0x1,
+} MEM_PWR_DIS_CTRL;
+typedef enum MEM_PWR_SEL_CTRL {
+ DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
+ DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
+ DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
+} MEM_PWR_SEL_CTRL;
+typedef enum MEM_PWR_SEL_CTRL2 {
+ DYNAMIC_DEEP_SLEEP_EN = 0x0,
+ DYNAMIC_LIGHT_SLEEP_EN = 0x1,
+} MEM_PWR_SEL_CTRL2;
+
+#endif /* BIF_5_0_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h
new file mode 100644
index 000000000000..adc71b01f793
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h
@@ -0,0 +1,11494 @@
+/*
+ * BIF_5_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef BIF_5_0_SH_MASK_H
+#define BIF_5_0_SH_MASK_H
+
+#define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
+#define MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define MM_INDEX__MM_APER_MASK 0x80000000
+#define MM_INDEX__MM_APER__SHIFT 0x1f
+#define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
+#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define MM_DATA__MM_DATA_MASK 0xffffffff
+#define MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
+#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
+#define BIF_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x1
+#define BIF_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x1
+#define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x0
+#define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2
+#define BUS_CNTL__BIOS_ROM_DIS__SHIFT 0x1
+#define BUS_CNTL__PMI_IO_DIS_MASK 0x4
+#define BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
+#define BUS_CNTL__PMI_MEM_DIS_MASK 0x8
+#define BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
+#define BUS_CNTL__PMI_BM_DIS_MASK 0x10
+#define BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
+#define BUS_CNTL__PMI_INT_DIS_MASK 0x20
+#define BUS_CNTL__PMI_INT_DIS__SHIFT 0x5
+#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x40
+#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6
+#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x80
+#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
+#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100
+#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8
+#define BUS_CNTL__SET_AZ_TC_MASK 0x1c00
+#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa
+#define BUS_CNTL__SET_MC_TC_MASK 0xe000
+#define BUS_CNTL__SET_MC_TC__SHIFT 0xd
+#define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x10000
+#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
+#define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x20000
+#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11
+#define BUS_CNTL__RD_STALL_IO_WR_MASK 0x40000
+#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12
+#define CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x1
+#define CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0
+#define CONFIG_CNTL__VGA_DIS_MASK 0x2
+#define CONFIG_CNTL__VGA_DIS__SHIFT 0x1
+#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x4
+#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2
+#define CONFIG_CNTL__GRPH_ADRSEL_MASK 0x18
+#define CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3
+#define CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xffffffff
+#define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xffffffff
+#define CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define BIF_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x1
+#define BIF_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define BIF_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000
+#define BIF_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define CONFIG_F0_BASE__F0_BASE_MASK 0xffffffff
+#define CONFIG_F0_BASE__F0_BASE__SHIFT 0x0
+#define CONFIG_APER_SIZE__APER_SIZE_MASK 0xffffffff
+#define CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0
+#define CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0xfffff
+#define CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0
+#define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xffffffff
+#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0
+#define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xffffffff
+#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0
+#define BIF_RLC_INTR_CNTL__RLC_HVCMD_INTERRUPT_MASK 0x1
+#define BIF_RLC_INTR_CNTL__RLC_HVCMD_INTERRUPT__SHIFT 0x0
+#define BIF_RLC_INTR_CNTL__RLC_VM_IDLE_INTERRUPT_MASK 0x100
+#define BIF_RLC_INTR_CNTL__RLC_VM_IDLE_INTERRUPT__SHIFT 0x8
+#define BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x1
+#define BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x10000
+#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x1
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x2
+#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x10000
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x20000
+#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BX_RESET_EN__COR_RESET_EN_MASK 0x1
+#define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0
+#define BX_RESET_EN__REG_RESET_EN_MASK 0x2
+#define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1
+#define BX_RESET_EN__STY_RESET_EN_MASK 0x4
+#define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2
+#define BX_RESET_EN__FLR_TWICE_EN_MASK 0x100
+#define BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8
+#define BX_RESET_EN__FLR_TIMER_SEL_MASK 0x600
+#define BX_RESET_EN__FLR_TIMER_SEL__SHIFT 0x9
+#define BX_RESET_EN__DB_APER_RESET_EN_MASK 0x8000
+#define BX_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf
+#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x10000
+#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10
+#define BX_RESET_EN__PF_FLR_NEWHDL_EN_MASK 0x20000
+#define BX_RESET_EN__PF_FLR_NEWHDL_EN__SHIFT 0x11
+#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x7
+#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0
+#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x8
+#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x3
+#define HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define HW_DEBUG__HW_16_DEBUG_MASK 0x10000
+#define HW_DEBUG__HW_16_DEBUG__SHIFT 0x10
+#define HW_DEBUG__HW_17_DEBUG_MASK 0x20000
+#define HW_DEBUG__HW_17_DEBUG__SHIFT 0x11
+#define HW_DEBUG__HW_18_DEBUG_MASK 0x40000
+#define HW_DEBUG__HW_18_DEBUG__SHIFT 0x12
+#define HW_DEBUG__HW_19_DEBUG_MASK 0x80000
+#define HW_DEBUG__HW_19_DEBUG__SHIFT 0x13
+#define HW_DEBUG__HW_20_DEBUG_MASK 0x100000
+#define HW_DEBUG__HW_20_DEBUG__SHIFT 0x14
+#define HW_DEBUG__HW_21_DEBUG_MASK 0x200000
+#define HW_DEBUG__HW_21_DEBUG__SHIFT 0x15
+#define HW_DEBUG__HW_22_DEBUG_MASK 0x400000
+#define HW_DEBUG__HW_22_DEBUG__SHIFT 0x16
+#define HW_DEBUG__HW_23_DEBUG_MASK 0x800000
+#define HW_DEBUG__HW_23_DEBUG__SHIFT 0x17
+#define HW_DEBUG__HW_24_DEBUG_MASK 0x1000000
+#define HW_DEBUG__HW_24_DEBUG__SHIFT 0x18
+#define HW_DEBUG__HW_25_DEBUG_MASK 0x2000000
+#define HW_DEBUG__HW_25_DEBUG__SHIFT 0x19
+#define HW_DEBUG__HW_26_DEBUG_MASK 0x4000000
+#define HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a
+#define HW_DEBUG__HW_27_DEBUG_MASK 0x8000000
+#define HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b
+#define HW_DEBUG__HW_28_DEBUG_MASK 0x10000000
+#define HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c
+#define HW_DEBUG__HW_29_DEBUG_MASK 0x20000000
+#define HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d
+#define HW_DEBUG__HW_30_DEBUG_MASK 0x40000000
+#define HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e
+#define HW_DEBUG__HW_31_DEBUG_MASK 0x80000000
+#define HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f
+#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT_MASK 0x7f
+#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT__SHIFT 0x0
+#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT_MASK 0x3f0000
+#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT__SHIFT 0x10
+#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT_MASK 0x1f
+#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT__SHIFT 0x0
+#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT_MASK 0x1e0
+#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT__SHIFT 0x5
+#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT_MASK 0x7c00
+#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT__SHIFT 0xa
+#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT_MASK 0x8000
+#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT__SHIFT 0xf
+#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT_MASK 0x100000
+#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT__SHIFT 0x14
+#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT_MASK 0x7e000000
+#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT__SHIFT 0x19
+#define BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x1
+#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0
+#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x1
+#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
+#define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x2
+#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1
+#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x8
+#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3
+#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0xf0
+#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
+#define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x100
+#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8
+#define INTERRUPT_CNTL__GEN_GPIO_INT_EN_MASK 0x1e00
+#define INTERRUPT_CNTL__GEN_GPIO_INT_EN__SHIFT 0x9
+#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT_MASK 0x6000
+#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT__SHIFT 0xd
+#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x8000
+#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf
+#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xffffffff
+#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0
+#define BIF_DEBUG_CNTL__DEBUG_EN_MASK 0x1
+#define BIF_DEBUG_CNTL__DEBUG_EN__SHIFT 0x0
+#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x2
+#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN__SHIFT 0x1
+#define BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK 0x4
+#define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x2
+#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x8
+#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL__SHIFT 0x3
+#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1_MASK 0x10
+#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT 0x4
+#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2_MASK 0x20
+#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2__SHIFT 0x5
+#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN_MASK 0x40
+#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN__SHIFT 0x6
+#define BIF_DEBUG_CNTL__DEBUG_SWAP_MASK 0x80
+#define BIF_DEBUG_CNTL__DEBUG_SWAP__SHIFT 0x7
+#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1_MASK 0x1f00
+#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x8
+#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2_MASK 0x1f0000
+#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2__SHIFT 0x10
+#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP_MASK 0x1000000
+#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP__SHIFT 0x18
+#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL_MASK 0xc0000000
+#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL__SHIFT 0x1e
+#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1_MASK 0x3f
+#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1__SHIFT 0x0
+#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2_MASK 0x3f00
+#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT 0x8
+#define BIF_DEBUG_OUT__DEBUG_OUTPUT_MASK 0x1ffff
+#define BIF_DEBUG_OUT__DEBUG_OUTPUT__SHIFT 0x0
+#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x1
+#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x1
+#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x1
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x2
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x4
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x18
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x20
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x40
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x80
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x100
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x200
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x400
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x800
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x1000
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x2000
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd
+#define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER_MASK 0xff000000
+#define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER__SHIFT 0x18
+#define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER_MASK 0xffffffff
+#define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER__SHIFT 0x0
+#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffff
+#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0
+#define BIF_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000
+#define BIF_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f
+#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffff
+#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0
+#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x1
+#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0
+#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x2
+#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
+#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x4
+#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
+#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x8
+#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3
+#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x10
+#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4
+#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x20
+#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5
+#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x40
+#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6
+#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x80
+#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x7
+#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x100
+#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x8
+#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS_MASK 0x200
+#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9
+#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS_MASK 0x400
+#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa
+#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x800
+#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb
+#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x1000
+#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc
+#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x2000
+#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd
+#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x8000
+#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf
+#define BIF_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x10000
+#define BIF_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x10
+#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS_MASK 0x20000
+#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x11
+#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS_MASK 0x40000
+#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x12
+#define BIF_FEATURES_CONTROL_MISC__SOFT_PF_FLR_UR_CFG_EN_MASK 0x80000
+#define BIF_FEATURES_CONTROL_MISC__SOFT_PF_FLR_UR_CFG_EN__SHIFT 0x13
+#define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_UR_DIS_MASK 0x100000
+#define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_UR_DIS__SHIFT 0x14
+#define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_HDL_DIS_MASK 0x200000
+#define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_HDL_DIS__SHIFT 0x15
+#define BIF_FEATURES_CONTROL_MISC__FLR_NEWREQ_HDL_DIS_MASK 0x400000
+#define BIF_FEATURES_CONTROL_MISC__FLR_NEWREQ_HDL_DIS__SHIFT 0x16
+#define BIF_FEATURES_CONTROL_MISC__FLR_CRS_CFG_DIS_MASK 0x800000
+#define BIF_FEATURES_CONTROL_MISC__FLR_CRS_CFG_DIS__SHIFT 0x17
+#define BIF_FEATURES_CONTROL_MISC__DUMMY_TRANS_CPL_RET_DIS_MASK 0x1000000
+#define BIF_FEATURES_CONTROL_MISC__DUMMY_TRANS_CPL_RET_DIS__SHIFT 0x18
+#define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x1
+#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0
+#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x2
+#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1
+#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x4
+#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
+#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x8
+#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
+#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x10
+#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4
+#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x20
+#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x5
+#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x10000
+#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x1000000
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x2000000
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x4000000
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x8000000
+#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b
+#define BIF_SLVARB_MODE__SLVARB_MODE_MASK 0x3
+#define BIF_SLVARB_MODE__SLVARB_MODE__SHIFT 0x0
+#define BIF_CLK_CTRL__BIF_XSTCLK_READY_MASK 0x1
+#define BIF_CLK_CTRL__BIF_XSTCLK_READY__SHIFT 0x0
+#define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS_MASK 0x2
+#define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS__SHIFT 0x1
+#define BIF_FB_EN__FB_READ_EN_MASK 0x1
+#define BIF_FB_EN__FB_READ_EN__SHIFT 0x0
+#define BIF_FB_EN__FB_WRITE_EN_MASK 0x2
+#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
+#define BIF_BUSNUM_CNTL1__ID_MASK_MASK 0xff
+#define BIF_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0
+#define BIF_BUSNUM_LIST0__ID0_MASK 0xff
+#define BIF_BUSNUM_LIST0__ID0__SHIFT 0x0
+#define BIF_BUSNUM_LIST0__ID1_MASK 0xff00
+#define BIF_BUSNUM_LIST0__ID1__SHIFT 0x8
+#define BIF_BUSNUM_LIST0__ID2_MASK 0xff0000
+#define BIF_BUSNUM_LIST0__ID2__SHIFT 0x10
+#define BIF_BUSNUM_LIST0__ID3_MASK 0xff000000
+#define BIF_BUSNUM_LIST0__ID3__SHIFT 0x18
+#define BIF_BUSNUM_LIST1__ID4_MASK 0xff
+#define BIF_BUSNUM_LIST1__ID4__SHIFT 0x0
+#define BIF_BUSNUM_LIST1__ID5_MASK 0xff00
+#define BIF_BUSNUM_LIST1__ID5__SHIFT 0x8
+#define BIF_BUSNUM_LIST1__ID6_MASK 0xff0000
+#define BIF_BUSNUM_LIST1__ID6__SHIFT 0x10
+#define BIF_BUSNUM_LIST1__ID7_MASK 0xff000000
+#define BIF_BUSNUM_LIST1__ID7__SHIFT 0x18
+#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0xff
+#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0
+#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x100
+#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8
+#define BIF_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x10000
+#define BIF_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10
+#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x20000
+#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11
+#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x3f
+#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0
+#define BIF_PERFMON_CNTL__PERFCOUNTER_EN_MASK 0x1
+#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x0
+#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK 0x2
+#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x1
+#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1_MASK 0x4
+#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2
+#define BIF_PERFMON_CNTL__PERF_SEL0_MASK 0x1f00
+#define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x8
+#define BIF_PERFMON_CNTL__PERF_SEL1_MASK 0x3e000
+#define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0xd
+#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff
+#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0
+#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff
+#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0
+#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL_MASK 0xe
+#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL__SHIFT 0x1
+#define GPU_HDP_FLUSH_REQ__CP0_MASK 0x1
+#define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define GPU_HDP_FLUSH_REQ__CP1_MASK 0x2
+#define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define GPU_HDP_FLUSH_REQ__CP2_MASK 0x4
+#define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define GPU_HDP_FLUSH_REQ__CP3_MASK 0x8
+#define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define GPU_HDP_FLUSH_REQ__CP4_MASK 0x10
+#define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define GPU_HDP_FLUSH_REQ__CP5_MASK 0x20
+#define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define GPU_HDP_FLUSH_REQ__CP6_MASK 0x40
+#define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define GPU_HDP_FLUSH_REQ__CP7_MASK 0x80
+#define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define GPU_HDP_FLUSH_REQ__CP8_MASK 0x100
+#define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define GPU_HDP_FLUSH_REQ__CP9_MASK 0x200
+#define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x400
+#define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x800
+#define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define GPU_HDP_FLUSH_DONE__CP0_MASK 0x1
+#define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define GPU_HDP_FLUSH_DONE__CP1_MASK 0x2
+#define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define GPU_HDP_FLUSH_DONE__CP2_MASK 0x4
+#define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define GPU_HDP_FLUSH_DONE__CP3_MASK 0x8
+#define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define GPU_HDP_FLUSH_DONE__CP4_MASK 0x10
+#define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define GPU_HDP_FLUSH_DONE__CP5_MASK 0x20
+#define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define GPU_HDP_FLUSH_DONE__CP6_MASK 0x40
+#define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define GPU_HDP_FLUSH_DONE__CP7_MASK 0x80
+#define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define GPU_HDP_FLUSH_DONE__CP8_MASK 0x100
+#define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define GPU_HDP_FLUSH_DONE__CP9_MASK 0x200
+#define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x400
+#define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x800
+#define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR_MASK 0x1
+#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR__SHIFT 0x0
+#define SLAVE_HANG_ERROR__HDP_HANG_ERROR_MASK 0x2
+#define SLAVE_HANG_ERROR__HDP_HANG_ERROR__SHIFT 0x1
+#define SLAVE_HANG_ERROR__VGA_HANG_ERROR_MASK 0x4
+#define SLAVE_HANG_ERROR__VGA_HANG_ERROR__SHIFT 0x2
+#define SLAVE_HANG_ERROR__ROM_HANG_ERROR_MASK 0x8
+#define SLAVE_HANG_ERROR__ROM_HANG_ERROR__SHIFT 0x3
+#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR_MASK 0x10
+#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR__SHIFT 0x4
+#define SLAVE_HANG_ERROR__CEC_HANG_ERROR_MASK 0x20
+#define SLAVE_HANG_ERROR__CEC_HANG_ERROR__SHIFT 0x5
+#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR_MASK 0x80
+#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR__SHIFT 0x7
+#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR_MASK 0x100
+#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR__SHIFT 0x8
+#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR_MASK 0x200
+#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR__SHIFT 0x9
+#define CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x1
+#define CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0
+#define HOST_BUSNUM__HOST_ID_MASK 0xffff
+#define HOST_BUSNUM__HOST_ID__SHIFT 0x0
+#define PEER_REG_RANGE0__START_ADDR_MASK 0xffff
+#define PEER_REG_RANGE0__START_ADDR__SHIFT 0x0
+#define PEER_REG_RANGE0__END_ADDR_MASK 0xffff0000
+#define PEER_REG_RANGE0__END_ADDR__SHIFT 0x10
+#define PEER_REG_RANGE1__START_ADDR_MASK 0xffff
+#define PEER_REG_RANGE1__START_ADDR__SHIFT 0x0
+#define PEER_REG_RANGE1__END_ADDR_MASK 0xffff0000
+#define PEER_REG_RANGE1__END_ADDR__SHIFT 0x10
+#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0xfffff
+#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0
+#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0xfffff
+#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0
+#define PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000
+#define PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f
+#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0xfffff
+#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0
+#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0xfffff
+#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0
+#define PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000
+#define PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f
+#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0xfffff
+#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0
+#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0xfffff
+#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0
+#define PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000
+#define PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f
+#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0xfffff
+#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0
+#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0xfffff
+#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0
+#define PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000
+#define PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f
+#define DBG_SMB_BYPASS_SRBM_ACCESS__DBG_SMB_BYPASS_SRBM_EN_MASK 0x1
+#define DBG_SMB_BYPASS_SRBM_ACCESS__DBG_SMB_BYPASS_SRBM_EN__SHIFT 0x0
+#define BIF_MST_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0xffffffff
+#define BIF_MST_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_SLV_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0xffffffff
+#define BIF_SLV_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x0
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0xff
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0xff00
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0xff0000
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xff000000
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0xff
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0xff00
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0xff0000
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xff000000
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18
+#define BACO_CNTL__BACO_EN_MASK 0x1
+#define BACO_CNTL__BACO_EN__SHIFT 0x0
+#define BACO_CNTL__BACO_BCLK_OFF_MASK 0x2
+#define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x1
+#define BACO_CNTL__BACO_ISO_DIS_MASK 0x4
+#define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x2
+#define BACO_CNTL__BACO_POWER_OFF_MASK 0x8
+#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3
+#define BACO_CNTL__BACO_RESET_EN_MASK 0x10
+#define BACO_CNTL__BACO_RESET_EN__SHIFT 0x4
+#define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x20
+#define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x5
+#define BACO_CNTL__BACO_MODE_MASK 0x40
+#define BACO_CNTL__BACO_MODE__SHIFT 0x6
+#define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x80
+#define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x7
+#define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x100
+#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x8
+#define BACO_CNTL__PWRGOOD_BF_MASK 0x200
+#define BACO_CNTL__PWRGOOD_BF__SHIFT 0x9
+#define BACO_CNTL__PWRGOOD_GPIO_MASK 0x400
+#define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0xa
+#define BACO_CNTL__PWRGOOD_MEM_MASK 0x800
+#define BACO_CNTL__PWRGOOD_MEM__SHIFT 0xb
+#define BACO_CNTL__PWRGOOD_DVO_MASK 0x1000
+#define BACO_CNTL__PWRGOOD_DVO__SHIFT 0xc
+#define BACO_CNTL__PWRGOOD_IDSC_MASK 0x2000
+#define BACO_CNTL__PWRGOOD_IDSC__SHIFT 0xd
+#define BACO_CNTL__BACO_POWER_OFF_DRAM_MASK 0x10000
+#define BACO_CNTL__BACO_POWER_OFF_DRAM__SHIFT 0x10
+#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL_MASK 0x20000
+#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL__SHIFT 0x11
+#define BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK 0x40000
+#define BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT 0x12
+#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK_MASK 0x1
+#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK__SHIFT 0x0
+#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK 0x2
+#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK__SHIFT 0x1
+#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x1
+#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0
+#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG_MASK 0x1
+#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG__SHIFT 0x0
+#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG_MASK 0x1
+#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG__SHIFT 0x0
+#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x1
+#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0
+#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x2
+#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1
+#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL_MASK 0xc
+#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2
+#define BACO_CNTL_MISC__BACO_REFCLK_SEL_MASK 0x10
+#define BACO_CNTL_MISC__BACO_REFCLK_SEL__SHIFT 0x4
+#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK 0x1
+#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK 0x1
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x2
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK 0x4
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK 0x8
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK 0x10
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK 0x20
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5
+#define BIF_SMU_INDEX__BIF_SMU_INDEX_MASK 0x7fffc
+#define BIF_SMU_INDEX__BIF_SMU_INDEX__SHIFT 0x2
+#define BIF_SMU_DATA__BIF_SMU_DATA_MASK 0x7fffc
+#define BIF_SMU_DATA__BIF_SMU_DATA__SHIFT 0x2
+#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK 0xffc
+#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2
+#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK 0x80000000
+#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f
+#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK 0xffc
+#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2
+#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK 0xffc
+#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2
+#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK 0x80000000
+#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f
+#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK 0xffc
+#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2
+#define IMPCTL_RESET__IMP_SW_RESET_MASK 0x1
+#define IMPCTL_RESET__IMP_SW_RESET__SHIFT 0x0
+#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR_MASK 0x1
+#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR__SHIFT 0x0
+#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR_MASK 0x2
+#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR__SHIFT 0x1
+#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR_MASK 0x4
+#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR__SHIFT 0x2
+#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR_MASK 0x8
+#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR__SHIFT 0x3
+#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR_MASK 0x10
+#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR__SHIFT 0x4
+#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR_MASK 0x20
+#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR__SHIFT 0x5
+#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND_MASK 0x40
+#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND__SHIFT 0x6
+#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND_MASK 0x80
+#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND__SHIFT 0x7
+#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR_MASK 0x100
+#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR__SHIFT 0x8
+#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR_MASK 0x200
+#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR__SHIFT 0x9
+#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR_MASK 0x400
+#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR__SHIFT 0xa
+#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2_MASK 0x800
+#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2__SHIFT 0xb
+#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR_MASK 0x1000
+#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR__SHIFT 0xc
+#define GARLIC_FLUSH_CNTL__HOST_DOORBELL_MASK 0x2000
+#define GARLIC_FLUSH_CNTL__HOST_DOORBELL__SHIFT 0xd
+#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL_MASK 0x4000
+#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL__SHIFT 0xe
+#define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND_MASK 0x8000
+#define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND__SHIFT 0xf
+#define GARLIC_FLUSH_CNTL__DISPLAY_MASK 0x10000
+#define GARLIC_FLUSH_CNTL__DISPLAY__SHIFT 0x10
+#define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR_MASK 0x20000
+#define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR__SHIFT 0x11
+#define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR_MASK 0x40000
+#define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR__SHIFT 0x12
+#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE_MASK 0x40000000
+#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE__SHIFT 0x1e
+#define GARLIC_FLUSH_CNTL__DISABLE_ALL_MASK 0x80000000
+#define GARLIC_FLUSH_CNTL__DISABLE_ALL__SHIFT 0x1f
+#define GARLIC_FLUSH_ADDR_START_0__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_0__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_0__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_0__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_0__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_0__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_START_1__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_1__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_1__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_1__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_1__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_1__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_START_2__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_2__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_2__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_2__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_2__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_2__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_START_3__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_3__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_3__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_3__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_3__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_3__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_START_4__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_4__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_4__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_4__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_4__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_4__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_START_5__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_5__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_5__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_5__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_5__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_5__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_START_6__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_6__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_6__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_6__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_6__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_6__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_START_7__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_7__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_7__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_7__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_7__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_7__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_0__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_0__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_1__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_1__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_2__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_2__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_3__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_3__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_4__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_4__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_5__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_5__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_6__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_6__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_7__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_7__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_REQ__FLUSH_REQ_MASK 0x1
+#define GARLIC_FLUSH_REQ__FLUSH_REQ__SHIFT 0x0
+#define GPU_GARLIC_FLUSH_REQ__CP0_MASK 0x1
+#define GPU_GARLIC_FLUSH_REQ__CP0__SHIFT 0x0
+#define GPU_GARLIC_FLUSH_REQ__CP1_MASK 0x2
+#define GPU_GARLIC_FLUSH_REQ__CP1__SHIFT 0x1
+#define GPU_GARLIC_FLUSH_REQ__CP2_MASK 0x4
+#define GPU_GARLIC_FLUSH_REQ__CP2__SHIFT 0x2
+#define GPU_GARLIC_FLUSH_REQ__CP3_MASK 0x8
+#define GPU_GARLIC_FLUSH_REQ__CP3__SHIFT 0x3
+#define GPU_GARLIC_FLUSH_REQ__CP4_MASK 0x10
+#define GPU_GARLIC_FLUSH_REQ__CP4__SHIFT 0x4
+#define GPU_GARLIC_FLUSH_REQ__CP5_MASK 0x20
+#define GPU_GARLIC_FLUSH_REQ__CP5__SHIFT 0x5
+#define GPU_GARLIC_FLUSH_REQ__CP6_MASK 0x40
+#define GPU_GARLIC_FLUSH_REQ__CP6__SHIFT 0x6
+#define GPU_GARLIC_FLUSH_REQ__CP7_MASK 0x80
+#define GPU_GARLIC_FLUSH_REQ__CP7__SHIFT 0x7
+#define GPU_GARLIC_FLUSH_REQ__CP8_MASK 0x100
+#define GPU_GARLIC_FLUSH_REQ__CP8__SHIFT 0x8
+#define GPU_GARLIC_FLUSH_REQ__CP9_MASK 0x200
+#define GPU_GARLIC_FLUSH_REQ__CP9__SHIFT 0x9
+#define GPU_GARLIC_FLUSH_REQ__SDMA0_MASK 0x400
+#define GPU_GARLIC_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define GPU_GARLIC_FLUSH_REQ__SDMA1_MASK 0x800
+#define GPU_GARLIC_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define GPU_GARLIC_FLUSH_REQ__SDMA2_MASK 0x1000
+#define GPU_GARLIC_FLUSH_REQ__SDMA2__SHIFT 0xc
+#define GPU_GARLIC_FLUSH_REQ__SDMA3_MASK 0x2000
+#define GPU_GARLIC_FLUSH_REQ__SDMA3__SHIFT 0xd
+#define GPU_GARLIC_FLUSH_DONE__CP0_MASK 0x1
+#define GPU_GARLIC_FLUSH_DONE__CP0__SHIFT 0x0
+#define GPU_GARLIC_FLUSH_DONE__CP1_MASK 0x2
+#define GPU_GARLIC_FLUSH_DONE__CP1__SHIFT 0x1
+#define GPU_GARLIC_FLUSH_DONE__CP2_MASK 0x4
+#define GPU_GARLIC_FLUSH_DONE__CP2__SHIFT 0x2
+#define GPU_GARLIC_FLUSH_DONE__CP3_MASK 0x8
+#define GPU_GARLIC_FLUSH_DONE__CP3__SHIFT 0x3
+#define GPU_GARLIC_FLUSH_DONE__CP4_MASK 0x10
+#define GPU_GARLIC_FLUSH_DONE__CP4__SHIFT 0x4
+#define GPU_GARLIC_FLUSH_DONE__CP5_MASK 0x20
+#define GPU_GARLIC_FLUSH_DONE__CP5__SHIFT 0x5
+#define GPU_GARLIC_FLUSH_DONE__CP6_MASK 0x40
+#define GPU_GARLIC_FLUSH_DONE__CP6__SHIFT 0x6
+#define GPU_GARLIC_FLUSH_DONE__CP7_MASK 0x80
+#define GPU_GARLIC_FLUSH_DONE__CP7__SHIFT 0x7
+#define GPU_GARLIC_FLUSH_DONE__CP8_MASK 0x100
+#define GPU_GARLIC_FLUSH_DONE__CP8__SHIFT 0x8
+#define GPU_GARLIC_FLUSH_DONE__CP9_MASK 0x200
+#define GPU_GARLIC_FLUSH_DONE__CP9__SHIFT 0x9
+#define GPU_GARLIC_FLUSH_DONE__SDMA0_MASK 0x400
+#define GPU_GARLIC_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define GPU_GARLIC_FLUSH_DONE__SDMA1_MASK 0x800
+#define GPU_GARLIC_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define GPU_GARLIC_FLUSH_DONE__SDMA2_MASK 0x1000
+#define GPU_GARLIC_FLUSH_DONE__SDMA2__SHIFT 0xc
+#define GPU_GARLIC_FLUSH_DONE__SDMA3_MASK 0x2000
+#define GPU_GARLIC_FLUSH_DONE__SDMA3__SHIFT 0xd
+#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x7fffc
+#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x7fffc
+#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xffffffff
+#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0
+#define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xffffffff
+#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0
+#define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xffffffff
+#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0
+#define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xffffffff
+#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0
+#define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xffffffff
+#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0
+#define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xffffffff
+#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0
+#define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xffffffff
+#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0
+#define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xffffffff
+#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0
+#define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xffffffff
+#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0
+#define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xffffffff
+#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0
+#define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xffffffff
+#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0
+#define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xffffffff
+#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0
+#define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xffffffff
+#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0
+#define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xffffffff
+#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0
+#define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xffffffff
+#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0
+#define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xffffffff
+#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0
+#define BIF_RB_CNTL__RB_ENABLE_MASK 0x1
+#define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define BIF_RB_CNTL__RB_SIZE_MASK 0x3e
+#define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100
+#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
+#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00
+#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
+#define BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x20000
+#define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11
+#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
+#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define BIF_RB_BASE__ADDR_MASK 0xffffffff
+#define BIF_RB_BASE__ADDR__SHIFT 0x0
+#define BIF_RB_RPTR__OFFSET_MASK 0x3fffc
+#define BIF_RB_RPTR__OFFSET__SHIFT 0x2
+#define BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x1
+#define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0
+#define BIF_RB_WPTR__OFFSET_MASK 0x3fffc
+#define BIF_RB_WPTR__OFFSET__SHIFT 0x2
+#define BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0xff
+#define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define MAILBOX_INDEX__MAILBOX_INDEX_MASK 0xf
+#define MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0
+#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xffffffff
+#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xffffffff
+#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xffffffff
+#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xffffffff
+#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xffffffff
+#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xffffffff
+#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xffffffff
+#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xffffffff
+#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x1
+#define MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x2
+#define MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x100
+#define MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x200
+#define MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x1
+#define MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x2
+#define MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_VF_MASK 0xffff
+#define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_VF__SHIFT 0x0
+#define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_SOFTPF_MASK 0x80000000
+#define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_SOFTPF__SHIFT 0x1f
+#define VM_INIT_STATUS__VM_INIT_STATUS_MASK 0x1
+#define VM_INIT_STATUS__VM_INIT_STATUS__SHIFT 0x0
+#define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION_MASK 0xffffffff
+#define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__SHIFT 0x0
+#define BIF_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS_MASK 0xffffffff
+#define BIF_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS__SHIFT 0x0
+#define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_AVAILABLE_MASK 0xffff
+#define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_CONSUMED_MASK 0xffff0000
+#define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_CONSUMED__SHIFT 0x10
+#define BIF_GPUIOV_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY_MASK 0xffffffff
+#define BIF_GPUIOV_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY__SHIFT 0x0
+#define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER_MASK 0xffff
+#define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER__SHIFT 0x0
+#define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER_MASK 0xffff0000
+#define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER__SHIFT 0x10
+#define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER_MASK 0xffff
+#define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER__SHIFT 0x0
+#define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER_MASK 0xffff0000
+#define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER__SHIFT 0x10
+#define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER_MASK 0xffff
+#define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER__SHIFT 0x0
+#define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER_MASK 0xffff0000
+#define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER__SHIFT 0x10
+#define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER_MASK 0xffff
+#define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER__SHIFT 0x0
+#define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER_MASK 0xffff0000
+#define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER__SHIFT 0x10
+#define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER_MASK 0xffff
+#define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER__SHIFT 0x0
+#define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER_MASK 0xffff0000
+#define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER__SHIFT 0x10
+#define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER_MASK 0xffff
+#define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER__SHIFT 0x0
+#define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER_MASK 0xffff0000
+#define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER__SHIFT 0x10
+#define BIF_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY_MASK 0xffffffff
+#define BIF_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY__SHIFT 0x0
+#define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER_MASK 0xffff
+#define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER__SHIFT 0x0
+#define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER_MASK 0xffff0000
+#define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER__SHIFT 0x10
+#define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER_MASK 0xffff
+#define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER__SHIFT 0x0
+#define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER_MASK 0xffff0000
+#define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER__SHIFT 0x10
+#define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER_MASK 0xffff
+#define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER__SHIFT 0x0
+#define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER_MASK 0xffff0000
+#define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER__SHIFT 0x10
+#define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER_MASK 0xffff
+#define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER__SHIFT 0x0
+#define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER_MASK 0xffff0000
+#define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER__SHIFT 0x10
+#define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER_MASK 0xffff
+#define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER__SHIFT 0x0
+#define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER_MASK 0xffff0000
+#define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER__SHIFT 0x10
+#define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER_MASK 0xffff
+#define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER__SHIFT 0x0
+#define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER_MASK 0xffff0000
+#define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER__SHIFT 0x10
+#define VENDOR_ID__VENDOR_ID_MASK 0xffff
+#define VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define DEVICE_ID__DEVICE_ID_MASK 0xffff
+#define DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define COMMAND__IO_ACCESS_EN_MASK 0x1
+#define COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define COMMAND__MEM_ACCESS_EN_MASK 0x2
+#define COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define COMMAND__BUS_MASTER_EN_MASK 0x4
+#define COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
+#define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
+#define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define COMMAND__PAL_SNOOP_EN_MASK 0x20
+#define COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
+#define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define COMMAND__AD_STEPPING_MASK 0x80
+#define COMMAND__AD_STEPPING__SHIFT 0x7
+#define COMMAND__SERR_EN_MASK 0x100
+#define COMMAND__SERR_EN__SHIFT 0x8
+#define COMMAND__FAST_B2B_EN_MASK 0x200
+#define COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define COMMAND__INT_DIS_MASK 0x400
+#define COMMAND__INT_DIS__SHIFT 0xa
+#define STATUS__INT_STATUS_MASK 0x8
+#define STATUS__INT_STATUS__SHIFT 0x3
+#define STATUS__CAP_LIST_MASK 0x10
+#define STATUS__CAP_LIST__SHIFT 0x4
+#define STATUS__PCI_66_EN_MASK 0x20
+#define STATUS__PCI_66_EN__SHIFT 0x5
+#define STATUS__FAST_BACK_CAPABLE_MASK 0x80
+#define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x100
+#define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define STATUS__DEVSEL_TIMING_MASK 0x600
+#define STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define STATUS__SIGNAL_TARGET_ABORT_MASK 0x800
+#define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000
+#define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000
+#define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000
+#define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define STATUS__PARITY_ERROR_DETECTED_MASK 0x8000
+#define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define REVISION_ID__MINOR_REV_ID_MASK 0xf
+#define REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define REVISION_ID__MAJOR_REV_ID_MASK 0xf0
+#define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define PROG_INTERFACE__PROG_INTERFACE_MASK 0xff
+#define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define SUB_CLASS__SUB_CLASS_MASK 0xff
+#define SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BASE_CLASS__BASE_CLASS_MASK 0xff
+#define BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
+#define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define LATENCY__LATENCY_TIMER_MASK 0xff
+#define LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define HEADER__HEADER_TYPE_MASK 0x7f
+#define HEADER__HEADER_TYPE__SHIFT 0x0
+#define HEADER__DEVICE_TYPE_MASK 0x80
+#define HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIST__BIST_COMP_MASK 0xf
+#define BIST__BIST_COMP__SHIFT 0x0
+#define BIST__BIST_STRT_MASK 0x40
+#define BIST__BIST_STRT__SHIFT 0x6
+#define BIST__BIST_CAP_MASK 0x80
+#define BIST__BIST_CAP__SHIFT 0x7
+#define BASE_ADDR_1__BASE_ADDR_MASK 0xffffffff
+#define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BASE_ADDR_2__BASE_ADDR_MASK 0xffffffff
+#define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BASE_ADDR_3__BASE_ADDR_MASK 0xffffffff
+#define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BASE_ADDR_4__BASE_ADDR_MASK 0xffffffff
+#define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BASE_ADDR_5__BASE_ADDR_MASK 0xffffffff
+#define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BASE_ADDR_6__BASE_ADDR_MASK 0xffffffff
+#define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define ROM_BASE_ADDR__BASE_ADDR_MASK 0xffffffff
+#define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define CAP_PTR__CAP_PTR_MASK 0xff
+#define CAP_PTR__CAP_PTR__SHIFT 0x0
+#define INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
+#define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff
+#define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0xffff
+#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define ADAPTER_ID__SUBSYSTEM_ID_MASK 0xffff0000
+#define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define MIN_GRANT__MIN_GNT_MASK 0xff
+#define MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define MAX_LATENCY__MAX_LAT_MASK 0xff
+#define MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define VENDOR_CAP_LIST__CAP_ID_MASK 0xff
+#define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define VENDOR_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define VENDOR_CAP_LIST__LENGTH_MASK 0xff0000
+#define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0xffff
+#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xffff0000
+#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define PMI_CAP_LIST__CAP_ID_MASK 0xff
+#define PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PMI_CAP__VERSION_MASK 0x7
+#define PMI_CAP__VERSION__SHIFT 0x0
+#define PMI_CAP__PME_CLOCK_MASK 0x8
+#define PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x20
+#define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define PMI_CAP__AUX_CURRENT_MASK 0x1c0
+#define PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define PMI_CAP__D1_SUPPORT_MASK 0x200
+#define PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define PMI_CAP__D2_SUPPORT_MASK 0x400
+#define PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define PMI_CAP__PME_SUPPORT_MASK 0xf800
+#define PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
+#define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
+#define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define PMI_STATUS_CNTL__PME_EN_MASK 0x100
+#define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
+#define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
+#define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
+#define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
+#define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
+#define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
+#define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define PCIE_CAP_LIST__CAP_ID_MASK 0xff
+#define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PCIE_CAP__VERSION_MASK 0xf
+#define PCIE_CAP__VERSION__SHIFT 0x0
+#define PCIE_CAP__DEVICE_TYPE_MASK 0xf0
+#define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x100
+#define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e00
+#define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
+#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
+#define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define DEVICE_CAP__EXTENDED_TAG_MASK 0x20
+#define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
+#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
+#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
+#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
+#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
+#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
+#define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
+#define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
+#define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
+#define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
+#define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
+#define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
+#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
+#define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
+#define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
+#define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
+#define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
+#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define DEVICE_CNTL__INITIATE_FLR_MASK 0x8000
+#define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define DEVICE_STATUS__CORR_ERR_MASK 0x1
+#define DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define DEVICE_STATUS__NON_FATAL_ERR_MASK 0x2
+#define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define DEVICE_STATUS__FATAL_ERR_MASK 0x4
+#define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define DEVICE_STATUS__USR_DETECTED_MASK 0x8
+#define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define DEVICE_STATUS__AUX_PWR_MASK 0x10
+#define DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x20
+#define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define LINK_CAP__LINK_SPEED_MASK 0xf
+#define LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define LINK_CAP__LINK_WIDTH_MASK 0x3f0
+#define LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define LINK_CAP__PM_SUPPORT_MASK 0xc00
+#define LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
+#define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
+#define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
+#define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
+#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
+#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
+#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
+#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define LINK_CAP__PORT_NUMBER_MASK 0xff000000
+#define LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define LINK_CNTL__PM_CONTROL_MASK 0x3
+#define LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
+#define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define LINK_CNTL__LINK_DIS_MASK 0x10
+#define LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define LINK_CNTL__RETRAIN_LINK_MASK 0x20
+#define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
+#define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define LINK_CNTL__EXTENDED_SYNC_MASK 0x80
+#define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
+#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
+#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
+#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
+#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf
+#define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f0
+#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define LINK_STATUS__LINK_TRAINING_MASK 0x800
+#define LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000
+#define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define LINK_STATUS__DL_ACTIVE_MASK 0x2000
+#define LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000
+#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000
+#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
+#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
+#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
+#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
+#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
+#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
+#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
+#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
+#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
+#define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
+#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
+#define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
+#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
+#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
+#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
+#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
+#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
+#define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
+#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
+#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
+#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
+#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define DEVICE_CNTL2__LTR_EN_MASK 0x400
+#define DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define DEVICE_CNTL2__OBFF_EN_MASK 0x6000
+#define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
+#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define DEVICE_STATUS2__RESERVED_MASK 0xffff
+#define DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
+#define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
+#define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define LINK_CAP2__RESERVED_MASK 0xfffffe00
+#define LINK_CAP2__RESERVED__SHIFT 0x9
+#define LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
+#define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
+#define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
+#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
+#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define LINK_CNTL2__XMIT_MARGIN_MASK 0x380
+#define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
+#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
+#define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
+#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x1
+#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x2
+#define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x4
+#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x8
+#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x10
+#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x20
+#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define MSI_CAP_LIST__CAP_ID_MASK 0xff
+#define MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define MSI_MSG_CNTL__MSI_EN_MASK 0x1
+#define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe
+#define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x70
+#define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define MSI_MSG_CNTL__MSI_64BIT_MASK 0x80
+#define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x100
+#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
+#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
+#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
+#define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define MSI_MSG_DATA__MSI_DATA_MASK 0xffff
+#define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define MSI_MASK__MSI_MASK_MASK 0xffffffff
+#define MSI_MASK__MSI_MASK__SHIFT 0x0
+#define MSI_PENDING__MSI_PENDING_MASK 0xffffffff
+#define MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define MSI_MASK_64__MSI_MASK_64_MASK 0xffffffff
+#define MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define MSI_PENDING_64__MSI_PENDING_64_MASK 0xffffffff
+#define MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define MSIX_CAP_LIST__CAP_ID_MASK 0xff
+#define MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define MSIX_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x7ff
+#define MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000
+#define MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000
+#define MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x7
+#define MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xfffffff8
+#define MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define MSIX_PBA__MSIX_PBA_BIR_MASK 0x7
+#define MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xfffffff8
+#define MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
+#define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
+#define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
+#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
+#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
+#define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
+#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
+#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
+#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
+#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
+#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x1
+#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1
+#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2
+#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1
+#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2
+#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
+#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
+#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
+#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
+#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
+#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
+#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
+#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
+#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
+#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
+#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
+#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
+#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
+#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
+#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
+#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
+#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
+#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
+#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
+#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
+#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
+#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
+#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
+#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
+#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
+#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
+#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
+#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
+#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
+#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
+#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
+#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
+#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
+#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
+#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
+#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
+#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
+#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
+#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
+#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
+#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
+#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
+#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
+#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
+#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
+#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
+#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
+#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
+#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
+#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
+#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
+#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
+#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
+#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
+#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
+#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
+#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
+#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
+#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
+#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
+#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
+#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
+#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
+#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
+#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
+#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
+#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
+#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
+#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
+#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
+#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
+#define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
+#define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
+#define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
+#define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
+#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
+#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
+#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
+#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
+#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x7
+#define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0xe0
+#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1f00
+#define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
+#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x7
+#define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0xe0
+#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1f00
+#define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
+#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x7
+#define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0xe0
+#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1f00
+#define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
+#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x7
+#define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0xe0
+#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1f00
+#define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
+#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x7
+#define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0xe0
+#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1f00
+#define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
+#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x7
+#define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0xe0
+#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1f00
+#define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xff
+#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0xff
+#define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x300
+#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x1c00
+#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x6000
+#define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x38000
+#define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x1c0000
+#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x1
+#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x1f
+#define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300
+#define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000
+#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff
+#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x1f
+#define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x100
+#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1f
+#define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
+#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
+#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
+#define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
+#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
+#define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
+#define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
+#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
+#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
+#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
+#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
+#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
+#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
+#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x1
+#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x2
+#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x4
+#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x8
+#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x10
+#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x20
+#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x40
+#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x1f
+#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x20
+#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x40
+#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define PCIE_ATS_CNTL__STU_MASK 0x1f
+#define PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000
+#define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x1
+#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x2
+#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x1
+#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x2
+#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x100
+#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000
+#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xffffffff
+#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xffffffff
+#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2
+#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x4
+#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1f00
+#define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x1
+#define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x2
+#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x4
+#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x1
+#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x2
+#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x4
+#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x100
+#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x600
+#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x7ff0000
+#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x7
+#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x300
+#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
+#define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3f00
+#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
+#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f
+#define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000
+#define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
+#define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
+#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
+#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
+#define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
+#define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
+#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
+#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
+#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
+#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x3ff
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x1c00
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x3ff0000
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1c000000
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x1
+#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x2
+#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xff00
+#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x1
+#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x2
+#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x70
+#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x1
+#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x2
+#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xffe00000
+#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x1
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x2
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x4
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x8
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x10
+#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x1
+#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xffff
+#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xffff
+#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xffff
+#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xff
+#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xffff
+#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xffff
+#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xffff
+#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xffffffff
+#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xffffffff
+#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xffffffff
+#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xffffffff
+#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xffffffff
+#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xffffffff
+#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xffffffff
+#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xffffffff
+#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xffffffff
+#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0xf0000
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xfff00000
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0xf0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xfff00000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__CMD_CONTROL_MASK 0xff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__CMD_CONTROL__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__FCN_ID_MASK 0xff00
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__FCN_ID__SHIFT 0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__NXT_FCN_ID_MASK 0xff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__NXT_FCN_ID__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS__CMD_STATUS_MASK 0xff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS__CMD_STATUS__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION_MASK 0xffffffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS_MASK 0xffffffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_SIZE_MASK 0x7f
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_SIZE__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x80
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_OFFSET_MASK 0xfffc0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_OFFSET__SHIFT 0x12
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GPU_INFO_OFFSET_MASK 0xff00
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GPU_INFO_OFFSET__SHIFT 0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__AUTO_SCH_OFFSET_MASK 0xff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__AUTO_SCH_OFFSET__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__DISP_OFFSET_MASK 0xff000000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__DISP_OFFSET__SHIFT 0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_OFFSET_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_OFFSET__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_SIZE_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_SIZE__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_OFFSET_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_OFFSET__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_SIZE_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_SIZE__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_OFFSET_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_OFFSET__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_SIZE_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_SIZE__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_OFFSET_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_OFFSET__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_SIZE_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_SIZE__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_OFFSET_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_OFFSET__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_SIZE_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_SIZE__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_OFFSET_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_OFFSET__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_SIZE_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_SIZE__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_OFFSET_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_OFFSET__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_SIZE_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_SIZE__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_OFFSET_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_OFFSET__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_SIZE_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_SIZE__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_OFFSET_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_OFFSET__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_SIZE_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_SIZE__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_OFFSET_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_OFFSET__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_SIZE_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_SIZE__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_OFFSET_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_OFFSET__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_SIZE_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_SIZE__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_OFFSET_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_OFFSET__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_SIZE_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_SIZE__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_OFFSET_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_OFFSET__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_SIZE_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_SIZE__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_OFFSET_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_OFFSET__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_SIZE_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_SIZE__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_OFFSET_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_OFFSET__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_SIZE_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_SIZE__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_OFFSET_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_OFFSET__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_SIZE_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_SIZE__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT__GPU_IDLE_LATENCY_MASK 0xffffffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT__GPU_IDLE_LATENCY__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__LOWER_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__LOWER__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__UPPER_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__UPPER__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__LOWER_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__LOWER__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__UPPER_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__UPPER__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__LOWER_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__LOWER__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__UPPER_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__UPPER__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__LOWER_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__LOWER__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__UPPER_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__UPPER__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__LOWER_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__LOWER__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__UPPER_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__UPPER__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__LOWER_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__LOWER__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__UPPER_MASK 0xffff0000
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__UPPER__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0__DATA_MASK 0xffffffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0__DATA__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1__DATA_MASK 0xffffffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1__DATA__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2__DATA_MASK 0xffffffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2__DATA__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3__DATA_MASK 0xffffffff
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3__DATA__SHIFT 0x0
+#define PCIE_INDEX__PCIE_INDEX_MASK 0xffffffff
+#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
+#define PCIE_DATA__PCIE_DATA_MASK 0xffffffff
+#define PCIE_DATA__PCIE_DATA__SHIFT 0x0
+#define PCIE_INDEX_2__PCIE_INDEX_MASK 0xffffffff
+#define PCIE_INDEX_2__PCIE_INDEX__SHIFT 0x0
+#define PCIE_DATA_2__PCIE_DATA_MASK 0xffffffff
+#define PCIE_DATA_2__PCIE_DATA__SHIFT 0x0
+#define PCIE_HOLD_TRAINING_A__HOLD_TRAINING_A_MASK 0x1
+#define PCIE_HOLD_TRAINING_A__HOLD_TRAINING_A__SHIFT 0x0
+#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN0_MASK 0x1
+#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN0__SHIFT 0x0
+#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1_MASK 0x2
+#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1__SHIFT 0x1
+#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2_MASK 0x4
+#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2__SHIFT 0x2
+#define LNCNT_CONTROL__CFG_LNC_OVRD_EN3_MASK 0x8
+#define LNCNT_CONTROL__CFG_LNC_OVRD_EN3__SHIFT 0x3
+#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL4_MASK 0x10
+#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL4__SHIFT 0x4
+#define CFG_LNC_WINDOW__CFG_LNC_WINDOW0_MASK 0xffffff
+#define CFG_LNC_WINDOW__CFG_LNC_WINDOW0__SHIFT 0x0
+#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0_MASK 0x7
+#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0__SHIFT 0x0
+#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4_MASK 0x70
+#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4__SHIFT 0x4
+#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0_MASK 0xffff
+#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0__SHIFT 0x0
+#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16_MASK 0xffff0000
+#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16__SHIFT 0x10
+#define LNC_TOTAL_WACC__LNC_TOTAL_WACC_MASK 0xffffffff
+#define LNC_TOTAL_WACC__LNC_TOTAL_WACC__SHIFT 0x0
+#define LNC_BW_WACC__LNC_BW_WACC_MASK 0xffffffff
+#define LNC_BW_WACC__LNC_BW_WACC__SHIFT 0x0
+#define LNC_CMN_WACC__LNC_CMN_WACC_MASK 0xffffffff
+#define LNC_CMN_WACC__LNC_CMN_WACC__SHIFT 0x0
+#define PCIE_EFUSE__PCIE_EFUSE_VALID_MASK 0x2
+#define PCIE_EFUSE__PCIE_EFUSE_VALID__SHIFT 0x1
+#define PCIE_EFUSE__PPHY_EFUSE_VALID_MASK 0x4
+#define PCIE_EFUSE__PPHY_EFUSE_VALID__SHIFT 0x2
+#define PCIE_EFUSE__SPARE_5_3_EFUSE0_MASK 0x38
+#define PCIE_EFUSE__SPARE_5_3_EFUSE0__SHIFT 0x3
+#define PCIE_EFUSE__ISTRAP_ARBEN0_MASK 0x40
+#define PCIE_EFUSE__ISTRAP_ARBEN0__SHIFT 0x6
+#define PCIE_EFUSE__SPARE_26_7_EFUSE0_MASK 0x7ffff80
+#define PCIE_EFUSE__SPARE_26_7_EFUSE0__SHIFT 0x7
+#define PCIE_EFUSE__CHIP_BIF_MODE_MASK 0x8000000
+#define PCIE_EFUSE__CHIP_BIF_MODE__SHIFT 0x1b
+#define PCIE_EFUSE__SPARE_31_28_EFUSE0_MASK 0xf0000000
+#define PCIE_EFUSE__SPARE_31_28_EFUSE0__SHIFT 0x1c
+#define PCIE_EFUSE2__SPARE_31_1_EFUSE2_MASK 0xfffffffe
+#define PCIE_EFUSE2__SPARE_31_1_EFUSE2__SHIFT 0x1
+#define PCIE_EFUSE3__STRAP_CEC_ID_MASK 0x1fffe
+#define PCIE_EFUSE3__STRAP_CEC_ID__SHIFT 0x1
+#define PCIE_EFUSE3__STRAP_BIF_KILL_GEN3_MASK 0x20000
+#define PCIE_EFUSE3__STRAP_BIF_KILL_GEN3__SHIFT 0x11
+#define PCIE_EFUSE3__SPARE_14_PCIEFUSE3_MASK 0xfffc0000
+#define PCIE_EFUSE3__SPARE_14_PCIEFUSE3__SHIFT 0x12
+#define PCIE_EFUSE4__CC_WRITE_DISABLE_MASK 0x1
+#define PCIE_EFUSE4__CC_WRITE_DISABLE__SHIFT 0x0
+#define PCIE_EFUSE4__SPARE_3_PCIEFUSE4_MASK 0xe
+#define PCIE_EFUSE4__SPARE_3_PCIEFUSE4__SHIFT 0x1
+#define PCIE_EFUSE4__STRAP_BIF_F0_DEVICE_ID_MASK 0xffff0
+#define PCIE_EFUSE4__STRAP_BIF_F0_DEVICE_ID__SHIFT 0x4
+#define PCIE_EFUSE4__STRAP_BIF_F0_MAJOR_REV_ID_MASK 0xf00000
+#define PCIE_EFUSE4__STRAP_BIF_F0_MAJOR_REV_ID__SHIFT 0x14
+#define PCIE_EFUSE4__STRAP_BIF_F0_MINOR_REV_ID_MASK 0xf000000
+#define PCIE_EFUSE4__STRAP_BIF_F0_MINOR_REV_ID__SHIFT 0x18
+#define PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK 0xf0000000
+#define PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT 0x1c
+#define PCIE_EFUSE5__STRAP_AZALIA_DID_MASK 0x1fffe
+#define PCIE_EFUSE5__STRAP_AZALIA_DID__SHIFT 0x1
+#define PCIE_EFUSE5__SPARE_16_PCIEFUSE5_MASK 0xfffe0000
+#define PCIE_EFUSE5__SPARE_16_PCIEFUSE5__SHIFT 0x11
+#define PCIE_EFUSE6__STRAP_BIF_F0_SUPPORTED_PAGE_SIZES_MASK 0x1fffe
+#define PCIE_EFUSE6__STRAP_BIF_F0_SUPPORTED_PAGE_SIZES__SHIFT 0x1
+#define PCIE_EFUSE6__SPARE_15_PCIEFUSE6_MASK 0xfffe0000
+#define PCIE_EFUSE6__SPARE_15_PCIEFUSE6__SHIFT 0x11
+#define PCIE_EFUSE7__STRAP_BIF_F0_SRIOV_VF_DEVICE_ID_MASK 0x1fffe
+#define PCIE_EFUSE7__STRAP_BIF_F0_SRIOV_VF_DEVICE_ID__SHIFT 0x1
+#define PCIE_EFUSE7__SPARE_15_PCIEFUSE7_MASK 0xfffe0000
+#define PCIE_EFUSE7__SPARE_15_PCIEFUSE7__SHIFT 0x11
+#define PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1_MASK 0xffffffff
+#define PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1__SHIFT 0x0
+#define PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2_MASK 0xffffffff
+#define PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2__SHIFT 0x0
+#define PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK_MASK 0x1
+#define PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK__SHIFT 0x0
+#define PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE_MASK 0x1
+#define PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE__SHIFT 0x0
+#define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN_MASK 0x1
+#define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN__SHIFT 0x0
+#define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN_MASK 0x2
+#define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN__SHIFT 0x1
+#define PCIE_WRAP_MISC__STRAP_BIF_HOLD_TRAINING_STICKY_MASK 0x2
+#define PCIE_WRAP_MISC__STRAP_BIF_HOLD_TRAINING_STICKY__SHIFT 0x1
+#define PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START_MASK 0x4
+#define PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START__SHIFT 0x2
+#define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI_MASK 0x7
+#define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI__SHIFT 0x0
+#define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI_MASK 0x70
+#define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI__SHIFT 0x4
+#define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI_MASK 0x80
+#define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI__SHIFT 0x7
+#define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI_MASK 0x100
+#define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI__SHIFT 0x8
+#define PCIE_RXDET_OVERRIDE__RxDetOvrVal_MASK 0xffff
+#define PCIE_RXDET_OVERRIDE__RxDetOvrVal__SHIFT 0x0
+#define PCIE_RXDET_OVERRIDE__RxDetOvrEn_MASK 0x10000
+#define PCIE_RXDET_OVERRIDE__RxDetOvrEn__SHIFT 0x10
+#define REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0_MASK 0x1
+#define REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0__SHIFT 0x0
+#define REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt_MASK 0x1
+#define REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt__SHIFT 0x0
+#define REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr_MASK 0x1
+#define REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr__SHIFT 0x0
+#define REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0_MASK 0x1
+#define REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0__SHIFT 0x0
+#define PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff
+#define PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff
+#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff
+#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0
+#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff
+#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0
+#define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1
+#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe
+#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1
+#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80
+#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100
+#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200
+#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9
+#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00
+#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa
+#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000
+#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf
+#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000
+#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10
+#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000
+#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11
+#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000
+#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12
+#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000
+#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13
+#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x100000
+#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14
+#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000
+#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15
+#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000
+#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16
+#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000
+#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17
+#define PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000
+#define PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18
+#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000
+#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000
+#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f
+#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf
+#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0
+#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000
+#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18
+#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000
+#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff
+#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0
+#define PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100
+#define PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8
+#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000
+#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10
+#define PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x1
+#define PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
+#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x2
+#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
+#define PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x4
+#define PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
+#define PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x8
+#define PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
+#define PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x10
+#define PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
+#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x40
+#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
+#define PCIE_INT_CNTL__LINK_BW_INT_EN_MASK 0x80
+#define PCIE_INT_CNTL__LINK_BW_INT_EN__SHIFT 0x7
+#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN_MASK 0x100
+#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN__SHIFT 0x8
+#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x1
+#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
+#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x2
+#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
+#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x4
+#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
+#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x8
+#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
+#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x10
+#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
+#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x40
+#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
+#define PCIE_INT_STATUS__LINK_BW_INT_STATUS_MASK 0x80
+#define PCIE_INT_STATUS__LINK_BW_INT_STATUS__SHIFT 0x7
+#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS_MASK 0x100
+#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS__SHIFT 0x8
+#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1
+#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0
+#define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e
+#define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1
+#define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0
+#define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6
+#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800
+#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb
+#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK 0x1000
+#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT 0xc
+#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK 0x2000
+#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT 0xd
+#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK 0x4000
+#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT 0xe
+#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000
+#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11
+#define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000
+#define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12
+#define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000
+#define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13
+#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000
+#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15
+#define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000
+#define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16
+#define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000
+#define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17
+#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000
+#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18
+#define PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000
+#define PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d
+#define PCIE_CNTL2__MST_MEM_DS_EN_MASK 0x40000000
+#define PCIE_CNTL2__MST_MEM_DS_EN__SHIFT 0x1e
+#define PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK 0x80000000
+#define PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT 0x1f
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9
+#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x1000
+#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc
+#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x2000
+#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd
+#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x4000
+#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10
+#define PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000
+#define PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P_MASK 0x3
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P__SHIFT 0x0
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP_MASK 0xc
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP__SHIFT 0x2
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL_MASK 0x30
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL__SHIFT 0x4
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P_MASK 0xc0
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P__SHIFT 0x6
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP_MASK 0x300
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP__SHIFT 0x8
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P_MASK 0xc00
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P__SHIFT 0xa
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP_MASK 0x3000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP__SHIFT 0xc
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P_MASK 0x30000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P__SHIFT 0x10
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP_MASK 0xc0000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP__SHIFT 0x12
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL_MASK 0x300000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL__SHIFT 0x14
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P_MASK 0xc00000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P__SHIFT 0x16
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP_MASK 0x3000000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP__SHIFT 0x18
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P_MASK 0xc000000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P__SHIFT 0x1a
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP_MASK 0x30000000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP__SHIFT 0x1c
+#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4
+#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2
+#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8
+#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3
+#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10
+#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4
+#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0
+#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6
+#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100
+#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8
+#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200
+#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc
+#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST_MASK 0x2000
+#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST__SHIFT 0xd
+#define PCIE_CI_CNTL__CI_MST_ATOMIC_ADDR_HASH_MASK 0x70000
+#define PCIE_CI_CNTL__CI_MST_ATOMIC_ADDR_HASH__SHIFT 0x10
+#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40
+#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6
+#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80
+#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000
+#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc
+#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f
+#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0
+#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00
+#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8
+#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000
+#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10
+#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000
+#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18
+#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f
+#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0
+#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00
+#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8
+#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000
+#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10
+#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000
+#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18
+#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f
+#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0
+#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00
+#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8
+#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000
+#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10
+#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000
+#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18
+#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f
+#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0
+#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00
+#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8
+#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000
+#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10
+#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000
+#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18
+#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f
+#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0
+#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00
+#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8
+#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000
+#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10
+#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000
+#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18
+#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f
+#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0
+#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00
+#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8
+#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000
+#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10
+#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000
+#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18
+#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1
+#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0
+#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2
+#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1
+#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c
+#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2
+#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0
+#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5
+#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff
+#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0
+#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000
+#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10
+#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1
+#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2
+#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8
+#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3
+#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10
+#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4
+#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20
+#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5
+#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40
+#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6
+#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff
+#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0
+#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff
+#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0
+#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff
+#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0
+#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff
+#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0
+#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff
+#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0
+#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff
+#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0
+#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff
+#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0
+#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff
+#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0
+#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff
+#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0
+#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff
+#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN_MASK 0x1
+#define PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN__SHIFT 0x0
+#define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1
+#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0
+#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2
+#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1
+#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4
+#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2
+#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8
+#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3
+#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10
+#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4
+#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20
+#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5
+#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40
+#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6
+#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80
+#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7
+#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100
+#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8
+#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000
+#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc
+#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000
+#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd
+#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000
+#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe
+#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000
+#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10
+#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff
+#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0
+#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000
+#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10
+#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff
+#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0
+#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff
+#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0
+#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000
+#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8
+#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE_MASK 0x1
+#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT 0x0
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN_MASK 0x2
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT 0x1
+#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE_MASK 0x4
+#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2
+#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE_MASK 0x8
+#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT 0x3
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH_MASK 0xf0
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT 0x4
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH_MASK 0xf00
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT 0x8
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD_MASK 0xf000
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT 0xc
+#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE_MASK 0x10000
+#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT 0x10
+#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE_MASK 0x20000
+#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT 0x11
+#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE_MASK 0x40000
+#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT 0x12
+#define PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0_MASK 0x80000
+#define PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0__SHIFT 0x13
+#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE_MASK 0xf00000
+#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT 0x14
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x7
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x38
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x40
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x380
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x1c00
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x2000
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x4000
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x8000
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x10000
+#define PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
+#define PCIE_IDLE_STATUS__PCIE_ALL_IDLE_STATUS_MASK 0x1
+#define PCIE_IDLE_STATUS__PCIE_ALL_IDLE_STATUS__SHIFT 0x0
+#define PCIE_IDLE_STATUS__TX_TXDL_IDLE_STATUS_MASK 0x2
+#define PCIE_IDLE_STATUS__TX_TXDL_IDLE_STATUS__SHIFT 0x1
+#define PCIE_IDLE_STATUS__TX_RBUF_IDLE_STATUS_MASK 0x4
+#define PCIE_IDLE_STATUS__TX_RBUF_IDLE_STATUS__SHIFT 0x2
+#define PCIE_IDLE_STATUS__TX_RCVD_FC_CREDITS_IDLE_MASK 0x8
+#define PCIE_IDLE_STATUS__TX_RCVD_FC_CREDITS_IDLE__SHIFT 0x3
+#define PCIE_IDLE_STATUS__TX_RPL_CREDITS_IDLE_MASK 0x10
+#define PCIE_IDLE_STATUS__TX_RPL_CREDITS_IDLE__SHIFT 0x4
+#define PCIE_IDLE_STATUS__TX_PBUF_IDLE_MASK 0x20
+#define PCIE_IDLE_STATUS__TX_PBUF_IDLE__SHIFT 0x5
+#define PCIE_IDLE_STATUS__TX_NPBUF_IDLE_MASK 0x40
+#define PCIE_IDLE_STATUS__TX_NPBUF_IDLE__SHIFT 0x6
+#define PCIE_IDLE_STATUS__TX_CPLBUF_IDLE_MASK 0x80
+#define PCIE_IDLE_STATUS__TX_CPLBUF_IDLE__SHIFT 0x7
+#define PCIE_IDLE_STATUS__TX_MSGBUF_IDLE_MASK 0x100
+#define PCIE_IDLE_STATUS__TX_MSGBUF_IDLE__SHIFT 0x8
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2
+#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff
+#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00
+#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000
+#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000
+#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff
+#define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff
+#define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff
+#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00
+#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff
+#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff
+#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff
+#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00
+#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff
+#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff
+#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff
+#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00
+#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff
+#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff
+#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff
+#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff
+#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff
+#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff
+#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18
+#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff
+#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00
+#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff
+#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff
+#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0
+#define PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1
+#define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
+#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2
+#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
+#define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4
+#define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2
+#define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8
+#define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3
+#define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10
+#define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4
+#define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20
+#define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5
+#define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40
+#define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6
+#define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80
+#define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7
+#define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100
+#define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8
+#define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200
+#define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9
+#define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400
+#define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa
+#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800
+#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb
+#define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000
+#define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc
+#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000
+#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd
+#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000
+#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe
+#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000
+#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf
+#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000
+#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
+#define PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000
+#define PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK 0x40000
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT 0x12
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK 0x80000
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT 0x13
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x100000
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x14
+#define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0xe00000
+#define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
+#define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK 0x7000000
+#define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT 0x18
+#define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000
+#define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b
+#define PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x10000000
+#define PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1c
+#define PCIE_STRAP_F0__STRAP_F0_ARI_EN_MASK 0x20000000
+#define PCIE_STRAP_F0__STRAP_F0_ARI_EN__SHIFT 0x1d
+#define PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK 0x40000000
+#define PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT 0x1e
+#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK 0x2
+#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
+#define PCIE_STRAP_F1__STRAP_F1_MSI_EN_MASK 0x4
+#define PCIE_STRAP_F1__STRAP_F1_MSI_EN__SHIFT 0x2
+#define PCIE_STRAP_F1__STRAP_F1_VC_EN_MASK 0x8
+#define PCIE_STRAP_F1__STRAP_F1_VC_EN__SHIFT 0x3
+#define PCIE_STRAP_F1__STRAP_F1_DSN_EN_MASK 0x10
+#define PCIE_STRAP_F1__STRAP_F1_DSN_EN__SHIFT 0x4
+#define PCIE_STRAP_F1__STRAP_F1_AER_EN_MASK 0x20
+#define PCIE_STRAP_F1__STRAP_F1_AER_EN__SHIFT 0x5
+#define PCIE_STRAP_F1__STRAP_F1_ACS_EN_MASK 0x40
+#define PCIE_STRAP_F1__STRAP_F1_ACS_EN__SHIFT 0x6
+#define PCIE_STRAP_F1__STRAP_F1_BAR_EN_MASK 0x80
+#define PCIE_STRAP_F1__STRAP_F1_BAR_EN__SHIFT 0x7
+#define PCIE_STRAP_F1__STRAP_F1_PWR_EN_MASK 0x100
+#define PCIE_STRAP_F1__STRAP_F1_PWR_EN__SHIFT 0x8
+#define PCIE_STRAP_F1__STRAP_F1_DPA_EN_MASK 0x200
+#define PCIE_STRAP_F1__STRAP_F1_DPA_EN__SHIFT 0x9
+#define PCIE_STRAP_F1__STRAP_F1_ATS_EN_MASK 0x400
+#define PCIE_STRAP_F1__STRAP_F1_ATS_EN__SHIFT 0xa
+#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN_MASK 0x800
+#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN__SHIFT 0xb
+#define PCIE_STRAP_F1__STRAP_F1_PASID_EN_MASK 0x1000
+#define PCIE_STRAP_F1__STRAP_F1_PASID_EN__SHIFT 0xc
+#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN_MASK 0x2000
+#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN__SHIFT 0xd
+#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN_MASK 0x4000
+#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN__SHIFT 0xe
+#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN_MASK 0x8000
+#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN__SHIFT 0xf
+#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL_MASK 0x10000
+#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
+#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_EN_MASK 0x40000
+#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_EN__SHIFT 0x12
+#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_64BIT_EN_MASK 0x80000
+#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_64BIT_EN__SHIFT 0x13
+#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_ROUTING_EN_MASK 0x100000
+#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_ROUTING_EN__SHIFT 0x14
+#define PCIE_STRAP_F1__STRAP_F1_MSI_MULTI_CAP_MASK 0xe00000
+#define PCIE_STRAP_F1__STRAP_F1_MSI_MULTI_CAP__SHIFT 0x15
+#define PCIE_STRAP_F1__STRAP_F1_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000
+#define PCIE_STRAP_F1__STRAP_F1_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b
+#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK 0x2
+#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
+#define PCIE_STRAP_F2__STRAP_F2_MSI_EN_MASK 0x4
+#define PCIE_STRAP_F2__STRAP_F2_MSI_EN__SHIFT 0x2
+#define PCIE_STRAP_F2__STRAP_F2_VC_EN_MASK 0x8
+#define PCIE_STRAP_F2__STRAP_F2_VC_EN__SHIFT 0x3
+#define PCIE_STRAP_F2__STRAP_F2_DSN_EN_MASK 0x10
+#define PCIE_STRAP_F2__STRAP_F2_DSN_EN__SHIFT 0x4
+#define PCIE_STRAP_F2__STRAP_F2_AER_EN_MASK 0x20
+#define PCIE_STRAP_F2__STRAP_F2_AER_EN__SHIFT 0x5
+#define PCIE_STRAP_F2__STRAP_F2_ACS_EN_MASK 0x40
+#define PCIE_STRAP_F2__STRAP_F2_ACS_EN__SHIFT 0x6
+#define PCIE_STRAP_F2__STRAP_F2_BAR_EN_MASK 0x80
+#define PCIE_STRAP_F2__STRAP_F2_BAR_EN__SHIFT 0x7
+#define PCIE_STRAP_F2__STRAP_F2_PWR_EN_MASK 0x100
+#define PCIE_STRAP_F2__STRAP_F2_PWR_EN__SHIFT 0x8
+#define PCIE_STRAP_F2__STRAP_F2_DPA_EN_MASK 0x200
+#define PCIE_STRAP_F2__STRAP_F2_DPA_EN__SHIFT 0x9
+#define PCIE_STRAP_F2__STRAP_F2_ATS_EN_MASK 0x400
+#define PCIE_STRAP_F2__STRAP_F2_ATS_EN__SHIFT 0xa
+#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN_MASK 0x800
+#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN__SHIFT 0xb
+#define PCIE_STRAP_F2__STRAP_F2_PASID_EN_MASK 0x1000
+#define PCIE_STRAP_F2__STRAP_F2_PASID_EN__SHIFT 0xc
+#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN_MASK 0x2000
+#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN__SHIFT 0xd
+#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN_MASK 0x4000
+#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN__SHIFT 0xe
+#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN_MASK 0x8000
+#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN__SHIFT 0xf
+#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL_MASK 0x10000
+#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
+#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_EN_MASK 0x40000
+#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_EN__SHIFT 0x12
+#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_64BIT_EN_MASK 0x80000
+#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_64BIT_EN__SHIFT 0x13
+#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_ROUTING_EN_MASK 0x100000
+#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_ROUTING_EN__SHIFT 0x14
+#define PCIE_STRAP_F2__STRAP_F2_MSI_MULTI_CAP_MASK 0xe00000
+#define PCIE_STRAP_F2__STRAP_F2_MSI_MULTI_CAP__SHIFT 0x15
+#define PCIE_STRAP_F2__STRAP_F2_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000
+#define PCIE_STRAP_F2__STRAP_F2_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b
+#define PCIE_STRAP_F3__RESERVED_MASK 0xffffffff
+#define PCIE_STRAP_F3__RESERVED__SHIFT 0x0
+#define PCIE_STRAP_F4__RESERVED_MASK 0xffffffff
+#define PCIE_STRAP_F4__RESERVED__SHIFT 0x0
+#define PCIE_STRAP_F5__RESERVED_MASK 0xffffffff
+#define PCIE_STRAP_F5__RESERVED__SHIFT 0x0
+#define PCIE_STRAP_F6__RESERVED_MASK 0xffffffff
+#define PCIE_STRAP_F6__RESERVED__SHIFT 0x0
+#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_EN_MASK 0x1
+#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_EN__SHIFT 0x0
+#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_BIR_MASK 0xe
+#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_BIR__SHIFT 0x1
+#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_OFFSET_MASK 0xfffff000
+#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_OFFSET__SHIFT 0xc
+#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10
+#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4
+#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH_MASK 0x1f00
+#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH__SHIFT 0x8
+#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2000
+#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0xd
+#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED_MASK 0x4000
+#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED__SHIFT 0xe
+#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_MASK 0x8000
+#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0xf
+#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000
+#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
+#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000
+#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19
+#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000
+#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a
+#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000
+#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c
+#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000
+#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000
+#define PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e
+#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000
+#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f
+#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2
+#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1
+#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4
+#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
+#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8
+#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3
+#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10
+#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
+#define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1
+#define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d
+#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f
+#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0
+#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80
+#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7
+#define PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff
+#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0
+#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000
+#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10
+#define PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x1000000
+#define PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18
+#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff
+#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0
+#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000
+#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10
+#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff
+#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0
+#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff
+#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0
+#define PCIE_PRBS_MISC__PRBS_EN_MASK 0x1
+#define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0
+#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0xe
+#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1
+#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x10
+#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4
+#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x20
+#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5
+#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0xc0
+#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6
+#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x1f00
+#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8
+#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000
+#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe
+#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000
+#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10
+#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff
+#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0
+#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff
+#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0
+#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff
+#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0
+#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300
+#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000
+#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000
+#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000
+#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff
+#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x1f
+#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
+#define PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x100
+#define PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x1
+#define SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0
+#define SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x2
+#define SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1
+#define SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x10000
+#define SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10
+#define SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x20000
+#define SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11
+#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x1
+#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0
+#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x2
+#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1
+#define SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x1c
+#define SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2
+#define SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x100
+#define SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8
+#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x200
+#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9
+#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x400
+#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa
+#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x1000
+#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc
+#define SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE_MASK 0x2000
+#define SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE__SHIFT 0xd
+#define SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE_MASK 0x4000
+#define SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE__SHIFT 0xe
+#define SWRST_GENERAL_CONTROL__BYPASS_HOLD_MASK 0x10000
+#define SWRST_GENERAL_CONTROL__BYPASS_HOLD__SHIFT 0x10
+#define SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD_MASK 0x20000
+#define SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD__SHIFT 0x11
+#define SWRST_GENERAL_CONTROL__EP_COMPLT_CHK_EN_MASK 0x10000000
+#define SWRST_GENERAL_CONTROL__EP_COMPLT_CHK_EN__SHIFT 0x1c
+#define SWRST_GENERAL_CONTROL__EP_COMPLT_WAIT_TMR_MASK 0x60000000
+#define SWRST_GENERAL_CONTROL__EP_COMPLT_WAIT_TMR__SHIFT 0x1d
+#define SWRST_COMMAND_0__BIF_STRAPREG_RESET_MASK 0x8000
+#define SWRST_COMMAND_0__BIF_STRAPREG_RESET__SHIFT 0xf
+#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x10000
+#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x10
+#define SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x20000
+#define SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x11
+#define SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x40000
+#define SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x12
+#define SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x80000
+#define SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x13
+#define SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x100000
+#define SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x14
+#define SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x200000
+#define SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x15
+#define SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x400000
+#define SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x16
+#define SWRST_COMMAND_1__SWITCHCLK_MASK 0x1
+#define SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x0
+#define SWRST_COMMAND_1__RESETPCFG_MASK 0x2
+#define SWRST_COMMAND_1__RESETPCFG__SHIFT 0x1
+#define SWRST_COMMAND_1__RESETLANEMUX_MASK 0x4
+#define SWRST_COMMAND_1__RESETLANEMUX__SHIFT 0x2
+#define SWRST_COMMAND_1__RESETWRAPREGS_MASK 0x8
+#define SWRST_COMMAND_1__RESETWRAPREGS__SHIFT 0x3
+#define SWRST_COMMAND_1__RESETSRBM0_MASK 0x10
+#define SWRST_COMMAND_1__RESETSRBM0__SHIFT 0x4
+#define SWRST_COMMAND_1__RESETSRBM1_MASK 0x20
+#define SWRST_COMMAND_1__RESETSRBM1__SHIFT 0x5
+#define SWRST_COMMAND_1__RESETLC_MASK 0x40
+#define SWRST_COMMAND_1__RESETLC__SHIFT 0x6
+#define SWRST_COMMAND_1__SYNCIDLEPIF0_MASK 0x100
+#define SWRST_COMMAND_1__SYNCIDLEPIF0__SHIFT 0x8
+#define SWRST_COMMAND_1__SYNCIDLEPIF1_MASK 0x200
+#define SWRST_COMMAND_1__SYNCIDLEPIF1__SHIFT 0x9
+#define SWRST_COMMAND_1__RESETMNTR_MASK 0x2000
+#define SWRST_COMMAND_1__RESETMNTR__SHIFT 0xd
+#define SWRST_COMMAND_1__RESETHLTR_MASK 0x4000
+#define SWRST_COMMAND_1__RESETHLTR__SHIFT 0xe
+#define SWRST_COMMAND_1__RESETCPM_MASK 0x8000
+#define SWRST_COMMAND_1__RESETCPM__SHIFT 0xf
+#define SWRST_COMMAND_1__RESETPIF0_MASK 0x10000
+#define SWRST_COMMAND_1__RESETPIF0__SHIFT 0x10
+#define SWRST_COMMAND_1__RESETPIF1_MASK 0x20000
+#define SWRST_COMMAND_1__RESETPIF1__SHIFT 0x11
+#define SWRST_COMMAND_1__RESETIMPARB0_MASK 0x100000
+#define SWRST_COMMAND_1__RESETIMPARB0__SHIFT 0x14
+#define SWRST_COMMAND_1__RESETIMPARB1_MASK 0x200000
+#define SWRST_COMMAND_1__RESETIMPARB1__SHIFT 0x15
+#define SWRST_COMMAND_1__RESETPHY0_MASK 0x1000000
+#define SWRST_COMMAND_1__RESETPHY0__SHIFT 0x18
+#define SWRST_COMMAND_1__RESETPHY1_MASK 0x2000000
+#define SWRST_COMMAND_1__RESETPHY1__SHIFT 0x19
+#define SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x10000000
+#define SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1c
+#define SWRST_COMMAND_1__CMDCFGEN_MASK 0x20000000
+#define SWRST_COMMAND_1__CMDCFGEN__SHIFT 0x1d
+#define SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN_MASK 0x8000
+#define SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN__SHIFT 0xf
+#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x10000
+#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x10
+#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x20000
+#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x11
+#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x40000
+#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x12
+#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x80000
+#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x13
+#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x100000
+#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x14
+#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x200000
+#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x15
+#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x400000
+#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x16
+#define SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x1
+#define SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x0
+#define SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x2
+#define SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x1
+#define SWRST_CONTROL_1__RESETLANEMUX_RCEN_MASK 0x4
+#define SWRST_CONTROL_1__RESETLANEMUX_RCEN__SHIFT 0x2
+#define SWRST_CONTROL_1__RESETWRAPREGS_RCEN_MASK 0x8
+#define SWRST_CONTROL_1__RESETWRAPREGS_RCEN__SHIFT 0x3
+#define SWRST_CONTROL_1__RESETSRBM0_RCEN_MASK 0x10
+#define SWRST_CONTROL_1__RESETSRBM0_RCEN__SHIFT 0x4
+#define SWRST_CONTROL_1__RESETSRBM1_RCEN_MASK 0x20
+#define SWRST_CONTROL_1__RESETSRBM1_RCEN__SHIFT 0x5
+#define SWRST_CONTROL_1__RESETLC_RCEN_MASK 0x40
+#define SWRST_CONTROL_1__RESETLC_RCEN__SHIFT 0x6
+#define SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN_MASK 0x100
+#define SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN__SHIFT 0x8
+#define SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN_MASK 0x200
+#define SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN__SHIFT 0x9
+#define SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x2000
+#define SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0xd
+#define SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x4000
+#define SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0xe
+#define SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x8000
+#define SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0xf
+#define SWRST_CONTROL_1__RESETPIF0_RCEN_MASK 0x10000
+#define SWRST_CONTROL_1__RESETPIF0_RCEN__SHIFT 0x10
+#define SWRST_CONTROL_1__RESETPIF1_RCEN_MASK 0x20000
+#define SWRST_CONTROL_1__RESETPIF1_RCEN__SHIFT 0x11
+#define SWRST_CONTROL_1__RESETIMPARB0_RCEN_MASK 0x100000
+#define SWRST_CONTROL_1__RESETIMPARB0_RCEN__SHIFT 0x14
+#define SWRST_CONTROL_1__RESETIMPARB1_RCEN_MASK 0x200000
+#define SWRST_CONTROL_1__RESETIMPARB1_RCEN__SHIFT 0x15
+#define SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x1000000
+#define SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x18
+#define SWRST_CONTROL_1__RESETPHY1_RCEN_MASK 0x2000000
+#define SWRST_CONTROL_1__RESETPHY1_RCEN__SHIFT 0x19
+#define SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x10000000
+#define SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1c
+#define SWRST_CONTROL_1__CMDCFG_RCEN_MASK 0x20000000
+#define SWRST_CONTROL_1__CMDCFG_RCEN__SHIFT 0x1d
+#define SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN_MASK 0x8000
+#define SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN__SHIFT 0xf
+#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x10000
+#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x10
+#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x20000
+#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x11
+#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x40000
+#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x12
+#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x80000
+#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x13
+#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x100000
+#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x14
+#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x200000
+#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x15
+#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x400000
+#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x16
+#define SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x1
+#define SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x0
+#define SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x2
+#define SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x1
+#define SWRST_CONTROL_3__RESETLANEMUX_ATEN_MASK 0x4
+#define SWRST_CONTROL_3__RESETLANEMUX_ATEN__SHIFT 0x2
+#define SWRST_CONTROL_3__RESETWRAPREGS_ATEN_MASK 0x8
+#define SWRST_CONTROL_3__RESETWRAPREGS_ATEN__SHIFT 0x3
+#define SWRST_CONTROL_3__RESETSRBM0_ATEN_MASK 0x10
+#define SWRST_CONTROL_3__RESETSRBM0_ATEN__SHIFT 0x4
+#define SWRST_CONTROL_3__RESETSRBM1_ATEN_MASK 0x20
+#define SWRST_CONTROL_3__RESETSRBM1_ATEN__SHIFT 0x5
+#define SWRST_CONTROL_3__RESETLC_ATEN_MASK 0x40
+#define SWRST_CONTROL_3__RESETLC_ATEN__SHIFT 0x6
+#define SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN_MASK 0x100
+#define SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN__SHIFT 0x8
+#define SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN_MASK 0x200
+#define SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN__SHIFT 0x9
+#define SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x2000
+#define SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0xd
+#define SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x4000
+#define SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0xe
+#define SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x8000
+#define SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0xf
+#define SWRST_CONTROL_3__RESETPIF0_ATEN_MASK 0x10000
+#define SWRST_CONTROL_3__RESETPIF0_ATEN__SHIFT 0x10
+#define SWRST_CONTROL_3__RESETPIF1_ATEN_MASK 0x20000
+#define SWRST_CONTROL_3__RESETPIF1_ATEN__SHIFT 0x11
+#define SWRST_CONTROL_3__RESETIMPARB0_ATEN_MASK 0x100000
+#define SWRST_CONTROL_3__RESETIMPARB0_ATEN__SHIFT 0x14
+#define SWRST_CONTROL_3__RESETIMPARB1_ATEN_MASK 0x200000
+#define SWRST_CONTROL_3__RESETIMPARB1_ATEN__SHIFT 0x15
+#define SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x1000000
+#define SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x18
+#define SWRST_CONTROL_3__RESETPHY1_ATEN_MASK 0x2000000
+#define SWRST_CONTROL_3__RESETPHY1_ATEN__SHIFT 0x19
+#define SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x10000000
+#define SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1c
+#define SWRST_CONTROL_3__CMDCFG_ATEN_MASK 0x20000000
+#define SWRST_CONTROL_3__CMDCFG_ATEN__SHIFT 0x1d
+#define SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN_MASK 0x4000
+#define SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN__SHIFT 0xe
+#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x10000
+#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x10
+#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x20000
+#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x11
+#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x40000
+#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x12
+#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x80000
+#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x13
+#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x100000
+#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x14
+#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x200000
+#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x15
+#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x400000
+#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x16
+#define SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x1
+#define SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x0
+#define SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x2
+#define SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x1
+#define SWRST_CONTROL_5__WRRESETLANEMUX_EN_MASK 0x4
+#define SWRST_CONTROL_5__WRRESETLANEMUX_EN__SHIFT 0x2
+#define SWRST_CONTROL_5__WRRESETWRAPREGS_EN_MASK 0x8
+#define SWRST_CONTROL_5__WRRESETWRAPREGS_EN__SHIFT 0x3
+#define SWRST_CONTROL_5__WRRESETSRBM0_EN_MASK 0x10
+#define SWRST_CONTROL_5__WRRESETSRBM0_EN__SHIFT 0x4
+#define SWRST_CONTROL_5__WRRESETSRBM1_EN_MASK 0x20
+#define SWRST_CONTROL_5__WRRESETSRBM1_EN__SHIFT 0x5
+#define SWRST_CONTROL_5__WRRESETLC_EN_MASK 0x40
+#define SWRST_CONTROL_5__WRRESETLC_EN__SHIFT 0x6
+#define SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN_MASK 0x100
+#define SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN__SHIFT 0x8
+#define SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN_MASK 0x200
+#define SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN__SHIFT 0x9
+#define SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x2000
+#define SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0xd
+#define SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x4000
+#define SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0xe
+#define SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x8000
+#define SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0xf
+#define SWRST_CONTROL_5__WRRESETPIF0_EN_MASK 0x10000
+#define SWRST_CONTROL_5__WRRESETPIF0_EN__SHIFT 0x10
+#define SWRST_CONTROL_5__WRRESETPIF1_EN_MASK 0x20000
+#define SWRST_CONTROL_5__WRRESETPIF1_EN__SHIFT 0x11
+#define SWRST_CONTROL_5__WRRESETIMPARB0_EN_MASK 0x100000
+#define SWRST_CONTROL_5__WRRESETIMPARB0_EN__SHIFT 0x14
+#define SWRST_CONTROL_5__WRRESETIMPARB1_EN_MASK 0x200000
+#define SWRST_CONTROL_5__WRRESETIMPARB1_EN__SHIFT 0x15
+#define SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x1000000
+#define SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x18
+#define SWRST_CONTROL_5__WRRESETPHY1_EN_MASK 0x2000000
+#define SWRST_CONTROL_5__WRRESETPHY1_EN__SHIFT 0x19
+#define SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x10000000
+#define SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1c
+#define SWRST_CONTROL_5__WRCMDCFG_EN_MASK 0x20000000
+#define SWRST_CONTROL_5__WRCMDCFG_EN__SHIFT 0x1d
+#define SWRST_CONTROL_6__WARMRESET_EN_MASK 0x1
+#define SWRST_CONTROL_6__WARMRESET_EN__SHIFT 0x0
+#define SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN_MASK 0x100
+#define SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN__SHIFT 0x8
+#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY_MASK 0x1
+#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY__SHIFT 0x0
+#define SWRST_EP_COMMAND_0__EP_SOFT_RESET_MASK 0x2
+#define SWRST_EP_COMMAND_0__EP_SOFT_RESET__SHIFT 0x1
+#define SWRST_EP_COMMAND_0__EP_DRV_RESET_MASK 0x4
+#define SWRST_EP_COMMAND_0__EP_DRV_RESET__SHIFT 0x2
+#define SWRST_EP_COMMAND_0__EP_HOT_RESET_MASK 0x100
+#define SWRST_EP_COMMAND_0__EP_HOT_RESET__SHIFT 0x8
+#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET_MASK 0x200
+#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET__SHIFT 0x9
+#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET_MASK 0x400
+#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET__SHIFT 0xa
+#define SWRST_EP_COMMAND_0__EP_FLR0_RESET_MASK 0x10000
+#define SWRST_EP_COMMAND_0__EP_FLR0_RESET__SHIFT 0x10
+#define SWRST_EP_COMMAND_0__EP_FLR1_RESET_MASK 0x20000
+#define SWRST_EP_COMMAND_0__EP_FLR1_RESET__SHIFT 0x11
+#define SWRST_EP_COMMAND_0__EP_FLR2_RESET_MASK 0x40000
+#define SWRST_EP_COMMAND_0__EP_FLR2_RESET__SHIFT 0x12
+#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN_MASK 0x1
+#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN__SHIFT 0x0
+#define SWRST_EP_CONTROL_0__EP_SOFT_RESET_EN_MASK 0x2
+#define SWRST_EP_CONTROL_0__EP_SOFT_RESET_EN__SHIFT 0x1
+#define SWRST_EP_CONTROL_0__EP_DRV_RESET_EN_MASK 0x4
+#define SWRST_EP_CONTROL_0__EP_DRV_RESET_EN__SHIFT 0x2
+#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN_MASK 0x100
+#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN__SHIFT 0x8
+#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN_MASK 0x200
+#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN__SHIFT 0x9
+#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN_MASK 0x400
+#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN__SHIFT 0xa
+#define SWRST_EP_CONTROL_0__EP_FLR0_RESET_EN_MASK 0x10000
+#define SWRST_EP_CONTROL_0__EP_FLR0_RESET_EN__SHIFT 0x10
+#define SWRST_EP_CONTROL_0__EP_FLR1_RESET_EN_MASK 0x20000
+#define SWRST_EP_CONTROL_0__EP_FLR1_RESET_EN__SHIFT 0x11
+#define SWRST_EP_CONTROL_0__EP_FLR2_RESET_EN_MASK 0x40000
+#define SWRST_EP_CONTROL_0__EP_FLR2_RESET_EN__SHIFT 0x12
+#define SWRST_EP_CONTROL_0__EP_CFG_WR_RESET_EN_MASK 0x80000
+#define SWRST_EP_CONTROL_0__EP_CFG_WR_RESET_EN__SHIFT 0x13
+#define SWRST_EP_CONTROL_0__EP_FLR_DISABLE_CFG_RST_MASK 0xf00000
+#define SWRST_EP_CONTROL_0__EP_FLR_DISABLE_CFG_RST__SHIFT 0x14
+#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x1
+#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0
+#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x2
+#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1
+#define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK 0x4
+#define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT 0x2
+#define CPM_CONTROL__TXCLK_PIF_GATE_ENABLE_MASK 0x8
+#define CPM_CONTROL__TXCLK_PIF_GATE_ENABLE__SHIFT 0x3
+#define CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE_MASK 0x10
+#define CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE__SHIFT 0x4
+#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x20
+#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5
+#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x40
+#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6
+#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x80
+#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7
+#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x100
+#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8
+#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x200
+#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9
+#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x400
+#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xa
+#define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK 0x800
+#define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT 0xb
+#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x1000
+#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xc
+#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x2000
+#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xd
+#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x4000
+#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0xe
+#define CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x8000
+#define CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0xf
+#define CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN_MASK 0x10000
+#define CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN__SHIFT 0x10
+#define CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0xe0000
+#define CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x11
+#define CPM_CONTROL__MASTER_PCIE_PLL_SELECT_MASK 0x100000
+#define CPM_CONTROL__MASTER_PCIE_PLL_SELECT__SHIFT 0x14
+#define CPM_CONTROL__MASTER_PCIE_PLL_AUTO_MASK 0x200000
+#define CPM_CONTROL__MASTER_PCIE_PLL_AUTO__SHIFT 0x15
+#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x400000
+#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16
+#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x800000
+#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17
+#define CPM_CONTROL__SPARE_REGS_MASK 0xff000000
+#define CPM_CONTROL__SPARE_REGS__SHIFT 0x18
+#define GSKT_CONTROL__GSKT_TxFifoBypass_MASK 0x1
+#define GSKT_CONTROL__GSKT_TxFifoBypass__SHIFT 0x0
+#define GSKT_CONTROL__GSKT_TxFifoDelay_MASK 0x2
+#define GSKT_CONTROL__GSKT_TxFifoDelay__SHIFT 0x1
+#define GSKT_CONTROL__GSKT_TxFifoDelay2_MASK 0x4
+#define GSKT_CONTROL__GSKT_TxFifoDelay2__SHIFT 0x2
+#define GSKT_CONTROL__GSKT_SpareRegs_MASK 0xf8
+#define GSKT_CONTROL__GSKT_SpareRegs__SHIFT 0x3
+#define LM_CONTROL__LoopbackSelect_MASK 0x1e
+#define LM_CONTROL__LoopbackSelect__SHIFT 0x1
+#define LM_CONTROL__PRBSPCIeLbSelect_MASK 0x20
+#define LM_CONTROL__PRBSPCIeLbSelect__SHIFT 0x5
+#define LM_CONTROL__LoopbackHalfRate_MASK 0xc0
+#define LM_CONTROL__LoopbackHalfRate__SHIFT 0x6
+#define LM_CONTROL__LoopbackFifoPtr_MASK 0x700
+#define LM_CONTROL__LoopbackFifoPtr__SHIFT 0x8
+#define LM_PCIETXMUX0__TXLANE0_MASK 0xff
+#define LM_PCIETXMUX0__TXLANE0__SHIFT 0x0
+#define LM_PCIETXMUX0__TXLANE1_MASK 0xff00
+#define LM_PCIETXMUX0__TXLANE1__SHIFT 0x8
+#define LM_PCIETXMUX0__TXLANE2_MASK 0xff0000
+#define LM_PCIETXMUX0__TXLANE2__SHIFT 0x10
+#define LM_PCIETXMUX0__TXLANE3_MASK 0xff000000
+#define LM_PCIETXMUX0__TXLANE3__SHIFT 0x18
+#define LM_PCIETXMUX1__TXLANE4_MASK 0xff
+#define LM_PCIETXMUX1__TXLANE4__SHIFT 0x0
+#define LM_PCIETXMUX1__TXLANE5_MASK 0xff00
+#define LM_PCIETXMUX1__TXLANE5__SHIFT 0x8
+#define LM_PCIETXMUX1__TXLANE6_MASK 0xff0000
+#define LM_PCIETXMUX1__TXLANE6__SHIFT 0x10
+#define LM_PCIETXMUX1__TXLANE7_MASK 0xff000000
+#define LM_PCIETXMUX1__TXLANE7__SHIFT 0x18
+#define LM_PCIETXMUX2__TXLANE8_MASK 0xff
+#define LM_PCIETXMUX2__TXLANE8__SHIFT 0x0
+#define LM_PCIETXMUX2__TXLANE9_MASK 0xff00
+#define LM_PCIETXMUX2__TXLANE9__SHIFT 0x8
+#define LM_PCIETXMUX2__TXLANE10_MASK 0xff0000
+#define LM_PCIETXMUX2__TXLANE10__SHIFT 0x10
+#define LM_PCIETXMUX2__TXLANE11_MASK 0xff000000
+#define LM_PCIETXMUX2__TXLANE11__SHIFT 0x18
+#define LM_PCIETXMUX3__TXLANE12_MASK 0xff
+#define LM_PCIETXMUX3__TXLANE12__SHIFT 0x0
+#define LM_PCIETXMUX3__TXLANE13_MASK 0xff00
+#define LM_PCIETXMUX3__TXLANE13__SHIFT 0x8
+#define LM_PCIETXMUX3__TXLANE14_MASK 0xff0000
+#define LM_PCIETXMUX3__TXLANE14__SHIFT 0x10
+#define LM_PCIETXMUX3__TXLANE15_MASK 0xff000000
+#define LM_PCIETXMUX3__TXLANE15__SHIFT 0x18
+#define LM_PCIERXMUX0__RXLANE0_MASK 0xff
+#define LM_PCIERXMUX0__RXLANE0__SHIFT 0x0
+#define LM_PCIERXMUX0__RXLANE1_MASK 0xff00
+#define LM_PCIERXMUX0__RXLANE1__SHIFT 0x8
+#define LM_PCIERXMUX0__RXLANE2_MASK 0xff0000
+#define LM_PCIERXMUX0__RXLANE2__SHIFT 0x10
+#define LM_PCIERXMUX0__RXLANE3_MASK 0xff000000
+#define LM_PCIERXMUX0__RXLANE3__SHIFT 0x18
+#define LM_PCIERXMUX1__RXLANE4_MASK 0xff
+#define LM_PCIERXMUX1__RXLANE4__SHIFT 0x0
+#define LM_PCIERXMUX1__RXLANE5_MASK 0xff00
+#define LM_PCIERXMUX1__RXLANE5__SHIFT 0x8
+#define LM_PCIERXMUX1__RXLANE6_MASK 0xff0000
+#define LM_PCIERXMUX1__RXLANE6__SHIFT 0x10
+#define LM_PCIERXMUX1__RXLANE7_MASK 0xff000000
+#define LM_PCIERXMUX1__RXLANE7__SHIFT 0x18
+#define LM_PCIERXMUX2__RXLANE8_MASK 0xff
+#define LM_PCIERXMUX2__RXLANE8__SHIFT 0x0
+#define LM_PCIERXMUX2__RXLANE9_MASK 0xff00
+#define LM_PCIERXMUX2__RXLANE9__SHIFT 0x8
+#define LM_PCIERXMUX2__RXLANE10_MASK 0xff0000
+#define LM_PCIERXMUX2__RXLANE10__SHIFT 0x10
+#define LM_PCIERXMUX2__RXLANE11_MASK 0xff000000
+#define LM_PCIERXMUX2__RXLANE11__SHIFT 0x18
+#define LM_PCIERXMUX3__RXLANE12_MASK 0xff
+#define LM_PCIERXMUX3__RXLANE12__SHIFT 0x0
+#define LM_PCIERXMUX3__RXLANE13_MASK 0xff00
+#define LM_PCIERXMUX3__RXLANE13__SHIFT 0x8
+#define LM_PCIERXMUX3__RXLANE14_MASK 0xff0000
+#define LM_PCIERXMUX3__RXLANE14__SHIFT 0x10
+#define LM_PCIERXMUX3__RXLANE15_MASK 0xff000000
+#define LM_PCIERXMUX3__RXLANE15__SHIFT 0x18
+#define LM_LANEENABLE__LANE_enable_MASK 0xffff
+#define LM_LANEENABLE__LANE_enable__SHIFT 0x0
+#define LM_PRBSCONTROL__PRBSPCIeSelect_MASK 0xffff
+#define LM_PRBSCONTROL__PRBSPCIeSelect__SHIFT 0x0
+#define LM_PRBSCONTROL__LMLaneDegrade0_MASK 0x10000000
+#define LM_PRBSCONTROL__LMLaneDegrade0__SHIFT 0x1c
+#define LM_PRBSCONTROL__LMLaneDegrade1_MASK 0x20000000
+#define LM_PRBSCONTROL__LMLaneDegrade1__SHIFT 0x1d
+#define LM_PRBSCONTROL__LMLaneDegrade2_MASK 0x40000000
+#define LM_PRBSCONTROL__LMLaneDegrade2__SHIFT 0x1e
+#define LM_PRBSCONTROL__LMLaneDegrade3_MASK 0x80000000
+#define LM_PRBSCONTROL__LMLaneDegrade3__SHIFT 0x1f
+#define LM_POWERCONTROL__LMTxPhyCmd0_MASK 0x7
+#define LM_POWERCONTROL__LMTxPhyCmd0__SHIFT 0x0
+#define LM_POWERCONTROL__LMRxPhyCmd0_MASK 0x38
+#define LM_POWERCONTROL__LMRxPhyCmd0__SHIFT 0x3
+#define LM_POWERCONTROL__LMLinkSpeed0_MASK 0xc0
+#define LM_POWERCONTROL__LMLinkSpeed0__SHIFT 0x6
+#define LM_POWERCONTROL__LMTxPhyCmd1_MASK 0x700
+#define LM_POWERCONTROL__LMTxPhyCmd1__SHIFT 0x8
+#define LM_POWERCONTROL__LMRxPhyCmd1_MASK 0x3800
+#define LM_POWERCONTROL__LMRxPhyCmd1__SHIFT 0xb
+#define LM_POWERCONTROL__LMLinkSpeed1_MASK 0xc000
+#define LM_POWERCONTROL__LMLinkSpeed1__SHIFT 0xe
+#define LM_POWERCONTROL__LMTxPhyCmd2_MASK 0x70000
+#define LM_POWERCONTROL__LMTxPhyCmd2__SHIFT 0x10
+#define LM_POWERCONTROL__LMRxPhyCmd2_MASK 0x380000
+#define LM_POWERCONTROL__LMRxPhyCmd2__SHIFT 0x13
+#define LM_POWERCONTROL__LMLinkSpeed2_MASK 0xc00000
+#define LM_POWERCONTROL__LMLinkSpeed2__SHIFT 0x16
+#define LM_POWERCONTROL__LMTxPhyCmd3_MASK 0x7000000
+#define LM_POWERCONTROL__LMTxPhyCmd3__SHIFT 0x18
+#define LM_POWERCONTROL__LMRxPhyCmd3_MASK 0x38000000
+#define LM_POWERCONTROL__LMRxPhyCmd3__SHIFT 0x1b
+#define LM_POWERCONTROL__LMLinkSpeed3_MASK 0xc0000000
+#define LM_POWERCONTROL__LMLinkSpeed3__SHIFT 0x1e
+#define LM_POWERCONTROL1__LMTxEn0_MASK 0x1
+#define LM_POWERCONTROL1__LMTxEn0__SHIFT 0x0
+#define LM_POWERCONTROL1__LMTxClkEn0_MASK 0x2
+#define LM_POWERCONTROL1__LMTxClkEn0__SHIFT 0x1
+#define LM_POWERCONTROL1__LMTxMargin0_MASK 0x1c
+#define LM_POWERCONTROL1__LMTxMargin0__SHIFT 0x2
+#define LM_POWERCONTROL1__LMSkipBit0_MASK 0x20
+#define LM_POWERCONTROL1__LMSkipBit0__SHIFT 0x5
+#define LM_POWERCONTROL1__LMLaneUnused0_MASK 0x40
+#define LM_POWERCONTROL1__LMLaneUnused0__SHIFT 0x6
+#define LM_POWERCONTROL1__LMTxMarginEn0_MASK 0x80
+#define LM_POWERCONTROL1__LMTxMarginEn0__SHIFT 0x7
+#define LM_POWERCONTROL1__LMDeemph0_MASK 0x100
+#define LM_POWERCONTROL1__LMDeemph0__SHIFT 0x8
+#define LM_POWERCONTROL1__LMTxEn1_MASK 0x200
+#define LM_POWERCONTROL1__LMTxEn1__SHIFT 0x9
+#define LM_POWERCONTROL1__LMTxClkEn1_MASK 0x400
+#define LM_POWERCONTROL1__LMTxClkEn1__SHIFT 0xa
+#define LM_POWERCONTROL1__LMTxMargin1_MASK 0x3800
+#define LM_POWERCONTROL1__LMTxMargin1__SHIFT 0xb
+#define LM_POWERCONTROL1__LMSkipBit1_MASK 0x4000
+#define LM_POWERCONTROL1__LMSkipBit1__SHIFT 0xe
+#define LM_POWERCONTROL1__LMLaneUnused1_MASK 0x8000
+#define LM_POWERCONTROL1__LMLaneUnused1__SHIFT 0xf
+#define LM_POWERCONTROL1__LMTxMarginEn1_MASK 0x10000
+#define LM_POWERCONTROL1__LMTxMarginEn1__SHIFT 0x10
+#define LM_POWERCONTROL1__LMDeemph1_MASK 0x20000
+#define LM_POWERCONTROL1__LMDeemph1__SHIFT 0x11
+#define LM_POWERCONTROL1__LMTxEn2_MASK 0x40000
+#define LM_POWERCONTROL1__LMTxEn2__SHIFT 0x12
+#define LM_POWERCONTROL1__LMTxClkEn2_MASK 0x80000
+#define LM_POWERCONTROL1__LMTxClkEn2__SHIFT 0x13
+#define LM_POWERCONTROL1__LMTxMargin2_MASK 0x700000
+#define LM_POWERCONTROL1__LMTxMargin2__SHIFT 0x14
+#define LM_POWERCONTROL1__LMSkipBit2_MASK 0x800000
+#define LM_POWERCONTROL1__LMSkipBit2__SHIFT 0x17
+#define LM_POWERCONTROL1__LMLaneUnused2_MASK 0x1000000
+#define LM_POWERCONTROL1__LMLaneUnused2__SHIFT 0x18
+#define LM_POWERCONTROL1__LMTxMarginEn2_MASK 0x2000000
+#define LM_POWERCONTROL1__LMTxMarginEn2__SHIFT 0x19
+#define LM_POWERCONTROL1__LMDeemph2_MASK 0x4000000
+#define LM_POWERCONTROL1__LMDeemph2__SHIFT 0x1a
+#define LM_POWERCONTROL1__TxCoeffID0_MASK 0x18000000
+#define LM_POWERCONTROL1__TxCoeffID0__SHIFT 0x1b
+#define LM_POWERCONTROL1__TxCoeffID1_MASK 0x60000000
+#define LM_POWERCONTROL1__TxCoeffID1__SHIFT 0x1d
+#define LM_POWERCONTROL2__LMTxEn3_MASK 0x1
+#define LM_POWERCONTROL2__LMTxEn3__SHIFT 0x0
+#define LM_POWERCONTROL2__LMTxClkEn3_MASK 0x2
+#define LM_POWERCONTROL2__LMTxClkEn3__SHIFT 0x1
+#define LM_POWERCONTROL2__LMTxMargin3_MASK 0x1c
+#define LM_POWERCONTROL2__LMTxMargin3__SHIFT 0x2
+#define LM_POWERCONTROL2__LMSkipBit3_MASK 0x20
+#define LM_POWERCONTROL2__LMSkipBit3__SHIFT 0x5
+#define LM_POWERCONTROL2__LMLaneUnused3_MASK 0x40
+#define LM_POWERCONTROL2__LMLaneUnused3__SHIFT 0x6
+#define LM_POWERCONTROL2__LMTxMarginEn3_MASK 0x80
+#define LM_POWERCONTROL2__LMTxMarginEn3__SHIFT 0x7
+#define LM_POWERCONTROL2__LMDeemph3_MASK 0x100
+#define LM_POWERCONTROL2__LMDeemph3__SHIFT 0x8
+#define LM_POWERCONTROL2__TxCoeffID2_MASK 0x600
+#define LM_POWERCONTROL2__TxCoeffID2__SHIFT 0x9
+#define LM_POWERCONTROL2__TxCoeffID3_MASK 0x1800
+#define LM_POWERCONTROL2__TxCoeffID3__SHIFT 0xb
+#define LM_POWERCONTROL2__TxCoeff0_MASK 0x7e000
+#define LM_POWERCONTROL2__TxCoeff0__SHIFT 0xd
+#define LM_POWERCONTROL2__TxCoeff1_MASK 0x1f80000
+#define LM_POWERCONTROL2__TxCoeff1__SHIFT 0x13
+#define LM_POWERCONTROL2__TxCoeff2_MASK 0x7e000000
+#define LM_POWERCONTROL2__TxCoeff2__SHIFT 0x19
+#define LM_POWERCONTROL3__TxCoeff3_MASK 0x3f
+#define LM_POWERCONTROL3__TxCoeff3__SHIFT 0x0
+#define LM_POWERCONTROL3__RxEqCtl0_MASK 0xfc0
+#define LM_POWERCONTROL3__RxEqCtl0__SHIFT 0x6
+#define LM_POWERCONTROL3__RxEqCtl1_MASK 0x3f000
+#define LM_POWERCONTROL3__RxEqCtl1__SHIFT 0xc
+#define LM_POWERCONTROL3__RxEqCtl2_MASK 0xfc0000
+#define LM_POWERCONTROL3__RxEqCtl2__SHIFT 0x12
+#define LM_POWERCONTROL3__RxEqCtl3_MASK 0x3f000000
+#define LM_POWERCONTROL3__RxEqCtl3__SHIFT 0x18
+#define LM_POWERCONTROL4__LinkNum0_MASK 0x7
+#define LM_POWERCONTROL4__LinkNum0__SHIFT 0x0
+#define LM_POWERCONTROL4__LinkNum1_MASK 0x38
+#define LM_POWERCONTROL4__LinkNum1__SHIFT 0x3
+#define LM_POWERCONTROL4__LinkNum2_MASK 0x1c0
+#define LM_POWERCONTROL4__LinkNum2__SHIFT 0x6
+#define LM_POWERCONTROL4__LinkNum3_MASK 0xe00
+#define LM_POWERCONTROL4__LinkNum3__SHIFT 0x9
+#define LM_POWERCONTROL4__LaneNum0_MASK 0xf000
+#define LM_POWERCONTROL4__LaneNum0__SHIFT 0xc
+#define LM_POWERCONTROL4__LaneNum1_MASK 0xf0000
+#define LM_POWERCONTROL4__LaneNum1__SHIFT 0x10
+#define LM_POWERCONTROL4__LaneNum2_MASK 0xf00000
+#define LM_POWERCONTROL4__LaneNum2__SHIFT 0x14
+#define LM_POWERCONTROL4__LaneNum3_MASK 0xf000000
+#define LM_POWERCONTROL4__LaneNum3__SHIFT 0x18
+#define LM_POWERCONTROL4__SpcMode0_MASK 0x10000000
+#define LM_POWERCONTROL4__SpcMode0__SHIFT 0x1c
+#define LM_POWERCONTROL4__SpcMode1_MASK 0x20000000
+#define LM_POWERCONTROL4__SpcMode1__SHIFT 0x1d
+#define LM_POWERCONTROL4__SpcMode2_MASK 0x40000000
+#define LM_POWERCONTROL4__SpcMode2__SHIFT 0x1e
+#define LM_POWERCONTROL4__SpcMode3_MASK 0x80000000
+#define LM_POWERCONTROL4__SpcMode3__SHIFT 0x1f
+#define PB0_GLB_CTRL_REG0__BACKUP_MASK 0xffff
+#define PB0_GLB_CTRL_REG0__BACKUP__SHIFT 0x0
+#define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x30000
+#define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x10
+#define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x700000
+#define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x14
+#define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x800000
+#define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x17
+#define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x1000000
+#define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x18
+#define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x2000000
+#define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x19
+#define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x4000000
+#define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x1a
+#define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000
+#define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x1e
+#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x1
+#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x0
+#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x7e
+#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x1
+#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x80
+#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x7
+#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x3f00
+#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x8
+#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x4000
+#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0xe
+#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x3f8000
+#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0xf
+#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x400000
+#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x16
+#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000
+#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x17
+#define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000
+#define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x1e
+#define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000
+#define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x1f
+#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x1
+#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x0
+#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0xfe
+#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x1
+#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x100
+#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x8
+#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0xfe00
+#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x9
+#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x10000
+#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x10
+#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0xfe0000
+#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x11
+#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x1000000
+#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x18
+#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000
+#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x19
+#define PB0_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x1f
+#define PB0_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x0
+#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x60
+#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x5
+#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x180
+#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x7
+#define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x600
+#define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x9
+#define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x800
+#define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0xb
+#define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x1000
+#define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0xc
+#define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x1c000
+#define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0xe
+#define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x1c0000
+#define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x12
+#define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x200000
+#define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x15
+#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x400000
+#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x16
+#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x7800000
+#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x17
+#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x8000000
+#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x1b
+#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000
+#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x1c
+#define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000
+#define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x1f
+#define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0xffff
+#define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x0
+#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x30000
+#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x10
+#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x40000
+#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x12
+#define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x3c00000
+#define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x16
+#define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x4000000
+#define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x1a
+#define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x8000000
+#define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x1b
+#define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000
+#define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x1c
+#define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0xff
+#define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x0
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3_MASK 0x1
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3__SHIFT 0x0
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7_MASK 0x2
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7__SHIFT 0x1
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11_MASK 0x4
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11__SHIFT 0x2
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15_MASK 0x8
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15__SHIFT 0x3
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT_MASK 0x10
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT__SHIFT 0x4
+#define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0xf00
+#define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x8
+#define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0xf000
+#define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0xc
+#define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0xf0000
+#define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x10
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x100000
+#define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x14
+#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3_MASK 0x1
+#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3__SHIFT 0x0
+#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3_MASK 0x2
+#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3__SHIFT 0x1
+#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3_MASK 0x4
+#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3__SHIFT 0x2
+#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x1000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0xc
+#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x2000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0xd
+#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x4000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0xe
+#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x8000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0xf
+#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0_MASK 0x30000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0__SHIFT 0x10
+#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0xc0000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x12
+#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1_MASK 0x300000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1__SHIFT 0x14
+#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0xc00000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x16
+#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2_MASK 0x3000000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2__SHIFT 0x18
+#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0xc000000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x1a
+#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3_MASK 0x30000000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3__SHIFT 0x1c
+#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000
+#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x1e
+#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7_MASK 0x1
+#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7__SHIFT 0x0
+#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7_MASK 0x2
+#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7__SHIFT 0x1
+#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7_MASK 0x4
+#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7__SHIFT 0x2
+#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x1000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0xc
+#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x2000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0xd
+#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x4000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0xe
+#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x8000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0xf
+#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4_MASK 0x30000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4__SHIFT 0x10
+#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0xc0000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x12
+#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5_MASK 0x300000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5__SHIFT 0x14
+#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0xc00000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x16
+#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6_MASK 0x3000000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6__SHIFT 0x18
+#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0xc000000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x1a
+#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7_MASK 0x30000000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7__SHIFT 0x1c
+#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000
+#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x1e
+#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11_MASK 0x1
+#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11__SHIFT 0x0
+#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11_MASK 0x2
+#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11__SHIFT 0x1
+#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11_MASK 0x4
+#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11__SHIFT 0x2
+#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x1000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0xc
+#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x2000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0xd
+#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x4000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0xe
+#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x8000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0xf
+#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8_MASK 0x30000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8__SHIFT 0x10
+#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0xc0000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x12
+#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9_MASK 0x300000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9__SHIFT 0x14
+#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0xc00000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x16
+#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10_MASK 0x3000000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10__SHIFT 0x18
+#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0xc000000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x1a
+#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11_MASK 0x30000000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11__SHIFT 0x1c
+#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000
+#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x1e
+#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15_MASK 0x1
+#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15__SHIFT 0x0
+#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15_MASK 0x2
+#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15__SHIFT 0x1
+#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15_MASK 0x4
+#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15__SHIFT 0x2
+#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x1000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0xc
+#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x2000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0xd
+#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x4000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0xe
+#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x8000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0xf
+#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12_MASK 0x30000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12__SHIFT 0x10
+#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0xc0000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x12
+#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13_MASK 0x300000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13__SHIFT 0x14
+#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0xc00000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x16
+#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14_MASK 0x3000000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14__SHIFT 0x18
+#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0xc000000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x1a
+#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15_MASK 0x30000000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15__SHIFT 0x1c
+#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000
+#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x1e
+#define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0xffff
+#define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x0
+#define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000
+#define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x10
+#define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x1
+#define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x0
+#define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x2
+#define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x1
+#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x4
+#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x2
+#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x8
+#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x3
+#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x8000
+#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0xf
+#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000
+#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x10
+#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x1
+#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x0
+#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x2
+#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x1
+#define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN_MASK 0x4
+#define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN__SHIFT 0x2
+#define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL_MASK 0x8
+#define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL__SHIFT 0x3
+#define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN_MASK 0x10
+#define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN__SHIFT 0x4
+#define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL_MASK 0x20
+#define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL__SHIFT 0x5
+#define PB0_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define PB0_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define PB0_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define PB0_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define PB0_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define PB0_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define PB0_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define PB0_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define PB0_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define PB0_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define PB0_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define PB0_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define PB0_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define PB0_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define PB0_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define PB0_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define PB0_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define PB0_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define PB0_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define PB0_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define PB0_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define PB0_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define PB0_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define PB0_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define PB0_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define PB0_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define PB0_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define PB0_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define PB0_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define PB0_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define PB0_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define PB0_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define PB0_HW_DEBUG__HW_16_DEBUG_MASK 0x10000
+#define PB0_HW_DEBUG__HW_16_DEBUG__SHIFT 0x10
+#define PB0_HW_DEBUG__HW_17_DEBUG_MASK 0x20000
+#define PB0_HW_DEBUG__HW_17_DEBUG__SHIFT 0x11
+#define PB0_HW_DEBUG__HW_18_DEBUG_MASK 0x40000
+#define PB0_HW_DEBUG__HW_18_DEBUG__SHIFT 0x12
+#define PB0_HW_DEBUG__HW_19_DEBUG_MASK 0x80000
+#define PB0_HW_DEBUG__HW_19_DEBUG__SHIFT 0x13
+#define PB0_HW_DEBUG__HW_20_DEBUG_MASK 0x100000
+#define PB0_HW_DEBUG__HW_20_DEBUG__SHIFT 0x14
+#define PB0_HW_DEBUG__HW_21_DEBUG_MASK 0x200000
+#define PB0_HW_DEBUG__HW_21_DEBUG__SHIFT 0x15
+#define PB0_HW_DEBUG__HW_22_DEBUG_MASK 0x400000
+#define PB0_HW_DEBUG__HW_22_DEBUG__SHIFT 0x16
+#define PB0_HW_DEBUG__HW_23_DEBUG_MASK 0x800000
+#define PB0_HW_DEBUG__HW_23_DEBUG__SHIFT 0x17
+#define PB0_HW_DEBUG__HW_24_DEBUG_MASK 0x1000000
+#define PB0_HW_DEBUG__HW_24_DEBUG__SHIFT 0x18
+#define PB0_HW_DEBUG__HW_25_DEBUG_MASK 0x2000000
+#define PB0_HW_DEBUG__HW_25_DEBUG__SHIFT 0x19
+#define PB0_HW_DEBUG__HW_26_DEBUG_MASK 0x4000000
+#define PB0_HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a
+#define PB0_HW_DEBUG__HW_27_DEBUG_MASK 0x8000000
+#define PB0_HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b
+#define PB0_HW_DEBUG__HW_28_DEBUG_MASK 0x10000000
+#define PB0_HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c
+#define PB0_HW_DEBUG__HW_29_DEBUG_MASK 0x20000000
+#define PB0_HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d
+#define PB0_HW_DEBUG__HW_30_DEBUG_MASK 0x40000000
+#define PB0_HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e
+#define PB0_HW_DEBUG__HW_31_DEBUG_MASK 0x80000000
+#define PB0_HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f
+#define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK 0x2
+#define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START__SHIFT 0x1
+#define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL_MASK 0x4
+#define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT 0x2
+#define PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS_MASK 0x8
+#define PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS__SHIFT 0x3
+#define PB0_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON_MASK 0x10
+#define PB0_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON__SHIFT 0x4
+#define PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH_MASK 0x60
+#define PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH__SHIFT 0x5
+#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL_MASK 0xf80
+#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL__SHIFT 0x7
+#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF_MASK 0x1000
+#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF__SHIFT 0xc
+#define PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0__MASK 0x2000
+#define PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0___SHIFT 0xd
+#define PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD_MASK 0x4000
+#define PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD__SHIFT 0xe
+#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x8000
+#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0xf
+#define PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE_MASK 0xf0000
+#define PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE__SHIFT 0x10
+#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE_MASK 0x100000
+#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE__SHIFT 0x14
+#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL_MASK 0x1e00000
+#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x15
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN_MASK 0x1e
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN__SHIFT 0x1
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL_MASK 0x1e0
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL__SHIFT 0x5
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN_MASK 0x3e00
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN__SHIFT 0x9
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL_MASK 0x7c000
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL__SHIFT 0xe
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN_MASK 0x780000
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN__SHIFT 0x13
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL_MASK 0x7800000
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL__SHIFT 0x17
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN_MASK 0x8000000
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN__SHIFT 0x1b
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL_MASK 0x10000000
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL__SHIFT 0x1c
+#define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1__MASK 0x20000000
+#define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT 0x1d
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN_MASK 0x40000000
+#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN__SHIFT 0x1e
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN_MASK 0x1e
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN__SHIFT 0x1
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE_MASK 0x20
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE__SHIFT 0x5
+#define PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN_MASK 0x40
+#define PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x6
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS_MASK 0x80
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS__SHIFT 0x7
+#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL_MASK 0x300
+#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x8
+#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL_MASK 0xc00
+#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL__SHIFT 0xa
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME_MASK 0xf000
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME__SHIFT 0xc
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME_MASK 0xf0000
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME__SHIFT 0x10
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME_MASK 0xf00000
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME__SHIFT 0x14
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME_MASK 0xf000000
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME__SHIFT 0x18
+#define PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL_MASK 0x70000000
+#define PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL__SHIFT 0x1c
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE_MASK 0x80000000
+#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE__SHIFT 0x1f
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK 0x2
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ__SHIFT 0x1
+#define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG_MASK 0x1c
+#define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT 0x2
+#define PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL_MASK 0x60
+#define PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL__SHIFT 0x5
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS_MASK 0x80
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS__SHIFT 0x7
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL_MASK 0x700
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL__SHIFT 0x8
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN_MASK 0x7800
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN__SHIFT 0xb
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE_MASK 0x1ff8000
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE__SHIFT 0xf
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME_MASK 0x1e000000
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT 0x19
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN_MASK 0x60000000
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN__SHIFT 0x1d
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS_MASK 0x80000000
+#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS__SHIFT 0x1f
+#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL_MASK 0xe
+#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL__SHIFT 0x1
+#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL_MASK 0x1ff0
+#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL__SHIFT 0x4
+#define PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF_MASK 0x2000
+#define PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF__SHIFT 0xd
+#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS_MASK 0x8000
+#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS__SHIFT 0xf
+#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL_MASK 0xff0000
+#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL__SHIFT 0x10
+#define PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL_MASK 0x1000000
+#define PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL__SHIFT 0x18
+#define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK 0x2
+#define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN__SHIFT 0x1
+#define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING_MASK 0x4
+#define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT 0x2
+#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE_MASK 0x6
+#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE__SHIFT 0x1
+#define PB0_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE_MASK 0x18
+#define PB0_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE__SHIFT 0x3
+#define PB0_STRAP_GLB_REG1__STRAP_RX_EI_FILTER_MASK 0x60
+#define PB0_STRAP_GLB_REG1__STRAP_RX_EI_FILTER__SHIFT 0x5
+#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY_MASK 0x80
+#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY__SHIFT 0x7
+#define PB0_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE_MASK 0x300
+#define PB0_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE__SHIFT 0x8
+#define PB0_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG_MASK 0x400
+#define PB0_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG__SHIFT 0xa
+#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT_MASK 0x1800
+#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT__SHIFT 0xb
+#define PB0_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME_MASK 0x1c
+#define PB0_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME__SHIFT 0x2
+#define PB0_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME_MASK 0x60
+#define PB0_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME__SHIFT 0x5
+#define PB0_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME_MASK 0x180
+#define PB0_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME__SHIFT 0x7
+#define PB0_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME_MASK 0x600
+#define PB0_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME__SHIFT 0x9
+#define PB0_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME_MASK 0x1800
+#define PB0_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME__SHIFT 0xb
+#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS0_MASK 0x10000000
+#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS0__SHIFT 0x1c
+#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS1_MASK 0x20000000
+#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS1__SHIFT 0x1d
+#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR_MASK 0xc0000000
+#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR__SHIFT 0x1e
+#define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x3f
+#define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x0
+#define PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR_MASK 0x80
+#define PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR__SHIFT 0x7
+#define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0xf00
+#define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x8
+#define PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN_MASK 0x100000
+#define PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN__SHIFT 0x14
+#define PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY_MASK 0x200000
+#define PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY__SHIFT 0x15
+#define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x400000
+#define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x16
+#define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x800000
+#define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x17
+#define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000
+#define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x18
+#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0xff
+#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x0
+#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x100
+#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x8
+#define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x10000
+#define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x10
+#define PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS_MASK 0xe0000
+#define PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS__SHIFT 0x11
+#define PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME_MASK 0xf00000
+#define PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME__SHIFT 0x14
+#define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0xffff
+#define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x0
+#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x1
+#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x0
+#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x3e
+#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x1
+#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR_MASK 0xff
+#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR__SHIFT 0x0
+#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR_MASK 0xff00
+#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR__SHIFT 0x8
+#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED_MASK 0x10000
+#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED__SHIFT 0x10
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x1
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x0
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x2
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x1
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x4
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x2
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x8
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x3
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x10
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x4
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x20
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x5
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x40
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x6
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x80
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x7
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x100
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x8
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x200
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x9
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x400
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0xa
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x800
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0xb
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x1000
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0xc
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x2000
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0xd
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x4000
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0xe
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN_MASK 0x8000
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN__SHIFT 0xf
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN_MASK 0x10000
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN__SHIFT 0x10
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN_MASK 0x20000
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN__SHIFT 0x11
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN_MASK 0x40000
+#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN__SHIFT 0x12
+#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x3
+#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x0
+#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x4
+#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x2
+#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x8
+#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x3
+#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x7f0
+#define PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x4
+#define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x800
+#define PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0xb
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0xff
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x100
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x8
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0xe00
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x9
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x1000
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0xc
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x2000
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0xd
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x4000
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0xe
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0xfff8000
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0xf
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x1c
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x1e
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000
+#define PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x1f
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x1f
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x0
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x20
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x5
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0xc0
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x6
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x100
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x8
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x200
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x9
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x400
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0xa
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x800
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0xb
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x1000
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0xc
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x2000
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0xd
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x4000
+#define PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0xe
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x380000
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x13
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x400000
+#define PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x16
+#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
+#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
+#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
+#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1
+#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x70
+#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x4
+#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ_MASK 0x300
+#define PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ__SHIFT 0x8
+#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
+#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
+#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
+#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1
+#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x70
+#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x4
+#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ_MASK 0x300
+#define PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ__SHIFT 0x8
+#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
+#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
+#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
+#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1
+#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x70
+#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x4
+#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ_MASK 0x300
+#define PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ__SHIFT 0x8
+#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
+#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
+#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
+#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1
+#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x70
+#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x4
+#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ_MASK 0x300
+#define PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ__SHIFT 0x8
+#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x3
+#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x0
+#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x4
+#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x2
+#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x8
+#define PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x3
+#define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x10
+#define PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x4
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x7
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x8
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x3
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x70
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x4
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x80
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x7
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x100
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x8
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x200
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x9
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x3fc00
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0xa
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x40000
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x12
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0xff80000
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x13
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x1c
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x1d
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000
+#define PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x1f
+#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x7
+#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x0
+#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x8
+#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x3
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x10
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x4
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x20
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x5
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x40
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x6
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x80
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x7
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x100
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x8
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x200
+#define PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x9
+#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x3c000
+#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0xe
+#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x40000
+#define PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x12
+#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
+#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
+#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x70
+#define PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x4
+#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
+#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
+#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x70
+#define PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x4
+#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
+#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
+#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x70
+#define PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x4
+#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
+#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
+#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x70
+#define PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x4
+#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x3ff
+#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x0
+#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0xffc00
+#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0xa
+#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000
+#define PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x14
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0xf
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x0
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0xf0
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x4
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0xf00
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x8
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0xf000
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0xc
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0xf0000
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x10
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0xf00000
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x14
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x1000000
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x18
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x2000000
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x19
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x4000000
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x1a
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x8000000
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x1b
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x1c
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000
+#define PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x1d
+#define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000
+#define PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x1e
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0xf000
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0xc
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0xf0000
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x10
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0xf00000
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x14
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x3000000
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x18
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0xc000000
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x1a
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000
+#define PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x1c
+#define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000
+#define PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x1e
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x1
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x0
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x2
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x1
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x4
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x2
+#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1_MASK 0x18
+#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1__SHIFT 0x3
+#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2_MASK 0x60
+#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2__SHIFT 0x5
+#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3_MASK 0x180
+#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3__SHIFT 0x7
+#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE_MASK 0xe00
+#define PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE__SHIFT 0x9
+#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1_MASK 0x3000
+#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1__SHIFT 0xc
+#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2_MASK 0xc000
+#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2__SHIFT 0xe
+#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3_MASK 0x30000
+#define PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3__SHIFT 0x10
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0xf00000
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x14
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0xf000000
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x18
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000
+#define PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x1c
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x7
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x0
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x38
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x3
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x1c0
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x6
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0xe00
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x9
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x7000
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0xc
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x38000
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0xf
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0xf00000
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x14
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0xf000000
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x18
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000
+#define PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x1c
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x1f
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x0
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x3e0
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x5
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x7c00
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0xa
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x8000
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0xf
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x10000
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x10
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x20000
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x11
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x40000
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x12
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x80000
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x13
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x100000
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x14
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x8000000
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x1b
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x1c
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000
+#define PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x1d
+#define PB0_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE_MASK 0x80000000
+#define PB0_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE__SHIFT 0x1f
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0xf
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x0
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0xf0
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x4
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0xf00
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x8
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0xf000
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0xc
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0xf0000
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x10
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0xf00000
+#define PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x14
+#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000000
+#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x18
+#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x4000000
+#define PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x1a
+#define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x8000000
+#define PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x1b
+#define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS_MASK 0x10000000
+#define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__SHIFT 0x1c
+#define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF_MASK 0x20000000
+#define PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF__SHIFT 0x1d
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0xf
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x0
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0xf0
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x4
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0xf00
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x8
+#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000
+#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0xc
+#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x2000
+#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0xd
+#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK_MASK 0x4000
+#define PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK__SHIFT 0xe
+#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3_MASK 0x10000
+#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3__SHIFT 0x10
+#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2_MASK 0x20000
+#define PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2__SHIFT 0x11
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x1c0000
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x12
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0xe00000
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x15
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x7000000
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x18
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x8000000
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x1b
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x1c
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000
+#define PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x1d
+#define PB0_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME_MASK 0x3
+#define PB0_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME__SHIFT 0x0
+#define PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME_MASK 0xc
+#define PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT 0x2
+#define PB0_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN_MASK 0x10
+#define PB0_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN__SHIFT 0x4
+#define PB0_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY_MASK 0x20
+#define PB0_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY__SHIFT 0x5
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3_MASK 0x1
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3__SHIFT 0x0
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7_MASK 0x2
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7__SHIFT 0x1
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11_MASK 0x4
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11__SHIFT 0x2
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15_MASK 0x8
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15__SHIFT 0x3
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3_MASK 0x10
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3__SHIFT 0x4
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7_MASK 0x20
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7__SHIFT 0x5
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11_MASK 0x40
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11__SHIFT 0x6
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15_MASK 0x80
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15__SHIFT 0x7
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3_MASK 0x100
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3__SHIFT 0x8
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7_MASK 0x200
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7__SHIFT 0x9
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11_MASK 0x400
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11__SHIFT 0xa
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15_MASK 0x800
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15__SHIFT 0xb
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3_MASK 0x1000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3__SHIFT 0xc
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7_MASK 0x2000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7__SHIFT 0xd
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11_MASK 0x4000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11__SHIFT 0xe
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15_MASK 0x8000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15__SHIFT 0xf
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3_MASK 0x10000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3__SHIFT 0x10
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7_MASK 0x20000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7__SHIFT 0x11
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11_MASK 0x40000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11__SHIFT 0x12
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15_MASK 0x80000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15__SHIFT 0x13
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3_MASK 0x100000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3__SHIFT 0x14
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7_MASK 0x200000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7__SHIFT 0x15
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11_MASK 0x400000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11__SHIFT 0x16
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15_MASK 0x800000
+#define PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15__SHIFT 0x17
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x1
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x0
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x2
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x1
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x4
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x2
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x8
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x3
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0xc0
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x6
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x100
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x8
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x200
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x9
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x400
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0xa
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x800
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0xb
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x1000
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xc
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x2000
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0xd
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x4000
+#define PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0xe
+#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x8000
+#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0xf
+#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x10000
+#define PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x10
+#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x20000
+#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x11
+#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x40000
+#define PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x12
+#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x80000
+#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x13
+#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x100000
+#define PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x14
+#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x200000
+#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x15
+#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x400000
+#define PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x16
+#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000
+#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x1c
+#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000
+#define PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x1d
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x1e
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000
+#define PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x1f
+#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x1
+#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x0
+#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x2
+#define PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x1
+#define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0xff
+#define PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x0
+#define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0xc00
+#define PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0xa
+#define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x1000
+#define PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0xc
+#define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x2000
+#define PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0xd
+#define PB0_RX_LANE0_CTRL_REG0__RX_TERM_EN_0_MASK 0x4000
+#define PB0_RX_LANE0_CTRL_REG0__RX_TERM_EN_0__SHIFT 0xe
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x7
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x0
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x8
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x3
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0_MASK 0x40
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0__SHIFT 0x6
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x80
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x7
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x100
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x8
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x200
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x9
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0_MASK 0x3fc00
+#define PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0__SHIFT 0xa
+#define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0xff
+#define PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x0
+#define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0xc00
+#define PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0xa
+#define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x1000
+#define PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0xc
+#define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x2000
+#define PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0xd
+#define PB0_RX_LANE1_CTRL_REG0__RX_TERM_EN_1_MASK 0x4000
+#define PB0_RX_LANE1_CTRL_REG0__RX_TERM_EN_1__SHIFT 0xe
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x7
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x0
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x8
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x3
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1_MASK 0x40
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1__SHIFT 0x6
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x80
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x7
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x100
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x8
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x200
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x9
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1_MASK 0x3fc00
+#define PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1__SHIFT 0xa
+#define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0xff
+#define PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x0
+#define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0xc00
+#define PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0xa
+#define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x1000
+#define PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0xc
+#define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x2000
+#define PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0xd
+#define PB0_RX_LANE2_CTRL_REG0__RX_TERM_EN_2_MASK 0x4000
+#define PB0_RX_LANE2_CTRL_REG0__RX_TERM_EN_2__SHIFT 0xe
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x7
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x0
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x8
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x3
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2_MASK 0x40
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2__SHIFT 0x6
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x80
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x7
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x100
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x8
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x200
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x9
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2_MASK 0x3fc00
+#define PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2__SHIFT 0xa
+#define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0xff
+#define PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x0
+#define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0xc00
+#define PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0xa
+#define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x1000
+#define PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0xc
+#define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x2000
+#define PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0xd
+#define PB0_RX_LANE3_CTRL_REG0__RX_TERM_EN_3_MASK 0x4000
+#define PB0_RX_LANE3_CTRL_REG0__RX_TERM_EN_3__SHIFT 0xe
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x7
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x0
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x8
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x3
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3_MASK 0x40
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3__SHIFT 0x6
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x80
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x7
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x100
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x8
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x200
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x9
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3_MASK 0x3fc00
+#define PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3__SHIFT 0xa
+#define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0xff
+#define PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x0
+#define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0xc00
+#define PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0xa
+#define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x1000
+#define PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0xc
+#define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x2000
+#define PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0xd
+#define PB0_RX_LANE4_CTRL_REG0__RX_TERM_EN_4_MASK 0x4000
+#define PB0_RX_LANE4_CTRL_REG0__RX_TERM_EN_4__SHIFT 0xe
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x7
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x0
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x8
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x3
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4_MASK 0x40
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4__SHIFT 0x6
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x80
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x7
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x100
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x8
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x200
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x9
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4_MASK 0x3fc00
+#define PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4__SHIFT 0xa
+#define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0xff
+#define PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x0
+#define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0xc00
+#define PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0xa
+#define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x1000
+#define PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0xc
+#define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x2000
+#define PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0xd
+#define PB0_RX_LANE5_CTRL_REG0__RX_TERM_EN_5_MASK 0x4000
+#define PB0_RX_LANE5_CTRL_REG0__RX_TERM_EN_5__SHIFT 0xe
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x7
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x0
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x8
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x3
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5_MASK 0x40
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5__SHIFT 0x6
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x80
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x7
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x100
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x8
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x200
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x9
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5_MASK 0x3fc00
+#define PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5__SHIFT 0xa
+#define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0xff
+#define PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x0
+#define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0xc00
+#define PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0xa
+#define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x1000
+#define PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0xc
+#define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x2000
+#define PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0xd
+#define PB0_RX_LANE6_CTRL_REG0__RX_TERM_EN_6_MASK 0x4000
+#define PB0_RX_LANE6_CTRL_REG0__RX_TERM_EN_6__SHIFT 0xe
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x7
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x0
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x8
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x3
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6_MASK 0x40
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6__SHIFT 0x6
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x80
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x7
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x100
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x8
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x200
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x9
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6_MASK 0x3fc00
+#define PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6__SHIFT 0xa
+#define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0xff
+#define PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x0
+#define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0xc00
+#define PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0xa
+#define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x1000
+#define PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0xc
+#define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x2000
+#define PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0xd
+#define PB0_RX_LANE7_CTRL_REG0__RX_TERM_EN_7_MASK 0x4000
+#define PB0_RX_LANE7_CTRL_REG0__RX_TERM_EN_7__SHIFT 0xe
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x7
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x0
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x8
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x3
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7_MASK 0x40
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7__SHIFT 0x6
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x80
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x7
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x100
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x8
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x200
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x9
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7_MASK 0x3fc00
+#define PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7__SHIFT 0xa
+#define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0xff
+#define PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x0
+#define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0xc00
+#define PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0xa
+#define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x1000
+#define PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0xc
+#define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x2000
+#define PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0xd
+#define PB0_RX_LANE8_CTRL_REG0__RX_TERM_EN_8_MASK 0x4000
+#define PB0_RX_LANE8_CTRL_REG0__RX_TERM_EN_8__SHIFT 0xe
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x7
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x0
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x8
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x3
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8_MASK 0x40
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8__SHIFT 0x6
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x80
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x7
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x100
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x8
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x200
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x9
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8_MASK 0x3fc00
+#define PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8__SHIFT 0xa
+#define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0xff
+#define PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x0
+#define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0xc00
+#define PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0xa
+#define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x1000
+#define PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0xc
+#define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x2000
+#define PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0xd
+#define PB0_RX_LANE9_CTRL_REG0__RX_TERM_EN_9_MASK 0x4000
+#define PB0_RX_LANE9_CTRL_REG0__RX_TERM_EN_9__SHIFT 0xe
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x7
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x0
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x8
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x3
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9_MASK 0x40
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9__SHIFT 0x6
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x80
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x7
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x100
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x8
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x200
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x9
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9_MASK 0x3fc00
+#define PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9__SHIFT 0xa
+#define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0xff
+#define PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x0
+#define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0xc00
+#define PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0xa
+#define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x1000
+#define PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0xc
+#define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x2000
+#define PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0xd
+#define PB0_RX_LANE10_CTRL_REG0__RX_TERM_EN_10_MASK 0x4000
+#define PB0_RX_LANE10_CTRL_REG0__RX_TERM_EN_10__SHIFT 0xe
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x7
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x0
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x8
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x3
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10_MASK 0x40
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10__SHIFT 0x6
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x80
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x7
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x100
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x8
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x200
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x9
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10_MASK 0x3fc00
+#define PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10__SHIFT 0xa
+#define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0xff
+#define PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x0
+#define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0xc00
+#define PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0xa
+#define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x1000
+#define PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0xc
+#define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x2000
+#define PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0xd
+#define PB0_RX_LANE11_CTRL_REG0__RX_TERM_EN_11_MASK 0x4000
+#define PB0_RX_LANE11_CTRL_REG0__RX_TERM_EN_11__SHIFT 0xe
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x7
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x0
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x8
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x3
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11_MASK 0x40
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11__SHIFT 0x6
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x80
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x7
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x100
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x8
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x200
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x9
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11_MASK 0x3fc00
+#define PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11__SHIFT 0xa
+#define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0xff
+#define PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x0
+#define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0xc00
+#define PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0xa
+#define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x1000
+#define PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0xc
+#define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x2000
+#define PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0xd
+#define PB0_RX_LANE12_CTRL_REG0__RX_TERM_EN_12_MASK 0x4000
+#define PB0_RX_LANE12_CTRL_REG0__RX_TERM_EN_12__SHIFT 0xe
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x7
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x0
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x8
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x3
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12_MASK 0x40
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12__SHIFT 0x6
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x80
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x7
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x100
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x8
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x200
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x9
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12_MASK 0x3fc00
+#define PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12__SHIFT 0xa
+#define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0xff
+#define PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x0
+#define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0xc00
+#define PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0xa
+#define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x1000
+#define PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0xc
+#define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x2000
+#define PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0xd
+#define PB0_RX_LANE13_CTRL_REG0__RX_TERM_EN_13_MASK 0x4000
+#define PB0_RX_LANE13_CTRL_REG0__RX_TERM_EN_13__SHIFT 0xe
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x7
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x0
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x8
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x3
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13_MASK 0x40
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13__SHIFT 0x6
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x80
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x7
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x100
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x8
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x200
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x9
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13_MASK 0x3fc00
+#define PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13__SHIFT 0xa
+#define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0xff
+#define PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x0
+#define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0xc00
+#define PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0xa
+#define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x1000
+#define PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0xc
+#define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x2000
+#define PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0xd
+#define PB0_RX_LANE14_CTRL_REG0__RX_TERM_EN_14_MASK 0x4000
+#define PB0_RX_LANE14_CTRL_REG0__RX_TERM_EN_14__SHIFT 0xe
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x7
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x0
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x8
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x3
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14_MASK 0x40
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14__SHIFT 0x6
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x80
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x7
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x100
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x8
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x200
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x9
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14_MASK 0x3fc00
+#define PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14__SHIFT 0xa
+#define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0xff
+#define PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x0
+#define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0xc00
+#define PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0xa
+#define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x1000
+#define PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0xc
+#define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x2000
+#define PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0xd
+#define PB0_RX_LANE15_CTRL_REG0__RX_TERM_EN_15_MASK 0x4000
+#define PB0_RX_LANE15_CTRL_REG0__RX_TERM_EN_15__SHIFT 0xe
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x7
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x0
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x8
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x3
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15_MASK 0x40
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15__SHIFT 0x6
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x80
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x7
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x100
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x8
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x200
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x9
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15_MASK 0x3fc00
+#define PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15__SHIFT 0xa
+#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x7
+#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x0
+#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x38
+#define PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x3
+#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x700
+#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x8
+#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x3800
+#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0xb
+#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x1c000
+#define PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0xe
+#define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x60000
+#define PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x11
+#define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x80000
+#define PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x13
+#define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x100000
+#define PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x14
+#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x200000
+#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x15
+#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x400000
+#define PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x16
+#define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x800000
+#define PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x17
+#define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4_MASK 0x1000000
+#define PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4__SHIFT 0x18
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x1
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x0
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x2
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x1
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x4
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x2
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x8
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x3
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x10
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x4
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x20
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x5
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x40
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x6
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x80
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x7
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x100
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x8
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x200
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x9
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x400
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0xa
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x800
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0xb
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x1000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0xc
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x2000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0xd
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x4000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0xe
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x8000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0xf
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x10000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x10
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x20000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x11
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x40000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x12
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x80000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x13
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x100000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x14
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x200000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x15
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x400000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x16
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x800000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x17
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x1000000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x18
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x2000000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x19
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x4000000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x1a
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x8000000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x1b
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x1c
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x1d
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000
+#define PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x1e
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3_MASK 0x1
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3__SHIFT 0x0
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7_MASK 0x2
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7__SHIFT 0x1
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11_MASK 0x4
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11__SHIFT 0x2
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15_MASK 0x8
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15__SHIFT 0x3
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3_MASK 0x100
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3__SHIFT 0x8
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7_MASK 0x200
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7__SHIFT 0x9
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11_MASK 0x400
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11__SHIFT 0xa
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15_MASK 0x800
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15__SHIFT 0xb
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3_MASK 0x1000
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3__SHIFT 0xc
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7_MASK 0x2000
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7__SHIFT 0xd
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11_MASK 0x4000
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11__SHIFT 0xe
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15_MASK 0x8000
+#define PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15__SHIFT 0xf
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x1
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x0
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x2
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x1
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x4
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x2
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x8
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x3
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x10
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x4
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x20
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x5
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x40
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x6
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x80
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x7
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x100
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x8
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x200
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x9
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x400
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0xa
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x800
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0xb
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x1000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0xc
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x2000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0xd
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x4000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0xe
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x8000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0xf
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x10000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x10
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x20000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x11
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x40000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x12
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x80000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x13
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x100000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x14
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x200000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x15
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x400000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x16
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x800000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x17
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x1000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x18
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x2000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x19
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x4000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x1a
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x8000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x1b
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x1c
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x1d
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x1e
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x1f
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x1
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x0
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x2
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x1
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x4
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x2
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x8
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x3
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x10
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x4
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x20
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x5
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x40
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x6
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x80
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x7
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x100
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x8
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x200
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x9
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x400
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0xa
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x800
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0xb
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x1000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0xc
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x2000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0xd
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x4000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0xe
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x8000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0xf
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x10000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x10
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x20000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x11
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x40000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x12
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x80000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x13
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x100000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x14
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x200000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x15
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x400000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x16
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x800000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x17
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x1000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x18
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x2000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x19
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x4000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x1a
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x8000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x1b
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x1c
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x1d
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x1e
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x1f
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x1
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x0
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x2
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x1
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x4
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x2
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x8
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x3
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x10
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x4
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x20
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x5
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x40
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x6
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x80
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x7
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x100
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x8
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x200
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x9
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x400
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0xa
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x800
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0xb
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x1000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0xc
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x2000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0xd
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x4000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0xe
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x8000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0xf
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x10000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x10
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x20000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x11
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x40000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x12
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x80000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x13
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x100000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x14
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x200000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x15
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x400000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x16
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x800000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x17
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x1000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x18
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x2000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x19
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x4000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x1a
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x8000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x1b
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x1c
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x1d
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x1e
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x1f
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x1
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x0
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x2
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x1
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x4
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x2
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x8
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x3
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x10
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x4
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x20
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x5
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x40
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x6
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x80
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x7
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x100
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x8
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x200
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x9
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x400
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0xa
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x800
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0xb
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x1000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0xc
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x2000
+#define PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0xd
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x7
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x0
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x8
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x3
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0xf0
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x4
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x100
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x8
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1e00
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x9
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x2000
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0xd
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x7c000
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0xe
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x80000
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x13
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1f00000
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x14
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x2000000
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x19
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x1a
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000
+#define PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x1e
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0xf
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x0
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x10
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x4
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x20
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x5
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x40
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x6
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x80
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x7
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x100
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x8
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x200
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x9
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x400
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xa
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x800
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0xb
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x1000
+#define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0xc
+#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x2000
+#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0xd
+#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x4000
+#define PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0xe
+#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x1ff8000
+#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0xf
+#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x2000000
+#define PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x19
+#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x4000000
+#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x1a
+#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x8000000
+#define PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x1b
+#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000
+#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x1c
+#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000
+#define PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x1d
+#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000
+#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x1e
+#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000
+#define PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x1f
+#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x1
+#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x0
+#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x2
+#define PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x1
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x4
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x2
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x8
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x3
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x10
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x4
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x20
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x5
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x40
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x6
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x80
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x7
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x100
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x8
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x200
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x9
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x400
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0xa
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x800
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0xb
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0xf000
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0xc
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0000
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x10
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x1f00000
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x14
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000
+#define PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x19
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0xf
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x0
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x4
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x100
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x8
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x200
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x9
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x3c00
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0xa
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x3c000
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0xe
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x7c0000
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x12
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf800000
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x17
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000
+#define PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x1c
+#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf
+#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0
+#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x10
+#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x4
+#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x20
+#define PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x5
+#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x1
+#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x0
+#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x2
+#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x1
+#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x4
+#define PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x2
+#define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x8
+#define PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x3
+#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x1
+#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x0
+#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x2
+#define PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x1
+#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x4
+#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x2
+#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x8
+#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x3
+#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x10
+#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x4
+#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x20
+#define PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x5
+#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x40
+#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x6
+#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x80
+#define PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x7
+#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x7
+#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x0
+#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x70
+#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x4
+#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x80
+#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x7
+#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x300
+#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x8
+#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0xfc00
+#define PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0xa
+#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x1
+#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x0
+#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x2
+#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x1
+#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x4
+#define PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x2
+#define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x8
+#define PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x3
+#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x1
+#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x0
+#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x2
+#define PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x1
+#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x4
+#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x2
+#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x8
+#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x3
+#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x10
+#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x4
+#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x20
+#define PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x5
+#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x40
+#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x6
+#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x80
+#define PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x7
+#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x7
+#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x0
+#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x70
+#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x4
+#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x80
+#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x7
+#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x300
+#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x8
+#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0xfc00
+#define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0xa
+#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x1
+#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x0
+#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x2
+#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x1
+#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x4
+#define PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x2
+#define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x8
+#define PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x3
+#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x1
+#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x0
+#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x2
+#define PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x1
+#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x4
+#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x2
+#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x8
+#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x3
+#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x10
+#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x4
+#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x20
+#define PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x5
+#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x40
+#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x6
+#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x80
+#define PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x7
+#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x7
+#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x0
+#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x70
+#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x4
+#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x80
+#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x7
+#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x300
+#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x8
+#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0xfc00
+#define PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0xa
+#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x1
+#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x0
+#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x2
+#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x1
+#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x4
+#define PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x2
+#define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x8
+#define PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x3
+#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x1
+#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x0
+#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x2
+#define PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x1
+#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x4
+#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x2
+#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x8
+#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x3
+#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x10
+#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x4
+#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x20
+#define PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x5
+#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x40
+#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x6
+#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x80
+#define PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x7
+#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x7
+#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x0
+#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x70
+#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x4
+#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x80
+#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x7
+#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x300
+#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x8
+#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0xfc00
+#define PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0xa
+#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x1
+#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x0
+#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x2
+#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x1
+#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x4
+#define PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x2
+#define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x8
+#define PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x3
+#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x1
+#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x0
+#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x2
+#define PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x1
+#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x4
+#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x2
+#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x8
+#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x3
+#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x10
+#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x4
+#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x20
+#define PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x5
+#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x40
+#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x6
+#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x80
+#define PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x7
+#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x7
+#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x0
+#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x70
+#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x4
+#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x80
+#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x7
+#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x300
+#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x8
+#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0xfc00
+#define PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0xa
+#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x1
+#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x0
+#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x2
+#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x1
+#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x4
+#define PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x2
+#define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x8
+#define PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x3
+#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x1
+#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x0
+#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x2
+#define PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x1
+#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x4
+#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x2
+#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x8
+#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x3
+#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x10
+#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x4
+#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x20
+#define PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x5
+#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x40
+#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x6
+#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x80
+#define PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x7
+#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x7
+#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x0
+#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x70
+#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x4
+#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x80
+#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x7
+#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x300
+#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x8
+#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0xfc00
+#define PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0xa
+#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x1
+#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x0
+#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x2
+#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x1
+#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x4
+#define PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x2
+#define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x8
+#define PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x3
+#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x1
+#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x0
+#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x2
+#define PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x1
+#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x4
+#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x2
+#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x8
+#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x3
+#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x10
+#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x4
+#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x20
+#define PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x5
+#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x40
+#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x6
+#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x80
+#define PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x7
+#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x7
+#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x0
+#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x70
+#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x4
+#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x80
+#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x7
+#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x300
+#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x8
+#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0xfc00
+#define PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0xa
+#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x1
+#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x0
+#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x2
+#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x1
+#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x4
+#define PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x2
+#define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x8
+#define PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x3
+#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x1
+#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x0
+#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x2
+#define PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x1
+#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x4
+#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x2
+#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x8
+#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x3
+#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x10
+#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x4
+#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x20
+#define PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x5
+#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x40
+#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x6
+#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x80
+#define PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x7
+#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x7
+#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x0
+#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x70
+#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x4
+#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x80
+#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x7
+#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x300
+#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x8
+#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0xfc00
+#define PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0xa
+#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x1
+#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x0
+#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x2
+#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x1
+#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x4
+#define PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x2
+#define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x8
+#define PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x3
+#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x1
+#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x0
+#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x2
+#define PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x1
+#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x4
+#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x2
+#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x8
+#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x3
+#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x10
+#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x4
+#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x20
+#define PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x5
+#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x40
+#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x6
+#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x80
+#define PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x7
+#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x7
+#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x0
+#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x70
+#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x4
+#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x80
+#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x7
+#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x300
+#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x8
+#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0xfc00
+#define PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0xa
+#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x1
+#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x0
+#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x2
+#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x1
+#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x4
+#define PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x2
+#define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x8
+#define PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x3
+#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x1
+#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x0
+#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x2
+#define PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x1
+#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x4
+#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x2
+#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x8
+#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x3
+#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x10
+#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x4
+#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x20
+#define PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x5
+#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x40
+#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x6
+#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x80
+#define PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x7
+#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x7
+#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x0
+#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x70
+#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x4
+#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x80
+#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x7
+#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x300
+#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x8
+#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0xfc00
+#define PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0xa
+#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x1
+#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x0
+#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x2
+#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x1
+#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x4
+#define PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x2
+#define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x8
+#define PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x3
+#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x1
+#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x0
+#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x2
+#define PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x1
+#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x4
+#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x2
+#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x8
+#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x3
+#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x10
+#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x4
+#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x20
+#define PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x5
+#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x40
+#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x6
+#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x80
+#define PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x7
+#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x7
+#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x0
+#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x70
+#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x4
+#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x80
+#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x7
+#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x300
+#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x8
+#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0xfc00
+#define PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0xa
+#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x1
+#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x0
+#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x2
+#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x1
+#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x4
+#define PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x2
+#define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x8
+#define PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x3
+#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x1
+#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x0
+#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x2
+#define PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x1
+#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x4
+#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x2
+#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x8
+#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x3
+#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x10
+#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x4
+#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x20
+#define PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x5
+#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x40
+#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x6
+#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x80
+#define PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x7
+#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x7
+#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x0
+#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x70
+#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x4
+#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x80
+#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x7
+#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x300
+#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x8
+#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0xfc00
+#define PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0xa
+#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x1
+#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x0
+#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x2
+#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x1
+#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x4
+#define PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x2
+#define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x8
+#define PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x3
+#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x1
+#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x0
+#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x2
+#define PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x1
+#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x4
+#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x2
+#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x8
+#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x3
+#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x10
+#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x4
+#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x20
+#define PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x5
+#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x40
+#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x6
+#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x80
+#define PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x7
+#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x7
+#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x0
+#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x70
+#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x4
+#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x80
+#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x7
+#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x300
+#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x8
+#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0xfc00
+#define PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0xa
+#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x1
+#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x0
+#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x2
+#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x1
+#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x4
+#define PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x2
+#define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x8
+#define PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x3
+#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x1
+#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x0
+#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x2
+#define PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x1
+#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x4
+#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x2
+#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x8
+#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x3
+#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x10
+#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x4
+#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x20
+#define PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x5
+#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x40
+#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x6
+#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x80
+#define PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x7
+#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x7
+#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x0
+#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x70
+#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x4
+#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x80
+#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x7
+#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x300
+#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x8
+#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0xfc00
+#define PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0xa
+#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x1
+#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x0
+#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x2
+#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x1
+#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x4
+#define PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x2
+#define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x8
+#define PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x3
+#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x1
+#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x0
+#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x2
+#define PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x1
+#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x4
+#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x2
+#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x8
+#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x3
+#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x10
+#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x4
+#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x20
+#define PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x5
+#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x40
+#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x6
+#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x80
+#define PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x7
+#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x7
+#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x0
+#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x70
+#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x4
+#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x80
+#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x7
+#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x300
+#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x8
+#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0xfc00
+#define PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0xa
+#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x1
+#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x0
+#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x2
+#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x1
+#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x4
+#define PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x2
+#define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x8
+#define PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x3
+#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x1
+#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x0
+#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x2
+#define PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x1
+#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x4
+#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x2
+#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x8
+#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x3
+#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x10
+#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x4
+#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x20
+#define PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x5
+#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x40
+#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x6
+#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x80
+#define PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x7
+#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x7
+#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x0
+#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x70
+#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x4
+#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x80
+#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x7
+#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x300
+#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x8
+#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0xfc00
+#define PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0xa
+#define PB1_GLB_CTRL_REG0__BACKUP_MASK 0xffff
+#define PB1_GLB_CTRL_REG0__BACKUP__SHIFT 0x0
+#define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x30000
+#define PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x10
+#define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x700000
+#define PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x14
+#define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x800000
+#define PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x17
+#define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x1000000
+#define PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x18
+#define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x2000000
+#define PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x19
+#define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x4000000
+#define PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x1a
+#define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000
+#define PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x1e
+#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x1
+#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x0
+#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x7e
+#define PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x1
+#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x80
+#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x7
+#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x3f00
+#define PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x8
+#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x4000
+#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0xe
+#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x3f8000
+#define PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0xf
+#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x400000
+#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x16
+#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000
+#define PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x17
+#define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000
+#define PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x1e
+#define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000
+#define PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x1f
+#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x1
+#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x0
+#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0xfe
+#define PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x1
+#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x100
+#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x8
+#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0xfe00
+#define PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x9
+#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x10000
+#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x10
+#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0xfe0000
+#define PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x11
+#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x1000000
+#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x18
+#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000
+#define PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x19
+#define PB1_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x1f
+#define PB1_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x0
+#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x60
+#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x5
+#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x180
+#define PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x7
+#define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x600
+#define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x9
+#define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x800
+#define PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0xb
+#define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x1000
+#define PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0xc
+#define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x1c000
+#define PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0xe
+#define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x1c0000
+#define PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x12
+#define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x200000
+#define PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x15
+#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x400000
+#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x16
+#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x7800000
+#define PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x17
+#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x8000000
+#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x1b
+#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000
+#define PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x1c
+#define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000
+#define PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x1f
+#define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0xffff
+#define PB1_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x0
+#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x30000
+#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x10
+#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x40000
+#define PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x12
+#define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x3c00000
+#define PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x16
+#define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x4000000
+#define PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x1a
+#define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x8000000
+#define PB1_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x1b
+#define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000
+#define PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x1c
+#define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0xff
+#define PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x0
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3_MASK 0x1
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3__SHIFT 0x0
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7_MASK 0x2
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7__SHIFT 0x1
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11_MASK 0x4
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11__SHIFT 0x2
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15_MASK 0x8
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15__SHIFT 0x3
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT_MASK 0x10
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT__SHIFT 0x4
+#define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0xf00
+#define PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x8
+#define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0xf000
+#define PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0xc
+#define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0xf0000
+#define PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x10
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x100000
+#define PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x14
+#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3_MASK 0x1
+#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3__SHIFT 0x0
+#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3_MASK 0x2
+#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3__SHIFT 0x1
+#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3_MASK 0x4
+#define PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3__SHIFT 0x2
+#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x1000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0xc
+#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x2000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0xd
+#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x4000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0xe
+#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x8000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0xf
+#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0_MASK 0x30000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0__SHIFT 0x10
+#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0xc0000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x12
+#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1_MASK 0x300000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1__SHIFT 0x14
+#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0xc00000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x16
+#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2_MASK 0x3000000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2__SHIFT 0x18
+#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0xc000000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x1a
+#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3_MASK 0x30000000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3__SHIFT 0x1c
+#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000
+#define PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x1e
+#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7_MASK 0x1
+#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7__SHIFT 0x0
+#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7_MASK 0x2
+#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7__SHIFT 0x1
+#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7_MASK 0x4
+#define PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7__SHIFT 0x2
+#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x1000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0xc
+#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x2000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0xd
+#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x4000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0xe
+#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x8000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0xf
+#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4_MASK 0x30000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4__SHIFT 0x10
+#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0xc0000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x12
+#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5_MASK 0x300000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5__SHIFT 0x14
+#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0xc00000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x16
+#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6_MASK 0x3000000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6__SHIFT 0x18
+#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0xc000000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x1a
+#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7_MASK 0x30000000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7__SHIFT 0x1c
+#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000
+#define PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x1e
+#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11_MASK 0x1
+#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11__SHIFT 0x0
+#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11_MASK 0x2
+#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11__SHIFT 0x1
+#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11_MASK 0x4
+#define PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11__SHIFT 0x2
+#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x1000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0xc
+#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x2000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0xd
+#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x4000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0xe
+#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x8000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0xf
+#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8_MASK 0x30000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8__SHIFT 0x10
+#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0xc0000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x12
+#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9_MASK 0x300000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9__SHIFT 0x14
+#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0xc00000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x16
+#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10_MASK 0x3000000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10__SHIFT 0x18
+#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0xc000000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x1a
+#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11_MASK 0x30000000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11__SHIFT 0x1c
+#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000
+#define PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x1e
+#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15_MASK 0x1
+#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15__SHIFT 0x0
+#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15_MASK 0x2
+#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15__SHIFT 0x1
+#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15_MASK 0x4
+#define PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15__SHIFT 0x2
+#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x1000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0xc
+#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x2000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0xd
+#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x4000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0xe
+#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x8000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0xf
+#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12_MASK 0x30000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12__SHIFT 0x10
+#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0xc0000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x12
+#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13_MASK 0x300000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13__SHIFT 0x14
+#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0xc00000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x16
+#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14_MASK 0x3000000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14__SHIFT 0x18
+#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0xc000000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x1a
+#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15_MASK 0x30000000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15__SHIFT 0x1c
+#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000
+#define PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x1e
+#define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0xffff
+#define PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x0
+#define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000
+#define PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x10
+#define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x1
+#define PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x0
+#define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x2
+#define PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x1
+#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x4
+#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x2
+#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x8
+#define PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x3
+#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x8000
+#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0xf
+#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000
+#define PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x10
+#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x1
+#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x0
+#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x2
+#define PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x1
+#define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN_MASK 0x4
+#define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN__SHIFT 0x2
+#define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL_MASK 0x8
+#define PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL__SHIFT 0x3
+#define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN_MASK 0x10
+#define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN__SHIFT 0x4
+#define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL_MASK 0x20
+#define PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL__SHIFT 0x5
+#define PB1_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define PB1_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define PB1_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define PB1_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define PB1_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define PB1_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define PB1_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define PB1_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define PB1_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define PB1_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define PB1_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define PB1_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define PB1_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define PB1_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define PB1_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define PB1_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define PB1_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define PB1_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define PB1_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define PB1_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define PB1_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define PB1_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define PB1_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define PB1_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define PB1_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define PB1_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define PB1_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define PB1_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define PB1_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define PB1_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define PB1_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define PB1_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define PB1_HW_DEBUG__HW_16_DEBUG_MASK 0x10000
+#define PB1_HW_DEBUG__HW_16_DEBUG__SHIFT 0x10
+#define PB1_HW_DEBUG__HW_17_DEBUG_MASK 0x20000
+#define PB1_HW_DEBUG__HW_17_DEBUG__SHIFT 0x11
+#define PB1_HW_DEBUG__HW_18_DEBUG_MASK 0x40000
+#define PB1_HW_DEBUG__HW_18_DEBUG__SHIFT 0x12
+#define PB1_HW_DEBUG__HW_19_DEBUG_MASK 0x80000
+#define PB1_HW_DEBUG__HW_19_DEBUG__SHIFT 0x13
+#define PB1_HW_DEBUG__HW_20_DEBUG_MASK 0x100000
+#define PB1_HW_DEBUG__HW_20_DEBUG__SHIFT 0x14
+#define PB1_HW_DEBUG__HW_21_DEBUG_MASK 0x200000
+#define PB1_HW_DEBUG__HW_21_DEBUG__SHIFT 0x15
+#define PB1_HW_DEBUG__HW_22_DEBUG_MASK 0x400000
+#define PB1_HW_DEBUG__HW_22_DEBUG__SHIFT 0x16
+#define PB1_HW_DEBUG__HW_23_DEBUG_MASK 0x800000
+#define PB1_HW_DEBUG__HW_23_DEBUG__SHIFT 0x17
+#define PB1_HW_DEBUG__HW_24_DEBUG_MASK 0x1000000
+#define PB1_HW_DEBUG__HW_24_DEBUG__SHIFT 0x18
+#define PB1_HW_DEBUG__HW_25_DEBUG_MASK 0x2000000
+#define PB1_HW_DEBUG__HW_25_DEBUG__SHIFT 0x19
+#define PB1_HW_DEBUG__HW_26_DEBUG_MASK 0x4000000
+#define PB1_HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a
+#define PB1_HW_DEBUG__HW_27_DEBUG_MASK 0x8000000
+#define PB1_HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b
+#define PB1_HW_DEBUG__HW_28_DEBUG_MASK 0x10000000
+#define PB1_HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c
+#define PB1_HW_DEBUG__HW_29_DEBUG_MASK 0x20000000
+#define PB1_HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d
+#define PB1_HW_DEBUG__HW_30_DEBUG_MASK 0x40000000
+#define PB1_HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e
+#define PB1_HW_DEBUG__HW_31_DEBUG_MASK 0x80000000
+#define PB1_HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f
+#define PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK 0x2
+#define PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START__SHIFT 0x1
+#define PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL_MASK 0x4
+#define PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT 0x2
+#define PB1_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS_MASK 0x8
+#define PB1_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS__SHIFT 0x3
+#define PB1_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON_MASK 0x10
+#define PB1_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON__SHIFT 0x4
+#define PB1_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH_MASK 0x60
+#define PB1_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH__SHIFT 0x5
+#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL_MASK 0xf80
+#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL__SHIFT 0x7
+#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF_MASK 0x1000
+#define PB1_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF__SHIFT 0xc
+#define PB1_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0__MASK 0x2000
+#define PB1_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0___SHIFT 0xd
+#define PB1_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD_MASK 0x4000
+#define PB1_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD__SHIFT 0xe
+#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x8000
+#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0xf
+#define PB1_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE_MASK 0xf0000
+#define PB1_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE__SHIFT 0x10
+#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE_MASK 0x100000
+#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE__SHIFT 0x14
+#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL_MASK 0x1e00000
+#define PB1_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x15
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN_MASK 0x1e
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN__SHIFT 0x1
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL_MASK 0x1e0
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL__SHIFT 0x5
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN_MASK 0x3e00
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN__SHIFT 0x9
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL_MASK 0x7c000
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL__SHIFT 0xe
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN_MASK 0x780000
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN__SHIFT 0x13
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL_MASK 0x7800000
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL__SHIFT 0x17
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN_MASK 0x8000000
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN__SHIFT 0x1b
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL_MASK 0x10000000
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL__SHIFT 0x1c
+#define PB1_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1__MASK 0x20000000
+#define PB1_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT 0x1d
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN_MASK 0x40000000
+#define PB1_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN__SHIFT 0x1e
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN_MASK 0x1e
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN__SHIFT 0x1
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE_MASK 0x20
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE__SHIFT 0x5
+#define PB1_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN_MASK 0x40
+#define PB1_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x6
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS_MASK 0x80
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS__SHIFT 0x7
+#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL_MASK 0x300
+#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x8
+#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL_MASK 0xc00
+#define PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL__SHIFT 0xa
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME_MASK 0xf000
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME__SHIFT 0xc
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME_MASK 0xf0000
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME__SHIFT 0x10
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME_MASK 0xf00000
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME__SHIFT 0x14
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME_MASK 0xf000000
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME__SHIFT 0x18
+#define PB1_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL_MASK 0x70000000
+#define PB1_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL__SHIFT 0x1c
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE_MASK 0x80000000
+#define PB1_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE__SHIFT 0x1f
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK 0x2
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ__SHIFT 0x1
+#define PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG_MASK 0x1c
+#define PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT 0x2
+#define PB1_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL_MASK 0x60
+#define PB1_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL__SHIFT 0x5
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS_MASK 0x80
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS__SHIFT 0x7
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL_MASK 0x700
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL__SHIFT 0x8
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN_MASK 0x7800
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN__SHIFT 0xb
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE_MASK 0x1ff8000
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE__SHIFT 0xf
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME_MASK 0x1e000000
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT 0x19
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN_MASK 0x60000000
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN__SHIFT 0x1d
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS_MASK 0x80000000
+#define PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS__SHIFT 0x1f
+#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL_MASK 0xe
+#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL__SHIFT 0x1
+#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL_MASK 0x1ff0
+#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL__SHIFT 0x4
+#define PB1_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF_MASK 0x2000
+#define PB1_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF__SHIFT 0xd
+#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS_MASK 0x8000
+#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS__SHIFT 0xf
+#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL_MASK 0xff0000
+#define PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL__SHIFT 0x10
+#define PB1_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL_MASK 0x1000000
+#define PB1_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL__SHIFT 0x18
+#define PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK 0x2
+#define PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN__SHIFT 0x1
+#define PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING_MASK 0x4
+#define PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT 0x2
+#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE_MASK 0x6
+#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE__SHIFT 0x1
+#define PB1_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE_MASK 0x18
+#define PB1_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE__SHIFT 0x3
+#define PB1_STRAP_GLB_REG1__STRAP_RX_EI_FILTER_MASK 0x60
+#define PB1_STRAP_GLB_REG1__STRAP_RX_EI_FILTER__SHIFT 0x5
+#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY_MASK 0x80
+#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY__SHIFT 0x7
+#define PB1_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE_MASK 0x300
+#define PB1_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE__SHIFT 0x8
+#define PB1_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG_MASK 0x400
+#define PB1_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG__SHIFT 0xa
+#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT_MASK 0x1800
+#define PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT__SHIFT 0xb
+#define PB1_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME_MASK 0x1c
+#define PB1_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME__SHIFT 0x2
+#define PB1_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME_MASK 0x60
+#define PB1_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME__SHIFT 0x5
+#define PB1_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME_MASK 0x180
+#define PB1_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME__SHIFT 0x7
+#define PB1_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME_MASK 0x600
+#define PB1_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME__SHIFT 0x9
+#define PB1_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME_MASK 0x1800
+#define PB1_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME__SHIFT 0xb
+#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS0_MASK 0x10000000
+#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS0__SHIFT 0x1c
+#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS1_MASK 0x20000000
+#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS1__SHIFT 0x1d
+#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR_MASK 0xc0000000
+#define PB1_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR__SHIFT 0x1e
+#define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x3f
+#define PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x0
+#define PB1_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR_MASK 0x80
+#define PB1_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR__SHIFT 0x7
+#define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0xf00
+#define PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x8
+#define PB1_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN_MASK 0x100000
+#define PB1_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN__SHIFT 0x14
+#define PB1_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY_MASK 0x200000
+#define PB1_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY__SHIFT 0x15
+#define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x400000
+#define PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x16
+#define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x800000
+#define PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x17
+#define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000
+#define PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x18
+#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0xff
+#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x0
+#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x100
+#define PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x8
+#define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x10000
+#define PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x10
+#define PB1_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS_MASK 0xe0000
+#define PB1_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS__SHIFT 0x11
+#define PB1_DFT_JIT_INJ_REG1__DFT_CHECK_TIME_MASK 0xf00000
+#define PB1_DFT_JIT_INJ_REG1__DFT_CHECK_TIME__SHIFT 0x14
+#define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0xffff
+#define PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x0
+#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x1
+#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x0
+#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x3e
+#define PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x1
+#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR_MASK 0xff
+#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR__SHIFT 0x0
+#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR_MASK 0xff00
+#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR__SHIFT 0x8
+#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED_MASK 0x10000
+#define PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED__SHIFT 0x10
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x1
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x0
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x2
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x1
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x4
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x2
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x8
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x3
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x10
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x4
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x20
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x5
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x40
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x6
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x80
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x7
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x100
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x8
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x200
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x9
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x400
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0xa
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x800
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0xb
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x1000
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0xc
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x2000
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0xd
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x4000
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0xe
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN_MASK 0x8000
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN__SHIFT 0xf
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN_MASK 0x10000
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN__SHIFT 0x10
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN_MASK 0x20000
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN__SHIFT 0x11
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN_MASK 0x40000
+#define PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN__SHIFT 0x12
+#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK 0x3
+#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT 0x0
+#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK 0x4
+#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT 0x2
+#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK 0x8
+#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT 0x3
+#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK 0x7f0
+#define PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT 0x4
+#define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK 0x800
+#define PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT 0xb
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK 0xff
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK 0x100
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT 0x8
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK 0xe00
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x9
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK 0x1000
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT 0xc
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK 0x2000
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT 0xd
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK 0x4000
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT 0xe
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK 0xfff8000
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT 0xf
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK 0x10000000
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT 0x1c
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK 0x40000000
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT 0x1e
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK 0x80000000
+#define PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT 0x1f
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK 0x1f
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT 0x0
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK 0x20
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT 0x5
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK 0xc0
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT 0x6
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK 0x100
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT 0x8
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x200
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x9
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x400
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0xa
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x800
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0xb
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x1000
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0xc
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK 0x2000
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT 0xd
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK 0x4000
+#define PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT 0xe
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK 0x380000
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x13
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK 0x400000
+#define PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT 0x16
+#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
+#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
+#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
+#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1
+#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK 0x70
+#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT 0x4
+#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ_MASK 0x300
+#define PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ__SHIFT 0x8
+#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
+#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
+#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
+#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1
+#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK 0x70
+#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT 0x4
+#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ_MASK 0x300
+#define PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ__SHIFT 0x8
+#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
+#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
+#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
+#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1
+#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK 0x70
+#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT 0x4
+#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ_MASK 0x300
+#define PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ__SHIFT 0x8
+#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
+#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
+#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT_MASK 0x2
+#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT__SHIFT 0x1
+#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK 0x70
+#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT 0x4
+#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ_MASK 0x300
+#define PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ__SHIFT 0x8
+#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK 0x3
+#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT 0x0
+#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK 0x4
+#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT 0x2
+#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK 0x8
+#define PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT 0x3
+#define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK 0x10
+#define PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT 0x4
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK 0x7
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT 0x0
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK 0x8
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT 0x3
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK 0x70
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT 0x4
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK 0x80
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT 0x7
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK 0x100
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT 0x8
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK 0x200
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT 0x9
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK 0x3fc00
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT 0xa
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK 0x40000
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT 0x12
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK 0xff80000
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT 0x13
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK 0x10000000
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT 0x1c
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK 0x60000000
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT 0x1d
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK 0x80000000
+#define PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT 0x1f
+#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK 0x7
+#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT 0x0
+#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK 0x8
+#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT 0x3
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK 0x10
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT 0x4
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK 0x20
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT 0x5
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK 0x40
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT 0x6
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK 0x80
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT 0x7
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK 0x100
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT 0x8
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK 0x200
+#define PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT 0x9
+#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK 0x3c000
+#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT 0xe
+#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK 0x40000
+#define PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT 0x12
+#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
+#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
+#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK 0x70
+#define PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT 0x4
+#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
+#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
+#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK 0x70
+#define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT 0x4
+#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
+#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
+#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK 0x70
+#define PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT 0x4
+#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT_MASK 0x1
+#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT__SHIFT 0x0
+#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK 0x70
+#define PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT 0x4
+#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK 0x3ff
+#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT 0x0
+#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK 0xffc00
+#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT 0xa
+#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK 0x3ff00000
+#define PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT 0x14
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK 0xf
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT 0x0
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK 0xf0
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT 0x4
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK 0xf00
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT 0x8
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK 0xf000
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT 0xc
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK 0xf0000
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT 0x10
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK 0xf00000
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT 0x14
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK 0x1000000
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT 0x18
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK 0x2000000
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT 0x19
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK 0x4000000
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT 0x1a
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK 0x8000000
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT 0x1b
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK 0x10000000
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT 0x1c
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK 0x20000000
+#define PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT 0x1d
+#define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK 0xc0000000
+#define PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT 0x1e
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK 0xf000
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT 0xc
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK 0xf0000
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT 0x10
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK 0xf00000
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT 0x14
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK 0x3000000
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT 0x18
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK 0xc000000
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT 0x1a
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK 0x30000000
+#define PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT 0x1c
+#define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK 0xc0000000
+#define PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT 0x1e
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK 0x1
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT 0x0
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK 0x2
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT 0x1
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK 0x4
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT 0x2
+#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1_MASK 0x18
+#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1__SHIFT 0x3
+#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2_MASK 0x60
+#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2__SHIFT 0x5
+#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3_MASK 0x180
+#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3__SHIFT 0x7
+#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE_MASK 0xe00
+#define PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE__SHIFT 0x9
+#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1_MASK 0x3000
+#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1__SHIFT 0xc
+#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2_MASK 0xc000
+#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2__SHIFT 0xe
+#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3_MASK 0x30000
+#define PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3__SHIFT 0x10
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK 0xf00000
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT 0x14
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK 0xf000000
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT 0x18
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK 0xf0000000
+#define PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT 0x1c
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK 0x7
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT 0x0
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK 0x38
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT 0x3
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK 0x1c0
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT 0x6
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK 0xe00
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT 0x9
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK 0x7000
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT 0xc
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK 0x38000
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT 0xf
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK 0xf00000
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT 0x14
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK 0xf000000
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT 0x18
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK 0xf0000000
+#define PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT 0x1c
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK 0x1f
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT 0x0
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK 0x3e0
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT 0x5
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK 0x7c00
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT 0xa
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK 0x8000
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT 0xf
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK 0x10000
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT 0x10
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK 0x20000
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT 0x11
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK 0x40000
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT 0x12
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK 0x80000
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT 0x13
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK 0x100000
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT 0x14
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK 0x8000000
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT 0x1b
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK 0x10000000
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT 0x1c
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000
+#define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT 0x1d
+#define PB1_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE_MASK 0x80000000
+#define PB1_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE__SHIFT 0x1f
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK 0xf
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT 0x0
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK 0xf0
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT 0x4
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK 0xf00
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT 0x8
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK 0xf000
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT 0xc
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK 0xf0000
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT 0x10
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK 0xf00000
+#define PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT 0x14
+#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000000
+#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0x18
+#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK 0x4000000
+#define PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT 0x1a
+#define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK 0x8000000
+#define PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT 0x1b
+#define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS_MASK 0x10000000
+#define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__SHIFT 0x1c
+#define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF_MASK 0x20000000
+#define PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF__SHIFT 0x1d
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK 0xf
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT 0x0
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK 0xf0
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT 0x4
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK 0xf00
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT 0x8
+#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK 0x1000
+#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT 0xc
+#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK 0x2000
+#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT 0xd
+#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK_MASK 0x4000
+#define PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK__SHIFT 0xe
+#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3_MASK 0x10000
+#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3__SHIFT 0x10
+#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2_MASK 0x20000
+#define PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2__SHIFT 0x11
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK 0x1c0000
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT 0x12
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK 0xe00000
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT 0x15
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK 0x7000000
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT 0x18
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK 0x8000000
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT 0x1b
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK 0x10000000
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT 0x1c
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK 0x20000000
+#define PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT 0x1d
+#define PB1_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME_MASK 0x3
+#define PB1_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME__SHIFT 0x0
+#define PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME_MASK 0xc
+#define PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT 0x2
+#define PB1_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN_MASK 0x10
+#define PB1_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN__SHIFT 0x4
+#define PB1_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY_MASK 0x20
+#define PB1_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY__SHIFT 0x5
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3_MASK 0x1
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3__SHIFT 0x0
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7_MASK 0x2
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7__SHIFT 0x1
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11_MASK 0x4
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11__SHIFT 0x2
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15_MASK 0x8
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15__SHIFT 0x3
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3_MASK 0x10
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3__SHIFT 0x4
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7_MASK 0x20
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7__SHIFT 0x5
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11_MASK 0x40
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11__SHIFT 0x6
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15_MASK 0x80
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15__SHIFT 0x7
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3_MASK 0x100
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3__SHIFT 0x8
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7_MASK 0x200
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7__SHIFT 0x9
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11_MASK 0x400
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11__SHIFT 0xa
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15_MASK 0x800
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15__SHIFT 0xb
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3_MASK 0x1000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3__SHIFT 0xc
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7_MASK 0x2000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7__SHIFT 0xd
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11_MASK 0x4000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11__SHIFT 0xe
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15_MASK 0x8000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15__SHIFT 0xf
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3_MASK 0x10000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3__SHIFT 0x10
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7_MASK 0x20000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7__SHIFT 0x11
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11_MASK 0x40000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11__SHIFT 0x12
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15_MASK 0x80000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15__SHIFT 0x13
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3_MASK 0x100000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3__SHIFT 0x14
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7_MASK 0x200000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7__SHIFT 0x15
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11_MASK 0x400000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11__SHIFT 0x16
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15_MASK 0x800000
+#define PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15__SHIFT 0x17
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK 0x1
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT 0x0
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK 0x2
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT 0x1
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK 0x4
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT 0x2
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK 0x8
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT 0x3
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK 0xc0
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x6
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK 0x100
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x8
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK 0x200
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT 0x9
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK 0x400
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT 0xa
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x800
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0xb
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x1000
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xc
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK 0x2000
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT 0xd
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK 0x4000
+#define PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT 0xe
+#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK 0x8000
+#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT 0xf
+#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK 0x10000
+#define PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT 0x10
+#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK 0x20000
+#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT 0x11
+#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK 0x40000
+#define PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT 0x12
+#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK 0x80000
+#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT 0x13
+#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK 0x100000
+#define PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT 0x14
+#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK 0x200000
+#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT 0x15
+#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK 0x400000
+#define PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT 0x16
+#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK 0x10000000
+#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT 0x1c
+#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK 0x20000000
+#define PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT 0x1d
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK 0x40000000
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT 0x1e
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK 0x80000000
+#define PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT 0x1f
+#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK 0x1
+#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT 0x0
+#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK 0x2
+#define PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT 0x1
+#define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK 0xff
+#define PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT 0x0
+#define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK 0xc00
+#define PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT 0xa
+#define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK 0x1000
+#define PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT 0xc
+#define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK 0x2000
+#define PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT 0xd
+#define PB1_RX_LANE0_CTRL_REG0__RX_TERM_EN_0_MASK 0x4000
+#define PB1_RX_LANE0_CTRL_REG0__RX_TERM_EN_0__SHIFT 0xe
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK 0x7
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT 0x0
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK 0x8
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT 0x3
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0_MASK 0x40
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0__SHIFT 0x6
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK 0x80
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT 0x7
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK 0x100
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT 0x8
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK 0x200
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT 0x9
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0_MASK 0x3fc00
+#define PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0__SHIFT 0xa
+#define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK 0xff
+#define PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT 0x0
+#define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK 0xc00
+#define PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT 0xa
+#define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK 0x1000
+#define PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT 0xc
+#define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK 0x2000
+#define PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT 0xd
+#define PB1_RX_LANE1_CTRL_REG0__RX_TERM_EN_1_MASK 0x4000
+#define PB1_RX_LANE1_CTRL_REG0__RX_TERM_EN_1__SHIFT 0xe
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK 0x7
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT 0x0
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK 0x8
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT 0x3
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1_MASK 0x40
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1__SHIFT 0x6
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK 0x80
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT 0x7
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK 0x100
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT 0x8
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK 0x200
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT 0x9
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1_MASK 0x3fc00
+#define PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1__SHIFT 0xa
+#define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK 0xff
+#define PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT 0x0
+#define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK 0xc00
+#define PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT 0xa
+#define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK 0x1000
+#define PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT 0xc
+#define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK 0x2000
+#define PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT 0xd
+#define PB1_RX_LANE2_CTRL_REG0__RX_TERM_EN_2_MASK 0x4000
+#define PB1_RX_LANE2_CTRL_REG0__RX_TERM_EN_2__SHIFT 0xe
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK 0x7
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT 0x0
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK 0x8
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT 0x3
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2_MASK 0x40
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2__SHIFT 0x6
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK 0x80
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT 0x7
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK 0x100
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT 0x8
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK 0x200
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT 0x9
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2_MASK 0x3fc00
+#define PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2__SHIFT 0xa
+#define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK 0xff
+#define PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT 0x0
+#define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK 0xc00
+#define PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT 0xa
+#define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK 0x1000
+#define PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT 0xc
+#define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK 0x2000
+#define PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT 0xd
+#define PB1_RX_LANE3_CTRL_REG0__RX_TERM_EN_3_MASK 0x4000
+#define PB1_RX_LANE3_CTRL_REG0__RX_TERM_EN_3__SHIFT 0xe
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK 0x7
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT 0x0
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK 0x8
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT 0x3
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3_MASK 0x40
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3__SHIFT 0x6
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK 0x80
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT 0x7
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK 0x100
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT 0x8
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK 0x200
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT 0x9
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3_MASK 0x3fc00
+#define PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3__SHIFT 0xa
+#define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK 0xff
+#define PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT 0x0
+#define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK 0xc00
+#define PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT 0xa
+#define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK 0x1000
+#define PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT 0xc
+#define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK 0x2000
+#define PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT 0xd
+#define PB1_RX_LANE4_CTRL_REG0__RX_TERM_EN_4_MASK 0x4000
+#define PB1_RX_LANE4_CTRL_REG0__RX_TERM_EN_4__SHIFT 0xe
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK 0x7
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT 0x0
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK 0x8
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT 0x3
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4_MASK 0x40
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4__SHIFT 0x6
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK 0x80
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT 0x7
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK 0x100
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT 0x8
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK 0x200
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT 0x9
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4_MASK 0x3fc00
+#define PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4__SHIFT 0xa
+#define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK 0xff
+#define PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT 0x0
+#define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK 0xc00
+#define PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT 0xa
+#define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK 0x1000
+#define PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT 0xc
+#define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK 0x2000
+#define PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT 0xd
+#define PB1_RX_LANE5_CTRL_REG0__RX_TERM_EN_5_MASK 0x4000
+#define PB1_RX_LANE5_CTRL_REG0__RX_TERM_EN_5__SHIFT 0xe
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK 0x7
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT 0x0
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK 0x8
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT 0x3
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5_MASK 0x40
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5__SHIFT 0x6
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK 0x80
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT 0x7
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK 0x100
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT 0x8
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK 0x200
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT 0x9
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5_MASK 0x3fc00
+#define PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5__SHIFT 0xa
+#define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK 0xff
+#define PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT 0x0
+#define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK 0xc00
+#define PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT 0xa
+#define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK 0x1000
+#define PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT 0xc
+#define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK 0x2000
+#define PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT 0xd
+#define PB1_RX_LANE6_CTRL_REG0__RX_TERM_EN_6_MASK 0x4000
+#define PB1_RX_LANE6_CTRL_REG0__RX_TERM_EN_6__SHIFT 0xe
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK 0x7
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT 0x0
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK 0x8
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT 0x3
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6_MASK 0x40
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6__SHIFT 0x6
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK 0x80
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT 0x7
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK 0x100
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT 0x8
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK 0x200
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT 0x9
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6_MASK 0x3fc00
+#define PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6__SHIFT 0xa
+#define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK 0xff
+#define PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT 0x0
+#define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK 0xc00
+#define PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT 0xa
+#define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK 0x1000
+#define PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT 0xc
+#define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK 0x2000
+#define PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT 0xd
+#define PB1_RX_LANE7_CTRL_REG0__RX_TERM_EN_7_MASK 0x4000
+#define PB1_RX_LANE7_CTRL_REG0__RX_TERM_EN_7__SHIFT 0xe
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK 0x7
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT 0x0
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK 0x8
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT 0x3
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7_MASK 0x40
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7__SHIFT 0x6
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK 0x80
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT 0x7
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK 0x100
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT 0x8
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK 0x200
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT 0x9
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7_MASK 0x3fc00
+#define PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7__SHIFT 0xa
+#define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK 0xff
+#define PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT 0x0
+#define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK 0xc00
+#define PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT 0xa
+#define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK 0x1000
+#define PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT 0xc
+#define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK 0x2000
+#define PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT 0xd
+#define PB1_RX_LANE8_CTRL_REG0__RX_TERM_EN_8_MASK 0x4000
+#define PB1_RX_LANE8_CTRL_REG0__RX_TERM_EN_8__SHIFT 0xe
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK 0x7
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT 0x0
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK 0x8
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT 0x3
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8_MASK 0x40
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8__SHIFT 0x6
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK 0x80
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT 0x7
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK 0x100
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT 0x8
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK 0x200
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT 0x9
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8_MASK 0x3fc00
+#define PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8__SHIFT 0xa
+#define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK 0xff
+#define PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT 0x0
+#define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK 0xc00
+#define PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT 0xa
+#define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK 0x1000
+#define PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT 0xc
+#define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK 0x2000
+#define PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT 0xd
+#define PB1_RX_LANE9_CTRL_REG0__RX_TERM_EN_9_MASK 0x4000
+#define PB1_RX_LANE9_CTRL_REG0__RX_TERM_EN_9__SHIFT 0xe
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK 0x7
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT 0x0
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK 0x8
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT 0x3
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9_MASK 0x40
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9__SHIFT 0x6
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK 0x80
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT 0x7
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK 0x100
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT 0x8
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK 0x200
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT 0x9
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9_MASK 0x3fc00
+#define PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9__SHIFT 0xa
+#define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK 0xff
+#define PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT 0x0
+#define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK 0xc00
+#define PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT 0xa
+#define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK 0x1000
+#define PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT 0xc
+#define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK 0x2000
+#define PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT 0xd
+#define PB1_RX_LANE10_CTRL_REG0__RX_TERM_EN_10_MASK 0x4000
+#define PB1_RX_LANE10_CTRL_REG0__RX_TERM_EN_10__SHIFT 0xe
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK 0x7
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT 0x0
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK 0x8
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT 0x3
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10_MASK 0x40
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10__SHIFT 0x6
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK 0x80
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT 0x7
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK 0x100
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT 0x8
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK 0x200
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT 0x9
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10_MASK 0x3fc00
+#define PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10__SHIFT 0xa
+#define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK 0xff
+#define PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT 0x0
+#define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK 0xc00
+#define PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT 0xa
+#define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK 0x1000
+#define PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT 0xc
+#define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK 0x2000
+#define PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT 0xd
+#define PB1_RX_LANE11_CTRL_REG0__RX_TERM_EN_11_MASK 0x4000
+#define PB1_RX_LANE11_CTRL_REG0__RX_TERM_EN_11__SHIFT 0xe
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK 0x7
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT 0x0
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK 0x8
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT 0x3
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11_MASK 0x40
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11__SHIFT 0x6
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK 0x80
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT 0x7
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK 0x100
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT 0x8
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK 0x200
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT 0x9
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11_MASK 0x3fc00
+#define PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11__SHIFT 0xa
+#define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK 0xff
+#define PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT 0x0
+#define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK 0xc00
+#define PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT 0xa
+#define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK 0x1000
+#define PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT 0xc
+#define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK 0x2000
+#define PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT 0xd
+#define PB1_RX_LANE12_CTRL_REG0__RX_TERM_EN_12_MASK 0x4000
+#define PB1_RX_LANE12_CTRL_REG0__RX_TERM_EN_12__SHIFT 0xe
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK 0x7
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT 0x0
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK 0x8
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT 0x3
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12_MASK 0x40
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12__SHIFT 0x6
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK 0x80
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT 0x7
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK 0x100
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT 0x8
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK 0x200
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT 0x9
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12_MASK 0x3fc00
+#define PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12__SHIFT 0xa
+#define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK 0xff
+#define PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT 0x0
+#define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK 0xc00
+#define PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT 0xa
+#define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK 0x1000
+#define PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT 0xc
+#define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK 0x2000
+#define PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT 0xd
+#define PB1_RX_LANE13_CTRL_REG0__RX_TERM_EN_13_MASK 0x4000
+#define PB1_RX_LANE13_CTRL_REG0__RX_TERM_EN_13__SHIFT 0xe
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK 0x7
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT 0x0
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK 0x8
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT 0x3
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13_MASK 0x40
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13__SHIFT 0x6
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK 0x80
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT 0x7
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK 0x100
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT 0x8
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK 0x200
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT 0x9
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13_MASK 0x3fc00
+#define PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13__SHIFT 0xa
+#define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK 0xff
+#define PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT 0x0
+#define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK 0xc00
+#define PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT 0xa
+#define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK 0x1000
+#define PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT 0xc
+#define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK 0x2000
+#define PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT 0xd
+#define PB1_RX_LANE14_CTRL_REG0__RX_TERM_EN_14_MASK 0x4000
+#define PB1_RX_LANE14_CTRL_REG0__RX_TERM_EN_14__SHIFT 0xe
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK 0x7
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT 0x0
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK 0x8
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT 0x3
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14_MASK 0x40
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14__SHIFT 0x6
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK 0x80
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT 0x7
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK 0x100
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT 0x8
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK 0x200
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT 0x9
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14_MASK 0x3fc00
+#define PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14__SHIFT 0xa
+#define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK 0xff
+#define PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT 0x0
+#define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK 0xc00
+#define PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT 0xa
+#define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK 0x1000
+#define PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT 0xc
+#define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK 0x2000
+#define PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT 0xd
+#define PB1_RX_LANE15_CTRL_REG0__RX_TERM_EN_15_MASK 0x4000
+#define PB1_RX_LANE15_CTRL_REG0__RX_TERM_EN_15__SHIFT 0xe
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK 0x7
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT 0x0
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK 0x8
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT 0x3
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15_MASK 0x40
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15__SHIFT 0x6
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK 0x80
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT 0x7
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK 0x100
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT 0x8
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK 0x200
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT 0x9
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15_MASK 0x3fc00
+#define PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15__SHIFT 0xa
+#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK 0x7
+#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT 0x0
+#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK 0x38
+#define PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT 0x3
+#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK 0x700
+#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT 0x8
+#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK 0x3800
+#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT 0xb
+#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK 0x1c000
+#define PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT 0xe
+#define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK 0x60000
+#define PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT 0x11
+#define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK 0x80000
+#define PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT 0x13
+#define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK 0x100000
+#define PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT 0x14
+#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK 0x200000
+#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT 0x15
+#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK 0x400000
+#define PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT 0x16
+#define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK 0x800000
+#define PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT 0x17
+#define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4_MASK 0x1000000
+#define PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4__SHIFT 0x18
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK 0x1
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT 0x0
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK 0x2
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT 0x1
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK 0x4
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT 0x2
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK 0x8
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT 0x3
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK 0x10
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT 0x4
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK 0x20
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT 0x5
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK 0x40
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT 0x6
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK 0x80
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT 0x7
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK 0x100
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT 0x8
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK 0x200
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT 0x9
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK 0x400
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT 0xa
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK 0x800
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT 0xb
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK 0x1000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT 0xc
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK 0x2000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT 0xd
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK 0x4000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT 0xe
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK 0x8000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT 0xf
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK 0x10000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT 0x10
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK 0x20000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT 0x11
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK 0x40000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT 0x12
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK 0x80000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT 0x13
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK 0x100000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT 0x14
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK 0x200000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT 0x15
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK 0x400000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT 0x16
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK 0x800000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT 0x17
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK 0x1000000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT 0x18
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK 0x2000000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT 0x19
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK 0x4000000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT 0x1a
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK 0x8000000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT 0x1b
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK 0x10000000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT 0x1c
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK 0x20000000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT 0x1d
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK 0x40000000
+#define PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT 0x1e
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3_MASK 0x1
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3__SHIFT 0x0
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7_MASK 0x2
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7__SHIFT 0x1
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11_MASK 0x4
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11__SHIFT 0x2
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15_MASK 0x8
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15__SHIFT 0x3
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3_MASK 0x100
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3__SHIFT 0x8
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7_MASK 0x200
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7__SHIFT 0x9
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11_MASK 0x400
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11__SHIFT 0xa
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15_MASK 0x800
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15__SHIFT 0xb
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3_MASK 0x1000
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3__SHIFT 0xc
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7_MASK 0x2000
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7__SHIFT 0xd
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11_MASK 0x4000
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11__SHIFT 0xe
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15_MASK 0x8000
+#define PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15__SHIFT 0xf
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK 0x1
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT 0x0
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK 0x2
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT 0x1
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK 0x4
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT 0x2
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK 0x8
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT 0x3
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK 0x10
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT 0x4
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK 0x20
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT 0x5
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK 0x40
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT 0x6
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK 0x80
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT 0x7
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK 0x100
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT 0x8
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK 0x200
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT 0x9
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK 0x400
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT 0xa
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK 0x800
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT 0xb
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK 0x1000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT 0xc
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK 0x2000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT 0xd
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK 0x4000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT 0xe
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK 0x8000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT 0xf
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK 0x10000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT 0x10
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK 0x20000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT 0x11
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK 0x40000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT 0x12
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK 0x80000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT 0x13
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK 0x100000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT 0x14
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK 0x200000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT 0x15
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK 0x400000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT 0x16
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK 0x800000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT 0x17
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK 0x1000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT 0x18
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK 0x2000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT 0x19
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK 0x4000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT 0x1a
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK 0x8000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT 0x1b
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK 0x10000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT 0x1c
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK 0x20000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT 0x1d
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK 0x40000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT 0x1e
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK 0x80000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT 0x1f
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK 0x1
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT 0x0
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK 0x2
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT 0x1
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK 0x4
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT 0x2
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK 0x8
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT 0x3
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK 0x10
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT 0x4
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK 0x20
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT 0x5
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK 0x40
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT 0x6
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK 0x80
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT 0x7
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK 0x100
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT 0x8
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK 0x200
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT 0x9
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK 0x400
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT 0xa
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK 0x800
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT 0xb
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK 0x1000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT 0xc
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK 0x2000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT 0xd
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK 0x4000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT 0xe
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK 0x8000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT 0xf
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK 0x10000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT 0x10
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK 0x20000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT 0x11
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK 0x40000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT 0x12
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK 0x80000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT 0x13
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK 0x100000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT 0x14
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK 0x200000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT 0x15
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK 0x400000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT 0x16
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK 0x800000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT 0x17
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK 0x1000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT 0x18
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK 0x2000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT 0x19
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK 0x4000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT 0x1a
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK 0x8000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT 0x1b
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK 0x10000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT 0x1c
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK 0x20000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT 0x1d
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK 0x40000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT 0x1e
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK 0x80000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT 0x1f
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK 0x1
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT 0x0
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK 0x2
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT 0x1
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK 0x4
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT 0x2
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK 0x8
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT 0x3
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK 0x10
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT 0x4
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK 0x20
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT 0x5
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK 0x40
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT 0x6
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK 0x80
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT 0x7
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK 0x100
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT 0x8
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK 0x200
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT 0x9
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK 0x400
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT 0xa
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK 0x800
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT 0xb
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK 0x1000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT 0xc
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK 0x2000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT 0xd
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK 0x4000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT 0xe
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK 0x8000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT 0xf
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK 0x10000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT 0x10
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK 0x20000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT 0x11
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK 0x40000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT 0x12
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK 0x80000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT 0x13
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK 0x100000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT 0x14
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK 0x200000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT 0x15
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK 0x400000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT 0x16
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK 0x800000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT 0x17
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK 0x1000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT 0x18
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK 0x2000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT 0x19
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK 0x4000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT 0x1a
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK 0x8000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT 0x1b
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK 0x10000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT 0x1c
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK 0x20000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT 0x1d
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK 0x40000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT 0x1e
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK 0x80000000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT 0x1f
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK 0x1
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT 0x0
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK 0x2
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT 0x1
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK 0x4
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT 0x2
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK 0x8
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT 0x3
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK 0x10
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT 0x4
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK 0x20
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT 0x5
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK 0x40
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT 0x6
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK 0x80
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT 0x7
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK 0x100
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT 0x8
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK 0x200
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT 0x9
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK 0x400
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT 0xa
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK 0x800
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT 0xb
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK 0x1000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT 0xc
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK 0x2000
+#define PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT 0xd
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK 0x7
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT 0x0
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK 0x8
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT 0x3
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK 0xf0
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT 0x4
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK 0x100
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT 0x8
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1e00
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x9
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK 0x2000
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT 0xd
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK 0x7c000
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT 0xe
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK 0x80000
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT 0x13
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK 0x1f00000
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x14
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK 0x2000000
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT 0x19
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK 0x3c000000
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT 0x1a
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK 0x40000000
+#define PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT 0x1e
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK 0xf
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x0
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK 0x10
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT 0x4
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK 0x20
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT 0x5
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK 0x40
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT 0x6
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK 0x80
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT 0x7
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK 0x100
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT 0x8
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK 0x200
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT 0x9
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK 0x400
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT 0xa
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK 0x800
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT 0xb
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x1000
+#define PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT 0xc
+#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK 0x2000
+#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT 0xd
+#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK 0x4000
+#define PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT 0xe
+#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK 0x1ff8000
+#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT 0xf
+#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK 0x2000000
+#define PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT 0x19
+#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK 0x4000000
+#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT 0x1a
+#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK 0x8000000
+#define PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT 0x1b
+#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK 0x10000000
+#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT 0x1c
+#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK 0x20000000
+#define PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT 0x1d
+#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK 0x40000000
+#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT 0x1e
+#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK 0x80000000
+#define PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT 0x1f
+#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK 0x1
+#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT 0x0
+#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK 0x2
+#define PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT 0x1
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK 0x4
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT 0x2
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK 0x8
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT 0x3
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK 0x10
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT 0x4
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK 0x20
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT 0x5
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK 0x40
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT 0x6
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK 0x80
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT 0x7
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK 0x100
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT 0x8
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK 0x200
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT 0x9
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK 0x400
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT 0xa
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK 0x800
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT 0xb
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK 0xf000
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT 0xc
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0000
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x10
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK 0x1f00000
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT 0x14
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK 0x3e000000
+#define PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x19
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK 0xf
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT 0x0
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK 0xf0
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x4
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK 0x100
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT 0x8
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK 0x200
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT 0x9
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK 0x3c00
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT 0xa
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK 0x3c000
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0xe
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK 0x7c0000
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT 0x12
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf800000
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x17
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK 0xf0000000
+#define PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT 0x1c
+#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK 0xf
+#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x0
+#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK 0x10
+#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT 0x4
+#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK 0x20
+#define PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT 0x5
+#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK 0x1
+#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT 0x0
+#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK 0x2
+#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT 0x1
+#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK 0x4
+#define PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT 0x2
+#define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK 0x8
+#define PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT 0x3
+#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK 0x1
+#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT 0x0
+#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK 0x2
+#define PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT 0x1
+#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK 0x4
+#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT 0x2
+#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK 0x8
+#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT 0x3
+#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK 0x10
+#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT 0x4
+#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK 0x20
+#define PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT 0x5
+#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK 0x40
+#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT 0x6
+#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK 0x80
+#define PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT 0x7
+#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK 0x7
+#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT 0x0
+#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK 0x70
+#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT 0x4
+#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK 0x80
+#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT 0x7
+#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK 0x300
+#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT 0x8
+#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK 0xfc00
+#define PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT 0xa
+#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK 0x1
+#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT 0x0
+#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK 0x2
+#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT 0x1
+#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK 0x4
+#define PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT 0x2
+#define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK 0x8
+#define PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT 0x3
+#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK 0x1
+#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT 0x0
+#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK 0x2
+#define PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT 0x1
+#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK 0x4
+#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT 0x2
+#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK 0x8
+#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT 0x3
+#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK 0x10
+#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT 0x4
+#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK 0x20
+#define PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT 0x5
+#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK 0x40
+#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT 0x6
+#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK 0x80
+#define PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT 0x7
+#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK 0x7
+#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x0
+#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK 0x70
+#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT 0x4
+#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK 0x80
+#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT 0x7
+#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK 0x300
+#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT 0x8
+#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK 0xfc00
+#define PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT 0xa
+#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK 0x1
+#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT 0x0
+#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK 0x2
+#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT 0x1
+#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK 0x4
+#define PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT 0x2
+#define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK 0x8
+#define PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT 0x3
+#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK 0x1
+#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT 0x0
+#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK 0x2
+#define PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT 0x1
+#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK 0x4
+#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT 0x2
+#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK 0x8
+#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT 0x3
+#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK 0x10
+#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT 0x4
+#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK 0x20
+#define PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT 0x5
+#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK 0x40
+#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT 0x6
+#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK 0x80
+#define PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT 0x7
+#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK 0x7
+#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT 0x0
+#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK 0x70
+#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT 0x4
+#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK 0x80
+#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT 0x7
+#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK 0x300
+#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT 0x8
+#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK 0xfc00
+#define PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT 0xa
+#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK 0x1
+#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT 0x0
+#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK 0x2
+#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT 0x1
+#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK 0x4
+#define PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT 0x2
+#define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK 0x8
+#define PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT 0x3
+#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK 0x1
+#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT 0x0
+#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK 0x2
+#define PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT 0x1
+#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK 0x4
+#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT 0x2
+#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK 0x8
+#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT 0x3
+#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK 0x10
+#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT 0x4
+#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK 0x20
+#define PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT 0x5
+#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK 0x40
+#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT 0x6
+#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK 0x80
+#define PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT 0x7
+#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK 0x7
+#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT 0x0
+#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK 0x70
+#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT 0x4
+#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK 0x80
+#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT 0x7
+#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK 0x300
+#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT 0x8
+#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK 0xfc00
+#define PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT 0xa
+#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK 0x1
+#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT 0x0
+#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK 0x2
+#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT 0x1
+#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK 0x4
+#define PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT 0x2
+#define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK 0x8
+#define PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT 0x3
+#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK 0x1
+#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT 0x0
+#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK 0x2
+#define PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT 0x1
+#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK 0x4
+#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT 0x2
+#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK 0x8
+#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT 0x3
+#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK 0x10
+#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT 0x4
+#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK 0x20
+#define PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT 0x5
+#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK 0x40
+#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT 0x6
+#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK 0x80
+#define PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT 0x7
+#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK 0x7
+#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT 0x0
+#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK 0x70
+#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT 0x4
+#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK 0x80
+#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT 0x7
+#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK 0x300
+#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT 0x8
+#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK 0xfc00
+#define PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT 0xa
+#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK 0x1
+#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT 0x0
+#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK 0x2
+#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT 0x1
+#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK 0x4
+#define PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT 0x2
+#define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK 0x8
+#define PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT 0x3
+#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK 0x1
+#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT 0x0
+#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK 0x2
+#define PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT 0x1
+#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK 0x4
+#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT 0x2
+#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK 0x8
+#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT 0x3
+#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK 0x10
+#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT 0x4
+#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK 0x20
+#define PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT 0x5
+#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK 0x40
+#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT 0x6
+#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK 0x80
+#define PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT 0x7
+#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK 0x7
+#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT 0x0
+#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK 0x70
+#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x4
+#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK 0x80
+#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT 0x7
+#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK 0x300
+#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT 0x8
+#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK 0xfc00
+#define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT 0xa
+#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK 0x1
+#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT 0x0
+#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK 0x2
+#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT 0x1
+#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK 0x4
+#define PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT 0x2
+#define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK 0x8
+#define PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT 0x3
+#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK 0x1
+#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT 0x0
+#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK 0x2
+#define PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT 0x1
+#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK 0x4
+#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT 0x2
+#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK 0x8
+#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT 0x3
+#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK 0x10
+#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT 0x4
+#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK 0x20
+#define PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT 0x5
+#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK 0x40
+#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT 0x6
+#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK 0x80
+#define PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT 0x7
+#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK 0x7
+#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT 0x0
+#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK 0x70
+#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT 0x4
+#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK 0x80
+#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT 0x7
+#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK 0x300
+#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT 0x8
+#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK 0xfc00
+#define PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT 0xa
+#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK 0x1
+#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT 0x0
+#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK 0x2
+#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT 0x1
+#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK 0x4
+#define PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT 0x2
+#define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK 0x8
+#define PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT 0x3
+#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK 0x1
+#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT 0x0
+#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK 0x2
+#define PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT 0x1
+#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK 0x4
+#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT 0x2
+#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK 0x8
+#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT 0x3
+#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK 0x10
+#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT 0x4
+#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK 0x20
+#define PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT 0x5
+#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK 0x40
+#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT 0x6
+#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK 0x80
+#define PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT 0x7
+#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK 0x7
+#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT 0x0
+#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK 0x70
+#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT 0x4
+#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK 0x80
+#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT 0x7
+#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK 0x300
+#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT 0x8
+#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK 0xfc00
+#define PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT 0xa
+#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK 0x1
+#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT 0x0
+#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK 0x2
+#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT 0x1
+#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK 0x4
+#define PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT 0x2
+#define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK 0x8
+#define PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT 0x3
+#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK 0x1
+#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT 0x0
+#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK 0x2
+#define PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT 0x1
+#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK 0x4
+#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT 0x2
+#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK 0x8
+#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT 0x3
+#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK 0x10
+#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT 0x4
+#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK 0x20
+#define PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT 0x5
+#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK 0x40
+#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT 0x6
+#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK 0x80
+#define PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT 0x7
+#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK 0x7
+#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT 0x0
+#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK 0x70
+#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT 0x4
+#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK 0x80
+#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT 0x7
+#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK 0x300
+#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT 0x8
+#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK 0xfc00
+#define PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT 0xa
+#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK 0x1
+#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT 0x0
+#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK 0x2
+#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT 0x1
+#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK 0x4
+#define PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT 0x2
+#define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK 0x8
+#define PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT 0x3
+#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK 0x1
+#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT 0x0
+#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK 0x2
+#define PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT 0x1
+#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK 0x4
+#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT 0x2
+#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK 0x8
+#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT 0x3
+#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK 0x10
+#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT 0x4
+#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK 0x20
+#define PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT 0x5
+#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK 0x40
+#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT 0x6
+#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK 0x80
+#define PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT 0x7
+#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK 0x7
+#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT 0x0
+#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK 0x70
+#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT 0x4
+#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK 0x80
+#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT 0x7
+#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK 0x300
+#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT 0x8
+#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK 0xfc00
+#define PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT 0xa
+#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK 0x1
+#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT 0x0
+#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK 0x2
+#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT 0x1
+#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK 0x4
+#define PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT 0x2
+#define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK 0x8
+#define PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT 0x3
+#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK 0x1
+#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT 0x0
+#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK 0x2
+#define PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT 0x1
+#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK 0x4
+#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT 0x2
+#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK 0x8
+#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT 0x3
+#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK 0x10
+#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT 0x4
+#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK 0x20
+#define PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT 0x5
+#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK 0x40
+#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT 0x6
+#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK 0x80
+#define PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT 0x7
+#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK 0x7
+#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT 0x0
+#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK 0x70
+#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT 0x4
+#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK 0x80
+#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT 0x7
+#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK 0x300
+#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT 0x8
+#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK 0xfc00
+#define PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT 0xa
+#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK 0x1
+#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT 0x0
+#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK 0x2
+#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT 0x1
+#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK 0x4
+#define PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT 0x2
+#define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK 0x8
+#define PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT 0x3
+#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK 0x1
+#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT 0x0
+#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK 0x2
+#define PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT 0x1
+#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK 0x4
+#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT 0x2
+#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK 0x8
+#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT 0x3
+#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK 0x10
+#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT 0x4
+#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK 0x20
+#define PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT 0x5
+#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK 0x40
+#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT 0x6
+#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK 0x80
+#define PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT 0x7
+#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK 0x7
+#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT 0x0
+#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK 0x70
+#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT 0x4
+#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK 0x80
+#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT 0x7
+#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK 0x300
+#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT 0x8
+#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK 0xfc00
+#define PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT 0xa
+#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK 0x1
+#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT 0x0
+#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK 0x2
+#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT 0x1
+#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK 0x4
+#define PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT 0x2
+#define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK 0x8
+#define PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT 0x3
+#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK 0x1
+#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT 0x0
+#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK 0x2
+#define PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT 0x1
+#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK 0x4
+#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT 0x2
+#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK 0x8
+#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT 0x3
+#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK 0x10
+#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT 0x4
+#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK 0x20
+#define PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT 0x5
+#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK 0x40
+#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT 0x6
+#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK 0x80
+#define PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT 0x7
+#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK 0x7
+#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT 0x0
+#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK 0x70
+#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT 0x4
+#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK 0x80
+#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT 0x7
+#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK 0x300
+#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT 0x8
+#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK 0xfc00
+#define PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT 0xa
+#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK 0x1
+#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT 0x0
+#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK 0x2
+#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT 0x1
+#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK 0x4
+#define PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT 0x2
+#define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK 0x8
+#define PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT 0x3
+#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK 0x1
+#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT 0x0
+#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK 0x2
+#define PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT 0x1
+#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK 0x4
+#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT 0x2
+#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK 0x8
+#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT 0x3
+#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK 0x10
+#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT 0x4
+#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK 0x20
+#define PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT 0x5
+#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK 0x40
+#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT 0x6
+#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK 0x80
+#define PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT 0x7
+#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK 0x7
+#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT 0x0
+#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK 0x70
+#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT 0x4
+#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK 0x80
+#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT 0x7
+#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK 0x300
+#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT 0x8
+#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK 0xfc00
+#define PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT 0xa
+#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK 0x1
+#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT 0x0
+#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK 0x2
+#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT 0x1
+#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK 0x4
+#define PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT 0x2
+#define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK 0x8
+#define PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT 0x3
+#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK 0x1
+#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT 0x0
+#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK 0x2
+#define PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT 0x1
+#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK 0x4
+#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT 0x2
+#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK 0x8
+#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT 0x3
+#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK 0x10
+#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT 0x4
+#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK 0x20
+#define PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT 0x5
+#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK 0x40
+#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT 0x6
+#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK 0x80
+#define PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT 0x7
+#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK 0x7
+#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT 0x0
+#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK 0x70
+#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT 0x4
+#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK 0x80
+#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT 0x7
+#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK 0x300
+#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT 0x8
+#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK 0xfc00
+#define PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT 0xa
+#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK 0x1
+#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT 0x0
+#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK 0x2
+#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT 0x1
+#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK 0x4
+#define PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT 0x2
+#define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK 0x8
+#define PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT 0x3
+#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK 0x1
+#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT 0x0
+#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK 0x2
+#define PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT 0x1
+#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK 0x4
+#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT 0x2
+#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK 0x8
+#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT 0x3
+#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK 0x10
+#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT 0x4
+#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK 0x20
+#define PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT 0x5
+#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK 0x40
+#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT 0x6
+#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK 0x80
+#define PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT 0x7
+#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK 0x7
+#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT 0x0
+#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK 0x70
+#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT 0x4
+#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK 0x80
+#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT 0x7
+#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK 0x300
+#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT 0x8
+#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK 0xfc00
+#define PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT 0xa
+#define PB0_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffff
+#define PB0_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x0
+#define PB0_PIF_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define PB0_PIF_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define PB0_PIF_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define PB0_PIF_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define PB0_PIF_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define PB0_PIF_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define PB0_PIF_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define PB0_PIF_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define PB0_PIF_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define PB0_PIF_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define PB0_PIF_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define PB0_PIF_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define PB0_PIF_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define PB0_PIF_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define PB0_PIF_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define PB0_PIF_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define PB0_PIF_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define PB0_PIF_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define PB0_PIF_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define PB0_PIF_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define PB0_PIF_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define PB0_PIF_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define PB0_PIF_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define PB0_PIF_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define PB0_PIF_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define PB0_PIF_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define PB0_PIF_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define PB0_PIF_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define PB0_PIF_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define PB0_PIF_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define PB0_PIF_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define PB0_PIF_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define PB0_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2
+#define PB0_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT 0x1
+#define PB0_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK 0x4
+#define PB0_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2
+#define PB0_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK 0x8
+#define PB0_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT 0x3
+#define PB0_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK 0x10
+#define PB0_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT 0x4
+#define PB0_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK 0x20
+#define PB0_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT 0x5
+#define PB0_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK 0xc0
+#define PB0_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT 0x6
+#define PB0_PIF_STRAP_0__STRAP_RX_EI_FILTER_MASK 0x300
+#define PB0_PIF_STRAP_0__STRAP_RX_EI_FILTER__SHIFT 0x8
+#define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK 0x400
+#define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT 0xa
+#define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK 0x800
+#define PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT 0xb
+#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_12_MASK 0x1000
+#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_12__SHIFT 0xc
+#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_13_MASK 0x2000
+#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_13__SHIFT 0xd
+#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_14_MASK 0x4000
+#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_14__SHIFT 0xe
+#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_15_MASK 0x8000
+#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_15__SHIFT 0xf
+#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_16_MASK 0x10000
+#define PB0_PIF_STRAP_0__STRAP_PIF_BIT_16__SHIFT 0x10
+#define PB0_PIF_CTRL__PIF_PLL_PWRDN_EN_MASK 0x1
+#define PB0_PIF_CTRL__PIF_PLL_PWRDN_EN__SHIFT 0x0
+#define PB0_PIF_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2
+#define PB0_PIF_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT 0x1
+#define PB0_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK 0x4
+#define PB0_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2
+#define PB0_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK 0x8
+#define PB0_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT 0x3
+#define PB0_PIF_CTRL__PHY_RST_PWROK_VDD_MASK 0x10
+#define PB0_PIF_CTRL__PHY_RST_PWROK_VDD__SHIFT 0x4
+#define PB0_PIF_CTRL__PIF_PLL_STATUS_MASK 0xc0
+#define PB0_PIF_CTRL__PIF_PLL_STATUS__SHIFT 0x6
+#define PB0_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK 0x100
+#define PB0_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT 0x8
+#define PB0_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK 0x200
+#define PB0_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT 0x9
+#define PB0_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK 0x400
+#define PB0_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT 0xa
+#define PB0_PIF_CTRL__PIF_PG_EXIT_MODE_MASK 0x800
+#define PB0_PIF_CTRL__PIF_PG_EXIT_MODE__SHIFT 0xb
+#define PB0_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK 0x1000
+#define PB0_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT 0xc
+#define PB0_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK 0x2000
+#define PB0_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT 0xd
+#define PB0_PIF_CTRL__PIF_PG_ABORT_DISABLE_MASK 0x4000
+#define PB0_PIF_CTRL__PIF_PG_ABORT_DISABLE__SHIFT 0xe
+#define PB0_PIF_TX_CTRL__TXPWR_IN_S2_MASK 0x7
+#define PB0_PIF_TX_CTRL__TXPWR_IN_S2__SHIFT 0x0
+#define PB0_PIF_TX_CTRL__TXPWR_IN_SPDCHNG_MASK 0x38
+#define PB0_PIF_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT 0x3
+#define PB0_PIF_TX_CTRL__TXPWR_IN_OFF_MASK 0x1c0
+#define PB0_PIF_TX_CTRL__TXPWR_IN_OFF__SHIFT 0x6
+#define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MASK 0xe00
+#define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT 0x9
+#define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED_MASK 0x7000
+#define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED__SHIFT 0xc
+#define PB0_PIF_TX_CTRL__TXPWR_IN_INIT_MASK 0x38000
+#define PB0_PIF_TX_CTRL__TXPWR_IN_INIT__SHIFT 0xf
+#define PB0_PIF_TX_CTRL__TXPWR_IN_PLL_OFF_MASK 0x1c0000
+#define PB0_PIF_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT 0x12
+#define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK 0x200000
+#define PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT 0x15
+#define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK 0x400000
+#define PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT 0x16
+#define PB0_PIF_TX_CTRL__TXPWR_GATING_IN_L1_MASK 0x800000
+#define PB0_PIF_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT 0x17
+#define PB0_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK 0x1000000
+#define PB0_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT 0x18
+#define PB0_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK 0x7
+#define PB0_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT 0x0
+#define PB0_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK 0x38
+#define PB0_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT 0x3
+#define PB0_PIF_TX_CTRL2__TXPHYSTATUS_DELAY_MASK 0x1c0
+#define PB0_PIF_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT 0x6
+#define PB0_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK 0x200
+#define PB0_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9
+#define PB0_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK 0x400
+#define PB0_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa
+#define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK 0x10000
+#define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT 0x10
+#define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK 0x60000
+#define PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT 0x11
+#define PB0_PIF_TX_CTRL2__TX_FORCE_DATA_VALID_MASK 0x200000
+#define PB0_PIF_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT 0x15
+#define PB0_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK 0x1c00000
+#define PB0_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT 0x16
+#define PB0_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK 0x2000000
+#define PB0_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT 0x19
+#define PB0_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK 0x1c000000
+#define PB0_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT 0x1a
+#define PB0_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK 0x20000000
+#define PB0_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT 0x1d
+#define PB0_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK 0x40000000
+#define PB0_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT 0x1e
+#define PB0_PIF_RX_CTRL__RXPWR_IN_S2_MASK 0x7
+#define PB0_PIF_RX_CTRL__RXPWR_IN_S2__SHIFT 0x0
+#define PB0_PIF_RX_CTRL__RXPWR_IN_SPDCHNG_MASK 0x38
+#define PB0_PIF_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT 0x3
+#define PB0_PIF_RX_CTRL__RXPWR_IN_OFF_MASK 0x1c0
+#define PB0_PIF_RX_CTRL__RXPWR_IN_OFF__SHIFT 0x6
+#define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MASK 0xe00
+#define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT 0x9
+#define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED_MASK 0x7000
+#define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED__SHIFT 0xc
+#define PB0_PIF_RX_CTRL__RXPWR_IN_INIT_MASK 0x38000
+#define PB0_PIF_RX_CTRL__RXPWR_IN_INIT__SHIFT 0xf
+#define PB0_PIF_RX_CTRL__RXPWR_IN_PLL_OFF_MASK 0x1c0000
+#define PB0_PIF_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT 0x12
+#define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK 0x200000
+#define PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT 0x15
+#define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK 0x400000
+#define PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT 0x16
+#define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_L1_MASK 0x800000
+#define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT 0x17
+#define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK 0x1000000
+#define PB0_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT 0x18
+#define PB0_PIF_RX_CTRL__RX_HLD_EIE_COUNT_MASK 0x2000000
+#define PB0_PIF_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT 0x19
+#define PB0_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK 0x4000000
+#define PB0_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT 0x1a
+#define PB0_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK 0x7
+#define PB0_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT 0x0
+#define PB0_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK 0x38
+#define PB0_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT 0x3
+#define PB0_PIF_RX_CTRL2__RXPHYSTATUS_DELAY_MASK 0x1c0
+#define PB0_PIF_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT 0x6
+#define PB0_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK 0x200
+#define PB0_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9
+#define PB0_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK 0x400
+#define PB0_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa
+#define PB0_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK 0x10000
+#define PB0_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT 0x10
+#define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_MODE_MASK 0x60000
+#define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT 0x11
+#define PB0_PIF_RX_CTRL2__EI_DET_ON_TIME_MASK 0x180000
+#define PB0_PIF_RX_CTRL2__EI_DET_ON_TIME__SHIFT 0x13
+#define PB0_PIF_RX_CTRL2__EI_DET_OFF_TIME_MASK 0xe00000
+#define PB0_PIF_RX_CTRL2__EI_DET_OFF_TIME__SHIFT 0x15
+#define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK 0x1000000
+#define PB0_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT 0x18
+#define PB0_PIF_RX_CTRL2__RX_CDR_XTND_MODE_MASK 0x6000000
+#define PB0_PIF_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT 0x19
+#define PB0_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK 0x8000000
+#define PB0_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT 0x1b
+#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK 0x1
+#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x0
+#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2
+#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x1
+#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK 0x4
+#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2
+#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK 0x8
+#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x3
+#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK 0x10
+#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x4
+#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK 0x20
+#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x5
+#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK 0x40
+#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x6
+#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK 0x80
+#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x7
+#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK 0x10000
+#define PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT 0x10
+#define PB0_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK 0x1
+#define PB0_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT 0x0
+#define PB0_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2
+#define PB0_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT 0x1
+#define PB0_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK 0x4
+#define PB0_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2
+#define PB0_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK 0x8
+#define PB0_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT 0x3
+#define PB0_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK 0x10
+#define PB0_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT 0x4
+#define PB0_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK 0x20
+#define PB0_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT 0x5
+#define PB0_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK 0x40
+#define PB0_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT 0x6
+#define PB0_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK 0x80
+#define PB0_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT 0x7
+#define PB0_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK 0x100
+#define PB0_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT 0x8
+#define PB0_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK 0x200
+#define PB0_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT 0x9
+#define PB0_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK 0x400
+#define PB0_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT 0xa
+#define PB0_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK 0x800
+#define PB0_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT 0xb
+#define PB0_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK 0x10000
+#define PB0_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT 0x10
+#define PB0_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK 0x20000
+#define PB0_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT 0x11
+#define PB0_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK 0x100000
+#define PB0_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT 0x14
+#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK 0x1
+#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT 0x0
+#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2
+#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT 0x1
+#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK 0x4
+#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2
+#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK 0x8
+#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT 0x3
+#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK 0x10
+#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT 0x4
+#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK 0x20
+#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT 0x5
+#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK 0x40
+#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT 0x6
+#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK 0x80
+#define PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT 0x7
+#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK 0x100
+#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT 0x8
+#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK 0x200
+#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT 0x9
+#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK 0x400
+#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT 0xa
+#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK 0x800
+#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT 0xb
+#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK 0x1000
+#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT 0xc
+#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK 0x2000
+#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT 0xd
+#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK 0x4000
+#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT 0xe
+#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK 0x8000
+#define PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT 0xf
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK 0x10000
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT 0x10
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK 0x20000
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT 0x11
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK 0x40000
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT 0x12
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK 0x80000
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT 0x13
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK 0x100000
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT 0x14
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK 0x200000
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT 0x15
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK 0x400000
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT 0x16
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK 0x800000
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT 0x17
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK 0x1000000
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT 0x18
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK 0x2000000
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT 0x19
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK 0x4000000
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT 0x1a
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK 0x8000000
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT 0x1b
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK 0x10000000
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT 0x1c
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK 0x20000000
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT 0x1d
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK 0x40000000
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT 0x1e
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK 0x80000000
+#define PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT 0x1f
+#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK 0x3
+#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT 0x0
+#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK 0xc
+#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2
+#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK 0x10
+#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT 0x4
+#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK 0x60
+#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT 0x5
+#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK 0x80
+#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT 0x7
+#define PB0_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK 0x100
+#define PB0_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT 0x8
+#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK 0x200
+#define PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT 0x9
+#define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK 0x1
+#define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT 0x0
+#define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2
+#define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT 0x1
+#define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK 0x4
+#define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2
+#define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG_MASK 0x38
+#define PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG__SHIFT 0x3
+#define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH_MASK 0x40
+#define PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT 0x6
+#define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_MASK 0x180
+#define PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT 0x7
+#define PB0_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK 0x200
+#define PB0_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT 0x9
+#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK 0x10000
+#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT 0x10
+#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK 0x20000
+#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT 0x11
+#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK 0x40000
+#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT 0x12
+#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK 0x80000
+#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT 0x13
+#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK 0x100000
+#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT 0x14
+#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK 0x200000
+#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT 0x15
+#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK 0x400000
+#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT 0x16
+#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK 0x800000
+#define PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT 0x17
+#define PB0_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK 0x1
+#define PB0_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT 0x0
+#define PB0_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2
+#define PB0_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT 0x1
+#define PB0_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK 0x4
+#define PB0_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2
+#define PB0_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK 0x8
+#define PB0_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT 0x3
+#define PB0_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK 0x10
+#define PB0_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT 0x4
+#define PB0_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK 0x20
+#define PB0_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT 0x5
+#define PB0_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK 0x40
+#define PB0_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT 0x6
+#define PB0_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK 0x80
+#define PB0_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT 0x7
+#define PB0_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK 0x100
+#define PB0_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT 0x8
+#define PB0_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK 0x200
+#define PB0_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT 0x9
+#define PB0_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK 0x400
+#define PB0_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT 0xa
+#define PB0_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK 0x800
+#define PB0_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT 0xb
+#define PB0_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK 0x1000
+#define PB0_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT 0xc
+#define PB0_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK 0x2000
+#define PB0_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT 0xd
+#define PB0_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK 0x4000
+#define PB0_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT 0xe
+#define PB0_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK 0x8000
+#define PB0_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT 0xf
+#define PB0_PIF_LANE0_OVRD__CDREN_OVRD_EN_0_MASK 0x10000
+#define PB0_PIF_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT 0x10
+#define PB0_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK 0x20000
+#define PB0_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT 0x11
+#define PB0_PIF_LANE0_OVRD2__GANGMODE_0_MASK 0x7
+#define PB0_PIF_LANE0_OVRD2__GANGMODE_0__SHIFT 0x0
+#define PB0_PIF_LANE0_OVRD2__FREQDIV_0_MASK 0x18
+#define PB0_PIF_LANE0_OVRD2__FREQDIV_0__SHIFT 0x3
+#define PB0_PIF_LANE0_OVRD2__LINKSPEED_0_MASK 0x60
+#define PB0_PIF_LANE0_OVRD2__LINKSPEED_0__SHIFT 0x5
+#define PB0_PIF_LANE0_OVRD2__TWOSYMENABLE_0_MASK 0x80
+#define PB0_PIF_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT 0x7
+#define PB0_PIF_LANE0_OVRD2__TXPWR_0_MASK 0x700
+#define PB0_PIF_LANE0_OVRD2__TXPWR_0__SHIFT 0x8
+#define PB0_PIF_LANE0_OVRD2__TXPGENABLE_0_MASK 0x1800
+#define PB0_PIF_LANE0_OVRD2__TXPGENABLE_0__SHIFT 0xb
+#define PB0_PIF_LANE0_OVRD2__RXPWR_0_MASK 0xe000
+#define PB0_PIF_LANE0_OVRD2__RXPWR_0__SHIFT 0xd
+#define PB0_PIF_LANE0_OVRD2__RXPGENABLE_0_MASK 0x30000
+#define PB0_PIF_LANE0_OVRD2__RXPGENABLE_0__SHIFT 0x10
+#define PB0_PIF_LANE0_OVRD2__ELECIDLEDETEN_0_MASK 0x40000
+#define PB0_PIF_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT 0x12
+#define PB0_PIF_LANE0_OVRD2__ENABLEFOM_0_MASK 0x80000
+#define PB0_PIF_LANE0_OVRD2__ENABLEFOM_0__SHIFT 0x13
+#define PB0_PIF_LANE0_OVRD2__REQUESTFOM_0_MASK 0x100000
+#define PB0_PIF_LANE0_OVRD2__REQUESTFOM_0__SHIFT 0x14
+#define PB0_PIF_LANE0_OVRD2__RESPONSEMODE_0_MASK 0x200000
+#define PB0_PIF_LANE0_OVRD2__RESPONSEMODE_0__SHIFT 0x15
+#define PB0_PIF_LANE0_OVRD2__REQUESTTRK_0_MASK 0x400000
+#define PB0_PIF_LANE0_OVRD2__REQUESTTRK_0__SHIFT 0x16
+#define PB0_PIF_LANE0_OVRD2__REQUESTTRN_0_MASK 0x800000
+#define PB0_PIF_LANE0_OVRD2__REQUESTTRN_0__SHIFT 0x17
+#define PB0_PIF_LANE0_OVRD2__COEFFICIENTID_0_MASK 0x3000000
+#define PB0_PIF_LANE0_OVRD2__COEFFICIENTID_0__SHIFT 0x18
+#define PB0_PIF_LANE0_OVRD2__COEFFICIENT_0_MASK 0xfc000000
+#define PB0_PIF_LANE0_OVRD2__COEFFICIENT_0__SHIFT 0x1a
+#define PB0_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK 0x1
+#define PB0_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT 0x0
+#define PB0_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2
+#define PB0_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT 0x1
+#define PB0_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK 0x4
+#define PB0_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2
+#define PB0_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK 0x8
+#define PB0_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT 0x3
+#define PB0_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK 0x10
+#define PB0_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT 0x4
+#define PB0_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK 0x20
+#define PB0_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT 0x5
+#define PB0_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK 0x40
+#define PB0_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT 0x6
+#define PB0_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK 0x80
+#define PB0_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT 0x7
+#define PB0_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK 0x100
+#define PB0_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT 0x8
+#define PB0_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK 0x200
+#define PB0_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT 0x9
+#define PB0_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK 0x400
+#define PB0_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT 0xa
+#define PB0_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK 0x800
+#define PB0_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT 0xb
+#define PB0_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK 0x1000
+#define PB0_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT 0xc
+#define PB0_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK 0x2000
+#define PB0_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT 0xd
+#define PB0_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK 0x4000
+#define PB0_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT 0xe
+#define PB0_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK 0x8000
+#define PB0_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT 0xf
+#define PB0_PIF_LANE1_OVRD__CDREN_OVRD_EN_1_MASK 0x10000
+#define PB0_PIF_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT 0x10
+#define PB0_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK 0x20000
+#define PB0_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT 0x11
+#define PB0_PIF_LANE1_OVRD2__GANGMODE_1_MASK 0x7
+#define PB0_PIF_LANE1_OVRD2__GANGMODE_1__SHIFT 0x0
+#define PB0_PIF_LANE1_OVRD2__FREQDIV_1_MASK 0x18
+#define PB0_PIF_LANE1_OVRD2__FREQDIV_1__SHIFT 0x3
+#define PB0_PIF_LANE1_OVRD2__LINKSPEED_1_MASK 0x60
+#define PB0_PIF_LANE1_OVRD2__LINKSPEED_1__SHIFT 0x5
+#define PB0_PIF_LANE1_OVRD2__TWOSYMENABLE_1_MASK 0x80
+#define PB0_PIF_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT 0x7
+#define PB0_PIF_LANE1_OVRD2__TXPWR_1_MASK 0x700
+#define PB0_PIF_LANE1_OVRD2__TXPWR_1__SHIFT 0x8
+#define PB0_PIF_LANE1_OVRD2__TXPGENABLE_1_MASK 0x1800
+#define PB0_PIF_LANE1_OVRD2__TXPGENABLE_1__SHIFT 0xb
+#define PB0_PIF_LANE1_OVRD2__RXPWR_1_MASK 0xe000
+#define PB0_PIF_LANE1_OVRD2__RXPWR_1__SHIFT 0xd
+#define PB0_PIF_LANE1_OVRD2__RXPGENABLE_1_MASK 0x30000
+#define PB0_PIF_LANE1_OVRD2__RXPGENABLE_1__SHIFT 0x10
+#define PB0_PIF_LANE1_OVRD2__ELECIDLEDETEN_1_MASK 0x40000
+#define PB0_PIF_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT 0x12
+#define PB0_PIF_LANE1_OVRD2__ENABLEFOM_1_MASK 0x80000
+#define PB0_PIF_LANE1_OVRD2__ENABLEFOM_1__SHIFT 0x13
+#define PB0_PIF_LANE1_OVRD2__REQUESTFOM_1_MASK 0x100000
+#define PB0_PIF_LANE1_OVRD2__REQUESTFOM_1__SHIFT 0x14
+#define PB0_PIF_LANE1_OVRD2__RESPONSEMODE_1_MASK 0x200000
+#define PB0_PIF_LANE1_OVRD2__RESPONSEMODE_1__SHIFT 0x15
+#define PB0_PIF_LANE1_OVRD2__REQUESTTRK_1_MASK 0x400000
+#define PB0_PIF_LANE1_OVRD2__REQUESTTRK_1__SHIFT 0x16
+#define PB0_PIF_LANE1_OVRD2__REQUESTTRN_1_MASK 0x800000
+#define PB0_PIF_LANE1_OVRD2__REQUESTTRN_1__SHIFT 0x17
+#define PB0_PIF_LANE1_OVRD2__COEFFICIENTID_1_MASK 0x3000000
+#define PB0_PIF_LANE1_OVRD2__COEFFICIENTID_1__SHIFT 0x18
+#define PB0_PIF_LANE1_OVRD2__COEFFICIENT_1_MASK 0xfc000000
+#define PB0_PIF_LANE1_OVRD2__COEFFICIENT_1__SHIFT 0x1a
+#define PB0_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK 0x1
+#define PB0_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT 0x0
+#define PB0_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2
+#define PB0_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT 0x1
+#define PB0_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK 0x4
+#define PB0_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2
+#define PB0_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK 0x8
+#define PB0_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT 0x3
+#define PB0_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK 0x10
+#define PB0_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT 0x4
+#define PB0_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK 0x20
+#define PB0_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT 0x5
+#define PB0_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK 0x40
+#define PB0_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT 0x6
+#define PB0_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK 0x80
+#define PB0_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT 0x7
+#define PB0_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK 0x100
+#define PB0_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT 0x8
+#define PB0_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK 0x200
+#define PB0_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT 0x9
+#define PB0_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK 0x400
+#define PB0_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT 0xa
+#define PB0_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK 0x800
+#define PB0_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT 0xb
+#define PB0_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK 0x1000
+#define PB0_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT 0xc
+#define PB0_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK 0x2000
+#define PB0_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT 0xd
+#define PB0_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK 0x4000
+#define PB0_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT 0xe
+#define PB0_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK 0x8000
+#define PB0_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT 0xf
+#define PB0_PIF_LANE2_OVRD__CDREN_OVRD_EN_2_MASK 0x10000
+#define PB0_PIF_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT 0x10
+#define PB0_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK 0x20000
+#define PB0_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT 0x11
+#define PB0_PIF_LANE2_OVRD2__GANGMODE_2_MASK 0x7
+#define PB0_PIF_LANE2_OVRD2__GANGMODE_2__SHIFT 0x0
+#define PB0_PIF_LANE2_OVRD2__FREQDIV_2_MASK 0x18
+#define PB0_PIF_LANE2_OVRD2__FREQDIV_2__SHIFT 0x3
+#define PB0_PIF_LANE2_OVRD2__LINKSPEED_2_MASK 0x60
+#define PB0_PIF_LANE2_OVRD2__LINKSPEED_2__SHIFT 0x5
+#define PB0_PIF_LANE2_OVRD2__TWOSYMENABLE_2_MASK 0x80
+#define PB0_PIF_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT 0x7
+#define PB0_PIF_LANE2_OVRD2__TXPWR_2_MASK 0x700
+#define PB0_PIF_LANE2_OVRD2__TXPWR_2__SHIFT 0x8
+#define PB0_PIF_LANE2_OVRD2__TXPGENABLE_2_MASK 0x1800
+#define PB0_PIF_LANE2_OVRD2__TXPGENABLE_2__SHIFT 0xb
+#define PB0_PIF_LANE2_OVRD2__RXPWR_2_MASK 0xe000
+#define PB0_PIF_LANE2_OVRD2__RXPWR_2__SHIFT 0xd
+#define PB0_PIF_LANE2_OVRD2__RXPGENABLE_2_MASK 0x30000
+#define PB0_PIF_LANE2_OVRD2__RXPGENABLE_2__SHIFT 0x10
+#define PB0_PIF_LANE2_OVRD2__ELECIDLEDETEN_2_MASK 0x40000
+#define PB0_PIF_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT 0x12
+#define PB0_PIF_LANE2_OVRD2__ENABLEFOM_2_MASK 0x80000
+#define PB0_PIF_LANE2_OVRD2__ENABLEFOM_2__SHIFT 0x13
+#define PB0_PIF_LANE2_OVRD2__REQUESTFOM_2_MASK 0x100000
+#define PB0_PIF_LANE2_OVRD2__REQUESTFOM_2__SHIFT 0x14
+#define PB0_PIF_LANE2_OVRD2__RESPONSEMODE_2_MASK 0x200000
+#define PB0_PIF_LANE2_OVRD2__RESPONSEMODE_2__SHIFT 0x15
+#define PB0_PIF_LANE2_OVRD2__REQUESTTRK_2_MASK 0x400000
+#define PB0_PIF_LANE2_OVRD2__REQUESTTRK_2__SHIFT 0x16
+#define PB0_PIF_LANE2_OVRD2__REQUESTTRN_2_MASK 0x800000
+#define PB0_PIF_LANE2_OVRD2__REQUESTTRN_2__SHIFT 0x17
+#define PB0_PIF_LANE2_OVRD2__COEFFICIENTID_2_MASK 0x3000000
+#define PB0_PIF_LANE2_OVRD2__COEFFICIENTID_2__SHIFT 0x18
+#define PB0_PIF_LANE2_OVRD2__COEFFICIENT_2_MASK 0xfc000000
+#define PB0_PIF_LANE2_OVRD2__COEFFICIENT_2__SHIFT 0x1a
+#define PB0_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK 0x1
+#define PB0_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT 0x0
+#define PB0_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2
+#define PB0_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT 0x1
+#define PB0_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK 0x4
+#define PB0_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2
+#define PB0_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK 0x8
+#define PB0_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT 0x3
+#define PB0_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK 0x10
+#define PB0_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT 0x4
+#define PB0_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK 0x20
+#define PB0_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT 0x5
+#define PB0_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK 0x40
+#define PB0_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT 0x6
+#define PB0_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK 0x80
+#define PB0_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT 0x7
+#define PB0_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK 0x100
+#define PB0_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT 0x8
+#define PB0_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK 0x200
+#define PB0_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT 0x9
+#define PB0_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK 0x400
+#define PB0_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT 0xa
+#define PB0_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK 0x800
+#define PB0_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT 0xb
+#define PB0_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK 0x1000
+#define PB0_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT 0xc
+#define PB0_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK 0x2000
+#define PB0_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT 0xd
+#define PB0_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK 0x4000
+#define PB0_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT 0xe
+#define PB0_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK 0x8000
+#define PB0_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT 0xf
+#define PB0_PIF_LANE3_OVRD__CDREN_OVRD_EN_3_MASK 0x10000
+#define PB0_PIF_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT 0x10
+#define PB0_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK 0x20000
+#define PB0_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT 0x11
+#define PB0_PIF_LANE3_OVRD2__GANGMODE_3_MASK 0x7
+#define PB0_PIF_LANE3_OVRD2__GANGMODE_3__SHIFT 0x0
+#define PB0_PIF_LANE3_OVRD2__FREQDIV_3_MASK 0x18
+#define PB0_PIF_LANE3_OVRD2__FREQDIV_3__SHIFT 0x3
+#define PB0_PIF_LANE3_OVRD2__LINKSPEED_3_MASK 0x60
+#define PB0_PIF_LANE3_OVRD2__LINKSPEED_3__SHIFT 0x5
+#define PB0_PIF_LANE3_OVRD2__TWOSYMENABLE_3_MASK 0x80
+#define PB0_PIF_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT 0x7
+#define PB0_PIF_LANE3_OVRD2__TXPWR_3_MASK 0x700
+#define PB0_PIF_LANE3_OVRD2__TXPWR_3__SHIFT 0x8
+#define PB0_PIF_LANE3_OVRD2__TXPGENABLE_3_MASK 0x1800
+#define PB0_PIF_LANE3_OVRD2__TXPGENABLE_3__SHIFT 0xb
+#define PB0_PIF_LANE3_OVRD2__RXPWR_3_MASK 0xe000
+#define PB0_PIF_LANE3_OVRD2__RXPWR_3__SHIFT 0xd
+#define PB0_PIF_LANE3_OVRD2__RXPGENABLE_3_MASK 0x30000
+#define PB0_PIF_LANE3_OVRD2__RXPGENABLE_3__SHIFT 0x10
+#define PB0_PIF_LANE3_OVRD2__ELECIDLEDETEN_3_MASK 0x40000
+#define PB0_PIF_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT 0x12
+#define PB0_PIF_LANE3_OVRD2__ENABLEFOM_3_MASK 0x80000
+#define PB0_PIF_LANE3_OVRD2__ENABLEFOM_3__SHIFT 0x13
+#define PB0_PIF_LANE3_OVRD2__REQUESTFOM_3_MASK 0x100000
+#define PB0_PIF_LANE3_OVRD2__REQUESTFOM_3__SHIFT 0x14
+#define PB0_PIF_LANE3_OVRD2__RESPONSEMODE_3_MASK 0x200000
+#define PB0_PIF_LANE3_OVRD2__RESPONSEMODE_3__SHIFT 0x15
+#define PB0_PIF_LANE3_OVRD2__REQUESTTRK_3_MASK 0x400000
+#define PB0_PIF_LANE3_OVRD2__REQUESTTRK_3__SHIFT 0x16
+#define PB0_PIF_LANE3_OVRD2__REQUESTTRN_3_MASK 0x800000
+#define PB0_PIF_LANE3_OVRD2__REQUESTTRN_3__SHIFT 0x17
+#define PB0_PIF_LANE3_OVRD2__COEFFICIENTID_3_MASK 0x3000000
+#define PB0_PIF_LANE3_OVRD2__COEFFICIENTID_3__SHIFT 0x18
+#define PB0_PIF_LANE3_OVRD2__COEFFICIENT_3_MASK 0xfc000000
+#define PB0_PIF_LANE3_OVRD2__COEFFICIENT_3__SHIFT 0x1a
+#define PB0_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK 0x1
+#define PB0_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT 0x0
+#define PB0_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2
+#define PB0_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT 0x1
+#define PB0_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK 0x4
+#define PB0_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2
+#define PB0_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK 0x8
+#define PB0_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT 0x3
+#define PB0_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK 0x10
+#define PB0_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT 0x4
+#define PB0_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK 0x20
+#define PB0_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT 0x5
+#define PB0_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK 0x40
+#define PB0_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT 0x6
+#define PB0_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK 0x80
+#define PB0_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT 0x7
+#define PB0_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK 0x100
+#define PB0_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT 0x8
+#define PB0_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK 0x200
+#define PB0_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT 0x9
+#define PB0_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK 0x400
+#define PB0_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT 0xa
+#define PB0_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK 0x800
+#define PB0_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT 0xb
+#define PB0_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK 0x1000
+#define PB0_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT 0xc
+#define PB0_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK 0x2000
+#define PB0_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT 0xd
+#define PB0_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK 0x4000
+#define PB0_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT 0xe
+#define PB0_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK 0x8000
+#define PB0_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT 0xf
+#define PB0_PIF_LANE4_OVRD__CDREN_OVRD_EN_4_MASK 0x10000
+#define PB0_PIF_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT 0x10
+#define PB0_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK 0x20000
+#define PB0_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT 0x11
+#define PB0_PIF_LANE4_OVRD2__GANGMODE_4_MASK 0x7
+#define PB0_PIF_LANE4_OVRD2__GANGMODE_4__SHIFT 0x0
+#define PB0_PIF_LANE4_OVRD2__FREQDIV_4_MASK 0x18
+#define PB0_PIF_LANE4_OVRD2__FREQDIV_4__SHIFT 0x3
+#define PB0_PIF_LANE4_OVRD2__LINKSPEED_4_MASK 0x60
+#define PB0_PIF_LANE4_OVRD2__LINKSPEED_4__SHIFT 0x5
+#define PB0_PIF_LANE4_OVRD2__TWOSYMENABLE_4_MASK 0x80
+#define PB0_PIF_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT 0x7
+#define PB0_PIF_LANE4_OVRD2__TXPWR_4_MASK 0x700
+#define PB0_PIF_LANE4_OVRD2__TXPWR_4__SHIFT 0x8
+#define PB0_PIF_LANE4_OVRD2__TXPGENABLE_4_MASK 0x1800
+#define PB0_PIF_LANE4_OVRD2__TXPGENABLE_4__SHIFT 0xb
+#define PB0_PIF_LANE4_OVRD2__RXPWR_4_MASK 0xe000
+#define PB0_PIF_LANE4_OVRD2__RXPWR_4__SHIFT 0xd
+#define PB0_PIF_LANE4_OVRD2__RXPGENABLE_4_MASK 0x30000
+#define PB0_PIF_LANE4_OVRD2__RXPGENABLE_4__SHIFT 0x10
+#define PB0_PIF_LANE4_OVRD2__ELECIDLEDETEN_4_MASK 0x40000
+#define PB0_PIF_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT 0x12
+#define PB0_PIF_LANE4_OVRD2__ENABLEFOM_4_MASK 0x80000
+#define PB0_PIF_LANE4_OVRD2__ENABLEFOM_4__SHIFT 0x13
+#define PB0_PIF_LANE4_OVRD2__REQUESTFOM_4_MASK 0x100000
+#define PB0_PIF_LANE4_OVRD2__REQUESTFOM_4__SHIFT 0x14
+#define PB0_PIF_LANE4_OVRD2__RESPONSEMODE_4_MASK 0x200000
+#define PB0_PIF_LANE4_OVRD2__RESPONSEMODE_4__SHIFT 0x15
+#define PB0_PIF_LANE4_OVRD2__REQUESTTRK_4_MASK 0x400000
+#define PB0_PIF_LANE4_OVRD2__REQUESTTRK_4__SHIFT 0x16
+#define PB0_PIF_LANE4_OVRD2__REQUESTTRN_4_MASK 0x800000
+#define PB0_PIF_LANE4_OVRD2__REQUESTTRN_4__SHIFT 0x17
+#define PB0_PIF_LANE4_OVRD2__COEFFICIENTID_4_MASK 0x3000000
+#define PB0_PIF_LANE4_OVRD2__COEFFICIENTID_4__SHIFT 0x18
+#define PB0_PIF_LANE4_OVRD2__COEFFICIENT_4_MASK 0xfc000000
+#define PB0_PIF_LANE4_OVRD2__COEFFICIENT_4__SHIFT 0x1a
+#define PB0_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK 0x1
+#define PB0_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT 0x0
+#define PB0_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2
+#define PB0_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT 0x1
+#define PB0_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK 0x4
+#define PB0_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2
+#define PB0_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK 0x8
+#define PB0_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT 0x3
+#define PB0_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK 0x10
+#define PB0_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT 0x4
+#define PB0_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK 0x20
+#define PB0_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT 0x5
+#define PB0_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK 0x40
+#define PB0_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT 0x6
+#define PB0_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK 0x80
+#define PB0_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT 0x7
+#define PB0_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK 0x100
+#define PB0_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT 0x8
+#define PB0_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK 0x200
+#define PB0_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT 0x9
+#define PB0_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK 0x400
+#define PB0_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT 0xa
+#define PB0_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK 0x800
+#define PB0_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT 0xb
+#define PB0_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK 0x1000
+#define PB0_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT 0xc
+#define PB0_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK 0x2000
+#define PB0_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT 0xd
+#define PB0_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK 0x4000
+#define PB0_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT 0xe
+#define PB0_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK 0x8000
+#define PB0_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT 0xf
+#define PB0_PIF_LANE5_OVRD__CDREN_OVRD_EN_5_MASK 0x10000
+#define PB0_PIF_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT 0x10
+#define PB0_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK 0x20000
+#define PB0_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT 0x11
+#define PB0_PIF_LANE5_OVRD2__GANGMODE_5_MASK 0x7
+#define PB0_PIF_LANE5_OVRD2__GANGMODE_5__SHIFT 0x0
+#define PB0_PIF_LANE5_OVRD2__FREQDIV_5_MASK 0x18
+#define PB0_PIF_LANE5_OVRD2__FREQDIV_5__SHIFT 0x3
+#define PB0_PIF_LANE5_OVRD2__LINKSPEED_5_MASK 0x60
+#define PB0_PIF_LANE5_OVRD2__LINKSPEED_5__SHIFT 0x5
+#define PB0_PIF_LANE5_OVRD2__TWOSYMENABLE_5_MASK 0x80
+#define PB0_PIF_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT 0x7
+#define PB0_PIF_LANE5_OVRD2__TXPWR_5_MASK 0x700
+#define PB0_PIF_LANE5_OVRD2__TXPWR_5__SHIFT 0x8
+#define PB0_PIF_LANE5_OVRD2__TXPGENABLE_5_MASK 0x1800
+#define PB0_PIF_LANE5_OVRD2__TXPGENABLE_5__SHIFT 0xb
+#define PB0_PIF_LANE5_OVRD2__RXPWR_5_MASK 0xe000
+#define PB0_PIF_LANE5_OVRD2__RXPWR_5__SHIFT 0xd
+#define PB0_PIF_LANE5_OVRD2__RXPGENABLE_5_MASK 0x30000
+#define PB0_PIF_LANE5_OVRD2__RXPGENABLE_5__SHIFT 0x10
+#define PB0_PIF_LANE5_OVRD2__ELECIDLEDETEN_5_MASK 0x40000
+#define PB0_PIF_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT 0x12
+#define PB0_PIF_LANE5_OVRD2__ENABLEFOM_5_MASK 0x80000
+#define PB0_PIF_LANE5_OVRD2__ENABLEFOM_5__SHIFT 0x13
+#define PB0_PIF_LANE5_OVRD2__REQUESTFOM_5_MASK 0x100000
+#define PB0_PIF_LANE5_OVRD2__REQUESTFOM_5__SHIFT 0x14
+#define PB0_PIF_LANE5_OVRD2__RESPONSEMODE_5_MASK 0x200000
+#define PB0_PIF_LANE5_OVRD2__RESPONSEMODE_5__SHIFT 0x15
+#define PB0_PIF_LANE5_OVRD2__REQUESTTRK_5_MASK 0x400000
+#define PB0_PIF_LANE5_OVRD2__REQUESTTRK_5__SHIFT 0x16
+#define PB0_PIF_LANE5_OVRD2__REQUESTTRN_5_MASK 0x800000
+#define PB0_PIF_LANE5_OVRD2__REQUESTTRN_5__SHIFT 0x17
+#define PB0_PIF_LANE5_OVRD2__COEFFICIENTID_5_MASK 0x3000000
+#define PB0_PIF_LANE5_OVRD2__COEFFICIENTID_5__SHIFT 0x18
+#define PB0_PIF_LANE5_OVRD2__COEFFICIENT_5_MASK 0xfc000000
+#define PB0_PIF_LANE5_OVRD2__COEFFICIENT_5__SHIFT 0x1a
+#define PB0_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK 0x1
+#define PB0_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT 0x0
+#define PB0_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2
+#define PB0_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT 0x1
+#define PB0_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK 0x4
+#define PB0_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2
+#define PB0_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK 0x8
+#define PB0_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT 0x3
+#define PB0_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK 0x10
+#define PB0_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT 0x4
+#define PB0_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK 0x20
+#define PB0_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT 0x5
+#define PB0_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK 0x40
+#define PB0_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT 0x6
+#define PB0_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK 0x80
+#define PB0_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT 0x7
+#define PB0_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK 0x100
+#define PB0_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT 0x8
+#define PB0_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK 0x200
+#define PB0_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT 0x9
+#define PB0_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK 0x400
+#define PB0_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT 0xa
+#define PB0_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK 0x800
+#define PB0_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT 0xb
+#define PB0_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK 0x1000
+#define PB0_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT 0xc
+#define PB0_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK 0x2000
+#define PB0_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT 0xd
+#define PB0_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK 0x4000
+#define PB0_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT 0xe
+#define PB0_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK 0x8000
+#define PB0_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT 0xf
+#define PB0_PIF_LANE6_OVRD__CDREN_OVRD_EN_6_MASK 0x10000
+#define PB0_PIF_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT 0x10
+#define PB0_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK 0x20000
+#define PB0_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT 0x11
+#define PB0_PIF_LANE6_OVRD2__GANGMODE_6_MASK 0x7
+#define PB0_PIF_LANE6_OVRD2__GANGMODE_6__SHIFT 0x0
+#define PB0_PIF_LANE6_OVRD2__FREQDIV_6_MASK 0x18
+#define PB0_PIF_LANE6_OVRD2__FREQDIV_6__SHIFT 0x3
+#define PB0_PIF_LANE6_OVRD2__LINKSPEED_6_MASK 0x60
+#define PB0_PIF_LANE6_OVRD2__LINKSPEED_6__SHIFT 0x5
+#define PB0_PIF_LANE6_OVRD2__TWOSYMENABLE_6_MASK 0x80
+#define PB0_PIF_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT 0x7
+#define PB0_PIF_LANE6_OVRD2__TXPWR_6_MASK 0x700
+#define PB0_PIF_LANE6_OVRD2__TXPWR_6__SHIFT 0x8
+#define PB0_PIF_LANE6_OVRD2__TXPGENABLE_6_MASK 0x1800
+#define PB0_PIF_LANE6_OVRD2__TXPGENABLE_6__SHIFT 0xb
+#define PB0_PIF_LANE6_OVRD2__RXPWR_6_MASK 0xe000
+#define PB0_PIF_LANE6_OVRD2__RXPWR_6__SHIFT 0xd
+#define PB0_PIF_LANE6_OVRD2__RXPGENABLE_6_MASK 0x30000
+#define PB0_PIF_LANE6_OVRD2__RXPGENABLE_6__SHIFT 0x10
+#define PB0_PIF_LANE6_OVRD2__ELECIDLEDETEN_6_MASK 0x40000
+#define PB0_PIF_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT 0x12
+#define PB0_PIF_LANE6_OVRD2__ENABLEFOM_6_MASK 0x80000
+#define PB0_PIF_LANE6_OVRD2__ENABLEFOM_6__SHIFT 0x13
+#define PB0_PIF_LANE6_OVRD2__REQUESTFOM_6_MASK 0x100000
+#define PB0_PIF_LANE6_OVRD2__REQUESTFOM_6__SHIFT 0x14
+#define PB0_PIF_LANE6_OVRD2__RESPONSEMODE_6_MASK 0x200000
+#define PB0_PIF_LANE6_OVRD2__RESPONSEMODE_6__SHIFT 0x15
+#define PB0_PIF_LANE6_OVRD2__REQUESTTRK_6_MASK 0x400000
+#define PB0_PIF_LANE6_OVRD2__REQUESTTRK_6__SHIFT 0x16
+#define PB0_PIF_LANE6_OVRD2__REQUESTTRN_6_MASK 0x800000
+#define PB0_PIF_LANE6_OVRD2__REQUESTTRN_6__SHIFT 0x17
+#define PB0_PIF_LANE6_OVRD2__COEFFICIENTID_6_MASK 0x3000000
+#define PB0_PIF_LANE6_OVRD2__COEFFICIENTID_6__SHIFT 0x18
+#define PB0_PIF_LANE6_OVRD2__COEFFICIENT_6_MASK 0xfc000000
+#define PB0_PIF_LANE6_OVRD2__COEFFICIENT_6__SHIFT 0x1a
+#define PB0_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK 0x1
+#define PB0_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT 0x0
+#define PB0_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK 0x2
+#define PB0_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT 0x1
+#define PB0_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK 0x4
+#define PB0_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT 0x2
+#define PB0_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK 0x8
+#define PB0_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT 0x3
+#define PB0_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK 0x10
+#define PB0_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT 0x4
+#define PB0_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK 0x20
+#define PB0_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT 0x5
+#define PB0_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK 0x40
+#define PB0_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT 0x6
+#define PB0_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK 0x80
+#define PB0_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT 0x7
+#define PB0_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK 0x100
+#define PB0_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT 0x8
+#define PB0_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK 0x200
+#define PB0_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT 0x9
+#define PB0_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK 0x400
+#define PB0_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT 0xa
+#define PB0_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK 0x800
+#define PB0_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT 0xb
+#define PB0_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK 0x1000
+#define PB0_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT 0xc
+#define PB0_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK 0x2000
+#define PB0_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT 0xd
+#define PB0_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK 0x4000
+#define PB0_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT 0xe
+#define PB0_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK 0x8000
+#define PB0_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT 0xf
+#define PB0_PIF_LANE7_OVRD__CDREN_OVRD_EN_7_MASK 0x10000
+#define PB0_PIF_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT 0x10
+#define PB0_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK 0x20000
+#define PB0_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT 0x11
+#define PB0_PIF_LANE7_OVRD2__GANGMODE_7_MASK 0x7
+#define PB0_PIF_LANE7_OVRD2__GANGMODE_7__SHIFT 0x0
+#define PB0_PIF_LANE7_OVRD2__FREQDIV_7_MASK 0x18
+#define PB0_PIF_LANE7_OVRD2__FREQDIV_7__SHIFT 0x3
+#define PB0_PIF_LANE7_OVRD2__LINKSPEED_7_MASK 0x60
+#define PB0_PIF_LANE7_OVRD2__LINKSPEED_7__SHIFT 0x5
+#define PB0_PIF_LANE7_OVRD2__TWOSYMENABLE_7_MASK 0x80
+#define PB0_PIF_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT 0x7
+#define PB0_PIF_LANE7_OVRD2__TXPWR_7_MASK 0x700
+#define PB0_PIF_LANE7_OVRD2__TXPWR_7__SHIFT 0x8
+#define PB0_PIF_LANE7_OVRD2__TXPGENABLE_7_MASK 0x1800
+#define PB0_PIF_LANE7_OVRD2__TXPGENABLE_7__SHIFT 0xb
+#define PB0_PIF_LANE7_OVRD2__RXPWR_7_MASK 0xe000
+#define PB0_PIF_LANE7_OVRD2__RXPWR_7__SHIFT 0xd
+#define PB0_PIF_LANE7_OVRD2__RXPGENABLE_7_MASK 0x30000
+#define PB0_PIF_LANE7_OVRD2__RXPGENABLE_7__SHIFT 0x10
+#define PB0_PIF_LANE7_OVRD2__ELECIDLEDETEN_7_MASK 0x40000
+#define PB0_PIF_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT 0x12
+#define PB0_PIF_LANE7_OVRD2__ENABLEFOM_7_MASK 0x80000
+#define PB0_PIF_LANE7_OVRD2__ENABLEFOM_7__SHIFT 0x13
+#define PB0_PIF_LANE7_OVRD2__REQUESTFOM_7_MASK 0x100000
+#define PB0_PIF_LANE7_OVRD2__REQUESTFOM_7__SHIFT 0x14
+#define PB0_PIF_LANE7_OVRD2__RESPONSEMODE_7_MASK 0x200000
+#define PB0_PIF_LANE7_OVRD2__RESPONSEMODE_7__SHIFT 0x15
+#define PB0_PIF_LANE7_OVRD2__REQUESTTRK_7_MASK 0x400000
+#define PB0_PIF_LANE7_OVRD2__REQUESTTRK_7__SHIFT 0x16
+#define PB0_PIF_LANE7_OVRD2__REQUESTTRN_7_MASK 0x800000
+#define PB0_PIF_LANE7_OVRD2__REQUESTTRN_7__SHIFT 0x17
+#define PB0_PIF_LANE7_OVRD2__COEFFICIENTID_7_MASK 0x3000000
+#define PB0_PIF_LANE7_OVRD2__COEFFICIENTID_7__SHIFT 0x18
+#define PB0_PIF_LANE7_OVRD2__COEFFICIENT_7_MASK 0xfc000000
+#define PB0_PIF_LANE7_OVRD2__COEFFICIENT_7__SHIFT 0x1a
+#define PB1_PIF_SCRATCH__PIF_SCRATCH_MASK 0xffffffff
+#define PB1_PIF_SCRATCH__PIF_SCRATCH__SHIFT 0x0
+#define PB1_PIF_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define PB1_PIF_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define PB1_PIF_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define PB1_PIF_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define PB1_PIF_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define PB1_PIF_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define PB1_PIF_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define PB1_PIF_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define PB1_PIF_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define PB1_PIF_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define PB1_PIF_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define PB1_PIF_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define PB1_PIF_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define PB1_PIF_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define PB1_PIF_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define PB1_PIF_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define PB1_PIF_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define PB1_PIF_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define PB1_PIF_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define PB1_PIF_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define PB1_PIF_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define PB1_PIF_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define PB1_PIF_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define PB1_PIF_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define PB1_PIF_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define PB1_PIF_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define PB1_PIF_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define PB1_PIF_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define PB1_PIF_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define PB1_PIF_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define PB1_PIF_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define PB1_PIF_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define PB1_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2
+#define PB1_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT 0x1
+#define PB1_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK 0x4
+#define PB1_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2
+#define PB1_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK 0x8
+#define PB1_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT 0x3
+#define PB1_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK 0x10
+#define PB1_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT 0x4
+#define PB1_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK 0x20
+#define PB1_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT 0x5
+#define PB1_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK 0xc0
+#define PB1_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT 0x6
+#define PB1_PIF_STRAP_0__STRAP_RX_EI_FILTER_MASK 0x300
+#define PB1_PIF_STRAP_0__STRAP_RX_EI_FILTER__SHIFT 0x8
+#define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK 0x400
+#define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT 0xa
+#define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK 0x800
+#define PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT 0xb
+#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_12_MASK 0x1000
+#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_12__SHIFT 0xc
+#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_13_MASK 0x2000
+#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_13__SHIFT 0xd
+#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_14_MASK 0x4000
+#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_14__SHIFT 0xe
+#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_15_MASK 0x8000
+#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_15__SHIFT 0xf
+#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_16_MASK 0x10000
+#define PB1_PIF_STRAP_0__STRAP_PIF_BIT_16__SHIFT 0x10
+#define PB1_PIF_CTRL__PIF_PLL_PWRDN_EN_MASK 0x1
+#define PB1_PIF_CTRL__PIF_PLL_PWRDN_EN__SHIFT 0x0
+#define PB1_PIF_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2
+#define PB1_PIF_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT 0x1
+#define PB1_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK 0x4
+#define PB1_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2
+#define PB1_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK 0x8
+#define PB1_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT 0x3
+#define PB1_PIF_CTRL__PHY_RST_PWROK_VDD_MASK 0x10
+#define PB1_PIF_CTRL__PHY_RST_PWROK_VDD__SHIFT 0x4
+#define PB1_PIF_CTRL__PIF_PLL_STATUS_MASK 0xc0
+#define PB1_PIF_CTRL__PIF_PLL_STATUS__SHIFT 0x6
+#define PB1_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK 0x100
+#define PB1_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT 0x8
+#define PB1_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK 0x200
+#define PB1_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT 0x9
+#define PB1_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK 0x400
+#define PB1_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT 0xa
+#define PB1_PIF_CTRL__PIF_PG_EXIT_MODE_MASK 0x800
+#define PB1_PIF_CTRL__PIF_PG_EXIT_MODE__SHIFT 0xb
+#define PB1_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK 0x1000
+#define PB1_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT 0xc
+#define PB1_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK 0x2000
+#define PB1_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT 0xd
+#define PB1_PIF_CTRL__PIF_PG_ABORT_DISABLE_MASK 0x4000
+#define PB1_PIF_CTRL__PIF_PG_ABORT_DISABLE__SHIFT 0xe
+#define PB1_PIF_TX_CTRL__TXPWR_IN_S2_MASK 0x7
+#define PB1_PIF_TX_CTRL__TXPWR_IN_S2__SHIFT 0x0
+#define PB1_PIF_TX_CTRL__TXPWR_IN_SPDCHNG_MASK 0x38
+#define PB1_PIF_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT 0x3
+#define PB1_PIF_TX_CTRL__TXPWR_IN_OFF_MASK 0x1c0
+#define PB1_PIF_TX_CTRL__TXPWR_IN_OFF__SHIFT 0x6
+#define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MASK 0xe00
+#define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT 0x9
+#define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED_MASK 0x7000
+#define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED__SHIFT 0xc
+#define PB1_PIF_TX_CTRL__TXPWR_IN_INIT_MASK 0x38000
+#define PB1_PIF_TX_CTRL__TXPWR_IN_INIT__SHIFT 0xf
+#define PB1_PIF_TX_CTRL__TXPWR_IN_PLL_OFF_MASK 0x1c0000
+#define PB1_PIF_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT 0x12
+#define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK 0x200000
+#define PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT 0x15
+#define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK 0x400000
+#define PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT 0x16
+#define PB1_PIF_TX_CTRL__TXPWR_GATING_IN_L1_MASK 0x800000
+#define PB1_PIF_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT 0x17
+#define PB1_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK 0x1000000
+#define PB1_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT 0x18
+#define PB1_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK 0x7
+#define PB1_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT 0x0
+#define PB1_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK 0x38
+#define PB1_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT 0x3
+#define PB1_PIF_TX_CTRL2__TXPHYSTATUS_DELAY_MASK 0x1c0
+#define PB1_PIF_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT 0x6
+#define PB1_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK 0x200
+#define PB1_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9
+#define PB1_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK 0x400
+#define PB1_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa
+#define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK 0x10000
+#define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT 0x10
+#define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK 0x60000
+#define PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT 0x11
+#define PB1_PIF_TX_CTRL2__TX_FORCE_DATA_VALID_MASK 0x200000
+#define PB1_PIF_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT 0x15
+#define PB1_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK 0x1c00000
+#define PB1_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT 0x16
+#define PB1_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK 0x2000000
+#define PB1_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT 0x19
+#define PB1_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK 0x1c000000
+#define PB1_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT 0x1a
+#define PB1_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK 0x20000000
+#define PB1_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT 0x1d
+#define PB1_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK 0x40000000
+#define PB1_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT 0x1e
+#define PB1_PIF_RX_CTRL__RXPWR_IN_S2_MASK 0x7
+#define PB1_PIF_RX_CTRL__RXPWR_IN_S2__SHIFT 0x0
+#define PB1_PIF_RX_CTRL__RXPWR_IN_SPDCHNG_MASK 0x38
+#define PB1_PIF_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT 0x3
+#define PB1_PIF_RX_CTRL__RXPWR_IN_OFF_MASK 0x1c0
+#define PB1_PIF_RX_CTRL__RXPWR_IN_OFF__SHIFT 0x6
+#define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MASK 0xe00
+#define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT 0x9
+#define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED_MASK 0x7000
+#define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED__SHIFT 0xc
+#define PB1_PIF_RX_CTRL__RXPWR_IN_INIT_MASK 0x38000
+#define PB1_PIF_RX_CTRL__RXPWR_IN_INIT__SHIFT 0xf
+#define PB1_PIF_RX_CTRL__RXPWR_IN_PLL_OFF_MASK 0x1c0000
+#define PB1_PIF_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT 0x12
+#define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK 0x200000
+#define PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT 0x15
+#define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK 0x400000
+#define PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT 0x16
+#define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_L1_MASK 0x800000
+#define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT 0x17
+#define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK 0x1000000
+#define PB1_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT 0x18
+#define PB1_PIF_RX_CTRL__RX_HLD_EIE_COUNT_MASK 0x2000000
+#define PB1_PIF_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT 0x19
+#define PB1_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK 0x4000000
+#define PB1_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT 0x1a
+#define PB1_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK 0x7
+#define PB1_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT 0x0
+#define PB1_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK 0x38
+#define PB1_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT 0x3
+#define PB1_PIF_RX_CTRL2__RXPHYSTATUS_DELAY_MASK 0x1c0
+#define PB1_PIF_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT 0x6
+#define PB1_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK 0x200
+#define PB1_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9
+#define PB1_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK 0x400
+#define PB1_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa
+#define PB1_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK 0x10000
+#define PB1_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT 0x10
+#define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_MODE_MASK 0x60000
+#define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT 0x11
+#define PB1_PIF_RX_CTRL2__EI_DET_ON_TIME_MASK 0x180000
+#define PB1_PIF_RX_CTRL2__EI_DET_ON_TIME__SHIFT 0x13
+#define PB1_PIF_RX_CTRL2__EI_DET_OFF_TIME_MASK 0xe00000
+#define PB1_PIF_RX_CTRL2__EI_DET_OFF_TIME__SHIFT 0x15
+#define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK 0x1000000
+#define PB1_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT 0x18
+#define PB1_PIF_RX_CTRL2__RX_CDR_XTND_MODE_MASK 0x6000000
+#define PB1_PIF_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT 0x19
+#define PB1_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK 0x8000000
+#define PB1_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT 0x1b
+#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK 0x1
+#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x0
+#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2
+#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x1
+#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK 0x4
+#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2
+#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK 0x8
+#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x3
+#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK 0x10
+#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x4
+#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK 0x20
+#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x5
+#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK 0x40
+#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x6
+#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK 0x80
+#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x7
+#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK 0x10000
+#define PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT 0x10
+#define PB1_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK 0x1
+#define PB1_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT 0x0
+#define PB1_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2
+#define PB1_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT 0x1
+#define PB1_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK 0x4
+#define PB1_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2
+#define PB1_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK 0x8
+#define PB1_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT 0x3
+#define PB1_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK 0x10
+#define PB1_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT 0x4
+#define PB1_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK 0x20
+#define PB1_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT 0x5
+#define PB1_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK 0x40
+#define PB1_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT 0x6
+#define PB1_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK 0x80
+#define PB1_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT 0x7
+#define PB1_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK 0x100
+#define PB1_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT 0x8
+#define PB1_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK 0x200
+#define PB1_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT 0x9
+#define PB1_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK 0x400
+#define PB1_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT 0xa
+#define PB1_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK 0x800
+#define PB1_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT 0xb
+#define PB1_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK 0x10000
+#define PB1_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT 0x10
+#define PB1_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK 0x20000
+#define PB1_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT 0x11
+#define PB1_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK 0x100000
+#define PB1_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT 0x14
+#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK 0x1
+#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT 0x0
+#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2
+#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT 0x1
+#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK 0x4
+#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2
+#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK 0x8
+#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT 0x3
+#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK 0x10
+#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT 0x4
+#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK 0x20
+#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT 0x5
+#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK 0x40
+#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT 0x6
+#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK 0x80
+#define PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT 0x7
+#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK 0x100
+#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT 0x8
+#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK 0x200
+#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT 0x9
+#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK 0x400
+#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT 0xa
+#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK 0x800
+#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT 0xb
+#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK 0x1000
+#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT 0xc
+#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK 0x2000
+#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT 0xd
+#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK 0x4000
+#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT 0xe
+#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK 0x8000
+#define PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT 0xf
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK 0x10000
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT 0x10
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK 0x20000
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT 0x11
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK 0x40000
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT 0x12
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK 0x80000
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT 0x13
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK 0x100000
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT 0x14
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK 0x200000
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT 0x15
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK 0x400000
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT 0x16
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK 0x800000
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT 0x17
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK 0x1000000
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT 0x18
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK 0x2000000
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT 0x19
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK 0x4000000
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT 0x1a
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK 0x8000000
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT 0x1b
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK 0x10000000
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT 0x1c
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK 0x20000000
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT 0x1d
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK 0x40000000
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT 0x1e
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK 0x80000000
+#define PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT 0x1f
+#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK 0x3
+#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT 0x0
+#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK 0xc
+#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2
+#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK 0x10
+#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT 0x4
+#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK 0x60
+#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT 0x5
+#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK 0x80
+#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT 0x7
+#define PB1_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK 0x100
+#define PB1_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT 0x8
+#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK 0x200
+#define PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT 0x9
+#define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK 0x1
+#define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT 0x0
+#define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2
+#define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT 0x1
+#define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK 0x4
+#define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2
+#define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG_MASK 0x38
+#define PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG__SHIFT 0x3
+#define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH_MASK 0x40
+#define PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT 0x6
+#define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_MASK 0x180
+#define PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT 0x7
+#define PB1_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK 0x200
+#define PB1_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT 0x9
+#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK 0x10000
+#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT 0x10
+#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK 0x20000
+#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT 0x11
+#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK 0x40000
+#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT 0x12
+#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK 0x80000
+#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT 0x13
+#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK 0x100000
+#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT 0x14
+#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK 0x200000
+#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT 0x15
+#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK 0x400000
+#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT 0x16
+#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK 0x800000
+#define PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT 0x17
+#define PB1_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK 0x1
+#define PB1_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT 0x0
+#define PB1_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2
+#define PB1_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT 0x1
+#define PB1_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK 0x4
+#define PB1_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2
+#define PB1_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK 0x8
+#define PB1_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT 0x3
+#define PB1_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK 0x10
+#define PB1_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT 0x4
+#define PB1_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK 0x20
+#define PB1_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT 0x5
+#define PB1_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK 0x40
+#define PB1_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT 0x6
+#define PB1_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK 0x80
+#define PB1_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT 0x7
+#define PB1_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK 0x100
+#define PB1_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT 0x8
+#define PB1_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK 0x200
+#define PB1_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT 0x9
+#define PB1_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK 0x400
+#define PB1_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT 0xa
+#define PB1_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK 0x800
+#define PB1_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT 0xb
+#define PB1_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK 0x1000
+#define PB1_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT 0xc
+#define PB1_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK 0x2000
+#define PB1_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT 0xd
+#define PB1_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK 0x4000
+#define PB1_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT 0xe
+#define PB1_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK 0x8000
+#define PB1_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT 0xf
+#define PB1_PIF_LANE0_OVRD__CDREN_OVRD_EN_0_MASK 0x10000
+#define PB1_PIF_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT 0x10
+#define PB1_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK 0x20000
+#define PB1_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT 0x11
+#define PB1_PIF_LANE0_OVRD2__GANGMODE_0_MASK 0x7
+#define PB1_PIF_LANE0_OVRD2__GANGMODE_0__SHIFT 0x0
+#define PB1_PIF_LANE0_OVRD2__FREQDIV_0_MASK 0x18
+#define PB1_PIF_LANE0_OVRD2__FREQDIV_0__SHIFT 0x3
+#define PB1_PIF_LANE0_OVRD2__LINKSPEED_0_MASK 0x60
+#define PB1_PIF_LANE0_OVRD2__LINKSPEED_0__SHIFT 0x5
+#define PB1_PIF_LANE0_OVRD2__TWOSYMENABLE_0_MASK 0x80
+#define PB1_PIF_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT 0x7
+#define PB1_PIF_LANE0_OVRD2__TXPWR_0_MASK 0x700
+#define PB1_PIF_LANE0_OVRD2__TXPWR_0__SHIFT 0x8
+#define PB1_PIF_LANE0_OVRD2__TXPGENABLE_0_MASK 0x1800
+#define PB1_PIF_LANE0_OVRD2__TXPGENABLE_0__SHIFT 0xb
+#define PB1_PIF_LANE0_OVRD2__RXPWR_0_MASK 0xe000
+#define PB1_PIF_LANE0_OVRD2__RXPWR_0__SHIFT 0xd
+#define PB1_PIF_LANE0_OVRD2__RXPGENABLE_0_MASK 0x30000
+#define PB1_PIF_LANE0_OVRD2__RXPGENABLE_0__SHIFT 0x10
+#define PB1_PIF_LANE0_OVRD2__ELECIDLEDETEN_0_MASK 0x40000
+#define PB1_PIF_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT 0x12
+#define PB1_PIF_LANE0_OVRD2__ENABLEFOM_0_MASK 0x80000
+#define PB1_PIF_LANE0_OVRD2__ENABLEFOM_0__SHIFT 0x13
+#define PB1_PIF_LANE0_OVRD2__REQUESTFOM_0_MASK 0x100000
+#define PB1_PIF_LANE0_OVRD2__REQUESTFOM_0__SHIFT 0x14
+#define PB1_PIF_LANE0_OVRD2__RESPONSEMODE_0_MASK 0x200000
+#define PB1_PIF_LANE0_OVRD2__RESPONSEMODE_0__SHIFT 0x15
+#define PB1_PIF_LANE0_OVRD2__REQUESTTRK_0_MASK 0x400000
+#define PB1_PIF_LANE0_OVRD2__REQUESTTRK_0__SHIFT 0x16
+#define PB1_PIF_LANE0_OVRD2__REQUESTTRN_0_MASK 0x800000
+#define PB1_PIF_LANE0_OVRD2__REQUESTTRN_0__SHIFT 0x17
+#define PB1_PIF_LANE0_OVRD2__COEFFICIENTID_0_MASK 0x3000000
+#define PB1_PIF_LANE0_OVRD2__COEFFICIENTID_0__SHIFT 0x18
+#define PB1_PIF_LANE0_OVRD2__COEFFICIENT_0_MASK 0xfc000000
+#define PB1_PIF_LANE0_OVRD2__COEFFICIENT_0__SHIFT 0x1a
+#define PB1_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK 0x1
+#define PB1_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT 0x0
+#define PB1_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2
+#define PB1_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT 0x1
+#define PB1_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK 0x4
+#define PB1_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2
+#define PB1_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK 0x8
+#define PB1_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT 0x3
+#define PB1_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK 0x10
+#define PB1_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT 0x4
+#define PB1_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK 0x20
+#define PB1_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT 0x5
+#define PB1_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK 0x40
+#define PB1_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT 0x6
+#define PB1_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK 0x80
+#define PB1_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT 0x7
+#define PB1_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK 0x100
+#define PB1_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT 0x8
+#define PB1_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK 0x200
+#define PB1_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT 0x9
+#define PB1_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK 0x400
+#define PB1_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT 0xa
+#define PB1_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK 0x800
+#define PB1_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT 0xb
+#define PB1_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK 0x1000
+#define PB1_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT 0xc
+#define PB1_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK 0x2000
+#define PB1_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT 0xd
+#define PB1_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK 0x4000
+#define PB1_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT 0xe
+#define PB1_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK 0x8000
+#define PB1_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT 0xf
+#define PB1_PIF_LANE1_OVRD__CDREN_OVRD_EN_1_MASK 0x10000
+#define PB1_PIF_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT 0x10
+#define PB1_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK 0x20000
+#define PB1_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT 0x11
+#define PB1_PIF_LANE1_OVRD2__GANGMODE_1_MASK 0x7
+#define PB1_PIF_LANE1_OVRD2__GANGMODE_1__SHIFT 0x0
+#define PB1_PIF_LANE1_OVRD2__FREQDIV_1_MASK 0x18
+#define PB1_PIF_LANE1_OVRD2__FREQDIV_1__SHIFT 0x3
+#define PB1_PIF_LANE1_OVRD2__LINKSPEED_1_MASK 0x60
+#define PB1_PIF_LANE1_OVRD2__LINKSPEED_1__SHIFT 0x5
+#define PB1_PIF_LANE1_OVRD2__TWOSYMENABLE_1_MASK 0x80
+#define PB1_PIF_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT 0x7
+#define PB1_PIF_LANE1_OVRD2__TXPWR_1_MASK 0x700
+#define PB1_PIF_LANE1_OVRD2__TXPWR_1__SHIFT 0x8
+#define PB1_PIF_LANE1_OVRD2__TXPGENABLE_1_MASK 0x1800
+#define PB1_PIF_LANE1_OVRD2__TXPGENABLE_1__SHIFT 0xb
+#define PB1_PIF_LANE1_OVRD2__RXPWR_1_MASK 0xe000
+#define PB1_PIF_LANE1_OVRD2__RXPWR_1__SHIFT 0xd
+#define PB1_PIF_LANE1_OVRD2__RXPGENABLE_1_MASK 0x30000
+#define PB1_PIF_LANE1_OVRD2__RXPGENABLE_1__SHIFT 0x10
+#define PB1_PIF_LANE1_OVRD2__ELECIDLEDETEN_1_MASK 0x40000
+#define PB1_PIF_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT 0x12
+#define PB1_PIF_LANE1_OVRD2__ENABLEFOM_1_MASK 0x80000
+#define PB1_PIF_LANE1_OVRD2__ENABLEFOM_1__SHIFT 0x13
+#define PB1_PIF_LANE1_OVRD2__REQUESTFOM_1_MASK 0x100000
+#define PB1_PIF_LANE1_OVRD2__REQUESTFOM_1__SHIFT 0x14
+#define PB1_PIF_LANE1_OVRD2__RESPONSEMODE_1_MASK 0x200000
+#define PB1_PIF_LANE1_OVRD2__RESPONSEMODE_1__SHIFT 0x15
+#define PB1_PIF_LANE1_OVRD2__REQUESTTRK_1_MASK 0x400000
+#define PB1_PIF_LANE1_OVRD2__REQUESTTRK_1__SHIFT 0x16
+#define PB1_PIF_LANE1_OVRD2__REQUESTTRN_1_MASK 0x800000
+#define PB1_PIF_LANE1_OVRD2__REQUESTTRN_1__SHIFT 0x17
+#define PB1_PIF_LANE1_OVRD2__COEFFICIENTID_1_MASK 0x3000000
+#define PB1_PIF_LANE1_OVRD2__COEFFICIENTID_1__SHIFT 0x18
+#define PB1_PIF_LANE1_OVRD2__COEFFICIENT_1_MASK 0xfc000000
+#define PB1_PIF_LANE1_OVRD2__COEFFICIENT_1__SHIFT 0x1a
+#define PB1_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK 0x1
+#define PB1_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT 0x0
+#define PB1_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2
+#define PB1_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT 0x1
+#define PB1_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK 0x4
+#define PB1_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2
+#define PB1_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK 0x8
+#define PB1_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT 0x3
+#define PB1_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK 0x10
+#define PB1_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT 0x4
+#define PB1_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK 0x20
+#define PB1_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT 0x5
+#define PB1_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK 0x40
+#define PB1_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT 0x6
+#define PB1_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK 0x80
+#define PB1_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT 0x7
+#define PB1_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK 0x100
+#define PB1_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT 0x8
+#define PB1_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK 0x200
+#define PB1_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT 0x9
+#define PB1_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK 0x400
+#define PB1_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT 0xa
+#define PB1_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK 0x800
+#define PB1_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT 0xb
+#define PB1_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK 0x1000
+#define PB1_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT 0xc
+#define PB1_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK 0x2000
+#define PB1_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT 0xd
+#define PB1_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK 0x4000
+#define PB1_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT 0xe
+#define PB1_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK 0x8000
+#define PB1_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT 0xf
+#define PB1_PIF_LANE2_OVRD__CDREN_OVRD_EN_2_MASK 0x10000
+#define PB1_PIF_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT 0x10
+#define PB1_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK 0x20000
+#define PB1_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT 0x11
+#define PB1_PIF_LANE2_OVRD2__GANGMODE_2_MASK 0x7
+#define PB1_PIF_LANE2_OVRD2__GANGMODE_2__SHIFT 0x0
+#define PB1_PIF_LANE2_OVRD2__FREQDIV_2_MASK 0x18
+#define PB1_PIF_LANE2_OVRD2__FREQDIV_2__SHIFT 0x3
+#define PB1_PIF_LANE2_OVRD2__LINKSPEED_2_MASK 0x60
+#define PB1_PIF_LANE2_OVRD2__LINKSPEED_2__SHIFT 0x5
+#define PB1_PIF_LANE2_OVRD2__TWOSYMENABLE_2_MASK 0x80
+#define PB1_PIF_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT 0x7
+#define PB1_PIF_LANE2_OVRD2__TXPWR_2_MASK 0x700
+#define PB1_PIF_LANE2_OVRD2__TXPWR_2__SHIFT 0x8
+#define PB1_PIF_LANE2_OVRD2__TXPGENABLE_2_MASK 0x1800
+#define PB1_PIF_LANE2_OVRD2__TXPGENABLE_2__SHIFT 0xb
+#define PB1_PIF_LANE2_OVRD2__RXPWR_2_MASK 0xe000
+#define PB1_PIF_LANE2_OVRD2__RXPWR_2__SHIFT 0xd
+#define PB1_PIF_LANE2_OVRD2__RXPGENABLE_2_MASK 0x30000
+#define PB1_PIF_LANE2_OVRD2__RXPGENABLE_2__SHIFT 0x10
+#define PB1_PIF_LANE2_OVRD2__ELECIDLEDETEN_2_MASK 0x40000
+#define PB1_PIF_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT 0x12
+#define PB1_PIF_LANE2_OVRD2__ENABLEFOM_2_MASK 0x80000
+#define PB1_PIF_LANE2_OVRD2__ENABLEFOM_2__SHIFT 0x13
+#define PB1_PIF_LANE2_OVRD2__REQUESTFOM_2_MASK 0x100000
+#define PB1_PIF_LANE2_OVRD2__REQUESTFOM_2__SHIFT 0x14
+#define PB1_PIF_LANE2_OVRD2__RESPONSEMODE_2_MASK 0x200000
+#define PB1_PIF_LANE2_OVRD2__RESPONSEMODE_2__SHIFT 0x15
+#define PB1_PIF_LANE2_OVRD2__REQUESTTRK_2_MASK 0x400000
+#define PB1_PIF_LANE2_OVRD2__REQUESTTRK_2__SHIFT 0x16
+#define PB1_PIF_LANE2_OVRD2__REQUESTTRN_2_MASK 0x800000
+#define PB1_PIF_LANE2_OVRD2__REQUESTTRN_2__SHIFT 0x17
+#define PB1_PIF_LANE2_OVRD2__COEFFICIENTID_2_MASK 0x3000000
+#define PB1_PIF_LANE2_OVRD2__COEFFICIENTID_2__SHIFT 0x18
+#define PB1_PIF_LANE2_OVRD2__COEFFICIENT_2_MASK 0xfc000000
+#define PB1_PIF_LANE2_OVRD2__COEFFICIENT_2__SHIFT 0x1a
+#define PB1_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK 0x1
+#define PB1_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT 0x0
+#define PB1_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2
+#define PB1_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT 0x1
+#define PB1_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK 0x4
+#define PB1_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2
+#define PB1_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK 0x8
+#define PB1_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT 0x3
+#define PB1_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK 0x10
+#define PB1_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT 0x4
+#define PB1_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK 0x20
+#define PB1_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT 0x5
+#define PB1_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK 0x40
+#define PB1_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT 0x6
+#define PB1_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK 0x80
+#define PB1_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT 0x7
+#define PB1_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK 0x100
+#define PB1_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT 0x8
+#define PB1_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK 0x200
+#define PB1_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT 0x9
+#define PB1_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK 0x400
+#define PB1_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT 0xa
+#define PB1_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK 0x800
+#define PB1_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT 0xb
+#define PB1_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK 0x1000
+#define PB1_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT 0xc
+#define PB1_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK 0x2000
+#define PB1_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT 0xd
+#define PB1_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK 0x4000
+#define PB1_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT 0xe
+#define PB1_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK 0x8000
+#define PB1_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT 0xf
+#define PB1_PIF_LANE3_OVRD__CDREN_OVRD_EN_3_MASK 0x10000
+#define PB1_PIF_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT 0x10
+#define PB1_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK 0x20000
+#define PB1_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT 0x11
+#define PB1_PIF_LANE3_OVRD2__GANGMODE_3_MASK 0x7
+#define PB1_PIF_LANE3_OVRD2__GANGMODE_3__SHIFT 0x0
+#define PB1_PIF_LANE3_OVRD2__FREQDIV_3_MASK 0x18
+#define PB1_PIF_LANE3_OVRD2__FREQDIV_3__SHIFT 0x3
+#define PB1_PIF_LANE3_OVRD2__LINKSPEED_3_MASK 0x60
+#define PB1_PIF_LANE3_OVRD2__LINKSPEED_3__SHIFT 0x5
+#define PB1_PIF_LANE3_OVRD2__TWOSYMENABLE_3_MASK 0x80
+#define PB1_PIF_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT 0x7
+#define PB1_PIF_LANE3_OVRD2__TXPWR_3_MASK 0x700
+#define PB1_PIF_LANE3_OVRD2__TXPWR_3__SHIFT 0x8
+#define PB1_PIF_LANE3_OVRD2__TXPGENABLE_3_MASK 0x1800
+#define PB1_PIF_LANE3_OVRD2__TXPGENABLE_3__SHIFT 0xb
+#define PB1_PIF_LANE3_OVRD2__RXPWR_3_MASK 0xe000
+#define PB1_PIF_LANE3_OVRD2__RXPWR_3__SHIFT 0xd
+#define PB1_PIF_LANE3_OVRD2__RXPGENABLE_3_MASK 0x30000
+#define PB1_PIF_LANE3_OVRD2__RXPGENABLE_3__SHIFT 0x10
+#define PB1_PIF_LANE3_OVRD2__ELECIDLEDETEN_3_MASK 0x40000
+#define PB1_PIF_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT 0x12
+#define PB1_PIF_LANE3_OVRD2__ENABLEFOM_3_MASK 0x80000
+#define PB1_PIF_LANE3_OVRD2__ENABLEFOM_3__SHIFT 0x13
+#define PB1_PIF_LANE3_OVRD2__REQUESTFOM_3_MASK 0x100000
+#define PB1_PIF_LANE3_OVRD2__REQUESTFOM_3__SHIFT 0x14
+#define PB1_PIF_LANE3_OVRD2__RESPONSEMODE_3_MASK 0x200000
+#define PB1_PIF_LANE3_OVRD2__RESPONSEMODE_3__SHIFT 0x15
+#define PB1_PIF_LANE3_OVRD2__REQUESTTRK_3_MASK 0x400000
+#define PB1_PIF_LANE3_OVRD2__REQUESTTRK_3__SHIFT 0x16
+#define PB1_PIF_LANE3_OVRD2__REQUESTTRN_3_MASK 0x800000
+#define PB1_PIF_LANE3_OVRD2__REQUESTTRN_3__SHIFT 0x17
+#define PB1_PIF_LANE3_OVRD2__COEFFICIENTID_3_MASK 0x3000000
+#define PB1_PIF_LANE3_OVRD2__COEFFICIENTID_3__SHIFT 0x18
+#define PB1_PIF_LANE3_OVRD2__COEFFICIENT_3_MASK 0xfc000000
+#define PB1_PIF_LANE3_OVRD2__COEFFICIENT_3__SHIFT 0x1a
+#define PB1_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK 0x1
+#define PB1_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT 0x0
+#define PB1_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2
+#define PB1_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT 0x1
+#define PB1_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK 0x4
+#define PB1_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2
+#define PB1_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK 0x8
+#define PB1_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT 0x3
+#define PB1_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK 0x10
+#define PB1_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT 0x4
+#define PB1_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK 0x20
+#define PB1_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT 0x5
+#define PB1_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK 0x40
+#define PB1_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT 0x6
+#define PB1_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK 0x80
+#define PB1_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT 0x7
+#define PB1_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK 0x100
+#define PB1_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT 0x8
+#define PB1_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK 0x200
+#define PB1_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT 0x9
+#define PB1_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK 0x400
+#define PB1_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT 0xa
+#define PB1_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK 0x800
+#define PB1_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT 0xb
+#define PB1_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK 0x1000
+#define PB1_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT 0xc
+#define PB1_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK 0x2000
+#define PB1_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT 0xd
+#define PB1_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK 0x4000
+#define PB1_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT 0xe
+#define PB1_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK 0x8000
+#define PB1_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT 0xf
+#define PB1_PIF_LANE4_OVRD__CDREN_OVRD_EN_4_MASK 0x10000
+#define PB1_PIF_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT 0x10
+#define PB1_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK 0x20000
+#define PB1_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT 0x11
+#define PB1_PIF_LANE4_OVRD2__GANGMODE_4_MASK 0x7
+#define PB1_PIF_LANE4_OVRD2__GANGMODE_4__SHIFT 0x0
+#define PB1_PIF_LANE4_OVRD2__FREQDIV_4_MASK 0x18
+#define PB1_PIF_LANE4_OVRD2__FREQDIV_4__SHIFT 0x3
+#define PB1_PIF_LANE4_OVRD2__LINKSPEED_4_MASK 0x60
+#define PB1_PIF_LANE4_OVRD2__LINKSPEED_4__SHIFT 0x5
+#define PB1_PIF_LANE4_OVRD2__TWOSYMENABLE_4_MASK 0x80
+#define PB1_PIF_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT 0x7
+#define PB1_PIF_LANE4_OVRD2__TXPWR_4_MASK 0x700
+#define PB1_PIF_LANE4_OVRD2__TXPWR_4__SHIFT 0x8
+#define PB1_PIF_LANE4_OVRD2__TXPGENABLE_4_MASK 0x1800
+#define PB1_PIF_LANE4_OVRD2__TXPGENABLE_4__SHIFT 0xb
+#define PB1_PIF_LANE4_OVRD2__RXPWR_4_MASK 0xe000
+#define PB1_PIF_LANE4_OVRD2__RXPWR_4__SHIFT 0xd
+#define PB1_PIF_LANE4_OVRD2__RXPGENABLE_4_MASK 0x30000
+#define PB1_PIF_LANE4_OVRD2__RXPGENABLE_4__SHIFT 0x10
+#define PB1_PIF_LANE4_OVRD2__ELECIDLEDETEN_4_MASK 0x40000
+#define PB1_PIF_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT 0x12
+#define PB1_PIF_LANE4_OVRD2__ENABLEFOM_4_MASK 0x80000
+#define PB1_PIF_LANE4_OVRD2__ENABLEFOM_4__SHIFT 0x13
+#define PB1_PIF_LANE4_OVRD2__REQUESTFOM_4_MASK 0x100000
+#define PB1_PIF_LANE4_OVRD2__REQUESTFOM_4__SHIFT 0x14
+#define PB1_PIF_LANE4_OVRD2__RESPONSEMODE_4_MASK 0x200000
+#define PB1_PIF_LANE4_OVRD2__RESPONSEMODE_4__SHIFT 0x15
+#define PB1_PIF_LANE4_OVRD2__REQUESTTRK_4_MASK 0x400000
+#define PB1_PIF_LANE4_OVRD2__REQUESTTRK_4__SHIFT 0x16
+#define PB1_PIF_LANE4_OVRD2__REQUESTTRN_4_MASK 0x800000
+#define PB1_PIF_LANE4_OVRD2__REQUESTTRN_4__SHIFT 0x17
+#define PB1_PIF_LANE4_OVRD2__COEFFICIENTID_4_MASK 0x3000000
+#define PB1_PIF_LANE4_OVRD2__COEFFICIENTID_4__SHIFT 0x18
+#define PB1_PIF_LANE4_OVRD2__COEFFICIENT_4_MASK 0xfc000000
+#define PB1_PIF_LANE4_OVRD2__COEFFICIENT_4__SHIFT 0x1a
+#define PB1_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK 0x1
+#define PB1_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT 0x0
+#define PB1_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2
+#define PB1_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT 0x1
+#define PB1_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK 0x4
+#define PB1_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2
+#define PB1_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK 0x8
+#define PB1_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT 0x3
+#define PB1_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK 0x10
+#define PB1_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT 0x4
+#define PB1_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK 0x20
+#define PB1_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT 0x5
+#define PB1_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK 0x40
+#define PB1_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT 0x6
+#define PB1_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK 0x80
+#define PB1_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT 0x7
+#define PB1_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK 0x100
+#define PB1_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT 0x8
+#define PB1_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK 0x200
+#define PB1_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT 0x9
+#define PB1_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK 0x400
+#define PB1_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT 0xa
+#define PB1_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK 0x800
+#define PB1_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT 0xb
+#define PB1_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK 0x1000
+#define PB1_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT 0xc
+#define PB1_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK 0x2000
+#define PB1_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT 0xd
+#define PB1_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK 0x4000
+#define PB1_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT 0xe
+#define PB1_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK 0x8000
+#define PB1_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT 0xf
+#define PB1_PIF_LANE5_OVRD__CDREN_OVRD_EN_5_MASK 0x10000
+#define PB1_PIF_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT 0x10
+#define PB1_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK 0x20000
+#define PB1_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT 0x11
+#define PB1_PIF_LANE5_OVRD2__GANGMODE_5_MASK 0x7
+#define PB1_PIF_LANE5_OVRD2__GANGMODE_5__SHIFT 0x0
+#define PB1_PIF_LANE5_OVRD2__FREQDIV_5_MASK 0x18
+#define PB1_PIF_LANE5_OVRD2__FREQDIV_5__SHIFT 0x3
+#define PB1_PIF_LANE5_OVRD2__LINKSPEED_5_MASK 0x60
+#define PB1_PIF_LANE5_OVRD2__LINKSPEED_5__SHIFT 0x5
+#define PB1_PIF_LANE5_OVRD2__TWOSYMENABLE_5_MASK 0x80
+#define PB1_PIF_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT 0x7
+#define PB1_PIF_LANE5_OVRD2__TXPWR_5_MASK 0x700
+#define PB1_PIF_LANE5_OVRD2__TXPWR_5__SHIFT 0x8
+#define PB1_PIF_LANE5_OVRD2__TXPGENABLE_5_MASK 0x1800
+#define PB1_PIF_LANE5_OVRD2__TXPGENABLE_5__SHIFT 0xb
+#define PB1_PIF_LANE5_OVRD2__RXPWR_5_MASK 0xe000
+#define PB1_PIF_LANE5_OVRD2__RXPWR_5__SHIFT 0xd
+#define PB1_PIF_LANE5_OVRD2__RXPGENABLE_5_MASK 0x30000
+#define PB1_PIF_LANE5_OVRD2__RXPGENABLE_5__SHIFT 0x10
+#define PB1_PIF_LANE5_OVRD2__ELECIDLEDETEN_5_MASK 0x40000
+#define PB1_PIF_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT 0x12
+#define PB1_PIF_LANE5_OVRD2__ENABLEFOM_5_MASK 0x80000
+#define PB1_PIF_LANE5_OVRD2__ENABLEFOM_5__SHIFT 0x13
+#define PB1_PIF_LANE5_OVRD2__REQUESTFOM_5_MASK 0x100000
+#define PB1_PIF_LANE5_OVRD2__REQUESTFOM_5__SHIFT 0x14
+#define PB1_PIF_LANE5_OVRD2__RESPONSEMODE_5_MASK 0x200000
+#define PB1_PIF_LANE5_OVRD2__RESPONSEMODE_5__SHIFT 0x15
+#define PB1_PIF_LANE5_OVRD2__REQUESTTRK_5_MASK 0x400000
+#define PB1_PIF_LANE5_OVRD2__REQUESTTRK_5__SHIFT 0x16
+#define PB1_PIF_LANE5_OVRD2__REQUESTTRN_5_MASK 0x800000
+#define PB1_PIF_LANE5_OVRD2__REQUESTTRN_5__SHIFT 0x17
+#define PB1_PIF_LANE5_OVRD2__COEFFICIENTID_5_MASK 0x3000000
+#define PB1_PIF_LANE5_OVRD2__COEFFICIENTID_5__SHIFT 0x18
+#define PB1_PIF_LANE5_OVRD2__COEFFICIENT_5_MASK 0xfc000000
+#define PB1_PIF_LANE5_OVRD2__COEFFICIENT_5__SHIFT 0x1a
+#define PB1_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK 0x1
+#define PB1_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT 0x0
+#define PB1_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2
+#define PB1_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT 0x1
+#define PB1_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK 0x4
+#define PB1_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2
+#define PB1_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK 0x8
+#define PB1_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT 0x3
+#define PB1_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK 0x10
+#define PB1_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT 0x4
+#define PB1_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK 0x20
+#define PB1_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT 0x5
+#define PB1_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK 0x40
+#define PB1_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT 0x6
+#define PB1_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK 0x80
+#define PB1_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT 0x7
+#define PB1_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK 0x100
+#define PB1_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT 0x8
+#define PB1_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK 0x200
+#define PB1_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT 0x9
+#define PB1_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK 0x400
+#define PB1_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT 0xa
+#define PB1_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK 0x800
+#define PB1_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT 0xb
+#define PB1_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK 0x1000
+#define PB1_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT 0xc
+#define PB1_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK 0x2000
+#define PB1_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT 0xd
+#define PB1_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK 0x4000
+#define PB1_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT 0xe
+#define PB1_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK 0x8000
+#define PB1_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT 0xf
+#define PB1_PIF_LANE6_OVRD__CDREN_OVRD_EN_6_MASK 0x10000
+#define PB1_PIF_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT 0x10
+#define PB1_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK 0x20000
+#define PB1_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT 0x11
+#define PB1_PIF_LANE6_OVRD2__GANGMODE_6_MASK 0x7
+#define PB1_PIF_LANE6_OVRD2__GANGMODE_6__SHIFT 0x0
+#define PB1_PIF_LANE6_OVRD2__FREQDIV_6_MASK 0x18
+#define PB1_PIF_LANE6_OVRD2__FREQDIV_6__SHIFT 0x3
+#define PB1_PIF_LANE6_OVRD2__LINKSPEED_6_MASK 0x60
+#define PB1_PIF_LANE6_OVRD2__LINKSPEED_6__SHIFT 0x5
+#define PB1_PIF_LANE6_OVRD2__TWOSYMENABLE_6_MASK 0x80
+#define PB1_PIF_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT 0x7
+#define PB1_PIF_LANE6_OVRD2__TXPWR_6_MASK 0x700
+#define PB1_PIF_LANE6_OVRD2__TXPWR_6__SHIFT 0x8
+#define PB1_PIF_LANE6_OVRD2__TXPGENABLE_6_MASK 0x1800
+#define PB1_PIF_LANE6_OVRD2__TXPGENABLE_6__SHIFT 0xb
+#define PB1_PIF_LANE6_OVRD2__RXPWR_6_MASK 0xe000
+#define PB1_PIF_LANE6_OVRD2__RXPWR_6__SHIFT 0xd
+#define PB1_PIF_LANE6_OVRD2__RXPGENABLE_6_MASK 0x30000
+#define PB1_PIF_LANE6_OVRD2__RXPGENABLE_6__SHIFT 0x10
+#define PB1_PIF_LANE6_OVRD2__ELECIDLEDETEN_6_MASK 0x40000
+#define PB1_PIF_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT 0x12
+#define PB1_PIF_LANE6_OVRD2__ENABLEFOM_6_MASK 0x80000
+#define PB1_PIF_LANE6_OVRD2__ENABLEFOM_6__SHIFT 0x13
+#define PB1_PIF_LANE6_OVRD2__REQUESTFOM_6_MASK 0x100000
+#define PB1_PIF_LANE6_OVRD2__REQUESTFOM_6__SHIFT 0x14
+#define PB1_PIF_LANE6_OVRD2__RESPONSEMODE_6_MASK 0x200000
+#define PB1_PIF_LANE6_OVRD2__RESPONSEMODE_6__SHIFT 0x15
+#define PB1_PIF_LANE6_OVRD2__REQUESTTRK_6_MASK 0x400000
+#define PB1_PIF_LANE6_OVRD2__REQUESTTRK_6__SHIFT 0x16
+#define PB1_PIF_LANE6_OVRD2__REQUESTTRN_6_MASK 0x800000
+#define PB1_PIF_LANE6_OVRD2__REQUESTTRN_6__SHIFT 0x17
+#define PB1_PIF_LANE6_OVRD2__COEFFICIENTID_6_MASK 0x3000000
+#define PB1_PIF_LANE6_OVRD2__COEFFICIENTID_6__SHIFT 0x18
+#define PB1_PIF_LANE6_OVRD2__COEFFICIENT_6_MASK 0xfc000000
+#define PB1_PIF_LANE6_OVRD2__COEFFICIENT_6__SHIFT 0x1a
+#define PB1_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK 0x1
+#define PB1_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT 0x0
+#define PB1_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK 0x2
+#define PB1_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT 0x1
+#define PB1_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK 0x4
+#define PB1_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT 0x2
+#define PB1_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK 0x8
+#define PB1_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT 0x3
+#define PB1_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK 0x10
+#define PB1_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT 0x4
+#define PB1_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK 0x20
+#define PB1_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT 0x5
+#define PB1_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK 0x40
+#define PB1_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT 0x6
+#define PB1_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK 0x80
+#define PB1_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT 0x7
+#define PB1_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK 0x100
+#define PB1_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT 0x8
+#define PB1_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK 0x200
+#define PB1_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT 0x9
+#define PB1_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK 0x400
+#define PB1_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT 0xa
+#define PB1_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK 0x800
+#define PB1_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT 0xb
+#define PB1_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK 0x1000
+#define PB1_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT 0xc
+#define PB1_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK 0x2000
+#define PB1_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT 0xd
+#define PB1_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK 0x4000
+#define PB1_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT 0xe
+#define PB1_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK 0x8000
+#define PB1_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT 0xf
+#define PB1_PIF_LANE7_OVRD__CDREN_OVRD_EN_7_MASK 0x10000
+#define PB1_PIF_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT 0x10
+#define PB1_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK 0x20000
+#define PB1_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT 0x11
+#define PB1_PIF_LANE7_OVRD2__GANGMODE_7_MASK 0x7
+#define PB1_PIF_LANE7_OVRD2__GANGMODE_7__SHIFT 0x0
+#define PB1_PIF_LANE7_OVRD2__FREQDIV_7_MASK 0x18
+#define PB1_PIF_LANE7_OVRD2__FREQDIV_7__SHIFT 0x3
+#define PB1_PIF_LANE7_OVRD2__LINKSPEED_7_MASK 0x60
+#define PB1_PIF_LANE7_OVRD2__LINKSPEED_7__SHIFT 0x5
+#define PB1_PIF_LANE7_OVRD2__TWOSYMENABLE_7_MASK 0x80
+#define PB1_PIF_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT 0x7
+#define PB1_PIF_LANE7_OVRD2__TXPWR_7_MASK 0x700
+#define PB1_PIF_LANE7_OVRD2__TXPWR_7__SHIFT 0x8
+#define PB1_PIF_LANE7_OVRD2__TXPGENABLE_7_MASK 0x1800
+#define PB1_PIF_LANE7_OVRD2__TXPGENABLE_7__SHIFT 0xb
+#define PB1_PIF_LANE7_OVRD2__RXPWR_7_MASK 0xe000
+#define PB1_PIF_LANE7_OVRD2__RXPWR_7__SHIFT 0xd
+#define PB1_PIF_LANE7_OVRD2__RXPGENABLE_7_MASK 0x30000
+#define PB1_PIF_LANE7_OVRD2__RXPGENABLE_7__SHIFT 0x10
+#define PB1_PIF_LANE7_OVRD2__ELECIDLEDETEN_7_MASK 0x40000
+#define PB1_PIF_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT 0x12
+#define PB1_PIF_LANE7_OVRD2__ENABLEFOM_7_MASK 0x80000
+#define PB1_PIF_LANE7_OVRD2__ENABLEFOM_7__SHIFT 0x13
+#define PB1_PIF_LANE7_OVRD2__REQUESTFOM_7_MASK 0x100000
+#define PB1_PIF_LANE7_OVRD2__REQUESTFOM_7__SHIFT 0x14
+#define PB1_PIF_LANE7_OVRD2__RESPONSEMODE_7_MASK 0x200000
+#define PB1_PIF_LANE7_OVRD2__RESPONSEMODE_7__SHIFT 0x15
+#define PB1_PIF_LANE7_OVRD2__REQUESTTRK_7_MASK 0x400000
+#define PB1_PIF_LANE7_OVRD2__REQUESTTRK_7__SHIFT 0x16
+#define PB1_PIF_LANE7_OVRD2__REQUESTTRN_7_MASK 0x800000
+#define PB1_PIF_LANE7_OVRD2__REQUESTTRN_7__SHIFT 0x17
+#define PB1_PIF_LANE7_OVRD2__COEFFICIENTID_7_MASK 0x3000000
+#define PB1_PIF_LANE7_OVRD2__COEFFICIENTID_7__SHIFT 0x18
+#define PB1_PIF_LANE7_OVRD2__COEFFICIENT_7_MASK 0xfc000000
+#define PB1_PIF_LANE7_OVRD2__COEFFICIENT_7__SHIFT 0x1a
+#define PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
+#define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
+#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
+#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
+#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
+#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
+#define PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
+#define PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
+#define PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
+#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
+#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
+#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
+#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
+#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
+#define PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
+#define PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
+#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
+#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
+#define PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
+#define PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
+#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
+#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x1000000
+#define PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x2000000
+#define PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x4000000
+#define PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
+#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
+#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
+#define PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
+#define PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
+#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
+#define PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
+#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
+#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
+#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
+#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
+#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
+#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
+#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
+#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
+#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
+#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
+#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
+#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
+#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
+#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
+#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
+#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define PCIE_FC_P__PD_CREDITS_MASK 0xff
+#define PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define PCIE_FC_P__PH_CREDITS_MASK 0xff00
+#define PCIE_FC_P__PH_CREDITS__SHIFT 0x8
+#define PCIE_FC_NP__NPD_CREDITS_MASK 0xff
+#define PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
+#define PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
+#define PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
+#define PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
+#define PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
+#define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
+#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
+#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
+#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
+#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
+#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
+#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
+#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
+#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x1000
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0xc
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x2000
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0xd
+#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
+#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
+#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
+#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
+#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
+#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
+#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
+#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
+#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
+#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
+#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
+#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
+#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
+#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
+#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
+#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
+#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
+#define PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
+#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
+#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
+#define PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
+#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
+#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
+#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
+#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
+#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
+#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
+#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
+#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
+#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
+#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
+#define PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
+#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
+#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
+#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
+#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
+#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
+#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
+#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
+#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
+#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
+#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
+#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
+#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define PCIEP_SRIOV_PRIV_CTRL__RX_SRIOV_VF_MAPPING_MODE_MASK 0x3
+#define PCIEP_SRIOV_PRIV_CTRL__RX_SRIOV_VF_MAPPING_MODE__SHIFT 0x0
+#define PCIEP_SRIOV_PRIV_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK 0xc
+#define PCIEP_SRIOV_PRIV_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x2
+#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
+#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
+#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
+#define PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
+#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
+#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
+#define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
+#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
+#define PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
+#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
+#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
+#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
+#define PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
+#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
+#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
+#define PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
+#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
+#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
+#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
+#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
+#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
+#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
+#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
+#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
+#define PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
+#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
+#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
+#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
+#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
+#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
+#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
+#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
+#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
+#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
+#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
+#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
+#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
+#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
+#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
+#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
+#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
+#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
+#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
+#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
+#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
+#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
+#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
+#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
+#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
+#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
+#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
+#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
+#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
+#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
+#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
+#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
+#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
+#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
+#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
+#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
+#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
+#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
+#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
+#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
+#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
+#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
+#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
+#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
+#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
+#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
+#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
+#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
+#define PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
+#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
+#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
+#define PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
+#define PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
+#define PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
+#define PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
+#define PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
+#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
+#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
+#define PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
+#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
+#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
+#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
+#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
+#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
+#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
+#define PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
+#define PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
+#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
+#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
+#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
+#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
+#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
+#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
+#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
+#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
+#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
+#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
+#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
+#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
+#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
+#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
+#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
+#define PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
+#define PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
+#define PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
+#define PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
+#define PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
+#define PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
+#define PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
+#define PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
+#define PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
+#define PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
+#define PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
+#define PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
+#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
+#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
+#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
+#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
+#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
+#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
+#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
+#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
+#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
+#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
+#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
+#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
+#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
+#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
+#define PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
+#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
+#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
+#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
+#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
+#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
+#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
+#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
+#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
+#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
+#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
+#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
+#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
+#define PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
+#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
+#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
+#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
+#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
+#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
+#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
+#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
+#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
+#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
+#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
+#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
+#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
+#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
+#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
+#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
+#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
+#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
+#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
+#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
+#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
+#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
+#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
+#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
+#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
+#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
+#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
+#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
+#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
+#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
+#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
+#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
+#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
+#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
+#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
+#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
+#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
+#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
+#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
+#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
+#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
+#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
+#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
+#define PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
+#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
+#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
+#define PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
+#define PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
+#define PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
+#define PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
+#define PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
+#define PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
+#define PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
+#define PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
+#define PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
+#define PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
+#define PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
+#define PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
+#define PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
+#define PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
+#define PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
+#define PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
+#define PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
+#define PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
+#define PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
+#define PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
+#define PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
+#define PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
+#define PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
+#define PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
+#define PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
+#define PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
+#define PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
+#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
+#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
+#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
+#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
+#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
+#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
+#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
+#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
+#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
+#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
+#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
+#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
+#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
+#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
+#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
+#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
+#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
+#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
+#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
+#define PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
+#define PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
+#define PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
+#define PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
+#define PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
+#define PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
+#define PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
+#define PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
+#define PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
+#define PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
+#define PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
+#define PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
+#define PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffc
+#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffff
+#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xffffffff
+#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x1
+#define PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffc
+#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffff
+#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xffffffff
+#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x1
+#define PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffc
+#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffff
+#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xffffffff
+#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x1
+#define PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xfffffffc
+#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xffffffff
+#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xffffffff
+#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x1
+#define PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK 0xf
+#define PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0
+#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER_MASK 0x1
+#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER__SHIFT 0x0
+#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER_MASK 0x2
+#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER__SHIFT 0x1
+#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn_MASK 0x1
+#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn__SHIFT 0x0
+#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstImpEn_MASK 0x2
+#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstImpEn__SHIFT 0x1
+#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer_MASK 0xffff
+#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer__SHIFT 0x0
+#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn_MASK 0x40000000
+#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn__SHIFT 0x1e
+#define BIF_RFE_SOFTRST_CNTL__SoftRstReg_MASK 0x80000000
+#define BIF_RFE_SOFTRST_CNTL__SoftRstReg__SHIFT 0x1f
+#define BIF_RFE_IMPRST_CNTL__REG_RST_impEn_MASK 0x1
+#define BIF_RFE_IMPRST_CNTL__REG_RST_impEn__SHIFT 0x0
+#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWDBIF_rst_MASK 0x1
+#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWDBIF_rst__SHIFT 0x0
+#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWDBIF_rst_MASK 0x2
+#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWDBIF_rst__SHIFT 0x1
+#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BU_rst_MASK 0x1
+#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BU_rst__SHIFT 0x0
+#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWDBIF_rst_MASK 0x2
+#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWDBIF_rst__SHIFT 0x1
+#define BIF_RFE_MASTER_SOFTRST_TRIGGER__SMBUS_rst_MASK 0x4
+#define BIF_RFE_MASTER_SOFTRST_TRIGGER__SMBUS_rst__SHIFT 0x2
+#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst_MASK 0x8
+#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst__SHIFT 0x3
+#define BIF_PWDN_COMMAND__REG_BU_pw_cmd_MASK 0x1
+#define BIF_PWDN_COMMAND__REG_BU_pw_cmd__SHIFT 0x0
+#define BIF_PWDN_COMMAND__REG_RWREG_RFEWDBIF_pw_cmd_MASK 0x2
+#define BIF_PWDN_COMMAND__REG_RWREG_RFEWDBIF_pw_cmd__SHIFT 0x1
+#define BIF_PWDN_COMMAND__REG_SMBUS_pw_cmd_MASK 0x4
+#define BIF_PWDN_COMMAND__REG_SMBUS_pw_cmd__SHIFT 0x2
+#define BIF_PWDN_COMMAND__REG_BX_pw_cmd_MASK 0x8
+#define BIF_PWDN_COMMAND__REG_BX_pw_cmd__SHIFT 0x3
+#define BIF_PWDN_STATUS__BU_REG_pw_status_MASK 0x1
+#define BIF_PWDN_STATUS__BU_REG_pw_status__SHIFT 0x0
+#define BIF_PWDN_STATUS__RWREG_RFEWDBIF_REG_pw_status_MASK 0x2
+#define BIF_PWDN_STATUS__RWREG_RFEWDBIF_REG_pw_status__SHIFT 0x1
+#define BIF_PWDN_STATUS__SMBUS_REG_pw_status_MASK 0x4
+#define BIF_PWDN_STATUS__SMBUS_REG_pw_status__SHIFT 0x2
+#define BIF_PWDN_STATUS__BX_REG_pw_status_MASK 0x8
+#define BIF_PWDN_STATUS__BX_REG_pw_status__SHIFT 0x3
+#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkGate_timer_MASK 0xff
+#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkGate_timer__SHIFT 0x0
+#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkSetup_timer_MASK 0xf00
+#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_clkSetup_timer__SHIFT 0x8
+#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_timeout_timer_MASK 0xff0000
+#define BIF_RFE_MST_BU_CMDSTATUS__REG_BU_timeout_timer__SHIFT 0x10
+#define BIF_RFE_MST_BU_CMDSTATUS__BU_RFE_mstTimeout_MASK 0x1000000
+#define BIF_RFE_MST_BU_CMDSTATUS__BU_RFE_mstTimeout__SHIFT 0x18
+#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkGate_timer_MASK 0xff
+#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkGate_timer__SHIFT 0x0
+#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkSetup_timer_MASK 0xf00
+#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_clkSetup_timer__SHIFT 0x8
+#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_timeout_timer_MASK 0xff0000
+#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__REG_RWREG_RFEWDBIF_timeout_timer__SHIFT 0x10
+#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__RWREG_RFEWDBIF_RFE_mstTimeout_MASK 0x1000000
+#define BIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS__RWREG_RFEWDBIF_RFE_mstTimeout__SHIFT 0x18
+#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkGate_timer_MASK 0xff
+#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkGate_timer__SHIFT 0x0
+#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkSetup_timer_MASK 0xf00
+#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_clkSetup_timer__SHIFT 0x8
+#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_timeout_timer_MASK 0xff0000
+#define BIF_RFE_MST_SMBUS_CMDSTATUS__REG_SMBUS_timeout_timer__SHIFT 0x10
+#define BIF_RFE_MST_SMBUS_CMDSTATUS__SMBUS_RFE_mstTimeout_MASK 0x1000000
+#define BIF_RFE_MST_SMBUS_CMDSTATUS__SMBUS_RFE_mstTimeout__SHIFT 0x18
+#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer_MASK 0xff
+#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer__SHIFT 0x0
+#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer_MASK 0xf00
+#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer__SHIFT 0x8
+#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer_MASK 0xff0000
+#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer__SHIFT 0x10
+#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout_MASK 0x1000000
+#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout__SHIFT 0x18
+#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus_MASK 0x1
+#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus__SHIFT 0x0
+#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN_MASK 0x1
+#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN__SHIFT 0x0
+#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL_MASK 0xe
+#define BIF_RFE_MMCFG_CNTL__CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL__SHIFT 0x1
+#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN_MASK 0x10
+#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN__SHIFT 0x4
+#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL_MASK 0xe0
+#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL__SHIFT 0x5
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_MASK 0x1e
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL__SHIFT 0x1
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_EN_MASK 0x20
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_RX_IMPVAL_EN__SHIFT 0x5
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PD_MASK 0x3c0
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PD__SHIFT 0x6
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PD_MASK 0x400
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PD__SHIFT 0xa
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PU_MASK 0x7800
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_PU__SHIFT 0xb
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PU_MASK 0x8000
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_TX_IMPVAL_EN_PU__SHIFT 0xf
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_DBG_ANALOG_EN_MASK 0x10000
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_DBG_ANALOG_EN__SHIFT 0x10
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_IGNORE_QUICKSIM_MASK 0x20000
+#define BIF_CC_RFE_IMP_OVERRIDECNTL__STRAP_PLL_IMP_IGNORE_QUICKSIM__SHIFT 0x11
+#define BIF_IMPCTL_SMPLCNTL__FORCE_DONE_MASK 0x1
+#define BIF_IMPCTL_SMPLCNTL__FORCE_DONE__SHIFT 0x0
+#define BIF_IMPCTL_SMPLCNTL__RxPDNB_MASK 0x2
+#define BIF_IMPCTL_SMPLCNTL__RxPDNB__SHIFT 0x1
+#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pd_MASK 0x4
+#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pd__SHIFT 0x2
+#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pu_MASK 0x8
+#define BIF_IMPCTL_SMPLCNTL__TxPDNB_pu__SHIFT 0x3
+#define BIF_IMPCTL_SMPLCNTL__SAMPLE_PERIOD_MASK 0x1f00
+#define BIF_IMPCTL_SMPLCNTL__SAMPLE_PERIOD__SHIFT 0x8
+#define BIF_IMPCTL_SMPLCNTL__EXTEND_SAMPLES_MASK 0x2000
+#define BIF_IMPCTL_SMPLCNTL__EXTEND_SAMPLES__SHIFT 0xd
+#define BIF_IMPCTL_SMPLCNTL__FORCE_ENABLE_MASK 0x4000
+#define BIF_IMPCTL_SMPLCNTL__FORCE_ENABLE__SHIFT 0xe
+#define BIF_IMPCTL_SMPLCNTL__SETUP_TIME_MASK 0xf8000
+#define BIF_IMPCTL_SMPLCNTL__SETUP_TIME__SHIFT 0xf
+#define BIF_IMPCTL_SMPLCNTL__LOWER_SAMPLE_THRESH_MASK 0x3f00000
+#define BIF_IMPCTL_SMPLCNTL__LOWER_SAMPLE_THRESH__SHIFT 0x14
+#define BIF_IMPCTL_SMPLCNTL__UPPER_SAMPLE_THRESH_MASK 0xfc000000
+#define BIF_IMPCTL_SMPLCNTL__UPPER_SAMPLE_THRESH__SHIFT 0x1a
+#define BIF_IMPCTL_RXCNTL__RX_ADJUST_MASK 0x7
+#define BIF_IMPCTL_RXCNTL__RX_ADJUST__SHIFT 0x0
+#define BIF_IMPCTL_RXCNTL__RX_BIAS_HIGH_MASK 0x8
+#define BIF_IMPCTL_RXCNTL__RX_BIAS_HIGH__SHIFT 0x3
+#define BIF_IMPCTL_RXCNTL__CONT_AFTER_RX_DECT_MASK 0x10
+#define BIF_IMPCTL_RXCNTL__CONT_AFTER_RX_DECT__SHIFT 0x4
+#define BIF_IMPCTL_RXCNTL__SUSPEND_MASK 0x40
+#define BIF_IMPCTL_RXCNTL__SUSPEND__SHIFT 0x6
+#define BIF_IMPCTL_RXCNTL__FORCE_RST_MASK 0x80
+#define BIF_IMPCTL_RXCNTL__FORCE_RST__SHIFT 0x7
+#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_THRESH_MASK 0xf00
+#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_THRESH__SHIFT 0x8
+#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ_MASK 0x1000
+#define BIF_IMPCTL_RXCNTL__LOWER_RX_ADJ__SHIFT 0xc
+#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_THRESH_MASK 0x1e000
+#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_THRESH__SHIFT 0xd
+#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ_MASK 0x20000
+#define BIF_IMPCTL_RXCNTL__UPPER_RX_ADJ__SHIFT 0x11
+#define BIF_IMPCTL_RXCNTL__RX_IMP_LOCKED_MASK 0x40000
+#define BIF_IMPCTL_RXCNTL__RX_IMP_LOCKED__SHIFT 0x12
+#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_SEL_MASK 0x80000
+#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_SEL__SHIFT 0x13
+#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK_MASK 0xf00000
+#define BIF_IMPCTL_RXCNTL__RX_IMP_READBACK__SHIFT 0x14
+#define BIF_IMPCTL_RXCNTL__RX_CMP_AMBIG_MASK 0x10000000
+#define BIF_IMPCTL_RXCNTL__RX_CMP_AMBIG__SHIFT 0x1c
+#define BIF_IMPCTL_RXCNTL__CAL_DONE_MASK 0x20000000
+#define BIF_IMPCTL_RXCNTL__CAL_DONE__SHIFT 0x1d
+#define BIF_IMPCTL_TXCNTL_pd__TX_ADJUST_pd_MASK 0x7
+#define BIF_IMPCTL_TXCNTL_pd__TX_ADJUST_pd__SHIFT 0x0
+#define BIF_IMPCTL_TXCNTL_pd__TX_BIAS_HIGH_pd_MASK 0x8
+#define BIF_IMPCTL_TXCNTL_pd__TX_BIAS_HIGH_pd__SHIFT 0x3
+#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_THRESH_pd_MASK 0xf00
+#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_THRESH_pd__SHIFT 0x8
+#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_pd_MASK 0x1000
+#define BIF_IMPCTL_TXCNTL_pd__LOWER_TX_ADJ_pd__SHIFT 0xc
+#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_THRESH_pd_MASK 0x1e000
+#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_THRESH_pd__SHIFT 0xd
+#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_pd_MASK 0x20000
+#define BIF_IMPCTL_TXCNTL_pd__UPPER_TX_ADJ_pd__SHIFT 0x11
+#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_LOCKED_pd_MASK 0x40000
+#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_LOCKED_pd__SHIFT 0x12
+#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_SEL_pd_MASK 0x80000
+#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_SEL_pd__SHIFT 0x13
+#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_pd_MASK 0xf00000
+#define BIF_IMPCTL_TXCNTL_pd__TX_IMP_READBACK_pd__SHIFT 0x14
+#define BIF_IMPCTL_TXCNTL_pd__TX_CMP_AMBIG_pd_MASK 0x10000000
+#define BIF_IMPCTL_TXCNTL_pd__TX_CMP_AMBIG_pd__SHIFT 0x1c
+#define BIF_IMPCTL_TXCNTL_pu__TX_ADJUST_pu_MASK 0x7
+#define BIF_IMPCTL_TXCNTL_pu__TX_ADJUST_pu__SHIFT 0x0
+#define BIF_IMPCTL_TXCNTL_pu__TX_BIAS_HIGH_pu_MASK 0x8
+#define BIF_IMPCTL_TXCNTL_pu__TX_BIAS_HIGH_pu__SHIFT 0x3
+#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_THRESH_pu_MASK 0xf00
+#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_THRESH_pu__SHIFT 0x8
+#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_pu_MASK 0x1000
+#define BIF_IMPCTL_TXCNTL_pu__LOWER_TX_ADJ_pu__SHIFT 0xc
+#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_THRESH_pu_MASK 0x1e000
+#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_THRESH_pu__SHIFT 0xd
+#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_pu_MASK 0x20000
+#define BIF_IMPCTL_TXCNTL_pu__UPPER_TX_ADJ_pu__SHIFT 0x11
+#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_LOCKED_pu_MASK 0x40000
+#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_LOCKED_pu__SHIFT 0x12
+#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_SEL_pu_MASK 0x80000
+#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_SEL_pu__SHIFT 0x13
+#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_pu_MASK 0xf00000
+#define BIF_IMPCTL_TXCNTL_pu__TX_IMP_READBACK_pu__SHIFT 0x14
+#define BIF_IMPCTL_TXCNTL_pu__TX_CMP_AMBIG_pu_MASK 0x10000000
+#define BIF_IMPCTL_TXCNTL_pu__TX_CMP_AMBIG_pu__SHIFT 0x1c
+#define BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__UPDATE_PERIOD_MASK 0xffffffff
+#define BIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD__UPDATE_PERIOD__SHIFT 0x0
+
+#endif /* BIF_5_0_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_d.h
new file mode 100644
index 000000000000..b52c9aaa5581
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_d.h
@@ -0,0 +1,3577 @@
+/*
+ * BIF_5_1 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef BIF_5_1_D_H
+#define BIF_5_1_D_H
+
+#define mmMM_INDEX 0x0
+#define mmMM_INDEX_HI 0x6
+#define mmMM_DATA 0x1
+#define mmBIF_MM_INDACCESS_CNTL 0x1500
+#define mmBUS_CNTL 0x1508
+#define mmCONFIG_CNTL 0x1509
+#define mmCONFIG_MEMSIZE 0x150a
+#define mmCONFIG_F0_BASE 0x150b
+#define mmCONFIG_APER_SIZE 0x150c
+#define mmCONFIG_REG_APER_SIZE 0x150d
+#define mmBIF_SCRATCH0 0x150e
+#define mmBIF_SCRATCH1 0x150f
+#define mmBX_RESET_EN 0x1514
+#define mmMM_CFGREGS_CNTL 0x1513
+#define mmHW_DEBUG 0x1515
+#define mmMASTER_CREDIT_CNTL 0x1516
+#define mmSLAVE_REQ_CREDIT_CNTL 0x1517
+#define mmBX_RESET_CNTL 0x1518
+#define mmINTERRUPT_CNTL 0x151a
+#define mmINTERRUPT_CNTL2 0x151b
+#define mmBIF_DEBUG_CNTL 0x151c
+#define mmBIF_DEBUG_MUX 0x151d
+#define mmBIF_DEBUG_OUT 0x151e
+#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528
+#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520
+#define mmCLKREQB_PAD_CNTL 0x1521
+#define mmSMBDAT_PAD_CNTL 0x1522
+#define mmSMBCLK_PAD_CNTL 0x1523
+#define mmBIF_XDMA_LO 0x14c0
+#define mmBIF_XDMA_HI 0x14c1
+#define mmBIF_FEATURES_CONTROL_MISC 0x14c2
+#define mmBIF_DOORBELL_CNTL 0x14c3
+#define mmBIF_SLVARB_MODE 0x14c4
+#define mmBIF_FB_EN 0x1524
+#define mmBIF_BUSNUM_CNTL1 0x1525
+#define mmBIF_BUSNUM_LIST0 0x1526
+#define mmBIF_BUSNUM_LIST1 0x1527
+#define mmBIF_BUSNUM_CNTL2 0x152b
+#define mmBIF_BUSY_DELAY_CNTR 0x1529
+#define mmBIF_PERFMON_CNTL 0x152c
+#define mmBIF_PERFCOUNTER0_RESULT 0x152d
+#define mmBIF_PERFCOUNTER1_RESULT 0x152e
+#define mmSLAVE_HANG_PROTECTION_CNTL 0x1536
+#define mmGPU_HDP_FLUSH_REQ 0x1537
+#define mmGPU_HDP_FLUSH_DONE 0x1538
+#define mmSLAVE_HANG_ERROR 0x153b
+#define mmCAPTURE_HOST_BUSNUM 0x153c
+#define mmHOST_BUSNUM 0x153d
+#define mmPEER_REG_RANGE0 0x153e
+#define mmPEER_REG_RANGE1 0x153f
+#define mmPEER0_FB_OFFSET_HI 0x14f3
+#define mmPEER0_FB_OFFSET_LO 0x14f2
+#define mmPEER1_FB_OFFSET_HI 0x14f1
+#define mmPEER1_FB_OFFSET_LO 0x14f0
+#define mmPEER2_FB_OFFSET_HI 0x14ef
+#define mmPEER2_FB_OFFSET_LO 0x14ee
+#define mmPEER3_FB_OFFSET_HI 0x14ed
+#define mmPEER3_FB_OFFSET_LO 0x14ec
+#define mmDBG_BYPASS_SRBM_ACCESS 0x14eb
+#define mmSMBUS_BACO_DUMMY 0x14c6
+#define mmBIF_DEVFUNCNUM_LIST0 0x14e8
+#define mmBIF_DEVFUNCNUM_LIST1 0x14e7
+#define mmBACO_CNTL 0x14e5
+#define mmBF_ANA_ISO_CNTL 0x14c7
+#define mmMEM_TYPE_CNTL 0x14e4
+#define mmBIF_BACO_DEBUG 0x14df
+#define mmBIF_BACO_DEBUG_LATCH 0x14dc
+#define mmBACO_CNTL_MISC 0x14db
+#define mmSMU_BIF_VDDGFX_PWR_STATUS 0x14f8
+#define mmBIF_VDDGFX_GFX0_LOWER 0x1428
+#define mmBIF_VDDGFX_GFX0_UPPER 0x1429
+#define mmBIF_VDDGFX_GFX1_LOWER 0x142a
+#define mmBIF_VDDGFX_GFX1_UPPER 0x142b
+#define mmBIF_VDDGFX_GFX2_LOWER 0x142c
+#define mmBIF_VDDGFX_GFX2_UPPER 0x142d
+#define mmBIF_VDDGFX_GFX3_LOWER 0x142e
+#define mmBIF_VDDGFX_GFX3_UPPER 0x142f
+#define mmBIF_VDDGFX_GFX4_LOWER 0x1430
+#define mmBIF_VDDGFX_GFX4_UPPER 0x1431
+#define mmBIF_VDDGFX_GFX5_LOWER 0x1432
+#define mmBIF_VDDGFX_GFX5_UPPER 0x1433
+#define mmBIF_VDDGFX_RSV1_LOWER 0x1434
+#define mmBIF_VDDGFX_RSV1_UPPER 0x1435
+#define mmBIF_VDDGFX_RSV2_LOWER 0x1436
+#define mmBIF_VDDGFX_RSV2_UPPER 0x1437
+#define mmBIF_VDDGFX_RSV3_LOWER 0x1438
+#define mmBIF_VDDGFX_RSV3_UPPER 0x1439
+#define mmBIF_VDDGFX_RSV4_LOWER 0x143a
+#define mmBIF_VDDGFX_RSV4_UPPER 0x143b
+#define mmBIF_VDDGFX_FB_CMP 0x143c
+#define mmBIF_DOORBELL_GBLAPER1_LOWER 0x14fc
+#define mmBIF_DOORBELL_GBLAPER1_UPPER 0x14fd
+#define mmBIF_DOORBELL_GBLAPER2_LOWER 0x14fe
+#define mmBIF_DOORBELL_GBLAPER2_UPPER 0x14ff
+#define mmBIF_SMU_INDEX 0x143d
+#define mmBIF_SMU_DATA 0x143e
+#define mmIMPCTL_RESET 0x14f5
+#define mmGARLIC_FLUSH_CNTL 0x1401
+#define mmGARLIC_FLUSH_ADDR_START_0 0x1402
+#define mmGARLIC_FLUSH_ADDR_START_1 0x1404
+#define mmGARLIC_FLUSH_ADDR_START_2 0x1406
+#define mmGARLIC_FLUSH_ADDR_START_3 0x1408
+#define mmGARLIC_FLUSH_ADDR_START_4 0x140a
+#define mmGARLIC_FLUSH_ADDR_START_5 0x140c
+#define mmGARLIC_FLUSH_ADDR_START_6 0x140e
+#define mmGARLIC_FLUSH_ADDR_START_7 0x1410
+#define mmGARLIC_FLUSH_ADDR_END_0 0x1403
+#define mmGARLIC_FLUSH_ADDR_END_1 0x1405
+#define mmGARLIC_FLUSH_ADDR_END_2 0x1407
+#define mmGARLIC_FLUSH_ADDR_END_3 0x1409
+#define mmGARLIC_FLUSH_ADDR_END_4 0x140b
+#define mmGARLIC_FLUSH_ADDR_END_5 0x140d
+#define mmGARLIC_FLUSH_ADDR_END_6 0x140f
+#define mmGARLIC_FLUSH_ADDR_END_7 0x1411
+#define mmGARLIC_FLUSH_REQ 0x1412
+#define mmGPU_GARLIC_FLUSH_REQ 0x1413
+#define mmGPU_GARLIC_FLUSH_DONE 0x1414
+#define mmGARLIC_COHE_CP_RB0_WPTR 0x1415
+#define mmGARLIC_COHE_CP_RB1_WPTR 0x1416
+#define mmGARLIC_COHE_CP_RB2_WPTR 0x1417
+#define mmGARLIC_COHE_UVD_RBC_RB_WPTR 0x1418
+#define mmGARLIC_COHE_SDMA0_GFX_RB_WPTR 0x1419
+#define mmGARLIC_COHE_SDMA1_GFX_RB_WPTR 0x141a
+#define mmGARLIC_COHE_CP_DMA_ME_COMMAND 0x141b
+#define mmGARLIC_COHE_CP_DMA_PFP_COMMAND 0x141c
+#define mmGARLIC_COHE_SAM_SAB_RBI_WPTR 0x141d
+#define mmGARLIC_COHE_SAM_SAB_RBO_WPTR 0x141e
+#define mmGARLIC_COHE_VCE_OUT_RB_WPTR 0x141f
+#define mmGARLIC_COHE_VCE_RB_WPTR2 0x1420
+#define mmGARLIC_COHE_VCE_RB_WPTR 0x1421
+#define mmGARLIC_COHE_SDMA2_GFX_RB_WPTR 0x1422
+#define mmGARLIC_COHE_SDMA3_GFX_RB_WPTR 0x1423
+#define mmGARLIC_COHE_CP_DMA_PIO_COMMAND 0x1424
+#define mmGARLIC_COHE_GARLIC_FLUSH_REQ 0x1425
+#define mmREMAP_HDP_MEM_FLUSH_CNTL 0x1426
+#define mmREMAP_HDP_REG_FLUSH_CNTL 0x1427
+#define mmBIOS_SCRATCH_0 0x5c9
+#define mmBIOS_SCRATCH_1 0x5ca
+#define mmBIOS_SCRATCH_2 0x5cb
+#define mmBIOS_SCRATCH_3 0x5cc
+#define mmBIOS_SCRATCH_4 0x5cd
+#define mmBIOS_SCRATCH_5 0x5ce
+#define mmBIOS_SCRATCH_6 0x5cf
+#define mmBIOS_SCRATCH_7 0x5d0
+#define mmBIOS_SCRATCH_8 0x5d1
+#define mmBIOS_SCRATCH_9 0x5d2
+#define mmBIOS_SCRATCH_10 0x5d3
+#define mmBIOS_SCRATCH_11 0x5d4
+#define mmBIOS_SCRATCH_12 0x5d5
+#define mmBIOS_SCRATCH_13 0x5d6
+#define mmBIOS_SCRATCH_14 0x5d7
+#define mmBIOS_SCRATCH_15 0x5d8
+#define mmBIF_RB_CNTL 0x1530
+#define mmBIF_RB_BASE 0x1531
+#define mmBIF_RB_RPTR 0x1532
+#define mmBIF_RB_WPTR 0x1533
+#define mmBIF_RB_WPTR_ADDR_HI 0x1534
+#define mmBIF_RB_WPTR_ADDR_LO 0x1535
+#define mmVENDOR_ID 0x0
+#define mmDEVICE_ID 0x0
+#define mmCOMMAND 0x1
+#define mmSTATUS 0x1
+#define mmREVISION_ID 0x2
+#define mmPROG_INTERFACE 0x2
+#define mmSUB_CLASS 0x2
+#define mmBASE_CLASS 0x2
+#define mmCACHE_LINE 0x3
+#define mmLATENCY 0x3
+#define mmHEADER 0x3
+#define mmBIST 0x3
+#define mmBASE_ADDR_1 0x4
+#define mmBASE_ADDR_2 0x5
+#define mmBASE_ADDR_3 0x6
+#define mmBASE_ADDR_4 0x7
+#define mmBASE_ADDR_5 0x8
+#define mmBASE_ADDR_6 0x9
+#define mmROM_BASE_ADDR 0xc
+#define mmCAP_PTR 0xd
+#define mmINTERRUPT_LINE 0xf
+#define mmINTERRUPT_PIN 0xf
+#define mmADAPTER_ID 0xb
+#define mmMIN_GRANT 0xf
+#define mmMAX_LATENCY 0xf
+#define mmVENDOR_CAP_LIST 0x12
+#define mmADAPTER_ID_W 0x13
+#define mmPMI_CAP_LIST 0x14
+#define mmPMI_CAP 0x14
+#define mmPMI_STATUS_CNTL 0x15
+#define mmPCIE_CAP_LIST 0x16
+#define mmPCIE_CAP 0x16
+#define mmDEVICE_CAP 0x17
+#define mmDEVICE_CNTL 0x18
+#define mmDEVICE_STATUS 0x18
+#define mmLINK_CAP 0x19
+#define mmLINK_CNTL 0x1a
+#define mmLINK_STATUS 0x1a
+#define mmDEVICE_CAP2 0x1f
+#define mmDEVICE_CNTL2 0x20
+#define mmDEVICE_STATUS2 0x20
+#define mmLINK_CAP2 0x21
+#define mmLINK_CNTL2 0x22
+#define mmLINK_STATUS2 0x22
+#define mmMSI_CAP_LIST 0x28
+#define mmMSI_MSG_CNTL 0x28
+#define mmMSI_MSG_ADDR_LO 0x29
+#define mmMSI_MSG_ADDR_HI 0x2a
+#define mmMSI_MSG_DATA_64 0x2b
+#define mmMSI_MSG_DATA 0x2a
+#define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x40
+#define mmPCIE_VENDOR_SPECIFIC_HDR 0x41
+#define mmPCIE_VENDOR_SPECIFIC1 0x42
+#define mmPCIE_VENDOR_SPECIFIC2 0x43
+#define mmPCIE_VC_ENH_CAP_LIST 0x44
+#define mmPCIE_PORT_VC_CAP_REG1 0x45
+#define mmPCIE_PORT_VC_CAP_REG2 0x46
+#define mmPCIE_PORT_VC_CNTL 0x47
+#define mmPCIE_PORT_VC_STATUS 0x47
+#define mmPCIE_VC0_RESOURCE_CAP 0x48
+#define mmPCIE_VC0_RESOURCE_CNTL 0x49
+#define mmPCIE_VC0_RESOURCE_STATUS 0x4a
+#define mmPCIE_VC1_RESOURCE_CAP 0x4b
+#define mmPCIE_VC1_RESOURCE_CNTL 0x4c
+#define mmPCIE_VC1_RESOURCE_STATUS 0x4d
+#define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x50
+#define mmPCIE_DEV_SERIAL_NUM_DW1 0x51
+#define mmPCIE_DEV_SERIAL_NUM_DW2 0x52
+#define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x54
+#define mmPCIE_UNCORR_ERR_STATUS 0x55
+#define mmPCIE_UNCORR_ERR_MASK 0x56
+#define mmPCIE_UNCORR_ERR_SEVERITY 0x57
+#define mmPCIE_CORR_ERR_STATUS 0x58
+#define mmPCIE_CORR_ERR_MASK 0x59
+#define mmPCIE_ADV_ERR_CAP_CNTL 0x5a
+#define mmPCIE_HDR_LOG0 0x5b
+#define mmPCIE_HDR_LOG1 0x5c
+#define mmPCIE_HDR_LOG2 0x5d
+#define mmPCIE_HDR_LOG3 0x5e
+#define mmPCIE_TLP_PREFIX_LOG0 0x62
+#define mmPCIE_TLP_PREFIX_LOG1 0x63
+#define mmPCIE_TLP_PREFIX_LOG2 0x64
+#define mmPCIE_TLP_PREFIX_LOG3 0x65
+#define mmPCIE_BAR_ENH_CAP_LIST 0x80
+#define mmPCIE_BAR1_CAP 0x81
+#define mmPCIE_BAR1_CNTL 0x82
+#define mmPCIE_BAR2_CAP 0x83
+#define mmPCIE_BAR2_CNTL 0x84
+#define mmPCIE_BAR3_CAP 0x85
+#define mmPCIE_BAR3_CNTL 0x86
+#define mmPCIE_BAR4_CAP 0x87
+#define mmPCIE_BAR4_CNTL 0x88
+#define mmPCIE_BAR5_CAP 0x89
+#define mmPCIE_BAR5_CNTL 0x8a
+#define mmPCIE_BAR6_CAP 0x8b
+#define mmPCIE_BAR6_CNTL 0x8c
+#define mmPCIE_PWR_BUDGET_ENH_CAP_LIST 0x90
+#define mmPCIE_PWR_BUDGET_DATA_SELECT 0x91
+#define mmPCIE_PWR_BUDGET_DATA 0x92
+#define mmPCIE_PWR_BUDGET_CAP 0x93
+#define mmPCIE_DPA_ENH_CAP_LIST 0x94
+#define mmPCIE_DPA_CAP 0x95
+#define mmPCIE_DPA_LATENCY_INDICATOR 0x96
+#define mmPCIE_DPA_STATUS 0x97
+#define mmPCIE_DPA_CNTL 0x97
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x98
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x98
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x98
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x98
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x99
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x99
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x99
+#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x99
+#define mmPCIE_SECONDARY_ENH_CAP_LIST 0x9c
+#define mmPCIE_LINK_CNTL3 0x9d
+#define mmPCIE_LANE_ERROR_STATUS 0x9e
+#define mmPCIE_LANE_0_EQUALIZATION_CNTL 0x9f
+#define mmPCIE_LANE_1_EQUALIZATION_CNTL 0x9f
+#define mmPCIE_LANE_2_EQUALIZATION_CNTL 0xa0
+#define mmPCIE_LANE_3_EQUALIZATION_CNTL 0xa0
+#define mmPCIE_LANE_4_EQUALIZATION_CNTL 0xa1
+#define mmPCIE_LANE_5_EQUALIZATION_CNTL 0xa1
+#define mmPCIE_LANE_6_EQUALIZATION_CNTL 0xa2
+#define mmPCIE_LANE_7_EQUALIZATION_CNTL 0xa2
+#define mmPCIE_LANE_8_EQUALIZATION_CNTL 0xa3
+#define mmPCIE_LANE_9_EQUALIZATION_CNTL 0xa3
+#define mmPCIE_LANE_10_EQUALIZATION_CNTL 0xa4
+#define mmPCIE_LANE_11_EQUALIZATION_CNTL 0xa4
+#define mmPCIE_LANE_12_EQUALIZATION_CNTL 0xa5
+#define mmPCIE_LANE_13_EQUALIZATION_CNTL 0xa5
+#define mmPCIE_LANE_14_EQUALIZATION_CNTL 0xa6
+#define mmPCIE_LANE_15_EQUALIZATION_CNTL 0xa6
+#define mmPCIE_ACS_ENH_CAP_LIST 0xa8
+#define mmPCIE_ACS_CAP 0xa9
+#define mmPCIE_ACS_CNTL 0xa9
+#define mmPCIE_ATS_ENH_CAP_LIST 0xac
+#define mmPCIE_ATS_CAP 0xad
+#define mmPCIE_ATS_CNTL 0xad
+#define mmPCIE_PAGE_REQ_ENH_CAP_LIST 0xb0
+#define mmPCIE_PAGE_REQ_CNTL 0xb1
+#define mmPCIE_PAGE_REQ_STATUS 0xb1
+#define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xb2
+#define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC 0xb3
+#define mmPCIE_PASID_ENH_CAP_LIST 0xb4
+#define mmPCIE_PASID_CAP 0xb5
+#define mmPCIE_PASID_CNTL 0xb5
+#define mmPCIE_TPH_REQR_ENH_CAP_LIST 0xb8
+#define mmPCIE_TPH_REQR_CAP 0xb9
+#define mmPCIE_TPH_REQR_CNTL 0xba
+#define mmPCIE_MC_ENH_CAP_LIST 0xbc
+#define mmPCIE_MC_CAP 0xbd
+#define mmPCIE_MC_CNTL 0xbd
+#define mmPCIE_MC_ADDR0 0xbe
+#define mmPCIE_MC_ADDR1 0xbf
+#define mmPCIE_MC_RCV0 0xc0
+#define mmPCIE_MC_RCV1 0xc1
+#define mmPCIE_MC_BLOCK_ALL0 0xc2
+#define mmPCIE_MC_BLOCK_ALL1 0xc3
+#define mmPCIE_MC_BLOCK_UNTRANSLATED_0 0xc4
+#define mmPCIE_MC_BLOCK_UNTRANSLATED_1 0xc5
+#define mmPCIE_LTR_ENH_CAP_LIST 0xc8
+#define mmPCIE_LTR_CAP 0xc9
+#define ixMM_INDEX_IND 0x1090000
+#define ixMM_INDEX_HI_IND 0x1090006
+#define ixMM_DATA_IND 0x1090001
+#define ixBIF_MM_INDACCESS_CNTL_IND 0x1091500
+#define ixBUS_CNTL_IND 0x1091508
+#define ixCONFIG_CNTL_IND 0x1091509
+#define ixCONFIG_MEMSIZE_IND 0x109150a
+#define ixCONFIG_F0_BASE_IND 0x109150b
+#define ixCONFIG_APER_SIZE_IND 0x109150c
+#define ixCONFIG_REG_APER_SIZE_IND 0x109150d
+#define ixBIF_SCRATCH0_IND 0x109150e
+#define ixBIF_SCRATCH1_IND 0x109150f
+#define ixBX_RESET_EN_IND 0x1091514
+#define ixMM_CFGREGS_CNTL_IND 0x1091513
+#define ixHW_DEBUG_IND 0x1091515
+#define ixMASTER_CREDIT_CNTL_IND 0x1091516
+#define ixSLAVE_REQ_CREDIT_CNTL_IND 0x1091517
+#define ixBX_RESET_CNTL_IND 0x1091518
+#define ixINTERRUPT_CNTL_IND 0x109151a
+#define ixINTERRUPT_CNTL2_IND 0x109151b
+#define ixBIF_DEBUG_CNTL_IND 0x109151c
+#define ixBIF_DEBUG_MUX_IND 0x109151d
+#define ixBIF_DEBUG_OUT_IND 0x109151e
+#define ixHDP_REG_COHERENCY_FLUSH_CNTL_IND 0x1091528
+#define ixHDP_MEM_COHERENCY_FLUSH_CNTL_IND 0x1091520
+#define ixCLKREQB_PAD_CNTL_IND 0x1091521
+#define ixSMBDAT_PAD_CNTL_IND 0x1091522
+#define ixSMBCLK_PAD_CNTL_IND 0x1091523
+#define ixBIF_XDMA_LO_IND 0x10914c0
+#define ixBIF_XDMA_HI_IND 0x10914c1
+#define ixBIF_FEATURES_CONTROL_MISC_IND 0x10914c2
+#define ixBIF_DOORBELL_CNTL_IND 0x10914c3
+#define ixBIF_SLVARB_MODE_IND 0x10914c4
+#define ixBIF_FB_EN_IND 0x1091524
+#define ixBIF_BUSNUM_CNTL1_IND 0x1091525
+#define ixBIF_BUSNUM_LIST0_IND 0x1091526
+#define ixBIF_BUSNUM_LIST1_IND 0x1091527
+#define ixBIF_BUSNUM_CNTL2_IND 0x109152b
+#define ixBIF_BUSY_DELAY_CNTR_IND 0x1091529
+#define ixBIF_PERFMON_CNTL_IND 0x109152c
+#define ixBIF_PERFCOUNTER0_RESULT_IND 0x109152d
+#define ixBIF_PERFCOUNTER1_RESULT_IND 0x109152e
+#define ixSLAVE_HANG_PROTECTION_CNTL_IND 0x1091536
+#define ixGPU_HDP_FLUSH_REQ_IND 0x1091537
+#define ixGPU_HDP_FLUSH_DONE_IND 0x1091538
+#define ixSLAVE_HANG_ERROR_IND 0x109153b
+#define ixCAPTURE_HOST_BUSNUM_IND 0x109153c
+#define ixHOST_BUSNUM_IND 0x109153d
+#define ixPEER_REG_RANGE0_IND 0x109153e
+#define ixPEER_REG_RANGE1_IND 0x109153f
+#define ixPEER0_FB_OFFSET_HI_IND 0x10914f3
+#define ixPEER0_FB_OFFSET_LO_IND 0x10914f2
+#define ixPEER1_FB_OFFSET_HI_IND 0x10914f1
+#define ixPEER1_FB_OFFSET_LO_IND 0x10914f0
+#define ixPEER2_FB_OFFSET_HI_IND 0x10914ef
+#define ixPEER2_FB_OFFSET_LO_IND 0x10914ee
+#define ixPEER3_FB_OFFSET_HI_IND 0x10914ed
+#define ixPEER3_FB_OFFSET_LO_IND 0x10914ec
+#define ixDBG_BYPASS_SRBM_ACCESS_IND 0x10914eb
+#define ixSMBUS_BACO_DUMMY_IND 0x10914c6
+#define ixBIF_DEVFUNCNUM_LIST0_IND 0x10914e8
+#define ixBIF_DEVFUNCNUM_LIST1_IND 0x10914e7
+#define ixBACO_CNTL_IND 0x10914e5
+#define ixBF_ANA_ISO_CNTL_IND 0x10914c7
+#define ixMEM_TYPE_CNTL_IND 0x10914e4
+#define ixBIF_BACO_DEBUG_IND 0x10914df
+#define ixBIF_BACO_DEBUG_LATCH_IND 0x10914dc
+#define ixBACO_CNTL_MISC_IND 0x10914db
+#define ixSMU_BIF_VDDGFX_PWR_STATUS_IND 0x10914f8
+#define ixBIF_VDDGFX_GFX0_LOWER_IND 0x1091428
+#define ixBIF_VDDGFX_GFX0_UPPER_IND 0x1091429
+#define ixBIF_VDDGFX_GFX1_LOWER_IND 0x109142a
+#define ixBIF_VDDGFX_GFX1_UPPER_IND 0x109142b
+#define ixBIF_VDDGFX_GFX2_LOWER_IND 0x109142c
+#define ixBIF_VDDGFX_GFX2_UPPER_IND 0x109142d
+#define ixBIF_VDDGFX_GFX3_LOWER_IND 0x109142e
+#define ixBIF_VDDGFX_GFX3_UPPER_IND 0x109142f
+#define ixBIF_VDDGFX_GFX4_LOWER_IND 0x1091430
+#define ixBIF_VDDGFX_GFX4_UPPER_IND 0x1091431
+#define ixBIF_VDDGFX_GFX5_LOWER_IND 0x1091432
+#define ixBIF_VDDGFX_GFX5_UPPER_IND 0x1091433
+#define ixBIF_VDDGFX_RSV1_LOWER_IND 0x1091434
+#define ixBIF_VDDGFX_RSV1_UPPER_IND 0x1091435
+#define ixBIF_VDDGFX_RSV2_LOWER_IND 0x1091436
+#define ixBIF_VDDGFX_RSV2_UPPER_IND 0x1091437
+#define ixBIF_VDDGFX_RSV3_LOWER_IND 0x1091438
+#define ixBIF_VDDGFX_RSV3_UPPER_IND 0x1091439
+#define ixBIF_VDDGFX_RSV4_LOWER_IND 0x109143a
+#define ixBIF_VDDGFX_RSV4_UPPER_IND 0x109143b
+#define ixBIF_VDDGFX_FB_CMP_IND 0x109143c
+#define ixBIF_DOORBELL_GBLAPER1_LOWER_IND 0x10914fc
+#define ixBIF_DOORBELL_GBLAPER1_UPPER_IND 0x10914fd
+#define ixBIF_DOORBELL_GBLAPER2_LOWER_IND 0x10914fe
+#define ixBIF_DOORBELL_GBLAPER2_UPPER_IND 0x10914ff
+#define ixBIF_SMU_INDEX_IND 0x109143d
+#define ixBIF_SMU_DATA_IND 0x109143e
+#define ixIMPCTL_RESET_IND 0x10914f5
+#define ixGARLIC_FLUSH_CNTL_IND 0x1091401
+#define ixGARLIC_FLUSH_REQ_IND 0x1091412
+#define ixGPU_GARLIC_FLUSH_REQ_IND 0x1091413
+#define ixGPU_GARLIC_FLUSH_DONE_IND 0x1091414
+#define ixGARLIC_COHE_CP_RB0_WPTR_IND 0x1091415
+#define ixGARLIC_COHE_CP_RB1_WPTR_IND 0x1091416
+#define ixGARLIC_COHE_CP_RB2_WPTR_IND 0x1091417
+#define ixGARLIC_COHE_UVD_RBC_RB_WPTR_IND 0x1091418
+#define ixGARLIC_COHE_SDMA0_GFX_RB_WPTR_IND 0x1091419
+#define ixGARLIC_COHE_SDMA1_GFX_RB_WPTR_IND 0x109141a
+#define ixGARLIC_COHE_CP_DMA_ME_COMMAND_IND 0x109141b
+#define ixGARLIC_COHE_CP_DMA_PFP_COMMAND_IND 0x109141c
+#define ixGARLIC_COHE_SAM_SAB_RBI_WPTR_IND 0x109141d
+#define ixGARLIC_COHE_SAM_SAB_RBO_WPTR_IND 0x109141e
+#define ixGARLIC_COHE_VCE_OUT_RB_WPTR_IND 0x109141f
+#define ixGARLIC_COHE_VCE_RB_WPTR2_IND 0x1091420
+#define ixGARLIC_COHE_VCE_RB_WPTR_IND 0x1091421
+#define ixGARLIC_COHE_SDMA2_GFX_RB_WPTR_IND 0x1091422
+#define ixGARLIC_COHE_SDMA3_GFX_RB_WPTR_IND 0x1091423
+#define ixGARLIC_COHE_CP_DMA_PIO_COMMAND_IND 0x1091424
+#define ixGARLIC_COHE_GARLIC_FLUSH_REQ_IND 0x1091425
+#define ixREMAP_HDP_MEM_FLUSH_CNTL_IND 0x1091426
+#define ixREMAP_HDP_REG_FLUSH_CNTL_IND 0x1091427
+#define ixBIOS_SCRATCH_0_IND 0x10905c9
+#define ixBIOS_SCRATCH_1_IND 0x10905ca
+#define ixBIOS_SCRATCH_2_IND 0x10905cb
+#define ixBIOS_SCRATCH_3_IND 0x10905cc
+#define ixBIOS_SCRATCH_4_IND 0x10905cd
+#define ixBIOS_SCRATCH_5_IND 0x10905ce
+#define ixBIOS_SCRATCH_6_IND 0x10905cf
+#define ixBIOS_SCRATCH_7_IND 0x10905d0
+#define ixBIOS_SCRATCH_8_IND 0x10905d1
+#define ixBIOS_SCRATCH_9_IND 0x10905d2
+#define ixBIOS_SCRATCH_10_IND 0x10905d3
+#define ixBIOS_SCRATCH_11_IND 0x10905d4
+#define ixBIOS_SCRATCH_12_IND 0x10905d5
+#define ixBIOS_SCRATCH_13_IND 0x10905d6
+#define ixBIOS_SCRATCH_14_IND 0x10905d7
+#define ixBIOS_SCRATCH_15_IND 0x10905d8
+#define ixBIF_RB_CNTL_IND 0x1091530
+#define ixBIF_RB_BASE_IND 0x1091531
+#define ixBIF_RB_RPTR_IND 0x1091532
+#define ixBIF_RB_WPTR_IND 0x1091533
+#define ixBIF_RB_WPTR_ADDR_HI_IND 0x1091534
+#define ixBIF_RB_WPTR_ADDR_LO_IND 0x1091535
+#define mmNB_GBIF_INDEX 0x34
+#define mmNB_GBIF_DATA 0x35
+#define mmPCIE_INDEX 0xe
+#define mmPCIE_DATA 0xf
+#define mmPCIE_INDEX_2 0xc
+#define mmPCIE_DATA_2 0xd
+#define ixPCIE_RESERVED 0x1400000
+#define ixPCIE_SCRATCH 0x1400001
+#define ixPCIE_HW_DEBUG 0x1400002
+#define ixPCIE_RX_NUM_NAK 0x140000e
+#define ixPCIE_RX_NUM_NAK_GENERATED 0x140000f
+#define ixPCIE_CNTL 0x1400010
+#define ixPCIE_CONFIG_CNTL 0x1400011
+#define ixPCIE_DEBUG_CNTL 0x1400012
+#define ixPCIE_INT_CNTL 0x140001a
+#define ixPCIE_INT_STATUS 0x140001b
+#define ixPCIE_CNTL2 0x140001c
+#define ixPCIE_RX_CNTL2 0x140001d
+#define ixPCIE_TX_F0_ATTR_CNTL 0x140001e
+#define ixPCIE_TX_F1_F2_ATTR_CNTL 0x140001f
+#define ixPCIE_CI_CNTL 0x1400020
+#define ixPCIE_BUS_CNTL 0x1400021
+#define ixPCIE_LC_STATE6 0x1400022
+#define ixPCIE_LC_STATE7 0x1400023
+#define ixPCIE_LC_STATE8 0x1400024
+#define ixPCIE_LC_STATE9 0x1400025
+#define ixPCIE_LC_STATE10 0x1400026
+#define ixPCIE_LC_STATE11 0x1400027
+#define ixPCIE_LC_STATUS1 0x1400028
+#define ixPCIE_LC_STATUS2 0x1400029
+#define ixPCIE_WPR_CNTL 0x1400030
+#define ixPCIE_RX_LAST_TLP0 0x1400031
+#define ixPCIE_RX_LAST_TLP1 0x1400032
+#define ixPCIE_RX_LAST_TLP2 0x1400033
+#define ixPCIE_RX_LAST_TLP3 0x1400034
+#define ixPCIE_TX_LAST_TLP0 0x1400035
+#define ixPCIE_TX_LAST_TLP1 0x1400036
+#define ixPCIE_TX_LAST_TLP2 0x1400037
+#define ixPCIE_TX_LAST_TLP3 0x1400038
+#define ixPCIE_I2C_REG_ADDR_EXPAND 0x140003a
+#define ixPCIE_I2C_REG_DATA 0x140003b
+#define ixPCIE_CFG_CNTL 0x140003c
+#define ixPCIE_P_CNTL 0x1400040
+#define ixPCIE_P_BUF_STATUS 0x1400041
+#define ixPCIE_P_DECODER_STATUS 0x1400042
+#define ixPCIE_P_MISC_STATUS 0x1400043
+#define ixPCIE_P_RCV_L0S_FTS_DET 0x1400050
+#define ixPCIE_OBFF_CNTL 0x1400061
+#define ixPCIE_TX_LTR_CNTL 0x1400060
+#define ixPCIE_PERF_COUNT_CNTL 0x1400080
+#define ixPCIE_PERF_CNTL_TXCLK 0x1400081
+#define ixPCIE_PERF_COUNT0_TXCLK 0x1400082
+#define ixPCIE_PERF_COUNT1_TXCLK 0x1400083
+#define ixPCIE_PERF_CNTL_MST_R_CLK 0x1400084
+#define ixPCIE_PERF_COUNT0_MST_R_CLK 0x1400085
+#define ixPCIE_PERF_COUNT1_MST_R_CLK 0x1400086
+#define ixPCIE_PERF_CNTL_MST_C_CLK 0x1400087
+#define ixPCIE_PERF_COUNT0_MST_C_CLK 0x1400088
+#define ixPCIE_PERF_COUNT1_MST_C_CLK 0x1400089
+#define ixPCIE_PERF_CNTL_SLV_R_CLK 0x140008a
+#define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x140008b
+#define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x140008c
+#define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d
+#define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e
+#define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f
+#define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090
+#define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091
+#define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092
+#define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093
+#define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094
+#define ixPCIE_PERF_CNTL_TXCLK2 0x1400095
+#define ixPCIE_PERF_COUNT0_TXCLK2 0x1400096
+#define ixPCIE_PERF_COUNT1_TXCLK2 0x1400097
+#define ixPCIE_STRAP_F0 0x14000b0
+#define ixPCIE_STRAP_F1 0x14000b1
+#define ixPCIE_STRAP_F2 0x14000b2
+#define ixPCIE_STRAP_F3 0x14000b3
+#define ixPCIE_STRAP_F4 0x14000b4
+#define ixPCIE_STRAP_F5 0x14000b5
+#define ixPCIE_STRAP_F6 0x14000b6
+#define ixPCIE_STRAP_F7 0x14000b7
+#define ixPCIE_STRAP_MISC 0x14000c0
+#define ixPCIE_STRAP_MISC2 0x14000c1
+#define ixPCIE_STRAP_PI 0x14000c2
+#define ixPCIE_STRAP_I2C_BD 0x14000c4
+#define ixPCIE_PRBS_CLR 0x14000c8
+#define ixPCIE_PRBS_STATUS1 0x14000c9
+#define ixPCIE_PRBS_STATUS2 0x14000ca
+#define ixPCIE_PRBS_FREERUN 0x14000cb
+#define ixPCIE_PRBS_MISC 0x14000cc
+#define ixPCIE_PRBS_USER_PATTERN 0x14000cd
+#define ixPCIE_PRBS_LO_BITCNT 0x14000ce
+#define ixPCIE_PRBS_HI_BITCNT 0x14000cf
+#define ixPCIE_PRBS_ERRCNT_0 0x14000d0
+#define ixPCIE_PRBS_ERRCNT_1 0x14000d1
+#define ixPCIE_PRBS_ERRCNT_2 0x14000d2
+#define ixPCIE_PRBS_ERRCNT_3 0x14000d3
+#define ixPCIE_PRBS_ERRCNT_4 0x14000d4
+#define ixPCIE_PRBS_ERRCNT_5 0x14000d5
+#define ixPCIE_PRBS_ERRCNT_6 0x14000d6
+#define ixPCIE_PRBS_ERRCNT_7 0x14000d7
+#define ixPCIE_PRBS_ERRCNT_8 0x14000d8
+#define ixPCIE_PRBS_ERRCNT_9 0x14000d9
+#define ixPCIE_PRBS_ERRCNT_10 0x14000da
+#define ixPCIE_PRBS_ERRCNT_11 0x14000db
+#define ixPCIE_PRBS_ERRCNT_12 0x14000dc
+#define ixPCIE_PRBS_ERRCNT_13 0x14000dd
+#define ixPCIE_PRBS_ERRCNT_14 0x14000de
+#define ixPCIE_PRBS_ERRCNT_15 0x14000df
+#define ixPCIE_F0_DPA_CAP 0x14000e0
+#define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x14000e4
+#define ixPCIE_F0_DPA_CNTL 0x14000e5
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x14000e7
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x14000e8
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x14000e9
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x14000ea
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x14000eb
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x14000ec
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x14000ed
+#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x14000ee
+#define ixPCIEP_RESERVED 0x10010000
+#define ixPCIEP_SCRATCH 0x10010001
+#define ixPCIEP_HW_DEBUG 0x10010002
+#define ixPCIEP_PORT_CNTL 0x10010010
+#define ixPCIE_TX_CNTL 0x10010020
+#define ixPCIE_TX_REQUESTER_ID 0x10010021
+#define ixPCIE_TX_VENDOR_SPECIFIC 0x10010022
+#define ixPCIE_TX_REQUEST_NUM_CNTL 0x10010023
+#define ixPCIE_TX_SEQ 0x10010024
+#define ixPCIE_TX_REPLAY 0x10010025
+#define ixPCIE_TX_ACK_LATENCY_LIMIT 0x10010026
+#define ixPCIE_TX_CREDITS_ADVT_P 0x10010030
+#define ixPCIE_TX_CREDITS_ADVT_NP 0x10010031
+#define ixPCIE_TX_CREDITS_ADVT_CPL 0x10010032
+#define ixPCIE_TX_CREDITS_INIT_P 0x10010033
+#define ixPCIE_TX_CREDITS_INIT_NP 0x10010034
+#define ixPCIE_TX_CREDITS_INIT_CPL 0x10010035
+#define ixPCIE_TX_CREDITS_STATUS 0x10010036
+#define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x10010037
+#define ixPCIE_P_PORT_LANE_STATUS 0x10010050
+#define ixPCIE_FC_P 0x10010060
+#define ixPCIE_FC_NP 0x10010061
+#define ixPCIE_FC_CPL 0x10010062
+#define ixPCIE_ERR_CNTL 0x1001006a
+#define ixPCIE_RX_CNTL 0x10010070
+#define ixPCIE_RX_EXPECTED_SEQNUM 0x10010071
+#define ixPCIE_RX_VENDOR_SPECIFIC 0x10010072
+#define ixPCIE_RX_CNTL3 0x10010074
+#define ixPCIE_RX_CREDITS_ALLOCATED_P 0x10010080
+#define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x10010081
+#define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x10010082
+#define ixPCIE_LC_CNTL 0x100100a0
+#define ixPCIE_LC_CNTL2 0x100100b1
+#define ixPCIE_LC_CNTL3 0x100100b5
+#define ixPCIE_LC_CNTL4 0x100100b6
+#define ixPCIE_LC_CNTL5 0x100100b7
+#define ixPCIE_LC_BW_CHANGE_CNTL 0x100100b2
+#define ixPCIE_LC_TRAINING_CNTL 0x100100a1
+#define ixPCIE_LC_LINK_WIDTH_CNTL 0x100100a2
+#define ixPCIE_LC_N_FTS_CNTL 0x100100a3
+#define ixPCIE_LC_SPEED_CNTL 0x100100a4
+#define ixPCIE_LC_CDR_CNTL 0x100100b3
+#define ixPCIE_LC_LANE_CNTL 0x100100b4
+#define ixPCIE_LC_FORCE_COEFF 0x100100b8
+#define ixPCIE_LC_BEST_EQ_SETTINGS 0x100100b9
+#define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x100100ba
+#define ixPCIE_LC_STATE0 0x100100a5
+#define ixPCIE_LC_STATE1 0x100100a6
+#define ixPCIE_LC_STATE2 0x100100a7
+#define ixPCIE_LC_STATE3 0x100100a8
+#define ixPCIE_LC_STATE4 0x100100a9
+#define ixPCIE_LC_STATE5 0x100100aa
+#define ixPCIEP_STRAP_LC 0x100100c0
+#define ixPCIEP_STRAP_MISC 0x100100c1
+#define ixPCIEP_BCH_ECC_CNTL 0x100100d0
+#define mmBIF_RFE_SNOOP_REG 0x27
+#define mmBIF_RFE_WARMRST_CNTL 0x1459
+#define mmBIF_RFE_SOFTRST_CNTL 0x1441
+#define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER 0x1442
+#define mmBIF_RFE_MASTER_SOFTRST_TRIGGER 0x1443
+#define mmBIF_PWDN_COMMAND 0x1444
+#define mmBIF_PWDN_STATUS 0x1445
+#define mmBIF_RFE_MST_FBU_CMDSTATUS 0x1446
+#define mmBIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS 0x1447
+#define mmBIF_RFE_MST_BX_CMDSTATUS 0x1448
+#define mmBIF_RFE_MST_TMOUT_STATUS 0x144b
+#define mmBIF_RFE_MMCFG_CNTL 0x144c
+#define ixBIF_CLOCKS_BITS_IND 0x1301489
+#define ixBIF_LNCNT_RESET_IND 0x1301488
+#define ixLNCNT_CONTROL_IND 0x1301487
+#define ixNEW_REFCLKB_TIMER_IND 0x1301485
+#define ixNEW_REFCLKB_TIMER_1_IND 0x1301484
+#define ixBIF_CLK_PDWN_DELAY_TIMER_IND 0x1301483
+#define ixBIF_RESET_EN_IND 0x1301482
+#define ixBIF_PIF_TXCLK_SWITCH_TIMER_IND 0x1301481
+#define ixBIF_BACO_MSIC_IND 0x1301480
+#define ixBIF_RESET_CNTL_IND 0x1301486
+#define ixBIF_RFE_CNTL_MISC_IND 0x130148c
+#define ixBIF_MEM_PG_CNTL_IND 0x130148a
+#define mmNB_GBIF_INDEX 0x34
+#define mmNB_GBIF_DATA 0x35
+#define mmBIF_CLOCKS_BITS 0x1489
+#define mmBIF_LNCNT_RESET 0x1488
+#define mmLNCNT_CONTROL 0x1487
+#define mmNEW_REFCLKB_TIMER 0x1485
+#define mmNEW_REFCLKB_TIMER_1 0x1484
+#define mmBIF_CLK_PDWN_DELAY_TIMER 0x1483
+#define mmBIF_RESET_EN 0x1482
+#define mmBIF_PIF_TXCLK_SWITCH_TIMER 0x1481
+#define mmBIF_BACO_MSIC 0x1480
+#define mmBIF_RESET_CNTL 0x1486
+#define mmBIF_RFE_CNTL_MISC 0x148c
+#define mmBIF_MEM_PG_CNTL 0x148a
+#define mmC_PCIE_P_INDEX 0x38
+#define mmC_PCIE_P_DATA 0x39
+#define ixD2F1_PCIE_PORT_INDEX 0x2000038
+#define ixD2F1_PCIE_PORT_DATA 0x2000039
+#define ixD2F1_PCIEP_RESERVED 0x0
+#define ixD2F1_PCIEP_SCRATCH 0x1
+#define ixD2F1_PCIEP_HW_DEBUG 0x2
+#define ixD2F1_PCIEP_PORT_CNTL 0x10
+#define ixD2F1_PCIE_TX_CNTL 0x20
+#define ixD2F1_PCIE_TX_REQUESTER_ID 0x21
+#define ixD2F1_PCIE_TX_VENDOR_SPECIFIC 0x22
+#define ixD2F1_PCIE_TX_REQUEST_NUM_CNTL 0x23
+#define ixD2F1_PCIE_TX_SEQ 0x24
+#define ixD2F1_PCIE_TX_REPLAY 0x25
+#define ixD2F1_PCIE_TX_ACK_LATENCY_LIMIT 0x26
+#define ixD2F1_PCIE_TX_CREDITS_ADVT_P 0x30
+#define ixD2F1_PCIE_TX_CREDITS_ADVT_NP 0x31
+#define ixD2F1_PCIE_TX_CREDITS_ADVT_CPL 0x32
+#define ixD2F1_PCIE_TX_CREDITS_INIT_P 0x33
+#define ixD2F1_PCIE_TX_CREDITS_INIT_NP 0x34
+#define ixD2F1_PCIE_TX_CREDITS_INIT_CPL 0x35
+#define ixD2F1_PCIE_TX_CREDITS_STATUS 0x36
+#define ixD2F1_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37
+#define ixD2F1_PCIE_P_PORT_LANE_STATUS 0x50
+#define ixD2F1_PCIE_FC_P 0x60
+#define ixD2F1_PCIE_FC_NP 0x61
+#define ixD2F1_PCIE_FC_CPL 0x62
+#define ixD2F1_PCIE_ERR_CNTL 0x6a
+#define ixD2F1_PCIE_RX_CNTL 0x70
+#define ixD2F1_PCIE_RX_EXPECTED_SEQNUM 0x71
+#define ixD2F1_PCIE_RX_VENDOR_SPECIFIC 0x72
+#define ixD2F1_PCIE_RX_CNTL3 0x74
+#define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_P 0x80
+#define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_NP 0x81
+#define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82
+#define ixD2F1_PCIEP_ERROR_INJECT_PHYSICAL 0x83
+#define ixD2F1_PCIEP_ERROR_INJECT_TRANSACTION 0x84
+#define ixD2F1_PCIE_LC_CNTL 0xa0
+#define ixD2F1_PCIE_LC_CNTL2 0xb1
+#define ixD2F1_PCIE_LC_CNTL3 0xb5
+#define ixD2F1_PCIE_LC_CNTL4 0xb6
+#define ixD2F1_PCIE_LC_CNTL5 0xb7
+#define ixD2F1_PCIE_LC_CNTL6 0xbb
+#define ixD2F1_PCIE_LC_BW_CHANGE_CNTL 0xb2
+#define ixD2F1_PCIE_LC_TRAINING_CNTL 0xa1
+#define ixD2F1_PCIE_LC_LINK_WIDTH_CNTL 0xa2
+#define ixD2F1_PCIE_LC_N_FTS_CNTL 0xa3
+#define ixD2F1_PCIE_LC_SPEED_CNTL 0xa4
+#define ixD2F1_PCIE_LC_CDR_CNTL 0xb3
+#define ixD2F1_PCIE_LC_LANE_CNTL 0xb4
+#define ixD2F1_PCIE_LC_FORCE_COEFF 0xb8
+#define ixD2F1_PCIE_LC_BEST_EQ_SETTINGS 0xb9
+#define ixD2F1_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba
+#define ixD2F1_PCIE_LC_STATE0 0xa5
+#define ixD2F1_PCIE_LC_STATE1 0xa6
+#define ixD2F1_PCIE_LC_STATE2 0xa7
+#define ixD2F1_PCIE_LC_STATE3 0xa8
+#define ixD2F1_PCIE_LC_STATE4 0xa9
+#define ixD2F1_PCIE_LC_STATE5 0xaa
+#define ixD2F1_PCIEP_STRAP_LC 0xc0
+#define ixD2F1_PCIEP_STRAP_MISC 0xc1
+#define ixD2F1_PCIEP_BCH_ECC_CNTL 0xd0
+#define ixD2F1_PCIEP_HPGI_PRIVATE 0xd2
+#define ixD2F1_PCIEP_HPGI 0xda
+#define ixD2F1_VENDOR_ID 0x2000000
+#define ixD2F1_DEVICE_ID 0x2000000
+#define ixD2F1_COMMAND 0x2000001
+#define ixD2F1_STATUS 0x2000001
+#define ixD2F1_REVISION_ID 0x2000002
+#define ixD2F1_PROG_INTERFACE 0x2000002
+#define ixD2F1_SUB_CLASS 0x2000002
+#define ixD2F1_BASE_CLASS 0x2000002
+#define ixD2F1_CACHE_LINE 0x2000003
+#define ixD2F1_LATENCY 0x2000003
+#define ixD2F1_HEADER 0x2000003
+#define ixD2F1_BIST 0x2000003
+#define ixD2F1_SUB_BUS_NUMBER_LATENCY 0x2000006
+#define ixD2F1_IO_BASE_LIMIT 0x2000007
+#define ixD2F1_SECONDARY_STATUS 0x2000007
+#define ixD2F1_MEM_BASE_LIMIT 0x2000008
+#define ixD2F1_PREF_BASE_LIMIT 0x2000009
+#define ixD2F1_PREF_BASE_UPPER 0x200000a
+#define ixD2F1_PREF_LIMIT_UPPER 0x200000b
+#define ixD2F1_IO_BASE_LIMIT_HI 0x200000c
+#define ixD2F1_IRQ_BRIDGE_CNTL 0x200000f
+#define ixD2F1_CAP_PTR 0x200000d
+#define ixD2F1_INTERRUPT_LINE 0x200000f
+#define ixD2F1_INTERRUPT_PIN 0x200000f
+#define ixD2F1_EXT_BRIDGE_CNTL 0x2000010
+#define ixD2F1_PMI_CAP_LIST 0x2000014
+#define ixD2F1_PMI_CAP 0x2000014
+#define ixD2F1_PMI_STATUS_CNTL 0x2000015
+#define ixD2F1_PCIE_CAP_LIST 0x2000016
+#define ixD2F1_PCIE_CAP 0x2000016
+#define ixD2F1_DEVICE_CAP 0x2000017
+#define ixD2F1_DEVICE_CNTL 0x2000018
+#define ixD2F1_DEVICE_STATUS 0x2000018
+#define ixD2F1_LINK_CAP 0x2000019
+#define ixD2F1_LINK_CNTL 0x200001a
+#define ixD2F1_LINK_STATUS 0x200001a
+#define ixD2F1_SLOT_CAP 0x200001b
+#define ixD2F1_SLOT_CNTL 0x200001c
+#define ixD2F1_SLOT_STATUS 0x200001c
+#define ixD2F1_ROOT_CNTL 0x200001d
+#define ixD2F1_ROOT_CAP 0x200001d
+#define ixD2F1_ROOT_STATUS 0x200001e
+#define ixD2F1_DEVICE_CAP2 0x200001f
+#define ixD2F1_DEVICE_CNTL2 0x2000020
+#define ixD2F1_DEVICE_STATUS2 0x2000020
+#define ixD2F1_LINK_CAP2 0x2000021
+#define ixD2F1_LINK_CNTL2 0x2000022
+#define ixD2F1_LINK_STATUS2 0x2000022
+#define ixD2F1_SLOT_CAP2 0x2000023
+#define ixD2F1_SLOT_CNTL2 0x2000024
+#define ixD2F1_SLOT_STATUS2 0x2000024
+#define ixD2F1_MSI_CAP_LIST 0x2000028
+#define ixD2F1_MSI_MSG_CNTL 0x2000028
+#define ixD2F1_MSI_MSG_ADDR_LO 0x2000029
+#define ixD2F1_MSI_MSG_ADDR_HI 0x200002a
+#define ixD2F1_MSI_MSG_DATA_64 0x200002b
+#define ixD2F1_MSI_MSG_DATA 0x200002a
+#define ixD2F1_SSID_CAP_LIST 0x2000030
+#define ixD2F1_SSID_CAP 0x2000031
+#define ixD2F1_MSI_MAP_CAP_LIST 0x2000032
+#define ixD2F1_MSI_MAP_CAP 0x2000032
+#define ixD2F1_MSI_MAP_ADDR_LO 0x2000033
+#define ixD2F1_MSI_MAP_ADDR_HI 0x2000034
+#define ixD2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x2000040
+#define ixD2F1_PCIE_VENDOR_SPECIFIC_HDR 0x2000041
+#define ixD2F1_PCIE_VENDOR_SPECIFIC1 0x2000042
+#define ixD2F1_PCIE_VENDOR_SPECIFIC2 0x2000043
+#define ixD2F1_PCIE_VC_ENH_CAP_LIST 0x2000044
+#define ixD2F1_PCIE_PORT_VC_CAP_REG1 0x2000045
+#define ixD2F1_PCIE_PORT_VC_CAP_REG2 0x2000046
+#define ixD2F1_PCIE_PORT_VC_CNTL 0x2000047
+#define ixD2F1_PCIE_PORT_VC_STATUS 0x2000047
+#define ixD2F1_PCIE_VC0_RESOURCE_CAP 0x2000048
+#define ixD2F1_PCIE_VC0_RESOURCE_CNTL 0x2000049
+#define ixD2F1_PCIE_VC0_RESOURCE_STATUS 0x200004a
+#define ixD2F1_PCIE_VC1_RESOURCE_CAP 0x200004b
+#define ixD2F1_PCIE_VC1_RESOURCE_CNTL 0x200004c
+#define ixD2F1_PCIE_VC1_RESOURCE_STATUS 0x200004d
+#define ixD2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x2000050
+#define ixD2F1_PCIE_DEV_SERIAL_NUM_DW1 0x2000051
+#define ixD2F1_PCIE_DEV_SERIAL_NUM_DW2 0x2000052
+#define ixD2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x2000054
+#define ixD2F1_PCIE_UNCORR_ERR_STATUS 0x2000055
+#define ixD2F1_PCIE_UNCORR_ERR_MASK 0x2000056
+#define ixD2F1_PCIE_UNCORR_ERR_SEVERITY 0x2000057
+#define ixD2F1_PCIE_CORR_ERR_STATUS 0x2000058
+#define ixD2F1_PCIE_CORR_ERR_MASK 0x2000059
+#define ixD2F1_PCIE_ADV_ERR_CAP_CNTL 0x200005a
+#define ixD2F1_PCIE_HDR_LOG0 0x200005b
+#define ixD2F1_PCIE_HDR_LOG1 0x200005c
+#define ixD2F1_PCIE_HDR_LOG2 0x200005d
+#define ixD2F1_PCIE_HDR_LOG3 0x200005e
+#define ixD2F1_PCIE_ROOT_ERR_CMD 0x200005f
+#define ixD2F1_PCIE_ROOT_ERR_STATUS 0x2000060
+#define ixD2F1_PCIE_ERR_SRC_ID 0x2000061
+#define ixD2F1_PCIE_TLP_PREFIX_LOG0 0x2000062
+#define ixD2F1_PCIE_TLP_PREFIX_LOG1 0x2000063
+#define ixD2F1_PCIE_TLP_PREFIX_LOG2 0x2000064
+#define ixD2F1_PCIE_TLP_PREFIX_LOG3 0x2000065
+#define ixD2F1_PCIE_SECONDARY_ENH_CAP_LIST 0x200009c
+#define ixD2F1_PCIE_LINK_CNTL3 0x200009d
+#define ixD2F1_PCIE_LANE_ERROR_STATUS 0x200009e
+#define ixD2F1_PCIE_LANE_0_EQUALIZATION_CNTL 0x200009f
+#define ixD2F1_PCIE_LANE_1_EQUALIZATION_CNTL 0x200009f
+#define ixD2F1_PCIE_LANE_2_EQUALIZATION_CNTL 0x20000a0
+#define ixD2F1_PCIE_LANE_3_EQUALIZATION_CNTL 0x20000a0
+#define ixD2F1_PCIE_LANE_4_EQUALIZATION_CNTL 0x20000a1
+#define ixD2F1_PCIE_LANE_5_EQUALIZATION_CNTL 0x20000a1
+#define ixD2F1_PCIE_LANE_6_EQUALIZATION_CNTL 0x20000a2
+#define ixD2F1_PCIE_LANE_7_EQUALIZATION_CNTL 0x20000a2
+#define ixD2F1_PCIE_LANE_8_EQUALIZATION_CNTL 0x20000a3
+#define ixD2F1_PCIE_LANE_9_EQUALIZATION_CNTL 0x20000a3
+#define ixD2F1_PCIE_LANE_10_EQUALIZATION_CNTL 0x20000a4
+#define ixD2F1_PCIE_LANE_11_EQUALIZATION_CNTL 0x20000a4
+#define ixD2F1_PCIE_LANE_12_EQUALIZATION_CNTL 0x20000a5
+#define ixD2F1_PCIE_LANE_13_EQUALIZATION_CNTL 0x20000a5
+#define ixD2F1_PCIE_LANE_14_EQUALIZATION_CNTL 0x20000a6
+#define ixD2F1_PCIE_LANE_15_EQUALIZATION_CNTL 0x20000a6
+#define ixD2F1_PCIE_ACS_ENH_CAP_LIST 0x20000a8
+#define ixD2F1_PCIE_ACS_CAP 0x20000a9
+#define ixD2F1_PCIE_ACS_CNTL 0x20000a9
+#define ixD2F1_PCIE_MC_ENH_CAP_LIST 0x20000bc
+#define ixD2F1_PCIE_MC_CAP 0x20000bd
+#define ixD2F1_PCIE_MC_CNTL 0x20000bd
+#define ixD2F1_PCIE_MC_ADDR0 0x20000be
+#define ixD2F1_PCIE_MC_ADDR1 0x20000bf
+#define ixD2F1_PCIE_MC_RCV0 0x20000c0
+#define ixD2F1_PCIE_MC_RCV1 0x20000c1
+#define ixD2F1_PCIE_MC_BLOCK_ALL0 0x20000c2
+#define ixD2F1_PCIE_MC_BLOCK_ALL1 0x20000c3
+#define ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x20000c4
+#define ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x20000c5
+#define ixD2F1_PCIE_MC_OVERLAY_BAR0 0x20000c6
+#define ixD2F1_PCIE_MC_OVERLAY_BAR1 0x20000c7
+#define ixD2F2_PCIE_PORT_INDEX 0x3000038
+#define ixD2F2_PCIE_PORT_DATA 0x3000039
+#define ixD2F2_PCIEP_RESERVED 0x0
+#define ixD2F2_PCIEP_SCRATCH 0x1
+#define ixD2F2_PCIEP_HW_DEBUG 0x2
+#define ixD2F2_PCIEP_PORT_CNTL 0x10
+#define ixD2F2_PCIE_TX_CNTL 0x20
+#define ixD2F2_PCIE_TX_REQUESTER_ID 0x21
+#define ixD2F2_PCIE_TX_VENDOR_SPECIFIC 0x22
+#define ixD2F2_PCIE_TX_REQUEST_NUM_CNTL 0x23
+#define ixD2F2_PCIE_TX_SEQ 0x24
+#define ixD2F2_PCIE_TX_REPLAY 0x25
+#define ixD2F2_PCIE_TX_ACK_LATENCY_LIMIT 0x26
+#define ixD2F2_PCIE_TX_CREDITS_ADVT_P 0x30
+#define ixD2F2_PCIE_TX_CREDITS_ADVT_NP 0x31
+#define ixD2F2_PCIE_TX_CREDITS_ADVT_CPL 0x32
+#define ixD2F2_PCIE_TX_CREDITS_INIT_P 0x33
+#define ixD2F2_PCIE_TX_CREDITS_INIT_NP 0x34
+#define ixD2F2_PCIE_TX_CREDITS_INIT_CPL 0x35
+#define ixD2F2_PCIE_TX_CREDITS_STATUS 0x36
+#define ixD2F2_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37
+#define ixD2F2_PCIE_P_PORT_LANE_STATUS 0x50
+#define ixD2F2_PCIE_FC_P 0x60
+#define ixD2F2_PCIE_FC_NP 0x61
+#define ixD2F2_PCIE_FC_CPL 0x62
+#define ixD2F2_PCIE_ERR_CNTL 0x6a
+#define ixD2F2_PCIE_RX_CNTL 0x70
+#define ixD2F2_PCIE_RX_EXPECTED_SEQNUM 0x71
+#define ixD2F2_PCIE_RX_VENDOR_SPECIFIC 0x72
+#define ixD2F2_PCIE_RX_CNTL3 0x74
+#define ixD2F2_PCIE_RX_CREDITS_ALLOCATED_P 0x80
+#define ixD2F2_PCIE_RX_CREDITS_ALLOCATED_NP 0x81
+#define ixD2F2_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82
+#define ixD2F2_PCIEP_ERROR_INJECT_PHYSICAL 0x83
+#define ixD2F2_PCIEP_ERROR_INJECT_TRANSACTION 0x84
+#define ixD2F2_PCIE_LC_CNTL 0xa0
+#define ixD2F2_PCIE_LC_CNTL2 0xb1
+#define ixD2F2_PCIE_LC_CNTL3 0xb5
+#define ixD2F2_PCIE_LC_CNTL4 0xb6
+#define ixD2F2_PCIE_LC_CNTL5 0xb7
+#define ixD2F2_PCIE_LC_CNTL6 0xbb
+#define ixD2F2_PCIE_LC_BW_CHANGE_CNTL 0xb2
+#define ixD2F2_PCIE_LC_TRAINING_CNTL 0xa1
+#define ixD2F2_PCIE_LC_LINK_WIDTH_CNTL 0xa2
+#define ixD2F2_PCIE_LC_N_FTS_CNTL 0xa3
+#define ixD2F2_PCIE_LC_SPEED_CNTL 0xa4
+#define ixD2F2_PCIE_LC_CDR_CNTL 0xb3
+#define ixD2F2_PCIE_LC_LANE_CNTL 0xb4
+#define ixD2F2_PCIE_LC_FORCE_COEFF 0xb8
+#define ixD2F2_PCIE_LC_BEST_EQ_SETTINGS 0xb9
+#define ixD2F2_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba
+#define ixD2F2_PCIE_LC_STATE0 0xa5
+#define ixD2F2_PCIE_LC_STATE1 0xa6
+#define ixD2F2_PCIE_LC_STATE2 0xa7
+#define ixD2F2_PCIE_LC_STATE3 0xa8
+#define ixD2F2_PCIE_LC_STATE4 0xa9
+#define ixD2F2_PCIE_LC_STATE5 0xaa
+#define ixD2F2_PCIEP_STRAP_LC 0xc0
+#define ixD2F2_PCIEP_STRAP_MISC 0xc1
+#define ixD2F2_PCIEP_BCH_ECC_CNTL 0xd0
+#define ixD2F2_PCIEP_HPGI_PRIVATE 0xd2
+#define ixD2F2_PCIEP_HPGI 0xda
+#define ixD2F2_VENDOR_ID 0x3000000
+#define ixD2F2_DEVICE_ID 0x3000000
+#define ixD2F2_COMMAND 0x3000001
+#define ixD2F2_STATUS 0x3000001
+#define ixD2F2_REVISION_ID 0x3000002
+#define ixD2F2_PROG_INTERFACE 0x3000002
+#define ixD2F2_SUB_CLASS 0x3000002
+#define ixD2F2_BASE_CLASS 0x3000002
+#define ixD2F2_CACHE_LINE 0x3000003
+#define ixD2F2_LATENCY 0x3000003
+#define ixD2F2_HEADER 0x3000003
+#define ixD2F2_BIST 0x3000003
+#define ixD2F2_SUB_BUS_NUMBER_LATENCY 0x3000006
+#define ixD2F2_IO_BASE_LIMIT 0x3000007
+#define ixD2F2_SECONDARY_STATUS 0x3000007
+#define ixD2F2_MEM_BASE_LIMIT 0x3000008
+#define ixD2F2_PREF_BASE_LIMIT 0x3000009
+#define ixD2F2_PREF_BASE_UPPER 0x300000a
+#define ixD2F2_PREF_LIMIT_UPPER 0x300000b
+#define ixD2F2_IO_BASE_LIMIT_HI 0x300000c
+#define ixD2F2_IRQ_BRIDGE_CNTL 0x300000f
+#define ixD2F2_CAP_PTR 0x300000d
+#define ixD2F2_INTERRUPT_LINE 0x300000f
+#define ixD2F2_INTERRUPT_PIN 0x300000f
+#define ixD2F2_EXT_BRIDGE_CNTL 0x3000010
+#define ixD2F2_PMI_CAP_LIST 0x3000014
+#define ixD2F2_PMI_CAP 0x3000014
+#define ixD2F2_PMI_STATUS_CNTL 0x3000015
+#define ixD2F2_PCIE_CAP_LIST 0x3000016
+#define ixD2F2_PCIE_CAP 0x3000016
+#define ixD2F2_DEVICE_CAP 0x3000017
+#define ixD2F2_DEVICE_CNTL 0x3000018
+#define ixD2F2_DEVICE_STATUS 0x3000018
+#define ixD2F2_LINK_CAP 0x3000019
+#define ixD2F2_LINK_CNTL 0x300001a
+#define ixD2F2_LINK_STATUS 0x300001a
+#define ixD2F2_SLOT_CAP 0x300001b
+#define ixD2F2_SLOT_CNTL 0x300001c
+#define ixD2F2_SLOT_STATUS 0x300001c
+#define ixD2F2_ROOT_CNTL 0x300001d
+#define ixD2F2_ROOT_CAP 0x300001d
+#define ixD2F2_ROOT_STATUS 0x300001e
+#define ixD2F2_DEVICE_CAP2 0x300001f
+#define ixD2F2_DEVICE_CNTL2 0x3000020
+#define ixD2F2_DEVICE_STATUS2 0x3000020
+#define ixD2F2_LINK_CAP2 0x3000021
+#define ixD2F2_LINK_CNTL2 0x3000022
+#define ixD2F2_LINK_STATUS2 0x3000022
+#define ixD2F2_SLOT_CAP2 0x3000023
+#define ixD2F2_SLOT_CNTL2 0x3000024
+#define ixD2F2_SLOT_STATUS2 0x3000024
+#define ixD2F2_MSI_CAP_LIST 0x3000028
+#define ixD2F2_MSI_MSG_CNTL 0x3000028
+#define ixD2F2_MSI_MSG_ADDR_LO 0x3000029
+#define ixD2F2_MSI_MSG_ADDR_HI 0x300002a
+#define ixD2F2_MSI_MSG_DATA_64 0x300002b
+#define ixD2F2_MSI_MSG_DATA 0x300002a
+#define ixD2F2_SSID_CAP_LIST 0x3000030
+#define ixD2F2_SSID_CAP 0x3000031
+#define ixD2F2_MSI_MAP_CAP_LIST 0x3000032
+#define ixD2F2_MSI_MAP_CAP 0x3000032
+#define ixD2F2_MSI_MAP_ADDR_LO 0x3000033
+#define ixD2F2_MSI_MAP_ADDR_HI 0x3000034
+#define ixD2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3000040
+#define ixD2F2_PCIE_VENDOR_SPECIFIC_HDR 0x3000041
+#define ixD2F2_PCIE_VENDOR_SPECIFIC1 0x3000042
+#define ixD2F2_PCIE_VENDOR_SPECIFIC2 0x3000043
+#define ixD2F2_PCIE_VC_ENH_CAP_LIST 0x3000044
+#define ixD2F2_PCIE_PORT_VC_CAP_REG1 0x3000045
+#define ixD2F2_PCIE_PORT_VC_CAP_REG2 0x3000046
+#define ixD2F2_PCIE_PORT_VC_CNTL 0x3000047
+#define ixD2F2_PCIE_PORT_VC_STATUS 0x3000047
+#define ixD2F2_PCIE_VC0_RESOURCE_CAP 0x3000048
+#define ixD2F2_PCIE_VC0_RESOURCE_CNTL 0x3000049
+#define ixD2F2_PCIE_VC0_RESOURCE_STATUS 0x300004a
+#define ixD2F2_PCIE_VC1_RESOURCE_CAP 0x300004b
+#define ixD2F2_PCIE_VC1_RESOURCE_CNTL 0x300004c
+#define ixD2F2_PCIE_VC1_RESOURCE_STATUS 0x300004d
+#define ixD2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x3000050
+#define ixD2F2_PCIE_DEV_SERIAL_NUM_DW1 0x3000051
+#define ixD2F2_PCIE_DEV_SERIAL_NUM_DW2 0x3000052
+#define ixD2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3000054
+#define ixD2F2_PCIE_UNCORR_ERR_STATUS 0x3000055
+#define ixD2F2_PCIE_UNCORR_ERR_MASK 0x3000056
+#define ixD2F2_PCIE_UNCORR_ERR_SEVERITY 0x3000057
+#define ixD2F2_PCIE_CORR_ERR_STATUS 0x3000058
+#define ixD2F2_PCIE_CORR_ERR_MASK 0x3000059
+#define ixD2F2_PCIE_ADV_ERR_CAP_CNTL 0x300005a
+#define ixD2F2_PCIE_HDR_LOG0 0x300005b
+#define ixD2F2_PCIE_HDR_LOG1 0x300005c
+#define ixD2F2_PCIE_HDR_LOG2 0x300005d
+#define ixD2F2_PCIE_HDR_LOG3 0x300005e
+#define ixD2F2_PCIE_ROOT_ERR_CMD 0x300005f
+#define ixD2F2_PCIE_ROOT_ERR_STATUS 0x3000060
+#define ixD2F2_PCIE_ERR_SRC_ID 0x3000061
+#define ixD2F2_PCIE_TLP_PREFIX_LOG0 0x3000062
+#define ixD2F2_PCIE_TLP_PREFIX_LOG1 0x3000063
+#define ixD2F2_PCIE_TLP_PREFIX_LOG2 0x3000064
+#define ixD2F2_PCIE_TLP_PREFIX_LOG3 0x3000065
+#define ixD2F2_PCIE_SECONDARY_ENH_CAP_LIST 0x300009c
+#define ixD2F2_PCIE_LINK_CNTL3 0x300009d
+#define ixD2F2_PCIE_LANE_ERROR_STATUS 0x300009e
+#define ixD2F2_PCIE_LANE_0_EQUALIZATION_CNTL 0x300009f
+#define ixD2F2_PCIE_LANE_1_EQUALIZATION_CNTL 0x300009f
+#define ixD2F2_PCIE_LANE_2_EQUALIZATION_CNTL 0x30000a0
+#define ixD2F2_PCIE_LANE_3_EQUALIZATION_CNTL 0x30000a0
+#define ixD2F2_PCIE_LANE_4_EQUALIZATION_CNTL 0x30000a1
+#define ixD2F2_PCIE_LANE_5_EQUALIZATION_CNTL 0x30000a1
+#define ixD2F2_PCIE_LANE_6_EQUALIZATION_CNTL 0x30000a2
+#define ixD2F2_PCIE_LANE_7_EQUALIZATION_CNTL 0x30000a2
+#define ixD2F2_PCIE_LANE_8_EQUALIZATION_CNTL 0x30000a3
+#define ixD2F2_PCIE_LANE_9_EQUALIZATION_CNTL 0x30000a3
+#define ixD2F2_PCIE_LANE_10_EQUALIZATION_CNTL 0x30000a4
+#define ixD2F2_PCIE_LANE_11_EQUALIZATION_CNTL 0x30000a4
+#define ixD2F2_PCIE_LANE_12_EQUALIZATION_CNTL 0x30000a5
+#define ixD2F2_PCIE_LANE_13_EQUALIZATION_CNTL 0x30000a5
+#define ixD2F2_PCIE_LANE_14_EQUALIZATION_CNTL 0x30000a6
+#define ixD2F2_PCIE_LANE_15_EQUALIZATION_CNTL 0x30000a6
+#define ixD2F2_PCIE_ACS_ENH_CAP_LIST 0x30000a8
+#define ixD2F2_PCIE_ACS_CAP 0x30000a9
+#define ixD2F2_PCIE_ACS_CNTL 0x30000a9
+#define ixD2F2_PCIE_MC_ENH_CAP_LIST 0x30000bc
+#define ixD2F2_PCIE_MC_CAP 0x30000bd
+#define ixD2F2_PCIE_MC_CNTL 0x30000bd
+#define ixD2F2_PCIE_MC_ADDR0 0x30000be
+#define ixD2F2_PCIE_MC_ADDR1 0x30000bf
+#define ixD2F2_PCIE_MC_RCV0 0x30000c0
+#define ixD2F2_PCIE_MC_RCV1 0x30000c1
+#define ixD2F2_PCIE_MC_BLOCK_ALL0 0x30000c2
+#define ixD2F2_PCIE_MC_BLOCK_ALL1 0x30000c3
+#define ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_0 0x30000c4
+#define ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_1 0x30000c5
+#define ixD2F2_PCIE_MC_OVERLAY_BAR0 0x30000c6
+#define ixD2F2_PCIE_MC_OVERLAY_BAR1 0x30000c7
+#define ixD2F3_PCIE_PORT_INDEX 0x4000038
+#define ixD2F3_PCIE_PORT_DATA 0x4000039
+#define ixD2F3_PCIEP_RESERVED 0x0
+#define ixD2F3_PCIEP_SCRATCH 0x1
+#define ixD2F3_PCIEP_HW_DEBUG 0x2
+#define ixD2F3_PCIEP_PORT_CNTL 0x10
+#define ixD2F3_PCIE_TX_CNTL 0x20
+#define ixD2F3_PCIE_TX_REQUESTER_ID 0x21
+#define ixD2F3_PCIE_TX_VENDOR_SPECIFIC 0x22
+#define ixD2F3_PCIE_TX_REQUEST_NUM_CNTL 0x23
+#define ixD2F3_PCIE_TX_SEQ 0x24
+#define ixD2F3_PCIE_TX_REPLAY 0x25
+#define ixD2F3_PCIE_TX_ACK_LATENCY_LIMIT 0x26
+#define ixD2F3_PCIE_TX_CREDITS_ADVT_P 0x30
+#define ixD2F3_PCIE_TX_CREDITS_ADVT_NP 0x31
+#define ixD2F3_PCIE_TX_CREDITS_ADVT_CPL 0x32
+#define ixD2F3_PCIE_TX_CREDITS_INIT_P 0x33
+#define ixD2F3_PCIE_TX_CREDITS_INIT_NP 0x34
+#define ixD2F3_PCIE_TX_CREDITS_INIT_CPL 0x35
+#define ixD2F3_PCIE_TX_CREDITS_STATUS 0x36
+#define ixD2F3_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37
+#define ixD2F3_PCIE_P_PORT_LANE_STATUS 0x50
+#define ixD2F3_PCIE_FC_P 0x60
+#define ixD2F3_PCIE_FC_NP 0x61
+#define ixD2F3_PCIE_FC_CPL 0x62
+#define ixD2F3_PCIE_ERR_CNTL 0x6a
+#define ixD2F3_PCIE_RX_CNTL 0x70
+#define ixD2F3_PCIE_RX_EXPECTED_SEQNUM 0x71
+#define ixD2F3_PCIE_RX_VENDOR_SPECIFIC 0x72
+#define ixD2F3_PCIE_RX_CNTL3 0x74
+#define ixD2F3_PCIE_RX_CREDITS_ALLOCATED_P 0x80
+#define ixD2F3_PCIE_RX_CREDITS_ALLOCATED_NP 0x81
+#define ixD2F3_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82
+#define ixD2F3_PCIEP_ERROR_INJECT_PHYSICAL 0x83
+#define ixD2F3_PCIEP_ERROR_INJECT_TRANSACTION 0x84
+#define ixD2F3_PCIE_LC_CNTL 0xa0
+#define ixD2F3_PCIE_LC_CNTL2 0xb1
+#define ixD2F3_PCIE_LC_CNTL3 0xb5
+#define ixD2F3_PCIE_LC_CNTL4 0xb6
+#define ixD2F3_PCIE_LC_CNTL5 0xb7
+#define ixD2F3_PCIE_LC_CNTL6 0xbb
+#define ixD2F3_PCIE_LC_BW_CHANGE_CNTL 0xb2
+#define ixD2F3_PCIE_LC_TRAINING_CNTL 0xa1
+#define ixD2F3_PCIE_LC_LINK_WIDTH_CNTL 0xa2
+#define ixD2F3_PCIE_LC_N_FTS_CNTL 0xa3
+#define ixD2F3_PCIE_LC_SPEED_CNTL 0xa4
+#define ixD2F3_PCIE_LC_CDR_CNTL 0xb3
+#define ixD2F3_PCIE_LC_LANE_CNTL 0xb4
+#define ixD2F3_PCIE_LC_FORCE_COEFF 0xb8
+#define ixD2F3_PCIE_LC_BEST_EQ_SETTINGS 0xb9
+#define ixD2F3_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba
+#define ixD2F3_PCIE_LC_STATE0 0xa5
+#define ixD2F3_PCIE_LC_STATE1 0xa6
+#define ixD2F3_PCIE_LC_STATE2 0xa7
+#define ixD2F3_PCIE_LC_STATE3 0xa8
+#define ixD2F3_PCIE_LC_STATE4 0xa9
+#define ixD2F3_PCIE_LC_STATE5 0xaa
+#define ixD2F3_PCIEP_STRAP_LC 0xc0
+#define ixD2F3_PCIEP_STRAP_MISC 0xc1
+#define ixD2F3_PCIEP_BCH_ECC_CNTL 0xd0
+#define ixD2F3_PCIEP_HPGI_PRIVATE 0xd2
+#define ixD2F3_PCIEP_HPGI 0xda
+#define ixD2F3_VENDOR_ID 0x4000000
+#define ixD2F3_DEVICE_ID 0x4000000
+#define ixD2F3_COMMAND 0x4000001
+#define ixD2F3_STATUS 0x4000001
+#define ixD2F3_REVISION_ID 0x4000002
+#define ixD2F3_PROG_INTERFACE 0x4000002
+#define ixD2F3_SUB_CLASS 0x4000002
+#define ixD2F3_BASE_CLASS 0x4000002
+#define ixD2F3_CACHE_LINE 0x4000003
+#define ixD2F3_LATENCY 0x4000003
+#define ixD2F3_HEADER 0x4000003
+#define ixD2F3_BIST 0x4000003
+#define ixD2F3_SUB_BUS_NUMBER_LATENCY 0x4000006
+#define ixD2F3_IO_BASE_LIMIT 0x4000007
+#define ixD2F3_SECONDARY_STATUS 0x4000007
+#define ixD2F3_MEM_BASE_LIMIT 0x4000008
+#define ixD2F3_PREF_BASE_LIMIT 0x4000009
+#define ixD2F3_PREF_BASE_UPPER 0x400000a
+#define ixD2F3_PREF_LIMIT_UPPER 0x400000b
+#define ixD2F3_IO_BASE_LIMIT_HI 0x400000c
+#define ixD2F3_IRQ_BRIDGE_CNTL 0x400000f
+#define ixD2F3_CAP_PTR 0x400000d
+#define ixD2F3_INTERRUPT_LINE 0x400000f
+#define ixD2F3_INTERRUPT_PIN 0x400000f
+#define ixD2F3_EXT_BRIDGE_CNTL 0x4000010
+#define ixD2F3_PMI_CAP_LIST 0x4000014
+#define ixD2F3_PMI_CAP 0x4000014
+#define ixD2F3_PMI_STATUS_CNTL 0x4000015
+#define ixD2F3_PCIE_CAP_LIST 0x4000016
+#define ixD2F3_PCIE_CAP 0x4000016
+#define ixD2F3_DEVICE_CAP 0x4000017
+#define ixD2F3_DEVICE_CNTL 0x4000018
+#define ixD2F3_DEVICE_STATUS 0x4000018
+#define ixD2F3_LINK_CAP 0x4000019
+#define ixD2F3_LINK_CNTL 0x400001a
+#define ixD2F3_LINK_STATUS 0x400001a
+#define ixD2F3_SLOT_CAP 0x400001b
+#define ixD2F3_SLOT_CNTL 0x400001c
+#define ixD2F3_SLOT_STATUS 0x400001c
+#define ixD2F3_ROOT_CNTL 0x400001d
+#define ixD2F3_ROOT_CAP 0x400001d
+#define ixD2F3_ROOT_STATUS 0x400001e
+#define ixD2F3_DEVICE_CAP2 0x400001f
+#define ixD2F3_DEVICE_CNTL2 0x4000020
+#define ixD2F3_DEVICE_STATUS2 0x4000020
+#define ixD2F3_LINK_CAP2 0x4000021
+#define ixD2F3_LINK_CNTL2 0x4000022
+#define ixD2F3_LINK_STATUS2 0x4000022
+#define ixD2F3_SLOT_CAP2 0x4000023
+#define ixD2F3_SLOT_CNTL2 0x4000024
+#define ixD2F3_SLOT_STATUS2 0x4000024
+#define ixD2F3_MSI_CAP_LIST 0x4000028
+#define ixD2F3_MSI_MSG_CNTL 0x4000028
+#define ixD2F3_MSI_MSG_ADDR_LO 0x4000029
+#define ixD2F3_MSI_MSG_ADDR_HI 0x400002a
+#define ixD2F3_MSI_MSG_DATA_64 0x400002b
+#define ixD2F3_MSI_MSG_DATA 0x400002a
+#define ixD2F3_SSID_CAP_LIST 0x4000030
+#define ixD2F3_SSID_CAP 0x4000031
+#define ixD2F3_MSI_MAP_CAP_LIST 0x4000032
+#define ixD2F3_MSI_MAP_CAP 0x4000032
+#define ixD2F3_MSI_MAP_ADDR_LO 0x4000033
+#define ixD2F3_MSI_MAP_ADDR_HI 0x4000034
+#define ixD2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x4000040
+#define ixD2F3_PCIE_VENDOR_SPECIFIC_HDR 0x4000041
+#define ixD2F3_PCIE_VENDOR_SPECIFIC1 0x4000042
+#define ixD2F3_PCIE_VENDOR_SPECIFIC2 0x4000043
+#define ixD2F3_PCIE_VC_ENH_CAP_LIST 0x4000044
+#define ixD2F3_PCIE_PORT_VC_CAP_REG1 0x4000045
+#define ixD2F3_PCIE_PORT_VC_CAP_REG2 0x4000046
+#define ixD2F3_PCIE_PORT_VC_CNTL 0x4000047
+#define ixD2F3_PCIE_PORT_VC_STATUS 0x4000047
+#define ixD2F3_PCIE_VC0_RESOURCE_CAP 0x4000048
+#define ixD2F3_PCIE_VC0_RESOURCE_CNTL 0x4000049
+#define ixD2F3_PCIE_VC0_RESOURCE_STATUS 0x400004a
+#define ixD2F3_PCIE_VC1_RESOURCE_CAP 0x400004b
+#define ixD2F3_PCIE_VC1_RESOURCE_CNTL 0x400004c
+#define ixD2F3_PCIE_VC1_RESOURCE_STATUS 0x400004d
+#define ixD2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x4000050
+#define ixD2F3_PCIE_DEV_SERIAL_NUM_DW1 0x4000051
+#define ixD2F3_PCIE_DEV_SERIAL_NUM_DW2 0x4000052
+#define ixD2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x4000054
+#define ixD2F3_PCIE_UNCORR_ERR_STATUS 0x4000055
+#define ixD2F3_PCIE_UNCORR_ERR_MASK 0x4000056
+#define ixD2F3_PCIE_UNCORR_ERR_SEVERITY 0x4000057
+#define ixD2F3_PCIE_CORR_ERR_STATUS 0x4000058
+#define ixD2F3_PCIE_CORR_ERR_MASK 0x4000059
+#define ixD2F3_PCIE_ADV_ERR_CAP_CNTL 0x400005a
+#define ixD2F3_PCIE_HDR_LOG0 0x400005b
+#define ixD2F3_PCIE_HDR_LOG1 0x400005c
+#define ixD2F3_PCIE_HDR_LOG2 0x400005d
+#define ixD2F3_PCIE_HDR_LOG3 0x400005e
+#define ixD2F3_PCIE_ROOT_ERR_CMD 0x400005f
+#define ixD2F3_PCIE_ROOT_ERR_STATUS 0x4000060
+#define ixD2F3_PCIE_ERR_SRC_ID 0x4000061
+#define ixD2F3_PCIE_TLP_PREFIX_LOG0 0x4000062
+#define ixD2F3_PCIE_TLP_PREFIX_LOG1 0x4000063
+#define ixD2F3_PCIE_TLP_PREFIX_LOG2 0x4000064
+#define ixD2F3_PCIE_TLP_PREFIX_LOG3 0x4000065
+#define ixD2F3_PCIE_SECONDARY_ENH_CAP_LIST 0x400009c
+#define ixD2F3_PCIE_LINK_CNTL3 0x400009d
+#define ixD2F3_PCIE_LANE_ERROR_STATUS 0x400009e
+#define ixD2F3_PCIE_LANE_0_EQUALIZATION_CNTL 0x400009f
+#define ixD2F3_PCIE_LANE_1_EQUALIZATION_CNTL 0x400009f
+#define ixD2F3_PCIE_LANE_2_EQUALIZATION_CNTL 0x40000a0
+#define ixD2F3_PCIE_LANE_3_EQUALIZATION_CNTL 0x40000a0
+#define ixD2F3_PCIE_LANE_4_EQUALIZATION_CNTL 0x40000a1
+#define ixD2F3_PCIE_LANE_5_EQUALIZATION_CNTL 0x40000a1
+#define ixD2F3_PCIE_LANE_6_EQUALIZATION_CNTL 0x40000a2
+#define ixD2F3_PCIE_LANE_7_EQUALIZATION_CNTL 0x40000a2
+#define ixD2F3_PCIE_LANE_8_EQUALIZATION_CNTL 0x40000a3
+#define ixD2F3_PCIE_LANE_9_EQUALIZATION_CNTL 0x40000a3
+#define ixD2F3_PCIE_LANE_10_EQUALIZATION_CNTL 0x40000a4
+#define ixD2F3_PCIE_LANE_11_EQUALIZATION_CNTL 0x40000a4
+#define ixD2F3_PCIE_LANE_12_EQUALIZATION_CNTL 0x40000a5
+#define ixD2F3_PCIE_LANE_13_EQUALIZATION_CNTL 0x40000a5
+#define ixD2F3_PCIE_LANE_14_EQUALIZATION_CNTL 0x40000a6
+#define ixD2F3_PCIE_LANE_15_EQUALIZATION_CNTL 0x40000a6
+#define ixD2F3_PCIE_ACS_ENH_CAP_LIST 0x40000a8
+#define ixD2F3_PCIE_ACS_CAP 0x40000a9
+#define ixD2F3_PCIE_ACS_CNTL 0x40000a9
+#define ixD2F3_PCIE_MC_ENH_CAP_LIST 0x40000bc
+#define ixD2F3_PCIE_MC_CAP 0x40000bd
+#define ixD2F3_PCIE_MC_CNTL 0x40000bd
+#define ixD2F3_PCIE_MC_ADDR0 0x40000be
+#define ixD2F3_PCIE_MC_ADDR1 0x40000bf
+#define ixD2F3_PCIE_MC_RCV0 0x40000c0
+#define ixD2F3_PCIE_MC_RCV1 0x40000c1
+#define ixD2F3_PCIE_MC_BLOCK_ALL0 0x40000c2
+#define ixD2F3_PCIE_MC_BLOCK_ALL1 0x40000c3
+#define ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_0 0x40000c4
+#define ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_1 0x40000c5
+#define ixD2F3_PCIE_MC_OVERLAY_BAR0 0x40000c6
+#define ixD2F3_PCIE_MC_OVERLAY_BAR1 0x40000c7
+#define ixD2F4_PCIE_PORT_INDEX 0x5000038
+#define ixD2F4_PCIE_PORT_DATA 0x5000039
+#define ixD2F4_PCIEP_RESERVED 0x0
+#define ixD2F4_PCIEP_SCRATCH 0x1
+#define ixD2F4_PCIEP_HW_DEBUG 0x2
+#define ixD2F4_PCIEP_PORT_CNTL 0x10
+#define ixD2F4_PCIE_TX_CNTL 0x20
+#define ixD2F4_PCIE_TX_REQUESTER_ID 0x21
+#define ixD2F4_PCIE_TX_VENDOR_SPECIFIC 0x22
+#define ixD2F4_PCIE_TX_REQUEST_NUM_CNTL 0x23
+#define ixD2F4_PCIE_TX_SEQ 0x24
+#define ixD2F4_PCIE_TX_REPLAY 0x25
+#define ixD2F4_PCIE_TX_ACK_LATENCY_LIMIT 0x26
+#define ixD2F4_PCIE_TX_CREDITS_ADVT_P 0x30
+#define ixD2F4_PCIE_TX_CREDITS_ADVT_NP 0x31
+#define ixD2F4_PCIE_TX_CREDITS_ADVT_CPL 0x32
+#define ixD2F4_PCIE_TX_CREDITS_INIT_P 0x33
+#define ixD2F4_PCIE_TX_CREDITS_INIT_NP 0x34
+#define ixD2F4_PCIE_TX_CREDITS_INIT_CPL 0x35
+#define ixD2F4_PCIE_TX_CREDITS_STATUS 0x36
+#define ixD2F4_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37
+#define ixD2F4_PCIE_P_PORT_LANE_STATUS 0x50
+#define ixD2F4_PCIE_FC_P 0x60
+#define ixD2F4_PCIE_FC_NP 0x61
+#define ixD2F4_PCIE_FC_CPL 0x62
+#define ixD2F4_PCIE_ERR_CNTL 0x6a
+#define ixD2F4_PCIE_RX_CNTL 0x70
+#define ixD2F4_PCIE_RX_EXPECTED_SEQNUM 0x71
+#define ixD2F4_PCIE_RX_VENDOR_SPECIFIC 0x72
+#define ixD2F4_PCIE_RX_CNTL3 0x74
+#define ixD2F4_PCIE_RX_CREDITS_ALLOCATED_P 0x80
+#define ixD2F4_PCIE_RX_CREDITS_ALLOCATED_NP 0x81
+#define ixD2F4_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82
+#define ixD2F4_PCIEP_ERROR_INJECT_PHYSICAL 0x83
+#define ixD2F4_PCIEP_ERROR_INJECT_TRANSACTION 0x84
+#define ixD2F4_PCIE_LC_CNTL 0xa0
+#define ixD2F4_PCIE_LC_CNTL2 0xb1
+#define ixD2F4_PCIE_LC_CNTL3 0xb5
+#define ixD2F4_PCIE_LC_CNTL4 0xb6
+#define ixD2F4_PCIE_LC_CNTL5 0xb7
+#define ixD2F4_PCIE_LC_CNTL6 0xbb
+#define ixD2F4_PCIE_LC_BW_CHANGE_CNTL 0xb2
+#define ixD2F4_PCIE_LC_TRAINING_CNTL 0xa1
+#define ixD2F4_PCIE_LC_LINK_WIDTH_CNTL 0xa2
+#define ixD2F4_PCIE_LC_N_FTS_CNTL 0xa3
+#define ixD2F4_PCIE_LC_SPEED_CNTL 0xa4
+#define ixD2F4_PCIE_LC_CDR_CNTL 0xb3
+#define ixD2F4_PCIE_LC_LANE_CNTL 0xb4
+#define ixD2F4_PCIE_LC_FORCE_COEFF 0xb8
+#define ixD2F4_PCIE_LC_BEST_EQ_SETTINGS 0xb9
+#define ixD2F4_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba
+#define ixD2F4_PCIE_LC_STATE0 0xa5
+#define ixD2F4_PCIE_LC_STATE1 0xa6
+#define ixD2F4_PCIE_LC_STATE2 0xa7
+#define ixD2F4_PCIE_LC_STATE3 0xa8
+#define ixD2F4_PCIE_LC_STATE4 0xa9
+#define ixD2F4_PCIE_LC_STATE5 0xaa
+#define ixD2F4_PCIEP_STRAP_LC 0xc0
+#define ixD2F4_PCIEP_STRAP_MISC 0xc1
+#define ixD2F4_PCIEP_BCH_ECC_CNTL 0xd0
+#define ixD2F4_PCIEP_HPGI_PRIVATE 0xd2
+#define ixD2F4_PCIEP_HPGI 0xda
+#define ixD2F4_VENDOR_ID 0x5000000
+#define ixD2F4_DEVICE_ID 0x5000000
+#define ixD2F4_COMMAND 0x5000001
+#define ixD2F4_STATUS 0x5000001
+#define ixD2F4_REVISION_ID 0x5000002
+#define ixD2F4_PROG_INTERFACE 0x5000002
+#define ixD2F4_SUB_CLASS 0x5000002
+#define ixD2F4_BASE_CLASS 0x5000002
+#define ixD2F4_CACHE_LINE 0x5000003
+#define ixD2F4_LATENCY 0x5000003
+#define ixD2F4_HEADER 0x5000003
+#define ixD2F4_BIST 0x5000003
+#define ixD2F4_SUB_BUS_NUMBER_LATENCY 0x5000006
+#define ixD2F4_IO_BASE_LIMIT 0x5000007
+#define ixD2F4_SECONDARY_STATUS 0x5000007
+#define ixD2F4_MEM_BASE_LIMIT 0x5000008
+#define ixD2F4_PREF_BASE_LIMIT 0x5000009
+#define ixD2F4_PREF_BASE_UPPER 0x500000a
+#define ixD2F4_PREF_LIMIT_UPPER 0x500000b
+#define ixD2F4_IO_BASE_LIMIT_HI 0x500000c
+#define ixD2F4_IRQ_BRIDGE_CNTL 0x500000f
+#define ixD2F4_CAP_PTR 0x500000d
+#define ixD2F4_INTERRUPT_LINE 0x500000f
+#define ixD2F4_INTERRUPT_PIN 0x500000f
+#define ixD2F4_EXT_BRIDGE_CNTL 0x5000010
+#define ixD2F4_PMI_CAP_LIST 0x5000014
+#define ixD2F4_PMI_CAP 0x5000014
+#define ixD2F4_PMI_STATUS_CNTL 0x5000015
+#define ixD2F4_PCIE_CAP_LIST 0x5000016
+#define ixD2F4_PCIE_CAP 0x5000016
+#define ixD2F4_DEVICE_CAP 0x5000017
+#define ixD2F4_DEVICE_CNTL 0x5000018
+#define ixD2F4_DEVICE_STATUS 0x5000018
+#define ixD2F4_LINK_CAP 0x5000019
+#define ixD2F4_LINK_CNTL 0x500001a
+#define ixD2F4_LINK_STATUS 0x500001a
+#define ixD2F4_SLOT_CAP 0x500001b
+#define ixD2F4_SLOT_CNTL 0x500001c
+#define ixD2F4_SLOT_STATUS 0x500001c
+#define ixD2F4_ROOT_CNTL 0x500001d
+#define ixD2F4_ROOT_CAP 0x500001d
+#define ixD2F4_ROOT_STATUS 0x500001e
+#define ixD2F4_DEVICE_CAP2 0x500001f
+#define ixD2F4_DEVICE_CNTL2 0x5000020
+#define ixD2F4_DEVICE_STATUS2 0x5000020
+#define ixD2F4_LINK_CAP2 0x5000021
+#define ixD2F4_LINK_CNTL2 0x5000022
+#define ixD2F4_LINK_STATUS2 0x5000022
+#define ixD2F4_SLOT_CAP2 0x5000023
+#define ixD2F4_SLOT_CNTL2 0x5000024
+#define ixD2F4_SLOT_STATUS2 0x5000024
+#define ixD2F4_MSI_CAP_LIST 0x5000028
+#define ixD2F4_MSI_MSG_CNTL 0x5000028
+#define ixD2F4_MSI_MSG_ADDR_LO 0x5000029
+#define ixD2F4_MSI_MSG_ADDR_HI 0x500002a
+#define ixD2F4_MSI_MSG_DATA_64 0x500002b
+#define ixD2F4_MSI_MSG_DATA 0x500002a
+#define ixD2F4_SSID_CAP_LIST 0x5000030
+#define ixD2F4_SSID_CAP 0x5000031
+#define ixD2F4_MSI_MAP_CAP_LIST 0x5000032
+#define ixD2F4_MSI_MAP_CAP 0x5000032
+#define ixD2F4_MSI_MAP_ADDR_LO 0x5000033
+#define ixD2F4_MSI_MAP_ADDR_HI 0x5000034
+#define ixD2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x5000040
+#define ixD2F4_PCIE_VENDOR_SPECIFIC_HDR 0x5000041
+#define ixD2F4_PCIE_VENDOR_SPECIFIC1 0x5000042
+#define ixD2F4_PCIE_VENDOR_SPECIFIC2 0x5000043
+#define ixD2F4_PCIE_VC_ENH_CAP_LIST 0x5000044
+#define ixD2F4_PCIE_PORT_VC_CAP_REG1 0x5000045
+#define ixD2F4_PCIE_PORT_VC_CAP_REG2 0x5000046
+#define ixD2F4_PCIE_PORT_VC_CNTL 0x5000047
+#define ixD2F4_PCIE_PORT_VC_STATUS 0x5000047
+#define ixD2F4_PCIE_VC0_RESOURCE_CAP 0x5000048
+#define ixD2F4_PCIE_VC0_RESOURCE_CNTL 0x5000049
+#define ixD2F4_PCIE_VC0_RESOURCE_STATUS 0x500004a
+#define ixD2F4_PCIE_VC1_RESOURCE_CAP 0x500004b
+#define ixD2F4_PCIE_VC1_RESOURCE_CNTL 0x500004c
+#define ixD2F4_PCIE_VC1_RESOURCE_STATUS 0x500004d
+#define ixD2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x5000050
+#define ixD2F4_PCIE_DEV_SERIAL_NUM_DW1 0x5000051
+#define ixD2F4_PCIE_DEV_SERIAL_NUM_DW2 0x5000052
+#define ixD2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x5000054
+#define ixD2F4_PCIE_UNCORR_ERR_STATUS 0x5000055
+#define ixD2F4_PCIE_UNCORR_ERR_MASK 0x5000056
+#define ixD2F4_PCIE_UNCORR_ERR_SEVERITY 0x5000057
+#define ixD2F4_PCIE_CORR_ERR_STATUS 0x5000058
+#define ixD2F4_PCIE_CORR_ERR_MASK 0x5000059
+#define ixD2F4_PCIE_ADV_ERR_CAP_CNTL 0x500005a
+#define ixD2F4_PCIE_HDR_LOG0 0x500005b
+#define ixD2F4_PCIE_HDR_LOG1 0x500005c
+#define ixD2F4_PCIE_HDR_LOG2 0x500005d
+#define ixD2F4_PCIE_HDR_LOG3 0x500005e
+#define ixD2F4_PCIE_ROOT_ERR_CMD 0x500005f
+#define ixD2F4_PCIE_ROOT_ERR_STATUS 0x5000060
+#define ixD2F4_PCIE_ERR_SRC_ID 0x5000061
+#define ixD2F4_PCIE_TLP_PREFIX_LOG0 0x5000062
+#define ixD2F4_PCIE_TLP_PREFIX_LOG1 0x5000063
+#define ixD2F4_PCIE_TLP_PREFIX_LOG2 0x5000064
+#define ixD2F4_PCIE_TLP_PREFIX_LOG3 0x5000065
+#define ixD2F4_PCIE_SECONDARY_ENH_CAP_LIST 0x500009c
+#define ixD2F4_PCIE_LINK_CNTL3 0x500009d
+#define ixD2F4_PCIE_LANE_ERROR_STATUS 0x500009e
+#define ixD2F4_PCIE_LANE_0_EQUALIZATION_CNTL 0x500009f
+#define ixD2F4_PCIE_LANE_1_EQUALIZATION_CNTL 0x500009f
+#define ixD2F4_PCIE_LANE_2_EQUALIZATION_CNTL 0x50000a0
+#define ixD2F4_PCIE_LANE_3_EQUALIZATION_CNTL 0x50000a0
+#define ixD2F4_PCIE_LANE_4_EQUALIZATION_CNTL 0x50000a1
+#define ixD2F4_PCIE_LANE_5_EQUALIZATION_CNTL 0x50000a1
+#define ixD2F4_PCIE_LANE_6_EQUALIZATION_CNTL 0x50000a2
+#define ixD2F4_PCIE_LANE_7_EQUALIZATION_CNTL 0x50000a2
+#define ixD2F4_PCIE_LANE_8_EQUALIZATION_CNTL 0x50000a3
+#define ixD2F4_PCIE_LANE_9_EQUALIZATION_CNTL 0x50000a3
+#define ixD2F4_PCIE_LANE_10_EQUALIZATION_CNTL 0x50000a4
+#define ixD2F4_PCIE_LANE_11_EQUALIZATION_CNTL 0x50000a4
+#define ixD2F4_PCIE_LANE_12_EQUALIZATION_CNTL 0x50000a5
+#define ixD2F4_PCIE_LANE_13_EQUALIZATION_CNTL 0x50000a5
+#define ixD2F4_PCIE_LANE_14_EQUALIZATION_CNTL 0x50000a6
+#define ixD2F4_PCIE_LANE_15_EQUALIZATION_CNTL 0x50000a6
+#define ixD2F4_PCIE_ACS_ENH_CAP_LIST 0x50000a8
+#define ixD2F4_PCIE_ACS_CAP 0x50000a9
+#define ixD2F4_PCIE_ACS_CNTL 0x50000a9
+#define ixD2F4_PCIE_MC_ENH_CAP_LIST 0x50000bc
+#define ixD2F4_PCIE_MC_CAP 0x50000bd
+#define ixD2F4_PCIE_MC_CNTL 0x50000bd
+#define ixD2F4_PCIE_MC_ADDR0 0x50000be
+#define ixD2F4_PCIE_MC_ADDR1 0x50000bf
+#define ixD2F4_PCIE_MC_RCV0 0x50000c0
+#define ixD2F4_PCIE_MC_RCV1 0x50000c1
+#define ixD2F4_PCIE_MC_BLOCK_ALL0 0x50000c2
+#define ixD2F4_PCIE_MC_BLOCK_ALL1 0x50000c3
+#define ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_0 0x50000c4
+#define ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_1 0x50000c5
+#define ixD2F4_PCIE_MC_OVERLAY_BAR0 0x50000c6
+#define ixD2F4_PCIE_MC_OVERLAY_BAR1 0x50000c7
+#define ixD2F5_PCIE_PORT_INDEX 0x6000038
+#define ixD2F5_PCIE_PORT_DATA 0x6000039
+#define ixD2F5_PCIEP_RESERVED 0x0
+#define ixD2F5_PCIEP_SCRATCH 0x1
+#define ixD2F5_PCIEP_HW_DEBUG 0x2
+#define ixD2F5_PCIEP_PORT_CNTL 0x10
+#define ixD2F5_PCIE_TX_CNTL 0x20
+#define ixD2F5_PCIE_TX_REQUESTER_ID 0x21
+#define ixD2F5_PCIE_TX_VENDOR_SPECIFIC 0x22
+#define ixD2F5_PCIE_TX_REQUEST_NUM_CNTL 0x23
+#define ixD2F5_PCIE_TX_SEQ 0x24
+#define ixD2F5_PCIE_TX_REPLAY 0x25
+#define ixD2F5_PCIE_TX_ACK_LATENCY_LIMIT 0x26
+#define ixD2F5_PCIE_TX_CREDITS_ADVT_P 0x30
+#define ixD2F5_PCIE_TX_CREDITS_ADVT_NP 0x31
+#define ixD2F5_PCIE_TX_CREDITS_ADVT_CPL 0x32
+#define ixD2F5_PCIE_TX_CREDITS_INIT_P 0x33
+#define ixD2F5_PCIE_TX_CREDITS_INIT_NP 0x34
+#define ixD2F5_PCIE_TX_CREDITS_INIT_CPL 0x35
+#define ixD2F5_PCIE_TX_CREDITS_STATUS 0x36
+#define ixD2F5_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37
+#define ixD2F5_PCIE_P_PORT_LANE_STATUS 0x50
+#define ixD2F5_PCIE_FC_P 0x60
+#define ixD2F5_PCIE_FC_NP 0x61
+#define ixD2F5_PCIE_FC_CPL 0x62
+#define ixD2F5_PCIE_ERR_CNTL 0x6a
+#define ixD2F5_PCIE_RX_CNTL 0x70
+#define ixD2F5_PCIE_RX_EXPECTED_SEQNUM 0x71
+#define ixD2F5_PCIE_RX_VENDOR_SPECIFIC 0x72
+#define ixD2F5_PCIE_RX_CNTL3 0x74
+#define ixD2F5_PCIE_RX_CREDITS_ALLOCATED_P 0x80
+#define ixD2F5_PCIE_RX_CREDITS_ALLOCATED_NP 0x81
+#define ixD2F5_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82
+#define ixD2F5_PCIEP_ERROR_INJECT_PHYSICAL 0x83
+#define ixD2F5_PCIEP_ERROR_INJECT_TRANSACTION 0x84
+#define ixD2F5_PCIE_LC_CNTL 0xa0
+#define ixD2F5_PCIE_LC_CNTL2 0xb1
+#define ixD2F5_PCIE_LC_CNTL3 0xb5
+#define ixD2F5_PCIE_LC_CNTL4 0xb6
+#define ixD2F5_PCIE_LC_CNTL5 0xb7
+#define ixD2F5_PCIE_LC_CNTL6 0xbb
+#define ixD2F5_PCIE_LC_BW_CHANGE_CNTL 0xb2
+#define ixD2F5_PCIE_LC_TRAINING_CNTL 0xa1
+#define ixD2F5_PCIE_LC_LINK_WIDTH_CNTL 0xa2
+#define ixD2F5_PCIE_LC_N_FTS_CNTL 0xa3
+#define ixD2F5_PCIE_LC_SPEED_CNTL 0xa4
+#define ixD2F5_PCIE_LC_CDR_CNTL 0xb3
+#define ixD2F5_PCIE_LC_LANE_CNTL 0xb4
+#define ixD2F5_PCIE_LC_FORCE_COEFF 0xb8
+#define ixD2F5_PCIE_LC_BEST_EQ_SETTINGS 0xb9
+#define ixD2F5_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba
+#define ixD2F5_PCIE_LC_STATE0 0xa5
+#define ixD2F5_PCIE_LC_STATE1 0xa6
+#define ixD2F5_PCIE_LC_STATE2 0xa7
+#define ixD2F5_PCIE_LC_STATE3 0xa8
+#define ixD2F5_PCIE_LC_STATE4 0xa9
+#define ixD2F5_PCIE_LC_STATE5 0xaa
+#define ixD2F5_PCIEP_STRAP_LC 0xc0
+#define ixD2F5_PCIEP_STRAP_MISC 0xc1
+#define ixD2F5_PCIEP_BCH_ECC_CNTL 0xd0
+#define ixD2F5_PCIEP_HPGI_PRIVATE 0xd2
+#define ixD2F5_PCIEP_HPGI 0xda
+#define ixD2F5_VENDOR_ID 0x6000000
+#define ixD2F5_DEVICE_ID 0x6000000
+#define ixD2F5_COMMAND 0x6000001
+#define ixD2F5_STATUS 0x6000001
+#define ixD2F5_REVISION_ID 0x6000002
+#define ixD2F5_PROG_INTERFACE 0x6000002
+#define ixD2F5_SUB_CLASS 0x6000002
+#define ixD2F5_BASE_CLASS 0x6000002
+#define ixD2F5_CACHE_LINE 0x6000003
+#define ixD2F5_LATENCY 0x6000003
+#define ixD2F5_HEADER 0x6000003
+#define ixD2F5_BIST 0x6000003
+#define ixD2F5_SUB_BUS_NUMBER_LATENCY 0x6000006
+#define ixD2F5_IO_BASE_LIMIT 0x6000007
+#define ixD2F5_SECONDARY_STATUS 0x6000007
+#define ixD2F5_MEM_BASE_LIMIT 0x6000008
+#define ixD2F5_PREF_BASE_LIMIT 0x6000009
+#define ixD2F5_PREF_BASE_UPPER 0x600000a
+#define ixD2F5_PREF_LIMIT_UPPER 0x600000b
+#define ixD2F5_IO_BASE_LIMIT_HI 0x600000c
+#define ixD2F5_IRQ_BRIDGE_CNTL 0x600000f
+#define ixD2F5_CAP_PTR 0x600000d
+#define ixD2F5_INTERRUPT_LINE 0x600000f
+#define ixD2F5_INTERRUPT_PIN 0x600000f
+#define ixD2F5_EXT_BRIDGE_CNTL 0x6000010
+#define ixD2F5_PMI_CAP_LIST 0x6000014
+#define ixD2F5_PMI_CAP 0x6000014
+#define ixD2F5_PMI_STATUS_CNTL 0x6000015
+#define ixD2F5_PCIE_CAP_LIST 0x6000016
+#define ixD2F5_PCIE_CAP 0x6000016
+#define ixD2F5_DEVICE_CAP 0x6000017
+#define ixD2F5_DEVICE_CNTL 0x6000018
+#define ixD2F5_DEVICE_STATUS 0x6000018
+#define ixD2F5_LINK_CAP 0x6000019
+#define ixD2F5_LINK_CNTL 0x600001a
+#define ixD2F5_LINK_STATUS 0x600001a
+#define ixD2F5_SLOT_CAP 0x600001b
+#define ixD2F5_SLOT_CNTL 0x600001c
+#define ixD2F5_SLOT_STATUS 0x600001c
+#define ixD2F5_ROOT_CNTL 0x600001d
+#define ixD2F5_ROOT_CAP 0x600001d
+#define ixD2F5_ROOT_STATUS 0x600001e
+#define ixD2F5_DEVICE_CAP2 0x600001f
+#define ixD2F5_DEVICE_CNTL2 0x6000020
+#define ixD2F5_DEVICE_STATUS2 0x6000020
+#define ixD2F5_LINK_CAP2 0x6000021
+#define ixD2F5_LINK_CNTL2 0x6000022
+#define ixD2F5_LINK_STATUS2 0x6000022
+#define ixD2F5_SLOT_CAP2 0x6000023
+#define ixD2F5_SLOT_CNTL2 0x6000024
+#define ixD2F5_SLOT_STATUS2 0x6000024
+#define ixD2F5_MSI_CAP_LIST 0x6000028
+#define ixD2F5_MSI_MSG_CNTL 0x6000028
+#define ixD2F5_MSI_MSG_ADDR_LO 0x6000029
+#define ixD2F5_MSI_MSG_ADDR_HI 0x600002a
+#define ixD2F5_MSI_MSG_DATA_64 0x600002b
+#define ixD2F5_MSI_MSG_DATA 0x600002a
+#define ixD2F5_SSID_CAP_LIST 0x6000030
+#define ixD2F5_SSID_CAP 0x6000031
+#define ixD2F5_MSI_MAP_CAP_LIST 0x6000032
+#define ixD2F5_MSI_MAP_CAP 0x6000032
+#define ixD2F5_MSI_MAP_ADDR_LO 0x6000033
+#define ixD2F5_MSI_MAP_ADDR_HI 0x6000034
+#define ixD2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x6000040
+#define ixD2F5_PCIE_VENDOR_SPECIFIC_HDR 0x6000041
+#define ixD2F5_PCIE_VENDOR_SPECIFIC1 0x6000042
+#define ixD2F5_PCIE_VENDOR_SPECIFIC2 0x6000043
+#define ixD2F5_PCIE_VC_ENH_CAP_LIST 0x6000044
+#define ixD2F5_PCIE_PORT_VC_CAP_REG1 0x6000045
+#define ixD2F5_PCIE_PORT_VC_CAP_REG2 0x6000046
+#define ixD2F5_PCIE_PORT_VC_CNTL 0x6000047
+#define ixD2F5_PCIE_PORT_VC_STATUS 0x6000047
+#define ixD2F5_PCIE_VC0_RESOURCE_CAP 0x6000048
+#define ixD2F5_PCIE_VC0_RESOURCE_CNTL 0x6000049
+#define ixD2F5_PCIE_VC0_RESOURCE_STATUS 0x600004a
+#define ixD2F5_PCIE_VC1_RESOURCE_CAP 0x600004b
+#define ixD2F5_PCIE_VC1_RESOURCE_CNTL 0x600004c
+#define ixD2F5_PCIE_VC1_RESOURCE_STATUS 0x600004d
+#define ixD2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x6000050
+#define ixD2F5_PCIE_DEV_SERIAL_NUM_DW1 0x6000051
+#define ixD2F5_PCIE_DEV_SERIAL_NUM_DW2 0x6000052
+#define ixD2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x6000054
+#define ixD2F5_PCIE_UNCORR_ERR_STATUS 0x6000055
+#define ixD2F5_PCIE_UNCORR_ERR_MASK 0x6000056
+#define ixD2F5_PCIE_UNCORR_ERR_SEVERITY 0x6000057
+#define ixD2F5_PCIE_CORR_ERR_STATUS 0x6000058
+#define ixD2F5_PCIE_CORR_ERR_MASK 0x6000059
+#define ixD2F5_PCIE_ADV_ERR_CAP_CNTL 0x600005a
+#define ixD2F5_PCIE_HDR_LOG0 0x600005b
+#define ixD2F5_PCIE_HDR_LOG1 0x600005c
+#define ixD2F5_PCIE_HDR_LOG2 0x600005d
+#define ixD2F5_PCIE_HDR_LOG3 0x600005e
+#define ixD2F5_PCIE_ROOT_ERR_CMD 0x600005f
+#define ixD2F5_PCIE_ROOT_ERR_STATUS 0x6000060
+#define ixD2F5_PCIE_ERR_SRC_ID 0x6000061
+#define ixD2F5_PCIE_TLP_PREFIX_LOG0 0x6000062
+#define ixD2F5_PCIE_TLP_PREFIX_LOG1 0x6000063
+#define ixD2F5_PCIE_TLP_PREFIX_LOG2 0x6000064
+#define ixD2F5_PCIE_TLP_PREFIX_LOG3 0x6000065
+#define ixD2F5_PCIE_SECONDARY_ENH_CAP_LIST 0x600009c
+#define ixD2F5_PCIE_LINK_CNTL3 0x600009d
+#define ixD2F5_PCIE_LANE_ERROR_STATUS 0x600009e
+#define ixD2F5_PCIE_LANE_0_EQUALIZATION_CNTL 0x600009f
+#define ixD2F5_PCIE_LANE_1_EQUALIZATION_CNTL 0x600009f
+#define ixD2F5_PCIE_LANE_2_EQUALIZATION_CNTL 0x60000a0
+#define ixD2F5_PCIE_LANE_3_EQUALIZATION_CNTL 0x60000a0
+#define ixD2F5_PCIE_LANE_4_EQUALIZATION_CNTL 0x60000a1
+#define ixD2F5_PCIE_LANE_5_EQUALIZATION_CNTL 0x60000a1
+#define ixD2F5_PCIE_LANE_6_EQUALIZATION_CNTL 0x60000a2
+#define ixD2F5_PCIE_LANE_7_EQUALIZATION_CNTL 0x60000a2
+#define ixD2F5_PCIE_LANE_8_EQUALIZATION_CNTL 0x60000a3
+#define ixD2F5_PCIE_LANE_9_EQUALIZATION_CNTL 0x60000a3
+#define ixD2F5_PCIE_LANE_10_EQUALIZATION_CNTL 0x60000a4
+#define ixD2F5_PCIE_LANE_11_EQUALIZATION_CNTL 0x60000a4
+#define ixD2F5_PCIE_LANE_12_EQUALIZATION_CNTL 0x60000a5
+#define ixD2F5_PCIE_LANE_13_EQUALIZATION_CNTL 0x60000a5
+#define ixD2F5_PCIE_LANE_14_EQUALIZATION_CNTL 0x60000a6
+#define ixD2F5_PCIE_LANE_15_EQUALIZATION_CNTL 0x60000a6
+#define ixD2F5_PCIE_ACS_ENH_CAP_LIST 0x60000a8
+#define ixD2F5_PCIE_ACS_CAP 0x60000a9
+#define ixD2F5_PCIE_ACS_CNTL 0x60000a9
+#define ixD2F5_PCIE_MC_ENH_CAP_LIST 0x60000bc
+#define ixD2F5_PCIE_MC_CAP 0x60000bd
+#define ixD2F5_PCIE_MC_CNTL 0x60000bd
+#define ixD2F5_PCIE_MC_ADDR0 0x60000be
+#define ixD2F5_PCIE_MC_ADDR1 0x60000bf
+#define ixD2F5_PCIE_MC_RCV0 0x60000c0
+#define ixD2F5_PCIE_MC_RCV1 0x60000c1
+#define ixD2F5_PCIE_MC_BLOCK_ALL0 0x60000c2
+#define ixD2F5_PCIE_MC_BLOCK_ALL1 0x60000c3
+#define ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_0 0x60000c4
+#define ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_1 0x60000c5
+#define ixD2F5_PCIE_MC_OVERLAY_BAR0 0x60000c6
+#define ixD2F5_PCIE_MC_OVERLAY_BAR1 0x60000c7
+#define ixD3F1_PCIE_PORT_INDEX 0x7000038
+#define ixD3F1_PCIE_PORT_DATA 0x7000039
+#define ixD3F1_PCIEP_RESERVED 0x0
+#define ixD3F1_PCIEP_SCRATCH 0x1
+#define ixD3F1_PCIEP_HW_DEBUG 0x2
+#define ixD3F1_PCIEP_PORT_CNTL 0x10
+#define ixD3F1_PCIE_TX_CNTL 0x20
+#define ixD3F1_PCIE_TX_REQUESTER_ID 0x21
+#define ixD3F1_PCIE_TX_VENDOR_SPECIFIC 0x22
+#define ixD3F1_PCIE_TX_REQUEST_NUM_CNTL 0x23
+#define ixD3F1_PCIE_TX_SEQ 0x24
+#define ixD3F1_PCIE_TX_REPLAY 0x25
+#define ixD3F1_PCIE_TX_ACK_LATENCY_LIMIT 0x26
+#define ixD3F1_PCIE_TX_CREDITS_ADVT_P 0x30
+#define ixD3F1_PCIE_TX_CREDITS_ADVT_NP 0x31
+#define ixD3F1_PCIE_TX_CREDITS_ADVT_CPL 0x32
+#define ixD3F1_PCIE_TX_CREDITS_INIT_P 0x33
+#define ixD3F1_PCIE_TX_CREDITS_INIT_NP 0x34
+#define ixD3F1_PCIE_TX_CREDITS_INIT_CPL 0x35
+#define ixD3F1_PCIE_TX_CREDITS_STATUS 0x36
+#define ixD3F1_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37
+#define ixD3F1_PCIE_P_PORT_LANE_STATUS 0x50
+#define ixD3F1_PCIE_FC_P 0x60
+#define ixD3F1_PCIE_FC_NP 0x61
+#define ixD3F1_PCIE_FC_CPL 0x62
+#define ixD3F1_PCIE_ERR_CNTL 0x6a
+#define ixD3F1_PCIE_RX_CNTL 0x70
+#define ixD3F1_PCIE_RX_EXPECTED_SEQNUM 0x71
+#define ixD3F1_PCIE_RX_VENDOR_SPECIFIC 0x72
+#define ixD3F1_PCIE_RX_CNTL3 0x74
+#define ixD3F1_PCIE_RX_CREDITS_ALLOCATED_P 0x80
+#define ixD3F1_PCIE_RX_CREDITS_ALLOCATED_NP 0x81
+#define ixD3F1_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82
+#define ixD3F1_PCIEP_ERROR_INJECT_PHYSICAL 0x83
+#define ixD3F1_PCIEP_ERROR_INJECT_TRANSACTION 0x84
+#define ixD3F1_PCIE_LC_CNTL 0xa0
+#define ixD3F1_PCIE_LC_CNTL2 0xb1
+#define ixD3F1_PCIE_LC_CNTL3 0xb5
+#define ixD3F1_PCIE_LC_CNTL4 0xb6
+#define ixD3F1_PCIE_LC_CNTL5 0xb7
+#define ixD3F1_PCIE_LC_CNTL6 0xbb
+#define ixD3F1_PCIE_LC_BW_CHANGE_CNTL 0xb2
+#define ixD3F1_PCIE_LC_TRAINING_CNTL 0xa1
+#define ixD3F1_PCIE_LC_LINK_WIDTH_CNTL 0xa2
+#define ixD3F1_PCIE_LC_N_FTS_CNTL 0xa3
+#define ixD3F1_PCIE_LC_SPEED_CNTL 0xa4
+#define ixD3F1_PCIE_LC_CDR_CNTL 0xb3
+#define ixD3F1_PCIE_LC_LANE_CNTL 0xb4
+#define ixD3F1_PCIE_LC_FORCE_COEFF 0xb8
+#define ixD3F1_PCIE_LC_BEST_EQ_SETTINGS 0xb9
+#define ixD3F1_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba
+#define ixD3F1_PCIE_LC_STATE0 0xa5
+#define ixD3F1_PCIE_LC_STATE1 0xa6
+#define ixD3F1_PCIE_LC_STATE2 0xa7
+#define ixD3F1_PCIE_LC_STATE3 0xa8
+#define ixD3F1_PCIE_LC_STATE4 0xa9
+#define ixD3F1_PCIE_LC_STATE5 0xaa
+#define ixD3F1_PCIEP_STRAP_LC 0xc0
+#define ixD3F1_PCIEP_STRAP_MISC 0xc1
+#define ixD3F1_PCIEP_BCH_ECC_CNTL 0xd0
+#define ixD3F1_PCIEP_HPGI_PRIVATE 0xd2
+#define ixD3F1_PCIEP_HPGI 0xda
+#define ixD3F1_VENDOR_ID 0x7000000
+#define ixD3F1_DEVICE_ID 0x7000000
+#define ixD3F1_COMMAND 0x7000001
+#define ixD3F1_STATUS 0x7000001
+#define ixD3F1_REVISION_ID 0x7000002
+#define ixD3F1_PROG_INTERFACE 0x7000002
+#define ixD3F1_SUB_CLASS 0x7000002
+#define ixD3F1_BASE_CLASS 0x7000002
+#define ixD3F1_CACHE_LINE 0x7000003
+#define ixD3F1_LATENCY 0x7000003
+#define ixD3F1_HEADER 0x7000003
+#define ixD3F1_BIST 0x7000003
+#define ixD3F1_SUB_BUS_NUMBER_LATENCY 0x7000006
+#define ixD3F1_IO_BASE_LIMIT 0x7000007
+#define ixD3F1_SECONDARY_STATUS 0x7000007
+#define ixD3F1_MEM_BASE_LIMIT 0x7000008
+#define ixD3F1_PREF_BASE_LIMIT 0x7000009
+#define ixD3F1_PREF_BASE_UPPER 0x700000a
+#define ixD3F1_PREF_LIMIT_UPPER 0x700000b
+#define ixD3F1_IO_BASE_LIMIT_HI 0x700000c
+#define ixD3F1_IRQ_BRIDGE_CNTL 0x700000f
+#define ixD3F1_CAP_PTR 0x700000d
+#define ixD3F1_INTERRUPT_LINE 0x700000f
+#define ixD3F1_INTERRUPT_PIN 0x700000f
+#define ixD3F1_EXT_BRIDGE_CNTL 0x7000010
+#define ixD3F1_PMI_CAP_LIST 0x7000014
+#define ixD3F1_PMI_CAP 0x7000014
+#define ixD3F1_PMI_STATUS_CNTL 0x7000015
+#define ixD3F1_PCIE_CAP_LIST 0x7000016
+#define ixD3F1_PCIE_CAP 0x7000016
+#define ixD3F1_DEVICE_CAP 0x7000017
+#define ixD3F1_DEVICE_CNTL 0x7000018
+#define ixD3F1_DEVICE_STATUS 0x7000018
+#define ixD3F1_LINK_CAP 0x7000019
+#define ixD3F1_LINK_CNTL 0x700001a
+#define ixD3F1_LINK_STATUS 0x700001a
+#define ixD3F1_SLOT_CAP 0x700001b
+#define ixD3F1_SLOT_CNTL 0x700001c
+#define ixD3F1_SLOT_STATUS 0x700001c
+#define ixD3F1_ROOT_CNTL 0x700001d
+#define ixD3F1_ROOT_CAP 0x700001d
+#define ixD3F1_ROOT_STATUS 0x700001e
+#define ixD3F1_DEVICE_CAP2 0x700001f
+#define ixD3F1_DEVICE_CNTL2 0x7000020
+#define ixD3F1_DEVICE_STATUS2 0x7000020
+#define ixD3F1_LINK_CAP2 0x7000021
+#define ixD3F1_LINK_CNTL2 0x7000022
+#define ixD3F1_LINK_STATUS2 0x7000022
+#define ixD3F1_SLOT_CAP2 0x7000023
+#define ixD3F1_SLOT_CNTL2 0x7000024
+#define ixD3F1_SLOT_STATUS2 0x7000024
+#define ixD3F1_MSI_CAP_LIST 0x7000028
+#define ixD3F1_MSI_MSG_CNTL 0x7000028
+#define ixD3F1_MSI_MSG_ADDR_LO 0x7000029
+#define ixD3F1_MSI_MSG_ADDR_HI 0x700002a
+#define ixD3F1_MSI_MSG_DATA_64 0x700002b
+#define ixD3F1_MSI_MSG_DATA 0x700002a
+#define ixD3F1_SSID_CAP_LIST 0x7000030
+#define ixD3F1_SSID_CAP 0x7000031
+#define ixD3F1_MSI_MAP_CAP_LIST 0x7000032
+#define ixD3F1_MSI_MAP_CAP 0x7000032
+#define ixD3F1_MSI_MAP_ADDR_LO 0x7000033
+#define ixD3F1_MSI_MAP_ADDR_HI 0x7000034
+#define ixD3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x7000040
+#define ixD3F1_PCIE_VENDOR_SPECIFIC_HDR 0x7000041
+#define ixD3F1_PCIE_VENDOR_SPECIFIC1 0x7000042
+#define ixD3F1_PCIE_VENDOR_SPECIFIC2 0x7000043
+#define ixD3F1_PCIE_VC_ENH_CAP_LIST 0x7000044
+#define ixD3F1_PCIE_PORT_VC_CAP_REG1 0x7000045
+#define ixD3F1_PCIE_PORT_VC_CAP_REG2 0x7000046
+#define ixD3F1_PCIE_PORT_VC_CNTL 0x7000047
+#define ixD3F1_PCIE_PORT_VC_STATUS 0x7000047
+#define ixD3F1_PCIE_VC0_RESOURCE_CAP 0x7000048
+#define ixD3F1_PCIE_VC0_RESOURCE_CNTL 0x7000049
+#define ixD3F1_PCIE_VC0_RESOURCE_STATUS 0x700004a
+#define ixD3F1_PCIE_VC1_RESOURCE_CAP 0x700004b
+#define ixD3F1_PCIE_VC1_RESOURCE_CNTL 0x700004c
+#define ixD3F1_PCIE_VC1_RESOURCE_STATUS 0x700004d
+#define ixD3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x7000050
+#define ixD3F1_PCIE_DEV_SERIAL_NUM_DW1 0x7000051
+#define ixD3F1_PCIE_DEV_SERIAL_NUM_DW2 0x7000052
+#define ixD3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x7000054
+#define ixD3F1_PCIE_UNCORR_ERR_STATUS 0x7000055
+#define ixD3F1_PCIE_UNCORR_ERR_MASK 0x7000056
+#define ixD3F1_PCIE_UNCORR_ERR_SEVERITY 0x7000057
+#define ixD3F1_PCIE_CORR_ERR_STATUS 0x7000058
+#define ixD3F1_PCIE_CORR_ERR_MASK 0x7000059
+#define ixD3F1_PCIE_ADV_ERR_CAP_CNTL 0x700005a
+#define ixD3F1_PCIE_HDR_LOG0 0x700005b
+#define ixD3F1_PCIE_HDR_LOG1 0x700005c
+#define ixD3F1_PCIE_HDR_LOG2 0x700005d
+#define ixD3F1_PCIE_HDR_LOG3 0x700005e
+#define ixD3F1_PCIE_ROOT_ERR_CMD 0x700005f
+#define ixD3F1_PCIE_ROOT_ERR_STATUS 0x7000060
+#define ixD3F1_PCIE_ERR_SRC_ID 0x7000061
+#define ixD3F1_PCIE_TLP_PREFIX_LOG0 0x7000062
+#define ixD3F1_PCIE_TLP_PREFIX_LOG1 0x7000063
+#define ixD3F1_PCIE_TLP_PREFIX_LOG2 0x7000064
+#define ixD3F1_PCIE_TLP_PREFIX_LOG3 0x7000065
+#define ixD3F1_PCIE_SECONDARY_ENH_CAP_LIST 0x700009c
+#define ixD3F1_PCIE_LINK_CNTL3 0x700009d
+#define ixD3F1_PCIE_LANE_ERROR_STATUS 0x700009e
+#define ixD3F1_PCIE_LANE_0_EQUALIZATION_CNTL 0x700009f
+#define ixD3F1_PCIE_LANE_1_EQUALIZATION_CNTL 0x700009f
+#define ixD3F1_PCIE_LANE_2_EQUALIZATION_CNTL 0x70000a0
+#define ixD3F1_PCIE_LANE_3_EQUALIZATION_CNTL 0x70000a0
+#define ixD3F1_PCIE_LANE_4_EQUALIZATION_CNTL 0x70000a1
+#define ixD3F1_PCIE_LANE_5_EQUALIZATION_CNTL 0x70000a1
+#define ixD3F1_PCIE_LANE_6_EQUALIZATION_CNTL 0x70000a2
+#define ixD3F1_PCIE_LANE_7_EQUALIZATION_CNTL 0x70000a2
+#define ixD3F1_PCIE_LANE_8_EQUALIZATION_CNTL 0x70000a3
+#define ixD3F1_PCIE_LANE_9_EQUALIZATION_CNTL 0x70000a3
+#define ixD3F1_PCIE_LANE_10_EQUALIZATION_CNTL 0x70000a4
+#define ixD3F1_PCIE_LANE_11_EQUALIZATION_CNTL 0x70000a4
+#define ixD3F1_PCIE_LANE_12_EQUALIZATION_CNTL 0x70000a5
+#define ixD3F1_PCIE_LANE_13_EQUALIZATION_CNTL 0x70000a5
+#define ixD3F1_PCIE_LANE_14_EQUALIZATION_CNTL 0x70000a6
+#define ixD3F1_PCIE_LANE_15_EQUALIZATION_CNTL 0x70000a6
+#define ixD3F1_PCIE_ACS_ENH_CAP_LIST 0x70000a8
+#define ixD3F1_PCIE_ACS_CAP 0x70000a9
+#define ixD3F1_PCIE_ACS_CNTL 0x70000a9
+#define ixD3F1_PCIE_MC_ENH_CAP_LIST 0x70000bc
+#define ixD3F1_PCIE_MC_CAP 0x70000bd
+#define ixD3F1_PCIE_MC_CNTL 0x70000bd
+#define ixD3F1_PCIE_MC_ADDR0 0x70000be
+#define ixD3F1_PCIE_MC_ADDR1 0x70000bf
+#define ixD3F1_PCIE_MC_RCV0 0x70000c0
+#define ixD3F1_PCIE_MC_RCV1 0x70000c1
+#define ixD3F1_PCIE_MC_BLOCK_ALL0 0x70000c2
+#define ixD3F1_PCIE_MC_BLOCK_ALL1 0x70000c3
+#define ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x70000c4
+#define ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x70000c5
+#define ixD3F1_PCIE_MC_OVERLAY_BAR0 0x70000c6
+#define ixD3F1_PCIE_MC_OVERLAY_BAR1 0x70000c7
+#define ixD3F2_PCIE_PORT_INDEX 0x8000038
+#define ixD3F2_PCIE_PORT_DATA 0x8000039
+#define ixD3F2_PCIEP_RESERVED 0x0
+#define ixD3F2_PCIEP_SCRATCH 0x1
+#define ixD3F2_PCIEP_HW_DEBUG 0x2
+#define ixD3F2_PCIEP_PORT_CNTL 0x10
+#define ixD3F2_PCIE_TX_CNTL 0x20
+#define ixD3F2_PCIE_TX_REQUESTER_ID 0x21
+#define ixD3F2_PCIE_TX_VENDOR_SPECIFIC 0x22
+#define ixD3F2_PCIE_TX_REQUEST_NUM_CNTL 0x23
+#define ixD3F2_PCIE_TX_SEQ 0x24
+#define ixD3F2_PCIE_TX_REPLAY 0x25
+#define ixD3F2_PCIE_TX_ACK_LATENCY_LIMIT 0x26
+#define ixD3F2_PCIE_TX_CREDITS_ADVT_P 0x30
+#define ixD3F2_PCIE_TX_CREDITS_ADVT_NP 0x31
+#define ixD3F2_PCIE_TX_CREDITS_ADVT_CPL 0x32
+#define ixD3F2_PCIE_TX_CREDITS_INIT_P 0x33
+#define ixD3F2_PCIE_TX_CREDITS_INIT_NP 0x34
+#define ixD3F2_PCIE_TX_CREDITS_INIT_CPL 0x35
+#define ixD3F2_PCIE_TX_CREDITS_STATUS 0x36
+#define ixD3F2_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37
+#define ixD3F2_PCIE_P_PORT_LANE_STATUS 0x50
+#define ixD3F2_PCIE_FC_P 0x60
+#define ixD3F2_PCIE_FC_NP 0x61
+#define ixD3F2_PCIE_FC_CPL 0x62
+#define ixD3F2_PCIE_ERR_CNTL 0x6a
+#define ixD3F2_PCIE_RX_CNTL 0x70
+#define ixD3F2_PCIE_RX_EXPECTED_SEQNUM 0x71
+#define ixD3F2_PCIE_RX_VENDOR_SPECIFIC 0x72
+#define ixD3F2_PCIE_RX_CNTL3 0x74
+#define ixD3F2_PCIE_RX_CREDITS_ALLOCATED_P 0x80
+#define ixD3F2_PCIE_RX_CREDITS_ALLOCATED_NP 0x81
+#define ixD3F2_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82
+#define ixD3F2_PCIEP_ERROR_INJECT_PHYSICAL 0x83
+#define ixD3F2_PCIEP_ERROR_INJECT_TRANSACTION 0x84
+#define ixD3F2_PCIE_LC_CNTL 0xa0
+#define ixD3F2_PCIE_LC_CNTL2 0xb1
+#define ixD3F2_PCIE_LC_CNTL3 0xb5
+#define ixD3F2_PCIE_LC_CNTL4 0xb6
+#define ixD3F2_PCIE_LC_CNTL5 0xb7
+#define ixD3F2_PCIE_LC_CNTL6 0xbb
+#define ixD3F2_PCIE_LC_BW_CHANGE_CNTL 0xb2
+#define ixD3F2_PCIE_LC_TRAINING_CNTL 0xa1
+#define ixD3F2_PCIE_LC_LINK_WIDTH_CNTL 0xa2
+#define ixD3F2_PCIE_LC_N_FTS_CNTL 0xa3
+#define ixD3F2_PCIE_LC_SPEED_CNTL 0xa4
+#define ixD3F2_PCIE_LC_CDR_CNTL 0xb3
+#define ixD3F2_PCIE_LC_LANE_CNTL 0xb4
+#define ixD3F2_PCIE_LC_FORCE_COEFF 0xb8
+#define ixD3F2_PCIE_LC_BEST_EQ_SETTINGS 0xb9
+#define ixD3F2_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba
+#define ixD3F2_PCIE_LC_STATE0 0xa5
+#define ixD3F2_PCIE_LC_STATE1 0xa6
+#define ixD3F2_PCIE_LC_STATE2 0xa7
+#define ixD3F2_PCIE_LC_STATE3 0xa8
+#define ixD3F2_PCIE_LC_STATE4 0xa9
+#define ixD3F2_PCIE_LC_STATE5 0xaa
+#define ixD3F2_PCIEP_STRAP_LC 0xc0
+#define ixD3F2_PCIEP_STRAP_MISC 0xc1
+#define ixD3F2_PCIEP_BCH_ECC_CNTL 0xd0
+#define ixD3F2_PCIEP_HPGI_PRIVATE 0xd2
+#define ixD3F2_PCIEP_HPGI 0xda
+#define ixD3F2_VENDOR_ID 0x8000000
+#define ixD3F2_DEVICE_ID 0x8000000
+#define ixD3F2_COMMAND 0x8000001
+#define ixD3F2_STATUS 0x8000001
+#define ixD3F2_REVISION_ID 0x8000002
+#define ixD3F2_PROG_INTERFACE 0x8000002
+#define ixD3F2_SUB_CLASS 0x8000002
+#define ixD3F2_BASE_CLASS 0x8000002
+#define ixD3F2_CACHE_LINE 0x8000003
+#define ixD3F2_LATENCY 0x8000003
+#define ixD3F2_HEADER 0x8000003
+#define ixD3F2_BIST 0x8000003
+#define ixD3F2_SUB_BUS_NUMBER_LATENCY 0x8000006
+#define ixD3F2_IO_BASE_LIMIT 0x8000007
+#define ixD3F2_SECONDARY_STATUS 0x8000007
+#define ixD3F2_MEM_BASE_LIMIT 0x8000008
+#define ixD3F2_PREF_BASE_LIMIT 0x8000009
+#define ixD3F2_PREF_BASE_UPPER 0x800000a
+#define ixD3F2_PREF_LIMIT_UPPER 0x800000b
+#define ixD3F2_IO_BASE_LIMIT_HI 0x800000c
+#define ixD3F2_IRQ_BRIDGE_CNTL 0x800000f
+#define ixD3F2_CAP_PTR 0x800000d
+#define ixD3F2_INTERRUPT_LINE 0x800000f
+#define ixD3F2_INTERRUPT_PIN 0x800000f
+#define ixD3F2_EXT_BRIDGE_CNTL 0x8000010
+#define ixD3F2_PMI_CAP_LIST 0x8000014
+#define ixD3F2_PMI_CAP 0x8000014
+#define ixD3F2_PMI_STATUS_CNTL 0x8000015
+#define ixD3F2_PCIE_CAP_LIST 0x8000016
+#define ixD3F2_PCIE_CAP 0x8000016
+#define ixD3F2_DEVICE_CAP 0x8000017
+#define ixD3F2_DEVICE_CNTL 0x8000018
+#define ixD3F2_DEVICE_STATUS 0x8000018
+#define ixD3F2_LINK_CAP 0x8000019
+#define ixD3F2_LINK_CNTL 0x800001a
+#define ixD3F2_LINK_STATUS 0x800001a
+#define ixD3F2_SLOT_CAP 0x800001b
+#define ixD3F2_SLOT_CNTL 0x800001c
+#define ixD3F2_SLOT_STATUS 0x800001c
+#define ixD3F2_ROOT_CNTL 0x800001d
+#define ixD3F2_ROOT_CAP 0x800001d
+#define ixD3F2_ROOT_STATUS 0x800001e
+#define ixD3F2_DEVICE_CAP2 0x800001f
+#define ixD3F2_DEVICE_CNTL2 0x8000020
+#define ixD3F2_DEVICE_STATUS2 0x8000020
+#define ixD3F2_LINK_CAP2 0x8000021
+#define ixD3F2_LINK_CNTL2 0x8000022
+#define ixD3F2_LINK_STATUS2 0x8000022
+#define ixD3F2_SLOT_CAP2 0x8000023
+#define ixD3F2_SLOT_CNTL2 0x8000024
+#define ixD3F2_SLOT_STATUS2 0x8000024
+#define ixD3F2_MSI_CAP_LIST 0x8000028
+#define ixD3F2_MSI_MSG_CNTL 0x8000028
+#define ixD3F2_MSI_MSG_ADDR_LO 0x8000029
+#define ixD3F2_MSI_MSG_ADDR_HI 0x800002a
+#define ixD3F2_MSI_MSG_DATA_64 0x800002b
+#define ixD3F2_MSI_MSG_DATA 0x800002a
+#define ixD3F2_SSID_CAP_LIST 0x8000030
+#define ixD3F2_SSID_CAP 0x8000031
+#define ixD3F2_MSI_MAP_CAP_LIST 0x8000032
+#define ixD3F2_MSI_MAP_CAP 0x8000032
+#define ixD3F2_MSI_MAP_ADDR_LO 0x8000033
+#define ixD3F2_MSI_MAP_ADDR_HI 0x8000034
+#define ixD3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x8000040
+#define ixD3F2_PCIE_VENDOR_SPECIFIC_HDR 0x8000041
+#define ixD3F2_PCIE_VENDOR_SPECIFIC1 0x8000042
+#define ixD3F2_PCIE_VENDOR_SPECIFIC2 0x8000043
+#define ixD3F2_PCIE_VC_ENH_CAP_LIST 0x8000044
+#define ixD3F2_PCIE_PORT_VC_CAP_REG1 0x8000045
+#define ixD3F2_PCIE_PORT_VC_CAP_REG2 0x8000046
+#define ixD3F2_PCIE_PORT_VC_CNTL 0x8000047
+#define ixD3F2_PCIE_PORT_VC_STATUS 0x8000047
+#define ixD3F2_PCIE_VC0_RESOURCE_CAP 0x8000048
+#define ixD3F2_PCIE_VC0_RESOURCE_CNTL 0x8000049
+#define ixD3F2_PCIE_VC0_RESOURCE_STATUS 0x800004a
+#define ixD3F2_PCIE_VC1_RESOURCE_CAP 0x800004b
+#define ixD3F2_PCIE_VC1_RESOURCE_CNTL 0x800004c
+#define ixD3F2_PCIE_VC1_RESOURCE_STATUS 0x800004d
+#define ixD3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x8000050
+#define ixD3F2_PCIE_DEV_SERIAL_NUM_DW1 0x8000051
+#define ixD3F2_PCIE_DEV_SERIAL_NUM_DW2 0x8000052
+#define ixD3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x8000054
+#define ixD3F2_PCIE_UNCORR_ERR_STATUS 0x8000055
+#define ixD3F2_PCIE_UNCORR_ERR_MASK 0x8000056
+#define ixD3F2_PCIE_UNCORR_ERR_SEVERITY 0x8000057
+#define ixD3F2_PCIE_CORR_ERR_STATUS 0x8000058
+#define ixD3F2_PCIE_CORR_ERR_MASK 0x8000059
+#define ixD3F2_PCIE_ADV_ERR_CAP_CNTL 0x800005a
+#define ixD3F2_PCIE_HDR_LOG0 0x800005b
+#define ixD3F2_PCIE_HDR_LOG1 0x800005c
+#define ixD3F2_PCIE_HDR_LOG2 0x800005d
+#define ixD3F2_PCIE_HDR_LOG3 0x800005e
+#define ixD3F2_PCIE_ROOT_ERR_CMD 0x800005f
+#define ixD3F2_PCIE_ROOT_ERR_STATUS 0x8000060
+#define ixD3F2_PCIE_ERR_SRC_ID 0x8000061
+#define ixD3F2_PCIE_TLP_PREFIX_LOG0 0x8000062
+#define ixD3F2_PCIE_TLP_PREFIX_LOG1 0x8000063
+#define ixD3F2_PCIE_TLP_PREFIX_LOG2 0x8000064
+#define ixD3F2_PCIE_TLP_PREFIX_LOG3 0x8000065
+#define ixD3F2_PCIE_SECONDARY_ENH_CAP_LIST 0x800009c
+#define ixD3F2_PCIE_LINK_CNTL3 0x800009d
+#define ixD3F2_PCIE_LANE_ERROR_STATUS 0x800009e
+#define ixD3F2_PCIE_LANE_0_EQUALIZATION_CNTL 0x800009f
+#define ixD3F2_PCIE_LANE_1_EQUALIZATION_CNTL 0x800009f
+#define ixD3F2_PCIE_LANE_2_EQUALIZATION_CNTL 0x80000a0
+#define ixD3F2_PCIE_LANE_3_EQUALIZATION_CNTL 0x80000a0
+#define ixD3F2_PCIE_LANE_4_EQUALIZATION_CNTL 0x80000a1
+#define ixD3F2_PCIE_LANE_5_EQUALIZATION_CNTL 0x80000a1
+#define ixD3F2_PCIE_LANE_6_EQUALIZATION_CNTL 0x80000a2
+#define ixD3F2_PCIE_LANE_7_EQUALIZATION_CNTL 0x80000a2
+#define ixD3F2_PCIE_LANE_8_EQUALIZATION_CNTL 0x80000a3
+#define ixD3F2_PCIE_LANE_9_EQUALIZATION_CNTL 0x80000a3
+#define ixD3F2_PCIE_LANE_10_EQUALIZATION_CNTL 0x80000a4
+#define ixD3F2_PCIE_LANE_11_EQUALIZATION_CNTL 0x80000a4
+#define ixD3F2_PCIE_LANE_12_EQUALIZATION_CNTL 0x80000a5
+#define ixD3F2_PCIE_LANE_13_EQUALIZATION_CNTL 0x80000a5
+#define ixD3F2_PCIE_LANE_14_EQUALIZATION_CNTL 0x80000a6
+#define ixD3F2_PCIE_LANE_15_EQUALIZATION_CNTL 0x80000a6
+#define ixD3F2_PCIE_ACS_ENH_CAP_LIST 0x80000a8
+#define ixD3F2_PCIE_ACS_CAP 0x80000a9
+#define ixD3F2_PCIE_ACS_CNTL 0x80000a9
+#define ixD3F2_PCIE_MC_ENH_CAP_LIST 0x80000bc
+#define ixD3F2_PCIE_MC_CAP 0x80000bd
+#define ixD3F2_PCIE_MC_CNTL 0x80000bd
+#define ixD3F2_PCIE_MC_ADDR0 0x80000be
+#define ixD3F2_PCIE_MC_ADDR1 0x80000bf
+#define ixD3F2_PCIE_MC_RCV0 0x80000c0
+#define ixD3F2_PCIE_MC_RCV1 0x80000c1
+#define ixD3F2_PCIE_MC_BLOCK_ALL0 0x80000c2
+#define ixD3F2_PCIE_MC_BLOCK_ALL1 0x80000c3
+#define ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_0 0x80000c4
+#define ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_1 0x80000c5
+#define ixD3F2_PCIE_MC_OVERLAY_BAR0 0x80000c6
+#define ixD3F2_PCIE_MC_OVERLAY_BAR1 0x80000c7
+#define ixD3F3_PCIE_PORT_INDEX 0x9000038
+#define ixD3F3_PCIE_PORT_DATA 0x9000039
+#define ixD3F3_PCIEP_RESERVED 0x0
+#define ixD3F3_PCIEP_SCRATCH 0x1
+#define ixD3F3_PCIEP_HW_DEBUG 0x2
+#define ixD3F3_PCIEP_PORT_CNTL 0x10
+#define ixD3F3_PCIE_TX_CNTL 0x20
+#define ixD3F3_PCIE_TX_REQUESTER_ID 0x21
+#define ixD3F3_PCIE_TX_VENDOR_SPECIFIC 0x22
+#define ixD3F3_PCIE_TX_REQUEST_NUM_CNTL 0x23
+#define ixD3F3_PCIE_TX_SEQ 0x24
+#define ixD3F3_PCIE_TX_REPLAY 0x25
+#define ixD3F3_PCIE_TX_ACK_LATENCY_LIMIT 0x26
+#define ixD3F3_PCIE_TX_CREDITS_ADVT_P 0x30
+#define ixD3F3_PCIE_TX_CREDITS_ADVT_NP 0x31
+#define ixD3F3_PCIE_TX_CREDITS_ADVT_CPL 0x32
+#define ixD3F3_PCIE_TX_CREDITS_INIT_P 0x33
+#define ixD3F3_PCIE_TX_CREDITS_INIT_NP 0x34
+#define ixD3F3_PCIE_TX_CREDITS_INIT_CPL 0x35
+#define ixD3F3_PCIE_TX_CREDITS_STATUS 0x36
+#define ixD3F3_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37
+#define ixD3F3_PCIE_P_PORT_LANE_STATUS 0x50
+#define ixD3F3_PCIE_FC_P 0x60
+#define ixD3F3_PCIE_FC_NP 0x61
+#define ixD3F3_PCIE_FC_CPL 0x62
+#define ixD3F3_PCIE_ERR_CNTL 0x6a
+#define ixD3F3_PCIE_RX_CNTL 0x70
+#define ixD3F3_PCIE_RX_EXPECTED_SEQNUM 0x71
+#define ixD3F3_PCIE_RX_VENDOR_SPECIFIC 0x72
+#define ixD3F3_PCIE_RX_CNTL3 0x74
+#define ixD3F3_PCIE_RX_CREDITS_ALLOCATED_P 0x80
+#define ixD3F3_PCIE_RX_CREDITS_ALLOCATED_NP 0x81
+#define ixD3F3_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82
+#define ixD3F3_PCIEP_ERROR_INJECT_PHYSICAL 0x83
+#define ixD3F3_PCIEP_ERROR_INJECT_TRANSACTION 0x84
+#define ixD3F3_PCIE_LC_CNTL 0xa0
+#define ixD3F3_PCIE_LC_CNTL2 0xb1
+#define ixD3F3_PCIE_LC_CNTL3 0xb5
+#define ixD3F3_PCIE_LC_CNTL4 0xb6
+#define ixD3F3_PCIE_LC_CNTL5 0xb7
+#define ixD3F3_PCIE_LC_CNTL6 0xbb
+#define ixD3F3_PCIE_LC_BW_CHANGE_CNTL 0xb2
+#define ixD3F3_PCIE_LC_TRAINING_CNTL 0xa1
+#define ixD3F3_PCIE_LC_LINK_WIDTH_CNTL 0xa2
+#define ixD3F3_PCIE_LC_N_FTS_CNTL 0xa3
+#define ixD3F3_PCIE_LC_SPEED_CNTL 0xa4
+#define ixD3F3_PCIE_LC_CDR_CNTL 0xb3
+#define ixD3F3_PCIE_LC_LANE_CNTL 0xb4
+#define ixD3F3_PCIE_LC_FORCE_COEFF 0xb8
+#define ixD3F3_PCIE_LC_BEST_EQ_SETTINGS 0xb9
+#define ixD3F3_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba
+#define ixD3F3_PCIE_LC_STATE0 0xa5
+#define ixD3F3_PCIE_LC_STATE1 0xa6
+#define ixD3F3_PCIE_LC_STATE2 0xa7
+#define ixD3F3_PCIE_LC_STATE3 0xa8
+#define ixD3F3_PCIE_LC_STATE4 0xa9
+#define ixD3F3_PCIE_LC_STATE5 0xaa
+#define ixD3F3_PCIEP_STRAP_LC 0xc0
+#define ixD3F3_PCIEP_STRAP_MISC 0xc1
+#define ixD3F3_PCIEP_BCH_ECC_CNTL 0xd0
+#define ixD3F3_PCIEP_HPGI_PRIVATE 0xd2
+#define ixD3F3_PCIEP_HPGI 0xda
+#define ixD3F3_VENDOR_ID 0x9000000
+#define ixD3F3_DEVICE_ID 0x9000000
+#define ixD3F3_COMMAND 0x9000001
+#define ixD3F3_STATUS 0x9000001
+#define ixD3F3_REVISION_ID 0x9000002
+#define ixD3F3_PROG_INTERFACE 0x9000002
+#define ixD3F3_SUB_CLASS 0x9000002
+#define ixD3F3_BASE_CLASS 0x9000002
+#define ixD3F3_CACHE_LINE 0x9000003
+#define ixD3F3_LATENCY 0x9000003
+#define ixD3F3_HEADER 0x9000003
+#define ixD3F3_BIST 0x9000003
+#define ixD3F3_SUB_BUS_NUMBER_LATENCY 0x9000006
+#define ixD3F3_IO_BASE_LIMIT 0x9000007
+#define ixD3F3_SECONDARY_STATUS 0x9000007
+#define ixD3F3_MEM_BASE_LIMIT 0x9000008
+#define ixD3F3_PREF_BASE_LIMIT 0x9000009
+#define ixD3F3_PREF_BASE_UPPER 0x900000a
+#define ixD3F3_PREF_LIMIT_UPPER 0x900000b
+#define ixD3F3_IO_BASE_LIMIT_HI 0x900000c
+#define ixD3F3_IRQ_BRIDGE_CNTL 0x900000f
+#define ixD3F3_CAP_PTR 0x900000d
+#define ixD3F3_INTERRUPT_LINE 0x900000f
+#define ixD3F3_INTERRUPT_PIN 0x900000f
+#define ixD3F3_EXT_BRIDGE_CNTL 0x9000010
+#define ixD3F3_PMI_CAP_LIST 0x9000014
+#define ixD3F3_PMI_CAP 0x9000014
+#define ixD3F3_PMI_STATUS_CNTL 0x9000015
+#define ixD3F3_PCIE_CAP_LIST 0x9000016
+#define ixD3F3_PCIE_CAP 0x9000016
+#define ixD3F3_DEVICE_CAP 0x9000017
+#define ixD3F3_DEVICE_CNTL 0x9000018
+#define ixD3F3_DEVICE_STATUS 0x9000018
+#define ixD3F3_LINK_CAP 0x9000019
+#define ixD3F3_LINK_CNTL 0x900001a
+#define ixD3F3_LINK_STATUS 0x900001a
+#define ixD3F3_SLOT_CAP 0x900001b
+#define ixD3F3_SLOT_CNTL 0x900001c
+#define ixD3F3_SLOT_STATUS 0x900001c
+#define ixD3F3_ROOT_CNTL 0x900001d
+#define ixD3F3_ROOT_CAP 0x900001d
+#define ixD3F3_ROOT_STATUS 0x900001e
+#define ixD3F3_DEVICE_CAP2 0x900001f
+#define ixD3F3_DEVICE_CNTL2 0x9000020
+#define ixD3F3_DEVICE_STATUS2 0x9000020
+#define ixD3F3_LINK_CAP2 0x9000021
+#define ixD3F3_LINK_CNTL2 0x9000022
+#define ixD3F3_LINK_STATUS2 0x9000022
+#define ixD3F3_SLOT_CAP2 0x9000023
+#define ixD3F3_SLOT_CNTL2 0x9000024
+#define ixD3F3_SLOT_STATUS2 0x9000024
+#define ixD3F3_MSI_CAP_LIST 0x9000028
+#define ixD3F3_MSI_MSG_CNTL 0x9000028
+#define ixD3F3_MSI_MSG_ADDR_LO 0x9000029
+#define ixD3F3_MSI_MSG_ADDR_HI 0x900002a
+#define ixD3F3_MSI_MSG_DATA_64 0x900002b
+#define ixD3F3_MSI_MSG_DATA 0x900002a
+#define ixD3F3_SSID_CAP_LIST 0x9000030
+#define ixD3F3_SSID_CAP 0x9000031
+#define ixD3F3_MSI_MAP_CAP_LIST 0x9000032
+#define ixD3F3_MSI_MAP_CAP 0x9000032
+#define ixD3F3_MSI_MAP_ADDR_LO 0x9000033
+#define ixD3F3_MSI_MAP_ADDR_HI 0x9000034
+#define ixD3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x9000040
+#define ixD3F3_PCIE_VENDOR_SPECIFIC_HDR 0x9000041
+#define ixD3F3_PCIE_VENDOR_SPECIFIC1 0x9000042
+#define ixD3F3_PCIE_VENDOR_SPECIFIC2 0x9000043
+#define ixD3F3_PCIE_VC_ENH_CAP_LIST 0x9000044
+#define ixD3F3_PCIE_PORT_VC_CAP_REG1 0x9000045
+#define ixD3F3_PCIE_PORT_VC_CAP_REG2 0x9000046
+#define ixD3F3_PCIE_PORT_VC_CNTL 0x9000047
+#define ixD3F3_PCIE_PORT_VC_STATUS 0x9000047
+#define ixD3F3_PCIE_VC0_RESOURCE_CAP 0x9000048
+#define ixD3F3_PCIE_VC0_RESOURCE_CNTL 0x9000049
+#define ixD3F3_PCIE_VC0_RESOURCE_STATUS 0x900004a
+#define ixD3F3_PCIE_VC1_RESOURCE_CAP 0x900004b
+#define ixD3F3_PCIE_VC1_RESOURCE_CNTL 0x900004c
+#define ixD3F3_PCIE_VC1_RESOURCE_STATUS 0x900004d
+#define ixD3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x9000050
+#define ixD3F3_PCIE_DEV_SERIAL_NUM_DW1 0x9000051
+#define ixD3F3_PCIE_DEV_SERIAL_NUM_DW2 0x9000052
+#define ixD3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x9000054
+#define ixD3F3_PCIE_UNCORR_ERR_STATUS 0x9000055
+#define ixD3F3_PCIE_UNCORR_ERR_MASK 0x9000056
+#define ixD3F3_PCIE_UNCORR_ERR_SEVERITY 0x9000057
+#define ixD3F3_PCIE_CORR_ERR_STATUS 0x9000058
+#define ixD3F3_PCIE_CORR_ERR_MASK 0x9000059
+#define ixD3F3_PCIE_ADV_ERR_CAP_CNTL 0x900005a
+#define ixD3F3_PCIE_HDR_LOG0 0x900005b
+#define ixD3F3_PCIE_HDR_LOG1 0x900005c
+#define ixD3F3_PCIE_HDR_LOG2 0x900005d
+#define ixD3F3_PCIE_HDR_LOG3 0x900005e
+#define ixD3F3_PCIE_ROOT_ERR_CMD 0x900005f
+#define ixD3F3_PCIE_ROOT_ERR_STATUS 0x9000060
+#define ixD3F3_PCIE_ERR_SRC_ID 0x9000061
+#define ixD3F3_PCIE_TLP_PREFIX_LOG0 0x9000062
+#define ixD3F3_PCIE_TLP_PREFIX_LOG1 0x9000063
+#define ixD3F3_PCIE_TLP_PREFIX_LOG2 0x9000064
+#define ixD3F3_PCIE_TLP_PREFIX_LOG3 0x9000065
+#define ixD3F3_PCIE_SECONDARY_ENH_CAP_LIST 0x900009c
+#define ixD3F3_PCIE_LINK_CNTL3 0x900009d
+#define ixD3F3_PCIE_LANE_ERROR_STATUS 0x900009e
+#define ixD3F3_PCIE_LANE_0_EQUALIZATION_CNTL 0x900009f
+#define ixD3F3_PCIE_LANE_1_EQUALIZATION_CNTL 0x900009f
+#define ixD3F3_PCIE_LANE_2_EQUALIZATION_CNTL 0x90000a0
+#define ixD3F3_PCIE_LANE_3_EQUALIZATION_CNTL 0x90000a0
+#define ixD3F3_PCIE_LANE_4_EQUALIZATION_CNTL 0x90000a1
+#define ixD3F3_PCIE_LANE_5_EQUALIZATION_CNTL 0x90000a1
+#define ixD3F3_PCIE_LANE_6_EQUALIZATION_CNTL 0x90000a2
+#define ixD3F3_PCIE_LANE_7_EQUALIZATION_CNTL 0x90000a2
+#define ixD3F3_PCIE_LANE_8_EQUALIZATION_CNTL 0x90000a3
+#define ixD3F3_PCIE_LANE_9_EQUALIZATION_CNTL 0x90000a3
+#define ixD3F3_PCIE_LANE_10_EQUALIZATION_CNTL 0x90000a4
+#define ixD3F3_PCIE_LANE_11_EQUALIZATION_CNTL 0x90000a4
+#define ixD3F3_PCIE_LANE_12_EQUALIZATION_CNTL 0x90000a5
+#define ixD3F3_PCIE_LANE_13_EQUALIZATION_CNTL 0x90000a5
+#define ixD3F3_PCIE_LANE_14_EQUALIZATION_CNTL 0x90000a6
+#define ixD3F3_PCIE_LANE_15_EQUALIZATION_CNTL 0x90000a6
+#define ixD3F3_PCIE_ACS_ENH_CAP_LIST 0x90000a8
+#define ixD3F3_PCIE_ACS_CAP 0x90000a9
+#define ixD3F3_PCIE_ACS_CNTL 0x90000a9
+#define ixD3F3_PCIE_MC_ENH_CAP_LIST 0x90000bc
+#define ixD3F3_PCIE_MC_CAP 0x90000bd
+#define ixD3F3_PCIE_MC_CNTL 0x90000bd
+#define ixD3F3_PCIE_MC_ADDR0 0x90000be
+#define ixD3F3_PCIE_MC_ADDR1 0x90000bf
+#define ixD3F3_PCIE_MC_RCV0 0x90000c0
+#define ixD3F3_PCIE_MC_RCV1 0x90000c1
+#define ixD3F3_PCIE_MC_BLOCK_ALL0 0x90000c2
+#define ixD3F3_PCIE_MC_BLOCK_ALL1 0x90000c3
+#define ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_0 0x90000c4
+#define ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_1 0x90000c5
+#define ixD3F3_PCIE_MC_OVERLAY_BAR0 0x90000c6
+#define ixD3F3_PCIE_MC_OVERLAY_BAR1 0x90000c7
+#define ixD3F4_PCIE_PORT_INDEX 0xa000038
+#define ixD3F4_PCIE_PORT_DATA 0xa000039
+#define ixD3F4_PCIEP_RESERVED 0x0
+#define ixD3F4_PCIEP_SCRATCH 0x1
+#define ixD3F4_PCIEP_HW_DEBUG 0x2
+#define ixD3F4_PCIEP_PORT_CNTL 0x10
+#define ixD3F4_PCIE_TX_CNTL 0x20
+#define ixD3F4_PCIE_TX_REQUESTER_ID 0x21
+#define ixD3F4_PCIE_TX_VENDOR_SPECIFIC 0x22
+#define ixD3F4_PCIE_TX_REQUEST_NUM_CNTL 0x23
+#define ixD3F4_PCIE_TX_SEQ 0x24
+#define ixD3F4_PCIE_TX_REPLAY 0x25
+#define ixD3F4_PCIE_TX_ACK_LATENCY_LIMIT 0x26
+#define ixD3F4_PCIE_TX_CREDITS_ADVT_P 0x30
+#define ixD3F4_PCIE_TX_CREDITS_ADVT_NP 0x31
+#define ixD3F4_PCIE_TX_CREDITS_ADVT_CPL 0x32
+#define ixD3F4_PCIE_TX_CREDITS_INIT_P 0x33
+#define ixD3F4_PCIE_TX_CREDITS_INIT_NP 0x34
+#define ixD3F4_PCIE_TX_CREDITS_INIT_CPL 0x35
+#define ixD3F4_PCIE_TX_CREDITS_STATUS 0x36
+#define ixD3F4_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37
+#define ixD3F4_PCIE_P_PORT_LANE_STATUS 0x50
+#define ixD3F4_PCIE_FC_P 0x60
+#define ixD3F4_PCIE_FC_NP 0x61
+#define ixD3F4_PCIE_FC_CPL 0x62
+#define ixD3F4_PCIE_ERR_CNTL 0x6a
+#define ixD3F4_PCIE_RX_CNTL 0x70
+#define ixD3F4_PCIE_RX_EXPECTED_SEQNUM 0x71
+#define ixD3F4_PCIE_RX_VENDOR_SPECIFIC 0x72
+#define ixD3F4_PCIE_RX_CNTL3 0x74
+#define ixD3F4_PCIE_RX_CREDITS_ALLOCATED_P 0x80
+#define ixD3F4_PCIE_RX_CREDITS_ALLOCATED_NP 0x81
+#define ixD3F4_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82
+#define ixD3F4_PCIEP_ERROR_INJECT_PHYSICAL 0x83
+#define ixD3F4_PCIEP_ERROR_INJECT_TRANSACTION 0x84
+#define ixD3F4_PCIE_LC_CNTL 0xa0
+#define ixD3F4_PCIE_LC_CNTL2 0xb1
+#define ixD3F4_PCIE_LC_CNTL3 0xb5
+#define ixD3F4_PCIE_LC_CNTL4 0xb6
+#define ixD3F4_PCIE_LC_CNTL5 0xb7
+#define ixD3F4_PCIE_LC_CNTL6 0xbb
+#define ixD3F4_PCIE_LC_BW_CHANGE_CNTL 0xb2
+#define ixD3F4_PCIE_LC_TRAINING_CNTL 0xa1
+#define ixD3F4_PCIE_LC_LINK_WIDTH_CNTL 0xa2
+#define ixD3F4_PCIE_LC_N_FTS_CNTL 0xa3
+#define ixD3F4_PCIE_LC_SPEED_CNTL 0xa4
+#define ixD3F4_PCIE_LC_CDR_CNTL 0xb3
+#define ixD3F4_PCIE_LC_LANE_CNTL 0xb4
+#define ixD3F4_PCIE_LC_FORCE_COEFF 0xb8
+#define ixD3F4_PCIE_LC_BEST_EQ_SETTINGS 0xb9
+#define ixD3F4_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba
+#define ixD3F4_PCIE_LC_STATE0 0xa5
+#define ixD3F4_PCIE_LC_STATE1 0xa6
+#define ixD3F4_PCIE_LC_STATE2 0xa7
+#define ixD3F4_PCIE_LC_STATE3 0xa8
+#define ixD3F4_PCIE_LC_STATE4 0xa9
+#define ixD3F4_PCIE_LC_STATE5 0xaa
+#define ixD3F4_PCIEP_STRAP_LC 0xc0
+#define ixD3F4_PCIEP_STRAP_MISC 0xc1
+#define ixD3F4_PCIEP_BCH_ECC_CNTL 0xd0
+#define ixD3F4_PCIEP_HPGI_PRIVATE 0xd2
+#define ixD3F4_PCIEP_HPGI 0xda
+#define ixD3F4_VENDOR_ID 0xa000000
+#define ixD3F4_DEVICE_ID 0xa000000
+#define ixD3F4_COMMAND 0xa000001
+#define ixD3F4_STATUS 0xa000001
+#define ixD3F4_REVISION_ID 0xa000002
+#define ixD3F4_PROG_INTERFACE 0xa000002
+#define ixD3F4_SUB_CLASS 0xa000002
+#define ixD3F4_BASE_CLASS 0xa000002
+#define ixD3F4_CACHE_LINE 0xa000003
+#define ixD3F4_LATENCY 0xa000003
+#define ixD3F4_HEADER 0xa000003
+#define ixD3F4_BIST 0xa000003
+#define ixD3F4_SUB_BUS_NUMBER_LATENCY 0xa000006
+#define ixD3F4_IO_BASE_LIMIT 0xa000007
+#define ixD3F4_SECONDARY_STATUS 0xa000007
+#define ixD3F4_MEM_BASE_LIMIT 0xa000008
+#define ixD3F4_PREF_BASE_LIMIT 0xa000009
+#define ixD3F4_PREF_BASE_UPPER 0xa00000a
+#define ixD3F4_PREF_LIMIT_UPPER 0xa00000b
+#define ixD3F4_IO_BASE_LIMIT_HI 0xa00000c
+#define ixD3F4_IRQ_BRIDGE_CNTL 0xa00000f
+#define ixD3F4_CAP_PTR 0xa00000d
+#define ixD3F4_INTERRUPT_LINE 0xa00000f
+#define ixD3F4_INTERRUPT_PIN 0xa00000f
+#define ixD3F4_EXT_BRIDGE_CNTL 0xa000010
+#define ixD3F4_PMI_CAP_LIST 0xa000014
+#define ixD3F4_PMI_CAP 0xa000014
+#define ixD3F4_PMI_STATUS_CNTL 0xa000015
+#define ixD3F4_PCIE_CAP_LIST 0xa000016
+#define ixD3F4_PCIE_CAP 0xa000016
+#define ixD3F4_DEVICE_CAP 0xa000017
+#define ixD3F4_DEVICE_CNTL 0xa000018
+#define ixD3F4_DEVICE_STATUS 0xa000018
+#define ixD3F4_LINK_CAP 0xa000019
+#define ixD3F4_LINK_CNTL 0xa00001a
+#define ixD3F4_LINK_STATUS 0xa00001a
+#define ixD3F4_SLOT_CAP 0xa00001b
+#define ixD3F4_SLOT_CNTL 0xa00001c
+#define ixD3F4_SLOT_STATUS 0xa00001c
+#define ixD3F4_ROOT_CNTL 0xa00001d
+#define ixD3F4_ROOT_CAP 0xa00001d
+#define ixD3F4_ROOT_STATUS 0xa00001e
+#define ixD3F4_DEVICE_CAP2 0xa00001f
+#define ixD3F4_DEVICE_CNTL2 0xa000020
+#define ixD3F4_DEVICE_STATUS2 0xa000020
+#define ixD3F4_LINK_CAP2 0xa000021
+#define ixD3F4_LINK_CNTL2 0xa000022
+#define ixD3F4_LINK_STATUS2 0xa000022
+#define ixD3F4_SLOT_CAP2 0xa000023
+#define ixD3F4_SLOT_CNTL2 0xa000024
+#define ixD3F4_SLOT_STATUS2 0xa000024
+#define ixD3F4_MSI_CAP_LIST 0xa000028
+#define ixD3F4_MSI_MSG_CNTL 0xa000028
+#define ixD3F4_MSI_MSG_ADDR_LO 0xa000029
+#define ixD3F4_MSI_MSG_ADDR_HI 0xa00002a
+#define ixD3F4_MSI_MSG_DATA_64 0xa00002b
+#define ixD3F4_MSI_MSG_DATA 0xa00002a
+#define ixD3F4_SSID_CAP_LIST 0xa000030
+#define ixD3F4_SSID_CAP 0xa000031
+#define ixD3F4_MSI_MAP_CAP_LIST 0xa000032
+#define ixD3F4_MSI_MAP_CAP 0xa000032
+#define ixD3F4_MSI_MAP_ADDR_LO 0xa000033
+#define ixD3F4_MSI_MAP_ADDR_HI 0xa000034
+#define ixD3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xa000040
+#define ixD3F4_PCIE_VENDOR_SPECIFIC_HDR 0xa000041
+#define ixD3F4_PCIE_VENDOR_SPECIFIC1 0xa000042
+#define ixD3F4_PCIE_VENDOR_SPECIFIC2 0xa000043
+#define ixD3F4_PCIE_VC_ENH_CAP_LIST 0xa000044
+#define ixD3F4_PCIE_PORT_VC_CAP_REG1 0xa000045
+#define ixD3F4_PCIE_PORT_VC_CAP_REG2 0xa000046
+#define ixD3F4_PCIE_PORT_VC_CNTL 0xa000047
+#define ixD3F4_PCIE_PORT_VC_STATUS 0xa000047
+#define ixD3F4_PCIE_VC0_RESOURCE_CAP 0xa000048
+#define ixD3F4_PCIE_VC0_RESOURCE_CNTL 0xa000049
+#define ixD3F4_PCIE_VC0_RESOURCE_STATUS 0xa00004a
+#define ixD3F4_PCIE_VC1_RESOURCE_CAP 0xa00004b
+#define ixD3F4_PCIE_VC1_RESOURCE_CNTL 0xa00004c
+#define ixD3F4_PCIE_VC1_RESOURCE_STATUS 0xa00004d
+#define ixD3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xa000050
+#define ixD3F4_PCIE_DEV_SERIAL_NUM_DW1 0xa000051
+#define ixD3F4_PCIE_DEV_SERIAL_NUM_DW2 0xa000052
+#define ixD3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xa000054
+#define ixD3F4_PCIE_UNCORR_ERR_STATUS 0xa000055
+#define ixD3F4_PCIE_UNCORR_ERR_MASK 0xa000056
+#define ixD3F4_PCIE_UNCORR_ERR_SEVERITY 0xa000057
+#define ixD3F4_PCIE_CORR_ERR_STATUS 0xa000058
+#define ixD3F4_PCIE_CORR_ERR_MASK 0xa000059
+#define ixD3F4_PCIE_ADV_ERR_CAP_CNTL 0xa00005a
+#define ixD3F4_PCIE_HDR_LOG0 0xa00005b
+#define ixD3F4_PCIE_HDR_LOG1 0xa00005c
+#define ixD3F4_PCIE_HDR_LOG2 0xa00005d
+#define ixD3F4_PCIE_HDR_LOG3 0xa00005e
+#define ixD3F4_PCIE_ROOT_ERR_CMD 0xa00005f
+#define ixD3F4_PCIE_ROOT_ERR_STATUS 0xa000060
+#define ixD3F4_PCIE_ERR_SRC_ID 0xa000061
+#define ixD3F4_PCIE_TLP_PREFIX_LOG0 0xa000062
+#define ixD3F4_PCIE_TLP_PREFIX_LOG1 0xa000063
+#define ixD3F4_PCIE_TLP_PREFIX_LOG2 0xa000064
+#define ixD3F4_PCIE_TLP_PREFIX_LOG3 0xa000065
+#define ixD3F4_PCIE_SECONDARY_ENH_CAP_LIST 0xa00009c
+#define ixD3F4_PCIE_LINK_CNTL3 0xa00009d
+#define ixD3F4_PCIE_LANE_ERROR_STATUS 0xa00009e
+#define ixD3F4_PCIE_LANE_0_EQUALIZATION_CNTL 0xa00009f
+#define ixD3F4_PCIE_LANE_1_EQUALIZATION_CNTL 0xa00009f
+#define ixD3F4_PCIE_LANE_2_EQUALIZATION_CNTL 0xa0000a0
+#define ixD3F4_PCIE_LANE_3_EQUALIZATION_CNTL 0xa0000a0
+#define ixD3F4_PCIE_LANE_4_EQUALIZATION_CNTL 0xa0000a1
+#define ixD3F4_PCIE_LANE_5_EQUALIZATION_CNTL 0xa0000a1
+#define ixD3F4_PCIE_LANE_6_EQUALIZATION_CNTL 0xa0000a2
+#define ixD3F4_PCIE_LANE_7_EQUALIZATION_CNTL 0xa0000a2
+#define ixD3F4_PCIE_LANE_8_EQUALIZATION_CNTL 0xa0000a3
+#define ixD3F4_PCIE_LANE_9_EQUALIZATION_CNTL 0xa0000a3
+#define ixD3F4_PCIE_LANE_10_EQUALIZATION_CNTL 0xa0000a4
+#define ixD3F4_PCIE_LANE_11_EQUALIZATION_CNTL 0xa0000a4
+#define ixD3F4_PCIE_LANE_12_EQUALIZATION_CNTL 0xa0000a5
+#define ixD3F4_PCIE_LANE_13_EQUALIZATION_CNTL 0xa0000a5
+#define ixD3F4_PCIE_LANE_14_EQUALIZATION_CNTL 0xa0000a6
+#define ixD3F4_PCIE_LANE_15_EQUALIZATION_CNTL 0xa0000a6
+#define ixD3F4_PCIE_ACS_ENH_CAP_LIST 0xa0000a8
+#define ixD3F4_PCIE_ACS_CAP 0xa0000a9
+#define ixD3F4_PCIE_ACS_CNTL 0xa0000a9
+#define ixD3F4_PCIE_MC_ENH_CAP_LIST 0xa0000bc
+#define ixD3F4_PCIE_MC_CAP 0xa0000bd
+#define ixD3F4_PCIE_MC_CNTL 0xa0000bd
+#define ixD3F4_PCIE_MC_ADDR0 0xa0000be
+#define ixD3F4_PCIE_MC_ADDR1 0xa0000bf
+#define ixD3F4_PCIE_MC_RCV0 0xa0000c0
+#define ixD3F4_PCIE_MC_RCV1 0xa0000c1
+#define ixD3F4_PCIE_MC_BLOCK_ALL0 0xa0000c2
+#define ixD3F4_PCIE_MC_BLOCK_ALL1 0xa0000c3
+#define ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_0 0xa0000c4
+#define ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_1 0xa0000c5
+#define ixD3F4_PCIE_MC_OVERLAY_BAR0 0xa0000c6
+#define ixD3F4_PCIE_MC_OVERLAY_BAR1 0xa0000c7
+#define ixD3F5_PCIE_PORT_INDEX 0xb000038
+#define ixD3F5_PCIE_PORT_DATA 0xb000039
+#define ixD3F5_PCIEP_RESERVED 0x0
+#define ixD3F5_PCIEP_SCRATCH 0x1
+#define ixD3F5_PCIEP_HW_DEBUG 0x2
+#define ixD3F5_PCIEP_PORT_CNTL 0x10
+#define ixD3F5_PCIE_TX_CNTL 0x20
+#define ixD3F5_PCIE_TX_REQUESTER_ID 0x21
+#define ixD3F5_PCIE_TX_VENDOR_SPECIFIC 0x22
+#define ixD3F5_PCIE_TX_REQUEST_NUM_CNTL 0x23
+#define ixD3F5_PCIE_TX_SEQ 0x24
+#define ixD3F5_PCIE_TX_REPLAY 0x25
+#define ixD3F5_PCIE_TX_ACK_LATENCY_LIMIT 0x26
+#define ixD3F5_PCIE_TX_CREDITS_ADVT_P 0x30
+#define ixD3F5_PCIE_TX_CREDITS_ADVT_NP 0x31
+#define ixD3F5_PCIE_TX_CREDITS_ADVT_CPL 0x32
+#define ixD3F5_PCIE_TX_CREDITS_INIT_P 0x33
+#define ixD3F5_PCIE_TX_CREDITS_INIT_NP 0x34
+#define ixD3F5_PCIE_TX_CREDITS_INIT_CPL 0x35
+#define ixD3F5_PCIE_TX_CREDITS_STATUS 0x36
+#define ixD3F5_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37
+#define ixD3F5_PCIE_P_PORT_LANE_STATUS 0x50
+#define ixD3F5_PCIE_FC_P 0x60
+#define ixD3F5_PCIE_FC_NP 0x61
+#define ixD3F5_PCIE_FC_CPL 0x62
+#define ixD3F5_PCIE_ERR_CNTL 0x6a
+#define ixD3F5_PCIE_RX_CNTL 0x70
+#define ixD3F5_PCIE_RX_EXPECTED_SEQNUM 0x71
+#define ixD3F5_PCIE_RX_VENDOR_SPECIFIC 0x72
+#define ixD3F5_PCIE_RX_CNTL3 0x74
+#define ixD3F5_PCIE_RX_CREDITS_ALLOCATED_P 0x80
+#define ixD3F5_PCIE_RX_CREDITS_ALLOCATED_NP 0x81
+#define ixD3F5_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82
+#define ixD3F5_PCIEP_ERROR_INJECT_PHYSICAL 0x83
+#define ixD3F5_PCIEP_ERROR_INJECT_TRANSACTION 0x84
+#define ixD3F5_PCIE_LC_CNTL 0xa0
+#define ixD3F5_PCIE_LC_CNTL2 0xb1
+#define ixD3F5_PCIE_LC_CNTL3 0xb5
+#define ixD3F5_PCIE_LC_CNTL4 0xb6
+#define ixD3F5_PCIE_LC_CNTL5 0xb7
+#define ixD3F5_PCIE_LC_CNTL6 0xbb
+#define ixD3F5_PCIE_LC_BW_CHANGE_CNTL 0xb2
+#define ixD3F5_PCIE_LC_TRAINING_CNTL 0xa1
+#define ixD3F5_PCIE_LC_LINK_WIDTH_CNTL 0xa2
+#define ixD3F5_PCIE_LC_N_FTS_CNTL 0xa3
+#define ixD3F5_PCIE_LC_SPEED_CNTL 0xa4
+#define ixD3F5_PCIE_LC_CDR_CNTL 0xb3
+#define ixD3F5_PCIE_LC_LANE_CNTL 0xb4
+#define ixD3F5_PCIE_LC_FORCE_COEFF 0xb8
+#define ixD3F5_PCIE_LC_BEST_EQ_SETTINGS 0xb9
+#define ixD3F5_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba
+#define ixD3F5_PCIE_LC_STATE0 0xa5
+#define ixD3F5_PCIE_LC_STATE1 0xa6
+#define ixD3F5_PCIE_LC_STATE2 0xa7
+#define ixD3F5_PCIE_LC_STATE3 0xa8
+#define ixD3F5_PCIE_LC_STATE4 0xa9
+#define ixD3F5_PCIE_LC_STATE5 0xaa
+#define ixD3F5_PCIEP_STRAP_LC 0xc0
+#define ixD3F5_PCIEP_STRAP_MISC 0xc1
+#define ixD3F5_PCIEP_BCH_ECC_CNTL 0xd0
+#define ixD3F5_PCIEP_HPGI_PRIVATE 0xd2
+#define ixD3F5_PCIEP_HPGI 0xda
+#define ixD3F5_VENDOR_ID 0xb000000
+#define ixD3F5_DEVICE_ID 0xb000000
+#define ixD3F5_COMMAND 0xb000001
+#define ixD3F5_STATUS 0xb000001
+#define ixD3F5_REVISION_ID 0xb000002
+#define ixD3F5_PROG_INTERFACE 0xb000002
+#define ixD3F5_SUB_CLASS 0xb000002
+#define ixD3F5_BASE_CLASS 0xb000002
+#define ixD3F5_CACHE_LINE 0xb000003
+#define ixD3F5_LATENCY 0xb000003
+#define ixD3F5_HEADER 0xb000003
+#define ixD3F5_BIST 0xb000003
+#define ixD3F5_SUB_BUS_NUMBER_LATENCY 0xb000006
+#define ixD3F5_IO_BASE_LIMIT 0xb000007
+#define ixD3F5_SECONDARY_STATUS 0xb000007
+#define ixD3F5_MEM_BASE_LIMIT 0xb000008
+#define ixD3F5_PREF_BASE_LIMIT 0xb000009
+#define ixD3F5_PREF_BASE_UPPER 0xb00000a
+#define ixD3F5_PREF_LIMIT_UPPER 0xb00000b
+#define ixD3F5_IO_BASE_LIMIT_HI 0xb00000c
+#define ixD3F5_IRQ_BRIDGE_CNTL 0xb00000f
+#define ixD3F5_CAP_PTR 0xb00000d
+#define ixD3F5_INTERRUPT_LINE 0xb00000f
+#define ixD3F5_INTERRUPT_PIN 0xb00000f
+#define ixD3F5_EXT_BRIDGE_CNTL 0xb000010
+#define ixD3F5_PMI_CAP_LIST 0xb000014
+#define ixD3F5_PMI_CAP 0xb000014
+#define ixD3F5_PMI_STATUS_CNTL 0xb000015
+#define ixD3F5_PCIE_CAP_LIST 0xb000016
+#define ixD3F5_PCIE_CAP 0xb000016
+#define ixD3F5_DEVICE_CAP 0xb000017
+#define ixD3F5_DEVICE_CNTL 0xb000018
+#define ixD3F5_DEVICE_STATUS 0xb000018
+#define ixD3F5_LINK_CAP 0xb000019
+#define ixD3F5_LINK_CNTL 0xb00001a
+#define ixD3F5_LINK_STATUS 0xb00001a
+#define ixD3F5_SLOT_CAP 0xb00001b
+#define ixD3F5_SLOT_CNTL 0xb00001c
+#define ixD3F5_SLOT_STATUS 0xb00001c
+#define ixD3F5_ROOT_CNTL 0xb00001d
+#define ixD3F5_ROOT_CAP 0xb00001d
+#define ixD3F5_ROOT_STATUS 0xb00001e
+#define ixD3F5_DEVICE_CAP2 0xb00001f
+#define ixD3F5_DEVICE_CNTL2 0xb000020
+#define ixD3F5_DEVICE_STATUS2 0xb000020
+#define ixD3F5_LINK_CAP2 0xb000021
+#define ixD3F5_LINK_CNTL2 0xb000022
+#define ixD3F5_LINK_STATUS2 0xb000022
+#define ixD3F5_SLOT_CAP2 0xb000023
+#define ixD3F5_SLOT_CNTL2 0xb000024
+#define ixD3F5_SLOT_STATUS2 0xb000024
+#define ixD3F5_MSI_CAP_LIST 0xb000028
+#define ixD3F5_MSI_MSG_CNTL 0xb000028
+#define ixD3F5_MSI_MSG_ADDR_LO 0xb000029
+#define ixD3F5_MSI_MSG_ADDR_HI 0xb00002a
+#define ixD3F5_MSI_MSG_DATA_64 0xb00002b
+#define ixD3F5_MSI_MSG_DATA 0xb00002a
+#define ixD3F5_SSID_CAP_LIST 0xb000030
+#define ixD3F5_SSID_CAP 0xb000031
+#define ixD3F5_MSI_MAP_CAP_LIST 0xb000032
+#define ixD3F5_MSI_MAP_CAP 0xb000032
+#define ixD3F5_MSI_MAP_ADDR_LO 0xb000033
+#define ixD3F5_MSI_MAP_ADDR_HI 0xb000034
+#define ixD3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xb000040
+#define ixD3F5_PCIE_VENDOR_SPECIFIC_HDR 0xb000041
+#define ixD3F5_PCIE_VENDOR_SPECIFIC1 0xb000042
+#define ixD3F5_PCIE_VENDOR_SPECIFIC2 0xb000043
+#define ixD3F5_PCIE_VC_ENH_CAP_LIST 0xb000044
+#define ixD3F5_PCIE_PORT_VC_CAP_REG1 0xb000045
+#define ixD3F5_PCIE_PORT_VC_CAP_REG2 0xb000046
+#define ixD3F5_PCIE_PORT_VC_CNTL 0xb000047
+#define ixD3F5_PCIE_PORT_VC_STATUS 0xb000047
+#define ixD3F5_PCIE_VC0_RESOURCE_CAP 0xb000048
+#define ixD3F5_PCIE_VC0_RESOURCE_CNTL 0xb000049
+#define ixD3F5_PCIE_VC0_RESOURCE_STATUS 0xb00004a
+#define ixD3F5_PCIE_VC1_RESOURCE_CAP 0xb00004b
+#define ixD3F5_PCIE_VC1_RESOURCE_CNTL 0xb00004c
+#define ixD3F5_PCIE_VC1_RESOURCE_STATUS 0xb00004d
+#define ixD3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xb000050
+#define ixD3F5_PCIE_DEV_SERIAL_NUM_DW1 0xb000051
+#define ixD3F5_PCIE_DEV_SERIAL_NUM_DW2 0xb000052
+#define ixD3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xb000054
+#define ixD3F5_PCIE_UNCORR_ERR_STATUS 0xb000055
+#define ixD3F5_PCIE_UNCORR_ERR_MASK 0xb000056
+#define ixD3F5_PCIE_UNCORR_ERR_SEVERITY 0xb000057
+#define ixD3F5_PCIE_CORR_ERR_STATUS 0xb000058
+#define ixD3F5_PCIE_CORR_ERR_MASK 0xb000059
+#define ixD3F5_PCIE_ADV_ERR_CAP_CNTL 0xb00005a
+#define ixD3F5_PCIE_HDR_LOG0 0xb00005b
+#define ixD3F5_PCIE_HDR_LOG1 0xb00005c
+#define ixD3F5_PCIE_HDR_LOG2 0xb00005d
+#define ixD3F5_PCIE_HDR_LOG3 0xb00005e
+#define ixD3F5_PCIE_ROOT_ERR_CMD 0xb00005f
+#define ixD3F5_PCIE_ROOT_ERR_STATUS 0xb000060
+#define ixD3F5_PCIE_ERR_SRC_ID 0xb000061
+#define ixD3F5_PCIE_TLP_PREFIX_LOG0 0xb000062
+#define ixD3F5_PCIE_TLP_PREFIX_LOG1 0xb000063
+#define ixD3F5_PCIE_TLP_PREFIX_LOG2 0xb000064
+#define ixD3F5_PCIE_TLP_PREFIX_LOG3 0xb000065
+#define ixD3F5_PCIE_SECONDARY_ENH_CAP_LIST 0xb00009c
+#define ixD3F5_PCIE_LINK_CNTL3 0xb00009d
+#define ixD3F5_PCIE_LANE_ERROR_STATUS 0xb00009e
+#define ixD3F5_PCIE_LANE_0_EQUALIZATION_CNTL 0xb00009f
+#define ixD3F5_PCIE_LANE_1_EQUALIZATION_CNTL 0xb00009f
+#define ixD3F5_PCIE_LANE_2_EQUALIZATION_CNTL 0xb0000a0
+#define ixD3F5_PCIE_LANE_3_EQUALIZATION_CNTL 0xb0000a0
+#define ixD3F5_PCIE_LANE_4_EQUALIZATION_CNTL 0xb0000a1
+#define ixD3F5_PCIE_LANE_5_EQUALIZATION_CNTL 0xb0000a1
+#define ixD3F5_PCIE_LANE_6_EQUALIZATION_CNTL 0xb0000a2
+#define ixD3F5_PCIE_LANE_7_EQUALIZATION_CNTL 0xb0000a2
+#define ixD3F5_PCIE_LANE_8_EQUALIZATION_CNTL 0xb0000a3
+#define ixD3F5_PCIE_LANE_9_EQUALIZATION_CNTL 0xb0000a3
+#define ixD3F5_PCIE_LANE_10_EQUALIZATION_CNTL 0xb0000a4
+#define ixD3F5_PCIE_LANE_11_EQUALIZATION_CNTL 0xb0000a4
+#define ixD3F5_PCIE_LANE_12_EQUALIZATION_CNTL 0xb0000a5
+#define ixD3F5_PCIE_LANE_13_EQUALIZATION_CNTL 0xb0000a5
+#define ixD3F5_PCIE_LANE_14_EQUALIZATION_CNTL 0xb0000a6
+#define ixD3F5_PCIE_LANE_15_EQUALIZATION_CNTL 0xb0000a6
+#define ixD3F5_PCIE_ACS_ENH_CAP_LIST 0xb0000a8
+#define ixD3F5_PCIE_ACS_CAP 0xb0000a9
+#define ixD3F5_PCIE_ACS_CNTL 0xb0000a9
+#define ixD3F5_PCIE_MC_ENH_CAP_LIST 0xb0000bc
+#define ixD3F5_PCIE_MC_CAP 0xb0000bd
+#define ixD3F5_PCIE_MC_CNTL 0xb0000bd
+#define ixD3F5_PCIE_MC_ADDR0 0xb0000be
+#define ixD3F5_PCIE_MC_ADDR1 0xb0000bf
+#define ixD3F5_PCIE_MC_RCV0 0xb0000c0
+#define ixD3F5_PCIE_MC_RCV1 0xb0000c1
+#define ixD3F5_PCIE_MC_BLOCK_ALL0 0xb0000c2
+#define ixD3F5_PCIE_MC_BLOCK_ALL1 0xb0000c3
+#define ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_0 0xb0000c4
+#define ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_1 0xb0000c5
+#define ixD3F5_PCIE_MC_OVERLAY_BAR0 0xb0000c6
+#define ixD3F5_PCIE_MC_OVERLAY_BAR1 0xb0000c7
+#define mmC_PCIE_INDEX 0x28
+#define mmPCIE_WRAPPER0_C_PCIE_INDEX 0x28
+#define mmPCIE_WRAPPER1_C_PCIE_INDEX 0x38
+#define mmC_PCIE_DATA 0x29
+#define mmPCIE_WRAPPER0_C_PCIE_DATA 0x29
+#define mmPCIE_WRAPPER1_C_PCIE_DATA 0x39
+#define mmRFE_SNOOP_RST 0x3c
+#define ixPSX80_WRP_BIF_STRAP_FEATURE_EN_1 0x1500000
+#define ixPSX80_WRP_BIF_STRAP_PI_CNTL 0x1500001
+#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_CORE 0x1500002
+#define ixPSX80_WRP_BIF_STRAP_LC_MISC_CORE 0x1500003
+#define ixPSX80_WRP_BIF_STRAP_ERROR_IGNORE 0x1500004
+#define ixPSX80_WRP_BIF_STRAP_TEST_DFT 0x1500005
+#define ixPSX80_WRP_BIF_STRAP_ID 0x1500006
+#define ixPSX80_WRP_BIF_STRAP_REV_ID 0x1500007
+#define ixPSX80_WRP_BIF_STRAP_I2C_CNTL 0x1500008
+#define ixPSX80_WRP_BIF_INT_CNTL 0x1500009
+#define ixPSX80_WRP_BIF_STRAP_ACS 0x150000a
+#define ixPSX80_WRP_BIF_STRAP_PM 0x150000b
+#define ixPSX80_WRP_BIF_STRAP_FEATURE_EN_2 0x150000c
+#define ixPSX80_WRP_BIF_SERIAL_NUM 0x1500045
+#define ixPSX80_WRP_BIF_SSID 0x1500046
+#define ixPSX80_WRP_BIF_LANE_EQUALIZATION_CNTL 0x1500050
+#define ixPSX80_WRP_PCIE_LINK_CONFIG 0x1500080
+#define ixPSX80_WRP_PCIE_HOLD_TRAINING_A 0x1500800
+#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A 0x1500801
+#define ixPSX80_WRP_BIF_STRAP_ASPM_A 0x1500802
+#define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_A 0x1500803
+#define ixPSX80_WRP_BIF_STRAP_MISC_PORT_A 0x1500804
+#define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_A 0x1500805
+#define ixPSX80_WRP_PCIE_PORT_IS_SB_A 0x1500813
+#define ixPSX80_WRP_PCIE_HOLD_TRAINING_B 0x1500900
+#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B 0x1500901
+#define ixPSX80_WRP_BIF_STRAP_ASPM_B 0x1500902
+#define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_B 0x1500903
+#define ixPSX80_WRP_BIF_STRAP_MISC_PORT_B 0x1500904
+#define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_B 0x1500905
+#define ixPSX80_WRP_PCIE_PORT_IS_SB_B 0x1500913
+#define ixPSX80_WRP_PCIE_HOLD_TRAINING_C 0x1500a00
+#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C 0x1500a01
+#define ixPSX80_WRP_BIF_STRAP_ASPM_C 0x1500a02
+#define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_C 0x1500a03
+#define ixPSX80_WRP_BIF_STRAP_MISC_PORT_C 0x1500a04
+#define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_C 0x1500a05
+#define ixPSX80_WRP_PCIE_PORT_IS_SB_C 0x1500a13
+#define ixPSX80_WRP_PCIE_HOLD_TRAINING_D 0x1500b00
+#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D 0x1500b01
+#define ixPSX80_WRP_BIF_STRAP_ASPM_D 0x1500b02
+#define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_D 0x1500b03
+#define ixPSX80_WRP_BIF_STRAP_MISC_PORT_D 0x1500b04
+#define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_D 0x1500b05
+#define ixPSX80_WRP_PCIE_PORT_IS_SB_D 0x1500b13
+#define ixPSX80_WRP_PCIE_HOLD_TRAINING_E 0x1500c00
+#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E 0x1500c01
+#define ixPSX80_WRP_BIF_STRAP_ASPM_E 0x1500c02
+#define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_E 0x1500c03
+#define ixPSX80_WRP_BIF_STRAP_MISC_PORT_E 0x1500c04
+#define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_E 0x1500c05
+#define ixPSX80_WRP_PCIE_PORT_IS_SB_E 0x1500c13
+#define ixPSX80_WRP_LNCNT_CONTROL 0x1508030
+#define ixPSX80_WRP_CFG_LNC_WINDOW 0x1508031
+#define ixPSX80_WRP_LNCNT_QUAN_THRD 0x1508032
+#define ixPSX80_WRP_LNCNT_WEIGHT 0x1508033
+#define ixPSX80_WRP_LNC_TOTAL_WACC 0x1508034
+#define ixPSX80_WRP_LNC_BW_WACC 0x1508035
+#define ixPSX80_WRP_LNC_CMN_WACC 0x1508036
+#define ixPSX80_WRP_PCIE_EFUSE 0x150fff0
+#define ixPSX80_WRP_PCIE_EFUSE2 0x150fff1
+#define ixPSX80_WRP_PCIE_EFUSE3 0x150fff2
+#define ixPSX80_WRP_PCIE_EFUSE4 0x150fff3
+#define ixPSX80_WRP_PCIE_EFUSE5 0x150fff4
+#define ixPSX80_WRP_PCIE_EFUSE6 0x150fff5
+#define ixPSX80_WRP_PCIE_EFUSE7 0x150fff6
+#define ixPSX80_WRP_PCIE_WRAP_SCRATCH1 0x1308001
+#define ixPSX80_WRP_PCIE_WRAP_SCRATCH2 0x1308002
+#define ixPSX80_WRP_PCIE_WRAP_REG_TARG_MISC 0x1308005
+#define ixPSX80_WRP_PCIE_WRAP_DTM_MISC 0x1308006
+#define ixPSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN 0x1308007
+#define ixPSX80_WRP_PCIE_WRAP_MISC 0x1308008
+#define ixPSX80_WRP_PCIE_WRAP_PIF_MISC 0x1308009
+#define ixPSX80_WRP_PCIE_RXDET_OVERRIDE 0x130800a
+#define ixPSX80_WRP_IMPCTL_CNTL_PIF0 0x1308070
+#define ixPSX80_WRP_REG_ADAPT_pciecore0_CONTROL 0x1308090
+#define ixPSX80_WRP_REG_ADAPT_pwregt_CONTROL 0x1308096
+#define ixPSX80_WRP_REG_ADAPT_pwregr_CONTROL 0x1308097
+#define ixPSX80_WRP_REG_ADAPT_pif0_CONTROL 0x1308098
+#define ixPSX80_WRP_BIOSTIMER_CMD 0x13080f0
+#define ixPSX80_WRP_BIOSTIMER_CNTL 0x13080f1
+#define ixPSX80_WRP_BIOSTIMER_DEBUG 0x13080f2
+#define ixPSX80_WRP_DTM_RX_BP_CNTL 0x130ffe0
+#define ixPSX80_WRP_DTM_CNTL 0x130ffe1
+#define ixPSX80_WRP_DTM_CNTL_LEGACY 0x130ffe2
+#define ixPSX80_WRP_DTM_STI_LCLK_CTRL 0x130ffe3
+#define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x 0x130ffe4
+#define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt 0x130ffe5
+#define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x 0x130ffe6
+#define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt 0x130ffe7
+#define ixPSX80_WRP_DELAYLINE_COMMAND 0x130ffd0
+#define ixPSX80_WRP_DELAYLINE_STATUS 0x130ffd1
+#define ixPSX81_WRP_BIF_STRAP_FEATURE_EN_1 0x1510000
+#define ixPSX81_WRP_BIF_STRAP_PI_CNTL 0x1510001
+#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_CORE 0x1510002
+#define ixPSX81_WRP_BIF_STRAP_LC_MISC_CORE 0x1510003
+#define ixPSX81_WRP_BIF_STRAP_ERROR_IGNORE 0x1510004
+#define ixPSX81_WRP_BIF_STRAP_TEST_DFT 0x1510005
+#define ixPSX81_WRP_BIF_STRAP_ID 0x1510006
+#define ixPSX81_WRP_BIF_STRAP_REV_ID 0x1510007
+#define ixPSX81_WRP_BIF_STRAP_I2C_CNTL 0x1510008
+#define ixPSX81_WRP_BIF_INT_CNTL 0x1510009
+#define ixPSX81_WRP_BIF_STRAP_ACS 0x151000a
+#define ixPSX81_WRP_BIF_STRAP_PM 0x151000b
+#define ixPSX81_WRP_BIF_STRAP_FEATURE_EN_2 0x151000c
+#define ixPSX81_WRP_BIF_SERIAL_NUM 0x1510045
+#define ixPSX81_WRP_BIF_SSID 0x1510046
+#define ixPSX81_WRP_BIF_LANE_EQUALIZATION_CNTL 0x1510050
+#define ixPSX81_WRP_PCIE_LINK_CONFIG 0x1510080
+#define ixPSX81_WRP_PCIE_HOLD_TRAINING_A 0x1510800
+#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A 0x1510801
+#define ixPSX81_WRP_BIF_STRAP_ASPM_A 0x1510802
+#define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_A 0x1510803
+#define ixPSX81_WRP_BIF_STRAP_MISC_PORT_A 0x1510804
+#define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_A 0x1510805
+#define ixPSX81_WRP_PCIE_PORT_IS_SB_A 0x1510813
+#define ixPSX81_WRP_PCIE_HOLD_TRAINING_B 0x1510900
+#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B 0x1510901
+#define ixPSX81_WRP_BIF_STRAP_ASPM_B 0x1510902
+#define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_B 0x1510903
+#define ixPSX81_WRP_BIF_STRAP_MISC_PORT_B 0x1510904
+#define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_B 0x1510905
+#define ixPSX81_WRP_PCIE_PORT_IS_SB_B 0x1510913
+#define ixPSX81_WRP_PCIE_HOLD_TRAINING_C 0x1510a00
+#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C 0x1510a01
+#define ixPSX81_WRP_BIF_STRAP_ASPM_C 0x1510a02
+#define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_C 0x1510a03
+#define ixPSX81_WRP_BIF_STRAP_MISC_PORT_C 0x1510a04
+#define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_C 0x1510a05
+#define ixPSX81_WRP_PCIE_PORT_IS_SB_C 0x1510a13
+#define ixPSX81_WRP_PCIE_HOLD_TRAINING_D 0x1510b00
+#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D 0x1510b01
+#define ixPSX81_WRP_BIF_STRAP_ASPM_D 0x1510b02
+#define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_D 0x1510b03
+#define ixPSX81_WRP_BIF_STRAP_MISC_PORT_D 0x1510b04
+#define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_D 0x1510b05
+#define ixPSX81_WRP_PCIE_PORT_IS_SB_D 0x1510b13
+#define ixPSX81_WRP_PCIE_HOLD_TRAINING_E 0x1510c00
+#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E 0x1510c01
+#define ixPSX81_WRP_BIF_STRAP_ASPM_E 0x1510c02
+#define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_E 0x1510c03
+#define ixPSX81_WRP_BIF_STRAP_MISC_PORT_E 0x1510c04
+#define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_E 0x1510c05
+#define ixPSX81_WRP_PCIE_PORT_IS_SB_E 0x1510c13
+#define ixPSX81_WRP_LNCNT_CONTROL 0x1518030
+#define ixPSX81_WRP_CFG_LNC_WINDOW 0x1518031
+#define ixPSX81_WRP_LNCNT_QUAN_THRD 0x1518032
+#define ixPSX81_WRP_LNCNT_WEIGHT 0x1518033
+#define ixPSX81_WRP_LNC_TOTAL_WACC 0x1518034
+#define ixPSX81_WRP_LNC_BW_WACC 0x1518035
+#define ixPSX81_WRP_LNC_CMN_WACC 0x1518036
+#define ixPSX81_WRP_PCIE_EFUSE 0x151fff0
+#define ixPSX81_WRP_PCIE_EFUSE2 0x151fff1
+#define ixPSX81_WRP_PCIE_EFUSE3 0x151fff2
+#define ixPSX81_WRP_PCIE_EFUSE4 0x151fff3
+#define ixPSX81_WRP_PCIE_EFUSE5 0x151fff4
+#define ixPSX81_WRP_PCIE_EFUSE6 0x151fff5
+#define ixPSX81_WRP_PCIE_EFUSE7 0x151fff6
+#define ixPSX81_WRP_PCIE_WRAP_SCRATCH1 0x1318001
+#define ixPSX81_WRP_PCIE_WRAP_SCRATCH2 0x1318002
+#define ixPSX81_WRP_PCIE_WRAP_REG_TARG_MISC 0x1318005
+#define ixPSX81_WRP_PCIE_WRAP_DTM_MISC 0x1318006
+#define ixPSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN 0x1318007
+#define ixPSX81_WRP_PCIE_WRAP_MISC 0x1318008
+#define ixPSX81_WRP_PCIE_WRAP_PIF_MISC 0x1318009
+#define ixPSX81_WRP_PCIE_RXDET_OVERRIDE 0x131800a
+#define ixPSX81_WRP_IMPCTL_CNTL_PIF0 0x1318070
+#define ixPSX81_WRP_REG_ADAPT_pciecore0_CONTROL 0x1318090
+#define ixPSX81_WRP_REG_ADAPT_pwregt_CONTROL 0x1318096
+#define ixPSX81_WRP_REG_ADAPT_pwregr_CONTROL 0x1318097
+#define ixPSX81_WRP_REG_ADAPT_pif0_CONTROL 0x1318098
+#define ixPSX81_WRP_BIOSTIMER_CMD 0x13180f0
+#define ixPSX81_WRP_BIOSTIMER_CNTL 0x13180f1
+#define ixPSX81_WRP_BIOSTIMER_DEBUG 0x13180f2
+#define ixPSX81_WRP_DTM_RX_BP_CNTL 0x131ffe0
+#define ixPSX81_WRP_DTM_CNTL 0x131ffe1
+#define ixPSX81_WRP_DTM_CNTL_LEGACY 0x131ffe2
+#define ixPSX81_WRP_DTM_STI_LCLK_CTRL 0x131ffe3
+#define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x 0x131ffe4
+#define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt 0x131ffe5
+#define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x 0x131ffe6
+#define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt 0x131ffe7
+#define ixPSX81_WRP_DELAYLINE_COMMAND 0x131ffd0
+#define ixPSX81_WRP_DELAYLINE_STATUS 0x131ffd1
+#define ixRFE_WARMRST_CNTL 0x1085164
+#define ixRFE_SOFTRST_CNTL 0x1080001
+#define ixRFE_IMPRST_CNTL 0x1085160
+#define ixRFE_CLIENT_SOFTRST_TRIGGER 0x1080004
+#define ixRFE_MASTER_SOFTRST_TRIGGER 0x1080005
+#define ixRFE_PWDN_COMMAND 0x1080010
+#define ixRFE_PWDN_STATUS 0x1080011
+#define ixRFE_MST_PCIEW0_CMDSTATUS 0x1080020
+#define ixRFE_MST_PCIEW1_CMDSTATUS 0x1080021
+#define ixRFE_MST_RWREG_RFEWRC_CMDSTATUS 0x1080022
+#define ixRFE_MST_TMOUT_STATUS 0x108003f
+#define ixRFE_IMPARBH_STATUS 0x1085140
+#define ixRFE_IMPARBH_CONTROL 0x1080083
+#define ixPSX80_BIF_PCIE_RESERVED 0x1400000
+#define ixPSX80_BIF_PCIE_SCRATCH 0x1400001
+#define ixPSX80_BIF_PCIE_HW_DEBUG 0x1400002
+#define ixPSX80_BIF_PCIE_RX_NUM_NAK 0x140000e
+#define ixPSX80_BIF_PCIE_RX_NUM_NAK_GENERATED 0x140000f
+#define ixPSX80_BIF_PCIE_CNTL 0x1400010
+#define ixPSX80_BIF_PCIE_CONFIG_CNTL 0x1400011
+#define ixPSX80_BIF_PCIE_DEBUG_CNTL 0x1400012
+#define ixPSX80_BIF_PCIE_CNTL2 0x140001c
+#define ixPSX80_BIF_PCIE_RX_CNTL2 0x140001d
+#define ixPSX80_BIF_PCIE_TX_F0_ATTR_CNTL 0x140001e
+#define ixPSX80_BIF_PCIE_CI_CNTL 0x1400020
+#define ixPSX80_BIF_PCIE_BUS_CNTL 0x1400021
+#define ixPSX80_BIF_PCIE_LC_STATE6 0x1400022
+#define ixPSX80_BIF_PCIE_LC_STATE7 0x1400023
+#define ixPSX80_BIF_PCIE_LC_STATE8 0x1400024
+#define ixPSX80_BIF_PCIE_LC_STATE9 0x1400025
+#define ixPSX80_BIF_PCIE_LC_STATE10 0x1400026
+#define ixPSX80_BIF_PCIE_LC_STATE11 0x1400027
+#define ixPSX80_BIF_PCIE_LC_STATUS1 0x1400028
+#define ixPSX80_BIF_PCIE_LC_STATUS2 0x1400029
+#define ixPSX80_BIF_PCIE_WPR_CNTL 0x1400030
+#define ixPSX80_BIF_PCIE_RX_LAST_TLP0 0x1400031
+#define ixPSX80_BIF_PCIE_RX_LAST_TLP1 0x1400032
+#define ixPSX80_BIF_PCIE_RX_LAST_TLP2 0x1400033
+#define ixPSX80_BIF_PCIE_RX_LAST_TLP3 0x1400034
+#define ixPSX80_BIF_PCIE_TX_LAST_TLP0 0x1400035
+#define ixPSX80_BIF_PCIE_TX_LAST_TLP1 0x1400036
+#define ixPSX80_BIF_PCIE_TX_LAST_TLP2 0x1400037
+#define ixPSX80_BIF_PCIE_TX_LAST_TLP3 0x1400038
+#define ixPSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND 0x140003a
+#define ixPSX80_BIF_PCIE_I2C_REG_DATA 0x140003b
+#define ixPSX80_BIF_PCIE_CFG_CNTL 0x140003c
+#define ixPSX80_BIF_PCIE_LC_PM_CNTL 0x140003d
+#define ixPSX80_BIF_PCIE_P_CNTL 0x1400040
+#define ixPSX80_BIF_PCIE_P_BUF_STATUS 0x1400041
+#define ixPSX80_BIF_PCIE_P_DECODER_STATUS 0x1400042
+#define ixPSX80_BIF_PCIE_P_MISC_STATUS 0x1400043
+#define ixPSX80_BIF_PCIE_P_RCV_L0S_FTS_DET 0x1400050
+#define ixPSX80_BIF_PCIE_PERF_COUNT_CNTL 0x1400080
+#define ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK 0x1400081
+#define ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK 0x1400082
+#define ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK 0x1400083
+#define ixPSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK 0x1400084
+#define ixPSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK 0x1400085
+#define ixPSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK 0x1400086
+#define ixPSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK 0x1400087
+#define ixPSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK 0x1400088
+#define ixPSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK 0x1400089
+#define ixPSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK 0x140008a
+#define ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK 0x140008b
+#define ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK 0x140008c
+#define ixPSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d
+#define ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e
+#define ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f
+#define ixPSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090
+#define ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091
+#define ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092
+#define ixPSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093
+#define ixPSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094
+#define ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK2 0x1400095
+#define ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK2 0x1400096
+#define ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK2 0x1400097
+#define ixPSX80_BIF_PCIE_STRAP_F0 0x14000b0
+#define ixPSX80_BIF_PCIE_STRAP_MISC 0x14000c0
+#define ixPSX80_BIF_PCIE_STRAP_MISC2 0x14000c1
+#define ixPSX80_BIF_PCIE_STRAP_PI 0x14000c2
+#define ixPSX80_BIF_PCIE_STRAP_I2C_BD 0x14000c4
+#define ixPSX80_BIF_PCIE_PRBS_CLR 0x14000c8
+#define ixPSX80_BIF_PCIE_PRBS_STATUS1 0x14000c9
+#define ixPSX80_BIF_PCIE_PRBS_STATUS2 0x14000ca
+#define ixPSX80_BIF_PCIE_PRBS_FREERUN 0x14000cb
+#define ixPSX80_BIF_PCIE_PRBS_MISC 0x14000cc
+#define ixPSX80_BIF_PCIE_PRBS_USER_PATTERN 0x14000cd
+#define ixPSX80_BIF_PCIE_PRBS_LO_BITCNT 0x14000ce
+#define ixPSX80_BIF_PCIE_PRBS_HI_BITCNT 0x14000cf
+#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_0 0x14000d0
+#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_1 0x14000d1
+#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_2 0x14000d2
+#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_3 0x14000d3
+#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_4 0x14000d4
+#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_5 0x14000d5
+#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_6 0x14000d6
+#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_7 0x14000d7
+#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_8 0x14000d8
+#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_9 0x14000d9
+#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_10 0x14000da
+#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_11 0x14000db
+#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_12 0x14000dc
+#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_13 0x14000dd
+#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_14 0x14000de
+#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_15 0x14000df
+#define ixPSX80_BIF_SWRST_COMMAND_STATUS 0x1400100
+#define ixPSX80_BIF_SWRST_GENERAL_CONTROL 0x1400101
+#define ixPSX80_BIF_SWRST_COMMAND_0 0x1400102
+#define ixPSX80_BIF_SWRST_COMMAND_1 0x1400103
+#define ixPSX80_BIF_SWRST_CONTROL_0 0x1400104
+#define ixPSX80_BIF_SWRST_CONTROL_1 0x1400105
+#define ixPSX80_BIF_SWRST_CONTROL_2 0x1400106
+#define ixPSX80_BIF_SWRST_CONTROL_3 0x1400107
+#define ixPSX80_BIF_SWRST_CONTROL_4 0x1400108
+#define ixPSX80_BIF_SWRST_CONTROL_5 0x1400109
+#define ixPSX80_BIF_SWRST_CONTROL_6 0x140010a
+#define ixPSX80_BIF_CPM_CONTROL 0x1400118
+#define ixPSX80_BIF_LM_CONTROL 0x1400120
+#define ixPSX80_BIF_LM_PCIETXMUX0 0x1400121
+#define ixPSX80_BIF_LM_PCIETXMUX1 0x1400122
+#define ixPSX80_BIF_LM_PCIETXMUX2 0x1400123
+#define ixPSX80_BIF_LM_PCIETXMUX3 0x1400124
+#define ixPSX80_BIF_LM_PCIERXMUX0 0x1400125
+#define ixPSX80_BIF_LM_PCIERXMUX1 0x1400126
+#define ixPSX80_BIF_LM_PCIERXMUX2 0x1400127
+#define ixPSX80_BIF_LM_PCIERXMUX3 0x1400128
+#define ixPSX80_BIF_LM_LANEENABLE 0x1400129
+#define ixPSX80_BIF_LM_PRBSCONTROL 0x140012a
+#define ixPSX80_BIF_LM_POWERCONTROL 0x140012b
+#define ixPSX80_BIF_LM_POWERCONTROL1 0x140012c
+#define ixPSX80_BIF_LM_POWERCONTROL2 0x140012d
+#define ixPSX80_BIF_LM_POWERCONTROL3 0x140012e
+#define ixPSX80_BIF_LM_POWERCONTROL4 0x140012f
+#define ixPSX81_BIF_PCIE_RESERVED 0x1410000
+#define ixPSX81_BIF_PCIE_SCRATCH 0x1410001
+#define ixPSX81_BIF_PCIE_HW_DEBUG 0x1410002
+#define ixPSX81_BIF_PCIE_RX_NUM_NAK 0x141000e
+#define ixPSX81_BIF_PCIE_RX_NUM_NAK_GENERATED 0x141000f
+#define ixPSX81_BIF_PCIE_CNTL 0x1410010
+#define ixPSX81_BIF_PCIE_CONFIG_CNTL 0x1410011
+#define ixPSX81_BIF_PCIE_DEBUG_CNTL 0x1410012
+#define ixPSX81_BIF_PCIE_CNTL2 0x141001c
+#define ixPSX81_BIF_PCIE_RX_CNTL2 0x141001d
+#define ixPSX81_BIF_PCIE_TX_F0_ATTR_CNTL 0x141001e
+#define ixPSX81_BIF_PCIE_CI_CNTL 0x1410020
+#define ixPSX81_BIF_PCIE_BUS_CNTL 0x1410021
+#define ixPSX81_BIF_PCIE_LC_STATE6 0x1410022
+#define ixPSX81_BIF_PCIE_LC_STATE7 0x1410023
+#define ixPSX81_BIF_PCIE_LC_STATE8 0x1410024
+#define ixPSX81_BIF_PCIE_LC_STATE9 0x1410025
+#define ixPSX81_BIF_PCIE_LC_STATE10 0x1410026
+#define ixPSX81_BIF_PCIE_LC_STATE11 0x1410027
+#define ixPSX81_BIF_PCIE_LC_STATUS1 0x1410028
+#define ixPSX81_BIF_PCIE_LC_STATUS2 0x1410029
+#define ixPSX81_BIF_PCIE_WPR_CNTL 0x1410030
+#define ixPSX81_BIF_PCIE_RX_LAST_TLP0 0x1410031
+#define ixPSX81_BIF_PCIE_RX_LAST_TLP1 0x1410032
+#define ixPSX81_BIF_PCIE_RX_LAST_TLP2 0x1410033
+#define ixPSX81_BIF_PCIE_RX_LAST_TLP3 0x1410034
+#define ixPSX81_BIF_PCIE_TX_LAST_TLP0 0x1410035
+#define ixPSX81_BIF_PCIE_TX_LAST_TLP1 0x1410036
+#define ixPSX81_BIF_PCIE_TX_LAST_TLP2 0x1410037
+#define ixPSX81_BIF_PCIE_TX_LAST_TLP3 0x1410038
+#define ixPSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND 0x141003a
+#define ixPSX81_BIF_PCIE_I2C_REG_DATA 0x141003b
+#define ixPSX81_BIF_PCIE_CFG_CNTL 0x141003c
+#define ixPSX81_BIF_PCIE_LC_PM_CNTL 0x141003d
+#define ixPSX81_BIF_PCIE_P_CNTL 0x1410040
+#define ixPSX81_BIF_PCIE_P_BUF_STATUS 0x1410041
+#define ixPSX81_BIF_PCIE_P_DECODER_STATUS 0x1410042
+#define ixPSX81_BIF_PCIE_P_MISC_STATUS 0x1410043
+#define ixPSX81_BIF_PCIE_P_RCV_L0S_FTS_DET 0x1410050
+#define ixPSX81_BIF_PCIE_PERF_COUNT_CNTL 0x1410080
+#define ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK 0x1410081
+#define ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK 0x1410082
+#define ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK 0x1410083
+#define ixPSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK 0x1410084
+#define ixPSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK 0x1410085
+#define ixPSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK 0x1410086
+#define ixPSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK 0x1410087
+#define ixPSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK 0x1410088
+#define ixPSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK 0x1410089
+#define ixPSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK 0x141008a
+#define ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK 0x141008b
+#define ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK 0x141008c
+#define ixPSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK 0x141008d
+#define ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK 0x141008e
+#define ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK 0x141008f
+#define ixPSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK 0x1410090
+#define ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1410091
+#define ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1410092
+#define ixPSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1410093
+#define ixPSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1410094
+#define ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK2 0x1410095
+#define ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK2 0x1410096
+#define ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK2 0x1410097
+#define ixPSX81_BIF_PCIE_STRAP_F0 0x14100b0
+#define ixPSX81_BIF_PCIE_STRAP_MISC 0x14100c0
+#define ixPSX81_BIF_PCIE_STRAP_MISC2 0x14100c1
+#define ixPSX81_BIF_PCIE_STRAP_PI 0x14100c2
+#define ixPSX81_BIF_PCIE_STRAP_I2C_BD 0x14100c4
+#define ixPSX81_BIF_PCIE_PRBS_CLR 0x14100c8
+#define ixPSX81_BIF_PCIE_PRBS_STATUS1 0x14100c9
+#define ixPSX81_BIF_PCIE_PRBS_STATUS2 0x14100ca
+#define ixPSX81_BIF_PCIE_PRBS_FREERUN 0x14100cb
+#define ixPSX81_BIF_PCIE_PRBS_MISC 0x14100cc
+#define ixPSX81_BIF_PCIE_PRBS_USER_PATTERN 0x14100cd
+#define ixPSX81_BIF_PCIE_PRBS_LO_BITCNT 0x14100ce
+#define ixPSX81_BIF_PCIE_PRBS_HI_BITCNT 0x14100cf
+#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_0 0x14100d0
+#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_1 0x14100d1
+#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_2 0x14100d2
+#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_3 0x14100d3
+#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_4 0x14100d4
+#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_5 0x14100d5
+#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_6 0x14100d6
+#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_7 0x14100d7
+#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_8 0x14100d8
+#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_9 0x14100d9
+#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_10 0x14100da
+#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_11 0x14100db
+#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_12 0x14100dc
+#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_13 0x14100dd
+#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_14 0x14100de
+#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_15 0x14100df
+#define ixPSX81_BIF_SWRST_COMMAND_STATUS 0x1410100
+#define ixPSX81_BIF_SWRST_GENERAL_CONTROL 0x1410101
+#define ixPSX81_BIF_SWRST_COMMAND_0 0x1410102
+#define ixPSX81_BIF_SWRST_COMMAND_1 0x1410103
+#define ixPSX81_BIF_SWRST_CONTROL_0 0x1410104
+#define ixPSX81_BIF_SWRST_CONTROL_1 0x1410105
+#define ixPSX81_BIF_SWRST_CONTROL_2 0x1410106
+#define ixPSX81_BIF_SWRST_CONTROL_3 0x1410107
+#define ixPSX81_BIF_SWRST_CONTROL_4 0x1410108
+#define ixPSX81_BIF_SWRST_CONTROL_5 0x1410109
+#define ixPSX81_BIF_SWRST_CONTROL_6 0x141010a
+#define ixPSX81_BIF_CPM_CONTROL 0x1410118
+#define ixPSX81_BIF_LM_CONTROL 0x1410120
+#define ixPSX81_BIF_LM_PCIETXMUX0 0x1410121
+#define ixPSX81_BIF_LM_PCIETXMUX1 0x1410122
+#define ixPSX81_BIF_LM_PCIETXMUX2 0x1410123
+#define ixPSX81_BIF_LM_PCIETXMUX3 0x1410124
+#define ixPSX81_BIF_LM_PCIERXMUX0 0x1410125
+#define ixPSX81_BIF_LM_PCIERXMUX1 0x1410126
+#define ixPSX81_BIF_LM_PCIERXMUX2 0x1410127
+#define ixPSX81_BIF_LM_PCIERXMUX3 0x1410128
+#define ixPSX81_BIF_LM_LANEENABLE 0x1410129
+#define ixPSX81_BIF_LM_PRBSCONTROL 0x141012a
+#define ixPSX81_BIF_LM_POWERCONTROL 0x141012b
+#define ixPSX81_BIF_LM_POWERCONTROL1 0x141012c
+#define ixPSX81_BIF_LM_POWERCONTROL2 0x141012d
+#define ixPSX81_BIF_LM_POWERCONTROL3 0x141012e
+#define ixPSX81_BIF_LM_POWERCONTROL4 0x141012f
+#define ixPSX80_PHY0_COM_COMMON_FUSE1 0x1206200
+#define ixPSX80_PHY0_COM_COMMON_FUSE2 0x1206201
+#define ixPSX80_PHY0_COM_COMMON_FUSE3 0x1206202
+#define ixPSX80_PHY0_COM_COMMON_ELECIDLE 0x1206204
+#define ixPSX80_PHY0_COM_COMMON_DFX 0x1206205
+#define ixPSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM 0x1206206
+#define ixPSX80_PHY0_COM_COMMON_SELDEEMPH35 0x1206207
+#define ixPSX80_PHY0_COM_COMMON_SELDEEMPH60 0x1206208
+#define ixPSX80_PHY0_COM_COMMON_LANE_PWRMGMT 0x1206209
+#define ixPSX80_PHY0_COM_COMMON_ADAPTCTL1 0x120620a
+#define ixPSX80_PHY0_COM_COMMON_ADAPTCTL2 0x120620b
+#define ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL 0x120620c
+#define ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1 0x120620d
+#define ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL 0x120620e
+#define ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1 0x120620f
+#define ixPSX80_PHY0_COM_COMMON_ADAPT_DBG1 0x1206210
+#define ixPSX80_PHY0_COM_COMMON_LNCNTRL 0x1206211
+#define ixPSX80_PHY0_COM_COMMON_TXTESTDEBUG 0x1206212
+#define ixPSX80_PHY0_COM_COMMON_RXTESTDEBUG 0x1206213
+#define ixPSX80_PHY0_COM_COMMON_CDR_PHCTL 0x1206214
+#define ixPSX80_PHY0_COM_COMMON_CDR_FRCTL 0x1206215
+#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST 0x120fe00
+#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0 0x1200000
+#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1 0x1200100
+#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2 0x1200200
+#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3 0x1200300
+#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4 0x1200400
+#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5 0x1200500
+#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6 0x1200600
+#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7 0x1200700
+#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST 0x120fe01
+#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0 0x1200001
+#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1 0x1200101
+#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2 0x1200201
+#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3 0x1200301
+#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4 0x1200401
+#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5 0x1200501
+#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6 0x1200601
+#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7 0x1200701
+#define ixPSX80_PHY0_RX_RX_CTL_BROADCAST 0x120fe02
+#define ixPSX80_PHY0_RX_RX_CTL_LANE0 0x1200002
+#define ixPSX80_PHY0_RX_RX_CTL_LANE1 0x1200102
+#define ixPSX80_PHY0_RX_RX_CTL_LANE2 0x1200202
+#define ixPSX80_PHY0_RX_RX_CTL_LANE3 0x1200302
+#define ixPSX80_PHY0_RX_RX_CTL_LANE4 0x1200402
+#define ixPSX80_PHY0_RX_RX_CTL_LANE5 0x1200502
+#define ixPSX80_PHY0_RX_RX_CTL_LANE6 0x1200602
+#define ixPSX80_PHY0_RX_RX_CTL_LANE7 0x1200702
+#define ixPSX80_PHY0_RX_DLL_CTL_BROADCAST 0x120fe03
+#define ixPSX80_PHY0_RX_DLL_CTL_LANE0 0x1200003
+#define ixPSX80_PHY0_RX_DLL_CTL_LANE1 0x1200103
+#define ixPSX80_PHY0_RX_DLL_CTL_LANE2 0x1200203
+#define ixPSX80_PHY0_RX_DLL_CTL_LANE3 0x1200303
+#define ixPSX80_PHY0_RX_DLL_CTL_LANE4 0x1200403
+#define ixPSX80_PHY0_RX_DLL_CTL_LANE5 0x1200503
+#define ixPSX80_PHY0_RX_DLL_CTL_LANE6 0x1200603
+#define ixPSX80_PHY0_RX_DLL_CTL_LANE7 0x1200703
+#define ixPSX80_PHY0_RX_RXTEST_REGS_BROADCAST 0x120fe04
+#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE0 0x1200004
+#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE1 0x1200104
+#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE2 0x1200204
+#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE3 0x1200304
+#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE4 0x1200404
+#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE5 0x1200504
+#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE6 0x1200604
+#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE7 0x1200704
+#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST 0x120fe05
+#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0 0x1200005
+#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1 0x1200105
+#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2 0x1200205
+#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3 0x1200305
+#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4 0x1200405
+#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5 0x1200505
+#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6 0x1200605
+#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7 0x1200705
+#define ixPSX80_PHY0_RX_ADAPTCTL_BROADCAST 0x120fe0a
+#define ixPSX80_PHY0_RX_ADAPTCTL_LANE0 0x120000a
+#define ixPSX80_PHY0_RX_ADAPTCTL_LANE1 0x120010a
+#define ixPSX80_PHY0_RX_ADAPTCTL_LANE2 0x120020a
+#define ixPSX80_PHY0_RX_ADAPTCTL_LANE3 0x120030a
+#define ixPSX80_PHY0_RX_ADAPTCTL_LANE4 0x120040a
+#define ixPSX80_PHY0_RX_ADAPTCTL_LANE5 0x120050a
+#define ixPSX80_PHY0_RX_ADAPTCTL_LANE6 0x120060a
+#define ixPSX80_PHY0_RX_ADAPTCTL_LANE7 0x120070a
+#define ixPSX80_PHY0_RX_FOMCALCCTL_BROADCAST 0x120fe0b
+#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE0 0x120000b
+#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE1 0x120010b
+#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE2 0x120020b
+#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE3 0x120030b
+#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE4 0x120040b
+#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE5 0x120050b
+#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE6 0x120060b
+#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE7 0x120070b
+#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST 0x120fe0c
+#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0 0x120000c
+#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1 0x120010c
+#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2 0x120020c
+#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3 0x120030c
+#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4 0x120040c
+#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5 0x120050c
+#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6 0x120060c
+#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7 0x120070c
+#define ixPSX80_PHY0_RX_DBG_BYP_EN_BROADCAST 0x120fe0d
+#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE0 0x120000d
+#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE1 0x120010d
+#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE2 0x120020d
+#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE3 0x120030d
+#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE4 0x120040d
+#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE5 0x120050d
+#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE6 0x120060d
+#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE7 0x120070d
+#define ixPSX80_PHY0_RX_ADAPTDBG1_BROADCAST 0x120fe0e
+#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE0 0x120000e
+#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE1 0x120010e
+#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE2 0x120020e
+#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE3 0x120030e
+#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE4 0x120040e
+#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE5 0x120050e
+#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE6 0x120060e
+#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE7 0x120070e
+#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST 0x120ff00
+#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0 0x1202000
+#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1 0x1202100
+#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2 0x1202200
+#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3 0x1202300
+#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4 0x1202400
+#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5 0x1202500
+#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6 0x1202600
+#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7 0x1202700
+#define ixPSX80_PHY0_TX_DFX_BROADCAST 0x120ff01
+#define ixPSX80_PHY0_TX_DFX_LANE0 0x1202001
+#define ixPSX80_PHY0_TX_DFX_LANE1 0x1202101
+#define ixPSX80_PHY0_TX_DFX_LANE2 0x1202201
+#define ixPSX80_PHY0_TX_DFX_LANE3 0x1202301
+#define ixPSX80_PHY0_TX_DFX_LANE4 0x1202401
+#define ixPSX80_PHY0_TX_DFX_LANE5 0x1202501
+#define ixPSX80_PHY0_TX_DFX_LANE6 0x1202601
+#define ixPSX80_PHY0_TX_DFX_LANE7 0x1202701
+#define ixPSX80_PHY0_TX_DEEMPH_BROADCAST 0x120ff02
+#define ixPSX80_PHY0_TX_DEEMPH_LANE0 0x1202002
+#define ixPSX80_PHY0_TX_DEEMPH_LANE1 0x1202102
+#define ixPSX80_PHY0_TX_DEEMPH_LANE2 0x1202202
+#define ixPSX80_PHY0_TX_DEEMPH_LANE3 0x1202302
+#define ixPSX80_PHY0_TX_DEEMPH_LANE4 0x1202402
+#define ixPSX80_PHY0_TX_DEEMPH_LANE5 0x1202502
+#define ixPSX80_PHY0_TX_DEEMPH_LANE6 0x1202602
+#define ixPSX80_PHY0_TX_DEEMPH_LANE7 0x1202702
+#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST 0x120ff03
+#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE0 0x1202003
+#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE1 0x1202103
+#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE2 0x1202203
+#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE3 0x1202303
+#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE4 0x1202403
+#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE5 0x1202503
+#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE6 0x1202603
+#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE7 0x1202703
+#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST 0x120ff04
+#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0 0x1202004
+#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1 0x1202104
+#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2 0x1202204
+#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3 0x1202304
+#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4 0x1202404
+#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5 0x1202504
+#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6 0x1202604
+#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7 0x1202704
+#define ixPSX80_PHY0_TX_TXCNTRL_BROADCAST 0x120ff06
+#define ixPSX80_PHY0_TX_TXCNTRL_LANE0 0x1202006
+#define ixPSX80_PHY0_TX_TXCNTRL_LANE1 0x1202106
+#define ixPSX80_PHY0_TX_TXCNTRL_LANE2 0x1202206
+#define ixPSX80_PHY0_TX_TXCNTRL_LANE3 0x1202306
+#define ixPSX80_PHY0_TX_TXCNTRL_LANE4 0x1202406
+#define ixPSX80_PHY0_TX_TXCNTRL_LANE5 0x1202506
+#define ixPSX80_PHY0_TX_TXCNTRL_LANE6 0x1202606
+#define ixPSX80_PHY0_TX_TXCNTRL_LANE7 0x1202706
+#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST 0x120ff07
+#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x1202007
+#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x1202107
+#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x1202207
+#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x1202307
+#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4 0x1202407
+#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5 0x1202507
+#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6 0x1202607
+#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7 0x1202707
+#define ixPSX80_PHY0_HTPLL_ROPLL_PowerDownEn 0x1204180
+#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllControlExt 0x1204101
+#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllControl 0x1204102
+#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1 0x1204103
+#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2 0x1204104
+#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode 0x1204105
+#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl 0x1204108
+#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3 0x1204109
+#define ixPSX80_PHY0_HTPLL_ROPLL_PciFuseProcess 0x120410a
+#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4 0x120410b
+#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5 0x120410c
+#define ixPSX80_PHY0_LCPLL_LCPLL_PowerDownEn 0x1204080
+#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllControlExt 0x1204001
+#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllControl 0x1204002
+#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1 0x1204003
+#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2 0x1204004
+#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode 0x1204005
+#define ixPSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl 0x1204007
+#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl 0x1204008
+#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3 0x1204009
+#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4 0x120400b
+#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5 0x120400c
+#define ixPSX81_PHY0_COM_COMMON_FUSE1 0x1216200
+#define ixPSX81_PHY0_COM_COMMON_FUSE2 0x1216201
+#define ixPSX81_PHY0_COM_COMMON_FUSE3 0x1216202
+#define ixPSX81_PHY0_COM_COMMON_ELECIDLE 0x1216204
+#define ixPSX81_PHY0_COM_COMMON_DFX 0x1216205
+#define ixPSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM 0x1216206
+#define ixPSX81_PHY0_COM_COMMON_SELDEEMPH35 0x1216207
+#define ixPSX81_PHY0_COM_COMMON_SELDEEMPH60 0x1216208
+#define ixPSX81_PHY0_COM_COMMON_LANE_PWRMGMT 0x1216209
+#define ixPSX81_PHY0_COM_COMMON_ADAPTCTL1 0x121620a
+#define ixPSX81_PHY0_COM_COMMON_ADAPTCTL2 0x121620b
+#define ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL 0x121620c
+#define ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1 0x121620d
+#define ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL 0x121620e
+#define ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1 0x121620f
+#define ixPSX81_PHY0_COM_COMMON_ADAPT_DBG1 0x1216210
+#define ixPSX81_PHY0_COM_COMMON_LNCNTRL 0x1216211
+#define ixPSX81_PHY0_COM_COMMON_TXTESTDEBUG 0x1216212
+#define ixPSX81_PHY0_COM_COMMON_RXTESTDEBUG 0x1216213
+#define ixPSX81_PHY0_COM_COMMON_CDR_PHCTL 0x1216214
+#define ixPSX81_PHY0_COM_COMMON_CDR_FRCTL 0x1216215
+#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST 0x121fe00
+#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0 0x1210000
+#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1 0x1210100
+#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2 0x1210200
+#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3 0x1210300
+#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4 0x1210400
+#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5 0x1210500
+#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6 0x1210600
+#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7 0x1210700
+#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST 0x121fe01
+#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0 0x1210001
+#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1 0x1210101
+#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2 0x1210201
+#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3 0x1210301
+#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4 0x1210401
+#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5 0x1210501
+#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6 0x1210601
+#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7 0x1210701
+#define ixPSX81_PHY0_RX_RX_CTL_BROADCAST 0x121fe02
+#define ixPSX81_PHY0_RX_RX_CTL_LANE0 0x1210002
+#define ixPSX81_PHY0_RX_RX_CTL_LANE1 0x1210102
+#define ixPSX81_PHY0_RX_RX_CTL_LANE2 0x1210202
+#define ixPSX81_PHY0_RX_RX_CTL_LANE3 0x1210302
+#define ixPSX81_PHY0_RX_RX_CTL_LANE4 0x1210402
+#define ixPSX81_PHY0_RX_RX_CTL_LANE5 0x1210502
+#define ixPSX81_PHY0_RX_RX_CTL_LANE6 0x1210602
+#define ixPSX81_PHY0_RX_RX_CTL_LANE7 0x1210702
+#define ixPSX81_PHY0_RX_DLL_CTL_BROADCAST 0x121fe03
+#define ixPSX81_PHY0_RX_DLL_CTL_LANE0 0x1210003
+#define ixPSX81_PHY0_RX_DLL_CTL_LANE1 0x1210103
+#define ixPSX81_PHY0_RX_DLL_CTL_LANE2 0x1210203
+#define ixPSX81_PHY0_RX_DLL_CTL_LANE3 0x1210303
+#define ixPSX81_PHY0_RX_DLL_CTL_LANE4 0x1210403
+#define ixPSX81_PHY0_RX_DLL_CTL_LANE5 0x1210503
+#define ixPSX81_PHY0_RX_DLL_CTL_LANE6 0x1210603
+#define ixPSX81_PHY0_RX_DLL_CTL_LANE7 0x1210703
+#define ixPSX81_PHY0_RX_RXTEST_REGS_BROADCAST 0x121fe04
+#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE0 0x1210004
+#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE1 0x1210104
+#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE2 0x1210204
+#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE3 0x1210304
+#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE4 0x1210404
+#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE5 0x1210504
+#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE6 0x1210604
+#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE7 0x1210704
+#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST 0x121fe05
+#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0 0x1210005
+#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1 0x1210105
+#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2 0x1210205
+#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3 0x1210305
+#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4 0x1210405
+#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5 0x1210505
+#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6 0x1210605
+#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7 0x1210705
+#define ixPSX81_PHY0_RX_ADAPTCTL_BROADCAST 0x121fe0a
+#define ixPSX81_PHY0_RX_ADAPTCTL_LANE0 0x121000a
+#define ixPSX81_PHY0_RX_ADAPTCTL_LANE1 0x121010a
+#define ixPSX81_PHY0_RX_ADAPTCTL_LANE2 0x121020a
+#define ixPSX81_PHY0_RX_ADAPTCTL_LANE3 0x121030a
+#define ixPSX81_PHY0_RX_ADAPTCTL_LANE4 0x121040a
+#define ixPSX81_PHY0_RX_ADAPTCTL_LANE5 0x121050a
+#define ixPSX81_PHY0_RX_ADAPTCTL_LANE6 0x121060a
+#define ixPSX81_PHY0_RX_ADAPTCTL_LANE7 0x121070a
+#define ixPSX81_PHY0_RX_FOMCALCCTL_BROADCAST 0x121fe0b
+#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE0 0x121000b
+#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE1 0x121010b
+#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE2 0x121020b
+#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE3 0x121030b
+#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE4 0x121040b
+#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE5 0x121050b
+#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE6 0x121060b
+#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE7 0x121070b
+#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST 0x121fe0c
+#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0 0x121000c
+#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1 0x121010c
+#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2 0x121020c
+#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3 0x121030c
+#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4 0x121040c
+#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5 0x121050c
+#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6 0x121060c
+#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7 0x121070c
+#define ixPSX81_PHY0_RX_DBG_BYP_EN_BROADCAST 0x121fe0d
+#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE0 0x121000d
+#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE1 0x121010d
+#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE2 0x121020d
+#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE3 0x121030d
+#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE4 0x121040d
+#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE5 0x121050d
+#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE6 0x121060d
+#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE7 0x121070d
+#define ixPSX81_PHY0_RX_ADAPTDBG1_BROADCAST 0x121fe0e
+#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE0 0x121000e
+#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE1 0x121010e
+#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE2 0x121020e
+#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE3 0x121030e
+#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE4 0x121040e
+#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE5 0x121050e
+#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE6 0x121060e
+#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE7 0x121070e
+#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST 0x121ff00
+#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0 0x1212000
+#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1 0x1212100
+#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2 0x1212200
+#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3 0x1212300
+#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4 0x1212400
+#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5 0x1212500
+#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6 0x1212600
+#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7 0x1212700
+#define ixPSX81_PHY0_TX_DFX_BROADCAST 0x121ff01
+#define ixPSX81_PHY0_TX_DFX_LANE0 0x1212001
+#define ixPSX81_PHY0_TX_DFX_LANE1 0x1212101
+#define ixPSX81_PHY0_TX_DFX_LANE2 0x1212201
+#define ixPSX81_PHY0_TX_DFX_LANE3 0x1212301
+#define ixPSX81_PHY0_TX_DFX_LANE4 0x1212401
+#define ixPSX81_PHY0_TX_DFX_LANE5 0x1212501
+#define ixPSX81_PHY0_TX_DFX_LANE6 0x1212601
+#define ixPSX81_PHY0_TX_DFX_LANE7 0x1212701
+#define ixPSX81_PHY0_TX_DEEMPH_BROADCAST 0x121ff02
+#define ixPSX81_PHY0_TX_DEEMPH_LANE0 0x1212002
+#define ixPSX81_PHY0_TX_DEEMPH_LANE1 0x1212102
+#define ixPSX81_PHY0_TX_DEEMPH_LANE2 0x1212202
+#define ixPSX81_PHY0_TX_DEEMPH_LANE3 0x1212302
+#define ixPSX81_PHY0_TX_DEEMPH_LANE4 0x1212402
+#define ixPSX81_PHY0_TX_DEEMPH_LANE5 0x1212502
+#define ixPSX81_PHY0_TX_DEEMPH_LANE6 0x1212602
+#define ixPSX81_PHY0_TX_DEEMPH_LANE7 0x1212702
+#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST 0x121ff03
+#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE0 0x1212003
+#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE1 0x1212103
+#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE2 0x1212203
+#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE3 0x1212303
+#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE4 0x1212403
+#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE5 0x1212503
+#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE6 0x1212603
+#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE7 0x1212703
+#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST 0x121ff04
+#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0 0x1212004
+#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1 0x1212104
+#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2 0x1212204
+#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3 0x1212304
+#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4 0x1212404
+#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5 0x1212504
+#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6 0x1212604
+#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7 0x1212704
+#define ixPSX81_PHY0_TX_TXCNTRL_BROADCAST 0x121ff06
+#define ixPSX81_PHY0_TX_TXCNTRL_LANE0 0x1212006
+#define ixPSX81_PHY0_TX_TXCNTRL_LANE1 0x1212106
+#define ixPSX81_PHY0_TX_TXCNTRL_LANE2 0x1212206
+#define ixPSX81_PHY0_TX_TXCNTRL_LANE3 0x1212306
+#define ixPSX81_PHY0_TX_TXCNTRL_LANE4 0x1212406
+#define ixPSX81_PHY0_TX_TXCNTRL_LANE5 0x1212506
+#define ixPSX81_PHY0_TX_TXCNTRL_LANE6 0x1212606
+#define ixPSX81_PHY0_TX_TXCNTRL_LANE7 0x1212706
+#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST 0x121ff07
+#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x1212007
+#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x1212107
+#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x1212207
+#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x1212307
+#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4 0x1212407
+#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5 0x1212507
+#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6 0x1212607
+#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7 0x1212707
+#define ixPSX81_PHY0_HTPLL_ROPLL_PowerDownEn 0x1214180
+#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllControlExt 0x1214101
+#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllControl 0x1214102
+#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1 0x1214103
+#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2 0x1214104
+#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode 0x1214105
+#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl 0x1214108
+#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3 0x1214109
+#define ixPSX81_PHY0_HTPLL_ROPLL_PciFuseProcess 0x121410a
+#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4 0x121410b
+#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5 0x121410c
+#define ixPSX81_PHY0_LCPLL_LCPLL_PowerDownEn 0x1214080
+#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllControlExt 0x1214001
+#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllControl 0x1214002
+#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1 0x1214003
+#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2 0x1214004
+#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode 0x1214005
+#define ixPSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl 0x1214007
+#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl 0x1214008
+#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3 0x1214009
+#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4 0x121400b
+#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5 0x121400c
+#define ixPSX80_PIF0_SCRATCH 0x1100001
+#define ixPSX80_PIF0_HW_DEBUG 0x1100002
+#define ixPSX80_PIF0_STRAP_0 0x1100003
+#define ixPSX80_PIF0_CTRL 0x1100004
+#define ixPSX80_PIF0_TX_CTRL 0x1100008
+#define ixPSX80_PIF0_TX_CTRL2 0x1100009
+#define ixPSX80_PIF0_RX_CTRL 0x110000a
+#define ixPSX80_PIF0_RX_CTRL2 0x110000b
+#define ixPSX80_PIF0_GLB_OVRD 0x110000c
+#define ixPSX80_PIF0_GLB_OVRD2 0x110000d
+#define ixPSX80_PIF0_BIF_CMD_STATUS 0x1100010
+#define ixPSX80_PIF0_CMD_BUS_CTRL 0x1100011
+#define ixPSX80_PIF0_CMD_BUS_GLB_OVRD 0x1100013
+#define ixPSX80_PIF0_LANE0_OVRD 0x1100014
+#define ixPSX80_PIF0_LANE0_OVRD2 0x1100015
+#define ixPSX80_PIF0_LANE1_OVRD 0x1100016
+#define ixPSX80_PIF0_LANE1_OVRD2 0x1100017
+#define ixPSX80_PIF0_LANE2_OVRD 0x1100018
+#define ixPSX80_PIF0_LANE2_OVRD2 0x1100019
+#define ixPSX80_PIF0_LANE3_OVRD 0x110001a
+#define ixPSX80_PIF0_LANE3_OVRD2 0x110001b
+#define ixPSX80_PIF0_LANE4_OVRD 0x110001c
+#define ixPSX80_PIF0_LANE4_OVRD2 0x110001d
+#define ixPSX80_PIF0_LANE5_OVRD 0x110001e
+#define ixPSX80_PIF0_LANE5_OVRD2 0x110001f
+#define ixPSX80_PIF0_LANE6_OVRD 0x1100020
+#define ixPSX80_PIF0_LANE6_OVRD2 0x1100021
+#define ixPSX80_PIF0_LANE7_OVRD 0x1100022
+#define ixPSX80_PIF0_LANE7_OVRD2 0x1100023
+#define ixPSX81_PIF0_SCRATCH 0x1110001
+#define ixPSX81_PIF0_HW_DEBUG 0x1110002
+#define ixPSX81_PIF0_STRAP_0 0x1110003
+#define ixPSX81_PIF0_CTRL 0x1110004
+#define ixPSX81_PIF0_TX_CTRL 0x1110008
+#define ixPSX81_PIF0_TX_CTRL2 0x1110009
+#define ixPSX81_PIF0_RX_CTRL 0x111000a
+#define ixPSX81_PIF0_RX_CTRL2 0x111000b
+#define ixPSX81_PIF0_GLB_OVRD 0x111000c
+#define ixPSX81_PIF0_GLB_OVRD2 0x111000d
+#define ixPSX81_PIF0_BIF_CMD_STATUS 0x1110010
+#define ixPSX81_PIF0_CMD_BUS_CTRL 0x1110011
+#define ixPSX81_PIF0_CMD_BUS_GLB_OVRD 0x1110013
+#define ixPSX81_PIF0_LANE0_OVRD 0x1110014
+#define ixPSX81_PIF0_LANE0_OVRD2 0x1110015
+#define ixPSX81_PIF0_LANE1_OVRD 0x1110016
+#define ixPSX81_PIF0_LANE1_OVRD2 0x1110017
+#define ixPSX81_PIF0_LANE2_OVRD 0x1110018
+#define ixPSX81_PIF0_LANE2_OVRD2 0x1110019
+#define ixPSX81_PIF0_LANE3_OVRD 0x111001a
+#define ixPSX81_PIF0_LANE3_OVRD2 0x111001b
+#define ixPSX81_PIF0_LANE4_OVRD 0x111001c
+#define ixPSX81_PIF0_LANE4_OVRD2 0x111001d
+#define ixPSX81_PIF0_LANE5_OVRD 0x111001e
+#define ixPSX81_PIF0_LANE5_OVRD2 0x111001f
+#define ixPSX81_PIF0_LANE6_OVRD 0x1110020
+#define ixPSX81_PIF0_LANE6_OVRD2 0x1110021
+#define ixPSX81_PIF0_LANE7_OVRD 0x1110022
+#define ixPSX81_PIF0_LANE7_OVRD2 0x1110023
+
+#endif /* BIF_5_1_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_enum.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_enum.h
new file mode 100644
index 000000000000..d8d5ae0b341f
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_enum.h
@@ -0,0 +1,1068 @@
+/*
+ * BIF_5_1 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef BIF_5_1_ENUM_H
+#define BIF_5_1_ENUM_H
+
+typedef enum DebugBlockId {
+ DBG_BLOCK_ID_RESERVED = 0x0,
+ DBG_BLOCK_ID_DBG = 0x1,
+ DBG_BLOCK_ID_VMC = 0x2,
+ DBG_BLOCK_ID_PDMA = 0x3,
+ DBG_BLOCK_ID_CG = 0x4,
+ DBG_BLOCK_ID_SRBM = 0x5,
+ DBG_BLOCK_ID_GRBM = 0x6,
+ DBG_BLOCK_ID_RLC = 0x7,
+ DBG_BLOCK_ID_CSC = 0x8,
+ DBG_BLOCK_ID_SEM = 0x9,
+ DBG_BLOCK_ID_IH = 0xa,
+ DBG_BLOCK_ID_SC = 0xb,
+ DBG_BLOCK_ID_SQ = 0xc,
+ DBG_BLOCK_ID_UVDU = 0xd,
+ DBG_BLOCK_ID_SQA = 0xe,
+ DBG_BLOCK_ID_SDMA0 = 0xf,
+ DBG_BLOCK_ID_SDMA1 = 0x10,
+ DBG_BLOCK_ID_SPIM = 0x11,
+ DBG_BLOCK_ID_GDS = 0x12,
+ DBG_BLOCK_ID_VC0 = 0x13,
+ DBG_BLOCK_ID_VC1 = 0x14,
+ DBG_BLOCK_ID_PA0 = 0x15,
+ DBG_BLOCK_ID_PA1 = 0x16,
+ DBG_BLOCK_ID_CP0 = 0x17,
+ DBG_BLOCK_ID_CP1 = 0x18,
+ DBG_BLOCK_ID_CP2 = 0x19,
+ DBG_BLOCK_ID_XBR = 0x1a,
+ DBG_BLOCK_ID_UVDM = 0x1b,
+ DBG_BLOCK_ID_VGT0 = 0x1c,
+ DBG_BLOCK_ID_VGT1 = 0x1d,
+ DBG_BLOCK_ID_IA = 0x1e,
+ DBG_BLOCK_ID_SXM0 = 0x1f,
+ DBG_BLOCK_ID_SXM1 = 0x20,
+ DBG_BLOCK_ID_SCT0 = 0x21,
+ DBG_BLOCK_ID_SCT1 = 0x22,
+ DBG_BLOCK_ID_SPM0 = 0x23,
+ DBG_BLOCK_ID_SPM1 = 0x24,
+ DBG_BLOCK_ID_UNUSED0 = 0x25,
+ DBG_BLOCK_ID_UNUSED1 = 0x26,
+ DBG_BLOCK_ID_TCAA = 0x27,
+ DBG_BLOCK_ID_TCAB = 0x28,
+ DBG_BLOCK_ID_TCCA = 0x29,
+ DBG_BLOCK_ID_TCCB = 0x2a,
+ DBG_BLOCK_ID_MCC0 = 0x2b,
+ DBG_BLOCK_ID_MCC1 = 0x2c,
+ DBG_BLOCK_ID_MCC2 = 0x2d,
+ DBG_BLOCK_ID_MCC3 = 0x2e,
+ DBG_BLOCK_ID_SXS0 = 0x2f,
+ DBG_BLOCK_ID_SXS1 = 0x30,
+ DBG_BLOCK_ID_SXS2 = 0x31,
+ DBG_BLOCK_ID_SXS3 = 0x32,
+ DBG_BLOCK_ID_SXS4 = 0x33,
+ DBG_BLOCK_ID_SXS5 = 0x34,
+ DBG_BLOCK_ID_SXS6 = 0x35,
+ DBG_BLOCK_ID_SXS7 = 0x36,
+ DBG_BLOCK_ID_SXS8 = 0x37,
+ DBG_BLOCK_ID_SXS9 = 0x38,
+ DBG_BLOCK_ID_BCI0 = 0x39,
+ DBG_BLOCK_ID_BCI1 = 0x3a,
+ DBG_BLOCK_ID_BCI2 = 0x3b,
+ DBG_BLOCK_ID_BCI3 = 0x3c,
+ DBG_BLOCK_ID_MCB = 0x3d,
+ DBG_BLOCK_ID_UNUSED6 = 0x3e,
+ DBG_BLOCK_ID_SQA00 = 0x3f,
+ DBG_BLOCK_ID_SQA01 = 0x40,
+ DBG_BLOCK_ID_SQA02 = 0x41,
+ DBG_BLOCK_ID_SQA10 = 0x42,
+ DBG_BLOCK_ID_SQA11 = 0x43,
+ DBG_BLOCK_ID_SQA12 = 0x44,
+ DBG_BLOCK_ID_UNUSED7 = 0x45,
+ DBG_BLOCK_ID_UNUSED8 = 0x46,
+ DBG_BLOCK_ID_SQB00 = 0x47,
+ DBG_BLOCK_ID_SQB01 = 0x48,
+ DBG_BLOCK_ID_SQB10 = 0x49,
+ DBG_BLOCK_ID_SQB11 = 0x4a,
+ DBG_BLOCK_ID_SQ00 = 0x4b,
+ DBG_BLOCK_ID_SQ01 = 0x4c,
+ DBG_BLOCK_ID_SQ10 = 0x4d,
+ DBG_BLOCK_ID_SQ11 = 0x4e,
+ DBG_BLOCK_ID_CB00 = 0x4f,
+ DBG_BLOCK_ID_CB01 = 0x50,
+ DBG_BLOCK_ID_CB02 = 0x51,
+ DBG_BLOCK_ID_CB03 = 0x52,
+ DBG_BLOCK_ID_CB04 = 0x53,
+ DBG_BLOCK_ID_UNUSED9 = 0x54,
+ DBG_BLOCK_ID_UNUSED10 = 0x55,
+ DBG_BLOCK_ID_UNUSED11 = 0x56,
+ DBG_BLOCK_ID_CB10 = 0x57,
+ DBG_BLOCK_ID_CB11 = 0x58,
+ DBG_BLOCK_ID_CB12 = 0x59,
+ DBG_BLOCK_ID_CB13 = 0x5a,
+ DBG_BLOCK_ID_CB14 = 0x5b,
+ DBG_BLOCK_ID_UNUSED12 = 0x5c,
+ DBG_BLOCK_ID_UNUSED13 = 0x5d,
+ DBG_BLOCK_ID_UNUSED14 = 0x5e,
+ DBG_BLOCK_ID_TCP0 = 0x5f,
+ DBG_BLOCK_ID_TCP1 = 0x60,
+ DBG_BLOCK_ID_TCP2 = 0x61,
+ DBG_BLOCK_ID_TCP3 = 0x62,
+ DBG_BLOCK_ID_TCP4 = 0x63,
+ DBG_BLOCK_ID_TCP5 = 0x64,
+ DBG_BLOCK_ID_TCP6 = 0x65,
+ DBG_BLOCK_ID_TCP7 = 0x66,
+ DBG_BLOCK_ID_TCP8 = 0x67,
+ DBG_BLOCK_ID_TCP9 = 0x68,
+ DBG_BLOCK_ID_TCP10 = 0x69,
+ DBG_BLOCK_ID_TCP11 = 0x6a,
+ DBG_BLOCK_ID_TCP12 = 0x6b,
+ DBG_BLOCK_ID_TCP13 = 0x6c,
+ DBG_BLOCK_ID_TCP14 = 0x6d,
+ DBG_BLOCK_ID_TCP15 = 0x6e,
+ DBG_BLOCK_ID_TCP16 = 0x6f,
+ DBG_BLOCK_ID_TCP17 = 0x70,
+ DBG_BLOCK_ID_TCP18 = 0x71,
+ DBG_BLOCK_ID_TCP19 = 0x72,
+ DBG_BLOCK_ID_TCP20 = 0x73,
+ DBG_BLOCK_ID_TCP21 = 0x74,
+ DBG_BLOCK_ID_TCP22 = 0x75,
+ DBG_BLOCK_ID_TCP23 = 0x76,
+ DBG_BLOCK_ID_TCP_RESERVED0 = 0x77,
+ DBG_BLOCK_ID_TCP_RESERVED1 = 0x78,
+ DBG_BLOCK_ID_TCP_RESERVED2 = 0x79,
+ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a,
+ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b,
+ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c,
+ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d,
+ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e,
+ DBG_BLOCK_ID_DB00 = 0x7f,
+ DBG_BLOCK_ID_DB01 = 0x80,
+ DBG_BLOCK_ID_DB02 = 0x81,
+ DBG_BLOCK_ID_DB03 = 0x82,
+ DBG_BLOCK_ID_DB04 = 0x83,
+ DBG_BLOCK_ID_UNUSED15 = 0x84,
+ DBG_BLOCK_ID_UNUSED16 = 0x85,
+ DBG_BLOCK_ID_UNUSED17 = 0x86,
+ DBG_BLOCK_ID_DB10 = 0x87,
+ DBG_BLOCK_ID_DB11 = 0x88,
+ DBG_BLOCK_ID_DB12 = 0x89,
+ DBG_BLOCK_ID_DB13 = 0x8a,
+ DBG_BLOCK_ID_DB14 = 0x8b,
+ DBG_BLOCK_ID_UNUSED18 = 0x8c,
+ DBG_BLOCK_ID_UNUSED19 = 0x8d,
+ DBG_BLOCK_ID_UNUSED20 = 0x8e,
+ DBG_BLOCK_ID_TCC0 = 0x8f,
+ DBG_BLOCK_ID_TCC1 = 0x90,
+ DBG_BLOCK_ID_TCC2 = 0x91,
+ DBG_BLOCK_ID_TCC3 = 0x92,
+ DBG_BLOCK_ID_TCC4 = 0x93,
+ DBG_BLOCK_ID_TCC5 = 0x94,
+ DBG_BLOCK_ID_TCC6 = 0x95,
+ DBG_BLOCK_ID_TCC7 = 0x96,
+ DBG_BLOCK_ID_SPS00 = 0x97,
+ DBG_BLOCK_ID_SPS01 = 0x98,
+ DBG_BLOCK_ID_SPS02 = 0x99,
+ DBG_BLOCK_ID_SPS10 = 0x9a,
+ DBG_BLOCK_ID_SPS11 = 0x9b,
+ DBG_BLOCK_ID_SPS12 = 0x9c,
+ DBG_BLOCK_ID_UNUSED21 = 0x9d,
+ DBG_BLOCK_ID_UNUSED22 = 0x9e,
+ DBG_BLOCK_ID_TA00 = 0x9f,
+ DBG_BLOCK_ID_TA01 = 0xa0,
+ DBG_BLOCK_ID_TA02 = 0xa1,
+ DBG_BLOCK_ID_TA03 = 0xa2,
+ DBG_BLOCK_ID_TA04 = 0xa3,
+ DBG_BLOCK_ID_TA05 = 0xa4,
+ DBG_BLOCK_ID_TA06 = 0xa5,
+ DBG_BLOCK_ID_TA07 = 0xa6,
+ DBG_BLOCK_ID_TA08 = 0xa7,
+ DBG_BLOCK_ID_TA09 = 0xa8,
+ DBG_BLOCK_ID_TA0A = 0xa9,
+ DBG_BLOCK_ID_TA0B = 0xaa,
+ DBG_BLOCK_ID_UNUSED23 = 0xab,
+ DBG_BLOCK_ID_UNUSED24 = 0xac,
+ DBG_BLOCK_ID_UNUSED25 = 0xad,
+ DBG_BLOCK_ID_UNUSED26 = 0xae,
+ DBG_BLOCK_ID_TA10 = 0xaf,
+ DBG_BLOCK_ID_TA11 = 0xb0,
+ DBG_BLOCK_ID_TA12 = 0xb1,
+ DBG_BLOCK_ID_TA13 = 0xb2,
+ DBG_BLOCK_ID_TA14 = 0xb3,
+ DBG_BLOCK_ID_TA15 = 0xb4,
+ DBG_BLOCK_ID_TA16 = 0xb5,
+ DBG_BLOCK_ID_TA17 = 0xb6,
+ DBG_BLOCK_ID_TA18 = 0xb7,
+ DBG_BLOCK_ID_TA19 = 0xb8,
+ DBG_BLOCK_ID_TA1A = 0xb9,
+ DBG_BLOCK_ID_TA1B = 0xba,
+ DBG_BLOCK_ID_UNUSED27 = 0xbb,
+ DBG_BLOCK_ID_UNUSED28 = 0xbc,
+ DBG_BLOCK_ID_UNUSED29 = 0xbd,
+ DBG_BLOCK_ID_UNUSED30 = 0xbe,
+ DBG_BLOCK_ID_TD00 = 0xbf,
+ DBG_BLOCK_ID_TD01 = 0xc0,
+ DBG_BLOCK_ID_TD02 = 0xc1,
+ DBG_BLOCK_ID_TD03 = 0xc2,
+ DBG_BLOCK_ID_TD04 = 0xc3,
+ DBG_BLOCK_ID_TD05 = 0xc4,
+ DBG_BLOCK_ID_TD06 = 0xc5,
+ DBG_BLOCK_ID_TD07 = 0xc6,
+ DBG_BLOCK_ID_TD08 = 0xc7,
+ DBG_BLOCK_ID_TD09 = 0xc8,
+ DBG_BLOCK_ID_TD0A = 0xc9,
+ DBG_BLOCK_ID_TD0B = 0xca,
+ DBG_BLOCK_ID_UNUSED31 = 0xcb,
+ DBG_BLOCK_ID_UNUSED32 = 0xcc,
+ DBG_BLOCK_ID_UNUSED33 = 0xcd,
+ DBG_BLOCK_ID_UNUSED34 = 0xce,
+ DBG_BLOCK_ID_TD10 = 0xcf,
+ DBG_BLOCK_ID_TD11 = 0xd0,
+ DBG_BLOCK_ID_TD12 = 0xd1,
+ DBG_BLOCK_ID_TD13 = 0xd2,
+ DBG_BLOCK_ID_TD14 = 0xd3,
+ DBG_BLOCK_ID_TD15 = 0xd4,
+ DBG_BLOCK_ID_TD16 = 0xd5,
+ DBG_BLOCK_ID_TD17 = 0xd6,
+ DBG_BLOCK_ID_TD18 = 0xd7,
+ DBG_BLOCK_ID_TD19 = 0xd8,
+ DBG_BLOCK_ID_TD1A = 0xd9,
+ DBG_BLOCK_ID_TD1B = 0xda,
+ DBG_BLOCK_ID_UNUSED35 = 0xdb,
+ DBG_BLOCK_ID_UNUSED36 = 0xdc,
+ DBG_BLOCK_ID_UNUSED37 = 0xdd,
+ DBG_BLOCK_ID_UNUSED38 = 0xde,
+ DBG_BLOCK_ID_LDS00 = 0xdf,
+ DBG_BLOCK_ID_LDS01 = 0xe0,
+ DBG_BLOCK_ID_LDS02 = 0xe1,
+ DBG_BLOCK_ID_LDS03 = 0xe2,
+ DBG_BLOCK_ID_LDS04 = 0xe3,
+ DBG_BLOCK_ID_LDS05 = 0xe4,
+ DBG_BLOCK_ID_LDS06 = 0xe5,
+ DBG_BLOCK_ID_LDS07 = 0xe6,
+ DBG_BLOCK_ID_LDS08 = 0xe7,
+ DBG_BLOCK_ID_LDS09 = 0xe8,
+ DBG_BLOCK_ID_LDS0A = 0xe9,
+ DBG_BLOCK_ID_LDS0B = 0xea,
+ DBG_BLOCK_ID_UNUSED39 = 0xeb,
+ DBG_BLOCK_ID_UNUSED40 = 0xec,
+ DBG_BLOCK_ID_UNUSED41 = 0xed,
+ DBG_BLOCK_ID_UNUSED42 = 0xee,
+ DBG_BLOCK_ID_LDS10 = 0xef,
+ DBG_BLOCK_ID_LDS11 = 0xf0,
+ DBG_BLOCK_ID_LDS12 = 0xf1,
+ DBG_BLOCK_ID_LDS13 = 0xf2,
+ DBG_BLOCK_ID_LDS14 = 0xf3,
+ DBG_BLOCK_ID_LDS15 = 0xf4,
+ DBG_BLOCK_ID_LDS16 = 0xf5,
+ DBG_BLOCK_ID_LDS17 = 0xf6,
+ DBG_BLOCK_ID_LDS18 = 0xf7,
+ DBG_BLOCK_ID_LDS19 = 0xf8,
+ DBG_BLOCK_ID_LDS1A = 0xf9,
+ DBG_BLOCK_ID_LDS1B = 0xfa,
+ DBG_BLOCK_ID_UNUSED43 = 0xfb,
+ DBG_BLOCK_ID_UNUSED44 = 0xfc,
+ DBG_BLOCK_ID_UNUSED45 = 0xfd,
+ DBG_BLOCK_ID_UNUSED46 = 0xfe,
+} DebugBlockId;
+typedef enum DebugBlockId_BY2 {
+ DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
+ DBG_BLOCK_ID_VMC_BY2 = 0x1,
+ DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
+ DBG_BLOCK_ID_GRBM_BY2 = 0x3,
+ DBG_BLOCK_ID_CSC_BY2 = 0x4,
+ DBG_BLOCK_ID_IH_BY2 = 0x5,
+ DBG_BLOCK_ID_SQ_BY2 = 0x6,
+ DBG_BLOCK_ID_UVD_BY2 = 0x7,
+ DBG_BLOCK_ID_SDMA0_BY2 = 0x8,
+ DBG_BLOCK_ID_SPIM_BY2 = 0x9,
+ DBG_BLOCK_ID_VC0_BY2 = 0xa,
+ DBG_BLOCK_ID_PA_BY2 = 0xb,
+ DBG_BLOCK_ID_CP0_BY2 = 0xc,
+ DBG_BLOCK_ID_CP2_BY2 = 0xd,
+ DBG_BLOCK_ID_PC0_BY2 = 0xe,
+ DBG_BLOCK_ID_BCI0_BY2 = 0xf,
+ DBG_BLOCK_ID_SXM0_BY2 = 0x10,
+ DBG_BLOCK_ID_SCT0_BY2 = 0x11,
+ DBG_BLOCK_ID_SPM0_BY2 = 0x12,
+ DBG_BLOCK_ID_BCI2_BY2 = 0x13,
+ DBG_BLOCK_ID_TCA_BY2 = 0x14,
+ DBG_BLOCK_ID_TCCA_BY2 = 0x15,
+ DBG_BLOCK_ID_MCC_BY2 = 0x16,
+ DBG_BLOCK_ID_MCC2_BY2 = 0x17,
+ DBG_BLOCK_ID_MCD_BY2 = 0x18,
+ DBG_BLOCK_ID_MCD2_BY2 = 0x19,
+ DBG_BLOCK_ID_MCD4_BY2 = 0x1a,
+ DBG_BLOCK_ID_MCB_BY2 = 0x1b,
+ DBG_BLOCK_ID_SQA_BY2 = 0x1c,
+ DBG_BLOCK_ID_SQA02_BY2 = 0x1d,
+ DBG_BLOCK_ID_SQA11_BY2 = 0x1e,
+ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f,
+ DBG_BLOCK_ID_SQB_BY2 = 0x20,
+ DBG_BLOCK_ID_SQB10_BY2 = 0x21,
+ DBG_BLOCK_ID_UNUSED10_BY2 = 0x22,
+ DBG_BLOCK_ID_UNUSED12_BY2 = 0x23,
+ DBG_BLOCK_ID_CB_BY2 = 0x24,
+ DBG_BLOCK_ID_CB02_BY2 = 0x25,
+ DBG_BLOCK_ID_CB10_BY2 = 0x26,
+ DBG_BLOCK_ID_CB12_BY2 = 0x27,
+ DBG_BLOCK_ID_SXS_BY2 = 0x28,
+ DBG_BLOCK_ID_SXS2_BY2 = 0x29,
+ DBG_BLOCK_ID_SXS4_BY2 = 0x2a,
+ DBG_BLOCK_ID_SXS6_BY2 = 0x2b,
+ DBG_BLOCK_ID_DB_BY2 = 0x2c,
+ DBG_BLOCK_ID_DB02_BY2 = 0x2d,
+ DBG_BLOCK_ID_DB10_BY2 = 0x2e,
+ DBG_BLOCK_ID_DB12_BY2 = 0x2f,
+ DBG_BLOCK_ID_TCP_BY2 = 0x30,
+ DBG_BLOCK_ID_TCP2_BY2 = 0x31,
+ DBG_BLOCK_ID_TCP4_BY2 = 0x32,
+ DBG_BLOCK_ID_TCP6_BY2 = 0x33,
+ DBG_BLOCK_ID_TCP8_BY2 = 0x34,
+ DBG_BLOCK_ID_TCP10_BY2 = 0x35,
+ DBG_BLOCK_ID_TCP12_BY2 = 0x36,
+ DBG_BLOCK_ID_TCP14_BY2 = 0x37,
+ DBG_BLOCK_ID_TCP16_BY2 = 0x38,
+ DBG_BLOCK_ID_TCP18_BY2 = 0x39,
+ DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
+ DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
+ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
+ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
+ DBG_BLOCK_ID_TCC_BY2 = 0x40,
+ DBG_BLOCK_ID_TCC2_BY2 = 0x41,
+ DBG_BLOCK_ID_TCC4_BY2 = 0x42,
+ DBG_BLOCK_ID_TCC6_BY2 = 0x43,
+ DBG_BLOCK_ID_SPS_BY2 = 0x44,
+ DBG_BLOCK_ID_SPS02_BY2 = 0x45,
+ DBG_BLOCK_ID_SPS11_BY2 = 0x46,
+ DBG_BLOCK_ID_UNUSED14_BY2 = 0x47,
+ DBG_BLOCK_ID_TA_BY2 = 0x48,
+ DBG_BLOCK_ID_TA02_BY2 = 0x49,
+ DBG_BLOCK_ID_TA04_BY2 = 0x4a,
+ DBG_BLOCK_ID_TA06_BY2 = 0x4b,
+ DBG_BLOCK_ID_TA08_BY2 = 0x4c,
+ DBG_BLOCK_ID_TA0A_BY2 = 0x4d,
+ DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e,
+ DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f,
+ DBG_BLOCK_ID_TA10_BY2 = 0x50,
+ DBG_BLOCK_ID_TA12_BY2 = 0x51,
+ DBG_BLOCK_ID_TA14_BY2 = 0x52,
+ DBG_BLOCK_ID_TA16_BY2 = 0x53,
+ DBG_BLOCK_ID_TA18_BY2 = 0x54,
+ DBG_BLOCK_ID_TA1A_BY2 = 0x55,
+ DBG_BLOCK_ID_UNUSED24_BY2 = 0x56,
+ DBG_BLOCK_ID_UNUSED26_BY2 = 0x57,
+ DBG_BLOCK_ID_TD_BY2 = 0x58,
+ DBG_BLOCK_ID_TD02_BY2 = 0x59,
+ DBG_BLOCK_ID_TD04_BY2 = 0x5a,
+ DBG_BLOCK_ID_TD06_BY2 = 0x5b,
+ DBG_BLOCK_ID_TD08_BY2 = 0x5c,
+ DBG_BLOCK_ID_TD0A_BY2 = 0x5d,
+ DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e,
+ DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f,
+ DBG_BLOCK_ID_TD10_BY2 = 0x60,
+ DBG_BLOCK_ID_TD12_BY2 = 0x61,
+ DBG_BLOCK_ID_TD14_BY2 = 0x62,
+ DBG_BLOCK_ID_TD16_BY2 = 0x63,
+ DBG_BLOCK_ID_TD18_BY2 = 0x64,
+ DBG_BLOCK_ID_TD1A_BY2 = 0x65,
+ DBG_BLOCK_ID_UNUSED32_BY2 = 0x66,
+ DBG_BLOCK_ID_UNUSED34_BY2 = 0x67,
+ DBG_BLOCK_ID_LDS_BY2 = 0x68,
+ DBG_BLOCK_ID_LDS02_BY2 = 0x69,
+ DBG_BLOCK_ID_LDS04_BY2 = 0x6a,
+ DBG_BLOCK_ID_LDS06_BY2 = 0x6b,
+ DBG_BLOCK_ID_LDS08_BY2 = 0x6c,
+ DBG_BLOCK_ID_LDS0A_BY2 = 0x6d,
+ DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e,
+ DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f,
+ DBG_BLOCK_ID_LDS10_BY2 = 0x70,
+ DBG_BLOCK_ID_LDS12_BY2 = 0x71,
+ DBG_BLOCK_ID_LDS14_BY2 = 0x72,
+ DBG_BLOCK_ID_LDS16_BY2 = 0x73,
+ DBG_BLOCK_ID_LDS18_BY2 = 0x74,
+ DBG_BLOCK_ID_LDS1A_BY2 = 0x75,
+ DBG_BLOCK_ID_UNUSED40_BY2 = 0x76,
+ DBG_BLOCK_ID_UNUSED42_BY2 = 0x77,
+} DebugBlockId_BY2;
+typedef enum DebugBlockId_BY4 {
+ DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
+ DBG_BLOCK_ID_UNUSED0_BY4 = 0x1,
+ DBG_BLOCK_ID_CSC_BY4 = 0x2,
+ DBG_BLOCK_ID_SQ_BY4 = 0x3,
+ DBG_BLOCK_ID_SDMA0_BY4 = 0x4,
+ DBG_BLOCK_ID_VC0_BY4 = 0x5,
+ DBG_BLOCK_ID_CP0_BY4 = 0x6,
+ DBG_BLOCK_ID_UNUSED1_BY4 = 0x7,
+ DBG_BLOCK_ID_SXM0_BY4 = 0x8,
+ DBG_BLOCK_ID_SPM0_BY4 = 0x9,
+ DBG_BLOCK_ID_TCAA_BY4 = 0xa,
+ DBG_BLOCK_ID_MCC_BY4 = 0xb,
+ DBG_BLOCK_ID_MCD_BY4 = 0xc,
+ DBG_BLOCK_ID_MCD4_BY4 = 0xd,
+ DBG_BLOCK_ID_SQA_BY4 = 0xe,
+ DBG_BLOCK_ID_SQA11_BY4 = 0xf,
+ DBG_BLOCK_ID_SQB_BY4 = 0x10,
+ DBG_BLOCK_ID_UNUSED10_BY4 = 0x11,
+ DBG_BLOCK_ID_CB_BY4 = 0x12,
+ DBG_BLOCK_ID_CB10_BY4 = 0x13,
+ DBG_BLOCK_ID_SXS_BY4 = 0x14,
+ DBG_BLOCK_ID_SXS4_BY4 = 0x15,
+ DBG_BLOCK_ID_DB_BY4 = 0x16,
+ DBG_BLOCK_ID_DB10_BY4 = 0x17,
+ DBG_BLOCK_ID_TCP_BY4 = 0x18,
+ DBG_BLOCK_ID_TCP4_BY4 = 0x19,
+ DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
+ DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
+ DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
+ DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
+ DBG_BLOCK_ID_TCC_BY4 = 0x20,
+ DBG_BLOCK_ID_TCC4_BY4 = 0x21,
+ DBG_BLOCK_ID_SPS_BY4 = 0x22,
+ DBG_BLOCK_ID_SPS11_BY4 = 0x23,
+ DBG_BLOCK_ID_TA_BY4 = 0x24,
+ DBG_BLOCK_ID_TA04_BY4 = 0x25,
+ DBG_BLOCK_ID_TA08_BY4 = 0x26,
+ DBG_BLOCK_ID_UNUSED20_BY4 = 0x27,
+ DBG_BLOCK_ID_TA10_BY4 = 0x28,
+ DBG_BLOCK_ID_TA14_BY4 = 0x29,
+ DBG_BLOCK_ID_TA18_BY4 = 0x2a,
+ DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b,
+ DBG_BLOCK_ID_TD_BY4 = 0x2c,
+ DBG_BLOCK_ID_TD04_BY4 = 0x2d,
+ DBG_BLOCK_ID_TD08_BY4 = 0x2e,
+ DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f,
+ DBG_BLOCK_ID_TD10_BY4 = 0x30,
+ DBG_BLOCK_ID_TD14_BY4 = 0x31,
+ DBG_BLOCK_ID_TD18_BY4 = 0x32,
+ DBG_BLOCK_ID_UNUSED32_BY4 = 0x33,
+ DBG_BLOCK_ID_LDS_BY4 = 0x34,
+ DBG_BLOCK_ID_LDS04_BY4 = 0x35,
+ DBG_BLOCK_ID_LDS08_BY4 = 0x36,
+ DBG_BLOCK_ID_UNUSED36_BY4 = 0x37,
+ DBG_BLOCK_ID_LDS10_BY4 = 0x38,
+ DBG_BLOCK_ID_LDS14_BY4 = 0x39,
+ DBG_BLOCK_ID_LDS18_BY4 = 0x3a,
+ DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b,
+} DebugBlockId_BY4;
+typedef enum DebugBlockId_BY8 {
+ DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
+ DBG_BLOCK_ID_CSC_BY8 = 0x1,
+ DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
+ DBG_BLOCK_ID_CP0_BY8 = 0x3,
+ DBG_BLOCK_ID_SXM0_BY8 = 0x4,
+ DBG_BLOCK_ID_TCA_BY8 = 0x5,
+ DBG_BLOCK_ID_MCD_BY8 = 0x6,
+ DBG_BLOCK_ID_SQA_BY8 = 0x7,
+ DBG_BLOCK_ID_SQB_BY8 = 0x8,
+ DBG_BLOCK_ID_CB_BY8 = 0x9,
+ DBG_BLOCK_ID_SXS_BY8 = 0xa,
+ DBG_BLOCK_ID_DB_BY8 = 0xb,
+ DBG_BLOCK_ID_TCP_BY8 = 0xc,
+ DBG_BLOCK_ID_TCP8_BY8 = 0xd,
+ DBG_BLOCK_ID_TCP16_BY8 = 0xe,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
+ DBG_BLOCK_ID_TCC_BY8 = 0x10,
+ DBG_BLOCK_ID_SPS_BY8 = 0x11,
+ DBG_BLOCK_ID_TA_BY8 = 0x12,
+ DBG_BLOCK_ID_TA08_BY8 = 0x13,
+ DBG_BLOCK_ID_TA10_BY8 = 0x14,
+ DBG_BLOCK_ID_TA18_BY8 = 0x15,
+ DBG_BLOCK_ID_TD_BY8 = 0x16,
+ DBG_BLOCK_ID_TD08_BY8 = 0x17,
+ DBG_BLOCK_ID_TD10_BY8 = 0x18,
+ DBG_BLOCK_ID_TD18_BY8 = 0x19,
+ DBG_BLOCK_ID_LDS_BY8 = 0x1a,
+ DBG_BLOCK_ID_LDS08_BY8 = 0x1b,
+ DBG_BLOCK_ID_LDS10_BY8 = 0x1c,
+ DBG_BLOCK_ID_LDS18_BY8 = 0x1d,
+} DebugBlockId_BY8;
+typedef enum DebugBlockId_BY16 {
+ DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
+ DBG_BLOCK_ID_SDMA0_BY16 = 0x1,
+ DBG_BLOCK_ID_SXM_BY16 = 0x2,
+ DBG_BLOCK_ID_MCD_BY16 = 0x3,
+ DBG_BLOCK_ID_SQB_BY16 = 0x4,
+ DBG_BLOCK_ID_SXS_BY16 = 0x5,
+ DBG_BLOCK_ID_TCP_BY16 = 0x6,
+ DBG_BLOCK_ID_TCP16_BY16 = 0x7,
+ DBG_BLOCK_ID_TCC_BY16 = 0x8,
+ DBG_BLOCK_ID_TA_BY16 = 0x9,
+ DBG_BLOCK_ID_TA10_BY16 = 0xa,
+ DBG_BLOCK_ID_TD_BY16 = 0xb,
+ DBG_BLOCK_ID_TD10_BY16 = 0xc,
+ DBG_BLOCK_ID_LDS_BY16 = 0xd,
+ DBG_BLOCK_ID_LDS10_BY16 = 0xe,
+} DebugBlockId_BY16;
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0x0,
+ ENDIAN_8IN16 = 0x1,
+ ENDIAN_8IN32 = 0x2,
+ ENDIAN_8IN64 = 0x3,
+} SurfaceEndian;
+typedef enum ArrayMode {
+ ARRAY_LINEAR_GENERAL = 0x0,
+ ARRAY_LINEAR_ALIGNED = 0x1,
+ ARRAY_1D_TILED_THIN1 = 0x2,
+ ARRAY_1D_TILED_THICK = 0x3,
+ ARRAY_2D_TILED_THIN1 = 0x4,
+ ARRAY_PRT_TILED_THIN1 = 0x5,
+ ARRAY_PRT_2D_TILED_THIN1 = 0x6,
+ ARRAY_2D_TILED_THICK = 0x7,
+ ARRAY_2D_TILED_XTHICK = 0x8,
+ ARRAY_PRT_TILED_THICK = 0x9,
+ ARRAY_PRT_2D_TILED_THICK = 0xa,
+ ARRAY_PRT_3D_TILED_THIN1 = 0xb,
+ ARRAY_3D_TILED_THIN1 = 0xc,
+ ARRAY_3D_TILED_THICK = 0xd,
+ ARRAY_3D_TILED_XTHICK = 0xe,
+ ARRAY_PRT_3D_TILED_THICK = 0xf,
+} ArrayMode;
+typedef enum PipeTiling {
+ CONFIG_1_PIPE = 0x0,
+ CONFIG_2_PIPE = 0x1,
+ CONFIG_4_PIPE = 0x2,
+ CONFIG_8_PIPE = 0x3,
+} PipeTiling;
+typedef enum BankTiling {
+ CONFIG_4_BANK = 0x0,
+ CONFIG_8_BANK = 0x1,
+} BankTiling;
+typedef enum GroupInterleave {
+ CONFIG_256B_GROUP = 0x0,
+ CONFIG_512B_GROUP = 0x1,
+} GroupInterleave;
+typedef enum RowTiling {
+ CONFIG_1KB_ROW = 0x0,
+ CONFIG_2KB_ROW = 0x1,
+ CONFIG_4KB_ROW = 0x2,
+ CONFIG_8KB_ROW = 0x3,
+ CONFIG_1KB_ROW_OPT = 0x4,
+ CONFIG_2KB_ROW_OPT = 0x5,
+ CONFIG_4KB_ROW_OPT = 0x6,
+ CONFIG_8KB_ROW_OPT = 0x7,
+} RowTiling;
+typedef enum BankSwapBytes {
+ CONFIG_128B_SWAPS = 0x0,
+ CONFIG_256B_SWAPS = 0x1,
+ CONFIG_512B_SWAPS = 0x2,
+ CONFIG_1KB_SWAPS = 0x3,
+} BankSwapBytes;
+typedef enum SampleSplitBytes {
+ CONFIG_1KB_SPLIT = 0x0,
+ CONFIG_2KB_SPLIT = 0x1,
+ CONFIG_4KB_SPLIT = 0x2,
+ CONFIG_8KB_SPLIT = 0x3,
+} SampleSplitBytes;
+typedef enum NumPipes {
+ ADDR_CONFIG_1_PIPE = 0x0,
+ ADDR_CONFIG_2_PIPE = 0x1,
+ ADDR_CONFIG_4_PIPE = 0x2,
+ ADDR_CONFIG_8_PIPE = 0x3,
+} NumPipes;
+typedef enum PipeInterleaveSize {
+ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
+ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
+} PipeInterleaveSize;
+typedef enum BankInterleaveSize {
+ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
+ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
+ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
+ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
+} BankInterleaveSize;
+typedef enum NumShaderEngines {
+ ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
+ ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
+} NumShaderEngines;
+typedef enum ShaderEngineTileSize {
+ ADDR_CONFIG_SE_TILE_16 = 0x0,
+ ADDR_CONFIG_SE_TILE_32 = 0x1,
+} ShaderEngineTileSize;
+typedef enum NumGPUs {
+ ADDR_CONFIG_1_GPU = 0x0,
+ ADDR_CONFIG_2_GPU = 0x1,
+ ADDR_CONFIG_4_GPU = 0x2,
+} NumGPUs;
+typedef enum MultiGPUTileSize {
+ ADDR_CONFIG_GPU_TILE_16 = 0x0,
+ ADDR_CONFIG_GPU_TILE_32 = 0x1,
+ ADDR_CONFIG_GPU_TILE_64 = 0x2,
+ ADDR_CONFIG_GPU_TILE_128 = 0x3,
+} MultiGPUTileSize;
+typedef enum RowSize {
+ ADDR_CONFIG_1KB_ROW = 0x0,
+ ADDR_CONFIG_2KB_ROW = 0x1,
+ ADDR_CONFIG_4KB_ROW = 0x2,
+} RowSize;
+typedef enum NumLowerPipes {
+ ADDR_CONFIG_1_LOWER_PIPES = 0x0,
+ ADDR_CONFIG_2_LOWER_PIPES = 0x1,
+} NumLowerPipes;
+typedef enum ColorTransform {
+ DCC_CT_AUTO = 0x0,
+ DCC_CT_NONE = 0x1,
+ ABGR_TO_A_BG_G_RB = 0x2,
+ BGRA_TO_BG_G_RB_A = 0x3,
+} ColorTransform;
+typedef enum CompareRef {
+ REF_NEVER = 0x0,
+ REF_LESS = 0x1,
+ REF_EQUAL = 0x2,
+ REF_LEQUAL = 0x3,
+ REF_GREATER = 0x4,
+ REF_NOTEQUAL = 0x5,
+ REF_GEQUAL = 0x6,
+ REF_ALWAYS = 0x7,
+} CompareRef;
+typedef enum ReadSize {
+ READ_256_BITS = 0x0,
+ READ_512_BITS = 0x1,
+} ReadSize;
+typedef enum DepthFormat {
+ DEPTH_INVALID = 0x0,
+ DEPTH_16 = 0x1,
+ DEPTH_X8_24 = 0x2,
+ DEPTH_8_24 = 0x3,
+ DEPTH_X8_24_FLOAT = 0x4,
+ DEPTH_8_24_FLOAT = 0x5,
+ DEPTH_32_FLOAT = 0x6,
+ DEPTH_X24_8_32_FLOAT = 0x7,
+} DepthFormat;
+typedef enum ZFormat {
+ Z_INVALID = 0x0,
+ Z_16 = 0x1,
+ Z_24 = 0x2,
+ Z_32_FLOAT = 0x3,
+} ZFormat;
+typedef enum StencilFormat {
+ STENCIL_INVALID = 0x0,
+ STENCIL_8 = 0x1,
+} StencilFormat;
+typedef enum CmaskMode {
+ CMASK_CLEAR_NONE = 0x0,
+ CMASK_CLEAR_ONE = 0x1,
+ CMASK_CLEAR_ALL = 0x2,
+ CMASK_ANY_EXPANDED = 0x3,
+ CMASK_ALPHA0_FRAG1 = 0x4,
+ CMASK_ALPHA0_FRAG2 = 0x5,
+ CMASK_ALPHA0_FRAG4 = 0x6,
+ CMASK_ALPHA0_FRAGS = 0x7,
+ CMASK_ALPHA1_FRAG1 = 0x8,
+ CMASK_ALPHA1_FRAG2 = 0x9,
+ CMASK_ALPHA1_FRAG4 = 0xa,
+ CMASK_ALPHA1_FRAGS = 0xb,
+ CMASK_ALPHAX_FRAG1 = 0xc,
+ CMASK_ALPHAX_FRAG2 = 0xd,
+ CMASK_ALPHAX_FRAG4 = 0xe,
+ CMASK_ALPHAX_FRAGS = 0xf,
+} CmaskMode;
+typedef enum QuadExportFormat {
+ EXPORT_UNUSED = 0x0,
+ EXPORT_32_R = 0x1,
+ EXPORT_32_GR = 0x2,
+ EXPORT_32_AR = 0x3,
+ EXPORT_FP16_ABGR = 0x4,
+ EXPORT_UNSIGNED16_ABGR = 0x5,
+ EXPORT_SIGNED16_ABGR = 0x6,
+ EXPORT_32_ABGR = 0x7,
+} QuadExportFormat;
+typedef enum QuadExportFormatOld {
+ EXPORT_4P_32BPC_ABGR = 0x0,
+ EXPORT_4P_16BPC_ABGR = 0x1,
+ EXPORT_4P_32BPC_GR = 0x2,
+ EXPORT_4P_32BPC_AR = 0x3,
+ EXPORT_2P_32BPC_ABGR = 0x4,
+ EXPORT_8P_32BPC_R = 0x5,
+} QuadExportFormatOld;
+typedef enum ColorFormat {
+ COLOR_INVALID = 0x0,
+ COLOR_8 = 0x1,
+ COLOR_16 = 0x2,
+ COLOR_8_8 = 0x3,
+ COLOR_32 = 0x4,
+ COLOR_16_16 = 0x5,
+ COLOR_10_11_11 = 0x6,
+ COLOR_11_11_10 = 0x7,
+ COLOR_10_10_10_2 = 0x8,
+ COLOR_2_10_10_10 = 0x9,
+ COLOR_8_8_8_8 = 0xa,
+ COLOR_32_32 = 0xb,
+ COLOR_16_16_16_16 = 0xc,
+ COLOR_RESERVED_13 = 0xd,
+ COLOR_32_32_32_32 = 0xe,
+ COLOR_RESERVED_15 = 0xf,
+ COLOR_5_6_5 = 0x10,
+ COLOR_1_5_5_5 = 0x11,
+ COLOR_5_5_5_1 = 0x12,
+ COLOR_4_4_4_4 = 0x13,
+ COLOR_8_24 = 0x14,
+ COLOR_24_8 = 0x15,
+ COLOR_X24_8_32_FLOAT = 0x16,
+ COLOR_RESERVED_23 = 0x17,
+} ColorFormat;
+typedef enum SurfaceFormat {
+ FMT_INVALID = 0x0,
+ FMT_8 = 0x1,
+ FMT_16 = 0x2,
+ FMT_8_8 = 0x3,
+ FMT_32 = 0x4,
+ FMT_16_16 = 0x5,
+ FMT_10_11_11 = 0x6,
+ FMT_11_11_10 = 0x7,
+ FMT_10_10_10_2 = 0x8,
+ FMT_2_10_10_10 = 0x9,
+ FMT_8_8_8_8 = 0xa,
+ FMT_32_32 = 0xb,
+ FMT_16_16_16_16 = 0xc,
+ FMT_32_32_32 = 0xd,
+ FMT_32_32_32_32 = 0xe,
+ FMT_RESERVED_4 = 0xf,
+ FMT_5_6_5 = 0x10,
+ FMT_1_5_5_5 = 0x11,
+ FMT_5_5_5_1 = 0x12,
+ FMT_4_4_4_4 = 0x13,
+ FMT_8_24 = 0x14,
+ FMT_24_8 = 0x15,
+ FMT_X24_8_32_FLOAT = 0x16,
+ FMT_RESERVED_33 = 0x17,
+ FMT_11_11_10_FLOAT = 0x18,
+ FMT_16_FLOAT = 0x19,
+ FMT_32_FLOAT = 0x1a,
+ FMT_16_16_FLOAT = 0x1b,
+ FMT_8_24_FLOAT = 0x1c,
+ FMT_24_8_FLOAT = 0x1d,
+ FMT_32_32_FLOAT = 0x1e,
+ FMT_10_11_11_FLOAT = 0x1f,
+ FMT_16_16_16_16_FLOAT = 0x20,
+ FMT_3_3_2 = 0x21,
+ FMT_6_5_5 = 0x22,
+ FMT_32_32_32_32_FLOAT = 0x23,
+ FMT_RESERVED_36 = 0x24,
+ FMT_1 = 0x25,
+ FMT_1_REVERSED = 0x26,
+ FMT_GB_GR = 0x27,
+ FMT_BG_RG = 0x28,
+ FMT_32_AS_8 = 0x29,
+ FMT_32_AS_8_8 = 0x2a,
+ FMT_5_9_9_9_SHAREDEXP = 0x2b,
+ FMT_8_8_8 = 0x2c,
+ FMT_16_16_16 = 0x2d,
+ FMT_16_16_16_FLOAT = 0x2e,
+ FMT_4_4 = 0x2f,
+ FMT_32_32_32_FLOAT = 0x30,
+ FMT_BC1 = 0x31,
+ FMT_BC2 = 0x32,
+ FMT_BC3 = 0x33,
+ FMT_BC4 = 0x34,
+ FMT_BC5 = 0x35,
+ FMT_BC6 = 0x36,
+ FMT_BC7 = 0x37,
+ FMT_32_AS_32_32_32_32 = 0x38,
+ FMT_APC3 = 0x39,
+ FMT_APC4 = 0x3a,
+ FMT_APC5 = 0x3b,
+ FMT_APC6 = 0x3c,
+ FMT_APC7 = 0x3d,
+ FMT_CTX1 = 0x3e,
+ FMT_RESERVED_63 = 0x3f,
+} SurfaceFormat;
+typedef enum BUF_DATA_FORMAT {
+ BUF_DATA_FORMAT_INVALID = 0x0,
+ BUF_DATA_FORMAT_8 = 0x1,
+ BUF_DATA_FORMAT_16 = 0x2,
+ BUF_DATA_FORMAT_8_8 = 0x3,
+ BUF_DATA_FORMAT_32 = 0x4,
+ BUF_DATA_FORMAT_16_16 = 0x5,
+ BUF_DATA_FORMAT_10_11_11 = 0x6,
+ BUF_DATA_FORMAT_11_11_10 = 0x7,
+ BUF_DATA_FORMAT_10_10_10_2 = 0x8,
+ BUF_DATA_FORMAT_2_10_10_10 = 0x9,
+ BUF_DATA_FORMAT_8_8_8_8 = 0xa,
+ BUF_DATA_FORMAT_32_32 = 0xb,
+ BUF_DATA_FORMAT_16_16_16_16 = 0xc,
+ BUF_DATA_FORMAT_32_32_32 = 0xd,
+ BUF_DATA_FORMAT_32_32_32_32 = 0xe,
+ BUF_DATA_FORMAT_RESERVED_15 = 0xf,
+} BUF_DATA_FORMAT;
+typedef enum IMG_DATA_FORMAT {
+ IMG_DATA_FORMAT_INVALID = 0x0,
+ IMG_DATA_FORMAT_8 = 0x1,
+ IMG_DATA_FORMAT_16 = 0x2,
+ IMG_DATA_FORMAT_8_8 = 0x3,
+ IMG_DATA_FORMAT_32 = 0x4,
+ IMG_DATA_FORMAT_16_16 = 0x5,
+ IMG_DATA_FORMAT_10_11_11 = 0x6,
+ IMG_DATA_FORMAT_11_11_10 = 0x7,
+ IMG_DATA_FORMAT_10_10_10_2 = 0x8,
+ IMG_DATA_FORMAT_2_10_10_10 = 0x9,
+ IMG_DATA_FORMAT_8_8_8_8 = 0xa,
+ IMG_DATA_FORMAT_32_32 = 0xb,
+ IMG_DATA_FORMAT_16_16_16_16 = 0xc,
+ IMG_DATA_FORMAT_32_32_32 = 0xd,
+ IMG_DATA_FORMAT_32_32_32_32 = 0xe,
+ IMG_DATA_FORMAT_RESERVED_15 = 0xf,
+ IMG_DATA_FORMAT_5_6_5 = 0x10,
+ IMG_DATA_FORMAT_1_5_5_5 = 0x11,
+ IMG_DATA_FORMAT_5_5_5_1 = 0x12,
+ IMG_DATA_FORMAT_4_4_4_4 = 0x13,
+ IMG_DATA_FORMAT_8_24 = 0x14,
+ IMG_DATA_FORMAT_24_8 = 0x15,
+ IMG_DATA_FORMAT_X24_8_32 = 0x16,
+ IMG_DATA_FORMAT_RESERVED_23 = 0x17,
+ IMG_DATA_FORMAT_RESERVED_24 = 0x18,
+ IMG_DATA_FORMAT_RESERVED_25 = 0x19,
+ IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
+ IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
+ IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
+ IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
+ IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
+ IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
+ IMG_DATA_FORMAT_GB_GR = 0x20,
+ IMG_DATA_FORMAT_BG_RG = 0x21,
+ IMG_DATA_FORMAT_5_9_9_9 = 0x22,
+ IMG_DATA_FORMAT_BC1 = 0x23,
+ IMG_DATA_FORMAT_BC2 = 0x24,
+ IMG_DATA_FORMAT_BC3 = 0x25,
+ IMG_DATA_FORMAT_BC4 = 0x26,
+ IMG_DATA_FORMAT_BC5 = 0x27,
+ IMG_DATA_FORMAT_BC6 = 0x28,
+ IMG_DATA_FORMAT_BC7 = 0x29,
+ IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
+ IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
+ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
+ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
+ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
+ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
+ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
+ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
+ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
+ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
+ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
+ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
+ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
+ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
+ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
+ IMG_DATA_FORMAT_4_4 = 0x39,
+ IMG_DATA_FORMAT_6_5_5 = 0x3a,
+ IMG_DATA_FORMAT_1 = 0x3b,
+ IMG_DATA_FORMAT_1_REVERSED = 0x3c,
+ IMG_DATA_FORMAT_32_AS_8 = 0x3d,
+ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
+ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
+} IMG_DATA_FORMAT;
+typedef enum BUF_NUM_FORMAT {
+ BUF_NUM_FORMAT_UNORM = 0x0,
+ BUF_NUM_FORMAT_SNORM = 0x1,
+ BUF_NUM_FORMAT_USCALED = 0x2,
+ BUF_NUM_FORMAT_SSCALED = 0x3,
+ BUF_NUM_FORMAT_UINT = 0x4,
+ BUF_NUM_FORMAT_SINT = 0x5,
+ BUF_NUM_FORMAT_RESERVED_6 = 0x6,
+ BUF_NUM_FORMAT_FLOAT = 0x7,
+} BUF_NUM_FORMAT;
+typedef enum IMG_NUM_FORMAT {
+ IMG_NUM_FORMAT_UNORM = 0x0,
+ IMG_NUM_FORMAT_SNORM = 0x1,
+ IMG_NUM_FORMAT_USCALED = 0x2,
+ IMG_NUM_FORMAT_SSCALED = 0x3,
+ IMG_NUM_FORMAT_UINT = 0x4,
+ IMG_NUM_FORMAT_SINT = 0x5,
+ IMG_NUM_FORMAT_RESERVED_6 = 0x6,
+ IMG_NUM_FORMAT_FLOAT = 0x7,
+ IMG_NUM_FORMAT_RESERVED_8 = 0x8,
+ IMG_NUM_FORMAT_SRGB = 0x9,
+ IMG_NUM_FORMAT_RESERVED_10 = 0xa,
+ IMG_NUM_FORMAT_RESERVED_11 = 0xb,
+ IMG_NUM_FORMAT_RESERVED_12 = 0xc,
+ IMG_NUM_FORMAT_RESERVED_13 = 0xd,
+ IMG_NUM_FORMAT_RESERVED_14 = 0xe,
+ IMG_NUM_FORMAT_RESERVED_15 = 0xf,
+} IMG_NUM_FORMAT;
+typedef enum TileType {
+ ARRAY_COLOR_TILE = 0x0,
+ ARRAY_DEPTH_TILE = 0x1,
+} TileType;
+typedef enum NonDispTilingOrder {
+ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
+ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
+} NonDispTilingOrder;
+typedef enum MicroTileMode {
+ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
+ ADDR_SURF_THIN_MICRO_TILING = 0x1,
+ ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
+ ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
+ ADDR_SURF_THICK_MICRO_TILING = 0x4,
+} MicroTileMode;
+typedef enum TileSplit {
+ ADDR_SURF_TILE_SPLIT_64B = 0x0,
+ ADDR_SURF_TILE_SPLIT_128B = 0x1,
+ ADDR_SURF_TILE_SPLIT_256B = 0x2,
+ ADDR_SURF_TILE_SPLIT_512B = 0x3,
+ ADDR_SURF_TILE_SPLIT_1KB = 0x4,
+ ADDR_SURF_TILE_SPLIT_2KB = 0x5,
+ ADDR_SURF_TILE_SPLIT_4KB = 0x6,
+} TileSplit;
+typedef enum SampleSplit {
+ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
+ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
+ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
+ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
+} SampleSplit;
+typedef enum PipeConfig {
+ ADDR_SURF_P2 = 0x0,
+ ADDR_SURF_P2_RESERVED0 = 0x1,
+ ADDR_SURF_P2_RESERVED1 = 0x2,
+ ADDR_SURF_P2_RESERVED2 = 0x3,
+ ADDR_SURF_P4_8x16 = 0x4,
+ ADDR_SURF_P4_16x16 = 0x5,
+ ADDR_SURF_P4_16x32 = 0x6,
+ ADDR_SURF_P4_32x32 = 0x7,
+ ADDR_SURF_P8_16x16_8x16 = 0x8,
+ ADDR_SURF_P8_16x32_8x16 = 0x9,
+ ADDR_SURF_P8_32x32_8x16 = 0xa,
+ ADDR_SURF_P8_16x32_16x16 = 0xb,
+ ADDR_SURF_P8_32x32_16x16 = 0xc,
+ ADDR_SURF_P8_32x32_16x32 = 0xd,
+ ADDR_SURF_P8_32x64_32x32 = 0xe,
+ ADDR_SURF_P8_RESERVED0 = 0xf,
+ ADDR_SURF_P16_32x32_8x16 = 0x10,
+ ADDR_SURF_P16_32x32_16x16 = 0x11,
+} PipeConfig;
+typedef enum NumBanks {
+ ADDR_SURF_2_BANK = 0x0,
+ ADDR_SURF_4_BANK = 0x1,
+ ADDR_SURF_8_BANK = 0x2,
+ ADDR_SURF_16_BANK = 0x3,
+} NumBanks;
+typedef enum BankWidth {
+ ADDR_SURF_BANK_WIDTH_1 = 0x0,
+ ADDR_SURF_BANK_WIDTH_2 = 0x1,
+ ADDR_SURF_BANK_WIDTH_4 = 0x2,
+ ADDR_SURF_BANK_WIDTH_8 = 0x3,
+} BankWidth;
+typedef enum BankHeight {
+ ADDR_SURF_BANK_HEIGHT_1 = 0x0,
+ ADDR_SURF_BANK_HEIGHT_2 = 0x1,
+ ADDR_SURF_BANK_HEIGHT_4 = 0x2,
+ ADDR_SURF_BANK_HEIGHT_8 = 0x3,
+} BankHeight;
+typedef enum BankWidthHeight {
+ ADDR_SURF_BANK_WH_1 = 0x0,
+ ADDR_SURF_BANK_WH_2 = 0x1,
+ ADDR_SURF_BANK_WH_4 = 0x2,
+ ADDR_SURF_BANK_WH_8 = 0x3,
+} BankWidthHeight;
+typedef enum MacroTileAspect {
+ ADDR_SURF_MACRO_ASPECT_1 = 0x0,
+ ADDR_SURF_MACRO_ASPECT_2 = 0x1,
+ ADDR_SURF_MACRO_ASPECT_4 = 0x2,
+ ADDR_SURF_MACRO_ASPECT_8 = 0x3,
+} MacroTileAspect;
+typedef enum GATCL1RequestType {
+ GATCL1_TYPE_NORMAL = 0x0,
+ GATCL1_TYPE_SHOOTDOWN = 0x1,
+ GATCL1_TYPE_BYPASS = 0x2,
+} GATCL1RequestType;
+typedef enum TCC_CACHE_POLICIES {
+ TCC_CACHE_POLICY_LRU = 0x0,
+ TCC_CACHE_POLICY_STREAM = 0x1,
+} TCC_CACHE_POLICIES;
+typedef enum MTYPE {
+ MTYPE_NC_NV = 0x0,
+ MTYPE_NC = 0x1,
+ MTYPE_CC = 0x2,
+ MTYPE_UC = 0x3,
+} MTYPE;
+typedef enum PERFMON_COUNTER_MODE {
+ PERFMON_COUNTER_MODE_ACCUM = 0x0,
+ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
+ PERFMON_COUNTER_MODE_MAX = 0x2,
+ PERFMON_COUNTER_MODE_DIRTY = 0x3,
+ PERFMON_COUNTER_MODE_SAMPLE = 0x4,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
+ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
+ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
+ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
+ PERFMON_COUNTER_MODE_RESERVED = 0xf,
+} PERFMON_COUNTER_MODE;
+typedef enum PERFMON_SPM_MODE {
+ PERFMON_SPM_MODE_OFF = 0x0,
+ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
+ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
+ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
+ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
+ PERFMON_SPM_MODE_RESERVED_5 = 0x5,
+ PERFMON_SPM_MODE_RESERVED_6 = 0x6,
+ PERFMON_SPM_MODE_RESERVED_7 = 0x7,
+ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
+ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
+ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
+} PERFMON_SPM_MODE;
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0x0,
+ ARRAY_TILED = 0x1,
+} SurfaceTiling;
+typedef enum SurfaceArray {
+ ARRAY_1D = 0x0,
+ ARRAY_2D = 0x1,
+ ARRAY_3D = 0x2,
+ ARRAY_3D_SLICE = 0x3,
+} SurfaceArray;
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0x0,
+ ARRAY_2D_COLOR = 0x1,
+ ARRAY_3D_SLICE_COLOR = 0x3,
+} ColorArray;
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0x0,
+ ARRAY_2D_DEPTH = 0x1,
+} DepthArray;
+typedef enum ENUM_NUM_SIMD_PER_CU {
+ NUM_SIMD_PER_CU = 0x4,
+} ENUM_NUM_SIMD_PER_CU;
+typedef enum MEM_PWR_FORCE_CTRL {
+ NO_FORCE_REQUEST = 0x0,
+ FORCE_LIGHT_SLEEP_REQUEST = 0x1,
+ FORCE_DEEP_SLEEP_REQUEST = 0x2,
+ FORCE_SHUT_DOWN_REQUEST = 0x3,
+} MEM_PWR_FORCE_CTRL;
+typedef enum MEM_PWR_FORCE_CTRL2 {
+ NO_FORCE_REQ = 0x0,
+ FORCE_LIGHT_SLEEP_REQ = 0x1,
+} MEM_PWR_FORCE_CTRL2;
+typedef enum MEM_PWR_DIS_CTRL {
+ ENABLE_MEM_PWR_CTRL = 0x0,
+ DISABLE_MEM_PWR_CTRL = 0x1,
+} MEM_PWR_DIS_CTRL;
+typedef enum MEM_PWR_SEL_CTRL {
+ DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
+ DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
+ DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
+} MEM_PWR_SEL_CTRL;
+typedef enum MEM_PWR_SEL_CTRL2 {
+ DYNAMIC_DEEP_SLEEP_EN = 0x0,
+ DYNAMIC_LIGHT_SLEEP_EN = 0x1,
+} MEM_PWR_SEL_CTRL2;
+
+#endif /* BIF_5_1_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h
new file mode 100644
index 000000000000..ee1da0cbc84d
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h
@@ -0,0 +1,33080 @@
+/*
+ * BIF_5_1 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef BIF_5_1_SH_MASK_H
+#define BIF_5_1_SH_MASK_H
+
+#define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
+#define MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define MM_INDEX__MM_APER_MASK 0x80000000
+#define MM_INDEX__MM_APER__SHIFT 0x1f
+#define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
+#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define MM_DATA__MM_DATA_MASK 0xffffffff
+#define MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
+#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
+#define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x1
+#define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x0
+#define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2
+#define BUS_CNTL__BIOS_ROM_DIS__SHIFT 0x1
+#define BUS_CNTL__PMI_IO_DIS_MASK 0x4
+#define BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
+#define BUS_CNTL__PMI_MEM_DIS_MASK 0x8
+#define BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
+#define BUS_CNTL__PMI_BM_DIS_MASK 0x10
+#define BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
+#define BUS_CNTL__PMI_INT_DIS_MASK 0x20
+#define BUS_CNTL__PMI_INT_DIS__SHIFT 0x5
+#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x40
+#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6
+#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x80
+#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
+#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100
+#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8
+#define BUS_CNTL__SET_AZ_TC_MASK 0x1c00
+#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa
+#define BUS_CNTL__SET_MC_TC_MASK 0xe000
+#define BUS_CNTL__SET_MC_TC__SHIFT 0xd
+#define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x10000
+#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
+#define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x20000
+#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11
+#define BUS_CNTL__RD_STALL_IO_WR_MASK 0x40000
+#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12
+#define CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x1
+#define CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0
+#define CONFIG_CNTL__VGA_DIS_MASK 0x2
+#define CONFIG_CNTL__VGA_DIS__SHIFT 0x1
+#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x4
+#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2
+#define CONFIG_CNTL__GRPH_ADRSEL_MASK 0x18
+#define CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3
+#define CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xffffffff
+#define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define CONFIG_F0_BASE__F0_BASE_MASK 0xffffffff
+#define CONFIG_F0_BASE__F0_BASE__SHIFT 0x0
+#define CONFIG_APER_SIZE__APER_SIZE_MASK 0xffffffff
+#define CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0
+#define CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0xfffff
+#define CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0
+#define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xffffffff
+#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0
+#define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xffffffff
+#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0
+#define BX_RESET_EN__COR_RESET_EN_MASK 0x1
+#define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0
+#define BX_RESET_EN__REG_RESET_EN_MASK 0x2
+#define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1
+#define BX_RESET_EN__STY_RESET_EN_MASK 0x4
+#define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2
+#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x7
+#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0
+#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x8
+#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x3
+#define HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define HW_DEBUG__HW_16_DEBUG_MASK 0x10000
+#define HW_DEBUG__HW_16_DEBUG__SHIFT 0x10
+#define HW_DEBUG__HW_17_DEBUG_MASK 0x20000
+#define HW_DEBUG__HW_17_DEBUG__SHIFT 0x11
+#define HW_DEBUG__HW_18_DEBUG_MASK 0x40000
+#define HW_DEBUG__HW_18_DEBUG__SHIFT 0x12
+#define HW_DEBUG__HW_19_DEBUG_MASK 0x80000
+#define HW_DEBUG__HW_19_DEBUG__SHIFT 0x13
+#define HW_DEBUG__HW_20_DEBUG_MASK 0x100000
+#define HW_DEBUG__HW_20_DEBUG__SHIFT 0x14
+#define HW_DEBUG__HW_21_DEBUG_MASK 0x200000
+#define HW_DEBUG__HW_21_DEBUG__SHIFT 0x15
+#define HW_DEBUG__HW_22_DEBUG_MASK 0x400000
+#define HW_DEBUG__HW_22_DEBUG__SHIFT 0x16
+#define HW_DEBUG__HW_23_DEBUG_MASK 0x800000
+#define HW_DEBUG__HW_23_DEBUG__SHIFT 0x17
+#define HW_DEBUG__HW_24_DEBUG_MASK 0x1000000
+#define HW_DEBUG__HW_24_DEBUG__SHIFT 0x18
+#define HW_DEBUG__HW_25_DEBUG_MASK 0x2000000
+#define HW_DEBUG__HW_25_DEBUG__SHIFT 0x19
+#define HW_DEBUG__HW_26_DEBUG_MASK 0x4000000
+#define HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a
+#define HW_DEBUG__HW_27_DEBUG_MASK 0x8000000
+#define HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b
+#define HW_DEBUG__HW_28_DEBUG_MASK 0x10000000
+#define HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c
+#define HW_DEBUG__HW_29_DEBUG_MASK 0x20000000
+#define HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d
+#define HW_DEBUG__HW_30_DEBUG_MASK 0x40000000
+#define HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e
+#define HW_DEBUG__HW_31_DEBUG_MASK 0x80000000
+#define HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f
+#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT_MASK 0x7f
+#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT__SHIFT 0x0
+#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT_MASK 0x3f0000
+#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT__SHIFT 0x10
+#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT_MASK 0x1f
+#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT__SHIFT 0x0
+#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT_MASK 0x1e0
+#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT__SHIFT 0x5
+#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT_MASK 0x7c00
+#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT__SHIFT 0xa
+#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT_MASK 0x8000
+#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT__SHIFT 0xf
+#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT_MASK 0x100000
+#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT__SHIFT 0x14
+#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT_MASK 0x7e000000
+#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT__SHIFT 0x19
+#define BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x1
+#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0
+#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x1
+#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
+#define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x2
+#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1
+#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x8
+#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3
+#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0xf0
+#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
+#define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x100
+#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8
+#define INTERRUPT_CNTL__GEN_GPIO_INT_EN_MASK 0x1e00
+#define INTERRUPT_CNTL__GEN_GPIO_INT_EN__SHIFT 0x9
+#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT_MASK 0x6000
+#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT__SHIFT 0xd
+#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x8000
+#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf
+#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xffffffff
+#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0
+#define BIF_DEBUG_CNTL__DEBUG_EN_MASK 0x1
+#define BIF_DEBUG_CNTL__DEBUG_EN__SHIFT 0x0
+#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x2
+#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN__SHIFT 0x1
+#define BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK 0x4
+#define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x2
+#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x8
+#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL__SHIFT 0x3
+#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1_MASK 0x10
+#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT 0x4
+#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2_MASK 0x20
+#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2__SHIFT 0x5
+#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN_MASK 0x40
+#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN__SHIFT 0x6
+#define BIF_DEBUG_CNTL__DEBUG_SWAP_MASK 0x80
+#define BIF_DEBUG_CNTL__DEBUG_SWAP__SHIFT 0x7
+#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1_MASK 0x1f00
+#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x8
+#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2_MASK 0x1f0000
+#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2__SHIFT 0x10
+#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP_MASK 0x1000000
+#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP__SHIFT 0x18
+#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL_MASK 0xc0000000
+#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL__SHIFT 0x1e
+#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1_MASK 0x3f
+#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1__SHIFT 0x0
+#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2_MASK 0x3f00
+#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT 0x8
+#define BIF_DEBUG_OUT__DEBUG_OUTPUT_MASK 0x1ffff
+#define BIF_DEBUG_OUT__DEBUG_OUTPUT__SHIFT 0x0
+#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x1
+#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x1
+#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x1
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x2
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x4
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x18
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x20
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x40
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x80
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x100
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x200
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x400
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x800
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x1000
+#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A_MASK 0x1
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A__SHIFT 0x0
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL_MASK 0x2
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL__SHIFT 0x1
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE_MASK 0x4
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE__SHIFT 0x2
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE_MASK 0x18
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE__SHIFT 0x3
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0_MASK 0x20
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0__SHIFT 0x5
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1_MASK 0x40
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1__SHIFT 0x6
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2_MASK 0x80
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2__SHIFT 0x7
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3_MASK 0x100
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3__SHIFT 0x8
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN_MASK 0x200
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN__SHIFT 0x9
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE_MASK 0x400
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE__SHIFT 0xa
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN_MASK 0x800
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN__SHIFT 0xb
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN_MASK 0x1000
+#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN__SHIFT 0xc
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A_MASK 0x1
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A__SHIFT 0x0
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL_MASK 0x2
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL__SHIFT 0x1
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE_MASK 0x4
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE__SHIFT 0x2
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE_MASK 0x18
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE__SHIFT 0x3
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0_MASK 0x20
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0__SHIFT 0x5
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1_MASK 0x40
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1__SHIFT 0x6
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2_MASK 0x80
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2__SHIFT 0x7
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3_MASK 0x100
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3__SHIFT 0x8
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN_MASK 0x200
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN__SHIFT 0x9
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE_MASK 0x400
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE__SHIFT 0xa
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN_MASK 0x800
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN__SHIFT 0xb
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN_MASK 0x1000
+#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN__SHIFT 0xc
+#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffff
+#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0
+#define BIF_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000
+#define BIF_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f
+#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffff
+#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0
+#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x1
+#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0
+#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x2
+#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
+#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x4
+#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
+#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x8
+#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3
+#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x10
+#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4
+#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x20
+#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5
+#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x40
+#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6
+#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x80
+#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x7
+#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x100
+#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x8
+#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS_MASK 0x200
+#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9
+#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS_MASK 0x400
+#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa
+#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x800
+#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb
+#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x1000
+#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc
+#define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x1
+#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0
+#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x2
+#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1
+#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x4
+#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
+#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x8
+#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
+#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x10
+#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4
+#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x20
+#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x5
+#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x10000
+#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10
+#define BIF_SLVARB_MODE__SLVARB_MODE_MASK 0x3
+#define BIF_SLVARB_MODE__SLVARB_MODE__SHIFT 0x0
+#define BIF_FB_EN__FB_READ_EN_MASK 0x1
+#define BIF_FB_EN__FB_READ_EN__SHIFT 0x0
+#define BIF_FB_EN__FB_WRITE_EN_MASK 0x2
+#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
+#define BIF_BUSNUM_CNTL1__ID_MASK_MASK 0xff
+#define BIF_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0
+#define BIF_BUSNUM_LIST0__ID0_MASK 0xff
+#define BIF_BUSNUM_LIST0__ID0__SHIFT 0x0
+#define BIF_BUSNUM_LIST0__ID1_MASK 0xff00
+#define BIF_BUSNUM_LIST0__ID1__SHIFT 0x8
+#define BIF_BUSNUM_LIST0__ID2_MASK 0xff0000
+#define BIF_BUSNUM_LIST0__ID2__SHIFT 0x10
+#define BIF_BUSNUM_LIST0__ID3_MASK 0xff000000
+#define BIF_BUSNUM_LIST0__ID3__SHIFT 0x18
+#define BIF_BUSNUM_LIST1__ID4_MASK 0xff
+#define BIF_BUSNUM_LIST1__ID4__SHIFT 0x0
+#define BIF_BUSNUM_LIST1__ID5_MASK 0xff00
+#define BIF_BUSNUM_LIST1__ID5__SHIFT 0x8
+#define BIF_BUSNUM_LIST1__ID6_MASK 0xff0000
+#define BIF_BUSNUM_LIST1__ID6__SHIFT 0x10
+#define BIF_BUSNUM_LIST1__ID7_MASK 0xff000000
+#define BIF_BUSNUM_LIST1__ID7__SHIFT 0x18
+#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0xff
+#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0
+#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x100
+#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8
+#define BIF_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x10000
+#define BIF_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10
+#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x20000
+#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11
+#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x3f
+#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0
+#define BIF_PERFMON_CNTL__PERFCOUNTER_EN_MASK 0x1
+#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x0
+#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK 0x2
+#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x1
+#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1_MASK 0x4
+#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2
+#define BIF_PERFMON_CNTL__PERF_SEL0_MASK 0x1f00
+#define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x8
+#define BIF_PERFMON_CNTL__PERF_SEL1_MASK 0x3e000
+#define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0xd
+#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff
+#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0
+#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff
+#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0
+#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL_MASK 0xe
+#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL__SHIFT 0x1
+#define GPU_HDP_FLUSH_REQ__CP0_MASK 0x1
+#define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define GPU_HDP_FLUSH_REQ__CP1_MASK 0x2
+#define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define GPU_HDP_FLUSH_REQ__CP2_MASK 0x4
+#define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define GPU_HDP_FLUSH_REQ__CP3_MASK 0x8
+#define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define GPU_HDP_FLUSH_REQ__CP4_MASK 0x10
+#define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define GPU_HDP_FLUSH_REQ__CP5_MASK 0x20
+#define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define GPU_HDP_FLUSH_REQ__CP6_MASK 0x40
+#define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define GPU_HDP_FLUSH_REQ__CP7_MASK 0x80
+#define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define GPU_HDP_FLUSH_REQ__CP8_MASK 0x100
+#define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define GPU_HDP_FLUSH_REQ__CP9_MASK 0x200
+#define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x400
+#define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x800
+#define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define GPU_HDP_FLUSH_DONE__CP0_MASK 0x1
+#define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define GPU_HDP_FLUSH_DONE__CP1_MASK 0x2
+#define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define GPU_HDP_FLUSH_DONE__CP2_MASK 0x4
+#define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define GPU_HDP_FLUSH_DONE__CP3_MASK 0x8
+#define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define GPU_HDP_FLUSH_DONE__CP4_MASK 0x10
+#define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define GPU_HDP_FLUSH_DONE__CP5_MASK 0x20
+#define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define GPU_HDP_FLUSH_DONE__CP6_MASK 0x40
+#define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define GPU_HDP_FLUSH_DONE__CP7_MASK 0x80
+#define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define GPU_HDP_FLUSH_DONE__CP8_MASK 0x100
+#define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define GPU_HDP_FLUSH_DONE__CP9_MASK 0x200
+#define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x400
+#define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x800
+#define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR_MASK 0x1
+#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR__SHIFT 0x0
+#define SLAVE_HANG_ERROR__HDP_HANG_ERROR_MASK 0x2
+#define SLAVE_HANG_ERROR__HDP_HANG_ERROR__SHIFT 0x1
+#define SLAVE_HANG_ERROR__VGA_HANG_ERROR_MASK 0x4
+#define SLAVE_HANG_ERROR__VGA_HANG_ERROR__SHIFT 0x2
+#define SLAVE_HANG_ERROR__ROM_HANG_ERROR_MASK 0x8
+#define SLAVE_HANG_ERROR__ROM_HANG_ERROR__SHIFT 0x3
+#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR_MASK 0x10
+#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR__SHIFT 0x4
+#define SLAVE_HANG_ERROR__CEC_HANG_ERROR_MASK 0x20
+#define SLAVE_HANG_ERROR__CEC_HANG_ERROR__SHIFT 0x5
+#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR_MASK 0x80
+#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR__SHIFT 0x7
+#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR_MASK 0x100
+#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR__SHIFT 0x8
+#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR_MASK 0x200
+#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR__SHIFT 0x9
+#define CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x1
+#define CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0
+#define HOST_BUSNUM__HOST_ID_MASK 0xffff
+#define HOST_BUSNUM__HOST_ID__SHIFT 0x0
+#define PEER_REG_RANGE0__START_ADDR_MASK 0xffff
+#define PEER_REG_RANGE0__START_ADDR__SHIFT 0x0
+#define PEER_REG_RANGE0__END_ADDR_MASK 0xffff0000
+#define PEER_REG_RANGE0__END_ADDR__SHIFT 0x10
+#define PEER_REG_RANGE1__START_ADDR_MASK 0xffff
+#define PEER_REG_RANGE1__START_ADDR__SHIFT 0x0
+#define PEER_REG_RANGE1__END_ADDR_MASK 0xffff0000
+#define PEER_REG_RANGE1__END_ADDR__SHIFT 0x10
+#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0xfffff
+#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0
+#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0xfffff
+#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0
+#define PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000
+#define PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f
+#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0xfffff
+#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0
+#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0xfffff
+#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0
+#define PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000
+#define PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f
+#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0xfffff
+#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0
+#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0xfffff
+#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0
+#define PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000
+#define PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f
+#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0xfffff
+#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0
+#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0xfffff
+#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0
+#define PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000
+#define PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f
+#define DBG_BYPASS_SRBM_ACCESS__DBG_BYPASS_SRBM_ACCESS_EN_MASK 0x1
+#define DBG_BYPASS_SRBM_ACCESS__DBG_BYPASS_SRBM_ACCESS_EN__SHIFT 0x0
+#define DBG_BYPASS_SRBM_ACCESS__DBG_APER_AD_MASK 0x1e
+#define DBG_BYPASS_SRBM_ACCESS__DBG_APER_AD__SHIFT 0x1
+#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA_MASK 0xffffffff
+#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA__SHIFT 0x0
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0xff
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0xff00
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0xff0000
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xff000000
+#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0xff
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0xff00
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0xff0000
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xff000000
+#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18
+#define BACO_CNTL__BACO_EN_MASK 0x1
+#define BACO_CNTL__BACO_EN__SHIFT 0x0
+#define BACO_CNTL__BACO_BCLK_OFF_MASK 0x2
+#define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x1
+#define BACO_CNTL__BACO_ISO_DIS_MASK 0x4
+#define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x2
+#define BACO_CNTL__BACO_POWER_OFF_MASK 0x8
+#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3
+#define BACO_CNTL__BACO_RESET_EN_MASK 0x10
+#define BACO_CNTL__BACO_RESET_EN__SHIFT 0x4
+#define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x20
+#define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x5
+#define BACO_CNTL__BACO_MODE_MASK 0x40
+#define BACO_CNTL__BACO_MODE__SHIFT 0x6
+#define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x80
+#define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x7
+#define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x100
+#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x8
+#define BACO_CNTL__PWRGOOD_BF_MASK 0x200
+#define BACO_CNTL__PWRGOOD_BF__SHIFT 0x9
+#define BACO_CNTL__PWRGOOD_GPIO_MASK 0x400
+#define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0xa
+#define BACO_CNTL__PWRGOOD_MEM_MASK 0x800
+#define BACO_CNTL__PWRGOOD_MEM__SHIFT 0xb
+#define BACO_CNTL__PWRGOOD_DVO_MASK 0x1000
+#define BACO_CNTL__PWRGOOD_DVO__SHIFT 0xc
+#define BACO_CNTL__PWRGOOD_IDSC_MASK 0x2000
+#define BACO_CNTL__PWRGOOD_IDSC__SHIFT 0xd
+#define BACO_CNTL__BACO_POWER_OFF_DRAM_MASK 0x10000
+#define BACO_CNTL__BACO_POWER_OFF_DRAM__SHIFT 0x10
+#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL_MASK 0x20000
+#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL__SHIFT 0x11
+#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK_MASK 0x1
+#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK__SHIFT 0x0
+#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK 0x2
+#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK__SHIFT 0x1
+#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x1
+#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0
+#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG_MASK 0x1
+#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG__SHIFT 0x0
+#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG_MASK 0x1
+#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG__SHIFT 0x0
+#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x1
+#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0
+#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x2
+#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1
+#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL_MASK 0xc
+#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2
+#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK 0x1
+#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK 0x1
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x2
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK 0x4
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK 0x8
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK 0x10
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK 0x20
+#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5
+#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK 0xffc
+#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2
+#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK 0x80000000
+#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f
+#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK 0xffc
+#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2
+#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK 0xffc
+#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2
+#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK 0x80000000
+#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f
+#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK 0xffc
+#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2
+#define BIF_SMU_INDEX__BIF_SMU_INDEX_MASK 0x7fffc
+#define BIF_SMU_INDEX__BIF_SMU_INDEX__SHIFT 0x2
+#define BIF_SMU_DATA__BIF_SMU_DATA_MASK 0x7fffc
+#define BIF_SMU_DATA__BIF_SMU_DATA__SHIFT 0x2
+#define IMPCTL_RESET__IMP_SW_RESET_MASK 0x1
+#define IMPCTL_RESET__IMP_SW_RESET__SHIFT 0x0
+#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR_MASK 0x1
+#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR__SHIFT 0x0
+#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR_MASK 0x2
+#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR__SHIFT 0x1
+#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR_MASK 0x4
+#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR__SHIFT 0x2
+#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR_MASK 0x8
+#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR__SHIFT 0x3
+#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR_MASK 0x10
+#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR__SHIFT 0x4
+#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR_MASK 0x20
+#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR__SHIFT 0x5
+#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND_MASK 0x40
+#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND__SHIFT 0x6
+#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND_MASK 0x80
+#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND__SHIFT 0x7
+#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR_MASK 0x100
+#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR__SHIFT 0x8
+#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR_MASK 0x200
+#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR__SHIFT 0x9
+#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR_MASK 0x400
+#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR__SHIFT 0xa
+#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2_MASK 0x800
+#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2__SHIFT 0xb
+#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR_MASK 0x1000
+#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR__SHIFT 0xc
+#define GARLIC_FLUSH_CNTL__HOST_DOORBELL_MASK 0x2000
+#define GARLIC_FLUSH_CNTL__HOST_DOORBELL__SHIFT 0xd
+#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL_MASK 0x4000
+#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL__SHIFT 0xe
+#define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND_MASK 0x8000
+#define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND__SHIFT 0xf
+#define GARLIC_FLUSH_CNTL__DISPLAY_MASK 0x10000
+#define GARLIC_FLUSH_CNTL__DISPLAY__SHIFT 0x10
+#define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR_MASK 0x20000
+#define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR__SHIFT 0x11
+#define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR_MASK 0x40000
+#define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR__SHIFT 0x12
+#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE_MASK 0x40000000
+#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE__SHIFT 0x1e
+#define GARLIC_FLUSH_CNTL__DISABLE_ALL_MASK 0x80000000
+#define GARLIC_FLUSH_CNTL__DISABLE_ALL__SHIFT 0x1f
+#define GARLIC_FLUSH_ADDR_START_0__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_0__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_0__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_0__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_0__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_0__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_START_1__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_1__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_1__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_1__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_1__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_1__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_START_2__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_2__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_2__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_2__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_2__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_2__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_START_3__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_3__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_3__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_3__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_3__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_3__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_START_4__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_4__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_4__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_4__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_4__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_4__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_START_5__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_5__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_5__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_5__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_5__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_5__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_START_6__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_6__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_6__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_6__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_6__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_6__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_START_7__ENABLE_MASK 0x1
+#define GARLIC_FLUSH_ADDR_START_7__ENABLE__SHIFT 0x0
+#define GARLIC_FLUSH_ADDR_START_7__MODE_MASK 0x2
+#define GARLIC_FLUSH_ADDR_START_7__MODE__SHIFT 0x1
+#define GARLIC_FLUSH_ADDR_START_7__ADDR_START_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_START_7__ADDR_START__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_0__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_0__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_1__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_1__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_2__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_2__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_3__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_3__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_4__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_4__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_5__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_5__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_6__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_6__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_ADDR_END_7__ADDR_END_MASK 0xfffffffc
+#define GARLIC_FLUSH_ADDR_END_7__ADDR_END__SHIFT 0x2
+#define GARLIC_FLUSH_REQ__FLUSH_REQ_MASK 0x1
+#define GARLIC_FLUSH_REQ__FLUSH_REQ__SHIFT 0x0
+#define GPU_GARLIC_FLUSH_REQ__CP0_MASK 0x1
+#define GPU_GARLIC_FLUSH_REQ__CP0__SHIFT 0x0
+#define GPU_GARLIC_FLUSH_REQ__CP1_MASK 0x2
+#define GPU_GARLIC_FLUSH_REQ__CP1__SHIFT 0x1
+#define GPU_GARLIC_FLUSH_REQ__CP2_MASK 0x4
+#define GPU_GARLIC_FLUSH_REQ__CP2__SHIFT 0x2
+#define GPU_GARLIC_FLUSH_REQ__CP3_MASK 0x8
+#define GPU_GARLIC_FLUSH_REQ__CP3__SHIFT 0x3
+#define GPU_GARLIC_FLUSH_REQ__CP4_MASK 0x10
+#define GPU_GARLIC_FLUSH_REQ__CP4__SHIFT 0x4
+#define GPU_GARLIC_FLUSH_REQ__CP5_MASK 0x20
+#define GPU_GARLIC_FLUSH_REQ__CP5__SHIFT 0x5
+#define GPU_GARLIC_FLUSH_REQ__CP6_MASK 0x40
+#define GPU_GARLIC_FLUSH_REQ__CP6__SHIFT 0x6
+#define GPU_GARLIC_FLUSH_REQ__CP7_MASK 0x80
+#define GPU_GARLIC_FLUSH_REQ__CP7__SHIFT 0x7
+#define GPU_GARLIC_FLUSH_REQ__CP8_MASK 0x100
+#define GPU_GARLIC_FLUSH_REQ__CP8__SHIFT 0x8
+#define GPU_GARLIC_FLUSH_REQ__CP9_MASK 0x200
+#define GPU_GARLIC_FLUSH_REQ__CP9__SHIFT 0x9
+#define GPU_GARLIC_FLUSH_REQ__SDMA0_MASK 0x400
+#define GPU_GARLIC_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define GPU_GARLIC_FLUSH_REQ__SDMA1_MASK 0x800
+#define GPU_GARLIC_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define GPU_GARLIC_FLUSH_REQ__SDMA2_MASK 0x1000
+#define GPU_GARLIC_FLUSH_REQ__SDMA2__SHIFT 0xc
+#define GPU_GARLIC_FLUSH_REQ__SDMA3_MASK 0x2000
+#define GPU_GARLIC_FLUSH_REQ__SDMA3__SHIFT 0xd
+#define GPU_GARLIC_FLUSH_DONE__CP0_MASK 0x1
+#define GPU_GARLIC_FLUSH_DONE__CP0__SHIFT 0x0
+#define GPU_GARLIC_FLUSH_DONE__CP1_MASK 0x2
+#define GPU_GARLIC_FLUSH_DONE__CP1__SHIFT 0x1
+#define GPU_GARLIC_FLUSH_DONE__CP2_MASK 0x4
+#define GPU_GARLIC_FLUSH_DONE__CP2__SHIFT 0x2
+#define GPU_GARLIC_FLUSH_DONE__CP3_MASK 0x8
+#define GPU_GARLIC_FLUSH_DONE__CP3__SHIFT 0x3
+#define GPU_GARLIC_FLUSH_DONE__CP4_MASK 0x10
+#define GPU_GARLIC_FLUSH_DONE__CP4__SHIFT 0x4
+#define GPU_GARLIC_FLUSH_DONE__CP5_MASK 0x20
+#define GPU_GARLIC_FLUSH_DONE__CP5__SHIFT 0x5
+#define GPU_GARLIC_FLUSH_DONE__CP6_MASK 0x40
+#define GPU_GARLIC_FLUSH_DONE__CP6__SHIFT 0x6
+#define GPU_GARLIC_FLUSH_DONE__CP7_MASK 0x80
+#define GPU_GARLIC_FLUSH_DONE__CP7__SHIFT 0x7
+#define GPU_GARLIC_FLUSH_DONE__CP8_MASK 0x100
+#define GPU_GARLIC_FLUSH_DONE__CP8__SHIFT 0x8
+#define GPU_GARLIC_FLUSH_DONE__CP9_MASK 0x200
+#define GPU_GARLIC_FLUSH_DONE__CP9__SHIFT 0x9
+#define GPU_GARLIC_FLUSH_DONE__SDMA0_MASK 0x400
+#define GPU_GARLIC_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define GPU_GARLIC_FLUSH_DONE__SDMA1_MASK 0x800
+#define GPU_GARLIC_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define GPU_GARLIC_FLUSH_DONE__SDMA2_MASK 0x1000
+#define GPU_GARLIC_FLUSH_DONE__SDMA2__SHIFT 0xc
+#define GPU_GARLIC_FLUSH_DONE__SDMA3_MASK 0x2000
+#define GPU_GARLIC_FLUSH_DONE__SDMA3__SHIFT 0xd
+#define GARLIC_COHE_CP_RB0_WPTR__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_CP_RB0_WPTR__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_CP_RB1_WPTR__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_CP_RB1_WPTR__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_CP_RB2_WPTR__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_CP_RB2_WPTR__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_VCE_RB_WPTR2__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_VCE_RB_WPTR2__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_VCE_RB_WPTR__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_VCE_RB_WPTR__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_SDMA2_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_SDMA2_GFX_RB_WPTR__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_SDMA3_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_SDMA3_GFX_RB_WPTR__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_CP_DMA_PIO_COMMAND__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_CP_DMA_PIO_COMMAND__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_GARLIC_FLUSH_REQ__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_GARLIC_FLUSH_REQ__ADDRESS__SHIFT 0x2
+#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x7fffc
+#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x7fffc
+#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xffffffff
+#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0
+#define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xffffffff
+#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0
+#define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xffffffff
+#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0
+#define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xffffffff
+#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0
+#define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xffffffff
+#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0
+#define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xffffffff
+#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0
+#define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xffffffff
+#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0
+#define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xffffffff
+#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0
+#define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xffffffff
+#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0
+#define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xffffffff
+#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0
+#define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xffffffff
+#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0
+#define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xffffffff
+#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0
+#define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xffffffff
+#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0
+#define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xffffffff
+#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0
+#define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xffffffff
+#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0
+#define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xffffffff
+#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0
+#define BIF_RB_CNTL__RB_ENABLE_MASK 0x1
+#define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define BIF_RB_CNTL__RB_SIZE_MASK 0x3e
+#define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100
+#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
+#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00
+#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
+#define BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x20000
+#define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11
+#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
+#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define BIF_RB_BASE__ADDR_MASK 0xffffffff
+#define BIF_RB_BASE__ADDR__SHIFT 0x0
+#define BIF_RB_RPTR__OFFSET_MASK 0x3fffc
+#define BIF_RB_RPTR__OFFSET__SHIFT 0x2
+#define BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x1
+#define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0
+#define BIF_RB_WPTR__OFFSET_MASK 0x3fffc
+#define BIF_RB_WPTR__OFFSET__SHIFT 0x2
+#define BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0xff
+#define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define VENDOR_ID__VENDOR_ID_MASK 0xffff
+#define VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define DEVICE_ID__DEVICE_ID_MASK 0xffff
+#define DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define COMMAND__IO_ACCESS_EN_MASK 0x1
+#define COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define COMMAND__MEM_ACCESS_EN_MASK 0x2
+#define COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define COMMAND__BUS_MASTER_EN_MASK 0x4
+#define COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
+#define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
+#define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define COMMAND__PAL_SNOOP_EN_MASK 0x20
+#define COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
+#define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define COMMAND__AD_STEPPING_MASK 0x80
+#define COMMAND__AD_STEPPING__SHIFT 0x7
+#define COMMAND__SERR_EN_MASK 0x100
+#define COMMAND__SERR_EN__SHIFT 0x8
+#define COMMAND__FAST_B2B_EN_MASK 0x200
+#define COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define COMMAND__INT_DIS_MASK 0x400
+#define COMMAND__INT_DIS__SHIFT 0xa
+#define STATUS__INT_STATUS_MASK 0x8
+#define STATUS__INT_STATUS__SHIFT 0x3
+#define STATUS__CAP_LIST_MASK 0x10
+#define STATUS__CAP_LIST__SHIFT 0x4
+#define STATUS__PCI_66_EN_MASK 0x20
+#define STATUS__PCI_66_EN__SHIFT 0x5
+#define STATUS__FAST_BACK_CAPABLE_MASK 0x80
+#define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x100
+#define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define STATUS__DEVSEL_TIMING_MASK 0x600
+#define STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define STATUS__SIGNAL_TARGET_ABORT_MASK 0x800
+#define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000
+#define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000
+#define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000
+#define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define STATUS__PARITY_ERROR_DETECTED_MASK 0x8000
+#define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define REVISION_ID__MINOR_REV_ID_MASK 0xf
+#define REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define REVISION_ID__MAJOR_REV_ID_MASK 0xf0
+#define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define PROG_INTERFACE__PROG_INTERFACE_MASK 0xff
+#define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define SUB_CLASS__SUB_CLASS_MASK 0xff
+#define SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BASE_CLASS__BASE_CLASS_MASK 0xff
+#define BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
+#define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define LATENCY__LATENCY_TIMER_MASK 0xff
+#define LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define HEADER__HEADER_TYPE_MASK 0x7f
+#define HEADER__HEADER_TYPE__SHIFT 0x0
+#define HEADER__DEVICE_TYPE_MASK 0x80
+#define HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIST__BIST_COMP_MASK 0xf
+#define BIST__BIST_COMP__SHIFT 0x0
+#define BIST__BIST_STRT_MASK 0x40
+#define BIST__BIST_STRT__SHIFT 0x6
+#define BIST__BIST_CAP_MASK 0x80
+#define BIST__BIST_CAP__SHIFT 0x7
+#define BASE_ADDR_1__BASE_ADDR_MASK 0xffffffff
+#define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BASE_ADDR_2__BASE_ADDR_MASK 0xffffffff
+#define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BASE_ADDR_3__BASE_ADDR_MASK 0xffffffff
+#define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BASE_ADDR_4__BASE_ADDR_MASK 0xffffffff
+#define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BASE_ADDR_5__BASE_ADDR_MASK 0xffffffff
+#define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BASE_ADDR_6__BASE_ADDR_MASK 0xffffffff
+#define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define ROM_BASE_ADDR__BASE_ADDR_MASK 0xffffffff
+#define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define CAP_PTR__CAP_PTR_MASK 0xff
+#define CAP_PTR__CAP_PTR__SHIFT 0x0
+#define INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
+#define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff
+#define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0xffff
+#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define ADAPTER_ID__SUBSYSTEM_ID_MASK 0xffff0000
+#define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define MIN_GRANT__MIN_GNT_MASK 0xff
+#define MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define MAX_LATENCY__MAX_LAT_MASK 0xff
+#define MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define VENDOR_CAP_LIST__CAP_ID_MASK 0xff
+#define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define VENDOR_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define VENDOR_CAP_LIST__LENGTH_MASK 0xff0000
+#define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0xffff
+#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xffff0000
+#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define PMI_CAP_LIST__CAP_ID_MASK 0xff
+#define PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PMI_CAP__VERSION_MASK 0x7
+#define PMI_CAP__VERSION__SHIFT 0x0
+#define PMI_CAP__PME_CLOCK_MASK 0x8
+#define PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x20
+#define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define PMI_CAP__AUX_CURRENT_MASK 0x1c0
+#define PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define PMI_CAP__D1_SUPPORT_MASK 0x200
+#define PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define PMI_CAP__D2_SUPPORT_MASK 0x400
+#define PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define PMI_CAP__PME_SUPPORT_MASK 0xf800
+#define PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
+#define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
+#define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define PMI_STATUS_CNTL__PME_EN_MASK 0x100
+#define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
+#define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
+#define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
+#define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
+#define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
+#define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
+#define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define PCIE_CAP_LIST__CAP_ID_MASK 0xff
+#define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define PCIE_CAP__VERSION_MASK 0xf
+#define PCIE_CAP__VERSION__SHIFT 0x0
+#define PCIE_CAP__DEVICE_TYPE_MASK 0xf0
+#define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x100
+#define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e00
+#define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
+#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
+#define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define DEVICE_CAP__EXTENDED_TAG_MASK 0x20
+#define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
+#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
+#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
+#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
+#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
+#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
+#define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
+#define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
+#define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
+#define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
+#define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
+#define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
+#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
+#define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
+#define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
+#define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
+#define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
+#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define DEVICE_CNTL__INITIATE_FLR_MASK 0x8000
+#define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define DEVICE_STATUS__CORR_ERR_MASK 0x1
+#define DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define DEVICE_STATUS__NON_FATAL_ERR_MASK 0x2
+#define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define DEVICE_STATUS__FATAL_ERR_MASK 0x4
+#define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define DEVICE_STATUS__USR_DETECTED_MASK 0x8
+#define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define DEVICE_STATUS__AUX_PWR_MASK 0x10
+#define DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x20
+#define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define LINK_CAP__LINK_SPEED_MASK 0xf
+#define LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define LINK_CAP__LINK_WIDTH_MASK 0x3f0
+#define LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define LINK_CAP__PM_SUPPORT_MASK 0xc00
+#define LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
+#define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
+#define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
+#define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
+#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
+#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
+#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
+#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define LINK_CAP__PORT_NUMBER_MASK 0xff000000
+#define LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define LINK_CNTL__PM_CONTROL_MASK 0x3
+#define LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
+#define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define LINK_CNTL__LINK_DIS_MASK 0x10
+#define LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define LINK_CNTL__RETRAIN_LINK_MASK 0x20
+#define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
+#define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define LINK_CNTL__EXTENDED_SYNC_MASK 0x80
+#define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
+#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
+#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
+#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
+#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf
+#define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f0
+#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define LINK_STATUS__LINK_TRAINING_MASK 0x800
+#define LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000
+#define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define LINK_STATUS__DL_ACTIVE_MASK 0x2000
+#define LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000
+#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000
+#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
+#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
+#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
+#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
+#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
+#define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
+#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
+#define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
+#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
+#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
+#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
+#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
+#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
+#define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
+#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
+#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define DEVICE_CNTL2__LTR_EN_MASK 0x400
+#define DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define DEVICE_CNTL2__OBFF_EN_MASK 0x6000
+#define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
+#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define DEVICE_STATUS2__RESERVED_MASK 0xffff
+#define DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
+#define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
+#define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define LINK_CAP2__RESERVED_MASK 0xfffffe00
+#define LINK_CAP2__RESERVED__SHIFT 0x9
+#define LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
+#define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
+#define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
+#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
+#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define LINK_CNTL2__XMIT_MARGIN_MASK 0x380
+#define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
+#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
+#define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
+#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x1
+#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x2
+#define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
+#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x4
+#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
+#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x8
+#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
+#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x10
+#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
+#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x20
+#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
+#define MSI_CAP_LIST__CAP_ID_MASK 0xff
+#define MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define MSI_MSG_CNTL__MSI_EN_MASK 0x1
+#define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe
+#define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x70
+#define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define MSI_MSG_CNTL__MSI_64BIT_MASK 0x80
+#define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
+#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
+#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
+#define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define MSI_MSG_DATA__MSI_DATA_MASK 0xffff
+#define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
+#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
+#define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
+#define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
+#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
+#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
+#define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
+#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
+#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
+#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
+#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
+#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x1
+#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1
+#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2
+#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1
+#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2
+#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
+#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
+#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
+#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
+#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
+#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
+#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
+#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
+#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
+#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
+#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
+#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
+#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
+#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
+#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
+#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
+#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
+#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
+#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
+#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
+#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
+#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
+#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
+#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
+#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
+#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
+#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
+#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
+#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
+#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
+#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
+#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
+#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
+#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
+#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
+#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
+#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
+#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
+#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
+#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
+#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
+#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
+#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
+#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
+#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
+#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
+#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
+#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
+#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
+#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
+#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
+#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
+#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
+#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
+#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
+#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
+#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
+#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
+#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
+#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
+#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
+#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
+#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
+#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
+#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
+#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
+#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
+#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
+#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
+#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
+#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
+#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
+#define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
+#define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
+#define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
+#define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
+#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
+#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
+#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
+#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
+#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x7
+#define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0xe0
+#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1f00
+#define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
+#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x7
+#define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0xe0
+#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1f00
+#define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
+#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x7
+#define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0xe0
+#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1f00
+#define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
+#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x7
+#define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0xe0
+#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1f00
+#define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
+#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x7
+#define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0xe0
+#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1f00
+#define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
+#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x7
+#define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0xe0
+#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1f00
+#define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xff
+#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0xff
+#define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x300
+#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x1c00
+#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x6000
+#define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x38000
+#define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x1c0000
+#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x1
+#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x1f
+#define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300
+#define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000
+#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff
+#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x1f
+#define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x100
+#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1f
+#define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
+#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
+#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
+#define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
+#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
+#define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
+#define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
+#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
+#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
+#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
+#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
+#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
+#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
+#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x1
+#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x2
+#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x4
+#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x8
+#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x10
+#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x20
+#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x40
+#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x1f
+#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x20
+#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x40
+#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define PCIE_ATS_CNTL__STU_MASK 0x1f
+#define PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000
+#define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x1
+#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x2
+#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x1
+#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x2
+#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x100
+#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000
+#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xffffffff
+#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xffffffff
+#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2
+#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x4
+#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1f00
+#define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x1
+#define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x2
+#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x4
+#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x1
+#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x2
+#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x4
+#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x100
+#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x600
+#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x7ff0000
+#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x7
+#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x300
+#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
+#define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3f00
+#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
+#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f
+#define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000
+#define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
+#define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
+#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
+#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
+#define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
+#define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
+#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
+#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
+#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
+#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x3ff
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x1c00
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x3ff0000
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1c000000
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define MM_INDEX_IND__MM_OFFSET_MASK 0x7fffffff
+#define MM_INDEX_IND__MM_OFFSET__SHIFT 0x0
+#define MM_INDEX_IND__MM_APER_MASK 0x80000000
+#define MM_INDEX_IND__MM_APER__SHIFT 0x1f
+#define MM_INDEX_HI_IND__MM_OFFSET_HI_MASK 0xffffffff
+#define MM_INDEX_HI_IND__MM_OFFSET_HI__SHIFT 0x0
+#define MM_DATA_IND__MM_DATA_MASK 0xffffffff
+#define MM_DATA_IND__MM_DATA__SHIFT 0x0
+#define BIF_MM_INDACCESS_CNTL_IND__MM_INDACCESS_DIS_MASK 0x2
+#define BIF_MM_INDACCESS_CNTL_IND__MM_INDACCESS_DIS__SHIFT 0x1
+#define BUS_CNTL_IND__BIOS_ROM_WRT_EN_MASK 0x1
+#define BUS_CNTL_IND__BIOS_ROM_WRT_EN__SHIFT 0x0
+#define BUS_CNTL_IND__BIOS_ROM_DIS_MASK 0x2
+#define BUS_CNTL_IND__BIOS_ROM_DIS__SHIFT 0x1
+#define BUS_CNTL_IND__PMI_IO_DIS_MASK 0x4
+#define BUS_CNTL_IND__PMI_IO_DIS__SHIFT 0x2
+#define BUS_CNTL_IND__PMI_MEM_DIS_MASK 0x8
+#define BUS_CNTL_IND__PMI_MEM_DIS__SHIFT 0x3
+#define BUS_CNTL_IND__PMI_BM_DIS_MASK 0x10
+#define BUS_CNTL_IND__PMI_BM_DIS__SHIFT 0x4
+#define BUS_CNTL_IND__PMI_INT_DIS_MASK 0x20
+#define BUS_CNTL_IND__PMI_INT_DIS__SHIFT 0x5
+#define BUS_CNTL_IND__VGA_REG_COHERENCY_DIS_MASK 0x40
+#define BUS_CNTL_IND__VGA_REG_COHERENCY_DIS__SHIFT 0x6
+#define BUS_CNTL_IND__VGA_MEM_COHERENCY_DIS_MASK 0x80
+#define BUS_CNTL_IND__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
+#define BUS_CNTL_IND__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100
+#define BUS_CNTL_IND__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8
+#define BUS_CNTL_IND__SET_AZ_TC_MASK 0x1c00
+#define BUS_CNTL_IND__SET_AZ_TC__SHIFT 0xa
+#define BUS_CNTL_IND__SET_MC_TC_MASK 0xe000
+#define BUS_CNTL_IND__SET_MC_TC__SHIFT 0xd
+#define BUS_CNTL_IND__ZERO_BE_WR_EN_MASK 0x10000
+#define BUS_CNTL_IND__ZERO_BE_WR_EN__SHIFT 0x10
+#define BUS_CNTL_IND__ZERO_BE_RD_EN_MASK 0x20000
+#define BUS_CNTL_IND__ZERO_BE_RD_EN__SHIFT 0x11
+#define BUS_CNTL_IND__RD_STALL_IO_WR_MASK 0x40000
+#define BUS_CNTL_IND__RD_STALL_IO_WR__SHIFT 0x12
+#define CONFIG_CNTL_IND__CFG_VGA_RAM_EN_MASK 0x1
+#define CONFIG_CNTL_IND__CFG_VGA_RAM_EN__SHIFT 0x0
+#define CONFIG_CNTL_IND__VGA_DIS_MASK 0x2
+#define CONFIG_CNTL_IND__VGA_DIS__SHIFT 0x1
+#define CONFIG_CNTL_IND__GENMO_MONO_ADDRESS_B_MASK 0x4
+#define CONFIG_CNTL_IND__GENMO_MONO_ADDRESS_B__SHIFT 0x2
+#define CONFIG_CNTL_IND__GRPH_ADRSEL_MASK 0x18
+#define CONFIG_CNTL_IND__GRPH_ADRSEL__SHIFT 0x3
+#define CONFIG_MEMSIZE_IND__CONFIG_MEMSIZE_MASK 0xffffffff
+#define CONFIG_MEMSIZE_IND__CONFIG_MEMSIZE__SHIFT 0x0
+#define CONFIG_F0_BASE_IND__F0_BASE_MASK 0xffffffff
+#define CONFIG_F0_BASE_IND__F0_BASE__SHIFT 0x0
+#define CONFIG_APER_SIZE_IND__APER_SIZE_MASK 0xffffffff
+#define CONFIG_APER_SIZE_IND__APER_SIZE__SHIFT 0x0
+#define CONFIG_REG_APER_SIZE_IND__REG_APER_SIZE_MASK 0xfffff
+#define CONFIG_REG_APER_SIZE_IND__REG_APER_SIZE__SHIFT 0x0
+#define BIF_SCRATCH0_IND__BIF_SCRATCH0_MASK 0xffffffff
+#define BIF_SCRATCH0_IND__BIF_SCRATCH0__SHIFT 0x0
+#define BIF_SCRATCH1_IND__BIF_SCRATCH1_MASK 0xffffffff
+#define BIF_SCRATCH1_IND__BIF_SCRATCH1__SHIFT 0x0
+#define BX_RESET_EN_IND__COR_RESET_EN_MASK 0x1
+#define BX_RESET_EN_IND__COR_RESET_EN__SHIFT 0x0
+#define BX_RESET_EN_IND__REG_RESET_EN_MASK 0x2
+#define BX_RESET_EN_IND__REG_RESET_EN__SHIFT 0x1
+#define BX_RESET_EN_IND__STY_RESET_EN_MASK 0x4
+#define BX_RESET_EN_IND__STY_RESET_EN__SHIFT 0x2
+#define MM_CFGREGS_CNTL_IND__MM_CFG_FUNC_SEL_MASK 0x7
+#define MM_CFGREGS_CNTL_IND__MM_CFG_FUNC_SEL__SHIFT 0x0
+#define MM_CFGREGS_CNTL_IND__MM_WR_TO_CFG_EN_MASK 0x8
+#define MM_CFGREGS_CNTL_IND__MM_WR_TO_CFG_EN__SHIFT 0x3
+#define HW_DEBUG_IND__HW_00_DEBUG_MASK 0x1
+#define HW_DEBUG_IND__HW_00_DEBUG__SHIFT 0x0
+#define HW_DEBUG_IND__HW_01_DEBUG_MASK 0x2
+#define HW_DEBUG_IND__HW_01_DEBUG__SHIFT 0x1
+#define HW_DEBUG_IND__HW_02_DEBUG_MASK 0x4
+#define HW_DEBUG_IND__HW_02_DEBUG__SHIFT 0x2
+#define HW_DEBUG_IND__HW_03_DEBUG_MASK 0x8
+#define HW_DEBUG_IND__HW_03_DEBUG__SHIFT 0x3
+#define HW_DEBUG_IND__HW_04_DEBUG_MASK 0x10
+#define HW_DEBUG_IND__HW_04_DEBUG__SHIFT 0x4
+#define HW_DEBUG_IND__HW_05_DEBUG_MASK 0x20
+#define HW_DEBUG_IND__HW_05_DEBUG__SHIFT 0x5
+#define HW_DEBUG_IND__HW_06_DEBUG_MASK 0x40
+#define HW_DEBUG_IND__HW_06_DEBUG__SHIFT 0x6
+#define HW_DEBUG_IND__HW_07_DEBUG_MASK 0x80
+#define HW_DEBUG_IND__HW_07_DEBUG__SHIFT 0x7
+#define HW_DEBUG_IND__HW_08_DEBUG_MASK 0x100
+#define HW_DEBUG_IND__HW_08_DEBUG__SHIFT 0x8
+#define HW_DEBUG_IND__HW_09_DEBUG_MASK 0x200
+#define HW_DEBUG_IND__HW_09_DEBUG__SHIFT 0x9
+#define HW_DEBUG_IND__HW_10_DEBUG_MASK 0x400
+#define HW_DEBUG_IND__HW_10_DEBUG__SHIFT 0xa
+#define HW_DEBUG_IND__HW_11_DEBUG_MASK 0x800
+#define HW_DEBUG_IND__HW_11_DEBUG__SHIFT 0xb
+#define HW_DEBUG_IND__HW_12_DEBUG_MASK 0x1000
+#define HW_DEBUG_IND__HW_12_DEBUG__SHIFT 0xc
+#define HW_DEBUG_IND__HW_13_DEBUG_MASK 0x2000
+#define HW_DEBUG_IND__HW_13_DEBUG__SHIFT 0xd
+#define HW_DEBUG_IND__HW_14_DEBUG_MASK 0x4000
+#define HW_DEBUG_IND__HW_14_DEBUG__SHIFT 0xe
+#define HW_DEBUG_IND__HW_15_DEBUG_MASK 0x8000
+#define HW_DEBUG_IND__HW_15_DEBUG__SHIFT 0xf
+#define HW_DEBUG_IND__HW_16_DEBUG_MASK 0x10000
+#define HW_DEBUG_IND__HW_16_DEBUG__SHIFT 0x10
+#define HW_DEBUG_IND__HW_17_DEBUG_MASK 0x20000
+#define HW_DEBUG_IND__HW_17_DEBUG__SHIFT 0x11
+#define HW_DEBUG_IND__HW_18_DEBUG_MASK 0x40000
+#define HW_DEBUG_IND__HW_18_DEBUG__SHIFT 0x12
+#define HW_DEBUG_IND__HW_19_DEBUG_MASK 0x80000
+#define HW_DEBUG_IND__HW_19_DEBUG__SHIFT 0x13
+#define HW_DEBUG_IND__HW_20_DEBUG_MASK 0x100000
+#define HW_DEBUG_IND__HW_20_DEBUG__SHIFT 0x14
+#define HW_DEBUG_IND__HW_21_DEBUG_MASK 0x200000
+#define HW_DEBUG_IND__HW_21_DEBUG__SHIFT 0x15
+#define HW_DEBUG_IND__HW_22_DEBUG_MASK 0x400000
+#define HW_DEBUG_IND__HW_22_DEBUG__SHIFT 0x16
+#define HW_DEBUG_IND__HW_23_DEBUG_MASK 0x800000
+#define HW_DEBUG_IND__HW_23_DEBUG__SHIFT 0x17
+#define HW_DEBUG_IND__HW_24_DEBUG_MASK 0x1000000
+#define HW_DEBUG_IND__HW_24_DEBUG__SHIFT 0x18
+#define HW_DEBUG_IND__HW_25_DEBUG_MASK 0x2000000
+#define HW_DEBUG_IND__HW_25_DEBUG__SHIFT 0x19
+#define HW_DEBUG_IND__HW_26_DEBUG_MASK 0x4000000
+#define HW_DEBUG_IND__HW_26_DEBUG__SHIFT 0x1a
+#define HW_DEBUG_IND__HW_27_DEBUG_MASK 0x8000000
+#define HW_DEBUG_IND__HW_27_DEBUG__SHIFT 0x1b
+#define HW_DEBUG_IND__HW_28_DEBUG_MASK 0x10000000
+#define HW_DEBUG_IND__HW_28_DEBUG__SHIFT 0x1c
+#define HW_DEBUG_IND__HW_29_DEBUG_MASK 0x20000000
+#define HW_DEBUG_IND__HW_29_DEBUG__SHIFT 0x1d
+#define HW_DEBUG_IND__HW_30_DEBUG_MASK 0x40000000
+#define HW_DEBUG_IND__HW_30_DEBUG__SHIFT 0x1e
+#define HW_DEBUG_IND__HW_31_DEBUG_MASK 0x80000000
+#define HW_DEBUG_IND__HW_31_DEBUG__SHIFT 0x1f
+#define MASTER_CREDIT_CNTL_IND__BIF_MC_RDRET_CREDIT_MASK 0x7f
+#define MASTER_CREDIT_CNTL_IND__BIF_MC_RDRET_CREDIT__SHIFT 0x0
+#define MASTER_CREDIT_CNTL_IND__BIF_AZ_RDRET_CREDIT_MASK 0x3f0000
+#define MASTER_CREDIT_CNTL_IND__BIF_AZ_RDRET_CREDIT__SHIFT 0x10
+#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_SRBM_REQ_CREDIT_MASK 0x1f
+#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_SRBM_REQ_CREDIT__SHIFT 0x0
+#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_VGA_REQ_CREDIT_MASK 0x1e0
+#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_VGA_REQ_CREDIT__SHIFT 0x5
+#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_HDP_REQ_CREDIT_MASK 0x7c00
+#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_HDP_REQ_CREDIT__SHIFT 0xa
+#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_ROM_REQ_CREDIT_MASK 0x8000
+#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_ROM_REQ_CREDIT__SHIFT 0xf
+#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_AZ_REQ_CREDIT_MASK 0x100000
+#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_AZ_REQ_CREDIT__SHIFT 0x14
+#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_XDMA_REQ_CREDIT_MASK 0x7e000000
+#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_XDMA_REQ_CREDIT__SHIFT 0x19
+#define BX_RESET_CNTL_IND__LINK_TRAIN_EN_MASK 0x1
+#define BX_RESET_CNTL_IND__LINK_TRAIN_EN__SHIFT 0x0
+#define INTERRUPT_CNTL_IND__IH_DUMMY_RD_OVERRIDE_MASK 0x1
+#define INTERRUPT_CNTL_IND__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
+#define INTERRUPT_CNTL_IND__IH_DUMMY_RD_EN_MASK 0x2
+#define INTERRUPT_CNTL_IND__IH_DUMMY_RD_EN__SHIFT 0x1
+#define INTERRUPT_CNTL_IND__IH_REQ_NONSNOOP_EN_MASK 0x8
+#define INTERRUPT_CNTL_IND__IH_REQ_NONSNOOP_EN__SHIFT 0x3
+#define INTERRUPT_CNTL_IND__IH_INTR_DLY_CNTR_MASK 0xf0
+#define INTERRUPT_CNTL_IND__IH_INTR_DLY_CNTR__SHIFT 0x4
+#define INTERRUPT_CNTL_IND__GEN_IH_INT_EN_MASK 0x100
+#define INTERRUPT_CNTL_IND__GEN_IH_INT_EN__SHIFT 0x8
+#define INTERRUPT_CNTL_IND__GEN_GPIO_INT_EN_MASK 0x1e00
+#define INTERRUPT_CNTL_IND__GEN_GPIO_INT_EN__SHIFT 0x9
+#define INTERRUPT_CNTL_IND__SELECT_INT_GPIO_OUTPUT_MASK 0x6000
+#define INTERRUPT_CNTL_IND__SELECT_INT_GPIO_OUTPUT__SHIFT 0xd
+#define INTERRUPT_CNTL_IND__BIF_RB_REQ_NONSNOOP_EN_MASK 0x8000
+#define INTERRUPT_CNTL_IND__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf
+#define INTERRUPT_CNTL2_IND__IH_DUMMY_RD_ADDR_MASK 0xffffffff
+#define INTERRUPT_CNTL2_IND__IH_DUMMY_RD_ADDR__SHIFT 0x0
+#define BIF_DEBUG_CNTL_IND__DEBUG_EN_MASK 0x1
+#define BIF_DEBUG_CNTL_IND__DEBUG_EN__SHIFT 0x0
+#define BIF_DEBUG_CNTL_IND__DEBUG_MULTIBLOCKEN_MASK 0x2
+#define BIF_DEBUG_CNTL_IND__DEBUG_MULTIBLOCKEN__SHIFT 0x1
+#define BIF_DEBUG_CNTL_IND__DEBUG_OUT_EN_MASK 0x4
+#define BIF_DEBUG_CNTL_IND__DEBUG_OUT_EN__SHIFT 0x2
+#define BIF_DEBUG_CNTL_IND__DEBUG_PAD_SEL_MASK 0x8
+#define BIF_DEBUG_CNTL_IND__DEBUG_PAD_SEL__SHIFT 0x3
+#define BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK1_MASK 0x10
+#define BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK1__SHIFT 0x4
+#define BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK2_MASK 0x20
+#define BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK2__SHIFT 0x5
+#define BIF_DEBUG_CNTL_IND__DEBUG_SYNC_EN_MASK 0x40
+#define BIF_DEBUG_CNTL_IND__DEBUG_SYNC_EN__SHIFT 0x6
+#define BIF_DEBUG_CNTL_IND__DEBUG_SWAP_MASK 0x80
+#define BIF_DEBUG_CNTL_IND__DEBUG_SWAP__SHIFT 0x7
+#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK1_MASK 0x1f00
+#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK1__SHIFT 0x8
+#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK2_MASK 0x1f0000
+#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK2__SHIFT 0x10
+#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_XSP_MASK 0x1000000
+#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_XSP__SHIFT 0x18
+#define BIF_DEBUG_CNTL_IND__DEBUG_SYNC_CLKSEL_MASK 0xc0000000
+#define BIF_DEBUG_CNTL_IND__DEBUG_SYNC_CLKSEL__SHIFT 0x1e
+#define BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK1_MASK 0x3f
+#define BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK1__SHIFT 0x0
+#define BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK2_MASK 0x3f00
+#define BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK2__SHIFT 0x8
+#define BIF_DEBUG_OUT_IND__DEBUG_OUTPUT_MASK 0x1ffff
+#define BIF_DEBUG_OUT_IND__DEBUG_OUTPUT__SHIFT 0x0
+#define HDP_REG_COHERENCY_FLUSH_CNTL_IND__HDP_REG_FLUSH_ADDR_MASK 0x1
+#define HDP_REG_COHERENCY_FLUSH_CNTL_IND__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define HDP_MEM_COHERENCY_FLUSH_CNTL_IND__HDP_MEM_FLUSH_ADDR_MASK 0x1
+#define HDP_MEM_COHERENCY_FLUSH_CNTL_IND__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_A_MASK 0x1
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_A__SHIFT 0x0
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SEL_MASK 0x2
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SEL__SHIFT 0x1
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_MODE_MASK 0x4
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_MODE__SHIFT 0x2
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SPARE_MASK 0x18
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SPARE__SHIFT 0x3
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN0_MASK 0x20
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN0__SHIFT 0x5
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN1_MASK 0x40
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN1__SHIFT 0x6
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN2_MASK 0x80
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN2__SHIFT 0x7
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN3_MASK 0x100
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN3__SHIFT 0x8
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SLEWN_MASK 0x200
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SLEWN__SHIFT 0x9
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_WAKE_MASK 0x400
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_WAKE__SHIFT 0xa
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SCHMEN_MASK 0x800
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SCHMEN__SHIFT 0xb
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_CNTL_EN_MASK 0x1000
+#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_A_MASK 0x1
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_A__SHIFT 0x0
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SEL_MASK 0x2
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SEL__SHIFT 0x1
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_MODE_MASK 0x4
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_MODE__SHIFT 0x2
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SPARE_MASK 0x18
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SPARE__SHIFT 0x3
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN0_MASK 0x20
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN0__SHIFT 0x5
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN1_MASK 0x40
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN1__SHIFT 0x6
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN2_MASK 0x80
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN2__SHIFT 0x7
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN3_MASK 0x100
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN3__SHIFT 0x8
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SLEWN_MASK 0x200
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SLEWN__SHIFT 0x9
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_WAKE_MASK 0x400
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_WAKE__SHIFT 0xa
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SCHMEN_MASK 0x800
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SCHMEN__SHIFT 0xb
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_CNTL_EN_MASK 0x1000
+#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_CNTL_EN__SHIFT 0xc
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_A_MASK 0x1
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_A__SHIFT 0x0
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SEL_MASK 0x2
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SEL__SHIFT 0x1
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_MODE_MASK 0x4
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_MODE__SHIFT 0x2
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SPARE_MASK 0x18
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SPARE__SHIFT 0x3
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN0_MASK 0x20
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN0__SHIFT 0x5
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN1_MASK 0x40
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN1__SHIFT 0x6
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN2_MASK 0x80
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN2__SHIFT 0x7
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN3_MASK 0x100
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN3__SHIFT 0x8
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SLEWN_MASK 0x200
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SLEWN__SHIFT 0x9
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_WAKE_MASK 0x400
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_WAKE__SHIFT 0xa
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SCHMEN_MASK 0x800
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SCHMEN__SHIFT 0xb
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_CNTL_EN_MASK 0x1000
+#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_CNTL_EN__SHIFT 0xc
+#define BIF_XDMA_LO_IND__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffff
+#define BIF_XDMA_LO_IND__BIF_XDMA_LOWER_BOUND__SHIFT 0x0
+#define BIF_XDMA_LO_IND__BIF_XDMA_APER_EN_MASK 0x80000000
+#define BIF_XDMA_LO_IND__BIF_XDMA_APER_EN__SHIFT 0x1f
+#define BIF_XDMA_HI_IND__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffff
+#define BIF_XDMA_HI_IND__BIF_XDMA_UPPER_BOUND__SHIFT 0x0
+#define BIF_FEATURES_CONTROL_MISC_IND__MST_BIF_REQ_EP_DIS_MASK 0x1
+#define BIF_FEATURES_CONTROL_MISC_IND__MST_BIF_REQ_EP_DIS__SHIFT 0x0
+#define BIF_FEATURES_CONTROL_MISC_IND__SLV_BIF_CPL_EP_DIS_MASK 0x2
+#define BIF_FEATURES_CONTROL_MISC_IND__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
+#define BIF_FEATURES_CONTROL_MISC_IND__BIF_SLV_REQ_EP_DIS_MASK 0x4
+#define BIF_FEATURES_CONTROL_MISC_IND__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
+#define BIF_FEATURES_CONTROL_MISC_IND__BIF_MST_CPL_EP_DIS_MASK 0x8
+#define BIF_FEATURES_CONTROL_MISC_IND__BIF_MST_CPL_EP_DIS__SHIFT 0x3
+#define BIF_FEATURES_CONTROL_MISC_IND__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x10
+#define BIF_FEATURES_CONTROL_MISC_IND__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4
+#define BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x20
+#define BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5
+#define BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x40
+#define BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6
+#define BIF_FEATURES_CONTROL_MISC_IND__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x80
+#define BIF_FEATURES_CONTROL_MISC_IND__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x7
+#define BIF_FEATURES_CONTROL_MISC_IND__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x100
+#define BIF_FEATURES_CONTROL_MISC_IND__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x8
+#define BIF_FEATURES_CONTROL_MISC_IND__MC_BIF_REQ_ID_ROUTING_DIS_MASK 0x200
+#define BIF_FEATURES_CONTROL_MISC_IND__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9
+#define BIF_FEATURES_CONTROL_MISC_IND__AZ_BIF_REQ_ID_ROUTING_DIS_MASK 0x400
+#define BIF_FEATURES_CONTROL_MISC_IND__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa
+#define BIF_FEATURES_CONTROL_MISC_IND__ATC_PRG_RESP_PASID_UR_EN_MASK 0x800
+#define BIF_FEATURES_CONTROL_MISC_IND__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb
+#define BIF_FEATURES_CONTROL_MISC_IND__BIF_RB_SET_OVERFLOW_EN_MASK 0x1000
+#define BIF_FEATURES_CONTROL_MISC_IND__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc
+#define BIF_DOORBELL_CNTL_IND__SELF_RING_DIS_MASK 0x1
+#define BIF_DOORBELL_CNTL_IND__SELF_RING_DIS__SHIFT 0x0
+#define BIF_DOORBELL_CNTL_IND__TRANS_CHECK_DIS_MASK 0x2
+#define BIF_DOORBELL_CNTL_IND__TRANS_CHECK_DIS__SHIFT 0x1
+#define BIF_DOORBELL_CNTL_IND__UNTRANS_LBACK_EN_MASK 0x4
+#define BIF_DOORBELL_CNTL_IND__UNTRANS_LBACK_EN__SHIFT 0x2
+#define BIF_DOORBELL_CNTL_IND__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x8
+#define BIF_DOORBELL_CNTL_IND__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
+#define BIF_DOORBELL_CNTL_IND__DOORBELL_MONITOR_EN_MASK 0x10
+#define BIF_DOORBELL_CNTL_IND__DOORBELL_MONITOR_EN__SHIFT 0x4
+#define BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_STATUS_MASK 0x20
+#define BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_STATUS__SHIFT 0x5
+#define BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_CLEAR_MASK 0x10000
+#define BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10
+#define BIF_SLVARB_MODE_IND__SLVARB_MODE_MASK 0x3
+#define BIF_SLVARB_MODE_IND__SLVARB_MODE__SHIFT 0x0
+#define BIF_FB_EN_IND__FB_READ_EN_MASK 0x1
+#define BIF_FB_EN_IND__FB_READ_EN__SHIFT 0x0
+#define BIF_FB_EN_IND__FB_WRITE_EN_MASK 0x2
+#define BIF_FB_EN_IND__FB_WRITE_EN__SHIFT 0x1
+#define BIF_BUSNUM_CNTL1_IND__ID_MASK_MASK 0xff
+#define BIF_BUSNUM_CNTL1_IND__ID_MASK__SHIFT 0x0
+#define BIF_BUSNUM_LIST0_IND__ID0_MASK 0xff
+#define BIF_BUSNUM_LIST0_IND__ID0__SHIFT 0x0
+#define BIF_BUSNUM_LIST0_IND__ID1_MASK 0xff00
+#define BIF_BUSNUM_LIST0_IND__ID1__SHIFT 0x8
+#define BIF_BUSNUM_LIST0_IND__ID2_MASK 0xff0000
+#define BIF_BUSNUM_LIST0_IND__ID2__SHIFT 0x10
+#define BIF_BUSNUM_LIST0_IND__ID3_MASK 0xff000000
+#define BIF_BUSNUM_LIST0_IND__ID3__SHIFT 0x18
+#define BIF_BUSNUM_LIST1_IND__ID4_MASK 0xff
+#define BIF_BUSNUM_LIST1_IND__ID4__SHIFT 0x0
+#define BIF_BUSNUM_LIST1_IND__ID5_MASK 0xff00
+#define BIF_BUSNUM_LIST1_IND__ID5__SHIFT 0x8
+#define BIF_BUSNUM_LIST1_IND__ID6_MASK 0xff0000
+#define BIF_BUSNUM_LIST1_IND__ID6__SHIFT 0x10
+#define BIF_BUSNUM_LIST1_IND__ID7_MASK 0xff000000
+#define BIF_BUSNUM_LIST1_IND__ID7__SHIFT 0x18
+#define BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_SEL_MASK 0xff
+#define BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_SEL__SHIFT 0x0
+#define BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_EN_MASK 0x100
+#define BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_EN__SHIFT 0x8
+#define BIF_BUSNUM_CNTL2_IND__HDPREG_CNTL_MASK 0x10000
+#define BIF_BUSNUM_CNTL2_IND__HDPREG_CNTL__SHIFT 0x10
+#define BIF_BUSNUM_CNTL2_IND__ERROR_MULTIPLE_ID_MATCH_MASK 0x20000
+#define BIF_BUSNUM_CNTL2_IND__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11
+#define BIF_BUSY_DELAY_CNTR_IND__DELAY_CNT_MASK 0x3f
+#define BIF_BUSY_DELAY_CNTR_IND__DELAY_CNT__SHIFT 0x0
+#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_EN_MASK 0x1
+#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_EN__SHIFT 0x0
+#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET0_MASK 0x2
+#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET0__SHIFT 0x1
+#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET1_MASK 0x4
+#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET1__SHIFT 0x2
+#define BIF_PERFMON_CNTL_IND__PERF_SEL0_MASK 0x1f00
+#define BIF_PERFMON_CNTL_IND__PERF_SEL0__SHIFT 0x8
+#define BIF_PERFMON_CNTL_IND__PERF_SEL1_MASK 0x3e000
+#define BIF_PERFMON_CNTL_IND__PERF_SEL1__SHIFT 0xd
+#define BIF_PERFCOUNTER0_RESULT_IND__PERFCOUNTER_RESULT_MASK 0xffffffff
+#define BIF_PERFCOUNTER0_RESULT_IND__PERFCOUNTER_RESULT__SHIFT 0x0
+#define BIF_PERFCOUNTER1_RESULT_IND__PERFCOUNTER_RESULT_MASK 0xffffffff
+#define BIF_PERFCOUNTER1_RESULT_IND__PERFCOUNTER_RESULT__SHIFT 0x0
+#define SLAVE_HANG_PROTECTION_CNTL_IND__HANG_PROTECTION_TIMER_SEL_MASK 0xe
+#define SLAVE_HANG_PROTECTION_CNTL_IND__HANG_PROTECTION_TIMER_SEL__SHIFT 0x1
+#define GPU_HDP_FLUSH_REQ_IND__CP0_MASK 0x1
+#define GPU_HDP_FLUSH_REQ_IND__CP0__SHIFT 0x0
+#define GPU_HDP_FLUSH_REQ_IND__CP1_MASK 0x2
+#define GPU_HDP_FLUSH_REQ_IND__CP1__SHIFT 0x1
+#define GPU_HDP_FLUSH_REQ_IND__CP2_MASK 0x4
+#define GPU_HDP_FLUSH_REQ_IND__CP2__SHIFT 0x2
+#define GPU_HDP_FLUSH_REQ_IND__CP3_MASK 0x8
+#define GPU_HDP_FLUSH_REQ_IND__CP3__SHIFT 0x3
+#define GPU_HDP_FLUSH_REQ_IND__CP4_MASK 0x10
+#define GPU_HDP_FLUSH_REQ_IND__CP4__SHIFT 0x4
+#define GPU_HDP_FLUSH_REQ_IND__CP5_MASK 0x20
+#define GPU_HDP_FLUSH_REQ_IND__CP5__SHIFT 0x5
+#define GPU_HDP_FLUSH_REQ_IND__CP6_MASK 0x40
+#define GPU_HDP_FLUSH_REQ_IND__CP6__SHIFT 0x6
+#define GPU_HDP_FLUSH_REQ_IND__CP7_MASK 0x80
+#define GPU_HDP_FLUSH_REQ_IND__CP7__SHIFT 0x7
+#define GPU_HDP_FLUSH_REQ_IND__CP8_MASK 0x100
+#define GPU_HDP_FLUSH_REQ_IND__CP8__SHIFT 0x8
+#define GPU_HDP_FLUSH_REQ_IND__CP9_MASK 0x200
+#define GPU_HDP_FLUSH_REQ_IND__CP9__SHIFT 0x9
+#define GPU_HDP_FLUSH_REQ_IND__SDMA0_MASK 0x400
+#define GPU_HDP_FLUSH_REQ_IND__SDMA0__SHIFT 0xa
+#define GPU_HDP_FLUSH_REQ_IND__SDMA1_MASK 0x800
+#define GPU_HDP_FLUSH_REQ_IND__SDMA1__SHIFT 0xb
+#define GPU_HDP_FLUSH_DONE_IND__CP0_MASK 0x1
+#define GPU_HDP_FLUSH_DONE_IND__CP0__SHIFT 0x0
+#define GPU_HDP_FLUSH_DONE_IND__CP1_MASK 0x2
+#define GPU_HDP_FLUSH_DONE_IND__CP1__SHIFT 0x1
+#define GPU_HDP_FLUSH_DONE_IND__CP2_MASK 0x4
+#define GPU_HDP_FLUSH_DONE_IND__CP2__SHIFT 0x2
+#define GPU_HDP_FLUSH_DONE_IND__CP3_MASK 0x8
+#define GPU_HDP_FLUSH_DONE_IND__CP3__SHIFT 0x3
+#define GPU_HDP_FLUSH_DONE_IND__CP4_MASK 0x10
+#define GPU_HDP_FLUSH_DONE_IND__CP4__SHIFT 0x4
+#define GPU_HDP_FLUSH_DONE_IND__CP5_MASK 0x20
+#define GPU_HDP_FLUSH_DONE_IND__CP5__SHIFT 0x5
+#define GPU_HDP_FLUSH_DONE_IND__CP6_MASK 0x40
+#define GPU_HDP_FLUSH_DONE_IND__CP6__SHIFT 0x6
+#define GPU_HDP_FLUSH_DONE_IND__CP7_MASK 0x80
+#define GPU_HDP_FLUSH_DONE_IND__CP7__SHIFT 0x7
+#define GPU_HDP_FLUSH_DONE_IND__CP8_MASK 0x100
+#define GPU_HDP_FLUSH_DONE_IND__CP8__SHIFT 0x8
+#define GPU_HDP_FLUSH_DONE_IND__CP9_MASK 0x200
+#define GPU_HDP_FLUSH_DONE_IND__CP9__SHIFT 0x9
+#define GPU_HDP_FLUSH_DONE_IND__SDMA0_MASK 0x400
+#define GPU_HDP_FLUSH_DONE_IND__SDMA0__SHIFT 0xa
+#define GPU_HDP_FLUSH_DONE_IND__SDMA1_MASK 0x800
+#define GPU_HDP_FLUSH_DONE_IND__SDMA1__SHIFT 0xb
+#define SLAVE_HANG_ERROR_IND__SRBM_HANG_ERROR_MASK 0x1
+#define SLAVE_HANG_ERROR_IND__SRBM_HANG_ERROR__SHIFT 0x0
+#define SLAVE_HANG_ERROR_IND__HDP_HANG_ERROR_MASK 0x2
+#define SLAVE_HANG_ERROR_IND__HDP_HANG_ERROR__SHIFT 0x1
+#define SLAVE_HANG_ERROR_IND__VGA_HANG_ERROR_MASK 0x4
+#define SLAVE_HANG_ERROR_IND__VGA_HANG_ERROR__SHIFT 0x2
+#define SLAVE_HANG_ERROR_IND__ROM_HANG_ERROR_MASK 0x8
+#define SLAVE_HANG_ERROR_IND__ROM_HANG_ERROR__SHIFT 0x3
+#define SLAVE_HANG_ERROR_IND__AUDIO_HANG_ERROR_MASK 0x10
+#define SLAVE_HANG_ERROR_IND__AUDIO_HANG_ERROR__SHIFT 0x4
+#define SLAVE_HANG_ERROR_IND__CEC_HANG_ERROR_MASK 0x20
+#define SLAVE_HANG_ERROR_IND__CEC_HANG_ERROR__SHIFT 0x5
+#define SLAVE_HANG_ERROR_IND__XDMA_HANG_ERROR_MASK 0x80
+#define SLAVE_HANG_ERROR_IND__XDMA_HANG_ERROR__SHIFT 0x7
+#define SLAVE_HANG_ERROR_IND__DOORBELL_HANG_ERROR_MASK 0x100
+#define SLAVE_HANG_ERROR_IND__DOORBELL_HANG_ERROR__SHIFT 0x8
+#define SLAVE_HANG_ERROR_IND__GARLIC_HANG_ERROR_MASK 0x200
+#define SLAVE_HANG_ERROR_IND__GARLIC_HANG_ERROR__SHIFT 0x9
+#define CAPTURE_HOST_BUSNUM_IND__CHECK_EN_MASK 0x1
+#define CAPTURE_HOST_BUSNUM_IND__CHECK_EN__SHIFT 0x0
+#define HOST_BUSNUM_IND__HOST_ID_MASK 0xffff
+#define HOST_BUSNUM_IND__HOST_ID__SHIFT 0x0
+#define PEER_REG_RANGE0_IND__START_ADDR_MASK 0xffff
+#define PEER_REG_RANGE0_IND__START_ADDR__SHIFT 0x0
+#define PEER_REG_RANGE0_IND__END_ADDR_MASK 0xffff0000
+#define PEER_REG_RANGE0_IND__END_ADDR__SHIFT 0x10
+#define PEER_REG_RANGE1_IND__START_ADDR_MASK 0xffff
+#define PEER_REG_RANGE1_IND__START_ADDR__SHIFT 0x0
+#define PEER_REG_RANGE1_IND__END_ADDR_MASK 0xffff0000
+#define PEER_REG_RANGE1_IND__END_ADDR__SHIFT 0x10
+#define PEER0_FB_OFFSET_HI_IND__PEER0_FB_OFFSET_HI_MASK 0xfffff
+#define PEER0_FB_OFFSET_HI_IND__PEER0_FB_OFFSET_HI__SHIFT 0x0
+#define PEER0_FB_OFFSET_LO_IND__PEER0_FB_OFFSET_LO_MASK 0xfffff
+#define PEER0_FB_OFFSET_LO_IND__PEER0_FB_OFFSET_LO__SHIFT 0x0
+#define PEER0_FB_OFFSET_LO_IND__PEER0_FB_EN_MASK 0x80000000
+#define PEER0_FB_OFFSET_LO_IND__PEER0_FB_EN__SHIFT 0x1f
+#define PEER1_FB_OFFSET_HI_IND__PEER1_FB_OFFSET_HI_MASK 0xfffff
+#define PEER1_FB_OFFSET_HI_IND__PEER1_FB_OFFSET_HI__SHIFT 0x0
+#define PEER1_FB_OFFSET_LO_IND__PEER1_FB_OFFSET_LO_MASK 0xfffff
+#define PEER1_FB_OFFSET_LO_IND__PEER1_FB_OFFSET_LO__SHIFT 0x0
+#define PEER1_FB_OFFSET_LO_IND__PEER1_FB_EN_MASK 0x80000000
+#define PEER1_FB_OFFSET_LO_IND__PEER1_FB_EN__SHIFT 0x1f
+#define PEER2_FB_OFFSET_HI_IND__PEER2_FB_OFFSET_HI_MASK 0xfffff
+#define PEER2_FB_OFFSET_HI_IND__PEER2_FB_OFFSET_HI__SHIFT 0x0
+#define PEER2_FB_OFFSET_LO_IND__PEER2_FB_OFFSET_LO_MASK 0xfffff
+#define PEER2_FB_OFFSET_LO_IND__PEER2_FB_OFFSET_LO__SHIFT 0x0
+#define PEER2_FB_OFFSET_LO_IND__PEER2_FB_EN_MASK 0x80000000
+#define PEER2_FB_OFFSET_LO_IND__PEER2_FB_EN__SHIFT 0x1f
+#define PEER3_FB_OFFSET_HI_IND__PEER3_FB_OFFSET_HI_MASK 0xfffff
+#define PEER3_FB_OFFSET_HI_IND__PEER3_FB_OFFSET_HI__SHIFT 0x0
+#define PEER3_FB_OFFSET_LO_IND__PEER3_FB_OFFSET_LO_MASK 0xfffff
+#define PEER3_FB_OFFSET_LO_IND__PEER3_FB_OFFSET_LO__SHIFT 0x0
+#define PEER3_FB_OFFSET_LO_IND__PEER3_FB_EN_MASK 0x80000000
+#define PEER3_FB_OFFSET_LO_IND__PEER3_FB_EN__SHIFT 0x1f
+#define DBG_BYPASS_SRBM_ACCESS_IND__DBG_BYPASS_SRBM_ACCESS_EN_MASK 0x1
+#define DBG_BYPASS_SRBM_ACCESS_IND__DBG_BYPASS_SRBM_ACCESS_EN__SHIFT 0x0
+#define DBG_BYPASS_SRBM_ACCESS_IND__DBG_APER_AD_MASK 0x1e
+#define DBG_BYPASS_SRBM_ACCESS_IND__DBG_APER_AD__SHIFT 0x1
+#define SMBUS_BACO_DUMMY_IND__SMBUS_BACO_DUMMY_DATA_MASK 0xffffffff
+#define SMBUS_BACO_DUMMY_IND__SMBUS_BACO_DUMMY_DATA__SHIFT 0x0
+#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID0_MASK 0xff
+#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID0__SHIFT 0x0
+#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID1_MASK 0xff00
+#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID1__SHIFT 0x8
+#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID2_MASK 0xff0000
+#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID2__SHIFT 0x10
+#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID3_MASK 0xff000000
+#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID3__SHIFT 0x18
+#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID4_MASK 0xff
+#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID4__SHIFT 0x0
+#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID5_MASK 0xff00
+#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID5__SHIFT 0x8
+#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID6_MASK 0xff0000
+#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID6__SHIFT 0x10
+#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID7_MASK 0xff000000
+#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID7__SHIFT 0x18
+#define BACO_CNTL_IND__BACO_EN_MASK 0x1
+#define BACO_CNTL_IND__BACO_EN__SHIFT 0x0
+#define BACO_CNTL_IND__BACO_BCLK_OFF_MASK 0x2
+#define BACO_CNTL_IND__BACO_BCLK_OFF__SHIFT 0x1
+#define BACO_CNTL_IND__BACO_ISO_DIS_MASK 0x4
+#define BACO_CNTL_IND__BACO_ISO_DIS__SHIFT 0x2
+#define BACO_CNTL_IND__BACO_POWER_OFF_MASK 0x8
+#define BACO_CNTL_IND__BACO_POWER_OFF__SHIFT 0x3
+#define BACO_CNTL_IND__BACO_RESET_EN_MASK 0x10
+#define BACO_CNTL_IND__BACO_RESET_EN__SHIFT 0x4
+#define BACO_CNTL_IND__BACO_HANG_PROTECTION_EN_MASK 0x20
+#define BACO_CNTL_IND__BACO_HANG_PROTECTION_EN__SHIFT 0x5
+#define BACO_CNTL_IND__BACO_MODE_MASK 0x40
+#define BACO_CNTL_IND__BACO_MODE__SHIFT 0x6
+#define BACO_CNTL_IND__BACO_ANA_ISO_DIS_MASK 0x80
+#define BACO_CNTL_IND__BACO_ANA_ISO_DIS__SHIFT 0x7
+#define BACO_CNTL_IND__RCU_BIF_CONFIG_DONE_MASK 0x100
+#define BACO_CNTL_IND__RCU_BIF_CONFIG_DONE__SHIFT 0x8
+#define BACO_CNTL_IND__PWRGOOD_BF_MASK 0x200
+#define BACO_CNTL_IND__PWRGOOD_BF__SHIFT 0x9
+#define BACO_CNTL_IND__PWRGOOD_GPIO_MASK 0x400
+#define BACO_CNTL_IND__PWRGOOD_GPIO__SHIFT 0xa
+#define BACO_CNTL_IND__PWRGOOD_MEM_MASK 0x800
+#define BACO_CNTL_IND__PWRGOOD_MEM__SHIFT 0xb
+#define BACO_CNTL_IND__PWRGOOD_DVO_MASK 0x1000
+#define BACO_CNTL_IND__PWRGOOD_DVO__SHIFT 0xc
+#define BACO_CNTL_IND__PWRGOOD_IDSC_MASK 0x2000
+#define BACO_CNTL_IND__PWRGOOD_IDSC__SHIFT 0xd
+#define BACO_CNTL_IND__BACO_POWER_OFF_DRAM_MASK 0x10000
+#define BACO_CNTL_IND__BACO_POWER_OFF_DRAM__SHIFT 0x10
+#define BACO_CNTL_IND__BACO_BF_MEM_PHY_ISO_CNTRL_MASK 0x20000
+#define BACO_CNTL_IND__BACO_BF_MEM_PHY_ISO_CNTRL__SHIFT 0x11
+#define BF_ANA_ISO_CNTL_IND__BF_ANA_ISO_DIS_MASK_MASK 0x1
+#define BF_ANA_ISO_CNTL_IND__BF_ANA_ISO_DIS_MASK__SHIFT 0x0
+#define BF_ANA_ISO_CNTL_IND__BF_VDDC_ISO_DIS_MASK_MASK 0x2
+#define BF_ANA_ISO_CNTL_IND__BF_VDDC_ISO_DIS_MASK__SHIFT 0x1
+#define MEM_TYPE_CNTL_IND__BF_MEM_PHY_G5_G3_MASK 0x1
+#define MEM_TYPE_CNTL_IND__BF_MEM_PHY_G5_G3__SHIFT 0x0
+#define BIF_BACO_DEBUG_IND__BIF_BACO_SCANDUMP_FLG_MASK 0x1
+#define BIF_BACO_DEBUG_IND__BIF_BACO_SCANDUMP_FLG__SHIFT 0x0
+#define BIF_BACO_DEBUG_LATCH_IND__BIF_BACO_LATCH_FLG_MASK 0x1
+#define BIF_BACO_DEBUG_LATCH_IND__BIF_BACO_LATCH_FLG__SHIFT 0x0
+#define BACO_CNTL_MISC_IND__BIF_ROM_REQ_DIS_MASK 0x1
+#define BACO_CNTL_MISC_IND__BIF_ROM_REQ_DIS__SHIFT 0x0
+#define BACO_CNTL_MISC_IND__BIF_AZ_REQ_DIS_MASK 0x2
+#define BACO_CNTL_MISC_IND__BIF_AZ_REQ_DIS__SHIFT 0x1
+#define BACO_CNTL_MISC_IND__BACO_LINK_RST_WIDTH_SEL_MASK 0xc
+#define BACO_CNTL_MISC_IND__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2
+#define SMU_BIF_VDDGFX_PWR_STATUS_IND__VDDGFX_GFX_PWR_OFF_MASK 0x1
+#define SMU_BIF_VDDGFX_PWR_STATUS_IND__VDDGFX_GFX_PWR_OFF__SHIFT 0x0
+#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX0_UPPER_IND__VDDGFX_GFX0_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX0_UPPER_IND__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX1_UPPER_IND__VDDGFX_GFX1_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX1_UPPER_IND__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX2_UPPER_IND__VDDGFX_GFX2_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX2_UPPER_IND__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX3_UPPER_IND__VDDGFX_GFX3_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX3_UPPER_IND__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX4_UPPER_IND__VDDGFX_GFX4_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX4_UPPER_IND__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_GFX5_UPPER_IND__VDDGFX_GFX5_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_GFX5_UPPER_IND__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_RSV1_UPPER_IND__VDDGFX_RSV1_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV1_UPPER_IND__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_RSV2_UPPER_IND__VDDGFX_RSV2_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV2_UPPER_IND__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_RSV3_UPPER_IND__VDDGFX_RSV3_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV3_UPPER_IND__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_LOWER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2
+#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000
+#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e
+#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000
+#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f
+#define BIF_VDDGFX_RSV4_UPPER_IND__VDDGFX_RSV4_REG_UPPER_MASK 0x3fffc
+#define BIF_VDDGFX_RSV4_UPPER_IND__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2
+#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_CMP_EN_MASK 0x1
+#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0
+#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_STALL_EN_MASK 0x2
+#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1
+#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_CMP_EN_MASK 0x4
+#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2
+#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_STALL_EN_MASK 0x8
+#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3
+#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_CMP_EN_MASK 0x10
+#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4
+#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_STALL_EN_MASK 0x20
+#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5
+#define BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_LOWER_MASK 0xffc
+#define BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2
+#define BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_EN_MASK 0x80000000
+#define BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_EN__SHIFT 0x1f
+#define BIF_DOORBELL_GBLAPER1_UPPER_IND__DOORBELL_GBLAPER1_UPPER_MASK 0xffc
+#define BIF_DOORBELL_GBLAPER1_UPPER_IND__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2
+#define BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_LOWER_MASK 0xffc
+#define BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2
+#define BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_EN_MASK 0x80000000
+#define BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_EN__SHIFT 0x1f
+#define BIF_DOORBELL_GBLAPER2_UPPER_IND__DOORBELL_GBLAPER2_UPPER_MASK 0xffc
+#define BIF_DOORBELL_GBLAPER2_UPPER_IND__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2
+#define BIF_SMU_INDEX_IND__BIF_SMU_INDEX_MASK 0x7fffc
+#define BIF_SMU_INDEX_IND__BIF_SMU_INDEX__SHIFT 0x2
+#define BIF_SMU_DATA_IND__BIF_SMU_DATA_MASK 0x7fffc
+#define BIF_SMU_DATA_IND__BIF_SMU_DATA__SHIFT 0x2
+#define IMPCTL_RESET_IND__IMP_SW_RESET_MASK 0x1
+#define IMPCTL_RESET_IND__IMP_SW_RESET__SHIFT 0x0
+#define GARLIC_FLUSH_CNTL_IND__CP_RB0_WPTR_MASK 0x1
+#define GARLIC_FLUSH_CNTL_IND__CP_RB0_WPTR__SHIFT 0x0
+#define GARLIC_FLUSH_CNTL_IND__CP_RB1_WPTR_MASK 0x2
+#define GARLIC_FLUSH_CNTL_IND__CP_RB1_WPTR__SHIFT 0x1
+#define GARLIC_FLUSH_CNTL_IND__CP_RB2_WPTR_MASK 0x4
+#define GARLIC_FLUSH_CNTL_IND__CP_RB2_WPTR__SHIFT 0x2
+#define GARLIC_FLUSH_CNTL_IND__UVD_RBC_RB_WPTR_MASK 0x8
+#define GARLIC_FLUSH_CNTL_IND__UVD_RBC_RB_WPTR__SHIFT 0x3
+#define GARLIC_FLUSH_CNTL_IND__SDMA0_GFX_RB_WPTR_MASK 0x10
+#define GARLIC_FLUSH_CNTL_IND__SDMA0_GFX_RB_WPTR__SHIFT 0x4
+#define GARLIC_FLUSH_CNTL_IND__SDMA1_GFX_RB_WPTR_MASK 0x20
+#define GARLIC_FLUSH_CNTL_IND__SDMA1_GFX_RB_WPTR__SHIFT 0x5
+#define GARLIC_FLUSH_CNTL_IND__CP_DMA_ME_COMMAND_MASK 0x40
+#define GARLIC_FLUSH_CNTL_IND__CP_DMA_ME_COMMAND__SHIFT 0x6
+#define GARLIC_FLUSH_CNTL_IND__CP_DMA_PFP_COMMAND_MASK 0x80
+#define GARLIC_FLUSH_CNTL_IND__CP_DMA_PFP_COMMAND__SHIFT 0x7
+#define GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBI_WPTR_MASK 0x100
+#define GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBI_WPTR__SHIFT 0x8
+#define GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBO_WPTR_MASK 0x200
+#define GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBO_WPTR__SHIFT 0x9
+#define GARLIC_FLUSH_CNTL_IND__VCE_OUT_RB_WPTR_MASK 0x400
+#define GARLIC_FLUSH_CNTL_IND__VCE_OUT_RB_WPTR__SHIFT 0xa
+#define GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR2_MASK 0x800
+#define GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR2__SHIFT 0xb
+#define GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR_MASK 0x1000
+#define GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR__SHIFT 0xc
+#define GARLIC_FLUSH_CNTL_IND__HOST_DOORBELL_MASK 0x2000
+#define GARLIC_FLUSH_CNTL_IND__HOST_DOORBELL__SHIFT 0xd
+#define GARLIC_FLUSH_CNTL_IND__SELFRING_DOORBELL_MASK 0x4000
+#define GARLIC_FLUSH_CNTL_IND__SELFRING_DOORBELL__SHIFT 0xe
+#define GARLIC_FLUSH_CNTL_IND__CP_DMA_PIO_COMMAND_MASK 0x8000
+#define GARLIC_FLUSH_CNTL_IND__CP_DMA_PIO_COMMAND__SHIFT 0xf
+#define GARLIC_FLUSH_CNTL_IND__DISPLAY_MASK 0x10000
+#define GARLIC_FLUSH_CNTL_IND__DISPLAY__SHIFT 0x10
+#define GARLIC_FLUSH_CNTL_IND__SDMA2_GFX_RB_WPTR_MASK 0x20000
+#define GARLIC_FLUSH_CNTL_IND__SDMA2_GFX_RB_WPTR__SHIFT 0x11
+#define GARLIC_FLUSH_CNTL_IND__SDMA3_GFX_RB_WPTR_MASK 0x40000
+#define GARLIC_FLUSH_CNTL_IND__SDMA3_GFX_RB_WPTR__SHIFT 0x12
+#define GARLIC_FLUSH_CNTL_IND__IGNORE_MC_DISABLE_MASK 0x40000000
+#define GARLIC_FLUSH_CNTL_IND__IGNORE_MC_DISABLE__SHIFT 0x1e
+#define GARLIC_FLUSH_CNTL_IND__DISABLE_ALL_MASK 0x80000000
+#define GARLIC_FLUSH_CNTL_IND__DISABLE_ALL__SHIFT 0x1f
+#define GARLIC_FLUSH_REQ_IND__FLUSH_REQ_MASK 0x1
+#define GARLIC_FLUSH_REQ_IND__FLUSH_REQ__SHIFT 0x0
+#define GPU_GARLIC_FLUSH_REQ_IND__CP0_MASK 0x1
+#define GPU_GARLIC_FLUSH_REQ_IND__CP0__SHIFT 0x0
+#define GPU_GARLIC_FLUSH_REQ_IND__CP1_MASK 0x2
+#define GPU_GARLIC_FLUSH_REQ_IND__CP1__SHIFT 0x1
+#define GPU_GARLIC_FLUSH_REQ_IND__CP2_MASK 0x4
+#define GPU_GARLIC_FLUSH_REQ_IND__CP2__SHIFT 0x2
+#define GPU_GARLIC_FLUSH_REQ_IND__CP3_MASK 0x8
+#define GPU_GARLIC_FLUSH_REQ_IND__CP3__SHIFT 0x3
+#define GPU_GARLIC_FLUSH_REQ_IND__CP4_MASK 0x10
+#define GPU_GARLIC_FLUSH_REQ_IND__CP4__SHIFT 0x4
+#define GPU_GARLIC_FLUSH_REQ_IND__CP5_MASK 0x20
+#define GPU_GARLIC_FLUSH_REQ_IND__CP5__SHIFT 0x5
+#define GPU_GARLIC_FLUSH_REQ_IND__CP6_MASK 0x40
+#define GPU_GARLIC_FLUSH_REQ_IND__CP6__SHIFT 0x6
+#define GPU_GARLIC_FLUSH_REQ_IND__CP7_MASK 0x80
+#define GPU_GARLIC_FLUSH_REQ_IND__CP7__SHIFT 0x7
+#define GPU_GARLIC_FLUSH_REQ_IND__CP8_MASK 0x100
+#define GPU_GARLIC_FLUSH_REQ_IND__CP8__SHIFT 0x8
+#define GPU_GARLIC_FLUSH_REQ_IND__CP9_MASK 0x200
+#define GPU_GARLIC_FLUSH_REQ_IND__CP9__SHIFT 0x9
+#define GPU_GARLIC_FLUSH_REQ_IND__SDMA0_MASK 0x400
+#define GPU_GARLIC_FLUSH_REQ_IND__SDMA0__SHIFT 0xa
+#define GPU_GARLIC_FLUSH_REQ_IND__SDMA1_MASK 0x800
+#define GPU_GARLIC_FLUSH_REQ_IND__SDMA1__SHIFT 0xb
+#define GPU_GARLIC_FLUSH_REQ_IND__SDMA2_MASK 0x1000
+#define GPU_GARLIC_FLUSH_REQ_IND__SDMA2__SHIFT 0xc
+#define GPU_GARLIC_FLUSH_REQ_IND__SDMA3_MASK 0x2000
+#define GPU_GARLIC_FLUSH_REQ_IND__SDMA3__SHIFT 0xd
+#define GPU_GARLIC_FLUSH_DONE_IND__CP0_MASK 0x1
+#define GPU_GARLIC_FLUSH_DONE_IND__CP0__SHIFT 0x0
+#define GPU_GARLIC_FLUSH_DONE_IND__CP1_MASK 0x2
+#define GPU_GARLIC_FLUSH_DONE_IND__CP1__SHIFT 0x1
+#define GPU_GARLIC_FLUSH_DONE_IND__CP2_MASK 0x4
+#define GPU_GARLIC_FLUSH_DONE_IND__CP2__SHIFT 0x2
+#define GPU_GARLIC_FLUSH_DONE_IND__CP3_MASK 0x8
+#define GPU_GARLIC_FLUSH_DONE_IND__CP3__SHIFT 0x3
+#define GPU_GARLIC_FLUSH_DONE_IND__CP4_MASK 0x10
+#define GPU_GARLIC_FLUSH_DONE_IND__CP4__SHIFT 0x4
+#define GPU_GARLIC_FLUSH_DONE_IND__CP5_MASK 0x20
+#define GPU_GARLIC_FLUSH_DONE_IND__CP5__SHIFT 0x5
+#define GPU_GARLIC_FLUSH_DONE_IND__CP6_MASK 0x40
+#define GPU_GARLIC_FLUSH_DONE_IND__CP6__SHIFT 0x6
+#define GPU_GARLIC_FLUSH_DONE_IND__CP7_MASK 0x80
+#define GPU_GARLIC_FLUSH_DONE_IND__CP7__SHIFT 0x7
+#define GPU_GARLIC_FLUSH_DONE_IND__CP8_MASK 0x100
+#define GPU_GARLIC_FLUSH_DONE_IND__CP8__SHIFT 0x8
+#define GPU_GARLIC_FLUSH_DONE_IND__CP9_MASK 0x200
+#define GPU_GARLIC_FLUSH_DONE_IND__CP9__SHIFT 0x9
+#define GPU_GARLIC_FLUSH_DONE_IND__SDMA0_MASK 0x400
+#define GPU_GARLIC_FLUSH_DONE_IND__SDMA0__SHIFT 0xa
+#define GPU_GARLIC_FLUSH_DONE_IND__SDMA1_MASK 0x800
+#define GPU_GARLIC_FLUSH_DONE_IND__SDMA1__SHIFT 0xb
+#define GPU_GARLIC_FLUSH_DONE_IND__SDMA2_MASK 0x1000
+#define GPU_GARLIC_FLUSH_DONE_IND__SDMA2__SHIFT 0xc
+#define GPU_GARLIC_FLUSH_DONE_IND__SDMA3_MASK 0x2000
+#define GPU_GARLIC_FLUSH_DONE_IND__SDMA3__SHIFT 0xd
+#define GARLIC_COHE_CP_RB0_WPTR_IND__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_CP_RB0_WPTR_IND__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_CP_RB1_WPTR_IND__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_CP_RB1_WPTR_IND__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_CP_RB2_WPTR_IND__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_CP_RB2_WPTR_IND__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_UVD_RBC_RB_WPTR_IND__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_UVD_RBC_RB_WPTR_IND__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_SDMA0_GFX_RB_WPTR_IND__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_SDMA0_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_SDMA1_GFX_RB_WPTR_IND__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_SDMA1_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_CP_DMA_ME_COMMAND_IND__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_CP_DMA_ME_COMMAND_IND__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_CP_DMA_PFP_COMMAND_IND__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_CP_DMA_PFP_COMMAND_IND__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_SAM_SAB_RBI_WPTR_IND__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_SAM_SAB_RBI_WPTR_IND__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_SAM_SAB_RBO_WPTR_IND__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_SAM_SAB_RBO_WPTR_IND__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_VCE_OUT_RB_WPTR_IND__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_VCE_OUT_RB_WPTR_IND__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_VCE_RB_WPTR2_IND__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_VCE_RB_WPTR2_IND__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_VCE_RB_WPTR_IND__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_VCE_RB_WPTR_IND__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_SDMA2_GFX_RB_WPTR_IND__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_SDMA2_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_SDMA3_GFX_RB_WPTR_IND__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_SDMA3_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_CP_DMA_PIO_COMMAND_IND__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_CP_DMA_PIO_COMMAND_IND__ADDRESS__SHIFT 0x2
+#define GARLIC_COHE_GARLIC_FLUSH_REQ_IND__ADDRESS_MASK 0x7fffc
+#define GARLIC_COHE_GARLIC_FLUSH_REQ_IND__ADDRESS__SHIFT 0x2
+#define REMAP_HDP_MEM_FLUSH_CNTL_IND__ADDRESS_MASK 0x7fffc
+#define REMAP_HDP_MEM_FLUSH_CNTL_IND__ADDRESS__SHIFT 0x2
+#define REMAP_HDP_REG_FLUSH_CNTL_IND__ADDRESS_MASK 0x7fffc
+#define REMAP_HDP_REG_FLUSH_CNTL_IND__ADDRESS__SHIFT 0x2
+#define BIOS_SCRATCH_0_IND__BIOS_SCRATCH_0_MASK 0xffffffff
+#define BIOS_SCRATCH_0_IND__BIOS_SCRATCH_0__SHIFT 0x0
+#define BIOS_SCRATCH_1_IND__BIOS_SCRATCH_1_MASK 0xffffffff
+#define BIOS_SCRATCH_1_IND__BIOS_SCRATCH_1__SHIFT 0x0
+#define BIOS_SCRATCH_2_IND__BIOS_SCRATCH_2_MASK 0xffffffff
+#define BIOS_SCRATCH_2_IND__BIOS_SCRATCH_2__SHIFT 0x0
+#define BIOS_SCRATCH_3_IND__BIOS_SCRATCH_3_MASK 0xffffffff
+#define BIOS_SCRATCH_3_IND__BIOS_SCRATCH_3__SHIFT 0x0
+#define BIOS_SCRATCH_4_IND__BIOS_SCRATCH_4_MASK 0xffffffff
+#define BIOS_SCRATCH_4_IND__BIOS_SCRATCH_4__SHIFT 0x0
+#define BIOS_SCRATCH_5_IND__BIOS_SCRATCH_5_MASK 0xffffffff
+#define BIOS_SCRATCH_5_IND__BIOS_SCRATCH_5__SHIFT 0x0
+#define BIOS_SCRATCH_6_IND__BIOS_SCRATCH_6_MASK 0xffffffff
+#define BIOS_SCRATCH_6_IND__BIOS_SCRATCH_6__SHIFT 0x0
+#define BIOS_SCRATCH_7_IND__BIOS_SCRATCH_7_MASK 0xffffffff
+#define BIOS_SCRATCH_7_IND__BIOS_SCRATCH_7__SHIFT 0x0
+#define BIOS_SCRATCH_8_IND__BIOS_SCRATCH_8_MASK 0xffffffff
+#define BIOS_SCRATCH_8_IND__BIOS_SCRATCH_8__SHIFT 0x0
+#define BIOS_SCRATCH_9_IND__BIOS_SCRATCH_9_MASK 0xffffffff
+#define BIOS_SCRATCH_9_IND__BIOS_SCRATCH_9__SHIFT 0x0
+#define BIOS_SCRATCH_10_IND__BIOS_SCRATCH_10_MASK 0xffffffff
+#define BIOS_SCRATCH_10_IND__BIOS_SCRATCH_10__SHIFT 0x0
+#define BIOS_SCRATCH_11_IND__BIOS_SCRATCH_11_MASK 0xffffffff
+#define BIOS_SCRATCH_11_IND__BIOS_SCRATCH_11__SHIFT 0x0
+#define BIOS_SCRATCH_12_IND__BIOS_SCRATCH_12_MASK 0xffffffff
+#define BIOS_SCRATCH_12_IND__BIOS_SCRATCH_12__SHIFT 0x0
+#define BIOS_SCRATCH_13_IND__BIOS_SCRATCH_13_MASK 0xffffffff
+#define BIOS_SCRATCH_13_IND__BIOS_SCRATCH_13__SHIFT 0x0
+#define BIOS_SCRATCH_14_IND__BIOS_SCRATCH_14_MASK 0xffffffff
+#define BIOS_SCRATCH_14_IND__BIOS_SCRATCH_14__SHIFT 0x0
+#define BIOS_SCRATCH_15_IND__BIOS_SCRATCH_15_MASK 0xffffffff
+#define BIOS_SCRATCH_15_IND__BIOS_SCRATCH_15__SHIFT 0x0
+#define BIF_RB_CNTL_IND__RB_ENABLE_MASK 0x1
+#define BIF_RB_CNTL_IND__RB_ENABLE__SHIFT 0x0
+#define BIF_RB_CNTL_IND__RB_SIZE_MASK 0x3e
+#define BIF_RB_CNTL_IND__RB_SIZE__SHIFT 0x1
+#define BIF_RB_CNTL_IND__WPTR_WRITEBACK_ENABLE_MASK 0x100
+#define BIF_RB_CNTL_IND__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
+#define BIF_RB_CNTL_IND__WPTR_WRITEBACK_TIMER_MASK 0x3e00
+#define BIF_RB_CNTL_IND__WPTR_WRITEBACK_TIMER__SHIFT 0x9
+#define BIF_RB_CNTL_IND__BIF_RB_TRAN_MASK 0x20000
+#define BIF_RB_CNTL_IND__BIF_RB_TRAN__SHIFT 0x11
+#define BIF_RB_CNTL_IND__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
+#define BIF_RB_CNTL_IND__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define BIF_RB_BASE_IND__ADDR_MASK 0xffffffff
+#define BIF_RB_BASE_IND__ADDR__SHIFT 0x0
+#define BIF_RB_RPTR_IND__OFFSET_MASK 0x3fffc
+#define BIF_RB_RPTR_IND__OFFSET__SHIFT 0x2
+#define BIF_RB_WPTR_IND__BIF_RB_OVERFLOW_MASK 0x1
+#define BIF_RB_WPTR_IND__BIF_RB_OVERFLOW__SHIFT 0x0
+#define BIF_RB_WPTR_IND__OFFSET_MASK 0x3fffc
+#define BIF_RB_WPTR_IND__OFFSET__SHIFT 0x2
+#define BIF_RB_WPTR_ADDR_HI_IND__ADDR_MASK 0xff
+#define BIF_RB_WPTR_ADDR_HI_IND__ADDR__SHIFT 0x0
+#define BIF_RB_WPTR_ADDR_LO_IND__ADDR_MASK 0xfffffffc
+#define BIF_RB_WPTR_ADDR_LO_IND__ADDR__SHIFT 0x2
+#define NB_GBIF_INDEX__NB_GBIF_IND_ADDR_MASK 0xffffffff
+#define NB_GBIF_INDEX__NB_GBIF_IND_ADDR__SHIFT 0x0
+#define NB_GBIF_DATA__NB_GBIF_DATA_MASK 0xffffffff
+#define NB_GBIF_DATA__NB_GBIF_DATA__SHIFT 0x0
+#define PCIE_INDEX__PCIE_INDEX_MASK 0xffffffff
+#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
+#define PCIE_DATA__PCIE_DATA_MASK 0xffffffff
+#define PCIE_DATA__PCIE_DATA__SHIFT 0x0
+#define PCIE_INDEX_2__PCIE_INDEX_MASK 0xffffffff
+#define PCIE_INDEX_2__PCIE_INDEX__SHIFT 0x0
+#define PCIE_DATA_2__PCIE_DATA_MASK 0xffffffff
+#define PCIE_DATA_2__PCIE_DATA__SHIFT 0x0
+#define PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff
+#define PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff
+#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff
+#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0
+#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff
+#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0
+#define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1
+#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe
+#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1
+#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80
+#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100
+#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200
+#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9
+#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00
+#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa
+#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000
+#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf
+#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000
+#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10
+#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000
+#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11
+#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000
+#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12
+#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000
+#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13
+#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING_MASK 0x100000
+#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING__SHIFT 0x14
+#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000
+#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15
+#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000
+#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16
+#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000
+#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17
+#define PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000
+#define PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18
+#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000
+#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000
+#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f
+#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf
+#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0
+#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000
+#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18
+#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000
+#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff
+#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0
+#define PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100
+#define PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8
+#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000
+#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10
+#define PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x1
+#define PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
+#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x2
+#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
+#define PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x4
+#define PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
+#define PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x8
+#define PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
+#define PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x10
+#define PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
+#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x40
+#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
+#define PCIE_INT_CNTL__LINK_BW_INT_EN_MASK 0x80
+#define PCIE_INT_CNTL__LINK_BW_INT_EN__SHIFT 0x7
+#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN_MASK 0x100
+#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN__SHIFT 0x8
+#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x1
+#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
+#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x2
+#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
+#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x4
+#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
+#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x8
+#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
+#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x10
+#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
+#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x40
+#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
+#define PCIE_INT_STATUS__LINK_BW_INT_STATUS_MASK 0x80
+#define PCIE_INT_STATUS__LINK_BW_INT_STATUS__SHIFT 0x7
+#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS_MASK 0x100
+#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS__SHIFT 0x8
+#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1
+#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0
+#define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e
+#define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1
+#define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0
+#define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6
+#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800
+#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb
+#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000
+#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11
+#define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000
+#define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12
+#define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000
+#define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13
+#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000
+#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15
+#define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000
+#define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16
+#define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000
+#define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17
+#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000
+#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P_MASK 0x3
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P__SHIFT 0x0
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP_MASK 0xc
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP__SHIFT 0x2
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL_MASK 0x30
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL__SHIFT 0x4
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P_MASK 0xc0
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P__SHIFT 0x6
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP_MASK 0x300
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP__SHIFT 0x8
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P_MASK 0xc00
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P__SHIFT 0xa
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP_MASK 0x3000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP__SHIFT 0xc
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P_MASK 0x30000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P__SHIFT 0x10
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP_MASK 0xc0000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP__SHIFT 0x12
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL_MASK 0x300000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL__SHIFT 0x14
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P_MASK 0xc00000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P__SHIFT 0x16
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP_MASK 0x3000000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP__SHIFT 0x18
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P_MASK 0xc000000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P__SHIFT 0x1a
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP_MASK 0x30000000
+#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP__SHIFT 0x1c
+#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4
+#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2
+#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8
+#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3
+#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10
+#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4
+#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0
+#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6
+#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100
+#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8
+#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200
+#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc
+#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST_MASK 0x2000
+#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST__SHIFT 0xd
+#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40
+#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6
+#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80
+#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000
+#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc
+#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f
+#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0
+#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00
+#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8
+#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000
+#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10
+#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000
+#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18
+#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f
+#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0
+#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00
+#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8
+#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000
+#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10
+#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000
+#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18
+#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f
+#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0
+#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00
+#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8
+#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000
+#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10
+#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000
+#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18
+#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f
+#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0
+#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00
+#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8
+#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000
+#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10
+#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000
+#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18
+#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f
+#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0
+#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00
+#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8
+#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000
+#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10
+#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000
+#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18
+#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f
+#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0
+#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00
+#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8
+#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000
+#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10
+#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000
+#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18
+#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1
+#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0
+#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2
+#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1
+#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c
+#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2
+#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0
+#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5
+#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff
+#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0
+#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000
+#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10
+#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1
+#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2
+#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8
+#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3
+#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10
+#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4
+#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20
+#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5
+#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40
+#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6
+#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff
+#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0
+#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff
+#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0
+#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff
+#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0
+#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff
+#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0
+#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff
+#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0
+#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff
+#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0
+#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff
+#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0
+#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff
+#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0
+#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff
+#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0
+#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff
+#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1
+#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0
+#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2
+#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1
+#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4
+#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2
+#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8
+#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3
+#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10
+#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4
+#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20
+#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5
+#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40
+#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6
+#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80
+#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7
+#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100
+#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8
+#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000
+#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc
+#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000
+#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd
+#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000
+#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe
+#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000
+#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10
+#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff
+#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0
+#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000
+#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10
+#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff
+#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0
+#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff
+#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0
+#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000
+#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8
+#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE_MASK 0x1
+#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT 0x0
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN_MASK 0x2
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT 0x1
+#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE_MASK 0x4
+#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2
+#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE_MASK 0x8
+#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT 0x3
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH_MASK 0xf0
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT 0x4
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH_MASK 0xf00
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT 0x8
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD_MASK 0xf000
+#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT 0xc
+#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE_MASK 0x10000
+#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT 0x10
+#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE_MASK 0x20000
+#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT 0x11
+#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE_MASK 0x40000
+#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT 0x12
+#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE_MASK 0xf00000
+#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT 0x14
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x7
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x38
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x40
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x380
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x1c00
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x2000
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x4000
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x8000
+#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2
+#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff
+#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00
+#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000
+#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000
+#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff
+#define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff
+#define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff
+#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00
+#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff
+#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff
+#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff
+#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00
+#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff
+#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff
+#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff
+#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00
+#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff
+#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff
+#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff
+#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff
+#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff
+#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff
+#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000
+#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000
+#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18
+#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff
+#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00
+#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff
+#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff
+#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0
+#define PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1
+#define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
+#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2
+#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
+#define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4
+#define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2
+#define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8
+#define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3
+#define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10
+#define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4
+#define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20
+#define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5
+#define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40
+#define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6
+#define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80
+#define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7
+#define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100
+#define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8
+#define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200
+#define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9
+#define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400
+#define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa
+#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800
+#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb
+#define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000
+#define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc
+#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000
+#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd
+#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000
+#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe
+#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000
+#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf
+#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000
+#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
+#define PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000
+#define PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
+#define PCIE_STRAP_F1__STRAP_F1_EN_MASK 0x1
+#define PCIE_STRAP_F1__STRAP_F1_EN__SHIFT 0x0
+#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK 0x2
+#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
+#define PCIE_STRAP_F1__STRAP_F1_MSI_EN_MASK 0x4
+#define PCIE_STRAP_F1__STRAP_F1_MSI_EN__SHIFT 0x2
+#define PCIE_STRAP_F1__STRAP_F1_VC_EN_MASK 0x8
+#define PCIE_STRAP_F1__STRAP_F1_VC_EN__SHIFT 0x3
+#define PCIE_STRAP_F1__STRAP_F1_DSN_EN_MASK 0x10
+#define PCIE_STRAP_F1__STRAP_F1_DSN_EN__SHIFT 0x4
+#define PCIE_STRAP_F1__STRAP_F1_AER_EN_MASK 0x20
+#define PCIE_STRAP_F1__STRAP_F1_AER_EN__SHIFT 0x5
+#define PCIE_STRAP_F1__STRAP_F1_ACS_EN_MASK 0x40
+#define PCIE_STRAP_F1__STRAP_F1_ACS_EN__SHIFT 0x6
+#define PCIE_STRAP_F1__STRAP_F1_BAR_EN_MASK 0x80
+#define PCIE_STRAP_F1__STRAP_F1_BAR_EN__SHIFT 0x7
+#define PCIE_STRAP_F1__STRAP_F1_PWR_EN_MASK 0x100
+#define PCIE_STRAP_F1__STRAP_F1_PWR_EN__SHIFT 0x8
+#define PCIE_STRAP_F1__STRAP_F1_DPA_EN_MASK 0x200
+#define PCIE_STRAP_F1__STRAP_F1_DPA_EN__SHIFT 0x9
+#define PCIE_STRAP_F1__STRAP_F1_ATS_EN_MASK 0x400
+#define PCIE_STRAP_F1__STRAP_F1_ATS_EN__SHIFT 0xa
+#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN_MASK 0x800
+#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN__SHIFT 0xb
+#define PCIE_STRAP_F1__STRAP_F1_PASID_EN_MASK 0x1000
+#define PCIE_STRAP_F1__STRAP_F1_PASID_EN__SHIFT 0xc
+#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN_MASK 0x2000
+#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN__SHIFT 0xd
+#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN_MASK 0x4000
+#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN__SHIFT 0xe
+#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN_MASK 0x8000
+#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN__SHIFT 0xf
+#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL_MASK 0x10000
+#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
+#define PCIE_STRAP_F2__STRAP_F2_EN_MASK 0x1
+#define PCIE_STRAP_F2__STRAP_F2_EN__SHIFT 0x0
+#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK 0x2
+#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
+#define PCIE_STRAP_F2__STRAP_F2_MSI_EN_MASK 0x4
+#define PCIE_STRAP_F2__STRAP_F2_MSI_EN__SHIFT 0x2
+#define PCIE_STRAP_F2__STRAP_F2_VC_EN_MASK 0x8
+#define PCIE_STRAP_F2__STRAP_F2_VC_EN__SHIFT 0x3
+#define PCIE_STRAP_F2__STRAP_F2_DSN_EN_MASK 0x10
+#define PCIE_STRAP_F2__STRAP_F2_DSN_EN__SHIFT 0x4
+#define PCIE_STRAP_F2__STRAP_F2_AER_EN_MASK 0x20
+#define PCIE_STRAP_F2__STRAP_F2_AER_EN__SHIFT 0x5
+#define PCIE_STRAP_F2__STRAP_F2_ACS_EN_MASK 0x40
+#define PCIE_STRAP_F2__STRAP_F2_ACS_EN__SHIFT 0x6
+#define PCIE_STRAP_F2__STRAP_F2_BAR_EN_MASK 0x80
+#define PCIE_STRAP_F2__STRAP_F2_BAR_EN__SHIFT 0x7
+#define PCIE_STRAP_F2__STRAP_F2_PWR_EN_MASK 0x100
+#define PCIE_STRAP_F2__STRAP_F2_PWR_EN__SHIFT 0x8
+#define PCIE_STRAP_F2__STRAP_F2_DPA_EN_MASK 0x200
+#define PCIE_STRAP_F2__STRAP_F2_DPA_EN__SHIFT 0x9
+#define PCIE_STRAP_F2__STRAP_F2_ATS_EN_MASK 0x400
+#define PCIE_STRAP_F2__STRAP_F2_ATS_EN__SHIFT 0xa
+#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN_MASK 0x800
+#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN__SHIFT 0xb
+#define PCIE_STRAP_F2__STRAP_F2_PASID_EN_MASK 0x1000
+#define PCIE_STRAP_F2__STRAP_F2_PASID_EN__SHIFT 0xc
+#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN_MASK 0x2000
+#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN__SHIFT 0xd
+#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN_MASK 0x4000
+#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN__SHIFT 0xe
+#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN_MASK 0x8000
+#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN__SHIFT 0xf
+#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL_MASK 0x10000
+#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
+#define PCIE_STRAP_F3__RESERVED_MASK 0xffffffff
+#define PCIE_STRAP_F3__RESERVED__SHIFT 0x0
+#define PCIE_STRAP_F4__RESERVED_MASK 0xffffffff
+#define PCIE_STRAP_F4__RESERVED__SHIFT 0x0
+#define PCIE_STRAP_F5__RESERVED_MASK 0xffffffff
+#define PCIE_STRAP_F5__RESERVED__SHIFT 0x0
+#define PCIE_STRAP_F6__RESERVED_MASK 0xffffffff
+#define PCIE_STRAP_F6__RESERVED__SHIFT 0x0
+#define PCIE_STRAP_F7__RESERVED_MASK 0xffffffff
+#define PCIE_STRAP_F7__RESERVED__SHIFT 0x0
+#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG_MASK 0xf
+#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG__SHIFT 0x0
+#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10
+#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4
+#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH_MASK 0x1f00
+#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH__SHIFT 0x8
+#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2000
+#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0xd
+#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED_MASK 0x4000
+#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED__SHIFT 0xe
+#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_MASK 0x8000
+#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0xf
+#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000
+#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
+#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000
+#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19
+#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000
+#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a
+#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000
+#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c
+#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000
+#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000
+#define PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e
+#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000
+#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f
+#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2
+#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1
+#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4
+#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
+#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8
+#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3
+#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10
+#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
+#define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1
+#define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d
+#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f
+#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0
+#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80
+#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7
+#define PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff
+#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0
+#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000
+#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10
+#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff
+#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0
+#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000
+#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10
+#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff
+#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0
+#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff
+#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0
+#define PCIE_PRBS_MISC__PRBS_EN_MASK 0x1
+#define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0
+#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0x6
+#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1
+#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x8
+#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x3
+#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x10
+#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x4
+#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0x60
+#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x5
+#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0xf80
+#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x7
+#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000
+#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe
+#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000
+#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10
+#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff
+#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0
+#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff
+#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0
+#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff
+#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff
+#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0
+#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300
+#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000
+#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000
+#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000
+#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff
+#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x1f
+#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff
+#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
+#define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
+#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
+#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
+#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
+#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
+#define PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
+#define PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
+#define PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
+#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
+#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
+#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
+#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
+#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
+#define PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
+#define PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
+#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
+#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
+#define PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
+#define PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
+#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
+#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x1000000
+#define PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x2000000
+#define PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x4000000
+#define PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
+#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
+#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
+#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
+#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
+#define PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
+#define PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
+#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
+#define PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
+#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
+#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
+#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
+#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
+#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
+#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
+#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
+#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
+#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
+#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
+#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
+#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
+#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
+#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
+#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
+#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
+#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
+#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define PCIE_FC_P__PD_CREDITS_MASK 0xff
+#define PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define PCIE_FC_P__PH_CREDITS_MASK 0xff00
+#define PCIE_FC_P__PH_CREDITS__SHIFT 0x8
+#define PCIE_FC_NP__NPD_CREDITS_MASK 0xff
+#define PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
+#define PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
+#define PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
+#define PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
+#define PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
+#define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
+#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
+#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
+#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
+#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
+#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
+#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
+#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
+#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x1000
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0xc
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x2000
+#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0xd
+#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
+#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
+#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
+#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
+#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
+#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
+#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
+#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
+#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
+#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
+#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
+#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
+#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
+#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
+#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
+#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
+#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
+#define PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
+#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
+#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
+#define PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
+#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
+#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
+#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
+#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
+#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
+#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
+#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
+#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
+#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
+#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
+#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
+#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
+#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
+#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
+#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
+#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
+#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
+#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
+#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
+#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
+#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
+#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
+#define PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
+#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
+#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
+#define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
+#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
+#define PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
+#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
+#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
+#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
+#define PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
+#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
+#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
+#define PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
+#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
+#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
+#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
+#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
+#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
+#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
+#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
+#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
+#define PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
+#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
+#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
+#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
+#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
+#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
+#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
+#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
+#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
+#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
+#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
+#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
+#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
+#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
+#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
+#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
+#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
+#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
+#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
+#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
+#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
+#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
+#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
+#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
+#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
+#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
+#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
+#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
+#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
+#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
+#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
+#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
+#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
+#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
+#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
+#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
+#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
+#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
+#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
+#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
+#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
+#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
+#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
+#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
+#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
+#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
+#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
+#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
+#define PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
+#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
+#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
+#define PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
+#define PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
+#define PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
+#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
+#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
+#define PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
+#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
+#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
+#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
+#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
+#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
+#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
+#define PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
+#define PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
+#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
+#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
+#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
+#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
+#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
+#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
+#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
+#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
+#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
+#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
+#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
+#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
+#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
+#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
+#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
+#define PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
+#define PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
+#define PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
+#define PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
+#define PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
+#define PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
+#define PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
+#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
+#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
+#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
+#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
+#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
+#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
+#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
+#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
+#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
+#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
+#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
+#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
+#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
+#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
+#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
+#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
+#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
+#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
+#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
+#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
+#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
+#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
+#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
+#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
+#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
+#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
+#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
+#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
+#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
+#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
+#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
+#define PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
+#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
+#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
+#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
+#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
+#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
+#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
+#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
+#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
+#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
+#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
+#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
+#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
+#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
+#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
+#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
+#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
+#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
+#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
+#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
+#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
+#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
+#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
+#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
+#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
+#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
+#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
+#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
+#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
+#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
+#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
+#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
+#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
+#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
+#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
+#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
+#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
+#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
+#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
+#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
+#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
+#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
+#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
+#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
+#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
+#define PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
+#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
+#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
+#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
+#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
+#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
+#define PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
+#define PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
+#define PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
+#define PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
+#define PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
+#define PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
+#define PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
+#define PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
+#define PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
+#define PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
+#define PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
+#define PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
+#define PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
+#define PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
+#define PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
+#define PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
+#define PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
+#define PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
+#define PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
+#define PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
+#define PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
+#define PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
+#define PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
+#define PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
+#define PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
+#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
+#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
+#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
+#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
+#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
+#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
+#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
+#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
+#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
+#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
+#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
+#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
+#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
+#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
+#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
+#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
+#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
+#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
+#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER_MASK 0x1
+#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER__SHIFT 0x0
+#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER_MASK 0x2
+#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER__SHIFT 0x1
+#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn_MASK 0x1
+#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn__SHIFT 0x0
+#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer_MASK 0xffff
+#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer__SHIFT 0x0
+#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn_MASK 0x40000000
+#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn__SHIFT 0x1e
+#define BIF_RFE_SOFTRST_CNTL__SoftRstReg_MASK 0x80000000
+#define BIF_RFE_SOFTRST_CNTL__SoftRstReg__SHIFT 0x1f
+#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWGBIF_rst_MASK 0x1
+#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWGBIF_rst__SHIFT 0x0
+#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWGBIF_rst_MASK 0x2
+#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWGBIF_rst__SHIFT 0x1
+#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWGBIF_rst_MASK 0x4
+#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWGBIF_rst__SHIFT 0x2
+#define BIF_RFE_MASTER_SOFTRST_TRIGGER__FBU_rst_MASK 0x1
+#define BIF_RFE_MASTER_SOFTRST_TRIGGER__FBU_rst__SHIFT 0x0
+#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWGBIF_rst_MASK 0x2
+#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWGBIF_rst__SHIFT 0x1
+#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst_MASK 0x4
+#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst__SHIFT 0x2
+#define BIF_PWDN_COMMAND__REG_FBU_pw_cmd_MASK 0x1
+#define BIF_PWDN_COMMAND__REG_FBU_pw_cmd__SHIFT 0x0
+#define BIF_PWDN_COMMAND__REG_RWREG_RFEWGBIF_pw_cmd_MASK 0x2
+#define BIF_PWDN_COMMAND__REG_RWREG_RFEWGBIF_pw_cmd__SHIFT 0x1
+#define BIF_PWDN_COMMAND__REG_BX_pw_cmd_MASK 0x4
+#define BIF_PWDN_COMMAND__REG_BX_pw_cmd__SHIFT 0x2
+#define BIF_PWDN_STATUS__FBU_REG_pw_status_MASK 0x1
+#define BIF_PWDN_STATUS__FBU_REG_pw_status__SHIFT 0x0
+#define BIF_PWDN_STATUS__RWREG_RFEWGBIF_REG_pw_status_MASK 0x2
+#define BIF_PWDN_STATUS__RWREG_RFEWGBIF_REG_pw_status__SHIFT 0x1
+#define BIF_PWDN_STATUS__BX_REG_pw_status_MASK 0x4
+#define BIF_PWDN_STATUS__BX_REG_pw_status__SHIFT 0x2
+#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkGate_timer_MASK 0xff
+#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkGate_timer__SHIFT 0x0
+#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkSetup_timer_MASK 0xf00
+#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkSetup_timer__SHIFT 0x8
+#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_timeout_timer_MASK 0xff0000
+#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_timeout_timer__SHIFT 0x10
+#define BIF_RFE_MST_FBU_CMDSTATUS__FBU_RFE_mstTimeout_MASK 0x1000000
+#define BIF_RFE_MST_FBU_CMDSTATUS__FBU_RFE_mstTimeout__SHIFT 0x18
+#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkGate_timer_MASK 0xff
+#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkGate_timer__SHIFT 0x0
+#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkSetup_timer_MASK 0xf00
+#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkSetup_timer__SHIFT 0x8
+#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_timeout_timer_MASK 0xff0000
+#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_timeout_timer__SHIFT 0x10
+#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__RWREG_RFEWGBIF_RFE_mstTimeout_MASK 0x1000000
+#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__RWREG_RFEWGBIF_RFE_mstTimeout__SHIFT 0x18
+#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer_MASK 0xff
+#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer__SHIFT 0x0
+#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer_MASK 0xf00
+#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer__SHIFT 0x8
+#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer_MASK 0xff0000
+#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer__SHIFT 0x10
+#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout_MASK 0x1000000
+#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout__SHIFT 0x18
+#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus_MASK 0x1
+#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus__SHIFT 0x0
+#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_WR_TO_CFG_EN_MASK 0x1
+#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_WR_TO_CFG_EN__SHIFT 0x0
+#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_CFG_FUNC_SEL_MASK 0xe
+#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_CFG_FUNC_SEL__SHIFT 0x1
+#define BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_WR_TO_CFG_EN_MASK 0x10
+#define BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_WR_TO_CFG_EN__SHIFT 0x4
+#define BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_CFG_FUNC_SEL_MASK 0xe0
+#define BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_CFG_FUNC_SEL__SHIFT 0x5
+#define BIF_CLOCKS_BITS_IND__OBFF_XSL_FORCE_REFCLK_MASK 0x1
+#define BIF_CLOCKS_BITS_IND__OBFF_XSL_FORCE_REFCLK__SHIFT 0x0
+#define BIF_LNCNT_RESET_IND__RESET_LNCNT_EN_MASK 0x1
+#define BIF_LNCNT_RESET_IND__RESET_LNCNT_EN__SHIFT 0x0
+#define LNCNT_CONTROL_IND__LNCNT_ACC_MODE_MASK 0x1
+#define LNCNT_CONTROL_IND__LNCNT_ACC_MODE__SHIFT 0x0
+#define LNCNT_CONTROL_IND__LNCNT_REF_TIMEBASE_MASK 0x6
+#define LNCNT_CONTROL_IND__LNCNT_REF_TIMEBASE__SHIFT 0x1
+#define NEW_REFCLKB_TIMER_IND__REG_STOP_REFCLK_EN_MASK 0x1
+#define NEW_REFCLKB_TIMER_IND__REG_STOP_REFCLK_EN__SHIFT 0x0
+#define NEW_REFCLKB_TIMER_IND__STOP_REFCLK_TIMER_MASK 0x1ffffe
+#define NEW_REFCLKB_TIMER_IND__STOP_REFCLK_TIMER__SHIFT 0x1
+#define NEW_REFCLKB_TIMER_IND__REFCLK_ON_MASK 0x200000
+#define NEW_REFCLKB_TIMER_IND__REFCLK_ON__SHIFT 0x15
+#define NEW_REFCLKB_TIMER_1_IND__PHY_PLL_PDWN_TIMER_MASK 0x3ff
+#define NEW_REFCLKB_TIMER_1_IND__PHY_PLL_PDWN_TIMER__SHIFT 0x0
+#define NEW_REFCLKB_TIMER_1_IND__PLL0_PDNB_EN_MASK 0x400
+#define NEW_REFCLKB_TIMER_1_IND__PLL0_PDNB_EN__SHIFT 0xa
+#define BIF_CLK_PDWN_DELAY_TIMER_IND__TIMER_MASK 0x3ff
+#define BIF_CLK_PDWN_DELAY_TIMER_IND__TIMER__SHIFT 0x0
+#define BIF_RESET_EN_IND__SOFT_RST_MODE_MASK 0x2
+#define BIF_RESET_EN_IND__SOFT_RST_MODE__SHIFT 0x1
+#define BIF_RESET_EN_IND__PHY_RESET_EN_MASK 0x4
+#define BIF_RESET_EN_IND__PHY_RESET_EN__SHIFT 0x2
+#define BIF_RESET_EN_IND__COR_RESET_EN_MASK 0x8
+#define BIF_RESET_EN_IND__COR_RESET_EN__SHIFT 0x3
+#define BIF_RESET_EN_IND__REG_RESET_EN_MASK 0x10
+#define BIF_RESET_EN_IND__REG_RESET_EN__SHIFT 0x4
+#define BIF_RESET_EN_IND__STY_RESET_EN_MASK 0x20
+#define BIF_RESET_EN_IND__STY_RESET_EN__SHIFT 0x5
+#define BIF_RESET_EN_IND__CFG_RESET_EN_MASK 0x40
+#define BIF_RESET_EN_IND__CFG_RESET_EN__SHIFT 0x6
+#define BIF_RESET_EN_IND__DRV_RESET_EN_MASK 0x80
+#define BIF_RESET_EN_IND__DRV_RESET_EN__SHIFT 0x7
+#define BIF_RESET_EN_IND__RESET_CFGREG_ONLY_EN_MASK 0x100
+#define BIF_RESET_EN_IND__RESET_CFGREG_ONLY_EN__SHIFT 0x8
+#define BIF_RESET_EN_IND__HOT_RESET_EN_MASK 0x200
+#define BIF_RESET_EN_IND__HOT_RESET_EN__SHIFT 0x9
+#define BIF_RESET_EN_IND__LINK_DISABLE_RESET_EN_MASK 0x400
+#define BIF_RESET_EN_IND__LINK_DISABLE_RESET_EN__SHIFT 0xa
+#define BIF_RESET_EN_IND__LINK_DOWN_RESET_EN_MASK 0x800
+#define BIF_RESET_EN_IND__LINK_DOWN_RESET_EN__SHIFT 0xb
+#define BIF_RESET_EN_IND__CFG_RESET_PULSE_WIDTH_MASK 0x3f000
+#define BIF_RESET_EN_IND__CFG_RESET_PULSE_WIDTH__SHIFT 0xc
+#define BIF_RESET_EN_IND__DRV_RESET_DELAY_SEL_MASK 0xc0000
+#define BIF_RESET_EN_IND__DRV_RESET_DELAY_SEL__SHIFT 0x12
+#define BIF_RESET_EN_IND__PIF_RSTB_EN_MASK 0x100000
+#define BIF_RESET_EN_IND__PIF_RSTB_EN__SHIFT 0x14
+#define BIF_RESET_EN_IND__PIF_STRAP_ALLVALID_EN_MASK 0x200000
+#define BIF_RESET_EN_IND__PIF_STRAP_ALLVALID_EN__SHIFT 0x15
+#define BIF_RESET_EN_IND__BIF_COR_RESET_EN_MASK 0x400000
+#define BIF_RESET_EN_IND__BIF_COR_RESET_EN__SHIFT 0x16
+#define BIF_RESET_EN_IND__FUNC0_FLR_EN_MASK 0x800000
+#define BIF_RESET_EN_IND__FUNC0_FLR_EN__SHIFT 0x17
+#define BIF_RESET_EN_IND__FUNC1_FLR_EN_MASK 0x1000000
+#define BIF_RESET_EN_IND__FUNC1_FLR_EN__SHIFT 0x18
+#define BIF_RESET_EN_IND__FUNC2_FLR_EN_MASK 0x2000000
+#define BIF_RESET_EN_IND__FUNC2_FLR_EN__SHIFT 0x19
+#define BIF_RESET_EN_IND__FUNC0_RESET_DELAY_SEL_MASK 0xc000000
+#define BIF_RESET_EN_IND__FUNC0_RESET_DELAY_SEL__SHIFT 0x1a
+#define BIF_RESET_EN_IND__FUNC1_RESET_DELAY_SEL_MASK 0x30000000
+#define BIF_RESET_EN_IND__FUNC1_RESET_DELAY_SEL__SHIFT 0x1c
+#define BIF_RESET_EN_IND__FUNC2_RESET_DELAY_SEL_MASK 0xc0000000
+#define BIF_RESET_EN_IND__FUNC2_RESET_DELAY_SEL__SHIFT 0x1e
+#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL0_ACK_TIMER_MASK 0x7
+#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL0_ACK_TIMER__SHIFT 0x0
+#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL1_ACK_TIMER_MASK 0x38
+#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL1_ACK_TIMER__SHIFT 0x3
+#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL_SWITCH_TIMER_MASK 0x3c0
+#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL_SWITCH_TIMER__SHIFT 0x6
+#define BIF_BACO_MSIC_IND__BIF_XTALIN_SEL_MASK 0x1
+#define BIF_BACO_MSIC_IND__BIF_XTALIN_SEL__SHIFT 0x0
+#define BIF_BACO_MSIC_IND__BACO_LINK_RST_SEL_MASK 0x6
+#define BIF_BACO_MSIC_IND__BACO_LINK_RST_SEL__SHIFT 0x1
+#define BIF_BACO_MSIC_IND__ACPI_BACO_MUX_DIS_MASK 0x10
+#define BIF_BACO_MSIC_IND__ACPI_BACO_MUX_DIS__SHIFT 0x4
+#define BIF_RESET_CNTL_IND__STRAP_EN_MASK 0x1
+#define BIF_RESET_CNTL_IND__STRAP_EN__SHIFT 0x0
+#define BIF_RESET_CNTL_IND__RST_DONE_MASK 0x2
+#define BIF_RESET_CNTL_IND__RST_DONE__SHIFT 0x1
+#define BIF_RESET_CNTL_IND__LINK_TRAIN_EN_MASK 0x4
+#define BIF_RESET_CNTL_IND__LINK_TRAIN_EN__SHIFT 0x2
+#define BIF_RESET_CNTL_IND__STRAP_ALL_VALID_MASK 0x8
+#define BIF_RESET_CNTL_IND__STRAP_ALL_VALID__SHIFT 0x3
+#define BIF_RESET_CNTL_IND__RECAP_STRAP_WARMRST_MASK 0x100
+#define BIF_RESET_CNTL_IND__RECAP_STRAP_WARMRST__SHIFT 0x8
+#define BIF_RESET_CNTL_IND__HOLD_LKTRN_WARMRST_DIS_MASK 0x200
+#define BIF_RESET_CNTL_IND__HOLD_LKTRN_WARMRST_DIS__SHIFT 0x9
+#define BIF_RFE_CNTL_MISC_IND__ADAPT_pif0_bu_reg_accessMode_MASK 0x1
+#define BIF_RFE_CNTL_MISC_IND__ADAPT_pif0_bu_reg_accessMode__SHIFT 0x0
+#define BIF_RFE_CNTL_MISC_IND__ADAPT_pif1_bu_reg_accessMode_MASK 0x2
+#define BIF_RFE_CNTL_MISC_IND__ADAPT_pif1_bu_reg_accessMode__SHIFT 0x1
+#define BIF_RFE_CNTL_MISC_IND__ADAPT_pwreg_bu_reg_accessMode_MASK 0x4
+#define BIF_RFE_CNTL_MISC_IND__ADAPT_pwreg_bu_reg_accessMode__SHIFT 0x2
+#define BIF_RFE_CNTL_MISC_IND__ADAPT_pciecore0_bu_reg_accessMode_MASK 0x8
+#define BIF_RFE_CNTL_MISC_IND__ADAPT_pciecore0_bu_reg_accessMode__SHIFT 0x3
+#define BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_EN_MASK 0x1
+#define BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_EN__SHIFT 0x0
+#define BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_TIMER_MASK 0xffff0000
+#define BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_TIMER__SHIFT 0x10
+#define NB_GBIF_INDEX__NB_GBIF_IND_ADDR_MASK 0xffffffff
+#define NB_GBIF_INDEX__NB_GBIF_IND_ADDR__SHIFT 0x0
+#define NB_GBIF_DATA__NB_GBIF_DATA_MASK 0xffffffff
+#define NB_GBIF_DATA__NB_GBIF_DATA__SHIFT 0x0
+#define BIF_CLOCKS_BITS__OBFF_XSL_FORCE_REFCLK_MASK 0x1
+#define BIF_CLOCKS_BITS__OBFF_XSL_FORCE_REFCLK__SHIFT 0x0
+#define BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK 0x1
+#define BIF_LNCNT_RESET__RESET_LNCNT_EN__SHIFT 0x0
+#define LNCNT_CONTROL__LNCNT_ACC_MODE_MASK 0x1
+#define LNCNT_CONTROL__LNCNT_ACC_MODE__SHIFT 0x0
+#define LNCNT_CONTROL__LNCNT_REF_TIMEBASE_MASK 0x6
+#define LNCNT_CONTROL__LNCNT_REF_TIMEBASE__SHIFT 0x1
+#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN_MASK 0x1
+#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN__SHIFT 0x0
+#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER_MASK 0x1ffffe
+#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER__SHIFT 0x1
+#define NEW_REFCLKB_TIMER__REFCLK_ON_MASK 0x200000
+#define NEW_REFCLKB_TIMER__REFCLK_ON__SHIFT 0x15
+#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER_MASK 0x3ff
+#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER__SHIFT 0x0
+#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN_MASK 0x400
+#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN__SHIFT 0xa
+#define BIF_CLK_PDWN_DELAY_TIMER__TIMER_MASK 0x3ff
+#define BIF_CLK_PDWN_DELAY_TIMER__TIMER__SHIFT 0x0
+#define BIF_RESET_EN__SOFT_RST_MODE_MASK 0x2
+#define BIF_RESET_EN__SOFT_RST_MODE__SHIFT 0x1
+#define BIF_RESET_EN__PHY_RESET_EN_MASK 0x4
+#define BIF_RESET_EN__PHY_RESET_EN__SHIFT 0x2
+#define BIF_RESET_EN__COR_RESET_EN_MASK 0x8
+#define BIF_RESET_EN__COR_RESET_EN__SHIFT 0x3
+#define BIF_RESET_EN__REG_RESET_EN_MASK 0x10
+#define BIF_RESET_EN__REG_RESET_EN__SHIFT 0x4
+#define BIF_RESET_EN__STY_RESET_EN_MASK 0x20
+#define BIF_RESET_EN__STY_RESET_EN__SHIFT 0x5
+#define BIF_RESET_EN__CFG_RESET_EN_MASK 0x40
+#define BIF_RESET_EN__CFG_RESET_EN__SHIFT 0x6
+#define BIF_RESET_EN__DRV_RESET_EN_MASK 0x80
+#define BIF_RESET_EN__DRV_RESET_EN__SHIFT 0x7
+#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN_MASK 0x100
+#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN__SHIFT 0x8
+#define BIF_RESET_EN__HOT_RESET_EN_MASK 0x200
+#define BIF_RESET_EN__HOT_RESET_EN__SHIFT 0x9
+#define BIF_RESET_EN__LINK_DISABLE_RESET_EN_MASK 0x400
+#define BIF_RESET_EN__LINK_DISABLE_RESET_EN__SHIFT 0xa
+#define BIF_RESET_EN__LINK_DOWN_RESET_EN_MASK 0x800
+#define BIF_RESET_EN__LINK_DOWN_RESET_EN__SHIFT 0xb
+#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH_MASK 0x3f000
+#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH__SHIFT 0xc
+#define BIF_RESET_EN__DRV_RESET_DELAY_SEL_MASK 0xc0000
+#define BIF_RESET_EN__DRV_RESET_DELAY_SEL__SHIFT 0x12
+#define BIF_RESET_EN__PIF_RSTB_EN_MASK 0x100000
+#define BIF_RESET_EN__PIF_RSTB_EN__SHIFT 0x14
+#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN_MASK 0x200000
+#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN__SHIFT 0x15
+#define BIF_RESET_EN__BIF_COR_RESET_EN_MASK 0x400000
+#define BIF_RESET_EN__BIF_COR_RESET_EN__SHIFT 0x16
+#define BIF_RESET_EN__FUNC0_FLR_EN_MASK 0x800000
+#define BIF_RESET_EN__FUNC0_FLR_EN__SHIFT 0x17
+#define BIF_RESET_EN__FUNC1_FLR_EN_MASK 0x1000000
+#define BIF_RESET_EN__FUNC1_FLR_EN__SHIFT 0x18
+#define BIF_RESET_EN__FUNC2_FLR_EN_MASK 0x2000000
+#define BIF_RESET_EN__FUNC2_FLR_EN__SHIFT 0x19
+#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL_MASK 0xc000000
+#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL__SHIFT 0x1a
+#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL_MASK 0x30000000
+#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL__SHIFT 0x1c
+#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL_MASK 0xc0000000
+#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL__SHIFT 0x1e
+#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER_MASK 0x7
+#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER__SHIFT 0x0
+#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER_MASK 0x38
+#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER__SHIFT 0x3
+#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER_MASK 0x3c0
+#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER__SHIFT 0x6
+#define BIF_BACO_MSIC__BIF_XTALIN_SEL_MASK 0x1
+#define BIF_BACO_MSIC__BIF_XTALIN_SEL__SHIFT 0x0
+#define BIF_BACO_MSIC__BACO_LINK_RST_SEL_MASK 0x6
+#define BIF_BACO_MSIC__BACO_LINK_RST_SEL__SHIFT 0x1
+#define BIF_BACO_MSIC__ACPI_BACO_MUX_DIS_MASK 0x10
+#define BIF_BACO_MSIC__ACPI_BACO_MUX_DIS__SHIFT 0x4
+#define BIF_RESET_CNTL__STRAP_EN_MASK 0x1
+#define BIF_RESET_CNTL__STRAP_EN__SHIFT 0x0
+#define BIF_RESET_CNTL__RST_DONE_MASK 0x2
+#define BIF_RESET_CNTL__RST_DONE__SHIFT 0x1
+#define BIF_RESET_CNTL__LINK_TRAIN_EN_MASK 0x4
+#define BIF_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x2
+#define BIF_RESET_CNTL__STRAP_ALL_VALID_MASK 0x8
+#define BIF_RESET_CNTL__STRAP_ALL_VALID__SHIFT 0x3
+#define BIF_RESET_CNTL__RECAP_STRAP_WARMRST_MASK 0x100
+#define BIF_RESET_CNTL__RECAP_STRAP_WARMRST__SHIFT 0x8
+#define BIF_RESET_CNTL__HOLD_LKTRN_WARMRST_DIS_MASK 0x200
+#define BIF_RESET_CNTL__HOLD_LKTRN_WARMRST_DIS__SHIFT 0x9
+#define BIF_RFE_CNTL_MISC__ADAPT_pif0_bu_reg_accessMode_MASK 0x1
+#define BIF_RFE_CNTL_MISC__ADAPT_pif0_bu_reg_accessMode__SHIFT 0x0
+#define BIF_RFE_CNTL_MISC__ADAPT_pif1_bu_reg_accessMode_MASK 0x2
+#define BIF_RFE_CNTL_MISC__ADAPT_pif1_bu_reg_accessMode__SHIFT 0x1
+#define BIF_RFE_CNTL_MISC__ADAPT_pwreg_bu_reg_accessMode_MASK 0x4
+#define BIF_RFE_CNTL_MISC__ADAPT_pwreg_bu_reg_accessMode__SHIFT 0x2
+#define BIF_RFE_CNTL_MISC__ADAPT_pciecore0_bu_reg_accessMode_MASK 0x8
+#define BIF_RFE_CNTL_MISC__ADAPT_pciecore0_bu_reg_accessMode__SHIFT 0x3
+#define BIF_MEM_PG_CNTL__BIF_MEM_SD_EN_MASK 0x1
+#define BIF_MEM_PG_CNTL__BIF_MEM_SD_EN__SHIFT 0x0
+#define BIF_MEM_PG_CNTL__BIF_MEM_SD_TIMER_MASK 0xffff0000
+#define BIF_MEM_PG_CNTL__BIF_MEM_SD_TIMER__SHIFT 0x10
+#define C_PCIE_P_INDEX__PCIE_INDEX_MASK 0xffffffff
+#define C_PCIE_P_INDEX__PCIE_INDEX__SHIFT 0x0
+#define C_PCIE_P_DATA__PCIE_DATA_MASK 0xffffffff
+#define C_PCIE_P_DATA__PCIE_DATA__SHIFT 0x0
+#define D2F1_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
+#define D2F1_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
+#define D2F1_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
+#define D2F1_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
+#define D2F1_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
+#define D2F1_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define D2F1_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
+#define D2F1_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define D2F1_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define D2F1_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define D2F1_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define D2F1_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define D2F1_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define D2F1_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define D2F1_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define D2F1_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define D2F1_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define D2F1_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define D2F1_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define D2F1_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define D2F1_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define D2F1_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define D2F1_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define D2F1_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define D2F1_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define D2F1_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define D2F1_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define D2F1_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define D2F1_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define D2F1_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define D2F1_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define D2F1_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define D2F1_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define D2F1_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define D2F1_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define D2F1_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define D2F1_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define D2F1_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define D2F1_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define D2F1_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define D2F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
+#define D2F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define D2F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
+#define D2F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define D2F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
+#define D2F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define D2F1_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
+#define D2F1_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define D2F1_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
+#define D2F1_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define D2F1_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
+#define D2F1_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define D2F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
+#define D2F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
+#define D2F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
+#define D2F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define D2F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
+#define D2F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define D2F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
+#define D2F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define D2F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
+#define D2F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define D2F1_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
+#define D2F1_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define D2F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
+#define D2F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define D2F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
+#define D2F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define D2F1_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
+#define D2F1_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define D2F1_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
+#define D2F1_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define D2F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
+#define D2F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define D2F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
+#define D2F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
+#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
+#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
+#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define D2F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
+#define D2F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
+#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
+#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
+#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define D2F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
+#define D2F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define D2F1_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
+#define D2F1_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
+#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
+#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
+#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
+#define D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
+#define D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
+#define D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
+#define D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
+#define D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
+#define D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
+#define D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
+#define D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
+#define D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
+#define D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
+#define D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
+#define D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
+#define D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
+#define D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
+#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
+#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
+#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
+#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
+#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
+#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
+#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define D2F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
+#define D2F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define D2F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
+#define D2F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define D2F1_PCIE_FC_P__PD_CREDITS_MASK 0xff
+#define D2F1_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define D2F1_PCIE_FC_P__PH_CREDITS_MASK 0xff00
+#define D2F1_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
+#define D2F1_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
+#define D2F1_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define D2F1_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
+#define D2F1_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
+#define D2F1_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
+#define D2F1_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define D2F1_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
+#define D2F1_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
+#define D2F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
+#define D2F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define D2F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
+#define D2F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define D2F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
+#define D2F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define D2F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
+#define D2F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define D2F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
+#define D2F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define D2F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
+#define D2F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define D2F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
+#define D2F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
+#define D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
+#define D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define D2F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
+#define D2F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define D2F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
+#define D2F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define D2F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
+#define D2F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define D2F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
+#define D2F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define D2F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
+#define D2F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define D2F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
+#define D2F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define D2F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
+#define D2F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
+#define D2F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
+#define D2F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
+#define D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
+#define D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define D2F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
+#define D2F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
+#define D2F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define D2F1_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
+#define D2F1_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define D2F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
+#define D2F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define D2F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
+#define D2F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
+#define D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
+#define D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
+#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
+#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
+#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
+#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
+#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
+#define D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
+#define D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
+#define D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
+#define D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
+#define D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
+#define D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
+#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
+#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
+#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
+#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
+#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
+#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
+#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
+#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
+#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
+#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
+#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define D2F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
+#define D2F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define D2F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
+#define D2F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define D2F1_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
+#define D2F1_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define D2F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
+#define D2F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define D2F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
+#define D2F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define D2F1_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
+#define D2F1_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define D2F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
+#define D2F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define D2F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
+#define D2F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define D2F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
+#define D2F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define D2F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
+#define D2F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define D2F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
+#define D2F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define D2F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
+#define D2F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define D2F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
+#define D2F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define D2F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
+#define D2F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define D2F1_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
+#define D2F1_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define D2F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
+#define D2F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define D2F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
+#define D2F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define D2F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
+#define D2F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define D2F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
+#define D2F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define D2F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
+#define D2F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define D2F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
+#define D2F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define D2F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
+#define D2F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define D2F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
+#define D2F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define D2F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
+#define D2F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define D2F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
+#define D2F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define D2F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
+#define D2F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
+#define D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
+#define D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
+#define D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define D2F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
+#define D2F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define D2F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
+#define D2F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
+#define D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
+#define D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define D2F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
+#define D2F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
+#define D2F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
+#define D2F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define D2F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
+#define D2F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define D2F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
+#define D2F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
+#define D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define D2F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
+#define D2F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define D2F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
+#define D2F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define D2F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
+#define D2F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define D2F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
+#define D2F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define D2F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
+#define D2F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define D2F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
+#define D2F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
+#define D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
+#define D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define D2F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
+#define D2F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define D2F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
+#define D2F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define D2F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
+#define D2F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
+#define D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
+#define D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define D2F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
+#define D2F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define D2F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
+#define D2F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define D2F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
+#define D2F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define D2F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
+#define D2F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
+#define D2F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
+#define D2F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
+#define D2F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
+#define D2F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
+#define D2F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
+#define D2F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
+#define D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
+#define D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define D2F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
+#define D2F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define D2F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
+#define D2F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
+#define D2F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
+#define D2F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define D2F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
+#define D2F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define D2F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
+#define D2F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define D2F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
+#define D2F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define D2F1_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
+#define D2F1_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
+#define D2F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
+#define D2F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define D2F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
+#define D2F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define D2F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
+#define D2F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
+#define D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
+#define D2F1_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
+#define D2F1_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
+#define D2F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
+#define D2F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define D2F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
+#define D2F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define D2F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
+#define D2F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
+#define D2F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
+#define D2F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define D2F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
+#define D2F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
+#define D2F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
+#define D2F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
+#define D2F1_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
+#define D2F1_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define D2F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
+#define D2F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define D2F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
+#define D2F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
+#define D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
+#define D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
+#define D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
+#define D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
+#define D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
+#define D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
+#define D2F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
+#define D2F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define D2F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
+#define D2F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
+#define D2F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
+#define D2F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define D2F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
+#define D2F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define D2F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
+#define D2F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define D2F1_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
+#define D2F1_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
+#define D2F1_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
+#define D2F1_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
+#define D2F1_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
+#define D2F1_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
+#define D2F1_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
+#define D2F1_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
+#define D2F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
+#define D2F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
+#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
+#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
+#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
+#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
+#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
+#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
+#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
+#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
+#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
+#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
+#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
+#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
+#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
+#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
+#define D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
+#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
+#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
+#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
+#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
+#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define D2F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
+#define D2F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
+#define D2F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
+#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
+#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
+#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
+#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define D2F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
+#define D2F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define D2F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
+#define D2F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
+#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
+#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
+#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
+#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
+#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
+#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
+#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
+#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
+#define D2F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
+#define D2F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
+#define D2F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
+#define D2F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
+#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
+#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
+#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
+#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
+#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
+#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
+#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
+#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
+#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
+#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
+#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
+#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
+#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
+#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
+#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
+#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
+#define D2F1_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
+#define D2F1_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
+#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
+#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
+#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
+#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
+#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
+#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
+#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
+#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
+#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
+#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
+#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
+#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
+#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
+#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
+#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
+#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
+#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
+#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
+#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
+#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
+#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
+#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
+#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define D2F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
+#define D2F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define D2F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
+#define D2F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define D2F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
+#define D2F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define D2F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
+#define D2F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define D2F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
+#define D2F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define D2F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
+#define D2F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define D2F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
+#define D2F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define D2F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
+#define D2F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define D2F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
+#define D2F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define D2F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
+#define D2F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define D2F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
+#define D2F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define D2F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
+#define D2F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define D2F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
+#define D2F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define D2F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
+#define D2F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define D2F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
+#define D2F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define D2F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
+#define D2F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define D2F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
+#define D2F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
+#define D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
+#define D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
+#define D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
+#define D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
+#define D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
+#define D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
+#define D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
+#define D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define D2F1_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
+#define D2F1_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
+#define D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
+#define D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
+#define D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
+#define D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define D2F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
+#define D2F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define D2F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
+#define D2F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define D2F1_VENDOR_ID__VENDOR_ID_MASK 0xffff
+#define D2F1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define D2F1_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
+#define D2F1_DEVICE_ID__DEVICE_ID__SHIFT 0x10
+#define D2F1_COMMAND__IO_ACCESS_EN_MASK 0x1
+#define D2F1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define D2F1_COMMAND__MEM_ACCESS_EN_MASK 0x2
+#define D2F1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define D2F1_COMMAND__BUS_MASTER_EN_MASK 0x4
+#define D2F1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define D2F1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
+#define D2F1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define D2F1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
+#define D2F1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define D2F1_COMMAND__PAL_SNOOP_EN_MASK 0x20
+#define D2F1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define D2F1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
+#define D2F1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define D2F1_COMMAND__AD_STEPPING_MASK 0x80
+#define D2F1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define D2F1_COMMAND__SERR_EN_MASK 0x100
+#define D2F1_COMMAND__SERR_EN__SHIFT 0x8
+#define D2F1_COMMAND__FAST_B2B_EN_MASK 0x200
+#define D2F1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define D2F1_COMMAND__INT_DIS_MASK 0x400
+#define D2F1_COMMAND__INT_DIS__SHIFT 0xa
+#define D2F1_STATUS__INT_STATUS_MASK 0x80000
+#define D2F1_STATUS__INT_STATUS__SHIFT 0x13
+#define D2F1_STATUS__CAP_LIST_MASK 0x100000
+#define D2F1_STATUS__CAP_LIST__SHIFT 0x14
+#define D2F1_STATUS__PCI_66_EN_MASK 0x200000
+#define D2F1_STATUS__PCI_66_EN__SHIFT 0x15
+#define D2F1_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
+#define D2F1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
+#define D2F1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
+#define D2F1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
+#define D2F1_STATUS__DEVSEL_TIMING_MASK 0x6000000
+#define D2F1_STATUS__DEVSEL_TIMING__SHIFT 0x19
+#define D2F1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
+#define D2F1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
+#define D2F1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
+#define D2F1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
+#define D2F1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
+#define D2F1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
+#define D2F1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
+#define D2F1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
+#define D2F1_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
+#define D2F1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
+#define D2F1_REVISION_ID__MINOR_REV_ID_MASK 0xf
+#define D2F1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define D2F1_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
+#define D2F1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define D2F1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
+#define D2F1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
+#define D2F1_SUB_CLASS__SUB_CLASS_MASK 0xff0000
+#define D2F1_SUB_CLASS__SUB_CLASS__SHIFT 0x10
+#define D2F1_BASE_CLASS__BASE_CLASS_MASK 0xff000000
+#define D2F1_BASE_CLASS__BASE_CLASS__SHIFT 0x18
+#define D2F1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
+#define D2F1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define D2F1_LATENCY__LATENCY_TIMER_MASK 0xff00
+#define D2F1_LATENCY__LATENCY_TIMER__SHIFT 0x8
+#define D2F1_HEADER__HEADER_TYPE_MASK 0x7f0000
+#define D2F1_HEADER__HEADER_TYPE__SHIFT 0x10
+#define D2F1_HEADER__DEVICE_TYPE_MASK 0x800000
+#define D2F1_HEADER__DEVICE_TYPE__SHIFT 0x17
+#define D2F1_BIST__BIST_COMP_MASK 0xf000000
+#define D2F1_BIST__BIST_COMP__SHIFT 0x18
+#define D2F1_BIST__BIST_STRT_MASK 0x40000000
+#define D2F1_BIST__BIST_STRT__SHIFT 0x1e
+#define D2F1_BIST__BIST_CAP_MASK 0x80000000
+#define D2F1_BIST__BIST_CAP__SHIFT 0x1f
+#define D2F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
+#define D2F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
+#define D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define D2F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
+#define D2F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
+#define D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define D2F1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
+#define D2F1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define D2F1_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
+#define D2F1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define D2F1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
+#define D2F1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define D2F1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
+#define D2F1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define D2F1_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
+#define D2F1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
+#define D2F1_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
+#define D2F1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
+#define D2F1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
+#define D2F1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
+#define D2F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
+#define D2F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
+#define D2F1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
+#define D2F1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
+#define D2F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
+#define D2F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
+#define D2F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
+#define D2F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
+#define D2F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
+#define D2F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
+#define D2F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
+#define D2F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
+#define D2F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
+#define D2F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
+#define D2F1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
+#define D2F1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define D2F1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
+#define D2F1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define D2F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
+#define D2F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define D2F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
+#define D2F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
+#define D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
+#define D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
+#define D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
+#define D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define D2F1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
+#define D2F1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define D2F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
+#define D2F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define D2F1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
+#define D2F1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define D2F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
+#define D2F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define D2F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
+#define D2F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
+#define D2F1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
+#define D2F1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
+#define D2F1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
+#define D2F1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
+#define D2F1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
+#define D2F1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
+#define D2F1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
+#define D2F1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
+#define D2F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
+#define D2F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
+#define D2F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
+#define D2F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
+#define D2F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
+#define D2F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
+#define D2F1_CAP_PTR__CAP_PTR_MASK 0xff
+#define D2F1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define D2F1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
+#define D2F1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define D2F1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
+#define D2F1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
+#define D2F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
+#define D2F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define D2F1_PMI_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F1_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F1_PMI_CAP__VERSION_MASK 0x70000
+#define D2F1_PMI_CAP__VERSION__SHIFT 0x10
+#define D2F1_PMI_CAP__PME_CLOCK_MASK 0x80000
+#define D2F1_PMI_CAP__PME_CLOCK__SHIFT 0x13
+#define D2F1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
+#define D2F1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
+#define D2F1_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
+#define D2F1_PMI_CAP__AUX_CURRENT__SHIFT 0x16
+#define D2F1_PMI_CAP__D1_SUPPORT_MASK 0x2000000
+#define D2F1_PMI_CAP__D1_SUPPORT__SHIFT 0x19
+#define D2F1_PMI_CAP__D2_SUPPORT_MASK 0x4000000
+#define D2F1_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
+#define D2F1_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
+#define D2F1_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
+#define D2F1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
+#define D2F1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define D2F1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
+#define D2F1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define D2F1_PMI_STATUS_CNTL__PME_EN_MASK 0x100
+#define D2F1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define D2F1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
+#define D2F1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define D2F1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
+#define D2F1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define D2F1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
+#define D2F1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define D2F1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
+#define D2F1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define D2F1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
+#define D2F1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define D2F1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
+#define D2F1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define D2F1_PCIE_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F1_PCIE_CAP__VERSION_MASK 0xf0000
+#define D2F1_PCIE_CAP__VERSION__SHIFT 0x10
+#define D2F1_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
+#define D2F1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
+#define D2F1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
+#define D2F1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
+#define D2F1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
+#define D2F1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
+#define D2F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
+#define D2F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define D2F1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
+#define D2F1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define D2F1_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
+#define D2F1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define D2F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
+#define D2F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define D2F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
+#define D2F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define D2F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
+#define D2F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
+#define D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
+#define D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define D2F1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
+#define D2F1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define D2F1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
+#define D2F1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define D2F1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
+#define D2F1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define D2F1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
+#define D2F1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define D2F1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
+#define D2F1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define D2F1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
+#define D2F1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define D2F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
+#define D2F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define D2F1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
+#define D2F1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define D2F1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
+#define D2F1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define D2F1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
+#define D2F1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define D2F1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
+#define D2F1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define D2F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
+#define D2F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define D2F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
+#define D2F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define D2F1_DEVICE_STATUS__CORR_ERR_MASK 0x10000
+#define D2F1_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
+#define D2F1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
+#define D2F1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
+#define D2F1_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
+#define D2F1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
+#define D2F1_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
+#define D2F1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
+#define D2F1_DEVICE_STATUS__AUX_PWR_MASK 0x100000
+#define D2F1_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
+#define D2F1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
+#define D2F1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
+#define D2F1_LINK_CAP__LINK_SPEED_MASK 0xf
+#define D2F1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define D2F1_LINK_CAP__LINK_WIDTH_MASK 0x3f0
+#define D2F1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define D2F1_LINK_CAP__PM_SUPPORT_MASK 0xc00
+#define D2F1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define D2F1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
+#define D2F1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define D2F1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
+#define D2F1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define D2F1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
+#define D2F1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define D2F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
+#define D2F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define D2F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
+#define D2F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define D2F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
+#define D2F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define D2F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
+#define D2F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define D2F1_LINK_CAP__PORT_NUMBER_MASK 0xff000000
+#define D2F1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define D2F1_LINK_CNTL__PM_CONTROL_MASK 0x3
+#define D2F1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define D2F1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
+#define D2F1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define D2F1_LINK_CNTL__LINK_DIS_MASK 0x10
+#define D2F1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define D2F1_LINK_CNTL__RETRAIN_LINK_MASK 0x20
+#define D2F1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define D2F1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
+#define D2F1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define D2F1_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
+#define D2F1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define D2F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
+#define D2F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define D2F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
+#define D2F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define D2F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
+#define D2F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define D2F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
+#define D2F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define D2F1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
+#define D2F1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
+#define D2F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
+#define D2F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
+#define D2F1_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
+#define D2F1_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
+#define D2F1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
+#define D2F1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
+#define D2F1_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
+#define D2F1_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
+#define D2F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
+#define D2F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
+#define D2F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
+#define D2F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
+#define D2F1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
+#define D2F1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define D2F1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
+#define D2F1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define D2F1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
+#define D2F1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define D2F1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
+#define D2F1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define D2F1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
+#define D2F1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define D2F1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
+#define D2F1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define D2F1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
+#define D2F1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define D2F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
+#define D2F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define D2F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
+#define D2F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define D2F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
+#define D2F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define D2F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
+#define D2F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define D2F1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
+#define D2F1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define D2F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
+#define D2F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define D2F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
+#define D2F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define D2F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
+#define D2F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define D2F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
+#define D2F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define D2F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
+#define D2F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define D2F1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
+#define D2F1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define D2F1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
+#define D2F1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define D2F1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
+#define D2F1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define D2F1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
+#define D2F1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define D2F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
+#define D2F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define D2F1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
+#define D2F1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define D2F1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
+#define D2F1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
+#define D2F1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
+#define D2F1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
+#define D2F1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
+#define D2F1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
+#define D2F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
+#define D2F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
+#define D2F1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
+#define D2F1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
+#define D2F1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
+#define D2F1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
+#define D2F1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
+#define D2F1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
+#define D2F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
+#define D2F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
+#define D2F1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
+#define D2F1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
+#define D2F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
+#define D2F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define D2F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
+#define D2F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define D2F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
+#define D2F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define D2F1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
+#define D2F1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define D2F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
+#define D2F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define D2F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
+#define D2F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
+#define D2F1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
+#define D2F1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define D2F1_ROOT_STATUS__PME_STATUS_MASK 0x10000
+#define D2F1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define D2F1_ROOT_STATUS__PME_PENDING_MASK 0x20000
+#define D2F1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define D2F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
+#define D2F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define D2F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
+#define D2F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define D2F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
+#define D2F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define D2F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
+#define D2F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define D2F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
+#define D2F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define D2F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
+#define D2F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define D2F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
+#define D2F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define D2F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
+#define D2F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define D2F1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
+#define D2F1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define D2F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
+#define D2F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define D2F1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
+#define D2F1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define D2F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
+#define D2F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define D2F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
+#define D2F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define D2F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
+#define D2F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define D2F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
+#define D2F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define D2F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
+#define D2F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define D2F1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
+#define D2F1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define D2F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
+#define D2F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define D2F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
+#define D2F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define D2F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
+#define D2F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define D2F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
+#define D2F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define D2F1_DEVICE_CNTL2__LTR_EN_MASK 0x400
+#define D2F1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define D2F1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
+#define D2F1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define D2F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
+#define D2F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define D2F1_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
+#define D2F1_DEVICE_STATUS2__RESERVED__SHIFT 0x10
+#define D2F1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
+#define D2F1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define D2F1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
+#define D2F1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define D2F1_LINK_CAP2__RESERVED_MASK 0xfffffe00
+#define D2F1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define D2F1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
+#define D2F1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define D2F1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
+#define D2F1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define D2F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
+#define D2F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define D2F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
+#define D2F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define D2F1_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
+#define D2F1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define D2F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
+#define D2F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define D2F1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
+#define D2F1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define D2F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
+#define D2F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define D2F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
+#define D2F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
+#define D2F1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
+#define D2F1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
+#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
+#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
+#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
+#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
+#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
+#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
+#define D2F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
+#define D2F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
+#define D2F1_SLOT_CAP2__RESERVED_MASK 0xffffffff
+#define D2F1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define D2F1_SLOT_CNTL2__RESERVED_MASK 0xffff
+#define D2F1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define D2F1_SLOT_STATUS2__RESERVED_MASK 0xffff0000
+#define D2F1_SLOT_STATUS2__RESERVED__SHIFT 0x10
+#define D2F1_MSI_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F1_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F1_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
+#define D2F1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
+#define D2F1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
+#define D2F1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
+#define D2F1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
+#define D2F1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
+#define D2F1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
+#define D2F1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
+#define D2F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
+#define D2F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
+#define D2F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
+#define D2F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define D2F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
+#define D2F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define D2F1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
+#define D2F1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define D2F1_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
+#define D2F1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define D2F1_SSID_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F1_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
+#define D2F1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define D2F1_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
+#define D2F1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define D2F1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F1_MSI_MAP_CAP__EN_MASK 0x10000
+#define D2F1_MSI_MAP_CAP__EN__SHIFT 0x10
+#define D2F1_MSI_MAP_CAP__FIXD_MASK 0x20000
+#define D2F1_MSI_MAP_CAP__FIXD__SHIFT 0x11
+#define D2F1_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
+#define D2F1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
+#define D2F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
+#define D2F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define D2F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
+#define D2F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
+#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
+#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
+#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define D2F1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
+#define D2F1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define D2F1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
+#define D2F1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define D2F1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
+#define D2F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define D2F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
+#define D2F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define D2F1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
+#define D2F1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define D2F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
+#define D2F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
+#define D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D2F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
+#define D2F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define D2F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
+#define D2F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define D2F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
+#define D2F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
+#define D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define D2F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define D2F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define D2F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define D2F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define D2F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define D2F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define D2F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define D2F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define D2F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
+#define D2F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
+#define D2F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
+#define D2F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
+#define D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define D2F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define D2F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define D2F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define D2F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define D2F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define D2F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define D2F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define D2F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define D2F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
+#define D2F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
+#define D2F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
+#define D2F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
+#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
+#define D2F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define D2F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
+#define D2F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
+#define D2F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define D2F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
+#define D2F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define D2F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
+#define D2F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define D2F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
+#define D2F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define D2F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
+#define D2F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define D2F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
+#define D2F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define D2F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
+#define D2F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define D2F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
+#define D2F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define D2F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
+#define D2F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define D2F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
+#define D2F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define D2F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
+#define D2F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define D2F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
+#define D2F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define D2F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
+#define D2F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define D2F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
+#define D2F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define D2F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
+#define D2F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define D2F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
+#define D2F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define D2F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
+#define D2F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define D2F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
+#define D2F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define D2F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
+#define D2F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define D2F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
+#define D2F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define D2F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
+#define D2F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define D2F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
+#define D2F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define D2F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
+#define D2F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define D2F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
+#define D2F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define D2F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
+#define D2F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define D2F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
+#define D2F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define D2F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
+#define D2F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define D2F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
+#define D2F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define D2F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
+#define D2F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define D2F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
+#define D2F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define D2F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
+#define D2F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define D2F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
+#define D2F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
+#define D2F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define D2F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
+#define D2F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define D2F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
+#define D2F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define D2F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
+#define D2F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define D2F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
+#define D2F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define D2F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
+#define D2F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define D2F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
+#define D2F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define D2F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
+#define D2F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define D2F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
+#define D2F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define D2F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
+#define D2F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define D2F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
+#define D2F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define D2F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
+#define D2F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define D2F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
+#define D2F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define D2F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
+#define D2F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define D2F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
+#define D2F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define D2F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
+#define D2F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define D2F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
+#define D2F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define D2F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
+#define D2F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
+#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
+#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
+#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
+#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
+#define D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
+#define D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define D2F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
+#define D2F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define D2F1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
+#define D2F1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define D2F1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
+#define D2F1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define D2F1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
+#define D2F1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define D2F1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
+#define D2F1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define D2F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
+#define D2F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define D2F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
+#define D2F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define D2F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
+#define D2F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define D2F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
+#define D2F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
+#define D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define D2F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
+#define D2F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
+#define D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define D2F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
+#define D2F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define D2F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
+#define D2F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define D2F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
+#define D2F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define D2F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
+#define D2F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define D2F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
+#define D2F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define D2F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
+#define D2F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define D2F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
+#define D2F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define D2F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
+#define D2F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define D2F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
+#define D2F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define D2F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
+#define D2F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
+#define D2F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define D2F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
+#define D2F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define D2F1_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
+#define D2F1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define D2F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
+#define D2F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define D2F1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
+#define D2F1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
+#define D2F1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define D2F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
+#define D2F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define D2F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
+#define D2F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define D2F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
+#define D2F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define D2F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
+#define D2F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define D2F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
+#define D2F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define D2F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
+#define D2F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define D2F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
+#define D2F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define D2F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
+#define D2F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
+#define D2F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
+#define D2F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
+#define D2F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
+#define D2F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
+#define D2F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
+#define D2F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
+#define D2F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
+#define D2F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
+#define D2F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
+#define D2F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
+#define D2F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
+#define D2F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
+#define D2F1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
+#define D2F1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define D2F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
+#define D2F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define D2F1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
+#define D2F1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
+#define D2F1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
+#define D2F1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
+#define D2F1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
+#define D2F1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define D2F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
+#define D2F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define D2F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
+#define D2F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define D2F1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
+#define D2F1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define D2F1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
+#define D2F1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define D2F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
+#define D2F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define D2F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
+#define D2F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define D2F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
+#define D2F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define D2F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
+#define D2F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
+#define D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
+#define D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define D2F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
+#define D2F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define D2F2_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
+#define D2F2_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
+#define D2F2_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
+#define D2F2_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
+#define D2F2_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
+#define D2F2_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define D2F2_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
+#define D2F2_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define D2F2_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define D2F2_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define D2F2_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define D2F2_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define D2F2_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define D2F2_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define D2F2_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define D2F2_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define D2F2_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define D2F2_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define D2F2_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define D2F2_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define D2F2_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define D2F2_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define D2F2_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define D2F2_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define D2F2_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define D2F2_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define D2F2_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define D2F2_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define D2F2_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define D2F2_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define D2F2_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define D2F2_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define D2F2_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define D2F2_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define D2F2_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define D2F2_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define D2F2_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define D2F2_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define D2F2_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define D2F2_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define D2F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
+#define D2F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define D2F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
+#define D2F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define D2F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
+#define D2F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define D2F2_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
+#define D2F2_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define D2F2_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
+#define D2F2_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define D2F2_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
+#define D2F2_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define D2F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
+#define D2F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
+#define D2F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
+#define D2F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define D2F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
+#define D2F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define D2F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
+#define D2F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define D2F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
+#define D2F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define D2F2_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
+#define D2F2_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define D2F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
+#define D2F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define D2F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
+#define D2F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define D2F2_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
+#define D2F2_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define D2F2_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
+#define D2F2_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define D2F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
+#define D2F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define D2F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
+#define D2F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
+#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
+#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
+#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define D2F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
+#define D2F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
+#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
+#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
+#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define D2F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
+#define D2F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define D2F2_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
+#define D2F2_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
+#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
+#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
+#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
+#define D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
+#define D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
+#define D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
+#define D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
+#define D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
+#define D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
+#define D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
+#define D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
+#define D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
+#define D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
+#define D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
+#define D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
+#define D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
+#define D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
+#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
+#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
+#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
+#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
+#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
+#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
+#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define D2F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
+#define D2F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define D2F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
+#define D2F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define D2F2_PCIE_FC_P__PD_CREDITS_MASK 0xff
+#define D2F2_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define D2F2_PCIE_FC_P__PH_CREDITS_MASK 0xff00
+#define D2F2_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
+#define D2F2_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
+#define D2F2_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define D2F2_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
+#define D2F2_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
+#define D2F2_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
+#define D2F2_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define D2F2_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
+#define D2F2_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
+#define D2F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
+#define D2F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define D2F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
+#define D2F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define D2F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
+#define D2F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define D2F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
+#define D2F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define D2F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
+#define D2F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define D2F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
+#define D2F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define D2F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
+#define D2F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
+#define D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
+#define D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define D2F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
+#define D2F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define D2F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
+#define D2F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define D2F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
+#define D2F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define D2F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
+#define D2F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define D2F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
+#define D2F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define D2F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
+#define D2F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define D2F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
+#define D2F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
+#define D2F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
+#define D2F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
+#define D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
+#define D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define D2F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
+#define D2F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
+#define D2F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define D2F2_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
+#define D2F2_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define D2F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
+#define D2F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define D2F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
+#define D2F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
+#define D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
+#define D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
+#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
+#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
+#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
+#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
+#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
+#define D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
+#define D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
+#define D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
+#define D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
+#define D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
+#define D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
+#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
+#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
+#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
+#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
+#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
+#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
+#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
+#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
+#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
+#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
+#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define D2F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
+#define D2F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define D2F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
+#define D2F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define D2F2_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
+#define D2F2_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define D2F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
+#define D2F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define D2F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
+#define D2F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define D2F2_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
+#define D2F2_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define D2F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
+#define D2F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define D2F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
+#define D2F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define D2F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
+#define D2F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define D2F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
+#define D2F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define D2F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
+#define D2F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define D2F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
+#define D2F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define D2F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
+#define D2F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define D2F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
+#define D2F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define D2F2_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
+#define D2F2_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define D2F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
+#define D2F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define D2F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
+#define D2F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define D2F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
+#define D2F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define D2F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
+#define D2F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define D2F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
+#define D2F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define D2F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
+#define D2F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define D2F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
+#define D2F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define D2F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
+#define D2F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define D2F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
+#define D2F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define D2F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
+#define D2F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define D2F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
+#define D2F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
+#define D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
+#define D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
+#define D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define D2F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
+#define D2F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define D2F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
+#define D2F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
+#define D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
+#define D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define D2F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
+#define D2F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
+#define D2F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
+#define D2F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define D2F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
+#define D2F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define D2F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
+#define D2F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
+#define D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define D2F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
+#define D2F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define D2F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
+#define D2F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define D2F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
+#define D2F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define D2F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
+#define D2F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define D2F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
+#define D2F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define D2F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
+#define D2F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
+#define D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
+#define D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define D2F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
+#define D2F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define D2F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
+#define D2F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define D2F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
+#define D2F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
+#define D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
+#define D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define D2F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
+#define D2F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define D2F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
+#define D2F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define D2F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
+#define D2F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define D2F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
+#define D2F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
+#define D2F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
+#define D2F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
+#define D2F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
+#define D2F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
+#define D2F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
+#define D2F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
+#define D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
+#define D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define D2F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
+#define D2F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define D2F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
+#define D2F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
+#define D2F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
+#define D2F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define D2F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
+#define D2F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define D2F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
+#define D2F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define D2F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
+#define D2F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define D2F2_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
+#define D2F2_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
+#define D2F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
+#define D2F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define D2F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
+#define D2F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define D2F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
+#define D2F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
+#define D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
+#define D2F2_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
+#define D2F2_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
+#define D2F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
+#define D2F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define D2F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
+#define D2F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define D2F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
+#define D2F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
+#define D2F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
+#define D2F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define D2F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
+#define D2F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
+#define D2F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
+#define D2F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
+#define D2F2_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
+#define D2F2_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define D2F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
+#define D2F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define D2F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
+#define D2F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
+#define D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
+#define D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
+#define D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
+#define D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
+#define D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
+#define D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
+#define D2F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
+#define D2F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define D2F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
+#define D2F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
+#define D2F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
+#define D2F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define D2F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
+#define D2F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define D2F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
+#define D2F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define D2F2_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
+#define D2F2_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
+#define D2F2_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
+#define D2F2_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
+#define D2F2_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
+#define D2F2_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
+#define D2F2_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
+#define D2F2_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
+#define D2F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
+#define D2F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
+#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
+#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
+#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
+#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
+#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
+#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
+#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
+#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
+#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
+#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
+#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
+#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
+#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
+#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
+#define D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
+#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
+#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
+#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
+#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
+#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define D2F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
+#define D2F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
+#define D2F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
+#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
+#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
+#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
+#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define D2F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
+#define D2F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define D2F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
+#define D2F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
+#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
+#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
+#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
+#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
+#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
+#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
+#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
+#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
+#define D2F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
+#define D2F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
+#define D2F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
+#define D2F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
+#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
+#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
+#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
+#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
+#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
+#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
+#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
+#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
+#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
+#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
+#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
+#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
+#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
+#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
+#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
+#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
+#define D2F2_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
+#define D2F2_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
+#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
+#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
+#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
+#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
+#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
+#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
+#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
+#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
+#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
+#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
+#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
+#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
+#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
+#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
+#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
+#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
+#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
+#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
+#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
+#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
+#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
+#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
+#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define D2F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
+#define D2F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define D2F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
+#define D2F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define D2F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
+#define D2F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define D2F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
+#define D2F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define D2F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
+#define D2F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define D2F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
+#define D2F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define D2F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
+#define D2F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define D2F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
+#define D2F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define D2F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
+#define D2F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define D2F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
+#define D2F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define D2F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
+#define D2F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define D2F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
+#define D2F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define D2F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
+#define D2F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define D2F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
+#define D2F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define D2F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
+#define D2F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define D2F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
+#define D2F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define D2F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
+#define D2F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
+#define D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
+#define D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
+#define D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
+#define D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
+#define D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
+#define D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
+#define D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
+#define D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define D2F2_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
+#define D2F2_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
+#define D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
+#define D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
+#define D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
+#define D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define D2F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
+#define D2F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define D2F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
+#define D2F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define D2F2_VENDOR_ID__VENDOR_ID_MASK 0xffff
+#define D2F2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define D2F2_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
+#define D2F2_DEVICE_ID__DEVICE_ID__SHIFT 0x10
+#define D2F2_COMMAND__IO_ACCESS_EN_MASK 0x1
+#define D2F2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define D2F2_COMMAND__MEM_ACCESS_EN_MASK 0x2
+#define D2F2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define D2F2_COMMAND__BUS_MASTER_EN_MASK 0x4
+#define D2F2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define D2F2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
+#define D2F2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define D2F2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
+#define D2F2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define D2F2_COMMAND__PAL_SNOOP_EN_MASK 0x20
+#define D2F2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define D2F2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
+#define D2F2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define D2F2_COMMAND__AD_STEPPING_MASK 0x80
+#define D2F2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define D2F2_COMMAND__SERR_EN_MASK 0x100
+#define D2F2_COMMAND__SERR_EN__SHIFT 0x8
+#define D2F2_COMMAND__FAST_B2B_EN_MASK 0x200
+#define D2F2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define D2F2_COMMAND__INT_DIS_MASK 0x400
+#define D2F2_COMMAND__INT_DIS__SHIFT 0xa
+#define D2F2_STATUS__INT_STATUS_MASK 0x80000
+#define D2F2_STATUS__INT_STATUS__SHIFT 0x13
+#define D2F2_STATUS__CAP_LIST_MASK 0x100000
+#define D2F2_STATUS__CAP_LIST__SHIFT 0x14
+#define D2F2_STATUS__PCI_66_EN_MASK 0x200000
+#define D2F2_STATUS__PCI_66_EN__SHIFT 0x15
+#define D2F2_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
+#define D2F2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
+#define D2F2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
+#define D2F2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
+#define D2F2_STATUS__DEVSEL_TIMING_MASK 0x6000000
+#define D2F2_STATUS__DEVSEL_TIMING__SHIFT 0x19
+#define D2F2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
+#define D2F2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
+#define D2F2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
+#define D2F2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
+#define D2F2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
+#define D2F2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
+#define D2F2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
+#define D2F2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
+#define D2F2_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
+#define D2F2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
+#define D2F2_REVISION_ID__MINOR_REV_ID_MASK 0xf
+#define D2F2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define D2F2_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
+#define D2F2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define D2F2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
+#define D2F2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
+#define D2F2_SUB_CLASS__SUB_CLASS_MASK 0xff0000
+#define D2F2_SUB_CLASS__SUB_CLASS__SHIFT 0x10
+#define D2F2_BASE_CLASS__BASE_CLASS_MASK 0xff000000
+#define D2F2_BASE_CLASS__BASE_CLASS__SHIFT 0x18
+#define D2F2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
+#define D2F2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define D2F2_LATENCY__LATENCY_TIMER_MASK 0xff00
+#define D2F2_LATENCY__LATENCY_TIMER__SHIFT 0x8
+#define D2F2_HEADER__HEADER_TYPE_MASK 0x7f0000
+#define D2F2_HEADER__HEADER_TYPE__SHIFT 0x10
+#define D2F2_HEADER__DEVICE_TYPE_MASK 0x800000
+#define D2F2_HEADER__DEVICE_TYPE__SHIFT 0x17
+#define D2F2_BIST__BIST_COMP_MASK 0xf000000
+#define D2F2_BIST__BIST_COMP__SHIFT 0x18
+#define D2F2_BIST__BIST_STRT_MASK 0x40000000
+#define D2F2_BIST__BIST_STRT__SHIFT 0x1e
+#define D2F2_BIST__BIST_CAP_MASK 0x80000000
+#define D2F2_BIST__BIST_CAP__SHIFT 0x1f
+#define D2F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
+#define D2F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
+#define D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define D2F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
+#define D2F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
+#define D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define D2F2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
+#define D2F2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define D2F2_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
+#define D2F2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define D2F2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
+#define D2F2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define D2F2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
+#define D2F2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define D2F2_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
+#define D2F2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
+#define D2F2_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
+#define D2F2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
+#define D2F2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
+#define D2F2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
+#define D2F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
+#define D2F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
+#define D2F2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
+#define D2F2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
+#define D2F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
+#define D2F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
+#define D2F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
+#define D2F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
+#define D2F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
+#define D2F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
+#define D2F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
+#define D2F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
+#define D2F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
+#define D2F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
+#define D2F2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
+#define D2F2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define D2F2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
+#define D2F2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define D2F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
+#define D2F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define D2F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
+#define D2F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
+#define D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
+#define D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
+#define D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
+#define D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define D2F2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
+#define D2F2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define D2F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
+#define D2F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define D2F2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
+#define D2F2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define D2F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
+#define D2F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define D2F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
+#define D2F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
+#define D2F2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
+#define D2F2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
+#define D2F2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
+#define D2F2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
+#define D2F2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
+#define D2F2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
+#define D2F2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
+#define D2F2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
+#define D2F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
+#define D2F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
+#define D2F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
+#define D2F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
+#define D2F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
+#define D2F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
+#define D2F2_CAP_PTR__CAP_PTR_MASK 0xff
+#define D2F2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define D2F2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
+#define D2F2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define D2F2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
+#define D2F2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
+#define D2F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
+#define D2F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define D2F2_PMI_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F2_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F2_PMI_CAP__VERSION_MASK 0x70000
+#define D2F2_PMI_CAP__VERSION__SHIFT 0x10
+#define D2F2_PMI_CAP__PME_CLOCK_MASK 0x80000
+#define D2F2_PMI_CAP__PME_CLOCK__SHIFT 0x13
+#define D2F2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
+#define D2F2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
+#define D2F2_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
+#define D2F2_PMI_CAP__AUX_CURRENT__SHIFT 0x16
+#define D2F2_PMI_CAP__D1_SUPPORT_MASK 0x2000000
+#define D2F2_PMI_CAP__D1_SUPPORT__SHIFT 0x19
+#define D2F2_PMI_CAP__D2_SUPPORT_MASK 0x4000000
+#define D2F2_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
+#define D2F2_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
+#define D2F2_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
+#define D2F2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
+#define D2F2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define D2F2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
+#define D2F2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define D2F2_PMI_STATUS_CNTL__PME_EN_MASK 0x100
+#define D2F2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define D2F2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
+#define D2F2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define D2F2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
+#define D2F2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define D2F2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
+#define D2F2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define D2F2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
+#define D2F2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define D2F2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
+#define D2F2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define D2F2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
+#define D2F2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define D2F2_PCIE_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F2_PCIE_CAP__VERSION_MASK 0xf0000
+#define D2F2_PCIE_CAP__VERSION__SHIFT 0x10
+#define D2F2_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
+#define D2F2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
+#define D2F2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
+#define D2F2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
+#define D2F2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
+#define D2F2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
+#define D2F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
+#define D2F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define D2F2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
+#define D2F2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define D2F2_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
+#define D2F2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define D2F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
+#define D2F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define D2F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
+#define D2F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define D2F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
+#define D2F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
+#define D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
+#define D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define D2F2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
+#define D2F2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define D2F2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
+#define D2F2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define D2F2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
+#define D2F2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define D2F2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
+#define D2F2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define D2F2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
+#define D2F2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define D2F2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
+#define D2F2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define D2F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
+#define D2F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define D2F2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
+#define D2F2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define D2F2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
+#define D2F2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define D2F2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
+#define D2F2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define D2F2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
+#define D2F2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define D2F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
+#define D2F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define D2F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
+#define D2F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define D2F2_DEVICE_STATUS__CORR_ERR_MASK 0x10000
+#define D2F2_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
+#define D2F2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
+#define D2F2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
+#define D2F2_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
+#define D2F2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
+#define D2F2_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
+#define D2F2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
+#define D2F2_DEVICE_STATUS__AUX_PWR_MASK 0x100000
+#define D2F2_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
+#define D2F2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
+#define D2F2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
+#define D2F2_LINK_CAP__LINK_SPEED_MASK 0xf
+#define D2F2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define D2F2_LINK_CAP__LINK_WIDTH_MASK 0x3f0
+#define D2F2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define D2F2_LINK_CAP__PM_SUPPORT_MASK 0xc00
+#define D2F2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define D2F2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
+#define D2F2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define D2F2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
+#define D2F2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define D2F2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
+#define D2F2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define D2F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
+#define D2F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define D2F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
+#define D2F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define D2F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
+#define D2F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define D2F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
+#define D2F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define D2F2_LINK_CAP__PORT_NUMBER_MASK 0xff000000
+#define D2F2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define D2F2_LINK_CNTL__PM_CONTROL_MASK 0x3
+#define D2F2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define D2F2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
+#define D2F2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define D2F2_LINK_CNTL__LINK_DIS_MASK 0x10
+#define D2F2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define D2F2_LINK_CNTL__RETRAIN_LINK_MASK 0x20
+#define D2F2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define D2F2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
+#define D2F2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define D2F2_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
+#define D2F2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define D2F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
+#define D2F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define D2F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
+#define D2F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define D2F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
+#define D2F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define D2F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
+#define D2F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define D2F2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
+#define D2F2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
+#define D2F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
+#define D2F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
+#define D2F2_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
+#define D2F2_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
+#define D2F2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
+#define D2F2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
+#define D2F2_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
+#define D2F2_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
+#define D2F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
+#define D2F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
+#define D2F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
+#define D2F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
+#define D2F2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
+#define D2F2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define D2F2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
+#define D2F2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define D2F2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
+#define D2F2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define D2F2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
+#define D2F2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define D2F2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
+#define D2F2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define D2F2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
+#define D2F2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define D2F2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
+#define D2F2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define D2F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
+#define D2F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define D2F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
+#define D2F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define D2F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
+#define D2F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define D2F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
+#define D2F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define D2F2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
+#define D2F2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define D2F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
+#define D2F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define D2F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
+#define D2F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define D2F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
+#define D2F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define D2F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
+#define D2F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define D2F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
+#define D2F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define D2F2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
+#define D2F2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define D2F2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
+#define D2F2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define D2F2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
+#define D2F2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define D2F2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
+#define D2F2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define D2F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
+#define D2F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define D2F2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
+#define D2F2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define D2F2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
+#define D2F2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
+#define D2F2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
+#define D2F2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
+#define D2F2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
+#define D2F2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
+#define D2F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
+#define D2F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
+#define D2F2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
+#define D2F2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
+#define D2F2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
+#define D2F2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
+#define D2F2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
+#define D2F2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
+#define D2F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
+#define D2F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
+#define D2F2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
+#define D2F2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
+#define D2F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
+#define D2F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define D2F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
+#define D2F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define D2F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
+#define D2F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define D2F2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
+#define D2F2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define D2F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
+#define D2F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define D2F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
+#define D2F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
+#define D2F2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
+#define D2F2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define D2F2_ROOT_STATUS__PME_STATUS_MASK 0x10000
+#define D2F2_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define D2F2_ROOT_STATUS__PME_PENDING_MASK 0x20000
+#define D2F2_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define D2F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
+#define D2F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define D2F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
+#define D2F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define D2F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
+#define D2F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define D2F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
+#define D2F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define D2F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
+#define D2F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define D2F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
+#define D2F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define D2F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
+#define D2F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define D2F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
+#define D2F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define D2F2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
+#define D2F2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define D2F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
+#define D2F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define D2F2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
+#define D2F2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define D2F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
+#define D2F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define D2F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
+#define D2F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define D2F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
+#define D2F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define D2F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
+#define D2F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define D2F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
+#define D2F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define D2F2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
+#define D2F2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define D2F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
+#define D2F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define D2F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
+#define D2F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define D2F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
+#define D2F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define D2F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
+#define D2F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define D2F2_DEVICE_CNTL2__LTR_EN_MASK 0x400
+#define D2F2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define D2F2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
+#define D2F2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define D2F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
+#define D2F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define D2F2_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
+#define D2F2_DEVICE_STATUS2__RESERVED__SHIFT 0x10
+#define D2F2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
+#define D2F2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define D2F2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
+#define D2F2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define D2F2_LINK_CAP2__RESERVED_MASK 0xfffffe00
+#define D2F2_LINK_CAP2__RESERVED__SHIFT 0x9
+#define D2F2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
+#define D2F2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define D2F2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
+#define D2F2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define D2F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
+#define D2F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define D2F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
+#define D2F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define D2F2_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
+#define D2F2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define D2F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
+#define D2F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define D2F2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
+#define D2F2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define D2F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
+#define D2F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define D2F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
+#define D2F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
+#define D2F2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
+#define D2F2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
+#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
+#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
+#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
+#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
+#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
+#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
+#define D2F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
+#define D2F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
+#define D2F2_SLOT_CAP2__RESERVED_MASK 0xffffffff
+#define D2F2_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define D2F2_SLOT_CNTL2__RESERVED_MASK 0xffff
+#define D2F2_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define D2F2_SLOT_STATUS2__RESERVED_MASK 0xffff0000
+#define D2F2_SLOT_STATUS2__RESERVED__SHIFT 0x10
+#define D2F2_MSI_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F2_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F2_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
+#define D2F2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
+#define D2F2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
+#define D2F2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
+#define D2F2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
+#define D2F2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
+#define D2F2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
+#define D2F2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
+#define D2F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
+#define D2F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
+#define D2F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
+#define D2F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define D2F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
+#define D2F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define D2F2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
+#define D2F2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define D2F2_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
+#define D2F2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define D2F2_SSID_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F2_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
+#define D2F2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define D2F2_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
+#define D2F2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define D2F2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F2_MSI_MAP_CAP__EN_MASK 0x10000
+#define D2F2_MSI_MAP_CAP__EN__SHIFT 0x10
+#define D2F2_MSI_MAP_CAP__FIXD_MASK 0x20000
+#define D2F2_MSI_MAP_CAP__FIXD__SHIFT 0x11
+#define D2F2_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
+#define D2F2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
+#define D2F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
+#define D2F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define D2F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
+#define D2F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
+#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
+#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
+#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define D2F2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
+#define D2F2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define D2F2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
+#define D2F2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define D2F2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
+#define D2F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define D2F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
+#define D2F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define D2F2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
+#define D2F2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define D2F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
+#define D2F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
+#define D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D2F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
+#define D2F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define D2F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
+#define D2F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define D2F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
+#define D2F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
+#define D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define D2F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define D2F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define D2F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define D2F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define D2F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define D2F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define D2F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define D2F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define D2F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
+#define D2F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
+#define D2F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
+#define D2F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
+#define D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define D2F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define D2F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define D2F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define D2F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define D2F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define D2F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define D2F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define D2F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define D2F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
+#define D2F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
+#define D2F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
+#define D2F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
+#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
+#define D2F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define D2F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
+#define D2F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
+#define D2F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define D2F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
+#define D2F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define D2F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
+#define D2F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define D2F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
+#define D2F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define D2F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
+#define D2F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define D2F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
+#define D2F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define D2F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
+#define D2F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define D2F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
+#define D2F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define D2F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
+#define D2F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define D2F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
+#define D2F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define D2F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
+#define D2F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define D2F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
+#define D2F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define D2F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
+#define D2F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define D2F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
+#define D2F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define D2F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
+#define D2F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define D2F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
+#define D2F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define D2F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
+#define D2F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define D2F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
+#define D2F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define D2F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
+#define D2F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define D2F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
+#define D2F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define D2F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
+#define D2F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define D2F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
+#define D2F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define D2F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
+#define D2F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define D2F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
+#define D2F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define D2F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
+#define D2F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define D2F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
+#define D2F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define D2F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
+#define D2F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define D2F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
+#define D2F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define D2F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
+#define D2F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define D2F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
+#define D2F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define D2F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
+#define D2F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define D2F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
+#define D2F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
+#define D2F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define D2F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
+#define D2F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define D2F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
+#define D2F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define D2F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
+#define D2F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define D2F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
+#define D2F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define D2F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
+#define D2F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define D2F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
+#define D2F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define D2F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
+#define D2F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define D2F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
+#define D2F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define D2F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
+#define D2F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define D2F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
+#define D2F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define D2F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
+#define D2F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define D2F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
+#define D2F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define D2F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
+#define D2F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define D2F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
+#define D2F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define D2F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
+#define D2F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define D2F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
+#define D2F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define D2F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
+#define D2F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
+#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
+#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
+#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
+#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
+#define D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
+#define D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define D2F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
+#define D2F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define D2F2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
+#define D2F2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define D2F2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
+#define D2F2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define D2F2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
+#define D2F2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define D2F2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
+#define D2F2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define D2F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
+#define D2F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define D2F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
+#define D2F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define D2F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
+#define D2F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define D2F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
+#define D2F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
+#define D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define D2F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
+#define D2F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
+#define D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define D2F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
+#define D2F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define D2F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
+#define D2F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define D2F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
+#define D2F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define D2F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
+#define D2F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define D2F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
+#define D2F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define D2F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
+#define D2F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define D2F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
+#define D2F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define D2F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
+#define D2F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define D2F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
+#define D2F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define D2F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
+#define D2F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
+#define D2F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define D2F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
+#define D2F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define D2F2_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
+#define D2F2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define D2F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
+#define D2F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define D2F2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
+#define D2F2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
+#define D2F2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define D2F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
+#define D2F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define D2F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
+#define D2F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define D2F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
+#define D2F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define D2F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
+#define D2F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define D2F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
+#define D2F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define D2F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
+#define D2F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define D2F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
+#define D2F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define D2F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
+#define D2F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
+#define D2F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
+#define D2F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
+#define D2F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
+#define D2F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
+#define D2F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
+#define D2F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
+#define D2F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
+#define D2F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
+#define D2F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
+#define D2F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
+#define D2F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
+#define D2F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
+#define D2F2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
+#define D2F2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define D2F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
+#define D2F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define D2F2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
+#define D2F2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
+#define D2F2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
+#define D2F2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
+#define D2F2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
+#define D2F2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define D2F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
+#define D2F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define D2F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
+#define D2F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define D2F2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
+#define D2F2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define D2F2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
+#define D2F2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define D2F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
+#define D2F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define D2F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
+#define D2F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define D2F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
+#define D2F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define D2F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
+#define D2F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
+#define D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
+#define D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define D2F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
+#define D2F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define D2F3_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
+#define D2F3_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
+#define D2F3_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
+#define D2F3_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
+#define D2F3_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
+#define D2F3_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define D2F3_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
+#define D2F3_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define D2F3_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define D2F3_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define D2F3_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define D2F3_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define D2F3_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define D2F3_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define D2F3_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define D2F3_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define D2F3_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define D2F3_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define D2F3_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define D2F3_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define D2F3_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define D2F3_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define D2F3_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define D2F3_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define D2F3_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define D2F3_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define D2F3_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define D2F3_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define D2F3_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define D2F3_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define D2F3_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define D2F3_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define D2F3_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define D2F3_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define D2F3_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define D2F3_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define D2F3_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define D2F3_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define D2F3_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define D2F3_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define D2F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
+#define D2F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define D2F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
+#define D2F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define D2F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
+#define D2F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define D2F3_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
+#define D2F3_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define D2F3_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
+#define D2F3_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define D2F3_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
+#define D2F3_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define D2F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
+#define D2F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
+#define D2F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
+#define D2F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define D2F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
+#define D2F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define D2F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
+#define D2F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define D2F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
+#define D2F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define D2F3_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
+#define D2F3_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define D2F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
+#define D2F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define D2F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
+#define D2F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define D2F3_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
+#define D2F3_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define D2F3_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
+#define D2F3_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define D2F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
+#define D2F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define D2F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
+#define D2F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
+#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
+#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
+#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define D2F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
+#define D2F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
+#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
+#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
+#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define D2F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
+#define D2F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define D2F3_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
+#define D2F3_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
+#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
+#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
+#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
+#define D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
+#define D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
+#define D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
+#define D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
+#define D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
+#define D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
+#define D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
+#define D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
+#define D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
+#define D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
+#define D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
+#define D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
+#define D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
+#define D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
+#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
+#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
+#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
+#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
+#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
+#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
+#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define D2F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
+#define D2F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define D2F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
+#define D2F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define D2F3_PCIE_FC_P__PD_CREDITS_MASK 0xff
+#define D2F3_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define D2F3_PCIE_FC_P__PH_CREDITS_MASK 0xff00
+#define D2F3_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
+#define D2F3_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
+#define D2F3_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define D2F3_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
+#define D2F3_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
+#define D2F3_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
+#define D2F3_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define D2F3_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
+#define D2F3_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
+#define D2F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
+#define D2F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define D2F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
+#define D2F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define D2F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
+#define D2F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define D2F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
+#define D2F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define D2F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
+#define D2F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define D2F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
+#define D2F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define D2F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
+#define D2F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
+#define D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
+#define D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define D2F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
+#define D2F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define D2F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
+#define D2F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define D2F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
+#define D2F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define D2F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
+#define D2F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define D2F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
+#define D2F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define D2F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
+#define D2F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define D2F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
+#define D2F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
+#define D2F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
+#define D2F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
+#define D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
+#define D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define D2F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
+#define D2F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
+#define D2F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define D2F3_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
+#define D2F3_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define D2F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
+#define D2F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define D2F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
+#define D2F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
+#define D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
+#define D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
+#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
+#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
+#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
+#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
+#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
+#define D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
+#define D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
+#define D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
+#define D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
+#define D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
+#define D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
+#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
+#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
+#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
+#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
+#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
+#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
+#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
+#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
+#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
+#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
+#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define D2F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
+#define D2F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define D2F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
+#define D2F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define D2F3_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
+#define D2F3_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define D2F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
+#define D2F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define D2F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
+#define D2F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define D2F3_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
+#define D2F3_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define D2F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
+#define D2F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define D2F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
+#define D2F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define D2F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
+#define D2F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define D2F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
+#define D2F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define D2F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
+#define D2F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define D2F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
+#define D2F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define D2F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
+#define D2F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define D2F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
+#define D2F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define D2F3_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
+#define D2F3_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define D2F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
+#define D2F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define D2F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
+#define D2F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define D2F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
+#define D2F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define D2F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
+#define D2F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define D2F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
+#define D2F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define D2F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
+#define D2F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define D2F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
+#define D2F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define D2F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
+#define D2F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define D2F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
+#define D2F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define D2F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
+#define D2F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define D2F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
+#define D2F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
+#define D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
+#define D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
+#define D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define D2F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
+#define D2F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define D2F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
+#define D2F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
+#define D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
+#define D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define D2F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
+#define D2F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
+#define D2F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
+#define D2F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define D2F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
+#define D2F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define D2F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
+#define D2F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
+#define D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define D2F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
+#define D2F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define D2F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
+#define D2F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define D2F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
+#define D2F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define D2F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
+#define D2F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define D2F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
+#define D2F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define D2F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
+#define D2F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
+#define D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
+#define D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define D2F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
+#define D2F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define D2F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
+#define D2F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define D2F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
+#define D2F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
+#define D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
+#define D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define D2F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
+#define D2F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define D2F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
+#define D2F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define D2F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
+#define D2F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define D2F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
+#define D2F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
+#define D2F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
+#define D2F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
+#define D2F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
+#define D2F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
+#define D2F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
+#define D2F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
+#define D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
+#define D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define D2F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
+#define D2F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define D2F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
+#define D2F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
+#define D2F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
+#define D2F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define D2F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
+#define D2F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define D2F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
+#define D2F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define D2F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
+#define D2F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define D2F3_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
+#define D2F3_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
+#define D2F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
+#define D2F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define D2F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
+#define D2F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define D2F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
+#define D2F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
+#define D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
+#define D2F3_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
+#define D2F3_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
+#define D2F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
+#define D2F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define D2F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
+#define D2F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define D2F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
+#define D2F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
+#define D2F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
+#define D2F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define D2F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
+#define D2F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
+#define D2F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
+#define D2F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
+#define D2F3_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
+#define D2F3_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define D2F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
+#define D2F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define D2F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
+#define D2F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
+#define D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
+#define D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
+#define D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
+#define D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
+#define D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
+#define D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
+#define D2F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
+#define D2F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define D2F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
+#define D2F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
+#define D2F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
+#define D2F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define D2F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
+#define D2F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define D2F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
+#define D2F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define D2F3_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
+#define D2F3_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
+#define D2F3_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
+#define D2F3_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
+#define D2F3_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
+#define D2F3_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
+#define D2F3_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
+#define D2F3_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
+#define D2F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
+#define D2F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
+#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
+#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
+#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
+#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
+#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
+#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
+#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
+#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
+#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
+#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
+#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
+#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
+#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
+#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
+#define D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
+#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
+#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
+#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
+#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
+#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define D2F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
+#define D2F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
+#define D2F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
+#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
+#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
+#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
+#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define D2F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
+#define D2F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define D2F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
+#define D2F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
+#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
+#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
+#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
+#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
+#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
+#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
+#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
+#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
+#define D2F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
+#define D2F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
+#define D2F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
+#define D2F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
+#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
+#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
+#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
+#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
+#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
+#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
+#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
+#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
+#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
+#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
+#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
+#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
+#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
+#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
+#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
+#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
+#define D2F3_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
+#define D2F3_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
+#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
+#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
+#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
+#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
+#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
+#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
+#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
+#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
+#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
+#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
+#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
+#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
+#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
+#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
+#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
+#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
+#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
+#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
+#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
+#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
+#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
+#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
+#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define D2F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
+#define D2F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define D2F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
+#define D2F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define D2F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
+#define D2F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define D2F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
+#define D2F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define D2F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
+#define D2F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define D2F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
+#define D2F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define D2F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
+#define D2F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define D2F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
+#define D2F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define D2F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
+#define D2F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define D2F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
+#define D2F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define D2F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
+#define D2F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define D2F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
+#define D2F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define D2F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
+#define D2F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define D2F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
+#define D2F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define D2F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
+#define D2F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define D2F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
+#define D2F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define D2F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
+#define D2F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
+#define D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
+#define D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
+#define D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
+#define D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
+#define D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
+#define D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
+#define D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
+#define D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define D2F3_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
+#define D2F3_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
+#define D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
+#define D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
+#define D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
+#define D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define D2F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
+#define D2F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define D2F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
+#define D2F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define D2F3_VENDOR_ID__VENDOR_ID_MASK 0xffff
+#define D2F3_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define D2F3_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
+#define D2F3_DEVICE_ID__DEVICE_ID__SHIFT 0x10
+#define D2F3_COMMAND__IO_ACCESS_EN_MASK 0x1
+#define D2F3_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define D2F3_COMMAND__MEM_ACCESS_EN_MASK 0x2
+#define D2F3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define D2F3_COMMAND__BUS_MASTER_EN_MASK 0x4
+#define D2F3_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define D2F3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
+#define D2F3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define D2F3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
+#define D2F3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define D2F3_COMMAND__PAL_SNOOP_EN_MASK 0x20
+#define D2F3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define D2F3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
+#define D2F3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define D2F3_COMMAND__AD_STEPPING_MASK 0x80
+#define D2F3_COMMAND__AD_STEPPING__SHIFT 0x7
+#define D2F3_COMMAND__SERR_EN_MASK 0x100
+#define D2F3_COMMAND__SERR_EN__SHIFT 0x8
+#define D2F3_COMMAND__FAST_B2B_EN_MASK 0x200
+#define D2F3_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define D2F3_COMMAND__INT_DIS_MASK 0x400
+#define D2F3_COMMAND__INT_DIS__SHIFT 0xa
+#define D2F3_STATUS__INT_STATUS_MASK 0x80000
+#define D2F3_STATUS__INT_STATUS__SHIFT 0x13
+#define D2F3_STATUS__CAP_LIST_MASK 0x100000
+#define D2F3_STATUS__CAP_LIST__SHIFT 0x14
+#define D2F3_STATUS__PCI_66_EN_MASK 0x200000
+#define D2F3_STATUS__PCI_66_EN__SHIFT 0x15
+#define D2F3_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
+#define D2F3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
+#define D2F3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
+#define D2F3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
+#define D2F3_STATUS__DEVSEL_TIMING_MASK 0x6000000
+#define D2F3_STATUS__DEVSEL_TIMING__SHIFT 0x19
+#define D2F3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
+#define D2F3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
+#define D2F3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
+#define D2F3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
+#define D2F3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
+#define D2F3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
+#define D2F3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
+#define D2F3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
+#define D2F3_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
+#define D2F3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
+#define D2F3_REVISION_ID__MINOR_REV_ID_MASK 0xf
+#define D2F3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define D2F3_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
+#define D2F3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define D2F3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
+#define D2F3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
+#define D2F3_SUB_CLASS__SUB_CLASS_MASK 0xff0000
+#define D2F3_SUB_CLASS__SUB_CLASS__SHIFT 0x10
+#define D2F3_BASE_CLASS__BASE_CLASS_MASK 0xff000000
+#define D2F3_BASE_CLASS__BASE_CLASS__SHIFT 0x18
+#define D2F3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
+#define D2F3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define D2F3_LATENCY__LATENCY_TIMER_MASK 0xff00
+#define D2F3_LATENCY__LATENCY_TIMER__SHIFT 0x8
+#define D2F3_HEADER__HEADER_TYPE_MASK 0x7f0000
+#define D2F3_HEADER__HEADER_TYPE__SHIFT 0x10
+#define D2F3_HEADER__DEVICE_TYPE_MASK 0x800000
+#define D2F3_HEADER__DEVICE_TYPE__SHIFT 0x17
+#define D2F3_BIST__BIST_COMP_MASK 0xf000000
+#define D2F3_BIST__BIST_COMP__SHIFT 0x18
+#define D2F3_BIST__BIST_STRT_MASK 0x40000000
+#define D2F3_BIST__BIST_STRT__SHIFT 0x1e
+#define D2F3_BIST__BIST_CAP_MASK 0x80000000
+#define D2F3_BIST__BIST_CAP__SHIFT 0x1f
+#define D2F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
+#define D2F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
+#define D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define D2F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
+#define D2F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
+#define D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define D2F3_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
+#define D2F3_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define D2F3_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
+#define D2F3_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define D2F3_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
+#define D2F3_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define D2F3_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
+#define D2F3_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define D2F3_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
+#define D2F3_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
+#define D2F3_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
+#define D2F3_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
+#define D2F3_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
+#define D2F3_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
+#define D2F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
+#define D2F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
+#define D2F3_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
+#define D2F3_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
+#define D2F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
+#define D2F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
+#define D2F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
+#define D2F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
+#define D2F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
+#define D2F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
+#define D2F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
+#define D2F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
+#define D2F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
+#define D2F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
+#define D2F3_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
+#define D2F3_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define D2F3_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
+#define D2F3_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define D2F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
+#define D2F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define D2F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
+#define D2F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
+#define D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
+#define D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
+#define D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
+#define D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define D2F3_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
+#define D2F3_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define D2F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
+#define D2F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define D2F3_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
+#define D2F3_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define D2F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
+#define D2F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define D2F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
+#define D2F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
+#define D2F3_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
+#define D2F3_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
+#define D2F3_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
+#define D2F3_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
+#define D2F3_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
+#define D2F3_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
+#define D2F3_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
+#define D2F3_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
+#define D2F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
+#define D2F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
+#define D2F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
+#define D2F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
+#define D2F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
+#define D2F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
+#define D2F3_CAP_PTR__CAP_PTR_MASK 0xff
+#define D2F3_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define D2F3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
+#define D2F3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define D2F3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
+#define D2F3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
+#define D2F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
+#define D2F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define D2F3_PMI_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F3_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F3_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F3_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F3_PMI_CAP__VERSION_MASK 0x70000
+#define D2F3_PMI_CAP__VERSION__SHIFT 0x10
+#define D2F3_PMI_CAP__PME_CLOCK_MASK 0x80000
+#define D2F3_PMI_CAP__PME_CLOCK__SHIFT 0x13
+#define D2F3_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
+#define D2F3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
+#define D2F3_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
+#define D2F3_PMI_CAP__AUX_CURRENT__SHIFT 0x16
+#define D2F3_PMI_CAP__D1_SUPPORT_MASK 0x2000000
+#define D2F3_PMI_CAP__D1_SUPPORT__SHIFT 0x19
+#define D2F3_PMI_CAP__D2_SUPPORT_MASK 0x4000000
+#define D2F3_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
+#define D2F3_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
+#define D2F3_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
+#define D2F3_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
+#define D2F3_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define D2F3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
+#define D2F3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define D2F3_PMI_STATUS_CNTL__PME_EN_MASK 0x100
+#define D2F3_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define D2F3_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
+#define D2F3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define D2F3_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
+#define D2F3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define D2F3_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
+#define D2F3_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define D2F3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
+#define D2F3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define D2F3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
+#define D2F3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define D2F3_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
+#define D2F3_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define D2F3_PCIE_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F3_PCIE_CAP__VERSION_MASK 0xf0000
+#define D2F3_PCIE_CAP__VERSION__SHIFT 0x10
+#define D2F3_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
+#define D2F3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
+#define D2F3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
+#define D2F3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
+#define D2F3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
+#define D2F3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
+#define D2F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
+#define D2F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define D2F3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
+#define D2F3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define D2F3_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
+#define D2F3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define D2F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
+#define D2F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define D2F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
+#define D2F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define D2F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
+#define D2F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
+#define D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
+#define D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define D2F3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
+#define D2F3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define D2F3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
+#define D2F3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define D2F3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
+#define D2F3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define D2F3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
+#define D2F3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define D2F3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
+#define D2F3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define D2F3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
+#define D2F3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define D2F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
+#define D2F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define D2F3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
+#define D2F3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define D2F3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
+#define D2F3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define D2F3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
+#define D2F3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define D2F3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
+#define D2F3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define D2F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
+#define D2F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define D2F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
+#define D2F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define D2F3_DEVICE_STATUS__CORR_ERR_MASK 0x10000
+#define D2F3_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
+#define D2F3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
+#define D2F3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
+#define D2F3_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
+#define D2F3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
+#define D2F3_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
+#define D2F3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
+#define D2F3_DEVICE_STATUS__AUX_PWR_MASK 0x100000
+#define D2F3_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
+#define D2F3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
+#define D2F3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
+#define D2F3_LINK_CAP__LINK_SPEED_MASK 0xf
+#define D2F3_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define D2F3_LINK_CAP__LINK_WIDTH_MASK 0x3f0
+#define D2F3_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define D2F3_LINK_CAP__PM_SUPPORT_MASK 0xc00
+#define D2F3_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define D2F3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
+#define D2F3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define D2F3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
+#define D2F3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define D2F3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
+#define D2F3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define D2F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
+#define D2F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define D2F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
+#define D2F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define D2F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
+#define D2F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define D2F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
+#define D2F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define D2F3_LINK_CAP__PORT_NUMBER_MASK 0xff000000
+#define D2F3_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define D2F3_LINK_CNTL__PM_CONTROL_MASK 0x3
+#define D2F3_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define D2F3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
+#define D2F3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define D2F3_LINK_CNTL__LINK_DIS_MASK 0x10
+#define D2F3_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define D2F3_LINK_CNTL__RETRAIN_LINK_MASK 0x20
+#define D2F3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define D2F3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
+#define D2F3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define D2F3_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
+#define D2F3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define D2F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
+#define D2F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define D2F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
+#define D2F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define D2F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
+#define D2F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define D2F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
+#define D2F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define D2F3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
+#define D2F3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
+#define D2F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
+#define D2F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
+#define D2F3_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
+#define D2F3_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
+#define D2F3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
+#define D2F3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
+#define D2F3_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
+#define D2F3_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
+#define D2F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
+#define D2F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
+#define D2F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
+#define D2F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
+#define D2F3_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
+#define D2F3_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define D2F3_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
+#define D2F3_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define D2F3_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
+#define D2F3_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define D2F3_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
+#define D2F3_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define D2F3_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
+#define D2F3_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define D2F3_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
+#define D2F3_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define D2F3_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
+#define D2F3_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define D2F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
+#define D2F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define D2F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
+#define D2F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define D2F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
+#define D2F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define D2F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
+#define D2F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define D2F3_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
+#define D2F3_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define D2F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
+#define D2F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define D2F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
+#define D2F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define D2F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
+#define D2F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define D2F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
+#define D2F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define D2F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
+#define D2F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define D2F3_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
+#define D2F3_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define D2F3_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
+#define D2F3_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define D2F3_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
+#define D2F3_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define D2F3_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
+#define D2F3_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define D2F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
+#define D2F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define D2F3_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
+#define D2F3_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define D2F3_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
+#define D2F3_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
+#define D2F3_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
+#define D2F3_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
+#define D2F3_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
+#define D2F3_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
+#define D2F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
+#define D2F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
+#define D2F3_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
+#define D2F3_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
+#define D2F3_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
+#define D2F3_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
+#define D2F3_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
+#define D2F3_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
+#define D2F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
+#define D2F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
+#define D2F3_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
+#define D2F3_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
+#define D2F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
+#define D2F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define D2F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
+#define D2F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define D2F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
+#define D2F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define D2F3_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
+#define D2F3_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define D2F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
+#define D2F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define D2F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
+#define D2F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
+#define D2F3_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
+#define D2F3_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define D2F3_ROOT_STATUS__PME_STATUS_MASK 0x10000
+#define D2F3_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define D2F3_ROOT_STATUS__PME_PENDING_MASK 0x20000
+#define D2F3_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define D2F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
+#define D2F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define D2F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
+#define D2F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define D2F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
+#define D2F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define D2F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
+#define D2F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define D2F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
+#define D2F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define D2F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
+#define D2F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define D2F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
+#define D2F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define D2F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
+#define D2F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define D2F3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
+#define D2F3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define D2F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
+#define D2F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define D2F3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
+#define D2F3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define D2F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
+#define D2F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define D2F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
+#define D2F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define D2F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
+#define D2F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define D2F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
+#define D2F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define D2F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
+#define D2F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define D2F3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
+#define D2F3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define D2F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
+#define D2F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define D2F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
+#define D2F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define D2F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
+#define D2F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define D2F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
+#define D2F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define D2F3_DEVICE_CNTL2__LTR_EN_MASK 0x400
+#define D2F3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define D2F3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
+#define D2F3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define D2F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
+#define D2F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define D2F3_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
+#define D2F3_DEVICE_STATUS2__RESERVED__SHIFT 0x10
+#define D2F3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
+#define D2F3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define D2F3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
+#define D2F3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define D2F3_LINK_CAP2__RESERVED_MASK 0xfffffe00
+#define D2F3_LINK_CAP2__RESERVED__SHIFT 0x9
+#define D2F3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
+#define D2F3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define D2F3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
+#define D2F3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define D2F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
+#define D2F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define D2F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
+#define D2F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define D2F3_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
+#define D2F3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define D2F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
+#define D2F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define D2F3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
+#define D2F3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define D2F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
+#define D2F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define D2F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
+#define D2F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
+#define D2F3_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
+#define D2F3_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
+#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
+#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
+#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
+#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
+#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
+#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
+#define D2F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
+#define D2F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
+#define D2F3_SLOT_CAP2__RESERVED_MASK 0xffffffff
+#define D2F3_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define D2F3_SLOT_CNTL2__RESERVED_MASK 0xffff
+#define D2F3_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define D2F3_SLOT_STATUS2__RESERVED_MASK 0xffff0000
+#define D2F3_SLOT_STATUS2__RESERVED__SHIFT 0x10
+#define D2F3_MSI_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F3_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F3_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
+#define D2F3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
+#define D2F3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
+#define D2F3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
+#define D2F3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
+#define D2F3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
+#define D2F3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
+#define D2F3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
+#define D2F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
+#define D2F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
+#define D2F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
+#define D2F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define D2F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
+#define D2F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define D2F3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
+#define D2F3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define D2F3_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
+#define D2F3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define D2F3_SSID_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F3_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F3_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F3_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F3_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
+#define D2F3_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define D2F3_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
+#define D2F3_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define D2F3_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F3_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F3_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F3_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F3_MSI_MAP_CAP__EN_MASK 0x10000
+#define D2F3_MSI_MAP_CAP__EN__SHIFT 0x10
+#define D2F3_MSI_MAP_CAP__FIXD_MASK 0x20000
+#define D2F3_MSI_MAP_CAP__FIXD__SHIFT 0x11
+#define D2F3_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
+#define D2F3_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
+#define D2F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
+#define D2F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define D2F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
+#define D2F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
+#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
+#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
+#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define D2F3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
+#define D2F3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define D2F3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
+#define D2F3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define D2F3_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F3_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F3_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F3_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
+#define D2F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define D2F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
+#define D2F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define D2F3_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
+#define D2F3_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define D2F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
+#define D2F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
+#define D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D2F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
+#define D2F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define D2F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
+#define D2F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define D2F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
+#define D2F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
+#define D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define D2F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define D2F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define D2F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define D2F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define D2F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define D2F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define D2F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define D2F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define D2F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
+#define D2F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
+#define D2F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
+#define D2F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
+#define D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define D2F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define D2F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define D2F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define D2F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define D2F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define D2F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define D2F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define D2F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define D2F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
+#define D2F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
+#define D2F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
+#define D2F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
+#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
+#define D2F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define D2F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
+#define D2F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
+#define D2F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define D2F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
+#define D2F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define D2F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
+#define D2F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define D2F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
+#define D2F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define D2F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
+#define D2F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define D2F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
+#define D2F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define D2F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
+#define D2F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define D2F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
+#define D2F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define D2F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
+#define D2F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define D2F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
+#define D2F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define D2F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
+#define D2F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define D2F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
+#define D2F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define D2F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
+#define D2F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define D2F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
+#define D2F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define D2F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
+#define D2F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define D2F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
+#define D2F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define D2F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
+#define D2F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define D2F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
+#define D2F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define D2F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
+#define D2F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define D2F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
+#define D2F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define D2F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
+#define D2F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define D2F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
+#define D2F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define D2F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
+#define D2F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define D2F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
+#define D2F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define D2F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
+#define D2F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define D2F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
+#define D2F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define D2F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
+#define D2F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define D2F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
+#define D2F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define D2F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
+#define D2F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define D2F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
+#define D2F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define D2F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
+#define D2F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define D2F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
+#define D2F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
+#define D2F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define D2F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
+#define D2F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define D2F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
+#define D2F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define D2F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
+#define D2F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define D2F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
+#define D2F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define D2F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
+#define D2F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define D2F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
+#define D2F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define D2F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
+#define D2F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define D2F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
+#define D2F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define D2F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
+#define D2F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define D2F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
+#define D2F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define D2F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
+#define D2F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define D2F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
+#define D2F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define D2F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
+#define D2F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define D2F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
+#define D2F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define D2F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
+#define D2F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define D2F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
+#define D2F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define D2F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
+#define D2F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
+#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
+#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
+#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
+#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
+#define D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
+#define D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define D2F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
+#define D2F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define D2F3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
+#define D2F3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define D2F3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
+#define D2F3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define D2F3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
+#define D2F3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define D2F3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
+#define D2F3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define D2F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
+#define D2F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define D2F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
+#define D2F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define D2F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
+#define D2F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define D2F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
+#define D2F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
+#define D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define D2F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
+#define D2F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
+#define D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define D2F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
+#define D2F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define D2F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
+#define D2F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define D2F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
+#define D2F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define D2F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
+#define D2F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define D2F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
+#define D2F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define D2F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
+#define D2F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define D2F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
+#define D2F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define D2F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
+#define D2F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define D2F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
+#define D2F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define D2F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
+#define D2F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
+#define D2F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define D2F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
+#define D2F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define D2F3_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
+#define D2F3_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define D2F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
+#define D2F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define D2F3_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
+#define D2F3_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
+#define D2F3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define D2F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
+#define D2F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define D2F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
+#define D2F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define D2F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
+#define D2F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define D2F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
+#define D2F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define D2F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
+#define D2F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define D2F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
+#define D2F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define D2F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
+#define D2F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define D2F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
+#define D2F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
+#define D2F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
+#define D2F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
+#define D2F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
+#define D2F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
+#define D2F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
+#define D2F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
+#define D2F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
+#define D2F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
+#define D2F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
+#define D2F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
+#define D2F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
+#define D2F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
+#define D2F3_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F3_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F3_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F3_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F3_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
+#define D2F3_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define D2F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
+#define D2F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define D2F3_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
+#define D2F3_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
+#define D2F3_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
+#define D2F3_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
+#define D2F3_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
+#define D2F3_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define D2F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
+#define D2F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define D2F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
+#define D2F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define D2F3_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
+#define D2F3_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define D2F3_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
+#define D2F3_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define D2F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
+#define D2F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define D2F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
+#define D2F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define D2F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
+#define D2F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define D2F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
+#define D2F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
+#define D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
+#define D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define D2F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
+#define D2F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define D2F4_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
+#define D2F4_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
+#define D2F4_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
+#define D2F4_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
+#define D2F4_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
+#define D2F4_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define D2F4_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
+#define D2F4_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define D2F4_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define D2F4_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define D2F4_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define D2F4_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define D2F4_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define D2F4_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define D2F4_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define D2F4_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define D2F4_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define D2F4_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define D2F4_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define D2F4_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define D2F4_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define D2F4_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define D2F4_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define D2F4_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define D2F4_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define D2F4_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define D2F4_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define D2F4_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define D2F4_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define D2F4_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define D2F4_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define D2F4_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define D2F4_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define D2F4_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define D2F4_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define D2F4_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define D2F4_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define D2F4_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define D2F4_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define D2F4_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define D2F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
+#define D2F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define D2F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
+#define D2F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define D2F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
+#define D2F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define D2F4_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
+#define D2F4_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define D2F4_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
+#define D2F4_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define D2F4_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
+#define D2F4_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define D2F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
+#define D2F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
+#define D2F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
+#define D2F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define D2F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
+#define D2F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define D2F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
+#define D2F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define D2F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
+#define D2F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define D2F4_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
+#define D2F4_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define D2F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
+#define D2F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define D2F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
+#define D2F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define D2F4_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
+#define D2F4_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define D2F4_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
+#define D2F4_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define D2F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
+#define D2F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define D2F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
+#define D2F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
+#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
+#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
+#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define D2F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
+#define D2F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
+#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
+#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
+#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define D2F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
+#define D2F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define D2F4_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
+#define D2F4_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
+#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
+#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
+#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
+#define D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
+#define D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
+#define D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
+#define D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
+#define D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
+#define D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
+#define D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
+#define D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
+#define D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
+#define D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
+#define D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
+#define D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
+#define D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
+#define D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
+#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
+#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
+#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
+#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
+#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
+#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
+#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define D2F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
+#define D2F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define D2F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
+#define D2F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define D2F4_PCIE_FC_P__PD_CREDITS_MASK 0xff
+#define D2F4_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define D2F4_PCIE_FC_P__PH_CREDITS_MASK 0xff00
+#define D2F4_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
+#define D2F4_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
+#define D2F4_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define D2F4_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
+#define D2F4_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
+#define D2F4_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
+#define D2F4_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define D2F4_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
+#define D2F4_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
+#define D2F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
+#define D2F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define D2F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
+#define D2F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define D2F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
+#define D2F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define D2F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
+#define D2F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define D2F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
+#define D2F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define D2F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
+#define D2F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define D2F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
+#define D2F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
+#define D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
+#define D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define D2F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
+#define D2F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define D2F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
+#define D2F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define D2F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
+#define D2F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define D2F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
+#define D2F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define D2F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
+#define D2F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define D2F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
+#define D2F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define D2F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
+#define D2F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
+#define D2F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
+#define D2F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
+#define D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
+#define D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define D2F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
+#define D2F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
+#define D2F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define D2F4_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
+#define D2F4_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define D2F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
+#define D2F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define D2F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
+#define D2F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
+#define D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
+#define D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
+#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
+#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
+#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
+#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
+#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
+#define D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
+#define D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
+#define D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
+#define D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
+#define D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
+#define D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
+#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
+#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
+#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
+#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
+#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
+#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
+#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
+#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
+#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
+#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
+#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define D2F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
+#define D2F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define D2F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
+#define D2F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define D2F4_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
+#define D2F4_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define D2F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
+#define D2F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define D2F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
+#define D2F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define D2F4_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
+#define D2F4_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define D2F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
+#define D2F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define D2F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
+#define D2F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define D2F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
+#define D2F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define D2F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
+#define D2F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define D2F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
+#define D2F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define D2F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
+#define D2F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define D2F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
+#define D2F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define D2F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
+#define D2F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define D2F4_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
+#define D2F4_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define D2F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
+#define D2F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define D2F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
+#define D2F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define D2F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
+#define D2F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define D2F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
+#define D2F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define D2F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
+#define D2F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define D2F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
+#define D2F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define D2F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
+#define D2F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define D2F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
+#define D2F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define D2F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
+#define D2F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define D2F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
+#define D2F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define D2F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
+#define D2F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
+#define D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
+#define D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
+#define D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define D2F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
+#define D2F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define D2F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
+#define D2F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
+#define D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
+#define D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define D2F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
+#define D2F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
+#define D2F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
+#define D2F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define D2F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
+#define D2F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define D2F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
+#define D2F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
+#define D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define D2F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
+#define D2F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define D2F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
+#define D2F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define D2F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
+#define D2F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define D2F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
+#define D2F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define D2F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
+#define D2F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define D2F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
+#define D2F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
+#define D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
+#define D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define D2F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
+#define D2F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define D2F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
+#define D2F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define D2F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
+#define D2F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
+#define D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
+#define D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define D2F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
+#define D2F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define D2F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
+#define D2F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define D2F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
+#define D2F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define D2F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
+#define D2F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
+#define D2F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
+#define D2F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
+#define D2F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
+#define D2F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
+#define D2F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
+#define D2F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
+#define D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
+#define D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define D2F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
+#define D2F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define D2F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
+#define D2F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
+#define D2F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
+#define D2F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define D2F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
+#define D2F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define D2F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
+#define D2F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define D2F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
+#define D2F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define D2F4_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
+#define D2F4_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
+#define D2F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
+#define D2F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define D2F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
+#define D2F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define D2F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
+#define D2F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
+#define D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
+#define D2F4_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
+#define D2F4_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
+#define D2F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
+#define D2F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define D2F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
+#define D2F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define D2F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
+#define D2F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
+#define D2F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
+#define D2F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define D2F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
+#define D2F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
+#define D2F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
+#define D2F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
+#define D2F4_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
+#define D2F4_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define D2F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
+#define D2F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define D2F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
+#define D2F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
+#define D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
+#define D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
+#define D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
+#define D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
+#define D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
+#define D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
+#define D2F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
+#define D2F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define D2F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
+#define D2F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
+#define D2F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
+#define D2F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define D2F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
+#define D2F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define D2F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
+#define D2F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define D2F4_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
+#define D2F4_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
+#define D2F4_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
+#define D2F4_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
+#define D2F4_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
+#define D2F4_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
+#define D2F4_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
+#define D2F4_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
+#define D2F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
+#define D2F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
+#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
+#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
+#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
+#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
+#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
+#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
+#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
+#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
+#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
+#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
+#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
+#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
+#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
+#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
+#define D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
+#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
+#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
+#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
+#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
+#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define D2F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
+#define D2F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
+#define D2F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
+#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
+#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
+#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
+#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define D2F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
+#define D2F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define D2F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
+#define D2F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
+#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
+#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
+#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
+#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
+#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
+#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
+#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
+#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
+#define D2F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
+#define D2F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
+#define D2F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
+#define D2F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
+#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
+#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
+#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
+#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
+#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
+#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
+#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
+#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
+#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
+#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
+#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
+#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
+#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
+#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
+#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
+#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
+#define D2F4_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
+#define D2F4_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
+#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
+#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
+#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
+#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
+#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
+#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
+#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
+#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
+#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
+#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
+#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
+#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
+#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
+#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
+#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
+#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
+#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
+#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
+#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
+#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
+#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
+#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
+#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define D2F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
+#define D2F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define D2F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
+#define D2F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define D2F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
+#define D2F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define D2F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
+#define D2F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define D2F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
+#define D2F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define D2F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
+#define D2F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define D2F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
+#define D2F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define D2F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
+#define D2F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define D2F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
+#define D2F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define D2F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
+#define D2F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define D2F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
+#define D2F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define D2F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
+#define D2F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define D2F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
+#define D2F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define D2F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
+#define D2F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define D2F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
+#define D2F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define D2F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
+#define D2F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define D2F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
+#define D2F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
+#define D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
+#define D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
+#define D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
+#define D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
+#define D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
+#define D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
+#define D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
+#define D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define D2F4_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
+#define D2F4_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
+#define D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
+#define D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
+#define D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
+#define D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define D2F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
+#define D2F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define D2F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
+#define D2F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define D2F4_VENDOR_ID__VENDOR_ID_MASK 0xffff
+#define D2F4_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define D2F4_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
+#define D2F4_DEVICE_ID__DEVICE_ID__SHIFT 0x10
+#define D2F4_COMMAND__IO_ACCESS_EN_MASK 0x1
+#define D2F4_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define D2F4_COMMAND__MEM_ACCESS_EN_MASK 0x2
+#define D2F4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define D2F4_COMMAND__BUS_MASTER_EN_MASK 0x4
+#define D2F4_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define D2F4_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
+#define D2F4_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define D2F4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
+#define D2F4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define D2F4_COMMAND__PAL_SNOOP_EN_MASK 0x20
+#define D2F4_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define D2F4_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
+#define D2F4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define D2F4_COMMAND__AD_STEPPING_MASK 0x80
+#define D2F4_COMMAND__AD_STEPPING__SHIFT 0x7
+#define D2F4_COMMAND__SERR_EN_MASK 0x100
+#define D2F4_COMMAND__SERR_EN__SHIFT 0x8
+#define D2F4_COMMAND__FAST_B2B_EN_MASK 0x200
+#define D2F4_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define D2F4_COMMAND__INT_DIS_MASK 0x400
+#define D2F4_COMMAND__INT_DIS__SHIFT 0xa
+#define D2F4_STATUS__INT_STATUS_MASK 0x80000
+#define D2F4_STATUS__INT_STATUS__SHIFT 0x13
+#define D2F4_STATUS__CAP_LIST_MASK 0x100000
+#define D2F4_STATUS__CAP_LIST__SHIFT 0x14
+#define D2F4_STATUS__PCI_66_EN_MASK 0x200000
+#define D2F4_STATUS__PCI_66_EN__SHIFT 0x15
+#define D2F4_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
+#define D2F4_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
+#define D2F4_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
+#define D2F4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
+#define D2F4_STATUS__DEVSEL_TIMING_MASK 0x6000000
+#define D2F4_STATUS__DEVSEL_TIMING__SHIFT 0x19
+#define D2F4_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
+#define D2F4_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
+#define D2F4_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
+#define D2F4_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
+#define D2F4_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
+#define D2F4_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
+#define D2F4_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
+#define D2F4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
+#define D2F4_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
+#define D2F4_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
+#define D2F4_REVISION_ID__MINOR_REV_ID_MASK 0xf
+#define D2F4_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define D2F4_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
+#define D2F4_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define D2F4_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
+#define D2F4_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
+#define D2F4_SUB_CLASS__SUB_CLASS_MASK 0xff0000
+#define D2F4_SUB_CLASS__SUB_CLASS__SHIFT 0x10
+#define D2F4_BASE_CLASS__BASE_CLASS_MASK 0xff000000
+#define D2F4_BASE_CLASS__BASE_CLASS__SHIFT 0x18
+#define D2F4_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
+#define D2F4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define D2F4_LATENCY__LATENCY_TIMER_MASK 0xff00
+#define D2F4_LATENCY__LATENCY_TIMER__SHIFT 0x8
+#define D2F4_HEADER__HEADER_TYPE_MASK 0x7f0000
+#define D2F4_HEADER__HEADER_TYPE__SHIFT 0x10
+#define D2F4_HEADER__DEVICE_TYPE_MASK 0x800000
+#define D2F4_HEADER__DEVICE_TYPE__SHIFT 0x17
+#define D2F4_BIST__BIST_COMP_MASK 0xf000000
+#define D2F4_BIST__BIST_COMP__SHIFT 0x18
+#define D2F4_BIST__BIST_STRT_MASK 0x40000000
+#define D2F4_BIST__BIST_STRT__SHIFT 0x1e
+#define D2F4_BIST__BIST_CAP_MASK 0x80000000
+#define D2F4_BIST__BIST_CAP__SHIFT 0x1f
+#define D2F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
+#define D2F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
+#define D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define D2F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
+#define D2F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
+#define D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define D2F4_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
+#define D2F4_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define D2F4_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
+#define D2F4_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define D2F4_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
+#define D2F4_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define D2F4_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
+#define D2F4_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define D2F4_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
+#define D2F4_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
+#define D2F4_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
+#define D2F4_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
+#define D2F4_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
+#define D2F4_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
+#define D2F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
+#define D2F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
+#define D2F4_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
+#define D2F4_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
+#define D2F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
+#define D2F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
+#define D2F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
+#define D2F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
+#define D2F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
+#define D2F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
+#define D2F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
+#define D2F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
+#define D2F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
+#define D2F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
+#define D2F4_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
+#define D2F4_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define D2F4_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
+#define D2F4_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define D2F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
+#define D2F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define D2F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
+#define D2F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
+#define D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
+#define D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
+#define D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
+#define D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define D2F4_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
+#define D2F4_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define D2F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
+#define D2F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define D2F4_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
+#define D2F4_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define D2F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
+#define D2F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define D2F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
+#define D2F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
+#define D2F4_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
+#define D2F4_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
+#define D2F4_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
+#define D2F4_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
+#define D2F4_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
+#define D2F4_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
+#define D2F4_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
+#define D2F4_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
+#define D2F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
+#define D2F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
+#define D2F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
+#define D2F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
+#define D2F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
+#define D2F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
+#define D2F4_CAP_PTR__CAP_PTR_MASK 0xff
+#define D2F4_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define D2F4_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
+#define D2F4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define D2F4_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
+#define D2F4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
+#define D2F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
+#define D2F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define D2F4_PMI_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F4_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F4_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F4_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F4_PMI_CAP__VERSION_MASK 0x70000
+#define D2F4_PMI_CAP__VERSION__SHIFT 0x10
+#define D2F4_PMI_CAP__PME_CLOCK_MASK 0x80000
+#define D2F4_PMI_CAP__PME_CLOCK__SHIFT 0x13
+#define D2F4_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
+#define D2F4_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
+#define D2F4_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
+#define D2F4_PMI_CAP__AUX_CURRENT__SHIFT 0x16
+#define D2F4_PMI_CAP__D1_SUPPORT_MASK 0x2000000
+#define D2F4_PMI_CAP__D1_SUPPORT__SHIFT 0x19
+#define D2F4_PMI_CAP__D2_SUPPORT_MASK 0x4000000
+#define D2F4_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
+#define D2F4_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
+#define D2F4_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
+#define D2F4_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
+#define D2F4_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define D2F4_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
+#define D2F4_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define D2F4_PMI_STATUS_CNTL__PME_EN_MASK 0x100
+#define D2F4_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define D2F4_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
+#define D2F4_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define D2F4_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
+#define D2F4_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define D2F4_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
+#define D2F4_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define D2F4_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
+#define D2F4_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define D2F4_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
+#define D2F4_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define D2F4_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
+#define D2F4_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define D2F4_PCIE_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F4_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F4_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F4_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F4_PCIE_CAP__VERSION_MASK 0xf0000
+#define D2F4_PCIE_CAP__VERSION__SHIFT 0x10
+#define D2F4_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
+#define D2F4_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
+#define D2F4_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
+#define D2F4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
+#define D2F4_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
+#define D2F4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
+#define D2F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
+#define D2F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define D2F4_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
+#define D2F4_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define D2F4_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
+#define D2F4_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define D2F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
+#define D2F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define D2F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
+#define D2F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define D2F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
+#define D2F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
+#define D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
+#define D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define D2F4_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
+#define D2F4_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define D2F4_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
+#define D2F4_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define D2F4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
+#define D2F4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define D2F4_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
+#define D2F4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define D2F4_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
+#define D2F4_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define D2F4_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
+#define D2F4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define D2F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
+#define D2F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define D2F4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
+#define D2F4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define D2F4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
+#define D2F4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define D2F4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
+#define D2F4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define D2F4_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
+#define D2F4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define D2F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
+#define D2F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define D2F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
+#define D2F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define D2F4_DEVICE_STATUS__CORR_ERR_MASK 0x10000
+#define D2F4_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
+#define D2F4_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
+#define D2F4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
+#define D2F4_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
+#define D2F4_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
+#define D2F4_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
+#define D2F4_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
+#define D2F4_DEVICE_STATUS__AUX_PWR_MASK 0x100000
+#define D2F4_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
+#define D2F4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
+#define D2F4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
+#define D2F4_LINK_CAP__LINK_SPEED_MASK 0xf
+#define D2F4_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define D2F4_LINK_CAP__LINK_WIDTH_MASK 0x3f0
+#define D2F4_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define D2F4_LINK_CAP__PM_SUPPORT_MASK 0xc00
+#define D2F4_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define D2F4_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
+#define D2F4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define D2F4_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
+#define D2F4_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define D2F4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
+#define D2F4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define D2F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
+#define D2F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define D2F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
+#define D2F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define D2F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
+#define D2F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define D2F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
+#define D2F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define D2F4_LINK_CAP__PORT_NUMBER_MASK 0xff000000
+#define D2F4_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define D2F4_LINK_CNTL__PM_CONTROL_MASK 0x3
+#define D2F4_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define D2F4_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
+#define D2F4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define D2F4_LINK_CNTL__LINK_DIS_MASK 0x10
+#define D2F4_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define D2F4_LINK_CNTL__RETRAIN_LINK_MASK 0x20
+#define D2F4_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define D2F4_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
+#define D2F4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define D2F4_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
+#define D2F4_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define D2F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
+#define D2F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define D2F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
+#define D2F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define D2F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
+#define D2F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define D2F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
+#define D2F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define D2F4_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
+#define D2F4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
+#define D2F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
+#define D2F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
+#define D2F4_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
+#define D2F4_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
+#define D2F4_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
+#define D2F4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
+#define D2F4_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
+#define D2F4_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
+#define D2F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
+#define D2F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
+#define D2F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
+#define D2F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
+#define D2F4_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
+#define D2F4_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define D2F4_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
+#define D2F4_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define D2F4_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
+#define D2F4_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define D2F4_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
+#define D2F4_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define D2F4_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
+#define D2F4_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define D2F4_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
+#define D2F4_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define D2F4_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
+#define D2F4_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define D2F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
+#define D2F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define D2F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
+#define D2F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define D2F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
+#define D2F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define D2F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
+#define D2F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define D2F4_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
+#define D2F4_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define D2F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
+#define D2F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define D2F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
+#define D2F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define D2F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
+#define D2F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define D2F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
+#define D2F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define D2F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
+#define D2F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define D2F4_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
+#define D2F4_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define D2F4_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
+#define D2F4_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define D2F4_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
+#define D2F4_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define D2F4_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
+#define D2F4_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define D2F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
+#define D2F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define D2F4_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
+#define D2F4_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define D2F4_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
+#define D2F4_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
+#define D2F4_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
+#define D2F4_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
+#define D2F4_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
+#define D2F4_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
+#define D2F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
+#define D2F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
+#define D2F4_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
+#define D2F4_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
+#define D2F4_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
+#define D2F4_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
+#define D2F4_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
+#define D2F4_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
+#define D2F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
+#define D2F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
+#define D2F4_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
+#define D2F4_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
+#define D2F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
+#define D2F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define D2F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
+#define D2F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define D2F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
+#define D2F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define D2F4_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
+#define D2F4_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define D2F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
+#define D2F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define D2F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
+#define D2F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
+#define D2F4_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
+#define D2F4_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define D2F4_ROOT_STATUS__PME_STATUS_MASK 0x10000
+#define D2F4_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define D2F4_ROOT_STATUS__PME_PENDING_MASK 0x20000
+#define D2F4_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define D2F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
+#define D2F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define D2F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
+#define D2F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define D2F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
+#define D2F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define D2F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
+#define D2F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define D2F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
+#define D2F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define D2F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
+#define D2F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define D2F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
+#define D2F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define D2F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
+#define D2F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define D2F4_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
+#define D2F4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define D2F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
+#define D2F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define D2F4_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
+#define D2F4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define D2F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
+#define D2F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define D2F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
+#define D2F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define D2F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
+#define D2F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define D2F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
+#define D2F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define D2F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
+#define D2F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define D2F4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
+#define D2F4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define D2F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
+#define D2F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define D2F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
+#define D2F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define D2F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
+#define D2F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define D2F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
+#define D2F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define D2F4_DEVICE_CNTL2__LTR_EN_MASK 0x400
+#define D2F4_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define D2F4_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
+#define D2F4_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define D2F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
+#define D2F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define D2F4_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
+#define D2F4_DEVICE_STATUS2__RESERVED__SHIFT 0x10
+#define D2F4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
+#define D2F4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define D2F4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
+#define D2F4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define D2F4_LINK_CAP2__RESERVED_MASK 0xfffffe00
+#define D2F4_LINK_CAP2__RESERVED__SHIFT 0x9
+#define D2F4_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
+#define D2F4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define D2F4_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
+#define D2F4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define D2F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
+#define D2F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define D2F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
+#define D2F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define D2F4_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
+#define D2F4_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define D2F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
+#define D2F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define D2F4_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
+#define D2F4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define D2F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
+#define D2F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define D2F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
+#define D2F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
+#define D2F4_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
+#define D2F4_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
+#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
+#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
+#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
+#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
+#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
+#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
+#define D2F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
+#define D2F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
+#define D2F4_SLOT_CAP2__RESERVED_MASK 0xffffffff
+#define D2F4_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define D2F4_SLOT_CNTL2__RESERVED_MASK 0xffff
+#define D2F4_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define D2F4_SLOT_STATUS2__RESERVED_MASK 0xffff0000
+#define D2F4_SLOT_STATUS2__RESERVED__SHIFT 0x10
+#define D2F4_MSI_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F4_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F4_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F4_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F4_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
+#define D2F4_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
+#define D2F4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
+#define D2F4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
+#define D2F4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
+#define D2F4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
+#define D2F4_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
+#define D2F4_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
+#define D2F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
+#define D2F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
+#define D2F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
+#define D2F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define D2F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
+#define D2F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define D2F4_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
+#define D2F4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define D2F4_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
+#define D2F4_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define D2F4_SSID_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F4_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F4_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F4_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F4_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
+#define D2F4_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define D2F4_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
+#define D2F4_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define D2F4_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F4_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F4_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F4_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F4_MSI_MAP_CAP__EN_MASK 0x10000
+#define D2F4_MSI_MAP_CAP__EN__SHIFT 0x10
+#define D2F4_MSI_MAP_CAP__FIXD_MASK 0x20000
+#define D2F4_MSI_MAP_CAP__FIXD__SHIFT 0x11
+#define D2F4_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
+#define D2F4_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
+#define D2F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
+#define D2F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define D2F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
+#define D2F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
+#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
+#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
+#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define D2F4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
+#define D2F4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define D2F4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
+#define D2F4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define D2F4_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F4_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F4_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F4_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
+#define D2F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define D2F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
+#define D2F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define D2F4_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
+#define D2F4_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define D2F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
+#define D2F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
+#define D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D2F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
+#define D2F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define D2F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
+#define D2F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define D2F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
+#define D2F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
+#define D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define D2F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define D2F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define D2F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define D2F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define D2F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define D2F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define D2F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define D2F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define D2F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
+#define D2F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
+#define D2F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
+#define D2F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
+#define D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define D2F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define D2F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define D2F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define D2F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define D2F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define D2F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define D2F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define D2F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define D2F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
+#define D2F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
+#define D2F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
+#define D2F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
+#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
+#define D2F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define D2F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
+#define D2F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
+#define D2F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define D2F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
+#define D2F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define D2F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
+#define D2F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define D2F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
+#define D2F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define D2F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
+#define D2F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define D2F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
+#define D2F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define D2F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
+#define D2F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define D2F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
+#define D2F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define D2F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
+#define D2F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define D2F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
+#define D2F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define D2F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
+#define D2F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define D2F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
+#define D2F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define D2F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
+#define D2F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define D2F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
+#define D2F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define D2F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
+#define D2F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define D2F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
+#define D2F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define D2F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
+#define D2F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define D2F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
+#define D2F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define D2F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
+#define D2F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define D2F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
+#define D2F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define D2F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
+#define D2F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define D2F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
+#define D2F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define D2F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
+#define D2F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define D2F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
+#define D2F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define D2F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
+#define D2F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define D2F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
+#define D2F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define D2F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
+#define D2F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define D2F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
+#define D2F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define D2F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
+#define D2F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define D2F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
+#define D2F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define D2F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
+#define D2F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define D2F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
+#define D2F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
+#define D2F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define D2F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
+#define D2F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define D2F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
+#define D2F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define D2F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
+#define D2F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define D2F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
+#define D2F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define D2F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
+#define D2F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define D2F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
+#define D2F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define D2F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
+#define D2F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define D2F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
+#define D2F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define D2F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
+#define D2F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define D2F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
+#define D2F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define D2F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
+#define D2F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define D2F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
+#define D2F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define D2F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
+#define D2F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define D2F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
+#define D2F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define D2F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
+#define D2F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define D2F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
+#define D2F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define D2F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
+#define D2F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
+#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
+#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
+#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
+#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
+#define D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
+#define D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define D2F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
+#define D2F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define D2F4_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
+#define D2F4_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define D2F4_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
+#define D2F4_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define D2F4_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
+#define D2F4_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define D2F4_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
+#define D2F4_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define D2F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
+#define D2F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define D2F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
+#define D2F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define D2F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
+#define D2F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define D2F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
+#define D2F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
+#define D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define D2F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
+#define D2F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
+#define D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define D2F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
+#define D2F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define D2F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
+#define D2F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define D2F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
+#define D2F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define D2F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
+#define D2F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define D2F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
+#define D2F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define D2F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
+#define D2F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define D2F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
+#define D2F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define D2F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
+#define D2F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define D2F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
+#define D2F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define D2F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
+#define D2F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
+#define D2F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define D2F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
+#define D2F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define D2F4_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
+#define D2F4_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define D2F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
+#define D2F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define D2F4_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
+#define D2F4_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F4_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
+#define D2F4_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define D2F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
+#define D2F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define D2F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
+#define D2F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define D2F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
+#define D2F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define D2F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
+#define D2F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define D2F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
+#define D2F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define D2F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
+#define D2F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define D2F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
+#define D2F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define D2F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
+#define D2F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
+#define D2F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
+#define D2F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
+#define D2F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
+#define D2F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
+#define D2F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
+#define D2F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
+#define D2F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
+#define D2F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
+#define D2F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
+#define D2F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
+#define D2F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
+#define D2F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
+#define D2F4_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F4_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F4_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F4_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F4_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
+#define D2F4_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define D2F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
+#define D2F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define D2F4_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
+#define D2F4_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
+#define D2F4_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
+#define D2F4_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
+#define D2F4_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
+#define D2F4_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define D2F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
+#define D2F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define D2F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
+#define D2F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define D2F4_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
+#define D2F4_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define D2F4_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
+#define D2F4_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define D2F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
+#define D2F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define D2F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
+#define D2F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define D2F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
+#define D2F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define D2F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
+#define D2F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
+#define D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
+#define D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define D2F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
+#define D2F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define D2F5_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
+#define D2F5_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
+#define D2F5_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
+#define D2F5_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
+#define D2F5_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
+#define D2F5_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define D2F5_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
+#define D2F5_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define D2F5_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define D2F5_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define D2F5_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define D2F5_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define D2F5_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define D2F5_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define D2F5_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define D2F5_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define D2F5_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define D2F5_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define D2F5_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define D2F5_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define D2F5_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define D2F5_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define D2F5_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define D2F5_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define D2F5_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define D2F5_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define D2F5_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define D2F5_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define D2F5_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define D2F5_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define D2F5_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define D2F5_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define D2F5_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define D2F5_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define D2F5_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define D2F5_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define D2F5_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define D2F5_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define D2F5_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define D2F5_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define D2F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
+#define D2F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define D2F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
+#define D2F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define D2F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
+#define D2F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define D2F5_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
+#define D2F5_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define D2F5_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
+#define D2F5_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define D2F5_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
+#define D2F5_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define D2F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
+#define D2F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
+#define D2F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
+#define D2F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define D2F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
+#define D2F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define D2F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
+#define D2F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define D2F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
+#define D2F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define D2F5_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
+#define D2F5_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define D2F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
+#define D2F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define D2F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
+#define D2F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define D2F5_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
+#define D2F5_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define D2F5_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
+#define D2F5_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define D2F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
+#define D2F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define D2F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
+#define D2F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
+#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
+#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
+#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define D2F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
+#define D2F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
+#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
+#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
+#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define D2F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
+#define D2F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define D2F5_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
+#define D2F5_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
+#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
+#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
+#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
+#define D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
+#define D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
+#define D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
+#define D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
+#define D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
+#define D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
+#define D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
+#define D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
+#define D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
+#define D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
+#define D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
+#define D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
+#define D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
+#define D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
+#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
+#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
+#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
+#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
+#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
+#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
+#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define D2F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
+#define D2F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define D2F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
+#define D2F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define D2F5_PCIE_FC_P__PD_CREDITS_MASK 0xff
+#define D2F5_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define D2F5_PCIE_FC_P__PH_CREDITS_MASK 0xff00
+#define D2F5_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
+#define D2F5_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
+#define D2F5_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define D2F5_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
+#define D2F5_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
+#define D2F5_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
+#define D2F5_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define D2F5_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
+#define D2F5_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
+#define D2F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
+#define D2F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define D2F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
+#define D2F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define D2F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
+#define D2F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define D2F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
+#define D2F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define D2F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
+#define D2F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define D2F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
+#define D2F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define D2F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
+#define D2F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
+#define D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
+#define D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define D2F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
+#define D2F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define D2F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
+#define D2F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define D2F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
+#define D2F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define D2F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
+#define D2F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define D2F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
+#define D2F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define D2F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
+#define D2F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define D2F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
+#define D2F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
+#define D2F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
+#define D2F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
+#define D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
+#define D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define D2F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
+#define D2F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
+#define D2F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define D2F5_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
+#define D2F5_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define D2F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
+#define D2F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define D2F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
+#define D2F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
+#define D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
+#define D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
+#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
+#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
+#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
+#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
+#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
+#define D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
+#define D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
+#define D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
+#define D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
+#define D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
+#define D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
+#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
+#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
+#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
+#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
+#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
+#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
+#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
+#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
+#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
+#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
+#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define D2F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
+#define D2F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define D2F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
+#define D2F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define D2F5_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
+#define D2F5_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define D2F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
+#define D2F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define D2F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
+#define D2F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define D2F5_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
+#define D2F5_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define D2F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
+#define D2F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define D2F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
+#define D2F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define D2F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
+#define D2F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define D2F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
+#define D2F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define D2F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
+#define D2F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define D2F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
+#define D2F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define D2F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
+#define D2F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define D2F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
+#define D2F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define D2F5_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
+#define D2F5_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define D2F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
+#define D2F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define D2F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
+#define D2F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define D2F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
+#define D2F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define D2F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
+#define D2F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define D2F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
+#define D2F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define D2F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
+#define D2F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define D2F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
+#define D2F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define D2F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
+#define D2F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define D2F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
+#define D2F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define D2F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
+#define D2F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define D2F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
+#define D2F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
+#define D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
+#define D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
+#define D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define D2F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
+#define D2F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define D2F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
+#define D2F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
+#define D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
+#define D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define D2F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
+#define D2F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
+#define D2F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
+#define D2F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define D2F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
+#define D2F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define D2F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
+#define D2F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
+#define D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define D2F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
+#define D2F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define D2F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
+#define D2F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define D2F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
+#define D2F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define D2F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
+#define D2F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define D2F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
+#define D2F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define D2F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
+#define D2F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
+#define D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
+#define D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define D2F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
+#define D2F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define D2F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
+#define D2F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define D2F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
+#define D2F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
+#define D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
+#define D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define D2F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
+#define D2F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define D2F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
+#define D2F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define D2F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
+#define D2F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define D2F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
+#define D2F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
+#define D2F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
+#define D2F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
+#define D2F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
+#define D2F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
+#define D2F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
+#define D2F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
+#define D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
+#define D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define D2F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
+#define D2F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define D2F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
+#define D2F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
+#define D2F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
+#define D2F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define D2F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
+#define D2F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define D2F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
+#define D2F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define D2F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
+#define D2F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define D2F5_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
+#define D2F5_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
+#define D2F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
+#define D2F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define D2F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
+#define D2F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define D2F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
+#define D2F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
+#define D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
+#define D2F5_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
+#define D2F5_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
+#define D2F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
+#define D2F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define D2F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
+#define D2F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define D2F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
+#define D2F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
+#define D2F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
+#define D2F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define D2F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
+#define D2F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
+#define D2F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
+#define D2F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
+#define D2F5_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
+#define D2F5_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define D2F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
+#define D2F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define D2F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
+#define D2F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
+#define D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
+#define D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
+#define D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
+#define D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
+#define D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
+#define D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
+#define D2F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
+#define D2F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define D2F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
+#define D2F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
+#define D2F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
+#define D2F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define D2F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
+#define D2F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define D2F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
+#define D2F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define D2F5_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
+#define D2F5_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
+#define D2F5_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
+#define D2F5_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
+#define D2F5_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
+#define D2F5_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
+#define D2F5_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
+#define D2F5_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
+#define D2F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
+#define D2F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
+#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
+#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
+#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
+#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
+#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
+#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
+#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
+#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
+#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
+#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
+#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
+#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
+#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
+#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
+#define D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
+#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
+#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
+#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
+#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
+#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define D2F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
+#define D2F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
+#define D2F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
+#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
+#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
+#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
+#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define D2F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
+#define D2F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define D2F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
+#define D2F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
+#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
+#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
+#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
+#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
+#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
+#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
+#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
+#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
+#define D2F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
+#define D2F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
+#define D2F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
+#define D2F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
+#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
+#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
+#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
+#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
+#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
+#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
+#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
+#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
+#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
+#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
+#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
+#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
+#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
+#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
+#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
+#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
+#define D2F5_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
+#define D2F5_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
+#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
+#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
+#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
+#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
+#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
+#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
+#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
+#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
+#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
+#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
+#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
+#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
+#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
+#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
+#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
+#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
+#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
+#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
+#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
+#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
+#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
+#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
+#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define D2F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
+#define D2F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define D2F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
+#define D2F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define D2F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
+#define D2F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define D2F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
+#define D2F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define D2F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
+#define D2F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define D2F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
+#define D2F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define D2F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
+#define D2F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define D2F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
+#define D2F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define D2F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
+#define D2F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define D2F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
+#define D2F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define D2F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
+#define D2F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define D2F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
+#define D2F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define D2F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
+#define D2F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define D2F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
+#define D2F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define D2F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
+#define D2F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define D2F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
+#define D2F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define D2F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
+#define D2F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
+#define D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
+#define D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
+#define D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
+#define D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
+#define D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
+#define D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
+#define D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
+#define D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define D2F5_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
+#define D2F5_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
+#define D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
+#define D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
+#define D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
+#define D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define D2F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
+#define D2F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define D2F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
+#define D2F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define D2F5_VENDOR_ID__VENDOR_ID_MASK 0xffff
+#define D2F5_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define D2F5_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
+#define D2F5_DEVICE_ID__DEVICE_ID__SHIFT 0x10
+#define D2F5_COMMAND__IO_ACCESS_EN_MASK 0x1
+#define D2F5_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define D2F5_COMMAND__MEM_ACCESS_EN_MASK 0x2
+#define D2F5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define D2F5_COMMAND__BUS_MASTER_EN_MASK 0x4
+#define D2F5_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define D2F5_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
+#define D2F5_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define D2F5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
+#define D2F5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define D2F5_COMMAND__PAL_SNOOP_EN_MASK 0x20
+#define D2F5_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define D2F5_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
+#define D2F5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define D2F5_COMMAND__AD_STEPPING_MASK 0x80
+#define D2F5_COMMAND__AD_STEPPING__SHIFT 0x7
+#define D2F5_COMMAND__SERR_EN_MASK 0x100
+#define D2F5_COMMAND__SERR_EN__SHIFT 0x8
+#define D2F5_COMMAND__FAST_B2B_EN_MASK 0x200
+#define D2F5_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define D2F5_COMMAND__INT_DIS_MASK 0x400
+#define D2F5_COMMAND__INT_DIS__SHIFT 0xa
+#define D2F5_STATUS__INT_STATUS_MASK 0x80000
+#define D2F5_STATUS__INT_STATUS__SHIFT 0x13
+#define D2F5_STATUS__CAP_LIST_MASK 0x100000
+#define D2F5_STATUS__CAP_LIST__SHIFT 0x14
+#define D2F5_STATUS__PCI_66_EN_MASK 0x200000
+#define D2F5_STATUS__PCI_66_EN__SHIFT 0x15
+#define D2F5_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
+#define D2F5_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
+#define D2F5_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
+#define D2F5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
+#define D2F5_STATUS__DEVSEL_TIMING_MASK 0x6000000
+#define D2F5_STATUS__DEVSEL_TIMING__SHIFT 0x19
+#define D2F5_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
+#define D2F5_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
+#define D2F5_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
+#define D2F5_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
+#define D2F5_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
+#define D2F5_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
+#define D2F5_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
+#define D2F5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
+#define D2F5_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
+#define D2F5_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
+#define D2F5_REVISION_ID__MINOR_REV_ID_MASK 0xf
+#define D2F5_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define D2F5_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
+#define D2F5_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define D2F5_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
+#define D2F5_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
+#define D2F5_SUB_CLASS__SUB_CLASS_MASK 0xff0000
+#define D2F5_SUB_CLASS__SUB_CLASS__SHIFT 0x10
+#define D2F5_BASE_CLASS__BASE_CLASS_MASK 0xff000000
+#define D2F5_BASE_CLASS__BASE_CLASS__SHIFT 0x18
+#define D2F5_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
+#define D2F5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define D2F5_LATENCY__LATENCY_TIMER_MASK 0xff00
+#define D2F5_LATENCY__LATENCY_TIMER__SHIFT 0x8
+#define D2F5_HEADER__HEADER_TYPE_MASK 0x7f0000
+#define D2F5_HEADER__HEADER_TYPE__SHIFT 0x10
+#define D2F5_HEADER__DEVICE_TYPE_MASK 0x800000
+#define D2F5_HEADER__DEVICE_TYPE__SHIFT 0x17
+#define D2F5_BIST__BIST_COMP_MASK 0xf000000
+#define D2F5_BIST__BIST_COMP__SHIFT 0x18
+#define D2F5_BIST__BIST_STRT_MASK 0x40000000
+#define D2F5_BIST__BIST_STRT__SHIFT 0x1e
+#define D2F5_BIST__BIST_CAP_MASK 0x80000000
+#define D2F5_BIST__BIST_CAP__SHIFT 0x1f
+#define D2F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
+#define D2F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
+#define D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define D2F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
+#define D2F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
+#define D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define D2F5_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
+#define D2F5_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define D2F5_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
+#define D2F5_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define D2F5_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
+#define D2F5_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define D2F5_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
+#define D2F5_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define D2F5_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
+#define D2F5_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
+#define D2F5_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
+#define D2F5_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
+#define D2F5_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
+#define D2F5_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
+#define D2F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
+#define D2F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
+#define D2F5_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
+#define D2F5_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
+#define D2F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
+#define D2F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
+#define D2F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
+#define D2F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
+#define D2F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
+#define D2F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
+#define D2F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
+#define D2F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
+#define D2F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
+#define D2F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
+#define D2F5_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
+#define D2F5_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define D2F5_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
+#define D2F5_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define D2F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
+#define D2F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define D2F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
+#define D2F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
+#define D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
+#define D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
+#define D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
+#define D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define D2F5_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
+#define D2F5_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define D2F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
+#define D2F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define D2F5_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
+#define D2F5_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define D2F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
+#define D2F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define D2F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
+#define D2F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
+#define D2F5_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
+#define D2F5_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
+#define D2F5_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
+#define D2F5_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
+#define D2F5_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
+#define D2F5_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
+#define D2F5_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
+#define D2F5_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
+#define D2F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
+#define D2F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
+#define D2F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
+#define D2F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
+#define D2F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
+#define D2F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
+#define D2F5_CAP_PTR__CAP_PTR_MASK 0xff
+#define D2F5_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define D2F5_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
+#define D2F5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define D2F5_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
+#define D2F5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
+#define D2F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
+#define D2F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define D2F5_PMI_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F5_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F5_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F5_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F5_PMI_CAP__VERSION_MASK 0x70000
+#define D2F5_PMI_CAP__VERSION__SHIFT 0x10
+#define D2F5_PMI_CAP__PME_CLOCK_MASK 0x80000
+#define D2F5_PMI_CAP__PME_CLOCK__SHIFT 0x13
+#define D2F5_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
+#define D2F5_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
+#define D2F5_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
+#define D2F5_PMI_CAP__AUX_CURRENT__SHIFT 0x16
+#define D2F5_PMI_CAP__D1_SUPPORT_MASK 0x2000000
+#define D2F5_PMI_CAP__D1_SUPPORT__SHIFT 0x19
+#define D2F5_PMI_CAP__D2_SUPPORT_MASK 0x4000000
+#define D2F5_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
+#define D2F5_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
+#define D2F5_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
+#define D2F5_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
+#define D2F5_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define D2F5_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
+#define D2F5_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define D2F5_PMI_STATUS_CNTL__PME_EN_MASK 0x100
+#define D2F5_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define D2F5_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
+#define D2F5_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define D2F5_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
+#define D2F5_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define D2F5_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
+#define D2F5_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define D2F5_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
+#define D2F5_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define D2F5_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
+#define D2F5_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define D2F5_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
+#define D2F5_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define D2F5_PCIE_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F5_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F5_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F5_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F5_PCIE_CAP__VERSION_MASK 0xf0000
+#define D2F5_PCIE_CAP__VERSION__SHIFT 0x10
+#define D2F5_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
+#define D2F5_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
+#define D2F5_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
+#define D2F5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
+#define D2F5_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
+#define D2F5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
+#define D2F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
+#define D2F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define D2F5_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
+#define D2F5_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define D2F5_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
+#define D2F5_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define D2F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
+#define D2F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define D2F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
+#define D2F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define D2F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
+#define D2F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
+#define D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
+#define D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define D2F5_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
+#define D2F5_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define D2F5_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
+#define D2F5_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define D2F5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
+#define D2F5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define D2F5_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
+#define D2F5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define D2F5_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
+#define D2F5_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define D2F5_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
+#define D2F5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define D2F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
+#define D2F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define D2F5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
+#define D2F5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define D2F5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
+#define D2F5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define D2F5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
+#define D2F5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define D2F5_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
+#define D2F5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define D2F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
+#define D2F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define D2F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
+#define D2F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define D2F5_DEVICE_STATUS__CORR_ERR_MASK 0x10000
+#define D2F5_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
+#define D2F5_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
+#define D2F5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
+#define D2F5_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
+#define D2F5_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
+#define D2F5_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
+#define D2F5_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
+#define D2F5_DEVICE_STATUS__AUX_PWR_MASK 0x100000
+#define D2F5_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
+#define D2F5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
+#define D2F5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
+#define D2F5_LINK_CAP__LINK_SPEED_MASK 0xf
+#define D2F5_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define D2F5_LINK_CAP__LINK_WIDTH_MASK 0x3f0
+#define D2F5_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define D2F5_LINK_CAP__PM_SUPPORT_MASK 0xc00
+#define D2F5_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define D2F5_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
+#define D2F5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define D2F5_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
+#define D2F5_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define D2F5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
+#define D2F5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define D2F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
+#define D2F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define D2F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
+#define D2F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define D2F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
+#define D2F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define D2F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
+#define D2F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define D2F5_LINK_CAP__PORT_NUMBER_MASK 0xff000000
+#define D2F5_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define D2F5_LINK_CNTL__PM_CONTROL_MASK 0x3
+#define D2F5_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define D2F5_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
+#define D2F5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define D2F5_LINK_CNTL__LINK_DIS_MASK 0x10
+#define D2F5_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define D2F5_LINK_CNTL__RETRAIN_LINK_MASK 0x20
+#define D2F5_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define D2F5_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
+#define D2F5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define D2F5_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
+#define D2F5_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define D2F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
+#define D2F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define D2F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
+#define D2F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define D2F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
+#define D2F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define D2F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
+#define D2F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define D2F5_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
+#define D2F5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
+#define D2F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
+#define D2F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
+#define D2F5_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
+#define D2F5_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
+#define D2F5_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
+#define D2F5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
+#define D2F5_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
+#define D2F5_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
+#define D2F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
+#define D2F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
+#define D2F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
+#define D2F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
+#define D2F5_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
+#define D2F5_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define D2F5_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
+#define D2F5_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define D2F5_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
+#define D2F5_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define D2F5_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
+#define D2F5_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define D2F5_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
+#define D2F5_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define D2F5_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
+#define D2F5_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define D2F5_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
+#define D2F5_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define D2F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
+#define D2F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define D2F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
+#define D2F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define D2F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
+#define D2F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define D2F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
+#define D2F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define D2F5_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
+#define D2F5_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define D2F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
+#define D2F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define D2F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
+#define D2F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define D2F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
+#define D2F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define D2F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
+#define D2F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define D2F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
+#define D2F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define D2F5_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
+#define D2F5_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define D2F5_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
+#define D2F5_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define D2F5_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
+#define D2F5_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define D2F5_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
+#define D2F5_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define D2F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
+#define D2F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define D2F5_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
+#define D2F5_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define D2F5_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
+#define D2F5_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
+#define D2F5_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
+#define D2F5_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
+#define D2F5_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
+#define D2F5_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
+#define D2F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
+#define D2F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
+#define D2F5_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
+#define D2F5_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
+#define D2F5_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
+#define D2F5_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
+#define D2F5_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
+#define D2F5_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
+#define D2F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
+#define D2F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
+#define D2F5_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
+#define D2F5_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
+#define D2F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
+#define D2F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define D2F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
+#define D2F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define D2F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
+#define D2F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define D2F5_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
+#define D2F5_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define D2F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
+#define D2F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define D2F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
+#define D2F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
+#define D2F5_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
+#define D2F5_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define D2F5_ROOT_STATUS__PME_STATUS_MASK 0x10000
+#define D2F5_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define D2F5_ROOT_STATUS__PME_PENDING_MASK 0x20000
+#define D2F5_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define D2F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
+#define D2F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define D2F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
+#define D2F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define D2F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
+#define D2F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define D2F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
+#define D2F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define D2F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
+#define D2F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define D2F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
+#define D2F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define D2F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
+#define D2F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define D2F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
+#define D2F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define D2F5_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
+#define D2F5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define D2F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
+#define D2F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define D2F5_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
+#define D2F5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define D2F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
+#define D2F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define D2F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
+#define D2F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define D2F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
+#define D2F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define D2F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
+#define D2F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define D2F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
+#define D2F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define D2F5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
+#define D2F5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define D2F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
+#define D2F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define D2F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
+#define D2F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define D2F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
+#define D2F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define D2F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
+#define D2F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define D2F5_DEVICE_CNTL2__LTR_EN_MASK 0x400
+#define D2F5_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define D2F5_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
+#define D2F5_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define D2F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
+#define D2F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define D2F5_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
+#define D2F5_DEVICE_STATUS2__RESERVED__SHIFT 0x10
+#define D2F5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
+#define D2F5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define D2F5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
+#define D2F5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define D2F5_LINK_CAP2__RESERVED_MASK 0xfffffe00
+#define D2F5_LINK_CAP2__RESERVED__SHIFT 0x9
+#define D2F5_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
+#define D2F5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define D2F5_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
+#define D2F5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define D2F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
+#define D2F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define D2F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
+#define D2F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define D2F5_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
+#define D2F5_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define D2F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
+#define D2F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define D2F5_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
+#define D2F5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define D2F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
+#define D2F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define D2F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
+#define D2F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
+#define D2F5_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
+#define D2F5_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
+#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
+#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
+#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
+#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
+#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
+#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
+#define D2F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
+#define D2F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
+#define D2F5_SLOT_CAP2__RESERVED_MASK 0xffffffff
+#define D2F5_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define D2F5_SLOT_CNTL2__RESERVED_MASK 0xffff
+#define D2F5_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define D2F5_SLOT_STATUS2__RESERVED_MASK 0xffff0000
+#define D2F5_SLOT_STATUS2__RESERVED__SHIFT 0x10
+#define D2F5_MSI_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F5_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F5_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F5_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F5_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
+#define D2F5_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
+#define D2F5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
+#define D2F5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
+#define D2F5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
+#define D2F5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
+#define D2F5_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
+#define D2F5_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
+#define D2F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
+#define D2F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
+#define D2F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
+#define D2F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define D2F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
+#define D2F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define D2F5_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
+#define D2F5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define D2F5_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
+#define D2F5_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define D2F5_SSID_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F5_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F5_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F5_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F5_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
+#define D2F5_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define D2F5_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
+#define D2F5_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define D2F5_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
+#define D2F5_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F5_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D2F5_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D2F5_MSI_MAP_CAP__EN_MASK 0x10000
+#define D2F5_MSI_MAP_CAP__EN__SHIFT 0x10
+#define D2F5_MSI_MAP_CAP__FIXD_MASK 0x20000
+#define D2F5_MSI_MAP_CAP__FIXD__SHIFT 0x11
+#define D2F5_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
+#define D2F5_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
+#define D2F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
+#define D2F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define D2F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
+#define D2F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
+#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
+#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
+#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define D2F5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
+#define D2F5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define D2F5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
+#define D2F5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define D2F5_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F5_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F5_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F5_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
+#define D2F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define D2F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
+#define D2F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define D2F5_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
+#define D2F5_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define D2F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
+#define D2F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
+#define D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D2F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
+#define D2F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define D2F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
+#define D2F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define D2F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
+#define D2F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
+#define D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define D2F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define D2F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define D2F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define D2F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define D2F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define D2F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define D2F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define D2F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define D2F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
+#define D2F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
+#define D2F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
+#define D2F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
+#define D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define D2F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define D2F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define D2F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define D2F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define D2F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define D2F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define D2F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define D2F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define D2F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
+#define D2F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
+#define D2F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
+#define D2F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
+#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
+#define D2F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define D2F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
+#define D2F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
+#define D2F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define D2F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
+#define D2F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define D2F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
+#define D2F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define D2F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
+#define D2F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define D2F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
+#define D2F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define D2F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
+#define D2F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define D2F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
+#define D2F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define D2F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
+#define D2F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define D2F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
+#define D2F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define D2F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
+#define D2F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define D2F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
+#define D2F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define D2F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
+#define D2F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define D2F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
+#define D2F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define D2F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
+#define D2F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define D2F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
+#define D2F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define D2F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
+#define D2F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define D2F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
+#define D2F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define D2F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
+#define D2F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define D2F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
+#define D2F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define D2F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
+#define D2F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define D2F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
+#define D2F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define D2F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
+#define D2F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define D2F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
+#define D2F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define D2F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
+#define D2F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define D2F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
+#define D2F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define D2F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
+#define D2F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define D2F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
+#define D2F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define D2F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
+#define D2F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define D2F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
+#define D2F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define D2F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
+#define D2F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define D2F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
+#define D2F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define D2F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
+#define D2F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
+#define D2F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define D2F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
+#define D2F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define D2F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
+#define D2F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define D2F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
+#define D2F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define D2F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
+#define D2F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define D2F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
+#define D2F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define D2F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
+#define D2F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define D2F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
+#define D2F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define D2F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
+#define D2F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define D2F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
+#define D2F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define D2F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
+#define D2F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define D2F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
+#define D2F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define D2F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
+#define D2F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define D2F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
+#define D2F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define D2F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
+#define D2F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define D2F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
+#define D2F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define D2F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
+#define D2F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define D2F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
+#define D2F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
+#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
+#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
+#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
+#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
+#define D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
+#define D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define D2F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
+#define D2F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define D2F5_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
+#define D2F5_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define D2F5_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
+#define D2F5_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define D2F5_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
+#define D2F5_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define D2F5_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
+#define D2F5_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define D2F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
+#define D2F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define D2F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
+#define D2F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define D2F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
+#define D2F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define D2F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
+#define D2F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
+#define D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define D2F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
+#define D2F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
+#define D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define D2F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
+#define D2F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define D2F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
+#define D2F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define D2F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
+#define D2F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define D2F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
+#define D2F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define D2F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
+#define D2F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define D2F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
+#define D2F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define D2F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
+#define D2F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define D2F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
+#define D2F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define D2F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
+#define D2F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define D2F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
+#define D2F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
+#define D2F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define D2F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
+#define D2F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define D2F5_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
+#define D2F5_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define D2F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
+#define D2F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define D2F5_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
+#define D2F5_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F5_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
+#define D2F5_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define D2F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
+#define D2F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define D2F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
+#define D2F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define D2F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
+#define D2F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define D2F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
+#define D2F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define D2F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
+#define D2F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define D2F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
+#define D2F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define D2F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
+#define D2F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define D2F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
+#define D2F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
+#define D2F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
+#define D2F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
+#define D2F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
+#define D2F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
+#define D2F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
+#define D2F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
+#define D2F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
+#define D2F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
+#define D2F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
+#define D2F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
+#define D2F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
+#define D2F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
+#define D2F5_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D2F5_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D2F5_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D2F5_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D2F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D2F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D2F5_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
+#define D2F5_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define D2F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
+#define D2F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define D2F5_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
+#define D2F5_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
+#define D2F5_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
+#define D2F5_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
+#define D2F5_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
+#define D2F5_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define D2F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
+#define D2F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define D2F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
+#define D2F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define D2F5_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
+#define D2F5_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define D2F5_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
+#define D2F5_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define D2F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
+#define D2F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define D2F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
+#define D2F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define D2F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
+#define D2F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define D2F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
+#define D2F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
+#define D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
+#define D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define D2F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
+#define D2F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define D3F1_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
+#define D3F1_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
+#define D3F1_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
+#define D3F1_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
+#define D3F1_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
+#define D3F1_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define D3F1_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
+#define D3F1_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define D3F1_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define D3F1_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define D3F1_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define D3F1_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define D3F1_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define D3F1_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define D3F1_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define D3F1_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define D3F1_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define D3F1_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define D3F1_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define D3F1_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define D3F1_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define D3F1_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define D3F1_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define D3F1_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define D3F1_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define D3F1_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define D3F1_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define D3F1_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define D3F1_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define D3F1_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define D3F1_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define D3F1_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define D3F1_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define D3F1_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define D3F1_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define D3F1_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define D3F1_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define D3F1_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define D3F1_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define D3F1_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define D3F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
+#define D3F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define D3F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
+#define D3F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define D3F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
+#define D3F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define D3F1_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
+#define D3F1_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define D3F1_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
+#define D3F1_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define D3F1_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
+#define D3F1_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define D3F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
+#define D3F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
+#define D3F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
+#define D3F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define D3F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
+#define D3F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define D3F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
+#define D3F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define D3F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
+#define D3F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define D3F1_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
+#define D3F1_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define D3F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
+#define D3F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define D3F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
+#define D3F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define D3F1_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
+#define D3F1_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define D3F1_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
+#define D3F1_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define D3F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
+#define D3F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define D3F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
+#define D3F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
+#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
+#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
+#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define D3F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
+#define D3F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
+#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
+#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
+#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define D3F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
+#define D3F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define D3F1_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
+#define D3F1_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
+#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
+#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
+#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
+#define D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
+#define D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
+#define D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
+#define D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
+#define D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
+#define D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
+#define D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
+#define D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
+#define D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
+#define D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
+#define D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
+#define D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
+#define D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
+#define D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
+#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
+#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
+#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
+#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
+#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
+#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
+#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define D3F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
+#define D3F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define D3F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
+#define D3F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define D3F1_PCIE_FC_P__PD_CREDITS_MASK 0xff
+#define D3F1_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define D3F1_PCIE_FC_P__PH_CREDITS_MASK 0xff00
+#define D3F1_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
+#define D3F1_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
+#define D3F1_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define D3F1_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
+#define D3F1_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
+#define D3F1_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
+#define D3F1_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define D3F1_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
+#define D3F1_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
+#define D3F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
+#define D3F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define D3F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
+#define D3F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define D3F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
+#define D3F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define D3F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
+#define D3F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define D3F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
+#define D3F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define D3F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
+#define D3F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define D3F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
+#define D3F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
+#define D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
+#define D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define D3F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
+#define D3F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define D3F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
+#define D3F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define D3F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
+#define D3F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define D3F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
+#define D3F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define D3F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
+#define D3F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define D3F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
+#define D3F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define D3F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
+#define D3F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
+#define D3F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
+#define D3F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
+#define D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
+#define D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define D3F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
+#define D3F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
+#define D3F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define D3F1_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
+#define D3F1_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define D3F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
+#define D3F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define D3F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
+#define D3F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
+#define D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
+#define D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
+#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
+#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
+#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
+#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
+#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
+#define D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
+#define D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
+#define D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
+#define D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
+#define D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
+#define D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
+#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
+#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
+#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
+#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
+#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
+#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
+#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
+#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
+#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
+#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
+#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define D3F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
+#define D3F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define D3F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
+#define D3F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define D3F1_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
+#define D3F1_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define D3F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
+#define D3F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define D3F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
+#define D3F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define D3F1_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
+#define D3F1_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define D3F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
+#define D3F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define D3F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
+#define D3F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define D3F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
+#define D3F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define D3F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
+#define D3F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define D3F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
+#define D3F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define D3F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
+#define D3F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define D3F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
+#define D3F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define D3F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
+#define D3F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define D3F1_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
+#define D3F1_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define D3F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
+#define D3F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define D3F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
+#define D3F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define D3F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
+#define D3F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define D3F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
+#define D3F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define D3F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
+#define D3F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define D3F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
+#define D3F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define D3F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
+#define D3F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define D3F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
+#define D3F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define D3F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
+#define D3F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define D3F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
+#define D3F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define D3F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
+#define D3F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
+#define D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
+#define D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
+#define D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define D3F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
+#define D3F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define D3F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
+#define D3F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
+#define D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
+#define D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define D3F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
+#define D3F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
+#define D3F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
+#define D3F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define D3F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
+#define D3F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define D3F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
+#define D3F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
+#define D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define D3F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
+#define D3F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define D3F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
+#define D3F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define D3F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
+#define D3F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define D3F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
+#define D3F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define D3F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
+#define D3F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define D3F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
+#define D3F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
+#define D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
+#define D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define D3F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
+#define D3F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define D3F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
+#define D3F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define D3F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
+#define D3F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
+#define D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
+#define D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define D3F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
+#define D3F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define D3F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
+#define D3F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define D3F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
+#define D3F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define D3F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
+#define D3F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
+#define D3F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
+#define D3F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
+#define D3F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
+#define D3F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
+#define D3F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
+#define D3F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
+#define D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
+#define D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define D3F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
+#define D3F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define D3F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
+#define D3F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
+#define D3F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
+#define D3F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define D3F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
+#define D3F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define D3F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
+#define D3F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define D3F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
+#define D3F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define D3F1_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
+#define D3F1_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
+#define D3F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
+#define D3F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define D3F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
+#define D3F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define D3F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
+#define D3F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
+#define D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
+#define D3F1_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
+#define D3F1_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
+#define D3F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
+#define D3F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define D3F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
+#define D3F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define D3F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
+#define D3F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
+#define D3F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
+#define D3F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define D3F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
+#define D3F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
+#define D3F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
+#define D3F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
+#define D3F1_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
+#define D3F1_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define D3F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
+#define D3F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define D3F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
+#define D3F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
+#define D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
+#define D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
+#define D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
+#define D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
+#define D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
+#define D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
+#define D3F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
+#define D3F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define D3F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
+#define D3F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
+#define D3F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
+#define D3F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define D3F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
+#define D3F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define D3F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
+#define D3F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define D3F1_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
+#define D3F1_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
+#define D3F1_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
+#define D3F1_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
+#define D3F1_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
+#define D3F1_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
+#define D3F1_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
+#define D3F1_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
+#define D3F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
+#define D3F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
+#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
+#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
+#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
+#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
+#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
+#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
+#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
+#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
+#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
+#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
+#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
+#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
+#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
+#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
+#define D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
+#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
+#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
+#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
+#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
+#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define D3F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
+#define D3F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
+#define D3F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
+#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
+#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
+#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
+#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define D3F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
+#define D3F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define D3F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
+#define D3F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
+#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
+#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
+#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
+#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
+#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
+#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
+#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
+#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
+#define D3F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
+#define D3F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
+#define D3F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
+#define D3F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
+#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
+#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
+#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
+#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
+#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
+#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
+#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
+#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
+#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
+#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
+#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
+#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
+#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
+#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
+#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
+#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
+#define D3F1_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
+#define D3F1_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
+#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
+#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
+#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
+#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
+#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
+#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
+#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
+#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
+#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
+#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
+#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
+#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
+#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
+#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
+#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
+#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
+#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
+#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
+#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
+#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
+#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
+#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
+#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define D3F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
+#define D3F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define D3F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
+#define D3F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define D3F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
+#define D3F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define D3F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
+#define D3F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define D3F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
+#define D3F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define D3F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
+#define D3F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define D3F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
+#define D3F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define D3F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
+#define D3F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define D3F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
+#define D3F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define D3F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
+#define D3F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define D3F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
+#define D3F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define D3F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
+#define D3F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define D3F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
+#define D3F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define D3F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
+#define D3F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define D3F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
+#define D3F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define D3F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
+#define D3F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define D3F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
+#define D3F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
+#define D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
+#define D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
+#define D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
+#define D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
+#define D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
+#define D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
+#define D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
+#define D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define D3F1_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
+#define D3F1_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
+#define D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
+#define D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
+#define D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
+#define D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define D3F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
+#define D3F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define D3F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
+#define D3F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define D3F1_VENDOR_ID__VENDOR_ID_MASK 0xffff
+#define D3F1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define D3F1_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
+#define D3F1_DEVICE_ID__DEVICE_ID__SHIFT 0x10
+#define D3F1_COMMAND__IO_ACCESS_EN_MASK 0x1
+#define D3F1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define D3F1_COMMAND__MEM_ACCESS_EN_MASK 0x2
+#define D3F1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define D3F1_COMMAND__BUS_MASTER_EN_MASK 0x4
+#define D3F1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define D3F1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
+#define D3F1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define D3F1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
+#define D3F1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define D3F1_COMMAND__PAL_SNOOP_EN_MASK 0x20
+#define D3F1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define D3F1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
+#define D3F1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define D3F1_COMMAND__AD_STEPPING_MASK 0x80
+#define D3F1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define D3F1_COMMAND__SERR_EN_MASK 0x100
+#define D3F1_COMMAND__SERR_EN__SHIFT 0x8
+#define D3F1_COMMAND__FAST_B2B_EN_MASK 0x200
+#define D3F1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define D3F1_COMMAND__INT_DIS_MASK 0x400
+#define D3F1_COMMAND__INT_DIS__SHIFT 0xa
+#define D3F1_STATUS__INT_STATUS_MASK 0x80000
+#define D3F1_STATUS__INT_STATUS__SHIFT 0x13
+#define D3F1_STATUS__CAP_LIST_MASK 0x100000
+#define D3F1_STATUS__CAP_LIST__SHIFT 0x14
+#define D3F1_STATUS__PCI_66_EN_MASK 0x200000
+#define D3F1_STATUS__PCI_66_EN__SHIFT 0x15
+#define D3F1_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
+#define D3F1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
+#define D3F1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
+#define D3F1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
+#define D3F1_STATUS__DEVSEL_TIMING_MASK 0x6000000
+#define D3F1_STATUS__DEVSEL_TIMING__SHIFT 0x19
+#define D3F1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
+#define D3F1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
+#define D3F1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
+#define D3F1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
+#define D3F1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
+#define D3F1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
+#define D3F1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
+#define D3F1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
+#define D3F1_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
+#define D3F1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
+#define D3F1_REVISION_ID__MINOR_REV_ID_MASK 0xf
+#define D3F1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define D3F1_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
+#define D3F1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define D3F1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
+#define D3F1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
+#define D3F1_SUB_CLASS__SUB_CLASS_MASK 0xff0000
+#define D3F1_SUB_CLASS__SUB_CLASS__SHIFT 0x10
+#define D3F1_BASE_CLASS__BASE_CLASS_MASK 0xff000000
+#define D3F1_BASE_CLASS__BASE_CLASS__SHIFT 0x18
+#define D3F1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
+#define D3F1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define D3F1_LATENCY__LATENCY_TIMER_MASK 0xff00
+#define D3F1_LATENCY__LATENCY_TIMER__SHIFT 0x8
+#define D3F1_HEADER__HEADER_TYPE_MASK 0x7f0000
+#define D3F1_HEADER__HEADER_TYPE__SHIFT 0x10
+#define D3F1_HEADER__DEVICE_TYPE_MASK 0x800000
+#define D3F1_HEADER__DEVICE_TYPE__SHIFT 0x17
+#define D3F1_BIST__BIST_COMP_MASK 0xf000000
+#define D3F1_BIST__BIST_COMP__SHIFT 0x18
+#define D3F1_BIST__BIST_STRT_MASK 0x40000000
+#define D3F1_BIST__BIST_STRT__SHIFT 0x1e
+#define D3F1_BIST__BIST_CAP_MASK 0x80000000
+#define D3F1_BIST__BIST_CAP__SHIFT 0x1f
+#define D3F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
+#define D3F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
+#define D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define D3F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
+#define D3F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
+#define D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define D3F1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
+#define D3F1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define D3F1_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
+#define D3F1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define D3F1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
+#define D3F1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define D3F1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
+#define D3F1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define D3F1_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
+#define D3F1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
+#define D3F1_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
+#define D3F1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
+#define D3F1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
+#define D3F1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
+#define D3F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
+#define D3F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
+#define D3F1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
+#define D3F1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
+#define D3F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
+#define D3F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
+#define D3F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
+#define D3F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
+#define D3F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
+#define D3F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
+#define D3F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
+#define D3F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
+#define D3F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
+#define D3F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
+#define D3F1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
+#define D3F1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define D3F1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
+#define D3F1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define D3F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
+#define D3F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define D3F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
+#define D3F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
+#define D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
+#define D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
+#define D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
+#define D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define D3F1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
+#define D3F1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define D3F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
+#define D3F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define D3F1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
+#define D3F1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define D3F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
+#define D3F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define D3F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
+#define D3F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
+#define D3F1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
+#define D3F1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
+#define D3F1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
+#define D3F1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
+#define D3F1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
+#define D3F1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
+#define D3F1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
+#define D3F1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
+#define D3F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
+#define D3F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
+#define D3F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
+#define D3F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
+#define D3F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
+#define D3F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
+#define D3F1_CAP_PTR__CAP_PTR_MASK 0xff
+#define D3F1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define D3F1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
+#define D3F1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define D3F1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
+#define D3F1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
+#define D3F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
+#define D3F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define D3F1_PMI_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F1_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F1_PMI_CAP__VERSION_MASK 0x70000
+#define D3F1_PMI_CAP__VERSION__SHIFT 0x10
+#define D3F1_PMI_CAP__PME_CLOCK_MASK 0x80000
+#define D3F1_PMI_CAP__PME_CLOCK__SHIFT 0x13
+#define D3F1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
+#define D3F1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
+#define D3F1_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
+#define D3F1_PMI_CAP__AUX_CURRENT__SHIFT 0x16
+#define D3F1_PMI_CAP__D1_SUPPORT_MASK 0x2000000
+#define D3F1_PMI_CAP__D1_SUPPORT__SHIFT 0x19
+#define D3F1_PMI_CAP__D2_SUPPORT_MASK 0x4000000
+#define D3F1_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
+#define D3F1_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
+#define D3F1_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
+#define D3F1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
+#define D3F1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define D3F1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
+#define D3F1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define D3F1_PMI_STATUS_CNTL__PME_EN_MASK 0x100
+#define D3F1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define D3F1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
+#define D3F1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define D3F1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
+#define D3F1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define D3F1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
+#define D3F1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define D3F1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
+#define D3F1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define D3F1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
+#define D3F1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define D3F1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
+#define D3F1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define D3F1_PCIE_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F1_PCIE_CAP__VERSION_MASK 0xf0000
+#define D3F1_PCIE_CAP__VERSION__SHIFT 0x10
+#define D3F1_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
+#define D3F1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
+#define D3F1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
+#define D3F1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
+#define D3F1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
+#define D3F1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
+#define D3F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
+#define D3F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define D3F1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
+#define D3F1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define D3F1_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
+#define D3F1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define D3F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
+#define D3F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define D3F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
+#define D3F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define D3F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
+#define D3F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
+#define D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
+#define D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define D3F1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
+#define D3F1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define D3F1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
+#define D3F1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define D3F1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
+#define D3F1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define D3F1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
+#define D3F1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define D3F1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
+#define D3F1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define D3F1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
+#define D3F1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define D3F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
+#define D3F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define D3F1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
+#define D3F1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define D3F1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
+#define D3F1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define D3F1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
+#define D3F1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define D3F1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
+#define D3F1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define D3F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
+#define D3F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define D3F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
+#define D3F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define D3F1_DEVICE_STATUS__CORR_ERR_MASK 0x10000
+#define D3F1_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
+#define D3F1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
+#define D3F1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
+#define D3F1_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
+#define D3F1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
+#define D3F1_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
+#define D3F1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
+#define D3F1_DEVICE_STATUS__AUX_PWR_MASK 0x100000
+#define D3F1_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
+#define D3F1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
+#define D3F1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
+#define D3F1_LINK_CAP__LINK_SPEED_MASK 0xf
+#define D3F1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define D3F1_LINK_CAP__LINK_WIDTH_MASK 0x3f0
+#define D3F1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define D3F1_LINK_CAP__PM_SUPPORT_MASK 0xc00
+#define D3F1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define D3F1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
+#define D3F1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define D3F1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
+#define D3F1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define D3F1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
+#define D3F1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define D3F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
+#define D3F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define D3F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
+#define D3F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define D3F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
+#define D3F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define D3F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
+#define D3F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define D3F1_LINK_CAP__PORT_NUMBER_MASK 0xff000000
+#define D3F1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define D3F1_LINK_CNTL__PM_CONTROL_MASK 0x3
+#define D3F1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define D3F1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
+#define D3F1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define D3F1_LINK_CNTL__LINK_DIS_MASK 0x10
+#define D3F1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define D3F1_LINK_CNTL__RETRAIN_LINK_MASK 0x20
+#define D3F1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define D3F1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
+#define D3F1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define D3F1_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
+#define D3F1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define D3F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
+#define D3F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define D3F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
+#define D3F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define D3F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
+#define D3F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define D3F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
+#define D3F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define D3F1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
+#define D3F1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
+#define D3F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
+#define D3F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
+#define D3F1_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
+#define D3F1_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
+#define D3F1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
+#define D3F1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
+#define D3F1_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
+#define D3F1_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
+#define D3F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
+#define D3F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
+#define D3F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
+#define D3F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
+#define D3F1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
+#define D3F1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define D3F1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
+#define D3F1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define D3F1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
+#define D3F1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define D3F1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
+#define D3F1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define D3F1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
+#define D3F1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define D3F1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
+#define D3F1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define D3F1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
+#define D3F1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define D3F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
+#define D3F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define D3F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
+#define D3F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define D3F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
+#define D3F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define D3F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
+#define D3F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define D3F1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
+#define D3F1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define D3F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
+#define D3F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define D3F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
+#define D3F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define D3F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
+#define D3F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define D3F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
+#define D3F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define D3F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
+#define D3F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define D3F1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
+#define D3F1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define D3F1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
+#define D3F1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define D3F1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
+#define D3F1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define D3F1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
+#define D3F1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define D3F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
+#define D3F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define D3F1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
+#define D3F1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define D3F1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
+#define D3F1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
+#define D3F1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
+#define D3F1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
+#define D3F1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
+#define D3F1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
+#define D3F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
+#define D3F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
+#define D3F1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
+#define D3F1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
+#define D3F1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
+#define D3F1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
+#define D3F1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
+#define D3F1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
+#define D3F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
+#define D3F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
+#define D3F1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
+#define D3F1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
+#define D3F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
+#define D3F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define D3F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
+#define D3F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define D3F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
+#define D3F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define D3F1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
+#define D3F1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define D3F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
+#define D3F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define D3F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
+#define D3F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
+#define D3F1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
+#define D3F1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define D3F1_ROOT_STATUS__PME_STATUS_MASK 0x10000
+#define D3F1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define D3F1_ROOT_STATUS__PME_PENDING_MASK 0x20000
+#define D3F1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define D3F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
+#define D3F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define D3F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
+#define D3F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define D3F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
+#define D3F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define D3F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
+#define D3F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define D3F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
+#define D3F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define D3F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
+#define D3F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define D3F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
+#define D3F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define D3F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
+#define D3F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define D3F1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
+#define D3F1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define D3F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
+#define D3F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define D3F1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
+#define D3F1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define D3F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
+#define D3F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define D3F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
+#define D3F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define D3F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
+#define D3F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define D3F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
+#define D3F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define D3F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
+#define D3F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define D3F1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
+#define D3F1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define D3F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
+#define D3F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define D3F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
+#define D3F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define D3F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
+#define D3F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define D3F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
+#define D3F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define D3F1_DEVICE_CNTL2__LTR_EN_MASK 0x400
+#define D3F1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define D3F1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
+#define D3F1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define D3F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
+#define D3F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define D3F1_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
+#define D3F1_DEVICE_STATUS2__RESERVED__SHIFT 0x10
+#define D3F1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
+#define D3F1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define D3F1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
+#define D3F1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define D3F1_LINK_CAP2__RESERVED_MASK 0xfffffe00
+#define D3F1_LINK_CAP2__RESERVED__SHIFT 0x9
+#define D3F1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
+#define D3F1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define D3F1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
+#define D3F1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define D3F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
+#define D3F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define D3F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
+#define D3F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define D3F1_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
+#define D3F1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define D3F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
+#define D3F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define D3F1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
+#define D3F1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define D3F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
+#define D3F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define D3F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
+#define D3F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
+#define D3F1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
+#define D3F1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
+#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
+#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
+#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
+#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
+#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
+#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
+#define D3F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
+#define D3F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
+#define D3F1_SLOT_CAP2__RESERVED_MASK 0xffffffff
+#define D3F1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define D3F1_SLOT_CNTL2__RESERVED_MASK 0xffff
+#define D3F1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define D3F1_SLOT_STATUS2__RESERVED_MASK 0xffff0000
+#define D3F1_SLOT_STATUS2__RESERVED__SHIFT 0x10
+#define D3F1_MSI_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F1_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F1_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
+#define D3F1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
+#define D3F1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
+#define D3F1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
+#define D3F1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
+#define D3F1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
+#define D3F1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
+#define D3F1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
+#define D3F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
+#define D3F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
+#define D3F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
+#define D3F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define D3F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
+#define D3F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define D3F1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
+#define D3F1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define D3F1_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
+#define D3F1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define D3F1_SSID_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F1_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
+#define D3F1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define D3F1_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
+#define D3F1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define D3F1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F1_MSI_MAP_CAP__EN_MASK 0x10000
+#define D3F1_MSI_MAP_CAP__EN__SHIFT 0x10
+#define D3F1_MSI_MAP_CAP__FIXD_MASK 0x20000
+#define D3F1_MSI_MAP_CAP__FIXD__SHIFT 0x11
+#define D3F1_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
+#define D3F1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
+#define D3F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
+#define D3F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define D3F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
+#define D3F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
+#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
+#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
+#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define D3F1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
+#define D3F1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define D3F1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
+#define D3F1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define D3F1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
+#define D3F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define D3F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
+#define D3F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define D3F1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
+#define D3F1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define D3F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
+#define D3F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
+#define D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D3F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
+#define D3F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define D3F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
+#define D3F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define D3F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
+#define D3F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
+#define D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define D3F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define D3F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define D3F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define D3F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define D3F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define D3F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define D3F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define D3F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define D3F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
+#define D3F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
+#define D3F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
+#define D3F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
+#define D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define D3F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define D3F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define D3F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define D3F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define D3F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define D3F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define D3F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define D3F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define D3F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
+#define D3F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
+#define D3F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
+#define D3F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
+#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
+#define D3F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define D3F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
+#define D3F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
+#define D3F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define D3F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
+#define D3F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define D3F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
+#define D3F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define D3F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
+#define D3F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define D3F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
+#define D3F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define D3F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
+#define D3F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define D3F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
+#define D3F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define D3F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
+#define D3F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define D3F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
+#define D3F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define D3F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
+#define D3F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define D3F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
+#define D3F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define D3F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
+#define D3F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define D3F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
+#define D3F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define D3F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
+#define D3F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define D3F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
+#define D3F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define D3F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
+#define D3F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define D3F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
+#define D3F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define D3F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
+#define D3F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define D3F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
+#define D3F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define D3F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
+#define D3F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define D3F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
+#define D3F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define D3F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
+#define D3F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define D3F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
+#define D3F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define D3F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
+#define D3F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define D3F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
+#define D3F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define D3F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
+#define D3F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define D3F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
+#define D3F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define D3F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
+#define D3F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define D3F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
+#define D3F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define D3F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
+#define D3F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define D3F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
+#define D3F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define D3F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
+#define D3F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
+#define D3F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define D3F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
+#define D3F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define D3F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
+#define D3F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define D3F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
+#define D3F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define D3F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
+#define D3F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define D3F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
+#define D3F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define D3F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
+#define D3F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define D3F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
+#define D3F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define D3F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
+#define D3F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define D3F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
+#define D3F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define D3F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
+#define D3F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define D3F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
+#define D3F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define D3F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
+#define D3F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define D3F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
+#define D3F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define D3F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
+#define D3F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define D3F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
+#define D3F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define D3F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
+#define D3F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define D3F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
+#define D3F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
+#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
+#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
+#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
+#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
+#define D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
+#define D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define D3F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
+#define D3F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define D3F1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
+#define D3F1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define D3F1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
+#define D3F1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define D3F1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
+#define D3F1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define D3F1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
+#define D3F1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define D3F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
+#define D3F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define D3F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
+#define D3F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define D3F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
+#define D3F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define D3F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
+#define D3F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
+#define D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define D3F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
+#define D3F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
+#define D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define D3F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
+#define D3F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define D3F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
+#define D3F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define D3F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
+#define D3F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define D3F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
+#define D3F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define D3F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
+#define D3F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define D3F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
+#define D3F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define D3F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
+#define D3F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define D3F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
+#define D3F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define D3F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
+#define D3F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define D3F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
+#define D3F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
+#define D3F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define D3F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
+#define D3F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define D3F1_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
+#define D3F1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define D3F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
+#define D3F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define D3F1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
+#define D3F1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
+#define D3F1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define D3F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
+#define D3F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define D3F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
+#define D3F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define D3F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
+#define D3F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define D3F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
+#define D3F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define D3F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
+#define D3F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define D3F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
+#define D3F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define D3F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
+#define D3F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define D3F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
+#define D3F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
+#define D3F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
+#define D3F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
+#define D3F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
+#define D3F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
+#define D3F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
+#define D3F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
+#define D3F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
+#define D3F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
+#define D3F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
+#define D3F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
+#define D3F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
+#define D3F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
+#define D3F1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
+#define D3F1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define D3F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
+#define D3F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define D3F1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
+#define D3F1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
+#define D3F1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
+#define D3F1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
+#define D3F1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
+#define D3F1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define D3F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
+#define D3F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define D3F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
+#define D3F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define D3F1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
+#define D3F1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define D3F1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
+#define D3F1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define D3F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
+#define D3F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define D3F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
+#define D3F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define D3F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
+#define D3F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define D3F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
+#define D3F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
+#define D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
+#define D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define D3F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
+#define D3F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define D3F2_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
+#define D3F2_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
+#define D3F2_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
+#define D3F2_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
+#define D3F2_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
+#define D3F2_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define D3F2_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
+#define D3F2_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define D3F2_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define D3F2_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define D3F2_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define D3F2_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define D3F2_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define D3F2_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define D3F2_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define D3F2_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define D3F2_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define D3F2_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define D3F2_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define D3F2_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define D3F2_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define D3F2_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define D3F2_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define D3F2_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define D3F2_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define D3F2_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define D3F2_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define D3F2_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define D3F2_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define D3F2_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define D3F2_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define D3F2_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define D3F2_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define D3F2_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define D3F2_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define D3F2_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define D3F2_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define D3F2_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define D3F2_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define D3F2_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define D3F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
+#define D3F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define D3F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
+#define D3F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define D3F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
+#define D3F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define D3F2_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
+#define D3F2_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define D3F2_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
+#define D3F2_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define D3F2_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
+#define D3F2_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define D3F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
+#define D3F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
+#define D3F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
+#define D3F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define D3F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
+#define D3F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define D3F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
+#define D3F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define D3F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
+#define D3F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define D3F2_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
+#define D3F2_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define D3F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
+#define D3F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define D3F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
+#define D3F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define D3F2_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
+#define D3F2_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define D3F2_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
+#define D3F2_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define D3F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
+#define D3F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define D3F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
+#define D3F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
+#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
+#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
+#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define D3F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
+#define D3F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
+#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
+#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
+#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define D3F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
+#define D3F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define D3F2_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
+#define D3F2_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
+#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
+#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
+#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
+#define D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
+#define D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
+#define D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
+#define D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
+#define D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
+#define D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
+#define D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
+#define D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
+#define D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
+#define D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
+#define D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
+#define D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
+#define D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
+#define D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
+#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
+#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
+#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
+#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
+#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
+#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
+#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define D3F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
+#define D3F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define D3F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
+#define D3F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define D3F2_PCIE_FC_P__PD_CREDITS_MASK 0xff
+#define D3F2_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define D3F2_PCIE_FC_P__PH_CREDITS_MASK 0xff00
+#define D3F2_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
+#define D3F2_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
+#define D3F2_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define D3F2_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
+#define D3F2_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
+#define D3F2_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
+#define D3F2_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define D3F2_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
+#define D3F2_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
+#define D3F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
+#define D3F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define D3F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
+#define D3F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define D3F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
+#define D3F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define D3F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
+#define D3F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define D3F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
+#define D3F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define D3F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
+#define D3F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define D3F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
+#define D3F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
+#define D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
+#define D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define D3F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
+#define D3F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define D3F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
+#define D3F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define D3F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
+#define D3F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define D3F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
+#define D3F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define D3F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
+#define D3F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define D3F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
+#define D3F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define D3F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
+#define D3F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
+#define D3F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
+#define D3F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
+#define D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
+#define D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define D3F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
+#define D3F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
+#define D3F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define D3F2_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
+#define D3F2_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define D3F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
+#define D3F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define D3F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
+#define D3F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
+#define D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
+#define D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
+#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
+#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
+#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
+#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
+#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
+#define D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
+#define D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
+#define D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
+#define D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
+#define D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
+#define D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
+#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
+#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
+#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
+#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
+#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
+#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
+#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
+#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
+#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
+#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
+#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define D3F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
+#define D3F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define D3F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
+#define D3F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define D3F2_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
+#define D3F2_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define D3F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
+#define D3F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define D3F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
+#define D3F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define D3F2_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
+#define D3F2_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define D3F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
+#define D3F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define D3F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
+#define D3F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define D3F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
+#define D3F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define D3F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
+#define D3F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define D3F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
+#define D3F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define D3F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
+#define D3F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define D3F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
+#define D3F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define D3F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
+#define D3F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define D3F2_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
+#define D3F2_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define D3F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
+#define D3F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define D3F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
+#define D3F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define D3F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
+#define D3F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define D3F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
+#define D3F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define D3F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
+#define D3F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define D3F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
+#define D3F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define D3F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
+#define D3F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define D3F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
+#define D3F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define D3F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
+#define D3F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define D3F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
+#define D3F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define D3F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
+#define D3F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
+#define D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
+#define D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
+#define D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define D3F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
+#define D3F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define D3F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
+#define D3F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
+#define D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
+#define D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define D3F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
+#define D3F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
+#define D3F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
+#define D3F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define D3F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
+#define D3F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define D3F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
+#define D3F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
+#define D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define D3F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
+#define D3F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define D3F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
+#define D3F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define D3F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
+#define D3F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define D3F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
+#define D3F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define D3F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
+#define D3F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define D3F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
+#define D3F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
+#define D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
+#define D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define D3F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
+#define D3F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define D3F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
+#define D3F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define D3F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
+#define D3F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
+#define D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
+#define D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define D3F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
+#define D3F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define D3F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
+#define D3F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define D3F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
+#define D3F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define D3F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
+#define D3F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
+#define D3F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
+#define D3F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
+#define D3F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
+#define D3F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
+#define D3F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
+#define D3F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
+#define D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
+#define D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define D3F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
+#define D3F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define D3F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
+#define D3F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
+#define D3F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
+#define D3F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define D3F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
+#define D3F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define D3F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
+#define D3F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define D3F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
+#define D3F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define D3F2_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
+#define D3F2_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
+#define D3F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
+#define D3F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define D3F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
+#define D3F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define D3F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
+#define D3F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
+#define D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
+#define D3F2_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
+#define D3F2_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
+#define D3F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
+#define D3F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define D3F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
+#define D3F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define D3F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
+#define D3F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
+#define D3F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
+#define D3F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define D3F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
+#define D3F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
+#define D3F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
+#define D3F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
+#define D3F2_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
+#define D3F2_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define D3F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
+#define D3F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define D3F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
+#define D3F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
+#define D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
+#define D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
+#define D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
+#define D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
+#define D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
+#define D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
+#define D3F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
+#define D3F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define D3F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
+#define D3F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
+#define D3F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
+#define D3F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define D3F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
+#define D3F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define D3F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
+#define D3F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define D3F2_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
+#define D3F2_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
+#define D3F2_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
+#define D3F2_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
+#define D3F2_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
+#define D3F2_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
+#define D3F2_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
+#define D3F2_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
+#define D3F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
+#define D3F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
+#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
+#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
+#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
+#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
+#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
+#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
+#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
+#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
+#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
+#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
+#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
+#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
+#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
+#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
+#define D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
+#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
+#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
+#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
+#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
+#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define D3F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
+#define D3F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
+#define D3F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
+#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
+#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
+#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
+#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define D3F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
+#define D3F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define D3F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
+#define D3F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
+#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
+#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
+#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
+#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
+#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
+#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
+#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
+#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
+#define D3F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
+#define D3F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
+#define D3F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
+#define D3F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
+#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
+#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
+#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
+#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
+#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
+#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
+#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
+#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
+#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
+#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
+#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
+#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
+#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
+#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
+#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
+#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
+#define D3F2_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
+#define D3F2_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
+#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
+#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
+#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
+#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
+#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
+#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
+#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
+#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
+#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
+#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
+#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
+#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
+#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
+#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
+#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
+#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
+#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
+#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
+#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
+#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
+#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
+#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
+#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define D3F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
+#define D3F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define D3F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
+#define D3F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define D3F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
+#define D3F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define D3F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
+#define D3F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define D3F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
+#define D3F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define D3F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
+#define D3F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define D3F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
+#define D3F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define D3F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
+#define D3F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define D3F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
+#define D3F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define D3F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
+#define D3F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define D3F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
+#define D3F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define D3F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
+#define D3F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define D3F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
+#define D3F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define D3F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
+#define D3F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define D3F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
+#define D3F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define D3F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
+#define D3F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define D3F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
+#define D3F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
+#define D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
+#define D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
+#define D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
+#define D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
+#define D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
+#define D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
+#define D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
+#define D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define D3F2_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
+#define D3F2_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
+#define D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
+#define D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
+#define D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
+#define D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define D3F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
+#define D3F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define D3F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
+#define D3F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define D3F2_VENDOR_ID__VENDOR_ID_MASK 0xffff
+#define D3F2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define D3F2_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
+#define D3F2_DEVICE_ID__DEVICE_ID__SHIFT 0x10
+#define D3F2_COMMAND__IO_ACCESS_EN_MASK 0x1
+#define D3F2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define D3F2_COMMAND__MEM_ACCESS_EN_MASK 0x2
+#define D3F2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define D3F2_COMMAND__BUS_MASTER_EN_MASK 0x4
+#define D3F2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define D3F2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
+#define D3F2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define D3F2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
+#define D3F2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define D3F2_COMMAND__PAL_SNOOP_EN_MASK 0x20
+#define D3F2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define D3F2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
+#define D3F2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define D3F2_COMMAND__AD_STEPPING_MASK 0x80
+#define D3F2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define D3F2_COMMAND__SERR_EN_MASK 0x100
+#define D3F2_COMMAND__SERR_EN__SHIFT 0x8
+#define D3F2_COMMAND__FAST_B2B_EN_MASK 0x200
+#define D3F2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define D3F2_COMMAND__INT_DIS_MASK 0x400
+#define D3F2_COMMAND__INT_DIS__SHIFT 0xa
+#define D3F2_STATUS__INT_STATUS_MASK 0x80000
+#define D3F2_STATUS__INT_STATUS__SHIFT 0x13
+#define D3F2_STATUS__CAP_LIST_MASK 0x100000
+#define D3F2_STATUS__CAP_LIST__SHIFT 0x14
+#define D3F2_STATUS__PCI_66_EN_MASK 0x200000
+#define D3F2_STATUS__PCI_66_EN__SHIFT 0x15
+#define D3F2_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
+#define D3F2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
+#define D3F2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
+#define D3F2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
+#define D3F2_STATUS__DEVSEL_TIMING_MASK 0x6000000
+#define D3F2_STATUS__DEVSEL_TIMING__SHIFT 0x19
+#define D3F2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
+#define D3F2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
+#define D3F2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
+#define D3F2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
+#define D3F2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
+#define D3F2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
+#define D3F2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
+#define D3F2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
+#define D3F2_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
+#define D3F2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
+#define D3F2_REVISION_ID__MINOR_REV_ID_MASK 0xf
+#define D3F2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define D3F2_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
+#define D3F2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define D3F2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
+#define D3F2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
+#define D3F2_SUB_CLASS__SUB_CLASS_MASK 0xff0000
+#define D3F2_SUB_CLASS__SUB_CLASS__SHIFT 0x10
+#define D3F2_BASE_CLASS__BASE_CLASS_MASK 0xff000000
+#define D3F2_BASE_CLASS__BASE_CLASS__SHIFT 0x18
+#define D3F2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
+#define D3F2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define D3F2_LATENCY__LATENCY_TIMER_MASK 0xff00
+#define D3F2_LATENCY__LATENCY_TIMER__SHIFT 0x8
+#define D3F2_HEADER__HEADER_TYPE_MASK 0x7f0000
+#define D3F2_HEADER__HEADER_TYPE__SHIFT 0x10
+#define D3F2_HEADER__DEVICE_TYPE_MASK 0x800000
+#define D3F2_HEADER__DEVICE_TYPE__SHIFT 0x17
+#define D3F2_BIST__BIST_COMP_MASK 0xf000000
+#define D3F2_BIST__BIST_COMP__SHIFT 0x18
+#define D3F2_BIST__BIST_STRT_MASK 0x40000000
+#define D3F2_BIST__BIST_STRT__SHIFT 0x1e
+#define D3F2_BIST__BIST_CAP_MASK 0x80000000
+#define D3F2_BIST__BIST_CAP__SHIFT 0x1f
+#define D3F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
+#define D3F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
+#define D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define D3F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
+#define D3F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
+#define D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define D3F2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
+#define D3F2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define D3F2_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
+#define D3F2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define D3F2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
+#define D3F2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define D3F2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
+#define D3F2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define D3F2_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
+#define D3F2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
+#define D3F2_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
+#define D3F2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
+#define D3F2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
+#define D3F2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
+#define D3F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
+#define D3F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
+#define D3F2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
+#define D3F2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
+#define D3F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
+#define D3F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
+#define D3F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
+#define D3F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
+#define D3F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
+#define D3F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
+#define D3F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
+#define D3F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
+#define D3F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
+#define D3F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
+#define D3F2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
+#define D3F2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define D3F2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
+#define D3F2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define D3F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
+#define D3F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define D3F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
+#define D3F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
+#define D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
+#define D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
+#define D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
+#define D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define D3F2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
+#define D3F2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define D3F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
+#define D3F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define D3F2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
+#define D3F2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define D3F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
+#define D3F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define D3F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
+#define D3F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
+#define D3F2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
+#define D3F2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
+#define D3F2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
+#define D3F2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
+#define D3F2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
+#define D3F2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
+#define D3F2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
+#define D3F2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
+#define D3F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
+#define D3F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
+#define D3F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
+#define D3F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
+#define D3F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
+#define D3F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
+#define D3F2_CAP_PTR__CAP_PTR_MASK 0xff
+#define D3F2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define D3F2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
+#define D3F2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define D3F2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
+#define D3F2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
+#define D3F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
+#define D3F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define D3F2_PMI_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F2_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F2_PMI_CAP__VERSION_MASK 0x70000
+#define D3F2_PMI_CAP__VERSION__SHIFT 0x10
+#define D3F2_PMI_CAP__PME_CLOCK_MASK 0x80000
+#define D3F2_PMI_CAP__PME_CLOCK__SHIFT 0x13
+#define D3F2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
+#define D3F2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
+#define D3F2_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
+#define D3F2_PMI_CAP__AUX_CURRENT__SHIFT 0x16
+#define D3F2_PMI_CAP__D1_SUPPORT_MASK 0x2000000
+#define D3F2_PMI_CAP__D1_SUPPORT__SHIFT 0x19
+#define D3F2_PMI_CAP__D2_SUPPORT_MASK 0x4000000
+#define D3F2_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
+#define D3F2_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
+#define D3F2_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
+#define D3F2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
+#define D3F2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define D3F2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
+#define D3F2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define D3F2_PMI_STATUS_CNTL__PME_EN_MASK 0x100
+#define D3F2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define D3F2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
+#define D3F2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define D3F2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
+#define D3F2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define D3F2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
+#define D3F2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define D3F2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
+#define D3F2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define D3F2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
+#define D3F2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define D3F2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
+#define D3F2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define D3F2_PCIE_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F2_PCIE_CAP__VERSION_MASK 0xf0000
+#define D3F2_PCIE_CAP__VERSION__SHIFT 0x10
+#define D3F2_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
+#define D3F2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
+#define D3F2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
+#define D3F2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
+#define D3F2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
+#define D3F2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
+#define D3F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
+#define D3F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define D3F2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
+#define D3F2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define D3F2_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
+#define D3F2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define D3F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
+#define D3F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define D3F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
+#define D3F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define D3F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
+#define D3F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
+#define D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
+#define D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define D3F2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
+#define D3F2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define D3F2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
+#define D3F2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define D3F2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
+#define D3F2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define D3F2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
+#define D3F2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define D3F2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
+#define D3F2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define D3F2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
+#define D3F2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define D3F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
+#define D3F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define D3F2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
+#define D3F2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define D3F2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
+#define D3F2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define D3F2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
+#define D3F2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define D3F2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
+#define D3F2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define D3F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
+#define D3F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define D3F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
+#define D3F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define D3F2_DEVICE_STATUS__CORR_ERR_MASK 0x10000
+#define D3F2_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
+#define D3F2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
+#define D3F2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
+#define D3F2_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
+#define D3F2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
+#define D3F2_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
+#define D3F2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
+#define D3F2_DEVICE_STATUS__AUX_PWR_MASK 0x100000
+#define D3F2_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
+#define D3F2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
+#define D3F2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
+#define D3F2_LINK_CAP__LINK_SPEED_MASK 0xf
+#define D3F2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define D3F2_LINK_CAP__LINK_WIDTH_MASK 0x3f0
+#define D3F2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define D3F2_LINK_CAP__PM_SUPPORT_MASK 0xc00
+#define D3F2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define D3F2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
+#define D3F2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define D3F2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
+#define D3F2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define D3F2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
+#define D3F2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define D3F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
+#define D3F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define D3F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
+#define D3F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define D3F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
+#define D3F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define D3F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
+#define D3F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define D3F2_LINK_CAP__PORT_NUMBER_MASK 0xff000000
+#define D3F2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define D3F2_LINK_CNTL__PM_CONTROL_MASK 0x3
+#define D3F2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define D3F2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
+#define D3F2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define D3F2_LINK_CNTL__LINK_DIS_MASK 0x10
+#define D3F2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define D3F2_LINK_CNTL__RETRAIN_LINK_MASK 0x20
+#define D3F2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define D3F2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
+#define D3F2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define D3F2_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
+#define D3F2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define D3F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
+#define D3F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define D3F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
+#define D3F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define D3F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
+#define D3F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define D3F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
+#define D3F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define D3F2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
+#define D3F2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
+#define D3F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
+#define D3F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
+#define D3F2_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
+#define D3F2_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
+#define D3F2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
+#define D3F2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
+#define D3F2_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
+#define D3F2_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
+#define D3F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
+#define D3F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
+#define D3F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
+#define D3F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
+#define D3F2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
+#define D3F2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define D3F2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
+#define D3F2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define D3F2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
+#define D3F2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define D3F2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
+#define D3F2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define D3F2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
+#define D3F2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define D3F2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
+#define D3F2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define D3F2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
+#define D3F2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define D3F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
+#define D3F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define D3F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
+#define D3F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define D3F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
+#define D3F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define D3F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
+#define D3F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define D3F2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
+#define D3F2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define D3F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
+#define D3F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define D3F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
+#define D3F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define D3F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
+#define D3F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define D3F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
+#define D3F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define D3F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
+#define D3F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define D3F2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
+#define D3F2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define D3F2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
+#define D3F2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define D3F2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
+#define D3F2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define D3F2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
+#define D3F2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define D3F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
+#define D3F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define D3F2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
+#define D3F2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define D3F2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
+#define D3F2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
+#define D3F2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
+#define D3F2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
+#define D3F2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
+#define D3F2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
+#define D3F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
+#define D3F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
+#define D3F2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
+#define D3F2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
+#define D3F2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
+#define D3F2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
+#define D3F2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
+#define D3F2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
+#define D3F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
+#define D3F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
+#define D3F2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
+#define D3F2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
+#define D3F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
+#define D3F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define D3F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
+#define D3F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define D3F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
+#define D3F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define D3F2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
+#define D3F2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define D3F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
+#define D3F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define D3F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
+#define D3F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
+#define D3F2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
+#define D3F2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define D3F2_ROOT_STATUS__PME_STATUS_MASK 0x10000
+#define D3F2_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define D3F2_ROOT_STATUS__PME_PENDING_MASK 0x20000
+#define D3F2_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define D3F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
+#define D3F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define D3F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
+#define D3F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define D3F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
+#define D3F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define D3F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
+#define D3F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define D3F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
+#define D3F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define D3F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
+#define D3F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define D3F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
+#define D3F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define D3F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
+#define D3F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define D3F2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
+#define D3F2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define D3F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
+#define D3F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define D3F2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
+#define D3F2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define D3F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
+#define D3F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define D3F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
+#define D3F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define D3F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
+#define D3F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define D3F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
+#define D3F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define D3F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
+#define D3F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define D3F2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
+#define D3F2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define D3F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
+#define D3F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define D3F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
+#define D3F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define D3F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
+#define D3F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define D3F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
+#define D3F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define D3F2_DEVICE_CNTL2__LTR_EN_MASK 0x400
+#define D3F2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define D3F2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
+#define D3F2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define D3F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
+#define D3F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define D3F2_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
+#define D3F2_DEVICE_STATUS2__RESERVED__SHIFT 0x10
+#define D3F2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
+#define D3F2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define D3F2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
+#define D3F2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define D3F2_LINK_CAP2__RESERVED_MASK 0xfffffe00
+#define D3F2_LINK_CAP2__RESERVED__SHIFT 0x9
+#define D3F2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
+#define D3F2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define D3F2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
+#define D3F2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define D3F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
+#define D3F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define D3F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
+#define D3F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define D3F2_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
+#define D3F2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define D3F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
+#define D3F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define D3F2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
+#define D3F2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define D3F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
+#define D3F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define D3F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
+#define D3F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
+#define D3F2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
+#define D3F2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
+#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
+#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
+#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
+#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
+#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
+#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
+#define D3F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
+#define D3F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
+#define D3F2_SLOT_CAP2__RESERVED_MASK 0xffffffff
+#define D3F2_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define D3F2_SLOT_CNTL2__RESERVED_MASK 0xffff
+#define D3F2_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define D3F2_SLOT_STATUS2__RESERVED_MASK 0xffff0000
+#define D3F2_SLOT_STATUS2__RESERVED__SHIFT 0x10
+#define D3F2_MSI_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F2_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F2_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
+#define D3F2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
+#define D3F2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
+#define D3F2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
+#define D3F2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
+#define D3F2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
+#define D3F2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
+#define D3F2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
+#define D3F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
+#define D3F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
+#define D3F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
+#define D3F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define D3F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
+#define D3F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define D3F2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
+#define D3F2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define D3F2_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
+#define D3F2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define D3F2_SSID_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F2_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
+#define D3F2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define D3F2_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
+#define D3F2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define D3F2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F2_MSI_MAP_CAP__EN_MASK 0x10000
+#define D3F2_MSI_MAP_CAP__EN__SHIFT 0x10
+#define D3F2_MSI_MAP_CAP__FIXD_MASK 0x20000
+#define D3F2_MSI_MAP_CAP__FIXD__SHIFT 0x11
+#define D3F2_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
+#define D3F2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
+#define D3F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
+#define D3F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define D3F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
+#define D3F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
+#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
+#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
+#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define D3F2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
+#define D3F2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define D3F2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
+#define D3F2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define D3F2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
+#define D3F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define D3F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
+#define D3F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define D3F2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
+#define D3F2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define D3F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
+#define D3F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
+#define D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D3F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
+#define D3F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define D3F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
+#define D3F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define D3F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
+#define D3F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
+#define D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define D3F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define D3F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define D3F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define D3F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define D3F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define D3F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define D3F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define D3F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define D3F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
+#define D3F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
+#define D3F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
+#define D3F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
+#define D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define D3F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define D3F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define D3F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define D3F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define D3F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define D3F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define D3F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define D3F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define D3F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
+#define D3F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
+#define D3F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
+#define D3F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
+#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
+#define D3F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define D3F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
+#define D3F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
+#define D3F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define D3F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
+#define D3F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define D3F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
+#define D3F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define D3F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
+#define D3F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define D3F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
+#define D3F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define D3F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
+#define D3F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define D3F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
+#define D3F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define D3F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
+#define D3F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define D3F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
+#define D3F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define D3F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
+#define D3F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define D3F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
+#define D3F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define D3F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
+#define D3F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define D3F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
+#define D3F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define D3F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
+#define D3F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define D3F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
+#define D3F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define D3F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
+#define D3F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define D3F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
+#define D3F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define D3F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
+#define D3F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define D3F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
+#define D3F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define D3F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
+#define D3F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define D3F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
+#define D3F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define D3F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
+#define D3F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define D3F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
+#define D3F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define D3F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
+#define D3F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define D3F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
+#define D3F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define D3F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
+#define D3F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define D3F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
+#define D3F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define D3F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
+#define D3F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define D3F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
+#define D3F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define D3F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
+#define D3F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define D3F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
+#define D3F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define D3F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
+#define D3F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
+#define D3F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define D3F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
+#define D3F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define D3F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
+#define D3F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define D3F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
+#define D3F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define D3F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
+#define D3F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define D3F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
+#define D3F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define D3F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
+#define D3F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define D3F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
+#define D3F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define D3F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
+#define D3F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define D3F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
+#define D3F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define D3F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
+#define D3F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define D3F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
+#define D3F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define D3F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
+#define D3F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define D3F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
+#define D3F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define D3F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
+#define D3F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define D3F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
+#define D3F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define D3F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
+#define D3F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define D3F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
+#define D3F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
+#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
+#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
+#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
+#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
+#define D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
+#define D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define D3F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
+#define D3F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define D3F2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
+#define D3F2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define D3F2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
+#define D3F2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define D3F2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
+#define D3F2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define D3F2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
+#define D3F2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define D3F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
+#define D3F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define D3F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
+#define D3F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define D3F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
+#define D3F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define D3F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
+#define D3F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
+#define D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define D3F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
+#define D3F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
+#define D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define D3F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
+#define D3F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define D3F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
+#define D3F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define D3F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
+#define D3F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define D3F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
+#define D3F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define D3F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
+#define D3F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define D3F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
+#define D3F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define D3F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
+#define D3F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define D3F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
+#define D3F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define D3F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
+#define D3F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define D3F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
+#define D3F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
+#define D3F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define D3F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
+#define D3F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define D3F2_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
+#define D3F2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define D3F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
+#define D3F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define D3F2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
+#define D3F2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
+#define D3F2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define D3F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
+#define D3F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define D3F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
+#define D3F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define D3F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
+#define D3F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define D3F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
+#define D3F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define D3F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
+#define D3F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define D3F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
+#define D3F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define D3F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
+#define D3F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define D3F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
+#define D3F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
+#define D3F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
+#define D3F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
+#define D3F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
+#define D3F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
+#define D3F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
+#define D3F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
+#define D3F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
+#define D3F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
+#define D3F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
+#define D3F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
+#define D3F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
+#define D3F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
+#define D3F2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
+#define D3F2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define D3F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
+#define D3F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define D3F2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
+#define D3F2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
+#define D3F2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
+#define D3F2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
+#define D3F2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
+#define D3F2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define D3F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
+#define D3F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define D3F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
+#define D3F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define D3F2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
+#define D3F2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define D3F2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
+#define D3F2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define D3F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
+#define D3F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define D3F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
+#define D3F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define D3F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
+#define D3F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define D3F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
+#define D3F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
+#define D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
+#define D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define D3F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
+#define D3F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define D3F3_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
+#define D3F3_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
+#define D3F3_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
+#define D3F3_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
+#define D3F3_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
+#define D3F3_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define D3F3_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
+#define D3F3_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define D3F3_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define D3F3_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define D3F3_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define D3F3_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define D3F3_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define D3F3_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define D3F3_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define D3F3_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define D3F3_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define D3F3_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define D3F3_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define D3F3_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define D3F3_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define D3F3_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define D3F3_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define D3F3_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define D3F3_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define D3F3_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define D3F3_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define D3F3_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define D3F3_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define D3F3_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define D3F3_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define D3F3_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define D3F3_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define D3F3_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define D3F3_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define D3F3_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define D3F3_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define D3F3_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define D3F3_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define D3F3_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define D3F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
+#define D3F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define D3F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
+#define D3F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define D3F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
+#define D3F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define D3F3_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
+#define D3F3_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define D3F3_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
+#define D3F3_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define D3F3_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
+#define D3F3_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define D3F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
+#define D3F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
+#define D3F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
+#define D3F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define D3F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
+#define D3F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define D3F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
+#define D3F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define D3F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
+#define D3F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define D3F3_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
+#define D3F3_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define D3F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
+#define D3F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define D3F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
+#define D3F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define D3F3_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
+#define D3F3_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define D3F3_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
+#define D3F3_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define D3F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
+#define D3F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define D3F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
+#define D3F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
+#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
+#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
+#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define D3F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
+#define D3F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
+#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
+#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
+#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define D3F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
+#define D3F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define D3F3_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
+#define D3F3_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
+#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
+#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
+#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
+#define D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
+#define D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
+#define D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
+#define D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
+#define D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
+#define D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
+#define D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
+#define D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
+#define D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
+#define D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
+#define D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
+#define D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
+#define D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
+#define D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
+#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
+#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
+#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
+#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
+#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
+#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
+#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define D3F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
+#define D3F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define D3F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
+#define D3F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define D3F3_PCIE_FC_P__PD_CREDITS_MASK 0xff
+#define D3F3_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define D3F3_PCIE_FC_P__PH_CREDITS_MASK 0xff00
+#define D3F3_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
+#define D3F3_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
+#define D3F3_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define D3F3_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
+#define D3F3_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
+#define D3F3_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
+#define D3F3_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define D3F3_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
+#define D3F3_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
+#define D3F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
+#define D3F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define D3F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
+#define D3F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define D3F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
+#define D3F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define D3F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
+#define D3F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define D3F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
+#define D3F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define D3F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
+#define D3F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define D3F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
+#define D3F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
+#define D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
+#define D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define D3F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
+#define D3F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define D3F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
+#define D3F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define D3F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
+#define D3F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define D3F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
+#define D3F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define D3F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
+#define D3F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define D3F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
+#define D3F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define D3F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
+#define D3F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
+#define D3F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
+#define D3F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
+#define D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
+#define D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define D3F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
+#define D3F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
+#define D3F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define D3F3_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
+#define D3F3_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define D3F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
+#define D3F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define D3F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
+#define D3F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
+#define D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
+#define D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
+#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
+#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
+#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
+#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
+#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
+#define D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
+#define D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
+#define D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
+#define D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
+#define D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
+#define D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
+#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
+#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
+#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
+#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
+#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
+#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
+#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
+#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
+#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
+#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
+#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define D3F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
+#define D3F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define D3F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
+#define D3F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define D3F3_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
+#define D3F3_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define D3F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
+#define D3F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define D3F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
+#define D3F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define D3F3_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
+#define D3F3_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define D3F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
+#define D3F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define D3F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
+#define D3F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define D3F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
+#define D3F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define D3F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
+#define D3F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define D3F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
+#define D3F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define D3F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
+#define D3F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define D3F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
+#define D3F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define D3F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
+#define D3F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define D3F3_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
+#define D3F3_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define D3F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
+#define D3F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define D3F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
+#define D3F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define D3F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
+#define D3F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define D3F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
+#define D3F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define D3F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
+#define D3F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define D3F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
+#define D3F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define D3F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
+#define D3F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define D3F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
+#define D3F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define D3F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
+#define D3F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define D3F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
+#define D3F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define D3F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
+#define D3F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
+#define D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
+#define D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
+#define D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define D3F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
+#define D3F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define D3F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
+#define D3F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
+#define D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
+#define D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define D3F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
+#define D3F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
+#define D3F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
+#define D3F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define D3F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
+#define D3F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define D3F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
+#define D3F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
+#define D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define D3F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
+#define D3F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define D3F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
+#define D3F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define D3F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
+#define D3F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define D3F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
+#define D3F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define D3F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
+#define D3F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define D3F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
+#define D3F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
+#define D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
+#define D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define D3F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
+#define D3F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define D3F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
+#define D3F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define D3F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
+#define D3F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
+#define D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
+#define D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define D3F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
+#define D3F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define D3F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
+#define D3F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define D3F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
+#define D3F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define D3F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
+#define D3F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
+#define D3F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
+#define D3F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
+#define D3F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
+#define D3F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
+#define D3F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
+#define D3F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
+#define D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
+#define D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define D3F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
+#define D3F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define D3F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
+#define D3F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
+#define D3F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
+#define D3F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define D3F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
+#define D3F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define D3F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
+#define D3F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define D3F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
+#define D3F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define D3F3_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
+#define D3F3_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
+#define D3F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
+#define D3F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define D3F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
+#define D3F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define D3F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
+#define D3F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
+#define D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
+#define D3F3_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
+#define D3F3_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
+#define D3F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
+#define D3F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define D3F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
+#define D3F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define D3F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
+#define D3F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
+#define D3F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
+#define D3F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define D3F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
+#define D3F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
+#define D3F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
+#define D3F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
+#define D3F3_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
+#define D3F3_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define D3F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
+#define D3F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define D3F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
+#define D3F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
+#define D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
+#define D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
+#define D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
+#define D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
+#define D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
+#define D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
+#define D3F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
+#define D3F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define D3F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
+#define D3F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
+#define D3F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
+#define D3F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define D3F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
+#define D3F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define D3F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
+#define D3F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define D3F3_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
+#define D3F3_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
+#define D3F3_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
+#define D3F3_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
+#define D3F3_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
+#define D3F3_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
+#define D3F3_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
+#define D3F3_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
+#define D3F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
+#define D3F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
+#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
+#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
+#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
+#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
+#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
+#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
+#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
+#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
+#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
+#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
+#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
+#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
+#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
+#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
+#define D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
+#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
+#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
+#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
+#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
+#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define D3F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
+#define D3F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
+#define D3F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
+#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
+#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
+#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
+#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define D3F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
+#define D3F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define D3F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
+#define D3F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
+#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
+#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
+#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
+#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
+#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
+#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
+#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
+#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
+#define D3F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
+#define D3F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
+#define D3F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
+#define D3F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
+#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
+#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
+#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
+#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
+#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
+#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
+#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
+#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
+#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
+#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
+#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
+#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
+#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
+#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
+#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
+#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
+#define D3F3_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
+#define D3F3_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
+#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
+#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
+#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
+#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
+#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
+#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
+#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
+#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
+#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
+#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
+#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
+#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
+#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
+#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
+#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
+#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
+#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
+#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
+#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
+#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
+#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
+#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
+#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define D3F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
+#define D3F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define D3F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
+#define D3F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define D3F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
+#define D3F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define D3F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
+#define D3F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define D3F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
+#define D3F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define D3F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
+#define D3F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define D3F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
+#define D3F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define D3F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
+#define D3F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define D3F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
+#define D3F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define D3F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
+#define D3F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define D3F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
+#define D3F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define D3F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
+#define D3F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define D3F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
+#define D3F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define D3F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
+#define D3F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define D3F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
+#define D3F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define D3F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
+#define D3F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define D3F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
+#define D3F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
+#define D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
+#define D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
+#define D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
+#define D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
+#define D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
+#define D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
+#define D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
+#define D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define D3F3_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
+#define D3F3_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
+#define D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
+#define D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
+#define D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
+#define D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define D3F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
+#define D3F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define D3F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
+#define D3F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define D3F3_VENDOR_ID__VENDOR_ID_MASK 0xffff
+#define D3F3_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define D3F3_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
+#define D3F3_DEVICE_ID__DEVICE_ID__SHIFT 0x10
+#define D3F3_COMMAND__IO_ACCESS_EN_MASK 0x1
+#define D3F3_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define D3F3_COMMAND__MEM_ACCESS_EN_MASK 0x2
+#define D3F3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define D3F3_COMMAND__BUS_MASTER_EN_MASK 0x4
+#define D3F3_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define D3F3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
+#define D3F3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define D3F3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
+#define D3F3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define D3F3_COMMAND__PAL_SNOOP_EN_MASK 0x20
+#define D3F3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define D3F3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
+#define D3F3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define D3F3_COMMAND__AD_STEPPING_MASK 0x80
+#define D3F3_COMMAND__AD_STEPPING__SHIFT 0x7
+#define D3F3_COMMAND__SERR_EN_MASK 0x100
+#define D3F3_COMMAND__SERR_EN__SHIFT 0x8
+#define D3F3_COMMAND__FAST_B2B_EN_MASK 0x200
+#define D3F3_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define D3F3_COMMAND__INT_DIS_MASK 0x400
+#define D3F3_COMMAND__INT_DIS__SHIFT 0xa
+#define D3F3_STATUS__INT_STATUS_MASK 0x80000
+#define D3F3_STATUS__INT_STATUS__SHIFT 0x13
+#define D3F3_STATUS__CAP_LIST_MASK 0x100000
+#define D3F3_STATUS__CAP_LIST__SHIFT 0x14
+#define D3F3_STATUS__PCI_66_EN_MASK 0x200000
+#define D3F3_STATUS__PCI_66_EN__SHIFT 0x15
+#define D3F3_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
+#define D3F3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
+#define D3F3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
+#define D3F3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
+#define D3F3_STATUS__DEVSEL_TIMING_MASK 0x6000000
+#define D3F3_STATUS__DEVSEL_TIMING__SHIFT 0x19
+#define D3F3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
+#define D3F3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
+#define D3F3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
+#define D3F3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
+#define D3F3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
+#define D3F3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
+#define D3F3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
+#define D3F3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
+#define D3F3_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
+#define D3F3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
+#define D3F3_REVISION_ID__MINOR_REV_ID_MASK 0xf
+#define D3F3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define D3F3_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
+#define D3F3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define D3F3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
+#define D3F3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
+#define D3F3_SUB_CLASS__SUB_CLASS_MASK 0xff0000
+#define D3F3_SUB_CLASS__SUB_CLASS__SHIFT 0x10
+#define D3F3_BASE_CLASS__BASE_CLASS_MASK 0xff000000
+#define D3F3_BASE_CLASS__BASE_CLASS__SHIFT 0x18
+#define D3F3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
+#define D3F3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define D3F3_LATENCY__LATENCY_TIMER_MASK 0xff00
+#define D3F3_LATENCY__LATENCY_TIMER__SHIFT 0x8
+#define D3F3_HEADER__HEADER_TYPE_MASK 0x7f0000
+#define D3F3_HEADER__HEADER_TYPE__SHIFT 0x10
+#define D3F3_HEADER__DEVICE_TYPE_MASK 0x800000
+#define D3F3_HEADER__DEVICE_TYPE__SHIFT 0x17
+#define D3F3_BIST__BIST_COMP_MASK 0xf000000
+#define D3F3_BIST__BIST_COMP__SHIFT 0x18
+#define D3F3_BIST__BIST_STRT_MASK 0x40000000
+#define D3F3_BIST__BIST_STRT__SHIFT 0x1e
+#define D3F3_BIST__BIST_CAP_MASK 0x80000000
+#define D3F3_BIST__BIST_CAP__SHIFT 0x1f
+#define D3F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
+#define D3F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
+#define D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define D3F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
+#define D3F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
+#define D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define D3F3_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
+#define D3F3_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define D3F3_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
+#define D3F3_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define D3F3_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
+#define D3F3_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define D3F3_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
+#define D3F3_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define D3F3_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
+#define D3F3_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
+#define D3F3_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
+#define D3F3_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
+#define D3F3_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
+#define D3F3_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
+#define D3F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
+#define D3F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
+#define D3F3_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
+#define D3F3_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
+#define D3F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
+#define D3F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
+#define D3F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
+#define D3F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
+#define D3F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
+#define D3F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
+#define D3F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
+#define D3F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
+#define D3F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
+#define D3F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
+#define D3F3_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
+#define D3F3_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define D3F3_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
+#define D3F3_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define D3F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
+#define D3F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define D3F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
+#define D3F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
+#define D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
+#define D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
+#define D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
+#define D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define D3F3_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
+#define D3F3_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define D3F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
+#define D3F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define D3F3_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
+#define D3F3_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define D3F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
+#define D3F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define D3F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
+#define D3F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
+#define D3F3_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
+#define D3F3_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
+#define D3F3_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
+#define D3F3_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
+#define D3F3_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
+#define D3F3_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
+#define D3F3_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
+#define D3F3_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
+#define D3F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
+#define D3F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
+#define D3F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
+#define D3F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
+#define D3F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
+#define D3F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
+#define D3F3_CAP_PTR__CAP_PTR_MASK 0xff
+#define D3F3_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define D3F3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
+#define D3F3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define D3F3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
+#define D3F3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
+#define D3F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
+#define D3F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define D3F3_PMI_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F3_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F3_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F3_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F3_PMI_CAP__VERSION_MASK 0x70000
+#define D3F3_PMI_CAP__VERSION__SHIFT 0x10
+#define D3F3_PMI_CAP__PME_CLOCK_MASK 0x80000
+#define D3F3_PMI_CAP__PME_CLOCK__SHIFT 0x13
+#define D3F3_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
+#define D3F3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
+#define D3F3_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
+#define D3F3_PMI_CAP__AUX_CURRENT__SHIFT 0x16
+#define D3F3_PMI_CAP__D1_SUPPORT_MASK 0x2000000
+#define D3F3_PMI_CAP__D1_SUPPORT__SHIFT 0x19
+#define D3F3_PMI_CAP__D2_SUPPORT_MASK 0x4000000
+#define D3F3_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
+#define D3F3_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
+#define D3F3_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
+#define D3F3_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
+#define D3F3_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define D3F3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
+#define D3F3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define D3F3_PMI_STATUS_CNTL__PME_EN_MASK 0x100
+#define D3F3_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define D3F3_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
+#define D3F3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define D3F3_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
+#define D3F3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define D3F3_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
+#define D3F3_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define D3F3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
+#define D3F3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define D3F3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
+#define D3F3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define D3F3_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
+#define D3F3_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define D3F3_PCIE_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F3_PCIE_CAP__VERSION_MASK 0xf0000
+#define D3F3_PCIE_CAP__VERSION__SHIFT 0x10
+#define D3F3_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
+#define D3F3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
+#define D3F3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
+#define D3F3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
+#define D3F3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
+#define D3F3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
+#define D3F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
+#define D3F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define D3F3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
+#define D3F3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define D3F3_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
+#define D3F3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define D3F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
+#define D3F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define D3F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
+#define D3F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define D3F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
+#define D3F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
+#define D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
+#define D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define D3F3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
+#define D3F3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define D3F3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
+#define D3F3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define D3F3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
+#define D3F3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define D3F3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
+#define D3F3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define D3F3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
+#define D3F3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define D3F3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
+#define D3F3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define D3F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
+#define D3F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define D3F3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
+#define D3F3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define D3F3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
+#define D3F3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define D3F3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
+#define D3F3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define D3F3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
+#define D3F3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define D3F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
+#define D3F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define D3F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
+#define D3F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define D3F3_DEVICE_STATUS__CORR_ERR_MASK 0x10000
+#define D3F3_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
+#define D3F3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
+#define D3F3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
+#define D3F3_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
+#define D3F3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
+#define D3F3_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
+#define D3F3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
+#define D3F3_DEVICE_STATUS__AUX_PWR_MASK 0x100000
+#define D3F3_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
+#define D3F3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
+#define D3F3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
+#define D3F3_LINK_CAP__LINK_SPEED_MASK 0xf
+#define D3F3_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define D3F3_LINK_CAP__LINK_WIDTH_MASK 0x3f0
+#define D3F3_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define D3F3_LINK_CAP__PM_SUPPORT_MASK 0xc00
+#define D3F3_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define D3F3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
+#define D3F3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define D3F3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
+#define D3F3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define D3F3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
+#define D3F3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define D3F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
+#define D3F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define D3F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
+#define D3F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define D3F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
+#define D3F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define D3F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
+#define D3F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define D3F3_LINK_CAP__PORT_NUMBER_MASK 0xff000000
+#define D3F3_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define D3F3_LINK_CNTL__PM_CONTROL_MASK 0x3
+#define D3F3_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define D3F3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
+#define D3F3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define D3F3_LINK_CNTL__LINK_DIS_MASK 0x10
+#define D3F3_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define D3F3_LINK_CNTL__RETRAIN_LINK_MASK 0x20
+#define D3F3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define D3F3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
+#define D3F3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define D3F3_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
+#define D3F3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define D3F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
+#define D3F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define D3F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
+#define D3F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define D3F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
+#define D3F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define D3F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
+#define D3F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define D3F3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
+#define D3F3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
+#define D3F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
+#define D3F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
+#define D3F3_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
+#define D3F3_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
+#define D3F3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
+#define D3F3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
+#define D3F3_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
+#define D3F3_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
+#define D3F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
+#define D3F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
+#define D3F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
+#define D3F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
+#define D3F3_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
+#define D3F3_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define D3F3_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
+#define D3F3_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define D3F3_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
+#define D3F3_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define D3F3_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
+#define D3F3_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define D3F3_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
+#define D3F3_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define D3F3_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
+#define D3F3_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define D3F3_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
+#define D3F3_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define D3F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
+#define D3F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define D3F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
+#define D3F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define D3F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
+#define D3F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define D3F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
+#define D3F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define D3F3_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
+#define D3F3_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define D3F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
+#define D3F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define D3F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
+#define D3F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define D3F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
+#define D3F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define D3F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
+#define D3F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define D3F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
+#define D3F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define D3F3_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
+#define D3F3_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define D3F3_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
+#define D3F3_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define D3F3_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
+#define D3F3_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define D3F3_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
+#define D3F3_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define D3F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
+#define D3F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define D3F3_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
+#define D3F3_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define D3F3_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
+#define D3F3_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
+#define D3F3_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
+#define D3F3_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
+#define D3F3_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
+#define D3F3_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
+#define D3F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
+#define D3F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
+#define D3F3_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
+#define D3F3_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
+#define D3F3_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
+#define D3F3_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
+#define D3F3_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
+#define D3F3_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
+#define D3F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
+#define D3F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
+#define D3F3_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
+#define D3F3_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
+#define D3F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
+#define D3F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define D3F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
+#define D3F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define D3F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
+#define D3F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define D3F3_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
+#define D3F3_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define D3F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
+#define D3F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define D3F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
+#define D3F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
+#define D3F3_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
+#define D3F3_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define D3F3_ROOT_STATUS__PME_STATUS_MASK 0x10000
+#define D3F3_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define D3F3_ROOT_STATUS__PME_PENDING_MASK 0x20000
+#define D3F3_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define D3F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
+#define D3F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define D3F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
+#define D3F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define D3F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
+#define D3F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define D3F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
+#define D3F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define D3F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
+#define D3F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define D3F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
+#define D3F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define D3F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
+#define D3F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define D3F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
+#define D3F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define D3F3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
+#define D3F3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define D3F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
+#define D3F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define D3F3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
+#define D3F3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define D3F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
+#define D3F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define D3F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
+#define D3F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define D3F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
+#define D3F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define D3F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
+#define D3F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define D3F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
+#define D3F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define D3F3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
+#define D3F3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define D3F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
+#define D3F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define D3F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
+#define D3F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define D3F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
+#define D3F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define D3F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
+#define D3F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define D3F3_DEVICE_CNTL2__LTR_EN_MASK 0x400
+#define D3F3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define D3F3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
+#define D3F3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define D3F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
+#define D3F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define D3F3_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
+#define D3F3_DEVICE_STATUS2__RESERVED__SHIFT 0x10
+#define D3F3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
+#define D3F3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define D3F3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
+#define D3F3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define D3F3_LINK_CAP2__RESERVED_MASK 0xfffffe00
+#define D3F3_LINK_CAP2__RESERVED__SHIFT 0x9
+#define D3F3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
+#define D3F3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define D3F3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
+#define D3F3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define D3F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
+#define D3F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define D3F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
+#define D3F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define D3F3_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
+#define D3F3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define D3F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
+#define D3F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define D3F3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
+#define D3F3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define D3F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
+#define D3F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define D3F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
+#define D3F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
+#define D3F3_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
+#define D3F3_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
+#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
+#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
+#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
+#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
+#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
+#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
+#define D3F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
+#define D3F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
+#define D3F3_SLOT_CAP2__RESERVED_MASK 0xffffffff
+#define D3F3_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define D3F3_SLOT_CNTL2__RESERVED_MASK 0xffff
+#define D3F3_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define D3F3_SLOT_STATUS2__RESERVED_MASK 0xffff0000
+#define D3F3_SLOT_STATUS2__RESERVED__SHIFT 0x10
+#define D3F3_MSI_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F3_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F3_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
+#define D3F3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
+#define D3F3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
+#define D3F3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
+#define D3F3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
+#define D3F3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
+#define D3F3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
+#define D3F3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
+#define D3F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
+#define D3F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
+#define D3F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
+#define D3F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define D3F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
+#define D3F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define D3F3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
+#define D3F3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define D3F3_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
+#define D3F3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define D3F3_SSID_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F3_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F3_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F3_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F3_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
+#define D3F3_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define D3F3_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
+#define D3F3_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define D3F3_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F3_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F3_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F3_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F3_MSI_MAP_CAP__EN_MASK 0x10000
+#define D3F3_MSI_MAP_CAP__EN__SHIFT 0x10
+#define D3F3_MSI_MAP_CAP__FIXD_MASK 0x20000
+#define D3F3_MSI_MAP_CAP__FIXD__SHIFT 0x11
+#define D3F3_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
+#define D3F3_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
+#define D3F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
+#define D3F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define D3F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
+#define D3F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
+#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
+#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
+#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define D3F3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
+#define D3F3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define D3F3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
+#define D3F3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define D3F3_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F3_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F3_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F3_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
+#define D3F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define D3F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
+#define D3F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define D3F3_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
+#define D3F3_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define D3F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
+#define D3F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
+#define D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D3F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
+#define D3F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define D3F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
+#define D3F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define D3F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
+#define D3F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
+#define D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define D3F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define D3F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define D3F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define D3F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define D3F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define D3F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define D3F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define D3F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define D3F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
+#define D3F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
+#define D3F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
+#define D3F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
+#define D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define D3F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define D3F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define D3F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define D3F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define D3F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define D3F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define D3F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define D3F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define D3F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
+#define D3F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
+#define D3F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
+#define D3F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
+#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
+#define D3F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define D3F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
+#define D3F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
+#define D3F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define D3F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
+#define D3F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define D3F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
+#define D3F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define D3F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
+#define D3F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define D3F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
+#define D3F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define D3F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
+#define D3F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define D3F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
+#define D3F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define D3F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
+#define D3F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define D3F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
+#define D3F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define D3F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
+#define D3F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define D3F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
+#define D3F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define D3F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
+#define D3F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define D3F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
+#define D3F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define D3F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
+#define D3F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define D3F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
+#define D3F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define D3F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
+#define D3F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define D3F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
+#define D3F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define D3F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
+#define D3F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define D3F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
+#define D3F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define D3F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
+#define D3F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define D3F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
+#define D3F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define D3F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
+#define D3F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define D3F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
+#define D3F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define D3F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
+#define D3F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define D3F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
+#define D3F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define D3F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
+#define D3F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define D3F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
+#define D3F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define D3F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
+#define D3F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define D3F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
+#define D3F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define D3F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
+#define D3F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define D3F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
+#define D3F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define D3F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
+#define D3F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
+#define D3F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define D3F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
+#define D3F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define D3F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
+#define D3F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define D3F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
+#define D3F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define D3F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
+#define D3F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define D3F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
+#define D3F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define D3F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
+#define D3F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define D3F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
+#define D3F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define D3F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
+#define D3F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define D3F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
+#define D3F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define D3F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
+#define D3F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define D3F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
+#define D3F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define D3F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
+#define D3F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define D3F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
+#define D3F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define D3F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
+#define D3F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define D3F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
+#define D3F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define D3F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
+#define D3F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define D3F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
+#define D3F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
+#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
+#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
+#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
+#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
+#define D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
+#define D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define D3F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
+#define D3F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define D3F3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
+#define D3F3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define D3F3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
+#define D3F3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define D3F3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
+#define D3F3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define D3F3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
+#define D3F3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define D3F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
+#define D3F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define D3F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
+#define D3F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define D3F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
+#define D3F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define D3F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
+#define D3F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
+#define D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define D3F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
+#define D3F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
+#define D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define D3F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
+#define D3F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define D3F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
+#define D3F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define D3F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
+#define D3F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define D3F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
+#define D3F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define D3F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
+#define D3F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define D3F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
+#define D3F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define D3F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
+#define D3F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define D3F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
+#define D3F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define D3F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
+#define D3F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define D3F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
+#define D3F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
+#define D3F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define D3F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
+#define D3F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define D3F3_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
+#define D3F3_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define D3F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
+#define D3F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define D3F3_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
+#define D3F3_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
+#define D3F3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define D3F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
+#define D3F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define D3F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
+#define D3F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define D3F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
+#define D3F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define D3F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
+#define D3F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define D3F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
+#define D3F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define D3F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
+#define D3F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define D3F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
+#define D3F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define D3F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
+#define D3F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
+#define D3F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
+#define D3F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
+#define D3F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
+#define D3F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
+#define D3F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
+#define D3F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
+#define D3F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
+#define D3F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
+#define D3F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
+#define D3F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
+#define D3F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
+#define D3F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
+#define D3F3_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F3_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F3_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F3_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F3_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
+#define D3F3_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define D3F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
+#define D3F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define D3F3_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
+#define D3F3_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
+#define D3F3_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
+#define D3F3_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
+#define D3F3_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
+#define D3F3_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define D3F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
+#define D3F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define D3F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
+#define D3F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define D3F3_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
+#define D3F3_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define D3F3_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
+#define D3F3_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define D3F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
+#define D3F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define D3F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
+#define D3F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define D3F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
+#define D3F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define D3F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
+#define D3F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
+#define D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
+#define D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define D3F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
+#define D3F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define D3F4_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
+#define D3F4_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
+#define D3F4_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
+#define D3F4_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
+#define D3F4_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
+#define D3F4_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define D3F4_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
+#define D3F4_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define D3F4_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define D3F4_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define D3F4_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define D3F4_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define D3F4_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define D3F4_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define D3F4_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define D3F4_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define D3F4_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define D3F4_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define D3F4_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define D3F4_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define D3F4_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define D3F4_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define D3F4_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define D3F4_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define D3F4_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define D3F4_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define D3F4_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define D3F4_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define D3F4_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define D3F4_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define D3F4_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define D3F4_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define D3F4_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define D3F4_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define D3F4_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define D3F4_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define D3F4_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define D3F4_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define D3F4_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define D3F4_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define D3F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
+#define D3F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define D3F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
+#define D3F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define D3F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
+#define D3F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define D3F4_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
+#define D3F4_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define D3F4_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
+#define D3F4_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define D3F4_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
+#define D3F4_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define D3F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
+#define D3F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
+#define D3F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
+#define D3F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define D3F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
+#define D3F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define D3F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
+#define D3F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define D3F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
+#define D3F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define D3F4_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
+#define D3F4_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define D3F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
+#define D3F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define D3F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
+#define D3F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define D3F4_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
+#define D3F4_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define D3F4_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
+#define D3F4_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define D3F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
+#define D3F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define D3F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
+#define D3F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
+#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
+#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
+#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define D3F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
+#define D3F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
+#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
+#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
+#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define D3F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
+#define D3F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define D3F4_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
+#define D3F4_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
+#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
+#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
+#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
+#define D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
+#define D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
+#define D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
+#define D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
+#define D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
+#define D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
+#define D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
+#define D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
+#define D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
+#define D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
+#define D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
+#define D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
+#define D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
+#define D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
+#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
+#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
+#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
+#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
+#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
+#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
+#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define D3F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
+#define D3F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define D3F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
+#define D3F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define D3F4_PCIE_FC_P__PD_CREDITS_MASK 0xff
+#define D3F4_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define D3F4_PCIE_FC_P__PH_CREDITS_MASK 0xff00
+#define D3F4_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
+#define D3F4_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
+#define D3F4_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define D3F4_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
+#define D3F4_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
+#define D3F4_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
+#define D3F4_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define D3F4_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
+#define D3F4_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
+#define D3F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
+#define D3F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define D3F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
+#define D3F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define D3F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
+#define D3F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define D3F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
+#define D3F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define D3F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
+#define D3F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define D3F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
+#define D3F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define D3F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
+#define D3F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
+#define D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
+#define D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define D3F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
+#define D3F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define D3F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
+#define D3F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define D3F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
+#define D3F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define D3F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
+#define D3F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define D3F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
+#define D3F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define D3F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
+#define D3F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define D3F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
+#define D3F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
+#define D3F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
+#define D3F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
+#define D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
+#define D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define D3F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
+#define D3F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
+#define D3F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define D3F4_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
+#define D3F4_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define D3F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
+#define D3F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define D3F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
+#define D3F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
+#define D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
+#define D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
+#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
+#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
+#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
+#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
+#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
+#define D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
+#define D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
+#define D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
+#define D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
+#define D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
+#define D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
+#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
+#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
+#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
+#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
+#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
+#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
+#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
+#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
+#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
+#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
+#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define D3F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
+#define D3F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define D3F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
+#define D3F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define D3F4_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
+#define D3F4_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define D3F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
+#define D3F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define D3F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
+#define D3F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define D3F4_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
+#define D3F4_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define D3F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
+#define D3F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define D3F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
+#define D3F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define D3F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
+#define D3F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define D3F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
+#define D3F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define D3F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
+#define D3F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define D3F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
+#define D3F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define D3F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
+#define D3F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define D3F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
+#define D3F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define D3F4_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
+#define D3F4_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define D3F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
+#define D3F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define D3F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
+#define D3F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define D3F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
+#define D3F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define D3F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
+#define D3F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define D3F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
+#define D3F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define D3F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
+#define D3F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define D3F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
+#define D3F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define D3F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
+#define D3F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define D3F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
+#define D3F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define D3F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
+#define D3F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define D3F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
+#define D3F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
+#define D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
+#define D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
+#define D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define D3F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
+#define D3F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define D3F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
+#define D3F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
+#define D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
+#define D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define D3F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
+#define D3F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
+#define D3F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
+#define D3F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define D3F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
+#define D3F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define D3F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
+#define D3F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
+#define D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define D3F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
+#define D3F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define D3F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
+#define D3F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define D3F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
+#define D3F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define D3F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
+#define D3F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define D3F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
+#define D3F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define D3F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
+#define D3F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
+#define D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
+#define D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define D3F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
+#define D3F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define D3F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
+#define D3F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define D3F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
+#define D3F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
+#define D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
+#define D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define D3F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
+#define D3F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define D3F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
+#define D3F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define D3F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
+#define D3F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define D3F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
+#define D3F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
+#define D3F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
+#define D3F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
+#define D3F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
+#define D3F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
+#define D3F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
+#define D3F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
+#define D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
+#define D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define D3F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
+#define D3F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define D3F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
+#define D3F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
+#define D3F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
+#define D3F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define D3F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
+#define D3F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define D3F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
+#define D3F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define D3F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
+#define D3F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define D3F4_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
+#define D3F4_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
+#define D3F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
+#define D3F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define D3F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
+#define D3F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define D3F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
+#define D3F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
+#define D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
+#define D3F4_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
+#define D3F4_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
+#define D3F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
+#define D3F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define D3F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
+#define D3F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define D3F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
+#define D3F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
+#define D3F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
+#define D3F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define D3F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
+#define D3F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
+#define D3F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
+#define D3F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
+#define D3F4_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
+#define D3F4_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define D3F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
+#define D3F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define D3F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
+#define D3F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
+#define D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
+#define D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
+#define D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
+#define D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
+#define D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
+#define D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
+#define D3F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
+#define D3F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define D3F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
+#define D3F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
+#define D3F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
+#define D3F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define D3F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
+#define D3F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define D3F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
+#define D3F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define D3F4_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
+#define D3F4_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
+#define D3F4_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
+#define D3F4_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
+#define D3F4_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
+#define D3F4_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
+#define D3F4_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
+#define D3F4_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
+#define D3F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
+#define D3F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
+#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
+#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
+#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
+#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
+#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
+#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
+#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
+#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
+#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
+#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
+#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
+#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
+#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
+#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
+#define D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
+#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
+#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
+#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
+#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
+#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define D3F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
+#define D3F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
+#define D3F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
+#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
+#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
+#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
+#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define D3F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
+#define D3F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define D3F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
+#define D3F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
+#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
+#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
+#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
+#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
+#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
+#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
+#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
+#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
+#define D3F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
+#define D3F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
+#define D3F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
+#define D3F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
+#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
+#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
+#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
+#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
+#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
+#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
+#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
+#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
+#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
+#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
+#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
+#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
+#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
+#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
+#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
+#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
+#define D3F4_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
+#define D3F4_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
+#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
+#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
+#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
+#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
+#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
+#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
+#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
+#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
+#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
+#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
+#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
+#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
+#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
+#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
+#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
+#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
+#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
+#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
+#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
+#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
+#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
+#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
+#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define D3F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
+#define D3F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define D3F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
+#define D3F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define D3F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
+#define D3F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define D3F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
+#define D3F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define D3F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
+#define D3F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define D3F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
+#define D3F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define D3F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
+#define D3F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define D3F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
+#define D3F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define D3F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
+#define D3F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define D3F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
+#define D3F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define D3F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
+#define D3F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define D3F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
+#define D3F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define D3F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
+#define D3F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define D3F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
+#define D3F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define D3F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
+#define D3F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define D3F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
+#define D3F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define D3F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
+#define D3F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
+#define D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
+#define D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
+#define D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
+#define D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
+#define D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
+#define D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
+#define D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
+#define D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define D3F4_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
+#define D3F4_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
+#define D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
+#define D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
+#define D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
+#define D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define D3F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
+#define D3F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define D3F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
+#define D3F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define D3F4_VENDOR_ID__VENDOR_ID_MASK 0xffff
+#define D3F4_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define D3F4_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
+#define D3F4_DEVICE_ID__DEVICE_ID__SHIFT 0x10
+#define D3F4_COMMAND__IO_ACCESS_EN_MASK 0x1
+#define D3F4_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define D3F4_COMMAND__MEM_ACCESS_EN_MASK 0x2
+#define D3F4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define D3F4_COMMAND__BUS_MASTER_EN_MASK 0x4
+#define D3F4_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define D3F4_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
+#define D3F4_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define D3F4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
+#define D3F4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define D3F4_COMMAND__PAL_SNOOP_EN_MASK 0x20
+#define D3F4_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define D3F4_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
+#define D3F4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define D3F4_COMMAND__AD_STEPPING_MASK 0x80
+#define D3F4_COMMAND__AD_STEPPING__SHIFT 0x7
+#define D3F4_COMMAND__SERR_EN_MASK 0x100
+#define D3F4_COMMAND__SERR_EN__SHIFT 0x8
+#define D3F4_COMMAND__FAST_B2B_EN_MASK 0x200
+#define D3F4_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define D3F4_COMMAND__INT_DIS_MASK 0x400
+#define D3F4_COMMAND__INT_DIS__SHIFT 0xa
+#define D3F4_STATUS__INT_STATUS_MASK 0x80000
+#define D3F4_STATUS__INT_STATUS__SHIFT 0x13
+#define D3F4_STATUS__CAP_LIST_MASK 0x100000
+#define D3F4_STATUS__CAP_LIST__SHIFT 0x14
+#define D3F4_STATUS__PCI_66_EN_MASK 0x200000
+#define D3F4_STATUS__PCI_66_EN__SHIFT 0x15
+#define D3F4_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
+#define D3F4_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
+#define D3F4_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
+#define D3F4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
+#define D3F4_STATUS__DEVSEL_TIMING_MASK 0x6000000
+#define D3F4_STATUS__DEVSEL_TIMING__SHIFT 0x19
+#define D3F4_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
+#define D3F4_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
+#define D3F4_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
+#define D3F4_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
+#define D3F4_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
+#define D3F4_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
+#define D3F4_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
+#define D3F4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
+#define D3F4_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
+#define D3F4_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
+#define D3F4_REVISION_ID__MINOR_REV_ID_MASK 0xf
+#define D3F4_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define D3F4_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
+#define D3F4_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define D3F4_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
+#define D3F4_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
+#define D3F4_SUB_CLASS__SUB_CLASS_MASK 0xff0000
+#define D3F4_SUB_CLASS__SUB_CLASS__SHIFT 0x10
+#define D3F4_BASE_CLASS__BASE_CLASS_MASK 0xff000000
+#define D3F4_BASE_CLASS__BASE_CLASS__SHIFT 0x18
+#define D3F4_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
+#define D3F4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define D3F4_LATENCY__LATENCY_TIMER_MASK 0xff00
+#define D3F4_LATENCY__LATENCY_TIMER__SHIFT 0x8
+#define D3F4_HEADER__HEADER_TYPE_MASK 0x7f0000
+#define D3F4_HEADER__HEADER_TYPE__SHIFT 0x10
+#define D3F4_HEADER__DEVICE_TYPE_MASK 0x800000
+#define D3F4_HEADER__DEVICE_TYPE__SHIFT 0x17
+#define D3F4_BIST__BIST_COMP_MASK 0xf000000
+#define D3F4_BIST__BIST_COMP__SHIFT 0x18
+#define D3F4_BIST__BIST_STRT_MASK 0x40000000
+#define D3F4_BIST__BIST_STRT__SHIFT 0x1e
+#define D3F4_BIST__BIST_CAP_MASK 0x80000000
+#define D3F4_BIST__BIST_CAP__SHIFT 0x1f
+#define D3F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
+#define D3F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
+#define D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define D3F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
+#define D3F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
+#define D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define D3F4_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
+#define D3F4_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define D3F4_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
+#define D3F4_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define D3F4_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
+#define D3F4_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define D3F4_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
+#define D3F4_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define D3F4_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
+#define D3F4_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
+#define D3F4_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
+#define D3F4_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
+#define D3F4_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
+#define D3F4_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
+#define D3F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
+#define D3F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
+#define D3F4_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
+#define D3F4_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
+#define D3F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
+#define D3F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
+#define D3F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
+#define D3F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
+#define D3F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
+#define D3F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
+#define D3F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
+#define D3F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
+#define D3F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
+#define D3F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
+#define D3F4_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
+#define D3F4_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define D3F4_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
+#define D3F4_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define D3F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
+#define D3F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define D3F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
+#define D3F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
+#define D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
+#define D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
+#define D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
+#define D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define D3F4_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
+#define D3F4_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define D3F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
+#define D3F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define D3F4_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
+#define D3F4_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define D3F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
+#define D3F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define D3F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
+#define D3F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
+#define D3F4_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
+#define D3F4_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
+#define D3F4_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
+#define D3F4_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
+#define D3F4_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
+#define D3F4_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
+#define D3F4_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
+#define D3F4_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
+#define D3F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
+#define D3F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
+#define D3F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
+#define D3F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
+#define D3F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
+#define D3F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
+#define D3F4_CAP_PTR__CAP_PTR_MASK 0xff
+#define D3F4_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define D3F4_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
+#define D3F4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define D3F4_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
+#define D3F4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
+#define D3F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
+#define D3F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define D3F4_PMI_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F4_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F4_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F4_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F4_PMI_CAP__VERSION_MASK 0x70000
+#define D3F4_PMI_CAP__VERSION__SHIFT 0x10
+#define D3F4_PMI_CAP__PME_CLOCK_MASK 0x80000
+#define D3F4_PMI_CAP__PME_CLOCK__SHIFT 0x13
+#define D3F4_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
+#define D3F4_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
+#define D3F4_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
+#define D3F4_PMI_CAP__AUX_CURRENT__SHIFT 0x16
+#define D3F4_PMI_CAP__D1_SUPPORT_MASK 0x2000000
+#define D3F4_PMI_CAP__D1_SUPPORT__SHIFT 0x19
+#define D3F4_PMI_CAP__D2_SUPPORT_MASK 0x4000000
+#define D3F4_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
+#define D3F4_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
+#define D3F4_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
+#define D3F4_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
+#define D3F4_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define D3F4_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
+#define D3F4_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define D3F4_PMI_STATUS_CNTL__PME_EN_MASK 0x100
+#define D3F4_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define D3F4_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
+#define D3F4_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define D3F4_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
+#define D3F4_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define D3F4_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
+#define D3F4_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define D3F4_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
+#define D3F4_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define D3F4_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
+#define D3F4_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define D3F4_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
+#define D3F4_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define D3F4_PCIE_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F4_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F4_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F4_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F4_PCIE_CAP__VERSION_MASK 0xf0000
+#define D3F4_PCIE_CAP__VERSION__SHIFT 0x10
+#define D3F4_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
+#define D3F4_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
+#define D3F4_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
+#define D3F4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
+#define D3F4_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
+#define D3F4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
+#define D3F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
+#define D3F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define D3F4_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
+#define D3F4_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define D3F4_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
+#define D3F4_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define D3F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
+#define D3F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define D3F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
+#define D3F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define D3F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
+#define D3F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
+#define D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
+#define D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define D3F4_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
+#define D3F4_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define D3F4_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
+#define D3F4_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define D3F4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
+#define D3F4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define D3F4_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
+#define D3F4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define D3F4_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
+#define D3F4_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define D3F4_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
+#define D3F4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define D3F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
+#define D3F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define D3F4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
+#define D3F4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define D3F4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
+#define D3F4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define D3F4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
+#define D3F4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define D3F4_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
+#define D3F4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define D3F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
+#define D3F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define D3F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
+#define D3F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define D3F4_DEVICE_STATUS__CORR_ERR_MASK 0x10000
+#define D3F4_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
+#define D3F4_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
+#define D3F4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
+#define D3F4_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
+#define D3F4_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
+#define D3F4_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
+#define D3F4_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
+#define D3F4_DEVICE_STATUS__AUX_PWR_MASK 0x100000
+#define D3F4_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
+#define D3F4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
+#define D3F4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
+#define D3F4_LINK_CAP__LINK_SPEED_MASK 0xf
+#define D3F4_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define D3F4_LINK_CAP__LINK_WIDTH_MASK 0x3f0
+#define D3F4_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define D3F4_LINK_CAP__PM_SUPPORT_MASK 0xc00
+#define D3F4_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define D3F4_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
+#define D3F4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define D3F4_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
+#define D3F4_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define D3F4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
+#define D3F4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define D3F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
+#define D3F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define D3F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
+#define D3F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define D3F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
+#define D3F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define D3F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
+#define D3F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define D3F4_LINK_CAP__PORT_NUMBER_MASK 0xff000000
+#define D3F4_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define D3F4_LINK_CNTL__PM_CONTROL_MASK 0x3
+#define D3F4_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define D3F4_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
+#define D3F4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define D3F4_LINK_CNTL__LINK_DIS_MASK 0x10
+#define D3F4_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define D3F4_LINK_CNTL__RETRAIN_LINK_MASK 0x20
+#define D3F4_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define D3F4_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
+#define D3F4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define D3F4_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
+#define D3F4_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define D3F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
+#define D3F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define D3F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
+#define D3F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define D3F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
+#define D3F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define D3F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
+#define D3F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define D3F4_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
+#define D3F4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
+#define D3F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
+#define D3F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
+#define D3F4_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
+#define D3F4_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
+#define D3F4_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
+#define D3F4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
+#define D3F4_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
+#define D3F4_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
+#define D3F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
+#define D3F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
+#define D3F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
+#define D3F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
+#define D3F4_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
+#define D3F4_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define D3F4_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
+#define D3F4_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define D3F4_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
+#define D3F4_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define D3F4_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
+#define D3F4_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define D3F4_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
+#define D3F4_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define D3F4_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
+#define D3F4_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define D3F4_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
+#define D3F4_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define D3F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
+#define D3F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define D3F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
+#define D3F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define D3F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
+#define D3F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define D3F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
+#define D3F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define D3F4_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
+#define D3F4_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define D3F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
+#define D3F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define D3F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
+#define D3F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define D3F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
+#define D3F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define D3F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
+#define D3F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define D3F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
+#define D3F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define D3F4_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
+#define D3F4_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define D3F4_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
+#define D3F4_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define D3F4_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
+#define D3F4_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define D3F4_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
+#define D3F4_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define D3F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
+#define D3F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define D3F4_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
+#define D3F4_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define D3F4_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
+#define D3F4_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
+#define D3F4_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
+#define D3F4_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
+#define D3F4_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
+#define D3F4_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
+#define D3F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
+#define D3F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
+#define D3F4_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
+#define D3F4_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
+#define D3F4_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
+#define D3F4_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
+#define D3F4_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
+#define D3F4_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
+#define D3F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
+#define D3F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
+#define D3F4_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
+#define D3F4_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
+#define D3F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
+#define D3F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define D3F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
+#define D3F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define D3F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
+#define D3F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define D3F4_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
+#define D3F4_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define D3F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
+#define D3F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define D3F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
+#define D3F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
+#define D3F4_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
+#define D3F4_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define D3F4_ROOT_STATUS__PME_STATUS_MASK 0x10000
+#define D3F4_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define D3F4_ROOT_STATUS__PME_PENDING_MASK 0x20000
+#define D3F4_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define D3F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
+#define D3F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define D3F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
+#define D3F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define D3F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
+#define D3F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define D3F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
+#define D3F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define D3F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
+#define D3F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define D3F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
+#define D3F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define D3F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
+#define D3F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define D3F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
+#define D3F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define D3F4_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
+#define D3F4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define D3F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
+#define D3F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define D3F4_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
+#define D3F4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define D3F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
+#define D3F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define D3F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
+#define D3F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define D3F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
+#define D3F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define D3F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
+#define D3F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define D3F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
+#define D3F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define D3F4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
+#define D3F4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define D3F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
+#define D3F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define D3F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
+#define D3F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define D3F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
+#define D3F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define D3F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
+#define D3F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define D3F4_DEVICE_CNTL2__LTR_EN_MASK 0x400
+#define D3F4_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define D3F4_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
+#define D3F4_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define D3F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
+#define D3F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define D3F4_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
+#define D3F4_DEVICE_STATUS2__RESERVED__SHIFT 0x10
+#define D3F4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
+#define D3F4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define D3F4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
+#define D3F4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define D3F4_LINK_CAP2__RESERVED_MASK 0xfffffe00
+#define D3F4_LINK_CAP2__RESERVED__SHIFT 0x9
+#define D3F4_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
+#define D3F4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define D3F4_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
+#define D3F4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define D3F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
+#define D3F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define D3F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
+#define D3F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define D3F4_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
+#define D3F4_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define D3F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
+#define D3F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define D3F4_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
+#define D3F4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define D3F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
+#define D3F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define D3F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
+#define D3F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
+#define D3F4_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
+#define D3F4_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
+#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
+#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
+#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
+#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
+#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
+#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
+#define D3F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
+#define D3F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
+#define D3F4_SLOT_CAP2__RESERVED_MASK 0xffffffff
+#define D3F4_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define D3F4_SLOT_CNTL2__RESERVED_MASK 0xffff
+#define D3F4_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define D3F4_SLOT_STATUS2__RESERVED_MASK 0xffff0000
+#define D3F4_SLOT_STATUS2__RESERVED__SHIFT 0x10
+#define D3F4_MSI_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F4_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F4_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F4_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F4_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
+#define D3F4_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
+#define D3F4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
+#define D3F4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
+#define D3F4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
+#define D3F4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
+#define D3F4_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
+#define D3F4_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
+#define D3F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
+#define D3F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
+#define D3F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
+#define D3F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define D3F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
+#define D3F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define D3F4_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
+#define D3F4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define D3F4_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
+#define D3F4_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define D3F4_SSID_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F4_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F4_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F4_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F4_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
+#define D3F4_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define D3F4_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
+#define D3F4_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define D3F4_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F4_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F4_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F4_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F4_MSI_MAP_CAP__EN_MASK 0x10000
+#define D3F4_MSI_MAP_CAP__EN__SHIFT 0x10
+#define D3F4_MSI_MAP_CAP__FIXD_MASK 0x20000
+#define D3F4_MSI_MAP_CAP__FIXD__SHIFT 0x11
+#define D3F4_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
+#define D3F4_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
+#define D3F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
+#define D3F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define D3F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
+#define D3F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
+#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
+#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
+#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define D3F4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
+#define D3F4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define D3F4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
+#define D3F4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define D3F4_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F4_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F4_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F4_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
+#define D3F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define D3F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
+#define D3F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define D3F4_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
+#define D3F4_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define D3F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
+#define D3F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
+#define D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D3F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
+#define D3F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define D3F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
+#define D3F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define D3F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
+#define D3F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
+#define D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define D3F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define D3F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define D3F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define D3F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define D3F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define D3F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define D3F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define D3F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define D3F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
+#define D3F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
+#define D3F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
+#define D3F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
+#define D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define D3F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define D3F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define D3F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define D3F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define D3F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define D3F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define D3F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define D3F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define D3F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
+#define D3F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
+#define D3F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
+#define D3F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
+#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
+#define D3F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define D3F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
+#define D3F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
+#define D3F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define D3F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
+#define D3F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define D3F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
+#define D3F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define D3F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
+#define D3F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define D3F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
+#define D3F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define D3F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
+#define D3F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define D3F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
+#define D3F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define D3F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
+#define D3F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define D3F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
+#define D3F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define D3F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
+#define D3F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define D3F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
+#define D3F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define D3F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
+#define D3F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define D3F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
+#define D3F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define D3F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
+#define D3F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define D3F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
+#define D3F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define D3F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
+#define D3F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define D3F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
+#define D3F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define D3F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
+#define D3F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define D3F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
+#define D3F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define D3F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
+#define D3F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define D3F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
+#define D3F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define D3F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
+#define D3F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define D3F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
+#define D3F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define D3F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
+#define D3F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define D3F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
+#define D3F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define D3F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
+#define D3F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define D3F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
+#define D3F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define D3F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
+#define D3F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define D3F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
+#define D3F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define D3F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
+#define D3F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define D3F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
+#define D3F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define D3F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
+#define D3F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
+#define D3F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define D3F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
+#define D3F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define D3F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
+#define D3F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define D3F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
+#define D3F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define D3F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
+#define D3F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define D3F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
+#define D3F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define D3F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
+#define D3F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define D3F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
+#define D3F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define D3F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
+#define D3F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define D3F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
+#define D3F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define D3F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
+#define D3F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define D3F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
+#define D3F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define D3F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
+#define D3F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define D3F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
+#define D3F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define D3F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
+#define D3F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define D3F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
+#define D3F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define D3F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
+#define D3F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define D3F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
+#define D3F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
+#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
+#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
+#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
+#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
+#define D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
+#define D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define D3F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
+#define D3F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define D3F4_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
+#define D3F4_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define D3F4_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
+#define D3F4_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define D3F4_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
+#define D3F4_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define D3F4_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
+#define D3F4_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define D3F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
+#define D3F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define D3F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
+#define D3F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define D3F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
+#define D3F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define D3F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
+#define D3F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
+#define D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define D3F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
+#define D3F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
+#define D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define D3F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
+#define D3F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define D3F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
+#define D3F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define D3F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
+#define D3F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define D3F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
+#define D3F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define D3F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
+#define D3F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define D3F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
+#define D3F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define D3F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
+#define D3F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define D3F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
+#define D3F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define D3F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
+#define D3F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define D3F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
+#define D3F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
+#define D3F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define D3F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
+#define D3F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define D3F4_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
+#define D3F4_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define D3F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
+#define D3F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define D3F4_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
+#define D3F4_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F4_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
+#define D3F4_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define D3F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
+#define D3F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define D3F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
+#define D3F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define D3F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
+#define D3F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define D3F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
+#define D3F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define D3F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
+#define D3F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define D3F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
+#define D3F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define D3F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
+#define D3F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define D3F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
+#define D3F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
+#define D3F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
+#define D3F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
+#define D3F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
+#define D3F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
+#define D3F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
+#define D3F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
+#define D3F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
+#define D3F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
+#define D3F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
+#define D3F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
+#define D3F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
+#define D3F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
+#define D3F4_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F4_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F4_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F4_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F4_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
+#define D3F4_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define D3F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
+#define D3F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define D3F4_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
+#define D3F4_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
+#define D3F4_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
+#define D3F4_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
+#define D3F4_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
+#define D3F4_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define D3F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
+#define D3F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define D3F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
+#define D3F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define D3F4_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
+#define D3F4_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define D3F4_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
+#define D3F4_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define D3F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
+#define D3F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define D3F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
+#define D3F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define D3F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
+#define D3F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define D3F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
+#define D3F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
+#define D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
+#define D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define D3F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
+#define D3F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define D3F5_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
+#define D3F5_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
+#define D3F5_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
+#define D3F5_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
+#define D3F5_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
+#define D3F5_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define D3F5_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
+#define D3F5_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define D3F5_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define D3F5_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define D3F5_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define D3F5_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define D3F5_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define D3F5_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define D3F5_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define D3F5_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define D3F5_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define D3F5_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define D3F5_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define D3F5_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define D3F5_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define D3F5_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define D3F5_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define D3F5_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define D3F5_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define D3F5_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define D3F5_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define D3F5_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define D3F5_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define D3F5_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define D3F5_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define D3F5_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define D3F5_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define D3F5_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define D3F5_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define D3F5_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define D3F5_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define D3F5_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define D3F5_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define D3F5_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define D3F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
+#define D3F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define D3F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
+#define D3F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define D3F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
+#define D3F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define D3F5_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
+#define D3F5_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define D3F5_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
+#define D3F5_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define D3F5_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
+#define D3F5_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define D3F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
+#define D3F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
+#define D3F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
+#define D3F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define D3F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
+#define D3F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define D3F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
+#define D3F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define D3F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
+#define D3F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define D3F5_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
+#define D3F5_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define D3F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
+#define D3F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define D3F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
+#define D3F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define D3F5_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
+#define D3F5_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define D3F5_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
+#define D3F5_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define D3F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
+#define D3F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define D3F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
+#define D3F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
+#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
+#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
+#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define D3F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
+#define D3F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
+#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
+#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
+#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define D3F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
+#define D3F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define D3F5_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
+#define D3F5_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
+#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
+#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
+#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
+#define D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
+#define D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
+#define D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
+#define D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
+#define D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
+#define D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
+#define D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
+#define D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
+#define D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
+#define D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
+#define D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
+#define D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
+#define D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
+#define D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
+#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
+#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
+#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
+#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
+#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
+#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
+#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define D3F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
+#define D3F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define D3F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
+#define D3F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define D3F5_PCIE_FC_P__PD_CREDITS_MASK 0xff
+#define D3F5_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define D3F5_PCIE_FC_P__PH_CREDITS_MASK 0xff00
+#define D3F5_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
+#define D3F5_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
+#define D3F5_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define D3F5_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
+#define D3F5_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
+#define D3F5_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
+#define D3F5_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define D3F5_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
+#define D3F5_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
+#define D3F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
+#define D3F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define D3F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
+#define D3F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define D3F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
+#define D3F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define D3F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
+#define D3F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define D3F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
+#define D3F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define D3F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
+#define D3F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define D3F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
+#define D3F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
+#define D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
+#define D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define D3F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
+#define D3F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define D3F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
+#define D3F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define D3F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
+#define D3F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define D3F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
+#define D3F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define D3F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
+#define D3F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define D3F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
+#define D3F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define D3F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
+#define D3F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
+#define D3F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
+#define D3F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
+#define D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
+#define D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define D3F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
+#define D3F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
+#define D3F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define D3F5_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
+#define D3F5_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define D3F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
+#define D3F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define D3F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
+#define D3F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
+#define D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
+#define D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
+#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
+#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
+#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
+#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
+#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
+#define D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
+#define D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
+#define D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
+#define D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
+#define D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
+#define D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
+#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
+#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
+#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
+#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
+#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
+#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
+#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
+#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
+#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
+#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
+#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define D3F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
+#define D3F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define D3F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
+#define D3F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define D3F5_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
+#define D3F5_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define D3F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
+#define D3F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define D3F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
+#define D3F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define D3F5_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
+#define D3F5_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define D3F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
+#define D3F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define D3F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
+#define D3F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define D3F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
+#define D3F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define D3F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
+#define D3F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define D3F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
+#define D3F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define D3F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
+#define D3F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define D3F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
+#define D3F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define D3F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
+#define D3F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define D3F5_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
+#define D3F5_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define D3F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
+#define D3F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define D3F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
+#define D3F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define D3F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
+#define D3F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define D3F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
+#define D3F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define D3F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
+#define D3F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define D3F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
+#define D3F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define D3F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
+#define D3F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define D3F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
+#define D3F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define D3F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
+#define D3F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define D3F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
+#define D3F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define D3F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
+#define D3F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
+#define D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
+#define D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
+#define D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define D3F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
+#define D3F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define D3F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
+#define D3F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
+#define D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
+#define D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define D3F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
+#define D3F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
+#define D3F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
+#define D3F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define D3F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
+#define D3F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define D3F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
+#define D3F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
+#define D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define D3F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
+#define D3F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define D3F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
+#define D3F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define D3F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
+#define D3F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define D3F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
+#define D3F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define D3F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
+#define D3F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define D3F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
+#define D3F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
+#define D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
+#define D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define D3F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
+#define D3F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define D3F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
+#define D3F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define D3F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
+#define D3F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
+#define D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
+#define D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define D3F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
+#define D3F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define D3F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
+#define D3F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define D3F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
+#define D3F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define D3F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
+#define D3F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
+#define D3F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
+#define D3F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
+#define D3F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
+#define D3F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
+#define D3F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
+#define D3F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
+#define D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
+#define D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define D3F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
+#define D3F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define D3F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
+#define D3F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
+#define D3F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
+#define D3F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define D3F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
+#define D3F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define D3F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
+#define D3F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define D3F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
+#define D3F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define D3F5_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
+#define D3F5_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
+#define D3F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
+#define D3F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define D3F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
+#define D3F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define D3F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
+#define D3F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
+#define D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
+#define D3F5_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
+#define D3F5_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
+#define D3F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
+#define D3F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define D3F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
+#define D3F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define D3F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
+#define D3F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
+#define D3F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
+#define D3F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define D3F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
+#define D3F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
+#define D3F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
+#define D3F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
+#define D3F5_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
+#define D3F5_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define D3F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
+#define D3F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define D3F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
+#define D3F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
+#define D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
+#define D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
+#define D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
+#define D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
+#define D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
+#define D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
+#define D3F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
+#define D3F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define D3F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
+#define D3F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
+#define D3F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
+#define D3F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define D3F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
+#define D3F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define D3F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
+#define D3F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define D3F5_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
+#define D3F5_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
+#define D3F5_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
+#define D3F5_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
+#define D3F5_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
+#define D3F5_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
+#define D3F5_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
+#define D3F5_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
+#define D3F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
+#define D3F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
+#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
+#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
+#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
+#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
+#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
+#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
+#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
+#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
+#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
+#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
+#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
+#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
+#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
+#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
+#define D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
+#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
+#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
+#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
+#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
+#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define D3F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
+#define D3F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
+#define D3F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
+#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
+#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
+#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
+#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define D3F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
+#define D3F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define D3F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
+#define D3F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
+#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
+#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
+#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
+#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
+#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
+#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
+#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
+#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
+#define D3F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
+#define D3F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
+#define D3F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
+#define D3F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
+#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
+#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
+#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
+#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
+#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
+#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
+#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
+#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
+#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
+#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
+#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
+#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
+#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
+#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
+#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
+#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
+#define D3F5_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
+#define D3F5_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
+#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
+#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
+#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
+#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
+#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
+#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
+#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
+#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
+#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
+#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
+#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
+#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
+#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
+#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
+#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
+#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
+#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
+#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
+#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
+#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
+#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
+#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
+#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define D3F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
+#define D3F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define D3F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
+#define D3F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define D3F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
+#define D3F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define D3F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
+#define D3F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define D3F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
+#define D3F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define D3F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
+#define D3F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define D3F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
+#define D3F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define D3F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
+#define D3F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define D3F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
+#define D3F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define D3F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
+#define D3F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define D3F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
+#define D3F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define D3F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
+#define D3F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define D3F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
+#define D3F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define D3F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
+#define D3F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define D3F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
+#define D3F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define D3F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
+#define D3F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define D3F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
+#define D3F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
+#define D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
+#define D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
+#define D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
+#define D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
+#define D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
+#define D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
+#define D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
+#define D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define D3F5_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
+#define D3F5_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
+#define D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
+#define D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
+#define D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
+#define D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define D3F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
+#define D3F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define D3F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
+#define D3F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define D3F5_VENDOR_ID__VENDOR_ID_MASK 0xffff
+#define D3F5_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define D3F5_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
+#define D3F5_DEVICE_ID__DEVICE_ID__SHIFT 0x10
+#define D3F5_COMMAND__IO_ACCESS_EN_MASK 0x1
+#define D3F5_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define D3F5_COMMAND__MEM_ACCESS_EN_MASK 0x2
+#define D3F5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define D3F5_COMMAND__BUS_MASTER_EN_MASK 0x4
+#define D3F5_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define D3F5_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
+#define D3F5_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define D3F5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
+#define D3F5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define D3F5_COMMAND__PAL_SNOOP_EN_MASK 0x20
+#define D3F5_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define D3F5_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
+#define D3F5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define D3F5_COMMAND__AD_STEPPING_MASK 0x80
+#define D3F5_COMMAND__AD_STEPPING__SHIFT 0x7
+#define D3F5_COMMAND__SERR_EN_MASK 0x100
+#define D3F5_COMMAND__SERR_EN__SHIFT 0x8
+#define D3F5_COMMAND__FAST_B2B_EN_MASK 0x200
+#define D3F5_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define D3F5_COMMAND__INT_DIS_MASK 0x400
+#define D3F5_COMMAND__INT_DIS__SHIFT 0xa
+#define D3F5_STATUS__INT_STATUS_MASK 0x80000
+#define D3F5_STATUS__INT_STATUS__SHIFT 0x13
+#define D3F5_STATUS__CAP_LIST_MASK 0x100000
+#define D3F5_STATUS__CAP_LIST__SHIFT 0x14
+#define D3F5_STATUS__PCI_66_EN_MASK 0x200000
+#define D3F5_STATUS__PCI_66_EN__SHIFT 0x15
+#define D3F5_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
+#define D3F5_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
+#define D3F5_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
+#define D3F5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
+#define D3F5_STATUS__DEVSEL_TIMING_MASK 0x6000000
+#define D3F5_STATUS__DEVSEL_TIMING__SHIFT 0x19
+#define D3F5_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
+#define D3F5_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
+#define D3F5_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
+#define D3F5_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
+#define D3F5_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
+#define D3F5_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
+#define D3F5_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
+#define D3F5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
+#define D3F5_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
+#define D3F5_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
+#define D3F5_REVISION_ID__MINOR_REV_ID_MASK 0xf
+#define D3F5_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define D3F5_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
+#define D3F5_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define D3F5_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
+#define D3F5_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
+#define D3F5_SUB_CLASS__SUB_CLASS_MASK 0xff0000
+#define D3F5_SUB_CLASS__SUB_CLASS__SHIFT 0x10
+#define D3F5_BASE_CLASS__BASE_CLASS_MASK 0xff000000
+#define D3F5_BASE_CLASS__BASE_CLASS__SHIFT 0x18
+#define D3F5_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
+#define D3F5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define D3F5_LATENCY__LATENCY_TIMER_MASK 0xff00
+#define D3F5_LATENCY__LATENCY_TIMER__SHIFT 0x8
+#define D3F5_HEADER__HEADER_TYPE_MASK 0x7f0000
+#define D3F5_HEADER__HEADER_TYPE__SHIFT 0x10
+#define D3F5_HEADER__DEVICE_TYPE_MASK 0x800000
+#define D3F5_HEADER__DEVICE_TYPE__SHIFT 0x17
+#define D3F5_BIST__BIST_COMP_MASK 0xf000000
+#define D3F5_BIST__BIST_COMP__SHIFT 0x18
+#define D3F5_BIST__BIST_STRT_MASK 0x40000000
+#define D3F5_BIST__BIST_STRT__SHIFT 0x1e
+#define D3F5_BIST__BIST_CAP_MASK 0x80000000
+#define D3F5_BIST__BIST_CAP__SHIFT 0x1f
+#define D3F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
+#define D3F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
+#define D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define D3F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
+#define D3F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
+#define D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define D3F5_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
+#define D3F5_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define D3F5_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
+#define D3F5_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define D3F5_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
+#define D3F5_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define D3F5_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
+#define D3F5_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define D3F5_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
+#define D3F5_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
+#define D3F5_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
+#define D3F5_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
+#define D3F5_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
+#define D3F5_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
+#define D3F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
+#define D3F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
+#define D3F5_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
+#define D3F5_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
+#define D3F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
+#define D3F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
+#define D3F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
+#define D3F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
+#define D3F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
+#define D3F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
+#define D3F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
+#define D3F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
+#define D3F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
+#define D3F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
+#define D3F5_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
+#define D3F5_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define D3F5_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
+#define D3F5_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define D3F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
+#define D3F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define D3F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
+#define D3F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
+#define D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
+#define D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
+#define D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
+#define D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define D3F5_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
+#define D3F5_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define D3F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
+#define D3F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define D3F5_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
+#define D3F5_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define D3F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
+#define D3F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define D3F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
+#define D3F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
+#define D3F5_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
+#define D3F5_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
+#define D3F5_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
+#define D3F5_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
+#define D3F5_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
+#define D3F5_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
+#define D3F5_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
+#define D3F5_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
+#define D3F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
+#define D3F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
+#define D3F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
+#define D3F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
+#define D3F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
+#define D3F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
+#define D3F5_CAP_PTR__CAP_PTR_MASK 0xff
+#define D3F5_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define D3F5_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
+#define D3F5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define D3F5_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
+#define D3F5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
+#define D3F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
+#define D3F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define D3F5_PMI_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F5_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F5_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F5_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F5_PMI_CAP__VERSION_MASK 0x70000
+#define D3F5_PMI_CAP__VERSION__SHIFT 0x10
+#define D3F5_PMI_CAP__PME_CLOCK_MASK 0x80000
+#define D3F5_PMI_CAP__PME_CLOCK__SHIFT 0x13
+#define D3F5_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
+#define D3F5_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
+#define D3F5_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
+#define D3F5_PMI_CAP__AUX_CURRENT__SHIFT 0x16
+#define D3F5_PMI_CAP__D1_SUPPORT_MASK 0x2000000
+#define D3F5_PMI_CAP__D1_SUPPORT__SHIFT 0x19
+#define D3F5_PMI_CAP__D2_SUPPORT_MASK 0x4000000
+#define D3F5_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
+#define D3F5_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
+#define D3F5_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
+#define D3F5_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
+#define D3F5_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define D3F5_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
+#define D3F5_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define D3F5_PMI_STATUS_CNTL__PME_EN_MASK 0x100
+#define D3F5_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define D3F5_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
+#define D3F5_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define D3F5_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
+#define D3F5_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define D3F5_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
+#define D3F5_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define D3F5_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
+#define D3F5_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define D3F5_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
+#define D3F5_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define D3F5_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
+#define D3F5_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define D3F5_PCIE_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F5_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F5_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F5_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F5_PCIE_CAP__VERSION_MASK 0xf0000
+#define D3F5_PCIE_CAP__VERSION__SHIFT 0x10
+#define D3F5_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
+#define D3F5_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
+#define D3F5_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
+#define D3F5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
+#define D3F5_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
+#define D3F5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
+#define D3F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
+#define D3F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define D3F5_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
+#define D3F5_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define D3F5_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
+#define D3F5_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define D3F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
+#define D3F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define D3F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
+#define D3F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define D3F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
+#define D3F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
+#define D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
+#define D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define D3F5_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
+#define D3F5_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define D3F5_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
+#define D3F5_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define D3F5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
+#define D3F5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define D3F5_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
+#define D3F5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define D3F5_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
+#define D3F5_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define D3F5_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
+#define D3F5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define D3F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
+#define D3F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define D3F5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
+#define D3F5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define D3F5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
+#define D3F5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define D3F5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
+#define D3F5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define D3F5_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
+#define D3F5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define D3F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
+#define D3F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define D3F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
+#define D3F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define D3F5_DEVICE_STATUS__CORR_ERR_MASK 0x10000
+#define D3F5_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
+#define D3F5_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
+#define D3F5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
+#define D3F5_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
+#define D3F5_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
+#define D3F5_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
+#define D3F5_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
+#define D3F5_DEVICE_STATUS__AUX_PWR_MASK 0x100000
+#define D3F5_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
+#define D3F5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
+#define D3F5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
+#define D3F5_LINK_CAP__LINK_SPEED_MASK 0xf
+#define D3F5_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define D3F5_LINK_CAP__LINK_WIDTH_MASK 0x3f0
+#define D3F5_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define D3F5_LINK_CAP__PM_SUPPORT_MASK 0xc00
+#define D3F5_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define D3F5_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
+#define D3F5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define D3F5_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
+#define D3F5_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define D3F5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
+#define D3F5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define D3F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
+#define D3F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define D3F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
+#define D3F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define D3F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
+#define D3F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define D3F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
+#define D3F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define D3F5_LINK_CAP__PORT_NUMBER_MASK 0xff000000
+#define D3F5_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define D3F5_LINK_CNTL__PM_CONTROL_MASK 0x3
+#define D3F5_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define D3F5_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
+#define D3F5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define D3F5_LINK_CNTL__LINK_DIS_MASK 0x10
+#define D3F5_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define D3F5_LINK_CNTL__RETRAIN_LINK_MASK 0x20
+#define D3F5_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define D3F5_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
+#define D3F5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define D3F5_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
+#define D3F5_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define D3F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
+#define D3F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define D3F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
+#define D3F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define D3F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
+#define D3F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define D3F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
+#define D3F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define D3F5_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
+#define D3F5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
+#define D3F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
+#define D3F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
+#define D3F5_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
+#define D3F5_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
+#define D3F5_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
+#define D3F5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
+#define D3F5_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
+#define D3F5_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
+#define D3F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
+#define D3F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
+#define D3F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
+#define D3F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
+#define D3F5_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
+#define D3F5_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define D3F5_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
+#define D3F5_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define D3F5_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
+#define D3F5_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define D3F5_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
+#define D3F5_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define D3F5_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
+#define D3F5_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define D3F5_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
+#define D3F5_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define D3F5_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
+#define D3F5_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define D3F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
+#define D3F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define D3F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
+#define D3F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define D3F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
+#define D3F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define D3F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
+#define D3F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define D3F5_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
+#define D3F5_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define D3F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
+#define D3F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define D3F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
+#define D3F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define D3F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
+#define D3F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define D3F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
+#define D3F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define D3F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
+#define D3F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define D3F5_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
+#define D3F5_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define D3F5_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
+#define D3F5_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define D3F5_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
+#define D3F5_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define D3F5_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
+#define D3F5_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define D3F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
+#define D3F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define D3F5_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
+#define D3F5_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define D3F5_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
+#define D3F5_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
+#define D3F5_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
+#define D3F5_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
+#define D3F5_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
+#define D3F5_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
+#define D3F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
+#define D3F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
+#define D3F5_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
+#define D3F5_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
+#define D3F5_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
+#define D3F5_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
+#define D3F5_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
+#define D3F5_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
+#define D3F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
+#define D3F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
+#define D3F5_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
+#define D3F5_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
+#define D3F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
+#define D3F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define D3F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
+#define D3F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define D3F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
+#define D3F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define D3F5_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
+#define D3F5_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define D3F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
+#define D3F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define D3F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
+#define D3F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
+#define D3F5_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
+#define D3F5_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define D3F5_ROOT_STATUS__PME_STATUS_MASK 0x10000
+#define D3F5_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define D3F5_ROOT_STATUS__PME_PENDING_MASK 0x20000
+#define D3F5_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define D3F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
+#define D3F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define D3F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
+#define D3F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define D3F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
+#define D3F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define D3F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
+#define D3F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define D3F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
+#define D3F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define D3F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
+#define D3F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define D3F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
+#define D3F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define D3F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
+#define D3F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define D3F5_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
+#define D3F5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define D3F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
+#define D3F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define D3F5_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
+#define D3F5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define D3F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
+#define D3F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define D3F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
+#define D3F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define D3F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
+#define D3F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define D3F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
+#define D3F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define D3F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
+#define D3F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define D3F5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
+#define D3F5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define D3F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
+#define D3F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define D3F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
+#define D3F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define D3F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
+#define D3F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define D3F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
+#define D3F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define D3F5_DEVICE_CNTL2__LTR_EN_MASK 0x400
+#define D3F5_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define D3F5_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
+#define D3F5_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define D3F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
+#define D3F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define D3F5_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
+#define D3F5_DEVICE_STATUS2__RESERVED__SHIFT 0x10
+#define D3F5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
+#define D3F5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define D3F5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
+#define D3F5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define D3F5_LINK_CAP2__RESERVED_MASK 0xfffffe00
+#define D3F5_LINK_CAP2__RESERVED__SHIFT 0x9
+#define D3F5_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
+#define D3F5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define D3F5_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
+#define D3F5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define D3F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
+#define D3F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define D3F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
+#define D3F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define D3F5_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
+#define D3F5_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define D3F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
+#define D3F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define D3F5_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
+#define D3F5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define D3F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
+#define D3F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define D3F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
+#define D3F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
+#define D3F5_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
+#define D3F5_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
+#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
+#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
+#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
+#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
+#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
+#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
+#define D3F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
+#define D3F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
+#define D3F5_SLOT_CAP2__RESERVED_MASK 0xffffffff
+#define D3F5_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define D3F5_SLOT_CNTL2__RESERVED_MASK 0xffff
+#define D3F5_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define D3F5_SLOT_STATUS2__RESERVED_MASK 0xffff0000
+#define D3F5_SLOT_STATUS2__RESERVED__SHIFT 0x10
+#define D3F5_MSI_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F5_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F5_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F5_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F5_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
+#define D3F5_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
+#define D3F5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
+#define D3F5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
+#define D3F5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
+#define D3F5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
+#define D3F5_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
+#define D3F5_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
+#define D3F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
+#define D3F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
+#define D3F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
+#define D3F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define D3F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
+#define D3F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define D3F5_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
+#define D3F5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define D3F5_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
+#define D3F5_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define D3F5_SSID_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F5_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F5_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F5_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F5_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
+#define D3F5_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define D3F5_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
+#define D3F5_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define D3F5_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
+#define D3F5_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F5_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
+#define D3F5_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define D3F5_MSI_MAP_CAP__EN_MASK 0x10000
+#define D3F5_MSI_MAP_CAP__EN__SHIFT 0x10
+#define D3F5_MSI_MAP_CAP__FIXD_MASK 0x20000
+#define D3F5_MSI_MAP_CAP__FIXD__SHIFT 0x11
+#define D3F5_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
+#define D3F5_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
+#define D3F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
+#define D3F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
+#define D3F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
+#define D3F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
+#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
+#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
+#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
+#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define D3F5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
+#define D3F5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define D3F5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
+#define D3F5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define D3F5_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F5_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F5_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F5_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
+#define D3F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define D3F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
+#define D3F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define D3F5_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
+#define D3F5_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define D3F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
+#define D3F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
+#define D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D3F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
+#define D3F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define D3F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
+#define D3F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define D3F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
+#define D3F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
+#define D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define D3F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define D3F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define D3F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define D3F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define D3F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define D3F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define D3F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define D3F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define D3F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
+#define D3F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
+#define D3F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
+#define D3F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
+#define D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
+#define D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define D3F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
+#define D3F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define D3F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
+#define D3F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
+#define D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
+#define D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
+#define D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define D3F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
+#define D3F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define D3F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
+#define D3F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
+#define D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
+#define D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define D3F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
+#define D3F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
+#define D3F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
+#define D3F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
+#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
+#define D3F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define D3F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
+#define D3F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
+#define D3F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define D3F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
+#define D3F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define D3F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
+#define D3F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define D3F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
+#define D3F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define D3F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
+#define D3F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define D3F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
+#define D3F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define D3F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
+#define D3F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define D3F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
+#define D3F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define D3F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
+#define D3F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define D3F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
+#define D3F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define D3F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
+#define D3F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define D3F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
+#define D3F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define D3F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
+#define D3F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define D3F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
+#define D3F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define D3F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
+#define D3F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define D3F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
+#define D3F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define D3F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
+#define D3F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define D3F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
+#define D3F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define D3F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
+#define D3F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define D3F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
+#define D3F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define D3F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
+#define D3F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define D3F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
+#define D3F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define D3F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
+#define D3F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define D3F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
+#define D3F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define D3F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
+#define D3F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define D3F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
+#define D3F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define D3F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
+#define D3F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define D3F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
+#define D3F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define D3F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
+#define D3F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define D3F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
+#define D3F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define D3F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
+#define D3F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define D3F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
+#define D3F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
+#define D3F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define D3F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
+#define D3F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define D3F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
+#define D3F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define D3F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
+#define D3F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define D3F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
+#define D3F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define D3F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
+#define D3F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define D3F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
+#define D3F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define D3F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
+#define D3F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define D3F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
+#define D3F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define D3F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
+#define D3F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define D3F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
+#define D3F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define D3F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
+#define D3F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define D3F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
+#define D3F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define D3F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
+#define D3F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define D3F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
+#define D3F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define D3F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
+#define D3F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define D3F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
+#define D3F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define D3F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
+#define D3F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
+#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
+#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
+#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
+#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
+#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
+#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
+#define D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
+#define D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define D3F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
+#define D3F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define D3F5_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
+#define D3F5_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define D3F5_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
+#define D3F5_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define D3F5_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
+#define D3F5_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define D3F5_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
+#define D3F5_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define D3F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
+#define D3F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define D3F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
+#define D3F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define D3F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
+#define D3F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define D3F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
+#define D3F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
+#define D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define D3F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
+#define D3F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
+#define D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define D3F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
+#define D3F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define D3F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
+#define D3F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define D3F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
+#define D3F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define D3F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
+#define D3F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define D3F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
+#define D3F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define D3F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
+#define D3F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define D3F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
+#define D3F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define D3F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
+#define D3F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define D3F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
+#define D3F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define D3F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
+#define D3F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
+#define D3F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define D3F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
+#define D3F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define D3F5_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
+#define D3F5_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
+#define D3F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
+#define D3F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define D3F5_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
+#define D3F5_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
+#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
+#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
+#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
+#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
+#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
+#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
+#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
+#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
+#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
+#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
+#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
+#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
+#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
+#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
+#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
+#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
+#define D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F5_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
+#define D3F5_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define D3F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
+#define D3F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define D3F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
+#define D3F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define D3F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
+#define D3F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define D3F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
+#define D3F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define D3F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
+#define D3F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define D3F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
+#define D3F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define D3F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
+#define D3F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define D3F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
+#define D3F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
+#define D3F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
+#define D3F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
+#define D3F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
+#define D3F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
+#define D3F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
+#define D3F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
+#define D3F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
+#define D3F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
+#define D3F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
+#define D3F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
+#define D3F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
+#define D3F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
+#define D3F5_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
+#define D3F5_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define D3F5_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
+#define D3F5_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define D3F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
+#define D3F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define D3F5_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
+#define D3F5_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define D3F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
+#define D3F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define D3F5_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
+#define D3F5_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
+#define D3F5_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
+#define D3F5_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
+#define D3F5_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
+#define D3F5_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define D3F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
+#define D3F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define D3F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
+#define D3F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define D3F5_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
+#define D3F5_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define D3F5_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
+#define D3F5_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define D3F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
+#define D3F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define D3F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
+#define D3F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define D3F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
+#define D3F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define D3F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
+#define D3F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
+#define D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
+#define D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define D3F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
+#define D3F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define C_PCIE_INDEX__PCIE_INDEX_MASK 0xffffffff
+#define C_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
+#define C_PCIE_DATA__PCIE_DATA_MASK 0xffffffff
+#define C_PCIE_DATA__PCIE_DATA__SHIFT 0x0
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN_MASK 0x2
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN__SHIFT 0x1
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN_MASK 0x4
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN__SHIFT 0x2
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE_MASK 0x8
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE__SHIFT 0x3
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG_MASK 0x20
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG__SHIFT 0x5
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN_MASK 0x200
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN__SHIFT 0x9
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED_MASK 0x800
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED__SHIFT 0xb
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN_MASK 0x2000
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN__SHIFT 0xd
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN_MASK 0x200000
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN__SHIFT 0x15
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN_MASK 0x800000
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN__SHIFT 0x17
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN_MASK 0x10000000
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN__SHIFT 0x1c
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED_MASK 0x20000000
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED__SHIFT 0x1d
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED_MASK 0xc0000000
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED__SHIFT 0x1e
+#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG_MASK 0x1ff8
+#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG__SHIFT 0x3
+#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ_MASK 0x6000
+#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ__SHIFT 0xd
+#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG_MASK 0x1f8000
+#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG__SHIFT 0xf
+#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS_MASK 0x200000
+#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS__SHIFT 0x15
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK_MASK 0x2
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK__SHIFT 0x1
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE_MASK 0xc
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE__SHIFT 0x2
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE_MASK 0x10
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE__SHIFT 0x4
+#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE_MASK 0x400
+#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE__SHIFT 0xa
+#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE_MASK 0x800
+#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE__SHIFT 0xb
+#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN_MASK 0x2000
+#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN__SHIFT 0xd
+#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN_MASK 0x4000
+#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN__SHIFT 0xe
+#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x18000
+#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0xf
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR_MASK 0x1
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR__SHIFT 0x0
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR_MASK 0x2
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR__SHIFT 0x1
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR_MASK 0x4
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR_MASK 0x10
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR_MASK 0x20
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR_MASK 0x40
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR__SHIFT 0x6
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR_MASK 0x200
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR__SHIFT 0x9
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR_MASK 0x1000
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR__SHIFT 0xc
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS_MASK 0x10000
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS__SHIFT 0x10
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN_MASK 0x20000
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN__SHIFT 0x11
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN_MASK 0x40000
+#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN__SHIFT 0x12
+#define PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE_MASK 0x4000000
+#define PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE__SHIFT 0x1a
+#define PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL_MASK 0xc0000000
+#define PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL__SHIFT 0x1e
+#define PSX80_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT_MASK 0x1
+#define PSX80_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT__SHIFT 0x0
+#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN_MASK 0x1
+#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN__SHIFT 0x0
+#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION_MASK 0x2
+#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION__SHIFT 0x1
+#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING_MASK 0x4
+#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING__SHIFT 0x2
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3_MASK 0x1
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3__SHIFT 0x0
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN_MASK 0x4
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN__SHIFT 0x2
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x8
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x3
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP_MASK 0x70
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP__SHIFT 0x4
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x80
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x7
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS_MASK 0x100
+#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS__SHIFT 0x8
+#define PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID_MASK 0xffff
+#define PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID__SHIFT 0x0
+#define PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID_MASK 0xffff0000
+#define PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID__SHIFT 0x10
+#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x7
+#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0
+#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x38
+#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x3
+#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_MASK 0x3c0
+#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x6
+#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_MASK 0x3c00
+#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET__SHIFT 0xa
+#define PSX80_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG_MASK 0xf
+#define PSX80_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG__SHIFT 0x0
+#define PSX80_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING_MASK 0x1
+#define PSX80_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING__SHIFT 0x0
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
+#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT_MASK 0xc000
+#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
+#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
+#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
+#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
+#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
+#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
+#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN_MASK 0x80
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
+#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
+#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
+#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
+#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
+#define PSX80_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB_MASK 0x1
+#define PSX80_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB__SHIFT 0x0
+#define PSX80_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING_MASK 0x1
+#define PSX80_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING__SHIFT 0x0
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
+#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT_MASK 0xc000
+#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
+#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
+#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
+#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
+#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
+#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
+#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN_MASK 0x80
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
+#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
+#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
+#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
+#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
+#define PSX80_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB_MASK 0x1
+#define PSX80_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB__SHIFT 0x0
+#define PSX80_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING_MASK 0x1
+#define PSX80_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING__SHIFT 0x0
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
+#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT_MASK 0xc000
+#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
+#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
+#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
+#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
+#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
+#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
+#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN_MASK 0x80
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
+#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
+#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
+#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
+#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
+#define PSX80_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB_MASK 0x1
+#define PSX80_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB__SHIFT 0x0
+#define PSX80_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING_MASK 0x1
+#define PSX80_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING__SHIFT 0x0
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
+#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT_MASK 0xc000
+#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
+#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
+#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
+#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
+#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
+#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
+#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN_MASK 0x80
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
+#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
+#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
+#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
+#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
+#define PSX80_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB_MASK 0x1
+#define PSX80_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB__SHIFT 0x0
+#define PSX80_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING_MASK 0x1
+#define PSX80_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING__SHIFT 0x0
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
+#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
+#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT_MASK 0xc000
+#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
+#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
+#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
+#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
+#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
+#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
+#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
+#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN_MASK 0x80
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
+#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
+#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
+#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
+#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
+#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
+#define PSX80_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB_MASK 0x1
+#define PSX80_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB__SHIFT 0x0
+#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0_MASK 0x1
+#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0__SHIFT 0x0
+#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1_MASK 0x2
+#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1__SHIFT 0x1
+#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2_MASK 0x4
+#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2__SHIFT 0x2
+#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3_MASK 0x8
+#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3__SHIFT 0x3
+#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4_MASK 0x10
+#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4__SHIFT 0x4
+#define PSX80_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0_MASK 0xffffff
+#define PSX80_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0__SHIFT 0x0
+#define PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0_MASK 0x7
+#define PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0__SHIFT 0x0
+#define PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4_MASK 0x70
+#define PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4__SHIFT 0x4
+#define PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0_MASK 0xffff
+#define PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0__SHIFT 0x0
+#define PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16_MASK 0xffff0000
+#define PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16__SHIFT 0x10
+#define PSX80_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC_MASK 0xffffffff
+#define PSX80_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC__SHIFT 0x0
+#define PSX80_WRP_LNC_BW_WACC__LNC_BW_WACC_MASK 0xffffffff
+#define PSX80_WRP_LNC_BW_WACC__LNC_BW_WACC__SHIFT 0x0
+#define PSX80_WRP_LNC_CMN_WACC__LNC_CMN_WACC_MASK 0xffffffff
+#define PSX80_WRP_LNC_CMN_WACC__LNC_CMN_WACC__SHIFT 0x0
+#define PSX80_WRP_PCIE_EFUSE__PCIE_EFUSE_MASK 0xffffffff
+#define PSX80_WRP_PCIE_EFUSE__PCIE_EFUSE__SHIFT 0x0
+#define PSX80_WRP_PCIE_EFUSE2__PCIE_EFUSE2_MASK 0xffffffff
+#define PSX80_WRP_PCIE_EFUSE2__PCIE_EFUSE2__SHIFT 0x0
+#define PSX80_WRP_PCIE_EFUSE3__PCIE_EFUSE3_MASK 0xffffffff
+#define PSX80_WRP_PCIE_EFUSE3__PCIE_EFUSE3__SHIFT 0x0
+#define PSX80_WRP_PCIE_EFUSE4__PCIE_EFUSE4_MASK 0xffffffff
+#define PSX80_WRP_PCIE_EFUSE4__PCIE_EFUSE4__SHIFT 0x0
+#define PSX80_WRP_PCIE_EFUSE5__PCIE_EFUSE5_MASK 0xffffffff
+#define PSX80_WRP_PCIE_EFUSE5__PCIE_EFUSE5__SHIFT 0x0
+#define PSX80_WRP_PCIE_EFUSE6__PCIE_EFUSE6_MASK 0xffffffff
+#define PSX80_WRP_PCIE_EFUSE6__PCIE_EFUSE6__SHIFT 0x0
+#define PSX80_WRP_PCIE_EFUSE7__PCIE_EFUSE7_MASK 0xffffffff
+#define PSX80_WRP_PCIE_EFUSE7__PCIE_EFUSE7__SHIFT 0x0
+#define PSX80_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1_MASK 0xffffffff
+#define PSX80_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1__SHIFT 0x0
+#define PSX80_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2_MASK 0xffffffff
+#define PSX80_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2__SHIFT 0x0
+#define PSX80_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK_MASK 0x1
+#define PSX80_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK__SHIFT 0x0
+#define PSX80_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE_MASK 0x1
+#define PSX80_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE__SHIFT 0x0
+#define PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN_MASK 0x1
+#define PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN__SHIFT 0x0
+#define PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN_MASK 0x2
+#define PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN__SHIFT 0x1
+#define PSX80_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY_MASK 0x2
+#define PSX80_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY__SHIFT 0x1
+#define PSX80_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START_MASK 0x4
+#define PSX80_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START__SHIFT 0x2
+#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI_MASK 0x7
+#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI__SHIFT 0x0
+#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI_MASK 0x70
+#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI__SHIFT 0x4
+#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI_MASK 0x80
+#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI__SHIFT 0x7
+#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI_MASK 0x100
+#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI__SHIFT 0x8
+#define PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal_MASK 0xff
+#define PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal__SHIFT 0x0
+#define PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn_MASK 0x10000
+#define PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn__SHIFT 0x10
+#define PSX80_WRP_IMPCTL_CNTL_PIF0__ArbEn0_MASK 0x1
+#define PSX80_WRP_IMPCTL_CNTL_PIF0__ArbEn0__SHIFT 0x0
+#define PSX80_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0_MASK 0x800
+#define PSX80_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0__SHIFT 0xb
+#define PSX80_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0_MASK 0x1
+#define PSX80_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0__SHIFT 0x0
+#define PSX80_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt_MASK 0x1
+#define PSX80_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt__SHIFT 0x0
+#define PSX80_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr_MASK 0x1
+#define PSX80_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr__SHIFT 0x0
+#define PSX80_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0_MASK 0x1
+#define PSX80_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0__SHIFT 0x0
+#define PSX80_WRP_BIOSTIMER_CMD__Microseconds_MASK 0xffffffff
+#define PSX80_WRP_BIOSTIMER_CMD__Microseconds__SHIFT 0x0
+#define PSX80_WRP_BIOSTIMER_CNTL__ClockRate_MASK 0xff
+#define PSX80_WRP_BIOSTIMER_CNTL__ClockRate__SHIFT 0x0
+#define PSX80_WRP_BIOSTIMER_DEBUG__Microseconds_compare_MASK 0xffffffff
+#define PSX80_WRP_BIOSTIMER_DEBUG__Microseconds_compare__SHIFT 0x0
+#define PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl_MASK 0xff
+#define PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl__SHIFT 0x0
+#define PSX80_WRP_DTM_RX_BP_CNTL__Dbg_Cntl_MASK 0xf0000
+#define PSX80_WRP_DTM_RX_BP_CNTL__Dbg_Cntl__SHIFT 0x10
+#define PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue_MASK 0xf00000
+#define PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue__SHIFT 0x14
+#define PSX80_WRP_DTM_RX_BP_CNTL__td_hold_training_override_MASK 0x1f000000
+#define PSX80_WRP_DTM_RX_BP_CNTL__td_hold_training_override__SHIFT 0x18
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy0_MASK 0x1
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy0__SHIFT 0x0
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy1_MASK 0x2
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy1__SHIFT 0x1
+#define PSX80_WRP_DTM_CNTL__Determinism_En_DTM_MASK 0x4
+#define PSX80_WRP_DTM_CNTL__Determinism_En_DTM__SHIFT 0x2
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy2_MASK 0x8
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy2__SHIFT 0x3
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy3_MASK 0x10
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy3__SHIFT 0x4
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy4_MASK 0x20
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy4__SHIFT 0x5
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy5_MASK 0x40
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy5__SHIFT 0x6
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy6_MASK 0x80
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy6__SHIFT 0x7
+#define PSX80_WRP_DTM_CNTL__TxClk1x_Cntl_MASK 0x300
+#define PSX80_WRP_DTM_CNTL__TxClk1x_Cntl__SHIFT 0x8
+#define PSX80_WRP_DTM_CNTL__TxClkGskt_Cntl_MASK 0xc00
+#define PSX80_WRP_DTM_CNTL__TxClkGskt_Cntl__SHIFT 0xa
+#define PSX80_WRP_DTM_CNTL__refClk_Cntl_MASK 0x3000
+#define PSX80_WRP_DTM_CNTL__refClk_Cntl__SHIFT 0xc
+#define PSX80_WRP_DTM_CNTL__dtmClk_Sel_Timer_MASK 0xc000
+#define PSX80_WRP_DTM_CNTL__dtmClk_Sel_Timer__SHIFT 0xe
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy7_MASK 0x10000
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy7__SHIFT 0x10
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy8_MASK 0x20000
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy8__SHIFT 0x11
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy9_MASK 0x40000
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy9__SHIFT 0x12
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy10_MASK 0x80000
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy10__SHIFT 0x13
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy11_MASK 0x100000
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy11__SHIFT 0x14
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy12_MASK 0x200000
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy12__SHIFT 0x15
+#define PSX80_WRP_DTM_CNTL__rxElasWidth_Cntl_MASK 0xc00000
+#define PSX80_WRP_DTM_CNTL__rxElasWidth_Cntl__SHIFT 0x16
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy13_MASK 0x1000000
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy13__SHIFT 0x18
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy14_MASK 0x2000000
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy14__SHIFT 0x19
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy15_MASK 0x4000000
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy15__SHIFT 0x1a
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy16_MASK 0x8000000
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy16__SHIFT 0x1b
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy17_MASK 0x10000000
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy17__SHIFT 0x1c
+#define PSX80_WRP_DTM_CNTL__Warm_RstTimer_MASK 0x60000000
+#define PSX80_WRP_DTM_CNTL__Warm_RstTimer__SHIFT 0x1d
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy18_MASK 0x80000000
+#define PSX80_WRP_DTM_CNTL__Dtm_Dummy18__SHIFT 0x1f
+#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19_MASK 0x1
+#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19__SHIFT 0x0
+#define PSX80_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout_MASK 0x2
+#define PSX80_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout__SHIFT 0x1
+#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym_MASK 0x4
+#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym__SHIFT 0x2
+#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym_MASK 0x8
+#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym__SHIFT 0x3
+#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide_MASK 0x30
+#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide__SHIFT 0x4
+#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide_MASK 0xc0
+#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide__SHIFT 0x6
+#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide_MASK 0x300
+#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide__SHIFT 0x8
+#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period_MASK 0xf000
+#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period__SHIFT 0xc
+#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send_MASK 0xf0000
+#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send__SHIFT 0x10
+#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv_MASK 0xf00000
+#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv__SHIFT 0x14
+#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period_MASK 0x1ff
+#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period__SHIFT 0x0
+#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send_MASK 0x3fe00
+#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send__SHIFT 0x9
+#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv_MASK 0x7fc0000
+#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv__SHIFT 0x12
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x_MASK 0xff
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x__SHIFT 0x0
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x_MASK 0xff00
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x__SHIFT 0x8
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x_MASK 0xff0000
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x__SHIFT 0x10
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt_MASK 0xff
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt__SHIFT 0x0
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt_MASK 0xff00
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt__SHIFT 0x8
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt_MASK 0xff0000
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt__SHIFT 0x10
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x_MASK 0xff
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x__SHIFT 0x0
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x_MASK 0xff00
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x__SHIFT 0x8
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x_MASK 0xff0000
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x__SHIFT 0x10
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt_MASK 0xff
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt__SHIFT 0x0
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt_MASK 0xff00
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt__SHIFT 0x8
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt_MASK 0xff0000
+#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt__SHIFT 0x10
+#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz_MASK 0x1
+#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz__SHIFT 0x0
+#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock_MASK 0x2
+#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock__SHIFT 0x1
+#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase_MASK 0x4
+#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase__SHIFT 0x2
+#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay_MASK 0x8
+#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay__SHIFT 0x3
+#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride_MASK 0xff00
+#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride__SHIFT 0x8
+#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle_MASK 0x10000
+#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle__SHIFT 0x10
+#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart_MASK 0x20000
+#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart__SHIFT 0x11
+#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart_MASK 0x40000
+#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart__SHIFT 0x12
+#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable_MASK 0x100000
+#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable__SHIFT 0x14
+#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable_MASK 0x200000
+#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable__SHIFT 0x15
+#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_spare_MASK 0xf0000000
+#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_spare__SHIFT 0x1c
+#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle_MASK 0x1
+#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle__SHIFT 0x0
+#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete_MASK 0x2
+#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete__SHIFT 0x1
+#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked_MASK 0x4
+#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked__SHIFT 0x2
+#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld_MASK 0x8
+#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld__SHIFT 0x3
+#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld_MASK 0x10
+#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld__SHIFT 0x4
+#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue_MASK 0xff00
+#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue__SHIFT 0x8
+#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue_MASK 0xff0000
+#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue__SHIFT 0x10
+#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio_MASK 0x1f000000
+#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio__SHIFT 0x18
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN_MASK 0x2
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN__SHIFT 0x1
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN_MASK 0x4
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN__SHIFT 0x2
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE_MASK 0x8
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE__SHIFT 0x3
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG_MASK 0x20
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG__SHIFT 0x5
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN_MASK 0x200
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN__SHIFT 0x9
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED_MASK 0x800
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED__SHIFT 0xb
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN_MASK 0x2000
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN__SHIFT 0xd
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN_MASK 0x200000
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN__SHIFT 0x15
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN_MASK 0x800000
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN__SHIFT 0x17
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN_MASK 0x10000000
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN__SHIFT 0x1c
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED_MASK 0x20000000
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED__SHIFT 0x1d
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED_MASK 0xc0000000
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED__SHIFT 0x1e
+#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG_MASK 0x1ff8
+#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG__SHIFT 0x3
+#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ_MASK 0x6000
+#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ__SHIFT 0xd
+#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG_MASK 0x1f8000
+#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG__SHIFT 0xf
+#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS_MASK 0x200000
+#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS__SHIFT 0x15
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK_MASK 0x2
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK__SHIFT 0x1
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE_MASK 0xc
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE__SHIFT 0x2
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE_MASK 0x10
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE__SHIFT 0x4
+#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE_MASK 0x400
+#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE__SHIFT 0xa
+#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE_MASK 0x800
+#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE__SHIFT 0xb
+#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN_MASK 0x2000
+#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN__SHIFT 0xd
+#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN_MASK 0x4000
+#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN__SHIFT 0xe
+#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x18000
+#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0xf
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR_MASK 0x1
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR__SHIFT 0x0
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR_MASK 0x2
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR__SHIFT 0x1
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR_MASK 0x4
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR_MASK 0x10
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR_MASK 0x20
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR_MASK 0x40
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR__SHIFT 0x6
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR_MASK 0x200
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR__SHIFT 0x9
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR_MASK 0x1000
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR__SHIFT 0xc
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS_MASK 0x10000
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS__SHIFT 0x10
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN_MASK 0x20000
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN__SHIFT 0x11
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN_MASK 0x40000
+#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN__SHIFT 0x12
+#define PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE_MASK 0x4000000
+#define PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE__SHIFT 0x1a
+#define PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL_MASK 0xc0000000
+#define PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL__SHIFT 0x1e
+#define PSX81_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT_MASK 0x1
+#define PSX81_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT__SHIFT 0x0
+#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN_MASK 0x1
+#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN__SHIFT 0x0
+#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION_MASK 0x2
+#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION__SHIFT 0x1
+#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING_MASK 0x4
+#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING__SHIFT 0x2
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3_MASK 0x1
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3__SHIFT 0x0
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN_MASK 0x4
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN__SHIFT 0x2
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x8
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x3
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP_MASK 0x70
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP__SHIFT 0x4
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x80
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x7
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS_MASK 0x100
+#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS__SHIFT 0x8
+#define PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID_MASK 0xffff
+#define PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID__SHIFT 0x0
+#define PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID_MASK 0xffff0000
+#define PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID__SHIFT 0x10
+#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x7
+#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0
+#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x38
+#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x3
+#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_MASK 0x3c0
+#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x6
+#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_MASK 0x3c00
+#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET__SHIFT 0xa
+#define PSX81_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG_MASK 0xf
+#define PSX81_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG__SHIFT 0x0
+#define PSX81_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING_MASK 0x1
+#define PSX81_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING__SHIFT 0x0
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
+#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT_MASK 0xc000
+#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
+#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
+#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
+#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
+#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
+#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
+#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN_MASK 0x80
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
+#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
+#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
+#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
+#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
+#define PSX81_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB_MASK 0x1
+#define PSX81_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB__SHIFT 0x0
+#define PSX81_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING_MASK 0x1
+#define PSX81_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING__SHIFT 0x0
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
+#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT_MASK 0xc000
+#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
+#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
+#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
+#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
+#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
+#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
+#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN_MASK 0x80
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
+#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
+#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
+#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
+#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
+#define PSX81_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB_MASK 0x1
+#define PSX81_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB__SHIFT 0x0
+#define PSX81_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING_MASK 0x1
+#define PSX81_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING__SHIFT 0x0
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
+#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT_MASK 0xc000
+#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
+#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
+#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
+#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
+#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
+#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
+#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN_MASK 0x80
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
+#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
+#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
+#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
+#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
+#define PSX81_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB_MASK 0x1
+#define PSX81_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB__SHIFT 0x0
+#define PSX81_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING_MASK 0x1
+#define PSX81_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING__SHIFT 0x0
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
+#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT_MASK 0xc000
+#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
+#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
+#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
+#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
+#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
+#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
+#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN_MASK 0x80
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
+#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
+#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
+#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
+#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
+#define PSX81_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB_MASK 0x1
+#define PSX81_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB__SHIFT 0x0
+#define PSX81_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING_MASK 0x1
+#define PSX81_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING__SHIFT 0x0
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
+#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
+#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT_MASK 0xc000
+#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
+#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
+#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
+#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
+#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
+#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
+#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
+#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN_MASK 0x80
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
+#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
+#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
+#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
+#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
+#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
+#define PSX81_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB_MASK 0x1
+#define PSX81_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB__SHIFT 0x0
+#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0_MASK 0x1
+#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0__SHIFT 0x0
+#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1_MASK 0x2
+#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1__SHIFT 0x1
+#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2_MASK 0x4
+#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2__SHIFT 0x2
+#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3_MASK 0x8
+#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3__SHIFT 0x3
+#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4_MASK 0x10
+#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4__SHIFT 0x4
+#define PSX81_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0_MASK 0xffffff
+#define PSX81_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0__SHIFT 0x0
+#define PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0_MASK 0x7
+#define PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0__SHIFT 0x0
+#define PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4_MASK 0x70
+#define PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4__SHIFT 0x4
+#define PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0_MASK 0xffff
+#define PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0__SHIFT 0x0
+#define PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16_MASK 0xffff0000
+#define PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16__SHIFT 0x10
+#define PSX81_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC_MASK 0xffffffff
+#define PSX81_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC__SHIFT 0x0
+#define PSX81_WRP_LNC_BW_WACC__LNC_BW_WACC_MASK 0xffffffff
+#define PSX81_WRP_LNC_BW_WACC__LNC_BW_WACC__SHIFT 0x0
+#define PSX81_WRP_LNC_CMN_WACC__LNC_CMN_WACC_MASK 0xffffffff
+#define PSX81_WRP_LNC_CMN_WACC__LNC_CMN_WACC__SHIFT 0x0
+#define PSX81_WRP_PCIE_EFUSE__PCIE_EFUSE_MASK 0xffffffff
+#define PSX81_WRP_PCIE_EFUSE__PCIE_EFUSE__SHIFT 0x0
+#define PSX81_WRP_PCIE_EFUSE2__PCIE_EFUSE2_MASK 0xffffffff
+#define PSX81_WRP_PCIE_EFUSE2__PCIE_EFUSE2__SHIFT 0x0
+#define PSX81_WRP_PCIE_EFUSE3__PCIE_EFUSE3_MASK 0xffffffff
+#define PSX81_WRP_PCIE_EFUSE3__PCIE_EFUSE3__SHIFT 0x0
+#define PSX81_WRP_PCIE_EFUSE4__PCIE_EFUSE4_MASK 0xffffffff
+#define PSX81_WRP_PCIE_EFUSE4__PCIE_EFUSE4__SHIFT 0x0
+#define PSX81_WRP_PCIE_EFUSE5__PCIE_EFUSE5_MASK 0xffffffff
+#define PSX81_WRP_PCIE_EFUSE5__PCIE_EFUSE5__SHIFT 0x0
+#define PSX81_WRP_PCIE_EFUSE6__PCIE_EFUSE6_MASK 0xffffffff
+#define PSX81_WRP_PCIE_EFUSE6__PCIE_EFUSE6__SHIFT 0x0
+#define PSX81_WRP_PCIE_EFUSE7__PCIE_EFUSE7_MASK 0xffffffff
+#define PSX81_WRP_PCIE_EFUSE7__PCIE_EFUSE7__SHIFT 0x0
+#define PSX81_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1_MASK 0xffffffff
+#define PSX81_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1__SHIFT 0x0
+#define PSX81_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2_MASK 0xffffffff
+#define PSX81_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2__SHIFT 0x0
+#define PSX81_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK_MASK 0x1
+#define PSX81_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK__SHIFT 0x0
+#define PSX81_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE_MASK 0x1
+#define PSX81_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE__SHIFT 0x0
+#define PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN_MASK 0x1
+#define PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN__SHIFT 0x0
+#define PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN_MASK 0x2
+#define PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN__SHIFT 0x1
+#define PSX81_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY_MASK 0x2
+#define PSX81_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY__SHIFT 0x1
+#define PSX81_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START_MASK 0x4
+#define PSX81_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START__SHIFT 0x2
+#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI_MASK 0x7
+#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI__SHIFT 0x0
+#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI_MASK 0x70
+#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI__SHIFT 0x4
+#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI_MASK 0x80
+#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI__SHIFT 0x7
+#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI_MASK 0x100
+#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI__SHIFT 0x8
+#define PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal_MASK 0xff
+#define PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal__SHIFT 0x0
+#define PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn_MASK 0x10000
+#define PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn__SHIFT 0x10
+#define PSX81_WRP_IMPCTL_CNTL_PIF0__ArbEn0_MASK 0x1
+#define PSX81_WRP_IMPCTL_CNTL_PIF0__ArbEn0__SHIFT 0x0
+#define PSX81_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0_MASK 0x800
+#define PSX81_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0__SHIFT 0xb
+#define PSX81_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0_MASK 0x1
+#define PSX81_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0__SHIFT 0x0
+#define PSX81_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt_MASK 0x1
+#define PSX81_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt__SHIFT 0x0
+#define PSX81_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr_MASK 0x1
+#define PSX81_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr__SHIFT 0x0
+#define PSX81_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0_MASK 0x1
+#define PSX81_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0__SHIFT 0x0
+#define PSX81_WRP_BIOSTIMER_CMD__Microseconds_MASK 0xffffffff
+#define PSX81_WRP_BIOSTIMER_CMD__Microseconds__SHIFT 0x0
+#define PSX81_WRP_BIOSTIMER_CNTL__ClockRate_MASK 0xff
+#define PSX81_WRP_BIOSTIMER_CNTL__ClockRate__SHIFT 0x0
+#define PSX81_WRP_BIOSTIMER_DEBUG__Microseconds_compare_MASK 0xffffffff
+#define PSX81_WRP_BIOSTIMER_DEBUG__Microseconds_compare__SHIFT 0x0
+#define PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl_MASK 0xff
+#define PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl__SHIFT 0x0
+#define PSX81_WRP_DTM_RX_BP_CNTL__Dbg_Cntl_MASK 0xf0000
+#define PSX81_WRP_DTM_RX_BP_CNTL__Dbg_Cntl__SHIFT 0x10
+#define PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue_MASK 0xf00000
+#define PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue__SHIFT 0x14
+#define PSX81_WRP_DTM_RX_BP_CNTL__td_hold_training_override_MASK 0x1f000000
+#define PSX81_WRP_DTM_RX_BP_CNTL__td_hold_training_override__SHIFT 0x18
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy0_MASK 0x1
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy0__SHIFT 0x0
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy1_MASK 0x2
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy1__SHIFT 0x1
+#define PSX81_WRP_DTM_CNTL__Determinism_En_DTM_MASK 0x4
+#define PSX81_WRP_DTM_CNTL__Determinism_En_DTM__SHIFT 0x2
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy2_MASK 0x8
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy2__SHIFT 0x3
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy3_MASK 0x10
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy3__SHIFT 0x4
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy4_MASK 0x20
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy4__SHIFT 0x5
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy5_MASK 0x40
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy5__SHIFT 0x6
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy6_MASK 0x80
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy6__SHIFT 0x7
+#define PSX81_WRP_DTM_CNTL__TxClk1x_Cntl_MASK 0x300
+#define PSX81_WRP_DTM_CNTL__TxClk1x_Cntl__SHIFT 0x8
+#define PSX81_WRP_DTM_CNTL__TxClkGskt_Cntl_MASK 0xc00
+#define PSX81_WRP_DTM_CNTL__TxClkGskt_Cntl__SHIFT 0xa
+#define PSX81_WRP_DTM_CNTL__refClk_Cntl_MASK 0x3000
+#define PSX81_WRP_DTM_CNTL__refClk_Cntl__SHIFT 0xc
+#define PSX81_WRP_DTM_CNTL__dtmClk_Sel_Timer_MASK 0xc000
+#define PSX81_WRP_DTM_CNTL__dtmClk_Sel_Timer__SHIFT 0xe
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy7_MASK 0x10000
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy7__SHIFT 0x10
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy8_MASK 0x20000
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy8__SHIFT 0x11
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy9_MASK 0x40000
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy9__SHIFT 0x12
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy10_MASK 0x80000
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy10__SHIFT 0x13
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy11_MASK 0x100000
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy11__SHIFT 0x14
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy12_MASK 0x200000
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy12__SHIFT 0x15
+#define PSX81_WRP_DTM_CNTL__rxElasWidth_Cntl_MASK 0xc00000
+#define PSX81_WRP_DTM_CNTL__rxElasWidth_Cntl__SHIFT 0x16
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy13_MASK 0x1000000
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy13__SHIFT 0x18
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy14_MASK 0x2000000
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy14__SHIFT 0x19
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy15_MASK 0x4000000
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy15__SHIFT 0x1a
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy16_MASK 0x8000000
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy16__SHIFT 0x1b
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy17_MASK 0x10000000
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy17__SHIFT 0x1c
+#define PSX81_WRP_DTM_CNTL__Warm_RstTimer_MASK 0x60000000
+#define PSX81_WRP_DTM_CNTL__Warm_RstTimer__SHIFT 0x1d
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy18_MASK 0x80000000
+#define PSX81_WRP_DTM_CNTL__Dtm_Dummy18__SHIFT 0x1f
+#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19_MASK 0x1
+#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19__SHIFT 0x0
+#define PSX81_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout_MASK 0x2
+#define PSX81_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout__SHIFT 0x1
+#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym_MASK 0x4
+#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym__SHIFT 0x2
+#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym_MASK 0x8
+#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym__SHIFT 0x3
+#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide_MASK 0x30
+#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide__SHIFT 0x4
+#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide_MASK 0xc0
+#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide__SHIFT 0x6
+#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide_MASK 0x300
+#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide__SHIFT 0x8
+#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period_MASK 0xf000
+#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period__SHIFT 0xc
+#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send_MASK 0xf0000
+#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send__SHIFT 0x10
+#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv_MASK 0xf00000
+#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv__SHIFT 0x14
+#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period_MASK 0x1ff
+#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period__SHIFT 0x0
+#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send_MASK 0x3fe00
+#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send__SHIFT 0x9
+#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv_MASK 0x7fc0000
+#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv__SHIFT 0x12
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x_MASK 0xff
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x__SHIFT 0x0
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x_MASK 0xff00
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x__SHIFT 0x8
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x_MASK 0xff0000
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x__SHIFT 0x10
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt_MASK 0xff
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt__SHIFT 0x0
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt_MASK 0xff00
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt__SHIFT 0x8
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt_MASK 0xff0000
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt__SHIFT 0x10
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x_MASK 0xff
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x__SHIFT 0x0
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x_MASK 0xff00
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x__SHIFT 0x8
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x_MASK 0xff0000
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x__SHIFT 0x10
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt_MASK 0xff
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt__SHIFT 0x0
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt_MASK 0xff00
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt__SHIFT 0x8
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt_MASK 0xff0000
+#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt__SHIFT 0x10
+#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz_MASK 0x1
+#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz__SHIFT 0x0
+#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock_MASK 0x2
+#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock__SHIFT 0x1
+#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase_MASK 0x4
+#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase__SHIFT 0x2
+#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay_MASK 0x8
+#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay__SHIFT 0x3
+#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride_MASK 0xff00
+#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride__SHIFT 0x8
+#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle_MASK 0x10000
+#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle__SHIFT 0x10
+#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart_MASK 0x20000
+#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart__SHIFT 0x11
+#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart_MASK 0x40000
+#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart__SHIFT 0x12
+#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable_MASK 0x100000
+#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable__SHIFT 0x14
+#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable_MASK 0x200000
+#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable__SHIFT 0x15
+#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_spare_MASK 0xf0000000
+#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_spare__SHIFT 0x1c
+#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle_MASK 0x1
+#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle__SHIFT 0x0
+#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete_MASK 0x2
+#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete__SHIFT 0x1
+#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked_MASK 0x4
+#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked__SHIFT 0x2
+#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld_MASK 0x8
+#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld__SHIFT 0x3
+#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld_MASK 0x10
+#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld__SHIFT 0x4
+#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue_MASK 0xff00
+#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue__SHIFT 0x8
+#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue_MASK 0xff0000
+#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue__SHIFT 0x10
+#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio_MASK 0x1f000000
+#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio__SHIFT 0x18
+#define RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn_MASK 0x1
+#define RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn__SHIFT 0x0
+#define RFE_WARMRST_CNTL__REG_RST_warmRstImpEn_MASK 0x2
+#define RFE_WARMRST_CNTL__REG_RST_warmRstImpEn__SHIFT 0x1
+#define RFE_SOFTRST_CNTL__REG_RST_rstTimer_MASK 0xffff
+#define RFE_SOFTRST_CNTL__REG_RST_rstTimer__SHIFT 0x0
+#define RFE_SOFTRST_CNTL__REG_RST_softRstPropEn_MASK 0x40000000
+#define RFE_SOFTRST_CNTL__REG_RST_softRstPropEn__SHIFT 0x1e
+#define RFE_SOFTRST_CNTL__SoftRstReg_MASK 0x80000000
+#define RFE_SOFTRST_CNTL__SoftRstReg__SHIFT 0x1f
+#define RFE_IMPRST_CNTL__REG_RST_impEn_MASK 0x1
+#define RFE_IMPRST_CNTL__REG_RST_impEn__SHIFT 0x0
+#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWRC_rst_MASK 0x1
+#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWRC_rst__SHIFT 0x0
+#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWRC_rst_MASK 0x2
+#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWRC_rst__SHIFT 0x1
+#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWRC_rst_MASK 0x4
+#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWRC_rst__SHIFT 0x2
+#define RFE_MASTER_SOFTRST_TRIGGER__PCIEW0_rst_MASK 0x1
+#define RFE_MASTER_SOFTRST_TRIGGER__PCIEW0_rst__SHIFT 0x0
+#define RFE_MASTER_SOFTRST_TRIGGER__PCIEW1_rst_MASK 0x2
+#define RFE_MASTER_SOFTRST_TRIGGER__PCIEW1_rst__SHIFT 0x1
+#define RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWRC_rst_MASK 0x4
+#define RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWRC_rst__SHIFT 0x2
+#define RFE_PWDN_COMMAND__REG_PCIEW0_pw_cmd_MASK 0x1
+#define RFE_PWDN_COMMAND__REG_PCIEW0_pw_cmd__SHIFT 0x0
+#define RFE_PWDN_COMMAND__REG_PCIEW1_pw_cmd_MASK 0x2
+#define RFE_PWDN_COMMAND__REG_PCIEW1_pw_cmd__SHIFT 0x1
+#define RFE_PWDN_COMMAND__REG_RWREG_RFEWRC_pw_cmd_MASK 0x4
+#define RFE_PWDN_COMMAND__REG_RWREG_RFEWRC_pw_cmd__SHIFT 0x2
+#define RFE_PWDN_STATUS__PCIEW0_REG_pw_status_MASK 0x1
+#define RFE_PWDN_STATUS__PCIEW0_REG_pw_status__SHIFT 0x0
+#define RFE_PWDN_STATUS__PCIEW1_REG_pw_status_MASK 0x2
+#define RFE_PWDN_STATUS__PCIEW1_REG_pw_status__SHIFT 0x1
+#define RFE_PWDN_STATUS__RWREG_RFEWRC_REG_pw_status_MASK 0x4
+#define RFE_PWDN_STATUS__RWREG_RFEWRC_REG_pw_status__SHIFT 0x2
+#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkGate_timer_MASK 0xff
+#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkGate_timer__SHIFT 0x0
+#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkSetup_timer_MASK 0xf00
+#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkSetup_timer__SHIFT 0x8
+#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_timeout_timer_MASK 0xff0000
+#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_timeout_timer__SHIFT 0x10
+#define RFE_MST_PCIEW0_CMDSTATUS__PCIEW0_RFE_mstTimeout_MASK 0x1000000
+#define RFE_MST_PCIEW0_CMDSTATUS__PCIEW0_RFE_mstTimeout__SHIFT 0x18
+#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkGate_timer_MASK 0xff
+#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkGate_timer__SHIFT 0x0
+#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkSetup_timer_MASK 0xf00
+#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkSetup_timer__SHIFT 0x8
+#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_timeout_timer_MASK 0xff0000
+#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_timeout_timer__SHIFT 0x10
+#define RFE_MST_PCIEW1_CMDSTATUS__PCIEW1_RFE_mstTimeout_MASK 0x1000000
+#define RFE_MST_PCIEW1_CMDSTATUS__PCIEW1_RFE_mstTimeout__SHIFT 0x18
+#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkGate_timer_MASK 0xff
+#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkGate_timer__SHIFT 0x0
+#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkSetup_timer_MASK 0xf00
+#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkSetup_timer__SHIFT 0x8
+#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_timeout_timer_MASK 0xff0000
+#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_timeout_timer__SHIFT 0x10
+#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__RWREG_RFEWRC_RFE_mstTimeout_MASK 0x1000000
+#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__RWREG_RFEWRC_RFE_mstTimeout__SHIFT 0x18
+#define RFE_MST_TMOUT_STATUS__MstTmoutStatus_MASK 0x1
+#define RFE_MST_TMOUT_STATUS__MstTmoutStatus__SHIFT 0x0
+#define RFE_IMPARBH_STATUS__IMPAH_REG_calDone_MASK 0x1
+#define RFE_IMPARBH_STATUS__IMPAH_REG_calDone__SHIFT 0x0
+#define RFE_IMPARBH_CONTROL__REG_IMPA_throttleTimer_MASK 0x3ff
+#define RFE_IMPARBH_CONTROL__REG_IMPA_throttleTimer__SHIFT 0x0
+#define PSX80_BIF_PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff
+#define PSX80_BIF_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define PSX80_BIF_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff
+#define PSX80_BIF_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define PSX80_BIF_PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define PSX80_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff
+#define PSX80_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0
+#define PSX80_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff
+#define PSX80_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0
+#define PSX80_BIF_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1
+#define PSX80_BIF_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define PSX80_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe
+#define PSX80_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1
+#define PSX80_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80
+#define PSX80_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define PSX80_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100
+#define PSX80_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define PSX80_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200
+#define PSX80_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9
+#define PSX80_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00
+#define PSX80_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa
+#define PSX80_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000
+#define PSX80_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf
+#define PSX80_BIF_PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000
+#define PSX80_BIF_PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10
+#define PSX80_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000
+#define PSX80_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11
+#define PSX80_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000
+#define PSX80_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12
+#define PSX80_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000
+#define PSX80_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13
+#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x100000
+#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14
+#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000
+#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15
+#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000
+#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16
+#define PSX80_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000
+#define PSX80_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17
+#define PSX80_BIF_PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000
+#define PSX80_BIF_PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18
+#define PSX80_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000
+#define PSX80_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define PSX80_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000
+#define PSX80_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f
+#define PSX80_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf
+#define PSX80_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0
+#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000
+#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000
+#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11
+#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000
+#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14
+#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000
+#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15
+#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000
+#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18
+#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000
+#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff
+#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0
+#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100
+#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8
+#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000
+#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10
+#define PSX80_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1
+#define PSX80_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0
+#define PSX80_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e
+#define PSX80_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1
+#define PSX80_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0
+#define PSX80_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6
+#define PSX80_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800
+#define PSX80_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb
+#define PSX80_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK 0x1000
+#define PSX80_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT 0xc
+#define PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK 0x2000
+#define PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT 0xd
+#define PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK 0x4000
+#define PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT 0xe
+#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000
+#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10
+#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000
+#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11
+#define PSX80_BIF_PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000
+#define PSX80_BIF_PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12
+#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000
+#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13
+#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000
+#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14
+#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000
+#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15
+#define PSX80_BIF_PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000
+#define PSX80_BIF_PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16
+#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000
+#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17
+#define PSX80_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000
+#define PSX80_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18
+#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000
+#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d
+#define PSX80_BIF_PCIE_CNTL2__MST_MEM_DS_EN_MASK 0x40000000
+#define PSX80_BIF_PCIE_CNTL2__MST_MEM_DS_EN__SHIFT 0x1e
+#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK 0x80000000
+#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT 0x1f
+#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1
+#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2
+#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1
+#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4
+#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2
+#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8
+#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3
+#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10
+#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4
+#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20
+#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5
+#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100
+#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8
+#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00
+#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9
+#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x1000
+#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc
+#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x2000
+#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd
+#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x4000
+#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe
+#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000
+#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10
+#define PSX80_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000
+#define PSX80_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3
+#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0
+#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc
+#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2
+#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30
+#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4
+#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0
+#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6
+#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300
+#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8
+#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00
+#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa
+#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000
+#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc
+#define PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4
+#define PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2
+#define PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8
+#define PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3
+#define PSX80_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10
+#define PSX80_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4
+#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0
+#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6
+#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100
+#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8
+#define PSX80_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200
+#define PSX80_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9
+#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400
+#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa
+#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800
+#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb
+#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000
+#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc
+#define PSX80_BIF_PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40
+#define PSX80_BIF_PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6
+#define PSX80_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80
+#define PSX80_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define PSX80_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000
+#define PSX80_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc
+#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f
+#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0
+#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00
+#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8
+#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000
+#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10
+#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000
+#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18
+#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f
+#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0
+#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00
+#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8
+#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000
+#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10
+#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000
+#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18
+#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f
+#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0
+#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00
+#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8
+#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000
+#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10
+#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000
+#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18
+#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f
+#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0
+#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00
+#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8
+#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000
+#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10
+#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000
+#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18
+#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f
+#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0
+#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00
+#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8
+#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000
+#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10
+#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000
+#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18
+#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f
+#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0
+#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00
+#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8
+#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000
+#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10
+#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000
+#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18
+#define PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1
+#define PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0
+#define PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2
+#define PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1
+#define PSX80_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c
+#define PSX80_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2
+#define PSX80_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0
+#define PSX80_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5
+#define PSX80_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff
+#define PSX80_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0
+#define PSX80_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000
+#define PSX80_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10
+#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1
+#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0
+#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2
+#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1
+#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4
+#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2
+#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8
+#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3
+#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10
+#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4
+#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20
+#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5
+#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40
+#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6
+#define PSX80_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff
+#define PSX80_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0
+#define PSX80_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff
+#define PSX80_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0
+#define PSX80_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff
+#define PSX80_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0
+#define PSX80_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff
+#define PSX80_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0
+#define PSX80_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff
+#define PSX80_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0
+#define PSX80_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff
+#define PSX80_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0
+#define PSX80_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff
+#define PSX80_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0
+#define PSX80_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff
+#define PSX80_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0
+#define PSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff
+#define PSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0
+#define PSX80_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff
+#define PSX80_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0
+#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1
+#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2
+#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4
+#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define PSX80_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN_MASK 0x1
+#define PSX80_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN__SHIFT 0x0
+#define PSX80_BIF_PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1
+#define PSX80_BIF_PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0
+#define PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2
+#define PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1
+#define PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4
+#define PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2
+#define PSX80_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8
+#define PSX80_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3
+#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10
+#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4
+#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20
+#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5
+#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40
+#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6
+#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80
+#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7
+#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100
+#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8
+#define PSX80_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000
+#define PSX80_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc
+#define PSX80_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000
+#define PSX80_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd
+#define PSX80_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000
+#define PSX80_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe
+#define PSX80_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000
+#define PSX80_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10
+#define PSX80_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff
+#define PSX80_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0
+#define PSX80_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000
+#define PSX80_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10
+#define PSX80_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff
+#define PSX80_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0
+#define PSX80_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff
+#define PSX80_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0
+#define PSX80_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000
+#define PSX80_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10
+#define PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff
+#define PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0
+#define PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00
+#define PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8
+#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1
+#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0
+#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2
+#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1
+#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4
+#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2
+#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff
+#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0
+#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00
+#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8
+#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000
+#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10
+#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000
+#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18
+#define PSX80_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0
+#define PSX80_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0
+#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff
+#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0
+#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00
+#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8
+#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0
+#define PSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0
+#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff
+#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0
+#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00
+#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8
+#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0
+#define PSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0
+#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0
+#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0
+#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000
+#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18
+#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff
+#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0
+#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00
+#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8
+#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000
+#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10
+#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000
+#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18
+#define PSX80_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0
+#define PSX80_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK 0x40000
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT 0x12
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK 0x80000
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT 0x13
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x100000
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x14
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0xe00000
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK 0x7000000
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT 0x18
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x10000000
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1c
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN_MASK 0x20000000
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN__SHIFT 0x1d
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK 0x40000000
+#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT 0x1e
+#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10
+#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4
+#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000
+#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
+#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000
+#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19
+#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000
+#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a
+#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000
+#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c
+#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000
+#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000
+#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e
+#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000
+#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f
+#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN_MASK 0x1
+#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN__SHIFT 0x0
+#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2
+#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1
+#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4
+#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
+#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8
+#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3
+#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10
+#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
+#define PSX80_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1
+#define PSX80_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0
+#define PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000
+#define PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c
+#define PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000
+#define PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d
+#define PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f
+#define PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0
+#define PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80
+#define PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7
+#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff
+#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0
+#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000
+#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10
+#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x1000000
+#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18
+#define PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff
+#define PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0
+#define PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000
+#define PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10
+#define PSX80_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff
+#define PSX80_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0
+#define PSX80_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff
+#define PSX80_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0
+#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_EN_MASK 0x1
+#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0
+#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0xe
+#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1
+#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x10
+#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4
+#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x20
+#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5
+#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0xc0
+#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6
+#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x1f00
+#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8
+#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000
+#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe
+#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000
+#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10
+#define PSX80_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff
+#define PSX80_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0
+#define PSX80_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0
+#define PSX80_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff
+#define PSX80_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff
+#define PSX80_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0
+#define PSX80_BIF_SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x1
+#define PSX80_BIF_SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0
+#define PSX80_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x2
+#define PSX80_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1
+#define PSX80_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x10000
+#define PSX80_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10
+#define PSX80_BIF_SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x20000
+#define PSX80_BIF_SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11
+#define PSX80_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x1
+#define PSX80_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0
+#define PSX80_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x2
+#define PSX80_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1
+#define PSX80_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x1c
+#define PSX80_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2
+#define PSX80_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x100
+#define PSX80_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8
+#define PSX80_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x200
+#define PSX80_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9
+#define PSX80_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x400
+#define PSX80_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa
+#define PSX80_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x1000
+#define PSX80_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc
+#define PSX80_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE_MASK 0x2000
+#define PSX80_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE__SHIFT 0xd
+#define PSX80_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE_MASK 0x4000
+#define PSX80_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE__SHIFT 0xe
+#define PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD_MASK 0x10000
+#define PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD__SHIFT 0x10
+#define PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD_MASK 0x20000
+#define PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD__SHIFT 0x11
+#define PSX80_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET_MASK 0x8000
+#define PSX80_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET__SHIFT 0xf
+#define PSX80_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x10000
+#define PSX80_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x10
+#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x20000
+#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x11
+#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x40000
+#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x12
+#define PSX80_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x80000
+#define PSX80_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x13
+#define PSX80_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x100000
+#define PSX80_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x14
+#define PSX80_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x200000
+#define PSX80_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x15
+#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x400000
+#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x16
+#define PSX80_BIF_SWRST_COMMAND_1__SWITCHCLK_MASK 0x1
+#define PSX80_BIF_SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x0
+#define PSX80_BIF_SWRST_COMMAND_1__RESETPCFG_MASK 0x2
+#define PSX80_BIF_SWRST_COMMAND_1__RESETPCFG__SHIFT 0x1
+#define PSX80_BIF_SWRST_COMMAND_1__RESETLANEMUX_MASK 0x4
+#define PSX80_BIF_SWRST_COMMAND_1__RESETLANEMUX__SHIFT 0x2
+#define PSX80_BIF_SWRST_COMMAND_1__RESETWRAPREGS_MASK 0x8
+#define PSX80_BIF_SWRST_COMMAND_1__RESETWRAPREGS__SHIFT 0x3
+#define PSX80_BIF_SWRST_COMMAND_1__RESETSRBM0_MASK 0x10
+#define PSX80_BIF_SWRST_COMMAND_1__RESETSRBM0__SHIFT 0x4
+#define PSX80_BIF_SWRST_COMMAND_1__RESETSRBM1_MASK 0x20
+#define PSX80_BIF_SWRST_COMMAND_1__RESETSRBM1__SHIFT 0x5
+#define PSX80_BIF_SWRST_COMMAND_1__RESETLC_MASK 0x40
+#define PSX80_BIF_SWRST_COMMAND_1__RESETLC__SHIFT 0x6
+#define PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0_MASK 0x100
+#define PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0__SHIFT 0x8
+#define PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1_MASK 0x200
+#define PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1__SHIFT 0x9
+#define PSX80_BIF_SWRST_COMMAND_1__RESETMNTR_MASK 0x2000
+#define PSX80_BIF_SWRST_COMMAND_1__RESETMNTR__SHIFT 0xd
+#define PSX80_BIF_SWRST_COMMAND_1__RESETHLTR_MASK 0x4000
+#define PSX80_BIF_SWRST_COMMAND_1__RESETHLTR__SHIFT 0xe
+#define PSX80_BIF_SWRST_COMMAND_1__RESETCPM_MASK 0x8000
+#define PSX80_BIF_SWRST_COMMAND_1__RESETCPM__SHIFT 0xf
+#define PSX80_BIF_SWRST_COMMAND_1__RESETPIF0_MASK 0x10000
+#define PSX80_BIF_SWRST_COMMAND_1__RESETPIF0__SHIFT 0x10
+#define PSX80_BIF_SWRST_COMMAND_1__RESETPIF1_MASK 0x20000
+#define PSX80_BIF_SWRST_COMMAND_1__RESETPIF1__SHIFT 0x11
+#define PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB0_MASK 0x100000
+#define PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB0__SHIFT 0x14
+#define PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB1_MASK 0x200000
+#define PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB1__SHIFT 0x15
+#define PSX80_BIF_SWRST_COMMAND_1__RESETPHY0_MASK 0x1000000
+#define PSX80_BIF_SWRST_COMMAND_1__RESETPHY0__SHIFT 0x18
+#define PSX80_BIF_SWRST_COMMAND_1__RESETPHY1_MASK 0x2000000
+#define PSX80_BIF_SWRST_COMMAND_1__RESETPHY1__SHIFT 0x19
+#define PSX80_BIF_SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x10000000
+#define PSX80_BIF_SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1c
+#define PSX80_BIF_SWRST_COMMAND_1__CMDCFGEN_MASK 0x20000000
+#define PSX80_BIF_SWRST_COMMAND_1__CMDCFGEN__SHIFT 0x1d
+#define PSX80_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN_MASK 0x8000
+#define PSX80_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN__SHIFT 0xf
+#define PSX80_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x10000
+#define PSX80_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x10
+#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x20000
+#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x11
+#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x40000
+#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x12
+#define PSX80_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x80000
+#define PSX80_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x13
+#define PSX80_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x100000
+#define PSX80_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x14
+#define PSX80_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x200000
+#define PSX80_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x15
+#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x400000
+#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x16
+#define PSX80_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x1
+#define PSX80_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x0
+#define PSX80_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x2
+#define PSX80_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x1
+#define PSX80_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN_MASK 0x4
+#define PSX80_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN__SHIFT 0x2
+#define PSX80_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN_MASK 0x8
+#define PSX80_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN__SHIFT 0x3
+#define PSX80_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN_MASK 0x10
+#define PSX80_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN__SHIFT 0x4
+#define PSX80_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN_MASK 0x20
+#define PSX80_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN__SHIFT 0x5
+#define PSX80_BIF_SWRST_CONTROL_1__RESETLC_RCEN_MASK 0x40
+#define PSX80_BIF_SWRST_CONTROL_1__RESETLC_RCEN__SHIFT 0x6
+#define PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN_MASK 0x100
+#define PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN__SHIFT 0x8
+#define PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN_MASK 0x200
+#define PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN__SHIFT 0x9
+#define PSX80_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x2000
+#define PSX80_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0xd
+#define PSX80_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x4000
+#define PSX80_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0xe
+#define PSX80_BIF_SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x8000
+#define PSX80_BIF_SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0xf
+#define PSX80_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN_MASK 0x10000
+#define PSX80_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN__SHIFT 0x10
+#define PSX80_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN_MASK 0x20000
+#define PSX80_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN__SHIFT 0x11
+#define PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN_MASK 0x100000
+#define PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN__SHIFT 0x14
+#define PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN_MASK 0x200000
+#define PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN__SHIFT 0x15
+#define PSX80_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x1000000
+#define PSX80_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x18
+#define PSX80_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN_MASK 0x2000000
+#define PSX80_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN__SHIFT 0x19
+#define PSX80_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x10000000
+#define PSX80_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1c
+#define PSX80_BIF_SWRST_CONTROL_1__CMDCFG_RCEN_MASK 0x20000000
+#define PSX80_BIF_SWRST_CONTROL_1__CMDCFG_RCEN__SHIFT 0x1d
+#define PSX80_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN_MASK 0x8000
+#define PSX80_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN__SHIFT 0xf
+#define PSX80_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x10000
+#define PSX80_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x10
+#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x20000
+#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x11
+#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x40000
+#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x12
+#define PSX80_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x80000
+#define PSX80_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x13
+#define PSX80_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x100000
+#define PSX80_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x14
+#define PSX80_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x200000
+#define PSX80_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x15
+#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x400000
+#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x16
+#define PSX80_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x1
+#define PSX80_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x0
+#define PSX80_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x2
+#define PSX80_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x1
+#define PSX80_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN_MASK 0x4
+#define PSX80_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN__SHIFT 0x2
+#define PSX80_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN_MASK 0x8
+#define PSX80_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN__SHIFT 0x3
+#define PSX80_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN_MASK 0x10
+#define PSX80_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN__SHIFT 0x4
+#define PSX80_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN_MASK 0x20
+#define PSX80_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN__SHIFT 0x5
+#define PSX80_BIF_SWRST_CONTROL_3__RESETLC_ATEN_MASK 0x40
+#define PSX80_BIF_SWRST_CONTROL_3__RESETLC_ATEN__SHIFT 0x6
+#define PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN_MASK 0x100
+#define PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN__SHIFT 0x8
+#define PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN_MASK 0x200
+#define PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN__SHIFT 0x9
+#define PSX80_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x2000
+#define PSX80_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0xd
+#define PSX80_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x4000
+#define PSX80_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0xe
+#define PSX80_BIF_SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x8000
+#define PSX80_BIF_SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0xf
+#define PSX80_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN_MASK 0x10000
+#define PSX80_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN__SHIFT 0x10
+#define PSX80_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN_MASK 0x20000
+#define PSX80_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN__SHIFT 0x11
+#define PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN_MASK 0x100000
+#define PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN__SHIFT 0x14
+#define PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN_MASK 0x200000
+#define PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN__SHIFT 0x15
+#define PSX80_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x1000000
+#define PSX80_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x18
+#define PSX80_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN_MASK 0x2000000
+#define PSX80_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN__SHIFT 0x19
+#define PSX80_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x10000000
+#define PSX80_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1c
+#define PSX80_BIF_SWRST_CONTROL_3__CMDCFG_ATEN_MASK 0x20000000
+#define PSX80_BIF_SWRST_CONTROL_3__CMDCFG_ATEN__SHIFT 0x1d
+#define PSX80_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN_MASK 0x4000
+#define PSX80_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN__SHIFT 0xe
+#define PSX80_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x10000
+#define PSX80_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x10
+#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x20000
+#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x11
+#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x40000
+#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x12
+#define PSX80_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x80000
+#define PSX80_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x13
+#define PSX80_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x100000
+#define PSX80_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x14
+#define PSX80_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x200000
+#define PSX80_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x15
+#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x400000
+#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x16
+#define PSX80_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x1
+#define PSX80_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x0
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x2
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x1
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN_MASK 0x4
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN__SHIFT 0x2
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN_MASK 0x8
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN__SHIFT 0x3
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN_MASK 0x10
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN__SHIFT 0x4
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN_MASK 0x20
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN__SHIFT 0x5
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETLC_EN_MASK 0x40
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETLC_EN__SHIFT 0x6
+#define PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN_MASK 0x100
+#define PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN__SHIFT 0x8
+#define PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN_MASK 0x200
+#define PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN__SHIFT 0x9
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x2000
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0xd
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x4000
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0xe
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x8000
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0xf
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN_MASK 0x10000
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN__SHIFT 0x10
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN_MASK 0x20000
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN__SHIFT 0x11
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN_MASK 0x100000
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN__SHIFT 0x14
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN_MASK 0x200000
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN__SHIFT 0x15
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x1000000
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x18
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN_MASK 0x2000000
+#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN__SHIFT 0x19
+#define PSX80_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x10000000
+#define PSX80_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1c
+#define PSX80_BIF_SWRST_CONTROL_5__WRCMDCFG_EN_MASK 0x20000000
+#define PSX80_BIF_SWRST_CONTROL_5__WRCMDCFG_EN__SHIFT 0x1d
+#define PSX80_BIF_SWRST_CONTROL_6__WARMRESET_EN_MASK 0x1
+#define PSX80_BIF_SWRST_CONTROL_6__WARMRESET_EN__SHIFT 0x0
+#define PSX80_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN_MASK 0x100
+#define PSX80_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN__SHIFT 0x8
+#define PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x1
+#define PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0
+#define PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x2
+#define PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1
+#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK 0x4
+#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT 0x2
+#define PSX80_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE_MASK 0x8
+#define PSX80_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE__SHIFT 0x3
+#define PSX80_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE_MASK 0x10
+#define PSX80_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE__SHIFT 0x4
+#define PSX80_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x20
+#define PSX80_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5
+#define PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x40
+#define PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6
+#define PSX80_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x80
+#define PSX80_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7
+#define PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x100
+#define PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8
+#define PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x200
+#define PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9
+#define PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x400
+#define PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xa
+#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK 0x800
+#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT 0xb
+#define PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x1000
+#define PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xc
+#define PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x2000
+#define PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xd
+#define PSX80_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x4000
+#define PSX80_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0xe
+#define PSX80_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x8000
+#define PSX80_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0xf
+#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN_MASK 0x10000
+#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN__SHIFT 0x10
+#define PSX80_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0xe0000
+#define PSX80_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x11
+#define PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT_MASK 0x100000
+#define PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT__SHIFT 0x14
+#define PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO_MASK 0x200000
+#define PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO__SHIFT 0x15
+#define PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x400000
+#define PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16
+#define PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x800000
+#define PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17
+#define PSX80_BIF_CPM_CONTROL__SPARE_REGS_MASK 0xff000000
+#define PSX80_BIF_CPM_CONTROL__SPARE_REGS__SHIFT 0x18
+#define PSX80_BIF_LM_CONTROL__LoopbackSelect_MASK 0x1e
+#define PSX80_BIF_LM_CONTROL__LoopbackSelect__SHIFT 0x1
+#define PSX80_BIF_LM_CONTROL__PRBSPCIeLbSelect_MASK 0x20
+#define PSX80_BIF_LM_CONTROL__PRBSPCIeLbSelect__SHIFT 0x5
+#define PSX80_BIF_LM_CONTROL__LoopbackHalfRate_MASK 0xc0
+#define PSX80_BIF_LM_CONTROL__LoopbackHalfRate__SHIFT 0x6
+#define PSX80_BIF_LM_CONTROL__LoopbackFifoPtr_MASK 0x700
+#define PSX80_BIF_LM_CONTROL__LoopbackFifoPtr__SHIFT 0x8
+#define PSX80_BIF_LM_PCIETXMUX0__TXLANE0_MASK 0xff
+#define PSX80_BIF_LM_PCIETXMUX0__TXLANE0__SHIFT 0x0
+#define PSX80_BIF_LM_PCIETXMUX0__TXLANE1_MASK 0xff00
+#define PSX80_BIF_LM_PCIETXMUX0__TXLANE1__SHIFT 0x8
+#define PSX80_BIF_LM_PCIETXMUX0__TXLANE2_MASK 0xff0000
+#define PSX80_BIF_LM_PCIETXMUX0__TXLANE2__SHIFT 0x10
+#define PSX80_BIF_LM_PCIETXMUX0__TXLANE3_MASK 0xff000000
+#define PSX80_BIF_LM_PCIETXMUX0__TXLANE3__SHIFT 0x18
+#define PSX80_BIF_LM_PCIETXMUX1__TXLANE4_MASK 0xff
+#define PSX80_BIF_LM_PCIETXMUX1__TXLANE4__SHIFT 0x0
+#define PSX80_BIF_LM_PCIETXMUX1__TXLANE5_MASK 0xff00
+#define PSX80_BIF_LM_PCIETXMUX1__TXLANE5__SHIFT 0x8
+#define PSX80_BIF_LM_PCIETXMUX1__TXLANE6_MASK 0xff0000
+#define PSX80_BIF_LM_PCIETXMUX1__TXLANE6__SHIFT 0x10
+#define PSX80_BIF_LM_PCIETXMUX1__TXLANE7_MASK 0xff000000
+#define PSX80_BIF_LM_PCIETXMUX1__TXLANE7__SHIFT 0x18
+#define PSX80_BIF_LM_PCIETXMUX2__TXLANE8_MASK 0xff
+#define PSX80_BIF_LM_PCIETXMUX2__TXLANE8__SHIFT 0x0
+#define PSX80_BIF_LM_PCIETXMUX2__TXLANE9_MASK 0xff00
+#define PSX80_BIF_LM_PCIETXMUX2__TXLANE9__SHIFT 0x8
+#define PSX80_BIF_LM_PCIETXMUX2__TXLANE10_MASK 0xff0000
+#define PSX80_BIF_LM_PCIETXMUX2__TXLANE10__SHIFT 0x10
+#define PSX80_BIF_LM_PCIETXMUX2__TXLANE11_MASK 0xff000000
+#define PSX80_BIF_LM_PCIETXMUX2__TXLANE11__SHIFT 0x18
+#define PSX80_BIF_LM_PCIETXMUX3__TXLANE12_MASK 0xff
+#define PSX80_BIF_LM_PCIETXMUX3__TXLANE12__SHIFT 0x0
+#define PSX80_BIF_LM_PCIETXMUX3__TXLANE13_MASK 0xff00
+#define PSX80_BIF_LM_PCIETXMUX3__TXLANE13__SHIFT 0x8
+#define PSX80_BIF_LM_PCIETXMUX3__TXLANE14_MASK 0xff0000
+#define PSX80_BIF_LM_PCIETXMUX3__TXLANE14__SHIFT 0x10
+#define PSX80_BIF_LM_PCIETXMUX3__TXLANE15_MASK 0xff000000
+#define PSX80_BIF_LM_PCIETXMUX3__TXLANE15__SHIFT 0x18
+#define PSX80_BIF_LM_PCIERXMUX0__RXLANE0_MASK 0xff
+#define PSX80_BIF_LM_PCIERXMUX0__RXLANE0__SHIFT 0x0
+#define PSX80_BIF_LM_PCIERXMUX0__RXLANE1_MASK 0xff00
+#define PSX80_BIF_LM_PCIERXMUX0__RXLANE1__SHIFT 0x8
+#define PSX80_BIF_LM_PCIERXMUX0__RXLANE2_MASK 0xff0000
+#define PSX80_BIF_LM_PCIERXMUX0__RXLANE2__SHIFT 0x10
+#define PSX80_BIF_LM_PCIERXMUX0__RXLANE3_MASK 0xff000000
+#define PSX80_BIF_LM_PCIERXMUX0__RXLANE3__SHIFT 0x18
+#define PSX80_BIF_LM_PCIERXMUX1__RXLANE4_MASK 0xff
+#define PSX80_BIF_LM_PCIERXMUX1__RXLANE4__SHIFT 0x0
+#define PSX80_BIF_LM_PCIERXMUX1__RXLANE5_MASK 0xff00
+#define PSX80_BIF_LM_PCIERXMUX1__RXLANE5__SHIFT 0x8
+#define PSX80_BIF_LM_PCIERXMUX1__RXLANE6_MASK 0xff0000
+#define PSX80_BIF_LM_PCIERXMUX1__RXLANE6__SHIFT 0x10
+#define PSX80_BIF_LM_PCIERXMUX1__RXLANE7_MASK 0xff000000
+#define PSX80_BIF_LM_PCIERXMUX1__RXLANE7__SHIFT 0x18
+#define PSX80_BIF_LM_PCIERXMUX2__RXLANE8_MASK 0xff
+#define PSX80_BIF_LM_PCIERXMUX2__RXLANE8__SHIFT 0x0
+#define PSX80_BIF_LM_PCIERXMUX2__RXLANE9_MASK 0xff00
+#define PSX80_BIF_LM_PCIERXMUX2__RXLANE9__SHIFT 0x8
+#define PSX80_BIF_LM_PCIERXMUX2__RXLANE10_MASK 0xff0000
+#define PSX80_BIF_LM_PCIERXMUX2__RXLANE10__SHIFT 0x10
+#define PSX80_BIF_LM_PCIERXMUX2__RXLANE11_MASK 0xff000000
+#define PSX80_BIF_LM_PCIERXMUX2__RXLANE11__SHIFT 0x18
+#define PSX80_BIF_LM_PCIERXMUX3__RXLANE12_MASK 0xff
+#define PSX80_BIF_LM_PCIERXMUX3__RXLANE12__SHIFT 0x0
+#define PSX80_BIF_LM_PCIERXMUX3__RXLANE13_MASK 0xff00
+#define PSX80_BIF_LM_PCIERXMUX3__RXLANE13__SHIFT 0x8
+#define PSX80_BIF_LM_PCIERXMUX3__RXLANE14_MASK 0xff0000
+#define PSX80_BIF_LM_PCIERXMUX3__RXLANE14__SHIFT 0x10
+#define PSX80_BIF_LM_PCIERXMUX3__RXLANE15_MASK 0xff000000
+#define PSX80_BIF_LM_PCIERXMUX3__RXLANE15__SHIFT 0x18
+#define PSX80_BIF_LM_LANEENABLE__LANE_enable_MASK 0xffff
+#define PSX80_BIF_LM_LANEENABLE__LANE_enable__SHIFT 0x0
+#define PSX80_BIF_LM_PRBSCONTROL__PRBSPCIeSelect_MASK 0xffff
+#define PSX80_BIF_LM_PRBSCONTROL__PRBSPCIeSelect__SHIFT 0x0
+#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade0_MASK 0x10000000
+#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade0__SHIFT 0x1c
+#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade1_MASK 0x20000000
+#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade1__SHIFT 0x1d
+#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade2_MASK 0x40000000
+#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade2__SHIFT 0x1e
+#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade3_MASK 0x80000000
+#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade3__SHIFT 0x1f
+#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd0_MASK 0x7
+#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd0__SHIFT 0x0
+#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd0_MASK 0x38
+#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd0__SHIFT 0x3
+#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed0_MASK 0xc0
+#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed0__SHIFT 0x6
+#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd1_MASK 0x700
+#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd1__SHIFT 0x8
+#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd1_MASK 0x3800
+#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd1__SHIFT 0xb
+#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed1_MASK 0xc000
+#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed1__SHIFT 0xe
+#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd2_MASK 0x70000
+#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd2__SHIFT 0x10
+#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd2_MASK 0x380000
+#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd2__SHIFT 0x13
+#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed2_MASK 0xc00000
+#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed2__SHIFT 0x16
+#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd3_MASK 0x7000000
+#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd3__SHIFT 0x18
+#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd3_MASK 0x38000000
+#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd3__SHIFT 0x1b
+#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed3_MASK 0xc0000000
+#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed3__SHIFT 0x1e
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn0_MASK 0x1
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn0__SHIFT 0x0
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn0_MASK 0x2
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn0__SHIFT 0x1
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin0_MASK 0x1c
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin0__SHIFT 0x2
+#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit0_MASK 0x20
+#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit0__SHIFT 0x5
+#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused0_MASK 0x40
+#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused0__SHIFT 0x6
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn0_MASK 0x80
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn0__SHIFT 0x7
+#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph0_MASK 0x100
+#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph0__SHIFT 0x8
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn1_MASK 0x200
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn1__SHIFT 0x9
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn1_MASK 0x400
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn1__SHIFT 0xa
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin1_MASK 0x3800
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin1__SHIFT 0xb
+#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit1_MASK 0x4000
+#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit1__SHIFT 0xe
+#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused1_MASK 0x8000
+#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused1__SHIFT 0xf
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn1_MASK 0x10000
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn1__SHIFT 0x10
+#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph1_MASK 0x20000
+#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph1__SHIFT 0x11
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn2_MASK 0x40000
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn2__SHIFT 0x12
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn2_MASK 0x80000
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn2__SHIFT 0x13
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin2_MASK 0x700000
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin2__SHIFT 0x14
+#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit2_MASK 0x800000
+#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit2__SHIFT 0x17
+#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused2_MASK 0x1000000
+#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused2__SHIFT 0x18
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn2_MASK 0x2000000
+#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn2__SHIFT 0x19
+#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph2_MASK 0x4000000
+#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph2__SHIFT 0x1a
+#define PSX80_BIF_LM_POWERCONTROL1__TxCoeffID0_MASK 0x18000000
+#define PSX80_BIF_LM_POWERCONTROL1__TxCoeffID0__SHIFT 0x1b
+#define PSX80_BIF_LM_POWERCONTROL1__TxCoeffID1_MASK 0x60000000
+#define PSX80_BIF_LM_POWERCONTROL1__TxCoeffID1__SHIFT 0x1d
+#define PSX80_BIF_LM_POWERCONTROL2__LMTxEn3_MASK 0x1
+#define PSX80_BIF_LM_POWERCONTROL2__LMTxEn3__SHIFT 0x0
+#define PSX80_BIF_LM_POWERCONTROL2__LMTxClkEn3_MASK 0x2
+#define PSX80_BIF_LM_POWERCONTROL2__LMTxClkEn3__SHIFT 0x1
+#define PSX80_BIF_LM_POWERCONTROL2__LMTxMargin3_MASK 0x1c
+#define PSX80_BIF_LM_POWERCONTROL2__LMTxMargin3__SHIFT 0x2
+#define PSX80_BIF_LM_POWERCONTROL2__LMSkipBit3_MASK 0x20
+#define PSX80_BIF_LM_POWERCONTROL2__LMSkipBit3__SHIFT 0x5
+#define PSX80_BIF_LM_POWERCONTROL2__LMLaneUnused3_MASK 0x40
+#define PSX80_BIF_LM_POWERCONTROL2__LMLaneUnused3__SHIFT 0x6
+#define PSX80_BIF_LM_POWERCONTROL2__LMTxMarginEn3_MASK 0x80
+#define PSX80_BIF_LM_POWERCONTROL2__LMTxMarginEn3__SHIFT 0x7
+#define PSX80_BIF_LM_POWERCONTROL2__LMDeemph3_MASK 0x100
+#define PSX80_BIF_LM_POWERCONTROL2__LMDeemph3__SHIFT 0x8
+#define PSX80_BIF_LM_POWERCONTROL2__TxCoeffID2_MASK 0x600
+#define PSX80_BIF_LM_POWERCONTROL2__TxCoeffID2__SHIFT 0x9
+#define PSX80_BIF_LM_POWERCONTROL2__TxCoeffID3_MASK 0x1800
+#define PSX80_BIF_LM_POWERCONTROL2__TxCoeffID3__SHIFT 0xb
+#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff0_MASK 0x7e000
+#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff0__SHIFT 0xd
+#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff1_MASK 0x1f80000
+#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff1__SHIFT 0x13
+#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff2_MASK 0x7e000000
+#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff2__SHIFT 0x19
+#define PSX80_BIF_LM_POWERCONTROL3__TxCoeff3_MASK 0x3f
+#define PSX80_BIF_LM_POWERCONTROL3__TxCoeff3__SHIFT 0x0
+#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl0_MASK 0xfc0
+#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl0__SHIFT 0x6
+#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl1_MASK 0x3f000
+#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl1__SHIFT 0xc
+#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl2_MASK 0xfc0000
+#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl2__SHIFT 0x12
+#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl3_MASK 0x3f000000
+#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl3__SHIFT 0x18
+#define PSX80_BIF_LM_POWERCONTROL4__LinkNum0_MASK 0x7
+#define PSX80_BIF_LM_POWERCONTROL4__LinkNum0__SHIFT 0x0
+#define PSX80_BIF_LM_POWERCONTROL4__LinkNum1_MASK 0x38
+#define PSX80_BIF_LM_POWERCONTROL4__LinkNum1__SHIFT 0x3
+#define PSX80_BIF_LM_POWERCONTROL4__LinkNum2_MASK 0x1c0
+#define PSX80_BIF_LM_POWERCONTROL4__LinkNum2__SHIFT 0x6
+#define PSX80_BIF_LM_POWERCONTROL4__LinkNum3_MASK 0xe00
+#define PSX80_BIF_LM_POWERCONTROL4__LinkNum3__SHIFT 0x9
+#define PSX80_BIF_LM_POWERCONTROL4__LaneNum0_MASK 0xf000
+#define PSX80_BIF_LM_POWERCONTROL4__LaneNum0__SHIFT 0xc
+#define PSX80_BIF_LM_POWERCONTROL4__LaneNum1_MASK 0xf0000
+#define PSX80_BIF_LM_POWERCONTROL4__LaneNum1__SHIFT 0x10
+#define PSX80_BIF_LM_POWERCONTROL4__LaneNum2_MASK 0xf00000
+#define PSX80_BIF_LM_POWERCONTROL4__LaneNum2__SHIFT 0x14
+#define PSX80_BIF_LM_POWERCONTROL4__LaneNum3_MASK 0xf000000
+#define PSX80_BIF_LM_POWERCONTROL4__LaneNum3__SHIFT 0x18
+#define PSX80_BIF_LM_POWERCONTROL4__SpcMode0_MASK 0x10000000
+#define PSX80_BIF_LM_POWERCONTROL4__SpcMode0__SHIFT 0x1c
+#define PSX80_BIF_LM_POWERCONTROL4__SpcMode1_MASK 0x20000000
+#define PSX80_BIF_LM_POWERCONTROL4__SpcMode1__SHIFT 0x1d
+#define PSX80_BIF_LM_POWERCONTROL4__SpcMode2_MASK 0x40000000
+#define PSX80_BIF_LM_POWERCONTROL4__SpcMode2__SHIFT 0x1e
+#define PSX80_BIF_LM_POWERCONTROL4__SpcMode3_MASK 0x80000000
+#define PSX80_BIF_LM_POWERCONTROL4__SpcMode3__SHIFT 0x1f
+#define PSX81_BIF_PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff
+#define PSX81_BIF_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define PSX81_BIF_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff
+#define PSX81_BIF_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define PSX81_BIF_PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define PSX81_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff
+#define PSX81_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0
+#define PSX81_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff
+#define PSX81_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0
+#define PSX81_BIF_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1
+#define PSX81_BIF_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define PSX81_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe
+#define PSX81_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1
+#define PSX81_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80
+#define PSX81_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define PSX81_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100
+#define PSX81_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define PSX81_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200
+#define PSX81_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9
+#define PSX81_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00
+#define PSX81_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa
+#define PSX81_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000
+#define PSX81_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf
+#define PSX81_BIF_PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000
+#define PSX81_BIF_PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10
+#define PSX81_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000
+#define PSX81_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11
+#define PSX81_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000
+#define PSX81_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12
+#define PSX81_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000
+#define PSX81_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13
+#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x100000
+#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14
+#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000
+#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15
+#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000
+#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16
+#define PSX81_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000
+#define PSX81_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17
+#define PSX81_BIF_PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000
+#define PSX81_BIF_PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18
+#define PSX81_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000
+#define PSX81_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define PSX81_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000
+#define PSX81_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f
+#define PSX81_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf
+#define PSX81_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0
+#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000
+#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000
+#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11
+#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000
+#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14
+#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000
+#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15
+#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000
+#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18
+#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000
+#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff
+#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0
+#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100
+#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8
+#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000
+#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10
+#define PSX81_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1
+#define PSX81_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0
+#define PSX81_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e
+#define PSX81_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1
+#define PSX81_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0
+#define PSX81_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6
+#define PSX81_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800
+#define PSX81_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb
+#define PSX81_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK 0x1000
+#define PSX81_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT 0xc
+#define PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK 0x2000
+#define PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT 0xd
+#define PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK 0x4000
+#define PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT 0xe
+#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000
+#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10
+#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000
+#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11
+#define PSX81_BIF_PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000
+#define PSX81_BIF_PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12
+#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000
+#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13
+#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000
+#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14
+#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000
+#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15
+#define PSX81_BIF_PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000
+#define PSX81_BIF_PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16
+#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000
+#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17
+#define PSX81_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000
+#define PSX81_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18
+#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000
+#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d
+#define PSX81_BIF_PCIE_CNTL2__MST_MEM_DS_EN_MASK 0x40000000
+#define PSX81_BIF_PCIE_CNTL2__MST_MEM_DS_EN__SHIFT 0x1e
+#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK 0x80000000
+#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT 0x1f
+#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1
+#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2
+#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1
+#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4
+#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2
+#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8
+#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3
+#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10
+#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4
+#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20
+#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5
+#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100
+#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8
+#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00
+#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9
+#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x1000
+#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc
+#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x2000
+#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd
+#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x4000
+#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe
+#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000
+#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10
+#define PSX81_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000
+#define PSX81_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3
+#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0
+#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc
+#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2
+#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30
+#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4
+#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0
+#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6
+#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300
+#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8
+#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00
+#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa
+#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000
+#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc
+#define PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4
+#define PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2
+#define PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8
+#define PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3
+#define PSX81_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10
+#define PSX81_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4
+#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0
+#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6
+#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100
+#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8
+#define PSX81_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200
+#define PSX81_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9
+#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400
+#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa
+#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800
+#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb
+#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000
+#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc
+#define PSX81_BIF_PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40
+#define PSX81_BIF_PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6
+#define PSX81_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80
+#define PSX81_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define PSX81_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000
+#define PSX81_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc
+#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f
+#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0
+#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00
+#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8
+#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000
+#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10
+#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000
+#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18
+#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f
+#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0
+#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00
+#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8
+#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000
+#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10
+#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000
+#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18
+#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f
+#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0
+#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00
+#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8
+#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000
+#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10
+#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000
+#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18
+#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f
+#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0
+#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00
+#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8
+#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000
+#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10
+#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000
+#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18
+#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f
+#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0
+#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00
+#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8
+#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000
+#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10
+#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000
+#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18
+#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f
+#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0
+#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00
+#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8
+#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000
+#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10
+#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000
+#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18
+#define PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1
+#define PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0
+#define PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2
+#define PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1
+#define PSX81_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c
+#define PSX81_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2
+#define PSX81_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0
+#define PSX81_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5
+#define PSX81_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff
+#define PSX81_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0
+#define PSX81_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000
+#define PSX81_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10
+#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1
+#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0
+#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2
+#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1
+#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4
+#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2
+#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8
+#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3
+#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10
+#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4
+#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20
+#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5
+#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40
+#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6
+#define PSX81_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff
+#define PSX81_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0
+#define PSX81_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff
+#define PSX81_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0
+#define PSX81_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff
+#define PSX81_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0
+#define PSX81_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff
+#define PSX81_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0
+#define PSX81_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff
+#define PSX81_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0
+#define PSX81_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff
+#define PSX81_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0
+#define PSX81_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff
+#define PSX81_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0
+#define PSX81_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff
+#define PSX81_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0
+#define PSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff
+#define PSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0
+#define PSX81_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff
+#define PSX81_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0
+#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1
+#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2
+#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4
+#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define PSX81_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN_MASK 0x1
+#define PSX81_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN__SHIFT 0x0
+#define PSX81_BIF_PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1
+#define PSX81_BIF_PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0
+#define PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2
+#define PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1
+#define PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4
+#define PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2
+#define PSX81_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8
+#define PSX81_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3
+#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10
+#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4
+#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20
+#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5
+#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40
+#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6
+#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80
+#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7
+#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100
+#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8
+#define PSX81_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000
+#define PSX81_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc
+#define PSX81_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000
+#define PSX81_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd
+#define PSX81_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000
+#define PSX81_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe
+#define PSX81_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000
+#define PSX81_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10
+#define PSX81_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff
+#define PSX81_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0
+#define PSX81_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000
+#define PSX81_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10
+#define PSX81_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff
+#define PSX81_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0
+#define PSX81_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff
+#define PSX81_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0
+#define PSX81_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000
+#define PSX81_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10
+#define PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff
+#define PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0
+#define PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00
+#define PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8
+#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1
+#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0
+#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2
+#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1
+#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4
+#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2
+#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff
+#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0
+#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00
+#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8
+#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000
+#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10
+#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000
+#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18
+#define PSX81_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0
+#define PSX81_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0
+#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff
+#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0
+#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00
+#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8
+#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0
+#define PSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0
+#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff
+#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0
+#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00
+#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8
+#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0
+#define PSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0
+#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0
+#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000
+#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18
+#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0
+#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000
+#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18
+#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff
+#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0
+#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00
+#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8
+#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000
+#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10
+#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000
+#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18
+#define PSX81_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0
+#define PSX81_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK 0x40000
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT 0x12
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK 0x80000
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT 0x13
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x100000
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x14
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0xe00000
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK 0x7000000
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT 0x18
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x10000000
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1c
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN_MASK 0x20000000
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN__SHIFT 0x1d
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK 0x40000000
+#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT 0x1e
+#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10
+#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4
+#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000
+#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
+#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000
+#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19
+#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000
+#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a
+#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000
+#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c
+#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000
+#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000
+#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e
+#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000
+#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f
+#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN_MASK 0x1
+#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN__SHIFT 0x0
+#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2
+#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1
+#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4
+#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
+#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8
+#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3
+#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10
+#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
+#define PSX81_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1
+#define PSX81_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0
+#define PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000
+#define PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c
+#define PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000
+#define PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d
+#define PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f
+#define PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0
+#define PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80
+#define PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7
+#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff
+#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0
+#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000
+#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10
+#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x1000000
+#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18
+#define PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff
+#define PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0
+#define PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000
+#define PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10
+#define PSX81_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff
+#define PSX81_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0
+#define PSX81_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff
+#define PSX81_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0
+#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_EN_MASK 0x1
+#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0
+#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0xe
+#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1
+#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x10
+#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4
+#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x20
+#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5
+#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0xc0
+#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6
+#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x1f00
+#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8
+#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000
+#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe
+#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000
+#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10
+#define PSX81_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff
+#define PSX81_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0
+#define PSX81_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0
+#define PSX81_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff
+#define PSX81_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff
+#define PSX81_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0
+#define PSX81_BIF_SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x1
+#define PSX81_BIF_SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0
+#define PSX81_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x2
+#define PSX81_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1
+#define PSX81_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x10000
+#define PSX81_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10
+#define PSX81_BIF_SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x20000
+#define PSX81_BIF_SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11
+#define PSX81_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x1
+#define PSX81_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0
+#define PSX81_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x2
+#define PSX81_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1
+#define PSX81_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x1c
+#define PSX81_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2
+#define PSX81_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x100
+#define PSX81_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8
+#define PSX81_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x200
+#define PSX81_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9
+#define PSX81_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x400
+#define PSX81_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa
+#define PSX81_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x1000
+#define PSX81_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc
+#define PSX81_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE_MASK 0x2000
+#define PSX81_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE__SHIFT 0xd
+#define PSX81_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE_MASK 0x4000
+#define PSX81_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE__SHIFT 0xe
+#define PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD_MASK 0x10000
+#define PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD__SHIFT 0x10
+#define PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD_MASK 0x20000
+#define PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD__SHIFT 0x11
+#define PSX81_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET_MASK 0x8000
+#define PSX81_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET__SHIFT 0xf
+#define PSX81_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x10000
+#define PSX81_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x10
+#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x20000
+#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x11
+#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x40000
+#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x12
+#define PSX81_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x80000
+#define PSX81_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x13
+#define PSX81_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x100000
+#define PSX81_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x14
+#define PSX81_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x200000
+#define PSX81_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x15
+#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x400000
+#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x16
+#define PSX81_BIF_SWRST_COMMAND_1__SWITCHCLK_MASK 0x1
+#define PSX81_BIF_SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x0
+#define PSX81_BIF_SWRST_COMMAND_1__RESETPCFG_MASK 0x2
+#define PSX81_BIF_SWRST_COMMAND_1__RESETPCFG__SHIFT 0x1
+#define PSX81_BIF_SWRST_COMMAND_1__RESETLANEMUX_MASK 0x4
+#define PSX81_BIF_SWRST_COMMAND_1__RESETLANEMUX__SHIFT 0x2
+#define PSX81_BIF_SWRST_COMMAND_1__RESETWRAPREGS_MASK 0x8
+#define PSX81_BIF_SWRST_COMMAND_1__RESETWRAPREGS__SHIFT 0x3
+#define PSX81_BIF_SWRST_COMMAND_1__RESETSRBM0_MASK 0x10
+#define PSX81_BIF_SWRST_COMMAND_1__RESETSRBM0__SHIFT 0x4
+#define PSX81_BIF_SWRST_COMMAND_1__RESETSRBM1_MASK 0x20
+#define PSX81_BIF_SWRST_COMMAND_1__RESETSRBM1__SHIFT 0x5
+#define PSX81_BIF_SWRST_COMMAND_1__RESETLC_MASK 0x40
+#define PSX81_BIF_SWRST_COMMAND_1__RESETLC__SHIFT 0x6
+#define PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0_MASK 0x100
+#define PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0__SHIFT 0x8
+#define PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1_MASK 0x200
+#define PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1__SHIFT 0x9
+#define PSX81_BIF_SWRST_COMMAND_1__RESETMNTR_MASK 0x2000
+#define PSX81_BIF_SWRST_COMMAND_1__RESETMNTR__SHIFT 0xd
+#define PSX81_BIF_SWRST_COMMAND_1__RESETHLTR_MASK 0x4000
+#define PSX81_BIF_SWRST_COMMAND_1__RESETHLTR__SHIFT 0xe
+#define PSX81_BIF_SWRST_COMMAND_1__RESETCPM_MASK 0x8000
+#define PSX81_BIF_SWRST_COMMAND_1__RESETCPM__SHIFT 0xf
+#define PSX81_BIF_SWRST_COMMAND_1__RESETPIF0_MASK 0x10000
+#define PSX81_BIF_SWRST_COMMAND_1__RESETPIF0__SHIFT 0x10
+#define PSX81_BIF_SWRST_COMMAND_1__RESETPIF1_MASK 0x20000
+#define PSX81_BIF_SWRST_COMMAND_1__RESETPIF1__SHIFT 0x11
+#define PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB0_MASK 0x100000
+#define PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB0__SHIFT 0x14
+#define PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB1_MASK 0x200000
+#define PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB1__SHIFT 0x15
+#define PSX81_BIF_SWRST_COMMAND_1__RESETPHY0_MASK 0x1000000
+#define PSX81_BIF_SWRST_COMMAND_1__RESETPHY0__SHIFT 0x18
+#define PSX81_BIF_SWRST_COMMAND_1__RESETPHY1_MASK 0x2000000
+#define PSX81_BIF_SWRST_COMMAND_1__RESETPHY1__SHIFT 0x19
+#define PSX81_BIF_SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x10000000
+#define PSX81_BIF_SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1c
+#define PSX81_BIF_SWRST_COMMAND_1__CMDCFGEN_MASK 0x20000000
+#define PSX81_BIF_SWRST_COMMAND_1__CMDCFGEN__SHIFT 0x1d
+#define PSX81_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN_MASK 0x8000
+#define PSX81_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN__SHIFT 0xf
+#define PSX81_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x10000
+#define PSX81_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x10
+#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x20000
+#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x11
+#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x40000
+#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x12
+#define PSX81_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x80000
+#define PSX81_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x13
+#define PSX81_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x100000
+#define PSX81_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x14
+#define PSX81_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x200000
+#define PSX81_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x15
+#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x400000
+#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x16
+#define PSX81_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x1
+#define PSX81_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x0
+#define PSX81_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x2
+#define PSX81_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x1
+#define PSX81_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN_MASK 0x4
+#define PSX81_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN__SHIFT 0x2
+#define PSX81_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN_MASK 0x8
+#define PSX81_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN__SHIFT 0x3
+#define PSX81_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN_MASK 0x10
+#define PSX81_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN__SHIFT 0x4
+#define PSX81_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN_MASK 0x20
+#define PSX81_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN__SHIFT 0x5
+#define PSX81_BIF_SWRST_CONTROL_1__RESETLC_RCEN_MASK 0x40
+#define PSX81_BIF_SWRST_CONTROL_1__RESETLC_RCEN__SHIFT 0x6
+#define PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN_MASK 0x100
+#define PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN__SHIFT 0x8
+#define PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN_MASK 0x200
+#define PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN__SHIFT 0x9
+#define PSX81_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x2000
+#define PSX81_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0xd
+#define PSX81_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x4000
+#define PSX81_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0xe
+#define PSX81_BIF_SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x8000
+#define PSX81_BIF_SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0xf
+#define PSX81_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN_MASK 0x10000
+#define PSX81_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN__SHIFT 0x10
+#define PSX81_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN_MASK 0x20000
+#define PSX81_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN__SHIFT 0x11
+#define PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN_MASK 0x100000
+#define PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN__SHIFT 0x14
+#define PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN_MASK 0x200000
+#define PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN__SHIFT 0x15
+#define PSX81_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x1000000
+#define PSX81_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x18
+#define PSX81_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN_MASK 0x2000000
+#define PSX81_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN__SHIFT 0x19
+#define PSX81_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x10000000
+#define PSX81_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1c
+#define PSX81_BIF_SWRST_CONTROL_1__CMDCFG_RCEN_MASK 0x20000000
+#define PSX81_BIF_SWRST_CONTROL_1__CMDCFG_RCEN__SHIFT 0x1d
+#define PSX81_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN_MASK 0x8000
+#define PSX81_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN__SHIFT 0xf
+#define PSX81_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x10000
+#define PSX81_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x10
+#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x20000
+#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x11
+#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x40000
+#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x12
+#define PSX81_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x80000
+#define PSX81_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x13
+#define PSX81_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x100000
+#define PSX81_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x14
+#define PSX81_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x200000
+#define PSX81_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x15
+#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x400000
+#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x16
+#define PSX81_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x1
+#define PSX81_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x0
+#define PSX81_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x2
+#define PSX81_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x1
+#define PSX81_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN_MASK 0x4
+#define PSX81_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN__SHIFT 0x2
+#define PSX81_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN_MASK 0x8
+#define PSX81_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN__SHIFT 0x3
+#define PSX81_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN_MASK 0x10
+#define PSX81_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN__SHIFT 0x4
+#define PSX81_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN_MASK 0x20
+#define PSX81_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN__SHIFT 0x5
+#define PSX81_BIF_SWRST_CONTROL_3__RESETLC_ATEN_MASK 0x40
+#define PSX81_BIF_SWRST_CONTROL_3__RESETLC_ATEN__SHIFT 0x6
+#define PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN_MASK 0x100
+#define PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN__SHIFT 0x8
+#define PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN_MASK 0x200
+#define PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN__SHIFT 0x9
+#define PSX81_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x2000
+#define PSX81_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0xd
+#define PSX81_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x4000
+#define PSX81_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0xe
+#define PSX81_BIF_SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x8000
+#define PSX81_BIF_SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0xf
+#define PSX81_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN_MASK 0x10000
+#define PSX81_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN__SHIFT 0x10
+#define PSX81_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN_MASK 0x20000
+#define PSX81_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN__SHIFT 0x11
+#define PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN_MASK 0x100000
+#define PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN__SHIFT 0x14
+#define PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN_MASK 0x200000
+#define PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN__SHIFT 0x15
+#define PSX81_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x1000000
+#define PSX81_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x18
+#define PSX81_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN_MASK 0x2000000
+#define PSX81_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN__SHIFT 0x19
+#define PSX81_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x10000000
+#define PSX81_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1c
+#define PSX81_BIF_SWRST_CONTROL_3__CMDCFG_ATEN_MASK 0x20000000
+#define PSX81_BIF_SWRST_CONTROL_3__CMDCFG_ATEN__SHIFT 0x1d
+#define PSX81_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN_MASK 0x4000
+#define PSX81_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN__SHIFT 0xe
+#define PSX81_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x10000
+#define PSX81_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x10
+#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x20000
+#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x11
+#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x40000
+#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x12
+#define PSX81_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x80000
+#define PSX81_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x13
+#define PSX81_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x100000
+#define PSX81_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x14
+#define PSX81_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x200000
+#define PSX81_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x15
+#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x400000
+#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x16
+#define PSX81_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x1
+#define PSX81_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x0
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x2
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x1
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN_MASK 0x4
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN__SHIFT 0x2
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN_MASK 0x8
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN__SHIFT 0x3
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN_MASK 0x10
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN__SHIFT 0x4
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN_MASK 0x20
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN__SHIFT 0x5
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETLC_EN_MASK 0x40
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETLC_EN__SHIFT 0x6
+#define PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN_MASK 0x100
+#define PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN__SHIFT 0x8
+#define PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN_MASK 0x200
+#define PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN__SHIFT 0x9
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x2000
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0xd
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x4000
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0xe
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x8000
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0xf
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN_MASK 0x10000
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN__SHIFT 0x10
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN_MASK 0x20000
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN__SHIFT 0x11
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN_MASK 0x100000
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN__SHIFT 0x14
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN_MASK 0x200000
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN__SHIFT 0x15
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x1000000
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x18
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN_MASK 0x2000000
+#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN__SHIFT 0x19
+#define PSX81_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x10000000
+#define PSX81_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1c
+#define PSX81_BIF_SWRST_CONTROL_5__WRCMDCFG_EN_MASK 0x20000000
+#define PSX81_BIF_SWRST_CONTROL_5__WRCMDCFG_EN__SHIFT 0x1d
+#define PSX81_BIF_SWRST_CONTROL_6__WARMRESET_EN_MASK 0x1
+#define PSX81_BIF_SWRST_CONTROL_6__WARMRESET_EN__SHIFT 0x0
+#define PSX81_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN_MASK 0x100
+#define PSX81_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN__SHIFT 0x8
+#define PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x1
+#define PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0
+#define PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x2
+#define PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1
+#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK 0x4
+#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT 0x2
+#define PSX81_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE_MASK 0x8
+#define PSX81_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE__SHIFT 0x3
+#define PSX81_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE_MASK 0x10
+#define PSX81_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE__SHIFT 0x4
+#define PSX81_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x20
+#define PSX81_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5
+#define PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x40
+#define PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6
+#define PSX81_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x80
+#define PSX81_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7
+#define PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x100
+#define PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8
+#define PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x200
+#define PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9
+#define PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x400
+#define PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xa
+#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK 0x800
+#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT 0xb
+#define PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x1000
+#define PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xc
+#define PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x2000
+#define PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xd
+#define PSX81_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x4000
+#define PSX81_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0xe
+#define PSX81_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x8000
+#define PSX81_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0xf
+#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN_MASK 0x10000
+#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN__SHIFT 0x10
+#define PSX81_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0xe0000
+#define PSX81_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x11
+#define PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT_MASK 0x100000
+#define PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT__SHIFT 0x14
+#define PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO_MASK 0x200000
+#define PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO__SHIFT 0x15
+#define PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x400000
+#define PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16
+#define PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x800000
+#define PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17
+#define PSX81_BIF_CPM_CONTROL__SPARE_REGS_MASK 0xff000000
+#define PSX81_BIF_CPM_CONTROL__SPARE_REGS__SHIFT 0x18
+#define PSX81_BIF_LM_CONTROL__LoopbackSelect_MASK 0x1e
+#define PSX81_BIF_LM_CONTROL__LoopbackSelect__SHIFT 0x1
+#define PSX81_BIF_LM_CONTROL__PRBSPCIeLbSelect_MASK 0x20
+#define PSX81_BIF_LM_CONTROL__PRBSPCIeLbSelect__SHIFT 0x5
+#define PSX81_BIF_LM_CONTROL__LoopbackHalfRate_MASK 0xc0
+#define PSX81_BIF_LM_CONTROL__LoopbackHalfRate__SHIFT 0x6
+#define PSX81_BIF_LM_CONTROL__LoopbackFifoPtr_MASK 0x700
+#define PSX81_BIF_LM_CONTROL__LoopbackFifoPtr__SHIFT 0x8
+#define PSX81_BIF_LM_PCIETXMUX0__TXLANE0_MASK 0xff
+#define PSX81_BIF_LM_PCIETXMUX0__TXLANE0__SHIFT 0x0
+#define PSX81_BIF_LM_PCIETXMUX0__TXLANE1_MASK 0xff00
+#define PSX81_BIF_LM_PCIETXMUX0__TXLANE1__SHIFT 0x8
+#define PSX81_BIF_LM_PCIETXMUX0__TXLANE2_MASK 0xff0000
+#define PSX81_BIF_LM_PCIETXMUX0__TXLANE2__SHIFT 0x10
+#define PSX81_BIF_LM_PCIETXMUX0__TXLANE3_MASK 0xff000000
+#define PSX81_BIF_LM_PCIETXMUX0__TXLANE3__SHIFT 0x18
+#define PSX81_BIF_LM_PCIETXMUX1__TXLANE4_MASK 0xff
+#define PSX81_BIF_LM_PCIETXMUX1__TXLANE4__SHIFT 0x0
+#define PSX81_BIF_LM_PCIETXMUX1__TXLANE5_MASK 0xff00
+#define PSX81_BIF_LM_PCIETXMUX1__TXLANE5__SHIFT 0x8
+#define PSX81_BIF_LM_PCIETXMUX1__TXLANE6_MASK 0xff0000
+#define PSX81_BIF_LM_PCIETXMUX1__TXLANE6__SHIFT 0x10
+#define PSX81_BIF_LM_PCIETXMUX1__TXLANE7_MASK 0xff000000
+#define PSX81_BIF_LM_PCIETXMUX1__TXLANE7__SHIFT 0x18
+#define PSX81_BIF_LM_PCIETXMUX2__TXLANE8_MASK 0xff
+#define PSX81_BIF_LM_PCIETXMUX2__TXLANE8__SHIFT 0x0
+#define PSX81_BIF_LM_PCIETXMUX2__TXLANE9_MASK 0xff00
+#define PSX81_BIF_LM_PCIETXMUX2__TXLANE9__SHIFT 0x8
+#define PSX81_BIF_LM_PCIETXMUX2__TXLANE10_MASK 0xff0000
+#define PSX81_BIF_LM_PCIETXMUX2__TXLANE10__SHIFT 0x10
+#define PSX81_BIF_LM_PCIETXMUX2__TXLANE11_MASK 0xff000000
+#define PSX81_BIF_LM_PCIETXMUX2__TXLANE11__SHIFT 0x18
+#define PSX81_BIF_LM_PCIETXMUX3__TXLANE12_MASK 0xff
+#define PSX81_BIF_LM_PCIETXMUX3__TXLANE12__SHIFT 0x0
+#define PSX81_BIF_LM_PCIETXMUX3__TXLANE13_MASK 0xff00
+#define PSX81_BIF_LM_PCIETXMUX3__TXLANE13__SHIFT 0x8
+#define PSX81_BIF_LM_PCIETXMUX3__TXLANE14_MASK 0xff0000
+#define PSX81_BIF_LM_PCIETXMUX3__TXLANE14__SHIFT 0x10
+#define PSX81_BIF_LM_PCIETXMUX3__TXLANE15_MASK 0xff000000
+#define PSX81_BIF_LM_PCIETXMUX3__TXLANE15__SHIFT 0x18
+#define PSX81_BIF_LM_PCIERXMUX0__RXLANE0_MASK 0xff
+#define PSX81_BIF_LM_PCIERXMUX0__RXLANE0__SHIFT 0x0
+#define PSX81_BIF_LM_PCIERXMUX0__RXLANE1_MASK 0xff00
+#define PSX81_BIF_LM_PCIERXMUX0__RXLANE1__SHIFT 0x8
+#define PSX81_BIF_LM_PCIERXMUX0__RXLANE2_MASK 0xff0000
+#define PSX81_BIF_LM_PCIERXMUX0__RXLANE2__SHIFT 0x10
+#define PSX81_BIF_LM_PCIERXMUX0__RXLANE3_MASK 0xff000000
+#define PSX81_BIF_LM_PCIERXMUX0__RXLANE3__SHIFT 0x18
+#define PSX81_BIF_LM_PCIERXMUX1__RXLANE4_MASK 0xff
+#define PSX81_BIF_LM_PCIERXMUX1__RXLANE4__SHIFT 0x0
+#define PSX81_BIF_LM_PCIERXMUX1__RXLANE5_MASK 0xff00
+#define PSX81_BIF_LM_PCIERXMUX1__RXLANE5__SHIFT 0x8
+#define PSX81_BIF_LM_PCIERXMUX1__RXLANE6_MASK 0xff0000
+#define PSX81_BIF_LM_PCIERXMUX1__RXLANE6__SHIFT 0x10
+#define PSX81_BIF_LM_PCIERXMUX1__RXLANE7_MASK 0xff000000
+#define PSX81_BIF_LM_PCIERXMUX1__RXLANE7__SHIFT 0x18
+#define PSX81_BIF_LM_PCIERXMUX2__RXLANE8_MASK 0xff
+#define PSX81_BIF_LM_PCIERXMUX2__RXLANE8__SHIFT 0x0
+#define PSX81_BIF_LM_PCIERXMUX2__RXLANE9_MASK 0xff00
+#define PSX81_BIF_LM_PCIERXMUX2__RXLANE9__SHIFT 0x8
+#define PSX81_BIF_LM_PCIERXMUX2__RXLANE10_MASK 0xff0000
+#define PSX81_BIF_LM_PCIERXMUX2__RXLANE10__SHIFT 0x10
+#define PSX81_BIF_LM_PCIERXMUX2__RXLANE11_MASK 0xff000000
+#define PSX81_BIF_LM_PCIERXMUX2__RXLANE11__SHIFT 0x18
+#define PSX81_BIF_LM_PCIERXMUX3__RXLANE12_MASK 0xff
+#define PSX81_BIF_LM_PCIERXMUX3__RXLANE12__SHIFT 0x0
+#define PSX81_BIF_LM_PCIERXMUX3__RXLANE13_MASK 0xff00
+#define PSX81_BIF_LM_PCIERXMUX3__RXLANE13__SHIFT 0x8
+#define PSX81_BIF_LM_PCIERXMUX3__RXLANE14_MASK 0xff0000
+#define PSX81_BIF_LM_PCIERXMUX3__RXLANE14__SHIFT 0x10
+#define PSX81_BIF_LM_PCIERXMUX3__RXLANE15_MASK 0xff000000
+#define PSX81_BIF_LM_PCIERXMUX3__RXLANE15__SHIFT 0x18
+#define PSX81_BIF_LM_LANEENABLE__LANE_enable_MASK 0xffff
+#define PSX81_BIF_LM_LANEENABLE__LANE_enable__SHIFT 0x0
+#define PSX81_BIF_LM_PRBSCONTROL__PRBSPCIeSelect_MASK 0xffff
+#define PSX81_BIF_LM_PRBSCONTROL__PRBSPCIeSelect__SHIFT 0x0
+#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade0_MASK 0x10000000
+#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade0__SHIFT 0x1c
+#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade1_MASK 0x20000000
+#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade1__SHIFT 0x1d
+#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade2_MASK 0x40000000
+#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade2__SHIFT 0x1e
+#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade3_MASK 0x80000000
+#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade3__SHIFT 0x1f
+#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd0_MASK 0x7
+#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd0__SHIFT 0x0
+#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd0_MASK 0x38
+#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd0__SHIFT 0x3
+#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed0_MASK 0xc0
+#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed0__SHIFT 0x6
+#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd1_MASK 0x700
+#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd1__SHIFT 0x8
+#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd1_MASK 0x3800
+#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd1__SHIFT 0xb
+#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed1_MASK 0xc000
+#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed1__SHIFT 0xe
+#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd2_MASK 0x70000
+#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd2__SHIFT 0x10
+#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd2_MASK 0x380000
+#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd2__SHIFT 0x13
+#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed2_MASK 0xc00000
+#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed2__SHIFT 0x16
+#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd3_MASK 0x7000000
+#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd3__SHIFT 0x18
+#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd3_MASK 0x38000000
+#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd3__SHIFT 0x1b
+#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed3_MASK 0xc0000000
+#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed3__SHIFT 0x1e
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn0_MASK 0x1
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn0__SHIFT 0x0
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn0_MASK 0x2
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn0__SHIFT 0x1
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin0_MASK 0x1c
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin0__SHIFT 0x2
+#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit0_MASK 0x20
+#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit0__SHIFT 0x5
+#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused0_MASK 0x40
+#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused0__SHIFT 0x6
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn0_MASK 0x80
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn0__SHIFT 0x7
+#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph0_MASK 0x100
+#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph0__SHIFT 0x8
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn1_MASK 0x200
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn1__SHIFT 0x9
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn1_MASK 0x400
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn1__SHIFT 0xa
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin1_MASK 0x3800
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin1__SHIFT 0xb
+#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit1_MASK 0x4000
+#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit1__SHIFT 0xe
+#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused1_MASK 0x8000
+#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused1__SHIFT 0xf
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn1_MASK 0x10000
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn1__SHIFT 0x10
+#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph1_MASK 0x20000
+#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph1__SHIFT 0x11
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn2_MASK 0x40000
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn2__SHIFT 0x12
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn2_MASK 0x80000
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn2__SHIFT 0x13
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin2_MASK 0x700000
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin2__SHIFT 0x14
+#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit2_MASK 0x800000
+#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit2__SHIFT 0x17
+#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused2_MASK 0x1000000
+#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused2__SHIFT 0x18
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn2_MASK 0x2000000
+#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn2__SHIFT 0x19
+#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph2_MASK 0x4000000
+#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph2__SHIFT 0x1a
+#define PSX81_BIF_LM_POWERCONTROL1__TxCoeffID0_MASK 0x18000000
+#define PSX81_BIF_LM_POWERCONTROL1__TxCoeffID0__SHIFT 0x1b
+#define PSX81_BIF_LM_POWERCONTROL1__TxCoeffID1_MASK 0x60000000
+#define PSX81_BIF_LM_POWERCONTROL1__TxCoeffID1__SHIFT 0x1d
+#define PSX81_BIF_LM_POWERCONTROL2__LMTxEn3_MASK 0x1
+#define PSX81_BIF_LM_POWERCONTROL2__LMTxEn3__SHIFT 0x0
+#define PSX81_BIF_LM_POWERCONTROL2__LMTxClkEn3_MASK 0x2
+#define PSX81_BIF_LM_POWERCONTROL2__LMTxClkEn3__SHIFT 0x1
+#define PSX81_BIF_LM_POWERCONTROL2__LMTxMargin3_MASK 0x1c
+#define PSX81_BIF_LM_POWERCONTROL2__LMTxMargin3__SHIFT 0x2
+#define PSX81_BIF_LM_POWERCONTROL2__LMSkipBit3_MASK 0x20
+#define PSX81_BIF_LM_POWERCONTROL2__LMSkipBit3__SHIFT 0x5
+#define PSX81_BIF_LM_POWERCONTROL2__LMLaneUnused3_MASK 0x40
+#define PSX81_BIF_LM_POWERCONTROL2__LMLaneUnused3__SHIFT 0x6
+#define PSX81_BIF_LM_POWERCONTROL2__LMTxMarginEn3_MASK 0x80
+#define PSX81_BIF_LM_POWERCONTROL2__LMTxMarginEn3__SHIFT 0x7
+#define PSX81_BIF_LM_POWERCONTROL2__LMDeemph3_MASK 0x100
+#define PSX81_BIF_LM_POWERCONTROL2__LMDeemph3__SHIFT 0x8
+#define PSX81_BIF_LM_POWERCONTROL2__TxCoeffID2_MASK 0x600
+#define PSX81_BIF_LM_POWERCONTROL2__TxCoeffID2__SHIFT 0x9
+#define PSX81_BIF_LM_POWERCONTROL2__TxCoeffID3_MASK 0x1800
+#define PSX81_BIF_LM_POWERCONTROL2__TxCoeffID3__SHIFT 0xb
+#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff0_MASK 0x7e000
+#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff0__SHIFT 0xd
+#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff1_MASK 0x1f80000
+#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff1__SHIFT 0x13
+#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff2_MASK 0x7e000000
+#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff2__SHIFT 0x19
+#define PSX81_BIF_LM_POWERCONTROL3__TxCoeff3_MASK 0x3f
+#define PSX81_BIF_LM_POWERCONTROL3__TxCoeff3__SHIFT 0x0
+#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl0_MASK 0xfc0
+#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl0__SHIFT 0x6
+#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl1_MASK 0x3f000
+#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl1__SHIFT 0xc
+#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl2_MASK 0xfc0000
+#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl2__SHIFT 0x12
+#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl3_MASK 0x3f000000
+#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl3__SHIFT 0x18
+#define PSX81_BIF_LM_POWERCONTROL4__LinkNum0_MASK 0x7
+#define PSX81_BIF_LM_POWERCONTROL4__LinkNum0__SHIFT 0x0
+#define PSX81_BIF_LM_POWERCONTROL4__LinkNum1_MASK 0x38
+#define PSX81_BIF_LM_POWERCONTROL4__LinkNum1__SHIFT 0x3
+#define PSX81_BIF_LM_POWERCONTROL4__LinkNum2_MASK 0x1c0
+#define PSX81_BIF_LM_POWERCONTROL4__LinkNum2__SHIFT 0x6
+#define PSX81_BIF_LM_POWERCONTROL4__LinkNum3_MASK 0xe00
+#define PSX81_BIF_LM_POWERCONTROL4__LinkNum3__SHIFT 0x9
+#define PSX81_BIF_LM_POWERCONTROL4__LaneNum0_MASK 0xf000
+#define PSX81_BIF_LM_POWERCONTROL4__LaneNum0__SHIFT 0xc
+#define PSX81_BIF_LM_POWERCONTROL4__LaneNum1_MASK 0xf0000
+#define PSX81_BIF_LM_POWERCONTROL4__LaneNum1__SHIFT 0x10
+#define PSX81_BIF_LM_POWERCONTROL4__LaneNum2_MASK 0xf00000
+#define PSX81_BIF_LM_POWERCONTROL4__LaneNum2__SHIFT 0x14
+#define PSX81_BIF_LM_POWERCONTROL4__LaneNum3_MASK 0xf000000
+#define PSX81_BIF_LM_POWERCONTROL4__LaneNum3__SHIFT 0x18
+#define PSX81_BIF_LM_POWERCONTROL4__SpcMode0_MASK 0x10000000
+#define PSX81_BIF_LM_POWERCONTROL4__SpcMode0__SHIFT 0x1c
+#define PSX81_BIF_LM_POWERCONTROL4__SpcMode1_MASK 0x20000000
+#define PSX81_BIF_LM_POWERCONTROL4__SpcMode1__SHIFT 0x1d
+#define PSX81_BIF_LM_POWERCONTROL4__SpcMode2_MASK 0x40000000
+#define PSX81_BIF_LM_POWERCONTROL4__SpcMode2__SHIFT 0x1e
+#define PSX81_BIF_LM_POWERCONTROL4__SpcMode3_MASK 0x80000000
+#define PSX81_BIF_LM_POWERCONTROL4__SpcMode3__SHIFT 0x1f
+#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_valid_MASK 0x1
+#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
+#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel_MASK 0x6
+#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel__SHIFT 0x1
+#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable_MASK 0x8
+#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable__SHIFT 0x3
+#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12_MASK 0xf0
+#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12__SHIFT 0x4
+#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12_MASK 0x100
+#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12__SHIFT 0x8
+#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x600
+#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0x9
+#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x1800
+#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0xb
+#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time_MASK 0xc0000
+#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time__SHIFT 0x12
+#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_spare_MASK 0xfff00000
+#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_spare__SHIFT 0x14
+#define PSX80_PHY0_COM_COMMON_FUSE2__fuse2_valid_MASK 0x1
+#define PSX80_PHY0_COM_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
+#define PSX80_PHY0_COM_COMMON_FUSE2__fuse2_spare_MASK 0xfffffffe
+#define PSX80_PHY0_COM_COMMON_FUSE2__fuse2_spare__SHIFT 0x1
+#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_valid_MASK 0x1
+#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
+#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel_MASK 0xe
+#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel__SHIFT 0x1
+#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val_MASK 0x3f0
+#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val__SHIFT 0x4
+#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val_MASK 0xfc00
+#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val__SHIFT 0xa
+#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj_MASK 0xf0000
+#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj__SHIFT 0x10
+#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj_MASK 0xf00000
+#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj__SHIFT 0x14
+#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj_MASK 0xf000000
+#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj__SHIFT 0x18
+#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en_MASK 0x10000000
+#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en__SHIFT 0x1c
+#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_spare_MASK 0xe0000000
+#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
+#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0_MASK 0x1
+#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0__SHIFT 0x0
+#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal_MASK 0x2
+#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal__SHIFT 0x1
+#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel_MASK 0x4
+#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel__SHIFT 0x2
+#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code_MASK 0x3f0
+#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code__SHIFT 0x4
+#define PSX80_PHY0_COM_COMMON_DFX__nelb_en_MASK 0x1
+#define PSX80_PHY0_COM_COMMON_DFX__nelb_en__SHIFT 0x0
+#define PSX80_PHY0_COM_COMMON_DFX__prbs_seed_MASK 0x7fe
+#define PSX80_PHY0_COM_COMMON_DFX__prbs_seed__SHIFT 0x1
+#define PSX80_PHY0_COM_COMMON_DFX__force_cdr_en_MASK 0x800
+#define PSX80_PHY0_COM_COMMON_DFX__force_cdr_en__SHIFT 0xb
+#define PSX80_PHY0_COM_COMMON_DFX__ovrd_pll_on_MASK 0x2000
+#define PSX80_PHY0_COM_COMMON_DFX__ovrd_pll_on__SHIFT 0xd
+#define PSX80_PHY0_COM_COMMON_DFX__ovrd_clk_en_MASK 0x8000
+#define PSX80_PHY0_COM_COMMON_DFX__ovrd_clk_en__SHIFT 0xf
+#define PSX80_PHY0_COM_COMMON_DFX__dsm_sel_MASK 0x7e0000
+#define PSX80_PHY0_COM_COMMON_DFX__dsm_sel__SHIFT 0x11
+#define PSX80_PHY0_COM_COMMON_DFX__dsm_en_MASK 0xf000000
+#define PSX80_PHY0_COM_COMMON_DFX__dsm_en__SHIFT 0x18
+#define PSX80_PHY0_COM_COMMON_DFX__hold_rdy_response_MASK 0x20000000
+#define PSX80_PHY0_COM_COMMON_DFX__hold_rdy_response__SHIFT 0x1d
+#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0xff
+#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
+#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0xff00
+#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
+#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0xff0000
+#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
+#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xff000000
+#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
+#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1_MASK 0xff
+#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1__SHIFT 0x0
+#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2_MASK 0xff00
+#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2__SHIFT 0x8
+#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3_MASK 0xff0000
+#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3__SHIFT 0x10
+#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4_MASK 0xff000000
+#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4__SHIFT 0x18
+#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1_MASK 0xff
+#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1__SHIFT 0x0
+#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2_MASK 0xff00
+#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2__SHIFT 0x8
+#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3_MASK 0xff0000
+#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3__SHIFT 0x10
+#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4_MASK 0xff000000
+#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4__SHIFT 0x18
+#define PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay_MASK 0xf
+#define PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
+#define PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask_MASK 0x3f0
+#define PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber_MASK 0x7
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber__SHIFT 0x0
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time_MASK 0xf0
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time__SHIFT 0x4
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time_MASK 0x1e00
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time__SHIFT 0x9
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time_MASK 0x3c000
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time__SHIFT 0xe
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time_MASK 0x780000
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time__SHIFT 0x13
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time_MASK 0x1e000000
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time__SHIFT 0x19
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel_MASK 0xe0000000
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel__SHIFT 0x1d
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain_MASK 0x3
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain__SHIFT 0x0
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain_MASK 0x78
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain__SHIFT 0x3
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain_MASK 0xf00
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain__SHIFT 0x8
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain_MASK 0x1e000
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain__SHIFT 0xd
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain_MASK 0x3c0000
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain__SHIFT 0x12
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt_MASK 0x3800000
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt__SHIFT 0x17
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt_MASK 0x38000000
+#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt__SHIFT 0x1b
+#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val_MASK 0x1f
+#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val__SHIFT 0x0
+#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val_MASK 0x7c0
+#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val__SHIFT 0x6
+#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val_MASK 0xe000
+#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val__SHIFT 0xd
+#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val_MASK 0xe0000
+#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val__SHIFT 0x11
+#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val_MASK 0xfc00000
+#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val__SHIFT 0x16
+#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val_MASK 0x3f
+#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val__SHIFT 0x0
+#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val_MASK 0xf00
+#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val__SHIFT 0x8
+#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val_MASK 0x1e000
+#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val__SHIFT 0xd
+#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val_MASK 0x1ff
+#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val__SHIFT 0x0
+#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val_MASK 0xff800
+#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val__SHIFT 0xb
+#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val_MASK 0x7fc00000
+#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val__SHIFT 0x16
+#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val_MASK 0x3f
+#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val__SHIFT 0x0
+#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val_MASK 0x1f80
+#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val__SHIFT 0x7
+#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode_MASK 0x7
+#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode__SHIFT 0x0
+#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec_MASK 0x1c0
+#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec__SHIFT 0x6
+#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst_MASK 0x3fffc00
+#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst__SHIFT 0xa
+#define PSX80_PHY0_COM_COMMON_LNCNTRL__clkgate_dis_MASK 0x20
+#define PSX80_PHY0_COM_COMMON_LNCNTRL__clkgate_dis__SHIFT 0x5
+#define PSX80_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel_MASK 0xc0
+#define PSX80_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel__SHIFT 0x6
+#define PSX80_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel_MASK 0x300
+#define PSX80_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel__SHIFT 0x8
+#define PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel_MASK 0x1f
+#define PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel__SHIFT 0x0
+#define PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en_MASK 0x40
+#define PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en__SHIFT 0x6
+#define PSX80_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel_MASK 0x70
+#define PSX80_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel__SHIFT 0x4
+#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3_MASK 0x1
+#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3__SHIFT 0x0
+#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3_MASK 0x780
+#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3__SHIFT 0x7
+#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val_MASK 0x7e000
+#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val__SHIFT 0xd
+#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en_MASK 0x1
+#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en__SHIFT 0x0
+#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12_MASK 0x3c
+#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12__SHIFT 0x2
+#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3_MASK 0x780
+#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3__SHIFT 0x7
+#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val_MASK 0x1ff000
+#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val__SHIFT 0xc
+#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit_MASK 0xc00000
+#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit__SHIFT 0x16
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr_MASK 0x7
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr__SHIFT 0x0
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en_MASK 0x18
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en__SHIFT 0x3
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en_MASK 0x20
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en__SHIFT 0x5
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr_MASK 0x7
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr__SHIFT 0x0
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en_MASK 0x18
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en__SHIFT 0x3
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en_MASK 0x20
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en__SHIFT 0x5
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr_MASK 0x7
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr__SHIFT 0x0
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en_MASK 0x18
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en__SHIFT 0x3
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en_MASK 0x20
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en__SHIFT 0x5
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr_MASK 0x7
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr__SHIFT 0x0
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en_MASK 0x18
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en__SHIFT 0x3
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en_MASK 0x20
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en__SHIFT 0x5
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr_MASK 0x7
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr__SHIFT 0x0
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en_MASK 0x18
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en__SHIFT 0x3
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en_MASK 0x20
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en__SHIFT 0x5
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr_MASK 0x7
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr__SHIFT 0x0
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en_MASK 0x18
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en__SHIFT 0x3
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en_MASK 0x20
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en__SHIFT 0x5
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr_MASK 0x7
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr__SHIFT 0x0
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en_MASK 0x18
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en__SHIFT 0x3
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en_MASK 0x20
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en__SHIFT 0x5
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr_MASK 0x7
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr__SHIFT 0x0
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en_MASK 0x18
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en__SHIFT 0x3
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en_MASK 0x20
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en__SHIFT 0x5
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr_MASK 0x7
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr__SHIFT 0x0
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en_MASK 0x18
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en__SHIFT 0x3
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en_MASK 0x20
+#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en__SHIFT 0x5
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en_MASK 0x1
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en__SHIFT 0x0
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed_MASK 0x6
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed__SHIFT 0x1
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2_MASK 0x8
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2__SHIFT 0x3
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en_MASK 0x1
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en__SHIFT 0x0
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed_MASK 0x6
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed__SHIFT 0x1
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2_MASK 0x8
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2__SHIFT 0x3
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en_MASK 0x1
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en__SHIFT 0x0
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed_MASK 0x6
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed__SHIFT 0x1
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2_MASK 0x8
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2__SHIFT 0x3
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en_MASK 0x1
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en__SHIFT 0x0
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed_MASK 0x6
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed__SHIFT 0x1
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2_MASK 0x8
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2__SHIFT 0x3
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en_MASK 0x1
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en__SHIFT 0x0
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed_MASK 0x6
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed__SHIFT 0x1
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2_MASK 0x8
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2__SHIFT 0x3
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en_MASK 0x1
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en__SHIFT 0x0
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed_MASK 0x6
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed__SHIFT 0x1
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2_MASK 0x8
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2__SHIFT 0x3
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en_MASK 0x1
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en__SHIFT 0x0
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed_MASK 0x6
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed__SHIFT 0x1
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2_MASK 0x8
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2__SHIFT 0x3
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en_MASK 0x1
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en__SHIFT 0x0
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed_MASK 0x6
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed__SHIFT 0x1
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2_MASK 0x8
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2__SHIFT 0x3
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en_MASK 0x1
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en__SHIFT 0x0
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed_MASK 0x6
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed__SHIFT 0x1
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2_MASK 0x8
+#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2__SHIFT 0x3
+#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis_MASK 0x1
+#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis__SHIFT 0x0
+#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc_MASK 0x1fe
+#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc__SHIFT 0x1
+#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode_MASK 0x1800
+#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode__SHIFT 0xb
+#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri_MASK 0x2000
+#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri__SHIFT 0xd
+#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity_MASK 0x4000
+#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity__SHIFT 0xe
+#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign_MASK 0x8000
+#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign__SHIFT 0xf
+#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis_MASK 0x1
+#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis__SHIFT 0x0
+#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc_MASK 0x1fe
+#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc__SHIFT 0x1
+#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_term_mode_MASK 0x1800
+#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_term_mode__SHIFT 0xb
+#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri_MASK 0x2000
+#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri__SHIFT 0xd
+#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity_MASK 0x4000
+#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity__SHIFT 0xe
+#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign_MASK 0x8000
+#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign__SHIFT 0xf
+#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis_MASK 0x1
+#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis__SHIFT 0x0
+#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc_MASK 0x1fe
+#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc__SHIFT 0x1
+#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_term_mode_MASK 0x1800
+#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_term_mode__SHIFT 0xb
+#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri_MASK 0x2000
+#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri__SHIFT 0xd
+#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity_MASK 0x4000
+#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity__SHIFT 0xe
+#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign_MASK 0x8000
+#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign__SHIFT 0xf
+#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis_MASK 0x1
+#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis__SHIFT 0x0
+#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc_MASK 0x1fe
+#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc__SHIFT 0x1
+#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_term_mode_MASK 0x1800
+#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_term_mode__SHIFT 0xb
+#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri_MASK 0x2000
+#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri__SHIFT 0xd
+#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity_MASK 0x4000
+#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity__SHIFT 0xe
+#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign_MASK 0x8000
+#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign__SHIFT 0xf
+#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis_MASK 0x1
+#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis__SHIFT 0x0
+#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc_MASK 0x1fe
+#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc__SHIFT 0x1
+#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_term_mode_MASK 0x1800
+#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_term_mode__SHIFT 0xb
+#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri_MASK 0x2000
+#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri__SHIFT 0xd
+#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity_MASK 0x4000
+#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity__SHIFT 0xe
+#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign_MASK 0x8000
+#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign__SHIFT 0xf
+#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis_MASK 0x1
+#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis__SHIFT 0x0
+#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc_MASK 0x1fe
+#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc__SHIFT 0x1
+#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_term_mode_MASK 0x1800
+#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_term_mode__SHIFT 0xb
+#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri_MASK 0x2000
+#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri__SHIFT 0xd
+#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity_MASK 0x4000
+#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity__SHIFT 0xe
+#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign_MASK 0x8000
+#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign__SHIFT 0xf
+#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis_MASK 0x1
+#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis__SHIFT 0x0
+#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc_MASK 0x1fe
+#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc__SHIFT 0x1
+#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_term_mode_MASK 0x1800
+#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_term_mode__SHIFT 0xb
+#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri_MASK 0x2000
+#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri__SHIFT 0xd
+#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity_MASK 0x4000
+#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity__SHIFT 0xe
+#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign_MASK 0x8000
+#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign__SHIFT 0xf
+#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis_MASK 0x1
+#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis__SHIFT 0x0
+#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc_MASK 0x1fe
+#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc__SHIFT 0x1
+#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_term_mode_MASK 0x1800
+#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_term_mode__SHIFT 0xb
+#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri_MASK 0x2000
+#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri__SHIFT 0xd
+#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity_MASK 0x4000
+#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity__SHIFT 0xe
+#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign_MASK 0x8000
+#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign__SHIFT 0xf
+#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis_MASK 0x1
+#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis__SHIFT 0x0
+#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc_MASK 0x1fe
+#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc__SHIFT 0x1
+#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_term_mode_MASK 0x1800
+#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_term_mode__SHIFT 0xb
+#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri_MASK 0x2000
+#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri__SHIFT 0xd
+#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity_MASK 0x4000
+#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity__SHIFT 0xe
+#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign_MASK 0x8000
+#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign__SHIFT 0xf
+#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel_MASK 0x7
+#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel__SHIFT 0x0
+#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel_MASK 0x10
+#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel__SHIFT 0x4
+#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en_MASK 0x20
+#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en__SHIFT 0x5
+#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl_MASK 0x80
+#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl__SHIFT 0x7
+#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel_MASK 0x7
+#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel__SHIFT 0x0
+#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel_MASK 0x10
+#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel__SHIFT 0x4
+#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en_MASK 0x20
+#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en__SHIFT 0x5
+#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl_MASK 0x80
+#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl__SHIFT 0x7
+#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel_MASK 0x7
+#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel__SHIFT 0x0
+#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel_MASK 0x10
+#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel__SHIFT 0x4
+#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en_MASK 0x20
+#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en__SHIFT 0x5
+#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl_MASK 0x80
+#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl__SHIFT 0x7
+#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel_MASK 0x7
+#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel__SHIFT 0x0
+#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel_MASK 0x10
+#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel__SHIFT 0x4
+#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en_MASK 0x20
+#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en__SHIFT 0x5
+#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl_MASK 0x80
+#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl__SHIFT 0x7
+#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel_MASK 0x7
+#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel__SHIFT 0x0
+#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel_MASK 0x10
+#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel__SHIFT 0x4
+#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en_MASK 0x20
+#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en__SHIFT 0x5
+#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl_MASK 0x80
+#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl__SHIFT 0x7
+#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel_MASK 0x7
+#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel__SHIFT 0x0
+#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel_MASK 0x10
+#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel__SHIFT 0x4
+#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en_MASK 0x20
+#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en__SHIFT 0x5
+#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl_MASK 0x80
+#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl__SHIFT 0x7
+#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel_MASK 0x7
+#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel__SHIFT 0x0
+#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel_MASK 0x10
+#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel__SHIFT 0x4
+#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en_MASK 0x20
+#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en__SHIFT 0x5
+#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl_MASK 0x80
+#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl__SHIFT 0x7
+#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel_MASK 0x7
+#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel__SHIFT 0x0
+#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel_MASK 0x10
+#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel__SHIFT 0x4
+#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en_MASK 0x20
+#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en__SHIFT 0x5
+#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl_MASK 0x80
+#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl__SHIFT 0x7
+#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel_MASK 0x7
+#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel__SHIFT 0x0
+#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel_MASK 0x10
+#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel__SHIFT 0x4
+#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en_MASK 0x20
+#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en__SHIFT 0x5
+#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl_MASK 0x80
+#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl__SHIFT 0x7
+#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr_MASK 0x1
+#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr__SHIFT 0x0
+#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err_MASK 0x2
+#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err__SHIFT 0x1
+#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force_MASK 0x10
+#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force__SHIFT 0x4
+#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en_MASK 0x20
+#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en__SHIFT 0x5
+#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap_MASK 0x40
+#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap__SHIFT 0x6
+#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res_MASK 0x80
+#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res__SHIFT 0x7
+#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate_MASK 0x100
+#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate__SHIFT 0x8
+#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out_MASK 0x400
+#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out__SHIFT 0xa
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr_MASK 0x1
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr__SHIFT 0x0
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_err_MASK 0x2
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_err__SHIFT 0x1
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force_MASK 0x10
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force__SHIFT 0x4
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en_MASK 0x20
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en__SHIFT 0x5
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap_MASK 0x40
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap__SHIFT 0x6
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res_MASK 0x80
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res__SHIFT 0x7
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate_MASK 0x100
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate__SHIFT 0x8
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out_MASK 0x400
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out__SHIFT 0xa
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr_MASK 0x1
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr__SHIFT 0x0
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_err_MASK 0x2
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_err__SHIFT 0x1
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force_MASK 0x10
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force__SHIFT 0x4
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en_MASK 0x20
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en__SHIFT 0x5
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap_MASK 0x40
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap__SHIFT 0x6
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res_MASK 0x80
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res__SHIFT 0x7
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate_MASK 0x100
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate__SHIFT 0x8
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out_MASK 0x400
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out__SHIFT 0xa
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr_MASK 0x1
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr__SHIFT 0x0
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_err_MASK 0x2
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_err__SHIFT 0x1
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force_MASK 0x10
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force__SHIFT 0x4
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en_MASK 0x20
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en__SHIFT 0x5
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap_MASK 0x40
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap__SHIFT 0x6
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res_MASK 0x80
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res__SHIFT 0x7
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate_MASK 0x100
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate__SHIFT 0x8
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out_MASK 0x400
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out__SHIFT 0xa
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr_MASK 0x1
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr__SHIFT 0x0
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_err_MASK 0x2
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_err__SHIFT 0x1
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force_MASK 0x10
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force__SHIFT 0x4
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en_MASK 0x20
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en__SHIFT 0x5
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap_MASK 0x40
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap__SHIFT 0x6
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res_MASK 0x80
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res__SHIFT 0x7
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate_MASK 0x100
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate__SHIFT 0x8
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out_MASK 0x400
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out__SHIFT 0xa
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr_MASK 0x1
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr__SHIFT 0x0
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_err_MASK 0x2
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_err__SHIFT 0x1
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force_MASK 0x10
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force__SHIFT 0x4
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en_MASK 0x20
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en__SHIFT 0x5
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap_MASK 0x40
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap__SHIFT 0x6
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res_MASK 0x80
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res__SHIFT 0x7
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate_MASK 0x100
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate__SHIFT 0x8
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out_MASK 0x400
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out__SHIFT 0xa
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr_MASK 0x1
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr__SHIFT 0x0
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_err_MASK 0x2
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_err__SHIFT 0x1
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force_MASK 0x10
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force__SHIFT 0x4
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en_MASK 0x20
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en__SHIFT 0x5
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap_MASK 0x40
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap__SHIFT 0x6
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res_MASK 0x80
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res__SHIFT 0x7
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate_MASK 0x100
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate__SHIFT 0x8
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out_MASK 0x400
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out__SHIFT 0xa
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr_MASK 0x1
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr__SHIFT 0x0
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_err_MASK 0x2
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_err__SHIFT 0x1
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force_MASK 0x10
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force__SHIFT 0x4
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en_MASK 0x20
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en__SHIFT 0x5
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap_MASK 0x40
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap__SHIFT 0x6
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res_MASK 0x80
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res__SHIFT 0x7
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate_MASK 0x100
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate__SHIFT 0x8
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out_MASK 0x400
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out__SHIFT 0xa
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr_MASK 0x1
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr__SHIFT 0x0
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_err_MASK 0x2
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_err__SHIFT 0x1
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force_MASK 0x10
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force__SHIFT 0x4
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en_MASK 0x20
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en__SHIFT 0x5
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap_MASK 0x40
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap__SHIFT 0x6
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res_MASK 0x80
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res__SHIFT 0x7
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate_MASK 0x100
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate__SHIFT 0x8
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out_MASK 0x400
+#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out__SHIFT 0xa
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei_MASK 0x1
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei__SHIFT 0x0
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out_MASK 0x2
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out__SHIFT 0x1
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds_MASK 0x4
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds__SHIFT 0x2
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj_MASK 0x1f8
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj__SHIFT 0x3
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en_MASK 0x400
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en__SHIFT 0xa
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei_MASK 0x1
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei__SHIFT 0x0
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out_MASK 0x2
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out__SHIFT 0x1
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds_MASK 0x4
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds__SHIFT 0x2
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj_MASK 0x1f8
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj__SHIFT 0x3
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en_MASK 0x400
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en__SHIFT 0xa
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei_MASK 0x1
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei__SHIFT 0x0
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out_MASK 0x2
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out__SHIFT 0x1
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds_MASK 0x4
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds__SHIFT 0x2
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj_MASK 0x1f8
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj__SHIFT 0x3
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en_MASK 0x400
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en__SHIFT 0xa
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei_MASK 0x1
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei__SHIFT 0x0
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out_MASK 0x2
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out__SHIFT 0x1
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds_MASK 0x4
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds__SHIFT 0x2
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj_MASK 0x1f8
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj__SHIFT 0x3
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en_MASK 0x400
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en__SHIFT 0xa
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei_MASK 0x1
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei__SHIFT 0x0
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out_MASK 0x2
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out__SHIFT 0x1
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds_MASK 0x4
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds__SHIFT 0x2
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj_MASK 0x1f8
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj__SHIFT 0x3
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en_MASK 0x400
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en__SHIFT 0xa
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei_MASK 0x1
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei__SHIFT 0x0
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out_MASK 0x2
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out__SHIFT 0x1
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds_MASK 0x4
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds__SHIFT 0x2
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj_MASK 0x1f8
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj__SHIFT 0x3
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en_MASK 0x400
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en__SHIFT 0xa
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei_MASK 0x1
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei__SHIFT 0x0
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out_MASK 0x2
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out__SHIFT 0x1
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds_MASK 0x4
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds__SHIFT 0x2
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj_MASK 0x1f8
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj__SHIFT 0x3
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en_MASK 0x400
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en__SHIFT 0xa
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei_MASK 0x1
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei__SHIFT 0x0
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out_MASK 0x2
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out__SHIFT 0x1
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds_MASK 0x4
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds__SHIFT 0x2
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj_MASK 0x1f8
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj__SHIFT 0x3
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en_MASK 0x400
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en__SHIFT 0xa
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei_MASK 0x1
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei__SHIFT 0x0
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out_MASK 0x2
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out__SHIFT 0x1
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds_MASK 0x4
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds__SHIFT 0x2
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj_MASK 0x1f8
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj__SHIFT 0x3
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en_MASK 0x400
+#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en__SHIFT 0xa
+#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode_MASK 0x3ff
+#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel_MASK 0xe000
+#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel__SHIFT 0xd
+#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off_MASK 0x20000
+#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off__SHIFT 0x11
+#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel_MASK 0x180000
+#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
+#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode_MASK 0x3ff
+#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel_MASK 0xe000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel__SHIFT 0xd
+#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off_MASK 0x20000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off__SHIFT 0x11
+#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel_MASK 0x180000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
+#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode_MASK 0x3ff
+#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel_MASK 0xe000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel__SHIFT 0xd
+#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off_MASK 0x20000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off__SHIFT 0x11
+#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel_MASK 0x180000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
+#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode_MASK 0x3ff
+#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel_MASK 0xe000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel__SHIFT 0xd
+#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off_MASK 0x20000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off__SHIFT 0x11
+#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel_MASK 0x180000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
+#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode_MASK 0x3ff
+#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel_MASK 0xe000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel__SHIFT 0xd
+#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off_MASK 0x20000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off__SHIFT 0x11
+#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel_MASK 0x180000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
+#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode_MASK 0x3ff
+#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel_MASK 0xe000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel__SHIFT 0xd
+#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off_MASK 0x20000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off__SHIFT 0x11
+#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel_MASK 0x180000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
+#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode_MASK 0x3ff
+#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel_MASK 0xe000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel__SHIFT 0xd
+#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off_MASK 0x20000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off__SHIFT 0x11
+#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel_MASK 0x180000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
+#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode_MASK 0x3ff
+#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel_MASK 0xe000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel__SHIFT 0xd
+#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off_MASK 0x20000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off__SHIFT 0x11
+#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel_MASK 0x180000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
+#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode_MASK 0x3ff
+#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel_MASK 0xe000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel__SHIFT 0xd
+#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off_MASK 0x20000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off__SHIFT 0x11
+#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel_MASK 0x180000
+#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
+#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid_MASK 0x1
+#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid__SHIFT 0x0
+#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom_MASK 0x1fe
+#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom__SHIFT 0x1
+#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom_MASK 0x800
+#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom__SHIFT 0xb
+#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom_MASK 0x1000
+#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom__SHIFT 0xc
+#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk_MASK 0x2000
+#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk__SHIFT 0xd
+#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn_MASK 0x4000
+#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn__SHIFT 0xe
+#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode_MASK 0x10000
+#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode__SHIFT 0x10
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid_MASK 0x1
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid__SHIFT 0x0
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom_MASK 0x1fe
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom__SHIFT 0x1
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__enable_fom_MASK 0x800
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__enable_fom__SHIFT 0xb
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_fom_MASK 0x1000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_fom__SHIFT 0xc
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trk_MASK 0x2000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trk__SHIFT 0xd
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trn_MASK 0x4000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trn__SHIFT 0xe
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__response_mode_MASK 0x10000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__response_mode__SHIFT 0x10
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid_MASK 0x1
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid__SHIFT 0x0
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom_MASK 0x1fe
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom__SHIFT 0x1
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__enable_fom_MASK 0x800
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__enable_fom__SHIFT 0xb
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_fom_MASK 0x1000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_fom__SHIFT 0xc
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trk_MASK 0x2000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trk__SHIFT 0xd
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trn_MASK 0x4000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trn__SHIFT 0xe
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__response_mode_MASK 0x10000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__response_mode__SHIFT 0x10
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid_MASK 0x1
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid__SHIFT 0x0
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom_MASK 0x1fe
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom__SHIFT 0x1
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__enable_fom_MASK 0x800
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__enable_fom__SHIFT 0xb
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_fom_MASK 0x1000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_fom__SHIFT 0xc
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trk_MASK 0x2000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trk__SHIFT 0xd
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trn_MASK 0x4000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trn__SHIFT 0xe
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__response_mode_MASK 0x10000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__response_mode__SHIFT 0x10
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid_MASK 0x1
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid__SHIFT 0x0
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom_MASK 0x1fe
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom__SHIFT 0x1
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__enable_fom_MASK 0x800
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__enable_fom__SHIFT 0xb
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_fom_MASK 0x1000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_fom__SHIFT 0xc
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trk_MASK 0x2000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trk__SHIFT 0xd
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trn_MASK 0x4000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trn__SHIFT 0xe
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__response_mode_MASK 0x10000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__response_mode__SHIFT 0x10
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid_MASK 0x1
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid__SHIFT 0x0
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom_MASK 0x1fe
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom__SHIFT 0x1
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__enable_fom_MASK 0x800
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__enable_fom__SHIFT 0xb
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_fom_MASK 0x1000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_fom__SHIFT 0xc
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trk_MASK 0x2000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trk__SHIFT 0xd
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trn_MASK 0x4000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trn__SHIFT 0xe
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__response_mode_MASK 0x10000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__response_mode__SHIFT 0x10
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid_MASK 0x1
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid__SHIFT 0x0
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom_MASK 0x1fe
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom__SHIFT 0x1
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__enable_fom_MASK 0x800
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__enable_fom__SHIFT 0xb
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_fom_MASK 0x1000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_fom__SHIFT 0xc
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trk_MASK 0x2000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trk__SHIFT 0xd
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trn_MASK 0x4000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trn__SHIFT 0xe
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__response_mode_MASK 0x10000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__response_mode__SHIFT 0x10
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid_MASK 0x1
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid__SHIFT 0x0
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom_MASK 0x1fe
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom__SHIFT 0x1
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__enable_fom_MASK 0x800
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__enable_fom__SHIFT 0xb
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_fom_MASK 0x1000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_fom__SHIFT 0xc
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trk_MASK 0x2000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trk__SHIFT 0xd
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trn_MASK 0x4000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trn__SHIFT 0xe
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__response_mode_MASK 0x10000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__response_mode__SHIFT 0x10
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid_MASK 0x1
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid__SHIFT 0x0
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom_MASK 0x1fe
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom__SHIFT 0x1
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__enable_fom_MASK 0x800
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__enable_fom__SHIFT 0xb
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_fom_MASK 0x1000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_fom__SHIFT 0xc
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trk_MASK 0x2000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trk__SHIFT 0xd
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trn_MASK 0x4000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trn__SHIFT 0xe
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__response_mode_MASK 0x10000
+#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__response_mode__SHIFT 0x10
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
+#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
+#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en_MASK 0x1
+#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en__SHIFT 0x0
+#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en_MASK 0x2
+#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en__SHIFT 0x1
+#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en_MASK 0x4
+#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en__SHIFT 0x2
+#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
+#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
+#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
+#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
+#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
+#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
+#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en_MASK 0x40
+#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en__SHIFT 0x6
+#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en_MASK 0x80
+#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en__SHIFT 0x7
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en_MASK 0x1
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en__SHIFT 0x0
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en_MASK 0x2
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en__SHIFT 0x1
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en_MASK 0x4
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en__SHIFT 0x2
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en_MASK 0x40
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en__SHIFT 0x6
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en_MASK 0x80
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en__SHIFT 0x7
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en_MASK 0x1
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en__SHIFT 0x0
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en_MASK 0x2
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en__SHIFT 0x1
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en_MASK 0x4
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en__SHIFT 0x2
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en_MASK 0x40
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en__SHIFT 0x6
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en_MASK 0x80
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en__SHIFT 0x7
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en_MASK 0x1
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en__SHIFT 0x0
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en_MASK 0x2
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en__SHIFT 0x1
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en_MASK 0x4
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en__SHIFT 0x2
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en_MASK 0x40
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en__SHIFT 0x6
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en_MASK 0x80
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en__SHIFT 0x7
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en_MASK 0x1
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en__SHIFT 0x0
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en_MASK 0x2
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en__SHIFT 0x1
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en_MASK 0x4
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en__SHIFT 0x2
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en_MASK 0x40
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en__SHIFT 0x6
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en_MASK 0x80
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en__SHIFT 0x7
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en_MASK 0x1
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en__SHIFT 0x0
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en_MASK 0x2
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en__SHIFT 0x1
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en_MASK 0x4
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en__SHIFT 0x2
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en_MASK 0x40
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en__SHIFT 0x6
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en_MASK 0x80
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en__SHIFT 0x7
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en_MASK 0x1
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en__SHIFT 0x0
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en_MASK 0x2
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en__SHIFT 0x1
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en_MASK 0x4
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en__SHIFT 0x2
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en_MASK 0x40
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en__SHIFT 0x6
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en_MASK 0x80
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en__SHIFT 0x7
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en_MASK 0x1
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en__SHIFT 0x0
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en_MASK 0x2
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en__SHIFT 0x1
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en_MASK 0x4
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en__SHIFT 0x2
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en_MASK 0x40
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en__SHIFT 0x6
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en_MASK 0x80
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en__SHIFT 0x7
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en_MASK 0x1
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en__SHIFT 0x0
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en_MASK 0x2
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en__SHIFT 0x1
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en_MASK 0x4
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en__SHIFT 0x2
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en_MASK 0x40
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en__SHIFT 0x6
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en_MASK 0x80
+#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en__SHIFT 0x7
+#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel_MASK 0xf
+#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out_MASK 0x1ffc0
+#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out__SHIFT 0x6
+#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst_MASK 0x80000
+#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst__SHIFT 0x13
+#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en_MASK 0x100000
+#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en__SHIFT 0x14
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel_MASK 0xf
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out_MASK 0x1ffc0
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out__SHIFT 0x6
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst_MASK 0x80000
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst__SHIFT 0x13
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en_MASK 0x100000
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en__SHIFT 0x14
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel_MASK 0xf
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out_MASK 0x1ffc0
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out__SHIFT 0x6
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst_MASK 0x80000
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst__SHIFT 0x13
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en_MASK 0x100000
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en__SHIFT 0x14
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel_MASK 0xf
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out_MASK 0x1ffc0
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out__SHIFT 0x6
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst_MASK 0x80000
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst__SHIFT 0x13
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en_MASK 0x100000
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en__SHIFT 0x14
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel_MASK 0xf
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out_MASK 0x1ffc0
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out__SHIFT 0x6
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst_MASK 0x80000
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst__SHIFT 0x13
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en_MASK 0x100000
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en__SHIFT 0x14
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel_MASK 0xf
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out_MASK 0x1ffc0
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out__SHIFT 0x6
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst_MASK 0x80000
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst__SHIFT 0x13
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en_MASK 0x100000
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en__SHIFT 0x14
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel_MASK 0xf
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out_MASK 0x1ffc0
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out__SHIFT 0x6
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst_MASK 0x80000
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst__SHIFT 0x13
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en_MASK 0x100000
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en__SHIFT 0x14
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel_MASK 0xf
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out_MASK 0x1ffc0
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out__SHIFT 0x6
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst_MASK 0x80000
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst__SHIFT 0x13
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en_MASK 0x100000
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en__SHIFT 0x14
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel_MASK 0xf
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel__SHIFT 0x0
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out_MASK 0x1ffc0
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out__SHIFT 0x6
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst_MASK 0x80000
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst__SHIFT 0x13
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en_MASK 0x100000
+#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en__SHIFT 0x14
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr_MASK 0x7
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr__SHIFT 0x0
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en_MASK 0x18
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en__SHIFT 0x3
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x7
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x18
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x7
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x18
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x7
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x18
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x7
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x18
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr_MASK 0x7
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr__SHIFT 0x0
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en_MASK 0x18
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en__SHIFT 0x3
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr_MASK 0x7
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr__SHIFT 0x0
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en_MASK 0x18
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en__SHIFT 0x3
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr_MASK 0x7
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr__SHIFT 0x0
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en_MASK 0x18
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en__SHIFT 0x3
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr_MASK 0x7
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr__SHIFT 0x0
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en_MASK 0x18
+#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en__SHIFT 0x3
+#define PSX80_PHY0_TX_DFX_BROADCAST__obs_en_MASK 0x1
+#define PSX80_PHY0_TX_DFX_BROADCAST__obs_en__SHIFT 0x0
+#define PSX80_PHY0_TX_DFX_BROADCAST__obs_sel_MASK 0x4
+#define PSX80_PHY0_TX_DFX_BROADCAST__obs_sel__SHIFT 0x2
+#define PSX80_PHY0_TX_DFX_BROADCAST__felb_en_MASK 0x10
+#define PSX80_PHY0_TX_DFX_BROADCAST__felb_en__SHIFT 0x4
+#define PSX80_PHY0_TX_DFX_BROADCAST__prbs_en_MASK 0x100
+#define PSX80_PHY0_TX_DFX_BROADCAST__prbs_en__SHIFT 0x8
+#define PSX80_PHY0_TX_DFX_LANE0__obs_en_MASK 0x1
+#define PSX80_PHY0_TX_DFX_LANE0__obs_en__SHIFT 0x0
+#define PSX80_PHY0_TX_DFX_LANE0__obs_sel_MASK 0x4
+#define PSX80_PHY0_TX_DFX_LANE0__obs_sel__SHIFT 0x2
+#define PSX80_PHY0_TX_DFX_LANE0__felb_en_MASK 0x10
+#define PSX80_PHY0_TX_DFX_LANE0__felb_en__SHIFT 0x4
+#define PSX80_PHY0_TX_DFX_LANE0__prbs_en_MASK 0x100
+#define PSX80_PHY0_TX_DFX_LANE0__prbs_en__SHIFT 0x8
+#define PSX80_PHY0_TX_DFX_LANE1__obs_en_MASK 0x1
+#define PSX80_PHY0_TX_DFX_LANE1__obs_en__SHIFT 0x0
+#define PSX80_PHY0_TX_DFX_LANE1__obs_sel_MASK 0x4
+#define PSX80_PHY0_TX_DFX_LANE1__obs_sel__SHIFT 0x2
+#define PSX80_PHY0_TX_DFX_LANE1__felb_en_MASK 0x10
+#define PSX80_PHY0_TX_DFX_LANE1__felb_en__SHIFT 0x4
+#define PSX80_PHY0_TX_DFX_LANE1__prbs_en_MASK 0x100
+#define PSX80_PHY0_TX_DFX_LANE1__prbs_en__SHIFT 0x8
+#define PSX80_PHY0_TX_DFX_LANE2__obs_en_MASK 0x1
+#define PSX80_PHY0_TX_DFX_LANE2__obs_en__SHIFT 0x0
+#define PSX80_PHY0_TX_DFX_LANE2__obs_sel_MASK 0x4
+#define PSX80_PHY0_TX_DFX_LANE2__obs_sel__SHIFT 0x2
+#define PSX80_PHY0_TX_DFX_LANE2__felb_en_MASK 0x10
+#define PSX80_PHY0_TX_DFX_LANE2__felb_en__SHIFT 0x4
+#define PSX80_PHY0_TX_DFX_LANE2__prbs_en_MASK 0x100
+#define PSX80_PHY0_TX_DFX_LANE2__prbs_en__SHIFT 0x8
+#define PSX80_PHY0_TX_DFX_LANE3__obs_en_MASK 0x1
+#define PSX80_PHY0_TX_DFX_LANE3__obs_en__SHIFT 0x0
+#define PSX80_PHY0_TX_DFX_LANE3__obs_sel_MASK 0x4
+#define PSX80_PHY0_TX_DFX_LANE3__obs_sel__SHIFT 0x2
+#define PSX80_PHY0_TX_DFX_LANE3__felb_en_MASK 0x10
+#define PSX80_PHY0_TX_DFX_LANE3__felb_en__SHIFT 0x4
+#define PSX80_PHY0_TX_DFX_LANE3__prbs_en_MASK 0x100
+#define PSX80_PHY0_TX_DFX_LANE3__prbs_en__SHIFT 0x8
+#define PSX80_PHY0_TX_DFX_LANE4__obs_en_MASK 0x1
+#define PSX80_PHY0_TX_DFX_LANE4__obs_en__SHIFT 0x0
+#define PSX80_PHY0_TX_DFX_LANE4__obs_sel_MASK 0x4
+#define PSX80_PHY0_TX_DFX_LANE4__obs_sel__SHIFT 0x2
+#define PSX80_PHY0_TX_DFX_LANE4__felb_en_MASK 0x10
+#define PSX80_PHY0_TX_DFX_LANE4__felb_en__SHIFT 0x4
+#define PSX80_PHY0_TX_DFX_LANE4__prbs_en_MASK 0x100
+#define PSX80_PHY0_TX_DFX_LANE4__prbs_en__SHIFT 0x8
+#define PSX80_PHY0_TX_DFX_LANE5__obs_en_MASK 0x1
+#define PSX80_PHY0_TX_DFX_LANE5__obs_en__SHIFT 0x0
+#define PSX80_PHY0_TX_DFX_LANE5__obs_sel_MASK 0x4
+#define PSX80_PHY0_TX_DFX_LANE5__obs_sel__SHIFT 0x2
+#define PSX80_PHY0_TX_DFX_LANE5__felb_en_MASK 0x10
+#define PSX80_PHY0_TX_DFX_LANE5__felb_en__SHIFT 0x4
+#define PSX80_PHY0_TX_DFX_LANE5__prbs_en_MASK 0x100
+#define PSX80_PHY0_TX_DFX_LANE5__prbs_en__SHIFT 0x8
+#define PSX80_PHY0_TX_DFX_LANE6__obs_en_MASK 0x1
+#define PSX80_PHY0_TX_DFX_LANE6__obs_en__SHIFT 0x0
+#define PSX80_PHY0_TX_DFX_LANE6__obs_sel_MASK 0x4
+#define PSX80_PHY0_TX_DFX_LANE6__obs_sel__SHIFT 0x2
+#define PSX80_PHY0_TX_DFX_LANE6__felb_en_MASK 0x10
+#define PSX80_PHY0_TX_DFX_LANE6__felb_en__SHIFT 0x4
+#define PSX80_PHY0_TX_DFX_LANE6__prbs_en_MASK 0x100
+#define PSX80_PHY0_TX_DFX_LANE6__prbs_en__SHIFT 0x8
+#define PSX80_PHY0_TX_DFX_LANE7__obs_en_MASK 0x1
+#define PSX80_PHY0_TX_DFX_LANE7__obs_en__SHIFT 0x0
+#define PSX80_PHY0_TX_DFX_LANE7__obs_sel_MASK 0x4
+#define PSX80_PHY0_TX_DFX_LANE7__obs_sel__SHIFT 0x2
+#define PSX80_PHY0_TX_DFX_LANE7__felb_en_MASK 0x10
+#define PSX80_PHY0_TX_DFX_LANE7__felb_en__SHIFT 0x4
+#define PSX80_PHY0_TX_DFX_LANE7__prbs_en_MASK 0x100
+#define PSX80_PHY0_TX_DFX_LANE7__prbs_en__SHIFT 0x8
+#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1_MASK 0xff
+#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1__SHIFT 0x0
+#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0_MASK 0x3f00
+#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0__SHIFT 0x8
+#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1_MASK 0xff0000
+#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1__SHIFT 0x10
+#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1_MASK 0xff
+#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1__SHIFT 0x0
+#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0_MASK 0x3f00
+#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0__SHIFT 0x8
+#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1_MASK 0xff0000
+#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1__SHIFT 0x10
+#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1_MASK 0xff
+#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1__SHIFT 0x0
+#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0_MASK 0x3f00
+#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0__SHIFT 0x8
+#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1_MASK 0xff0000
+#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1__SHIFT 0x10
+#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1_MASK 0xff
+#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1__SHIFT 0x0
+#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0_MASK 0x3f00
+#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0__SHIFT 0x8
+#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1_MASK 0xff0000
+#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1__SHIFT 0x10
+#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1_MASK 0xff
+#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1__SHIFT 0x0
+#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0_MASK 0x3f00
+#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0__SHIFT 0x8
+#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1_MASK 0xff0000
+#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1__SHIFT 0x10
+#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1_MASK 0xff
+#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1__SHIFT 0x0
+#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0_MASK 0x3f00
+#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0__SHIFT 0x8
+#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1_MASK 0xff0000
+#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1__SHIFT 0x10
+#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1_MASK 0xff
+#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1__SHIFT 0x0
+#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0_MASK 0x3f00
+#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0__SHIFT 0x8
+#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1_MASK 0xff0000
+#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1__SHIFT 0x10
+#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1_MASK 0xff
+#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1__SHIFT 0x0
+#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0_MASK 0x3f00
+#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0__SHIFT 0x8
+#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1_MASK 0xff0000
+#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1__SHIFT 0x10
+#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1_MASK 0xff
+#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1__SHIFT 0x0
+#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0_MASK 0x3f00
+#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0__SHIFT 0x8
+#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1_MASK 0xff0000
+#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1__SHIFT 0x10
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel_MASK 0x7
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel__SHIFT 0x0
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel_MASK 0x8
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel__SHIFT 0x3
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel_MASK 0x7
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel__SHIFT 0x0
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel_MASK 0x8
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel__SHIFT 0x3
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel_MASK 0x7
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel__SHIFT 0x0
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel_MASK 0x8
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel__SHIFT 0x3
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel_MASK 0x7
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel__SHIFT 0x0
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel_MASK 0x8
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel__SHIFT 0x3
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel_MASK 0x7
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel__SHIFT 0x0
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel_MASK 0x8
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel__SHIFT 0x3
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel_MASK 0x7
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel__SHIFT 0x0
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel_MASK 0x8
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel__SHIFT 0x3
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel_MASK 0x7
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel__SHIFT 0x0
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel_MASK 0x8
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel__SHIFT 0x3
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel_MASK 0x7
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel__SHIFT 0x0
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel_MASK 0x8
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel__SHIFT 0x3
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel_MASK 0x7
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel__SHIFT 0x0
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel_MASK 0x8
+#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel__SHIFT 0x3
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary_MASK 0x1f
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary__SHIFT 0x0
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid_MASK 0x40
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid__SHIFT 0x6
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated_MASK 0x100
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated__SHIFT 0x8
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error_MASK 0x400
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error__SHIFT 0xa
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done_MASK 0x1000
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done__SHIFT 0xc
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated_MASK 0x7f0000
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated__SHIFT 0x10
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary_MASK 0x1f
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary__SHIFT 0x0
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid_MASK 0x40
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid__SHIFT 0x6
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated_MASK 0x100
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated__SHIFT 0x8
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error_MASK 0x400
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error__SHIFT 0xa
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done_MASK 0x1000
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done__SHIFT 0xc
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated_MASK 0x7f0000
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated__SHIFT 0x10
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary_MASK 0x1f
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary__SHIFT 0x0
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid_MASK 0x40
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid__SHIFT 0x6
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated_MASK 0x100
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated__SHIFT 0x8
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error_MASK 0x400
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error__SHIFT 0xa
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done_MASK 0x1000
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done__SHIFT 0xc
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated_MASK 0x7f0000
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated__SHIFT 0x10
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary_MASK 0x1f
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary__SHIFT 0x0
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid_MASK 0x40
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid__SHIFT 0x6
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated_MASK 0x100
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated__SHIFT 0x8
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error_MASK 0x400
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error__SHIFT 0xa
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done_MASK 0x1000
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done__SHIFT 0xc
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated_MASK 0x7f0000
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated__SHIFT 0x10
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary_MASK 0x1f
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary__SHIFT 0x0
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid_MASK 0x40
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid__SHIFT 0x6
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated_MASK 0x100
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated__SHIFT 0x8
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error_MASK 0x400
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error__SHIFT 0xa
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done_MASK 0x1000
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done__SHIFT 0xc
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated_MASK 0x7f0000
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated__SHIFT 0x10
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary_MASK 0x1f
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary__SHIFT 0x0
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid_MASK 0x40
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid__SHIFT 0x6
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated_MASK 0x100
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated__SHIFT 0x8
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error_MASK 0x400
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error__SHIFT 0xa
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done_MASK 0x1000
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done__SHIFT 0xc
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated_MASK 0x7f0000
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated__SHIFT 0x10
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary_MASK 0x1f
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary__SHIFT 0x0
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid_MASK 0x40
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid__SHIFT 0x6
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated_MASK 0x100
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated__SHIFT 0x8
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error_MASK 0x400
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error__SHIFT 0xa
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done_MASK 0x1000
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done__SHIFT 0xc
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated_MASK 0x7f0000
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated__SHIFT 0x10
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary_MASK 0x1f
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary__SHIFT 0x0
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid_MASK 0x40
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid__SHIFT 0x6
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated_MASK 0x100
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated__SHIFT 0x8
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error_MASK 0x400
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error__SHIFT 0xa
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done_MASK 0x1000
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done__SHIFT 0xc
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated_MASK 0x7f0000
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated__SHIFT 0x10
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary_MASK 0x1f
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary__SHIFT 0x0
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid_MASK 0x40
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid__SHIFT 0x6
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated_MASK 0x100
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated__SHIFT 0x8
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error_MASK 0x400
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error__SHIFT 0xa
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done_MASK 0x1000
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done__SHIFT 0xc
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated_MASK 0x7f0000
+#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated__SHIFT 0x10
+#define PSX80_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response_MASK 0x800
+#define PSX80_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response__SHIFT 0xb
+#define PSX80_PHY0_TX_TXCNTRL_LANE0__rxdetect_response_MASK 0x800
+#define PSX80_PHY0_TX_TXCNTRL_LANE0__rxdetect_response__SHIFT 0xb
+#define PSX80_PHY0_TX_TXCNTRL_LANE1__rxdetect_response_MASK 0x800
+#define PSX80_PHY0_TX_TXCNTRL_LANE1__rxdetect_response__SHIFT 0xb
+#define PSX80_PHY0_TX_TXCNTRL_LANE2__rxdetect_response_MASK 0x800
+#define PSX80_PHY0_TX_TXCNTRL_LANE2__rxdetect_response__SHIFT 0xb
+#define PSX80_PHY0_TX_TXCNTRL_LANE3__rxdetect_response_MASK 0x800
+#define PSX80_PHY0_TX_TXCNTRL_LANE3__rxdetect_response__SHIFT 0xb
+#define PSX80_PHY0_TX_TXCNTRL_LANE4__rxdetect_response_MASK 0x800
+#define PSX80_PHY0_TX_TXCNTRL_LANE4__rxdetect_response__SHIFT 0xb
+#define PSX80_PHY0_TX_TXCNTRL_LANE5__rxdetect_response_MASK 0x800
+#define PSX80_PHY0_TX_TXCNTRL_LANE5__rxdetect_response__SHIFT 0xb
+#define PSX80_PHY0_TX_TXCNTRL_LANE6__rxdetect_response_MASK 0x800
+#define PSX80_PHY0_TX_TXCNTRL_LANE6__rxdetect_response__SHIFT 0xb
+#define PSX80_PHY0_TX_TXCNTRL_LANE7__rxdetect_response_MASK 0x800
+#define PSX80_PHY0_TX_TXCNTRL_LANE7__rxdetect_response__SHIFT 0xb
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en_MASK 0x1
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en__SHIFT 0x0
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed_MASK 0x6
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed__SHIFT 0x1
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2_MASK 0x8
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2__SHIFT 0x3
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode_MASK 0xe0
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode__SHIFT 0x5
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x1
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x0
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x6
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x1
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2_MASK 0x8
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2__SHIFT 0x3
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0xe0
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x1
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x0
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x6
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x1
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2_MASK 0x8
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2__SHIFT 0x3
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0xe0
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x1
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x0
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x6
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x1
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2_MASK 0x8
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2__SHIFT 0x3
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0xe0
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x1
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x0
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x6
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x1
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2_MASK 0x8
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2__SHIFT 0x3
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0xe0
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en_MASK 0x1
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en__SHIFT 0x0
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed_MASK 0x6
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed__SHIFT 0x1
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2_MASK 0x8
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2__SHIFT 0x3
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode_MASK 0xe0
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode__SHIFT 0x5
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en_MASK 0x1
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en__SHIFT 0x0
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed_MASK 0x6
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed__SHIFT 0x1
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2_MASK 0x8
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2__SHIFT 0x3
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode_MASK 0xe0
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode__SHIFT 0x5
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en_MASK 0x1
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en__SHIFT 0x0
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed_MASK 0x6
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed__SHIFT 0x1
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2_MASK 0x8
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2__SHIFT 0x3
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode_MASK 0xe0
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode__SHIFT 0x5
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en_MASK 0x1
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en__SHIFT 0x0
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed_MASK 0x6
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed__SHIFT 0x1
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2_MASK 0x8
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2__SHIFT 0x3
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode_MASK 0xe0
+#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode__SHIFT 0x5
+#define PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn_MASK 0x7
+#define PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn__SHIFT 0x0
+#define PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd_MASK 0x10
+#define PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd__SHIFT 0x4
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer_MASK 0x7
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT 0x0
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce_MASK 0x8
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT 0x3
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange_MASK 0xff
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange__SHIFT 0x0
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes_MASK 0x3c00
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes__SHIFT 0xa
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac_MASK 0x3fc000
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac__SHIFT 0xe
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer_MASK 0x3c00000
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer__SHIFT 0x16
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLock_MASK 0x4000000
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLock__SHIFT 0x1a
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect_MASK 0x10000000
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect__SHIFT 0x1c
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked_MASK 0x20000000
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked__SHIFT 0x1d
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer_MASK 0xc0000000
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer__SHIFT 0x1e
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl_MASK 0x7ff
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl__SHIFT 0x0
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp_MASK 0xfffff800
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp__SHIFT 0xb
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut_MASK 0x3ffff
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut__SHIFT 0x0
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo_MASK 0x40000
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo__SHIFT 0x12
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel_MASK 0xe00000
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT 0x15
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq_MASK 0x7f
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq__SHIFT 0x0
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd_MASK 0x80
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd__SHIFT 0x7
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn_MASK 0x100
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn__SHIFT 0x8
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd_MASK 0x200
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd__SHIFT 0x9
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate_MASK 0x400
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate__SHIFT 0xa
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd_MASK 0x800
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd__SHIFT 0xb
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn_MASK 0x1000
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn__SHIFT 0xc
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK 0x2000
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT 0xd
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn_MASK 0x10000
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn__SHIFT 0x10
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK 0x20000
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT 0x11
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate_MASK 0x1
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT 0x0
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal_MASK 0x1
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal__SHIFT 0x0
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal_MASK 0x2
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal__SHIFT 0x1
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal_MASK 0x4
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal__SHIFT 0x2
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone_MASK 0x8
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone__SHIFT 0x3
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext_MASK 0x10
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT 0x4
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail_MASK 0x60
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail__SHIFT 0x5
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn_MASK 0x3f00000
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn__SHIFT 0x14
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut_MASK 0x4000000
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut__SHIFT 0x1a
+#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid_MASK 0x1
+#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid__SHIFT 0x0
+#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj_MASK 0x1e
+#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj__SHIFT 0x1
+#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare_MASK 0xf00
+#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare__SHIFT 0x8
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv_MASK 0xffff
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv__SHIFT 0x0
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0_MASK 0xff
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0__SHIFT 0x0
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8_MASK 0xf00
+#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8__SHIFT 0x8
+#define PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn_MASK 0x7
+#define PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn__SHIFT 0x0
+#define PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd_MASK 0x10
+#define PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd__SHIFT 0x4
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer_MASK 0x7
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT 0x0
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce_MASK 0x8
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT 0x3
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange_MASK 0xff
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange__SHIFT 0x0
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin_MASK 0x700
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin__SHIFT 0x8
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes_MASK 0x3000
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes__SHIFT 0xc
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0_MASK 0x3c000
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0__SHIFT 0xe
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4_MASK 0x3c0000
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4__SHIFT 0x12
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer_MASK 0x3c00000
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer__SHIFT 0x16
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLock_MASK 0x4000000
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLock__SHIFT 0x1a
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect_MASK 0x10000000
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect__SHIFT 0x1c
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked_MASK 0x20000000
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked__SHIFT 0x1d
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer_MASK 0xc0000000
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer__SHIFT 0x1e
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl_MASK 0x7ff
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl__SHIFT 0x0
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp_MASK 0xfffff800
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp__SHIFT 0xb
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut_MASK 0x3ffff
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut__SHIFT 0x0
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo_MASK 0x40000
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo__SHIFT 0x12
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel_MASK 0xe00000
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT 0x15
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn_MASK 0x1000
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn__SHIFT 0xc
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK 0x2000
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT 0xd
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn_MASK 0x10000
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn__SHIFT 0x10
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK 0x20000
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT 0x11
+#define PSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI_MASK 0xff
+#define PSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI__SHIFT 0x0
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate_MASK 0x1
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT 0x0
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt_MASK 0x3800000
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt__SHIFT 0x17
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt_MASK 0x3fff
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt__SHIFT 0x0
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone_MASK 0x8000
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone__SHIFT 0xf
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext_MASK 0x10000
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT 0x10
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail_MASK 0xe0000
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail__SHIFT 0x11
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn_MASK 0x3f00000
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn__SHIFT 0x14
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut_MASK 0x4000000
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut__SHIFT 0x1a
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn_MASK 0x8000000
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn__SHIFT 0x1b
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal_MASK 0x20000000
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal__SHIFT 0x1d
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv_MASK 0xffff
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv__SHIFT 0x0
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0_MASK 0xff
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0__SHIFT 0x0
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8_MASK 0xf00
+#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8__SHIFT 0x8
+#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_valid_MASK 0x1
+#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
+#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel_MASK 0x6
+#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel__SHIFT 0x1
+#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable_MASK 0x8
+#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable__SHIFT 0x3
+#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12_MASK 0xf0
+#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12__SHIFT 0x4
+#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12_MASK 0x100
+#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12__SHIFT 0x8
+#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x600
+#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0x9
+#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x1800
+#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0xb
+#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time_MASK 0xc0000
+#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time__SHIFT 0x12
+#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_spare_MASK 0xfff00000
+#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_spare__SHIFT 0x14
+#define PSX81_PHY0_COM_COMMON_FUSE2__fuse2_valid_MASK 0x1
+#define PSX81_PHY0_COM_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
+#define PSX81_PHY0_COM_COMMON_FUSE2__fuse2_spare_MASK 0xfffffffe
+#define PSX81_PHY0_COM_COMMON_FUSE2__fuse2_spare__SHIFT 0x1
+#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_valid_MASK 0x1
+#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
+#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel_MASK 0xe
+#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel__SHIFT 0x1
+#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val_MASK 0x3f0
+#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val__SHIFT 0x4
+#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val_MASK 0xfc00
+#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val__SHIFT 0xa
+#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj_MASK 0xf0000
+#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj__SHIFT 0x10
+#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj_MASK 0xf00000
+#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj__SHIFT 0x14
+#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj_MASK 0xf000000
+#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj__SHIFT 0x18
+#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en_MASK 0x10000000
+#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en__SHIFT 0x1c
+#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_spare_MASK 0xe0000000
+#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
+#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0_MASK 0x1
+#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0__SHIFT 0x0
+#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal_MASK 0x2
+#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal__SHIFT 0x1
+#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel_MASK 0x4
+#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel__SHIFT 0x2
+#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code_MASK 0x3f0
+#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code__SHIFT 0x4
+#define PSX81_PHY0_COM_COMMON_DFX__nelb_en_MASK 0x1
+#define PSX81_PHY0_COM_COMMON_DFX__nelb_en__SHIFT 0x0
+#define PSX81_PHY0_COM_COMMON_DFX__prbs_seed_MASK 0x7fe
+#define PSX81_PHY0_COM_COMMON_DFX__prbs_seed__SHIFT 0x1
+#define PSX81_PHY0_COM_COMMON_DFX__force_cdr_en_MASK 0x800
+#define PSX81_PHY0_COM_COMMON_DFX__force_cdr_en__SHIFT 0xb
+#define PSX81_PHY0_COM_COMMON_DFX__ovrd_pll_on_MASK 0x2000
+#define PSX81_PHY0_COM_COMMON_DFX__ovrd_pll_on__SHIFT 0xd
+#define PSX81_PHY0_COM_COMMON_DFX__ovrd_clk_en_MASK 0x8000
+#define PSX81_PHY0_COM_COMMON_DFX__ovrd_clk_en__SHIFT 0xf
+#define PSX81_PHY0_COM_COMMON_DFX__dsm_sel_MASK 0x7e0000
+#define PSX81_PHY0_COM_COMMON_DFX__dsm_sel__SHIFT 0x11
+#define PSX81_PHY0_COM_COMMON_DFX__dsm_en_MASK 0xf000000
+#define PSX81_PHY0_COM_COMMON_DFX__dsm_en__SHIFT 0x18
+#define PSX81_PHY0_COM_COMMON_DFX__hold_rdy_response_MASK 0x20000000
+#define PSX81_PHY0_COM_COMMON_DFX__hold_rdy_response__SHIFT 0x1d
+#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0xff
+#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
+#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0xff00
+#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
+#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0xff0000
+#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
+#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xff000000
+#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
+#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1_MASK 0xff
+#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1__SHIFT 0x0
+#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2_MASK 0xff00
+#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2__SHIFT 0x8
+#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3_MASK 0xff0000
+#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3__SHIFT 0x10
+#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4_MASK 0xff000000
+#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4__SHIFT 0x18
+#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1_MASK 0xff
+#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1__SHIFT 0x0
+#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2_MASK 0xff00
+#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2__SHIFT 0x8
+#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3_MASK 0xff0000
+#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3__SHIFT 0x10
+#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4_MASK 0xff000000
+#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4__SHIFT 0x18
+#define PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay_MASK 0xf
+#define PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
+#define PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask_MASK 0x3f0
+#define PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber_MASK 0x7
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber__SHIFT 0x0
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time_MASK 0xf0
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time__SHIFT 0x4
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time_MASK 0x1e00
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time__SHIFT 0x9
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time_MASK 0x3c000
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time__SHIFT 0xe
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time_MASK 0x780000
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time__SHIFT 0x13
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time_MASK 0x1e000000
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time__SHIFT 0x19
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel_MASK 0xe0000000
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel__SHIFT 0x1d
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain_MASK 0x3
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain__SHIFT 0x0
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain_MASK 0x78
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain__SHIFT 0x3
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain_MASK 0xf00
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain__SHIFT 0x8
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain_MASK 0x1e000
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain__SHIFT 0xd
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain_MASK 0x3c0000
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain__SHIFT 0x12
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt_MASK 0x3800000
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt__SHIFT 0x17
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt_MASK 0x38000000
+#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt__SHIFT 0x1b
+#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val_MASK 0x1f
+#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val__SHIFT 0x0
+#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val_MASK 0x7c0
+#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val__SHIFT 0x6
+#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val_MASK 0xe000
+#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val__SHIFT 0xd
+#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val_MASK 0xe0000
+#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val__SHIFT 0x11
+#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val_MASK 0xfc00000
+#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val__SHIFT 0x16
+#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val_MASK 0x3f
+#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val__SHIFT 0x0
+#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val_MASK 0xf00
+#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val__SHIFT 0x8
+#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val_MASK 0x1e000
+#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val__SHIFT 0xd
+#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val_MASK 0x1ff
+#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val__SHIFT 0x0
+#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val_MASK 0xff800
+#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val__SHIFT 0xb
+#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val_MASK 0x7fc00000
+#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val__SHIFT 0x16
+#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val_MASK 0x3f
+#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val__SHIFT 0x0
+#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val_MASK 0x1f80
+#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val__SHIFT 0x7
+#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode_MASK 0x7
+#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode__SHIFT 0x0
+#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec_MASK 0x1c0
+#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec__SHIFT 0x6
+#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst_MASK 0x3fffc00
+#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst__SHIFT 0xa
+#define PSX81_PHY0_COM_COMMON_LNCNTRL__clkgate_dis_MASK 0x20
+#define PSX81_PHY0_COM_COMMON_LNCNTRL__clkgate_dis__SHIFT 0x5
+#define PSX81_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel_MASK 0xc0
+#define PSX81_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel__SHIFT 0x6
+#define PSX81_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel_MASK 0x300
+#define PSX81_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel__SHIFT 0x8
+#define PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel_MASK 0x1f
+#define PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel__SHIFT 0x0
+#define PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en_MASK 0x40
+#define PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en__SHIFT 0x6
+#define PSX81_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel_MASK 0x70
+#define PSX81_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel__SHIFT 0x4
+#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3_MASK 0x1
+#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3__SHIFT 0x0
+#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3_MASK 0x780
+#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3__SHIFT 0x7
+#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val_MASK 0x7e000
+#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val__SHIFT 0xd
+#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en_MASK 0x1
+#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en__SHIFT 0x0
+#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12_MASK 0x3c
+#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12__SHIFT 0x2
+#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3_MASK 0x780
+#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3__SHIFT 0x7
+#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val_MASK 0x1ff000
+#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val__SHIFT 0xc
+#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit_MASK 0xc00000
+#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit__SHIFT 0x16
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr_MASK 0x7
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr__SHIFT 0x0
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en_MASK 0x18
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en__SHIFT 0x3
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en_MASK 0x20
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en__SHIFT 0x5
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr_MASK 0x7
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr__SHIFT 0x0
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en_MASK 0x18
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en__SHIFT 0x3
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en_MASK 0x20
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en__SHIFT 0x5
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr_MASK 0x7
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr__SHIFT 0x0
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en_MASK 0x18
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en__SHIFT 0x3
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en_MASK 0x20
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en__SHIFT 0x5
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr_MASK 0x7
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr__SHIFT 0x0
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en_MASK 0x18
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en__SHIFT 0x3
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en_MASK 0x20
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en__SHIFT 0x5
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr_MASK 0x7
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr__SHIFT 0x0
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en_MASK 0x18
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en__SHIFT 0x3
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en_MASK 0x20
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en__SHIFT 0x5
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr_MASK 0x7
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr__SHIFT 0x0
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en_MASK 0x18
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en__SHIFT 0x3
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en_MASK 0x20
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en__SHIFT 0x5
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr_MASK 0x7
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr__SHIFT 0x0
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en_MASK 0x18
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en__SHIFT 0x3
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en_MASK 0x20
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en__SHIFT 0x5
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr_MASK 0x7
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr__SHIFT 0x0
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en_MASK 0x18
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en__SHIFT 0x3
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en_MASK 0x20
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en__SHIFT 0x5
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr_MASK 0x7
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr__SHIFT 0x0
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en_MASK 0x18
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en__SHIFT 0x3
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en_MASK 0x20
+#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en__SHIFT 0x5
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en_MASK 0x1
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en__SHIFT 0x0
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed_MASK 0x6
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed__SHIFT 0x1
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2_MASK 0x8
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2__SHIFT 0x3
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en_MASK 0x1
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en__SHIFT 0x0
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed_MASK 0x6
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed__SHIFT 0x1
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2_MASK 0x8
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2__SHIFT 0x3
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en_MASK 0x1
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en__SHIFT 0x0
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed_MASK 0x6
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed__SHIFT 0x1
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2_MASK 0x8
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2__SHIFT 0x3
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en_MASK 0x1
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en__SHIFT 0x0
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed_MASK 0x6
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed__SHIFT 0x1
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2_MASK 0x8
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2__SHIFT 0x3
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en_MASK 0x1
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en__SHIFT 0x0
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed_MASK 0x6
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed__SHIFT 0x1
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2_MASK 0x8
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2__SHIFT 0x3
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en_MASK 0x1
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en__SHIFT 0x0
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed_MASK 0x6
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed__SHIFT 0x1
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2_MASK 0x8
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2__SHIFT 0x3
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en_MASK 0x1
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en__SHIFT 0x0
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed_MASK 0x6
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed__SHIFT 0x1
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2_MASK 0x8
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2__SHIFT 0x3
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en_MASK 0x1
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en__SHIFT 0x0
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed_MASK 0x6
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed__SHIFT 0x1
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2_MASK 0x8
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2__SHIFT 0x3
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en_MASK 0x1
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en__SHIFT 0x0
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed_MASK 0x6
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed__SHIFT 0x1
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2_MASK 0x8
+#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2__SHIFT 0x3
+#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis_MASK 0x1
+#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis__SHIFT 0x0
+#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc_MASK 0x1fe
+#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc__SHIFT 0x1
+#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode_MASK 0x1800
+#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode__SHIFT 0xb
+#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri_MASK 0x2000
+#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri__SHIFT 0xd
+#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity_MASK 0x4000
+#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity__SHIFT 0xe
+#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign_MASK 0x8000
+#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign__SHIFT 0xf
+#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis_MASK 0x1
+#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis__SHIFT 0x0
+#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc_MASK 0x1fe
+#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc__SHIFT 0x1
+#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_term_mode_MASK 0x1800
+#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_term_mode__SHIFT 0xb
+#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri_MASK 0x2000
+#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri__SHIFT 0xd
+#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity_MASK 0x4000
+#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity__SHIFT 0xe
+#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign_MASK 0x8000
+#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign__SHIFT 0xf
+#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis_MASK 0x1
+#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis__SHIFT 0x0
+#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc_MASK 0x1fe
+#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc__SHIFT 0x1
+#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_term_mode_MASK 0x1800
+#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_term_mode__SHIFT 0xb
+#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri_MASK 0x2000
+#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri__SHIFT 0xd
+#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity_MASK 0x4000
+#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity__SHIFT 0xe
+#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign_MASK 0x8000
+#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign__SHIFT 0xf
+#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis_MASK 0x1
+#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis__SHIFT 0x0
+#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc_MASK 0x1fe
+#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc__SHIFT 0x1
+#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_term_mode_MASK 0x1800
+#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_term_mode__SHIFT 0xb
+#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri_MASK 0x2000
+#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri__SHIFT 0xd
+#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity_MASK 0x4000
+#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity__SHIFT 0xe
+#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign_MASK 0x8000
+#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign__SHIFT 0xf
+#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis_MASK 0x1
+#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis__SHIFT 0x0
+#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc_MASK 0x1fe
+#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc__SHIFT 0x1
+#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_term_mode_MASK 0x1800
+#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_term_mode__SHIFT 0xb
+#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri_MASK 0x2000
+#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri__SHIFT 0xd
+#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity_MASK 0x4000
+#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity__SHIFT 0xe
+#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign_MASK 0x8000
+#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign__SHIFT 0xf
+#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis_MASK 0x1
+#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis__SHIFT 0x0
+#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc_MASK 0x1fe
+#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc__SHIFT 0x1
+#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_term_mode_MASK 0x1800
+#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_term_mode__SHIFT 0xb
+#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri_MASK 0x2000
+#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri__SHIFT 0xd
+#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity_MASK 0x4000
+#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity__SHIFT 0xe
+#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign_MASK 0x8000
+#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign__SHIFT 0xf
+#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis_MASK 0x1
+#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis__SHIFT 0x0
+#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc_MASK 0x1fe
+#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc__SHIFT 0x1
+#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_term_mode_MASK 0x1800
+#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_term_mode__SHIFT 0xb
+#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri_MASK 0x2000
+#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri__SHIFT 0xd
+#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity_MASK 0x4000
+#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity__SHIFT 0xe
+#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign_MASK 0x8000
+#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign__SHIFT 0xf
+#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis_MASK 0x1
+#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis__SHIFT 0x0
+#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc_MASK 0x1fe
+#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc__SHIFT 0x1
+#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_term_mode_MASK 0x1800
+#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_term_mode__SHIFT 0xb
+#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri_MASK 0x2000
+#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri__SHIFT 0xd
+#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity_MASK 0x4000
+#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity__SHIFT 0xe
+#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign_MASK 0x8000
+#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign__SHIFT 0xf
+#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis_MASK 0x1
+#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis__SHIFT 0x0
+#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc_MASK 0x1fe
+#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc__SHIFT 0x1
+#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_term_mode_MASK 0x1800
+#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_term_mode__SHIFT 0xb
+#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri_MASK 0x2000
+#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri__SHIFT 0xd
+#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity_MASK 0x4000
+#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity__SHIFT 0xe
+#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign_MASK 0x8000
+#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign__SHIFT 0xf
+#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel_MASK 0x7
+#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel__SHIFT 0x0
+#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel_MASK 0x10
+#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel__SHIFT 0x4
+#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en_MASK 0x20
+#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en__SHIFT 0x5
+#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl_MASK 0x80
+#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl__SHIFT 0x7
+#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel_MASK 0x7
+#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel__SHIFT 0x0
+#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel_MASK 0x10
+#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel__SHIFT 0x4
+#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en_MASK 0x20
+#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en__SHIFT 0x5
+#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl_MASK 0x80
+#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl__SHIFT 0x7
+#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel_MASK 0x7
+#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel__SHIFT 0x0
+#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel_MASK 0x10
+#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel__SHIFT 0x4
+#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en_MASK 0x20
+#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en__SHIFT 0x5
+#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl_MASK 0x80
+#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl__SHIFT 0x7
+#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel_MASK 0x7
+#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel__SHIFT 0x0
+#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel_MASK 0x10
+#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel__SHIFT 0x4
+#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en_MASK 0x20
+#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en__SHIFT 0x5
+#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl_MASK 0x80
+#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl__SHIFT 0x7
+#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel_MASK 0x7
+#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel__SHIFT 0x0
+#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel_MASK 0x10
+#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel__SHIFT 0x4
+#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en_MASK 0x20
+#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en__SHIFT 0x5
+#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl_MASK 0x80
+#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl__SHIFT 0x7
+#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel_MASK 0x7
+#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel__SHIFT 0x0
+#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel_MASK 0x10
+#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel__SHIFT 0x4
+#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en_MASK 0x20
+#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en__SHIFT 0x5
+#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl_MASK 0x80
+#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl__SHIFT 0x7
+#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel_MASK 0x7
+#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel__SHIFT 0x0
+#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel_MASK 0x10
+#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel__SHIFT 0x4
+#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en_MASK 0x20
+#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en__SHIFT 0x5
+#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl_MASK 0x80
+#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl__SHIFT 0x7
+#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel_MASK 0x7
+#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel__SHIFT 0x0
+#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel_MASK 0x10
+#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel__SHIFT 0x4
+#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en_MASK 0x20
+#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en__SHIFT 0x5
+#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl_MASK 0x80
+#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl__SHIFT 0x7
+#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel_MASK 0x7
+#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel__SHIFT 0x0
+#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel_MASK 0x10
+#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel__SHIFT 0x4
+#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en_MASK 0x20
+#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en__SHIFT 0x5
+#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl_MASK 0x80
+#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl__SHIFT 0x7
+#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr_MASK 0x1
+#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr__SHIFT 0x0
+#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err_MASK 0x2
+#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err__SHIFT 0x1
+#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force_MASK 0x10
+#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force__SHIFT 0x4
+#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en_MASK 0x20
+#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en__SHIFT 0x5
+#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap_MASK 0x40
+#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap__SHIFT 0x6
+#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res_MASK 0x80
+#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res__SHIFT 0x7
+#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate_MASK 0x100
+#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate__SHIFT 0x8
+#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out_MASK 0x400
+#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out__SHIFT 0xa
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr_MASK 0x1
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr__SHIFT 0x0
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_err_MASK 0x2
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_err__SHIFT 0x1
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force_MASK 0x10
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force__SHIFT 0x4
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en_MASK 0x20
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en__SHIFT 0x5
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap_MASK 0x40
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap__SHIFT 0x6
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res_MASK 0x80
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res__SHIFT 0x7
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate_MASK 0x100
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate__SHIFT 0x8
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out_MASK 0x400
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out__SHIFT 0xa
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr_MASK 0x1
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr__SHIFT 0x0
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_err_MASK 0x2
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_err__SHIFT 0x1
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force_MASK 0x10
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force__SHIFT 0x4
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en_MASK 0x20
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en__SHIFT 0x5
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap_MASK 0x40
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap__SHIFT 0x6
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res_MASK 0x80
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res__SHIFT 0x7
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate_MASK 0x100
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate__SHIFT 0x8
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out_MASK 0x400
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out__SHIFT 0xa
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr_MASK 0x1
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr__SHIFT 0x0
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_err_MASK 0x2
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_err__SHIFT 0x1
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force_MASK 0x10
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force__SHIFT 0x4
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en_MASK 0x20
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en__SHIFT 0x5
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap_MASK 0x40
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap__SHIFT 0x6
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res_MASK 0x80
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res__SHIFT 0x7
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate_MASK 0x100
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate__SHIFT 0x8
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out_MASK 0x400
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out__SHIFT 0xa
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr_MASK 0x1
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr__SHIFT 0x0
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_err_MASK 0x2
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_err__SHIFT 0x1
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force_MASK 0x10
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force__SHIFT 0x4
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en_MASK 0x20
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en__SHIFT 0x5
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap_MASK 0x40
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap__SHIFT 0x6
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res_MASK 0x80
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res__SHIFT 0x7
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate_MASK 0x100
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate__SHIFT 0x8
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out_MASK 0x400
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out__SHIFT 0xa
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr_MASK 0x1
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr__SHIFT 0x0
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_err_MASK 0x2
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_err__SHIFT 0x1
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force_MASK 0x10
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force__SHIFT 0x4
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en_MASK 0x20
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en__SHIFT 0x5
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap_MASK 0x40
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap__SHIFT 0x6
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res_MASK 0x80
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res__SHIFT 0x7
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate_MASK 0x100
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate__SHIFT 0x8
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out_MASK 0x400
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out__SHIFT 0xa
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr_MASK 0x1
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr__SHIFT 0x0
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_err_MASK 0x2
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_err__SHIFT 0x1
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force_MASK 0x10
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force__SHIFT 0x4
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en_MASK 0x20
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en__SHIFT 0x5
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap_MASK 0x40
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap__SHIFT 0x6
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res_MASK 0x80
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res__SHIFT 0x7
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate_MASK 0x100
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate__SHIFT 0x8
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out_MASK 0x400
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out__SHIFT 0xa
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr_MASK 0x1
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr__SHIFT 0x0
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_err_MASK 0x2
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_err__SHIFT 0x1
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force_MASK 0x10
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force__SHIFT 0x4
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en_MASK 0x20
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en__SHIFT 0x5
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap_MASK 0x40
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap__SHIFT 0x6
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res_MASK 0x80
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res__SHIFT 0x7
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate_MASK 0x100
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate__SHIFT 0x8
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out_MASK 0x400
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out__SHIFT 0xa
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr_MASK 0x1
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr__SHIFT 0x0
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_err_MASK 0x2
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_err__SHIFT 0x1
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force_MASK 0x10
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force__SHIFT 0x4
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en_MASK 0x20
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en__SHIFT 0x5
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap_MASK 0x40
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap__SHIFT 0x6
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res_MASK 0x80
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res__SHIFT 0x7
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate_MASK 0x100
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate__SHIFT 0x8
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out_MASK 0x400
+#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out__SHIFT 0xa
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei_MASK 0x1
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei__SHIFT 0x0
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out_MASK 0x2
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out__SHIFT 0x1
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds_MASK 0x4
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds__SHIFT 0x2
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj_MASK 0x1f8
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj__SHIFT 0x3
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en_MASK 0x400
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en__SHIFT 0xa
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei_MASK 0x1
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei__SHIFT 0x0
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out_MASK 0x2
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out__SHIFT 0x1
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds_MASK 0x4
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds__SHIFT 0x2
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj_MASK 0x1f8
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj__SHIFT 0x3
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en_MASK 0x400
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en__SHIFT 0xa
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei_MASK 0x1
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei__SHIFT 0x0
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out_MASK 0x2
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out__SHIFT 0x1
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds_MASK 0x4
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds__SHIFT 0x2
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj_MASK 0x1f8
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj__SHIFT 0x3
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en_MASK 0x400
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en__SHIFT 0xa
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei_MASK 0x1
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei__SHIFT 0x0
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out_MASK 0x2
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out__SHIFT 0x1
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds_MASK 0x4
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds__SHIFT 0x2
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj_MASK 0x1f8
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj__SHIFT 0x3
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en_MASK 0x400
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en__SHIFT 0xa
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei_MASK 0x1
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei__SHIFT 0x0
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out_MASK 0x2
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out__SHIFT 0x1
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds_MASK 0x4
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds__SHIFT 0x2
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj_MASK 0x1f8
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj__SHIFT 0x3
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en_MASK 0x400
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en__SHIFT 0xa
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei_MASK 0x1
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei__SHIFT 0x0
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out_MASK 0x2
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out__SHIFT 0x1
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds_MASK 0x4
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds__SHIFT 0x2
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj_MASK 0x1f8
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj__SHIFT 0x3
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en_MASK 0x400
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en__SHIFT 0xa
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei_MASK 0x1
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei__SHIFT 0x0
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out_MASK 0x2
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out__SHIFT 0x1
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds_MASK 0x4
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds__SHIFT 0x2
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj_MASK 0x1f8
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj__SHIFT 0x3
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en_MASK 0x400
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en__SHIFT 0xa
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei_MASK 0x1
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei__SHIFT 0x0
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out_MASK 0x2
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out__SHIFT 0x1
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds_MASK 0x4
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds__SHIFT 0x2
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj_MASK 0x1f8
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj__SHIFT 0x3
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en_MASK 0x400
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en__SHIFT 0xa
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei_MASK 0x1
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei__SHIFT 0x0
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out_MASK 0x2
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out__SHIFT 0x1
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds_MASK 0x4
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds__SHIFT 0x2
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj_MASK 0x1f8
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj__SHIFT 0x3
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en_MASK 0x400
+#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en__SHIFT 0xa
+#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode_MASK 0x3ff
+#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel_MASK 0xe000
+#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel__SHIFT 0xd
+#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off_MASK 0x20000
+#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off__SHIFT 0x11
+#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel_MASK 0x180000
+#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
+#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode_MASK 0x3ff
+#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel_MASK 0xe000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel__SHIFT 0xd
+#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off_MASK 0x20000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off__SHIFT 0x11
+#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel_MASK 0x180000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
+#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode_MASK 0x3ff
+#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel_MASK 0xe000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel__SHIFT 0xd
+#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off_MASK 0x20000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off__SHIFT 0x11
+#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel_MASK 0x180000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
+#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode_MASK 0x3ff
+#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel_MASK 0xe000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel__SHIFT 0xd
+#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off_MASK 0x20000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off__SHIFT 0x11
+#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel_MASK 0x180000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
+#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode_MASK 0x3ff
+#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel_MASK 0xe000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel__SHIFT 0xd
+#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off_MASK 0x20000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off__SHIFT 0x11
+#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel_MASK 0x180000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
+#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode_MASK 0x3ff
+#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel_MASK 0xe000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel__SHIFT 0xd
+#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off_MASK 0x20000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off__SHIFT 0x11
+#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel_MASK 0x180000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
+#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode_MASK 0x3ff
+#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel_MASK 0xe000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel__SHIFT 0xd
+#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off_MASK 0x20000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off__SHIFT 0x11
+#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel_MASK 0x180000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
+#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode_MASK 0x3ff
+#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel_MASK 0xe000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel__SHIFT 0xd
+#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off_MASK 0x20000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off__SHIFT 0x11
+#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel_MASK 0x180000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
+#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode_MASK 0x3ff
+#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel_MASK 0xe000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel__SHIFT 0xd
+#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off_MASK 0x20000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off__SHIFT 0x11
+#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel_MASK 0x180000
+#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
+#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid_MASK 0x1
+#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid__SHIFT 0x0
+#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom_MASK 0x1fe
+#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom__SHIFT 0x1
+#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom_MASK 0x800
+#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom__SHIFT 0xb
+#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom_MASK 0x1000
+#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom__SHIFT 0xc
+#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk_MASK 0x2000
+#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk__SHIFT 0xd
+#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn_MASK 0x4000
+#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn__SHIFT 0xe
+#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode_MASK 0x10000
+#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode__SHIFT 0x10
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid_MASK 0x1
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid__SHIFT 0x0
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom_MASK 0x1fe
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom__SHIFT 0x1
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__enable_fom_MASK 0x800
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__enable_fom__SHIFT 0xb
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_fom_MASK 0x1000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_fom__SHIFT 0xc
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trk_MASK 0x2000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trk__SHIFT 0xd
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trn_MASK 0x4000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trn__SHIFT 0xe
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__response_mode_MASK 0x10000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__response_mode__SHIFT 0x10
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid_MASK 0x1
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid__SHIFT 0x0
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom_MASK 0x1fe
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom__SHIFT 0x1
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__enable_fom_MASK 0x800
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__enable_fom__SHIFT 0xb
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_fom_MASK 0x1000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_fom__SHIFT 0xc
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trk_MASK 0x2000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trk__SHIFT 0xd
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trn_MASK 0x4000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trn__SHIFT 0xe
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__response_mode_MASK 0x10000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__response_mode__SHIFT 0x10
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid_MASK 0x1
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid__SHIFT 0x0
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom_MASK 0x1fe
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom__SHIFT 0x1
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__enable_fom_MASK 0x800
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__enable_fom__SHIFT 0xb
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_fom_MASK 0x1000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_fom__SHIFT 0xc
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trk_MASK 0x2000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trk__SHIFT 0xd
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trn_MASK 0x4000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trn__SHIFT 0xe
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__response_mode_MASK 0x10000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__response_mode__SHIFT 0x10
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid_MASK 0x1
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid__SHIFT 0x0
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom_MASK 0x1fe
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom__SHIFT 0x1
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__enable_fom_MASK 0x800
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__enable_fom__SHIFT 0xb
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_fom_MASK 0x1000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_fom__SHIFT 0xc
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trk_MASK 0x2000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trk__SHIFT 0xd
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trn_MASK 0x4000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trn__SHIFT 0xe
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__response_mode_MASK 0x10000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__response_mode__SHIFT 0x10
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid_MASK 0x1
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid__SHIFT 0x0
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom_MASK 0x1fe
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom__SHIFT 0x1
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__enable_fom_MASK 0x800
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__enable_fom__SHIFT 0xb
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_fom_MASK 0x1000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_fom__SHIFT 0xc
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trk_MASK 0x2000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trk__SHIFT 0xd
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trn_MASK 0x4000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trn__SHIFT 0xe
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__response_mode_MASK 0x10000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__response_mode__SHIFT 0x10
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid_MASK 0x1
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid__SHIFT 0x0
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom_MASK 0x1fe
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom__SHIFT 0x1
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__enable_fom_MASK 0x800
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__enable_fom__SHIFT 0xb
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_fom_MASK 0x1000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_fom__SHIFT 0xc
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trk_MASK 0x2000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trk__SHIFT 0xd
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trn_MASK 0x4000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trn__SHIFT 0xe
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__response_mode_MASK 0x10000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__response_mode__SHIFT 0x10
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid_MASK 0x1
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid__SHIFT 0x0
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom_MASK 0x1fe
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom__SHIFT 0x1
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__enable_fom_MASK 0x800
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__enable_fom__SHIFT 0xb
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_fom_MASK 0x1000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_fom__SHIFT 0xc
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trk_MASK 0x2000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trk__SHIFT 0xd
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trn_MASK 0x4000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trn__SHIFT 0xe
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__response_mode_MASK 0x10000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__response_mode__SHIFT 0x10
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid_MASK 0x1
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid__SHIFT 0x0
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom_MASK 0x1fe
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom__SHIFT 0x1
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__enable_fom_MASK 0x800
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__enable_fom__SHIFT 0xb
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_fom_MASK 0x1000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_fom__SHIFT 0xc
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trk_MASK 0x2000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trk__SHIFT 0xd
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trn_MASK 0x4000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trn__SHIFT 0xe
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__response_mode_MASK 0x10000
+#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__response_mode__SHIFT 0x10
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
+#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
+#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en_MASK 0x1
+#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en__SHIFT 0x0
+#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en_MASK 0x2
+#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en__SHIFT 0x1
+#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en_MASK 0x4
+#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en__SHIFT 0x2
+#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
+#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
+#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
+#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
+#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
+#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
+#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en_MASK 0x40
+#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en__SHIFT 0x6
+#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en_MASK 0x80
+#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en__SHIFT 0x7
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en_MASK 0x1
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en__SHIFT 0x0
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en_MASK 0x2
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en__SHIFT 0x1
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en_MASK 0x4
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en__SHIFT 0x2
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en_MASK 0x40
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en__SHIFT 0x6
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en_MASK 0x80
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en__SHIFT 0x7
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en_MASK 0x1
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en__SHIFT 0x0
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en_MASK 0x2
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en__SHIFT 0x1
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en_MASK 0x4
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en__SHIFT 0x2
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en_MASK 0x40
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en__SHIFT 0x6
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en_MASK 0x80
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en__SHIFT 0x7
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en_MASK 0x1
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en__SHIFT 0x0
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en_MASK 0x2
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en__SHIFT 0x1
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en_MASK 0x4
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en__SHIFT 0x2
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en_MASK 0x40
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en__SHIFT 0x6
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en_MASK 0x80
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en__SHIFT 0x7
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en_MASK 0x1
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en__SHIFT 0x0
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en_MASK 0x2
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en__SHIFT 0x1
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en_MASK 0x4
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en__SHIFT 0x2
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en_MASK 0x40
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en__SHIFT 0x6
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en_MASK 0x80
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en__SHIFT 0x7
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en_MASK 0x1
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en__SHIFT 0x0
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en_MASK 0x2
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en__SHIFT 0x1
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en_MASK 0x4
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en__SHIFT 0x2
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en_MASK 0x40
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en__SHIFT 0x6
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en_MASK 0x80
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en__SHIFT 0x7
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en_MASK 0x1
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en__SHIFT 0x0
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en_MASK 0x2
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en__SHIFT 0x1
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en_MASK 0x4
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en__SHIFT 0x2
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en_MASK 0x40
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en__SHIFT 0x6
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en_MASK 0x80
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en__SHIFT 0x7
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en_MASK 0x1
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en__SHIFT 0x0
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en_MASK 0x2
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en__SHIFT 0x1
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en_MASK 0x4
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en__SHIFT 0x2
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en_MASK 0x40
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en__SHIFT 0x6
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en_MASK 0x80
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en__SHIFT 0x7
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en_MASK 0x1
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en__SHIFT 0x0
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en_MASK 0x2
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en__SHIFT 0x1
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en_MASK 0x4
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en__SHIFT 0x2
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en_MASK 0x40
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en__SHIFT 0x6
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en_MASK 0x80
+#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en__SHIFT 0x7
+#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel_MASK 0xf
+#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out_MASK 0x1ffc0
+#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out__SHIFT 0x6
+#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst_MASK 0x80000
+#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst__SHIFT 0x13
+#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en_MASK 0x100000
+#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en__SHIFT 0x14
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel_MASK 0xf
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out_MASK 0x1ffc0
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out__SHIFT 0x6
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst_MASK 0x80000
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst__SHIFT 0x13
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en_MASK 0x100000
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en__SHIFT 0x14
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel_MASK 0xf
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out_MASK 0x1ffc0
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out__SHIFT 0x6
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst_MASK 0x80000
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst__SHIFT 0x13
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en_MASK 0x100000
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en__SHIFT 0x14
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel_MASK 0xf
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out_MASK 0x1ffc0
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out__SHIFT 0x6
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst_MASK 0x80000
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst__SHIFT 0x13
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en_MASK 0x100000
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en__SHIFT 0x14
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel_MASK 0xf
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out_MASK 0x1ffc0
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out__SHIFT 0x6
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst_MASK 0x80000
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst__SHIFT 0x13
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en_MASK 0x100000
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en__SHIFT 0x14
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel_MASK 0xf
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out_MASK 0x1ffc0
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out__SHIFT 0x6
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst_MASK 0x80000
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst__SHIFT 0x13
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en_MASK 0x100000
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en__SHIFT 0x14
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel_MASK 0xf
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out_MASK 0x1ffc0
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out__SHIFT 0x6
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst_MASK 0x80000
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst__SHIFT 0x13
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en_MASK 0x100000
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en__SHIFT 0x14
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel_MASK 0xf
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out_MASK 0x1ffc0
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out__SHIFT 0x6
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst_MASK 0x80000
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst__SHIFT 0x13
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en_MASK 0x100000
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en__SHIFT 0x14
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel_MASK 0xf
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel__SHIFT 0x0
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out_MASK 0x1ffc0
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out__SHIFT 0x6
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst_MASK 0x80000
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst__SHIFT 0x13
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en_MASK 0x100000
+#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en__SHIFT 0x14
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr_MASK 0x7
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr__SHIFT 0x0
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en_MASK 0x18
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en__SHIFT 0x3
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x7
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x18
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x7
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x18
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x7
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x18
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x7
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x18
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr_MASK 0x7
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr__SHIFT 0x0
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en_MASK 0x18
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en__SHIFT 0x3
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr_MASK 0x7
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr__SHIFT 0x0
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en_MASK 0x18
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en__SHIFT 0x3
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr_MASK 0x7
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr__SHIFT 0x0
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en_MASK 0x18
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en__SHIFT 0x3
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr_MASK 0x7
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr__SHIFT 0x0
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en_MASK 0x18
+#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en__SHIFT 0x3
+#define PSX81_PHY0_TX_DFX_BROADCAST__obs_en_MASK 0x1
+#define PSX81_PHY0_TX_DFX_BROADCAST__obs_en__SHIFT 0x0
+#define PSX81_PHY0_TX_DFX_BROADCAST__obs_sel_MASK 0x4
+#define PSX81_PHY0_TX_DFX_BROADCAST__obs_sel__SHIFT 0x2
+#define PSX81_PHY0_TX_DFX_BROADCAST__felb_en_MASK 0x10
+#define PSX81_PHY0_TX_DFX_BROADCAST__felb_en__SHIFT 0x4
+#define PSX81_PHY0_TX_DFX_BROADCAST__prbs_en_MASK 0x100
+#define PSX81_PHY0_TX_DFX_BROADCAST__prbs_en__SHIFT 0x8
+#define PSX81_PHY0_TX_DFX_LANE0__obs_en_MASK 0x1
+#define PSX81_PHY0_TX_DFX_LANE0__obs_en__SHIFT 0x0
+#define PSX81_PHY0_TX_DFX_LANE0__obs_sel_MASK 0x4
+#define PSX81_PHY0_TX_DFX_LANE0__obs_sel__SHIFT 0x2
+#define PSX81_PHY0_TX_DFX_LANE0__felb_en_MASK 0x10
+#define PSX81_PHY0_TX_DFX_LANE0__felb_en__SHIFT 0x4
+#define PSX81_PHY0_TX_DFX_LANE0__prbs_en_MASK 0x100
+#define PSX81_PHY0_TX_DFX_LANE0__prbs_en__SHIFT 0x8
+#define PSX81_PHY0_TX_DFX_LANE1__obs_en_MASK 0x1
+#define PSX81_PHY0_TX_DFX_LANE1__obs_en__SHIFT 0x0
+#define PSX81_PHY0_TX_DFX_LANE1__obs_sel_MASK 0x4
+#define PSX81_PHY0_TX_DFX_LANE1__obs_sel__SHIFT 0x2
+#define PSX81_PHY0_TX_DFX_LANE1__felb_en_MASK 0x10
+#define PSX81_PHY0_TX_DFX_LANE1__felb_en__SHIFT 0x4
+#define PSX81_PHY0_TX_DFX_LANE1__prbs_en_MASK 0x100
+#define PSX81_PHY0_TX_DFX_LANE1__prbs_en__SHIFT 0x8
+#define PSX81_PHY0_TX_DFX_LANE2__obs_en_MASK 0x1
+#define PSX81_PHY0_TX_DFX_LANE2__obs_en__SHIFT 0x0
+#define PSX81_PHY0_TX_DFX_LANE2__obs_sel_MASK 0x4
+#define PSX81_PHY0_TX_DFX_LANE2__obs_sel__SHIFT 0x2
+#define PSX81_PHY0_TX_DFX_LANE2__felb_en_MASK 0x10
+#define PSX81_PHY0_TX_DFX_LANE2__felb_en__SHIFT 0x4
+#define PSX81_PHY0_TX_DFX_LANE2__prbs_en_MASK 0x100
+#define PSX81_PHY0_TX_DFX_LANE2__prbs_en__SHIFT 0x8
+#define PSX81_PHY0_TX_DFX_LANE3__obs_en_MASK 0x1
+#define PSX81_PHY0_TX_DFX_LANE3__obs_en__SHIFT 0x0
+#define PSX81_PHY0_TX_DFX_LANE3__obs_sel_MASK 0x4
+#define PSX81_PHY0_TX_DFX_LANE3__obs_sel__SHIFT 0x2
+#define PSX81_PHY0_TX_DFX_LANE3__felb_en_MASK 0x10
+#define PSX81_PHY0_TX_DFX_LANE3__felb_en__SHIFT 0x4
+#define PSX81_PHY0_TX_DFX_LANE3__prbs_en_MASK 0x100
+#define PSX81_PHY0_TX_DFX_LANE3__prbs_en__SHIFT 0x8
+#define PSX81_PHY0_TX_DFX_LANE4__obs_en_MASK 0x1
+#define PSX81_PHY0_TX_DFX_LANE4__obs_en__SHIFT 0x0
+#define PSX81_PHY0_TX_DFX_LANE4__obs_sel_MASK 0x4
+#define PSX81_PHY0_TX_DFX_LANE4__obs_sel__SHIFT 0x2
+#define PSX81_PHY0_TX_DFX_LANE4__felb_en_MASK 0x10
+#define PSX81_PHY0_TX_DFX_LANE4__felb_en__SHIFT 0x4
+#define PSX81_PHY0_TX_DFX_LANE4__prbs_en_MASK 0x100
+#define PSX81_PHY0_TX_DFX_LANE4__prbs_en__SHIFT 0x8
+#define PSX81_PHY0_TX_DFX_LANE5__obs_en_MASK 0x1
+#define PSX81_PHY0_TX_DFX_LANE5__obs_en__SHIFT 0x0
+#define PSX81_PHY0_TX_DFX_LANE5__obs_sel_MASK 0x4
+#define PSX81_PHY0_TX_DFX_LANE5__obs_sel__SHIFT 0x2
+#define PSX81_PHY0_TX_DFX_LANE5__felb_en_MASK 0x10
+#define PSX81_PHY0_TX_DFX_LANE5__felb_en__SHIFT 0x4
+#define PSX81_PHY0_TX_DFX_LANE5__prbs_en_MASK 0x100
+#define PSX81_PHY0_TX_DFX_LANE5__prbs_en__SHIFT 0x8
+#define PSX81_PHY0_TX_DFX_LANE6__obs_en_MASK 0x1
+#define PSX81_PHY0_TX_DFX_LANE6__obs_en__SHIFT 0x0
+#define PSX81_PHY0_TX_DFX_LANE6__obs_sel_MASK 0x4
+#define PSX81_PHY0_TX_DFX_LANE6__obs_sel__SHIFT 0x2
+#define PSX81_PHY0_TX_DFX_LANE6__felb_en_MASK 0x10
+#define PSX81_PHY0_TX_DFX_LANE6__felb_en__SHIFT 0x4
+#define PSX81_PHY0_TX_DFX_LANE6__prbs_en_MASK 0x100
+#define PSX81_PHY0_TX_DFX_LANE6__prbs_en__SHIFT 0x8
+#define PSX81_PHY0_TX_DFX_LANE7__obs_en_MASK 0x1
+#define PSX81_PHY0_TX_DFX_LANE7__obs_en__SHIFT 0x0
+#define PSX81_PHY0_TX_DFX_LANE7__obs_sel_MASK 0x4
+#define PSX81_PHY0_TX_DFX_LANE7__obs_sel__SHIFT 0x2
+#define PSX81_PHY0_TX_DFX_LANE7__felb_en_MASK 0x10
+#define PSX81_PHY0_TX_DFX_LANE7__felb_en__SHIFT 0x4
+#define PSX81_PHY0_TX_DFX_LANE7__prbs_en_MASK 0x100
+#define PSX81_PHY0_TX_DFX_LANE7__prbs_en__SHIFT 0x8
+#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1_MASK 0xff
+#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1__SHIFT 0x0
+#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0_MASK 0x3f00
+#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0__SHIFT 0x8
+#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1_MASK 0xff0000
+#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1__SHIFT 0x10
+#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1_MASK 0xff
+#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1__SHIFT 0x0
+#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0_MASK 0x3f00
+#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0__SHIFT 0x8
+#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1_MASK 0xff0000
+#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1__SHIFT 0x10
+#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1_MASK 0xff
+#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1__SHIFT 0x0
+#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0_MASK 0x3f00
+#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0__SHIFT 0x8
+#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1_MASK 0xff0000
+#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1__SHIFT 0x10
+#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1_MASK 0xff
+#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1__SHIFT 0x0
+#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0_MASK 0x3f00
+#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0__SHIFT 0x8
+#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1_MASK 0xff0000
+#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1__SHIFT 0x10
+#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1_MASK 0xff
+#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1__SHIFT 0x0
+#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0_MASK 0x3f00
+#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0__SHIFT 0x8
+#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1_MASK 0xff0000
+#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1__SHIFT 0x10
+#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1_MASK 0xff
+#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1__SHIFT 0x0
+#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0_MASK 0x3f00
+#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0__SHIFT 0x8
+#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1_MASK 0xff0000
+#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1__SHIFT 0x10
+#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1_MASK 0xff
+#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1__SHIFT 0x0
+#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0_MASK 0x3f00
+#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0__SHIFT 0x8
+#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1_MASK 0xff0000
+#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1__SHIFT 0x10
+#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1_MASK 0xff
+#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1__SHIFT 0x0
+#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0_MASK 0x3f00
+#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0__SHIFT 0x8
+#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1_MASK 0xff0000
+#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1__SHIFT 0x10
+#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1_MASK 0xff
+#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1__SHIFT 0x0
+#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0_MASK 0x3f00
+#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0__SHIFT 0x8
+#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1_MASK 0xff0000
+#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1__SHIFT 0x10
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel_MASK 0x7
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel__SHIFT 0x0
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel_MASK 0x8
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel__SHIFT 0x3
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel_MASK 0x7
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel__SHIFT 0x0
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel_MASK 0x8
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel__SHIFT 0x3
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel_MASK 0x7
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel__SHIFT 0x0
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel_MASK 0x8
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel__SHIFT 0x3
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel_MASK 0x7
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel__SHIFT 0x0
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel_MASK 0x8
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel__SHIFT 0x3
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel_MASK 0x7
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel__SHIFT 0x0
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel_MASK 0x8
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel__SHIFT 0x3
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel_MASK 0x7
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel__SHIFT 0x0
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel_MASK 0x8
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel__SHIFT 0x3
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel_MASK 0x7
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel__SHIFT 0x0
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel_MASK 0x8
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel__SHIFT 0x3
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel_MASK 0x7
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel__SHIFT 0x0
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel_MASK 0x8
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel__SHIFT 0x3
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel_MASK 0x7
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel__SHIFT 0x0
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel_MASK 0x8
+#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel__SHIFT 0x3
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary_MASK 0x1f
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary__SHIFT 0x0
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid_MASK 0x40
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid__SHIFT 0x6
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated_MASK 0x100
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated__SHIFT 0x8
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error_MASK 0x400
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error__SHIFT 0xa
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done_MASK 0x1000
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done__SHIFT 0xc
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated_MASK 0x7f0000
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated__SHIFT 0x10
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary_MASK 0x1f
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary__SHIFT 0x0
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid_MASK 0x40
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid__SHIFT 0x6
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated_MASK 0x100
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated__SHIFT 0x8
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error_MASK 0x400
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error__SHIFT 0xa
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done_MASK 0x1000
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done__SHIFT 0xc
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated_MASK 0x7f0000
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated__SHIFT 0x10
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary_MASK 0x1f
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary__SHIFT 0x0
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid_MASK 0x40
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid__SHIFT 0x6
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated_MASK 0x100
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated__SHIFT 0x8
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error_MASK 0x400
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error__SHIFT 0xa
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done_MASK 0x1000
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done__SHIFT 0xc
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated_MASK 0x7f0000
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated__SHIFT 0x10
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary_MASK 0x1f
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary__SHIFT 0x0
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid_MASK 0x40
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid__SHIFT 0x6
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated_MASK 0x100
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated__SHIFT 0x8
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error_MASK 0x400
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error__SHIFT 0xa
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done_MASK 0x1000
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done__SHIFT 0xc
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated_MASK 0x7f0000
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated__SHIFT 0x10
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary_MASK 0x1f
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary__SHIFT 0x0
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid_MASK 0x40
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid__SHIFT 0x6
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated_MASK 0x100
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated__SHIFT 0x8
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error_MASK 0x400
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error__SHIFT 0xa
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done_MASK 0x1000
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done__SHIFT 0xc
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated_MASK 0x7f0000
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated__SHIFT 0x10
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary_MASK 0x1f
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary__SHIFT 0x0
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid_MASK 0x40
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid__SHIFT 0x6
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated_MASK 0x100
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated__SHIFT 0x8
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error_MASK 0x400
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error__SHIFT 0xa
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done_MASK 0x1000
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done__SHIFT 0xc
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated_MASK 0x7f0000
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated__SHIFT 0x10
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary_MASK 0x1f
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary__SHIFT 0x0
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid_MASK 0x40
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid__SHIFT 0x6
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated_MASK 0x100
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated__SHIFT 0x8
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error_MASK 0x400
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error__SHIFT 0xa
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done_MASK 0x1000
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done__SHIFT 0xc
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated_MASK 0x7f0000
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated__SHIFT 0x10
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary_MASK 0x1f
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary__SHIFT 0x0
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid_MASK 0x40
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid__SHIFT 0x6
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated_MASK 0x100
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated__SHIFT 0x8
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error_MASK 0x400
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error__SHIFT 0xa
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done_MASK 0x1000
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done__SHIFT 0xc
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated_MASK 0x7f0000
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated__SHIFT 0x10
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary_MASK 0x1f
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary__SHIFT 0x0
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid_MASK 0x40
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid__SHIFT 0x6
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated_MASK 0x100
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated__SHIFT 0x8
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error_MASK 0x400
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error__SHIFT 0xa
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done_MASK 0x1000
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done__SHIFT 0xc
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated_MASK 0x7f0000
+#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated__SHIFT 0x10
+#define PSX81_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response_MASK 0x800
+#define PSX81_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response__SHIFT 0xb
+#define PSX81_PHY0_TX_TXCNTRL_LANE0__rxdetect_response_MASK 0x800
+#define PSX81_PHY0_TX_TXCNTRL_LANE0__rxdetect_response__SHIFT 0xb
+#define PSX81_PHY0_TX_TXCNTRL_LANE1__rxdetect_response_MASK 0x800
+#define PSX81_PHY0_TX_TXCNTRL_LANE1__rxdetect_response__SHIFT 0xb
+#define PSX81_PHY0_TX_TXCNTRL_LANE2__rxdetect_response_MASK 0x800
+#define PSX81_PHY0_TX_TXCNTRL_LANE2__rxdetect_response__SHIFT 0xb
+#define PSX81_PHY0_TX_TXCNTRL_LANE3__rxdetect_response_MASK 0x800
+#define PSX81_PHY0_TX_TXCNTRL_LANE3__rxdetect_response__SHIFT 0xb
+#define PSX81_PHY0_TX_TXCNTRL_LANE4__rxdetect_response_MASK 0x800
+#define PSX81_PHY0_TX_TXCNTRL_LANE4__rxdetect_response__SHIFT 0xb
+#define PSX81_PHY0_TX_TXCNTRL_LANE5__rxdetect_response_MASK 0x800
+#define PSX81_PHY0_TX_TXCNTRL_LANE5__rxdetect_response__SHIFT 0xb
+#define PSX81_PHY0_TX_TXCNTRL_LANE6__rxdetect_response_MASK 0x800
+#define PSX81_PHY0_TX_TXCNTRL_LANE6__rxdetect_response__SHIFT 0xb
+#define PSX81_PHY0_TX_TXCNTRL_LANE7__rxdetect_response_MASK 0x800
+#define PSX81_PHY0_TX_TXCNTRL_LANE7__rxdetect_response__SHIFT 0xb
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en_MASK 0x1
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en__SHIFT 0x0
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed_MASK 0x6
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed__SHIFT 0x1
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2_MASK 0x8
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2__SHIFT 0x3
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode_MASK 0xe0
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode__SHIFT 0x5
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x1
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x0
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x6
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x1
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2_MASK 0x8
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2__SHIFT 0x3
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0xe0
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x1
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x0
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x6
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x1
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2_MASK 0x8
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2__SHIFT 0x3
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0xe0
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x1
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x0
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x6
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x1
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2_MASK 0x8
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2__SHIFT 0x3
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0xe0
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x1
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x0
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x6
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x1
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2_MASK 0x8
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2__SHIFT 0x3
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0xe0
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en_MASK 0x1
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en__SHIFT 0x0
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed_MASK 0x6
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed__SHIFT 0x1
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2_MASK 0x8
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2__SHIFT 0x3
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode_MASK 0xe0
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode__SHIFT 0x5
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en_MASK 0x1
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en__SHIFT 0x0
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed_MASK 0x6
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed__SHIFT 0x1
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2_MASK 0x8
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2__SHIFT 0x3
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode_MASK 0xe0
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode__SHIFT 0x5
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en_MASK 0x1
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en__SHIFT 0x0
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed_MASK 0x6
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed__SHIFT 0x1
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2_MASK 0x8
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2__SHIFT 0x3
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode_MASK 0xe0
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode__SHIFT 0x5
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en_MASK 0x1
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en__SHIFT 0x0
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed_MASK 0x6
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed__SHIFT 0x1
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2_MASK 0x8
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2__SHIFT 0x3
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode_MASK 0xe0
+#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode__SHIFT 0x5
+#define PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn_MASK 0x7
+#define PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn__SHIFT 0x0
+#define PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd_MASK 0x10
+#define PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd__SHIFT 0x4
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer_MASK 0x7
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT 0x0
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce_MASK 0x8
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT 0x3
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange_MASK 0xff
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange__SHIFT 0x0
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes_MASK 0x3c00
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes__SHIFT 0xa
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac_MASK 0x3fc000
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac__SHIFT 0xe
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer_MASK 0x3c00000
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer__SHIFT 0x16
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLock_MASK 0x4000000
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLock__SHIFT 0x1a
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect_MASK 0x10000000
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect__SHIFT 0x1c
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked_MASK 0x20000000
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked__SHIFT 0x1d
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer_MASK 0xc0000000
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer__SHIFT 0x1e
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl_MASK 0x7ff
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl__SHIFT 0x0
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp_MASK 0xfffff800
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp__SHIFT 0xb
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut_MASK 0x3ffff
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut__SHIFT 0x0
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo_MASK 0x40000
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo__SHIFT 0x12
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel_MASK 0xe00000
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT 0x15
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq_MASK 0x7f
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq__SHIFT 0x0
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd_MASK 0x80
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd__SHIFT 0x7
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn_MASK 0x100
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn__SHIFT 0x8
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd_MASK 0x200
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd__SHIFT 0x9
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate_MASK 0x400
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate__SHIFT 0xa
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd_MASK 0x800
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd__SHIFT 0xb
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn_MASK 0x1000
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn__SHIFT 0xc
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK 0x2000
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT 0xd
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn_MASK 0x10000
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn__SHIFT 0x10
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK 0x20000
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT 0x11
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate_MASK 0x1
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT 0x0
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal_MASK 0x1
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal__SHIFT 0x0
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal_MASK 0x2
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal__SHIFT 0x1
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal_MASK 0x4
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal__SHIFT 0x2
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone_MASK 0x8
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone__SHIFT 0x3
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext_MASK 0x10
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT 0x4
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail_MASK 0x60
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail__SHIFT 0x5
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn_MASK 0x3f00000
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn__SHIFT 0x14
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut_MASK 0x4000000
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut__SHIFT 0x1a
+#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid_MASK 0x1
+#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid__SHIFT 0x0
+#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj_MASK 0x1e
+#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj__SHIFT 0x1
+#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare_MASK 0xf00
+#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare__SHIFT 0x8
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv_MASK 0xffff
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv__SHIFT 0x0
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0_MASK 0xff
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0__SHIFT 0x0
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8_MASK 0xf00
+#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8__SHIFT 0x8
+#define PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn_MASK 0x7
+#define PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn__SHIFT 0x0
+#define PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd_MASK 0x10
+#define PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd__SHIFT 0x4
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer_MASK 0x7
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT 0x0
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce_MASK 0x8
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT 0x3
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange_MASK 0xff
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange__SHIFT 0x0
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin_MASK 0x700
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin__SHIFT 0x8
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes_MASK 0x3000
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes__SHIFT 0xc
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0_MASK 0x3c000
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0__SHIFT 0xe
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4_MASK 0x3c0000
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4__SHIFT 0x12
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer_MASK 0x3c00000
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer__SHIFT 0x16
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLock_MASK 0x4000000
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLock__SHIFT 0x1a
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect_MASK 0x10000000
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect__SHIFT 0x1c
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked_MASK 0x20000000
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked__SHIFT 0x1d
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer_MASK 0xc0000000
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer__SHIFT 0x1e
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl_MASK 0x7ff
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl__SHIFT 0x0
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp_MASK 0xfffff800
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp__SHIFT 0xb
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut_MASK 0x3ffff
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut__SHIFT 0x0
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo_MASK 0x40000
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo__SHIFT 0x12
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel_MASK 0xe00000
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT 0x15
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn_MASK 0x1000
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn__SHIFT 0xc
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK 0x2000
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT 0xd
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn_MASK 0x10000
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn__SHIFT 0x10
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK 0x20000
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT 0x11
+#define PSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI_MASK 0xff
+#define PSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI__SHIFT 0x0
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate_MASK 0x1
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT 0x0
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt_MASK 0x3800000
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt__SHIFT 0x17
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt_MASK 0x3fff
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt__SHIFT 0x0
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone_MASK 0x8000
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone__SHIFT 0xf
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext_MASK 0x10000
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT 0x10
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail_MASK 0xe0000
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail__SHIFT 0x11
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn_MASK 0x3f00000
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn__SHIFT 0x14
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut_MASK 0x4000000
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut__SHIFT 0x1a
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn_MASK 0x8000000
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn__SHIFT 0x1b
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal_MASK 0x20000000
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal__SHIFT 0x1d
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv_MASK 0xffff
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv__SHIFT 0x0
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0_MASK 0xff
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0__SHIFT 0x0
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8_MASK 0xf00
+#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8__SHIFT 0x8
+#define PSX80_PIF0_SCRATCH__PIF_SCRATCH_MASK 0xffffffff
+#define PSX80_PIF0_SCRATCH__PIF_SCRATCH__SHIFT 0x0
+#define PSX80_PIF0_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define PSX80_PIF0_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define PSX80_PIF0_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define PSX80_PIF0_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define PSX80_PIF0_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define PSX80_PIF0_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define PSX80_PIF0_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define PSX80_PIF0_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define PSX80_PIF0_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define PSX80_PIF0_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define PSX80_PIF0_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define PSX80_PIF0_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define PSX80_PIF0_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define PSX80_PIF0_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define PSX80_PIF0_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define PSX80_PIF0_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define PSX80_PIF0_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define PSX80_PIF0_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define PSX80_PIF0_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define PSX80_PIF0_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define PSX80_PIF0_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define PSX80_PIF0_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define PSX80_PIF0_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define PSX80_PIF0_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define PSX80_PIF0_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define PSX80_PIF0_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define PSX80_PIF0_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define PSX80_PIF0_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define PSX80_PIF0_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define PSX80_PIF0_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define PSX80_PIF0_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define PSX80_PIF0_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define PSX80_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2
+#define PSX80_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT 0x1
+#define PSX80_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK 0x4
+#define PSX80_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2
+#define PSX80_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK 0x8
+#define PSX80_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT 0x3
+#define PSX80_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK 0x10
+#define PSX80_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT 0x4
+#define PSX80_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK 0x20
+#define PSX80_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT 0x5
+#define PSX80_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK 0xc0
+#define PSX80_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT 0x6
+#define PSX80_PIF0_STRAP_0__STRAP_RX_EI_FILTER_MASK 0x300
+#define PSX80_PIF0_STRAP_0__STRAP_RX_EI_FILTER__SHIFT 0x8
+#define PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK 0x400
+#define PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT 0xa
+#define PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK 0x800
+#define PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT 0xb
+#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_12_MASK 0x1000
+#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_12__SHIFT 0xc
+#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_13_MASK 0x2000
+#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_13__SHIFT 0xd
+#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_14_MASK 0x4000
+#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_14__SHIFT 0xe
+#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_15_MASK 0x8000
+#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_15__SHIFT 0xf
+#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_16_MASK 0x10000
+#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_16__SHIFT 0x10
+#define PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EN_MASK 0x1
+#define PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EN__SHIFT 0x0
+#define PSX80_PIF0_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2
+#define PSX80_PIF0_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT 0x1
+#define PSX80_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK 0x4
+#define PSX80_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2
+#define PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK 0x8
+#define PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT 0x3
+#define PSX80_PIF0_CTRL__PHY_RST_PWROK_VDD_MASK 0x10
+#define PSX80_PIF0_CTRL__PHY_RST_PWROK_VDD__SHIFT 0x4
+#define PSX80_PIF0_CTRL__PIF_PLL_STATUS_MASK 0xc0
+#define PSX80_PIF0_CTRL__PIF_PLL_STATUS__SHIFT 0x6
+#define PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK 0x100
+#define PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT 0x8
+#define PSX80_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK 0x200
+#define PSX80_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT 0x9
+#define PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK 0x400
+#define PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT 0xa
+#define PSX80_PIF0_CTRL__PIF_PG_EXIT_MODE_MASK 0x800
+#define PSX80_PIF0_CTRL__PIF_PG_EXIT_MODE__SHIFT 0xb
+#define PSX80_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK 0x1000
+#define PSX80_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT 0xc
+#define PSX80_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK 0x2000
+#define PSX80_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT 0xd
+#define PSX80_PIF0_CTRL__PIF_PG_ABORT_DISABLE_MASK 0x4000
+#define PSX80_PIF0_CTRL__PIF_PG_ABORT_DISABLE__SHIFT 0xe
+#define PSX80_PIF0_TX_CTRL__TXPWR_IN_S2_MASK 0x7
+#define PSX80_PIF0_TX_CTRL__TXPWR_IN_S2__SHIFT 0x0
+#define PSX80_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG_MASK 0x38
+#define PSX80_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT 0x3
+#define PSX80_PIF0_TX_CTRL__TXPWR_IN_OFF_MASK 0x1c0
+#define PSX80_PIF0_TX_CTRL__TXPWR_IN_OFF__SHIFT 0x6
+#define PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MASK 0xe00
+#define PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT 0x9
+#define PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MASK 0x7000
+#define PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED__SHIFT 0xc
+#define PSX80_PIF0_TX_CTRL__TXPWR_IN_INIT_MASK 0x38000
+#define PSX80_PIF0_TX_CTRL__TXPWR_IN_INIT__SHIFT 0xf
+#define PSX80_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF_MASK 0x1c0000
+#define PSX80_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT 0x12
+#define PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK 0x200000
+#define PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT 0x15
+#define PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK 0x400000
+#define PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT 0x16
+#define PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_L1_MASK 0x800000
+#define PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT 0x17
+#define PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK 0x1000000
+#define PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT 0x18
+#define PSX80_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK 0x7
+#define PSX80_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT 0x0
+#define PSX80_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK 0x38
+#define PSX80_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT 0x3
+#define PSX80_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY_MASK 0x1c0
+#define PSX80_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT 0x6
+#define PSX80_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK 0x200
+#define PSX80_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9
+#define PSX80_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK 0x400
+#define PSX80_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa
+#define PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK 0x10000
+#define PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT 0x10
+#define PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK 0x60000
+#define PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT 0x11
+#define PSX80_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID_MASK 0x200000
+#define PSX80_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT 0x15
+#define PSX80_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK 0x1c00000
+#define PSX80_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT 0x16
+#define PSX80_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK 0x2000000
+#define PSX80_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT 0x19
+#define PSX80_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK 0x1c000000
+#define PSX80_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT 0x1a
+#define PSX80_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK 0x20000000
+#define PSX80_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT 0x1d
+#define PSX80_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK 0x40000000
+#define PSX80_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT 0x1e
+#define PSX80_PIF0_RX_CTRL__RXPWR_IN_S2_MASK 0x7
+#define PSX80_PIF0_RX_CTRL__RXPWR_IN_S2__SHIFT 0x0
+#define PSX80_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG_MASK 0x38
+#define PSX80_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT 0x3
+#define PSX80_PIF0_RX_CTRL__RXPWR_IN_OFF_MASK 0x1c0
+#define PSX80_PIF0_RX_CTRL__RXPWR_IN_OFF__SHIFT 0x6
+#define PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MASK 0xe00
+#define PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT 0x9
+#define PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MASK 0x7000
+#define PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED__SHIFT 0xc
+#define PSX80_PIF0_RX_CTRL__RXPWR_IN_INIT_MASK 0x38000
+#define PSX80_PIF0_RX_CTRL__RXPWR_IN_INIT__SHIFT 0xf
+#define PSX80_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF_MASK 0x1c0000
+#define PSX80_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT 0x12
+#define PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK 0x200000
+#define PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT 0x15
+#define PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK 0x400000
+#define PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT 0x16
+#define PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_L1_MASK 0x800000
+#define PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT 0x17
+#define PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK 0x1000000
+#define PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT 0x18
+#define PSX80_PIF0_RX_CTRL__RX_HLD_EIE_COUNT_MASK 0x2000000
+#define PSX80_PIF0_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT 0x19
+#define PSX80_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK 0x4000000
+#define PSX80_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT 0x1a
+#define PSX80_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK 0x7
+#define PSX80_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT 0x0
+#define PSX80_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK 0x38
+#define PSX80_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT 0x3
+#define PSX80_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY_MASK 0x1c0
+#define PSX80_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT 0x6
+#define PSX80_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK 0x200
+#define PSX80_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9
+#define PSX80_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK 0x400
+#define PSX80_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa
+#define PSX80_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK 0x10000
+#define PSX80_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT 0x10
+#define PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE_MASK 0x60000
+#define PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT 0x11
+#define PSX80_PIF0_RX_CTRL2__EI_DET_ON_TIME_MASK 0x180000
+#define PSX80_PIF0_RX_CTRL2__EI_DET_ON_TIME__SHIFT 0x13
+#define PSX80_PIF0_RX_CTRL2__EI_DET_OFF_TIME_MASK 0xe00000
+#define PSX80_PIF0_RX_CTRL2__EI_DET_OFF_TIME__SHIFT 0x15
+#define PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK 0x1000000
+#define PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT 0x18
+#define PSX80_PIF0_RX_CTRL2__RX_CDR_XTND_MODE_MASK 0x6000000
+#define PSX80_PIF0_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT 0x19
+#define PSX80_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK 0x8000000
+#define PSX80_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT 0x1b
+#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK 0x1
+#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x0
+#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2
+#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x1
+#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK 0x4
+#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2
+#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK 0x8
+#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x3
+#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK 0x10
+#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x4
+#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK 0x20
+#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x5
+#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK 0x40
+#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x6
+#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK 0x80
+#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x7
+#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK 0x10000
+#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT 0x10
+#define PSX80_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK 0x1
+#define PSX80_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT 0x0
+#define PSX80_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2
+#define PSX80_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT 0x1
+#define PSX80_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK 0x4
+#define PSX80_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2
+#define PSX80_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK 0x8
+#define PSX80_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT 0x3
+#define PSX80_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK 0x10
+#define PSX80_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT 0x4
+#define PSX80_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK 0x20
+#define PSX80_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT 0x5
+#define PSX80_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK 0x40
+#define PSX80_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT 0x6
+#define PSX80_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK 0x80
+#define PSX80_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT 0x7
+#define PSX80_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK 0x100
+#define PSX80_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT 0x8
+#define PSX80_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK 0x200
+#define PSX80_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT 0x9
+#define PSX80_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK 0x400
+#define PSX80_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT 0xa
+#define PSX80_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK 0x800
+#define PSX80_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT 0xb
+#define PSX80_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK 0x10000
+#define PSX80_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT 0x10
+#define PSX80_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK 0x20000
+#define PSX80_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT 0x11
+#define PSX80_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK 0x100000
+#define PSX80_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT 0x14
+#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK 0x1
+#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT 0x0
+#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2
+#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT 0x1
+#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK 0x4
+#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2
+#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK 0x8
+#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT 0x3
+#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK 0x10
+#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT 0x4
+#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK 0x20
+#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT 0x5
+#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK 0x40
+#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT 0x6
+#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK 0x80
+#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT 0x7
+#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK 0x100
+#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT 0x8
+#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK 0x200
+#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT 0x9
+#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK 0x400
+#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT 0xa
+#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK 0x800
+#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT 0xb
+#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK 0x1000
+#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT 0xc
+#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK 0x2000
+#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT 0xd
+#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK 0x4000
+#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT 0xe
+#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK 0x8000
+#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT 0xf
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK 0x10000
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT 0x10
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK 0x20000
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT 0x11
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK 0x40000
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT 0x12
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK 0x80000
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT 0x13
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK 0x100000
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT 0x14
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK 0x200000
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT 0x15
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK 0x400000
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT 0x16
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK 0x800000
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT 0x17
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK 0x1000000
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT 0x18
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK 0x2000000
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT 0x19
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK 0x4000000
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT 0x1a
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK 0x8000000
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT 0x1b
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK 0x10000000
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT 0x1c
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK 0x20000000
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT 0x1d
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK 0x40000000
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT 0x1e
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK 0x80000000
+#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT 0x1f
+#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK 0x3
+#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT 0x0
+#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK 0xc
+#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2
+#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK 0x10
+#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT 0x4
+#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK 0x60
+#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT 0x5
+#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK 0x80
+#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT 0x7
+#define PSX80_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK 0x100
+#define PSX80_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT 0x8
+#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK 0x200
+#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT 0x9
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK 0x1
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT 0x0
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT 0x1
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK 0x4
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG_MASK 0x38
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG__SHIFT 0x3
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_MASK 0x40
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT 0x6
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_MASK 0x180
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT 0x7
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK 0x200
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT 0x9
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK 0x10000
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT 0x10
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK 0x20000
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT 0x11
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK 0x40000
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT 0x12
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK 0x80000
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT 0x13
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK 0x100000
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT 0x14
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK 0x200000
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT 0x15
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK 0x400000
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT 0x16
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK 0x800000
+#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT 0x17
+#define PSX80_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK 0x1
+#define PSX80_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT 0x0
+#define PSX80_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2
+#define PSX80_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT 0x1
+#define PSX80_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK 0x4
+#define PSX80_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2
+#define PSX80_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK 0x8
+#define PSX80_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT 0x3
+#define PSX80_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK 0x10
+#define PSX80_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT 0x4
+#define PSX80_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK 0x20
+#define PSX80_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT 0x5
+#define PSX80_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK 0x40
+#define PSX80_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT 0x6
+#define PSX80_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK 0x80
+#define PSX80_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT 0x7
+#define PSX80_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK 0x100
+#define PSX80_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT 0x8
+#define PSX80_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK 0x200
+#define PSX80_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT 0x9
+#define PSX80_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK 0x400
+#define PSX80_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT 0xa
+#define PSX80_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK 0x800
+#define PSX80_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT 0xb
+#define PSX80_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK 0x1000
+#define PSX80_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT 0xc
+#define PSX80_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK 0x2000
+#define PSX80_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT 0xd
+#define PSX80_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK 0x4000
+#define PSX80_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT 0xe
+#define PSX80_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK 0x8000
+#define PSX80_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT 0xf
+#define PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0_MASK 0x10000
+#define PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT 0x10
+#define PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK 0x20000
+#define PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT 0x11
+#define PSX80_PIF0_LANE0_OVRD2__GANGMODE_0_MASK 0x7
+#define PSX80_PIF0_LANE0_OVRD2__GANGMODE_0__SHIFT 0x0
+#define PSX80_PIF0_LANE0_OVRD2__FREQDIV_0_MASK 0x18
+#define PSX80_PIF0_LANE0_OVRD2__FREQDIV_0__SHIFT 0x3
+#define PSX80_PIF0_LANE0_OVRD2__LINKSPEED_0_MASK 0x60
+#define PSX80_PIF0_LANE0_OVRD2__LINKSPEED_0__SHIFT 0x5
+#define PSX80_PIF0_LANE0_OVRD2__TWOSYMENABLE_0_MASK 0x80
+#define PSX80_PIF0_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT 0x7
+#define PSX80_PIF0_LANE0_OVRD2__TXPWR_0_MASK 0x700
+#define PSX80_PIF0_LANE0_OVRD2__TXPWR_0__SHIFT 0x8
+#define PSX80_PIF0_LANE0_OVRD2__TXPGENABLE_0_MASK 0x1800
+#define PSX80_PIF0_LANE0_OVRD2__TXPGENABLE_0__SHIFT 0xb
+#define PSX80_PIF0_LANE0_OVRD2__RXPWR_0_MASK 0xe000
+#define PSX80_PIF0_LANE0_OVRD2__RXPWR_0__SHIFT 0xd
+#define PSX80_PIF0_LANE0_OVRD2__RXPGENABLE_0_MASK 0x30000
+#define PSX80_PIF0_LANE0_OVRD2__RXPGENABLE_0__SHIFT 0x10
+#define PSX80_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0_MASK 0x40000
+#define PSX80_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT 0x12
+#define PSX80_PIF0_LANE0_OVRD2__ENABLEFOM_0_MASK 0x80000
+#define PSX80_PIF0_LANE0_OVRD2__ENABLEFOM_0__SHIFT 0x13
+#define PSX80_PIF0_LANE0_OVRD2__REQUESTFOM_0_MASK 0x100000
+#define PSX80_PIF0_LANE0_OVRD2__REQUESTFOM_0__SHIFT 0x14
+#define PSX80_PIF0_LANE0_OVRD2__RESPONSEMODE_0_MASK 0x200000
+#define PSX80_PIF0_LANE0_OVRD2__RESPONSEMODE_0__SHIFT 0x15
+#define PSX80_PIF0_LANE0_OVRD2__REQUESTTRK_0_MASK 0x400000
+#define PSX80_PIF0_LANE0_OVRD2__REQUESTTRK_0__SHIFT 0x16
+#define PSX80_PIF0_LANE0_OVRD2__REQUESTTRN_0_MASK 0x800000
+#define PSX80_PIF0_LANE0_OVRD2__REQUESTTRN_0__SHIFT 0x17
+#define PSX80_PIF0_LANE0_OVRD2__COEFFICIENTID_0_MASK 0x3000000
+#define PSX80_PIF0_LANE0_OVRD2__COEFFICIENTID_0__SHIFT 0x18
+#define PSX80_PIF0_LANE0_OVRD2__COEFFICIENT_0_MASK 0xfc000000
+#define PSX80_PIF0_LANE0_OVRD2__COEFFICIENT_0__SHIFT 0x1a
+#define PSX80_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK 0x1
+#define PSX80_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT 0x0
+#define PSX80_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2
+#define PSX80_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT 0x1
+#define PSX80_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK 0x4
+#define PSX80_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2
+#define PSX80_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK 0x8
+#define PSX80_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT 0x3
+#define PSX80_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK 0x10
+#define PSX80_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT 0x4
+#define PSX80_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK 0x20
+#define PSX80_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT 0x5
+#define PSX80_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK 0x40
+#define PSX80_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT 0x6
+#define PSX80_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK 0x80
+#define PSX80_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT 0x7
+#define PSX80_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK 0x100
+#define PSX80_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT 0x8
+#define PSX80_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK 0x200
+#define PSX80_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT 0x9
+#define PSX80_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK 0x400
+#define PSX80_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT 0xa
+#define PSX80_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK 0x800
+#define PSX80_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT 0xb
+#define PSX80_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK 0x1000
+#define PSX80_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT 0xc
+#define PSX80_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK 0x2000
+#define PSX80_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT 0xd
+#define PSX80_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK 0x4000
+#define PSX80_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT 0xe
+#define PSX80_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK 0x8000
+#define PSX80_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT 0xf
+#define PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1_MASK 0x10000
+#define PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT 0x10
+#define PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK 0x20000
+#define PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT 0x11
+#define PSX80_PIF0_LANE1_OVRD2__GANGMODE_1_MASK 0x7
+#define PSX80_PIF0_LANE1_OVRD2__GANGMODE_1__SHIFT 0x0
+#define PSX80_PIF0_LANE1_OVRD2__FREQDIV_1_MASK 0x18
+#define PSX80_PIF0_LANE1_OVRD2__FREQDIV_1__SHIFT 0x3
+#define PSX80_PIF0_LANE1_OVRD2__LINKSPEED_1_MASK 0x60
+#define PSX80_PIF0_LANE1_OVRD2__LINKSPEED_1__SHIFT 0x5
+#define PSX80_PIF0_LANE1_OVRD2__TWOSYMENABLE_1_MASK 0x80
+#define PSX80_PIF0_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT 0x7
+#define PSX80_PIF0_LANE1_OVRD2__TXPWR_1_MASK 0x700
+#define PSX80_PIF0_LANE1_OVRD2__TXPWR_1__SHIFT 0x8
+#define PSX80_PIF0_LANE1_OVRD2__TXPGENABLE_1_MASK 0x1800
+#define PSX80_PIF0_LANE1_OVRD2__TXPGENABLE_1__SHIFT 0xb
+#define PSX80_PIF0_LANE1_OVRD2__RXPWR_1_MASK 0xe000
+#define PSX80_PIF0_LANE1_OVRD2__RXPWR_1__SHIFT 0xd
+#define PSX80_PIF0_LANE1_OVRD2__RXPGENABLE_1_MASK 0x30000
+#define PSX80_PIF0_LANE1_OVRD2__RXPGENABLE_1__SHIFT 0x10
+#define PSX80_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1_MASK 0x40000
+#define PSX80_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT 0x12
+#define PSX80_PIF0_LANE1_OVRD2__ENABLEFOM_1_MASK 0x80000
+#define PSX80_PIF0_LANE1_OVRD2__ENABLEFOM_1__SHIFT 0x13
+#define PSX80_PIF0_LANE1_OVRD2__REQUESTFOM_1_MASK 0x100000
+#define PSX80_PIF0_LANE1_OVRD2__REQUESTFOM_1__SHIFT 0x14
+#define PSX80_PIF0_LANE1_OVRD2__RESPONSEMODE_1_MASK 0x200000
+#define PSX80_PIF0_LANE1_OVRD2__RESPONSEMODE_1__SHIFT 0x15
+#define PSX80_PIF0_LANE1_OVRD2__REQUESTTRK_1_MASK 0x400000
+#define PSX80_PIF0_LANE1_OVRD2__REQUESTTRK_1__SHIFT 0x16
+#define PSX80_PIF0_LANE1_OVRD2__REQUESTTRN_1_MASK 0x800000
+#define PSX80_PIF0_LANE1_OVRD2__REQUESTTRN_1__SHIFT 0x17
+#define PSX80_PIF0_LANE1_OVRD2__COEFFICIENTID_1_MASK 0x3000000
+#define PSX80_PIF0_LANE1_OVRD2__COEFFICIENTID_1__SHIFT 0x18
+#define PSX80_PIF0_LANE1_OVRD2__COEFFICIENT_1_MASK 0xfc000000
+#define PSX80_PIF0_LANE1_OVRD2__COEFFICIENT_1__SHIFT 0x1a
+#define PSX80_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK 0x1
+#define PSX80_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT 0x0
+#define PSX80_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2
+#define PSX80_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT 0x1
+#define PSX80_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK 0x4
+#define PSX80_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2
+#define PSX80_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK 0x8
+#define PSX80_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT 0x3
+#define PSX80_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK 0x10
+#define PSX80_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT 0x4
+#define PSX80_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK 0x20
+#define PSX80_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT 0x5
+#define PSX80_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK 0x40
+#define PSX80_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT 0x6
+#define PSX80_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK 0x80
+#define PSX80_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT 0x7
+#define PSX80_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK 0x100
+#define PSX80_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT 0x8
+#define PSX80_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK 0x200
+#define PSX80_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT 0x9
+#define PSX80_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK 0x400
+#define PSX80_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT 0xa
+#define PSX80_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK 0x800
+#define PSX80_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT 0xb
+#define PSX80_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK 0x1000
+#define PSX80_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT 0xc
+#define PSX80_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK 0x2000
+#define PSX80_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT 0xd
+#define PSX80_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK 0x4000
+#define PSX80_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT 0xe
+#define PSX80_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK 0x8000
+#define PSX80_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT 0xf
+#define PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2_MASK 0x10000
+#define PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT 0x10
+#define PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK 0x20000
+#define PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT 0x11
+#define PSX80_PIF0_LANE2_OVRD2__GANGMODE_2_MASK 0x7
+#define PSX80_PIF0_LANE2_OVRD2__GANGMODE_2__SHIFT 0x0
+#define PSX80_PIF0_LANE2_OVRD2__FREQDIV_2_MASK 0x18
+#define PSX80_PIF0_LANE2_OVRD2__FREQDIV_2__SHIFT 0x3
+#define PSX80_PIF0_LANE2_OVRD2__LINKSPEED_2_MASK 0x60
+#define PSX80_PIF0_LANE2_OVRD2__LINKSPEED_2__SHIFT 0x5
+#define PSX80_PIF0_LANE2_OVRD2__TWOSYMENABLE_2_MASK 0x80
+#define PSX80_PIF0_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT 0x7
+#define PSX80_PIF0_LANE2_OVRD2__TXPWR_2_MASK 0x700
+#define PSX80_PIF0_LANE2_OVRD2__TXPWR_2__SHIFT 0x8
+#define PSX80_PIF0_LANE2_OVRD2__TXPGENABLE_2_MASK 0x1800
+#define PSX80_PIF0_LANE2_OVRD2__TXPGENABLE_2__SHIFT 0xb
+#define PSX80_PIF0_LANE2_OVRD2__RXPWR_2_MASK 0xe000
+#define PSX80_PIF0_LANE2_OVRD2__RXPWR_2__SHIFT 0xd
+#define PSX80_PIF0_LANE2_OVRD2__RXPGENABLE_2_MASK 0x30000
+#define PSX80_PIF0_LANE2_OVRD2__RXPGENABLE_2__SHIFT 0x10
+#define PSX80_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2_MASK 0x40000
+#define PSX80_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT 0x12
+#define PSX80_PIF0_LANE2_OVRD2__ENABLEFOM_2_MASK 0x80000
+#define PSX80_PIF0_LANE2_OVRD2__ENABLEFOM_2__SHIFT 0x13
+#define PSX80_PIF0_LANE2_OVRD2__REQUESTFOM_2_MASK 0x100000
+#define PSX80_PIF0_LANE2_OVRD2__REQUESTFOM_2__SHIFT 0x14
+#define PSX80_PIF0_LANE2_OVRD2__RESPONSEMODE_2_MASK 0x200000
+#define PSX80_PIF0_LANE2_OVRD2__RESPONSEMODE_2__SHIFT 0x15
+#define PSX80_PIF0_LANE2_OVRD2__REQUESTTRK_2_MASK 0x400000
+#define PSX80_PIF0_LANE2_OVRD2__REQUESTTRK_2__SHIFT 0x16
+#define PSX80_PIF0_LANE2_OVRD2__REQUESTTRN_2_MASK 0x800000
+#define PSX80_PIF0_LANE2_OVRD2__REQUESTTRN_2__SHIFT 0x17
+#define PSX80_PIF0_LANE2_OVRD2__COEFFICIENTID_2_MASK 0x3000000
+#define PSX80_PIF0_LANE2_OVRD2__COEFFICIENTID_2__SHIFT 0x18
+#define PSX80_PIF0_LANE2_OVRD2__COEFFICIENT_2_MASK 0xfc000000
+#define PSX80_PIF0_LANE2_OVRD2__COEFFICIENT_2__SHIFT 0x1a
+#define PSX80_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK 0x1
+#define PSX80_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT 0x0
+#define PSX80_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2
+#define PSX80_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT 0x1
+#define PSX80_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK 0x4
+#define PSX80_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2
+#define PSX80_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK 0x8
+#define PSX80_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT 0x3
+#define PSX80_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK 0x10
+#define PSX80_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT 0x4
+#define PSX80_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK 0x20
+#define PSX80_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT 0x5
+#define PSX80_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK 0x40
+#define PSX80_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT 0x6
+#define PSX80_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK 0x80
+#define PSX80_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT 0x7
+#define PSX80_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK 0x100
+#define PSX80_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT 0x8
+#define PSX80_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK 0x200
+#define PSX80_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT 0x9
+#define PSX80_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK 0x400
+#define PSX80_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT 0xa
+#define PSX80_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK 0x800
+#define PSX80_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT 0xb
+#define PSX80_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK 0x1000
+#define PSX80_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT 0xc
+#define PSX80_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK 0x2000
+#define PSX80_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT 0xd
+#define PSX80_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK 0x4000
+#define PSX80_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT 0xe
+#define PSX80_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK 0x8000
+#define PSX80_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT 0xf
+#define PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3_MASK 0x10000
+#define PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT 0x10
+#define PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK 0x20000
+#define PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT 0x11
+#define PSX80_PIF0_LANE3_OVRD2__GANGMODE_3_MASK 0x7
+#define PSX80_PIF0_LANE3_OVRD2__GANGMODE_3__SHIFT 0x0
+#define PSX80_PIF0_LANE3_OVRD2__FREQDIV_3_MASK 0x18
+#define PSX80_PIF0_LANE3_OVRD2__FREQDIV_3__SHIFT 0x3
+#define PSX80_PIF0_LANE3_OVRD2__LINKSPEED_3_MASK 0x60
+#define PSX80_PIF0_LANE3_OVRD2__LINKSPEED_3__SHIFT 0x5
+#define PSX80_PIF0_LANE3_OVRD2__TWOSYMENABLE_3_MASK 0x80
+#define PSX80_PIF0_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT 0x7
+#define PSX80_PIF0_LANE3_OVRD2__TXPWR_3_MASK 0x700
+#define PSX80_PIF0_LANE3_OVRD2__TXPWR_3__SHIFT 0x8
+#define PSX80_PIF0_LANE3_OVRD2__TXPGENABLE_3_MASK 0x1800
+#define PSX80_PIF0_LANE3_OVRD2__TXPGENABLE_3__SHIFT 0xb
+#define PSX80_PIF0_LANE3_OVRD2__RXPWR_3_MASK 0xe000
+#define PSX80_PIF0_LANE3_OVRD2__RXPWR_3__SHIFT 0xd
+#define PSX80_PIF0_LANE3_OVRD2__RXPGENABLE_3_MASK 0x30000
+#define PSX80_PIF0_LANE3_OVRD2__RXPGENABLE_3__SHIFT 0x10
+#define PSX80_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3_MASK 0x40000
+#define PSX80_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT 0x12
+#define PSX80_PIF0_LANE3_OVRD2__ENABLEFOM_3_MASK 0x80000
+#define PSX80_PIF0_LANE3_OVRD2__ENABLEFOM_3__SHIFT 0x13
+#define PSX80_PIF0_LANE3_OVRD2__REQUESTFOM_3_MASK 0x100000
+#define PSX80_PIF0_LANE3_OVRD2__REQUESTFOM_3__SHIFT 0x14
+#define PSX80_PIF0_LANE3_OVRD2__RESPONSEMODE_3_MASK 0x200000
+#define PSX80_PIF0_LANE3_OVRD2__RESPONSEMODE_3__SHIFT 0x15
+#define PSX80_PIF0_LANE3_OVRD2__REQUESTTRK_3_MASK 0x400000
+#define PSX80_PIF0_LANE3_OVRD2__REQUESTTRK_3__SHIFT 0x16
+#define PSX80_PIF0_LANE3_OVRD2__REQUESTTRN_3_MASK 0x800000
+#define PSX80_PIF0_LANE3_OVRD2__REQUESTTRN_3__SHIFT 0x17
+#define PSX80_PIF0_LANE3_OVRD2__COEFFICIENTID_3_MASK 0x3000000
+#define PSX80_PIF0_LANE3_OVRD2__COEFFICIENTID_3__SHIFT 0x18
+#define PSX80_PIF0_LANE3_OVRD2__COEFFICIENT_3_MASK 0xfc000000
+#define PSX80_PIF0_LANE3_OVRD2__COEFFICIENT_3__SHIFT 0x1a
+#define PSX80_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK 0x1
+#define PSX80_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT 0x0
+#define PSX80_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2
+#define PSX80_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT 0x1
+#define PSX80_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK 0x4
+#define PSX80_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2
+#define PSX80_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK 0x8
+#define PSX80_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT 0x3
+#define PSX80_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK 0x10
+#define PSX80_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT 0x4
+#define PSX80_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK 0x20
+#define PSX80_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT 0x5
+#define PSX80_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK 0x40
+#define PSX80_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT 0x6
+#define PSX80_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK 0x80
+#define PSX80_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT 0x7
+#define PSX80_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK 0x100
+#define PSX80_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT 0x8
+#define PSX80_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK 0x200
+#define PSX80_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT 0x9
+#define PSX80_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK 0x400
+#define PSX80_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT 0xa
+#define PSX80_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK 0x800
+#define PSX80_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT 0xb
+#define PSX80_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK 0x1000
+#define PSX80_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT 0xc
+#define PSX80_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK 0x2000
+#define PSX80_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT 0xd
+#define PSX80_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK 0x4000
+#define PSX80_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT 0xe
+#define PSX80_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK 0x8000
+#define PSX80_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT 0xf
+#define PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4_MASK 0x10000
+#define PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT 0x10
+#define PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK 0x20000
+#define PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT 0x11
+#define PSX80_PIF0_LANE4_OVRD2__GANGMODE_4_MASK 0x7
+#define PSX80_PIF0_LANE4_OVRD2__GANGMODE_4__SHIFT 0x0
+#define PSX80_PIF0_LANE4_OVRD2__FREQDIV_4_MASK 0x18
+#define PSX80_PIF0_LANE4_OVRD2__FREQDIV_4__SHIFT 0x3
+#define PSX80_PIF0_LANE4_OVRD2__LINKSPEED_4_MASK 0x60
+#define PSX80_PIF0_LANE4_OVRD2__LINKSPEED_4__SHIFT 0x5
+#define PSX80_PIF0_LANE4_OVRD2__TWOSYMENABLE_4_MASK 0x80
+#define PSX80_PIF0_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT 0x7
+#define PSX80_PIF0_LANE4_OVRD2__TXPWR_4_MASK 0x700
+#define PSX80_PIF0_LANE4_OVRD2__TXPWR_4__SHIFT 0x8
+#define PSX80_PIF0_LANE4_OVRD2__TXPGENABLE_4_MASK 0x1800
+#define PSX80_PIF0_LANE4_OVRD2__TXPGENABLE_4__SHIFT 0xb
+#define PSX80_PIF0_LANE4_OVRD2__RXPWR_4_MASK 0xe000
+#define PSX80_PIF0_LANE4_OVRD2__RXPWR_4__SHIFT 0xd
+#define PSX80_PIF0_LANE4_OVRD2__RXPGENABLE_4_MASK 0x30000
+#define PSX80_PIF0_LANE4_OVRD2__RXPGENABLE_4__SHIFT 0x10
+#define PSX80_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4_MASK 0x40000
+#define PSX80_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT 0x12
+#define PSX80_PIF0_LANE4_OVRD2__ENABLEFOM_4_MASK 0x80000
+#define PSX80_PIF0_LANE4_OVRD2__ENABLEFOM_4__SHIFT 0x13
+#define PSX80_PIF0_LANE4_OVRD2__REQUESTFOM_4_MASK 0x100000
+#define PSX80_PIF0_LANE4_OVRD2__REQUESTFOM_4__SHIFT 0x14
+#define PSX80_PIF0_LANE4_OVRD2__RESPONSEMODE_4_MASK 0x200000
+#define PSX80_PIF0_LANE4_OVRD2__RESPONSEMODE_4__SHIFT 0x15
+#define PSX80_PIF0_LANE4_OVRD2__REQUESTTRK_4_MASK 0x400000
+#define PSX80_PIF0_LANE4_OVRD2__REQUESTTRK_4__SHIFT 0x16
+#define PSX80_PIF0_LANE4_OVRD2__REQUESTTRN_4_MASK 0x800000
+#define PSX80_PIF0_LANE4_OVRD2__REQUESTTRN_4__SHIFT 0x17
+#define PSX80_PIF0_LANE4_OVRD2__COEFFICIENTID_4_MASK 0x3000000
+#define PSX80_PIF0_LANE4_OVRD2__COEFFICIENTID_4__SHIFT 0x18
+#define PSX80_PIF0_LANE4_OVRD2__COEFFICIENT_4_MASK 0xfc000000
+#define PSX80_PIF0_LANE4_OVRD2__COEFFICIENT_4__SHIFT 0x1a
+#define PSX80_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK 0x1
+#define PSX80_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT 0x0
+#define PSX80_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2
+#define PSX80_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT 0x1
+#define PSX80_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK 0x4
+#define PSX80_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2
+#define PSX80_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK 0x8
+#define PSX80_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT 0x3
+#define PSX80_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK 0x10
+#define PSX80_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT 0x4
+#define PSX80_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK 0x20
+#define PSX80_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT 0x5
+#define PSX80_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK 0x40
+#define PSX80_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT 0x6
+#define PSX80_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK 0x80
+#define PSX80_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT 0x7
+#define PSX80_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK 0x100
+#define PSX80_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT 0x8
+#define PSX80_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK 0x200
+#define PSX80_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT 0x9
+#define PSX80_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK 0x400
+#define PSX80_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT 0xa
+#define PSX80_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK 0x800
+#define PSX80_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT 0xb
+#define PSX80_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK 0x1000
+#define PSX80_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT 0xc
+#define PSX80_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK 0x2000
+#define PSX80_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT 0xd
+#define PSX80_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK 0x4000
+#define PSX80_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT 0xe
+#define PSX80_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK 0x8000
+#define PSX80_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT 0xf
+#define PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5_MASK 0x10000
+#define PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT 0x10
+#define PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK 0x20000
+#define PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT 0x11
+#define PSX80_PIF0_LANE5_OVRD2__GANGMODE_5_MASK 0x7
+#define PSX80_PIF0_LANE5_OVRD2__GANGMODE_5__SHIFT 0x0
+#define PSX80_PIF0_LANE5_OVRD2__FREQDIV_5_MASK 0x18
+#define PSX80_PIF0_LANE5_OVRD2__FREQDIV_5__SHIFT 0x3
+#define PSX80_PIF0_LANE5_OVRD2__LINKSPEED_5_MASK 0x60
+#define PSX80_PIF0_LANE5_OVRD2__LINKSPEED_5__SHIFT 0x5
+#define PSX80_PIF0_LANE5_OVRD2__TWOSYMENABLE_5_MASK 0x80
+#define PSX80_PIF0_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT 0x7
+#define PSX80_PIF0_LANE5_OVRD2__TXPWR_5_MASK 0x700
+#define PSX80_PIF0_LANE5_OVRD2__TXPWR_5__SHIFT 0x8
+#define PSX80_PIF0_LANE5_OVRD2__TXPGENABLE_5_MASK 0x1800
+#define PSX80_PIF0_LANE5_OVRD2__TXPGENABLE_5__SHIFT 0xb
+#define PSX80_PIF0_LANE5_OVRD2__RXPWR_5_MASK 0xe000
+#define PSX80_PIF0_LANE5_OVRD2__RXPWR_5__SHIFT 0xd
+#define PSX80_PIF0_LANE5_OVRD2__RXPGENABLE_5_MASK 0x30000
+#define PSX80_PIF0_LANE5_OVRD2__RXPGENABLE_5__SHIFT 0x10
+#define PSX80_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5_MASK 0x40000
+#define PSX80_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT 0x12
+#define PSX80_PIF0_LANE5_OVRD2__ENABLEFOM_5_MASK 0x80000
+#define PSX80_PIF0_LANE5_OVRD2__ENABLEFOM_5__SHIFT 0x13
+#define PSX80_PIF0_LANE5_OVRD2__REQUESTFOM_5_MASK 0x100000
+#define PSX80_PIF0_LANE5_OVRD2__REQUESTFOM_5__SHIFT 0x14
+#define PSX80_PIF0_LANE5_OVRD2__RESPONSEMODE_5_MASK 0x200000
+#define PSX80_PIF0_LANE5_OVRD2__RESPONSEMODE_5__SHIFT 0x15
+#define PSX80_PIF0_LANE5_OVRD2__REQUESTTRK_5_MASK 0x400000
+#define PSX80_PIF0_LANE5_OVRD2__REQUESTTRK_5__SHIFT 0x16
+#define PSX80_PIF0_LANE5_OVRD2__REQUESTTRN_5_MASK 0x800000
+#define PSX80_PIF0_LANE5_OVRD2__REQUESTTRN_5__SHIFT 0x17
+#define PSX80_PIF0_LANE5_OVRD2__COEFFICIENTID_5_MASK 0x3000000
+#define PSX80_PIF0_LANE5_OVRD2__COEFFICIENTID_5__SHIFT 0x18
+#define PSX80_PIF0_LANE5_OVRD2__COEFFICIENT_5_MASK 0xfc000000
+#define PSX80_PIF0_LANE5_OVRD2__COEFFICIENT_5__SHIFT 0x1a
+#define PSX80_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK 0x1
+#define PSX80_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT 0x0
+#define PSX80_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2
+#define PSX80_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT 0x1
+#define PSX80_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK 0x4
+#define PSX80_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2
+#define PSX80_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK 0x8
+#define PSX80_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT 0x3
+#define PSX80_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK 0x10
+#define PSX80_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT 0x4
+#define PSX80_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK 0x20
+#define PSX80_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT 0x5
+#define PSX80_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK 0x40
+#define PSX80_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT 0x6
+#define PSX80_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK 0x80
+#define PSX80_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT 0x7
+#define PSX80_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK 0x100
+#define PSX80_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT 0x8
+#define PSX80_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK 0x200
+#define PSX80_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT 0x9
+#define PSX80_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK 0x400
+#define PSX80_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT 0xa
+#define PSX80_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK 0x800
+#define PSX80_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT 0xb
+#define PSX80_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK 0x1000
+#define PSX80_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT 0xc
+#define PSX80_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK 0x2000
+#define PSX80_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT 0xd
+#define PSX80_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK 0x4000
+#define PSX80_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT 0xe
+#define PSX80_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK 0x8000
+#define PSX80_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT 0xf
+#define PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6_MASK 0x10000
+#define PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT 0x10
+#define PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK 0x20000
+#define PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT 0x11
+#define PSX80_PIF0_LANE6_OVRD2__GANGMODE_6_MASK 0x7
+#define PSX80_PIF0_LANE6_OVRD2__GANGMODE_6__SHIFT 0x0
+#define PSX80_PIF0_LANE6_OVRD2__FREQDIV_6_MASK 0x18
+#define PSX80_PIF0_LANE6_OVRD2__FREQDIV_6__SHIFT 0x3
+#define PSX80_PIF0_LANE6_OVRD2__LINKSPEED_6_MASK 0x60
+#define PSX80_PIF0_LANE6_OVRD2__LINKSPEED_6__SHIFT 0x5
+#define PSX80_PIF0_LANE6_OVRD2__TWOSYMENABLE_6_MASK 0x80
+#define PSX80_PIF0_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT 0x7
+#define PSX80_PIF0_LANE6_OVRD2__TXPWR_6_MASK 0x700
+#define PSX80_PIF0_LANE6_OVRD2__TXPWR_6__SHIFT 0x8
+#define PSX80_PIF0_LANE6_OVRD2__TXPGENABLE_6_MASK 0x1800
+#define PSX80_PIF0_LANE6_OVRD2__TXPGENABLE_6__SHIFT 0xb
+#define PSX80_PIF0_LANE6_OVRD2__RXPWR_6_MASK 0xe000
+#define PSX80_PIF0_LANE6_OVRD2__RXPWR_6__SHIFT 0xd
+#define PSX80_PIF0_LANE6_OVRD2__RXPGENABLE_6_MASK 0x30000
+#define PSX80_PIF0_LANE6_OVRD2__RXPGENABLE_6__SHIFT 0x10
+#define PSX80_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6_MASK 0x40000
+#define PSX80_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT 0x12
+#define PSX80_PIF0_LANE6_OVRD2__ENABLEFOM_6_MASK 0x80000
+#define PSX80_PIF0_LANE6_OVRD2__ENABLEFOM_6__SHIFT 0x13
+#define PSX80_PIF0_LANE6_OVRD2__REQUESTFOM_6_MASK 0x100000
+#define PSX80_PIF0_LANE6_OVRD2__REQUESTFOM_6__SHIFT 0x14
+#define PSX80_PIF0_LANE6_OVRD2__RESPONSEMODE_6_MASK 0x200000
+#define PSX80_PIF0_LANE6_OVRD2__RESPONSEMODE_6__SHIFT 0x15
+#define PSX80_PIF0_LANE6_OVRD2__REQUESTTRK_6_MASK 0x400000
+#define PSX80_PIF0_LANE6_OVRD2__REQUESTTRK_6__SHIFT 0x16
+#define PSX80_PIF0_LANE6_OVRD2__REQUESTTRN_6_MASK 0x800000
+#define PSX80_PIF0_LANE6_OVRD2__REQUESTTRN_6__SHIFT 0x17
+#define PSX80_PIF0_LANE6_OVRD2__COEFFICIENTID_6_MASK 0x3000000
+#define PSX80_PIF0_LANE6_OVRD2__COEFFICIENTID_6__SHIFT 0x18
+#define PSX80_PIF0_LANE6_OVRD2__COEFFICIENT_6_MASK 0xfc000000
+#define PSX80_PIF0_LANE6_OVRD2__COEFFICIENT_6__SHIFT 0x1a
+#define PSX80_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK 0x1
+#define PSX80_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT 0x0
+#define PSX80_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK 0x2
+#define PSX80_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT 0x1
+#define PSX80_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK 0x4
+#define PSX80_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT 0x2
+#define PSX80_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK 0x8
+#define PSX80_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT 0x3
+#define PSX80_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK 0x10
+#define PSX80_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT 0x4
+#define PSX80_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK 0x20
+#define PSX80_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT 0x5
+#define PSX80_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK 0x40
+#define PSX80_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT 0x6
+#define PSX80_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK 0x80
+#define PSX80_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT 0x7
+#define PSX80_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK 0x100
+#define PSX80_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT 0x8
+#define PSX80_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK 0x200
+#define PSX80_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT 0x9
+#define PSX80_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK 0x400
+#define PSX80_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT 0xa
+#define PSX80_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK 0x800
+#define PSX80_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT 0xb
+#define PSX80_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK 0x1000
+#define PSX80_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT 0xc
+#define PSX80_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK 0x2000
+#define PSX80_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT 0xd
+#define PSX80_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK 0x4000
+#define PSX80_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT 0xe
+#define PSX80_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK 0x8000
+#define PSX80_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT 0xf
+#define PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7_MASK 0x10000
+#define PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT 0x10
+#define PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK 0x20000
+#define PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT 0x11
+#define PSX80_PIF0_LANE7_OVRD2__GANGMODE_7_MASK 0x7
+#define PSX80_PIF0_LANE7_OVRD2__GANGMODE_7__SHIFT 0x0
+#define PSX80_PIF0_LANE7_OVRD2__FREQDIV_7_MASK 0x18
+#define PSX80_PIF0_LANE7_OVRD2__FREQDIV_7__SHIFT 0x3
+#define PSX80_PIF0_LANE7_OVRD2__LINKSPEED_7_MASK 0x60
+#define PSX80_PIF0_LANE7_OVRD2__LINKSPEED_7__SHIFT 0x5
+#define PSX80_PIF0_LANE7_OVRD2__TWOSYMENABLE_7_MASK 0x80
+#define PSX80_PIF0_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT 0x7
+#define PSX80_PIF0_LANE7_OVRD2__TXPWR_7_MASK 0x700
+#define PSX80_PIF0_LANE7_OVRD2__TXPWR_7__SHIFT 0x8
+#define PSX80_PIF0_LANE7_OVRD2__TXPGENABLE_7_MASK 0x1800
+#define PSX80_PIF0_LANE7_OVRD2__TXPGENABLE_7__SHIFT 0xb
+#define PSX80_PIF0_LANE7_OVRD2__RXPWR_7_MASK 0xe000
+#define PSX80_PIF0_LANE7_OVRD2__RXPWR_7__SHIFT 0xd
+#define PSX80_PIF0_LANE7_OVRD2__RXPGENABLE_7_MASK 0x30000
+#define PSX80_PIF0_LANE7_OVRD2__RXPGENABLE_7__SHIFT 0x10
+#define PSX80_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7_MASK 0x40000
+#define PSX80_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT 0x12
+#define PSX80_PIF0_LANE7_OVRD2__ENABLEFOM_7_MASK 0x80000
+#define PSX80_PIF0_LANE7_OVRD2__ENABLEFOM_7__SHIFT 0x13
+#define PSX80_PIF0_LANE7_OVRD2__REQUESTFOM_7_MASK 0x100000
+#define PSX80_PIF0_LANE7_OVRD2__REQUESTFOM_7__SHIFT 0x14
+#define PSX80_PIF0_LANE7_OVRD2__RESPONSEMODE_7_MASK 0x200000
+#define PSX80_PIF0_LANE7_OVRD2__RESPONSEMODE_7__SHIFT 0x15
+#define PSX80_PIF0_LANE7_OVRD2__REQUESTTRK_7_MASK 0x400000
+#define PSX80_PIF0_LANE7_OVRD2__REQUESTTRK_7__SHIFT 0x16
+#define PSX80_PIF0_LANE7_OVRD2__REQUESTTRN_7_MASK 0x800000
+#define PSX80_PIF0_LANE7_OVRD2__REQUESTTRN_7__SHIFT 0x17
+#define PSX80_PIF0_LANE7_OVRD2__COEFFICIENTID_7_MASK 0x3000000
+#define PSX80_PIF0_LANE7_OVRD2__COEFFICIENTID_7__SHIFT 0x18
+#define PSX80_PIF0_LANE7_OVRD2__COEFFICIENT_7_MASK 0xfc000000
+#define PSX80_PIF0_LANE7_OVRD2__COEFFICIENT_7__SHIFT 0x1a
+#define PSX81_PIF0_SCRATCH__PIF_SCRATCH_MASK 0xffffffff
+#define PSX81_PIF0_SCRATCH__PIF_SCRATCH__SHIFT 0x0
+#define PSX81_PIF0_HW_DEBUG__HW_00_DEBUG_MASK 0x1
+#define PSX81_PIF0_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
+#define PSX81_PIF0_HW_DEBUG__HW_01_DEBUG_MASK 0x2
+#define PSX81_PIF0_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
+#define PSX81_PIF0_HW_DEBUG__HW_02_DEBUG_MASK 0x4
+#define PSX81_PIF0_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
+#define PSX81_PIF0_HW_DEBUG__HW_03_DEBUG_MASK 0x8
+#define PSX81_PIF0_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
+#define PSX81_PIF0_HW_DEBUG__HW_04_DEBUG_MASK 0x10
+#define PSX81_PIF0_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
+#define PSX81_PIF0_HW_DEBUG__HW_05_DEBUG_MASK 0x20
+#define PSX81_PIF0_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
+#define PSX81_PIF0_HW_DEBUG__HW_06_DEBUG_MASK 0x40
+#define PSX81_PIF0_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
+#define PSX81_PIF0_HW_DEBUG__HW_07_DEBUG_MASK 0x80
+#define PSX81_PIF0_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
+#define PSX81_PIF0_HW_DEBUG__HW_08_DEBUG_MASK 0x100
+#define PSX81_PIF0_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
+#define PSX81_PIF0_HW_DEBUG__HW_09_DEBUG_MASK 0x200
+#define PSX81_PIF0_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
+#define PSX81_PIF0_HW_DEBUG__HW_10_DEBUG_MASK 0x400
+#define PSX81_PIF0_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
+#define PSX81_PIF0_HW_DEBUG__HW_11_DEBUG_MASK 0x800
+#define PSX81_PIF0_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
+#define PSX81_PIF0_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
+#define PSX81_PIF0_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
+#define PSX81_PIF0_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
+#define PSX81_PIF0_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
+#define PSX81_PIF0_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
+#define PSX81_PIF0_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
+#define PSX81_PIF0_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
+#define PSX81_PIF0_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
+#define PSX81_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2
+#define PSX81_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT 0x1
+#define PSX81_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK 0x4
+#define PSX81_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2
+#define PSX81_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK 0x8
+#define PSX81_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT 0x3
+#define PSX81_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK 0x10
+#define PSX81_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT 0x4
+#define PSX81_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK 0x20
+#define PSX81_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT 0x5
+#define PSX81_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK 0xc0
+#define PSX81_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT 0x6
+#define PSX81_PIF0_STRAP_0__STRAP_RX_EI_FILTER_MASK 0x300
+#define PSX81_PIF0_STRAP_0__STRAP_RX_EI_FILTER__SHIFT 0x8
+#define PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK 0x400
+#define PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT 0xa
+#define PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK 0x800
+#define PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT 0xb
+#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_12_MASK 0x1000
+#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_12__SHIFT 0xc
+#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_13_MASK 0x2000
+#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_13__SHIFT 0xd
+#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_14_MASK 0x4000
+#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_14__SHIFT 0xe
+#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_15_MASK 0x8000
+#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_15__SHIFT 0xf
+#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_16_MASK 0x10000
+#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_16__SHIFT 0x10
+#define PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EN_MASK 0x1
+#define PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EN__SHIFT 0x0
+#define PSX81_PIF0_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2
+#define PSX81_PIF0_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT 0x1
+#define PSX81_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK 0x4
+#define PSX81_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2
+#define PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK 0x8
+#define PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT 0x3
+#define PSX81_PIF0_CTRL__PHY_RST_PWROK_VDD_MASK 0x10
+#define PSX81_PIF0_CTRL__PHY_RST_PWROK_VDD__SHIFT 0x4
+#define PSX81_PIF0_CTRL__PIF_PLL_STATUS_MASK 0xc0
+#define PSX81_PIF0_CTRL__PIF_PLL_STATUS__SHIFT 0x6
+#define PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK 0x100
+#define PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT 0x8
+#define PSX81_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK 0x200
+#define PSX81_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT 0x9
+#define PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK 0x400
+#define PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT 0xa
+#define PSX81_PIF0_CTRL__PIF_PG_EXIT_MODE_MASK 0x800
+#define PSX81_PIF0_CTRL__PIF_PG_EXIT_MODE__SHIFT 0xb
+#define PSX81_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK 0x1000
+#define PSX81_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT 0xc
+#define PSX81_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK 0x2000
+#define PSX81_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT 0xd
+#define PSX81_PIF0_CTRL__PIF_PG_ABORT_DISABLE_MASK 0x4000
+#define PSX81_PIF0_CTRL__PIF_PG_ABORT_DISABLE__SHIFT 0xe
+#define PSX81_PIF0_TX_CTRL__TXPWR_IN_S2_MASK 0x7
+#define PSX81_PIF0_TX_CTRL__TXPWR_IN_S2__SHIFT 0x0
+#define PSX81_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG_MASK 0x38
+#define PSX81_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT 0x3
+#define PSX81_PIF0_TX_CTRL__TXPWR_IN_OFF_MASK 0x1c0
+#define PSX81_PIF0_TX_CTRL__TXPWR_IN_OFF__SHIFT 0x6
+#define PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MASK 0xe00
+#define PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT 0x9
+#define PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MASK 0x7000
+#define PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED__SHIFT 0xc
+#define PSX81_PIF0_TX_CTRL__TXPWR_IN_INIT_MASK 0x38000
+#define PSX81_PIF0_TX_CTRL__TXPWR_IN_INIT__SHIFT 0xf
+#define PSX81_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF_MASK 0x1c0000
+#define PSX81_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT 0x12
+#define PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK 0x200000
+#define PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT 0x15
+#define PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK 0x400000
+#define PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT 0x16
+#define PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_L1_MASK 0x800000
+#define PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT 0x17
+#define PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK 0x1000000
+#define PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT 0x18
+#define PSX81_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK 0x7
+#define PSX81_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT 0x0
+#define PSX81_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK 0x38
+#define PSX81_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT 0x3
+#define PSX81_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY_MASK 0x1c0
+#define PSX81_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT 0x6
+#define PSX81_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK 0x200
+#define PSX81_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9
+#define PSX81_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK 0x400
+#define PSX81_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa
+#define PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK 0x10000
+#define PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT 0x10
+#define PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK 0x60000
+#define PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT 0x11
+#define PSX81_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID_MASK 0x200000
+#define PSX81_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT 0x15
+#define PSX81_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK 0x1c00000
+#define PSX81_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT 0x16
+#define PSX81_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK 0x2000000
+#define PSX81_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT 0x19
+#define PSX81_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK 0x1c000000
+#define PSX81_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT 0x1a
+#define PSX81_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK 0x20000000
+#define PSX81_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT 0x1d
+#define PSX81_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK 0x40000000
+#define PSX81_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT 0x1e
+#define PSX81_PIF0_RX_CTRL__RXPWR_IN_S2_MASK 0x7
+#define PSX81_PIF0_RX_CTRL__RXPWR_IN_S2__SHIFT 0x0
+#define PSX81_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG_MASK 0x38
+#define PSX81_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT 0x3
+#define PSX81_PIF0_RX_CTRL__RXPWR_IN_OFF_MASK 0x1c0
+#define PSX81_PIF0_RX_CTRL__RXPWR_IN_OFF__SHIFT 0x6
+#define PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MASK 0xe00
+#define PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT 0x9
+#define PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MASK 0x7000
+#define PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED__SHIFT 0xc
+#define PSX81_PIF0_RX_CTRL__RXPWR_IN_INIT_MASK 0x38000
+#define PSX81_PIF0_RX_CTRL__RXPWR_IN_INIT__SHIFT 0xf
+#define PSX81_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF_MASK 0x1c0000
+#define PSX81_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT 0x12
+#define PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK 0x200000
+#define PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT 0x15
+#define PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK 0x400000
+#define PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT 0x16
+#define PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_L1_MASK 0x800000
+#define PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT 0x17
+#define PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK 0x1000000
+#define PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT 0x18
+#define PSX81_PIF0_RX_CTRL__RX_HLD_EIE_COUNT_MASK 0x2000000
+#define PSX81_PIF0_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT 0x19
+#define PSX81_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK 0x4000000
+#define PSX81_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT 0x1a
+#define PSX81_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK 0x7
+#define PSX81_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT 0x0
+#define PSX81_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK 0x38
+#define PSX81_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT 0x3
+#define PSX81_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY_MASK 0x1c0
+#define PSX81_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT 0x6
+#define PSX81_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK 0x200
+#define PSX81_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9
+#define PSX81_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK 0x400
+#define PSX81_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa
+#define PSX81_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK 0x10000
+#define PSX81_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT 0x10
+#define PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE_MASK 0x60000
+#define PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT 0x11
+#define PSX81_PIF0_RX_CTRL2__EI_DET_ON_TIME_MASK 0x180000
+#define PSX81_PIF0_RX_CTRL2__EI_DET_ON_TIME__SHIFT 0x13
+#define PSX81_PIF0_RX_CTRL2__EI_DET_OFF_TIME_MASK 0xe00000
+#define PSX81_PIF0_RX_CTRL2__EI_DET_OFF_TIME__SHIFT 0x15
+#define PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK 0x1000000
+#define PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT 0x18
+#define PSX81_PIF0_RX_CTRL2__RX_CDR_XTND_MODE_MASK 0x6000000
+#define PSX81_PIF0_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT 0x19
+#define PSX81_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK 0x8000000
+#define PSX81_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT 0x1b
+#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK 0x1
+#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x0
+#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2
+#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x1
+#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK 0x4
+#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2
+#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK 0x8
+#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x3
+#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK 0x10
+#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x4
+#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK 0x20
+#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x5
+#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK 0x40
+#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x6
+#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK 0x80
+#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x7
+#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK 0x10000
+#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT 0x10
+#define PSX81_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK 0x1
+#define PSX81_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT 0x0
+#define PSX81_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2
+#define PSX81_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT 0x1
+#define PSX81_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK 0x4
+#define PSX81_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2
+#define PSX81_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK 0x8
+#define PSX81_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT 0x3
+#define PSX81_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK 0x10
+#define PSX81_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT 0x4
+#define PSX81_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK 0x20
+#define PSX81_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT 0x5
+#define PSX81_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK 0x40
+#define PSX81_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT 0x6
+#define PSX81_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK 0x80
+#define PSX81_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT 0x7
+#define PSX81_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK 0x100
+#define PSX81_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT 0x8
+#define PSX81_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK 0x200
+#define PSX81_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT 0x9
+#define PSX81_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK 0x400
+#define PSX81_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT 0xa
+#define PSX81_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK 0x800
+#define PSX81_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT 0xb
+#define PSX81_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK 0x10000
+#define PSX81_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT 0x10
+#define PSX81_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK 0x20000
+#define PSX81_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT 0x11
+#define PSX81_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK 0x100000
+#define PSX81_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT 0x14
+#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK 0x1
+#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT 0x0
+#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2
+#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT 0x1
+#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK 0x4
+#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2
+#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK 0x8
+#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT 0x3
+#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK 0x10
+#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT 0x4
+#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK 0x20
+#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT 0x5
+#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK 0x40
+#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT 0x6
+#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK 0x80
+#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT 0x7
+#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK 0x100
+#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT 0x8
+#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK 0x200
+#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT 0x9
+#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK 0x400
+#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT 0xa
+#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK 0x800
+#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT 0xb
+#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK 0x1000
+#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT 0xc
+#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK 0x2000
+#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT 0xd
+#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK 0x4000
+#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT 0xe
+#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK 0x8000
+#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT 0xf
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK 0x10000
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT 0x10
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK 0x20000
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT 0x11
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK 0x40000
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT 0x12
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK 0x80000
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT 0x13
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK 0x100000
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT 0x14
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK 0x200000
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT 0x15
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK 0x400000
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT 0x16
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK 0x800000
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT 0x17
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK 0x1000000
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT 0x18
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK 0x2000000
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT 0x19
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK 0x4000000
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT 0x1a
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK 0x8000000
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT 0x1b
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK 0x10000000
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT 0x1c
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK 0x20000000
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT 0x1d
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK 0x40000000
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT 0x1e
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK 0x80000000
+#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT 0x1f
+#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK 0x3
+#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT 0x0
+#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK 0xc
+#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2
+#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK 0x10
+#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT 0x4
+#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK 0x60
+#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT 0x5
+#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK 0x80
+#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT 0x7
+#define PSX81_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK 0x100
+#define PSX81_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT 0x8
+#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK 0x200
+#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT 0x9
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK 0x1
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT 0x0
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT 0x1
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK 0x4
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG_MASK 0x38
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG__SHIFT 0x3
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_MASK 0x40
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT 0x6
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_MASK 0x180
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT 0x7
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK 0x200
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT 0x9
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK 0x10000
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT 0x10
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK 0x20000
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT 0x11
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK 0x40000
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT 0x12
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK 0x80000
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT 0x13
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK 0x100000
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT 0x14
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK 0x200000
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT 0x15
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK 0x400000
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT 0x16
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK 0x800000
+#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT 0x17
+#define PSX81_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK 0x1
+#define PSX81_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT 0x0
+#define PSX81_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2
+#define PSX81_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT 0x1
+#define PSX81_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK 0x4
+#define PSX81_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2
+#define PSX81_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK 0x8
+#define PSX81_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT 0x3
+#define PSX81_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK 0x10
+#define PSX81_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT 0x4
+#define PSX81_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK 0x20
+#define PSX81_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT 0x5
+#define PSX81_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK 0x40
+#define PSX81_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT 0x6
+#define PSX81_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK 0x80
+#define PSX81_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT 0x7
+#define PSX81_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK 0x100
+#define PSX81_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT 0x8
+#define PSX81_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK 0x200
+#define PSX81_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT 0x9
+#define PSX81_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK 0x400
+#define PSX81_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT 0xa
+#define PSX81_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK 0x800
+#define PSX81_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT 0xb
+#define PSX81_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK 0x1000
+#define PSX81_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT 0xc
+#define PSX81_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK 0x2000
+#define PSX81_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT 0xd
+#define PSX81_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK 0x4000
+#define PSX81_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT 0xe
+#define PSX81_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK 0x8000
+#define PSX81_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT 0xf
+#define PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0_MASK 0x10000
+#define PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT 0x10
+#define PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK 0x20000
+#define PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT 0x11
+#define PSX81_PIF0_LANE0_OVRD2__GANGMODE_0_MASK 0x7
+#define PSX81_PIF0_LANE0_OVRD2__GANGMODE_0__SHIFT 0x0
+#define PSX81_PIF0_LANE0_OVRD2__FREQDIV_0_MASK 0x18
+#define PSX81_PIF0_LANE0_OVRD2__FREQDIV_0__SHIFT 0x3
+#define PSX81_PIF0_LANE0_OVRD2__LINKSPEED_0_MASK 0x60
+#define PSX81_PIF0_LANE0_OVRD2__LINKSPEED_0__SHIFT 0x5
+#define PSX81_PIF0_LANE0_OVRD2__TWOSYMENABLE_0_MASK 0x80
+#define PSX81_PIF0_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT 0x7
+#define PSX81_PIF0_LANE0_OVRD2__TXPWR_0_MASK 0x700
+#define PSX81_PIF0_LANE0_OVRD2__TXPWR_0__SHIFT 0x8
+#define PSX81_PIF0_LANE0_OVRD2__TXPGENABLE_0_MASK 0x1800
+#define PSX81_PIF0_LANE0_OVRD2__TXPGENABLE_0__SHIFT 0xb
+#define PSX81_PIF0_LANE0_OVRD2__RXPWR_0_MASK 0xe000
+#define PSX81_PIF0_LANE0_OVRD2__RXPWR_0__SHIFT 0xd
+#define PSX81_PIF0_LANE0_OVRD2__RXPGENABLE_0_MASK 0x30000
+#define PSX81_PIF0_LANE0_OVRD2__RXPGENABLE_0__SHIFT 0x10
+#define PSX81_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0_MASK 0x40000
+#define PSX81_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT 0x12
+#define PSX81_PIF0_LANE0_OVRD2__ENABLEFOM_0_MASK 0x80000
+#define PSX81_PIF0_LANE0_OVRD2__ENABLEFOM_0__SHIFT 0x13
+#define PSX81_PIF0_LANE0_OVRD2__REQUESTFOM_0_MASK 0x100000
+#define PSX81_PIF0_LANE0_OVRD2__REQUESTFOM_0__SHIFT 0x14
+#define PSX81_PIF0_LANE0_OVRD2__RESPONSEMODE_0_MASK 0x200000
+#define PSX81_PIF0_LANE0_OVRD2__RESPONSEMODE_0__SHIFT 0x15
+#define PSX81_PIF0_LANE0_OVRD2__REQUESTTRK_0_MASK 0x400000
+#define PSX81_PIF0_LANE0_OVRD2__REQUESTTRK_0__SHIFT 0x16
+#define PSX81_PIF0_LANE0_OVRD2__REQUESTTRN_0_MASK 0x800000
+#define PSX81_PIF0_LANE0_OVRD2__REQUESTTRN_0__SHIFT 0x17
+#define PSX81_PIF0_LANE0_OVRD2__COEFFICIENTID_0_MASK 0x3000000
+#define PSX81_PIF0_LANE0_OVRD2__COEFFICIENTID_0__SHIFT 0x18
+#define PSX81_PIF0_LANE0_OVRD2__COEFFICIENT_0_MASK 0xfc000000
+#define PSX81_PIF0_LANE0_OVRD2__COEFFICIENT_0__SHIFT 0x1a
+#define PSX81_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK 0x1
+#define PSX81_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT 0x0
+#define PSX81_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2
+#define PSX81_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT 0x1
+#define PSX81_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK 0x4
+#define PSX81_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2
+#define PSX81_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK 0x8
+#define PSX81_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT 0x3
+#define PSX81_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK 0x10
+#define PSX81_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT 0x4
+#define PSX81_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK 0x20
+#define PSX81_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT 0x5
+#define PSX81_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK 0x40
+#define PSX81_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT 0x6
+#define PSX81_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK 0x80
+#define PSX81_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT 0x7
+#define PSX81_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK 0x100
+#define PSX81_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT 0x8
+#define PSX81_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK 0x200
+#define PSX81_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT 0x9
+#define PSX81_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK 0x400
+#define PSX81_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT 0xa
+#define PSX81_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK 0x800
+#define PSX81_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT 0xb
+#define PSX81_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK 0x1000
+#define PSX81_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT 0xc
+#define PSX81_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK 0x2000
+#define PSX81_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT 0xd
+#define PSX81_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK 0x4000
+#define PSX81_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT 0xe
+#define PSX81_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK 0x8000
+#define PSX81_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT 0xf
+#define PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1_MASK 0x10000
+#define PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT 0x10
+#define PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK 0x20000
+#define PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT 0x11
+#define PSX81_PIF0_LANE1_OVRD2__GANGMODE_1_MASK 0x7
+#define PSX81_PIF0_LANE1_OVRD2__GANGMODE_1__SHIFT 0x0
+#define PSX81_PIF0_LANE1_OVRD2__FREQDIV_1_MASK 0x18
+#define PSX81_PIF0_LANE1_OVRD2__FREQDIV_1__SHIFT 0x3
+#define PSX81_PIF0_LANE1_OVRD2__LINKSPEED_1_MASK 0x60
+#define PSX81_PIF0_LANE1_OVRD2__LINKSPEED_1__SHIFT 0x5
+#define PSX81_PIF0_LANE1_OVRD2__TWOSYMENABLE_1_MASK 0x80
+#define PSX81_PIF0_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT 0x7
+#define PSX81_PIF0_LANE1_OVRD2__TXPWR_1_MASK 0x700
+#define PSX81_PIF0_LANE1_OVRD2__TXPWR_1__SHIFT 0x8
+#define PSX81_PIF0_LANE1_OVRD2__TXPGENABLE_1_MASK 0x1800
+#define PSX81_PIF0_LANE1_OVRD2__TXPGENABLE_1__SHIFT 0xb
+#define PSX81_PIF0_LANE1_OVRD2__RXPWR_1_MASK 0xe000
+#define PSX81_PIF0_LANE1_OVRD2__RXPWR_1__SHIFT 0xd
+#define PSX81_PIF0_LANE1_OVRD2__RXPGENABLE_1_MASK 0x30000
+#define PSX81_PIF0_LANE1_OVRD2__RXPGENABLE_1__SHIFT 0x10
+#define PSX81_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1_MASK 0x40000
+#define PSX81_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT 0x12
+#define PSX81_PIF0_LANE1_OVRD2__ENABLEFOM_1_MASK 0x80000
+#define PSX81_PIF0_LANE1_OVRD2__ENABLEFOM_1__SHIFT 0x13
+#define PSX81_PIF0_LANE1_OVRD2__REQUESTFOM_1_MASK 0x100000
+#define PSX81_PIF0_LANE1_OVRD2__REQUESTFOM_1__SHIFT 0x14
+#define PSX81_PIF0_LANE1_OVRD2__RESPONSEMODE_1_MASK 0x200000
+#define PSX81_PIF0_LANE1_OVRD2__RESPONSEMODE_1__SHIFT 0x15
+#define PSX81_PIF0_LANE1_OVRD2__REQUESTTRK_1_MASK 0x400000
+#define PSX81_PIF0_LANE1_OVRD2__REQUESTTRK_1__SHIFT 0x16
+#define PSX81_PIF0_LANE1_OVRD2__REQUESTTRN_1_MASK 0x800000
+#define PSX81_PIF0_LANE1_OVRD2__REQUESTTRN_1__SHIFT 0x17
+#define PSX81_PIF0_LANE1_OVRD2__COEFFICIENTID_1_MASK 0x3000000
+#define PSX81_PIF0_LANE1_OVRD2__COEFFICIENTID_1__SHIFT 0x18
+#define PSX81_PIF0_LANE1_OVRD2__COEFFICIENT_1_MASK 0xfc000000
+#define PSX81_PIF0_LANE1_OVRD2__COEFFICIENT_1__SHIFT 0x1a
+#define PSX81_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK 0x1
+#define PSX81_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT 0x0
+#define PSX81_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2
+#define PSX81_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT 0x1
+#define PSX81_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK 0x4
+#define PSX81_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2
+#define PSX81_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK 0x8
+#define PSX81_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT 0x3
+#define PSX81_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK 0x10
+#define PSX81_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT 0x4
+#define PSX81_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK 0x20
+#define PSX81_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT 0x5
+#define PSX81_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK 0x40
+#define PSX81_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT 0x6
+#define PSX81_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK 0x80
+#define PSX81_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT 0x7
+#define PSX81_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK 0x100
+#define PSX81_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT 0x8
+#define PSX81_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK 0x200
+#define PSX81_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT 0x9
+#define PSX81_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK 0x400
+#define PSX81_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT 0xa
+#define PSX81_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK 0x800
+#define PSX81_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT 0xb
+#define PSX81_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK 0x1000
+#define PSX81_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT 0xc
+#define PSX81_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK 0x2000
+#define PSX81_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT 0xd
+#define PSX81_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK 0x4000
+#define PSX81_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT 0xe
+#define PSX81_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK 0x8000
+#define PSX81_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT 0xf
+#define PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2_MASK 0x10000
+#define PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT 0x10
+#define PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK 0x20000
+#define PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT 0x11
+#define PSX81_PIF0_LANE2_OVRD2__GANGMODE_2_MASK 0x7
+#define PSX81_PIF0_LANE2_OVRD2__GANGMODE_2__SHIFT 0x0
+#define PSX81_PIF0_LANE2_OVRD2__FREQDIV_2_MASK 0x18
+#define PSX81_PIF0_LANE2_OVRD2__FREQDIV_2__SHIFT 0x3
+#define PSX81_PIF0_LANE2_OVRD2__LINKSPEED_2_MASK 0x60
+#define PSX81_PIF0_LANE2_OVRD2__LINKSPEED_2__SHIFT 0x5
+#define PSX81_PIF0_LANE2_OVRD2__TWOSYMENABLE_2_MASK 0x80
+#define PSX81_PIF0_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT 0x7
+#define PSX81_PIF0_LANE2_OVRD2__TXPWR_2_MASK 0x700
+#define PSX81_PIF0_LANE2_OVRD2__TXPWR_2__SHIFT 0x8
+#define PSX81_PIF0_LANE2_OVRD2__TXPGENABLE_2_MASK 0x1800
+#define PSX81_PIF0_LANE2_OVRD2__TXPGENABLE_2__SHIFT 0xb
+#define PSX81_PIF0_LANE2_OVRD2__RXPWR_2_MASK 0xe000
+#define PSX81_PIF0_LANE2_OVRD2__RXPWR_2__SHIFT 0xd
+#define PSX81_PIF0_LANE2_OVRD2__RXPGENABLE_2_MASK 0x30000
+#define PSX81_PIF0_LANE2_OVRD2__RXPGENABLE_2__SHIFT 0x10
+#define PSX81_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2_MASK 0x40000
+#define PSX81_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT 0x12
+#define PSX81_PIF0_LANE2_OVRD2__ENABLEFOM_2_MASK 0x80000
+#define PSX81_PIF0_LANE2_OVRD2__ENABLEFOM_2__SHIFT 0x13
+#define PSX81_PIF0_LANE2_OVRD2__REQUESTFOM_2_MASK 0x100000
+#define PSX81_PIF0_LANE2_OVRD2__REQUESTFOM_2__SHIFT 0x14
+#define PSX81_PIF0_LANE2_OVRD2__RESPONSEMODE_2_MASK 0x200000
+#define PSX81_PIF0_LANE2_OVRD2__RESPONSEMODE_2__SHIFT 0x15
+#define PSX81_PIF0_LANE2_OVRD2__REQUESTTRK_2_MASK 0x400000
+#define PSX81_PIF0_LANE2_OVRD2__REQUESTTRK_2__SHIFT 0x16
+#define PSX81_PIF0_LANE2_OVRD2__REQUESTTRN_2_MASK 0x800000
+#define PSX81_PIF0_LANE2_OVRD2__REQUESTTRN_2__SHIFT 0x17
+#define PSX81_PIF0_LANE2_OVRD2__COEFFICIENTID_2_MASK 0x3000000
+#define PSX81_PIF0_LANE2_OVRD2__COEFFICIENTID_2__SHIFT 0x18
+#define PSX81_PIF0_LANE2_OVRD2__COEFFICIENT_2_MASK 0xfc000000
+#define PSX81_PIF0_LANE2_OVRD2__COEFFICIENT_2__SHIFT 0x1a
+#define PSX81_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK 0x1
+#define PSX81_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT 0x0
+#define PSX81_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2
+#define PSX81_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT 0x1
+#define PSX81_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK 0x4
+#define PSX81_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2
+#define PSX81_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK 0x8
+#define PSX81_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT 0x3
+#define PSX81_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK 0x10
+#define PSX81_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT 0x4
+#define PSX81_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK 0x20
+#define PSX81_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT 0x5
+#define PSX81_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK 0x40
+#define PSX81_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT 0x6
+#define PSX81_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK 0x80
+#define PSX81_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT 0x7
+#define PSX81_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK 0x100
+#define PSX81_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT 0x8
+#define PSX81_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK 0x200
+#define PSX81_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT 0x9
+#define PSX81_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK 0x400
+#define PSX81_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT 0xa
+#define PSX81_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK 0x800
+#define PSX81_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT 0xb
+#define PSX81_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK 0x1000
+#define PSX81_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT 0xc
+#define PSX81_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK 0x2000
+#define PSX81_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT 0xd
+#define PSX81_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK 0x4000
+#define PSX81_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT 0xe
+#define PSX81_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK 0x8000
+#define PSX81_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT 0xf
+#define PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3_MASK 0x10000
+#define PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT 0x10
+#define PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK 0x20000
+#define PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT 0x11
+#define PSX81_PIF0_LANE3_OVRD2__GANGMODE_3_MASK 0x7
+#define PSX81_PIF0_LANE3_OVRD2__GANGMODE_3__SHIFT 0x0
+#define PSX81_PIF0_LANE3_OVRD2__FREQDIV_3_MASK 0x18
+#define PSX81_PIF0_LANE3_OVRD2__FREQDIV_3__SHIFT 0x3
+#define PSX81_PIF0_LANE3_OVRD2__LINKSPEED_3_MASK 0x60
+#define PSX81_PIF0_LANE3_OVRD2__LINKSPEED_3__SHIFT 0x5
+#define PSX81_PIF0_LANE3_OVRD2__TWOSYMENABLE_3_MASK 0x80
+#define PSX81_PIF0_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT 0x7
+#define PSX81_PIF0_LANE3_OVRD2__TXPWR_3_MASK 0x700
+#define PSX81_PIF0_LANE3_OVRD2__TXPWR_3__SHIFT 0x8
+#define PSX81_PIF0_LANE3_OVRD2__TXPGENABLE_3_MASK 0x1800
+#define PSX81_PIF0_LANE3_OVRD2__TXPGENABLE_3__SHIFT 0xb
+#define PSX81_PIF0_LANE3_OVRD2__RXPWR_3_MASK 0xe000
+#define PSX81_PIF0_LANE3_OVRD2__RXPWR_3__SHIFT 0xd
+#define PSX81_PIF0_LANE3_OVRD2__RXPGENABLE_3_MASK 0x30000
+#define PSX81_PIF0_LANE3_OVRD2__RXPGENABLE_3__SHIFT 0x10
+#define PSX81_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3_MASK 0x40000
+#define PSX81_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT 0x12
+#define PSX81_PIF0_LANE3_OVRD2__ENABLEFOM_3_MASK 0x80000
+#define PSX81_PIF0_LANE3_OVRD2__ENABLEFOM_3__SHIFT 0x13
+#define PSX81_PIF0_LANE3_OVRD2__REQUESTFOM_3_MASK 0x100000
+#define PSX81_PIF0_LANE3_OVRD2__REQUESTFOM_3__SHIFT 0x14
+#define PSX81_PIF0_LANE3_OVRD2__RESPONSEMODE_3_MASK 0x200000
+#define PSX81_PIF0_LANE3_OVRD2__RESPONSEMODE_3__SHIFT 0x15
+#define PSX81_PIF0_LANE3_OVRD2__REQUESTTRK_3_MASK 0x400000
+#define PSX81_PIF0_LANE3_OVRD2__REQUESTTRK_3__SHIFT 0x16
+#define PSX81_PIF0_LANE3_OVRD2__REQUESTTRN_3_MASK 0x800000
+#define PSX81_PIF0_LANE3_OVRD2__REQUESTTRN_3__SHIFT 0x17
+#define PSX81_PIF0_LANE3_OVRD2__COEFFICIENTID_3_MASK 0x3000000
+#define PSX81_PIF0_LANE3_OVRD2__COEFFICIENTID_3__SHIFT 0x18
+#define PSX81_PIF0_LANE3_OVRD2__COEFFICIENT_3_MASK 0xfc000000
+#define PSX81_PIF0_LANE3_OVRD2__COEFFICIENT_3__SHIFT 0x1a
+#define PSX81_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK 0x1
+#define PSX81_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT 0x0
+#define PSX81_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2
+#define PSX81_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT 0x1
+#define PSX81_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK 0x4
+#define PSX81_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2
+#define PSX81_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK 0x8
+#define PSX81_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT 0x3
+#define PSX81_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK 0x10
+#define PSX81_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT 0x4
+#define PSX81_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK 0x20
+#define PSX81_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT 0x5
+#define PSX81_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK 0x40
+#define PSX81_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT 0x6
+#define PSX81_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK 0x80
+#define PSX81_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT 0x7
+#define PSX81_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK 0x100
+#define PSX81_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT 0x8
+#define PSX81_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK 0x200
+#define PSX81_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT 0x9
+#define PSX81_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK 0x400
+#define PSX81_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT 0xa
+#define PSX81_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK 0x800
+#define PSX81_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT 0xb
+#define PSX81_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK 0x1000
+#define PSX81_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT 0xc
+#define PSX81_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK 0x2000
+#define PSX81_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT 0xd
+#define PSX81_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK 0x4000
+#define PSX81_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT 0xe
+#define PSX81_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK 0x8000
+#define PSX81_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT 0xf
+#define PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4_MASK 0x10000
+#define PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT 0x10
+#define PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK 0x20000
+#define PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT 0x11
+#define PSX81_PIF0_LANE4_OVRD2__GANGMODE_4_MASK 0x7
+#define PSX81_PIF0_LANE4_OVRD2__GANGMODE_4__SHIFT 0x0
+#define PSX81_PIF0_LANE4_OVRD2__FREQDIV_4_MASK 0x18
+#define PSX81_PIF0_LANE4_OVRD2__FREQDIV_4__SHIFT 0x3
+#define PSX81_PIF0_LANE4_OVRD2__LINKSPEED_4_MASK 0x60
+#define PSX81_PIF0_LANE4_OVRD2__LINKSPEED_4__SHIFT 0x5
+#define PSX81_PIF0_LANE4_OVRD2__TWOSYMENABLE_4_MASK 0x80
+#define PSX81_PIF0_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT 0x7
+#define PSX81_PIF0_LANE4_OVRD2__TXPWR_4_MASK 0x700
+#define PSX81_PIF0_LANE4_OVRD2__TXPWR_4__SHIFT 0x8
+#define PSX81_PIF0_LANE4_OVRD2__TXPGENABLE_4_MASK 0x1800
+#define PSX81_PIF0_LANE4_OVRD2__TXPGENABLE_4__SHIFT 0xb
+#define PSX81_PIF0_LANE4_OVRD2__RXPWR_4_MASK 0xe000
+#define PSX81_PIF0_LANE4_OVRD2__RXPWR_4__SHIFT 0xd
+#define PSX81_PIF0_LANE4_OVRD2__RXPGENABLE_4_MASK 0x30000
+#define PSX81_PIF0_LANE4_OVRD2__RXPGENABLE_4__SHIFT 0x10
+#define PSX81_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4_MASK 0x40000
+#define PSX81_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT 0x12
+#define PSX81_PIF0_LANE4_OVRD2__ENABLEFOM_4_MASK 0x80000
+#define PSX81_PIF0_LANE4_OVRD2__ENABLEFOM_4__SHIFT 0x13
+#define PSX81_PIF0_LANE4_OVRD2__REQUESTFOM_4_MASK 0x100000
+#define PSX81_PIF0_LANE4_OVRD2__REQUESTFOM_4__SHIFT 0x14
+#define PSX81_PIF0_LANE4_OVRD2__RESPONSEMODE_4_MASK 0x200000
+#define PSX81_PIF0_LANE4_OVRD2__RESPONSEMODE_4__SHIFT 0x15
+#define PSX81_PIF0_LANE4_OVRD2__REQUESTTRK_4_MASK 0x400000
+#define PSX81_PIF0_LANE4_OVRD2__REQUESTTRK_4__SHIFT 0x16
+#define PSX81_PIF0_LANE4_OVRD2__REQUESTTRN_4_MASK 0x800000
+#define PSX81_PIF0_LANE4_OVRD2__REQUESTTRN_4__SHIFT 0x17
+#define PSX81_PIF0_LANE4_OVRD2__COEFFICIENTID_4_MASK 0x3000000
+#define PSX81_PIF0_LANE4_OVRD2__COEFFICIENTID_4__SHIFT 0x18
+#define PSX81_PIF0_LANE4_OVRD2__COEFFICIENT_4_MASK 0xfc000000
+#define PSX81_PIF0_LANE4_OVRD2__COEFFICIENT_4__SHIFT 0x1a
+#define PSX81_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK 0x1
+#define PSX81_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT 0x0
+#define PSX81_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2
+#define PSX81_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT 0x1
+#define PSX81_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK 0x4
+#define PSX81_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2
+#define PSX81_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK 0x8
+#define PSX81_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT 0x3
+#define PSX81_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK 0x10
+#define PSX81_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT 0x4
+#define PSX81_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK 0x20
+#define PSX81_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT 0x5
+#define PSX81_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK 0x40
+#define PSX81_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT 0x6
+#define PSX81_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK 0x80
+#define PSX81_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT 0x7
+#define PSX81_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK 0x100
+#define PSX81_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT 0x8
+#define PSX81_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK 0x200
+#define PSX81_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT 0x9
+#define PSX81_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK 0x400
+#define PSX81_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT 0xa
+#define PSX81_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK 0x800
+#define PSX81_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT 0xb
+#define PSX81_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK 0x1000
+#define PSX81_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT 0xc
+#define PSX81_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK 0x2000
+#define PSX81_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT 0xd
+#define PSX81_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK 0x4000
+#define PSX81_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT 0xe
+#define PSX81_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK 0x8000
+#define PSX81_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT 0xf
+#define PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5_MASK 0x10000
+#define PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT 0x10
+#define PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK 0x20000
+#define PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT 0x11
+#define PSX81_PIF0_LANE5_OVRD2__GANGMODE_5_MASK 0x7
+#define PSX81_PIF0_LANE5_OVRD2__GANGMODE_5__SHIFT 0x0
+#define PSX81_PIF0_LANE5_OVRD2__FREQDIV_5_MASK 0x18
+#define PSX81_PIF0_LANE5_OVRD2__FREQDIV_5__SHIFT 0x3
+#define PSX81_PIF0_LANE5_OVRD2__LINKSPEED_5_MASK 0x60
+#define PSX81_PIF0_LANE5_OVRD2__LINKSPEED_5__SHIFT 0x5
+#define PSX81_PIF0_LANE5_OVRD2__TWOSYMENABLE_5_MASK 0x80
+#define PSX81_PIF0_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT 0x7
+#define PSX81_PIF0_LANE5_OVRD2__TXPWR_5_MASK 0x700
+#define PSX81_PIF0_LANE5_OVRD2__TXPWR_5__SHIFT 0x8
+#define PSX81_PIF0_LANE5_OVRD2__TXPGENABLE_5_MASK 0x1800
+#define PSX81_PIF0_LANE5_OVRD2__TXPGENABLE_5__SHIFT 0xb
+#define PSX81_PIF0_LANE5_OVRD2__RXPWR_5_MASK 0xe000
+#define PSX81_PIF0_LANE5_OVRD2__RXPWR_5__SHIFT 0xd
+#define PSX81_PIF0_LANE5_OVRD2__RXPGENABLE_5_MASK 0x30000
+#define PSX81_PIF0_LANE5_OVRD2__RXPGENABLE_5__SHIFT 0x10
+#define PSX81_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5_MASK 0x40000
+#define PSX81_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT 0x12
+#define PSX81_PIF0_LANE5_OVRD2__ENABLEFOM_5_MASK 0x80000
+#define PSX81_PIF0_LANE5_OVRD2__ENABLEFOM_5__SHIFT 0x13
+#define PSX81_PIF0_LANE5_OVRD2__REQUESTFOM_5_MASK 0x100000
+#define PSX81_PIF0_LANE5_OVRD2__REQUESTFOM_5__SHIFT 0x14
+#define PSX81_PIF0_LANE5_OVRD2__RESPONSEMODE_5_MASK 0x200000
+#define PSX81_PIF0_LANE5_OVRD2__RESPONSEMODE_5__SHIFT 0x15
+#define PSX81_PIF0_LANE5_OVRD2__REQUESTTRK_5_MASK 0x400000
+#define PSX81_PIF0_LANE5_OVRD2__REQUESTTRK_5__SHIFT 0x16
+#define PSX81_PIF0_LANE5_OVRD2__REQUESTTRN_5_MASK 0x800000
+#define PSX81_PIF0_LANE5_OVRD2__REQUESTTRN_5__SHIFT 0x17
+#define PSX81_PIF0_LANE5_OVRD2__COEFFICIENTID_5_MASK 0x3000000
+#define PSX81_PIF0_LANE5_OVRD2__COEFFICIENTID_5__SHIFT 0x18
+#define PSX81_PIF0_LANE5_OVRD2__COEFFICIENT_5_MASK 0xfc000000
+#define PSX81_PIF0_LANE5_OVRD2__COEFFICIENT_5__SHIFT 0x1a
+#define PSX81_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK 0x1
+#define PSX81_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT 0x0
+#define PSX81_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2
+#define PSX81_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT 0x1
+#define PSX81_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK 0x4
+#define PSX81_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2
+#define PSX81_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK 0x8
+#define PSX81_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT 0x3
+#define PSX81_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK 0x10
+#define PSX81_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT 0x4
+#define PSX81_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK 0x20
+#define PSX81_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT 0x5
+#define PSX81_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK 0x40
+#define PSX81_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT 0x6
+#define PSX81_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK 0x80
+#define PSX81_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT 0x7
+#define PSX81_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK 0x100
+#define PSX81_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT 0x8
+#define PSX81_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK 0x200
+#define PSX81_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT 0x9
+#define PSX81_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK 0x400
+#define PSX81_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT 0xa
+#define PSX81_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK 0x800
+#define PSX81_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT 0xb
+#define PSX81_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK 0x1000
+#define PSX81_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT 0xc
+#define PSX81_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK 0x2000
+#define PSX81_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT 0xd
+#define PSX81_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK 0x4000
+#define PSX81_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT 0xe
+#define PSX81_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK 0x8000
+#define PSX81_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT 0xf
+#define PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6_MASK 0x10000
+#define PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT 0x10
+#define PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK 0x20000
+#define PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT 0x11
+#define PSX81_PIF0_LANE6_OVRD2__GANGMODE_6_MASK 0x7
+#define PSX81_PIF0_LANE6_OVRD2__GANGMODE_6__SHIFT 0x0
+#define PSX81_PIF0_LANE6_OVRD2__FREQDIV_6_MASK 0x18
+#define PSX81_PIF0_LANE6_OVRD2__FREQDIV_6__SHIFT 0x3
+#define PSX81_PIF0_LANE6_OVRD2__LINKSPEED_6_MASK 0x60
+#define PSX81_PIF0_LANE6_OVRD2__LINKSPEED_6__SHIFT 0x5
+#define PSX81_PIF0_LANE6_OVRD2__TWOSYMENABLE_6_MASK 0x80
+#define PSX81_PIF0_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT 0x7
+#define PSX81_PIF0_LANE6_OVRD2__TXPWR_6_MASK 0x700
+#define PSX81_PIF0_LANE6_OVRD2__TXPWR_6__SHIFT 0x8
+#define PSX81_PIF0_LANE6_OVRD2__TXPGENABLE_6_MASK 0x1800
+#define PSX81_PIF0_LANE6_OVRD2__TXPGENABLE_6__SHIFT 0xb
+#define PSX81_PIF0_LANE6_OVRD2__RXPWR_6_MASK 0xe000
+#define PSX81_PIF0_LANE6_OVRD2__RXPWR_6__SHIFT 0xd
+#define PSX81_PIF0_LANE6_OVRD2__RXPGENABLE_6_MASK 0x30000
+#define PSX81_PIF0_LANE6_OVRD2__RXPGENABLE_6__SHIFT 0x10
+#define PSX81_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6_MASK 0x40000
+#define PSX81_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT 0x12
+#define PSX81_PIF0_LANE6_OVRD2__ENABLEFOM_6_MASK 0x80000
+#define PSX81_PIF0_LANE6_OVRD2__ENABLEFOM_6__SHIFT 0x13
+#define PSX81_PIF0_LANE6_OVRD2__REQUESTFOM_6_MASK 0x100000
+#define PSX81_PIF0_LANE6_OVRD2__REQUESTFOM_6__SHIFT 0x14
+#define PSX81_PIF0_LANE6_OVRD2__RESPONSEMODE_6_MASK 0x200000
+#define PSX81_PIF0_LANE6_OVRD2__RESPONSEMODE_6__SHIFT 0x15
+#define PSX81_PIF0_LANE6_OVRD2__REQUESTTRK_6_MASK 0x400000
+#define PSX81_PIF0_LANE6_OVRD2__REQUESTTRK_6__SHIFT 0x16
+#define PSX81_PIF0_LANE6_OVRD2__REQUESTTRN_6_MASK 0x800000
+#define PSX81_PIF0_LANE6_OVRD2__REQUESTTRN_6__SHIFT 0x17
+#define PSX81_PIF0_LANE6_OVRD2__COEFFICIENTID_6_MASK 0x3000000
+#define PSX81_PIF0_LANE6_OVRD2__COEFFICIENTID_6__SHIFT 0x18
+#define PSX81_PIF0_LANE6_OVRD2__COEFFICIENT_6_MASK 0xfc000000
+#define PSX81_PIF0_LANE6_OVRD2__COEFFICIENT_6__SHIFT 0x1a
+#define PSX81_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK 0x1
+#define PSX81_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT 0x0
+#define PSX81_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK 0x2
+#define PSX81_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT 0x1
+#define PSX81_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK 0x4
+#define PSX81_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT 0x2
+#define PSX81_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK 0x8
+#define PSX81_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT 0x3
+#define PSX81_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK 0x10
+#define PSX81_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT 0x4
+#define PSX81_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK 0x20
+#define PSX81_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT 0x5
+#define PSX81_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK 0x40
+#define PSX81_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT 0x6
+#define PSX81_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK 0x80
+#define PSX81_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT 0x7
+#define PSX81_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK 0x100
+#define PSX81_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT 0x8
+#define PSX81_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK 0x200
+#define PSX81_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT 0x9
+#define PSX81_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK 0x400
+#define PSX81_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT 0xa
+#define PSX81_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK 0x800
+#define PSX81_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT 0xb
+#define PSX81_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK 0x1000
+#define PSX81_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT 0xc
+#define PSX81_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK 0x2000
+#define PSX81_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT 0xd
+#define PSX81_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK 0x4000
+#define PSX81_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT 0xe
+#define PSX81_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK 0x8000
+#define PSX81_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT 0xf
+#define PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7_MASK 0x10000
+#define PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT 0x10
+#define PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK 0x20000
+#define PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT 0x11
+#define PSX81_PIF0_LANE7_OVRD2__GANGMODE_7_MASK 0x7
+#define PSX81_PIF0_LANE7_OVRD2__GANGMODE_7__SHIFT 0x0
+#define PSX81_PIF0_LANE7_OVRD2__FREQDIV_7_MASK 0x18
+#define PSX81_PIF0_LANE7_OVRD2__FREQDIV_7__SHIFT 0x3
+#define PSX81_PIF0_LANE7_OVRD2__LINKSPEED_7_MASK 0x60
+#define PSX81_PIF0_LANE7_OVRD2__LINKSPEED_7__SHIFT 0x5
+#define PSX81_PIF0_LANE7_OVRD2__TWOSYMENABLE_7_MASK 0x80
+#define PSX81_PIF0_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT 0x7
+#define PSX81_PIF0_LANE7_OVRD2__TXPWR_7_MASK 0x700
+#define PSX81_PIF0_LANE7_OVRD2__TXPWR_7__SHIFT 0x8
+#define PSX81_PIF0_LANE7_OVRD2__TXPGENABLE_7_MASK 0x1800
+#define PSX81_PIF0_LANE7_OVRD2__TXPGENABLE_7__SHIFT 0xb
+#define PSX81_PIF0_LANE7_OVRD2__RXPWR_7_MASK 0xe000
+#define PSX81_PIF0_LANE7_OVRD2__RXPWR_7__SHIFT 0xd
+#define PSX81_PIF0_LANE7_OVRD2__RXPGENABLE_7_MASK 0x30000
+#define PSX81_PIF0_LANE7_OVRD2__RXPGENABLE_7__SHIFT 0x10
+#define PSX81_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7_MASK 0x40000
+#define PSX81_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT 0x12
+#define PSX81_PIF0_LANE7_OVRD2__ENABLEFOM_7_MASK 0x80000
+#define PSX81_PIF0_LANE7_OVRD2__ENABLEFOM_7__SHIFT 0x13
+#define PSX81_PIF0_LANE7_OVRD2__REQUESTFOM_7_MASK 0x100000
+#define PSX81_PIF0_LANE7_OVRD2__REQUESTFOM_7__SHIFT 0x14
+#define PSX81_PIF0_LANE7_OVRD2__RESPONSEMODE_7_MASK 0x200000
+#define PSX81_PIF0_LANE7_OVRD2__RESPONSEMODE_7__SHIFT 0x15
+#define PSX81_PIF0_LANE7_OVRD2__REQUESTTRK_7_MASK 0x400000
+#define PSX81_PIF0_LANE7_OVRD2__REQUESTTRK_7__SHIFT 0x16
+#define PSX81_PIF0_LANE7_OVRD2__REQUESTTRN_7_MASK 0x800000
+#define PSX81_PIF0_LANE7_OVRD2__REQUESTTRN_7__SHIFT 0x17
+#define PSX81_PIF0_LANE7_OVRD2__COEFFICIENTID_7_MASK 0x3000000
+#define PSX81_PIF0_LANE7_OVRD2__COEFFICIENTID_7__SHIFT 0x18
+#define PSX81_PIF0_LANE7_OVRD2__COEFFICIENT_7_MASK 0xfc000000
+#define PSX81_PIF0_LANE7_OVRD2__COEFFICIENT_7__SHIFT 0x1a
+
+#endif /* BIF_5_1_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h
new file mode 100644
index 000000000000..95570dbd18bb
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h
@@ -0,0 +1,7350 @@
+/*
+ * DCE_10_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef DCE_10_0_D_H
+#define DCE_10_0_D_H
+
+#define mmPIPE0_PG_CONFIG 0x2c0
+#define mmPIPE0_PG_ENABLE 0x2c1
+#define mmPIPE0_PG_STATUS 0x2c2
+#define mmPIPE1_PG_CONFIG 0x2c3
+#define mmPIPE1_PG_ENABLE 0x2c4
+#define mmPIPE1_PG_STATUS 0x2c5
+#define mmPIPE2_PG_CONFIG 0x2c6
+#define mmPIPE2_PG_ENABLE 0x2c7
+#define mmPIPE2_PG_STATUS 0x2c8
+#define mmPIPE3_PG_CONFIG 0x2c9
+#define mmPIPE3_PG_ENABLE 0x2ca
+#define mmPIPE3_PG_STATUS 0x2cb
+#define mmPIPE4_PG_CONFIG 0x2cc
+#define mmPIPE4_PG_ENABLE 0x2cd
+#define mmPIPE4_PG_STATUS 0x2ce
+#define mmPIPE5_PG_CONFIG 0x2cf
+#define mmPIPE5_PG_ENABLE 0x2d0
+#define mmPIPE5_PG_STATUS 0x2d1
+#define mmDC_IP_REQUEST_CNTL 0x2d2
+#define mmDC_PGFSM_CONFIG_REG 0x2d3
+#define mmDC_PGFSM_WRITE_REG 0x2d4
+#define mmDC_PGCNTL_STATUS_REG 0x2d5
+#define mmDCPG_TEST_DEBUG_INDEX 0x2d6
+#define mmDCPG_TEST_DEBUG_DATA 0x2d7
+#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628
+#define mmBL1_PWM_USER_LEVEL 0x1629
+#define mmBL1_PWM_TARGET_ABM_LEVEL 0x162a
+#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x162b
+#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c
+#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162d
+#define mmBL1_PWM_ABM_CNTL 0x162e
+#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162f
+#define mmBL1_PWM_GRP2_REG_LOCK 0x1630
+#define mmDC_ABM1_CNTL 0x1638
+#define mmDC_ABM1_IPCSC_COEFF_SEL 0x1639
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163a
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163b
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163c
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163d
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163e
+#define mmDC_ABM1_ACE_THRES_12 0x163f
+#define mmDC_ABM1_ACE_THRES_34 0x1640
+#define mmDC_ABM1_ACE_CNTL_MISC 0x1641
+#define mmDC_ABM1_DEBUG_MISC 0x1649
+#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164a
+#define mmDC_ABM1_HG_MISC_CTRL 0x164b
+#define mmDC_ABM1_LS_SUM_OF_LUMA 0x164c
+#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x164d
+#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164e
+#define mmDC_ABM1_LS_PIXEL_COUNT 0x164f
+#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650
+#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651
+#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652
+#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653
+#define mmDC_ABM1_HG_SAMPLE_RATE 0x1654
+#define mmDC_ABM1_LS_SAMPLE_RATE 0x1655
+#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656
+#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657
+#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658
+#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659
+#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165a
+#define mmDC_ABM1_HG_RESULT_1 0x165b
+#define mmDC_ABM1_HG_RESULT_2 0x165c
+#define mmDC_ABM1_HG_RESULT_3 0x165d
+#define mmDC_ABM1_HG_RESULT_4 0x165e
+#define mmDC_ABM1_HG_RESULT_5 0x165f
+#define mmDC_ABM1_HG_RESULT_6 0x1660
+#define mmDC_ABM1_HG_RESULT_7 0x1661
+#define mmDC_ABM1_HG_RESULT_8 0x1662
+#define mmDC_ABM1_HG_RESULT_9 0x1663
+#define mmDC_ABM1_HG_RESULT_10 0x1664
+#define mmDC_ABM1_HG_RESULT_11 0x1665
+#define mmDC_ABM1_HG_RESULT_12 0x1666
+#define mmDC_ABM1_HG_RESULT_13 0x1667
+#define mmDC_ABM1_HG_RESULT_14 0x1668
+#define mmDC_ABM1_HG_RESULT_15 0x1669
+#define mmDC_ABM1_HG_RESULT_16 0x166a
+#define mmDC_ABM1_HG_RESULT_17 0x166b
+#define mmDC_ABM1_HG_RESULT_18 0x166c
+#define mmDC_ABM1_HG_RESULT_19 0x166d
+#define mmDC_ABM1_HG_RESULT_20 0x166e
+#define mmDC_ABM1_HG_RESULT_21 0x166f
+#define mmDC_ABM1_HG_RESULT_22 0x1670
+#define mmDC_ABM1_HG_RESULT_23 0x1671
+#define mmDC_ABM1_HG_RESULT_24 0x1672
+#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169b
+#define mmDC_ABM1_BL_MASTER_LOCK 0x169c
+#define mmABM_TEST_DEBUG_INDEX 0x169e
+#define mmABM_TEST_DEBUG_DATA 0x169f
+#define mmCRTC_DCFE_CLOCK_CONTROL 0x1b7c
+#define mmCRTC0_CRTC_DCFE_CLOCK_CONTROL 0x1b7c
+#define mmCRTC1_CRTC_DCFE_CLOCK_CONTROL 0x1d7c
+#define mmCRTC2_CRTC_DCFE_CLOCK_CONTROL 0x1f7c
+#define mmCRTC3_CRTC_DCFE_CLOCK_CONTROL 0x417c
+#define mmCRTC4_CRTC_DCFE_CLOCK_CONTROL 0x437c
+#define mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 0x457c
+#define mmCRTC6_CRTC_DCFE_CLOCK_CONTROL 0x477c
+#define mmCRTC_H_BLANK_EARLY_NUM 0x1b7d
+#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1b7d
+#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1d7d
+#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x1f7d
+#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x417d
+#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x437d
+#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x457d
+#define mmCRTC6_CRTC_H_BLANK_EARLY_NUM 0x477d
+#define mmDCFE_DBG_SEL 0x1b7e
+#define mmCRTC0_DCFE_DBG_SEL 0x1b7e
+#define mmCRTC1_DCFE_DBG_SEL 0x1d7e
+#define mmCRTC2_DCFE_DBG_SEL 0x1f7e
+#define mmCRTC3_DCFE_DBG_SEL 0x417e
+#define mmCRTC4_DCFE_DBG_SEL 0x437e
+#define mmCRTC5_DCFE_DBG_SEL 0x457e
+#define mmCRTC6_DCFE_DBG_SEL 0x477e
+#define mmDCFE_MEM_PWR_CTRL 0x1b7f
+#define mmCRTC0_DCFE_MEM_PWR_CTRL 0x1b7f
+#define mmCRTC1_DCFE_MEM_PWR_CTRL 0x1d7f
+#define mmCRTC2_DCFE_MEM_PWR_CTRL 0x1f7f
+#define mmCRTC3_DCFE_MEM_PWR_CTRL 0x417f
+#define mmCRTC4_DCFE_MEM_PWR_CTRL 0x437f
+#define mmCRTC5_DCFE_MEM_PWR_CTRL 0x457f
+#define mmCRTC6_DCFE_MEM_PWR_CTRL 0x477f
+#define mmDCFE_MEM_PWR_CTRL2 0x1bb8
+#define mmCRTC0_DCFE_MEM_PWR_CTRL2 0x1bb8
+#define mmCRTC1_DCFE_MEM_PWR_CTRL2 0x1db8
+#define mmCRTC2_DCFE_MEM_PWR_CTRL2 0x1fb8
+#define mmCRTC3_DCFE_MEM_PWR_CTRL2 0x41b8
+#define mmCRTC4_DCFE_MEM_PWR_CTRL2 0x43b8
+#define mmCRTC5_DCFE_MEM_PWR_CTRL2 0x45b8
+#define mmCRTC6_DCFE_MEM_PWR_CTRL2 0x47b8
+#define mmDCFE_MEM_PWR_STATUS 0x1bb9
+#define mmCRTC0_DCFE_MEM_PWR_STATUS 0x1bb9
+#define mmCRTC1_DCFE_MEM_PWR_STATUS 0x1db9
+#define mmCRTC2_DCFE_MEM_PWR_STATUS 0x1fb9
+#define mmCRTC3_DCFE_MEM_PWR_STATUS 0x41b9
+#define mmCRTC4_DCFE_MEM_PWR_STATUS 0x43b9
+#define mmCRTC5_DCFE_MEM_PWR_STATUS 0x45b9
+#define mmCRTC6_DCFE_MEM_PWR_STATUS 0x47b9
+#define mmCRTC_H_TOTAL 0x1b80
+#define mmCRTC0_CRTC_H_TOTAL 0x1b80
+#define mmCRTC1_CRTC_H_TOTAL 0x1d80
+#define mmCRTC2_CRTC_H_TOTAL 0x1f80
+#define mmCRTC3_CRTC_H_TOTAL 0x4180
+#define mmCRTC4_CRTC_H_TOTAL 0x4380
+#define mmCRTC5_CRTC_H_TOTAL 0x4580
+#define mmCRTC6_CRTC_H_TOTAL 0x4780
+#define mmCRTC_H_BLANK_START_END 0x1b81
+#define mmCRTC0_CRTC_H_BLANK_START_END 0x1b81
+#define mmCRTC1_CRTC_H_BLANK_START_END 0x1d81
+#define mmCRTC2_CRTC_H_BLANK_START_END 0x1f81
+#define mmCRTC3_CRTC_H_BLANK_START_END 0x4181
+#define mmCRTC4_CRTC_H_BLANK_START_END 0x4381
+#define mmCRTC5_CRTC_H_BLANK_START_END 0x4581
+#define mmCRTC6_CRTC_H_BLANK_START_END 0x4781
+#define mmCRTC_H_SYNC_A 0x1b82
+#define mmCRTC0_CRTC_H_SYNC_A 0x1b82
+#define mmCRTC1_CRTC_H_SYNC_A 0x1d82
+#define mmCRTC2_CRTC_H_SYNC_A 0x1f82
+#define mmCRTC3_CRTC_H_SYNC_A 0x4182
+#define mmCRTC4_CRTC_H_SYNC_A 0x4382
+#define mmCRTC5_CRTC_H_SYNC_A 0x4582
+#define mmCRTC6_CRTC_H_SYNC_A 0x4782
+#define mmCRTC_H_SYNC_A_CNTL 0x1b83
+#define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1b83
+#define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1d83
+#define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x1f83
+#define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4183
+#define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4383
+#define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4583
+#define mmCRTC6_CRTC_H_SYNC_A_CNTL 0x4783
+#define mmCRTC_H_SYNC_B 0x1b84
+#define mmCRTC0_CRTC_H_SYNC_B 0x1b84
+#define mmCRTC1_CRTC_H_SYNC_B 0x1d84
+#define mmCRTC2_CRTC_H_SYNC_B 0x1f84
+#define mmCRTC3_CRTC_H_SYNC_B 0x4184
+#define mmCRTC4_CRTC_H_SYNC_B 0x4384
+#define mmCRTC5_CRTC_H_SYNC_B 0x4584
+#define mmCRTC6_CRTC_H_SYNC_B 0x4784
+#define mmCRTC_H_SYNC_B_CNTL 0x1b85
+#define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1b85
+#define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1d85
+#define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x1f85
+#define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4185
+#define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4385
+#define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4585
+#define mmCRTC6_CRTC_H_SYNC_B_CNTL 0x4785
+#define mmCRTC_VBI_END 0x1b86
+#define mmCRTC0_CRTC_VBI_END 0x1b86
+#define mmCRTC1_CRTC_VBI_END 0x1d86
+#define mmCRTC2_CRTC_VBI_END 0x1f86
+#define mmCRTC3_CRTC_VBI_END 0x4186
+#define mmCRTC4_CRTC_VBI_END 0x4386
+#define mmCRTC5_CRTC_VBI_END 0x4586
+#define mmCRTC6_CRTC_VBI_END 0x4786
+#define mmCRTC_V_TOTAL 0x1b87
+#define mmCRTC0_CRTC_V_TOTAL 0x1b87
+#define mmCRTC1_CRTC_V_TOTAL 0x1d87
+#define mmCRTC2_CRTC_V_TOTAL 0x1f87
+#define mmCRTC3_CRTC_V_TOTAL 0x4187
+#define mmCRTC4_CRTC_V_TOTAL 0x4387
+#define mmCRTC5_CRTC_V_TOTAL 0x4587
+#define mmCRTC6_CRTC_V_TOTAL 0x4787
+#define mmCRTC_V_TOTAL_MIN 0x1b88
+#define mmCRTC0_CRTC_V_TOTAL_MIN 0x1b88
+#define mmCRTC1_CRTC_V_TOTAL_MIN 0x1d88
+#define mmCRTC2_CRTC_V_TOTAL_MIN 0x1f88
+#define mmCRTC3_CRTC_V_TOTAL_MIN 0x4188
+#define mmCRTC4_CRTC_V_TOTAL_MIN 0x4388
+#define mmCRTC5_CRTC_V_TOTAL_MIN 0x4588
+#define mmCRTC6_CRTC_V_TOTAL_MIN 0x4788
+#define mmCRTC_V_TOTAL_MAX 0x1b89
+#define mmCRTC0_CRTC_V_TOTAL_MAX 0x1b89
+#define mmCRTC1_CRTC_V_TOTAL_MAX 0x1d89
+#define mmCRTC2_CRTC_V_TOTAL_MAX 0x1f89
+#define mmCRTC3_CRTC_V_TOTAL_MAX 0x4189
+#define mmCRTC4_CRTC_V_TOTAL_MAX 0x4389
+#define mmCRTC5_CRTC_V_TOTAL_MAX 0x4589
+#define mmCRTC6_CRTC_V_TOTAL_MAX 0x4789
+#define mmCRTC_V_TOTAL_CONTROL 0x1b8a
+#define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1b8a
+#define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1d8a
+#define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x1f8a
+#define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x418a
+#define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x438a
+#define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x458a
+#define mmCRTC6_CRTC_V_TOTAL_CONTROL 0x478a
+#define mmCRTC_V_TOTAL_INT_STATUS 0x1b8b
+#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1b8b
+#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1d8b
+#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x1f8b
+#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x418b
+#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x438b
+#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x458b
+#define mmCRTC6_CRTC_V_TOTAL_INT_STATUS 0x478b
+#define mmCRTC_VSYNC_NOM_INT_STATUS 0x1b8c
+#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1b8c
+#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1d8c
+#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x1f8c
+#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x418c
+#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x438c
+#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x458c
+#define mmCRTC6_CRTC_VSYNC_NOM_INT_STATUS 0x478c
+#define mmCRTC_V_BLANK_START_END 0x1b8d
+#define mmCRTC0_CRTC_V_BLANK_START_END 0x1b8d
+#define mmCRTC1_CRTC_V_BLANK_START_END 0x1d8d
+#define mmCRTC2_CRTC_V_BLANK_START_END 0x1f8d
+#define mmCRTC3_CRTC_V_BLANK_START_END 0x418d
+#define mmCRTC4_CRTC_V_BLANK_START_END 0x438d
+#define mmCRTC5_CRTC_V_BLANK_START_END 0x458d
+#define mmCRTC6_CRTC_V_BLANK_START_END 0x478d
+#define mmCRTC_V_SYNC_A 0x1b8e
+#define mmCRTC0_CRTC_V_SYNC_A 0x1b8e
+#define mmCRTC1_CRTC_V_SYNC_A 0x1d8e
+#define mmCRTC2_CRTC_V_SYNC_A 0x1f8e
+#define mmCRTC3_CRTC_V_SYNC_A 0x418e
+#define mmCRTC4_CRTC_V_SYNC_A 0x438e
+#define mmCRTC5_CRTC_V_SYNC_A 0x458e
+#define mmCRTC6_CRTC_V_SYNC_A 0x478e
+#define mmCRTC_V_SYNC_A_CNTL 0x1b8f
+#define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1b8f
+#define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1d8f
+#define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x1f8f
+#define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x418f
+#define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x438f
+#define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x458f
+#define mmCRTC6_CRTC_V_SYNC_A_CNTL 0x478f
+#define mmCRTC_V_SYNC_B 0x1b90
+#define mmCRTC0_CRTC_V_SYNC_B 0x1b90
+#define mmCRTC1_CRTC_V_SYNC_B 0x1d90
+#define mmCRTC2_CRTC_V_SYNC_B 0x1f90
+#define mmCRTC3_CRTC_V_SYNC_B 0x4190
+#define mmCRTC4_CRTC_V_SYNC_B 0x4390
+#define mmCRTC5_CRTC_V_SYNC_B 0x4590
+#define mmCRTC6_CRTC_V_SYNC_B 0x4790
+#define mmCRTC_V_SYNC_B_CNTL 0x1b91
+#define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1b91
+#define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1d91
+#define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x1f91
+#define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4191
+#define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4391
+#define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4591
+#define mmCRTC6_CRTC_V_SYNC_B_CNTL 0x4791
+#define mmCRTC_DTMTEST_CNTL 0x1b92
+#define mmCRTC0_CRTC_DTMTEST_CNTL 0x1b92
+#define mmCRTC1_CRTC_DTMTEST_CNTL 0x1d92
+#define mmCRTC2_CRTC_DTMTEST_CNTL 0x1f92
+#define mmCRTC3_CRTC_DTMTEST_CNTL 0x4192
+#define mmCRTC4_CRTC_DTMTEST_CNTL 0x4392
+#define mmCRTC5_CRTC_DTMTEST_CNTL 0x4592
+#define mmCRTC6_CRTC_DTMTEST_CNTL 0x4792
+#define mmCRTC_DTMTEST_STATUS_POSITION 0x1b93
+#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1b93
+#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1d93
+#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x1f93
+#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4193
+#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4393
+#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4593
+#define mmCRTC6_CRTC_DTMTEST_STATUS_POSITION 0x4793
+#define mmCRTC_TRIGA_CNTL 0x1b94
+#define mmCRTC0_CRTC_TRIGA_CNTL 0x1b94
+#define mmCRTC1_CRTC_TRIGA_CNTL 0x1d94
+#define mmCRTC2_CRTC_TRIGA_CNTL 0x1f94
+#define mmCRTC3_CRTC_TRIGA_CNTL 0x4194
+#define mmCRTC4_CRTC_TRIGA_CNTL 0x4394
+#define mmCRTC5_CRTC_TRIGA_CNTL 0x4594
+#define mmCRTC6_CRTC_TRIGA_CNTL 0x4794
+#define mmCRTC_TRIGA_MANUAL_TRIG 0x1b95
+#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1b95
+#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1d95
+#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x1f95
+#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4195
+#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4395
+#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4595
+#define mmCRTC6_CRTC_TRIGA_MANUAL_TRIG 0x4795
+#define mmCRTC_TRIGB_CNTL 0x1b96
+#define mmCRTC0_CRTC_TRIGB_CNTL 0x1b96
+#define mmCRTC1_CRTC_TRIGB_CNTL 0x1d96
+#define mmCRTC2_CRTC_TRIGB_CNTL 0x1f96
+#define mmCRTC3_CRTC_TRIGB_CNTL 0x4196
+#define mmCRTC4_CRTC_TRIGB_CNTL 0x4396
+#define mmCRTC5_CRTC_TRIGB_CNTL 0x4596
+#define mmCRTC6_CRTC_TRIGB_CNTL 0x4796
+#define mmCRTC_TRIGB_MANUAL_TRIG 0x1b97
+#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1b97
+#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1d97
+#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x1f97
+#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4197
+#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4397
+#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4597
+#define mmCRTC6_CRTC_TRIGB_MANUAL_TRIG 0x4797
+#define mmCRTC_FORCE_COUNT_NOW_CNTL 0x1b98
+#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1b98
+#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1d98
+#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x1f98
+#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4198
+#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4398
+#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4598
+#define mmCRTC6_CRTC_FORCE_COUNT_NOW_CNTL 0x4798
+#define mmCRTC_FLOW_CONTROL 0x1b99
+#define mmCRTC0_CRTC_FLOW_CONTROL 0x1b99
+#define mmCRTC1_CRTC_FLOW_CONTROL 0x1d99
+#define mmCRTC2_CRTC_FLOW_CONTROL 0x1f99
+#define mmCRTC3_CRTC_FLOW_CONTROL 0x4199
+#define mmCRTC4_CRTC_FLOW_CONTROL 0x4399
+#define mmCRTC5_CRTC_FLOW_CONTROL 0x4599
+#define mmCRTC6_CRTC_FLOW_CONTROL 0x4799
+#define mmCRTC_STEREO_FORCE_NEXT_EYE 0x1b9a
+#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1b9a
+#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1d9a
+#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x1f9a
+#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x419a
+#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x439a
+#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x459a
+#define mmCRTC6_CRTC_STEREO_FORCE_NEXT_EYE 0x479a
+#define mmCRTC_AVSYNC_COUNTER 0x1b9b
+#define mmCRTC0_CRTC_AVSYNC_COUNTER 0x1b9b
+#define mmCRTC1_CRTC_AVSYNC_COUNTER 0x1d9b
+#define mmCRTC2_CRTC_AVSYNC_COUNTER 0x1f9b
+#define mmCRTC3_CRTC_AVSYNC_COUNTER 0x419b
+#define mmCRTC4_CRTC_AVSYNC_COUNTER 0x439b
+#define mmCRTC5_CRTC_AVSYNC_COUNTER 0x459b
+#define mmCRTC6_CRTC_AVSYNC_COUNTER 0x479b
+#define mmCRTC_CONTROL 0x1b9c
+#define mmCRTC0_CRTC_CONTROL 0x1b9c
+#define mmCRTC1_CRTC_CONTROL 0x1d9c
+#define mmCRTC2_CRTC_CONTROL 0x1f9c
+#define mmCRTC3_CRTC_CONTROL 0x419c
+#define mmCRTC4_CRTC_CONTROL 0x439c
+#define mmCRTC5_CRTC_CONTROL 0x459c
+#define mmCRTC6_CRTC_CONTROL 0x479c
+#define mmCRTC_BLANK_CONTROL 0x1b9d
+#define mmCRTC0_CRTC_BLANK_CONTROL 0x1b9d
+#define mmCRTC1_CRTC_BLANK_CONTROL 0x1d9d
+#define mmCRTC2_CRTC_BLANK_CONTROL 0x1f9d
+#define mmCRTC3_CRTC_BLANK_CONTROL 0x419d
+#define mmCRTC4_CRTC_BLANK_CONTROL 0x439d
+#define mmCRTC5_CRTC_BLANK_CONTROL 0x459d
+#define mmCRTC6_CRTC_BLANK_CONTROL 0x479d
+#define mmCRTC_INTERLACE_CONTROL 0x1b9e
+#define mmCRTC0_CRTC_INTERLACE_CONTROL 0x1b9e
+#define mmCRTC1_CRTC_INTERLACE_CONTROL 0x1d9e
+#define mmCRTC2_CRTC_INTERLACE_CONTROL 0x1f9e
+#define mmCRTC3_CRTC_INTERLACE_CONTROL 0x419e
+#define mmCRTC4_CRTC_INTERLACE_CONTROL 0x439e
+#define mmCRTC5_CRTC_INTERLACE_CONTROL 0x459e
+#define mmCRTC6_CRTC_INTERLACE_CONTROL 0x479e
+#define mmCRTC_INTERLACE_STATUS 0x1b9f
+#define mmCRTC0_CRTC_INTERLACE_STATUS 0x1b9f
+#define mmCRTC1_CRTC_INTERLACE_STATUS 0x1d9f
+#define mmCRTC2_CRTC_INTERLACE_STATUS 0x1f9f
+#define mmCRTC3_CRTC_INTERLACE_STATUS 0x419f
+#define mmCRTC4_CRTC_INTERLACE_STATUS 0x439f
+#define mmCRTC5_CRTC_INTERLACE_STATUS 0x459f
+#define mmCRTC6_CRTC_INTERLACE_STATUS 0x479f
+#define mmCRTC_FIELD_INDICATION_CONTROL 0x1ba0
+#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x1ba0
+#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x1da0
+#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x1fa0
+#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x41a0
+#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x43a0
+#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x45a0
+#define mmCRTC6_CRTC_FIELD_INDICATION_CONTROL 0x47a0
+#define mmCRTC_PIXEL_DATA_READBACK0 0x1ba1
+#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x1ba1
+#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x1da1
+#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x1fa1
+#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x41a1
+#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x43a1
+#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x45a1
+#define mmCRTC6_CRTC_PIXEL_DATA_READBACK0 0x47a1
+#define mmCRTC_PIXEL_DATA_READBACK1 0x1ba2
+#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x1ba2
+#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x1da2
+#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x1fa2
+#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x41a2
+#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x43a2
+#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x45a2
+#define mmCRTC6_CRTC_PIXEL_DATA_READBACK1 0x47a2
+#define mmCRTC_STATUS 0x1ba3
+#define mmCRTC0_CRTC_STATUS 0x1ba3
+#define mmCRTC1_CRTC_STATUS 0x1da3
+#define mmCRTC2_CRTC_STATUS 0x1fa3
+#define mmCRTC3_CRTC_STATUS 0x41a3
+#define mmCRTC4_CRTC_STATUS 0x43a3
+#define mmCRTC5_CRTC_STATUS 0x45a3
+#define mmCRTC6_CRTC_STATUS 0x47a3
+#define mmCRTC_STATUS_POSITION 0x1ba4
+#define mmCRTC0_CRTC_STATUS_POSITION 0x1ba4
+#define mmCRTC1_CRTC_STATUS_POSITION 0x1da4
+#define mmCRTC2_CRTC_STATUS_POSITION 0x1fa4
+#define mmCRTC3_CRTC_STATUS_POSITION 0x41a4
+#define mmCRTC4_CRTC_STATUS_POSITION 0x43a4
+#define mmCRTC5_CRTC_STATUS_POSITION 0x45a4
+#define mmCRTC6_CRTC_STATUS_POSITION 0x47a4
+#define mmCRTC_NOM_VERT_POSITION 0x1ba5
+#define mmCRTC0_CRTC_NOM_VERT_POSITION 0x1ba5
+#define mmCRTC1_CRTC_NOM_VERT_POSITION 0x1da5
+#define mmCRTC2_CRTC_NOM_VERT_POSITION 0x1fa5
+#define mmCRTC3_CRTC_NOM_VERT_POSITION 0x41a5
+#define mmCRTC4_CRTC_NOM_VERT_POSITION 0x43a5
+#define mmCRTC5_CRTC_NOM_VERT_POSITION 0x45a5
+#define mmCRTC6_CRTC_NOM_VERT_POSITION 0x47a5
+#define mmCRTC_STATUS_FRAME_COUNT 0x1ba6
+#define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1ba6
+#define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1da6
+#define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x1fa6
+#define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x41a6
+#define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x43a6
+#define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x45a6
+#define mmCRTC6_CRTC_STATUS_FRAME_COUNT 0x47a6
+#define mmCRTC_STATUS_VF_COUNT 0x1ba7
+#define mmCRTC0_CRTC_STATUS_VF_COUNT 0x1ba7
+#define mmCRTC1_CRTC_STATUS_VF_COUNT 0x1da7
+#define mmCRTC2_CRTC_STATUS_VF_COUNT 0x1fa7
+#define mmCRTC3_CRTC_STATUS_VF_COUNT 0x41a7
+#define mmCRTC4_CRTC_STATUS_VF_COUNT 0x43a7
+#define mmCRTC5_CRTC_STATUS_VF_COUNT 0x45a7
+#define mmCRTC6_CRTC_STATUS_VF_COUNT 0x47a7
+#define mmCRTC_STATUS_HV_COUNT 0x1ba8
+#define mmCRTC0_CRTC_STATUS_HV_COUNT 0x1ba8
+#define mmCRTC1_CRTC_STATUS_HV_COUNT 0x1da8
+#define mmCRTC2_CRTC_STATUS_HV_COUNT 0x1fa8
+#define mmCRTC3_CRTC_STATUS_HV_COUNT 0x41a8
+#define mmCRTC4_CRTC_STATUS_HV_COUNT 0x43a8
+#define mmCRTC5_CRTC_STATUS_HV_COUNT 0x45a8
+#define mmCRTC6_CRTC_STATUS_HV_COUNT 0x47a8
+#define mmCRTC_COUNT_CONTROL 0x1ba9
+#define mmCRTC0_CRTC_COUNT_CONTROL 0x1ba9
+#define mmCRTC1_CRTC_COUNT_CONTROL 0x1da9
+#define mmCRTC2_CRTC_COUNT_CONTROL 0x1fa9
+#define mmCRTC3_CRTC_COUNT_CONTROL 0x41a9
+#define mmCRTC4_CRTC_COUNT_CONTROL 0x43a9
+#define mmCRTC5_CRTC_COUNT_CONTROL 0x45a9
+#define mmCRTC6_CRTC_COUNT_CONTROL 0x47a9
+#define mmCRTC_COUNT_RESET 0x1baa
+#define mmCRTC0_CRTC_COUNT_RESET 0x1baa
+#define mmCRTC1_CRTC_COUNT_RESET 0x1daa
+#define mmCRTC2_CRTC_COUNT_RESET 0x1faa
+#define mmCRTC3_CRTC_COUNT_RESET 0x41aa
+#define mmCRTC4_CRTC_COUNT_RESET 0x43aa
+#define mmCRTC5_CRTC_COUNT_RESET 0x45aa
+#define mmCRTC6_CRTC_COUNT_RESET 0x47aa
+#define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab
+#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab
+#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dab
+#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1fab
+#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41ab
+#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x43ab
+#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x45ab
+#define mmCRTC6_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47ab
+#define mmCRTC_VERT_SYNC_CONTROL 0x1bac
+#define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1bac
+#define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1dac
+#define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x1fac
+#define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x41ac
+#define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x43ac
+#define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x45ac
+#define mmCRTC6_CRTC_VERT_SYNC_CONTROL 0x47ac
+#define mmCRTC_STEREO_STATUS 0x1bad
+#define mmCRTC0_CRTC_STEREO_STATUS 0x1bad
+#define mmCRTC1_CRTC_STEREO_STATUS 0x1dad
+#define mmCRTC2_CRTC_STEREO_STATUS 0x1fad
+#define mmCRTC3_CRTC_STEREO_STATUS 0x41ad
+#define mmCRTC4_CRTC_STEREO_STATUS 0x43ad
+#define mmCRTC5_CRTC_STEREO_STATUS 0x45ad
+#define mmCRTC6_CRTC_STEREO_STATUS 0x47ad
+#define mmCRTC_STEREO_CONTROL 0x1bae
+#define mmCRTC0_CRTC_STEREO_CONTROL 0x1bae
+#define mmCRTC1_CRTC_STEREO_CONTROL 0x1dae
+#define mmCRTC2_CRTC_STEREO_CONTROL 0x1fae
+#define mmCRTC3_CRTC_STEREO_CONTROL 0x41ae
+#define mmCRTC4_CRTC_STEREO_CONTROL 0x43ae
+#define mmCRTC5_CRTC_STEREO_CONTROL 0x45ae
+#define mmCRTC6_CRTC_STEREO_CONTROL 0x47ae
+#define mmCRTC_SNAPSHOT_STATUS 0x1baf
+#define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1baf
+#define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1daf
+#define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x1faf
+#define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x41af
+#define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x43af
+#define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x45af
+#define mmCRTC6_CRTC_SNAPSHOT_STATUS 0x47af
+#define mmCRTC_SNAPSHOT_CONTROL 0x1bb0
+#define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1bb0
+#define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1db0
+#define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x1fb0
+#define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x41b0
+#define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x43b0
+#define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x45b0
+#define mmCRTC6_CRTC_SNAPSHOT_CONTROL 0x47b0
+#define mmCRTC_SNAPSHOT_POSITION 0x1bb1
+#define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1bb1
+#define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1db1
+#define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x1fb1
+#define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x41b1
+#define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x43b1
+#define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x45b1
+#define mmCRTC6_CRTC_SNAPSHOT_POSITION 0x47b1
+#define mmCRTC_SNAPSHOT_FRAME 0x1bb2
+#define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1bb2
+#define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1db2
+#define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x1fb2
+#define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x41b2
+#define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x43b2
+#define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x45b2
+#define mmCRTC6_CRTC_SNAPSHOT_FRAME 0x47b2
+#define mmCRTC_START_LINE_CONTROL 0x1bb3
+#define mmCRTC0_CRTC_START_LINE_CONTROL 0x1bb3
+#define mmCRTC1_CRTC_START_LINE_CONTROL 0x1db3
+#define mmCRTC2_CRTC_START_LINE_CONTROL 0x1fb3
+#define mmCRTC3_CRTC_START_LINE_CONTROL 0x41b3
+#define mmCRTC4_CRTC_START_LINE_CONTROL 0x43b3
+#define mmCRTC5_CRTC_START_LINE_CONTROL 0x45b3
+#define mmCRTC6_CRTC_START_LINE_CONTROL 0x47b3
+#define mmCRTC_INTERRUPT_CONTROL 0x1bb4
+#define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1bb4
+#define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1db4
+#define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x1fb4
+#define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x41b4
+#define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x43b4
+#define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x45b4
+#define mmCRTC6_CRTC_INTERRUPT_CONTROL 0x47b4
+#define mmCRTC_UPDATE_LOCK 0x1bb5
+#define mmCRTC0_CRTC_UPDATE_LOCK 0x1bb5
+#define mmCRTC1_CRTC_UPDATE_LOCK 0x1db5
+#define mmCRTC2_CRTC_UPDATE_LOCK 0x1fb5
+#define mmCRTC3_CRTC_UPDATE_LOCK 0x41b5
+#define mmCRTC4_CRTC_UPDATE_LOCK 0x43b5
+#define mmCRTC5_CRTC_UPDATE_LOCK 0x45b5
+#define mmCRTC6_CRTC_UPDATE_LOCK 0x47b5
+#define mmCRTC_DOUBLE_BUFFER_CONTROL 0x1bb6
+#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1bb6
+#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1db6
+#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x1fb6
+#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x41b6
+#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x43b6
+#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x45b6
+#define mmCRTC6_CRTC_DOUBLE_BUFFER_CONTROL 0x47b6
+#define mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7
+#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7
+#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1db7
+#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1fb7
+#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41b7
+#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x43b7
+#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x45b7
+#define mmCRTC6_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x47b7
+#define mmCRTC_TEST_PATTERN_CONTROL 0x1bba
+#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba
+#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1dba
+#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x1fba
+#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x41ba
+#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x43ba
+#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x45ba
+#define mmCRTC6_CRTC_TEST_PATTERN_CONTROL 0x47ba
+#define mmCRTC_TEST_PATTERN_PARAMETERS 0x1bbb
+#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1bbb
+#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1dbb
+#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x1fbb
+#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x41bb
+#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x43bb
+#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x45bb
+#define mmCRTC6_CRTC_TEST_PATTERN_PARAMETERS 0x47bb
+#define mmCRTC_TEST_PATTERN_COLOR 0x1bbc
+#define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1bbc
+#define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1dbc
+#define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x1fbc
+#define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x41bc
+#define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x43bc
+#define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x45bc
+#define mmCRTC6_CRTC_TEST_PATTERN_COLOR 0x47bc
+#define mmMASTER_UPDATE_LOCK 0x1bbd
+#define mmCRTC0_MASTER_UPDATE_LOCK 0x1bbd
+#define mmCRTC1_MASTER_UPDATE_LOCK 0x1dbd
+#define mmCRTC2_MASTER_UPDATE_LOCK 0x1fbd
+#define mmCRTC3_MASTER_UPDATE_LOCK 0x41bd
+#define mmCRTC4_MASTER_UPDATE_LOCK 0x43bd
+#define mmCRTC5_MASTER_UPDATE_LOCK 0x45bd
+#define mmCRTC6_MASTER_UPDATE_LOCK 0x47bd
+#define mmMASTER_UPDATE_MODE 0x1bbe
+#define mmCRTC0_MASTER_UPDATE_MODE 0x1bbe
+#define mmCRTC1_MASTER_UPDATE_MODE 0x1dbe
+#define mmCRTC2_MASTER_UPDATE_MODE 0x1fbe
+#define mmCRTC3_MASTER_UPDATE_MODE 0x41be
+#define mmCRTC4_MASTER_UPDATE_MODE 0x43be
+#define mmCRTC5_MASTER_UPDATE_MODE 0x45be
+#define mmCRTC6_MASTER_UPDATE_MODE 0x47be
+#define mmCRTC_MVP_INBAND_CNTL_INSERT 0x1bbf
+#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1bbf
+#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1dbf
+#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x1fbf
+#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x41bf
+#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x43bf
+#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x45bf
+#define mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT 0x47bf
+#define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0
+#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0
+#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1dc0
+#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1fc0
+#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41c0
+#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x43c0
+#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x45c0
+#define mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x47c0
+#define mmCRTC_MVP_STATUS 0x1bc1
+#define mmCRTC0_CRTC_MVP_STATUS 0x1bc1
+#define mmCRTC1_CRTC_MVP_STATUS 0x1dc1
+#define mmCRTC2_CRTC_MVP_STATUS 0x1fc1
+#define mmCRTC3_CRTC_MVP_STATUS 0x41c1
+#define mmCRTC4_CRTC_MVP_STATUS 0x43c1
+#define mmCRTC5_CRTC_MVP_STATUS 0x45c1
+#define mmCRTC6_CRTC_MVP_STATUS 0x47c1
+#define mmCRTC_MASTER_EN 0x1bc2
+#define mmCRTC0_CRTC_MASTER_EN 0x1bc2
+#define mmCRTC1_CRTC_MASTER_EN 0x1dc2
+#define mmCRTC2_CRTC_MASTER_EN 0x1fc2
+#define mmCRTC3_CRTC_MASTER_EN 0x41c2
+#define mmCRTC4_CRTC_MASTER_EN 0x43c2
+#define mmCRTC5_CRTC_MASTER_EN 0x45c2
+#define mmCRTC6_CRTC_MASTER_EN 0x47c2
+#define mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3
+#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3
+#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1dc3
+#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x1fc3
+#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x41c3
+#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x43c3
+#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x45c3
+#define mmCRTC6_CRTC_ALLOW_STOP_OFF_V_CNT 0x47c3
+#define mmCRTC_V_UPDATE_INT_STATUS 0x1bc4
+#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1bc4
+#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1dc4
+#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x1fc4
+#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x41c4
+#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x43c4
+#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x45c4
+#define mmCRTC6_CRTC_V_UPDATE_INT_STATUS 0x47c4
+#define mmCRTC_OVERSCAN_COLOR 0x1bc8
+#define mmCRTC0_CRTC_OVERSCAN_COLOR 0x1bc8
+#define mmCRTC1_CRTC_OVERSCAN_COLOR 0x1dc8
+#define mmCRTC2_CRTC_OVERSCAN_COLOR 0x1fc8
+#define mmCRTC3_CRTC_OVERSCAN_COLOR 0x41c8
+#define mmCRTC4_CRTC_OVERSCAN_COLOR 0x43c8
+#define mmCRTC5_CRTC_OVERSCAN_COLOR 0x45c8
+#define mmCRTC6_CRTC_OVERSCAN_COLOR 0x47c8
+#define mmCRTC_OVERSCAN_COLOR_EXT 0x1bc9
+#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x1bc9
+#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x1dc9
+#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x1fc9
+#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x41c9
+#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x43c9
+#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x45c9
+#define mmCRTC6_CRTC_OVERSCAN_COLOR_EXT 0x47c9
+#define mmCRTC_BLANK_DATA_COLOR 0x1bca
+#define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1bca
+#define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1dca
+#define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x1fca
+#define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x41ca
+#define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x43ca
+#define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x45ca
+#define mmCRTC6_CRTC_BLANK_DATA_COLOR 0x47ca
+#define mmCRTC_BLANK_DATA_COLOR_EXT 0x1bcb
+#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x1bcb
+#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x1dcb
+#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x1fcb
+#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x41cb
+#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x43cb
+#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x45cb
+#define mmCRTC6_CRTC_BLANK_DATA_COLOR_EXT 0x47cb
+#define mmCRTC_BLACK_COLOR 0x1bcc
+#define mmCRTC0_CRTC_BLACK_COLOR 0x1bcc
+#define mmCRTC1_CRTC_BLACK_COLOR 0x1dcc
+#define mmCRTC2_CRTC_BLACK_COLOR 0x1fcc
+#define mmCRTC3_CRTC_BLACK_COLOR 0x41cc
+#define mmCRTC4_CRTC_BLACK_COLOR 0x43cc
+#define mmCRTC5_CRTC_BLACK_COLOR 0x45cc
+#define mmCRTC6_CRTC_BLACK_COLOR 0x47cc
+#define mmCRTC_BLACK_COLOR_EXT 0x1bcd
+#define mmCRTC0_CRTC_BLACK_COLOR_EXT 0x1bcd
+#define mmCRTC1_CRTC_BLACK_COLOR_EXT 0x1dcd
+#define mmCRTC2_CRTC_BLACK_COLOR_EXT 0x1fcd
+#define mmCRTC3_CRTC_BLACK_COLOR_EXT 0x41cd
+#define mmCRTC4_CRTC_BLACK_COLOR_EXT 0x43cd
+#define mmCRTC5_CRTC_BLACK_COLOR_EXT 0x45cd
+#define mmCRTC6_CRTC_BLACK_COLOR_EXT 0x47cd
+#define mmCRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1dce
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1fce
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x41ce
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x43ce
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x45ce
+#define mmCRTC6_CRTC_VERTICAL_INTERRUPT0_POSITION 0x47ce
+#define mmCRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1dcf
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1fcf
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x41cf
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x43cf
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x45cf
+#define mmCRTC6_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x47cf
+#define mmCRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1dd0
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1fd0
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x41d0
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x43d0
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x45d0
+#define mmCRTC6_CRTC_VERTICAL_INTERRUPT1_POSITION 0x47d0
+#define mmCRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1dd1
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1fd1
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x41d1
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x43d1
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x45d1
+#define mmCRTC6_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x47d1
+#define mmCRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1dd2
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1fd2
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x41d2
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x43d2
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x45d2
+#define mmCRTC6_CRTC_VERTICAL_INTERRUPT2_POSITION 0x47d2
+#define mmCRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1dd3
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1fd3
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x41d3
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x43d3
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x45d3
+#define mmCRTC6_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x47d3
+#define mmCRTC_CRC_CNTL 0x1bd4
+#define mmCRTC0_CRTC_CRC_CNTL 0x1bd4
+#define mmCRTC1_CRTC_CRC_CNTL 0x1dd4
+#define mmCRTC2_CRTC_CRC_CNTL 0x1fd4
+#define mmCRTC3_CRTC_CRC_CNTL 0x41d4
+#define mmCRTC4_CRTC_CRC_CNTL 0x43d4
+#define mmCRTC5_CRTC_CRC_CNTL 0x45d4
+#define mmCRTC6_CRTC_CRC_CNTL 0x47d4
+#define mmCRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5
+#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5
+#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x1dd5
+#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x1fd5
+#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x41d5
+#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x43d5
+#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x45d5
+#define mmCRTC6_CRTC_CRC0_WINDOWA_X_CONTROL 0x47d5
+#define mmCRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6
+#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6
+#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1dd6
+#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1fd6
+#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x41d6
+#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x43d6
+#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x45d6
+#define mmCRTC6_CRTC_CRC0_WINDOWA_Y_CONTROL 0x47d6
+#define mmCRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7
+#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7
+#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x1dd7
+#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x1fd7
+#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x41d7
+#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x43d7
+#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x45d7
+#define mmCRTC6_CRTC_CRC0_WINDOWB_X_CONTROL 0x47d7
+#define mmCRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8
+#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8
+#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1dd8
+#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1fd8
+#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x41d8
+#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x43d8
+#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x45d8
+#define mmCRTC6_CRTC_CRC0_WINDOWB_Y_CONTROL 0x47d8
+#define mmCRTC_CRC0_DATA_RG 0x1bd9
+#define mmCRTC0_CRTC_CRC0_DATA_RG 0x1bd9
+#define mmCRTC1_CRTC_CRC0_DATA_RG 0x1dd9
+#define mmCRTC2_CRTC_CRC0_DATA_RG 0x1fd9
+#define mmCRTC3_CRTC_CRC0_DATA_RG 0x41d9
+#define mmCRTC4_CRTC_CRC0_DATA_RG 0x43d9
+#define mmCRTC5_CRTC_CRC0_DATA_RG 0x45d9
+#define mmCRTC6_CRTC_CRC0_DATA_RG 0x47d9
+#define mmCRTC_CRC0_DATA_B 0x1bda
+#define mmCRTC0_CRTC_CRC0_DATA_B 0x1bda
+#define mmCRTC1_CRTC_CRC0_DATA_B 0x1dda
+#define mmCRTC2_CRTC_CRC0_DATA_B 0x1fda
+#define mmCRTC3_CRTC_CRC0_DATA_B 0x41da
+#define mmCRTC4_CRTC_CRC0_DATA_B 0x43da
+#define mmCRTC5_CRTC_CRC0_DATA_B 0x45da
+#define mmCRTC6_CRTC_CRC0_DATA_B 0x47da
+#define mmCRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb
+#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb
+#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x1ddb
+#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x1fdb
+#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x41db
+#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x43db
+#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x45db
+#define mmCRTC6_CRTC_CRC1_WINDOWA_X_CONTROL 0x47db
+#define mmCRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc
+#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc
+#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1ddc
+#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1fdc
+#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x41dc
+#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x43dc
+#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x45dc
+#define mmCRTC6_CRTC_CRC1_WINDOWA_Y_CONTROL 0x47dc
+#define mmCRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd
+#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd
+#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x1ddd
+#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x1fdd
+#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x41dd
+#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x43dd
+#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x45dd
+#define mmCRTC6_CRTC_CRC1_WINDOWB_X_CONTROL 0x47dd
+#define mmCRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde
+#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde
+#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1dde
+#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1fde
+#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x41de
+#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x43de
+#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x45de
+#define mmCRTC6_CRTC_CRC1_WINDOWB_Y_CONTROL 0x47de
+#define mmCRTC_CRC1_DATA_RG 0x1bdf
+#define mmCRTC0_CRTC_CRC1_DATA_RG 0x1bdf
+#define mmCRTC1_CRTC_CRC1_DATA_RG 0x1ddf
+#define mmCRTC2_CRTC_CRC1_DATA_RG 0x1fdf
+#define mmCRTC3_CRTC_CRC1_DATA_RG 0x41df
+#define mmCRTC4_CRTC_CRC1_DATA_RG 0x43df
+#define mmCRTC5_CRTC_CRC1_DATA_RG 0x45df
+#define mmCRTC6_CRTC_CRC1_DATA_RG 0x47df
+#define mmCRTC_CRC1_DATA_B 0x1be0
+#define mmCRTC0_CRTC_CRC1_DATA_B 0x1be0
+#define mmCRTC1_CRTC_CRC1_DATA_B 0x1de0
+#define mmCRTC2_CRTC_CRC1_DATA_B 0x1fe0
+#define mmCRTC3_CRTC_CRC1_DATA_B 0x41e0
+#define mmCRTC4_CRTC_CRC1_DATA_B 0x43e0
+#define mmCRTC5_CRTC_CRC1_DATA_B 0x45e0
+#define mmCRTC6_CRTC_CRC1_DATA_B 0x47e0
+#define mmCRTC_EXT_TIMING_SYNC_CONTROL 0x1be1
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL 0x1be1
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL 0x1de1
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL 0x1fe1
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL 0x41e1
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL 0x43e1
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL 0x45e1
+#define mmCRTC6_CRTC_EXT_TIMING_SYNC_CONTROL 0x47e1
+#define mmCRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1de2
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1fe2
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x41e2
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x43e2
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x45e2
+#define mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x47e2
+#define mmCRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1de3
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1fe3
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x41e3
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x43e3
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x45e3
+#define mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x47e3
+#define mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1de4
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1fe4
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x41e4
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x43e4
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x45e4
+#define mmCRTC6_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x47e4
+#define mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1de5
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1fe5
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x41e5
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x43e5
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x45e5
+#define mmCRTC6_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x47e5
+#define mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1de6
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1fe6
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x41e6
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x43e6
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x45e6
+#define mmCRTC6_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x47e6
+#define mmCRTC_STATIC_SCREEN_CONTROL 0x1be7
+#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x1be7
+#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x1de7
+#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x1fe7
+#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x41e7
+#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x43e7
+#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x45e7
+#define mmCRTC6_CRTC_STATIC_SCREEN_CONTROL 0x47e7
+#define mmCRTC_3D_STRUCTURE_CONTROL 0x1b78
+#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1b78
+#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1d78
+#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x1f78
+#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4178
+#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4378
+#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4578
+#define mmCRTC6_CRTC_3D_STRUCTURE_CONTROL 0x4778
+#define mmCRTC_GSL_VSYNC_GAP 0x1b79
+#define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1b79
+#define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1d79
+#define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x1f79
+#define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4179
+#define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4379
+#define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4579
+#define mmCRTC6_CRTC_GSL_VSYNC_GAP 0x4779
+#define mmCRTC_GSL_WINDOW 0x1b7a
+#define mmCRTC0_CRTC_GSL_WINDOW 0x1b7a
+#define mmCRTC1_CRTC_GSL_WINDOW 0x1d7a
+#define mmCRTC2_CRTC_GSL_WINDOW 0x1f7a
+#define mmCRTC3_CRTC_GSL_WINDOW 0x417a
+#define mmCRTC4_CRTC_GSL_WINDOW 0x437a
+#define mmCRTC5_CRTC_GSL_WINDOW 0x457a
+#define mmCRTC6_CRTC_GSL_WINDOW 0x477a
+#define mmCRTC_GSL_CONTROL 0x1b7b
+#define mmCRTC0_CRTC_GSL_CONTROL 0x1b7b
+#define mmCRTC1_CRTC_GSL_CONTROL 0x1d7b
+#define mmCRTC2_CRTC_GSL_CONTROL 0x1f7b
+#define mmCRTC3_CRTC_GSL_CONTROL 0x417b
+#define mmCRTC4_CRTC_GSL_CONTROL 0x437b
+#define mmCRTC5_CRTC_GSL_CONTROL 0x457b
+#define mmCRTC6_CRTC_GSL_CONTROL 0x477b
+#define mmCRTC_TEST_DEBUG_INDEX 0x1bc6
+#define mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1bc6
+#define mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1dc6
+#define mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x1fc6
+#define mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x41c6
+#define mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x43c6
+#define mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x45c6
+#define mmCRTC6_CRTC_TEST_DEBUG_INDEX 0x47c6
+#define mmCRTC_TEST_DEBUG_DATA 0x1bc7
+#define mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1bc7
+#define mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1dc7
+#define mmCRTC2_CRTC_TEST_DEBUG_DATA 0x1fc7
+#define mmCRTC3_CRTC_TEST_DEBUG_DATA 0x41c7
+#define mmCRTC4_CRTC_TEST_DEBUG_DATA 0x43c7
+#define mmCRTC5_CRTC_TEST_DEBUG_DATA 0x45c7
+#define mmCRTC6_CRTC_TEST_DEBUG_DATA 0x47c7
+#define mmDAC_ENABLE 0x16aa
+#define mmDAC_SOURCE_SELECT 0x16ab
+#define mmDAC_CRC_EN 0x16ac
+#define mmDAC_CRC_CONTROL 0x16ad
+#define mmDAC_CRC_SIG_RGB_MASK 0x16ae
+#define mmDAC_CRC_SIG_CONTROL_MASK 0x16af
+#define mmDAC_CRC_SIG_RGB 0x16b0
+#define mmDAC_CRC_SIG_CONTROL 0x16b1
+#define mmDAC_SYNC_TRISTATE_CONTROL 0x16b2
+#define mmDAC_STEREOSYNC_SELECT 0x16b3
+#define mmDAC_AUTODETECT_CONTROL 0x16b4
+#define mmDAC_AUTODETECT_CONTROL2 0x16b5
+#define mmDAC_AUTODETECT_CONTROL3 0x16b6
+#define mmDAC_AUTODETECT_STATUS 0x16b7
+#define mmDAC_AUTODETECT_INT_CONTROL 0x16b8
+#define mmDAC_FORCE_OUTPUT_CNTL 0x16b9
+#define mmDAC_FORCE_DATA 0x16ba
+#define mmDAC_POWERDOWN 0x16bb
+#define mmDAC_CONTROL 0x16bc
+#define mmDAC_COMPARATOR_ENABLE 0x16bd
+#define mmDAC_COMPARATOR_OUTPUT 0x16be
+#define mmDAC_PWR_CNTL 0x16bf
+#define mmDAC_DFT_CONFIG 0x16c0
+#define mmDAC_FIFO_STATUS 0x16c1
+#define mmDAC_TEST_DEBUG_INDEX 0x16c2
+#define mmDAC_TEST_DEBUG_DATA 0x16c3
+#define mmPERFCOUNTER_CNTL 0x170
+#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x170
+#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x364
+#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x18c8
+#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x1b24
+#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x1d24
+#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x1f24
+#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x4124
+#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x4324
+#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x4524
+#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x4724
+#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x59a0
+#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x5f68
+#define mmPERFCOUNTER_STATE 0x171
+#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x171
+#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x365
+#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x18c9
+#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x1b25
+#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x1d25
+#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x1f25
+#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x4125
+#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x4325
+#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x4525
+#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x4725
+#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x59a1
+#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x5f69
+#define mmPERFMON_CNTL 0x173
+#define mmDC_PERFMON0_PERFMON_CNTL 0x173
+#define mmDC_PERFMON1_PERFMON_CNTL 0x367
+#define mmDC_PERFMON2_PERFMON_CNTL 0x18cb
+#define mmDC_PERFMON3_PERFMON_CNTL 0x1b27
+#define mmDC_PERFMON4_PERFMON_CNTL 0x1d27
+#define mmDC_PERFMON5_PERFMON_CNTL 0x1f27
+#define mmDC_PERFMON6_PERFMON_CNTL 0x4127
+#define mmDC_PERFMON7_PERFMON_CNTL 0x4327
+#define mmDC_PERFMON8_PERFMON_CNTL 0x4527
+#define mmDC_PERFMON9_PERFMON_CNTL 0x4727
+#define mmDC_PERFMON10_PERFMON_CNTL 0x59a3
+#define mmDC_PERFMON11_PERFMON_CNTL 0x5f6b
+#define mmPERFMON_CNTL2 0x17a
+#define mmDC_PERFMON0_PERFMON_CNTL2 0x17a
+#define mmDC_PERFMON1_PERFMON_CNTL2 0x36e
+#define mmDC_PERFMON2_PERFMON_CNTL2 0x18d2
+#define mmDC_PERFMON3_PERFMON_CNTL2 0x1b2e
+#define mmDC_PERFMON4_PERFMON_CNTL2 0x1d2e
+#define mmDC_PERFMON5_PERFMON_CNTL2 0x1f2e
+#define mmDC_PERFMON6_PERFMON_CNTL2 0x412e
+#define mmDC_PERFMON7_PERFMON_CNTL2 0x432e
+#define mmDC_PERFMON8_PERFMON_CNTL2 0x452e
+#define mmDC_PERFMON9_PERFMON_CNTL2 0x472e
+#define mmDC_PERFMON10_PERFMON_CNTL2 0x59aa
+#define mmDC_PERFMON11_PERFMON_CNTL2 0x5f72
+#define mmPERFMON_CVALUE_INT_MISC 0x172
+#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x172
+#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x366
+#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x18ca
+#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x1b26
+#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x1d26
+#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x1f26
+#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x4126
+#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x4326
+#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x4526
+#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x4726
+#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x59a2
+#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x5f6a
+#define mmPERFMON_CVALUE_LOW 0x174
+#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x174
+#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x368
+#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x18cc
+#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x1b28
+#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x1d28
+#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x1f28
+#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x4128
+#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x4328
+#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x4528
+#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x4728
+#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x59a4
+#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x5f6c
+#define mmPERFMON_HI 0x175
+#define mmDC_PERFMON0_PERFMON_HI 0x175
+#define mmDC_PERFMON1_PERFMON_HI 0x369
+#define mmDC_PERFMON2_PERFMON_HI 0x18cd
+#define mmDC_PERFMON3_PERFMON_HI 0x1b29
+#define mmDC_PERFMON4_PERFMON_HI 0x1d29
+#define mmDC_PERFMON5_PERFMON_HI 0x1f29
+#define mmDC_PERFMON6_PERFMON_HI 0x4129
+#define mmDC_PERFMON7_PERFMON_HI 0x4329
+#define mmDC_PERFMON8_PERFMON_HI 0x4529
+#define mmDC_PERFMON9_PERFMON_HI 0x4729
+#define mmDC_PERFMON10_PERFMON_HI 0x59a5
+#define mmDC_PERFMON11_PERFMON_HI 0x5f6d
+#define mmPERFMON_LOW 0x176
+#define mmDC_PERFMON0_PERFMON_LOW 0x176
+#define mmDC_PERFMON1_PERFMON_LOW 0x36a
+#define mmDC_PERFMON2_PERFMON_LOW 0x18ce
+#define mmDC_PERFMON3_PERFMON_LOW 0x1b2a
+#define mmDC_PERFMON4_PERFMON_LOW 0x1d2a
+#define mmDC_PERFMON5_PERFMON_LOW 0x1f2a
+#define mmDC_PERFMON6_PERFMON_LOW 0x412a
+#define mmDC_PERFMON7_PERFMON_LOW 0x432a
+#define mmDC_PERFMON8_PERFMON_LOW 0x452a
+#define mmDC_PERFMON9_PERFMON_LOW 0x472a
+#define mmDC_PERFMON10_PERFMON_LOW 0x59a6
+#define mmDC_PERFMON11_PERFMON_LOW 0x5f6e
+#define mmPERFMON_TEST_DEBUG_INDEX 0x177
+#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX 0x177
+#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX 0x36b
+#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX 0x18cf
+#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX 0x1b2b
+#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX 0x1d2b
+#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX 0x1f2b
+#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX 0x412b
+#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX 0x432b
+#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX 0x452b
+#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX 0x472b
+#define mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX 0x59a7
+#define mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX 0x5f6f
+#define mmPERFMON_TEST_DEBUG_DATA 0x178
+#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA 0x178
+#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA 0x36c
+#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA 0x18d0
+#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA 0x1b2c
+#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA 0x1d2c
+#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA 0x1f2c
+#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA 0x412c
+#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA 0x432c
+#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA 0x452c
+#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA 0x472c
+#define mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA 0x59a8
+#define mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA 0x5f70
+#define mmREFCLK_CNTL 0x109
+#define mmDCCG_CBUS_WRCMD_DELAY 0x110
+#define mmDPREFCLK_CNTL 0x118
+#define mmAVSYNC_COUNTER_WRITE 0x12a
+#define mmAVSYNC_COUNTER_CONTROL 0x12b
+#define mmAVSYNC_COUNTER_READ 0x12f
+#define mmDCCG_GTC_CNTL 0x120
+#define mmDCCG_GTC_DTO_INCR 0x121
+#define mmDCCG_GTC_DTO_MODULO 0x122
+#define mmDCCG_GTC_CURRENT 0x123
+#define mmDCCG_DS_DTO_INCR 0x113
+#define mmDCCG_DS_DTO_MODULO 0x114
+#define mmDCCG_DS_CNTL 0x115
+#define mmDCCG_DS_HW_CAL_INTERVAL 0x116
+#define mmDCCG_DS_DEBUG_CNTL 0x112
+#define mmDMCU_SMU_INTERRUPT_CNTL 0x12c
+#define mmSMU_CONTROL 0x12d
+#define mmSMU_INTERRUPT_CONTROL 0x12e
+#define mmDAC_CLK_ENABLE 0x128
+#define mmDVO_CLK_ENABLE 0x129
+#define mmDCCG_GATE_DISABLE_CNTL 0x134
+#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x135
+#define mmSCLK_CGTT_BLK_CTRL_REG 0x136
+#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x108
+#define mmREFCLK_CGTT_BLK_CTRL_REG 0x10b
+#define mmDCCG_CAC_STATUS 0x137
+#define mmPIXCLK1_RESYNC_CNTL 0x138
+#define mmPIXCLK2_RESYNC_CNTL 0x139
+#define mmPIXCLK0_RESYNC_CNTL 0x13a
+#define mmMICROSECOND_TIME_BASE_DIV 0x13b
+#define mmDCCG_DISP_CNTL_REG 0x13f
+#define mmMILLISECOND_TIME_BASE_DIV 0x130
+#define mmDISPCLK_FREQ_CHANGE_CNTL 0x131
+#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x132
+#define mmDCCG_PERFMON_CNTL 0x133
+#define mmDCCG_PERFMON_CNTL2 0x10e
+#define mmCRTC0_PIXEL_RATE_CNTL 0x140
+#define mmDP_DTO0_PHASE 0x141
+#define mmDP_DTO0_MODULO 0x142
+#define mmCRTC1_PIXEL_RATE_CNTL 0x144
+#define mmDP_DTO1_PHASE 0x145
+#define mmDP_DTO1_MODULO 0x146
+#define mmCRTC2_PIXEL_RATE_CNTL 0x148
+#define mmDP_DTO2_PHASE 0x149
+#define mmDP_DTO2_MODULO 0x14a
+#define mmCRTC3_PIXEL_RATE_CNTL 0x14c
+#define mmDP_DTO3_PHASE 0x14d
+#define mmDP_DTO3_MODULO 0x14e
+#define mmCRTC4_PIXEL_RATE_CNTL 0x150
+#define mmDP_DTO4_PHASE 0x151
+#define mmDP_DTO4_MODULO 0x152
+#define mmCRTC5_PIXEL_RATE_CNTL 0x154
+#define mmDP_DTO5_PHASE 0x155
+#define mmDP_DTO5_MODULO 0x156
+#define mmDCCG_SOFT_RESET 0x15f
+#define mmSYMCLKA_CLOCK_ENABLE 0x160
+#define mmSYMCLKB_CLOCK_ENABLE 0x161
+#define mmSYMCLKC_CLOCK_ENABLE 0x162
+#define mmSYMCLKD_CLOCK_ENABLE 0x163
+#define mmSYMCLKE_CLOCK_ENABLE 0x164
+#define mmSYMCLKF_CLOCK_ENABLE 0x165
+#define mmDPDBG_CLK_FORCE_CONTROL 0x10d
+#define mmDVOACLKD_CNTL 0x168
+#define mmDVOACLKC_MVP_CNTL 0x169
+#define mmDVOACLKC_CNTL 0x16a
+#define mmDCCG_AUDIO_DTO_SOURCE 0x16b
+#define mmDCCG_AUDIO_DTO0_PHASE 0x16c
+#define mmDCCG_AUDIO_DTO0_MODULE 0x16d
+#define mmDCCG_AUDIO_DTO1_PHASE 0x16e
+#define mmDCCG_AUDIO_DTO1_MODULE 0x16f
+#define mmDCCG_TEST_DEBUG_INDEX 0x17c
+#define mmDCCG_TEST_DEBUG_DATA 0x17d
+#define mmDCCG_TEST_CLK_SEL 0x17e
+#define mmCPLL_MACRO_CNTL_RESERVED0 0x5fd0
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0 0x5fd0
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0 0x5fdc
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0 0x5fe8
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0 0x5ff4
+#define mmCPLL_MACRO_CNTL_RESERVED1 0x5fd1
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1 0x5fd1
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1 0x5fdd
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1 0x5fe9
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1 0x5ff5
+#define mmCPLL_MACRO_CNTL_RESERVED2 0x5fd2
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2 0x5fd2
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2 0x5fde
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2 0x5fea
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2 0x5ff6
+#define mmCPLL_MACRO_CNTL_RESERVED3 0x5fd3
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3 0x5fd3
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3 0x5fdf
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3 0x5feb
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3 0x5ff7
+#define mmCPLL_MACRO_CNTL_RESERVED4 0x5fd4
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4 0x5fd4
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4 0x5fe0
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4 0x5fec
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4 0x5ff8
+#define mmCPLL_MACRO_CNTL_RESERVED5 0x5fd5
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5 0x5fd5
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5 0x5fe1
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5 0x5fed
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5 0x5ff9
+#define mmCPLL_MACRO_CNTL_RESERVED6 0x5fd6
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6 0x5fd6
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6 0x5fe2
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6 0x5fee
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6 0x5ffa
+#define mmCPLL_MACRO_CNTL_RESERVED7 0x5fd7
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7 0x5fd7
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7 0x5fe3
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7 0x5fef
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7 0x5ffb
+#define mmCPLL_MACRO_CNTL_RESERVED8 0x5fd8
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8 0x5fd8
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8 0x5fe4
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8 0x5ff0
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8 0x5ffc
+#define mmCPLL_MACRO_CNTL_RESERVED9 0x5fd9
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9 0x5fd9
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9 0x5fe5
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9 0x5ff1
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9 0x5ffd
+#define mmCPLL_MACRO_CNTL_RESERVED10 0x5fda
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10 0x5fda
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10 0x5fe6
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10 0x5ff2
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10 0x5ffe
+#define mmCPLL_MACRO_CNTL_RESERVED11 0x5fdb
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11 0x5fdb
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11 0x5fe7
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11 0x5ff3
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11 0x5fff
+#define mmPLL_MACRO_CNTL_RESERVED0 0x1700
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0 0x1700
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0 0x172a
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0 0x1754
+#define mmPLL_MACRO_CNTL_RESERVED1 0x1701
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1 0x1701
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1 0x172b
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1 0x1755
+#define mmPLL_MACRO_CNTL_RESERVED2 0x1702
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2 0x1702
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2 0x172c
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2 0x1756
+#define mmPLL_MACRO_CNTL_RESERVED3 0x1703
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3 0x1703
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3 0x172d
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3 0x1757
+#define mmPLL_MACRO_CNTL_RESERVED4 0x1704
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4 0x1704
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4 0x172e
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4 0x1758
+#define mmPLL_MACRO_CNTL_RESERVED5 0x1705
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5 0x1705
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5 0x172f
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5 0x1759
+#define mmPLL_MACRO_CNTL_RESERVED6 0x1706
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6 0x1706
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6 0x1730
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6 0x175a
+#define mmPLL_MACRO_CNTL_RESERVED7 0x1707
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7 0x1707
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7 0x1731
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7 0x175b
+#define mmPLL_MACRO_CNTL_RESERVED8 0x1708
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8 0x1708
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8 0x1732
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8 0x175c
+#define mmPLL_MACRO_CNTL_RESERVED9 0x1709
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9 0x1709
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9 0x1733
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9 0x175d
+#define mmPLL_MACRO_CNTL_RESERVED10 0x170a
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10 0x170a
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10 0x1734
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10 0x175e
+#define mmPLL_MACRO_CNTL_RESERVED11 0x170b
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11 0x170b
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11 0x1735
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11 0x175f
+#define mmPLL_MACRO_CNTL_RESERVED12 0x170c
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12 0x170c
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12 0x1736
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12 0x1760
+#define mmPLL_MACRO_CNTL_RESERVED13 0x170d
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13 0x170d
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13 0x1737
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13 0x1761
+#define mmPLL_MACRO_CNTL_RESERVED14 0x170e
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14 0x170e
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14 0x1738
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14 0x1762
+#define mmPLL_MACRO_CNTL_RESERVED15 0x170f
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15 0x170f
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15 0x1739
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15 0x1763
+#define mmPLL_MACRO_CNTL_RESERVED16 0x1710
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16 0x1710
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16 0x173a
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16 0x1764
+#define mmPLL_MACRO_CNTL_RESERVED17 0x1711
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17 0x1711
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17 0x173b
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17 0x1765
+#define mmPLL_MACRO_CNTL_RESERVED18 0x1712
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18 0x1712
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18 0x173c
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18 0x1766
+#define mmPLL_MACRO_CNTL_RESERVED19 0x1713
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19 0x1713
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19 0x173d
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19 0x1767
+#define mmPLL_MACRO_CNTL_RESERVED20 0x1714
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20 0x1714
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20 0x173e
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20 0x1768
+#define mmPLL_MACRO_CNTL_RESERVED21 0x1715
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21 0x1715
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21 0x173f
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21 0x1769
+#define mmPLL_MACRO_CNTL_RESERVED22 0x1716
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22 0x1716
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22 0x1740
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22 0x176a
+#define mmPLL_MACRO_CNTL_RESERVED23 0x1717
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23 0x1717
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23 0x1741
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23 0x176b
+#define mmPLL_MACRO_CNTL_RESERVED24 0x1718
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24 0x1718
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24 0x1742
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24 0x176c
+#define mmPLL_MACRO_CNTL_RESERVED25 0x1719
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25 0x1719
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25 0x1743
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25 0x176d
+#define mmPLL_MACRO_CNTL_RESERVED26 0x171a
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26 0x171a
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26 0x1744
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26 0x176e
+#define mmPLL_MACRO_CNTL_RESERVED27 0x171b
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27 0x171b
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27 0x1745
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27 0x176f
+#define mmPLL_MACRO_CNTL_RESERVED28 0x171c
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28 0x171c
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28 0x1746
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28 0x1770
+#define mmPLL_MACRO_CNTL_RESERVED29 0x171d
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29 0x171d
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29 0x1747
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29 0x1771
+#define mmPLL_MACRO_CNTL_RESERVED30 0x171e
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30 0x171e
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30 0x1748
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30 0x1772
+#define mmPLL_MACRO_CNTL_RESERVED31 0x171f
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31 0x171f
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31 0x1749
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31 0x1773
+#define mmPLL_MACRO_CNTL_RESERVED32 0x1720
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32 0x1720
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32 0x174a
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32 0x1774
+#define mmPLL_MACRO_CNTL_RESERVED33 0x1721
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33 0x1721
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33 0x174b
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33 0x1775
+#define mmPLL_MACRO_CNTL_RESERVED34 0x1722
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34 0x1722
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34 0x174c
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34 0x1776
+#define mmPLL_MACRO_CNTL_RESERVED35 0x1723
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35 0x1723
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35 0x174d
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35 0x1777
+#define mmPLL_MACRO_CNTL_RESERVED36 0x1724
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36 0x1724
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36 0x174e
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36 0x1778
+#define mmPLL_MACRO_CNTL_RESERVED37 0x1725
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37 0x1725
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37 0x174f
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37 0x1779
+#define mmPLL_MACRO_CNTL_RESERVED38 0x1726
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38 0x1726
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38 0x1750
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38 0x177a
+#define mmPLL_MACRO_CNTL_RESERVED39 0x1727
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39 0x1727
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39 0x1751
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39 0x177b
+#define mmPLL_MACRO_CNTL_RESERVED40 0x1728
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40 0x1728
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40 0x1752
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40 0x177c
+#define mmPLL_MACRO_CNTL_RESERVED41 0x1729
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41 0x1729
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41 0x1753
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41 0x177d
+#define mmDENTIST_DISPCLK_CNTL 0x124
+#define mmDCDEBUG_BUS_CLK1_SEL 0x16c4
+#define mmDCDEBUG_BUS_CLK2_SEL 0x16c5
+#define mmDCDEBUG_BUS_CLK3_SEL 0x16c6
+#define mmDCDEBUG_BUS_CLK4_SEL 0x16c7
+#define mmDCDEBUG_BUS_CLK5_SEL 0x16c8
+#define mmDCDEBUG_OUT_PIN_OVERRIDE 0x16c9
+#define mmDCDEBUG_OUT_CNTL 0x16ca
+#define mmDCDEBUG_OUT_DATA 0x16cb
+#define mmDMIF_ADDR_CONFIG 0x2f5
+#define mmDMIF_CONTROL 0x2f6
+#define mmDMIF_STATUS 0x2f7
+#define mmDMIF_HW_DEBUG 0x2f8
+#define mmDMIF_ARBITRATION_CONTROL 0x2f9
+#define mmPIPE0_ARBITRATION_CONTROL3 0x2fa
+#define mmPIPE1_ARBITRATION_CONTROL3 0x2fb
+#define mmPIPE2_ARBITRATION_CONTROL3 0x2fc
+#define mmPIPE3_ARBITRATION_CONTROL3 0x2fd
+#define mmPIPE4_ARBITRATION_CONTROL3 0x2fe
+#define mmPIPE5_ARBITRATION_CONTROL3 0x2ff
+#define mmPIPE6_ARBITRATION_CONTROL3 0x32a
+#define mmPIPE7_ARBITRATION_CONTROL3 0x32b
+#define mmDMIF_P_VMID 0x300
+#define mmDMIF_URG_OVERRIDE 0x329
+#define mmDMIF_TEST_DEBUG_INDEX 0x301
+#define mmDMIF_TEST_DEBUG_DATA 0x302
+#define ixDMIF_DEBUG02_CORE0 0x2
+#define ixDMIF_DEBUG02_CORE1 0xa
+#define mmDMIF_ADDR_CALC 0x303
+#define mmDMIF_STATUS2 0x304
+#define mmPIPE0_MAX_REQUESTS 0x305
+#define mmPIPE1_MAX_REQUESTS 0x306
+#define mmPIPE2_MAX_REQUESTS 0x307
+#define mmPIPE3_MAX_REQUESTS 0x308
+#define mmPIPE4_MAX_REQUESTS 0x309
+#define mmPIPE5_MAX_REQUESTS 0x30a
+#define mmPIPE6_MAX_REQUESTS 0x32c
+#define mmPIPE7_MAX_REQUESTS 0x32d
+#define mmLOW_POWER_TILING_CONTROL 0x30b
+#define mmMCIF_CONTROL 0x30c
+#define mmMCIF_WRITE_COMBINE_CONTROL 0x30d
+#define mmMCIF_TEST_DEBUG_INDEX 0x30e
+#define mmMCIF_TEST_DEBUG_DATA 0x30f
+#define ixIDDCCIF02_DBG_DCCIF_C 0x9
+#define ixIDDCCIF04_DBG_DCCIF_E 0xb
+#define ixIDDCCIF05_DBG_DCCIF_F 0xc
+#define mmMCIF_VMID 0x310
+#define mmMCIF_MEM_CONTROL 0x311
+#define mmCC_DC_PIPE_DIS 0x312
+#define mmMC_DC_INTERFACE_NACK_STATUS 0x313
+#define mmRBBMIF_TIMEOUT 0x314
+#define mmRBBMIF_STATUS 0x315
+#define mmRBBMIF_TIMEOUT_DIS 0x316
+#define mmRBBMIF_STATUS_FLAG 0x327
+#define mmDCI_MEM_PWR_STATUS 0x317
+#define mmDCI_MEM_PWR_STATUS2 0x318
+#define mmDCI_CLK_CNTL 0x319
+#define mmDCI_MEM_PWR_CNTL 0x31b
+#define mmDCI_MEM_PWR_CNTL2 0x31c
+#define mmDCI_MEM_PWR_CNTL3 0x31d
+#define mmDCI_SOFT_RESET 0x328
+#define mmDCI_TEST_DEBUG_INDEX 0x31e
+#define mmDCI_TEST_DEBUG_DATA 0x31f
+#define mmDCI_DEBUG_CONFIG 0x320
+#define mmPIPE0_DMIF_BUFFER_CONTROL 0x321
+#define mmPIPE1_DMIF_BUFFER_CONTROL 0x322
+#define mmPIPE2_DMIF_BUFFER_CONTROL 0x323
+#define mmPIPE3_DMIF_BUFFER_CONTROL 0x324
+#define mmPIPE4_DMIF_BUFFER_CONTROL 0x325
+#define mmPIPE5_DMIF_BUFFER_CONTROL 0x326
+#define mmDC_GENERICA 0x4800
+#define mmDC_GENERICB 0x4801
+#define mmDC_PAD_EXTERN_SIG 0x4802
+#define mmDC_REF_CLK_CNTL 0x4803
+#define mmDC_GPIO_DEBUG 0x4804
+#define mmUNIPHYA_LINK_CNTL 0x4805
+#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x4806
+#define mmUNIPHYB_LINK_CNTL 0x4807
+#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x4808
+#define mmUNIPHYC_LINK_CNTL 0x4809
+#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x480a
+#define mmUNIPHYD_LINK_CNTL 0x480b
+#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x480c
+#define mmUNIPHYE_LINK_CNTL 0x480d
+#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x480e
+#define mmUNIPHYF_LINK_CNTL 0x480f
+#define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x4810
+#define mmUNIPHYG_LINK_CNTL 0x4811
+#define mmUNIPHYG_CHANNEL_XBAR_CNTL 0x4812
+#define mmUNIPHY_IMPCAL_LINKA 0x4838
+#define mmUNIPHY_IMPCAL_LINKB 0x4839
+#define mmUNIPHY_IMPCAL_LINKC 0x483f
+#define mmUNIPHY_IMPCAL_LINKD 0x4840
+#define mmUNIPHY_IMPCAL_LINKE 0x4843
+#define mmUNIPHY_IMPCAL_LINKF 0x4844
+#define mmUNIPHY_IMPCAL_PERIOD 0x483a
+#define mmAUXP_IMPCAL 0x483b
+#define mmAUXN_IMPCAL 0x483c
+#define mmDCIO_IMPCAL_CNTL 0x483d
+#define mmUNIPHY_IMPCAL_PSW_AB 0x483e
+#define mmDCIO_IMPCAL_CNTL_CD 0x4841
+#define mmUNIPHY_IMPCAL_PSW_CD 0x4842
+#define mmDCIO_IMPCAL_CNTL_EF 0x4845
+#define mmUNIPHY_IMPCAL_PSW_EF 0x4846
+#define mmDCIO_WRCMD_DELAY 0x4816
+#define mmDC_PINSTRAPS 0x4818
+#define mmDC_DVODATA_CONFIG 0x481a
+#define mmLVTMA_PWRSEQ_CNTL 0x481b
+#define mmLVTMA_PWRSEQ_STATE 0x481c
+#define mmLVTMA_PWRSEQ_REF_DIV 0x481d
+#define mmLVTMA_PWRSEQ_DELAY1 0x481e
+#define mmLVTMA_PWRSEQ_DELAY2 0x481f
+#define mmBL_PWM_CNTL 0x4820
+#define mmBL_PWM_CNTL2 0x4821
+#define mmBL_PWM_PERIOD_CNTL 0x4822
+#define mmBL_PWM_GRP1_REG_LOCK 0x4823
+#define mmDCIO_GSL_GENLK_PAD_CNTL 0x4824
+#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x4825
+#define mmDCIO_GSL0_CNTL 0x4826
+#define mmDCIO_GSL1_CNTL 0x4827
+#define mmDCIO_GSL2_CNTL 0x4828
+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x4829
+#define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x482a
+#define mmDC_GPU_TIMER_READ 0x482b
+#define mmDC_GPU_TIMER_READ_CNTL 0x482c
+#define mmDCIO_CLOCK_CNTL 0x482d
+#define mmDCIO_DEBUG 0x482f
+#define mmDCO_DCFE_EXT_VSYNC_CNTL 0x4830
+#define mmDBG_OUT_CNTL 0x4834
+#define mmDCIO_DEBUG_CONFIG 0x4835
+#define mmDCIO_SOFT_RESET 0x4836
+#define mmDCIO_DPHY_SEL 0x4837
+#define mmDCIO_TEST_DEBUG_INDEX 0x4831
+#define mmDCIO_TEST_DEBUG_DATA 0x4832
+#define ixDCIO_DEBUG1 0x1
+#define ixDCIO_DEBUG2 0x2
+#define ixDCIO_DEBUG3 0x3
+#define ixDCIO_DEBUG4 0x4
+#define ixDCIO_DEBUG5 0x5
+#define ixDCIO_DEBUG6 0x6
+#define ixDCIO_DEBUG7 0x7
+#define ixDCIO_DEBUG8 0x8
+#define ixDCIO_DEBUG9 0x9
+#define ixDCIO_DEBUGA 0xa
+#define ixDCIO_DEBUGB 0xb
+#define ixDCIO_DEBUGC 0xc
+#define ixDCIO_DEBUGD 0xd
+#define ixDCIO_DEBUGE 0xe
+#define ixDCIO_DEBUGF 0xf
+#define ixDCIO_DEBUG10 0x10
+#define ixDCIO_DEBUG11 0x11
+#define ixDCIO_DEBUG12 0x12
+#define ixDCIO_DEBUG13 0x13
+#define ixDCIO_DEBUG14 0x14
+#define ixDCIO_DEBUG15 0x15
+#define ixDCIO_DEBUG16 0x16
+#define ixDCIO_DEBUG_ID 0x0
+#define mmDC_GPIO_GENERIC_MASK 0x4860
+#define mmDC_GPIO_GENERIC_A 0x4861
+#define mmDC_GPIO_GENERIC_EN 0x4862
+#define mmDC_GPIO_GENERIC_Y 0x4863
+#define mmDC_GPIO_DVODATA_MASK 0x4864
+#define mmDC_GPIO_DVODATA_A 0x4865
+#define mmDC_GPIO_DVODATA_EN 0x4866
+#define mmDC_GPIO_DVODATA_Y 0x4867
+#define mmDC_GPIO_DDC1_MASK 0x4868
+#define mmDC_GPIO_DDC1_A 0x4869
+#define mmDC_GPIO_DDC1_EN 0x486a
+#define mmDC_GPIO_DDC1_Y 0x486b
+#define mmDC_GPIO_DDC2_MASK 0x486c
+#define mmDC_GPIO_DDC2_A 0x486d
+#define mmDC_GPIO_DDC2_EN 0x486e
+#define mmDC_GPIO_DDC2_Y 0x486f
+#define mmDC_GPIO_DDC3_MASK 0x4870
+#define mmDC_GPIO_DDC3_A 0x4871
+#define mmDC_GPIO_DDC3_EN 0x4872
+#define mmDC_GPIO_DDC3_Y 0x4873
+#define mmDC_GPIO_DDC4_MASK 0x4874
+#define mmDC_GPIO_DDC4_A 0x4875
+#define mmDC_GPIO_DDC4_EN 0x4876
+#define mmDC_GPIO_DDC4_Y 0x4877
+#define mmDC_GPIO_DDC5_MASK 0x4878
+#define mmDC_GPIO_DDC5_A 0x4879
+#define mmDC_GPIO_DDC5_EN 0x487a
+#define mmDC_GPIO_DDC5_Y 0x487b
+#define mmDC_GPIO_DDC6_MASK 0x487c
+#define mmDC_GPIO_DDC6_A 0x487d
+#define mmDC_GPIO_DDC6_EN 0x487e
+#define mmDC_GPIO_DDC6_Y 0x487f
+#define mmDC_GPIO_DDCVGA_MASK 0x4880
+#define mmDC_GPIO_DDCVGA_A 0x4881
+#define mmDC_GPIO_DDCVGA_EN 0x4882
+#define mmDC_GPIO_DDCVGA_Y 0x4883
+#define mmDC_GPIO_SYNCA_MASK 0x4884
+#define mmDC_GPIO_SYNCA_A 0x4885
+#define mmDC_GPIO_SYNCA_EN 0x4886
+#define mmDC_GPIO_SYNCA_Y 0x4887
+#define mmDC_GPIO_GENLK_MASK 0x4888
+#define mmDC_GPIO_GENLK_A 0x4889
+#define mmDC_GPIO_GENLK_EN 0x488a
+#define mmDC_GPIO_GENLK_Y 0x488b
+#define mmDC_GPIO_HPD_MASK 0x488c
+#define mmDC_GPIO_HPD_A 0x488d
+#define mmDC_GPIO_HPD_EN 0x488e
+#define mmDC_GPIO_HPD_Y 0x488f
+#define mmDC_GPIO_PWRSEQ_MASK 0x4890
+#define mmDC_GPIO_PWRSEQ_A 0x4891
+#define mmDC_GPIO_PWRSEQ_EN 0x4892
+#define mmDC_GPIO_PWRSEQ_Y 0x4893
+#define mmDC_GPIO_PAD_STRENGTH_1 0x4894
+#define mmDC_GPIO_PAD_STRENGTH_2 0x4895
+#define mmPHY_AUX_CNTL 0x4897
+#define mmDC_GPIO_I2CPAD_A 0x4899
+#define mmDC_GPIO_I2CPAD_EN 0x489a
+#define mmDC_GPIO_I2CPAD_Y 0x489b
+#define mmDC_GPIO_I2CPAD_STRENGTH 0x489c
+#define mmDVO_STRENGTH_CONTROL 0x489d
+#define mmDVO_VREF_CONTROL 0x489e
+#define mmDVO_SKEW_ADJUST 0x489f
+#define mmDAC_MACRO_CNTL_RESERVED0 0x48b8
+#define mmDAC_MACRO_CNTL_RESERVED1 0x48b9
+#define mmDAC_MACRO_CNTL_RESERVED2 0x48ba
+#define mmDAC_MACRO_CNTL_RESERVED3 0x48bb
+#define mmUNIPHY_MACRO_CNTL_RESERVED0 0x48c0
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x48c0
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x48e0
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x4900
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x4920
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x4940
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x4960
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x4980
+#define mmUNIPHY_MACRO_CNTL_RESERVED1 0x48c1
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x48c1
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x48e1
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x4901
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x4921
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x4941
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x4961
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x4981
+#define mmUNIPHY_MACRO_CNTL_RESERVED2 0x48c2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x48c2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x48e2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x4902
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x4922
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x4942
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x4962
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x4982
+#define mmUNIPHY_MACRO_CNTL_RESERVED3 0x48c3
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x48c3
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x48e3
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x4903
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x4923
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x4943
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x4963
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x4983
+#define mmUNIPHY_MACRO_CNTL_RESERVED4 0x48c4
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x48c4
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x48e4
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x4904
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x4924
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x4944
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x4964
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x4984
+#define mmUNIPHY_MACRO_CNTL_RESERVED5 0x48c5
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x48c5
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x48e5
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x4905
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x4925
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x4945
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x4965
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x4985
+#define mmUNIPHY_MACRO_CNTL_RESERVED6 0x48c6
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x48c6
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x48e6
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x4906
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x4926
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x4946
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x4966
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x4986
+#define mmUNIPHY_MACRO_CNTL_RESERVED7 0x48c7
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x48c7
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x48e7
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x4907
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x4927
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x4947
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x4967
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x4987
+#define mmUNIPHY_MACRO_CNTL_RESERVED8 0x48c8
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x48c8
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x48e8
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x4908
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x4928
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x4948
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x4968
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x4988
+#define mmUNIPHY_MACRO_CNTL_RESERVED9 0x48c9
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x48c9
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x48e9
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x4909
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x4929
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x4949
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x4969
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x4989
+#define mmUNIPHY_MACRO_CNTL_RESERVED10 0x48ca
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x48ca
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x48ea
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x490a
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x492a
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x494a
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x496a
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x498a
+#define mmUNIPHY_MACRO_CNTL_RESERVED11 0x48cb
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x48cb
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x48eb
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x490b
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x492b
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x494b
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x496b
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x498b
+#define mmUNIPHY_MACRO_CNTL_RESERVED12 0x48cc
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x48cc
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x48ec
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x490c
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x492c
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x494c
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x496c
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x498c
+#define mmUNIPHY_MACRO_CNTL_RESERVED13 0x48cd
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x48cd
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x48ed
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x490d
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x492d
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x494d
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x496d
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x498d
+#define mmUNIPHY_MACRO_CNTL_RESERVED14 0x48ce
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x48ce
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x48ee
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x490e
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x492e
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x494e
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x496e
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x498e
+#define mmUNIPHY_MACRO_CNTL_RESERVED15 0x48cf
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x48cf
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x48ef
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x490f
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x492f
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x494f
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x496f
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x498f
+#define mmUNIPHY_MACRO_CNTL_RESERVED16 0x48d0
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x48d0
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x48f0
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x4910
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x4930
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x4950
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x4970
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x4990
+#define mmUNIPHY_MACRO_CNTL_RESERVED17 0x48d1
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x48d1
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x48f1
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x4911
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x4931
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x4951
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x4971
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x4991
+#define mmUNIPHY_MACRO_CNTL_RESERVED18 0x48d2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x48d2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x48f2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x4912
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x4932
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x4952
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x4972
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x4992
+#define mmUNIPHY_MACRO_CNTL_RESERVED19 0x48d3
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x48d3
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x48f3
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x4913
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x4933
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x4953
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x4973
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x4993
+#define mmUNIPHY_MACRO_CNTL_RESERVED20 0x48d4
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x48d4
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x48f4
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x4914
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x4934
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x4954
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x4974
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x4994
+#define mmUNIPHY_MACRO_CNTL_RESERVED21 0x48d5
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x48d5
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x48f5
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x4915
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x4935
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x4955
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x4975
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x4995
+#define mmUNIPHY_MACRO_CNTL_RESERVED22 0x48d6
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x48d6
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x48f6
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x4916
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x4936
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x4956
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x4976
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x4996
+#define mmUNIPHY_MACRO_CNTL_RESERVED23 0x48d7
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x48d7
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x48f7
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x4917
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x4937
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x4957
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x4977
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x4997
+#define mmUNIPHY_MACRO_CNTL_RESERVED24 0x48d8
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x48d8
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x48f8
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x4918
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x4938
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x4958
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x4978
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x4998
+#define mmUNIPHY_MACRO_CNTL_RESERVED25 0x48d9
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x48d9
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x48f9
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x4919
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x4939
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x4959
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x4979
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x4999
+#define mmUNIPHY_MACRO_CNTL_RESERVED26 0x48da
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x48da
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x48fa
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x491a
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x493a
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x495a
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x497a
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x499a
+#define mmUNIPHY_MACRO_CNTL_RESERVED27 0x48db
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x48db
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x48fb
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x491b
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x493b
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x495b
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x497b
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x499b
+#define mmUNIPHY_MACRO_CNTL_RESERVED28 0x48dc
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x48dc
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x48fc
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x491c
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x493c
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x495c
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x497c
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x499c
+#define mmUNIPHY_MACRO_CNTL_RESERVED29 0x48dd
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x48dd
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x48fd
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x491d
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x493d
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x495d
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x497d
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x499d
+#define mmUNIPHY_MACRO_CNTL_RESERVED30 0x48de
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x48de
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x48fe
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x491e
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x493e
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x495e
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x497e
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x499e
+#define mmUNIPHY_MACRO_CNTL_RESERVED31 0x48df
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x48df
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x48ff
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x491f
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x493f
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x495f
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x497f
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x499f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED0 0x5a84
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED1 0x5a85
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED2 0x5a86
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED3 0x5a87
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED4 0x5a88
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED5 0x5a89
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED6 0x5a8a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED7 0x5a8b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED8 0x5a8c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED9 0x5a8d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED10 0x5a8e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED11 0x5a8f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED12 0x5a90
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED13 0x5a91
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED14 0x5a92
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED15 0x5a93
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED16 0x5a94
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED17 0x5a95
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED18 0x5a96
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED19 0x5a97
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED20 0x5a98
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED21 0x5a99
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED22 0x5a9a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED23 0x5a9b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED24 0x5a9c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED25 0x5a9d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED26 0x5a9e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED27 0x5a9f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED28 0x5aa0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED29 0x5aa1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED30 0x5aa2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED31 0x5aa3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED32 0x5aa4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED33 0x5aa5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED34 0x5aa6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED35 0x5aa7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED36 0x5aa8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED37 0x5aa9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED38 0x5aaa
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED39 0x5aab
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED40 0x5aac
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED41 0x5aad
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED42 0x5aae
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED43 0x5aaf
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED44 0x5ab0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED45 0x5ab1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED46 0x5ab2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED47 0x5ab3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED48 0x5ab4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED49 0x5ab5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED50 0x5ab6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED51 0x5ab7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED52 0x5ab8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED53 0x5ab9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED54 0x5aba
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED55 0x5abb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED56 0x5abc
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED57 0x5abd
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED58 0x5abe
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED59 0x5abf
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED60 0x5ac0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED61 0x5ac1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED62 0x5ac2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED63 0x5ac3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED64 0x5ac4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED65 0x5ac5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED66 0x5ac6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED67 0x5ac7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED68 0x5ac8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED69 0x5ac9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED70 0x5aca
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED71 0x5acb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED72 0x5acc
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED73 0x5acd
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED74 0x5ace
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED75 0x5acf
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED76 0x5ad0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED77 0x5ad1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED78 0x5ad2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED79 0x5ad3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED80 0x5ad4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED81 0x5ad5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED82 0x5ad6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED83 0x5ad7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED84 0x5ad8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED85 0x5ad9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED86 0x5ada
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED87 0x5adb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED88 0x5adc
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED89 0x5add
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED90 0x5ade
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED91 0x5adf
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED92 0x5ae0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED93 0x5ae1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED94 0x5ae2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED95 0x5ae3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED96 0x5ae4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED97 0x5ae5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED98 0x5ae6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED99 0x5ae7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED100 0x5ae8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED101 0x5ae9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED102 0x5aea
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED103 0x5aeb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED104 0x5aec
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED105 0x5aed
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED106 0x5aee
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED107 0x5aef
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED108 0x5af0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED109 0x5af1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED110 0x5af2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED111 0x5af3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED112 0x5af4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED113 0x5af5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED114 0x5af6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED115 0x5af7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED116 0x5af8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED117 0x5af9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED118 0x5afa
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED119 0x5afb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED120 0x5afc
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED121 0x5afd
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED122 0x5afe
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED123 0x5aff
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED124 0x5b00
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED125 0x5b01
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED126 0x5b02
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED127 0x5b03
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED128 0x5b04
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED129 0x5b05
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED130 0x5b06
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED131 0x5b07
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED132 0x5b08
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED133 0x5b09
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED134 0x5b0a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED135 0x5b0b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED136 0x5b0c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED137 0x5b0d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED138 0x5b0e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED139 0x5b0f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED140 0x5b10
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED141 0x5b11
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED142 0x5b12
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED143 0x5b13
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED144 0x5b14
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED145 0x5b15
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED146 0x5b16
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED147 0x5b17
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED148 0x5b18
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED149 0x5b19
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED150 0x5b1a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED151 0x5b1b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED152 0x5b1c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED153 0x5b1d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED154 0x5b1e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED155 0x5b1f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED156 0x5b20
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED157 0x5b21
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED158 0x5b22
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED159 0x5b23
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED160 0x5b24
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED161 0x5b25
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED162 0x5b26
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED163 0x5b27
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED164 0x5b28
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED165 0x5b29
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED166 0x5b2a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED167 0x5b2b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED168 0x5b2c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED169 0x5b2d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED170 0x5b2e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED171 0x5b2f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED172 0x5b30
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED173 0x5b31
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED174 0x5b32
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED175 0x5b33
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED176 0x5b34
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED177 0x5b35
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED178 0x5b36
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED179 0x5b37
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED180 0x5b38
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED181 0x5b39
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED182 0x5b3a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED183 0x5b3b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED184 0x5b3c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED185 0x5b3d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED186 0x5b3e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED187 0x5b3f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED188 0x5b40
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED189 0x5b41
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED190 0x5b42
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED191 0x5b43
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED192 0x5b44
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED193 0x5b45
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED194 0x5b46
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED195 0x5b47
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED196 0x5b48
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED197 0x5b49
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED198 0x5b4a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED199 0x5b4b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED200 0x5b4c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED201 0x5b4d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED202 0x5b4e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED203 0x5b4f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED204 0x5b50
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED205 0x5b51
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED206 0x5b52
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED207 0x5b53
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED208 0x5b54
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED209 0x5b55
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED210 0x5b56
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED211 0x5b57
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED212 0x5b58
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED213 0x5b59
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED214 0x5b5a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED215 0x5b5b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED216 0x5b5c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED217 0x5b5d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED218 0x5b5e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED219 0x5b5f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED220 0x5b60
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED221 0x5b61
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED222 0x5b62
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED223 0x5b63
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED224 0x5b64
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED225 0x5b65
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED226 0x5b66
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED227 0x5b67
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED228 0x5b68
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED229 0x5b69
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED230 0x5b6a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED231 0x5b6b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED232 0x5b6c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED233 0x5b6d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED234 0x5b6e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED235 0x5b6f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED236 0x5b70
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED237 0x5b71
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED238 0x5b72
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED239 0x5b73
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED240 0x5b74
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED241 0x5b75
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED242 0x5b76
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED243 0x5b77
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED244 0x5b78
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED245 0x5b79
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED246 0x5b7a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED247 0x5b7b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED248 0x5b7c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED249 0x5b7d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED250 0x5b7e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED251 0x5b7f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED252 0x5b80
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED253 0x5b81
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED254 0x5b82
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED255 0x5b83
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED256 0x5b84
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED257 0x5b85
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED258 0x5b86
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED259 0x5b87
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED260 0x5b88
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED261 0x5b89
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED262 0x5b8a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED263 0x5b8b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED264 0x5b8c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED265 0x5b8d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED266 0x5b8e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED267 0x5b8f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED268 0x5b90
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED269 0x5b91
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED270 0x5b92
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED271 0x5b93
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED272 0x5b94
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED273 0x5b95
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED274 0x5b96
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED275 0x5b97
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED276 0x5b98
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED277 0x5b99
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED278 0x5b9a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED279 0x5b9b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED280 0x5b9c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED281 0x5b9d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED282 0x5b9e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED283 0x5b9f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED284 0x5ba0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED285 0x5ba1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED286 0x5ba2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED287 0x5ba3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED288 0x5ba4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED289 0x5ba5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED290 0x5ba6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED291 0x5ba7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED292 0x5ba8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED293 0x5ba9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED294 0x5baa
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED295 0x5bab
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED296 0x5bac
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED297 0x5bad
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED298 0x5bae
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED299 0x5baf
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED300 0x5bb0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED301 0x5bb1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED302 0x5bb2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED303 0x5bb3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED304 0x5bb4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED305 0x5bb5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED306 0x5bb6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED307 0x5bb7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED308 0x5bb8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED309 0x5bb9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED310 0x5bba
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED311 0x5bbb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED312 0x5bbc
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED313 0x5bbd
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED314 0x5bbe
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED315 0x5bbf
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED316 0x5bc0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED317 0x5bc1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED318 0x5bc2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED319 0x5bc3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED320 0x5bc4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED321 0x5bc5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED322 0x5bc6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED323 0x5bc7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED324 0x5bc8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED325 0x5bc9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED326 0x5bca
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED327 0x5bcb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED328 0x5bcc
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED329 0x5bcd
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED330 0x5bce
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED331 0x5bcf
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED332 0x5bd0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED333 0x5bd1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED334 0x5bd2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED335 0x5bd3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED336 0x5bd4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED337 0x5bd5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED338 0x5bd6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED339 0x5bd7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED340 0x5bd8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED341 0x5bd9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED342 0x5bda
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED343 0x5bdb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED344 0x5bdc
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED345 0x5bdd
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED346 0x5bde
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED347 0x5bdf
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED348 0x5be0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED349 0x5be1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED350 0x5be2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED351 0x5be3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED352 0x5be4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED353 0x5be5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED354 0x5be6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED355 0x5be7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED356 0x5be8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED357 0x5be9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED358 0x5bea
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED359 0x5beb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED360 0x5bec
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED361 0x5bed
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED362 0x5bee
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED363 0x5bef
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED364 0x5bf0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED365 0x5bf1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED366 0x5bf2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED367 0x5bf3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED368 0x5bf4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED369 0x5bf5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED370 0x5bf6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED371 0x5bf7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED372 0x5bf8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED373 0x5bf9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED374 0x5bfa
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED375 0x5bfb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED376 0x5bfc
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED377 0x5bfd
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED378 0x5bfe
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED379 0x5bff
+#define mmDPHY_MACRO_CNTL_RESERVED0 0x5d98
+#define mmDPHY_MACRO_CNTL_RESERVED1 0x5d99
+#define mmDPHY_MACRO_CNTL_RESERVED2 0x5d9a
+#define mmDPHY_MACRO_CNTL_RESERVED3 0x5d9b
+#define mmDPHY_MACRO_CNTL_RESERVED4 0x5d9c
+#define mmDPHY_MACRO_CNTL_RESERVED5 0x5d9d
+#define mmDPHY_MACRO_CNTL_RESERVED6 0x5d9e
+#define mmDPHY_MACRO_CNTL_RESERVED7 0x5d9f
+#define mmDPHY_MACRO_CNTL_RESERVED8 0x5da0
+#define mmDPHY_MACRO_CNTL_RESERVED9 0x5da1
+#define mmDPHY_MACRO_CNTL_RESERVED10 0x5da2
+#define mmDPHY_MACRO_CNTL_RESERVED11 0x5da3
+#define mmDPHY_MACRO_CNTL_RESERVED12 0x5da4
+#define mmDPHY_MACRO_CNTL_RESERVED13 0x5da5
+#define mmDPHY_MACRO_CNTL_RESERVED14 0x5da6
+#define mmDPHY_MACRO_CNTL_RESERVED15 0x5da7
+#define mmDPHY_MACRO_CNTL_RESERVED16 0x5da8
+#define mmDPHY_MACRO_CNTL_RESERVED17 0x5da9
+#define mmDPHY_MACRO_CNTL_RESERVED18 0x5daa
+#define mmDPHY_MACRO_CNTL_RESERVED19 0x5dab
+#define mmDPHY_MACRO_CNTL_RESERVED20 0x5dac
+#define mmDPHY_MACRO_CNTL_RESERVED21 0x5dad
+#define mmDPHY_MACRO_CNTL_RESERVED22 0x5dae
+#define mmDPHY_MACRO_CNTL_RESERVED23 0x5daf
+#define mmDPHY_MACRO_CNTL_RESERVED24 0x5db0
+#define mmDPHY_MACRO_CNTL_RESERVED25 0x5db1
+#define mmDPHY_MACRO_CNTL_RESERVED26 0x5db2
+#define mmDPHY_MACRO_CNTL_RESERVED27 0x5db3
+#define mmDPHY_MACRO_CNTL_RESERVED28 0x5db4
+#define mmDPHY_MACRO_CNTL_RESERVED29 0x5db5
+#define mmDPHY_MACRO_CNTL_RESERVED30 0x5db6
+#define mmDPHY_MACRO_CNTL_RESERVED31 0x5db7
+#define mmDPHY_MACRO_CNTL_RESERVED32 0x5db8
+#define mmDPHY_MACRO_CNTL_RESERVED33 0x5db9
+#define mmDPHY_MACRO_CNTL_RESERVED34 0x5dba
+#define mmDPHY_MACRO_CNTL_RESERVED35 0x5dbb
+#define mmDPHY_MACRO_CNTL_RESERVED36 0x5dbc
+#define mmDPHY_MACRO_CNTL_RESERVED37 0x5dbd
+#define mmDPHY_MACRO_CNTL_RESERVED38 0x5dbe
+#define mmDPHY_MACRO_CNTL_RESERVED39 0x5dbf
+#define mmDPHY_MACRO_CNTL_RESERVED40 0x5dc0
+#define mmDPHY_MACRO_CNTL_RESERVED41 0x5dc1
+#define mmDPHY_MACRO_CNTL_RESERVED42 0x5dc2
+#define mmDPHY_MACRO_CNTL_RESERVED43 0x5dc3
+#define mmDPHY_MACRO_CNTL_RESERVED44 0x5dc4
+#define mmDPHY_MACRO_CNTL_RESERVED45 0x5dc5
+#define mmDPHY_MACRO_CNTL_RESERVED46 0x5dc6
+#define mmDPHY_MACRO_CNTL_RESERVED47 0x5dc7
+#define mmDPHY_MACRO_CNTL_RESERVED48 0x5dc8
+#define mmDPHY_MACRO_CNTL_RESERVED49 0x5dc9
+#define mmDPHY_MACRO_CNTL_RESERVED50 0x5dca
+#define mmDPHY_MACRO_CNTL_RESERVED51 0x5dcb
+#define mmDPHY_MACRO_CNTL_RESERVED52 0x5dcc
+#define mmDPHY_MACRO_CNTL_RESERVED53 0x5dcd
+#define mmDPHY_MACRO_CNTL_RESERVED54 0x5dce
+#define mmDPHY_MACRO_CNTL_RESERVED55 0x5dcf
+#define mmDPHY_MACRO_CNTL_RESERVED56 0x5dd0
+#define mmDPHY_MACRO_CNTL_RESERVED57 0x5dd1
+#define mmDPHY_MACRO_CNTL_RESERVED58 0x5dd2
+#define mmDPHY_MACRO_CNTL_RESERVED59 0x5dd3
+#define mmDPHY_MACRO_CNTL_RESERVED60 0x5dd4
+#define mmDPHY_MACRO_CNTL_RESERVED61 0x5dd5
+#define mmDPHY_MACRO_CNTL_RESERVED62 0x5dd6
+#define mmDPHY_MACRO_CNTL_RESERVED63 0x5dd7
+#define mmGRPH_ENABLE 0x1a00
+#define mmDCP0_GRPH_ENABLE 0x1a00
+#define mmDCP1_GRPH_ENABLE 0x1c00
+#define mmDCP2_GRPH_ENABLE 0x1e00
+#define mmDCP3_GRPH_ENABLE 0x4000
+#define mmDCP4_GRPH_ENABLE 0x4200
+#define mmDCP5_GRPH_ENABLE 0x4400
+#define mmGRPH_CONTROL 0x1a01
+#define mmDCP0_GRPH_CONTROL 0x1a01
+#define mmDCP1_GRPH_CONTROL 0x1c01
+#define mmDCP2_GRPH_CONTROL 0x1e01
+#define mmDCP3_GRPH_CONTROL 0x4001
+#define mmDCP4_GRPH_CONTROL 0x4201
+#define mmDCP5_GRPH_CONTROL 0x4401
+#define mmGRPH_LUT_10BIT_BYPASS 0x1a02
+#define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1a02
+#define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1c02
+#define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x1e02
+#define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4002
+#define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4202
+#define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4402
+#define mmGRPH_SWAP_CNTL 0x1a03
+#define mmDCP0_GRPH_SWAP_CNTL 0x1a03
+#define mmDCP1_GRPH_SWAP_CNTL 0x1c03
+#define mmDCP2_GRPH_SWAP_CNTL 0x1e03
+#define mmDCP3_GRPH_SWAP_CNTL 0x4003
+#define mmDCP4_GRPH_SWAP_CNTL 0x4203
+#define mmDCP5_GRPH_SWAP_CNTL 0x4403
+#define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04
+#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04
+#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1c04
+#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x1e04
+#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004
+#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4204
+#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4404
+#define mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1a05
+#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05
+#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1c05
+#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x1e05
+#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005
+#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4205
+#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4405
+#define mmGRPH_PITCH 0x1a06
+#define mmDCP0_GRPH_PITCH 0x1a06
+#define mmDCP1_GRPH_PITCH 0x1c06
+#define mmDCP2_GRPH_PITCH 0x1e06
+#define mmDCP3_GRPH_PITCH 0x4006
+#define mmDCP4_GRPH_PITCH 0x4206
+#define mmDCP5_GRPH_PITCH 0x4406
+#define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07
+#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07
+#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1c07
+#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1e07
+#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007
+#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4207
+#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4407
+#define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08
+#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08
+#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1c08
+#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1e08
+#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008
+#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4208
+#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4408
+#define mmGRPH_SURFACE_OFFSET_X 0x1a09
+#define mmDCP0_GRPH_SURFACE_OFFSET_X 0x1a09
+#define mmDCP1_GRPH_SURFACE_OFFSET_X 0x1c09
+#define mmDCP2_GRPH_SURFACE_OFFSET_X 0x1e09
+#define mmDCP3_GRPH_SURFACE_OFFSET_X 0x4009
+#define mmDCP4_GRPH_SURFACE_OFFSET_X 0x4209
+#define mmDCP5_GRPH_SURFACE_OFFSET_X 0x4409
+#define mmGRPH_SURFACE_OFFSET_Y 0x1a0a
+#define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1a0a
+#define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1c0a
+#define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x1e0a
+#define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x400a
+#define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x420a
+#define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x440a
+#define mmGRPH_X_START 0x1a0b
+#define mmDCP0_GRPH_X_START 0x1a0b
+#define mmDCP1_GRPH_X_START 0x1c0b
+#define mmDCP2_GRPH_X_START 0x1e0b
+#define mmDCP3_GRPH_X_START 0x400b
+#define mmDCP4_GRPH_X_START 0x420b
+#define mmDCP5_GRPH_X_START 0x440b
+#define mmGRPH_Y_START 0x1a0c
+#define mmDCP0_GRPH_Y_START 0x1a0c
+#define mmDCP1_GRPH_Y_START 0x1c0c
+#define mmDCP2_GRPH_Y_START 0x1e0c
+#define mmDCP3_GRPH_Y_START 0x400c
+#define mmDCP4_GRPH_Y_START 0x420c
+#define mmDCP5_GRPH_Y_START 0x440c
+#define mmGRPH_X_END 0x1a0d
+#define mmDCP0_GRPH_X_END 0x1a0d
+#define mmDCP1_GRPH_X_END 0x1c0d
+#define mmDCP2_GRPH_X_END 0x1e0d
+#define mmDCP3_GRPH_X_END 0x400d
+#define mmDCP4_GRPH_X_END 0x420d
+#define mmDCP5_GRPH_X_END 0x440d
+#define mmGRPH_Y_END 0x1a0e
+#define mmDCP0_GRPH_Y_END 0x1a0e
+#define mmDCP1_GRPH_Y_END 0x1c0e
+#define mmDCP2_GRPH_Y_END 0x1e0e
+#define mmDCP3_GRPH_Y_END 0x400e
+#define mmDCP4_GRPH_Y_END 0x420e
+#define mmDCP5_GRPH_Y_END 0x440e
+#define mmINPUT_GAMMA_CONTROL 0x1a10
+#define mmDCP0_INPUT_GAMMA_CONTROL 0x1a10
+#define mmDCP1_INPUT_GAMMA_CONTROL 0x1c10
+#define mmDCP2_INPUT_GAMMA_CONTROL 0x1e10
+#define mmDCP3_INPUT_GAMMA_CONTROL 0x4010
+#define mmDCP4_INPUT_GAMMA_CONTROL 0x4210
+#define mmDCP5_INPUT_GAMMA_CONTROL 0x4410
+#define mmGRPH_UPDATE 0x1a11
+#define mmDCP0_GRPH_UPDATE 0x1a11
+#define mmDCP1_GRPH_UPDATE 0x1c11
+#define mmDCP2_GRPH_UPDATE 0x1e11
+#define mmDCP3_GRPH_UPDATE 0x4011
+#define mmDCP4_GRPH_UPDATE 0x4211
+#define mmDCP5_GRPH_UPDATE 0x4411
+#define mmGRPH_FLIP_CONTROL 0x1a12
+#define mmDCP0_GRPH_FLIP_CONTROL 0x1a12
+#define mmDCP1_GRPH_FLIP_CONTROL 0x1c12
+#define mmDCP2_GRPH_FLIP_CONTROL 0x1e12
+#define mmDCP3_GRPH_FLIP_CONTROL 0x4012
+#define mmDCP4_GRPH_FLIP_CONTROL 0x4212
+#define mmDCP5_GRPH_FLIP_CONTROL 0x4412
+#define mmGRPH_SURFACE_ADDRESS_INUSE 0x1a13
+#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1a13
+#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1c13
+#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x1e13
+#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4013
+#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4213
+#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4413
+#define mmGRPH_DFQ_CONTROL 0x1a14
+#define mmDCP0_GRPH_DFQ_CONTROL 0x1a14
+#define mmDCP1_GRPH_DFQ_CONTROL 0x1c14
+#define mmDCP2_GRPH_DFQ_CONTROL 0x1e14
+#define mmDCP3_GRPH_DFQ_CONTROL 0x4014
+#define mmDCP4_GRPH_DFQ_CONTROL 0x4214
+#define mmDCP5_GRPH_DFQ_CONTROL 0x4414
+#define mmGRPH_DFQ_STATUS 0x1a15
+#define mmDCP0_GRPH_DFQ_STATUS 0x1a15
+#define mmDCP1_GRPH_DFQ_STATUS 0x1c15
+#define mmDCP2_GRPH_DFQ_STATUS 0x1e15
+#define mmDCP3_GRPH_DFQ_STATUS 0x4015
+#define mmDCP4_GRPH_DFQ_STATUS 0x4215
+#define mmDCP5_GRPH_DFQ_STATUS 0x4415
+#define mmGRPH_INTERRUPT_STATUS 0x1a16
+#define mmDCP0_GRPH_INTERRUPT_STATUS 0x1a16
+#define mmDCP1_GRPH_INTERRUPT_STATUS 0x1c16
+#define mmDCP2_GRPH_INTERRUPT_STATUS 0x1e16
+#define mmDCP3_GRPH_INTERRUPT_STATUS 0x4016
+#define mmDCP4_GRPH_INTERRUPT_STATUS 0x4216
+#define mmDCP5_GRPH_INTERRUPT_STATUS 0x4416
+#define mmGRPH_INTERRUPT_CONTROL 0x1a17
+#define mmDCP0_GRPH_INTERRUPT_CONTROL 0x1a17
+#define mmDCP1_GRPH_INTERRUPT_CONTROL 0x1c17
+#define mmDCP2_GRPH_INTERRUPT_CONTROL 0x1e17
+#define mmDCP3_GRPH_INTERRUPT_CONTROL 0x4017
+#define mmDCP4_GRPH_INTERRUPT_CONTROL 0x4217
+#define mmDCP5_GRPH_INTERRUPT_CONTROL 0x4417
+#define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18
+#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18
+#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1c18
+#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1e18
+#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018
+#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4218
+#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4418
+#define mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1a19
+#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1a19
+#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1c19
+#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x1e19
+#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019
+#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4219
+#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4419
+#define mmGRPH_COMPRESS_PITCH 0x1a1a
+#define mmDCP0_GRPH_COMPRESS_PITCH 0x1a1a
+#define mmDCP1_GRPH_COMPRESS_PITCH 0x1c1a
+#define mmDCP2_GRPH_COMPRESS_PITCH 0x1e1a
+#define mmDCP3_GRPH_COMPRESS_PITCH 0x401a
+#define mmDCP4_GRPH_COMPRESS_PITCH 0x421a
+#define mmDCP5_GRPH_COMPRESS_PITCH 0x441a
+#define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b
+#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b
+#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1c1b
+#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1e1b
+#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401b
+#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x421b
+#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x441b
+#define mmOVL_ENABLE 0x1a1c
+#define mmDCP0_OVL_ENABLE 0x1a1c
+#define mmDCP1_OVL_ENABLE 0x1c1c
+#define mmDCP2_OVL_ENABLE 0x1e1c
+#define mmDCP3_OVL_ENABLE 0x401c
+#define mmDCP4_OVL_ENABLE 0x421c
+#define mmDCP5_OVL_ENABLE 0x441c
+#define mmOVL_CONTROL1 0x1a1d
+#define mmDCP0_OVL_CONTROL1 0x1a1d
+#define mmDCP1_OVL_CONTROL1 0x1c1d
+#define mmDCP2_OVL_CONTROL1 0x1e1d
+#define mmDCP3_OVL_CONTROL1 0x401d
+#define mmDCP4_OVL_CONTROL1 0x421d
+#define mmDCP5_OVL_CONTROL1 0x441d
+#define mmOVL_CONTROL2 0x1a1e
+#define mmDCP0_OVL_CONTROL2 0x1a1e
+#define mmDCP1_OVL_CONTROL2 0x1c1e
+#define mmDCP2_OVL_CONTROL2 0x1e1e
+#define mmDCP3_OVL_CONTROL2 0x401e
+#define mmDCP4_OVL_CONTROL2 0x421e
+#define mmDCP5_OVL_CONTROL2 0x441e
+#define mmOVL_SWAP_CNTL 0x1a1f
+#define mmDCP0_OVL_SWAP_CNTL 0x1a1f
+#define mmDCP1_OVL_SWAP_CNTL 0x1c1f
+#define mmDCP2_OVL_SWAP_CNTL 0x1e1f
+#define mmDCP3_OVL_SWAP_CNTL 0x401f
+#define mmDCP4_OVL_SWAP_CNTL 0x421f
+#define mmDCP5_OVL_SWAP_CNTL 0x441f
+#define mmOVL_SURFACE_ADDRESS 0x1a20
+#define mmDCP0_OVL_SURFACE_ADDRESS 0x1a20
+#define mmDCP1_OVL_SURFACE_ADDRESS 0x1c20
+#define mmDCP2_OVL_SURFACE_ADDRESS 0x1e20
+#define mmDCP3_OVL_SURFACE_ADDRESS 0x4020
+#define mmDCP4_OVL_SURFACE_ADDRESS 0x4220
+#define mmDCP5_OVL_SURFACE_ADDRESS 0x4420
+#define mmOVL_PITCH 0x1a21
+#define mmDCP0_OVL_PITCH 0x1a21
+#define mmDCP1_OVL_PITCH 0x1c21
+#define mmDCP2_OVL_PITCH 0x1e21
+#define mmDCP3_OVL_PITCH 0x4021
+#define mmDCP4_OVL_PITCH 0x4221
+#define mmDCP5_OVL_PITCH 0x4421
+#define mmOVL_SURFACE_ADDRESS_HIGH 0x1a22
+#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH 0x1a22
+#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH 0x1c22
+#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH 0x1e22
+#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH 0x4022
+#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH 0x4222
+#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH 0x4422
+#define mmOVL_SURFACE_OFFSET_X 0x1a23
+#define mmDCP0_OVL_SURFACE_OFFSET_X 0x1a23
+#define mmDCP1_OVL_SURFACE_OFFSET_X 0x1c23
+#define mmDCP2_OVL_SURFACE_OFFSET_X 0x1e23
+#define mmDCP3_OVL_SURFACE_OFFSET_X 0x4023
+#define mmDCP4_OVL_SURFACE_OFFSET_X 0x4223
+#define mmDCP5_OVL_SURFACE_OFFSET_X 0x4423
+#define mmOVL_SURFACE_OFFSET_Y 0x1a24
+#define mmDCP0_OVL_SURFACE_OFFSET_Y 0x1a24
+#define mmDCP1_OVL_SURFACE_OFFSET_Y 0x1c24
+#define mmDCP2_OVL_SURFACE_OFFSET_Y 0x1e24
+#define mmDCP3_OVL_SURFACE_OFFSET_Y 0x4024
+#define mmDCP4_OVL_SURFACE_OFFSET_Y 0x4224
+#define mmDCP5_OVL_SURFACE_OFFSET_Y 0x4424
+#define mmOVL_START 0x1a25
+#define mmDCP0_OVL_START 0x1a25
+#define mmDCP1_OVL_START 0x1c25
+#define mmDCP2_OVL_START 0x1e25
+#define mmDCP3_OVL_START 0x4025
+#define mmDCP4_OVL_START 0x4225
+#define mmDCP5_OVL_START 0x4425
+#define mmOVL_END 0x1a26
+#define mmDCP0_OVL_END 0x1a26
+#define mmDCP1_OVL_END 0x1c26
+#define mmDCP2_OVL_END 0x1e26
+#define mmDCP3_OVL_END 0x4026
+#define mmDCP4_OVL_END 0x4226
+#define mmDCP5_OVL_END 0x4426
+#define mmOVL_UPDATE 0x1a27
+#define mmDCP0_OVL_UPDATE 0x1a27
+#define mmDCP1_OVL_UPDATE 0x1c27
+#define mmDCP2_OVL_UPDATE 0x1e27
+#define mmDCP3_OVL_UPDATE 0x4027
+#define mmDCP4_OVL_UPDATE 0x4227
+#define mmDCP5_OVL_UPDATE 0x4427
+#define mmOVL_SURFACE_ADDRESS_INUSE 0x1a28
+#define mmDCP0_OVL_SURFACE_ADDRESS_INUSE 0x1a28
+#define mmDCP1_OVL_SURFACE_ADDRESS_INUSE 0x1c28
+#define mmDCP2_OVL_SURFACE_ADDRESS_INUSE 0x1e28
+#define mmDCP3_OVL_SURFACE_ADDRESS_INUSE 0x4028
+#define mmDCP4_OVL_SURFACE_ADDRESS_INUSE 0x4228
+#define mmDCP5_OVL_SURFACE_ADDRESS_INUSE 0x4428
+#define mmOVL_DFQ_CONTROL 0x1a29
+#define mmDCP0_OVL_DFQ_CONTROL 0x1a29
+#define mmDCP1_OVL_DFQ_CONTROL 0x1c29
+#define mmDCP2_OVL_DFQ_CONTROL 0x1e29
+#define mmDCP3_OVL_DFQ_CONTROL 0x4029
+#define mmDCP4_OVL_DFQ_CONTROL 0x4229
+#define mmDCP5_OVL_DFQ_CONTROL 0x4429
+#define mmOVL_DFQ_STATUS 0x1a2a
+#define mmDCP0_OVL_DFQ_STATUS 0x1a2a
+#define mmDCP1_OVL_DFQ_STATUS 0x1c2a
+#define mmDCP2_OVL_DFQ_STATUS 0x1e2a
+#define mmDCP3_OVL_DFQ_STATUS 0x402a
+#define mmDCP4_OVL_DFQ_STATUS 0x422a
+#define mmDCP5_OVL_DFQ_STATUS 0x442a
+#define mmOVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b
+#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b
+#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1c2b
+#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1e2b
+#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x402b
+#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x422b
+#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x442b
+#define mmOVLSCL_EDGE_PIXEL_CNTL 0x1a2c
+#define mmDCP0_OVLSCL_EDGE_PIXEL_CNTL 0x1a2c
+#define mmDCP1_OVLSCL_EDGE_PIXEL_CNTL 0x1c2c
+#define mmDCP2_OVLSCL_EDGE_PIXEL_CNTL 0x1e2c
+#define mmDCP3_OVLSCL_EDGE_PIXEL_CNTL 0x402c
+#define mmDCP4_OVLSCL_EDGE_PIXEL_CNTL 0x422c
+#define mmDCP5_OVLSCL_EDGE_PIXEL_CNTL 0x442c
+#define mmPRESCALE_GRPH_CONTROL 0x1a2d
+#define mmDCP0_PRESCALE_GRPH_CONTROL 0x1a2d
+#define mmDCP1_PRESCALE_GRPH_CONTROL 0x1c2d
+#define mmDCP2_PRESCALE_GRPH_CONTROL 0x1e2d
+#define mmDCP3_PRESCALE_GRPH_CONTROL 0x402d
+#define mmDCP4_PRESCALE_GRPH_CONTROL 0x422d
+#define mmDCP5_PRESCALE_GRPH_CONTROL 0x442d
+#define mmPRESCALE_VALUES_GRPH_R 0x1a2e
+#define mmDCP0_PRESCALE_VALUES_GRPH_R 0x1a2e
+#define mmDCP1_PRESCALE_VALUES_GRPH_R 0x1c2e
+#define mmDCP2_PRESCALE_VALUES_GRPH_R 0x1e2e
+#define mmDCP3_PRESCALE_VALUES_GRPH_R 0x402e
+#define mmDCP4_PRESCALE_VALUES_GRPH_R 0x422e
+#define mmDCP5_PRESCALE_VALUES_GRPH_R 0x442e
+#define mmPRESCALE_VALUES_GRPH_G 0x1a2f
+#define mmDCP0_PRESCALE_VALUES_GRPH_G 0x1a2f
+#define mmDCP1_PRESCALE_VALUES_GRPH_G 0x1c2f
+#define mmDCP2_PRESCALE_VALUES_GRPH_G 0x1e2f
+#define mmDCP3_PRESCALE_VALUES_GRPH_G 0x402f
+#define mmDCP4_PRESCALE_VALUES_GRPH_G 0x422f
+#define mmDCP5_PRESCALE_VALUES_GRPH_G 0x442f
+#define mmPRESCALE_VALUES_GRPH_B 0x1a30
+#define mmDCP0_PRESCALE_VALUES_GRPH_B 0x1a30
+#define mmDCP1_PRESCALE_VALUES_GRPH_B 0x1c30
+#define mmDCP2_PRESCALE_VALUES_GRPH_B 0x1e30
+#define mmDCP3_PRESCALE_VALUES_GRPH_B 0x4030
+#define mmDCP4_PRESCALE_VALUES_GRPH_B 0x4230
+#define mmDCP5_PRESCALE_VALUES_GRPH_B 0x4430
+#define mmPRESCALE_OVL_CONTROL 0x1a31
+#define mmDCP0_PRESCALE_OVL_CONTROL 0x1a31
+#define mmDCP1_PRESCALE_OVL_CONTROL 0x1c31
+#define mmDCP2_PRESCALE_OVL_CONTROL 0x1e31
+#define mmDCP3_PRESCALE_OVL_CONTROL 0x4031
+#define mmDCP4_PRESCALE_OVL_CONTROL 0x4231
+#define mmDCP5_PRESCALE_OVL_CONTROL 0x4431
+#define mmPRESCALE_VALUES_OVL_CB 0x1a32
+#define mmDCP0_PRESCALE_VALUES_OVL_CB 0x1a32
+#define mmDCP1_PRESCALE_VALUES_OVL_CB 0x1c32
+#define mmDCP2_PRESCALE_VALUES_OVL_CB 0x1e32
+#define mmDCP3_PRESCALE_VALUES_OVL_CB 0x4032
+#define mmDCP4_PRESCALE_VALUES_OVL_CB 0x4232
+#define mmDCP5_PRESCALE_VALUES_OVL_CB 0x4432
+#define mmPRESCALE_VALUES_OVL_Y 0x1a33
+#define mmDCP0_PRESCALE_VALUES_OVL_Y 0x1a33
+#define mmDCP1_PRESCALE_VALUES_OVL_Y 0x1c33
+#define mmDCP2_PRESCALE_VALUES_OVL_Y 0x1e33
+#define mmDCP3_PRESCALE_VALUES_OVL_Y 0x4033
+#define mmDCP4_PRESCALE_VALUES_OVL_Y 0x4233
+#define mmDCP5_PRESCALE_VALUES_OVL_Y 0x4433
+#define mmPRESCALE_VALUES_OVL_CR 0x1a34
+#define mmDCP0_PRESCALE_VALUES_OVL_CR 0x1a34
+#define mmDCP1_PRESCALE_VALUES_OVL_CR 0x1c34
+#define mmDCP2_PRESCALE_VALUES_OVL_CR 0x1e34
+#define mmDCP3_PRESCALE_VALUES_OVL_CR 0x4034
+#define mmDCP4_PRESCALE_VALUES_OVL_CR 0x4234
+#define mmDCP5_PRESCALE_VALUES_OVL_CR 0x4434
+#define mmINPUT_CSC_CONTROL 0x1a35
+#define mmDCP0_INPUT_CSC_CONTROL 0x1a35
+#define mmDCP1_INPUT_CSC_CONTROL 0x1c35
+#define mmDCP2_INPUT_CSC_CONTROL 0x1e35
+#define mmDCP3_INPUT_CSC_CONTROL 0x4035
+#define mmDCP4_INPUT_CSC_CONTROL 0x4235
+#define mmDCP5_INPUT_CSC_CONTROL 0x4435
+#define mmINPUT_CSC_C11_C12 0x1a36
+#define mmDCP0_INPUT_CSC_C11_C12 0x1a36
+#define mmDCP1_INPUT_CSC_C11_C12 0x1c36
+#define mmDCP2_INPUT_CSC_C11_C12 0x1e36
+#define mmDCP3_INPUT_CSC_C11_C12 0x4036
+#define mmDCP4_INPUT_CSC_C11_C12 0x4236
+#define mmDCP5_INPUT_CSC_C11_C12 0x4436
+#define mmINPUT_CSC_C13_C14 0x1a37
+#define mmDCP0_INPUT_CSC_C13_C14 0x1a37
+#define mmDCP1_INPUT_CSC_C13_C14 0x1c37
+#define mmDCP2_INPUT_CSC_C13_C14 0x1e37
+#define mmDCP3_INPUT_CSC_C13_C14 0x4037
+#define mmDCP4_INPUT_CSC_C13_C14 0x4237
+#define mmDCP5_INPUT_CSC_C13_C14 0x4437
+#define mmINPUT_CSC_C21_C22 0x1a38
+#define mmDCP0_INPUT_CSC_C21_C22 0x1a38
+#define mmDCP1_INPUT_CSC_C21_C22 0x1c38
+#define mmDCP2_INPUT_CSC_C21_C22 0x1e38
+#define mmDCP3_INPUT_CSC_C21_C22 0x4038
+#define mmDCP4_INPUT_CSC_C21_C22 0x4238
+#define mmDCP5_INPUT_CSC_C21_C22 0x4438
+#define mmINPUT_CSC_C23_C24 0x1a39
+#define mmDCP0_INPUT_CSC_C23_C24 0x1a39
+#define mmDCP1_INPUT_CSC_C23_C24 0x1c39
+#define mmDCP2_INPUT_CSC_C23_C24 0x1e39
+#define mmDCP3_INPUT_CSC_C23_C24 0x4039
+#define mmDCP4_INPUT_CSC_C23_C24 0x4239
+#define mmDCP5_INPUT_CSC_C23_C24 0x4439
+#define mmINPUT_CSC_C31_C32 0x1a3a
+#define mmDCP0_INPUT_CSC_C31_C32 0x1a3a
+#define mmDCP1_INPUT_CSC_C31_C32 0x1c3a
+#define mmDCP2_INPUT_CSC_C31_C32 0x1e3a
+#define mmDCP3_INPUT_CSC_C31_C32 0x403a
+#define mmDCP4_INPUT_CSC_C31_C32 0x423a
+#define mmDCP5_INPUT_CSC_C31_C32 0x443a
+#define mmINPUT_CSC_C33_C34 0x1a3b
+#define mmDCP0_INPUT_CSC_C33_C34 0x1a3b
+#define mmDCP1_INPUT_CSC_C33_C34 0x1c3b
+#define mmDCP2_INPUT_CSC_C33_C34 0x1e3b
+#define mmDCP3_INPUT_CSC_C33_C34 0x403b
+#define mmDCP4_INPUT_CSC_C33_C34 0x423b
+#define mmDCP5_INPUT_CSC_C33_C34 0x443b
+#define mmOUTPUT_CSC_CONTROL 0x1a3c
+#define mmDCP0_OUTPUT_CSC_CONTROL 0x1a3c
+#define mmDCP1_OUTPUT_CSC_CONTROL 0x1c3c
+#define mmDCP2_OUTPUT_CSC_CONTROL 0x1e3c
+#define mmDCP3_OUTPUT_CSC_CONTROL 0x403c
+#define mmDCP4_OUTPUT_CSC_CONTROL 0x423c
+#define mmDCP5_OUTPUT_CSC_CONTROL 0x443c
+#define mmOUTPUT_CSC_C11_C12 0x1a3d
+#define mmDCP0_OUTPUT_CSC_C11_C12 0x1a3d
+#define mmDCP1_OUTPUT_CSC_C11_C12 0x1c3d
+#define mmDCP2_OUTPUT_CSC_C11_C12 0x1e3d
+#define mmDCP3_OUTPUT_CSC_C11_C12 0x403d
+#define mmDCP4_OUTPUT_CSC_C11_C12 0x423d
+#define mmDCP5_OUTPUT_CSC_C11_C12 0x443d
+#define mmOUTPUT_CSC_C13_C14 0x1a3e
+#define mmDCP0_OUTPUT_CSC_C13_C14 0x1a3e
+#define mmDCP1_OUTPUT_CSC_C13_C14 0x1c3e
+#define mmDCP2_OUTPUT_CSC_C13_C14 0x1e3e
+#define mmDCP3_OUTPUT_CSC_C13_C14 0x403e
+#define mmDCP4_OUTPUT_CSC_C13_C14 0x423e
+#define mmDCP5_OUTPUT_CSC_C13_C14 0x443e
+#define mmOUTPUT_CSC_C21_C22 0x1a3f
+#define mmDCP0_OUTPUT_CSC_C21_C22 0x1a3f
+#define mmDCP1_OUTPUT_CSC_C21_C22 0x1c3f
+#define mmDCP2_OUTPUT_CSC_C21_C22 0x1e3f
+#define mmDCP3_OUTPUT_CSC_C21_C22 0x403f
+#define mmDCP4_OUTPUT_CSC_C21_C22 0x423f
+#define mmDCP5_OUTPUT_CSC_C21_C22 0x443f
+#define mmOUTPUT_CSC_C23_C24 0x1a40
+#define mmDCP0_OUTPUT_CSC_C23_C24 0x1a40
+#define mmDCP1_OUTPUT_CSC_C23_C24 0x1c40
+#define mmDCP2_OUTPUT_CSC_C23_C24 0x1e40
+#define mmDCP3_OUTPUT_CSC_C23_C24 0x4040
+#define mmDCP4_OUTPUT_CSC_C23_C24 0x4240
+#define mmDCP5_OUTPUT_CSC_C23_C24 0x4440
+#define mmOUTPUT_CSC_C31_C32 0x1a41
+#define mmDCP0_OUTPUT_CSC_C31_C32 0x1a41
+#define mmDCP1_OUTPUT_CSC_C31_C32 0x1c41
+#define mmDCP2_OUTPUT_CSC_C31_C32 0x1e41
+#define mmDCP3_OUTPUT_CSC_C31_C32 0x4041
+#define mmDCP4_OUTPUT_CSC_C31_C32 0x4241
+#define mmDCP5_OUTPUT_CSC_C31_C32 0x4441
+#define mmOUTPUT_CSC_C33_C34 0x1a42
+#define mmDCP0_OUTPUT_CSC_C33_C34 0x1a42
+#define mmDCP1_OUTPUT_CSC_C33_C34 0x1c42
+#define mmDCP2_OUTPUT_CSC_C33_C34 0x1e42
+#define mmDCP3_OUTPUT_CSC_C33_C34 0x4042
+#define mmDCP4_OUTPUT_CSC_C33_C34 0x4242
+#define mmDCP5_OUTPUT_CSC_C33_C34 0x4442
+#define mmCOMM_MATRIXA_TRANS_C11_C12 0x1a43
+#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1a43
+#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1c43
+#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x1e43
+#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4043
+#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4243
+#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4443
+#define mmCOMM_MATRIXA_TRANS_C13_C14 0x1a44
+#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1a44
+#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1c44
+#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x1e44
+#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4044
+#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4244
+#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4444
+#define mmCOMM_MATRIXA_TRANS_C21_C22 0x1a45
+#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1a45
+#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1c45
+#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x1e45
+#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4045
+#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4245
+#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4445
+#define mmCOMM_MATRIXA_TRANS_C23_C24 0x1a46
+#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1a46
+#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1c46
+#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x1e46
+#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4046
+#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4246
+#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4446
+#define mmCOMM_MATRIXA_TRANS_C31_C32 0x1a47
+#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1a47
+#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1c47
+#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x1e47
+#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4047
+#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4247
+#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4447
+#define mmCOMM_MATRIXA_TRANS_C33_C34 0x1a48
+#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1a48
+#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1c48
+#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x1e48
+#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4048
+#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4248
+#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4448
+#define mmCOMM_MATRIXB_TRANS_C11_C12 0x1a49
+#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1a49
+#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1c49
+#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x1e49
+#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4049
+#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4249
+#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4449
+#define mmCOMM_MATRIXB_TRANS_C13_C14 0x1a4a
+#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1a4a
+#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1c4a
+#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x1e4a
+#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x404a
+#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x424a
+#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x444a
+#define mmCOMM_MATRIXB_TRANS_C21_C22 0x1a4b
+#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1a4b
+#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1c4b
+#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x1e4b
+#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x404b
+#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x424b
+#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x444b
+#define mmCOMM_MATRIXB_TRANS_C23_C24 0x1a4c
+#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1a4c
+#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1c4c
+#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x1e4c
+#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x404c
+#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x424c
+#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x444c
+#define mmCOMM_MATRIXB_TRANS_C31_C32 0x1a4d
+#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1a4d
+#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1c4d
+#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x1e4d
+#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x404d
+#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x424d
+#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x444d
+#define mmCOMM_MATRIXB_TRANS_C33_C34 0x1a4e
+#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1a4e
+#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1c4e
+#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x1e4e
+#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x404e
+#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x424e
+#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x444e
+#define mmDENORM_CONTROL 0x1a50
+#define mmDCP0_DENORM_CONTROL 0x1a50
+#define mmDCP1_DENORM_CONTROL 0x1c50
+#define mmDCP2_DENORM_CONTROL 0x1e50
+#define mmDCP3_DENORM_CONTROL 0x4050
+#define mmDCP4_DENORM_CONTROL 0x4250
+#define mmDCP5_DENORM_CONTROL 0x4450
+#define mmOUT_ROUND_CONTROL 0x1a51
+#define mmDCP0_OUT_ROUND_CONTROL 0x1a51
+#define mmDCP1_OUT_ROUND_CONTROL 0x1c51
+#define mmDCP2_OUT_ROUND_CONTROL 0x1e51
+#define mmDCP3_OUT_ROUND_CONTROL 0x4051
+#define mmDCP4_OUT_ROUND_CONTROL 0x4251
+#define mmDCP5_OUT_ROUND_CONTROL 0x4451
+#define mmOUT_CLAMP_CONTROL_R_CR 0x1a52
+#define mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x1a52
+#define mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x1c52
+#define mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x1e52
+#define mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x4052
+#define mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x4252
+#define mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x4452
+#define mmOUT_CLAMP_CONTROL_G_Y 0x1a9c
+#define mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x1a9c
+#define mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x1c9c
+#define mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x1e9c
+#define mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x409c
+#define mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x429c
+#define mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x449c
+#define mmOUT_CLAMP_CONTROL_B_CB 0x1a9d
+#define mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x1a9d
+#define mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x1c9d
+#define mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x1e9d
+#define mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x409d
+#define mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x429d
+#define mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x449d
+#define mmKEY_CONTROL 0x1a53
+#define mmDCP0_KEY_CONTROL 0x1a53
+#define mmDCP1_KEY_CONTROL 0x1c53
+#define mmDCP2_KEY_CONTROL 0x1e53
+#define mmDCP3_KEY_CONTROL 0x4053
+#define mmDCP4_KEY_CONTROL 0x4253
+#define mmDCP5_KEY_CONTROL 0x4453
+#define mmKEY_RANGE_ALPHA 0x1a54
+#define mmDCP0_KEY_RANGE_ALPHA 0x1a54
+#define mmDCP1_KEY_RANGE_ALPHA 0x1c54
+#define mmDCP2_KEY_RANGE_ALPHA 0x1e54
+#define mmDCP3_KEY_RANGE_ALPHA 0x4054
+#define mmDCP4_KEY_RANGE_ALPHA 0x4254
+#define mmDCP5_KEY_RANGE_ALPHA 0x4454
+#define mmKEY_RANGE_RED 0x1a55
+#define mmDCP0_KEY_RANGE_RED 0x1a55
+#define mmDCP1_KEY_RANGE_RED 0x1c55
+#define mmDCP2_KEY_RANGE_RED 0x1e55
+#define mmDCP3_KEY_RANGE_RED 0x4055
+#define mmDCP4_KEY_RANGE_RED 0x4255
+#define mmDCP5_KEY_RANGE_RED 0x4455
+#define mmKEY_RANGE_GREEN 0x1a56
+#define mmDCP0_KEY_RANGE_GREEN 0x1a56
+#define mmDCP1_KEY_RANGE_GREEN 0x1c56
+#define mmDCP2_KEY_RANGE_GREEN 0x1e56
+#define mmDCP3_KEY_RANGE_GREEN 0x4056
+#define mmDCP4_KEY_RANGE_GREEN 0x4256
+#define mmDCP5_KEY_RANGE_GREEN 0x4456
+#define mmKEY_RANGE_BLUE 0x1a57
+#define mmDCP0_KEY_RANGE_BLUE 0x1a57
+#define mmDCP1_KEY_RANGE_BLUE 0x1c57
+#define mmDCP2_KEY_RANGE_BLUE 0x1e57
+#define mmDCP3_KEY_RANGE_BLUE 0x4057
+#define mmDCP4_KEY_RANGE_BLUE 0x4257
+#define mmDCP5_KEY_RANGE_BLUE 0x4457
+#define mmDEGAMMA_CONTROL 0x1a58
+#define mmDCP0_DEGAMMA_CONTROL 0x1a58
+#define mmDCP1_DEGAMMA_CONTROL 0x1c58
+#define mmDCP2_DEGAMMA_CONTROL 0x1e58
+#define mmDCP3_DEGAMMA_CONTROL 0x4058
+#define mmDCP4_DEGAMMA_CONTROL 0x4258
+#define mmDCP5_DEGAMMA_CONTROL 0x4458
+#define mmGAMUT_REMAP_CONTROL 0x1a59
+#define mmDCP0_GAMUT_REMAP_CONTROL 0x1a59
+#define mmDCP1_GAMUT_REMAP_CONTROL 0x1c59
+#define mmDCP2_GAMUT_REMAP_CONTROL 0x1e59
+#define mmDCP3_GAMUT_REMAP_CONTROL 0x4059
+#define mmDCP4_GAMUT_REMAP_CONTROL 0x4259
+#define mmDCP5_GAMUT_REMAP_CONTROL 0x4459
+#define mmGAMUT_REMAP_C11_C12 0x1a5a
+#define mmDCP0_GAMUT_REMAP_C11_C12 0x1a5a
+#define mmDCP1_GAMUT_REMAP_C11_C12 0x1c5a
+#define mmDCP2_GAMUT_REMAP_C11_C12 0x1e5a
+#define mmDCP3_GAMUT_REMAP_C11_C12 0x405a
+#define mmDCP4_GAMUT_REMAP_C11_C12 0x425a
+#define mmDCP5_GAMUT_REMAP_C11_C12 0x445a
+#define mmGAMUT_REMAP_C13_C14 0x1a5b
+#define mmDCP0_GAMUT_REMAP_C13_C14 0x1a5b
+#define mmDCP1_GAMUT_REMAP_C13_C14 0x1c5b
+#define mmDCP2_GAMUT_REMAP_C13_C14 0x1e5b
+#define mmDCP3_GAMUT_REMAP_C13_C14 0x405b
+#define mmDCP4_GAMUT_REMAP_C13_C14 0x425b
+#define mmDCP5_GAMUT_REMAP_C13_C14 0x445b
+#define mmGAMUT_REMAP_C21_C22 0x1a5c
+#define mmDCP0_GAMUT_REMAP_C21_C22 0x1a5c
+#define mmDCP1_GAMUT_REMAP_C21_C22 0x1c5c
+#define mmDCP2_GAMUT_REMAP_C21_C22 0x1e5c
+#define mmDCP3_GAMUT_REMAP_C21_C22 0x405c
+#define mmDCP4_GAMUT_REMAP_C21_C22 0x425c
+#define mmDCP5_GAMUT_REMAP_C21_C22 0x445c
+#define mmGAMUT_REMAP_C23_C24 0x1a5d
+#define mmDCP0_GAMUT_REMAP_C23_C24 0x1a5d
+#define mmDCP1_GAMUT_REMAP_C23_C24 0x1c5d
+#define mmDCP2_GAMUT_REMAP_C23_C24 0x1e5d
+#define mmDCP3_GAMUT_REMAP_C23_C24 0x405d
+#define mmDCP4_GAMUT_REMAP_C23_C24 0x425d
+#define mmDCP5_GAMUT_REMAP_C23_C24 0x445d
+#define mmGAMUT_REMAP_C31_C32 0x1a5e
+#define mmDCP0_GAMUT_REMAP_C31_C32 0x1a5e
+#define mmDCP1_GAMUT_REMAP_C31_C32 0x1c5e
+#define mmDCP2_GAMUT_REMAP_C31_C32 0x1e5e
+#define mmDCP3_GAMUT_REMAP_C31_C32 0x405e
+#define mmDCP4_GAMUT_REMAP_C31_C32 0x425e
+#define mmDCP5_GAMUT_REMAP_C31_C32 0x445e
+#define mmGAMUT_REMAP_C33_C34 0x1a5f
+#define mmDCP0_GAMUT_REMAP_C33_C34 0x1a5f
+#define mmDCP1_GAMUT_REMAP_C33_C34 0x1c5f
+#define mmDCP2_GAMUT_REMAP_C33_C34 0x1e5f
+#define mmDCP3_GAMUT_REMAP_C33_C34 0x405f
+#define mmDCP4_GAMUT_REMAP_C33_C34 0x425f
+#define mmDCP5_GAMUT_REMAP_C33_C34 0x445f
+#define mmDCP_SPATIAL_DITHER_CNTL 0x1a60
+#define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1a60
+#define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1c60
+#define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x1e60
+#define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4060
+#define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4260
+#define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4460
+#define mmDCP_RANDOM_SEEDS 0x1a61
+#define mmDCP0_DCP_RANDOM_SEEDS 0x1a61
+#define mmDCP1_DCP_RANDOM_SEEDS 0x1c61
+#define mmDCP2_DCP_RANDOM_SEEDS 0x1e61
+#define mmDCP3_DCP_RANDOM_SEEDS 0x4061
+#define mmDCP4_DCP_RANDOM_SEEDS 0x4261
+#define mmDCP5_DCP_RANDOM_SEEDS 0x4461
+#define mmDCP_FP_CONVERTED_FIELD 0x1a65
+#define mmDCP0_DCP_FP_CONVERTED_FIELD 0x1a65
+#define mmDCP1_DCP_FP_CONVERTED_FIELD 0x1c65
+#define mmDCP2_DCP_FP_CONVERTED_FIELD 0x1e65
+#define mmDCP3_DCP_FP_CONVERTED_FIELD 0x4065
+#define mmDCP4_DCP_FP_CONVERTED_FIELD 0x4265
+#define mmDCP5_DCP_FP_CONVERTED_FIELD 0x4465
+#define mmCUR_CONTROL 0x1a66
+#define mmDCP0_CUR_CONTROL 0x1a66
+#define mmDCP1_CUR_CONTROL 0x1c66
+#define mmDCP2_CUR_CONTROL 0x1e66
+#define mmDCP3_CUR_CONTROL 0x4066
+#define mmDCP4_CUR_CONTROL 0x4266
+#define mmDCP5_CUR_CONTROL 0x4466
+#define mmCUR_SURFACE_ADDRESS 0x1a67
+#define mmDCP0_CUR_SURFACE_ADDRESS 0x1a67
+#define mmDCP1_CUR_SURFACE_ADDRESS 0x1c67
+#define mmDCP2_CUR_SURFACE_ADDRESS 0x1e67
+#define mmDCP3_CUR_SURFACE_ADDRESS 0x4067
+#define mmDCP4_CUR_SURFACE_ADDRESS 0x4267
+#define mmDCP5_CUR_SURFACE_ADDRESS 0x4467
+#define mmCUR_SIZE 0x1a68
+#define mmDCP0_CUR_SIZE 0x1a68
+#define mmDCP1_CUR_SIZE 0x1c68
+#define mmDCP2_CUR_SIZE 0x1e68
+#define mmDCP3_CUR_SIZE 0x4068
+#define mmDCP4_CUR_SIZE 0x4268
+#define mmDCP5_CUR_SIZE 0x4468
+#define mmCUR_SURFACE_ADDRESS_HIGH 0x1a69
+#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1a69
+#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1c69
+#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x1e69
+#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4069
+#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4269
+#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4469
+#define mmCUR_POSITION 0x1a6a
+#define mmDCP0_CUR_POSITION 0x1a6a
+#define mmDCP1_CUR_POSITION 0x1c6a
+#define mmDCP2_CUR_POSITION 0x1e6a
+#define mmDCP3_CUR_POSITION 0x406a
+#define mmDCP4_CUR_POSITION 0x426a
+#define mmDCP5_CUR_POSITION 0x446a
+#define mmCUR_HOT_SPOT 0x1a6b
+#define mmDCP0_CUR_HOT_SPOT 0x1a6b
+#define mmDCP1_CUR_HOT_SPOT 0x1c6b
+#define mmDCP2_CUR_HOT_SPOT 0x1e6b
+#define mmDCP3_CUR_HOT_SPOT 0x406b
+#define mmDCP4_CUR_HOT_SPOT 0x426b
+#define mmDCP5_CUR_HOT_SPOT 0x446b
+#define mmCUR_COLOR1 0x1a6c
+#define mmDCP0_CUR_COLOR1 0x1a6c
+#define mmDCP1_CUR_COLOR1 0x1c6c
+#define mmDCP2_CUR_COLOR1 0x1e6c
+#define mmDCP3_CUR_COLOR1 0x406c
+#define mmDCP4_CUR_COLOR1 0x426c
+#define mmDCP5_CUR_COLOR1 0x446c
+#define mmCUR_COLOR2 0x1a6d
+#define mmDCP0_CUR_COLOR2 0x1a6d
+#define mmDCP1_CUR_COLOR2 0x1c6d
+#define mmDCP2_CUR_COLOR2 0x1e6d
+#define mmDCP3_CUR_COLOR2 0x406d
+#define mmDCP4_CUR_COLOR2 0x426d
+#define mmDCP5_CUR_COLOR2 0x446d
+#define mmCUR_UPDATE 0x1a6e
+#define mmDCP0_CUR_UPDATE 0x1a6e
+#define mmDCP1_CUR_UPDATE 0x1c6e
+#define mmDCP2_CUR_UPDATE 0x1e6e
+#define mmDCP3_CUR_UPDATE 0x406e
+#define mmDCP4_CUR_UPDATE 0x426e
+#define mmDCP5_CUR_UPDATE 0x446e
+#define mmCUR_REQUEST_FILTER_CNTL 0x1a99
+#define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1a99
+#define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1c99
+#define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x1e99
+#define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4099
+#define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4299
+#define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4499
+#define mmCUR_STEREO_CONTROL 0x1a9a
+#define mmDCP0_CUR_STEREO_CONTROL 0x1a9a
+#define mmDCP1_CUR_STEREO_CONTROL 0x1c9a
+#define mmDCP2_CUR_STEREO_CONTROL 0x1e9a
+#define mmDCP3_CUR_STEREO_CONTROL 0x409a
+#define mmDCP4_CUR_STEREO_CONTROL 0x429a
+#define mmDCP5_CUR_STEREO_CONTROL 0x449a
+#define mmDC_LUT_RW_MODE 0x1a78
+#define mmDCP0_DC_LUT_RW_MODE 0x1a78
+#define mmDCP1_DC_LUT_RW_MODE 0x1c78
+#define mmDCP2_DC_LUT_RW_MODE 0x1e78
+#define mmDCP3_DC_LUT_RW_MODE 0x4078
+#define mmDCP4_DC_LUT_RW_MODE 0x4278
+#define mmDCP5_DC_LUT_RW_MODE 0x4478
+#define mmDC_LUT_RW_INDEX 0x1a79
+#define mmDCP0_DC_LUT_RW_INDEX 0x1a79
+#define mmDCP1_DC_LUT_RW_INDEX 0x1c79
+#define mmDCP2_DC_LUT_RW_INDEX 0x1e79
+#define mmDCP3_DC_LUT_RW_INDEX 0x4079
+#define mmDCP4_DC_LUT_RW_INDEX 0x4279
+#define mmDCP5_DC_LUT_RW_INDEX 0x4479
+#define mmDC_LUT_SEQ_COLOR 0x1a7a
+#define mmDCP0_DC_LUT_SEQ_COLOR 0x1a7a
+#define mmDCP1_DC_LUT_SEQ_COLOR 0x1c7a
+#define mmDCP2_DC_LUT_SEQ_COLOR 0x1e7a
+#define mmDCP3_DC_LUT_SEQ_COLOR 0x407a
+#define mmDCP4_DC_LUT_SEQ_COLOR 0x427a
+#define mmDCP5_DC_LUT_SEQ_COLOR 0x447a
+#define mmDC_LUT_PWL_DATA 0x1a7b
+#define mmDCP0_DC_LUT_PWL_DATA 0x1a7b
+#define mmDCP1_DC_LUT_PWL_DATA 0x1c7b
+#define mmDCP2_DC_LUT_PWL_DATA 0x1e7b
+#define mmDCP3_DC_LUT_PWL_DATA 0x407b
+#define mmDCP4_DC_LUT_PWL_DATA 0x427b
+#define mmDCP5_DC_LUT_PWL_DATA 0x447b
+#define mmDC_LUT_30_COLOR 0x1a7c
+#define mmDCP0_DC_LUT_30_COLOR 0x1a7c
+#define mmDCP1_DC_LUT_30_COLOR 0x1c7c
+#define mmDCP2_DC_LUT_30_COLOR 0x1e7c
+#define mmDCP3_DC_LUT_30_COLOR 0x407c
+#define mmDCP4_DC_LUT_30_COLOR 0x427c
+#define mmDCP5_DC_LUT_30_COLOR 0x447c
+#define mmDC_LUT_VGA_ACCESS_ENABLE 0x1a7d
+#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1a7d
+#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1c7d
+#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x1e7d
+#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x407d
+#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x427d
+#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x447d
+#define mmDC_LUT_WRITE_EN_MASK 0x1a7e
+#define mmDCP0_DC_LUT_WRITE_EN_MASK 0x1a7e
+#define mmDCP1_DC_LUT_WRITE_EN_MASK 0x1c7e
+#define mmDCP2_DC_LUT_WRITE_EN_MASK 0x1e7e
+#define mmDCP3_DC_LUT_WRITE_EN_MASK 0x407e
+#define mmDCP4_DC_LUT_WRITE_EN_MASK 0x427e
+#define mmDCP5_DC_LUT_WRITE_EN_MASK 0x447e
+#define mmDC_LUT_AUTOFILL 0x1a7f
+#define mmDCP0_DC_LUT_AUTOFILL 0x1a7f
+#define mmDCP1_DC_LUT_AUTOFILL 0x1c7f
+#define mmDCP2_DC_LUT_AUTOFILL 0x1e7f
+#define mmDCP3_DC_LUT_AUTOFILL 0x407f
+#define mmDCP4_DC_LUT_AUTOFILL 0x427f
+#define mmDCP5_DC_LUT_AUTOFILL 0x447f
+#define mmDC_LUT_CONTROL 0x1a80
+#define mmDCP0_DC_LUT_CONTROL 0x1a80
+#define mmDCP1_DC_LUT_CONTROL 0x1c80
+#define mmDCP2_DC_LUT_CONTROL 0x1e80
+#define mmDCP3_DC_LUT_CONTROL 0x4080
+#define mmDCP4_DC_LUT_CONTROL 0x4280
+#define mmDCP5_DC_LUT_CONTROL 0x4480
+#define mmDC_LUT_BLACK_OFFSET_BLUE 0x1a81
+#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1a81
+#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1c81
+#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x1e81
+#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4081
+#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4281
+#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4481
+#define mmDC_LUT_BLACK_OFFSET_GREEN 0x1a82
+#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1a82
+#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1c82
+#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x1e82
+#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4082
+#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4282
+#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4482
+#define mmDC_LUT_BLACK_OFFSET_RED 0x1a83
+#define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1a83
+#define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1c83
+#define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x1e83
+#define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4083
+#define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4283
+#define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4483
+#define mmDC_LUT_WHITE_OFFSET_BLUE 0x1a84
+#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1a84
+#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1c84
+#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x1e84
+#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4084
+#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4284
+#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4484
+#define mmDC_LUT_WHITE_OFFSET_GREEN 0x1a85
+#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1a85
+#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1c85
+#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x1e85
+#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4085
+#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4285
+#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4485
+#define mmDC_LUT_WHITE_OFFSET_RED 0x1a86
+#define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1a86
+#define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1c86
+#define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x1e86
+#define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4086
+#define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4286
+#define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4486
+#define mmDCP_CRC_CONTROL 0x1a87
+#define mmDCP0_DCP_CRC_CONTROL 0x1a87
+#define mmDCP1_DCP_CRC_CONTROL 0x1c87
+#define mmDCP2_DCP_CRC_CONTROL 0x1e87
+#define mmDCP3_DCP_CRC_CONTROL 0x4087
+#define mmDCP4_DCP_CRC_CONTROL 0x4287
+#define mmDCP5_DCP_CRC_CONTROL 0x4487
+#define mmDCP_CRC_MASK 0x1a88
+#define mmDCP0_DCP_CRC_MASK 0x1a88
+#define mmDCP1_DCP_CRC_MASK 0x1c88
+#define mmDCP2_DCP_CRC_MASK 0x1e88
+#define mmDCP3_DCP_CRC_MASK 0x4088
+#define mmDCP4_DCP_CRC_MASK 0x4288
+#define mmDCP5_DCP_CRC_MASK 0x4488
+#define mmDCP_CRC_CURRENT 0x1a89
+#define mmDCP0_DCP_CRC_CURRENT 0x1a89
+#define mmDCP1_DCP_CRC_CURRENT 0x1c89
+#define mmDCP2_DCP_CRC_CURRENT 0x1e89
+#define mmDCP3_DCP_CRC_CURRENT 0x4089
+#define mmDCP4_DCP_CRC_CURRENT 0x4289
+#define mmDCP5_DCP_CRC_CURRENT 0x4489
+#define mmDCP_CRC_LAST 0x1a8b
+#define mmDCP0_DCP_CRC_LAST 0x1a8b
+#define mmDCP1_DCP_CRC_LAST 0x1c8b
+#define mmDCP2_DCP_CRC_LAST 0x1e8b
+#define mmDCP3_DCP_CRC_LAST 0x408b
+#define mmDCP4_DCP_CRC_LAST 0x428b
+#define mmDCP5_DCP_CRC_LAST 0x448b
+#define mmDCP_DEBUG 0x1a8d
+#define mmDCP0_DCP_DEBUG 0x1a8d
+#define mmDCP1_DCP_DEBUG 0x1c8d
+#define mmDCP2_DCP_DEBUG 0x1e8d
+#define mmDCP3_DCP_DEBUG 0x408d
+#define mmDCP4_DCP_DEBUG 0x428d
+#define mmDCP5_DCP_DEBUG 0x448d
+#define mmGRPH_FLIP_RATE_CNTL 0x1a8e
+#define mmDCP0_GRPH_FLIP_RATE_CNTL 0x1a8e
+#define mmDCP1_GRPH_FLIP_RATE_CNTL 0x1c8e
+#define mmDCP2_GRPH_FLIP_RATE_CNTL 0x1e8e
+#define mmDCP3_GRPH_FLIP_RATE_CNTL 0x408e
+#define mmDCP4_GRPH_FLIP_RATE_CNTL 0x428e
+#define mmDCP5_GRPH_FLIP_RATE_CNTL 0x448e
+#define mmDCP_GSL_CONTROL 0x1a90
+#define mmDCP0_DCP_GSL_CONTROL 0x1a90
+#define mmDCP1_DCP_GSL_CONTROL 0x1c90
+#define mmDCP2_DCP_GSL_CONTROL 0x1e90
+#define mmDCP3_DCP_GSL_CONTROL 0x4090
+#define mmDCP4_DCP_GSL_CONTROL 0x4290
+#define mmDCP5_DCP_GSL_CONTROL 0x4490
+#define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91
+#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91
+#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1c91
+#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1e91
+#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091
+#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4291
+#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4491
+#define mmOVL_SECONDARY_SURFACE_ADDRESS 0x1a92
+#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS 0x1a92
+#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS 0x1c92
+#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS 0x1e92
+#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS 0x4092
+#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS 0x4292
+#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS 0x4492
+#define mmOVL_STEREOSYNC_FLIP 0x1a93
+#define mmDCP0_OVL_STEREOSYNC_FLIP 0x1a93
+#define mmDCP1_OVL_STEREOSYNC_FLIP 0x1c93
+#define mmDCP2_OVL_STEREOSYNC_FLIP 0x1e93
+#define mmDCP3_OVL_STEREOSYNC_FLIP 0x4093
+#define mmDCP4_OVL_STEREOSYNC_FLIP 0x4293
+#define mmDCP5_OVL_STEREOSYNC_FLIP 0x4493
+#define mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94
+#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94
+#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1c94
+#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1e94
+#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4094
+#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4294
+#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4494
+#define mmDCP_TEST_DEBUG_INDEX 0x1a95
+#define mmDCP0_DCP_TEST_DEBUG_INDEX 0x1a95
+#define mmDCP1_DCP_TEST_DEBUG_INDEX 0x1c95
+#define mmDCP2_DCP_TEST_DEBUG_INDEX 0x1e95
+#define mmDCP3_DCP_TEST_DEBUG_INDEX 0x4095
+#define mmDCP4_DCP_TEST_DEBUG_INDEX 0x4295
+#define mmDCP5_DCP_TEST_DEBUG_INDEX 0x4495
+#define mmDCP_TEST_DEBUG_DATA 0x1a96
+#define mmDCP0_DCP_TEST_DEBUG_DATA 0x1a96
+#define mmDCP1_DCP_TEST_DEBUG_DATA 0x1c96
+#define mmDCP2_DCP_TEST_DEBUG_DATA 0x1e96
+#define mmDCP3_DCP_TEST_DEBUG_DATA 0x4096
+#define mmDCP4_DCP_TEST_DEBUG_DATA 0x4296
+#define mmDCP5_DCP_TEST_DEBUG_DATA 0x4496
+#define mmGRPH_STEREOSYNC_FLIP 0x1a97
+#define mmDCP0_GRPH_STEREOSYNC_FLIP 0x1a97
+#define mmDCP1_GRPH_STEREOSYNC_FLIP 0x1c97
+#define mmDCP2_GRPH_STEREOSYNC_FLIP 0x1e97
+#define mmDCP3_GRPH_STEREOSYNC_FLIP 0x4097
+#define mmDCP4_GRPH_STEREOSYNC_FLIP 0x4297
+#define mmDCP5_GRPH_STEREOSYNC_FLIP 0x4497
+#define mmDCP_DEBUG2 0x1a98
+#define mmDCP0_DCP_DEBUG2 0x1a98
+#define mmDCP1_DCP_DEBUG2 0x1c98
+#define mmDCP2_DCP_DEBUG2 0x1e98
+#define mmDCP3_DCP_DEBUG2 0x4098
+#define mmDCP4_DCP_DEBUG2 0x4298
+#define mmDCP5_DCP_DEBUG2 0x4498
+#define mmHW_ROTATION 0x1a9e
+#define mmDCP0_HW_ROTATION 0x1a9e
+#define mmDCP1_HW_ROTATION 0x1c9e
+#define mmDCP2_HW_ROTATION 0x1e9e
+#define mmDCP3_HW_ROTATION 0x409e
+#define mmDCP4_HW_ROTATION 0x429e
+#define mmDCP5_HW_ROTATION 0x449e
+#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f
+#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f
+#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1c9f
+#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1e9f
+#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x409f
+#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x429f
+#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x449f
+#define mmREGAMMA_CONTROL 0x1aa0
+#define mmDCP0_REGAMMA_CONTROL 0x1aa0
+#define mmDCP1_REGAMMA_CONTROL 0x1ca0
+#define mmDCP2_REGAMMA_CONTROL 0x1ea0
+#define mmDCP3_REGAMMA_CONTROL 0x40a0
+#define mmDCP4_REGAMMA_CONTROL 0x42a0
+#define mmDCP5_REGAMMA_CONTROL 0x44a0
+#define mmREGAMMA_LUT_INDEX 0x1aa1
+#define mmDCP0_REGAMMA_LUT_INDEX 0x1aa1
+#define mmDCP1_REGAMMA_LUT_INDEX 0x1ca1
+#define mmDCP2_REGAMMA_LUT_INDEX 0x1ea1
+#define mmDCP3_REGAMMA_LUT_INDEX 0x40a1
+#define mmDCP4_REGAMMA_LUT_INDEX 0x42a1
+#define mmDCP5_REGAMMA_LUT_INDEX 0x44a1
+#define mmREGAMMA_LUT_DATA 0x1aa2
+#define mmDCP0_REGAMMA_LUT_DATA 0x1aa2
+#define mmDCP1_REGAMMA_LUT_DATA 0x1ca2
+#define mmDCP2_REGAMMA_LUT_DATA 0x1ea2
+#define mmDCP3_REGAMMA_LUT_DATA 0x40a2
+#define mmDCP4_REGAMMA_LUT_DATA 0x42a2
+#define mmDCP5_REGAMMA_LUT_DATA 0x44a2
+#define mmREGAMMA_LUT_WRITE_EN_MASK 0x1aa3
+#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1aa3
+#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1ca3
+#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x1ea3
+#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x40a3
+#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x42a3
+#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x44a3
+#define mmREGAMMA_CNTLA_START_CNTL 0x1aa4
+#define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1aa4
+#define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1ca4
+#define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x1ea4
+#define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x40a4
+#define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x42a4
+#define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x44a4
+#define mmREGAMMA_CNTLA_SLOPE_CNTL 0x1aa5
+#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1aa5
+#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1ca5
+#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x1ea5
+#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x40a5
+#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x42a5
+#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x44a5
+#define mmREGAMMA_CNTLA_END_CNTL1 0x1aa6
+#define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1aa6
+#define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1ca6
+#define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x1ea6
+#define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x40a6
+#define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x42a6
+#define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x44a6
+#define mmREGAMMA_CNTLA_END_CNTL2 0x1aa7
+#define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1aa7
+#define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1ca7
+#define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x1ea7
+#define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x40a7
+#define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x42a7
+#define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x44a7
+#define mmREGAMMA_CNTLA_REGION_0_1 0x1aa8
+#define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1aa8
+#define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1ca8
+#define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x1ea8
+#define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x40a8
+#define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x42a8
+#define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x44a8
+#define mmREGAMMA_CNTLA_REGION_2_3 0x1aa9
+#define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1aa9
+#define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1ca9
+#define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x1ea9
+#define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x40a9
+#define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x42a9
+#define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x44a9
+#define mmREGAMMA_CNTLA_REGION_4_5 0x1aaa
+#define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1aaa
+#define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1caa
+#define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x1eaa
+#define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x40aa
+#define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x42aa
+#define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x44aa
+#define mmREGAMMA_CNTLA_REGION_6_7 0x1aab
+#define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1aab
+#define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1cab
+#define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x1eab
+#define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x40ab
+#define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x42ab
+#define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x44ab
+#define mmREGAMMA_CNTLA_REGION_8_9 0x1aac
+#define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1aac
+#define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1cac
+#define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x1eac
+#define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x40ac
+#define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x42ac
+#define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x44ac
+#define mmREGAMMA_CNTLA_REGION_10_11 0x1aad
+#define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1aad
+#define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1cad
+#define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x1ead
+#define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x40ad
+#define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x42ad
+#define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x44ad
+#define mmREGAMMA_CNTLA_REGION_12_13 0x1aae
+#define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1aae
+#define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1cae
+#define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x1eae
+#define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x40ae
+#define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x42ae
+#define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x44ae
+#define mmREGAMMA_CNTLA_REGION_14_15 0x1aaf
+#define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1aaf
+#define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1caf
+#define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x1eaf
+#define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x40af
+#define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x42af
+#define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x44af
+#define mmREGAMMA_CNTLB_START_CNTL 0x1ab0
+#define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1ab0
+#define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1cb0
+#define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x1eb0
+#define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x40b0
+#define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x42b0
+#define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x44b0
+#define mmREGAMMA_CNTLB_SLOPE_CNTL 0x1ab1
+#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1ab1
+#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1cb1
+#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x1eb1
+#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x40b1
+#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x42b1
+#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x44b1
+#define mmREGAMMA_CNTLB_END_CNTL1 0x1ab2
+#define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1ab2
+#define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1cb2
+#define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x1eb2
+#define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x40b2
+#define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x42b2
+#define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x44b2
+#define mmREGAMMA_CNTLB_END_CNTL2 0x1ab3
+#define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1ab3
+#define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1cb3
+#define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x1eb3
+#define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x40b3
+#define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x42b3
+#define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x44b3
+#define mmREGAMMA_CNTLB_REGION_0_1 0x1ab4
+#define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1ab4
+#define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1cb4
+#define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x1eb4
+#define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x40b4
+#define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x42b4
+#define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x44b4
+#define mmREGAMMA_CNTLB_REGION_2_3 0x1ab5
+#define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1ab5
+#define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1cb5
+#define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x1eb5
+#define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x40b5
+#define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x42b5
+#define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x44b5
+#define mmREGAMMA_CNTLB_REGION_4_5 0x1ab6
+#define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1ab6
+#define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1cb6
+#define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x1eb6
+#define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x40b6
+#define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x42b6
+#define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x44b6
+#define mmREGAMMA_CNTLB_REGION_6_7 0x1ab7
+#define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1ab7
+#define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1cb7
+#define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x1eb7
+#define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x40b7
+#define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x42b7
+#define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x44b7
+#define mmREGAMMA_CNTLB_REGION_8_9 0x1ab8
+#define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1ab8
+#define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1cb8
+#define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x1eb8
+#define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x40b8
+#define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x42b8
+#define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x44b8
+#define mmREGAMMA_CNTLB_REGION_10_11 0x1ab9
+#define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1ab9
+#define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1cb9
+#define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x1eb9
+#define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x40b9
+#define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x42b9
+#define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x44b9
+#define mmREGAMMA_CNTLB_REGION_12_13 0x1aba
+#define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1aba
+#define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1cba
+#define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x1eba
+#define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x40ba
+#define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x42ba
+#define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x44ba
+#define mmREGAMMA_CNTLB_REGION_14_15 0x1abb
+#define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1abb
+#define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1cbb
+#define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x1ebb
+#define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x40bb
+#define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x42bb
+#define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x44bb
+#define mmALPHA_CONTROL 0x1abc
+#define mmDCP0_ALPHA_CONTROL 0x1abc
+#define mmDCP1_ALPHA_CONTROL 0x1cbc
+#define mmDCP2_ALPHA_CONTROL 0x1ebc
+#define mmDCP3_ALPHA_CONTROL 0x40bc
+#define mmDCP4_ALPHA_CONTROL 0x42bc
+#define mmDCP5_ALPHA_CONTROL 0x44bc
+#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd
+#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd
+#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1cbd
+#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1ebd
+#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x40bd
+#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x42bd
+#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x44bd
+#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe
+#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe
+#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1cbe
+#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1ebe
+#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x40be
+#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x42be
+#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x44be
+#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf
+#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf
+#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1cbf
+#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1ebf
+#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x40bf
+#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x42bf
+#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x44bf
+#define mmDIG_FE_CNTL 0x4a00
+#define mmDIG0_DIG_FE_CNTL 0x4a00
+#define mmDIG1_DIG_FE_CNTL 0x4b00
+#define mmDIG2_DIG_FE_CNTL 0x4c00
+#define mmDIG3_DIG_FE_CNTL 0x4d00
+#define mmDIG4_DIG_FE_CNTL 0x4e00
+#define mmDIG5_DIG_FE_CNTL 0x4f00
+#define mmDIG6_DIG_FE_CNTL 0x5400
+#define mmDIG_OUTPUT_CRC_CNTL 0x4a01
+#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x4a01
+#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x4b01
+#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4c01
+#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4d01
+#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4e01
+#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4f01
+#define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x5401
+#define mmDIG_OUTPUT_CRC_RESULT 0x4a02
+#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x4a02
+#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x4b02
+#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4c02
+#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4d02
+#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4e02
+#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4f02
+#define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x5402
+#define mmDIG_CLOCK_PATTERN 0x4a03
+#define mmDIG0_DIG_CLOCK_PATTERN 0x4a03
+#define mmDIG1_DIG_CLOCK_PATTERN 0x4b03
+#define mmDIG2_DIG_CLOCK_PATTERN 0x4c03
+#define mmDIG3_DIG_CLOCK_PATTERN 0x4d03
+#define mmDIG4_DIG_CLOCK_PATTERN 0x4e03
+#define mmDIG5_DIG_CLOCK_PATTERN 0x4f03
+#define mmDIG6_DIG_CLOCK_PATTERN 0x5403
+#define mmDIG_TEST_PATTERN 0x4a04
+#define mmDIG0_DIG_TEST_PATTERN 0x4a04
+#define mmDIG1_DIG_TEST_PATTERN 0x4b04
+#define mmDIG2_DIG_TEST_PATTERN 0x4c04
+#define mmDIG3_DIG_TEST_PATTERN 0x4d04
+#define mmDIG4_DIG_TEST_PATTERN 0x4e04
+#define mmDIG5_DIG_TEST_PATTERN 0x4f04
+#define mmDIG6_DIG_TEST_PATTERN 0x5404
+#define mmDIG_RANDOM_PATTERN_SEED 0x4a05
+#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x4a05
+#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x4b05
+#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4c05
+#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4d05
+#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4e05
+#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4f05
+#define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x5405
+#define mmDIG_FIFO_STATUS 0x4a06
+#define mmDIG0_DIG_FIFO_STATUS 0x4a06
+#define mmDIG1_DIG_FIFO_STATUS 0x4b06
+#define mmDIG2_DIG_FIFO_STATUS 0x4c06
+#define mmDIG3_DIG_FIFO_STATUS 0x4d06
+#define mmDIG4_DIG_FIFO_STATUS 0x4e06
+#define mmDIG5_DIG_FIFO_STATUS 0x4f06
+#define mmDIG6_DIG_FIFO_STATUS 0x5406
+#define mmDIG_DISPCLK_SWITCH_CNTL 0x4a07
+#define mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x4a07
+#define mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x4b07
+#define mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4c07
+#define mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4d07
+#define mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4e07
+#define mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4f07
+#define mmDIG6_DIG_DISPCLK_SWITCH_CNTL 0x5407
+#define mmDIG_DISPCLK_SWITCH_STATUS 0x4a08
+#define mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x4a08
+#define mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x4b08
+#define mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4c08
+#define mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4d08
+#define mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4e08
+#define mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4f08
+#define mmDIG6_DIG_DISPCLK_SWITCH_STATUS 0x5408
+#define mmHDMI_CONTROL 0x4a09
+#define mmDIG0_HDMI_CONTROL 0x4a09
+#define mmDIG1_HDMI_CONTROL 0x4b09
+#define mmDIG2_HDMI_CONTROL 0x4c09
+#define mmDIG3_HDMI_CONTROL 0x4d09
+#define mmDIG4_HDMI_CONTROL 0x4e09
+#define mmDIG5_HDMI_CONTROL 0x4f09
+#define mmDIG6_HDMI_CONTROL 0x5409
+#define mmHDMI_STATUS 0x4a0a
+#define mmDIG0_HDMI_STATUS 0x4a0a
+#define mmDIG1_HDMI_STATUS 0x4b0a
+#define mmDIG2_HDMI_STATUS 0x4c0a
+#define mmDIG3_HDMI_STATUS 0x4d0a
+#define mmDIG4_HDMI_STATUS 0x4e0a
+#define mmDIG5_HDMI_STATUS 0x4f0a
+#define mmDIG6_HDMI_STATUS 0x540a
+#define mmHDMI_AUDIO_PACKET_CONTROL 0x4a0b
+#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x4a0b
+#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x4b0b
+#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x4c0b
+#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x4d0b
+#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x4e0b
+#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4f0b
+#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x540b
+#define mmHDMI_ACR_PACKET_CONTROL 0x4a0c
+#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x4a0c
+#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x4b0c
+#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x4c0c
+#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x4d0c
+#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x4e0c
+#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4f0c
+#define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x540c
+#define mmHDMI_VBI_PACKET_CONTROL 0x4a0d
+#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x4a0d
+#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x4b0d
+#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4c0d
+#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4d0d
+#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4e0d
+#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4f0d
+#define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x540d
+#define mmHDMI_INFOFRAME_CONTROL0 0x4a0e
+#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x4a0e
+#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x4b0e
+#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4c0e
+#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4d0e
+#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4e0e
+#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4f0e
+#define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x540e
+#define mmHDMI_INFOFRAME_CONTROL1 0x4a0f
+#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x4a0f
+#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x4b0f
+#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4c0f
+#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4d0f
+#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4e0f
+#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4f0f
+#define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x540f
+#define mmHDMI_GENERIC_PACKET_CONTROL0 0x4a10
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x4a10
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x4b10
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4c10
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4d10
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4e10
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4f10
+#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x5410
+#define mmAFMT_INTERRUPT_STATUS 0x4a11
+#define mmDIG0_AFMT_INTERRUPT_STATUS 0x4a11
+#define mmDIG1_AFMT_INTERRUPT_STATUS 0x4b11
+#define mmDIG2_AFMT_INTERRUPT_STATUS 0x4c11
+#define mmDIG3_AFMT_INTERRUPT_STATUS 0x4d11
+#define mmDIG4_AFMT_INTERRUPT_STATUS 0x4e11
+#define mmDIG5_AFMT_INTERRUPT_STATUS 0x4f11
+#define mmDIG6_AFMT_INTERRUPT_STATUS 0x5411
+#define mmHDMI_GC 0x4a13
+#define mmDIG0_HDMI_GC 0x4a13
+#define mmDIG1_HDMI_GC 0x4b13
+#define mmDIG2_HDMI_GC 0x4c13
+#define mmDIG3_HDMI_GC 0x4d13
+#define mmDIG4_HDMI_GC 0x4e13
+#define mmDIG5_HDMI_GC 0x4f13
+#define mmDIG6_HDMI_GC 0x5413
+#define mmAFMT_AUDIO_PACKET_CONTROL2 0x4a14
+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x4a14
+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x4b14
+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4c14
+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4d14
+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4e14
+#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4f14
+#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x5414
+#define mmAFMT_ISRC1_0 0x4a15
+#define mmDIG0_AFMT_ISRC1_0 0x4a15
+#define mmDIG1_AFMT_ISRC1_0 0x4b15
+#define mmDIG2_AFMT_ISRC1_0 0x4c15
+#define mmDIG3_AFMT_ISRC1_0 0x4d15
+#define mmDIG4_AFMT_ISRC1_0 0x4e15
+#define mmDIG5_AFMT_ISRC1_0 0x4f15
+#define mmDIG6_AFMT_ISRC1_0 0x5415
+#define mmAFMT_ISRC1_1 0x4a16
+#define mmDIG0_AFMT_ISRC1_1 0x4a16
+#define mmDIG1_AFMT_ISRC1_1 0x4b16
+#define mmDIG2_AFMT_ISRC1_1 0x4c16
+#define mmDIG3_AFMT_ISRC1_1 0x4d16
+#define mmDIG4_AFMT_ISRC1_1 0x4e16
+#define mmDIG5_AFMT_ISRC1_1 0x4f16
+#define mmDIG6_AFMT_ISRC1_1 0x5416
+#define mmAFMT_ISRC1_2 0x4a17
+#define mmDIG0_AFMT_ISRC1_2 0x4a17
+#define mmDIG1_AFMT_ISRC1_2 0x4b17
+#define mmDIG2_AFMT_ISRC1_2 0x4c17
+#define mmDIG3_AFMT_ISRC1_2 0x4d17
+#define mmDIG4_AFMT_ISRC1_2 0x4e17
+#define mmDIG5_AFMT_ISRC1_2 0x4f17
+#define mmDIG6_AFMT_ISRC1_2 0x5417
+#define mmAFMT_ISRC1_3 0x4a18
+#define mmDIG0_AFMT_ISRC1_3 0x4a18
+#define mmDIG1_AFMT_ISRC1_3 0x4b18
+#define mmDIG2_AFMT_ISRC1_3 0x4c18
+#define mmDIG3_AFMT_ISRC1_3 0x4d18
+#define mmDIG4_AFMT_ISRC1_3 0x4e18
+#define mmDIG5_AFMT_ISRC1_3 0x4f18
+#define mmDIG6_AFMT_ISRC1_3 0x5418
+#define mmAFMT_ISRC1_4 0x4a19
+#define mmDIG0_AFMT_ISRC1_4 0x4a19
+#define mmDIG1_AFMT_ISRC1_4 0x4b19
+#define mmDIG2_AFMT_ISRC1_4 0x4c19
+#define mmDIG3_AFMT_ISRC1_4 0x4d19
+#define mmDIG4_AFMT_ISRC1_4 0x4e19
+#define mmDIG5_AFMT_ISRC1_4 0x4f19
+#define mmDIG6_AFMT_ISRC1_4 0x5419
+#define mmAFMT_ISRC2_0 0x4a1a
+#define mmDIG0_AFMT_ISRC2_0 0x4a1a
+#define mmDIG1_AFMT_ISRC2_0 0x4b1a
+#define mmDIG2_AFMT_ISRC2_0 0x4c1a
+#define mmDIG3_AFMT_ISRC2_0 0x4d1a
+#define mmDIG4_AFMT_ISRC2_0 0x4e1a
+#define mmDIG5_AFMT_ISRC2_0 0x4f1a
+#define mmDIG6_AFMT_ISRC2_0 0x541a
+#define mmAFMT_ISRC2_1 0x4a1b
+#define mmDIG0_AFMT_ISRC2_1 0x4a1b
+#define mmDIG1_AFMT_ISRC2_1 0x4b1b
+#define mmDIG2_AFMT_ISRC2_1 0x4c1b
+#define mmDIG3_AFMT_ISRC2_1 0x4d1b
+#define mmDIG4_AFMT_ISRC2_1 0x4e1b
+#define mmDIG5_AFMT_ISRC2_1 0x4f1b
+#define mmDIG6_AFMT_ISRC2_1 0x541b
+#define mmAFMT_ISRC2_2 0x4a1c
+#define mmDIG0_AFMT_ISRC2_2 0x4a1c
+#define mmDIG1_AFMT_ISRC2_2 0x4b1c
+#define mmDIG2_AFMT_ISRC2_2 0x4c1c
+#define mmDIG3_AFMT_ISRC2_2 0x4d1c
+#define mmDIG4_AFMT_ISRC2_2 0x4e1c
+#define mmDIG5_AFMT_ISRC2_2 0x4f1c
+#define mmDIG6_AFMT_ISRC2_2 0x541c
+#define mmAFMT_ISRC2_3 0x4a1d
+#define mmDIG0_AFMT_ISRC2_3 0x4a1d
+#define mmDIG1_AFMT_ISRC2_3 0x4b1d
+#define mmDIG2_AFMT_ISRC2_3 0x4c1d
+#define mmDIG3_AFMT_ISRC2_3 0x4d1d
+#define mmDIG4_AFMT_ISRC2_3 0x4e1d
+#define mmDIG5_AFMT_ISRC2_3 0x4f1d
+#define mmDIG6_AFMT_ISRC2_3 0x541d
+#define mmAFMT_AVI_INFO0 0x4a1e
+#define mmDIG0_AFMT_AVI_INFO0 0x4a1e
+#define mmDIG1_AFMT_AVI_INFO0 0x4b1e
+#define mmDIG2_AFMT_AVI_INFO0 0x4c1e
+#define mmDIG3_AFMT_AVI_INFO0 0x4d1e
+#define mmDIG4_AFMT_AVI_INFO0 0x4e1e
+#define mmDIG5_AFMT_AVI_INFO0 0x4f1e
+#define mmDIG6_AFMT_AVI_INFO0 0x541e
+#define mmAFMT_AVI_INFO1 0x4a1f
+#define mmDIG0_AFMT_AVI_INFO1 0x4a1f
+#define mmDIG1_AFMT_AVI_INFO1 0x4b1f
+#define mmDIG2_AFMT_AVI_INFO1 0x4c1f
+#define mmDIG3_AFMT_AVI_INFO1 0x4d1f
+#define mmDIG4_AFMT_AVI_INFO1 0x4e1f
+#define mmDIG5_AFMT_AVI_INFO1 0x4f1f
+#define mmDIG6_AFMT_AVI_INFO1 0x541f
+#define mmAFMT_AVI_INFO2 0x4a20
+#define mmDIG0_AFMT_AVI_INFO2 0x4a20
+#define mmDIG1_AFMT_AVI_INFO2 0x4b20
+#define mmDIG2_AFMT_AVI_INFO2 0x4c20
+#define mmDIG3_AFMT_AVI_INFO2 0x4d20
+#define mmDIG4_AFMT_AVI_INFO2 0x4e20
+#define mmDIG5_AFMT_AVI_INFO2 0x4f20
+#define mmDIG6_AFMT_AVI_INFO2 0x5420
+#define mmAFMT_AVI_INFO3 0x4a21
+#define mmDIG0_AFMT_AVI_INFO3 0x4a21
+#define mmDIG1_AFMT_AVI_INFO3 0x4b21
+#define mmDIG2_AFMT_AVI_INFO3 0x4c21
+#define mmDIG3_AFMT_AVI_INFO3 0x4d21
+#define mmDIG4_AFMT_AVI_INFO3 0x4e21
+#define mmDIG5_AFMT_AVI_INFO3 0x4f21
+#define mmDIG6_AFMT_AVI_INFO3 0x5421
+#define mmAFMT_MPEG_INFO0 0x4a22
+#define mmDIG0_AFMT_MPEG_INFO0 0x4a22
+#define mmDIG1_AFMT_MPEG_INFO0 0x4b22
+#define mmDIG2_AFMT_MPEG_INFO0 0x4c22
+#define mmDIG3_AFMT_MPEG_INFO0 0x4d22
+#define mmDIG4_AFMT_MPEG_INFO0 0x4e22
+#define mmDIG5_AFMT_MPEG_INFO0 0x4f22
+#define mmDIG6_AFMT_MPEG_INFO0 0x5422
+#define mmAFMT_MPEG_INFO1 0x4a23
+#define mmDIG0_AFMT_MPEG_INFO1 0x4a23
+#define mmDIG1_AFMT_MPEG_INFO1 0x4b23
+#define mmDIG2_AFMT_MPEG_INFO1 0x4c23
+#define mmDIG3_AFMT_MPEG_INFO1 0x4d23
+#define mmDIG4_AFMT_MPEG_INFO1 0x4e23
+#define mmDIG5_AFMT_MPEG_INFO1 0x4f23
+#define mmDIG6_AFMT_MPEG_INFO1 0x5423
+#define mmAFMT_GENERIC_HDR 0x4a24
+#define mmDIG0_AFMT_GENERIC_HDR 0x4a24
+#define mmDIG1_AFMT_GENERIC_HDR 0x4b24
+#define mmDIG2_AFMT_GENERIC_HDR 0x4c24
+#define mmDIG3_AFMT_GENERIC_HDR 0x4d24
+#define mmDIG4_AFMT_GENERIC_HDR 0x4e24
+#define mmDIG5_AFMT_GENERIC_HDR 0x4f24
+#define mmDIG6_AFMT_GENERIC_HDR 0x5424
+#define mmAFMT_GENERIC_0 0x4a25
+#define mmDIG0_AFMT_GENERIC_0 0x4a25
+#define mmDIG1_AFMT_GENERIC_0 0x4b25
+#define mmDIG2_AFMT_GENERIC_0 0x4c25
+#define mmDIG3_AFMT_GENERIC_0 0x4d25
+#define mmDIG4_AFMT_GENERIC_0 0x4e25
+#define mmDIG5_AFMT_GENERIC_0 0x4f25
+#define mmDIG6_AFMT_GENERIC_0 0x5425
+#define mmAFMT_GENERIC_1 0x4a26
+#define mmDIG0_AFMT_GENERIC_1 0x4a26
+#define mmDIG1_AFMT_GENERIC_1 0x4b26
+#define mmDIG2_AFMT_GENERIC_1 0x4c26
+#define mmDIG3_AFMT_GENERIC_1 0x4d26
+#define mmDIG4_AFMT_GENERIC_1 0x4e26
+#define mmDIG5_AFMT_GENERIC_1 0x4f26
+#define mmDIG6_AFMT_GENERIC_1 0x5426
+#define mmAFMT_GENERIC_2 0x4a27
+#define mmDIG0_AFMT_GENERIC_2 0x4a27
+#define mmDIG1_AFMT_GENERIC_2 0x4b27
+#define mmDIG2_AFMT_GENERIC_2 0x4c27
+#define mmDIG3_AFMT_GENERIC_2 0x4d27
+#define mmDIG4_AFMT_GENERIC_2 0x4e27
+#define mmDIG5_AFMT_GENERIC_2 0x4f27
+#define mmDIG6_AFMT_GENERIC_2 0x5427
+#define mmAFMT_GENERIC_3 0x4a28
+#define mmDIG0_AFMT_GENERIC_3 0x4a28
+#define mmDIG1_AFMT_GENERIC_3 0x4b28
+#define mmDIG2_AFMT_GENERIC_3 0x4c28
+#define mmDIG3_AFMT_GENERIC_3 0x4d28
+#define mmDIG4_AFMT_GENERIC_3 0x4e28
+#define mmDIG5_AFMT_GENERIC_3 0x4f28
+#define mmDIG6_AFMT_GENERIC_3 0x5428
+#define mmAFMT_GENERIC_4 0x4a29
+#define mmDIG0_AFMT_GENERIC_4 0x4a29
+#define mmDIG1_AFMT_GENERIC_4 0x4b29
+#define mmDIG2_AFMT_GENERIC_4 0x4c29
+#define mmDIG3_AFMT_GENERIC_4 0x4d29
+#define mmDIG4_AFMT_GENERIC_4 0x4e29
+#define mmDIG5_AFMT_GENERIC_4 0x4f29
+#define mmDIG6_AFMT_GENERIC_4 0x5429
+#define mmAFMT_GENERIC_5 0x4a2a
+#define mmDIG0_AFMT_GENERIC_5 0x4a2a
+#define mmDIG1_AFMT_GENERIC_5 0x4b2a
+#define mmDIG2_AFMT_GENERIC_5 0x4c2a
+#define mmDIG3_AFMT_GENERIC_5 0x4d2a
+#define mmDIG4_AFMT_GENERIC_5 0x4e2a
+#define mmDIG5_AFMT_GENERIC_5 0x4f2a
+#define mmDIG6_AFMT_GENERIC_5 0x542a
+#define mmAFMT_GENERIC_6 0x4a2b
+#define mmDIG0_AFMT_GENERIC_6 0x4a2b
+#define mmDIG1_AFMT_GENERIC_6 0x4b2b
+#define mmDIG2_AFMT_GENERIC_6 0x4c2b
+#define mmDIG3_AFMT_GENERIC_6 0x4d2b
+#define mmDIG4_AFMT_GENERIC_6 0x4e2b
+#define mmDIG5_AFMT_GENERIC_6 0x4f2b
+#define mmDIG6_AFMT_GENERIC_6 0x542b
+#define mmAFMT_GENERIC_7 0x4a2c
+#define mmDIG0_AFMT_GENERIC_7 0x4a2c
+#define mmDIG1_AFMT_GENERIC_7 0x4b2c
+#define mmDIG2_AFMT_GENERIC_7 0x4c2c
+#define mmDIG3_AFMT_GENERIC_7 0x4d2c
+#define mmDIG4_AFMT_GENERIC_7 0x4e2c
+#define mmDIG5_AFMT_GENERIC_7 0x4f2c
+#define mmDIG6_AFMT_GENERIC_7 0x542c
+#define mmHDMI_GENERIC_PACKET_CONTROL1 0x4a2d
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x4a2d
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x4b2d
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4c2d
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4d2d
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4e2d
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4f2d
+#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x542d
+#define mmHDMI_ACR_32_0 0x4a2e
+#define mmDIG0_HDMI_ACR_32_0 0x4a2e
+#define mmDIG1_HDMI_ACR_32_0 0x4b2e
+#define mmDIG2_HDMI_ACR_32_0 0x4c2e
+#define mmDIG3_HDMI_ACR_32_0 0x4d2e
+#define mmDIG4_HDMI_ACR_32_0 0x4e2e
+#define mmDIG5_HDMI_ACR_32_0 0x4f2e
+#define mmDIG6_HDMI_ACR_32_0 0x542e
+#define mmHDMI_ACR_32_1 0x4a2f
+#define mmDIG0_HDMI_ACR_32_1 0x4a2f
+#define mmDIG1_HDMI_ACR_32_1 0x4b2f
+#define mmDIG2_HDMI_ACR_32_1 0x4c2f
+#define mmDIG3_HDMI_ACR_32_1 0x4d2f
+#define mmDIG4_HDMI_ACR_32_1 0x4e2f
+#define mmDIG5_HDMI_ACR_32_1 0x4f2f
+#define mmDIG6_HDMI_ACR_32_1 0x542f
+#define mmHDMI_ACR_44_0 0x4a30
+#define mmDIG0_HDMI_ACR_44_0 0x4a30
+#define mmDIG1_HDMI_ACR_44_0 0x4b30
+#define mmDIG2_HDMI_ACR_44_0 0x4c30
+#define mmDIG3_HDMI_ACR_44_0 0x4d30
+#define mmDIG4_HDMI_ACR_44_0 0x4e30
+#define mmDIG5_HDMI_ACR_44_0 0x4f30
+#define mmDIG6_HDMI_ACR_44_0 0x5430
+#define mmHDMI_ACR_44_1 0x4a31
+#define mmDIG0_HDMI_ACR_44_1 0x4a31
+#define mmDIG1_HDMI_ACR_44_1 0x4b31
+#define mmDIG2_HDMI_ACR_44_1 0x4c31
+#define mmDIG3_HDMI_ACR_44_1 0x4d31
+#define mmDIG4_HDMI_ACR_44_1 0x4e31
+#define mmDIG5_HDMI_ACR_44_1 0x4f31
+#define mmDIG6_HDMI_ACR_44_1 0x5431
+#define mmHDMI_ACR_48_0 0x4a32
+#define mmDIG0_HDMI_ACR_48_0 0x4a32
+#define mmDIG1_HDMI_ACR_48_0 0x4b32
+#define mmDIG2_HDMI_ACR_48_0 0x4c32
+#define mmDIG3_HDMI_ACR_48_0 0x4d32
+#define mmDIG4_HDMI_ACR_48_0 0x4e32
+#define mmDIG5_HDMI_ACR_48_0 0x4f32
+#define mmDIG6_HDMI_ACR_48_0 0x5432
+#define mmHDMI_ACR_48_1 0x4a33
+#define mmDIG0_HDMI_ACR_48_1 0x4a33
+#define mmDIG1_HDMI_ACR_48_1 0x4b33
+#define mmDIG2_HDMI_ACR_48_1 0x4c33
+#define mmDIG3_HDMI_ACR_48_1 0x4d33
+#define mmDIG4_HDMI_ACR_48_1 0x4e33
+#define mmDIG5_HDMI_ACR_48_1 0x4f33
+#define mmDIG6_HDMI_ACR_48_1 0x5433
+#define mmHDMI_ACR_STATUS_0 0x4a34
+#define mmDIG0_HDMI_ACR_STATUS_0 0x4a34
+#define mmDIG1_HDMI_ACR_STATUS_0 0x4b34
+#define mmDIG2_HDMI_ACR_STATUS_0 0x4c34
+#define mmDIG3_HDMI_ACR_STATUS_0 0x4d34
+#define mmDIG4_HDMI_ACR_STATUS_0 0x4e34
+#define mmDIG5_HDMI_ACR_STATUS_0 0x4f34
+#define mmDIG6_HDMI_ACR_STATUS_0 0x5434
+#define mmHDMI_ACR_STATUS_1 0x4a35
+#define mmDIG0_HDMI_ACR_STATUS_1 0x4a35
+#define mmDIG1_HDMI_ACR_STATUS_1 0x4b35
+#define mmDIG2_HDMI_ACR_STATUS_1 0x4c35
+#define mmDIG3_HDMI_ACR_STATUS_1 0x4d35
+#define mmDIG4_HDMI_ACR_STATUS_1 0x4e35
+#define mmDIG5_HDMI_ACR_STATUS_1 0x4f35
+#define mmDIG6_HDMI_ACR_STATUS_1 0x5435
+#define mmAFMT_AUDIO_INFO0 0x4a36
+#define mmDIG0_AFMT_AUDIO_INFO0 0x4a36
+#define mmDIG1_AFMT_AUDIO_INFO0 0x4b36
+#define mmDIG2_AFMT_AUDIO_INFO0 0x4c36
+#define mmDIG3_AFMT_AUDIO_INFO0 0x4d36
+#define mmDIG4_AFMT_AUDIO_INFO0 0x4e36
+#define mmDIG5_AFMT_AUDIO_INFO0 0x4f36
+#define mmDIG6_AFMT_AUDIO_INFO0 0x5436
+#define mmAFMT_AUDIO_INFO1 0x4a37
+#define mmDIG0_AFMT_AUDIO_INFO1 0x4a37
+#define mmDIG1_AFMT_AUDIO_INFO1 0x4b37
+#define mmDIG2_AFMT_AUDIO_INFO1 0x4c37
+#define mmDIG3_AFMT_AUDIO_INFO1 0x4d37
+#define mmDIG4_AFMT_AUDIO_INFO1 0x4e37
+#define mmDIG5_AFMT_AUDIO_INFO1 0x4f37
+#define mmDIG6_AFMT_AUDIO_INFO1 0x5437
+#define mmAFMT_60958_0 0x4a38
+#define mmDIG0_AFMT_60958_0 0x4a38
+#define mmDIG1_AFMT_60958_0 0x4b38
+#define mmDIG2_AFMT_60958_0 0x4c38
+#define mmDIG3_AFMT_60958_0 0x4d38
+#define mmDIG4_AFMT_60958_0 0x4e38
+#define mmDIG5_AFMT_60958_0 0x4f38
+#define mmDIG6_AFMT_60958_0 0x5438
+#define mmAFMT_60958_1 0x4a39
+#define mmDIG0_AFMT_60958_1 0x4a39
+#define mmDIG1_AFMT_60958_1 0x4b39
+#define mmDIG2_AFMT_60958_1 0x4c39
+#define mmDIG3_AFMT_60958_1 0x4d39
+#define mmDIG4_AFMT_60958_1 0x4e39
+#define mmDIG5_AFMT_60958_1 0x4f39
+#define mmDIG6_AFMT_60958_1 0x5439
+#define mmAFMT_AUDIO_CRC_CONTROL 0x4a3a
+#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x4a3a
+#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x4b3a
+#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4c3a
+#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4d3a
+#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4e3a
+#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4f3a
+#define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x543a
+#define mmAFMT_RAMP_CONTROL0 0x4a3b
+#define mmDIG0_AFMT_RAMP_CONTROL0 0x4a3b
+#define mmDIG1_AFMT_RAMP_CONTROL0 0x4b3b
+#define mmDIG2_AFMT_RAMP_CONTROL0 0x4c3b
+#define mmDIG3_AFMT_RAMP_CONTROL0 0x4d3b
+#define mmDIG4_AFMT_RAMP_CONTROL0 0x4e3b
+#define mmDIG5_AFMT_RAMP_CONTROL0 0x4f3b
+#define mmDIG6_AFMT_RAMP_CONTROL0 0x543b
+#define mmAFMT_RAMP_CONTROL1 0x4a3c
+#define mmDIG0_AFMT_RAMP_CONTROL1 0x4a3c
+#define mmDIG1_AFMT_RAMP_CONTROL1 0x4b3c
+#define mmDIG2_AFMT_RAMP_CONTROL1 0x4c3c
+#define mmDIG3_AFMT_RAMP_CONTROL1 0x4d3c
+#define mmDIG4_AFMT_RAMP_CONTROL1 0x4e3c
+#define mmDIG5_AFMT_RAMP_CONTROL1 0x4f3c
+#define mmDIG6_AFMT_RAMP_CONTROL1 0x543c
+#define mmAFMT_RAMP_CONTROL2 0x4a3d
+#define mmDIG0_AFMT_RAMP_CONTROL2 0x4a3d
+#define mmDIG1_AFMT_RAMP_CONTROL2 0x4b3d
+#define mmDIG2_AFMT_RAMP_CONTROL2 0x4c3d
+#define mmDIG3_AFMT_RAMP_CONTROL2 0x4d3d
+#define mmDIG4_AFMT_RAMP_CONTROL2 0x4e3d
+#define mmDIG5_AFMT_RAMP_CONTROL2 0x4f3d
+#define mmDIG6_AFMT_RAMP_CONTROL2 0x543d
+#define mmAFMT_RAMP_CONTROL3 0x4a3e
+#define mmDIG0_AFMT_RAMP_CONTROL3 0x4a3e
+#define mmDIG1_AFMT_RAMP_CONTROL3 0x4b3e
+#define mmDIG2_AFMT_RAMP_CONTROL3 0x4c3e
+#define mmDIG3_AFMT_RAMP_CONTROL3 0x4d3e
+#define mmDIG4_AFMT_RAMP_CONTROL3 0x4e3e
+#define mmDIG5_AFMT_RAMP_CONTROL3 0x4f3e
+#define mmDIG6_AFMT_RAMP_CONTROL3 0x543e
+#define mmAFMT_60958_2 0x4a3f
+#define mmDIG0_AFMT_60958_2 0x4a3f
+#define mmDIG1_AFMT_60958_2 0x4b3f
+#define mmDIG2_AFMT_60958_2 0x4c3f
+#define mmDIG3_AFMT_60958_2 0x4d3f
+#define mmDIG4_AFMT_60958_2 0x4e3f
+#define mmDIG5_AFMT_60958_2 0x4f3f
+#define mmDIG6_AFMT_60958_2 0x543f
+#define mmAFMT_AUDIO_CRC_RESULT 0x4a40
+#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x4a40
+#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x4b40
+#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4c40
+#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4d40
+#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4e40
+#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4f40
+#define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x5440
+#define mmAFMT_STATUS 0x4a41
+#define mmDIG0_AFMT_STATUS 0x4a41
+#define mmDIG1_AFMT_STATUS 0x4b41
+#define mmDIG2_AFMT_STATUS 0x4c41
+#define mmDIG3_AFMT_STATUS 0x4d41
+#define mmDIG4_AFMT_STATUS 0x4e41
+#define mmDIG5_AFMT_STATUS 0x4f41
+#define mmDIG6_AFMT_STATUS 0x5441
+#define mmAFMT_AUDIO_PACKET_CONTROL 0x4a42
+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x4a42
+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x4b42
+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x4c42
+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x4d42
+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x4e42
+#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4f42
+#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x5442
+#define mmAFMT_VBI_PACKET_CONTROL 0x4a43
+#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x4a43
+#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x4b43
+#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x4c43
+#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x4d43
+#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x4e43
+#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4f43
+#define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x5443
+#define mmAFMT_INFOFRAME_CONTROL0 0x4a44
+#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x4a44
+#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x4b44
+#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x4c44
+#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x4d44
+#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x4e44
+#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4f44
+#define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x5444
+#define mmAFMT_AUDIO_SRC_CONTROL 0x4a45
+#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x4a45
+#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x4b45
+#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x4c45
+#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x4d45
+#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x4e45
+#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4f45
+#define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x5445
+#define mmAFMT_AUDIO_DBG_DTO_CNTL 0x4a46
+#define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x4a46
+#define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x4b46
+#define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4c46
+#define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4d46
+#define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4e46
+#define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4f46
+#define mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL 0x5446
+#define mmDIG_BE_CNTL 0x4a47
+#define mmDIG0_DIG_BE_CNTL 0x4a47
+#define mmDIG1_DIG_BE_CNTL 0x4b47
+#define mmDIG2_DIG_BE_CNTL 0x4c47
+#define mmDIG3_DIG_BE_CNTL 0x4d47
+#define mmDIG4_DIG_BE_CNTL 0x4e47
+#define mmDIG5_DIG_BE_CNTL 0x4f47
+#define mmDIG6_DIG_BE_CNTL 0x5447
+#define mmDIG_BE_EN_CNTL 0x4a48
+#define mmDIG0_DIG_BE_EN_CNTL 0x4a48
+#define mmDIG1_DIG_BE_EN_CNTL 0x4b48
+#define mmDIG2_DIG_BE_EN_CNTL 0x4c48
+#define mmDIG3_DIG_BE_EN_CNTL 0x4d48
+#define mmDIG4_DIG_BE_EN_CNTL 0x4e48
+#define mmDIG5_DIG_BE_EN_CNTL 0x4f48
+#define mmDIG6_DIG_BE_EN_CNTL 0x5448
+#define mmTMDS_CNTL 0x4a6b
+#define mmDIG0_TMDS_CNTL 0x4a6b
+#define mmDIG1_TMDS_CNTL 0x4b6b
+#define mmDIG2_TMDS_CNTL 0x4c6b
+#define mmDIG3_TMDS_CNTL 0x4d6b
+#define mmDIG4_TMDS_CNTL 0x4e6b
+#define mmDIG5_TMDS_CNTL 0x4f6b
+#define mmDIG6_TMDS_CNTL 0x546b
+#define mmTMDS_CONTROL_CHAR 0x4a6c
+#define mmDIG0_TMDS_CONTROL_CHAR 0x4a6c
+#define mmDIG1_TMDS_CONTROL_CHAR 0x4b6c
+#define mmDIG2_TMDS_CONTROL_CHAR 0x4c6c
+#define mmDIG3_TMDS_CONTROL_CHAR 0x4d6c
+#define mmDIG4_TMDS_CONTROL_CHAR 0x4e6c
+#define mmDIG5_TMDS_CONTROL_CHAR 0x4f6c
+#define mmDIG6_TMDS_CONTROL_CHAR 0x546c
+#define mmTMDS_CONTROL0_FEEDBACK 0x4a6d
+#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x4a6d
+#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x4b6d
+#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x4c6d
+#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x4d6d
+#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x4e6d
+#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4f6d
+#define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x546d
+#define mmTMDS_STEREOSYNC_CTL_SEL 0x4a6e
+#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x4a6e
+#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x4b6e
+#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x4c6e
+#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x4d6e
+#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x4e6e
+#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4f6e
+#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x546e
+#define mmTMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x4b6f
+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4c6f
+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4d6f
+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4e6f
+#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4f6f
+#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x546f
+#define mmTMDS_SYNC_CHAR_PATTERN_2_3 0x4a70
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x4a70
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x4b70
+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4c70
+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4d70
+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4e70
+#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4f70
+#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x5470
+#define mmTMDS_DEBUG 0x4a71
+#define mmDIG0_TMDS_DEBUG 0x4a71
+#define mmDIG1_TMDS_DEBUG 0x4b71
+#define mmDIG2_TMDS_DEBUG 0x4c71
+#define mmDIG3_TMDS_DEBUG 0x4d71
+#define mmDIG4_TMDS_DEBUG 0x4e71
+#define mmDIG5_TMDS_DEBUG 0x4f71
+#define mmDIG6_TMDS_DEBUG 0x5471
+#define mmTMDS_CTL_BITS 0x4a72
+#define mmDIG0_TMDS_CTL_BITS 0x4a72
+#define mmDIG1_TMDS_CTL_BITS 0x4b72
+#define mmDIG2_TMDS_CTL_BITS 0x4c72
+#define mmDIG3_TMDS_CTL_BITS 0x4d72
+#define mmDIG4_TMDS_CTL_BITS 0x4e72
+#define mmDIG5_TMDS_CTL_BITS 0x4f72
+#define mmDIG6_TMDS_CTL_BITS 0x5472
+#define mmTMDS_DCBALANCER_CONTROL 0x4a73
+#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x4a73
+#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x4b73
+#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x4c73
+#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x4d73
+#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x4e73
+#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4f73
+#define mmDIG6_TMDS_DCBALANCER_CONTROL 0x5473
+#define mmTMDS_CTL0_1_GEN_CNTL 0x4a75
+#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x4a75
+#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x4b75
+#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4c75
+#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4d75
+#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4e75
+#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4f75
+#define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x5475
+#define mmTMDS_CTL2_3_GEN_CNTL 0x4a76
+#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x4a76
+#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x4b76
+#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4c76
+#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4d76
+#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4e76
+#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4f76
+#define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x5476
+#define ixTMDS_DEBUG1 0x1
+#define ixTMDS_DEBUG2 0x2
+#define ixTMDS_DEBUG3 0x3
+#define ixTMDS_DEBUG7 0x4
+#define ixTMDS_DEBUG8 0x5
+#define ixTMDS_DEBUG9 0x6
+#define ixTMDS_DEBUG10 0x7
+#define ixTMDS_DEBUG11 0x8
+#define ixTMDS_DEBUG12 0x9
+#define ixTMDS_DEBUG13 0xa
+#define mmLVDS_DATA_CNTL 0x4a78
+#define mmDIG0_LVDS_DATA_CNTL 0x4a78
+#define mmDIG1_LVDS_DATA_CNTL 0x4b78
+#define mmDIG2_LVDS_DATA_CNTL 0x4c78
+#define mmDIG3_LVDS_DATA_CNTL 0x4d78
+#define mmDIG4_LVDS_DATA_CNTL 0x4e78
+#define mmDIG5_LVDS_DATA_CNTL 0x4f78
+#define mmDIG6_LVDS_DATA_CNTL 0x5478
+#define mmDIG_LANE_ENABLE 0x4a79
+#define mmDIG0_DIG_LANE_ENABLE 0x4a79
+#define mmDIG1_DIG_LANE_ENABLE 0x4b79
+#define mmDIG2_DIG_LANE_ENABLE 0x4c79
+#define mmDIG3_DIG_LANE_ENABLE 0x4d79
+#define mmDIG4_DIG_LANE_ENABLE 0x4e79
+#define mmDIG5_DIG_LANE_ENABLE 0x4f79
+#define mmDIG6_DIG_LANE_ENABLE 0x5479
+#define mmDIG_TEST_DEBUG_INDEX 0x4a7a
+#define mmDIG0_DIG_TEST_DEBUG_INDEX 0x4a7a
+#define mmDIG1_DIG_TEST_DEBUG_INDEX 0x4b7a
+#define mmDIG2_DIG_TEST_DEBUG_INDEX 0x4c7a
+#define mmDIG3_DIG_TEST_DEBUG_INDEX 0x4d7a
+#define mmDIG4_DIG_TEST_DEBUG_INDEX 0x4e7a
+#define mmDIG5_DIG_TEST_DEBUG_INDEX 0x4f7a
+#define mmDIG6_DIG_TEST_DEBUG_INDEX 0x547a
+#define mmDIG_TEST_DEBUG_DATA 0x4a7b
+#define mmDIG0_DIG_TEST_DEBUG_DATA 0x4a7b
+#define mmDIG1_DIG_TEST_DEBUG_DATA 0x4b7b
+#define mmDIG2_DIG_TEST_DEBUG_DATA 0x4c7b
+#define mmDIG3_DIG_TEST_DEBUG_DATA 0x4d7b
+#define mmDIG4_DIG_TEST_DEBUG_DATA 0x4e7b
+#define mmDIG5_DIG_TEST_DEBUG_DATA 0x4f7b
+#define mmDIG6_DIG_TEST_DEBUG_DATA 0x547b
+#define mmDIG_FE_TEST_DEBUG_INDEX 0x4a7c
+#define mmDIG0_DIG_FE_TEST_DEBUG_INDEX 0x4a7c
+#define mmDIG1_DIG_FE_TEST_DEBUG_INDEX 0x4b7c
+#define mmDIG2_DIG_FE_TEST_DEBUG_INDEX 0x4c7c
+#define mmDIG3_DIG_FE_TEST_DEBUG_INDEX 0x4d7c
+#define mmDIG4_DIG_FE_TEST_DEBUG_INDEX 0x4e7c
+#define mmDIG5_DIG_FE_TEST_DEBUG_INDEX 0x4f7c
+#define mmDIG6_DIG_FE_TEST_DEBUG_INDEX 0x547c
+#define mmDIG_FE_TEST_DEBUG_DATA 0x4a7d
+#define mmDIG0_DIG_FE_TEST_DEBUG_DATA 0x4a7d
+#define mmDIG1_DIG_FE_TEST_DEBUG_DATA 0x4b7d
+#define mmDIG2_DIG_FE_TEST_DEBUG_DATA 0x4c7d
+#define mmDIG3_DIG_FE_TEST_DEBUG_DATA 0x4d7d
+#define mmDIG4_DIG_FE_TEST_DEBUG_DATA 0x4e7d
+#define mmDIG5_DIG_FE_TEST_DEBUG_DATA 0x4f7d
+#define mmDIG6_DIG_FE_TEST_DEBUG_DATA 0x547d
+#define mmDMCU_CTRL 0x1600
+#define mmDMCU_STATUS 0x1601
+#define mmDMCU_PC_START_ADDR 0x1602
+#define mmDMCU_FW_START_ADDR 0x1603
+#define mmDMCU_FW_END_ADDR 0x1604
+#define mmDMCU_FW_ISR_START_ADDR 0x1605
+#define mmDMCU_FW_CS_HI 0x1606
+#define mmDMCU_FW_CS_LO 0x1607
+#define mmDMCU_RAM_ACCESS_CTRL 0x1608
+#define mmDMCU_ERAM_WR_CTRL 0x1609
+#define mmDMCU_ERAM_WR_DATA 0x160a
+#define mmDMCU_ERAM_RD_CTRL 0x160b
+#define mmDMCU_ERAM_RD_DATA 0x160c
+#define mmDMCU_IRAM_WR_CTRL 0x160d
+#define mmDMCU_IRAM_WR_DATA 0x160e
+#define mmDMCU_IRAM_RD_CTRL 0x160f
+#define mmDMCU_IRAM_RD_DATA 0x1610
+#define mmDMCU_EVENT_TRIGGER 0x1611
+#define mmDMCU_UC_INTERNAL_INT_STATUS 0x1612
+#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x1613
+#define mmDMCU_INTERRUPT_STATUS 0x1614
+#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617
+#define mmDC_DMCU_SCRATCH 0x1618
+#define mmDMCU_INT_CNT 0x1619
+#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161a
+#define mmDMCU_UC_CLK_GATING_CNTL 0x161b
+#define mmMASTER_COMM_DATA_REG1 0x161c
+#define mmMASTER_COMM_DATA_REG2 0x161d
+#define mmMASTER_COMM_DATA_REG3 0x161e
+#define mmMASTER_COMM_CMD_REG 0x161f
+#define mmMASTER_COMM_CNTL_REG 0x1620
+#define mmSLAVE_COMM_DATA_REG1 0x1621
+#define mmSLAVE_COMM_DATA_REG2 0x1622
+#define mmSLAVE_COMM_DATA_REG3 0x1623
+#define mmSLAVE_COMM_CMD_REG 0x1624
+#define mmSLAVE_COMM_CNTL_REG 0x1625
+#define mmDMCU_TEST_DEBUG_INDEX 0x1626
+#define mmDMCU_TEST_DEBUG_DATA 0x1627
+#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x1644
+#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x1645
+#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x1646
+#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x1647
+#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x1642
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x1674
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x1675
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x1676
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x1677
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x1643
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1678
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x1679
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x167a
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x167b
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x1673
+#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1 0x167c
+#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2 0x167d
+#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3 0x167e
+#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4 0x167f
+#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5 0x1633
+#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x1634
+#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x1635
+#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1636
+#define mmDP_LINK_CNTL 0x4aa0
+#define mmDP0_DP_LINK_CNTL 0x4aa0
+#define mmDP1_DP_LINK_CNTL 0x4ba0
+#define mmDP2_DP_LINK_CNTL 0x4ca0
+#define mmDP3_DP_LINK_CNTL 0x4da0
+#define mmDP4_DP_LINK_CNTL 0x4ea0
+#define mmDP5_DP_LINK_CNTL 0x4fa0
+#define mmDP6_DP_LINK_CNTL 0x54a0
+#define mmDP_PIXEL_FORMAT 0x4aa1
+#define mmDP0_DP_PIXEL_FORMAT 0x4aa1
+#define mmDP1_DP_PIXEL_FORMAT 0x4ba1
+#define mmDP2_DP_PIXEL_FORMAT 0x4ca1
+#define mmDP3_DP_PIXEL_FORMAT 0x4da1
+#define mmDP4_DP_PIXEL_FORMAT 0x4ea1
+#define mmDP5_DP_PIXEL_FORMAT 0x4fa1
+#define mmDP6_DP_PIXEL_FORMAT 0x54a1
+#define mmDP_MSA_COLORIMETRY 0x4aa2
+#define mmDP0_DP_MSA_COLORIMETRY 0x4aa2
+#define mmDP1_DP_MSA_COLORIMETRY 0x4ba2
+#define mmDP2_DP_MSA_COLORIMETRY 0x4ca2
+#define mmDP3_DP_MSA_COLORIMETRY 0x4da2
+#define mmDP4_DP_MSA_COLORIMETRY 0x4ea2
+#define mmDP5_DP_MSA_COLORIMETRY 0x4fa2
+#define mmDP6_DP_MSA_COLORIMETRY 0x54a2
+#define mmDP_CONFIG 0x4aa3
+#define mmDP0_DP_CONFIG 0x4aa3
+#define mmDP1_DP_CONFIG 0x4ba3
+#define mmDP2_DP_CONFIG 0x4ca3
+#define mmDP3_DP_CONFIG 0x4da3
+#define mmDP4_DP_CONFIG 0x4ea3
+#define mmDP5_DP_CONFIG 0x4fa3
+#define mmDP6_DP_CONFIG 0x54a3
+#define mmDP_VID_STREAM_CNTL 0x4aa4
+#define mmDP0_DP_VID_STREAM_CNTL 0x4aa4
+#define mmDP1_DP_VID_STREAM_CNTL 0x4ba4
+#define mmDP2_DP_VID_STREAM_CNTL 0x4ca4
+#define mmDP3_DP_VID_STREAM_CNTL 0x4da4
+#define mmDP4_DP_VID_STREAM_CNTL 0x4ea4
+#define mmDP5_DP_VID_STREAM_CNTL 0x4fa4
+#define mmDP6_DP_VID_STREAM_CNTL 0x54a4
+#define mmDP_STEER_FIFO 0x4aa5
+#define mmDP0_DP_STEER_FIFO 0x4aa5
+#define mmDP1_DP_STEER_FIFO 0x4ba5
+#define mmDP2_DP_STEER_FIFO 0x4ca5
+#define mmDP3_DP_STEER_FIFO 0x4da5
+#define mmDP4_DP_STEER_FIFO 0x4ea5
+#define mmDP5_DP_STEER_FIFO 0x4fa5
+#define mmDP6_DP_STEER_FIFO 0x54a5
+#define mmDP_MSA_MISC 0x4aa6
+#define mmDP0_DP_MSA_MISC 0x4aa6
+#define mmDP1_DP_MSA_MISC 0x4ba6
+#define mmDP2_DP_MSA_MISC 0x4ca6
+#define mmDP3_DP_MSA_MISC 0x4da6
+#define mmDP4_DP_MSA_MISC 0x4ea6
+#define mmDP5_DP_MSA_MISC 0x4fa6
+#define mmDP6_DP_MSA_MISC 0x54a6
+#define mmDP_VID_TIMING 0x4aa8
+#define mmDP0_DP_VID_TIMING 0x4aa8
+#define mmDP1_DP_VID_TIMING 0x4ba8
+#define mmDP2_DP_VID_TIMING 0x4ca8
+#define mmDP3_DP_VID_TIMING 0x4da8
+#define mmDP4_DP_VID_TIMING 0x4ea8
+#define mmDP5_DP_VID_TIMING 0x4fa8
+#define mmDP6_DP_VID_TIMING 0x54a8
+#define mmDP_VID_N 0x4aa9
+#define mmDP0_DP_VID_N 0x4aa9
+#define mmDP1_DP_VID_N 0x4ba9
+#define mmDP2_DP_VID_N 0x4ca9
+#define mmDP3_DP_VID_N 0x4da9
+#define mmDP4_DP_VID_N 0x4ea9
+#define mmDP5_DP_VID_N 0x4fa9
+#define mmDP6_DP_VID_N 0x54a9
+#define mmDP_VID_M 0x4aaa
+#define mmDP0_DP_VID_M 0x4aaa
+#define mmDP1_DP_VID_M 0x4baa
+#define mmDP2_DP_VID_M 0x4caa
+#define mmDP3_DP_VID_M 0x4daa
+#define mmDP4_DP_VID_M 0x4eaa
+#define mmDP5_DP_VID_M 0x4faa
+#define mmDP6_DP_VID_M 0x54aa
+#define mmDP_LINK_FRAMING_CNTL 0x4aab
+#define mmDP0_DP_LINK_FRAMING_CNTL 0x4aab
+#define mmDP1_DP_LINK_FRAMING_CNTL 0x4bab
+#define mmDP2_DP_LINK_FRAMING_CNTL 0x4cab
+#define mmDP3_DP_LINK_FRAMING_CNTL 0x4dab
+#define mmDP4_DP_LINK_FRAMING_CNTL 0x4eab
+#define mmDP5_DP_LINK_FRAMING_CNTL 0x4fab
+#define mmDP6_DP_LINK_FRAMING_CNTL 0x54ab
+#define mmDP_HBR2_EYE_PATTERN 0x4aac
+#define mmDP0_DP_HBR2_EYE_PATTERN 0x4aac
+#define mmDP1_DP_HBR2_EYE_PATTERN 0x4bac
+#define mmDP2_DP_HBR2_EYE_PATTERN 0x4cac
+#define mmDP3_DP_HBR2_EYE_PATTERN 0x4dac
+#define mmDP4_DP_HBR2_EYE_PATTERN 0x4eac
+#define mmDP5_DP_HBR2_EYE_PATTERN 0x4fac
+#define mmDP6_DP_HBR2_EYE_PATTERN 0x54ac
+#define mmDP_VID_MSA_VBID 0x4aad
+#define mmDP0_DP_VID_MSA_VBID 0x4aad
+#define mmDP1_DP_VID_MSA_VBID 0x4bad
+#define mmDP2_DP_VID_MSA_VBID 0x4cad
+#define mmDP3_DP_VID_MSA_VBID 0x4dad
+#define mmDP4_DP_VID_MSA_VBID 0x4ead
+#define mmDP5_DP_VID_MSA_VBID 0x4fad
+#define mmDP6_DP_VID_MSA_VBID 0x54ad
+#define mmDP_VID_INTERRUPT_CNTL 0x4aae
+#define mmDP0_DP_VID_INTERRUPT_CNTL 0x4aae
+#define mmDP1_DP_VID_INTERRUPT_CNTL 0x4bae
+#define mmDP2_DP_VID_INTERRUPT_CNTL 0x4cae
+#define mmDP3_DP_VID_INTERRUPT_CNTL 0x4dae
+#define mmDP4_DP_VID_INTERRUPT_CNTL 0x4eae
+#define mmDP5_DP_VID_INTERRUPT_CNTL 0x4fae
+#define mmDP6_DP_VID_INTERRUPT_CNTL 0x54ae
+#define mmDP_DPHY_CNTL 0x4aaf
+#define mmDP0_DP_DPHY_CNTL 0x4aaf
+#define mmDP1_DP_DPHY_CNTL 0x4baf
+#define mmDP2_DP_DPHY_CNTL 0x4caf
+#define mmDP3_DP_DPHY_CNTL 0x4daf
+#define mmDP4_DP_DPHY_CNTL 0x4eaf
+#define mmDP5_DP_DPHY_CNTL 0x4faf
+#define mmDP6_DP_DPHY_CNTL 0x54af
+#define mmDP_DPHY_TRAINING_PATTERN_SEL 0x4ab0
+#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x4ab0
+#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x4bb0
+#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x4cb0
+#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x4db0
+#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x4eb0
+#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4fb0
+#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x54b0
+#define mmDP_DPHY_SYM0 0x4ab1
+#define mmDP0_DP_DPHY_SYM0 0x4ab1
+#define mmDP1_DP_DPHY_SYM0 0x4bb1
+#define mmDP2_DP_DPHY_SYM0 0x4cb1
+#define mmDP3_DP_DPHY_SYM0 0x4db1
+#define mmDP4_DP_DPHY_SYM0 0x4eb1
+#define mmDP5_DP_DPHY_SYM0 0x4fb1
+#define mmDP6_DP_DPHY_SYM0 0x54b1
+#define mmDP_DPHY_SYM1 0x4ab2
+#define mmDP0_DP_DPHY_SYM1 0x4ab2
+#define mmDP1_DP_DPHY_SYM1 0x4bb2
+#define mmDP2_DP_DPHY_SYM1 0x4cb2
+#define mmDP3_DP_DPHY_SYM1 0x4db2
+#define mmDP4_DP_DPHY_SYM1 0x4eb2
+#define mmDP5_DP_DPHY_SYM1 0x4fb2
+#define mmDP6_DP_DPHY_SYM1 0x54b2
+#define mmDP_DPHY_SYM2 0x4ab3
+#define mmDP0_DP_DPHY_SYM2 0x4ab3
+#define mmDP1_DP_DPHY_SYM2 0x4bb3
+#define mmDP2_DP_DPHY_SYM2 0x4cb3
+#define mmDP3_DP_DPHY_SYM2 0x4db3
+#define mmDP4_DP_DPHY_SYM2 0x4eb3
+#define mmDP5_DP_DPHY_SYM2 0x4fb3
+#define mmDP6_DP_DPHY_SYM2 0x54b3
+#define mmDP_DPHY_8B10B_CNTL 0x4ab4
+#define mmDP0_DP_DPHY_8B10B_CNTL 0x4ab4
+#define mmDP1_DP_DPHY_8B10B_CNTL 0x4bb4
+#define mmDP2_DP_DPHY_8B10B_CNTL 0x4cb4
+#define mmDP3_DP_DPHY_8B10B_CNTL 0x4db4
+#define mmDP4_DP_DPHY_8B10B_CNTL 0x4eb4
+#define mmDP5_DP_DPHY_8B10B_CNTL 0x4fb4
+#define mmDP6_DP_DPHY_8B10B_CNTL 0x54b4
+#define mmDP_DPHY_PRBS_CNTL 0x4ab5
+#define mmDP0_DP_DPHY_PRBS_CNTL 0x4ab5
+#define mmDP1_DP_DPHY_PRBS_CNTL 0x4bb5
+#define mmDP2_DP_DPHY_PRBS_CNTL 0x4cb5
+#define mmDP3_DP_DPHY_PRBS_CNTL 0x4db5
+#define mmDP4_DP_DPHY_PRBS_CNTL 0x4eb5
+#define mmDP5_DP_DPHY_PRBS_CNTL 0x4fb5
+#define mmDP6_DP_DPHY_PRBS_CNTL 0x54b5
+#define mmDP_DPHY_CRC_EN 0x4ab7
+#define mmDP0_DP_DPHY_CRC_EN 0x4ab7
+#define mmDP1_DP_DPHY_CRC_EN 0x4bb7
+#define mmDP2_DP_DPHY_CRC_EN 0x4cb7
+#define mmDP3_DP_DPHY_CRC_EN 0x4db7
+#define mmDP4_DP_DPHY_CRC_EN 0x4eb7
+#define mmDP5_DP_DPHY_CRC_EN 0x4fb7
+#define mmDP6_DP_DPHY_CRC_EN 0x54b7
+#define mmDP_DPHY_CRC_CNTL 0x4ab8
+#define mmDP0_DP_DPHY_CRC_CNTL 0x4ab8
+#define mmDP1_DP_DPHY_CRC_CNTL 0x4bb8
+#define mmDP2_DP_DPHY_CRC_CNTL 0x4cb8
+#define mmDP3_DP_DPHY_CRC_CNTL 0x4db8
+#define mmDP4_DP_DPHY_CRC_CNTL 0x4eb8
+#define mmDP5_DP_DPHY_CRC_CNTL 0x4fb8
+#define mmDP6_DP_DPHY_CRC_CNTL 0x54b8
+#define mmDP_DPHY_CRC_RESULT 0x4ab9
+#define mmDP0_DP_DPHY_CRC_RESULT 0x4ab9
+#define mmDP1_DP_DPHY_CRC_RESULT 0x4bb9
+#define mmDP2_DP_DPHY_CRC_RESULT 0x4cb9
+#define mmDP3_DP_DPHY_CRC_RESULT 0x4db9
+#define mmDP4_DP_DPHY_CRC_RESULT 0x4eb9
+#define mmDP5_DP_DPHY_CRC_RESULT 0x4fb9
+#define mmDP6_DP_DPHY_CRC_RESULT 0x54b9
+#define mmDP_DPHY_CRC_MST_CNTL 0x4aba
+#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x4aba
+#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x4bba
+#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x4cba
+#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x4dba
+#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x4eba
+#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x4fba
+#define mmDP6_DP_DPHY_CRC_MST_CNTL 0x54ba
+#define mmDP_DPHY_CRC_MST_STATUS 0x4abb
+#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x4abb
+#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x4bbb
+#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x4cbb
+#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x4dbb
+#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x4ebb
+#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x4fbb
+#define mmDP6_DP_DPHY_CRC_MST_STATUS 0x54bb
+#define mmDP_DPHY_FAST_TRAINING 0x4abc
+#define mmDP0_DP_DPHY_FAST_TRAINING 0x4abc
+#define mmDP1_DP_DPHY_FAST_TRAINING 0x4bbc
+#define mmDP2_DP_DPHY_FAST_TRAINING 0x4cbc
+#define mmDP3_DP_DPHY_FAST_TRAINING 0x4dbc
+#define mmDP4_DP_DPHY_FAST_TRAINING 0x4ebc
+#define mmDP5_DP_DPHY_FAST_TRAINING 0x4fbc
+#define mmDP6_DP_DPHY_FAST_TRAINING 0x54bc
+#define mmDP_DPHY_FAST_TRAINING_STATUS 0x4abd
+#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x4abd
+#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x4bbd
+#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x4cbd
+#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x4dbd
+#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x4ebd
+#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4fbd
+#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x54bd
+#define mmDP_MSA_V_TIMING_OVERRIDE1 0x4abe
+#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x4abe
+#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x4bbe
+#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x4cbe
+#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x4dbe
+#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x4ebe
+#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4fbe
+#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x54be
+#define mmDP_MSA_V_TIMING_OVERRIDE2 0x4abf
+#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x4abf
+#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x4bbf
+#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x4cbf
+#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x4dbf
+#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x4ebf
+#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4fbf
+#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x54bf
+#define mmDP_SEC_CNTL 0x4ac3
+#define mmDP0_DP_SEC_CNTL 0x4ac3
+#define mmDP1_DP_SEC_CNTL 0x4bc3
+#define mmDP2_DP_SEC_CNTL 0x4cc3
+#define mmDP3_DP_SEC_CNTL 0x4dc3
+#define mmDP4_DP_SEC_CNTL 0x4ec3
+#define mmDP5_DP_SEC_CNTL 0x4fc3
+#define mmDP6_DP_SEC_CNTL 0x54c3
+#define mmDP_SEC_CNTL1 0x4ac4
+#define mmDP0_DP_SEC_CNTL1 0x4ac4
+#define mmDP1_DP_SEC_CNTL1 0x4bc4
+#define mmDP2_DP_SEC_CNTL1 0x4cc4
+#define mmDP3_DP_SEC_CNTL1 0x4dc4
+#define mmDP4_DP_SEC_CNTL1 0x4ec4
+#define mmDP5_DP_SEC_CNTL1 0x4fc4
+#define mmDP6_DP_SEC_CNTL1 0x54c4
+#define mmDP_SEC_FRAMING1 0x4ac5
+#define mmDP0_DP_SEC_FRAMING1 0x4ac5
+#define mmDP1_DP_SEC_FRAMING1 0x4bc5
+#define mmDP2_DP_SEC_FRAMING1 0x4cc5
+#define mmDP3_DP_SEC_FRAMING1 0x4dc5
+#define mmDP4_DP_SEC_FRAMING1 0x4ec5
+#define mmDP5_DP_SEC_FRAMING1 0x4fc5
+#define mmDP6_DP_SEC_FRAMING1 0x54c5
+#define mmDP_SEC_FRAMING2 0x4ac6
+#define mmDP0_DP_SEC_FRAMING2 0x4ac6
+#define mmDP1_DP_SEC_FRAMING2 0x4bc6
+#define mmDP2_DP_SEC_FRAMING2 0x4cc6
+#define mmDP3_DP_SEC_FRAMING2 0x4dc6
+#define mmDP4_DP_SEC_FRAMING2 0x4ec6
+#define mmDP5_DP_SEC_FRAMING2 0x4fc6
+#define mmDP6_DP_SEC_FRAMING2 0x54c6
+#define mmDP_SEC_FRAMING3 0x4ac7
+#define mmDP0_DP_SEC_FRAMING3 0x4ac7
+#define mmDP1_DP_SEC_FRAMING3 0x4bc7
+#define mmDP2_DP_SEC_FRAMING3 0x4cc7
+#define mmDP3_DP_SEC_FRAMING3 0x4dc7
+#define mmDP4_DP_SEC_FRAMING3 0x4ec7
+#define mmDP5_DP_SEC_FRAMING3 0x4fc7
+#define mmDP6_DP_SEC_FRAMING3 0x54c7
+#define mmDP_SEC_FRAMING4 0x4ac8
+#define mmDP0_DP_SEC_FRAMING4 0x4ac8
+#define mmDP1_DP_SEC_FRAMING4 0x4bc8
+#define mmDP2_DP_SEC_FRAMING4 0x4cc8
+#define mmDP3_DP_SEC_FRAMING4 0x4dc8
+#define mmDP4_DP_SEC_FRAMING4 0x4ec8
+#define mmDP5_DP_SEC_FRAMING4 0x4fc8
+#define mmDP6_DP_SEC_FRAMING4 0x54c8
+#define mmDP_SEC_AUD_N 0x4ac9
+#define mmDP0_DP_SEC_AUD_N 0x4ac9
+#define mmDP1_DP_SEC_AUD_N 0x4bc9
+#define mmDP2_DP_SEC_AUD_N 0x4cc9
+#define mmDP3_DP_SEC_AUD_N 0x4dc9
+#define mmDP4_DP_SEC_AUD_N 0x4ec9
+#define mmDP5_DP_SEC_AUD_N 0x4fc9
+#define mmDP6_DP_SEC_AUD_N 0x54c9
+#define mmDP_SEC_AUD_N_READBACK 0x4aca
+#define mmDP0_DP_SEC_AUD_N_READBACK 0x4aca
+#define mmDP1_DP_SEC_AUD_N_READBACK 0x4bca
+#define mmDP2_DP_SEC_AUD_N_READBACK 0x4cca
+#define mmDP3_DP_SEC_AUD_N_READBACK 0x4dca
+#define mmDP4_DP_SEC_AUD_N_READBACK 0x4eca
+#define mmDP5_DP_SEC_AUD_N_READBACK 0x4fca
+#define mmDP6_DP_SEC_AUD_N_READBACK 0x54ca
+#define mmDP_SEC_AUD_M 0x4acb
+#define mmDP0_DP_SEC_AUD_M 0x4acb
+#define mmDP1_DP_SEC_AUD_M 0x4bcb
+#define mmDP2_DP_SEC_AUD_M 0x4ccb
+#define mmDP3_DP_SEC_AUD_M 0x4dcb
+#define mmDP4_DP_SEC_AUD_M 0x4ecb
+#define mmDP5_DP_SEC_AUD_M 0x4fcb
+#define mmDP6_DP_SEC_AUD_M 0x54cb
+#define mmDP_SEC_AUD_M_READBACK 0x4acc
+#define mmDP0_DP_SEC_AUD_M_READBACK 0x4acc
+#define mmDP1_DP_SEC_AUD_M_READBACK 0x4bcc
+#define mmDP2_DP_SEC_AUD_M_READBACK 0x4ccc
+#define mmDP3_DP_SEC_AUD_M_READBACK 0x4dcc
+#define mmDP4_DP_SEC_AUD_M_READBACK 0x4ecc
+#define mmDP5_DP_SEC_AUD_M_READBACK 0x4fcc
+#define mmDP6_DP_SEC_AUD_M_READBACK 0x54cc
+#define mmDP_SEC_TIMESTAMP 0x4acd
+#define mmDP0_DP_SEC_TIMESTAMP 0x4acd
+#define mmDP1_DP_SEC_TIMESTAMP 0x4bcd
+#define mmDP2_DP_SEC_TIMESTAMP 0x4ccd
+#define mmDP3_DP_SEC_TIMESTAMP 0x4dcd
+#define mmDP4_DP_SEC_TIMESTAMP 0x4ecd
+#define mmDP5_DP_SEC_TIMESTAMP 0x4fcd
+#define mmDP6_DP_SEC_TIMESTAMP 0x54cd
+#define mmDP_SEC_PACKET_CNTL 0x4ace
+#define mmDP0_DP_SEC_PACKET_CNTL 0x4ace
+#define mmDP1_DP_SEC_PACKET_CNTL 0x4bce
+#define mmDP2_DP_SEC_PACKET_CNTL 0x4cce
+#define mmDP3_DP_SEC_PACKET_CNTL 0x4dce
+#define mmDP4_DP_SEC_PACKET_CNTL 0x4ece
+#define mmDP5_DP_SEC_PACKET_CNTL 0x4fce
+#define mmDP6_DP_SEC_PACKET_CNTL 0x54ce
+#define mmDP_MSE_RATE_CNTL 0x4acf
+#define mmDP0_DP_MSE_RATE_CNTL 0x4acf
+#define mmDP1_DP_MSE_RATE_CNTL 0x4bcf
+#define mmDP2_DP_MSE_RATE_CNTL 0x4ccf
+#define mmDP3_DP_MSE_RATE_CNTL 0x4dcf
+#define mmDP4_DP_MSE_RATE_CNTL 0x4ecf
+#define mmDP5_DP_MSE_RATE_CNTL 0x4fcf
+#define mmDP6_DP_MSE_RATE_CNTL 0x54cf
+#define mmDP_MSE_RATE_UPDATE 0x4ad1
+#define mmDP0_DP_MSE_RATE_UPDATE 0x4ad1
+#define mmDP1_DP_MSE_RATE_UPDATE 0x4bd1
+#define mmDP2_DP_MSE_RATE_UPDATE 0x4cd1
+#define mmDP3_DP_MSE_RATE_UPDATE 0x4dd1
+#define mmDP4_DP_MSE_RATE_UPDATE 0x4ed1
+#define mmDP5_DP_MSE_RATE_UPDATE 0x4fd1
+#define mmDP6_DP_MSE_RATE_UPDATE 0x54d1
+#define mmDP_MSE_SAT0 0x4ad2
+#define mmDP0_DP_MSE_SAT0 0x4ad2
+#define mmDP1_DP_MSE_SAT0 0x4bd2
+#define mmDP2_DP_MSE_SAT0 0x4cd2
+#define mmDP3_DP_MSE_SAT0 0x4dd2
+#define mmDP4_DP_MSE_SAT0 0x4ed2
+#define mmDP5_DP_MSE_SAT0 0x4fd2
+#define mmDP6_DP_MSE_SAT0 0x54d2
+#define mmDP_MSE_SAT1 0x4ad3
+#define mmDP0_DP_MSE_SAT1 0x4ad3
+#define mmDP1_DP_MSE_SAT1 0x4bd3
+#define mmDP2_DP_MSE_SAT1 0x4cd3
+#define mmDP3_DP_MSE_SAT1 0x4dd3
+#define mmDP4_DP_MSE_SAT1 0x4ed3
+#define mmDP5_DP_MSE_SAT1 0x4fd3
+#define mmDP6_DP_MSE_SAT1 0x54d3
+#define mmDP_MSE_SAT2 0x4ad4
+#define mmDP0_DP_MSE_SAT2 0x4ad4
+#define mmDP1_DP_MSE_SAT2 0x4bd4
+#define mmDP2_DP_MSE_SAT2 0x4cd4
+#define mmDP3_DP_MSE_SAT2 0x4dd4
+#define mmDP4_DP_MSE_SAT2 0x4ed4
+#define mmDP5_DP_MSE_SAT2 0x4fd4
+#define mmDP6_DP_MSE_SAT2 0x54d4
+#define mmDP_MSE_SAT_UPDATE 0x4ad5
+#define mmDP0_DP_MSE_SAT_UPDATE 0x4ad5
+#define mmDP1_DP_MSE_SAT_UPDATE 0x4bd5
+#define mmDP2_DP_MSE_SAT_UPDATE 0x4cd5
+#define mmDP3_DP_MSE_SAT_UPDATE 0x4dd5
+#define mmDP4_DP_MSE_SAT_UPDATE 0x4ed5
+#define mmDP5_DP_MSE_SAT_UPDATE 0x4fd5
+#define mmDP6_DP_MSE_SAT_UPDATE 0x54d5
+#define mmDP_MSE_LINK_TIMING 0x4ad6
+#define mmDP0_DP_MSE_LINK_TIMING 0x4ad6
+#define mmDP1_DP_MSE_LINK_TIMING 0x4bd6
+#define mmDP2_DP_MSE_LINK_TIMING 0x4cd6
+#define mmDP3_DP_MSE_LINK_TIMING 0x4dd6
+#define mmDP4_DP_MSE_LINK_TIMING 0x4ed6
+#define mmDP5_DP_MSE_LINK_TIMING 0x4fd6
+#define mmDP6_DP_MSE_LINK_TIMING 0x54d6
+#define mmDP_MSE_MISC_CNTL 0x4ad7
+#define mmDP0_DP_MSE_MISC_CNTL 0x4ad7
+#define mmDP1_DP_MSE_MISC_CNTL 0x4bd7
+#define mmDP2_DP_MSE_MISC_CNTL 0x4cd7
+#define mmDP3_DP_MSE_MISC_CNTL 0x4dd7
+#define mmDP4_DP_MSE_MISC_CNTL 0x4ed7
+#define mmDP5_DP_MSE_MISC_CNTL 0x4fd7
+#define mmDP6_DP_MSE_MISC_CNTL 0x54d7
+#define mmDP_TEST_DEBUG_INDEX 0x4ad8
+#define mmDP0_DP_TEST_DEBUG_INDEX 0x4ad8
+#define mmDP1_DP_TEST_DEBUG_INDEX 0x4bd8
+#define mmDP2_DP_TEST_DEBUG_INDEX 0x4cd8
+#define mmDP3_DP_TEST_DEBUG_INDEX 0x4dd8
+#define mmDP4_DP_TEST_DEBUG_INDEX 0x4ed8
+#define mmDP5_DP_TEST_DEBUG_INDEX 0x4fd8
+#define mmDP6_DP_TEST_DEBUG_INDEX 0x54d8
+#define mmDP_TEST_DEBUG_DATA 0x4ad9
+#define mmDP0_DP_TEST_DEBUG_DATA 0x4ad9
+#define mmDP1_DP_TEST_DEBUG_DATA 0x4bd9
+#define mmDP2_DP_TEST_DEBUG_DATA 0x4cd9
+#define mmDP3_DP_TEST_DEBUG_DATA 0x4dd9
+#define mmDP4_DP_TEST_DEBUG_DATA 0x4ed9
+#define mmDP5_DP_TEST_DEBUG_DATA 0x4fd9
+#define mmDP6_DP_TEST_DEBUG_DATA 0x54d9
+#define mmDP_FE_TEST_DEBUG_INDEX 0x4ada
+#define mmDP0_DP_FE_TEST_DEBUG_INDEX 0x4ada
+#define mmDP1_DP_FE_TEST_DEBUG_INDEX 0x4bda
+#define mmDP2_DP_FE_TEST_DEBUG_INDEX 0x4cda
+#define mmDP3_DP_FE_TEST_DEBUG_INDEX 0x4dda
+#define mmDP4_DP_FE_TEST_DEBUG_INDEX 0x4eda
+#define mmDP5_DP_FE_TEST_DEBUG_INDEX 0x4fda
+#define mmDP6_DP_FE_TEST_DEBUG_INDEX 0x54da
+#define mmDP_FE_TEST_DEBUG_DATA 0x4adb
+#define mmDP0_DP_FE_TEST_DEBUG_DATA 0x4adb
+#define mmDP1_DP_FE_TEST_DEBUG_DATA 0x4bdb
+#define mmDP2_DP_FE_TEST_DEBUG_DATA 0x4cdb
+#define mmDP3_DP_FE_TEST_DEBUG_DATA 0x4ddb
+#define mmDP4_DP_FE_TEST_DEBUG_DATA 0x4edb
+#define mmDP5_DP_FE_TEST_DEBUG_DATA 0x4fdb
+#define mmDP6_DP_FE_TEST_DEBUG_DATA 0x54db
+#define mmAUX_CONTROL 0x5c00
+#define mmDP_AUX0_AUX_CONTROL 0x5c00
+#define mmDP_AUX1_AUX_CONTROL 0x5c1c
+#define mmDP_AUX2_AUX_CONTROL 0x5c38
+#define mmDP_AUX3_AUX_CONTROL 0x5c54
+#define mmDP_AUX4_AUX_CONTROL 0x5c70
+#define mmDP_AUX5_AUX_CONTROL 0x5c8c
+#define mmAUX_SW_CONTROL 0x5c01
+#define mmDP_AUX0_AUX_SW_CONTROL 0x5c01
+#define mmDP_AUX1_AUX_SW_CONTROL 0x5c1d
+#define mmDP_AUX2_AUX_SW_CONTROL 0x5c39
+#define mmDP_AUX3_AUX_SW_CONTROL 0x5c55
+#define mmDP_AUX4_AUX_SW_CONTROL 0x5c71
+#define mmDP_AUX5_AUX_SW_CONTROL 0x5c8d
+#define mmAUX_ARB_CONTROL 0x5c02
+#define mmDP_AUX0_AUX_ARB_CONTROL 0x5c02
+#define mmDP_AUX1_AUX_ARB_CONTROL 0x5c1e
+#define mmDP_AUX2_AUX_ARB_CONTROL 0x5c3a
+#define mmDP_AUX3_AUX_ARB_CONTROL 0x5c56
+#define mmDP_AUX4_AUX_ARB_CONTROL 0x5c72
+#define mmDP_AUX5_AUX_ARB_CONTROL 0x5c8e
+#define mmAUX_INTERRUPT_CONTROL 0x5c03
+#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x5c03
+#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x5c1f
+#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x5c3b
+#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x5c57
+#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x5c73
+#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x5c8f
+#define mmAUX_SW_STATUS 0x5c04
+#define mmDP_AUX0_AUX_SW_STATUS 0x5c04
+#define mmDP_AUX1_AUX_SW_STATUS 0x5c20
+#define mmDP_AUX2_AUX_SW_STATUS 0x5c3c
+#define mmDP_AUX3_AUX_SW_STATUS 0x5c58
+#define mmDP_AUX4_AUX_SW_STATUS 0x5c74
+#define mmDP_AUX5_AUX_SW_STATUS 0x5c90
+#define mmAUX_LS_STATUS 0x5c05
+#define mmDP_AUX0_AUX_LS_STATUS 0x5c05
+#define mmDP_AUX1_AUX_LS_STATUS 0x5c21
+#define mmDP_AUX2_AUX_LS_STATUS 0x5c3d
+#define mmDP_AUX3_AUX_LS_STATUS 0x5c59
+#define mmDP_AUX4_AUX_LS_STATUS 0x5c75
+#define mmDP_AUX5_AUX_LS_STATUS 0x5c91
+#define mmAUX_SW_DATA 0x5c06
+#define mmDP_AUX0_AUX_SW_DATA 0x5c06
+#define mmDP_AUX1_AUX_SW_DATA 0x5c22
+#define mmDP_AUX2_AUX_SW_DATA 0x5c3e
+#define mmDP_AUX3_AUX_SW_DATA 0x5c5a
+#define mmDP_AUX4_AUX_SW_DATA 0x5c76
+#define mmDP_AUX5_AUX_SW_DATA 0x5c92
+#define mmAUX_LS_DATA 0x5c07
+#define mmDP_AUX0_AUX_LS_DATA 0x5c07
+#define mmDP_AUX1_AUX_LS_DATA 0x5c23
+#define mmDP_AUX2_AUX_LS_DATA 0x5c3f
+#define mmDP_AUX3_AUX_LS_DATA 0x5c5b
+#define mmDP_AUX4_AUX_LS_DATA 0x5c77
+#define mmDP_AUX5_AUX_LS_DATA 0x5c93
+#define mmAUX_DPHY_TX_REF_CONTROL 0x5c08
+#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x5c08
+#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x5c24
+#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x5c40
+#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x5c5c
+#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x5c78
+#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x5c94
+#define mmAUX_DPHY_TX_CONTROL 0x5c09
+#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x5c09
+#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x5c25
+#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x5c41
+#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x5c5d
+#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x5c79
+#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x5c95
+#define mmAUX_DPHY_RX_CONTROL0 0x5c0a
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x5c0a
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x5c26
+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x5c42
+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x5c5e
+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x5c7a
+#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x5c96
+#define mmAUX_DPHY_RX_CONTROL1 0x5c0b
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x5c0b
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x5c27
+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x5c43
+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x5c5f
+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x5c7b
+#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x5c97
+#define mmAUX_DPHY_TX_STATUS 0x5c0c
+#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x5c0c
+#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x5c28
+#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x5c44
+#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x5c60
+#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x5c7c
+#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x5c98
+#define mmAUX_DPHY_RX_STATUS 0x5c0d
+#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x5c0d
+#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x5c29
+#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x5c45
+#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x5c61
+#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x5c7d
+#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x5c99
+#define mmAUX_GTC_SYNC_CONTROL 0x5c0e
+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x5c0e
+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x5c2a
+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x5c46
+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x5c62
+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x5c7e
+#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x5c9a
+#define mmAUX_GTC_SYNC_ERROR_CONTROL 0x5c0f
+#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x5c0f
+#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x5c2b
+#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x5c47
+#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x5c63
+#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x5c7f
+#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x5c9b
+#define mmAUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10
+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10
+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c2c
+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c48
+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c64
+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c80
+#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c9c
+#define mmAUX_GTC_SYNC_STATUS 0x5c11
+#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x5c11
+#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x5c2d
+#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x5c49
+#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x5c65
+#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x5c81
+#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x5c9d
+#define mmAUX_GTC_SYNC_DATA 0x5c12
+#define mmDP_AUX0_AUX_GTC_SYNC_DATA 0x5c12
+#define mmDP_AUX1_AUX_GTC_SYNC_DATA 0x5c2e
+#define mmDP_AUX2_AUX_GTC_SYNC_DATA 0x5c4a
+#define mmDP_AUX3_AUX_GTC_SYNC_DATA 0x5c66
+#define mmDP_AUX4_AUX_GTC_SYNC_DATA 0x5c82
+#define mmDP_AUX5_AUX_GTC_SYNC_DATA 0x5c9e
+#define mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13
+#define mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13
+#define mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c2f
+#define mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c4b
+#define mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c67
+#define mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c83
+#define mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c9f
+#define mmAUX_TEST_DEBUG_INDEX 0x5c14
+#define mmDP_AUX0_AUX_TEST_DEBUG_INDEX 0x5c14
+#define mmDP_AUX1_AUX_TEST_DEBUG_INDEX 0x5c30
+#define mmDP_AUX2_AUX_TEST_DEBUG_INDEX 0x5c4c
+#define mmDP_AUX3_AUX_TEST_DEBUG_INDEX 0x5c68
+#define mmDP_AUX4_AUX_TEST_DEBUG_INDEX 0x5c84
+#define mmDP_AUX5_AUX_TEST_DEBUG_INDEX 0x5ca0
+#define mmAUX_TEST_DEBUG_DATA 0x5c15
+#define mmDP_AUX0_AUX_TEST_DEBUG_DATA 0x5c15
+#define mmDP_AUX1_AUX_TEST_DEBUG_DATA 0x5c31
+#define mmDP_AUX2_AUX_TEST_DEBUG_DATA 0x5c4d
+#define mmDP_AUX3_AUX_TEST_DEBUG_DATA 0x5c69
+#define mmDP_AUX4_AUX_TEST_DEBUG_DATA 0x5c85
+#define mmDP_AUX5_AUX_TEST_DEBUG_DATA 0x5ca1
+#define ixDP_AUX_DEBUG_A 0x10
+#define ixDP_AUX_DEBUG_B 0x11
+#define ixDP_AUX_DEBUG_C 0x12
+#define ixDP_AUX_DEBUG_D 0x13
+#define ixDP_AUX_DEBUG_E 0x14
+#define ixDP_AUX_DEBUG_F 0x15
+#define ixDP_AUX_DEBUG_G 0x16
+#define ixDP_AUX_DEBUG_H 0x17
+#define ixDP_AUX_DEBUG_I 0x18
+#define ixDP_AUX_DEBUG_J 0x19
+#define ixDP_AUX_DEBUG_K 0x1a
+#define ixDP_AUX_DEBUG_L 0x1b
+#define ixDP_AUX_DEBUG_M 0x1c
+#define ixDP_AUX_DEBUG_N 0x1d
+#define ixDP_AUX_DEBUG_O 0x1e
+#define ixDP_AUX_DEBUG_P 0x1f
+#define ixDP_AUX_DEBUG_Q 0x20
+#define mmDVO_ENABLE 0x16a0
+#define mmDVO_SOURCE_SELECT 0x16a1
+#define mmDVO_OUTPUT 0x16a2
+#define mmDVO_CONTROL 0x16a3
+#define mmDVO_CRC_EN 0x16a4
+#define mmDVO_CRC2_SIG_MASK 0x16a5
+#define mmDVO_CRC2_SIG_RESULT 0x16a6
+#define mmDVO_FIFO_ERROR_STATUS 0x16a7
+#define mmDVO_TEST_DEBUG_INDEX 0x16a8
+#define mmDVO_TEST_DEBUG_DATA 0x16a9
+#define mmFBC_CNTL 0x280
+#define mmFBC_IDLE_MASK 0x281
+#define mmFBC_IDLE_FORCE_CLEAR_MASK 0x282
+#define mmFBC_START_STOP_DELAY 0x283
+#define mmFBC_COMP_CNTL 0x284
+#define mmFBC_COMP_MODE 0x285
+#define mmFBC_DEBUG0 0x286
+#define mmFBC_DEBUG1 0x287
+#define mmFBC_DEBUG2 0x288
+#define mmFBC_IND_LUT0 0x289
+#define mmFBC_IND_LUT1 0x28a
+#define mmFBC_IND_LUT2 0x28b
+#define mmFBC_IND_LUT3 0x28c
+#define mmFBC_IND_LUT4 0x28d
+#define mmFBC_IND_LUT5 0x28e
+#define mmFBC_IND_LUT6 0x28f
+#define mmFBC_IND_LUT7 0x290
+#define mmFBC_IND_LUT8 0x291
+#define mmFBC_IND_LUT9 0x292
+#define mmFBC_IND_LUT10 0x293
+#define mmFBC_IND_LUT11 0x294
+#define mmFBC_IND_LUT12 0x295
+#define mmFBC_IND_LUT13 0x296
+#define mmFBC_IND_LUT14 0x297
+#define mmFBC_IND_LUT15 0x298
+#define mmFBC_CSM_REGION_OFFSET_01 0x299
+#define mmFBC_CSM_REGION_OFFSET_23 0x29a
+#define mmFBC_CLIENT_REGION_MASK 0x29b
+#define mmFBC_DEBUG_COMP 0x29c
+#define mmFBC_DEBUG_CSR 0x29d
+#define mmFBC_DEBUG_CSR_RDATA 0x29e
+#define mmFBC_DEBUG_CSR_WDATA 0x29f
+#define mmFBC_DEBUG_CSR_RDATA_HI 0x2a0
+#define mmFBC_DEBUG_CSR_WDATA_HI 0x2a1
+#define mmFBC_MISC 0x2a2
+#define mmFBC_STATUS 0x2a3
+#define mmFBC_TEST_DEBUG_INDEX 0x2a4
+#define mmFBC_TEST_DEBUG_DATA 0x2a5
+#define mmFMT_CLAMP_COMPONENT_R 0x1be8
+#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x1be8
+#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1de8
+#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x1fe8
+#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x41e8
+#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x43e8
+#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x45e8
+#define mmFMT_CLAMP_COMPONENT_G 0x1be9
+#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x1be9
+#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1de9
+#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x1fe9
+#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x41e9
+#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x43e9
+#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x45e9
+#define mmFMT_CLAMP_COMPONENT_B 0x1bea
+#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x1bea
+#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1dea
+#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x1fea
+#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x41ea
+#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x43ea
+#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x45ea
+#define mmFMT_DYNAMIC_EXP_CNTL 0x1bed
+#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1bed
+#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1ded
+#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x1fed
+#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x41ed
+#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x43ed
+#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x45ed
+#define mmFMT_CONTROL 0x1bee
+#define mmFMT0_FMT_CONTROL 0x1bee
+#define mmFMT1_FMT_CONTROL 0x1dee
+#define mmFMT2_FMT_CONTROL 0x1fee
+#define mmFMT3_FMT_CONTROL 0x41ee
+#define mmFMT4_FMT_CONTROL 0x43ee
+#define mmFMT5_FMT_CONTROL 0x45ee
+#define mmFMT_FORCE_OUTPUT_CNTL 0x1bef
+#define mmFMT0_FMT_FORCE_OUTPUT_CNTL 0x1bef
+#define mmFMT1_FMT_FORCE_OUTPUT_CNTL 0x1def
+#define mmFMT2_FMT_FORCE_OUTPUT_CNTL 0x1fef
+#define mmFMT3_FMT_FORCE_OUTPUT_CNTL 0x41ef
+#define mmFMT4_FMT_FORCE_OUTPUT_CNTL 0x43ef
+#define mmFMT5_FMT_FORCE_OUTPUT_CNTL 0x45ef
+#define mmFMT_FORCE_DATA_0_1 0x1bf0
+#define mmFMT0_FMT_FORCE_DATA_0_1 0x1bf0
+#define mmFMT1_FMT_FORCE_DATA_0_1 0x1df0
+#define mmFMT2_FMT_FORCE_DATA_0_1 0x1ff0
+#define mmFMT3_FMT_FORCE_DATA_0_1 0x41f0
+#define mmFMT4_FMT_FORCE_DATA_0_1 0x43f0
+#define mmFMT5_FMT_FORCE_DATA_0_1 0x45f0
+#define mmFMT_FORCE_DATA_2_3 0x1bf1
+#define mmFMT0_FMT_FORCE_DATA_2_3 0x1bf1
+#define mmFMT1_FMT_FORCE_DATA_2_3 0x1df1
+#define mmFMT2_FMT_FORCE_DATA_2_3 0x1ff1
+#define mmFMT3_FMT_FORCE_DATA_2_3 0x41f1
+#define mmFMT4_FMT_FORCE_DATA_2_3 0x43f1
+#define mmFMT5_FMT_FORCE_DATA_2_3 0x45f1
+#define mmFMT_BIT_DEPTH_CONTROL 0x1bf2
+#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1bf2
+#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1df2
+#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x1ff2
+#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x41f2
+#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x43f2
+#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x45f2
+#define mmFMT_DITHER_RAND_R_SEED 0x1bf3
+#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1bf3
+#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x1df3
+#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x1ff3
+#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x41f3
+#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x43f3
+#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x45f3
+#define mmFMT_DITHER_RAND_G_SEED 0x1bf4
+#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1bf4
+#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x1df4
+#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x1ff4
+#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x41f4
+#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x43f4
+#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x45f4
+#define mmFMT_DITHER_RAND_B_SEED 0x1bf5
+#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1bf5
+#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x1df5
+#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x1ff5
+#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x41f5
+#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x43f5
+#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x45f5
+#define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6
+#define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6
+#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1df6
+#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1ff6
+#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41f6
+#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x43f6
+#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x45f6
+#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7
+#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7
+#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1df7
+#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1ff7
+#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41f7
+#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x43f7
+#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x45f7
+#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8
+#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8
+#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1df8
+#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1ff8
+#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41f8
+#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x43f8
+#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x45f8
+#define mmFMT_CLAMP_CNTL 0x1bf9
+#define mmFMT0_FMT_CLAMP_CNTL 0x1bf9
+#define mmFMT1_FMT_CLAMP_CNTL 0x1df9
+#define mmFMT2_FMT_CLAMP_CNTL 0x1ff9
+#define mmFMT3_FMT_CLAMP_CNTL 0x41f9
+#define mmFMT4_FMT_CLAMP_CNTL 0x43f9
+#define mmFMT5_FMT_CLAMP_CNTL 0x45f9
+#define mmFMT_CRC_CNTL 0x1bfa
+#define mmFMT0_FMT_CRC_CNTL 0x1bfa
+#define mmFMT1_FMT_CRC_CNTL 0x1dfa
+#define mmFMT2_FMT_CRC_CNTL 0x1ffa
+#define mmFMT3_FMT_CRC_CNTL 0x41fa
+#define mmFMT4_FMT_CRC_CNTL 0x43fa
+#define mmFMT5_FMT_CRC_CNTL 0x45fa
+#define mmFMT_CRC_SIG_RED_GREEN_MASK 0x1bfb
+#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1bfb
+#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1dfb
+#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x1ffb
+#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x41fb
+#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x43fb
+#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x45fb
+#define mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc
+#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc
+#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1dfc
+#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1ffc
+#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41fc
+#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x43fc
+#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x45fc
+#define mmFMT_CRC_SIG_RED_GREEN 0x1bfd
+#define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1bfd
+#define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1dfd
+#define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x1ffd
+#define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x41fd
+#define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x43fd
+#define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x45fd
+#define mmFMT_CRC_SIG_BLUE_CONTROL 0x1bfe
+#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1bfe
+#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1dfe
+#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x1ffe
+#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x41fe
+#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x43fe
+#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x45fe
+#define mmFMT_DEBUG_CNTL 0x1bff
+#define mmFMT0_FMT_DEBUG_CNTL 0x1bff
+#define mmFMT1_FMT_DEBUG_CNTL 0x1dff
+#define mmFMT2_FMT_DEBUG_CNTL 0x1fff
+#define mmFMT3_FMT_DEBUG_CNTL 0x41ff
+#define mmFMT4_FMT_DEBUG_CNTL 0x43ff
+#define mmFMT5_FMT_DEBUG_CNTL 0x45ff
+#define mmFMT_TEST_DEBUG_INDEX 0x1beb
+#define mmFMT0_FMT_TEST_DEBUG_INDEX 0x1beb
+#define mmFMT1_FMT_TEST_DEBUG_INDEX 0x1deb
+#define mmFMT2_FMT_TEST_DEBUG_INDEX 0x1feb
+#define mmFMT3_FMT_TEST_DEBUG_INDEX 0x41eb
+#define mmFMT4_FMT_TEST_DEBUG_INDEX 0x43eb
+#define mmFMT5_FMT_TEST_DEBUG_INDEX 0x45eb
+#define mmFMT_TEST_DEBUG_DATA 0x1bec
+#define mmFMT0_FMT_TEST_DEBUG_DATA 0x1bec
+#define mmFMT1_FMT_TEST_DEBUG_DATA 0x1dec
+#define mmFMT2_FMT_TEST_DEBUG_DATA 0x1fec
+#define mmFMT3_FMT_TEST_DEBUG_DATA 0x41ec
+#define mmFMT4_FMT_TEST_DEBUG_DATA 0x43ec
+#define mmFMT5_FMT_TEST_DEBUG_DATA 0x45ec
+#define ixFMT_DEBUG0 0x1
+#define ixFMT_DEBUG1 0x2
+#define ixFMT_DEBUG2 0x3
+#define ixFMT_DEBUG_ID 0x0
+#define mmLB_DATA_FORMAT 0x1ac0
+#define mmLB0_LB_DATA_FORMAT 0x1ac0
+#define mmLB1_LB_DATA_FORMAT 0x1cc0
+#define mmLB2_LB_DATA_FORMAT 0x1ec0
+#define mmLB3_LB_DATA_FORMAT 0x40c0
+#define mmLB4_LB_DATA_FORMAT 0x42c0
+#define mmLB5_LB_DATA_FORMAT 0x44c0
+#define mmLB_MEMORY_CTRL 0x1ac1
+#define mmLB0_LB_MEMORY_CTRL 0x1ac1
+#define mmLB1_LB_MEMORY_CTRL 0x1cc1
+#define mmLB2_LB_MEMORY_CTRL 0x1ec1
+#define mmLB3_LB_MEMORY_CTRL 0x40c1
+#define mmLB4_LB_MEMORY_CTRL 0x42c1
+#define mmLB5_LB_MEMORY_CTRL 0x44c1
+#define mmLB_MEMORY_SIZE_STATUS 0x1ac2
+#define mmLB0_LB_MEMORY_SIZE_STATUS 0x1ac2
+#define mmLB1_LB_MEMORY_SIZE_STATUS 0x1cc2
+#define mmLB2_LB_MEMORY_SIZE_STATUS 0x1ec2
+#define mmLB3_LB_MEMORY_SIZE_STATUS 0x40c2
+#define mmLB4_LB_MEMORY_SIZE_STATUS 0x42c2
+#define mmLB5_LB_MEMORY_SIZE_STATUS 0x44c2
+#define mmLB_DESKTOP_HEIGHT 0x1ac3
+#define mmLB0_LB_DESKTOP_HEIGHT 0x1ac3
+#define mmLB1_LB_DESKTOP_HEIGHT 0x1cc3
+#define mmLB2_LB_DESKTOP_HEIGHT 0x1ec3
+#define mmLB3_LB_DESKTOP_HEIGHT 0x40c3
+#define mmLB4_LB_DESKTOP_HEIGHT 0x42c3
+#define mmLB5_LB_DESKTOP_HEIGHT 0x44c3
+#define mmLB_VLINE_START_END 0x1ac4
+#define mmLB0_LB_VLINE_START_END 0x1ac4
+#define mmLB1_LB_VLINE_START_END 0x1cc4
+#define mmLB2_LB_VLINE_START_END 0x1ec4
+#define mmLB3_LB_VLINE_START_END 0x40c4
+#define mmLB4_LB_VLINE_START_END 0x42c4
+#define mmLB5_LB_VLINE_START_END 0x44c4
+#define mmLB_VLINE2_START_END 0x1ac5
+#define mmLB0_LB_VLINE2_START_END 0x1ac5
+#define mmLB1_LB_VLINE2_START_END 0x1cc5
+#define mmLB2_LB_VLINE2_START_END 0x1ec5
+#define mmLB3_LB_VLINE2_START_END 0x40c5
+#define mmLB4_LB_VLINE2_START_END 0x42c5
+#define mmLB5_LB_VLINE2_START_END 0x44c5
+#define mmLB_V_COUNTER 0x1ac6
+#define mmLB0_LB_V_COUNTER 0x1ac6
+#define mmLB1_LB_V_COUNTER 0x1cc6
+#define mmLB2_LB_V_COUNTER 0x1ec6
+#define mmLB3_LB_V_COUNTER 0x40c6
+#define mmLB4_LB_V_COUNTER 0x42c6
+#define mmLB5_LB_V_COUNTER 0x44c6
+#define mmLB_SNAPSHOT_V_COUNTER 0x1ac7
+#define mmLB0_LB_SNAPSHOT_V_COUNTER 0x1ac7
+#define mmLB1_LB_SNAPSHOT_V_COUNTER 0x1cc7
+#define mmLB2_LB_SNAPSHOT_V_COUNTER 0x1ec7
+#define mmLB3_LB_SNAPSHOT_V_COUNTER 0x40c7
+#define mmLB4_LB_SNAPSHOT_V_COUNTER 0x42c7
+#define mmLB5_LB_SNAPSHOT_V_COUNTER 0x44c7
+#define mmLB_INTERRUPT_MASK 0x1ac8
+#define mmLB0_LB_INTERRUPT_MASK 0x1ac8
+#define mmLB1_LB_INTERRUPT_MASK 0x1cc8
+#define mmLB2_LB_INTERRUPT_MASK 0x1ec8
+#define mmLB3_LB_INTERRUPT_MASK 0x40c8
+#define mmLB4_LB_INTERRUPT_MASK 0x42c8
+#define mmLB5_LB_INTERRUPT_MASK 0x44c8
+#define mmLB_VLINE_STATUS 0x1ac9
+#define mmLB0_LB_VLINE_STATUS 0x1ac9
+#define mmLB1_LB_VLINE_STATUS 0x1cc9
+#define mmLB2_LB_VLINE_STATUS 0x1ec9
+#define mmLB3_LB_VLINE_STATUS 0x40c9
+#define mmLB4_LB_VLINE_STATUS 0x42c9
+#define mmLB5_LB_VLINE_STATUS 0x44c9
+#define mmLB_VLINE2_STATUS 0x1aca
+#define mmLB0_LB_VLINE2_STATUS 0x1aca
+#define mmLB1_LB_VLINE2_STATUS 0x1cca
+#define mmLB2_LB_VLINE2_STATUS 0x1eca
+#define mmLB3_LB_VLINE2_STATUS 0x40ca
+#define mmLB4_LB_VLINE2_STATUS 0x42ca
+#define mmLB5_LB_VLINE2_STATUS 0x44ca
+#define mmLB_VBLANK_STATUS 0x1acb
+#define mmLB0_LB_VBLANK_STATUS 0x1acb
+#define mmLB1_LB_VBLANK_STATUS 0x1ccb
+#define mmLB2_LB_VBLANK_STATUS 0x1ecb
+#define mmLB3_LB_VBLANK_STATUS 0x40cb
+#define mmLB4_LB_VBLANK_STATUS 0x42cb
+#define mmLB5_LB_VBLANK_STATUS 0x44cb
+#define mmLB_SYNC_RESET_SEL 0x1acc
+#define mmLB0_LB_SYNC_RESET_SEL 0x1acc
+#define mmLB1_LB_SYNC_RESET_SEL 0x1ccc
+#define mmLB2_LB_SYNC_RESET_SEL 0x1ecc
+#define mmLB3_LB_SYNC_RESET_SEL 0x40cc
+#define mmLB4_LB_SYNC_RESET_SEL 0x42cc
+#define mmLB5_LB_SYNC_RESET_SEL 0x44cc
+#define mmLB_BLACK_KEYER_R_CR 0x1acd
+#define mmLB0_LB_BLACK_KEYER_R_CR 0x1acd
+#define mmLB1_LB_BLACK_KEYER_R_CR 0x1ccd
+#define mmLB2_LB_BLACK_KEYER_R_CR 0x1ecd
+#define mmLB3_LB_BLACK_KEYER_R_CR 0x40cd
+#define mmLB4_LB_BLACK_KEYER_R_CR 0x42cd
+#define mmLB5_LB_BLACK_KEYER_R_CR 0x44cd
+#define mmLB_BLACK_KEYER_G_Y 0x1ace
+#define mmLB0_LB_BLACK_KEYER_G_Y 0x1ace
+#define mmLB1_LB_BLACK_KEYER_G_Y 0x1cce
+#define mmLB2_LB_BLACK_KEYER_G_Y 0x1ece
+#define mmLB3_LB_BLACK_KEYER_G_Y 0x40ce
+#define mmLB4_LB_BLACK_KEYER_G_Y 0x42ce
+#define mmLB5_LB_BLACK_KEYER_G_Y 0x44ce
+#define mmLB_BLACK_KEYER_B_CB 0x1acf
+#define mmLB0_LB_BLACK_KEYER_B_CB 0x1acf
+#define mmLB1_LB_BLACK_KEYER_B_CB 0x1ccf
+#define mmLB2_LB_BLACK_KEYER_B_CB 0x1ecf
+#define mmLB3_LB_BLACK_KEYER_B_CB 0x40cf
+#define mmLB4_LB_BLACK_KEYER_B_CB 0x42cf
+#define mmLB5_LB_BLACK_KEYER_B_CB 0x44cf
+#define mmLB_KEYER_COLOR_CTRL 0x1ad0
+#define mmLB0_LB_KEYER_COLOR_CTRL 0x1ad0
+#define mmLB1_LB_KEYER_COLOR_CTRL 0x1cd0
+#define mmLB2_LB_KEYER_COLOR_CTRL 0x1ed0
+#define mmLB3_LB_KEYER_COLOR_CTRL 0x40d0
+#define mmLB4_LB_KEYER_COLOR_CTRL 0x42d0
+#define mmLB5_LB_KEYER_COLOR_CTRL 0x44d0
+#define mmLB_KEYER_COLOR_R_CR 0x1ad1
+#define mmLB0_LB_KEYER_COLOR_R_CR 0x1ad1
+#define mmLB1_LB_KEYER_COLOR_R_CR 0x1cd1
+#define mmLB2_LB_KEYER_COLOR_R_CR 0x1ed1
+#define mmLB3_LB_KEYER_COLOR_R_CR 0x40d1
+#define mmLB4_LB_KEYER_COLOR_R_CR 0x42d1
+#define mmLB5_LB_KEYER_COLOR_R_CR 0x44d1
+#define mmLB_KEYER_COLOR_G_Y 0x1ad2
+#define mmLB0_LB_KEYER_COLOR_G_Y 0x1ad2
+#define mmLB1_LB_KEYER_COLOR_G_Y 0x1cd2
+#define mmLB2_LB_KEYER_COLOR_G_Y 0x1ed2
+#define mmLB3_LB_KEYER_COLOR_G_Y 0x40d2
+#define mmLB4_LB_KEYER_COLOR_G_Y 0x42d2
+#define mmLB5_LB_KEYER_COLOR_G_Y 0x44d2
+#define mmLB_KEYER_COLOR_B_CB 0x1ad3
+#define mmLB0_LB_KEYER_COLOR_B_CB 0x1ad3
+#define mmLB1_LB_KEYER_COLOR_B_CB 0x1cd3
+#define mmLB2_LB_KEYER_COLOR_B_CB 0x1ed3
+#define mmLB3_LB_KEYER_COLOR_B_CB 0x40d3
+#define mmLB4_LB_KEYER_COLOR_B_CB 0x42d3
+#define mmLB5_LB_KEYER_COLOR_B_CB 0x44d3
+#define mmLB_KEYER_COLOR_REP_R_CR 0x1ad4
+#define mmLB0_LB_KEYER_COLOR_REP_R_CR 0x1ad4
+#define mmLB1_LB_KEYER_COLOR_REP_R_CR 0x1cd4
+#define mmLB2_LB_KEYER_COLOR_REP_R_CR 0x1ed4
+#define mmLB3_LB_KEYER_COLOR_REP_R_CR 0x40d4
+#define mmLB4_LB_KEYER_COLOR_REP_R_CR 0x42d4
+#define mmLB5_LB_KEYER_COLOR_REP_R_CR 0x44d4
+#define mmLB_KEYER_COLOR_REP_G_Y 0x1ad5
+#define mmLB0_LB_KEYER_COLOR_REP_G_Y 0x1ad5
+#define mmLB1_LB_KEYER_COLOR_REP_G_Y 0x1cd5
+#define mmLB2_LB_KEYER_COLOR_REP_G_Y 0x1ed5
+#define mmLB3_LB_KEYER_COLOR_REP_G_Y 0x40d5
+#define mmLB4_LB_KEYER_COLOR_REP_G_Y 0x42d5
+#define mmLB5_LB_KEYER_COLOR_REP_G_Y 0x44d5
+#define mmLB_KEYER_COLOR_REP_B_CB 0x1ad6
+#define mmLB0_LB_KEYER_COLOR_REP_B_CB 0x1ad6
+#define mmLB1_LB_KEYER_COLOR_REP_B_CB 0x1cd6
+#define mmLB2_LB_KEYER_COLOR_REP_B_CB 0x1ed6
+#define mmLB3_LB_KEYER_COLOR_REP_B_CB 0x40d6
+#define mmLB4_LB_KEYER_COLOR_REP_B_CB 0x42d6
+#define mmLB5_LB_KEYER_COLOR_REP_B_CB 0x44d6
+#define mmLB_BUFFER_LEVEL_STATUS 0x1ad7
+#define mmLB0_LB_BUFFER_LEVEL_STATUS 0x1ad7
+#define mmLB1_LB_BUFFER_LEVEL_STATUS 0x1cd7
+#define mmLB2_LB_BUFFER_LEVEL_STATUS 0x1ed7
+#define mmLB3_LB_BUFFER_LEVEL_STATUS 0x40d7
+#define mmLB4_LB_BUFFER_LEVEL_STATUS 0x42d7
+#define mmLB5_LB_BUFFER_LEVEL_STATUS 0x44d7
+#define mmLB_BUFFER_URGENCY_CTRL 0x1ad8
+#define mmLB0_LB_BUFFER_URGENCY_CTRL 0x1ad8
+#define mmLB1_LB_BUFFER_URGENCY_CTRL 0x1cd8
+#define mmLB2_LB_BUFFER_URGENCY_CTRL 0x1ed8
+#define mmLB3_LB_BUFFER_URGENCY_CTRL 0x40d8
+#define mmLB4_LB_BUFFER_URGENCY_CTRL 0x42d8
+#define mmLB5_LB_BUFFER_URGENCY_CTRL 0x44d8
+#define mmLB_BUFFER_URGENCY_STATUS 0x1ad9
+#define mmLB0_LB_BUFFER_URGENCY_STATUS 0x1ad9
+#define mmLB1_LB_BUFFER_URGENCY_STATUS 0x1cd9
+#define mmLB2_LB_BUFFER_URGENCY_STATUS 0x1ed9
+#define mmLB3_LB_BUFFER_URGENCY_STATUS 0x40d9
+#define mmLB4_LB_BUFFER_URGENCY_STATUS 0x42d9
+#define mmLB5_LB_BUFFER_URGENCY_STATUS 0x44d9
+#define mmLB_BUFFER_STATUS 0x1ada
+#define mmLB0_LB_BUFFER_STATUS 0x1ada
+#define mmLB1_LB_BUFFER_STATUS 0x1cda
+#define mmLB2_LB_BUFFER_STATUS 0x1eda
+#define mmLB3_LB_BUFFER_STATUS 0x40da
+#define mmLB4_LB_BUFFER_STATUS 0x42da
+#define mmLB5_LB_BUFFER_STATUS 0x44da
+#define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1adc
+#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1adc
+#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1cdc
+#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x1edc
+#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x40dc
+#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x42dc
+#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x44dc
+#define mmMVP_AFR_FLIP_MODE 0x1ae0
+#define mmLB0_MVP_AFR_FLIP_MODE 0x1ae0
+#define mmLB1_MVP_AFR_FLIP_MODE 0x1ce0
+#define mmLB2_MVP_AFR_FLIP_MODE 0x1ee0
+#define mmLB3_MVP_AFR_FLIP_MODE 0x40e0
+#define mmLB4_MVP_AFR_FLIP_MODE 0x42e0
+#define mmLB5_MVP_AFR_FLIP_MODE 0x44e0
+#define mmMVP_AFR_FLIP_FIFO_CNTL 0x1ae1
+#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1ae1
+#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1ce1
+#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x1ee1
+#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x40e1
+#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x42e1
+#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x44e1
+#define mmMVP_FLIP_LINE_NUM_INSERT 0x1ae2
+#define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ae2
+#define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1ce2
+#define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x1ee2
+#define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x40e2
+#define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x42e2
+#define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x44e2
+#define mmDC_MVP_LB_CONTROL 0x1ae3
+#define mmLB0_DC_MVP_LB_CONTROL 0x1ae3
+#define mmLB1_DC_MVP_LB_CONTROL 0x1ce3
+#define mmLB2_DC_MVP_LB_CONTROL 0x1ee3
+#define mmLB3_DC_MVP_LB_CONTROL 0x40e3
+#define mmLB4_DC_MVP_LB_CONTROL 0x42e3
+#define mmLB5_DC_MVP_LB_CONTROL 0x44e3
+#define mmLB_DEBUG 0x1ae4
+#define mmLB0_LB_DEBUG 0x1ae4
+#define mmLB1_LB_DEBUG 0x1ce4
+#define mmLB2_LB_DEBUG 0x1ee4
+#define mmLB3_LB_DEBUG 0x40e4
+#define mmLB4_LB_DEBUG 0x42e4
+#define mmLB5_LB_DEBUG 0x44e4
+#define mmLB_DEBUG2 0x1ae5
+#define mmLB0_LB_DEBUG2 0x1ae5
+#define mmLB1_LB_DEBUG2 0x1ce5
+#define mmLB2_LB_DEBUG2 0x1ee5
+#define mmLB3_LB_DEBUG2 0x40e5
+#define mmLB4_LB_DEBUG2 0x42e5
+#define mmLB5_LB_DEBUG2 0x44e5
+#define mmLB_DEBUG3 0x1ae6
+#define mmLB0_LB_DEBUG3 0x1ae6
+#define mmLB1_LB_DEBUG3 0x1ce6
+#define mmLB2_LB_DEBUG3 0x1ee6
+#define mmLB3_LB_DEBUG3 0x40e6
+#define mmLB4_LB_DEBUG3 0x42e6
+#define mmLB5_LB_DEBUG3 0x44e6
+#define mmLB_TEST_DEBUG_INDEX 0x1afe
+#define mmLB0_LB_TEST_DEBUG_INDEX 0x1afe
+#define mmLB1_LB_TEST_DEBUG_INDEX 0x1cfe
+#define mmLB2_LB_TEST_DEBUG_INDEX 0x1efe
+#define mmLB3_LB_TEST_DEBUG_INDEX 0x40fe
+#define mmLB4_LB_TEST_DEBUG_INDEX 0x42fe
+#define mmLB5_LB_TEST_DEBUG_INDEX 0x44fe
+#define mmLB_TEST_DEBUG_DATA 0x1aff
+#define mmLB0_LB_TEST_DEBUG_DATA 0x1aff
+#define mmLB1_LB_TEST_DEBUG_DATA 0x1cff
+#define mmLB2_LB_TEST_DEBUG_DATA 0x1eff
+#define mmLB3_LB_TEST_DEBUG_DATA 0x40ff
+#define mmLB4_LB_TEST_DEBUG_DATA 0x42ff
+#define mmLB5_LB_TEST_DEBUG_DATA 0x44ff
+#define mmLBV_DATA_FORMAT 0x463c
+#define mmLBV_MEMORY_CTRL 0x463d
+#define mmLBV_MEMORY_SIZE_STATUS 0x463e
+#define mmLBV_DESKTOP_HEIGHT 0x463f
+#define mmLBV_VLINE_START_END 0x4640
+#define mmLBV_VLINE2_START_END 0x4641
+#define mmLBV_V_COUNTER 0x4642
+#define mmLBV_SNAPSHOT_V_COUNTER 0x4643
+#define mmLBV_V_COUNTER_CHROMA 0x4644
+#define mmLBV_SNAPSHOT_V_COUNTER_CHROMA 0x4645
+#define mmLBV_INTERRUPT_MASK 0x4646
+#define mmLBV_VLINE_STATUS 0x4647
+#define mmLBV_VLINE2_STATUS 0x4648
+#define mmLBV_VBLANK_STATUS 0x4649
+#define mmLBV_SYNC_RESET_SEL 0x464a
+#define mmLBV_BLACK_KEYER_R_CR 0x464b
+#define mmLBV_BLACK_KEYER_G_Y 0x464c
+#define mmLBV_BLACK_KEYER_B_CB 0x464d
+#define mmLBV_KEYER_COLOR_CTRL 0x464e
+#define mmLBV_KEYER_COLOR_R_CR 0x464f
+#define mmLBV_KEYER_COLOR_G_Y 0x4650
+#define mmLBV_KEYER_COLOR_B_CB 0x4651
+#define mmLBV_KEYER_COLOR_REP_R_CR 0x4652
+#define mmLBV_KEYER_COLOR_REP_G_Y 0x4653
+#define mmLBV_KEYER_COLOR_REP_B_CB 0x4654
+#define mmLBV_BUFFER_LEVEL_STATUS 0x4655
+#define mmLBV_BUFFER_URGENCY_CTRL 0x4656
+#define mmLBV_BUFFER_URGENCY_STATUS 0x4657
+#define mmLBV_BUFFER_STATUS 0x4658
+#define mmLBV_NO_OUTSTANDING_REQ_STATUS 0x4659
+#define mmLBV_DEBUG 0x465a
+#define mmLBV_DEBUG2 0x465b
+#define mmLBV_DEBUG3 0x465c
+#define mmLBV_TEST_DEBUG_INDEX 0x4666
+#define mmLBV_TEST_DEBUG_DATA 0x4667
+#define mmMVP_CONTROL1 0x2ac
+#define mmMVP_CONTROL2 0x2ad
+#define mmMVP_FIFO_CONTROL 0x2ae
+#define mmMVP_FIFO_STATUS 0x2af
+#define mmMVP_SLAVE_STATUS 0x2b0
+#define mmMVP_INBAND_CNTL_CAP 0x2b1
+#define mmMVP_BLACK_KEYER 0x2b2
+#define mmMVP_CRC_CNTL 0x2b3
+#define mmMVP_CRC_RESULT_BLUE_GREEN 0x2b4
+#define mmMVP_CRC_RESULT_RED 0x2b5
+#define mmMVP_CONTROL3 0x2b6
+#define mmMVP_RECEIVE_CNT_CNTL1 0x2b7
+#define mmMVP_RECEIVE_CNT_CNTL2 0x2b8
+#define mmMVP_DEBUG 0x2bb
+#define mmMVP_TEST_DEBUG_INDEX 0x2b9
+#define mmMVP_TEST_DEBUG_DATA 0x2ba
+#define ixMVP_DEBUG_12 0xc
+#define ixMVP_DEBUG_13 0xd
+#define ixMVP_DEBUG_14 0xe
+#define ixMVP_DEBUG_15 0xf
+#define ixMVP_DEBUG_16 0x10
+#define ixMVP_DEBUG_17 0x11
+#define mmSCL_COEF_RAM_SELECT 0x1b40
+#define mmSCL0_SCL_COEF_RAM_SELECT 0x1b40
+#define mmSCL1_SCL_COEF_RAM_SELECT 0x1d40
+#define mmSCL2_SCL_COEF_RAM_SELECT 0x1f40
+#define mmSCL3_SCL_COEF_RAM_SELECT 0x4140
+#define mmSCL4_SCL_COEF_RAM_SELECT 0x4340
+#define mmSCL5_SCL_COEF_RAM_SELECT 0x4540
+#define mmSCL_COEF_RAM_TAP_DATA 0x1b41
+#define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1b41
+#define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1d41
+#define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x1f41
+#define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4141
+#define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4341
+#define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4541
+#define mmSCL_MODE 0x1b42
+#define mmSCL0_SCL_MODE 0x1b42
+#define mmSCL1_SCL_MODE 0x1d42
+#define mmSCL2_SCL_MODE 0x1f42
+#define mmSCL3_SCL_MODE 0x4142
+#define mmSCL4_SCL_MODE 0x4342
+#define mmSCL5_SCL_MODE 0x4542
+#define mmSCL_TAP_CONTROL 0x1b43
+#define mmSCL0_SCL_TAP_CONTROL 0x1b43
+#define mmSCL1_SCL_TAP_CONTROL 0x1d43
+#define mmSCL2_SCL_TAP_CONTROL 0x1f43
+#define mmSCL3_SCL_TAP_CONTROL 0x4143
+#define mmSCL4_SCL_TAP_CONTROL 0x4343
+#define mmSCL5_SCL_TAP_CONTROL 0x4543
+#define mmSCL_CONTROL 0x1b44
+#define mmSCL0_SCL_CONTROL 0x1b44
+#define mmSCL1_SCL_CONTROL 0x1d44
+#define mmSCL2_SCL_CONTROL 0x1f44
+#define mmSCL3_SCL_CONTROL 0x4144
+#define mmSCL4_SCL_CONTROL 0x4344
+#define mmSCL5_SCL_CONTROL 0x4544
+#define mmSCL_BYPASS_CONTROL 0x1b45
+#define mmSCL0_SCL_BYPASS_CONTROL 0x1b45
+#define mmSCL1_SCL_BYPASS_CONTROL 0x1d45
+#define mmSCL2_SCL_BYPASS_CONTROL 0x1f45
+#define mmSCL3_SCL_BYPASS_CONTROL 0x4145
+#define mmSCL4_SCL_BYPASS_CONTROL 0x4345
+#define mmSCL5_SCL_BYPASS_CONTROL 0x4545
+#define mmSCL_MANUAL_REPLICATE_CONTROL 0x1b46
+#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1b46
+#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1d46
+#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x1f46
+#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4146
+#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4346
+#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4546
+#define mmSCL_AUTOMATIC_MODE_CONTROL 0x1b47
+#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1b47
+#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1d47
+#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x1f47
+#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4147
+#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4347
+#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4547
+#define mmSCL_HORZ_FILTER_CONTROL 0x1b48
+#define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1b48
+#define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1d48
+#define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x1f48
+#define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x4148
+#define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x4348
+#define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4548
+#define mmSCL_HORZ_FILTER_SCALE_RATIO 0x1b49
+#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1b49
+#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1d49
+#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x1f49
+#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x4149
+#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x4349
+#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4549
+#define mmSCL_HORZ_FILTER_INIT 0x1b4a
+#define mmSCL0_SCL_HORZ_FILTER_INIT 0x1b4a
+#define mmSCL1_SCL_HORZ_FILTER_INIT 0x1d4a
+#define mmSCL2_SCL_HORZ_FILTER_INIT 0x1f4a
+#define mmSCL3_SCL_HORZ_FILTER_INIT 0x414a
+#define mmSCL4_SCL_HORZ_FILTER_INIT 0x434a
+#define mmSCL5_SCL_HORZ_FILTER_INIT 0x454a
+#define mmSCL_VERT_FILTER_CONTROL 0x1b4b
+#define mmSCL0_SCL_VERT_FILTER_CONTROL 0x1b4b
+#define mmSCL1_SCL_VERT_FILTER_CONTROL 0x1d4b
+#define mmSCL2_SCL_VERT_FILTER_CONTROL 0x1f4b
+#define mmSCL3_SCL_VERT_FILTER_CONTROL 0x414b
+#define mmSCL4_SCL_VERT_FILTER_CONTROL 0x434b
+#define mmSCL5_SCL_VERT_FILTER_CONTROL 0x454b
+#define mmSCL_VERT_FILTER_SCALE_RATIO 0x1b4c
+#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1b4c
+#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1d4c
+#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x1f4c
+#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x414c
+#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x434c
+#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x454c
+#define mmSCL_VERT_FILTER_INIT 0x1b4d
+#define mmSCL0_SCL_VERT_FILTER_INIT 0x1b4d
+#define mmSCL1_SCL_VERT_FILTER_INIT 0x1d4d
+#define mmSCL2_SCL_VERT_FILTER_INIT 0x1f4d
+#define mmSCL3_SCL_VERT_FILTER_INIT 0x414d
+#define mmSCL4_SCL_VERT_FILTER_INIT 0x434d
+#define mmSCL5_SCL_VERT_FILTER_INIT 0x454d
+#define mmSCL_VERT_FILTER_INIT_BOT 0x1b4e
+#define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1b4e
+#define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1d4e
+#define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x1f4e
+#define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x414e
+#define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x434e
+#define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x454e
+#define mmSCL_ROUND_OFFSET 0x1b4f
+#define mmSCL0_SCL_ROUND_OFFSET 0x1b4f
+#define mmSCL1_SCL_ROUND_OFFSET 0x1d4f
+#define mmSCL2_SCL_ROUND_OFFSET 0x1f4f
+#define mmSCL3_SCL_ROUND_OFFSET 0x414f
+#define mmSCL4_SCL_ROUND_OFFSET 0x434f
+#define mmSCL5_SCL_ROUND_OFFSET 0x454f
+#define mmSCL_UPDATE 0x1b51
+#define mmSCL0_SCL_UPDATE 0x1b51
+#define mmSCL1_SCL_UPDATE 0x1d51
+#define mmSCL2_SCL_UPDATE 0x1f51
+#define mmSCL3_SCL_UPDATE 0x4151
+#define mmSCL4_SCL_UPDATE 0x4351
+#define mmSCL5_SCL_UPDATE 0x4551
+#define mmSCL_F_SHARP_CONTROL 0x1b53
+#define mmSCL0_SCL_F_SHARP_CONTROL 0x1b53
+#define mmSCL1_SCL_F_SHARP_CONTROL 0x1d53
+#define mmSCL2_SCL_F_SHARP_CONTROL 0x1f53
+#define mmSCL3_SCL_F_SHARP_CONTROL 0x4153
+#define mmSCL4_SCL_F_SHARP_CONTROL 0x4353
+#define mmSCL5_SCL_F_SHARP_CONTROL 0x4553
+#define mmSCL_ALU_CONTROL 0x1b54
+#define mmSCL0_SCL_ALU_CONTROL 0x1b54
+#define mmSCL1_SCL_ALU_CONTROL 0x1d54
+#define mmSCL2_SCL_ALU_CONTROL 0x1f54
+#define mmSCL3_SCL_ALU_CONTROL 0x4154
+#define mmSCL4_SCL_ALU_CONTROL 0x4354
+#define mmSCL5_SCL_ALU_CONTROL 0x4554
+#define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1b55
+#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1b55
+#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1d55
+#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x1f55
+#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4155
+#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4355
+#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4555
+#define mmVIEWPORT_START_SECONDARY 0x1b5b
+#define mmSCL0_VIEWPORT_START_SECONDARY 0x1b5b
+#define mmSCL1_VIEWPORT_START_SECONDARY 0x1d5b
+#define mmSCL2_VIEWPORT_START_SECONDARY 0x1f5b
+#define mmSCL3_VIEWPORT_START_SECONDARY 0x415b
+#define mmSCL4_VIEWPORT_START_SECONDARY 0x435b
+#define mmSCL5_VIEWPORT_START_SECONDARY 0x455b
+#define mmVIEWPORT_START 0x1b5c
+#define mmSCL0_VIEWPORT_START 0x1b5c
+#define mmSCL1_VIEWPORT_START 0x1d5c
+#define mmSCL2_VIEWPORT_START 0x1f5c
+#define mmSCL3_VIEWPORT_START 0x415c
+#define mmSCL4_VIEWPORT_START 0x435c
+#define mmSCL5_VIEWPORT_START 0x455c
+#define mmVIEWPORT_SIZE 0x1b5d
+#define mmSCL0_VIEWPORT_SIZE 0x1b5d
+#define mmSCL1_VIEWPORT_SIZE 0x1d5d
+#define mmSCL2_VIEWPORT_SIZE 0x1f5d
+#define mmSCL3_VIEWPORT_SIZE 0x415d
+#define mmSCL4_VIEWPORT_SIZE 0x435d
+#define mmSCL5_VIEWPORT_SIZE 0x455d
+#define mmEXT_OVERSCAN_LEFT_RIGHT 0x1b5e
+#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1b5e
+#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1d5e
+#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x1f5e
+#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x415e
+#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x435e
+#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x455e
+#define mmEXT_OVERSCAN_TOP_BOTTOM 0x1b5f
+#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1b5f
+#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1d5f
+#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x1f5f
+#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x415f
+#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x435f
+#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x455f
+#define mmSCL_MODE_CHANGE_DET1 0x1b60
+#define mmSCL0_SCL_MODE_CHANGE_DET1 0x1b60
+#define mmSCL1_SCL_MODE_CHANGE_DET1 0x1d60
+#define mmSCL2_SCL_MODE_CHANGE_DET1 0x1f60
+#define mmSCL3_SCL_MODE_CHANGE_DET1 0x4160
+#define mmSCL4_SCL_MODE_CHANGE_DET1 0x4360
+#define mmSCL5_SCL_MODE_CHANGE_DET1 0x4560
+#define mmSCL_MODE_CHANGE_DET2 0x1b61
+#define mmSCL0_SCL_MODE_CHANGE_DET2 0x1b61
+#define mmSCL1_SCL_MODE_CHANGE_DET2 0x1d61
+#define mmSCL2_SCL_MODE_CHANGE_DET2 0x1f61
+#define mmSCL3_SCL_MODE_CHANGE_DET2 0x4161
+#define mmSCL4_SCL_MODE_CHANGE_DET2 0x4361
+#define mmSCL5_SCL_MODE_CHANGE_DET2 0x4561
+#define mmSCL_MODE_CHANGE_DET3 0x1b62
+#define mmSCL0_SCL_MODE_CHANGE_DET3 0x1b62
+#define mmSCL1_SCL_MODE_CHANGE_DET3 0x1d62
+#define mmSCL2_SCL_MODE_CHANGE_DET3 0x1f62
+#define mmSCL3_SCL_MODE_CHANGE_DET3 0x4162
+#define mmSCL4_SCL_MODE_CHANGE_DET3 0x4362
+#define mmSCL5_SCL_MODE_CHANGE_DET3 0x4562
+#define mmSCL_MODE_CHANGE_MASK 0x1b63
+#define mmSCL0_SCL_MODE_CHANGE_MASK 0x1b63
+#define mmSCL1_SCL_MODE_CHANGE_MASK 0x1d63
+#define mmSCL2_SCL_MODE_CHANGE_MASK 0x1f63
+#define mmSCL3_SCL_MODE_CHANGE_MASK 0x4163
+#define mmSCL4_SCL_MODE_CHANGE_MASK 0x4363
+#define mmSCL5_SCL_MODE_CHANGE_MASK 0x4563
+#define mmSCL_DEBUG2 0x1b69
+#define mmSCL0_SCL_DEBUG2 0x1b69
+#define mmSCL1_SCL_DEBUG2 0x1d69
+#define mmSCL2_SCL_DEBUG2 0x1f69
+#define mmSCL3_SCL_DEBUG2 0x4169
+#define mmSCL4_SCL_DEBUG2 0x4369
+#define mmSCL5_SCL_DEBUG2 0x4569
+#define mmSCL_DEBUG 0x1b6a
+#define mmSCL0_SCL_DEBUG 0x1b6a
+#define mmSCL1_SCL_DEBUG 0x1d6a
+#define mmSCL2_SCL_DEBUG 0x1f6a
+#define mmSCL3_SCL_DEBUG 0x416a
+#define mmSCL4_SCL_DEBUG 0x436a
+#define mmSCL5_SCL_DEBUG 0x456a
+#define mmSCL_TEST_DEBUG_INDEX 0x1b6b
+#define mmSCL0_SCL_TEST_DEBUG_INDEX 0x1b6b
+#define mmSCL1_SCL_TEST_DEBUG_INDEX 0x1d6b
+#define mmSCL2_SCL_TEST_DEBUG_INDEX 0x1f6b
+#define mmSCL3_SCL_TEST_DEBUG_INDEX 0x416b
+#define mmSCL4_SCL_TEST_DEBUG_INDEX 0x436b
+#define mmSCL5_SCL_TEST_DEBUG_INDEX 0x456b
+#define mmSCL_TEST_DEBUG_DATA 0x1b6c
+#define mmSCL0_SCL_TEST_DEBUG_DATA 0x1b6c
+#define mmSCL1_SCL_TEST_DEBUG_DATA 0x1d6c
+#define mmSCL2_SCL_TEST_DEBUG_DATA 0x1f6c
+#define mmSCL3_SCL_TEST_DEBUG_DATA 0x416c
+#define mmSCL4_SCL_TEST_DEBUG_DATA 0x436c
+#define mmSCL5_SCL_TEST_DEBUG_DATA 0x456c
+#define mmSCLV_COEF_RAM_SELECT 0x4670
+#define mmSCLV_COEF_RAM_TAP_DATA 0x4671
+#define mmSCLV_MODE 0x4672
+#define mmSCLV_TAP_CONTROL 0x4673
+#define mmSCLV_CONTROL 0x4674
+#define mmSCLV_MANUAL_REPLICATE_CONTROL 0x4675
+#define mmSCLV_AUTOMATIC_MODE_CONTROL 0x4676
+#define mmSCLV_HORZ_FILTER_CONTROL 0x4677
+#define mmSCLV_HORZ_FILTER_SCALE_RATIO 0x4678
+#define mmSCLV_HORZ_FILTER_INIT 0x4679
+#define mmSCLV_HORZ_FILTER_SCALE_RATIO_C 0x467a
+#define mmSCLV_HORZ_FILTER_INIT_C 0x467b
+#define mmSCLV_VERT_FILTER_CONTROL 0x467c
+#define mmSCLV_VERT_FILTER_SCALE_RATIO 0x467d
+#define mmSCLV_VERT_FILTER_INIT 0x467e
+#define mmSCLV_VERT_FILTER_INIT_BOT 0x467f
+#define mmSCLV_VERT_FILTER_SCALE_RATIO_C 0x4680
+#define mmSCLV_VERT_FILTER_INIT_C 0x4681
+#define mmSCLV_VERT_FILTER_INIT_BOT_C 0x4682
+#define mmSCLV_ROUND_OFFSET 0x4683
+#define mmSCLV_UPDATE 0x4684
+#define mmSCLV_ALU_CONTROL 0x4685
+#define mmSCLV_VIEWPORT_START 0x4686
+#define mmSCLV_VIEWPORT_START_SECONDARY 0x4687
+#define mmSCLV_VIEWPORT_SIZE 0x4688
+#define mmSCLV_VIEWPORT_START_C 0x4689
+#define mmSCLV_VIEWPORT_START_SECONDARY_C 0x468a
+#define mmSCLV_VIEWPORT_SIZE_C 0x468b
+#define mmSCLV_EXT_OVERSCAN_LEFT_RIGHT 0x468c
+#define mmSCLV_EXT_OVERSCAN_TOP_BOTTOM 0x468d
+#define mmSCLV_MODE_CHANGE_DET1 0x468e
+#define mmSCLV_MODE_CHANGE_DET2 0x468f
+#define mmSCLV_MODE_CHANGE_DET3 0x4690
+#define mmSCLV_MODE_CHANGE_MASK 0x4691
+#define mmSCLV_DEBUG2 0x4692
+#define mmSCLV_DEBUG 0x4693
+#define mmSCLV_TEST_DEBUG_INDEX 0x4694
+#define mmSCLV_TEST_DEBUG_DATA 0x4695
+#define mmCOL_MAN_UPDATE 0x46a4
+#define mmCOL_MAN_INPUT_CSC_CONTROL 0x46a5
+#define mmINPUT_CSC_C11_C12_A 0x46a6
+#define mmINPUT_CSC_C13_C14_A 0x46a7
+#define mmINPUT_CSC_C21_C22_A 0x46a8
+#define mmINPUT_CSC_C23_C24_A 0x46a9
+#define mmINPUT_CSC_C31_C32_A 0x46aa
+#define mmINPUT_CSC_C33_C34_A 0x46ab
+#define mmINPUT_CSC_C11_C12_B 0x46ac
+#define mmINPUT_CSC_C13_C14_B 0x46ad
+#define mmINPUT_CSC_C21_C22_B 0x46ae
+#define mmINPUT_CSC_C23_C24_B 0x46af
+#define mmINPUT_CSC_C31_C32_B 0x46b0
+#define mmINPUT_CSC_C33_C34_B 0x46b1
+#define mmPRESCALE_CONTROL 0x46b2
+#define mmPRESCALE_VALUES_R 0x46b3
+#define mmPRESCALE_VALUES_G 0x46b4
+#define mmPRESCALE_VALUES_B 0x46b5
+#define mmCOL_MAN_OUTPUT_CSC_CONTROL 0x46b6
+#define mmOUTPUT_CSC_C11_C12_A 0x46b7
+#define mmOUTPUT_CSC_C13_C14_A 0x46b8
+#define mmOUTPUT_CSC_C21_C22_A 0x46b9
+#define mmOUTPUT_CSC_C23_C24_A 0x46ba
+#define mmOUTPUT_CSC_C31_C32_A 0x46bb
+#define mmOUTPUT_CSC_C33_C34_A 0x46bc
+#define mmOUTPUT_CSC_C11_C12_B 0x46bd
+#define mmOUTPUT_CSC_C13_C14_B 0x46be
+#define mmOUTPUT_CSC_C21_C22_B 0x46bf
+#define mmOUTPUT_CSC_C23_C24_B 0x46c0
+#define mmOUTPUT_CSC_C31_C32_B 0x46c1
+#define mmOUTPUT_CSC_C33_C34_B 0x46c2
+#define mmDENORM_CLAMP_CONTROL 0x46c3
+#define mmDENORM_CLAMP_RANGE_R_CR 0x46c4
+#define mmDENORM_CLAMP_RANGE_G_Y 0x46c5
+#define mmDENORM_CLAMP_RANGE_B_CB 0x46c6
+#define mmCOL_MAN_FP_CONVERTED_FIELD 0x46c7
+#define mmGAMMA_CORR_CONTROL 0x46c8
+#define mmGAMMA_CORR_LUT_INDEX 0x46c9
+#define mmGAMMA_CORR_LUT_DATA 0x46ca
+#define mmGAMMA_CORR_LUT_WRITE_EN_MASK 0x46cb
+#define mmGAMMA_CORR_CNTLA_START_CNTL 0x46cc
+#define mmGAMMA_CORR_CNTLA_SLOPE_CNTL 0x46cd
+#define mmGAMMA_CORR_CNTLA_END_CNTL1 0x46ce
+#define mmGAMMA_CORR_CNTLA_END_CNTL2 0x46cf
+#define mmGAMMA_CORR_CNTLA_REGION_0_1 0x46d0
+#define mmGAMMA_CORR_CNTLA_REGION_2_3 0x46d1
+#define mmGAMMA_CORR_CNTLA_REGION_4_5 0x46d2
+#define mmGAMMA_CORR_CNTLA_REGION_6_7 0x46d3
+#define mmGAMMA_CORR_CNTLA_REGION_8_9 0x46d4
+#define mmGAMMA_CORR_CNTLA_REGION_10_11 0x46d5
+#define mmGAMMA_CORR_CNTLA_REGION_12_13 0x46d6
+#define mmGAMMA_CORR_CNTLA_REGION_14_15 0x46d7
+#define mmGAMMA_CORR_CNTLB_START_CNTL 0x46d8
+#define mmGAMMA_CORR_CNTLB_SLOPE_CNTL 0x46d9
+#define mmGAMMA_CORR_CNTLB_END_CNTL1 0x46da
+#define mmGAMMA_CORR_CNTLB_END_CNTL2 0x46db
+#define mmGAMMA_CORR_CNTLB_REGION_0_1 0x46dc
+#define mmGAMMA_CORR_CNTLB_REGION_2_3 0x46dd
+#define mmGAMMA_CORR_CNTLB_REGION_4_5 0x46de
+#define mmGAMMA_CORR_CNTLB_REGION_6_7 0x46df
+#define mmGAMMA_CORR_CNTLB_REGION_8_9 0x46e0
+#define mmGAMMA_CORR_CNTLB_REGION_10_11 0x46e1
+#define mmGAMMA_CORR_CNTLB_REGION_12_13 0x46e2
+#define mmGAMMA_CORR_CNTLB_REGION_14_15 0x46e3
+#define mmCOL_MAN_TEST_DEBUG_INDEX 0x46e4
+#define mmCOL_MAN_TEST_DEBUG_DATA 0x46e5
+#define mmCOL_MAN_DEBUG_CONTROL 0x46e6
+#define mmUNP_GRPH_ENABLE 0x4600
+#define mmUNP_GRPH_CONTROL 0x4601
+#define mmUNP_GRPH_CONTROL_EXP 0x4603
+#define mmUNP_GRPH_SWAP_CNTL 0x4605
+#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x4606
+#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x4607
+#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x4608
+#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x4609
+#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x460a
+#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x460b
+#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x460c
+#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x460d
+#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x460e
+#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x460f
+#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x4610
+#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x4611
+#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x4612
+#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x4613
+#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x4614
+#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x4615
+#define mmUNP_GRPH_PITCH_L 0x4616
+#define mmUNP_GRPH_PITCH_C 0x4617
+#define mmUNP_GRPH_SURFACE_OFFSET_X_L 0x4618
+#define mmUNP_GRPH_SURFACE_OFFSET_X_C 0x4619
+#define mmUNP_GRPH_SURFACE_OFFSET_Y_L 0x461a
+#define mmUNP_GRPH_SURFACE_OFFSET_Y_C 0x461b
+#define mmUNP_GRPH_X_START_L 0x461c
+#define mmUNP_GRPH_X_START_C 0x461d
+#define mmUNP_GRPH_Y_START_L 0x461e
+#define mmUNP_GRPH_Y_START_C 0x461f
+#define mmUNP_GRPH_X_END_L 0x4620
+#define mmUNP_GRPH_X_END_C 0x4621
+#define mmUNP_GRPH_Y_END_L 0x4622
+#define mmUNP_GRPH_Y_END_C 0x4623
+#define mmUNP_GRPH_UPDATE 0x4624
+#define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x4625
+#define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x4626
+#define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x4627
+#define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x4628
+#define mmUNP_GRPH_DFQ_CONTROL 0x4629
+#define mmUNP_GRPH_DFQ_STATUS 0x462a
+#define mmUNP_GRPH_INTERRUPT_STATUS 0x462b
+#define mmUNP_GRPH_INTERRUPT_CONTROL 0x462c
+#define mmUNP_GRPH_STEREOSYNC_FLIP 0x462e
+#define mmUNP_GRPH_FLIP_RATE_CNTL 0x462f
+#define mmUNP_CRC_CONTROL 0x4630
+#define mmUNP_CRC_MASK 0x4631
+#define mmUNP_CRC_CURRENT 0x4632
+#define mmUNP_CRC_LAST 0x4633
+#define mmUNP_LB_DATA_GAP_BETWEEN_CHUNK 0x4634
+#define mmUNP_HW_ROTATION 0x4635
+#define mmUNP_DEBUG 0x4636
+#define mmUNP_DEBUG2 0x4637
+#define mmUNP_TEST_DEBUG_INDEX 0x4638
+#define mmUNP_TEST_DEBUG_DATA 0x4639
+#define mmGENMO_WT 0xf0
+#define mmGENMO_RD 0xf3
+#define mmGENENB 0xf0
+#define mmGENFC_WT 0xee
+#define mmVGA0_GENFC_WT 0xee
+#define mmVGA1_GENFC_WT 0xf6
+#define mmGENFC_RD 0xf2
+#define mmGENS0 0xf0
+#define mmGENS1 0xee
+#define mmVGA0_GENS1 0xee
+#define mmVGA1_GENS1 0xf6
+#define mmDAC_DATA 0xf2
+#define mmDAC_MASK 0xf1
+#define mmDAC_R_INDEX 0xf1
+#define mmDAC_W_INDEX 0xf2
+#define mmSEQ8_IDX 0xf1
+#define mmSEQ8_DATA 0xf1
+#define ixSEQ00 0x0
+#define ixSEQ01 0x1
+#define ixSEQ02 0x2
+#define ixSEQ03 0x3
+#define ixSEQ04 0x4
+#define mmCRTC8_IDX 0xed
+#define mmVGA0_CRTC8_IDX 0xed
+#define mmVGA1_CRTC8_IDX 0xf5
+#define mmCRTC8_DATA 0xed
+#define mmVGA0_CRTC8_DATA 0xed
+#define mmVGA1_CRTC8_DATA 0xf5
+#define ixCRT00 0x0
+#define ixCRT01 0x1
+#define ixCRT02 0x2
+#define ixCRT03 0x3
+#define ixCRT04 0x4
+#define ixCRT05 0x5
+#define ixCRT06 0x6
+#define ixCRT07 0x7
+#define ixCRT08 0x8
+#define ixCRT09 0x9
+#define ixCRT0A 0xa
+#define ixCRT0B 0xb
+#define ixCRT0C 0xc
+#define ixCRT0D 0xd
+#define ixCRT0E 0xe
+#define ixCRT0F 0xf
+#define ixCRT10 0x10
+#define ixCRT11 0x11
+#define ixCRT12 0x12
+#define ixCRT13 0x13
+#define ixCRT14 0x14
+#define ixCRT15 0x15
+#define ixCRT16 0x16
+#define ixCRT17 0x17
+#define ixCRT18 0x18
+#define ixCRT1E 0x1e
+#define ixCRT1F 0x1f
+#define ixCRT22 0x22
+#define mmGRPH8_IDX 0xf3
+#define mmGRPH8_DATA 0xf3
+#define ixGRA00 0x0
+#define ixGRA01 0x1
+#define ixGRA02 0x2
+#define ixGRA03 0x3
+#define ixGRA04 0x4
+#define ixGRA05 0x5
+#define ixGRA06 0x6
+#define ixGRA07 0x7
+#define ixGRA08 0x8
+#define mmATTRX 0xf0
+#define mmATTRDW 0xf0
+#define mmATTRDR 0xf0
+#define ixATTR00 0x0
+#define ixATTR01 0x1
+#define ixATTR02 0x2
+#define ixATTR03 0x3
+#define ixATTR04 0x4
+#define ixATTR05 0x5
+#define ixATTR06 0x6
+#define ixATTR07 0x7
+#define ixATTR08 0x8
+#define ixATTR09 0x9
+#define ixATTR0A 0xa
+#define ixATTR0B 0xb
+#define ixATTR0C 0xc
+#define ixATTR0D 0xd
+#define ixATTR0E 0xe
+#define ixATTR0F 0xf
+#define ixATTR10 0x10
+#define ixATTR11 0x11
+#define ixATTR12 0x12
+#define ixATTR13 0x13
+#define ixATTR14 0x14
+#define mmVGA_RENDER_CONTROL 0xc0
+#define mmVGA_SOURCE_SELECT 0xfc
+#define mmVGA_SEQUENCER_RESET_CONTROL 0xc1
+#define mmVGA_MODE_CONTROL 0xc2
+#define mmVGA_SURFACE_PITCH_SELECT 0xc3
+#define mmVGA_MEMORY_BASE_ADDRESS 0xc4
+#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0xc9
+#define mmVGA_DISPBUF1_SURFACE_ADDR 0xc6
+#define mmVGA_DISPBUF2_SURFACE_ADDR 0xc8
+#define mmVGA_HDP_CONTROL 0xca
+#define mmVGA_CACHE_CONTROL 0xcb
+#define mmD1VGA_CONTROL 0xcc
+#define mmD2VGA_CONTROL 0xce
+#define mmD3VGA_CONTROL 0xf8
+#define mmD4VGA_CONTROL 0xf9
+#define mmD5VGA_CONTROL 0xfa
+#define mmD6VGA_CONTROL 0xfb
+#define mmVGA_HW_DEBUG 0xcf
+#define mmVGA_STATUS 0xd0
+#define mmVGA_INTERRUPT_CONTROL 0xd1
+#define mmVGA_STATUS_CLEAR 0xd2
+#define mmVGA_INTERRUPT_STATUS 0xd3
+#define mmVGA_MAIN_CONTROL 0xd4
+#define mmVGA_TEST_CONTROL 0xd5
+#define mmVGA_DEBUG_READBACK_INDEX 0xd6
+#define mmVGA_DEBUG_READBACK_DATA 0xd7
+#define mmVGA_MEM_WRITE_PAGE_ADDR 0x12
+#define mmVGA_MEM_READ_PAGE_ADDR 0x13
+#define mmVGA_TEST_DEBUG_INDEX 0xc5
+#define mmVGA_TEST_DEBUG_DATA 0xc7
+#define ixVGADCC_DBG_DCCIF_C 0x7e
+#define mmBPHYC_DAC_MACRO_CNTL 0x48b9
+#define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x48ba
+#define mmPLL_REF_DIV 0x1700
+#define mmBPHYC_PLL0_PLL_REF_DIV 0x1700
+#define mmBPHYC_PLL1_PLL_REF_DIV 0x172a
+#define mmBPHYC_PLL2_PLL_REF_DIV 0x1754
+#define mmPLL_FB_DIV 0x1701
+#define mmBPHYC_PLL0_PLL_FB_DIV 0x1701
+#define mmBPHYC_PLL1_PLL_FB_DIV 0x172b
+#define mmBPHYC_PLL2_PLL_FB_DIV 0x1755
+#define mmPLL_POST_DIV 0x1702
+#define mmBPHYC_PLL0_PLL_POST_DIV 0x1702
+#define mmBPHYC_PLL1_PLL_POST_DIV 0x172c
+#define mmBPHYC_PLL2_PLL_POST_DIV 0x1756
+#define mmPLL_SS_AMOUNT_DSFRAC 0x1703
+#define mmBPHYC_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703
+#define mmBPHYC_PLL1_PLL_SS_AMOUNT_DSFRAC 0x172d
+#define mmBPHYC_PLL2_PLL_SS_AMOUNT_DSFRAC 0x1757
+#define mmPLL_SS_CNTL 0x1704
+#define mmBPHYC_PLL0_PLL_SS_CNTL 0x1704
+#define mmBPHYC_PLL1_PLL_SS_CNTL 0x172e
+#define mmBPHYC_PLL2_PLL_SS_CNTL 0x1758
+#define mmPLL_DS_CNTL 0x1705
+#define mmBPHYC_PLL0_PLL_DS_CNTL 0x1705
+#define mmBPHYC_PLL1_PLL_DS_CNTL 0x172f
+#define mmBPHYC_PLL2_PLL_DS_CNTL 0x1759
+#define mmPLL_IDCLK_CNTL 0x1706
+#define mmBPHYC_PLL0_PLL_IDCLK_CNTL 0x1706
+#define mmBPHYC_PLL1_PLL_IDCLK_CNTL 0x1730
+#define mmBPHYC_PLL2_PLL_IDCLK_CNTL 0x175a
+#define mmPLL_CNTL 0x1707
+#define mmBPHYC_PLL0_PLL_CNTL 0x1707
+#define mmBPHYC_PLL1_PLL_CNTL 0x1731
+#define mmBPHYC_PLL2_PLL_CNTL 0x175b
+#define mmPLL_ANALOG 0x1708
+#define mmBPHYC_PLL0_PLL_ANALOG 0x1708
+#define mmBPHYC_PLL1_PLL_ANALOG 0x1732
+#define mmBPHYC_PLL2_PLL_ANALOG 0x175c
+#define mmPLL_VREG_CNTL 0x1709
+#define mmBPHYC_PLL0_PLL_VREG_CNTL 0x1709
+#define mmBPHYC_PLL1_PLL_VREG_CNTL 0x1733
+#define mmBPHYC_PLL2_PLL_VREG_CNTL 0x175d
+#define mmPLL_UNLOCK_DETECT_CNTL 0x170a
+#define mmBPHYC_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170a
+#define mmBPHYC_PLL1_PLL_UNLOCK_DETECT_CNTL 0x1734
+#define mmBPHYC_PLL2_PLL_UNLOCK_DETECT_CNTL 0x175e
+#define mmPLL_DEBUG_CNTL 0x170b
+#define mmBPHYC_PLL0_PLL_DEBUG_CNTL 0x170b
+#define mmBPHYC_PLL1_PLL_DEBUG_CNTL 0x1735
+#define mmBPHYC_PLL2_PLL_DEBUG_CNTL 0x175f
+#define mmPLL_UPDATE_LOCK 0x170c
+#define mmBPHYC_PLL0_PLL_UPDATE_LOCK 0x170c
+#define mmBPHYC_PLL1_PLL_UPDATE_LOCK 0x1736
+#define mmBPHYC_PLL2_PLL_UPDATE_LOCK 0x1760
+#define mmPLL_UPDATE_CNTL 0x170d
+#define mmBPHYC_PLL0_PLL_UPDATE_CNTL 0x170d
+#define mmBPHYC_PLL1_PLL_UPDATE_CNTL 0x1737
+#define mmBPHYC_PLL2_PLL_UPDATE_CNTL 0x1761
+#define mmPLL_XOR_LOCK 0x1710
+#define mmBPHYC_PLL0_PLL_XOR_LOCK 0x1710
+#define mmBPHYC_PLL1_PLL_XOR_LOCK 0x173a
+#define mmBPHYC_PLL2_PLL_XOR_LOCK 0x1764
+#define mmPLL_ANALOG_CNTL 0x1711
+#define mmBPHYC_PLL0_PLL_ANALOG_CNTL 0x1711
+#define mmBPHYC_PLL1_PLL_ANALOG_CNTL 0x173b
+#define mmBPHYC_PLL2_PLL_ANALOG_CNTL 0x1765
+#define mmVGA25_PPLL_REF_DIV 0x1712
+#define mmBPHYC_PLL0_VGA25_PPLL_REF_DIV 0x1712
+#define mmBPHYC_PLL1_VGA25_PPLL_REF_DIV 0x173c
+#define mmBPHYC_PLL2_VGA25_PPLL_REF_DIV 0x1766
+#define mmVGA28_PPLL_REF_DIV 0x1713
+#define mmBPHYC_PLL0_VGA28_PPLL_REF_DIV 0x1713
+#define mmBPHYC_PLL1_VGA28_PPLL_REF_DIV 0x173d
+#define mmBPHYC_PLL2_VGA28_PPLL_REF_DIV 0x1767
+#define mmVGA41_PPLL_REF_DIV 0x1714
+#define mmBPHYC_PLL0_VGA41_PPLL_REF_DIV 0x1714
+#define mmBPHYC_PLL1_VGA41_PPLL_REF_DIV 0x173e
+#define mmBPHYC_PLL2_VGA41_PPLL_REF_DIV 0x1768
+#define mmVGA25_PPLL_FB_DIV 0x1715
+#define mmBPHYC_PLL0_VGA25_PPLL_FB_DIV 0x1715
+#define mmBPHYC_PLL1_VGA25_PPLL_FB_DIV 0x173f
+#define mmBPHYC_PLL2_VGA25_PPLL_FB_DIV 0x1769
+#define mmVGA28_PPLL_FB_DIV 0x1716
+#define mmBPHYC_PLL0_VGA28_PPLL_FB_DIV 0x1716
+#define mmBPHYC_PLL1_VGA28_PPLL_FB_DIV 0x1740
+#define mmBPHYC_PLL2_VGA28_PPLL_FB_DIV 0x176a
+#define mmVGA41_PPLL_FB_DIV 0x1717
+#define mmBPHYC_PLL0_VGA41_PPLL_FB_DIV 0x1717
+#define mmBPHYC_PLL1_VGA41_PPLL_FB_DIV 0x1741
+#define mmBPHYC_PLL2_VGA41_PPLL_FB_DIV 0x176b
+#define mmVGA25_PPLL_POST_DIV 0x1718
+#define mmBPHYC_PLL0_VGA25_PPLL_POST_DIV 0x1718
+#define mmBPHYC_PLL1_VGA25_PPLL_POST_DIV 0x1742
+#define mmBPHYC_PLL2_VGA25_PPLL_POST_DIV 0x176c
+#define mmVGA28_PPLL_POST_DIV 0x1719
+#define mmBPHYC_PLL0_VGA28_PPLL_POST_DIV 0x1719
+#define mmBPHYC_PLL1_VGA28_PPLL_POST_DIV 0x1743
+#define mmBPHYC_PLL2_VGA28_PPLL_POST_DIV 0x176d
+#define mmVGA41_PPLL_POST_DIV 0x171a
+#define mmBPHYC_PLL0_VGA41_PPLL_POST_DIV 0x171a
+#define mmBPHYC_PLL1_VGA41_PPLL_POST_DIV 0x1744
+#define mmBPHYC_PLL2_VGA41_PPLL_POST_DIV 0x176e
+#define mmVGA25_PPLL_ANALOG 0x171b
+#define mmBPHYC_PLL0_VGA25_PPLL_ANALOG 0x171b
+#define mmBPHYC_PLL1_VGA25_PPLL_ANALOG 0x1745
+#define mmBPHYC_PLL2_VGA25_PPLL_ANALOG 0x176f
+#define mmVGA28_PPLL_ANALOG 0x171c
+#define mmBPHYC_PLL0_VGA28_PPLL_ANALOG 0x171c
+#define mmBPHYC_PLL1_VGA28_PPLL_ANALOG 0x1746
+#define mmBPHYC_PLL2_VGA28_PPLL_ANALOG 0x1770
+#define mmVGA41_PPLL_ANALOG 0x171d
+#define mmBPHYC_PLL0_VGA41_PPLL_ANALOG 0x171d
+#define mmBPHYC_PLL1_VGA41_PPLL_ANALOG 0x1747
+#define mmBPHYC_PLL2_VGA41_PPLL_ANALOG 0x1771
+#define mmDISPPLL_BG_CNTL 0x171e
+#define mmBPHYC_PLL0_DISPPLL_BG_CNTL 0x171e
+#define mmBPHYC_PLL1_DISPPLL_BG_CNTL 0x1748
+#define mmBPHYC_PLL2_DISPPLL_BG_CNTL 0x1772
+#define mmPPLL_DIV_UPDATE_DEBUG 0x171f
+#define mmBPHYC_PLL0_PPLL_DIV_UPDATE_DEBUG 0x171f
+#define mmBPHYC_PLL1_PPLL_DIV_UPDATE_DEBUG 0x1749
+#define mmBPHYC_PLL2_PPLL_DIV_UPDATE_DEBUG 0x1773
+#define mmPPLL_STATUS_DEBUG 0x1720
+#define mmBPHYC_PLL0_PPLL_STATUS_DEBUG 0x1720
+#define mmBPHYC_PLL1_PPLL_STATUS_DEBUG 0x174a
+#define mmBPHYC_PLL2_PPLL_STATUS_DEBUG 0x1774
+#define mmPPLL_DEBUG_MUX_CNTL 0x1721
+#define mmBPHYC_PLL0_PPLL_DEBUG_MUX_CNTL 0x1721
+#define mmBPHYC_PLL1_PPLL_DEBUG_MUX_CNTL 0x174b
+#define mmBPHYC_PLL2_PPLL_DEBUG_MUX_CNTL 0x1775
+#define mmPPLL_SPARE0 0x1722
+#define mmBPHYC_PLL0_PPLL_SPARE0 0x1722
+#define mmBPHYC_PLL1_PPLL_SPARE0 0x174c
+#define mmBPHYC_PLL2_PPLL_SPARE0 0x1776
+#define mmPPLL_SPARE1 0x1723
+#define mmBPHYC_PLL0_PPLL_SPARE1 0x1723
+#define mmBPHYC_PLL1_PPLL_SPARE1 0x174d
+#define mmBPHYC_PLL2_PPLL_SPARE1 0x1777
+#define mmUNIPHY_TX_CONTROL1 0x48c0
+#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1 0x48c0
+#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1 0x48e0
+#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1 0x4900
+#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1 0x4920
+#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1 0x4940
+#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1 0x4960
+#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1 0x4980
+#define mmUNIPHY_TX_CONTROL2 0x48c1
+#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2 0x48c1
+#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2 0x48e1
+#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2 0x4901
+#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2 0x4921
+#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2 0x4941
+#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2 0x4961
+#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2 0x4981
+#define mmUNIPHY_TX_CONTROL3 0x48c2
+#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3 0x48c2
+#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3 0x48e2
+#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3 0x4902
+#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3 0x4922
+#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3 0x4942
+#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3 0x4962
+#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3 0x4982
+#define mmUNIPHY_TX_CONTROL4 0x48c3
+#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4 0x48c3
+#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4 0x48e3
+#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4 0x4903
+#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4 0x4923
+#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4 0x4943
+#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4 0x4963
+#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4 0x4983
+#define mmUNIPHY_POWER_CONTROL 0x48c4
+#define mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL 0x48c4
+#define mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL 0x48e4
+#define mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL 0x4904
+#define mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL 0x4924
+#define mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL 0x4944
+#define mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL 0x4964
+#define mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL 0x4984
+#define mmUNIPHY_PLL_FBDIV 0x48c5
+#define mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV 0x48c5
+#define mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV 0x48e5
+#define mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV 0x4905
+#define mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV 0x4925
+#define mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV 0x4945
+#define mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV 0x4965
+#define mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV 0x4985
+#define mmUNIPHY_PLL_CONTROL1 0x48c6
+#define mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1 0x48c6
+#define mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1 0x48e6
+#define mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1 0x4906
+#define mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1 0x4926
+#define mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1 0x4946
+#define mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1 0x4966
+#define mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1 0x4986
+#define mmUNIPHY_PLL_CONTROL2 0x48c7
+#define mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2 0x48c7
+#define mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2 0x48e7
+#define mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2 0x4907
+#define mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2 0x4927
+#define mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2 0x4947
+#define mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2 0x4967
+#define mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2 0x4987
+#define mmUNIPHY_PLL_SS_STEP_SIZE 0x48c8
+#define mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x48c8
+#define mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x48e8
+#define mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x4908
+#define mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x4928
+#define mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x4948
+#define mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x4968
+#define mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE 0x4988
+#define mmUNIPHY_PLL_SS_CNTL 0x48c9
+#define mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x48c9
+#define mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x48e9
+#define mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x4909
+#define mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x4929
+#define mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x4949
+#define mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x4969
+#define mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL 0x4989
+#define mmUNIPHY_DATA_SYNCHRONIZATION 0x48ca
+#define mmBPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x48ca
+#define mmBPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x48ea
+#define mmBPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x490a
+#define mmBPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x492a
+#define mmBPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x494a
+#define mmBPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x496a
+#define mmBPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION 0x498a
+#define mmUNIPHY_REG_TEST_OUTPUT 0x48cb
+#define mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x48cb
+#define mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x48eb
+#define mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x490b
+#define mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x492b
+#define mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x494b
+#define mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x496b
+#define mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT 0x498b
+#define mmUNIPHY_ANG_BIST_CNTL 0x48cc
+#define mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x48cc
+#define mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x48ec
+#define mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x490c
+#define mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x492c
+#define mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x494c
+#define mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x496c
+#define mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL 0x498c
+#define mmUNIPHY_REG_TEST_OUTPUT2 0x48cd
+#define mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 0x48cd
+#define mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 0x48ed
+#define mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 0x490d
+#define mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 0x492d
+#define mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 0x494d
+#define mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 0x496d
+#define mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 0x498d
+#define mmUNIPHY_TMDP_REG0 0x48ce
+#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG0 0x48ce
+#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG0 0x48ee
+#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG0 0x490e
+#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG0 0x492e
+#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG0 0x494e
+#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG0 0x496e
+#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG0 0x498e
+#define mmUNIPHY_TMDP_REG1 0x48cf
+#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG1 0x48cf
+#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG1 0x48ef
+#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG1 0x490f
+#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG1 0x492f
+#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG1 0x494f
+#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG1 0x496f
+#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG1 0x498f
+#define mmUNIPHY_TMDP_REG2 0x48d0
+#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG2 0x48d0
+#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG2 0x48f0
+#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG2 0x4910
+#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG2 0x4930
+#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG2 0x4950
+#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG2 0x4970
+#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG2 0x4990
+#define mmUNIPHY_TMDP_REG3 0x48d1
+#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG3 0x48d1
+#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG3 0x48f1
+#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG3 0x4911
+#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG3 0x4931
+#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG3 0x4951
+#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG3 0x4971
+#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG3 0x4991
+#define mmUNIPHY_TMDP_REG4 0x48d2
+#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG4 0x48d2
+#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG4 0x48f2
+#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG4 0x4912
+#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG4 0x4932
+#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG4 0x4952
+#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG4 0x4972
+#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG4 0x4992
+#define mmUNIPHY_TMDP_REG5 0x48d3
+#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG5 0x48d3
+#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG5 0x48f3
+#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG5 0x4913
+#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG5 0x4933
+#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG5 0x4953
+#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG5 0x4973
+#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG5 0x4993
+#define mmUNIPHY_TMDP_REG6 0x48d4
+#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG6 0x48d4
+#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG6 0x48f4
+#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG6 0x4914
+#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG6 0x4934
+#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG6 0x4954
+#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG6 0x4974
+#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG6 0x4994
+#define mmUNIPHY_TPG_CONTROL 0x48d5
+#define mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL 0x48d5
+#define mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL 0x48f5
+#define mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL 0x4915
+#define mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL 0x4935
+#define mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL 0x4955
+#define mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL 0x4975
+#define mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL 0x4995
+#define mmUNIPHY_TPG_SEED 0x48d6
+#define mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED 0x48d6
+#define mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED 0x48f6
+#define mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED 0x4916
+#define mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED 0x4936
+#define mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED 0x4956
+#define mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED 0x4976
+#define mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED 0x4996
+#define mmUNIPHY_DEBUG 0x48d7
+#define mmBPHYC_UNIPHY0_UNIPHY_DEBUG 0x48d7
+#define mmBPHYC_UNIPHY1_UNIPHY_DEBUG 0x48f7
+#define mmBPHYC_UNIPHY2_UNIPHY_DEBUG 0x4917
+#define mmBPHYC_UNIPHY3_UNIPHY_DEBUG 0x4937
+#define mmBPHYC_UNIPHY4_UNIPHY_DEBUG 0x4957
+#define mmBPHYC_UNIPHY5_UNIPHY_DEBUG 0x4977
+#define mmBPHYC_UNIPHY6_UNIPHY_DEBUG 0x4997
+#define mmDPG_PIPE_ARBITRATION_CONTROL1 0x1b30
+#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1b30
+#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1d30
+#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x1f30
+#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4130
+#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4330
+#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4530
+#define mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL1 0x4730
+#define mmDPG_PIPE_ARBITRATION_CONTROL2 0x1b31
+#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1b31
+#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1d31
+#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x1f31
+#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4131
+#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4331
+#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4531
+#define mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL2 0x4731
+#define mmDPG_WATERMARK_MASK_CONTROL 0x1b32
+#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x1b32
+#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x1d32
+#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x1f32
+#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x4132
+#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x4332
+#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x4532
+#define mmDMIF_PG6_DPG_WATERMARK_MASK_CONTROL 0x4732
+#define mmDPG_PIPE_URGENCY_CONTROL 0x1b33
+#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1b33
+#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1d33
+#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x1f33
+#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4133
+#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4333
+#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4533
+#define mmDMIF_PG6_DPG_PIPE_URGENCY_CONTROL 0x4733
+#define mmDPG_PIPE_DPM_CONTROL 0x1b34
+#define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1b34
+#define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1d34
+#define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x1f34
+#define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4134
+#define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4334
+#define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4534
+#define mmDMIF_PG6_DPG_PIPE_DPM_CONTROL 0x4734
+#define mmDPG_PIPE_STUTTER_CONTROL 0x1b35
+#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1b35
+#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1d35
+#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x1f35
+#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4135
+#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4335
+#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4535
+#define mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL 0x4735
+#define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36
+#define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36
+#define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1d36
+#define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1f36
+#define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136
+#define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4336
+#define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4536
+#define mmDMIF_PG6_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736
+#define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37
+#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37
+#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1d37
+#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1f37
+#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137
+#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4337
+#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4537
+#define mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737
+#define mmDPG_REPEATER_PROGRAM 0x1b3a
+#define mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x1b3a
+#define mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x1d3a
+#define mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x1f3a
+#define mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x413a
+#define mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x433a
+#define mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x453a
+#define mmDMIF_PG6_DPG_REPEATER_PROGRAM 0x473a
+#define mmDPG_HW_DEBUG_A 0x1b3b
+#define mmDMIF_PG0_DPG_HW_DEBUG_A 0x1b3b
+#define mmDMIF_PG1_DPG_HW_DEBUG_A 0x1d3b
+#define mmDMIF_PG2_DPG_HW_DEBUG_A 0x1f3b
+#define mmDMIF_PG3_DPG_HW_DEBUG_A 0x413b
+#define mmDMIF_PG4_DPG_HW_DEBUG_A 0x433b
+#define mmDMIF_PG5_DPG_HW_DEBUG_A 0x453b
+#define mmDMIF_PG6_DPG_HW_DEBUG_A 0x473b
+#define mmDPG_HW_DEBUG_B 0x1b3c
+#define mmDMIF_PG0_DPG_HW_DEBUG_B 0x1b3c
+#define mmDMIF_PG1_DPG_HW_DEBUG_B 0x1d3c
+#define mmDMIF_PG2_DPG_HW_DEBUG_B 0x1f3c
+#define mmDMIF_PG3_DPG_HW_DEBUG_B 0x413c
+#define mmDMIF_PG4_DPG_HW_DEBUG_B 0x433c
+#define mmDMIF_PG5_DPG_HW_DEBUG_B 0x453c
+#define mmDMIF_PG6_DPG_HW_DEBUG_B 0x473c
+#define mmDPG_HW_DEBUG_11 0x1b3d
+#define mmDMIF_PG0_DPG_HW_DEBUG_11 0x1b3d
+#define mmDMIF_PG1_DPG_HW_DEBUG_11 0x1d3d
+#define mmDMIF_PG2_DPG_HW_DEBUG_11 0x1f3d
+#define mmDMIF_PG3_DPG_HW_DEBUG_11 0x413d
+#define mmDMIF_PG4_DPG_HW_DEBUG_11 0x433d
+#define mmDMIF_PG5_DPG_HW_DEBUG_11 0x453d
+#define mmDMIF_PG6_DPG_HW_DEBUG_11 0x473d
+#define mmDPG_TEST_DEBUG_INDEX 0x1b38
+#define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1b38
+#define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1d38
+#define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x1f38
+#define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4138
+#define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4338
+#define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4538
+#define mmDMIF_PG6_DPG_TEST_DEBUG_INDEX 0x4738
+#define mmDPG_TEST_DEBUG_DATA 0x1b39
+#define mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1b39
+#define mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1d39
+#define mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x1f39
+#define mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4139
+#define mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4339
+#define mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4539
+#define mmDMIF_PG6_DPG_TEST_DEBUG_DATA 0x4739
+#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18
+#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0xf00
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0xf02
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0xf04
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x1828
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x1829
+#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x182a
+#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x182b
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x182c
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x182d
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x182e
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x182f
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1830
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x1831
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1832
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1833
+#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x1834
+#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x1835
+#define mmAZALIA_F0_CODEC_DEBUG 0x1836
+#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x1837
+#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x1838
+#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x1839
+#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x183a
+#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x183b
+#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x183c
+#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x183d
+#define mmGLOBAL_CAPABILITIES 0x0
+#define mmMINOR_VERSION 0x0
+#define mmMAJOR_VERSION 0x0
+#define mmOUTPUT_PAYLOAD_CAPABILITY 0x1
+#define mmINPUT_PAYLOAD_CAPABILITY 0x1
+#define mmGLOBAL_CONTROL 0x2
+#define mmWAKE_ENABLE 0x3
+#define mmSTATE_CHANGE_STATUS 0x3
+#define mmGLOBAL_STATUS 0x4
+#define mmOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x6
+#define mmINPUT_STREAM_PAYLOAD_CAPABILITY 0x6
+#define mmINTERRUPT_CONTROL 0x8
+#define mmINTERRUPT_STATUS 0x9
+#define mmWALL_CLOCK_COUNTER 0xc
+#define mmSTREAM_SYNCHRONIZATION 0xe
+#define mmCORB_LOWER_BASE_ADDRESS 0x10
+#define mmCORB_UPPER_BASE_ADDRESS 0x11
+#define mmCORB_WRITE_POINTER 0x12
+#define mmCORB_READ_POINTER 0x12
+#define mmCORB_CONTROL 0x13
+#define mmCORB_STATUS 0x13
+#define mmCORB_SIZE 0x13
+#define mmRIRB_LOWER_BASE_ADDRESS 0x14
+#define mmRIRB_UPPER_BASE_ADDRESS 0x15
+#define mmRIRB_WRITE_POINTER 0x16
+#define mmRESPONSE_INTERRUPT_COUNT 0x16
+#define mmRIRB_CONTROL 0x17
+#define mmRIRB_STATUS 0x17
+#define mmRIRB_SIZE 0x17
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x18
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18
+#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x19
+#define mmIMMEDIATE_COMMAND_STATUS 0x1a
+#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x1c
+#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x1d
+#define mmWALL_CLOCK_COUNTER_ALIAS 0x80c
+#define mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x20
+#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x21
+#define mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x22
+#define mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x23
+#define mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x24
+#define mmOUTPUT_STREAM_DESCRIPTOR_FORMAT 0x24
+#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x26
+#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x27
+#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x821
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e
+#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776
+#define ixAUDIO_DESCRIPTOR0 0x1
+#define ixAUDIO_DESCRIPTOR1 0x2
+#define ixAUDIO_DESCRIPTOR2 0x3
+#define ixAUDIO_DESCRIPTOR3 0x4
+#define ixAUDIO_DESCRIPTOR4 0x5
+#define ixAUDIO_DESCRIPTOR5 0x6
+#define ixAUDIO_DESCRIPTOR6 0x7
+#define ixAUDIO_DESCRIPTOR7 0x8
+#define ixAUDIO_DESCRIPTOR8 0x9
+#define ixAUDIO_DESCRIPTOR9 0xa
+#define ixAUDIO_DESCRIPTOR10 0xb
+#define ixAUDIO_DESCRIPTOR11 0xc
+#define ixAUDIO_DESCRIPTOR12 0xd
+#define ixAUDIO_DESCRIPTOR13 0xe
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x1
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x2
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x3
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x4
+#define ixSINK_DESCRIPTION0 0x5
+#define ixSINK_DESCRIPTION1 0x6
+#define ixSINK_DESCRIPTION2 0x7
+#define ixSINK_DESCRIPTION3 0x8
+#define ixSINK_DESCRIPTION4 0x9
+#define ixSINK_DESCRIPTION5 0xa
+#define ixSINK_DESCRIPTION6 0xb
+#define ixSINK_DESCRIPTION7 0xc
+#define ixSINK_DESCRIPTION8 0xd
+#define ixSINK_DESCRIPTION9 0xe
+#define ixSINK_DESCRIPTION10 0xf
+#define ixSINK_DESCRIPTION11 0x10
+#define ixSINK_DESCRIPTION12 0x11
+#define ixSINK_DESCRIPTION13 0x12
+#define ixSINK_DESCRIPTION14 0x13
+#define ixSINK_DESCRIPTION15 0x14
+#define ixSINK_DESCRIPTION16 0x15
+#define ixSINK_DESCRIPTION17 0x16
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792
+#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e
+#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x17e4
+#define mmAZALIA_AUDIO_DTO 0x17e5
+#define mmAZALIA_AUDIO_DTO_CONTROL 0x17e6
+#define mmAZALIA_SCLK_CONTROL 0x17e7
+#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17e8
+#define mmAZALIA_DATA_DMA_CONTROL 0x17e9
+#define mmAZALIA_BDL_DMA_CONTROL 0x17ea
+#define mmAZALIA_RIRB_AND_DP_CONTROL 0x17eb
+#define mmAZALIA_CORB_DMA_CONTROL 0x17ec
+#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17f3
+#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x17f4
+#define mmAZALIA_GLOBAL_CAPABILITIES 0x17f5
+#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17f6
+#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17f7
+#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x17f8
+#define mmAZALIA_CONTROLLER_DEBUG 0x17f9
+#define mmAZALIA_MEM_PWR_CTRL 0x1810
+#define mmAZALIA_MEM_PWR_STATUS 0x1811
+#define mmDCI_PG_DEBUG_CONFIG 0x1812
+#define mmAZALIA_INPUT_CRC0_CONTROL0 0x17fb
+#define mmAZALIA_INPUT_CRC0_CONTROL1 0x17fc
+#define mmAZALIA_INPUT_CRC0_CONTROL2 0x17fd
+#define mmAZALIA_INPUT_CRC0_CONTROL3 0x17fe
+#define mmAZALIA_INPUT_CRC0_RESULT 0x17ff
+#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0
+#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x1
+#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x2
+#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x3
+#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x4
+#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x5
+#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x6
+#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x7
+#define mmAZALIA_INPUT_CRC1_CONTROL0 0x1800
+#define mmAZALIA_INPUT_CRC1_CONTROL1 0x1801
+#define mmAZALIA_INPUT_CRC1_CONTROL2 0x1802
+#define mmAZALIA_INPUT_CRC1_CONTROL3 0x1803
+#define mmAZALIA_INPUT_CRC1_RESULT 0x1804
+#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0
+#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x1
+#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x2
+#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x3
+#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x4
+#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x5
+#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x6
+#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x7
+#define mmAZALIA_CRC0_CONTROL0 0x1805
+#define mmAZALIA_CRC0_CONTROL1 0x1806
+#define mmAZALIA_CRC0_CONTROL2 0x1807
+#define mmAZALIA_CRC0_CONTROL3 0x1808
+#define mmAZALIA_CRC0_RESULT 0x1809
+#define ixAZALIA_CRC0_CHANNEL0 0x0
+#define ixAZALIA_CRC0_CHANNEL1 0x1
+#define ixAZALIA_CRC0_CHANNEL2 0x2
+#define ixAZALIA_CRC0_CHANNEL3 0x3
+#define ixAZALIA_CRC0_CHANNEL4 0x4
+#define ixAZALIA_CRC0_CHANNEL5 0x5
+#define ixAZALIA_CRC0_CHANNEL6 0x6
+#define ixAZALIA_CRC0_CHANNEL7 0x7
+#define mmAZALIA_CRC1_CONTROL0 0x180a
+#define mmAZALIA_CRC1_CONTROL1 0x180b
+#define mmAZALIA_CRC1_CONTROL2 0x180c
+#define mmAZALIA_CRC1_CONTROL3 0x180d
+#define mmAZALIA_CRC1_RESULT 0x180e
+#define ixAZALIA_CRC1_CHANNEL0 0x0
+#define ixAZALIA_CRC1_CHANNEL1 0x1
+#define ixAZALIA_CRC1_CHANNEL2 0x2
+#define ixAZALIA_CRC1_CHANNEL3 0x3
+#define ixAZALIA_CRC1_CHANNEL4 0x4
+#define ixAZALIA_CRC1_CHANNEL5 0x5
+#define ixAZALIA_CRC1_CHANNEL6 0x6
+#define ixAZALIA_CRC1_CHANNEL7 0x7
+#define mmAZ_TEST_DEBUG_INDEX 0x181f
+#define mmAZ_TEST_DEBUG_DATA 0x1820
+#define mmAZALIA_STREAM_INDEX 0x1780
+#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x1780
+#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x1782
+#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x1784
+#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x1786
+#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x1788
+#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x178a
+#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x178c
+#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x178e
+#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x59c0
+#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x59c2
+#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x59c4
+#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x59c6
+#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x59c8
+#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x59ca
+#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x59cc
+#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x59ce
+#define mmAZALIA_STREAM_DATA 0x1781
+#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x1781
+#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x1783
+#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x1785
+#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x1787
+#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x1789
+#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x178b
+#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x178d
+#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x178f
+#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x59c1
+#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x59c3
+#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x59c5
+#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x59c7
+#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x59c9
+#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x59cb
+#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x59cd
+#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x59cf
+#define ixAZALIA_FIFO_SIZE_CONTROL 0x0
+#define ixAZALIA_LATENCY_COUNTER_CONTROL 0x1
+#define ixAZALIA_WORSTCASE_LATENCY_COUNT 0x2
+#define ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x3
+#define ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x4
+#define ixAZALIA_STREAM_DEBUG 0x5
+#define mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17ac
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b0
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b4
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b8
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17bc
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c0
+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c4
+#define mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17ad
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b1
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b5
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b9
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17bd
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c1
+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c5
+#define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0
+#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1
+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2
+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3
+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4
+#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x5
+#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6
+#define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x7
+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x8
+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x9
+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG 0xa
+#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0xc
+#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0xd
+#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0xe
+#define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20
+#define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x21
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x23
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x24
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2a
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2b
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2c
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2d
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2e
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2f
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x57
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x58
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x59
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x5a
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x5b
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x5c
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x5d
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x5e
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x5f
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x60
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x61
+#define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x62
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x63
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x65
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x67
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x68
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x69
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x6a
+#define ixAZALIA_F0_AUDIO_ENABLE_STATUS 0x6b
+#define ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x6c
+#define ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x6d
+#define ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x6e
+#define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4
+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4
+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d8
+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59dc
+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e0
+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e4
+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e8
+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59ec
+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59f0
+#define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5
+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5
+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d9
+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59dd
+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e1
+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e5
+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e9
+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59ed
+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59f1
+#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0
+#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1
+#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2
+#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3
+#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4
+#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x5
+#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6
+#define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20
+#define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x21
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x23
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x24
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x37
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x38
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x53
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x54
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x67
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x68
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x65
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x18
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x18
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a
+#define mmBLND_CONTROL 0x1b6d
+#define mmBLND0_BLND_CONTROL 0x1b6d
+#define mmBLND1_BLND_CONTROL 0x1d6d
+#define mmBLND2_BLND_CONTROL 0x1f6d
+#define mmBLND3_BLND_CONTROL 0x416d
+#define mmBLND4_BLND_CONTROL 0x436d
+#define mmBLND5_BLND_CONTROL 0x456d
+#define mmBLND6_BLND_CONTROL 0x476d
+#define mmSM_CONTROL2 0x1b6e
+#define mmBLND0_SM_CONTROL2 0x1b6e
+#define mmBLND1_SM_CONTROL2 0x1d6e
+#define mmBLND2_SM_CONTROL2 0x1f6e
+#define mmBLND3_SM_CONTROL2 0x416e
+#define mmBLND4_SM_CONTROL2 0x436e
+#define mmBLND5_SM_CONTROL2 0x456e
+#define mmBLND6_SM_CONTROL2 0x476e
+#define mmBLND_CONTROL2 0x1b6f
+#define mmBLND0_BLND_CONTROL2 0x1b6f
+#define mmBLND1_BLND_CONTROL2 0x1d6f
+#define mmBLND2_BLND_CONTROL2 0x1f6f
+#define mmBLND3_BLND_CONTROL2 0x416f
+#define mmBLND4_BLND_CONTROL2 0x436f
+#define mmBLND5_BLND_CONTROL2 0x456f
+#define mmBLND6_BLND_CONTROL2 0x476f
+#define mmBLND_UPDATE 0x1b70
+#define mmBLND0_BLND_UPDATE 0x1b70
+#define mmBLND1_BLND_UPDATE 0x1d70
+#define mmBLND2_BLND_UPDATE 0x1f70
+#define mmBLND3_BLND_UPDATE 0x4170
+#define mmBLND4_BLND_UPDATE 0x4370
+#define mmBLND5_BLND_UPDATE 0x4570
+#define mmBLND6_BLND_UPDATE 0x4770
+#define mmBLND_UNDERFLOW_INTERRUPT 0x1b71
+#define mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x1b71
+#define mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x1d71
+#define mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x1f71
+#define mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x4171
+#define mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x4371
+#define mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x4571
+#define mmBLND6_BLND_UNDERFLOW_INTERRUPT 0x4771
+#define mmBLND_V_UPDATE_LOCK 0x1b73
+#define mmBLND0_BLND_V_UPDATE_LOCK 0x1b73
+#define mmBLND1_BLND_V_UPDATE_LOCK 0x1d73
+#define mmBLND2_BLND_V_UPDATE_LOCK 0x1f73
+#define mmBLND3_BLND_V_UPDATE_LOCK 0x4173
+#define mmBLND4_BLND_V_UPDATE_LOCK 0x4373
+#define mmBLND5_BLND_V_UPDATE_LOCK 0x4573
+#define mmBLND6_BLND_V_UPDATE_LOCK 0x4773
+#define mmBLND_REG_UPDATE_STATUS 0x1b77
+#define mmBLND0_BLND_REG_UPDATE_STATUS 0x1b77
+#define mmBLND1_BLND_REG_UPDATE_STATUS 0x1d77
+#define mmBLND2_BLND_REG_UPDATE_STATUS 0x1f77
+#define mmBLND3_BLND_REG_UPDATE_STATUS 0x4177
+#define mmBLND4_BLND_REG_UPDATE_STATUS 0x4377
+#define mmBLND5_BLND_REG_UPDATE_STATUS 0x4577
+#define mmBLND6_BLND_REG_UPDATE_STATUS 0x4777
+#define mmBLND_DEBUG 0x1b74
+#define mmBLND0_BLND_DEBUG 0x1b74
+#define mmBLND1_BLND_DEBUG 0x1d74
+#define mmBLND2_BLND_DEBUG 0x1f74
+#define mmBLND3_BLND_DEBUG 0x4174
+#define mmBLND4_BLND_DEBUG 0x4374
+#define mmBLND5_BLND_DEBUG 0x4574
+#define mmBLND6_BLND_DEBUG 0x4774
+#define mmBLND_TEST_DEBUG_INDEX 0x1b75
+#define mmBLND0_BLND_TEST_DEBUG_INDEX 0x1b75
+#define mmBLND1_BLND_TEST_DEBUG_INDEX 0x1d75
+#define mmBLND2_BLND_TEST_DEBUG_INDEX 0x1f75
+#define mmBLND3_BLND_TEST_DEBUG_INDEX 0x4175
+#define mmBLND4_BLND_TEST_DEBUG_INDEX 0x4375
+#define mmBLND5_BLND_TEST_DEBUG_INDEX 0x4575
+#define mmBLND6_BLND_TEST_DEBUG_INDEX 0x4775
+#define mmBLND_TEST_DEBUG_DATA 0x1b76
+#define mmBLND0_BLND_TEST_DEBUG_DATA 0x1b76
+#define mmBLND1_BLND_TEST_DEBUG_DATA 0x1d76
+#define mmBLND2_BLND_TEST_DEBUG_DATA 0x1f76
+#define mmBLND3_BLND_TEST_DEBUG_DATA 0x4176
+#define mmBLND4_BLND_TEST_DEBUG_DATA 0x4376
+#define mmBLND5_BLND_TEST_DEBUG_DATA 0x4576
+#define mmBLND6_BLND_TEST_DEBUG_DATA 0x4776
+#define mmWB_ENABLE 0x5e18
+#define mmWB_EC_CONFIG 0x5e19
+#define mmCNV_MODE 0x5e1a
+#define mmCNV_WINDOW_START 0x5e1b
+#define mmCNV_WINDOW_SIZE 0x5e1c
+#define mmCNV_UPDATE 0x5e1d
+#define mmCNV_SOURCE_SIZE 0x5e1e
+#define mmCNV_CSC_CONTROL 0x5e1f
+#define mmCNV_CSC_C11_C12 0x5e20
+#define mmCNV_CSC_C13_C14 0x5e21
+#define mmCNV_CSC_C21_C22 0x5e22
+#define mmCNV_CSC_C23_C24 0x5e23
+#define mmCNV_CSC_C31_C32 0x5e24
+#define mmCNV_CSC_C33_C34 0x5e25
+#define mmCNV_CSC_ROUND_OFFSET_R 0x5e26
+#define mmCNV_CSC_ROUND_OFFSET_G 0x5e27
+#define mmCNV_CSC_ROUND_OFFSET_B 0x5e28
+#define mmCNV_CSC_CLAMP_R 0x5e29
+#define mmCNV_CSC_CLAMP_G 0x5e2a
+#define mmCNV_CSC_CLAMP_B 0x5e2b
+#define mmCNV_TEST_CNTL 0x5e2c
+#define mmCNV_TEST_CRC_RED 0x5e2d
+#define mmCNV_TEST_CRC_GREEN 0x5e2e
+#define mmCNV_TEST_CRC_BLUE 0x5e2f
+#define mmWB_DEBUG_CTRL 0x5e30
+#define mmWB_DBG_MODE 0x5e31
+#define mmWB_HW_DEBUG 0x5e32
+#define mmCNV_INPUT_SELECT 0x5e33
+#define mmWB_SOFT_RESET 0x5e36
+#define mmCNV_TEST_DEBUG_INDEX 0x5e34
+#define mmCNV_TEST_DEBUG_DATA 0x5e35
+#define mmDCFE_CLOCK_CONTROL 0x1b00
+#define mmDCFE0_DCFE_CLOCK_CONTROL 0x1b00
+#define mmDCFE1_DCFE_CLOCK_CONTROL 0x1d00
+#define mmDCFE2_DCFE_CLOCK_CONTROL 0x1f00
+#define mmDCFE3_DCFE_CLOCK_CONTROL 0x4100
+#define mmDCFE4_DCFE_CLOCK_CONTROL 0x4300
+#define mmDCFE5_DCFE_CLOCK_CONTROL 0x4500
+#define mmDCFE_SOFT_RESET 0x1b01
+#define mmDCFE0_DCFE_SOFT_RESET 0x1b01
+#define mmDCFE1_DCFE_SOFT_RESET 0x1d01
+#define mmDCFE2_DCFE_SOFT_RESET 0x1f01
+#define mmDCFE3_DCFE_SOFT_RESET 0x4101
+#define mmDCFE4_DCFE_SOFT_RESET 0x4301
+#define mmDCFE5_DCFE_SOFT_RESET 0x4501
+#define mmDCFE_DBG_CONFIG 0x1b02
+#define mmDCFE0_DCFE_DBG_CONFIG 0x1b02
+#define mmDCFE1_DCFE_DBG_CONFIG 0x1d02
+#define mmDCFE2_DCFE_DBG_CONFIG 0x1f02
+#define mmDCFE3_DCFE_DBG_CONFIG 0x4102
+#define mmDCFE4_DCFE_DBG_CONFIG 0x4302
+#define mmDCFE5_DCFE_DBG_CONFIG 0x4502
+#define mmDCFEV_CLOCK_CONTROL 0x46f4
+#define mmDCFEV_SOFT_RESET 0x46f5
+#define mmDCFEV_DMIFV_CLOCK_CONTROL 0x46f6
+#define mmDCFEV_DBG_CONFIG 0x46f7
+#define mmDCFEV_DMIFV_MEM_PWR_CTRL 0x46f8
+#define mmDCFEV_DMIFV_MEM_PWR_STATUS 0x46f9
+#define mmDC_HPD_INT_STATUS 0x1898
+#define mmHPD0_DC_HPD_INT_STATUS 0x1898
+#define mmHPD1_DC_HPD_INT_STATUS 0x18a0
+#define mmHPD2_DC_HPD_INT_STATUS 0x18a8
+#define mmHPD3_DC_HPD_INT_STATUS 0x18b0
+#define mmHPD4_DC_HPD_INT_STATUS 0x18b8
+#define mmHPD5_DC_HPD_INT_STATUS 0x18c0
+#define mmDC_HPD_INT_CONTROL 0x1899
+#define mmHPD0_DC_HPD_INT_CONTROL 0x1899
+#define mmHPD1_DC_HPD_INT_CONTROL 0x18a1
+#define mmHPD2_DC_HPD_INT_CONTROL 0x18a9
+#define mmHPD3_DC_HPD_INT_CONTROL 0x18b1
+#define mmHPD4_DC_HPD_INT_CONTROL 0x18b9
+#define mmHPD5_DC_HPD_INT_CONTROL 0x18c1
+#define mmDC_HPD_CONTROL 0x189a
+#define mmHPD0_DC_HPD_CONTROL 0x189a
+#define mmHPD1_DC_HPD_CONTROL 0x18a2
+#define mmHPD2_DC_HPD_CONTROL 0x18aa
+#define mmHPD3_DC_HPD_CONTROL 0x18b2
+#define mmHPD4_DC_HPD_CONTROL 0x18ba
+#define mmHPD5_DC_HPD_CONTROL 0x18c2
+#define mmDC_HPD_FAST_TRAIN_CNTL 0x189b
+#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x189b
+#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x18a3
+#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x18ab
+#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x18b3
+#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x18bb
+#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x18c3
+#define mmDC_HPD_TOGGLE_FILT_CNTL 0x189c
+#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x189c
+#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x18a4
+#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x18ac
+#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x18b4
+#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x18bc
+#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x18c4
+#define mmDCO_SCRATCH0 0x184e
+#define mmDCO_SCRATCH1 0x184f
+#define mmDCO_SCRATCH2 0x1850
+#define mmDCO_SCRATCH3 0x1851
+#define mmDCO_SCRATCH4 0x1852
+#define mmDCO_SCRATCH5 0x1853
+#define mmDCO_SCRATCH6 0x1854
+#define mmDCO_SCRATCH7 0x1855
+#define mmDCE_VCE_CONTROL 0x1856
+#define mmDISP_INTERRUPT_STATUS 0x1857
+#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x1858
+#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x1859
+#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x185a
+#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x185b
+#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x185c
+#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x185d
+#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x185e
+#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x185f
+#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x1860
+#define mmDCO_MEM_PWR_STATUS 0x1861
+#define mmDCO_MEM_PWR_CTRL 0x1862
+#define mmDCO_MEM_PWR_CTRL2 0x1863
+#define mmDCO_CLK_CNTL 0x1864
+#define mmDCO_CLK_RAMP_CNTL 0x1865
+#define mmDPDBG_CNTL 0x1866
+#define mmDPDBG_INTERRUPT 0x1867
+#define mmDCO_POWER_MANAGEMENT_CNTL 0x1868
+#define mmDCO_SOFT_RESET 0x1871
+#define mmDIG_SOFT_RESET 0x1872
+#define mmDCO_STEREOSYNC_SEL 0x186e
+#define mmDCO_TEST_DEBUG_INDEX 0x186f
+#define mmDCO_TEST_DEBUG_DATA 0x1870
+#define mmDC_I2C_CONTROL 0x16d4
+#define mmDC_I2C_ARBITRATION 0x16d5
+#define mmDC_I2C_INTERRUPT_CONTROL 0x16d6
+#define mmDC_I2C_SW_STATUS 0x16d7
+#define mmDC_I2C_DDC1_HW_STATUS 0x16d8
+#define mmDC_I2C_DDC2_HW_STATUS 0x16d9
+#define mmDC_I2C_DDC3_HW_STATUS 0x16da
+#define mmDC_I2C_DDC4_HW_STATUS 0x16db
+#define mmDC_I2C_DDC5_HW_STATUS 0x16dc
+#define mmDC_I2C_DDC6_HW_STATUS 0x16dd
+#define mmDC_I2C_DDC1_SPEED 0x16de
+#define mmDC_I2C_DDC1_SETUP 0x16df
+#define mmDC_I2C_DDC2_SPEED 0x16e0
+#define mmDC_I2C_DDC2_SETUP 0x16e1
+#define mmDC_I2C_DDC3_SPEED 0x16e2
+#define mmDC_I2C_DDC3_SETUP 0x16e3
+#define mmDC_I2C_DDC4_SPEED 0x16e4
+#define mmDC_I2C_DDC4_SETUP 0x16e5
+#define mmDC_I2C_DDC5_SPEED 0x16e6
+#define mmDC_I2C_DDC5_SETUP 0x16e7
+#define mmDC_I2C_DDC6_SPEED 0x16e8
+#define mmDC_I2C_DDC6_SETUP 0x16e9
+#define mmDC_I2C_TRANSACTION0 0x16ea
+#define mmDC_I2C_TRANSACTION1 0x16eb
+#define mmDC_I2C_TRANSACTION2 0x16ec
+#define mmDC_I2C_TRANSACTION3 0x16ed
+#define mmDC_I2C_DATA 0x16ee
+#define mmDC_I2C_DDCVGA_HW_STATUS 0x16ef
+#define mmDC_I2C_DDCVGA_SPEED 0x16f0
+#define mmDC_I2C_DDCVGA_SETUP 0x16f1
+#define mmDC_I2C_EDID_DETECT_CTRL 0x16f2
+#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x16f3
+#define mmGENERIC_I2C_CONTROL 0x16f4
+#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x16f5
+#define mmGENERIC_I2C_STATUS 0x16f6
+#define mmGENERIC_I2C_SPEED 0x16f7
+#define mmGENERIC_I2C_SETUP 0x16f8
+#define mmGENERIC_I2C_TRANSACTION 0x16f9
+#define mmGENERIC_I2C_DATA 0x16fa
+#define mmGENERIC_I2C_PIN_SELECTION 0x16fb
+#define mmGENERIC_I2C_PIN_DEBUG 0x16fc
+#define mmXDMA_MC_PCIE_CLIENT_CONFIG 0x3e0
+#define mmXDMA_LOCAL_SURFACE_TILING1 0x3e1
+#define mmXDMA_LOCAL_SURFACE_TILING2 0x3e2
+#define mmXDMA_INTERRUPT 0x3e3
+#define mmXDMA_CLOCK_GATING_CNTL 0x3e4
+#define mmXDMA_MEM_POWER_CNTL 0x3e6
+#define mmXDMA_IF_BIF_STATUS 0x3e7
+#define mmXDMA_PERF_MEAS_STATUS 0x3e8
+#define mmXDMA_IF_STATUS 0x3e9
+#define mmXDMA_TEST_DEBUG_INDEX 0x3ea
+#define mmXDMA_TEST_DEBUG_DATA 0x3eb
+#define mmXDMA_RBBMIF_RDWR_CNTL 0x3f8
+#define mmXDMA_PG_CONTROL 0x3f9
+#define mmXDMA_PG_WDATA 0x3fa
+#define mmXDMA_PG_STATUS 0x3fb
+#define mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc
+#define mmXDMA_AON_TEST_DEBUG_DATA 0x3fd
+#define mmXDMA_MSTR_CNTL 0x3ec
+#define mmXDMA_MSTR_STATUS 0x3ed
+#define mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x3ee
+#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x3ef
+#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x3f0
+#define mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x3f1
+#define mmXDMA_MSTR_CMD_URGENT_CNTL 0x3f2
+#define mmXDMA_MSTR_MEM_URGENT_CNTL 0x3f3
+#define mmXDMA_MSTR_PCIE_NACK_STATUS 0x3f5
+#define mmXDMA_MSTR_MEM_NACK_STATUS 0x3f6
+#define mmXDMA_MSTR_VSYNC_GSL_CHECK 0x3f7
+#define mmXDMA_MSTR_PIPE_CNTL 0x400
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL 0x400
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL 0x410
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL 0x420
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL 0x430
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL 0x440
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL 0x450
+#define mmXDMA_MSTR_READ_COMMAND 0x401
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND 0x401
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND 0x411
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND 0x421
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND 0x431
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND 0x441
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND 0x451
+#define mmXDMA_MSTR_CHANNEL_DIM 0x402
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM 0x402
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM 0x412
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM 0x422
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM 0x432
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM 0x442
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM 0x452
+#define mmXDMA_MSTR_HEIGHT 0x403
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT 0x403
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT 0x413
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT 0x423
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT 0x433
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT 0x443
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT 0x453
+#define mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x404
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE 0x404
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE 0x414
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE 0x424
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE 0x434
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE 0x444
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE 0x454
+#define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x415
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x425
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x435
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x445
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x455
+#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x406
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x406
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x416
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x426
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x436
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x446
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x456
+#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x417
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x427
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x437
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x447
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x457
+#define mmXDMA_MSTR_CACHE_BASE_ADDR 0x408
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR 0x408
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR 0x418
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR 0x428
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR 0x438
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR 0x448
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR 0x458
+#define mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x419
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x429
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x439
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x449
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x459
+#define mmXDMA_MSTR_CACHE 0x40a
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE 0x40a
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE 0x41a
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE 0x42a
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE 0x43a
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE 0x44a
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE 0x45a
+#define mmXDMA_MSTR_CHANNEL_START 0x40b
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START 0x40b
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START 0x41b
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START 0x42b
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START 0x43b
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START 0x44b
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START 0x45b
+#define mmXDMA_MSTR_PERFMEAS_STATUS 0x40e
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS 0x40e
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS 0x41e
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS 0x42e
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS 0x43e
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS 0x44e
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS 0x45e
+#define mmXDMA_MSTR_PERFMEAS_CNTL 0x40f
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL 0x40f
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL 0x41f
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL 0x42f
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL 0x43f
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL 0x44f
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL 0x45f
+#define mmXDMA_SLV_CNTL 0x460
+#define mmXDMA_SLV_MEM_CLIENT_CONFIG 0x461
+#define mmXDMA_SLV_SLS_PITCH 0x462
+#define mmXDMA_SLV_READ_URGENT_CNTL 0x463
+#define mmXDMA_SLV_WRITE_URGENT_CNTL 0x464
+#define mmXDMA_SLV_WB_RATE_CNTL 0x465
+#define mmXDMA_SLV_READ_LATENCY_MINMAX 0x466
+#define mmXDMA_SLV_READ_LATENCY_AVE 0x467
+#define mmXDMA_SLV_PCIE_NACK_STATUS 0x468
+#define mmXDMA_SLV_MEM_NACK_STATUS 0x469
+#define mmXDMA_SLV_RDRET_BUF_STATUS 0x46a
+#define mmXDMA_SLV_READ_LATENCY_TIMER 0x46b
+#define mmXDMA_SLV_FLIP_PENDING 0x46c
+#define mmXDMA_SLV_CHANNEL_CNTL 0x470
+#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL 0x470
+#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL 0x478
+#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL 0x480
+#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL 0x488
+#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL 0x490
+#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL 0x498
+#define mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x471
+#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS 0x471
+#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS 0x479
+#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS 0x481
+#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS 0x489
+#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS 0x491
+#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS 0x499
+#define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472
+#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472
+#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x47a
+#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x482
+#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x48a
+#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x492
+#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x49a
+
+#endif /* DCE_10_0_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h
new file mode 100644
index 000000000000..061560e1be57
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h
@@ -0,0 +1,1773 @@
+/*
+ * DCE_10_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef DCE_10_0_ENUM_H
+#define DCE_10_0_ENUM_H
+
+typedef enum DCIO_DC_GENERICA_SEL {
+ DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0x0,
+ DCIO_GENERICA_SEL_STEREOSYNC = 0x1,
+ DCIO_GENERICA_SEL_DACA_PIXCLK = 0x2,
+ DCIO_GENERICA_SEL_DACB_PIXCLK = 0x3,
+ DCIO_GENERICA_SEL_DVOA_CTL3 = 0x4,
+ DCIO_GENERICA_SEL_P1_PLLCLK = 0x5,
+ DCIO_GENERICA_SEL_P2_PLLCLK = 0x6,
+ DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 0x7,
+ DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 0x8,
+ DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 0x9,
+ DCIO_GENERICA_SEL_GENERICA_DCCG = 0xa,
+ DCIO_GENERICA_SEL_SYNCEN = 0xb,
+ DCIO_GENERICA_SEL_GENERICA_SCG = 0xc,
+ DCIO_GENERICA_SEL_RESERVED_VALUE13 = 0xd,
+ DCIO_GENERICA_SEL_RESERVED_VALUE14 = 0xe,
+ DCIO_GENERICA_SEL_RESERVED_VALUE15 = 0xf,
+ DCIO_GENERICA_SEL_GENERICA_DPRX = 0x10,
+ DCIO_GENERICA_SEL_GENERICB_DPRX = 0x11,
+} DCIO_DC_GENERICA_SEL;
+typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
+ DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x0,
+ DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x1,
+ DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x2,
+ DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x3,
+ DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x4,
+ DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x5,
+} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
+typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
+ DCIO_UNIPHYA_FBDIV_CLK = 0x0,
+ DCIO_UNIPHYB_FBDIV_CLK = 0x1,
+ DCIO_UNIPHYC_FBDIV_CLK = 0x2,
+ DCIO_UNIPHYD_FBDIV_CLK = 0x3,
+ DCIO_UNIPHYE_FBDIV_CLK = 0x4,
+ DCIO_UNIPHYF_FBDIV_CLK = 0x5,
+} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
+typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
+ DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x0,
+ DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x1,
+ DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x2,
+ DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x3,
+ DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x4,
+ DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x5,
+} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
+typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
+ DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x0,
+ DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x1,
+ DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x2,
+ DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x3,
+ DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x4,
+ DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x5,
+} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
+typedef enum DCIO_DC_GENERICB_SEL {
+ DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0x0,
+ DCIO_GENERICB_SEL_STEREOSYNC = 0x1,
+ DCIO_GENERICB_SEL_DACA_PIXCLK = 0x2,
+ DCIO_GENERICB_SEL_DACB_PIXCLK = 0x3,
+ DCIO_GENERICB_SEL_DVOA_CTL3 = 0x4,
+ DCIO_GENERICB_SEL_P1_PLLCLK = 0x5,
+ DCIO_GENERICB_SEL_P2_PLLCLK = 0x6,
+ DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 0x7,
+ DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 0x8,
+ DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 0x9,
+ DCIO_GENERICB_SEL_GENERICB_DCCG = 0xa,
+ DCIO_GENERICB_SEL_SYNCEN = 0xb,
+ DCIO_GENERICB_SEL_GENERICA_SCG = 0xc,
+ DCIO_GENERICB_SEL_RESERVED_VALUE13 = 0xd,
+ DCIO_GENERICB_SEL_RESERVED_VALUE14 = 0xe,
+ DCIO_GENERICB_SEL_RESERVED_VALUE15 = 0xf,
+} DCIO_DC_GENERICB_SEL;
+typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL {
+ DCIO_DC_PAD_EXTERN_SIG_SEL_MVP = 0x0,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA = 0x1,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK = 0x2,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC = 0x3,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA = 0x4,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB = 0x5,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC = 0x6,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1 = 0x7,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2 = 0x8,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK = 0x9,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA = 0xa,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK = 0xb,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA = 0xc,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1 = 0xd,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0 = 0xe,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL = 0xf,
+} DCIO_DC_PAD_EXTERN_SIG_SEL;
+typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS {
+ DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA = 0x0,
+ DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE = 0x1,
+ DCIO_MVP_PIXEL_SRC_STATUS_CRTC = 0x2,
+ DCIO_MVP_PIXEL_SRC_STATUS_LB = 0x3,
+} DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS;
+typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
+ DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0x0,
+ DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 0x1,
+ DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x2,
+ DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 0x3,
+} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;
+typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
+ DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x0,
+ DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x1,
+ DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x2,
+ DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x3,
+} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
+typedef enum DCIO_DC_GPIO_VIP_DEBUG {
+ DCIO_DC_GPIO_VIP_DEBUG_NORMAL = 0x0,
+ DCIO_DC_GPIO_VIP_DEBUG_CG_BIG = 0x1,
+} DCIO_DC_GPIO_VIP_DEBUG;
+typedef enum DCIO_DC_GPIO_MACRO_DEBUG {
+ DCIO_DC_GPIO_MACRO_DEBUG_NORMAL = 0x0,
+ DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF = 0x1,
+ DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 0x2,
+ DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3 = 0x3,
+} DCIO_DC_GPIO_MACRO_DEBUG;
+typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL {
+ DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL = 0x0,
+ DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP = 0x1,
+} DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL;
+typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN {
+ DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS = 0x0,
+ DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE = 0x1,
+} DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN;
+typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
+ DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0x0,
+ DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 0x1,
+} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE;
+typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
+ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x0,
+ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x1,
+ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS= 0x2,
+ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS= 0x3,
+ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS= 0x4,
+ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS= 0x5,
+ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS= 0x6,
+ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS= 0x7,
+} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION;
+typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
+ DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x0,
+ DCIO_UNIPHY_CHANNEL_INVERTED = 0x1,
+} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
+typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
+ DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x0,
+ DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x1,
+ DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x2,
+ DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED= 0x3,
+} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
+typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
+ DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x0,
+ DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x1,
+ DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x2,
+ DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x3,
+} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
+typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
+ DCIO_VIP_MUX_EN_DVO = 0x0,
+ DCIO_VIP_MUX_EN_VIP = 0x1,
+} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN;
+typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
+ DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0x0,
+ DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 0x1,
+} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN;
+typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
+ DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0x0,
+ DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 0x1,
+} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN;
+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
+ DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE= 0x0,
+ DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE= 0x1,
+} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN;
+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
+ DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0x0,
+ DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 0x1,
+} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE;
+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
+ DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0x0,
+ DCIO_LVTMA_SYNCEN_POL_INVERT = 0x1,
+} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL;
+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
+ DCIO_LVTMA_DIGON_OFF = 0x0,
+ DCIO_LVTMA_DIGON_ON = 0x1,
+} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON;
+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
+ DCIO_LVTMA_DIGON_POL_NON_INVERT = 0x0,
+ DCIO_LVTMA_DIGON_POL_INVERT = 0x1,
+} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL;
+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
+ DCIO_LVTMA_BLON_OFF = 0x0,
+ DCIO_LVTMA_BLON_ON = 0x1,
+} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON;
+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
+ DCIO_LVTMA_BLON_POL_NON_INVERT = 0x0,
+ DCIO_LVTMA_BLON_POL_INVERT = 0x1,
+} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL;
+typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
+ DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0x0,
+ DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 0x1,
+} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN;
+typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
+ DCIO_BL_PWM_FRACTIONAL_DISABLE = 0x0,
+ DCIO_BL_PWM_FRACTIONAL_ENABLE = 0x1,
+} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
+typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
+ DCIO_BL_PWM_DISABLE = 0x0,
+ DCIO_BL_PWM_ENABLE = 0x1,
+} DCIO_BL_PWM_CNTL_BL_PWM_EN;
+typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
+ DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x0,
+ DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x1,
+ DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x2,
+ DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x3,
+} DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT;
+typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
+ DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x0,
+ DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x1,
+} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
+typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
+ DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0x0,
+ DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 0x1,
+} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN;
+typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
+ DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x0,
+ DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x1,
+} DCIO_BL_PWM_GRP1_REG_LOCK;
+typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
+ DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x0,
+ DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x1,
+} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
+typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
+ DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1= 0x0,
+ DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2= 0x1,
+ DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3= 0x2,
+ DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4= 0x3,
+ DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5= 0x4,
+ DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6= 0x5,
+} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
+typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
+ DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x0,
+ DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM= 0x1,
+} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
+typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
+ DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x0,
+ DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x1,
+} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
+typedef enum DCIO_GSL_SEL {
+ DCIO_GSL_SEL_GROUP_0 = 0x0,
+ DCIO_GSL_SEL_GROUP_1 = 0x1,
+ DCIO_GSL_SEL_GROUP_2 = 0x2,
+} DCIO_GSL_SEL;
+typedef enum DCIO_GENLK_CLK_GSL_MASK {
+ DCIO_GENLK_CLK_GSL_MASK_NO = 0x0,
+ DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x1,
+ DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x2,
+} DCIO_GENLK_CLK_GSL_MASK;
+typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
+ DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x0,
+ DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x1,
+ DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x2,
+} DCIO_GENLK_VSYNC_GSL_MASK;
+typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
+ DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x0,
+ DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x1,
+ DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x2,
+} DCIO_SWAPLOCK_A_GSL_MASK;
+typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
+ DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x0,
+ DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x1,
+ DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x2,
+} DCIO_SWAPLOCK_B_GSL_MASK;
+typedef enum DCIO_GSL_VSYNC_SEL {
+ DCIO_GSL_VSYNC_SEL_PIPE0 = 0x0,
+ DCIO_GSL_VSYNC_SEL_PIPE1 = 0x1,
+ DCIO_GSL_VSYNC_SEL_PIPE2 = 0x2,
+ DCIO_GSL_VSYNC_SEL_PIPE3 = 0x3,
+ DCIO_GSL_VSYNC_SEL_PIPE4 = 0x4,
+ DCIO_GSL_VSYNC_SEL_PIPE5 = 0x5,
+} DCIO_GSL_VSYNC_SEL;
+typedef enum DCIO_GSL0_TIMING_SYNC_SEL {
+ DCIO_GSL0_TIMING_SYNC_SEL_PIPE = 0x0,
+ DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1,
+ DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
+ DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3,
+ DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4,
+} DCIO_GSL0_TIMING_SYNC_SEL;
+typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL {
+ DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION = 0x0,
+ DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1,
+ DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
+ DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3,
+ DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4,
+} DCIO_GSL0_GLOBAL_UNLOCK_SEL;
+typedef enum DCIO_GSL1_TIMING_SYNC_SEL {
+ DCIO_GSL1_TIMING_SYNC_SEL_PIPE = 0x0,
+ DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1,
+ DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
+ DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3,
+ DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4,
+} DCIO_GSL1_TIMING_SYNC_SEL;
+typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL {
+ DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION = 0x0,
+ DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1,
+ DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
+ DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3,
+ DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4,
+} DCIO_GSL1_GLOBAL_UNLOCK_SEL;
+typedef enum DCIO_GSL2_TIMING_SYNC_SEL {
+ DCIO_GSL2_TIMING_SYNC_SEL_PIPE = 0x0,
+ DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1,
+ DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
+ DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3,
+ DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4,
+} DCIO_GSL2_TIMING_SYNC_SEL;
+typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL {
+ DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION = 0x0,
+ DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1,
+ DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
+ DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3,
+ DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4,
+} DCIO_GSL2_GLOBAL_UNLOCK_SEL;
+typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
+ DCIO_GPU_TIMER_START_0_END_27 = 0x0,
+ DCIO_GPU_TIMER_START_1_END_28 = 0x1,
+ DCIO_GPU_TIMER_START_2_END_29 = 0x2,
+ DCIO_GPU_TIMER_START_3_END_30 = 0x3,
+ DCIO_GPU_TIMER_START_4_END_31 = 0x4,
+ DCIO_GPU_TIMER_START_6_END_33 = 0x5,
+ DCIO_GPU_TIMER_START_8_END_35 = 0x6,
+ DCIO_GPU_TIMER_START_10_END_37 = 0x7,
+} DCIO_DC_GPU_TIMER_START_POSITION;
+typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
+ DCIO_TEST_CLK_SEL_DISPCLK = 0x0,
+ DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x1,
+ DCIO_TEST_CLK_SEL_SCLK = 0x2,
+} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
+typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
+ DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x0,
+ DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x1,
+} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
+typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_RAMP_DIS {
+ DCIO_DISPCLK_R_DCIO_RAMP_DISABLE = 0x0,
+ DCIO_DISPCLK_R_DCIO_RAMP_ENABLE = 0x1,
+} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_RAMP_DIS;
+typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX {
+ DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x0,
+ DCIO_EXT_VSYNC_MUX_CRTC0 = 0x1,
+ DCIO_EXT_VSYNC_MUX_CRTC1 = 0x2,
+ DCIO_EXT_VSYNC_MUX_CRTC2 = 0x3,
+ DCIO_EXT_VSYNC_MUX_CRTC3 = 0x4,
+ DCIO_EXT_VSYNC_MUX_CRTC4 = 0x5,
+ DCIO_EXT_VSYNC_MUX_CRTC5 = 0x6,
+ DCIO_EXT_VSYNC_MUX_GENERICB = 0x7,
+} DCIO_DCO_DCFE_EXT_VSYNC_MUX;
+typedef enum DCIO_DCO_EXT_VSYNC_MASK {
+ DCIO_EXT_VSYNC_MASK_NONE = 0x0,
+ DCIO_EXT_VSYNC_MASK_PIPE0 = 0x1,
+ DCIO_EXT_VSYNC_MASK_PIPE1 = 0x2,
+ DCIO_EXT_VSYNC_MASK_PIPE2 = 0x3,
+ DCIO_EXT_VSYNC_MASK_PIPE3 = 0x4,
+ DCIO_EXT_VSYNC_MASK_PIPE4 = 0x5,
+ DCIO_EXT_VSYNC_MASK_PIPE5 = 0x6,
+ DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x7,
+} DCIO_DCO_EXT_VSYNC_MASK;
+typedef enum DCIO_DBG_OUT_PIN_SEL {
+ DCIO_DBG_OUT_PIN_SEL_LOW_12BIT = 0x0,
+ DCIO_DBG_OUT_PIN_SEL_HIGH_12BIT = 0x1,
+} DCIO_DBG_OUT_PIN_SEL;
+typedef enum DCIO_DBG_OUT_12BIT_SEL {
+ DCIO_DBG_OUT_12BIT_SEL_LOW_12BIT = 0x0,
+ DCIO_DBG_OUT_12BIT_SEL_MID_12BIT = 0x1,
+ DCIO_DBG_OUT_12BIT_SEL_HIGH_12BIT = 0x2,
+ DCIO_DBG_OUT_12BIT_SEL_OVERRIDE = 0x3,
+} DCIO_DBG_OUT_12BIT_SEL;
+typedef enum DCIO_DSYNC_SOFT_RESET {
+ DCIO_DSYNC_SOFT_RESET_DEASSERT = 0x0,
+ DCIO_DSYNC_SOFT_RESET_ASSERT = 0x1,
+} DCIO_DSYNC_SOFT_RESET;
+typedef enum DCIO_DACA_SOFT_RESET {
+ DCIO_DACA_SOFT_RESET_DEASSERT = 0x0,
+ DCIO_DACA_SOFT_RESET_ASSERT = 0x1,
+} DCIO_DACA_SOFT_RESET;
+typedef enum DCIO_DCRXPHY_SOFT_RESET {
+ DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x0,
+ DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x1,
+} DCIO_DCRXPHY_SOFT_RESET;
+typedef enum DCIO_DPHY_LANE_SEL {
+ DCIO_DPHY_LANE_SEL_LANE0 = 0x0,
+ DCIO_DPHY_LANE_SEL_LANE1 = 0x1,
+ DCIO_DPHY_LANE_SEL_LANE2 = 0x2,
+ DCIO_DPHY_LANE_SEL_LANE3 = 0x3,
+} DCIO_DPHY_LANE_SEL;
+typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x0,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x1,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 0x2,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE = 0x3,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 0x4,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE = 0x5,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE = 0x6,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE = 0x7,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE = 0x8,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE = 0x9,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE = 0xa,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE = 0xb,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0xc,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0xd,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP = 0xe,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP = 0xf,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP = 0x10,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP = 0x11,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP = 0x12,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP = 0x13,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP = 0x14,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP = 0x15,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP = 0x16,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP = 0x17,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x18,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x19,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM = 0x1a,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM = 0x1b,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM = 0x1c,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM = 0x1d,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM = 0x1e,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM = 0x1f,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM = 0x20,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM = 0x21,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM = 0x22,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM = 0x23,
+} DCIO_DC_GPU_TIMER_READ_SELECT;
+typedef enum DCIO_IMPCAL_STEP_DELAY {
+ DCIO_IMPCAL_STEP_DELAY_1us = 0x0,
+ DCIO_IMPCAL_STEP_DELAY_2us = 0x1,
+ DCIO_IMPCAL_STEP_DELAY_3us = 0x2,
+ DCIO_IMPCAL_STEP_DELAY_4us = 0x3,
+ DCIO_IMPCAL_STEP_DELAY_5us = 0x4,
+ DCIO_IMPCAL_STEP_DELAY_6us = 0x5,
+ DCIO_IMPCAL_STEP_DELAY_7us = 0x6,
+ DCIO_IMPCAL_STEP_DELAY_8us = 0x7,
+ DCIO_IMPCAL_STEP_DELAY_9us = 0x8,
+ DCIO_IMPCAL_STEP_DELAY_10us = 0x9,
+ DCIO_IMPCAL_STEP_DELAY_11us = 0xa,
+ DCIO_IMPCAL_STEP_DELAY_12us = 0xb,
+ DCIO_IMPCAL_STEP_DELAY_13us = 0xc,
+ DCIO_IMPCAL_STEP_DELAY_14us = 0xd,
+ DCIO_IMPCAL_STEP_DELAY_15us = 0xe,
+ DCIO_IMPCAL_STEP_DELAY_16us = 0xf,
+} DCIO_IMPCAL_STEP_DELAY;
+typedef enum DCIO_UNIPHY_IMPCAL_SEL {
+ DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x0,
+ DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x1,
+} DCIO_UNIPHY_IMPCAL_SEL;
+typedef enum DCIOCHIP_HPD_SEL {
+ DCIOCHIP_HPD_SEL_ASYNC = 0x0,
+ DCIOCHIP_HPD_SEL_CLOCKED = 0x1,
+} DCIOCHIP_HPD_SEL;
+typedef enum DCIOCHIP_PAD_MODE {
+ DCIOCHIP_PAD_MODE_DDC = 0x0,
+ DCIOCHIP_PAD_MODE_DP = 0x1,
+} DCIOCHIP_PAD_MODE;
+typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
+ DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0x0,
+ DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 0x1,
+} DCIOCHIP_AUXSLAVE_PAD_MODE;
+typedef enum DCIOCHIP_INVERT {
+ DCIOCHIP_POL_NON_INVERT = 0x0,
+ DCIOCHIP_POL_INVERT = 0x1,
+} DCIOCHIP_INVERT;
+typedef enum DCIOCHIP_PD_EN {
+ DCIOCHIP_PD_EN_NOTALLOW = 0x0,
+ DCIOCHIP_PD_EN_ALLOW = 0x1,
+} DCIOCHIP_PD_EN;
+typedef enum DCIOCHIP_GPIO_MASK_EN {
+ DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x0,
+ DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x1,
+} DCIOCHIP_GPIO_MASK_EN;
+typedef enum DCIOCHIP_MASK {
+ DCIOCHIP_MASK_DISABLE = 0x0,
+ DCIOCHIP_MASK_ENABLE = 0x1,
+} DCIOCHIP_MASK;
+typedef enum DCIOCHIP_GPIO_I2C_MASK {
+ DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0x0,
+ DCIOCHIP_GPIO_I2C_MASK_ENABLE = 0x1,
+} DCIOCHIP_GPIO_I2C_MASK;
+typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
+ DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0x0,
+ DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 0x1,
+} DCIOCHIP_GPIO_I2C_DRIVE;
+typedef enum DCIOCHIP_GPIO_I2C_EN {
+ DCIOCHIP_GPIO_I2C_DISABLE = 0x0,
+ DCIOCHIP_GPIO_I2C_ENABLE = 0x1,
+} DCIOCHIP_GPIO_I2C_EN;
+typedef enum DCIOCHIP_MASK_4BIT {
+ DCIOCHIP_MASK_4BIT_DISABLE = 0x0,
+ DCIOCHIP_MASK_4BIT_ENABLE = 0xf,
+} DCIOCHIP_MASK_4BIT;
+typedef enum DCIOCHIP_ENABLE_4BIT {
+ DCIOCHIP_4BIT_DISABLE = 0x0,
+ DCIOCHIP_4BIT_ENABLE = 0xf,
+} DCIOCHIP_ENABLE_4BIT;
+typedef enum DCIOCHIP_MASK_5BIT {
+ DCIOCHIP_MASIK_5BIT_DISABLE = 0x0,
+ DCIOCHIP_MASIK_5BIT_ENABLE = 0x1f,
+} DCIOCHIP_MASK_5BIT;
+typedef enum DCIOCHIP_ENABLE_5BIT {
+ DCIOCHIP_5BIT_DISABLE = 0x0,
+ DCIOCHIP_5BIT_ENABLE = 0x1f,
+} DCIOCHIP_ENABLE_5BIT;
+typedef enum DCIOCHIP_MASK_2BIT {
+ DCIOCHIP_MASK_2BIT_DISABLE = 0x0,
+ DCIOCHIP_MASK_2BIT_ENABLE = 0x3,
+} DCIOCHIP_MASK_2BIT;
+typedef enum DCIOCHIP_ENABLE_2BIT {
+ DCIOCHIP_2BIT_DISABLE = 0x0,
+ DCIOCHIP_2BIT_ENABLE = 0x3,
+} DCIOCHIP_ENABLE_2BIT;
+typedef enum DCIOCHIP_REF_27_SRC_SEL {
+ DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x0,
+ DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x1,
+ DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x2,
+ DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x3,
+} DCIOCHIP_REF_27_SRC_SEL;
+typedef enum DCIOCHIP_DVO_VREFPON {
+ DCIOCHIP_DVO_VREFPON_DISABLE = 0x0,
+ DCIOCHIP_DVO_VREFPON_ENABLE = 0x1,
+} DCIOCHIP_DVO_VREFPON;
+typedef enum DCIOCHIP_DVO_VREFSEL {
+ DCIOCHIP_DVO_VREFSEL_ONCHIP = 0x0,
+ DCIOCHIP_DVO_VREFSEL_EXTERNAL = 0x1,
+} DCIOCHIP_DVO_VREFSEL;
+typedef enum COL_MAN_UPDATE_LOCK {
+ COL_MAN_UPDATE_UNLOCKED = 0x0,
+ COL_MAN_UPDATE_LOCKED = 0x1,
+} COL_MAN_UPDATE_LOCK;
+typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE {
+ COL_MAN_MULTIPLE_UPDATE = 0x0,
+ COL_MAN_MULTIPLE_UPDAT_EDISABLE = 0x1,
+} COL_MAN_DISABLE_MULTIPLE_UPDATE;
+typedef enum COL_MAN_INPUTCSC_MODE {
+ INPUTCSC_MODE_BYPASS = 0x0,
+ INPUTCSC_MODE_A = 0x1,
+ INPUTCSC_MODE_B = 0x2,
+ INPUTCSC_MODE_UNITY = 0x3,
+} COL_MAN_INPUTCSC_MODE;
+typedef enum COL_MAN_INPUTCSC_TYPE {
+ INPUTCSC_TYPE_12_0 = 0x0,
+ INPUTCSC_TYPE_10_2 = 0x1,
+ INPUTCSC_TYPE_8_4 = 0x2,
+} COL_MAN_INPUTCSC_TYPE;
+typedef enum COL_MAN_INPUTCSC_CONVERT {
+ INPUTCSC_ROUND = 0x0,
+ INPUTCSC_TRUNCATE = 0x1,
+} COL_MAN_INPUTCSC_CONVERT;
+typedef enum COL_MAN_PRESCALE_MODE {
+ PRESCALE_MODE_BYPASS = 0x0,
+ PRESCALE_MODE_PROGRAM = 0x1,
+ PRESCALE_MODE_UNITY = 0x2,
+} COL_MAN_PRESCALE_MODE;
+typedef enum COL_MAN_OUTPUT_CSC_MODE {
+ COL_MAN_OUTPUT_CSC_BYPASS = 0x0,
+ COL_MAN_OUTPUT_CSC_RGB = 0x1,
+ COL_MAN_OUTPUT_CSC_YCrCb601 = 0x2,
+ COL_MAN_OUTPUT_CSC_YCrCb709 = 0x3,
+ COL_MAN_OUTPUT_CSC_A = 0x4,
+ COL_MAN_OUTPUT_CSC_B = 0x5,
+} COL_MAN_OUTPUT_CSC_MODE;
+typedef enum COL_MAN_DENORM_CLAMP_CONTROL {
+ DENORM_CLAMP_CONTROL_UNITY = 0x0,
+ DENORM_CLAMP_CONTROL_8 = 0x1,
+ DENORM_CLAMP_CONTROL_10 = 0x2,
+ DENORM_CLAMP_CONTROL_12 = 0x3,
+} COL_MAN_DENORM_CLAMP_CONTROL;
+typedef enum COL_MAN_GAMMA_CORR_CONTROL {
+ GAMMA_CORR_CONTROL_BYPASS = 0x0,
+ GAMMA_CORR_CONTROL_A = 0x1,
+ GAMMA_CORR_CONTROL_B = 0x2,
+} COL_MAN_GAMMA_CORR_CONTROL;
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0x0,
+ ENDIAN_8IN16 = 0x1,
+ ENDIAN_8IN32 = 0x2,
+ ENDIAN_8IN64 = 0x3,
+} SurfaceEndian;
+typedef enum ArrayMode {
+ ARRAY_LINEAR_GENERAL = 0x0,
+ ARRAY_LINEAR_ALIGNED = 0x1,
+ ARRAY_1D_TILED_THIN1 = 0x2,
+ ARRAY_1D_TILED_THICK = 0x3,
+ ARRAY_2D_TILED_THIN1 = 0x4,
+ ARRAY_PRT_TILED_THIN1 = 0x5,
+ ARRAY_PRT_2D_TILED_THIN1 = 0x6,
+ ARRAY_2D_TILED_THICK = 0x7,
+ ARRAY_2D_TILED_XTHICK = 0x8,
+ ARRAY_PRT_TILED_THICK = 0x9,
+ ARRAY_PRT_2D_TILED_THICK = 0xa,
+ ARRAY_PRT_3D_TILED_THIN1 = 0xb,
+ ARRAY_3D_TILED_THIN1 = 0xc,
+ ARRAY_3D_TILED_THICK = 0xd,
+ ARRAY_3D_TILED_XTHICK = 0xe,
+ ARRAY_PRT_3D_TILED_THICK = 0xf,
+} ArrayMode;
+typedef enum PipeTiling {
+ CONFIG_1_PIPE = 0x0,
+ CONFIG_2_PIPE = 0x1,
+ CONFIG_4_PIPE = 0x2,
+ CONFIG_8_PIPE = 0x3,
+} PipeTiling;
+typedef enum BankTiling {
+ CONFIG_4_BANK = 0x0,
+ CONFIG_8_BANK = 0x1,
+} BankTiling;
+typedef enum GroupInterleave {
+ CONFIG_256B_GROUP = 0x0,
+ CONFIG_512B_GROUP = 0x1,
+} GroupInterleave;
+typedef enum RowTiling {
+ CONFIG_1KB_ROW = 0x0,
+ CONFIG_2KB_ROW = 0x1,
+ CONFIG_4KB_ROW = 0x2,
+ CONFIG_8KB_ROW = 0x3,
+ CONFIG_1KB_ROW_OPT = 0x4,
+ CONFIG_2KB_ROW_OPT = 0x5,
+ CONFIG_4KB_ROW_OPT = 0x6,
+ CONFIG_8KB_ROW_OPT = 0x7,
+} RowTiling;
+typedef enum BankSwapBytes {
+ CONFIG_128B_SWAPS = 0x0,
+ CONFIG_256B_SWAPS = 0x1,
+ CONFIG_512B_SWAPS = 0x2,
+ CONFIG_1KB_SWAPS = 0x3,
+} BankSwapBytes;
+typedef enum SampleSplitBytes {
+ CONFIG_1KB_SPLIT = 0x0,
+ CONFIG_2KB_SPLIT = 0x1,
+ CONFIG_4KB_SPLIT = 0x2,
+ CONFIG_8KB_SPLIT = 0x3,
+} SampleSplitBytes;
+typedef enum NumPipes {
+ ADDR_CONFIG_1_PIPE = 0x0,
+ ADDR_CONFIG_2_PIPE = 0x1,
+ ADDR_CONFIG_4_PIPE = 0x2,
+ ADDR_CONFIG_8_PIPE = 0x3,
+} NumPipes;
+typedef enum PipeInterleaveSize {
+ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
+ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
+} PipeInterleaveSize;
+typedef enum BankInterleaveSize {
+ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
+ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
+ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
+ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
+} BankInterleaveSize;
+typedef enum NumShaderEngines {
+ ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
+ ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
+} NumShaderEngines;
+typedef enum ShaderEngineTileSize {
+ ADDR_CONFIG_SE_TILE_16 = 0x0,
+ ADDR_CONFIG_SE_TILE_32 = 0x1,
+} ShaderEngineTileSize;
+typedef enum NumGPUs {
+ ADDR_CONFIG_1_GPU = 0x0,
+ ADDR_CONFIG_2_GPU = 0x1,
+ ADDR_CONFIG_4_GPU = 0x2,
+} NumGPUs;
+typedef enum MultiGPUTileSize {
+ ADDR_CONFIG_GPU_TILE_16 = 0x0,
+ ADDR_CONFIG_GPU_TILE_32 = 0x1,
+ ADDR_CONFIG_GPU_TILE_64 = 0x2,
+ ADDR_CONFIG_GPU_TILE_128 = 0x3,
+} MultiGPUTileSize;
+typedef enum RowSize {
+ ADDR_CONFIG_1KB_ROW = 0x0,
+ ADDR_CONFIG_2KB_ROW = 0x1,
+ ADDR_CONFIG_4KB_ROW = 0x2,
+} RowSize;
+typedef enum NumLowerPipes {
+ ADDR_CONFIG_1_LOWER_PIPES = 0x0,
+ ADDR_CONFIG_2_LOWER_PIPES = 0x1,
+} NumLowerPipes;
+typedef enum DebugBlockId {
+ DBG_CLIENT_BLKID_RESERVED = 0x0,
+ DBG_CLIENT_BLKID_dbg = 0x1,
+ DBG_CLIENT_BLKID_scf2 = 0x2,
+ DBG_CLIENT_BLKID_mcd5 = 0x3,
+ DBG_CLIENT_BLKID_vmc = 0x4,
+ DBG_CLIENT_BLKID_sx30 = 0x5,
+ DBG_CLIENT_BLKID_mcd2 = 0x6,
+ DBG_CLIENT_BLKID_bci1 = 0x7,
+ DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8,
+ DBG_CLIENT_BLKID_mcc0 = 0x9,
+ DBG_CLIENT_BLKID_uvdf_0 = 0xa,
+ DBG_CLIENT_BLKID_uvdf_1 = 0xb,
+ DBG_CLIENT_BLKID_uvdf_2 = 0xc,
+ DBG_CLIENT_BLKID_uvdi_0 = 0xd,
+ DBG_CLIENT_BLKID_bci0 = 0xe,
+ DBG_CLIENT_BLKID_vcec0_0 = 0xf,
+ DBG_CLIENT_BLKID_cb100 = 0x10,
+ DBG_CLIENT_BLKID_cb001 = 0x11,
+ DBG_CLIENT_BLKID_mcd4 = 0x12,
+ DBG_CLIENT_BLKID_tmonw00 = 0x13,
+ DBG_CLIENT_BLKID_cb101 = 0x14,
+ DBG_CLIENT_BLKID_sx10 = 0x15,
+ DBG_CLIENT_BLKID_cb301 = 0x16,
+ DBG_CLIENT_BLKID_tmonw01 = 0x17,
+ DBG_CLIENT_BLKID_vcea0_0 = 0x18,
+ DBG_CLIENT_BLKID_vcea0_1 = 0x19,
+ DBG_CLIENT_BLKID_vcea0_2 = 0x1a,
+ DBG_CLIENT_BLKID_vcea0_3 = 0x1b,
+ DBG_CLIENT_BLKID_scf1 = 0x1c,
+ DBG_CLIENT_BLKID_sx20 = 0x1d,
+ DBG_CLIENT_BLKID_spim1 = 0x1e,
+ DBG_CLIENT_BLKID_pa10 = 0x1f,
+ DBG_CLIENT_BLKID_pa00 = 0x20,
+ DBG_CLIENT_BLKID_gmcon = 0x21,
+ DBG_CLIENT_BLKID_mcb = 0x22,
+ DBG_CLIENT_BLKID_vgt0 = 0x23,
+ DBG_CLIENT_BLKID_pc0 = 0x24,
+ DBG_CLIENT_BLKID_bci2 = 0x25,
+ DBG_CLIENT_BLKID_uvdb_0 = 0x26,
+ DBG_CLIENT_BLKID_spim3 = 0x27,
+ DBG_CLIENT_BLKID_cpc_0 = 0x28,
+ DBG_CLIENT_BLKID_cpc_1 = 0x29,
+ DBG_CLIENT_BLKID_uvdm_0 = 0x2a,
+ DBG_CLIENT_BLKID_uvdm_1 = 0x2b,
+ DBG_CLIENT_BLKID_uvdm_2 = 0x2c,
+ DBG_CLIENT_BLKID_uvdm_3 = 0x2d,
+ DBG_CLIENT_BLKID_cb000 = 0x2e,
+ DBG_CLIENT_BLKID_spim0 = 0x2f,
+ DBG_CLIENT_BLKID_mcc2 = 0x30,
+ DBG_CLIENT_BLKID_ds0 = 0x31,
+ DBG_CLIENT_BLKID_srbm = 0x32,
+ DBG_CLIENT_BLKID_ih = 0x33,
+ DBG_CLIENT_BLKID_sem = 0x34,
+ DBG_CLIENT_BLKID_sdma_0 = 0x35,
+ DBG_CLIENT_BLKID_sdma_1 = 0x36,
+ DBG_CLIENT_BLKID_hdp = 0x37,
+ DBG_CLIENT_BLKID_acp_0 = 0x38,
+ DBG_CLIENT_BLKID_acp_1 = 0x39,
+ DBG_CLIENT_BLKID_cb200 = 0x3a,
+ DBG_CLIENT_BLKID_scf3 = 0x3b,
+ DBG_CLIENT_BLKID_vceb1_0 = 0x3c,
+ DBG_CLIENT_BLKID_vcea1_0 = 0x3d,
+ DBG_CLIENT_BLKID_vcea1_1 = 0x3e,
+ DBG_CLIENT_BLKID_vcea1_2 = 0x3f,
+ DBG_CLIENT_BLKID_vcea1_3 = 0x40,
+ DBG_CLIENT_BLKID_bci3 = 0x41,
+ DBG_CLIENT_BLKID_mcd0 = 0x42,
+ DBG_CLIENT_BLKID_pa11 = 0x43,
+ DBG_CLIENT_BLKID_pa01 = 0x44,
+ DBG_CLIENT_BLKID_cb201 = 0x45,
+ DBG_CLIENT_BLKID_spim2 = 0x46,
+ DBG_CLIENT_BLKID_vgt2 = 0x47,
+ DBG_CLIENT_BLKID_pc2 = 0x48,
+ DBG_CLIENT_BLKID_smu_0 = 0x49,
+ DBG_CLIENT_BLKID_smu_1 = 0x4a,
+ DBG_CLIENT_BLKID_smu_2 = 0x4b,
+ DBG_CLIENT_BLKID_cb1 = 0x4c,
+ DBG_CLIENT_BLKID_ia0 = 0x4d,
+ DBG_CLIENT_BLKID_wd = 0x4e,
+ DBG_CLIENT_BLKID_ia1 = 0x4f,
+ DBG_CLIENT_BLKID_vcec1_0 = 0x50,
+ DBG_CLIENT_BLKID_scf0 = 0x51,
+ DBG_CLIENT_BLKID_vgt1 = 0x52,
+ DBG_CLIENT_BLKID_pc1 = 0x53,
+ DBG_CLIENT_BLKID_cb0 = 0x54,
+ DBG_CLIENT_BLKID_gdc_one_0 = 0x55,
+ DBG_CLIENT_BLKID_gdc_one_1 = 0x56,
+ DBG_CLIENT_BLKID_gdc_one_2 = 0x57,
+ DBG_CLIENT_BLKID_gdc_one_3 = 0x58,
+ DBG_CLIENT_BLKID_gdc_one_4 = 0x59,
+ DBG_CLIENT_BLKID_gdc_one_5 = 0x5a,
+ DBG_CLIENT_BLKID_gdc_one_6 = 0x5b,
+ DBG_CLIENT_BLKID_gdc_one_7 = 0x5c,
+ DBG_CLIENT_BLKID_gdc_one_8 = 0x5d,
+ DBG_CLIENT_BLKID_gdc_one_9 = 0x5e,
+ DBG_CLIENT_BLKID_gdc_one_10 = 0x5f,
+ DBG_CLIENT_BLKID_gdc_one_11 = 0x60,
+ DBG_CLIENT_BLKID_gdc_one_12 = 0x61,
+ DBG_CLIENT_BLKID_gdc_one_13 = 0x62,
+ DBG_CLIENT_BLKID_gdc_one_14 = 0x63,
+ DBG_CLIENT_BLKID_gdc_one_15 = 0x64,
+ DBG_CLIENT_BLKID_gdc_one_16 = 0x65,
+ DBG_CLIENT_BLKID_gdc_one_17 = 0x66,
+ DBG_CLIENT_BLKID_gdc_one_18 = 0x67,
+ DBG_CLIENT_BLKID_gdc_one_19 = 0x68,
+ DBG_CLIENT_BLKID_gdc_one_20 = 0x69,
+ DBG_CLIENT_BLKID_gdc_one_21 = 0x6a,
+ DBG_CLIENT_BLKID_gdc_one_22 = 0x6b,
+ DBG_CLIENT_BLKID_gdc_one_23 = 0x6c,
+ DBG_CLIENT_BLKID_gdc_one_24 = 0x6d,
+ DBG_CLIENT_BLKID_gdc_one_25 = 0x6e,
+ DBG_CLIENT_BLKID_gdc_one_26 = 0x6f,
+ DBG_CLIENT_BLKID_gdc_one_27 = 0x70,
+ DBG_CLIENT_BLKID_gdc_one_28 = 0x71,
+ DBG_CLIENT_BLKID_gdc_one_29 = 0x72,
+ DBG_CLIENT_BLKID_gdc_one_30 = 0x73,
+ DBG_CLIENT_BLKID_gdc_one_31 = 0x74,
+ DBG_CLIENT_BLKID_gdc_one_32 = 0x75,
+ DBG_CLIENT_BLKID_gdc_one_33 = 0x76,
+ DBG_CLIENT_BLKID_gdc_one_34 = 0x77,
+ DBG_CLIENT_BLKID_gdc_one_35 = 0x78,
+ DBG_CLIENT_BLKID_vceb0_0 = 0x79,
+ DBG_CLIENT_BLKID_vgt3 = 0x7a,
+ DBG_CLIENT_BLKID_pc3 = 0x7b,
+ DBG_CLIENT_BLKID_mcd3 = 0x7c,
+ DBG_CLIENT_BLKID_uvdu_0 = 0x7d,
+ DBG_CLIENT_BLKID_uvdu_1 = 0x7e,
+ DBG_CLIENT_BLKID_uvdu_2 = 0x7f,
+ DBG_CLIENT_BLKID_uvdu_3 = 0x80,
+ DBG_CLIENT_BLKID_uvdu_4 = 0x81,
+ DBG_CLIENT_BLKID_uvdu_5 = 0x82,
+ DBG_CLIENT_BLKID_uvdu_6 = 0x83,
+ DBG_CLIENT_BLKID_cb300 = 0x84,
+ DBG_CLIENT_BLKID_mcd1 = 0x85,
+ DBG_CLIENT_BLKID_sx00 = 0x86,
+ DBG_CLIENT_BLKID_uvdc_0 = 0x87,
+ DBG_CLIENT_BLKID_uvdc_1 = 0x88,
+ DBG_CLIENT_BLKID_mcc3 = 0x89,
+ DBG_CLIENT_BLKID_cpg_0 = 0x8a,
+ DBG_CLIENT_BLKID_cpg_1 = 0x8b,
+ DBG_CLIENT_BLKID_gck = 0x8c,
+ DBG_CLIENT_BLKID_mcc1 = 0x8d,
+ DBG_CLIENT_BLKID_cpf_0 = 0x8e,
+ DBG_CLIENT_BLKID_cpf_1 = 0x8f,
+ DBG_CLIENT_BLKID_rlc = 0x90,
+ DBG_CLIENT_BLKID_grbm = 0x91,
+ DBG_CLIENT_BLKID_sammsp = 0x92,
+ DBG_CLIENT_BLKID_dci_pg = 0x93,
+ DBG_CLIENT_BLKID_dci_0 = 0x94,
+ DBG_CLIENT_BLKID_dccg0_0 = 0x95,
+ DBG_CLIENT_BLKID_dccg0_1 = 0x96,
+ DBG_CLIENT_BLKID_dcfe01_0 = 0x97,
+ DBG_CLIENT_BLKID_dcfe02_0 = 0x98,
+ DBG_CLIENT_BLKID_dcfe03_0 = 0x99,
+ DBG_CLIENT_BLKID_dcfe04_0 = 0x9a,
+ DBG_CLIENT_BLKID_dcfe05_0 = 0x9b,
+ DBG_CLIENT_BLKID_dcfe06_0 = 0x9c,
+ DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d,
+} DebugBlockId;
+typedef enum DebugBlockId_OLD {
+ DBG_BLOCK_ID_RESERVED = 0x0,
+ DBG_BLOCK_ID_DBG = 0x1,
+ DBG_BLOCK_ID_VMC = 0x2,
+ DBG_BLOCK_ID_PDMA = 0x3,
+ DBG_BLOCK_ID_CG = 0x4,
+ DBG_BLOCK_ID_SRBM = 0x5,
+ DBG_BLOCK_ID_GRBM = 0x6,
+ DBG_BLOCK_ID_RLC = 0x7,
+ DBG_BLOCK_ID_CSC = 0x8,
+ DBG_BLOCK_ID_SEM = 0x9,
+ DBG_BLOCK_ID_IH = 0xa,
+ DBG_BLOCK_ID_SC = 0xb,
+ DBG_BLOCK_ID_SQ = 0xc,
+ DBG_BLOCK_ID_AVP = 0xd,
+ DBG_BLOCK_ID_GMCON = 0xe,
+ DBG_BLOCK_ID_SMU = 0xf,
+ DBG_BLOCK_ID_DMA0 = 0x10,
+ DBG_BLOCK_ID_DMA1 = 0x11,
+ DBG_BLOCK_ID_SPIM = 0x12,
+ DBG_BLOCK_ID_GDS = 0x13,
+ DBG_BLOCK_ID_SPIS = 0x14,
+ DBG_BLOCK_ID_UNUSED0 = 0x15,
+ DBG_BLOCK_ID_PA0 = 0x16,
+ DBG_BLOCK_ID_PA1 = 0x17,
+ DBG_BLOCK_ID_CP0 = 0x18,
+ DBG_BLOCK_ID_CP1 = 0x19,
+ DBG_BLOCK_ID_CP2 = 0x1a,
+ DBG_BLOCK_ID_UNUSED1 = 0x1b,
+ DBG_BLOCK_ID_UVDU = 0x1c,
+ DBG_BLOCK_ID_UVDM = 0x1d,
+ DBG_BLOCK_ID_VCE = 0x1e,
+ DBG_BLOCK_ID_UNUSED2 = 0x1f,
+ DBG_BLOCK_ID_VGT0 = 0x20,
+ DBG_BLOCK_ID_VGT1 = 0x21,
+ DBG_BLOCK_ID_IA = 0x22,
+ DBG_BLOCK_ID_UNUSED3 = 0x23,
+ DBG_BLOCK_ID_SCT0 = 0x24,
+ DBG_BLOCK_ID_SCT1 = 0x25,
+ DBG_BLOCK_ID_SPM0 = 0x26,
+ DBG_BLOCK_ID_SPM1 = 0x27,
+ DBG_BLOCK_ID_TCAA = 0x28,
+ DBG_BLOCK_ID_TCAB = 0x29,
+ DBG_BLOCK_ID_TCCA = 0x2a,
+ DBG_BLOCK_ID_TCCB = 0x2b,
+ DBG_BLOCK_ID_MCC0 = 0x2c,
+ DBG_BLOCK_ID_MCC1 = 0x2d,
+ DBG_BLOCK_ID_MCC2 = 0x2e,
+ DBG_BLOCK_ID_MCC3 = 0x2f,
+ DBG_BLOCK_ID_SX0 = 0x30,
+ DBG_BLOCK_ID_SX1 = 0x31,
+ DBG_BLOCK_ID_SX2 = 0x32,
+ DBG_BLOCK_ID_SX3 = 0x33,
+ DBG_BLOCK_ID_UNUSED4 = 0x34,
+ DBG_BLOCK_ID_UNUSED5 = 0x35,
+ DBG_BLOCK_ID_UNUSED6 = 0x36,
+ DBG_BLOCK_ID_UNUSED7 = 0x37,
+ DBG_BLOCK_ID_PC0 = 0x38,
+ DBG_BLOCK_ID_PC1 = 0x39,
+ DBG_BLOCK_ID_UNUSED8 = 0x3a,
+ DBG_BLOCK_ID_UNUSED9 = 0x3b,
+ DBG_BLOCK_ID_UNUSED10 = 0x3c,
+ DBG_BLOCK_ID_UNUSED11 = 0x3d,
+ DBG_BLOCK_ID_MCB = 0x3e,
+ DBG_BLOCK_ID_UNUSED12 = 0x3f,
+ DBG_BLOCK_ID_SCB0 = 0x40,
+ DBG_BLOCK_ID_SCB1 = 0x41,
+ DBG_BLOCK_ID_UNUSED13 = 0x42,
+ DBG_BLOCK_ID_UNUSED14 = 0x43,
+ DBG_BLOCK_ID_SCF0 = 0x44,
+ DBG_BLOCK_ID_SCF1 = 0x45,
+ DBG_BLOCK_ID_UNUSED15 = 0x46,
+ DBG_BLOCK_ID_UNUSED16 = 0x47,
+ DBG_BLOCK_ID_BCI0 = 0x48,
+ DBG_BLOCK_ID_BCI1 = 0x49,
+ DBG_BLOCK_ID_BCI2 = 0x4a,
+ DBG_BLOCK_ID_BCI3 = 0x4b,
+ DBG_BLOCK_ID_UNUSED17 = 0x4c,
+ DBG_BLOCK_ID_UNUSED18 = 0x4d,
+ DBG_BLOCK_ID_UNUSED19 = 0x4e,
+ DBG_BLOCK_ID_UNUSED20 = 0x4f,
+ DBG_BLOCK_ID_CB00 = 0x50,
+ DBG_BLOCK_ID_CB01 = 0x51,
+ DBG_BLOCK_ID_CB02 = 0x52,
+ DBG_BLOCK_ID_CB03 = 0x53,
+ DBG_BLOCK_ID_CB04 = 0x54,
+ DBG_BLOCK_ID_UNUSED21 = 0x55,
+ DBG_BLOCK_ID_UNUSED22 = 0x56,
+ DBG_BLOCK_ID_UNUSED23 = 0x57,
+ DBG_BLOCK_ID_CB10 = 0x58,
+ DBG_BLOCK_ID_CB11 = 0x59,
+ DBG_BLOCK_ID_CB12 = 0x5a,
+ DBG_BLOCK_ID_CB13 = 0x5b,
+ DBG_BLOCK_ID_CB14 = 0x5c,
+ DBG_BLOCK_ID_UNUSED24 = 0x5d,
+ DBG_BLOCK_ID_UNUSED25 = 0x5e,
+ DBG_BLOCK_ID_UNUSED26 = 0x5f,
+ DBG_BLOCK_ID_TCP0 = 0x60,
+ DBG_BLOCK_ID_TCP1 = 0x61,
+ DBG_BLOCK_ID_TCP2 = 0x62,
+ DBG_BLOCK_ID_TCP3 = 0x63,
+ DBG_BLOCK_ID_TCP4 = 0x64,
+ DBG_BLOCK_ID_TCP5 = 0x65,
+ DBG_BLOCK_ID_TCP6 = 0x66,
+ DBG_BLOCK_ID_TCP7 = 0x67,
+ DBG_BLOCK_ID_TCP8 = 0x68,
+ DBG_BLOCK_ID_TCP9 = 0x69,
+ DBG_BLOCK_ID_TCP10 = 0x6a,
+ DBG_BLOCK_ID_TCP11 = 0x6b,
+ DBG_BLOCK_ID_TCP12 = 0x6c,
+ DBG_BLOCK_ID_TCP13 = 0x6d,
+ DBG_BLOCK_ID_TCP14 = 0x6e,
+ DBG_BLOCK_ID_TCP15 = 0x6f,
+ DBG_BLOCK_ID_TCP16 = 0x70,
+ DBG_BLOCK_ID_TCP17 = 0x71,
+ DBG_BLOCK_ID_TCP18 = 0x72,
+ DBG_BLOCK_ID_TCP19 = 0x73,
+ DBG_BLOCK_ID_TCP20 = 0x74,
+ DBG_BLOCK_ID_TCP21 = 0x75,
+ DBG_BLOCK_ID_TCP22 = 0x76,
+ DBG_BLOCK_ID_TCP23 = 0x77,
+ DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
+ DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
+ DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
+ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
+ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
+ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
+ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
+ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
+ DBG_BLOCK_ID_DB00 = 0x80,
+ DBG_BLOCK_ID_DB01 = 0x81,
+ DBG_BLOCK_ID_DB02 = 0x82,
+ DBG_BLOCK_ID_DB03 = 0x83,
+ DBG_BLOCK_ID_DB04 = 0x84,
+ DBG_BLOCK_ID_UNUSED27 = 0x85,
+ DBG_BLOCK_ID_UNUSED28 = 0x86,
+ DBG_BLOCK_ID_UNUSED29 = 0x87,
+ DBG_BLOCK_ID_DB10 = 0x88,
+ DBG_BLOCK_ID_DB11 = 0x89,
+ DBG_BLOCK_ID_DB12 = 0x8a,
+ DBG_BLOCK_ID_DB13 = 0x8b,
+ DBG_BLOCK_ID_DB14 = 0x8c,
+ DBG_BLOCK_ID_UNUSED30 = 0x8d,
+ DBG_BLOCK_ID_UNUSED31 = 0x8e,
+ DBG_BLOCK_ID_UNUSED32 = 0x8f,
+ DBG_BLOCK_ID_TCC0 = 0x90,
+ DBG_BLOCK_ID_TCC1 = 0x91,
+ DBG_BLOCK_ID_TCC2 = 0x92,
+ DBG_BLOCK_ID_TCC3 = 0x93,
+ DBG_BLOCK_ID_TCC4 = 0x94,
+ DBG_BLOCK_ID_TCC5 = 0x95,
+ DBG_BLOCK_ID_TCC6 = 0x96,
+ DBG_BLOCK_ID_TCC7 = 0x97,
+ DBG_BLOCK_ID_SPS00 = 0x98,
+ DBG_BLOCK_ID_SPS01 = 0x99,
+ DBG_BLOCK_ID_SPS02 = 0x9a,
+ DBG_BLOCK_ID_SPS10 = 0x9b,
+ DBG_BLOCK_ID_SPS11 = 0x9c,
+ DBG_BLOCK_ID_SPS12 = 0x9d,
+ DBG_BLOCK_ID_UNUSED33 = 0x9e,
+ DBG_BLOCK_ID_UNUSED34 = 0x9f,
+ DBG_BLOCK_ID_TA00 = 0xa0,
+ DBG_BLOCK_ID_TA01 = 0xa1,
+ DBG_BLOCK_ID_TA02 = 0xa2,
+ DBG_BLOCK_ID_TA03 = 0xa3,
+ DBG_BLOCK_ID_TA04 = 0xa4,
+ DBG_BLOCK_ID_TA05 = 0xa5,
+ DBG_BLOCK_ID_TA06 = 0xa6,
+ DBG_BLOCK_ID_TA07 = 0xa7,
+ DBG_BLOCK_ID_TA08 = 0xa8,
+ DBG_BLOCK_ID_TA09 = 0xa9,
+ DBG_BLOCK_ID_TA0A = 0xaa,
+ DBG_BLOCK_ID_TA0B = 0xab,
+ DBG_BLOCK_ID_UNUSED35 = 0xac,
+ DBG_BLOCK_ID_UNUSED36 = 0xad,
+ DBG_BLOCK_ID_UNUSED37 = 0xae,
+ DBG_BLOCK_ID_UNUSED38 = 0xaf,
+ DBG_BLOCK_ID_TA10 = 0xb0,
+ DBG_BLOCK_ID_TA11 = 0xb1,
+ DBG_BLOCK_ID_TA12 = 0xb2,
+ DBG_BLOCK_ID_TA13 = 0xb3,
+ DBG_BLOCK_ID_TA14 = 0xb4,
+ DBG_BLOCK_ID_TA15 = 0xb5,
+ DBG_BLOCK_ID_TA16 = 0xb6,
+ DBG_BLOCK_ID_TA17 = 0xb7,
+ DBG_BLOCK_ID_TA18 = 0xb8,
+ DBG_BLOCK_ID_TA19 = 0xb9,
+ DBG_BLOCK_ID_TA1A = 0xba,
+ DBG_BLOCK_ID_TA1B = 0xbb,
+ DBG_BLOCK_ID_UNUSED39 = 0xbc,
+ DBG_BLOCK_ID_UNUSED40 = 0xbd,
+ DBG_BLOCK_ID_UNUSED41 = 0xbe,
+ DBG_BLOCK_ID_UNUSED42 = 0xbf,
+ DBG_BLOCK_ID_TD00 = 0xc0,
+ DBG_BLOCK_ID_TD01 = 0xc1,
+ DBG_BLOCK_ID_TD02 = 0xc2,
+ DBG_BLOCK_ID_TD03 = 0xc3,
+ DBG_BLOCK_ID_TD04 = 0xc4,
+ DBG_BLOCK_ID_TD05 = 0xc5,
+ DBG_BLOCK_ID_TD06 = 0xc6,
+ DBG_BLOCK_ID_TD07 = 0xc7,
+ DBG_BLOCK_ID_TD08 = 0xc8,
+ DBG_BLOCK_ID_TD09 = 0xc9,
+ DBG_BLOCK_ID_TD0A = 0xca,
+ DBG_BLOCK_ID_TD0B = 0xcb,
+ DBG_BLOCK_ID_UNUSED43 = 0xcc,
+ DBG_BLOCK_ID_UNUSED44 = 0xcd,
+ DBG_BLOCK_ID_UNUSED45 = 0xce,
+ DBG_BLOCK_ID_UNUSED46 = 0xcf,
+ DBG_BLOCK_ID_TD10 = 0xd0,
+ DBG_BLOCK_ID_TD11 = 0xd1,
+ DBG_BLOCK_ID_TD12 = 0xd2,
+ DBG_BLOCK_ID_TD13 = 0xd3,
+ DBG_BLOCK_ID_TD14 = 0xd4,
+ DBG_BLOCK_ID_TD15 = 0xd5,
+ DBG_BLOCK_ID_TD16 = 0xd6,
+ DBG_BLOCK_ID_TD17 = 0xd7,
+ DBG_BLOCK_ID_TD18 = 0xd8,
+ DBG_BLOCK_ID_TD19 = 0xd9,
+ DBG_BLOCK_ID_TD1A = 0xda,
+ DBG_BLOCK_ID_TD1B = 0xdb,
+ DBG_BLOCK_ID_UNUSED47 = 0xdc,
+ DBG_BLOCK_ID_UNUSED48 = 0xdd,
+ DBG_BLOCK_ID_UNUSED49 = 0xde,
+ DBG_BLOCK_ID_UNUSED50 = 0xdf,
+ DBG_BLOCK_ID_MCD0 = 0xe0,
+ DBG_BLOCK_ID_MCD1 = 0xe1,
+ DBG_BLOCK_ID_MCD2 = 0xe2,
+ DBG_BLOCK_ID_MCD3 = 0xe3,
+ DBG_BLOCK_ID_MCD4 = 0xe4,
+ DBG_BLOCK_ID_MCD5 = 0xe5,
+ DBG_BLOCK_ID_UNUSED51 = 0xe6,
+ DBG_BLOCK_ID_UNUSED52 = 0xe7,
+} DebugBlockId_OLD;
+typedef enum DebugBlockId_BY2 {
+ DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
+ DBG_BLOCK_ID_VMC_BY2 = 0x1,
+ DBG_BLOCK_ID_CG_BY2 = 0x2,
+ DBG_BLOCK_ID_GRBM_BY2 = 0x3,
+ DBG_BLOCK_ID_CSC_BY2 = 0x4,
+ DBG_BLOCK_ID_IH_BY2 = 0x5,
+ DBG_BLOCK_ID_SQ_BY2 = 0x6,
+ DBG_BLOCK_ID_GMCON_BY2 = 0x7,
+ DBG_BLOCK_ID_DMA0_BY2 = 0x8,
+ DBG_BLOCK_ID_SPIM_BY2 = 0x9,
+ DBG_BLOCK_ID_SPIS_BY2 = 0xa,
+ DBG_BLOCK_ID_PA0_BY2 = 0xb,
+ DBG_BLOCK_ID_CP0_BY2 = 0xc,
+ DBG_BLOCK_ID_CP2_BY2 = 0xd,
+ DBG_BLOCK_ID_UVDU_BY2 = 0xe,
+ DBG_BLOCK_ID_VCE_BY2 = 0xf,
+ DBG_BLOCK_ID_VGT0_BY2 = 0x10,
+ DBG_BLOCK_ID_IA_BY2 = 0x11,
+ DBG_BLOCK_ID_SCT0_BY2 = 0x12,
+ DBG_BLOCK_ID_SPM0_BY2 = 0x13,
+ DBG_BLOCK_ID_TCAA_BY2 = 0x14,
+ DBG_BLOCK_ID_TCCA_BY2 = 0x15,
+ DBG_BLOCK_ID_MCC0_BY2 = 0x16,
+ DBG_BLOCK_ID_MCC2_BY2 = 0x17,
+ DBG_BLOCK_ID_SX0_BY2 = 0x18,
+ DBG_BLOCK_ID_SX2_BY2 = 0x19,
+ DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
+ DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
+ DBG_BLOCK_ID_PC0_BY2 = 0x1c,
+ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
+ DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
+ DBG_BLOCK_ID_MCB_BY2 = 0x1f,
+ DBG_BLOCK_ID_SCB0_BY2 = 0x20,
+ DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
+ DBG_BLOCK_ID_SCF0_BY2 = 0x22,
+ DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
+ DBG_BLOCK_ID_BCI0_BY2 = 0x24,
+ DBG_BLOCK_ID_BCI2_BY2 = 0x25,
+ DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
+ DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
+ DBG_BLOCK_ID_CB00_BY2 = 0x28,
+ DBG_BLOCK_ID_CB02_BY2 = 0x29,
+ DBG_BLOCK_ID_CB04_BY2 = 0x2a,
+ DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
+ DBG_BLOCK_ID_CB10_BY2 = 0x2c,
+ DBG_BLOCK_ID_CB12_BY2 = 0x2d,
+ DBG_BLOCK_ID_CB14_BY2 = 0x2e,
+ DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
+ DBG_BLOCK_ID_TCP0_BY2 = 0x30,
+ DBG_BLOCK_ID_TCP2_BY2 = 0x31,
+ DBG_BLOCK_ID_TCP4_BY2 = 0x32,
+ DBG_BLOCK_ID_TCP6_BY2 = 0x33,
+ DBG_BLOCK_ID_TCP8_BY2 = 0x34,
+ DBG_BLOCK_ID_TCP10_BY2 = 0x35,
+ DBG_BLOCK_ID_TCP12_BY2 = 0x36,
+ DBG_BLOCK_ID_TCP14_BY2 = 0x37,
+ DBG_BLOCK_ID_TCP16_BY2 = 0x38,
+ DBG_BLOCK_ID_TCP18_BY2 = 0x39,
+ DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
+ DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
+ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
+ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
+ DBG_BLOCK_ID_DB00_BY2 = 0x40,
+ DBG_BLOCK_ID_DB02_BY2 = 0x41,
+ DBG_BLOCK_ID_DB04_BY2 = 0x42,
+ DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
+ DBG_BLOCK_ID_DB10_BY2 = 0x44,
+ DBG_BLOCK_ID_DB12_BY2 = 0x45,
+ DBG_BLOCK_ID_DB14_BY2 = 0x46,
+ DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
+ DBG_BLOCK_ID_TCC0_BY2 = 0x48,
+ DBG_BLOCK_ID_TCC2_BY2 = 0x49,
+ DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
+ DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
+ DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
+ DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
+ DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
+ DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
+ DBG_BLOCK_ID_TA00_BY2 = 0x50,
+ DBG_BLOCK_ID_TA02_BY2 = 0x51,
+ DBG_BLOCK_ID_TA04_BY2 = 0x52,
+ DBG_BLOCK_ID_TA06_BY2 = 0x53,
+ DBG_BLOCK_ID_TA08_BY2 = 0x54,
+ DBG_BLOCK_ID_TA0A_BY2 = 0x55,
+ DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
+ DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
+ DBG_BLOCK_ID_TA10_BY2 = 0x58,
+ DBG_BLOCK_ID_TA12_BY2 = 0x59,
+ DBG_BLOCK_ID_TA14_BY2 = 0x5a,
+ DBG_BLOCK_ID_TA16_BY2 = 0x5b,
+ DBG_BLOCK_ID_TA18_BY2 = 0x5c,
+ DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
+ DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
+ DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
+ DBG_BLOCK_ID_TD00_BY2 = 0x60,
+ DBG_BLOCK_ID_TD02_BY2 = 0x61,
+ DBG_BLOCK_ID_TD04_BY2 = 0x62,
+ DBG_BLOCK_ID_TD06_BY2 = 0x63,
+ DBG_BLOCK_ID_TD08_BY2 = 0x64,
+ DBG_BLOCK_ID_TD0A_BY2 = 0x65,
+ DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
+ DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
+ DBG_BLOCK_ID_TD10_BY2 = 0x68,
+ DBG_BLOCK_ID_TD12_BY2 = 0x69,
+ DBG_BLOCK_ID_TD14_BY2 = 0x6a,
+ DBG_BLOCK_ID_TD16_BY2 = 0x6b,
+ DBG_BLOCK_ID_TD18_BY2 = 0x6c,
+ DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
+ DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
+ DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
+ DBG_BLOCK_ID_MCD0_BY2 = 0x70,
+ DBG_BLOCK_ID_MCD2_BY2 = 0x71,
+ DBG_BLOCK_ID_MCD4_BY2 = 0x72,
+ DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
+} DebugBlockId_BY2;
+typedef enum DebugBlockId_BY4 {
+ DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
+ DBG_BLOCK_ID_CG_BY4 = 0x1,
+ DBG_BLOCK_ID_CSC_BY4 = 0x2,
+ DBG_BLOCK_ID_SQ_BY4 = 0x3,
+ DBG_BLOCK_ID_DMA0_BY4 = 0x4,
+ DBG_BLOCK_ID_SPIS_BY4 = 0x5,
+ DBG_BLOCK_ID_CP0_BY4 = 0x6,
+ DBG_BLOCK_ID_UVDU_BY4 = 0x7,
+ DBG_BLOCK_ID_VGT0_BY4 = 0x8,
+ DBG_BLOCK_ID_SCT0_BY4 = 0x9,
+ DBG_BLOCK_ID_TCAA_BY4 = 0xa,
+ DBG_BLOCK_ID_MCC0_BY4 = 0xb,
+ DBG_BLOCK_ID_SX0_BY4 = 0xc,
+ DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
+ DBG_BLOCK_ID_PC0_BY4 = 0xe,
+ DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
+ DBG_BLOCK_ID_SCB0_BY4 = 0x10,
+ DBG_BLOCK_ID_SCF0_BY4 = 0x11,
+ DBG_BLOCK_ID_BCI0_BY4 = 0x12,
+ DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
+ DBG_BLOCK_ID_CB00_BY4 = 0x14,
+ DBG_BLOCK_ID_CB04_BY4 = 0x15,
+ DBG_BLOCK_ID_CB10_BY4 = 0x16,
+ DBG_BLOCK_ID_CB14_BY4 = 0x17,
+ DBG_BLOCK_ID_TCP0_BY4 = 0x18,
+ DBG_BLOCK_ID_TCP4_BY4 = 0x19,
+ DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
+ DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
+ DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
+ DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
+ DBG_BLOCK_ID_DB_BY4 = 0x20,
+ DBG_BLOCK_ID_DB04_BY4 = 0x21,
+ DBG_BLOCK_ID_DB10_BY4 = 0x22,
+ DBG_BLOCK_ID_DB14_BY4 = 0x23,
+ DBG_BLOCK_ID_TCC0_BY4 = 0x24,
+ DBG_BLOCK_ID_TCC4_BY4 = 0x25,
+ DBG_BLOCK_ID_SPS00_BY4 = 0x26,
+ DBG_BLOCK_ID_SPS11_BY4 = 0x27,
+ DBG_BLOCK_ID_TA00_BY4 = 0x28,
+ DBG_BLOCK_ID_TA04_BY4 = 0x29,
+ DBG_BLOCK_ID_TA08_BY4 = 0x2a,
+ DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
+ DBG_BLOCK_ID_TA10_BY4 = 0x2c,
+ DBG_BLOCK_ID_TA14_BY4 = 0x2d,
+ DBG_BLOCK_ID_TA18_BY4 = 0x2e,
+ DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
+ DBG_BLOCK_ID_TD00_BY4 = 0x30,
+ DBG_BLOCK_ID_TD04_BY4 = 0x31,
+ DBG_BLOCK_ID_TD08_BY4 = 0x32,
+ DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
+ DBG_BLOCK_ID_TD10_BY4 = 0x34,
+ DBG_BLOCK_ID_TD14_BY4 = 0x35,
+ DBG_BLOCK_ID_TD18_BY4 = 0x36,
+ DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
+ DBG_BLOCK_ID_MCD0_BY4 = 0x38,
+ DBG_BLOCK_ID_MCD4_BY4 = 0x39,
+} DebugBlockId_BY4;
+typedef enum DebugBlockId_BY8 {
+ DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
+ DBG_BLOCK_ID_CSC_BY8 = 0x1,
+ DBG_BLOCK_ID_DMA0_BY8 = 0x2,
+ DBG_BLOCK_ID_CP0_BY8 = 0x3,
+ DBG_BLOCK_ID_VGT0_BY8 = 0x4,
+ DBG_BLOCK_ID_TCAA_BY8 = 0x5,
+ DBG_BLOCK_ID_SX0_BY8 = 0x6,
+ DBG_BLOCK_ID_PC0_BY8 = 0x7,
+ DBG_BLOCK_ID_SCB0_BY8 = 0x8,
+ DBG_BLOCK_ID_BCI0_BY8 = 0x9,
+ DBG_BLOCK_ID_CB00_BY8 = 0xa,
+ DBG_BLOCK_ID_CB10_BY8 = 0xb,
+ DBG_BLOCK_ID_TCP0_BY8 = 0xc,
+ DBG_BLOCK_ID_TCP8_BY8 = 0xd,
+ DBG_BLOCK_ID_TCP16_BY8 = 0xe,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
+ DBG_BLOCK_ID_DB00_BY8 = 0x10,
+ DBG_BLOCK_ID_DB10_BY8 = 0x11,
+ DBG_BLOCK_ID_TCC0_BY8 = 0x12,
+ DBG_BLOCK_ID_SPS00_BY8 = 0x13,
+ DBG_BLOCK_ID_TA00_BY8 = 0x14,
+ DBG_BLOCK_ID_TA08_BY8 = 0x15,
+ DBG_BLOCK_ID_TA10_BY8 = 0x16,
+ DBG_BLOCK_ID_TA18_BY8 = 0x17,
+ DBG_BLOCK_ID_TD00_BY8 = 0x18,
+ DBG_BLOCK_ID_TD08_BY8 = 0x19,
+ DBG_BLOCK_ID_TD10_BY8 = 0x1a,
+ DBG_BLOCK_ID_TD18_BY8 = 0x1b,
+ DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
+} DebugBlockId_BY8;
+typedef enum DebugBlockId_BY16 {
+ DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
+ DBG_BLOCK_ID_DMA0_BY16 = 0x1,
+ DBG_BLOCK_ID_VGT0_BY16 = 0x2,
+ DBG_BLOCK_ID_SX0_BY16 = 0x3,
+ DBG_BLOCK_ID_SCB0_BY16 = 0x4,
+ DBG_BLOCK_ID_CB00_BY16 = 0x5,
+ DBG_BLOCK_ID_TCP0_BY16 = 0x6,
+ DBG_BLOCK_ID_TCP16_BY16 = 0x7,
+ DBG_BLOCK_ID_DB00_BY16 = 0x8,
+ DBG_BLOCK_ID_TCC0_BY16 = 0x9,
+ DBG_BLOCK_ID_TA00_BY16 = 0xa,
+ DBG_BLOCK_ID_TA10_BY16 = 0xb,
+ DBG_BLOCK_ID_TD00_BY16 = 0xc,
+ DBG_BLOCK_ID_TD10_BY16 = 0xd,
+ DBG_BLOCK_ID_MCD0_BY16 = 0xe,
+} DebugBlockId_BY16;
+typedef enum ColorTransform {
+ DCC_CT_AUTO = 0x0,
+ DCC_CT_NONE = 0x1,
+ ABGR_TO_A_BG_G_RB = 0x2,
+ BGRA_TO_BG_G_RB_A = 0x3,
+} ColorTransform;
+typedef enum CompareRef {
+ REF_NEVER = 0x0,
+ REF_LESS = 0x1,
+ REF_EQUAL = 0x2,
+ REF_LEQUAL = 0x3,
+ REF_GREATER = 0x4,
+ REF_NOTEQUAL = 0x5,
+ REF_GEQUAL = 0x6,
+ REF_ALWAYS = 0x7,
+} CompareRef;
+typedef enum ReadSize {
+ READ_256_BITS = 0x0,
+ READ_512_BITS = 0x1,
+} ReadSize;
+typedef enum DepthFormat {
+ DEPTH_INVALID = 0x0,
+ DEPTH_16 = 0x1,
+ DEPTH_X8_24 = 0x2,
+ DEPTH_8_24 = 0x3,
+ DEPTH_X8_24_FLOAT = 0x4,
+ DEPTH_8_24_FLOAT = 0x5,
+ DEPTH_32_FLOAT = 0x6,
+ DEPTH_X24_8_32_FLOAT = 0x7,
+} DepthFormat;
+typedef enum ZFormat {
+ Z_INVALID = 0x0,
+ Z_16 = 0x1,
+ Z_24 = 0x2,
+ Z_32_FLOAT = 0x3,
+} ZFormat;
+typedef enum StencilFormat {
+ STENCIL_INVALID = 0x0,
+ STENCIL_8 = 0x1,
+} StencilFormat;
+typedef enum CmaskMode {
+ CMASK_CLEAR_NONE = 0x0,
+ CMASK_CLEAR_ONE = 0x1,
+ CMASK_CLEAR_ALL = 0x2,
+ CMASK_ANY_EXPANDED = 0x3,
+ CMASK_ALPHA0_FRAG1 = 0x4,
+ CMASK_ALPHA0_FRAG2 = 0x5,
+ CMASK_ALPHA0_FRAG4 = 0x6,
+ CMASK_ALPHA0_FRAGS = 0x7,
+ CMASK_ALPHA1_FRAG1 = 0x8,
+ CMASK_ALPHA1_FRAG2 = 0x9,
+ CMASK_ALPHA1_FRAG4 = 0xa,
+ CMASK_ALPHA1_FRAGS = 0xb,
+ CMASK_ALPHAX_FRAG1 = 0xc,
+ CMASK_ALPHAX_FRAG2 = 0xd,
+ CMASK_ALPHAX_FRAG4 = 0xe,
+ CMASK_ALPHAX_FRAGS = 0xf,
+} CmaskMode;
+typedef enum QuadExportFormat {
+ EXPORT_UNUSED = 0x0,
+ EXPORT_32_R = 0x1,
+ EXPORT_32_GR = 0x2,
+ EXPORT_32_AR = 0x3,
+ EXPORT_FP16_ABGR = 0x4,
+ EXPORT_UNSIGNED16_ABGR = 0x5,
+ EXPORT_SIGNED16_ABGR = 0x6,
+ EXPORT_32_ABGR = 0x7,
+} QuadExportFormat;
+typedef enum QuadExportFormatOld {
+ EXPORT_4P_32BPC_ABGR = 0x0,
+ EXPORT_4P_16BPC_ABGR = 0x1,
+ EXPORT_4P_32BPC_GR = 0x2,
+ EXPORT_4P_32BPC_AR = 0x3,
+ EXPORT_2P_32BPC_ABGR = 0x4,
+ EXPORT_8P_32BPC_R = 0x5,
+} QuadExportFormatOld;
+typedef enum ColorFormat {
+ COLOR_INVALID = 0x0,
+ COLOR_8 = 0x1,
+ COLOR_16 = 0x2,
+ COLOR_8_8 = 0x3,
+ COLOR_32 = 0x4,
+ COLOR_16_16 = 0x5,
+ COLOR_10_11_11 = 0x6,
+ COLOR_11_11_10 = 0x7,
+ COLOR_10_10_10_2 = 0x8,
+ COLOR_2_10_10_10 = 0x9,
+ COLOR_8_8_8_8 = 0xa,
+ COLOR_32_32 = 0xb,
+ COLOR_16_16_16_16 = 0xc,
+ COLOR_RESERVED_13 = 0xd,
+ COLOR_32_32_32_32 = 0xe,
+ COLOR_RESERVED_15 = 0xf,
+ COLOR_5_6_5 = 0x10,
+ COLOR_1_5_5_5 = 0x11,
+ COLOR_5_5_5_1 = 0x12,
+ COLOR_4_4_4_4 = 0x13,
+ COLOR_8_24 = 0x14,
+ COLOR_24_8 = 0x15,
+ COLOR_X24_8_32_FLOAT = 0x16,
+ COLOR_RESERVED_23 = 0x17,
+} ColorFormat;
+typedef enum SurfaceFormat {
+ FMT_INVALID = 0x0,
+ FMT_8 = 0x1,
+ FMT_16 = 0x2,
+ FMT_8_8 = 0x3,
+ FMT_32 = 0x4,
+ FMT_16_16 = 0x5,
+ FMT_10_11_11 = 0x6,
+ FMT_11_11_10 = 0x7,
+ FMT_10_10_10_2 = 0x8,
+ FMT_2_10_10_10 = 0x9,
+ FMT_8_8_8_8 = 0xa,
+ FMT_32_32 = 0xb,
+ FMT_16_16_16_16 = 0xc,
+ FMT_32_32_32 = 0xd,
+ FMT_32_32_32_32 = 0xe,
+ FMT_RESERVED_4 = 0xf,
+ FMT_5_6_5 = 0x10,
+ FMT_1_5_5_5 = 0x11,
+ FMT_5_5_5_1 = 0x12,
+ FMT_4_4_4_4 = 0x13,
+ FMT_8_24 = 0x14,
+ FMT_24_8 = 0x15,
+ FMT_X24_8_32_FLOAT = 0x16,
+ FMT_RESERVED_33 = 0x17,
+ FMT_11_11_10_FLOAT = 0x18,
+ FMT_16_FLOAT = 0x19,
+ FMT_32_FLOAT = 0x1a,
+ FMT_16_16_FLOAT = 0x1b,
+ FMT_8_24_FLOAT = 0x1c,
+ FMT_24_8_FLOAT = 0x1d,
+ FMT_32_32_FLOAT = 0x1e,
+ FMT_10_11_11_FLOAT = 0x1f,
+ FMT_16_16_16_16_FLOAT = 0x20,
+ FMT_3_3_2 = 0x21,
+ FMT_6_5_5 = 0x22,
+ FMT_32_32_32_32_FLOAT = 0x23,
+ FMT_RESERVED_36 = 0x24,
+ FMT_1 = 0x25,
+ FMT_1_REVERSED = 0x26,
+ FMT_GB_GR = 0x27,
+ FMT_BG_RG = 0x28,
+ FMT_32_AS_8 = 0x29,
+ FMT_32_AS_8_8 = 0x2a,
+ FMT_5_9_9_9_SHAREDEXP = 0x2b,
+ FMT_8_8_8 = 0x2c,
+ FMT_16_16_16 = 0x2d,
+ FMT_16_16_16_FLOAT = 0x2e,
+ FMT_4_4 = 0x2f,
+ FMT_32_32_32_FLOAT = 0x30,
+ FMT_BC1 = 0x31,
+ FMT_BC2 = 0x32,
+ FMT_BC3 = 0x33,
+ FMT_BC4 = 0x34,
+ FMT_BC5 = 0x35,
+ FMT_BC6 = 0x36,
+ FMT_BC7 = 0x37,
+ FMT_32_AS_32_32_32_32 = 0x38,
+ FMT_APC3 = 0x39,
+ FMT_APC4 = 0x3a,
+ FMT_APC5 = 0x3b,
+ FMT_APC6 = 0x3c,
+ FMT_APC7 = 0x3d,
+ FMT_CTX1 = 0x3e,
+ FMT_RESERVED_63 = 0x3f,
+} SurfaceFormat;
+typedef enum BUF_DATA_FORMAT {
+ BUF_DATA_FORMAT_INVALID = 0x0,
+ BUF_DATA_FORMAT_8 = 0x1,
+ BUF_DATA_FORMAT_16 = 0x2,
+ BUF_DATA_FORMAT_8_8 = 0x3,
+ BUF_DATA_FORMAT_32 = 0x4,
+ BUF_DATA_FORMAT_16_16 = 0x5,
+ BUF_DATA_FORMAT_10_11_11 = 0x6,
+ BUF_DATA_FORMAT_11_11_10 = 0x7,
+ BUF_DATA_FORMAT_10_10_10_2 = 0x8,
+ BUF_DATA_FORMAT_2_10_10_10 = 0x9,
+ BUF_DATA_FORMAT_8_8_8_8 = 0xa,
+ BUF_DATA_FORMAT_32_32 = 0xb,
+ BUF_DATA_FORMAT_16_16_16_16 = 0xc,
+ BUF_DATA_FORMAT_32_32_32 = 0xd,
+ BUF_DATA_FORMAT_32_32_32_32 = 0xe,
+ BUF_DATA_FORMAT_RESERVED_15 = 0xf,
+} BUF_DATA_FORMAT;
+typedef enum IMG_DATA_FORMAT {
+ IMG_DATA_FORMAT_INVALID = 0x0,
+ IMG_DATA_FORMAT_8 = 0x1,
+ IMG_DATA_FORMAT_16 = 0x2,
+ IMG_DATA_FORMAT_8_8 = 0x3,
+ IMG_DATA_FORMAT_32 = 0x4,
+ IMG_DATA_FORMAT_16_16 = 0x5,
+ IMG_DATA_FORMAT_10_11_11 = 0x6,
+ IMG_DATA_FORMAT_11_11_10 = 0x7,
+ IMG_DATA_FORMAT_10_10_10_2 = 0x8,
+ IMG_DATA_FORMAT_2_10_10_10 = 0x9,
+ IMG_DATA_FORMAT_8_8_8_8 = 0xa,
+ IMG_DATA_FORMAT_32_32 = 0xb,
+ IMG_DATA_FORMAT_16_16_16_16 = 0xc,
+ IMG_DATA_FORMAT_32_32_32 = 0xd,
+ IMG_DATA_FORMAT_32_32_32_32 = 0xe,
+ IMG_DATA_FORMAT_RESERVED_15 = 0xf,
+ IMG_DATA_FORMAT_5_6_5 = 0x10,
+ IMG_DATA_FORMAT_1_5_5_5 = 0x11,
+ IMG_DATA_FORMAT_5_5_5_1 = 0x12,
+ IMG_DATA_FORMAT_4_4_4_4 = 0x13,
+ IMG_DATA_FORMAT_8_24 = 0x14,
+ IMG_DATA_FORMAT_24_8 = 0x15,
+ IMG_DATA_FORMAT_X24_8_32 = 0x16,
+ IMG_DATA_FORMAT_RESERVED_23 = 0x17,
+ IMG_DATA_FORMAT_RESERVED_24 = 0x18,
+ IMG_DATA_FORMAT_RESERVED_25 = 0x19,
+ IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
+ IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
+ IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
+ IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
+ IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
+ IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
+ IMG_DATA_FORMAT_GB_GR = 0x20,
+ IMG_DATA_FORMAT_BG_RG = 0x21,
+ IMG_DATA_FORMAT_5_9_9_9 = 0x22,
+ IMG_DATA_FORMAT_BC1 = 0x23,
+ IMG_DATA_FORMAT_BC2 = 0x24,
+ IMG_DATA_FORMAT_BC3 = 0x25,
+ IMG_DATA_FORMAT_BC4 = 0x26,
+ IMG_DATA_FORMAT_BC5 = 0x27,
+ IMG_DATA_FORMAT_BC6 = 0x28,
+ IMG_DATA_FORMAT_BC7 = 0x29,
+ IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
+ IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
+ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
+ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
+ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
+ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
+ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
+ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
+ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
+ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
+ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
+ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
+ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
+ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
+ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
+ IMG_DATA_FORMAT_4_4 = 0x39,
+ IMG_DATA_FORMAT_6_5_5 = 0x3a,
+ IMG_DATA_FORMAT_1 = 0x3b,
+ IMG_DATA_FORMAT_1_REVERSED = 0x3c,
+ IMG_DATA_FORMAT_32_AS_8 = 0x3d,
+ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
+ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
+} IMG_DATA_FORMAT;
+typedef enum BUF_NUM_FORMAT {
+ BUF_NUM_FORMAT_UNORM = 0x0,
+ BUF_NUM_FORMAT_SNORM = 0x1,
+ BUF_NUM_FORMAT_USCALED = 0x2,
+ BUF_NUM_FORMAT_SSCALED = 0x3,
+ BUF_NUM_FORMAT_UINT = 0x4,
+ BUF_NUM_FORMAT_SINT = 0x5,
+ BUF_NUM_FORMAT_RESERVED_6 = 0x6,
+ BUF_NUM_FORMAT_FLOAT = 0x7,
+} BUF_NUM_FORMAT;
+typedef enum IMG_NUM_FORMAT {
+ IMG_NUM_FORMAT_UNORM = 0x0,
+ IMG_NUM_FORMAT_SNORM = 0x1,
+ IMG_NUM_FORMAT_USCALED = 0x2,
+ IMG_NUM_FORMAT_SSCALED = 0x3,
+ IMG_NUM_FORMAT_UINT = 0x4,
+ IMG_NUM_FORMAT_SINT = 0x5,
+ IMG_NUM_FORMAT_RESERVED_6 = 0x6,
+ IMG_NUM_FORMAT_FLOAT = 0x7,
+ IMG_NUM_FORMAT_RESERVED_8 = 0x8,
+ IMG_NUM_FORMAT_SRGB = 0x9,
+ IMG_NUM_FORMAT_RESERVED_10 = 0xa,
+ IMG_NUM_FORMAT_RESERVED_11 = 0xb,
+ IMG_NUM_FORMAT_RESERVED_12 = 0xc,
+ IMG_NUM_FORMAT_RESERVED_13 = 0xd,
+ IMG_NUM_FORMAT_RESERVED_14 = 0xe,
+ IMG_NUM_FORMAT_RESERVED_15 = 0xf,
+} IMG_NUM_FORMAT;
+typedef enum TileType {
+ ARRAY_COLOR_TILE = 0x0,
+ ARRAY_DEPTH_TILE = 0x1,
+} TileType;
+typedef enum NonDispTilingOrder {
+ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
+ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
+} NonDispTilingOrder;
+typedef enum MicroTileMode {
+ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
+ ADDR_SURF_THIN_MICRO_TILING = 0x1,
+ ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
+ ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
+ ADDR_SURF_THICK_MICRO_TILING = 0x4,
+} MicroTileMode;
+typedef enum TileSplit {
+ ADDR_SURF_TILE_SPLIT_64B = 0x0,
+ ADDR_SURF_TILE_SPLIT_128B = 0x1,
+ ADDR_SURF_TILE_SPLIT_256B = 0x2,
+ ADDR_SURF_TILE_SPLIT_512B = 0x3,
+ ADDR_SURF_TILE_SPLIT_1KB = 0x4,
+ ADDR_SURF_TILE_SPLIT_2KB = 0x5,
+ ADDR_SURF_TILE_SPLIT_4KB = 0x6,
+} TileSplit;
+typedef enum SampleSplit {
+ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
+ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
+ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
+ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
+} SampleSplit;
+typedef enum PipeConfig {
+ ADDR_SURF_P2 = 0x0,
+ ADDR_SURF_P2_RESERVED0 = 0x1,
+ ADDR_SURF_P2_RESERVED1 = 0x2,
+ ADDR_SURF_P2_RESERVED2 = 0x3,
+ ADDR_SURF_P4_8x16 = 0x4,
+ ADDR_SURF_P4_16x16 = 0x5,
+ ADDR_SURF_P4_16x32 = 0x6,
+ ADDR_SURF_P4_32x32 = 0x7,
+ ADDR_SURF_P8_16x16_8x16 = 0x8,
+ ADDR_SURF_P8_16x32_8x16 = 0x9,
+ ADDR_SURF_P8_32x32_8x16 = 0xa,
+ ADDR_SURF_P8_16x32_16x16 = 0xb,
+ ADDR_SURF_P8_32x32_16x16 = 0xc,
+ ADDR_SURF_P8_32x32_16x32 = 0xd,
+ ADDR_SURF_P8_32x64_32x32 = 0xe,
+ ADDR_SURF_P8_RESERVED0 = 0xf,
+ ADDR_SURF_P16_32x32_8x16 = 0x10,
+ ADDR_SURF_P16_32x32_16x16 = 0x11,
+} PipeConfig;
+typedef enum NumBanks {
+ ADDR_SURF_2_BANK = 0x0,
+ ADDR_SURF_4_BANK = 0x1,
+ ADDR_SURF_8_BANK = 0x2,
+ ADDR_SURF_16_BANK = 0x3,
+} NumBanks;
+typedef enum BankWidth {
+ ADDR_SURF_BANK_WIDTH_1 = 0x0,
+ ADDR_SURF_BANK_WIDTH_2 = 0x1,
+ ADDR_SURF_BANK_WIDTH_4 = 0x2,
+ ADDR_SURF_BANK_WIDTH_8 = 0x3,
+} BankWidth;
+typedef enum BankHeight {
+ ADDR_SURF_BANK_HEIGHT_1 = 0x0,
+ ADDR_SURF_BANK_HEIGHT_2 = 0x1,
+ ADDR_SURF_BANK_HEIGHT_4 = 0x2,
+ ADDR_SURF_BANK_HEIGHT_8 = 0x3,
+} BankHeight;
+typedef enum BankWidthHeight {
+ ADDR_SURF_BANK_WH_1 = 0x0,
+ ADDR_SURF_BANK_WH_2 = 0x1,
+ ADDR_SURF_BANK_WH_4 = 0x2,
+ ADDR_SURF_BANK_WH_8 = 0x3,
+} BankWidthHeight;
+typedef enum MacroTileAspect {
+ ADDR_SURF_MACRO_ASPECT_1 = 0x0,
+ ADDR_SURF_MACRO_ASPECT_2 = 0x1,
+ ADDR_SURF_MACRO_ASPECT_4 = 0x2,
+ ADDR_SURF_MACRO_ASPECT_8 = 0x3,
+} MacroTileAspect;
+typedef enum GATCL1RequestType {
+ GATCL1_TYPE_NORMAL = 0x0,
+ GATCL1_TYPE_SHOOTDOWN = 0x1,
+ GATCL1_TYPE_BYPASS = 0x2,
+} GATCL1RequestType;
+typedef enum TCC_CACHE_POLICIES {
+ TCC_CACHE_POLICY_LRU = 0x0,
+ TCC_CACHE_POLICY_STREAM = 0x1,
+} TCC_CACHE_POLICIES;
+typedef enum MTYPE {
+ MTYPE_NC_NV = 0x0,
+ MTYPE_NC = 0x1,
+ MTYPE_CC = 0x2,
+ MTYPE_UC = 0x3,
+} MTYPE;
+typedef enum PERFMON_COUNTER_MODE {
+ PERFMON_COUNTER_MODE_ACCUM = 0x0,
+ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
+ PERFMON_COUNTER_MODE_MAX = 0x2,
+ PERFMON_COUNTER_MODE_DIRTY = 0x3,
+ PERFMON_COUNTER_MODE_SAMPLE = 0x4,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
+ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
+ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
+ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
+ PERFMON_COUNTER_MODE_RESERVED = 0xf,
+} PERFMON_COUNTER_MODE;
+typedef enum PERFMON_SPM_MODE {
+ PERFMON_SPM_MODE_OFF = 0x0,
+ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
+ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
+ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
+ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
+ PERFMON_SPM_MODE_RESERVED_5 = 0x5,
+ PERFMON_SPM_MODE_RESERVED_6 = 0x6,
+ PERFMON_SPM_MODE_RESERVED_7 = 0x7,
+ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
+ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
+ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
+} PERFMON_SPM_MODE;
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0x0,
+ ARRAY_TILED = 0x1,
+} SurfaceTiling;
+typedef enum SurfaceArray {
+ ARRAY_1D = 0x0,
+ ARRAY_2D = 0x1,
+ ARRAY_3D = 0x2,
+ ARRAY_3D_SLICE = 0x3,
+} SurfaceArray;
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0x0,
+ ARRAY_2D_COLOR = 0x1,
+ ARRAY_3D_SLICE_COLOR = 0x3,
+} ColorArray;
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0x0,
+ ARRAY_2D_DEPTH = 0x1,
+} DepthArray;
+typedef enum ENUM_NUM_SIMD_PER_CU {
+ NUM_SIMD_PER_CU = 0x4,
+} ENUM_NUM_SIMD_PER_CU;
+typedef enum MEM_PWR_FORCE_CTRL {
+ NO_FORCE_REQUEST = 0x0,
+ FORCE_LIGHT_SLEEP_REQUEST = 0x1,
+ FORCE_DEEP_SLEEP_REQUEST = 0x2,
+ FORCE_SHUT_DOWN_REQUEST = 0x3,
+} MEM_PWR_FORCE_CTRL;
+typedef enum MEM_PWR_FORCE_CTRL2 {
+ NO_FORCE_REQ = 0x0,
+ FORCE_LIGHT_SLEEP_REQ = 0x1,
+} MEM_PWR_FORCE_CTRL2;
+typedef enum MEM_PWR_DIS_CTRL {
+ ENABLE_MEM_PWR_CTRL = 0x0,
+ DISABLE_MEM_PWR_CTRL = 0x1,
+} MEM_PWR_DIS_CTRL;
+typedef enum MEM_PWR_SEL_CTRL {
+ DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
+ DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
+ DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
+} MEM_PWR_SEL_CTRL;
+typedef enum MEM_PWR_SEL_CTRL2 {
+ DYNAMIC_DEEP_SLEEP_EN = 0x0,
+ DYNAMIC_LIGHT_SLEEP_EN = 0x1,
+} MEM_PWR_SEL_CTRL2;
+
+#endif /* DCE_10_0_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h
new file mode 100644
index 000000000000..8a75eb9d732b
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h
@@ -0,0 +1,16647 @@
+/*
+ * DCE_10_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef DCE_10_0_SH_MASK_H
+#define DCE_10_0_SH_MASK_H
+
+#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
+#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
+#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
+#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
+#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
+#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
+#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
+#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
+#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
+#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
+#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000
+#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT 0x1d
+#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xc0000000
+#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x1
+#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x0
+#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x1
+#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x0
+#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK 0xffffff
+#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT 0x0
+#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS_MASK 0x3000000
+#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS__SHIFT 0x18
+#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000
+#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x1c
+#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK 0x20000000
+#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x1d
+#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xc0000000
+#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x1
+#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x0
+#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x1
+#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x0
+#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK 0xffffff
+#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT 0x0
+#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS_MASK 0x3000000
+#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS__SHIFT 0x18
+#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000
+#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x1c
+#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK 0x20000000
+#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT 0x1d
+#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xc0000000
+#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x1
+#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT 0x0
+#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x1
+#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT 0x0
+#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA_MASK 0xffffff
+#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA__SHIFT 0x0
+#define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS_MASK 0x3000000
+#define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS__SHIFT 0x18
+#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK 0x10000000
+#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT 0x1c
+#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE_MASK 0x20000000
+#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE__SHIFT 0x1d
+#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK 0xc0000000
+#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x1
+#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT 0x0
+#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x1
+#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT 0x0
+#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA_MASK 0xffffff
+#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA__SHIFT 0x0
+#define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS_MASK 0x3000000
+#define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS__SHIFT 0x18
+#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK 0x10000000
+#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x1c
+#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE_MASK 0x20000000
+#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE__SHIFT 0x1d
+#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK 0xc0000000
+#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK 0x1
+#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT 0x0
+#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK 0x1
+#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT 0x0
+#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA_MASK 0xffffff
+#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA__SHIFT 0x0
+#define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS_MASK 0x3000000
+#define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS__SHIFT 0x18
+#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000
+#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT 0x1c
+#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK 0x20000000
+#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE__SHIFT 0x1d
+#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xc0000000
+#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x1
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0
+#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK 0xffffffff
+#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT 0x0
+#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK 0xffffffff
+#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT 0x0
+#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK 0x1
+#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT 0x0
+#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x2
+#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT 0x1
+#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK 0x4
+#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x2
+#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK 0xffff0000
+#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x10
+#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK 0xff
+#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT 0x0
+#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x1ffff
+#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0
+#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x1ffff
+#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0
+#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x1ffff
+#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0
+#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x1ffff
+#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0
+#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x1ffff
+#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0
+#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x1ffff
+#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0
+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x1
+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0
+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x2
+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x4
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x8
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xffff0000
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x1
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x1
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x100
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x10000
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0xe0000
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x1000000
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f
+#define DC_ABM1_CNTL__ABM1_EN_MASK 0x1
+#define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0
+#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x700
+#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8
+#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000
+#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x1f
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0xf
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0xf00
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0xf0000
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x7fff
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x7ff0000
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x7fff
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x7ff0000
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x7fff
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x7ff0000
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x7fff
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x7ff0000
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x7fff
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x7ff0000
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x3ff
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x3ff0000
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x3ff
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x3ff0000
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x1
+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0
+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x100
+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8
+#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK 0x1
+#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT 0x0
+#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x100
+#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x8
+#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK 0x10000
+#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT 0x10
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x1
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x2
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x4
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x100
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x200
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x400
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x10000
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x1000000
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x3
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x100
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x1000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x30000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10
+#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x100000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x800000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x7000000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xffffffff
+#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0
+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x3ff
+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0
+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x3ff0000
+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10
+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x3ff
+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0
+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x3ff0000
+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10
+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0xffffff
+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0
+#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0xffffff
+#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x0
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x3ff
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x3ff0000
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0xffffff
+#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0
+#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0xffffff
+#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x1
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x1
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xffffffff
+#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0
+#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xffffffff
+#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0
+#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xffffffff
+#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0
+#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xffffffff
+#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0
+#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xffffffff
+#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x3ff
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x0
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0xffc00
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0xa
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3ff00000
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x14
+#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000
+#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f
+#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0xff
+#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x0
+#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffff
+#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x0
+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x10
+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE_MASK 0x100
+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE_MASK 0x1000
+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL_MASK 0x1f000000
+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL__SHIFT 0x18
+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE_MASK 0x80000000
+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE__SHIFT 0x1f
+#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x3ff
+#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
+#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x10000
+#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
+#define DCFE_DBG_SEL__DCFE_DBG_SEL_MASK 0xf
+#define DCFE_DBG_SEL__DCFE_DBG_SEL__SHIFT 0x0
+#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x3
+#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0
+#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x4
+#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2
+#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x18
+#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3
+#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x20
+#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5
+#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0xc0
+#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6
+#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x100
+#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8
+#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x600
+#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9
+#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x800
+#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb
+#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x3000
+#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc
+#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x4000
+#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe
+#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x18000
+#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf
+#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x20000
+#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11
+#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0xc0000
+#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12
+#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x100000
+#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14
+#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x600000
+#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15
+#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x800000
+#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17
+#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x3000000
+#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18
+#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x4000000
+#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a
+#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000
+#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b
+#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000
+#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d
+#define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x3
+#define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0
+#define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0xc
+#define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
+#define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x30
+#define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0xc0
+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6
+#define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x300
+#define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8
+#define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0xc00
+#define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa
+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x3000
+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc
+#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0xc000
+#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe
+#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x30000
+#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10
+#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x40000
+#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12
+#define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_FORCE_MASK 0x80000
+#define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_FORCE__SHIFT 0x13
+#define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_DIS_MASK 0x100000
+#define DCFE_MEM_PWR_CTRL2__OVLSCL_MEM_PWR_DIS__SHIFT 0x14
+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x600000
+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15
+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x800000
+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17
+#define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x3
+#define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0
+#define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0xc
+#define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2
+#define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x30
+#define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4
+#define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0xc0
+#define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6
+#define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x300
+#define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8
+#define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0xc00
+#define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa
+#define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x3000
+#define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc
+#define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0xc000
+#define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe
+#define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x30000
+#define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
+#define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0xc0000
+#define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12
+#define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x300000
+#define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14
+#define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0xc00000
+#define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16
+#define DCFE_MEM_PWR_STATUS__OVLSCL_MEM_PWR_STATE_MASK 0x1000000
+#define DCFE_MEM_PWR_STATUS__OVLSCL_MEM_PWR_STATE__SHIFT 0x18
+#define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x3fff
+#define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
+#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x3fff
+#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
+#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3fff0000
+#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
+#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x3fff
+#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
+#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3fff0000
+#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
+#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x1
+#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
+#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x10000
+#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
+#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x20000
+#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
+#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x3fff
+#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
+#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3fff0000
+#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
+#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x1
+#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
+#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x10000
+#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
+#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x20000
+#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
+#define CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x3fff
+#define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
+#define CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3fff0000
+#define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
+#define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x3fff
+#define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
+#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x3fff
+#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
+#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x3fff
+#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
+#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x10000
+#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
+#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x1
+#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
+#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x10
+#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
+#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100
+#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
+#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x1000
+#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
+#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x8000
+#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
+#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000
+#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x1
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x10
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x100
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x1000
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x1
+#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
+#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x10
+#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x3fff
+#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
+#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3fff0000
+#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
+#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x3fff
+#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
+#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3fff0000
+#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
+#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x1
+#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
+#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x3fff
+#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
+#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3fff0000
+#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
+#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x1
+#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
+#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x1
+#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
+#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x1e
+#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
+#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x3fff
+#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
+#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3fff0000
+#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x1f
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0xe0
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x100
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x400
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x3000
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x30000
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x300000
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
+#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x1
+#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x1f
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0xe0
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x100
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x400
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x3000
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x30000
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x300000
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
+#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x1
+#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x3
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x10
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x100
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x10000
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x1000000
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x1f
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x100
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x10000
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x1000000
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x3
+#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0xff00
+#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1fff0000
+#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
+#define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xffffffff
+#define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
+#define CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x1
+#define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x10
+#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
+#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x300
+#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
+#define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000
+#define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
+#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x2000
+#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
+#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x4000
+#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
+#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x10000
+#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x700000
+#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
+#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x1000000
+#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x18
+#define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000
+#define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
+#define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000
+#define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+#define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000
+#define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x1
+#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
+#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x100
+#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
+#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x10000
+#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
+#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x1
+#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
+#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x30000
+#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x1
+#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x2
+#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
+#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x1
+#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
+#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x2
+#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
+#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0xfff
+#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0xfff0000
+#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0xfff
+#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
+#define CRTC_STATUS__CRTC_V_BLANK_MASK 0x1
+#define CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
+#define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x2
+#define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
+#define CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x4
+#define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
+#define CRTC_STATUS__CRTC_V_UPDATE_MASK 0x8
+#define CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
+#define CRTC_STATUS__CRTC_V_START_LINE_MASK 0x10
+#define CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
+#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x20
+#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+#define CRTC_STATUS__CRTC_H_BLANK_MASK 0x10000
+#define CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
+#define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x20000
+#define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
+#define CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x40000
+#define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
+#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x3fff
+#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
+#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3fff0000
+#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
+#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x3fff
+#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
+#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0xffffff
+#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
+#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3fffffff
+#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
+#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3fffffff
+#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
+#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x1
+#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
+#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x1e
+#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
+#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x1
+#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
+#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x1
+#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x1
+#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x100
+#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x30000
+#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x1
+#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
+#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x100
+#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
+#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x10000
+#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
+#define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x100000
+#define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
+#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x3000000
+#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x3fff
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x8000
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x10000
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x20000
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+#define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x40000
+#define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+#define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x80000
+#define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
+#define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x100000
+#define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x1000000
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x1
+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x2
+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x4
+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x3
+#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x3fff
+#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3fff0000
+#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0xffffff
+#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x1
+#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
+#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x100
+#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x8
+#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0xff000
+#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
+#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100000
+#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x14
+#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x10000000
+#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x1c
+#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x1
+#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
+#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x2
+#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
+#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x10
+#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
+#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x20
+#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x100
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x10000
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x20000
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x1000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x2000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x4000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x8000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
+#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x1
+#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x1
+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x100
+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x10000
+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x1
+#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x1
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x700
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x10000
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0xf
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0xf0
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0xf00
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0xf000
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
+#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0xffff
+#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
+#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x3f0000
+#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
+#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x1
+#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
+#define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x100
+#define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
+#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x7
+#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
+#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x30000
+#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
+#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x3
+#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
+#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00
+#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
+#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0xff
+#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
+#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x1
+#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
+#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x10
+#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
+#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x10000
+#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
+#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x100000
+#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
+#define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x1
+#define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0xff
+#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
+#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x10000
+#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
+#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x1
+#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
+#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x100
+#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x3ff
+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0xffc00
+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000
+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x3
+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x300
+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x30000
+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x3ff
+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0xffc00
+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000
+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x3
+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x300
+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x30000
+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x3ff
+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0xffc00
+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000
+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x3
+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x300
+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x30000
+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x3fff
+#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3fff0000
+#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x10
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x100
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x1000
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x10000
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x100000
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x1000000
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x3fff
+#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x100
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x1000
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x10000
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x100000
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x1000000
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x3fff
+#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x100
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x1000
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x10000
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x100000
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x1000000
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+#define CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x1
+#define CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
+#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x10
+#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
+#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x300
+#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
+#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x3000
+#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
+#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000
+#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x700000
+#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
+#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x7000000
+#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
+#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x3fff
+#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
+#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3fff0000
+#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
+#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x3fff
+#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
+#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3fff0000
+#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
+#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x3fff
+#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
+#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3fff0000
+#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
+#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x3fff
+#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
+#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3fff0000
+#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
+#define CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0xffff
+#define CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+#define CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xffff0000
+#define CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+#define CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0xffff
+#define CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x3fff
+#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
+#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3fff0000
+#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
+#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x3fff
+#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
+#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3fff0000
+#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
+#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x3fff
+#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
+#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3fff0000
+#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
+#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x3fff
+#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
+#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3fff0000
+#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
+#define CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0xffff
+#define CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+#define CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xffff0000
+#define CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+#define CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0xffff
+#define CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x3
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x8
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x10
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x60
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x100
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x200
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x1000
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x2000
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x4000
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x7000000
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
+#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x3fff
+#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
+#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x3fff0000
+#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
+#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x3fff
+#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
+#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x3fff0000
+#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x1
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x10
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x100
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x10000
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x100000
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xe0000000
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x1
+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x10
+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x100
+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x10000
+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x100000
+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x1
+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x10
+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x100
+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x10000
+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x100000
+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0xffff
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0xff0000
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x1000000
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x2000000
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x4000000
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x8000000
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x1
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x10
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x300
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x1000
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x10000
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x20000
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0xc0000
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0xff
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0xff00
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x10000
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x60000
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x80000
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x100000
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x800000
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
+#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x3fff
+#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
+#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3fff0000
+#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
+#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x3fff
+#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
+#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x1f0000
+#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
+#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000
+#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0xff
+#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x0
+#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffff
+#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x0
+#define DAC_ENABLE__DAC_ENABLE_MASK 0x1
+#define DAC_ENABLE__DAC_ENABLE__SHIFT 0x0
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x2
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x1
+#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0xc
+#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x2
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x10
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x4
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x20
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x5
+#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x100
+#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x8
+#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x7
+#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x0
+#define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x8
+#define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x3
+#define DAC_CRC_EN__DAC_CRC_EN_MASK 0x1
+#define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x0
+#define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x10000
+#define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x10
+#define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x1
+#define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x0
+#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB_MASK 0x100
+#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB__SHIFT 0x8
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x3ff
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x0
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0xffc00
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0xa
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3ff00000
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x14
+#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x3f
+#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x0
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x3ff
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x0
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0xffc00
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0xa
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3ff00000
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x14
+#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x3f
+#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x0
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x1
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x0
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x100
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x8
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x10000
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x10
+#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x7
+#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x0
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x3
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x0
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0xff00
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x8
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x70000
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x10
+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0xff
+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x0
+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x100
+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x8
+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0xff
+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x0
+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0xff00
+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x8
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x1
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x0
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x10
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x4
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x300
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x8
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x30000
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x10
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x3000000
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x18
+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x1
+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x0
+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x10000
+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x10
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x1
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x0
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x700
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x8
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY_MASK 0x1000000
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY__SHIFT 0x18
+#define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x3ff
+#define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x0
+#define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x1
+#define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x0
+#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x100
+#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x8
+#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x10000
+#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x10
+#define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x1000000
+#define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x18
+#define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x1
+#define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x0
+#define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x100
+#define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x8
+#define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x10000
+#define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x10
+#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x1
+#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x0
+#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x100
+#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x8
+#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x10000
+#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x10
+#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x20000
+#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x11
+#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x40000
+#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x12
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x1
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x0
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x2
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x1
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x4
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x2
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x8
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x3
+#define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x3
+#define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x0
+#define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x30000
+#define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x10
+#define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xffffffff
+#define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x0
+#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
+#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0xfc
+#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00
+#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0xf0000
+#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x3c00000
+#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000
+#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x1d
+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000
+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000
+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX_MASK 0xff
+#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA__SHIFT 0x0
+#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x1ff
+#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0xe00
+#define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x3000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x4000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xe
+#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x8000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0xf
+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x1f0000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x10
+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x200000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x15
+#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x400000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x16
+#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x800000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x17
+#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x1000000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x18
+#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x2000000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x19
+#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x4000000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1a
+#define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x8000000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x1b
+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xe0000000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x3
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x4
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x30
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x40
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x300
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x400
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x3000
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x4000
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x30000
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x40000
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x300000
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x400000
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x3000000
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x4000000
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define PERFMON_CNTL__PERFMON_STATE_MASK 0x3
+#define PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL_MASK 0xfc
+#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL__SHIFT 0x2
+#define PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0xfffff00
+#define PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000
+#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000
+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000
+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000
+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x1
+#define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x1
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x2
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x4
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x8
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x10
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x20
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x40
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x80
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x100
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x200
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x400
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x800
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x1000
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x2000
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x4000
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x8000
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xffff0000
+#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xffffffff
+#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define PERFMON_HI__PERFMON_HI_MASK 0xffff
+#define PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define PERFMON_HI__PERFMON_READ_SEL_MASK 0xe0000000
+#define PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define PERFMON_LOW__PERFMON_LOW_MASK 0xffffffff
+#define PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX_MASK 0xff
+#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX__SHIFT 0x0
+#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA_MASK 0xffffffff
+#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA__SHIFT 0x0
+#define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK 0x1
+#define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT 0x0
+#define REFCLK_CNTL__REFCLK_SRC_SEL_MASK 0x2
+#define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT 0x1
+#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY_MASK 0xf
+#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY__SHIFT 0x0
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x7
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0
+#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE_MASK 0x100
+#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE__SHIFT 0x8
+#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE_MASK 0xffffffff
+#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE__SHIFT 0x0
+#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE_MASK 0x1
+#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE__SHIFT 0x0
+#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE_MASK 0xffffffff
+#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE__SHIFT 0x0
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x1
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xffffffff
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xffffffff
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xffffffff
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xffffffff
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xffffffff
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x1
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x100
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x200
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x30000
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x1000000
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x2000000
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xffffffff
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE_MASK 0x1
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE__SHIFT 0x0
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE_MASK 0x1ff0
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE__SHIFT 0x4
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED_MASK 0x10000
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED__SHIFT 0x10
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR_MASK 0x20000
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR__SHIFT 0x11
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE_MASK 0x100000
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE__SHIFT 0x14
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL_MASK 0x200000
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL__SHIFT 0x15
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_MASK 0xff000000
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT__SHIFT 0x18
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x1
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xffff0000
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10
+#define SMU_CONTROL__DISPLAY0_FORCE_VBI_MASK 0x1
+#define SMU_CONTROL__DISPLAY0_FORCE_VBI__SHIFT 0x0
+#define SMU_CONTROL__DISPLAY1_FORCE_VBI_MASK 0x2
+#define SMU_CONTROL__DISPLAY1_FORCE_VBI__SHIFT 0x1
+#define SMU_CONTROL__DISPLAY2_FORCE_VBI_MASK 0x4
+#define SMU_CONTROL__DISPLAY2_FORCE_VBI__SHIFT 0x2
+#define SMU_CONTROL__DISPLAY3_FORCE_VBI_MASK 0x8
+#define SMU_CONTROL__DISPLAY3_FORCE_VBI__SHIFT 0x3
+#define SMU_CONTROL__DISPLAY4_FORCE_VBI_MASK 0x10
+#define SMU_CONTROL__DISPLAY4_FORCE_VBI__SHIFT 0x4
+#define SMU_CONTROL__DISPLAY5_FORCE_VBI_MASK 0x20
+#define SMU_CONTROL__DISPLAY5_FORCE_VBI__SHIFT 0x5
+#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI_MASK 0x40
+#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI__SHIFT 0x6
+#define SMU_CONTROL__SMU_DC_INT_CLEAR_MASK 0x10000
+#define SMU_CONTROL__SMU_DC_INT_CLEAR__SHIFT 0x10
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x1
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x10
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10
+#define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x1
+#define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x0
+#define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x10
+#define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x4
+#define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x1
+#define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x0
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x1
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x2
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1
+#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x4
+#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x2
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x8
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x10
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4
+#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x20
+#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x5
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x40
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6
+#define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE_MASK 0x80
+#define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE__SHIFT 0x7
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x100
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8
+#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE_MASK 0x10000
+#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE__SHIFT 0x10
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x20000
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x40000
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x80000
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE_MASK 0x100000
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE__SHIFT 0x14
+#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x200000
+#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x400000
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16
+#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE_MASK 0x800000
+#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE__SHIFT 0x17
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x4000000
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x8000000
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0xf
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0xff0
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE_MASK 0x1000
+#define DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE__SHIFT 0xc
+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0xf
+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x0
+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0xff0
+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE_MASK 0x1000
+#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE__SHIFT 0xc
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0xf
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0xff0
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0xf
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0xff0
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xffffffff
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0
+#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x1
+#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x0
+#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x30
+#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x4
+#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x1
+#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x0
+#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x30
+#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x4
+#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x1
+#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x0
+#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x30
+#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x4
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x7f
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x7f00
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x10000
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x20000
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x100
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x1ffff
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x3fff
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0xf0000
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x100000
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0xe000000
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x1
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x1
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x2
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x4
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x8
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x10
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4
+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x20
+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x40
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x80
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7
+#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x700
+#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x8
+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xfffff800
+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK 0x1
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT 0x0
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK 0x2
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT 0x1
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x3
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x10
+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4
+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x20
+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x100
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x8
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x200
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x9
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0xc000
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0xfff0000
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xffffffff
+#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0
+#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xffffffff
+#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x3
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x10
+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4
+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x20
+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x100
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x8
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x200
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x9
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0xc000
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0xfff0000
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xffffffff
+#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0
+#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xffffffff
+#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x3
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x10
+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4
+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x20
+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x100
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x8
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x200
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x9
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0xc000
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0xfff0000
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xffffffff
+#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0
+#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xffffffff
+#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x3
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x10
+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4
+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x20
+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x100
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x8
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x200
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x9
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0xc000
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0xfff0000
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xffffffff
+#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0
+#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xffffffff
+#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x3
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x10
+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x4
+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK 0x20
+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT 0x5
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x100
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x8
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x200
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x9
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0xc000
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0xfff0000
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xffffffff
+#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x0
+#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xffffffff
+#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x0
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x3
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x10
+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x4
+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK 0x20
+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT 0x5
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x100
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x8
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x200
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x9
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0xc000
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0xfff0000
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xffffffff
+#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x0
+#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xffffffff
+#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x0
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x1
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0
+#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK 0x2
+#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT 0x1
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x4
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x8
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x10
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x100
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x1000
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x2000
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x4000
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x8000
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x10000
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x20000
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x40000
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x80000
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x100000
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x200000
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x1
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x10
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x700
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x1
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x10
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x700
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x1
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x10
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x700
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x1
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x10
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x700
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x1
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x10
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x700
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x1
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x10
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x700
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x8
+#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN_MASK 0x10
+#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN__SHIFT 0x4
+#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC_MASK 0x700
+#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC__SHIFT 0x8
+#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK 0x7
+#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT 0x0
+#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK 0x1f00
+#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT 0x8
+#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK 0x10000
+#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT 0x10
+#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK 0x20000
+#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT 0x11
+#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK 0x40000
+#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT 0x12
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK 0x7
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT 0x0
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK 0x1f00
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT 0x8
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK 0x10000
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT 0x10
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK 0x20000
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT 0x11
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK 0x40000
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT 0x12
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK 0x100000
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT 0x14
+#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL_MASK 0x3000000
+#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL__SHIFT 0x18
+#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL_MASK 0x30000000
+#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT 0x1c
+#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK 0x7
+#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT 0x0
+#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK 0x1f00
+#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT 0x8
+#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK 0x10000
+#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT 0x10
+#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK 0x20000
+#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT 0x11
+#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK 0x40000
+#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT 0x12
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x7
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x30
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x3000
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x10000
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x100000
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x1000000
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xffffffff
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xffffffff
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xffffffff
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xffffffff
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0
+#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK 0xff
+#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT 0x0
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x1ff
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x1000
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x1ff0000
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c
+#define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x7f
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x7f00
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x18000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x20000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x40000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x80000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x100000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x14
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x200000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x15
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x400000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x16
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7f000000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x18
+#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK 0xffffffff
+#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT 0x0
+#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK 0xffffffff
+#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT 0x0
+#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK 0xffffffff
+#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT 0x0
+#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK 0xffffffff
+#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT 0x0
+#define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL_MASK 0xffffffff
+#define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL__SHIFT 0x0
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK 0x1f
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT 0x0
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK 0x3e0
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT 0x5
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK 0x1000
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT 0xc
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK 0xf8000
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT 0xf
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK 0x1f00000
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT 0x14
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK 0x10000000
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT 0x1c
+#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK 0x1f
+#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT 0x0
+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL_MASK 0x800000
+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL__SHIFT 0x17
+#define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL_MASK 0x1f000000
+#define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL__SHIFT 0x18
+#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK 0xffffffff
+#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT 0x0
+#define DMIF_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define DMIF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define DMIF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define DMIF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x3
+#define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x0
+#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x4
+#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x2
+#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x10
+#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x4
+#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x700
+#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x8
+#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN_MASK 0x800
+#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN__SHIFT 0xb
+#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0xf000
+#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0xc
+#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x3f0000
+#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x10
+#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1f000000
+#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x18
+#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000
+#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x1d
+#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0xff
+#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x0
+#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0xff00
+#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x10000
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x10
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x20000
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x11
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0x700000
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x14
+#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0x7000000
+#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x18
+#define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000
+#define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x1c
+#define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK 0xffffffff
+#define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT 0x0
+#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0xffff
+#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x0
+#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xffff0000
+#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x10
+#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
+#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
+#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
+#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
+#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
+#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
+#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
+#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
+#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define DMIF_P_VMID__P_VMID_PIPE0_MASK 0xf
+#define DMIF_P_VMID__P_VMID_PIPE0__SHIFT 0x0
+#define DMIF_P_VMID__P_VMID_PIPE1_MASK 0xf0
+#define DMIF_P_VMID__P_VMID_PIPE1__SHIFT 0x4
+#define DMIF_P_VMID__P_VMID_PIPE2_MASK 0xf00
+#define DMIF_P_VMID__P_VMID_PIPE2__SHIFT 0x8
+#define DMIF_P_VMID__P_VMID_PIPE3_MASK 0xf000
+#define DMIF_P_VMID__P_VMID_PIPE3__SHIFT 0xc
+#define DMIF_P_VMID__P_VMID_PIPE4_MASK 0xf0000
+#define DMIF_P_VMID__P_VMID_PIPE4__SHIFT 0x10
+#define DMIF_P_VMID__P_VMID_PIPE5_MASK 0xf00000
+#define DMIF_P_VMID__P_VMID_PIPE5__SHIFT 0x14
+#define DMIF_P_VMID__P_VMID_PIPE6_MASK 0xf000000
+#define DMIF_P_VMID__P_VMID_PIPE6__SHIFT 0x18
+#define DMIF_P_VMID__P_VMID_PIPE7_MASK 0xf0000000
+#define DMIF_P_VMID__P_VMID_PIPE7__SHIFT 0x1c
+#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN_MASK 0x1
+#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN__SHIFT 0x0
+#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL_MASK 0xf0
+#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL__SHIFT 0x4
+#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK 0xff
+#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT 0x0
+#define DMIF_DEBUG02_CORE0__DB_DATA_MASK 0xffff
+#define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT 0x0
+#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK 0x10000
+#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT 0x10
+#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK 0xffe0000
+#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT 0x11
+#define DMIF_DEBUG02_CORE1__DB_DATA_MASK 0xffff
+#define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT 0x0
+#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK 0x10000
+#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT 0x10
+#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK 0xffe0000
+#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT 0x11
+#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000
+#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x1c
+#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x1
+#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x0
+#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x2
+#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x1
+#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x4
+#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x2
+#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x8
+#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x3
+#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x10
+#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x4
+#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x20
+#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x5
+#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x100
+#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x8
+#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x200
+#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x9
+#define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
+#define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
+#define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
+#define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
+#define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
+#define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
+#define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE6_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
+#define PIPE6_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE7_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
+#define PIPE7_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x1
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x0
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x18
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x3
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0xe0
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x5
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x700
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x8
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x800
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0xb
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x7000
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0xc
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0xfff0000
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x10
+#define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK 0x3
+#define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT 0x0
+#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x10
+#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x4
+#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x100
+#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x8
+#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK 0xf000
+#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT 0xc
+#define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK 0xff0000
+#define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x10
+#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK 0x3f000000
+#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT 0x18
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0xff
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0
+#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK 0xff00
+#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT 0x8
+#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK 0xff
+#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT 0x0
+#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK 0xffffffff
+#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT 0x0
+#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff
+#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0
+#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK 0xffffffff
+#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT 0x0
+#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK 0xffffffff
+#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT 0x0
+#define MCIF_VMID__MCIF_WR_VMID_MASK 0xf
+#define MCIF_VMID__MCIF_WR_VMID__SHIFT 0x0
+#define MCIF_VMID__VIP_WR_VMID_MASK 0xf0
+#define MCIF_VMID__VIP_WR_VMID__SHIFT 0x4
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK 0x1
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT 0x0
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK 0x30
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT 0x4
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK 0xff00
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT 0x8
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK 0x70000
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT 0x10
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK 0x180000
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT 0x13
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x7e
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x1
+#define CC_DC_PIPE_DIS__MCIF_WB_URG_OVRD_MASK 0x100
+#define CC_DC_PIPE_DIS__MCIF_WB_URG_OVRD__SHIFT 0x8
+#define CC_DC_PIPE_DIS__MCIF_WB_URG_LVL_MASK 0x1e00
+#define CC_DC_PIPE_DIS__MCIF_WB_URG_LVL__SHIFT 0x9
+#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK 0x1
+#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT 0x0
+#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK 0x10
+#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT 0x4
+#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK 0x100
+#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT 0x8
+#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK 0x1000
+#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT 0xc
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK 0x10000
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT 0x10
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK 0x100000
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT 0x14
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK 0x1000000
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT 0x18
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK 0x10000000
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT 0x1c
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0xfffff
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0
+#define RBBMIF_TIMEOUT__RBBMIF_ACK_HOLD_MASK 0xfff00000
+#define RBBMIF_TIMEOUT__RBBMIF_ACK_HOLD__SHIFT 0x14
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0x7fff
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f
+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x1
+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0
+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x2
+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1
+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x4
+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2
+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x8
+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3
+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x10
+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4
+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x20
+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5
+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x40
+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6
+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x80
+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7
+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x100
+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8
+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x200
+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9
+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x400
+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa
+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x800
+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb
+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x1000
+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc
+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x2000
+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd
+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x4000
+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe
+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x7
+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0
+#define RBBMIF_STATUS_FLAG__RBBMIF_ACK_TIMEOUT_MASK 0x8
+#define RBBMIF_STATUS_FLAG__RBBMIF_ACK_TIMEOUT__SHIFT 0x3
+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x10
+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x20
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x40
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6
+#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE_MASK 0x3
+#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE__SHIFT 0x0
+#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE_MASK 0xc
+#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE__SHIFT 0x2
+#define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE_MASK 0x10
+#define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE__SHIFT 0x4
+#define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE_MASK 0x40
+#define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE__SHIFT 0x6
+#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK 0x100
+#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT 0x8
+#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE_MASK 0x600
+#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE__SHIFT 0x9
+#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE_MASK 0x800
+#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xb
+#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE_MASK 0x3000
+#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE__SHIFT 0xc
+#define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE_MASK 0xc000
+#define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE__SHIFT 0xe
+#define DCI_MEM_PWR_STATUS__MCIF_DWB_MEM_PWR_STATE_MASK 0x30000
+#define DCI_MEM_PWR_STATUS__MCIF_DWB_MEM_PWR_STATE__SHIFT 0x10
+#define DCI_MEM_PWR_STATUS__MCIF_CWB0_MEM_PWR_STATE_MASK 0xc0000
+#define DCI_MEM_PWR_STATUS__MCIF_CWB0_MEM_PWR_STATE__SHIFT 0x12
+#define DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE_MASK 0x300000
+#define DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE__SHIFT 0x14
+#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE_MASK 0x400000
+#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE__SHIFT 0x16
+#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x3000000
+#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0x18
+#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE_MASK 0xc000000
+#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE__SHIFT 0x1a
+#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE_MASK 0x10000000
+#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE__SHIFT 0x1c
+#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0x3
+#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0
+#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE_MASK 0xc
+#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE__SHIFT 0x2
+#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE_MASK 0x10
+#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE__SHIFT 0x4
+#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x60
+#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x5
+#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE_MASK 0x180
+#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE__SHIFT 0x7
+#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE_MASK 0x200
+#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE__SHIFT 0x9
+#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0xc00
+#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0xa
+#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE_MASK 0x3000
+#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE__SHIFT 0xc
+#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE_MASK 0x4000
+#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE__SHIFT 0xe
+#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x18000
+#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0xf
+#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK 0x60000
+#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT 0x11
+#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE_MASK 0x80000
+#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE__SHIFT 0x13
+#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0x300000
+#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x14
+#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE_MASK 0xc00000
+#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE__SHIFT 0x16
+#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE_MASK 0x1000000
+#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE__SHIFT 0x18
+#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x1f
+#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x0
+#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x20
+#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x5
+#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x40
+#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x6
+#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x80
+#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x7
+#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x100
+#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8
+#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x200
+#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x9
+#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x800
+#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0xb
+#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x2000
+#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0xd
+#define DCI_CLK_CNTL__VPCLK_POL_MASK 0x4000
+#define DCI_CLK_CNTL__VPCLK_POL__SHIFT 0xe
+#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x8000
+#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0xf
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x10000
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x10
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x20000
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x11
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x40000
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x12
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x80000
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x13
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x100000
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x14
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x200000
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x15
+#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK 0x400000
+#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT 0x16
+#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK 0x800000
+#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x17
+#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x1000000
+#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x18
+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_L_GATE_DIS_MASK 0x2000000
+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_L_GATE_DIS__SHIFT 0x19
+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_C_GATE_DIS_MASK 0x4000000
+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_C_GATE_DIS__SHIFT 0x1a
+#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xf8000000
+#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x1b
+#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE_MASK 0x3
+#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x0
+#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS_MASK 0x4
+#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS__SHIFT 0x2
+#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE_MASK 0x8
+#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x3
+#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS_MASK 0x10
+#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS__SHIFT 0x4
+#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE_MASK 0x20
+#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE__SHIFT 0x5
+#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS_MASK 0x40
+#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS__SHIFT 0x6
+#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK 0x80
+#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT 0x7
+#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK 0x100
+#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT 0x8
+#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK 0x600
+#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT 0x9
+#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK 0x800
+#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT 0xb
+#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK 0x1000
+#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT 0xc
+#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK 0x2000
+#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT 0xd
+#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE_MASK 0xc000
+#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE__SHIFT 0xe
+#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS_MASK 0x10000
+#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS__SHIFT 0x10
+#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE_MASK 0x60000
+#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE__SHIFT 0x11
+#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS_MASK 0x80000
+#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS__SHIFT 0x13
+#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE_MASK 0x300000
+#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE__SHIFT 0x14
+#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS_MASK 0x400000
+#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS__SHIFT 0x16
+#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE_MASK 0x1800000
+#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE__SHIFT 0x17
+#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS_MASK 0x2000000
+#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS__SHIFT 0x19
+#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE_MASK 0xc000000
+#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE__SHIFT 0x1a
+#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS_MASK 0x10000000
+#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS__SHIFT 0x1c
+#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE_MASK 0x20000000
+#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE__SHIFT 0x1d
+#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS_MASK 0x40000000
+#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS__SHIFT 0x1e
+#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE_MASK 0x3
+#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE__SHIFT 0x0
+#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS_MASK 0x4
+#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS__SHIFT 0x2
+#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE_MASK 0x18
+#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE__SHIFT 0x3
+#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS_MASK 0x20
+#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS__SHIFT 0x5
+#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE_MASK 0x40
+#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE__SHIFT 0x6
+#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS_MASK 0x80
+#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS__SHIFT 0x7
+#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE_MASK 0x300
+#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE__SHIFT 0x8
+#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS_MASK 0x400
+#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS__SHIFT 0xa
+#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE_MASK 0x1800
+#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE__SHIFT 0xb
+#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS_MASK 0x2000
+#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS__SHIFT 0xd
+#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE_MASK 0x4000
+#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE__SHIFT 0xe
+#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS_MASK 0x8000
+#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS__SHIFT 0xf
+#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE_MASK 0x30000
+#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE__SHIFT 0x10
+#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS_MASK 0x40000
+#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS__SHIFT 0x12
+#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE_MASK 0x180000
+#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE__SHIFT 0x13
+#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS_MASK 0x200000
+#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS__SHIFT 0x15
+#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE_MASK 0x400000
+#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE__SHIFT 0x16
+#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS_MASK 0x800000
+#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS__SHIFT 0x17
+#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE_MASK 0x3000000
+#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE__SHIFT 0x18
+#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS_MASK 0x4000000
+#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS__SHIFT 0x1a
+#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE_MASK 0x18000000
+#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE__SHIFT 0x1b
+#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS_MASK 0x20000000
+#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS__SHIFT 0x1d
+#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE_MASK 0x40000000
+#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE__SHIFT 0x1e
+#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS_MASK 0x80000000
+#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS__SHIFT 0x1f
+#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE_MASK 0x3
+#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE__SHIFT 0x0
+#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS_MASK 0x4
+#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS__SHIFT 0x2
+#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE_MASK 0x18
+#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE__SHIFT 0x3
+#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS_MASK 0x20
+#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS__SHIFT 0x5
+#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE_MASK 0x40
+#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE__SHIFT 0x6
+#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS_MASK 0x80
+#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS__SHIFT 0x7
+#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE_MASK 0x300
+#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE__SHIFT 0x8
+#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS_MASK 0x400
+#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS__SHIFT 0xa
+#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE_MASK 0x1800
+#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE__SHIFT 0xb
+#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS_MASK 0x2000
+#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS__SHIFT 0xd
+#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE_MASK 0x4000
+#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE__SHIFT 0xe
+#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS_MASK 0x8000
+#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS__SHIFT 0xf
+#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL_MASK 0x30000
+#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL__SHIFT 0x10
+#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL_MASK 0xc0000
+#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL__SHIFT 0x12
+#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL_MASK 0x300000
+#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL__SHIFT 0x14
+#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x400000
+#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT 0x16
+#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL_MASK 0x1800000
+#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL__SHIFT 0x17
+#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL_MASK 0x6000000
+#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL__SHIFT 0x19
+#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL_MASK 0x18000000
+#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL__SHIFT 0x1b
+#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL_MASK 0x60000000
+#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL__SHIFT 0x1d
+#define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x1
+#define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0
+#define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x2
+#define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x1
+#define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x4
+#define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x2
+#define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x8
+#define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x3
+#define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x10
+#define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x4
+#define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x20
+#define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x5
+#define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x40
+#define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x6
+#define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x80
+#define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x7
+#define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x100
+#define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x8
+#define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x200
+#define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x9
+#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET_MASK 0x400
+#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET__SHIFT 0xa
+#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET_MASK 0x800
+#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET__SHIFT 0xb
+#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x1000
+#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0xc
+#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET_MASK 0x10000
+#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET__SHIFT 0x10
+#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET_MASK 0x20000
+#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET__SHIFT 0x11
+#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET_MASK 0x40000
+#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET__SHIFT 0x12
+#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK 0xff
+#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT 0x0
+#define DCI_DEBUG_CONFIG__DCI_DBG_EN_MASK 0x1
+#define DCI_DEBUG_CONFIG__DCI_DBG_EN__SHIFT 0x0
+#define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL_MASK 0xf0
+#define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL__SHIFT 0x4
+#define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL_MASK 0xf00
+#define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL__SHIFT 0x8
+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define DC_GENERICA__GENERICA_EN_MASK 0x1
+#define DC_GENERICA__GENERICA_EN__SHIFT 0x0
+#define DC_GENERICA__GENERICA_SEL_MASK 0xf80
+#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x7000
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x70000
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x700000
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x7000000
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18
+#define DC_GENERICB__GENERICB_EN_MASK 0x1
+#define DC_GENERICB__GENERICB_EN__SHIFT 0x0
+#define DC_GENERICB__GENERICB_SEL_MASK 0xf00
+#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x7000
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x70000
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x700000
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x7000000
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18
+#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0xf
+#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x0
+#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x30
+#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x4
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x3
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x300
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8
+#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x1
+#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x0
+#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x300
+#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x8
+#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x10000
+#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x10
+#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN_MASK 0x20000
+#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN__SHIFT 0x11
+#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE_MASK 0x80000000
+#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE__SHIFT 0x1f
+#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
+#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
+#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
+#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
+#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
+#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
+#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
+#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
+#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
+#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
+#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
+#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
+#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
+#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
+#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
+#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
+#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
+#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
+#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
+#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
+#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
+#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
+#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
+#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
+#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
+#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
+#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
+#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
+#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
+#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
+#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
+#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x1
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x100
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x200
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x400
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0xf0000
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0xf00000
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0xf000000
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x1e
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x1
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x100
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x200
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x400
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0xf0000
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0xf00000
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0xf000000
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x1e
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x1
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x100
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x200
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x400
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0xf0000
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0xf00000
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0xf000000
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x1e
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x1
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x100
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x200
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x400
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0xf0000
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0xf00000
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0xf000000
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x1e
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x1
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x100
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x200
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x400
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0xf0000
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0xf00000
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0xf000000
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x1e
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x1
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x100
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x200
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x400
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0xf0000
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0xf00000
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0xf000000
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x1e
+#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xffffffff
+#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x0
+#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x1
+#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x0
+#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x100
+#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x8
+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x200
+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x9
+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x400
+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0xa
+#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0xf0000
+#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x10
+#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0xf00000
+#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x14
+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0xf000000
+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x18
+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000
+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c
+#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x1
+#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x0
+#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x100
+#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x8
+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x200
+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x9
+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x400
+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0xa
+#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0xf0000
+#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x10
+#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0xf00000
+#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x14
+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0xf000000
+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x18
+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000
+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c
+#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE_MASK 0xf
+#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE__SHIFT 0x0
+#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET_MASK 0x20
+#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET__SHIFT 0x5
+#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS_MASK 0x300
+#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS__SHIFT 0x8
+#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE_MASK 0x7000
+#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE__SHIFT 0xc
+#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL_MASK 0x78000
+#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL__SHIFT 0xf
+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x7fff
+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x0
+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7fff0000
+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x10
+#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0xf
+#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x0
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x20
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x5
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x300
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x8
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x7000
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0xc
+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x7fff
+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x0
+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7fff0000
+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x10
+#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0xf
+#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x0
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x20
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x5
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x300
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x8
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x7000
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0xc
+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x7fff
+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x0
+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7fff0000
+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x10
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xf
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x0
+#define DCIO_WRCMD_DELAY__DAC_DELAY_MASK 0xf0
+#define DCIO_WRCMD_DELAY__DAC_DELAY__SHIFT 0x4
+#define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK 0xf00
+#define DCIO_WRCMD_DELAY__DPHY_DELAY__SHIFT 0x8
+#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK 0xf000
+#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT 0xc
+#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK 0x400
+#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT 0xa
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x2000
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0xc000
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x10000
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK 0xe0000
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT 0x11
+#define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x80000
+#define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x13
+#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x100000
+#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x14
+#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x200000
+#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x15
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x1
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x2
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x10
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x100
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x200
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x400
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x10000
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x20000
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x40000
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x1000000
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x2000000
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x4000000
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x1
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x2
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x4
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x8
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x10
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0xf00
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8
+#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0xfff
+#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0
+#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000
+#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0xff
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0xff00
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0xff0000
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xff000000
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0xff
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0xff00
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0xff0000
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x1000000
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18
+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0xffff
+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0
+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000
+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e
+#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000
+#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f
+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0xffff
+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0
+#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000
+#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x1c
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0xffff
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0xf0000
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x1
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x100
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x10000
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0xe0000
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x1000000
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x3
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x0
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x30
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x4
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x300
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x30000
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x10
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x300000
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x14
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x3000000
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x3
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x0
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x30
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x4
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x300
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x30000
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x10
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x300000
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x14
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x3000000
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18
+#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x7
+#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x0
+#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x700
+#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x8
+#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x70000
+#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x10
+#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x7
+#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x0
+#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x700
+#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x8
+#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x70000
+#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x10
+#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x7
+#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x0
+#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x700
+#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x8
+#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x70000
+#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x10
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x7
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x70
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x700
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x7000
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x70000
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x700000
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x7
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x0
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x70
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x4
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x700
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x8
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x7000
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0xc
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x70000
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x10
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x700000
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x14
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xffffffff
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x3f
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x700
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x3800
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x1c000
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0xe0000
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x700000
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x3800000
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x1f
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x20
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_RAMP_DIS_MASK 0x100
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_RAMP_DIS__SHIFT 0x8
+#define DCIO_DEBUG__DCIO_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x0
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX_MASK 0x7
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX__SHIFT 0x0
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX_MASK 0x70
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX__SHIFT 0x4
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX_MASK 0x700
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX__SHIFT 0x8
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX_MASK 0x7000
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX__SHIFT 0xc
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX_MASK 0x70000
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX__SHIFT 0x10
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX_MASK 0x700000
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX__SHIFT 0x14
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK_MASK 0x7000000
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT 0x18
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK_MASK 0x70000000
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK__SHIFT 0x1c
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL_MASK 0x80000000
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL__SHIFT 0x1f
+#define DBG_OUT_CNTL__DBG_OUT_PIN_EN_MASK 0x1
+#define DBG_OUT_CNTL__DBG_OUT_PIN_EN__SHIFT 0x0
+#define DBG_OUT_CNTL__DBG_OUT_PIN_SEL_MASK 0x10
+#define DBG_OUT_CNTL__DBG_OUT_PIN_SEL__SHIFT 0x4
+#define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL_MASK 0x300
+#define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL__SHIFT 0x8
+#define DBG_OUT_CNTL__DBG_OUT_TEST_DATA_MASK 0xfff000
+#define DBG_OUT_CNTL__DBG_OUT_TEST_DATA__SHIFT 0xc
+#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN_MASK 0x1
+#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN__SHIFT 0x0
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x1
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x2
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x1
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x4
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x2
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x8
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x3
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x10
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x4
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x20
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x5
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x40
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x6
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x80
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x7
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x100
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x8
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x200
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x9
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x400
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0xa
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x800
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xb
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x1000
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0xc
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x2000
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xd
+#define DCIO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x10000
+#define DCIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x10
+#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK 0x100000
+#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT 0x14
+#define DCIO_SOFT_RESET__DPHY_SOFT_RESET_MASK 0x1000000
+#define DCIO_SOFT_RESET__DPHY_SOFT_RESET__SHIFT 0x18
+#define DCIO_DPHY_SEL__DPHY_LANE0_SEL_MASK 0x3
+#define DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT 0x0
+#define DCIO_DPHY_SEL__DPHY_LANE1_SEL_MASK 0xc
+#define DCIO_DPHY_SEL__DPHY_LANE1_SEL__SHIFT 0x2
+#define DCIO_DPHY_SEL__DPHY_LANE2_SEL_MASK 0x30
+#define DCIO_DPHY_SEL__DPHY_LANE2_SEL__SHIFT 0x4
+#define DCIO_DPHY_SEL__DPHY_LANE3_SEL_MASK 0xc0
+#define DCIO_DPHY_SEL__DPHY_LANE3_SEL__SHIFT 0x6
+#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0xff
+#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x0
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG_MASK 0x3
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG__SHIFT 0x0
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG_MASK 0xc
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x2
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG_MASK 0x30
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG__SHIFT 0x4
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_MASK 0xc0
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0__SHIFT 0x6
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0_MASK 0x300
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0__SHIFT 0x8
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_MASK 0xc00
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN__SHIFT 0xa
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C_MASK 0x1000
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C__SHIFT 0xc
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG_MASK 0x2000
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG__SHIFT 0xd
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX_MASK 0x4000
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX__SHIFT 0xe
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_MASK 0x8000
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0__SHIFT 0xf
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG_MASK 0x10000
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG__SHIFT 0x10
+#define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE_MASK 0x20000
+#define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE__SHIFT 0x11
+#define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE_MASK 0x40000
+#define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE__SHIFT 0x12
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX_MASK 0x80000
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX__SHIFT 0x13
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_MASK 0x100000
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN__SHIFT 0x14
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX_MASK 0x200000
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX__SHIFT 0x15
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG_MASK 0x400000
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG__SHIFT 0x16
+#define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE_MASK 0x800000
+#define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE__SHIFT 0x17
+#define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE_MASK 0x1000000
+#define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE__SHIFT 0x18
+#define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL_MASK 0x2000000
+#define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL__SHIFT 0x19
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX_MASK 0x4000000
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT 0x1a
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_MASK 0x8000000
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0__SHIFT 0x1b
+#define DCIO_DEBUG2__DCIO_DEBUG2_MASK 0xffffffff
+#define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT 0x0
+#define DCIO_DEBUG3__DCIO_DEBUG3_MASK 0xffffffff
+#define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT 0x0
+#define DCIO_DEBUG4__DCIO_DEBUG4_MASK 0xffffffff
+#define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT 0x0
+#define DCIO_DEBUG5__DCIO_DEBUG5_MASK 0xffffffff
+#define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT 0x0
+#define DCIO_DEBUG6__DCIO_DEBUG6_MASK 0xffffffff
+#define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT 0x0
+#define DCIO_DEBUG7__DCIO_DEBUG7_MASK 0xffffffff
+#define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT 0x0
+#define DCIO_DEBUG8__DCIO_DEBUG8_MASK 0xffffffff
+#define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT 0x0
+#define DCIO_DEBUG9__DCIO_DEBUG9_MASK 0xffffffff
+#define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT 0x0
+#define DCIO_DEBUGA__DCIO_DEBUGA_MASK 0xffffffff
+#define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT 0x0
+#define DCIO_DEBUGB__DCIO_DEBUGB_MASK 0xffffffff
+#define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT 0x0
+#define DCIO_DEBUGC__DCIO_DEBUGC_MASK 0xffffffff
+#define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT 0x0
+#define DCIO_DEBUGD__DCIO_DEBUGD_MASK 0xffffffff
+#define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT 0x0
+#define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT 0x0
+#define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT 0x0
+#define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT 0x0
+#define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT 0x0
+#define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT 0x0
+#define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT 0x0
+#define DCIO_DEBUG14__DCIO_DIGG_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUG14__DCIO_DIGG_DEBUG__SHIFT 0x0
+#define DCIO_DEBUG15__DCIO_DEBUG15_MASK 0xffffffff
+#define DCIO_DEBUG15__DCIO_DEBUG15__SHIFT 0x0
+#define DCIO_DEBUG16__DCIO_DEBUG16_MASK 0xffffffff
+#define DCIO_DEBUG16__DCIO_DEBUG16__SHIFT 0x0
+#define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK 0xffffffff
+#define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT 0x0
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x1
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x2
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x4
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x10
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x20
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x40
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x100
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x200
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x400
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x1000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x2000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x4000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x10000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x20000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x40000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x100000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x200000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x400000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x1000000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x2000000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x4000000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x1
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x100
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x10000
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x100000
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x200000
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x400000
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x800000
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x1
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x100
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x10000
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x100000
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x200000
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x400000
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x800000
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x1
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x100
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x10000
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x100000
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x200000
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x400000
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x800000
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0xffffff
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x0
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x1f000000
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x18
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x20000000
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x1d
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xc0000000
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x1e
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0xffffff
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x0
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x1f000000
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x18
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x20000000
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x1d
+#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xc0000000
+#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x1e
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0xffffff
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x0
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x1f000000
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x18
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x20000000
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x1d
+#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xc0000000
+#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x1e
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0xffffff
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x0
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x1f000000
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x18
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x20000000
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x1d
+#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xc0000000
+#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x1e
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x1
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x10
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x40
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x100
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x1000
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x4000
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x10000
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10
+#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x100000
+#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x400000
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0xf000000
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xf0000000
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x1
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x100
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x1
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x100
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x1
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x100
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x1
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x10
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x40
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x100
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x1000
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x4000
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x10000
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10
+#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x100000
+#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x400000
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0xf000000
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xf0000000
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x1
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x100
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x1
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x100
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x1
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x100
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x1
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x10
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x40
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x100
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x1000
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x4000
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x10000
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10
+#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x100000
+#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x400000
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0xf000000
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xf0000000
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x1
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x100
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x1
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x100
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x1
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x100
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x1
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x10
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x40
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x100
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x1000
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x4000
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x10000
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10
+#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x100000
+#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x400000
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0xf000000
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xf0000000
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x1
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x100
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x1
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x100
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x1
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x100
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x1
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x10
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x40
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x100
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x1000
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x4000
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x10000
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10
+#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x100000
+#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x400000
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0xf000000
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xf0000000
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x1
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x100
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x1
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x100
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x1
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x100
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x1
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x10
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x40
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x100
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x1000
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x4000
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x10000
+#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x10
+#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x100000
+#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x14
+#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x400000
+#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0xf000000
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xf0000000
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x1
+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x100
+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x1
+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x100
+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x1
+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x100
+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x1
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x40
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x100
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x1000
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x4000
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x10000
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x100000
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x400000
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0xf000000
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xf0000000
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x1
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x100
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x1
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x100
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x1
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x100
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x1
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x0
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x10
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x4
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x40
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x6
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x100
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x8
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x1000
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0xc
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x4000
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0xe
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x7000000
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x18
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x1c
+#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x1
+#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x0
+#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x100
+#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x8
+#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x1
+#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x0
+#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x100
+#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x8
+#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x1
+#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x0
+#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x100
+#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x8
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x1
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x2
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x4
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x2
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x8
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x100
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x200
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x400
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xa
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x800
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x10000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x20000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x40000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x12
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x80000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x1000000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x2000000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x4000000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1a
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x8000000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x1
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x100
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x10000
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x1000000
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x1
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x100
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x10000
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x1000000
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x1
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x100
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x10000
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x1000000
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x1
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK 0x2
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT 0x1
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK 0x4
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT 0x2
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK 0x8
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT 0x3
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x10
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x40
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x100
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x200
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x400
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x10000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x20000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x40000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x100000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x200000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x400000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x1000000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x2000000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x4000000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0x40000000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x1
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x100
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x10000
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x1000000
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x4000000
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x1
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x2
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x4
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2
+#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK 0x8
+#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT 0x3
+#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK 0x10
+#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT 0x4
+#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x40
+#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6
+#define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK 0x80
+#define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT 0x7
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x100
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x10000
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x1000000
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x18
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x4000000
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x1a
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x1
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x100
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x10000
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x1000000
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x4000000
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x1
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x10
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x40
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x100
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x1000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x4000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x10000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x100000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x400000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x1000000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x2000000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x4000000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x1
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x100
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x10000
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x1000000
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x1
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x2
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x100
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x10000
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x1000000
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x1
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x100
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x10000
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x1000000
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0xf
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0xf0
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK 0xf00
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT 0x8
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK 0xf000
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT 0xc
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0xf000000
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xf0000000
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0xf
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0xf0
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x700
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x7000
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0xf0000
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0xf00000
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xc0000000
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK 0x1
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT 0x0
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK 0x2
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT 0x1
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK 0x4
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT 0x2
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK 0x8
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT 0x3
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK 0x10
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT 0x4
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK 0x20
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT 0x5
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK 0x40
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT 0x6
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK 0x80
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT 0x7
+#define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x1000
+#define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0xc
+#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK 0x2000
+#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT 0xd
+#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x4000
+#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0xe
+#define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x10000
+#define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x10
+#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x1
+#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x0
+#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x2
+#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x1
+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x1
+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x0
+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x2
+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x1
+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x1
+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x0
+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x2
+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x1
+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0xf
+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x0
+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0xf0
+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x4
+#define DVO_STRENGTH_CONTROL__DVO_SP_MASK 0xf
+#define DVO_STRENGTH_CONTROL__DVO_SP__SHIFT 0x0
+#define DVO_STRENGTH_CONTROL__DVO_SN_MASK 0xf0
+#define DVO_STRENGTH_CONTROL__DVO_SN__SHIFT 0x4
+#define DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK 0xf00
+#define DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT 0x8
+#define DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK 0xf000
+#define DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT 0xc
+#define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH_MASK 0x70000
+#define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH__SHIFT 0x10
+#define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH_MASK 0x700000
+#define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH__SHIFT 0x14
+#define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH_MASK 0x7000000
+#define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH__SHIFT 0x18
+#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK 0x10000000
+#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT 0x1c
+#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK 0x20000000
+#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT 0x1d
+#define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x1
+#define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x0
+#define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x2
+#define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1
+#define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0xf0
+#define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x4
+#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xffffffff
+#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x0
+#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define GRPH_ENABLE__GRPH_ENABLE_MASK 0x1
+#define GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
+#define GRPH_CONTROL__GRPH_DEPTH_MASK 0x3
+#define GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
+#define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc
+#define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2
+#define GRPH_CONTROL__GRPH_Z_MASK 0x30
+#define GRPH_CONTROL__GRPH_Z__SHIFT 0x4
+#define GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0xc0
+#define GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x6
+#define GRPH_CONTROL__GRPH_FORMAT_MASK 0x700
+#define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
+#define GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x1800
+#define GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0xb
+#define GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0xe000
+#define GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0xd
+#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000
+#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
+#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000
+#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
+#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0xc0000
+#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x12
+#define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000
+#define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14
+#define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000
+#define GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18
+#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK 0x60000000
+#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT 0x1d
+#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000
+#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
+#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x100
+#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
+#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x10000
+#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
+#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3
+#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
+#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30
+#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
+#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0
+#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
+#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300
+#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
+#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0xc00
+#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
+#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x1
+#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
+#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xffffff00
+#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
+#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x1
+#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
+#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00
+#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
+#define GRPH_PITCH__GRPH_PITCH_MASK 0x7fff
+#define GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
+#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0xff
+#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff
+#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x3fff
+#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
+#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x3fff
+#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
+#define GRPH_X_START__GRPH_X_START_MASK 0x3fff
+#define GRPH_X_START__GRPH_X_START__SHIFT 0x0
+#define GRPH_Y_START__GRPH_Y_START_MASK 0x3fff
+#define GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
+#define GRPH_X_END__GRPH_X_END_MASK 0x7fff
+#define GRPH_X_END__GRPH_X_END__SHIFT 0x0
+#define GRPH_Y_END__GRPH_Y_END_MASK 0x7fff
+#define GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
+#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x3
+#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
+#define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE_MASK 0x30
+#define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT 0x4
+#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1
+#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
+#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2
+#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
+#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4
+#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
+#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8
+#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
+#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK 0x100
+#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT 0x8
+#define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000
+#define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
+#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000
+#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
+#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
+#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000
+#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
+#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x1
+#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
+#define GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x2
+#define GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1
+#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xffffff00
+#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
+#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x1
+#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
+#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x70
+#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
+#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x700
+#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
+#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0xf
+#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
+#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0
+#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
+#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x100
+#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
+#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x200
+#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
+#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1
+#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
+#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100
+#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
+#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1
+#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
+#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100
+#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
+#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff
+#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
+#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xffffff00
+#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
+#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x1ffc0
+#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
+#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0xff
+#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define OVL_ENABLE__OVL_ENABLE_MASK 0x1
+#define OVL_ENABLE__OVL_ENABLE__SHIFT 0x0
+#define OVL_ENABLE__OVLSCL_EN_MASK 0x100
+#define OVL_ENABLE__OVLSCL_EN__SHIFT 0x8
+#define OVL_CONTROL1__OVL_DEPTH_MASK 0x3
+#define OVL_CONTROL1__OVL_DEPTH__SHIFT 0x0
+#define OVL_CONTROL1__OVL_NUM_BANKS_MASK 0xc
+#define OVL_CONTROL1__OVL_NUM_BANKS__SHIFT 0x2
+#define OVL_CONTROL1__OVL_Z_MASK 0x30
+#define OVL_CONTROL1__OVL_Z__SHIFT 0x4
+#define OVL_CONTROL1__OVL_BANK_WIDTH_MASK 0xc0
+#define OVL_CONTROL1__OVL_BANK_WIDTH__SHIFT 0x6
+#define OVL_CONTROL1__OVL_FORMAT_MASK 0x700
+#define OVL_CONTROL1__OVL_FORMAT__SHIFT 0x8
+#define OVL_CONTROL1__OVL_BANK_HEIGHT_MASK 0x1800
+#define OVL_CONTROL1__OVL_BANK_HEIGHT__SHIFT 0xb
+#define OVL_CONTROL1__OVL_TILE_SPLIT_MASK 0xe000
+#define OVL_CONTROL1__OVL_TILE_SPLIT__SHIFT 0xd
+#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000
+#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
+#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000
+#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
+#define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT_MASK 0xc0000
+#define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT__SHIFT 0x12
+#define OVL_CONTROL1__OVL_ARRAY_MODE_MASK 0xf00000
+#define OVL_CONTROL1__OVL_ARRAY_MODE__SHIFT 0x14
+#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE_MASK 0x1000000
+#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE__SHIFT 0x18
+#define OVL_CONTROL1__OVL_PIPE_CONFIG_MASK 0x3e000000
+#define OVL_CONTROL1__OVL_PIPE_CONFIG__SHIFT 0x19
+#define OVL_CONTROL1__OVL_MICRO_TILE_MODE_MASK 0xc0000000
+#define OVL_CONTROL1__OVL_MICRO_TILE_MODE__SHIFT 0x1e
+#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE_MASK 0x1
+#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE__SHIFT 0x0
+#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP_MASK 0x3
+#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP__SHIFT 0x0
+#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR_MASK 0x30
+#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR__SHIFT 0x4
+#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR_MASK 0xc0
+#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR__SHIFT 0x6
+#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR_MASK 0x300
+#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR__SHIFT 0x8
+#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR_MASK 0xc00
+#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR__SHIFT 0xa
+#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE_MASK 0x1
+#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE__SHIFT 0x0
+#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS_MASK 0xffffff00
+#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS__SHIFT 0x8
+#define OVL_PITCH__OVL_PITCH_MASK 0x7fff
+#define OVL_PITCH__OVL_PITCH__SHIFT 0x0
+#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH_MASK 0xff
+#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X_MASK 0x3fff
+#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X__SHIFT 0x0
+#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y_MASK 0x3fff
+#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y__SHIFT 0x0
+#define OVL_START__OVL_Y_START_MASK 0x3fff
+#define OVL_START__OVL_Y_START__SHIFT 0x0
+#define OVL_START__OVL_X_START_MASK 0x3fff0000
+#define OVL_START__OVL_X_START__SHIFT 0x10
+#define OVL_END__OVL_Y_END_MASK 0x7fff
+#define OVL_END__OVL_Y_END__SHIFT 0x0
+#define OVL_END__OVL_X_END_MASK 0x7fff0000
+#define OVL_END__OVL_X_END__SHIFT 0x10
+#define OVL_UPDATE__OVL_UPDATE_PENDING_MASK 0x1
+#define OVL_UPDATE__OVL_UPDATE_PENDING__SHIFT 0x0
+#define OVL_UPDATE__OVL_UPDATE_TAKEN_MASK 0x2
+#define OVL_UPDATE__OVL_UPDATE_TAKEN__SHIFT 0x1
+#define OVL_UPDATE__OVL_UPDATE_LOCK_MASK 0x10000
+#define OVL_UPDATE__OVL_UPDATE_LOCK__SHIFT 0x10
+#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
+#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE_MASK 0xffffff00
+#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE__SHIFT 0x8
+#define OVL_DFQ_CONTROL__OVL_DFQ_RESET_MASK 0x1
+#define OVL_DFQ_CONTROL__OVL_DFQ_RESET__SHIFT 0x0
+#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE_MASK 0x70
+#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE__SHIFT 0x4
+#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES_MASK 0x700
+#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
+#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES_MASK 0xf
+#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES__SHIFT 0x0
+#define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0
+#define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
+#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG_MASK 0x100
+#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG__SHIFT 0x8
+#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK_MASK 0x200
+#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK__SHIFT 0x9
+#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff
+#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB_MASK 0x3ff
+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB__SHIFT 0x0
+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY_MASK 0xffc00
+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY__SHIFT 0xa
+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR_MASK 0x3ff00000
+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR__SHIFT 0x14
+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL_MASK 0x80000000
+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL__SHIFT 0x1f
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x1
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x2
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x4
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x8
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x10
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
+#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0xffff
+#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
+#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xffff0000
+#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
+#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0xffff
+#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
+#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xffff0000
+#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
+#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0xffff
+#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
+#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xffff0000
+#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT_MASK 0x1
+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT__SHIFT 0x0
+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN_MASK 0x2
+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN__SHIFT 0x1
+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN_MASK 0x4
+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN__SHIFT 0x2
+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN_MASK 0x8
+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN__SHIFT 0x3
+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK 0x10
+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS__SHIFT 0x4
+#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB_MASK 0xffff
+#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB__SHIFT 0x0
+#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB_MASK 0xffff0000
+#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB__SHIFT 0x10
+#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y_MASK 0xffff
+#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y__SHIFT 0x0
+#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y_MASK 0xffff0000
+#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y__SHIFT 0x10
+#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR_MASK 0xffff
+#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR__SHIFT 0x0
+#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR_MASK 0xffff0000
+#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR__SHIFT 0x10
+#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x3
+#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
+#define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE_MASK 0x30
+#define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT 0x4
+#define INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0xffff
+#define INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
+#define INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xffff0000
+#define INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
+#define INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0xffff
+#define INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
+#define INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xffff0000
+#define INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
+#define INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0xffff
+#define INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
+#define INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xffff0000
+#define INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
+#define INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0xffff
+#define INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
+#define INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xffff0000
+#define INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
+#define INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0xffff
+#define INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
+#define INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xffff0000
+#define INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
+#define INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0xffff
+#define INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
+#define INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xffff0000
+#define INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
+#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x7
+#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
+#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE_MASK 0x70
+#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT 0x4
+#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0xffff
+#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
+#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xffff0000
+#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
+#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0xffff
+#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
+#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xffff0000
+#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
+#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0xffff
+#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
+#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xffff0000
+#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
+#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0xffff
+#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
+#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xffff0000
+#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
+#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0xffff
+#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
+#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xffff0000
+#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
+#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0xffff
+#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
+#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xffff0000
+#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
+#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0xffff
+#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
+#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xffff0000
+#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
+#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0xffff
+#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
+#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xffff0000
+#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
+#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0xffff
+#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
+#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xffff0000
+#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
+#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0xffff
+#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
+#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xffff0000
+#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
+#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0xffff
+#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
+#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xffff0000
+#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
+#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0xffff
+#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
+#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xffff0000
+#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
+#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0xffff
+#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
+#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xffff0000
+#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
+#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0xffff
+#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
+#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xffff0000
+#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
+#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0xffff
+#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
+#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xffff0000
+#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
+#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0xffff
+#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
+#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xffff0000
+#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
+#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0xffff
+#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
+#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xffff0000
+#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
+#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0xffff
+#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
+#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xffff0000
+#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
+#define DENORM_CONTROL__DENORM_MODE_MASK 0x7
+#define DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
+#define DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x10
+#define DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
+#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0xf
+#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
+#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x3fff
+#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
+#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3fff0000
+#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
+#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x3fff
+#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
+#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3fff0000
+#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
+#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x3fff
+#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
+#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3fff0000
+#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
+#define KEY_CONTROL__KEY_SELECT_MASK 0x1
+#define KEY_CONTROL__KEY_SELECT__SHIFT 0x0
+#define KEY_CONTROL__KEY_MODE_MASK 0x6
+#define KEY_CONTROL__KEY_MODE__SHIFT 0x1
+#define KEY_CONTROL__GRPH_OVL_HALF_BLEND_MASK 0x10000000
+#define KEY_CONTROL__GRPH_OVL_HALF_BLEND__SHIFT 0x1c
+#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0xffff
+#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
+#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xffff0000
+#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
+#define KEY_RANGE_RED__KEY_RED_LOW_MASK 0xffff
+#define KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
+#define KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xffff0000
+#define KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
+#define KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0xffff
+#define KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
+#define KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xffff0000
+#define KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
+#define KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0xffff
+#define KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
+#define KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xffff0000
+#define KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
+#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x3
+#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
+#define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE_MASK 0x30
+#define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT 0x4
+#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x300
+#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
+#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x3000
+#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
+#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x3
+#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
+#define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE_MASK 0x30
+#define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT 0x4
+#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0xffff
+#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
+#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xffff0000
+#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
+#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0xffff
+#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
+#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xffff0000
+#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
+#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0xffff
+#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
+#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xffff0000
+#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
+#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0xffff
+#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
+#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xffff0000
+#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
+#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0xffff
+#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
+#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xffff0000
+#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
+#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0xffff
+#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
+#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xffff0000
+#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x1
+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x30
+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0xc0
+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
+#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x100
+#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
+#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x200
+#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
+#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x400
+#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
+#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0xff
+#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0
+#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0xff00
+#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8
+#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0xff0000
+#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10
+#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff
+#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
+#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x7f00000
+#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
+#define CUR_CONTROL__CURSOR_EN_MASK 0x1
+#define CUR_CONTROL__CURSOR_EN__SHIFT 0x0
+#define CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x10
+#define CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
+#define CUR_CONTROL__CURSOR_MODE_MASK 0x300
+#define CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
+#define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x10000
+#define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
+#define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x100000
+#define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
+#define CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x7000000
+#define CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
+#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xffffffff
+#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
+#define CUR_SIZE__CURSOR_HEIGHT_MASK 0x7f
+#define CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
+#define CUR_SIZE__CURSOR_WIDTH_MASK 0x7f0000
+#define CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
+#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0xff
+#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define CUR_POSITION__CURSOR_Y_POSITION_MASK 0x3fff
+#define CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
+#define CUR_POSITION__CURSOR_X_POSITION_MASK 0x3fff0000
+#define CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
+#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x7f
+#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
+#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x7f0000
+#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
+#define CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0xff
+#define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
+#define CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0xff00
+#define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
+#define CUR_COLOR1__CUR_COLOR1_RED_MASK 0xff0000
+#define CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
+#define CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0xff
+#define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
+#define CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0xff00
+#define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
+#define CUR_COLOR2__CUR_COLOR2_RED_MASK 0xff0000
+#define CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
+#define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x1
+#define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
+#define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x2
+#define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
+#define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x10000
+#define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
+#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
+#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x6000000
+#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
+#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x1
+#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
+#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x1
+#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
+#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX_MASK 0x2
+#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX__SHIFT 0x1
+#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x3ff0
+#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
+#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x3ff0000
+#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
+#define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x1
+#define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
+#define DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x10000
+#define DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10
+#define DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x20000
+#define DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11
+#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0xff
+#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
+#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0xffff
+#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
+#define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0xffff
+#define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
+#define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xffff0000
+#define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x3ff
+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0xffc00
+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3ff00000
+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
+#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x1
+#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
+#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x7
+#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x1
+#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
+#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x2
+#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
+#define DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0xf
+#define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
+#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x10
+#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
+#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x20
+#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
+#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0xc0
+#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
+#define DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0xf00
+#define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
+#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x1000
+#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
+#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x2000
+#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
+#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0xc000
+#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
+#define DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0xf0000
+#define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
+#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x100000
+#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
+#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x200000
+#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
+#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0xc00000
+#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
+#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0xffff
+#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
+#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0xffff
+#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
+#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0xffff
+#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
+#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0xffff
+#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
+#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0xffff
+#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
+#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0xffff
+#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
+#define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x1
+#define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
+#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x1c
+#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
+#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x300
+#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
+#define DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xffffffff
+#define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
+#define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xffffffff
+#define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
+#define DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xffffffff
+#define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
+#define DCP_DEBUG__DCP_DEBUG_MASK 0xffffffff
+#define DCP_DEBUG__DCP_DEBUG__SHIFT 0x0
+#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x7
+#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
+#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x8
+#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
+#define DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x1
+#define DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
+#define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x2
+#define DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
+#define DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x4
+#define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
+#define DCP_GSL_CONTROL__DCP_GSL_MODE_MASK 0x300
+#define DCP_GSL_CONTROL__DCP_GSL_MODE__SHIFT 0x8
+#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0xf000
+#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0xc
+#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x10000
+#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x10
+#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x60000
+#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x11
+#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x80000
+#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x13
+#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x3000000
+#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
+#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x8000000
+#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
+#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xf0000000
+#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
+#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0xf
+#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
+#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x1f0
+#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
+#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE_MASK 0x1
+#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE__SHIFT 0x0
+#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00
+#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
+#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN_MASK 0x1
+#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN__SHIFT 0x0
+#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE_MASK 0x300
+#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE__SHIFT 0x8
+#define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING_MASK 0x10000
+#define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING__SHIFT 0x10
+#define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING_MASK 0x20000
+#define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING__SHIFT 0x11
+#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000
+#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
+#define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff
+#define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK 0xff
+#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT 0x0
+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1
+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x300
+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
+#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000
+#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
+#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000
+#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000
+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
+#define DCP_DEBUG2__DCP_DEBUG2_MASK 0xffffffff
+#define DCP_DEBUG2__DCP_DEBUG2__SHIFT 0x0
+#define HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x7
+#define HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x1
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x2
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x1fff0
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
+#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x7
+#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
+#define REGAMMA_CONTROL__OVL_REGAMMA_MODE_MASK 0x70
+#define REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT 0x4
+#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x1ff
+#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
+#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x7ffff
+#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
+#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x7
+#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x3ffff
+#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
+#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000
+#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
+#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0xffff
+#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
+#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff
+#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000
+#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x3ffff
+#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
+#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000
+#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
+#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0xffff
+#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
+#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff
+#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000
+#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x1
+#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
+#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x2
+#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
+#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xffffff00
+#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
+#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0xff
+#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0xfffff
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x1000000
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x2000000
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x4000000
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
+#define DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x7
+#define DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
+#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x70
+#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
+#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x100
+#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
+#define DIG_FE_CNTL__DIG_START_MASK 0x400
+#define DIG_FE_CNTL__DIG_START__SHIFT 0xa
+#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x1000000
+#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
+#define DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000
+#define DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
+#define DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xc0000000
+#define DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x1
+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x10
+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x300
+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
+#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3fffffff
+#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
+#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x3ff
+#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
+#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x1
+#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
+#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x2
+#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
+#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA_MASK 0x4
+#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA__SHIFT 0x2
+#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x10
+#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
+#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x20
+#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
+#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x40
+#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
+#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN_MASK 0x100
+#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN__SHIFT 0x8
+#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x3ff0000
+#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
+#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0xffffff
+#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
+#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x1000000
+#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
+#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x1
+#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
+#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
+#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0xfc
+#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x100
+#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
+#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00
+#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x1f0000
+#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x3c00000
+#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000
+#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
+#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000
+#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000
+#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK 0x1
+#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT 0x0
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK 0x1
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT 0x0
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK 0x10
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT 0x4
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK 0x100
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT 0x8
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK 0x1000
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0xc
+#define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x1
+#define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
+#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x4
+#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
+#define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x8
+#define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
+#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x10
+#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
+#define HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x100
+#define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
+#define HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x200
+#define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
+#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x1000000
+#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
+#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000
+#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
+#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x1
+#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
+#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x10000
+#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
+#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x100000
+#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
+#define HDMI_STATUS__HDMI_ERROR_INT_MASK 0x8000000
+#define HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x30
+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x100
+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8
+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x1f0000
+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x1
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x2
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x30
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x100
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x1000
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x70000
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
+#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x1
+#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
+#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x10
+#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
+#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x20
+#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x100
+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x200
+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x3f0000
+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x1
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x2
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x10
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x20
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
+#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x100
+#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
+#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x200
+#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
+#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x3f
+#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
+#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x3f00
+#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
+#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x3f0000
+#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x1
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x2
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x10
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x20
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x3f0000
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3f000000
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
+#define HDMI_GC__HDMI_GC_AVMUTE_MASK 0x1
+#define HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
+#define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x4
+#define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
+#define HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x10
+#define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
+#define HDMI_GC__HDMI_PACKING_PHASE_MASK 0xf00
+#define HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
+#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x1000
+#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x1
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x2
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0xff00
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0xff0000
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x1000000
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
+#define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x7
+#define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
+#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x40
+#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
+#define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x80
+#define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0xff
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0xff00
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0xff0000
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xff000000
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0xff
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0xff00
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0xff0000
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xff000000
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0xff
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0xff00
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0xff0000
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xff000000
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0xff
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0xff00
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0xff0000
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xff000000
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0xff
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0xff00
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0xff0000
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xff000000
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0xff
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0xff00
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0xff0000
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xff000000
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0xff
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0xff00
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0xff0000
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xff000000
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0xff
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0xff00
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0xff0000
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xff000000
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0xff
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x300
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0xc00
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x1000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x6000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD_MASK 0x8000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD__SHIFT 0xf
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0xf0000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x300000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0xc00000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x3000000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0xc000000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x7f
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD_MASK 0x80
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD__SHIFT 0x7
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0xf00
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x3000
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0xc000
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xffff0000
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
+#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0xffff
+#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
+#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xffff0000
+#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
+#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0xffff
+#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
+#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xff000000
+#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0xff
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0xff00
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0xff0000
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xff000000
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0xff
+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x300
+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x1000
+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0xff
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0xff00
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0xff0000
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xff000000
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0xff
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0xff00
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0xff0000
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xff000000
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0xff
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0xff00
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0xff0000
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xff000000
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0xff
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0xff00
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0xff0000
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xff000000
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0xff
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0xff00
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0xff0000
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xff000000
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0xff
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0xff00
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0xff0000
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xff000000
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0xff
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0xff00
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0xff0000
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xff000000
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0xff
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0xff00
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0xff0000
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xff000000
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0xff
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0xff00
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0xff0000
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xff000000
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x1
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x2
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x10
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x20
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x3f0000
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3f000000
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
+#define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xfffff000
+#define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
+#define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0xfffff
+#define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
+#define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xfffff000
+#define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
+#define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0xfffff
+#define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
+#define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xfffff000
+#define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
+#define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0xfffff
+#define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
+#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xfffff000
+#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
+#define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0xfffff
+#define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0xff
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x700
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x7800
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0xff0000
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1f000000
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0xff
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x7800
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x8000
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x30000
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
+#define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x1
+#define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
+#define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x2
+#define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
+#define AFMT_60958_0__AFMT_60958_CS_C_MASK 0x4
+#define AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
+#define AFMT_60958_0__AFMT_60958_CS_D_MASK 0x38
+#define AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
+#define AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0xc0
+#define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
+#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0xff00
+#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
+#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0xf0000
+#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
+#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0xf00000
+#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
+#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0xf000000
+#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
+#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000
+#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
+#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0xf
+#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
+#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf0
+#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
+#define AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x10000
+#define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
+#define AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x40000
+#define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
+#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0xf00000
+#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x1
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x10
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x100
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0xf000
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xffff0000
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
+#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0xffffff
+#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
+#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000
+#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
+#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0xffffff
+#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
+#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xff000000
+#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
+#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0xffffff
+#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
+#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0xffffff
+#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0xf
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0xf00
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0xf000
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0xf0000
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0xf00000
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
+#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x1
+#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
+#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xffffff00
+#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
+#define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x10
+#define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
+#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x100
+#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
+#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x1000000
+#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
+#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000
+#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x1
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x800
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x1000
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x4000
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x800000
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x1000000
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x4000000
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f
+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x4
+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x8
+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xc0000000
+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
+#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x40
+#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
+#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x80
+#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
+#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x400
+#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
+#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x7
+#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x7
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x0
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x100
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x8
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x7000
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0xc
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x70000
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x10
+#define DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x1
+#define DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
+#define DIG_BE_CNTL__DIG_SWAP_MASK 0x2
+#define DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
+#define DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x4
+#define DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2
+#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x7f00
+#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
+#define DIG_BE_CNTL__DIG_MODE_MASK 0x70000
+#define DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
+#define DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000
+#define DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
+#define DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x1
+#define DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
+#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x100
+#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
+#define TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x1
+#define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x1
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x2
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x4
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x8
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
+#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x3
+#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
+#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x300
+#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
+#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x3
+#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
+#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x3ff
+#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
+#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x3ff0000
+#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
+#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x3ff
+#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
+#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x3ff0000
+#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
+#define TMDS_DEBUG__TMDS_DEBUG_EN_MASK 0x1
+#define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT 0x0
+#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK 0x100
+#define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT 0x8
+#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK 0x200
+#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT 0x9
+#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK 0x10000
+#define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT 0x10
+#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK 0x20000
+#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT 0x11
+#define TMDS_DEBUG__TMDS_DEBUG_DE_MASK 0x1000000
+#define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT 0x18
+#define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK 0x2000000
+#define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT 0x19
+#define TMDS_CTL_BITS__TMDS_CTL0_MASK 0x1
+#define TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
+#define TMDS_CTL_BITS__TMDS_CTL1_MASK 0x100
+#define TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
+#define TMDS_CTL_BITS__TMDS_CTL2_MASK 0x10000
+#define TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
+#define TMDS_CTL_BITS__TMDS_CTL3_MASK 0x1000000
+#define TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x1
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
+#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x70
+#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x100
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0xf0000
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x1000000
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0xf
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x70
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x80
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x300
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x400
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x800
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x1000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0xf0000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x700000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x800000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x3000000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x4000000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x8000000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0xf
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x70
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x80
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x300
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x400
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x800
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x1000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0xf0000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x700000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x800000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x3000000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x4000000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x8000000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
+#define TMDS_DEBUG1__DBG_DIG_TMDS_PIXCLK_MASK 0x1
+#define TMDS_DEBUG1__DBG_DIG_TMDS_PIXCLK__SHIFT 0x0
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_IN_MASK 0x2
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_IN__SHIFT 0x1
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_IN_MASK 0x4
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_IN__SHIFT 0x2
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_DE_IN_MASK 0x8
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_DE_IN__SHIFT 0x3
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_IN_MASK 0xff0
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_IN__SHIFT 0x4
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_STEREOSYNC_IN_MASK 0x1000
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_STEREOSYNC_IN__SHIFT 0xc
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLCTL0_IN_MASK 0x2000
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLCTL0_IN__SHIFT 0xd
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_OUT_MASK 0x3fc000
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_OUT__SHIFT 0xe
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_DE_MASK 0x400000
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_DE__SHIFT 0x16
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_OUT_MASK 0x800000
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_OUT__SHIFT 0x17
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_OUT_MASK 0x1000000
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_OUT__SHIFT 0x18
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL0_OUT_MASK 0x2000000
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL0_OUT__SHIFT 0x19
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL1_OUT_MASK 0x4000000
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL1_OUT__SHIFT 0x1a
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL2_OUT_MASK 0x8000000
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL2_OUT__SHIFT 0x1b
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL3_OUT_MASK 0x10000000
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL3_OUT__SHIFT 0x1c
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLDEVS_OUT_MASK 0x20000000
+#define TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLDEVS_OUT__SHIFT 0x1d
+#define TMDS_DEBUG2__DBG_DIG_TMDS_PIXCLK_MASK 0x1
+#define TMDS_DEBUG2__DBG_DIG_TMDS_PIXCLK__SHIFT 0x0
+#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_A_IN_MASK 0x2
+#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_A_IN__SHIFT 0x1
+#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_B_IN_MASK 0x4
+#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_B_IN__SHIFT 0x2
+#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DE_IN_MASK 0x8
+#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DE_IN__SHIFT 0x3
+#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_IN_MASK 0xff0
+#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_IN__SHIFT 0x4
+#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DCB_MASK 0x1ff000
+#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DCB__SHIFT 0xc
+#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_DE_TX_MASK 0x200000
+#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_DE_TX__SHIFT 0x15
+#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_TX_MASK 0xffc00000
+#define TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_TX__SHIFT 0x16
+#define TMDS_DEBUG3__DBG_DIG_TMDS_PIXCLK_MASK 0x1
+#define TMDS_DEBUG3__DBG_DIG_TMDS_PIXCLK__SHIFT 0x0
+#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_DE_IN_MASK 0x2
+#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_DE_IN__SHIFT 0x1
+#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_IN_MASK 0xffc
+#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_IN__SHIFT 0x2
+#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL0_IN_MASK 0x1000
+#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL0_IN__SHIFT 0xc
+#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL1_IN_MASK 0x2000
+#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL1_IN__SHIFT 0xd
+#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL2_IN_MASK 0x4000
+#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL2_IN__SHIFT 0xe
+#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL3_IN_MASK 0x8000
+#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL3_IN__SHIFT 0xf
+#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_HSYNC_IN_MASK 0x100000
+#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_HSYNC_IN__SHIFT 0x14
+#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_VSYNC_IN_MASK 0x200000
+#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_VSYNC_IN__SHIFT 0x15
+#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_PLPIXA_OUT_MASK 0xffc00000
+#define TMDS_DEBUG3__DBG_DIG_TMDS_TX_PLPIXA_OUT__SHIFT 0x16
+#define TMDS_DEBUG7__DBG_DIG_TMDS7_MASK 0xffffffff
+#define TMDS_DEBUG7__DBG_DIG_TMDS7__SHIFT 0x0
+#define TMDS_DEBUG8__DBG_DIG_TMDS8_MASK 0xffffffff
+#define TMDS_DEBUG8__DBG_DIG_TMDS8__SHIFT 0x0
+#define TMDS_DEBUG9__DBG_DIG_TMDS9_MASK 0xffffffff
+#define TMDS_DEBUG9__DBG_DIG_TMDS9__SHIFT 0x0
+#define TMDS_DEBUG10__DBG_DIG_TMDS10_MASK 0xffffffff
+#define TMDS_DEBUG10__DBG_DIG_TMDS10__SHIFT 0x0
+#define TMDS_DEBUG11__DBG_DIG_TMDS11_MASK 0xffffffff
+#define TMDS_DEBUG11__DBG_DIG_TMDS11__SHIFT 0x0
+#define TMDS_DEBUG12__DBG_LVDS_DEBUG1_MASK 0xffffffff
+#define TMDS_DEBUG12__DBG_LVDS_DEBUG1__SHIFT 0x0
+#define TMDS_DEBUG13__DBG_LVDS_DEBUG2_MASK 0xffffffff
+#define TMDS_DEBUG13__DBG_LVDS_DEBUG2__SHIFT 0x0
+#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE_MASK 0x1
+#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE__SHIFT 0x0
+#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT_MASK 0x10
+#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT__SHIFT 0x4
+#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE_MASK 0x100
+#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE__SHIFT 0x8
+#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS_MASK 0x200
+#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS__SHIFT 0x9
+#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS_MASK 0x400
+#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS__SHIFT 0xa
+#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS_MASK 0x7000
+#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS__SHIFT 0xc
+#define LVDS_DATA_CNTL__LVDS_FP_POL_MASK 0x10000
+#define LVDS_DATA_CNTL__LVDS_FP_POL__SHIFT 0x10
+#define LVDS_DATA_CNTL__LVDS_LP_POL_MASK 0x20000
+#define LVDS_DATA_CNTL__LVDS_LP_POL__SHIFT 0x11
+#define LVDS_DATA_CNTL__LVDS_DTMG_POL_MASK 0x40000
+#define LVDS_DATA_CNTL__LVDS_DTMG_POL__SHIFT 0x12
+#define DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x1
+#define DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
+#define DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x2
+#define DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
+#define DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x4
+#define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
+#define DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x8
+#define DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
+#define DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x100
+#define DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
+#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX_MASK 0xff
+#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA__SHIFT 0x0
+#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX_MASK 0xff
+#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA__SHIFT 0x0
+#define DMCU_CTRL__RESET_UC_MASK 0x1
+#define DMCU_CTRL__RESET_UC__SHIFT 0x0
+#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x2
+#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1
+#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x4
+#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2
+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x8
+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3
+#define DMCU_CTRL__DMCU_ENABLE_MASK 0x10
+#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4
+#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xffff0000
+#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x10
+#define DMCU_STATUS__UC_IN_RESET_MASK 0x1
+#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0
+#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x2
+#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1
+#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x4
+#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2
+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0xff
+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0
+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0xff00
+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8
+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0xff
+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0
+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0xff00
+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8
+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0xff
+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0
+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0xff00
+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0xff
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0xff00
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8
+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xffffffff
+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0
+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xffffffff
+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0
+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x1
+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0
+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x2
+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1
+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x4
+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2
+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x8
+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3
+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x10
+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4
+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x20
+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5
+#define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT_MASK 0xff00
+#define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT__SHIFT 0x8
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0xffff
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0xf0000
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x100000
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14
+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xffffffff
+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0xffff
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0xf0000
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x100000
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14
+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xffffffff
+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0
+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x3ff
+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0
+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0xff
+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0
+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x3ff
+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0
+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0xff
+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0
+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x1
+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0
+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x7f0000
+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10
+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x800000
+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x1
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x2
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x4
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x8
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x10
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x20
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x40
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x80
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x100
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x200
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x400
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x800
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x1000
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x2000
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x4000
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x8000
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x2000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x4000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x4000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x8000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x10000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x10000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x20000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x40000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x40000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x80000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x100000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x100000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x200000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x400000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x400000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x800000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x1000000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x1000000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x2
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x2
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x4
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x4
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2
+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x8
+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED_MASK 0x10
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED__SHIFT 0x4
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR_MASK 0x10
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR__SHIFT 0x4
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED_MASK 0x20
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED__SHIFT 0x5
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR_MASK 0x20
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR__SHIFT 0x5
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x100
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x100
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8
+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x200
+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x400
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x400
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x800
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x800
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x1000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0xc
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x1000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0xc
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x2000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0xd
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x2000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0xd
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x4000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0xe
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x4000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0xe
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x8000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0xf
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x8000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xf
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x10000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x10
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x10000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x10
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x20000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x11
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x20000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x11
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x40000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x40000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x12
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x80000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x80000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x13
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x100000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x100000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x14
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x200000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x200000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x15
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x400000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x400000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x16
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x800000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x800000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x1000000
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x1000000
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x2000000
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x2000000
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x4000000
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x4000000
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x8000000
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x8000000
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x1
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x0
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x2
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x1
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x4
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x2
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_MASK_MASK 0x10
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_MASK__SHIFT 0x4
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_MASK_MASK 0x20
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_MASK__SHIFT 0x5
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x200
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x400
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x800
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK_MASK 0x1000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK__SHIFT 0xc
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK_MASK 0x2000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK__SHIFT 0xd
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK_MASK 0x4000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK__SHIFT 0xe
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK_MASK 0x8000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK__SHIFT 0xf
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK_MASK 0x10000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK__SHIFT 0x10
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK_MASK 0x20000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK__SHIFT 0x11
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK_MASK 0x40000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x12
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK_MASK 0x80000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x13
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK_MASK 0x100000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK__SHIFT 0x14
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK_MASK 0x200000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK__SHIFT 0x15
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK_MASK 0x400000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x16
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK_MASK 0x800000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x17
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x4
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN_MASK 0x10
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN_MASK 0x20
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x40
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x80
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x100
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x200
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x400
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x800
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x1000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x2000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x4000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x8000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x10000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x20000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x40000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x80000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x100000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x200000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x400000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x800000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x1000000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x2000000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x4000000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x8000000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x40000000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x1e
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x4
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x20
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x40
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x80
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x100
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x200
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x400
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x800
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x1000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x2000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x4000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x8000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x20000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x40000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x80000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x100000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x200000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x400000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x800000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x1000000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x2000000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x4000000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x8000000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x40000000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0x1e
+#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xffffffff
+#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0
+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0xff
+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0
+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0xff00
+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8
+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0xff0000
+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x3
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0xc
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2
+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x7
+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0
+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x700
+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8
+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x10000
+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0xff
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0xff00
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0xff0000
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xff000000
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0xff
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0xff00
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0xff0000
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xff000000
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0xff
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0xff00
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0xff0000
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xff000000
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0xff
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0xff00
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0xff0000
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xff000000
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18
+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x1
+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0xff
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0xff00
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0xff0000
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xff000000
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0xff
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0xff00
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0xff0000
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xff000000
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0xff
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0xff00
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0xff0000
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xff000000
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0xff
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0xff00
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0xff0000
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xff000000
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18
+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x1
+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0
+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x100
+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8
+#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK 0xff
+#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER0_INT_MASK_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER1_INT_MASK_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER2_INT_MASK_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER3_INT_MASK_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER4_INT_MASK_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER5_INT_MASK_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER6_INT_MASK_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER7_INT_MASK_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER0_INT_MASK_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER1_INT_MASK_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER2_INT_MASK_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER3_INT_MASK_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER4_INT_MASK_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER5_INT_MASK_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER6_INT_MASK_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER7_INT_MASK_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_MASK_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_MASK_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_MASK_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_MASK_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_MASK_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_MASK_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_MASK_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_MASK_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_MASK_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_MASK_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_MASK_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_MASK_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_MASK_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_MASK_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_MASK_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_MASK_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_MASK_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_MASK_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_MASK_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_MASK_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_MASK_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_MASK_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_MASK_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_MASK_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_MASK_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_MASK_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_MASK_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_MASK_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_MASK_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_MASK_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_MASK_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_MASK_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_MASK_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_MASK_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_MASK_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_MASK_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_MASK_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_MASK_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_MASK_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_MASK_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_MASK_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_MASK_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_MASK_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_MASK_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_MASK_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_MASK_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_MASK_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_MASK_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_MASK_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_MASK_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_MASK_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_MASK_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_MASK_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_MASK_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_MASK_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_MASK_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER0_INT_MASK_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER1_INT_MASK_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER2_INT_MASK_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER3_INT_MASK_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER4_INT_MASK_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER5_INT_MASK_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER6_INT_MASK_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER7_INT_MASK_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_MASK_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_MASK_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_MASK_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_MASK_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_MASK_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_MASK_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_MASK_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_MASK_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_MASK_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_MASK_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_MASK_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_MASK_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_MASK_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_MASK_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_MASK_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_MASK_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x8
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x0
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK 0x1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x0
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x2
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x2
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK 0x4
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT 0x2
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK 0x4
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT 0x2
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK 0x8
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT 0x3
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK 0x8
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT 0x3
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x10
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x4
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK 0x10
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x4
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x20
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x5
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK 0x20
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x5
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x40
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x6
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x40
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x6
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK 0x80
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT 0x7
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK 0x80
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT 0x7
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK 0x100
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT 0x8
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK 0x100
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT 0x8
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x200
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x9
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK 0x200
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x9
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x400
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xa
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x400
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xa
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x800
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xb
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x800
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xb
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x1000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xc
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x1000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xc
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x2000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xd
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x2000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xd
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x4000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xe
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x4000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xe
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x8000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xf
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x8000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xf
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x10000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0x10
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x10000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0x10
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK 0x20000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT 0x11
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK 0x20000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT 0x11
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK 0x40000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT 0x12
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK 0x40000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT 0x12
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK 0x80000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT 0x13
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK 0x80000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT 0x13
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK 0x100000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT 0x14
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK 0x100000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT 0x14
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK 0x200000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT 0x15
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK 0x200000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT 0x15
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK 0x400000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT 0x16
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK 0x400000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT 0x16
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK 0x800000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT 0x17
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK 0x800000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT 0x17
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK 0x1000000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT 0x18
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK 0x1000000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT 0x18
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK 0x2000000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT 0x19
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK 0x2000000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT 0x19
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK 0x4000000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT 0x1a
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK 0x4000000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT 0x1a
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK 0x8000000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT 0x1b
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK 0x8000000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT 0x1b
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK 0x10000000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT 0x1c
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK 0x10000000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT 0x1c
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x1
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x2
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK 0x4
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x2
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK 0x8
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x3
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x10
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x20
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x40
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK 0x80
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x7
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK 0x100
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x8
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x200
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x400
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x800
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x1000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x2000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x4000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x8000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x10000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK 0x20000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK 0x40000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK 0x80000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK 0x100000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT 0x14
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK 0x200000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT 0x15
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK 0x400000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT 0x16
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK 0x800000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT 0x17
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK 0x1000000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK 0x2000000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK 0x4000000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1a
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK 0x8000000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1b
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK 0x10000000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1c
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x1
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x2
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x4
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x8
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x10
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x20
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x40
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x80
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x100
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x200
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x400
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x800
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x1000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x2000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x4000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x8000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x10000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK 0x20000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK 0x40000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK 0x80000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK 0x100000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK 0x200000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK 0x400000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK 0x800000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK 0x1000000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x2000000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x4000000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x8000000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1b
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x10000000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1c
+#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x10
+#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
+#define DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x100
+#define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
+#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x20000
+#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
+#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x7
+#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
+#define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x100
+#define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
+#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x10000
+#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
+#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x7000000
+#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
+#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0xff
+#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
+#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x100
+#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
+#define DP_CONFIG__DP_UDI_LANES_MASK 0x3
+#define DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x1
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x300
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x10000
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x100000
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
+#define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x1
+#define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x10
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x20
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x40
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x80
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
+#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x100
+#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
+#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x1000
+#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
+#define DP_MSA_MISC__DP_MSA_MISC1_MASK 0x78
+#define DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
+#define DP_MSA_MISC__DP_MSA_MISC2_MASK 0xff00
+#define DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
+#define DP_MSA_MISC__DP_MSA_MISC3_MASK 0xff0000
+#define DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
+#define DP_MSA_MISC__DP_MSA_MISC4_MASK 0xff000000
+#define DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
+#define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x1
+#define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
+#define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x100
+#define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
+#define DP_VID_TIMING__DP_VID_N_DIV_MASK 0xff000000
+#define DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
+#define DP_VID_N__DP_VID_N_MASK 0xffffff
+#define DP_VID_N__DP_VID_N__SHIFT 0x0
+#define DP_VID_M__DP_VID_M_MASK 0xffffff
+#define DP_VID_M__DP_VID_M__SHIFT 0x0
+#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x3ffff
+#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
+#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x1000000
+#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
+#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000
+#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
+#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x1
+#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
+#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0xfff
+#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
+#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x10000
+#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
+#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x1000000
+#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x1
+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x2
+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x4
+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x1
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x2
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x4
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x8
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
+#define DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x10000
+#define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
+#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x1000000
+#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
+#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x3
+#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
+#define DP_DPHY_SYM0__DPHY_SYM1_MASK 0x3ff
+#define DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
+#define DP_DPHY_SYM0__DPHY_SYM2_MASK 0xffc00
+#define DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
+#define DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3ff00000
+#define DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
+#define DP_DPHY_SYM1__DPHY_SYM4_MASK 0x3ff
+#define DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
+#define DP_DPHY_SYM1__DPHY_SYM5_MASK 0xffc00
+#define DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
+#define DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3ff00000
+#define DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
+#define DP_DPHY_SYM2__DPHY_SYM7_MASK 0x3ff
+#define DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
+#define DP_DPHY_SYM2__DPHY_SYM8_MASK 0xffc00
+#define DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x100
+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x10000
+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x1000000
+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x1
+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x30
+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00
+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
+#define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x1
+#define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
+#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x10
+#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
+#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x100
+#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
+#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x1
+#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
+#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x30
+#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
+#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0xff0000
+#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0xff
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0xff00
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0xff0000
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xff000000
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
+#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x3f
+#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
+#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x3f00
+#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x1
+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x100
+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x10000
+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
+#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x1
+#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
+#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x2
+#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x4
+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0xfff00
+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xfff00000
+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x7
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x10
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x100
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x1000
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
+#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x1
+#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
+#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x3fff0
+#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
+#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x3fff
+#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
+#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3fff0000
+#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
+#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x1
+#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
+#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x10
+#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
+#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x100
+#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
+#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x1000
+#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
+#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x10000
+#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
+#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x100000
+#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
+#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x200000
+#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
+#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x400000
+#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
+#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x800000
+#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
+#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x1000000
+#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
+#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000
+#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
+#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x1
+#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
+#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0xfff
+#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
+#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xffff0000
+#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0xffff
+#define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
+#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xffff0000
+#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x3fff
+#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
+#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xffff0000
+#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x100000
+#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
+#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x1000000
+#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
+#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000
+#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
+#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000
+#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
+#define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0xffffff
+#define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
+#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0xffffff
+#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
+#define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0xffffff
+#define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
+#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0xffffff
+#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x1
+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0xe
+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x10
+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
+#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x3f00
+#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x10000
+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
+#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x3ffffff
+#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
+#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xfc000000
+#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
+#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x1
+#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
+#define DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x7
+#define DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
+#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x3f00
+#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
+#define DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x70000
+#define DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
+#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3f000000
+#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
+#define DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x7
+#define DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
+#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x3f00
+#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
+#define DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x70000
+#define DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
+#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3f000000
+#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
+#define DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x7
+#define DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
+#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x3f00
+#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
+#define DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x70000
+#define DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
+#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3f000000
+#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
+#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x3
+#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
+#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x100
+#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
+#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x3ff
+#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
+#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x30000
+#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
+#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x1
+#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
+#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x10
+#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
+#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x100
+#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
+#define DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA_MASK 0x10000
+#define DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA__SHIFT 0x10
+#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK 0xff
+#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT 0x0
+#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX_MASK 0xff
+#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA__SHIFT 0x0
+#define AUX_CONTROL__AUX_EN_MASK 0x1
+#define AUX_CONTROL__AUX_EN__SHIFT 0x0
+#define AUX_CONTROL__AUX_LS_READ_EN_MASK 0x100
+#define AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
+#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x1000
+#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
+#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x10000
+#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
+#define AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x40000
+#define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
+#define AUX_CONTROL__AUX_HPD_SEL_MASK 0x700000
+#define AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
+#define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x1000000
+#define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
+#define AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000
+#define AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
+#define AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000
+#define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
+#define AUX_CONTROL__SPARE_0_MASK 0x40000000
+#define AUX_CONTROL__SPARE_0__SHIFT 0x1e
+#define AUX_CONTROL__SPARE_1_MASK 0x80000000
+#define AUX_CONTROL__SPARE_1__SHIFT 0x1f
+#define AUX_SW_CONTROL__AUX_SW_GO_MASK 0x1
+#define AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
+#define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x4
+#define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
+#define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0xf0
+#define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
+#define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x1f0000
+#define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
+#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x3
+#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
+#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0xc
+#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
+#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x100
+#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
+#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x400
+#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
+#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x10000
+#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
+#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x10000
+#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
+#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x20000
+#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
+#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x1000000
+#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
+#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x1000000
+#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
+#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x2000000
+#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x1
+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x2
+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x4
+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x10
+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x20
+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x40
+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x100
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x200
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x400
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x1000
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x2000
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x4000
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
+#define AUX_SW_STATUS__AUX_SW_DONE_MASK 0x1
+#define AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
+#define AUX_SW_STATUS__AUX_SW_REQ_MASK 0x2
+#define AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
+#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x70
+#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
+#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x80
+#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
+#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x100
+#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
+#define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x200
+#define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
+#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x400
+#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
+#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x800
+#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
+#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x1000
+#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x4000
+#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
+#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x20000
+#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
+#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x40000
+#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
+#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x80000
+#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
+#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x100000
+#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
+#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x400000
+#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
+#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x800000
+#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
+#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1f000000
+#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
+#define AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xc0000000
+#define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
+#define AUX_LS_STATUS__AUX_LS_DONE_MASK 0x1
+#define AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
+#define AUX_LS_STATUS__AUX_LS_REQ_MASK 0x2
+#define AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
+#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x70
+#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
+#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x80
+#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
+#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x100
+#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
+#define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x200
+#define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
+#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x400
+#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
+#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x800
+#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
+#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x1000
+#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x4000
+#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
+#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x20000
+#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
+#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x40000
+#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
+#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x80000
+#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
+#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x100000
+#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
+#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x400000
+#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
+#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x800000
+#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
+#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1f000000
+#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
+#define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000
+#define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
+#define AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000
+#define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
+#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000
+#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
+#define AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x1
+#define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
+#define AUX_SW_DATA__AUX_SW_DATA_MASK 0xff00
+#define AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
+#define AUX_SW_DATA__AUX_SW_INDEX_MASK 0x1f0000
+#define AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
+#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000
+#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+#define AUX_LS_DATA__AUX_LS_DATA_MASK 0xff00
+#define AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
+#define AUX_LS_DATA__AUX_LS_INDEX_MASK 0x1f0000
+#define AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x1
+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x30
+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x1ff0000
+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
+#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x7
+#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
+#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x3f00
+#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
+#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x70000
+#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x70
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x700
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x3000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x10000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x20000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x40000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x80000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x300000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x7000000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
+#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0xff
+#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
+#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x1
+#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
+#define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x70
+#define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
+#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x1ff0000
+#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
+#define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x7
+#define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
+#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x1f00
+#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
+#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x1f0000
+#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
+#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3fe00000
+#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x1
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x10
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0xf00
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0xf000
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x70000
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x100000
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0xc00000
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x3000000
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xf0000000
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x1f
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x1f00
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x30000
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x300000
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x1
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x10
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x100
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x1e00
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x10000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x100000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x200000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x400000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x800000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x1000000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x2000000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xf0000000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x1
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x2
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x70
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x80
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x100
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x200
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x400
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x800
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x1000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x4000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x20000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x40000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x80000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x100000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x400000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x800000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1f000000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
+#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW_MASK 0x1
+#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW__SHIFT 0x0
+#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_MASK 0xff00
+#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA__SHIFT 0x8
+#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_MASK 0x3f0000
+#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX__SHIFT 0x10
+#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE_MASK 0x80000000
+#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN_MASK 0x1
+#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN__SHIFT 0x0
+#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE_MASK 0xffff0
+#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE__SHIFT 0x4
+#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX_MASK 0xff
+#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX__SHIFT 0x0
+#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA_MASK 0xffffffff
+#define AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA__SHIFT 0x0
+#define DP_AUX_DEBUG_A__DP_AUX_DEBUG_A_MASK 0xffffffff
+#define DP_AUX_DEBUG_A__DP_AUX_DEBUG_A__SHIFT 0x0
+#define DP_AUX_DEBUG_B__DP_AUX_DEBUG_B_MASK 0xffffffff
+#define DP_AUX_DEBUG_B__DP_AUX_DEBUG_B__SHIFT 0x0
+#define DP_AUX_DEBUG_C__DP_AUX_DEBUG_C_MASK 0xffffffff
+#define DP_AUX_DEBUG_C__DP_AUX_DEBUG_C__SHIFT 0x0
+#define DP_AUX_DEBUG_D__DP_AUX_DEBUG_D_MASK 0xffffffff
+#define DP_AUX_DEBUG_D__DP_AUX_DEBUG_D__SHIFT 0x0
+#define DP_AUX_DEBUG_E__DP_AUX_DEBUG_E_MASK 0xffffffff
+#define DP_AUX_DEBUG_E__DP_AUX_DEBUG_E__SHIFT 0x0
+#define DP_AUX_DEBUG_F__DP_AUX_DEBUG_F_MASK 0xffffffff
+#define DP_AUX_DEBUG_F__DP_AUX_DEBUG_F__SHIFT 0x0
+#define DP_AUX_DEBUG_G__DP_AUX_DEBUG_G_MASK 0xffffffff
+#define DP_AUX_DEBUG_G__DP_AUX_DEBUG_G__SHIFT 0x0
+#define DP_AUX_DEBUG_H__DP_AUX_DEBUG_H_MASK 0xffffffff
+#define DP_AUX_DEBUG_H__DP_AUX_DEBUG_H__SHIFT 0x0
+#define DP_AUX_DEBUG_I__DP_AUX_DEBUG_I_MASK 0xffffffff
+#define DP_AUX_DEBUG_I__DP_AUX_DEBUG_I__SHIFT 0x0
+#define DP_AUX_DEBUG_J__DP_AUX_DEBUG_J_MASK 0xffffffff
+#define DP_AUX_DEBUG_J__DP_AUX_DEBUG_J__SHIFT 0x0
+#define DP_AUX_DEBUG_K__DP_AUX_DEBUG_K_MASK 0xffffffff
+#define DP_AUX_DEBUG_K__DP_AUX_DEBUG_K__SHIFT 0x0
+#define DP_AUX_DEBUG_L__DP_AUX_DEBUG_L_MASK 0xffffffff
+#define DP_AUX_DEBUG_L__DP_AUX_DEBUG_L__SHIFT 0x0
+#define DP_AUX_DEBUG_M__DP_AUX_DEBUG_M_MASK 0xffffffff
+#define DP_AUX_DEBUG_M__DP_AUX_DEBUG_M__SHIFT 0x0
+#define DP_AUX_DEBUG_N__DP_AUX_DEBUG_N_MASK 0xffffffff
+#define DP_AUX_DEBUG_N__DP_AUX_DEBUG_N__SHIFT 0x0
+#define DP_AUX_DEBUG_O__DP_AUX_DEBUG_O_MASK 0xffffffff
+#define DP_AUX_DEBUG_O__DP_AUX_DEBUG_O__SHIFT 0x0
+#define DP_AUX_DEBUG_P__DP_AUX_DEBUG_P_MASK 0xffffffff
+#define DP_AUX_DEBUG_P__DP_AUX_DEBUG_P__SHIFT 0x0
+#define DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q_MASK 0xffffffff
+#define DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q__SHIFT 0x0
+#define DVO_ENABLE__DVO_ENABLE_MASK 0x1
+#define DVO_ENABLE__DVO_ENABLE__SHIFT 0x0
+#define DVO_ENABLE__DVO_PIXEL_WIDTH_MASK 0x30
+#define DVO_ENABLE__DVO_PIXEL_WIDTH__SHIFT 0x4
+#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK 0x7
+#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT 0x0
+#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK 0x70000
+#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT 0x10
+#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK 0x3
+#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT 0x0
+#define DVO_OUTPUT__DVO_CLOCK_MODE_MASK 0x100
+#define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT 0x8
+#define DVO_CONTROL__DVO_RATE_SELECT_MASK 0x1
+#define DVO_CONTROL__DVO_RATE_SELECT__SHIFT 0x0
+#define DVO_CONTROL__DVO_SDRCLK_SEL_MASK 0x2
+#define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT 0x1
+#define DVO_CONTROL__DVO_DVPDATA_WIDTH_MASK 0x30
+#define DVO_CONTROL__DVO_DVPDATA_WIDTH__SHIFT 0x4
+#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK 0x100
+#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT 0x8
+#define DVO_CONTROL__DVO_RESET_FIFO_MASK 0x10000
+#define DVO_CONTROL__DVO_RESET_FIFO__SHIFT 0x10
+#define DVO_CONTROL__DVO_SYNC_PHASE_MASK 0x20000
+#define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT 0x11
+#define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK 0x40000
+#define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT 0x12
+#define DVO_CONTROL__DVO_HSYNC_POLARITY_MASK 0x100000
+#define DVO_CONTROL__DVO_HSYNC_POLARITY__SHIFT 0x14
+#define DVO_CONTROL__DVO_VSYNC_POLARITY_MASK 0x200000
+#define DVO_CONTROL__DVO_VSYNC_POLARITY__SHIFT 0x15
+#define DVO_CONTROL__DVO_DE_POLARITY_MASK 0x400000
+#define DVO_CONTROL__DVO_DE_POLARITY__SHIFT 0x16
+#define DVO_CONTROL__DVO_COLOR_FORMAT_MASK 0x3000000
+#define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT 0x18
+#define DVO_CONTROL__DVO_CTL3_MASK 0x80000000
+#define DVO_CONTROL__DVO_CTL3__SHIFT 0x1f
+#define DVO_CRC_EN__DVO_CRC2_EN_MASK 0x10000
+#define DVO_CRC_EN__DVO_CRC2_EN__SHIFT 0x10
+#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK 0x7ffffff
+#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT 0x0
+#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK 0x7ffffff
+#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT 0x0
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK 0x1
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT 0x0
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK 0xfc
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK 0x100
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT 0x8
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK 0xf0000
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK 0x3c00000
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK 0x20000000
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT 0x1d
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX_MASK 0xff
+#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA__SHIFT 0x0
+#define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x1
+#define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x0
+#define FBC_CNTL__FBC_SRC_SEL_MASK 0xe
+#define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x1
+#define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x30000
+#define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x10
+#define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x2000000
+#define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x19
+#define FBC_CNTL__FBC_EN_MASK 0x80000000
+#define FBC_CNTL__FBC_EN__SHIFT 0x1f
+#define FBC_IDLE_MASK__FBC_IDLE_MASK_MASK 0xffffffff
+#define FBC_IDLE_MASK__FBC_IDLE_MASK__SHIFT 0x0
+#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xffffffff
+#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x0
+#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x1f
+#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x0
+#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x80
+#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x7
+#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x1f00
+#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x8
+#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0xf
+#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x0
+#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x10000
+#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x10
+#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x20000
+#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x11
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x40000
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x12
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x80000
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x13
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x100000
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x14
+#define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x1
+#define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x0
+#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x100
+#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x8
+#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x200
+#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x9
+#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x400
+#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0xa
+#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x800
+#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0xb
+#define FBC_COMP_MODE__FBC_IND_EN_MASK 0x10000
+#define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x10
+#define FBC_DEBUG0__FBC_PERF_MUX0_MASK 0xff
+#define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT 0x0
+#define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0xff00
+#define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT 0x8
+#define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK 0x10000
+#define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT 0x10
+#define FBC_DEBUG0__FBC_DEBUG0_MASK 0xfe0000
+#define FBC_DEBUG0__FBC_DEBUG0__SHIFT 0x11
+#define FBC_DEBUG0__FBC_DEBUG_MUX_MASK 0xff000000
+#define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT 0x18
+#define FBC_DEBUG1__FBC_DEBUG1_MASK 0xffffffff
+#define FBC_DEBUG1__FBC_DEBUG1__SHIFT 0x0
+#define FBC_DEBUG2__FBC_DEBUG2_MASK 0xffffffff
+#define FBC_DEBUG2__FBC_DEBUG2__SHIFT 0x0
+#define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0xffffff
+#define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x0
+#define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0xffffff
+#define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x0
+#define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0xffffff
+#define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x0
+#define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0xffffff
+#define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x0
+#define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0xffffff
+#define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x0
+#define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0xffffff
+#define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x0
+#define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0xffffff
+#define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x0
+#define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0xffffff
+#define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x0
+#define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0xffffff
+#define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x0
+#define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0xffffff
+#define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x0
+#define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0xffffff
+#define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x0
+#define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0xffffff
+#define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x0
+#define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0xffffff
+#define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x0
+#define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0xffffff
+#define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x0
+#define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0xffffff
+#define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x0
+#define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0xffffff
+#define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x0
+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0x3ff
+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x0
+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0x3ff0000
+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x10
+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0x3ff
+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x0
+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0x3ff0000
+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x10
+#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0xf0000
+#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x10
+#define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x3
+#define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x0
+#define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x8
+#define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x3
+#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0xf0
+#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x4
+#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x300
+#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x8
+#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x400
+#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0xa
+#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x800
+#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0xb
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK 0x3ff
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT 0x0
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA_MASK 0x10000
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA__SHIFT 0x10
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA_MASK 0x20000
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA__SHIFT 0x11
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK 0x80000000
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT 0x1f
+#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK 0xffffffff
+#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT 0x0
+#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK 0xffffffff
+#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT 0x0
+#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI_MASK 0xff
+#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI__SHIFT 0x0
+#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI_MASK 0xff
+#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI__SHIFT 0x0
+#define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x3
+#define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x0
+#define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x4
+#define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x2
+#define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x8
+#define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x3
+#define FBC_MISC__FBC_ERROR_PIXEL_MASK 0xf0
+#define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x4
+#define FBC_MISC__FBC_DIVIDE_X_MASK 0x300
+#define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x8
+#define FBC_MISC__FBC_DIVIDE_Y_MASK 0x400
+#define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0xa
+#define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x800
+#define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0xb
+#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x1000
+#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0xc
+#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x10000
+#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x10
+#define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x100000
+#define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x14
+#define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x200000
+#define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x15
+#define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0x1f000000
+#define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x18
+#define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x1
+#define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x0
+#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK 0xff
+#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT 0x0
+#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK 0xffffffff
+#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT 0x0
+#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0xffff
+#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
+#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xffff0000
+#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
+#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0xffff
+#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
+#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xffff0000
+#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
+#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0xffff
+#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
+#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xffff0000
+#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
+#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x1
+#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
+#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x10
+#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
+#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x1
+#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
+#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x10
+#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
+#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0xf00
+#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
+#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x3000
+#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
+#define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x10000
+#define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
+#define FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x20000
+#define FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x11
+#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x40000
+#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x12
+#define FMT_CONTROL__FMT_SRC_SELECT_MASK 0x7000000
+#define FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN_MASK 0x1
+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN__SHIFT 0x0
+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR_MASK 0x700
+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR__SHIFT 0x8
+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT_MASK 0xf000
+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT__SHIFT 0xc
+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKB_ONLY_MASK 0x10000
+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKB_ONLY__SHIFT 0x10
+#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0_MASK 0xffff
+#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0__SHIFT 0x0
+#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1_MASK 0xffff0000
+#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1__SHIFT 0x10
+#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2_MASK 0xffff
+#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2__SHIFT 0x0
+#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3_MASK 0xffff0000
+#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3__SHIFT 0x10
+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x1
+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x2
+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x30
+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x100
+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x600
+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x1800
+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
+#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x2000
+#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
+#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x4000
+#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
+#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x8000
+#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x10000
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x60000
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x600000
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x1000000
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x2000000
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
+#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0xc000000
+#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
+#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000
+#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
+#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xc0000000
+#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
+#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0xff
+#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
+#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xffff0000
+#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
+#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0xff
+#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
+#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xffff0000
+#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
+#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0xff
+#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
+#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xffff0000
+#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
+#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT_MASK 0x1
+#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT__SHIFT 0x0
+#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0_MASK 0x10
+#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0__SHIFT 0x4
+#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX_MASK 0xffffffff
+#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SHIFT 0x0
+#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX_MASK 0xffffffff
+#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SHIFT 0x0
+#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x1
+#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
+#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x70000
+#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
+#define FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x1
+#define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
+#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x2
+#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
+#define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x10
+#define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
+#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x100
+#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8
+#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x3000
+#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
+#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000
+#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x100000
+#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
+#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x1000000
+#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
+#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0xffff
+#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
+#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xffff0000
+#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
+#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0xffff
+#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
+#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xffff0000
+#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
+#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0xffff
+#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
+#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xffff0000
+#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
+#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0xffff
+#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
+#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xffff0000
+#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
+#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK 0x3
+#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT 0x0
+#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX_MASK 0xff
+#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX__SHIFT 0x0
+#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA_MASK 0xffffffff
+#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA__SHIFT 0x0
+#define FMT_DEBUG0__FMT_DEBUG0_MASK 0xffffffff
+#define FMT_DEBUG0__FMT_DEBUG0__SHIFT 0x0
+#define FMT_DEBUG1__FMT_DEBUG1_MASK 0xffffffff
+#define FMT_DEBUG1__FMT_DEBUG1__SHIFT 0x0
+#define FMT_DEBUG2__FMT_DEBUG2_MASK 0xffffffff
+#define FMT_DEBUG2__FMT_DEBUG2__SHIFT 0x0
+#define FMT_DEBUG_ID__FMT_DEBUG_ID_MASK 0xffffffff
+#define FMT_DEBUG_ID__FMT_DEBUG_ID__SHIFT 0x0
+#define LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3
+#define LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
+#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4
+#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
+#define LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8
+#define LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
+#define LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x10
+#define LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
+#define LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x20
+#define LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
+#define LB_DATA_FORMAT__PREFETCH_MASK 0x1000
+#define LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
+#define LB_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000
+#define LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
+#define LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000
+#define LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
+#define LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0xfff
+#define LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
+#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000
+#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000
+#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
+#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0xfff
+#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
+#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff
+#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
+#define LB_VLINE_START_END__VLINE_START_MASK 0x3fff
+#define LB_VLINE_START_END__VLINE_START__SHIFT 0x0
+#define LB_VLINE_START_END__VLINE_END_MASK 0x7fff0000
+#define LB_VLINE_START_END__VLINE_END__SHIFT 0x10
+#define LB_VLINE_START_END__VLINE_INV_MASK 0x80000000
+#define LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
+#define LB_VLINE2_START_END__VLINE2_START_MASK 0x3fff
+#define LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
+#define LB_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000
+#define LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
+#define LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000
+#define LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
+#define LB_V_COUNTER__V_COUNTER_MASK 0x7fff
+#define LB_V_COUNTER__V_COUNTER__SHIFT 0x0
+#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff
+#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
+#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1
+#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
+#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10
+#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
+#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100
+#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
+#define LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1
+#define LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
+#define LB_VLINE_STATUS__VLINE_ACK_MASK 0x10
+#define LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
+#define LB_VLINE_STATUS__VLINE_STAT_MASK 0x1000
+#define LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
+#define LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000
+#define LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
+#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000
+#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
+#define LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1
+#define LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
+#define LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x10
+#define LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
+#define LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000
+#define LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
+#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000
+#define LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
+#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000
+#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
+#define LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1
+#define LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
+#define LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x10
+#define LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
+#define LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000
+#define LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
+#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000
+#define LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
+#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000
+#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3
+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10
+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00
+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
+#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000
+#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
+#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0
+#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
+#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0
+#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
+#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0
+#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
+#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1
+#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
+#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100
+#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
+#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0
+#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
+#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0
+#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
+#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0
+#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
+#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0
+#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
+#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0
+#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
+#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0
+#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
+#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f
+#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
+#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00
+#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
+#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000
+#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
+#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000
+#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
+#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff
+#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
+#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000
+#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
+#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff
+#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
+#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000
+#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000
+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000
+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000
+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
+#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1
+#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
+#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x3
+#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0xf
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x10
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x100
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x1000
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x3
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x7fff00
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3f000000
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
+#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x3
+#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x100
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x1000
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x10000
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x100000
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
+#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000
+#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
+#define LB_DEBUG__LB_DEBUG_MASK 0xffffffff
+#define LB_DEBUG__LB_DEBUG__SHIFT 0x0
+#define LB_DEBUG2__LB_DEBUG2_MASK 0xffffffff
+#define LB_DEBUG2__LB_DEBUG2__SHIFT 0x0
+#define LB_DEBUG3__LB_DEBUG3_MASK 0xffffffff
+#define LB_DEBUG3__LB_DEBUG3__SHIFT 0x0
+#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff
+#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0
+#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff
+#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0
+#define LBV_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3
+#define LBV_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
+#define LBV_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4
+#define LBV_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
+#define LBV_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8
+#define LBV_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
+#define LBV_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x10
+#define LBV_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
+#define LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x20
+#define LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
+#define LBV_DATA_FORMAT__DITHER_EN_MASK 0x40
+#define LBV_DATA_FORMAT__DITHER_EN__SHIFT 0x6
+#define LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN_MASK 0x80
+#define LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN__SHIFT 0x7
+#define LBV_DATA_FORMAT__PREFETCH_MASK 0x1000
+#define LBV_DATA_FORMAT__PREFETCH__SHIFT 0xc
+#define LBV_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000
+#define LBV_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
+#define LBV_DATA_FORMAT__ALPHA_EN_MASK 0x80000000
+#define LBV_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
+#define LBV_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0xfff
+#define LBV_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
+#define LBV_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000
+#define LBV_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+#define LBV_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000
+#define LBV_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
+#define LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0xfff
+#define LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
+#define LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff
+#define LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
+#define LBV_VLINE_START_END__VLINE_START_MASK 0x3fff
+#define LBV_VLINE_START_END__VLINE_START__SHIFT 0x0
+#define LBV_VLINE_START_END__VLINE_END_MASK 0x7fff0000
+#define LBV_VLINE_START_END__VLINE_END__SHIFT 0x10
+#define LBV_VLINE_START_END__VLINE_INV_MASK 0x80000000
+#define LBV_VLINE_START_END__VLINE_INV__SHIFT 0x1f
+#define LBV_VLINE2_START_END__VLINE2_START_MASK 0x3fff
+#define LBV_VLINE2_START_END__VLINE2_START__SHIFT 0x0
+#define LBV_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000
+#define LBV_VLINE2_START_END__VLINE2_END__SHIFT 0x10
+#define LBV_VLINE2_START_END__VLINE2_INV_MASK 0x80000000
+#define LBV_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
+#define LBV_V_COUNTER__V_COUNTER_MASK 0x7fff
+#define LBV_V_COUNTER__V_COUNTER__SHIFT 0x0
+#define LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff
+#define LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
+#define LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA_MASK 0x7fff
+#define LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA__SHIFT 0x0
+#define LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA_MASK 0x7fff
+#define LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA__SHIFT 0x0
+#define LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1
+#define LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
+#define LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10
+#define LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
+#define LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100
+#define LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
+#define LBV_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1
+#define LBV_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
+#define LBV_VLINE_STATUS__VLINE_ACK_MASK 0x10
+#define LBV_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
+#define LBV_VLINE_STATUS__VLINE_STAT_MASK 0x1000
+#define LBV_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
+#define LBV_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000
+#define LBV_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
+#define LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000
+#define LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
+#define LBV_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1
+#define LBV_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
+#define LBV_VLINE2_STATUS__VLINE2_ACK_MASK 0x10
+#define LBV_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
+#define LBV_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000
+#define LBV_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
+#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000
+#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
+#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000
+#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
+#define LBV_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1
+#define LBV_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
+#define LBV_VBLANK_STATUS__VBLANK_ACK_MASK 0x10
+#define LBV_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
+#define LBV_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000
+#define LBV_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
+#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000
+#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
+#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000
+#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
+#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3
+#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
+#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10
+#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
+#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00
+#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
+#define LBV_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000
+#define LBV_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
+#define LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0
+#define LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
+#define LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0
+#define LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
+#define LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0
+#define LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
+#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1
+#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
+#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100
+#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
+#define LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0
+#define LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
+#define LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0
+#define LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
+#define LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0
+#define LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
+#define LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0
+#define LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
+#define LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0
+#define LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
+#define LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0
+#define LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
+#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f
+#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
+#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00
+#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
+#define LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000
+#define LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
+#define LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000
+#define LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
+#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff
+#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
+#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000
+#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
+#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff
+#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
+#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000
+#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf
+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10
+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100
+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000
+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
+#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000
+#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
+#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000
+#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
+#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000
+#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
+#define LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1
+#define LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
+#define LBV_DEBUG__LB_DEBUG_MASK 0xffffffff
+#define LBV_DEBUG__LB_DEBUG__SHIFT 0x0
+#define LBV_DEBUG2__LB_DEBUG2_MASK 0xffffffff
+#define LBV_DEBUG2__LB_DEBUG2__SHIFT 0x0
+#define LBV_DEBUG3__LB_DEBUG3_MASK 0xffffffff
+#define LBV_DEBUG3__LB_DEBUG3__SHIFT 0x0
+#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff
+#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0
+#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define LBV_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff
+#define LBV_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0
+#define MVP_CONTROL1__MVP_EN_MASK 0x1
+#define MVP_CONTROL1__MVP_EN__SHIFT 0x0
+#define MVP_CONTROL1__MVP_MIXER_MODE_MASK 0x70
+#define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT 0x4
+#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK 0x100
+#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT 0x8
+#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK 0x200
+#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT 0x9
+#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK 0x400
+#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT 0xa
+#define MVP_CONTROL1__MVP_RATE_CONTROL_MASK 0x1000
+#define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT 0xc
+#define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK 0x10000
+#define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT 0x10
+#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK 0x300000
+#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT 0x14
+#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK 0x1000000
+#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT 0x18
+#define MVP_CONTROL1__MVP_30BPP_EN_MASK 0x10000000
+#define MVP_CONTROL1__MVP_30BPP_EN__SHIFT 0x1c
+#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK 0x40000000
+#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT 0x1e
+#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK 0x80000000
+#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT 0x1f
+#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK 0x1
+#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT 0x0
+#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK 0x10
+#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT 0x4
+#define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK 0x100
+#define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT 0x8
+#define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK 0x1000
+#define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT 0xc
+#define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK 0x10000
+#define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT 0x10
+#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK 0x100000
+#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT 0x14
+#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK 0x1000000
+#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT 0x18
+#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK 0x10000000
+#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT 0x1c
+#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK 0xff
+#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT 0x0
+#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK 0xff00
+#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT 0x8
+#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK 0xff0000
+#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT 0x10
+#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK 0xff
+#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT 0x0
+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK 0x100
+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT 0x8
+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK 0x1000
+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT 0xc
+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK 0x10000
+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT 0x10
+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK 0x100000
+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT 0x14
+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK 0x1000000
+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT 0x18
+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK 0x10000000
+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT 0x1c
+#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK 0x40000000
+#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT 0x1e
+#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK 0x80000000
+#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT 0x1f
+#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK 0x1fff
+#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT 0x0
+#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK 0x1fff0000
+#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT 0x10
+#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK 0x1
+#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT 0x0
+#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK 0x10
+#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT 0x4
+#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK 0xffffff00
+#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT 0x8
+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK 0x3ff
+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT 0x0
+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK 0xffc00
+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT 0xa
+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK 0x3ff00000
+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT 0x14
+#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK 0xff
+#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT 0x0
+#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK 0xff00
+#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT 0x8
+#define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK 0xff0000
+#define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT 0x10
+#define MVP_CRC_CNTL__MVP_CRC_EN_MASK 0x10000000
+#define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT 0x1c
+#define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK 0x20000000
+#define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT 0x1d
+#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK 0x40000000
+#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT 0x1e
+#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK 0xffff
+#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT 0x0
+#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK 0xffff0000
+#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT 0x10
+#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK 0xffff
+#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT 0x0
+#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK 0x1
+#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT 0x0
+#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x10
+#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x4
+#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK 0x100
+#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT 0x8
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK 0x1000
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT 0xc
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK 0x10000
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT 0x10
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK 0x100000
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT 0x14
+#define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK 0x1000000
+#define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT 0x18
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK 0x10000000
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT 0x1c
+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK 0x1fff
+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT 0x0
+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK 0x1fff0000
+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT 0x10
+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK 0x80000000
+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT 0x1f
+#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK 0x1fff
+#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT 0x0
+#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK 0x80000000
+#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT 0x1f
+#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN_MASK 0x1
+#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN__SHIFT 0x0
+#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK 0x2
+#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN__SHIFT 0x1
+#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL_MASK 0x4
+#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT 0x2
+#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL_MASK 0x8
+#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL__SHIFT 0x3
+#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP_MASK 0x10
+#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP__SHIFT 0x4
+#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP_MASK 0x20
+#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP__SHIFT 0x5
+#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR_MASK 0x40
+#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR__SHIFT 0x6
+#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY_MASK 0x80
+#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY__SHIFT 0x7
+#define MVP_DEBUG__MVP_DEBUG_BITS_MASK 0xffffff00
+#define MVP_DEBUG__MVP_DEBUG_BITS__SHIFT 0x8
+#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK 0xff
+#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT 0x0
+#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK 0xffffffff
+#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT 0x0
+#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION_MASK 0x6
+#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1
+#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION_MASK 0x6
+#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1
+#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK 0x1
+#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT 0x0
+#define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK 0x1fffffe
+#define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT 0x1
+#define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK 0x1
+#define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT 0x0
+#define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK 0x1fffffe
+#define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT 0x1
+#define MVP_DEBUG_13__IDED_START_READ_B_MASK 0x2000000
+#define MVP_DEBUG_13__IDED_START_READ_B__SHIFT 0x19
+#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK 0x4000000
+#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT 0x1a
+#define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK 0x38000000
+#define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT 0x1b
+#define MVP_DEBUG_14__IDEE_READ_ADD_MASK 0x7
+#define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT 0x0
+#define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK 0x38
+#define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT 0x3
+#define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK 0x1c0
+#define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT 0x6
+#define MVP_DEBUG_14__IDEE_START_READ_MASK 0x200
+#define MVP_DEBUG_14__IDEE_START_READ__SHIFT 0x9
+#define MVP_DEBUG_14__IDEE_START_READ_B_MASK 0x400
+#define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT 0xa
+#define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK 0x800
+#define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT 0xb
+#define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK 0x1000
+#define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT 0xc
+#define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK 0x2000
+#define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT 0xd
+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK 0x4000
+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT 0xe
+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK 0x8000
+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT 0xf
+#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK 0x10000
+#define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT 0x10
+#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK 0x20000
+#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT 0x11
+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK 0x40000
+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT 0x12
+#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK 0x80000
+#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT 0x13
+#define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK 0x100000
+#define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT 0x14
+#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK 0x1
+#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT 0x0
+#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK 0xfffffff0
+#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT 0x4
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK 0x1
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT 0x0
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK 0x2
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT 0x1
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK 0x4
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT 0x2
+#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK 0x8
+#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT 0x3
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK 0xff0
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT 0x4
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK 0x1000
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT 0xc
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK 0x2000
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT 0xd
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK 0xff0000
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT 0x10
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK 0xff000000
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT 0x18
+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK 0x1
+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT 0x0
+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK 0x2
+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x1
+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK 0xfffffffc
+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT 0x2
+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0xf
+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0xf00
+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x70000
+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+#define SCL_MODE__SCL_MODE_MASK 0x3
+#define SCL_MODE__SCL_MODE__SHIFT 0x0
+#define SCL_MODE__SCL_PSCL_EN_MASK 0x10
+#define SCL_MODE__SCL_PSCL_EN__SHIFT 0x4
+#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7
+#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
+#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0xf00
+#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
+#define SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1
+#define SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+#define SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x10
+#define SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
+#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x3
+#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
+#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf
+#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00
+#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1
+#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
+#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000
+#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
+#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x1
+#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
+#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100
+#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff
+#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff
+#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000
+#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x1
+#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
+#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100
+#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff
+#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff
+#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000
+#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff
+#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000
+#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff
+#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
+#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000
+#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+#define SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x1
+#define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+#define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100
+#define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
+#define SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000
+#define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
+#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000
+#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
+#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x7
+#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
+#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x10
+#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
+#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x700
+#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
+#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x1000
+#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
+#define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1
+#define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x1
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x100
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x1000
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x10000
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
+#define VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x3fff
+#define VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
+#define VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3fff0000
+#define VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
+#define VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff
+#define VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
+#define VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000
+#define VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
+#define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x3fff
+#define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
+#define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3fff0000
+#define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
+#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff
+#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000
+#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff
+#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000
+#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1
+#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
+#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10
+#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
+#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80
+#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
+#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff
+#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
+#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff
+#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
+#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000
+#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
+#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1
+#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
+#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1
+#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0
+#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6
+#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1
+#define SCL_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8
+#define SCL_DEBUG2__SCL_DEBUG2__SHIFT 0x3
+#define SCL_DEBUG__SCL_DEBUG_MASK 0xffffffff
+#define SCL_DEBUG__SCL_DEBUG__SHIFT 0x0
+#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff
+#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0
+#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff
+#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0
+#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x3
+#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
+#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x7f00
+#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
+#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x30000
+#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff
+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000
+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000
+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000
+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+#define SCLV_MODE__SCL_MODE_MASK 0x1
+#define SCLV_MODE__SCL_MODE__SHIFT 0x0
+#define SCLV_MODE__SCL_PSCL_EN_MASK 0x10
+#define SCLV_MODE__SCL_PSCL_EN__SHIFT 0x4
+#define SCLV_MODE__SCL_INTERLACE_SOURCE_MASK 0x300
+#define SCLV_MODE__SCL_INTERLACE_SOURCE__SHIFT 0x8
+#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7
+#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
+#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x70
+#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x4
+#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C_MASK 0x700
+#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C__SHIFT 0x8
+#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C_MASK 0x7000
+#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C__SHIFT 0xc
+#define SCLV_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1
+#define SCLV_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+#define SCLV_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x10
+#define SCLV_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
+#define SCLV_CONTROL__SCL_TOTAL_PHASE_MASK 0x100
+#define SCLV_CONTROL__SCL_TOTAL_PHASE__SHIFT 0x8
+#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf
+#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00
+#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1
+#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
+#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000
+#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
+#define SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100
+#define SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff
+#define SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff
+#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000
+#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+#define SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x3ffffff
+#define SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0
+#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0xffffff
+#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0
+#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0xf000000
+#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18
+#define SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100
+#define SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff
+#define SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff
+#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000
+#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff
+#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000
+#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+#define SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x3ffffff
+#define SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0
+#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0xffffff
+#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0
+#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x7000000
+#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18
+#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0xffffff
+#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0
+#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x7000000
+#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18
+#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff
+#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
+#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000
+#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+#define SCLV_UPDATE__SCL_UPDATE_PENDING_MASK 0x1
+#define SCLV_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+#define SCLV_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100
+#define SCLV_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
+#define SCLV_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000
+#define SCLV_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
+#define SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000
+#define SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
+#define SCLV_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1
+#define SCLV_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
+#define SCLV_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff
+#define SCLV_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
+#define SCLV_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000
+#define SCLV_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
+#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x3fff
+#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
+#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3fff0000
+#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
+#define SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x1fff
+#define SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
+#define SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x1fff0000
+#define SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
+#define SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C_MASK 0x3fff
+#define SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C__SHIFT 0x0
+#define SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C_MASK 0x3fff0000
+#define SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C__SHIFT 0x10
+#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C_MASK 0x3fff
+#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C__SHIFT 0x0
+#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C_MASK 0x3fff0000
+#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C__SHIFT 0x10
+#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C_MASK 0x1fff
+#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C__SHIFT 0x0
+#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C_MASK 0x1fff0000
+#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C__SHIFT 0x10
+#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff
+#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000
+#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff
+#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000
+#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1
+#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
+#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10
+#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
+#define SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80
+#define SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
+#define SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff
+#define SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
+#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff
+#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
+#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000
+#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
+#define SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1
+#define SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
+#define SCLV_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1
+#define SCLV_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0
+#define SCLV_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6
+#define SCLV_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1
+#define SCLV_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8
+#define SCLV_DEBUG2__SCL_DEBUG2__SHIFT 0x3
+#define SCLV_DEBUG__SCL_DEBUG_MASK 0xffffffff
+#define SCLV_DEBUG__SCL_DEBUG__SHIFT 0x0
+#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff
+#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0
+#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define SCLV_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff
+#define SCLV_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0
+#define COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING_MASK 0x1
+#define COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING__SHIFT 0x0
+#define COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN_MASK 0x2
+#define COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN__SHIFT 0x1
+#define COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK_MASK 0x10000
+#define COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK__SHIFT 0x10
+#define COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
+#define COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE_MASK 0x3
+#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE__SHIFT 0x0
+#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE_MASK 0xc
+#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE__SHIFT 0x2
+#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE_MASK 0x10
+#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE__SHIFT 0x4
+#define INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A_MASK 0xffff
+#define INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A__SHIFT 0x0
+#define INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A_MASK 0xffff0000
+#define INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A__SHIFT 0x10
+#define INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A_MASK 0xffff
+#define INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A__SHIFT 0x0
+#define INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A_MASK 0xffff0000
+#define INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A__SHIFT 0x10
+#define INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A_MASK 0xffff
+#define INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A__SHIFT 0x0
+#define INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A_MASK 0xffff0000
+#define INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A__SHIFT 0x10
+#define INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A_MASK 0xffff
+#define INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A__SHIFT 0x0
+#define INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A_MASK 0xffff0000
+#define INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A__SHIFT 0x10
+#define INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A_MASK 0xffff
+#define INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A__SHIFT 0x0
+#define INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A_MASK 0xffff0000
+#define INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A__SHIFT 0x10
+#define INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A_MASK 0xffff
+#define INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A__SHIFT 0x0
+#define INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A_MASK 0xffff0000
+#define INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A__SHIFT 0x10
+#define INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B_MASK 0xffff
+#define INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B__SHIFT 0x0
+#define INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B_MASK 0xffff0000
+#define INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B__SHIFT 0x10
+#define INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B_MASK 0xffff
+#define INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B__SHIFT 0x0
+#define INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B_MASK 0xffff0000
+#define INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B__SHIFT 0x10
+#define INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B_MASK 0xffff
+#define INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B__SHIFT 0x0
+#define INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B_MASK 0xffff0000
+#define INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B__SHIFT 0x10
+#define INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B_MASK 0xffff
+#define INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B__SHIFT 0x0
+#define INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B_MASK 0xffff0000
+#define INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B__SHIFT 0x10
+#define INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B_MASK 0xffff
+#define INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B__SHIFT 0x0
+#define INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B_MASK 0xffff0000
+#define INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B__SHIFT 0x10
+#define INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B_MASK 0xffff
+#define INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B__SHIFT 0x0
+#define INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B_MASK 0xffff0000
+#define INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B__SHIFT 0x10
+#define PRESCALE_CONTROL__PRESCALE_MODE_MASK 0x3
+#define PRESCALE_CONTROL__PRESCALE_MODE__SHIFT 0x0
+#define PRESCALE_VALUES_R__PRESCALE_BIAS_R_MASK 0xffff
+#define PRESCALE_VALUES_R__PRESCALE_BIAS_R__SHIFT 0x0
+#define PRESCALE_VALUES_R__PRESCALE_SCALE_R_MASK 0xffff0000
+#define PRESCALE_VALUES_R__PRESCALE_SCALE_R__SHIFT 0x10
+#define PRESCALE_VALUES_G__PRESCALE_BIAS_G_MASK 0xffff
+#define PRESCALE_VALUES_G__PRESCALE_BIAS_G__SHIFT 0x0
+#define PRESCALE_VALUES_G__PRESCALE_SCALE_G_MASK 0xffff0000
+#define PRESCALE_VALUES_G__PRESCALE_SCALE_G__SHIFT 0x10
+#define PRESCALE_VALUES_B__PRESCALE_BIAS_B_MASK 0xffff
+#define PRESCALE_VALUES_B__PRESCALE_BIAS_B__SHIFT 0x0
+#define PRESCALE_VALUES_B__PRESCALE_SCALE_B_MASK 0xffff0000
+#define PRESCALE_VALUES_B__PRESCALE_SCALE_B__SHIFT 0x10
+#define COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE_MASK 0x7
+#define COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE__SHIFT 0x0
+#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A_MASK 0xffff
+#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A__SHIFT 0x0
+#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A_MASK 0xffff0000
+#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A__SHIFT 0x10
+#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A_MASK 0xffff
+#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A__SHIFT 0x0
+#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A_MASK 0xffff0000
+#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A__SHIFT 0x10
+#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A_MASK 0xffff
+#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A__SHIFT 0x0
+#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A_MASK 0xffff0000
+#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A__SHIFT 0x10
+#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A_MASK 0xffff
+#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A__SHIFT 0x0
+#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A_MASK 0xffff0000
+#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A__SHIFT 0x10
+#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A_MASK 0xffff
+#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A__SHIFT 0x0
+#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A_MASK 0xffff0000
+#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A__SHIFT 0x10
+#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A_MASK 0xffff
+#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A__SHIFT 0x0
+#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A_MASK 0xffff0000
+#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A__SHIFT 0x10
+#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B_MASK 0xffff
+#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B__SHIFT 0x0
+#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B_MASK 0xffff0000
+#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B__SHIFT 0x10
+#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B_MASK 0xffff
+#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B__SHIFT 0x0
+#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B_MASK 0xffff0000
+#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B__SHIFT 0x10
+#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B_MASK 0xffff
+#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B__SHIFT 0x0
+#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B_MASK 0xffff0000
+#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B__SHIFT 0x10
+#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B_MASK 0xffff
+#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B__SHIFT 0x0
+#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B_MASK 0xffff0000
+#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B__SHIFT 0x10
+#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B_MASK 0xffff
+#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B__SHIFT 0x0
+#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B_MASK 0xffff0000
+#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B__SHIFT 0x10
+#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B_MASK 0xffff
+#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B__SHIFT 0x0
+#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B_MASK 0xffff0000
+#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B__SHIFT 0x10
+#define DENORM_CLAMP_CONTROL__DENORM_FACTOR_MASK 0x3
+#define DENORM_CLAMP_CONTROL__DENORM_FACTOR__SHIFT 0x0
+#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR_MASK 0xfff
+#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR__SHIFT 0x0
+#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR_MASK 0xfff000
+#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR__SHIFT 0xc
+#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y_MASK 0xfff
+#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y__SHIFT 0x0
+#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y_MASK 0xfff000
+#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y__SHIFT 0xc
+#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB_MASK 0xfff
+#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB__SHIFT 0x0
+#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB_MASK 0xfff000
+#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB__SHIFT 0xc
+#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff
+#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
+#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX_MASK 0x3f00000
+#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
+#define GAMMA_CORR_CONTROL__GAMMA_CORR_MODE_MASK 0x3
+#define GAMMA_CORR_CONTROL__GAMMA_CORR_MODE__SHIFT 0x0
+#define GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX_MASK 0x1ff
+#define GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX__SHIFT 0x0
+#define GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA_MASK 0x7ffff
+#define GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA__SHIFT 0x0
+#define GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK_MASK 0x7
+#define GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_MASK 0x3ffff
+#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000
+#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
+#define GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END_MASK 0xffff
+#define GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff
+#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000
+#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_MASK 0x3ffff
+#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000
+#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
+#define GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END_MASK 0xffff
+#define GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff
+#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000
+#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b
+#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_INDEX_MASK 0xff
+#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_INDEX__SHIFT 0x0
+#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define COL_MAN_TEST_DEBUG_DATA__COL_MAN_TEST_DEBUG_DATA_MASK 0xffffffff
+#define COL_MAN_TEST_DEBUG_DATA__COL_MAN_TEST_DEBUG_DATA__SHIFT 0x0
+#define COL_MAN_DEBUG_CONTROL__COL_MAN_GLOBAL_PASSTHROUGH_ENABLE_MASK 0x1
+#define COL_MAN_DEBUG_CONTROL__COL_MAN_GLOBAL_PASSTHROUGH_ENABLE__SHIFT 0x0
+#define UNP_GRPH_ENABLE__GRPH_ENABLE_MASK 0x1
+#define UNP_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
+#define UNP_GRPH_CONTROL__GRPH_DEPTH_MASK 0x3
+#define UNP_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
+#define UNP_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc
+#define UNP_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2
+#define UNP_GRPH_CONTROL__GRPH_Z_MASK 0x30
+#define UNP_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
+#define UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0xc0
+#define UNP_GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x6
+#define UNP_GRPH_CONTROL__GRPH_FORMAT_MASK 0x700
+#define UNP_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
+#define UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x1800
+#define UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0xb
+#define UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0xe000
+#define UNP_GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0xd
+#define UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000
+#define UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
+#define UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000
+#define UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
+#define UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0xc0000
+#define UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x12
+#define UNP_GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000
+#define UNP_GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14
+#define UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000
+#define UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18
+#define UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK 0x60000000
+#define UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT 0x1d
+#define UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000
+#define UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
+#define UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT_MASK 0x7
+#define UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT__SHIFT 0x0
+#define UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3
+#define UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
+#define UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30
+#define UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
+#define UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0
+#define UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
+#define UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300
+#define UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_DFQ_ENABLE_L_MASK 0x1
+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_DFQ_ENABLE_L__SHIFT 0x0
+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L_MASK 0xffffff00
+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT 0x8
+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_DFQ_ENABLE_C_MASK 0x1
+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_DFQ_ENABLE_C__SHIFT 0x0
+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C_MASK 0xffffff00
+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x8
+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK 0xff
+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0xff
+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_L_MASK 0x1
+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_L__SHIFT 0x0
+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xffffff00
+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8
+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_C_MASK 0x1
+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_C__SHIFT 0x0
+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xffffff00
+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8
+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0xff
+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0xff
+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_DFQ_ENABLE_L_MASK 0x1
+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_DFQ_ENABLE_L__SHIFT 0x0
+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L_MASK 0xffffff00
+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L__SHIFT 0x8
+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_DFQ_ENABLE_C_MASK 0x1
+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_DFQ_ENABLE_C__SHIFT 0x0
+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C_MASK 0xffffff00
+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x8
+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_MASK 0xff
+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0xff
+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_L_MASK 0x1
+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_L__SHIFT 0x0
+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xffffff00
+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8
+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_C_MASK 0x1
+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_C__SHIFT 0x0
+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xffffff00
+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8
+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0xff
+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0xff
+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define UNP_GRPH_PITCH_L__GRPH_PITCH_L_MASK 0x7fff
+#define UNP_GRPH_PITCH_L__GRPH_PITCH_L__SHIFT 0x0
+#define UNP_GRPH_PITCH_C__GRPH_PITCH_C_MASK 0x7fff
+#define UNP_GRPH_PITCH_C__GRPH_PITCH_C__SHIFT 0x0
+#define UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L_MASK 0x3fff
+#define UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L__SHIFT 0x0
+#define UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C_MASK 0x3fff
+#define UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C__SHIFT 0x0
+#define UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L_MASK 0x3fff
+#define UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L__SHIFT 0x0
+#define UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C_MASK 0x3fff
+#define UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C__SHIFT 0x0
+#define UNP_GRPH_X_START_L__GRPH_X_START_L_MASK 0x3fff
+#define UNP_GRPH_X_START_L__GRPH_X_START_L__SHIFT 0x0
+#define UNP_GRPH_X_START_C__GRPH_X_START_C_MASK 0x3fff
+#define UNP_GRPH_X_START_C__GRPH_X_START_C__SHIFT 0x0
+#define UNP_GRPH_Y_START_L__GRPH_Y_START_L_MASK 0x3fff
+#define UNP_GRPH_Y_START_L__GRPH_Y_START_L__SHIFT 0x0
+#define UNP_GRPH_Y_START_C__GRPH_Y_START_C_MASK 0x3fff
+#define UNP_GRPH_Y_START_C__GRPH_Y_START_C__SHIFT 0x0
+#define UNP_GRPH_X_END_L__GRPH_X_END_L_MASK 0x7fff
+#define UNP_GRPH_X_END_L__GRPH_X_END_L__SHIFT 0x0
+#define UNP_GRPH_X_END_C__GRPH_X_END_C_MASK 0x7fff
+#define UNP_GRPH_X_END_C__GRPH_X_END_C__SHIFT 0x0
+#define UNP_GRPH_Y_END_L__GRPH_Y_END_L_MASK 0x7fff
+#define UNP_GRPH_Y_END_L__GRPH_Y_END_L__SHIFT 0x0
+#define UNP_GRPH_Y_END_C__GRPH_Y_END_C_MASK 0x7fff
+#define UNP_GRPH_Y_END_C__GRPH_Y_END_C__SHIFT 0x0
+#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1
+#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
+#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2
+#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
+#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4
+#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
+#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8
+#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
+#define UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000
+#define UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
+#define UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000
+#define UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
+#define UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
+#define UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000
+#define UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
+#define UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L_MASK 0xffffff00
+#define UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L__SHIFT 0x8
+#define UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C_MASK 0xffffff00
+#define UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C__SHIFT 0x8
+#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_MASK 0xff
+#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__SHIFT 0x0
+#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_MASK 0xff
+#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__SHIFT 0x0
+#define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x1
+#define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
+#define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x70
+#define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
+#define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x700
+#define UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
+#define UNP_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0xf
+#define UNP_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
+#define UNP_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0
+#define UNP_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
+#define UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x100
+#define UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
+#define UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x200
+#define UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
+#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1
+#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
+#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100
+#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
+#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1
+#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
+#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100
+#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x30
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x4
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN_MASK 0x100
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN__SHIFT 0x8
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE_MASK 0x3000
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE__SHIFT 0xc
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING_MASK 0x40000
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING__SHIFT 0x12
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING_MASK 0x80000
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING__SHIFT 0x13
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
+#define UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x7
+#define UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
+#define UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x8
+#define UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
+#define UNP_CRC_CONTROL__UNP_CRC_ENABLE_MASK 0x1
+#define UNP_CRC_CONTROL__UNP_CRC_ENABLE__SHIFT 0x0
+#define UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL_MASK 0x1c
+#define UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL__SHIFT 0x2
+#define UNP_CRC_CONTROL__UNP_CRC_LINE_SEL_MASK 0x300
+#define UNP_CRC_CONTROL__UNP_CRC_LINE_SEL__SHIFT 0x8
+#define UNP_CRC_MASK__UNP_CRC_MASK_MASK 0xffffffff
+#define UNP_CRC_MASK__UNP_CRC_MASK__SHIFT 0x0
+#define UNP_CRC_CURRENT__UNP_CRC_CURRENT_MASK 0xffffffff
+#define UNP_CRC_CURRENT__UNP_CRC_CURRENT__SHIFT 0x0
+#define UNP_CRC_LAST__UNP_CRC_LAST_MASK 0xffffffff
+#define UNP_CRC_LAST__UNP_CRC_LAST__SHIFT 0x0
+#define UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK_MASK 0x1f0
+#define UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK__SHIFT 0x4
+#define UNP_HW_ROTATION__ROTATION_ANGLE_MASK 0x7
+#define UNP_HW_ROTATION__ROTATION_ANGLE__SHIFT 0x0
+#define UNP_HW_ROTATION__PIXEL_DROP_MASK 0x10
+#define UNP_HW_ROTATION__PIXEL_DROP__SHIFT 0x4
+#define UNP_HW_ROTATION__BUFFER_MODE_MASK 0x100
+#define UNP_HW_ROTATION__BUFFER_MODE__SHIFT 0x8
+#define UNP_DEBUG__UNP_DEBUG_MASK 0xffffffff
+#define UNP_DEBUG__UNP_DEBUG__SHIFT 0x0
+#define UNP_DEBUG2__UNP_DEBUG2_MASK 0xffffffff
+#define UNP_DEBUG2__UNP_DEBUG2__SHIFT 0x0
+#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX_MASK 0xff
+#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX__SHIFT 0x0
+#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA_MASK 0xffffffff
+#define UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA__SHIFT 0x0
+#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x1
+#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0
+#define GENMO_WT__VGA_RAM_EN_MASK 0x2
+#define GENMO_WT__VGA_RAM_EN__SHIFT 0x1
+#define GENMO_WT__VGA_CKSEL_MASK 0xc
+#define GENMO_WT__VGA_CKSEL__SHIFT 0x2
+#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20
+#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5
+#define GENMO_WT__VGA_HSYNC_POL_MASK 0x40
+#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6
+#define GENMO_WT__VGA_VSYNC_POL_MASK 0x80
+#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7
+#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x1
+#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0
+#define GENMO_RD__VGA_RAM_EN_MASK 0x2
+#define GENMO_RD__VGA_RAM_EN__SHIFT 0x1
+#define GENMO_RD__VGA_CKSEL_MASK 0xc
+#define GENMO_RD__VGA_CKSEL__SHIFT 0x2
+#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20
+#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5
+#define GENMO_RD__VGA_HSYNC_POL_MASK 0x40
+#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6
+#define GENMO_RD__VGA_VSYNC_POL_MASK 0x80
+#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7
+#define GENENB__BLK_IO_BASE_MASK 0xff
+#define GENENB__BLK_IO_BASE__SHIFT 0x0
+#define GENFC_WT__VSYNC_SEL_W_MASK 0x8
+#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3
+#define GENFC_RD__VSYNC_SEL_R_MASK 0x8
+#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3
+#define GENS0__SENSE_SWITCH_MASK 0x10
+#define GENS0__SENSE_SWITCH__SHIFT 0x4
+#define GENS0__CRT_INTR_MASK 0x80
+#define GENS0__CRT_INTR__SHIFT 0x7
+#define GENS1__NO_DISPLAY_MASK 0x1
+#define GENS1__NO_DISPLAY__SHIFT 0x0
+#define GENS1__VGA_VSTATUS_MASK 0x8
+#define GENS1__VGA_VSTATUS__SHIFT 0x3
+#define GENS1__PIXEL_READ_BACK_MASK 0x30
+#define GENS1__PIXEL_READ_BACK__SHIFT 0x4
+#define DAC_DATA__DAC_DATA_MASK 0x3f
+#define DAC_DATA__DAC_DATA__SHIFT 0x0
+#define DAC_MASK__DAC_MASK_MASK 0xff
+#define DAC_MASK__DAC_MASK__SHIFT 0x0
+#define DAC_R_INDEX__DAC_R_INDEX_MASK 0xff
+#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0
+#define DAC_W_INDEX__DAC_W_INDEX_MASK 0xff
+#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0
+#define SEQ8_IDX__SEQ_IDX_MASK 0x7
+#define SEQ8_IDX__SEQ_IDX__SHIFT 0x0
+#define SEQ8_DATA__SEQ_DATA_MASK 0xff
+#define SEQ8_DATA__SEQ_DATA__SHIFT 0x0
+#define SEQ00__SEQ_RST0B_MASK 0x1
+#define SEQ00__SEQ_RST0B__SHIFT 0x0
+#define SEQ00__SEQ_RST1B_MASK 0x2
+#define SEQ00__SEQ_RST1B__SHIFT 0x1
+#define SEQ01__SEQ_DOT8_MASK 0x1
+#define SEQ01__SEQ_DOT8__SHIFT 0x0
+#define SEQ01__SEQ_SHIFT2_MASK 0x4
+#define SEQ01__SEQ_SHIFT2__SHIFT 0x2
+#define SEQ01__SEQ_PCLKBY2_MASK 0x8
+#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3
+#define SEQ01__SEQ_SHIFT4_MASK 0x10
+#define SEQ01__SEQ_SHIFT4__SHIFT 0x4
+#define SEQ01__SEQ_MAXBW_MASK 0x20
+#define SEQ01__SEQ_MAXBW__SHIFT 0x5
+#define SEQ02__SEQ_MAP0_EN_MASK 0x1
+#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0
+#define SEQ02__SEQ_MAP1_EN_MASK 0x2
+#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1
+#define SEQ02__SEQ_MAP2_EN_MASK 0x4
+#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2
+#define SEQ02__SEQ_MAP3_EN_MASK 0x8
+#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3
+#define SEQ03__SEQ_FONT_B1_MASK 0x1
+#define SEQ03__SEQ_FONT_B1__SHIFT 0x0
+#define SEQ03__SEQ_FONT_B2_MASK 0x2
+#define SEQ03__SEQ_FONT_B2__SHIFT 0x1
+#define SEQ03__SEQ_FONT_A1_MASK 0x4
+#define SEQ03__SEQ_FONT_A1__SHIFT 0x2
+#define SEQ03__SEQ_FONT_A2_MASK 0x8
+#define SEQ03__SEQ_FONT_A2__SHIFT 0x3
+#define SEQ03__SEQ_FONT_B0_MASK 0x10
+#define SEQ03__SEQ_FONT_B0__SHIFT 0x4
+#define SEQ03__SEQ_FONT_A0_MASK 0x20
+#define SEQ03__SEQ_FONT_A0__SHIFT 0x5
+#define SEQ04__SEQ_256K_MASK 0x2
+#define SEQ04__SEQ_256K__SHIFT 0x1
+#define SEQ04__SEQ_ODDEVEN_MASK 0x4
+#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2
+#define SEQ04__SEQ_CHAIN_MASK 0x8
+#define SEQ04__SEQ_CHAIN__SHIFT 0x3
+#define CRTC8_IDX__VCRTC_IDX_MASK 0x3f
+#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0
+#define CRTC8_DATA__VCRTC_DATA_MASK 0xff
+#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0
+#define CRT00__H_TOTAL_MASK 0xff
+#define CRT00__H_TOTAL__SHIFT 0x0
+#define CRT01__H_DISP_END_MASK 0xff
+#define CRT01__H_DISP_END__SHIFT 0x0
+#define CRT02__H_BLANK_START_MASK 0xff
+#define CRT02__H_BLANK_START__SHIFT 0x0
+#define CRT03__H_BLANK_END_MASK 0x1f
+#define CRT03__H_BLANK_END__SHIFT 0x0
+#define CRT03__H_DE_SKEW_MASK 0x60
+#define CRT03__H_DE_SKEW__SHIFT 0x5
+#define CRT03__CR10CR11_R_DIS_B_MASK 0x80
+#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7
+#define CRT04__H_SYNC_START_MASK 0xff
+#define CRT04__H_SYNC_START__SHIFT 0x0
+#define CRT05__H_SYNC_END_MASK 0x1f
+#define CRT05__H_SYNC_END__SHIFT 0x0
+#define CRT05__H_SYNC_SKEW_MASK 0x60
+#define CRT05__H_SYNC_SKEW__SHIFT 0x5
+#define CRT05__H_BLANK_END_B5_MASK 0x80
+#define CRT05__H_BLANK_END_B5__SHIFT 0x7
+#define CRT06__V_TOTAL_MASK 0xff
+#define CRT06__V_TOTAL__SHIFT 0x0
+#define CRT07__V_TOTAL_B8_MASK 0x1
+#define CRT07__V_TOTAL_B8__SHIFT 0x0
+#define CRT07__V_DISP_END_B8_MASK 0x2
+#define CRT07__V_DISP_END_B8__SHIFT 0x1
+#define CRT07__V_SYNC_START_B8_MASK 0x4
+#define CRT07__V_SYNC_START_B8__SHIFT 0x2
+#define CRT07__V_BLANK_START_B8_MASK 0x8
+#define CRT07__V_BLANK_START_B8__SHIFT 0x3
+#define CRT07__LINE_CMP_B8_MASK 0x10
+#define CRT07__LINE_CMP_B8__SHIFT 0x4
+#define CRT07__V_TOTAL_B9_MASK 0x20
+#define CRT07__V_TOTAL_B9__SHIFT 0x5
+#define CRT07__V_DISP_END_B9_MASK 0x40
+#define CRT07__V_DISP_END_B9__SHIFT 0x6
+#define CRT07__V_SYNC_START_B9_MASK 0x80
+#define CRT07__V_SYNC_START_B9__SHIFT 0x7
+#define CRT08__ROW_SCAN_START_MASK 0x1f
+#define CRT08__ROW_SCAN_START__SHIFT 0x0
+#define CRT08__BYTE_PAN_MASK 0x60
+#define CRT08__BYTE_PAN__SHIFT 0x5
+#define CRT09__MAX_ROW_SCAN_MASK 0x1f
+#define CRT09__MAX_ROW_SCAN__SHIFT 0x0
+#define CRT09__V_BLANK_START_B9_MASK 0x20
+#define CRT09__V_BLANK_START_B9__SHIFT 0x5
+#define CRT09__LINE_CMP_B9_MASK 0x40
+#define CRT09__LINE_CMP_B9__SHIFT 0x6
+#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80
+#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7
+#define CRT0A__CURSOR_START_MASK 0x1f
+#define CRT0A__CURSOR_START__SHIFT 0x0
+#define CRT0A__CURSOR_DISABLE_MASK 0x20
+#define CRT0A__CURSOR_DISABLE__SHIFT 0x5
+#define CRT0B__CURSOR_END_MASK 0x1f
+#define CRT0B__CURSOR_END__SHIFT 0x0
+#define CRT0B__CURSOR_SKEW_MASK 0x60
+#define CRT0B__CURSOR_SKEW__SHIFT 0x5
+#define CRT0C__DISP_START_MASK 0xff
+#define CRT0C__DISP_START__SHIFT 0x0
+#define CRT0D__DISP_START_MASK 0xff
+#define CRT0D__DISP_START__SHIFT 0x0
+#define CRT0E__CURSOR_LOC_HI_MASK 0xff
+#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0
+#define CRT0F__CURSOR_LOC_LO_MASK 0xff
+#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0
+#define CRT10__V_SYNC_START_MASK 0xff
+#define CRT10__V_SYNC_START__SHIFT 0x0
+#define CRT11__V_SYNC_END_MASK 0xf
+#define CRT11__V_SYNC_END__SHIFT 0x0
+#define CRT11__V_INTR_CLR_MASK 0x10
+#define CRT11__V_INTR_CLR__SHIFT 0x4
+#define CRT11__V_INTR_EN_MASK 0x20
+#define CRT11__V_INTR_EN__SHIFT 0x5
+#define CRT11__SEL5_REFRESH_CYC_MASK 0x40
+#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6
+#define CRT11__C0T7_WR_ONLY_MASK 0x80
+#define CRT11__C0T7_WR_ONLY__SHIFT 0x7
+#define CRT12__V_DISP_END_MASK 0xff
+#define CRT12__V_DISP_END__SHIFT 0x0
+#define CRT13__DISP_PITCH_MASK 0xff
+#define CRT13__DISP_PITCH__SHIFT 0x0
+#define CRT14__UNDRLN_LOC_MASK 0x1f
+#define CRT14__UNDRLN_LOC__SHIFT 0x0
+#define CRT14__ADDR_CNT_BY4_MASK 0x20
+#define CRT14__ADDR_CNT_BY4__SHIFT 0x5
+#define CRT14__DOUBLE_WORD_MASK 0x40
+#define CRT14__DOUBLE_WORD__SHIFT 0x6
+#define CRT15__V_BLANK_START_MASK 0xff
+#define CRT15__V_BLANK_START__SHIFT 0x0
+#define CRT16__V_BLANK_END_MASK 0xff
+#define CRT16__V_BLANK_END__SHIFT 0x0
+#define CRT17__RA0_AS_A13B_MASK 0x1
+#define CRT17__RA0_AS_A13B__SHIFT 0x0
+#define CRT17__RA1_AS_A14B_MASK 0x2
+#define CRT17__RA1_AS_A14B__SHIFT 0x1
+#define CRT17__VCOUNT_BY2_MASK 0x4
+#define CRT17__VCOUNT_BY2__SHIFT 0x2
+#define CRT17__ADDR_CNT_BY2_MASK 0x8
+#define CRT17__ADDR_CNT_BY2__SHIFT 0x3
+#define CRT17__WRAP_A15TOA0_MASK 0x20
+#define CRT17__WRAP_A15TOA0__SHIFT 0x5
+#define CRT17__BYTE_MODE_MASK 0x40
+#define CRT17__BYTE_MODE__SHIFT 0x6
+#define CRT17__CRTC_SYNC_EN_MASK 0x80
+#define CRT17__CRTC_SYNC_EN__SHIFT 0x7
+#define CRT18__LINE_CMP_MASK 0xff
+#define CRT18__LINE_CMP__SHIFT 0x0
+#define CRT1E__GRPH_DEC_RD1_MASK 0x2
+#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1
+#define CRT1F__GRPH_DEC_RD0_MASK 0xff
+#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0
+#define CRT22__GRPH_LATCH_DATA_MASK 0xff
+#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0
+#define GRPH8_IDX__GRPH_IDX_MASK 0xf
+#define GRPH8_IDX__GRPH_IDX__SHIFT 0x0
+#define GRPH8_DATA__GRPH_DATA_MASK 0xff
+#define GRPH8_DATA__GRPH_DATA__SHIFT 0x0
+#define GRA00__GRPH_SET_RESET0_MASK 0x1
+#define GRA00__GRPH_SET_RESET0__SHIFT 0x0
+#define GRA00__GRPH_SET_RESET1_MASK 0x2
+#define GRA00__GRPH_SET_RESET1__SHIFT 0x1
+#define GRA00__GRPH_SET_RESET2_MASK 0x4
+#define GRA00__GRPH_SET_RESET2__SHIFT 0x2
+#define GRA00__GRPH_SET_RESET3_MASK 0x8
+#define GRA00__GRPH_SET_RESET3__SHIFT 0x3
+#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x1
+#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0
+#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x2
+#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1
+#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x4
+#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2
+#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x8
+#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3
+#define GRA02__GRPH_CCOMP_MASK 0xf
+#define GRA02__GRPH_CCOMP__SHIFT 0x0
+#define GRA03__GRPH_ROTATE_MASK 0x7
+#define GRA03__GRPH_ROTATE__SHIFT 0x0
+#define GRA03__GRPH_FN_SEL_MASK 0x18
+#define GRA03__GRPH_FN_SEL__SHIFT 0x3
+#define GRA04__GRPH_RMAP_MASK 0x3
+#define GRA04__GRPH_RMAP__SHIFT 0x0
+#define GRA05__GRPH_WRITE_MODE_MASK 0x3
+#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0
+#define GRA05__GRPH_READ1_MASK 0x8
+#define GRA05__GRPH_READ1__SHIFT 0x3
+#define GRA05__CGA_ODDEVEN_MASK 0x10
+#define GRA05__CGA_ODDEVEN__SHIFT 0x4
+#define GRA05__GRPH_OES_MASK 0x20
+#define GRA05__GRPH_OES__SHIFT 0x5
+#define GRA05__GRPH_PACK_MASK 0x40
+#define GRA05__GRPH_PACK__SHIFT 0x6
+#define GRA06__GRPH_GRAPHICS_MASK 0x1
+#define GRA06__GRPH_GRAPHICS__SHIFT 0x0
+#define GRA06__GRPH_ODDEVEN_MASK 0x2
+#define GRA06__GRPH_ODDEVEN__SHIFT 0x1
+#define GRA06__GRPH_ADRSEL_MASK 0xc
+#define GRA06__GRPH_ADRSEL__SHIFT 0x2
+#define GRA07__GRPH_XCARE0_MASK 0x1
+#define GRA07__GRPH_XCARE0__SHIFT 0x0
+#define GRA07__GRPH_XCARE1_MASK 0x2
+#define GRA07__GRPH_XCARE1__SHIFT 0x1
+#define GRA07__GRPH_XCARE2_MASK 0x4
+#define GRA07__GRPH_XCARE2__SHIFT 0x2
+#define GRA07__GRPH_XCARE3_MASK 0x8
+#define GRA07__GRPH_XCARE3__SHIFT 0x3
+#define GRA08__GRPH_BMSK_MASK 0xff
+#define GRA08__GRPH_BMSK__SHIFT 0x0
+#define ATTRX__ATTR_IDX_MASK 0x1f
+#define ATTRX__ATTR_IDX__SHIFT 0x0
+#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20
+#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5
+#define ATTRDW__ATTR_DATA_MASK 0xff
+#define ATTRDW__ATTR_DATA__SHIFT 0x0
+#define ATTRDR__ATTR_DATA_MASK 0xff
+#define ATTRDR__ATTR_DATA__SHIFT 0x0
+#define ATTR00__ATTR_PAL_MASK 0x3f
+#define ATTR00__ATTR_PAL__SHIFT 0x0
+#define ATTR01__ATTR_PAL_MASK 0x3f
+#define ATTR01__ATTR_PAL__SHIFT 0x0
+#define ATTR02__ATTR_PAL_MASK 0x3f
+#define ATTR02__ATTR_PAL__SHIFT 0x0
+#define ATTR03__ATTR_PAL_MASK 0x3f
+#define ATTR03__ATTR_PAL__SHIFT 0x0
+#define ATTR04__ATTR_PAL_MASK 0x3f
+#define ATTR04__ATTR_PAL__SHIFT 0x0
+#define ATTR05__ATTR_PAL_MASK 0x3f
+#define ATTR05__ATTR_PAL__SHIFT 0x0
+#define ATTR06__ATTR_PAL_MASK 0x3f
+#define ATTR06__ATTR_PAL__SHIFT 0x0
+#define ATTR07__ATTR_PAL_MASK 0x3f
+#define ATTR07__ATTR_PAL__SHIFT 0x0
+#define ATTR08__ATTR_PAL_MASK 0x3f
+#define ATTR08__ATTR_PAL__SHIFT 0x0
+#define ATTR09__ATTR_PAL_MASK 0x3f
+#define ATTR09__ATTR_PAL__SHIFT 0x0
+#define ATTR0A__ATTR_PAL_MASK 0x3f
+#define ATTR0A__ATTR_PAL__SHIFT 0x0
+#define ATTR0B__ATTR_PAL_MASK 0x3f
+#define ATTR0B__ATTR_PAL__SHIFT 0x0
+#define ATTR0C__ATTR_PAL_MASK 0x3f
+#define ATTR0C__ATTR_PAL__SHIFT 0x0
+#define ATTR0D__ATTR_PAL_MASK 0x3f
+#define ATTR0D__ATTR_PAL__SHIFT 0x0
+#define ATTR0E__ATTR_PAL_MASK 0x3f
+#define ATTR0E__ATTR_PAL__SHIFT 0x0
+#define ATTR0F__ATTR_PAL_MASK 0x3f
+#define ATTR0F__ATTR_PAL__SHIFT 0x0
+#define ATTR10__ATTR_GRPH_MODE_MASK 0x1
+#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0
+#define ATTR10__ATTR_MONO_EN_MASK 0x2
+#define ATTR10__ATTR_MONO_EN__SHIFT 0x1
+#define ATTR10__ATTR_LGRPH_EN_MASK 0x4
+#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2
+#define ATTR10__ATTR_BLINK_EN_MASK 0x8
+#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3
+#define ATTR10__ATTR_PANTOPONLY_MASK 0x20
+#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5
+#define ATTR10__ATTR_PCLKBY2_MASK 0x40
+#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6
+#define ATTR10__ATTR_CSEL_EN_MASK 0x80
+#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7
+#define ATTR11__ATTR_OVSC_MASK 0xff
+#define ATTR11__ATTR_OVSC__SHIFT 0x0
+#define ATTR12__ATTR_MAP_EN_MASK 0xf
+#define ATTR12__ATTR_MAP_EN__SHIFT 0x0
+#define ATTR12__ATTR_VSMUX_MASK 0x30
+#define ATTR12__ATTR_VSMUX__SHIFT 0x4
+#define ATTR13__ATTR_PPAN_MASK 0xf
+#define ATTR13__ATTR_PPAN__SHIFT 0x0
+#define ATTR14__ATTR_CSEL1_MASK 0x3
+#define ATTR14__ATTR_CSEL1__SHIFT 0x0
+#define ATTR14__ATTR_CSEL2_MASK 0xc
+#define ATTR14__ATTR_CSEL2__SHIFT 0x2
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x1f
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x60
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x80
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x100
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x30000
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x1000000
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18
+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x2000000
+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x7
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x700
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x1
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x2
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x4
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x8
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x10
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x20
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x100
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x200
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x400
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x800
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x1000
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x2000
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x10000
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x20000
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0xfc0000
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x1
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x30
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x100
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x10000
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x3
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x300
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xffffffff
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0xff
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x1ffffff
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x1ffffff
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x1
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x10
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x100
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x10000
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x1000000
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x1
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x100
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x10000
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x100000
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3f000000
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x1
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x100
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x200
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x10000
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x3000000
+#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x1
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x100
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x200
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x10000
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x3000000
+#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x1
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x100
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x200
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x10000
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x3000000
+#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x1
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x100
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x200
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x10000
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x3000000
+#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x1
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x100
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x200
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x10000
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x3000000
+#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x1
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x100
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x200
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x10000
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x3000000
+#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18
+#define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK 0xffffffff
+#define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT 0x0
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x1
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x2
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x4
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x8
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x1
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x100
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x10000
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x1000000
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x1
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x100
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x10000
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x1000000
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x1
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x2
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x4
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x8
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x3
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x18
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0xe0
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x300
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8
+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK 0xf000
+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT 0xc
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x30000
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x3000000
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x4000000
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a
+#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK 0x8000000
+#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT 0x1b
+#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK 0x10000000
+#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT 0x1c
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x1
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x100
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x10000
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x1000000
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18
+#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK 0xff
+#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT 0x0
+#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK 0xffffffff
+#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT 0x0
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x3ff
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x3ff0000
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x3ff
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x3ff0000
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
+#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK 0xff
+#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT 0x0
+#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK 0xffffffff
+#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT 0x0
+#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff
+#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x3
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x0
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x3f00
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x8
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x3f0000
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x10
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0xf000000
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x18
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x1c
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x1
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x0
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x2
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x1
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x4
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x2
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x3ff0
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x4
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x700000
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x14
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x1c
+#define PLL_REF_DIV__PLL_REF_DIV_MASK 0x3ff
+#define PLL_REF_DIV__PLL_REF_DIV__SHIFT 0x0
+#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV_MASK 0xf000
+#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV__SHIFT 0xc
+#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_MASK 0xf
+#define PLL_FB_DIV__PLL_FB_DIV_FRACTION__SHIFT 0x0
+#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL_MASK 0x30
+#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
+#define PLL_FB_DIV__PLL_FB_DIV_MASK 0xfff0000
+#define PLL_FB_DIV__PLL_FB_DIV__SHIFT 0x10
+#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK 0x7f
+#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK__SHIFT 0x0
+#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK_MASK 0x80
+#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x7
+#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK_MASK 0x7f00
+#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK__SHIFT 0x8
+#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK_MASK 0x8000
+#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK__SHIFT 0xf
+#define PLL_POST_DIV__PLL_POST_DIV_IDCLK_MASK 0x7f0000
+#define PLL_POST_DIV__PLL_POST_DIV_IDCLK__SHIFT 0x10
+#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC_MASK 0xffff
+#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC__SHIFT 0x0
+#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV_MASK 0xff
+#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x0
+#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP_MASK 0xf00
+#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT 0x8
+#define PLL_SS_CNTL__PLL_SS_EN_MASK 0x1000
+#define PLL_SS_CNTL__PLL_SS_EN__SHIFT 0xc
+#define PLL_SS_CNTL__PLL_SS_MODE_MASK 0x2000
+#define PLL_SS_CNTL__PLL_SS_MODE__SHIFT 0xd
+#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC_MASK 0xffff0000
+#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC__SHIFT 0x10
+#define PLL_DS_CNTL__PLL_DS_FRAC_MASK 0xffff
+#define PLL_DS_CNTL__PLL_DS_FRAC__SHIFT 0x0
+#define PLL_DS_CNTL__PLL_DS_ORDER_MASK 0x30000
+#define PLL_DS_CNTL__PLL_DS_ORDER__SHIFT 0x10
+#define PLL_DS_CNTL__PLL_DS_MODE_MASK 0x40000
+#define PLL_DS_CNTL__PLL_DS_MODE__SHIFT 0x12
+#define PLL_DS_CNTL__PLL_DS_PRBS_EN_MASK 0x80000
+#define PLL_DS_CNTL__PLL_DS_PRBS_EN__SHIFT 0x13
+#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN_MASK 0x1
+#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN__SHIFT 0x0
+#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN_MASK 0x2
+#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN__SHIFT 0x1
+#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN_MASK 0x4
+#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN__SHIFT 0x2
+#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN_MASK 0x8
+#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN__SHIFT 0x3
+#define PLL_IDCLK_CNTL__PLL_IDCLK_EN_MASK 0x10
+#define PLL_IDCLK_CNTL__PLL_IDCLK_EN__SHIFT 0x4
+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET_MASK 0x100
+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET__SHIFT 0x8
+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT_MASK 0x1000
+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT__SHIFT 0xc
+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_MASK 0xf0000
+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV__SHIFT 0x10
+#define PLL_IDCLK_CNTL__PLL_CUR_LTDP_MASK 0x300000
+#define PLL_IDCLK_CNTL__PLL_CUR_LTDP__SHIFT 0x14
+#define PLL_IDCLK_CNTL__PLL_CUR_PREDRV_MASK 0xc00000
+#define PLL_IDCLK_CNTL__PLL_CUR_PREDRV__SHIFT 0x16
+#define PLL_IDCLK_CNTL__PLL_CUR_TMDP_MASK 0x3000000
+#define PLL_IDCLK_CNTL__PLL_CUR_TMDP__SHIFT 0x18
+#define PLL_IDCLK_CNTL__PLL_CML_A_DRVSTR_MASK 0xc000000
+#define PLL_IDCLK_CNTL__PLL_CML_A_DRVSTR__SHIFT 0x1a
+#define PLL_IDCLK_CNTL__PLL_CML_B_DRVSTR_MASK 0x30000000
+#define PLL_IDCLK_CNTL__PLL_CML_B_DRVSTR__SHIFT 0x1c
+#define PLL_CNTL__PLL_RESET_MASK 0x1
+#define PLL_CNTL__PLL_RESET__SHIFT 0x0
+#define PLL_CNTL__PLL_POWER_DOWN_MASK 0x2
+#define PLL_CNTL__PLL_POWER_DOWN__SHIFT 0x1
+#define PLL_CNTL__PLL_BYPASS_CAL_MASK 0x4
+#define PLL_CNTL__PLL_BYPASS_CAL__SHIFT 0x2
+#define PLL_CNTL__PLL_POST_DIV_SRC_MASK 0x8
+#define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x3
+#define PLL_CNTL__PLL_VCOREF_MASK 0x30
+#define PLL_CNTL__PLL_VCOREF__SHIFT 0x4
+#define PLL_CNTL__PLL_PCIE_REFCLK_SEL_MASK 0x40
+#define PLL_CNTL__PLL_PCIE_REFCLK_SEL__SHIFT 0x6
+#define PLL_CNTL__PLL_ANTIGLITCH_RESETB_MASK 0x80
+#define PLL_CNTL__PLL_ANTIGLITCH_RESETB__SHIFT 0x7
+#define PLL_CNTL__PLL_CALREF_MASK 0x300
+#define PLL_CNTL__PLL_CALREF__SHIFT 0x8
+#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV_MASK 0x400
+#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV__SHIFT 0xa
+#define PLL_CNTL__PLL_REFCLK_SEL_MASK 0x1800
+#define PLL_CNTL__PLL_REFCLK_SEL__SHIFT 0xb
+#define PLL_CNTL__PLL_ANTI_GLITCH_RESET_MASK 0x2000
+#define PLL_CNTL__PLL_ANTI_GLITCH_RESET__SHIFT 0xd
+#define PLL_CNTL__PLL_XOCLK_DRV_R_EN_MASK 0x4000
+#define PLL_CNTL__PLL_XOCLK_DRV_R_EN__SHIFT 0xe
+#define PLL_CNTL__PLL_REF_DIV_SRC_MASK 0x70000
+#define PLL_CNTL__PLL_REF_DIV_SRC__SHIFT 0x10
+#define PLL_CNTL__PLL_LOCK_FREQ_SEL_MASK 0x80000
+#define PLL_CNTL__PLL_LOCK_FREQ_SEL__SHIFT 0x13
+#define PLL_CNTL__PLL_CALIB_DONE_MASK 0x100000
+#define PLL_CNTL__PLL_CALIB_DONE__SHIFT 0x14
+#define PLL_CNTL__PLL_LOCKED_MASK 0x200000
+#define PLL_CNTL__PLL_LOCKED__SHIFT 0x15
+#define PLL_CNTL__PLL_REFCLK_RECV_EN_MASK 0x400000
+#define PLL_CNTL__PLL_REFCLK_RECV_EN__SHIFT 0x16
+#define PLL_CNTL__PLL_REFCLK_RECV_SEL_MASK 0x800000
+#define PLL_CNTL__PLL_REFCLK_RECV_SEL__SHIFT 0x17
+#define PLL_CNTL__PLL_TIMING_MODE_STATUS_MASK 0x3000000
+#define PLL_CNTL__PLL_TIMING_MODE_STATUS__SHIFT 0x18
+#define PLL_CNTL__PLL_DIG_SPARE_MASK 0xfc000000
+#define PLL_CNTL__PLL_DIG_SPARE__SHIFT 0x1a
+#define PLL_ANALOG__PLL_CAL_MODE_MASK 0x1f
+#define PLL_ANALOG__PLL_CAL_MODE__SHIFT 0x0
+#define PLL_ANALOG__PLL_PFD_PULSE_SEL_MASK 0x60
+#define PLL_ANALOG__PLL_PFD_PULSE_SEL__SHIFT 0x5
+#define PLL_ANALOG__PLL_CP_MASK 0xf00
+#define PLL_ANALOG__PLL_CP__SHIFT 0x8
+#define PLL_ANALOG__PLL_LF_MODE_MASK 0x1ff000
+#define PLL_ANALOG__PLL_LF_MODE__SHIFT 0xc
+#define PLL_ANALOG__PLL_VREG_FB_TRIM_MASK 0xe00000
+#define PLL_ANALOG__PLL_VREG_FB_TRIM__SHIFT 0x15
+#define PLL_ANALOG__PLL_IBIAS_MASK 0xff000000
+#define PLL_ANALOG__PLL_IBIAS__SHIFT 0x18
+#define PLL_VREG_CNTL__PLL_VREG_CNTL_MASK 0xfffff
+#define PLL_VREG_CNTL__PLL_VREG_CNTL__SHIFT 0x0
+#define PLL_VREG_CNTL__PLL_BG_VREG_BIAS_MASK 0x300000
+#define PLL_VREG_CNTL__PLL_BG_VREG_BIAS__SHIFT 0x14
+#define PLL_VREG_CNTL__PLL_VREF_SEL_MASK 0x4000000
+#define PLL_VREG_CNTL__PLL_VREF_SEL__SHIFT 0x1a
+#define PLL_VREG_CNTL__PLL_VREG_BIAS_MASK 0xf0000000
+#define PLL_VREG_CNTL__PLL_VREG_BIAS__SHIFT 0x1c
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE_MASK 0x1
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE__SHIFT 0x0
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT_MASK 0x2
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT__SHIFT 0x1
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS_MASK 0x4
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS__SHIFT 0x2
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT_MASK 0x70
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT__SHIFT 0x4
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST_MASK 0x80
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST__SHIFT 0x7
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK_MASK 0x100
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK__SHIFT 0x8
+#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE_MASK 0x1
+#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE__SHIFT 0x0
+#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL_MASK 0xf0
+#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL__SHIFT 0x4
+#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL_MASK 0x1f00
+#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL__SHIFT 0x8
+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL_MASK 0xff0000
+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL__SHIFT 0x10
+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK_MASK 0x7000000
+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK__SHIFT 0x18
+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN_MASK 0x8000000
+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN__SHIFT 0x1b
+#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK_MASK 0x1
+#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK__SHIFT 0x0
+#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING_MASK 0x1
+#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING__SHIFT 0x0
+#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT_MASK 0x100
+#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT__SHIFT 0x8
+#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE_MASK 0x10000
+#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE__SHIFT 0x10
+#define PLL_XOR_LOCK__PLL_XOR_LOCK_MASK 0x1
+#define PLL_XOR_LOCK__PLL_XOR_LOCK__SHIFT 0x0
+#define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK_MASK 0x2
+#define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK__SHIFT 0x1
+#define PLL_XOR_LOCK__PLL_SPARE_MASK 0x3f00
+#define PLL_XOR_LOCK__PLL_SPARE__SHIFT 0x8
+#define PLL_XOR_LOCK__PLL_LOCK_COUNT_SEL_MASK 0xf0000
+#define PLL_XOR_LOCK__PLL_LOCK_COUNT_SEL__SHIFT 0x10
+#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FREF_MASK 0x700000
+#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FREF__SHIFT 0x14
+#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FFB_MASK 0x3800000
+#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FFB__SHIFT 0x17
+#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_OPAMP_BIAS_MASK 0xc000000
+#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_OPAMP_BIAS__SHIFT 0x1a
+#define PLL_XOR_LOCK__PLL_FAST_LOCK_MODE_EN_MASK 0x10000000
+#define PLL_XOR_LOCK__PLL_FAST_LOCK_MODE_EN__SHIFT 0x1c
+#define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN_MASK 0x1
+#define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN__SHIFT 0x0
+#define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL_MASK 0x1e
+#define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL__SHIFT 0x1
+#define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL_MASK 0x1e0
+#define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL__SHIFT 0x5
+#define PLL_ANALOG_CNTL__PLL_REGREF_TRIM_MASK 0x3e00
+#define PLL_ANALOG_CNTL__PLL_REGREF_TRIM__SHIFT 0x9
+#define PLL_ANALOG_CNTL__PLL_CALIB_FBDIV_MASK 0x1c000
+#define PLL_ANALOG_CNTL__PLL_CALIB_FBDIV__SHIFT 0xe
+#define PLL_ANALOG_CNTL__PLL_CALIB_FASTCAL_MASK 0x20000
+#define PLL_ANALOG_CNTL__PLL_CALIB_FASTCAL__SHIFT 0x11
+#define PLL_ANALOG_CNTL__PLL_TEST_SSAMP_EN_MASK 0x40000
+#define PLL_ANALOG_CNTL__PLL_TEST_SSAMP_EN__SHIFT 0x12
+#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV_MASK 0x3ff
+#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV__SHIFT 0x0
+#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV_MASK 0x3ff
+#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV__SHIFT 0x0
+#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV_MASK 0x3ff
+#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV__SHIFT 0x0
+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_MASK 0xf
+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION__SHIFT 0x0
+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30
+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_MASK 0x7ff0000
+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV__SHIFT 0x10
+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_MASK 0xf
+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION__SHIFT 0x0
+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30
+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_MASK 0x7ff0000
+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV__SHIFT 0x10
+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_MASK 0xf
+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION__SHIFT 0x0
+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30
+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_MASK 0x7ff0000
+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV__SHIFT 0x10
+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x7f
+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK__SHIFT 0x0
+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK_MASK 0x7f00
+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK__SHIFT 0x8
+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK_MASK 0x7f0000
+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK__SHIFT 0x10
+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK_MASK 0x7f
+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK__SHIFT 0x0
+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK_MASK 0x7f00
+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK__SHIFT 0x8
+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK_MASK 0x7f0000
+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK__SHIFT 0x10
+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK_MASK 0x7f
+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK__SHIFT 0x0
+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK_MASK 0x7f00
+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK__SHIFT 0x8
+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK_MASK 0x7f0000
+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK__SHIFT 0x10
+#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK 0x1f
+#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT 0x0
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL_MASK 0x60
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL__SHIFT 0x5
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK 0xf00
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP__SHIFT 0x8
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE_MASK 0x1ff000
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE__SHIFT 0xc
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS_MASK 0xff000000
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS__SHIFT 0x18
+#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE_MASK 0x1f
+#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE__SHIFT 0x0
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL_MASK 0x60
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL__SHIFT 0x5
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP_MASK 0xf00
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP__SHIFT 0x8
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE_MASK 0x1ff000
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE__SHIFT 0xc
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS_MASK 0xff000000
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS__SHIFT 0x18
+#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE_MASK 0x1f
+#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE__SHIFT 0x0
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL_MASK 0x60
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL__SHIFT 0x5
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP_MASK 0xf00
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP__SHIFT 0x8
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE_MASK 0x1ff000
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE__SHIFT 0xc
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS_MASK 0xff000000
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS__SHIFT 0x18
+#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK 0x1
+#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT 0x0
+#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ_MASK 0xf0
+#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ__SHIFT 0x4
+#define PPLL_DIV_UPDATE_DEBUG__PLL_REF_DIV_CHANGED_MASK 0x1
+#define PPLL_DIV_UPDATE_DEBUG__PLL_REF_DIV_CHANGED__SHIFT 0x0
+#define PPLL_DIV_UPDATE_DEBUG__PLL_FB_DIV_CHANGED_MASK 0x2
+#define PPLL_DIV_UPDATE_DEBUG__PLL_FB_DIV_CHANGED__SHIFT 0x1
+#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_PENDING_MASK 0x4
+#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_PENDING__SHIFT 0x2
+#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_CURRENT_STATE_MASK 0x18
+#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_CURRENT_STATE__SHIFT 0x3
+#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ENABLE_MASK 0x20
+#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ENABLE__SHIFT 0x5
+#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_REQ_MASK 0x40
+#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_REQ__SHIFT 0x6
+#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ACK_MASK 0x80
+#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ACK__SHIFT 0x7
+#define PPLL_STATUS_DEBUG__PLL_DEBUG_BUS_MASK 0xffff
+#define PPLL_STATUS_DEBUG__PLL_DEBUG_BUS__SHIFT 0x0
+#define PPLL_STATUS_DEBUG__PLL_UNLOCK_MASK 0x10000
+#define PPLL_STATUS_DEBUG__PLL_UNLOCK__SHIFT 0x10
+#define PPLL_STATUS_DEBUG__PLL_CAL_RESULT_MASK 0x1e0000
+#define PPLL_STATUS_DEBUG__PLL_CAL_RESULT__SHIFT 0x11
+#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_ISO_ENB_MASK 0x1000000
+#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_ISO_ENB__SHIFT 0x18
+#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_S_MASK 0x2000000
+#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_S__SHIFT 0x19
+#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_V_MASK 0x4000000
+#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_V__SHIFT 0x1a
+#define PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL_MASK 0x1f
+#define PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL__SHIFT 0x0
+#define PPLL_SPARE0__PLL_SPARE0_MASK 0xffffffff
+#define PPLL_SPARE0__PLL_SPARE0__SHIFT 0x0
+#define PPLL_SPARE1__PLL_SPARE1_MASK 0xffffffff
+#define PPLL_SPARE1__PLL_SPARE1__SHIFT 0x0
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0_MASK 0x7
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0__SHIFT 0x0
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1_MASK 0x70
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1__SHIFT 0x4
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2_MASK 0x700
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2__SHIFT 0x8
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3_MASK 0x7000
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3__SHIFT 0xc
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4_MASK 0x70000
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4__SHIFT 0x10
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0_MASK 0x300000
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0__SHIFT 0x14
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1_MASK 0xc00000
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1__SHIFT 0x16
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2_MASK 0x3000000
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2__SHIFT 0x18
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3_MASK 0xc000000
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3__SHIFT 0x1a
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4_MASK 0x30000000
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4__SHIFT 0x1c
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC_MASK 0x3
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC__SHIFT 0x0
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC_MASK 0x30
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC__SHIFT 0x4
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC_MASK 0x300
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC__SHIFT 0x8
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC_MASK 0x3000
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC__SHIFT 0xc
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC_MASK 0x30000
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC__SHIFT 0x10
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL_MASK 0x100000
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL__SHIFT 0x14
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL_MASK 0x600000
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL__SHIFT 0x15
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL_MASK 0x1800000
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL__SHIFT 0x17
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL_MASK 0x6000000
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL__SHIFT 0x19
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL_MASK 0x18000000
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL__SHIFT 0x1b
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL_MASK 0x60000000
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL__SHIFT 0x1d
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK_MASK 0x3
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK__SHIFT 0x0
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT_MASK 0xc
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT__SHIFT 0x2
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK_MASK 0xf0
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK__SHIFT 0x4
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT_MASK 0xf00
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT__SHIFT 0x8
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK_MASK 0xf000
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK__SHIFT 0xc
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT_MASK 0xf0000
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT__SHIFT 0x10
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0_MASK 0x100000
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0__SHIFT 0x14
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1_MASK 0x200000
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1__SHIFT 0x15
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2_MASK 0x400000
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2__SHIFT 0x16
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3_MASK 0x800000
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3__SHIFT 0x17
+#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ_MASK 0x1f000000
+#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ__SHIFT 0x18
+#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN_MASK 0x80000000
+#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN__SHIFT 0x1f
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK_MASK 0x1f
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK__SHIFT 0x0
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT_MASK 0x3e0
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT__SHIFT 0x5
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK_MASK 0x1f000
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT 0xc
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK 0x3e0000
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT 0x11
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK_MASK 0x7000000
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK__SHIFT 0x18
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT_MASK 0x70000000
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT__SHIFT 0x1c
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN_MASK 0x1
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN__SHIFT 0x0
+#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC_MASK 0x2
+#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC__SHIFT 0x1
+#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL_MASK 0xc
+#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL__SHIFT 0x2
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00_MASK 0xf00
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00__SHIFT 0x8
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25_MASK 0xf000
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25__SHIFT 0xc
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45_MASK 0xf0000
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45__SHIFT 0x10
+#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION_MASK 0xfffc
+#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION__SHIFT 0x2
+#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_MASK 0xfff0000
+#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV__SHIFT 0x10
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE_MASK 0x1
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE__SHIFT 0x0
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET_MASK 0x2
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET__SHIFT 0x1
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN_MASK 0x4
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN__SHIFT 0x2
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN_MASK 0x8
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN__SHIFT 0x3
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN_MASK 0xf0
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN__SHIFT 0x4
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL_MASK 0x7f00
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL__SHIFT 0x8
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL_MASK 0xff0000
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL__SHIFT 0x10
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC_MASK 0x1000000
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC__SHIFT 0x18
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN_MASK 0x2000000
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN__SHIFT 0x19
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN_MASK 0x4000000
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN__SHIFT 0x1a
+#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE_MASK 0x30000000
+#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE__SHIFT 0x1c
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE_MASK 0x3
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE__SHIFT 0x0
+#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL_MASK 0xc
+#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x2
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL_MASK 0x10
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL__SHIFT 0x4
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL_MASK 0x20
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL__SHIFT 0x5
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x40
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL__SHIFT 0x6
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC_MASK 0x700
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC__SHIFT 0x8
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN_MASK 0x800
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN__SHIFT 0xb
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN_MASK 0x1000
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN__SHIFT 0xc
+#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV_MASK 0x2000
+#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV__SHIFT 0xd
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL_MASK 0x10000
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL__SHIFT 0x10
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS_MASK 0x80000
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS__SHIFT 0x13
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL_MASK 0x100000
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL__SHIFT 0x14
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV_MASK 0x1f000000
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV__SHIFT 0x18
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL_MASK 0xe0000000
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL__SHIFT 0x1d
+#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE_MASK 0x3ffffff
+#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE__SHIFT 0x0
+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM_MASK 0xfff
+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM__SHIFT 0x0
+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN_MASK 0x1000
+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN__SHIFT 0xc
+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN_MASK 0x2000
+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN__SHIFT 0xd
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL_MASK 0x1
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL__SHIFT 0x0
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL_MASK 0x30
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL__SHIFT 0x4
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR_MASK 0x40
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR__SHIFT 0x6
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT_MASK 0x100
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT__SHIFT 0x8
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE_MASK 0x10000
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE__SHIFT 0x10
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL_MASK 0x1f
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x0
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_MASK 0x1e0
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL__SHIFT 0x5
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN_MASK 0x200
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN__SHIFT 0x9
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR_MASK 0x400
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR__SHIFT 0xa
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET_MASK 0x8000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET__SHIFT 0xf
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL_MASK 0x10000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL__SHIFT 0x10
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN_MASK 0x20000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN__SHIFT 0x11
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_MASK 0x1f00000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR__SHIFT 0x14
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC_MASK 0xe000000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC__SHIFT 0x19
+#define UNIPHY_REG_TEST_OUTPUT__OA_PLL_TEST_UNLOCK_RAW_MASK 0x10000000
+#define UNIPHY_REG_TEST_OUTPUT__OA_PLL_TEST_UNLOCK_RAW__SHIFT 0x1c
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET_MASK 0x20000000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET__SHIFT 0x1d
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY_MASK 0x40000000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY__SHIFT 0x1e
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK_MASK 0x80000000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK__SHIFT 0x1f
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN_MASK 0x1
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN__SHIFT 0x0
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET_MASK 0x2
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET__SHIFT 0x1
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS_MASK 0xf00
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS__SHIFT 0x8
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR_MASK 0x1f0000
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR__SHIFT 0x10
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB_MASK 0x1000000
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB__SHIFT 0x18
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN_MASK 0x2000000
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN__SHIFT 0x19
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT_MASK 0x4000000
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT__SHIFT 0x1a
+#define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX_MASK 0xffff
+#define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX__SHIFT 0x0
+#define UNIPHY_TMDP_REG0__ITXA_IMPCAL_EN_MASK 0x1
+#define UNIPHY_TMDP_REG0__ITXA_IMPCAL_EN__SHIFT 0x0
+#define UNIPHY_TMDP_REG0__ICALRA_MODE_MASK 0x2
+#define UNIPHY_TMDP_REG0__ICALRA_MODE__SHIFT 0x1
+#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_PG_MASK 0x7fc
+#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_PG__SHIFT 0x2
+#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_NG_MASK 0xff800
+#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_NG__SHIFT 0xb
+#define UNIPHY_TMDP_REG0__ITXA_TPC_SEL_MASK 0x100000
+#define UNIPHY_TMDP_REG0__ITXA_TPC_SEL__SHIFT 0x14
+#define UNIPHY_TMDP_REG0__ITXA_PCALEN_MASK 0x200000
+#define UNIPHY_TMDP_REG0__ITXA_PCALEN__SHIFT 0x15
+#define UNIPHY_TMDP_REG0__ITXA_DPPC_PWN_MASK 0x400000
+#define UNIPHY_TMDP_REG0__ITXA_DPPC_PWN__SHIFT 0x16
+#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_EN_MASK 0x800000
+#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_EN__SHIFT 0x17
+#define UNIPHY_TMDP_REG0__ITXA_TPC_CNTL_MASK 0x3000000
+#define UNIPHY_TMDP_REG0__ITXA_TPC_CNTL__SHIFT 0x18
+#define UNIPHY_TMDP_REG0__ITXA_VSCALEN_MASK 0x4000000
+#define UNIPHY_TMDP_REG0__ITXA_VSCALEN__SHIFT 0x1a
+#define UNIPHY_TMDP_REG0__ITXA_IOCNTL_TSTSEL_MASK 0x78000000
+#define UNIPHY_TMDP_REG0__ITXA_IOCNTL_TSTSEL__SHIFT 0x1b
+#define UNIPHY_TMDP_REG0__ITXA_IMPVSCALEN_MASK 0x80000000
+#define UNIPHY_TMDP_REG0__ITXA_IMPVSCALEN__SHIFT 0x1f
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_TST_MASK 0x1f
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_TST__SHIFT 0x0
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL100_ADJ_MASK 0x1e0
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL100_ADJ__SHIFT 0x5
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL50_ADJ_MASK 0x1e00
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL50_ADJ__SHIFT 0x9
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_ADJ_MASK 0x1e000
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_ADJ__SHIFT 0xd
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_PDN_MASK 0x20000
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_PDN__SHIFT 0x11
+#define UNIPHY_TMDP_REG1__ITXA_IOCNTL_MASK 0xffc0000
+#define UNIPHY_TMDP_REG1__ITXA_IOCNTL__SHIFT 0x12
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_PLLREFSEL_MASK 0x10000000
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_PLLREFSEL__SHIFT 0x1c
+#define UNIPHY_TMDP_REG1__ITX_EDPSEL_MASK 0xe0000000
+#define UNIPHY_TMDP_REG1__ITX_EDPSEL__SHIFT 0x1d
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_PDN_MASK 0x1
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_PDN__SHIFT 0x0
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_EN_MASK 0x2
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_EN__SHIFT 0x1
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_MASK 0x3c
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET__SHIFT 0x2
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_EN_MASK 0x40
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_EN__SHIFT 0x6
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_MASK 0x3f80
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE__SHIFT 0x7
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_SET_MASK 0x4000
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_SET__SHIFT 0xe
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_PDN_MASK 0x10000
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_PDN__SHIFT 0x10
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_EN_MASK 0x20000
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_EN__SHIFT 0x11
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_MASK 0x3c0000
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET__SHIFT 0x12
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_EN_MASK 0x400000
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_EN__SHIFT 0x16
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_MASK 0x3f800000
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE__SHIFT 0x17
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_SET_MASK 0x40000000
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_SET__SHIFT 0x1e
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_PDN_MASK 0x1
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_PDN__SHIFT 0x0
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_EN_MASK 0x2
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_EN__SHIFT 0x1
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_MASK 0x3c
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET__SHIFT 0x2
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_EN_MASK 0x40
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_EN__SHIFT 0x6
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_MASK 0x3f80
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE__SHIFT 0x7
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_SET_MASK 0x4000
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_SET__SHIFT 0xe
+#define UNIPHY_TMDP_REG3__ITXA_PREM_ADJ_MASK 0xf8000
+#define UNIPHY_TMDP_REG3__ITXA_PREM_ADJ__SHIFT 0xf
+#define UNIPHY_TMDP_REG3__OTXA_RES_NCAL_MASK 0x1f00000
+#define UNIPHY_TMDP_REG3__OTXA_RES_NCAL__SHIFT 0x14
+#define UNIPHY_TMDP_REG3__OTXA_RES_PCAL_MASK 0x3e000000
+#define UNIPHY_TMDP_REG3__OTXA_RES_PCAL__SHIFT 0x19
+#define UNIPHY_TMDP_REG4__RESERVED_MASK 0x3fffff
+#define UNIPHY_TMDP_REG4__RESERVED__SHIFT 0x0
+#define UNIPHY_TMDP_REG4__OTXA_IOCNTL_NF_MASK 0x7fc00000
+#define UNIPHY_TMDP_REG4__OTXA_IOCNTL_NF__SHIFT 0x16
+#define UNIPHY_TMDP_REG5__OTXA0_IOFSM_TIMEOUT_MASK 0x1
+#define UNIPHY_TMDP_REG5__OTXA0_IOFSM_TIMEOUT__SHIFT 0x0
+#define UNIPHY_TMDP_REG5__OTXA0_RESCAL_DONE_MASK 0x2
+#define UNIPHY_TMDP_REG5__OTXA0_RESCAL_DONE__SHIFT 0x1
+#define UNIPHY_TMDP_REG5__OTXA1_IOFSM_TIMEOUT_MASK 0x4
+#define UNIPHY_TMDP_REG5__OTXA1_IOFSM_TIMEOUT__SHIFT 0x2
+#define UNIPHY_TMDP_REG5__OTXA1_RESCAL_DONE_MASK 0x8
+#define UNIPHY_TMDP_REG5__OTXA1_RESCAL_DONE__SHIFT 0x3
+#define UNIPHY_TMDP_REG5__OTXA2_IOFSM_TIMEOUT_MASK 0x10
+#define UNIPHY_TMDP_REG5__OTXA2_IOFSM_TIMEOUT__SHIFT 0x4
+#define UNIPHY_TMDP_REG5__OTXA2_RESCAL_DONE_MASK 0x20
+#define UNIPHY_TMDP_REG5__OTXA2_RESCAL_DONE__SHIFT 0x5
+#define UNIPHY_TMDP_REG5__OTXA3_IOFSM_TIMEOUT_MASK 0x40
+#define UNIPHY_TMDP_REG5__OTXA3_IOFSM_TIMEOUT__SHIFT 0x6
+#define UNIPHY_TMDP_REG5__OTXA3_RESCAL_DONE_MASK 0x80
+#define UNIPHY_TMDP_REG5__OTXA3_RESCAL_DONE__SHIFT 0x7
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_MASK 0x1ff00
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALN__SHIFT 0x8
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_DONE_MASK 0x20000
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_DONE__SHIFT 0x11
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_ERROR_MASK 0x40000
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_ERROR__SHIFT 0x12
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_MASK 0x780000
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALP__SHIFT 0x13
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_DONE_MASK 0x800000
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_DONE__SHIFT 0x17
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_ERROR_MASK 0x1000000
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_ERROR__SHIFT 0x18
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_MASK 0x3e000000
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS__SHIFT 0x19
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_DONE_MASK 0x40000000
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_DONE__SHIFT 0x1e
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_ERROR_MASK 0x80000000
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_ERROR__SHIFT 0x1f
+#define UNIPHY_TMDP_REG6__IRXA_OS_ADJ_MASK 0x1
+#define UNIPHY_TMDP_REG6__IRXA_OS_ADJ__SHIFT 0x0
+#define UNIPHY_TMDP_REG6__IRXA_OS_POLB_MASK 0x2
+#define UNIPHY_TMDP_REG6__IRXA_OS_POLB__SHIFT 0x1
+#define UNIPHY_TMDP_REG6__IRXA_BIST_SEL_MASK 0x4
+#define UNIPHY_TMDP_REG6__IRXA_BIST_SEL__SHIFT 0x2
+#define UNIPHY_TMDP_REG6__IRXA_SENADJ_MASK 0x78
+#define UNIPHY_TMDP_REG6__IRXA_SENADJ__SHIFT 0x3
+#define UNIPHY_TMDP_REG6__IRXA_CPSEL_MASK 0x780
+#define UNIPHY_TMDP_REG6__IRXA_CPSEL__SHIFT 0x7
+#define UNIPHY_TMDP_REG6__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x800
+#define UNIPHY_TMDP_REG6__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0xb
+#define UNIPHY_TPG_CONTROL__UNIPHY_STATIC_TEST_PATTERN_MASK 0x3ff
+#define UNIPHY_TPG_CONTROL__UNIPHY_STATIC_TEST_PATTERN__SHIFT 0x0
+#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_EN_MASK 0x10000
+#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_EN__SHIFT 0x10
+#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_SEL_MASK 0xe0000
+#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_SEL__SHIFT 0x11
+#define UNIPHY_TPG_SEED__UNIPHY_TPG_SEED_MASK 0x7fffff
+#define UNIPHY_TPG_SEED__UNIPHY_TPG_SEED__SHIFT 0x0
+#define UNIPHY_DEBUG__DEBUG0_MASK 0x3ff000
+#define UNIPHY_DEBUG__DEBUG0__SHIFT 0xc
+#define UNIPHY_DEBUG__DEBUG1_MASK 0x1c00000
+#define UNIPHY_DEBUG__DEBUG1__SHIFT 0x16
+#define UNIPHY_DEBUG__DBG_SEL_MASK 0x6000000
+#define UNIPHY_DEBUG__DBG_SEL__SHIFT 0x19
+#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff
+#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000
+#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff
+#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000
+#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3
+#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300
+#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000
+#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
+#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff
+#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000
+#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1
+#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
+#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7
+#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70
+#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff
+#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0
+#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff
+#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0
+#define DPG_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK 0x1
+#define DPG_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT 0x0
+#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0xff
+#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x0
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0xff
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0xff
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0xff
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x7
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x70
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x3f
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x7
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x7
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
+#define AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON_MASK 0x3f
+#define AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON__SHIFT 0x0
+#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK 0xffffffc0
+#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT 0x6
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xffffffff
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xffffffff
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xffffffff
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xffffffff
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xffffffff
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xffffffff
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xffffffff
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0
+#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x1
+#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0
+#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6
+#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1
+#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0xf8
+#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3
+#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0xf00
+#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8
+#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xf000
+#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc
+#define MINOR_VERSION__MINOR_VERSION_MASK 0xff
+#define MINOR_VERSION__MINOR_VERSION__SHIFT 0x0
+#define MAJOR_VERSION__MAJOR_VERSION_MASK 0xff
+#define MAJOR_VERSION__MAJOR_VERSION__SHIFT 0x0
+#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff
+#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
+#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff
+#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
+#define GLOBAL_CONTROL__CONTROLLER_RESET_MASK 0x1
+#define GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT 0x0
+#define GLOBAL_CONTROL__FLUSH_CONTROL_MASK 0x2
+#define GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT 0x1
+#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK 0x100
+#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT 0x8
+#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK 0x1
+#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT 0x0
+#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK 0x1
+#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT 0x0
+#define GLOBAL_STATUS__FLUSH_STATUS_MASK 0x2
+#define GLOBAL_STATUS__FLUSH_STATUS__SHIFT 0x1
+#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff
+#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x0
+#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xffff
+#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x0
+#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK 0x1
+#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT 0x0
+#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK 0x2
+#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT 0x1
+#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK 0x4
+#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT 0x2
+#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK 0x8
+#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT 0x3
+#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK 0x10
+#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT 0x4
+#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK 0x20
+#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT 0x5
+#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK 0x40
+#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT 0x6
+#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK 0x80
+#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT 0x7
+#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK 0x100
+#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT 0x8
+#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK 0x200
+#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT 0x9
+#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK 0x400
+#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT 0xa
+#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK 0x800
+#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT 0xb
+#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK 0x1000
+#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT 0xc
+#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK 0x2000
+#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT 0xd
+#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK 0x4000
+#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT 0xe
+#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK 0x8000
+#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT 0xf
+#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000
+#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT 0x1e
+#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK 0x80000000
+#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT 0x1f
+#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK 0x1
+#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT 0x0
+#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK 0x2
+#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT 0x1
+#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK 0x4
+#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT 0x2
+#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK 0x8
+#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT 0x3
+#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK 0x10
+#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT 0x4
+#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK 0x20
+#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT 0x5
+#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK 0x40
+#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT 0x6
+#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK 0x80
+#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT 0x7
+#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK 0x100
+#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT 0x8
+#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK 0x200
+#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT 0x9
+#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK 0x400
+#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT 0xa
+#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK 0x800
+#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT 0xb
+#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK 0x1000
+#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT 0xc
+#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK 0x2000
+#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT 0xd
+#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK 0x4000
+#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT 0xe
+#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK 0x8000
+#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT 0xf
+#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK 0x40000000
+#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT 0x1e
+#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK 0x80000000
+#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT 0x1f
+#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK 0xffffffff
+#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT 0x0
+#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK 0x1
+#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT 0x0
+#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK 0x2
+#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT 0x1
+#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK 0x4
+#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT 0x2
+#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK 0x8
+#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT 0x3
+#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK 0x10
+#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT 0x4
+#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK 0x20
+#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT 0x5
+#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION_MASK 0x40
+#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION__SHIFT 0x6
+#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION_MASK 0x80
+#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION__SHIFT 0x7
+#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION_MASK 0x100
+#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION__SHIFT 0x8
+#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION_MASK 0x200
+#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION__SHIFT 0x9
+#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION_MASK 0x400
+#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT 0xa
+#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION_MASK 0x800
+#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION__SHIFT 0xb
+#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION_MASK 0x1000
+#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION__SHIFT 0xc
+#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION_MASK 0x2000
+#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION__SHIFT 0xd
+#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION_MASK 0x4000
+#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION__SHIFT 0xe
+#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION_MASK 0x8000
+#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION__SHIFT 0xf
+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f
+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK 0xffffff80
+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK 0xffffffff
+#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0xff
+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0
+#define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0xff
+#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0
+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000
+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf
+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x1
+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0
+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x2
+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1
+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x1
+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0
+#define CORB_SIZE__CORB_SIZE_MASK 0x3
+#define CORB_SIZE__CORB_SIZE__SHIFT 0x0
+#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0xf0
+#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xffffff80
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xffffffff
+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0xff
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf
+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0xff
+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0
+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x1
+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0
+#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2
+#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1
+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x4
+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2
+#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x1
+#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0
+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x4
+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2
+#define RIRB_SIZE__RIRB_SIZE_MASK 0x3
+#define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0
+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0xf0
+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0xfffffff
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xf0000000
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xffffffff
+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x1
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x2
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x1
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7e
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xffffff80
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xffffffff
+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xffffffff
+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x1
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x2
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x4
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x8
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x10
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x30000
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x40000
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0xf00000
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x4000000
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x8000000
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xffffffff
+#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xffffffff
+#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0xff
+#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xffff
+#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x70
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x7f
+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xffffff80
+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xffffffff
+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xffffffff
+#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x8000
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x7f
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x80
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x7f
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x100
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x200
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0xfc00
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x78
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x80
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x78
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0xff
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0xffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0xffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0xff
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0
+#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0xff
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0xff00
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0xff0000
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x1
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x10
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0xffff
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xffff0000
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x300
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8
+#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK 0x30
+#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT 0x4
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xffffffff
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x3
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0xc
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x30
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0xc0
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x10000
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x20000
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x3
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0xc
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x30
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0xc0
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x1
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x10
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x1e0
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x1
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x10
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xffffffff
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x1
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff0000
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0xff
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x100
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0xff0000
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xffff0000
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10
+#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK 0xffffffff
+#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT 0x0
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x3
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x4
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x18
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x20
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0xc0
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x100
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x600
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x800
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x3000
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x4000
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x18000
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x20000
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0xc0000
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x100000
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x3
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0xc
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x30
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0xc0
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x300
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0xc00
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x3000
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc
+#define DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN_MASK 0x1
+#define DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x1
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x10
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x700
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xffffffff
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0xffff
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x1
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x700
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xffffffff
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xffffffff
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xffffffff
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xffffffff
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xffffffff
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xffffffff
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xffffffff
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xffffffff
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xffffffff
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x1
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x10
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x700
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xffffffff
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0xffff
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x1
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x700
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xffffffff
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xffffffff
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xffffffff
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xffffffff
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xffffffff
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xffffffff
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xffffffff
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xffffffff
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xffffffff
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0
+#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x1
+#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x10
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x1
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
+#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xffffffff
+#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0
+#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x1
+#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x10
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x1
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
+#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xffffffff
+#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0
+#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK 0xff
+#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT 0x0
+#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK 0xffffffff
+#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT 0x0
+#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0xff
+#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x100
+#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xffffffff
+#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x7f
+#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x7f00
+#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0xff0000
+#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x1
+#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xffffffff
+#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xffffffff
+#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xffffffff
+#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xffffffff
+#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0
+#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x3fff
+#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xffffffff
+#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3
+#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000
+#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x4
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG_MASK 0xffffffff
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xffffffff
+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xffffffff
+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xffffffff
+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40
+#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x7f
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x10000
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x20000
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0xfc0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x3000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x100
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x200
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x10000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x20000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf00000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x2
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x100
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x200
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0xf000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x10000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x20000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf00000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0xffff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xffff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0xff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xffffffff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xffffffff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0xff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xff000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0xff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xff000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0xff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xff000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0xff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xff000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0xff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff
+#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff
+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff
+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0xff
+#define AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x2
+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x3
+#define AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+#define AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x1
+#define AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x1
+#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x10
+#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x100
+#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x1
+#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x10
+#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x100
+#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x1
+#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x10
+#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x100
+#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+#define AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x3fff
+#define AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xffffffff
+#define AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xffffffff
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x20
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x2
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x100
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x200
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x10000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x20000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0xf00000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x2
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x100
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x200
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x10000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x20000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0xf00000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x6
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x10
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x20
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x7
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0xff00
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0xff0000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x20
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x20
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0xff00
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0xff0000
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xffffffff
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xffffffff
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0xff
+#define BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
+#define BLND_CONTROL__BLND_MODE_MASK 0x300
+#define BLND_CONTROL__BLND_MODE__SHIFT 0x8
+#define BLND_CONTROL__BLND_STEREO_TYPE_MASK 0xc00
+#define BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
+#define BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x1000
+#define BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
+#define BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x2000
+#define BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
+#define BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x30000
+#define BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
+#define BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x100000
+#define BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
+#define BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xff000000
+#define BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
+#define SM_CONTROL2__SM_MODE_MASK 0x7
+#define SM_CONTROL2__SM_MODE__SHIFT 0x0
+#define SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x10
+#define SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
+#define SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x20
+#define SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
+#define SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x300
+#define SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+#define SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x30000
+#define SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+#define SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x1000000
+#define SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
+#define BLND_CONTROL2__PTI_ENABLE_MASK 0x1
+#define BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0
+#define BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x30
+#define BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
+#define BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x40
+#define BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
+#define BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x80
+#define BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
+#define BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x100
+#define BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
+#define BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x1
+#define BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
+#define BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x100
+#define BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
+#define BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x10000
+#define BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x1
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x100
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x1000
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x30000
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
+#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x1
+#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
+#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x2
+#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
+#define BLND_V_UPDATE_LOCK__BLND_DCP_OVL_V_UPDATE_LOCK_MASK 0x100
+#define BLND_V_UPDATE_LOCK__BLND_DCP_OVL_V_UPDATE_LOCK__SHIFT 0x8
+#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x10000
+#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
+#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK 0x1000000
+#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT 0x18
+#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000
+#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
+#define BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000
+#define BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
+#define BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000
+#define BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x1
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x2
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x4
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x8
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_OVL_UPDATE_PENDING_MASK 0x10
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_OVL_UPDATE_PENDING__SHIFT 0x4
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_OVL_UPDATE_PENDING_MASK 0x20
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_OVL_UPDATE_PENDING__SHIFT 0x5
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x40
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x80
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
+#define BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x100
+#define BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
+#define BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x200
+#define BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
+#define BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x400
+#define BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
+#define BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x800
+#define BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
+#define BLND_DEBUG__BLND_CNV_MUX_SELECT_MASK 0x1
+#define BLND_DEBUG__BLND_CNV_MUX_SELECT__SHIFT 0x0
+#define BLND_DEBUG__BLND_DEBUG_MASK 0xfffffffe
+#define BLND_DEBUG__BLND_DEBUG__SHIFT 0x1
+#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK 0xff
+#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT 0x0
+#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK 0xffffffff
+#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT 0x0
+#define WB_ENABLE__WB_ENABLE_MASK 0x1
+#define WB_ENABLE__WB_ENABLE__SHIFT 0x0
+#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS_MASK 0x1
+#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS__SHIFT 0x0
+#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS_MASK 0x2
+#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS__SHIFT 0x1
+#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS_MASK 0x4
+#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS__SHIFT 0x2
+#define WB_EC_CONFIG__DISPCLK_R_WB_RAMP_DIS_MASK 0x8
+#define WB_EC_CONFIG__DISPCLK_R_WB_RAMP_DIS__SHIFT 0x3
+#define WB_EC_CONFIG__DISPCLK_G_WB_RAMP_DIS_MASK 0x10
+#define WB_EC_CONFIG__DISPCLK_G_WB_RAMP_DIS__SHIFT 0x4
+#define WB_EC_CONFIG__DISPCLK_G_WBSCL_RAMP_DIS_MASK 0x20
+#define WB_EC_CONFIG__DISPCLK_G_WBSCL_RAMP_DIS__SHIFT 0x5
+#define WB_EC_CONFIG__WB_LB_LS_DIS_MASK 0x40
+#define WB_EC_CONFIG__WB_LB_LS_DIS__SHIFT 0x6
+#define WB_EC_CONFIG__WB_LB_SD_DIS_MASK 0x80
+#define WB_EC_CONFIG__WB_LB_SD_DIS__SHIFT 0x7
+#define WB_EC_CONFIG__WB_LUT_LS_DIS_MASK 0x100
+#define WB_EC_CONFIG__WB_LUT_LS_DIS__SHIFT 0x8
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK 0x600
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL__SHIFT 0x9
+#define WB_EC_CONFIG__WB_TEST_CLK_SEL_MASK 0xf000
+#define WB_EC_CONFIG__WB_TEST_CLK_SEL__SHIFT 0xc
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS_MASK 0x10000
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS__SHIFT 0x10
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE_MASK 0x60000
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE__SHIFT 0x11
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_MASK 0x180000
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE__SHIFT 0x13
+#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE_MASK 0x800000
+#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE__SHIFT 0x17
+#define WB_EC_CONFIG__LB_MEM_PWR_STATE_MASK 0x30000000
+#define WB_EC_CONFIG__LB_MEM_PWR_STATE__SHIFT 0x1c
+#define WB_EC_CONFIG__LUT_MEM_PWR_STATE_MASK 0xc0000000
+#define WB_EC_CONFIG__LUT_MEM_PWR_STATE__SHIFT 0x1e
+#define CNV_MODE__CNV_FRAME_CAPTURE_RATE_MASK 0x300
+#define CNV_MODE__CNV_FRAME_CAPTURE_RATE__SHIFT 0x8
+#define CNV_MODE__CNV_WINDOW_CROP_EN_MASK 0x1000
+#define CNV_MODE__CNV_WINDOW_CROP_EN__SHIFT 0xc
+#define CNV_MODE__CNV_STEREO_TYPE_MASK 0x6000
+#define CNV_MODE__CNV_STEREO_TYPE__SHIFT 0xd
+#define CNV_MODE__CNV_INTERLACED_MODE_MASK 0x8000
+#define CNV_MODE__CNV_INTERLACED_MODE__SHIFT 0xf
+#define CNV_MODE__CNV_EYE_SELECTION_MASK 0x30000
+#define CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10
+#define CNV_MODE__CNV_STEREO_POLARITY_MASK 0x40000
+#define CNV_MODE__CNV_STEREO_POLARITY__SHIFT 0x12
+#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER_MASK 0x80000
+#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER__SHIFT 0x13
+#define CNV_MODE__CNV_STEREO_SPLIT_MASK 0x100000
+#define CNV_MODE__CNV_STEREO_SPLIT__SHIFT 0x14
+#define CNV_MODE__CNV_NEW_CONTENT_MASK 0x1000000
+#define CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18
+#define CNV_MODE__CNV_FRAME_CAPTURE_EN_MASK 0x80000000
+#define CNV_MODE__CNV_FRAME_CAPTURE_EN__SHIFT 0x1f
+#define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0xfff
+#define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0
+#define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0xfff0000
+#define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10
+#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0xfff
+#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0
+#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0xfff0000
+#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10
+#define CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x1
+#define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0
+#define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x100
+#define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8
+#define CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x10000
+#define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10
+#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x7fff
+#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0
+#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7fff0000
+#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10
+#define CNV_CSC_CONTROL__CNV_CSC_BYPASS_MASK 0x1
+#define CNV_CSC_CONTROL__CNV_CSC_BYPASS__SHIFT 0x0
+#define CNV_CSC_C11_C12__CNV_CSC_C11_MASK 0x1fff
+#define CNV_CSC_C11_C12__CNV_CSC_C11__SHIFT 0x0
+#define CNV_CSC_C11_C12__CNV_CSC_C12_MASK 0x1fff0000
+#define CNV_CSC_C11_C12__CNV_CSC_C12__SHIFT 0x10
+#define CNV_CSC_C13_C14__CNV_CSC_C13_MASK 0x1fff
+#define CNV_CSC_C13_C14__CNV_CSC_C13__SHIFT 0x0
+#define CNV_CSC_C13_C14__CNV_CSC_C14_MASK 0x7fff0000
+#define CNV_CSC_C13_C14__CNV_CSC_C14__SHIFT 0x10
+#define CNV_CSC_C21_C22__CNV_CSC_C21_MASK 0x1fff
+#define CNV_CSC_C21_C22__CNV_CSC_C21__SHIFT 0x0
+#define CNV_CSC_C21_C22__CNV_CSC_C22_MASK 0x1fff0000
+#define CNV_CSC_C21_C22__CNV_CSC_C22__SHIFT 0x10
+#define CNV_CSC_C23_C24__CNV_CSC_C23_MASK 0x1fff
+#define CNV_CSC_C23_C24__CNV_CSC_C23__SHIFT 0x0
+#define CNV_CSC_C23_C24__CNV_CSC_C24_MASK 0x7fff0000
+#define CNV_CSC_C23_C24__CNV_CSC_C24__SHIFT 0x10
+#define CNV_CSC_C31_C32__CNV_CSC_C31_MASK 0x1fff
+#define CNV_CSC_C31_C32__CNV_CSC_C31__SHIFT 0x0
+#define CNV_CSC_C31_C32__CNV_CSC_C32_MASK 0x1fff0000
+#define CNV_CSC_C31_C32__CNV_CSC_C32__SHIFT 0x10
+#define CNV_CSC_C33_C34__CNV_CSC_C33_MASK 0x1fff
+#define CNV_CSC_C33_C34__CNV_CSC_C33__SHIFT 0x0
+#define CNV_CSC_C33_C34__CNV_CSC_C34_MASK 0x7fff0000
+#define CNV_CSC_C33_C34__CNV_CSC_C34__SHIFT 0x10
+#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R_MASK 0xffff
+#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R__SHIFT 0x0
+#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G_MASK 0xffff
+#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G__SHIFT 0x0
+#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B_MASK 0xffff
+#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B__SHIFT 0x0
+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R_MASK 0xffff
+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R__SHIFT 0x0
+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R_MASK 0xffff0000
+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R__SHIFT 0x10
+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G_MASK 0xffff
+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G__SHIFT 0x0
+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G_MASK 0xffff0000
+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G__SHIFT 0x10
+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B_MASK 0xffff
+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B__SHIFT 0x0
+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B_MASK 0xffff0000
+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B__SHIFT 0x10
+#define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x10
+#define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4
+#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x100
+#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8
+#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY_MASK 0x10000
+#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY__SHIFT 0x10
+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0xfff0
+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x4
+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xffff0000
+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10
+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0xfff0
+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x4
+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xffff0000
+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10
+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0xfff0
+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x4
+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xffff0000
+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10
+#define WB_DEBUG_CTRL__WB_DEBUG_EN_MASK 0x1
+#define WB_DEBUG_CTRL__WB_DEBUG_EN__SHIFT 0x0
+#define WB_DEBUG_CTRL__WB_DEBUG_SEL_MASK 0xc0
+#define WB_DEBUG_CTRL__WB_DEBUG_SEL__SHIFT 0x6
+#define WB_DBG_MODE__WB_DBG_MODE_EN_MASK 0x1
+#define WB_DBG_MODE__WB_DBG_MODE_EN__SHIFT 0x0
+#define WB_DBG_MODE__WB_DBG_DIN_FMT_MASK 0x2
+#define WB_DBG_MODE__WB_DBG_DIN_FMT__SHIFT 0x1
+#define WB_DBG_MODE__WB_DBG_36MODE_MASK 0x4
+#define WB_DBG_MODE__WB_DBG_36MODE__SHIFT 0x2
+#define WB_DBG_MODE__WB_DBG_CMAP_MASK 0x8
+#define WB_DBG_MODE__WB_DBG_CMAP__SHIFT 0x3
+#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR_MASK 0x100
+#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR__SHIFT 0x8
+#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH_MASK 0x7fff0000
+#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH__SHIFT 0x10
+#define WB_HW_DEBUG__WB_HW_DEBUG_MASK 0xffffffff
+#define WB_HW_DEBUG__WB_HW_DEBUG__SHIFT 0x0
+#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT_MASK 0x3
+#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT__SHIFT 0x0
+#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT_MASK 0x1c
+#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT__SHIFT 0x2
+#define WB_SOFT_RESET__WB_SOFT_RESET_MASK 0x1
+#define WB_SOFT_RESET__WB_SOFT_RESET__SHIFT 0x0
+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX_MASK 0xff
+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX__SHIFT 0x0
+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA_MASK 0xffffffff
+#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA__SHIFT 0x0
+#define DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x10
+#define DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
+#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x100
+#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
+#define DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x1000
+#define DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
+#define DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1f000000
+#define DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18
+#define DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000
+#define DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f
+#define DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x1
+#define DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0
+#define DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x2
+#define DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1
+#define DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x4
+#define DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2
+#define DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x8
+#define DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3
+#define DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x10
+#define DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
+#define DCFE_DBG_CONFIG__DCFE_DBG_EN_MASK 0x1
+#define DCFE_DBG_CONFIG__DCFE_DBG_EN__SHIFT 0x0
+#define DCFE_DBG_CONFIG__DCFE_DBG_SEL_MASK 0xf0
+#define DCFE_DBG_CONFIG__DCFE_DBG_SEL__SHIFT 0x4
+#define DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE_MASK 0x8
+#define DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE__SHIFT 0x3
+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE_MASK 0x80
+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE__SHIFT 0x7
+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE_MASK 0x200
+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE__SHIFT 0x9
+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE_MASK 0x800
+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE__SHIFT 0xb
+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE_MASK 0x2000
+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE__SHIFT 0xd
+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE_MASK 0x8000
+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE__SHIFT 0xf
+#define DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL_MASK 0x1f000000
+#define DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL__SHIFT 0x18
+#define DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE_MASK 0x80000000
+#define DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE__SHIFT 0x1f
+#define DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET_MASK 0x1
+#define DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET__SHIFT 0x0
+#define DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET_MASK 0x2
+#define DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET__SHIFT 0x1
+#define DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET_MASK 0x4
+#define DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET__SHIFT 0x2
+#define DCFEV_SOFT_RESET__SCLV_SOFT_RESET_MASK 0x8
+#define DCFEV_SOFT_RESET__SCLV_SOFT_RESET__SHIFT 0x3
+#define DCFEV_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x10
+#define DCFEV_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
+#define DCFEV_SOFT_RESET__PSCLV_SOFT_RESET_MASK 0x20
+#define DCFEV_SOFT_RESET__PSCLV_SOFT_RESET__SHIFT 0x5
+#define DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET_MASK 0x40
+#define DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET__SHIFT 0x6
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS_MASK 0x8
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x3
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS_MASK 0x10
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS__SHIFT 0x4
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS_MASK 0x20
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS__SHIFT 0x5
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET_MASK 0x40
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET__SHIFT 0x6
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL_MASK 0x1f000000
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL__SHIFT 0x18
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE_MASK 0x80000000
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE__SHIFT 0x1f
+#define DCFEV_DBG_CONFIG__DCFEV_DBG_EN_MASK 0x1
+#define DCFEV_DBG_CONFIG__DCFEV_DBG_EN__SHIFT 0x0
+#define DCFEV_DBG_CONFIG__DCFEV_DBG_SEL_MASK 0xf0
+#define DCFEV_DBG_CONFIG__DCFEV_DBG_SEL__SHIFT 0x4
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL_MASK 0x3
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL__SHIFT 0x0
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE_MASK 0x4
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE__SHIFT 0x2
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE_MASK 0x8
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE__SHIFT 0x3
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE_MASK 0x10
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE__SHIFT 0x4
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE_MASK 0x20
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE__SHIFT 0x5
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE_MASK 0x40
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE__SHIFT 0x6
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE_MASK 0x80
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE__SHIFT 0x7
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE_MASK 0x100
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE__SHIFT 0x8
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE_MASK 0x200
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE__SHIFT 0x9
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE_MASK 0x400
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE__SHIFT 0xa
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE_MASK 0x800
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE__SHIFT 0xb
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE_MASK 0x3
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE__SHIFT 0x0
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE_MASK 0xc
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE__SHIFT 0x2
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE_MASK 0x30
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE__SHIFT 0x4
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE_MASK 0xc0
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE__SHIFT 0x6
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE_MASK 0x300
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE__SHIFT 0x8
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE_MASK 0xc00
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE__SHIFT 0xa
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE_MASK 0x3000
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE__SHIFT 0xc
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE_MASK 0xc000
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE__SHIFT 0xe
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE_MASK 0x30000
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE__SHIFT 0x10
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE_MASK 0xc0000
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE__SHIFT 0x12
+#define DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x1
+#define DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
+#define DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x2
+#define DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
+#define DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x10
+#define DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
+#define DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x100
+#define DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
+#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000
+#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000
+#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+#define DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x1
+#define DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
+#define DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x100
+#define DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
+#define DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x10000
+#define DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
+#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x100000
+#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
+#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x1000000
+#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
+#define DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x1fff
+#define DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
+#define DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x3ff0000
+#define DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
+#define DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000
+#define DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0xff
+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000
+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x1000000
+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000
+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0xff
+#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
+#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0xff00000
+#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
+#define DCO_SCRATCH0__DCO_SCRATCH0_MASK 0xffffffff
+#define DCO_SCRATCH0__DCO_SCRATCH0__SHIFT 0x0
+#define DCO_SCRATCH1__DCO_SCRATCH1_MASK 0xffffffff
+#define DCO_SCRATCH1__DCO_SCRATCH1__SHIFT 0x0
+#define DCO_SCRATCH2__DCO_SCRATCH2_MASK 0xffffffff
+#define DCO_SCRATCH2__DCO_SCRATCH2__SHIFT 0x0
+#define DCO_SCRATCH3__DCO_SCRATCH3_MASK 0xffffffff
+#define DCO_SCRATCH3__DCO_SCRATCH3__SHIFT 0x0
+#define DCO_SCRATCH4__DCO_SCRATCH4_MASK 0xffffffff
+#define DCO_SCRATCH4__DCO_SCRATCH4__SHIFT 0x0
+#define DCO_SCRATCH5__DCO_SCRATCH5_MASK 0xffffffff
+#define DCO_SCRATCH5__DCO_SCRATCH5__SHIFT 0x0
+#define DCO_SCRATCH6__DCO_SCRATCH6_MASK 0xffffffff
+#define DCO_SCRATCH6__DCO_SCRATCH6__SHIFT 0x0
+#define DCO_SCRATCH7__DCO_SCRATCH7_MASK 0xffffffff
+#define DCO_SCRATCH7__DCO_SCRATCH7__SHIFT 0x0
+#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x7
+#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x0
+#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x70
+#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
+#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x1000000
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x1000000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT_MASK 0x800
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT_MASK 0x800
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT_MASK 0x800
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1b
+#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK 0x1
+#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT 0x0
+#define DCO_MEM_PWR_STATUS__TVOUT_MEM_PWR_STATE_MASK 0x2
+#define DCO_MEM_PWR_STATUS__TVOUT_MEM_PWR_STATE__SHIFT 0x1
+#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE_MASK 0x4
+#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE__SHIFT 0x2
+#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK 0x8
+#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT 0x3
+#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK 0x10
+#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT 0x4
+#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK 0x20
+#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT 0x5
+#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK 0x40
+#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT 0x6
+#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK 0x80
+#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT 0x7
+#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK 0x100
+#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT 0x8
+#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK 0x200
+#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT 0x9
+#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE_MASK 0xc00
+#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE__SHIFT 0xa
+#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE_MASK 0x3000
+#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE__SHIFT 0xc
+#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE_MASK 0xc000
+#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE__SHIFT 0xe
+#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE_MASK 0x30000
+#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE__SHIFT 0x10
+#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE_MASK 0xc0000
+#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE__SHIFT 0x12
+#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE_MASK 0x300000
+#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE__SHIFT 0x14
+#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE_MASK 0xc00000
+#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE__SHIFT 0x16
+#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK 0x1
+#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x0
+#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK 0x2
+#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT 0x1
+#define DCO_MEM_PWR_CTRL__TVOUT_LIGHT_SLEEP_DIS_MASK 0x4
+#define DCO_MEM_PWR_CTRL__TVOUT_LIGHT_SLEEP_DIS__SHIFT 0x2
+#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS_MASK 0x8
+#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS__SHIFT 0x3
+#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK 0x10
+#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT 0x4
+#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK 0x20
+#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT 0x5
+#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK 0x40
+#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT 0x6
+#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK 0x80
+#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT 0x7
+#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK 0x100
+#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT 0x8
+#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK 0x200
+#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT 0x9
+#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK 0x400
+#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT 0xa
+#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE_MASK 0x1800
+#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE__SHIFT 0xb
+#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS_MASK 0x2000
+#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS__SHIFT 0xd
+#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE_MASK 0xc000
+#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE__SHIFT 0xe
+#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS_MASK 0x10000
+#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS__SHIFT 0x10
+#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE_MASK 0x60000
+#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE__SHIFT 0x11
+#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS_MASK 0x80000
+#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS__SHIFT 0x13
+#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE_MASK 0x300000
+#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE__SHIFT 0x14
+#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS_MASK 0x400000
+#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS__SHIFT 0x16
+#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE_MASK 0x1800000
+#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE__SHIFT 0x17
+#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS_MASK 0x2000000
+#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS__SHIFT 0x19
+#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE_MASK 0xc000000
+#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE__SHIFT 0x1a
+#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS_MASK 0x10000000
+#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS__SHIFT 0x1c
+#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE_MASK 0x60000000
+#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE__SHIFT 0x1d
+#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS_MASK 0x80000000
+#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS__SHIFT 0x1f
+#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL_MASK 0x3
+#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL__SHIFT 0x0
+#define DCO_CLK_CNTL__DCO_TEST_CLK_SEL_MASK 0x1f
+#define DCO_CLK_CNTL__DCO_TEST_CLK_SEL__SHIFT 0x0
+#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x20
+#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x5
+#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x40
+#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x6
+#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x80
+#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x7
+#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x100
+#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x8
+#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x200
+#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x9
+#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS_MASK 0x400
+#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS__SHIFT 0xa
+#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x10000
+#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x10
+#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x20000
+#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x11
+#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x40000
+#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x12
+#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x80000
+#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x13
+#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x100000
+#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x14
+#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x200000
+#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x15
+#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x1000000
+#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18
+#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x2000000
+#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19
+#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x4000000
+#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a
+#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x8000000
+#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b
+#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000
+#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c
+#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000
+#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d
+#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000
+#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e
+#define DCO_CLK_RAMP_CNTL__REFCLK_R_DCO_RAMP_DIS_MASK 0x10
+#define DCO_CLK_RAMP_CNTL__REFCLK_R_DCO_RAMP_DIS__SHIFT 0x4
+#define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS_MASK 0x20
+#define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS__SHIFT 0x5
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS_MASK 0x40
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS__SHIFT 0x6
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS_MASK 0x80
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS__SHIFT 0x7
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS_MASK 0x100
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS__SHIFT 0x8
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS_MASK 0x200
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS__SHIFT 0x9
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS_MASK 0x10000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS__SHIFT 0x10
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS_MASK 0x20000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS__SHIFT 0x11
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS_MASK 0x40000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS__SHIFT 0x12
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS_MASK 0x80000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS__SHIFT 0x13
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS_MASK 0x100000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS__SHIFT 0x14
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS_MASK 0x200000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS__SHIFT 0x15
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS_MASK 0x1000000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS__SHIFT 0x18
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS_MASK 0x2000000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS__SHIFT 0x19
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS_MASK 0x4000000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS__SHIFT 0x1a
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS_MASK 0x8000000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS__SHIFT 0x1b
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS_MASK 0x10000000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS__SHIFT 0x1c
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS_MASK 0x20000000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS__SHIFT 0x1d
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGG_RAMP_DIS_MASK 0x40000000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGG_RAMP_DIS__SHIFT 0x1e
+#define DPDBG_CNTL__DPDBG_ENABLE_MASK 0x1
+#define DPDBG_CNTL__DPDBG_ENABLE__SHIFT 0x0
+#define DPDBG_CNTL__DPDBG_INPUT_ENABLE_MASK 0x2
+#define DPDBG_CNTL__DPDBG_INPUT_ENABLE__SHIFT 0x1
+#define DPDBG_CNTL__DPDBG_SYMCLK_ON_MASK 0x10
+#define DPDBG_CNTL__DPDBG_SYMCLK_ON__SHIFT 0x4
+#define DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE_MASK 0x100
+#define DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE__SHIFT 0x8
+#define DPDBG_CNTL__DPDBG_LINE_LENGTH_MASK 0xffff0000
+#define DPDBG_CNTL__DPDBG_LINE_LENGTH__SHIFT 0x10
+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK_MASK 0x1
+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK__SHIFT 0x0
+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE_MASK 0x2
+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE__SHIFT 0x1
+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK_MASK 0x100
+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK__SHIFT 0x8
+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED_MASK 0x10000
+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED__SHIFT 0x10
+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS_MASK 0x1000000
+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS__SHIFT 0x18
+#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x1
+#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0
+#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x100
+#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8
+#define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x1
+#define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x0
+#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK 0x10
+#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT 0x4
+#define DCO_SOFT_RESET__I2S1_SOFT_RESET_MASK 0x20
+#define DCO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT 0x5
+#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK 0x40
+#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT 0x6
+#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET_MASK 0x1000
+#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET__SHIFT 0xc
+#define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x10000
+#define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x10
+#define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x20000
+#define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x11
+#define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x40000
+#define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x12
+#define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x80000
+#define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x13
+#define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x100000
+#define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x14
+#define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x200000
+#define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x15
+#define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x1000000
+#define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x18
+#define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x2000000
+#define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x19
+#define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x8000000
+#define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x1b
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x1
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x2
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x10
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x20
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x100
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x200
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x1000
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x2000
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x10000
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x20000
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x100000
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x200000
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x1000000
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x2000000
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19
+#define DIG_SOFT_RESET__DPDBG_SOFT_RESET_MASK 0x80000000
+#define DIG_SOFT_RESET__DPDBG_SOFT_RESET__SHIFT 0x1f
+#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x7
+#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x0
+#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x70000
+#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x10
+#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX_MASK 0xff
+#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA__SHIFT 0x0
+#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x1
+#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x2
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x4
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x8
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x700
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x300000
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14
+#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000
+#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x1f
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x3
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0xc
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x10
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x100
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x1000
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x100000
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x200000
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x1000000
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x2000000
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x1
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x2
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x4
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x10
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x20
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x40
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x100
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x200
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x400
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x1000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x2000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x4000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x10000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x20000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x40000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x100000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x200000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x400000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x1000000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x2000000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x4000000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x8000000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x3
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x4
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x10
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x20
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x40
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x80
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x100
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x1000
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x2000
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x4000
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x8000
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x40000
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x3
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x8
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x10000
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x20000
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x100000
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x3
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x8
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x10000
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x20000
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x100000
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x3
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x8
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x10000
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x20000
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x100000
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x3
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x8
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x10000
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x20000
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x100000
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x3
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x8
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x10000
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x20000
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x100000
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x3
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x8
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x10000
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x20000
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x100000
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x3
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x300
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xffff0000
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x1
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x2
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x10
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x20
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x40
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x80
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0xff00
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0xff0000
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xff000000
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x3
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x300
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xffff0000
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x1
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x2
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x10
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x20
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x40
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x80
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0xff00
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0xff0000
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xff000000
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x3
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK 0x300
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xffff0000
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x1
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x2
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x10
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x20
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x40
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x80
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0xff00
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0xff0000
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xff000000
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x3
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK 0x300
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xffff0000
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x1
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x2
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x10
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x20
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x40
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x80
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0xff00
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0xff0000
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xff000000
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x3
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK 0x300
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xffff0000
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x1
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x2
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x10
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x20
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x40
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x80
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0xff00
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0xff0000
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xff000000
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x3
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL_MASK 0x300
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xffff0000
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x1
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x2
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x10
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x20
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x40
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x80
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0xff00
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0xff0000
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xff000000
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x1
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x100
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8
+#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x1000
+#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x2000
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0xff0000
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x1
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x100
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8
+#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x1000
+#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x2000
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0xff0000
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x1
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x100
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8
+#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x1000
+#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x2000
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0xff0000
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x1
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x100
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8
+#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x1000
+#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x2000
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0xff0000
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10
+#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x1
+#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0
+#define DC_I2C_DATA__DC_I2C_DATA_MASK 0xff00
+#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8
+#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0xff0000
+#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x3
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x8
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x10000
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x20000
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x11
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x100000
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x3
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL_MASK 0x300
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xffff0000
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x1
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x2
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x10
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x20
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x40
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x6
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x80
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0xff00
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0xff0000
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xff000000
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0xffff
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0xf00000
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x1
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x2
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x4
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x8
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x10
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x20
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x40
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x80
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x100
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x200
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x400
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x800
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x1000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x2000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x4000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x8000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x10000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x20000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x40000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x80000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x100000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x200000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x400000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x800000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x1000000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x2000000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x4000000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x8000000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x1
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x0
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x2
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x1
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x4
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x2
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x8
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x3
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK 0x80000000
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT 0x1f
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x1
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x0
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x2
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x1
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x4
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x2
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED_MASK 0x100
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED__SHIFT 0x8
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_MASK 0x200
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT__SHIFT 0x9
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK_MASK 0x400
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK__SHIFT 0xa
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK_MASK 0x800
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK__SHIFT 0xb
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x1000
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0xc
+#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0xf
+#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x0
+#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x10
+#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x4
+#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x20
+#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x5
+#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x40
+#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x6
+#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x200
+#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x9
+#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x400
+#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0xa
+#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x3
+#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x0
+#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL_MASK 0x300
+#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xffff0000
+#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x10
+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x1
+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x0
+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x2
+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x1
+#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x80
+#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x7
+#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0xff00
+#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x8
+#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xff000000
+#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x18
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x1
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x0
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x100
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x8
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x200
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x9
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x1000
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0xc
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x2000
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0xd
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0xf0000
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x10
+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x1
+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x0
+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0xff00
+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x8
+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0xf0000
+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x10
+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000
+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x1f
+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x7f
+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x0
+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x7f00
+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x8
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK 0x1
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT 0x0
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK 0x2
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT 0x1
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK 0x4
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT 0x2
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK 0x10
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT 0x4
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK 0x20
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT 0x5
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK 0x40
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT 0x6
+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP_MASK 0x300
+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP__SHIFT 0x8
+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID_MASK 0xf000
+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID__SHIFT 0xc
+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV_MASK 0x10000
+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV__SHIFT 0x10
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE_MASK 0xf
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE__SHIFT 0x0
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT_MASK 0x70
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT__SHIFT 0x4
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH_MASK 0x300
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH__SHIFT 0x8
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT_MASK 0xc00
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT__SHIFT 0xa
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT_MASK 0x3000
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT__SHIFT 0xc
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS_MASK 0x300000
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS__SHIFT 0x14
+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE_MASK 0x7
+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE__SHIFT 0x0
+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE_MASK 0x700000
+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE__SHIFT 0x14
+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG_MASK 0xf8000000
+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG__SHIFT 0x1b
+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT_MASK 0x100
+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT__SHIFT 0x8
+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK_MASK 0x200
+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK__SHIFT 0x9
+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK_MASK 0x400
+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK__SHIFT 0xa
+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT_MASK 0x10000
+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT__SHIFT 0x10
+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK_MASK 0x20000
+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK__SHIFT 0x11
+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK_MASK 0x40000
+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK__SHIFT 0x12
+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT_MASK 0x100000
+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT__SHIFT 0x14
+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK_MASK 0x200000
+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK__SHIFT 0x15
+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK_MASK 0x400000
+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK__SHIFT 0x16
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY_MASK 0xf
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY__SHIFT 0x0
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY_MASK 0xff0
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS_MASK 0x8000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS__SHIFT 0xf
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS_MASK 0x10000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS__SHIFT 0x10
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0_MASK 0x20000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0__SHIFT 0x11
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1_MASK 0x40000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1__SHIFT 0x12
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2_MASK 0x80000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2__SHIFT 0x13
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3_MASK 0x100000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3__SHIFT 0x14
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4_MASK 0x200000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4__SHIFT 0x15
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5_MASK 0x400000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5__SHIFT 0x16
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS_MASK 0x800000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS__SHIFT 0x17
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS_MASK 0x1000000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS__SHIFT 0x18
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS_MASK 0x2000000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS__SHIFT 0x19
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_CORE_IDLE_STATE_MASK 0x3
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_CORE_IDLE_STATE__SHIFT 0x0
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_IDLE_STATE_MASK 0xc
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_IDLE_STATE__SHIFT 0x2
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_STATE_MASK 0x180000
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_STATE__SHIFT 0x13
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_TRANS_MASK 0x200000
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_TRANS__SHIFT 0x15
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_STATE_MASK 0xc00000
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_STATE__SHIFT 0x16
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_TRANS_MASK 0x2000000
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_TRANS__SHIFT 0x19
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_STATE_MASK 0xc000000
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_STATE__SHIFT 0x1a
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_TRANS_MASK 0x10000000
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_TRANS__SHIFT 0x1c
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_STATE_MASK 0x60000000
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_STATE__SHIFT 0x1d
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_TRANS_MASK 0x80000000
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_TRANS__SHIFT 0x1f
+#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS_MASK 0xf
+#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS__SHIFT 0x0
+#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR_MASK 0x100
+#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR__SHIFT 0x8
+#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS_MASK 0xff
+#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS__SHIFT 0x0
+#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY_MASK 0x1
+#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY__SHIFT 0x0
+#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX_MASK 0xff
+#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT 0x0
+#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA_MASK 0xffffffff
+#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA__SHIFT 0x0
+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY_MASK 0x7
+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY__SHIFT 0x0
+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS_MASK 0x8
+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT 0x3
+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY_MASK 0xffff8000
+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY__SHIFT 0xf
+#define XDMA_PG_CONTROL__XDMA_PG_CONTROL_MASK 0xffffffff
+#define XDMA_PG_CONTROL__XDMA_PG_CONTROL__SHIFT 0x0
+#define XDMA_PG_WDATA__XDMA_PG_WDATA_MASK 0xffffffff
+#define XDMA_PG_WDATA__XDMA_PG_WDATA__SHIFT 0x0
+#define XDMA_PG_STATUS__XDMA_SERDES_RDATA_MASK 0xffffff
+#define XDMA_PG_STATUS__XDMA_SERDES_RDATA__SHIFT 0x0
+#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY_MASK 0x1000000
+#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY__SHIFT 0x18
+#define XDMA_PG_STATUS__XDMA_SERDES_BUSY_MASK 0x2000000
+#define XDMA_PG_STATUS__XDMA_SERDES_BUSY__SHIFT 0x19
+#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS_MASK 0x4000000
+#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS__SHIFT 0x1a
+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX_MASK 0xff
+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX__SHIFT 0x0
+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL_MASK 0x200
+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL__SHIFT 0x9
+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_OUT_EN_MASK 0x400
+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_OUT_EN__SHIFT 0xa
+#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA_MASK 0xffffffff
+#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA__SHIFT 0x0
+#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION_MASK 0x3000
+#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION__SHIFT 0xc
+#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY_MASK 0x4000
+#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY__SHIFT 0xe
+#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE_MASK 0x10000
+#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE__SHIFT 0x10
+#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE_MASK 0x40000
+#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE__SHIFT 0x12
+#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET_MASK 0x100000
+#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET__SHIFT 0x14
+#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN_MASK 0x200000
+#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN__SHIFT 0x15
+#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT_MASK 0x3fff
+#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT__SHIFT 0x0
+#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT_MASK 0xfff0000
+#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT__SHIFT 0x10
+#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT_MASK 0x70000000
+#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT__SHIFT 0x1c
+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP_MASK 0x300
+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP__SHIFT 0x8
+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID_MASK 0xf000
+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID__SHIFT 0xc
+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV_MASK 0x10000
+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV__SHIFT 0x10
+#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_MASK 0xffffffff
+#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__SHIFT 0x0
+#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH_MASK 0xff
+#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__SHIFT 0x0
+#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH_MASK 0x3fff
+#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH__SHIFT 0x0
+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL_MASK 0x1
+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL__SHIFT 0x0
+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL_MASK 0xf00
+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL__SHIFT 0x8
+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY_MASK 0xf000
+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY__SHIFT 0xc
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL_MASK 0x1
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL__SHIFT 0x0
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT_MASK 0xf0
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT__SHIFT 0x4
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL_MASK 0xf00
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL__SHIFT 0x8
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY_MASK 0xf000
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY__SHIFT 0xc
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER_MASK 0xffff0000
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER__SHIFT 0x10
+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG_MASK 0x3ff
+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG__SHIFT 0x0
+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_MASK 0x3000
+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK__SHIFT 0xc
+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR_MASK 0x10000
+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR__SHIFT 0x10
+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG_MASK 0x3ff
+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG__SHIFT 0x0
+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_MASK 0x3000
+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK__SHIFT 0xc
+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR_MASK 0x10000
+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR__SHIFT 0x10
+#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL_MASK 0x7
+#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL__SHIFT 0x0
+#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT_MASK 0x3fff00
+#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT__SHIFT 0x8
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES_MASK 0xff
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES__SHIFT 0x0
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST_MASK 0x100
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST__SHIFT 0x8
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE_MASK 0x200
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE__SHIFT 0x9
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET_MASK 0x400
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET__SHIFT 0xa
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE_MASK 0x800
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE__SHIFT 0xb
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID_MASK 0x7000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID__SHIFT 0xc
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE_MASK 0x8000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE__SHIFT 0xf
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN_MASK 0xff0000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN__SHIFT 0x10
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE_MASK 0x1000000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE__SHIFT 0x18
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING_MASK 0x2000000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING__SHIFT 0x19
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING_MASK 0x4000000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING__SHIFT 0x1a
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE_MASK 0x8000000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE__SHIFT 0x1b
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_SUPERAA_ENABLE_MASK 0x10000000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_SUPERAA_ENABLE__SHIFT 0x1c
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_HSYNC_GSL_GROUP_MASK 0x60000000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_HSYNC_GSL_GROUP__SHIFT 0x1d
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_GSL_GROUP_MASTER_MASK 0x80000000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_GSL_GROUP_MASTER__SHIFT 0x1f
+#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE_MASK 0x3fff
+#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE__SHIFT 0x0
+#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH_MASK 0x3fff0000
+#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH__SHIFT 0x10
+#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH_MASK 0x3fff
+#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH__SHIFT 0x0
+#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT_MASK 0x3fff0000
+#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT__SHIFT 0x10
+#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT_MASK 0x3fff
+#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT__SHIFT 0x0
+#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT_MASK 0x3fff0000
+#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT__SHIFT 0x10
+#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE_MASK 0xffffffff
+#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE__SHIFT 0x0
+#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH_MASK 0xff
+#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__SHIFT 0x0
+#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS_MASK 0xffffffff
+#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS__SHIFT 0x0
+#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff
+#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0
+#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR_MASK 0xffffffff
+#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR__SHIFT 0x0
+#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH_MASK 0xff
+#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH__SHIFT 0x0
+#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_PITCH_MASK 0x3fff
+#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_PITCH__SHIFT 0x0
+#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_STATE_MASK 0x60000000
+#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_STATE__SHIFT 0x1d
+#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_TRANS_MASK 0x80000000
+#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_TRANS__SHIFT 0x1f
+#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X_MASK 0x3fff
+#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X__SHIFT 0x0
+#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y_MASK 0x3fff0000
+#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y__SHIFT 0x10
+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA_MASK 0xffffff
+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA__SHIFT 0x0
+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MASK 0x7000000
+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX__SHIFT 0x18
+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE_MASK 0xc0000000
+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE__SHIFT 0x1e
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER_MASK 0xfff
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER__SHIFT 0x0
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL_MASK 0x1f000
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL__SHIFT 0xc
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST_MASK 0x20000
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST__SHIFT 0x11
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER_MASK 0x7ff80000
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER__SHIFT 0x13
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST_MASK 0x80000000
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST__SHIFT 0x1f
+#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES_MASK 0x1
+#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES__SHIFT 0x0
+#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK 0x200
+#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY__SHIFT 0x9
+#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE_MASK 0x400
+#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE__SHIFT 0xa
+#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION_MASK 0x3000
+#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION__SHIFT 0xc
+#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE_MASK 0x10000
+#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE__SHIFT 0x10
+#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN_MASK 0x80000
+#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN__SHIFT 0x13
+#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET_MASK 0x100000
+#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET__SHIFT 0x14
+#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT_MASK 0x1000000
+#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT__SHIFT 0x18
+#define XDMA_SLV_CNTL__XDMA_SLV_WB_BURST_RESET_MASK 0x2000000
+#define XDMA_SLV_CNTL__XDMA_SLV_WB_BURST_RESET__SHIFT 0x19
+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP_MASK 0x300
+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP__SHIFT 0x8
+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID_MASK 0xf000
+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID__SHIFT 0xc
+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV_MASK 0x10000
+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV__SHIFT 0x10
+#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH_MASK 0x3fff
+#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH__SHIFT 0x0
+#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH_MASK 0x3fff0000
+#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH__SHIFT 0x10
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL_MASK 0x1
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL__SHIFT 0x0
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT_MASK 0xf0
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT__SHIFT 0x4
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL_MASK 0xf00
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL__SHIFT 0x8
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY_MASK 0xf000
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY__SHIFT 0xc
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER_MASK 0xffff0000
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER__SHIFT 0x10
+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_MASK 0x1
+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL__SHIFT 0x0
+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL_MASK 0xf00
+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL__SHIFT 0x8
+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY_MASK 0xf000
+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY__SHIFT 0xc
+#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE_MASK 0x1ff
+#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE__SHIFT 0x0
+#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD_MASK 0xffff0000
+#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD__SHIFT 0x10
+#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN_MASK 0xffff
+#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN__SHIFT 0x0
+#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX_MASK 0xffff0000
+#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX__SHIFT 0x10
+#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC_MASK 0xfffff
+#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC__SHIFT 0x0
+#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT_MASK 0xfff00000
+#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT__SHIFT 0x14
+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG_MASK 0x3ff
+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG__SHIFT 0x0
+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_MASK 0x3000
+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK__SHIFT 0xc
+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR_MASK 0x10000
+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR__SHIFT 0x10
+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG_MASK 0xffff
+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG__SHIFT 0x0
+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_MASK 0x30000
+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK__SHIFT 0x10
+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR_MASK 0x80000000
+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR__SHIFT 0x1f
+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES_MASK 0x3ff
+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES__SHIFT 0x0
+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE_MASK 0x3ff000
+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE__SHIFT 0xc
+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_STATE_MASK 0xc00000
+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_STATE__SHIFT 0x16
+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_TRANS_MASK 0x1000000
+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_TRANS__SHIFT 0x18
+#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER_MASK 0xffff
+#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER__SHIFT 0x0
+#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING_MASK 0x1
+#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING__SHIFT 0x0
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT_MASK 0x1ff
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT__SHIFT 0x0
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER_MASK 0x10000
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER__SHIFT 0x10
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET_MASK 0x20000
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET__SHIFT 0x11
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE_MASK 0x1000000
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE__SHIFT 0x18
+#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS_MASK 0xffffffff
+#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS__SHIFT 0x0
+#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff
+#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0
+
+#endif /* DCE_10_0_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h
new file mode 100644
index 000000000000..c39234ecedd0
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h
@@ -0,0 +1,7648 @@
+/*
+ * DCE_11_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef DCE_11_0_D_H
+#define DCE_11_0_D_H
+
+#define mmPIPE0_PG_CONFIG 0x2c0
+#define mmPIPE0_PG_ENABLE 0x2c1
+#define mmPIPE0_PG_STATUS 0x2c2
+#define mmPIPE1_PG_CONFIG 0x2c3
+#define mmPIPE1_PG_ENABLE 0x2c4
+#define mmPIPE1_PG_STATUS 0x2c5
+#define mmPIPE2_PG_CONFIG 0x2c6
+#define mmPIPE2_PG_ENABLE 0x2c7
+#define mmPIPE2_PG_STATUS 0x2c8
+#define mmDCFEV0_PG_CONFIG 0x2db
+#define mmDCFEV0_PG_ENABLE 0x2dc
+#define mmDCFEV0_PG_STATUS 0x2dd
+#define mmDCPG_INTERRUPT_STATUS 0x2de
+#define mmDCPG_INTERRUPT_CONTROL 0x2df
+#define mmDC_IP_REQUEST_CNTL 0x2d2
+#define mmDC_PGFSM_CONFIG_REG 0x2d3
+#define mmDC_PGFSM_WRITE_REG 0x2d4
+#define mmDC_PGCNTL_STATUS_REG 0x2d5
+#define mmDCPG_TEST_DEBUG_INDEX 0x2d6
+#define mmDCPG_TEST_DEBUG_DATA 0x2d7
+#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628
+#define mmBL1_PWM_USER_LEVEL 0x1629
+#define mmBL1_PWM_TARGET_ABM_LEVEL 0x162a
+#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x162b
+#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c
+#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162d
+#define mmBL1_PWM_ABM_CNTL 0x162e
+#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162f
+#define mmBL1_PWM_GRP2_REG_LOCK 0x1630
+#define mmDC_ABM1_CNTL 0x1638
+#define mmDC_ABM1_IPCSC_COEFF_SEL 0x1639
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163a
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163b
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163c
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163d
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163e
+#define mmDC_ABM1_ACE_THRES_12 0x163f
+#define mmDC_ABM1_ACE_THRES_34 0x1640
+#define mmDC_ABM1_ACE_CNTL_MISC 0x1641
+#define mmDC_ABM1_DEBUG_MISC 0x1649
+#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164a
+#define mmDC_ABM1_HG_MISC_CTRL 0x164b
+#define mmDC_ABM1_LS_SUM_OF_LUMA 0x164c
+#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x164d
+#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164e
+#define mmDC_ABM1_LS_PIXEL_COUNT 0x164f
+#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650
+#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651
+#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652
+#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653
+#define mmDC_ABM1_HG_SAMPLE_RATE 0x1654
+#define mmDC_ABM1_LS_SAMPLE_RATE 0x1655
+#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656
+#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657
+#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658
+#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659
+#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165a
+#define mmDC_ABM1_HG_RESULT_1 0x165b
+#define mmDC_ABM1_HG_RESULT_2 0x165c
+#define mmDC_ABM1_HG_RESULT_3 0x165d
+#define mmDC_ABM1_HG_RESULT_4 0x165e
+#define mmDC_ABM1_HG_RESULT_5 0x165f
+#define mmDC_ABM1_HG_RESULT_6 0x1660
+#define mmDC_ABM1_HG_RESULT_7 0x1661
+#define mmDC_ABM1_HG_RESULT_8 0x1662
+#define mmDC_ABM1_HG_RESULT_9 0x1663
+#define mmDC_ABM1_HG_RESULT_10 0x1664
+#define mmDC_ABM1_HG_RESULT_11 0x1665
+#define mmDC_ABM1_HG_RESULT_12 0x1666
+#define mmDC_ABM1_HG_RESULT_13 0x1667
+#define mmDC_ABM1_HG_RESULT_14 0x1668
+#define mmDC_ABM1_HG_RESULT_15 0x1669
+#define mmDC_ABM1_HG_RESULT_16 0x166a
+#define mmDC_ABM1_HG_RESULT_17 0x166b
+#define mmDC_ABM1_HG_RESULT_18 0x166c
+#define mmDC_ABM1_HG_RESULT_19 0x166d
+#define mmDC_ABM1_HG_RESULT_20 0x166e
+#define mmDC_ABM1_HG_RESULT_21 0x166f
+#define mmDC_ABM1_HG_RESULT_22 0x1670
+#define mmDC_ABM1_HG_RESULT_23 0x1671
+#define mmDC_ABM1_HG_RESULT_24 0x1672
+#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169b
+#define mmDC_ABM1_BL_MASTER_LOCK 0x169c
+#define mmABM_TEST_DEBUG_INDEX 0x169e
+#define mmABM_TEST_DEBUG_DATA 0x169f
+#define mmCRTC_H_BLANK_EARLY_NUM 0x1b7d
+#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1b7d
+#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1d7d
+#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x1f7d
+#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x417d
+#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x437d
+#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x457d
+#define mmCRTC_H_TOTAL 0x1b80
+#define mmCRTC0_CRTC_H_TOTAL 0x1b80
+#define mmCRTC1_CRTC_H_TOTAL 0x1d80
+#define mmCRTC2_CRTC_H_TOTAL 0x1f80
+#define mmCRTC3_CRTC_H_TOTAL 0x4180
+#define mmCRTC4_CRTC_H_TOTAL 0x4380
+#define mmCRTC5_CRTC_H_TOTAL 0x4580
+#define mmCRTC_H_BLANK_START_END 0x1b81
+#define mmCRTC0_CRTC_H_BLANK_START_END 0x1b81
+#define mmCRTC1_CRTC_H_BLANK_START_END 0x1d81
+#define mmCRTC2_CRTC_H_BLANK_START_END 0x1f81
+#define mmCRTC3_CRTC_H_BLANK_START_END 0x4181
+#define mmCRTC4_CRTC_H_BLANK_START_END 0x4381
+#define mmCRTC5_CRTC_H_BLANK_START_END 0x4581
+#define mmCRTC_H_SYNC_A 0x1b82
+#define mmCRTC0_CRTC_H_SYNC_A 0x1b82
+#define mmCRTC1_CRTC_H_SYNC_A 0x1d82
+#define mmCRTC2_CRTC_H_SYNC_A 0x1f82
+#define mmCRTC3_CRTC_H_SYNC_A 0x4182
+#define mmCRTC4_CRTC_H_SYNC_A 0x4382
+#define mmCRTC5_CRTC_H_SYNC_A 0x4582
+#define mmCRTC_H_SYNC_A_CNTL 0x1b83
+#define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1b83
+#define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1d83
+#define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x1f83
+#define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4183
+#define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4383
+#define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4583
+#define mmCRTC_H_SYNC_B 0x1b84
+#define mmCRTC0_CRTC_H_SYNC_B 0x1b84
+#define mmCRTC1_CRTC_H_SYNC_B 0x1d84
+#define mmCRTC2_CRTC_H_SYNC_B 0x1f84
+#define mmCRTC3_CRTC_H_SYNC_B 0x4184
+#define mmCRTC4_CRTC_H_SYNC_B 0x4384
+#define mmCRTC5_CRTC_H_SYNC_B 0x4584
+#define mmCRTC_H_SYNC_B_CNTL 0x1b85
+#define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1b85
+#define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1d85
+#define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x1f85
+#define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4185
+#define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4385
+#define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4585
+#define mmCRTC_VBI_END 0x1b86
+#define mmCRTC0_CRTC_VBI_END 0x1b86
+#define mmCRTC1_CRTC_VBI_END 0x1d86
+#define mmCRTC2_CRTC_VBI_END 0x1f86
+#define mmCRTC3_CRTC_VBI_END 0x4186
+#define mmCRTC4_CRTC_VBI_END 0x4386
+#define mmCRTC5_CRTC_VBI_END 0x4586
+#define mmCRTC_V_TOTAL 0x1b87
+#define mmCRTC0_CRTC_V_TOTAL 0x1b87
+#define mmCRTC1_CRTC_V_TOTAL 0x1d87
+#define mmCRTC2_CRTC_V_TOTAL 0x1f87
+#define mmCRTC3_CRTC_V_TOTAL 0x4187
+#define mmCRTC4_CRTC_V_TOTAL 0x4387
+#define mmCRTC5_CRTC_V_TOTAL 0x4587
+#define mmCRTC_V_TOTAL_MIN 0x1b88
+#define mmCRTC0_CRTC_V_TOTAL_MIN 0x1b88
+#define mmCRTC1_CRTC_V_TOTAL_MIN 0x1d88
+#define mmCRTC2_CRTC_V_TOTAL_MIN 0x1f88
+#define mmCRTC3_CRTC_V_TOTAL_MIN 0x4188
+#define mmCRTC4_CRTC_V_TOTAL_MIN 0x4388
+#define mmCRTC5_CRTC_V_TOTAL_MIN 0x4588
+#define mmCRTC_V_TOTAL_MAX 0x1b89
+#define mmCRTC0_CRTC_V_TOTAL_MAX 0x1b89
+#define mmCRTC1_CRTC_V_TOTAL_MAX 0x1d89
+#define mmCRTC2_CRTC_V_TOTAL_MAX 0x1f89
+#define mmCRTC3_CRTC_V_TOTAL_MAX 0x4189
+#define mmCRTC4_CRTC_V_TOTAL_MAX 0x4389
+#define mmCRTC5_CRTC_V_TOTAL_MAX 0x4589
+#define mmCRTC_V_TOTAL_CONTROL 0x1b8a
+#define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1b8a
+#define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1d8a
+#define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x1f8a
+#define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x418a
+#define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x438a
+#define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x458a
+#define mmCRTC_V_TOTAL_INT_STATUS 0x1b8b
+#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1b8b
+#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1d8b
+#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x1f8b
+#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x418b
+#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x438b
+#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x458b
+#define mmCRTC_VSYNC_NOM_INT_STATUS 0x1b8c
+#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1b8c
+#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1d8c
+#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x1f8c
+#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x418c
+#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x438c
+#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x458c
+#define mmCRTC_V_BLANK_START_END 0x1b8d
+#define mmCRTC0_CRTC_V_BLANK_START_END 0x1b8d
+#define mmCRTC1_CRTC_V_BLANK_START_END 0x1d8d
+#define mmCRTC2_CRTC_V_BLANK_START_END 0x1f8d
+#define mmCRTC3_CRTC_V_BLANK_START_END 0x418d
+#define mmCRTC4_CRTC_V_BLANK_START_END 0x438d
+#define mmCRTC5_CRTC_V_BLANK_START_END 0x458d
+#define mmCRTC_V_SYNC_A 0x1b8e
+#define mmCRTC0_CRTC_V_SYNC_A 0x1b8e
+#define mmCRTC1_CRTC_V_SYNC_A 0x1d8e
+#define mmCRTC2_CRTC_V_SYNC_A 0x1f8e
+#define mmCRTC3_CRTC_V_SYNC_A 0x418e
+#define mmCRTC4_CRTC_V_SYNC_A 0x438e
+#define mmCRTC5_CRTC_V_SYNC_A 0x458e
+#define mmCRTC_V_SYNC_A_CNTL 0x1b8f
+#define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1b8f
+#define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1d8f
+#define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x1f8f
+#define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x418f
+#define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x438f
+#define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x458f
+#define mmCRTC_V_SYNC_B 0x1b90
+#define mmCRTC0_CRTC_V_SYNC_B 0x1b90
+#define mmCRTC1_CRTC_V_SYNC_B 0x1d90
+#define mmCRTC2_CRTC_V_SYNC_B 0x1f90
+#define mmCRTC3_CRTC_V_SYNC_B 0x4190
+#define mmCRTC4_CRTC_V_SYNC_B 0x4390
+#define mmCRTC5_CRTC_V_SYNC_B 0x4590
+#define mmCRTC_V_SYNC_B_CNTL 0x1b91
+#define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1b91
+#define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1d91
+#define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x1f91
+#define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4191
+#define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4391
+#define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4591
+#define mmCRTC_DTMTEST_CNTL 0x1b92
+#define mmCRTC0_CRTC_DTMTEST_CNTL 0x1b92
+#define mmCRTC1_CRTC_DTMTEST_CNTL 0x1d92
+#define mmCRTC2_CRTC_DTMTEST_CNTL 0x1f92
+#define mmCRTC3_CRTC_DTMTEST_CNTL 0x4192
+#define mmCRTC4_CRTC_DTMTEST_CNTL 0x4392
+#define mmCRTC5_CRTC_DTMTEST_CNTL 0x4592
+#define mmCRTC_DTMTEST_STATUS_POSITION 0x1b93
+#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1b93
+#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1d93
+#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x1f93
+#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4193
+#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4393
+#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4593
+#define mmCRTC_TRIGA_CNTL 0x1b94
+#define mmCRTC0_CRTC_TRIGA_CNTL 0x1b94
+#define mmCRTC1_CRTC_TRIGA_CNTL 0x1d94
+#define mmCRTC2_CRTC_TRIGA_CNTL 0x1f94
+#define mmCRTC3_CRTC_TRIGA_CNTL 0x4194
+#define mmCRTC4_CRTC_TRIGA_CNTL 0x4394
+#define mmCRTC5_CRTC_TRIGA_CNTL 0x4594
+#define mmCRTC_TRIGA_MANUAL_TRIG 0x1b95
+#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1b95
+#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1d95
+#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x1f95
+#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4195
+#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4395
+#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4595
+#define mmCRTC_TRIGB_CNTL 0x1b96
+#define mmCRTC0_CRTC_TRIGB_CNTL 0x1b96
+#define mmCRTC1_CRTC_TRIGB_CNTL 0x1d96
+#define mmCRTC2_CRTC_TRIGB_CNTL 0x1f96
+#define mmCRTC3_CRTC_TRIGB_CNTL 0x4196
+#define mmCRTC4_CRTC_TRIGB_CNTL 0x4396
+#define mmCRTC5_CRTC_TRIGB_CNTL 0x4596
+#define mmCRTC_TRIGB_MANUAL_TRIG 0x1b97
+#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1b97
+#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1d97
+#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x1f97
+#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4197
+#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4397
+#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4597
+#define mmCRTC_FORCE_COUNT_NOW_CNTL 0x1b98
+#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1b98
+#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1d98
+#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x1f98
+#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4198
+#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4398
+#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4598
+#define mmCRTC_FLOW_CONTROL 0x1b99
+#define mmCRTC0_CRTC_FLOW_CONTROL 0x1b99
+#define mmCRTC1_CRTC_FLOW_CONTROL 0x1d99
+#define mmCRTC2_CRTC_FLOW_CONTROL 0x1f99
+#define mmCRTC3_CRTC_FLOW_CONTROL 0x4199
+#define mmCRTC4_CRTC_FLOW_CONTROL 0x4399
+#define mmCRTC5_CRTC_FLOW_CONTROL 0x4599
+#define mmCRTC_STEREO_FORCE_NEXT_EYE 0x1b9a
+#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1b9a
+#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1d9a
+#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x1f9a
+#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x419a
+#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x439a
+#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x459a
+#define mmCRTC_AVSYNC_COUNTER 0x1b9b
+#define mmCRTC0_CRTC_AVSYNC_COUNTER 0x1b9b
+#define mmCRTC1_CRTC_AVSYNC_COUNTER 0x1d9b
+#define mmCRTC2_CRTC_AVSYNC_COUNTER 0x1f9b
+#define mmCRTC3_CRTC_AVSYNC_COUNTER 0x419b
+#define mmCRTC4_CRTC_AVSYNC_COUNTER 0x439b
+#define mmCRTC5_CRTC_AVSYNC_COUNTER 0x459b
+#define mmCRTC_CONTROL 0x1b9c
+#define mmCRTC0_CRTC_CONTROL 0x1b9c
+#define mmCRTC1_CRTC_CONTROL 0x1d9c
+#define mmCRTC2_CRTC_CONTROL 0x1f9c
+#define mmCRTC3_CRTC_CONTROL 0x419c
+#define mmCRTC4_CRTC_CONTROL 0x439c
+#define mmCRTC5_CRTC_CONTROL 0x459c
+#define mmCRTC_BLANK_CONTROL 0x1b9d
+#define mmCRTC0_CRTC_BLANK_CONTROL 0x1b9d
+#define mmCRTC1_CRTC_BLANK_CONTROL 0x1d9d
+#define mmCRTC2_CRTC_BLANK_CONTROL 0x1f9d
+#define mmCRTC3_CRTC_BLANK_CONTROL 0x419d
+#define mmCRTC4_CRTC_BLANK_CONTROL 0x439d
+#define mmCRTC5_CRTC_BLANK_CONTROL 0x459d
+#define mmCRTC_INTERLACE_CONTROL 0x1b9e
+#define mmCRTC0_CRTC_INTERLACE_CONTROL 0x1b9e
+#define mmCRTC1_CRTC_INTERLACE_CONTROL 0x1d9e
+#define mmCRTC2_CRTC_INTERLACE_CONTROL 0x1f9e
+#define mmCRTC3_CRTC_INTERLACE_CONTROL 0x419e
+#define mmCRTC4_CRTC_INTERLACE_CONTROL 0x439e
+#define mmCRTC5_CRTC_INTERLACE_CONTROL 0x459e
+#define mmCRTC_INTERLACE_STATUS 0x1b9f
+#define mmCRTC0_CRTC_INTERLACE_STATUS 0x1b9f
+#define mmCRTC1_CRTC_INTERLACE_STATUS 0x1d9f
+#define mmCRTC2_CRTC_INTERLACE_STATUS 0x1f9f
+#define mmCRTC3_CRTC_INTERLACE_STATUS 0x419f
+#define mmCRTC4_CRTC_INTERLACE_STATUS 0x439f
+#define mmCRTC5_CRTC_INTERLACE_STATUS 0x459f
+#define mmCRTC_FIELD_INDICATION_CONTROL 0x1ba0
+#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x1ba0
+#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x1da0
+#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x1fa0
+#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x41a0
+#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x43a0
+#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x45a0
+#define mmCRTC_PIXEL_DATA_READBACK0 0x1ba1
+#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x1ba1
+#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x1da1
+#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x1fa1
+#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x41a1
+#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x43a1
+#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x45a1
+#define mmCRTC_PIXEL_DATA_READBACK1 0x1ba2
+#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x1ba2
+#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x1da2
+#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x1fa2
+#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x41a2
+#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x43a2
+#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x45a2
+#define mmCRTC_STATUS 0x1ba3
+#define mmCRTC0_CRTC_STATUS 0x1ba3
+#define mmCRTC1_CRTC_STATUS 0x1da3
+#define mmCRTC2_CRTC_STATUS 0x1fa3
+#define mmCRTC3_CRTC_STATUS 0x41a3
+#define mmCRTC4_CRTC_STATUS 0x43a3
+#define mmCRTC5_CRTC_STATUS 0x45a3
+#define mmCRTC_STATUS_POSITION 0x1ba4
+#define mmCRTC0_CRTC_STATUS_POSITION 0x1ba4
+#define mmCRTC1_CRTC_STATUS_POSITION 0x1da4
+#define mmCRTC2_CRTC_STATUS_POSITION 0x1fa4
+#define mmCRTC3_CRTC_STATUS_POSITION 0x41a4
+#define mmCRTC4_CRTC_STATUS_POSITION 0x43a4
+#define mmCRTC5_CRTC_STATUS_POSITION 0x45a4
+#define mmCRTC_NOM_VERT_POSITION 0x1ba5
+#define mmCRTC0_CRTC_NOM_VERT_POSITION 0x1ba5
+#define mmCRTC1_CRTC_NOM_VERT_POSITION 0x1da5
+#define mmCRTC2_CRTC_NOM_VERT_POSITION 0x1fa5
+#define mmCRTC3_CRTC_NOM_VERT_POSITION 0x41a5
+#define mmCRTC4_CRTC_NOM_VERT_POSITION 0x43a5
+#define mmCRTC5_CRTC_NOM_VERT_POSITION 0x45a5
+#define mmCRTC_STATUS_FRAME_COUNT 0x1ba6
+#define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1ba6
+#define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1da6
+#define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x1fa6
+#define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x41a6
+#define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x43a6
+#define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x45a6
+#define mmCRTC_STATUS_VF_COUNT 0x1ba7
+#define mmCRTC0_CRTC_STATUS_VF_COUNT 0x1ba7
+#define mmCRTC1_CRTC_STATUS_VF_COUNT 0x1da7
+#define mmCRTC2_CRTC_STATUS_VF_COUNT 0x1fa7
+#define mmCRTC3_CRTC_STATUS_VF_COUNT 0x41a7
+#define mmCRTC4_CRTC_STATUS_VF_COUNT 0x43a7
+#define mmCRTC5_CRTC_STATUS_VF_COUNT 0x45a7
+#define mmCRTC_STATUS_HV_COUNT 0x1ba8
+#define mmCRTC0_CRTC_STATUS_HV_COUNT 0x1ba8
+#define mmCRTC1_CRTC_STATUS_HV_COUNT 0x1da8
+#define mmCRTC2_CRTC_STATUS_HV_COUNT 0x1fa8
+#define mmCRTC3_CRTC_STATUS_HV_COUNT 0x41a8
+#define mmCRTC4_CRTC_STATUS_HV_COUNT 0x43a8
+#define mmCRTC5_CRTC_STATUS_HV_COUNT 0x45a8
+#define mmCRTC_COUNT_CONTROL 0x1ba9
+#define mmCRTC0_CRTC_COUNT_CONTROL 0x1ba9
+#define mmCRTC1_CRTC_COUNT_CONTROL 0x1da9
+#define mmCRTC2_CRTC_COUNT_CONTROL 0x1fa9
+#define mmCRTC3_CRTC_COUNT_CONTROL 0x41a9
+#define mmCRTC4_CRTC_COUNT_CONTROL 0x43a9
+#define mmCRTC5_CRTC_COUNT_CONTROL 0x45a9
+#define mmCRTC_COUNT_RESET 0x1baa
+#define mmCRTC0_CRTC_COUNT_RESET 0x1baa
+#define mmCRTC1_CRTC_COUNT_RESET 0x1daa
+#define mmCRTC2_CRTC_COUNT_RESET 0x1faa
+#define mmCRTC3_CRTC_COUNT_RESET 0x41aa
+#define mmCRTC4_CRTC_COUNT_RESET 0x43aa
+#define mmCRTC5_CRTC_COUNT_RESET 0x45aa
+#define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab
+#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab
+#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dab
+#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1fab
+#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41ab
+#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x43ab
+#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x45ab
+#define mmCRTC_VERT_SYNC_CONTROL 0x1bac
+#define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1bac
+#define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1dac
+#define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x1fac
+#define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x41ac
+#define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x43ac
+#define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x45ac
+#define mmCRTC_STEREO_STATUS 0x1bad
+#define mmCRTC0_CRTC_STEREO_STATUS 0x1bad
+#define mmCRTC1_CRTC_STEREO_STATUS 0x1dad
+#define mmCRTC2_CRTC_STEREO_STATUS 0x1fad
+#define mmCRTC3_CRTC_STEREO_STATUS 0x41ad
+#define mmCRTC4_CRTC_STEREO_STATUS 0x43ad
+#define mmCRTC5_CRTC_STEREO_STATUS 0x45ad
+#define mmCRTC_STEREO_CONTROL 0x1bae
+#define mmCRTC0_CRTC_STEREO_CONTROL 0x1bae
+#define mmCRTC1_CRTC_STEREO_CONTROL 0x1dae
+#define mmCRTC2_CRTC_STEREO_CONTROL 0x1fae
+#define mmCRTC3_CRTC_STEREO_CONTROL 0x41ae
+#define mmCRTC4_CRTC_STEREO_CONTROL 0x43ae
+#define mmCRTC5_CRTC_STEREO_CONTROL 0x45ae
+#define mmCRTC_SNAPSHOT_STATUS 0x1baf
+#define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1baf
+#define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1daf
+#define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x1faf
+#define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x41af
+#define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x43af
+#define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x45af
+#define mmCRTC_SNAPSHOT_CONTROL 0x1bb0
+#define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1bb0
+#define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1db0
+#define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x1fb0
+#define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x41b0
+#define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x43b0
+#define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x45b0
+#define mmCRTC_SNAPSHOT_POSITION 0x1bb1
+#define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1bb1
+#define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1db1
+#define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x1fb1
+#define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x41b1
+#define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x43b1
+#define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x45b1
+#define mmCRTC_SNAPSHOT_FRAME 0x1bb2
+#define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1bb2
+#define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1db2
+#define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x1fb2
+#define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x41b2
+#define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x43b2
+#define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x45b2
+#define mmCRTC_START_LINE_CONTROL 0x1bb3
+#define mmCRTC0_CRTC_START_LINE_CONTROL 0x1bb3
+#define mmCRTC1_CRTC_START_LINE_CONTROL 0x1db3
+#define mmCRTC2_CRTC_START_LINE_CONTROL 0x1fb3
+#define mmCRTC3_CRTC_START_LINE_CONTROL 0x41b3
+#define mmCRTC4_CRTC_START_LINE_CONTROL 0x43b3
+#define mmCRTC5_CRTC_START_LINE_CONTROL 0x45b3
+#define mmCRTC_INTERRUPT_CONTROL 0x1bb4
+#define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1bb4
+#define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1db4
+#define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x1fb4
+#define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x41b4
+#define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x43b4
+#define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x45b4
+#define mmCRTC_UPDATE_LOCK 0x1bb5
+#define mmCRTC0_CRTC_UPDATE_LOCK 0x1bb5
+#define mmCRTC1_CRTC_UPDATE_LOCK 0x1db5
+#define mmCRTC2_CRTC_UPDATE_LOCK 0x1fb5
+#define mmCRTC3_CRTC_UPDATE_LOCK 0x41b5
+#define mmCRTC4_CRTC_UPDATE_LOCK 0x43b5
+#define mmCRTC5_CRTC_UPDATE_LOCK 0x45b5
+#define mmCRTC_DOUBLE_BUFFER_CONTROL 0x1bb6
+#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1bb6
+#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1db6
+#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x1fb6
+#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x41b6
+#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x43b6
+#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x45b6
+#define mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7
+#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7
+#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1db7
+#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1fb7
+#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41b7
+#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x43b7
+#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x45b7
+#define mmCRTC_TEST_PATTERN_CONTROL 0x1bba
+#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba
+#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1dba
+#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x1fba
+#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x41ba
+#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x43ba
+#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x45ba
+#define mmCRTC_TEST_PATTERN_PARAMETERS 0x1bbb
+#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1bbb
+#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1dbb
+#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x1fbb
+#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x41bb
+#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x43bb
+#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x45bb
+#define mmCRTC_TEST_PATTERN_COLOR 0x1bbc
+#define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1bbc
+#define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1dbc
+#define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x1fbc
+#define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x41bc
+#define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x43bc
+#define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x45bc
+#define mmCRTC_MASTER_UPDATE_LOCK 0x1bbd
+#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK 0x1bbd
+#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK 0x1dbd
+#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK 0x1fbd
+#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK 0x41bd
+#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK 0x43bd
+#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK 0x45bd
+#define mmCRTC_MASTER_UPDATE_MODE 0x1bbe
+#define mmCRTC0_CRTC_MASTER_UPDATE_MODE 0x1bbe
+#define mmCRTC1_CRTC_MASTER_UPDATE_MODE 0x1dbe
+#define mmCRTC2_CRTC_MASTER_UPDATE_MODE 0x1fbe
+#define mmCRTC3_CRTC_MASTER_UPDATE_MODE 0x41be
+#define mmCRTC4_CRTC_MASTER_UPDATE_MODE 0x43be
+#define mmCRTC5_CRTC_MASTER_UPDATE_MODE 0x45be
+#define mmCRTC_MVP_INBAND_CNTL_INSERT 0x1bbf
+#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1bbf
+#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1dbf
+#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x1fbf
+#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x41bf
+#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x43bf
+#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x45bf
+#define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0
+#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0
+#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1dc0
+#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1fc0
+#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41c0
+#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x43c0
+#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x45c0
+#define mmCRTC_MVP_STATUS 0x1bc1
+#define mmCRTC0_CRTC_MVP_STATUS 0x1bc1
+#define mmCRTC1_CRTC_MVP_STATUS 0x1dc1
+#define mmCRTC2_CRTC_MVP_STATUS 0x1fc1
+#define mmCRTC3_CRTC_MVP_STATUS 0x41c1
+#define mmCRTC4_CRTC_MVP_STATUS 0x43c1
+#define mmCRTC5_CRTC_MVP_STATUS 0x45c1
+#define mmCRTC_MASTER_EN 0x1bc2
+#define mmCRTC0_CRTC_MASTER_EN 0x1bc2
+#define mmCRTC1_CRTC_MASTER_EN 0x1dc2
+#define mmCRTC2_CRTC_MASTER_EN 0x1fc2
+#define mmCRTC3_CRTC_MASTER_EN 0x41c2
+#define mmCRTC4_CRTC_MASTER_EN 0x43c2
+#define mmCRTC5_CRTC_MASTER_EN 0x45c2
+#define mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3
+#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3
+#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1dc3
+#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x1fc3
+#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x41c3
+#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x43c3
+#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x45c3
+#define mmCRTC_V_UPDATE_INT_STATUS 0x1bc4
+#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1bc4
+#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1dc4
+#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x1fc4
+#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x41c4
+#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x43c4
+#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x45c4
+#define mmCRTC_OVERSCAN_COLOR 0x1bc8
+#define mmCRTC0_CRTC_OVERSCAN_COLOR 0x1bc8
+#define mmCRTC1_CRTC_OVERSCAN_COLOR 0x1dc8
+#define mmCRTC2_CRTC_OVERSCAN_COLOR 0x1fc8
+#define mmCRTC3_CRTC_OVERSCAN_COLOR 0x41c8
+#define mmCRTC4_CRTC_OVERSCAN_COLOR 0x43c8
+#define mmCRTC5_CRTC_OVERSCAN_COLOR 0x45c8
+#define mmCRTC_OVERSCAN_COLOR_EXT 0x1bc9
+#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x1bc9
+#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x1dc9
+#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x1fc9
+#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x41c9
+#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x43c9
+#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x45c9
+#define mmCRTC_BLANK_DATA_COLOR 0x1bca
+#define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1bca
+#define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1dca
+#define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x1fca
+#define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x41ca
+#define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x43ca
+#define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x45ca
+#define mmCRTC_BLANK_DATA_COLOR_EXT 0x1bcb
+#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x1bcb
+#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x1dcb
+#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x1fcb
+#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x41cb
+#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x43cb
+#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x45cb
+#define mmCRTC_BLACK_COLOR 0x1bcc
+#define mmCRTC0_CRTC_BLACK_COLOR 0x1bcc
+#define mmCRTC1_CRTC_BLACK_COLOR 0x1dcc
+#define mmCRTC2_CRTC_BLACK_COLOR 0x1fcc
+#define mmCRTC3_CRTC_BLACK_COLOR 0x41cc
+#define mmCRTC4_CRTC_BLACK_COLOR 0x43cc
+#define mmCRTC5_CRTC_BLACK_COLOR 0x45cc
+#define mmCRTC_BLACK_COLOR_EXT 0x1bcd
+#define mmCRTC0_CRTC_BLACK_COLOR_EXT 0x1bcd
+#define mmCRTC1_CRTC_BLACK_COLOR_EXT 0x1dcd
+#define mmCRTC2_CRTC_BLACK_COLOR_EXT 0x1fcd
+#define mmCRTC3_CRTC_BLACK_COLOR_EXT 0x41cd
+#define mmCRTC4_CRTC_BLACK_COLOR_EXT 0x43cd
+#define mmCRTC5_CRTC_BLACK_COLOR_EXT 0x45cd
+#define mmCRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1dce
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1fce
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x41ce
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x43ce
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x45ce
+#define mmCRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1dcf
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1fcf
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x41cf
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x43cf
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x45cf
+#define mmCRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1dd0
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1fd0
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x41d0
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x43d0
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x45d0
+#define mmCRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1dd1
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1fd1
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x41d1
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x43d1
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x45d1
+#define mmCRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1dd2
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1fd2
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x41d2
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x43d2
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x45d2
+#define mmCRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1dd3
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1fd3
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x41d3
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x43d3
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x45d3
+#define mmCRTC_CRC_CNTL 0x1bd4
+#define mmCRTC0_CRTC_CRC_CNTL 0x1bd4
+#define mmCRTC1_CRTC_CRC_CNTL 0x1dd4
+#define mmCRTC2_CRTC_CRC_CNTL 0x1fd4
+#define mmCRTC3_CRTC_CRC_CNTL 0x41d4
+#define mmCRTC4_CRTC_CRC_CNTL 0x43d4
+#define mmCRTC5_CRTC_CRC_CNTL 0x45d4
+#define mmCRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5
+#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5
+#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x1dd5
+#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x1fd5
+#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x41d5
+#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x43d5
+#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x45d5
+#define mmCRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6
+#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6
+#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1dd6
+#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1fd6
+#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x41d6
+#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x43d6
+#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x45d6
+#define mmCRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7
+#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7
+#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x1dd7
+#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x1fd7
+#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x41d7
+#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x43d7
+#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x45d7
+#define mmCRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8
+#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8
+#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1dd8
+#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1fd8
+#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x41d8
+#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x43d8
+#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x45d8
+#define mmCRTC_CRC0_DATA_RG 0x1bd9
+#define mmCRTC0_CRTC_CRC0_DATA_RG 0x1bd9
+#define mmCRTC1_CRTC_CRC0_DATA_RG 0x1dd9
+#define mmCRTC2_CRTC_CRC0_DATA_RG 0x1fd9
+#define mmCRTC3_CRTC_CRC0_DATA_RG 0x41d9
+#define mmCRTC4_CRTC_CRC0_DATA_RG 0x43d9
+#define mmCRTC5_CRTC_CRC0_DATA_RG 0x45d9
+#define mmCRTC_CRC0_DATA_B 0x1bda
+#define mmCRTC0_CRTC_CRC0_DATA_B 0x1bda
+#define mmCRTC1_CRTC_CRC0_DATA_B 0x1dda
+#define mmCRTC2_CRTC_CRC0_DATA_B 0x1fda
+#define mmCRTC3_CRTC_CRC0_DATA_B 0x41da
+#define mmCRTC4_CRTC_CRC0_DATA_B 0x43da
+#define mmCRTC5_CRTC_CRC0_DATA_B 0x45da
+#define mmCRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb
+#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb
+#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x1ddb
+#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x1fdb
+#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x41db
+#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x43db
+#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x45db
+#define mmCRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc
+#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc
+#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1ddc
+#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1fdc
+#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x41dc
+#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x43dc
+#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x45dc
+#define mmCRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd
+#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd
+#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x1ddd
+#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x1fdd
+#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x41dd
+#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x43dd
+#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x45dd
+#define mmCRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde
+#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde
+#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1dde
+#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1fde
+#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x41de
+#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x43de
+#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x45de
+#define mmCRTC_CRC1_DATA_RG 0x1bdf
+#define mmCRTC0_CRTC_CRC1_DATA_RG 0x1bdf
+#define mmCRTC1_CRTC_CRC1_DATA_RG 0x1ddf
+#define mmCRTC2_CRTC_CRC1_DATA_RG 0x1fdf
+#define mmCRTC3_CRTC_CRC1_DATA_RG 0x41df
+#define mmCRTC4_CRTC_CRC1_DATA_RG 0x43df
+#define mmCRTC5_CRTC_CRC1_DATA_RG 0x45df
+#define mmCRTC_CRC1_DATA_B 0x1be0
+#define mmCRTC0_CRTC_CRC1_DATA_B 0x1be0
+#define mmCRTC1_CRTC_CRC1_DATA_B 0x1de0
+#define mmCRTC2_CRTC_CRC1_DATA_B 0x1fe0
+#define mmCRTC3_CRTC_CRC1_DATA_B 0x41e0
+#define mmCRTC4_CRTC_CRC1_DATA_B 0x43e0
+#define mmCRTC5_CRTC_CRC1_DATA_B 0x45e0
+#define mmCRTC_STATIC_SCREEN_CONTROL 0x1be7
+#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x1be7
+#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x1de7
+#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x1fe7
+#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x41e7
+#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x43e7
+#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x45e7
+#define mmCRTC_3D_STRUCTURE_CONTROL 0x1b78
+#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1b78
+#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1d78
+#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x1f78
+#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4178
+#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4378
+#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4578
+#define mmCRTC_GSL_VSYNC_GAP 0x1b79
+#define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1b79
+#define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1d79
+#define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x1f79
+#define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4179
+#define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4379
+#define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4579
+#define mmCRTC_GSL_WINDOW 0x1b7a
+#define mmCRTC0_CRTC_GSL_WINDOW 0x1b7a
+#define mmCRTC1_CRTC_GSL_WINDOW 0x1d7a
+#define mmCRTC2_CRTC_GSL_WINDOW 0x1f7a
+#define mmCRTC3_CRTC_GSL_WINDOW 0x417a
+#define mmCRTC4_CRTC_GSL_WINDOW 0x437a
+#define mmCRTC5_CRTC_GSL_WINDOW 0x457a
+#define mmCRTC_GSL_CONTROL 0x1b7b
+#define mmCRTC0_CRTC_GSL_CONTROL 0x1b7b
+#define mmCRTC1_CRTC_GSL_CONTROL 0x1d7b
+#define mmCRTC2_CRTC_GSL_CONTROL 0x1f7b
+#define mmCRTC3_CRTC_GSL_CONTROL 0x417b
+#define mmCRTC4_CRTC_GSL_CONTROL 0x437b
+#define mmCRTC5_CRTC_GSL_CONTROL 0x457b
+#define mmCRTC_TEST_DEBUG_INDEX 0x1bc6
+#define mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1bc6
+#define mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1dc6
+#define mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x1fc6
+#define mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x41c6
+#define mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x43c6
+#define mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x45c6
+#define mmCRTC_TEST_DEBUG_DATA 0x1bc7
+#define mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1bc7
+#define mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1dc7
+#define mmCRTC2_CRTC_TEST_DEBUG_DATA 0x1fc7
+#define mmCRTC3_CRTC_TEST_DEBUG_DATA 0x41c7
+#define mmCRTC4_CRTC_TEST_DEBUG_DATA 0x43c7
+#define mmCRTC5_CRTC_TEST_DEBUG_DATA 0x45c7
+#define mmDAC_ENABLE 0x16aa
+#define mmDAC_SOURCE_SELECT 0x16ab
+#define mmDAC_CRC_EN 0x16ac
+#define mmDAC_CRC_CONTROL 0x16ad
+#define mmDAC_CRC_SIG_RGB_MASK 0x16ae
+#define mmDAC_CRC_SIG_CONTROL_MASK 0x16af
+#define mmDAC_CRC_SIG_RGB 0x16b0
+#define mmDAC_CRC_SIG_CONTROL 0x16b1
+#define mmDAC_SYNC_TRISTATE_CONTROL 0x16b2
+#define mmDAC_STEREOSYNC_SELECT 0x16b3
+#define mmDAC_AUTODETECT_CONTROL 0x16b4
+#define mmDAC_AUTODETECT_CONTROL2 0x16b5
+#define mmDAC_AUTODETECT_CONTROL3 0x16b6
+#define mmDAC_AUTODETECT_STATUS 0x16b7
+#define mmDAC_AUTODETECT_INT_CONTROL 0x16b8
+#define mmDAC_FORCE_OUTPUT_CNTL 0x16b9
+#define mmDAC_FORCE_DATA 0x16ba
+#define mmDAC_POWERDOWN 0x16bb
+#define mmDAC_CONTROL 0x16bc
+#define mmDAC_COMPARATOR_ENABLE 0x16bd
+#define mmDAC_COMPARATOR_OUTPUT 0x16be
+#define mmDAC_PWR_CNTL 0x16bf
+#define mmDAC_DFT_CONFIG 0x16c0
+#define mmDAC_FIFO_STATUS 0x16c1
+#define mmDAC_TEST_DEBUG_INDEX 0x16c2
+#define mmDAC_TEST_DEBUG_DATA 0x16c3
+#define mmPERFCOUNTER_CNTL 0x170
+#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x170
+#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x364
+#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x18c8
+#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x1b24
+#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x1d24
+#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x1f24
+#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x4124
+#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x4324
+#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x4524
+#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x4724
+#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x59a0
+#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x5f68
+#define mmPERFCOUNTER_STATE 0x171
+#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x171
+#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x365
+#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x18c9
+#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x1b25
+#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x1d25
+#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x1f25
+#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x4125
+#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x4325
+#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x4525
+#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x4725
+#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x59a1
+#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x5f69
+#define mmPERFMON_CNTL 0x173
+#define mmDC_PERFMON0_PERFMON_CNTL 0x173
+#define mmDC_PERFMON1_PERFMON_CNTL 0x367
+#define mmDC_PERFMON2_PERFMON_CNTL 0x18cb
+#define mmDC_PERFMON3_PERFMON_CNTL 0x1b27
+#define mmDC_PERFMON4_PERFMON_CNTL 0x1d27
+#define mmDC_PERFMON5_PERFMON_CNTL 0x1f27
+#define mmDC_PERFMON6_PERFMON_CNTL 0x4127
+#define mmDC_PERFMON7_PERFMON_CNTL 0x4327
+#define mmDC_PERFMON8_PERFMON_CNTL 0x4527
+#define mmDC_PERFMON9_PERFMON_CNTL 0x4727
+#define mmDC_PERFMON10_PERFMON_CNTL 0x59a3
+#define mmDC_PERFMON11_PERFMON_CNTL 0x5f6b
+#define mmPERFMON_CNTL2 0x17a
+#define mmDC_PERFMON0_PERFMON_CNTL2 0x17a
+#define mmDC_PERFMON1_PERFMON_CNTL2 0x36e
+#define mmDC_PERFMON2_PERFMON_CNTL2 0x18d2
+#define mmDC_PERFMON3_PERFMON_CNTL2 0x1b2e
+#define mmDC_PERFMON4_PERFMON_CNTL2 0x1d2e
+#define mmDC_PERFMON5_PERFMON_CNTL2 0x1f2e
+#define mmDC_PERFMON6_PERFMON_CNTL2 0x412e
+#define mmDC_PERFMON7_PERFMON_CNTL2 0x432e
+#define mmDC_PERFMON8_PERFMON_CNTL2 0x452e
+#define mmDC_PERFMON9_PERFMON_CNTL2 0x472e
+#define mmDC_PERFMON10_PERFMON_CNTL2 0x59aa
+#define mmDC_PERFMON11_PERFMON_CNTL2 0x5f72
+#define mmPERFMON_CVALUE_INT_MISC 0x172
+#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x172
+#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x366
+#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x18ca
+#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x1b26
+#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x1d26
+#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x1f26
+#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x4126
+#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x4326
+#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x4526
+#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x4726
+#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x59a2
+#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x5f6a
+#define mmPERFMON_CVALUE_LOW 0x174
+#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x174
+#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x368
+#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x18cc
+#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x1b28
+#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x1d28
+#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x1f28
+#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x4128
+#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x4328
+#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x4528
+#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x4728
+#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x59a4
+#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x5f6c
+#define mmPERFMON_HI 0x175
+#define mmDC_PERFMON0_PERFMON_HI 0x175
+#define mmDC_PERFMON1_PERFMON_HI 0x369
+#define mmDC_PERFMON2_PERFMON_HI 0x18cd
+#define mmDC_PERFMON3_PERFMON_HI 0x1b29
+#define mmDC_PERFMON4_PERFMON_HI 0x1d29
+#define mmDC_PERFMON5_PERFMON_HI 0x1f29
+#define mmDC_PERFMON6_PERFMON_HI 0x4129
+#define mmDC_PERFMON7_PERFMON_HI 0x4329
+#define mmDC_PERFMON8_PERFMON_HI 0x4529
+#define mmDC_PERFMON9_PERFMON_HI 0x4729
+#define mmDC_PERFMON10_PERFMON_HI 0x59a5
+#define mmDC_PERFMON11_PERFMON_HI 0x5f6d
+#define mmPERFMON_LOW 0x176
+#define mmDC_PERFMON0_PERFMON_LOW 0x176
+#define mmDC_PERFMON1_PERFMON_LOW 0x36a
+#define mmDC_PERFMON2_PERFMON_LOW 0x18ce
+#define mmDC_PERFMON3_PERFMON_LOW 0x1b2a
+#define mmDC_PERFMON4_PERFMON_LOW 0x1d2a
+#define mmDC_PERFMON5_PERFMON_LOW 0x1f2a
+#define mmDC_PERFMON6_PERFMON_LOW 0x412a
+#define mmDC_PERFMON7_PERFMON_LOW 0x432a
+#define mmDC_PERFMON8_PERFMON_LOW 0x452a
+#define mmDC_PERFMON9_PERFMON_LOW 0x472a
+#define mmDC_PERFMON10_PERFMON_LOW 0x59a6
+#define mmDC_PERFMON11_PERFMON_LOW 0x5f6e
+#define mmPERFMON_TEST_DEBUG_INDEX 0x177
+#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX 0x177
+#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX 0x36b
+#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX 0x18cf
+#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX 0x1b2b
+#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX 0x1d2b
+#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX 0x1f2b
+#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX 0x412b
+#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX 0x432b
+#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX 0x452b
+#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX 0x472b
+#define mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX 0x59a7
+#define mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX 0x5f6f
+#define mmPERFMON_TEST_DEBUG_DATA 0x178
+#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA 0x178
+#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA 0x36c
+#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA 0x18d0
+#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA 0x1b2c
+#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA 0x1d2c
+#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA 0x1f2c
+#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA 0x412c
+#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA 0x432c
+#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA 0x452c
+#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA 0x472c
+#define mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA 0x59a8
+#define mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA 0x5f70
+#define mmREFCLK_CNTL 0x109
+#define mmDCCG_CBUS_WRCMD_DELAY 0x110
+#define mmDPREFCLK_CNTL 0x118
+#define mmDCE_VERSION 0x11e
+#define mmAVSYNC_COUNTER_WRITE 0x12a
+#define mmAVSYNC_COUNTER_CONTROL 0x12b
+#define mmAVSYNC_COUNTER_READ 0x12f
+#define mmDCCG_GTC_CNTL 0x120
+#define mmDCCG_GTC_DTO_INCR 0x121
+#define mmDCCG_GTC_DTO_MODULO 0x122
+#define mmDCCG_GTC_CURRENT 0x123
+#define mmDCCG_DS_DTO_INCR 0x113
+#define mmDCCG_DS_DTO_MODULO 0x114
+#define mmDCCG_DS_CNTL 0x115
+#define mmDCCG_DS_HW_CAL_INTERVAL 0x116
+#define mmDCCG_DS_DEBUG_CNTL 0x112
+#define mmDMCU_SMU_INTERRUPT_CNTL 0x12c
+#define mmSMU_CONTROL 0x12d
+#define mmSMU_INTERRUPT_CONTROL 0x12e
+#define mmDAC_CLK_ENABLE 0x128
+#define mmDVO_CLK_ENABLE 0x129
+#define mmDCCG_GATE_DISABLE_CNTL 0x134
+#define mmDCCG_GATE_DISABLE_CNTL2 0x13c
+#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x135
+#define mmSCLK_CGTT_BLK_CTRL_REG 0x136
+#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x108
+#define mmREFCLK_CGTT_BLK_CTRL_REG 0x10b
+#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x13d
+#define mmDCCG_CAC_STATUS 0x137
+#define mmPIXCLK1_RESYNC_CNTL 0x138
+#define mmPIXCLK2_RESYNC_CNTL 0x139
+#define mmPIXCLK0_RESYNC_CNTL 0x13a
+#define mmPHYPLL_PIXCLK_CNTL 0x13e
+#define mmMICROSECOND_TIME_BASE_DIV 0x13b
+#define mmDCCG_DISP_CNTL_REG 0x13f
+#define mmMILLISECOND_TIME_BASE_DIV 0x130
+#define mmDISPCLK_FREQ_CHANGE_CNTL 0x131
+#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x132
+#define mmDCCG_PERFMON_CNTL 0x133
+#define mmDCCG_PERFMON_CNTL2 0x10e
+#define mmCRTC0_PIXEL_RATE_CNTL 0x140
+#define mmDP_DTO0_PHASE 0x141
+#define mmDP_DTO0_MODULO 0x142
+#define mmCRTC1_PIXEL_RATE_CNTL 0x144
+#define mmDP_DTO1_PHASE 0x145
+#define mmDP_DTO1_MODULO 0x146
+#define mmCRTC2_PIXEL_RATE_CNTL 0x148
+#define mmDP_DTO2_PHASE 0x149
+#define mmDP_DTO2_MODULO 0x14a
+#define mmCRTC3_PIXEL_RATE_CNTL 0x14c
+#define mmDP_DTO3_PHASE 0x14d
+#define mmDP_DTO3_MODULO 0x14e
+#define mmCRTC4_PIXEL_RATE_CNTL 0x150
+#define mmDP_DTO4_PHASE 0x151
+#define mmDP_DTO4_MODULO 0x152
+#define mmCRTC5_PIXEL_RATE_CNTL 0x154
+#define mmDP_DTO5_PHASE 0x155
+#define mmDP_DTO5_MODULO 0x156
+#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL 0x104
+#define mmDCCG_SOFT_RESET 0x15f
+#define mmSYMCLKA_CLOCK_ENABLE 0x160
+#define mmSYMCLKB_CLOCK_ENABLE 0x161
+#define mmSYMCLKC_CLOCK_ENABLE 0x162
+#define mmSYMCLKD_CLOCK_ENABLE 0x163
+#define mmSYMCLKE_CLOCK_ENABLE 0x164
+#define mmSYMCLKF_CLOCK_ENABLE 0x165
+#define mmSYMCLKG_CLOCK_ENABLE 0x117
+#define mmDPDBG_CLK_FORCE_CONTROL 0x10d
+#define mmDCCG_AUDIO_DTO_SOURCE 0x16b
+#define mmDCCG_AUDIO_DTO0_PHASE 0x16c
+#define mmDCCG_AUDIO_DTO0_MODULE 0x16d
+#define mmDCCG_AUDIO_DTO1_PHASE 0x16e
+#define mmDCCG_AUDIO_DTO1_MODULE 0x16f
+#define mmDCCG_TEST_DEBUG_INDEX 0x17c
+#define mmDCCG_TEST_DEBUG_DATA 0x17d
+#define mmDCCG_TEST_CLK_SEL 0x17e
+#define mmCPLL_MACRO_CNTL_RESERVED0 0x5fd0
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0 0x5fd0
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0 0x5fdc
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0 0x5fe8
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0 0x5ff4
+#define mmCPLL_MACRO_CNTL_RESERVED1 0x5fd1
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1 0x5fd1
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1 0x5fdd
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1 0x5fe9
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1 0x5ff5
+#define mmCPLL_MACRO_CNTL_RESERVED2 0x5fd2
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2 0x5fd2
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2 0x5fde
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2 0x5fea
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2 0x5ff6
+#define mmCPLL_MACRO_CNTL_RESERVED3 0x5fd3
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3 0x5fd3
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3 0x5fdf
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3 0x5feb
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3 0x5ff7
+#define mmCPLL_MACRO_CNTL_RESERVED4 0x5fd4
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4 0x5fd4
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4 0x5fe0
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4 0x5fec
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4 0x5ff8
+#define mmCPLL_MACRO_CNTL_RESERVED5 0x5fd5
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5 0x5fd5
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5 0x5fe1
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5 0x5fed
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5 0x5ff9
+#define mmCPLL_MACRO_CNTL_RESERVED6 0x5fd6
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6 0x5fd6
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6 0x5fe2
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6 0x5fee
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6 0x5ffa
+#define mmCPLL_MACRO_CNTL_RESERVED7 0x5fd7
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7 0x5fd7
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7 0x5fe3
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7 0x5fef
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7 0x5ffb
+#define mmCPLL_MACRO_CNTL_RESERVED8 0x5fd8
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8 0x5fd8
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8 0x5fe4
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8 0x5ff0
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8 0x5ffc
+#define mmCPLL_MACRO_CNTL_RESERVED9 0x5fd9
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9 0x5fd9
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9 0x5fe5
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9 0x5ff1
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9 0x5ffd
+#define mmCPLL_MACRO_CNTL_RESERVED10 0x5fda
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10 0x5fda
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10 0x5fe6
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10 0x5ff2
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10 0x5ffe
+#define mmCPLL_MACRO_CNTL_RESERVED11 0x5fdb
+#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11 0x5fdb
+#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11 0x5fe7
+#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11 0x5ff3
+#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11 0x5fff
+#define mmPLL_MACRO_CNTL_RESERVED0 0x1700
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0 0x1700
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0 0x172a
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0 0x1754
+#define mmPLL_MACRO_CNTL_RESERVED1 0x1701
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1 0x1701
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1 0x172b
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1 0x1755
+#define mmPLL_MACRO_CNTL_RESERVED2 0x1702
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2 0x1702
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2 0x172c
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2 0x1756
+#define mmPLL_MACRO_CNTL_RESERVED3 0x1703
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3 0x1703
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3 0x172d
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3 0x1757
+#define mmPLL_MACRO_CNTL_RESERVED4 0x1704
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4 0x1704
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4 0x172e
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4 0x1758
+#define mmPLL_MACRO_CNTL_RESERVED5 0x1705
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5 0x1705
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5 0x172f
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5 0x1759
+#define mmPLL_MACRO_CNTL_RESERVED6 0x1706
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6 0x1706
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6 0x1730
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6 0x175a
+#define mmPLL_MACRO_CNTL_RESERVED7 0x1707
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7 0x1707
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7 0x1731
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7 0x175b
+#define mmPLL_MACRO_CNTL_RESERVED8 0x1708
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8 0x1708
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8 0x1732
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8 0x175c
+#define mmPLL_MACRO_CNTL_RESERVED9 0x1709
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9 0x1709
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9 0x1733
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9 0x175d
+#define mmPLL_MACRO_CNTL_RESERVED10 0x170a
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10 0x170a
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10 0x1734
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10 0x175e
+#define mmPLL_MACRO_CNTL_RESERVED11 0x170b
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11 0x170b
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11 0x1735
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11 0x175f
+#define mmPLL_MACRO_CNTL_RESERVED12 0x170c
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12 0x170c
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12 0x1736
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12 0x1760
+#define mmPLL_MACRO_CNTL_RESERVED13 0x170d
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13 0x170d
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13 0x1737
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13 0x1761
+#define mmPLL_MACRO_CNTL_RESERVED14 0x170e
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14 0x170e
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14 0x1738
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14 0x1762
+#define mmPLL_MACRO_CNTL_RESERVED15 0x170f
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15 0x170f
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15 0x1739
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15 0x1763
+#define mmPLL_MACRO_CNTL_RESERVED16 0x1710
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16 0x1710
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16 0x173a
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16 0x1764
+#define mmPLL_MACRO_CNTL_RESERVED17 0x1711
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17 0x1711
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17 0x173b
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17 0x1765
+#define mmPLL_MACRO_CNTL_RESERVED18 0x1712
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18 0x1712
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18 0x173c
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18 0x1766
+#define mmPLL_MACRO_CNTL_RESERVED19 0x1713
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19 0x1713
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19 0x173d
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19 0x1767
+#define mmPLL_MACRO_CNTL_RESERVED20 0x1714
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20 0x1714
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20 0x173e
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20 0x1768
+#define mmPLL_MACRO_CNTL_RESERVED21 0x1715
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21 0x1715
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21 0x173f
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21 0x1769
+#define mmPLL_MACRO_CNTL_RESERVED22 0x1716
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22 0x1716
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22 0x1740
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22 0x176a
+#define mmPLL_MACRO_CNTL_RESERVED23 0x1717
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23 0x1717
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23 0x1741
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23 0x176b
+#define mmPLL_MACRO_CNTL_RESERVED24 0x1718
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24 0x1718
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24 0x1742
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24 0x176c
+#define mmPLL_MACRO_CNTL_RESERVED25 0x1719
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25 0x1719
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25 0x1743
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25 0x176d
+#define mmPLL_MACRO_CNTL_RESERVED26 0x171a
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26 0x171a
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26 0x1744
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26 0x176e
+#define mmPLL_MACRO_CNTL_RESERVED27 0x171b
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27 0x171b
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27 0x1745
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27 0x176f
+#define mmPLL_MACRO_CNTL_RESERVED28 0x171c
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28 0x171c
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28 0x1746
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28 0x1770
+#define mmPLL_MACRO_CNTL_RESERVED29 0x171d
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29 0x171d
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29 0x1747
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29 0x1771
+#define mmPLL_MACRO_CNTL_RESERVED30 0x171e
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30 0x171e
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30 0x1748
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30 0x1772
+#define mmPLL_MACRO_CNTL_RESERVED31 0x171f
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31 0x171f
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31 0x1749
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31 0x1773
+#define mmPLL_MACRO_CNTL_RESERVED32 0x1720
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32 0x1720
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32 0x174a
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32 0x1774
+#define mmPLL_MACRO_CNTL_RESERVED33 0x1721
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33 0x1721
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33 0x174b
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33 0x1775
+#define mmPLL_MACRO_CNTL_RESERVED34 0x1722
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34 0x1722
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34 0x174c
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34 0x1776
+#define mmPLL_MACRO_CNTL_RESERVED35 0x1723
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35 0x1723
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35 0x174d
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35 0x1777
+#define mmPLL_MACRO_CNTL_RESERVED36 0x1724
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36 0x1724
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36 0x174e
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36 0x1778
+#define mmPLL_MACRO_CNTL_RESERVED37 0x1725
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37 0x1725
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37 0x174f
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37 0x1779
+#define mmPLL_MACRO_CNTL_RESERVED38 0x1726
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38 0x1726
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38 0x1750
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38 0x177a
+#define mmPLL_MACRO_CNTL_RESERVED39 0x1727
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39 0x1727
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39 0x1751
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39 0x177b
+#define mmPLL_MACRO_CNTL_RESERVED40 0x1728
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40 0x1728
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40 0x1752
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40 0x177c
+#define mmPLL_MACRO_CNTL_RESERVED41 0x1729
+#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41 0x1729
+#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41 0x1753
+#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41 0x177d
+#define mmDENTIST_DISPCLK_CNTL 0x124
+#define mmDCDEBUG_BUS_CLK1_SEL 0x16c4
+#define mmDCDEBUG_BUS_CLK2_SEL 0x16c5
+#define mmDCDEBUG_BUS_CLK3_SEL 0x16c6
+#define mmDCDEBUG_BUS_CLK4_SEL 0x16c7
+#define mmDCDEBUG_BUS_CLK5_SEL 0x16c8
+#define mmDCDEBUG_OUT_PIN_OVERRIDE 0x16c9
+#define mmDCDEBUG_OUT_CNTL 0x16ca
+#define mmDCDEBUG_OUT_DATA 0x16cb
+#define mmDMIF_ADDR_CONFIG 0x2f5
+#define mmDMIF_CONTROL 0x2f6
+#define mmDMIF_STATUS 0x2f7
+#define mmDMIF_HW_DEBUG 0x2f8
+#define mmDMIF_ARBITRATION_CONTROL 0x2f9
+#define mmPIPE0_ARBITRATION_CONTROL3 0x2fa
+#define mmPIPE1_ARBITRATION_CONTROL3 0x2fb
+#define mmPIPE2_ARBITRATION_CONTROL3 0x2fc
+#define mmPIPE3_ARBITRATION_CONTROL3 0x2fd
+#define mmPIPE4_ARBITRATION_CONTROL3 0x2fe
+#define mmPIPE5_ARBITRATION_CONTROL3 0x2ff
+#define mmPIPE6_ARBITRATION_CONTROL3 0x32a
+#define mmPIPE7_ARBITRATION_CONTROL3 0x32b
+#define mmDMIF_P_VMID 0x300
+#define mmDMIF_URG_OVERRIDE 0x329
+#define mmDMIF_TEST_DEBUG_INDEX 0x301
+#define mmDMIF_TEST_DEBUG_DATA 0x302
+#define ixDMIF_DEBUG02_CORE0 0x2
+#define ixDMIF_DEBUG02_CORE1 0xa
+#define mmDMIF_ADDR_CALC 0x303
+#define mmDMIF_STATUS2 0x304
+#define mmPIPE0_MAX_REQUESTS 0x305
+#define mmPIPE1_MAX_REQUESTS 0x306
+#define mmPIPE2_MAX_REQUESTS 0x307
+#define mmPIPE3_MAX_REQUESTS 0x308
+#define mmPIPE4_MAX_REQUESTS 0x309
+#define mmPIPE5_MAX_REQUESTS 0x30a
+#define mmPIPE6_MAX_REQUESTS 0x32c
+#define mmPIPE7_MAX_REQUESTS 0x32d
+#define mmDVMM_REG_RD_STATUS 0x32e
+#define mmDVMM_REG_RD_DATA 0x32f
+#define mmDVMM_PTE_REQ 0x330
+#define mmDVMM_CNTL 0x331
+#define mmDVMM_FAULT_STATUS 0x332
+#define mmDVMM_FAULT_ADDR 0x333
+#define mmLOW_POWER_TILING_CONTROL 0x30b
+#define mmMCIF_CONTROL 0x30c
+#define mmMCIF_WRITE_COMBINE_CONTROL 0x30d
+#define mmMCIF_TEST_DEBUG_INDEX 0x30e
+#define mmMCIF_TEST_DEBUG_DATA 0x30f
+#define ixIDDCCIF02_DBG_DCCIF_C 0x9
+#define ixIDDCCIF04_DBG_DCCIF_E 0xb
+#define ixIDDCCIF05_DBG_DCCIF_F 0xc
+#define mmMCIF_VMID 0x310
+#define mmMCIF_MEM_CONTROL 0x311
+#define mmCC_DC_PIPE_DIS 0x312
+#define mmMC_DC_INTERFACE_NACK_STATUS 0x313
+#define mmRBBMIF_TIMEOUT 0x314
+#define mmRBBMIF_STATUS 0x315
+#define mmRBBMIF_TIMEOUT_DIS 0x316
+#define mmRBBMIF_STATUS_FLAG 0x327
+#define mmDCI_MEM_PWR_STATUS 0x317
+#define mmDCI_MEM_PWR_STATUS2 0x318
+#define mmDCI_CLK_CNTL 0x319
+#define mmDCI_CLK_RAMP_CNTL 0x31a
+#define mmDCI_MEM_PWR_CNTL 0x31b
+#define mmDCI_MEM_PWR_CNTL2 0x31c
+#define mmDCI_MEM_PWR_CNTL3 0x31d
+#define mmDVMM_PTE_PGMEM_CONTROL 0x335
+#define mmDVMM_PTE_PGMEM_STATE 0x336
+#define mmDCI_SOFT_RESET 0x328
+#define mmDCI_MISC 0x334
+#define mmDCI_TEST_DEBUG_INDEX 0x31e
+#define mmDCI_TEST_DEBUG_DATA 0x31f
+#define mmDCI_DEBUG_CONFIG 0x320
+#define mmPIPE0_DMIF_BUFFER_CONTROL 0x321
+#define mmPIPE1_DMIF_BUFFER_CONTROL 0x322
+#define mmPIPE2_DMIF_BUFFER_CONTROL 0x323
+#define mmPIPE3_DMIF_BUFFER_CONTROL 0x324
+#define mmPIPE4_DMIF_BUFFER_CONTROL 0x325
+#define mmPIPE5_DMIF_BUFFER_CONTROL 0x326
+#define mmDC_GENERICA 0x4800
+#define mmDC_GENERICB 0x4801
+#define mmDC_PAD_EXTERN_SIG 0x4802
+#define mmDC_REF_CLK_CNTL 0x4803
+#define mmDC_GPIO_DEBUG 0x4804
+#define mmUNIPHYA_LINK_CNTL 0x4805
+#define mmUNIPHYB_LINK_CNTL 0x4807
+#define mmUNIPHYC_LINK_CNTL 0x4809
+#define mmUNIPHYD_LINK_CNTL 0x480b
+#define mmUNIPHYE_LINK_CNTL 0x480d
+#define mmUNIPHYF_LINK_CNTL 0x480f
+#define mmUNIPHYG_LINK_CNTL 0x4811
+#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x4806
+#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x4808
+#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x480a
+#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x480c
+#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x480e
+#define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x4810
+#define mmUNIPHYG_CHANNEL_XBAR_CNTL 0x4812
+#define mmUNIPHYLPA_LINK_CNTL 0x4847
+#define mmUNIPHYLPB_LINK_CNTL 0x4848
+#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL 0x4849
+#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL 0x484a
+#define mmUNIPHY_IMPCAL_LINKA 0x4838
+#define mmUNIPHY_IMPCAL_LINKB 0x4839
+#define mmUNIPHY_IMPCAL_LINKC 0x483f
+#define mmUNIPHY_IMPCAL_LINKD 0x4840
+#define mmUNIPHY_IMPCAL_LINKE 0x4843
+#define mmUNIPHY_IMPCAL_LINKF 0x4844
+#define mmUNIPHY_IMPCAL_PERIOD 0x483a
+#define mmAUXP_IMPCAL 0x483b
+#define mmAUXN_IMPCAL 0x483c
+#define mmDCIO_IMPCAL_CNTL 0x483d
+#define mmUNIPHY_IMPCAL_PSW_AB 0x483e
+#define mmDCIO_IMPCAL_CNTL_CD 0x4841
+#define mmUNIPHY_IMPCAL_PSW_CD 0x4842
+#define mmDCIO_IMPCAL_CNTL_EF 0x4845
+#define mmUNIPHY_IMPCAL_PSW_EF 0x4846
+#define mmDCIO_WRCMD_DELAY 0x4816
+#define mmDC_PINSTRAPS 0x4818
+#define mmDC_DVODATA_CONFIG 0x481a
+#define mmLVTMA_PWRSEQ_CNTL 0x481b
+#define mmLVTMA_PWRSEQ_STATE 0x481c
+#define mmLVTMA_PWRSEQ_REF_DIV 0x481d
+#define mmLVTMA_PWRSEQ_DELAY1 0x481e
+#define mmLVTMA_PWRSEQ_DELAY2 0x481f
+#define mmBL_PWM_CNTL 0x4820
+#define mmBL_PWM_CNTL2 0x4821
+#define mmBL_PWM_PERIOD_CNTL 0x4822
+#define mmBL_PWM_GRP1_REG_LOCK 0x4823
+#define mmDCIO_GSL_GENLK_PAD_CNTL 0x4824
+#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x4825
+#define mmDCIO_GSL0_CNTL 0x4826
+#define mmDCIO_GSL1_CNTL 0x4827
+#define mmDCIO_GSL2_CNTL 0x4828
+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x4829
+#define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x482a
+#define mmDC_GPU_TIMER_READ 0x482b
+#define mmDC_GPU_TIMER_READ_CNTL 0x482c
+#define mmDCIO_CLOCK_CNTL 0x482d
+#define mmDCIO_DEBUG 0x482f
+#define mmDCO_DCFE_EXT_VSYNC_CNTL 0x4830
+#define mmDBG_OUT_CNTL 0x4834
+#define mmDCIO_DEBUG_CONFIG 0x4835
+#define mmDCIO_SOFT_RESET 0x4836
+#define mmDCIO_DPHY_SEL 0x4837
+#define mmDCIO_TEST_DEBUG_INDEX 0x4831
+#define mmDCIO_TEST_DEBUG_DATA 0x4832
+#define ixDCIO_DEBUG1 0x1
+#define ixDCIO_DEBUG2 0x2
+#define ixDCIO_DEBUG3 0x3
+#define ixDCIO_DEBUG4 0x4
+#define ixDCIO_DEBUG5 0x5
+#define ixDCIO_DEBUG6 0x6
+#define ixDCIO_DEBUG7 0x7
+#define ixDCIO_DEBUG8 0x8
+#define ixDCIO_DEBUG9 0x9
+#define ixDCIO_DEBUGA 0xa
+#define ixDCIO_DEBUGB 0xb
+#define ixDCIO_DEBUGC 0xc
+#define ixDCIO_DEBUGD 0xd
+#define ixDCIO_DEBUGE 0xe
+#define ixDCIO_DEBUGF 0xf
+#define ixDCIO_DEBUG10 0x10
+#define ixDCIO_DEBUG11 0x11
+#define ixDCIO_DEBUG12 0x12
+#define ixDCIO_DEBUG13 0x13
+#define ixDCIO_DEBUG14 0x14
+#define ixDCIO_DEBUG15 0x15
+#define ixDCIO_DEBUG16 0x16
+#define ixDCIO_DEBUG17 0x17
+#define ixDCIO_DEBUG18 0x18
+#define ixDCIO_DEBUG19 0x19
+#define ixDCIO_DEBUG1A 0x1a
+#define ixDCIO_DEBUG1B 0x1b
+#define ixDCIO_DEBUG_ID 0x0
+#define mmDC_GPIO_GENERIC_MASK 0x4860
+#define mmDC_GPIO_GENERIC_A 0x4861
+#define mmDC_GPIO_GENERIC_EN 0x4862
+#define mmDC_GPIO_GENERIC_Y 0x4863
+#define mmDC_GPIO_DVODATA_MASK 0x4864
+#define mmDC_GPIO_DVODATA_A 0x4865
+#define mmDC_GPIO_DVODATA_EN 0x4866
+#define mmDC_GPIO_DVODATA_Y 0x4867
+#define mmDC_GPIO_DDC1_MASK 0x4868
+#define mmDC_GPIO_DDC1_A 0x4869
+#define mmDC_GPIO_DDC1_EN 0x486a
+#define mmDC_GPIO_DDC1_Y 0x486b
+#define mmDC_GPIO_DDC2_MASK 0x486c
+#define mmDC_GPIO_DDC2_A 0x486d
+#define mmDC_GPIO_DDC2_EN 0x486e
+#define mmDC_GPIO_DDC2_Y 0x486f
+#define mmDC_GPIO_DDC3_MASK 0x4870
+#define mmDC_GPIO_DDC3_A 0x4871
+#define mmDC_GPIO_DDC3_EN 0x4872
+#define mmDC_GPIO_DDC3_Y 0x4873
+#define mmDC_GPIO_DDC4_MASK 0x4874
+#define mmDC_GPIO_DDC4_A 0x4875
+#define mmDC_GPIO_DDC4_EN 0x4876
+#define mmDC_GPIO_DDC4_Y 0x4877
+#define mmDC_GPIO_DDC5_MASK 0x4878
+#define mmDC_GPIO_DDC5_A 0x4879
+#define mmDC_GPIO_DDC5_EN 0x487a
+#define mmDC_GPIO_DDC5_Y 0x487b
+#define mmDC_GPIO_DDC6_MASK 0x487c
+#define mmDC_GPIO_DDC6_A 0x487d
+#define mmDC_GPIO_DDC6_EN 0x487e
+#define mmDC_GPIO_DDC6_Y 0x487f
+#define mmDC_GPIO_DDCVGA_MASK 0x4880
+#define mmDC_GPIO_DDCVGA_A 0x4881
+#define mmDC_GPIO_DDCVGA_EN 0x4882
+#define mmDC_GPIO_DDCVGA_Y 0x4883
+#define mmDC_GPIO_SYNCA_MASK 0x4884
+#define mmDC_GPIO_SYNCA_A 0x4885
+#define mmDC_GPIO_SYNCA_EN 0x4886
+#define mmDC_GPIO_SYNCA_Y 0x4887
+#define mmDC_GPIO_GENLK_MASK 0x4888
+#define mmDC_GPIO_GENLK_A 0x4889
+#define mmDC_GPIO_GENLK_EN 0x488a
+#define mmDC_GPIO_GENLK_Y 0x488b
+#define mmDC_GPIO_HPD_MASK 0x488c
+#define mmDC_GPIO_HPD_A 0x488d
+#define mmDC_GPIO_HPD_EN 0x488e
+#define mmDC_GPIO_HPD_Y 0x488f
+#define mmDC_GPIO_PWRSEQ_MASK 0x4890
+#define mmDC_GPIO_PWRSEQ_A 0x4891
+#define mmDC_GPIO_PWRSEQ_EN 0x4892
+#define mmDC_GPIO_PWRSEQ_Y 0x4893
+#define mmDC_GPIO_PAD_STRENGTH_1 0x4894
+#define mmDC_GPIO_PAD_STRENGTH_2 0x4895
+#define mmPHY_AUX_CNTL 0x4897
+#define mmDC_GPIO_I2CPAD_MASK 0x4898
+#define mmDC_GPIO_I2CPAD_A 0x4899
+#define mmDC_GPIO_I2CPAD_EN 0x489a
+#define mmDC_GPIO_I2CPAD_Y 0x489b
+#define mmDC_GPIO_I2CPAD_STRENGTH 0x489c
+#define mmDVO_VREF_CONTROL 0x489e
+#define mmDVO_SKEW_ADJUST 0x489f
+#define mmDAC_MACRO_CNTL_RESERVED0 0x48b8
+#define mmDAC_MACRO_CNTL_RESERVED1 0x48b9
+#define mmDAC_MACRO_CNTL_RESERVED2 0x48ba
+#define mmDAC_MACRO_CNTL_RESERVED3 0x48bb
+#define mmUNIPHY_MACRO_CNTL_RESERVED0 0x48c0
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x48c0
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x48e0
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x4900
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x4920
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x4940
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x4960
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x4980
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED0 0x49c0
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0 0x49e0
+#define mmUNIPHY_MACRO_CNTL_RESERVED1 0x48c1
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x48c1
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x48e1
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x4901
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x4921
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x4941
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x4961
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x4981
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED1 0x49c1
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1 0x49e1
+#define mmUNIPHY_MACRO_CNTL_RESERVED2 0x48c2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x48c2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x48e2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x4902
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x4922
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x4942
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x4962
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x4982
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED2 0x49c2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2 0x49e2
+#define mmUNIPHY_MACRO_CNTL_RESERVED3 0x48c3
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x48c3
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x48e3
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x4903
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x4923
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x4943
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x4963
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x4983
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED3 0x49c3
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3 0x49e3
+#define mmUNIPHY_MACRO_CNTL_RESERVED4 0x48c4
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x48c4
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x48e4
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x4904
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x4924
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x4944
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x4964
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x4984
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED4 0x49c4
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4 0x49e4
+#define mmUNIPHY_MACRO_CNTL_RESERVED5 0x48c5
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x48c5
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x48e5
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x4905
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x4925
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x4945
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x4965
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x4985
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED5 0x49c5
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5 0x49e5
+#define mmUNIPHY_MACRO_CNTL_RESERVED6 0x48c6
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x48c6
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x48e6
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x4906
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x4926
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x4946
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x4966
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x4986
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED6 0x49c6
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6 0x49e6
+#define mmUNIPHY_MACRO_CNTL_RESERVED7 0x48c7
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x48c7
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x48e7
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x4907
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x4927
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x4947
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x4967
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x4987
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED7 0x49c7
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7 0x49e7
+#define mmUNIPHY_MACRO_CNTL_RESERVED8 0x48c8
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x48c8
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x48e8
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x4908
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x4928
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x4948
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x4968
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x4988
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED8 0x49c8
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8 0x49e8
+#define mmUNIPHY_MACRO_CNTL_RESERVED9 0x48c9
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x48c9
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x48e9
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x4909
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x4929
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x4949
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x4969
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x4989
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED9 0x49c9
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9 0x49e9
+#define mmUNIPHY_MACRO_CNTL_RESERVED10 0x48ca
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x48ca
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x48ea
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x490a
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x492a
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x494a
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x496a
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x498a
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED10 0x49ca
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10 0x49ea
+#define mmUNIPHY_MACRO_CNTL_RESERVED11 0x48cb
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x48cb
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x48eb
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x490b
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x492b
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x494b
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x496b
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x498b
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED11 0x49cb
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11 0x49eb
+#define mmUNIPHY_MACRO_CNTL_RESERVED12 0x48cc
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x48cc
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x48ec
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x490c
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x492c
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x494c
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x496c
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x498c
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED12 0x49cc
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12 0x49ec
+#define mmUNIPHY_MACRO_CNTL_RESERVED13 0x48cd
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x48cd
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x48ed
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x490d
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x492d
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x494d
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x496d
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x498d
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED13 0x49cd
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13 0x49ed
+#define mmUNIPHY_MACRO_CNTL_RESERVED14 0x48ce
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x48ce
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x48ee
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x490e
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x492e
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x494e
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x496e
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x498e
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED14 0x49ce
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14 0x49ee
+#define mmUNIPHY_MACRO_CNTL_RESERVED15 0x48cf
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x48cf
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x48ef
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x490f
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x492f
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x494f
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x496f
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x498f
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED15 0x49cf
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15 0x49ef
+#define mmUNIPHY_MACRO_CNTL_RESERVED16 0x48d0
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x48d0
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x48f0
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x4910
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x4930
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x4950
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x4970
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x4990
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED16 0x49d0
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16 0x49f0
+#define mmUNIPHY_MACRO_CNTL_RESERVED17 0x48d1
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x48d1
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x48f1
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x4911
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x4931
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x4951
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x4971
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x4991
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED17 0x49d1
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17 0x49f1
+#define mmUNIPHY_MACRO_CNTL_RESERVED18 0x48d2
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x48d2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x48f2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x4912
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x4932
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x4952
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x4972
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x4992
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED18 0x49d2
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18 0x49f2
+#define mmUNIPHY_MACRO_CNTL_RESERVED19 0x48d3
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x48d3
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x48f3
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x4913
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x4933
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x4953
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x4973
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x4993
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED19 0x49d3
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19 0x49f3
+#define mmUNIPHY_MACRO_CNTL_RESERVED20 0x48d4
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x48d4
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x48f4
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x4914
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x4934
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x4954
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x4974
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x4994
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED20 0x49d4
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20 0x49f4
+#define mmUNIPHY_MACRO_CNTL_RESERVED21 0x48d5
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x48d5
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x48f5
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x4915
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x4935
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x4955
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x4975
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x4995
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED21 0x49d5
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21 0x49f5
+#define mmUNIPHY_MACRO_CNTL_RESERVED22 0x48d6
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x48d6
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x48f6
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x4916
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x4936
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x4956
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x4976
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x4996
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED22 0x49d6
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22 0x49f6
+#define mmUNIPHY_MACRO_CNTL_RESERVED23 0x48d7
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x48d7
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x48f7
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x4917
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x4937
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x4957
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x4977
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x4997
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED23 0x49d7
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23 0x49f7
+#define mmUNIPHY_MACRO_CNTL_RESERVED24 0x48d8
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x48d8
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x48f8
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x4918
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x4938
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x4958
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x4978
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x4998
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED24 0x49d8
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24 0x49f8
+#define mmUNIPHY_MACRO_CNTL_RESERVED25 0x48d9
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x48d9
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x48f9
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x4919
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x4939
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x4959
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x4979
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x4999
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED25 0x49d9
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25 0x49f9
+#define mmUNIPHY_MACRO_CNTL_RESERVED26 0x48da
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x48da
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x48fa
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x491a
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x493a
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x495a
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x497a
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x499a
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED26 0x49da
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26 0x49fa
+#define mmUNIPHY_MACRO_CNTL_RESERVED27 0x48db
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x48db
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x48fb
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x491b
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x493b
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x495b
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x497b
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x499b
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED27 0x49db
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27 0x49fb
+#define mmUNIPHY_MACRO_CNTL_RESERVED28 0x48dc
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x48dc
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x48fc
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x491c
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x493c
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x495c
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x497c
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x499c
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED28 0x49dc
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28 0x49fc
+#define mmUNIPHY_MACRO_CNTL_RESERVED29 0x48dd
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x48dd
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x48fd
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x491d
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x493d
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x495d
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x497d
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x499d
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED29 0x49dd
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29 0x49fd
+#define mmUNIPHY_MACRO_CNTL_RESERVED30 0x48de
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x48de
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x48fe
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x491e
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x493e
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x495e
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x497e
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x499e
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED30 0x49de
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30 0x49fe
+#define mmUNIPHY_MACRO_CNTL_RESERVED31 0x48df
+#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x48df
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x48ff
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x491f
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x493f
+#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x495f
+#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x497f
+#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x499f
+#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED31 0x49df
+#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31 0x49ff
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED0 0x5a84
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED1 0x5a85
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED2 0x5a86
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED3 0x5a87
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED4 0x5a88
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED5 0x5a89
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED6 0x5a8a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED7 0x5a8b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED8 0x5a8c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED9 0x5a8d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED10 0x5a8e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED11 0x5a8f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED12 0x5a90
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED13 0x5a91
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED14 0x5a92
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED15 0x5a93
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED16 0x5a94
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED17 0x5a95
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED18 0x5a96
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED19 0x5a97
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED20 0x5a98
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED21 0x5a99
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED22 0x5a9a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED23 0x5a9b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED24 0x5a9c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED25 0x5a9d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED26 0x5a9e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED27 0x5a9f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED28 0x5aa0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED29 0x5aa1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED30 0x5aa2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED31 0x5aa3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED32 0x5aa4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED33 0x5aa5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED34 0x5aa6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED35 0x5aa7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED36 0x5aa8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED37 0x5aa9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED38 0x5aaa
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED39 0x5aab
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED40 0x5aac
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED41 0x5aad
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED42 0x5aae
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED43 0x5aaf
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED44 0x5ab0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED45 0x5ab1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED46 0x5ab2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED47 0x5ab3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED48 0x5ab4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED49 0x5ab5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED50 0x5ab6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED51 0x5ab7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED52 0x5ab8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED53 0x5ab9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED54 0x5aba
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED55 0x5abb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED56 0x5abc
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED57 0x5abd
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED58 0x5abe
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED59 0x5abf
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED60 0x5ac0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED61 0x5ac1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED62 0x5ac2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED63 0x5ac3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED64 0x5ac4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED65 0x5ac5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED66 0x5ac6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED67 0x5ac7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED68 0x5ac8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED69 0x5ac9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED70 0x5aca
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED71 0x5acb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED72 0x5acc
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED73 0x5acd
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED74 0x5ace
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED75 0x5acf
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED76 0x5ad0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED77 0x5ad1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED78 0x5ad2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED79 0x5ad3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED80 0x5ad4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED81 0x5ad5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED82 0x5ad6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED83 0x5ad7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED84 0x5ad8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED85 0x5ad9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED86 0x5ada
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED87 0x5adb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED88 0x5adc
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED89 0x5add
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED90 0x5ade
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED91 0x5adf
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED92 0x5ae0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED93 0x5ae1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED94 0x5ae2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED95 0x5ae3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED96 0x5ae4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED97 0x5ae5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED98 0x5ae6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED99 0x5ae7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED100 0x5ae8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED101 0x5ae9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED102 0x5aea
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED103 0x5aeb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED104 0x5aec
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED105 0x5aed
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED106 0x5aee
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED107 0x5aef
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED108 0x5af0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED109 0x5af1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED110 0x5af2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED111 0x5af3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED112 0x5af4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED113 0x5af5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED114 0x5af6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED115 0x5af7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED116 0x5af8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED117 0x5af9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED118 0x5afa
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED119 0x5afb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED120 0x5afc
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED121 0x5afd
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED122 0x5afe
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED123 0x5aff
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED124 0x5b00
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED125 0x5b01
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED126 0x5b02
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED127 0x5b03
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED128 0x5b04
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED129 0x5b05
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED130 0x5b06
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED131 0x5b07
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED132 0x5b08
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED133 0x5b09
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED134 0x5b0a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED135 0x5b0b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED136 0x5b0c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED137 0x5b0d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED138 0x5b0e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED139 0x5b0f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED140 0x5b10
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED141 0x5b11
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED142 0x5b12
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED143 0x5b13
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED144 0x5b14
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED145 0x5b15
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED146 0x5b16
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED147 0x5b17
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED148 0x5b18
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED149 0x5b19
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED150 0x5b1a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED151 0x5b1b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED152 0x5b1c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED153 0x5b1d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED154 0x5b1e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED155 0x5b1f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED156 0x5b20
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED157 0x5b21
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED158 0x5b22
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED159 0x5b23
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED160 0x5b24
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED161 0x5b25
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED162 0x5b26
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED163 0x5b27
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED164 0x5b28
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED165 0x5b29
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED166 0x5b2a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED167 0x5b2b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED168 0x5b2c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED169 0x5b2d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED170 0x5b2e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED171 0x5b2f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED172 0x5b30
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED173 0x5b31
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED174 0x5b32
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED175 0x5b33
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED176 0x5b34
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED177 0x5b35
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED178 0x5b36
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED179 0x5b37
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED180 0x5b38
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED181 0x5b39
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED182 0x5b3a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED183 0x5b3b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED184 0x5b3c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED185 0x5b3d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED186 0x5b3e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED187 0x5b3f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED188 0x5b40
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED189 0x5b41
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED190 0x5b42
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED191 0x5b43
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED192 0x5b44
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED193 0x5b45
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED194 0x5b46
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED195 0x5b47
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED196 0x5b48
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED197 0x5b49
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED198 0x5b4a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED199 0x5b4b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED200 0x5b4c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED201 0x5b4d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED202 0x5b4e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED203 0x5b4f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED204 0x5b50
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED205 0x5b51
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED206 0x5b52
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED207 0x5b53
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED208 0x5b54
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED209 0x5b55
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED210 0x5b56
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED211 0x5b57
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED212 0x5b58
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED213 0x5b59
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED214 0x5b5a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED215 0x5b5b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED216 0x5b5c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED217 0x5b5d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED218 0x5b5e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED219 0x5b5f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED220 0x5b60
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED221 0x5b61
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED222 0x5b62
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED223 0x5b63
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED224 0x5b64
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED225 0x5b65
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED226 0x5b66
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED227 0x5b67
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED228 0x5b68
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED229 0x5b69
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED230 0x5b6a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED231 0x5b6b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED232 0x5b6c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED233 0x5b6d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED234 0x5b6e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED235 0x5b6f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED236 0x5b70
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED237 0x5b71
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED238 0x5b72
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED239 0x5b73
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED240 0x5b74
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED241 0x5b75
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED242 0x5b76
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED243 0x5b77
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED244 0x5b78
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED245 0x5b79
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED246 0x5b7a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED247 0x5b7b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED248 0x5b7c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED249 0x5b7d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED250 0x5b7e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED251 0x5b7f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED252 0x5b80
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED253 0x5b81
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED254 0x5b82
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED255 0x5b83
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED256 0x5b84
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED257 0x5b85
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED258 0x5b86
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED259 0x5b87
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED260 0x5b88
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED261 0x5b89
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED262 0x5b8a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED263 0x5b8b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED264 0x5b8c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED265 0x5b8d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED266 0x5b8e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED267 0x5b8f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED268 0x5b90
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED269 0x5b91
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED270 0x5b92
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED271 0x5b93
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED272 0x5b94
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED273 0x5b95
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED274 0x5b96
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED275 0x5b97
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED276 0x5b98
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED277 0x5b99
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED278 0x5b9a
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED279 0x5b9b
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED280 0x5b9c
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED281 0x5b9d
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED282 0x5b9e
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED283 0x5b9f
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED284 0x5ba0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED285 0x5ba1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED286 0x5ba2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED287 0x5ba3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED288 0x5ba4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED289 0x5ba5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED290 0x5ba6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED291 0x5ba7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED292 0x5ba8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED293 0x5ba9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED294 0x5baa
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED295 0x5bab
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED296 0x5bac
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED297 0x5bad
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED298 0x5bae
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED299 0x5baf
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED300 0x5bb0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED301 0x5bb1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED302 0x5bb2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED303 0x5bb3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED304 0x5bb4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED305 0x5bb5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED306 0x5bb6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED307 0x5bb7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED308 0x5bb8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED309 0x5bb9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED310 0x5bba
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED311 0x5bbb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED312 0x5bbc
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED313 0x5bbd
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED314 0x5bbe
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED315 0x5bbf
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED316 0x5bc0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED317 0x5bc1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED318 0x5bc2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED319 0x5bc3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED320 0x5bc4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED321 0x5bc5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED322 0x5bc6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED323 0x5bc7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED324 0x5bc8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED325 0x5bc9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED326 0x5bca
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED327 0x5bcb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED328 0x5bcc
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED329 0x5bcd
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED330 0x5bce
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED331 0x5bcf
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED332 0x5bd0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED333 0x5bd1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED334 0x5bd2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED335 0x5bd3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED336 0x5bd4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED337 0x5bd5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED338 0x5bd6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED339 0x5bd7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED340 0x5bd8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED341 0x5bd9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED342 0x5bda
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED343 0x5bdb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED344 0x5bdc
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED345 0x5bdd
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED346 0x5bde
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED347 0x5bdf
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED348 0x5be0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED349 0x5be1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED350 0x5be2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED351 0x5be3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED352 0x5be4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED353 0x5be5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED354 0x5be6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED355 0x5be7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED356 0x5be8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED357 0x5be9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED358 0x5bea
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED359 0x5beb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED360 0x5bec
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED361 0x5bed
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED362 0x5bee
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED363 0x5bef
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED364 0x5bf0
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED365 0x5bf1
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED366 0x5bf2
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED367 0x5bf3
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED368 0x5bf4
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED369 0x5bf5
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED370 0x5bf6
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED371 0x5bf7
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED372 0x5bf8
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED373 0x5bf9
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED374 0x5bfa
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED375 0x5bfb
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED376 0x5bfc
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED377 0x5bfd
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED378 0x5bfe
+#define mmDCRX_PHY_MACRO_CNTL_RESERVED379 0x5bff
+#define mmDPHY_MACRO_CNTL_RESERVED0 0x5d98
+#define mmDPHY_MACRO_CNTL_RESERVED1 0x5d99
+#define mmDPHY_MACRO_CNTL_RESERVED2 0x5d9a
+#define mmDPHY_MACRO_CNTL_RESERVED3 0x5d9b
+#define mmDPHY_MACRO_CNTL_RESERVED4 0x5d9c
+#define mmDPHY_MACRO_CNTL_RESERVED5 0x5d9d
+#define mmDPHY_MACRO_CNTL_RESERVED6 0x5d9e
+#define mmDPHY_MACRO_CNTL_RESERVED7 0x5d9f
+#define mmDPHY_MACRO_CNTL_RESERVED8 0x5da0
+#define mmDPHY_MACRO_CNTL_RESERVED9 0x5da1
+#define mmDPHY_MACRO_CNTL_RESERVED10 0x5da2
+#define mmDPHY_MACRO_CNTL_RESERVED11 0x5da3
+#define mmDPHY_MACRO_CNTL_RESERVED12 0x5da4
+#define mmDPHY_MACRO_CNTL_RESERVED13 0x5da5
+#define mmDPHY_MACRO_CNTL_RESERVED14 0x5da6
+#define mmDPHY_MACRO_CNTL_RESERVED15 0x5da7
+#define mmDPHY_MACRO_CNTL_RESERVED16 0x5da8
+#define mmDPHY_MACRO_CNTL_RESERVED17 0x5da9
+#define mmDPHY_MACRO_CNTL_RESERVED18 0x5daa
+#define mmDPHY_MACRO_CNTL_RESERVED19 0x5dab
+#define mmDPHY_MACRO_CNTL_RESERVED20 0x5dac
+#define mmDPHY_MACRO_CNTL_RESERVED21 0x5dad
+#define mmDPHY_MACRO_CNTL_RESERVED22 0x5dae
+#define mmDPHY_MACRO_CNTL_RESERVED23 0x5daf
+#define mmDPHY_MACRO_CNTL_RESERVED24 0x5db0
+#define mmDPHY_MACRO_CNTL_RESERVED25 0x5db1
+#define mmDPHY_MACRO_CNTL_RESERVED26 0x5db2
+#define mmDPHY_MACRO_CNTL_RESERVED27 0x5db3
+#define mmDPHY_MACRO_CNTL_RESERVED28 0x5db4
+#define mmDPHY_MACRO_CNTL_RESERVED29 0x5db5
+#define mmDPHY_MACRO_CNTL_RESERVED30 0x5db6
+#define mmDPHY_MACRO_CNTL_RESERVED31 0x5db7
+#define mmDPHY_MACRO_CNTL_RESERVED32 0x5db8
+#define mmDPHY_MACRO_CNTL_RESERVED33 0x5db9
+#define mmDPHY_MACRO_CNTL_RESERVED34 0x5dba
+#define mmDPHY_MACRO_CNTL_RESERVED35 0x5dbb
+#define mmDPHY_MACRO_CNTL_RESERVED36 0x5dbc
+#define mmDPHY_MACRO_CNTL_RESERVED37 0x5dbd
+#define mmDPHY_MACRO_CNTL_RESERVED38 0x5dbe
+#define mmDPHY_MACRO_CNTL_RESERVED39 0x5dbf
+#define mmDPHY_MACRO_CNTL_RESERVED40 0x5dc0
+#define mmDPHY_MACRO_CNTL_RESERVED41 0x5dc1
+#define mmDPHY_MACRO_CNTL_RESERVED42 0x5dc2
+#define mmDPHY_MACRO_CNTL_RESERVED43 0x5dc3
+#define mmDPHY_MACRO_CNTL_RESERVED44 0x5dc4
+#define mmDPHY_MACRO_CNTL_RESERVED45 0x5dc5
+#define mmDPHY_MACRO_CNTL_RESERVED46 0x5dc6
+#define mmDPHY_MACRO_CNTL_RESERVED47 0x5dc7
+#define mmDPHY_MACRO_CNTL_RESERVED48 0x5dc8
+#define mmDPHY_MACRO_CNTL_RESERVED49 0x5dc9
+#define mmDPHY_MACRO_CNTL_RESERVED50 0x5dca
+#define mmDPHY_MACRO_CNTL_RESERVED51 0x5dcb
+#define mmDPHY_MACRO_CNTL_RESERVED52 0x5dcc
+#define mmDPHY_MACRO_CNTL_RESERVED53 0x5dcd
+#define mmDPHY_MACRO_CNTL_RESERVED54 0x5dce
+#define mmDPHY_MACRO_CNTL_RESERVED55 0x5dcf
+#define mmDPHY_MACRO_CNTL_RESERVED56 0x5dd0
+#define mmDPHY_MACRO_CNTL_RESERVED57 0x5dd1
+#define mmDPHY_MACRO_CNTL_RESERVED58 0x5dd2
+#define mmDPHY_MACRO_CNTL_RESERVED59 0x5dd3
+#define mmDPHY_MACRO_CNTL_RESERVED60 0x5dd4
+#define mmDPHY_MACRO_CNTL_RESERVED61 0x5dd5
+#define mmDPHY_MACRO_CNTL_RESERVED62 0x5dd6
+#define mmDPHY_MACRO_CNTL_RESERVED63 0x5dd7
+#define mmGRPH_ENABLE 0x1a00
+#define mmDCP0_GRPH_ENABLE 0x1a00
+#define mmDCP1_GRPH_ENABLE 0x1c00
+#define mmDCP2_GRPH_ENABLE 0x1e00
+#define mmDCP3_GRPH_ENABLE 0x4000
+#define mmDCP4_GRPH_ENABLE 0x4200
+#define mmDCP5_GRPH_ENABLE 0x4400
+#define mmGRPH_CONTROL 0x1a01
+#define mmDCP0_GRPH_CONTROL 0x1a01
+#define mmDCP1_GRPH_CONTROL 0x1c01
+#define mmDCP2_GRPH_CONTROL 0x1e01
+#define mmDCP3_GRPH_CONTROL 0x4001
+#define mmDCP4_GRPH_CONTROL 0x4201
+#define mmDCP5_GRPH_CONTROL 0x4401
+#define mmGRPH_LUT_10BIT_BYPASS 0x1a02
+#define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1a02
+#define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1c02
+#define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x1e02
+#define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4002
+#define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4202
+#define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4402
+#define mmGRPH_SWAP_CNTL 0x1a03
+#define mmDCP0_GRPH_SWAP_CNTL 0x1a03
+#define mmDCP1_GRPH_SWAP_CNTL 0x1c03
+#define mmDCP2_GRPH_SWAP_CNTL 0x1e03
+#define mmDCP3_GRPH_SWAP_CNTL 0x4003
+#define mmDCP4_GRPH_SWAP_CNTL 0x4203
+#define mmDCP5_GRPH_SWAP_CNTL 0x4403
+#define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04
+#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04
+#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1c04
+#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x1e04
+#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004
+#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4204
+#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4404
+#define mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1a05
+#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05
+#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1c05
+#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x1e05
+#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005
+#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4205
+#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4405
+#define mmGRPH_PITCH 0x1a06
+#define mmDCP0_GRPH_PITCH 0x1a06
+#define mmDCP1_GRPH_PITCH 0x1c06
+#define mmDCP2_GRPH_PITCH 0x1e06
+#define mmDCP3_GRPH_PITCH 0x4006
+#define mmDCP4_GRPH_PITCH 0x4206
+#define mmDCP5_GRPH_PITCH 0x4406
+#define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07
+#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07
+#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1c07
+#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1e07
+#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007
+#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4207
+#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4407
+#define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08
+#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08
+#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1c08
+#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1e08
+#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008
+#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4208
+#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4408
+#define mmGRPH_SURFACE_OFFSET_X 0x1a09
+#define mmDCP0_GRPH_SURFACE_OFFSET_X 0x1a09
+#define mmDCP1_GRPH_SURFACE_OFFSET_X 0x1c09
+#define mmDCP2_GRPH_SURFACE_OFFSET_X 0x1e09
+#define mmDCP3_GRPH_SURFACE_OFFSET_X 0x4009
+#define mmDCP4_GRPH_SURFACE_OFFSET_X 0x4209
+#define mmDCP5_GRPH_SURFACE_OFFSET_X 0x4409
+#define mmGRPH_SURFACE_OFFSET_Y 0x1a0a
+#define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1a0a
+#define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1c0a
+#define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x1e0a
+#define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x400a
+#define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x420a
+#define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x440a
+#define mmGRPH_X_START 0x1a0b
+#define mmDCP0_GRPH_X_START 0x1a0b
+#define mmDCP1_GRPH_X_START 0x1c0b
+#define mmDCP2_GRPH_X_START 0x1e0b
+#define mmDCP3_GRPH_X_START 0x400b
+#define mmDCP4_GRPH_X_START 0x420b
+#define mmDCP5_GRPH_X_START 0x440b
+#define mmGRPH_Y_START 0x1a0c
+#define mmDCP0_GRPH_Y_START 0x1a0c
+#define mmDCP1_GRPH_Y_START 0x1c0c
+#define mmDCP2_GRPH_Y_START 0x1e0c
+#define mmDCP3_GRPH_Y_START 0x400c
+#define mmDCP4_GRPH_Y_START 0x420c
+#define mmDCP5_GRPH_Y_START 0x440c
+#define mmGRPH_X_END 0x1a0d
+#define mmDCP0_GRPH_X_END 0x1a0d
+#define mmDCP1_GRPH_X_END 0x1c0d
+#define mmDCP2_GRPH_X_END 0x1e0d
+#define mmDCP3_GRPH_X_END 0x400d
+#define mmDCP4_GRPH_X_END 0x420d
+#define mmDCP5_GRPH_X_END 0x440d
+#define mmGRPH_Y_END 0x1a0e
+#define mmDCP0_GRPH_Y_END 0x1a0e
+#define mmDCP1_GRPH_Y_END 0x1c0e
+#define mmDCP2_GRPH_Y_END 0x1e0e
+#define mmDCP3_GRPH_Y_END 0x400e
+#define mmDCP4_GRPH_Y_END 0x420e
+#define mmDCP5_GRPH_Y_END 0x440e
+#define mmINPUT_GAMMA_CONTROL 0x1a10
+#define mmDCP0_INPUT_GAMMA_CONTROL 0x1a10
+#define mmDCP1_INPUT_GAMMA_CONTROL 0x1c10
+#define mmDCP2_INPUT_GAMMA_CONTROL 0x1e10
+#define mmDCP3_INPUT_GAMMA_CONTROL 0x4010
+#define mmDCP4_INPUT_GAMMA_CONTROL 0x4210
+#define mmDCP5_INPUT_GAMMA_CONTROL 0x4410
+#define mmGRPH_UPDATE 0x1a11
+#define mmDCP0_GRPH_UPDATE 0x1a11
+#define mmDCP1_GRPH_UPDATE 0x1c11
+#define mmDCP2_GRPH_UPDATE 0x1e11
+#define mmDCP3_GRPH_UPDATE 0x4011
+#define mmDCP4_GRPH_UPDATE 0x4211
+#define mmDCP5_GRPH_UPDATE 0x4411
+#define mmGRPH_FLIP_CONTROL 0x1a12
+#define mmDCP0_GRPH_FLIP_CONTROL 0x1a12
+#define mmDCP1_GRPH_FLIP_CONTROL 0x1c12
+#define mmDCP2_GRPH_FLIP_CONTROL 0x1e12
+#define mmDCP3_GRPH_FLIP_CONTROL 0x4012
+#define mmDCP4_GRPH_FLIP_CONTROL 0x4212
+#define mmDCP5_GRPH_FLIP_CONTROL 0x4412
+#define mmGRPH_SURFACE_ADDRESS_INUSE 0x1a13
+#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1a13
+#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1c13
+#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x1e13
+#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4013
+#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4213
+#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4413
+#define mmGRPH_DFQ_CONTROL 0x1a14
+#define mmDCP0_GRPH_DFQ_CONTROL 0x1a14
+#define mmDCP1_GRPH_DFQ_CONTROL 0x1c14
+#define mmDCP2_GRPH_DFQ_CONTROL 0x1e14
+#define mmDCP3_GRPH_DFQ_CONTROL 0x4014
+#define mmDCP4_GRPH_DFQ_CONTROL 0x4214
+#define mmDCP5_GRPH_DFQ_CONTROL 0x4414
+#define mmGRPH_DFQ_STATUS 0x1a15
+#define mmDCP0_GRPH_DFQ_STATUS 0x1a15
+#define mmDCP1_GRPH_DFQ_STATUS 0x1c15
+#define mmDCP2_GRPH_DFQ_STATUS 0x1e15
+#define mmDCP3_GRPH_DFQ_STATUS 0x4015
+#define mmDCP4_GRPH_DFQ_STATUS 0x4215
+#define mmDCP5_GRPH_DFQ_STATUS 0x4415
+#define mmGRPH_INTERRUPT_STATUS 0x1a16
+#define mmDCP0_GRPH_INTERRUPT_STATUS 0x1a16
+#define mmDCP1_GRPH_INTERRUPT_STATUS 0x1c16
+#define mmDCP2_GRPH_INTERRUPT_STATUS 0x1e16
+#define mmDCP3_GRPH_INTERRUPT_STATUS 0x4016
+#define mmDCP4_GRPH_INTERRUPT_STATUS 0x4216
+#define mmDCP5_GRPH_INTERRUPT_STATUS 0x4416
+#define mmGRPH_INTERRUPT_CONTROL 0x1a17
+#define mmDCP0_GRPH_INTERRUPT_CONTROL 0x1a17
+#define mmDCP1_GRPH_INTERRUPT_CONTROL 0x1c17
+#define mmDCP2_GRPH_INTERRUPT_CONTROL 0x1e17
+#define mmDCP3_GRPH_INTERRUPT_CONTROL 0x4017
+#define mmDCP4_GRPH_INTERRUPT_CONTROL 0x4217
+#define mmDCP5_GRPH_INTERRUPT_CONTROL 0x4417
+#define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18
+#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18
+#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1c18
+#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1e18
+#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018
+#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4218
+#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4418
+#define mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1a19
+#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1a19
+#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1c19
+#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x1e19
+#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019
+#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4219
+#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4419
+#define mmGRPH_COMPRESS_PITCH 0x1a1a
+#define mmDCP0_GRPH_COMPRESS_PITCH 0x1a1a
+#define mmDCP1_GRPH_COMPRESS_PITCH 0x1c1a
+#define mmDCP2_GRPH_COMPRESS_PITCH 0x1e1a
+#define mmDCP3_GRPH_COMPRESS_PITCH 0x401a
+#define mmDCP4_GRPH_COMPRESS_PITCH 0x421a
+#define mmDCP5_GRPH_COMPRESS_PITCH 0x441a
+#define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b
+#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b
+#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1c1b
+#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1e1b
+#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401b
+#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x421b
+#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x441b
+#define mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1a1c
+#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1a1c
+#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1c1c
+#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1e1c
+#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x401c
+#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x421c
+#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x441c
+#define mmPRESCALE_GRPH_CONTROL 0x1a2d
+#define mmDCP0_PRESCALE_GRPH_CONTROL 0x1a2d
+#define mmDCP1_PRESCALE_GRPH_CONTROL 0x1c2d
+#define mmDCP2_PRESCALE_GRPH_CONTROL 0x1e2d
+#define mmDCP3_PRESCALE_GRPH_CONTROL 0x402d
+#define mmDCP4_PRESCALE_GRPH_CONTROL 0x422d
+#define mmDCP5_PRESCALE_GRPH_CONTROL 0x442d
+#define mmPRESCALE_VALUES_GRPH_R 0x1a2e
+#define mmDCP0_PRESCALE_VALUES_GRPH_R 0x1a2e
+#define mmDCP1_PRESCALE_VALUES_GRPH_R 0x1c2e
+#define mmDCP2_PRESCALE_VALUES_GRPH_R 0x1e2e
+#define mmDCP3_PRESCALE_VALUES_GRPH_R 0x402e
+#define mmDCP4_PRESCALE_VALUES_GRPH_R 0x422e
+#define mmDCP5_PRESCALE_VALUES_GRPH_R 0x442e
+#define mmPRESCALE_VALUES_GRPH_G 0x1a2f
+#define mmDCP0_PRESCALE_VALUES_GRPH_G 0x1a2f
+#define mmDCP1_PRESCALE_VALUES_GRPH_G 0x1c2f
+#define mmDCP2_PRESCALE_VALUES_GRPH_G 0x1e2f
+#define mmDCP3_PRESCALE_VALUES_GRPH_G 0x402f
+#define mmDCP4_PRESCALE_VALUES_GRPH_G 0x422f
+#define mmDCP5_PRESCALE_VALUES_GRPH_G 0x442f
+#define mmPRESCALE_VALUES_GRPH_B 0x1a30
+#define mmDCP0_PRESCALE_VALUES_GRPH_B 0x1a30
+#define mmDCP1_PRESCALE_VALUES_GRPH_B 0x1c30
+#define mmDCP2_PRESCALE_VALUES_GRPH_B 0x1e30
+#define mmDCP3_PRESCALE_VALUES_GRPH_B 0x4030
+#define mmDCP4_PRESCALE_VALUES_GRPH_B 0x4230
+#define mmDCP5_PRESCALE_VALUES_GRPH_B 0x4430
+#define mmINPUT_CSC_CONTROL 0x1a35
+#define mmDCP0_INPUT_CSC_CONTROL 0x1a35
+#define mmDCP1_INPUT_CSC_CONTROL 0x1c35
+#define mmDCP2_INPUT_CSC_CONTROL 0x1e35
+#define mmDCP3_INPUT_CSC_CONTROL 0x4035
+#define mmDCP4_INPUT_CSC_CONTROL 0x4235
+#define mmDCP5_INPUT_CSC_CONTROL 0x4435
+#define mmINPUT_CSC_C11_C12 0x1a36
+#define mmDCP0_INPUT_CSC_C11_C12 0x1a36
+#define mmDCP1_INPUT_CSC_C11_C12 0x1c36
+#define mmDCP2_INPUT_CSC_C11_C12 0x1e36
+#define mmDCP3_INPUT_CSC_C11_C12 0x4036
+#define mmDCP4_INPUT_CSC_C11_C12 0x4236
+#define mmDCP5_INPUT_CSC_C11_C12 0x4436
+#define mmINPUT_CSC_C13_C14 0x1a37
+#define mmDCP0_INPUT_CSC_C13_C14 0x1a37
+#define mmDCP1_INPUT_CSC_C13_C14 0x1c37
+#define mmDCP2_INPUT_CSC_C13_C14 0x1e37
+#define mmDCP3_INPUT_CSC_C13_C14 0x4037
+#define mmDCP4_INPUT_CSC_C13_C14 0x4237
+#define mmDCP5_INPUT_CSC_C13_C14 0x4437
+#define mmINPUT_CSC_C21_C22 0x1a38
+#define mmDCP0_INPUT_CSC_C21_C22 0x1a38
+#define mmDCP1_INPUT_CSC_C21_C22 0x1c38
+#define mmDCP2_INPUT_CSC_C21_C22 0x1e38
+#define mmDCP3_INPUT_CSC_C21_C22 0x4038
+#define mmDCP4_INPUT_CSC_C21_C22 0x4238
+#define mmDCP5_INPUT_CSC_C21_C22 0x4438
+#define mmINPUT_CSC_C23_C24 0x1a39
+#define mmDCP0_INPUT_CSC_C23_C24 0x1a39
+#define mmDCP1_INPUT_CSC_C23_C24 0x1c39
+#define mmDCP2_INPUT_CSC_C23_C24 0x1e39
+#define mmDCP3_INPUT_CSC_C23_C24 0x4039
+#define mmDCP4_INPUT_CSC_C23_C24 0x4239
+#define mmDCP5_INPUT_CSC_C23_C24 0x4439
+#define mmINPUT_CSC_C31_C32 0x1a3a
+#define mmDCP0_INPUT_CSC_C31_C32 0x1a3a
+#define mmDCP1_INPUT_CSC_C31_C32 0x1c3a
+#define mmDCP2_INPUT_CSC_C31_C32 0x1e3a
+#define mmDCP3_INPUT_CSC_C31_C32 0x403a
+#define mmDCP4_INPUT_CSC_C31_C32 0x423a
+#define mmDCP5_INPUT_CSC_C31_C32 0x443a
+#define mmINPUT_CSC_C33_C34 0x1a3b
+#define mmDCP0_INPUT_CSC_C33_C34 0x1a3b
+#define mmDCP1_INPUT_CSC_C33_C34 0x1c3b
+#define mmDCP2_INPUT_CSC_C33_C34 0x1e3b
+#define mmDCP3_INPUT_CSC_C33_C34 0x403b
+#define mmDCP4_INPUT_CSC_C33_C34 0x423b
+#define mmDCP5_INPUT_CSC_C33_C34 0x443b
+#define mmOUTPUT_CSC_CONTROL 0x1a3c
+#define mmDCP0_OUTPUT_CSC_CONTROL 0x1a3c
+#define mmDCP1_OUTPUT_CSC_CONTROL 0x1c3c
+#define mmDCP2_OUTPUT_CSC_CONTROL 0x1e3c
+#define mmDCP3_OUTPUT_CSC_CONTROL 0x403c
+#define mmDCP4_OUTPUT_CSC_CONTROL 0x423c
+#define mmDCP5_OUTPUT_CSC_CONTROL 0x443c
+#define mmOUTPUT_CSC_C11_C12 0x1a3d
+#define mmDCP0_OUTPUT_CSC_C11_C12 0x1a3d
+#define mmDCP1_OUTPUT_CSC_C11_C12 0x1c3d
+#define mmDCP2_OUTPUT_CSC_C11_C12 0x1e3d
+#define mmDCP3_OUTPUT_CSC_C11_C12 0x403d
+#define mmDCP4_OUTPUT_CSC_C11_C12 0x423d
+#define mmDCP5_OUTPUT_CSC_C11_C12 0x443d
+#define mmOUTPUT_CSC_C13_C14 0x1a3e
+#define mmDCP0_OUTPUT_CSC_C13_C14 0x1a3e
+#define mmDCP1_OUTPUT_CSC_C13_C14 0x1c3e
+#define mmDCP2_OUTPUT_CSC_C13_C14 0x1e3e
+#define mmDCP3_OUTPUT_CSC_C13_C14 0x403e
+#define mmDCP4_OUTPUT_CSC_C13_C14 0x423e
+#define mmDCP5_OUTPUT_CSC_C13_C14 0x443e
+#define mmOUTPUT_CSC_C21_C22 0x1a3f
+#define mmDCP0_OUTPUT_CSC_C21_C22 0x1a3f
+#define mmDCP1_OUTPUT_CSC_C21_C22 0x1c3f
+#define mmDCP2_OUTPUT_CSC_C21_C22 0x1e3f
+#define mmDCP3_OUTPUT_CSC_C21_C22 0x403f
+#define mmDCP4_OUTPUT_CSC_C21_C22 0x423f
+#define mmDCP5_OUTPUT_CSC_C21_C22 0x443f
+#define mmOUTPUT_CSC_C23_C24 0x1a40
+#define mmDCP0_OUTPUT_CSC_C23_C24 0x1a40
+#define mmDCP1_OUTPUT_CSC_C23_C24 0x1c40
+#define mmDCP2_OUTPUT_CSC_C23_C24 0x1e40
+#define mmDCP3_OUTPUT_CSC_C23_C24 0x4040
+#define mmDCP4_OUTPUT_CSC_C23_C24 0x4240
+#define mmDCP5_OUTPUT_CSC_C23_C24 0x4440
+#define mmOUTPUT_CSC_C31_C32 0x1a41
+#define mmDCP0_OUTPUT_CSC_C31_C32 0x1a41
+#define mmDCP1_OUTPUT_CSC_C31_C32 0x1c41
+#define mmDCP2_OUTPUT_CSC_C31_C32 0x1e41
+#define mmDCP3_OUTPUT_CSC_C31_C32 0x4041
+#define mmDCP4_OUTPUT_CSC_C31_C32 0x4241
+#define mmDCP5_OUTPUT_CSC_C31_C32 0x4441
+#define mmOUTPUT_CSC_C33_C34 0x1a42
+#define mmDCP0_OUTPUT_CSC_C33_C34 0x1a42
+#define mmDCP1_OUTPUT_CSC_C33_C34 0x1c42
+#define mmDCP2_OUTPUT_CSC_C33_C34 0x1e42
+#define mmDCP3_OUTPUT_CSC_C33_C34 0x4042
+#define mmDCP4_OUTPUT_CSC_C33_C34 0x4242
+#define mmDCP5_OUTPUT_CSC_C33_C34 0x4442
+#define mmCOMM_MATRIXA_TRANS_C11_C12 0x1a43
+#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1a43
+#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1c43
+#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x1e43
+#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4043
+#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4243
+#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4443
+#define mmCOMM_MATRIXA_TRANS_C13_C14 0x1a44
+#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1a44
+#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1c44
+#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x1e44
+#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4044
+#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4244
+#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4444
+#define mmCOMM_MATRIXA_TRANS_C21_C22 0x1a45
+#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1a45
+#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1c45
+#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x1e45
+#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4045
+#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4245
+#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4445
+#define mmCOMM_MATRIXA_TRANS_C23_C24 0x1a46
+#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1a46
+#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1c46
+#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x1e46
+#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4046
+#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4246
+#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4446
+#define mmCOMM_MATRIXA_TRANS_C31_C32 0x1a47
+#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1a47
+#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1c47
+#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x1e47
+#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4047
+#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4247
+#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4447
+#define mmCOMM_MATRIXA_TRANS_C33_C34 0x1a48
+#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1a48
+#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1c48
+#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x1e48
+#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4048
+#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4248
+#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4448
+#define mmCOMM_MATRIXB_TRANS_C11_C12 0x1a49
+#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1a49
+#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1c49
+#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x1e49
+#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4049
+#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4249
+#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4449
+#define mmCOMM_MATRIXB_TRANS_C13_C14 0x1a4a
+#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1a4a
+#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1c4a
+#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x1e4a
+#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x404a
+#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x424a
+#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x444a
+#define mmCOMM_MATRIXB_TRANS_C21_C22 0x1a4b
+#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1a4b
+#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1c4b
+#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x1e4b
+#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x404b
+#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x424b
+#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x444b
+#define mmCOMM_MATRIXB_TRANS_C23_C24 0x1a4c
+#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1a4c
+#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1c4c
+#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x1e4c
+#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x404c
+#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x424c
+#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x444c
+#define mmCOMM_MATRIXB_TRANS_C31_C32 0x1a4d
+#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1a4d
+#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1c4d
+#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x1e4d
+#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x404d
+#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x424d
+#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x444d
+#define mmCOMM_MATRIXB_TRANS_C33_C34 0x1a4e
+#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1a4e
+#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1c4e
+#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x1e4e
+#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x404e
+#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x424e
+#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x444e
+#define mmDENORM_CONTROL 0x1a50
+#define mmDCP0_DENORM_CONTROL 0x1a50
+#define mmDCP1_DENORM_CONTROL 0x1c50
+#define mmDCP2_DENORM_CONTROL 0x1e50
+#define mmDCP3_DENORM_CONTROL 0x4050
+#define mmDCP4_DENORM_CONTROL 0x4250
+#define mmDCP5_DENORM_CONTROL 0x4450
+#define mmOUT_ROUND_CONTROL 0x1a51
+#define mmDCP0_OUT_ROUND_CONTROL 0x1a51
+#define mmDCP1_OUT_ROUND_CONTROL 0x1c51
+#define mmDCP2_OUT_ROUND_CONTROL 0x1e51
+#define mmDCP3_OUT_ROUND_CONTROL 0x4051
+#define mmDCP4_OUT_ROUND_CONTROL 0x4251
+#define mmDCP5_OUT_ROUND_CONTROL 0x4451
+#define mmOUT_CLAMP_CONTROL_R_CR 0x1a52
+#define mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x1a52
+#define mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x1c52
+#define mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x1e52
+#define mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x4052
+#define mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x4252
+#define mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x4452
+#define mmOUT_CLAMP_CONTROL_G_Y 0x1a9c
+#define mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x1a9c
+#define mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x1c9c
+#define mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x1e9c
+#define mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x409c
+#define mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x429c
+#define mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x449c
+#define mmOUT_CLAMP_CONTROL_B_CB 0x1a9d
+#define mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x1a9d
+#define mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x1c9d
+#define mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x1e9d
+#define mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x409d
+#define mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x429d
+#define mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x449d
+#define mmKEY_CONTROL 0x1a53
+#define mmDCP0_KEY_CONTROL 0x1a53
+#define mmDCP1_KEY_CONTROL 0x1c53
+#define mmDCP2_KEY_CONTROL 0x1e53
+#define mmDCP3_KEY_CONTROL 0x4053
+#define mmDCP4_KEY_CONTROL 0x4253
+#define mmDCP5_KEY_CONTROL 0x4453
+#define mmKEY_RANGE_ALPHA 0x1a54
+#define mmDCP0_KEY_RANGE_ALPHA 0x1a54
+#define mmDCP1_KEY_RANGE_ALPHA 0x1c54
+#define mmDCP2_KEY_RANGE_ALPHA 0x1e54
+#define mmDCP3_KEY_RANGE_ALPHA 0x4054
+#define mmDCP4_KEY_RANGE_ALPHA 0x4254
+#define mmDCP5_KEY_RANGE_ALPHA 0x4454
+#define mmKEY_RANGE_RED 0x1a55
+#define mmDCP0_KEY_RANGE_RED 0x1a55
+#define mmDCP1_KEY_RANGE_RED 0x1c55
+#define mmDCP2_KEY_RANGE_RED 0x1e55
+#define mmDCP3_KEY_RANGE_RED 0x4055
+#define mmDCP4_KEY_RANGE_RED 0x4255
+#define mmDCP5_KEY_RANGE_RED 0x4455
+#define mmKEY_RANGE_GREEN 0x1a56
+#define mmDCP0_KEY_RANGE_GREEN 0x1a56
+#define mmDCP1_KEY_RANGE_GREEN 0x1c56
+#define mmDCP2_KEY_RANGE_GREEN 0x1e56
+#define mmDCP3_KEY_RANGE_GREEN 0x4056
+#define mmDCP4_KEY_RANGE_GREEN 0x4256
+#define mmDCP5_KEY_RANGE_GREEN 0x4456
+#define mmKEY_RANGE_BLUE 0x1a57
+#define mmDCP0_KEY_RANGE_BLUE 0x1a57
+#define mmDCP1_KEY_RANGE_BLUE 0x1c57
+#define mmDCP2_KEY_RANGE_BLUE 0x1e57
+#define mmDCP3_KEY_RANGE_BLUE 0x4057
+#define mmDCP4_KEY_RANGE_BLUE 0x4257
+#define mmDCP5_KEY_RANGE_BLUE 0x4457
+#define mmDEGAMMA_CONTROL 0x1a58
+#define mmDCP0_DEGAMMA_CONTROL 0x1a58
+#define mmDCP1_DEGAMMA_CONTROL 0x1c58
+#define mmDCP2_DEGAMMA_CONTROL 0x1e58
+#define mmDCP3_DEGAMMA_CONTROL 0x4058
+#define mmDCP4_DEGAMMA_CONTROL 0x4258
+#define mmDCP5_DEGAMMA_CONTROL 0x4458
+#define mmGAMUT_REMAP_CONTROL 0x1a59
+#define mmDCP0_GAMUT_REMAP_CONTROL 0x1a59
+#define mmDCP1_GAMUT_REMAP_CONTROL 0x1c59
+#define mmDCP2_GAMUT_REMAP_CONTROL 0x1e59
+#define mmDCP3_GAMUT_REMAP_CONTROL 0x4059
+#define mmDCP4_GAMUT_REMAP_CONTROL 0x4259
+#define mmDCP5_GAMUT_REMAP_CONTROL 0x4459
+#define mmGAMUT_REMAP_C11_C12 0x1a5a
+#define mmDCP0_GAMUT_REMAP_C11_C12 0x1a5a
+#define mmDCP1_GAMUT_REMAP_C11_C12 0x1c5a
+#define mmDCP2_GAMUT_REMAP_C11_C12 0x1e5a
+#define mmDCP3_GAMUT_REMAP_C11_C12 0x405a
+#define mmDCP4_GAMUT_REMAP_C11_C12 0x425a
+#define mmDCP5_GAMUT_REMAP_C11_C12 0x445a
+#define mmGAMUT_REMAP_C13_C14 0x1a5b
+#define mmDCP0_GAMUT_REMAP_C13_C14 0x1a5b
+#define mmDCP1_GAMUT_REMAP_C13_C14 0x1c5b
+#define mmDCP2_GAMUT_REMAP_C13_C14 0x1e5b
+#define mmDCP3_GAMUT_REMAP_C13_C14 0x405b
+#define mmDCP4_GAMUT_REMAP_C13_C14 0x425b
+#define mmDCP5_GAMUT_REMAP_C13_C14 0x445b
+#define mmGAMUT_REMAP_C21_C22 0x1a5c
+#define mmDCP0_GAMUT_REMAP_C21_C22 0x1a5c
+#define mmDCP1_GAMUT_REMAP_C21_C22 0x1c5c
+#define mmDCP2_GAMUT_REMAP_C21_C22 0x1e5c
+#define mmDCP3_GAMUT_REMAP_C21_C22 0x405c
+#define mmDCP4_GAMUT_REMAP_C21_C22 0x425c
+#define mmDCP5_GAMUT_REMAP_C21_C22 0x445c
+#define mmGAMUT_REMAP_C23_C24 0x1a5d
+#define mmDCP0_GAMUT_REMAP_C23_C24 0x1a5d
+#define mmDCP1_GAMUT_REMAP_C23_C24 0x1c5d
+#define mmDCP2_GAMUT_REMAP_C23_C24 0x1e5d
+#define mmDCP3_GAMUT_REMAP_C23_C24 0x405d
+#define mmDCP4_GAMUT_REMAP_C23_C24 0x425d
+#define mmDCP5_GAMUT_REMAP_C23_C24 0x445d
+#define mmGAMUT_REMAP_C31_C32 0x1a5e
+#define mmDCP0_GAMUT_REMAP_C31_C32 0x1a5e
+#define mmDCP1_GAMUT_REMAP_C31_C32 0x1c5e
+#define mmDCP2_GAMUT_REMAP_C31_C32 0x1e5e
+#define mmDCP3_GAMUT_REMAP_C31_C32 0x405e
+#define mmDCP4_GAMUT_REMAP_C31_C32 0x425e
+#define mmDCP5_GAMUT_REMAP_C31_C32 0x445e
+#define mmGAMUT_REMAP_C33_C34 0x1a5f
+#define mmDCP0_GAMUT_REMAP_C33_C34 0x1a5f
+#define mmDCP1_GAMUT_REMAP_C33_C34 0x1c5f
+#define mmDCP2_GAMUT_REMAP_C33_C34 0x1e5f
+#define mmDCP3_GAMUT_REMAP_C33_C34 0x405f
+#define mmDCP4_GAMUT_REMAP_C33_C34 0x425f
+#define mmDCP5_GAMUT_REMAP_C33_C34 0x445f
+#define mmDCP_SPATIAL_DITHER_CNTL 0x1a60
+#define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1a60
+#define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1c60
+#define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x1e60
+#define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4060
+#define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4260
+#define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4460
+#define mmDCP_FP_CONVERTED_FIELD 0x1a65
+#define mmDCP0_DCP_FP_CONVERTED_FIELD 0x1a65
+#define mmDCP1_DCP_FP_CONVERTED_FIELD 0x1c65
+#define mmDCP2_DCP_FP_CONVERTED_FIELD 0x1e65
+#define mmDCP3_DCP_FP_CONVERTED_FIELD 0x4065
+#define mmDCP4_DCP_FP_CONVERTED_FIELD 0x4265
+#define mmDCP5_DCP_FP_CONVERTED_FIELD 0x4465
+#define mmCUR_CONTROL 0x1a66
+#define mmDCP0_CUR_CONTROL 0x1a66
+#define mmDCP1_CUR_CONTROL 0x1c66
+#define mmDCP2_CUR_CONTROL 0x1e66
+#define mmDCP3_CUR_CONTROL 0x4066
+#define mmDCP4_CUR_CONTROL 0x4266
+#define mmDCP5_CUR_CONTROL 0x4466
+#define mmCUR_SURFACE_ADDRESS 0x1a67
+#define mmDCP0_CUR_SURFACE_ADDRESS 0x1a67
+#define mmDCP1_CUR_SURFACE_ADDRESS 0x1c67
+#define mmDCP2_CUR_SURFACE_ADDRESS 0x1e67
+#define mmDCP3_CUR_SURFACE_ADDRESS 0x4067
+#define mmDCP4_CUR_SURFACE_ADDRESS 0x4267
+#define mmDCP5_CUR_SURFACE_ADDRESS 0x4467
+#define mmCUR_SIZE 0x1a68
+#define mmDCP0_CUR_SIZE 0x1a68
+#define mmDCP1_CUR_SIZE 0x1c68
+#define mmDCP2_CUR_SIZE 0x1e68
+#define mmDCP3_CUR_SIZE 0x4068
+#define mmDCP4_CUR_SIZE 0x4268
+#define mmDCP5_CUR_SIZE 0x4468
+#define mmCUR_SURFACE_ADDRESS_HIGH 0x1a69
+#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1a69
+#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1c69
+#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x1e69
+#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4069
+#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4269
+#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4469
+#define mmCUR_POSITION 0x1a6a
+#define mmDCP0_CUR_POSITION 0x1a6a
+#define mmDCP1_CUR_POSITION 0x1c6a
+#define mmDCP2_CUR_POSITION 0x1e6a
+#define mmDCP3_CUR_POSITION 0x406a
+#define mmDCP4_CUR_POSITION 0x426a
+#define mmDCP5_CUR_POSITION 0x446a
+#define mmCUR_HOT_SPOT 0x1a6b
+#define mmDCP0_CUR_HOT_SPOT 0x1a6b
+#define mmDCP1_CUR_HOT_SPOT 0x1c6b
+#define mmDCP2_CUR_HOT_SPOT 0x1e6b
+#define mmDCP3_CUR_HOT_SPOT 0x406b
+#define mmDCP4_CUR_HOT_SPOT 0x426b
+#define mmDCP5_CUR_HOT_SPOT 0x446b
+#define mmCUR_COLOR1 0x1a6c
+#define mmDCP0_CUR_COLOR1 0x1a6c
+#define mmDCP1_CUR_COLOR1 0x1c6c
+#define mmDCP2_CUR_COLOR1 0x1e6c
+#define mmDCP3_CUR_COLOR1 0x406c
+#define mmDCP4_CUR_COLOR1 0x426c
+#define mmDCP5_CUR_COLOR1 0x446c
+#define mmCUR_COLOR2 0x1a6d
+#define mmDCP0_CUR_COLOR2 0x1a6d
+#define mmDCP1_CUR_COLOR2 0x1c6d
+#define mmDCP2_CUR_COLOR2 0x1e6d
+#define mmDCP3_CUR_COLOR2 0x406d
+#define mmDCP4_CUR_COLOR2 0x426d
+#define mmDCP5_CUR_COLOR2 0x446d
+#define mmCUR_UPDATE 0x1a6e
+#define mmDCP0_CUR_UPDATE 0x1a6e
+#define mmDCP1_CUR_UPDATE 0x1c6e
+#define mmDCP2_CUR_UPDATE 0x1e6e
+#define mmDCP3_CUR_UPDATE 0x406e
+#define mmDCP4_CUR_UPDATE 0x426e
+#define mmDCP5_CUR_UPDATE 0x446e
+#define mmCUR_REQUEST_FILTER_CNTL 0x1a99
+#define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1a99
+#define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1c99
+#define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x1e99
+#define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4099
+#define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4299
+#define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4499
+#define mmCUR_STEREO_CONTROL 0x1a9a
+#define mmDCP0_CUR_STEREO_CONTROL 0x1a9a
+#define mmDCP1_CUR_STEREO_CONTROL 0x1c9a
+#define mmDCP2_CUR_STEREO_CONTROL 0x1e9a
+#define mmDCP3_CUR_STEREO_CONTROL 0x409a
+#define mmDCP4_CUR_STEREO_CONTROL 0x429a
+#define mmDCP5_CUR_STEREO_CONTROL 0x449a
+#define mmDC_LUT_RW_MODE 0x1a78
+#define mmDCP0_DC_LUT_RW_MODE 0x1a78
+#define mmDCP1_DC_LUT_RW_MODE 0x1c78
+#define mmDCP2_DC_LUT_RW_MODE 0x1e78
+#define mmDCP3_DC_LUT_RW_MODE 0x4078
+#define mmDCP4_DC_LUT_RW_MODE 0x4278
+#define mmDCP5_DC_LUT_RW_MODE 0x4478
+#define mmDC_LUT_RW_INDEX 0x1a79
+#define mmDCP0_DC_LUT_RW_INDEX 0x1a79
+#define mmDCP1_DC_LUT_RW_INDEX 0x1c79
+#define mmDCP2_DC_LUT_RW_INDEX 0x1e79
+#define mmDCP3_DC_LUT_RW_INDEX 0x4079
+#define mmDCP4_DC_LUT_RW_INDEX 0x4279
+#define mmDCP5_DC_LUT_RW_INDEX 0x4479
+#define mmDC_LUT_SEQ_COLOR 0x1a7a
+#define mmDCP0_DC_LUT_SEQ_COLOR 0x1a7a
+#define mmDCP1_DC_LUT_SEQ_COLOR 0x1c7a
+#define mmDCP2_DC_LUT_SEQ_COLOR 0x1e7a
+#define mmDCP3_DC_LUT_SEQ_COLOR 0x407a
+#define mmDCP4_DC_LUT_SEQ_COLOR 0x427a
+#define mmDCP5_DC_LUT_SEQ_COLOR 0x447a
+#define mmDC_LUT_PWL_DATA 0x1a7b
+#define mmDCP0_DC_LUT_PWL_DATA 0x1a7b
+#define mmDCP1_DC_LUT_PWL_DATA 0x1c7b
+#define mmDCP2_DC_LUT_PWL_DATA 0x1e7b
+#define mmDCP3_DC_LUT_PWL_DATA 0x407b
+#define mmDCP4_DC_LUT_PWL_DATA 0x427b
+#define mmDCP5_DC_LUT_PWL_DATA 0x447b
+#define mmDC_LUT_30_COLOR 0x1a7c
+#define mmDCP0_DC_LUT_30_COLOR 0x1a7c
+#define mmDCP1_DC_LUT_30_COLOR 0x1c7c
+#define mmDCP2_DC_LUT_30_COLOR 0x1e7c
+#define mmDCP3_DC_LUT_30_COLOR 0x407c
+#define mmDCP4_DC_LUT_30_COLOR 0x427c
+#define mmDCP5_DC_LUT_30_COLOR 0x447c
+#define mmDC_LUT_VGA_ACCESS_ENABLE 0x1a7d
+#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1a7d
+#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1c7d
+#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x1e7d
+#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x407d
+#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x427d
+#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x447d
+#define mmDC_LUT_WRITE_EN_MASK 0x1a7e
+#define mmDCP0_DC_LUT_WRITE_EN_MASK 0x1a7e
+#define mmDCP1_DC_LUT_WRITE_EN_MASK 0x1c7e
+#define mmDCP2_DC_LUT_WRITE_EN_MASK 0x1e7e
+#define mmDCP3_DC_LUT_WRITE_EN_MASK 0x407e
+#define mmDCP4_DC_LUT_WRITE_EN_MASK 0x427e
+#define mmDCP5_DC_LUT_WRITE_EN_MASK 0x447e
+#define mmDC_LUT_AUTOFILL 0x1a7f
+#define mmDCP0_DC_LUT_AUTOFILL 0x1a7f
+#define mmDCP1_DC_LUT_AUTOFILL 0x1c7f
+#define mmDCP2_DC_LUT_AUTOFILL 0x1e7f
+#define mmDCP3_DC_LUT_AUTOFILL 0x407f
+#define mmDCP4_DC_LUT_AUTOFILL 0x427f
+#define mmDCP5_DC_LUT_AUTOFILL 0x447f
+#define mmDC_LUT_CONTROL 0x1a80
+#define mmDCP0_DC_LUT_CONTROL 0x1a80
+#define mmDCP1_DC_LUT_CONTROL 0x1c80
+#define mmDCP2_DC_LUT_CONTROL 0x1e80
+#define mmDCP3_DC_LUT_CONTROL 0x4080
+#define mmDCP4_DC_LUT_CONTROL 0x4280
+#define mmDCP5_DC_LUT_CONTROL 0x4480
+#define mmDC_LUT_BLACK_OFFSET_BLUE 0x1a81
+#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1a81
+#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1c81
+#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x1e81
+#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4081
+#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4281
+#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4481
+#define mmDC_LUT_BLACK_OFFSET_GREEN 0x1a82
+#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1a82
+#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1c82
+#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x1e82
+#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4082
+#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4282
+#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4482
+#define mmDC_LUT_BLACK_OFFSET_RED 0x1a83
+#define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1a83
+#define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1c83
+#define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x1e83
+#define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4083
+#define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4283
+#define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4483
+#define mmDC_LUT_WHITE_OFFSET_BLUE 0x1a84
+#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1a84
+#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1c84
+#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x1e84
+#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4084
+#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4284
+#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4484
+#define mmDC_LUT_WHITE_OFFSET_GREEN 0x1a85
+#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1a85
+#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1c85
+#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x1e85
+#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4085
+#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4285
+#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4485
+#define mmDC_LUT_WHITE_OFFSET_RED 0x1a86
+#define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1a86
+#define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1c86
+#define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x1e86
+#define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4086
+#define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4286
+#define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4486
+#define mmDCP_CRC_CONTROL 0x1a87
+#define mmDCP0_DCP_CRC_CONTROL 0x1a87
+#define mmDCP1_DCP_CRC_CONTROL 0x1c87
+#define mmDCP2_DCP_CRC_CONTROL 0x1e87
+#define mmDCP3_DCP_CRC_CONTROL 0x4087
+#define mmDCP4_DCP_CRC_CONTROL 0x4287
+#define mmDCP5_DCP_CRC_CONTROL 0x4487
+#define mmDCP_CRC_MASK 0x1a88
+#define mmDCP0_DCP_CRC_MASK 0x1a88
+#define mmDCP1_DCP_CRC_MASK 0x1c88
+#define mmDCP2_DCP_CRC_MASK 0x1e88
+#define mmDCP3_DCP_CRC_MASK 0x4088
+#define mmDCP4_DCP_CRC_MASK 0x4288
+#define mmDCP5_DCP_CRC_MASK 0x4488
+#define mmDCP_CRC_CURRENT 0x1a89
+#define mmDCP0_DCP_CRC_CURRENT 0x1a89
+#define mmDCP1_DCP_CRC_CURRENT 0x1c89
+#define mmDCP2_DCP_CRC_CURRENT 0x1e89
+#define mmDCP3_DCP_CRC_CURRENT 0x4089
+#define mmDCP4_DCP_CRC_CURRENT 0x4289
+#define mmDCP5_DCP_CRC_CURRENT 0x4489
+#define mmDVMM_PTE_CONTROL 0x1a8a
+#define mmDCP0_DVMM_PTE_CONTROL 0x1a8a
+#define mmDCP1_DVMM_PTE_CONTROL 0x1c8a
+#define mmDCP2_DVMM_PTE_CONTROL 0x1e8a
+#define mmDCP3_DVMM_PTE_CONTROL 0x408a
+#define mmDCP4_DVMM_PTE_CONTROL 0x428a
+#define mmDCP5_DVMM_PTE_CONTROL 0x448a
+#define mmDCP_CRC_LAST 0x1a8b
+#define mmDCP0_DCP_CRC_LAST 0x1a8b
+#define mmDCP1_DCP_CRC_LAST 0x1c8b
+#define mmDCP2_DCP_CRC_LAST 0x1e8b
+#define mmDCP3_DCP_CRC_LAST 0x408b
+#define mmDCP4_DCP_CRC_LAST 0x428b
+#define mmDCP5_DCP_CRC_LAST 0x448b
+#define mmDVMM_PTE_ARB_CONTROL 0x1a8c
+#define mmDCP0_DVMM_PTE_ARB_CONTROL 0x1a8c
+#define mmDCP1_DVMM_PTE_ARB_CONTROL 0x1c8c
+#define mmDCP2_DVMM_PTE_ARB_CONTROL 0x1e8c
+#define mmDCP3_DVMM_PTE_ARB_CONTROL 0x408c
+#define mmDCP4_DVMM_PTE_ARB_CONTROL 0x428c
+#define mmDCP5_DVMM_PTE_ARB_CONTROL 0x448c
+#define mmDCP_DEBUG 0x1a8d
+#define mmDCP0_DCP_DEBUG 0x1a8d
+#define mmDCP1_DCP_DEBUG 0x1c8d
+#define mmDCP2_DCP_DEBUG 0x1e8d
+#define mmDCP3_DCP_DEBUG 0x408d
+#define mmDCP4_DCP_DEBUG 0x428d
+#define mmDCP5_DCP_DEBUG 0x448d
+#define mmGRPH_FLIP_RATE_CNTL 0x1a8e
+#define mmDCP0_GRPH_FLIP_RATE_CNTL 0x1a8e
+#define mmDCP1_GRPH_FLIP_RATE_CNTL 0x1c8e
+#define mmDCP2_GRPH_FLIP_RATE_CNTL 0x1e8e
+#define mmDCP3_GRPH_FLIP_RATE_CNTL 0x408e
+#define mmDCP4_GRPH_FLIP_RATE_CNTL 0x428e
+#define mmDCP5_GRPH_FLIP_RATE_CNTL 0x448e
+#define mmDCP_GSL_CONTROL 0x1a90
+#define mmDCP0_DCP_GSL_CONTROL 0x1a90
+#define mmDCP1_DCP_GSL_CONTROL 0x1c90
+#define mmDCP2_DCP_GSL_CONTROL 0x1e90
+#define mmDCP3_DCP_GSL_CONTROL 0x4090
+#define mmDCP4_DCP_GSL_CONTROL 0x4290
+#define mmDCP5_DCP_GSL_CONTROL 0x4490
+#define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91
+#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91
+#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1c91
+#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1e91
+#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091
+#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4291
+#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4491
+#define mmDCP_DEBUG_SG 0x1a92
+#define mmDCP0_DCP_DEBUG_SG 0x1a92
+#define mmDCP1_DCP_DEBUG_SG 0x1c92
+#define mmDCP2_DCP_DEBUG_SG 0x1e92
+#define mmDCP3_DCP_DEBUG_SG 0x4092
+#define mmDCP4_DCP_DEBUG_SG 0x4292
+#define mmDCP5_DCP_DEBUG_SG 0x4492
+#define mmDCP_DEBUG_SG2 0x1a94
+#define mmDCP0_DCP_DEBUG_SG2 0x1a94
+#define mmDCP1_DCP_DEBUG_SG2 0x1c94
+#define mmDCP2_DCP_DEBUG_SG2 0x1e94
+#define mmDCP3_DCP_DEBUG_SG2 0x4094
+#define mmDCP4_DCP_DEBUG_SG2 0x4294
+#define mmDCP5_DCP_DEBUG_SG2 0x4494
+#define mmDCP_DVMM_DEBUG 0x1a93
+#define mmDCP0_DCP_DVMM_DEBUG 0x1a93
+#define mmDCP1_DCP_DVMM_DEBUG 0x1c93
+#define mmDCP2_DCP_DVMM_DEBUG 0x1e93
+#define mmDCP3_DCP_DVMM_DEBUG 0x4093
+#define mmDCP4_DCP_DVMM_DEBUG 0x4293
+#define mmDCP5_DCP_DVMM_DEBUG 0x4493
+#define mmDCP_TEST_DEBUG_INDEX 0x1a95
+#define mmDCP0_DCP_TEST_DEBUG_INDEX 0x1a95
+#define mmDCP1_DCP_TEST_DEBUG_INDEX 0x1c95
+#define mmDCP2_DCP_TEST_DEBUG_INDEX 0x1e95
+#define mmDCP3_DCP_TEST_DEBUG_INDEX 0x4095
+#define mmDCP4_DCP_TEST_DEBUG_INDEX 0x4295
+#define mmDCP5_DCP_TEST_DEBUG_INDEX 0x4495
+#define mmDCP_TEST_DEBUG_DATA 0x1a96
+#define mmDCP0_DCP_TEST_DEBUG_DATA 0x1a96
+#define mmDCP1_DCP_TEST_DEBUG_DATA 0x1c96
+#define mmDCP2_DCP_TEST_DEBUG_DATA 0x1e96
+#define mmDCP3_DCP_TEST_DEBUG_DATA 0x4096
+#define mmDCP4_DCP_TEST_DEBUG_DATA 0x4296
+#define mmDCP5_DCP_TEST_DEBUG_DATA 0x4496
+#define mmGRPH_STEREOSYNC_FLIP 0x1a97
+#define mmDCP0_GRPH_STEREOSYNC_FLIP 0x1a97
+#define mmDCP1_GRPH_STEREOSYNC_FLIP 0x1c97
+#define mmDCP2_GRPH_STEREOSYNC_FLIP 0x1e97
+#define mmDCP3_GRPH_STEREOSYNC_FLIP 0x4097
+#define mmDCP4_GRPH_STEREOSYNC_FLIP 0x4297
+#define mmDCP5_GRPH_STEREOSYNC_FLIP 0x4497
+#define mmDCP_DEBUG2 0x1a98
+#define mmDCP0_DCP_DEBUG2 0x1a98
+#define mmDCP1_DCP_DEBUG2 0x1c98
+#define mmDCP2_DCP_DEBUG2 0x1e98
+#define mmDCP3_DCP_DEBUG2 0x4098
+#define mmDCP4_DCP_DEBUG2 0x4298
+#define mmDCP5_DCP_DEBUG2 0x4498
+#define mmHW_ROTATION 0x1a9e
+#define mmDCP0_HW_ROTATION 0x1a9e
+#define mmDCP1_HW_ROTATION 0x1c9e
+#define mmDCP2_HW_ROTATION 0x1e9e
+#define mmDCP3_HW_ROTATION 0x409e
+#define mmDCP4_HW_ROTATION 0x429e
+#define mmDCP5_HW_ROTATION 0x449e
+#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f
+#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f
+#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1c9f
+#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1e9f
+#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x409f
+#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x429f
+#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x449f
+#define mmREGAMMA_CONTROL 0x1aa0
+#define mmDCP0_REGAMMA_CONTROL 0x1aa0
+#define mmDCP1_REGAMMA_CONTROL 0x1ca0
+#define mmDCP2_REGAMMA_CONTROL 0x1ea0
+#define mmDCP3_REGAMMA_CONTROL 0x40a0
+#define mmDCP4_REGAMMA_CONTROL 0x42a0
+#define mmDCP5_REGAMMA_CONTROL 0x44a0
+#define mmREGAMMA_LUT_INDEX 0x1aa1
+#define mmDCP0_REGAMMA_LUT_INDEX 0x1aa1
+#define mmDCP1_REGAMMA_LUT_INDEX 0x1ca1
+#define mmDCP2_REGAMMA_LUT_INDEX 0x1ea1
+#define mmDCP3_REGAMMA_LUT_INDEX 0x40a1
+#define mmDCP4_REGAMMA_LUT_INDEX 0x42a1
+#define mmDCP5_REGAMMA_LUT_INDEX 0x44a1
+#define mmREGAMMA_LUT_DATA 0x1aa2
+#define mmDCP0_REGAMMA_LUT_DATA 0x1aa2
+#define mmDCP1_REGAMMA_LUT_DATA 0x1ca2
+#define mmDCP2_REGAMMA_LUT_DATA 0x1ea2
+#define mmDCP3_REGAMMA_LUT_DATA 0x40a2
+#define mmDCP4_REGAMMA_LUT_DATA 0x42a2
+#define mmDCP5_REGAMMA_LUT_DATA 0x44a2
+#define mmREGAMMA_LUT_WRITE_EN_MASK 0x1aa3
+#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1aa3
+#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1ca3
+#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x1ea3
+#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x40a3
+#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x42a3
+#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x44a3
+#define mmREGAMMA_CNTLA_START_CNTL 0x1aa4
+#define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1aa4
+#define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1ca4
+#define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x1ea4
+#define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x40a4
+#define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x42a4
+#define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x44a4
+#define mmREGAMMA_CNTLA_SLOPE_CNTL 0x1aa5
+#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1aa5
+#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1ca5
+#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x1ea5
+#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x40a5
+#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x42a5
+#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x44a5
+#define mmREGAMMA_CNTLA_END_CNTL1 0x1aa6
+#define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1aa6
+#define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1ca6
+#define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x1ea6
+#define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x40a6
+#define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x42a6
+#define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x44a6
+#define mmREGAMMA_CNTLA_END_CNTL2 0x1aa7
+#define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1aa7
+#define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1ca7
+#define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x1ea7
+#define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x40a7
+#define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x42a7
+#define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x44a7
+#define mmREGAMMA_CNTLA_REGION_0_1 0x1aa8
+#define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1aa8
+#define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1ca8
+#define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x1ea8
+#define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x40a8
+#define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x42a8
+#define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x44a8
+#define mmREGAMMA_CNTLA_REGION_2_3 0x1aa9
+#define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1aa9
+#define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1ca9
+#define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x1ea9
+#define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x40a9
+#define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x42a9
+#define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x44a9
+#define mmREGAMMA_CNTLA_REGION_4_5 0x1aaa
+#define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1aaa
+#define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1caa
+#define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x1eaa
+#define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x40aa
+#define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x42aa
+#define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x44aa
+#define mmREGAMMA_CNTLA_REGION_6_7 0x1aab
+#define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1aab
+#define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1cab
+#define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x1eab
+#define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x40ab
+#define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x42ab
+#define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x44ab
+#define mmREGAMMA_CNTLA_REGION_8_9 0x1aac
+#define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1aac
+#define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1cac
+#define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x1eac
+#define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x40ac
+#define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x42ac
+#define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x44ac
+#define mmREGAMMA_CNTLA_REGION_10_11 0x1aad
+#define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1aad
+#define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1cad
+#define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x1ead
+#define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x40ad
+#define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x42ad
+#define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x44ad
+#define mmREGAMMA_CNTLA_REGION_12_13 0x1aae
+#define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1aae
+#define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1cae
+#define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x1eae
+#define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x40ae
+#define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x42ae
+#define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x44ae
+#define mmREGAMMA_CNTLA_REGION_14_15 0x1aaf
+#define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1aaf
+#define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1caf
+#define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x1eaf
+#define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x40af
+#define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x42af
+#define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x44af
+#define mmREGAMMA_CNTLB_START_CNTL 0x1ab0
+#define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1ab0
+#define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1cb0
+#define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x1eb0
+#define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x40b0
+#define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x42b0
+#define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x44b0
+#define mmREGAMMA_CNTLB_SLOPE_CNTL 0x1ab1
+#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1ab1
+#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1cb1
+#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x1eb1
+#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x40b1
+#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x42b1
+#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x44b1
+#define mmREGAMMA_CNTLB_END_CNTL1 0x1ab2
+#define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1ab2
+#define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1cb2
+#define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x1eb2
+#define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x40b2
+#define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x42b2
+#define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x44b2
+#define mmREGAMMA_CNTLB_END_CNTL2 0x1ab3
+#define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1ab3
+#define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1cb3
+#define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x1eb3
+#define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x40b3
+#define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x42b3
+#define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x44b3
+#define mmREGAMMA_CNTLB_REGION_0_1 0x1ab4
+#define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1ab4
+#define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1cb4
+#define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x1eb4
+#define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x40b4
+#define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x42b4
+#define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x44b4
+#define mmREGAMMA_CNTLB_REGION_2_3 0x1ab5
+#define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1ab5
+#define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1cb5
+#define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x1eb5
+#define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x40b5
+#define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x42b5
+#define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x44b5
+#define mmREGAMMA_CNTLB_REGION_4_5 0x1ab6
+#define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1ab6
+#define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1cb6
+#define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x1eb6
+#define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x40b6
+#define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x42b6
+#define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x44b6
+#define mmREGAMMA_CNTLB_REGION_6_7 0x1ab7
+#define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1ab7
+#define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1cb7
+#define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x1eb7
+#define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x40b7
+#define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x42b7
+#define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x44b7
+#define mmREGAMMA_CNTLB_REGION_8_9 0x1ab8
+#define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1ab8
+#define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1cb8
+#define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x1eb8
+#define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x40b8
+#define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x42b8
+#define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x44b8
+#define mmREGAMMA_CNTLB_REGION_10_11 0x1ab9
+#define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1ab9
+#define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1cb9
+#define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x1eb9
+#define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x40b9
+#define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x42b9
+#define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x44b9
+#define mmREGAMMA_CNTLB_REGION_12_13 0x1aba
+#define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1aba
+#define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1cba
+#define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x1eba
+#define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x40ba
+#define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x42ba
+#define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x44ba
+#define mmREGAMMA_CNTLB_REGION_14_15 0x1abb
+#define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1abb
+#define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1cbb
+#define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x1ebb
+#define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x40bb
+#define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x42bb
+#define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x44bb
+#define mmALPHA_CONTROL 0x1abc
+#define mmDCP0_ALPHA_CONTROL 0x1abc
+#define mmDCP1_ALPHA_CONTROL 0x1cbc
+#define mmDCP2_ALPHA_CONTROL 0x1ebc
+#define mmDCP3_ALPHA_CONTROL 0x40bc
+#define mmDCP4_ALPHA_CONTROL 0x42bc
+#define mmDCP5_ALPHA_CONTROL 0x44bc
+#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd
+#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd
+#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1cbd
+#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1ebd
+#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x40bd
+#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x42bd
+#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x44bd
+#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe
+#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe
+#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1cbe
+#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1ebe
+#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x40be
+#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x42be
+#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x44be
+#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf
+#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf
+#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1cbf
+#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1ebf
+#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x40bf
+#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x42bf
+#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x44bf
+#define mmGRPH_SURFACE_COUNTER_CONTROL 0x1a0f
+#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL 0x1a0f
+#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL 0x1c0f
+#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL 0x1e0f
+#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL 0x400f
+#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL 0x420f
+#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL 0x440f
+#define mmGRPH_SURFACE_COUNTER_OUTPUT 0x1a1d
+#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT 0x1a1d
+#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT 0x1c1d
+#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT 0x1e1d
+#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT 0x401d
+#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT 0x421d
+#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT 0x441d
+#define mmDIG_FE_CNTL 0x4a00
+#define mmDIG0_DIG_FE_CNTL 0x4a00
+#define mmDIG1_DIG_FE_CNTL 0x4b00
+#define mmDIG2_DIG_FE_CNTL 0x4c00
+#define mmDIG3_DIG_FE_CNTL 0x4d00
+#define mmDIG4_DIG_FE_CNTL 0x4e00
+#define mmDIG5_DIG_FE_CNTL 0x4f00
+#define mmDIG6_DIG_FE_CNTL 0x5400
+#define mmDIG7_DIG_FE_CNTL 0x5600
+#define mmDIG8_DIG_FE_CNTL 0x5700
+#define mmDIG_OUTPUT_CRC_CNTL 0x4a01
+#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x4a01
+#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x4b01
+#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4c01
+#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4d01
+#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4e01
+#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4f01
+#define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x5401
+#define mmDIG7_DIG_OUTPUT_CRC_CNTL 0x5601
+#define mmDIG8_DIG_OUTPUT_CRC_CNTL 0x5701
+#define mmDIG_OUTPUT_CRC_RESULT 0x4a02
+#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x4a02
+#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x4b02
+#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4c02
+#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4d02
+#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4e02
+#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4f02
+#define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x5402
+#define mmDIG7_DIG_OUTPUT_CRC_RESULT 0x5602
+#define mmDIG8_DIG_OUTPUT_CRC_RESULT 0x5702
+#define mmDIG_CLOCK_PATTERN 0x4a03
+#define mmDIG0_DIG_CLOCK_PATTERN 0x4a03
+#define mmDIG1_DIG_CLOCK_PATTERN 0x4b03
+#define mmDIG2_DIG_CLOCK_PATTERN 0x4c03
+#define mmDIG3_DIG_CLOCK_PATTERN 0x4d03
+#define mmDIG4_DIG_CLOCK_PATTERN 0x4e03
+#define mmDIG5_DIG_CLOCK_PATTERN 0x4f03
+#define mmDIG6_DIG_CLOCK_PATTERN 0x5403
+#define mmDIG7_DIG_CLOCK_PATTERN 0x5603
+#define mmDIG8_DIG_CLOCK_PATTERN 0x5703
+#define mmDIG_TEST_PATTERN 0x4a04
+#define mmDIG0_DIG_TEST_PATTERN 0x4a04
+#define mmDIG1_DIG_TEST_PATTERN 0x4b04
+#define mmDIG2_DIG_TEST_PATTERN 0x4c04
+#define mmDIG3_DIG_TEST_PATTERN 0x4d04
+#define mmDIG4_DIG_TEST_PATTERN 0x4e04
+#define mmDIG5_DIG_TEST_PATTERN 0x4f04
+#define mmDIG6_DIG_TEST_PATTERN 0x5404
+#define mmDIG7_DIG_TEST_PATTERN 0x5604
+#define mmDIG8_DIG_TEST_PATTERN 0x5704
+#define mmDIG_RANDOM_PATTERN_SEED 0x4a05
+#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x4a05
+#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x4b05
+#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4c05
+#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4d05
+#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4e05
+#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4f05
+#define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x5405
+#define mmDIG7_DIG_RANDOM_PATTERN_SEED 0x5605
+#define mmDIG8_DIG_RANDOM_PATTERN_SEED 0x5705
+#define mmDIG_FIFO_STATUS 0x4a06
+#define mmDIG0_DIG_FIFO_STATUS 0x4a06
+#define mmDIG1_DIG_FIFO_STATUS 0x4b06
+#define mmDIG2_DIG_FIFO_STATUS 0x4c06
+#define mmDIG3_DIG_FIFO_STATUS 0x4d06
+#define mmDIG4_DIG_FIFO_STATUS 0x4e06
+#define mmDIG5_DIG_FIFO_STATUS 0x4f06
+#define mmDIG6_DIG_FIFO_STATUS 0x5406
+#define mmDIG7_DIG_FIFO_STATUS 0x5606
+#define mmDIG8_DIG_FIFO_STATUS 0x5706
+#define mmDIG_DISPCLK_SWITCH_CNTL 0x4a07
+#define mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x4a07
+#define mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x4b07
+#define mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4c07
+#define mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4d07
+#define mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4e07
+#define mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4f07
+#define mmDIG6_DIG_DISPCLK_SWITCH_CNTL 0x5407
+#define mmDIG7_DIG_DISPCLK_SWITCH_CNTL 0x5607
+#define mmDIG8_DIG_DISPCLK_SWITCH_CNTL 0x5707
+#define mmDIG_DISPCLK_SWITCH_STATUS 0x4a08
+#define mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x4a08
+#define mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x4b08
+#define mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4c08
+#define mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4d08
+#define mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4e08
+#define mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4f08
+#define mmDIG6_DIG_DISPCLK_SWITCH_STATUS 0x5408
+#define mmDIG7_DIG_DISPCLK_SWITCH_STATUS 0x5608
+#define mmDIG8_DIG_DISPCLK_SWITCH_STATUS 0x5708
+#define mmHDMI_CONTROL 0x4a09
+#define mmDIG0_HDMI_CONTROL 0x4a09
+#define mmDIG1_HDMI_CONTROL 0x4b09
+#define mmDIG2_HDMI_CONTROL 0x4c09
+#define mmDIG3_HDMI_CONTROL 0x4d09
+#define mmDIG4_HDMI_CONTROL 0x4e09
+#define mmDIG5_HDMI_CONTROL 0x4f09
+#define mmDIG6_HDMI_CONTROL 0x5409
+#define mmDIG7_HDMI_CONTROL 0x5609
+#define mmDIG8_HDMI_CONTROL 0x5709
+#define mmHDMI_STATUS 0x4a0a
+#define mmDIG0_HDMI_STATUS 0x4a0a
+#define mmDIG1_HDMI_STATUS 0x4b0a
+#define mmDIG2_HDMI_STATUS 0x4c0a
+#define mmDIG3_HDMI_STATUS 0x4d0a
+#define mmDIG4_HDMI_STATUS 0x4e0a
+#define mmDIG5_HDMI_STATUS 0x4f0a
+#define mmDIG6_HDMI_STATUS 0x540a
+#define mmDIG7_HDMI_STATUS 0x560a
+#define mmDIG8_HDMI_STATUS 0x570a
+#define mmHDMI_AUDIO_PACKET_CONTROL 0x4a0b
+#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x4a0b
+#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x4b0b
+#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x4c0b
+#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x4d0b
+#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x4e0b
+#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4f0b
+#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x540b
+#define mmDIG7_HDMI_AUDIO_PACKET_CONTROL 0x560b
+#define mmDIG8_HDMI_AUDIO_PACKET_CONTROL 0x570b
+#define mmHDMI_ACR_PACKET_CONTROL 0x4a0c
+#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x4a0c
+#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x4b0c
+#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x4c0c
+#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x4d0c
+#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x4e0c
+#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4f0c
+#define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x540c
+#define mmDIG7_HDMI_ACR_PACKET_CONTROL 0x560c
+#define mmDIG8_HDMI_ACR_PACKET_CONTROL 0x570c
+#define mmHDMI_VBI_PACKET_CONTROL 0x4a0d
+#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x4a0d
+#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x4b0d
+#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4c0d
+#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4d0d
+#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4e0d
+#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4f0d
+#define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x540d
+#define mmDIG7_HDMI_VBI_PACKET_CONTROL 0x560d
+#define mmDIG8_HDMI_VBI_PACKET_CONTROL 0x570d
+#define mmHDMI_INFOFRAME_CONTROL0 0x4a0e
+#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x4a0e
+#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x4b0e
+#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4c0e
+#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4d0e
+#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4e0e
+#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4f0e
+#define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x540e
+#define mmDIG7_HDMI_INFOFRAME_CONTROL0 0x560e
+#define mmDIG8_HDMI_INFOFRAME_CONTROL0 0x570e
+#define mmHDMI_INFOFRAME_CONTROL1 0x4a0f
+#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x4a0f
+#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x4b0f
+#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4c0f
+#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4d0f
+#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4e0f
+#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4f0f
+#define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x540f
+#define mmDIG7_HDMI_INFOFRAME_CONTROL1 0x560f
+#define mmDIG8_HDMI_INFOFRAME_CONTROL1 0x570f
+#define mmHDMI_GENERIC_PACKET_CONTROL0 0x4a10
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x4a10
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x4b10
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4c10
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4d10
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4e10
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4f10
+#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x5410
+#define mmDIG7_HDMI_GENERIC_PACKET_CONTROL0 0x5610
+#define mmDIG8_HDMI_GENERIC_PACKET_CONTROL0 0x5710
+#define mmAFMT_INTERRUPT_STATUS 0x4a11
+#define mmDIG0_AFMT_INTERRUPT_STATUS 0x4a11
+#define mmDIG1_AFMT_INTERRUPT_STATUS 0x4b11
+#define mmDIG2_AFMT_INTERRUPT_STATUS 0x4c11
+#define mmDIG3_AFMT_INTERRUPT_STATUS 0x4d11
+#define mmDIG4_AFMT_INTERRUPT_STATUS 0x4e11
+#define mmDIG5_AFMT_INTERRUPT_STATUS 0x4f11
+#define mmDIG6_AFMT_INTERRUPT_STATUS 0x5411
+#define mmDIG7_AFMT_INTERRUPT_STATUS 0x5611
+#define mmDIG8_AFMT_INTERRUPT_STATUS 0x5711
+#define mmHDMI_GC 0x4a13
+#define mmDIG0_HDMI_GC 0x4a13
+#define mmDIG1_HDMI_GC 0x4b13
+#define mmDIG2_HDMI_GC 0x4c13
+#define mmDIG3_HDMI_GC 0x4d13
+#define mmDIG4_HDMI_GC 0x4e13
+#define mmDIG5_HDMI_GC 0x4f13
+#define mmDIG6_HDMI_GC 0x5413
+#define mmDIG7_HDMI_GC 0x5613
+#define mmDIG8_HDMI_GC 0x5713
+#define mmAFMT_AUDIO_PACKET_CONTROL2 0x4a14
+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x4a14
+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x4b14
+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4c14
+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4d14
+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4e14
+#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4f14
+#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x5414
+#define mmDIG7_AFMT_AUDIO_PACKET_CONTROL2 0x5614
+#define mmDIG8_AFMT_AUDIO_PACKET_CONTROL2 0x5714
+#define mmAFMT_ISRC1_0 0x4a15
+#define mmDIG0_AFMT_ISRC1_0 0x4a15
+#define mmDIG1_AFMT_ISRC1_0 0x4b15
+#define mmDIG2_AFMT_ISRC1_0 0x4c15
+#define mmDIG3_AFMT_ISRC1_0 0x4d15
+#define mmDIG4_AFMT_ISRC1_0 0x4e15
+#define mmDIG5_AFMT_ISRC1_0 0x4f15
+#define mmDIG6_AFMT_ISRC1_0 0x5415
+#define mmDIG7_AFMT_ISRC1_0 0x5615
+#define mmDIG8_AFMT_ISRC1_0 0x5715
+#define mmAFMT_ISRC1_1 0x4a16
+#define mmDIG0_AFMT_ISRC1_1 0x4a16
+#define mmDIG1_AFMT_ISRC1_1 0x4b16
+#define mmDIG2_AFMT_ISRC1_1 0x4c16
+#define mmDIG3_AFMT_ISRC1_1 0x4d16
+#define mmDIG4_AFMT_ISRC1_1 0x4e16
+#define mmDIG5_AFMT_ISRC1_1 0x4f16
+#define mmDIG6_AFMT_ISRC1_1 0x5416
+#define mmDIG7_AFMT_ISRC1_1 0x5616
+#define mmDIG8_AFMT_ISRC1_1 0x5716
+#define mmAFMT_ISRC1_2 0x4a17
+#define mmDIG0_AFMT_ISRC1_2 0x4a17
+#define mmDIG1_AFMT_ISRC1_2 0x4b17
+#define mmDIG2_AFMT_ISRC1_2 0x4c17
+#define mmDIG3_AFMT_ISRC1_2 0x4d17
+#define mmDIG4_AFMT_ISRC1_2 0x4e17
+#define mmDIG5_AFMT_ISRC1_2 0x4f17
+#define mmDIG6_AFMT_ISRC1_2 0x5417
+#define mmDIG7_AFMT_ISRC1_2 0x5617
+#define mmDIG8_AFMT_ISRC1_2 0x5717
+#define mmAFMT_ISRC1_3 0x4a18
+#define mmDIG0_AFMT_ISRC1_3 0x4a18
+#define mmDIG1_AFMT_ISRC1_3 0x4b18
+#define mmDIG2_AFMT_ISRC1_3 0x4c18
+#define mmDIG3_AFMT_ISRC1_3 0x4d18
+#define mmDIG4_AFMT_ISRC1_3 0x4e18
+#define mmDIG5_AFMT_ISRC1_3 0x4f18
+#define mmDIG6_AFMT_ISRC1_3 0x5418
+#define mmDIG7_AFMT_ISRC1_3 0x5618
+#define mmDIG8_AFMT_ISRC1_3 0x5718
+#define mmAFMT_ISRC1_4 0x4a19
+#define mmDIG0_AFMT_ISRC1_4 0x4a19
+#define mmDIG1_AFMT_ISRC1_4 0x4b19
+#define mmDIG2_AFMT_ISRC1_4 0x4c19
+#define mmDIG3_AFMT_ISRC1_4 0x4d19
+#define mmDIG4_AFMT_ISRC1_4 0x4e19
+#define mmDIG5_AFMT_ISRC1_4 0x4f19
+#define mmDIG6_AFMT_ISRC1_4 0x5419
+#define mmDIG7_AFMT_ISRC1_4 0x5619
+#define mmDIG8_AFMT_ISRC1_4 0x5719
+#define mmAFMT_ISRC2_0 0x4a1a
+#define mmDIG0_AFMT_ISRC2_0 0x4a1a
+#define mmDIG1_AFMT_ISRC2_0 0x4b1a
+#define mmDIG2_AFMT_ISRC2_0 0x4c1a
+#define mmDIG3_AFMT_ISRC2_0 0x4d1a
+#define mmDIG4_AFMT_ISRC2_0 0x4e1a
+#define mmDIG5_AFMT_ISRC2_0 0x4f1a
+#define mmDIG6_AFMT_ISRC2_0 0x541a
+#define mmDIG7_AFMT_ISRC2_0 0x561a
+#define mmDIG8_AFMT_ISRC2_0 0x571a
+#define mmAFMT_ISRC2_1 0x4a1b
+#define mmDIG0_AFMT_ISRC2_1 0x4a1b
+#define mmDIG1_AFMT_ISRC2_1 0x4b1b
+#define mmDIG2_AFMT_ISRC2_1 0x4c1b
+#define mmDIG3_AFMT_ISRC2_1 0x4d1b
+#define mmDIG4_AFMT_ISRC2_1 0x4e1b
+#define mmDIG5_AFMT_ISRC2_1 0x4f1b
+#define mmDIG6_AFMT_ISRC2_1 0x541b
+#define mmDIG7_AFMT_ISRC2_1 0x561b
+#define mmDIG8_AFMT_ISRC2_1 0x571b
+#define mmAFMT_ISRC2_2 0x4a1c
+#define mmDIG0_AFMT_ISRC2_2 0x4a1c
+#define mmDIG1_AFMT_ISRC2_2 0x4b1c
+#define mmDIG2_AFMT_ISRC2_2 0x4c1c
+#define mmDIG3_AFMT_ISRC2_2 0x4d1c
+#define mmDIG4_AFMT_ISRC2_2 0x4e1c
+#define mmDIG5_AFMT_ISRC2_2 0x4f1c
+#define mmDIG6_AFMT_ISRC2_2 0x541c
+#define mmDIG7_AFMT_ISRC2_2 0x561c
+#define mmDIG8_AFMT_ISRC2_2 0x571c
+#define mmAFMT_ISRC2_3 0x4a1d
+#define mmDIG0_AFMT_ISRC2_3 0x4a1d
+#define mmDIG1_AFMT_ISRC2_3 0x4b1d
+#define mmDIG2_AFMT_ISRC2_3 0x4c1d
+#define mmDIG3_AFMT_ISRC2_3 0x4d1d
+#define mmDIG4_AFMT_ISRC2_3 0x4e1d
+#define mmDIG5_AFMT_ISRC2_3 0x4f1d
+#define mmDIG6_AFMT_ISRC2_3 0x541d
+#define mmDIG7_AFMT_ISRC2_3 0x561d
+#define mmDIG8_AFMT_ISRC2_3 0x571d
+#define mmAFMT_AVI_INFO0 0x4a1e
+#define mmDIG0_AFMT_AVI_INFO0 0x4a1e
+#define mmDIG1_AFMT_AVI_INFO0 0x4b1e
+#define mmDIG2_AFMT_AVI_INFO0 0x4c1e
+#define mmDIG3_AFMT_AVI_INFO0 0x4d1e
+#define mmDIG4_AFMT_AVI_INFO0 0x4e1e
+#define mmDIG5_AFMT_AVI_INFO0 0x4f1e
+#define mmDIG6_AFMT_AVI_INFO0 0x541e
+#define mmDIG7_AFMT_AVI_INFO0 0x561e
+#define mmDIG8_AFMT_AVI_INFO0 0x571e
+#define mmAFMT_AVI_INFO1 0x4a1f
+#define mmDIG0_AFMT_AVI_INFO1 0x4a1f
+#define mmDIG1_AFMT_AVI_INFO1 0x4b1f
+#define mmDIG2_AFMT_AVI_INFO1 0x4c1f
+#define mmDIG3_AFMT_AVI_INFO1 0x4d1f
+#define mmDIG4_AFMT_AVI_INFO1 0x4e1f
+#define mmDIG5_AFMT_AVI_INFO1 0x4f1f
+#define mmDIG6_AFMT_AVI_INFO1 0x541f
+#define mmDIG7_AFMT_AVI_INFO1 0x561f
+#define mmDIG8_AFMT_AVI_INFO1 0x571f
+#define mmAFMT_AVI_INFO2 0x4a20
+#define mmDIG0_AFMT_AVI_INFO2 0x4a20
+#define mmDIG1_AFMT_AVI_INFO2 0x4b20
+#define mmDIG2_AFMT_AVI_INFO2 0x4c20
+#define mmDIG3_AFMT_AVI_INFO2 0x4d20
+#define mmDIG4_AFMT_AVI_INFO2 0x4e20
+#define mmDIG5_AFMT_AVI_INFO2 0x4f20
+#define mmDIG6_AFMT_AVI_INFO2 0x5420
+#define mmDIG7_AFMT_AVI_INFO2 0x5620
+#define mmDIG8_AFMT_AVI_INFO2 0x5720
+#define mmAFMT_AVI_INFO3 0x4a21
+#define mmDIG0_AFMT_AVI_INFO3 0x4a21
+#define mmDIG1_AFMT_AVI_INFO3 0x4b21
+#define mmDIG2_AFMT_AVI_INFO3 0x4c21
+#define mmDIG3_AFMT_AVI_INFO3 0x4d21
+#define mmDIG4_AFMT_AVI_INFO3 0x4e21
+#define mmDIG5_AFMT_AVI_INFO3 0x4f21
+#define mmDIG6_AFMT_AVI_INFO3 0x5421
+#define mmDIG7_AFMT_AVI_INFO3 0x5621
+#define mmDIG8_AFMT_AVI_INFO3 0x5721
+#define mmAFMT_MPEG_INFO0 0x4a22
+#define mmDIG0_AFMT_MPEG_INFO0 0x4a22
+#define mmDIG1_AFMT_MPEG_INFO0 0x4b22
+#define mmDIG2_AFMT_MPEG_INFO0 0x4c22
+#define mmDIG3_AFMT_MPEG_INFO0 0x4d22
+#define mmDIG4_AFMT_MPEG_INFO0 0x4e22
+#define mmDIG5_AFMT_MPEG_INFO0 0x4f22
+#define mmDIG6_AFMT_MPEG_INFO0 0x5422
+#define mmDIG7_AFMT_MPEG_INFO0 0x5622
+#define mmDIG8_AFMT_MPEG_INFO0 0x5722
+#define mmAFMT_MPEG_INFO1 0x4a23
+#define mmDIG0_AFMT_MPEG_INFO1 0x4a23
+#define mmDIG1_AFMT_MPEG_INFO1 0x4b23
+#define mmDIG2_AFMT_MPEG_INFO1 0x4c23
+#define mmDIG3_AFMT_MPEG_INFO1 0x4d23
+#define mmDIG4_AFMT_MPEG_INFO1 0x4e23
+#define mmDIG5_AFMT_MPEG_INFO1 0x4f23
+#define mmDIG6_AFMT_MPEG_INFO1 0x5423
+#define mmDIG7_AFMT_MPEG_INFO1 0x5623
+#define mmDIG8_AFMT_MPEG_INFO1 0x5723
+#define mmAFMT_GENERIC_HDR 0x4a24
+#define mmDIG0_AFMT_GENERIC_HDR 0x4a24
+#define mmDIG1_AFMT_GENERIC_HDR 0x4b24
+#define mmDIG2_AFMT_GENERIC_HDR 0x4c24
+#define mmDIG3_AFMT_GENERIC_HDR 0x4d24
+#define mmDIG4_AFMT_GENERIC_HDR 0x4e24
+#define mmDIG5_AFMT_GENERIC_HDR 0x4f24
+#define mmDIG6_AFMT_GENERIC_HDR 0x5424
+#define mmDIG7_AFMT_GENERIC_HDR 0x5624
+#define mmDIG8_AFMT_GENERIC_HDR 0x5724
+#define mmAFMT_GENERIC_0 0x4a25
+#define mmDIG0_AFMT_GENERIC_0 0x4a25
+#define mmDIG1_AFMT_GENERIC_0 0x4b25
+#define mmDIG2_AFMT_GENERIC_0 0x4c25
+#define mmDIG3_AFMT_GENERIC_0 0x4d25
+#define mmDIG4_AFMT_GENERIC_0 0x4e25
+#define mmDIG5_AFMT_GENERIC_0 0x4f25
+#define mmDIG6_AFMT_GENERIC_0 0x5425
+#define mmDIG7_AFMT_GENERIC_0 0x5625
+#define mmDIG8_AFMT_GENERIC_0 0x5725
+#define mmAFMT_GENERIC_1 0x4a26
+#define mmDIG0_AFMT_GENERIC_1 0x4a26
+#define mmDIG1_AFMT_GENERIC_1 0x4b26
+#define mmDIG2_AFMT_GENERIC_1 0x4c26
+#define mmDIG3_AFMT_GENERIC_1 0x4d26
+#define mmDIG4_AFMT_GENERIC_1 0x4e26
+#define mmDIG5_AFMT_GENERIC_1 0x4f26
+#define mmDIG6_AFMT_GENERIC_1 0x5426
+#define mmDIG7_AFMT_GENERIC_1 0x5626
+#define mmDIG8_AFMT_GENERIC_1 0x5726
+#define mmAFMT_GENERIC_2 0x4a27
+#define mmDIG0_AFMT_GENERIC_2 0x4a27
+#define mmDIG1_AFMT_GENERIC_2 0x4b27
+#define mmDIG2_AFMT_GENERIC_2 0x4c27
+#define mmDIG3_AFMT_GENERIC_2 0x4d27
+#define mmDIG4_AFMT_GENERIC_2 0x4e27
+#define mmDIG5_AFMT_GENERIC_2 0x4f27
+#define mmDIG6_AFMT_GENERIC_2 0x5427
+#define mmDIG7_AFMT_GENERIC_2 0x5627
+#define mmDIG8_AFMT_GENERIC_2 0x5727
+#define mmAFMT_GENERIC_3 0x4a28
+#define mmDIG0_AFMT_GENERIC_3 0x4a28
+#define mmDIG1_AFMT_GENERIC_3 0x4b28
+#define mmDIG2_AFMT_GENERIC_3 0x4c28
+#define mmDIG3_AFMT_GENERIC_3 0x4d28
+#define mmDIG4_AFMT_GENERIC_3 0x4e28
+#define mmDIG5_AFMT_GENERIC_3 0x4f28
+#define mmDIG6_AFMT_GENERIC_3 0x5428
+#define mmDIG7_AFMT_GENERIC_3 0x5628
+#define mmDIG8_AFMT_GENERIC_3 0x5728
+#define mmAFMT_GENERIC_4 0x4a29
+#define mmDIG0_AFMT_GENERIC_4 0x4a29
+#define mmDIG1_AFMT_GENERIC_4 0x4b29
+#define mmDIG2_AFMT_GENERIC_4 0x4c29
+#define mmDIG3_AFMT_GENERIC_4 0x4d29
+#define mmDIG4_AFMT_GENERIC_4 0x4e29
+#define mmDIG5_AFMT_GENERIC_4 0x4f29
+#define mmDIG6_AFMT_GENERIC_4 0x5429
+#define mmDIG7_AFMT_GENERIC_4 0x5629
+#define mmDIG8_AFMT_GENERIC_4 0x5729
+#define mmAFMT_GENERIC_5 0x4a2a
+#define mmDIG0_AFMT_GENERIC_5 0x4a2a
+#define mmDIG1_AFMT_GENERIC_5 0x4b2a
+#define mmDIG2_AFMT_GENERIC_5 0x4c2a
+#define mmDIG3_AFMT_GENERIC_5 0x4d2a
+#define mmDIG4_AFMT_GENERIC_5 0x4e2a
+#define mmDIG5_AFMT_GENERIC_5 0x4f2a
+#define mmDIG6_AFMT_GENERIC_5 0x542a
+#define mmDIG7_AFMT_GENERIC_5 0x562a
+#define mmDIG8_AFMT_GENERIC_5 0x572a
+#define mmAFMT_GENERIC_6 0x4a2b
+#define mmDIG0_AFMT_GENERIC_6 0x4a2b
+#define mmDIG1_AFMT_GENERIC_6 0x4b2b
+#define mmDIG2_AFMT_GENERIC_6 0x4c2b
+#define mmDIG3_AFMT_GENERIC_6 0x4d2b
+#define mmDIG4_AFMT_GENERIC_6 0x4e2b
+#define mmDIG5_AFMT_GENERIC_6 0x4f2b
+#define mmDIG6_AFMT_GENERIC_6 0x542b
+#define mmDIG7_AFMT_GENERIC_6 0x562b
+#define mmDIG8_AFMT_GENERIC_6 0x572b
+#define mmAFMT_GENERIC_7 0x4a2c
+#define mmDIG0_AFMT_GENERIC_7 0x4a2c
+#define mmDIG1_AFMT_GENERIC_7 0x4b2c
+#define mmDIG2_AFMT_GENERIC_7 0x4c2c
+#define mmDIG3_AFMT_GENERIC_7 0x4d2c
+#define mmDIG4_AFMT_GENERIC_7 0x4e2c
+#define mmDIG5_AFMT_GENERIC_7 0x4f2c
+#define mmDIG6_AFMT_GENERIC_7 0x542c
+#define mmDIG7_AFMT_GENERIC_7 0x562c
+#define mmDIG8_AFMT_GENERIC_7 0x572c
+#define mmHDMI_GENERIC_PACKET_CONTROL1 0x4a2d
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x4a2d
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x4b2d
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4c2d
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4d2d
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4e2d
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4f2d
+#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x542d
+#define mmDIG7_HDMI_GENERIC_PACKET_CONTROL1 0x562d
+#define mmDIG8_HDMI_GENERIC_PACKET_CONTROL1 0x572d
+#define mmHDMI_ACR_32_0 0x4a2e
+#define mmDIG0_HDMI_ACR_32_0 0x4a2e
+#define mmDIG1_HDMI_ACR_32_0 0x4b2e
+#define mmDIG2_HDMI_ACR_32_0 0x4c2e
+#define mmDIG3_HDMI_ACR_32_0 0x4d2e
+#define mmDIG4_HDMI_ACR_32_0 0x4e2e
+#define mmDIG5_HDMI_ACR_32_0 0x4f2e
+#define mmDIG6_HDMI_ACR_32_0 0x542e
+#define mmDIG7_HDMI_ACR_32_0 0x562e
+#define mmDIG8_HDMI_ACR_32_0 0x572e
+#define mmHDMI_ACR_32_1 0x4a2f
+#define mmDIG0_HDMI_ACR_32_1 0x4a2f
+#define mmDIG1_HDMI_ACR_32_1 0x4b2f
+#define mmDIG2_HDMI_ACR_32_1 0x4c2f
+#define mmDIG3_HDMI_ACR_32_1 0x4d2f
+#define mmDIG4_HDMI_ACR_32_1 0x4e2f
+#define mmDIG5_HDMI_ACR_32_1 0x4f2f
+#define mmDIG6_HDMI_ACR_32_1 0x542f
+#define mmDIG7_HDMI_ACR_32_1 0x562f
+#define mmDIG8_HDMI_ACR_32_1 0x572f
+#define mmHDMI_ACR_44_0 0x4a30
+#define mmDIG0_HDMI_ACR_44_0 0x4a30
+#define mmDIG1_HDMI_ACR_44_0 0x4b30
+#define mmDIG2_HDMI_ACR_44_0 0x4c30
+#define mmDIG3_HDMI_ACR_44_0 0x4d30
+#define mmDIG4_HDMI_ACR_44_0 0x4e30
+#define mmDIG5_HDMI_ACR_44_0 0x4f30
+#define mmDIG6_HDMI_ACR_44_0 0x5430
+#define mmDIG7_HDMI_ACR_44_0 0x5630
+#define mmDIG8_HDMI_ACR_44_0 0x5730
+#define mmHDMI_ACR_44_1 0x4a31
+#define mmDIG0_HDMI_ACR_44_1 0x4a31
+#define mmDIG1_HDMI_ACR_44_1 0x4b31
+#define mmDIG2_HDMI_ACR_44_1 0x4c31
+#define mmDIG3_HDMI_ACR_44_1 0x4d31
+#define mmDIG4_HDMI_ACR_44_1 0x4e31
+#define mmDIG5_HDMI_ACR_44_1 0x4f31
+#define mmDIG6_HDMI_ACR_44_1 0x5431
+#define mmDIG7_HDMI_ACR_44_1 0x5631
+#define mmDIG8_HDMI_ACR_44_1 0x5731
+#define mmHDMI_ACR_48_0 0x4a32
+#define mmDIG0_HDMI_ACR_48_0 0x4a32
+#define mmDIG1_HDMI_ACR_48_0 0x4b32
+#define mmDIG2_HDMI_ACR_48_0 0x4c32
+#define mmDIG3_HDMI_ACR_48_0 0x4d32
+#define mmDIG4_HDMI_ACR_48_0 0x4e32
+#define mmDIG5_HDMI_ACR_48_0 0x4f32
+#define mmDIG6_HDMI_ACR_48_0 0x5432
+#define mmDIG7_HDMI_ACR_48_0 0x5632
+#define mmDIG8_HDMI_ACR_48_0 0x5732
+#define mmHDMI_ACR_48_1 0x4a33
+#define mmDIG0_HDMI_ACR_48_1 0x4a33
+#define mmDIG1_HDMI_ACR_48_1 0x4b33
+#define mmDIG2_HDMI_ACR_48_1 0x4c33
+#define mmDIG3_HDMI_ACR_48_1 0x4d33
+#define mmDIG4_HDMI_ACR_48_1 0x4e33
+#define mmDIG5_HDMI_ACR_48_1 0x4f33
+#define mmDIG6_HDMI_ACR_48_1 0x5433
+#define mmDIG7_HDMI_ACR_48_1 0x5633
+#define mmDIG8_HDMI_ACR_48_1 0x5733
+#define mmHDMI_ACR_STATUS_0 0x4a34
+#define mmDIG0_HDMI_ACR_STATUS_0 0x4a34
+#define mmDIG1_HDMI_ACR_STATUS_0 0x4b34
+#define mmDIG2_HDMI_ACR_STATUS_0 0x4c34
+#define mmDIG3_HDMI_ACR_STATUS_0 0x4d34
+#define mmDIG4_HDMI_ACR_STATUS_0 0x4e34
+#define mmDIG5_HDMI_ACR_STATUS_0 0x4f34
+#define mmDIG6_HDMI_ACR_STATUS_0 0x5434
+#define mmDIG7_HDMI_ACR_STATUS_0 0x5634
+#define mmDIG8_HDMI_ACR_STATUS_0 0x5734
+#define mmHDMI_ACR_STATUS_1 0x4a35
+#define mmDIG0_HDMI_ACR_STATUS_1 0x4a35
+#define mmDIG1_HDMI_ACR_STATUS_1 0x4b35
+#define mmDIG2_HDMI_ACR_STATUS_1 0x4c35
+#define mmDIG3_HDMI_ACR_STATUS_1 0x4d35
+#define mmDIG4_HDMI_ACR_STATUS_1 0x4e35
+#define mmDIG5_HDMI_ACR_STATUS_1 0x4f35
+#define mmDIG6_HDMI_ACR_STATUS_1 0x5435
+#define mmDIG7_HDMI_ACR_STATUS_1 0x5635
+#define mmDIG8_HDMI_ACR_STATUS_1 0x5735
+#define mmAFMT_AUDIO_INFO0 0x4a36
+#define mmDIG0_AFMT_AUDIO_INFO0 0x4a36
+#define mmDIG1_AFMT_AUDIO_INFO0 0x4b36
+#define mmDIG2_AFMT_AUDIO_INFO0 0x4c36
+#define mmDIG3_AFMT_AUDIO_INFO0 0x4d36
+#define mmDIG4_AFMT_AUDIO_INFO0 0x4e36
+#define mmDIG5_AFMT_AUDIO_INFO0 0x4f36
+#define mmDIG6_AFMT_AUDIO_INFO0 0x5436
+#define mmDIG7_AFMT_AUDIO_INFO0 0x5636
+#define mmDIG8_AFMT_AUDIO_INFO0 0x5736
+#define mmAFMT_AUDIO_INFO1 0x4a37
+#define mmDIG0_AFMT_AUDIO_INFO1 0x4a37
+#define mmDIG1_AFMT_AUDIO_INFO1 0x4b37
+#define mmDIG2_AFMT_AUDIO_INFO1 0x4c37
+#define mmDIG3_AFMT_AUDIO_INFO1 0x4d37
+#define mmDIG4_AFMT_AUDIO_INFO1 0x4e37
+#define mmDIG5_AFMT_AUDIO_INFO1 0x4f37
+#define mmDIG6_AFMT_AUDIO_INFO1 0x5437
+#define mmDIG7_AFMT_AUDIO_INFO1 0x5637
+#define mmDIG8_AFMT_AUDIO_INFO1 0x5737
+#define mmAFMT_60958_0 0x4a38
+#define mmDIG0_AFMT_60958_0 0x4a38
+#define mmDIG1_AFMT_60958_0 0x4b38
+#define mmDIG2_AFMT_60958_0 0x4c38
+#define mmDIG3_AFMT_60958_0 0x4d38
+#define mmDIG4_AFMT_60958_0 0x4e38
+#define mmDIG5_AFMT_60958_0 0x4f38
+#define mmDIG6_AFMT_60958_0 0x5438
+#define mmDIG7_AFMT_60958_0 0x5638
+#define mmDIG8_AFMT_60958_0 0x5738
+#define mmAFMT_60958_1 0x4a39
+#define mmDIG0_AFMT_60958_1 0x4a39
+#define mmDIG1_AFMT_60958_1 0x4b39
+#define mmDIG2_AFMT_60958_1 0x4c39
+#define mmDIG3_AFMT_60958_1 0x4d39
+#define mmDIG4_AFMT_60958_1 0x4e39
+#define mmDIG5_AFMT_60958_1 0x4f39
+#define mmDIG6_AFMT_60958_1 0x5439
+#define mmDIG7_AFMT_60958_1 0x5639
+#define mmDIG8_AFMT_60958_1 0x5739
+#define mmAFMT_AUDIO_CRC_CONTROL 0x4a3a
+#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x4a3a
+#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x4b3a
+#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4c3a
+#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4d3a
+#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4e3a
+#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4f3a
+#define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x543a
+#define mmDIG7_AFMT_AUDIO_CRC_CONTROL 0x563a
+#define mmDIG8_AFMT_AUDIO_CRC_CONTROL 0x573a
+#define mmAFMT_RAMP_CONTROL0 0x4a3b
+#define mmDIG0_AFMT_RAMP_CONTROL0 0x4a3b
+#define mmDIG1_AFMT_RAMP_CONTROL0 0x4b3b
+#define mmDIG2_AFMT_RAMP_CONTROL0 0x4c3b
+#define mmDIG3_AFMT_RAMP_CONTROL0 0x4d3b
+#define mmDIG4_AFMT_RAMP_CONTROL0 0x4e3b
+#define mmDIG5_AFMT_RAMP_CONTROL0 0x4f3b
+#define mmDIG6_AFMT_RAMP_CONTROL0 0x543b
+#define mmDIG7_AFMT_RAMP_CONTROL0 0x563b
+#define mmDIG8_AFMT_RAMP_CONTROL0 0x573b
+#define mmAFMT_RAMP_CONTROL1 0x4a3c
+#define mmDIG0_AFMT_RAMP_CONTROL1 0x4a3c
+#define mmDIG1_AFMT_RAMP_CONTROL1 0x4b3c
+#define mmDIG2_AFMT_RAMP_CONTROL1 0x4c3c
+#define mmDIG3_AFMT_RAMP_CONTROL1 0x4d3c
+#define mmDIG4_AFMT_RAMP_CONTROL1 0x4e3c
+#define mmDIG5_AFMT_RAMP_CONTROL1 0x4f3c
+#define mmDIG6_AFMT_RAMP_CONTROL1 0x543c
+#define mmDIG7_AFMT_RAMP_CONTROL1 0x563c
+#define mmDIG8_AFMT_RAMP_CONTROL1 0x573c
+#define mmAFMT_RAMP_CONTROL2 0x4a3d
+#define mmDIG0_AFMT_RAMP_CONTROL2 0x4a3d
+#define mmDIG1_AFMT_RAMP_CONTROL2 0x4b3d
+#define mmDIG2_AFMT_RAMP_CONTROL2 0x4c3d
+#define mmDIG3_AFMT_RAMP_CONTROL2 0x4d3d
+#define mmDIG4_AFMT_RAMP_CONTROL2 0x4e3d
+#define mmDIG5_AFMT_RAMP_CONTROL2 0x4f3d
+#define mmDIG6_AFMT_RAMP_CONTROL2 0x543d
+#define mmDIG7_AFMT_RAMP_CONTROL2 0x563d
+#define mmDIG8_AFMT_RAMP_CONTROL2 0x573d
+#define mmAFMT_RAMP_CONTROL3 0x4a3e
+#define mmDIG0_AFMT_RAMP_CONTROL3 0x4a3e
+#define mmDIG1_AFMT_RAMP_CONTROL3 0x4b3e
+#define mmDIG2_AFMT_RAMP_CONTROL3 0x4c3e
+#define mmDIG3_AFMT_RAMP_CONTROL3 0x4d3e
+#define mmDIG4_AFMT_RAMP_CONTROL3 0x4e3e
+#define mmDIG5_AFMT_RAMP_CONTROL3 0x4f3e
+#define mmDIG6_AFMT_RAMP_CONTROL3 0x543e
+#define mmDIG7_AFMT_RAMP_CONTROL3 0x563e
+#define mmDIG8_AFMT_RAMP_CONTROL3 0x573e
+#define mmAFMT_60958_2 0x4a3f
+#define mmDIG0_AFMT_60958_2 0x4a3f
+#define mmDIG1_AFMT_60958_2 0x4b3f
+#define mmDIG2_AFMT_60958_2 0x4c3f
+#define mmDIG3_AFMT_60958_2 0x4d3f
+#define mmDIG4_AFMT_60958_2 0x4e3f
+#define mmDIG5_AFMT_60958_2 0x4f3f
+#define mmDIG6_AFMT_60958_2 0x543f
+#define mmDIG7_AFMT_60958_2 0x563f
+#define mmDIG8_AFMT_60958_2 0x573f
+#define mmAFMT_AUDIO_CRC_RESULT 0x4a40
+#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x4a40
+#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x4b40
+#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4c40
+#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4d40
+#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4e40
+#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4f40
+#define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x5440
+#define mmDIG7_AFMT_AUDIO_CRC_RESULT 0x5640
+#define mmDIG8_AFMT_AUDIO_CRC_RESULT 0x5740
+#define mmAFMT_STATUS 0x4a41
+#define mmDIG0_AFMT_STATUS 0x4a41
+#define mmDIG1_AFMT_STATUS 0x4b41
+#define mmDIG2_AFMT_STATUS 0x4c41
+#define mmDIG3_AFMT_STATUS 0x4d41
+#define mmDIG4_AFMT_STATUS 0x4e41
+#define mmDIG5_AFMT_STATUS 0x4f41
+#define mmDIG6_AFMT_STATUS 0x5441
+#define mmDIG7_AFMT_STATUS 0x5641
+#define mmDIG8_AFMT_STATUS 0x5741
+#define mmAFMT_AUDIO_PACKET_CONTROL 0x4a42
+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x4a42
+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x4b42
+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x4c42
+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x4d42
+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x4e42
+#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4f42
+#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x5442
+#define mmDIG7_AFMT_AUDIO_PACKET_CONTROL 0x5642
+#define mmDIG8_AFMT_AUDIO_PACKET_CONTROL 0x5742
+#define mmAFMT_VBI_PACKET_CONTROL 0x4a43
+#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x4a43
+#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x4b43
+#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x4c43
+#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x4d43
+#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x4e43
+#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4f43
+#define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x5443
+#define mmDIG7_AFMT_VBI_PACKET_CONTROL 0x5643
+#define mmDIG8_AFMT_VBI_PACKET_CONTROL 0x5743
+#define mmAFMT_INFOFRAME_CONTROL0 0x4a44
+#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x4a44
+#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x4b44
+#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x4c44
+#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x4d44
+#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x4e44
+#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4f44
+#define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x5444
+#define mmDIG7_AFMT_INFOFRAME_CONTROL0 0x5644
+#define mmDIG8_AFMT_INFOFRAME_CONTROL0 0x5744
+#define mmAFMT_AUDIO_SRC_CONTROL 0x4a45
+#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x4a45
+#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x4b45
+#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x4c45
+#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x4d45
+#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x4e45
+#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4f45
+#define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x5445
+#define mmDIG7_AFMT_AUDIO_SRC_CONTROL 0x5645
+#define mmDIG8_AFMT_AUDIO_SRC_CONTROL 0x5745
+#define mmAFMT_AUDIO_DBG_DTO_CNTL 0x4a46
+#define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x4a46
+#define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x4b46
+#define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4c46
+#define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4d46
+#define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4e46
+#define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4f46
+#define mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL 0x5446
+#define mmDIG7_AFMT_AUDIO_DBG_DTO_CNTL 0x5646
+#define mmDIG8_AFMT_AUDIO_DBG_DTO_CNTL 0x5746
+#define mmAFMT_CNTL 0x4a7e
+#define mmDIG0_AFMT_CNTL 0x4a7e
+#define mmDIG1_AFMT_CNTL 0x4b7e
+#define mmDIG2_AFMT_CNTL 0x4c7e
+#define mmDIG3_AFMT_CNTL 0x4d7e
+#define mmDIG4_AFMT_CNTL 0x4e7e
+#define mmDIG5_AFMT_CNTL 0x4f7e
+#define mmDIG6_AFMT_CNTL 0x547e
+#define mmDIG7_AFMT_CNTL 0x567e
+#define mmDIG8_AFMT_CNTL 0x577e
+#define mmDIG_BE_CNTL 0x4a47
+#define mmDIG0_DIG_BE_CNTL 0x4a47
+#define mmDIG1_DIG_BE_CNTL 0x4b47
+#define mmDIG2_DIG_BE_CNTL 0x4c47
+#define mmDIG3_DIG_BE_CNTL 0x4d47
+#define mmDIG4_DIG_BE_CNTL 0x4e47
+#define mmDIG5_DIG_BE_CNTL 0x4f47
+#define mmDIG6_DIG_BE_CNTL 0x5447
+#define mmDIG7_DIG_BE_CNTL 0x5647
+#define mmDIG8_DIG_BE_CNTL 0x5747
+#define mmDIG_BE_EN_CNTL 0x4a48
+#define mmDIG0_DIG_BE_EN_CNTL 0x4a48
+#define mmDIG1_DIG_BE_EN_CNTL 0x4b48
+#define mmDIG2_DIG_BE_EN_CNTL 0x4c48
+#define mmDIG3_DIG_BE_EN_CNTL 0x4d48
+#define mmDIG4_DIG_BE_EN_CNTL 0x4e48
+#define mmDIG5_DIG_BE_EN_CNTL 0x4f48
+#define mmDIG6_DIG_BE_EN_CNTL 0x5448
+#define mmDIG7_DIG_BE_EN_CNTL 0x5648
+#define mmDIG8_DIG_BE_EN_CNTL 0x5748
+#define mmTMDS_CNTL 0x4a6b
+#define mmDIG0_TMDS_CNTL 0x4a6b
+#define mmDIG1_TMDS_CNTL 0x4b6b
+#define mmDIG2_TMDS_CNTL 0x4c6b
+#define mmDIG3_TMDS_CNTL 0x4d6b
+#define mmDIG4_TMDS_CNTL 0x4e6b
+#define mmDIG5_TMDS_CNTL 0x4f6b
+#define mmDIG6_TMDS_CNTL 0x546b
+#define mmDIG7_TMDS_CNTL 0x566b
+#define mmDIG8_TMDS_CNTL 0x576b
+#define mmTMDS_CONTROL_CHAR 0x4a6c
+#define mmDIG0_TMDS_CONTROL_CHAR 0x4a6c
+#define mmDIG1_TMDS_CONTROL_CHAR 0x4b6c
+#define mmDIG2_TMDS_CONTROL_CHAR 0x4c6c
+#define mmDIG3_TMDS_CONTROL_CHAR 0x4d6c
+#define mmDIG4_TMDS_CONTROL_CHAR 0x4e6c
+#define mmDIG5_TMDS_CONTROL_CHAR 0x4f6c
+#define mmDIG6_TMDS_CONTROL_CHAR 0x546c
+#define mmDIG7_TMDS_CONTROL_CHAR 0x566c
+#define mmDIG8_TMDS_CONTROL_CHAR 0x576c
+#define mmTMDS_CONTROL0_FEEDBACK 0x4a6d
+#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x4a6d
+#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x4b6d
+#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x4c6d
+#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x4d6d
+#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x4e6d
+#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4f6d
+#define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x546d
+#define mmDIG7_TMDS_CONTROL0_FEEDBACK 0x566d
+#define mmDIG8_TMDS_CONTROL0_FEEDBACK 0x576d
+#define mmTMDS_STEREOSYNC_CTL_SEL 0x4a6e
+#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x4a6e
+#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x4b6e
+#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x4c6e
+#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x4d6e
+#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x4e6e
+#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4f6e
+#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x546e
+#define mmDIG7_TMDS_STEREOSYNC_CTL_SEL 0x566e
+#define mmDIG8_TMDS_STEREOSYNC_CTL_SEL 0x576e
+#define mmTMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x4b6f
+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4c6f
+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4d6f
+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4e6f
+#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4f6f
+#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x546f
+#define mmDIG7_TMDS_SYNC_CHAR_PATTERN_0_1 0x566f
+#define mmDIG8_TMDS_SYNC_CHAR_PATTERN_0_1 0x576f
+#define mmTMDS_SYNC_CHAR_PATTERN_2_3 0x4a70
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x4a70
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x4b70
+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4c70
+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4d70
+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4e70
+#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4f70
+#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x5470
+#define mmDIG7_TMDS_SYNC_CHAR_PATTERN_2_3 0x5670
+#define mmDIG8_TMDS_SYNC_CHAR_PATTERN_2_3 0x5770
+#define mmTMDS_DEBUG 0x4a71
+#define mmDIG0_TMDS_DEBUG 0x4a71
+#define mmDIG1_TMDS_DEBUG 0x4b71
+#define mmDIG2_TMDS_DEBUG 0x4c71
+#define mmDIG3_TMDS_DEBUG 0x4d71
+#define mmDIG4_TMDS_DEBUG 0x4e71
+#define mmDIG5_TMDS_DEBUG 0x4f71
+#define mmDIG6_TMDS_DEBUG 0x5471
+#define mmDIG7_TMDS_DEBUG 0x5671
+#define mmDIG8_TMDS_DEBUG 0x5771
+#define mmTMDS_CTL_BITS 0x4a72
+#define mmDIG0_TMDS_CTL_BITS 0x4a72
+#define mmDIG1_TMDS_CTL_BITS 0x4b72
+#define mmDIG2_TMDS_CTL_BITS 0x4c72
+#define mmDIG3_TMDS_CTL_BITS 0x4d72
+#define mmDIG4_TMDS_CTL_BITS 0x4e72
+#define mmDIG5_TMDS_CTL_BITS 0x4f72
+#define mmDIG6_TMDS_CTL_BITS 0x5472
+#define mmDIG7_TMDS_CTL_BITS 0x5672
+#define mmDIG8_TMDS_CTL_BITS 0x5772
+#define mmTMDS_DCBALANCER_CONTROL 0x4a73
+#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x4a73
+#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x4b73
+#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x4c73
+#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x4d73
+#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x4e73
+#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4f73
+#define mmDIG6_TMDS_DCBALANCER_CONTROL 0x5473
+#define mmDIG7_TMDS_DCBALANCER_CONTROL 0x5673
+#define mmDIG8_TMDS_DCBALANCER_CONTROL 0x5773
+#define mmTMDS_CTL0_1_GEN_CNTL 0x4a75
+#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x4a75
+#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x4b75
+#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4c75
+#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4d75
+#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4e75
+#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4f75
+#define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x5475
+#define mmDIG7_TMDS_CTL0_1_GEN_CNTL 0x5675
+#define mmDIG8_TMDS_CTL0_1_GEN_CNTL 0x5775
+#define mmTMDS_CTL2_3_GEN_CNTL 0x4a76
+#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x4a76
+#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x4b76
+#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4c76
+#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4d76
+#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4e76
+#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4f76
+#define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x5476
+#define mmDIG7_TMDS_CTL2_3_GEN_CNTL 0x5676
+#define mmDIG8_TMDS_CTL2_3_GEN_CNTL 0x5776
+#define mmDIG_VERSION 0x4a78
+#define mmDIG0_DIG_VERSION 0x4a78
+#define mmDIG1_DIG_VERSION 0x4b78
+#define mmDIG2_DIG_VERSION 0x4c78
+#define mmDIG3_DIG_VERSION 0x4d78
+#define mmDIG4_DIG_VERSION 0x4e78
+#define mmDIG5_DIG_VERSION 0x4f78
+#define mmDIG6_DIG_VERSION 0x5478
+#define mmDIG7_DIG_VERSION 0x5678
+#define mmDIG8_DIG_VERSION 0x5778
+#define mmDIG_LANE_ENABLE 0x4a79
+#define mmDIG0_DIG_LANE_ENABLE 0x4a79
+#define mmDIG1_DIG_LANE_ENABLE 0x4b79
+#define mmDIG2_DIG_LANE_ENABLE 0x4c79
+#define mmDIG3_DIG_LANE_ENABLE 0x4d79
+#define mmDIG4_DIG_LANE_ENABLE 0x4e79
+#define mmDIG5_DIG_LANE_ENABLE 0x4f79
+#define mmDIG6_DIG_LANE_ENABLE 0x5479
+#define mmDIG7_DIG_LANE_ENABLE 0x5679
+#define mmDIG8_DIG_LANE_ENABLE 0x5779
+#define mmDIG_TEST_DEBUG_INDEX 0x4a7a
+#define mmDIG0_DIG_TEST_DEBUG_INDEX 0x4a7a
+#define mmDIG1_DIG_TEST_DEBUG_INDEX 0x4b7a
+#define mmDIG2_DIG_TEST_DEBUG_INDEX 0x4c7a
+#define mmDIG3_DIG_TEST_DEBUG_INDEX 0x4d7a
+#define mmDIG4_DIG_TEST_DEBUG_INDEX 0x4e7a
+#define mmDIG5_DIG_TEST_DEBUG_INDEX 0x4f7a
+#define mmDIG6_DIG_TEST_DEBUG_INDEX 0x547a
+#define mmDIG7_DIG_TEST_DEBUG_INDEX 0x567a
+#define mmDIG8_DIG_TEST_DEBUG_INDEX 0x577a
+#define mmDIG_TEST_DEBUG_DATA 0x4a7b
+#define mmDIG0_DIG_TEST_DEBUG_DATA 0x4a7b
+#define mmDIG1_DIG_TEST_DEBUG_DATA 0x4b7b
+#define mmDIG2_DIG_TEST_DEBUG_DATA 0x4c7b
+#define mmDIG3_DIG_TEST_DEBUG_DATA 0x4d7b
+#define mmDIG4_DIG_TEST_DEBUG_DATA 0x4e7b
+#define mmDIG5_DIG_TEST_DEBUG_DATA 0x4f7b
+#define mmDIG6_DIG_TEST_DEBUG_DATA 0x547b
+#define mmDIG7_DIG_TEST_DEBUG_DATA 0x567b
+#define mmDIG8_DIG_TEST_DEBUG_DATA 0x577b
+#define mmDIG_FE_TEST_DEBUG_INDEX 0x4a7c
+#define mmDIG0_DIG_FE_TEST_DEBUG_INDEX 0x4a7c
+#define mmDIG1_DIG_FE_TEST_DEBUG_INDEX 0x4b7c
+#define mmDIG2_DIG_FE_TEST_DEBUG_INDEX 0x4c7c
+#define mmDIG3_DIG_FE_TEST_DEBUG_INDEX 0x4d7c
+#define mmDIG4_DIG_FE_TEST_DEBUG_INDEX 0x4e7c
+#define mmDIG5_DIG_FE_TEST_DEBUG_INDEX 0x4f7c
+#define mmDIG6_DIG_FE_TEST_DEBUG_INDEX 0x547c
+#define mmDIG7_DIG_FE_TEST_DEBUG_INDEX 0x567c
+#define mmDIG8_DIG_FE_TEST_DEBUG_INDEX 0x577c
+#define mmDIG_FE_TEST_DEBUG_DATA 0x4a7d
+#define mmDIG0_DIG_FE_TEST_DEBUG_DATA 0x4a7d
+#define mmDIG1_DIG_FE_TEST_DEBUG_DATA 0x4b7d
+#define mmDIG2_DIG_FE_TEST_DEBUG_DATA 0x4c7d
+#define mmDIG3_DIG_FE_TEST_DEBUG_DATA 0x4d7d
+#define mmDIG4_DIG_FE_TEST_DEBUG_DATA 0x4e7d
+#define mmDIG5_DIG_FE_TEST_DEBUG_DATA 0x4f7d
+#define mmDIG6_DIG_FE_TEST_DEBUG_DATA 0x547d
+#define mmDIG7_DIG_FE_TEST_DEBUG_DATA 0x567d
+#define mmDIG8_DIG_FE_TEST_DEBUG_DATA 0x577d
+#define mmDMCU_CTRL 0x1600
+#define mmDMCU_STATUS 0x1601
+#define mmDMCU_PC_START_ADDR 0x1602
+#define mmDMCU_FW_START_ADDR 0x1603
+#define mmDMCU_FW_END_ADDR 0x1604
+#define mmDMCU_FW_ISR_START_ADDR 0x1605
+#define mmDMCU_FW_CS_HI 0x1606
+#define mmDMCU_FW_CS_LO 0x1607
+#define mmDMCU_RAM_ACCESS_CTRL 0x1608
+#define mmDMCU_ERAM_WR_CTRL 0x1609
+#define mmDMCU_ERAM_WR_DATA 0x160a
+#define mmDMCU_ERAM_RD_CTRL 0x160b
+#define mmDMCU_ERAM_RD_DATA 0x160c
+#define mmDMCU_IRAM_WR_CTRL 0x160d
+#define mmDMCU_IRAM_WR_DATA 0x160e
+#define mmDMCU_IRAM_RD_CTRL 0x160f
+#define mmDMCU_IRAM_RD_DATA 0x1610
+#define mmDMCU_EVENT_TRIGGER 0x1611
+#define mmDMCU_UC_INTERNAL_INT_STATUS 0x1612
+#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x1613
+#define mmDMCU_INTERRUPT_STATUS 0x1614
+#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x1631
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x1632
+#define mmDC_DMCU_SCRATCH 0x1618
+#define mmDMCU_INT_CNT 0x1619
+#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161a
+#define mmDMCU_UC_CLK_GATING_CNTL 0x161b
+#define mmMASTER_COMM_DATA_REG1 0x161c
+#define mmMASTER_COMM_DATA_REG2 0x161d
+#define mmMASTER_COMM_DATA_REG3 0x161e
+#define mmMASTER_COMM_CMD_REG 0x161f
+#define mmMASTER_COMM_CNTL_REG 0x1620
+#define mmSLAVE_COMM_DATA_REG1 0x1621
+#define mmSLAVE_COMM_DATA_REG2 0x1622
+#define mmSLAVE_COMM_DATA_REG3 0x1623
+#define mmSLAVE_COMM_CMD_REG 0x1624
+#define mmSLAVE_COMM_CNTL_REG 0x1625
+#define mmDMCU_TEST_DEBUG_INDEX 0x1626
+#define mmDMCU_TEST_DEBUG_DATA 0x1627
+#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x1644
+#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x1645
+#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x1646
+#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x1647
+#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x1642
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x1674
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x1675
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x1676
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x1677
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x1643
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1678
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x1679
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x167a
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x167b
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x1673
+#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x1634
+#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x1635
+#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1636
+#define mmDP_LINK_CNTL 0x4aa0
+#define mmDP0_DP_LINK_CNTL 0x4aa0
+#define mmDP1_DP_LINK_CNTL 0x4ba0
+#define mmDP2_DP_LINK_CNTL 0x4ca0
+#define mmDP3_DP_LINK_CNTL 0x4da0
+#define mmDP4_DP_LINK_CNTL 0x4ea0
+#define mmDP5_DP_LINK_CNTL 0x4fa0
+#define mmDP6_DP_LINK_CNTL 0x54a0
+#define mmDP7_DP_LINK_CNTL 0x56a0
+#define mmDP8_DP_LINK_CNTL 0x57a0
+#define mmDP_PIXEL_FORMAT 0x4aa1
+#define mmDP0_DP_PIXEL_FORMAT 0x4aa1
+#define mmDP1_DP_PIXEL_FORMAT 0x4ba1
+#define mmDP2_DP_PIXEL_FORMAT 0x4ca1
+#define mmDP3_DP_PIXEL_FORMAT 0x4da1
+#define mmDP4_DP_PIXEL_FORMAT 0x4ea1
+#define mmDP5_DP_PIXEL_FORMAT 0x4fa1
+#define mmDP6_DP_PIXEL_FORMAT 0x54a1
+#define mmDP7_DP_PIXEL_FORMAT 0x56a1
+#define mmDP8_DP_PIXEL_FORMAT 0x57a1
+#define mmDP_MSA_COLORIMETRY 0x4aa2
+#define mmDP0_DP_MSA_COLORIMETRY 0x4aa2
+#define mmDP1_DP_MSA_COLORIMETRY 0x4ba2
+#define mmDP2_DP_MSA_COLORIMETRY 0x4ca2
+#define mmDP3_DP_MSA_COLORIMETRY 0x4da2
+#define mmDP4_DP_MSA_COLORIMETRY 0x4ea2
+#define mmDP5_DP_MSA_COLORIMETRY 0x4fa2
+#define mmDP6_DP_MSA_COLORIMETRY 0x54a2
+#define mmDP7_DP_MSA_COLORIMETRY 0x56a2
+#define mmDP8_DP_MSA_COLORIMETRY 0x57a2
+#define mmDP_CONFIG 0x4aa3
+#define mmDP0_DP_CONFIG 0x4aa3
+#define mmDP1_DP_CONFIG 0x4ba3
+#define mmDP2_DP_CONFIG 0x4ca3
+#define mmDP3_DP_CONFIG 0x4da3
+#define mmDP4_DP_CONFIG 0x4ea3
+#define mmDP5_DP_CONFIG 0x4fa3
+#define mmDP6_DP_CONFIG 0x54a3
+#define mmDP7_DP_CONFIG 0x56a3
+#define mmDP8_DP_CONFIG 0x57a3
+#define mmDP_VID_STREAM_CNTL 0x4aa4
+#define mmDP0_DP_VID_STREAM_CNTL 0x4aa4
+#define mmDP1_DP_VID_STREAM_CNTL 0x4ba4
+#define mmDP2_DP_VID_STREAM_CNTL 0x4ca4
+#define mmDP3_DP_VID_STREAM_CNTL 0x4da4
+#define mmDP4_DP_VID_STREAM_CNTL 0x4ea4
+#define mmDP5_DP_VID_STREAM_CNTL 0x4fa4
+#define mmDP6_DP_VID_STREAM_CNTL 0x54a4
+#define mmDP7_DP_VID_STREAM_CNTL 0x56a4
+#define mmDP8_DP_VID_STREAM_CNTL 0x57a4
+#define mmDP_STEER_FIFO 0x4aa5
+#define mmDP0_DP_STEER_FIFO 0x4aa5
+#define mmDP1_DP_STEER_FIFO 0x4ba5
+#define mmDP2_DP_STEER_FIFO 0x4ca5
+#define mmDP3_DP_STEER_FIFO 0x4da5
+#define mmDP4_DP_STEER_FIFO 0x4ea5
+#define mmDP5_DP_STEER_FIFO 0x4fa5
+#define mmDP6_DP_STEER_FIFO 0x54a5
+#define mmDP7_DP_STEER_FIFO 0x56a5
+#define mmDP8_DP_STEER_FIFO 0x57a5
+#define mmDP_MSA_MISC 0x4aa6
+#define mmDP0_DP_MSA_MISC 0x4aa6
+#define mmDP1_DP_MSA_MISC 0x4ba6
+#define mmDP2_DP_MSA_MISC 0x4ca6
+#define mmDP3_DP_MSA_MISC 0x4da6
+#define mmDP4_DP_MSA_MISC 0x4ea6
+#define mmDP5_DP_MSA_MISC 0x4fa6
+#define mmDP6_DP_MSA_MISC 0x54a6
+#define mmDP7_DP_MSA_MISC 0x56a6
+#define mmDP8_DP_MSA_MISC 0x57a6
+#define mmDP_VID_TIMING 0x4aa8
+#define mmDP0_DP_VID_TIMING 0x4aa8
+#define mmDP1_DP_VID_TIMING 0x4ba8
+#define mmDP2_DP_VID_TIMING 0x4ca8
+#define mmDP3_DP_VID_TIMING 0x4da8
+#define mmDP4_DP_VID_TIMING 0x4ea8
+#define mmDP5_DP_VID_TIMING 0x4fa8
+#define mmDP6_DP_VID_TIMING 0x54a8
+#define mmDP7_DP_VID_TIMING 0x56a8
+#define mmDP8_DP_VID_TIMING 0x57a8
+#define mmDP_VID_N 0x4aa9
+#define mmDP0_DP_VID_N 0x4aa9
+#define mmDP1_DP_VID_N 0x4ba9
+#define mmDP2_DP_VID_N 0x4ca9
+#define mmDP3_DP_VID_N 0x4da9
+#define mmDP4_DP_VID_N 0x4ea9
+#define mmDP5_DP_VID_N 0x4fa9
+#define mmDP6_DP_VID_N 0x54a9
+#define mmDP7_DP_VID_N 0x56a9
+#define mmDP8_DP_VID_N 0x57a9
+#define mmDP_VID_M 0x4aaa
+#define mmDP0_DP_VID_M 0x4aaa
+#define mmDP1_DP_VID_M 0x4baa
+#define mmDP2_DP_VID_M 0x4caa
+#define mmDP3_DP_VID_M 0x4daa
+#define mmDP4_DP_VID_M 0x4eaa
+#define mmDP5_DP_VID_M 0x4faa
+#define mmDP6_DP_VID_M 0x54aa
+#define mmDP7_DP_VID_M 0x56aa
+#define mmDP8_DP_VID_M 0x57aa
+#define mmDP_LINK_FRAMING_CNTL 0x4aab
+#define mmDP0_DP_LINK_FRAMING_CNTL 0x4aab
+#define mmDP1_DP_LINK_FRAMING_CNTL 0x4bab
+#define mmDP2_DP_LINK_FRAMING_CNTL 0x4cab
+#define mmDP3_DP_LINK_FRAMING_CNTL 0x4dab
+#define mmDP4_DP_LINK_FRAMING_CNTL 0x4eab
+#define mmDP5_DP_LINK_FRAMING_CNTL 0x4fab
+#define mmDP6_DP_LINK_FRAMING_CNTL 0x54ab
+#define mmDP7_DP_LINK_FRAMING_CNTL 0x56ab
+#define mmDP8_DP_LINK_FRAMING_CNTL 0x57ab
+#define mmDP_HBR2_EYE_PATTERN 0x4aac
+#define mmDP0_DP_HBR2_EYE_PATTERN 0x4aac
+#define mmDP1_DP_HBR2_EYE_PATTERN 0x4bac
+#define mmDP2_DP_HBR2_EYE_PATTERN 0x4cac
+#define mmDP3_DP_HBR2_EYE_PATTERN 0x4dac
+#define mmDP4_DP_HBR2_EYE_PATTERN 0x4eac
+#define mmDP5_DP_HBR2_EYE_PATTERN 0x4fac
+#define mmDP6_DP_HBR2_EYE_PATTERN 0x54ac
+#define mmDP7_DP_HBR2_EYE_PATTERN 0x56ac
+#define mmDP8_DP_HBR2_EYE_PATTERN 0x57ac
+#define mmDP_VID_MSA_VBID 0x4aad
+#define mmDP0_DP_VID_MSA_VBID 0x4aad
+#define mmDP1_DP_VID_MSA_VBID 0x4bad
+#define mmDP2_DP_VID_MSA_VBID 0x4cad
+#define mmDP3_DP_VID_MSA_VBID 0x4dad
+#define mmDP4_DP_VID_MSA_VBID 0x4ead
+#define mmDP5_DP_VID_MSA_VBID 0x4fad
+#define mmDP6_DP_VID_MSA_VBID 0x54ad
+#define mmDP7_DP_VID_MSA_VBID 0x56ad
+#define mmDP8_DP_VID_MSA_VBID 0x57ad
+#define mmDP_VID_INTERRUPT_CNTL 0x4aae
+#define mmDP0_DP_VID_INTERRUPT_CNTL 0x4aae
+#define mmDP1_DP_VID_INTERRUPT_CNTL 0x4bae
+#define mmDP2_DP_VID_INTERRUPT_CNTL 0x4cae
+#define mmDP3_DP_VID_INTERRUPT_CNTL 0x4dae
+#define mmDP4_DP_VID_INTERRUPT_CNTL 0x4eae
+#define mmDP5_DP_VID_INTERRUPT_CNTL 0x4fae
+#define mmDP6_DP_VID_INTERRUPT_CNTL 0x54ae
+#define mmDP7_DP_VID_INTERRUPT_CNTL 0x56ae
+#define mmDP8_DP_VID_INTERRUPT_CNTL 0x57ae
+#define mmDP_DPHY_CNTL 0x4aaf
+#define mmDP0_DP_DPHY_CNTL 0x4aaf
+#define mmDP1_DP_DPHY_CNTL 0x4baf
+#define mmDP2_DP_DPHY_CNTL 0x4caf
+#define mmDP3_DP_DPHY_CNTL 0x4daf
+#define mmDP4_DP_DPHY_CNTL 0x4eaf
+#define mmDP5_DP_DPHY_CNTL 0x4faf
+#define mmDP6_DP_DPHY_CNTL 0x54af
+#define mmDP7_DP_DPHY_CNTL 0x56af
+#define mmDP8_DP_DPHY_CNTL 0x57af
+#define mmDP_DPHY_TRAINING_PATTERN_SEL 0x4ab0
+#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x4ab0
+#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x4bb0
+#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x4cb0
+#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x4db0
+#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x4eb0
+#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4fb0
+#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x54b0
+#define mmDP7_DP_DPHY_TRAINING_PATTERN_SEL 0x56b0
+#define mmDP8_DP_DPHY_TRAINING_PATTERN_SEL 0x57b0
+#define mmDP_DPHY_SYM0 0x4ab1
+#define mmDP0_DP_DPHY_SYM0 0x4ab1
+#define mmDP1_DP_DPHY_SYM0 0x4bb1
+#define mmDP2_DP_DPHY_SYM0 0x4cb1
+#define mmDP3_DP_DPHY_SYM0 0x4db1
+#define mmDP4_DP_DPHY_SYM0 0x4eb1
+#define mmDP5_DP_DPHY_SYM0 0x4fb1
+#define mmDP6_DP_DPHY_SYM0 0x54b1
+#define mmDP7_DP_DPHY_SYM0 0x56b1
+#define mmDP8_DP_DPHY_SYM0 0x57b1
+#define mmDP_DPHY_SYM1 0x4ab2
+#define mmDP0_DP_DPHY_SYM1 0x4ab2
+#define mmDP1_DP_DPHY_SYM1 0x4bb2
+#define mmDP2_DP_DPHY_SYM1 0x4cb2
+#define mmDP3_DP_DPHY_SYM1 0x4db2
+#define mmDP4_DP_DPHY_SYM1 0x4eb2
+#define mmDP5_DP_DPHY_SYM1 0x4fb2
+#define mmDP6_DP_DPHY_SYM1 0x54b2
+#define mmDP7_DP_DPHY_SYM1 0x56b2
+#define mmDP8_DP_DPHY_SYM1 0x57b2
+#define mmDP_DPHY_SYM2 0x4ab3
+#define mmDP0_DP_DPHY_SYM2 0x4ab3
+#define mmDP1_DP_DPHY_SYM2 0x4bb3
+#define mmDP2_DP_DPHY_SYM2 0x4cb3
+#define mmDP3_DP_DPHY_SYM2 0x4db3
+#define mmDP4_DP_DPHY_SYM2 0x4eb3
+#define mmDP5_DP_DPHY_SYM2 0x4fb3
+#define mmDP6_DP_DPHY_SYM2 0x54b3
+#define mmDP7_DP_DPHY_SYM2 0x56b3
+#define mmDP8_DP_DPHY_SYM2 0x57b3
+#define mmDP_DPHY_8B10B_CNTL 0x4ab4
+#define mmDP0_DP_DPHY_8B10B_CNTL 0x4ab4
+#define mmDP1_DP_DPHY_8B10B_CNTL 0x4bb4
+#define mmDP2_DP_DPHY_8B10B_CNTL 0x4cb4
+#define mmDP3_DP_DPHY_8B10B_CNTL 0x4db4
+#define mmDP4_DP_DPHY_8B10B_CNTL 0x4eb4
+#define mmDP5_DP_DPHY_8B10B_CNTL 0x4fb4
+#define mmDP6_DP_DPHY_8B10B_CNTL 0x54b4
+#define mmDP7_DP_DPHY_8B10B_CNTL 0x56b4
+#define mmDP8_DP_DPHY_8B10B_CNTL 0x57b4
+#define mmDP_DPHY_PRBS_CNTL 0x4ab5
+#define mmDP0_DP_DPHY_PRBS_CNTL 0x4ab5
+#define mmDP1_DP_DPHY_PRBS_CNTL 0x4bb5
+#define mmDP2_DP_DPHY_PRBS_CNTL 0x4cb5
+#define mmDP3_DP_DPHY_PRBS_CNTL 0x4db5
+#define mmDP4_DP_DPHY_PRBS_CNTL 0x4eb5
+#define mmDP5_DP_DPHY_PRBS_CNTL 0x4fb5
+#define mmDP6_DP_DPHY_PRBS_CNTL 0x54b5
+#define mmDP7_DP_DPHY_PRBS_CNTL 0x56b5
+#define mmDP8_DP_DPHY_PRBS_CNTL 0x57b5
+#define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4adc
+#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4adc
+#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4bdc
+#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4cdc
+#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4ddc
+#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4edc
+#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4fdc
+#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54dc
+#define mmDP7_DP_DPHY_BS_SR_SWAP_CNTL 0x56dc
+#define mmDP8_DP_DPHY_BS_SR_SWAP_CNTL 0x57dc
+#define mmDP_DPHY_CRC_EN 0x4ab7
+#define mmDP0_DP_DPHY_CRC_EN 0x4ab7
+#define mmDP1_DP_DPHY_CRC_EN 0x4bb7
+#define mmDP2_DP_DPHY_CRC_EN 0x4cb7
+#define mmDP3_DP_DPHY_CRC_EN 0x4db7
+#define mmDP4_DP_DPHY_CRC_EN 0x4eb7
+#define mmDP5_DP_DPHY_CRC_EN 0x4fb7
+#define mmDP6_DP_DPHY_CRC_EN 0x54b7
+#define mmDP7_DP_DPHY_CRC_EN 0x56b7
+#define mmDP8_DP_DPHY_CRC_EN 0x57b7
+#define mmDP_DPHY_CRC_CNTL 0x4ab8
+#define mmDP0_DP_DPHY_CRC_CNTL 0x4ab8
+#define mmDP1_DP_DPHY_CRC_CNTL 0x4bb8
+#define mmDP2_DP_DPHY_CRC_CNTL 0x4cb8
+#define mmDP3_DP_DPHY_CRC_CNTL 0x4db8
+#define mmDP4_DP_DPHY_CRC_CNTL 0x4eb8
+#define mmDP5_DP_DPHY_CRC_CNTL 0x4fb8
+#define mmDP6_DP_DPHY_CRC_CNTL 0x54b8
+#define mmDP7_DP_DPHY_CRC_CNTL 0x56b8
+#define mmDP8_DP_DPHY_CRC_CNTL 0x57b8
+#define mmDP_DPHY_CRC_RESULT 0x4ab9
+#define mmDP0_DP_DPHY_CRC_RESULT 0x4ab9
+#define mmDP1_DP_DPHY_CRC_RESULT 0x4bb9
+#define mmDP2_DP_DPHY_CRC_RESULT 0x4cb9
+#define mmDP3_DP_DPHY_CRC_RESULT 0x4db9
+#define mmDP4_DP_DPHY_CRC_RESULT 0x4eb9
+#define mmDP5_DP_DPHY_CRC_RESULT 0x4fb9
+#define mmDP6_DP_DPHY_CRC_RESULT 0x54b9
+#define mmDP7_DP_DPHY_CRC_RESULT 0x56b9
+#define mmDP8_DP_DPHY_CRC_RESULT 0x57b9
+#define mmDP_DPHY_CRC_MST_CNTL 0x4aba
+#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x4aba
+#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x4bba
+#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x4cba
+#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x4dba
+#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x4eba
+#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x4fba
+#define mmDP6_DP_DPHY_CRC_MST_CNTL 0x54ba
+#define mmDP7_DP_DPHY_CRC_MST_CNTL 0x56ba
+#define mmDP8_DP_DPHY_CRC_MST_CNTL 0x57ba
+#define mmDP_DPHY_CRC_MST_STATUS 0x4abb
+#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x4abb
+#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x4bbb
+#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x4cbb
+#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x4dbb
+#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x4ebb
+#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x4fbb
+#define mmDP6_DP_DPHY_CRC_MST_STATUS 0x54bb
+#define mmDP7_DP_DPHY_CRC_MST_STATUS 0x56bb
+#define mmDP8_DP_DPHY_CRC_MST_STATUS 0x57bb
+#define mmDP_DPHY_FAST_TRAINING 0x4abc
+#define mmDP0_DP_DPHY_FAST_TRAINING 0x4abc
+#define mmDP1_DP_DPHY_FAST_TRAINING 0x4bbc
+#define mmDP2_DP_DPHY_FAST_TRAINING 0x4cbc
+#define mmDP3_DP_DPHY_FAST_TRAINING 0x4dbc
+#define mmDP4_DP_DPHY_FAST_TRAINING 0x4ebc
+#define mmDP5_DP_DPHY_FAST_TRAINING 0x4fbc
+#define mmDP6_DP_DPHY_FAST_TRAINING 0x54bc
+#define mmDP7_DP_DPHY_FAST_TRAINING 0x56bc
+#define mmDP8_DP_DPHY_FAST_TRAINING 0x57bc
+#define mmDP_DPHY_FAST_TRAINING_STATUS 0x4abd
+#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x4abd
+#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x4bbd
+#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x4cbd
+#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x4dbd
+#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x4ebd
+#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4fbd
+#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x54bd
+#define mmDP7_DP_DPHY_FAST_TRAINING_STATUS 0x56bd
+#define mmDP8_DP_DPHY_FAST_TRAINING_STATUS 0x57bd
+#define mmDP_DPHY_HBR2_PATTERN_CONTROL 0x4add
+#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x4add
+#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x4bdd
+#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x4cdd
+#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x4ddd
+#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x4edd
+#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x4fdd
+#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL 0x54dd
+#define mmDP7_DP_DPHY_HBR2_PATTERN_CONTROL 0x56dd
+#define mmDP8_DP_DPHY_HBR2_PATTERN_CONTROL 0x57dd
+#define mmDP_MSA_V_TIMING_OVERRIDE1 0x4abe
+#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x4abe
+#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x4bbe
+#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x4cbe
+#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x4dbe
+#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x4ebe
+#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4fbe
+#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x54be
+#define mmDP7_DP_MSA_V_TIMING_OVERRIDE1 0x56be
+#define mmDP8_DP_MSA_V_TIMING_OVERRIDE1 0x57be
+#define mmDP_MSA_V_TIMING_OVERRIDE2 0x4abf
+#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x4abf
+#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x4bbf
+#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x4cbf
+#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x4dbf
+#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x4ebf
+#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4fbf
+#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x54bf
+#define mmDP7_DP_MSA_V_TIMING_OVERRIDE2 0x56bf
+#define mmDP8_DP_MSA_V_TIMING_OVERRIDE2 0x57bf
+#define mmDP_SEC_CNTL 0x4ac3
+#define mmDP0_DP_SEC_CNTL 0x4ac3
+#define mmDP1_DP_SEC_CNTL 0x4bc3
+#define mmDP2_DP_SEC_CNTL 0x4cc3
+#define mmDP3_DP_SEC_CNTL 0x4dc3
+#define mmDP4_DP_SEC_CNTL 0x4ec3
+#define mmDP5_DP_SEC_CNTL 0x4fc3
+#define mmDP6_DP_SEC_CNTL 0x54c3
+#define mmDP7_DP_SEC_CNTL 0x56c3
+#define mmDP8_DP_SEC_CNTL 0x57c3
+#define mmDP_SEC_CNTL1 0x4ac4
+#define mmDP0_DP_SEC_CNTL1 0x4ac4
+#define mmDP1_DP_SEC_CNTL1 0x4bc4
+#define mmDP2_DP_SEC_CNTL1 0x4cc4
+#define mmDP3_DP_SEC_CNTL1 0x4dc4
+#define mmDP4_DP_SEC_CNTL1 0x4ec4
+#define mmDP5_DP_SEC_CNTL1 0x4fc4
+#define mmDP6_DP_SEC_CNTL1 0x54c4
+#define mmDP7_DP_SEC_CNTL1 0x56c4
+#define mmDP8_DP_SEC_CNTL1 0x57c4
+#define mmDP_SEC_FRAMING1 0x4ac5
+#define mmDP0_DP_SEC_FRAMING1 0x4ac5
+#define mmDP1_DP_SEC_FRAMING1 0x4bc5
+#define mmDP2_DP_SEC_FRAMING1 0x4cc5
+#define mmDP3_DP_SEC_FRAMING1 0x4dc5
+#define mmDP4_DP_SEC_FRAMING1 0x4ec5
+#define mmDP5_DP_SEC_FRAMING1 0x4fc5
+#define mmDP6_DP_SEC_FRAMING1 0x54c5
+#define mmDP7_DP_SEC_FRAMING1 0x56c5
+#define mmDP8_DP_SEC_FRAMING1 0x57c5
+#define mmDP_SEC_FRAMING2 0x4ac6
+#define mmDP0_DP_SEC_FRAMING2 0x4ac6
+#define mmDP1_DP_SEC_FRAMING2 0x4bc6
+#define mmDP2_DP_SEC_FRAMING2 0x4cc6
+#define mmDP3_DP_SEC_FRAMING2 0x4dc6
+#define mmDP4_DP_SEC_FRAMING2 0x4ec6
+#define mmDP5_DP_SEC_FRAMING2 0x4fc6
+#define mmDP6_DP_SEC_FRAMING2 0x54c6
+#define mmDP7_DP_SEC_FRAMING2 0x56c6
+#define mmDP8_DP_SEC_FRAMING2 0x57c6
+#define mmDP_SEC_FRAMING3 0x4ac7
+#define mmDP0_DP_SEC_FRAMING3 0x4ac7
+#define mmDP1_DP_SEC_FRAMING3 0x4bc7
+#define mmDP2_DP_SEC_FRAMING3 0x4cc7
+#define mmDP3_DP_SEC_FRAMING3 0x4dc7
+#define mmDP4_DP_SEC_FRAMING3 0x4ec7
+#define mmDP5_DP_SEC_FRAMING3 0x4fc7
+#define mmDP6_DP_SEC_FRAMING3 0x54c7
+#define mmDP7_DP_SEC_FRAMING3 0x56c7
+#define mmDP8_DP_SEC_FRAMING3 0x57c7
+#define mmDP_SEC_FRAMING4 0x4ac8
+#define mmDP0_DP_SEC_FRAMING4 0x4ac8
+#define mmDP1_DP_SEC_FRAMING4 0x4bc8
+#define mmDP2_DP_SEC_FRAMING4 0x4cc8
+#define mmDP3_DP_SEC_FRAMING4 0x4dc8
+#define mmDP4_DP_SEC_FRAMING4 0x4ec8
+#define mmDP5_DP_SEC_FRAMING4 0x4fc8
+#define mmDP6_DP_SEC_FRAMING4 0x54c8
+#define mmDP7_DP_SEC_FRAMING4 0x56c8
+#define mmDP8_DP_SEC_FRAMING4 0x57c8
+#define mmDP_SEC_AUD_N 0x4ac9
+#define mmDP0_DP_SEC_AUD_N 0x4ac9
+#define mmDP1_DP_SEC_AUD_N 0x4bc9
+#define mmDP2_DP_SEC_AUD_N 0x4cc9
+#define mmDP3_DP_SEC_AUD_N 0x4dc9
+#define mmDP4_DP_SEC_AUD_N 0x4ec9
+#define mmDP5_DP_SEC_AUD_N 0x4fc9
+#define mmDP6_DP_SEC_AUD_N 0x54c9
+#define mmDP7_DP_SEC_AUD_N 0x56c9
+#define mmDP8_DP_SEC_AUD_N 0x57c9
+#define mmDP_SEC_AUD_N_READBACK 0x4aca
+#define mmDP0_DP_SEC_AUD_N_READBACK 0x4aca
+#define mmDP1_DP_SEC_AUD_N_READBACK 0x4bca
+#define mmDP2_DP_SEC_AUD_N_READBACK 0x4cca
+#define mmDP3_DP_SEC_AUD_N_READBACK 0x4dca
+#define mmDP4_DP_SEC_AUD_N_READBACK 0x4eca
+#define mmDP5_DP_SEC_AUD_N_READBACK 0x4fca
+#define mmDP6_DP_SEC_AUD_N_READBACK 0x54ca
+#define mmDP7_DP_SEC_AUD_N_READBACK 0x56ca
+#define mmDP8_DP_SEC_AUD_N_READBACK 0x57ca
+#define mmDP_SEC_AUD_M 0x4acb
+#define mmDP0_DP_SEC_AUD_M 0x4acb
+#define mmDP1_DP_SEC_AUD_M 0x4bcb
+#define mmDP2_DP_SEC_AUD_M 0x4ccb
+#define mmDP3_DP_SEC_AUD_M 0x4dcb
+#define mmDP4_DP_SEC_AUD_M 0x4ecb
+#define mmDP5_DP_SEC_AUD_M 0x4fcb
+#define mmDP6_DP_SEC_AUD_M 0x54cb
+#define mmDP7_DP_SEC_AUD_M 0x56cb
+#define mmDP8_DP_SEC_AUD_M 0x57cb
+#define mmDP_SEC_AUD_M_READBACK 0x4acc
+#define mmDP0_DP_SEC_AUD_M_READBACK 0x4acc
+#define mmDP1_DP_SEC_AUD_M_READBACK 0x4bcc
+#define mmDP2_DP_SEC_AUD_M_READBACK 0x4ccc
+#define mmDP3_DP_SEC_AUD_M_READBACK 0x4dcc
+#define mmDP4_DP_SEC_AUD_M_READBACK 0x4ecc
+#define mmDP5_DP_SEC_AUD_M_READBACK 0x4fcc
+#define mmDP6_DP_SEC_AUD_M_READBACK 0x54cc
+#define mmDP7_DP_SEC_AUD_M_READBACK 0x56cc
+#define mmDP8_DP_SEC_AUD_M_READBACK 0x57cc
+#define mmDP_SEC_TIMESTAMP 0x4acd
+#define mmDP0_DP_SEC_TIMESTAMP 0x4acd
+#define mmDP1_DP_SEC_TIMESTAMP 0x4bcd
+#define mmDP2_DP_SEC_TIMESTAMP 0x4ccd
+#define mmDP3_DP_SEC_TIMESTAMP 0x4dcd
+#define mmDP4_DP_SEC_TIMESTAMP 0x4ecd
+#define mmDP5_DP_SEC_TIMESTAMP 0x4fcd
+#define mmDP6_DP_SEC_TIMESTAMP 0x54cd
+#define mmDP7_DP_SEC_TIMESTAMP 0x56cd
+#define mmDP8_DP_SEC_TIMESTAMP 0x57cd
+#define mmDP_SEC_PACKET_CNTL 0x4ace
+#define mmDP0_DP_SEC_PACKET_CNTL 0x4ace
+#define mmDP1_DP_SEC_PACKET_CNTL 0x4bce
+#define mmDP2_DP_SEC_PACKET_CNTL 0x4cce
+#define mmDP3_DP_SEC_PACKET_CNTL 0x4dce
+#define mmDP4_DP_SEC_PACKET_CNTL 0x4ece
+#define mmDP5_DP_SEC_PACKET_CNTL 0x4fce
+#define mmDP6_DP_SEC_PACKET_CNTL 0x54ce
+#define mmDP7_DP_SEC_PACKET_CNTL 0x56ce
+#define mmDP8_DP_SEC_PACKET_CNTL 0x57ce
+#define mmDP_MSE_RATE_CNTL 0x4acf
+#define mmDP0_DP_MSE_RATE_CNTL 0x4acf
+#define mmDP1_DP_MSE_RATE_CNTL 0x4bcf
+#define mmDP2_DP_MSE_RATE_CNTL 0x4ccf
+#define mmDP3_DP_MSE_RATE_CNTL 0x4dcf
+#define mmDP4_DP_MSE_RATE_CNTL 0x4ecf
+#define mmDP5_DP_MSE_RATE_CNTL 0x4fcf
+#define mmDP6_DP_MSE_RATE_CNTL 0x54cf
+#define mmDP7_DP_MSE_RATE_CNTL 0x56cf
+#define mmDP8_DP_MSE_RATE_CNTL 0x57cf
+#define mmDP_MSE_RATE_UPDATE 0x4ad1
+#define mmDP0_DP_MSE_RATE_UPDATE 0x4ad1
+#define mmDP1_DP_MSE_RATE_UPDATE 0x4bd1
+#define mmDP2_DP_MSE_RATE_UPDATE 0x4cd1
+#define mmDP3_DP_MSE_RATE_UPDATE 0x4dd1
+#define mmDP4_DP_MSE_RATE_UPDATE 0x4ed1
+#define mmDP5_DP_MSE_RATE_UPDATE 0x4fd1
+#define mmDP6_DP_MSE_RATE_UPDATE 0x54d1
+#define mmDP7_DP_MSE_RATE_UPDATE 0x56d1
+#define mmDP8_DP_MSE_RATE_UPDATE 0x57d1
+#define mmDP_MSE_SAT0 0x4ad2
+#define mmDP0_DP_MSE_SAT0 0x4ad2
+#define mmDP1_DP_MSE_SAT0 0x4bd2
+#define mmDP2_DP_MSE_SAT0 0x4cd2
+#define mmDP3_DP_MSE_SAT0 0x4dd2
+#define mmDP4_DP_MSE_SAT0 0x4ed2
+#define mmDP5_DP_MSE_SAT0 0x4fd2
+#define mmDP6_DP_MSE_SAT0 0x54d2
+#define mmDP7_DP_MSE_SAT0 0x56d2
+#define mmDP8_DP_MSE_SAT0 0x57d2
+#define mmDP_MSE_SAT1 0x4ad3
+#define mmDP0_DP_MSE_SAT1 0x4ad3
+#define mmDP1_DP_MSE_SAT1 0x4bd3
+#define mmDP2_DP_MSE_SAT1 0x4cd3
+#define mmDP3_DP_MSE_SAT1 0x4dd3
+#define mmDP4_DP_MSE_SAT1 0x4ed3
+#define mmDP5_DP_MSE_SAT1 0x4fd3
+#define mmDP6_DP_MSE_SAT1 0x54d3
+#define mmDP7_DP_MSE_SAT1 0x56d3
+#define mmDP8_DP_MSE_SAT1 0x57d3
+#define mmDP_MSE_SAT2 0x4ad4
+#define mmDP0_DP_MSE_SAT2 0x4ad4
+#define mmDP1_DP_MSE_SAT2 0x4bd4
+#define mmDP2_DP_MSE_SAT2 0x4cd4
+#define mmDP3_DP_MSE_SAT2 0x4dd4
+#define mmDP4_DP_MSE_SAT2 0x4ed4
+#define mmDP5_DP_MSE_SAT2 0x4fd4
+#define mmDP6_DP_MSE_SAT2 0x54d4
+#define mmDP7_DP_MSE_SAT2 0x56d4
+#define mmDP8_DP_MSE_SAT2 0x57d4
+#define mmDP_MSE_SAT_UPDATE 0x4ad5
+#define mmDP0_DP_MSE_SAT_UPDATE 0x4ad5
+#define mmDP1_DP_MSE_SAT_UPDATE 0x4bd5
+#define mmDP2_DP_MSE_SAT_UPDATE 0x4cd5
+#define mmDP3_DP_MSE_SAT_UPDATE 0x4dd5
+#define mmDP4_DP_MSE_SAT_UPDATE 0x4ed5
+#define mmDP5_DP_MSE_SAT_UPDATE 0x4fd5
+#define mmDP6_DP_MSE_SAT_UPDATE 0x54d5
+#define mmDP7_DP_MSE_SAT_UPDATE 0x56d5
+#define mmDP8_DP_MSE_SAT_UPDATE 0x57d5
+#define mmDP_MSE_LINK_TIMING 0x4ad6
+#define mmDP0_DP_MSE_LINK_TIMING 0x4ad6
+#define mmDP1_DP_MSE_LINK_TIMING 0x4bd6
+#define mmDP2_DP_MSE_LINK_TIMING 0x4cd6
+#define mmDP3_DP_MSE_LINK_TIMING 0x4dd6
+#define mmDP4_DP_MSE_LINK_TIMING 0x4ed6
+#define mmDP5_DP_MSE_LINK_TIMING 0x4fd6
+#define mmDP6_DP_MSE_LINK_TIMING 0x54d6
+#define mmDP7_DP_MSE_LINK_TIMING 0x56d6
+#define mmDP8_DP_MSE_LINK_TIMING 0x57d6
+#define mmDP_MSE_MISC_CNTL 0x4ad7
+#define mmDP0_DP_MSE_MISC_CNTL 0x4ad7
+#define mmDP1_DP_MSE_MISC_CNTL 0x4bd7
+#define mmDP2_DP_MSE_MISC_CNTL 0x4cd7
+#define mmDP3_DP_MSE_MISC_CNTL 0x4dd7
+#define mmDP4_DP_MSE_MISC_CNTL 0x4ed7
+#define mmDP5_DP_MSE_MISC_CNTL 0x4fd7
+#define mmDP6_DP_MSE_MISC_CNTL 0x54d7
+#define mmDP7_DP_MSE_MISC_CNTL 0x56d7
+#define mmDP8_DP_MSE_MISC_CNTL 0x57d7
+#define mmDP_TEST_DEBUG_INDEX 0x4ad8
+#define mmDP0_DP_TEST_DEBUG_INDEX 0x4ad8
+#define mmDP1_DP_TEST_DEBUG_INDEX 0x4bd8
+#define mmDP2_DP_TEST_DEBUG_INDEX 0x4cd8
+#define mmDP3_DP_TEST_DEBUG_INDEX 0x4dd8
+#define mmDP4_DP_TEST_DEBUG_INDEX 0x4ed8
+#define mmDP5_DP_TEST_DEBUG_INDEX 0x4fd8
+#define mmDP6_DP_TEST_DEBUG_INDEX 0x54d8
+#define mmDP7_DP_TEST_DEBUG_INDEX 0x56d8
+#define mmDP8_DP_TEST_DEBUG_INDEX 0x57d8
+#define mmDP_TEST_DEBUG_DATA 0x4ad9
+#define mmDP0_DP_TEST_DEBUG_DATA 0x4ad9
+#define mmDP1_DP_TEST_DEBUG_DATA 0x4bd9
+#define mmDP2_DP_TEST_DEBUG_DATA 0x4cd9
+#define mmDP3_DP_TEST_DEBUG_DATA 0x4dd9
+#define mmDP4_DP_TEST_DEBUG_DATA 0x4ed9
+#define mmDP5_DP_TEST_DEBUG_DATA 0x4fd9
+#define mmDP6_DP_TEST_DEBUG_DATA 0x54d9
+#define mmDP7_DP_TEST_DEBUG_DATA 0x56d9
+#define mmDP8_DP_TEST_DEBUG_DATA 0x57d9
+#define mmDP_FE_TEST_DEBUG_INDEX 0x4ada
+#define mmDP0_DP_FE_TEST_DEBUG_INDEX 0x4ada
+#define mmDP1_DP_FE_TEST_DEBUG_INDEX 0x4bda
+#define mmDP2_DP_FE_TEST_DEBUG_INDEX 0x4cda
+#define mmDP3_DP_FE_TEST_DEBUG_INDEX 0x4dda
+#define mmDP4_DP_FE_TEST_DEBUG_INDEX 0x4eda
+#define mmDP5_DP_FE_TEST_DEBUG_INDEX 0x4fda
+#define mmDP6_DP_FE_TEST_DEBUG_INDEX 0x54da
+#define mmDP7_DP_FE_TEST_DEBUG_INDEX 0x56da
+#define mmDP8_DP_FE_TEST_DEBUG_INDEX 0x57da
+#define mmDP_FE_TEST_DEBUG_DATA 0x4adb
+#define mmDP0_DP_FE_TEST_DEBUG_DATA 0x4adb
+#define mmDP1_DP_FE_TEST_DEBUG_DATA 0x4bdb
+#define mmDP2_DP_FE_TEST_DEBUG_DATA 0x4cdb
+#define mmDP3_DP_FE_TEST_DEBUG_DATA 0x4ddb
+#define mmDP4_DP_FE_TEST_DEBUG_DATA 0x4edb
+#define mmDP5_DP_FE_TEST_DEBUG_DATA 0x4fdb
+#define mmDP6_DP_FE_TEST_DEBUG_DATA 0x54db
+#define mmDP7_DP_FE_TEST_DEBUG_DATA 0x56db
+#define mmDP8_DP_FE_TEST_DEBUG_DATA 0x57db
+#define mmAUX_CONTROL 0x5c00
+#define mmDP_AUX0_AUX_CONTROL 0x5c00
+#define mmDP_AUX1_AUX_CONTROL 0x5c1c
+#define mmDP_AUX2_AUX_CONTROL 0x5c38
+#define mmDP_AUX3_AUX_CONTROL 0x5c54
+#define mmDP_AUX4_AUX_CONTROL 0x5c70
+#define mmDP_AUX5_AUX_CONTROL 0x5c8c
+#define mmAUX_SW_CONTROL 0x5c01
+#define mmDP_AUX0_AUX_SW_CONTROL 0x5c01
+#define mmDP_AUX1_AUX_SW_CONTROL 0x5c1d
+#define mmDP_AUX2_AUX_SW_CONTROL 0x5c39
+#define mmDP_AUX3_AUX_SW_CONTROL 0x5c55
+#define mmDP_AUX4_AUX_SW_CONTROL 0x5c71
+#define mmDP_AUX5_AUX_SW_CONTROL 0x5c8d
+#define mmAUX_ARB_CONTROL 0x5c02
+#define mmDP_AUX0_AUX_ARB_CONTROL 0x5c02
+#define mmDP_AUX1_AUX_ARB_CONTROL 0x5c1e
+#define mmDP_AUX2_AUX_ARB_CONTROL 0x5c3a
+#define mmDP_AUX3_AUX_ARB_CONTROL 0x5c56
+#define mmDP_AUX4_AUX_ARB_CONTROL 0x5c72
+#define mmDP_AUX5_AUX_ARB_CONTROL 0x5c8e
+#define mmAUX_INTERRUPT_CONTROL 0x5c03
+#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x5c03
+#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x5c1f
+#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x5c3b
+#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x5c57
+#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x5c73
+#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x5c8f
+#define mmAUX_SW_STATUS 0x5c04
+#define mmDP_AUX0_AUX_SW_STATUS 0x5c04
+#define mmDP_AUX1_AUX_SW_STATUS 0x5c20
+#define mmDP_AUX2_AUX_SW_STATUS 0x5c3c
+#define mmDP_AUX3_AUX_SW_STATUS 0x5c58
+#define mmDP_AUX4_AUX_SW_STATUS 0x5c74
+#define mmDP_AUX5_AUX_SW_STATUS 0x5c90
+#define mmAUX_LS_STATUS 0x5c05
+#define mmDP_AUX0_AUX_LS_STATUS 0x5c05
+#define mmDP_AUX1_AUX_LS_STATUS 0x5c21
+#define mmDP_AUX2_AUX_LS_STATUS 0x5c3d
+#define mmDP_AUX3_AUX_LS_STATUS 0x5c59
+#define mmDP_AUX4_AUX_LS_STATUS 0x5c75
+#define mmDP_AUX5_AUX_LS_STATUS 0x5c91
+#define mmAUX_SW_DATA 0x5c06
+#define mmDP_AUX0_AUX_SW_DATA 0x5c06
+#define mmDP_AUX1_AUX_SW_DATA 0x5c22
+#define mmDP_AUX2_AUX_SW_DATA 0x5c3e
+#define mmDP_AUX3_AUX_SW_DATA 0x5c5a
+#define mmDP_AUX4_AUX_SW_DATA 0x5c76
+#define mmDP_AUX5_AUX_SW_DATA 0x5c92
+#define mmAUX_LS_DATA 0x5c07
+#define mmDP_AUX0_AUX_LS_DATA 0x5c07
+#define mmDP_AUX1_AUX_LS_DATA 0x5c23
+#define mmDP_AUX2_AUX_LS_DATA 0x5c3f
+#define mmDP_AUX3_AUX_LS_DATA 0x5c5b
+#define mmDP_AUX4_AUX_LS_DATA 0x5c77
+#define mmDP_AUX5_AUX_LS_DATA 0x5c93
+#define mmAUX_DPHY_TX_REF_CONTROL 0x5c08
+#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x5c08
+#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x5c24
+#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x5c40
+#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x5c5c
+#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x5c78
+#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x5c94
+#define mmAUX_DPHY_TX_CONTROL 0x5c09
+#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x5c09
+#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x5c25
+#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x5c41
+#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x5c5d
+#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x5c79
+#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x5c95
+#define mmAUX_DPHY_RX_CONTROL0 0x5c0a
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x5c0a
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x5c26
+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x5c42
+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x5c5e
+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x5c7a
+#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x5c96
+#define mmAUX_DPHY_RX_CONTROL1 0x5c0b
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x5c0b
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x5c27
+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x5c43
+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x5c5f
+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x5c7b
+#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x5c97
+#define mmAUX_DPHY_TX_STATUS 0x5c0c
+#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x5c0c
+#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x5c28
+#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x5c44
+#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x5c60
+#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x5c7c
+#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x5c98
+#define mmAUX_DPHY_RX_STATUS 0x5c0d
+#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x5c0d
+#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x5c29
+#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x5c45
+#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x5c61
+#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x5c7d
+#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x5c99
+#define mmAUX_GTC_SYNC_CONTROL 0x5c0e
+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x5c0e
+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x5c2a
+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x5c46
+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x5c62
+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x5c7e
+#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x5c9a
+#define mmAUX_GTC_SYNC_ERROR_CONTROL 0x5c0f
+#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x5c0f
+#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x5c2b
+#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x5c47
+#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x5c63
+#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x5c7f
+#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x5c9b
+#define mmAUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10
+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10
+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c2c
+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c48
+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c64
+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c80
+#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c9c
+#define mmAUX_GTC_SYNC_STATUS 0x5c11
+#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x5c11
+#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x5c2d
+#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x5c49
+#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x5c65
+#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x5c81
+#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x5c9d
+#define mmAUX_GTC_SYNC_DATA 0x5c12
+#define mmDP_AUX0_AUX_GTC_SYNC_DATA 0x5c12
+#define mmDP_AUX1_AUX_GTC_SYNC_DATA 0x5c2e
+#define mmDP_AUX2_AUX_GTC_SYNC_DATA 0x5c4a
+#define mmDP_AUX3_AUX_GTC_SYNC_DATA 0x5c66
+#define mmDP_AUX4_AUX_GTC_SYNC_DATA 0x5c82
+#define mmDP_AUX5_AUX_GTC_SYNC_DATA 0x5c9e
+#define mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13
+#define mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13
+#define mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c2f
+#define mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c4b
+#define mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c67
+#define mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c83
+#define mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c9f
+#define mmAUX_TEST_DEBUG_INDEX 0x5c14
+#define mmDP_AUX0_AUX_TEST_DEBUG_INDEX 0x5c14
+#define mmDP_AUX1_AUX_TEST_DEBUG_INDEX 0x5c30
+#define mmDP_AUX2_AUX_TEST_DEBUG_INDEX 0x5c4c
+#define mmDP_AUX3_AUX_TEST_DEBUG_INDEX 0x5c68
+#define mmDP_AUX4_AUX_TEST_DEBUG_INDEX 0x5c84
+#define mmDP_AUX5_AUX_TEST_DEBUG_INDEX 0x5ca0
+#define mmAUX_TEST_DEBUG_DATA 0x5c15
+#define mmDP_AUX0_AUX_TEST_DEBUG_DATA 0x5c15
+#define mmDP_AUX1_AUX_TEST_DEBUG_DATA 0x5c31
+#define mmDP_AUX2_AUX_TEST_DEBUG_DATA 0x5c4d
+#define mmDP_AUX3_AUX_TEST_DEBUG_DATA 0x5c69
+#define mmDP_AUX4_AUX_TEST_DEBUG_DATA 0x5c85
+#define mmDP_AUX5_AUX_TEST_DEBUG_DATA 0x5ca1
+#define ixDP_AUX_DEBUG_A 0x10
+#define ixDP_AUX_DEBUG_B 0x11
+#define ixDP_AUX_DEBUG_C 0x12
+#define ixDP_AUX_DEBUG_D 0x13
+#define ixDP_AUX_DEBUG_E 0x14
+#define ixDP_AUX_DEBUG_F 0x15
+#define ixDP_AUX_DEBUG_G 0x16
+#define ixDP_AUX_DEBUG_H 0x17
+#define ixDP_AUX_DEBUG_I 0x18
+#define ixDP_AUX_DEBUG_J 0x19
+#define ixDP_AUX_DEBUG_K 0x1a
+#define ixDP_AUX_DEBUG_L 0x1b
+#define ixDP_AUX_DEBUG_M 0x1c
+#define ixDP_AUX_DEBUG_N 0x1d
+#define ixDP_AUX_DEBUG_O 0x1e
+#define ixDP_AUX_DEBUG_P 0x1f
+#define ixDP_AUX_DEBUG_Q 0x20
+#define mmDVO_ENABLE 0x16a0
+#define mmDVO_SOURCE_SELECT 0x16a1
+#define mmDVO_OUTPUT 0x16a2
+#define mmDVO_CONTROL 0x16a3
+#define mmDVO_CRC_EN 0x16a4
+#define mmDVO_CRC2_SIG_MASK 0x16a5
+#define mmDVO_CRC2_SIG_RESULT 0x16a6
+#define mmDVO_FIFO_ERROR_STATUS 0x16a7
+#define mmDVO_TEST_DEBUG_INDEX 0x16a8
+#define mmDVO_TEST_DEBUG_DATA 0x16a9
+#define mmFBC_CNTL 0x280
+#define mmFBC_IDLE_MASK 0x281
+#define mmFBC_IDLE_FORCE_CLEAR_MASK 0x282
+#define mmFBC_START_STOP_DELAY 0x283
+#define mmFBC_COMP_CNTL 0x284
+#define mmFBC_COMP_MODE 0x285
+#define mmFBC_DEBUG0 0x286
+#define mmFBC_DEBUG1 0x287
+#define mmFBC_DEBUG2 0x288
+#define mmFBC_IND_LUT0 0x289
+#define mmFBC_IND_LUT1 0x28a
+#define mmFBC_IND_LUT2 0x28b
+#define mmFBC_IND_LUT3 0x28c
+#define mmFBC_IND_LUT4 0x28d
+#define mmFBC_IND_LUT5 0x28e
+#define mmFBC_IND_LUT6 0x28f
+#define mmFBC_IND_LUT7 0x290
+#define mmFBC_IND_LUT8 0x291
+#define mmFBC_IND_LUT9 0x292
+#define mmFBC_IND_LUT10 0x293
+#define mmFBC_IND_LUT11 0x294
+#define mmFBC_IND_LUT12 0x295
+#define mmFBC_IND_LUT13 0x296
+#define mmFBC_IND_LUT14 0x297
+#define mmFBC_IND_LUT15 0x298
+#define mmFBC_CSM_REGION_OFFSET_01 0x299
+#define mmFBC_CSM_REGION_OFFSET_23 0x29a
+#define mmFBC_CLIENT_REGION_MASK 0x29b
+#define mmFBC_DEBUG_COMP 0x29c
+#define mmFBC_DEBUG_CSR 0x29d
+#define mmFBC_DEBUG_CSR_RDATA 0x29e
+#define mmFBC_DEBUG_CSR_WDATA 0x29f
+#define mmFBC_DEBUG_CSR_RDATA_HI 0x2a0
+#define mmFBC_DEBUG_CSR_WDATA_HI 0x2a1
+#define mmFBC_MISC 0x2a2
+#define mmFBC_STATUS 0x2a3
+#define mmFBC_TEST_DEBUG_INDEX 0x2a4
+#define mmFBC_TEST_DEBUG_DATA 0x2a5
+#define mmFMT_CLAMP_COMPONENT_R 0x1be8
+#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x1be8
+#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1de8
+#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x1fe8
+#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x41e8
+#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x43e8
+#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x45e8
+#define mmFMT_CLAMP_COMPONENT_G 0x1be9
+#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x1be9
+#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1de9
+#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x1fe9
+#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x41e9
+#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x43e9
+#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x45e9
+#define mmFMT_CLAMP_COMPONENT_B 0x1bea
+#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x1bea
+#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1dea
+#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x1fea
+#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x41ea
+#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x43ea
+#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x45ea
+#define mmFMT_DYNAMIC_EXP_CNTL 0x1bed
+#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1bed
+#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1ded
+#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x1fed
+#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x41ed
+#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x43ed
+#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x45ed
+#define mmFMT_CONTROL 0x1bee
+#define mmFMT0_FMT_CONTROL 0x1bee
+#define mmFMT1_FMT_CONTROL 0x1dee
+#define mmFMT2_FMT_CONTROL 0x1fee
+#define mmFMT3_FMT_CONTROL 0x41ee
+#define mmFMT4_FMT_CONTROL 0x43ee
+#define mmFMT5_FMT_CONTROL 0x45ee
+#define mmFMT_BIT_DEPTH_CONTROL 0x1bf2
+#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1bf2
+#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1df2
+#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x1ff2
+#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x41f2
+#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x43f2
+#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x45f2
+#define mmFMT_DITHER_RAND_R_SEED 0x1bf3
+#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1bf3
+#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x1df3
+#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x1ff3
+#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x41f3
+#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x43f3
+#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x45f3
+#define mmFMT_DITHER_RAND_G_SEED 0x1bf4
+#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1bf4
+#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x1df4
+#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x1ff4
+#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x41f4
+#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x43f4
+#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x45f4
+#define mmFMT_DITHER_RAND_B_SEED 0x1bf5
+#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1bf5
+#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x1df5
+#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x1ff5
+#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x41f5
+#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x43f5
+#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x45f5
+#define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6
+#define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6
+#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1df6
+#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1ff6
+#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41f6
+#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x43f6
+#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x45f6
+#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7
+#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7
+#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1df7
+#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1ff7
+#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41f7
+#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x43f7
+#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x45f7
+#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8
+#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8
+#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1df8
+#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1ff8
+#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41f8
+#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x43f8
+#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x45f8
+#define mmFMT_CLAMP_CNTL 0x1bf9
+#define mmFMT0_FMT_CLAMP_CNTL 0x1bf9
+#define mmFMT1_FMT_CLAMP_CNTL 0x1df9
+#define mmFMT2_FMT_CLAMP_CNTL 0x1ff9
+#define mmFMT3_FMT_CLAMP_CNTL 0x41f9
+#define mmFMT4_FMT_CLAMP_CNTL 0x43f9
+#define mmFMT5_FMT_CLAMP_CNTL 0x45f9
+#define mmFMT_CRC_CNTL 0x1bfa
+#define mmFMT0_FMT_CRC_CNTL 0x1bfa
+#define mmFMT1_FMT_CRC_CNTL 0x1dfa
+#define mmFMT2_FMT_CRC_CNTL 0x1ffa
+#define mmFMT3_FMT_CRC_CNTL 0x41fa
+#define mmFMT4_FMT_CRC_CNTL 0x43fa
+#define mmFMT5_FMT_CRC_CNTL 0x45fa
+#define mmFMT_CRC_SIG_RED_GREEN_MASK 0x1bfb
+#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1bfb
+#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1dfb
+#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x1ffb
+#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x41fb
+#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x43fb
+#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x45fb
+#define mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc
+#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc
+#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1dfc
+#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1ffc
+#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41fc
+#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x43fc
+#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x45fc
+#define mmFMT_CRC_SIG_RED_GREEN 0x1bfd
+#define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1bfd
+#define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1dfd
+#define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x1ffd
+#define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x41fd
+#define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x43fd
+#define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x45fd
+#define mmFMT_CRC_SIG_BLUE_CONTROL 0x1bfe
+#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1bfe
+#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1dfe
+#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x1ffe
+#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x41fe
+#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x43fe
+#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x45fe
+#define mmFMT_DEBUG_CNTL 0x1bff
+#define mmFMT0_FMT_DEBUG_CNTL 0x1bff
+#define mmFMT1_FMT_DEBUG_CNTL 0x1dff
+#define mmFMT2_FMT_DEBUG_CNTL 0x1fff
+#define mmFMT3_FMT_DEBUG_CNTL 0x41ff
+#define mmFMT4_FMT_DEBUG_CNTL 0x43ff
+#define mmFMT5_FMT_DEBUG_CNTL 0x45ff
+#define mmFMT_TEST_DEBUG_INDEX 0x1beb
+#define mmFMT0_FMT_TEST_DEBUG_INDEX 0x1beb
+#define mmFMT1_FMT_TEST_DEBUG_INDEX 0x1deb
+#define mmFMT2_FMT_TEST_DEBUG_INDEX 0x1feb
+#define mmFMT3_FMT_TEST_DEBUG_INDEX 0x41eb
+#define mmFMT4_FMT_TEST_DEBUG_INDEX 0x43eb
+#define mmFMT5_FMT_TEST_DEBUG_INDEX 0x45eb
+#define mmFMT_TEST_DEBUG_DATA 0x1bec
+#define mmFMT0_FMT_TEST_DEBUG_DATA 0x1bec
+#define mmFMT1_FMT_TEST_DEBUG_DATA 0x1dec
+#define mmFMT2_FMT_TEST_DEBUG_DATA 0x1fec
+#define mmFMT3_FMT_TEST_DEBUG_DATA 0x41ec
+#define mmFMT4_FMT_TEST_DEBUG_DATA 0x43ec
+#define mmFMT5_FMT_TEST_DEBUG_DATA 0x45ec
+#define ixFMT_DEBUG0 0x1
+#define ixFMT_DEBUG1 0x2
+#define ixFMT_DEBUG2 0x3
+#define ixFMT_DEBUG_ID 0x0
+#define mmLB_DATA_FORMAT 0x1ac0
+#define mmLB0_LB_DATA_FORMAT 0x1ac0
+#define mmLB1_LB_DATA_FORMAT 0x1cc0
+#define mmLB2_LB_DATA_FORMAT 0x1ec0
+#define mmLB3_LB_DATA_FORMAT 0x40c0
+#define mmLB4_LB_DATA_FORMAT 0x42c0
+#define mmLB5_LB_DATA_FORMAT 0x44c0
+#define mmLB_MEMORY_CTRL 0x1ac1
+#define mmLB0_LB_MEMORY_CTRL 0x1ac1
+#define mmLB1_LB_MEMORY_CTRL 0x1cc1
+#define mmLB2_LB_MEMORY_CTRL 0x1ec1
+#define mmLB3_LB_MEMORY_CTRL 0x40c1
+#define mmLB4_LB_MEMORY_CTRL 0x42c1
+#define mmLB5_LB_MEMORY_CTRL 0x44c1
+#define mmLB_MEMORY_SIZE_STATUS 0x1ac2
+#define mmLB0_LB_MEMORY_SIZE_STATUS 0x1ac2
+#define mmLB1_LB_MEMORY_SIZE_STATUS 0x1cc2
+#define mmLB2_LB_MEMORY_SIZE_STATUS 0x1ec2
+#define mmLB3_LB_MEMORY_SIZE_STATUS 0x40c2
+#define mmLB4_LB_MEMORY_SIZE_STATUS 0x42c2
+#define mmLB5_LB_MEMORY_SIZE_STATUS 0x44c2
+#define mmLB_DESKTOP_HEIGHT 0x1ac3
+#define mmLB0_LB_DESKTOP_HEIGHT 0x1ac3
+#define mmLB1_LB_DESKTOP_HEIGHT 0x1cc3
+#define mmLB2_LB_DESKTOP_HEIGHT 0x1ec3
+#define mmLB3_LB_DESKTOP_HEIGHT 0x40c3
+#define mmLB4_LB_DESKTOP_HEIGHT 0x42c3
+#define mmLB5_LB_DESKTOP_HEIGHT 0x44c3
+#define mmLB_VLINE_START_END 0x1ac4
+#define mmLB0_LB_VLINE_START_END 0x1ac4
+#define mmLB1_LB_VLINE_START_END 0x1cc4
+#define mmLB2_LB_VLINE_START_END 0x1ec4
+#define mmLB3_LB_VLINE_START_END 0x40c4
+#define mmLB4_LB_VLINE_START_END 0x42c4
+#define mmLB5_LB_VLINE_START_END 0x44c4
+#define mmLB_VLINE2_START_END 0x1ac5
+#define mmLB0_LB_VLINE2_START_END 0x1ac5
+#define mmLB1_LB_VLINE2_START_END 0x1cc5
+#define mmLB2_LB_VLINE2_START_END 0x1ec5
+#define mmLB3_LB_VLINE2_START_END 0x40c5
+#define mmLB4_LB_VLINE2_START_END 0x42c5
+#define mmLB5_LB_VLINE2_START_END 0x44c5
+#define mmLB_V_COUNTER 0x1ac6
+#define mmLB0_LB_V_COUNTER 0x1ac6
+#define mmLB1_LB_V_COUNTER 0x1cc6
+#define mmLB2_LB_V_COUNTER 0x1ec6
+#define mmLB3_LB_V_COUNTER 0x40c6
+#define mmLB4_LB_V_COUNTER 0x42c6
+#define mmLB5_LB_V_COUNTER 0x44c6
+#define mmLB_SNAPSHOT_V_COUNTER 0x1ac7
+#define mmLB0_LB_SNAPSHOT_V_COUNTER 0x1ac7
+#define mmLB1_LB_SNAPSHOT_V_COUNTER 0x1cc7
+#define mmLB2_LB_SNAPSHOT_V_COUNTER 0x1ec7
+#define mmLB3_LB_SNAPSHOT_V_COUNTER 0x40c7
+#define mmLB4_LB_SNAPSHOT_V_COUNTER 0x42c7
+#define mmLB5_LB_SNAPSHOT_V_COUNTER 0x44c7
+#define mmLB_INTERRUPT_MASK 0x1ac8
+#define mmLB0_LB_INTERRUPT_MASK 0x1ac8
+#define mmLB1_LB_INTERRUPT_MASK 0x1cc8
+#define mmLB2_LB_INTERRUPT_MASK 0x1ec8
+#define mmLB3_LB_INTERRUPT_MASK 0x40c8
+#define mmLB4_LB_INTERRUPT_MASK 0x42c8
+#define mmLB5_LB_INTERRUPT_MASK 0x44c8
+#define mmLB_VLINE_STATUS 0x1ac9
+#define mmLB0_LB_VLINE_STATUS 0x1ac9
+#define mmLB1_LB_VLINE_STATUS 0x1cc9
+#define mmLB2_LB_VLINE_STATUS 0x1ec9
+#define mmLB3_LB_VLINE_STATUS 0x40c9
+#define mmLB4_LB_VLINE_STATUS 0x42c9
+#define mmLB5_LB_VLINE_STATUS 0x44c9
+#define mmLB_VLINE2_STATUS 0x1aca
+#define mmLB0_LB_VLINE2_STATUS 0x1aca
+#define mmLB1_LB_VLINE2_STATUS 0x1cca
+#define mmLB2_LB_VLINE2_STATUS 0x1eca
+#define mmLB3_LB_VLINE2_STATUS 0x40ca
+#define mmLB4_LB_VLINE2_STATUS 0x42ca
+#define mmLB5_LB_VLINE2_STATUS 0x44ca
+#define mmLB_VBLANK_STATUS 0x1acb
+#define mmLB0_LB_VBLANK_STATUS 0x1acb
+#define mmLB1_LB_VBLANK_STATUS 0x1ccb
+#define mmLB2_LB_VBLANK_STATUS 0x1ecb
+#define mmLB3_LB_VBLANK_STATUS 0x40cb
+#define mmLB4_LB_VBLANK_STATUS 0x42cb
+#define mmLB5_LB_VBLANK_STATUS 0x44cb
+#define mmLB_SYNC_RESET_SEL 0x1acc
+#define mmLB0_LB_SYNC_RESET_SEL 0x1acc
+#define mmLB1_LB_SYNC_RESET_SEL 0x1ccc
+#define mmLB2_LB_SYNC_RESET_SEL 0x1ecc
+#define mmLB3_LB_SYNC_RESET_SEL 0x40cc
+#define mmLB4_LB_SYNC_RESET_SEL 0x42cc
+#define mmLB5_LB_SYNC_RESET_SEL 0x44cc
+#define mmLB_BLACK_KEYER_R_CR 0x1acd
+#define mmLB0_LB_BLACK_KEYER_R_CR 0x1acd
+#define mmLB1_LB_BLACK_KEYER_R_CR 0x1ccd
+#define mmLB2_LB_BLACK_KEYER_R_CR 0x1ecd
+#define mmLB3_LB_BLACK_KEYER_R_CR 0x40cd
+#define mmLB4_LB_BLACK_KEYER_R_CR 0x42cd
+#define mmLB5_LB_BLACK_KEYER_R_CR 0x44cd
+#define mmLB_BLACK_KEYER_G_Y 0x1ace
+#define mmLB0_LB_BLACK_KEYER_G_Y 0x1ace
+#define mmLB1_LB_BLACK_KEYER_G_Y 0x1cce
+#define mmLB2_LB_BLACK_KEYER_G_Y 0x1ece
+#define mmLB3_LB_BLACK_KEYER_G_Y 0x40ce
+#define mmLB4_LB_BLACK_KEYER_G_Y 0x42ce
+#define mmLB5_LB_BLACK_KEYER_G_Y 0x44ce
+#define mmLB_BLACK_KEYER_B_CB 0x1acf
+#define mmLB0_LB_BLACK_KEYER_B_CB 0x1acf
+#define mmLB1_LB_BLACK_KEYER_B_CB 0x1ccf
+#define mmLB2_LB_BLACK_KEYER_B_CB 0x1ecf
+#define mmLB3_LB_BLACK_KEYER_B_CB 0x40cf
+#define mmLB4_LB_BLACK_KEYER_B_CB 0x42cf
+#define mmLB5_LB_BLACK_KEYER_B_CB 0x44cf
+#define mmLB_KEYER_COLOR_CTRL 0x1ad0
+#define mmLB0_LB_KEYER_COLOR_CTRL 0x1ad0
+#define mmLB1_LB_KEYER_COLOR_CTRL 0x1cd0
+#define mmLB2_LB_KEYER_COLOR_CTRL 0x1ed0
+#define mmLB3_LB_KEYER_COLOR_CTRL 0x40d0
+#define mmLB4_LB_KEYER_COLOR_CTRL 0x42d0
+#define mmLB5_LB_KEYER_COLOR_CTRL 0x44d0
+#define mmLB_KEYER_COLOR_R_CR 0x1ad1
+#define mmLB0_LB_KEYER_COLOR_R_CR 0x1ad1
+#define mmLB1_LB_KEYER_COLOR_R_CR 0x1cd1
+#define mmLB2_LB_KEYER_COLOR_R_CR 0x1ed1
+#define mmLB3_LB_KEYER_COLOR_R_CR 0x40d1
+#define mmLB4_LB_KEYER_COLOR_R_CR 0x42d1
+#define mmLB5_LB_KEYER_COLOR_R_CR 0x44d1
+#define mmLB_KEYER_COLOR_G_Y 0x1ad2
+#define mmLB0_LB_KEYER_COLOR_G_Y 0x1ad2
+#define mmLB1_LB_KEYER_COLOR_G_Y 0x1cd2
+#define mmLB2_LB_KEYER_COLOR_G_Y 0x1ed2
+#define mmLB3_LB_KEYER_COLOR_G_Y 0x40d2
+#define mmLB4_LB_KEYER_COLOR_G_Y 0x42d2
+#define mmLB5_LB_KEYER_COLOR_G_Y 0x44d2
+#define mmLB_KEYER_COLOR_B_CB 0x1ad3
+#define mmLB0_LB_KEYER_COLOR_B_CB 0x1ad3
+#define mmLB1_LB_KEYER_COLOR_B_CB 0x1cd3
+#define mmLB2_LB_KEYER_COLOR_B_CB 0x1ed3
+#define mmLB3_LB_KEYER_COLOR_B_CB 0x40d3
+#define mmLB4_LB_KEYER_COLOR_B_CB 0x42d3
+#define mmLB5_LB_KEYER_COLOR_B_CB 0x44d3
+#define mmLB_KEYER_COLOR_REP_R_CR 0x1ad4
+#define mmLB0_LB_KEYER_COLOR_REP_R_CR 0x1ad4
+#define mmLB1_LB_KEYER_COLOR_REP_R_CR 0x1cd4
+#define mmLB2_LB_KEYER_COLOR_REP_R_CR 0x1ed4
+#define mmLB3_LB_KEYER_COLOR_REP_R_CR 0x40d4
+#define mmLB4_LB_KEYER_COLOR_REP_R_CR 0x42d4
+#define mmLB5_LB_KEYER_COLOR_REP_R_CR 0x44d4
+#define mmLB_KEYER_COLOR_REP_G_Y 0x1ad5
+#define mmLB0_LB_KEYER_COLOR_REP_G_Y 0x1ad5
+#define mmLB1_LB_KEYER_COLOR_REP_G_Y 0x1cd5
+#define mmLB2_LB_KEYER_COLOR_REP_G_Y 0x1ed5
+#define mmLB3_LB_KEYER_COLOR_REP_G_Y 0x40d5
+#define mmLB4_LB_KEYER_COLOR_REP_G_Y 0x42d5
+#define mmLB5_LB_KEYER_COLOR_REP_G_Y 0x44d5
+#define mmLB_KEYER_COLOR_REP_B_CB 0x1ad6
+#define mmLB0_LB_KEYER_COLOR_REP_B_CB 0x1ad6
+#define mmLB1_LB_KEYER_COLOR_REP_B_CB 0x1cd6
+#define mmLB2_LB_KEYER_COLOR_REP_B_CB 0x1ed6
+#define mmLB3_LB_KEYER_COLOR_REP_B_CB 0x40d6
+#define mmLB4_LB_KEYER_COLOR_REP_B_CB 0x42d6
+#define mmLB5_LB_KEYER_COLOR_REP_B_CB 0x44d6
+#define mmLB_BUFFER_LEVEL_STATUS 0x1ad7
+#define mmLB0_LB_BUFFER_LEVEL_STATUS 0x1ad7
+#define mmLB1_LB_BUFFER_LEVEL_STATUS 0x1cd7
+#define mmLB2_LB_BUFFER_LEVEL_STATUS 0x1ed7
+#define mmLB3_LB_BUFFER_LEVEL_STATUS 0x40d7
+#define mmLB4_LB_BUFFER_LEVEL_STATUS 0x42d7
+#define mmLB5_LB_BUFFER_LEVEL_STATUS 0x44d7
+#define mmLB_BUFFER_URGENCY_CTRL 0x1ad8
+#define mmLB0_LB_BUFFER_URGENCY_CTRL 0x1ad8
+#define mmLB1_LB_BUFFER_URGENCY_CTRL 0x1cd8
+#define mmLB2_LB_BUFFER_URGENCY_CTRL 0x1ed8
+#define mmLB3_LB_BUFFER_URGENCY_CTRL 0x40d8
+#define mmLB4_LB_BUFFER_URGENCY_CTRL 0x42d8
+#define mmLB5_LB_BUFFER_URGENCY_CTRL 0x44d8
+#define mmLB_BUFFER_URGENCY_STATUS 0x1ad9
+#define mmLB0_LB_BUFFER_URGENCY_STATUS 0x1ad9
+#define mmLB1_LB_BUFFER_URGENCY_STATUS 0x1cd9
+#define mmLB2_LB_BUFFER_URGENCY_STATUS 0x1ed9
+#define mmLB3_LB_BUFFER_URGENCY_STATUS 0x40d9
+#define mmLB4_LB_BUFFER_URGENCY_STATUS 0x42d9
+#define mmLB5_LB_BUFFER_URGENCY_STATUS 0x44d9
+#define mmLB_BUFFER_STATUS 0x1ada
+#define mmLB0_LB_BUFFER_STATUS 0x1ada
+#define mmLB1_LB_BUFFER_STATUS 0x1cda
+#define mmLB2_LB_BUFFER_STATUS 0x1eda
+#define mmLB3_LB_BUFFER_STATUS 0x40da
+#define mmLB4_LB_BUFFER_STATUS 0x42da
+#define mmLB5_LB_BUFFER_STATUS 0x44da
+#define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1adc
+#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1adc
+#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1cdc
+#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x1edc
+#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x40dc
+#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x42dc
+#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x44dc
+#define mmMVP_AFR_FLIP_MODE 0x1ae0
+#define mmLB0_MVP_AFR_FLIP_MODE 0x1ae0
+#define mmLB1_MVP_AFR_FLIP_MODE 0x1ce0
+#define mmLB2_MVP_AFR_FLIP_MODE 0x1ee0
+#define mmLB3_MVP_AFR_FLIP_MODE 0x40e0
+#define mmLB4_MVP_AFR_FLIP_MODE 0x42e0
+#define mmLB5_MVP_AFR_FLIP_MODE 0x44e0
+#define mmMVP_AFR_FLIP_FIFO_CNTL 0x1ae1
+#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1ae1
+#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1ce1
+#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x1ee1
+#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x40e1
+#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x42e1
+#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x44e1
+#define mmMVP_FLIP_LINE_NUM_INSERT 0x1ae2
+#define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ae2
+#define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1ce2
+#define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x1ee2
+#define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x40e2
+#define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x42e2
+#define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x44e2
+#define mmDC_MVP_LB_CONTROL 0x1ae3
+#define mmLB0_DC_MVP_LB_CONTROL 0x1ae3
+#define mmLB1_DC_MVP_LB_CONTROL 0x1ce3
+#define mmLB2_DC_MVP_LB_CONTROL 0x1ee3
+#define mmLB3_DC_MVP_LB_CONTROL 0x40e3
+#define mmLB4_DC_MVP_LB_CONTROL 0x42e3
+#define mmLB5_DC_MVP_LB_CONTROL 0x44e3
+#define mmLB_DEBUG 0x1ae4
+#define mmLB0_LB_DEBUG 0x1ae4
+#define mmLB1_LB_DEBUG 0x1ce4
+#define mmLB2_LB_DEBUG 0x1ee4
+#define mmLB3_LB_DEBUG 0x40e4
+#define mmLB4_LB_DEBUG 0x42e4
+#define mmLB5_LB_DEBUG 0x44e4
+#define mmLB_DEBUG2 0x1ae5
+#define mmLB0_LB_DEBUG2 0x1ae5
+#define mmLB1_LB_DEBUG2 0x1ce5
+#define mmLB2_LB_DEBUG2 0x1ee5
+#define mmLB3_LB_DEBUG2 0x40e5
+#define mmLB4_LB_DEBUG2 0x42e5
+#define mmLB5_LB_DEBUG2 0x44e5
+#define mmLB_DEBUG3 0x1ae6
+#define mmLB0_LB_DEBUG3 0x1ae6
+#define mmLB1_LB_DEBUG3 0x1ce6
+#define mmLB2_LB_DEBUG3 0x1ee6
+#define mmLB3_LB_DEBUG3 0x40e6
+#define mmLB4_LB_DEBUG3 0x42e6
+#define mmLB5_LB_DEBUG3 0x44e6
+#define mmLB_TEST_DEBUG_INDEX 0x1afe
+#define mmLB0_LB_TEST_DEBUG_INDEX 0x1afe
+#define mmLB1_LB_TEST_DEBUG_INDEX 0x1cfe
+#define mmLB2_LB_TEST_DEBUG_INDEX 0x1efe
+#define mmLB3_LB_TEST_DEBUG_INDEX 0x40fe
+#define mmLB4_LB_TEST_DEBUG_INDEX 0x42fe
+#define mmLB5_LB_TEST_DEBUG_INDEX 0x44fe
+#define mmLB_TEST_DEBUG_DATA 0x1aff
+#define mmLB0_LB_TEST_DEBUG_DATA 0x1aff
+#define mmLB1_LB_TEST_DEBUG_DATA 0x1cff
+#define mmLB2_LB_TEST_DEBUG_DATA 0x1eff
+#define mmLB3_LB_TEST_DEBUG_DATA 0x40ff
+#define mmLB4_LB_TEST_DEBUG_DATA 0x42ff
+#define mmLB5_LB_TEST_DEBUG_DATA 0x44ff
+#define mmLBV_DATA_FORMAT 0x463c
+#define mmLBV_MEMORY_CTRL 0x463d
+#define mmLBV_MEMORY_SIZE_STATUS 0x463e
+#define mmLBV_DESKTOP_HEIGHT 0x463f
+#define mmLBV_VLINE_START_END 0x4640
+#define mmLBV_VLINE2_START_END 0x4641
+#define mmLBV_V_COUNTER 0x4642
+#define mmLBV_SNAPSHOT_V_COUNTER 0x4643
+#define mmLBV_V_COUNTER_CHROMA 0x4644
+#define mmLBV_SNAPSHOT_V_COUNTER_CHROMA 0x4645
+#define mmLBV_INTERRUPT_MASK 0x4646
+#define mmLBV_VLINE_STATUS 0x4647
+#define mmLBV_VLINE2_STATUS 0x4648
+#define mmLBV_VBLANK_STATUS 0x4649
+#define mmLBV_SYNC_RESET_SEL 0x464a
+#define mmLBV_BLACK_KEYER_R_CR 0x464b
+#define mmLBV_BLACK_KEYER_G_Y 0x464c
+#define mmLBV_BLACK_KEYER_B_CB 0x464d
+#define mmLBV_KEYER_COLOR_CTRL 0x464e
+#define mmLBV_KEYER_COLOR_R_CR 0x464f
+#define mmLBV_KEYER_COLOR_G_Y 0x4650
+#define mmLBV_KEYER_COLOR_B_CB 0x4651
+#define mmLBV_KEYER_COLOR_REP_R_CR 0x4652
+#define mmLBV_KEYER_COLOR_REP_G_Y 0x4653
+#define mmLBV_KEYER_COLOR_REP_B_CB 0x4654
+#define mmLBV_BUFFER_LEVEL_STATUS 0x4655
+#define mmLBV_BUFFER_URGENCY_CTRL 0x4656
+#define mmLBV_BUFFER_URGENCY_STATUS 0x4657
+#define mmLBV_BUFFER_STATUS 0x4658
+#define mmLBV_NO_OUTSTANDING_REQ_STATUS 0x4659
+#define mmLBV_DEBUG 0x465a
+#define mmLBV_DEBUG2 0x465b
+#define mmLBV_DEBUG3 0x465c
+#define mmLBV_TEST_DEBUG_INDEX 0x4666
+#define mmLBV_TEST_DEBUG_DATA 0x4667
+#define mmMVP_CONTROL1 0x2ac
+#define mmMVP_CONTROL2 0x2ad
+#define mmMVP_FIFO_CONTROL 0x2ae
+#define mmMVP_FIFO_STATUS 0x2af
+#define mmMVP_SLAVE_STATUS 0x2b0
+#define mmMVP_INBAND_CNTL_CAP 0x2b1
+#define mmMVP_BLACK_KEYER 0x2b2
+#define mmMVP_CRC_CNTL 0x2b3
+#define mmMVP_CRC_RESULT_BLUE_GREEN 0x2b4
+#define mmMVP_CRC_RESULT_RED 0x2b5
+#define mmMVP_CONTROL3 0x2b6
+#define mmMVP_RECEIVE_CNT_CNTL1 0x2b7
+#define mmMVP_RECEIVE_CNT_CNTL2 0x2b8
+#define mmMVP_DEBUG 0x2bb
+#define mmMVP_TEST_DEBUG_INDEX 0x2b9
+#define mmMVP_TEST_DEBUG_DATA 0x2ba
+#define ixMVP_DEBUG_12 0xc
+#define ixMVP_DEBUG_13 0xd
+#define ixMVP_DEBUG_14 0xe
+#define ixMVP_DEBUG_15 0xf
+#define ixMVP_DEBUG_16 0x10
+#define ixMVP_DEBUG_17 0x11
+#define mmSCL_COEF_RAM_SELECT 0x1b40
+#define mmSCL0_SCL_COEF_RAM_SELECT 0x1b40
+#define mmSCL1_SCL_COEF_RAM_SELECT 0x1d40
+#define mmSCL2_SCL_COEF_RAM_SELECT 0x1f40
+#define mmSCL3_SCL_COEF_RAM_SELECT 0x4140
+#define mmSCL4_SCL_COEF_RAM_SELECT 0x4340
+#define mmSCL5_SCL_COEF_RAM_SELECT 0x4540
+#define mmSCL_COEF_RAM_TAP_DATA 0x1b41
+#define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1b41
+#define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1d41
+#define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x1f41
+#define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4141
+#define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4341
+#define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4541
+#define mmSCL_MODE 0x1b42
+#define mmSCL0_SCL_MODE 0x1b42
+#define mmSCL1_SCL_MODE 0x1d42
+#define mmSCL2_SCL_MODE 0x1f42
+#define mmSCL3_SCL_MODE 0x4142
+#define mmSCL4_SCL_MODE 0x4342
+#define mmSCL5_SCL_MODE 0x4542
+#define mmSCL_TAP_CONTROL 0x1b43
+#define mmSCL0_SCL_TAP_CONTROL 0x1b43
+#define mmSCL1_SCL_TAP_CONTROL 0x1d43
+#define mmSCL2_SCL_TAP_CONTROL 0x1f43
+#define mmSCL3_SCL_TAP_CONTROL 0x4143
+#define mmSCL4_SCL_TAP_CONTROL 0x4343
+#define mmSCL5_SCL_TAP_CONTROL 0x4543
+#define mmSCL_CONTROL 0x1b44
+#define mmSCL0_SCL_CONTROL 0x1b44
+#define mmSCL1_SCL_CONTROL 0x1d44
+#define mmSCL2_SCL_CONTROL 0x1f44
+#define mmSCL3_SCL_CONTROL 0x4144
+#define mmSCL4_SCL_CONTROL 0x4344
+#define mmSCL5_SCL_CONTROL 0x4544
+#define mmSCL_BYPASS_CONTROL 0x1b45
+#define mmSCL0_SCL_BYPASS_CONTROL 0x1b45
+#define mmSCL1_SCL_BYPASS_CONTROL 0x1d45
+#define mmSCL2_SCL_BYPASS_CONTROL 0x1f45
+#define mmSCL3_SCL_BYPASS_CONTROL 0x4145
+#define mmSCL4_SCL_BYPASS_CONTROL 0x4345
+#define mmSCL5_SCL_BYPASS_CONTROL 0x4545
+#define mmSCL_MANUAL_REPLICATE_CONTROL 0x1b46
+#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1b46
+#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1d46
+#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x1f46
+#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4146
+#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4346
+#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4546
+#define mmSCL_AUTOMATIC_MODE_CONTROL 0x1b47
+#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1b47
+#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1d47
+#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x1f47
+#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4147
+#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4347
+#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4547
+#define mmSCL_HORZ_FILTER_CONTROL 0x1b48
+#define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1b48
+#define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1d48
+#define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x1f48
+#define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x4148
+#define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x4348
+#define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4548
+#define mmSCL_HORZ_FILTER_SCALE_RATIO 0x1b49
+#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1b49
+#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1d49
+#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x1f49
+#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x4149
+#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x4349
+#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4549
+#define mmSCL_HORZ_FILTER_INIT 0x1b4a
+#define mmSCL0_SCL_HORZ_FILTER_INIT 0x1b4a
+#define mmSCL1_SCL_HORZ_FILTER_INIT 0x1d4a
+#define mmSCL2_SCL_HORZ_FILTER_INIT 0x1f4a
+#define mmSCL3_SCL_HORZ_FILTER_INIT 0x414a
+#define mmSCL4_SCL_HORZ_FILTER_INIT 0x434a
+#define mmSCL5_SCL_HORZ_FILTER_INIT 0x454a
+#define mmSCL_VERT_FILTER_CONTROL 0x1b4b
+#define mmSCL0_SCL_VERT_FILTER_CONTROL 0x1b4b
+#define mmSCL1_SCL_VERT_FILTER_CONTROL 0x1d4b
+#define mmSCL2_SCL_VERT_FILTER_CONTROL 0x1f4b
+#define mmSCL3_SCL_VERT_FILTER_CONTROL 0x414b
+#define mmSCL4_SCL_VERT_FILTER_CONTROL 0x434b
+#define mmSCL5_SCL_VERT_FILTER_CONTROL 0x454b
+#define mmSCL_VERT_FILTER_SCALE_RATIO 0x1b4c
+#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1b4c
+#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1d4c
+#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x1f4c
+#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x414c
+#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x434c
+#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x454c
+#define mmSCL_VERT_FILTER_INIT 0x1b4d
+#define mmSCL0_SCL_VERT_FILTER_INIT 0x1b4d
+#define mmSCL1_SCL_VERT_FILTER_INIT 0x1d4d
+#define mmSCL2_SCL_VERT_FILTER_INIT 0x1f4d
+#define mmSCL3_SCL_VERT_FILTER_INIT 0x414d
+#define mmSCL4_SCL_VERT_FILTER_INIT 0x434d
+#define mmSCL5_SCL_VERT_FILTER_INIT 0x454d
+#define mmSCL_VERT_FILTER_INIT_BOT 0x1b4e
+#define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1b4e
+#define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1d4e
+#define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x1f4e
+#define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x414e
+#define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x434e
+#define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x454e
+#define mmSCL_ROUND_OFFSET 0x1b4f
+#define mmSCL0_SCL_ROUND_OFFSET 0x1b4f
+#define mmSCL1_SCL_ROUND_OFFSET 0x1d4f
+#define mmSCL2_SCL_ROUND_OFFSET 0x1f4f
+#define mmSCL3_SCL_ROUND_OFFSET 0x414f
+#define mmSCL4_SCL_ROUND_OFFSET 0x434f
+#define mmSCL5_SCL_ROUND_OFFSET 0x454f
+#define mmSCL_UPDATE 0x1b51
+#define mmSCL0_SCL_UPDATE 0x1b51
+#define mmSCL1_SCL_UPDATE 0x1d51
+#define mmSCL2_SCL_UPDATE 0x1f51
+#define mmSCL3_SCL_UPDATE 0x4151
+#define mmSCL4_SCL_UPDATE 0x4351
+#define mmSCL5_SCL_UPDATE 0x4551
+#define mmSCL_F_SHARP_CONTROL 0x1b53
+#define mmSCL0_SCL_F_SHARP_CONTROL 0x1b53
+#define mmSCL1_SCL_F_SHARP_CONTROL 0x1d53
+#define mmSCL2_SCL_F_SHARP_CONTROL 0x1f53
+#define mmSCL3_SCL_F_SHARP_CONTROL 0x4153
+#define mmSCL4_SCL_F_SHARP_CONTROL 0x4353
+#define mmSCL5_SCL_F_SHARP_CONTROL 0x4553
+#define mmSCL_ALU_CONTROL 0x1b54
+#define mmSCL0_SCL_ALU_CONTROL 0x1b54
+#define mmSCL1_SCL_ALU_CONTROL 0x1d54
+#define mmSCL2_SCL_ALU_CONTROL 0x1f54
+#define mmSCL3_SCL_ALU_CONTROL 0x4154
+#define mmSCL4_SCL_ALU_CONTROL 0x4354
+#define mmSCL5_SCL_ALU_CONTROL 0x4554
+#define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1b55
+#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1b55
+#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1d55
+#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x1f55
+#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4155
+#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4355
+#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4555
+#define mmVIEWPORT_START_SECONDARY 0x1b5b
+#define mmSCL0_VIEWPORT_START_SECONDARY 0x1b5b
+#define mmSCL1_VIEWPORT_START_SECONDARY 0x1d5b
+#define mmSCL2_VIEWPORT_START_SECONDARY 0x1f5b
+#define mmSCL3_VIEWPORT_START_SECONDARY 0x415b
+#define mmSCL4_VIEWPORT_START_SECONDARY 0x435b
+#define mmSCL5_VIEWPORT_START_SECONDARY 0x455b
+#define mmVIEWPORT_START 0x1b5c
+#define mmSCL0_VIEWPORT_START 0x1b5c
+#define mmSCL1_VIEWPORT_START 0x1d5c
+#define mmSCL2_VIEWPORT_START 0x1f5c
+#define mmSCL3_VIEWPORT_START 0x415c
+#define mmSCL4_VIEWPORT_START 0x435c
+#define mmSCL5_VIEWPORT_START 0x455c
+#define mmVIEWPORT_SIZE 0x1b5d
+#define mmSCL0_VIEWPORT_SIZE 0x1b5d
+#define mmSCL1_VIEWPORT_SIZE 0x1d5d
+#define mmSCL2_VIEWPORT_SIZE 0x1f5d
+#define mmSCL3_VIEWPORT_SIZE 0x415d
+#define mmSCL4_VIEWPORT_SIZE 0x435d
+#define mmSCL5_VIEWPORT_SIZE 0x455d
+#define mmEXT_OVERSCAN_LEFT_RIGHT 0x1b5e
+#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1b5e
+#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1d5e
+#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x1f5e
+#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x415e
+#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x435e
+#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x455e
+#define mmEXT_OVERSCAN_TOP_BOTTOM 0x1b5f
+#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1b5f
+#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1d5f
+#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x1f5f
+#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x415f
+#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x435f
+#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x455f
+#define mmSCL_MODE_CHANGE_DET1 0x1b60
+#define mmSCL0_SCL_MODE_CHANGE_DET1 0x1b60
+#define mmSCL1_SCL_MODE_CHANGE_DET1 0x1d60
+#define mmSCL2_SCL_MODE_CHANGE_DET1 0x1f60
+#define mmSCL3_SCL_MODE_CHANGE_DET1 0x4160
+#define mmSCL4_SCL_MODE_CHANGE_DET1 0x4360
+#define mmSCL5_SCL_MODE_CHANGE_DET1 0x4560
+#define mmSCL_MODE_CHANGE_DET2 0x1b61
+#define mmSCL0_SCL_MODE_CHANGE_DET2 0x1b61
+#define mmSCL1_SCL_MODE_CHANGE_DET2 0x1d61
+#define mmSCL2_SCL_MODE_CHANGE_DET2 0x1f61
+#define mmSCL3_SCL_MODE_CHANGE_DET2 0x4161
+#define mmSCL4_SCL_MODE_CHANGE_DET2 0x4361
+#define mmSCL5_SCL_MODE_CHANGE_DET2 0x4561
+#define mmSCL_MODE_CHANGE_DET3 0x1b62
+#define mmSCL0_SCL_MODE_CHANGE_DET3 0x1b62
+#define mmSCL1_SCL_MODE_CHANGE_DET3 0x1d62
+#define mmSCL2_SCL_MODE_CHANGE_DET3 0x1f62
+#define mmSCL3_SCL_MODE_CHANGE_DET3 0x4162
+#define mmSCL4_SCL_MODE_CHANGE_DET3 0x4362
+#define mmSCL5_SCL_MODE_CHANGE_DET3 0x4562
+#define mmSCL_MODE_CHANGE_MASK 0x1b63
+#define mmSCL0_SCL_MODE_CHANGE_MASK 0x1b63
+#define mmSCL1_SCL_MODE_CHANGE_MASK 0x1d63
+#define mmSCL2_SCL_MODE_CHANGE_MASK 0x1f63
+#define mmSCL3_SCL_MODE_CHANGE_MASK 0x4163
+#define mmSCL4_SCL_MODE_CHANGE_MASK 0x4363
+#define mmSCL5_SCL_MODE_CHANGE_MASK 0x4563
+#define mmSCL_DEBUG2 0x1b69
+#define mmSCL0_SCL_DEBUG2 0x1b69
+#define mmSCL1_SCL_DEBUG2 0x1d69
+#define mmSCL2_SCL_DEBUG2 0x1f69
+#define mmSCL3_SCL_DEBUG2 0x4169
+#define mmSCL4_SCL_DEBUG2 0x4369
+#define mmSCL5_SCL_DEBUG2 0x4569
+#define mmSCL_DEBUG 0x1b6a
+#define mmSCL0_SCL_DEBUG 0x1b6a
+#define mmSCL1_SCL_DEBUG 0x1d6a
+#define mmSCL2_SCL_DEBUG 0x1f6a
+#define mmSCL3_SCL_DEBUG 0x416a
+#define mmSCL4_SCL_DEBUG 0x436a
+#define mmSCL5_SCL_DEBUG 0x456a
+#define mmSCL_TEST_DEBUG_INDEX 0x1b6b
+#define mmSCL0_SCL_TEST_DEBUG_INDEX 0x1b6b
+#define mmSCL1_SCL_TEST_DEBUG_INDEX 0x1d6b
+#define mmSCL2_SCL_TEST_DEBUG_INDEX 0x1f6b
+#define mmSCL3_SCL_TEST_DEBUG_INDEX 0x416b
+#define mmSCL4_SCL_TEST_DEBUG_INDEX 0x436b
+#define mmSCL5_SCL_TEST_DEBUG_INDEX 0x456b
+#define mmSCL_TEST_DEBUG_DATA 0x1b6c
+#define mmSCL0_SCL_TEST_DEBUG_DATA 0x1b6c
+#define mmSCL1_SCL_TEST_DEBUG_DATA 0x1d6c
+#define mmSCL2_SCL_TEST_DEBUG_DATA 0x1f6c
+#define mmSCL3_SCL_TEST_DEBUG_DATA 0x416c
+#define mmSCL4_SCL_TEST_DEBUG_DATA 0x436c
+#define mmSCL5_SCL_TEST_DEBUG_DATA 0x456c
+#define mmSCLV_COEF_RAM_SELECT 0x4670
+#define mmSCLV_COEF_RAM_TAP_DATA 0x4671
+#define mmSCLV_MODE 0x4672
+#define mmSCLV_TAP_CONTROL 0x4673
+#define mmSCLV_CONTROL 0x4674
+#define mmSCLV_MANUAL_REPLICATE_CONTROL 0x4675
+#define mmSCLV_AUTOMATIC_MODE_CONTROL 0x4676
+#define mmSCLV_HORZ_FILTER_CONTROL 0x4677
+#define mmSCLV_HORZ_FILTER_SCALE_RATIO 0x4678
+#define mmSCLV_HORZ_FILTER_INIT 0x4679
+#define mmSCLV_HORZ_FILTER_SCALE_RATIO_C 0x467a
+#define mmSCLV_HORZ_FILTER_INIT_C 0x467b
+#define mmSCLV_VERT_FILTER_CONTROL 0x467c
+#define mmSCLV_VERT_FILTER_SCALE_RATIO 0x467d
+#define mmSCLV_VERT_FILTER_INIT 0x467e
+#define mmSCLV_VERT_FILTER_INIT_BOT 0x467f
+#define mmSCLV_VERT_FILTER_SCALE_RATIO_C 0x4680
+#define mmSCLV_VERT_FILTER_INIT_C 0x4681
+#define mmSCLV_VERT_FILTER_INIT_BOT_C 0x4682
+#define mmSCLV_ROUND_OFFSET 0x4683
+#define mmSCLV_UPDATE 0x4684
+#define mmSCLV_ALU_CONTROL 0x4685
+#define mmSCLV_VIEWPORT_START 0x4686
+#define mmSCLV_VIEWPORT_START_SECONDARY 0x4687
+#define mmSCLV_VIEWPORT_SIZE 0x4688
+#define mmSCLV_VIEWPORT_START_C 0x4689
+#define mmSCLV_VIEWPORT_START_SECONDARY_C 0x468a
+#define mmSCLV_VIEWPORT_SIZE_C 0x468b
+#define mmSCLV_EXT_OVERSCAN_LEFT_RIGHT 0x468c
+#define mmSCLV_EXT_OVERSCAN_TOP_BOTTOM 0x468d
+#define mmSCLV_MODE_CHANGE_DET1 0x468e
+#define mmSCLV_MODE_CHANGE_DET2 0x468f
+#define mmSCLV_MODE_CHANGE_DET3 0x4690
+#define mmSCLV_MODE_CHANGE_MASK 0x4691
+#define mmSCLV_HORZ_FILTER_INIT_BOT 0x4692
+#define mmSCLV_HORZ_FILTER_INIT_BOT_C 0x4693
+#define mmSCLV_DEBUG2 0x4694
+#define mmSCLV_DEBUG 0x4695
+#define mmSCLV_TEST_DEBUG_INDEX 0x4696
+#define mmSCLV_TEST_DEBUG_DATA 0x4697
+#define mmCOL_MAN_UPDATE 0x46a4
+#define mmCOL_MAN_INPUT_CSC_CONTROL 0x46a5
+#define mmINPUT_CSC_C11_C12_A 0x46a6
+#define mmINPUT_CSC_C13_C14_A 0x46a7
+#define mmINPUT_CSC_C21_C22_A 0x46a8
+#define mmINPUT_CSC_C23_C24_A 0x46a9
+#define mmINPUT_CSC_C31_C32_A 0x46aa
+#define mmINPUT_CSC_C33_C34_A 0x46ab
+#define mmINPUT_CSC_C11_C12_B 0x46ac
+#define mmINPUT_CSC_C13_C14_B 0x46ad
+#define mmINPUT_CSC_C21_C22_B 0x46ae
+#define mmINPUT_CSC_C23_C24_B 0x46af
+#define mmINPUT_CSC_C31_C32_B 0x46b0
+#define mmINPUT_CSC_C33_C34_B 0x46b1
+#define mmPRESCALE_CONTROL 0x46b2
+#define mmPRESCALE_VALUES_R 0x46b3
+#define mmPRESCALE_VALUES_G 0x46b4
+#define mmPRESCALE_VALUES_B 0x46b5
+#define mmCOL_MAN_OUTPUT_CSC_CONTROL 0x46b6
+#define mmOUTPUT_CSC_C11_C12_A 0x46b7
+#define mmOUTPUT_CSC_C13_C14_A 0x46b8
+#define mmOUTPUT_CSC_C21_C22_A 0x46b9
+#define mmOUTPUT_CSC_C23_C24_A 0x46ba
+#define mmOUTPUT_CSC_C31_C32_A 0x46bb
+#define mmOUTPUT_CSC_C33_C34_A 0x46bc
+#define mmOUTPUT_CSC_C11_C12_B 0x46bd
+#define mmOUTPUT_CSC_C13_C14_B 0x46be
+#define mmOUTPUT_CSC_C21_C22_B 0x46bf
+#define mmOUTPUT_CSC_C23_C24_B 0x46c0
+#define mmOUTPUT_CSC_C31_C32_B 0x46c1
+#define mmOUTPUT_CSC_C33_C34_B 0x46c2
+#define mmDENORM_CLAMP_CONTROL 0x46c3
+#define mmDENORM_CLAMP_RANGE_R_CR 0x46c4
+#define mmDENORM_CLAMP_RANGE_G_Y 0x46c5
+#define mmDENORM_CLAMP_RANGE_B_CB 0x46c6
+#define mmCOL_MAN_FP_CONVERTED_FIELD 0x46c7
+#define mmGAMMA_CORR_CONTROL 0x46c8
+#define mmGAMMA_CORR_LUT_INDEX 0x46c9
+#define mmGAMMA_CORR_LUT_DATA 0x46ca
+#define mmGAMMA_CORR_LUT_WRITE_EN_MASK 0x46cb
+#define mmGAMMA_CORR_CNTLA_START_CNTL 0x46cc
+#define mmGAMMA_CORR_CNTLA_SLOPE_CNTL 0x46cd
+#define mmGAMMA_CORR_CNTLA_END_CNTL1 0x46ce
+#define mmGAMMA_CORR_CNTLA_END_CNTL2 0x46cf
+#define mmGAMMA_CORR_CNTLA_REGION_0_1 0x46d0
+#define mmGAMMA_CORR_CNTLA_REGION_2_3 0x46d1
+#define mmGAMMA_CORR_CNTLA_REGION_4_5 0x46d2
+#define mmGAMMA_CORR_CNTLA_REGION_6_7 0x46d3
+#define mmGAMMA_CORR_CNTLA_REGION_8_9 0x46d4
+#define mmGAMMA_CORR_CNTLA_REGION_10_11 0x46d5
+#define mmGAMMA_CORR_CNTLA_REGION_12_13 0x46d6
+#define mmGAMMA_CORR_CNTLA_REGION_14_15 0x46d7
+#define mmGAMMA_CORR_CNTLB_START_CNTL 0x46d8
+#define mmGAMMA_CORR_CNTLB_SLOPE_CNTL 0x46d9
+#define mmGAMMA_CORR_CNTLB_END_CNTL1 0x46da
+#define mmGAMMA_CORR_CNTLB_END_CNTL2 0x46db
+#define mmGAMMA_CORR_CNTLB_REGION_0_1 0x46dc
+#define mmGAMMA_CORR_CNTLB_REGION_2_3 0x46dd
+#define mmGAMMA_CORR_CNTLB_REGION_4_5 0x46de
+#define mmGAMMA_CORR_CNTLB_REGION_6_7 0x46df
+#define mmGAMMA_CORR_CNTLB_REGION_8_9 0x46e0
+#define mmGAMMA_CORR_CNTLB_REGION_10_11 0x46e1
+#define mmGAMMA_CORR_CNTLB_REGION_12_13 0x46e2
+#define mmGAMMA_CORR_CNTLB_REGION_14_15 0x46e3
+#define mmPACK_FIFO_ERROR 0x46e4
+#define mmOUTPUT_FIFO_ERROR 0x46e5
+#define mmINPUT_GAMMA_LUT_AUTOFILL 0x46e6
+#define mmINPUT_GAMMA_LUT_RW_INDEX 0x46e7
+#define mmINPUT_GAMMA_LUT_SEQ_COLOR 0x46e8
+#define mmINPUT_GAMMA_LUT_PWL_DATA 0x46e9
+#define mmINPUT_GAMMA_LUT_30_COLOR 0x46ea
+#define mmCOL_MAN_INPUT_GAMMA_CONTROL1 0x46eb
+#define mmCOL_MAN_INPUT_GAMMA_CONTROL2 0x46ec
+#define mmINPUT_GAMMA_BW_OFFSETS_B 0x46ed
+#define mmINPUT_GAMMA_BW_OFFSETS_G 0x46ee
+#define mmINPUT_GAMMA_BW_OFFSETS_R 0x46ef
+#define mmCOL_MAN_DEBUG_CONTROL 0x46f0
+#define mmCOL_MAN_TEST_DEBUG_INDEX 0x46f1
+#define mmCOL_MAN_TEST_DEBUG_DATA 0x46f3
+#define mmUNP_GRPH_ENABLE 0x4600
+#define mmUNP_GRPH_CONTROL 0x4601
+#define mmUNP_GRPH_CONTROL_C 0x4602
+#define mmUNP_GRPH_CONTROL_EXP 0x4603
+#define mmUNP_GRPH_SWAP_CNTL 0x4605
+#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x4606
+#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x4607
+#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x4608
+#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x4609
+#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x460a
+#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x460b
+#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x460c
+#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x460d
+#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x460e
+#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x460f
+#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x4610
+#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x4611
+#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x4612
+#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x4613
+#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x4614
+#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x4615
+#define mmUNP_GRPH_PITCH_L 0x4616
+#define mmUNP_GRPH_PITCH_C 0x4617
+#define mmUNP_GRPH_SURFACE_OFFSET_X_L 0x4618
+#define mmUNP_GRPH_SURFACE_OFFSET_X_C 0x4619
+#define mmUNP_GRPH_SURFACE_OFFSET_Y_L 0x461a
+#define mmUNP_GRPH_SURFACE_OFFSET_Y_C 0x461b
+#define mmUNP_GRPH_X_START_L 0x461c
+#define mmUNP_GRPH_X_START_C 0x461d
+#define mmUNP_GRPH_Y_START_L 0x461e
+#define mmUNP_GRPH_Y_START_C 0x461f
+#define mmUNP_GRPH_X_END_L 0x4620
+#define mmUNP_GRPH_X_END_C 0x4621
+#define mmUNP_GRPH_Y_END_L 0x4622
+#define mmUNP_GRPH_Y_END_C 0x4623
+#define mmUNP_GRPH_UPDATE 0x4624
+#define mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x463a
+#define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x4625
+#define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x4626
+#define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x4627
+#define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x4628
+#define mmUNP_DVMM_PTE_CONTROL 0x4629
+#define mmUNP_DVMM_PTE_CONTROL_C 0x4604
+#define mmUNP_DVMM_PTE_ARB_CONTROL 0x462a
+#define mmUNP_DVMM_PTE_ARB_CONTROL_C 0x462d
+#define mmUNP_GRPH_INTERRUPT_STATUS 0x462b
+#define mmUNP_GRPH_INTERRUPT_CONTROL 0x462c
+#define mmUNP_GRPH_STEREOSYNC_FLIP 0x462e
+#define mmUNP_FLIP_CONTROL 0x462f
+#define mmUNP_CRC_CONTROL 0x4630
+#define mmUNP_CRC_MASK 0x4631
+#define mmUNP_CRC_CURRENT 0x4632
+#define mmUNP_CRC_LAST 0x4633
+#define mmUNP_LB_DATA_GAP_BETWEEN_CHUNK 0x4634
+#define mmUNP_HW_ROTATION 0x4635
+#define mmUNP_DEBUG 0x4636
+#define mmUNP_DEBUG2 0x4637
+#define mmUNP_DVMM_DEBUG 0x463b
+#define mmUNP_TEST_DEBUG_INDEX 0x4638
+#define mmUNP_TEST_DEBUG_DATA 0x4639
+#define mmGENMO_WT 0xf0
+#define mmGENMO_RD 0xf3
+#define mmGENENB 0xf0
+#define mmGENFC_WT 0xee
+#define mmVGA0_GENFC_WT 0xee
+#define mmVGA1_GENFC_WT 0xf6
+#define mmGENFC_RD 0xf2
+#define mmGENS0 0xf0
+#define mmGENS1 0xee
+#define mmVGA0_GENS1 0xee
+#define mmVGA1_GENS1 0xf6
+#define mmDAC_DATA 0xf2
+#define mmDAC_MASK 0xf1
+#define mmDAC_R_INDEX 0xf1
+#define mmDAC_W_INDEX 0xf2
+#define mmSEQ8_IDX 0xf1
+#define mmSEQ8_DATA 0xf1
+#define ixSEQ00 0x0
+#define ixSEQ01 0x1
+#define ixSEQ02 0x2
+#define ixSEQ03 0x3
+#define ixSEQ04 0x4
+#define mmCRTC8_IDX 0xed
+#define mmVGA0_CRTC8_IDX 0xed
+#define mmVGA1_CRTC8_IDX 0xf5
+#define mmCRTC8_DATA 0xed
+#define mmVGA0_CRTC8_DATA 0xed
+#define mmVGA1_CRTC8_DATA 0xf5
+#define ixCRT00 0x0
+#define ixCRT01 0x1
+#define ixCRT02 0x2
+#define ixCRT03 0x3
+#define ixCRT04 0x4
+#define ixCRT05 0x5
+#define ixCRT06 0x6
+#define ixCRT07 0x7
+#define ixCRT08 0x8
+#define ixCRT09 0x9
+#define ixCRT0A 0xa
+#define ixCRT0B 0xb
+#define ixCRT0C 0xc
+#define ixCRT0D 0xd
+#define ixCRT0E 0xe
+#define ixCRT0F 0xf
+#define ixCRT10 0x10
+#define ixCRT11 0x11
+#define ixCRT12 0x12
+#define ixCRT13 0x13
+#define ixCRT14 0x14
+#define ixCRT15 0x15
+#define ixCRT16 0x16
+#define ixCRT17 0x17
+#define ixCRT18 0x18
+#define ixCRT1E 0x1e
+#define ixCRT1F 0x1f
+#define ixCRT22 0x22
+#define mmGRPH8_IDX 0xf3
+#define mmGRPH8_DATA 0xf3
+#define ixGRA00 0x0
+#define ixGRA01 0x1
+#define ixGRA02 0x2
+#define ixGRA03 0x3
+#define ixGRA04 0x4
+#define ixGRA05 0x5
+#define ixGRA06 0x6
+#define ixGRA07 0x7
+#define ixGRA08 0x8
+#define mmATTRX 0xf0
+#define mmATTRDW 0xf0
+#define mmATTRDR 0xf0
+#define ixATTR00 0x0
+#define ixATTR01 0x1
+#define ixATTR02 0x2
+#define ixATTR03 0x3
+#define ixATTR04 0x4
+#define ixATTR05 0x5
+#define ixATTR06 0x6
+#define ixATTR07 0x7
+#define ixATTR08 0x8
+#define ixATTR09 0x9
+#define ixATTR0A 0xa
+#define ixATTR0B 0xb
+#define ixATTR0C 0xc
+#define ixATTR0D 0xd
+#define ixATTR0E 0xe
+#define ixATTR0F 0xf
+#define ixATTR10 0x10
+#define ixATTR11 0x11
+#define ixATTR12 0x12
+#define ixATTR13 0x13
+#define ixATTR14 0x14
+#define mmVGA_RENDER_CONTROL 0xc0
+#define mmVGA_SOURCE_SELECT 0xfc
+#define mmVGA_SEQUENCER_RESET_CONTROL 0xc1
+#define mmVGA_MODE_CONTROL 0xc2
+#define mmVGA_SURFACE_PITCH_SELECT 0xc3
+#define mmVGA_MEMORY_BASE_ADDRESS 0xc4
+#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0xc9
+#define mmVGA_DISPBUF1_SURFACE_ADDR 0xc6
+#define mmVGA_DISPBUF2_SURFACE_ADDR 0xc8
+#define mmVGA_HDP_CONTROL 0xca
+#define mmVGA_CACHE_CONTROL 0xcb
+#define mmD1VGA_CONTROL 0xcc
+#define mmD2VGA_CONTROL 0xce
+#define mmD3VGA_CONTROL 0xf8
+#define mmD4VGA_CONTROL 0xf9
+#define mmD5VGA_CONTROL 0xfa
+#define mmD6VGA_CONTROL 0xfb
+#define mmVGA_HW_DEBUG 0xcf
+#define mmVGA_STATUS 0xd0
+#define mmVGA_INTERRUPT_CONTROL 0xd1
+#define mmVGA_STATUS_CLEAR 0xd2
+#define mmVGA_INTERRUPT_STATUS 0xd3
+#define mmVGA_MAIN_CONTROL 0xd4
+#define mmVGA_TEST_CONTROL 0xd5
+#define mmVGA_DEBUG_READBACK_INDEX 0xd6
+#define mmVGA_DEBUG_READBACK_DATA 0xd7
+#define mmVGA_MEM_WRITE_PAGE_ADDR 0x12
+#define mmVGA_MEM_READ_PAGE_ADDR 0x13
+#define mmVGA_TEST_DEBUG_INDEX 0xc5
+#define mmVGA_TEST_DEBUG_DATA 0xc7
+#define ixVGADCC_DBG_DCCIF_C 0x7e
+#define mmBPHYC_DAC_MACRO_CNTL 0x48b9
+#define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x48ba
+#define mmPLL_REF_DIV 0x1700
+#define mmBPHYC_PLL0_PLL_REF_DIV 0x1700
+#define mmBPHYC_PLL1_PLL_REF_DIV 0x172a
+#define mmBPHYC_PLL2_PLL_REF_DIV 0x1754
+#define mmPLL_FB_DIV 0x1701
+#define mmBPHYC_PLL0_PLL_FB_DIV 0x1701
+#define mmBPHYC_PLL1_PLL_FB_DIV 0x172b
+#define mmBPHYC_PLL2_PLL_FB_DIV 0x1755
+#define mmPLL_POST_DIV 0x1702
+#define mmBPHYC_PLL0_PLL_POST_DIV 0x1702
+#define mmBPHYC_PLL1_PLL_POST_DIV 0x172c
+#define mmBPHYC_PLL2_PLL_POST_DIV 0x1756
+#define mmPLL_SS_AMOUNT_DSFRAC 0x1703
+#define mmBPHYC_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703
+#define mmBPHYC_PLL1_PLL_SS_AMOUNT_DSFRAC 0x172d
+#define mmBPHYC_PLL2_PLL_SS_AMOUNT_DSFRAC 0x1757
+#define mmPLL_SS_CNTL 0x1704
+#define mmBPHYC_PLL0_PLL_SS_CNTL 0x1704
+#define mmBPHYC_PLL1_PLL_SS_CNTL 0x172e
+#define mmBPHYC_PLL2_PLL_SS_CNTL 0x1758
+#define mmPLL_DS_CNTL 0x1705
+#define mmBPHYC_PLL0_PLL_DS_CNTL 0x1705
+#define mmBPHYC_PLL1_PLL_DS_CNTL 0x172f
+#define mmBPHYC_PLL2_PLL_DS_CNTL 0x1759
+#define mmPLL_IDCLK_CNTL 0x1706
+#define mmBPHYC_PLL0_PLL_IDCLK_CNTL 0x1706
+#define mmBPHYC_PLL1_PLL_IDCLK_CNTL 0x1730
+#define mmBPHYC_PLL2_PLL_IDCLK_CNTL 0x175a
+#define mmPLL_CNTL 0x1707
+#define mmBPHYC_PLL0_PLL_CNTL 0x1707
+#define mmBPHYC_PLL1_PLL_CNTL 0x1731
+#define mmBPHYC_PLL2_PLL_CNTL 0x175b
+#define mmPLL_ANALOG 0x1708
+#define mmBPHYC_PLL0_PLL_ANALOG 0x1708
+#define mmBPHYC_PLL1_PLL_ANALOG 0x1732
+#define mmBPHYC_PLL2_PLL_ANALOG 0x175c
+#define mmPLL_VREG_CNTL 0x1709
+#define mmBPHYC_PLL0_PLL_VREG_CNTL 0x1709
+#define mmBPHYC_PLL1_PLL_VREG_CNTL 0x1733
+#define mmBPHYC_PLL2_PLL_VREG_CNTL 0x175d
+#define mmPLL_UNLOCK_DETECT_CNTL 0x170a
+#define mmBPHYC_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170a
+#define mmBPHYC_PLL1_PLL_UNLOCK_DETECT_CNTL 0x1734
+#define mmBPHYC_PLL2_PLL_UNLOCK_DETECT_CNTL 0x175e
+#define mmPLL_DEBUG_CNTL 0x170b
+#define mmBPHYC_PLL0_PLL_DEBUG_CNTL 0x170b
+#define mmBPHYC_PLL1_PLL_DEBUG_CNTL 0x1735
+#define mmBPHYC_PLL2_PLL_DEBUG_CNTL 0x175f
+#define mmPLL_UPDATE_LOCK 0x170c
+#define mmBPHYC_PLL0_PLL_UPDATE_LOCK 0x170c
+#define mmBPHYC_PLL1_PLL_UPDATE_LOCK 0x1736
+#define mmBPHYC_PLL2_PLL_UPDATE_LOCK 0x1760
+#define mmPLL_UPDATE_CNTL 0x170d
+#define mmBPHYC_PLL0_PLL_UPDATE_CNTL 0x170d
+#define mmBPHYC_PLL1_PLL_UPDATE_CNTL 0x1737
+#define mmBPHYC_PLL2_PLL_UPDATE_CNTL 0x1761
+#define mmPLL_XOR_LOCK 0x1710
+#define mmBPHYC_PLL0_PLL_XOR_LOCK 0x1710
+#define mmBPHYC_PLL1_PLL_XOR_LOCK 0x173a
+#define mmBPHYC_PLL2_PLL_XOR_LOCK 0x1764
+#define mmPLL_ANALOG_CNTL 0x1711
+#define mmBPHYC_PLL0_PLL_ANALOG_CNTL 0x1711
+#define mmBPHYC_PLL1_PLL_ANALOG_CNTL 0x173b
+#define mmBPHYC_PLL2_PLL_ANALOG_CNTL 0x1765
+#define mmVGA25_PPLL_REF_DIV 0x1712
+#define mmBPHYC_PLL0_VGA25_PPLL_REF_DIV 0x1712
+#define mmBPHYC_PLL1_VGA25_PPLL_REF_DIV 0x173c
+#define mmBPHYC_PLL2_VGA25_PPLL_REF_DIV 0x1766
+#define mmVGA28_PPLL_REF_DIV 0x1713
+#define mmBPHYC_PLL0_VGA28_PPLL_REF_DIV 0x1713
+#define mmBPHYC_PLL1_VGA28_PPLL_REF_DIV 0x173d
+#define mmBPHYC_PLL2_VGA28_PPLL_REF_DIV 0x1767
+#define mmVGA41_PPLL_REF_DIV 0x1714
+#define mmBPHYC_PLL0_VGA41_PPLL_REF_DIV 0x1714
+#define mmBPHYC_PLL1_VGA41_PPLL_REF_DIV 0x173e
+#define mmBPHYC_PLL2_VGA41_PPLL_REF_DIV 0x1768
+#define mmVGA25_PPLL_FB_DIV 0x1715
+#define mmBPHYC_PLL0_VGA25_PPLL_FB_DIV 0x1715
+#define mmBPHYC_PLL1_VGA25_PPLL_FB_DIV 0x173f
+#define mmBPHYC_PLL2_VGA25_PPLL_FB_DIV 0x1769
+#define mmVGA28_PPLL_FB_DIV 0x1716
+#define mmBPHYC_PLL0_VGA28_PPLL_FB_DIV 0x1716
+#define mmBPHYC_PLL1_VGA28_PPLL_FB_DIV 0x1740
+#define mmBPHYC_PLL2_VGA28_PPLL_FB_DIV 0x176a
+#define mmVGA41_PPLL_FB_DIV 0x1717
+#define mmBPHYC_PLL0_VGA41_PPLL_FB_DIV 0x1717
+#define mmBPHYC_PLL1_VGA41_PPLL_FB_DIV 0x1741
+#define mmBPHYC_PLL2_VGA41_PPLL_FB_DIV 0x176b
+#define mmVGA25_PPLL_POST_DIV 0x1718
+#define mmBPHYC_PLL0_VGA25_PPLL_POST_DIV 0x1718
+#define mmBPHYC_PLL1_VGA25_PPLL_POST_DIV 0x1742
+#define mmBPHYC_PLL2_VGA25_PPLL_POST_DIV 0x176c
+#define mmVGA28_PPLL_POST_DIV 0x1719
+#define mmBPHYC_PLL0_VGA28_PPLL_POST_DIV 0x1719
+#define mmBPHYC_PLL1_VGA28_PPLL_POST_DIV 0x1743
+#define mmBPHYC_PLL2_VGA28_PPLL_POST_DIV 0x176d
+#define mmVGA41_PPLL_POST_DIV 0x171a
+#define mmBPHYC_PLL0_VGA41_PPLL_POST_DIV 0x171a
+#define mmBPHYC_PLL1_VGA41_PPLL_POST_DIV 0x1744
+#define mmBPHYC_PLL2_VGA41_PPLL_POST_DIV 0x176e
+#define mmVGA25_PPLL_ANALOG 0x171b
+#define mmBPHYC_PLL0_VGA25_PPLL_ANALOG 0x171b
+#define mmBPHYC_PLL1_VGA25_PPLL_ANALOG 0x1745
+#define mmBPHYC_PLL2_VGA25_PPLL_ANALOG 0x176f
+#define mmVGA28_PPLL_ANALOG 0x171c
+#define mmBPHYC_PLL0_VGA28_PPLL_ANALOG 0x171c
+#define mmBPHYC_PLL1_VGA28_PPLL_ANALOG 0x1746
+#define mmBPHYC_PLL2_VGA28_PPLL_ANALOG 0x1770
+#define mmVGA41_PPLL_ANALOG 0x171d
+#define mmBPHYC_PLL0_VGA41_PPLL_ANALOG 0x171d
+#define mmBPHYC_PLL1_VGA41_PPLL_ANALOG 0x1747
+#define mmBPHYC_PLL2_VGA41_PPLL_ANALOG 0x1771
+#define mmDISPPLL_BG_CNTL 0x171e
+#define mmBPHYC_PLL0_DISPPLL_BG_CNTL 0x171e
+#define mmBPHYC_PLL1_DISPPLL_BG_CNTL 0x1748
+#define mmBPHYC_PLL2_DISPPLL_BG_CNTL 0x1772
+#define mmPPLL_DIV_UPDATE_DEBUG 0x171f
+#define mmBPHYC_PLL0_PPLL_DIV_UPDATE_DEBUG 0x171f
+#define mmBPHYC_PLL1_PPLL_DIV_UPDATE_DEBUG 0x1749
+#define mmBPHYC_PLL2_PPLL_DIV_UPDATE_DEBUG 0x1773
+#define mmPPLL_STATUS_DEBUG 0x1720
+#define mmBPHYC_PLL0_PPLL_STATUS_DEBUG 0x1720
+#define mmBPHYC_PLL1_PPLL_STATUS_DEBUG 0x174a
+#define mmBPHYC_PLL2_PPLL_STATUS_DEBUG 0x1774
+#define mmPPLL_DEBUG_MUX_CNTL 0x1721
+#define mmBPHYC_PLL0_PPLL_DEBUG_MUX_CNTL 0x1721
+#define mmBPHYC_PLL1_PPLL_DEBUG_MUX_CNTL 0x174b
+#define mmBPHYC_PLL2_PPLL_DEBUG_MUX_CNTL 0x1775
+#define mmPPLL_SPARE0 0x1722
+#define mmBPHYC_PLL0_PPLL_SPARE0 0x1722
+#define mmBPHYC_PLL1_PPLL_SPARE0 0x174c
+#define mmBPHYC_PLL2_PPLL_SPARE0 0x1776
+#define mmPPLL_SPARE1 0x1723
+#define mmBPHYC_PLL0_PPLL_SPARE1 0x1723
+#define mmBPHYC_PLL1_PPLL_SPARE1 0x174d
+#define mmBPHYC_PLL2_PPLL_SPARE1 0x1777
+#define mmUNIPHY_TX_CONTROL1 0x48c0
+#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1 0x48c0
+#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1 0x48e0
+#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1 0x4900
+#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1 0x4920
+#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1 0x4940
+#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1 0x4960
+#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1 0x4980
+#define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL1 0x49c0
+#define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL1 0x49e0
+#define mmUNIPHY_TX_CONTROL2 0x48c1
+#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2 0x48c1
+#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2 0x48e1
+#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2 0x4901
+#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2 0x4921
+#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2 0x4941
+#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2 0x4961
+#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2 0x4981
+#define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL2 0x49c1
+#define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL2 0x49e1
+#define mmUNIPHY_TX_CONTROL3 0x48c2
+#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3 0x48c2
+#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3 0x48e2
+#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3 0x4902
+#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3 0x4922
+#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3 0x4942
+#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3 0x4962
+#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3 0x4982
+#define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL3 0x49c2
+#define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL3 0x49e2
+#define mmUNIPHY_TX_CONTROL4 0x48c3
+#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4 0x48c3
+#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4 0x48e3
+#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4 0x4903
+#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4 0x4923
+#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4 0x4943
+#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4 0x4963
+#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4 0x4983
+#define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL4 0x49c3
+#define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL4 0x49e3
+#define mmUNIPHY_POWER_CONTROL 0x48c4
+#define mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL 0x48c4
+#define mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL 0x48e4
+#define mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL 0x4904
+#define mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL 0x4924
+#define mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL 0x4944
+#define mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL 0x4964
+#define mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL 0x4984
+#define mmBPHYC_UNIPHY7_UNIPHY_POWER_CONTROL 0x49c4
+#define mmBPHYC_UNIPHY8_UNIPHY_POWER_CONTROL 0x49e4
+#define mmUNIPHY_PLL_FBDIV 0x48c5
+#define mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV 0x48c5
+#define mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV 0x48e5
+#define mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV 0x4905
+#define mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV 0x4925
+#define mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV 0x4945
+#define mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV 0x4965
+#define mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV 0x4985
+#define mmBPHYC_UNIPHY7_UNIPHY_PLL_FBDIV 0x49c5
+#define mmBPHYC_UNIPHY8_UNIPHY_PLL_FBDIV 0x49e5
+#define mmUNIPHY_PLL_CONTROL1 0x48c6
+#define mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1 0x48c6
+#define mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1 0x48e6
+#define mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1 0x4906
+#define mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1 0x4926
+#define mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1 0x4946
+#define mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1 0x4966
+#define mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1 0x4986
+#define mmBPHYC_UNIPHY7_UNIPHY_PLL_CONTROL1 0x49c6
+#define mmBPHYC_UNIPHY8_UNIPHY_PLL_CONTROL1 0x49e6
+#define mmUNIPHY_PLL_CONTROL2 0x48c7
+#define mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2 0x48c7
+#define mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2 0x48e7
+#define mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2 0x4907
+#define mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2 0x4927
+#define mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2 0x4947
+#define mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2 0x4967
+#define mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2 0x4987
+#define mmBPHYC_UNIPHY7_UNIPHY_PLL_CONTROL2 0x49c7
+#define mmBPHYC_UNIPHY8_UNIPHY_PLL_CONTROL2 0x49e7
+#define mmUNIPHY_PLL_SS_STEP_SIZE 0x48c8
+#define mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x48c8
+#define mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x48e8
+#define mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x4908
+#define mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x4928
+#define mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x4948
+#define mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x4968
+#define mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE 0x4988
+#define mmBPHYC_UNIPHY7_UNIPHY_PLL_SS_STEP_SIZE 0x49c8
+#define mmBPHYC_UNIPHY8_UNIPHY_PLL_SS_STEP_SIZE 0x49e8
+#define mmUNIPHY_PLL_SS_CNTL 0x48c9
+#define mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x48c9
+#define mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x48e9
+#define mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x4909
+#define mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x4929
+#define mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x4949
+#define mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x4969
+#define mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL 0x4989
+#define mmBPHYC_UNIPHY7_UNIPHY_PLL_SS_CNTL 0x49c9
+#define mmBPHYC_UNIPHY8_UNIPHY_PLL_SS_CNTL 0x49e9
+#define mmUNIPHY_DATA_SYNCHRONIZATION 0x48ca
+#define mmBPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x48ca
+#define mmBPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x48ea
+#define mmBPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x490a
+#define mmBPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x492a
+#define mmBPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x494a
+#define mmBPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x496a
+#define mmBPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION 0x498a
+#define mmBPHYC_UNIPHY7_UNIPHY_DATA_SYNCHRONIZATION 0x49ca
+#define mmBPHYC_UNIPHY8_UNIPHY_DATA_SYNCHRONIZATION 0x49ea
+#define mmUNIPHY_REG_TEST_OUTPUT 0x48cb
+#define mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x48cb
+#define mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x48eb
+#define mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x490b
+#define mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x492b
+#define mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x494b
+#define mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x496b
+#define mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT 0x498b
+#define mmBPHYC_UNIPHY7_UNIPHY_REG_TEST_OUTPUT 0x49cb
+#define mmBPHYC_UNIPHY8_UNIPHY_REG_TEST_OUTPUT 0x49eb
+#define mmUNIPHY_ANG_BIST_CNTL 0x48cc
+#define mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x48cc
+#define mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x48ec
+#define mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x490c
+#define mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x492c
+#define mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x494c
+#define mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x496c
+#define mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL 0x498c
+#define mmBPHYC_UNIPHY7_UNIPHY_ANG_BIST_CNTL 0x49cc
+#define mmBPHYC_UNIPHY8_UNIPHY_ANG_BIST_CNTL 0x49ec
+#define mmUNIPHY_REG_TEST_OUTPUT2 0x48cd
+#define mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 0x48cd
+#define mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 0x48ed
+#define mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 0x490d
+#define mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 0x492d
+#define mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 0x494d
+#define mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 0x496d
+#define mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 0x498d
+#define mmBPHYC_UNIPHY7_UNIPHY_REG_TEST_OUTPUT2 0x49cd
+#define mmBPHYC_UNIPHY8_UNIPHY_REG_TEST_OUTPUT2 0x49ed
+#define mmUNIPHY_TMDP_REG0 0x48ce
+#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG0 0x48ce
+#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG0 0x48ee
+#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG0 0x490e
+#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG0 0x492e
+#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG0 0x494e
+#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG0 0x496e
+#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG0 0x498e
+#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG0 0x49ce
+#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG0 0x49ee
+#define mmUNIPHY_TMDP_REG1 0x48cf
+#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG1 0x48cf
+#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG1 0x48ef
+#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG1 0x490f
+#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG1 0x492f
+#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG1 0x494f
+#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG1 0x496f
+#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG1 0x498f
+#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG1 0x49cf
+#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG1 0x49ef
+#define mmUNIPHY_TMDP_REG2 0x48d0
+#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG2 0x48d0
+#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG2 0x48f0
+#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG2 0x4910
+#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG2 0x4930
+#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG2 0x4950
+#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG2 0x4970
+#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG2 0x4990
+#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG2 0x49d0
+#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG2 0x49f0
+#define mmUNIPHY_TMDP_REG3 0x48d1
+#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG3 0x48d1
+#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG3 0x48f1
+#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG3 0x4911
+#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG3 0x4931
+#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG3 0x4951
+#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG3 0x4971
+#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG3 0x4991
+#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG3 0x49d1
+#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG3 0x49f1
+#define mmUNIPHY_TMDP_REG4 0x48d2
+#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG4 0x48d2
+#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG4 0x48f2
+#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG4 0x4912
+#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG4 0x4932
+#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG4 0x4952
+#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG4 0x4972
+#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG4 0x4992
+#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG4 0x49d2
+#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG4 0x49f2
+#define mmUNIPHY_TMDP_REG5 0x48d3
+#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG5 0x48d3
+#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG5 0x48f3
+#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG5 0x4913
+#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG5 0x4933
+#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG5 0x4953
+#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG5 0x4973
+#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG5 0x4993
+#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG5 0x49d3
+#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG5 0x49f3
+#define mmUNIPHY_TMDP_REG6 0x48d4
+#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG6 0x48d4
+#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG6 0x48f4
+#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG6 0x4914
+#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG6 0x4934
+#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG6 0x4954
+#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG6 0x4974
+#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG6 0x4994
+#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG6 0x49d4
+#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG6 0x49f4
+#define mmUNIPHY_TPG_CONTROL 0x48d5
+#define mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL 0x48d5
+#define mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL 0x48f5
+#define mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL 0x4915
+#define mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL 0x4935
+#define mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL 0x4955
+#define mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL 0x4975
+#define mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL 0x4995
+#define mmBPHYC_UNIPHY7_UNIPHY_TPG_CONTROL 0x49d5
+#define mmBPHYC_UNIPHY8_UNIPHY_TPG_CONTROL 0x49f5
+#define mmUNIPHY_TPG_SEED 0x48d6
+#define mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED 0x48d6
+#define mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED 0x48f6
+#define mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED 0x4916
+#define mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED 0x4936
+#define mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED 0x4956
+#define mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED 0x4976
+#define mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED 0x4996
+#define mmBPHYC_UNIPHY7_UNIPHY_TPG_SEED 0x49d6
+#define mmBPHYC_UNIPHY8_UNIPHY_TPG_SEED 0x49f6
+#define mmUNIPHY_DEBUG 0x48d7
+#define mmBPHYC_UNIPHY0_UNIPHY_DEBUG 0x48d7
+#define mmBPHYC_UNIPHY1_UNIPHY_DEBUG 0x48f7
+#define mmBPHYC_UNIPHY2_UNIPHY_DEBUG 0x4917
+#define mmBPHYC_UNIPHY3_UNIPHY_DEBUG 0x4937
+#define mmBPHYC_UNIPHY4_UNIPHY_DEBUG 0x4957
+#define mmBPHYC_UNIPHY5_UNIPHY_DEBUG 0x4977
+#define mmBPHYC_UNIPHY6_UNIPHY_DEBUG 0x4997
+#define mmBPHYC_UNIPHY7_UNIPHY_DEBUG 0x49d7
+#define mmBPHYC_UNIPHY8_UNIPHY_DEBUG 0x49f7
+#define mmDPG_PIPE_ARBITRATION_CONTROL1 0x1b30
+#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1b30
+#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1d30
+#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x1f30
+#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4130
+#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4330
+#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4530
+#define mmDPG_PIPE_ARBITRATION_CONTROL2 0x1b31
+#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1b31
+#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1d31
+#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x1f31
+#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4131
+#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4331
+#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4531
+#define mmDPG_WATERMARK_MASK_CONTROL 0x1b32
+#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x1b32
+#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x1d32
+#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x1f32
+#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x4132
+#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x4332
+#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x4532
+#define mmDPG_PIPE_URGENCY_CONTROL 0x1b33
+#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1b33
+#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1d33
+#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x1f33
+#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4133
+#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4333
+#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4533
+#define mmDPG_PIPE_DPM_CONTROL 0x1b34
+#define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1b34
+#define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1d34
+#define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x1f34
+#define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4134
+#define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4334
+#define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4534
+#define mmDPG_PIPE_STUTTER_CONTROL 0x1b35
+#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1b35
+#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1d35
+#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x1f35
+#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4135
+#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4335
+#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4535
+#define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36
+#define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36
+#define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1d36
+#define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1f36
+#define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136
+#define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4336
+#define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4536
+#define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37
+#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37
+#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1d37
+#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1f37
+#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137
+#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4337
+#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4537
+#define mmDPG_REPEATER_PROGRAM 0x1b3a
+#define mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x1b3a
+#define mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x1d3a
+#define mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x1f3a
+#define mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x413a
+#define mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x433a
+#define mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x453a
+#define mmDPG_HW_DEBUG_A 0x1b3b
+#define mmDMIF_PG0_DPG_HW_DEBUG_A 0x1b3b
+#define mmDMIF_PG1_DPG_HW_DEBUG_A 0x1d3b
+#define mmDMIF_PG2_DPG_HW_DEBUG_A 0x1f3b
+#define mmDMIF_PG3_DPG_HW_DEBUG_A 0x413b
+#define mmDMIF_PG4_DPG_HW_DEBUG_A 0x433b
+#define mmDMIF_PG5_DPG_HW_DEBUG_A 0x453b
+#define mmDPG_HW_DEBUG_B 0x1b3c
+#define mmDMIF_PG0_DPG_HW_DEBUG_B 0x1b3c
+#define mmDMIF_PG1_DPG_HW_DEBUG_B 0x1d3c
+#define mmDMIF_PG2_DPG_HW_DEBUG_B 0x1f3c
+#define mmDMIF_PG3_DPG_HW_DEBUG_B 0x413c
+#define mmDMIF_PG4_DPG_HW_DEBUG_B 0x433c
+#define mmDMIF_PG5_DPG_HW_DEBUG_B 0x453c
+#define mmDPG_HW_DEBUG_11 0x1b3d
+#define mmDMIF_PG0_DPG_HW_DEBUG_11 0x1b3d
+#define mmDMIF_PG1_DPG_HW_DEBUG_11 0x1d3d
+#define mmDMIF_PG2_DPG_HW_DEBUG_11 0x1f3d
+#define mmDMIF_PG3_DPG_HW_DEBUG_11 0x413d
+#define mmDMIF_PG4_DPG_HW_DEBUG_11 0x433d
+#define mmDMIF_PG5_DPG_HW_DEBUG_11 0x453d
+#define mmDPG_CHK_PRE_PROC_CNTL 0x1b3e
+#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL 0x1b3e
+#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL 0x1d3e
+#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL 0x1f3e
+#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL 0x413e
+#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL 0x433e
+#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL 0x453e
+#define mmDPG_TEST_DEBUG_INDEX 0x1b38
+#define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1b38
+#define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1d38
+#define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x1f38
+#define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4138
+#define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4338
+#define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4538
+#define mmDPG_TEST_DEBUG_DATA 0x1b39
+#define mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1b39
+#define mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1d39
+#define mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x1f39
+#define mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4139
+#define mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4339
+#define mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4539
+#define mmDPGV0_PIPE_ARBITRATION_CONTROL1 0x4730
+#define mmDPGV1_PIPE_ARBITRATION_CONTROL1 0x473d
+#define mmDPGV0_PIPE_ARBITRATION_CONTROL2 0x4731
+#define mmDPGV1_PIPE_ARBITRATION_CONTROL2 0x473e
+#define mmDPGV0_WATERMARK_MASK_CONTROL 0x4732
+#define mmDPGV1_WATERMARK_MASK_CONTROL 0x473f
+#define mmDPGV0_PIPE_URGENCY_CONTROL 0x4733
+#define mmDPGV1_PIPE_URGENCY_CONTROL 0x4740
+#define mmDPGV0_PIPE_DPM_CONTROL 0x4734
+#define mmDPGV1_PIPE_DPM_CONTROL 0x4741
+#define mmDPGV0_PIPE_STUTTER_CONTROL 0x4735
+#define mmDPGV1_PIPE_STUTTER_CONTROL 0x4742
+#define mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736
+#define mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4743
+#define mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737
+#define mmDPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x4744
+#define mmDPGV0_REPEATER_PROGRAM 0x4738
+#define mmDPGV1_REPEATER_PROGRAM 0x4745
+#define mmDPGV0_HW_DEBUG_A 0x4739
+#define mmDPGV1_HW_DEBUG_A 0x4746
+#define mmDPGV0_HW_DEBUG_B 0x473a
+#define mmDPGV1_HW_DEBUG_B 0x4747
+#define mmDPGV0_HW_DEBUG_11 0x473b
+#define mmDPGV1_HW_DEBUG_11 0x4748
+#define mmDPGV0_CHK_PRE_PROC_CNTL 0x473c
+#define mmDPGV1_CHK_PRE_PROC_CNTL 0x4749
+#define mmDPGV_TEST_DEBUG_INDEX 0x474e
+#define mmDPGV_TEST_DEBUG_DATA 0x474f
+#define ixDPGV0_DEBUG00_DMIFARB 0x1
+#define ixDPGV1_DEBUG00_DMIFARB 0x6a
+#define ixDPGV0_DEBUG01_DMIFARB 0x2
+#define ixDPGV1_DEBUG01_DMIFARB 0x6b
+#define ixDPGV0_DEBUG02_DMIFARB 0x3
+#define ixDPGV1_DEBUG02_DMIFARB 0x6c
+#define ixDPGV0_DEBUG03_DMIFARB 0x4
+#define ixDPGV1_DEBUG03_DMIFARB 0x6d
+#define ixDPGV0_DEBUG04_DMIFARB 0x5
+#define ixDPGV1_DEBUG04_DMIFARB 0x6e
+#define ixDPGV0_DEBUG00 0x6
+#define ixDPGV1_DEBUG00 0x6f
+#define ixDPGV0_DEBUG01 0x7
+#define ixDPGV1_DEBUG01 0x70
+#define ixDPGV0_DEBUG02 0x8
+#define ixDPGV1_DEBUG02 0x71
+#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18
+#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0xf00
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0xf02
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0xf04
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x1828
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x1829
+#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x182a
+#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x182b
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x182c
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x182d
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x182e
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x182f
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1830
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x1831
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1832
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1833
+#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x1834
+#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x1835
+#define mmAZALIA_F0_CODEC_DEBUG 0x1836
+#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x1837
+#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x1838
+#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x1839
+#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x183a
+#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x183b
+#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x183c
+#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x183d
+#define mmGLOBAL_CAPABILITIES 0x0
+#define mmMINOR_VERSION 0x0
+#define mmMAJOR_VERSION 0x0
+#define mmOUTPUT_PAYLOAD_CAPABILITY 0x1
+#define mmINPUT_PAYLOAD_CAPABILITY 0x1
+#define mmGLOBAL_CONTROL 0x2
+#define mmWAKE_ENABLE 0x3
+#define mmSTATE_CHANGE_STATUS 0x3
+#define mmGLOBAL_STATUS 0x4
+#define mmOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x6
+#define mmINPUT_STREAM_PAYLOAD_CAPABILITY 0x6
+#define mmINTERRUPT_CONTROL 0x8
+#define mmINTERRUPT_STATUS 0x9
+#define mmWALL_CLOCK_COUNTER 0xc
+#define mmSTREAM_SYNCHRONIZATION 0xe
+#define mmCORB_LOWER_BASE_ADDRESS 0x10
+#define mmCORB_UPPER_BASE_ADDRESS 0x11
+#define mmCORB_WRITE_POINTER 0x12
+#define mmCORB_READ_POINTER 0x12
+#define mmCORB_CONTROL 0x13
+#define mmCORB_STATUS 0x13
+#define mmCORB_SIZE 0x13
+#define mmRIRB_LOWER_BASE_ADDRESS 0x14
+#define mmRIRB_UPPER_BASE_ADDRESS 0x15
+#define mmRIRB_WRITE_POINTER 0x16
+#define mmRESPONSE_INTERRUPT_COUNT 0x16
+#define mmRIRB_CONTROL 0x17
+#define mmRIRB_STATUS 0x17
+#define mmRIRB_SIZE 0x17
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x18
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18
+#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x19
+#define mmIMMEDIATE_COMMAND_STATUS 0x1a
+#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x1c
+#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x1d
+#define mmWALL_CLOCK_COUNTER_ALIAS 0x80c
+#define mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x20
+#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x21
+#define mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x22
+#define mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x23
+#define mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x24
+#define mmOUTPUT_STREAM_DESCRIPTOR_FORMAT 0x24
+#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x26
+#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x27
+#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x821
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e
+#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776
+#define ixAUDIO_DESCRIPTOR0 0x1
+#define ixAUDIO_DESCRIPTOR1 0x2
+#define ixAUDIO_DESCRIPTOR2 0x3
+#define ixAUDIO_DESCRIPTOR3 0x4
+#define ixAUDIO_DESCRIPTOR4 0x5
+#define ixAUDIO_DESCRIPTOR5 0x6
+#define ixAUDIO_DESCRIPTOR6 0x7
+#define ixAUDIO_DESCRIPTOR7 0x8
+#define ixAUDIO_DESCRIPTOR8 0x9
+#define ixAUDIO_DESCRIPTOR9 0xa
+#define ixAUDIO_DESCRIPTOR10 0xb
+#define ixAUDIO_DESCRIPTOR11 0xc
+#define ixAUDIO_DESCRIPTOR12 0xd
+#define ixAUDIO_DESCRIPTOR13 0xe
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x1
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x2
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x3
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x4
+#define ixSINK_DESCRIPTION0 0x5
+#define ixSINK_DESCRIPTION1 0x6
+#define ixSINK_DESCRIPTION2 0x7
+#define ixSINK_DESCRIPTION3 0x8
+#define ixSINK_DESCRIPTION4 0x9
+#define ixSINK_DESCRIPTION5 0xa
+#define ixSINK_DESCRIPTION6 0xb
+#define ixSINK_DESCRIPTION7 0xc
+#define ixSINK_DESCRIPTION8 0xd
+#define ixSINK_DESCRIPTION9 0xe
+#define ixSINK_DESCRIPTION10 0xf
+#define ixSINK_DESCRIPTION11 0x10
+#define ixSINK_DESCRIPTION12 0x11
+#define ixSINK_DESCRIPTION13 0x12
+#define ixSINK_DESCRIPTION14 0x13
+#define ixSINK_DESCRIPTION15 0x14
+#define ixSINK_DESCRIPTION16 0x15
+#define ixSINK_DESCRIPTION17 0x16
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792
+#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e
+#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x17e4
+#define mmAZALIA_AUDIO_DTO 0x17e5
+#define mmAZALIA_AUDIO_DTO_CONTROL 0x17e6
+#define mmAZALIA_SCLK_CONTROL 0x17e7
+#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17e8
+#define mmAZALIA_DATA_DMA_CONTROL 0x17e9
+#define mmAZALIA_BDL_DMA_CONTROL 0x17ea
+#define mmAZALIA_RIRB_AND_DP_CONTROL 0x17eb
+#define mmAZALIA_CORB_DMA_CONTROL 0x17ec
+#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17f3
+#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x17f4
+#define mmAZALIA_GLOBAL_CAPABILITIES 0x17f5
+#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17f6
+#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17f7
+#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x17f8
+#define mmAZALIA_CONTROLLER_DEBUG 0x17f9
+#define mmAZALIA_MEM_PWR_CTRL 0x1810
+#define mmAZALIA_MEM_PWR_STATUS 0x1811
+#define mmDCI_PG_DEBUG_CONFIG 0x1812
+#define mmAZALIA_INPUT_CRC0_CONTROL0 0x17fb
+#define mmAZALIA_INPUT_CRC0_CONTROL1 0x17fc
+#define mmAZALIA_INPUT_CRC0_CONTROL2 0x17fd
+#define mmAZALIA_INPUT_CRC0_CONTROL3 0x17fe
+#define mmAZALIA_INPUT_CRC0_RESULT 0x17ff
+#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0
+#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x1
+#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x2
+#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x3
+#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x4
+#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x5
+#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x6
+#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x7
+#define mmAZALIA_INPUT_CRC1_CONTROL0 0x1800
+#define mmAZALIA_INPUT_CRC1_CONTROL1 0x1801
+#define mmAZALIA_INPUT_CRC1_CONTROL2 0x1802
+#define mmAZALIA_INPUT_CRC1_CONTROL3 0x1803
+#define mmAZALIA_INPUT_CRC1_RESULT 0x1804
+#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0
+#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x1
+#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x2
+#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x3
+#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x4
+#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x5
+#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x6
+#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x7
+#define mmAZALIA_CRC0_CONTROL0 0x1805
+#define mmAZALIA_CRC0_CONTROL1 0x1806
+#define mmAZALIA_CRC0_CONTROL2 0x1807
+#define mmAZALIA_CRC0_CONTROL3 0x1808
+#define mmAZALIA_CRC0_RESULT 0x1809
+#define ixAZALIA_CRC0_CHANNEL0 0x0
+#define ixAZALIA_CRC0_CHANNEL1 0x1
+#define ixAZALIA_CRC0_CHANNEL2 0x2
+#define ixAZALIA_CRC0_CHANNEL3 0x3
+#define ixAZALIA_CRC0_CHANNEL4 0x4
+#define ixAZALIA_CRC0_CHANNEL5 0x5
+#define ixAZALIA_CRC0_CHANNEL6 0x6
+#define ixAZALIA_CRC0_CHANNEL7 0x7
+#define mmAZALIA_CRC1_CONTROL0 0x180a
+#define mmAZALIA_CRC1_CONTROL1 0x180b
+#define mmAZALIA_CRC1_CONTROL2 0x180c
+#define mmAZALIA_CRC1_CONTROL3 0x180d
+#define mmAZALIA_CRC1_RESULT 0x180e
+#define ixAZALIA_CRC1_CHANNEL0 0x0
+#define ixAZALIA_CRC1_CHANNEL1 0x1
+#define ixAZALIA_CRC1_CHANNEL2 0x2
+#define ixAZALIA_CRC1_CHANNEL3 0x3
+#define ixAZALIA_CRC1_CHANNEL4 0x4
+#define ixAZALIA_CRC1_CHANNEL5 0x5
+#define ixAZALIA_CRC1_CHANNEL6 0x6
+#define ixAZALIA_CRC1_CHANNEL7 0x7
+#define mmAZ_TEST_DEBUG_INDEX 0x181f
+#define mmAZ_TEST_DEBUG_DATA 0x1820
+#define mmAZALIA_STREAM_INDEX 0x1780
+#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x1780
+#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x1782
+#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x1784
+#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x1786
+#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x1788
+#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x178a
+#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x178c
+#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x178e
+#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x59c0
+#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x59c2
+#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x59c4
+#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x59c6
+#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x59c8
+#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x59ca
+#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x59cc
+#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x59ce
+#define mmAZALIA_STREAM_DATA 0x1781
+#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x1781
+#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x1783
+#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x1785
+#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x1787
+#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x1789
+#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x178b
+#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x178d
+#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x178f
+#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x59c1
+#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x59c3
+#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x59c5
+#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x59c7
+#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x59c9
+#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x59cb
+#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x59cd
+#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x59cf
+#define ixAZALIA_FIFO_SIZE_CONTROL 0x0
+#define ixAZALIA_LATENCY_COUNTER_CONTROL 0x1
+#define ixAZALIA_WORSTCASE_LATENCY_COUNT 0x2
+#define ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x3
+#define ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x4
+#define ixAZALIA_STREAM_DEBUG 0x5
+#define mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17ac
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b0
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b4
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b8
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17bc
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c0
+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c4
+#define mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17ad
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b1
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b5
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b9
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17bd
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c1
+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c5
+#define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0
+#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1
+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2
+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3
+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4
+#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x5
+#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6
+#define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x7
+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x8
+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x9
+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG 0xa
+#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0xc
+#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0xd
+#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0xe
+#define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20
+#define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x21
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x23
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x24
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2a
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2b
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2c
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2d
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2e
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2f
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x57
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x58
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x59
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x5a
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x5b
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x5c
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x5d
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x5e
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x5f
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x60
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x61
+#define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x62
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x63
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x65
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x67
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x68
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x69
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x6a
+#define ixAZALIA_F0_AUDIO_ENABLE_STATUS 0x6b
+#define ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x6c
+#define ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x6d
+#define ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x6e
+#define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4
+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4
+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d8
+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59dc
+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e0
+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e4
+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e8
+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59ec
+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59f0
+#define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5
+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5
+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d9
+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59dd
+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e1
+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e5
+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e9
+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59ed
+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59f1
+#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0
+#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1
+#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2
+#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3
+#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4
+#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x5
+#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6
+#define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20
+#define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x21
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x23
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x24
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x37
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x38
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x53
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x54
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x67
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x68
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x65
+#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x18
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x18
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a
+#define mmBLND_CONTROL 0x1b6d
+#define mmBLND0_BLND_CONTROL 0x1b6d
+#define mmBLND1_BLND_CONTROL 0x1d6d
+#define mmBLND2_BLND_CONTROL 0x1f6d
+#define mmBLND3_BLND_CONTROL 0x416d
+#define mmBLND4_BLND_CONTROL 0x436d
+#define mmBLND5_BLND_CONTROL 0x456d
+#define mmBLND_SM_CONTROL2 0x1b6e
+#define mmBLND0_BLND_SM_CONTROL2 0x1b6e
+#define mmBLND1_BLND_SM_CONTROL2 0x1d6e
+#define mmBLND2_BLND_SM_CONTROL2 0x1f6e
+#define mmBLND3_BLND_SM_CONTROL2 0x416e
+#define mmBLND4_BLND_SM_CONTROL2 0x436e
+#define mmBLND5_BLND_SM_CONTROL2 0x456e
+#define mmBLND_CONTROL2 0x1b6f
+#define mmBLND0_BLND_CONTROL2 0x1b6f
+#define mmBLND1_BLND_CONTROL2 0x1d6f
+#define mmBLND2_BLND_CONTROL2 0x1f6f
+#define mmBLND3_BLND_CONTROL2 0x416f
+#define mmBLND4_BLND_CONTROL2 0x436f
+#define mmBLND5_BLND_CONTROL2 0x456f
+#define mmBLND_UPDATE 0x1b70
+#define mmBLND0_BLND_UPDATE 0x1b70
+#define mmBLND1_BLND_UPDATE 0x1d70
+#define mmBLND2_BLND_UPDATE 0x1f70
+#define mmBLND3_BLND_UPDATE 0x4170
+#define mmBLND4_BLND_UPDATE 0x4370
+#define mmBLND5_BLND_UPDATE 0x4570
+#define mmBLND_UNDERFLOW_INTERRUPT 0x1b71
+#define mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x1b71
+#define mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x1d71
+#define mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x1f71
+#define mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x4171
+#define mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x4371
+#define mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x4571
+#define mmBLND_V_UPDATE_LOCK 0x1b73
+#define mmBLND0_BLND_V_UPDATE_LOCK 0x1b73
+#define mmBLND1_BLND_V_UPDATE_LOCK 0x1d73
+#define mmBLND2_BLND_V_UPDATE_LOCK 0x1f73
+#define mmBLND3_BLND_V_UPDATE_LOCK 0x4173
+#define mmBLND4_BLND_V_UPDATE_LOCK 0x4373
+#define mmBLND5_BLND_V_UPDATE_LOCK 0x4573
+#define mmBLND_REG_UPDATE_STATUS 0x1b77
+#define mmBLND0_BLND_REG_UPDATE_STATUS 0x1b77
+#define mmBLND1_BLND_REG_UPDATE_STATUS 0x1d77
+#define mmBLND2_BLND_REG_UPDATE_STATUS 0x1f77
+#define mmBLND3_BLND_REG_UPDATE_STATUS 0x4177
+#define mmBLND4_BLND_REG_UPDATE_STATUS 0x4377
+#define mmBLND5_BLND_REG_UPDATE_STATUS 0x4577
+#define mmBLND_DEBUG 0x1b74
+#define mmBLND0_BLND_DEBUG 0x1b74
+#define mmBLND1_BLND_DEBUG 0x1d74
+#define mmBLND2_BLND_DEBUG 0x1f74
+#define mmBLND3_BLND_DEBUG 0x4174
+#define mmBLND4_BLND_DEBUG 0x4374
+#define mmBLND5_BLND_DEBUG 0x4574
+#define mmBLND_TEST_DEBUG_INDEX 0x1b75
+#define mmBLND0_BLND_TEST_DEBUG_INDEX 0x1b75
+#define mmBLND1_BLND_TEST_DEBUG_INDEX 0x1d75
+#define mmBLND2_BLND_TEST_DEBUG_INDEX 0x1f75
+#define mmBLND3_BLND_TEST_DEBUG_INDEX 0x4175
+#define mmBLND4_BLND_TEST_DEBUG_INDEX 0x4375
+#define mmBLND5_BLND_TEST_DEBUG_INDEX 0x4575
+#define mmBLND_TEST_DEBUG_DATA 0x1b76
+#define mmBLND0_BLND_TEST_DEBUG_DATA 0x1b76
+#define mmBLND1_BLND_TEST_DEBUG_DATA 0x1d76
+#define mmBLND2_BLND_TEST_DEBUG_DATA 0x1f76
+#define mmBLND3_BLND_TEST_DEBUG_DATA 0x4176
+#define mmBLND4_BLND_TEST_DEBUG_DATA 0x4376
+#define mmBLND5_BLND_TEST_DEBUG_DATA 0x4576
+#define mmWB_ENABLE 0x5e18
+#define mmWB_EC_CONFIG 0x5e19
+#define mmCNV_MODE 0x5e1a
+#define mmCNV_WINDOW_START 0x5e1b
+#define mmCNV_WINDOW_SIZE 0x5e1c
+#define mmCNV_UPDATE 0x5e1d
+#define mmCNV_SOURCE_SIZE 0x5e1e
+#define mmCNV_CSC_CONTROL 0x5e1f
+#define mmCNV_CSC_C11_C12 0x5e20
+#define mmCNV_CSC_C13_C14 0x5e21
+#define mmCNV_CSC_C21_C22 0x5e22
+#define mmCNV_CSC_C23_C24 0x5e23
+#define mmCNV_CSC_C31_C32 0x5e24
+#define mmCNV_CSC_C33_C34 0x5e25
+#define mmCNV_CSC_ROUND_OFFSET_R 0x5e26
+#define mmCNV_CSC_ROUND_OFFSET_G 0x5e27
+#define mmCNV_CSC_ROUND_OFFSET_B 0x5e28
+#define mmCNV_CSC_CLAMP_R 0x5e29
+#define mmCNV_CSC_CLAMP_G 0x5e2a
+#define mmCNV_CSC_CLAMP_B 0x5e2b
+#define mmCNV_TEST_CNTL 0x5e2c
+#define mmCNV_TEST_CRC_RED 0x5e2d
+#define mmCNV_TEST_CRC_GREEN 0x5e2e
+#define mmCNV_TEST_CRC_BLUE 0x5e2f
+#define mmWB_DEBUG_CTRL 0x5e30
+#define mmWB_DBG_MODE 0x5e31
+#define mmWB_HW_DEBUG 0x5e32
+#define mmCNV_INPUT_SELECT 0x5e33
+#define mmWB_SOFT_RESET 0x5e36
+#define mmCNV_TEST_DEBUG_INDEX 0x5e34
+#define mmCNV_TEST_DEBUG_DATA 0x5e35
+#define mmDCFE_CLOCK_CONTROL 0x1b00
+#define mmDCFE0_DCFE_CLOCK_CONTROL 0x1b00
+#define mmDCFE1_DCFE_CLOCK_CONTROL 0x1d00
+#define mmDCFE2_DCFE_CLOCK_CONTROL 0x1f00
+#define mmDCFE3_DCFE_CLOCK_CONTROL 0x4100
+#define mmDCFE4_DCFE_CLOCK_CONTROL 0x4300
+#define mmDCFE5_DCFE_CLOCK_CONTROL 0x4500
+#define mmDCFE_SOFT_RESET 0x1b01
+#define mmDCFE0_DCFE_SOFT_RESET 0x1b01
+#define mmDCFE1_DCFE_SOFT_RESET 0x1d01
+#define mmDCFE2_DCFE_SOFT_RESET 0x1f01
+#define mmDCFE3_DCFE_SOFT_RESET 0x4101
+#define mmDCFE4_DCFE_SOFT_RESET 0x4301
+#define mmDCFE5_DCFE_SOFT_RESET 0x4501
+#define mmDCFE_DBG_CONFIG 0x1b02
+#define mmDCFE0_DCFE_DBG_CONFIG 0x1b02
+#define mmDCFE1_DCFE_DBG_CONFIG 0x1d02
+#define mmDCFE2_DCFE_DBG_CONFIG 0x1f02
+#define mmDCFE3_DCFE_DBG_CONFIG 0x4102
+#define mmDCFE4_DCFE_DBG_CONFIG 0x4302
+#define mmDCFE5_DCFE_DBG_CONFIG 0x4502
+#define mmDCFE_MEM_PWR_CTRL 0x1b03
+#define mmDCFE0_DCFE_MEM_PWR_CTRL 0x1b03
+#define mmDCFE1_DCFE_MEM_PWR_CTRL 0x1d03
+#define mmDCFE2_DCFE_MEM_PWR_CTRL 0x1f03
+#define mmDCFE3_DCFE_MEM_PWR_CTRL 0x4103
+#define mmDCFE4_DCFE_MEM_PWR_CTRL 0x4303
+#define mmDCFE5_DCFE_MEM_PWR_CTRL 0x4503
+#define mmDCFE_MEM_PWR_CTRL2 0x1b04
+#define mmDCFE0_DCFE_MEM_PWR_CTRL2 0x1b04
+#define mmDCFE1_DCFE_MEM_PWR_CTRL2 0x1d04
+#define mmDCFE2_DCFE_MEM_PWR_CTRL2 0x1f04
+#define mmDCFE3_DCFE_MEM_PWR_CTRL2 0x4104
+#define mmDCFE4_DCFE_MEM_PWR_CTRL2 0x4304
+#define mmDCFE5_DCFE_MEM_PWR_CTRL2 0x4504
+#define mmDCFE_MEM_PWR_STATUS 0x1b05
+#define mmDCFE0_DCFE_MEM_PWR_STATUS 0x1b05
+#define mmDCFE1_DCFE_MEM_PWR_STATUS 0x1d05
+#define mmDCFE2_DCFE_MEM_PWR_STATUS 0x1f05
+#define mmDCFE3_DCFE_MEM_PWR_STATUS 0x4105
+#define mmDCFE4_DCFE_MEM_PWR_STATUS 0x4305
+#define mmDCFE5_DCFE_MEM_PWR_STATUS 0x4505
+#define mmDCFE_MISC 0x1b06
+#define mmDCFE0_DCFE_MISC 0x1b06
+#define mmDCFE1_DCFE_MISC 0x1d06
+#define mmDCFE2_DCFE_MISC 0x1f06
+#define mmDCFE3_DCFE_MISC 0x4106
+#define mmDCFE4_DCFE_MISC 0x4306
+#define mmDCFE5_DCFE_MISC 0x4506
+#define mmDCFEV_CLOCK_CONTROL 0x46f4
+#define mmDCFEV_SOFT_RESET 0x46f5
+#define mmDCFEV_DMIFV_CLOCK_CONTROL 0x46f6
+#define mmDCFEV_DBG_CONFIG 0x46f7
+#define mmDCFEV_DMIFV_MEM_PWR_CTRL 0x46f8
+#define mmDCFEV_DMIFV_MEM_PWR_STATUS 0x46f9
+#define mmDCFEV_MEM_PWR_CTRL 0x46fa
+#define mmDCFEV_MEM_PWR_CTRL2 0x46fb
+#define mmDCFEV_MEM_PWR_STATUS 0x46fc
+#define mmDCFEV_DMIFV_DEBUG 0x46fd
+#define mmDCFEV_MISC 0x46fe
+#define mmDC_HPD_INT_STATUS 0x1898
+#define mmHPD0_DC_HPD_INT_STATUS 0x1898
+#define mmHPD1_DC_HPD_INT_STATUS 0x18a0
+#define mmHPD2_DC_HPD_INT_STATUS 0x18a8
+#define mmHPD3_DC_HPD_INT_STATUS 0x18b0
+#define mmHPD4_DC_HPD_INT_STATUS 0x18b8
+#define mmHPD5_DC_HPD_INT_STATUS 0x18c0
+#define mmDC_HPD_INT_CONTROL 0x1899
+#define mmHPD0_DC_HPD_INT_CONTROL 0x1899
+#define mmHPD1_DC_HPD_INT_CONTROL 0x18a1
+#define mmHPD2_DC_HPD_INT_CONTROL 0x18a9
+#define mmHPD3_DC_HPD_INT_CONTROL 0x18b1
+#define mmHPD4_DC_HPD_INT_CONTROL 0x18b9
+#define mmHPD5_DC_HPD_INT_CONTROL 0x18c1
+#define mmDC_HPD_CONTROL 0x189a
+#define mmHPD0_DC_HPD_CONTROL 0x189a
+#define mmHPD1_DC_HPD_CONTROL 0x18a2
+#define mmHPD2_DC_HPD_CONTROL 0x18aa
+#define mmHPD3_DC_HPD_CONTROL 0x18b2
+#define mmHPD4_DC_HPD_CONTROL 0x18ba
+#define mmHPD5_DC_HPD_CONTROL 0x18c2
+#define mmDC_HPD_FAST_TRAIN_CNTL 0x189b
+#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x189b
+#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x18a3
+#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x18ab
+#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x18b3
+#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x18bb
+#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x18c3
+#define mmDC_HPD_TOGGLE_FILT_CNTL 0x189c
+#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x189c
+#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x18a4
+#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x18ac
+#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x18b4
+#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x18bc
+#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x18c4
+#define mmDCO_SCRATCH0 0x184e
+#define mmDCO_SCRATCH1 0x184f
+#define mmDCO_SCRATCH2 0x1850
+#define mmDCO_SCRATCH3 0x1851
+#define mmDCO_SCRATCH4 0x1852
+#define mmDCO_SCRATCH5 0x1853
+#define mmDCO_SCRATCH6 0x1854
+#define mmDCO_SCRATCH7 0x1855
+#define mmDCE_VCE_CONTROL 0x1856
+#define mmDISP_INTERRUPT_STATUS 0x1857
+#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x1858
+#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x1859
+#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x185a
+#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x185b
+#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x185c
+#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x185d
+#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x185e
+#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x185f
+#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x1860
+#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x1875
+#define mmDCO_MEM_PWR_STATUS 0x1861
+#define mmDCO_MEM_PWR_STATUS1 0x1874
+#define mmDCO_MEM_PWR_CTRL 0x1862
+#define mmDCO_MEM_PWR_CTRL2 0x1863
+#define mmDCO_CLK_CNTL 0x1864
+#define mmDCO_CLK_CNTL2 0x1876
+#define mmDCO_CLK_CNTL3 0x1877
+#define mmDPDBG_CNTL 0x1866
+#define mmDPDBG_INTERRUPT 0x1867
+#define mmDCO_POWER_MANAGEMENT_CNTL 0x1868
+#define mmDCO_SOFT_RESET 0x1871
+#define mmDIG_SOFT_RESET 0x1872
+#define mmDIG_SOFT_RESET_2 0x186a
+#define mmDCO_STEREOSYNC_SEL 0x186e
+#define mmDCO_TEST_DEBUG_INDEX 0x186f
+#define mmDCO_TEST_DEBUG_DATA 0x1870
+#define mmDC_I2C_CONTROL 0x16d4
+#define mmDC_I2C_ARBITRATION 0x16d5
+#define mmDC_I2C_INTERRUPT_CONTROL 0x16d6
+#define mmDC_I2C_SW_STATUS 0x16d7
+#define mmDC_I2C_DDC1_HW_STATUS 0x16d8
+#define mmDC_I2C_DDC2_HW_STATUS 0x16d9
+#define mmDC_I2C_DDC3_HW_STATUS 0x16da
+#define mmDC_I2C_DDC4_HW_STATUS 0x16db
+#define mmDC_I2C_DDC5_HW_STATUS 0x16dc
+#define mmDC_I2C_DDC6_HW_STATUS 0x16dd
+#define mmDC_I2C_DDC1_SPEED 0x16de
+#define mmDC_I2C_DDC1_SETUP 0x16df
+#define mmDC_I2C_DDC2_SPEED 0x16e0
+#define mmDC_I2C_DDC2_SETUP 0x16e1
+#define mmDC_I2C_DDC3_SPEED 0x16e2
+#define mmDC_I2C_DDC3_SETUP 0x16e3
+#define mmDC_I2C_DDC4_SPEED 0x16e4
+#define mmDC_I2C_DDC4_SETUP 0x16e5
+#define mmDC_I2C_DDC5_SPEED 0x16e6
+#define mmDC_I2C_DDC5_SETUP 0x16e7
+#define mmDC_I2C_DDC6_SPEED 0x16e8
+#define mmDC_I2C_DDC6_SETUP 0x16e9
+#define mmDC_I2C_TRANSACTION0 0x16ea
+#define mmDC_I2C_TRANSACTION1 0x16eb
+#define mmDC_I2C_TRANSACTION2 0x16ec
+#define mmDC_I2C_TRANSACTION3 0x16ed
+#define mmDC_I2C_DATA 0x16ee
+#define mmDC_I2C_DDCVGA_HW_STATUS 0x16ef
+#define mmDC_I2C_DDCVGA_SPEED 0x16f0
+#define mmDC_I2C_DDCVGA_SETUP 0x16f1
+#define mmDC_I2C_EDID_DETECT_CTRL 0x16f2
+#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x16f3
+#define mmGENERIC_I2C_CONTROL 0x16f4
+#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x16f5
+#define mmGENERIC_I2C_STATUS 0x16f6
+#define mmGENERIC_I2C_SPEED 0x16f7
+#define mmGENERIC_I2C_SETUP 0x16f8
+#define mmGENERIC_I2C_TRANSACTION 0x16f9
+#define mmGENERIC_I2C_DATA 0x16fa
+#define mmGENERIC_I2C_PIN_SELECTION 0x16fb
+#define mmGENERIC_I2C_PIN_DEBUG 0x16fc
+#define mmBLNDV_CONTROL 0x476d
+#define mmBLNDV_SM_CONTROL2 0x476e
+#define mmBLNDV_CONTROL2 0x476f
+#define mmBLNDV_UPDATE 0x4770
+#define mmBLNDV_UNDERFLOW_INTERRUPT 0x4771
+#define mmBLNDV_V_UPDATE_LOCK 0x4773
+#define mmBLNDV_REG_UPDATE_STATUS 0x4777
+#define mmBLNDV_DEBUG 0x4774
+#define mmBLNDV_TEST_DEBUG_INDEX 0x4775
+#define mmBLNDV_TEST_DEBUG_DATA 0x4776
+#define mmCRTCV_H_BLANK_EARLY_NUM 0x477d
+#define mmCRTCV_H_TOTAL 0x4780
+#define mmCRTCV_H_BLANK_START_END 0x4781
+#define mmCRTCV_H_SYNC_A 0x4782
+#define mmCRTCV_H_SYNC_A_CNTL 0x4783
+#define mmCRTCV_H_SYNC_B 0x4784
+#define mmCRTCV_H_SYNC_B_CNTL 0x4785
+#define mmCRTCV_VBI_END 0x4786
+#define mmCRTCV_V_TOTAL 0x4787
+#define mmCRTCV_V_TOTAL_MIN 0x4788
+#define mmCRTCV_V_TOTAL_MAX 0x4789
+#define mmCRTCV_V_TOTAL_CONTROL 0x478a
+#define mmCRTCV_V_TOTAL_INT_STATUS 0x478b
+#define mmCRTCV_VSYNC_NOM_INT_STATUS 0x478c
+#define mmCRTCV_V_BLANK_START_END 0x478d
+#define mmCRTCV_V_SYNC_A 0x478e
+#define mmCRTCV_V_SYNC_A_CNTL 0x478f
+#define mmCRTCV_V_SYNC_B 0x4790
+#define mmCRTCV_V_SYNC_B_CNTL 0x4791
+#define mmCRTCV_DTMTEST_CNTL 0x4792
+#define mmCRTCV_DTMTEST_STATUS_POSITION 0x4793
+#define mmCRTCV_TRIGA_CNTL 0x4794
+#define mmCRTCV_TRIGA_MANUAL_TRIG 0x4795
+#define mmCRTCV_TRIGB_CNTL 0x4796
+#define mmCRTCV_TRIGB_MANUAL_TRIG 0x4797
+#define mmCRTCV_FORCE_COUNT_NOW_CNTL 0x4798
+#define mmCRTCV_FLOW_CONTROL 0x4799
+#define mmCRTCV_STEREO_FORCE_NEXT_EYE 0x479a
+#define mmCRTCV_AVSYNC_COUNTER 0x479b
+#define mmCRTCV_CONTROL 0x479c
+#define mmCRTCV_BLANK_CONTROL 0x479d
+#define mmCRTCV_INTERLACE_CONTROL 0x479e
+#define mmCRTCV_INTERLACE_STATUS 0x479f
+#define mmCRTCV_FIELD_INDICATION_CONTROL 0x47a0
+#define mmCRTCV_PIXEL_DATA_READBACK0 0x47a1
+#define mmCRTCV_PIXEL_DATA_READBACK1 0x47a2
+#define mmCRTCV_STATUS 0x47a3
+#define mmCRTCV_STATUS_POSITION 0x47a4
+#define mmCRTCV_NOM_VERT_POSITION 0x47a5
+#define mmCRTCV_STATUS_FRAME_COUNT 0x47a6
+#define mmCRTCV_STATUS_VF_COUNT 0x47a7
+#define mmCRTCV_STATUS_HV_COUNT 0x47a8
+#define mmCRTCV_COUNT_CONTROL 0x47a9
+#define mmCRTCV_COUNT_RESET 0x47aa
+#define mmCRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47ab
+#define mmCRTCV_VERT_SYNC_CONTROL 0x47ac
+#define mmCRTCV_STEREO_STATUS 0x47ad
+#define mmCRTCV_STEREO_CONTROL 0x47ae
+#define mmCRTCV_SNAPSHOT_STATUS 0x47af
+#define mmCRTCV_SNAPSHOT_CONTROL 0x47b0
+#define mmCRTCV_SNAPSHOT_POSITION 0x47b1
+#define mmCRTCV_SNAPSHOT_FRAME 0x47b2
+#define mmCRTCV_START_LINE_CONTROL 0x47b3
+#define mmCRTCV_INTERRUPT_CONTROL 0x47b4
+#define mmCRTCV_UPDATE_LOCK 0x47b5
+#define mmCRTCV_DOUBLE_BUFFER_CONTROL 0x47b6
+#define mmCRTCV_VGA_PARAMETER_CAPTURE_MODE 0x47b7
+#define mmCRTCV_TEST_PATTERN_CONTROL 0x47ba
+#define mmCRTCV_TEST_PATTERN_PARAMETERS 0x47bb
+#define mmCRTCV_TEST_PATTERN_COLOR 0x47bc
+#define mmCRTCV_MASTER_UPDATE_LOCK 0x47bd
+#define mmCRTCV_MASTER_UPDATE_MODE 0x47be
+#define mmCRTCV_MVP_INBAND_CNTL_INSERT 0x47bf
+#define mmCRTCV_MVP_INBAND_CNTL_INSERT_TIMER 0x47c0
+#define mmCRTCV_MVP_STATUS 0x47c1
+#define mmCRTCV_MASTER_EN 0x47c2
+#define mmCRTCV_ALLOW_STOP_OFF_V_CNT 0x47c3
+#define mmCRTCV_V_UPDATE_INT_STATUS 0x47c4
+#define mmCRTCV_OVERSCAN_COLOR 0x47c8
+#define mmCRTCV_OVERSCAN_COLOR_EXT 0x47c9
+#define mmCRTCV_BLANK_DATA_COLOR 0x47ca
+#define mmCRTCV_BLANK_DATA_COLOR_EXT 0x47cb
+#define mmCRTCV_BLACK_COLOR 0x47cc
+#define mmCRTCV_BLACK_COLOR_EXT 0x47cd
+#define mmCRTCV_VERTICAL_INTERRUPT0_POSITION 0x47ce
+#define mmCRTCV_VERTICAL_INTERRUPT0_CONTROL 0x47cf
+#define mmCRTCV_VERTICAL_INTERRUPT1_POSITION 0x47d0
+#define mmCRTCV_VERTICAL_INTERRUPT1_CONTROL 0x47d1
+#define mmCRTCV_VERTICAL_INTERRUPT2_POSITION 0x47d2
+#define mmCRTCV_VERTICAL_INTERRUPT2_CONTROL 0x47d3
+#define mmCRTCV_CRC_CNTL 0x47d4
+#define mmCRTCV_CRC0_WINDOWA_X_CONTROL 0x47d5
+#define mmCRTCV_CRC0_WINDOWA_Y_CONTROL 0x47d6
+#define mmCRTCV_CRC0_WINDOWB_X_CONTROL 0x47d7
+#define mmCRTCV_CRC0_WINDOWB_Y_CONTROL 0x47d8
+#define mmCRTCV_CRC0_DATA_RG 0x47d9
+#define mmCRTCV_CRC0_DATA_B 0x47da
+#define mmCRTCV_CRC1_WINDOWA_X_CONTROL 0x47db
+#define mmCRTCV_CRC1_WINDOWA_Y_CONTROL 0x47dc
+#define mmCRTCV_CRC1_WINDOWB_X_CONTROL 0x47dd
+#define mmCRTCV_CRC1_WINDOWB_Y_CONTROL 0x47de
+#define mmCRTCV_CRC1_DATA_RG 0x47df
+#define mmCRTCV_CRC1_DATA_B 0x47e0
+#define mmCRTCV_STATIC_SCREEN_CONTROL 0x47e7
+#define mmCRTCV_3D_STRUCTURE_CONTROL 0x4778
+#define mmCRTCV_GSL_VSYNC_GAP 0x4779
+#define mmCRTCV_GSL_WINDOW 0x477a
+#define mmCRTCV_GSL_CONTROL 0x477b
+#define mmCRTCV_TEST_DEBUG_INDEX 0x47c6
+#define mmCRTCV_TEST_DEBUG_DATA 0x47c7
+#define mmXDMA_MC_PCIE_CLIENT_CONFIG 0x3e0
+#define mmXDMA_LOCAL_SURFACE_TILING1 0x3e1
+#define mmXDMA_LOCAL_SURFACE_TILING2 0x3e2
+#define mmXDMA_INTERRUPT 0x3e3
+#define mmXDMA_CLOCK_GATING_CNTL 0x3e4
+#define mmXDMA_MEM_POWER_CNTL 0x3e6
+#define mmXDMA_IF_BIF_STATUS 0x3e7
+#define mmXDMA_PERF_MEAS_STATUS 0x3e8
+#define mmXDMA_IF_STATUS 0x3e9
+#define mmXDMA_TEST_DEBUG_INDEX 0x3ea
+#define mmXDMA_TEST_DEBUG_DATA 0x3eb
+#define mmXDMA_RBBMIF_RDWR_CNTL 0x3f8
+#define mmXDMA_PG_CONTROL 0x3f9
+#define mmXDMA_PG_WDATA 0x3fa
+#define mmXDMA_PG_STATUS 0x3fb
+#define mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc
+#define mmXDMA_AON_TEST_DEBUG_DATA 0x3fd
+#define mmXDMA_MSTR_CNTL 0x3ec
+#define mmXDMA_MSTR_STATUS 0x3ed
+#define mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x3ee
+#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x3ef
+#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x3f0
+#define mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x3f1
+#define mmXDMA_MSTR_CMD_URGENT_CNTL 0x3f2
+#define mmXDMA_MSTR_MEM_URGENT_CNTL 0x3f3
+#define mmXDMA_MSTR_PCIE_NACK_STATUS 0x3f5
+#define mmXDMA_MSTR_MEM_NACK_STATUS 0x3f6
+#define mmXDMA_MSTR_VSYNC_GSL_CHECK 0x3f7
+#define mmXDMA_MSTR_PIPE_CNTL 0x400
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL 0x400
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL 0x410
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL 0x420
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL 0x430
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL 0x440
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL 0x450
+#define mmXDMA_MSTR_READ_COMMAND 0x401
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND 0x401
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND 0x411
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND 0x421
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND 0x431
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND 0x441
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND 0x451
+#define mmXDMA_MSTR_CHANNEL_DIM 0x402
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM 0x402
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM 0x412
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM 0x422
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM 0x432
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM 0x442
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM 0x452
+#define mmXDMA_MSTR_HEIGHT 0x403
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT 0x403
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT 0x413
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT 0x423
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT 0x433
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT 0x443
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT 0x453
+#define mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x404
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE 0x404
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE 0x414
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE 0x424
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE 0x434
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE 0x444
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE 0x454
+#define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x415
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x425
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x435
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x445
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x455
+#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x406
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x406
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x416
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x426
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x436
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x446
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x456
+#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x417
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x427
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x437
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x447
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x457
+#define mmXDMA_MSTR_CACHE_BASE_ADDR 0x408
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR 0x408
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR 0x418
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR 0x428
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR 0x438
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR 0x448
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR 0x458
+#define mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x419
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x429
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x439
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x449
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x459
+#define mmXDMA_MSTR_CACHE 0x40a
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE 0x40a
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE 0x41a
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE 0x42a
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE 0x43a
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE 0x44a
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE 0x45a
+#define mmXDMA_MSTR_CHANNEL_START 0x40b
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START 0x40b
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START 0x41b
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START 0x42b
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START 0x43b
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START 0x44b
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START 0x45b
+#define mmXDMA_MSTR_PERFMEAS_STATUS 0x40e
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS 0x40e
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS 0x41e
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS 0x42e
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS 0x43e
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS 0x44e
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS 0x45e
+#define mmXDMA_MSTR_PERFMEAS_CNTL 0x40f
+#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL 0x40f
+#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL 0x41f
+#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL 0x42f
+#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL 0x43f
+#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL 0x44f
+#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL 0x45f
+#define mmXDMA_SLV_CNTL 0x460
+#define mmXDMA_SLV_MEM_CLIENT_CONFIG 0x461
+#define mmXDMA_SLV_SLS_PITCH 0x462
+#define mmXDMA_SLV_READ_URGENT_CNTL 0x463
+#define mmXDMA_SLV_WRITE_URGENT_CNTL 0x464
+#define mmXDMA_SLV_WB_RATE_CNTL 0x465
+#define mmXDMA_SLV_READ_LATENCY_MINMAX 0x466
+#define mmXDMA_SLV_READ_LATENCY_AVE 0x467
+#define mmXDMA_SLV_PCIE_NACK_STATUS 0x468
+#define mmXDMA_SLV_MEM_NACK_STATUS 0x469
+#define mmXDMA_SLV_RDRET_BUF_STATUS 0x46a
+#define mmXDMA_SLV_READ_LATENCY_TIMER 0x46b
+#define mmXDMA_SLV_FLIP_PENDING 0x46c
+#define mmXDMA_SLV_CHANNEL_CNTL 0x470
+#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL 0x470
+#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL 0x478
+#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL 0x480
+#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL 0x488
+#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL 0x490
+#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL 0x498
+#define mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x471
+#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS 0x471
+#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS 0x479
+#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS 0x481
+#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS 0x489
+#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS 0x491
+#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS 0x499
+#define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472
+#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472
+#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x47a
+#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x482
+#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x48a
+#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x492
+#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x49a
+
+#endif /* DCE_11_0_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h
new file mode 100644
index 000000000000..d74bca76e261
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h
@@ -0,0 +1,6129 @@
+/*
+ * DCE_11_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef DCE_11_0_ENUM_H
+#define DCE_11_0_ENUM_H
+
+typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL {
+ CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x0,
+ CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x1,
+} CRTC_CONTROL_CRTC_START_POINT_CNTL;
+typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL {
+ CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x0,
+ CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x1,
+} CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL;
+typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL {
+ CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0x0,
+ CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT= 0x1,
+ CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 0x2,
+ CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST= 0x3,
+} CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL;
+typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY {
+ CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE = 0x0,
+ CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 0x1,
+} CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY;
+typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE {
+ CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE= 0x0,
+ CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 0x1,
+} CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE;
+typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN {
+ CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE = 0x0,
+ CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE = 0x1,
+} CRTC_CONTROL_CRTC_SOF_PULL_EN;
+typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL {
+ CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE = 0x0,
+ CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE = 0x1,
+} CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL;
+typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL {
+ CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE = 0x0,
+ CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE = 0x1,
+} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL;
+typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL {
+ CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE = 0x0,
+ CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE = 0x1,
+} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL;
+typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN {
+ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE= 0x0,
+ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE= 0x1,
+} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN;
+typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC {
+ CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE= 0x0,
+ CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE= 0x1,
+} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC;
+typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT {
+ CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE= 0x0,
+ CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE= 0x1,
+} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT;
+typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK {
+ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_FRAME_START= 0x0,
+ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_A= 0x1,
+ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_B= 0x2,
+ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CURSOR_CHANGE= 0x3,
+ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_OTHER_CLIENT= 0x4,
+ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION0= 0x5,
+ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION1= 0x6,
+ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION2= 0x7,
+ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION3= 0x8,
+ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_GRAPHIC_UPDATE_PENDING= 0x9,
+ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED2= 0xa,
+ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_INVALID= 0xb,
+ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_DOUBLE_BUFFER= 0xc,
+ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT_NOM= 0xd,
+ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT= 0xe,
+ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED= 0xf,
+} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK;
+typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
+ CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE= 0x0,
+ CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE= 0x1,
+} CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK;
+typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR {
+ CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE= 0x0,
+ CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE= 0x1,
+} CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR;
+typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL {
+ CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE = 0x0,
+ CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE = 0x1,
+} CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL;
+typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN {
+ CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE = 0x0,
+ CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE = 0x1,
+} CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN;
+typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT {
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER= 0x1,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER= 0x2,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF= 0x5,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE= 0x6,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA = 0x7,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA = 0x8,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB = 0x9,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB = 0xa,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1 = 0xb,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2 = 0xc,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD= 0xd,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC= 0xe,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VIDEO = 0xf,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0 = 0x10,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1 = 0x11,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2 = 0x12,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON = 0x13,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA= 0x14,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB= 0x15,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW= 0x16,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW= 0x17,
+} CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT;
+typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT {
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE= 0x1,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA= 0x2,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB= 0x3,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA= 0x4,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB= 0x5,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO = 0x6,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC= 0x7,
+} CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT;
+typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN {
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE= 0x0,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x1,
+} CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN;
+typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR {
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE = 0x0,
+ CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE = 0x1,
+} CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR;
+typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT {
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER= 0x1,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER= 0x2,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF= 0x5,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE= 0x6,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA = 0x7,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA = 0x8,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB = 0x9,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB = 0xa,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1 = 0xb,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2 = 0xc,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD= 0xd,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC= 0xe,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VIDEO = 0xf,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0 = 0x10,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1 = 0x11,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2 = 0x12,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON = 0x13,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA= 0x14,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB= 0x15,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW= 0x16,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW= 0x17,
+} CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT;
+typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT {
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE= 0x1,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA= 0x2,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB= 0x3,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA= 0x4,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB= 0x5,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO = 0x6,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC= 0x7,
+} CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT;
+typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN {
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE= 0x0,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x1,
+} CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN;
+typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR {
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE = 0x0,
+ CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE = 0x1,
+} CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR;
+typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE {
+ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE= 0x0,
+ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT= 0x1,
+ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT= 0x2,
+ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED= 0x3,
+} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE;
+typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK {
+ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE= 0x0,
+ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE= 0x1,
+} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK;
+typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL {
+ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE= 0x0,
+ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE= 0x1,
+} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL;
+typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR {
+ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE= 0x0,
+ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE= 0x1,
+} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR;
+typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT {
+ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0= 0x0,
+ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF= 0x1,
+ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE= 0x2,
+ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1= 0x3,
+ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2= 0x4,
+ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA= 0x5,
+ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK= 0x6,
+ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA= 0x7,
+ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK= 0x8,
+ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK= 0x9,
+ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL= 0xa,
+ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1= 0xb,
+ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB= 0xc,
+ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA= 0xd,
+ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD= 0xe,
+ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC= 0xf,
+ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GPIO= 0x10,
+} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT;
+typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY {
+ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE= 0x0,
+ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE= 0x1,
+} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY;
+typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY {
+ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE= 0x0,
+ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE= 0x1,
+} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY;
+typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE {
+ CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO= 0x0,
+ CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT= 0x1,
+ CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT= 0x2,
+ CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED= 0x3,
+} CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE;
+typedef enum CRTC_CONTROL_CRTC_MASTER_EN {
+ CRTC_CONTROL_CRTC_MASTER_EN_FALSE = 0x0,
+ CRTC_CONTROL_CRTC_MASTER_EN_TRUE = 0x1,
+} CRTC_CONTROL_CRTC_MASTER_EN;
+typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN {
+ CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE = 0x0,
+ CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE = 0x1,
+} CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN;
+typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE {
+ CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE = 0x0,
+ CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE = 0x1,
+} CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE;
+typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE {
+ CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE= 0x0,
+ CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE= 0x1,
+} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE;
+typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD {
+ CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT= 0x0,
+ CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD= 0x1,
+ CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN= 0x2,
+ CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2= 0x3,
+} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD;
+typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY {
+ CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE= 0x0,
+ CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE= 0x1,
+} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY;
+typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT {
+ CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE= 0x0,
+ CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE= 0x1,
+} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT;
+typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN {
+ CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE = 0x0,
+ CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE = 0x1,
+} CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN;
+typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE {
+ CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE= 0x0,
+ CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE= 0x1,
+} CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE;
+typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR {
+ CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE= 0x0,
+ CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE= 0x1,
+} CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR;
+typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE {
+ CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE= 0x0,
+ CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA= 0x1,
+ CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB= 0x2,
+ CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED= 0x3,
+} CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE;
+typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY {
+ CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE= 0x0,
+ CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE= 0x1,
+} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY;
+typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY {
+ CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE= 0x0,
+ CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE= 0x1,
+} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY;
+typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY {
+ CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE= 0x0,
+ CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE= 0x1,
+} CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY;
+typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN {
+ CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE = 0x0,
+ CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE = 0x1,
+} CRTC_STEREO_CONTROL_CRTC_STEREO_EN;
+typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR {
+ CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE = 0x0,
+ CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE = 0x1,
+} CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR;
+typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL {
+ CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE= 0x0,
+ CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA= 0x1,
+ CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB= 0x2,
+ CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED= 0x3,
+} CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL;
+typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY {
+ CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE= 0x0,
+ CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE= 0x1,
+} CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY;
+typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY {
+ CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE= 0x0,
+ CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE= 0x1,
+} CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY;
+typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN {
+ CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE= 0x0,
+ CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE= 0x1,
+} CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN;
+typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN {
+ CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE = 0x0,
+ CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE = 0x1,
+} CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN;
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK {
+ CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE= 0x0,
+ CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE= 0x1,
+} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK;
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE {
+ CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE= 0x0,
+ CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE= 0x1,
+} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE;
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK {
+ CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE= 0x0,
+ CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE= 0x1,
+} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK;
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE {
+ CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE= 0x0,
+ CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE= 0x1,
+} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE;
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK {
+ CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE= 0x0,
+ CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE= 0x1,
+} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK;
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE {
+ CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE= 0x0,
+ CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE= 0x1,
+} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE;
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK {
+ CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE= 0x0,
+ CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE= 0x1,
+} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK;
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
+ CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE= 0x0,
+ CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE= 0x1,
+} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK {
+ CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE = 0x0,
+ CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE = 0x1,
+} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK;
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE {
+ CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE = 0x0,
+ CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE = 0x1,
+} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE;
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK {
+ CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE = 0x0,
+ CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE = 0x1,
+} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK;
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE {
+ CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE = 0x0,
+ CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE = 0x1,
+} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE;
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK {
+ CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE= 0x0,
+ CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE= 0x1,
+} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK;
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE {
+ CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE= 0x0,
+ CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE= 0x1,
+} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE;
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK {
+ CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE= 0x0,
+ CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE= 0x1,
+} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK;
+typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE {
+ CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE= 0x0,
+ CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE= 0x1,
+} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE;
+typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK {
+ CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE = 0x0,
+ CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE = 0x1,
+} CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK;
+typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY {
+ CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE= 0x0,
+ CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE= 0x1,
+} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY;
+typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN {
+ CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE= 0x0,
+ CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE= 0x1,
+} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN;
+typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE {
+ CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE= 0x0,
+ CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE= 0x1,
+} CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE;
+typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN {
+ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE= 0x0,
+ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE= 0x1,
+} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN;
+typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE {
+ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB= 0x0,
+ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601= 0x1,
+ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709= 0x2,
+ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS= 0x3,
+ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS= 0x4,
+ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB= 0x5,
+ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB= 0x6,
+ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS= 0x7,
+} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE;
+typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE {
+ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE= 0x0,
+ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE= 0x1,
+} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE;
+typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT {
+ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC= 0x0,
+ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC= 0x1,
+ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC= 0x2,
+ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED= 0x3,
+} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT;
+typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
+ MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x0,
+ MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x1,
+} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
+typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK {
+ MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE= 0x0,
+ MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE= 0x1,
+} MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK;
+typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
+ MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0x0,
+ MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 0x1,
+} MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK;
+typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE {
+ MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN = 0x0,
+ MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA = 0x1,
+ MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA = 0x2,
+ MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE = 0x3,
+} MASTER_UPDATE_MODE_MASTER_UPDATE_MODE;
+typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
+ MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH= 0x0,
+ MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN= 0x1,
+ MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD= 0x2,
+ MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED= 0x3,
+} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
+typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE {
+ CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE= 0x0,
+ CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG= 0x1,
+ CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL= 0x2,
+} CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE;
+typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR {
+ CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE = 0x0,
+ CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE = 0x1,
+} CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR;
+typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {
+ CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE= 0x0,
+ CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE= 0x1,
+} CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR;
+typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR {
+ CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE= 0x0,
+ CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE= 0x1,
+} CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR;
+typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
+ CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE= 0x0,
+ CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE= 0x1,
+} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
+typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE {
+ CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE= 0x0,
+ CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE= 0x1,
+} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE;
+typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR {
+ CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE= 0x0,
+ CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE= 0x1,
+} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR;
+typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE {
+ CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE= 0x0,
+ CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE= 0x1,
+} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE;
+typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR {
+ CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE= 0x0,
+ CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE= 0x1,
+} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR;
+typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE {
+ CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE= 0x0,
+ CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE= 0x1,
+} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE;
+typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE {
+ CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE= 0x0,
+ CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE= 0x1,
+} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE;
+typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR {
+ CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE= 0x0,
+ CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE= 0x1,
+} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR;
+typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE {
+ CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE= 0x0,
+ CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE= 0x1,
+} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE;
+typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE {
+ CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE= 0x0,
+ CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE= 0x1,
+} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE;
+typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN {
+ CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE = 0x0,
+ CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE = 0x1,
+} CRTC_CRC_CNTL_CRTC_CRC_EN;
+typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN {
+ CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE = 0x0,
+ CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE = 0x1,
+} CRTC_CRC_CNTL_CRTC_CRC_CONT_EN;
+typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE {
+ CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT = 0x0,
+ CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT = 0x1,
+ CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES = 0x2,
+ CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS = 0x3,
+} CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE;
+typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE {
+ CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP = 0x0,
+ CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM = 0x1,
+ CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM= 0x2,
+ CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD = 0x3,
+} CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE;
+typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS {
+ CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE= 0x0,
+ CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE= 0x1,
+} CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS;
+typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT {
+ CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB = 0x0,
+ CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B = 0x1,
+ CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB = 0x2,
+ CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B = 0x3,
+ CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB = 0x4,
+ CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B = 0x5,
+ CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB = 0x6,
+ CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B = 0x7,
+} CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT;
+typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT {
+ CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB = 0x0,
+ CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B = 0x1,
+ CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB = 0x2,
+ CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B = 0x3,
+ CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB = 0x4,
+ CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B = 0x5,
+ CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB = 0x6,
+ CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B = 0x7,
+} CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT;
+typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE {
+ CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE= 0x0,
+ CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE= 0x1,
+} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE;
+typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR {
+ CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE= 0x0,
+ CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE= 0x1,
+} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR;
+typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE {
+ CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE= 0x0,
+ CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE= 0x1,
+} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE;
+typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN {
+ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE= 0x0,
+ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE= 0x1,
+} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN;
+typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB {
+ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE= 0x0,
+ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE= 0x1,
+} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB;
+typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE {
+ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH= 0x0,
+ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE= 0x1,
+ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE= 0x2,
+ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED= 0x3,
+} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE;
+typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR {
+ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE= 0x0,
+ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE= 0x1,
+} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR;
+typedef enum CRTC_V_SYNC_A_POL {
+ CRTC_V_SYNC_A_POL_HIGH = 0x0,
+ CRTC_V_SYNC_A_POL_LOW = 0x1,
+} CRTC_V_SYNC_A_POL;
+typedef enum CRTC_H_SYNC_A_POL {
+ CRTC_H_SYNC_A_POL_HIGH = 0x0,
+ CRTC_H_SYNC_A_POL_LOW = 0x1,
+} CRTC_H_SYNC_A_POL;
+typedef enum CRTC_HORZ_REPETITION_COUNT {
+ CRTC_HORZ_REPETITION_COUNT_0 = 0x0,
+ CRTC_HORZ_REPETITION_COUNT_1 = 0x1,
+ CRTC_HORZ_REPETITION_COUNT_2 = 0x2,
+ CRTC_HORZ_REPETITION_COUNT_3 = 0x3,
+ CRTC_HORZ_REPETITION_COUNT_4 = 0x4,
+ CRTC_HORZ_REPETITION_COUNT_5 = 0x5,
+ CRTC_HORZ_REPETITION_COUNT_6 = 0x6,
+ CRTC_HORZ_REPETITION_COUNT_7 = 0x7,
+ CRTC_HORZ_REPETITION_COUNT_8 = 0x8,
+ CRTC_HORZ_REPETITION_COUNT_9 = 0x9,
+ CRTC_HORZ_REPETITION_COUNT_10 = 0xa,
+ CRTC_HORZ_REPETITION_COUNT_11 = 0xb,
+ CRTC_HORZ_REPETITION_COUNT_12 = 0xc,
+ CRTC_HORZ_REPETITION_COUNT_13 = 0xd,
+ CRTC_HORZ_REPETITION_COUNT_14 = 0xe,
+ CRTC_HORZ_REPETITION_COUNT_15 = 0xf,
+} CRTC_HORZ_REPETITION_COUNT;
+typedef enum PERFCOUNTER_CVALUE_SEL {
+ PERFCOUNTER_CVALUE_SEL_47_0 = 0x0,
+ PERFCOUNTER_CVALUE_SEL_15_0 = 0x1,
+ PERFCOUNTER_CVALUE_SEL_31_16 = 0x2,
+ PERFCOUNTER_CVALUE_SEL_47_32 = 0x3,
+ PERFCOUNTER_CVALUE_SEL_11_0 = 0x4,
+ PERFCOUNTER_CVALUE_SEL_23_12 = 0x5,
+ PERFCOUNTER_CVALUE_SEL_35_24 = 0x6,
+ PERFCOUNTER_CVALUE_SEL_47_36 = 0x7,
+} PERFCOUNTER_CVALUE_SEL;
+typedef enum PERFCOUNTER_INC_MODE {
+ PERFCOUNTER_INC_MODE_MULTI_BIT = 0x0,
+ PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x1,
+ PERFCOUNTER_INC_MODE_LSB = 0x2,
+ PERFCOUNTER_INC_MODE_POS_EDGE = 0x3,
+} PERFCOUNTER_INC_MODE;
+typedef enum PERFCOUNTER_HW_CNTL_SEL {
+ PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x0,
+ PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x1,
+} PERFCOUNTER_HW_CNTL_SEL;
+typedef enum PERFCOUNTER_RUNEN_MODE {
+ PERFCOUNTER_RUNEN_MODE_LEVEL = 0x0,
+ PERFCOUNTER_RUNEN_MODE_EDGE = 0x1,
+} PERFCOUNTER_RUNEN_MODE;
+typedef enum PERFCOUNTER_CNTOFF_START_DIS {
+ PERFCOUNTER_CNTOFF_START_ENABLE = 0x0,
+ PERFCOUNTER_CNTOFF_START_DISABLE = 0x1,
+} PERFCOUNTER_CNTOFF_START_DIS;
+typedef enum PERFCOUNTER_RESTART_EN {
+ PERFCOUNTER_RESTART_DISABLE = 0x0,
+ PERFCOUNTER_RESTART_ENABLE = 0x1,
+} PERFCOUNTER_RESTART_EN;
+typedef enum PERFCOUNTER_INT_EN {
+ PERFCOUNTER_INT_DISABLE = 0x0,
+ PERFCOUNTER_INT_ENABLE = 0x1,
+} PERFCOUNTER_INT_EN;
+typedef enum PERFCOUNTER_OFF_MASK {
+ PERFCOUNTER_OFF_MASK_DISABLE = 0x0,
+ PERFCOUNTER_OFF_MASK_ENABLE = 0x1,
+} PERFCOUNTER_OFF_MASK;
+typedef enum PERFCOUNTER_ACTIVE {
+ PERFCOUNTER_IS_IDLE = 0x0,
+ PERFCOUNTER_IS_ACTIVE = 0x1,
+} PERFCOUNTER_ACTIVE;
+typedef enum PERFCOUNTER_INT_TYPE {
+ PERFCOUNTER_INT_TYPE_LEVEL = 0x0,
+ PERFCOUNTER_INT_TYPE_PULSE = 0x1,
+} PERFCOUNTER_INT_TYPE;
+typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
+ PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x0,
+ PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x1,
+} PERFCOUNTER_COUNTED_VALUE_TYPE;
+typedef enum PERFCOUNTER_CNTL_SEL {
+ PERFCOUNTER_CNTL_SEL_0 = 0x0,
+ PERFCOUNTER_CNTL_SEL_1 = 0x1,
+ PERFCOUNTER_CNTL_SEL_2 = 0x2,
+ PERFCOUNTER_CNTL_SEL_3 = 0x3,
+ PERFCOUNTER_CNTL_SEL_4 = 0x4,
+ PERFCOUNTER_CNTL_SEL_5 = 0x5,
+ PERFCOUNTER_CNTL_SEL_6 = 0x6,
+ PERFCOUNTER_CNTL_SEL_7 = 0x7,
+} PERFCOUNTER_CNTL_SEL;
+typedef enum PERFCOUNTER_CNT0_STATE {
+ PERFCOUNTER_CNT0_STATE_RESET = 0x0,
+ PERFCOUNTER_CNT0_STATE_START = 0x1,
+ PERFCOUNTER_CNT0_STATE_FREEZE = 0x2,
+ PERFCOUNTER_CNT0_STATE_HW = 0x3,
+} PERFCOUNTER_CNT0_STATE;
+typedef enum PERFCOUNTER_STATE_SEL0 {
+ PERFCOUNTER_STATE_SEL0_GLOBAL = 0x0,
+ PERFCOUNTER_STATE_SEL0_LOCAL = 0x1,
+} PERFCOUNTER_STATE_SEL0;
+typedef enum PERFCOUNTER_CNT1_STATE {
+ PERFCOUNTER_CNT1_STATE_RESET = 0x0,
+ PERFCOUNTER_CNT1_STATE_START = 0x1,
+ PERFCOUNTER_CNT1_STATE_FREEZE = 0x2,
+ PERFCOUNTER_CNT1_STATE_HW = 0x3,
+} PERFCOUNTER_CNT1_STATE;
+typedef enum PERFCOUNTER_STATE_SEL1 {
+ PERFCOUNTER_STATE_SEL1_GLOBAL = 0x0,
+ PERFCOUNTER_STATE_SEL1_LOCAL = 0x1,
+} PERFCOUNTER_STATE_SEL1;
+typedef enum PERFCOUNTER_CNT2_STATE {
+ PERFCOUNTER_CNT2_STATE_RESET = 0x0,
+ PERFCOUNTER_CNT2_STATE_START = 0x1,
+ PERFCOUNTER_CNT2_STATE_FREEZE = 0x2,
+ PERFCOUNTER_CNT2_STATE_HW = 0x3,
+} PERFCOUNTER_CNT2_STATE;
+typedef enum PERFCOUNTER_STATE_SEL2 {
+ PERFCOUNTER_STATE_SEL2_GLOBAL = 0x0,
+ PERFCOUNTER_STATE_SEL2_LOCAL = 0x1,
+} PERFCOUNTER_STATE_SEL2;
+typedef enum PERFCOUNTER_CNT3_STATE {
+ PERFCOUNTER_CNT3_STATE_RESET = 0x0,
+ PERFCOUNTER_CNT3_STATE_START = 0x1,
+ PERFCOUNTER_CNT3_STATE_FREEZE = 0x2,
+ PERFCOUNTER_CNT3_STATE_HW = 0x3,
+} PERFCOUNTER_CNT3_STATE;
+typedef enum PERFCOUNTER_STATE_SEL3 {
+ PERFCOUNTER_STATE_SEL3_GLOBAL = 0x0,
+ PERFCOUNTER_STATE_SEL3_LOCAL = 0x1,
+} PERFCOUNTER_STATE_SEL3;
+typedef enum PERFCOUNTER_CNT4_STATE {
+ PERFCOUNTER_CNT4_STATE_RESET = 0x0,
+ PERFCOUNTER_CNT4_STATE_START = 0x1,
+ PERFCOUNTER_CNT4_STATE_FREEZE = 0x2,
+ PERFCOUNTER_CNT4_STATE_HW = 0x3,
+} PERFCOUNTER_CNT4_STATE;
+typedef enum PERFCOUNTER_STATE_SEL4 {
+ PERFCOUNTER_STATE_SEL4_GLOBAL = 0x0,
+ PERFCOUNTER_STATE_SEL4_LOCAL = 0x1,
+} PERFCOUNTER_STATE_SEL4;
+typedef enum PERFCOUNTER_CNT5_STATE {
+ PERFCOUNTER_CNT5_STATE_RESET = 0x0,
+ PERFCOUNTER_CNT5_STATE_START = 0x1,
+ PERFCOUNTER_CNT5_STATE_FREEZE = 0x2,
+ PERFCOUNTER_CNT5_STATE_HW = 0x3,
+} PERFCOUNTER_CNT5_STATE;
+typedef enum PERFCOUNTER_STATE_SEL5 {
+ PERFCOUNTER_STATE_SEL5_GLOBAL = 0x0,
+ PERFCOUNTER_STATE_SEL5_LOCAL = 0x1,
+} PERFCOUNTER_STATE_SEL5;
+typedef enum PERFCOUNTER_CNT6_STATE {
+ PERFCOUNTER_CNT6_STATE_RESET = 0x0,
+ PERFCOUNTER_CNT6_STATE_START = 0x1,
+ PERFCOUNTER_CNT6_STATE_FREEZE = 0x2,
+ PERFCOUNTER_CNT6_STATE_HW = 0x3,
+} PERFCOUNTER_CNT6_STATE;
+typedef enum PERFCOUNTER_STATE_SEL6 {
+ PERFCOUNTER_STATE_SEL6_GLOBAL = 0x0,
+ PERFCOUNTER_STATE_SEL6_LOCAL = 0x1,
+} PERFCOUNTER_STATE_SEL6;
+typedef enum PERFCOUNTER_CNT7_STATE {
+ PERFCOUNTER_CNT7_STATE_RESET = 0x0,
+ PERFCOUNTER_CNT7_STATE_START = 0x1,
+ PERFCOUNTER_CNT7_STATE_FREEZE = 0x2,
+ PERFCOUNTER_CNT7_STATE_HW = 0x3,
+} PERFCOUNTER_CNT7_STATE;
+typedef enum PERFCOUNTER_STATE_SEL7 {
+ PERFCOUNTER_STATE_SEL7_GLOBAL = 0x0,
+ PERFCOUNTER_STATE_SEL7_LOCAL = 0x1,
+} PERFCOUNTER_STATE_SEL7;
+typedef enum PERFMON_STATE {
+ PERFMON_STATE_RESET = 0x0,
+ PERFMON_STATE_START = 0x1,
+ PERFMON_STATE_FREEZE = 0x2,
+ PERFMON_STATE_HW = 0x3,
+} PERFMON_STATE;
+typedef enum PERFMON_CNTOFF_AND_OR {
+ PERFMON_CNTOFF_OR = 0x0,
+ PERFMON_CNTOFF_AND = 0x1,
+} PERFMON_CNTOFF_AND_OR;
+typedef enum PERFMON_CNTOFF_INT_EN {
+ PERFMON_CNTOFF_INT_DISABLE = 0x0,
+ PERFMON_CNTOFF_INT_ENABLE = 0x1,
+} PERFMON_CNTOFF_INT_EN;
+typedef enum PERFMON_CNTOFF_INT_TYPE {
+ PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x0,
+ PERFMON_CNTOFF_INT_TYPE_PULSE = 0x1,
+} PERFMON_CNTOFF_INT_TYPE;
+typedef enum LptNumBanks {
+ LPT_NUM_BANKS_2BANK = 0x0,
+ LPT_NUM_BANKS_4BANK = 0x1,
+ LPT_NUM_BANKS_8BANK = 0x2,
+ LPT_NUM_BANKS_16BANK = 0x3,
+ LPT_NUM_BANKS_32BANK = 0x4,
+} LptNumBanks;
+typedef enum DCIO_DC_GENERICA_SEL {
+ DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0x0,
+ DCIO_GENERICA_SEL_STEREOSYNC = 0x1,
+ DCIO_GENERICA_SEL_DACA_PIXCLK = 0x2,
+ DCIO_GENERICA_SEL_DACB_PIXCLK = 0x3,
+ DCIO_GENERICA_SEL_DVOA_CTL3 = 0x4,
+ DCIO_GENERICA_SEL_P1_PLLCLK = 0x5,
+ DCIO_GENERICA_SEL_P2_PLLCLK = 0x6,
+ DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 0x7,
+ DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 0x8,
+ DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 0x9,
+ DCIO_GENERICA_SEL_GENERICA_DCCG = 0xa,
+ DCIO_GENERICA_SEL_SYNCEN = 0xb,
+ DCIO_GENERICA_SEL_GENERICA_SCG = 0xc,
+ DCIO_GENERICA_SEL_RESERVED_VALUE13 = 0xd,
+ DCIO_GENERICA_SEL_RESERVED_VALUE14 = 0xe,
+ DCIO_GENERICA_SEL_RESERVED_VALUE15 = 0xf,
+ DCIO_GENERICA_SEL_GENERICA_DPRX = 0x10,
+ DCIO_GENERICA_SEL_GENERICB_DPRX = 0x11,
+} DCIO_DC_GENERICA_SEL;
+typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
+ DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x0,
+ DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x1,
+ DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x2,
+ DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x3,
+ DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x4,
+ DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x5,
+ DCIO_UNIPHYG_TEST_REFDIV_CLK = 0x6,
+ DCIO_UNIPHYLPA_TEST_REFDIV_CLK = 0x7,
+ DCIO_UNIPHYLPB_TEST_REFDIV_CLK = 0x8,
+} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
+typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
+ DCIO_UNIPHYA_FBDIV_CLK = 0x0,
+ DCIO_UNIPHYB_FBDIV_CLK = 0x1,
+ DCIO_UNIPHYC_FBDIV_CLK = 0x2,
+ DCIO_UNIPHYD_FBDIV_CLK = 0x3,
+ DCIO_UNIPHYE_FBDIV_CLK = 0x4,
+ DCIO_UNIPHYF_FBDIV_CLK = 0x5,
+ DCIO_UNIPHYG_FBDIV_CLK = 0x6,
+ DCIO_UNIPHYLPA_FBDIV_CLK = 0x7,
+ DCIO_UNIPHYLPB_FBDIV_CLK = 0x8,
+} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
+typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
+ DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x0,
+ DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x1,
+ DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x2,
+ DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x3,
+ DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x4,
+ DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x5,
+ DCIO_UNIPHYG_FBDIV_SSC_CLK = 0x6,
+ DCIO_UNIPHYLPA_FBDIV_SSC_CLK = 0x7,
+ DCIO_UNIPHYLPB_FBDIV_SSC_CLK = 0x8,
+} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
+typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
+ DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x0,
+ DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x1,
+ DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x2,
+ DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x3,
+ DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x4,
+ DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x5,
+ DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 0x6,
+ DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2 = 0x7,
+ DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2 = 0x8,
+} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
+typedef enum DCIO_DC_GENERICB_SEL {
+ DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0x0,
+ DCIO_GENERICB_SEL_STEREOSYNC = 0x1,
+ DCIO_GENERICB_SEL_DACA_PIXCLK = 0x2,
+ DCIO_GENERICB_SEL_DACB_PIXCLK = 0x3,
+ DCIO_GENERICB_SEL_DVOA_CTL3 = 0x4,
+ DCIO_GENERICB_SEL_P1_PLLCLK = 0x5,
+ DCIO_GENERICB_SEL_P2_PLLCLK = 0x6,
+ DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 0x7,
+ DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 0x8,
+ DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 0x9,
+ DCIO_GENERICB_SEL_GENERICB_DCCG = 0xa,
+ DCIO_GENERICB_SEL_SYNCEN = 0xb,
+ DCIO_GENERICB_SEL_GENERICA_SCG = 0xc,
+ DCIO_GENERICB_SEL_RESERVED_VALUE13 = 0xd,
+ DCIO_GENERICB_SEL_RESERVED_VALUE14 = 0xe,
+ DCIO_GENERICB_SEL_RESERVED_VALUE15 = 0xf,
+} DCIO_DC_GENERICB_SEL;
+typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL {
+ DCIO_DC_PAD_EXTERN_SIG_SEL_MVP = 0x0,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA = 0x1,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK = 0x2,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC = 0x3,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA = 0x4,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB = 0x5,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC = 0x6,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1 = 0x7,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2 = 0x8,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK = 0x9,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA = 0xa,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK = 0xb,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA = 0xc,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1 = 0xd,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0 = 0xe,
+ DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL = 0xf,
+} DCIO_DC_PAD_EXTERN_SIG_SEL;
+typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS {
+ DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA = 0x0,
+ DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE = 0x1,
+ DCIO_MVP_PIXEL_SRC_STATUS_CRTC = 0x2,
+ DCIO_MVP_PIXEL_SRC_STATUS_LB = 0x3,
+} DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS;
+typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
+ DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0x0,
+ DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 0x1,
+ DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x2,
+ DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 0x3,
+} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;
+typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
+ DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x0,
+ DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x1,
+ DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x2,
+ DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x3,
+} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
+typedef enum DCIO_DC_GPIO_VIP_DEBUG {
+ DCIO_DC_GPIO_VIP_DEBUG_NORMAL = 0x0,
+ DCIO_DC_GPIO_VIP_DEBUG_CG_BIG = 0x1,
+} DCIO_DC_GPIO_VIP_DEBUG;
+typedef enum DCIO_DC_GPIO_MACRO_DEBUG {
+ DCIO_DC_GPIO_MACRO_DEBUG_NORMAL = 0x0,
+ DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF = 0x1,
+ DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 0x2,
+ DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3 = 0x3,
+} DCIO_DC_GPIO_MACRO_DEBUG;
+typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL {
+ DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL = 0x0,
+ DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP = 0x1,
+} DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL;
+typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN {
+ DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS = 0x0,
+ DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE = 0x1,
+} DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN;
+typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
+ DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0x0,
+ DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 0x1,
+} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE;
+typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
+ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x0,
+ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x1,
+ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS= 0x2,
+ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS= 0x3,
+ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS= 0x4,
+ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS= 0x5,
+ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS= 0x6,
+ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS= 0x7,
+} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION;
+typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
+ DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x0,
+ DCIO_UNIPHY_CHANNEL_INVERTED = 0x1,
+} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
+typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
+ DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x0,
+ DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x1,
+ DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x2,
+ DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED= 0x3,
+} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
+typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
+ DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x0,
+ DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x1,
+ DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x2,
+ DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x3,
+} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
+typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
+ DCIO_VIP_MUX_EN_DVO = 0x0,
+ DCIO_VIP_MUX_EN_VIP = 0x1,
+} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN;
+typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
+ DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0x0,
+ DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 0x1,
+} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN;
+typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
+ DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0x0,
+ DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 0x1,
+} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN;
+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
+ DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE= 0x0,
+ DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE= 0x1,
+} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN;
+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
+ DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0x0,
+ DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 0x1,
+} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE;
+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
+ DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0x0,
+ DCIO_LVTMA_SYNCEN_POL_INVERT = 0x1,
+} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL;
+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
+ DCIO_LVTMA_DIGON_OFF = 0x0,
+ DCIO_LVTMA_DIGON_ON = 0x1,
+} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON;
+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
+ DCIO_LVTMA_DIGON_POL_NON_INVERT = 0x0,
+ DCIO_LVTMA_DIGON_POL_INVERT = 0x1,
+} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL;
+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
+ DCIO_LVTMA_BLON_OFF = 0x0,
+ DCIO_LVTMA_BLON_ON = 0x1,
+} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON;
+typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
+ DCIO_LVTMA_BLON_POL_NON_INVERT = 0x0,
+ DCIO_LVTMA_BLON_POL_INVERT = 0x1,
+} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL;
+typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
+ DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0x0,
+ DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 0x1,
+} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN;
+typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
+ DCIO_BL_PWM_FRACTIONAL_DISABLE = 0x0,
+ DCIO_BL_PWM_FRACTIONAL_ENABLE = 0x1,
+} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
+typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
+ DCIO_BL_PWM_DISABLE = 0x0,
+ DCIO_BL_PWM_ENABLE = 0x1,
+} DCIO_BL_PWM_CNTL_BL_PWM_EN;
+typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
+ DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x0,
+ DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x1,
+ DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x2,
+ DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x3,
+} DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT;
+typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
+ DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x0,
+ DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x1,
+} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
+typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
+ DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0x0,
+ DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 0x1,
+} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN;
+typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
+ DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x0,
+ DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x1,
+} DCIO_BL_PWM_GRP1_REG_LOCK;
+typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
+ DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x0,
+ DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x1,
+} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
+typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
+ DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1= 0x0,
+ DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2= 0x1,
+ DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3= 0x2,
+ DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4= 0x3,
+ DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5= 0x4,
+ DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6= 0x5,
+} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
+typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
+ DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x0,
+ DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM= 0x1,
+} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
+typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
+ DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x0,
+ DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x1,
+} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
+typedef enum DCIO_GSL_SEL {
+ DCIO_GSL_SEL_GROUP_0 = 0x0,
+ DCIO_GSL_SEL_GROUP_1 = 0x1,
+ DCIO_GSL_SEL_GROUP_2 = 0x2,
+} DCIO_GSL_SEL;
+typedef enum DCIO_GENLK_CLK_GSL_MASK {
+ DCIO_GENLK_CLK_GSL_MASK_NO = 0x0,
+ DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x1,
+ DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x2,
+} DCIO_GENLK_CLK_GSL_MASK;
+typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
+ DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x0,
+ DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x1,
+ DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x2,
+} DCIO_GENLK_VSYNC_GSL_MASK;
+typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
+ DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x0,
+ DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x1,
+ DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x2,
+} DCIO_SWAPLOCK_A_GSL_MASK;
+typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
+ DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x0,
+ DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x1,
+ DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x2,
+} DCIO_SWAPLOCK_B_GSL_MASK;
+typedef enum DCIO_GSL_VSYNC_SEL {
+ DCIO_GSL_VSYNC_SEL_PIPE0 = 0x0,
+ DCIO_GSL_VSYNC_SEL_PIPE1 = 0x1,
+ DCIO_GSL_VSYNC_SEL_PIPE2 = 0x2,
+ DCIO_GSL_VSYNC_SEL_PIPE3 = 0x3,
+ DCIO_GSL_VSYNC_SEL_PIPE4 = 0x4,
+ DCIO_GSL_VSYNC_SEL_PIPE5 = 0x5,
+} DCIO_GSL_VSYNC_SEL;
+typedef enum DCIO_GSL0_TIMING_SYNC_SEL {
+ DCIO_GSL0_TIMING_SYNC_SEL_PIPE = 0x0,
+ DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1,
+ DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
+ DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3,
+ DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4,
+} DCIO_GSL0_TIMING_SYNC_SEL;
+typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL {
+ DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION = 0x0,
+ DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1,
+ DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
+ DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3,
+ DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4,
+} DCIO_GSL0_GLOBAL_UNLOCK_SEL;
+typedef enum DCIO_GSL1_TIMING_SYNC_SEL {
+ DCIO_GSL1_TIMING_SYNC_SEL_PIPE = 0x0,
+ DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1,
+ DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
+ DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3,
+ DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4,
+} DCIO_GSL1_TIMING_SYNC_SEL;
+typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL {
+ DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION = 0x0,
+ DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1,
+ DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
+ DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3,
+ DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4,
+} DCIO_GSL1_GLOBAL_UNLOCK_SEL;
+typedef enum DCIO_GSL2_TIMING_SYNC_SEL {
+ DCIO_GSL2_TIMING_SYNC_SEL_PIPE = 0x0,
+ DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1,
+ DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
+ DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3,
+ DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4,
+} DCIO_GSL2_TIMING_SYNC_SEL;
+typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL {
+ DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION = 0x0,
+ DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1,
+ DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
+ DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3,
+ DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4,
+} DCIO_GSL2_GLOBAL_UNLOCK_SEL;
+typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
+ DCIO_GPU_TIMER_START_0_END_27 = 0x0,
+ DCIO_GPU_TIMER_START_1_END_28 = 0x1,
+ DCIO_GPU_TIMER_START_2_END_29 = 0x2,
+ DCIO_GPU_TIMER_START_3_END_30 = 0x3,
+ DCIO_GPU_TIMER_START_4_END_31 = 0x4,
+ DCIO_GPU_TIMER_START_6_END_33 = 0x5,
+ DCIO_GPU_TIMER_START_8_END_35 = 0x6,
+ DCIO_GPU_TIMER_START_10_END_37 = 0x7,
+} DCIO_DC_GPU_TIMER_START_POSITION;
+typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
+ DCIO_TEST_CLK_SEL_DISPCLK = 0x0,
+ DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x1,
+ DCIO_TEST_CLK_SEL_SCLK = 0x2,
+} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
+typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
+ DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x0,
+ DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x1,
+} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
+typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX {
+ DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x0,
+ DCIO_EXT_VSYNC_MUX_CRTC0 = 0x1,
+ DCIO_EXT_VSYNC_MUX_CRTC1 = 0x2,
+ DCIO_EXT_VSYNC_MUX_CRTC2 = 0x3,
+ DCIO_EXT_VSYNC_MUX_CRTC3 = 0x4,
+ DCIO_EXT_VSYNC_MUX_CRTC4 = 0x5,
+ DCIO_EXT_VSYNC_MUX_CRTC5 = 0x6,
+ DCIO_EXT_VSYNC_MUX_GENERICB = 0x7,
+} DCIO_DCO_DCFE_EXT_VSYNC_MUX;
+typedef enum DCIO_DCO_EXT_VSYNC_MASK {
+ DCIO_EXT_VSYNC_MASK_NONE = 0x0,
+ DCIO_EXT_VSYNC_MASK_PIPE0 = 0x1,
+ DCIO_EXT_VSYNC_MASK_PIPE1 = 0x2,
+ DCIO_EXT_VSYNC_MASK_PIPE2 = 0x3,
+ DCIO_EXT_VSYNC_MASK_PIPE3 = 0x4,
+ DCIO_EXT_VSYNC_MASK_PIPE4 = 0x5,
+ DCIO_EXT_VSYNC_MASK_PIPE5 = 0x6,
+ DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x7,
+} DCIO_DCO_EXT_VSYNC_MASK;
+typedef enum DCIO_DBG_OUT_PIN_SEL {
+ DCIO_DBG_OUT_PIN_SEL_LOW_12BIT = 0x0,
+ DCIO_DBG_OUT_PIN_SEL_HIGH_12BIT = 0x1,
+} DCIO_DBG_OUT_PIN_SEL;
+typedef enum DCIO_DBG_OUT_12BIT_SEL {
+ DCIO_DBG_OUT_12BIT_SEL_LOW_12BIT = 0x0,
+ DCIO_DBG_OUT_12BIT_SEL_MID_12BIT = 0x1,
+ DCIO_DBG_OUT_12BIT_SEL_HIGH_12BIT = 0x2,
+ DCIO_DBG_OUT_12BIT_SEL_OVERRIDE = 0x3,
+} DCIO_DBG_OUT_12BIT_SEL;
+typedef enum DCIO_DSYNC_SOFT_RESET {
+ DCIO_DSYNC_SOFT_RESET_DEASSERT = 0x0,
+ DCIO_DSYNC_SOFT_RESET_ASSERT = 0x1,
+} DCIO_DSYNC_SOFT_RESET;
+typedef enum DCIO_DACA_SOFT_RESET {
+ DCIO_DACA_SOFT_RESET_DEASSERT = 0x0,
+ DCIO_DACA_SOFT_RESET_ASSERT = 0x1,
+} DCIO_DACA_SOFT_RESET;
+typedef enum DCIO_DCRXPHY_SOFT_RESET {
+ DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x0,
+ DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x1,
+} DCIO_DCRXPHY_SOFT_RESET;
+typedef enum DCIO_DPHY_LANE_SEL {
+ DCIO_DPHY_LANE_SEL_LANE0 = 0x0,
+ DCIO_DPHY_LANE_SEL_LANE1 = 0x1,
+ DCIO_DPHY_LANE_SEL_LANE2 = 0x2,
+ DCIO_DPHY_LANE_SEL_LANE3 = 0x3,
+} DCIO_DPHY_LANE_SEL;
+typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x0,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x1,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 0x2,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE = 0x3,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 0x4,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE = 0x5,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0xc,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0xd,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP = 0xe,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP = 0xf,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP = 0x10,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP = 0x11,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x18,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x19,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM = 0x1a,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM = 0x1b,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM = 0x1c,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM = 0x1d,
+ DCIO_GPU_TIMER_READ_SELECT_LOWER_DCFEV_P_FLIP = 0x24,
+ DCIO_GPU_TIMER_READ_SELECT_UPPER_DCFEV_P_FLIP = 0x25,
+} DCIO_DC_GPU_TIMER_READ_SELECT;
+typedef enum DCIO_IMPCAL_STEP_DELAY {
+ DCIO_IMPCAL_STEP_DELAY_1us = 0x0,
+ DCIO_IMPCAL_STEP_DELAY_2us = 0x1,
+ DCIO_IMPCAL_STEP_DELAY_3us = 0x2,
+ DCIO_IMPCAL_STEP_DELAY_4us = 0x3,
+ DCIO_IMPCAL_STEP_DELAY_5us = 0x4,
+ DCIO_IMPCAL_STEP_DELAY_6us = 0x5,
+ DCIO_IMPCAL_STEP_DELAY_7us = 0x6,
+ DCIO_IMPCAL_STEP_DELAY_8us = 0x7,
+ DCIO_IMPCAL_STEP_DELAY_9us = 0x8,
+ DCIO_IMPCAL_STEP_DELAY_10us = 0x9,
+ DCIO_IMPCAL_STEP_DELAY_11us = 0xa,
+ DCIO_IMPCAL_STEP_DELAY_12us = 0xb,
+ DCIO_IMPCAL_STEP_DELAY_13us = 0xc,
+ DCIO_IMPCAL_STEP_DELAY_14us = 0xd,
+ DCIO_IMPCAL_STEP_DELAY_15us = 0xe,
+ DCIO_IMPCAL_STEP_DELAY_16us = 0xf,
+} DCIO_IMPCAL_STEP_DELAY;
+typedef enum DCIO_UNIPHY_IMPCAL_SEL {
+ DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x0,
+ DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x1,
+} DCIO_UNIPHY_IMPCAL_SEL;
+typedef enum DCIOCHIP_HPD_SEL {
+ DCIOCHIP_HPD_SEL_ASYNC = 0x0,
+ DCIOCHIP_HPD_SEL_CLOCKED = 0x1,
+} DCIOCHIP_HPD_SEL;
+typedef enum DCIOCHIP_PAD_MODE {
+ DCIOCHIP_PAD_MODE_DDC = 0x0,
+ DCIOCHIP_PAD_MODE_DP = 0x1,
+} DCIOCHIP_PAD_MODE;
+typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
+ DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0x0,
+ DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 0x1,
+} DCIOCHIP_AUXSLAVE_PAD_MODE;
+typedef enum DCIOCHIP_INVERT {
+ DCIOCHIP_POL_NON_INVERT = 0x0,
+ DCIOCHIP_POL_INVERT = 0x1,
+} DCIOCHIP_INVERT;
+typedef enum DCIOCHIP_PD_EN {
+ DCIOCHIP_PD_EN_NOTALLOW = 0x0,
+ DCIOCHIP_PD_EN_ALLOW = 0x1,
+} DCIOCHIP_PD_EN;
+typedef enum DCIOCHIP_GPIO_MASK_EN {
+ DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x0,
+ DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x1,
+} DCIOCHIP_GPIO_MASK_EN;
+typedef enum DCIOCHIP_MASK {
+ DCIOCHIP_MASK_DISABLE = 0x0,
+ DCIOCHIP_MASK_ENABLE = 0x1,
+} DCIOCHIP_MASK;
+typedef enum DCIOCHIP_GPIO_I2C_MASK {
+ DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0x0,
+ DCIOCHIP_GPIO_I2C_MASK_ENABLE = 0x1,
+} DCIOCHIP_GPIO_I2C_MASK;
+typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
+ DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0x0,
+ DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 0x1,
+} DCIOCHIP_GPIO_I2C_DRIVE;
+typedef enum DCIOCHIP_GPIO_I2C_EN {
+ DCIOCHIP_GPIO_I2C_DISABLE = 0x0,
+ DCIOCHIP_GPIO_I2C_ENABLE = 0x1,
+} DCIOCHIP_GPIO_I2C_EN;
+typedef enum DCIOCHIP_MASK_4BIT {
+ DCIOCHIP_MASK_4BIT_DISABLE = 0x0,
+ DCIOCHIP_MASK_4BIT_ENABLE = 0xf,
+} DCIOCHIP_MASK_4BIT;
+typedef enum DCIOCHIP_ENABLE_4BIT {
+ DCIOCHIP_4BIT_DISABLE = 0x0,
+ DCIOCHIP_4BIT_ENABLE = 0xf,
+} DCIOCHIP_ENABLE_4BIT;
+typedef enum DCIOCHIP_MASK_5BIT {
+ DCIOCHIP_MASIK_5BIT_DISABLE = 0x0,
+ DCIOCHIP_MASIK_5BIT_ENABLE = 0x1f,
+} DCIOCHIP_MASK_5BIT;
+typedef enum DCIOCHIP_ENABLE_5BIT {
+ DCIOCHIP_5BIT_DISABLE = 0x0,
+ DCIOCHIP_5BIT_ENABLE = 0x1f,
+} DCIOCHIP_ENABLE_5BIT;
+typedef enum DCIOCHIP_MASK_2BIT {
+ DCIOCHIP_MASK_2BIT_DISABLE = 0x0,
+ DCIOCHIP_MASK_2BIT_ENABLE = 0x3,
+} DCIOCHIP_MASK_2BIT;
+typedef enum DCIOCHIP_ENABLE_2BIT {
+ DCIOCHIP_2BIT_DISABLE = 0x0,
+ DCIOCHIP_2BIT_ENABLE = 0x3,
+} DCIOCHIP_ENABLE_2BIT;
+typedef enum DCIOCHIP_REF_27_SRC_SEL {
+ DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x0,
+ DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x1,
+ DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x2,
+ DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x3,
+} DCIOCHIP_REF_27_SRC_SEL;
+typedef enum DCIOCHIP_DVO_VREFPON {
+ DCIOCHIP_DVO_VREFPON_DISABLE = 0x0,
+ DCIOCHIP_DVO_VREFPON_ENABLE = 0x1,
+} DCIOCHIP_DVO_VREFPON;
+typedef enum DCIOCHIP_DVO_VREFSEL {
+ DCIOCHIP_DVO_VREFSEL_ONCHIP = 0x0,
+ DCIOCHIP_DVO_VREFSEL_EXTERNAL = 0x1,
+} DCIOCHIP_DVO_VREFSEL;
+typedef enum DCP_GRPH_ENABLE {
+ DCP_GRPH_ENABLE_FALSE = 0x0,
+ DCP_GRPH_ENABLE_TRUE = 0x1,
+} DCP_GRPH_ENABLE;
+typedef enum DCP_GRPH_KEYER_ALPHA_SEL {
+ DCP_GRPH_KEYER_ALPHA_SEL_FALSE = 0x0,
+ DCP_GRPH_KEYER_ALPHA_SEL_TRUE = 0x1,
+} DCP_GRPH_KEYER_ALPHA_SEL;
+typedef enum DCP_GRPH_DEPTH {
+ DCP_GRPH_DEPTH_8BPP = 0x0,
+ DCP_GRPH_DEPTH_16BPP = 0x1,
+ DCP_GRPH_DEPTH_32BPP = 0x2,
+ DCP_GRPH_DEPTH_64BPP = 0x3,
+} DCP_GRPH_DEPTH;
+typedef enum DCP_GRPH_NUM_BANKS {
+ DCP_GRPH_NUM_BANKS_2BANK = 0x0,
+ DCP_GRPH_NUM_BANKS_4BANK = 0x1,
+ DCP_GRPH_NUM_BANKS_8BANK = 0x2,
+ DCP_GRPH_NUM_BANKS_16BANK = 0x3,
+} DCP_GRPH_NUM_BANKS;
+typedef enum DCP_GRPH_BANK_WIDTH {
+ DCP_GRPH_BANK_WIDTH_1 = 0x0,
+ DCP_GRPH_BANK_WIDTH_2 = 0x1,
+ DCP_GRPH_BANK_WIDTH_4 = 0x2,
+ DCP_GRPH_BANK_WIDTH_8 = 0x3,
+} DCP_GRPH_BANK_WIDTH;
+typedef enum DCP_GRPH_FORMAT {
+ DCP_GRPH_FORMAT_8BPP = 0x0,
+ DCP_GRPH_FORMAT_16BPP = 0x1,
+ DCP_GRPH_FORMAT_32BPP = 0x2,
+ DCP_GRPH_FORMAT_64BPP = 0x3,
+} DCP_GRPH_FORMAT;
+typedef enum DCP_GRPH_BANK_HEIGHT {
+ DCP_GRPH_BANK_HEIGHT_1 = 0x0,
+ DCP_GRPH_BANK_HEIGHT_2 = 0x1,
+ DCP_GRPH_BANK_HEIGHT_4 = 0x2,
+ DCP_GRPH_BANK_HEIGHT_8 = 0x3,
+} DCP_GRPH_BANK_HEIGHT;
+typedef enum DCP_GRPH_TILE_SPLIT {
+ DCP_GRPH_TILE_SPLIT_64B = 0x0,
+ DCP_GRPH_TILE_SPLIT_128B = 0x1,
+ DCP_GRPH_TILE_SPLIT_256B = 0x2,
+ DCP_GRPH_TILE_SPLIT_512B = 0x3,
+ DCP_GRPH_TILE_SPLIT_1B = 0x4,
+ DCP_GRPH_TILE_SPLIT_2B = 0x5,
+ DCP_GRPH_TILE_SPLIT_4B = 0x6,
+} DCP_GRPH_TILE_SPLIT;
+typedef enum DCP_GRPH_ADDRESS_TRANSLATION_ENABLE {
+ DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE = 0x0,
+ DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE = 0x1,
+} DCP_GRPH_ADDRESS_TRANSLATION_ENABLE;
+typedef enum DCP_GRPH_PRIVILEGED_ACCESS_ENABLE {
+ DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_FALSE = 0x0,
+ DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_TRUE = 0x1,
+} DCP_GRPH_PRIVILEGED_ACCESS_ENABLE;
+typedef enum DCP_GRPH_MACRO_TILE_ASPECT {
+ DCP_GRPH_MACRO_TILE_ASPECT_1 = 0x0,
+ DCP_GRPH_MACRO_TILE_ASPECT_2 = 0x1,
+ DCP_GRPH_MACRO_TILE_ASPECT_4 = 0x2,
+ DCP_GRPH_MACRO_TILE_ASPECT_8 = 0x3,
+} DCP_GRPH_MACRO_TILE_ASPECT;
+typedef enum DCP_GRPH_ARRAY_MODE {
+ DCP_GRPH_ARRAY_MODE_0 = 0x0,
+ DCP_GRPH_ARRAY_MODE_1 = 0x1,
+ DCP_GRPH_ARRAY_MODE_2 = 0x2,
+ DCP_GRPH_ARRAY_MODE_3 = 0x3,
+ DCP_GRPH_ARRAY_MODE_4 = 0x4,
+ DCP_GRPH_ARRAY_MODE_7 = 0x7,
+ DCP_GRPH_ARRAY_MODE_12 = 0xc,
+ DCP_GRPH_ARRAY_MODE_13 = 0xd,
+} DCP_GRPH_ARRAY_MODE;
+typedef enum DCP_GRPH_MICRO_TILE_MODE {
+ DCP_GRPH_MICRO_TILE_MODE_0 = 0x0,
+ DCP_GRPH_MICRO_TILE_MODE_1 = 0x1,
+ DCP_GRPH_MICRO_TILE_MODE_2 = 0x2,
+ DCP_GRPH_MICRO_TILE_MODE_3 = 0x3,
+} DCP_GRPH_MICRO_TILE_MODE;
+typedef enum DCP_GRPH_COLOR_EXPANSION_MODE {
+ DCP_GRPH_COLOR_EXPANSION_MODE_DEXP = 0x0,
+ DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP = 0x1,
+} DCP_GRPH_COLOR_EXPANSION_MODE;
+typedef enum DCP_GRPH_LUT_10BIT_BYPASS_EN {
+ DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE = 0x0,
+ DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE = 0x1,
+} DCP_GRPH_LUT_10BIT_BYPASS_EN;
+typedef enum DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN {
+ DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE = 0x0,
+ DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE = 0x1,
+} DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN;
+typedef enum DCP_GRPH_ENDIAN_SWAP {
+ DCP_GRPH_ENDIAN_SWAP_NONE = 0x0,
+ DCP_GRPH_ENDIAN_SWAP_8IN16 = 0x1,
+ DCP_GRPH_ENDIAN_SWAP_8IN32 = 0x2,
+ DCP_GRPH_ENDIAN_SWAP_8IN64 = 0x3,
+} DCP_GRPH_ENDIAN_SWAP;
+typedef enum DCP_GRPH_RED_CROSSBAR {
+ DCP_GRPH_RED_CROSSBAR_FROM_R = 0x0,
+ DCP_GRPH_RED_CROSSBAR_FROM_G = 0x1,
+ DCP_GRPH_RED_CROSSBAR_FROM_B = 0x2,
+ DCP_GRPH_RED_CROSSBAR_FROM_A = 0x3,
+} DCP_GRPH_RED_CROSSBAR;
+typedef enum DCP_GRPH_GREEN_CROSSBAR {
+ DCP_GRPH_GREEN_CROSSBAR_FROM_G = 0x0,
+ DCP_GRPH_GREEN_CROSSBAR_FROM_B = 0x1,
+ DCP_GRPH_GREEN_CROSSBAR_FROM_A = 0x2,
+ DCP_GRPH_GREEN_CROSSBAR_FROM_R = 0x3,
+} DCP_GRPH_GREEN_CROSSBAR;
+typedef enum DCP_GRPH_BLUE_CROSSBAR {
+ DCP_GRPH_BLUE_CROSSBAR_FROM_B = 0x0,
+ DCP_GRPH_BLUE_CROSSBAR_FROM_A = 0x1,
+ DCP_GRPH_BLUE_CROSSBAR_FROM_R = 0x2,
+ DCP_GRPH_BLUE_CROSSBAR_FROM_G = 0x3,
+} DCP_GRPH_BLUE_CROSSBAR;
+typedef enum DCP_GRPH_ALPHA_CROSSBAR {
+ DCP_GRPH_ALPHA_CROSSBAR_FROM_A = 0x0,
+ DCP_GRPH_ALPHA_CROSSBAR_FROM_R = 0x1,
+ DCP_GRPH_ALPHA_CROSSBAR_FROM_G = 0x2,
+ DCP_GRPH_ALPHA_CROSSBAR_FROM_B = 0x3,
+} DCP_GRPH_ALPHA_CROSSBAR;
+typedef enum DCP_GRPH_PRIMARY_DFQ_ENABLE {
+ DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE = 0x0,
+ DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE = 0x1,
+} DCP_GRPH_PRIMARY_DFQ_ENABLE;
+typedef enum DCP_GRPH_SECONDARY_DFQ_ENABLE {
+ DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE = 0x0,
+ DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE = 0x1,
+} DCP_GRPH_SECONDARY_DFQ_ENABLE;
+typedef enum DCP_GRPH_INPUT_GAMMA_MODE {
+ DCP_GRPH_INPUT_GAMMA_MODE_LUT = 0x0,
+ DCP_GRPH_INPUT_GAMMA_MODE_BYPASS = 0x1,
+} DCP_GRPH_INPUT_GAMMA_MODE;
+typedef enum DCP_GRPH_MODE_UPDATE_PENDING {
+ DCP_GRPH_MODE_UPDATE_PENDING_FALSE = 0x0,
+ DCP_GRPH_MODE_UPDATE_PENDING_TRUE = 0x1,
+} DCP_GRPH_MODE_UPDATE_PENDING;
+typedef enum DCP_GRPH_MODE_UPDATE_TAKEN {
+ DCP_GRPH_MODE_UPDATE_TAKEN_FALSE = 0x0,
+ DCP_GRPH_MODE_UPDATE_TAKEN_TRUE = 0x1,
+} DCP_GRPH_MODE_UPDATE_TAKEN;
+typedef enum DCP_GRPH_SURFACE_UPDATE_PENDING {
+ DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE = 0x0,
+ DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE = 0x1,
+} DCP_GRPH_SURFACE_UPDATE_PENDING;
+typedef enum DCP_GRPH_SURFACE_UPDATE_TAKEN {
+ DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE = 0x0,
+ DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE = 0x1,
+} DCP_GRPH_SURFACE_UPDATE_TAKEN;
+typedef enum DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE {
+ DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE = 0x0,
+ DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE = 0x1,
+} DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE;
+typedef enum DCP_GRPH_UPDATE_LOCK {
+ DCP_GRPH_UPDATE_LOCK_FALSE = 0x0,
+ DCP_GRPH_UPDATE_LOCK_TRUE = 0x1,
+} DCP_GRPH_UPDATE_LOCK;
+typedef enum DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
+ DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE = 0x0,
+ DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE = 0x1,
+} DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
+typedef enum DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
+ DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0,
+ DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1,
+} DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
+typedef enum DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
+ DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0,
+ DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1,
+} DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
+typedef enum DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN {
+ DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE = 0x0,
+ DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE = 0x1,
+} DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
+typedef enum DCP_GRPH_XDMA_SUPER_AA_EN {
+ DCP_GRPH_XDMA_SUPER_AA_EN_FALSE = 0x0,
+ DCP_GRPH_XDMA_SUPER_AA_EN_TRUE = 0x1,
+} DCP_GRPH_XDMA_SUPER_AA_EN;
+typedef enum DCP_GRPH_DFQ_RESET {
+ DCP_GRPH_DFQ_RESET_FALSE = 0x0,
+ DCP_GRPH_DFQ_RESET_TRUE = 0x1,
+} DCP_GRPH_DFQ_RESET;
+typedef enum DCP_GRPH_DFQ_SIZE {
+ DCP_GRPH_DFQ_SIZE_DEEP1 = 0x0,
+ DCP_GRPH_DFQ_SIZE_DEEP2 = 0x1,
+ DCP_GRPH_DFQ_SIZE_DEEP3 = 0x2,
+ DCP_GRPH_DFQ_SIZE_DEEP4 = 0x3,
+ DCP_GRPH_DFQ_SIZE_DEEP5 = 0x4,
+ DCP_GRPH_DFQ_SIZE_DEEP6 = 0x5,
+ DCP_GRPH_DFQ_SIZE_DEEP7 = 0x6,
+ DCP_GRPH_DFQ_SIZE_DEEP8 = 0x7,
+} DCP_GRPH_DFQ_SIZE;
+typedef enum DCP_GRPH_DFQ_MIN_FREE_ENTRIES {
+ DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1 = 0x0,
+ DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2 = 0x1,
+ DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3 = 0x2,
+ DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4 = 0x3,
+ DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5 = 0x4,
+ DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6 = 0x5,
+ DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7 = 0x6,
+ DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8 = 0x7,
+} DCP_GRPH_DFQ_MIN_FREE_ENTRIES;
+typedef enum DCP_GRPH_DFQ_RESET_ACK {
+ DCP_GRPH_DFQ_RESET_ACK_FALSE = 0x0,
+ DCP_GRPH_DFQ_RESET_ACK_TRUE = 0x1,
+} DCP_GRPH_DFQ_RESET_ACK;
+typedef enum DCP_GRPH_PFLIP_INT_CLEAR {
+ DCP_GRPH_PFLIP_INT_CLEAR_FALSE = 0x0,
+ DCP_GRPH_PFLIP_INT_CLEAR_TRUE = 0x1,
+} DCP_GRPH_PFLIP_INT_CLEAR;
+typedef enum DCP_GRPH_PFLIP_INT_MASK {
+ DCP_GRPH_PFLIP_INT_MASK_FALSE = 0x0,
+ DCP_GRPH_PFLIP_INT_MASK_TRUE = 0x1,
+} DCP_GRPH_PFLIP_INT_MASK;
+typedef enum DCP_GRPH_PFLIP_INT_TYPE {
+ DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL = 0x0,
+ DCP_GRPH_PFLIP_INT_TYPE_PULSE = 0x1,
+} DCP_GRPH_PFLIP_INT_TYPE;
+typedef enum DCP_GRPH_PRESCALE_SELECT {
+ DCP_GRPH_PRESCALE_SELECT_FIXED = 0x0,
+ DCP_GRPH_PRESCALE_SELECT_FLOATING = 0x1,
+} DCP_GRPH_PRESCALE_SELECT;
+typedef enum DCP_GRPH_PRESCALE_R_SIGN {
+ DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED = 0x0,
+ DCP_GRPH_PRESCALE_R_SIGN_SIGNED = 0x1,
+} DCP_GRPH_PRESCALE_R_SIGN;
+typedef enum DCP_GRPH_PRESCALE_G_SIGN {
+ DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED = 0x0,
+ DCP_GRPH_PRESCALE_G_SIGN_SIGNED = 0x1,
+} DCP_GRPH_PRESCALE_G_SIGN;
+typedef enum DCP_GRPH_PRESCALE_B_SIGN {
+ DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED = 0x0,
+ DCP_GRPH_PRESCALE_B_SIGN_SIGNED = 0x1,
+} DCP_GRPH_PRESCALE_B_SIGN;
+typedef enum DCP_GRPH_PRESCALE_BYPASS {
+ DCP_GRPH_PRESCALE_BYPASS_FALSE = 0x0,
+ DCP_GRPH_PRESCALE_BYPASS_TRUE = 0x1,
+} DCP_GRPH_PRESCALE_BYPASS;
+typedef enum DCP_INPUT_CSC_GRPH_MODE {
+ DCP_INPUT_CSC_GRPH_MODE_BYPASS = 0x0,
+ DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF = 0x1,
+ DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF = 0x2,
+ DCP_INPUT_CSC_GRPH_MODE_RESERVED = 0x3,
+} DCP_INPUT_CSC_GRPH_MODE;
+typedef enum DCP_OUTPUT_CSC_GRPH_MODE {
+ DCP_OUTPUT_CSC_GRPH_MODE_BYPASS = 0x0,
+ DCP_OUTPUT_CSC_GRPH_MODE_RGB = 0x1,
+ DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601 = 0x2,
+ DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709 = 0x3,
+ DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF = 0x4,
+ DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF = 0x5,
+ DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0 = 0x6,
+ DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1 = 0x7,
+} DCP_OUTPUT_CSC_GRPH_MODE;
+typedef enum DCP_DENORM_MODE {
+ DCP_DENORM_MODE_UNITY = 0x0,
+ DCP_DENORM_MODE_6BIT = 0x1,
+ DCP_DENORM_MODE_8BIT = 0x2,
+ DCP_DENORM_MODE_10BIT = 0x3,
+ DCP_DENORM_MODE_11BIT = 0x4,
+ DCP_DENORM_MODE_12BIT = 0x5,
+ DCP_DENORM_MODE_RESERVED0 = 0x6,
+ DCP_DENORM_MODE_RESERVED1 = 0x7,
+} DCP_DENORM_MODE;
+typedef enum DCP_DENORM_14BIT_OUT {
+ DCP_DENORM_14BIT_OUT_FALSE = 0x0,
+ DCP_DENORM_14BIT_OUT_TRUE = 0x1,
+} DCP_DENORM_14BIT_OUT;
+typedef enum DCP_OUT_ROUND_TRUNC_MODE {
+ DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12 = 0x0,
+ DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11 = 0x1,
+ DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10 = 0x2,
+ DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9 = 0x3,
+ DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8 = 0x4,
+ DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED = 0x5,
+ DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14 = 0x6,
+ DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13 = 0x7,
+ DCP_OUT_ROUND_TRUNC_MODE_ROUND_12 = 0x8,
+ DCP_OUT_ROUND_TRUNC_MODE_ROUND_11 = 0x9,
+ DCP_OUT_ROUND_TRUNC_MODE_ROUND_10 = 0xa,
+ DCP_OUT_ROUND_TRUNC_MODE_ROUND_9 = 0xb,
+ DCP_OUT_ROUND_TRUNC_MODE_ROUND_8 = 0xc,
+ DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED = 0xd,
+ DCP_OUT_ROUND_TRUNC_MODE_ROUND_14 = 0xe,
+ DCP_OUT_ROUND_TRUNC_MODE_ROUND_13 = 0xf,
+} DCP_OUT_ROUND_TRUNC_MODE;
+typedef enum DCP_KEY_MODE {
+ DCP_KEY_MODE_ALPHA0 = 0x0,
+ DCP_KEY_MODE_ALPHA1 = 0x1,
+ DCP_KEY_MODE_IN_RANGE_ALPHA1 = 0x2,
+ DCP_KEY_MODE_IN_RANGE_ALPHA0 = 0x3,
+} DCP_KEY_MODE;
+typedef enum DCP_GRPH_DEGAMMA_MODE {
+ DCP_GRPH_DEGAMMA_MODE_BYPASS = 0x0,
+ DCP_GRPH_DEGAMMA_MODE_ROMA = 0x1,
+ DCP_GRPH_DEGAMMA_MODE_ROMB = 0x2,
+ DCP_GRPH_DEGAMMA_MODE_RESERVED = 0x3,
+} DCP_GRPH_DEGAMMA_MODE;
+typedef enum DCP_CURSOR2_DEGAMMA_MODE {
+ DCP_CURSOR2_DEGAMMA_MODE_BYPASS = 0x0,
+ DCP_CURSOR2_DEGAMMA_MODE_ROMA = 0x1,
+ DCP_CURSOR2_DEGAMMA_MODE_ROMB = 0x2,
+ DCP_CURSOR2_DEGAMMA_MODE_RESERVED = 0x3,
+} DCP_CURSOR2_DEGAMMA_MODE;
+typedef enum DCP_CURSOR_DEGAMMA_MODE {
+ DCP_CURSOR_DEGAMMA_MODE_BYPASS = 0x0,
+ DCP_CURSOR_DEGAMMA_MODE_ROMA = 0x1,
+ DCP_CURSOR_DEGAMMA_MODE_ROMB = 0x2,
+ DCP_CURSOR_DEGAMMA_MODE_RESERVED = 0x3,
+} DCP_CURSOR_DEGAMMA_MODE;
+typedef enum DCP_GRPH_GAMUT_REMAP_MODE {
+ DCP_GRPH_GAMUT_REMAP_MODE_BYPASS = 0x0,
+ DCP_GRPH_GAMUT_REMAP_MODE_ROMA = 0x1,
+ DCP_GRPH_GAMUT_REMAP_MODE_ROMB = 0x2,
+ DCP_GRPH_GAMUT_REMAP_MODE_RESERVED = 0x3,
+} DCP_GRPH_GAMUT_REMAP_MODE;
+typedef enum DCP_SPATIAL_DITHER_EN {
+ DCP_SPATIAL_DITHER_EN_FALSE = 0x0,
+ DCP_SPATIAL_DITHER_EN_TRUE = 0x1,
+} DCP_SPATIAL_DITHER_EN;
+typedef enum DCP_SPATIAL_DITHER_MODE {
+ DCP_SPATIAL_DITHER_MODE_BYPASS = 0x0,
+ DCP_SPATIAL_DITHER_MODE_ROMA = 0x1,
+ DCP_SPATIAL_DITHER_MODE_ROMB = 0x2,
+ DCP_SPATIAL_DITHER_MODE_RESERVED = 0x3,
+} DCP_SPATIAL_DITHER_MODE;
+typedef enum DCP_SPATIAL_DITHER_DEPTH {
+ DCP_SPATIAL_DITHER_DEPTH_30BPP = 0x0,
+ DCP_SPATIAL_DITHER_DEPTH_24BPP = 0x1,
+ DCP_SPATIAL_DITHER_DEPTH_36BPP = 0x2,
+ DCP_SPATIAL_DITHER_DEPTH_UNDEFINED = 0x3,
+} DCP_SPATIAL_DITHER_DEPTH;
+typedef enum DCP_FRAME_RANDOM_ENABLE {
+ DCP_FRAME_RANDOM_ENABLE_FALSE = 0x0,
+ DCP_FRAME_RANDOM_ENABLE_TRUE = 0x1,
+} DCP_FRAME_RANDOM_ENABLE;
+typedef enum DCP_RGB_RANDOM_ENABLE {
+ DCP_RGB_RANDOM_ENABLE_FALSE = 0x0,
+ DCP_RGB_RANDOM_ENABLE_TRUE = 0x1,
+} DCP_RGB_RANDOM_ENABLE;
+typedef enum DCP_HIGHPASS_RANDOM_ENABLE {
+ DCP_HIGHPASS_RANDOM_ENABLE_FALSE = 0x0,
+ DCP_HIGHPASS_RANDOM_ENABLE_TRUE = 0x1,
+} DCP_HIGHPASS_RANDOM_ENABLE;
+typedef enum DCP_CURSOR_EN {
+ DCP_CURSOR_EN_FALSE = 0x0,
+ DCP_CURSOR_EN_TRUE = 0x1,
+} DCP_CURSOR_EN;
+typedef enum DCP_CUR_INV_TRANS_CLAMP {
+ DCP_CUR_INV_TRANS_CLAMP_FALSE = 0x0,
+ DCP_CUR_INV_TRANS_CLAMP_TRUE = 0x1,
+} DCP_CUR_INV_TRANS_CLAMP;
+typedef enum DCP_CURSOR_MODE {
+ DCP_CURSOR_MODE_MONO_2BPP = 0x0,
+ DCP_CURSOR_MODE_24BPP_1BIT = 0x1,
+ DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI = 0x2,
+ DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI = 0x3,
+} DCP_CURSOR_MODE;
+typedef enum DCP_CURSOR_2X_MAGNIFY {
+ DCP_CURSOR_2X_MAGNIFY_FALSE = 0x0,
+ DCP_CURSOR_2X_MAGNIFY_TRUE = 0x1,
+} DCP_CURSOR_2X_MAGNIFY;
+typedef enum DCP_CURSOR_FORCE_MC_ON {
+ DCP_CURSOR_FORCE_MC_ON_FALSE = 0x0,
+ DCP_CURSOR_FORCE_MC_ON_TRUE = 0x1,
+} DCP_CURSOR_FORCE_MC_ON;
+typedef enum DCP_CURSOR_URGENT_CONTROL {
+ DCP_CURSOR_URGENT_CONTROL_MODE_0 = 0x0,
+ DCP_CURSOR_URGENT_CONTROL_MODE_1 = 0x1,
+ DCP_CURSOR_URGENT_CONTROL_MODE_2 = 0x2,
+ DCP_CURSOR_URGENT_CONTROL_MODE_3 = 0x3,
+ DCP_CURSOR_URGENT_CONTROL_MODE_4 = 0x4,
+} DCP_CURSOR_URGENT_CONTROL;
+typedef enum DCP_CURSOR_UPDATE_PENDING {
+ DCP_CURSOR_UPDATE_PENDING_FALSE = 0x0,
+ DCP_CURSOR_UPDATE_PENDING_TRUE = 0x1,
+} DCP_CURSOR_UPDATE_PENDING;
+typedef enum DCP_CURSOR_UPDATE_TAKEN {
+ DCP_CURSOR_UPDATE_TAKEN_FALSE = 0x0,
+ DCP_CURSOR_UPDATE_TAKEN_TRUE = 0x1,
+} DCP_CURSOR_UPDATE_TAKEN;
+typedef enum DCP_CURSOR_UPDATE_LOCK {
+ DCP_CURSOR_UPDATE_LOCK_FALSE = 0x0,
+ DCP_CURSOR_UPDATE_LOCK_TRUE = 0x1,
+} DCP_CURSOR_UPDATE_LOCK;
+typedef enum DCP_CURSOR_DISABLE_MULTIPLE_UPDATE {
+ DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0,
+ DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1,
+} DCP_CURSOR_DISABLE_MULTIPLE_UPDATE;
+typedef enum DCP_CURSOR_UPDATE_STEREO_MODE {
+ DCP_CURSOR_UPDATE_STEREO_MODE_BOTH = 0x0,
+ DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY = 0x1,
+ DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED = 0x2,
+ DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY = 0x3,
+} DCP_CURSOR_UPDATE_STEREO_MODE;
+typedef enum DCP_CURSOR2_EN {
+ DCP_CURSOR2_EN_FALSE = 0x0,
+ DCP_CURSOR2_EN_TRUE = 0x1,
+} DCP_CURSOR2_EN;
+typedef enum DCP_CUR2_INV_TRANS_CLAMP {
+ DCP_CUR2_INV_TRANS_CLAMP_FALSE = 0x0,
+ DCP_CUR2_INV_TRANS_CLAMP_TRUE = 0x1,
+} DCP_CUR2_INV_TRANS_CLAMP;
+typedef enum DCP_CURSOR2_MODE {
+ DCP_CURSOR2_MODE_MONO_2BPP = 0x0,
+ DCP_CURSOR2_MODE_24BPP_1BIT = 0x1,
+ DCP_CURSOR2_MODE_24BPP_8BIT_PREMULTI = 0x2,
+ DCP_CURSOR2_MODE_24BPP_8BIT_UNPREMULTI = 0x3,
+} DCP_CURSOR2_MODE;
+typedef enum DCP_CURSOR2_2X_MAGNIFY {
+ DCP_CURSOR2_2X_MAGNIFY_FALSE = 0x0,
+ DCP_CURSOR2_2X_MAGNIFY_TRUE = 0x1,
+} DCP_CURSOR2_2X_MAGNIFY;
+typedef enum DCP_CURSOR2_FORCE_MC_ON {
+ DCP_CURSOR2_FORCE_MC_ON_FALSE = 0x0,
+ DCP_CURSOR2_FORCE_MC_ON_TRUE = 0x1,
+} DCP_CURSOR2_FORCE_MC_ON;
+typedef enum DCP_CURSOR2_URGENT_CONTROL {
+ DCP_CURSOR2_URGENT_CONTROL_MODE_0 = 0x0,
+ DCP_CURSOR2_URGENT_CONTROL_MODE_1 = 0x1,
+ DCP_CURSOR2_URGENT_CONTROL_MODE_2 = 0x2,
+ DCP_CURSOR2_URGENT_CONTROL_MODE_3 = 0x3,
+ DCP_CURSOR2_URGENT_CONTROL_MODE_4 = 0x4,
+} DCP_CURSOR2_URGENT_CONTROL;
+typedef enum DCP_CURSOR2_UPDATE_PENDING {
+ DCP_CURSOR2_UPDATE_PENDING_FALSE = 0x0,
+ DCP_CURSOR2_UPDATE_PENDING_TRUE = 0x1,
+} DCP_CURSOR2_UPDATE_PENDING;
+typedef enum DCP_CURSOR2_UPDATE_TAKEN {
+ DCP_CURSOR2_UPDATE_TAKEN_FALSE = 0x0,
+ DCP_CURSOR2_UPDATE_TAKEN_TRUE = 0x1,
+} DCP_CURSOR2_UPDATE_TAKEN;
+typedef enum DCP_CURSOR2_UPDATE_LOCK {
+ DCP_CURSOR2_UPDATE_LOCK_FALSE = 0x0,
+ DCP_CURSOR2_UPDATE_LOCK_TRUE = 0x1,
+} DCP_CURSOR2_UPDATE_LOCK;
+typedef enum DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE {
+ DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0,
+ DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1,
+} DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE;
+typedef enum DCP_CURSOR2_UPDATE_STEREO_MODE {
+ DCP_CURSOR2_UPDATE_STEREO_MODE_BOTH = 0x0,
+ DCP_CURSOR2_UPDATE_STEREO_MODE_SECONDARY_ONLY = 0x1,
+ DCP_CURSOR2_UPDATE_STEREO_MODE_UNDEFINED = 0x2,
+ DCP_CURSOR2_UPDATE_STEREO_MODE_PRIMARY_ONLY = 0x3,
+} DCP_CURSOR2_UPDATE_STEREO_MODE;
+typedef enum DCP_CUR_REQUEST_FILTER_DIS {
+ DCP_CUR_REQUEST_FILTER_DIS_FALSE = 0x0,
+ DCP_CUR_REQUEST_FILTER_DIS_TRUE = 0x1,
+} DCP_CUR_REQUEST_FILTER_DIS;
+typedef enum DCP_CURSOR_STEREO_EN {
+ DCP_CURSOR_STEREO_EN_FALSE = 0x0,
+ DCP_CURSOR_STEREO_EN_TRUE = 0x1,
+} DCP_CURSOR_STEREO_EN;
+typedef enum DCP_CURSOR_STEREO_OFFSET_YNX {
+ DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION = 0x0,
+ DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION = 0x1,
+} DCP_CURSOR_STEREO_OFFSET_YNX;
+typedef enum DCP_CURSOR2_STEREO_EN {
+ DCP_CURSOR2_STEREO_EN_FALSE = 0x0,
+ DCP_CURSOR2_STEREO_EN_TRUE = 0x1,
+} DCP_CURSOR2_STEREO_EN;
+typedef enum DCP_CURSOR2_STEREO_OFFSET_YNX {
+ DCP_CURSOR2_STEREO_OFFSET_YNX_X_POSITION = 0x0,
+ DCP_CURSOR2_STEREO_OFFSET_YNX_Y_POSITION = 0x1,
+} DCP_CURSOR2_STEREO_OFFSET_YNX;
+typedef enum DCP_DC_LUT_RW_MODE {
+ DCP_DC_LUT_RW_MODE_256_ENTRY = 0x0,
+ DCP_DC_LUT_RW_MODE_PWL = 0x1,
+} DCP_DC_LUT_RW_MODE;
+typedef enum DCP_DC_LUT_VGA_ACCESS_ENABLE {
+ DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE = 0x0,
+ DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE = 0x1,
+} DCP_DC_LUT_VGA_ACCESS_ENABLE;
+typedef enum DCP_DC_LUT_AUTOFILL {
+ DCP_DC_LUT_AUTOFILL_FALSE = 0x0,
+ DCP_DC_LUT_AUTOFILL_TRUE = 0x1,
+} DCP_DC_LUT_AUTOFILL;
+typedef enum DCP_DC_LUT_AUTOFILL_DONE {
+ DCP_DC_LUT_AUTOFILL_DONE_FALSE = 0x0,
+ DCP_DC_LUT_AUTOFILL_DONE_TRUE = 0x1,
+} DCP_DC_LUT_AUTOFILL_DONE;
+typedef enum DCP_DC_LUT_INC_B {
+ DCP_DC_LUT_INC_B_NA = 0x0,
+ DCP_DC_LUT_INC_B_2 = 0x1,
+ DCP_DC_LUT_INC_B_4 = 0x2,
+ DCP_DC_LUT_INC_B_8 = 0x3,
+ DCP_DC_LUT_INC_B_16 = 0x4,
+ DCP_DC_LUT_INC_B_32 = 0x5,
+ DCP_DC_LUT_INC_B_64 = 0x6,
+ DCP_DC_LUT_INC_B_128 = 0x7,
+ DCP_DC_LUT_INC_B_256 = 0x8,
+ DCP_DC_LUT_INC_B_512 = 0x9,
+} DCP_DC_LUT_INC_B;
+typedef enum DCP_DC_LUT_DATA_B_SIGNED_EN {
+ DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE = 0x0,
+ DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE = 0x1,
+} DCP_DC_LUT_DATA_B_SIGNED_EN;
+typedef enum DCP_DC_LUT_DATA_B_FLOAT_POINT_EN {
+ DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE = 0x0,
+ DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE = 0x1,
+} DCP_DC_LUT_DATA_B_FLOAT_POINT_EN;
+typedef enum DCP_DC_LUT_DATA_B_FORMAT {
+ DCP_DC_LUT_DATA_B_FORMAT_U0P10 = 0x0,
+ DCP_DC_LUT_DATA_B_FORMAT_S1P10 = 0x1,
+ DCP_DC_LUT_DATA_B_FORMAT_U1P11 = 0x2,
+ DCP_DC_LUT_DATA_B_FORMAT_U0P12 = 0x3,
+} DCP_DC_LUT_DATA_B_FORMAT;
+typedef enum DCP_DC_LUT_INC_G {
+ DCP_DC_LUT_INC_G_NA = 0x0,
+ DCP_DC_LUT_INC_G_2 = 0x1,
+ DCP_DC_LUT_INC_G_4 = 0x2,
+ DCP_DC_LUT_INC_G_8 = 0x3,
+ DCP_DC_LUT_INC_G_16 = 0x4,
+ DCP_DC_LUT_INC_G_32 = 0x5,
+ DCP_DC_LUT_INC_G_64 = 0x6,
+ DCP_DC_LUT_INC_G_128 = 0x7,
+ DCP_DC_LUT_INC_G_256 = 0x8,
+ DCP_DC_LUT_INC_G_512 = 0x9,
+} DCP_DC_LUT_INC_G;
+typedef enum DCP_DC_LUT_DATA_G_SIGNED_EN {
+ DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE = 0x0,
+ DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE = 0x1,
+} DCP_DC_LUT_DATA_G_SIGNED_EN;
+typedef enum DCP_DC_LUT_DATA_G_FLOAT_POINT_EN {
+ DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE = 0x0,
+ DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE = 0x1,
+} DCP_DC_LUT_DATA_G_FLOAT_POINT_EN;
+typedef enum DCP_DC_LUT_DATA_G_FORMAT {
+ DCP_DC_LUT_DATA_G_FORMAT_U0P10 = 0x0,
+ DCP_DC_LUT_DATA_G_FORMAT_S1P10 = 0x1,
+ DCP_DC_LUT_DATA_G_FORMAT_U1P11 = 0x2,
+ DCP_DC_LUT_DATA_G_FORMAT_U0P12 = 0x3,
+} DCP_DC_LUT_DATA_G_FORMAT;
+typedef enum DCP_DC_LUT_INC_R {
+ DCP_DC_LUT_INC_R_NA = 0x0,
+ DCP_DC_LUT_INC_R_2 = 0x1,
+ DCP_DC_LUT_INC_R_4 = 0x2,
+ DCP_DC_LUT_INC_R_8 = 0x3,
+ DCP_DC_LUT_INC_R_16 = 0x4,
+ DCP_DC_LUT_INC_R_32 = 0x5,
+ DCP_DC_LUT_INC_R_64 = 0x6,
+ DCP_DC_LUT_INC_R_128 = 0x7,
+ DCP_DC_LUT_INC_R_256 = 0x8,
+ DCP_DC_LUT_INC_R_512 = 0x9,
+} DCP_DC_LUT_INC_R;
+typedef enum DCP_DC_LUT_DATA_R_SIGNED_EN {
+ DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE = 0x0,
+ DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE = 0x1,
+} DCP_DC_LUT_DATA_R_SIGNED_EN;
+typedef enum DCP_DC_LUT_DATA_R_FLOAT_POINT_EN {
+ DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE = 0x0,
+ DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE = 0x1,
+} DCP_DC_LUT_DATA_R_FLOAT_POINT_EN;
+typedef enum DCP_DC_LUT_DATA_R_FORMAT {
+ DCP_DC_LUT_DATA_R_FORMAT_U0P10 = 0x0,
+ DCP_DC_LUT_DATA_R_FORMAT_S1P10 = 0x1,
+ DCP_DC_LUT_DATA_R_FORMAT_U1P11 = 0x2,
+ DCP_DC_LUT_DATA_R_FORMAT_U0P12 = 0x3,
+} DCP_DC_LUT_DATA_R_FORMAT;
+typedef enum DCP_CRC_ENABLE {
+ DCP_CRC_ENABLE_FALSE = 0x0,
+ DCP_CRC_ENABLE_TRUE = 0x1,
+} DCP_CRC_ENABLE;
+typedef enum DCP_CRC_SOURCE_SEL {
+ DCP_CRC_SOURCE_SEL_OUTPUT_PIX = 0x0,
+ DCP_CRC_SOURCE_SEL_INPUT_L32 = 0x1,
+ DCP_CRC_SOURCE_SEL_INPUT_H32 = 0x2,
+ DCP_CRC_SOURCE_SEL_OUTPUT_CNTL = 0x4,
+} DCP_CRC_SOURCE_SEL;
+typedef enum DCP_CRC_LINE_SEL {
+ DCP_CRC_LINE_SEL_RESERVED = 0x0,
+ DCP_CRC_LINE_SEL_EVEN = 0x1,
+ DCP_CRC_LINE_SEL_ODD = 0x2,
+ DCP_CRC_LINE_SEL_BOTH = 0x3,
+} DCP_CRC_LINE_SEL;
+typedef enum DCP_GRPH_FLIP_RATE {
+ DCP_GRPH_FLIP_RATE_1FRAME = 0x0,
+ DCP_GRPH_FLIP_RATE_2FRAME = 0x1,
+ DCP_GRPH_FLIP_RATE_3FRAME = 0x2,
+ DCP_GRPH_FLIP_RATE_4FRAME = 0x3,
+ DCP_GRPH_FLIP_RATE_5FRAME = 0x4,
+ DCP_GRPH_FLIP_RATE_6FRAME = 0x5,
+ DCP_GRPH_FLIP_RATE_7FRAME = 0x6,
+ DCP_GRPH_FLIP_RATE_8FRAME = 0x7,
+} DCP_GRPH_FLIP_RATE;
+typedef enum DCP_GRPH_FLIP_RATE_ENABLE {
+ DCP_GRPH_FLIP_RATE_ENABLE_FALSE = 0x0,
+ DCP_GRPH_FLIP_RATE_ENABLE_TRUE = 0x1,
+} DCP_GRPH_FLIP_RATE_ENABLE;
+typedef enum DCP_GSL0_EN {
+ DCP_GSL0_EN_FALSE = 0x0,
+ DCP_GSL0_EN_TRUE = 0x1,
+} DCP_GSL0_EN;
+typedef enum DCP_GSL1_EN {
+ DCP_GSL1_EN_FALSE = 0x0,
+ DCP_GSL1_EN_TRUE = 0x1,
+} DCP_GSL1_EN;
+typedef enum DCP_GSL2_EN {
+ DCP_GSL2_EN_FALSE = 0x0,
+ DCP_GSL2_EN_TRUE = 0x1,
+} DCP_GSL2_EN;
+typedef enum DCP_GSL_MASTER_EN {
+ DCP_GSL_MASTER_EN_FALSE = 0x0,
+ DCP_GSL_MASTER_EN_TRUE = 0x1,
+} DCP_GSL_MASTER_EN;
+typedef enum DCP_GSL_XDMA_GROUP {
+ DCP_GSL_XDMA_GROUP_VSYNC = 0x0,
+ DCP_GSL_XDMA_GROUP_HSYNC0 = 0x1,
+ DCP_GSL_XDMA_GROUP_HSYNC1 = 0x2,
+ DCP_GSL_XDMA_GROUP_HSYNC2 = 0x3,
+} DCP_GSL_XDMA_GROUP;
+typedef enum DCP_GSL_XDMA_GROUP_UNDERFLOW_EN {
+ DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE = 0x0,
+ DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE = 0x1,
+} DCP_GSL_XDMA_GROUP_UNDERFLOW_EN;
+typedef enum DCP_GSL_SYNC_SOURCE {
+ DCP_GSL_SYNC_SOURCE_FLIP = 0x0,
+ DCP_GSL_SYNC_SOURCE_PHASE0 = 0x1,
+ DCP_GSL_SYNC_SOURCE_RESET = 0x2,
+ DCP_GSL_SYNC_SOURCE_PHASE1 = 0x3,
+} DCP_GSL_SYNC_SOURCE;
+typedef enum DCP_GSL_DELAY_SURFACE_UPDATE_PENDING {
+ DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE = 0x0,
+ DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE = 0x1,
+} DCP_GSL_DELAY_SURFACE_UPDATE_PENDING;
+typedef enum DCP_TEST_DEBUG_WRITE_EN {
+ DCP_TEST_DEBUG_WRITE_EN_FALSE = 0x0,
+ DCP_TEST_DEBUG_WRITE_EN_TRUE = 0x1,
+} DCP_TEST_DEBUG_WRITE_EN;
+typedef enum DCP_GRPH_STEREOSYNC_FLIP_EN {
+ DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE = 0x0,
+ DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE = 0x1,
+} DCP_GRPH_STEREOSYNC_FLIP_EN;
+typedef enum DCP_GRPH_STEREOSYNC_FLIP_MODE {
+ DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP = 0x0,
+ DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0 = 0x1,
+ DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET = 0x2,
+ DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1 = 0x3,
+} DCP_GRPH_STEREOSYNC_FLIP_MODE;
+typedef enum DCP_GRPH_STEREOSYNC_SELECT_DISABLE {
+ DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE = 0x0,
+ DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE = 0x1,
+} DCP_GRPH_STEREOSYNC_SELECT_DISABLE;
+typedef enum DCP_GRPH_ROTATION_ANGLE {
+ DCP_GRPH_ROTATION_ANGLE_0 = 0x0,
+ DCP_GRPH_ROTATION_ANGLE_90 = 0x1,
+ DCP_GRPH_ROTATION_ANGLE_180 = 0x2,
+ DCP_GRPH_ROTATION_ANGLE_270 = 0x3,
+} DCP_GRPH_ROTATION_ANGLE;
+typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN {
+ DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE = 0x0,
+ DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE = 0x1,
+} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN;
+typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE {
+ DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM = 0x0,
+ DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE= 0x1,
+} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE;
+typedef enum DCP_GRPH_REGAMMA_MODE {
+ DCP_GRPH_REGAMMA_MODE_BYPASS = 0x0,
+ DCP_GRPH_REGAMMA_MODE_SRGB = 0x1,
+ DCP_GRPH_REGAMMA_MODE_XVYCC = 0x2,
+ DCP_GRPH_REGAMMA_MODE_PROGA = 0x3,
+ DCP_GRPH_REGAMMA_MODE_PROGB = 0x4,
+} DCP_GRPH_REGAMMA_MODE;
+typedef enum DCP_ALPHA_ROUND_TRUNC_MODE {
+ DCP_ALPHA_ROUND_TRUNC_MODE_ROUND = 0x0,
+ DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC = 0x1,
+} DCP_ALPHA_ROUND_TRUNC_MODE;
+typedef enum DCP_CURSOR_ALPHA_BLND_ENA {
+ DCP_CURSOR_ALPHA_BLND_ENA_FALSE = 0x0,
+ DCP_CURSOR_ALPHA_BLND_ENA_TRUE = 0x1,
+} DCP_CURSOR_ALPHA_BLND_ENA;
+typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK {
+ DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE = 0x0,
+ DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE = 0x1,
+} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK;
+typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK {
+ DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE = 0x0,
+ DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE = 0x1,
+} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK;
+typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK {
+ DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE = 0x0,
+ DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE = 0x1,
+} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK;
+typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK {
+ DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE = 0x0,
+ DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE = 0x1,
+} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK;
+typedef enum DCP_GRPH_SURFACE_COUNTER_EN {
+ DCP_GRPH_SURFACE_COUNTER_EN_DISABLE = 0x0,
+ DCP_GRPH_SURFACE_COUNTER_EN_ENABLE = 0x1,
+} DCP_GRPH_SURFACE_COUNTER_EN;
+typedef enum DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT {
+ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0 = 0x0,
+ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1 = 0x1,
+ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2 = 0x2,
+ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3 = 0x3,
+ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4 = 0x4,
+ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5 = 0x5,
+ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6 = 0x6,
+ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7 = 0x7,
+ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8 = 0x8,
+ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9 = 0x9,
+ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10 = 0xa,
+ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11 = 0xb,
+} DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT;
+typedef enum DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED {
+ DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO = 0x0,
+ DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES = 0x1,
+} DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED;
+typedef enum HDMI_KEEPOUT_MODE {
+ HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0x0,
+ HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 0x1,
+} HDMI_KEEPOUT_MODE;
+typedef enum HDMI_CLOCK_CHANNEL_RATE {
+ HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0x0,
+ HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 0x1,
+} HDMI_CLOCK_CHANNEL_RATE;
+typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
+ HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0x0,
+ HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 0x1,
+} HDMI_NO_EXTRA_NULL_PACKET_FILLED;
+typedef enum HDMI_PACKET_GEN_VERSION {
+ HDMI_PACKET_GEN_VERSION_OLD = 0x0,
+ HDMI_PACKET_GEN_VERSION_NEW = 0x1,
+} HDMI_PACKET_GEN_VERSION;
+typedef enum HDMI_ERROR_ACK {
+ HDMI_ERROR_ACK_INT = 0x0,
+ HDMI_ERROR_NOT_ACK = 0x1,
+} HDMI_ERROR_ACK;
+typedef enum HDMI_ERROR_MASK {
+ HDMI_ERROR_MASK_INT = 0x0,
+ HDMI_ERROR_NOT_MASK = 0x1,
+} HDMI_ERROR_MASK;
+typedef enum HDMI_DEEP_COLOR_DEPTH {
+ HDMI_DEEP_COLOR_DEPTH_24BPP = 0x0,
+ HDMI_DEEP_COLOR_DEPTH_30BPP = 0x1,
+ HDMI_DEEP_COLOR_DEPTH_36BPP = 0x2,
+ HDMI_DEEP_COLOR_DEPTH_RESERVED = 0x3,
+} HDMI_DEEP_COLOR_DEPTH;
+typedef enum HDMI_AUDIO_DELAY_EN {
+ HDMI_AUDIO_DELAY_DISABLE = 0x0,
+ HDMI_AUDIO_DELAY_58CLK = 0x1,
+ HDMI_AUDIO_DELAY_56CLK = 0x2,
+ HDMI_AUDIO_DELAY_RESERVED = 0x3,
+} HDMI_AUDIO_DELAY_EN;
+typedef enum HDMI_AUDIO_SEND_MAX_PACKETS {
+ HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0x0,
+ HDMI_SEND_MAX_AUDIO_PACKETS = 0x1,
+} HDMI_AUDIO_SEND_MAX_PACKETS;
+typedef enum HDMI_ACR_SEND {
+ HDMI_ACR_NOT_SEND = 0x0,
+ HDMI_ACR_PKT_SEND = 0x1,
+} HDMI_ACR_SEND;
+typedef enum HDMI_ACR_CONT {
+ HDMI_ACR_CONT_DISABLE = 0x0,
+ HDMI_ACR_CONT_ENABLE = 0x1,
+} HDMI_ACR_CONT;
+typedef enum HDMI_ACR_SELECT {
+ HDMI_ACR_SELECT_HW = 0x0,
+ HDMI_ACR_SELECT_32K = 0x1,
+ HDMI_ACR_SELECT_44K = 0x2,
+ HDMI_ACR_SELECT_48K = 0x3,
+} HDMI_ACR_SELECT;
+typedef enum HDMI_ACR_SOURCE {
+ HDMI_ACR_SOURCE_HW = 0x0,
+ HDMI_ACR_SOURCE_SW = 0x1,
+} HDMI_ACR_SOURCE;
+typedef enum HDMI_ACR_N_MULTIPLE {
+ HDMI_ACR_0_MULTIPLE_RESERVED = 0x0,
+ HDMI_ACR_1_MULTIPLE = 0x1,
+ HDMI_ACR_2_MULTIPLE = 0x2,
+ HDMI_ACR_3_MULTIPLE_RESERVED = 0x3,
+ HDMI_ACR_4_MULTIPLE = 0x4,
+ HDMI_ACR_5_MULTIPLE_RESERVED = 0x5,
+ HDMI_ACR_6_MULTIPLE_RESERVED = 0x6,
+ HDMI_ACR_7_MULTIPLE_RESERVED = 0x7,
+} HDMI_ACR_N_MULTIPLE;
+typedef enum HDMI_ACR_AUDIO_PRIORITY {
+ HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x0,
+ HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x1,
+} HDMI_ACR_AUDIO_PRIORITY;
+typedef enum HDMI_NULL_SEND {
+ HDMI_NULL_NOT_SEND = 0x0,
+ HDMI_NULL_PKT_SEND = 0x1,
+} HDMI_NULL_SEND;
+typedef enum HDMI_GC_SEND {
+ HDMI_GC_NOT_SEND = 0x0,
+ HDMI_GC_PKT_SEND = 0x1,
+} HDMI_GC_SEND;
+typedef enum HDMI_GC_CONT {
+ HDMI_GC_CONT_DISABLE = 0x0,
+ HDMI_GC_CONT_ENABLE = 0x1,
+} HDMI_GC_CONT;
+typedef enum HDMI_ISRC_SEND {
+ HDMI_ISRC_NOT_SEND = 0x0,
+ HDMI_ISRC_PKT_SEND = 0x1,
+} HDMI_ISRC_SEND;
+typedef enum HDMI_ISRC_CONT {
+ HDMI_ISRC_CONT_DISABLE = 0x0,
+ HDMI_ISRC_CONT_ENABLE = 0x1,
+} HDMI_ISRC_CONT;
+typedef enum HDMI_AVI_INFO_SEND {
+ HDMI_AVI_INFO_NOT_SEND = 0x0,
+ HDMI_AVI_INFO_PKT_SEND = 0x1,
+} HDMI_AVI_INFO_SEND;
+typedef enum HDMI_AVI_INFO_CONT {
+ HDMI_AVI_INFO_CONT_DISABLE = 0x0,
+ HDMI_AVI_INFO_CONT_ENABLE = 0x1,
+} HDMI_AVI_INFO_CONT;
+typedef enum HDMI_AUDIO_INFO_SEND {
+ HDMI_AUDIO_INFO_NOT_SEND = 0x0,
+ HDMI_AUDIO_INFO_PKT_SEND = 0x1,
+} HDMI_AUDIO_INFO_SEND;
+typedef enum HDMI_AUDIO_INFO_CONT {
+ HDMI_AUDIO_INFO_CONT_DISABLE = 0x0,
+ HDMI_AUDIO_INFO_CONT_ENABLE = 0x1,
+} HDMI_AUDIO_INFO_CONT;
+typedef enum HDMI_MPEG_INFO_SEND {
+ HDMI_MPEG_INFO_NOT_SEND = 0x0,
+ HDMI_MPEG_INFO_PKT_SEND = 0x1,
+} HDMI_MPEG_INFO_SEND;
+typedef enum HDMI_MPEG_INFO_CONT {
+ HDMI_MPEG_INFO_CONT_DISABLE = 0x0,
+ HDMI_MPEG_INFO_CONT_ENABLE = 0x1,
+} HDMI_MPEG_INFO_CONT;
+typedef enum HDMI_GENERIC0_SEND {
+ HDMI_GENERIC0_NOT_SEND = 0x0,
+ HDMI_GENERIC0_PKT_SEND = 0x1,
+} HDMI_GENERIC0_SEND;
+typedef enum HDMI_GENERIC0_CONT {
+ HDMI_GENERIC0_CONT_DISABLE = 0x0,
+ HDMI_GENERIC0_CONT_ENABLE = 0x1,
+} HDMI_GENERIC0_CONT;
+typedef enum HDMI_GENERIC1_SEND {
+ HDMI_GENERIC1_NOT_SEND = 0x0,
+ HDMI_GENERIC1_PKT_SEND = 0x1,
+} HDMI_GENERIC1_SEND;
+typedef enum HDMI_GENERIC1_CONT {
+ HDMI_GENERIC1_CONT_DISABLE = 0x0,
+ HDMI_GENERIC1_CONT_ENABLE = 0x1,
+} HDMI_GENERIC1_CONT;
+typedef enum HDMI_GC_AVMUTE_CONT {
+ HDMI_GC_AVMUTE_CONT_DISABLE = 0x0,
+ HDMI_GC_AVMUTE_CONT_ENABLE = 0x1,
+} HDMI_GC_AVMUTE_CONT;
+typedef enum HDMI_PACKING_PHASE_OVERRIDE {
+ HDMI_PACKING_PHASE_SET_BY_HW = 0x0,
+ HDMI_PACKING_PHASE_SET_BY_SW = 0x1,
+} HDMI_PACKING_PHASE_OVERRIDE;
+typedef enum HDMI_GENERIC2_SEND {
+ HDMI_GENERIC2_NOT_SEND = 0x0,
+ HDMI_GENERIC2_PKT_SEND = 0x1,
+} HDMI_GENERIC2_SEND;
+typedef enum HDMI_GENERIC2_CONT {
+ HDMI_GENERIC2_CONT_DISABLE = 0x0,
+ HDMI_GENERIC2_CONT_ENABLE = 0x1,
+} HDMI_GENERIC2_CONT;
+typedef enum HDMI_GENERIC3_SEND {
+ HDMI_GENERIC3_NOT_SEND = 0x0,
+ HDMI_GENERIC3_PKT_SEND = 0x1,
+} HDMI_GENERIC3_SEND;
+typedef enum HDMI_GENERIC3_CONT {
+ HDMI_GENERIC3_CONT_DISABLE = 0x0,
+ HDMI_GENERIC3_CONT_ENABLE = 0x1,
+} HDMI_GENERIC3_CONT;
+typedef enum TMDS_PIXEL_ENCODING {
+ TMDS_PIXEL_ENCODING_444 = 0x0,
+ TMDS_PIXEL_ENCODING_422 = 0x1,
+} TMDS_PIXEL_ENCODING;
+typedef enum TMDS_COLOR_FORMAT {
+ TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP= 0x0,
+ TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 0x1,
+ TMDS_COLOR_FORMAT_DUAL30BPP = 0x2,
+ TMDS_COLOR_FORMAT_RESERVED = 0x3,
+} TMDS_COLOR_FORMAT;
+typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
+ TMDS_STEREOSYNC_CTL0 = 0x0,
+ TMDS_STEREOSYNC_CTL1 = 0x1,
+ TMDS_STEREOSYNC_CTL2 = 0x2,
+ TMDS_STEREOSYNC_CTL3 = 0x3,
+} TMDS_STEREOSYNC_CTL_SEL_REG;
+typedef enum TMDS_CTL0_DATA_SEL {
+ TMDS_CTL0_DATA_SEL0_RESERVED = 0x0,
+ TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 0x1,
+ TMDS_CTL0_DATA_SEL2_VSYNC = 0x2,
+ TMDS_CTL0_DATA_SEL3_RESERVED = 0x3,
+ TMDS_CTL0_DATA_SEL4_HSYNC = 0x4,
+ TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 0x5,
+ TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 0x6,
+ TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 0x7,
+} TMDS_CTL0_DATA_SEL;
+typedef enum TMDS_CTL0_DATA_DELAY {
+ TMDS_CTL0_DATA_DELAY_0PIX = 0x0,
+ TMDS_CTL0_DATA_DELAY_1PIX = 0x1,
+ TMDS_CTL0_DATA_DELAY_2PIX = 0x2,
+ TMDS_CTL0_DATA_DELAY_3PIX = 0x3,
+ TMDS_CTL0_DATA_DELAY_4PIX = 0x4,
+ TMDS_CTL0_DATA_DELAY_5PIX = 0x5,
+ TMDS_CTL0_DATA_DELAY_6PIX = 0x6,
+ TMDS_CTL0_DATA_DELAY_7PIX = 0x7,
+} TMDS_CTL0_DATA_DELAY;
+typedef enum TMDS_CTL0_DATA_INVERT {
+ TMDS_CTL0_DATA_NORMAL = 0x0,
+ TMDS_CTL0_DATA_INVERT_EN = 0x1,
+} TMDS_CTL0_DATA_INVERT;
+typedef enum TMDS_CTL0_DATA_MODULATION {
+ TMDS_CTL0_DATA_MODULATION_DISABLE = 0x0,
+ TMDS_CTL0_DATA_MODULATION_BIT0 = 0x1,
+ TMDS_CTL0_DATA_MODULATION_BIT1 = 0x2,
+ TMDS_CTL0_DATA_MODULATION_BIT2 = 0x3,
+} TMDS_CTL0_DATA_MODULATION;
+typedef enum TMDS_CTL0_PATTERN_OUT_EN {
+ TMDS_CTL0_PATTERN_OUT_DISABLE = 0x0,
+ TMDS_CTL0_PATTERN_OUT_ENABLE = 0x1,
+} TMDS_CTL0_PATTERN_OUT_EN;
+typedef enum TMDS_CTL1_DATA_SEL {
+ TMDS_CTL1_DATA_SEL0_RESERVED = 0x0,
+ TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 0x1,
+ TMDS_CTL1_DATA_SEL2_VSYNC = 0x2,
+ TMDS_CTL1_DATA_SEL3_RESERVED = 0x3,
+ TMDS_CTL1_DATA_SEL4_HSYNC = 0x4,
+ TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 0x5,
+ TMDS_CTL1_DATA_SEL8_BLANK_TIME = 0x6,
+ TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 0x7,
+} TMDS_CTL1_DATA_SEL;
+typedef enum TMDS_CTL1_DATA_DELAY {
+ TMDS_CTL1_DATA_DELAY_0PIX = 0x0,
+ TMDS_CTL1_DATA_DELAY_1PIX = 0x1,
+ TMDS_CTL1_DATA_DELAY_2PIX = 0x2,
+ TMDS_CTL1_DATA_DELAY_3PIX = 0x3,
+ TMDS_CTL1_DATA_DELAY_4PIX = 0x4,
+ TMDS_CTL1_DATA_DELAY_5PIX = 0x5,
+ TMDS_CTL1_DATA_DELAY_6PIX = 0x6,
+ TMDS_CTL1_DATA_DELAY_7PIX = 0x7,
+} TMDS_CTL1_DATA_DELAY;
+typedef enum TMDS_CTL1_DATA_INVERT {
+ TMDS_CTL1_DATA_NORMAL = 0x0,
+ TMDS_CTL1_DATA_INVERT_EN = 0x1,
+} TMDS_CTL1_DATA_INVERT;
+typedef enum TMDS_CTL1_DATA_MODULATION {
+ TMDS_CTL1_DATA_MODULATION_DISABLE = 0x0,
+ TMDS_CTL1_DATA_MODULATION_BIT0 = 0x1,
+ TMDS_CTL1_DATA_MODULATION_BIT1 = 0x2,
+ TMDS_CTL1_DATA_MODULATION_BIT2 = 0x3,
+} TMDS_CTL1_DATA_MODULATION;
+typedef enum TMDS_CTL1_PATTERN_OUT_EN {
+ TMDS_CTL1_PATTERN_OUT_DISABLE = 0x0,
+ TMDS_CTL1_PATTERN_OUT_ENABLE = 0x1,
+} TMDS_CTL1_PATTERN_OUT_EN;
+typedef enum TMDS_CTL2_DATA_SEL {
+ TMDS_CTL2_DATA_SEL0_RESERVED = 0x0,
+ TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 0x1,
+ TMDS_CTL2_DATA_SEL2_VSYNC = 0x2,
+ TMDS_CTL2_DATA_SEL3_RESERVED = 0x3,
+ TMDS_CTL2_DATA_SEL4_HSYNC = 0x4,
+ TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 0x5,
+ TMDS_CTL2_DATA_SEL8_BLANK_TIME = 0x6,
+ TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 0x7,
+} TMDS_CTL2_DATA_SEL;
+typedef enum TMDS_CTL2_DATA_DELAY {
+ TMDS_CTL2_DATA_DELAY_0PIX = 0x0,
+ TMDS_CTL2_DATA_DELAY_1PIX = 0x1,
+ TMDS_CTL2_DATA_DELAY_2PIX = 0x2,
+ TMDS_CTL2_DATA_DELAY_3PIX = 0x3,
+ TMDS_CTL2_DATA_DELAY_4PIX = 0x4,
+ TMDS_CTL2_DATA_DELAY_5PIX = 0x5,
+ TMDS_CTL2_DATA_DELAY_6PIX = 0x6,
+ TMDS_CTL2_DATA_DELAY_7PIX = 0x7,
+} TMDS_CTL2_DATA_DELAY;
+typedef enum TMDS_CTL2_DATA_INVERT {
+ TMDS_CTL2_DATA_NORMAL = 0x0,
+ TMDS_CTL2_DATA_INVERT_EN = 0x1,
+} TMDS_CTL2_DATA_INVERT;
+typedef enum TMDS_CTL2_DATA_MODULATION {
+ TMDS_CTL2_DATA_MODULATION_DISABLE = 0x0,
+ TMDS_CTL2_DATA_MODULATION_BIT0 = 0x1,
+ TMDS_CTL2_DATA_MODULATION_BIT1 = 0x2,
+ TMDS_CTL2_DATA_MODULATION_BIT2 = 0x3,
+} TMDS_CTL2_DATA_MODULATION;
+typedef enum TMDS_CTL2_PATTERN_OUT_EN {
+ TMDS_CTL2_PATTERN_OUT_DISABLE = 0x0,
+ TMDS_CTL2_PATTERN_OUT_ENABLE = 0x1,
+} TMDS_CTL2_PATTERN_OUT_EN;
+typedef enum TMDS_CTL3_DATA_DELAY {
+ TMDS_CTL3_DATA_DELAY_0PIX = 0x0,
+ TMDS_CTL3_DATA_DELAY_1PIX = 0x1,
+ TMDS_CTL3_DATA_DELAY_2PIX = 0x2,
+ TMDS_CTL3_DATA_DELAY_3PIX = 0x3,
+ TMDS_CTL3_DATA_DELAY_4PIX = 0x4,
+ TMDS_CTL3_DATA_DELAY_5PIX = 0x5,
+ TMDS_CTL3_DATA_DELAY_6PIX = 0x6,
+ TMDS_CTL3_DATA_DELAY_7PIX = 0x7,
+} TMDS_CTL3_DATA_DELAY;
+typedef enum TMDS_CTL3_DATA_INVERT {
+ TMDS_CTL3_DATA_NORMAL = 0x0,
+ TMDS_CTL3_DATA_INVERT_EN = 0x1,
+} TMDS_CTL3_DATA_INVERT;
+typedef enum TMDS_CTL3_DATA_MODULATION {
+ TMDS_CTL3_DATA_MODULATION_DISABLE = 0x0,
+ TMDS_CTL3_DATA_MODULATION_BIT0 = 0x1,
+ TMDS_CTL3_DATA_MODULATION_BIT1 = 0x2,
+ TMDS_CTL3_DATA_MODULATION_BIT2 = 0x3,
+} TMDS_CTL3_DATA_MODULATION;
+typedef enum TMDS_CTL3_PATTERN_OUT_EN {
+ TMDS_CTL3_PATTERN_OUT_DISABLE = 0x0,
+ TMDS_CTL3_PATTERN_OUT_ENABLE = 0x1,
+} TMDS_CTL3_PATTERN_OUT_EN;
+typedef enum TMDS_CTL3_DATA_SEL {
+ TMDS_CTL3_DATA_SEL0_RESERVED = 0x0,
+ TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 0x1,
+ TMDS_CTL3_DATA_SEL2_VSYNC = 0x2,
+ TMDS_CTL3_DATA_SEL3_RESERVED = 0x3,
+ TMDS_CTL3_DATA_SEL4_HSYNC = 0x4,
+ TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 0x5,
+ TMDS_CTL3_DATA_SEL8_BLANK_TIME = 0x6,
+ TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 0x7,
+} TMDS_CTL3_DATA_SEL;
+typedef enum DIG_FE_CNTL_SOURCE_SELECT {
+ DIG_FE_SOURCE_FROM_FMT0 = 0x0,
+ DIG_FE_SOURCE_FROM_FMT1 = 0x1,
+ DIG_FE_SOURCE_FROM_FMT2 = 0x2,
+ DIG_FE_SOURCE_FROM_FMT3 = 0x3,
+} DIG_FE_CNTL_SOURCE_SELECT;
+typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
+ DIG_FE_STEREOSYNC_FROM_FMT0 = 0x0,
+ DIG_FE_STEREOSYNC_FROM_FMT1 = 0x1,
+ DIG_FE_STEREOSYNC_FROM_FMT2 = 0x2,
+ DIG_FE_STEREOSYNC_FROM_FMT3 = 0x3,
+} DIG_FE_CNTL_STEREOSYNC_SELECT;
+typedef enum DIG_FIFO_READ_CLOCK_SRC {
+ DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0x0,
+ DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 0x1,
+} DIG_FIFO_READ_CLOCK_SRC;
+typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
+ DIG_OUTPUT_CRC_ON_LINK0 = 0x0,
+ DIG_OUTPUT_CRC_ON_LINK1 = 0x1,
+} DIG_OUTPUT_CRC_CNTL_LINK_SEL;
+typedef enum DIG_OUTPUT_CRC_DATA_SEL {
+ DIG_OUTPUT_CRC_FOR_FULLFRAME = 0x0,
+ DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 0x1,
+ DIG_OUTPUT_CRC_FOR_VBI = 0x2,
+ DIG_OUTPUT_CRC_FOR_AUDIO = 0x3,
+} DIG_OUTPUT_CRC_DATA_SEL;
+typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
+ DIG_IN_NORMAL_OPERATION = 0x0,
+ DIG_IN_DEBUG_MODE = 0x1,
+} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN;
+typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
+ DIG_10BIT_TEST_PATTERN = 0x0,
+ DIG_ALTERNATING_TEST_PATTERN = 0x1,
+} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL;
+typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
+ DIG_TEST_PATTERN_NORMAL = 0x0,
+ DIG_TEST_PATTERN_RANDOM = 0x1,
+} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN;
+typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
+ DIG_RANDOM_PATTERN_ENABLED = 0x0,
+ DIG_RANDOM_PATTERN_RESETED = 0x1,
+} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET;
+typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
+ DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0x0,
+ DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 0x1,
+} DIG_TEST_PATTERN_EXTERNAL_RESET_EN;
+typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
+ DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0x0,
+ DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 0x1,
+} DIG_RANDOM_PATTERN_SEED_RAN_PAT;
+typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL {
+ DIG_FIFO_USE_OVERWRITE_LEVEL = 0x0,
+ DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 0x1,
+} DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL;
+typedef enum DIG_FIFO_ERROR_ACK {
+ DIG_FIFO_ERROR_ACK_INT = 0x0,
+ DIG_FIFO_ERROR_NOT_ACK = 0x1,
+} DIG_FIFO_ERROR_ACK;
+typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE {
+ DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0x0,
+ DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 0x1,
+} DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE;
+typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX {
+ DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0x0,
+ DIG_FIFO_FORCE_RECOMP_MINMAX = 0x1,
+} DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX;
+typedef enum DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT {
+ DIG_DISPCLK_SWITCH_AT_EARLY_VBLANK = 0x0,
+ DIG_DISPCLK_SWITCH_AT_FIRST_HSYNC = 0x1,
+} DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT;
+typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK {
+ DIG_DISPCLK_SWITCH_ALLOWED_ACK_INT = 0x0,
+ DIG_DISPCLK_SWITCH_ALLOWED_INT_NOT_ACK = 0x1,
+} DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK;
+typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK {
+ DIG_DISPCLK_SWITCH_ALLOWED_MASK_INT = 0x0,
+ DIG_DISPCLK_SWITCH_ALLOWED_INT_UNMASK = 0x1,
+} DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK;
+typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
+ AFMT_INTERRUPT_DISABLE = 0x0,
+ AFMT_INTERRUPT_ENABLE = 0x1,
+} AFMT_INTERRUPT_STATUS_CHG_MASK;
+typedef enum HDMI_GC_AVMUTE {
+ HDMI_GC_AVMUTE_SET = 0x0,
+ HDMI_GC_AVMUTE_UNSET = 0x1,
+} HDMI_GC_AVMUTE;
+typedef enum HDMI_DEFAULT_PAHSE {
+ HDMI_DEFAULT_PHASE_IS_0 = 0x0,
+ HDMI_DEFAULT_PHASE_IS_1 = 0x1,
+} HDMI_DEFAULT_PAHSE;
+typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
+ AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS= 0x0,
+ AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 0x1,
+} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD;
+typedef enum AUDIO_LAYOUT_SELECT {
+ AUDIO_LAYOUT_0 = 0x0,
+ AUDIO_LAYOUT_1 = 0x1,
+} AUDIO_LAYOUT_SELECT;
+typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
+ AFMT_AUDIO_CRC_ONESHOT = 0x0,
+ AFMT_AUDIO_CRC_AUTO_RESTART = 0x1,
+} AFMT_AUDIO_CRC_CONTROL_CONT;
+typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
+ AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0x0,
+ AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 0x1,
+} AFMT_AUDIO_CRC_CONTROL_SOURCE;
+typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
+ AFMT_AUDIO_CRC_CH0_SIG = 0x0,
+ AFMT_AUDIO_CRC_CH1_SIG = 0x1,
+ AFMT_AUDIO_CRC_CH2_SIG = 0x2,
+ AFMT_AUDIO_CRC_CH3_SIG = 0x3,
+ AFMT_AUDIO_CRC_CH4_SIG = 0x4,
+ AFMT_AUDIO_CRC_CH5_SIG = 0x5,
+ AFMT_AUDIO_CRC_CH6_SIG = 0x6,
+ AFMT_AUDIO_CRC_CH7_SIG = 0x7,
+ AFMT_AUDIO_CRC_RESERVED = 0x8,
+ AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 0x9,
+} AFMT_AUDIO_CRC_CONTROL_CH_SEL;
+typedef enum AFMT_RAMP_CONTROL0_SIGN {
+ AFMT_RAMP_SIGNED = 0x0,
+ AFMT_RAMP_UNSIGNED = 0x1,
+} AFMT_RAMP_CONTROL0_SIGN;
+typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
+ AFMT_AUDIO_PACKET_SENT_DISABLED = 0x0,
+ AFMT_AUDIO_PACKET_SENT_ENABLED = 0x1,
+} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND;
+typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
+ AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED= 0x0,
+ AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 0x1,
+} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS;
+typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
+ AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0x0,
+ AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 0x1,
+} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE;
+typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
+ AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0x0,
+ AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 0x1,
+ AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 0x2,
+ AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 0x3,
+ AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 0x4,
+ AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 0x5,
+ AFMT_AUDIO_SRC_RESERVED = 0x6,
+} AFMT_AUDIO_SRC_CONTROL_SELECT;
+typedef enum DIG_BE_CNTL_MODE {
+ DIG_BE_DP_SST_MODE = 0x0,
+ DIG_BE_RESERVED1 = 0x1,
+ DIG_BE_TMDS_DVI_MODE = 0x2,
+ DIG_BE_TMDS_HDMI_MODE = 0x3,
+ DIG_BE_SDVO_RESERVED = 0x4,
+ DIG_BE_DP_MST_MODE = 0x5,
+ DIG_BE_RESERVED2 = 0x6,
+ DIG_BE_RESERVED3 = 0x7,
+} DIG_BE_CNTL_MODE;
+typedef enum DIG_BE_CNTL_HPD_SELECT {
+ DIG_BE_CNTL_HPD1 = 0x0,
+ DIG_BE_CNTL_HPD2 = 0x1,
+ DIG_BE_CNTL_HPD3 = 0x2,
+ DIG_BE_CNTL_HPD4 = 0x3,
+ DIG_BE_CNTL_HPD5 = 0x4,
+ DIG_BE_CNTL_HPD6 = 0x5,
+} DIG_BE_CNTL_HPD_SELECT;
+typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
+ LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0x0,
+ LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 0x1,
+} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT;
+typedef enum TMDS_SYNC_PHASE {
+ TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0x0,
+ TMDS_SYNC_PHASE_ON_FRAME_START = 0x1,
+} TMDS_SYNC_PHASE;
+typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
+ TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0x0,
+ TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 0x1,
+} TMDS_DATA_SYNCHRONIZATION_DSINTSEL;
+typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
+ TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0x0,
+ TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 0x1,
+} TMDS_TRANSMITTER_ENABLE_HPD_MASK;
+typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
+ TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0x0,
+ TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 0x1,
+} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK;
+typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
+ TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0x0,
+ TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 0x1,
+} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK;
+typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
+ TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0x0,
+ TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON= 0x1,
+ TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 0x2,
+ TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 0x3,
+} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK;
+typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
+ TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0x0,
+ TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 0x1,
+} TMDS_TRANSMITTER_CONTROL_IDSCKSELA;
+typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
+ TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0x0,
+ TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 0x1,
+} TMDS_TRANSMITTER_CONTROL_IDSCKSELB;
+typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
+ TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0x0,
+ TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 0x1,
+} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN;
+typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
+ TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0x0,
+ TMDS_TRANSMITTER_PLL_RST_ON_HPD = 0x1,
+} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK;
+typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
+ TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0x0,
+ TMDS_TRANSMITTER_TMCLK_FROM_PADS = 0x1,
+} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS;
+typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
+ TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0x0,
+ TMDS_TRANSMITTER_TDCLK_FROM_PADS = 0x1,
+} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS;
+typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
+ TMDS_TRANSMITTER_PLLSEL_BY_HW = 0x0,
+ TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 0x1,
+} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN;
+typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
+ TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0x0,
+ TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 0x1,
+} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA;
+typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
+ TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0x0,
+ TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 0x1,
+} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB;
+typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
+ TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0x0,
+ TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 0x1,
+ TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 0x2,
+ TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 0x3,
+} TMDS_REG_TEST_OUTPUTA_CNTLA;
+typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
+ TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0x0,
+ TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 0x1,
+ TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 0x2,
+ TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 0x3,
+} TMDS_REG_TEST_OUTPUTB_CNTLB;
+typedef enum DP_LINK_TRAINING_COMPLETE {
+ DP_LINK_TRAINING_NOT_COMPLETE = 0x0,
+ DP_LINK_TRAINING_ALREADY_COMPLETE = 0x1,
+} DP_LINK_TRAINING_COMPLETE;
+typedef enum DP_EMBEDDED_PANEL_MODE {
+ DP_EXTERNAL_PANEL = 0x0,
+ DP_EMBEDDED_PANEL = 0x1,
+} DP_EMBEDDED_PANEL_MODE;
+typedef enum DP_PIXEL_ENCODING {
+ DP_PIXEL_ENCODING_RGB444 = 0x0,
+ DP_PIXEL_ENCODING_YCBCR422 = 0x1,
+ DP_PIXEL_ENCODING_YCBCR444 = 0x2,
+ DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x3,
+ DP_PIXEL_ENCODING_Y_ONLY = 0x4,
+ DP_PIXEL_ENCODING_RESERVED = 0x5,
+} DP_PIXEL_ENCODING;
+typedef enum DP_DYN_RANGE {
+ DP_DYN_VESA_RANGE = 0x0,
+ DP_DYN_CEA_RANGE = 0x1,
+} DP_DYN_RANGE;
+typedef enum DP_YCBCR_RANGE {
+ DP_YCBCR_RANGE_BT601_5 = 0x0,
+ DP_YCBCR_RANGE_BT709_5 = 0x1,
+} DP_YCBCR_RANGE;
+typedef enum DP_COMPONENT_DEPTH {
+ DP_COMPONENT_DEPTH_6BPC = 0x0,
+ DP_COMPONENT_DEPTH_8BPC = 0x1,
+ DP_COMPONENT_DEPTH_10BPC = 0x2,
+ DP_COMPONENT_DEPTH_12BPC = 0x3,
+ DP_COMPONENT_DEPTH_16BPC = 0x4,
+ DP_COMPONENT_DEPTH_RESERVED = 0x5,
+} DP_COMPONENT_DEPTH;
+typedef enum DP_MSA_MISC0_OVERRIDE_ENABLE {
+ MSA_MISC0_OVERRIDE_DISABLE = 0x0,
+ MSA_MISC0_OVERRIDE_ENABLE = 0x1,
+} DP_MSA_MISC0_OVERRIDE_ENABLE;
+typedef enum DP_UDI_LANES {
+ DP_UDI_1_LANE = 0x0,
+ DP_UDI_2_LANES = 0x1,
+ DP_UDI_LANES_RESERVED = 0x2,
+ DP_UDI_4_LANES = 0x3,
+} DP_UDI_LANES;
+typedef enum DP_VID_STREAM_DIS_DEFER {
+ DP_VID_STREAM_DIS_NO_DEFER = 0x0,
+ DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 0x1,
+ DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 0x2,
+} DP_VID_STREAM_DIS_DEFER;
+typedef enum DP_STEER_OVERFLOW_ACK {
+ DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0x0,
+ DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 0x1,
+} DP_STEER_OVERFLOW_ACK;
+typedef enum DP_STEER_OVERFLOW_MASK {
+ DP_STEER_OVERFLOW_MASKED = 0x0,
+ DP_STEER_OVERFLOW_UNMASK = 0x1,
+} DP_STEER_OVERFLOW_MASK;
+typedef enum DP_TU_OVERFLOW_ACK {
+ DP_TU_OVERFLOW_ACK_NO_EFFECT = 0x0,
+ DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 0x1,
+} DP_TU_OVERFLOW_ACK;
+typedef enum DP_VID_TIMING_MODE {
+ DP_VID_TIMING_MODE_ASYNC = 0x0,
+ DP_VID_TIMING_MODE_SYNC = 0x1,
+} DP_VID_TIMING_MODE;
+typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
+ DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0x0,
+ DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 0x1,
+} DP_VID_M_N_DOUBLE_BUFFER_MODE;
+typedef enum DP_VID_M_N_GEN_EN {
+ DP_VID_M_N_PROGRAMMED_VIA_REG = 0x0,
+ DP_VID_M_N_CALC_AUTO = 0x1,
+} DP_VID_M_N_GEN_EN;
+typedef enum DP_VID_ENHANCED_FRAME_MODE {
+ VID_NORMAL_FRAME_MODE = 0x0,
+ VID_ENHANCED_MODE = 0x1,
+} DP_VID_ENHANCED_FRAME_MODE;
+typedef enum DP_VID_MSA_TOP_FIELD_MODE {
+ DP_TOP_FIELD_ONLY = 0x0,
+ DP_TOP_PLUS_BOTTOM_FIELD = 0x1,
+} DP_VID_MSA_TOP_FIELD_MODE;
+typedef enum DP_VID_VBID_FIELD_POL {
+ DP_VID_VBID_FIELD_POL_NORMAL = 0x0,
+ DP_VID_VBID_FIELD_POL_INV = 0x1,
+} DP_VID_VBID_FIELD_POL;
+typedef enum DP_VID_STREAM_DISABLE_ACK {
+ ID_STREAM_DISABLE_NO_ACK = 0x0,
+ ID_STREAM_DISABLE_ACKED = 0x1,
+} DP_VID_STREAM_DISABLE_ACK;
+typedef enum DP_VID_STREAM_DISABLE_MASK {
+ VID_STREAM_DISABLE_MASKED = 0x0,
+ VID_STREAM_DISABLE_UNMASK = 0x1,
+} DP_VID_STREAM_DISABLE_MASK;
+typedef enum DPHY_ATEST_SEL_LANE0 {
+ DPHY_ATEST_LANE0_PRBS_PATTERN = 0x0,
+ DPHY_ATEST_LANE0_REG_PATTERN = 0x1,
+} DPHY_ATEST_SEL_LANE0;
+typedef enum DPHY_ATEST_SEL_LANE1 {
+ DPHY_ATEST_LANE1_PRBS_PATTERN = 0x0,
+ DPHY_ATEST_LANE1_REG_PATTERN = 0x1,
+} DPHY_ATEST_SEL_LANE1;
+typedef enum DPHY_ATEST_SEL_LANE2 {
+ DPHY_ATEST_LANE2_PRBS_PATTERN = 0x0,
+ DPHY_ATEST_LANE2_REG_PATTERN = 0x1,
+} DPHY_ATEST_SEL_LANE2;
+typedef enum DPHY_ATEST_SEL_LANE3 {
+ DPHY_ATEST_LANE3_PRBS_PATTERN = 0x0,
+ DPHY_ATEST_LANE3_REG_PATTERN = 0x1,
+} DPHY_ATEST_SEL_LANE3;
+typedef enum DPHY_BYPASS {
+ DPHY_8B10B_OUTPUT = 0x0,
+ DPHY_DBG_OUTPUT = 0x1,
+} DPHY_BYPASS;
+typedef enum DPHY_SKEW_BYPASS {
+ DPHY_WITH_SKEW = 0x0,
+ DPHY_NO_SKEW = 0x1,
+} DPHY_SKEW_BYPASS;
+typedef enum DPHY_TRAINING_PATTERN_SEL {
+ DPHY_TRAINING_PATTERN_1 = 0x0,
+ DPHY_TRAINING_PATTERN_2 = 0x1,
+ DPHY_TRAINING_PATTERN_3 = 0x2,
+} DPHY_TRAINING_PATTERN_SEL;
+typedef enum DPHY_8B10B_RESET {
+ DPHY_8B10B_NOT_RESET = 0x0,
+ DPHY_8B10B_RESETET = 0x1,
+} DPHY_8B10B_RESET;
+typedef enum DP_DPHY_8B10B_EXT_DISP {
+ DP_DPHY_8B10B_EXT_DISP_ZERO = 0x0,
+ DP_DPHY_8B10B_EXT_DISP_ONE = 0x1,
+} DP_DPHY_8B10B_EXT_DISP;
+typedef enum DPHY_8B10B_CUR_DISP {
+ DPHY_8B10B_CUR_DISP_ZERO = 0x0,
+ DPHY_8B10B_CUR_DISP_ONE = 0x1,
+} DPHY_8B10B_CUR_DISP;
+typedef enum DPHY_PRBS_EN {
+ DPHY_PRBS_DISABLE = 0x0,
+ DPHY_PRBS_ENABLE = 0x1,
+} DPHY_PRBS_EN;
+typedef enum DPHY_PRBS_SEL {
+ DPHY_PRBS7_SELECTED = 0x0,
+ DPHY_PRBS23_SELECTED = 0x1,
+ DPHY_PRBS11_SELECTED = 0x2,
+} DPHY_PRBS_SEL;
+typedef enum DPHY_LOAD_BS_COUNT_START {
+ DPHY_LOAD_BS_COUNT_STARTED = 0x0,
+ DPHY_LOAD_BS_COUNT_NOT_STARTED = 0x1,
+} DPHY_LOAD_BS_COUNT_START;
+typedef enum DPHY_CRC_EN {
+ DPHY_CRC_DISABLED = 0x0,
+ DPHY_CRC_ENABLED = 0x1,
+} DPHY_CRC_EN;
+typedef enum DPHY_CRC_CONT_EN {
+ DPHY_CRC_ONE_SHOT = 0x0,
+ DPHY_CRC_CONTINUOUS = 0x1,
+} DPHY_CRC_CONT_EN;
+typedef enum DPHY_CRC_FIELD {
+ DPHY_CRC_START_FROM_TOP_FIELD = 0x0,
+ DPHY_CRC_START_FROM_BOTTOM_FIELD = 0x1,
+} DPHY_CRC_FIELD;
+typedef enum DPHY_CRC_SEL {
+ DPHY_CRC_LANE0_SELECTED = 0x0,
+ DPHY_CRC_LANE1_SELECTED = 0x1,
+ DPHY_CRC_LANE2_SELECTED = 0x2,
+ DPHY_CRC_LANE3_SELECTED = 0x3,
+} DPHY_CRC_SEL;
+typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
+ DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0x0,
+ DPHY_FAST_TRAINING_CAPABLE = 0x1,
+} DPHY_RX_FAST_TRAINING_CAPABLE;
+typedef enum DP_SEC_COLLISION_ACK {
+ DP_SEC_COLLISION_ACK_NO_EFFECT = 0x0,
+ DP_SEC_COLLISION_ACK_CLR_FLAG = 0x1,
+} DP_SEC_COLLISION_ACK;
+typedef enum DP_SEC_AUDIO_MUTE {
+ DP_SEC_AUDIO_MUTE_HW_CTRL = 0x0,
+ DP_SEC_AUDIO_MUTE_SW_CTRL = 0x1,
+} DP_SEC_AUDIO_MUTE;
+typedef enum DP_SEC_TIMESTAMP_MODE {
+ DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0x0,
+ DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 0x1,
+} DP_SEC_TIMESTAMP_MODE;
+typedef enum DP_SEC_ASP_PRIORITY {
+ DP_SEC_ASP_LOW_PRIORITY = 0x0,
+ DP_SEC_ASP_HIGH_PRIORITY = 0x1,
+} DP_SEC_ASP_PRIORITY;
+typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
+ DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0x0,
+ DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x1,
+} DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE;
+typedef enum DP_MSE_SAT_UPDATE_ACT {
+ DP_MSE_SAT_UPDATE_NO_ACTION = 0x0,
+ DP_MSE_SAT_UPDATE_WITH_TRIGGER = 0x1,
+ DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 0x2,
+} DP_MSE_SAT_UPDATE_ACT;
+typedef enum DP_MSE_LINK_LINE {
+ DP_MSE_LINK_LINE_32_MTP_LONG = 0x0,
+ DP_MSE_LINK_LINE_64_MTP_LONG = 0x1,
+ DP_MSE_LINK_LINE_128_MTP_LONG = 0x2,
+ DP_MSE_LINK_LINE_256_MTP_LONG = 0x3,
+} DP_MSE_LINK_LINE;
+typedef enum DP_MSE_BLANK_CODE {
+ DP_MSE_BLANK_CODE_SF_FILLED = 0x0,
+ DP_MSE_BLANK_CODE_ZERO_FILLED = 0x1,
+} DP_MSE_BLANK_CODE;
+typedef enum DP_MSE_TIMESTAMP_MODE {
+ DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0x0,
+ DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 0x1,
+} DP_MSE_TIMESTAMP_MODE;
+typedef enum DP_MSE_ZERO_ENCODER {
+ DP_MSE_NOT_ZERO_FE_ENCODER = 0x0,
+ DP_MSE_ZERO_FE_ENCODER = 0x1,
+} DP_MSE_ZERO_ENCODER;
+typedef enum DP_MSE_OUTPUT_DPDBG_DATA {
+ DP_MSE_OUTPUT_DPDBG_DATA_DIS = 0x0,
+ DP_MSE_OUTPUT_DPDBG_DATA_EN = 0x1,
+} DP_MSE_OUTPUT_DPDBG_DATA;
+typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
+ DP_DPHY_HBR2_PASS_THROUGH = 0x0,
+ DP_DPHY_HBR2_PATTERN_1 = 0x1,
+ DP_DPHY_HBR2_PATTERN_2_NEG = 0x2,
+ DP_DPHY_HBR2_PATTERN_3 = 0x3,
+ DP_DPHY_HBR2_PATTERN_2_POS = 0x6,
+} DP_DPHY_HBR2_PATTERN_CONTROL_MODE;
+typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
+ DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0x0,
+ DPHY_CRC_MST_PHASE_ERROR_ACKED = 0x1,
+} DPHY_CRC_MST_PHASE_ERROR_ACK;
+typedef enum DPHY_SW_FAST_TRAINING_START {
+ DPHY_SW_FAST_TRAINING_NOT_STARTED = 0x0,
+ DPHY_SW_FAST_TRAINING_STARTED = 0x1,
+} DPHY_SW_FAST_TRAINING_START;
+typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
+ DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED= 0x0,
+ DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x1,
+} DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN;
+typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
+ DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0x0,
+ DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 0x1,
+} DP_DPHY_FAST_TRAINING_COMPLETE_MASK;
+typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
+ DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0x0,
+ DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 0x1,
+} DP_DPHY_FAST_TRAINING_COMPLETE_ACK;
+typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
+ MSA_V_TIMING_OVERRIDE_DISABLED = 0x0,
+ MSA_V_TIMING_OVERRIDE_ENABLED = 0x1,
+} DP_MSA_V_TIMING_OVERRIDE_EN;
+typedef enum DP_SEC_GSP0_PRIORITY {
+ SEC_GSP0_PRIORITY_LOW = 0x0,
+ SEC_GSP0_PRIORITY_HIGH = 0x1,
+} DP_SEC_GSP0_PRIORITY;
+typedef enum DP_SEC_GSP0_SEND {
+ NOT_SENT = 0x0,
+ FORCE_SENT = 0x1,
+} DP_SEC_GSP0_SEND;
+typedef enum DP_AUX_CONTROL_HPD_SEL {
+ DP_AUX_CONTROL_HPD1_SELECTED = 0x0,
+ DP_AUX_CONTROL_HPD2_SELECTED = 0x1,
+ DP_AUX_CONTROL_HPD3_SELECTED = 0x2,
+ DP_AUX_CONTROL_HPD4_SELECTED = 0x3,
+ DP_AUX_CONTROL_HPD5_SELECTED = 0x4,
+ DP_AUX_CONTROL_HPD6_SELECTED = 0x5,
+} DP_AUX_CONTROL_HPD_SEL;
+typedef enum DP_AUX_CONTROL_TEST_MODE {
+ DP_AUX_CONTROL_TEST_MODE_DISABLE = 0x0,
+ DP_AUX_CONTROL_TEST_MODE_ENABLE = 0x1,
+} DP_AUX_CONTROL_TEST_MODE;
+typedef enum DP_AUX_SW_CONTROL_SW_GO {
+ DP_AUX_SW_CONTROL_SW__NOT_GO = 0x0,
+ DP_AUX_SW_CONTROL_SW__GO = 0x1,
+} DP_AUX_SW_CONTROL_SW_GO;
+typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
+ DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0x0,
+ DP_AUX_SW_CONTROL_LS_READ__TRIG = 0x1,
+} DP_AUX_SW_CONTROL_LS_READ_TRIG;
+typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
+ DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0x0,
+ DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 0x1,
+ DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 0x2,
+ DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 0x3,
+} DP_AUX_ARB_CONTROL_ARB_PRIORITY;
+typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
+ DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0x0,
+ DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 0x1,
+} DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ;
+typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
+ DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x0,
+ DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 0x1,
+} DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG;
+typedef enum DP_AUX_INT_ACK {
+ DP_AUX_INT__NOT_ACK = 0x0,
+ DP_AUX_INT__ACK = 0x1,
+} DP_AUX_INT_ACK;
+typedef enum DP_AUX_LS_UPDATE_ACK {
+ DP_AUX_INT_LS_UPDATE_NOT_ACK = 0x0,
+ DP_AUX_INT_LS_UPDATE_ACK = 0x1,
+} DP_AUX_LS_UPDATE_ACK;
+typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
+ DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK= 0x0,
+ DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF= 0x1,
+} DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL;
+typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
+ DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x0,
+ DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x1,
+ DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x2,
+ DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x3,
+} DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE;
+typedef enum DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN {
+ DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US = 0x0,
+ DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US = 0x1,
+ DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US = 0x2,
+ DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US = 0x3,
+ DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US = 0x4,
+ DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US = 0x5,
+ DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US = 0x6,
+ DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US = 0x7,
+} DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN;
+typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
+ DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x0,
+ DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US= 0x1,
+ DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US= 0x2,
+ DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US= 0x3,
+ DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US= 0x4,
+ DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US= 0x5,
+} DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY;
+typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
+ DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x0,
+ DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x1,
+ DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x2,
+ DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD= 0x3,
+ DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD= 0x4,
+ DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD= 0x5,
+ DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD= 0x6,
+ DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD= 0x7,
+} DP_AUX_DPHY_RX_CONTROL_START_WINDOW;
+typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
+ DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD= 0x0,
+ DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD= 0x1,
+ DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD= 0x2,
+ DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD= 0x3,
+ DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD= 0x4,
+ DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD= 0x5,
+ DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD= 0x6,
+ DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD= 0x7,
+} DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW;
+typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
+ DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES= 0x0,
+ DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES= 0x1,
+ DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES= 0x2,
+ DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED= 0x3,
+} DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN;
+typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
+ DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x0,
+ DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x1,
+} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT;
+typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
+ DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START= 0x0,
+ DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START= 0x1,
+} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START;
+typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
+ DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP= 0x0,
+ DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP= 0x1,
+} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP;
+typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
+ DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS= 0x0,
+ DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS= 0x1,
+ DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS= 0x2,
+ DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS= 0x3,
+} DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN;
+typedef enum DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN {
+ DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US = 0x0,
+ DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US = 0x1,
+ DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US = 0x2,
+ DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US = 0x3,
+ DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US = 0x4,
+ DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US = 0x5,
+ DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US = 0x6,
+ DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US = 0x7,
+} DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN;
+typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
+ DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0x0,
+ DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 0x1,
+ DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 0x2,
+ DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 0x3,
+ DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 0x4,
+ DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 0x5,
+ DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 0x6,
+ DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 0x7,
+} DP_AUX_DPHY_RX_DETECTION_THRESHOLD;
+typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
+ DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX= 0x0,
+ DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX= 0x1,
+} DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ;
+typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
+ DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US= 0x0,
+ DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US= 0x1,
+ DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US= 0x2,
+ DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US= 0x3,
+} DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW;
+typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
+ DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS= 0x0,
+ DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS= 0x1,
+ DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS= 0x2,
+ DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED= 0x3,
+} DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT;
+typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
+ DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0= 0x0,
+ DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64= 0x1,
+ DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128= 0x2,
+ DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256= 0x3,
+} DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN;
+typedef enum DP_AUX_ERR_OCCURRED_ACK {
+ DP_AUX_ERR_OCCURRED__NOT_ACK = 0x0,
+ DP_AUX_ERR_OCCURRED__ACK = 0x1,
+} DP_AUX_ERR_OCCURRED_ACK;
+typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
+ DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0x0,
+ DP_AUX_POTENTIAL_ERR_REACHED__ACK = 0x1,
+} DP_AUX_POTENTIAL_ERR_REACHED_ACK;
+typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
+ ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x0,
+ ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 0x1,
+} DP_AUX_DEFINITE_ERR_REACHED_ACK;
+typedef enum DP_AUX_RESET {
+ DP_AUX_RESET_DEASSERTED = 0x0,
+ DP_AUX_RESET_ASSERTED = 0x1,
+} DP_AUX_RESET;
+typedef enum DP_AUX_RESET_DONE {
+ DP_AUX_RESET_SEQUENCE_NOT_DONE = 0x0,
+ DP_AUX_RESET_SEQUENCE_DONE = 0x1,
+} DP_AUX_RESET_DONE;
+typedef enum FMT_CONTROL_PIXEL_ENCODING {
+ FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x0,
+ FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 0x1,
+} FMT_CONTROL_PIXEL_ENCODING;
+typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
+ FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0x0,
+ FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 0x1,
+} FMT_CONTROL_SUBSAMPLING_MODE;
+typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
+ FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x0,
+ FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x1,
+} FMT_CONTROL_SUBSAMPLING_ORDER;
+typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
+ FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x0,
+ FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x1,
+} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;
+typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
+ FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x0,
+ FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x1,
+ FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x2,
+} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;
+typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
+ FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x0,
+ FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x1,
+ FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x2,
+} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;
+typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
+ FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP= 0x0,
+ FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP= 0x1,
+ FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP= 0x2,
+} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;
+typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
+ FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x0,
+ FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x1,
+} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;
+typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
+ FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0x0,
+ FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 0x1,
+ FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x2,
+ FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x3,
+} FMT_BIT_DEPTH_CONTROL_25FRC_SEL;
+typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
+ FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0x0,
+ FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 0x1,
+ FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x2,
+ FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 0x3,
+} FMT_BIT_DEPTH_CONTROL_50FRC_SEL;
+typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
+ FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0x0,
+ FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 0x1,
+ FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x2,
+ FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x3,
+} FMT_BIT_DEPTH_CONTROL_75FRC_SEL;
+typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT {
+ FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN= 0x0,
+ FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN= 0x1,
+} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT;
+typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
+ FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR= 0x0,
+ FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB= 0x1,
+} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;
+typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
+ FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0x0,
+ FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 0x1,
+ FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x2,
+ FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED0 = 0x3,
+ FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 0x4,
+ FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 0x5,
+ FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 0x6,
+ FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x7,
+} FMT_CLAMP_CNTL_COLOR_FORMAT;
+typedef enum FMT_CRC_CNTL_CONT_EN {
+ FMT_CRC_CNTL_CONT_EN_ONE_SHOT = 0x0,
+ FMT_CRC_CNTL_CONT_EN_CONT = 0x1,
+} FMT_CRC_CNTL_CONT_EN;
+typedef enum FMT_CRC_CNTL_INCLUDE_OVERSCAN {
+ FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE = 0x0,
+ FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE = 0x1,
+} FMT_CRC_CNTL_INCLUDE_OVERSCAN;
+typedef enum FMT_CRC_CNTL_ONLY_BLANKB {
+ FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD = 0x0,
+ FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK = 0x1,
+} FMT_CRC_CNTL_ONLY_BLANKB;
+typedef enum FMT_CRC_CNTL_PSR_MODE_ENABLE {
+ FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL = 0x0,
+ FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC = 0x1,
+} FMT_CRC_CNTL_PSR_MODE_ENABLE;
+typedef enum FMT_CRC_CNTL_INTERLACE_MODE {
+ FMT_CRC_CNTL_INTERLACE_MODE_TOP = 0x0,
+ FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM = 0x1,
+ FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM = 0x2,
+ FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH = 0x3,
+} FMT_CRC_CNTL_INTERLACE_MODE;
+typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE {
+ FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL = 0x0,
+ FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN = 0x1,
+} FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE;
+typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT {
+ FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN = 0x0,
+ FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD = 0x1,
+} FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT;
+typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
+ FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0x0,
+ FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 0x1,
+ FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 0x2,
+ FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 0x3,
+} FMT_DEBUG_CNTL_COLOR_SELECT;
+typedef enum FMT_SPATIAL_DITHER_MODE {
+ FMT_SPATIAL_DITHER_MODE_0 = 0x0,
+ FMT_SPATIAL_DITHER_MODE_1 = 0x1,
+ FMT_SPATIAL_DITHER_MODE_2 = 0x2,
+ FMT_SPATIAL_DITHER_MODE_3 = 0x3,
+} FMT_SPATIAL_DITHER_MODE;
+typedef enum FMT_STEREOSYNC_OVR_POL {
+ FMT_STEREOSYNC_OVR_POL_INVERTED = 0x0,
+ FMT_STEREOSYNC_OVR_POL_NOT_INVERTED = 0x1,
+} FMT_STEREOSYNC_OVR_POL;
+typedef enum FMT_DYNAMIC_EXP_MODE {
+ FMT_DYNAMIC_EXP_MODE_10to12 = 0x0,
+ FMT_DYNAMIC_EXP_MODE_8to12 = 0x1,
+} FMT_DYNAMIC_EXP_MODE;
+typedef enum LB_DATA_FORMAT_PIXEL_DEPTH {
+ LB_DATA_FORMAT_PIXEL_DEPTH_30BPP = 0x0,
+ LB_DATA_FORMAT_PIXEL_DEPTH_24BPP = 0x1,
+ LB_DATA_FORMAT_PIXEL_DEPTH_18BPP = 0x2,
+ LB_DATA_FORMAT_PIXEL_DEPTH_36BPP = 0x3,
+} LB_DATA_FORMAT_PIXEL_DEPTH;
+typedef enum LB_DATA_FORMAT_PIXEL_EXPAN_MODE {
+ LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION= 0x0,
+ LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION= 0x1,
+} LB_DATA_FORMAT_PIXEL_EXPAN_MODE;
+typedef enum LB_DATA_FORMAT_PIXEL_REDUCE_MODE {
+ LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION = 0x0,
+ LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING = 0x1,
+} LB_DATA_FORMAT_PIXEL_REDUCE_MODE;
+typedef enum LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH {
+ LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP = 0x0,
+ LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP = 0x1,
+} LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH;
+typedef enum LB_DATA_FORMAT_INTERLEAVE_EN {
+ LB_DATA_FORMAT_INTERLEAVE_DISABLE = 0x0,
+ LB_DATA_FORMAT_INTERLEAVE_ENABLE = 0x1,
+} LB_DATA_FORMAT_INTERLEAVE_EN;
+typedef enum LB_DATA_FORMAT_REQUEST_MODE {
+ LB_DATA_FORMAT_REQUEST_MODE_NORMAL = 0x0,
+ LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE = 0x1,
+} LB_DATA_FORMAT_REQUEST_MODE;
+typedef enum LB_DATA_FORMAT_ALPHA_EN {
+ LB_DATA_FORMAT_ALPHA_DISABLE = 0x0,
+ LB_DATA_FORMAT_ALPHA_ENABLE = 0x1,
+} LB_DATA_FORMAT_ALPHA_EN;
+typedef enum LB_VLINE_START_END_VLINE_INV {
+ LB_VLINE_START_END_VLINE_NORMAL = 0x0,
+ LB_VLINE_START_END_VLINE_INVERSE = 0x1,
+} LB_VLINE_START_END_VLINE_INV;
+typedef enum LB_VLINE2_START_END_VLINE2_INV {
+ LB_VLINE2_START_END_VLINE2_NORMAL = 0x0,
+ LB_VLINE2_START_END_VLINE2_INVERSE = 0x1,
+} LB_VLINE2_START_END_VLINE2_INV;
+typedef enum LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK {
+ LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE = 0x0,
+ LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE = 0x1,
+} LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK;
+typedef enum LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK {
+ LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE = 0x0,
+ LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE = 0x1,
+} LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK;
+typedef enum LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK {
+ LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE = 0x0,
+ LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE = 0x1,
+} LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK;
+typedef enum LB_VLINE_STATUS_VLINE_ACK {
+ LB_VLINE_STATUS_VLINE_NORMAL = 0x0,
+ LB_VLINE_STATUS_VLINE_CLEAR = 0x1,
+} LB_VLINE_STATUS_VLINE_ACK;
+typedef enum LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE {
+ LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED = 0x0,
+ LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED = 0x1,
+} LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE;
+typedef enum LB_VLINE2_STATUS_VLINE2_ACK {
+ LB_VLINE2_STATUS_VLINE2_NORMAL = 0x0,
+ LB_VLINE2_STATUS_VLINE2_CLEAR = 0x1,
+} LB_VLINE2_STATUS_VLINE2_ACK;
+typedef enum LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE {
+ LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED= 0x0,
+ LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED= 0x1,
+} LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE;
+typedef enum LB_VBLANK_STATUS_VBLANK_ACK {
+ LB_VBLANK_STATUS_VBLANK_NORMAL = 0x0,
+ LB_VBLANK_STATUS_VBLANK_CLEAR = 0x1,
+} LB_VBLANK_STATUS_VBLANK_ACK;
+typedef enum LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE {
+ LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED= 0x0,
+ LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED= 0x1,
+} LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE;
+typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL {
+ LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE = 0x0,
+ LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK= 0x1,
+ LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET= 0x2,
+ LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET= 0x3,
+} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL;
+typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 {
+ LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK = 0x0,
+ LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC = 0x1,
+} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2;
+typedef enum LB_SYNC_RESET_SEL_LB_SYNC_DURATION {
+ LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS = 0x0,
+ LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS = 0x1,
+ LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS = 0x2,
+ LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS = 0x3,
+} LB_SYNC_RESET_SEL_LB_SYNC_DURATION;
+typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN {
+ LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE = 0x0,
+ LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE = 0x1,
+} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN;
+typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN {
+ LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE= 0x0,
+ LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE= 0x1,
+} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN;
+typedef enum LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK {
+ LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL = 0x0,
+ LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET = 0x1,
+} LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK;
+typedef enum LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK {
+ LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL = 0x0,
+ LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET = 0x1,
+} LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK;
+typedef enum LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE {
+ LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP = 0x2,
+ LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP= 0x3,
+} LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE;
+typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET {
+ LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL= 0x0,
+ LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE= 0x1,
+} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET;
+typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK {
+ LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0= 0x0,
+ LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1= 0x1,
+} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK;
+typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE {
+ LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT= 0x0,
+ LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG= 0x1,
+ LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE= 0x2,
+} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE;
+typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE {
+ LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE= 0x0,
+ LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN = 0x1,
+} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE;
+typedef enum LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE {
+ ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER= 0x1,
+ ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE= 0x2,
+} LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE;
+typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL {
+ LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0= 0x0,
+ LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1= 0x1,
+} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL;
+typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE {
+ LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE= 0x0,
+ LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE= 0x1,
+} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE;
+typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO {
+ LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO= 0x0,
+ LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO= 0x1,
+} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO;
+typedef enum LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN {
+ LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0= 0x0,
+ LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1= 0x1,
+} LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN;
+typedef enum LBV_PIXEL_DEPTH {
+ PIXEL_DEPTH_30BPP = 0x0,
+ PIXEL_DEPTH_24BPP = 0x1,
+ PIXEL_DEPTH_18BPP = 0x2,
+ PIXEL_DEPTH_38BPP = 0x3,
+} LBV_PIXEL_DEPTH;
+typedef enum LBV_PIXEL_EXPAN_MODE {
+ PIXEL_EXPAN_MODE_ZERO_EXP = 0x0,
+ PIXEL_EXPAN_MODE_DYN_EXP = 0x1,
+} LBV_PIXEL_EXPAN_MODE;
+typedef enum LBV_INTERLEAVE_EN {
+ INTERLEAVE_DIS = 0x0,
+ INTERLEAVE_EN = 0x1,
+} LBV_INTERLEAVE_EN;
+typedef enum LBV_PIXEL_REDUCE_MODE {
+ PIXEL_REDUCE_MODE_TRUNCATION = 0x0,
+ PIXEL_REDUCE_MODE_ROUNDING = 0x1,
+} LBV_PIXEL_REDUCE_MODE;
+typedef enum LBV_DYNAMIC_PIXEL_DEPTH {
+ DYNAMIC_PIXEL_DEPTH_36BPP = 0x0,
+ DYNAMIC_PIXEL_DEPTH_30BPP = 0x1,
+} LBV_DYNAMIC_PIXEL_DEPTH;
+typedef enum LBV_DITHER_EN {
+ DITHER_DIS = 0x0,
+ DITHER_EN = 0x1,
+} LBV_DITHER_EN;
+typedef enum LBV_DOWNSCALE_PREFETCH_EN {
+ DOWNSCALE_PREFETCH_DIS = 0x0,
+ DOWNSCALE_PREFETCH_EN = 0x1,
+} LBV_DOWNSCALE_PREFETCH_EN;
+typedef enum LBV_MEMORY_CONFIG {
+ MEMORY_CONFIG_0 = 0x0,
+ MEMORY_CONFIG_1 = 0x1,
+ MEMORY_CONFIG_2 = 0x2,
+ MEMORY_CONFIG_3 = 0x3,
+} LBV_MEMORY_CONFIG;
+typedef enum LBV_SYNC_RESET_SEL2 {
+ SYNC_RESET_SEL2_VBLANK = 0x0,
+ SYNC_RESET_SEL2_VSYNC = 0x1,
+} LBV_SYNC_RESET_SEL2;
+typedef enum LBV_SYNC_DURATION {
+ SYNC_DURATION_16 = 0x0,
+ SYNC_DURATION_32 = 0x1,
+ SYNC_DURATION_64 = 0x2,
+ SYNC_DURATION_128 = 0x3,
+} LBV_SYNC_DURATION;
+typedef enum SCL_C_RAM_TAP_PAIR_IDX {
+ SCL_C_RAM_TAP_PAIR_ID0 = 0x0,
+ SCL_C_RAM_TAP_PAIR_ID1 = 0x1,
+ SCL_C_RAM_TAP_PAIR_ID2 = 0x2,
+ SCL_C_RAM_TAP_PAIR_ID3 = 0x3,
+ SCL_C_RAM_TAP_PAIR_ID4 = 0x4,
+} SCL_C_RAM_TAP_PAIR_IDX;
+typedef enum SCL_C_RAM_PHASE {
+ SCL_C_RAM_PHASE_0 = 0x0,
+ SCL_C_RAM_PHASE_1 = 0x1,
+ SCL_C_RAM_PHASE_2 = 0x2,
+ SCL_C_RAM_PHASE_3 = 0x3,
+ SCL_C_RAM_PHASE_4 = 0x4,
+ SCL_C_RAM_PHASE_5 = 0x5,
+ SCL_C_RAM_PHASE_6 = 0x6,
+ SCL_C_RAM_PHASE_7 = 0x7,
+ SCL_C_RAM_PHASE_8 = 0x8,
+} SCL_C_RAM_PHASE;
+typedef enum SCL_C_RAM_FILTER_TYPE {
+ SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT = 0x0,
+ SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT = 0x1,
+ SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT = 0x2,
+ SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT = 0x3,
+ SCL_C_RAM_FILTER_TYPE_VERT_ALPHA_LUT = 0x4,
+ SCL_C_RAM_FILTER_TYPE_HORI_ALPHA_LUT = 0x5,
+} SCL_C_RAM_FILTER_TYPE;
+typedef enum SCL_MODE_SEL {
+ SCL_MODE_SCL_BYPASS = 0x0,
+ SCL_MODE_RGB_SCALING = 0x1,
+ SCL_MODE_YCBCR_SCALING = 0x2,
+} SCL_MODE_SEL;
+typedef enum SCL_PSCL_EN {
+ SCL_PSCL_DISABLE = 0x0,
+ SCL_PSCL_ENANBLE = 0x1,
+} SCL_PSCL_EN;
+typedef enum SCL_V_NUM_OF_TAPS {
+ SCL_V_NUM_OF_TAPS_1 = 0x0,
+ SCL_V_NUM_OF_TAPS_2 = 0x1,
+ SCL_V_NUM_OF_TAPS_3 = 0x2,
+ SCL_V_NUM_OF_TAPS_4 = 0x3,
+ SCL_V_NUM_OF_TAPS_5 = 0x4,
+ SCL_V_NUM_OF_TAPS_6 = 0x5,
+} SCL_V_NUM_OF_TAPS;
+typedef enum SCL_H_NUM_OF_TAPS {
+ SCL_H_NUM_OF_TAPS_1 = 0x0,
+ SCL_H_NUM_OF_TAPS_2 = 0x1,
+ SCL_H_NUM_OF_TAPS_4 = 0x3,
+ SCL_H_NUM_OF_TAPS_6 = 0x5,
+ SCL_H_NUM_OF_TAPS_8 = 0x7,
+ SCL_H_NUM_OF_TAPS_10 = 0x9,
+} SCL_H_NUM_OF_TAPS;
+typedef enum SCL_BOUNDARY_MODE {
+ SCL_BOUNDARY_MODE_BLACK = 0x0,
+ SCL_BOUNDARY_MODE_EDGE = 0x1,
+} SCL_BOUNDARY_MODE;
+typedef enum SCL_EARLY_EOL_MOD {
+ SCL_EARLY_EOL_MODE_CRTC = 0x0,
+ SCL_EARLY_EOL_MODE_INTERNAL = 0x1,
+} SCL_EARLY_EOL_MOD;
+typedef enum SCL_BYPASS_MODE {
+ SCL_BYPASS_MODE_MC_MR = 0x0,
+ SCL_BYPASS_MODE_AC_NR = 0x1,
+ SCL_BYPASS_MODE_AC_AR = 0x2,
+ SCL_BYPASS_MODE_RESERVED = 0x3,
+} SCL_BYPASS_MODE;
+typedef enum SCL_V_MANUAL_REPLICATE_FACTOR {
+ SCL_V_MANUAL_REPLICATE_FACTOR_1 = 0x0,
+ SCL_V_MANUAL_REPLICATE_FACTOR_2 = 0x1,
+ SCL_V_MANUAL_REPLICATE_FACTOR_3 = 0x2,
+ SCL_V_MANUAL_REPLICATE_FACTOR_4 = 0x3,
+ SCL_V_MANUAL_REPLICATE_FACTOR_5 = 0x4,
+ SCL_V_MANUAL_REPLICATE_FACTOR_6 = 0x5,
+ SCL_V_MANUAL_REPLICATE_FACTOR_7 = 0x6,
+ SCL_V_MANUAL_REPLICATE_FACTOR_8 = 0x7,
+ SCL_V_MANUAL_REPLICATE_FACTOR_9 = 0x8,
+ SCL_V_MANUAL_REPLICATE_FACTOR_10 = 0x9,
+ SCL_V_MANUAL_REPLICATE_FACTOR_11 = 0xa,
+ SCL_V_MANUAL_REPLICATE_FACTOR_12 = 0xb,
+ SCL_V_MANUAL_REPLICATE_FACTOR_13 = 0xc,
+ SCL_V_MANUAL_REPLICATE_FACTOR_14 = 0xd,
+ SCL_V_MANUAL_REPLICATE_FACTOR_15 = 0xe,
+ SCL_V_MANUAL_REPLICATE_FACTOR_16 = 0xf,
+} SCL_V_MANUAL_REPLICATE_FACTOR;
+typedef enum SCL_H_MANUAL_REPLICATE_FACTOR {
+ SCL_H_MANUAL_REPLICATE_FACTOR_1 = 0x0,
+ SCL_H_MANUAL_REPLICATE_FACTOR_2 = 0x1,
+ SCL_H_MANUAL_REPLICATE_FACTOR_3 = 0x2,
+ SCL_H_MANUAL_REPLICATE_FACTOR_4 = 0x3,
+ SCL_H_MANUAL_REPLICATE_FACTOR_5 = 0x4,
+ SCL_H_MANUAL_REPLICATE_FACTOR_6 = 0x5,
+ SCL_H_MANUAL_REPLICATE_FACTOR_7 = 0x6,
+ SCL_H_MANUAL_REPLICATE_FACTOR_8 = 0x7,
+ SCL_H_MANUAL_REPLICATE_FACTOR_9 = 0x8,
+ SCL_H_MANUAL_REPLICATE_FACTOR_10 = 0x9,
+ SCL_H_MANUAL_REPLICATE_FACTOR_11 = 0xa,
+ SCL_H_MANUAL_REPLICATE_FACTOR_12 = 0xb,
+ SCL_H_MANUAL_REPLICATE_FACTOR_13 = 0xc,
+ SCL_H_MANUAL_REPLICATE_FACTOR_14 = 0xd,
+ SCL_H_MANUAL_REPLICATE_FACTOR_15 = 0xe,
+ SCL_H_MANUAL_REPLICATE_FACTOR_16 = 0xf,
+} SCL_H_MANUAL_REPLICATE_FACTOR;
+typedef enum SCL_V_CALC_AUTO_RATIO_EN {
+ SCL_V_CALC_AUTO_RATIO_DISABLE = 0x0,
+ SCL_V_CALC_AUTO_RATIO_ENABLE = 0x1,
+} SCL_V_CALC_AUTO_RATIO_EN;
+typedef enum SCL_H_CALC_AUTO_RATIO_EN {
+ SCL_H_CALC_AUTO_RATIO_DISABLE = 0x0,
+ SCL_H_CALC_AUTO_RATIO_ENABLE = 0x1,
+} SCL_H_CALC_AUTO_RATIO_EN;
+typedef enum SCL_H_FILTER_PICK_NEAREST {
+ SCL_H_FILTER_PICK_NEAREST_DISABLE = 0x0,
+ SCL_H_FILTER_PICK_NEAREST_ENABLE = 0x1,
+} SCL_H_FILTER_PICK_NEAREST;
+typedef enum SCL_H_2TAP_HARDCODE_COEF_EN {
+ SCL_H_2TAP_HARDCODE_COEF_DISABLE = 0x0,
+ SCL_H_2TAP_HARDCODE_COEF_ENABLE = 0x1,
+} SCL_H_2TAP_HARDCODE_COEF_EN;
+typedef enum SCL_V_FILTER_PICK_NEAREST {
+ SCL_V_FILTER_PICK_NEAREST_DISABLE = 0x0,
+ SCL_V_FILTER_PICK_NEAREST_ENABLE = 0x1,
+} SCL_V_FILTER_PICK_NEAREST;
+typedef enum SCL_V_2TAP_HARDCODE_COEF_EN {
+ SCL_V_2TAP_HARDCODE_COEF_DISABLE = 0x0,
+ SCL_V_2TAP_HARDCODE_COEF_ENABLE = 0x1,
+} SCL_V_2TAP_HARDCODE_COEF_EN;
+typedef enum SCL_UPDATE_TAKEN {
+ SCL_UPDATE_TAKEN_NO = 0x0,
+ SCL_UPDATE_TAKEN_YES = 0x1,
+} SCL_UPDATE_TAKEN;
+typedef enum SCL_UPDATE_LOCK {
+ SCL_UPDATE_UNLOCKED = 0x0,
+ SCL_UPDATE_LOCKED = 0x1,
+} SCL_UPDATE_LOCK;
+typedef enum SCL_COEF_UPDATE_COMPLETE {
+ SCL_COEF_UPDATE_NOT_COMPLETED = 0x0,
+ SCL_COEF_UPDATE_COMPLETED = 0x1,
+} SCL_COEF_UPDATE_COMPLETE;
+typedef enum SCL_HF_SHARP_SCALE_FACTOR {
+ SCL_HF_SHARP_SCALE_FACTOR_0 = 0x0,
+ SCL_HF_SHARP_SCALE_FACTOR_1 = 0x1,
+ SCL_HF_SHARP_SCALE_FACTOR_2 = 0x2,
+ SCL_HF_SHARP_SCALE_FACTOR_3 = 0x3,
+ SCL_HF_SHARP_SCALE_FACTOR_4 = 0x4,
+ SCL_HF_SHARP_SCALE_FACTOR_5 = 0x5,
+ SCL_HF_SHARP_SCALE_FACTOR_6 = 0x6,
+ SCL_HF_SHARP_SCALE_FACTOR_7 = 0x7,
+} SCL_HF_SHARP_SCALE_FACTOR;
+typedef enum SCL_HF_SHARP_EN {
+ SCL_HF_SHARP_DISABLE = 0x0,
+ SCL_HF_SHARP_ENABLE = 0x1,
+} SCL_HF_SHARP_EN;
+typedef enum SCL_VF_SHARP_SCALE_FACTOR {
+ SCL_VF_SHARP_SCALE_FACTOR_0 = 0x0,
+ SCL_VF_SHARP_SCALE_FACTOR_1 = 0x1,
+ SCL_VF_SHARP_SCALE_FACTOR_2 = 0x2,
+ SCL_VF_SHARP_SCALE_FACTOR_3 = 0x3,
+ SCL_VF_SHARP_SCALE_FACTOR_4 = 0x4,
+ SCL_VF_SHARP_SCALE_FACTOR_5 = 0x5,
+ SCL_VF_SHARP_SCALE_FACTOR_6 = 0x6,
+ SCL_VF_SHARP_SCALE_FACTOR_7 = 0x7,
+} SCL_VF_SHARP_SCALE_FACTOR;
+typedef enum SCL_VF_SHARP_EN {
+ SCL_VF_SHARP_DISABLE = 0x0,
+ SCL_VF_SHARP_ENABLE = 0x1,
+} SCL_VF_SHARP_EN;
+typedef enum SCL_ALU_DISABLE {
+ SCL_ALU_ENABLED = 0x0,
+ SCL_ALU_DISABLED = 0x1,
+} SCL_ALU_DISABLE;
+typedef enum SCL_HOST_CONFLICT_MASK {
+ SCL_HOST_CONFLICT_DISABLE_INTERRUPT = 0x0,
+ SCL_HOST_CONFLICT_ENABLE_INTERRUPT = 0x1,
+} SCL_HOST_CONFLICT_MASK;
+typedef enum SCL_SCL_MODE_CHANGE_MASK {
+ SCL_MODE_CHANGE_DISABLE_INTERRUPT = 0x0,
+ SCL_MODE_CHANGE_ENABLE_INTERRUPT = 0x1,
+} SCL_SCL_MODE_CHANGE_MASK;
+typedef enum SCLV_INTERLACE_SOURCE {
+ INTERLACE_SOURCE_PROGRESSIVE = 0x0,
+ INTERLACE_SOURCE_INTERLEAVE = 0x1,
+ INTERLACE_SOURCE_STACK = 0x2,
+} SCLV_INTERLACE_SOURCE;
+typedef enum SCLV_UPDATE_LOCK {
+ UPDATE_UNLOCKED = 0x0,
+ UPDATE_LOCKED = 0x1,
+} SCLV_UPDATE_LOCK;
+typedef enum SCLV_COEF_UPDATE_COMPLETE {
+ COEF_UPDATE_NOT_COMPLETE = 0x0,
+ COEF_UPDATE_COMPLETE = 0x1,
+} SCLV_COEF_UPDATE_COMPLETE;
+typedef enum COL_MAN_UPDATE_LOCK {
+ COL_MAN_UPDATE_UNLOCKED = 0x0,
+ COL_MAN_UPDATE_LOCKED = 0x1,
+} COL_MAN_UPDATE_LOCK;
+typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE {
+ COL_MAN_MULTIPLE_UPDATE = 0x0,
+ COL_MAN_MULTIPLE_UPDAT_EDISABLE = 0x1,
+} COL_MAN_DISABLE_MULTIPLE_UPDATE;
+typedef enum COL_MAN_INPUTCSC_MODE {
+ INPUTCSC_MODE_BYPASS = 0x0,
+ INPUTCSC_MODE_A = 0x1,
+ INPUTCSC_MODE_B = 0x2,
+ INPUTCSC_MODE_UNITY = 0x3,
+} COL_MAN_INPUTCSC_MODE;
+typedef enum COL_MAN_INPUTCSC_TYPE {
+ INPUTCSC_TYPE_12_0 = 0x0,
+ INPUTCSC_TYPE_10_2 = 0x1,
+ INPUTCSC_TYPE_8_4 = 0x2,
+} COL_MAN_INPUTCSC_TYPE;
+typedef enum COL_MAN_INPUTCSC_CONVERT {
+ INPUTCSC_ROUND = 0x0,
+ INPUTCSC_TRUNCATE = 0x1,
+} COL_MAN_INPUTCSC_CONVERT;
+typedef enum COL_MAN_PRESCALE_MODE {
+ PRESCALE_MODE_BYPASS = 0x0,
+ PRESCALE_MODE_PROGRAM = 0x1,
+ PRESCALE_MODE_UNITY = 0x2,
+} COL_MAN_PRESCALE_MODE;
+typedef enum COL_MAN_INPUT_GAMMA_MODE {
+ INGAMMA_MODE_BYPASS = 0x0,
+ INGAMMA_MODE_FIX = 0x1,
+ INGAMMA_MODE_FLOAT = 0x2,
+} COL_MAN_INPUT_GAMMA_MODE;
+typedef enum COL_MAN_OUTPUT_CSC_MODE {
+ COL_MAN_OUTPUT_CSC_BYPASS = 0x0,
+ COL_MAN_OUTPUT_CSC_RGB = 0x1,
+ COL_MAN_OUTPUT_CSC_YCrCb601 = 0x2,
+ COL_MAN_OUTPUT_CSC_YCrCb709 = 0x3,
+ COL_MAN_OUTPUT_CSC_A = 0x4,
+ COL_MAN_OUTPUT_CSC_B = 0x5,
+ COL_MAN_OUTPUT_CSC_UNITY = 0x6,
+} COL_MAN_OUTPUT_CSC_MODE;
+typedef enum COL_MAN_DENORM_CLAMP_CONTROL {
+ DENORM_CLAMP_MODE_UNITY = 0x0,
+ DENORM_CLAMP_MODE_8 = 0x1,
+ DENORM_CLAMP_MODE_10 = 0x2,
+ DENORM_CLAMP_MODE_12 = 0x3,
+} COL_MAN_DENORM_CLAMP_CONTROL;
+typedef enum COL_MAN_GAMMA_CORR_CONTROL {
+ GAMMA_CORR_MODE_BYPASS = 0x0,
+ GAMMA_CORR_MODE_A = 0x1,
+ GAMMA_CORR_MODE_B = 0x2,
+} COL_MAN_GAMMA_CORR_CONTROL;
+typedef enum COL_MAN_GLOBAL_PASSTHROUGH_ENABLE {
+ CM_GLOBAL_PASSTHROUGH_DISBALE = 0x0,
+ CM_GLOBAL_PASSTHROUGH_ENABLE = 0x1,
+} COL_MAN_GLOBAL_PASSTHROUGH_ENABLE;
+typedef enum UNP_GRPH_EN {
+ UNP_GRPH_DISABLED = 0x0,
+ UNP_GRPH_ENABLED = 0x1,
+} UNP_GRPH_EN;
+typedef enum UNP_GRPH_DEPTH {
+ UNP_GRPH_8BPP = 0x0,
+ UNP_GRPH_16BPP = 0x1,
+ UNP_GRPH_32BPP = 0x2,
+} UNP_GRPH_DEPTH;
+typedef enum UNP_GRPH_NUM_BANKS {
+ UNP_GRPH_ADDR_SURF_2_BANK = 0x0,
+ UNP_GRPH_ADDR_SURF_4_BANK = 0x1,
+ UNP_GRPH_ADDR_SURF_8_BANK = 0x2,
+ UNP_GRPH_ADDR_SURF_16_BANK = 0x3,
+} UNP_GRPH_NUM_BANKS;
+typedef enum UNP_GRPH_BANK_WIDTH {
+ UNP_GRPH_ADDR_SURF_BANK_WIDTH_1 = 0x0,
+ UNP_GRPH_ADDR_SURF_BANK_WIDTH_2 = 0x1,
+ UNP_GRPH_ADDR_SURF_BANK_WIDTH_4 = 0x2,
+ UNP_GRPH_ADDR_SURF_BANK_WIDTH_8 = 0x3,
+} UNP_GRPH_BANK_WIDTH;
+typedef enum UNP_GRPH_BANK_HEIGHT {
+ UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1 = 0x0,
+ UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2 = 0x1,
+ UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4 = 0x2,
+ UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8 = 0x3,
+} UNP_GRPH_BANK_HEIGHT;
+typedef enum UNP_GRPH_TILE_SPLIT {
+ UNP_ADDR_SURF_TILE_SPLIT_64B = 0x0,
+ UNP_ADDR_SURF_TILE_SPLIT_128B = 0x1,
+ UNP_ADDR_SURF_TILE_SPLIT_256B = 0x2,
+ UNP_ADDR_SURF_TILE_SPLIT_512B = 0x3,
+ UNP_ADDR_SURF_TILE_SPLIT_1KB = 0x4,
+ UNP_ADDR_SURF_TILE_SPLIT_2KB = 0x5,
+ UNP_ADDR_SURF_TILE_SPLIT_4KB = 0x6,
+} UNP_GRPH_TILE_SPLIT;
+typedef enum UNP_GRPH_ADDRESS_TRANSLATION_ENABLE {
+ UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0 = 0x0,
+ UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1 = 0x1,
+} UNP_GRPH_ADDRESS_TRANSLATION_ENABLE;
+typedef enum UNP_GRPH_PRIVILEGED_ACCESS_ENABLE {
+ UNP_GRPH_PRIVILEGED_ACCESS_DIS = 0x0,
+ UNP_GRPH_PRIVILEGED_ACCESS_EN = 0x1,
+} UNP_GRPH_PRIVILEGED_ACCESS_ENABLE;
+typedef enum UNP_GRPH_MACRO_TILE_ASPECT {
+ UNP_ADDR_SURF_MACRO_ASPECT_1 = 0x0,
+ UNP_ADDR_SURF_MACRO_ASPECT_2 = 0x1,
+ UNP_ADDR_SURF_MACRO_ASPECT_4 = 0x2,
+ UNP_ADDR_SURF_MACRO_ASPECT_8 = 0x3,
+} UNP_GRPH_MACRO_TILE_ASPECT;
+typedef enum UNP_GRPH_COLOR_EXPANSION_MODE {
+ UNP_GRPH_DYNAMIC_EXPANSION = 0x0,
+ UNP_GRPH_ZERO_EXPANSION = 0x1,
+} UNP_GRPH_COLOR_EXPANSION_MODE;
+typedef enum UNP_VIDEO_FORMAT {
+ UNP_VIDEO_FORMAT0 = 0x0,
+ UNP_VIDEO_FORMAT1 = 0x1,
+ UNP_VIDEO_FORMAT_YUV420_YCbCr = 0x2,
+ UNP_VIDEO_FORMAT_YUV420_YCrCb = 0x3,
+ UNP_VIDEO_FORMAT_YUV422_YCb = 0x4,
+ UNP_VIDEO_FORMAT_YUV422_YCr = 0x5,
+ UNP_VIDEO_FORMAT_YUV422_CbY = 0x6,
+ UNP_VIDEO_FORMAT_YUV422_CrY = 0x7,
+} UNP_VIDEO_FORMAT;
+typedef enum UNP_GRPH_ENDIAN_SWAP {
+ UNP_GRPH_ENDIAN_SWAP_NONE = 0x0,
+ UNP_GRPH_ENDIAN_SWAP_8IN16 = 0x1,
+ UNP_GRPH_ENDIAN_SWAP_8IN32 = 0x2,
+ UNP_GRPH_ENDIAN_SWAP_8IN43 = 0x3,
+} UNP_GRPH_ENDIAN_SWAP;
+typedef enum UNP_GRPH_RED_CROSSBAR {
+ UNP_GRPH_RED_CROSSBAR_R_Cr = 0x0,
+ UNP_GRPH_RED_CROSSBAR_G_Y = 0x1,
+ UNP_GRPH_RED_CROSSBAR_B_Cb = 0x2,
+ UNP_GRPH_RED_CROSSBAR_A = 0x3,
+} UNP_GRPH_RED_CROSSBAR;
+typedef enum UNP_GRPH_GREEN_CROSSBAR {
+ UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y = 0x0,
+ UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C = 0x1,
+ UNP_UNP_GRPH_GREEN_CROSSBAR_A = 0x2,
+ UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr = 0x3,
+} UNP_GRPH_GREEN_CROSSBAR;
+typedef enum UNP_GRPH_BLUE_CROSSBAR {
+ UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C = 0x0,
+ UNP_GRPH_BLUE_CROSSBAR_A = 0x1,
+ UNP_GRPH_BLUE_CROSSBAR_R_Cr = 0x2,
+ UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y = 0x3,
+} UNP_GRPH_BLUE_CROSSBAR;
+typedef enum UNP_GRPH_MODE_UPDATE_LOCKG {
+ UNP_GRPH_UPDATE_LOCK_0 = 0x0,
+ UNP_GRPH_UPDATE_LOCK_1 = 0x1,
+} UNP_GRPH_MODE_UPDATE_LOCKG;
+typedef enum UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
+ UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0 = 0x0,
+ UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1 = 0x1,
+} UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
+typedef enum UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
+ UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0 = 0x0,
+ UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1 = 0x1,
+} UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
+typedef enum UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
+ UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0 = 0x0,
+ UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1 = 0x1,
+} UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
+typedef enum UNP_GRPH_STEREOSYNC_FLIP_EN {
+ UNP_GRPH_STEREOSYNC_FLIP_DISABLE = 0x0,
+ UNP_GRPH_STEREOSYNC_FLIP_ENABLE = 0x1,
+} UNP_GRPH_STEREOSYNC_FLIP_EN;
+typedef enum UNP_GRPH_STEREOSYNC_FLIP_MODE {
+ UNP_GRPH_STEREOSYNC_FLIP_MODE_0 = 0x0,
+ UNP_GRPH_STEREOSYNC_FLIP_MODE_1 = 0x1,
+ UNP_GRPH_STEREOSYNC_FLIP_MODE_2 = 0x2,
+ UNP_GRPH_STEREOSYNC_FLIP_MODE_3 = 0x3,
+} UNP_GRPH_STEREOSYNC_FLIP_MODE;
+typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_EN {
+ UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE = 0x0,
+ UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE = 0x1,
+} UNP_GRPH_STACK_INTERLACE_FLIP_EN;
+typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_MODE {
+ UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0 = 0x0,
+ UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1 = 0x1,
+ UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2 = 0x2,
+ UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3 = 0x3,
+} UNP_GRPH_STACK_INTERLACE_FLIP_MODE;
+typedef enum UNP_GRPH_STEREOSYNC_SELECT_DISABLE {
+ UNP_GRPH_STEREOSYNC_SELECT_EN = 0x0,
+ UNP_GRPH_STEREOSYNC_SELECT_DIS = 0x1,
+} UNP_GRPH_STEREOSYNC_SELECT_DISABLE;
+typedef enum UNP_CRC_SOURCE_SEL {
+ UNP_CRC_SOURCE_SEL_NP_TO_LBV = 0x0,
+ UNP_CRC_SOURCE_SEL_LOWER32 = 0x1,
+ UNP_CRC_SOURCE_SEL_RESERVED = 0x2,
+ UNP_CRC_SOURCE_SEL_LOWER16 = 0x3,
+ UNP_CRC_SOURCE_SEL_UNP_TO_LBV = 0x4,
+} UNP_CRC_SOURCE_SEL;
+typedef enum UNP_CRC_LINE_SEL {
+ UNP_CRC_LINE_SEL_RESERVED = 0x0,
+ UNP_CRC_LINE_SEL_EVEN_ONLY = 0x1,
+ UNP_CRC_LINE_SEL_ODD_ONLY = 0x2,
+ UNP_CRC_LINE_SEL_ODD_EVEN = 0x3,
+} UNP_CRC_LINE_SEL;
+typedef enum UNP_ROTATION_ANGLE {
+ UNP_ROTATION_ANGLE_0 = 0x0,
+ UNP_ROTATION_ANGLE_90 = 0x1,
+ UNP_ROTATION_ANGLE_180 = 0x2,
+ UNP_ROTATION_ANGLE_270 = 0x3,
+ UNP_ROTATION_ANGLE_0m = 0x4,
+ UNP_ROTATION_ANGLE_90m = 0x5,
+ UNP_ROTATION_ANGLE_180m = 0x6,
+ UNP_ROTATION_ANGLE_270m = 0x7,
+} UNP_ROTATION_ANGLE;
+typedef enum UNP_PIXEL_DROP {
+ UNP_PIXEL_NO_DROP = 0x0,
+ UNP_PIXEL_DROPPING = 0x1,
+} UNP_PIXEL_DROP;
+typedef enum UNP_BUFFER_MODE {
+ UNP_BUFFER_MODE_LUMA = 0x0,
+ UNP_BUFFER_MODE_LUMA_CHROMA = 0x1,
+} UNP_BUFFER_MODE;
+typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
+ AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET= 0x0,
+ AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET= 0x1,
+} AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET;
+typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
+ CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL= 0x0,
+ CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6= 0x1,
+ CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5= 0x2,
+ CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4= 0x3,
+ CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3= 0x4,
+ CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2= 0x5,
+ CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1= 0x6,
+ CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0= 0x7,
+} CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY;
+typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
+ CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL= 0x0,
+ CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6= 0x1,
+ CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5= 0x2,
+ CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4= 0x3,
+ CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3= 0x4,
+ CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2= 0x5,
+ CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1= 0x6,
+ CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0= 0x7,
+} CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY;
+typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
+ GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0x0,
+ GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 0x1,
+} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL;
+typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
+ GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0x0,
+ GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 0x1,
+} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED;
+typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
+ GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0x0,
+ GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 0x1,
+} GENERIC_AZ_CONTROLLER_REGISTER_STATUS;
+typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
+ GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED= 0x0,
+ GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED= 0x1,
+} GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED;
+typedef enum AZ_GLOBAL_CAPABILITIES {
+ AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED= 0x0,
+ AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED= 0x1,
+} AZ_GLOBAL_CAPABILITIES;
+typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
+ ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0x0,
+ ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 0x1,
+} GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE;
+typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
+ FLUSH_CONTROL_FLUSH_NOT_STARTED = 0x0,
+ FLUSH_CONTROL_FLUSH_STARTED = 0x1,
+} GLOBAL_CONTROL_FLUSH_CONTROL;
+typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
+ CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0x0,
+ CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 0x1,
+} GLOBAL_CONTROL_CONTROLLER_RESET;
+typedef enum AZ_STATE_CHANGE_STATUS {
+ AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0x0,
+ AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 0x1,
+} AZ_STATE_CHANGE_STATUS;
+typedef enum GLOBAL_STATUS_FLUSH_STATUS {
+ GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0x0,
+ GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 0x1,
+} GLOBAL_STATUS_FLUSH_STATUS;
+typedef enum STREAM_0_SYNCHRONIZATION {
+ STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0,
+ STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 0x1,
+} STREAM_0_SYNCHRONIZATION;
+typedef enum STREAM_1_SYNCHRONIZATION {
+ STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0,
+ STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 0x1,
+} STREAM_1_SYNCHRONIZATION;
+typedef enum STREAM_2_SYNCHRONIZATION {
+ STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0,
+ STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 0x1,
+} STREAM_2_SYNCHRONIZATION;
+typedef enum STREAM_3_SYNCHRONIZATION {
+ STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
+ STREAM_3_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
+} STREAM_3_SYNCHRONIZATION;
+typedef enum STREAM_4_SYNCHRONIZATION {
+ STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
+ STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
+} STREAM_4_SYNCHRONIZATION;
+typedef enum STREAM_5_SYNCHRONIZATION {
+ STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
+ STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
+} STREAM_5_SYNCHRONIZATION;
+typedef enum STREAM_6_SYNCHRONIZATION {
+ STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
+ STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
+} STREAM_6_SYNCHRONIZATION;
+typedef enum STREAM_7_SYNCHRONIZATION {
+ STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
+ STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
+} STREAM_7_SYNCHRONIZATION;
+typedef enum STREAM_8_SYNCHRONIZATION {
+ STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
+ STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
+} STREAM_8_SYNCHRONIZATION;
+typedef enum STREAM_9_SYNCHRONIZATION {
+ STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
+ STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
+} STREAM_9_SYNCHRONIZATION;
+typedef enum STREAM_10_SYNCHRONIZATION {
+ STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
+ STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
+} STREAM_10_SYNCHRONIZATION;
+typedef enum STREAM_11_SYNCHRONIZATION {
+ STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
+ STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
+} STREAM_11_SYNCHRONIZATION;
+typedef enum STREAM_12_SYNCHRONIZATION {
+ STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
+ STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
+} STREAM_12_SYNCHRONIZATION;
+typedef enum STREAM_13_SYNCHRONIZATION {
+ STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
+ STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
+} STREAM_13_SYNCHRONIZATION;
+typedef enum STREAM_14_SYNCHRONIZATION {
+ STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
+ STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
+} STREAM_14_SYNCHRONIZATION;
+typedef enum STREAM_15_SYNCHRONIZATION {
+ STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
+ STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
+} STREAM_15_SYNCHRONIZATION;
+typedef enum CORB_READ_POINTER_RESET {
+ CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0x0,
+ CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 0x1,
+} CORB_READ_POINTER_RESET;
+typedef enum AZ_CORB_SIZE {
+ AZ_CORB_SIZE_2ENTRIES_RESERVED = 0x0,
+ AZ_CORB_SIZE_16ENTRIES_RESERVED = 0x1,
+ AZ_CORB_SIZE_256ENTRIES = 0x2,
+ AZ_CORB_SIZE_RESERVED = 0x3,
+} AZ_CORB_SIZE;
+typedef enum AZ_RIRB_WRITE_POINTER_RESET {
+ AZ_RIRB_WRITE_POINTER_NOT_RESET = 0x0,
+ AZ_RIRB_WRITE_POINTER_DO_RESET = 0x1,
+} AZ_RIRB_WRITE_POINTER_RESET;
+typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
+ RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED= 0x0,
+ RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED= 0x1,
+} RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL;
+typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
+ RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED= 0x0,
+ RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED= 0x1,
+} RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL;
+typedef enum AZ_RIRB_SIZE {
+ AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0x0,
+ AZ_RIRB_SIZE_16ENTRIES_RESERVED = 0x1,
+ AZ_RIRB_SIZE_256ENTRIES = 0x2,
+ AZ_RIRB_SIZE_UNDEFINED = 0x3,
+} AZ_RIRB_SIZE;
+typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
+ IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID= 0x0,
+ IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID= 0x1,
+} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID;
+typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
+ IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY= 0x0,
+ IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY= 0x1,
+} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY;
+typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
+ DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE= 0x0,
+ DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE= 0x1,
+} DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE;
+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
+ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET= 0x0,
+ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET= 0x1,
+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR;
+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
+ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET= 0x0,
+ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET= 0x1,
+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR;
+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
+ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET= 0x0,
+ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET= 0x1,
+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS;
+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
+ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY= 0x0,
+ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY= 0x1,
+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY;
+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
+ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED= 0x0,
+ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED= 0x1,
+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE;
+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
+ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED= 0x0,
+ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED= 0x1,
+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE;
+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
+ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED= 0x0,
+ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED= 0x1,
+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE;
+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
+ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN= 0x0,
+ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN= 0x1,
+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN;
+typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
+ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET= 0x0,
+ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET= 0x1,
+} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET;
+typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1,
+} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE;
+typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4,
+} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE;
+typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7,
+} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR;
+typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16= 0x1,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20= 0x2,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24= 0x3,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5,
+} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE;
+typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1= 0x0,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2= 0x1,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4= 0x3,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5= 0x4,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6= 0x5,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7= 0x6,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8= 0x7,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED= 0x8,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED= 0x9,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED= 0xa,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED= 0xb,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED= 0xc,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED= 0xd,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED= 0xe,
+ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED= 0xf,
+} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS;
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM= 0x0,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM= 0x1,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16= 0x1,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24= 0x3,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1= 0x0,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2= 0x1,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4= 0x3,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5= 0x4,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6= 0x5,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7= 0x6,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8= 0x7,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED= 0x8,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET= 0x0,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET= 0x1,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L;
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET= 0x0,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET= 0x1,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO;
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET= 0x0,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET= 0x1,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO;
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET= 0x0,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET= 0x1,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY;
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET= 0x0,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET= 0x1,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE;
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON= 0x0,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON= 0x1,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG;
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO= 0x0,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE= 0x1,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V;
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED= 0x0,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED= 0x1,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
+typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE= 0x0,
+ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE= 0x1,
+} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE;
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
+ AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF= 0x0,
+ AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN= 0x1,
+} AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE;
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
+ AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED= 0x0,
+ AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED= 0x1,
+} AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
+ AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED= 0x0,
+ AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 0x1,
+} AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT;
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
+ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED= 0x0,
+ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED= 0x1,
+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE;
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
+ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED= 0x0,
+ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED= 0x1,
+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE;
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
+ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED= 0x0,
+ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED= 0x1,
+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE;
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
+ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED= 0x0,
+ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED= 0x1,
+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE;
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
+ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED= 0x0,
+ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED= 0x1,
+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
+ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED= 0x0,
+ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED= 0x1,
+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
+ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED= 0x0,
+ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED= 0x1,
+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
+ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED= 0x0,
+ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED= 0x1,
+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
+typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
+ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE= 0x0,
+ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE= 0x1,
+} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
+typedef enum AZ_LATENCY_COUNTER_CONTROL {
+ AZ_LATENCY_COUNTER_NO_RESET = 0x0,
+ AZ_LATENCY_COUNTER_RESET_DONE = 0x1,
+} AZ_LATENCY_COUNTER_CONTROL;
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED= 0x8,
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0,
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0,
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES= 0x0,
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES= 0x1,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0,
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE= 0x0,
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE= 0x1,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0,
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
+typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC= 0x0,
+ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO= 0x1,
+} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED= 0x8,
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0,
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1,
+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0,
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1,
+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES= 0x0,
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES= 0x1,
+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0,
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1,
+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT= 0x0,
+ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
+} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
+ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN= 0x0,
+ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN= 0x1,
+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
+ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED= 0x0,
+ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED= 0x1,
+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
+ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN= 0x0,
+ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN= 0x1,
+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
+ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN= 0x0,
+ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN= 0x1,
+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
+ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY= 0x0,
+ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY= 0x1,
+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
+ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY= 0x0,
+ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY= 0x1,
+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
+ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x0,
+ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x1,
+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
+typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
+ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY= 0x0,
+ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY= 0x1,
+} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
+typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
+ AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE= 0x0,
+ AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE= 0x1,
+} AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
+typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
+ AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY= 0x0,
+ AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY= 0x1,
+} AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED= 0x8,
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0,
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG= 0x0,
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL= 0x1,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES= 0x0,
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES= 0x1,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING= 0x0,
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE= 0x0,
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE= 0x1,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER= 0x1,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0,
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
+typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC= 0x0,
+ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO= 0x1,
+} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED= 0x8,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP= 0x0,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP= 0x1,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES= 0x0,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES= 0x1,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED= 0x0,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED= 0x1,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP;
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN= 0x0,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN= 0x1,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED= 0x0,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED= 0x1,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI;
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED= 0x0,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED= 0x1,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN= 0x0,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN= 0x1,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN= 0x0,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN= 0x1,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY= 0x0,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY= 0x1,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY= 0x0,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY= 0x1,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x0,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x1,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY= 0x0,
+ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY= 0x1,
+} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
+typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
+ AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY= 0x0,
+ AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY= 0x1,
+} AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
+typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM= 0x0,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM= 0x1,
+} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
+typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1,
+} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
+typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4,
+} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
+typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7,
+} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
+typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16= 0x1,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24= 0x3,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5,
+} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
+typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1= 0x0,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2= 0x1,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4= 0x3,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5= 0x4,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6= 0x5,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7= 0x6,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8= 0x7,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED= 0x8,
+} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
+typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED= 0x0,
+ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED= 0x1,
+} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
+ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF= 0x0,
+ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN= 0x1,
+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE;
+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
+ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED= 0x0,
+ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED= 0x1,
+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
+ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED= 0x0,
+ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED= 0x1,
+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE;
+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
+ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED= 0x0,
+ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED= 0x1,
+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
+ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED= 0x0,
+ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED= 0x1,
+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE;
+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
+ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED= 0x0,
+ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED= 0x1,
+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
+ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED= 0x0,
+ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED= 0x1,
+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE;
+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
+ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED= 0x0,
+ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED= 0x1,
+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
+ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED= 0x0,
+ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED= 0x1,
+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE;
+typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
+ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED= 0x0,
+ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED= 0x1,
+} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
+typedef enum BLND_CONTROL_BLND_MODE {
+ BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x0,
+ BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x1,
+ BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x2,
+ BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x3,
+} BLND_CONTROL_BLND_MODE;
+typedef enum BLND_CONTROL_BLND_STEREO_TYPE {
+ BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO= 0x0,
+ BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO= 0x1,
+ BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2,
+ BLND_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x3,
+} BLND_CONTROL_BLND_STEREO_TYPE;
+typedef enum BLND_CONTROL_BLND_STEREO_POLARITY {
+ BLND_CONTROL_BLND_STEREO_POLARITY_LOW = 0x0,
+ BLND_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x1,
+} BLND_CONTROL_BLND_STEREO_POLARITY;
+typedef enum BLND_CONTROL_BLND_FEEDTHROUGH_EN {
+ BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x0,
+ BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x1,
+} BLND_CONTROL_BLND_FEEDTHROUGH_EN;
+typedef enum BLND_CONTROL_BLND_ALPHA_MODE {
+ BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x0,
+ BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN= 0x1,
+ BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x2,
+ BLND_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x3,
+} BLND_CONTROL_BLND_ALPHA_MODE;
+typedef enum BLND_CONTROL_BLND_MULTIPLIED_MODE {
+ BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x0,
+ BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x1,
+} BLND_CONTROL_BLND_MULTIPLIED_MODE;
+typedef enum BLND_SM_CONTROL2_SM_MODE {
+ BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x0,
+ BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x2,
+ BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x4,
+ BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING= 0x6,
+} BLND_SM_CONTROL2_SM_MODE;
+typedef enum BLND_SM_CONTROL2_SM_FRAME_ALTERNATE {
+ BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x0,
+ BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x1,
+} BLND_SM_CONTROL2_SM_FRAME_ALTERNATE;
+typedef enum BLND_SM_CONTROL2_SM_FIELD_ALTERNATE {
+ BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x0,
+ BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x1,
+} BLND_SM_CONTROL2_SM_FIELD_ALTERNATE;
+typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
+ BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE= 0x0,
+ BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED= 0x1,
+ BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2,
+ BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH= 0x3,
+} BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
+typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
+ BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x0,
+ BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x1,
+ BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x2,
+ BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH= 0x3,
+} BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
+typedef enum BLND_CONTROL2_PTI_ENABLE {
+ BLND_CONTROL2_PTI_ENABLE_FALSE = 0x0,
+ BLND_CONTROL2_PTI_ENABLE_TRUE = 0x1,
+} BLND_CONTROL2_PTI_ENABLE;
+typedef enum BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
+ BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x0,
+ BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x1,
+} BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
+typedef enum BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
+ BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x0,
+ BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x1,
+} BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
+typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
+ BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE= 0x0,
+ BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE= 0x1,
+} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
+typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
+ BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE= 0x0,
+ BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE= 0x1,
+} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
+typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
+ BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE= 0x0,
+ BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE= 0x1,
+} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
+typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
+ BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE= 0x0,
+ BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE= 0x1,
+} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
+typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
+ BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE= 0x0,
+ BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE= 0x1,
+} BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
+typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
+ BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE= 0x0,
+ BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE= 0x1,
+} BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
+typedef enum BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
+ BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x0,
+ BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x1,
+} BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
+typedef enum BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
+ BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x0,
+ BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x1,
+} BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
+typedef enum BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
+ BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x0,
+ BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x1,
+} BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
+typedef enum BLND_DEBUG_BLND_CNV_MUX_SELECT {
+ BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x0,
+ BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x1,
+} BLND_DEBUG_BLND_CNV_MUX_SELECT;
+typedef enum BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
+ BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE= 0x0,
+ BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE= 0x1,
+} BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
+typedef enum DebugBlockId {
+ DBG_BLOCK_ID_RESERVED = 0x0,
+ DBG_BLOCK_ID_DBG = 0x1,
+ DBG_BLOCK_ID_VMC = 0x2,
+ DBG_BLOCK_ID_PDMA = 0x3,
+ DBG_BLOCK_ID_CG = 0x4,
+ DBG_BLOCK_ID_SRBM = 0x5,
+ DBG_BLOCK_ID_GRBM = 0x6,
+ DBG_BLOCK_ID_RLC = 0x7,
+ DBG_BLOCK_ID_CSC = 0x8,
+ DBG_BLOCK_ID_SEM = 0x9,
+ DBG_BLOCK_ID_IH = 0xa,
+ DBG_BLOCK_ID_SC = 0xb,
+ DBG_BLOCK_ID_SQ = 0xc,
+ DBG_BLOCK_ID_UVDU = 0xd,
+ DBG_BLOCK_ID_SQA = 0xe,
+ DBG_BLOCK_ID_SDMA0 = 0xf,
+ DBG_BLOCK_ID_SDMA1 = 0x10,
+ DBG_BLOCK_ID_SPIM = 0x11,
+ DBG_BLOCK_ID_GDS = 0x12,
+ DBG_BLOCK_ID_VC0 = 0x13,
+ DBG_BLOCK_ID_VC1 = 0x14,
+ DBG_BLOCK_ID_PA0 = 0x15,
+ DBG_BLOCK_ID_PA1 = 0x16,
+ DBG_BLOCK_ID_CP0 = 0x17,
+ DBG_BLOCK_ID_CP1 = 0x18,
+ DBG_BLOCK_ID_CP2 = 0x19,
+ DBG_BLOCK_ID_XBR = 0x1a,
+ DBG_BLOCK_ID_UVDM = 0x1b,
+ DBG_BLOCK_ID_VGT0 = 0x1c,
+ DBG_BLOCK_ID_VGT1 = 0x1d,
+ DBG_BLOCK_ID_IA = 0x1e,
+ DBG_BLOCK_ID_SXM0 = 0x1f,
+ DBG_BLOCK_ID_SXM1 = 0x20,
+ DBG_BLOCK_ID_SCT0 = 0x21,
+ DBG_BLOCK_ID_SCT1 = 0x22,
+ DBG_BLOCK_ID_SPM0 = 0x23,
+ DBG_BLOCK_ID_SPM1 = 0x24,
+ DBG_BLOCK_ID_UNUSED0 = 0x25,
+ DBG_BLOCK_ID_UNUSED1 = 0x26,
+ DBG_BLOCK_ID_TCAA = 0x27,
+ DBG_BLOCK_ID_TCAB = 0x28,
+ DBG_BLOCK_ID_TCCA = 0x29,
+ DBG_BLOCK_ID_TCCB = 0x2a,
+ DBG_BLOCK_ID_MCC0 = 0x2b,
+ DBG_BLOCK_ID_MCC1 = 0x2c,
+ DBG_BLOCK_ID_MCC2 = 0x2d,
+ DBG_BLOCK_ID_MCC3 = 0x2e,
+ DBG_BLOCK_ID_SXS0 = 0x2f,
+ DBG_BLOCK_ID_SXS1 = 0x30,
+ DBG_BLOCK_ID_SXS2 = 0x31,
+ DBG_BLOCK_ID_SXS3 = 0x32,
+ DBG_BLOCK_ID_SXS4 = 0x33,
+ DBG_BLOCK_ID_SXS5 = 0x34,
+ DBG_BLOCK_ID_SXS6 = 0x35,
+ DBG_BLOCK_ID_SXS7 = 0x36,
+ DBG_BLOCK_ID_SXS8 = 0x37,
+ DBG_BLOCK_ID_SXS9 = 0x38,
+ DBG_BLOCK_ID_BCI0 = 0x39,
+ DBG_BLOCK_ID_BCI1 = 0x3a,
+ DBG_BLOCK_ID_BCI2 = 0x3b,
+ DBG_BLOCK_ID_BCI3 = 0x3c,
+ DBG_BLOCK_ID_MCB = 0x3d,
+ DBG_BLOCK_ID_UNUSED6 = 0x3e,
+ DBG_BLOCK_ID_SQA00 = 0x3f,
+ DBG_BLOCK_ID_SQA01 = 0x40,
+ DBG_BLOCK_ID_SQA02 = 0x41,
+ DBG_BLOCK_ID_SQA10 = 0x42,
+ DBG_BLOCK_ID_SQA11 = 0x43,
+ DBG_BLOCK_ID_SQA12 = 0x44,
+ DBG_BLOCK_ID_UNUSED7 = 0x45,
+ DBG_BLOCK_ID_UNUSED8 = 0x46,
+ DBG_BLOCK_ID_SQB00 = 0x47,
+ DBG_BLOCK_ID_SQB01 = 0x48,
+ DBG_BLOCK_ID_SQB10 = 0x49,
+ DBG_BLOCK_ID_SQB11 = 0x4a,
+ DBG_BLOCK_ID_SQ00 = 0x4b,
+ DBG_BLOCK_ID_SQ01 = 0x4c,
+ DBG_BLOCK_ID_SQ10 = 0x4d,
+ DBG_BLOCK_ID_SQ11 = 0x4e,
+ DBG_BLOCK_ID_CB00 = 0x4f,
+ DBG_BLOCK_ID_CB01 = 0x50,
+ DBG_BLOCK_ID_CB02 = 0x51,
+ DBG_BLOCK_ID_CB03 = 0x52,
+ DBG_BLOCK_ID_CB04 = 0x53,
+ DBG_BLOCK_ID_UNUSED9 = 0x54,
+ DBG_BLOCK_ID_UNUSED10 = 0x55,
+ DBG_BLOCK_ID_UNUSED11 = 0x56,
+ DBG_BLOCK_ID_CB10 = 0x57,
+ DBG_BLOCK_ID_CB11 = 0x58,
+ DBG_BLOCK_ID_CB12 = 0x59,
+ DBG_BLOCK_ID_CB13 = 0x5a,
+ DBG_BLOCK_ID_CB14 = 0x5b,
+ DBG_BLOCK_ID_UNUSED12 = 0x5c,
+ DBG_BLOCK_ID_UNUSED13 = 0x5d,
+ DBG_BLOCK_ID_UNUSED14 = 0x5e,
+ DBG_BLOCK_ID_TCP0 = 0x5f,
+ DBG_BLOCK_ID_TCP1 = 0x60,
+ DBG_BLOCK_ID_TCP2 = 0x61,
+ DBG_BLOCK_ID_TCP3 = 0x62,
+ DBG_BLOCK_ID_TCP4 = 0x63,
+ DBG_BLOCK_ID_TCP5 = 0x64,
+ DBG_BLOCK_ID_TCP6 = 0x65,
+ DBG_BLOCK_ID_TCP7 = 0x66,
+ DBG_BLOCK_ID_TCP8 = 0x67,
+ DBG_BLOCK_ID_TCP9 = 0x68,
+ DBG_BLOCK_ID_TCP10 = 0x69,
+ DBG_BLOCK_ID_TCP11 = 0x6a,
+ DBG_BLOCK_ID_TCP12 = 0x6b,
+ DBG_BLOCK_ID_TCP13 = 0x6c,
+ DBG_BLOCK_ID_TCP14 = 0x6d,
+ DBG_BLOCK_ID_TCP15 = 0x6e,
+ DBG_BLOCK_ID_TCP16 = 0x6f,
+ DBG_BLOCK_ID_TCP17 = 0x70,
+ DBG_BLOCK_ID_TCP18 = 0x71,
+ DBG_BLOCK_ID_TCP19 = 0x72,
+ DBG_BLOCK_ID_TCP20 = 0x73,
+ DBG_BLOCK_ID_TCP21 = 0x74,
+ DBG_BLOCK_ID_TCP22 = 0x75,
+ DBG_BLOCK_ID_TCP23 = 0x76,
+ DBG_BLOCK_ID_TCP_RESERVED0 = 0x77,
+ DBG_BLOCK_ID_TCP_RESERVED1 = 0x78,
+ DBG_BLOCK_ID_TCP_RESERVED2 = 0x79,
+ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a,
+ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b,
+ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c,
+ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d,
+ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e,
+ DBG_BLOCK_ID_DB00 = 0x7f,
+ DBG_BLOCK_ID_DB01 = 0x80,
+ DBG_BLOCK_ID_DB02 = 0x81,
+ DBG_BLOCK_ID_DB03 = 0x82,
+ DBG_BLOCK_ID_DB04 = 0x83,
+ DBG_BLOCK_ID_UNUSED15 = 0x84,
+ DBG_BLOCK_ID_UNUSED16 = 0x85,
+ DBG_BLOCK_ID_UNUSED17 = 0x86,
+ DBG_BLOCK_ID_DB10 = 0x87,
+ DBG_BLOCK_ID_DB11 = 0x88,
+ DBG_BLOCK_ID_DB12 = 0x89,
+ DBG_BLOCK_ID_DB13 = 0x8a,
+ DBG_BLOCK_ID_DB14 = 0x8b,
+ DBG_BLOCK_ID_UNUSED18 = 0x8c,
+ DBG_BLOCK_ID_UNUSED19 = 0x8d,
+ DBG_BLOCK_ID_UNUSED20 = 0x8e,
+ DBG_BLOCK_ID_TCC0 = 0x8f,
+ DBG_BLOCK_ID_TCC1 = 0x90,
+ DBG_BLOCK_ID_TCC2 = 0x91,
+ DBG_BLOCK_ID_TCC3 = 0x92,
+ DBG_BLOCK_ID_TCC4 = 0x93,
+ DBG_BLOCK_ID_TCC5 = 0x94,
+ DBG_BLOCK_ID_TCC6 = 0x95,
+ DBG_BLOCK_ID_TCC7 = 0x96,
+ DBG_BLOCK_ID_SPS00 = 0x97,
+ DBG_BLOCK_ID_SPS01 = 0x98,
+ DBG_BLOCK_ID_SPS02 = 0x99,
+ DBG_BLOCK_ID_SPS10 = 0x9a,
+ DBG_BLOCK_ID_SPS11 = 0x9b,
+ DBG_BLOCK_ID_SPS12 = 0x9c,
+ DBG_BLOCK_ID_UNUSED21 = 0x9d,
+ DBG_BLOCK_ID_UNUSED22 = 0x9e,
+ DBG_BLOCK_ID_TA00 = 0x9f,
+ DBG_BLOCK_ID_TA01 = 0xa0,
+ DBG_BLOCK_ID_TA02 = 0xa1,
+ DBG_BLOCK_ID_TA03 = 0xa2,
+ DBG_BLOCK_ID_TA04 = 0xa3,
+ DBG_BLOCK_ID_TA05 = 0xa4,
+ DBG_BLOCK_ID_TA06 = 0xa5,
+ DBG_BLOCK_ID_TA07 = 0xa6,
+ DBG_BLOCK_ID_TA08 = 0xa7,
+ DBG_BLOCK_ID_TA09 = 0xa8,
+ DBG_BLOCK_ID_TA0A = 0xa9,
+ DBG_BLOCK_ID_TA0B = 0xaa,
+ DBG_BLOCK_ID_UNUSED23 = 0xab,
+ DBG_BLOCK_ID_UNUSED24 = 0xac,
+ DBG_BLOCK_ID_UNUSED25 = 0xad,
+ DBG_BLOCK_ID_UNUSED26 = 0xae,
+ DBG_BLOCK_ID_TA10 = 0xaf,
+ DBG_BLOCK_ID_TA11 = 0xb0,
+ DBG_BLOCK_ID_TA12 = 0xb1,
+ DBG_BLOCK_ID_TA13 = 0xb2,
+ DBG_BLOCK_ID_TA14 = 0xb3,
+ DBG_BLOCK_ID_TA15 = 0xb4,
+ DBG_BLOCK_ID_TA16 = 0xb5,
+ DBG_BLOCK_ID_TA17 = 0xb6,
+ DBG_BLOCK_ID_TA18 = 0xb7,
+ DBG_BLOCK_ID_TA19 = 0xb8,
+ DBG_BLOCK_ID_TA1A = 0xb9,
+ DBG_BLOCK_ID_TA1B = 0xba,
+ DBG_BLOCK_ID_UNUSED27 = 0xbb,
+ DBG_BLOCK_ID_UNUSED28 = 0xbc,
+ DBG_BLOCK_ID_UNUSED29 = 0xbd,
+ DBG_BLOCK_ID_UNUSED30 = 0xbe,
+ DBG_BLOCK_ID_TD00 = 0xbf,
+ DBG_BLOCK_ID_TD01 = 0xc0,
+ DBG_BLOCK_ID_TD02 = 0xc1,
+ DBG_BLOCK_ID_TD03 = 0xc2,
+ DBG_BLOCK_ID_TD04 = 0xc3,
+ DBG_BLOCK_ID_TD05 = 0xc4,
+ DBG_BLOCK_ID_TD06 = 0xc5,
+ DBG_BLOCK_ID_TD07 = 0xc6,
+ DBG_BLOCK_ID_TD08 = 0xc7,
+ DBG_BLOCK_ID_TD09 = 0xc8,
+ DBG_BLOCK_ID_TD0A = 0xc9,
+ DBG_BLOCK_ID_TD0B = 0xca,
+ DBG_BLOCK_ID_UNUSED31 = 0xcb,
+ DBG_BLOCK_ID_UNUSED32 = 0xcc,
+ DBG_BLOCK_ID_UNUSED33 = 0xcd,
+ DBG_BLOCK_ID_UNUSED34 = 0xce,
+ DBG_BLOCK_ID_TD10 = 0xcf,
+ DBG_BLOCK_ID_TD11 = 0xd0,
+ DBG_BLOCK_ID_TD12 = 0xd1,
+ DBG_BLOCK_ID_TD13 = 0xd2,
+ DBG_BLOCK_ID_TD14 = 0xd3,
+ DBG_BLOCK_ID_TD15 = 0xd4,
+ DBG_BLOCK_ID_TD16 = 0xd5,
+ DBG_BLOCK_ID_TD17 = 0xd6,
+ DBG_BLOCK_ID_TD18 = 0xd7,
+ DBG_BLOCK_ID_TD19 = 0xd8,
+ DBG_BLOCK_ID_TD1A = 0xd9,
+ DBG_BLOCK_ID_TD1B = 0xda,
+ DBG_BLOCK_ID_UNUSED35 = 0xdb,
+ DBG_BLOCK_ID_UNUSED36 = 0xdc,
+ DBG_BLOCK_ID_UNUSED37 = 0xdd,
+ DBG_BLOCK_ID_UNUSED38 = 0xde,
+ DBG_BLOCK_ID_LDS00 = 0xdf,
+ DBG_BLOCK_ID_LDS01 = 0xe0,
+ DBG_BLOCK_ID_LDS02 = 0xe1,
+ DBG_BLOCK_ID_LDS03 = 0xe2,
+ DBG_BLOCK_ID_LDS04 = 0xe3,
+ DBG_BLOCK_ID_LDS05 = 0xe4,
+ DBG_BLOCK_ID_LDS06 = 0xe5,
+ DBG_BLOCK_ID_LDS07 = 0xe6,
+ DBG_BLOCK_ID_LDS08 = 0xe7,
+ DBG_BLOCK_ID_LDS09 = 0xe8,
+ DBG_BLOCK_ID_LDS0A = 0xe9,
+ DBG_BLOCK_ID_LDS0B = 0xea,
+ DBG_BLOCK_ID_UNUSED39 = 0xeb,
+ DBG_BLOCK_ID_UNUSED40 = 0xec,
+ DBG_BLOCK_ID_UNUSED41 = 0xed,
+ DBG_BLOCK_ID_UNUSED42 = 0xee,
+ DBG_BLOCK_ID_LDS10 = 0xef,
+ DBG_BLOCK_ID_LDS11 = 0xf0,
+ DBG_BLOCK_ID_LDS12 = 0xf1,
+ DBG_BLOCK_ID_LDS13 = 0xf2,
+ DBG_BLOCK_ID_LDS14 = 0xf3,
+ DBG_BLOCK_ID_LDS15 = 0xf4,
+ DBG_BLOCK_ID_LDS16 = 0xf5,
+ DBG_BLOCK_ID_LDS17 = 0xf6,
+ DBG_BLOCK_ID_LDS18 = 0xf7,
+ DBG_BLOCK_ID_LDS19 = 0xf8,
+ DBG_BLOCK_ID_LDS1A = 0xf9,
+ DBG_BLOCK_ID_LDS1B = 0xfa,
+ DBG_BLOCK_ID_UNUSED43 = 0xfb,
+ DBG_BLOCK_ID_UNUSED44 = 0xfc,
+ DBG_BLOCK_ID_UNUSED45 = 0xfd,
+ DBG_BLOCK_ID_UNUSED46 = 0xfe,
+} DebugBlockId;
+typedef enum DebugBlockId_BY2 {
+ DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
+ DBG_BLOCK_ID_VMC_BY2 = 0x1,
+ DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
+ DBG_BLOCK_ID_GRBM_BY2 = 0x3,
+ DBG_BLOCK_ID_CSC_BY2 = 0x4,
+ DBG_BLOCK_ID_IH_BY2 = 0x5,
+ DBG_BLOCK_ID_SQ_BY2 = 0x6,
+ DBG_BLOCK_ID_UVD_BY2 = 0x7,
+ DBG_BLOCK_ID_SDMA0_BY2 = 0x8,
+ DBG_BLOCK_ID_SPIM_BY2 = 0x9,
+ DBG_BLOCK_ID_VC0_BY2 = 0xa,
+ DBG_BLOCK_ID_PA_BY2 = 0xb,
+ DBG_BLOCK_ID_CP0_BY2 = 0xc,
+ DBG_BLOCK_ID_CP2_BY2 = 0xd,
+ DBG_BLOCK_ID_PC0_BY2 = 0xe,
+ DBG_BLOCK_ID_BCI0_BY2 = 0xf,
+ DBG_BLOCK_ID_SXM0_BY2 = 0x10,
+ DBG_BLOCK_ID_SCT0_BY2 = 0x11,
+ DBG_BLOCK_ID_SPM0_BY2 = 0x12,
+ DBG_BLOCK_ID_BCI2_BY2 = 0x13,
+ DBG_BLOCK_ID_TCA_BY2 = 0x14,
+ DBG_BLOCK_ID_TCCA_BY2 = 0x15,
+ DBG_BLOCK_ID_MCC_BY2 = 0x16,
+ DBG_BLOCK_ID_MCC2_BY2 = 0x17,
+ DBG_BLOCK_ID_MCD_BY2 = 0x18,
+ DBG_BLOCK_ID_MCD2_BY2 = 0x19,
+ DBG_BLOCK_ID_MCD4_BY2 = 0x1a,
+ DBG_BLOCK_ID_MCB_BY2 = 0x1b,
+ DBG_BLOCK_ID_SQA_BY2 = 0x1c,
+ DBG_BLOCK_ID_SQA02_BY2 = 0x1d,
+ DBG_BLOCK_ID_SQA11_BY2 = 0x1e,
+ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f,
+ DBG_BLOCK_ID_SQB_BY2 = 0x20,
+ DBG_BLOCK_ID_SQB10_BY2 = 0x21,
+ DBG_BLOCK_ID_UNUSED10_BY2 = 0x22,
+ DBG_BLOCK_ID_UNUSED12_BY2 = 0x23,
+ DBG_BLOCK_ID_CB_BY2 = 0x24,
+ DBG_BLOCK_ID_CB02_BY2 = 0x25,
+ DBG_BLOCK_ID_CB10_BY2 = 0x26,
+ DBG_BLOCK_ID_CB12_BY2 = 0x27,
+ DBG_BLOCK_ID_SXS_BY2 = 0x28,
+ DBG_BLOCK_ID_SXS2_BY2 = 0x29,
+ DBG_BLOCK_ID_SXS4_BY2 = 0x2a,
+ DBG_BLOCK_ID_SXS6_BY2 = 0x2b,
+ DBG_BLOCK_ID_DB_BY2 = 0x2c,
+ DBG_BLOCK_ID_DB02_BY2 = 0x2d,
+ DBG_BLOCK_ID_DB10_BY2 = 0x2e,
+ DBG_BLOCK_ID_DB12_BY2 = 0x2f,
+ DBG_BLOCK_ID_TCP_BY2 = 0x30,
+ DBG_BLOCK_ID_TCP2_BY2 = 0x31,
+ DBG_BLOCK_ID_TCP4_BY2 = 0x32,
+ DBG_BLOCK_ID_TCP6_BY2 = 0x33,
+ DBG_BLOCK_ID_TCP8_BY2 = 0x34,
+ DBG_BLOCK_ID_TCP10_BY2 = 0x35,
+ DBG_BLOCK_ID_TCP12_BY2 = 0x36,
+ DBG_BLOCK_ID_TCP14_BY2 = 0x37,
+ DBG_BLOCK_ID_TCP16_BY2 = 0x38,
+ DBG_BLOCK_ID_TCP18_BY2 = 0x39,
+ DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
+ DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
+ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
+ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
+ DBG_BLOCK_ID_TCC_BY2 = 0x40,
+ DBG_BLOCK_ID_TCC2_BY2 = 0x41,
+ DBG_BLOCK_ID_TCC4_BY2 = 0x42,
+ DBG_BLOCK_ID_TCC6_BY2 = 0x43,
+ DBG_BLOCK_ID_SPS_BY2 = 0x44,
+ DBG_BLOCK_ID_SPS02_BY2 = 0x45,
+ DBG_BLOCK_ID_SPS11_BY2 = 0x46,
+ DBG_BLOCK_ID_UNUSED14_BY2 = 0x47,
+ DBG_BLOCK_ID_TA_BY2 = 0x48,
+ DBG_BLOCK_ID_TA02_BY2 = 0x49,
+ DBG_BLOCK_ID_TA04_BY2 = 0x4a,
+ DBG_BLOCK_ID_TA06_BY2 = 0x4b,
+ DBG_BLOCK_ID_TA08_BY2 = 0x4c,
+ DBG_BLOCK_ID_TA0A_BY2 = 0x4d,
+ DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e,
+ DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f,
+ DBG_BLOCK_ID_TA10_BY2 = 0x50,
+ DBG_BLOCK_ID_TA12_BY2 = 0x51,
+ DBG_BLOCK_ID_TA14_BY2 = 0x52,
+ DBG_BLOCK_ID_TA16_BY2 = 0x53,
+ DBG_BLOCK_ID_TA18_BY2 = 0x54,
+ DBG_BLOCK_ID_TA1A_BY2 = 0x55,
+ DBG_BLOCK_ID_UNUSED24_BY2 = 0x56,
+ DBG_BLOCK_ID_UNUSED26_BY2 = 0x57,
+ DBG_BLOCK_ID_TD_BY2 = 0x58,
+ DBG_BLOCK_ID_TD02_BY2 = 0x59,
+ DBG_BLOCK_ID_TD04_BY2 = 0x5a,
+ DBG_BLOCK_ID_TD06_BY2 = 0x5b,
+ DBG_BLOCK_ID_TD08_BY2 = 0x5c,
+ DBG_BLOCK_ID_TD0A_BY2 = 0x5d,
+ DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e,
+ DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f,
+ DBG_BLOCK_ID_TD10_BY2 = 0x60,
+ DBG_BLOCK_ID_TD12_BY2 = 0x61,
+ DBG_BLOCK_ID_TD14_BY2 = 0x62,
+ DBG_BLOCK_ID_TD16_BY2 = 0x63,
+ DBG_BLOCK_ID_TD18_BY2 = 0x64,
+ DBG_BLOCK_ID_TD1A_BY2 = 0x65,
+ DBG_BLOCK_ID_UNUSED32_BY2 = 0x66,
+ DBG_BLOCK_ID_UNUSED34_BY2 = 0x67,
+ DBG_BLOCK_ID_LDS_BY2 = 0x68,
+ DBG_BLOCK_ID_LDS02_BY2 = 0x69,
+ DBG_BLOCK_ID_LDS04_BY2 = 0x6a,
+ DBG_BLOCK_ID_LDS06_BY2 = 0x6b,
+ DBG_BLOCK_ID_LDS08_BY2 = 0x6c,
+ DBG_BLOCK_ID_LDS0A_BY2 = 0x6d,
+ DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e,
+ DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f,
+ DBG_BLOCK_ID_LDS10_BY2 = 0x70,
+ DBG_BLOCK_ID_LDS12_BY2 = 0x71,
+ DBG_BLOCK_ID_LDS14_BY2 = 0x72,
+ DBG_BLOCK_ID_LDS16_BY2 = 0x73,
+ DBG_BLOCK_ID_LDS18_BY2 = 0x74,
+ DBG_BLOCK_ID_LDS1A_BY2 = 0x75,
+ DBG_BLOCK_ID_UNUSED40_BY2 = 0x76,
+ DBG_BLOCK_ID_UNUSED42_BY2 = 0x77,
+} DebugBlockId_BY2;
+typedef enum DebugBlockId_BY4 {
+ DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
+ DBG_BLOCK_ID_UNUSED0_BY4 = 0x1,
+ DBG_BLOCK_ID_CSC_BY4 = 0x2,
+ DBG_BLOCK_ID_SQ_BY4 = 0x3,
+ DBG_BLOCK_ID_SDMA0_BY4 = 0x4,
+ DBG_BLOCK_ID_VC0_BY4 = 0x5,
+ DBG_BLOCK_ID_CP0_BY4 = 0x6,
+ DBG_BLOCK_ID_UNUSED1_BY4 = 0x7,
+ DBG_BLOCK_ID_SXM0_BY4 = 0x8,
+ DBG_BLOCK_ID_SPM0_BY4 = 0x9,
+ DBG_BLOCK_ID_TCAA_BY4 = 0xa,
+ DBG_BLOCK_ID_MCC_BY4 = 0xb,
+ DBG_BLOCK_ID_MCD_BY4 = 0xc,
+ DBG_BLOCK_ID_MCD4_BY4 = 0xd,
+ DBG_BLOCK_ID_SQA_BY4 = 0xe,
+ DBG_BLOCK_ID_SQA11_BY4 = 0xf,
+ DBG_BLOCK_ID_SQB_BY4 = 0x10,
+ DBG_BLOCK_ID_UNUSED10_BY4 = 0x11,
+ DBG_BLOCK_ID_CB_BY4 = 0x12,
+ DBG_BLOCK_ID_CB10_BY4 = 0x13,
+ DBG_BLOCK_ID_SXS_BY4 = 0x14,
+ DBG_BLOCK_ID_SXS4_BY4 = 0x15,
+ DBG_BLOCK_ID_DB_BY4 = 0x16,
+ DBG_BLOCK_ID_DB10_BY4 = 0x17,
+ DBG_BLOCK_ID_TCP_BY4 = 0x18,
+ DBG_BLOCK_ID_TCP4_BY4 = 0x19,
+ DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
+ DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
+ DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
+ DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
+ DBG_BLOCK_ID_TCC_BY4 = 0x20,
+ DBG_BLOCK_ID_TCC4_BY4 = 0x21,
+ DBG_BLOCK_ID_SPS_BY4 = 0x22,
+ DBG_BLOCK_ID_SPS11_BY4 = 0x23,
+ DBG_BLOCK_ID_TA_BY4 = 0x24,
+ DBG_BLOCK_ID_TA04_BY4 = 0x25,
+ DBG_BLOCK_ID_TA08_BY4 = 0x26,
+ DBG_BLOCK_ID_UNUSED20_BY4 = 0x27,
+ DBG_BLOCK_ID_TA10_BY4 = 0x28,
+ DBG_BLOCK_ID_TA14_BY4 = 0x29,
+ DBG_BLOCK_ID_TA18_BY4 = 0x2a,
+ DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b,
+ DBG_BLOCK_ID_TD_BY4 = 0x2c,
+ DBG_BLOCK_ID_TD04_BY4 = 0x2d,
+ DBG_BLOCK_ID_TD08_BY4 = 0x2e,
+ DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f,
+ DBG_BLOCK_ID_TD10_BY4 = 0x30,
+ DBG_BLOCK_ID_TD14_BY4 = 0x31,
+ DBG_BLOCK_ID_TD18_BY4 = 0x32,
+ DBG_BLOCK_ID_UNUSED32_BY4 = 0x33,
+ DBG_BLOCK_ID_LDS_BY4 = 0x34,
+ DBG_BLOCK_ID_LDS04_BY4 = 0x35,
+ DBG_BLOCK_ID_LDS08_BY4 = 0x36,
+ DBG_BLOCK_ID_UNUSED36_BY4 = 0x37,
+ DBG_BLOCK_ID_LDS10_BY4 = 0x38,
+ DBG_BLOCK_ID_LDS14_BY4 = 0x39,
+ DBG_BLOCK_ID_LDS18_BY4 = 0x3a,
+ DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b,
+} DebugBlockId_BY4;
+typedef enum DebugBlockId_BY8 {
+ DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
+ DBG_BLOCK_ID_CSC_BY8 = 0x1,
+ DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
+ DBG_BLOCK_ID_CP0_BY8 = 0x3,
+ DBG_BLOCK_ID_SXM0_BY8 = 0x4,
+ DBG_BLOCK_ID_TCA_BY8 = 0x5,
+ DBG_BLOCK_ID_MCD_BY8 = 0x6,
+ DBG_BLOCK_ID_SQA_BY8 = 0x7,
+ DBG_BLOCK_ID_SQB_BY8 = 0x8,
+ DBG_BLOCK_ID_CB_BY8 = 0x9,
+ DBG_BLOCK_ID_SXS_BY8 = 0xa,
+ DBG_BLOCK_ID_DB_BY8 = 0xb,
+ DBG_BLOCK_ID_TCP_BY8 = 0xc,
+ DBG_BLOCK_ID_TCP8_BY8 = 0xd,
+ DBG_BLOCK_ID_TCP16_BY8 = 0xe,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
+ DBG_BLOCK_ID_TCC_BY8 = 0x10,
+ DBG_BLOCK_ID_SPS_BY8 = 0x11,
+ DBG_BLOCK_ID_TA_BY8 = 0x12,
+ DBG_BLOCK_ID_TA08_BY8 = 0x13,
+ DBG_BLOCK_ID_TA10_BY8 = 0x14,
+ DBG_BLOCK_ID_TA18_BY8 = 0x15,
+ DBG_BLOCK_ID_TD_BY8 = 0x16,
+ DBG_BLOCK_ID_TD08_BY8 = 0x17,
+ DBG_BLOCK_ID_TD10_BY8 = 0x18,
+ DBG_BLOCK_ID_TD18_BY8 = 0x19,
+ DBG_BLOCK_ID_LDS_BY8 = 0x1a,
+ DBG_BLOCK_ID_LDS08_BY8 = 0x1b,
+ DBG_BLOCK_ID_LDS10_BY8 = 0x1c,
+ DBG_BLOCK_ID_LDS18_BY8 = 0x1d,
+} DebugBlockId_BY8;
+typedef enum DebugBlockId_BY16 {
+ DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
+ DBG_BLOCK_ID_SDMA0_BY16 = 0x1,
+ DBG_BLOCK_ID_SXM_BY16 = 0x2,
+ DBG_BLOCK_ID_MCD_BY16 = 0x3,
+ DBG_BLOCK_ID_SQB_BY16 = 0x4,
+ DBG_BLOCK_ID_SXS_BY16 = 0x5,
+ DBG_BLOCK_ID_TCP_BY16 = 0x6,
+ DBG_BLOCK_ID_TCP16_BY16 = 0x7,
+ DBG_BLOCK_ID_TCC_BY16 = 0x8,
+ DBG_BLOCK_ID_TA_BY16 = 0x9,
+ DBG_BLOCK_ID_TA10_BY16 = 0xa,
+ DBG_BLOCK_ID_TD_BY16 = 0xb,
+ DBG_BLOCK_ID_TD10_BY16 = 0xc,
+ DBG_BLOCK_ID_LDS_BY16 = 0xd,
+ DBG_BLOCK_ID_LDS10_BY16 = 0xe,
+} DebugBlockId_BY16;
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0x0,
+ ENDIAN_8IN16 = 0x1,
+ ENDIAN_8IN32 = 0x2,
+ ENDIAN_8IN64 = 0x3,
+} SurfaceEndian;
+typedef enum ArrayMode {
+ ARRAY_LINEAR_GENERAL = 0x0,
+ ARRAY_LINEAR_ALIGNED = 0x1,
+ ARRAY_1D_TILED_THIN1 = 0x2,
+ ARRAY_1D_TILED_THICK = 0x3,
+ ARRAY_2D_TILED_THIN1 = 0x4,
+ ARRAY_PRT_TILED_THIN1 = 0x5,
+ ARRAY_PRT_2D_TILED_THIN1 = 0x6,
+ ARRAY_2D_TILED_THICK = 0x7,
+ ARRAY_2D_TILED_XTHICK = 0x8,
+ ARRAY_PRT_TILED_THICK = 0x9,
+ ARRAY_PRT_2D_TILED_THICK = 0xa,
+ ARRAY_PRT_3D_TILED_THIN1 = 0xb,
+ ARRAY_3D_TILED_THIN1 = 0xc,
+ ARRAY_3D_TILED_THICK = 0xd,
+ ARRAY_3D_TILED_XTHICK = 0xe,
+ ARRAY_PRT_3D_TILED_THICK = 0xf,
+} ArrayMode;
+typedef enum PipeTiling {
+ CONFIG_1_PIPE = 0x0,
+ CONFIG_2_PIPE = 0x1,
+ CONFIG_4_PIPE = 0x2,
+ CONFIG_8_PIPE = 0x3,
+} PipeTiling;
+typedef enum BankTiling {
+ CONFIG_4_BANK = 0x0,
+ CONFIG_8_BANK = 0x1,
+} BankTiling;
+typedef enum GroupInterleave {
+ CONFIG_256B_GROUP = 0x0,
+ CONFIG_512B_GROUP = 0x1,
+} GroupInterleave;
+typedef enum RowTiling {
+ CONFIG_1KB_ROW = 0x0,
+ CONFIG_2KB_ROW = 0x1,
+ CONFIG_4KB_ROW = 0x2,
+ CONFIG_8KB_ROW = 0x3,
+ CONFIG_1KB_ROW_OPT = 0x4,
+ CONFIG_2KB_ROW_OPT = 0x5,
+ CONFIG_4KB_ROW_OPT = 0x6,
+ CONFIG_8KB_ROW_OPT = 0x7,
+} RowTiling;
+typedef enum BankSwapBytes {
+ CONFIG_128B_SWAPS = 0x0,
+ CONFIG_256B_SWAPS = 0x1,
+ CONFIG_512B_SWAPS = 0x2,
+ CONFIG_1KB_SWAPS = 0x3,
+} BankSwapBytes;
+typedef enum SampleSplitBytes {
+ CONFIG_1KB_SPLIT = 0x0,
+ CONFIG_2KB_SPLIT = 0x1,
+ CONFIG_4KB_SPLIT = 0x2,
+ CONFIG_8KB_SPLIT = 0x3,
+} SampleSplitBytes;
+typedef enum NumPipes {
+ ADDR_CONFIG_1_PIPE = 0x0,
+ ADDR_CONFIG_2_PIPE = 0x1,
+ ADDR_CONFIG_4_PIPE = 0x2,
+ ADDR_CONFIG_8_PIPE = 0x3,
+} NumPipes;
+typedef enum PipeInterleaveSize {
+ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
+ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
+} PipeInterleaveSize;
+typedef enum BankInterleaveSize {
+ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
+ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
+ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
+ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
+} BankInterleaveSize;
+typedef enum NumShaderEngines {
+ ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
+ ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
+} NumShaderEngines;
+typedef enum ShaderEngineTileSize {
+ ADDR_CONFIG_SE_TILE_16 = 0x0,
+ ADDR_CONFIG_SE_TILE_32 = 0x1,
+} ShaderEngineTileSize;
+typedef enum NumGPUs {
+ ADDR_CONFIG_1_GPU = 0x0,
+ ADDR_CONFIG_2_GPU = 0x1,
+ ADDR_CONFIG_4_GPU = 0x2,
+} NumGPUs;
+typedef enum MultiGPUTileSize {
+ ADDR_CONFIG_GPU_TILE_16 = 0x0,
+ ADDR_CONFIG_GPU_TILE_32 = 0x1,
+ ADDR_CONFIG_GPU_TILE_64 = 0x2,
+ ADDR_CONFIG_GPU_TILE_128 = 0x3,
+} MultiGPUTileSize;
+typedef enum RowSize {
+ ADDR_CONFIG_1KB_ROW = 0x0,
+ ADDR_CONFIG_2KB_ROW = 0x1,
+ ADDR_CONFIG_4KB_ROW = 0x2,
+} RowSize;
+typedef enum NumLowerPipes {
+ ADDR_CONFIG_1_LOWER_PIPES = 0x0,
+ ADDR_CONFIG_2_LOWER_PIPES = 0x1,
+} NumLowerPipes;
+typedef enum ColorTransform {
+ DCC_CT_AUTO = 0x0,
+ DCC_CT_NONE = 0x1,
+ ABGR_TO_A_BG_G_RB = 0x2,
+ BGRA_TO_BG_G_RB_A = 0x3,
+} ColorTransform;
+typedef enum CompareRef {
+ REF_NEVER = 0x0,
+ REF_LESS = 0x1,
+ REF_EQUAL = 0x2,
+ REF_LEQUAL = 0x3,
+ REF_GREATER = 0x4,
+ REF_NOTEQUAL = 0x5,
+ REF_GEQUAL = 0x6,
+ REF_ALWAYS = 0x7,
+} CompareRef;
+typedef enum ReadSize {
+ READ_256_BITS = 0x0,
+ READ_512_BITS = 0x1,
+} ReadSize;
+typedef enum DepthFormat {
+ DEPTH_INVALID = 0x0,
+ DEPTH_16 = 0x1,
+ DEPTH_X8_24 = 0x2,
+ DEPTH_8_24 = 0x3,
+ DEPTH_X8_24_FLOAT = 0x4,
+ DEPTH_8_24_FLOAT = 0x5,
+ DEPTH_32_FLOAT = 0x6,
+ DEPTH_X24_8_32_FLOAT = 0x7,
+} DepthFormat;
+typedef enum ZFormat {
+ Z_INVALID = 0x0,
+ Z_16 = 0x1,
+ Z_24 = 0x2,
+ Z_32_FLOAT = 0x3,
+} ZFormat;
+typedef enum StencilFormat {
+ STENCIL_INVALID = 0x0,
+ STENCIL_8 = 0x1,
+} StencilFormat;
+typedef enum CmaskMode {
+ CMASK_CLEAR_NONE = 0x0,
+ CMASK_CLEAR_ONE = 0x1,
+ CMASK_CLEAR_ALL = 0x2,
+ CMASK_ANY_EXPANDED = 0x3,
+ CMASK_ALPHA0_FRAG1 = 0x4,
+ CMASK_ALPHA0_FRAG2 = 0x5,
+ CMASK_ALPHA0_FRAG4 = 0x6,
+ CMASK_ALPHA0_FRAGS = 0x7,
+ CMASK_ALPHA1_FRAG1 = 0x8,
+ CMASK_ALPHA1_FRAG2 = 0x9,
+ CMASK_ALPHA1_FRAG4 = 0xa,
+ CMASK_ALPHA1_FRAGS = 0xb,
+ CMASK_ALPHAX_FRAG1 = 0xc,
+ CMASK_ALPHAX_FRAG2 = 0xd,
+ CMASK_ALPHAX_FRAG4 = 0xe,
+ CMASK_ALPHAX_FRAGS = 0xf,
+} CmaskMode;
+typedef enum QuadExportFormat {
+ EXPORT_UNUSED = 0x0,
+ EXPORT_32_R = 0x1,
+ EXPORT_32_GR = 0x2,
+ EXPORT_32_AR = 0x3,
+ EXPORT_FP16_ABGR = 0x4,
+ EXPORT_UNSIGNED16_ABGR = 0x5,
+ EXPORT_SIGNED16_ABGR = 0x6,
+ EXPORT_32_ABGR = 0x7,
+} QuadExportFormat;
+typedef enum QuadExportFormatOld {
+ EXPORT_4P_32BPC_ABGR = 0x0,
+ EXPORT_4P_16BPC_ABGR = 0x1,
+ EXPORT_4P_32BPC_GR = 0x2,
+ EXPORT_4P_32BPC_AR = 0x3,
+ EXPORT_2P_32BPC_ABGR = 0x4,
+ EXPORT_8P_32BPC_R = 0x5,
+} QuadExportFormatOld;
+typedef enum ColorFormat {
+ COLOR_INVALID = 0x0,
+ COLOR_8 = 0x1,
+ COLOR_16 = 0x2,
+ COLOR_8_8 = 0x3,
+ COLOR_32 = 0x4,
+ COLOR_16_16 = 0x5,
+ COLOR_10_11_11 = 0x6,
+ COLOR_11_11_10 = 0x7,
+ COLOR_10_10_10_2 = 0x8,
+ COLOR_2_10_10_10 = 0x9,
+ COLOR_8_8_8_8 = 0xa,
+ COLOR_32_32 = 0xb,
+ COLOR_16_16_16_16 = 0xc,
+ COLOR_RESERVED_13 = 0xd,
+ COLOR_32_32_32_32 = 0xe,
+ COLOR_RESERVED_15 = 0xf,
+ COLOR_5_6_5 = 0x10,
+ COLOR_1_5_5_5 = 0x11,
+ COLOR_5_5_5_1 = 0x12,
+ COLOR_4_4_4_4 = 0x13,
+ COLOR_8_24 = 0x14,
+ COLOR_24_8 = 0x15,
+ COLOR_X24_8_32_FLOAT = 0x16,
+ COLOR_RESERVED_23 = 0x17,
+} ColorFormat;
+typedef enum SurfaceFormat {
+ FMT_INVALID = 0x0,
+ FMT_8 = 0x1,
+ FMT_16 = 0x2,
+ FMT_8_8 = 0x3,
+ FMT_32 = 0x4,
+ FMT_16_16 = 0x5,
+ FMT_10_11_11 = 0x6,
+ FMT_11_11_10 = 0x7,
+ FMT_10_10_10_2 = 0x8,
+ FMT_2_10_10_10 = 0x9,
+ FMT_8_8_8_8 = 0xa,
+ FMT_32_32 = 0xb,
+ FMT_16_16_16_16 = 0xc,
+ FMT_32_32_32 = 0xd,
+ FMT_32_32_32_32 = 0xe,
+ FMT_RESERVED_4 = 0xf,
+ FMT_5_6_5 = 0x10,
+ FMT_1_5_5_5 = 0x11,
+ FMT_5_5_5_1 = 0x12,
+ FMT_4_4_4_4 = 0x13,
+ FMT_8_24 = 0x14,
+ FMT_24_8 = 0x15,
+ FMT_X24_8_32_FLOAT = 0x16,
+ FMT_RESERVED_33 = 0x17,
+ FMT_11_11_10_FLOAT = 0x18,
+ FMT_16_FLOAT = 0x19,
+ FMT_32_FLOAT = 0x1a,
+ FMT_16_16_FLOAT = 0x1b,
+ FMT_8_24_FLOAT = 0x1c,
+ FMT_24_8_FLOAT = 0x1d,
+ FMT_32_32_FLOAT = 0x1e,
+ FMT_10_11_11_FLOAT = 0x1f,
+ FMT_16_16_16_16_FLOAT = 0x20,
+ FMT_3_3_2 = 0x21,
+ FMT_6_5_5 = 0x22,
+ FMT_32_32_32_32_FLOAT = 0x23,
+ FMT_RESERVED_36 = 0x24,
+ FMT_1 = 0x25,
+ FMT_1_REVERSED = 0x26,
+ FMT_GB_GR = 0x27,
+ FMT_BG_RG = 0x28,
+ FMT_32_AS_8 = 0x29,
+ FMT_32_AS_8_8 = 0x2a,
+ FMT_5_9_9_9_SHAREDEXP = 0x2b,
+ FMT_8_8_8 = 0x2c,
+ FMT_16_16_16 = 0x2d,
+ FMT_16_16_16_FLOAT = 0x2e,
+ FMT_4_4 = 0x2f,
+ FMT_32_32_32_FLOAT = 0x30,
+ FMT_BC1 = 0x31,
+ FMT_BC2 = 0x32,
+ FMT_BC3 = 0x33,
+ FMT_BC4 = 0x34,
+ FMT_BC5 = 0x35,
+ FMT_BC6 = 0x36,
+ FMT_BC7 = 0x37,
+ FMT_32_AS_32_32_32_32 = 0x38,
+ FMT_APC3 = 0x39,
+ FMT_APC4 = 0x3a,
+ FMT_APC5 = 0x3b,
+ FMT_APC6 = 0x3c,
+ FMT_APC7 = 0x3d,
+ FMT_CTX1 = 0x3e,
+ FMT_RESERVED_63 = 0x3f,
+} SurfaceFormat;
+typedef enum BUF_DATA_FORMAT {
+ BUF_DATA_FORMAT_INVALID = 0x0,
+ BUF_DATA_FORMAT_8 = 0x1,
+ BUF_DATA_FORMAT_16 = 0x2,
+ BUF_DATA_FORMAT_8_8 = 0x3,
+ BUF_DATA_FORMAT_32 = 0x4,
+ BUF_DATA_FORMAT_16_16 = 0x5,
+ BUF_DATA_FORMAT_10_11_11 = 0x6,
+ BUF_DATA_FORMAT_11_11_10 = 0x7,
+ BUF_DATA_FORMAT_10_10_10_2 = 0x8,
+ BUF_DATA_FORMAT_2_10_10_10 = 0x9,
+ BUF_DATA_FORMAT_8_8_8_8 = 0xa,
+ BUF_DATA_FORMAT_32_32 = 0xb,
+ BUF_DATA_FORMAT_16_16_16_16 = 0xc,
+ BUF_DATA_FORMAT_32_32_32 = 0xd,
+ BUF_DATA_FORMAT_32_32_32_32 = 0xe,
+ BUF_DATA_FORMAT_RESERVED_15 = 0xf,
+} BUF_DATA_FORMAT;
+typedef enum IMG_DATA_FORMAT {
+ IMG_DATA_FORMAT_INVALID = 0x0,
+ IMG_DATA_FORMAT_8 = 0x1,
+ IMG_DATA_FORMAT_16 = 0x2,
+ IMG_DATA_FORMAT_8_8 = 0x3,
+ IMG_DATA_FORMAT_32 = 0x4,
+ IMG_DATA_FORMAT_16_16 = 0x5,
+ IMG_DATA_FORMAT_10_11_11 = 0x6,
+ IMG_DATA_FORMAT_11_11_10 = 0x7,
+ IMG_DATA_FORMAT_10_10_10_2 = 0x8,
+ IMG_DATA_FORMAT_2_10_10_10 = 0x9,
+ IMG_DATA_FORMAT_8_8_8_8 = 0xa,
+ IMG_DATA_FORMAT_32_32 = 0xb,
+ IMG_DATA_FORMAT_16_16_16_16 = 0xc,
+ IMG_DATA_FORMAT_32_32_32 = 0xd,
+ IMG_DATA_FORMAT_32_32_32_32 = 0xe,
+ IMG_DATA_FORMAT_RESERVED_15 = 0xf,
+ IMG_DATA_FORMAT_5_6_5 = 0x10,
+ IMG_DATA_FORMAT_1_5_5_5 = 0x11,
+ IMG_DATA_FORMAT_5_5_5_1 = 0x12,
+ IMG_DATA_FORMAT_4_4_4_4 = 0x13,
+ IMG_DATA_FORMAT_8_24 = 0x14,
+ IMG_DATA_FORMAT_24_8 = 0x15,
+ IMG_DATA_FORMAT_X24_8_32 = 0x16,
+ IMG_DATA_FORMAT_RESERVED_23 = 0x17,
+ IMG_DATA_FORMAT_RESERVED_24 = 0x18,
+ IMG_DATA_FORMAT_RESERVED_25 = 0x19,
+ IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
+ IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
+ IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
+ IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
+ IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
+ IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
+ IMG_DATA_FORMAT_GB_GR = 0x20,
+ IMG_DATA_FORMAT_BG_RG = 0x21,
+ IMG_DATA_FORMAT_5_9_9_9 = 0x22,
+ IMG_DATA_FORMAT_BC1 = 0x23,
+ IMG_DATA_FORMAT_BC2 = 0x24,
+ IMG_DATA_FORMAT_BC3 = 0x25,
+ IMG_DATA_FORMAT_BC4 = 0x26,
+ IMG_DATA_FORMAT_BC5 = 0x27,
+ IMG_DATA_FORMAT_BC6 = 0x28,
+ IMG_DATA_FORMAT_BC7 = 0x29,
+ IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
+ IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
+ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
+ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
+ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
+ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
+ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
+ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
+ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
+ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
+ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
+ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
+ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
+ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
+ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
+ IMG_DATA_FORMAT_4_4 = 0x39,
+ IMG_DATA_FORMAT_6_5_5 = 0x3a,
+ IMG_DATA_FORMAT_1 = 0x3b,
+ IMG_DATA_FORMAT_1_REVERSED = 0x3c,
+ IMG_DATA_FORMAT_32_AS_8 = 0x3d,
+ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
+ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
+} IMG_DATA_FORMAT;
+typedef enum BUF_NUM_FORMAT {
+ BUF_NUM_FORMAT_UNORM = 0x0,
+ BUF_NUM_FORMAT_SNORM = 0x1,
+ BUF_NUM_FORMAT_USCALED = 0x2,
+ BUF_NUM_FORMAT_SSCALED = 0x3,
+ BUF_NUM_FORMAT_UINT = 0x4,
+ BUF_NUM_FORMAT_SINT = 0x5,
+ BUF_NUM_FORMAT_RESERVED_6 = 0x6,
+ BUF_NUM_FORMAT_FLOAT = 0x7,
+} BUF_NUM_FORMAT;
+typedef enum IMG_NUM_FORMAT {
+ IMG_NUM_FORMAT_UNORM = 0x0,
+ IMG_NUM_FORMAT_SNORM = 0x1,
+ IMG_NUM_FORMAT_USCALED = 0x2,
+ IMG_NUM_FORMAT_SSCALED = 0x3,
+ IMG_NUM_FORMAT_UINT = 0x4,
+ IMG_NUM_FORMAT_SINT = 0x5,
+ IMG_NUM_FORMAT_RESERVED_6 = 0x6,
+ IMG_NUM_FORMAT_FLOAT = 0x7,
+ IMG_NUM_FORMAT_RESERVED_8 = 0x8,
+ IMG_NUM_FORMAT_SRGB = 0x9,
+ IMG_NUM_FORMAT_RESERVED_10 = 0xa,
+ IMG_NUM_FORMAT_RESERVED_11 = 0xb,
+ IMG_NUM_FORMAT_RESERVED_12 = 0xc,
+ IMG_NUM_FORMAT_RESERVED_13 = 0xd,
+ IMG_NUM_FORMAT_RESERVED_14 = 0xe,
+ IMG_NUM_FORMAT_RESERVED_15 = 0xf,
+} IMG_NUM_FORMAT;
+typedef enum TileType {
+ ARRAY_COLOR_TILE = 0x0,
+ ARRAY_DEPTH_TILE = 0x1,
+} TileType;
+typedef enum NonDispTilingOrder {
+ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
+ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
+} NonDispTilingOrder;
+typedef enum MicroTileMode {
+ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
+ ADDR_SURF_THIN_MICRO_TILING = 0x1,
+ ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
+ ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
+ ADDR_SURF_THICK_MICRO_TILING = 0x4,
+} MicroTileMode;
+typedef enum TileSplit {
+ ADDR_SURF_TILE_SPLIT_64B = 0x0,
+ ADDR_SURF_TILE_SPLIT_128B = 0x1,
+ ADDR_SURF_TILE_SPLIT_256B = 0x2,
+ ADDR_SURF_TILE_SPLIT_512B = 0x3,
+ ADDR_SURF_TILE_SPLIT_1KB = 0x4,
+ ADDR_SURF_TILE_SPLIT_2KB = 0x5,
+ ADDR_SURF_TILE_SPLIT_4KB = 0x6,
+} TileSplit;
+typedef enum SampleSplit {
+ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
+ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
+ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
+ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
+} SampleSplit;
+typedef enum PipeConfig {
+ ADDR_SURF_P2 = 0x0,
+ ADDR_SURF_P2_RESERVED0 = 0x1,
+ ADDR_SURF_P2_RESERVED1 = 0x2,
+ ADDR_SURF_P2_RESERVED2 = 0x3,
+ ADDR_SURF_P4_8x16 = 0x4,
+ ADDR_SURF_P4_16x16 = 0x5,
+ ADDR_SURF_P4_16x32 = 0x6,
+ ADDR_SURF_P4_32x32 = 0x7,
+ ADDR_SURF_P8_16x16_8x16 = 0x8,
+ ADDR_SURF_P8_16x32_8x16 = 0x9,
+ ADDR_SURF_P8_32x32_8x16 = 0xa,
+ ADDR_SURF_P8_16x32_16x16 = 0xb,
+ ADDR_SURF_P8_32x32_16x16 = 0xc,
+ ADDR_SURF_P8_32x32_16x32 = 0xd,
+ ADDR_SURF_P8_32x64_32x32 = 0xe,
+ ADDR_SURF_P8_RESERVED0 = 0xf,
+ ADDR_SURF_P16_32x32_8x16 = 0x10,
+ ADDR_SURF_P16_32x32_16x16 = 0x11,
+} PipeConfig;
+typedef enum NumBanks {
+ ADDR_SURF_2_BANK = 0x0,
+ ADDR_SURF_4_BANK = 0x1,
+ ADDR_SURF_8_BANK = 0x2,
+ ADDR_SURF_16_BANK = 0x3,
+} NumBanks;
+typedef enum BankWidth {
+ ADDR_SURF_BANK_WIDTH_1 = 0x0,
+ ADDR_SURF_BANK_WIDTH_2 = 0x1,
+ ADDR_SURF_BANK_WIDTH_4 = 0x2,
+ ADDR_SURF_BANK_WIDTH_8 = 0x3,
+} BankWidth;
+typedef enum BankHeight {
+ ADDR_SURF_BANK_HEIGHT_1 = 0x0,
+ ADDR_SURF_BANK_HEIGHT_2 = 0x1,
+ ADDR_SURF_BANK_HEIGHT_4 = 0x2,
+ ADDR_SURF_BANK_HEIGHT_8 = 0x3,
+} BankHeight;
+typedef enum BankWidthHeight {
+ ADDR_SURF_BANK_WH_1 = 0x0,
+ ADDR_SURF_BANK_WH_2 = 0x1,
+ ADDR_SURF_BANK_WH_4 = 0x2,
+ ADDR_SURF_BANK_WH_8 = 0x3,
+} BankWidthHeight;
+typedef enum MacroTileAspect {
+ ADDR_SURF_MACRO_ASPECT_1 = 0x0,
+ ADDR_SURF_MACRO_ASPECT_2 = 0x1,
+ ADDR_SURF_MACRO_ASPECT_4 = 0x2,
+ ADDR_SURF_MACRO_ASPECT_8 = 0x3,
+} MacroTileAspect;
+typedef enum GATCL1RequestType {
+ GATCL1_TYPE_NORMAL = 0x0,
+ GATCL1_TYPE_SHOOTDOWN = 0x1,
+ GATCL1_TYPE_BYPASS = 0x2,
+} GATCL1RequestType;
+typedef enum TCC_CACHE_POLICIES {
+ TCC_CACHE_POLICY_LRU = 0x0,
+ TCC_CACHE_POLICY_STREAM = 0x1,
+} TCC_CACHE_POLICIES;
+typedef enum MTYPE {
+ MTYPE_NC_NV = 0x0,
+ MTYPE_NC = 0x1,
+ MTYPE_CC = 0x2,
+ MTYPE_UC = 0x3,
+} MTYPE;
+typedef enum PERFMON_COUNTER_MODE {
+ PERFMON_COUNTER_MODE_ACCUM = 0x0,
+ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
+ PERFMON_COUNTER_MODE_MAX = 0x2,
+ PERFMON_COUNTER_MODE_DIRTY = 0x3,
+ PERFMON_COUNTER_MODE_SAMPLE = 0x4,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
+ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
+ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
+ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
+ PERFMON_COUNTER_MODE_RESERVED = 0xf,
+} PERFMON_COUNTER_MODE;
+typedef enum PERFMON_SPM_MODE {
+ PERFMON_SPM_MODE_OFF = 0x0,
+ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
+ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
+ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
+ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
+ PERFMON_SPM_MODE_RESERVED_5 = 0x5,
+ PERFMON_SPM_MODE_RESERVED_6 = 0x6,
+ PERFMON_SPM_MODE_RESERVED_7 = 0x7,
+ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
+ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
+ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
+} PERFMON_SPM_MODE;
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0x0,
+ ARRAY_TILED = 0x1,
+} SurfaceTiling;
+typedef enum SurfaceArray {
+ ARRAY_1D = 0x0,
+ ARRAY_2D = 0x1,
+ ARRAY_3D = 0x2,
+ ARRAY_3D_SLICE = 0x3,
+} SurfaceArray;
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0x0,
+ ARRAY_2D_COLOR = 0x1,
+ ARRAY_3D_SLICE_COLOR = 0x3,
+} ColorArray;
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0x0,
+ ARRAY_2D_DEPTH = 0x1,
+} DepthArray;
+typedef enum ENUM_NUM_SIMD_PER_CU {
+ NUM_SIMD_PER_CU = 0x4,
+} ENUM_NUM_SIMD_PER_CU;
+typedef enum MEM_PWR_FORCE_CTRL {
+ NO_FORCE_REQUEST = 0x0,
+ FORCE_LIGHT_SLEEP_REQUEST = 0x1,
+ FORCE_DEEP_SLEEP_REQUEST = 0x2,
+ FORCE_SHUT_DOWN_REQUEST = 0x3,
+} MEM_PWR_FORCE_CTRL;
+typedef enum MEM_PWR_FORCE_CTRL2 {
+ NO_FORCE_REQ = 0x0,
+ FORCE_LIGHT_SLEEP_REQ = 0x1,
+} MEM_PWR_FORCE_CTRL2;
+typedef enum MEM_PWR_DIS_CTRL {
+ ENABLE_MEM_PWR_CTRL = 0x0,
+ DISABLE_MEM_PWR_CTRL = 0x1,
+} MEM_PWR_DIS_CTRL;
+typedef enum MEM_PWR_SEL_CTRL {
+ DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
+ DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
+ DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
+} MEM_PWR_SEL_CTRL;
+typedef enum MEM_PWR_SEL_CTRL2 {
+ DYNAMIC_DEEP_SLEEP_EN = 0x0,
+ DYNAMIC_LIGHT_SLEEP_EN = 0x1,
+} MEM_PWR_SEL_CTRL2;
+typedef enum HPD_INT_CONTROL_ACK {
+ HPD_INT_CONTROL_ACK_0 = 0x0,
+ HPD_INT_CONTROL_ACK_1 = 0x1,
+} HPD_INT_CONTROL_ACK;
+typedef enum HPD_INT_CONTROL_POLARITY {
+ HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0x0,
+ HPD_INT_CONTROL_GEN_INT_ON_CON = 0x1,
+} HPD_INT_CONTROL_POLARITY;
+typedef enum HPD_INT_CONTROL_RX_INT_ACK {
+ HPD_INT_CONTROL_RX_INT_ACK_0 = 0x0,
+ HPD_INT_CONTROL_RX_INT_ACK_1 = 0x1,
+} HPD_INT_CONTROL_RX_INT_ACK;
+typedef enum DPDBG_EN {
+ DPDBG_DISABLE = 0x0,
+ DPDBG_ENABLE = 0x1,
+} DPDBG_EN;
+typedef enum DPDBG_INPUT_EN {
+ DPDBG_INPUT_DISABLE = 0x0,
+ DPDBG_INPUT_ENABLE = 0x1,
+} DPDBG_INPUT_EN;
+typedef enum DPDBG_ERROR_DETECTION_MODE {
+ DPDBG_ERROR_DETECTION_MODE_CSC = 0x0,
+ DPDBG_ERROR_DETECTION_MODE_RS_ENCODING = 0x1,
+} DPDBG_ERROR_DETECTION_MODE;
+typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK {
+ DPDBG_FIFO_OVERFLOW_INT_DISABLE = 0x0,
+ DPDBG_FIFO_OVERFLOW_INT_ENABLE = 0x1,
+} DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK;
+typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE {
+ DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED = 0x0,
+ DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED = 0x1,
+} DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE;
+typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK {
+ DPDBG_FIFO_OVERFLOW_INT_NO_ACK = 0x0,
+ DPDBG_FIFO_OVERFLOW_INT_CLEAR = 0x1,
+} DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK;
+typedef enum PM_ASSERT_RESET {
+ PM_ASSERT_RESET_0 = 0x0,
+ PM_ASSERT_RESET_1 = 0x1,
+} PM_ASSERT_RESET;
+typedef enum DAC_MUX_SELECT {
+ DAC_MUX_SELECT_DACA = 0x0,
+ DAC_MUX_SELECT_DACB = 0x1,
+} DAC_MUX_SELECT;
+typedef enum TMDS_DVO_MUX_SELECT {
+ TMDS_DVO_MUX_SELECT_B = 0x0,
+ TMDS_DVO_MUX_SELECT_G = 0x1,
+ TMDS_DVO_MUX_SELECT_R = 0x2,
+ TMDS_DVO_MUX_SELECT_RESERVED = 0x3,
+} TMDS_DVO_MUX_SELECT;
+typedef enum DACA_SOFT_RESET {
+ DACA_SOFT_RESET_0 = 0x0,
+ DACA_SOFT_RESET_1 = 0x1,
+} DACA_SOFT_RESET;
+typedef enum I2S0_SPDIF0_SOFT_RESET {
+ I2S0_SPDIF0_SOFT_RESET_0 = 0x0,
+ I2S0_SPDIF0_SOFT_RESET_1 = 0x1,
+} I2S0_SPDIF0_SOFT_RESET;
+typedef enum I2S1_SOFT_RESET {
+ I2S1_SOFT_RESET_0 = 0x0,
+ I2S1_SOFT_RESET_1 = 0x1,
+} I2S1_SOFT_RESET;
+typedef enum SPDIF1_SOFT_RESET {
+ SPDIF1_SOFT_RESET_0 = 0x0,
+ SPDIF1_SOFT_RESET_1 = 0x1,
+} SPDIF1_SOFT_RESET;
+typedef enum DB_CLK_SOFT_RESET {
+ DB_CLK_SOFT_RESET_0 = 0x0,
+ DB_CLK_SOFT_RESET_1 = 0x1,
+} DB_CLK_SOFT_RESET;
+typedef enum FMT0_SOFT_RESET {
+ FMT0_SOFT_RESET_0 = 0x0,
+ FMT0_SOFT_RESET_1 = 0x1,
+} FMT0_SOFT_RESET;
+typedef enum FMT1_SOFT_RESET {
+ FMT1_SOFT_RESET_0 = 0x0,
+ FMT1_SOFT_RESET_1 = 0x1,
+} FMT1_SOFT_RESET;
+typedef enum FMT2_SOFT_RESET {
+ FMT2_SOFT_RESET_0 = 0x0,
+ FMT2_SOFT_RESET_1 = 0x1,
+} FMT2_SOFT_RESET;
+typedef enum FMT3_SOFT_RESET {
+ FMT3_SOFT_RESET_0 = 0x0,
+ FMT3_SOFT_RESET_1 = 0x1,
+} FMT3_SOFT_RESET;
+typedef enum FMT4_SOFT_RESET {
+ FMT4_SOFT_RESET_0 = 0x0,
+ FMT4_SOFT_RESET_1 = 0x1,
+} FMT4_SOFT_RESET;
+typedef enum FMT5_SOFT_RESET {
+ FMT5_SOFT_RESET_0 = 0x0,
+ FMT5_SOFT_RESET_1 = 0x1,
+} FMT5_SOFT_RESET;
+typedef enum MVP_SOFT_RESET {
+ MVP_SOFT_RESET_0 = 0x0,
+ MVP_SOFT_RESET_1 = 0x1,
+} MVP_SOFT_RESET;
+typedef enum ABM_SOFT_RESET {
+ ABM_SOFT_RESET_0 = 0x0,
+ ABM_SOFT_RESET_1 = 0x1,
+} ABM_SOFT_RESET;
+typedef enum DVO_SOFT_RESET {
+ DVO_SOFT_RESET_0 = 0x0,
+ DVO_SOFT_RESET_1 = 0x1,
+} DVO_SOFT_RESET;
+typedef enum DIGA_FE_SOFT_RESET {
+ DIGA_FE_SOFT_RESET_0 = 0x0,
+ DIGA_FE_SOFT_RESET_1 = 0x1,
+} DIGA_FE_SOFT_RESET;
+typedef enum DIGA_BE_SOFT_RESET {
+ DIGA_BE_SOFT_RESET_0 = 0x0,
+ DIGA_BE_SOFT_RESET_1 = 0x1,
+} DIGA_BE_SOFT_RESET;
+typedef enum DIGB_FE_SOFT_RESET {
+ DIGB_FE_SOFT_RESET_0 = 0x0,
+ DIGB_FE_SOFT_RESET_1 = 0x1,
+} DIGB_FE_SOFT_RESET;
+typedef enum DIGB_BE_SOFT_RESET {
+ DIGB_BE_SOFT_RESET_0 = 0x0,
+ DIGB_BE_SOFT_RESET_1 = 0x1,
+} DIGB_BE_SOFT_RESET;
+typedef enum DIGC_FE_SOFT_RESET {
+ DIGC_FE_SOFT_RESET_0 = 0x0,
+ DIGC_FE_SOFT_RESET_1 = 0x1,
+} DIGC_FE_SOFT_RESET;
+typedef enum DIGC_BE_SOFT_RESET {
+ DIGC_BE_SOFT_RESET_0 = 0x0,
+ DIGC_BE_SOFT_RESET_1 = 0x1,
+} DIGC_BE_SOFT_RESET;
+typedef enum DIGD_FE_SOFT_RESET {
+ DIGD_FE_SOFT_RESET_0 = 0x0,
+ DIGD_FE_SOFT_RESET_1 = 0x1,
+} DIGD_FE_SOFT_RESET;
+typedef enum DIGD_BE_SOFT_RESET {
+ DIGD_BE_SOFT_RESET_0 = 0x0,
+ DIGD_BE_SOFT_RESET_1 = 0x1,
+} DIGD_BE_SOFT_RESET;
+typedef enum DIGE_FE_SOFT_RESET {
+ DIGE_FE_SOFT_RESET_0 = 0x0,
+ DIGE_FE_SOFT_RESET_1 = 0x1,
+} DIGE_FE_SOFT_RESET;
+typedef enum DIGE_BE_SOFT_RESET {
+ DIGE_BE_SOFT_RESET_0 = 0x0,
+ DIGE_BE_SOFT_RESET_1 = 0x1,
+} DIGE_BE_SOFT_RESET;
+typedef enum DIGF_FE_SOFT_RESET {
+ DIGF_FE_SOFT_RESET_0 = 0x0,
+ DIGF_FE_SOFT_RESET_1 = 0x1,
+} DIGF_FE_SOFT_RESET;
+typedef enum DIGF_BE_SOFT_RESET {
+ DIGF_BE_SOFT_RESET_0 = 0x0,
+ DIGF_BE_SOFT_RESET_1 = 0x1,
+} DIGF_BE_SOFT_RESET;
+typedef enum DIGG_FE_SOFT_RESET {
+ DIGG_FE_SOFT_RESET_0 = 0x0,
+ DIGG_FE_SOFT_RESET_1 = 0x1,
+} DIGG_FE_SOFT_RESET;
+typedef enum DIGG_BE_SOFT_RESET {
+ DIGG_BE_SOFT_RESET_0 = 0x0,
+ DIGG_BE_SOFT_RESET_1 = 0x1,
+} DIGG_BE_SOFT_RESET;
+typedef enum DPDBG_SOFT_RESET {
+ DPDBG_SOFT_RESET_0 = 0x0,
+ DPDBG_SOFT_RESET_1 = 0x1,
+} DPDBG_SOFT_RESET;
+typedef enum DIGLPA_FE_SOFT_RESET {
+ DIGLPA_FE_SOFT_RESET_0 = 0x0,
+ DIGLPA_FE_SOFT_RESET_1 = 0x1,
+} DIGLPA_FE_SOFT_RESET;
+typedef enum DIGLPA_BE_SOFT_RESET {
+ DIGLPA_BE_SOFT_RESET_0 = 0x0,
+ DIGLPA_BE_SOFT_RESET_1 = 0x1,
+} DIGLPA_BE_SOFT_RESET;
+typedef enum DIGLPB_FE_SOFT_RESET {
+ DIGLPB_FE_SOFT_RESET_0 = 0x0,
+ DIGLPB_FE_SOFT_RESET_1 = 0x1,
+} DIGLPB_FE_SOFT_RESET;
+typedef enum DIGLPB_BE_SOFT_RESET {
+ DIGLPB_BE_SOFT_RESET_0 = 0x0,
+ DIGLPB_BE_SOFT_RESET_1 = 0x1,
+} DIGLPB_BE_SOFT_RESET;
+typedef enum GENERICA_STEREOSYNC_SEL {
+ GENERICA_STEREOSYNC_SEL_D1 = 0x0,
+ GENERICA_STEREOSYNC_SEL_D2 = 0x1,
+ GENERICA_STEREOSYNC_SEL_D3 = 0x2,
+ GENERICA_STEREOSYNC_SEL_D4 = 0x3,
+ GENERICA_STEREOSYNC_SEL_D5 = 0x4,
+ GENERICA_STEREOSYNC_SEL_D6 = 0x5,
+ GENERICA_STEREOSYNC_SEL_RESERVED = 0x6,
+} GENERICA_STEREOSYNC_SEL;
+typedef enum GENERICB_STEREOSYNC_SEL {
+ GENERICB_STEREOSYNC_SEL_D1 = 0x0,
+ GENERICB_STEREOSYNC_SEL_D2 = 0x1,
+ GENERICB_STEREOSYNC_SEL_D3 = 0x2,
+ GENERICB_STEREOSYNC_SEL_D4 = 0x3,
+ GENERICB_STEREOSYNC_SEL_D5 = 0x4,
+ GENERICB_STEREOSYNC_SEL_D6 = 0x5,
+ GENERICB_STEREOSYNC_SEL_RESERVED = 0x6,
+} GENERICB_STEREOSYNC_SEL;
+typedef enum DCO_DBG_BLOCK_SEL {
+ DCO_DBG_BLOCK_SEL_DCO = 0x0,
+ DCO_DBG_BLOCK_SEL_ABM = 0x1,
+ DCO_DBG_BLOCK_SEL_DVO = 0x2,
+ DCO_DBG_BLOCK_SEL_DAC = 0x3,
+ DCO_DBG_BLOCK_SEL_MVP = 0x4,
+ DCO_DBG_BLOCK_SEL_FMT0 = 0x5,
+ DCO_DBG_BLOCK_SEL_FMT1 = 0x6,
+ DCO_DBG_BLOCK_SEL_FMT2 = 0x7,
+ DCO_DBG_BLOCK_SEL_FMT3 = 0x8,
+ DCO_DBG_BLOCK_SEL_FMT4 = 0x9,
+ DCO_DBG_BLOCK_SEL_FMT5 = 0xa,
+ DCO_DBG_BLOCK_SEL_DIGFE_A = 0xb,
+ DCO_DBG_BLOCK_SEL_DIGFE_B = 0xc,
+ DCO_DBG_BLOCK_SEL_DIGFE_C = 0xd,
+ DCO_DBG_BLOCK_SEL_DIGFE_D = 0xe,
+ DCO_DBG_BLOCK_SEL_DIGFE_E = 0xf,
+ DCO_DBG_BLOCK_SEL_DIGFE_F = 0x10,
+ DCO_DBG_BLOCK_SEL_DIGFE_G = 0x11,
+ DCO_DBG_BLOCK_SEL_DIGA = 0x12,
+ DCO_DBG_BLOCK_SEL_DIGB = 0x13,
+ DCO_DBG_BLOCK_SEL_DIGC = 0x14,
+ DCO_DBG_BLOCK_SEL_DIGD = 0x15,
+ DCO_DBG_BLOCK_SEL_DIGE = 0x16,
+ DCO_DBG_BLOCK_SEL_DIGF = 0x17,
+ DCO_DBG_BLOCK_SEL_DIGG = 0x18,
+ DCO_DBG_BLOCK_SEL_DPFE_A = 0x19,
+ DCO_DBG_BLOCK_SEL_DPFE_B = 0x1a,
+ DCO_DBG_BLOCK_SEL_DPFE_C = 0x1b,
+ DCO_DBG_BLOCK_SEL_DPFE_D = 0x1c,
+ DCO_DBG_BLOCK_SEL_DPFE_E = 0x1d,
+ DCO_DBG_BLOCK_SEL_DPFE_F = 0x1e,
+ DCO_DBG_BLOCK_SEL_DPFE_G = 0x1f,
+ DCO_DBG_BLOCK_SEL_DPA = 0x20,
+ DCO_DBG_BLOCK_SEL_DPB = 0x21,
+ DCO_DBG_BLOCK_SEL_DPC = 0x22,
+ DCO_DBG_BLOCK_SEL_DPD = 0x23,
+ DCO_DBG_BLOCK_SEL_DPE = 0x24,
+ DCO_DBG_BLOCK_SEL_DPF = 0x25,
+ DCO_DBG_BLOCK_SEL_DPG = 0x26,
+ DCO_DBG_BLOCK_SEL_AUX0 = 0x27,
+ DCO_DBG_BLOCK_SEL_AUX1 = 0x28,
+ DCO_DBG_BLOCK_SEL_AUX2 = 0x29,
+ DCO_DBG_BLOCK_SEL_AUX3 = 0x2a,
+ DCO_DBG_BLOCK_SEL_AUX4 = 0x2b,
+ DCO_DBG_BLOCK_SEL_AUX5 = 0x2c,
+ DCO_DBG_BLOCK_SEL_PERFMON_DCO = 0x2d,
+ DCO_DBG_BLOCK_SEL_AUDIO_OUT = 0x2e,
+ DCO_DBG_BLOCK_SEL_DIGLPFEA = 0x2f,
+ DCO_DBG_BLOCK_SEL_DIGLPFEB = 0x30,
+ DCO_DBG_BLOCK_SEL_DIGLPA = 0x31,
+ DCO_DBG_BLOCK_SEL_DIGLPB = 0x32,
+ DCO_DBG_BLOCK_SEL_DPLPFEA = 0x33,
+ DCO_DBG_BLOCK_SEL_DPLPFEB = 0x34,
+ DCO_DBG_BLOCK_SEL_DPLPA = 0x35,
+ DCO_DBG_BLOCK_SEL_DPLPB = 0x36,
+} DCO_DBG_BLOCK_SEL;
+typedef enum DCO_DBG_CLOCK_SEL {
+ DCO_DBG_CLOCK_SEL_DISPCLK = 0x0,
+ DCO_DBG_CLOCK_SEL_SCLK = 0x1,
+ DCO_DBG_CLOCK_SEL_MVPCLK = 0x2,
+ DCO_DBG_CLOCK_SEL_DVOCLK = 0x3,
+ DCO_DBG_CLOCK_SEL_DACCLK = 0x4,
+ DCO_DBG_CLOCK_SEL_REFCLK = 0x5,
+ DCO_DBG_CLOCK_SEL_SYMCLKA = 0x6,
+ DCO_DBG_CLOCK_SEL_SYMCLKB = 0x7,
+ DCO_DBG_CLOCK_SEL_SYMCLKC = 0x8,
+ DCO_DBG_CLOCK_SEL_SYMCLKD = 0x9,
+ DCO_DBG_CLOCK_SEL_SYMCLKE = 0xa,
+ DCO_DBG_CLOCK_SEL_SYMCLKF = 0xb,
+ DCO_DBG_CLOCK_SEL_SYMCLKG = 0xc,
+ DCO_DBG_CLOCK_SEL_RESERVED = 0xd,
+ DCO_DBG_CLOCK_SEL_AM0CLK = 0xe,
+ DCO_DBG_CLOCK_SEL_AM1CLK = 0xf,
+ DCO_DBG_CLOCK_SEL_AM2CLK = 0x10,
+ DCO_DBG_CLOCK_SEL_SYMCLKLPA = 0x11,
+ DCO_DBG_CLOCK_SEL_SYMCLKLPB = 0x12,
+} DCO_DBG_CLOCK_SEL;
+typedef enum DOUT_I2C_CONTROL_GO {
+ DOUT_I2C_CONTROL_STOP_TRANSFER = 0x0,
+ DOUT_I2C_CONTROL_START_TRANSFER = 0x1,
+} DOUT_I2C_CONTROL_GO;
+typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
+ DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x0,
+ DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 0x1,
+} DOUT_I2C_CONTROL_SOFT_RESET;
+typedef enum DOUT_I2C_CONTROL_SEND_RESET {
+ DOUT_I2C_CONTROL__NOT_SEND_RESET = 0x0,
+ DOUT_I2C_CONTROL__SEND_RESET = 0x1,
+} DOUT_I2C_CONTROL_SEND_RESET;
+typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
+ DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0x0,
+ DOUT_I2C_CONTROL_RESET_SW_STATUS = 0x1,
+} DOUT_I2C_CONTROL_SW_STATUS_RESET;
+typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
+ DOUT_I2C_CONTROL_SELECT_DDC1 = 0x0,
+ DOUT_I2C_CONTROL_SELECT_DDC2 = 0x1,
+ DOUT_I2C_CONTROL_SELECT_DDC3 = 0x2,
+ DOUT_I2C_CONTROL_SELECT_DDC4 = 0x3,
+ DOUT_I2C_CONTROL_SELECT_DDC5 = 0x4,
+ DOUT_I2C_CONTROL_SELECT_DDC6 = 0x5,
+ DOUT_I2C_CONTROL_SELECT_DDCVGA = 0x6,
+} DOUT_I2C_CONTROL_DDC_SELECT;
+typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
+ DOUT_I2C_CONTROL_TRANS0 = 0x0,
+ DOUT_I2C_CONTROL_TRANS0_TRANS1 = 0x1,
+ DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 0x2,
+ DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 0x3,
+} DOUT_I2C_CONTROL_TRANSACTION_COUNT;
+typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL {
+ DOUT_I2C_CONTROL_NORMAL_DEBUG = 0x0,
+ DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 0x1,
+} DOUT_I2C_CONTROL_DBG_REF_SEL;
+typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
+ DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0x0,
+ DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 0x1,
+ DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x2,
+ DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x3,
+} DOUT_I2C_ARBITRATION_SW_PRIORITY;
+typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
+ DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0x0,
+ DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 0x1,
+} DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO;
+typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
+ DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x0,
+ DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 0x1,
+} DOUT_I2C_ARBITRATION_ABORT_XFER;
+typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
+ DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x0,
+ DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 0x1,
+} DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ;
+typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
+ DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x0,
+ DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 0x1,
+} DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG;
+typedef enum DOUT_I2C_ACK {
+ DOUT_I2C_NO_ACK = 0x0,
+ DOUT_I2C_ACK_TO_CLEAN = 0x1,
+} DOUT_I2C_ACK;
+typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
+ DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0x0,
+ DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE= 0x1,
+ DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE= 0x2,
+ DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE= 0x3,
+} DOUT_I2C_DDC_SPEED_THRESHOLD;
+typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
+ DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR= 0x0,
+ DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 0x1,
+} DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN;
+typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
+ DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0x0,
+ DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 0x1,
+} DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL;
+typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
+ DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0x0,
+ DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 0x1,
+} DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE;
+typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
+ DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR= 0x0,
+ DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 0x1,
+} DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN;
+typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
+ DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0x0,
+ DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 0x1,
+} DOUT_I2C_TRANSACTION_STOP_ON_NACK;
+typedef enum DOUT_I2C_DATA_INDEX_WRITE {
+ DOUT_I2C_DATA__NOT_INDEX_WRITE = 0x0,
+ DOUT_I2C_DATA__INDEX_WRITE = 0x1,
+} DOUT_I2C_DATA_INDEX_WRITE;
+typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
+ DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION= 0x0,
+ DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION= 0x1,
+} DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET;
+typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
+ DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0x0,
+ DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 0x1,
+} DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE;
+typedef enum BLNDV_CONTROL_BLND_MODE {
+ BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x0,
+ BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x1,
+ BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x2,
+ BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x3,
+} BLNDV_CONTROL_BLND_MODE;
+typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE {
+ BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO= 0x0,
+ BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO= 0x1,
+ BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2,
+ BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x3,
+} BLNDV_CONTROL_BLND_STEREO_TYPE;
+typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY {
+ BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW = 0x0,
+ BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x1,
+} BLNDV_CONTROL_BLND_STEREO_POLARITY;
+typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN {
+ BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x0,
+ BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x1,
+} BLNDV_CONTROL_BLND_FEEDTHROUGH_EN;
+typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE {
+ BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA= 0x0,
+ BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN= 0x1,
+ BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x2,
+ BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x3,
+} BLNDV_CONTROL_BLND_ALPHA_MODE;
+typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE {
+ BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x0,
+ BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x1,
+} BLNDV_CONTROL_BLND_MULTIPLIED_MODE;
+typedef enum BLNDV_SM_CONTROL2_SM_MODE {
+ BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x0,
+ BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x2,
+ BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x4,
+ BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING= 0x6,
+} BLNDV_SM_CONTROL2_SM_MODE;
+typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE {
+ BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x0,
+ BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x1,
+} BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE;
+typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE {
+ BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x0,
+ BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x1,
+} BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE;
+typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
+ BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE= 0x0,
+ BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED= 0x1,
+ BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2,
+ BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH= 0x3,
+} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
+typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
+ BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x0,
+ BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x1,
+ BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW= 0x2,
+ BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH= 0x3,
+} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
+typedef enum BLNDV_CONTROL2_PTI_ENABLE {
+ BLNDV_CONTROL2_PTI_ENABLE_FALSE = 0x0,
+ BLNDV_CONTROL2_PTI_ENABLE_TRUE = 0x1,
+} BLNDV_CONTROL2_PTI_ENABLE;
+typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
+ BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x0,
+ BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x1,
+} BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
+typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
+ BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x0,
+ BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x1,
+} BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
+typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
+ BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE= 0x0,
+ BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE= 0x1,
+} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
+typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
+ BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE= 0x0,
+ BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE= 0x1,
+} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
+typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
+ BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE= 0x0,
+ BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE= 0x1,
+} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
+typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
+ BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE= 0x0,
+ BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE= 0x1,
+} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
+typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
+ BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE= 0x0,
+ BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE= 0x1,
+} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
+typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
+ BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE= 0x0,
+ BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE= 0x1,
+} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
+typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
+ BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x0,
+ BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x1,
+} BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
+typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
+ BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE= 0x0,
+ BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x1,
+} BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
+typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
+ BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE= 0x0,
+ BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x1,
+} BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
+typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT {
+ BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x0,
+ BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x1,
+} BLNDV_DEBUG_BLND_CNV_MUX_SELECT;
+typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
+ BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE= 0x0,
+ BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE= 0x1,
+} BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
+
+#endif /* DCE_11_0_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h
new file mode 100644
index 000000000000..a438c2b6e280
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h
@@ -0,0 +1,17557 @@
+/*
+ * DCE_11_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef DCE_11_0_SH_MASK_H
+#define DCE_11_0_SH_MASK_H
+
+#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
+#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
+#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
+#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
+#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
+#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
+#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
+#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
+#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
+#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
+#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000
+#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT 0x1d
+#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xc0000000
+#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x1
+#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x0
+#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x1
+#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x0
+#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK 0xffffff
+#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT 0x0
+#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS_MASK 0x3000000
+#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS__SHIFT 0x18
+#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000
+#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x1c
+#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK 0x20000000
+#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x1d
+#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xc0000000
+#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x1
+#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x0
+#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x1
+#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x0
+#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK 0xffffff
+#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT 0x0
+#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS_MASK 0x3000000
+#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS__SHIFT 0x18
+#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000
+#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x1c
+#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK 0x20000000
+#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT 0x1d
+#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xc0000000
+#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DCFEV0_PG_CONFIG__DCFEV0_POWER_FORCEON_MASK 0x1
+#define DCFEV0_PG_CONFIG__DCFEV0_POWER_FORCEON__SHIFT 0x0
+#define DCFEV0_PG_ENABLE__DCFEV0_POWER_GATE_MASK 0x1
+#define DCFEV0_PG_ENABLE__DCFEV0_POWER_GATE__SHIFT 0x0
+#define DCFEV0_PG_STATUS__DCFEV0_PGFSM_READ_DATA_MASK 0xffffff
+#define DCFEV0_PG_STATUS__DCFEV0_PGFSM_READ_DATA__SHIFT 0x0
+#define DCFEV0_PG_STATUS__DCFEV0_DEBUG_PWR_STATUS_MASK 0x3000000
+#define DCFEV0_PG_STATUS__DCFEV0_DEBUG_PWR_STATUS__SHIFT 0x18
+#define DCFEV0_PG_STATUS__DCFEV0_DESIRED_PWR_STATE_MASK 0x10000000
+#define DCFEV0_PG_STATUS__DCFEV0_DESIRED_PWR_STATE__SHIFT 0x1c
+#define DCFEV0_PG_STATUS__DCFEV0_REQUESTED_PWR_STATE_MASK 0x20000000
+#define DCFEV0_PG_STATUS__DCFEV0_REQUESTED_PWR_STATE__SHIFT 0x1d
+#define DCFEV0_PG_STATUS__DCFEV0_PGFSM_PWR_STATUS_MASK 0xc0000000
+#define DCFEV0_PG_STATUS__DCFEV0_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_UP_INT_OCCURRED_MASK 0x1
+#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0x0
+#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x2
+#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x1
+#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_UP_INT_OCCURRED_MASK 0x4
+#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0x2
+#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x8
+#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3
+#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_UP_INT_OCCURRED_MASK 0x10
+#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0x4
+#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x20
+#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x5
+#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_UP_INT_OCCURRED_MASK 0x40
+#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0x6
+#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x80
+#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x7
+#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED_MASK 0x100
+#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x8
+#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x200
+#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x9
+#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_UP_INT_OCCURRED_MASK 0x400
+#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0xa
+#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x800
+#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0xb
+#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_UP_INT_OCCURRED_MASK 0x1000
+#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_UP_INT_OCCURRED__SHIFT 0xc
+#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_DOWN_INT_OCCURRED_MASK 0x2000
+#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_DOWN_INT_OCCURRED__SHIFT 0xd
+#define DCPG_INTERRUPT_STATUS__DSI_POWER_UP_INT_OCCURRED_MASK 0x4000
+#define DCPG_INTERRUPT_STATUS__DSI_POWER_UP_INT_OCCURRED__SHIFT 0xe
+#define DCPG_INTERRUPT_STATUS__DSI_POWER_DOWN_INT_OCCURRED_MASK 0x8000
+#define DCPG_INTERRUPT_STATUS__DSI_POWER_DOWN_INT_OCCURRED__SHIFT 0xf
+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_MASK_MASK 0x1
+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_MASK__SHIFT 0x0
+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_CLEAR_MASK 0x2
+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_CLEAR__SHIFT 0x1
+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_MASK_MASK 0x4
+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x2
+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x8
+#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x3
+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_MASK_MASK 0x10
+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_MASK__SHIFT 0x4
+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_CLEAR_MASK 0x20
+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_CLEAR__SHIFT 0x5
+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_MASK_MASK 0x40
+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x6
+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x80
+#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x7
+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK_MASK 0x100
+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK__SHIFT 0x8
+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR_MASK 0x200
+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR__SHIFT 0x9
+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_MASK_MASK 0x400
+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_MASK__SHIFT 0xa
+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x800
+#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0xb
+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_MASK_MASK 0x1000
+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_MASK__SHIFT 0xc
+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_CLEAR_MASK 0x2000
+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xd
+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_MASK_MASK 0x4000
+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_MASK__SHIFT 0xe
+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x8000
+#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0xf
+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_MASK_MASK 0x10000
+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_MASK__SHIFT 0x10
+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_CLEAR_MASK 0x20000
+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x11
+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_MASK_MASK 0x40000
+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x12
+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x80000
+#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x13
+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_MASK_MASK 0x100000
+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_MASK__SHIFT 0x14
+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_CLEAR_MASK 0x200000
+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x15
+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_MASK_MASK 0x400000
+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x16
+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x800000
+#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17
+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_MASK_MASK 0x1000000
+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_MASK__SHIFT 0x18
+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_CLEAR_MASK 0x2000000
+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_CLEAR__SHIFT 0x19
+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_MASK_MASK 0x4000000
+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_MASK__SHIFT 0x1a
+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_CLEAR_MASK 0x8000000
+#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_CLEAR__SHIFT 0x1b
+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_MASK_MASK 0x10000000
+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_MASK__SHIFT 0x1c
+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_CLEAR_MASK 0x20000000
+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_CLEAR__SHIFT 0x1d
+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_MASK_MASK 0x40000000
+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_MASK__SHIFT 0x1e
+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_CLEAR_MASK 0x80000000
+#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_CLEAR__SHIFT 0x1f
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x1
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0
+#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK 0xffffffff
+#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT 0x0
+#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK 0xffffffff
+#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT 0x0
+#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK 0x1
+#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT 0x0
+#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x2
+#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT 0x1
+#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK 0x4
+#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x2
+#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK 0xffff0000
+#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x10
+#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK 0xff
+#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT 0x0
+#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x1ffff
+#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0
+#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x1ffff
+#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0
+#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x1ffff
+#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0
+#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x1ffff
+#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0
+#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x1ffff
+#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0
+#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x1ffff
+#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0
+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x1
+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0
+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x2
+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x4
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x8
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xffff0000
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x1
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x1
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x100
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x10000
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0xe0000
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x1000000
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f
+#define DC_ABM1_CNTL__ABM1_EN_MASK 0x1
+#define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0
+#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x700
+#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8
+#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000
+#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x1f
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0xf
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0xf00
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0xf0000
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x7fff
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x7ff0000
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x7fff
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x7ff0000
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x7fff
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x7ff0000
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x7fff
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x7ff0000
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x7fff
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x7ff0000
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x3ff
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x3ff0000
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x3ff
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x3ff0000
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x1
+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0
+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x100
+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8
+#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK 0x1
+#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT 0x0
+#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x100
+#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x8
+#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK 0x10000
+#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT 0x10
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x1
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x2
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x4
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x100
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x200
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x400
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x10000
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x1000000
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x3
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x100
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x1000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x30000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10
+#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x100000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x800000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x7000000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xffffffff
+#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0
+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x3ff
+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0
+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x3ff0000
+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10
+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x3ff
+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0
+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x3ff0000
+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10
+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0xffffff
+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0
+#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0xffffff
+#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x0
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x3ff
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x3ff0000
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0xffffff
+#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0
+#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0xffffff
+#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x1
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x1
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xffffffff
+#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0
+#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xffffffff
+#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0
+#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xffffffff
+#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0
+#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xffffffff
+#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0
+#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xffffffff
+#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x3ff
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x0
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0xffc00
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0xa
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3ff00000
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x14
+#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000
+#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f
+#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0xff
+#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x0
+#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffff
+#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x0
+#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x3ff
+#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
+#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x10000
+#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
+#define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x3fff
+#define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
+#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x3fff
+#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
+#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3fff0000
+#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
+#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x3fff
+#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
+#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3fff0000
+#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
+#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x1
+#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
+#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x10000
+#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
+#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x20000
+#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
+#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x3fff
+#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
+#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3fff0000
+#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
+#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x1
+#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
+#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x10000
+#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
+#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x20000
+#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
+#define CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x3fff
+#define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
+#define CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3fff0000
+#define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
+#define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x3fff
+#define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
+#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x3fff
+#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
+#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x3fff
+#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
+#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x10000
+#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
+#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x1
+#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
+#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x10
+#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
+#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100
+#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
+#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x1000
+#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
+#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x8000
+#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
+#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000
+#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x1
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x10
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x100
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x1000
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x1
+#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
+#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x10
+#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x3fff
+#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
+#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3fff0000
+#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
+#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x3fff
+#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
+#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3fff0000
+#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
+#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x1
+#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
+#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x3fff
+#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
+#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3fff0000
+#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
+#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x1
+#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
+#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x1
+#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
+#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x1e
+#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
+#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x3fff
+#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
+#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3fff0000
+#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x1f
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0xe0
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x100
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x400
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x3000
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x30000
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x300000
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
+#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x1
+#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x1f
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0xe0
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x100
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x400
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x3000
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x30000
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x300000
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
+#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x1
+#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x3
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x10
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x100
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x10000
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x1000000
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x1f
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x100
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x10000
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x1000000
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x3
+#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0xff00
+#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1fff0000
+#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
+#define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xffffffff
+#define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
+#define CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x1
+#define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x10
+#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
+#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x300
+#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
+#define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000
+#define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
+#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x2000
+#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
+#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x4000
+#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
+#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x10000
+#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x700000
+#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
+#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x1000000
+#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x18
+#define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000
+#define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
+#define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000
+#define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+#define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000
+#define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x1
+#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
+#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x100
+#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
+#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x10000
+#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
+#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x1
+#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
+#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x30000
+#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x1
+#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x2
+#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
+#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x1
+#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
+#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x2
+#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
+#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0xfff
+#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0xfff0000
+#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0xfff
+#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
+#define CRTC_STATUS__CRTC_V_BLANK_MASK 0x1
+#define CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
+#define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x2
+#define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
+#define CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x4
+#define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
+#define CRTC_STATUS__CRTC_V_UPDATE_MASK 0x8
+#define CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
+#define CRTC_STATUS__CRTC_V_START_LINE_MASK 0x10
+#define CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
+#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x20
+#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+#define CRTC_STATUS__CRTC_H_BLANK_MASK 0x10000
+#define CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
+#define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x20000
+#define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
+#define CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x40000
+#define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
+#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x3fff
+#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
+#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3fff0000
+#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
+#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x3fff
+#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
+#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0xffffff
+#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
+#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3fffffff
+#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
+#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3fffffff
+#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
+#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x1
+#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
+#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x1e
+#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
+#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x1
+#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
+#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x1
+#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x1
+#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x100
+#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x30000
+#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x1
+#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
+#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x100
+#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
+#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x10000
+#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
+#define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x100000
+#define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
+#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x3000000
+#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x3fff
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x8000
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x10000
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x20000
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+#define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x40000
+#define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+#define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x80000
+#define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
+#define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x100000
+#define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x1000000
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x1
+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x2
+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x4
+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x3
+#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x3fff
+#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3fff0000
+#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0xffffff
+#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x1
+#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
+#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x2
+#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
+#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x4
+#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
+#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100
+#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
+#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0xff000
+#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
+#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x1
+#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
+#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x2
+#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
+#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x10
+#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
+#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x20
+#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x100
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x10000
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x20000
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x1000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x2000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x4000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x8000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
+#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x1
+#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x1
+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x100
+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x10000
+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x1
+#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x1
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x700
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x10000
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0xf
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0xf0
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0xf00
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0xf000
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
+#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0xffff
+#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
+#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x3f0000
+#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
+#define CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x1
+#define CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
+#define CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x100
+#define CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
+#define CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x10000
+#define CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
+#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x7
+#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
+#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x30000
+#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
+#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x3
+#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
+#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00
+#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
+#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0xff
+#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
+#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x1
+#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
+#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x10
+#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
+#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x10000
+#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
+#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x100000
+#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
+#define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x1
+#define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0xff
+#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
+#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x10000
+#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
+#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x1
+#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
+#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x100
+#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x3ff
+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0xffc00
+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000
+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x3
+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x300
+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x30000
+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x3ff
+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0xffc00
+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000
+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x3
+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x300
+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x30000
+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x3ff
+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0xffc00
+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000
+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x3
+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x300
+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x30000
+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x3fff
+#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3fff0000
+#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x10
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x100
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x1000
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x10000
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x100000
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x1000000
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x3fff
+#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x100
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x1000
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x10000
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x100000
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x1000000
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x3fff
+#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x100
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x1000
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x10000
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x100000
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x1000000
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+#define CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x1
+#define CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
+#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x10
+#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
+#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x300
+#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
+#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x3000
+#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
+#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000
+#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x700000
+#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
+#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x7000000
+#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
+#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x3fff
+#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
+#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3fff0000
+#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
+#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x3fff
+#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
+#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3fff0000
+#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
+#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x3fff
+#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
+#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3fff0000
+#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
+#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x3fff
+#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
+#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3fff0000
+#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
+#define CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0xffff
+#define CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+#define CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xffff0000
+#define CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+#define CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0xffff
+#define CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x3fff
+#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
+#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3fff0000
+#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
+#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x3fff
+#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
+#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3fff0000
+#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
+#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x3fff
+#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
+#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3fff0000
+#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
+#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x3fff
+#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
+#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3fff0000
+#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
+#define CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0xffff
+#define CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+#define CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xffff0000
+#define CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+#define CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0xffff
+#define CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0xffff
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0xff0000
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x1000000
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x2000000
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x4000000
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x8000000
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x1
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x10
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x300
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x1000
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x10000
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x20000
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0xc0000
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0xff
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0xff00
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x10000
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x60000
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x80000
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x100000
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x800000
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
+#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x3fff
+#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
+#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3fff0000
+#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
+#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x3fff
+#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
+#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x1f0000
+#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
+#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000
+#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0xff
+#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x0
+#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffff
+#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x0
+#define DAC_ENABLE__DAC_ENABLE_MASK 0x1
+#define DAC_ENABLE__DAC_ENABLE__SHIFT 0x0
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x2
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x1
+#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0xc
+#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x2
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x10
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x4
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x20
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x5
+#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x100
+#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x8
+#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x7
+#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x0
+#define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x8
+#define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x3
+#define DAC_CRC_EN__DAC_CRC_EN_MASK 0x1
+#define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x0
+#define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x10000
+#define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x10
+#define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x1
+#define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x0
+#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB_MASK 0x100
+#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB__SHIFT 0x8
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x3ff
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x0
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0xffc00
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0xa
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3ff00000
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x14
+#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x3f
+#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x0
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x3ff
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x0
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0xffc00
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0xa
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3ff00000
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x14
+#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x3f
+#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x0
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x1
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x0
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x100
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x8
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x10000
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x10
+#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x7
+#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x0
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x3
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x0
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0xff00
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x8
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x70000
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x10
+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0xff
+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x0
+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x100
+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x8
+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0xff
+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x0
+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0xff00
+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x8
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x1
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x0
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x10
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x4
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x300
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x8
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x30000
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x10
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x3000000
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x18
+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x1
+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x0
+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x10000
+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x10
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x1
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x0
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x700
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x8
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY_MASK 0x1000000
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY__SHIFT 0x18
+#define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x3ff
+#define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x0
+#define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x1
+#define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x0
+#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x100
+#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x8
+#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x10000
+#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x10
+#define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x1000000
+#define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x18
+#define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x1
+#define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x0
+#define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x100
+#define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x8
+#define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x10000
+#define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x10
+#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x1
+#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x0
+#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x100
+#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x8
+#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x10000
+#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x10
+#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x20000
+#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x11
+#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x40000
+#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x12
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x1
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x0
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x2
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x1
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x4
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x2
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x8
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x3
+#define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x3
+#define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x0
+#define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x30000
+#define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x10
+#define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xffffffff
+#define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x0
+#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
+#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0xfc
+#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00
+#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0xf0000
+#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x3c00000
+#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000
+#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x1d
+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000
+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000
+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX_MASK 0xff
+#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA__SHIFT 0x0
+#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x1ff
+#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0xe00
+#define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9
+#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x3000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x4000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xe
+#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x8000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0xf
+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x1f0000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x10
+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x200000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x15
+#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x400000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x16
+#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x800000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x17
+#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x1000000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x18
+#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x2000000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x19
+#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x4000000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1a
+#define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x8000000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x1b
+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xe0000000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x3
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x4
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x30
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x40
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x300
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x400
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x3000
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x4000
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x30000
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x40000
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x300000
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x400000
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x3000000
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x4000000
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define PERFMON_CNTL__PERFMON_STATE_MASK 0x3
+#define PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL_MASK 0xfc
+#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL__SHIFT 0x2
+#define PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0xfffff00
+#define PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000
+#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000
+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000
+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000
+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x1
+#define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0
+#define PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x2
+#define PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x1
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x2
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x4
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x8
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x10
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x20
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x40
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x80
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x100
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x200
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x400
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x800
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x1000
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x2000
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x4000
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x8000
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xffff0000
+#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xffffffff
+#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define PERFMON_HI__PERFMON_HI_MASK 0xffff
+#define PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define PERFMON_HI__PERFMON_READ_SEL_MASK 0xe0000000
+#define PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define PERFMON_LOW__PERFMON_LOW_MASK 0xffffffff
+#define PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX_MASK 0xff
+#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX__SHIFT 0x0
+#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA_MASK 0xffffffff
+#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA__SHIFT 0x0
+#define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK 0x1
+#define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT 0x0
+#define REFCLK_CNTL__REFCLK_SRC_SEL_MASK 0x2
+#define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT 0x1
+#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY_MASK 0xf
+#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY__SHIFT 0x0
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x7
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0
+#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE_MASK 0x100
+#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE__SHIFT 0x8
+#define DCE_VERSION__MAJOR_VERSION_MASK 0xff
+#define DCE_VERSION__MAJOR_VERSION__SHIFT 0x0
+#define DCE_VERSION__MINOR_VERSION_MASK 0xff00
+#define DCE_VERSION__MINOR_VERSION__SHIFT 0x8
+#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE_MASK 0xffffffff
+#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE__SHIFT 0x0
+#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE_MASK 0x1
+#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE__SHIFT 0x0
+#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE_MASK 0xffffffff
+#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE__SHIFT 0x0
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x1
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xffffffff
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xffffffff
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xffffffff
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xffffffff
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xffffffff
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x1
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x100
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x200
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x30000
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x1000000
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x2000000
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xffffffff
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE_MASK 0x1
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE__SHIFT 0x0
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE_MASK 0x1ff0
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE__SHIFT 0x4
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED_MASK 0x10000
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED__SHIFT 0x10
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR_MASK 0x20000
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR__SHIFT 0x11
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE_MASK 0x100000
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE__SHIFT 0x14
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL_MASK 0x200000
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL__SHIFT 0x15
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_MASK 0xff000000
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT__SHIFT 0x18
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x1
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xffff0000
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10
+#define SMU_CONTROL__DISPLAY0_FORCE_VBI_MASK 0x1
+#define SMU_CONTROL__DISPLAY0_FORCE_VBI__SHIFT 0x0
+#define SMU_CONTROL__DISPLAY1_FORCE_VBI_MASK 0x2
+#define SMU_CONTROL__DISPLAY1_FORCE_VBI__SHIFT 0x1
+#define SMU_CONTROL__DISPLAY2_FORCE_VBI_MASK 0x4
+#define SMU_CONTROL__DISPLAY2_FORCE_VBI__SHIFT 0x2
+#define SMU_CONTROL__DISPLAY3_FORCE_VBI_MASK 0x8
+#define SMU_CONTROL__DISPLAY3_FORCE_VBI__SHIFT 0x3
+#define SMU_CONTROL__DISPLAY4_FORCE_VBI_MASK 0x10
+#define SMU_CONTROL__DISPLAY4_FORCE_VBI__SHIFT 0x4
+#define SMU_CONTROL__DISPLAY5_FORCE_VBI_MASK 0x20
+#define SMU_CONTROL__DISPLAY5_FORCE_VBI__SHIFT 0x5
+#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI_MASK 0x40
+#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI__SHIFT 0x6
+#define SMU_CONTROL__SMU_DC_INT_CLEAR_MASK 0x10000
+#define SMU_CONTROL__SMU_DC_INT_CLEAR__SHIFT 0x10
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x1
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x10
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10
+#define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x1
+#define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x0
+#define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x10
+#define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x4
+#define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x1
+#define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x0
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x1
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x2
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1
+#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x4
+#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x2
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x8
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x10
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4
+#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x20
+#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x5
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x40
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6
+#define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE_MASK 0x80
+#define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE__SHIFT 0x7
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x100
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x20000
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x40000
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x80000
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13
+#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x200000
+#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x400000
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16
+#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE_MASK 0x800000
+#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE__SHIFT 0x17
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x4000000
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x8000000
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK 0x1
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT 0x0
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK 0x2
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT 0x1
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK 0x4
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT 0x2
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK 0x8
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT 0x3
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK 0x10
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT 0x4
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK 0x20
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT 0x5
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK 0x40
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT 0x6
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_FE_GATE_DISABLE_MASK 0x100
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_FE_GATE_DISABLE__SHIFT 0x8
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE_MASK 0x200
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE__SHIFT 0x9
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK 0x10000
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT 0x10
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK 0x20000
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT 0x11
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK 0x40000
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT 0x12
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK 0x80000
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT 0x13
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK 0x100000
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT 0x14
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK 0x200000
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT 0x15
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK 0x400000
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT 0x16
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_GATE_DISABLE_MASK 0x1000000
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_GATE_DISABLE__SHIFT 0x18
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_GATE_DISABLE_MASK 0x2000000
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_GATE_DISABLE__SHIFT 0x19
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0xf
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0xff0
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0xf
+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x0
+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0xff0
+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE_MASK 0x1000
+#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE__SHIFT 0xc
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0xf
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0xff0
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0xf
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0xff0
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK 0xf
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT 0x0
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK 0xff0
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xffffffff
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0
+#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x1
+#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x0
+#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x30
+#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x4
+#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x1
+#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x0
+#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x30
+#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x4
+#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x1
+#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x0
+#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x30
+#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x4
+#define PHYPLL_PIXCLK_CNTL__PHYPLL_PIXCLK_RESYNC_ENABLE_MASK 0x1
+#define PHYPLL_PIXCLK_CNTL__PHYPLL_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
+#define PHYPLL_PIXCLK_CNTL__DCCG_DEEP_COLOR_CNTL_PHYPLL_PIXCLK_MASK 0x30
+#define PHYPLL_PIXCLK_CNTL__DCCG_DEEP_COLOR_CNTL_PHYPLL_PIXCLK__SHIFT 0x4
+#define PHYPLL_PIXCLK_CNTL__PIXEL_RATE_PHYPLL_SEL_MASK 0x100
+#define PHYPLL_PIXCLK_CNTL__PIXEL_RATE_PHYPLL_SEL__SHIFT 0x8
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x7f
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x7f00
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x10000
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x20000
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x100
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x1ffff
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x3fff
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0xf0000
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x100000
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0xe000000
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x1
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x1
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x2
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x4
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x8
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x10
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4
+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x20
+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x40
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x80
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7
+#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x700
+#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x8
+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xfffff800
+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK 0x1
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT 0x0
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK 0x2
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT 0x1
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x3
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x10
+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4
+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x20
+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x100
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x8
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x200
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x9
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0xc000
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0xfff0000
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xffffffff
+#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0
+#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xffffffff
+#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x3
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x10
+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4
+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x20
+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x100
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x8
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x200
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x9
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0xc000
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0xfff0000
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xffffffff
+#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0
+#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xffffffff
+#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x3
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x10
+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4
+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x20
+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x100
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x8
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x200
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x9
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0xc000
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0xfff0000
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xffffffff
+#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0
+#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xffffffff
+#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x3
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x10
+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4
+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x20
+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x100
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x8
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x200
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x9
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0xc000
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0xfff0000
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xffffffff
+#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0
+#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xffffffff
+#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x3
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x10
+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x4
+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK 0x20
+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT 0x5
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x100
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x8
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x200
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x9
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0xc000
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0xfff0000
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xffffffff
+#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x0
+#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xffffffff
+#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x0
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x3
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x10
+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x4
+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK 0x20
+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT 0x5
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x100
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x8
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x200
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x9
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0xc000
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0xfff0000
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xffffffff
+#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x0
+#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xffffffff
+#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x0
+#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_SOURCE_MASK 0x3
+#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x1
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0
+#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK 0x2
+#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT 0x1
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x4
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x8
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x10
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x100
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x1000
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x2000
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x4000
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x8000
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x10000
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x20000
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x40000
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x80000
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x100000
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x200000
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x1
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x10
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x700
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x1
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x10
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x700
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x1
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x10
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x700
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x1
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x10
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x700
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x1
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x10
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x700
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x1
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x10
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x700
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE_MASK 0x1
+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN_MASK 0x10
+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC_MASK 0x700
+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC__SHIFT 0x8
+#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN_MASK 0x10
+#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN__SHIFT 0x4
+#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC_MASK 0x700
+#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC__SHIFT 0x8
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x7
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x30
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x3000
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x10000
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x100000
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x1000000
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xffffffff
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xffffffff
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xffffffff
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xffffffff
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0
+#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK 0xff
+#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT 0x0
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x1ff
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x1000
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x1ff0000
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c
+#define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x7f
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x7f00
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x18000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x20000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x40000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x80000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x100000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x14
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x200000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x15
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x400000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x16
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7f000000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x18
+#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK 0xffffffff
+#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT 0x0
+#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK 0xffffffff
+#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT 0x0
+#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK 0xffffffff
+#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT 0x0
+#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK 0xffffffff
+#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT 0x0
+#define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL_MASK 0xffffffff
+#define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL__SHIFT 0x0
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK 0x1f
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT 0x0
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK 0x3e0
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT 0x5
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK 0x1000
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT 0xc
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK 0xf8000
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT 0xf
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK 0x1f00000
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT 0x14
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK 0x10000000
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT 0x1c
+#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK 0x1f
+#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT 0x0
+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL_MASK 0x800000
+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL__SHIFT 0x17
+#define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL_MASK 0x1f000000
+#define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL__SHIFT 0x18
+#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK 0xffffffff
+#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT 0x0
+#define DMIF_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define DMIF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define DMIF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define DMIF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x3
+#define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x0
+#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x4
+#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x2
+#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x10
+#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x4
+#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x700
+#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x8
+#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN_MASK 0x800
+#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN__SHIFT 0xb
+#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0xf000
+#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0xc
+#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x3f0000
+#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x10
+#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1f000000
+#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x18
+#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000
+#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x1d
+#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0xff
+#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x0
+#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0xff00
+#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x10000
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x10
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x20000
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x11
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0xf00000
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x14
+#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0xf000000
+#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x18
+#define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000
+#define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x1c
+#define DMIF_STATUS__DMIF_MC_LATENCY_TAP_POINT_MASK 0x60000000
+#define DMIF_STATUS__DMIF_MC_LATENCY_TAP_POINT__SHIFT 0x1d
+#define DMIF_STATUS__DMIF_MC_LATENCY_REQ_TYPE_MASK 0x80000000
+#define DMIF_STATUS__DMIF_MC_LATENCY_REQ_TYPE__SHIFT 0x1f
+#define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK 0xffffffff
+#define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT 0x0
+#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0xffff
+#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x0
+#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xffff0000
+#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x10
+#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
+#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
+#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
+#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
+#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
+#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
+#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
+#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
+#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define DMIF_P_VMID__P_VMID_PIPE0_MASK 0xf
+#define DMIF_P_VMID__P_VMID_PIPE0__SHIFT 0x0
+#define DMIF_P_VMID__P_VMID_PIPE1_MASK 0xf0
+#define DMIF_P_VMID__P_VMID_PIPE1__SHIFT 0x4
+#define DMIF_P_VMID__P_VMID_PIPE2_MASK 0xf00
+#define DMIF_P_VMID__P_VMID_PIPE2__SHIFT 0x8
+#define DMIF_P_VMID__P_VMID_PIPE3_MASK 0xf000
+#define DMIF_P_VMID__P_VMID_PIPE3__SHIFT 0xc
+#define DMIF_P_VMID__P_VMID_PIPE4_MASK 0xf0000
+#define DMIF_P_VMID__P_VMID_PIPE4__SHIFT 0x10
+#define DMIF_P_VMID__P_VMID_PIPE5_MASK 0xf00000
+#define DMIF_P_VMID__P_VMID_PIPE5__SHIFT 0x14
+#define DMIF_P_VMID__P_VMID_PIPE6_MASK 0xf000000
+#define DMIF_P_VMID__P_VMID_PIPE6__SHIFT 0x18
+#define DMIF_P_VMID__P_VMID_PIPE7_MASK 0xf0000000
+#define DMIF_P_VMID__P_VMID_PIPE7__SHIFT 0x1c
+#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN_MASK 0x1
+#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN__SHIFT 0x0
+#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL_MASK 0xf0
+#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL__SHIFT 0x4
+#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK 0xff
+#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT 0x0
+#define DMIF_DEBUG02_CORE0__DB_DATA_MASK 0xffff
+#define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT 0x0
+#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK 0x10000
+#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT 0x10
+#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK 0xffe0000
+#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT 0x11
+#define DMIF_DEBUG02_CORE1__DB_DATA_MASK 0xffff
+#define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT 0x0
+#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK 0x10000
+#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT 0x10
+#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK 0xffe0000
+#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT 0x11
+#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000
+#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x1c
+#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x1
+#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x0
+#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x2
+#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x1
+#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x4
+#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x2
+#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x8
+#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x3
+#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x10
+#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x4
+#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x20
+#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x5
+#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x100
+#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x8
+#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x200
+#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x9
+#define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
+#define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
+#define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
+#define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
+#define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
+#define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
+#define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE6_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
+#define PIPE6_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE7_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
+#define PIPE7_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define DVMM_REG_RD_STATUS__DVMM_REG_RD_STATUS_MASK 0x1
+#define DVMM_REG_RD_STATUS__DVMM_REG_RD_STATUS__SHIFT 0x0
+#define DVMM_REG_RD_DATA__DVMM_REG_RD_DATA_MASK 0xffffffff
+#define DVMM_REG_RD_DATA__DVMM_REG_RD_DATA__SHIFT 0x0
+#define DVMM_PTE_REQ__MAX_PTEREQ_TO_ISSUE_MASK 0xff
+#define DVMM_PTE_REQ__MAX_PTEREQ_TO_ISSUE__SHIFT 0x0
+#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_INT_MASK 0xff00
+#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_INT__SHIFT 0x8
+#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER_MASK 0x3f0000
+#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER__SHIFT 0x10
+#define DVMM_CNTL__PDE_CACHE_INVALIDATE_CNTL_MASK 0x3
+#define DVMM_CNTL__PDE_CACHE_INVALIDATE_CNTL__SHIFT 0x0
+#define DVMM_CNTL__DEBUG_SYSTEM_ACCESS_MODE_MASK 0x30
+#define DVMM_CNTL__DEBUG_SYSTEM_ACCESS_MODE__SHIFT 0x4
+#define DVMM_CNTL__FORCE_SYSTEM_ACCESS_MODE_MASK 0x80
+#define DVMM_CNTL__FORCE_SYSTEM_ACCESS_MODE__SHIFT 0x7
+#define DVMM_CNTL__DBG_DCE_VMID_MASK 0xf00
+#define DVMM_CNTL__DBG_DCE_VMID__SHIFT 0x8
+#define DVMM_CNTL__FORCE_DBG_DCE_VMID_MASK 0x8000
+#define DVMM_CNTL__FORCE_DBG_DCE_VMID__SHIFT 0xf
+#define DVMM_CNTL__OVERRIDE_SNOOP_MASK 0x20000
+#define DVMM_CNTL__OVERRIDE_SNOOP__SHIFT 0x11
+#define DVMM_CNTL__ENABLE_PDE_INVALIDATE_MASK 0x40000
+#define DVMM_CNTL__ENABLE_PDE_INVALIDATE__SHIFT 0x12
+#define DVMM_FAULT_STATUS__DVMM_FAULT_STATUS_MASK 0xffffffff
+#define DVMM_FAULT_STATUS__DVMM_FAULT_STATUS__SHIFT 0x0
+#define DVMM_FAULT_ADDR__DVMM_FAULT_ADDR_MASK 0xffffffff
+#define DVMM_FAULT_ADDR__DVMM_FAULT_ADDR__SHIFT 0x0
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x1
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x0
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x18
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x3
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0xe0
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x5
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x700
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x8
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x800
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0xb
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x7000
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0xc
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0xfff0000
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x10
+#define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK 0x3
+#define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT 0x0
+#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x10
+#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x4
+#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x100
+#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x8
+#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK 0xf000
+#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT 0xc
+#define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK 0xff0000
+#define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x10
+#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK 0x3f000000
+#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT 0x18
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0xff
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0
+#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK 0xff00
+#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT 0x8
+#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK 0xff
+#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT 0x0
+#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK 0xffffffff
+#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT 0x0
+#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff
+#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0
+#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK 0xffffffff
+#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT 0x0
+#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK 0xffffffff
+#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT 0x0
+#define MCIF_VMID__MCIF_WR_VMID_MASK 0xf
+#define MCIF_VMID__MCIF_WR_VMID__SHIFT 0x0
+#define MCIF_VMID__VIP_WR_VMID_MASK 0xf0
+#define MCIF_VMID__VIP_WR_VMID__SHIFT 0x4
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK 0x1
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT 0x0
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK 0x30
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT 0x4
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK 0xff00
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT 0x8
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK 0x70000
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT 0x10
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK 0x180000
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT 0x13
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x7e
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x1
+#define CC_DC_PIPE_DIS__DC_UNDERLAY_PIPE_DIS_MASK 0x3f0000
+#define CC_DC_PIPE_DIS__DC_UNDERLAY_PIPE_DIS__SHIFT 0x10
+#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK 0x1
+#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT 0x0
+#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK 0x10
+#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT 0x4
+#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK 0x100
+#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT 0x8
+#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK 0x1000
+#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT 0xc
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK 0x10000
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT 0x10
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK 0x100000
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT 0x14
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK 0x1000000
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT 0x18
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK 0x10000000
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT 0x1c
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0xfffff
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK 0xfff00000
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT 0x14
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0x7fff
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f
+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x1
+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0
+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x2
+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1
+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x4
+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2
+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x8
+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3
+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x10
+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4
+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x20
+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5
+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x40
+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6
+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x80
+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7
+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x100
+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8
+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x200
+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9
+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x400
+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa
+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x800
+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb
+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x1000
+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc
+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x2000
+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd
+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x4000
+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe
+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x3
+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0
+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x10
+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x20
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x40
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6
+#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE_MASK 0x3
+#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE__SHIFT 0x0
+#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE_MASK 0xc
+#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE__SHIFT 0x2
+#define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE_MASK 0x10
+#define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE__SHIFT 0x4
+#define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE_MASK 0x40
+#define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE__SHIFT 0x6
+#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK 0x100
+#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT 0x8
+#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE_MASK 0x600
+#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE__SHIFT 0x9
+#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE_MASK 0x800
+#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xb
+#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE_MASK 0x3000
+#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE__SHIFT 0xc
+#define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE_MASK 0xc000
+#define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE__SHIFT 0xe
+#define DCI_MEM_PWR_STATUS__MCIF_DWB_MEM_PWR_STATE_MASK 0x30000
+#define DCI_MEM_PWR_STATUS__MCIF_DWB_MEM_PWR_STATE__SHIFT 0x10
+#define DCI_MEM_PWR_STATUS__MCIF_CWB0_MEM_PWR_STATE_MASK 0xc0000
+#define DCI_MEM_PWR_STATUS__MCIF_CWB0_MEM_PWR_STATE__SHIFT 0x12
+#define DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE_MASK 0x300000
+#define DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE__SHIFT 0x14
+#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE_MASK 0x400000
+#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE__SHIFT 0x16
+#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x3000000
+#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0x18
+#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE_MASK 0xc000000
+#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE__SHIFT 0x1a
+#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE_MASK 0x10000000
+#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE__SHIFT 0x1c
+#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0x3
+#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0
+#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE_MASK 0xc
+#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE__SHIFT 0x2
+#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE_MASK 0x10
+#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE__SHIFT 0x4
+#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x60
+#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x5
+#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE_MASK 0x180
+#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE__SHIFT 0x7
+#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE_MASK 0x200
+#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE__SHIFT 0x9
+#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0xc00
+#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0xa
+#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE_MASK 0x3000
+#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE__SHIFT 0xc
+#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE_MASK 0x4000
+#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE__SHIFT 0xe
+#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x18000
+#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0xf
+#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK 0x60000
+#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT 0x11
+#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE_MASK 0x80000
+#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE__SHIFT 0x13
+#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0x300000
+#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x14
+#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE_MASK 0xc00000
+#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE__SHIFT 0x16
+#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE_MASK 0x1000000
+#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE__SHIFT 0x18
+#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x1f
+#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x0
+#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x20
+#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x5
+#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x40
+#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x6
+#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x80
+#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x7
+#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x100
+#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8
+#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x200
+#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x9
+#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x800
+#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0xb
+#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x2000
+#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0xd
+#define DCI_CLK_CNTL__VPCLK_POL_MASK 0x4000
+#define DCI_CLK_CNTL__VPCLK_POL__SHIFT 0xe
+#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x8000
+#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0xf
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x10000
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x10
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x20000
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x11
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x40000
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x12
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x80000
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x13
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x100000
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x14
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x200000
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x15
+#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK 0x400000
+#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT 0x16
+#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK 0x800000
+#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x17
+#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x1000000
+#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x18
+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_L_GATE_DIS_MASK 0x2000000
+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_L_GATE_DIS__SHIFT 0x19
+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_C_GATE_DIS_MASK 0x4000000
+#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_C_GATE_DIS__SHIFT 0x1a
+#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xf8000000
+#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x1b
+#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_DWB_GATE_DIS_MASK 0x1
+#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_DWB_GATE_DIS__SHIFT 0x0
+#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_DWB_GATE_DIS_MASK 0x2
+#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_DWB_GATE_DIS__SHIFT 0x1
+#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB0_GATE_DIS_MASK 0x4
+#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB0_GATE_DIS__SHIFT 0x2
+#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB0_GATE_DIS_MASK 0x8
+#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB0_GATE_DIS__SHIFT 0x3
+#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB1_GATE_DIS_MASK 0x10
+#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB1_GATE_DIS__SHIFT 0x4
+#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB1_GATE_DIS_MASK 0x80000000
+#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB1_GATE_DIS__SHIFT 0x1f
+#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE_MASK 0x3
+#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x0
+#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS_MASK 0x4
+#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS__SHIFT 0x2
+#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE_MASK 0x8
+#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x3
+#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS_MASK 0x10
+#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS__SHIFT 0x4
+#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE_MASK 0x20
+#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE__SHIFT 0x5
+#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS_MASK 0x40
+#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS__SHIFT 0x6
+#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK 0x80
+#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT 0x7
+#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK 0x100
+#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT 0x8
+#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK 0x600
+#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT 0x9
+#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK 0x800
+#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT 0xb
+#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK 0x1000
+#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT 0xc
+#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK 0x2000
+#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT 0xd
+#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE_MASK 0xc000
+#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE__SHIFT 0xe
+#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS_MASK 0x10000
+#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS__SHIFT 0x10
+#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE_MASK 0x60000
+#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE__SHIFT 0x11
+#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS_MASK 0x80000
+#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS__SHIFT 0x13
+#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE_MASK 0x300000
+#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE__SHIFT 0x14
+#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS_MASK 0x400000
+#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS__SHIFT 0x16
+#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE_MASK 0x1800000
+#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE__SHIFT 0x17
+#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS_MASK 0x2000000
+#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS__SHIFT 0x19
+#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE_MASK 0xc000000
+#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE__SHIFT 0x1a
+#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS_MASK 0x10000000
+#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS__SHIFT 0x1c
+#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE_MASK 0x20000000
+#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE__SHIFT 0x1d
+#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS_MASK 0x40000000
+#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS__SHIFT 0x1e
+#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE_MASK 0x3
+#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE__SHIFT 0x0
+#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS_MASK 0x4
+#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS__SHIFT 0x2
+#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE_MASK 0x18
+#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE__SHIFT 0x3
+#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS_MASK 0x20
+#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS__SHIFT 0x5
+#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE_MASK 0x40
+#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE__SHIFT 0x6
+#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS_MASK 0x80
+#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS__SHIFT 0x7
+#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE_MASK 0x300
+#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE__SHIFT 0x8
+#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS_MASK 0x400
+#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS__SHIFT 0xa
+#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE_MASK 0x1800
+#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE__SHIFT 0xb
+#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS_MASK 0x2000
+#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS__SHIFT 0xd
+#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE_MASK 0x4000
+#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE__SHIFT 0xe
+#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS_MASK 0x8000
+#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS__SHIFT 0xf
+#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE_MASK 0x30000
+#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE__SHIFT 0x10
+#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS_MASK 0x40000
+#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS__SHIFT 0x12
+#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE_MASK 0x180000
+#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE__SHIFT 0x13
+#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS_MASK 0x200000
+#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS__SHIFT 0x15
+#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE_MASK 0x400000
+#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE__SHIFT 0x16
+#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS_MASK 0x800000
+#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS__SHIFT 0x17
+#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE_MASK 0x3000000
+#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE__SHIFT 0x18
+#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS_MASK 0x4000000
+#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS__SHIFT 0x1a
+#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE_MASK 0x18000000
+#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE__SHIFT 0x1b
+#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS_MASK 0x20000000
+#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS__SHIFT 0x1d
+#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE_MASK 0x40000000
+#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE__SHIFT 0x1e
+#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS_MASK 0x80000000
+#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS__SHIFT 0x1f
+#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE_MASK 0x3
+#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE__SHIFT 0x0
+#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS_MASK 0x4
+#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS__SHIFT 0x2
+#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE_MASK 0x18
+#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE__SHIFT 0x3
+#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS_MASK 0x20
+#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS__SHIFT 0x5
+#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE_MASK 0x40
+#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE__SHIFT 0x6
+#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS_MASK 0x80
+#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS__SHIFT 0x7
+#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE_MASK 0x300
+#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE__SHIFT 0x8
+#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS_MASK 0x400
+#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS__SHIFT 0xa
+#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE_MASK 0x1800
+#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE__SHIFT 0xb
+#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS_MASK 0x2000
+#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS__SHIFT 0xd
+#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE_MASK 0x4000
+#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE__SHIFT 0xe
+#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS_MASK 0x8000
+#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS__SHIFT 0xf
+#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL_MASK 0x30000
+#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL__SHIFT 0x10
+#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL_MASK 0xc0000
+#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL__SHIFT 0x12
+#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL_MASK 0x300000
+#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL__SHIFT 0x14
+#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x400000
+#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT 0x16
+#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL_MASK 0x1800000
+#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL__SHIFT 0x17
+#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL_MASK 0x6000000
+#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL__SHIFT 0x19
+#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL_MASK 0x18000000
+#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL__SHIFT 0x1b
+#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL_MASK 0x60000000
+#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL__SHIFT 0x1d
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_FORCE_MASK 0x3
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_FORCE__SHIFT 0x0
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_DIS_MASK 0x4
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_DIS__SHIFT 0x2
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_FORCE_MASK 0x18
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_FORCE__SHIFT 0x3
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_DIS_MASK 0x20
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_DIS__SHIFT 0x5
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_FORCE_MASK 0xc0
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_FORCE__SHIFT 0x6
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_DIS_MASK 0x100
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_DIS__SHIFT 0x8
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_FORCE_MASK 0x600
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_FORCE__SHIFT 0x9
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_DIS_MASK 0x800
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_DIS__SHIFT 0xb
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_FORCE_MASK 0x3000
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_FORCE__SHIFT 0xc
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_DIS_MASK 0x4000
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_DIS__SHIFT 0xe
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_FORCE_MASK 0x18000
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_FORCE__SHIFT 0xf
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_DIS_MASK 0x20000
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_DIS__SHIFT 0x11
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_FORCE_MASK 0xc0000
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_FORCE__SHIFT 0x12
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_DIS_MASK 0x100000
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_DIS__SHIFT 0x14
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_FORCE_MASK 0x600000
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_FORCE__SHIFT 0x15
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_DIS_MASK 0x800000
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_DIS__SHIFT 0x17
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE_MEM_PWR_MODE_SEL_MASK 0x3000000
+#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE_MEM_PWR_MODE_SEL__SHIFT 0x18
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE0_PTE_PGMEM_STATE_MASK 0x3
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE0_PTE_PGMEM_STATE__SHIFT 0x0
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE1_PTE_PGMEM_STATE_MASK 0xc
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE1_PTE_PGMEM_STATE__SHIFT 0x2
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE2_PTE_PGMEM_STATE_MASK 0x30
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE2_PTE_PGMEM_STATE__SHIFT 0x4
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE3_PTE_PGMEM_STATE_MASK 0xc0
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE3_PTE_PGMEM_STATE__SHIFT 0x6
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE4_PTE_PGMEM_STATE_MASK 0x300
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE4_PTE_PGMEM_STATE__SHIFT 0x8
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE5_PTE_PGMEM_STATE_MASK 0xc00
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE5_PTE_PGMEM_STATE__SHIFT 0xa
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE6_PTE_PGMEM_STATE_MASK 0x3000
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE6_PTE_PGMEM_STATE__SHIFT 0xc
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE7_PTE_PGMEM_STATE_MASK 0xc000
+#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE7_PTE_PGMEM_STATE__SHIFT 0xe
+#define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x1
+#define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0
+#define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x2
+#define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x1
+#define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x4
+#define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x2
+#define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x8
+#define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x3
+#define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x10
+#define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x4
+#define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x20
+#define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x5
+#define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x40
+#define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x6
+#define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x80
+#define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x7
+#define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x100
+#define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x8
+#define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x200
+#define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x9
+#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET_MASK 0x400
+#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET__SHIFT 0xa
+#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET_MASK 0x800
+#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET__SHIFT 0xb
+#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x1000
+#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0xc
+#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET_MASK 0x10000
+#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET__SHIFT 0x10
+#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET_MASK 0x20000
+#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET__SHIFT 0x11
+#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET_MASK 0x40000
+#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET__SHIFT 0x12
+#define DCI_MISC__MCIF_WB_URG_OVRD_MASK 0x1
+#define DCI_MISC__MCIF_WB_URG_OVRD__SHIFT 0x0
+#define DCI_MISC__MCIF_WB_URG_LVL_MASK 0x1e
+#define DCI_MISC__MCIF_WB_URG_LVL__SHIFT 0x1
+#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK 0xff
+#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT 0x0
+#define DCI_DEBUG_CONFIG__DCI_DBG_EN_MASK 0x1
+#define DCI_DEBUG_CONFIG__DCI_DBG_EN__SHIFT 0x0
+#define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL_MASK 0xf0
+#define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL__SHIFT 0x4
+#define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL_MASK 0xf00
+#define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL__SHIFT 0x8
+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define DC_GENERICA__GENERICA_EN_MASK 0x1
+#define DC_GENERICA__GENERICA_EN__SHIFT 0x0
+#define DC_GENERICA__GENERICA_SEL_MASK 0xf80
+#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0xf000
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0xf0000
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0xf00000
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0xf000000
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18
+#define DC_GENERICB__GENERICB_EN_MASK 0x1
+#define DC_GENERICB__GENERICB_EN__SHIFT 0x0
+#define DC_GENERICB__GENERICB_SEL_MASK 0xf00
+#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0xf000
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0xf0000
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0xf00000
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0xf000000
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18
+#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0xf
+#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x0
+#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x30
+#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x4
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x3
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x300
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8
+#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x1
+#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x0
+#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x300
+#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x8
+#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x10000
+#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x10
+#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN_MASK 0x20000
+#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN__SHIFT 0x11
+#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE_MASK 0x80000000
+#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE__SHIFT 0x1f
+#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
+#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
+#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
+#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
+#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
+#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
+#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
+#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
+#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
+#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
+#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
+#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
+#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
+#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
+#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
+#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
+#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
+#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
+#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
+#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
+#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
+#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
+#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
+#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
+#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
+#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
+#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
+#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
+#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
+#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
+#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
+#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
+#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000
+#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
+#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000
+#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PFREQCHG_MASK 0x1
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PFREQCHG__SHIFT 0x0
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PIXVLD_RESET_MASK 0x10
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT_MASK 0x1000
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT_MASK 0x2000
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT_MASK 0x4000
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT_MASK 0x8000
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY_MASK 0x700000
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK_MASK 0x3000000
+#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PFREQCHG_MASK 0x1
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PFREQCHG__SHIFT 0x0
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PIXVLD_RESET_MASK 0x10
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT_MASK 0x1000
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT_MASK 0x2000
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT_MASK 0x4000
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT_MASK 0x8000
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY_MASK 0x700000
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK_MASK 0x3000000
+#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK__SHIFT 0x18
+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE_MASK 0x3
+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE_MASK 0x300
+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE_MASK 0x30000
+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE_MASK 0x10000000
+#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE_MASK 0x3
+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE_MASK 0x300
+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE_MASK 0x30000
+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE_MASK 0x10000000
+#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x1
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x100
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x200
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x400
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0xf0000
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0xf00000
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0xf000000
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x1e
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x1
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x100
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x200
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x400
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0xf0000
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0xf00000
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0xf000000
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x1e
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x1
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x100
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x200
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x400
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0xf0000
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0xf00000
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0xf000000
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x1e
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x1
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x100
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x200
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x400
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0xf0000
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0xf00000
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0xf000000
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x1e
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x1
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x100
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x200
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x400
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0xf0000
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0xf00000
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0xf000000
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x1e
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x1
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x100
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x200
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x400
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0xf0000
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0xf00000
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0xf000000
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x1e
+#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xffffffff
+#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x0
+#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x1
+#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x0
+#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x100
+#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x8
+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x200
+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x9
+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x400
+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0xa
+#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0xf0000
+#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x10
+#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0xf00000
+#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x14
+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0xf000000
+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x18
+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000
+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c
+#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x1
+#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x0
+#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x100
+#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x8
+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x200
+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x9
+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x400
+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0xa
+#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0xf0000
+#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x10
+#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0xf00000
+#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x14
+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0xf000000
+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x18
+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000
+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c
+#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE_MASK 0xf
+#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE__SHIFT 0x0
+#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET_MASK 0x20
+#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET__SHIFT 0x5
+#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS_MASK 0x300
+#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS__SHIFT 0x8
+#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE_MASK 0x7000
+#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE__SHIFT 0xc
+#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL_MASK 0x78000
+#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL__SHIFT 0xf
+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x7fff
+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x0
+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7fff0000
+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x10
+#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0xf
+#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x0
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x20
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x5
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x300
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x8
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x7000
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0xc
+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x7fff
+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x0
+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7fff0000
+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x10
+#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0xf
+#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x0
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x20
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x5
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x300
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x8
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x7000
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0xc
+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x7fff
+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x0
+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7fff0000
+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x10
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xf
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x0
+#define DCIO_WRCMD_DELAY__DAC_DELAY_MASK 0xf0
+#define DCIO_WRCMD_DELAY__DAC_DELAY__SHIFT 0x4
+#define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK 0xf00
+#define DCIO_WRCMD_DELAY__DPHY_DELAY__SHIFT 0x8
+#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK 0xf000
+#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT 0xc
+#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK 0x400
+#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT 0xa
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x2000
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0xc000
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x10000
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK 0xe0000
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT 0x11
+#define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x80000
+#define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x13
+#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x100000
+#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x14
+#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x200000
+#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x15
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x1
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x2
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x10
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x100
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x200
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x400
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x10000
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x20000
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x40000
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x1000000
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x2000000
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x4000000
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x1
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x2
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x4
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x8
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x10
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0xf00
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8
+#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0xfff
+#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0
+#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000
+#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0xff
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0xff00
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0xff0000
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xff000000
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0xff
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0xff00
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0xff0000
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x1000000
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18
+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0xffff
+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0
+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000
+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e
+#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000
+#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f
+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0xffff
+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0
+#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000
+#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x1c
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0xffff
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0xf0000
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x1
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x100
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x10000
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0xe0000
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x1000000
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x3
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x0
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x30
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x4
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x300
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x30000
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x10
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x300000
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x14
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x3000000
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x3
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x0
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x30
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x4
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x300
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x30000
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x10
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x300000
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x14
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x3000000
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18
+#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x7
+#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x0
+#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x700
+#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x8
+#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x70000
+#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x10
+#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x7
+#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x0
+#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x700
+#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x8
+#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x70000
+#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x10
+#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x7
+#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x0
+#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x700
+#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x8
+#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x70000
+#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x10
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x7
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x70
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x700
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x7000
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x70000
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x700000
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x7
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x0
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x70
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x4
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x700
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x8
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x7000
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0xc
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x70000
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x10
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x700000
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x14
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV_P_FLIP_MASK 0x3800000
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV_P_FLIP__SHIFT 0x17
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xffffffff
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x3f
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x700
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x3800
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x1c000
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0xe0000
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x700000
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x3800000
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x1f
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x20
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5
+#define DCIO_DEBUG__DCIO_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x0
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX_MASK 0x7
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX__SHIFT 0x0
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX_MASK 0x70
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX__SHIFT 0x4
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX_MASK 0x700
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX__SHIFT 0x8
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX_MASK 0x7000
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX__SHIFT 0xc
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX_MASK 0x70000
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX__SHIFT 0x10
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX_MASK 0x700000
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX__SHIFT 0x14
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK_MASK 0x7000000
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT 0x18
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK_MASK 0x70000000
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK__SHIFT 0x1c
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL_MASK 0x80000000
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL__SHIFT 0x1f
+#define DBG_OUT_CNTL__DBG_OUT_PIN_EN_MASK 0x1
+#define DBG_OUT_CNTL__DBG_OUT_PIN_EN__SHIFT 0x0
+#define DBG_OUT_CNTL__DBG_OUT_PIN_SEL_MASK 0x10
+#define DBG_OUT_CNTL__DBG_OUT_PIN_SEL__SHIFT 0x4
+#define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL_MASK 0x300
+#define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL__SHIFT 0x8
+#define DBG_OUT_CNTL__DBG_OUT_TEST_DATA_MASK 0xfff000
+#define DBG_OUT_CNTL__DBG_OUT_TEST_DATA__SHIFT 0xc
+#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN_MASK 0x1
+#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN__SHIFT 0x0
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x1
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x2
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x1
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x4
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x2
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x8
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x3
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x10
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x4
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x20
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x5
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x40
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x6
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x80
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x7
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x100
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x8
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x200
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x9
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x400
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0xa
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x800
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xb
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x1000
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0xc
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x2000
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xd
+#define DCIO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x10000
+#define DCIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x10
+#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK 0x100000
+#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT 0x14
+#define DCIO_SOFT_RESET__DPHY_SOFT_RESET_MASK 0x1000000
+#define DCIO_SOFT_RESET__DPHY_SOFT_RESET__SHIFT 0x18
+#define DCIO_SOFT_RESET__UNIPHYLPA_SOFT_RESET_MASK 0x10000000
+#define DCIO_SOFT_RESET__UNIPHYLPA_SOFT_RESET__SHIFT 0x1c
+#define DCIO_SOFT_RESET__DSYNCLPA_SOFT_RESET_MASK 0x20000000
+#define DCIO_SOFT_RESET__DSYNCLPA_SOFT_RESET__SHIFT 0x1d
+#define DCIO_SOFT_RESET__UNIPHYLPB_SOFT_RESET_MASK 0x40000000
+#define DCIO_SOFT_RESET__UNIPHYLPB_SOFT_RESET__SHIFT 0x1e
+#define DCIO_SOFT_RESET__DSYNCLPB_SOFT_RESET_MASK 0x80000000
+#define DCIO_SOFT_RESET__DSYNCLPB_SOFT_RESET__SHIFT 0x1f
+#define DCIO_DPHY_SEL__DPHY_LANE0_SEL_MASK 0x3
+#define DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT 0x0
+#define DCIO_DPHY_SEL__DPHY_LANE1_SEL_MASK 0xc
+#define DCIO_DPHY_SEL__DPHY_LANE1_SEL__SHIFT 0x2
+#define DCIO_DPHY_SEL__DPHY_LANE2_SEL_MASK 0x30
+#define DCIO_DPHY_SEL__DPHY_LANE2_SEL__SHIFT 0x4
+#define DCIO_DPHY_SEL__DPHY_LANE3_SEL_MASK 0xc0
+#define DCIO_DPHY_SEL__DPHY_LANE3_SEL__SHIFT 0x6
+#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0xff
+#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x0
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG_MASK 0x3
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG__SHIFT 0x0
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG_MASK 0xc
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x2
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG_MASK 0x30
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG__SHIFT 0x4
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_MASK 0xc0
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0__SHIFT 0x6
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0_MASK 0x300
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0__SHIFT 0x8
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_MASK 0xc00
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN__SHIFT 0xa
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C_MASK 0x1000
+#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C__SHIFT 0xc
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG_MASK 0x2000
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG__SHIFT 0xd
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX_MASK 0x4000
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX__SHIFT 0xe
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_MASK 0x8000
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0__SHIFT 0xf
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG_MASK 0x10000
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG__SHIFT 0x10
+#define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE_MASK 0x20000
+#define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE__SHIFT 0x11
+#define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE_MASK 0x40000
+#define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE__SHIFT 0x12
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX_MASK 0x80000
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX__SHIFT 0x13
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_MASK 0x100000
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN__SHIFT 0x14
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX_MASK 0x200000
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX__SHIFT 0x15
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG_MASK 0x400000
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG__SHIFT 0x16
+#define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE_MASK 0x800000
+#define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE__SHIFT 0x17
+#define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE_MASK 0x1000000
+#define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE__SHIFT 0x18
+#define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL_MASK 0x2000000
+#define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL__SHIFT 0x19
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX_MASK 0x4000000
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT 0x1a
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_MASK 0x8000000
+#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0__SHIFT 0x1b
+#define DCIO_DEBUG2__DCIO_DEBUG2_MASK 0xffffffff
+#define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT 0x0
+#define DCIO_DEBUG3__DCIO_DEBUG3_MASK 0xffffffff
+#define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT 0x0
+#define DCIO_DEBUG4__DCIO_DEBUG4_MASK 0xffffffff
+#define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT 0x0
+#define DCIO_DEBUG5__DCIO_DEBUG5_MASK 0xffffffff
+#define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT 0x0
+#define DCIO_DEBUG6__DCIO_DEBUG6_MASK 0xffffffff
+#define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT 0x0
+#define DCIO_DEBUG7__DCIO_DEBUG7_MASK 0xffffffff
+#define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT 0x0
+#define DCIO_DEBUG8__DCIO_DEBUG8_MASK 0xffffffff
+#define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT 0x0
+#define DCIO_DEBUG9__DCIO_DEBUG9_MASK 0xffffffff
+#define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT 0x0
+#define DCIO_DEBUGA__DCIO_DEBUGA_MASK 0xffffffff
+#define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT 0x0
+#define DCIO_DEBUGB__DCIO_DEBUGB_MASK 0xffffffff
+#define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT 0x0
+#define DCIO_DEBUGC__DCIO_DEBUGC_MASK 0xffffffff
+#define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT 0x0
+#define DCIO_DEBUGD__DCIO_DEBUGD_MASK 0xffffffff
+#define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT 0x0
+#define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT 0x0
+#define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT 0x0
+#define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT 0x0
+#define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT 0x0
+#define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT 0x0
+#define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT 0x0
+#define DCIO_DEBUG14__DCIO_DIGG_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUG14__DCIO_DIGG_DEBUG__SHIFT 0x0
+#define DCIO_DEBUG15__DCIO_DEBUG15_MASK 0xffffffff
+#define DCIO_DEBUG15__DCIO_DEBUG15__SHIFT 0x0
+#define DCIO_DEBUG16__DCIO_DEBUG16_MASK 0xffffffff
+#define DCIO_DEBUG16__DCIO_DEBUG16__SHIFT 0x0
+#define DCIO_DEBUG17__DCIO_DEBUG17_MASK 0xffffffff
+#define DCIO_DEBUG17__DCIO_DEBUG17__SHIFT 0x0
+#define DCIO_DEBUG18__DCIO_DEBUG18_MASK 0xffffffff
+#define DCIO_DEBUG18__DCIO_DEBUG18__SHIFT 0x0
+#define DCIO_DEBUG19__DCIO_DIGLPA_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUG19__DCIO_DIGLPA_DEBUG__SHIFT 0x0
+#define DCIO_DEBUG1A__DCIO_DIGLPB_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUG1A__DCIO_DIGLPB_DEBUG__SHIFT 0x0
+#define DCIO_DEBUG1B__DCIO_DEBUGHPD_MASK 0xffffffff
+#define DCIO_DEBUG1B__DCIO_DEBUGHPD__SHIFT 0x0
+#define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK 0xffffffff
+#define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT 0x0
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x1
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x2
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x4
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x10
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x20
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x40
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x100
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x200
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x400
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x1000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x2000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x4000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x10000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x20000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x40000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x100000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x200000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x400000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x1000000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x2000000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x4000000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x1
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x100
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x10000
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x100000
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x200000
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x400000
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x800000
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x1
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x100
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x10000
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x100000
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x200000
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x400000
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x800000
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x1
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x100
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x10000
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x100000
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x200000
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x400000
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x800000
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0xffffff
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x0
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x1f000000
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x18
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x20000000
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x1d
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xc0000000
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x1e
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0xffffff
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x0
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x1f000000
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x18
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x20000000
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x1d
+#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xc0000000
+#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x1e
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0xffffff
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x0
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x1f000000
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x18
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x20000000
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x1d
+#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xc0000000
+#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x1e
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0xffffff
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x0
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x1f000000
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x18
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x20000000
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x1d
+#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xc0000000
+#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x1e
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x1
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x10
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x40
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x100
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x1000
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x4000
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x10000
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10
+#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x100000
+#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x400000
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0xf000000
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xf0000000
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x1
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x100
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x1
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x100
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x1
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x100
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x1
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x10
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x40
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x100
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x1000
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x4000
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x10000
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10
+#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x100000
+#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x400000
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0xf000000
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xf0000000
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x1
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x100
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x1
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x100
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x1
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x100
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x1
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x10
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x40
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x100
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x1000
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x4000
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x10000
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10
+#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x100000
+#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x400000
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0xf000000
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xf0000000
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x1
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x100
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x1
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x100
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x1
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x100
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x1
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x10
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x40
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x100
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x1000
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x4000
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x10000
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10
+#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x100000
+#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x400000
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0xf000000
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xf0000000
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x1
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x100
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x1
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x100
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x1
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x100
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x1
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x10
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x40
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x100
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x1000
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x4000
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x10000
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10
+#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x100000
+#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x400000
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0xf000000
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xf0000000
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x1
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x100
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x1
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x100
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x1
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x100
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x1
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x10
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x40
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x100
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x1000
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x4000
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x10000
+#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x10
+#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x100000
+#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x14
+#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x400000
+#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0xf000000
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xf0000000
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x1
+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x100
+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x1
+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x100
+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x1
+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x100
+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x1
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x40
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x100
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x1000
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x4000
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x10000
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x100000
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x400000
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0xf000000
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xf0000000
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x1
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x100
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x1
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x100
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x1
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x100
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x1
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x0
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x10
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x4
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x40
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x6
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x100
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x8
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x1000
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0xc
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x4000
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0xe
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x7000000
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x18
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x1c
+#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x1
+#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x0
+#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x100
+#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x8
+#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x1
+#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x0
+#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x100
+#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x8
+#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x1
+#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x0
+#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x100
+#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x8
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x1
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x2
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x4
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x2
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x8
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x100
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x200
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x400
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xa
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x800
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x10000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x20000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x40000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x12
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x80000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x1000000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x2000000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x4000000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1a
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x8000000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x1
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x100
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x10000
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x1000000
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x1
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x100
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x10000
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x1000000
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x1
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x100
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x10000
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x1000000
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x1
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK 0x2
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT 0x1
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK 0x4
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT 0x2
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK 0x8
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT 0x3
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x10
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x40
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x100
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x200
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x400
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x10000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x20000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x40000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x100000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x200000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x400000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x1000000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x2000000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x4000000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0x40000000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x1
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x100
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x10000
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x1000000
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x4000000
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x1
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x2
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x4
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2
+#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK 0x8
+#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT 0x3
+#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK 0x10
+#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT 0x4
+#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK 0x20
+#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT 0x5
+#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x40
+#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6
+#define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK 0x80
+#define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT 0x7
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x100
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK 0x200
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT 0x9
+#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK 0x400
+#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT 0xa
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x10000
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK 0x20000
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT 0x11
+#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK 0x40000
+#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT 0x12
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x100000
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x14
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK 0x200000
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT 0x15
+#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK 0x400000
+#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT 0x16
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x1000000
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x18
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK 0x2000000
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT 0x19
+#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK 0x4000000
+#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT 0x1a
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK 0x20000000
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT 0x1d
+#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK 0x40000000
+#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT 0x1e
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x1
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x100
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x10000
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x1000000
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x4000000
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x1
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x10
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x40
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x100
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x1000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x4000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x10000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x100000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x400000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x1000000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x2000000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x4000000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x1
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x100
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x10000
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x1000000
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x1
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x2
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x100
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x10000
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x1000000
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x1
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x100
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x10000
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x1000000
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0xf
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0xf0
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK 0xf00
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT 0x8
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK 0xf000
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT 0xc
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK 0xf0000
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT 0x10
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK 0xf00000
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT 0x14
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0xf000000
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xf0000000
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0xf
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0xf0
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x700
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x7000
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0xf0000
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0xf00000
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xc0000000
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK 0x1
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT 0x0
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK 0x2
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT 0x1
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK 0x4
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT 0x2
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK 0x8
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT 0x3
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK 0x10
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT 0x4
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK 0x20
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT 0x5
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK 0x40
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT 0x6
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK 0x80
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT 0x7
+#define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x1000
+#define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0xc
+#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK 0x2000
+#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT 0xd
+#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x4000
+#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0xe
+#define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x10000
+#define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x10
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK 0x1
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK__SHIFT 0x0
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS_MASK 0x2
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS__SHIFT 0x1
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV_MASK 0x4
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV__SHIFT 0x2
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK 0x10
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK__SHIFT 0x4
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS_MASK 0x20
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS__SHIFT 0x5
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV_MASK 0x40
+#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV__SHIFT 0x6
+#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x1
+#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x0
+#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x2
+#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x1
+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x1
+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x0
+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x2
+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x1
+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x1
+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x0
+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x2
+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x1
+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0xf
+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x0
+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0xf0
+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x4
+#define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x1
+#define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x0
+#define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x2
+#define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1
+#define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0xf0
+#define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x4
+#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xffffffff
+#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x0
+#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define GRPH_ENABLE__GRPH_ENABLE_MASK 0x1
+#define GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
+#define GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x2
+#define GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1
+#define GRPH_CONTROL__GRPH_DEPTH_MASK 0x3
+#define GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
+#define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc
+#define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2
+#define GRPH_CONTROL__GRPH_Z_MASK 0x30
+#define GRPH_CONTROL__GRPH_Z__SHIFT 0x4
+#define GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0xc0
+#define GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x6
+#define GRPH_CONTROL__GRPH_FORMAT_MASK 0x700
+#define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
+#define GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x1800
+#define GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0xb
+#define GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0xe000
+#define GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0xd
+#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000
+#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
+#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000
+#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
+#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0xc0000
+#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x12
+#define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000
+#define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14
+#define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000
+#define GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18
+#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK 0x60000000
+#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT 0x1d
+#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000
+#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
+#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x100
+#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
+#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x10000
+#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
+#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3
+#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
+#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30
+#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
+#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0
+#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
+#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300
+#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
+#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0xc00
+#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
+#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x1
+#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
+#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xffffff00
+#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
+#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x1
+#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
+#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00
+#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
+#define GRPH_PITCH__GRPH_PITCH_MASK 0x7fff
+#define GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
+#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0xff
+#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff
+#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x3fff
+#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
+#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x3fff
+#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
+#define GRPH_X_START__GRPH_X_START_MASK 0x3fff
+#define GRPH_X_START__GRPH_X_START__SHIFT 0x0
+#define GRPH_Y_START__GRPH_Y_START_MASK 0x3fff
+#define GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
+#define GRPH_X_END__GRPH_X_END_MASK 0x7fff
+#define GRPH_X_END__GRPH_X_END__SHIFT 0x0
+#define GRPH_Y_END__GRPH_Y_END_MASK 0x7fff
+#define GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
+#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x1
+#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
+#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1
+#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
+#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2
+#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
+#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4
+#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
+#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8
+#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
+#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK 0x100
+#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT 0x8
+#define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000
+#define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
+#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000
+#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
+#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
+#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000
+#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
+#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x1
+#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
+#define GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x2
+#define GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1
+#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x10
+#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4
+#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x20
+#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5
+#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xffffff00
+#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
+#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x1
+#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
+#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x70
+#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
+#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x700
+#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
+#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0xf
+#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
+#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0
+#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
+#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x100
+#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
+#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x200
+#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
+#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1
+#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
+#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100
+#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
+#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1
+#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
+#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100
+#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
+#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff
+#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
+#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xffffff00
+#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
+#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x1ffc0
+#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
+#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0xff
+#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0xff
+#define GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x1
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x2
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x4
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x8
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x10
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
+#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0xffff
+#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
+#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xffff0000
+#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
+#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0xffff
+#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
+#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xffff0000
+#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
+#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0xffff
+#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
+#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xffff0000
+#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
+#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x3
+#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
+#define INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0xffff
+#define INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
+#define INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xffff0000
+#define INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
+#define INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0xffff
+#define INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
+#define INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xffff0000
+#define INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
+#define INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0xffff
+#define INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
+#define INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xffff0000
+#define INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
+#define INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0xffff
+#define INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
+#define INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xffff0000
+#define INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
+#define INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0xffff
+#define INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
+#define INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xffff0000
+#define INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
+#define INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0xffff
+#define INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
+#define INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xffff0000
+#define INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
+#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x7
+#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
+#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0xffff
+#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
+#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xffff0000
+#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
+#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0xffff
+#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
+#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xffff0000
+#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
+#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0xffff
+#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
+#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xffff0000
+#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
+#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0xffff
+#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
+#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xffff0000
+#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
+#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0xffff
+#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
+#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xffff0000
+#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
+#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0xffff
+#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
+#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xffff0000
+#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
+#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0xffff
+#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
+#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xffff0000
+#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
+#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0xffff
+#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
+#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xffff0000
+#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
+#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0xffff
+#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
+#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xffff0000
+#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
+#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0xffff
+#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
+#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xffff0000
+#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
+#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0xffff
+#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
+#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xffff0000
+#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
+#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0xffff
+#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
+#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xffff0000
+#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
+#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0xffff
+#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
+#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xffff0000
+#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
+#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0xffff
+#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
+#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xffff0000
+#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
+#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0xffff
+#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
+#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xffff0000
+#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
+#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0xffff
+#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
+#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xffff0000
+#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
+#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0xffff
+#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
+#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xffff0000
+#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
+#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0xffff
+#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
+#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xffff0000
+#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
+#define DENORM_CONTROL__DENORM_MODE_MASK 0x7
+#define DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
+#define DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x10
+#define DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
+#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0xf
+#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
+#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x3fff
+#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
+#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3fff0000
+#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
+#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x3fff
+#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
+#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3fff0000
+#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
+#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x3fff
+#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
+#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3fff0000
+#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
+#define KEY_CONTROL__KEY_MODE_MASK 0x6
+#define KEY_CONTROL__KEY_MODE__SHIFT 0x1
+#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0xffff
+#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
+#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xffff0000
+#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
+#define KEY_RANGE_RED__KEY_RED_LOW_MASK 0xffff
+#define KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
+#define KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xffff0000
+#define KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
+#define KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0xffff
+#define KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
+#define KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xffff0000
+#define KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
+#define KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0xffff
+#define KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
+#define KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xffff0000
+#define KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
+#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x3
+#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
+#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x300
+#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
+#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x3000
+#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
+#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x3
+#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
+#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0xffff
+#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
+#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xffff0000
+#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
+#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0xffff
+#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
+#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xffff0000
+#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
+#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0xffff
+#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
+#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xffff0000
+#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
+#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0xffff
+#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
+#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xffff0000
+#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
+#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0xffff
+#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
+#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xffff0000
+#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
+#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0xffff
+#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
+#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xffff0000
+#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x1
+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x30
+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0xc0
+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
+#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x100
+#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
+#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x200
+#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
+#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x400
+#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
+#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff
+#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
+#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x7f00000
+#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
+#define CUR_CONTROL__CURSOR_EN_MASK 0x1
+#define CUR_CONTROL__CURSOR_EN__SHIFT 0x0
+#define CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x10
+#define CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
+#define CUR_CONTROL__CURSOR_MODE_MASK 0x300
+#define CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
+#define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x10000
+#define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
+#define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x100000
+#define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
+#define CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x7000000
+#define CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
+#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xffffffff
+#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
+#define CUR_SIZE__CURSOR_HEIGHT_MASK 0x7f
+#define CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
+#define CUR_SIZE__CURSOR_WIDTH_MASK 0x7f0000
+#define CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
+#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0xff
+#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define CUR_POSITION__CURSOR_Y_POSITION_MASK 0x3fff
+#define CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
+#define CUR_POSITION__CURSOR_X_POSITION_MASK 0x3fff0000
+#define CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
+#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x7f
+#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
+#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x7f0000
+#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
+#define CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0xff
+#define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
+#define CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0xff00
+#define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
+#define CUR_COLOR1__CUR_COLOR1_RED_MASK 0xff0000
+#define CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
+#define CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0xff
+#define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
+#define CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0xff00
+#define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
+#define CUR_COLOR2__CUR_COLOR2_RED_MASK 0xff0000
+#define CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
+#define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x1
+#define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
+#define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x2
+#define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
+#define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x10000
+#define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
+#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
+#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x6000000
+#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
+#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x1
+#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
+#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x1
+#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
+#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX_MASK 0x2
+#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX__SHIFT 0x1
+#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x3ff0
+#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
+#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x3ff0000
+#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
+#define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x1
+#define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
+#define DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x10000
+#define DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10
+#define DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x20000
+#define DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11
+#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0xff
+#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
+#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0xffff
+#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
+#define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0xffff
+#define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
+#define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xffff0000
+#define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x3ff
+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0xffc00
+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3ff00000
+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
+#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x1
+#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
+#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x7
+#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x1
+#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
+#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x2
+#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
+#define DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0xf
+#define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
+#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x10
+#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
+#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x20
+#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
+#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0xc0
+#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
+#define DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0xf00
+#define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
+#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x1000
+#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
+#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x2000
+#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
+#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0xc000
+#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
+#define DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0xf0000
+#define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
+#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x100000
+#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
+#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x200000
+#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
+#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0xc00000
+#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
+#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0xffff
+#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
+#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0xffff
+#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
+#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0xffff
+#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
+#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0xffff
+#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
+#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0xffff
+#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
+#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0xffff
+#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
+#define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x1
+#define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
+#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x1c
+#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
+#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x300
+#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
+#define DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xffffffff
+#define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
+#define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xffffffff
+#define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
+#define DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x1
+#define DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
+#define DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x1e
+#define DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
+#define DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x1e0
+#define DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
+#define DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x7fe00
+#define DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
+#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x100000
+#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
+#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x200000
+#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
+#define DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xffffffff
+#define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
+#define DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x3f
+#define DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
+#define DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0xff00
+#define DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
+#define DCP_DEBUG__DCP_DEBUG_MASK 0xffffffff
+#define DCP_DEBUG__DCP_DEBUG__SHIFT 0x0
+#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x7
+#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
+#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x8
+#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
+#define DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x1
+#define DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
+#define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x2
+#define DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
+#define DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x4
+#define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
+#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0xf000
+#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0xc
+#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x10000
+#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x10
+#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x60000
+#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x11
+#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x80000
+#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x13
+#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x3000000
+#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
+#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x8000000
+#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
+#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xf0000000
+#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
+#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0xf
+#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
+#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x1f0
+#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
+#define DCP_DEBUG_SG__DCP_DEBUG_SG_MASK 0xffffffff
+#define DCP_DEBUG_SG__DCP_DEBUG_SG__SHIFT 0x0
+#define DCP_DEBUG_SG2__DCP_DEBUG_SG2_MASK 0xffffffff
+#define DCP_DEBUG_SG2__DCP_DEBUG_SG2__SHIFT 0x0
+#define DCP_DVMM_DEBUG__DCP_DVMM_DEBUG_MASK 0xffffffff
+#define DCP_DVMM_DEBUG__DCP_DVMM_DEBUG__SHIFT 0x0
+#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK 0xff
+#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT 0x0
+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1
+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x300
+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
+#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000
+#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
+#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000
+#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000
+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
+#define DCP_DEBUG2__DCP_DEBUG2_MASK 0xffffffff
+#define DCP_DEBUG2__DCP_DEBUG2__SHIFT 0x0
+#define HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x7
+#define HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x1
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x2
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x1fff0
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
+#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x7
+#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
+#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x1ff
+#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
+#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x7ffff
+#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
+#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x7
+#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x3ffff
+#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
+#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000
+#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
+#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0xffff
+#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
+#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff
+#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000
+#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x3ffff
+#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
+#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000
+#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
+#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0xffff
+#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
+#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff
+#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000
+#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x1
+#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
+#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x2
+#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
+#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xffffff00
+#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
+#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0xff
+#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0xfffff
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x1000000
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x2000000
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x4000000
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
+#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x1
+#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0
+#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x1e
+#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1
+#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x200
+#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9
+#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0xffff
+#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0
+#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xffff0000
+#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10
+#define DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x7
+#define DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
+#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x70
+#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
+#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x100
+#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
+#define DIG_FE_CNTL__DIG_START_MASK 0x400
+#define DIG_FE_CNTL__DIG_START__SHIFT 0xa
+#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x1000000
+#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
+#define DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000
+#define DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c
+#define DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xc0000000
+#define DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e
+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x1
+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x10
+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x300
+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
+#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3fffffff
+#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
+#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x3ff
+#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
+#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x1
+#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
+#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x2
+#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
+#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x10
+#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
+#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x20
+#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
+#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x40
+#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
+#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x3ff0000
+#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
+#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0xffffff
+#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
+#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x1000000
+#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
+#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x1
+#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
+#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
+#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0xfc
+#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x100
+#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
+#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00
+#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x1f0000
+#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x3c00000
+#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+#define DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x4000000
+#define DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a
+#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000
+#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
+#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000
+#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000
+#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK 0x1
+#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT 0x0
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK 0x1
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT 0x0
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK 0x10
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT 0x4
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK 0x100
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT 0x8
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK 0x1000
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0xc
+#define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x1
+#define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
+#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x4
+#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2
+#define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x8
+#define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3
+#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x10
+#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
+#define HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x100
+#define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
+#define HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x200
+#define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
+#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x1000000
+#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
+#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000
+#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
+#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x1
+#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
+#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x10000
+#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
+#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x100000
+#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
+#define HDMI_STATUS__HDMI_ERROR_INT_MASK 0x8000000
+#define HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x30
+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x100
+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8
+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x1f0000
+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x1
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x2
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x30
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x100
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x1000
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x70000
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
+#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x1
+#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
+#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x10
+#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
+#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x20
+#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x100
+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x200
+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x3f0000
+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x1
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x2
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x10
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x20
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
+#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x100
+#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
+#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x200
+#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
+#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x3f
+#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
+#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x3f00
+#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
+#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x3f0000
+#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x1
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x2
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x10
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x20
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x3f0000
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3f000000
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
+#define HDMI_GC__HDMI_GC_AVMUTE_MASK 0x1
+#define HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
+#define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x4
+#define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
+#define HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x10
+#define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
+#define HDMI_GC__HDMI_PACKING_PHASE_MASK 0xf00
+#define HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
+#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x1000
+#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x1
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x2
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0xff00
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0xff0000
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x1000000
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
+#define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x7
+#define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
+#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x40
+#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
+#define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x80
+#define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0xff
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0xff00
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0xff0000
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xff000000
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0xff
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0xff00
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0xff0000
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xff000000
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0xff
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0xff00
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0xff0000
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xff000000
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0xff
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0xff00
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0xff0000
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xff000000
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0xff
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0xff00
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0xff0000
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xff000000
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0xff
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0xff00
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0xff0000
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xff000000
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0xff
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0xff00
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0xff0000
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xff000000
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0xff
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0xff00
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0xff0000
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xff000000
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0xff
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x300
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0xc00
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x1000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x6000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD_MASK 0x8000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD__SHIFT 0xf
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0xf0000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x300000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0xc00000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x3000000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0xc000000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x7f
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD_MASK 0x80
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD__SHIFT 0x7
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0xf00
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x3000
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0xc000
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xffff0000
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
+#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0xffff
+#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
+#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xffff0000
+#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
+#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0xffff
+#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
+#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xff000000
+#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0xff
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0xff00
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0xff0000
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xff000000
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0xff
+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x300
+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x1000
+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0xff
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0xff00
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0xff0000
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xff000000
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0xff
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0xff00
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0xff0000
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xff000000
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0xff
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0xff00
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0xff0000
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xff000000
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0xff
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0xff00
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0xff0000
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xff000000
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0xff
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0xff00
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0xff0000
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xff000000
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0xff
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0xff00
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0xff0000
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xff000000
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0xff
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0xff00
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0xff0000
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xff000000
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0xff
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0xff00
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0xff0000
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xff000000
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0xff
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0xff00
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0xff0000
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xff000000
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x1
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x2
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x10
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x20
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x3f0000
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3f000000
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
+#define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xfffff000
+#define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
+#define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0xfffff
+#define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
+#define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xfffff000
+#define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
+#define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0xfffff
+#define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
+#define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xfffff000
+#define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
+#define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0xfffff
+#define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
+#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xfffff000
+#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
+#define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0xfffff
+#define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0xff
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x700
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x7800
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0xff0000
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1f000000
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0xff
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x7800
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x8000
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x30000
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
+#define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x1
+#define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
+#define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x2
+#define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
+#define AFMT_60958_0__AFMT_60958_CS_C_MASK 0x4
+#define AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
+#define AFMT_60958_0__AFMT_60958_CS_D_MASK 0x38
+#define AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
+#define AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0xc0
+#define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
+#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0xff00
+#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
+#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0xf0000
+#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
+#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0xf00000
+#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
+#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0xf000000
+#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
+#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000
+#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
+#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0xf
+#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
+#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf0
+#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
+#define AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x10000
+#define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
+#define AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x40000
+#define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
+#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0xf00000
+#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x1
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x10
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x100
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0xf000
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xffff0000
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
+#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0xffffff
+#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
+#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000
+#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
+#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0xffffff
+#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
+#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xff000000
+#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
+#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0xffffff
+#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
+#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0xffffff
+#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0xf
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0xf00
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0xf000
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0xf0000
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0xf00000
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
+#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x1
+#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
+#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xffffff00
+#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
+#define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x10
+#define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
+#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x100
+#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
+#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x1000000
+#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
+#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000
+#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x1
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x800
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x1000
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x4000
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x800000
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x1000000
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x4000000
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f
+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x4
+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x8
+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xc0000000
+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
+#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x40
+#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
+#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x80
+#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
+#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x400
+#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
+#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x7
+#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x7
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x0
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x100
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x8
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x7000
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0xc
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x70000
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x10
+#define AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x1
+#define AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0
+#define AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x100
+#define AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8
+#define DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x1
+#define DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0
+#define DIG_BE_CNTL__DIG_SWAP_MASK 0x2
+#define DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1
+#define DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x4
+#define DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2
+#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x7f00
+#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
+#define DIG_BE_CNTL__DIG_MODE_MASK 0x70000
+#define DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
+#define DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000
+#define DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
+#define DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x1
+#define DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
+#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x100
+#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
+#define TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x1
+#define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x1
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x2
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x4
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x8
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
+#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x3
+#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
+#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x300
+#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
+#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x3
+#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
+#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x3ff
+#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
+#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x3ff0000
+#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
+#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x3ff
+#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
+#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x3ff0000
+#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
+#define TMDS_DEBUG__TMDS_DEBUG_EN_MASK 0x1
+#define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT 0x0
+#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK 0x100
+#define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT 0x8
+#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK 0x200
+#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT 0x9
+#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK 0x10000
+#define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT 0x10
+#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK 0x20000
+#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT 0x11
+#define TMDS_DEBUG__TMDS_DEBUG_DE_MASK 0x1000000
+#define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT 0x18
+#define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK 0x2000000
+#define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT 0x19
+#define TMDS_CTL_BITS__TMDS_CTL0_MASK 0x1
+#define TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
+#define TMDS_CTL_BITS__TMDS_CTL1_MASK 0x100
+#define TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
+#define TMDS_CTL_BITS__TMDS_CTL2_MASK 0x10000
+#define TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
+#define TMDS_CTL_BITS__TMDS_CTL3_MASK 0x1000000
+#define TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x1
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
+#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x70
+#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x100
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0xf0000
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x1000000
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0xf
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x70
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x80
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x300
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x400
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x800
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x1000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0xf0000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x700000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x800000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x3000000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x4000000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x8000000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0xf
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x70
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x80
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x300
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x400
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x800
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x1000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0xf0000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x700000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x800000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x3000000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x4000000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x8000000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
+#define DIG_VERSION__DIG_TYPE_MASK 0x1
+#define DIG_VERSION__DIG_TYPE__SHIFT 0x0
+#define DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x1
+#define DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
+#define DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x2
+#define DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
+#define DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x4
+#define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
+#define DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x8
+#define DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
+#define DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x100
+#define DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
+#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX_MASK 0xff
+#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA__SHIFT 0x0
+#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX_MASK 0xff
+#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA__SHIFT 0x0
+#define DMCU_CTRL__RESET_UC_MASK 0x1
+#define DMCU_CTRL__RESET_UC__SHIFT 0x0
+#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x2
+#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1
+#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x4
+#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2
+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x8
+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3
+#define DMCU_CTRL__DMCU_ENABLE_MASK 0x10
+#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4
+#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN_MASK 0x100
+#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN__SHIFT 0x8
+#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xffff0000
+#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x10
+#define DMCU_STATUS__UC_IN_RESET_MASK 0x1
+#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0
+#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x2
+#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1
+#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x4
+#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2
+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0xff
+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0
+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0xff00
+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8
+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0xff
+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0
+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0xff00
+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8
+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0xff
+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0
+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0xff00
+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0xff
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0xff00
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8
+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xffffffff
+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0
+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xffffffff
+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0
+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x1
+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0
+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x2
+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1
+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x4
+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2
+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x8
+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3
+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x10
+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4
+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x20
+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0xffff
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0xf0000
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x100000
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14
+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xffffffff
+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0xffff
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0xf0000
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x100000
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14
+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xffffffff
+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0
+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x3ff
+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0
+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0xff
+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0
+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x3ff
+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0
+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0xff
+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0
+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x1
+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0
+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x7f0000
+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10
+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x800000
+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x1
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x2
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x4
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x8
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x10
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x20
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x40
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x80
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x100
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x200
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x400
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x800
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x1000
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x2000
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x4000
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x8000
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x2000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x4000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x4000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x8000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x10000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x10000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x20000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x40000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x40000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x80000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x100000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x100000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x200000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x400000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x400000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x800000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x1000000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x1000000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x2
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x2
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x4
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x4
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2
+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x8
+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED_MASK 0x10
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED__SHIFT 0x4
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR_MASK 0x10
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR__SHIFT 0x4
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED_MASK 0x20
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED__SHIFT 0x5
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR_MASK 0x20
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR__SHIFT 0x5
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED_MASK 0x40
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED__SHIFT 0x6
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR_MASK 0x40
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR__SHIFT 0x6
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED_MASK 0x80
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED__SHIFT 0x7
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR_MASK 0x80
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR__SHIFT 0x7
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x100
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x100
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8
+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x200
+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x400
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x400
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x800
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x800
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x1000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0xc
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x1000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0xc
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x2000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0xd
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x2000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0xd
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x4000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0xe
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x4000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0xe
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x8000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0xf
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x8000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xf
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x10000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x10
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x10000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x10
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x20000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x11
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x20000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x11
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x40000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x40000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x12
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x80000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x80000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x13
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x100000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x100000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x14
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x200000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x200000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x15
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x400000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x400000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x16
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x800000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x800000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x1000000
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x1000000
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x2000000
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x2000000
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x4000000
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x4000000
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x8000000
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x8000000
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d
+#define DMCU_INTERRUPT_STATUS__DCFEV0_VBLANK_INT_OCCURRED_MASK 0x40000000
+#define DMCU_INTERRUPT_STATUS__DCFEV0_VBLANK_INT_OCCURRED__SHIFT 0x1e
+#define DMCU_INTERRUPT_STATUS__DCFEV0_VBLANK_INT_CLEAR_MASK 0x40000000
+#define DMCU_INTERRUPT_STATUS__DCFEV0_VBLANK_INT_CLEAR__SHIFT 0x1e
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x1
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x0
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x2
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x1
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x4
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x2
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x200
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x400
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x800
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x4
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN_MASK 0x10
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN_MASK 0x20
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x40
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x80
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x100
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x200
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x400
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x800
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x1000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x2000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x4000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x8000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x10000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x20000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x40000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x80000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x100000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x200000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x400000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x800000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x1000000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x2000000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x4000000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x8000000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x40000000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x1e
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCFEV0_VBLANK_INT_TO_UC_EN_MASK 0x80000000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCFEV0_VBLANK_INT_TO_UC_EN__SHIFT 0x1f
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_UP_INT_TO_UC_EN_MASK 0x1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_UP_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_TO_UC_EN_MASK 0x2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x4
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x20
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x40
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x80
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x100
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x200
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x400
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x800
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x1000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x2000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x4000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x8000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x20000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x40000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x80000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x100000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x200000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x400000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x800000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x1000000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x2000000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x4000000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x8000000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x40000000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0x1e
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL_MASK 0x80000000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL__SHIFT 0x1f
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xffffffff
+#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0
+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0xff
+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0
+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0xff00
+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8
+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0xff0000
+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x3
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0xc
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2
+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x7
+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0
+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x700
+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8
+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x10000
+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0xff
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0xff00
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0xff0000
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xff000000
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0xff
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0xff00
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0xff0000
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xff000000
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0xff
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0xff00
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0xff0000
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xff000000
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0xff
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0xff00
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0xff0000
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xff000000
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18
+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x1
+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0xff
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0xff00
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0xff0000
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xff000000
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0xff
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0xff00
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0xff0000
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xff000000
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0xff
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0xff00
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0xff0000
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xff000000
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0xff
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0xff00
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0xff0000
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xff000000
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18
+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x1
+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0
+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x100
+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8
+#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK 0xff
+#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x0
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK 0x1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x0
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x2
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x2
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK 0x4
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT 0x2
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK 0x4
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT 0x2
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK 0x8
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT 0x3
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK 0x8
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT 0x3
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x10
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x4
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK 0x10
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x4
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x20
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x5
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK 0x20
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x5
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x40
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x6
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x40
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x6
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK 0x80
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT 0x7
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK 0x80
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT 0x7
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK 0x100
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT 0x8
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK 0x100
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT 0x8
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x200
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x9
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK 0x200
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x9
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x400
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xa
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x400
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xa
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x800
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xb
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x800
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xb
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x1000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xc
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x1000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xc
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x2000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xd
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x2000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xd
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x4000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xe
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x4000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xe
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x8000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xf
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x8000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xf
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x10000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0x10
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x10000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0x10
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK 0x20000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT 0x11
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK 0x20000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT 0x11
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK 0x40000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT 0x12
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK 0x40000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT 0x12
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK 0x80000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT 0x13
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK 0x80000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT 0x13
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK 0x100000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT 0x14
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK 0x100000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT 0x14
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK 0x200000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT 0x15
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK 0x200000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT 0x15
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK 0x400000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT 0x16
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK 0x400000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT 0x16
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK 0x800000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT 0x17
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK 0x800000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT 0x17
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK 0x1000000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT 0x18
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK 0x1000000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT 0x18
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK 0x2000000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT 0x19
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK 0x2000000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT 0x19
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK 0x4000000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT 0x1a
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK 0x4000000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT 0x1a
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK 0x8000000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT 0x1b
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK 0x8000000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT 0x1b
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK 0x10000000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT 0x1c
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK 0x10000000
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT 0x1c
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x1
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x2
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK 0x4
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x2
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK 0x8
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x3
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x10
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x20
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x40
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK 0x80
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x7
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK 0x100
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x8
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x200
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x400
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x800
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x1000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x2000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x4000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x8000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x10000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK 0x20000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK 0x40000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK 0x80000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK 0x100000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT 0x14
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK 0x200000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT 0x15
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK 0x400000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT 0x16
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK 0x800000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT 0x17
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK 0x1000000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK 0x2000000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK 0x4000000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1a
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK 0x8000000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1b
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK 0x10000000
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1c
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x1
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x2
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x4
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x8
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x10
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x20
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x40
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x80
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x100
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x200
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x400
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x800
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x1000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x2000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x4000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x8000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x10000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK 0x20000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK 0x40000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK 0x80000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK 0x100000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK 0x200000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK 0x400000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK 0x800000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK 0x1000000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x2000000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x4000000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x8000000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1b
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x10000000
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1c
+#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x10
+#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
+#define DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x100
+#define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
+#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x20000
+#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
+#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x7
+#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
+#define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x100
+#define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
+#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x10000
+#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
+#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x7000000
+#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
+#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0xff
+#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
+#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x100
+#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
+#define DP_CONFIG__DP_UDI_LANES_MASK 0x3
+#define DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x1
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x300
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x10000
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x100000
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
+#define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x1
+#define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x10
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x20
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x40
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x80
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
+#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x100
+#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
+#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x1000
+#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
+#define DP_MSA_MISC__DP_MSA_MISC1_MASK 0x78
+#define DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
+#define DP_MSA_MISC__DP_MSA_MISC2_MASK 0xff00
+#define DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
+#define DP_MSA_MISC__DP_MSA_MISC3_MASK 0xff0000
+#define DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
+#define DP_MSA_MISC__DP_MSA_MISC4_MASK 0xff000000
+#define DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
+#define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x1
+#define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
+#define DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x10
+#define DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4
+#define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x100
+#define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
+#define DP_VID_TIMING__DP_VID_N_DIV_MASK 0xff000000
+#define DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
+#define DP_VID_N__DP_VID_N_MASK 0xffffff
+#define DP_VID_N__DP_VID_N__SHIFT 0x0
+#define DP_VID_M__DP_VID_M_MASK 0xffffff
+#define DP_VID_M__DP_VID_M__SHIFT 0x0
+#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x3ffff
+#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
+#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x1000000
+#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
+#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000
+#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
+#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x1
+#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
+#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0xfff
+#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
+#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x10000
+#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
+#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x1000000
+#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x1
+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x2
+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x4
+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x1
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x2
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x4
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x8
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
+#define DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x10000
+#define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
+#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x1000000
+#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
+#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x3
+#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
+#define DP_DPHY_SYM0__DPHY_SYM1_MASK 0x3ff
+#define DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
+#define DP_DPHY_SYM0__DPHY_SYM2_MASK 0xffc00
+#define DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
+#define DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3ff00000
+#define DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
+#define DP_DPHY_SYM1__DPHY_SYM4_MASK 0x3ff
+#define DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
+#define DP_DPHY_SYM1__DPHY_SYM5_MASK 0xffc00
+#define DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
+#define DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3ff00000
+#define DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
+#define DP_DPHY_SYM2__DPHY_SYM7_MASK 0x3ff
+#define DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
+#define DP_DPHY_SYM2__DPHY_SYM8_MASK 0xffc00
+#define DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x100
+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x10000
+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x1000000
+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x1
+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x30
+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00
+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
+#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x3ff
+#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0
+#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x8000
+#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf
+#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x10000
+#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10
+#define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x1
+#define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
+#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x10
+#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
+#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x100
+#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
+#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x1
+#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
+#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x30
+#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
+#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0xff0000
+#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0xff
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0xff00
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0xff0000
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xff000000
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
+#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x3f
+#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
+#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x3f00
+#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x1
+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x100
+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x10000
+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
+#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x1
+#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
+#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x2
+#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x4
+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0xfff00
+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xfff00000
+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x7
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x10
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x100
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x1000
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
+#define DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x7
+#define DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0
+#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x1
+#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
+#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x3fff0
+#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
+#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x3fff
+#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
+#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3fff0000
+#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
+#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x1
+#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
+#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x10
+#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
+#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x100
+#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
+#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x1000
+#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
+#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x10000
+#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
+#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x100000
+#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
+#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x200000
+#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
+#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x400000
+#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
+#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x800000
+#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
+#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x1000000
+#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
+#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000
+#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
+#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x1
+#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
+#define DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x10
+#define DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4
+#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x20
+#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5
+#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x40
+#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6
+#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x80
+#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7
+#define DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xffff0000
+#define DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10
+#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0xfff
+#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
+#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xffff0000
+#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0xffff
+#define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
+#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xffff0000
+#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x3fff
+#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
+#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xffff0000
+#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x100000
+#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
+#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x1000000
+#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
+#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000
+#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
+#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000
+#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
+#define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0xffffff
+#define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
+#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0xffffff
+#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
+#define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0xffffff
+#define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
+#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0xffffff
+#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x1
+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0xe
+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x10
+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
+#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x3f00
+#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x10000
+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
+#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x3ffffff
+#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
+#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xfc000000
+#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
+#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x1
+#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
+#define DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x7
+#define DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
+#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x3f00
+#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
+#define DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x70000
+#define DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
+#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3f000000
+#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
+#define DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x7
+#define DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
+#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x3f00
+#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
+#define DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x70000
+#define DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
+#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3f000000
+#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
+#define DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x7
+#define DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
+#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x3f00
+#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
+#define DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x70000
+#define DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
+#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3f000000
+#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
+#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x3
+#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
+#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x100
+#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
+#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x3ff
+#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
+#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x30000
+#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
+#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x1
+#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
+#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x10
+#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
+#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x100
+#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
+#define DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA_MASK 0x10000
+#define DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA__SHIFT 0x10
+#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK 0xff
+#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT 0x0
+#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX_MASK 0xff
+#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA__SHIFT 0x0
+#define AUX_CONTROL__AUX_EN_MASK 0x1
+#define AUX_CONTROL__AUX_EN__SHIFT 0x0
+#define AUX_CONTROL__AUX_RESET_MASK 0x10
+#define AUX_CONTROL__AUX_RESET__SHIFT 0x4
+#define AUX_CONTROL__AUX_RESET_DONE_MASK 0x20
+#define AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5
+#define AUX_CONTROL__AUX_LS_READ_EN_MASK 0x100
+#define AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
+#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x1000
+#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
+#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x10000
+#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
+#define AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x40000
+#define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
+#define AUX_CONTROL__AUX_HPD_SEL_MASK 0x700000
+#define AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
+#define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x1000000
+#define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
+#define AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000
+#define AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
+#define AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000
+#define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
+#define AUX_CONTROL__SPARE_0_MASK 0x40000000
+#define AUX_CONTROL__SPARE_0__SHIFT 0x1e
+#define AUX_CONTROL__SPARE_1_MASK 0x80000000
+#define AUX_CONTROL__SPARE_1__SHIFT 0x1f
+#define AUX_SW_CONTROL__AUX_SW_GO_MASK 0x1
+#define AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
+#define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x4
+#define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
+#define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0xf0
+#define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
+#define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x1f0000
+#define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
+#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x3
+#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
+#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0xc
+#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
+#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x100
+#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
+#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x400
+#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
+#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x10000
+#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
+#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x10000
+#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
+#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x20000
+#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
+#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x1000000
+#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
+#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x1000000
+#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
+#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x2000000
+#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x1
+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x2
+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x4
+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x10
+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x20
+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x40
+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x100
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x200
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x400
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x1000
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x2000
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x4000
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
+#define AUX_SW_STATUS__AUX_SW_DONE_MASK 0x1
+#define AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
+#define AUX_SW_STATUS__AUX_SW_REQ_MASK 0x2
+#define AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
+#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x70
+#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
+#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x80
+#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
+#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x100
+#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
+#define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x200
+#define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
+#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x400
+#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
+#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x800
+#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
+#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x1000
+#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x4000
+#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
+#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x20000
+#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
+#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x40000
+#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
+#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x80000
+#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
+#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x100000
+#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
+#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x400000
+#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
+#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x800000
+#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
+#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1f000000
+#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
+#define AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xc0000000
+#define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
+#define AUX_LS_STATUS__AUX_LS_DONE_MASK 0x1
+#define AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
+#define AUX_LS_STATUS__AUX_LS_REQ_MASK 0x2
+#define AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
+#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x70
+#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
+#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x80
+#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
+#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x100
+#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
+#define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x200
+#define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
+#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x400
+#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
+#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x800
+#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
+#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x1000
+#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x4000
+#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
+#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x20000
+#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
+#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x40000
+#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
+#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x80000
+#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
+#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x100000
+#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
+#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x400000
+#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
+#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x800000
+#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
+#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1f000000
+#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
+#define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000
+#define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
+#define AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000
+#define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
+#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000
+#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
+#define AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x1
+#define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
+#define AUX_SW_DATA__AUX_SW_DATA_MASK 0xff00
+#define AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
+#define AUX_SW_DATA__AUX_SW_INDEX_MASK 0x1f0000
+#define AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
+#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000
+#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+#define AUX_LS_DATA__AUX_LS_DATA_MASK 0xff00
+#define AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
+#define AUX_LS_DATA__AUX_LS_INDEX_MASK 0x1f0000
+#define AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x1
+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x30
+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x1ff0000
+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
+#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x7
+#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
+#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x3f00
+#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
+#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x70000
+#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x70
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x700
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x3000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x10000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x20000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x40000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x80000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x300000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x7000000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
+#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0xff
+#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
+#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x1
+#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
+#define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x70
+#define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
+#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x1ff0000
+#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
+#define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x7
+#define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
+#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x1f00
+#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
+#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x1f0000
+#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
+#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3fe00000
+#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x1
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x10
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0xf00
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0xf000
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x70000
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x100000
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0xc00000
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x3000000
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xf0000000
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x1f
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x1f00
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x30000
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x300000
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x1
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x10
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x100
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x1e00
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x10000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x100000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x200000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x400000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x800000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x1000000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x2000000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xf0000000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x1
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x2
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x70
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x80
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x100
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x200
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x400
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x800
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x1000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x4000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x20000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x40000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x80000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x100000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x400000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x800000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1f000000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
+#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW_MASK 0x1
+#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW__SHIFT 0x0
+#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_MASK 0xff00
+#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA__SHIFT 0x8
+#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_MASK 0x3f0000
+#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX__SHIFT 0x10
+#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE_MASK 0x80000000
+#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN_MASK 0x1
+#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN__SHIFT 0x0
+#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE_MASK 0xffff0
+#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE__SHIFT 0x4
+#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX_MASK 0xff
+#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX__SHIFT 0x0
+#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA_MASK 0xffffffff
+#define AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA__SHIFT 0x0
+#define DP_AUX_DEBUG_A__DP_AUX_DEBUG_A_MASK 0xffffffff
+#define DP_AUX_DEBUG_A__DP_AUX_DEBUG_A__SHIFT 0x0
+#define DP_AUX_DEBUG_B__DP_AUX_DEBUG_B_MASK 0xffffffff
+#define DP_AUX_DEBUG_B__DP_AUX_DEBUG_B__SHIFT 0x0
+#define DP_AUX_DEBUG_C__DP_AUX_DEBUG_C_MASK 0xffffffff
+#define DP_AUX_DEBUG_C__DP_AUX_DEBUG_C__SHIFT 0x0
+#define DP_AUX_DEBUG_D__DP_AUX_DEBUG_D_MASK 0xffffffff
+#define DP_AUX_DEBUG_D__DP_AUX_DEBUG_D__SHIFT 0x0
+#define DP_AUX_DEBUG_E__DP_AUX_DEBUG_E_MASK 0xffffffff
+#define DP_AUX_DEBUG_E__DP_AUX_DEBUG_E__SHIFT 0x0
+#define DP_AUX_DEBUG_F__DP_AUX_DEBUG_F_MASK 0xffffffff
+#define DP_AUX_DEBUG_F__DP_AUX_DEBUG_F__SHIFT 0x0
+#define DP_AUX_DEBUG_G__DP_AUX_DEBUG_G_MASK 0xffffffff
+#define DP_AUX_DEBUG_G__DP_AUX_DEBUG_G__SHIFT 0x0
+#define DP_AUX_DEBUG_H__DP_AUX_DEBUG_H_MASK 0xffffffff
+#define DP_AUX_DEBUG_H__DP_AUX_DEBUG_H__SHIFT 0x0
+#define DP_AUX_DEBUG_I__DP_AUX_DEBUG_I_MASK 0xffffffff
+#define DP_AUX_DEBUG_I__DP_AUX_DEBUG_I__SHIFT 0x0
+#define DP_AUX_DEBUG_J__DP_AUX_DEBUG_J_MASK 0xffffffff
+#define DP_AUX_DEBUG_J__DP_AUX_DEBUG_J__SHIFT 0x0
+#define DP_AUX_DEBUG_K__DP_AUX_DEBUG_K_MASK 0xffffffff
+#define DP_AUX_DEBUG_K__DP_AUX_DEBUG_K__SHIFT 0x0
+#define DP_AUX_DEBUG_L__DP_AUX_DEBUG_L_MASK 0xffffffff
+#define DP_AUX_DEBUG_L__DP_AUX_DEBUG_L__SHIFT 0x0
+#define DP_AUX_DEBUG_M__DP_AUX_DEBUG_M_MASK 0xffffffff
+#define DP_AUX_DEBUG_M__DP_AUX_DEBUG_M__SHIFT 0x0
+#define DP_AUX_DEBUG_N__DP_AUX_DEBUG_N_MASK 0xffffffff
+#define DP_AUX_DEBUG_N__DP_AUX_DEBUG_N__SHIFT 0x0
+#define DP_AUX_DEBUG_O__DP_AUX_DEBUG_O_MASK 0xffffffff
+#define DP_AUX_DEBUG_O__DP_AUX_DEBUG_O__SHIFT 0x0
+#define DP_AUX_DEBUG_P__DP_AUX_DEBUG_P_MASK 0xffffffff
+#define DP_AUX_DEBUG_P__DP_AUX_DEBUG_P__SHIFT 0x0
+#define DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q_MASK 0xffffffff
+#define DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q__SHIFT 0x0
+#define DVO_ENABLE__DVO_ENABLE_MASK 0x1
+#define DVO_ENABLE__DVO_ENABLE__SHIFT 0x0
+#define DVO_ENABLE__DVO_PIXEL_WIDTH_MASK 0x30
+#define DVO_ENABLE__DVO_PIXEL_WIDTH__SHIFT 0x4
+#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK 0x7
+#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT 0x0
+#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK 0x70000
+#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT 0x10
+#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK 0x3
+#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT 0x0
+#define DVO_OUTPUT__DVO_CLOCK_MODE_MASK 0x100
+#define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT 0x8
+#define DVO_CONTROL__DVO_RATE_SELECT_MASK 0x1
+#define DVO_CONTROL__DVO_RATE_SELECT__SHIFT 0x0
+#define DVO_CONTROL__DVO_SDRCLK_SEL_MASK 0x2
+#define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT 0x1
+#define DVO_CONTROL__DVO_DVPDATA_WIDTH_MASK 0x30
+#define DVO_CONTROL__DVO_DVPDATA_WIDTH__SHIFT 0x4
+#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK 0x100
+#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT 0x8
+#define DVO_CONTROL__DVO_RESET_FIFO_MASK 0x10000
+#define DVO_CONTROL__DVO_RESET_FIFO__SHIFT 0x10
+#define DVO_CONTROL__DVO_SYNC_PHASE_MASK 0x20000
+#define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT 0x11
+#define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK 0x40000
+#define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT 0x12
+#define DVO_CONTROL__DVO_HSYNC_POLARITY_MASK 0x100000
+#define DVO_CONTROL__DVO_HSYNC_POLARITY__SHIFT 0x14
+#define DVO_CONTROL__DVO_VSYNC_POLARITY_MASK 0x200000
+#define DVO_CONTROL__DVO_VSYNC_POLARITY__SHIFT 0x15
+#define DVO_CONTROL__DVO_DE_POLARITY_MASK 0x400000
+#define DVO_CONTROL__DVO_DE_POLARITY__SHIFT 0x16
+#define DVO_CONTROL__DVO_COLOR_FORMAT_MASK 0x3000000
+#define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT 0x18
+#define DVO_CONTROL__DVO_CTL3_MASK 0x80000000
+#define DVO_CONTROL__DVO_CTL3__SHIFT 0x1f
+#define DVO_CRC_EN__DVO_CRC2_EN_MASK 0x10000
+#define DVO_CRC_EN__DVO_CRC2_EN__SHIFT 0x10
+#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK 0x7ffffff
+#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT 0x0
+#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK 0x7ffffff
+#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT 0x0
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK 0x1
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT 0x0
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK 0xfc
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK 0x100
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT 0x8
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK 0xf0000
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK 0x3c00000
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK 0x20000000
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT 0x1d
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX_MASK 0xff
+#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA__SHIFT 0x0
+#define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x1
+#define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x0
+#define FBC_CNTL__FBC_SRC_SEL_MASK 0xe
+#define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x1
+#define FBC_CNTL__FBC_COMP_CLK_GATE_EN_MASK 0x100
+#define FBC_CNTL__FBC_COMP_CLK_GATE_EN__SHIFT 0x8
+#define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x30000
+#define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x10
+#define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x2000000
+#define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x19
+#define FBC_CNTL__FBC_EN_MASK 0x80000000
+#define FBC_CNTL__FBC_EN__SHIFT 0x1f
+#define FBC_IDLE_MASK__FBC_IDLE_MASK_MASK 0xffffffff
+#define FBC_IDLE_MASK__FBC_IDLE_MASK__SHIFT 0x0
+#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xffffffff
+#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x0
+#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x1f
+#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x0
+#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x80
+#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x7
+#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x1f00
+#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x8
+#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0xf
+#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x0
+#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x10000
+#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x10
+#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x20000
+#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x11
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x40000
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x12
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x80000
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x13
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x100000
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x14
+#define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x1
+#define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x0
+#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x100
+#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x8
+#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x200
+#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x9
+#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x400
+#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0xa
+#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x800
+#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0xb
+#define FBC_COMP_MODE__FBC_IND_EN_MASK 0x10000
+#define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x10
+#define FBC_DEBUG0__FBC_PERF_MUX0_MASK 0xff
+#define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT 0x0
+#define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0xff00
+#define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT 0x8
+#define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK 0x10000
+#define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT 0x10
+#define FBC_DEBUG0__FBC_DEBUG0_MASK 0xfe0000
+#define FBC_DEBUG0__FBC_DEBUG0__SHIFT 0x11
+#define FBC_DEBUG0__FBC_DEBUG_MUX_MASK 0xff000000
+#define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT 0x18
+#define FBC_DEBUG1__FBC_DEBUG1_MASK 0xffffffff
+#define FBC_DEBUG1__FBC_DEBUG1__SHIFT 0x0
+#define FBC_DEBUG2__FBC_DEBUG2_MASK 0xffffffff
+#define FBC_DEBUG2__FBC_DEBUG2__SHIFT 0x0
+#define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0xffffff
+#define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x0
+#define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0xffffff
+#define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x0
+#define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0xffffff
+#define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x0
+#define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0xffffff
+#define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x0
+#define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0xffffff
+#define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x0
+#define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0xffffff
+#define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x0
+#define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0xffffff
+#define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x0
+#define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0xffffff
+#define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x0
+#define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0xffffff
+#define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x0
+#define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0xffffff
+#define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x0
+#define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0xffffff
+#define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x0
+#define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0xffffff
+#define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x0
+#define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0xffffff
+#define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x0
+#define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0xffffff
+#define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x0
+#define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0xffffff
+#define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x0
+#define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0xffffff
+#define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x0
+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0xfff
+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x0
+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0xfff0000
+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x10
+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0xfff
+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x0
+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0xfff0000
+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x10
+#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0xf0000
+#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x10
+#define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x3
+#define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x0
+#define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x8
+#define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x3
+#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0xf0
+#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x4
+#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x300
+#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x8
+#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x400
+#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0xa
+#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x800
+#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0xb
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK 0xfff
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT 0x0
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA_MASK 0x10000
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA__SHIFT 0x10
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA_MASK 0x20000
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA__SHIFT 0x11
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK 0x80000000
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT 0x1f
+#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK 0xffffffff
+#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT 0x0
+#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK 0xffffffff
+#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT 0x0
+#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI_MASK 0xff
+#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI__SHIFT 0x0
+#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI_MASK 0xff
+#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI__SHIFT 0x0
+#define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x3
+#define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x0
+#define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x4
+#define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x2
+#define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x8
+#define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x3
+#define FBC_MISC__FBC_ERROR_PIXEL_MASK 0xf0
+#define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x4
+#define FBC_MISC__FBC_DIVIDE_X_MASK 0x300
+#define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x8
+#define FBC_MISC__FBC_DIVIDE_Y_MASK 0x400
+#define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0xa
+#define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x800
+#define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0xb
+#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x1000
+#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0xc
+#define FBC_MISC__FBC_STOP_ON_HFLIP_EVENT_MASK 0x2000
+#define FBC_MISC__FBC_STOP_ON_HFLIP_EVENT__SHIFT 0xd
+#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x10000
+#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x10
+#define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x100000
+#define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x14
+#define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x200000
+#define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x15
+#define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0x1f000000
+#define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x18
+#define FBC_MISC__FBC_FORCE_DECOMPRESSOR_EN_MASK 0x80000000
+#define FBC_MISC__FBC_FORCE_DECOMPRESSOR_EN__SHIFT 0x1f
+#define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x1
+#define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x0
+#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK 0xff
+#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT 0x0
+#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK 0xffffffff
+#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT 0x0
+#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0xffff
+#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
+#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xffff0000
+#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
+#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0xffff
+#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
+#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xffff0000
+#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
+#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0xffff
+#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
+#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xffff0000
+#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
+#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x1
+#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
+#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x10
+#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
+#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x1
+#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
+#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x10
+#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
+#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0xf00
+#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8
+#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x3000
+#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc
+#define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x10000
+#define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
+#define FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x20000
+#define FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x11
+#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x40000
+#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x12
+#define FMT_CONTROL__FMT_SRC_SELECT_MASK 0x7000000
+#define FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x1
+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x2
+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x30
+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x100
+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x600
+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x1800
+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
+#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x2000
+#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
+#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x4000
+#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
+#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x8000
+#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x10000
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x60000
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x600000
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x1000000
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x2000000
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
+#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0xc000000
+#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
+#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000
+#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
+#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xc0000000
+#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
+#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0xff
+#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
+#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xffff0000
+#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
+#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0xff
+#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
+#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xffff0000
+#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
+#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0xff
+#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
+#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xffff0000
+#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
+#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT_MASK 0x1
+#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT__SHIFT 0x0
+#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0_MASK 0x10
+#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0__SHIFT 0x4
+#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX_MASK 0xffffffff
+#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SHIFT 0x0
+#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX_MASK 0xffffffff
+#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SHIFT 0x0
+#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x1
+#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
+#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x70000
+#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
+#define FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x1
+#define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
+#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x2
+#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
+#define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x10
+#define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
+#define FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x20
+#define FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5
+#define FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x40
+#define FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6
+#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x100
+#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8
+#define FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x200
+#define FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9
+#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x3000
+#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
+#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000
+#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x100000
+#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
+#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x1000000
+#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
+#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0xffff
+#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
+#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xffff0000
+#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
+#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0xffff
+#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
+#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xffff0000
+#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
+#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0xffff
+#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
+#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xffff0000
+#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
+#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0xffff
+#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
+#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xffff0000
+#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
+#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK 0x3
+#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT 0x0
+#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX_MASK 0xff
+#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX__SHIFT 0x0
+#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA_MASK 0xffffffff
+#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA__SHIFT 0x0
+#define FMT_DEBUG0__FMT_DEBUG0_MASK 0xffffffff
+#define FMT_DEBUG0__FMT_DEBUG0__SHIFT 0x0
+#define FMT_DEBUG1__FMT_DEBUG1_MASK 0xffffffff
+#define FMT_DEBUG1__FMT_DEBUG1__SHIFT 0x0
+#define FMT_DEBUG2__FMT_DEBUG2_MASK 0xffffffff
+#define FMT_DEBUG2__FMT_DEBUG2__SHIFT 0x0
+#define FMT_DEBUG_ID__FMT_DEBUG_ID_MASK 0xffffffff
+#define FMT_DEBUG_ID__FMT_DEBUG_ID__SHIFT 0x0
+#define LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3
+#define LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
+#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4
+#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
+#define LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8
+#define LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
+#define LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x10
+#define LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
+#define LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x20
+#define LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
+#define LB_DATA_FORMAT__PREFETCH_MASK 0x1000
+#define LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
+#define LB_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000
+#define LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
+#define LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000
+#define LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
+#define LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0xfff
+#define LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
+#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000
+#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000
+#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
+#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0xfff
+#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
+#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff
+#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
+#define LB_VLINE_START_END__VLINE_START_MASK 0x3fff
+#define LB_VLINE_START_END__VLINE_START__SHIFT 0x0
+#define LB_VLINE_START_END__VLINE_END_MASK 0x7fff0000
+#define LB_VLINE_START_END__VLINE_END__SHIFT 0x10
+#define LB_VLINE_START_END__VLINE_INV_MASK 0x80000000
+#define LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
+#define LB_VLINE2_START_END__VLINE2_START_MASK 0x3fff
+#define LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
+#define LB_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000
+#define LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
+#define LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000
+#define LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
+#define LB_V_COUNTER__V_COUNTER_MASK 0x7fff
+#define LB_V_COUNTER__V_COUNTER__SHIFT 0x0
+#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff
+#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
+#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1
+#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
+#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10
+#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
+#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100
+#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
+#define LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1
+#define LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
+#define LB_VLINE_STATUS__VLINE_ACK_MASK 0x10
+#define LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
+#define LB_VLINE_STATUS__VLINE_STAT_MASK 0x1000
+#define LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
+#define LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000
+#define LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
+#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000
+#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
+#define LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1
+#define LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
+#define LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x10
+#define LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
+#define LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000
+#define LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
+#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000
+#define LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
+#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000
+#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
+#define LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1
+#define LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
+#define LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x10
+#define LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
+#define LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000
+#define LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
+#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000
+#define LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
+#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000
+#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3
+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10
+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00
+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
+#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000
+#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
+#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0
+#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
+#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0
+#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
+#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0
+#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
+#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1
+#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
+#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100
+#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
+#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0
+#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
+#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0
+#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
+#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0
+#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
+#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0
+#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
+#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0
+#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
+#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0
+#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
+#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f
+#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
+#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00
+#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
+#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000
+#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
+#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000
+#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
+#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff
+#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
+#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000
+#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
+#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff
+#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
+#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000
+#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000
+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000
+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000
+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
+#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1
+#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
+#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x3
+#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0xf
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x10
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x100
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x1000
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x3
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x7fff00
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3f000000
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
+#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x3
+#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x100
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x1000
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x10000
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x100000
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
+#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000
+#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
+#define LB_DEBUG__LB_DEBUG_MASK 0xffffffff
+#define LB_DEBUG__LB_DEBUG__SHIFT 0x0
+#define LB_DEBUG2__LB_DEBUG2_MASK 0xffffffff
+#define LB_DEBUG2__LB_DEBUG2__SHIFT 0x0
+#define LB_DEBUG3__LB_DEBUG3_MASK 0xffffffff
+#define LB_DEBUG3__LB_DEBUG3__SHIFT 0x0
+#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff
+#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0
+#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff
+#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0
+#define LBV_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3
+#define LBV_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
+#define LBV_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4
+#define LBV_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
+#define LBV_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8
+#define LBV_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
+#define LBV_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x10
+#define LBV_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4
+#define LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x20
+#define LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5
+#define LBV_DATA_FORMAT__DITHER_EN_MASK 0x40
+#define LBV_DATA_FORMAT__DITHER_EN__SHIFT 0x6
+#define LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN_MASK 0x80
+#define LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN__SHIFT 0x7
+#define LBV_DATA_FORMAT__PREFETCH_MASK 0x1000
+#define LBV_DATA_FORMAT__PREFETCH__SHIFT 0xc
+#define LBV_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000
+#define LBV_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
+#define LBV_DATA_FORMAT__ALPHA_EN_MASK 0x80000000
+#define LBV_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
+#define LBV_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0xfff
+#define LBV_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
+#define LBV_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000
+#define LBV_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+#define LBV_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000
+#define LBV_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
+#define LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0xfff
+#define LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
+#define LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff
+#define LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
+#define LBV_VLINE_START_END__VLINE_START_MASK 0x3fff
+#define LBV_VLINE_START_END__VLINE_START__SHIFT 0x0
+#define LBV_VLINE_START_END__VLINE_END_MASK 0x7fff0000
+#define LBV_VLINE_START_END__VLINE_END__SHIFT 0x10
+#define LBV_VLINE_START_END__VLINE_INV_MASK 0x80000000
+#define LBV_VLINE_START_END__VLINE_INV__SHIFT 0x1f
+#define LBV_VLINE2_START_END__VLINE2_START_MASK 0x3fff
+#define LBV_VLINE2_START_END__VLINE2_START__SHIFT 0x0
+#define LBV_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000
+#define LBV_VLINE2_START_END__VLINE2_END__SHIFT 0x10
+#define LBV_VLINE2_START_END__VLINE2_INV_MASK 0x80000000
+#define LBV_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
+#define LBV_V_COUNTER__V_COUNTER_MASK 0x7fff
+#define LBV_V_COUNTER__V_COUNTER__SHIFT 0x0
+#define LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff
+#define LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
+#define LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA_MASK 0x7fff
+#define LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA__SHIFT 0x0
+#define LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA_MASK 0x7fff
+#define LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA__SHIFT 0x0
+#define LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1
+#define LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
+#define LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10
+#define LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
+#define LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100
+#define LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
+#define LBV_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1
+#define LBV_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
+#define LBV_VLINE_STATUS__VLINE_ACK_MASK 0x10
+#define LBV_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
+#define LBV_VLINE_STATUS__VLINE_STAT_MASK 0x1000
+#define LBV_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
+#define LBV_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000
+#define LBV_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
+#define LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000
+#define LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
+#define LBV_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1
+#define LBV_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
+#define LBV_VLINE2_STATUS__VLINE2_ACK_MASK 0x10
+#define LBV_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
+#define LBV_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000
+#define LBV_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
+#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000
+#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
+#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000
+#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
+#define LBV_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1
+#define LBV_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
+#define LBV_VBLANK_STATUS__VBLANK_ACK_MASK 0x10
+#define LBV_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
+#define LBV_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000
+#define LBV_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
+#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000
+#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
+#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000
+#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
+#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3
+#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
+#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10
+#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
+#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00
+#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
+#define LBV_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000
+#define LBV_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
+#define LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0
+#define LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
+#define LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0
+#define LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
+#define LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0
+#define LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
+#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1
+#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
+#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100
+#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
+#define LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0
+#define LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
+#define LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0
+#define LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
+#define LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0
+#define LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
+#define LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0
+#define LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
+#define LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0
+#define LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
+#define LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0
+#define LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
+#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f
+#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
+#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00
+#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
+#define LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000
+#define LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
+#define LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000
+#define LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
+#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff
+#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
+#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000
+#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
+#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff
+#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
+#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000
+#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf
+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10
+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100
+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000
+#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
+#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000
+#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
+#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000
+#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
+#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000
+#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
+#define LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1
+#define LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
+#define LBV_DEBUG__LB_DEBUG_MASK 0xffffffff
+#define LBV_DEBUG__LB_DEBUG__SHIFT 0x0
+#define LBV_DEBUG2__LB_DEBUG2_MASK 0xffffffff
+#define LBV_DEBUG2__LB_DEBUG2__SHIFT 0x0
+#define LBV_DEBUG3__LB_DEBUG3_MASK 0xffffffff
+#define LBV_DEBUG3__LB_DEBUG3__SHIFT 0x0
+#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff
+#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0
+#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define LBV_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff
+#define LBV_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0
+#define MVP_CONTROL1__MVP_EN_MASK 0x1
+#define MVP_CONTROL1__MVP_EN__SHIFT 0x0
+#define MVP_CONTROL1__MVP_MIXER_MODE_MASK 0x70
+#define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT 0x4
+#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK 0x100
+#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT 0x8
+#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK 0x200
+#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT 0x9
+#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK 0x400
+#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT 0xa
+#define MVP_CONTROL1__MVP_RATE_CONTROL_MASK 0x1000
+#define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT 0xc
+#define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK 0x10000
+#define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT 0x10
+#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK 0x300000
+#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT 0x14
+#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK 0x1000000
+#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT 0x18
+#define MVP_CONTROL1__MVP_30BPP_EN_MASK 0x10000000
+#define MVP_CONTROL1__MVP_30BPP_EN__SHIFT 0x1c
+#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK 0x40000000
+#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT 0x1e
+#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK 0x80000000
+#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT 0x1f
+#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK 0x1
+#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT 0x0
+#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK 0x10
+#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT 0x4
+#define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK 0x100
+#define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT 0x8
+#define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK 0x1000
+#define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT 0xc
+#define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK 0x10000
+#define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT 0x10
+#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK 0x100000
+#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT 0x14
+#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK 0x1000000
+#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT 0x18
+#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK 0x10000000
+#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT 0x1c
+#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK 0xff
+#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT 0x0
+#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK 0xff00
+#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT 0x8
+#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK 0xff0000
+#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT 0x10
+#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK 0xff
+#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT 0x0
+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK 0x100
+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT 0x8
+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK 0x1000
+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT 0xc
+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK 0x10000
+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT 0x10
+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK 0x100000
+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT 0x14
+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK 0x1000000
+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT 0x18
+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK 0x10000000
+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT 0x1c
+#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK 0x40000000
+#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT 0x1e
+#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK 0x80000000
+#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT 0x1f
+#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK 0x1fff
+#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT 0x0
+#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK 0x1fff0000
+#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT 0x10
+#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK 0x1
+#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT 0x0
+#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK 0x10
+#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT 0x4
+#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK 0xffffff00
+#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT 0x8
+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK 0x3ff
+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT 0x0
+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK 0xffc00
+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT 0xa
+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK 0x3ff00000
+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT 0x14
+#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK 0xff
+#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT 0x0
+#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK 0xff00
+#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT 0x8
+#define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK 0xff0000
+#define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT 0x10
+#define MVP_CRC_CNTL__MVP_CRC_EN_MASK 0x10000000
+#define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT 0x1c
+#define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK 0x20000000
+#define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT 0x1d
+#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK 0x40000000
+#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT 0x1e
+#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK 0xffff
+#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT 0x0
+#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK 0xffff0000
+#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT 0x10
+#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK 0xffff
+#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT 0x0
+#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK 0x1
+#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT 0x0
+#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x10
+#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x4
+#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK 0x100
+#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT 0x8
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK 0x1000
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT 0xc
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK 0x10000
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT 0x10
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK 0x100000
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT 0x14
+#define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK 0x1000000
+#define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT 0x18
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK 0x10000000
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT 0x1c
+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK 0x1fff
+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT 0x0
+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK 0x1fff0000
+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT 0x10
+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK 0x80000000
+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT 0x1f
+#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK 0x1fff
+#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT 0x0
+#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK 0x80000000
+#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT 0x1f
+#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN_MASK 0x1
+#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN__SHIFT 0x0
+#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK 0x2
+#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN__SHIFT 0x1
+#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL_MASK 0x4
+#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT 0x2
+#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL_MASK 0x8
+#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL__SHIFT 0x3
+#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP_MASK 0x10
+#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP__SHIFT 0x4
+#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP_MASK 0x20
+#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP__SHIFT 0x5
+#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR_MASK 0x40
+#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR__SHIFT 0x6
+#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY_MASK 0x80
+#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY__SHIFT 0x7
+#define MVP_DEBUG__MVP_DEBUG_BITS_MASK 0xffffff00
+#define MVP_DEBUG__MVP_DEBUG_BITS__SHIFT 0x8
+#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK 0xff
+#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT 0x0
+#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK 0xffffffff
+#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT 0x0
+#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION_MASK 0x6
+#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1
+#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION_MASK 0x6
+#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1
+#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK 0x1
+#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT 0x0
+#define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK 0x1fffffe
+#define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT 0x1
+#define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK 0x1
+#define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT 0x0
+#define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK 0x1fffffe
+#define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT 0x1
+#define MVP_DEBUG_13__IDED_START_READ_B_MASK 0x2000000
+#define MVP_DEBUG_13__IDED_START_READ_B__SHIFT 0x19
+#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK 0x4000000
+#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT 0x1a
+#define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK 0x38000000
+#define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT 0x1b
+#define MVP_DEBUG_14__IDEE_READ_ADD_MASK 0x7
+#define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT 0x0
+#define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK 0x38
+#define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT 0x3
+#define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK 0x1c0
+#define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT 0x6
+#define MVP_DEBUG_14__IDEE_START_READ_MASK 0x200
+#define MVP_DEBUG_14__IDEE_START_READ__SHIFT 0x9
+#define MVP_DEBUG_14__IDEE_START_READ_B_MASK 0x400
+#define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT 0xa
+#define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK 0x800
+#define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT 0xb
+#define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK 0x1000
+#define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT 0xc
+#define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK 0x2000
+#define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT 0xd
+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK 0x4000
+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT 0xe
+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK 0x8000
+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT 0xf
+#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK 0x10000
+#define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT 0x10
+#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK 0x20000
+#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT 0x11
+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK 0x40000
+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT 0x12
+#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK 0x80000
+#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT 0x13
+#define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK 0x100000
+#define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT 0x14
+#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK 0x1
+#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT 0x0
+#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK 0xfffffff0
+#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT 0x4
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK 0x1
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT 0x0
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK 0x2
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT 0x1
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK 0x4
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT 0x2
+#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK 0x8
+#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT 0x3
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK 0xff0
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT 0x4
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK 0x1000
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT 0xc
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK 0x2000
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT 0xd
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK 0xff0000
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT 0x10
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK 0xff000000
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT 0x18
+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK 0x1
+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT 0x0
+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK 0x2
+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x1
+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK 0xfffffffc
+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT 0x2
+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0xf
+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0xf00
+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x70000
+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+#define SCL_MODE__SCL_MODE_MASK 0x3
+#define SCL_MODE__SCL_MODE__SHIFT 0x0
+#define SCL_MODE__SCL_PSCL_EN_MASK 0x10
+#define SCL_MODE__SCL_PSCL_EN__SHIFT 0x4
+#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7
+#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
+#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0xf00
+#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
+#define SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1
+#define SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+#define SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x10
+#define SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
+#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x3
+#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
+#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf
+#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00
+#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1
+#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
+#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000
+#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
+#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x1
+#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
+#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100
+#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff
+#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff
+#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000
+#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x1
+#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
+#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100
+#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff
+#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff
+#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000
+#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff
+#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000
+#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff
+#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
+#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000
+#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+#define SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x1
+#define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+#define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100
+#define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
+#define SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000
+#define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
+#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000
+#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
+#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x7
+#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
+#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x10
+#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
+#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x700
+#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
+#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x1000
+#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
+#define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1
+#define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x1
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x100
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x1000
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x10000
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
+#define VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x3fff
+#define VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
+#define VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3fff0000
+#define VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
+#define VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff
+#define VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
+#define VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000
+#define VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
+#define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x3fff
+#define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
+#define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3fff0000
+#define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
+#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff
+#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000
+#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff
+#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000
+#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1
+#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
+#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10
+#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
+#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80
+#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
+#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff
+#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
+#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff
+#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
+#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000
+#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
+#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1
+#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
+#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1
+#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0
+#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6
+#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1
+#define SCL_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8
+#define SCL_DEBUG2__SCL_DEBUG2__SHIFT 0x3
+#define SCL_DEBUG__SCL_DEBUG_MASK 0xffffffff
+#define SCL_DEBUG__SCL_DEBUG__SHIFT 0x0
+#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff
+#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0
+#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff
+#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0
+#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x3
+#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
+#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x7f00
+#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
+#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x30000
+#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff
+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000
+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000
+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000
+#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+#define SCLV_MODE__SCL_MODE_MASK 0x1
+#define SCLV_MODE__SCL_MODE__SHIFT 0x0
+#define SCLV_MODE__SCL_MODE_C_MASK 0x2
+#define SCLV_MODE__SCL_MODE_C__SHIFT 0x1
+#define SCLV_MODE__SCL_PSCL_EN_MASK 0x10
+#define SCLV_MODE__SCL_PSCL_EN__SHIFT 0x4
+#define SCLV_MODE__SCL_PSCL_EN_C_MASK 0x20
+#define SCLV_MODE__SCL_PSCL_EN_C__SHIFT 0x5
+#define SCLV_MODE__SCL_INTERLACE_SOURCE_MASK 0x300
+#define SCLV_MODE__SCL_INTERLACE_SOURCE__SHIFT 0x8
+#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7
+#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
+#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x70
+#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x4
+#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C_MASK 0x700
+#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C__SHIFT 0x8
+#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C_MASK 0x7000
+#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C__SHIFT 0xc
+#define SCLV_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1
+#define SCLV_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+#define SCLV_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x10
+#define SCLV_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4
+#define SCLV_CONTROL__SCL_TOTAL_PHASE_MASK 0x100
+#define SCLV_CONTROL__SCL_TOTAL_PHASE__SHIFT 0x8
+#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf
+#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00
+#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1
+#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
+#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000
+#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
+#define SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100
+#define SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff
+#define SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff
+#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000
+#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+#define SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x3ffffff
+#define SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0
+#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0xffffff
+#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0
+#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0xf000000
+#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18
+#define SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100
+#define SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff
+#define SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff
+#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000
+#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff
+#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000
+#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+#define SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x3ffffff
+#define SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0
+#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0xffffff
+#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0
+#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x7000000
+#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18
+#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0xffffff
+#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0
+#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x7000000
+#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18
+#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff
+#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
+#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000
+#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+#define SCLV_UPDATE__SCL_UPDATE_PENDING_MASK 0x1
+#define SCLV_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+#define SCLV_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100
+#define SCLV_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
+#define SCLV_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000
+#define SCLV_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
+#define SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000
+#define SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
+#define SCLV_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1
+#define SCLV_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
+#define SCLV_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff
+#define SCLV_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
+#define SCLV_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000
+#define SCLV_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
+#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x3fff
+#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0
+#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3fff0000
+#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10
+#define SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x1fff
+#define SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
+#define SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x1fff0000
+#define SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
+#define SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C_MASK 0x3fff
+#define SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C__SHIFT 0x0
+#define SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C_MASK 0x3fff0000
+#define SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C__SHIFT 0x10
+#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C_MASK 0x3fff
+#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C__SHIFT 0x0
+#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C_MASK 0x3fff0000
+#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C__SHIFT 0x10
+#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C_MASK 0x1fff
+#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C__SHIFT 0x0
+#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C_MASK 0x1fff0000
+#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C__SHIFT 0x10
+#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff
+#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000
+#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff
+#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000
+#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1
+#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
+#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10
+#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
+#define SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80
+#define SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
+#define SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff
+#define SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
+#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff
+#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
+#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000
+#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
+#define SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1
+#define SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
+#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT_MASK 0xffffff
+#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT__SHIFT 0x0
+#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT_MASK 0xf000000
+#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT__SHIFT 0x18
+#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C_MASK 0xffffff
+#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C__SHIFT 0x0
+#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C_MASK 0xf000000
+#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C__SHIFT 0x18
+#define SCLV_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1
+#define SCLV_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0
+#define SCLV_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6
+#define SCLV_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1
+#define SCLV_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8
+#define SCLV_DEBUG2__SCL_DEBUG2__SHIFT 0x3
+#define SCLV_DEBUG__SCL_DEBUG_MASK 0xffffffff
+#define SCLV_DEBUG__SCL_DEBUG__SHIFT 0x0
+#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff
+#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0
+#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define SCLV_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff
+#define SCLV_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0
+#define COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING_MASK 0x1
+#define COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING__SHIFT 0x0
+#define COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN_MASK 0x2
+#define COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN__SHIFT 0x1
+#define COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK_MASK 0x10000
+#define COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK__SHIFT 0x10
+#define COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
+#define COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE_MASK 0x3
+#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE__SHIFT 0x0
+#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE_MASK 0x300
+#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE__SHIFT 0x8
+#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE_MASK 0x10000
+#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE__SHIFT 0x10
+#define INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A_MASK 0xffff
+#define INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A__SHIFT 0x0
+#define INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A_MASK 0xffff0000
+#define INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A__SHIFT 0x10
+#define INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A_MASK 0xffff
+#define INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A__SHIFT 0x0
+#define INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A_MASK 0xffff0000
+#define INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A__SHIFT 0x10
+#define INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A_MASK 0xffff
+#define INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A__SHIFT 0x0
+#define INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A_MASK 0xffff0000
+#define INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A__SHIFT 0x10
+#define INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A_MASK 0xffff
+#define INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A__SHIFT 0x0
+#define INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A_MASK 0xffff0000
+#define INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A__SHIFT 0x10
+#define INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A_MASK 0xffff
+#define INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A__SHIFT 0x0
+#define INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A_MASK 0xffff0000
+#define INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A__SHIFT 0x10
+#define INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A_MASK 0xffff
+#define INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A__SHIFT 0x0
+#define INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A_MASK 0xffff0000
+#define INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A__SHIFT 0x10
+#define INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B_MASK 0xffff
+#define INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B__SHIFT 0x0
+#define INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B_MASK 0xffff0000
+#define INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B__SHIFT 0x10
+#define INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B_MASK 0xffff
+#define INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B__SHIFT 0x0
+#define INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B_MASK 0xffff0000
+#define INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B__SHIFT 0x10
+#define INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B_MASK 0xffff
+#define INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B__SHIFT 0x0
+#define INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B_MASK 0xffff0000
+#define INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B__SHIFT 0x10
+#define INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B_MASK 0xffff
+#define INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B__SHIFT 0x0
+#define INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B_MASK 0xffff0000
+#define INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B__SHIFT 0x10
+#define INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B_MASK 0xffff
+#define INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B__SHIFT 0x0
+#define INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B_MASK 0xffff0000
+#define INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B__SHIFT 0x10
+#define INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B_MASK 0xffff
+#define INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B__SHIFT 0x0
+#define INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B_MASK 0xffff0000
+#define INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B__SHIFT 0x10
+#define PRESCALE_CONTROL__PRESCALE_MODE_MASK 0x3
+#define PRESCALE_CONTROL__PRESCALE_MODE__SHIFT 0x0
+#define PRESCALE_VALUES_R__PRESCALE_BIAS_R_MASK 0xffff
+#define PRESCALE_VALUES_R__PRESCALE_BIAS_R__SHIFT 0x0
+#define PRESCALE_VALUES_R__PRESCALE_SCALE_R_MASK 0xffff0000
+#define PRESCALE_VALUES_R__PRESCALE_SCALE_R__SHIFT 0x10
+#define PRESCALE_VALUES_G__PRESCALE_BIAS_G_MASK 0xffff
+#define PRESCALE_VALUES_G__PRESCALE_BIAS_G__SHIFT 0x0
+#define PRESCALE_VALUES_G__PRESCALE_SCALE_G_MASK 0xffff0000
+#define PRESCALE_VALUES_G__PRESCALE_SCALE_G__SHIFT 0x10
+#define PRESCALE_VALUES_B__PRESCALE_BIAS_B_MASK 0xffff
+#define PRESCALE_VALUES_B__PRESCALE_BIAS_B__SHIFT 0x0
+#define PRESCALE_VALUES_B__PRESCALE_SCALE_B_MASK 0xffff0000
+#define PRESCALE_VALUES_B__PRESCALE_SCALE_B__SHIFT 0x10
+#define COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE_MASK 0x7
+#define COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE__SHIFT 0x0
+#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A_MASK 0xffff
+#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A__SHIFT 0x0
+#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A_MASK 0xffff0000
+#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A__SHIFT 0x10
+#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A_MASK 0xffff
+#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A__SHIFT 0x0
+#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A_MASK 0xffff0000
+#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A__SHIFT 0x10
+#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A_MASK 0xffff
+#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A__SHIFT 0x0
+#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A_MASK 0xffff0000
+#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A__SHIFT 0x10
+#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A_MASK 0xffff
+#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A__SHIFT 0x0
+#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A_MASK 0xffff0000
+#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A__SHIFT 0x10
+#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A_MASK 0xffff
+#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A__SHIFT 0x0
+#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A_MASK 0xffff0000
+#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A__SHIFT 0x10
+#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A_MASK 0xffff
+#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A__SHIFT 0x0
+#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A_MASK 0xffff0000
+#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A__SHIFT 0x10
+#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B_MASK 0xffff
+#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B__SHIFT 0x0
+#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B_MASK 0xffff0000
+#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B__SHIFT 0x10
+#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B_MASK 0xffff
+#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B__SHIFT 0x0
+#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B_MASK 0xffff0000
+#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B__SHIFT 0x10
+#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B_MASK 0xffff
+#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B__SHIFT 0x0
+#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B_MASK 0xffff0000
+#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B__SHIFT 0x10
+#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B_MASK 0xffff
+#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B__SHIFT 0x0
+#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B_MASK 0xffff0000
+#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B__SHIFT 0x10
+#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B_MASK 0xffff
+#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B__SHIFT 0x0
+#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B_MASK 0xffff0000
+#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B__SHIFT 0x10
+#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B_MASK 0xffff
+#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B__SHIFT 0x0
+#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B_MASK 0xffff0000
+#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B__SHIFT 0x10
+#define DENORM_CLAMP_CONTROL__DENORM_MODE_MASK 0x3
+#define DENORM_CLAMP_CONTROL__DENORM_MODE__SHIFT 0x0
+#define DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT_MASK 0x100
+#define DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT__SHIFT 0x8
+#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR_MASK 0xfff
+#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR__SHIFT 0x0
+#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR_MASK 0xfff000
+#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR__SHIFT 0xc
+#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y_MASK 0xfff
+#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y__SHIFT 0x0
+#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y_MASK 0xfff000
+#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y__SHIFT 0xc
+#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB_MASK 0xfff
+#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB__SHIFT 0x0
+#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB_MASK 0xfff000
+#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB__SHIFT 0xc
+#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff
+#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
+#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX_MASK 0x3f00000
+#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
+#define GAMMA_CORR_CONTROL__GAMMA_CORR_MODE_MASK 0x3
+#define GAMMA_CORR_CONTROL__GAMMA_CORR_MODE__SHIFT 0x0
+#define GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX_MASK 0xff
+#define GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX__SHIFT 0x0
+#define GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA_MASK 0x7ffff
+#define GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA__SHIFT 0x0
+#define GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK_MASK 0x7
+#define GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_MASK 0x3ffff
+#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000
+#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
+#define GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END_MASK 0xffff
+#define GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff
+#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000
+#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_MASK 0x3ffff
+#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000
+#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
+#define GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END_MASK 0xffff
+#define GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff
+#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000
+#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b
+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0xff
+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x3800
+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb
+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x7f8000
+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0xf
+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000
+#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b
+#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED_MASK 0x1
+#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED__SHIFT 0x0
+#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK_MASK 0x2
+#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK__SHIFT 0x1
+#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED_MASK 0x100
+#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED__SHIFT 0x8
+#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK_MASK 0x200
+#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK__SHIFT 0x9
+#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED_MASK 0x10000
+#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED__SHIFT 0x10
+#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK_MASK 0x20000
+#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK__SHIFT 0x11
+#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED_MASK 0x1000000
+#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED__SHIFT 0x18
+#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK_MASK 0x2000000
+#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK__SHIFT 0x19
+#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED_MASK 0x1
+#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED__SHIFT 0x0
+#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK_MASK 0x2
+#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK__SHIFT 0x1
+#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED_MASK 0x100
+#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED__SHIFT 0x8
+#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK_MASK 0x200
+#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK__SHIFT 0x9
+#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_MASK 0x1
+#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL__SHIFT 0x0
+#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE_MASK 0x2
+#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE__SHIFT 0x1
+#define INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX_MASK 0xff
+#define INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX__SHIFT 0x0
+#define INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR_MASK 0xffff
+#define INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR__SHIFT 0x0
+#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE_MASK 0xffff
+#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE__SHIFT 0x0
+#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA_MASK 0xffff0000
+#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA__SHIFT 0x10
+#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE_MASK 0x3ff
+#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE__SHIFT 0x0
+#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN_MASK 0xffc00
+#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN__SHIFT 0xa
+#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED_MASK 0x3ff00000
+#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED__SHIFT 0x14
+#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE_MASK 0x3
+#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE__SHIFT 0x0
+#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN_MASK 0x4000000
+#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN__SHIFT 0x1a
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B_MASK 0x1e
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B__SHIFT 0x1
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN_MASK 0x20
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN__SHIFT 0x5
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT_MASK 0xc0
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT__SHIFT 0x6
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G_MASK 0xf00
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G__SHIFT 0x8
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN_MASK 0x1000
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN__SHIFT 0xc
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT_MASK 0x6000
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT__SHIFT 0xd
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R_MASK 0x78000
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R__SHIFT 0xf
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN_MASK 0x80000
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN__SHIFT 0x13
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT_MASK 0x300000
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT__SHIFT 0x14
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE_MASK 0x400000
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE__SHIFT 0x16
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK_MASK 0x3800000
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK__SHIFT 0x17
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE_MASK 0x4000000
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE__SHIFT 0x1a
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x8000000
+#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x1b
+#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B_MASK 0xffff
+#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B__SHIFT 0x0
+#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B_MASK 0xffff0000
+#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B__SHIFT 0x10
+#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G_MASK 0xffff
+#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G__SHIFT 0x0
+#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G_MASK 0xffff0000
+#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G__SHIFT 0x10
+#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R_MASK 0xffff
+#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R__SHIFT 0x0
+#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R_MASK 0xffff0000
+#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R__SHIFT 0x10
+#define COL_MAN_DEBUG_CONTROL__COL_MAN_GLOBAL_PASSTHROUGH_ENABLE_MASK 0x1
+#define COL_MAN_DEBUG_CONTROL__COL_MAN_GLOBAL_PASSTHROUGH_ENABLE__SHIFT 0x0
+#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_INDEX_MASK 0xff
+#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_INDEX__SHIFT 0x0
+#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define COL_MAN_TEST_DEBUG_DATA__COL_MAN_TEST_DEBUG_DATA_MASK 0xffffffff
+#define COL_MAN_TEST_DEBUG_DATA__COL_MAN_TEST_DEBUG_DATA__SHIFT 0x0
+#define UNP_GRPH_ENABLE__GRPH_ENABLE_MASK 0x1
+#define UNP_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
+#define UNP_GRPH_CONTROL__GRPH_DEPTH_MASK 0x3
+#define UNP_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
+#define UNP_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc
+#define UNP_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2
+#define UNP_GRPH_CONTROL__GRPH_Z_MASK 0x30
+#define UNP_GRPH_CONTROL__GRPH_Z__SHIFT 0x4
+#define UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L_MASK 0xc0
+#define UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L__SHIFT 0x6
+#define UNP_GRPH_CONTROL__GRPH_FORMAT_MASK 0x700
+#define UNP_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
+#define UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L_MASK 0x1800
+#define UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L__SHIFT 0xb
+#define UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L_MASK 0xe000
+#define UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L__SHIFT 0xd
+#define UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000
+#define UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
+#define UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000
+#define UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
+#define UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L_MASK 0xc0000
+#define UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L__SHIFT 0x12
+#define UNP_GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000
+#define UNP_GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14
+#define UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000
+#define UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18
+#define UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L_MASK 0x60000000
+#define UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L__SHIFT 0x1d
+#define UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000
+#define UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
+#define UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C_MASK 0xc0
+#define UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C__SHIFT 0x6
+#define UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C_MASK 0x1800
+#define UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C__SHIFT 0xb
+#define UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C_MASK 0xe000
+#define UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C__SHIFT 0xd
+#define UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C_MASK 0xc0000
+#define UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C__SHIFT 0x12
+#define UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C_MASK 0x60000000
+#define UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C__SHIFT 0x1d
+#define UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT_MASK 0x7
+#define UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT__SHIFT 0x0
+#define UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3
+#define UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
+#define UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30
+#define UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
+#define UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0
+#define UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
+#define UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300
+#define UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L_MASK 0xffffff00
+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT 0x8
+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C_MASK 0xffffff00
+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x8
+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK 0xff
+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0xff
+#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xffffff00
+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8
+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xffffff00
+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8
+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0xff
+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0xff
+#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L_MASK 0xffffff00
+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L__SHIFT 0x8
+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C_MASK 0xffffff00
+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x8
+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_MASK 0xff
+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0xff
+#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xffffff00
+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8
+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xffffff00
+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8
+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0xff
+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0
+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0xff
+#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0
+#define UNP_GRPH_PITCH_L__GRPH_PITCH_L_MASK 0x7fff
+#define UNP_GRPH_PITCH_L__GRPH_PITCH_L__SHIFT 0x0
+#define UNP_GRPH_PITCH_C__GRPH_PITCH_C_MASK 0x7fff
+#define UNP_GRPH_PITCH_C__GRPH_PITCH_C__SHIFT 0x0
+#define UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L_MASK 0x3fff
+#define UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L__SHIFT 0x0
+#define UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C_MASK 0x3fff
+#define UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C__SHIFT 0x0
+#define UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L_MASK 0x3fff
+#define UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L__SHIFT 0x0
+#define UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C_MASK 0x3fff
+#define UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C__SHIFT 0x0
+#define UNP_GRPH_X_START_L__GRPH_X_START_L_MASK 0x3fff
+#define UNP_GRPH_X_START_L__GRPH_X_START_L__SHIFT 0x0
+#define UNP_GRPH_X_START_C__GRPH_X_START_C_MASK 0x3fff
+#define UNP_GRPH_X_START_C__GRPH_X_START_C__SHIFT 0x0
+#define UNP_GRPH_Y_START_L__GRPH_Y_START_L_MASK 0x3fff
+#define UNP_GRPH_Y_START_L__GRPH_Y_START_L__SHIFT 0x0
+#define UNP_GRPH_Y_START_C__GRPH_Y_START_C_MASK 0x3fff
+#define UNP_GRPH_Y_START_C__GRPH_Y_START_C__SHIFT 0x0
+#define UNP_GRPH_X_END_L__GRPH_X_END_L_MASK 0x7fff
+#define UNP_GRPH_X_END_L__GRPH_X_END_L__SHIFT 0x0
+#define UNP_GRPH_X_END_C__GRPH_X_END_C_MASK 0x7fff
+#define UNP_GRPH_X_END_C__GRPH_X_END_C__SHIFT 0x0
+#define UNP_GRPH_Y_END_L__GRPH_Y_END_L_MASK 0x7fff
+#define UNP_GRPH_Y_END_L__GRPH_Y_END_L__SHIFT 0x0
+#define UNP_GRPH_Y_END_C__GRPH_Y_END_C_MASK 0x7fff
+#define UNP_GRPH_Y_END_C__GRPH_Y_END_C__SHIFT 0x0
+#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1
+#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
+#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2
+#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
+#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4
+#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
+#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8
+#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
+#define UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000
+#define UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
+#define UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000
+#define UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
+#define UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
+#define UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000
+#define UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
+#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L_MASK 0xff
+#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L__SHIFT 0x0
+#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C_MASK 0xff00
+#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C__SHIFT 0x8
+#define UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L_MASK 0xffffff00
+#define UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L__SHIFT 0x8
+#define UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C_MASK 0xffffff00
+#define UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C__SHIFT 0x8
+#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_MASK 0xff
+#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__SHIFT 0x0
+#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_MASK 0xff
+#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__SHIFT 0x0
+#define UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x1
+#define UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0
+#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x1e
+#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1
+#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x1e0
+#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5
+#define UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x7fe00
+#define UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9
+#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x100000
+#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14
+#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x200000
+#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15
+#define UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C_MASK 0x1
+#define UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C__SHIFT 0x0
+#define UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C_MASK 0x1e
+#define UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C__SHIFT 0x1
+#define UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C_MASK 0x1e0
+#define UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C__SHIFT 0x5
+#define UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C_MASK 0x7fe00
+#define UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C__SHIFT 0x9
+#define UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C_MASK 0x100000
+#define UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C__SHIFT 0x14
+#define UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C_MASK 0x200000
+#define UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C__SHIFT 0x15
+#define UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x3f
+#define UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0
+#define UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0xff00
+#define UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8
+#define UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C_MASK 0x3f
+#define UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C__SHIFT 0x0
+#define UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C_MASK 0xff00
+#define UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C__SHIFT 0x8
+#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1
+#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
+#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100
+#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
+#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1
+#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
+#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100
+#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x30
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x4
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN_MASK 0x100
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN__SHIFT 0x8
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE_MASK 0x3000
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE__SHIFT 0xc
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING_MASK 0x40000
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING__SHIFT 0x12
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING_MASK 0x80000
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING__SHIFT 0x13
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000
+#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
+#define UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x1
+#define UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x0
+#define UNP_FLIP_CONTROL__UNP_DEBUG_SG_MASK 0xfffffffc
+#define UNP_FLIP_CONTROL__UNP_DEBUG_SG__SHIFT 0x2
+#define UNP_CRC_CONTROL__UNP_CRC_ENABLE_MASK 0x1
+#define UNP_CRC_CONTROL__UNP_CRC_ENABLE__SHIFT 0x0
+#define UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL_MASK 0x1c
+#define UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL__SHIFT 0x2
+#define UNP_CRC_CONTROL__UNP_CRC_LINE_SEL_MASK 0x300
+#define UNP_CRC_CONTROL__UNP_CRC_LINE_SEL__SHIFT 0x8
+#define UNP_CRC_MASK__UNP_CRC_MASK_MASK 0xffffffff
+#define UNP_CRC_MASK__UNP_CRC_MASK__SHIFT 0x0
+#define UNP_CRC_CURRENT__UNP_CRC_CURRENT_MASK 0xffffffff
+#define UNP_CRC_CURRENT__UNP_CRC_CURRENT__SHIFT 0x0
+#define UNP_CRC_LAST__UNP_CRC_LAST_MASK 0xffffffff
+#define UNP_CRC_LAST__UNP_CRC_LAST__SHIFT 0x0
+#define UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK_MASK 0x1f0
+#define UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK__SHIFT 0x4
+#define UNP_HW_ROTATION__ROTATION_ANGLE_MASK 0x7
+#define UNP_HW_ROTATION__ROTATION_ANGLE__SHIFT 0x0
+#define UNP_HW_ROTATION__PIXEL_DROP_MASK 0x10
+#define UNP_HW_ROTATION__PIXEL_DROP__SHIFT 0x4
+#define UNP_HW_ROTATION__BUFFER_MODE_MASK 0x100
+#define UNP_HW_ROTATION__BUFFER_MODE__SHIFT 0x8
+#define UNP_DEBUG__UNP_DEBUG_MASK 0xffffffff
+#define UNP_DEBUG__UNP_DEBUG__SHIFT 0x0
+#define UNP_DEBUG2__UNP_DEBUG2_MASK 0xffffffff
+#define UNP_DEBUG2__UNP_DEBUG2__SHIFT 0x0
+#define UNP_DVMM_DEBUG__UNP_L_DVMM_DEBUG_MASK 0xffff
+#define UNP_DVMM_DEBUG__UNP_L_DVMM_DEBUG__SHIFT 0x0
+#define UNP_DVMM_DEBUG__UNP_C_DVMM_DEBUG_MASK 0xffff0000
+#define UNP_DVMM_DEBUG__UNP_C_DVMM_DEBUG__SHIFT 0x10
+#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX_MASK 0xff
+#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX__SHIFT 0x0
+#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA_MASK 0xffffffff
+#define UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA__SHIFT 0x0
+#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x1
+#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0
+#define GENMO_WT__VGA_RAM_EN_MASK 0x2
+#define GENMO_WT__VGA_RAM_EN__SHIFT 0x1
+#define GENMO_WT__VGA_CKSEL_MASK 0xc
+#define GENMO_WT__VGA_CKSEL__SHIFT 0x2
+#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20
+#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5
+#define GENMO_WT__VGA_HSYNC_POL_MASK 0x40
+#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6
+#define GENMO_WT__VGA_VSYNC_POL_MASK 0x80
+#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7
+#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x1
+#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0
+#define GENMO_RD__VGA_RAM_EN_MASK 0x2
+#define GENMO_RD__VGA_RAM_EN__SHIFT 0x1
+#define GENMO_RD__VGA_CKSEL_MASK 0xc
+#define GENMO_RD__VGA_CKSEL__SHIFT 0x2
+#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20
+#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5
+#define GENMO_RD__VGA_HSYNC_POL_MASK 0x40
+#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6
+#define GENMO_RD__VGA_VSYNC_POL_MASK 0x80
+#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7
+#define GENENB__BLK_IO_BASE_MASK 0xff
+#define GENENB__BLK_IO_BASE__SHIFT 0x0
+#define GENFC_WT__VSYNC_SEL_W_MASK 0x8
+#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3
+#define GENFC_RD__VSYNC_SEL_R_MASK 0x8
+#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3
+#define GENS0__SENSE_SWITCH_MASK 0x10
+#define GENS0__SENSE_SWITCH__SHIFT 0x4
+#define GENS0__CRT_INTR_MASK 0x80
+#define GENS0__CRT_INTR__SHIFT 0x7
+#define GENS1__NO_DISPLAY_MASK 0x1
+#define GENS1__NO_DISPLAY__SHIFT 0x0
+#define GENS1__VGA_VSTATUS_MASK 0x8
+#define GENS1__VGA_VSTATUS__SHIFT 0x3
+#define GENS1__PIXEL_READ_BACK_MASK 0x30
+#define GENS1__PIXEL_READ_BACK__SHIFT 0x4
+#define DAC_DATA__DAC_DATA_MASK 0x3f
+#define DAC_DATA__DAC_DATA__SHIFT 0x0
+#define DAC_MASK__DAC_MASK_MASK 0xff
+#define DAC_MASK__DAC_MASK__SHIFT 0x0
+#define DAC_R_INDEX__DAC_R_INDEX_MASK 0xff
+#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0
+#define DAC_W_INDEX__DAC_W_INDEX_MASK 0xff
+#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0
+#define SEQ8_IDX__SEQ_IDX_MASK 0x7
+#define SEQ8_IDX__SEQ_IDX__SHIFT 0x0
+#define SEQ8_DATA__SEQ_DATA_MASK 0xff
+#define SEQ8_DATA__SEQ_DATA__SHIFT 0x0
+#define SEQ00__SEQ_RST0B_MASK 0x1
+#define SEQ00__SEQ_RST0B__SHIFT 0x0
+#define SEQ00__SEQ_RST1B_MASK 0x2
+#define SEQ00__SEQ_RST1B__SHIFT 0x1
+#define SEQ01__SEQ_DOT8_MASK 0x1
+#define SEQ01__SEQ_DOT8__SHIFT 0x0
+#define SEQ01__SEQ_SHIFT2_MASK 0x4
+#define SEQ01__SEQ_SHIFT2__SHIFT 0x2
+#define SEQ01__SEQ_PCLKBY2_MASK 0x8
+#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3
+#define SEQ01__SEQ_SHIFT4_MASK 0x10
+#define SEQ01__SEQ_SHIFT4__SHIFT 0x4
+#define SEQ01__SEQ_MAXBW_MASK 0x20
+#define SEQ01__SEQ_MAXBW__SHIFT 0x5
+#define SEQ02__SEQ_MAP0_EN_MASK 0x1
+#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0
+#define SEQ02__SEQ_MAP1_EN_MASK 0x2
+#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1
+#define SEQ02__SEQ_MAP2_EN_MASK 0x4
+#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2
+#define SEQ02__SEQ_MAP3_EN_MASK 0x8
+#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3
+#define SEQ03__SEQ_FONT_B1_MASK 0x1
+#define SEQ03__SEQ_FONT_B1__SHIFT 0x0
+#define SEQ03__SEQ_FONT_B2_MASK 0x2
+#define SEQ03__SEQ_FONT_B2__SHIFT 0x1
+#define SEQ03__SEQ_FONT_A1_MASK 0x4
+#define SEQ03__SEQ_FONT_A1__SHIFT 0x2
+#define SEQ03__SEQ_FONT_A2_MASK 0x8
+#define SEQ03__SEQ_FONT_A2__SHIFT 0x3
+#define SEQ03__SEQ_FONT_B0_MASK 0x10
+#define SEQ03__SEQ_FONT_B0__SHIFT 0x4
+#define SEQ03__SEQ_FONT_A0_MASK 0x20
+#define SEQ03__SEQ_FONT_A0__SHIFT 0x5
+#define SEQ04__SEQ_256K_MASK 0x2
+#define SEQ04__SEQ_256K__SHIFT 0x1
+#define SEQ04__SEQ_ODDEVEN_MASK 0x4
+#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2
+#define SEQ04__SEQ_CHAIN_MASK 0x8
+#define SEQ04__SEQ_CHAIN__SHIFT 0x3
+#define CRTC8_IDX__VCRTC_IDX_MASK 0x3f
+#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0
+#define CRTC8_DATA__VCRTC_DATA_MASK 0xff
+#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0
+#define CRT00__H_TOTAL_MASK 0xff
+#define CRT00__H_TOTAL__SHIFT 0x0
+#define CRT01__H_DISP_END_MASK 0xff
+#define CRT01__H_DISP_END__SHIFT 0x0
+#define CRT02__H_BLANK_START_MASK 0xff
+#define CRT02__H_BLANK_START__SHIFT 0x0
+#define CRT03__H_BLANK_END_MASK 0x1f
+#define CRT03__H_BLANK_END__SHIFT 0x0
+#define CRT03__H_DE_SKEW_MASK 0x60
+#define CRT03__H_DE_SKEW__SHIFT 0x5
+#define CRT03__CR10CR11_R_DIS_B_MASK 0x80
+#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7
+#define CRT04__H_SYNC_START_MASK 0xff
+#define CRT04__H_SYNC_START__SHIFT 0x0
+#define CRT05__H_SYNC_END_MASK 0x1f
+#define CRT05__H_SYNC_END__SHIFT 0x0
+#define CRT05__H_SYNC_SKEW_MASK 0x60
+#define CRT05__H_SYNC_SKEW__SHIFT 0x5
+#define CRT05__H_BLANK_END_B5_MASK 0x80
+#define CRT05__H_BLANK_END_B5__SHIFT 0x7
+#define CRT06__V_TOTAL_MASK 0xff
+#define CRT06__V_TOTAL__SHIFT 0x0
+#define CRT07__V_TOTAL_B8_MASK 0x1
+#define CRT07__V_TOTAL_B8__SHIFT 0x0
+#define CRT07__V_DISP_END_B8_MASK 0x2
+#define CRT07__V_DISP_END_B8__SHIFT 0x1
+#define CRT07__V_SYNC_START_B8_MASK 0x4
+#define CRT07__V_SYNC_START_B8__SHIFT 0x2
+#define CRT07__V_BLANK_START_B8_MASK 0x8
+#define CRT07__V_BLANK_START_B8__SHIFT 0x3
+#define CRT07__LINE_CMP_B8_MASK 0x10
+#define CRT07__LINE_CMP_B8__SHIFT 0x4
+#define CRT07__V_TOTAL_B9_MASK 0x20
+#define CRT07__V_TOTAL_B9__SHIFT 0x5
+#define CRT07__V_DISP_END_B9_MASK 0x40
+#define CRT07__V_DISP_END_B9__SHIFT 0x6
+#define CRT07__V_SYNC_START_B9_MASK 0x80
+#define CRT07__V_SYNC_START_B9__SHIFT 0x7
+#define CRT08__ROW_SCAN_START_MASK 0x1f
+#define CRT08__ROW_SCAN_START__SHIFT 0x0
+#define CRT08__BYTE_PAN_MASK 0x60
+#define CRT08__BYTE_PAN__SHIFT 0x5
+#define CRT09__MAX_ROW_SCAN_MASK 0x1f
+#define CRT09__MAX_ROW_SCAN__SHIFT 0x0
+#define CRT09__V_BLANK_START_B9_MASK 0x20
+#define CRT09__V_BLANK_START_B9__SHIFT 0x5
+#define CRT09__LINE_CMP_B9_MASK 0x40
+#define CRT09__LINE_CMP_B9__SHIFT 0x6
+#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80
+#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7
+#define CRT0A__CURSOR_START_MASK 0x1f
+#define CRT0A__CURSOR_START__SHIFT 0x0
+#define CRT0A__CURSOR_DISABLE_MASK 0x20
+#define CRT0A__CURSOR_DISABLE__SHIFT 0x5
+#define CRT0B__CURSOR_END_MASK 0x1f
+#define CRT0B__CURSOR_END__SHIFT 0x0
+#define CRT0B__CURSOR_SKEW_MASK 0x60
+#define CRT0B__CURSOR_SKEW__SHIFT 0x5
+#define CRT0C__DISP_START_MASK 0xff
+#define CRT0C__DISP_START__SHIFT 0x0
+#define CRT0D__DISP_START_MASK 0xff
+#define CRT0D__DISP_START__SHIFT 0x0
+#define CRT0E__CURSOR_LOC_HI_MASK 0xff
+#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0
+#define CRT0F__CURSOR_LOC_LO_MASK 0xff
+#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0
+#define CRT10__V_SYNC_START_MASK 0xff
+#define CRT10__V_SYNC_START__SHIFT 0x0
+#define CRT11__V_SYNC_END_MASK 0xf
+#define CRT11__V_SYNC_END__SHIFT 0x0
+#define CRT11__V_INTR_CLR_MASK 0x10
+#define CRT11__V_INTR_CLR__SHIFT 0x4
+#define CRT11__V_INTR_EN_MASK 0x20
+#define CRT11__V_INTR_EN__SHIFT 0x5
+#define CRT11__SEL5_REFRESH_CYC_MASK 0x40
+#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6
+#define CRT11__C0T7_WR_ONLY_MASK 0x80
+#define CRT11__C0T7_WR_ONLY__SHIFT 0x7
+#define CRT12__V_DISP_END_MASK 0xff
+#define CRT12__V_DISP_END__SHIFT 0x0
+#define CRT13__DISP_PITCH_MASK 0xff
+#define CRT13__DISP_PITCH__SHIFT 0x0
+#define CRT14__UNDRLN_LOC_MASK 0x1f
+#define CRT14__UNDRLN_LOC__SHIFT 0x0
+#define CRT14__ADDR_CNT_BY4_MASK 0x20
+#define CRT14__ADDR_CNT_BY4__SHIFT 0x5
+#define CRT14__DOUBLE_WORD_MASK 0x40
+#define CRT14__DOUBLE_WORD__SHIFT 0x6
+#define CRT15__V_BLANK_START_MASK 0xff
+#define CRT15__V_BLANK_START__SHIFT 0x0
+#define CRT16__V_BLANK_END_MASK 0xff
+#define CRT16__V_BLANK_END__SHIFT 0x0
+#define CRT17__RA0_AS_A13B_MASK 0x1
+#define CRT17__RA0_AS_A13B__SHIFT 0x0
+#define CRT17__RA1_AS_A14B_MASK 0x2
+#define CRT17__RA1_AS_A14B__SHIFT 0x1
+#define CRT17__VCOUNT_BY2_MASK 0x4
+#define CRT17__VCOUNT_BY2__SHIFT 0x2
+#define CRT17__ADDR_CNT_BY2_MASK 0x8
+#define CRT17__ADDR_CNT_BY2__SHIFT 0x3
+#define CRT17__WRAP_A15TOA0_MASK 0x20
+#define CRT17__WRAP_A15TOA0__SHIFT 0x5
+#define CRT17__BYTE_MODE_MASK 0x40
+#define CRT17__BYTE_MODE__SHIFT 0x6
+#define CRT17__CRTC_SYNC_EN_MASK 0x80
+#define CRT17__CRTC_SYNC_EN__SHIFT 0x7
+#define CRT18__LINE_CMP_MASK 0xff
+#define CRT18__LINE_CMP__SHIFT 0x0
+#define CRT1E__GRPH_DEC_RD1_MASK 0x2
+#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1
+#define CRT1F__GRPH_DEC_RD0_MASK 0xff
+#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0
+#define CRT22__GRPH_LATCH_DATA_MASK 0xff
+#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0
+#define GRPH8_IDX__GRPH_IDX_MASK 0xf
+#define GRPH8_IDX__GRPH_IDX__SHIFT 0x0
+#define GRPH8_DATA__GRPH_DATA_MASK 0xff
+#define GRPH8_DATA__GRPH_DATA__SHIFT 0x0
+#define GRA00__GRPH_SET_RESET0_MASK 0x1
+#define GRA00__GRPH_SET_RESET0__SHIFT 0x0
+#define GRA00__GRPH_SET_RESET1_MASK 0x2
+#define GRA00__GRPH_SET_RESET1__SHIFT 0x1
+#define GRA00__GRPH_SET_RESET2_MASK 0x4
+#define GRA00__GRPH_SET_RESET2__SHIFT 0x2
+#define GRA00__GRPH_SET_RESET3_MASK 0x8
+#define GRA00__GRPH_SET_RESET3__SHIFT 0x3
+#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x1
+#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0
+#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x2
+#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1
+#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x4
+#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2
+#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x8
+#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3
+#define GRA02__GRPH_CCOMP_MASK 0xf
+#define GRA02__GRPH_CCOMP__SHIFT 0x0
+#define GRA03__GRPH_ROTATE_MASK 0x7
+#define GRA03__GRPH_ROTATE__SHIFT 0x0
+#define GRA03__GRPH_FN_SEL_MASK 0x18
+#define GRA03__GRPH_FN_SEL__SHIFT 0x3
+#define GRA04__GRPH_RMAP_MASK 0x3
+#define GRA04__GRPH_RMAP__SHIFT 0x0
+#define GRA05__GRPH_WRITE_MODE_MASK 0x3
+#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0
+#define GRA05__GRPH_READ1_MASK 0x8
+#define GRA05__GRPH_READ1__SHIFT 0x3
+#define GRA05__CGA_ODDEVEN_MASK 0x10
+#define GRA05__CGA_ODDEVEN__SHIFT 0x4
+#define GRA05__GRPH_OES_MASK 0x20
+#define GRA05__GRPH_OES__SHIFT 0x5
+#define GRA05__GRPH_PACK_MASK 0x40
+#define GRA05__GRPH_PACK__SHIFT 0x6
+#define GRA06__GRPH_GRAPHICS_MASK 0x1
+#define GRA06__GRPH_GRAPHICS__SHIFT 0x0
+#define GRA06__GRPH_ODDEVEN_MASK 0x2
+#define GRA06__GRPH_ODDEVEN__SHIFT 0x1
+#define GRA06__GRPH_ADRSEL_MASK 0xc
+#define GRA06__GRPH_ADRSEL__SHIFT 0x2
+#define GRA07__GRPH_XCARE0_MASK 0x1
+#define GRA07__GRPH_XCARE0__SHIFT 0x0
+#define GRA07__GRPH_XCARE1_MASK 0x2
+#define GRA07__GRPH_XCARE1__SHIFT 0x1
+#define GRA07__GRPH_XCARE2_MASK 0x4
+#define GRA07__GRPH_XCARE2__SHIFT 0x2
+#define GRA07__GRPH_XCARE3_MASK 0x8
+#define GRA07__GRPH_XCARE3__SHIFT 0x3
+#define GRA08__GRPH_BMSK_MASK 0xff
+#define GRA08__GRPH_BMSK__SHIFT 0x0
+#define ATTRX__ATTR_IDX_MASK 0x1f
+#define ATTRX__ATTR_IDX__SHIFT 0x0
+#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20
+#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5
+#define ATTRDW__ATTR_DATA_MASK 0xff
+#define ATTRDW__ATTR_DATA__SHIFT 0x0
+#define ATTRDR__ATTR_DATA_MASK 0xff
+#define ATTRDR__ATTR_DATA__SHIFT 0x0
+#define ATTR00__ATTR_PAL_MASK 0x3f
+#define ATTR00__ATTR_PAL__SHIFT 0x0
+#define ATTR01__ATTR_PAL_MASK 0x3f
+#define ATTR01__ATTR_PAL__SHIFT 0x0
+#define ATTR02__ATTR_PAL_MASK 0x3f
+#define ATTR02__ATTR_PAL__SHIFT 0x0
+#define ATTR03__ATTR_PAL_MASK 0x3f
+#define ATTR03__ATTR_PAL__SHIFT 0x0
+#define ATTR04__ATTR_PAL_MASK 0x3f
+#define ATTR04__ATTR_PAL__SHIFT 0x0
+#define ATTR05__ATTR_PAL_MASK 0x3f
+#define ATTR05__ATTR_PAL__SHIFT 0x0
+#define ATTR06__ATTR_PAL_MASK 0x3f
+#define ATTR06__ATTR_PAL__SHIFT 0x0
+#define ATTR07__ATTR_PAL_MASK 0x3f
+#define ATTR07__ATTR_PAL__SHIFT 0x0
+#define ATTR08__ATTR_PAL_MASK 0x3f
+#define ATTR08__ATTR_PAL__SHIFT 0x0
+#define ATTR09__ATTR_PAL_MASK 0x3f
+#define ATTR09__ATTR_PAL__SHIFT 0x0
+#define ATTR0A__ATTR_PAL_MASK 0x3f
+#define ATTR0A__ATTR_PAL__SHIFT 0x0
+#define ATTR0B__ATTR_PAL_MASK 0x3f
+#define ATTR0B__ATTR_PAL__SHIFT 0x0
+#define ATTR0C__ATTR_PAL_MASK 0x3f
+#define ATTR0C__ATTR_PAL__SHIFT 0x0
+#define ATTR0D__ATTR_PAL_MASK 0x3f
+#define ATTR0D__ATTR_PAL__SHIFT 0x0
+#define ATTR0E__ATTR_PAL_MASK 0x3f
+#define ATTR0E__ATTR_PAL__SHIFT 0x0
+#define ATTR0F__ATTR_PAL_MASK 0x3f
+#define ATTR0F__ATTR_PAL__SHIFT 0x0
+#define ATTR10__ATTR_GRPH_MODE_MASK 0x1
+#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0
+#define ATTR10__ATTR_MONO_EN_MASK 0x2
+#define ATTR10__ATTR_MONO_EN__SHIFT 0x1
+#define ATTR10__ATTR_LGRPH_EN_MASK 0x4
+#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2
+#define ATTR10__ATTR_BLINK_EN_MASK 0x8
+#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3
+#define ATTR10__ATTR_PANTOPONLY_MASK 0x20
+#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5
+#define ATTR10__ATTR_PCLKBY2_MASK 0x40
+#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6
+#define ATTR10__ATTR_CSEL_EN_MASK 0x80
+#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7
+#define ATTR11__ATTR_OVSC_MASK 0xff
+#define ATTR11__ATTR_OVSC__SHIFT 0x0
+#define ATTR12__ATTR_MAP_EN_MASK 0xf
+#define ATTR12__ATTR_MAP_EN__SHIFT 0x0
+#define ATTR12__ATTR_VSMUX_MASK 0x30
+#define ATTR12__ATTR_VSMUX__SHIFT 0x4
+#define ATTR13__ATTR_PPAN_MASK 0xf
+#define ATTR13__ATTR_PPAN__SHIFT 0x0
+#define ATTR14__ATTR_CSEL1_MASK 0x3
+#define ATTR14__ATTR_CSEL1__SHIFT 0x0
+#define ATTR14__ATTR_CSEL2_MASK 0xc
+#define ATTR14__ATTR_CSEL2__SHIFT 0x2
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x1f
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x60
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x80
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x100
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x30000
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x1000000
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18
+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x2000000
+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x7
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x700
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x1
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x2
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x4
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x8
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x10
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x20
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x100
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x200
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x400
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x800
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x1000
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x2000
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x10000
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x20000
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0xfc0000
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x1
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x30
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x100
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x10000
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x3
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x300
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xffffffff
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0xff
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x1ffffff
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x1ffffff
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x1
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x10
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x100
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x10000
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x1000000
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x1
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x100
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x10000
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x100000
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3f000000
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x1
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x100
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x200
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x10000
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x3000000
+#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x1
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x100
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x200
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x10000
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x3000000
+#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x1
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x100
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x200
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x10000
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x3000000
+#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x1
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x100
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x200
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x10000
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x3000000
+#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x1
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x100
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x200
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x10000
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x3000000
+#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x1
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x100
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x200
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x10000
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x3000000
+#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18
+#define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK 0xffffffff
+#define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT 0x0
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x1
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x2
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x4
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x8
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x1
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x100
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x10000
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x1000000
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x1
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x100
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x10000
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x1000000
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x1
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x2
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x4
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x8
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x3
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x18
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0xe0
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x300
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8
+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK 0xf000
+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT 0xc
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x30000
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x3000000
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x4000000
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a
+#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK 0x8000000
+#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT 0x1b
+#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK 0x10000000
+#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT 0x1c
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x1
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x100
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x10000
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x1000000
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18
+#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK 0xff
+#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT 0x0
+#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK 0xffffffff
+#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT 0x0
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x3ff
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x3ff0000
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x3ff
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x3ff0000
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
+#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK 0xff
+#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT 0x0
+#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK 0xffffffff
+#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT 0x0
+#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff
+#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x3
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x0
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x3f00
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x8
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x3f0000
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x10
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0xf000000
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x18
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x1c
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x1
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x0
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x2
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x1
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x4
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x2
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x3ff0
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x4
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x700000
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x14
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x1c
+#define PLL_REF_DIV__PLL_REF_DIV_MASK 0x3ff
+#define PLL_REF_DIV__PLL_REF_DIV__SHIFT 0x0
+#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV_MASK 0xf000
+#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV__SHIFT 0xc
+#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_MASK 0xf
+#define PLL_FB_DIV__PLL_FB_DIV_FRACTION__SHIFT 0x0
+#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL_MASK 0x30
+#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
+#define PLL_FB_DIV__PLL_FB_DIV_MASK 0xfff0000
+#define PLL_FB_DIV__PLL_FB_DIV__SHIFT 0x10
+#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK 0x7f
+#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK__SHIFT 0x0
+#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK_MASK 0x80
+#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x7
+#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK_MASK 0x7f00
+#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK__SHIFT 0x8
+#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK_MASK 0x8000
+#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK__SHIFT 0xf
+#define PLL_POST_DIV__PLL_POST_DIV_IDCLK_MASK 0x7f0000
+#define PLL_POST_DIV__PLL_POST_DIV_IDCLK__SHIFT 0x10
+#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC_MASK 0xffff
+#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC__SHIFT 0x0
+#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV_MASK 0xff
+#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x0
+#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP_MASK 0xf00
+#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT 0x8
+#define PLL_SS_CNTL__PLL_SS_EN_MASK 0x1000
+#define PLL_SS_CNTL__PLL_SS_EN__SHIFT 0xc
+#define PLL_SS_CNTL__PLL_SS_MODE_MASK 0x2000
+#define PLL_SS_CNTL__PLL_SS_MODE__SHIFT 0xd
+#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC_MASK 0xffff0000
+#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC__SHIFT 0x10
+#define PLL_DS_CNTL__PLL_DS_FRAC_MASK 0xffff
+#define PLL_DS_CNTL__PLL_DS_FRAC__SHIFT 0x0
+#define PLL_DS_CNTL__PLL_DS_ORDER_MASK 0x30000
+#define PLL_DS_CNTL__PLL_DS_ORDER__SHIFT 0x10
+#define PLL_DS_CNTL__PLL_DS_MODE_MASK 0x40000
+#define PLL_DS_CNTL__PLL_DS_MODE__SHIFT 0x12
+#define PLL_DS_CNTL__PLL_DS_PRBS_EN_MASK 0x80000
+#define PLL_DS_CNTL__PLL_DS_PRBS_EN__SHIFT 0x13
+#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN_MASK 0x1
+#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN__SHIFT 0x0
+#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN_MASK 0x2
+#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN__SHIFT 0x1
+#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN_MASK 0x4
+#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN__SHIFT 0x2
+#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN_MASK 0x8
+#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN__SHIFT 0x3
+#define PLL_IDCLK_CNTL__PLL_IDCLK_EN_MASK 0x10
+#define PLL_IDCLK_CNTL__PLL_IDCLK_EN__SHIFT 0x4
+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET_MASK 0x100
+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET__SHIFT 0x8
+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT_MASK 0x1000
+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT__SHIFT 0xc
+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_MASK 0xf0000
+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV__SHIFT 0x10
+#define PLL_IDCLK_CNTL__PLL_CUR_LTDP_MASK 0x300000
+#define PLL_IDCLK_CNTL__PLL_CUR_LTDP__SHIFT 0x14
+#define PLL_IDCLK_CNTL__PLL_CUR_PREDRV_MASK 0xc00000
+#define PLL_IDCLK_CNTL__PLL_CUR_PREDRV__SHIFT 0x16
+#define PLL_IDCLK_CNTL__PLL_CUR_TMDP_MASK 0x3000000
+#define PLL_IDCLK_CNTL__PLL_CUR_TMDP__SHIFT 0x18
+#define PLL_IDCLK_CNTL__PLL_CML_A_DRVSTR_MASK 0xc000000
+#define PLL_IDCLK_CNTL__PLL_CML_A_DRVSTR__SHIFT 0x1a
+#define PLL_IDCLK_CNTL__PLL_CML_B_DRVSTR_MASK 0x30000000
+#define PLL_IDCLK_CNTL__PLL_CML_B_DRVSTR__SHIFT 0x1c
+#define PLL_CNTL__PLL_RESET_MASK 0x1
+#define PLL_CNTL__PLL_RESET__SHIFT 0x0
+#define PLL_CNTL__PLL_POWER_DOWN_MASK 0x2
+#define PLL_CNTL__PLL_POWER_DOWN__SHIFT 0x1
+#define PLL_CNTL__PLL_BYPASS_CAL_MASK 0x4
+#define PLL_CNTL__PLL_BYPASS_CAL__SHIFT 0x2
+#define PLL_CNTL__PLL_POST_DIV_SRC_MASK 0x8
+#define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x3
+#define PLL_CNTL__PLL_VCOREF_MASK 0x30
+#define PLL_CNTL__PLL_VCOREF__SHIFT 0x4
+#define PLL_CNTL__PLL_PCIE_REFCLK_SEL_MASK 0x40
+#define PLL_CNTL__PLL_PCIE_REFCLK_SEL__SHIFT 0x6
+#define PLL_CNTL__PLL_ANTIGLITCH_RESETB_MASK 0x80
+#define PLL_CNTL__PLL_ANTIGLITCH_RESETB__SHIFT 0x7
+#define PLL_CNTL__PLL_CALREF_MASK 0x300
+#define PLL_CNTL__PLL_CALREF__SHIFT 0x8
+#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV_MASK 0x400
+#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV__SHIFT 0xa
+#define PLL_CNTL__PLL_REFCLK_SEL_MASK 0x1800
+#define PLL_CNTL__PLL_REFCLK_SEL__SHIFT 0xb
+#define PLL_CNTL__PLL_ANTI_GLITCH_RESET_MASK 0x2000
+#define PLL_CNTL__PLL_ANTI_GLITCH_RESET__SHIFT 0xd
+#define PLL_CNTL__PLL_XOCLK_DRV_R_EN_MASK 0x4000
+#define PLL_CNTL__PLL_XOCLK_DRV_R_EN__SHIFT 0xe
+#define PLL_CNTL__PLL_REF_DIV_SRC_MASK 0x70000
+#define PLL_CNTL__PLL_REF_DIV_SRC__SHIFT 0x10
+#define PLL_CNTL__PLL_LOCK_FREQ_SEL_MASK 0x80000
+#define PLL_CNTL__PLL_LOCK_FREQ_SEL__SHIFT 0x13
+#define PLL_CNTL__PLL_CALIB_DONE_MASK 0x100000
+#define PLL_CNTL__PLL_CALIB_DONE__SHIFT 0x14
+#define PLL_CNTL__PLL_LOCKED_MASK 0x200000
+#define PLL_CNTL__PLL_LOCKED__SHIFT 0x15
+#define PLL_CNTL__PLL_REFCLK_RECV_EN_MASK 0x400000
+#define PLL_CNTL__PLL_REFCLK_RECV_EN__SHIFT 0x16
+#define PLL_CNTL__PLL_REFCLK_RECV_SEL_MASK 0x800000
+#define PLL_CNTL__PLL_REFCLK_RECV_SEL__SHIFT 0x17
+#define PLL_CNTL__PLL_TIMING_MODE_STATUS_MASK 0x3000000
+#define PLL_CNTL__PLL_TIMING_MODE_STATUS__SHIFT 0x18
+#define PLL_CNTL__PLL_DIG_SPARE_MASK 0xfc000000
+#define PLL_CNTL__PLL_DIG_SPARE__SHIFT 0x1a
+#define PLL_ANALOG__PLL_CAL_MODE_MASK 0x1f
+#define PLL_ANALOG__PLL_CAL_MODE__SHIFT 0x0
+#define PLL_ANALOG__PLL_PFD_PULSE_SEL_MASK 0x60
+#define PLL_ANALOG__PLL_PFD_PULSE_SEL__SHIFT 0x5
+#define PLL_ANALOG__PLL_CP_MASK 0xf00
+#define PLL_ANALOG__PLL_CP__SHIFT 0x8
+#define PLL_ANALOG__PLL_LF_MODE_MASK 0x1ff000
+#define PLL_ANALOG__PLL_LF_MODE__SHIFT 0xc
+#define PLL_ANALOG__PLL_VREG_FB_TRIM_MASK 0xe00000
+#define PLL_ANALOG__PLL_VREG_FB_TRIM__SHIFT 0x15
+#define PLL_ANALOG__PLL_IBIAS_MASK 0xff000000
+#define PLL_ANALOG__PLL_IBIAS__SHIFT 0x18
+#define PLL_VREG_CNTL__PLL_VREG_CNTL_MASK 0xfffff
+#define PLL_VREG_CNTL__PLL_VREG_CNTL__SHIFT 0x0
+#define PLL_VREG_CNTL__PLL_BG_VREG_BIAS_MASK 0x300000
+#define PLL_VREG_CNTL__PLL_BG_VREG_BIAS__SHIFT 0x14
+#define PLL_VREG_CNTL__PLL_VREF_SEL_MASK 0x4000000
+#define PLL_VREG_CNTL__PLL_VREF_SEL__SHIFT 0x1a
+#define PLL_VREG_CNTL__PLL_VREG_BIAS_MASK 0xf0000000
+#define PLL_VREG_CNTL__PLL_VREG_BIAS__SHIFT 0x1c
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE_MASK 0x1
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE__SHIFT 0x0
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT_MASK 0x2
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT__SHIFT 0x1
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS_MASK 0x4
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS__SHIFT 0x2
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT_MASK 0x70
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT__SHIFT 0x4
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST_MASK 0x80
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST__SHIFT 0x7
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK_MASK 0x100
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK__SHIFT 0x8
+#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE_MASK 0x1
+#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE__SHIFT 0x0
+#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL_MASK 0xf0
+#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL__SHIFT 0x4
+#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL_MASK 0x1f00
+#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL__SHIFT 0x8
+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL_MASK 0xff0000
+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL__SHIFT 0x10
+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK_MASK 0x7000000
+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK__SHIFT 0x18
+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN_MASK 0x8000000
+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN__SHIFT 0x1b
+#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK_MASK 0x1
+#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK__SHIFT 0x0
+#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING_MASK 0x1
+#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING__SHIFT 0x0
+#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT_MASK 0x100
+#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT__SHIFT 0x8
+#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE_MASK 0x10000
+#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE__SHIFT 0x10
+#define PLL_XOR_LOCK__PLL_XOR_LOCK_MASK 0x1
+#define PLL_XOR_LOCK__PLL_XOR_LOCK__SHIFT 0x0
+#define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK_MASK 0x2
+#define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK__SHIFT 0x1
+#define PLL_XOR_LOCK__PLL_SPARE_MASK 0x3f00
+#define PLL_XOR_LOCK__PLL_SPARE__SHIFT 0x8
+#define PLL_XOR_LOCK__PLL_LOCK_COUNT_SEL_MASK 0xf0000
+#define PLL_XOR_LOCK__PLL_LOCK_COUNT_SEL__SHIFT 0x10
+#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FREF_MASK 0x700000
+#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FREF__SHIFT 0x14
+#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FFB_MASK 0x3800000
+#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FFB__SHIFT 0x17
+#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_OPAMP_BIAS_MASK 0xc000000
+#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_OPAMP_BIAS__SHIFT 0x1a
+#define PLL_XOR_LOCK__PLL_FAST_LOCK_MODE_EN_MASK 0x10000000
+#define PLL_XOR_LOCK__PLL_FAST_LOCK_MODE_EN__SHIFT 0x1c
+#define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN_MASK 0x1
+#define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN__SHIFT 0x0
+#define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL_MASK 0x1e
+#define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL__SHIFT 0x1
+#define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL_MASK 0x1e0
+#define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL__SHIFT 0x5
+#define PLL_ANALOG_CNTL__PLL_REGREF_TRIM_MASK 0x3e00
+#define PLL_ANALOG_CNTL__PLL_REGREF_TRIM__SHIFT 0x9
+#define PLL_ANALOG_CNTL__PLL_CALIB_FBDIV_MASK 0x1c000
+#define PLL_ANALOG_CNTL__PLL_CALIB_FBDIV__SHIFT 0xe
+#define PLL_ANALOG_CNTL__PLL_CALIB_FASTCAL_MASK 0x20000
+#define PLL_ANALOG_CNTL__PLL_CALIB_FASTCAL__SHIFT 0x11
+#define PLL_ANALOG_CNTL__PLL_TEST_SSAMP_EN_MASK 0x40000
+#define PLL_ANALOG_CNTL__PLL_TEST_SSAMP_EN__SHIFT 0x12
+#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV_MASK 0x3ff
+#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV__SHIFT 0x0
+#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV_MASK 0x3ff
+#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV__SHIFT 0x0
+#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV_MASK 0x3ff
+#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV__SHIFT 0x0
+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_MASK 0xf
+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION__SHIFT 0x0
+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30
+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_MASK 0x7ff0000
+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV__SHIFT 0x10
+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_MASK 0xf
+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION__SHIFT 0x0
+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30
+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_MASK 0x7ff0000
+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV__SHIFT 0x10
+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_MASK 0xf
+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION__SHIFT 0x0
+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30
+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_MASK 0x7ff0000
+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV__SHIFT 0x10
+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x7f
+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK__SHIFT 0x0
+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK_MASK 0x7f00
+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK__SHIFT 0x8
+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK_MASK 0x7f0000
+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK__SHIFT 0x10
+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK_MASK 0x7f
+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK__SHIFT 0x0
+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK_MASK 0x7f00
+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK__SHIFT 0x8
+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK_MASK 0x7f0000
+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK__SHIFT 0x10
+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK_MASK 0x7f
+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK__SHIFT 0x0
+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK_MASK 0x7f00
+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK__SHIFT 0x8
+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK_MASK 0x7f0000
+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK__SHIFT 0x10
+#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK 0x1f
+#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT 0x0
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL_MASK 0x60
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL__SHIFT 0x5
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK 0xf00
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP__SHIFT 0x8
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE_MASK 0x1ff000
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE__SHIFT 0xc
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS_MASK 0xff000000
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS__SHIFT 0x18
+#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE_MASK 0x1f
+#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE__SHIFT 0x0
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL_MASK 0x60
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL__SHIFT 0x5
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP_MASK 0xf00
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP__SHIFT 0x8
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE_MASK 0x1ff000
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE__SHIFT 0xc
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS_MASK 0xff000000
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS__SHIFT 0x18
+#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE_MASK 0x1f
+#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE__SHIFT 0x0
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL_MASK 0x60
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL__SHIFT 0x5
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP_MASK 0xf00
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP__SHIFT 0x8
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE_MASK 0x1ff000
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE__SHIFT 0xc
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS_MASK 0xff000000
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS__SHIFT 0x18
+#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK 0x1
+#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT 0x0
+#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ_MASK 0xf0
+#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ__SHIFT 0x4
+#define PPLL_DIV_UPDATE_DEBUG__PLL_REF_DIV_CHANGED_MASK 0x1
+#define PPLL_DIV_UPDATE_DEBUG__PLL_REF_DIV_CHANGED__SHIFT 0x0
+#define PPLL_DIV_UPDATE_DEBUG__PLL_FB_DIV_CHANGED_MASK 0x2
+#define PPLL_DIV_UPDATE_DEBUG__PLL_FB_DIV_CHANGED__SHIFT 0x1
+#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_PENDING_MASK 0x4
+#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_PENDING__SHIFT 0x2
+#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_CURRENT_STATE_MASK 0x18
+#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_CURRENT_STATE__SHIFT 0x3
+#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ENABLE_MASK 0x20
+#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ENABLE__SHIFT 0x5
+#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_REQ_MASK 0x40
+#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_REQ__SHIFT 0x6
+#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ACK_MASK 0x80
+#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ACK__SHIFT 0x7
+#define PPLL_STATUS_DEBUG__PLL_DEBUG_BUS_MASK 0xffff
+#define PPLL_STATUS_DEBUG__PLL_DEBUG_BUS__SHIFT 0x0
+#define PPLL_STATUS_DEBUG__PLL_UNLOCK_MASK 0x10000
+#define PPLL_STATUS_DEBUG__PLL_UNLOCK__SHIFT 0x10
+#define PPLL_STATUS_DEBUG__PLL_CAL_RESULT_MASK 0x1e0000
+#define PPLL_STATUS_DEBUG__PLL_CAL_RESULT__SHIFT 0x11
+#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_ISO_ENB_MASK 0x1000000
+#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_ISO_ENB__SHIFT 0x18
+#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_S_MASK 0x2000000
+#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_S__SHIFT 0x19
+#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_V_MASK 0x4000000
+#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_V__SHIFT 0x1a
+#define PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL_MASK 0x1f
+#define PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL__SHIFT 0x0
+#define PPLL_SPARE0__PLL_SPARE0_MASK 0xffffffff
+#define PPLL_SPARE0__PLL_SPARE0__SHIFT 0x0
+#define PPLL_SPARE1__PLL_SPARE1_MASK 0xffffffff
+#define PPLL_SPARE1__PLL_SPARE1__SHIFT 0x0
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0_MASK 0x7
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0__SHIFT 0x0
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1_MASK 0x70
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1__SHIFT 0x4
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2_MASK 0x700
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2__SHIFT 0x8
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3_MASK 0x7000
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3__SHIFT 0xc
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4_MASK 0x70000
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4__SHIFT 0x10
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0_MASK 0x300000
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0__SHIFT 0x14
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1_MASK 0xc00000
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1__SHIFT 0x16
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2_MASK 0x3000000
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2__SHIFT 0x18
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3_MASK 0xc000000
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3__SHIFT 0x1a
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4_MASK 0x30000000
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4__SHIFT 0x1c
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC_MASK 0x3
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC__SHIFT 0x0
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC_MASK 0x30
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC__SHIFT 0x4
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC_MASK 0x300
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC__SHIFT 0x8
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC_MASK 0x3000
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC__SHIFT 0xc
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC_MASK 0x30000
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC__SHIFT 0x10
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL_MASK 0x100000
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL__SHIFT 0x14
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL_MASK 0x600000
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL__SHIFT 0x15
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL_MASK 0x1800000
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL__SHIFT 0x17
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL_MASK 0x6000000
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL__SHIFT 0x19
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL_MASK 0x18000000
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL__SHIFT 0x1b
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL_MASK 0x60000000
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL__SHIFT 0x1d
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK_MASK 0x3
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK__SHIFT 0x0
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT_MASK 0xc
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT__SHIFT 0x2
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK_MASK 0xf0
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK__SHIFT 0x4
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT_MASK 0xf00
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT__SHIFT 0x8
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK_MASK 0xf000
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK__SHIFT 0xc
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT_MASK 0xf0000
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT__SHIFT 0x10
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0_MASK 0x100000
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0__SHIFT 0x14
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1_MASK 0x200000
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1__SHIFT 0x15
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2_MASK 0x400000
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2__SHIFT 0x16
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3_MASK 0x800000
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3__SHIFT 0x17
+#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ_MASK 0x1f000000
+#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ__SHIFT 0x18
+#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN_MASK 0x80000000
+#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN__SHIFT 0x1f
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK_MASK 0x1f
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK__SHIFT 0x0
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT_MASK 0x3e0
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT__SHIFT 0x5
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK_MASK 0x1f000
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT 0xc
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK 0x3e0000
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT 0x11
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK_MASK 0x7000000
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK__SHIFT 0x18
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT_MASK 0x70000000
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT__SHIFT 0x1c
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN_MASK 0x1
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN__SHIFT 0x0
+#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC_MASK 0x2
+#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC__SHIFT 0x1
+#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL_MASK 0xc
+#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL__SHIFT 0x2
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00_MASK 0xf00
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00__SHIFT 0x8
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25_MASK 0xf000
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25__SHIFT 0xc
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45_MASK 0xf0000
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45__SHIFT 0x10
+#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION_MASK 0xfffc
+#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION__SHIFT 0x2
+#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_MASK 0xfff0000
+#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV__SHIFT 0x10
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE_MASK 0x1
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE__SHIFT 0x0
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET_MASK 0x2
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET__SHIFT 0x1
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN_MASK 0x4
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN__SHIFT 0x2
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN_MASK 0x8
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN__SHIFT 0x3
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN_MASK 0xf0
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN__SHIFT 0x4
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL_MASK 0x7f00
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL__SHIFT 0x8
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL_MASK 0xff0000
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL__SHIFT 0x10
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC_MASK 0x1000000
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC__SHIFT 0x18
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN_MASK 0x2000000
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN__SHIFT 0x19
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN_MASK 0x4000000
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN__SHIFT 0x1a
+#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE_MASK 0x30000000
+#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE__SHIFT 0x1c
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE_MASK 0x3
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE__SHIFT 0x0
+#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL_MASK 0xc
+#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x2
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL_MASK 0x10
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL__SHIFT 0x4
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL_MASK 0x20
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL__SHIFT 0x5
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x40
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL__SHIFT 0x6
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC_MASK 0x700
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC__SHIFT 0x8
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN_MASK 0x800
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN__SHIFT 0xb
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN_MASK 0x1000
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN__SHIFT 0xc
+#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV_MASK 0x2000
+#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV__SHIFT 0xd
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL_MASK 0x10000
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL__SHIFT 0x10
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS_MASK 0x80000
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS__SHIFT 0x13
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL_MASK 0x100000
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL__SHIFT 0x14
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV_MASK 0x1f000000
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV__SHIFT 0x18
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL_MASK 0xe0000000
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL__SHIFT 0x1d
+#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE_MASK 0x3ffffff
+#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE__SHIFT 0x0
+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM_MASK 0xfff
+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM__SHIFT 0x0
+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN_MASK 0x1000
+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN__SHIFT 0xc
+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN_MASK 0x2000
+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN__SHIFT 0xd
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL_MASK 0x1
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL__SHIFT 0x0
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL_MASK 0x30
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL__SHIFT 0x4
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR_MASK 0x40
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR__SHIFT 0x6
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT_MASK 0x100
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT__SHIFT 0x8
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE_MASK 0x10000
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE__SHIFT 0x10
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL_MASK 0x1f
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x0
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_MASK 0x1e0
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL__SHIFT 0x5
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN_MASK 0x200
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN__SHIFT 0x9
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR_MASK 0x400
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR__SHIFT 0xa
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET_MASK 0x8000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET__SHIFT 0xf
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL_MASK 0x10000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL__SHIFT 0x10
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN_MASK 0x20000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN__SHIFT 0x11
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_MASK 0x1f00000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR__SHIFT 0x14
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC_MASK 0xe000000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC__SHIFT 0x19
+#define UNIPHY_REG_TEST_OUTPUT__OA_PLL_TEST_UNLOCK_RAW_MASK 0x10000000
+#define UNIPHY_REG_TEST_OUTPUT__OA_PLL_TEST_UNLOCK_RAW__SHIFT 0x1c
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET_MASK 0x20000000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET__SHIFT 0x1d
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY_MASK 0x40000000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY__SHIFT 0x1e
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK_MASK 0x80000000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK__SHIFT 0x1f
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN_MASK 0x1
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN__SHIFT 0x0
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET_MASK 0x2
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET__SHIFT 0x1
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS_MASK 0xf00
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS__SHIFT 0x8
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR_MASK 0x1f0000
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR__SHIFT 0x10
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB_MASK 0x1000000
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB__SHIFT 0x18
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN_MASK 0x2000000
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN__SHIFT 0x19
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT_MASK 0x4000000
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT__SHIFT 0x1a
+#define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX_MASK 0xffff
+#define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX__SHIFT 0x0
+#define UNIPHY_TMDP_REG0__ITXA_IMPCAL_EN_MASK 0x1
+#define UNIPHY_TMDP_REG0__ITXA_IMPCAL_EN__SHIFT 0x0
+#define UNIPHY_TMDP_REG0__ICALRA_MODE_MASK 0x2
+#define UNIPHY_TMDP_REG0__ICALRA_MODE__SHIFT 0x1
+#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_PG_MASK 0x7fc
+#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_PG__SHIFT 0x2
+#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_NG_MASK 0xff800
+#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_NG__SHIFT 0xb
+#define UNIPHY_TMDP_REG0__ITXA_TPC_SEL_MASK 0x100000
+#define UNIPHY_TMDP_REG0__ITXA_TPC_SEL__SHIFT 0x14
+#define UNIPHY_TMDP_REG0__ITXA_PCALEN_MASK 0x200000
+#define UNIPHY_TMDP_REG0__ITXA_PCALEN__SHIFT 0x15
+#define UNIPHY_TMDP_REG0__ITXA_DPPC_PWN_MASK 0x400000
+#define UNIPHY_TMDP_REG0__ITXA_DPPC_PWN__SHIFT 0x16
+#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_EN_MASK 0x800000
+#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_EN__SHIFT 0x17
+#define UNIPHY_TMDP_REG0__ITXA_TPC_CNTL_MASK 0x3000000
+#define UNIPHY_TMDP_REG0__ITXA_TPC_CNTL__SHIFT 0x18
+#define UNIPHY_TMDP_REG0__ITXA_VSCALEN_MASK 0x4000000
+#define UNIPHY_TMDP_REG0__ITXA_VSCALEN__SHIFT 0x1a
+#define UNIPHY_TMDP_REG0__ITXA_IOCNTL_TSTSEL_MASK 0x78000000
+#define UNIPHY_TMDP_REG0__ITXA_IOCNTL_TSTSEL__SHIFT 0x1b
+#define UNIPHY_TMDP_REG0__ITXA_IMPVSCALEN_MASK 0x80000000
+#define UNIPHY_TMDP_REG0__ITXA_IMPVSCALEN__SHIFT 0x1f
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_TST_MASK 0x1f
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_TST__SHIFT 0x0
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL100_ADJ_MASK 0x1e0
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL100_ADJ__SHIFT 0x5
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL50_ADJ_MASK 0x1e00
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL50_ADJ__SHIFT 0x9
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_ADJ_MASK 0x1e000
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_ADJ__SHIFT 0xd
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_PDN_MASK 0x20000
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_PDN__SHIFT 0x11
+#define UNIPHY_TMDP_REG1__ITXA_IOCNTL_MASK 0xffc0000
+#define UNIPHY_TMDP_REG1__ITXA_IOCNTL__SHIFT 0x12
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_PLLREFSEL_MASK 0x10000000
+#define UNIPHY_TMDP_REG1__ITXA_BIAS_PLLREFSEL__SHIFT 0x1c
+#define UNIPHY_TMDP_REG1__ITX_EDPSEL_MASK 0xe0000000
+#define UNIPHY_TMDP_REG1__ITX_EDPSEL__SHIFT 0x1d
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_PDN_MASK 0x1
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_PDN__SHIFT 0x0
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_EN_MASK 0x2
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_EN__SHIFT 0x1
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_MASK 0x3c
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET__SHIFT 0x2
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_EN_MASK 0x40
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_EN__SHIFT 0x6
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_MASK 0x3f80
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE__SHIFT 0x7
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_SET_MASK 0x4000
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_SET__SHIFT 0xe
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_PDN_MASK 0x10000
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_PDN__SHIFT 0x10
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_EN_MASK 0x20000
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_EN__SHIFT 0x11
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_MASK 0x3c0000
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET__SHIFT 0x12
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_EN_MASK 0x400000
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_EN__SHIFT 0x16
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_MASK 0x3f800000
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE__SHIFT 0x17
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_SET_MASK 0x40000000
+#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_SET__SHIFT 0x1e
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_PDN_MASK 0x1
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_PDN__SHIFT 0x0
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_EN_MASK 0x2
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_EN__SHIFT 0x1
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_MASK 0x3c
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET__SHIFT 0x2
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_EN_MASK 0x40
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_EN__SHIFT 0x6
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_MASK 0x3f80
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE__SHIFT 0x7
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_SET_MASK 0x4000
+#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_SET__SHIFT 0xe
+#define UNIPHY_TMDP_REG3__ITXA_PREM_ADJ_MASK 0xf8000
+#define UNIPHY_TMDP_REG3__ITXA_PREM_ADJ__SHIFT 0xf
+#define UNIPHY_TMDP_REG3__OTXA_RES_NCAL_MASK 0x1f00000
+#define UNIPHY_TMDP_REG3__OTXA_RES_NCAL__SHIFT 0x14
+#define UNIPHY_TMDP_REG3__OTXA_RES_PCAL_MASK 0x3e000000
+#define UNIPHY_TMDP_REG3__OTXA_RES_PCAL__SHIFT 0x19
+#define UNIPHY_TMDP_REG4__RESERVED_MASK 0x3fffff
+#define UNIPHY_TMDP_REG4__RESERVED__SHIFT 0x0
+#define UNIPHY_TMDP_REG4__OTXA_IOCNTL_NF_MASK 0x7fc00000
+#define UNIPHY_TMDP_REG4__OTXA_IOCNTL_NF__SHIFT 0x16
+#define UNIPHY_TMDP_REG5__OTXA0_IOFSM_TIMEOUT_MASK 0x1
+#define UNIPHY_TMDP_REG5__OTXA0_IOFSM_TIMEOUT__SHIFT 0x0
+#define UNIPHY_TMDP_REG5__OTXA0_RESCAL_DONE_MASK 0x2
+#define UNIPHY_TMDP_REG5__OTXA0_RESCAL_DONE__SHIFT 0x1
+#define UNIPHY_TMDP_REG5__OTXA1_IOFSM_TIMEOUT_MASK 0x4
+#define UNIPHY_TMDP_REG5__OTXA1_IOFSM_TIMEOUT__SHIFT 0x2
+#define UNIPHY_TMDP_REG5__OTXA1_RESCAL_DONE_MASK 0x8
+#define UNIPHY_TMDP_REG5__OTXA1_RESCAL_DONE__SHIFT 0x3
+#define UNIPHY_TMDP_REG5__OTXA2_IOFSM_TIMEOUT_MASK 0x10
+#define UNIPHY_TMDP_REG5__OTXA2_IOFSM_TIMEOUT__SHIFT 0x4
+#define UNIPHY_TMDP_REG5__OTXA2_RESCAL_DONE_MASK 0x20
+#define UNIPHY_TMDP_REG5__OTXA2_RESCAL_DONE__SHIFT 0x5
+#define UNIPHY_TMDP_REG5__OTXA3_IOFSM_TIMEOUT_MASK 0x40
+#define UNIPHY_TMDP_REG5__OTXA3_IOFSM_TIMEOUT__SHIFT 0x6
+#define UNIPHY_TMDP_REG5__OTXA3_RESCAL_DONE_MASK 0x80
+#define UNIPHY_TMDP_REG5__OTXA3_RESCAL_DONE__SHIFT 0x7
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_MASK 0x1ff00
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALN__SHIFT 0x8
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_DONE_MASK 0x20000
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_DONE__SHIFT 0x11
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_ERROR_MASK 0x40000
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_ERROR__SHIFT 0x12
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_MASK 0x780000
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALP__SHIFT 0x13
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_DONE_MASK 0x800000
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_DONE__SHIFT 0x17
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_ERROR_MASK 0x1000000
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_ERROR__SHIFT 0x18
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_MASK 0x3e000000
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS__SHIFT 0x19
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_DONE_MASK 0x40000000
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_DONE__SHIFT 0x1e
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_ERROR_MASK 0x80000000
+#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_ERROR__SHIFT 0x1f
+#define UNIPHY_TMDP_REG6__IRXA_OS_ADJ_MASK 0x1
+#define UNIPHY_TMDP_REG6__IRXA_OS_ADJ__SHIFT 0x0
+#define UNIPHY_TMDP_REG6__IRXA_OS_POLB_MASK 0x2
+#define UNIPHY_TMDP_REG6__IRXA_OS_POLB__SHIFT 0x1
+#define UNIPHY_TMDP_REG6__IRXA_BIST_SEL_MASK 0x4
+#define UNIPHY_TMDP_REG6__IRXA_BIST_SEL__SHIFT 0x2
+#define UNIPHY_TMDP_REG6__IRXA_SENADJ_MASK 0x78
+#define UNIPHY_TMDP_REG6__IRXA_SENADJ__SHIFT 0x3
+#define UNIPHY_TMDP_REG6__IRXA_CPSEL_MASK 0x780
+#define UNIPHY_TMDP_REG6__IRXA_CPSEL__SHIFT 0x7
+#define UNIPHY_TMDP_REG6__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x800
+#define UNIPHY_TMDP_REG6__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0xb
+#define UNIPHY_TPG_CONTROL__UNIPHY_STATIC_TEST_PATTERN_MASK 0x3ff
+#define UNIPHY_TPG_CONTROL__UNIPHY_STATIC_TEST_PATTERN__SHIFT 0x0
+#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_EN_MASK 0x10000
+#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_EN__SHIFT 0x10
+#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_SEL_MASK 0xe0000
+#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_SEL__SHIFT 0x11
+#define UNIPHY_TPG_SEED__UNIPHY_TPG_SEED_MASK 0x7fffff
+#define UNIPHY_TPG_SEED__UNIPHY_TPG_SEED__SHIFT 0x0
+#define UNIPHY_DEBUG__DEBUG0_MASK 0x3ff000
+#define UNIPHY_DEBUG__DEBUG0__SHIFT 0xc
+#define UNIPHY_DEBUG__DEBUG1_MASK 0x1c00000
+#define UNIPHY_DEBUG__DEBUG1__SHIFT 0x16
+#define UNIPHY_DEBUG__DBG_SEL_MASK 0x6000000
+#define UNIPHY_DEBUG__DBG_SEL__SHIFT 0x19
+#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff
+#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000
+#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff
+#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000
+#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3
+#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300
+#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000
+#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
+#define DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x1000000
+#define DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18
+#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff
+#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000
+#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1
+#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
+#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7
+#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70
+#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff
+#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0
+#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff
+#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0
+#define DPG_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK 0x1
+#define DPG_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT 0x0
+#define DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x1
+#define DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
+#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0xff
+#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x0
+#define DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff
+#define DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+#define DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000
+#define DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+#define DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff
+#define DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+#define DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000
+#define DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+#define DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff
+#define DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+#define DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000
+#define DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+#define DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff
+#define DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+#define DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000
+#define DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+#define DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3
+#define DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+#define DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300
+#define DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+#define DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000
+#define DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
+#define DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x1000000
+#define DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18
+#define DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3
+#define DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+#define DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300
+#define DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+#define DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000
+#define DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
+#define DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x1000000
+#define DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18
+#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff
+#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000
+#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff
+#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000
+#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+#define DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1
+#define DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
+#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10
+#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4
+#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100
+#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8
+#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000
+#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc
+#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000
+#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10
+#define DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1
+#define DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
+#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10
+#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4
+#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100
+#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8
+#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000
+#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc
+#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000
+#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10
+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1
+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10
+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20
+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40
+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80
+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100
+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200
+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400
+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800
+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000
+#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1
+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10
+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20
+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40
+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80
+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100
+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200
+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400
+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800
+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000
+#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1
+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10
+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100
+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200
+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400
+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000
+#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1
+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10
+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100
+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200
+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400
+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000
+#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1
+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10
+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20
+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40
+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80
+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100
+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200
+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400
+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800
+#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1
+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10
+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20
+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40
+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80
+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100
+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200
+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400
+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800
+#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
+#define DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7
+#define DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+#define DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70
+#define DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+#define DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7
+#define DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+#define DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70
+#define DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+#define DPGV0_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff
+#define DPGV0_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0
+#define DPGV1_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff
+#define DPGV1_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0
+#define DPGV0_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff
+#define DPGV0_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0
+#define DPGV1_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff
+#define DPGV1_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0
+#define DPGV0_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK 0x1
+#define DPGV0_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT 0x0
+#define DPGV1_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK 0x1
+#define DPGV1_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT 0x0
+#define DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x1
+#define DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
+#define DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x1
+#define DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0
+#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0xff
+#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DPGV_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DPGV_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x0
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0xff
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0xff
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0xff
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x7
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x70
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x3f
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x7
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x7
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
+#define AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON_MASK 0x3f
+#define AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON__SHIFT 0x0
+#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK 0xffffffc0
+#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT 0x6
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xffffffff
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xffffffff
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xffffffff
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xffffffff
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xffffffff
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xffffffff
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xffffffff
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0
+#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x1
+#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0
+#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6
+#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1
+#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0xf8
+#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3
+#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0xf00
+#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8
+#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xf000
+#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc
+#define MINOR_VERSION__MINOR_VERSION_MASK 0xff
+#define MINOR_VERSION__MINOR_VERSION__SHIFT 0x0
+#define MAJOR_VERSION__MAJOR_VERSION_MASK 0xff
+#define MAJOR_VERSION__MAJOR_VERSION__SHIFT 0x0
+#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff
+#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
+#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff
+#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
+#define GLOBAL_CONTROL__CONTROLLER_RESET_MASK 0x1
+#define GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT 0x0
+#define GLOBAL_CONTROL__FLUSH_CONTROL_MASK 0x2
+#define GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT 0x1
+#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK 0x100
+#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT 0x8
+#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK 0x1
+#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT 0x0
+#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK 0x1
+#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT 0x0
+#define GLOBAL_STATUS__FLUSH_STATUS_MASK 0x2
+#define GLOBAL_STATUS__FLUSH_STATUS__SHIFT 0x1
+#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff
+#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x0
+#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xffff
+#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x0
+#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK 0x1
+#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT 0x0
+#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK 0x2
+#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT 0x1
+#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK 0x4
+#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT 0x2
+#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK 0x8
+#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT 0x3
+#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK 0x10
+#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT 0x4
+#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK 0x20
+#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT 0x5
+#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK 0x40
+#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT 0x6
+#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK 0x80
+#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT 0x7
+#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK 0x100
+#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT 0x8
+#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK 0x200
+#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT 0x9
+#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK 0x400
+#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT 0xa
+#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK 0x800
+#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT 0xb
+#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK 0x1000
+#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT 0xc
+#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK 0x2000
+#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT 0xd
+#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK 0x4000
+#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT 0xe
+#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK 0x8000
+#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT 0xf
+#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000
+#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT 0x1e
+#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK 0x80000000
+#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT 0x1f
+#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK 0x1
+#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT 0x0
+#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK 0x2
+#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT 0x1
+#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK 0x4
+#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT 0x2
+#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK 0x8
+#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT 0x3
+#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK 0x10
+#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT 0x4
+#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK 0x20
+#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT 0x5
+#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK 0x40
+#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT 0x6
+#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK 0x80
+#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT 0x7
+#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK 0x100
+#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT 0x8
+#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK 0x200
+#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT 0x9
+#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK 0x400
+#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT 0xa
+#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK 0x800
+#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT 0xb
+#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK 0x1000
+#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT 0xc
+#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK 0x2000
+#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT 0xd
+#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK 0x4000
+#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT 0xe
+#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK 0x8000
+#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT 0xf
+#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK 0x40000000
+#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT 0x1e
+#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK 0x80000000
+#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT 0x1f
+#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK 0xffffffff
+#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT 0x0
+#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK 0x1
+#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT 0x0
+#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK 0x2
+#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT 0x1
+#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK 0x4
+#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT 0x2
+#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK 0x8
+#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT 0x3
+#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK 0x10
+#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT 0x4
+#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK 0x20
+#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT 0x5
+#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION_MASK 0x40
+#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION__SHIFT 0x6
+#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION_MASK 0x80
+#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION__SHIFT 0x7
+#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION_MASK 0x100
+#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION__SHIFT 0x8
+#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION_MASK 0x200
+#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION__SHIFT 0x9
+#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION_MASK 0x400
+#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT 0xa
+#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION_MASK 0x800
+#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION__SHIFT 0xb
+#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION_MASK 0x1000
+#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION__SHIFT 0xc
+#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION_MASK 0x2000
+#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION__SHIFT 0xd
+#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION_MASK 0x4000
+#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION__SHIFT 0xe
+#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION_MASK 0x8000
+#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION__SHIFT 0xf
+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f
+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK 0xffffff80
+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK 0xffffffff
+#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0xff
+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0
+#define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0xff
+#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0
+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000
+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf
+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x1
+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0
+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x2
+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1
+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x1
+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0
+#define CORB_SIZE__CORB_SIZE_MASK 0x3
+#define CORB_SIZE__CORB_SIZE__SHIFT 0x0
+#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0xf0
+#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xffffff80
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xffffffff
+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0xff
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf
+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0xff
+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0
+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x1
+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0
+#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2
+#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1
+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x4
+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2
+#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x1
+#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0
+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x4
+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2
+#define RIRB_SIZE__RIRB_SIZE_MASK 0x3
+#define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0
+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0xf0
+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0xfffffff
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xf0000000
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xffffffff
+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x1
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x2
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x1
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7e
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xffffff80
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xffffffff
+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xffffffff
+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x1
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x2
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x4
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x8
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x10
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x30000
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x40000
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0xf00000
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x4000000
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x8000000
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xffffffff
+#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xffffffff
+#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0xff
+#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xffff
+#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x70
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x7f
+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xffffff80
+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xffffffff
+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xffffffff
+#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x8000
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x7f
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x80
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x7f
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x100
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x200
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0xfc00
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x78
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x80
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x78
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0xff
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0xffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0xffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0xff
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0
+#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0xff
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0xff00
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0xff0000
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x1
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x10
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0xffff
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xffff0000
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x300
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8
+#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK 0x30
+#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT 0x4
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xffffffff
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x3
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0xc
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x30
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0xc0
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x10000
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x20000
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x3
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0xc
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x30
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0xc0
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x1
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x10
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x1e0
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x1
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x10
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xffffffff
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x1
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff0000
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0xff
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x100
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0xff0000
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xffff0000
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10
+#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK 0xffffffff
+#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT 0x0
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x3
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x4
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x18
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x20
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0xc0
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x100
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x600
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x800
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x3000
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x4000
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x18000
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x20000
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0xc0000
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x100000
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x3
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0xc
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x30
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0xc0
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x300
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0xc00
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x3000
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc
+#define DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN_MASK 0x1
+#define DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x1
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x10
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x700
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xffffffff
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0xffff
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x1
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x700
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xffffffff
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xffffffff
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xffffffff
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xffffffff
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xffffffff
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xffffffff
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xffffffff
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xffffffff
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xffffffff
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x1
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x10
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x700
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xffffffff
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0xffff
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x1
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x700
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xffffffff
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xffffffff
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xffffffff
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xffffffff
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xffffffff
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xffffffff
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xffffffff
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xffffffff
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xffffffff
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0
+#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x1
+#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x10
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x1
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
+#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xffffffff
+#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0
+#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x1
+#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x10
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x1
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
+#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xffffffff
+#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0
+#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK 0xff
+#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT 0x0
+#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK 0xffffffff
+#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT 0x0
+#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0xff
+#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x100
+#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xffffffff
+#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x7f
+#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x7f00
+#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0xff0000
+#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x1
+#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xffffffff
+#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xffffffff
+#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xffffffff
+#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xffffffff
+#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0
+#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x3fff
+#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xffffffff
+#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3
+#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000
+#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x4
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG_MASK 0xffffffff
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xffffffff
+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xffffffff
+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xffffffff
+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40
+#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x7f
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x10000
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x20000
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0xfc0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x3000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x100
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x200
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x10000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x20000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf00000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x2
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x100
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x200
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0xf000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x10000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x20000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf00000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0xffff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xffff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0xff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xffffffff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xffffffff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0xff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xff000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0xff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xff000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0xff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xff000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0xff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xff000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0xff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff
+#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff
+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff
+#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0xff
+#define AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x2
+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x3
+#define AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4
+#define AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x1
+#define AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0
+#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x1
+#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0
+#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x10
+#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4
+#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x100
+#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8
+#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x1
+#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0
+#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x10
+#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4
+#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x100
+#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8
+#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x1
+#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0
+#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x10
+#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4
+#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x100
+#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8
+#define AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x3fff
+#define AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xffffffff
+#define AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xffffffff
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
+#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
+#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x20
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x2
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x100
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x200
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x10000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x20000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0xf00000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x2
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x100
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x200
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x10000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x20000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0xf00000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x6
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x10
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x20
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x7
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0xff00
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0xff0000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff
+#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x20
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x20
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0xff00
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0xff0000
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xffffffff
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xffffffff
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0
+#define BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0xff
+#define BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
+#define BLND_CONTROL__BLND_MODE_MASK 0x300
+#define BLND_CONTROL__BLND_MODE__SHIFT 0x8
+#define BLND_CONTROL__BLND_STEREO_TYPE_MASK 0xc00
+#define BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
+#define BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x1000
+#define BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
+#define BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x2000
+#define BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
+#define BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x30000
+#define BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
+#define BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x100000
+#define BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
+#define BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xff000000
+#define BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
+#define BLND_SM_CONTROL2__SM_MODE_MASK 0x7
+#define BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0
+#define BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x10
+#define BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
+#define BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x20
+#define BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
+#define BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x300
+#define BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+#define BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x30000
+#define BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+#define BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x1000000
+#define BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
+#define BLND_CONTROL2__PTI_ENABLE_MASK 0x1
+#define BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0
+#define BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x30
+#define BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
+#define BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x40
+#define BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
+#define BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x80
+#define BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
+#define BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x100
+#define BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
+#define BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x1
+#define BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
+#define BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x100
+#define BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
+#define BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x10000
+#define BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x1
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x100
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x1000
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x30000
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
+#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x1
+#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
+#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x2
+#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
+#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x10000
+#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
+#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK 0x1000000
+#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT 0x18
+#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000
+#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
+#define BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000
+#define BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
+#define BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000
+#define BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x1
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x2
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x4
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x8
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x40
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x80
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
+#define BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x100
+#define BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
+#define BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x200
+#define BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
+#define BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x400
+#define BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
+#define BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x800
+#define BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
+#define BLND_DEBUG__BLND_CNV_MUX_SELECT_MASK 0x1
+#define BLND_DEBUG__BLND_CNV_MUX_SELECT__SHIFT 0x0
+#define BLND_DEBUG__BLND_DEBUG_MASK 0xfffffffe
+#define BLND_DEBUG__BLND_DEBUG__SHIFT 0x1
+#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK 0xff
+#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT 0x0
+#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK 0xffffffff
+#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT 0x0
+#define WB_ENABLE__WB_ENABLE_MASK 0x1
+#define WB_ENABLE__WB_ENABLE__SHIFT 0x0
+#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS_MASK 0x1
+#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS__SHIFT 0x0
+#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS_MASK 0x2
+#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS__SHIFT 0x1
+#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS_MASK 0x4
+#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS__SHIFT 0x2
+#define WB_EC_CONFIG__WB_LB_LS_DIS_MASK 0x40
+#define WB_EC_CONFIG__WB_LB_LS_DIS__SHIFT 0x6
+#define WB_EC_CONFIG__WB_LB_SD_DIS_MASK 0x80
+#define WB_EC_CONFIG__WB_LB_SD_DIS__SHIFT 0x7
+#define WB_EC_CONFIG__WB_LUT_LS_DIS_MASK 0x100
+#define WB_EC_CONFIG__WB_LUT_LS_DIS__SHIFT 0x8
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK 0x600
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL__SHIFT 0x9
+#define WB_EC_CONFIG__WB_TEST_CLK_SEL_MASK 0xf000
+#define WB_EC_CONFIG__WB_TEST_CLK_SEL__SHIFT 0xc
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS_MASK 0x10000
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS__SHIFT 0x10
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE_MASK 0x60000
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE__SHIFT 0x11
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_MASK 0x180000
+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE__SHIFT 0x13
+#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE_MASK 0x800000
+#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE__SHIFT 0x17
+#define WB_EC_CONFIG__LB_MEM_PWR_STATE_MASK 0x30000000
+#define WB_EC_CONFIG__LB_MEM_PWR_STATE__SHIFT 0x1c
+#define WB_EC_CONFIG__LUT_MEM_PWR_STATE_MASK 0xc0000000
+#define WB_EC_CONFIG__LUT_MEM_PWR_STATE__SHIFT 0x1e
+#define CNV_MODE__CNV_FRAME_CAPTURE_RATE_MASK 0x300
+#define CNV_MODE__CNV_FRAME_CAPTURE_RATE__SHIFT 0x8
+#define CNV_MODE__CNV_WINDOW_CROP_EN_MASK 0x1000
+#define CNV_MODE__CNV_WINDOW_CROP_EN__SHIFT 0xc
+#define CNV_MODE__CNV_STEREO_TYPE_MASK 0x6000
+#define CNV_MODE__CNV_STEREO_TYPE__SHIFT 0xd
+#define CNV_MODE__CNV_INTERLACED_MODE_MASK 0x8000
+#define CNV_MODE__CNV_INTERLACED_MODE__SHIFT 0xf
+#define CNV_MODE__CNV_EYE_SELECTION_MASK 0x30000
+#define CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10
+#define CNV_MODE__CNV_STEREO_POLARITY_MASK 0x40000
+#define CNV_MODE__CNV_STEREO_POLARITY__SHIFT 0x12
+#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER_MASK 0x80000
+#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER__SHIFT 0x13
+#define CNV_MODE__CNV_STEREO_SPLIT_MASK 0x100000
+#define CNV_MODE__CNV_STEREO_SPLIT__SHIFT 0x14
+#define CNV_MODE__CNV_NEW_CONTENT_MASK 0x1000000
+#define CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18
+#define CNV_MODE__CNV_FRAME_CAPTURE_EN_MASK 0x80000000
+#define CNV_MODE__CNV_FRAME_CAPTURE_EN__SHIFT 0x1f
+#define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0xfff
+#define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0
+#define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0xfff0000
+#define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10
+#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0xfff
+#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0
+#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0xfff0000
+#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10
+#define CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x1
+#define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0
+#define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x100
+#define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8
+#define CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x10000
+#define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10
+#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x7fff
+#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0
+#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7fff0000
+#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10
+#define CNV_CSC_CONTROL__CNV_CSC_BYPASS_MASK 0x1
+#define CNV_CSC_CONTROL__CNV_CSC_BYPASS__SHIFT 0x0
+#define CNV_CSC_C11_C12__CNV_CSC_C11_MASK 0x1fff
+#define CNV_CSC_C11_C12__CNV_CSC_C11__SHIFT 0x0
+#define CNV_CSC_C11_C12__CNV_CSC_C12_MASK 0x1fff0000
+#define CNV_CSC_C11_C12__CNV_CSC_C12__SHIFT 0x10
+#define CNV_CSC_C13_C14__CNV_CSC_C13_MASK 0x1fff
+#define CNV_CSC_C13_C14__CNV_CSC_C13__SHIFT 0x0
+#define CNV_CSC_C13_C14__CNV_CSC_C14_MASK 0x7fff0000
+#define CNV_CSC_C13_C14__CNV_CSC_C14__SHIFT 0x10
+#define CNV_CSC_C21_C22__CNV_CSC_C21_MASK 0x1fff
+#define CNV_CSC_C21_C22__CNV_CSC_C21__SHIFT 0x0
+#define CNV_CSC_C21_C22__CNV_CSC_C22_MASK 0x1fff0000
+#define CNV_CSC_C21_C22__CNV_CSC_C22__SHIFT 0x10
+#define CNV_CSC_C23_C24__CNV_CSC_C23_MASK 0x1fff
+#define CNV_CSC_C23_C24__CNV_CSC_C23__SHIFT 0x0
+#define CNV_CSC_C23_C24__CNV_CSC_C24_MASK 0x7fff0000
+#define CNV_CSC_C23_C24__CNV_CSC_C24__SHIFT 0x10
+#define CNV_CSC_C31_C32__CNV_CSC_C31_MASK 0x1fff
+#define CNV_CSC_C31_C32__CNV_CSC_C31__SHIFT 0x0
+#define CNV_CSC_C31_C32__CNV_CSC_C32_MASK 0x1fff0000
+#define CNV_CSC_C31_C32__CNV_CSC_C32__SHIFT 0x10
+#define CNV_CSC_C33_C34__CNV_CSC_C33_MASK 0x1fff
+#define CNV_CSC_C33_C34__CNV_CSC_C33__SHIFT 0x0
+#define CNV_CSC_C33_C34__CNV_CSC_C34_MASK 0x7fff0000
+#define CNV_CSC_C33_C34__CNV_CSC_C34__SHIFT 0x10
+#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R_MASK 0xffff
+#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R__SHIFT 0x0
+#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G_MASK 0xffff
+#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G__SHIFT 0x0
+#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B_MASK 0xffff
+#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B__SHIFT 0x0
+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R_MASK 0xffff
+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R__SHIFT 0x0
+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R_MASK 0xffff0000
+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R__SHIFT 0x10
+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G_MASK 0xffff
+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G__SHIFT 0x0
+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G_MASK 0xffff0000
+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G__SHIFT 0x10
+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B_MASK 0xffff
+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B__SHIFT 0x0
+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B_MASK 0xffff0000
+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B__SHIFT 0x10
+#define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x10
+#define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4
+#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x100
+#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8
+#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY_MASK 0x10000
+#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY__SHIFT 0x10
+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0xfff0
+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x4
+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xffff0000
+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10
+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0xfff0
+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x4
+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xffff0000
+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10
+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0xfff0
+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x4
+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xffff0000
+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10
+#define WB_DEBUG_CTRL__WB_DEBUG_EN_MASK 0x1
+#define WB_DEBUG_CTRL__WB_DEBUG_EN__SHIFT 0x0
+#define WB_DEBUG_CTRL__WB_DEBUG_SEL_MASK 0xc0
+#define WB_DEBUG_CTRL__WB_DEBUG_SEL__SHIFT 0x6
+#define WB_DBG_MODE__WB_DBG_MODE_EN_MASK 0x1
+#define WB_DBG_MODE__WB_DBG_MODE_EN__SHIFT 0x0
+#define WB_DBG_MODE__WB_DBG_DIN_FMT_MASK 0x2
+#define WB_DBG_MODE__WB_DBG_DIN_FMT__SHIFT 0x1
+#define WB_DBG_MODE__WB_DBG_36MODE_MASK 0x4
+#define WB_DBG_MODE__WB_DBG_36MODE__SHIFT 0x2
+#define WB_DBG_MODE__WB_DBG_CMAP_MASK 0x8
+#define WB_DBG_MODE__WB_DBG_CMAP__SHIFT 0x3
+#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR_MASK 0x100
+#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR__SHIFT 0x8
+#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH_MASK 0x7fff0000
+#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH__SHIFT 0x10
+#define WB_HW_DEBUG__WB_HW_DEBUG_MASK 0xffffffff
+#define WB_HW_DEBUG__WB_HW_DEBUG__SHIFT 0x0
+#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT_MASK 0x3
+#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT__SHIFT 0x0
+#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT_MASK 0x1c
+#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT__SHIFT 0x2
+#define WB_SOFT_RESET__WB_SOFT_RESET_MASK 0x1
+#define WB_SOFT_RESET__WB_SOFT_RESET__SHIFT 0x0
+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX_MASK 0xff
+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX__SHIFT 0x0
+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA_MASK 0xffffffff
+#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA__SHIFT 0x0
+#define DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x10
+#define DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
+#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x100
+#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
+#define DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x1000
+#define DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
+#define DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x8000
+#define DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf
+#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_LOW_POWER_GATE_DISABLE_MASK 0x20000
+#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_LOW_POWER_GATE_DISABLE__SHIFT 0x11
+#define DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1f000000
+#define DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18
+#define DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000
+#define DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f
+#define DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x1
+#define DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0
+#define DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x2
+#define DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1
+#define DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x4
+#define DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2
+#define DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x8
+#define DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3
+#define DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x10
+#define DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
+#define DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x20
+#define DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5
+#define DCFE_SOFT_RESET__DCP_LOW_POWER_SOFT_RESET_MASK 0x40
+#define DCFE_SOFT_RESET__DCP_LOW_POWER_SOFT_RESET__SHIFT 0x6
+#define DCFE_DBG_CONFIG__DCFE_DBG_EN_MASK 0x1
+#define DCFE_DBG_CONFIG__DCFE_DBG_EN__SHIFT 0x0
+#define DCFE_DBG_CONFIG__DCFE_DBG_SEL_MASK 0xf0
+#define DCFE_DBG_CONFIG__DCFE_DBG_SEL__SHIFT 0x4
+#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x3
+#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0
+#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x4
+#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2
+#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x18
+#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3
+#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x20
+#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5
+#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0xc0
+#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6
+#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x100
+#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8
+#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x600
+#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9
+#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x800
+#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb
+#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x3000
+#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc
+#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x4000
+#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe
+#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x18000
+#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf
+#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x20000
+#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11
+#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0xc0000
+#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12
+#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x100000
+#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14
+#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x600000
+#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15
+#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x800000
+#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17
+#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x3000000
+#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18
+#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x4000000
+#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a
+#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000
+#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b
+#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000
+#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d
+#define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x3
+#define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0
+#define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0xc
+#define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
+#define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x30
+#define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0xc0
+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6
+#define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x300
+#define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8
+#define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0xc00
+#define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa
+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x3000
+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc
+#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0xc000
+#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe
+#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x30000
+#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10
+#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x40000
+#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12
+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x600000
+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15
+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x800000
+#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17
+#define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x3
+#define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0
+#define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0xc
+#define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2
+#define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x30
+#define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4
+#define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0xc0
+#define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6
+#define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x300
+#define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8
+#define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0xc00
+#define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa
+#define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x3000
+#define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc
+#define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0xc000
+#define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe
+#define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x30000
+#define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10
+#define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0xc0000
+#define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12
+#define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x300000
+#define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14
+#define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0xc00000
+#define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16
+#define DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x1
+#define DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
+#define DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE_MASK 0x8
+#define DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE__SHIFT 0x3
+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE_MASK 0x80
+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE__SHIFT 0x7
+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE_MASK 0x200
+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE__SHIFT 0x9
+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE_MASK 0x800
+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE__SHIFT 0xb
+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE_MASK 0x2000
+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE__SHIFT 0xd
+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE_MASK 0x8000
+#define DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE__SHIFT 0xf
+#define DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL_MASK 0x1f000000
+#define DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL__SHIFT 0x18
+#define DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE_MASK 0x80000000
+#define DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE__SHIFT 0x1f
+#define DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET_MASK 0x1
+#define DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET__SHIFT 0x0
+#define DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET_MASK 0x2
+#define DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET__SHIFT 0x1
+#define DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET_MASK 0x4
+#define DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET__SHIFT 0x2
+#define DCFEV_SOFT_RESET__SCLV_SOFT_RESET_MASK 0x8
+#define DCFEV_SOFT_RESET__SCLV_SOFT_RESET__SHIFT 0x3
+#define DCFEV_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x10
+#define DCFEV_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4
+#define DCFEV_SOFT_RESET__PSCLV_SOFT_RESET_MASK 0x20
+#define DCFEV_SOFT_RESET__PSCLV_SOFT_RESET__SHIFT 0x5
+#define DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET_MASK 0x40
+#define DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET__SHIFT 0x6
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS_MASK 0x8
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x3
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS_MASK 0x10
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS__SHIFT 0x4
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS_MASK 0x20
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS__SHIFT 0x5
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET_MASK 0x40
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET__SHIFT 0x6
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL_MASK 0x1f000000
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL__SHIFT 0x18
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE_MASK 0x80000000
+#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE__SHIFT 0x1f
+#define DCFEV_DBG_CONFIG__DCFEV_DBG_EN_MASK 0x1
+#define DCFEV_DBG_CONFIG__DCFEV_DBG_EN__SHIFT 0x0
+#define DCFEV_DBG_CONFIG__DCFEV_DBG_SEL_MASK 0xf0
+#define DCFEV_DBG_CONFIG__DCFEV_DBG_SEL__SHIFT 0x4
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL_MASK 0x3
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL__SHIFT 0x0
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE_MASK 0x4
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE__SHIFT 0x2
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE_MASK 0x8
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE__SHIFT 0x3
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE_MASK 0x10
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE__SHIFT 0x4
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE_MASK 0x20
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE__SHIFT 0x5
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE_MASK 0x40
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE__SHIFT 0x6
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE_MASK 0x80
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE__SHIFT 0x7
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE_MASK 0x100
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE__SHIFT 0x8
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE_MASK 0x200
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE__SHIFT 0x9
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE_MASK 0x400
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE__SHIFT 0xa
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE_MASK 0x800
+#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE__SHIFT 0xb
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE_MASK 0x3
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE__SHIFT 0x0
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE_MASK 0xc
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE__SHIFT 0x2
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE_MASK 0x30
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE__SHIFT 0x4
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE_MASK 0xc0
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE__SHIFT 0x6
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE_MASK 0x300
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE__SHIFT 0x8
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE_MASK 0xc00
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE__SHIFT 0xa
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE_MASK 0x3000
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE__SHIFT 0xc
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE_MASK 0xc000
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE__SHIFT 0xe
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE_MASK 0x30000
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE__SHIFT 0x10
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE_MASK 0xc0000
+#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE__SHIFT 0x12
+#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_FORCE_MASK 0x3
+#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_FORCE__SHIFT 0x0
+#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_DIS_MASK 0x4
+#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_DIS__SHIFT 0x2
+#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE_MASK 0x18
+#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE__SHIFT 0x3
+#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS_MASK 0x20
+#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS__SHIFT 0x5
+#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE_MASK 0xc0
+#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE__SHIFT 0x6
+#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS_MASK 0x100
+#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS__SHIFT 0x8
+#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE_MASK 0x600
+#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE__SHIFT 0x9
+#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS_MASK 0x800
+#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS__SHIFT 0xb
+#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE_MASK 0x3000
+#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE__SHIFT 0xc
+#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS_MASK 0x4000
+#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS__SHIFT 0xe
+#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE_MASK 0x18000
+#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE__SHIFT 0xf
+#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS_MASK 0x20000
+#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS__SHIFT 0x11
+#define DCFEV_MEM_PWR_CTRL2__COL_MAN_GAMMA_CORR_MEM_PWR_MODE_SEL_MASK 0x3
+#define DCFEV_MEM_PWR_CTRL2__COL_MAN_GAMMA_CORR_MEM_PWR_MODE_SEL__SHIFT 0x0
+#define DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL_MASK 0xc
+#define DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2
+#define DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL_MASK 0x30
+#define DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4
+#define DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL_MASK 0xc0
+#define DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL__SHIFT 0x6
+#define DCFEV_MEM_PWR_STATUS__COL_MAN_GAMMA_CORR_MEM_PWR_STATE_MASK 0x3
+#define DCFEV_MEM_PWR_STATUS__COL_MAN_GAMMA_CORR_MEM_PWR_STATE__SHIFT 0x0
+#define DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE_MASK 0xc
+#define DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE__SHIFT 0x2
+#define DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE_MASK 0x30
+#define DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE__SHIFT 0x4
+#define DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE_MASK 0xc0
+#define DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE__SHIFT 0x6
+#define DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE_MASK 0x300
+#define DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE__SHIFT 0x8
+#define DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE_MASK 0xc00
+#define DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE__SHIFT 0xa
+#define DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE_MASK 0x3000
+#define DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE__SHIFT 0xc
+#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_BUS_SEL_MASK 0xf
+#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_BUS_SEL__SHIFT 0x0
+#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LUMA_VS_CHROMA_MASK 0x10
+#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LUMA_VS_CHROMA__SHIFT 0x4
+#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LOWER_UPPER_MASK 0x20
+#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LOWER_UPPER__SHIFT 0x5
+#define DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN_MASK 0x1
+#define DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0
+#define DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x1
+#define DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0
+#define DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x2
+#define DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1
+#define DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x10
+#define DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4
+#define DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x100
+#define DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8
+#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000
+#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000
+#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+#define DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x1
+#define DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0
+#define DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x100
+#define DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8
+#define DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x10000
+#define DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10
+#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x100000
+#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14
+#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x1000000
+#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18
+#define DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x1fff
+#define DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0
+#define DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x3ff0000
+#define DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10
+#define DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000
+#define DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c
+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0xff
+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000
+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x1000000
+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18
+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000
+#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0xff
+#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0
+#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0xff00000
+#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14
+#define DCO_SCRATCH0__DCO_SCRATCH0_MASK 0xffffffff
+#define DCO_SCRATCH0__DCO_SCRATCH0__SHIFT 0x0
+#define DCO_SCRATCH1__DCO_SCRATCH1_MASK 0xffffffff
+#define DCO_SCRATCH1__DCO_SCRATCH1__SHIFT 0x0
+#define DCO_SCRATCH2__DCO_SCRATCH2_MASK 0xffffffff
+#define DCO_SCRATCH2__DCO_SCRATCH2__SHIFT 0x0
+#define DCO_SCRATCH3__DCO_SCRATCH3_MASK 0xffffffff
+#define DCO_SCRATCH3__DCO_SCRATCH3__SHIFT 0x0
+#define DCO_SCRATCH4__DCO_SCRATCH4_MASK 0xffffffff
+#define DCO_SCRATCH4__DCO_SCRATCH4__SHIFT 0x0
+#define DCO_SCRATCH5__DCO_SCRATCH5_MASK 0xffffffff
+#define DCO_SCRATCH5__DCO_SCRATCH5__SHIFT 0x0
+#define DCO_SCRATCH6__DCO_SCRATCH6_MASK 0xffffffff
+#define DCO_SCRATCH6__DCO_SCRATCH6__SHIFT 0x0
+#define DCO_SCRATCH7__DCO_SCRATCH7_MASK 0xffffffff
+#define DCO_SCRATCH7__DCO_SCRATCH7__SHIFT 0x0
+#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x7
+#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x0
+#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x70
+#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
+#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x1000000
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x1000000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT_MASK 0x800
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT_MASK 0x800
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT_MASK 0x800
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x800
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0xb
+#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK 0x1
+#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT 0x0
+#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE_MASK 0x4
+#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE__SHIFT 0x2
+#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK 0x8
+#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT 0x3
+#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK 0x10
+#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT 0x4
+#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK 0x20
+#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT 0x5
+#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK 0x40
+#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT 0x6
+#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK 0x80
+#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT 0x7
+#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK 0x100
+#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT 0x8
+#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK 0x200
+#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT 0x9
+#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE_MASK 0xc00
+#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE__SHIFT 0xa
+#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE_MASK 0x3000
+#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE__SHIFT 0xc
+#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE_MASK 0xc000
+#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE__SHIFT 0xe
+#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE_MASK 0x30000
+#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE__SHIFT 0x10
+#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE_MASK 0xc0000
+#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE__SHIFT 0x12
+#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE_MASK 0x300000
+#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE__SHIFT 0x14
+#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE_MASK 0xc00000
+#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE__SHIFT 0x16
+#define DCO_MEM_PWR_STATUS1__DPLPA_MEM_PWR_STATE_MASK 0x1
+#define DCO_MEM_PWR_STATUS1__DPLPA_MEM_PWR_STATE__SHIFT 0x0
+#define DCO_MEM_PWR_STATUS1__DPLPB_MEM_PWR_STATE_MASK 0x2
+#define DCO_MEM_PWR_STATUS1__DPLPB_MEM_PWR_STATE__SHIFT 0x1
+#define DCO_MEM_PWR_STATUS1__HDMILP0_MEM_PWR_STATE_MASK 0xc00
+#define DCO_MEM_PWR_STATUS1__HDMILP0_MEM_PWR_STATE__SHIFT 0xa
+#define DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE_MASK 0x3000
+#define DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE__SHIFT 0xc
+#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK 0x1
+#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x0
+#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK 0x2
+#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT 0x1
+#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS_MASK 0x8
+#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS__SHIFT 0x3
+#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK 0x10
+#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT 0x4
+#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK 0x20
+#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT 0x5
+#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK 0x40
+#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT 0x6
+#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK 0x80
+#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT 0x7
+#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK 0x100
+#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT 0x8
+#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK 0x200
+#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT 0x9
+#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK 0x400
+#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT 0xa
+#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE_MASK 0x1800
+#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE__SHIFT 0xb
+#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS_MASK 0x2000
+#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS__SHIFT 0xd
+#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE_MASK 0xc000
+#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE__SHIFT 0xe
+#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS_MASK 0x10000
+#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS__SHIFT 0x10
+#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE_MASK 0x60000
+#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE__SHIFT 0x11
+#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS_MASK 0x80000
+#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS__SHIFT 0x13
+#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE_MASK 0x300000
+#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE__SHIFT 0x14
+#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS_MASK 0x400000
+#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS__SHIFT 0x16
+#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE_MASK 0x1800000
+#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE__SHIFT 0x17
+#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS_MASK 0x2000000
+#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS__SHIFT 0x19
+#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE_MASK 0xc000000
+#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE__SHIFT 0x1a
+#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS_MASK 0x10000000
+#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS__SHIFT 0x1c
+#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE_MASK 0x60000000
+#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE__SHIFT 0x1d
+#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS_MASK 0x80000000
+#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS__SHIFT 0x1f
+#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL_MASK 0x3
+#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL__SHIFT 0x0
+#define DCO_MEM_PWR_CTRL2__DPLPA_LIGHT_SLEEP_DIS_MASK 0x4
+#define DCO_MEM_PWR_CTRL2__DPLPA_LIGHT_SLEEP_DIS__SHIFT 0x2
+#define DCO_MEM_PWR_CTRL2__DPLPB_LIGHT_SLEEP_DIS_MASK 0x8
+#define DCO_MEM_PWR_CTRL2__DPLPB_LIGHT_SLEEP_DIS__SHIFT 0x3
+#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_FORCE_MASK 0x30000
+#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_FORCE__SHIFT 0x10
+#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_DIS_MASK 0x40000
+#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_DIS__SHIFT 0x12
+#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_FORCE_MASK 0x180000
+#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_FORCE__SHIFT 0x13
+#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_DIS_MASK 0x200000
+#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_DIS__SHIFT 0x15
+#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x20
+#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x5
+#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x40
+#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x6
+#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x80
+#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x7
+#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x100
+#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x8
+#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x200
+#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x9
+#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS_MASK 0x400
+#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS__SHIFT 0xa
+#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x10000
+#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x10
+#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x20000
+#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x11
+#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x40000
+#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x12
+#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x80000
+#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x13
+#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x100000
+#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x14
+#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x200000
+#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x15
+#define DCO_CLK_CNTL__DISPCLK_G_DIGLPA_GATE_DIS_MASK 0x400000
+#define DCO_CLK_CNTL__DISPCLK_G_DIGLPA_GATE_DIS__SHIFT 0x16
+#define DCO_CLK_CNTL__DISPCLK_G_DIGLPB_GATE_DIS_MASK 0x800000
+#define DCO_CLK_CNTL__DISPCLK_G_DIGLPB_GATE_DIS__SHIFT 0x17
+#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x1000000
+#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18
+#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x2000000
+#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19
+#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x4000000
+#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a
+#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x8000000
+#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b
+#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000
+#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c
+#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000
+#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d
+#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000
+#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e
+#define DCO_CLK_CNTL2__DCO_TEST_CLK_SEL_MASK 0x7f
+#define DCO_CLK_CNTL2__DCO_TEST_CLK_SEL__SHIFT 0x0
+#define DCO_CLK_CNTL2__SCLK_G_AFMTA_GATE_DIS_MASK 0x80
+#define DCO_CLK_CNTL2__SCLK_G_AFMTA_GATE_DIS__SHIFT 0x7
+#define DCO_CLK_CNTL2__SCLK_G_AFMTB_GATE_DIS_MASK 0x100
+#define DCO_CLK_CNTL2__SCLK_G_AFMTB_GATE_DIS__SHIFT 0x8
+#define DCO_CLK_CNTL2__SCLK_G_AFMTC_GATE_DIS_MASK 0x200
+#define DCO_CLK_CNTL2__SCLK_G_AFMTC_GATE_DIS__SHIFT 0x9
+#define DCO_CLK_CNTL2__SCLK_G_AFMTD_GATE_DIS_MASK 0x400
+#define DCO_CLK_CNTL2__SCLK_G_AFMTD_GATE_DIS__SHIFT 0xa
+#define DCO_CLK_CNTL2__SCLK_G_AFMTE_GATE_DIS_MASK 0x800
+#define DCO_CLK_CNTL2__SCLK_G_AFMTE_GATE_DIS__SHIFT 0xb
+#define DCO_CLK_CNTL2__SCLK_G_AFMTF_GATE_DIS_MASK 0x1000
+#define DCO_CLK_CNTL2__SCLK_G_AFMTF_GATE_DIS__SHIFT 0xc
+#define DCO_CLK_CNTL2__SCLK_G_AFMTG_GATE_DIS_MASK 0x2000
+#define DCO_CLK_CNTL2__SCLK_G_AFMTG_GATE_DIS__SHIFT 0xd
+#define DCO_CLK_CNTL2__SCLK_G_AFMTLPA_GATE_DIS_MASK 0x8000
+#define DCO_CLK_CNTL2__SCLK_G_AFMTLPA_GATE_DIS__SHIFT 0xf
+#define DCO_CLK_CNTL2__SCLK_G_AFMTLPB_GATE_DIS_MASK 0x10000
+#define DCO_CLK_CNTL2__SCLK_G_AFMTLPB_GATE_DIS__SHIFT 0x10
+#define DCO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK 0x20000
+#define DCO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT 0x11
+#define DCO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK 0x40000
+#define DCO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT 0x12
+#define DCO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK 0x80000
+#define DCO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT 0x13
+#define DCO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK 0x100000
+#define DCO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT 0x14
+#define DCO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK 0x200000
+#define DCO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT 0x15
+#define DCO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK 0x400000
+#define DCO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT 0x16
+#define DCO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK 0x800000
+#define DCO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT 0x17
+#define DCO_CLK_CNTL2__SYMCLKLPA_FE_G_AFMT_GATE_DIS_MASK 0x2000000
+#define DCO_CLK_CNTL2__SYMCLKLPA_FE_G_AFMT_GATE_DIS__SHIFT 0x19
+#define DCO_CLK_CNTL2__SYMCLKLPB_FE_G_AFMT_GATE_DIS_MASK 0x4000000
+#define DCO_CLK_CNTL2__SYMCLKLPB_FE_G_AFMT_GATE_DIS__SHIFT 0x1a
+#define DCO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK 0x1
+#define DCO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT 0x0
+#define DCO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK 0x2
+#define DCO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT 0x1
+#define DCO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK 0x4
+#define DCO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT 0x2
+#define DCO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK 0x8
+#define DCO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT 0x3
+#define DCO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK 0x10
+#define DCO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT 0x4
+#define DCO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK 0x20
+#define DCO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT 0x5
+#define DCO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK 0x40
+#define DCO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT 0x6
+#define DCO_CLK_CNTL3__SYMCLKLPA_FE_G_TMDS_GATE_DIS_MASK 0x100
+#define DCO_CLK_CNTL3__SYMCLKLPA_FE_G_TMDS_GATE_DIS__SHIFT 0x8
+#define DCO_CLK_CNTL3__SYMCLKLPB_FE_G_TMDS_GATE_DIS_MASK 0x200
+#define DCO_CLK_CNTL3__SYMCLKLPB_FE_G_TMDS_GATE_DIS__SHIFT 0x9
+#define DCO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK 0x400
+#define DCO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT 0xa
+#define DCO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK 0x800
+#define DCO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT 0xb
+#define DCO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK 0x1000
+#define DCO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT 0xc
+#define DCO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK 0x2000
+#define DCO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT 0xd
+#define DCO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK 0x4000
+#define DCO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT 0xe
+#define DCO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK 0x8000
+#define DCO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT 0xf
+#define DCO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK 0x10000
+#define DCO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT 0x10
+#define DCO_CLK_CNTL3__SYMCLKLPA_G_TMDS_GATE_DIS_MASK 0x40000
+#define DCO_CLK_CNTL3__SYMCLKLPA_G_TMDS_GATE_DIS__SHIFT 0x12
+#define DCO_CLK_CNTL3__SYMCLKLPB_G_TMDS_GATE_DIS_MASK 0x80000
+#define DCO_CLK_CNTL3__SYMCLKLPB_G_TMDS_GATE_DIS__SHIFT 0x13
+#define DPDBG_CNTL__DPDBG_ENABLE_MASK 0x1
+#define DPDBG_CNTL__DPDBG_ENABLE__SHIFT 0x0
+#define DPDBG_CNTL__DPDBG_INPUT_ENABLE_MASK 0x2
+#define DPDBG_CNTL__DPDBG_INPUT_ENABLE__SHIFT 0x1
+#define DPDBG_CNTL__DPDBG_SYMCLK_ON_MASK 0x10
+#define DPDBG_CNTL__DPDBG_SYMCLK_ON__SHIFT 0x4
+#define DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE_MASK 0x100
+#define DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE__SHIFT 0x8
+#define DPDBG_CNTL__DPDBG_LINE_LENGTH_MASK 0xffff0000
+#define DPDBG_CNTL__DPDBG_LINE_LENGTH__SHIFT 0x10
+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK_MASK 0x1
+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK__SHIFT 0x0
+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE_MASK 0x2
+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE__SHIFT 0x1
+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK_MASK 0x100
+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK__SHIFT 0x8
+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED_MASK 0x10000
+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED__SHIFT 0x10
+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS_MASK 0x1000000
+#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS__SHIFT 0x18
+#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x1
+#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0
+#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x100
+#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8
+#define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x1
+#define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x0
+#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK 0x10
+#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT 0x4
+#define DCO_SOFT_RESET__I2S1_SOFT_RESET_MASK 0x20
+#define DCO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT 0x5
+#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK 0x40
+#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT 0x6
+#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET_MASK 0x1000
+#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET__SHIFT 0xc
+#define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x10000
+#define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x10
+#define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x20000
+#define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x11
+#define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x40000
+#define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x12
+#define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x80000
+#define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x13
+#define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x100000
+#define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x14
+#define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x200000
+#define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x15
+#define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x1000000
+#define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x18
+#define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x2000000
+#define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x19
+#define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x8000000
+#define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x1b
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x1
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x2
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x10
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x20
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x100
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x200
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x1000
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x2000
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x10000
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x20000
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x100000
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x200000
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x1000000
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x2000000
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19
+#define DIG_SOFT_RESET__DPDBG_SOFT_RESET_MASK 0x80000000
+#define DIG_SOFT_RESET__DPDBG_SOFT_RESET__SHIFT 0x1f
+#define DIG_SOFT_RESET_2__DIGLPA_FE_SOFT_RESET_MASK 0x1
+#define DIG_SOFT_RESET_2__DIGLPA_FE_SOFT_RESET__SHIFT 0x0
+#define DIG_SOFT_RESET_2__DIGLPA_BE_SOFT_RESET_MASK 0x2
+#define DIG_SOFT_RESET_2__DIGLPA_BE_SOFT_RESET__SHIFT 0x1
+#define DIG_SOFT_RESET_2__DIGLPB_FE_SOFT_RESET_MASK 0x10
+#define DIG_SOFT_RESET_2__DIGLPB_FE_SOFT_RESET__SHIFT 0x4
+#define DIG_SOFT_RESET_2__DIGLPB_BE_SOFT_RESET_MASK 0x20
+#define DIG_SOFT_RESET_2__DIGLPB_BE_SOFT_RESET__SHIFT 0x5
+#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x7
+#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x0
+#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x70000
+#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x10
+#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX_MASK 0xff
+#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA__SHIFT 0x0
+#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x1
+#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x2
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x4
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x8
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x700
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x300000
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14
+#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000
+#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x1f
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x3
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0xc
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x10
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x100
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x1000
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x100000
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x200000
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x1000000
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x2000000
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x1
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x2
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x4
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x10
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x20
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x40
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x100
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x200
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x400
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x1000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x2000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x4000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x10000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x20000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x40000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x100000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x200000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x400000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x1000000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x2000000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x4000000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x8000000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x3
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x4
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x10
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x20
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x40
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x80
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x100
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x1000
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x2000
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x4000
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x8000
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x40000
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x3
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x8
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x10000
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x20000
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x100000
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x3
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x8
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x10000
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x20000
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x100000
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x3
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x8
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x10000
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x20000
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x100000
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x3
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x8
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x10000
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x20000
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x100000
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x3
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x8
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x10000
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x20000
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x100000
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x3
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x8
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x10000
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x20000
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x100000
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x3
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x300
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xffff0000
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x1
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x2
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x10
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x20
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x40
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x80
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0xff00
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0xff0000
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xff000000
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x3
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x300
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xffff0000
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x1
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x2
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x10
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x20
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x40
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x80
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0xff00
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0xff0000
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xff000000
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x3
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK 0x300
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xffff0000
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x1
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x2
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x10
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x20
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x40
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x80
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0xff00
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0xff0000
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xff000000
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x3
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK 0x300
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xffff0000
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x1
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x2
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x10
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x20
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x40
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x80
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0xff00
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0xff0000
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xff000000
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x3
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK 0x300
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xffff0000
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x1
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x2
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x10
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x20
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x40
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x80
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0xff00
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0xff0000
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xff000000
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x3
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL_MASK 0x300
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xffff0000
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x1
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x2
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x10
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x20
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x40
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x80
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0xff00
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0xff0000
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xff000000
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x1
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x100
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8
+#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x1000
+#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x2000
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0xff0000
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x1
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x100
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8
+#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x1000
+#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x2000
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0xff0000
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x1
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x100
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8
+#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x1000
+#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x2000
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0xff0000
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x1
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x100
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8
+#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x1000
+#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x2000
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0xff0000
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10
+#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x1
+#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0
+#define DC_I2C_DATA__DC_I2C_DATA_MASK 0xff00
+#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8
+#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0xff0000
+#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x3
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x8
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x10000
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x20000
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x11
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x100000
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x3
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL_MASK 0x300
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xffff0000
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x1
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x2
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x10
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x20
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x40
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x6
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x80
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0xff00
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0xff0000
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xff000000
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0xffff
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0xf00000
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x1
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x2
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x4
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x8
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x10
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x20
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x40
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x80
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x100
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x200
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x400
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x800
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x1000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x2000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x4000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x8000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x10000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x20000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x40000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x80000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x100000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x200000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x400000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x800000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x1000000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x2000000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x4000000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x8000000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x1
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x0
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x2
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x1
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x4
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x2
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x8
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x3
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK 0x80000000
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT 0x1f
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x1
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x0
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x2
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x1
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x4
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x2
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED_MASK 0x100
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED__SHIFT 0x8
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_MASK 0x200
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT__SHIFT 0x9
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK_MASK 0x400
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK__SHIFT 0xa
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK_MASK 0x800
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK__SHIFT 0xb
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x1000
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0xc
+#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0xf
+#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x0
+#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x10
+#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x4
+#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x20
+#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x5
+#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x40
+#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x6
+#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x200
+#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x9
+#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x400
+#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0xa
+#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x3
+#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x0
+#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL_MASK 0x300
+#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL__SHIFT 0x8
+#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xffff0000
+#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x10
+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x1
+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x0
+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x2
+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x1
+#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x80
+#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x7
+#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0xff00
+#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x8
+#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xff000000
+#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x18
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x1
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x0
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x100
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x8
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x200
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x9
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x1000
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0xc
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x2000
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0xd
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0xf0000
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x10
+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x1
+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x0
+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0xff00
+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x8
+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0xf0000
+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x10
+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000
+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x1f
+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x7f
+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x0
+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x7f00
+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x8
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK 0x1
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT 0x0
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK 0x2
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT 0x1
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK 0x4
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT 0x2
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK 0x10
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT 0x4
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK 0x20
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT 0x5
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK 0x40
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT 0x6
+#define BLNDV_CONTROL__BLND_GLOBAL_GAIN_MASK 0xff
+#define BLNDV_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0
+#define BLNDV_CONTROL__BLND_MODE_MASK 0x300
+#define BLNDV_CONTROL__BLND_MODE__SHIFT 0x8
+#define BLNDV_CONTROL__BLND_STEREO_TYPE_MASK 0xc00
+#define BLNDV_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa
+#define BLNDV_CONTROL__BLND_STEREO_POLARITY_MASK 0x1000
+#define BLNDV_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc
+#define BLNDV_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x2000
+#define BLNDV_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd
+#define BLNDV_CONTROL__BLND_ALPHA_MODE_MASK 0x30000
+#define BLNDV_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
+#define BLNDV_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x100000
+#define BLNDV_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
+#define BLNDV_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xff000000
+#define BLNDV_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
+#define BLNDV_SM_CONTROL2__SM_MODE_MASK 0x7
+#define BLNDV_SM_CONTROL2__SM_MODE__SHIFT 0x0
+#define BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x10
+#define BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
+#define BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x20
+#define BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
+#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x300
+#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x30000
+#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+#define BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x1000000
+#define BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
+#define BLNDV_CONTROL2__PTI_ENABLE_MASK 0x1
+#define BLNDV_CONTROL2__PTI_ENABLE__SHIFT 0x0
+#define BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x30
+#define BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4
+#define BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x40
+#define BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6
+#define BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x80
+#define BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7
+#define BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x100
+#define BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8
+#define BLNDV_UPDATE__BLND_UPDATE_PENDING_MASK 0x1
+#define BLNDV_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
+#define BLNDV_UPDATE__BLND_UPDATE_TAKEN_MASK 0x100
+#define BLNDV_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
+#define BLNDV_UPDATE__BLND_UPDATE_LOCK_MASK 0x10000
+#define BLNDV_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
+#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x1
+#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
+#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x100
+#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
+#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x1000
+#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
+#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x30000
+#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
+#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x1
+#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
+#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x2
+#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
+#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x10000
+#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
+#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK 0x1000000
+#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT 0x18
+#define BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000
+#define BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
+#define BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000
+#define BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d
+#define BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000
+#define BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f
+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x1
+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0
+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x2
+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1
+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x4
+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x8
+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x40
+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6
+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x80
+#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7
+#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x100
+#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8
+#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x200
+#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9
+#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x400
+#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa
+#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x800
+#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb
+#define BLNDV_DEBUG__BLND_CNV_MUX_SELECT_MASK 0x1
+#define BLNDV_DEBUG__BLND_CNV_MUX_SELECT__SHIFT 0x0
+#define BLNDV_DEBUG__BLND_DEBUG_MASK 0xfffffffe
+#define BLNDV_DEBUG__BLND_DEBUG__SHIFT 0x1
+#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK 0xff
+#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT 0x0
+#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define BLNDV_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK 0xffffffff
+#define BLNDV_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT 0x0
+#define CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x3ff
+#define CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
+#define CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x10000
+#define CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
+#define CRTCV_H_TOTAL__CRTC_H_TOTAL_MASK 0x3fff
+#define CRTCV_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
+#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x3fff
+#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
+#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3fff0000
+#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
+#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x3fff
+#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
+#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3fff0000
+#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
+#define CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x1
+#define CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
+#define CRTCV_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x10000
+#define CRTCV_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
+#define CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x20000
+#define CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
+#define CRTCV_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x3fff
+#define CRTCV_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
+#define CRTCV_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3fff0000
+#define CRTCV_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
+#define CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x1
+#define CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
+#define CRTCV_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x10000
+#define CRTCV_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
+#define CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x20000
+#define CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
+#define CRTCV_VBI_END__CRTC_VBI_V_END_MASK 0x3fff
+#define CRTCV_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
+#define CRTCV_VBI_END__CRTC_VBI_H_END_MASK 0x3fff0000
+#define CRTCV_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
+#define CRTCV_V_TOTAL__CRTC_V_TOTAL_MASK 0x3fff
+#define CRTCV_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
+#define CRTCV_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x3fff
+#define CRTCV_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
+#define CRTCV_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x3fff
+#define CRTCV_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
+#define CRTCV_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x10000
+#define CRTCV_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
+#define CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x1
+#define CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
+#define CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x10
+#define CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
+#define CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100
+#define CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
+#define CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x1000
+#define CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
+#define CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x8000
+#define CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
+#define CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000
+#define CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x1
+#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x10
+#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x100
+#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x1000
+#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+#define CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x1
+#define CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
+#define CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x10
+#define CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x3fff
+#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
+#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3fff0000
+#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
+#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x3fff
+#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
+#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3fff0000
+#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
+#define CRTCV_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x1
+#define CRTCV_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
+#define CRTCV_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x3fff
+#define CRTCV_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
+#define CRTCV_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3fff0000
+#define CRTCV_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
+#define CRTCV_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x1
+#define CRTCV_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
+#define CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x1
+#define CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
+#define CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x1e
+#define CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
+#define CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x3fff
+#define CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
+#define CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3fff0000
+#define CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
+#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x1f
+#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
+#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0xe0
+#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
+#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x100
+#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200
+#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
+#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x400
+#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
+#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800
+#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
+#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x3000
+#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x30000
+#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x300000
+#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000
+#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
+#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000
+#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
+#define CRTCV_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x1
+#define CRTCV_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
+#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x1f
+#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
+#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0xe0
+#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
+#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x100
+#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200
+#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
+#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x400
+#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
+#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800
+#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
+#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x3000
+#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x30000
+#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x300000
+#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000
+#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
+#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000
+#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
+#define CRTCV_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x1
+#define CRTCV_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
+#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x3
+#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x10
+#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x100
+#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x10000
+#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x1000000
+#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x1f
+#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x100
+#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
+#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x10000
+#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x1000000
+#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x3
+#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0xff00
+#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8
+#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1fff0000
+#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10
+#define CRTCV_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xffffffff
+#define CRTCV_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0
+#define CRTCV_CONTROL__CRTC_MASTER_EN_MASK 0x1
+#define CRTCV_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTCV_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x10
+#define CRTCV_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
+#define CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x300
+#define CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
+#define CRTCV_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000
+#define CRTCV_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
+#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x2000
+#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
+#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x4000
+#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
+#define CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x10000
+#define CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+#define CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x700000
+#define CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
+#define CRTCV_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x1000000
+#define CRTCV_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x18
+#define CRTCV_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000
+#define CRTCV_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
+#define CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000
+#define CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e
+#define CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000
+#define CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f
+#define CRTCV_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x1
+#define CRTCV_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
+#define CRTCV_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x100
+#define CRTCV_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
+#define CRTCV_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x10000
+#define CRTCV_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
+#define CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x1
+#define CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
+#define CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x30000
+#define CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+#define CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x1
+#define CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+#define CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x2
+#define CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
+#define CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x1
+#define CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
+#define CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x2
+#define CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
+#define CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0xfff
+#define CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+#define CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0xfff0000
+#define CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+#define CRTCV_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0xfff
+#define CRTCV_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
+#define CRTCV_STATUS__CRTC_V_BLANK_MASK 0x1
+#define CRTCV_STATUS__CRTC_V_BLANK__SHIFT 0x0
+#define CRTCV_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x2
+#define CRTCV_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
+#define CRTCV_STATUS__CRTC_V_SYNC_A_MASK 0x4
+#define CRTCV_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
+#define CRTCV_STATUS__CRTC_V_UPDATE_MASK 0x8
+#define CRTCV_STATUS__CRTC_V_UPDATE__SHIFT 0x3
+#define CRTCV_STATUS__CRTC_V_START_LINE_MASK 0x10
+#define CRTCV_STATUS__CRTC_V_START_LINE__SHIFT 0x4
+#define CRTCV_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x20
+#define CRTCV_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+#define CRTCV_STATUS__CRTC_H_BLANK_MASK 0x10000
+#define CRTCV_STATUS__CRTC_H_BLANK__SHIFT 0x10
+#define CRTCV_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x20000
+#define CRTCV_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
+#define CRTCV_STATUS__CRTC_H_SYNC_A_MASK 0x40000
+#define CRTCV_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
+#define CRTCV_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x3fff
+#define CRTCV_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
+#define CRTCV_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3fff0000
+#define CRTCV_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
+#define CRTCV_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x3fff
+#define CRTCV_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
+#define CRTCV_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0xffffff
+#define CRTCV_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
+#define CRTCV_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3fffffff
+#define CRTCV_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
+#define CRTCV_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3fffffff
+#define CRTCV_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
+#define CRTCV_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x1
+#define CRTCV_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
+#define CRTCV_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x1e
+#define CRTCV_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
+#define CRTCV_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x1
+#define CRTCV_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
+#define CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x1
+#define CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+#define CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x1
+#define CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+#define CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x100
+#define CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+#define CRTCV_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x30000
+#define CRTCV_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+#define CRTCV_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x1
+#define CRTCV_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
+#define CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x100
+#define CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
+#define CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x10000
+#define CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
+#define CRTCV_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x100000
+#define CRTCV_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14
+#define CRTCV_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x3000000
+#define CRTCV_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x3fff
+#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x8000
+#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x10000
+#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
+#define CRTCV_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x20000
+#define CRTCV_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11
+#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x40000
+#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12
+#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x80000
+#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13
+#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x100000
+#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14
+#define CRTCV_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x1000000
+#define CRTCV_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
+#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x1
+#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
+#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x2
+#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
+#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x4
+#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+#define CRTCV_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x3
+#define CRTCV_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+#define CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x3fff
+#define CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+#define CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3fff0000
+#define CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+#define CRTCV_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0xffffff
+#define CRTCV_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+#define CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x1
+#define CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
+#define CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x2
+#define CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1
+#define CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x4
+#define CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2
+#define CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100
+#define CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8
+#define CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0xff000
+#define CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc
+#define CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x1
+#define CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
+#define CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x2
+#define CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
+#define CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x10
+#define CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
+#define CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x20
+#define CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
+#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x100
+#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200
+#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x10000
+#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x20000
+#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x1000000
+#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
+#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x2000000
+#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
+#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x4000000
+#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
+#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x8000000
+#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
+#define CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000
+#define CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+#define CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000
+#define CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+#define CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000
+#define CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+#define CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000
+#define CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+#define CRTCV_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x1
+#define CRTCV_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
+#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x1
+#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
+#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x100
+#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
+#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x10000
+#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+#define CRTCV_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x1
+#define CRTCV_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
+#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x1
+#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
+#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x700
+#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
+#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x10000
+#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
+#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000
+#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
+#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0xf
+#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
+#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0xf0
+#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
+#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0xf00
+#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
+#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0xf000
+#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
+#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000
+#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
+#define CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0xffff
+#define CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
+#define CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x3f0000
+#define CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
+#define CRTCV_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x1
+#define CRTCV_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
+#define CRTCV_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x100
+#define CRTCV_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
+#define CRTCV_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x10000
+#define CRTCV_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10
+#define CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x7
+#define CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
+#define CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x30000
+#define CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
+#define CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x3
+#define CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
+#define CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00
+#define CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
+#define CRTCV_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0xff
+#define CRTCV_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
+#define CRTCV_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x1
+#define CRTCV_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
+#define CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x10
+#define CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
+#define CRTCV_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x10000
+#define CRTCV_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
+#define CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x100000
+#define CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
+#define CRTCV_MASTER_EN__CRTC_MASTER_EN_MASK 0x1
+#define CRTCV_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0xff
+#define CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
+#define CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x10000
+#define CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
+#define CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x1
+#define CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
+#define CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x100
+#define CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
+#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x3ff
+#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
+#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0xffc00
+#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
+#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000
+#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
+#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x3
+#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
+#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x300
+#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
+#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x30000
+#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
+#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x3ff
+#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0xffc00
+#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000
+#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x3
+#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x300
+#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x30000
+#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x3ff
+#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
+#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0xffc00
+#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
+#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000
+#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
+#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x3
+#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x300
+#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x30000
+#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+#define CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x3fff
+#define CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+#define CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3fff0000
+#define CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x10
+#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x100
+#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x1000
+#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x10000
+#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x100000
+#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x1000000
+#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+#define CRTCV_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x3fff
+#define CRTCV_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x100
+#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x1000
+#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x10000
+#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x100000
+#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x1000000
+#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+#define CRTCV_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x3fff
+#define CRTCV_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x100
+#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x1000
+#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x10000
+#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x100000
+#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x1000000
+#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+#define CRTCV_CRC_CNTL__CRTC_CRC_EN_MASK 0x1
+#define CRTCV_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
+#define CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x10
+#define CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
+#define CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x300
+#define CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
+#define CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x3000
+#define CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
+#define CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000
+#define CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+#define CRTCV_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x700000
+#define CRTCV_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
+#define CRTCV_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x7000000
+#define CRTCV_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
+#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x3fff
+#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
+#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3fff0000
+#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
+#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x3fff
+#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
+#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3fff0000
+#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
+#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x3fff
+#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
+#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3fff0000
+#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
+#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x3fff
+#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
+#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3fff0000
+#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
+#define CRTCV_CRC0_DATA_RG__CRC0_R_CR_MASK 0xffff
+#define CRTCV_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+#define CRTCV_CRC0_DATA_RG__CRC0_G_Y_MASK 0xffff0000
+#define CRTCV_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+#define CRTCV_CRC0_DATA_B__CRC0_B_CB_MASK 0xffff
+#define CRTCV_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x3fff
+#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
+#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3fff0000
+#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
+#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x3fff
+#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
+#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3fff0000
+#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
+#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x3fff
+#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
+#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3fff0000
+#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
+#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x3fff
+#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
+#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3fff0000
+#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
+#define CRTCV_CRC1_DATA_RG__CRC1_R_CR_MASK 0xffff
+#define CRTCV_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+#define CRTCV_CRC1_DATA_RG__CRC1_G_Y_MASK 0xffff0000
+#define CRTCV_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+#define CRTCV_CRC1_DATA_B__CRC1_B_CB_MASK 0xffff
+#define CRTCV_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0xffff
+#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0xff0000
+#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x1000000
+#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
+#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x2000000
+#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
+#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x4000000
+#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
+#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x8000000
+#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
+#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000
+#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
+#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x1
+#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
+#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x10
+#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
+#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x300
+#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x1000
+#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x10000
+#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x20000
+#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0xc0000
+#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0xff
+#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0xff00
+#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x10000
+#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x60000
+#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x80000
+#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x100000
+#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x800000
+#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000
+#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
+#define CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x3fff
+#define CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
+#define CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3fff0000
+#define CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
+#define CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x3fff
+#define CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
+#define CRTCV_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x1f0000
+#define CRTCV_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
+#define CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000
+#define CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0xff
+#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x0
+#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define CRTCV_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffff
+#define CRTCV_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x0
+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP_MASK 0x300
+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP__SHIFT 0x8
+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID_MASK 0xf000
+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID__SHIFT 0xc
+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV_MASK 0x10000
+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV__SHIFT 0x10
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE_MASK 0xf
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE__SHIFT 0x0
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT_MASK 0x70
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT__SHIFT 0x4
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH_MASK 0x300
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH__SHIFT 0x8
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT_MASK 0xc00
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT__SHIFT 0xa
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT_MASK 0x3000
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT__SHIFT 0xc
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS_MASK 0x300000
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS__SHIFT 0x14
+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE_MASK 0x7
+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE__SHIFT 0x0
+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE_MASK 0x700000
+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE__SHIFT 0x14
+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG_MASK 0xf8000000
+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG__SHIFT 0x1b
+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT_MASK 0x100
+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT__SHIFT 0x8
+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK_MASK 0x200
+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK__SHIFT 0x9
+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK_MASK 0x400
+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK__SHIFT 0xa
+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT_MASK 0x10000
+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT__SHIFT 0x10
+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK_MASK 0x20000
+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK__SHIFT 0x11
+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK_MASK 0x40000
+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK__SHIFT 0x12
+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT_MASK 0x100000
+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT__SHIFT 0x14
+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK_MASK 0x200000
+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK__SHIFT 0x15
+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK_MASK 0x400000
+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK__SHIFT 0x16
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY_MASK 0xf
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY__SHIFT 0x0
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY_MASK 0xff0
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS_MASK 0x8000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS__SHIFT 0xf
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS_MASK 0x10000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS__SHIFT 0x10
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0_MASK 0x20000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0__SHIFT 0x11
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1_MASK 0x40000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1__SHIFT 0x12
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2_MASK 0x80000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2__SHIFT 0x13
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3_MASK 0x100000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3__SHIFT 0x14
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4_MASK 0x200000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4__SHIFT 0x15
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5_MASK 0x400000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5__SHIFT 0x16
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS_MASK 0x800000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS__SHIFT 0x17
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS_MASK 0x1000000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS__SHIFT 0x18
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS_MASK 0x2000000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS__SHIFT 0x19
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_CORE_IDLE_STATE_MASK 0x3
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_CORE_IDLE_STATE__SHIFT 0x0
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_IDLE_STATE_MASK 0xc
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_IDLE_STATE__SHIFT 0x2
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_STATE_MASK 0x180000
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_STATE__SHIFT 0x13
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_TRANS_MASK 0x200000
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_TRANS__SHIFT 0x15
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_STATE_MASK 0xc00000
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_STATE__SHIFT 0x16
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_TRANS_MASK 0x2000000
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_TRANS__SHIFT 0x19
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_STATE_MASK 0xc000000
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_STATE__SHIFT 0x1a
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_TRANS_MASK 0x10000000
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_TRANS__SHIFT 0x1c
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_STATE_MASK 0x60000000
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_STATE__SHIFT 0x1d
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_TRANS_MASK 0x80000000
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_TRANS__SHIFT 0x1f
+#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS_MASK 0xf
+#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS__SHIFT 0x0
+#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR_MASK 0x100
+#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR__SHIFT 0x8
+#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS_MASK 0xff
+#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS__SHIFT 0x0
+#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY_MASK 0x1
+#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY__SHIFT 0x0
+#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX_MASK 0xff
+#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT 0x0
+#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA_MASK 0xffffffff
+#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA__SHIFT 0x0
+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY_MASK 0x7
+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY__SHIFT 0x0
+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS_MASK 0x8
+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT 0x3
+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY_MASK 0xffff8000
+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY__SHIFT 0xf
+#define XDMA_PG_CONTROL__XDMA_PG_CONTROL_MASK 0xffffffff
+#define XDMA_PG_CONTROL__XDMA_PG_CONTROL__SHIFT 0x0
+#define XDMA_PG_WDATA__XDMA_PG_WDATA_MASK 0xffffffff
+#define XDMA_PG_WDATA__XDMA_PG_WDATA__SHIFT 0x0
+#define XDMA_PG_STATUS__XDMA_SERDES_RDATA_MASK 0xffffff
+#define XDMA_PG_STATUS__XDMA_SERDES_RDATA__SHIFT 0x0
+#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY_MASK 0x1000000
+#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY__SHIFT 0x18
+#define XDMA_PG_STATUS__XDMA_SERDES_BUSY_MASK 0x2000000
+#define XDMA_PG_STATUS__XDMA_SERDES_BUSY__SHIFT 0x19
+#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS_MASK 0x4000000
+#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS__SHIFT 0x1a
+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX_MASK 0xff
+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX__SHIFT 0x0
+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL_MASK 0x200
+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL__SHIFT 0x9
+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_OUT_EN_MASK 0x400
+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_OUT_EN__SHIFT 0xa
+#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA_MASK 0xffffffff
+#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA__SHIFT 0x0
+#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION_MASK 0x3000
+#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION__SHIFT 0xc
+#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY_MASK 0x4000
+#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY__SHIFT 0xe
+#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE_MASK 0x10000
+#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE__SHIFT 0x10
+#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE_MASK 0x40000
+#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE__SHIFT 0x12
+#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET_MASK 0x100000
+#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET__SHIFT 0x14
+#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN_MASK 0x200000
+#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN__SHIFT 0x15
+#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT_MASK 0x3fff
+#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT__SHIFT 0x0
+#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT_MASK 0xfff0000
+#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT__SHIFT 0x10
+#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT_MASK 0x70000000
+#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT__SHIFT 0x1c
+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP_MASK 0x300
+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP__SHIFT 0x8
+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID_MASK 0xf000
+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID__SHIFT 0xc
+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV_MASK 0x10000
+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV__SHIFT 0x10
+#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_MASK 0xffffffff
+#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__SHIFT 0x0
+#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH_MASK 0xff
+#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__SHIFT 0x0
+#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH_MASK 0x3fff
+#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH__SHIFT 0x0
+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL_MASK 0x1
+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL__SHIFT 0x0
+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL_MASK 0xf00
+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL__SHIFT 0x8
+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY_MASK 0xf000
+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY__SHIFT 0xc
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL_MASK 0x1
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL__SHIFT 0x0
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT_MASK 0xf0
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT__SHIFT 0x4
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL_MASK 0xf00
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL__SHIFT 0x8
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY_MASK 0xf000
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY__SHIFT 0xc
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER_MASK 0xffff0000
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER__SHIFT 0x10
+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG_MASK 0x3ff
+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG__SHIFT 0x0
+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_MASK 0x3000
+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK__SHIFT 0xc
+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR_MASK 0x10000
+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR__SHIFT 0x10
+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG_MASK 0x3ff
+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG__SHIFT 0x0
+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_MASK 0x3000
+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK__SHIFT 0xc
+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR_MASK 0x10000
+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR__SHIFT 0x10
+#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL_MASK 0x7
+#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL__SHIFT 0x0
+#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT_MASK 0x3fff00
+#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT__SHIFT 0x8
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES_MASK 0xff
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES__SHIFT 0x0
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST_MASK 0x100
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST__SHIFT 0x8
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE_MASK 0x200
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE__SHIFT 0x9
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET_MASK 0x400
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET__SHIFT 0xa
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE_MASK 0x800
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE__SHIFT 0xb
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID_MASK 0x7000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID__SHIFT 0xc
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE_MASK 0x8000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE__SHIFT 0xf
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN_MASK 0xff0000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN__SHIFT 0x10
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE_MASK 0x1000000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE__SHIFT 0x18
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING_MASK 0x2000000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING__SHIFT 0x19
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING_MASK 0x4000000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING__SHIFT 0x1a
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE_MASK 0x8000000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE__SHIFT 0x1b
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_SUPERAA_ENABLE_MASK 0x10000000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_SUPERAA_ENABLE__SHIFT 0x1c
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_HSYNC_GSL_GROUP_MASK 0x60000000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_HSYNC_GSL_GROUP__SHIFT 0x1d
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_GSL_GROUP_MASTER_MASK 0x80000000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_GSL_GROUP_MASTER__SHIFT 0x1f
+#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE_MASK 0x3fff
+#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE__SHIFT 0x0
+#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH_MASK 0x3fff0000
+#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH__SHIFT 0x10
+#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH_MASK 0x3fff
+#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH__SHIFT 0x0
+#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT_MASK 0x3fff0000
+#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT__SHIFT 0x10
+#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT_MASK 0x3fff
+#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT__SHIFT 0x0
+#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT_MASK 0x3fff0000
+#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT__SHIFT 0x10
+#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE_MASK 0xffffffff
+#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE__SHIFT 0x0
+#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH_MASK 0xff
+#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__SHIFT 0x0
+#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS_MASK 0xffffffff
+#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS__SHIFT 0x0
+#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff
+#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0
+#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR_MASK 0xffffffff
+#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR__SHIFT 0x0
+#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH_MASK 0xff
+#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH__SHIFT 0x0
+#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_PITCH_MASK 0x3fff
+#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_PITCH__SHIFT 0x0
+#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_STATE_MASK 0x60000000
+#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_STATE__SHIFT 0x1d
+#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_TRANS_MASK 0x80000000
+#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_TRANS__SHIFT 0x1f
+#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X_MASK 0x3fff
+#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X__SHIFT 0x0
+#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y_MASK 0x3fff0000
+#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y__SHIFT 0x10
+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA_MASK 0xffffff
+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA__SHIFT 0x0
+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MASK 0x7000000
+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX__SHIFT 0x18
+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE_MASK 0xc0000000
+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE__SHIFT 0x1e
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER_MASK 0xfff
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER__SHIFT 0x0
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL_MASK 0x1f000
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL__SHIFT 0xc
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST_MASK 0x20000
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST__SHIFT 0x11
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER_MASK 0x7ff80000
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER__SHIFT 0x13
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST_MASK 0x80000000
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST__SHIFT 0x1f
+#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES_MASK 0x1
+#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES__SHIFT 0x0
+#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK 0x200
+#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY__SHIFT 0x9
+#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE_MASK 0x400
+#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE__SHIFT 0xa
+#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION_MASK 0x3000
+#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION__SHIFT 0xc
+#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE_MASK 0x10000
+#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE__SHIFT 0x10
+#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN_MASK 0x80000
+#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN__SHIFT 0x13
+#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET_MASK 0x100000
+#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET__SHIFT 0x14
+#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT_MASK 0x1000000
+#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT__SHIFT 0x18
+#define XDMA_SLV_CNTL__XDMA_SLV_WB_BURST_RESET_MASK 0x2000000
+#define XDMA_SLV_CNTL__XDMA_SLV_WB_BURST_RESET__SHIFT 0x19
+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP_MASK 0x300
+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP__SHIFT 0x8
+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID_MASK 0xf000
+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID__SHIFT 0xc
+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV_MASK 0x10000
+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV__SHIFT 0x10
+#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH_MASK 0x3fff
+#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH__SHIFT 0x0
+#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH_MASK 0x3fff0000
+#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH__SHIFT 0x10
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL_MASK 0x1
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL__SHIFT 0x0
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT_MASK 0xf0
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT__SHIFT 0x4
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL_MASK 0xf00
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL__SHIFT 0x8
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY_MASK 0xf000
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY__SHIFT 0xc
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER_MASK 0xffff0000
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER__SHIFT 0x10
+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_MASK 0x1
+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL__SHIFT 0x0
+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL_MASK 0xf00
+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL__SHIFT 0x8
+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY_MASK 0xf000
+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY__SHIFT 0xc
+#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE_MASK 0x1ff
+#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE__SHIFT 0x0
+#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD_MASK 0xffff0000
+#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD__SHIFT 0x10
+#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN_MASK 0xffff
+#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN__SHIFT 0x0
+#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX_MASK 0xffff0000
+#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX__SHIFT 0x10
+#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC_MASK 0xfffff
+#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC__SHIFT 0x0
+#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT_MASK 0xfff00000
+#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT__SHIFT 0x14
+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG_MASK 0x3ff
+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG__SHIFT 0x0
+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_MASK 0x3000
+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK__SHIFT 0xc
+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR_MASK 0x10000
+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR__SHIFT 0x10
+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG_MASK 0xffff
+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG__SHIFT 0x0
+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_MASK 0x30000
+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK__SHIFT 0x10
+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR_MASK 0x80000000
+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR__SHIFT 0x1f
+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES_MASK 0x3ff
+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES__SHIFT 0x0
+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE_MASK 0x3ff000
+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE__SHIFT 0xc
+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_STATE_MASK 0xc00000
+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_STATE__SHIFT 0x16
+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_TRANS_MASK 0x1000000
+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_TRANS__SHIFT 0x18
+#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER_MASK 0xffff
+#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER__SHIFT 0x0
+#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING_MASK 0x1
+#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING__SHIFT 0x0
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT_MASK 0x1ff
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT__SHIFT 0x0
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER_MASK 0x10000
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER__SHIFT 0x10
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET_MASK 0x20000
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET__SHIFT 0x11
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE_MASK 0x1000000
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE__SHIFT 0x18
+#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS_MASK 0xffffffff
+#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS__SHIFT 0x0
+#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff
+#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0
+
+#endif /* DCE_11_0_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h
new file mode 100644
index 000000000000..dc52ea0df4b4
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h
@@ -0,0 +1,5703 @@
+/*
+ * DCE_8_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef DCE_8_0_D_H
+#define DCE_8_0_D_H
+
+#define mmPIPE0_PG_CONFIG 0x1760
+#define mmPIPE0_PG_ENABLE 0x1761
+#define mmPIPE0_PG_STATUS 0x1762
+#define mmPIPE1_PG_CONFIG 0x1764
+#define mmPIPE1_PG_ENABLE 0x1765
+#define mmPIPE1_PG_STATUS 0x1766
+#define mmPIPE2_PG_CONFIG 0x1768
+#define mmPIPE2_PG_ENABLE 0x1769
+#define mmPIPE2_PG_STATUS 0x176a
+#define mmPIPE3_PG_CONFIG 0x176c
+#define mmPIPE3_PG_ENABLE 0x176d
+#define mmPIPE3_PG_STATUS 0x176e
+#define mmPIPE4_PG_CONFIG 0x1770
+#define mmPIPE4_PG_ENABLE 0x1771
+#define mmPIPE4_PG_STATUS 0x1772
+#define mmPIPE5_PG_CONFIG 0x1774
+#define mmPIPE5_PG_ENABLE 0x1775
+#define mmPIPE5_PG_STATUS 0x1776
+#define mmDC_IP_REQUEST_CNTL 0x1778
+#define mmDC_PGFSM_CONFIG_REG 0x177c
+#define mmDC_PGFSM_WRITE_REG 0x177d
+#define mmDC_PGCNTL_STATUS_REG 0x177e
+#define mmDCPG_TEST_DEBUG_INDEX 0x1779
+#define mmDCPG_TEST_DEBUG_DATA 0x177b
+#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628
+#define mmBL1_PWM_USER_LEVEL 0x1629
+#define mmBL1_PWM_TARGET_ABM_LEVEL 0x162a
+#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x162b
+#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c
+#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162d
+#define mmBL1_PWM_ABM_CNTL 0x162e
+#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162f
+#define mmBL1_PWM_GRP2_REG_LOCK 0x1630
+#define mmDC_ABM1_CNTL 0x1638
+#define mmDC_ABM1_IPCSC_COEFF_SEL 0x1639
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163a
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163b
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163c
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163d
+#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163e
+#define mmDC_ABM1_ACE_THRES_12 0x163f
+#define mmDC_ABM1_ACE_THRES_34 0x1640
+#define mmDC_ABM1_ACE_CNTL_MISC 0x1641
+#define mmDC_ABM1_DEBUG_MISC 0x1649
+#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164a
+#define mmDC_ABM1_HG_MISC_CTRL 0x164b
+#define mmDC_ABM1_LS_SUM_OF_LUMA 0x164c
+#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x164d
+#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164e
+#define mmDC_ABM1_LS_PIXEL_COUNT 0x164f
+#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650
+#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651
+#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652
+#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653
+#define mmDC_ABM1_HG_SAMPLE_RATE 0x1654
+#define mmDC_ABM1_LS_SAMPLE_RATE 0x1655
+#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656
+#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657
+#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658
+#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659
+#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165a
+#define mmDC_ABM1_HG_RESULT_1 0x165b
+#define mmDC_ABM1_HG_RESULT_2 0x165c
+#define mmDC_ABM1_HG_RESULT_3 0x165d
+#define mmDC_ABM1_HG_RESULT_4 0x165e
+#define mmDC_ABM1_HG_RESULT_5 0x165f
+#define mmDC_ABM1_HG_RESULT_6 0x1660
+#define mmDC_ABM1_HG_RESULT_7 0x1661
+#define mmDC_ABM1_HG_RESULT_8 0x1662
+#define mmDC_ABM1_HG_RESULT_9 0x1663
+#define mmDC_ABM1_HG_RESULT_10 0x1664
+#define mmDC_ABM1_HG_RESULT_11 0x1665
+#define mmDC_ABM1_HG_RESULT_12 0x1666
+#define mmDC_ABM1_HG_RESULT_13 0x1667
+#define mmDC_ABM1_HG_RESULT_14 0x1668
+#define mmDC_ABM1_HG_RESULT_15 0x1669
+#define mmDC_ABM1_HG_RESULT_16 0x166a
+#define mmDC_ABM1_HG_RESULT_17 0x166b
+#define mmDC_ABM1_HG_RESULT_18 0x166c
+#define mmDC_ABM1_HG_RESULT_19 0x166d
+#define mmDC_ABM1_HG_RESULT_20 0x166e
+#define mmDC_ABM1_HG_RESULT_21 0x166f
+#define mmDC_ABM1_HG_RESULT_22 0x1670
+#define mmDC_ABM1_HG_RESULT_23 0x1671
+#define mmDC_ABM1_HG_RESULT_24 0x1672
+#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169b
+#define mmDC_ABM1_BL_MASTER_LOCK 0x169c
+#define mmABM_TEST_DEBUG_INDEX 0x169e
+#define mmABM_TEST_DEBUG_DATA 0x169f
+#define mmCRTC_DCFE_CLOCK_CONTROL 0x1b7c
+#define mmCRTC0_CRTC_DCFE_CLOCK_CONTROL 0x1b7c
+#define mmCRTC1_CRTC_DCFE_CLOCK_CONTROL 0x1e7c
+#define mmCRTC2_CRTC_DCFE_CLOCK_CONTROL 0x417c
+#define mmCRTC3_CRTC_DCFE_CLOCK_CONTROL 0x447c
+#define mmCRTC4_CRTC_DCFE_CLOCK_CONTROL 0x477c
+#define mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 0x4a7c
+#define mmCRTC_H_BLANK_EARLY_NUM 0x1b7d
+#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1b7d
+#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1e7d
+#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x417d
+#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x447d
+#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x477d
+#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x4a7d
+#define mmDCFE_DBG_SEL 0x1b7e
+#define mmCRTC0_DCFE_DBG_SEL 0x1b7e
+#define mmCRTC1_DCFE_DBG_SEL 0x1e7e
+#define mmCRTC2_DCFE_DBG_SEL 0x417e
+#define mmCRTC3_DCFE_DBG_SEL 0x447e
+#define mmCRTC4_DCFE_DBG_SEL 0x477e
+#define mmCRTC5_DCFE_DBG_SEL 0x4a7e
+#define mmDCFE_MEM_LIGHT_SLEEP_CNTL 0x1b7f
+#define mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1b7f
+#define mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1e7f
+#define mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL 0x417f
+#define mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL 0x447f
+#define mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL 0x477f
+#define mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL 0x4a7f
+#define mmCRTC_H_TOTAL 0x1b80
+#define mmCRTC0_CRTC_H_TOTAL 0x1b80
+#define mmCRTC1_CRTC_H_TOTAL 0x1e80
+#define mmCRTC2_CRTC_H_TOTAL 0x4180
+#define mmCRTC3_CRTC_H_TOTAL 0x4480
+#define mmCRTC4_CRTC_H_TOTAL 0x4780
+#define mmCRTC5_CRTC_H_TOTAL 0x4a80
+#define mmCRTC_H_BLANK_START_END 0x1b81
+#define mmCRTC0_CRTC_H_BLANK_START_END 0x1b81
+#define mmCRTC1_CRTC_H_BLANK_START_END 0x1e81
+#define mmCRTC2_CRTC_H_BLANK_START_END 0x4181
+#define mmCRTC3_CRTC_H_BLANK_START_END 0x4481
+#define mmCRTC4_CRTC_H_BLANK_START_END 0x4781
+#define mmCRTC5_CRTC_H_BLANK_START_END 0x4a81
+#define mmCRTC_H_SYNC_A 0x1b82
+#define mmCRTC0_CRTC_H_SYNC_A 0x1b82
+#define mmCRTC1_CRTC_H_SYNC_A 0x1e82
+#define mmCRTC2_CRTC_H_SYNC_A 0x4182
+#define mmCRTC3_CRTC_H_SYNC_A 0x4482
+#define mmCRTC4_CRTC_H_SYNC_A 0x4782
+#define mmCRTC5_CRTC_H_SYNC_A 0x4a82
+#define mmCRTC_H_SYNC_A_CNTL 0x1b83
+#define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1b83
+#define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1e83
+#define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x4183
+#define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4483
+#define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4783
+#define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4a83
+#define mmCRTC_H_SYNC_B 0x1b84
+#define mmCRTC0_CRTC_H_SYNC_B 0x1b84
+#define mmCRTC1_CRTC_H_SYNC_B 0x1e84
+#define mmCRTC2_CRTC_H_SYNC_B 0x4184
+#define mmCRTC3_CRTC_H_SYNC_B 0x4484
+#define mmCRTC4_CRTC_H_SYNC_B 0x4784
+#define mmCRTC5_CRTC_H_SYNC_B 0x4a84
+#define mmCRTC_H_SYNC_B_CNTL 0x1b85
+#define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1b85
+#define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1e85
+#define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x4185
+#define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4485
+#define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4785
+#define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4a85
+#define mmCRTC_VBI_END 0x1b86
+#define mmCRTC0_CRTC_VBI_END 0x1b86
+#define mmCRTC1_CRTC_VBI_END 0x1e86
+#define mmCRTC2_CRTC_VBI_END 0x4186
+#define mmCRTC3_CRTC_VBI_END 0x4486
+#define mmCRTC4_CRTC_VBI_END 0x4786
+#define mmCRTC5_CRTC_VBI_END 0x4a86
+#define mmCRTC_V_TOTAL 0x1b87
+#define mmCRTC0_CRTC_V_TOTAL 0x1b87
+#define mmCRTC1_CRTC_V_TOTAL 0x1e87
+#define mmCRTC2_CRTC_V_TOTAL 0x4187
+#define mmCRTC3_CRTC_V_TOTAL 0x4487
+#define mmCRTC4_CRTC_V_TOTAL 0x4787
+#define mmCRTC5_CRTC_V_TOTAL 0x4a87
+#define mmCRTC_V_TOTAL_MIN 0x1b88
+#define mmCRTC0_CRTC_V_TOTAL_MIN 0x1b88
+#define mmCRTC1_CRTC_V_TOTAL_MIN 0x1e88
+#define mmCRTC2_CRTC_V_TOTAL_MIN 0x4188
+#define mmCRTC3_CRTC_V_TOTAL_MIN 0x4488
+#define mmCRTC4_CRTC_V_TOTAL_MIN 0x4788
+#define mmCRTC5_CRTC_V_TOTAL_MIN 0x4a88
+#define mmCRTC_V_TOTAL_MAX 0x1b89
+#define mmCRTC0_CRTC_V_TOTAL_MAX 0x1b89
+#define mmCRTC1_CRTC_V_TOTAL_MAX 0x1e89
+#define mmCRTC2_CRTC_V_TOTAL_MAX 0x4189
+#define mmCRTC3_CRTC_V_TOTAL_MAX 0x4489
+#define mmCRTC4_CRTC_V_TOTAL_MAX 0x4789
+#define mmCRTC5_CRTC_V_TOTAL_MAX 0x4a89
+#define mmCRTC_V_TOTAL_CONTROL 0x1b8a
+#define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1b8a
+#define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1e8a
+#define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x418a
+#define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x448a
+#define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x478a
+#define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x4a8a
+#define mmCRTC_V_TOTAL_INT_STATUS 0x1b8b
+#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1b8b
+#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1e8b
+#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x418b
+#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x448b
+#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x478b
+#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x4a8b
+#define mmCRTC_VSYNC_NOM_INT_STATUS 0x1b8c
+#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1b8c
+#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1e8c
+#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x418c
+#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x448c
+#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x478c
+#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x4a8c
+#define mmCRTC_V_BLANK_START_END 0x1b8d
+#define mmCRTC0_CRTC_V_BLANK_START_END 0x1b8d
+#define mmCRTC1_CRTC_V_BLANK_START_END 0x1e8d
+#define mmCRTC2_CRTC_V_BLANK_START_END 0x418d
+#define mmCRTC3_CRTC_V_BLANK_START_END 0x448d
+#define mmCRTC4_CRTC_V_BLANK_START_END 0x478d
+#define mmCRTC5_CRTC_V_BLANK_START_END 0x4a8d
+#define mmCRTC_V_SYNC_A 0x1b8e
+#define mmCRTC0_CRTC_V_SYNC_A 0x1b8e
+#define mmCRTC1_CRTC_V_SYNC_A 0x1e8e
+#define mmCRTC2_CRTC_V_SYNC_A 0x418e
+#define mmCRTC3_CRTC_V_SYNC_A 0x448e
+#define mmCRTC4_CRTC_V_SYNC_A 0x478e
+#define mmCRTC5_CRTC_V_SYNC_A 0x4a8e
+#define mmCRTC_V_SYNC_A_CNTL 0x1b8f
+#define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1b8f
+#define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1e8f
+#define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x418f
+#define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x448f
+#define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x478f
+#define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x4a8f
+#define mmCRTC_V_SYNC_B 0x1b90
+#define mmCRTC0_CRTC_V_SYNC_B 0x1b90
+#define mmCRTC1_CRTC_V_SYNC_B 0x1e90
+#define mmCRTC2_CRTC_V_SYNC_B 0x4190
+#define mmCRTC3_CRTC_V_SYNC_B 0x4490
+#define mmCRTC4_CRTC_V_SYNC_B 0x4790
+#define mmCRTC5_CRTC_V_SYNC_B 0x4a90
+#define mmCRTC_V_SYNC_B_CNTL 0x1b91
+#define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1b91
+#define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1e91
+#define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x4191
+#define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4491
+#define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4791
+#define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4a91
+#define mmCRTC_DTMTEST_CNTL 0x1b92
+#define mmCRTC0_CRTC_DTMTEST_CNTL 0x1b92
+#define mmCRTC1_CRTC_DTMTEST_CNTL 0x1e92
+#define mmCRTC2_CRTC_DTMTEST_CNTL 0x4192
+#define mmCRTC3_CRTC_DTMTEST_CNTL 0x4492
+#define mmCRTC4_CRTC_DTMTEST_CNTL 0x4792
+#define mmCRTC5_CRTC_DTMTEST_CNTL 0x4a92
+#define mmCRTC_DTMTEST_STATUS_POSITION 0x1b93
+#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1b93
+#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1e93
+#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x4193
+#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4493
+#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4793
+#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4a93
+#define mmCRTC_TRIGA_CNTL 0x1b94
+#define mmCRTC0_CRTC_TRIGA_CNTL 0x1b94
+#define mmCRTC1_CRTC_TRIGA_CNTL 0x1e94
+#define mmCRTC2_CRTC_TRIGA_CNTL 0x4194
+#define mmCRTC3_CRTC_TRIGA_CNTL 0x4494
+#define mmCRTC4_CRTC_TRIGA_CNTL 0x4794
+#define mmCRTC5_CRTC_TRIGA_CNTL 0x4a94
+#define mmCRTC_TRIGA_MANUAL_TRIG 0x1b95
+#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1b95
+#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1e95
+#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x4195
+#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4495
+#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4795
+#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4a95
+#define mmCRTC_TRIGB_CNTL 0x1b96
+#define mmCRTC0_CRTC_TRIGB_CNTL 0x1b96
+#define mmCRTC1_CRTC_TRIGB_CNTL 0x1e96
+#define mmCRTC2_CRTC_TRIGB_CNTL 0x4196
+#define mmCRTC3_CRTC_TRIGB_CNTL 0x4496
+#define mmCRTC4_CRTC_TRIGB_CNTL 0x4796
+#define mmCRTC5_CRTC_TRIGB_CNTL 0x4a96
+#define mmCRTC_TRIGB_MANUAL_TRIG 0x1b97
+#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1b97
+#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1e97
+#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x4197
+#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4497
+#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4797
+#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4a97
+#define mmCRTC_FORCE_COUNT_NOW_CNTL 0x1b98
+#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1b98
+#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1e98
+#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x4198
+#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4498
+#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4798
+#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4a98
+#define mmCRTC_FLOW_CONTROL 0x1b99
+#define mmCRTC0_CRTC_FLOW_CONTROL 0x1b99
+#define mmCRTC1_CRTC_FLOW_CONTROL 0x1e99
+#define mmCRTC2_CRTC_FLOW_CONTROL 0x4199
+#define mmCRTC3_CRTC_FLOW_CONTROL 0x4499
+#define mmCRTC4_CRTC_FLOW_CONTROL 0x4799
+#define mmCRTC5_CRTC_FLOW_CONTROL 0x4a99
+#define mmCRTC_STEREO_FORCE_NEXT_EYE 0x1b9b
+#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1b9b
+#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1e9b
+#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x419b
+#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x449b
+#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x479b
+#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x4a9b
+#define mmCRTC_CONTROL 0x1b9c
+#define mmCRTC0_CRTC_CONTROL 0x1b9c
+#define mmCRTC1_CRTC_CONTROL 0x1e9c
+#define mmCRTC2_CRTC_CONTROL 0x419c
+#define mmCRTC3_CRTC_CONTROL 0x449c
+#define mmCRTC4_CRTC_CONTROL 0x479c
+#define mmCRTC5_CRTC_CONTROL 0x4a9c
+#define mmCRTC_BLANK_CONTROL 0x1b9d
+#define mmCRTC0_CRTC_BLANK_CONTROL 0x1b9d
+#define mmCRTC1_CRTC_BLANK_CONTROL 0x1e9d
+#define mmCRTC2_CRTC_BLANK_CONTROL 0x419d
+#define mmCRTC3_CRTC_BLANK_CONTROL 0x449d
+#define mmCRTC4_CRTC_BLANK_CONTROL 0x479d
+#define mmCRTC5_CRTC_BLANK_CONTROL 0x4a9d
+#define mmCRTC_INTERLACE_CONTROL 0x1b9e
+#define mmCRTC0_CRTC_INTERLACE_CONTROL 0x1b9e
+#define mmCRTC1_CRTC_INTERLACE_CONTROL 0x1e9e
+#define mmCRTC2_CRTC_INTERLACE_CONTROL 0x419e
+#define mmCRTC3_CRTC_INTERLACE_CONTROL 0x449e
+#define mmCRTC4_CRTC_INTERLACE_CONTROL 0x479e
+#define mmCRTC5_CRTC_INTERLACE_CONTROL 0x4a9e
+#define mmCRTC_INTERLACE_STATUS 0x1b9f
+#define mmCRTC0_CRTC_INTERLACE_STATUS 0x1b9f
+#define mmCRTC1_CRTC_INTERLACE_STATUS 0x1e9f
+#define mmCRTC2_CRTC_INTERLACE_STATUS 0x419f
+#define mmCRTC3_CRTC_INTERLACE_STATUS 0x449f
+#define mmCRTC4_CRTC_INTERLACE_STATUS 0x479f
+#define mmCRTC5_CRTC_INTERLACE_STATUS 0x4a9f
+#define mmCRTC_FIELD_INDICATION_CONTROL 0x1ba0
+#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x1ba0
+#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x1ea0
+#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x41a0
+#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x44a0
+#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x47a0
+#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x4aa0
+#define mmCRTC_PIXEL_DATA_READBACK0 0x1ba1
+#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x1ba1
+#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x1ea1
+#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x41a1
+#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x44a1
+#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x47a1
+#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x4aa1
+#define mmCRTC_PIXEL_DATA_READBACK1 0x1ba2
+#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x1ba2
+#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x1ea2
+#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x41a2
+#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x44a2
+#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x47a2
+#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x4aa2
+#define mmCRTC_STATUS 0x1ba3
+#define mmCRTC0_CRTC_STATUS 0x1ba3
+#define mmCRTC1_CRTC_STATUS 0x1ea3
+#define mmCRTC2_CRTC_STATUS 0x41a3
+#define mmCRTC3_CRTC_STATUS 0x44a3
+#define mmCRTC4_CRTC_STATUS 0x47a3
+#define mmCRTC5_CRTC_STATUS 0x4aa3
+#define mmCRTC_STATUS_POSITION 0x1ba4
+#define mmCRTC0_CRTC_STATUS_POSITION 0x1ba4
+#define mmCRTC1_CRTC_STATUS_POSITION 0x1ea4
+#define mmCRTC2_CRTC_STATUS_POSITION 0x41a4
+#define mmCRTC3_CRTC_STATUS_POSITION 0x44a4
+#define mmCRTC4_CRTC_STATUS_POSITION 0x47a4
+#define mmCRTC5_CRTC_STATUS_POSITION 0x4aa4
+#define mmCRTC_NOM_VERT_POSITION 0x1ba5
+#define mmCRTC0_CRTC_NOM_VERT_POSITION 0x1ba5
+#define mmCRTC1_CRTC_NOM_VERT_POSITION 0x1ea5
+#define mmCRTC2_CRTC_NOM_VERT_POSITION 0x41a5
+#define mmCRTC3_CRTC_NOM_VERT_POSITION 0x44a5
+#define mmCRTC4_CRTC_NOM_VERT_POSITION 0x47a5
+#define mmCRTC5_CRTC_NOM_VERT_POSITION 0x4aa5
+#define mmCRTC_STATUS_FRAME_COUNT 0x1ba6
+#define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1ba6
+#define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1ea6
+#define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x41a6
+#define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x44a6
+#define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x47a6
+#define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x4aa6
+#define mmCRTC_STATUS_VF_COUNT 0x1ba7
+#define mmCRTC0_CRTC_STATUS_VF_COUNT 0x1ba7
+#define mmCRTC1_CRTC_STATUS_VF_COUNT 0x1ea7
+#define mmCRTC2_CRTC_STATUS_VF_COUNT 0x41a7
+#define mmCRTC3_CRTC_STATUS_VF_COUNT 0x44a7
+#define mmCRTC4_CRTC_STATUS_VF_COUNT 0x47a7
+#define mmCRTC5_CRTC_STATUS_VF_COUNT 0x4aa7
+#define mmCRTC_STATUS_HV_COUNT 0x1ba8
+#define mmCRTC0_CRTC_STATUS_HV_COUNT 0x1ba8
+#define mmCRTC1_CRTC_STATUS_HV_COUNT 0x1ea8
+#define mmCRTC2_CRTC_STATUS_HV_COUNT 0x41a8
+#define mmCRTC3_CRTC_STATUS_HV_COUNT 0x44a8
+#define mmCRTC4_CRTC_STATUS_HV_COUNT 0x47a8
+#define mmCRTC5_CRTC_STATUS_HV_COUNT 0x4aa8
+#define mmCRTC_COUNT_CONTROL 0x1ba9
+#define mmCRTC0_CRTC_COUNT_CONTROL 0x1ba9
+#define mmCRTC1_CRTC_COUNT_CONTROL 0x1ea9
+#define mmCRTC2_CRTC_COUNT_CONTROL 0x41a9
+#define mmCRTC3_CRTC_COUNT_CONTROL 0x44a9
+#define mmCRTC4_CRTC_COUNT_CONTROL 0x47a9
+#define mmCRTC5_CRTC_COUNT_CONTROL 0x4aa9
+#define mmCRTC_COUNT_RESET 0x1baa
+#define mmCRTC0_CRTC_COUNT_RESET 0x1baa
+#define mmCRTC1_CRTC_COUNT_RESET 0x1eaa
+#define mmCRTC2_CRTC_COUNT_RESET 0x41aa
+#define mmCRTC3_CRTC_COUNT_RESET 0x44aa
+#define mmCRTC4_CRTC_COUNT_RESET 0x47aa
+#define mmCRTC5_CRTC_COUNT_RESET 0x4aaa
+#define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab
+#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab
+#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1eab
+#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41ab
+#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x44ab
+#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47ab
+#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x4aab
+#define mmCRTC_VERT_SYNC_CONTROL 0x1bac
+#define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1bac
+#define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1eac
+#define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x41ac
+#define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x44ac
+#define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x47ac
+#define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x4aac
+#define mmCRTC_STEREO_STATUS 0x1bad
+#define mmCRTC0_CRTC_STEREO_STATUS 0x1bad
+#define mmCRTC1_CRTC_STEREO_STATUS 0x1ead
+#define mmCRTC2_CRTC_STEREO_STATUS 0x41ad
+#define mmCRTC3_CRTC_STEREO_STATUS 0x44ad
+#define mmCRTC4_CRTC_STEREO_STATUS 0x47ad
+#define mmCRTC5_CRTC_STEREO_STATUS 0x4aad
+#define mmCRTC_STEREO_CONTROL 0x1bae
+#define mmCRTC0_CRTC_STEREO_CONTROL 0x1bae
+#define mmCRTC1_CRTC_STEREO_CONTROL 0x1eae
+#define mmCRTC2_CRTC_STEREO_CONTROL 0x41ae
+#define mmCRTC3_CRTC_STEREO_CONTROL 0x44ae
+#define mmCRTC4_CRTC_STEREO_CONTROL 0x47ae
+#define mmCRTC5_CRTC_STEREO_CONTROL 0x4aae
+#define mmCRTC_SNAPSHOT_STATUS 0x1baf
+#define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1baf
+#define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1eaf
+#define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x41af
+#define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x44af
+#define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x47af
+#define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x4aaf
+#define mmCRTC_SNAPSHOT_CONTROL 0x1bb0
+#define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1bb0
+#define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1eb0
+#define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x41b0
+#define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x44b0
+#define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x47b0
+#define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x4ab0
+#define mmCRTC_SNAPSHOT_POSITION 0x1bb1
+#define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1bb1
+#define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1eb1
+#define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x41b1
+#define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x44b1
+#define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x47b1
+#define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x4ab1
+#define mmCRTC_SNAPSHOT_FRAME 0x1bb2
+#define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1bb2
+#define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1eb2
+#define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x41b2
+#define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x44b2
+#define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x47b2
+#define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x4ab2
+#define mmCRTC_START_LINE_CONTROL 0x1bb3
+#define mmCRTC0_CRTC_START_LINE_CONTROL 0x1bb3
+#define mmCRTC1_CRTC_START_LINE_CONTROL 0x1eb3
+#define mmCRTC2_CRTC_START_LINE_CONTROL 0x41b3
+#define mmCRTC3_CRTC_START_LINE_CONTROL 0x44b3
+#define mmCRTC4_CRTC_START_LINE_CONTROL 0x47b3
+#define mmCRTC5_CRTC_START_LINE_CONTROL 0x4ab3
+#define mmCRTC_INTERRUPT_CONTROL 0x1bb4
+#define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1bb4
+#define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1eb4
+#define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x41b4
+#define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x44b4
+#define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x47b4
+#define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x4ab4
+#define mmCRTC_UPDATE_LOCK 0x1bb5
+#define mmCRTC0_CRTC_UPDATE_LOCK 0x1bb5
+#define mmCRTC1_CRTC_UPDATE_LOCK 0x1eb5
+#define mmCRTC2_CRTC_UPDATE_LOCK 0x41b5
+#define mmCRTC3_CRTC_UPDATE_LOCK 0x44b5
+#define mmCRTC4_CRTC_UPDATE_LOCK 0x47b5
+#define mmCRTC5_CRTC_UPDATE_LOCK 0x4ab5
+#define mmCRTC_DOUBLE_BUFFER_CONTROL 0x1bb6
+#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1bb6
+#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1eb6
+#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x41b6
+#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x44b6
+#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x47b6
+#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x4ab6
+#define mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7
+#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7
+#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1eb7
+#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41b7
+#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x44b7
+#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x47b7
+#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x4ab7
+#define mmCRTC_TEST_PATTERN_CONTROL 0x1bba
+#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba
+#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1eba
+#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x41ba
+#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x44ba
+#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x47ba
+#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x4aba
+#define mmCRTC_TEST_PATTERN_PARAMETERS 0x1bbb
+#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1bbb
+#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1ebb
+#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x41bb
+#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x44bb
+#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x47bb
+#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x4abb
+#define mmCRTC_TEST_PATTERN_COLOR 0x1bbc
+#define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1bbc
+#define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1ebc
+#define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x41bc
+#define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x44bc
+#define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x47bc
+#define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x4abc
+#define mmMASTER_UPDATE_LOCK 0x1bbd
+#define mmCRTC0_MASTER_UPDATE_LOCK 0x1bbd
+#define mmCRTC1_MASTER_UPDATE_LOCK 0x1ebd
+#define mmCRTC2_MASTER_UPDATE_LOCK 0x41bd
+#define mmCRTC3_MASTER_UPDATE_LOCK 0x44bd
+#define mmCRTC4_MASTER_UPDATE_LOCK 0x47bd
+#define mmCRTC5_MASTER_UPDATE_LOCK 0x4abd
+#define mmMASTER_UPDATE_MODE 0x1bbe
+#define mmCRTC0_MASTER_UPDATE_MODE 0x1bbe
+#define mmCRTC1_MASTER_UPDATE_MODE 0x1ebe
+#define mmCRTC2_MASTER_UPDATE_MODE 0x41be
+#define mmCRTC3_MASTER_UPDATE_MODE 0x44be
+#define mmCRTC4_MASTER_UPDATE_MODE 0x47be
+#define mmCRTC5_MASTER_UPDATE_MODE 0x4abe
+#define mmCRTC_MVP_INBAND_CNTL_INSERT 0x1bbf
+#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1bbf
+#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1ebf
+#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x41bf
+#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x44bf
+#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x47bf
+#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x4abf
+#define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0
+#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0
+#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1ec0
+#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41c0
+#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x44c0
+#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x47c0
+#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x4ac0
+#define mmCRTC_MVP_STATUS 0x1bc1
+#define mmCRTC0_CRTC_MVP_STATUS 0x1bc1
+#define mmCRTC1_CRTC_MVP_STATUS 0x1ec1
+#define mmCRTC2_CRTC_MVP_STATUS 0x41c1
+#define mmCRTC3_CRTC_MVP_STATUS 0x44c1
+#define mmCRTC4_CRTC_MVP_STATUS 0x47c1
+#define mmCRTC5_CRTC_MVP_STATUS 0x4ac1
+#define mmCRTC_MASTER_EN 0x1bc2
+#define mmCRTC0_CRTC_MASTER_EN 0x1bc2
+#define mmCRTC1_CRTC_MASTER_EN 0x1ec2
+#define mmCRTC2_CRTC_MASTER_EN 0x41c2
+#define mmCRTC3_CRTC_MASTER_EN 0x44c2
+#define mmCRTC4_CRTC_MASTER_EN 0x47c2
+#define mmCRTC5_CRTC_MASTER_EN 0x4ac2
+#define mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3
+#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3
+#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1ec3
+#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x41c3
+#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x44c3
+#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x47c3
+#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x4ac3
+#define mmCRTC_V_UPDATE_INT_STATUS 0x1bc4
+#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1bc4
+#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1ec4
+#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x41c4
+#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x44c4
+#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x47c4
+#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x4ac4
+#define mmCRTC_OVERSCAN_COLOR 0x1bc8
+#define mmCRTC0_CRTC_OVERSCAN_COLOR 0x1bc8
+#define mmCRTC1_CRTC_OVERSCAN_COLOR 0x1ec8
+#define mmCRTC2_CRTC_OVERSCAN_COLOR 0x41c8
+#define mmCRTC3_CRTC_OVERSCAN_COLOR 0x44c8
+#define mmCRTC4_CRTC_OVERSCAN_COLOR 0x47c8
+#define mmCRTC5_CRTC_OVERSCAN_COLOR 0x4ac8
+#define mmCRTC_OVERSCAN_COLOR_EXT 0x1bc9
+#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x1bc9
+#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x1ec9
+#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x41c9
+#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x44c9
+#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x47c9
+#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x4ac9
+#define mmCRTC_BLANK_DATA_COLOR 0x1bca
+#define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1bca
+#define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1eca
+#define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x41ca
+#define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x44ca
+#define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x47ca
+#define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x4aca
+#define mmCRTC_BLANK_DATA_COLOR_EXT 0x1bcb
+#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x1bcb
+#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x1ecb
+#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x41cb
+#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x44cb
+#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x47cb
+#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x4acb
+#define mmCRTC_BLACK_COLOR 0x1bcc
+#define mmCRTC0_CRTC_BLACK_COLOR 0x1bcc
+#define mmCRTC1_CRTC_BLACK_COLOR 0x1ecc
+#define mmCRTC2_CRTC_BLACK_COLOR 0x41cc
+#define mmCRTC3_CRTC_BLACK_COLOR 0x44cc
+#define mmCRTC4_CRTC_BLACK_COLOR 0x47cc
+#define mmCRTC5_CRTC_BLACK_COLOR 0x4acc
+#define mmCRTC_BLACK_COLOR_EXT 0x1bcd
+#define mmCRTC0_CRTC_BLACK_COLOR_EXT 0x1bcd
+#define mmCRTC1_CRTC_BLACK_COLOR_EXT 0x1ecd
+#define mmCRTC2_CRTC_BLACK_COLOR_EXT 0x41cd
+#define mmCRTC3_CRTC_BLACK_COLOR_EXT 0x44cd
+#define mmCRTC4_CRTC_BLACK_COLOR_EXT 0x47cd
+#define mmCRTC5_CRTC_BLACK_COLOR_EXT 0x4acd
+#define mmCRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1ece
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x41ce
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x44ce
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x47ce
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x4ace
+#define mmCRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1ecf
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x41cf
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x44cf
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x47cf
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x4acf
+#define mmCRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1ed0
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x41d0
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x44d0
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x47d0
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x4ad0
+#define mmCRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1ed1
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x41d1
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x44d1
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x47d1
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x4ad1
+#define mmCRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1ed2
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x41d2
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x44d2
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x47d2
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x4ad2
+#define mmCRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3
+#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3
+#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1ed3
+#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x41d3
+#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x44d3
+#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x47d3
+#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x4ad3
+#define mmCRTC_CRC_CNTL 0x1bd4
+#define mmCRTC0_CRTC_CRC_CNTL 0x1bd4
+#define mmCRTC1_CRTC_CRC_CNTL 0x1ed4
+#define mmCRTC2_CRTC_CRC_CNTL 0x41d4
+#define mmCRTC3_CRTC_CRC_CNTL 0x44d4
+#define mmCRTC4_CRTC_CRC_CNTL 0x47d4
+#define mmCRTC5_CRTC_CRC_CNTL 0x4ad4
+#define mmCRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5
+#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5
+#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x1ed5
+#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x41d5
+#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x44d5
+#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x47d5
+#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x4ad5
+#define mmCRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6
+#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6
+#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1ed6
+#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x41d6
+#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x44d6
+#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x47d6
+#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x4ad6
+#define mmCRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7
+#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7
+#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x1ed7
+#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x41d7
+#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x44d7
+#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x47d7
+#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x4ad7
+#define mmCRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8
+#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8
+#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1ed8
+#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x41d8
+#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x44d8
+#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x47d8
+#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x4ad8
+#define mmCRTC_CRC0_DATA_RG 0x1bd9
+#define mmCRTC0_CRTC_CRC0_DATA_RG 0x1bd9
+#define mmCRTC1_CRTC_CRC0_DATA_RG 0x1ed9
+#define mmCRTC2_CRTC_CRC0_DATA_RG 0x41d9
+#define mmCRTC3_CRTC_CRC0_DATA_RG 0x44d9
+#define mmCRTC4_CRTC_CRC0_DATA_RG 0x47d9
+#define mmCRTC5_CRTC_CRC0_DATA_RG 0x4ad9
+#define mmCRTC_CRC0_DATA_B 0x1bda
+#define mmCRTC0_CRTC_CRC0_DATA_B 0x1bda
+#define mmCRTC1_CRTC_CRC0_DATA_B 0x1eda
+#define mmCRTC2_CRTC_CRC0_DATA_B 0x41da
+#define mmCRTC3_CRTC_CRC0_DATA_B 0x44da
+#define mmCRTC4_CRTC_CRC0_DATA_B 0x47da
+#define mmCRTC5_CRTC_CRC0_DATA_B 0x4ada
+#define mmCRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb
+#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb
+#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x1edb
+#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x41db
+#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x44db
+#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x47db
+#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x4adb
+#define mmCRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc
+#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc
+#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1edc
+#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x41dc
+#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x44dc
+#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x47dc
+#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x4adc
+#define mmCRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd
+#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd
+#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x1edd
+#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x41dd
+#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x44dd
+#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x47dd
+#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x4add
+#define mmCRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde
+#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde
+#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1ede
+#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x41de
+#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x44de
+#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x47de
+#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x4ade
+#define mmCRTC_CRC1_DATA_RG 0x1bdf
+#define mmCRTC0_CRTC_CRC1_DATA_RG 0x1bdf
+#define mmCRTC1_CRTC_CRC1_DATA_RG 0x1edf
+#define mmCRTC2_CRTC_CRC1_DATA_RG 0x41df
+#define mmCRTC3_CRTC_CRC1_DATA_RG 0x44df
+#define mmCRTC4_CRTC_CRC1_DATA_RG 0x47df
+#define mmCRTC5_CRTC_CRC1_DATA_RG 0x4adf
+#define mmCRTC_CRC1_DATA_B 0x1be0
+#define mmCRTC0_CRTC_CRC1_DATA_B 0x1be0
+#define mmCRTC1_CRTC_CRC1_DATA_B 0x1ee0
+#define mmCRTC2_CRTC_CRC1_DATA_B 0x41e0
+#define mmCRTC3_CRTC_CRC1_DATA_B 0x44e0
+#define mmCRTC4_CRTC_CRC1_DATA_B 0x47e0
+#define mmCRTC5_CRTC_CRC1_DATA_B 0x4ae0
+#define mmCRTC_EXT_TIMING_SYNC_CONTROL 0x1be1
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL 0x1be1
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL 0x1ee1
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL 0x41e1
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL 0x44e1
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL 0x47e1
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL 0x4ae1
+#define mmCRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1ee2
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x41e2
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x44e2
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x47e2
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x4ae2
+#define mmCRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1ee3
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x41e3
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x44e3
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x47e3
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x4ae3
+#define mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1ee4
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x41e4
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x44e4
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x47e4
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x4ae4
+#define mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1ee5
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x41e5
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x44e5
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x47e5
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x4ae5
+#define mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6
+#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6
+#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1ee6
+#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x41e6
+#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x44e6
+#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x47e6
+#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x4ae6
+#define mmCRTC_STATIC_SCREEN_CONTROL 0x1be7
+#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x1be7
+#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x1ee7
+#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x41e7
+#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x44e7
+#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x47e7
+#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x4ae7
+#define mmCRTC_3D_STRUCTURE_CONTROL 0x1b78
+#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1b78
+#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1e78
+#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x4178
+#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4478
+#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4778
+#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4a78
+#define mmCRTC_GSL_VSYNC_GAP 0x1b79
+#define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1b79
+#define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1e79
+#define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x4179
+#define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4479
+#define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4779
+#define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4a79
+#define mmCRTC_GSL_WINDOW 0x1b7a
+#define mmCRTC0_CRTC_GSL_WINDOW 0x1b7a
+#define mmCRTC1_CRTC_GSL_WINDOW 0x1e7a
+#define mmCRTC2_CRTC_GSL_WINDOW 0x417a
+#define mmCRTC3_CRTC_GSL_WINDOW 0x447a
+#define mmCRTC4_CRTC_GSL_WINDOW 0x477a
+#define mmCRTC5_CRTC_GSL_WINDOW 0x4a7a
+#define mmCRTC_GSL_CONTROL 0x1b7b
+#define mmCRTC0_CRTC_GSL_CONTROL 0x1b7b
+#define mmCRTC1_CRTC_GSL_CONTROL 0x1e7b
+#define mmCRTC2_CRTC_GSL_CONTROL 0x417b
+#define mmCRTC3_CRTC_GSL_CONTROL 0x447b
+#define mmCRTC4_CRTC_GSL_CONTROL 0x477b
+#define mmCRTC5_CRTC_GSL_CONTROL 0x4a7b
+#define mmCRTC_TEST_DEBUG_INDEX 0x1bc6
+#define mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1bc6
+#define mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1ec6
+#define mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x41c6
+#define mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x44c6
+#define mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x47c6
+#define mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x4ac6
+#define mmCRTC_TEST_DEBUG_DATA 0x1bc7
+#define mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1bc7
+#define mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1ec7
+#define mmCRTC2_CRTC_TEST_DEBUG_DATA 0x41c7
+#define mmCRTC3_CRTC_TEST_DEBUG_DATA 0x44c7
+#define mmCRTC4_CRTC_TEST_DEBUG_DATA 0x47c7
+#define mmCRTC5_CRTC_TEST_DEBUG_DATA 0x4ac7
+#define mmDAC_ENABLE 0x19e4
+#define mmDAC_SOURCE_SELECT 0x19e5
+#define mmDAC_CRC_EN 0x19e6
+#define mmDAC_CRC_CONTROL 0x19e7
+#define mmDAC_CRC_SIG_RGB_MASK 0x19e8
+#define mmDAC_CRC_SIG_CONTROL_MASK 0x19e9
+#define mmDAC_CRC_SIG_RGB 0x19ea
+#define mmDAC_CRC_SIG_CONTROL 0x19eb
+#define mmDAC_SYNC_TRISTATE_CONTROL 0x19ec
+#define mmDAC_STEREOSYNC_SELECT 0x19ed
+#define mmDAC_AUTODETECT_CONTROL 0x19ee
+#define mmDAC_AUTODETECT_CONTROL2 0x19ef
+#define mmDAC_AUTODETECT_CONTROL3 0x19f0
+#define mmDAC_AUTODETECT_STATUS 0x19f1
+#define mmDAC_AUTODETECT_INT_CONTROL 0x19f2
+#define mmDAC_FORCE_OUTPUT_CNTL 0x19f3
+#define mmDAC_FORCE_DATA 0x19f4
+#define mmDAC_POWERDOWN 0x19f5
+#define mmDAC_CONTROL 0x19f6
+#define mmDAC_COMPARATOR_ENABLE 0x19f7
+#define mmDAC_COMPARATOR_OUTPUT 0x19f8
+#define mmDAC_PWR_CNTL 0x19f9
+#define mmDAC_DFT_CONFIG 0x19fa
+#define mmDAC_FIFO_STATUS 0x19fb
+#define mmPERFCOUNTER_CNTL 0x170
+#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x170
+#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x1870
+#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x1b24
+#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x1e24
+#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x4124
+#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x4424
+#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x4724
+#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x4a24
+#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x4c40
+#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x4d14
+#define mmPERFCOUNTER_STATE 0x171
+#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x171
+#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x1871
+#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x1b25
+#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x1e25
+#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x4125
+#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x4425
+#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x4725
+#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x4a25
+#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x4c41
+#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x4d15
+#define mmPERFMON_CNTL 0x173
+#define mmDC_PERFMON0_PERFMON_CNTL 0x173
+#define mmDC_PERFMON1_PERFMON_CNTL 0x1873
+#define mmDC_PERFMON2_PERFMON_CNTL 0x1b27
+#define mmDC_PERFMON3_PERFMON_CNTL 0x1e27
+#define mmDC_PERFMON4_PERFMON_CNTL 0x4127
+#define mmDC_PERFMON5_PERFMON_CNTL 0x4427
+#define mmDC_PERFMON6_PERFMON_CNTL 0x4727
+#define mmDC_PERFMON7_PERFMON_CNTL 0x4a27
+#define mmDC_PERFMON8_PERFMON_CNTL 0x4c43
+#define mmDC_PERFMON9_PERFMON_CNTL 0x4d17
+#define mmPERFMON_CVALUE_INT_MISC 0x172
+#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x172
+#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x1872
+#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x1b26
+#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x1e26
+#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x4126
+#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x4426
+#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x4726
+#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x4a26
+#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x4c42
+#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x4d16
+#define mmPERFMON_CVALUE_LOW 0x174
+#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x174
+#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x1874
+#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x1b28
+#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x1e28
+#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x4128
+#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x4428
+#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x4728
+#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x4a28
+#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x4c44
+#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x4d18
+#define mmPERFMON_HI 0x175
+#define mmDC_PERFMON0_PERFMON_HI 0x175
+#define mmDC_PERFMON1_PERFMON_HI 0x1875
+#define mmDC_PERFMON2_PERFMON_HI 0x1b29
+#define mmDC_PERFMON3_PERFMON_HI 0x1e29
+#define mmDC_PERFMON4_PERFMON_HI 0x4129
+#define mmDC_PERFMON5_PERFMON_HI 0x4429
+#define mmDC_PERFMON6_PERFMON_HI 0x4729
+#define mmDC_PERFMON7_PERFMON_HI 0x4a29
+#define mmDC_PERFMON8_PERFMON_HI 0x4c45
+#define mmDC_PERFMON9_PERFMON_HI 0x4d19
+#define mmPERFMON_LOW 0x176
+#define mmDC_PERFMON0_PERFMON_LOW 0x176
+#define mmDC_PERFMON1_PERFMON_LOW 0x1876
+#define mmDC_PERFMON2_PERFMON_LOW 0x1b2a
+#define mmDC_PERFMON3_PERFMON_LOW 0x1e2a
+#define mmDC_PERFMON4_PERFMON_LOW 0x412a
+#define mmDC_PERFMON5_PERFMON_LOW 0x442a
+#define mmDC_PERFMON6_PERFMON_LOW 0x472a
+#define mmDC_PERFMON7_PERFMON_LOW 0x4a2a
+#define mmDC_PERFMON8_PERFMON_LOW 0x4c46
+#define mmDC_PERFMON9_PERFMON_LOW 0x4d1a
+#define mmPERFMON_TEST_DEBUG_INDEX 0x177
+#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX 0x177
+#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX 0x1877
+#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX 0x1b2b
+#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX 0x1e2b
+#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX 0x412b
+#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX 0x442b
+#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX 0x472b
+#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX 0x4a2b
+#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX 0x4c47
+#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX 0x4d1b
+#define mmPERFMON_TEST_DEBUG_DATA 0x178
+#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA 0x178
+#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA 0x1878
+#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA 0x1b2c
+#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA 0x1e2c
+#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA 0x412c
+#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA 0x442c
+#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA 0x472c
+#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA 0x4a2c
+#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA 0x4c48
+#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA 0x4d1c
+#define mmVGA25_PPLL_REF_DIV 0xd8
+#define mmVGA28_PPLL_REF_DIV 0xd9
+#define mmVGA41_PPLL_REF_DIV 0xda
+#define mmVGA25_PPLL_FB_DIV 0xdc
+#define mmVGA28_PPLL_FB_DIV 0xdd
+#define mmVGA41_PPLL_FB_DIV 0xde
+#define mmVGA25_PPLL_POST_DIV 0xe0
+#define mmVGA28_PPLL_POST_DIV 0xe1
+#define mmVGA41_PPLL_POST_DIV 0xe2
+#define mmVGA25_PPLL_ANALOG 0xe4
+#define mmVGA28_PPLL_ANALOG 0xe5
+#define mmVGA41_PPLL_ANALOG 0xe6
+#define mmDPREFCLK_CNTL 0x118
+#define mmSCANIN_SOFT_RESET 0x11e
+#define mmDCCG_GTC_CNTL 0x120
+#define mmDCCG_GTC_DTO_INCR 0x121
+#define mmDCCG_GTC_DTO_MODULO 0x122
+#define mmDCCG_GTC_CURRENT 0x123
+#define mmDCCG_DS_DTO_INCR 0x113
+#define mmDCCG_DS_DTO_MODULO 0x114
+#define mmDCCG_DS_CNTL 0x115
+#define mmDCCG_DS_HW_CAL_INTERVAL 0x116
+#define mmDCCG_DS_DEBUG_CNTL 0x112
+#define mmDMCU_SMU_INTERRUPT_CNTL 0x12c
+#define mmSMU_CONTROL 0x12d
+#define mmSMU_INTERRUPT_CONTROL 0x12e
+#define mmDAC_CLK_ENABLE 0x128
+#define mmDVO_CLK_ENABLE 0x129
+#define mmDCCG_GATE_DISABLE_CNTL 0x134
+#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x135
+#define mmSCLK_CGTT_BLK_CTRL_REG 0x136
+#define mmDCCG_CAC_STATUS 0x137
+#define mmPIXCLK1_RESYNC_CNTL 0x138
+#define mmPIXCLK2_RESYNC_CNTL 0x139
+#define mmPIXCLK0_RESYNC_CNTL 0x13a
+#define mmMICROSECOND_TIME_BASE_DIV 0x13b
+#define mmDCCG_DISP_CNTL_REG 0x13f
+#define mmDISPPLL_BG_CNTL 0x13c
+#define mmDIG_SOFT_RESET 0x13d
+#define mmMILLISECOND_TIME_BASE_DIV 0x130
+#define mmDISPCLK_FREQ_CHANGE_CNTL 0x131
+#define mmLIGHT_SLEEP_CNTL 0x132
+#define mmDCCG_PERFMON_CNTL 0x133
+#define mmCRTC0_PIXEL_RATE_CNTL 0x140
+#define mmDP_DTO0_PHASE 0x141
+#define mmDP_DTO0_MODULO 0x142
+#define mmCRTC1_PIXEL_RATE_CNTL 0x144
+#define mmDP_DTO1_PHASE 0x145
+#define mmDP_DTO1_MODULO 0x146
+#define mmCRTC2_PIXEL_RATE_CNTL 0x148
+#define mmDP_DTO2_PHASE 0x149
+#define mmDP_DTO2_MODULO 0x14a
+#define mmCRTC3_PIXEL_RATE_CNTL 0x14c
+#define mmDP_DTO3_PHASE 0x14d
+#define mmDP_DTO3_MODULO 0x14e
+#define mmCRTC4_PIXEL_RATE_CNTL 0x150
+#define mmDP_DTO4_PHASE 0x151
+#define mmDP_DTO4_MODULO 0x152
+#define mmCRTC5_PIXEL_RATE_CNTL 0x154
+#define mmDP_DTO5_PHASE 0x155
+#define mmDP_DTO5_MODULO 0x156
+#define mmDCFE0_SOFT_RESET 0x158
+#define mmDCFE1_SOFT_RESET 0x159
+#define mmDCFE2_SOFT_RESET 0x15a
+#define mmDCFE3_SOFT_RESET 0x15b
+#define mmDCFE4_SOFT_RESET 0x15c
+#define mmDCFE5_SOFT_RESET 0x15d
+#define mmDCI_SOFT_RESET 0x15e
+#define mmDCCG_SOFT_RESET 0x15f
+#define mmSYMCLKA_CLOCK_ENABLE 0x160
+#define mmSYMCLKB_CLOCK_ENABLE 0x161
+#define mmSYMCLKC_CLOCK_ENABLE 0x162
+#define mmSYMCLKD_CLOCK_ENABLE 0x163
+#define mmSYMCLKE_CLOCK_ENABLE 0x164
+#define mmSYMCLKF_CLOCK_ENABLE 0x165
+#define mmSYMCLKG_CLOCK_ENABLE 0x117
+#define mmUNIPHY_SOFT_RESET 0x166
+#define mmDCO_SOFT_RESET 0x167
+#define mmDVOACLKD_CNTL 0x168
+#define mmDVOACLKC_MVP_CNTL 0x169
+#define mmDVOACLKC_CNTL 0x16a
+#define mmDCCG_AUDIO_DTO_SOURCE 0x16b
+#define mmDCCG_AUDIO_DTO0_PHASE 0x16c
+#define mmDCCG_AUDIO_DTO0_MODULE 0x16d
+#define mmDCCG_AUDIO_DTO1_PHASE 0x16e
+#define mmDCCG_AUDIO_DTO1_MODULE 0x16f
+#define mmDCCG_TEST_DEBUG_INDEX 0x17c
+#define mmDCCG_TEST_DEBUG_DATA 0x17d
+#define mmDCCG_TEST_CLK_SEL 0x17e
+#define mmPLL_REF_DIV 0x1700
+#define mmDCCG_PLL0_PLL_REF_DIV 0x1700
+#define mmDCCG_PLL1_PLL_REF_DIV 0x1714
+#define mmDCCG_PLL2_PLL_REF_DIV 0x1728
+#define mmDCCG_PLL3_PLL_REF_DIV 0x173c
+#define mmPLL_FB_DIV 0x1701
+#define mmDCCG_PLL0_PLL_FB_DIV 0x1701
+#define mmDCCG_PLL1_PLL_FB_DIV 0x1715
+#define mmDCCG_PLL2_PLL_FB_DIV 0x1729
+#define mmDCCG_PLL3_PLL_FB_DIV 0x173d
+#define mmPLL_POST_DIV 0x1702
+#define mmDCCG_PLL0_PLL_POST_DIV 0x1702
+#define mmDCCG_PLL1_PLL_POST_DIV 0x1716
+#define mmDCCG_PLL2_PLL_POST_DIV 0x172a
+#define mmDCCG_PLL3_PLL_POST_DIV 0x173e
+#define mmPLL_SS_AMOUNT_DSFRAC 0x1703
+#define mmDCCG_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703
+#define mmDCCG_PLL1_PLL_SS_AMOUNT_DSFRAC 0x1717
+#define mmDCCG_PLL2_PLL_SS_AMOUNT_DSFRAC 0x172b
+#define mmDCCG_PLL3_PLL_SS_AMOUNT_DSFRAC 0x173f
+#define mmPLL_SS_CNTL 0x1704
+#define mmDCCG_PLL0_PLL_SS_CNTL 0x1704
+#define mmDCCG_PLL1_PLL_SS_CNTL 0x1718
+#define mmDCCG_PLL2_PLL_SS_CNTL 0x172c
+#define mmDCCG_PLL3_PLL_SS_CNTL 0x1740
+#define mmPLL_DS_CNTL 0x1705
+#define mmDCCG_PLL0_PLL_DS_CNTL 0x1705
+#define mmDCCG_PLL1_PLL_DS_CNTL 0x1719
+#define mmDCCG_PLL2_PLL_DS_CNTL 0x172d
+#define mmDCCG_PLL3_PLL_DS_CNTL 0x1741
+#define mmPLL_IDCLK_CNTL 0x1706
+#define mmDCCG_PLL0_PLL_IDCLK_CNTL 0x1706
+#define mmDCCG_PLL1_PLL_IDCLK_CNTL 0x171a
+#define mmDCCG_PLL2_PLL_IDCLK_CNTL 0x172e
+#define mmDCCG_PLL3_PLL_IDCLK_CNTL 0x1742
+#define mmPLL_CNTL 0x1707
+#define mmDCCG_PLL0_PLL_CNTL 0x1707
+#define mmDCCG_PLL1_PLL_CNTL 0x171b
+#define mmDCCG_PLL2_PLL_CNTL 0x172f
+#define mmDCCG_PLL3_PLL_CNTL 0x1743
+#define mmPLL_ANALOG 0x1708
+#define mmDCCG_PLL0_PLL_ANALOG 0x1708
+#define mmDCCG_PLL1_PLL_ANALOG 0x171c
+#define mmDCCG_PLL2_PLL_ANALOG 0x1730
+#define mmDCCG_PLL3_PLL_ANALOG 0x1744
+#define mmPLL_ANALOG_CNTL 0x1711
+#define mmDCCG_PLL0_PLL_ANALOG_CNTL 0x1711
+#define mmDCCG_PLL1_PLL_ANALOG_CNTL 0x1725
+#define mmDCCG_PLL2_PLL_ANALOG_CNTL 0x1739
+#define mmDCCG_PLL3_PLL_ANALOG_CNTL 0x174d
+#define mmPLL_VREG_CNTL 0x1709
+#define mmDCCG_PLL0_PLL_VREG_CNTL 0x1709
+#define mmDCCG_PLL1_PLL_VREG_CNTL 0x171d
+#define mmDCCG_PLL2_PLL_VREG_CNTL 0x1731
+#define mmDCCG_PLL3_PLL_VREG_CNTL 0x1745
+#define mmPLL_XOR_LOCK 0x1710
+#define mmDCCG_PLL0_PLL_XOR_LOCK 0x1710
+#define mmDCCG_PLL1_PLL_XOR_LOCK 0x1724
+#define mmDCCG_PLL2_PLL_XOR_LOCK 0x1738
+#define mmDCCG_PLL3_PLL_XOR_LOCK 0x174c
+#define mmPLL_UNLOCK_DETECT_CNTL 0x170a
+#define mmDCCG_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170a
+#define mmDCCG_PLL1_PLL_UNLOCK_DETECT_CNTL 0x171e
+#define mmDCCG_PLL2_PLL_UNLOCK_DETECT_CNTL 0x1732
+#define mmDCCG_PLL3_PLL_UNLOCK_DETECT_CNTL 0x1746
+#define mmPLL_DEBUG_CNTL 0x170b
+#define mmDCCG_PLL0_PLL_DEBUG_CNTL 0x170b
+#define mmDCCG_PLL1_PLL_DEBUG_CNTL 0x171f
+#define mmDCCG_PLL2_PLL_DEBUG_CNTL 0x1733
+#define mmDCCG_PLL3_PLL_DEBUG_CNTL 0x1747
+#define mmPLL_UPDATE_LOCK 0x170c
+#define mmDCCG_PLL0_PLL_UPDATE_LOCK 0x170c
+#define mmDCCG_PLL1_PLL_UPDATE_LOCK 0x1720
+#define mmDCCG_PLL2_PLL_UPDATE_LOCK 0x1734
+#define mmDCCG_PLL3_PLL_UPDATE_LOCK 0x1748
+#define mmPLL_UPDATE_CNTL 0x170d
+#define mmDCCG_PLL0_PLL_UPDATE_CNTL 0x170d
+#define mmDCCG_PLL1_PLL_UPDATE_CNTL 0x1721
+#define mmDCCG_PLL2_PLL_UPDATE_CNTL 0x1735
+#define mmDCCG_PLL3_PLL_UPDATE_CNTL 0x1749
+#define mmPLL_DISPCLK_DTO_CNTL 0x170e
+#define mmDCCG_PLL0_PLL_DISPCLK_DTO_CNTL 0x170e
+#define mmDCCG_PLL1_PLL_DISPCLK_DTO_CNTL 0x1722
+#define mmDCCG_PLL2_PLL_DISPCLK_DTO_CNTL 0x1736
+#define mmDCCG_PLL3_PLL_DISPCLK_DTO_CNTL 0x174a
+#define mmPLL_DISPCLK_CURRENT_DTO_PHASE 0x170f
+#define mmDCCG_PLL0_PLL_DISPCLK_CURRENT_DTO_PHASE 0x170f
+#define mmDCCG_PLL1_PLL_DISPCLK_CURRENT_DTO_PHASE 0x1723
+#define mmDCCG_PLL2_PLL_DISPCLK_CURRENT_DTO_PHASE 0x1737
+#define mmDCCG_PLL3_PLL_DISPCLK_CURRENT_DTO_PHASE 0x174b
+#define mmDENTIST_DISPCLK_CNTL 0x124
+#define mmDCDEBUG_BUS_CLK1_SEL 0x1860
+#define mmDCDEBUG_BUS_CLK2_SEL 0x1861
+#define mmDCDEBUG_BUS_CLK3_SEL 0x1862
+#define mmDCDEBUG_BUS_CLK4_SEL 0x1863
+#define mmDCDEBUG_OUT_PIN_OVERRIDE 0x186a
+#define mmDCDEBUG_OUT_CNTL 0x186b
+#define mmDCDEBUG_OUT_DATA 0x186e
+#define mmDMIF_ADDR_CONFIG 0x2f5
+#define mmDMIF_CONTROL 0x2f6
+#define mmDMIF_STATUS 0x2f7
+#define mmDMIF_HW_DEBUG 0x2f8
+#define mmDMIF_ARBITRATION_CONTROL 0x2f9
+#define mmPIPE0_ARBITRATION_CONTROL3 0x2fa
+#define mmPIPE1_ARBITRATION_CONTROL3 0x2fb
+#define mmPIPE2_ARBITRATION_CONTROL3 0x2fc
+#define mmPIPE3_ARBITRATION_CONTROL3 0x2fd
+#define mmPIPE4_ARBITRATION_CONTROL3 0x2fe
+#define mmPIPE5_ARBITRATION_CONTROL3 0x2ff
+#define mmDMIF_TEST_DEBUG_INDEX 0x312
+#define mmDMIF_TEST_DEBUG_DATA 0x313
+#define ixDMIF_DEBUG02_CORE0 0x2
+#define ixDMIF_DEBUG02_CORE1 0xa
+#define mmDMIF_ADDR_CALC 0x300
+#define mmDMIF_STATUS2 0x301
+#define mmPIPE0_MAX_REQUESTS 0x302
+#define mmPIPE1_MAX_REQUESTS 0x303
+#define mmPIPE2_MAX_REQUESTS 0x304
+#define mmPIPE3_MAX_REQUESTS 0x305
+#define mmPIPE4_MAX_REQUESTS 0x306
+#define mmPIPE5_MAX_REQUESTS 0x307
+#define mmLOW_POWER_TILING_CONTROL 0x325
+#define mmMCIF_CONTROL 0x314
+#define mmMCIF_WRITE_COMBINE_CONTROL 0x315
+#define mmMCIF_TEST_DEBUG_INDEX 0x316
+#define mmMCIF_TEST_DEBUG_DATA 0x317
+#define ixIDDCCIF02_DBG_DCCIF_C 0x9
+#define ixIDDCCIF04_DBG_DCCIF_E 0xb
+#define ixIDDCCIF05_DBG_DCCIF_F 0xc
+#define mmMCIF_VMID 0x318
+#define mmMCIF_MEM_CONTROL 0x319
+#define mmCC_DC_PIPE_DIS 0x177f
+#define mmMC_DC_INTERFACE_NACK_STATUS 0x31c
+#define mmDC_RBBMIF_RDWR_CNTL1 0x31a
+#define mmDC_RBBMIF_RDWR_CNTL2 0x31d
+#define mmDC_RBBMIF_RDWR_CNTL3 0x311
+#define mmDCI_MEM_PWR_STATE 0x31b
+#define mmDCI_MEM_PWR_STATE2 0x322
+#define mmDCI_CLK_CNTL 0x31e
+#define mmDCCG_VPCLK_CNTL 0x31f
+#define mmDCI_MEM_PWR_CNTL 0x326
+#define mmDC_XDMA_INTERFACE_CNTL 0x327
+#define mmDCI_TEST_DEBUG_INDEX 0x320
+#define mmDCI_TEST_DEBUG_DATA 0x321
+#define mmDCI_DEBUG_CONFIG 0x323
+#define mmPIPE0_DMIF_BUFFER_CONTROL 0x328
+#define mmPIPE1_DMIF_BUFFER_CONTROL 0x330
+#define mmPIPE2_DMIF_BUFFER_CONTROL 0x338
+#define mmPIPE3_DMIF_BUFFER_CONTROL 0x340
+#define mmPIPE4_DMIF_BUFFER_CONTROL 0x348
+#define mmPIPE5_DMIF_BUFFER_CONTROL 0x350
+#define mmMCIF_BUFMGR_SW_CONTROL 0x358
+#define mmMCIF_BUFMGR_STATUS 0x35a
+#define mmMCIF_BUF_PITCH 0x35b
+#define mmMCIF_BUF_1_ADDR_Y_LOW 0x35c
+#define mmMCIF_BUF_2_ADDR_Y_LOW 0x360
+#define mmMCIF_BUF_3_ADDR_Y_LOW 0x364
+#define mmMCIF_BUF_4_ADDR_Y_LOW 0x368
+#define mmMCIF_BUF_1_ADDR_UP 0x35d
+#define mmMCIF_BUF_2_ADDR_UP 0x361
+#define mmMCIF_BUF_3_ADDR_UP 0x365
+#define mmMCIF_BUF_4_ADDR_UP 0x369
+#define mmMCIF_BUF_1_ADDR_C_LOW 0x35e
+#define mmMCIF_BUF_2_ADDR_C_LOW 0x362
+#define mmMCIF_BUF_3_ADDR_C_LOW 0x366
+#define mmMCIF_BUF_4_ADDR_C_LOW 0x36a
+#define mmMCIF_BUF_1_STATUS 0x35f
+#define mmMCIF_BUF_2_STATUS 0x363
+#define mmMCIF_BUF_3_STATUS 0x367
+#define mmMCIF_BUF_4_STATUS 0x36b
+#define mmMCIF_SI_ARBITRATION_CONTROL 0x36c
+#define mmMCIF_URGENCY_WATERMARK 0x36d
+#define mmDC_GENERICA 0x1900
+#define mmDC_GENERICB 0x1901
+#define mmDC_PAD_EXTERN_SIG 0x1902
+#define mmDC_REF_CLK_CNTL 0x1903
+#define mmDC_GPIO_DEBUG 0x1904
+#define mmDCO_MEM_POWER_STATE 0x1906
+#define mmDCO_MEM_POWER_STATE_2 0x193a
+#define mmDCO_LIGHT_SLEEP_DIS 0x1907
+#define mmUNIPHY_IMPCAL_LINKA 0x1908
+#define mmUNIPHY_IMPCAL_LINKB 0x1909
+#define mmUNIPHY_IMPCAL_PERIOD 0x190a
+#define mmAUXP_IMPCAL 0x190b
+#define mmAUXN_IMPCAL 0x190c
+#define mmDCIO_IMPCAL_CNTL_AB 0x190d
+#define mmUNIPHY_IMPCAL_PSW_AB 0x190e
+#define mmUNIPHY_IMPCAL_LINKC 0x190f
+#define mmUNIPHY_IMPCAL_LINKD 0x1910
+#define mmDCIO_IMPCAL_CNTL_CD 0x1911
+#define mmUNIPHY_IMPCAL_PSW_CD 0x1912
+#define mmUNIPHY_IMPCAL_LINKE 0x1913
+#define mmUNIPHY_IMPCAL_LINKF 0x1914
+#define mmDCIO_IMPCAL_CNTL_EF 0x1915
+#define mmUNIPHY_IMPCAL_PSW_EF 0x1916
+#define mmDC_PINSTRAPS 0x1917
+#define mmDC_DVODATA_CONFIG 0x1905
+#define mmLVTMA_PWRSEQ_CNTL 0x1919
+#define mmLVTMA_PWRSEQ_STATE 0x191a
+#define mmLVTMA_PWRSEQ_REF_DIV 0x191b
+#define mmLVTMA_PWRSEQ_DELAY1 0x191c
+#define mmLVTMA_PWRSEQ_DELAY2 0x191d
+#define mmBL_PWM_CNTL 0x191e
+#define mmBL_PWM_CNTL2 0x191f
+#define mmBL_PWM_PERIOD_CNTL 0x1920
+#define mmBL_PWM_GRP1_REG_LOCK 0x1921
+#define mmDCIO_GSL_GENLK_PAD_CNTL 0x1922
+#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x1923
+#define mmDCIO_GSL0_CNTL 0x1924
+#define mmDCIO_GSL1_CNTL 0x1925
+#define mmDCIO_GSL2_CNTL 0x1926
+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x1927
+#define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x1928
+#define mmDC_GPU_TIMER_READ 0x1929
+#define mmDC_GPU_TIMER_READ_CNTL 0x192a
+#define mmDCO_CLK_CNTL 0x192b
+#define mmDCO_CLK_RAMP_CNTL 0x192c
+#define mmDCIO_DEBUG 0x192e
+#define mmDCO_DCFE_EXT_VSYNC_CNTL 0x1937
+#define mmDCIO_TEST_DEBUG_INDEX 0x192f
+#define mmDCIO_TEST_DEBUG_DATA 0x1930
+#define ixDCIO_DEBUG1 0x1
+#define ixDCIO_DEBUG2 0x2
+#define ixDCIO_DEBUG3 0x3
+#define ixDCIO_DEBUG4 0x4
+#define ixDCIO_DEBUG5 0x5
+#define ixDCIO_DEBUG6 0x6
+#define ixDCIO_DEBUG7 0x7
+#define ixDCIO_DEBUG8 0x8
+#define ixDCIO_DEBUG9 0x9
+#define ixDCIO_DEBUGA 0xa
+#define ixDCIO_DEBUGB 0xb
+#define ixDCIO_DEBUGC 0xc
+#define ixDCIO_DEBUGD 0xd
+#define ixDCIO_DEBUGE 0xe
+#define ixDCIO_DEBUGF 0xf
+#define ixDCIO_DEBUG10 0x10
+#define ixDCIO_DEBUG11 0x11
+#define ixDCIO_DEBUG12 0x12
+#define ixDCIO_DEBUG13 0x13
+#define ixDCIO_DEBUG14 0x14
+#define ixDCIO_DEBUG15 0x15
+#define ixDCIO_DEBUG_ID 0x0
+#define mmDC_GPIO_GENERIC_MASK 0x1944
+#define mmDC_GPIO_GENERIC_A 0x1945
+#define mmDC_GPIO_GENERIC_EN 0x1946
+#define mmDC_GPIO_GENERIC_Y 0x1947
+#define mmDC_GPIO_DVODATA_MASK 0x1948
+#define mmDC_GPIO_DVODATA_A 0x1949
+#define mmDC_GPIO_DVODATA_EN 0x194a
+#define mmDC_GPIO_DVODATA_Y 0x194b
+#define mmDC_GPIO_DDC1_MASK 0x194c
+#define mmDC_GPIO_DDC1_A 0x194d
+#define mmDC_GPIO_DDC1_EN 0x194e
+#define mmDC_GPIO_DDC1_Y 0x194f
+#define mmDC_GPIO_DDC2_MASK 0x1950
+#define mmDC_GPIO_DDC2_A 0x1951
+#define mmDC_GPIO_DDC2_EN 0x1952
+#define mmDC_GPIO_DDC2_Y 0x1953
+#define mmDC_GPIO_DDC3_MASK 0x1954
+#define mmDC_GPIO_DDC3_A 0x1955
+#define mmDC_GPIO_DDC3_EN 0x1956
+#define mmDC_GPIO_DDC3_Y 0x1957
+#define mmDC_GPIO_DDC4_MASK 0x1958
+#define mmDC_GPIO_DDC4_A 0x1959
+#define mmDC_GPIO_DDC4_EN 0x195a
+#define mmDC_GPIO_DDC4_Y 0x195b
+#define mmDC_GPIO_DDC5_MASK 0x195c
+#define mmDC_GPIO_DDC5_A 0x195d
+#define mmDC_GPIO_DDC5_EN 0x195e
+#define mmDC_GPIO_DDC5_Y 0x195f
+#define mmDC_GPIO_DDC6_MASK 0x1960
+#define mmDC_GPIO_DDC6_A 0x1961
+#define mmDC_GPIO_DDC6_EN 0x1962
+#define mmDC_GPIO_DDC6_Y 0x1963
+#define mmDC_GPIO_DDCVGA_MASK 0x1970
+#define mmDC_GPIO_DDCVGA_A 0x1971
+#define mmDC_GPIO_DDCVGA_EN 0x1972
+#define mmDC_GPIO_DDCVGA_Y 0x1973
+#define mmDC_GPIO_SYNCA_MASK 0x1964
+#define mmDC_GPIO_SYNCA_A 0x1965
+#define mmDC_GPIO_SYNCA_EN 0x1966
+#define mmDC_GPIO_SYNCA_Y 0x1967
+#define mmDC_GPIO_GENLK_MASK 0x1968
+#define mmDC_GPIO_GENLK_A 0x1969
+#define mmDC_GPIO_GENLK_EN 0x196a
+#define mmDC_GPIO_GENLK_Y 0x196b
+#define mmDC_GPIO_HPD_MASK 0x196c
+#define mmDC_GPIO_HPD_A 0x196d
+#define mmDC_GPIO_HPD_EN 0x196e
+#define mmDC_GPIO_HPD_Y 0x196f
+#define mmDC_GPIO_PWRSEQ_MASK 0x1940
+#define mmDC_GPIO_PWRSEQ_A 0x1941
+#define mmDC_GPIO_PWRSEQ_EN 0x1942
+#define mmDC_GPIO_PWRSEQ_Y 0x1943
+#define mmDC_GPIO_PAD_STRENGTH_1 0x1978
+#define mmDC_GPIO_PAD_STRENGTH_2 0x1979
+#define mmPHY_AUX_CNTL 0x197f
+#define mmDC_GPIO_I2CPAD_A 0x1975
+#define mmDC_GPIO_I2CPAD_EN 0x1976
+#define mmDC_GPIO_I2CPAD_Y 0x1977
+#define mmDC_GPIO_I2CPAD_STRENGTH 0x197a
+#define mmDVO_STRENGTH_CONTROL 0x197b
+#define mmDVO_VREF_CONTROL 0x197c
+#define mmDVO_SKEW_ADJUST 0x197d
+#define mmUNIPHYAB_TPG_CONTROL 0x1931
+#define mmUNIPHYAB_TPG_SEED 0x1932
+#define mmUNIPHYCD_TPG_CONTROL 0x1933
+#define mmUNIPHYCD_TPG_SEED 0x1934
+#define mmUNIPHYEF_TPG_CONTROL 0x1935
+#define mmUNIPHYEF_TPG_SEED 0x1936
+#define mmUNIPHYGH_TPG_CONTROL 0x1938
+#define mmUNIPHYGH_TPG_SEED 0x1939
+#define mmDC_GPIO_I2S_SPDIF_MASK 0x193c
+#define mmDC_GPIO_I2S_SPDIF_A 0x193d
+#define mmDC_GPIO_I2S_SPDIF_EN 0x193e
+#define mmDC_GPIO_I2S_SPDIF_Y 0x193f
+#define mmDC_GPIO_I2S_SPDIF_STRENGTH 0x193b
+#define mmDAC_MACRO_CNTL_RESERVED0 0x19fc
+#define mmDAC_MACRO_CNTL_RESERVED1 0x19fd
+#define mmDAC_MACRO_CNTL_RESERVED2 0x19fe
+#define mmDAC_MACRO_CNTL_RESERVED3 0x19ff
+#define mmUNIPHY_TX_CONTROL1 0x1980
+#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL1 0x1980
+#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL1 0x1990
+#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL1 0x19a0
+#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL1 0x19b0
+#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL1 0x19c0
+#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL1 0x19d0
+#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL1 0x4df0
+#define mmUNIPHY_TX_CONTROL2 0x1981
+#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL2 0x1981
+#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL2 0x1991
+#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL2 0x19a1
+#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL2 0x19b1
+#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL2 0x19c1
+#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL2 0x19d1
+#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL2 0x4df1
+#define mmUNIPHY_TX_CONTROL3 0x1982
+#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL3 0x1982
+#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL3 0x1992
+#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL3 0x19a2
+#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL3 0x19b2
+#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL3 0x19c2
+#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL3 0x19d2
+#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL3 0x4df2
+#define mmUNIPHY_TX_CONTROL4 0x1983
+#define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL4 0x1983
+#define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL4 0x1993
+#define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL4 0x19a3
+#define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL4 0x19b3
+#define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL4 0x19c3
+#define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL4 0x19d3
+#define mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL4 0x4df3
+#define mmUNIPHY_POWER_CONTROL 0x1984
+#define mmDCIO_UNIPHY0_UNIPHY_POWER_CONTROL 0x1984
+#define mmDCIO_UNIPHY1_UNIPHY_POWER_CONTROL 0x1994
+#define mmDCIO_UNIPHY2_UNIPHY_POWER_CONTROL 0x19a4
+#define mmDCIO_UNIPHY3_UNIPHY_POWER_CONTROL 0x19b4
+#define mmDCIO_UNIPHY4_UNIPHY_POWER_CONTROL 0x19c4
+#define mmDCIO_UNIPHY5_UNIPHY_POWER_CONTROL 0x19d4
+#define mmDCIO_UNIPHY6_UNIPHY_POWER_CONTROL 0x4df4
+#define mmUNIPHY_PLL_FBDIV 0x1985
+#define mmDCIO_UNIPHY0_UNIPHY_PLL_FBDIV 0x1985
+#define mmDCIO_UNIPHY1_UNIPHY_PLL_FBDIV 0x1995
+#define mmDCIO_UNIPHY2_UNIPHY_PLL_FBDIV 0x19a5
+#define mmDCIO_UNIPHY3_UNIPHY_PLL_FBDIV 0x19b5
+#define mmDCIO_UNIPHY4_UNIPHY_PLL_FBDIV 0x19c5
+#define mmDCIO_UNIPHY5_UNIPHY_PLL_FBDIV 0x19d5
+#define mmDCIO_UNIPHY6_UNIPHY_PLL_FBDIV 0x4df5
+#define mmUNIPHY_PLL_CONTROL1 0x1986
+#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL1 0x1986
+#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL1 0x1996
+#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL1 0x19a6
+#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL1 0x19b6
+#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL1 0x19c6
+#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL1 0x19d6
+#define mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL1 0x4df6
+#define mmUNIPHY_PLL_CONTROL2 0x1987
+#define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL2 0x1987
+#define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL2 0x1997
+#define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL2 0x19a7
+#define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL2 0x19b7
+#define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL2 0x19c7
+#define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL2 0x19d7
+#define mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL2 0x4df7
+#define mmUNIPHY_PLL_SS_STEP_SIZE 0x1988
+#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x1988
+#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x1998
+#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x19a8
+#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x19b8
+#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x19c8
+#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x19d8
+#define mmDCIO_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE 0x4df8
+#define mmUNIPHY_PLL_SS_CNTL 0x1989
+#define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x1989
+#define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x1999
+#define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x19a9
+#define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x19b9
+#define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x19c9
+#define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x19d9
+#define mmDCIO_UNIPHY6_UNIPHY_PLL_SS_CNTL 0x4df9
+#define mmUNIPHY_DATA_SYNCHRONIZATION 0x198a
+#define mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x198a
+#define mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x199a
+#define mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x19aa
+#define mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x19ba
+#define mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x19ca
+#define mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x19da
+#define mmDCIO_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION 0x4dfa
+#define mmUNIPHY_REG_TEST_OUTPUT 0x198b
+#define mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x198b
+#define mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x199b
+#define mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x19ab
+#define mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x19bb
+#define mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x19cb
+#define mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x19db
+#define mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT 0x4dfb
+#define mmUNIPHY_ANG_BIST_CNTL 0x198c
+#define mmDCIO_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x198c
+#define mmDCIO_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x199c
+#define mmDCIO_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x19ac
+#define mmDCIO_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x19bc
+#define mmDCIO_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x19cc
+#define mmDCIO_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x19dc
+#define mmDCIO_UNIPHY6_UNIPHY_ANG_BIST_CNTL 0x4dfc
+#define mmUNIPHY_LINK_CNTL 0x198d
+#define mmDCIO_UNIPHY0_UNIPHY_LINK_CNTL 0x198d
+#define mmDCIO_UNIPHY1_UNIPHY_LINK_CNTL 0x199d
+#define mmDCIO_UNIPHY2_UNIPHY_LINK_CNTL 0x19ad
+#define mmDCIO_UNIPHY3_UNIPHY_LINK_CNTL 0x19bd
+#define mmDCIO_UNIPHY4_UNIPHY_LINK_CNTL 0x19cd
+#define mmDCIO_UNIPHY5_UNIPHY_LINK_CNTL 0x19dd
+#define mmDCIO_UNIPHY6_UNIPHY_LINK_CNTL 0x4dfd
+#define mmUNIPHY_CHANNEL_XBAR_CNTL 0x198e
+#define mmDCIO_UNIPHY0_UNIPHY_CHANNEL_XBAR_CNTL 0x198e
+#define mmDCIO_UNIPHY1_UNIPHY_CHANNEL_XBAR_CNTL 0x199e
+#define mmDCIO_UNIPHY2_UNIPHY_CHANNEL_XBAR_CNTL 0x19ae
+#define mmDCIO_UNIPHY3_UNIPHY_CHANNEL_XBAR_CNTL 0x19be
+#define mmDCIO_UNIPHY4_UNIPHY_CHANNEL_XBAR_CNTL 0x19ce
+#define mmDCIO_UNIPHY5_UNIPHY_CHANNEL_XBAR_CNTL 0x19de
+#define mmDCIO_UNIPHY6_UNIPHY_CHANNEL_XBAR_CNTL 0x4dfe
+#define mmUNIPHY_REG_TEST_OUTPUT2 0x198f
+#define mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 0x198f
+#define mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 0x199f
+#define mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 0x19af
+#define mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 0x19bf
+#define mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 0x19cf
+#define mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 0x19df
+#define mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 0x4dff
+#define mmGRPH_ENABLE 0x1a00
+#define mmDCP0_GRPH_ENABLE 0x1a00
+#define mmDCP1_GRPH_ENABLE 0x1d00
+#define mmDCP2_GRPH_ENABLE 0x4000
+#define mmDCP3_GRPH_ENABLE 0x4300
+#define mmDCP4_GRPH_ENABLE 0x4600
+#define mmDCP5_GRPH_ENABLE 0x4900
+#define mmGRPH_CONTROL 0x1a01
+#define mmDCP0_GRPH_CONTROL 0x1a01
+#define mmDCP1_GRPH_CONTROL 0x1d01
+#define mmDCP2_GRPH_CONTROL 0x4001
+#define mmDCP3_GRPH_CONTROL 0x4301
+#define mmDCP4_GRPH_CONTROL 0x4601
+#define mmDCP5_GRPH_CONTROL 0x4901
+#define mmGRPH_LUT_10BIT_BYPASS 0x1a02
+#define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1a02
+#define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1d02
+#define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x4002
+#define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4302
+#define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4602
+#define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4902
+#define mmGRPH_SWAP_CNTL 0x1a03
+#define mmDCP0_GRPH_SWAP_CNTL 0x1a03
+#define mmDCP1_GRPH_SWAP_CNTL 0x1d03
+#define mmDCP2_GRPH_SWAP_CNTL 0x4003
+#define mmDCP3_GRPH_SWAP_CNTL 0x4303
+#define mmDCP4_GRPH_SWAP_CNTL 0x4603
+#define mmDCP5_GRPH_SWAP_CNTL 0x4903
+#define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04
+#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04
+#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1d04
+#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004
+#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4304
+#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4604
+#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4904
+#define mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1a05
+#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05
+#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1d05
+#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005
+#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4305
+#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4605
+#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4905
+#define mmGRPH_PITCH 0x1a06
+#define mmDCP0_GRPH_PITCH 0x1a06
+#define mmDCP1_GRPH_PITCH 0x1d06
+#define mmDCP2_GRPH_PITCH 0x4006
+#define mmDCP3_GRPH_PITCH 0x4306
+#define mmDCP4_GRPH_PITCH 0x4606
+#define mmDCP5_GRPH_PITCH 0x4906
+#define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07
+#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07
+#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1d07
+#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007
+#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4307
+#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4607
+#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4907
+#define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08
+#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08
+#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1d08
+#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008
+#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4308
+#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4608
+#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4908
+#define mmGRPH_SURFACE_OFFSET_X 0x1a09
+#define mmDCP0_GRPH_SURFACE_OFFSET_X 0x1a09
+#define mmDCP1_GRPH_SURFACE_OFFSET_X 0x1d09
+#define mmDCP2_GRPH_SURFACE_OFFSET_X 0x4009
+#define mmDCP3_GRPH_SURFACE_OFFSET_X 0x4309
+#define mmDCP4_GRPH_SURFACE_OFFSET_X 0x4609
+#define mmDCP5_GRPH_SURFACE_OFFSET_X 0x4909
+#define mmGRPH_SURFACE_OFFSET_Y 0x1a0a
+#define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1a0a
+#define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1d0a
+#define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x400a
+#define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x430a
+#define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x460a
+#define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x490a
+#define mmGRPH_X_START 0x1a0b
+#define mmDCP0_GRPH_X_START 0x1a0b
+#define mmDCP1_GRPH_X_START 0x1d0b
+#define mmDCP2_GRPH_X_START 0x400b
+#define mmDCP3_GRPH_X_START 0x430b
+#define mmDCP4_GRPH_X_START 0x460b
+#define mmDCP5_GRPH_X_START 0x490b
+#define mmGRPH_Y_START 0x1a0c
+#define mmDCP0_GRPH_Y_START 0x1a0c
+#define mmDCP1_GRPH_Y_START 0x1d0c
+#define mmDCP2_GRPH_Y_START 0x400c
+#define mmDCP3_GRPH_Y_START 0x430c
+#define mmDCP4_GRPH_Y_START 0x460c
+#define mmDCP5_GRPH_Y_START 0x490c
+#define mmGRPH_X_END 0x1a0d
+#define mmDCP0_GRPH_X_END 0x1a0d
+#define mmDCP1_GRPH_X_END 0x1d0d
+#define mmDCP2_GRPH_X_END 0x400d
+#define mmDCP3_GRPH_X_END 0x430d
+#define mmDCP4_GRPH_X_END 0x460d
+#define mmDCP5_GRPH_X_END 0x490d
+#define mmGRPH_Y_END 0x1a0e
+#define mmDCP0_GRPH_Y_END 0x1a0e
+#define mmDCP1_GRPH_Y_END 0x1d0e
+#define mmDCP2_GRPH_Y_END 0x400e
+#define mmDCP3_GRPH_Y_END 0x430e
+#define mmDCP4_GRPH_Y_END 0x460e
+#define mmDCP5_GRPH_Y_END 0x490e
+#define mmINPUT_GAMMA_CONTROL 0x1a10
+#define mmDCP0_INPUT_GAMMA_CONTROL 0x1a10
+#define mmDCP1_INPUT_GAMMA_CONTROL 0x1d10
+#define mmDCP2_INPUT_GAMMA_CONTROL 0x4010
+#define mmDCP3_INPUT_GAMMA_CONTROL 0x4310
+#define mmDCP4_INPUT_GAMMA_CONTROL 0x4610
+#define mmDCP5_INPUT_GAMMA_CONTROL 0x4910
+#define mmGRPH_UPDATE 0x1a11
+#define mmDCP0_GRPH_UPDATE 0x1a11
+#define mmDCP1_GRPH_UPDATE 0x1d11
+#define mmDCP2_GRPH_UPDATE 0x4011
+#define mmDCP3_GRPH_UPDATE 0x4311
+#define mmDCP4_GRPH_UPDATE 0x4611
+#define mmDCP5_GRPH_UPDATE 0x4911
+#define mmGRPH_FLIP_CONTROL 0x1a12
+#define mmDCP0_GRPH_FLIP_CONTROL 0x1a12
+#define mmDCP1_GRPH_FLIP_CONTROL 0x1d12
+#define mmDCP2_GRPH_FLIP_CONTROL 0x4012
+#define mmDCP3_GRPH_FLIP_CONTROL 0x4312
+#define mmDCP4_GRPH_FLIP_CONTROL 0x4612
+#define mmDCP5_GRPH_FLIP_CONTROL 0x4912
+#define mmGRPH_SURFACE_ADDRESS_INUSE 0x1a13
+#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1a13
+#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1d13
+#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x4013
+#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4313
+#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4613
+#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4913
+#define mmGRPH_DFQ_CONTROL 0x1a14
+#define mmDCP0_GRPH_DFQ_CONTROL 0x1a14
+#define mmDCP1_GRPH_DFQ_CONTROL 0x1d14
+#define mmDCP2_GRPH_DFQ_CONTROL 0x4014
+#define mmDCP3_GRPH_DFQ_CONTROL 0x4314
+#define mmDCP4_GRPH_DFQ_CONTROL 0x4614
+#define mmDCP5_GRPH_DFQ_CONTROL 0x4914
+#define mmGRPH_DFQ_STATUS 0x1a15
+#define mmDCP0_GRPH_DFQ_STATUS 0x1a15
+#define mmDCP1_GRPH_DFQ_STATUS 0x1d15
+#define mmDCP2_GRPH_DFQ_STATUS 0x4015
+#define mmDCP3_GRPH_DFQ_STATUS 0x4315
+#define mmDCP4_GRPH_DFQ_STATUS 0x4615
+#define mmDCP5_GRPH_DFQ_STATUS 0x4915
+#define mmGRPH_INTERRUPT_STATUS 0x1a16
+#define mmDCP0_GRPH_INTERRUPT_STATUS 0x1a16
+#define mmDCP1_GRPH_INTERRUPT_STATUS 0x1d16
+#define mmDCP2_GRPH_INTERRUPT_STATUS 0x4016
+#define mmDCP3_GRPH_INTERRUPT_STATUS 0x4316
+#define mmDCP4_GRPH_INTERRUPT_STATUS 0x4616
+#define mmDCP5_GRPH_INTERRUPT_STATUS 0x4916
+#define mmGRPH_INTERRUPT_CONTROL 0x1a17
+#define mmDCP0_GRPH_INTERRUPT_CONTROL 0x1a17
+#define mmDCP1_GRPH_INTERRUPT_CONTROL 0x1d17
+#define mmDCP2_GRPH_INTERRUPT_CONTROL 0x4017
+#define mmDCP3_GRPH_INTERRUPT_CONTROL 0x4317
+#define mmDCP4_GRPH_INTERRUPT_CONTROL 0x4617
+#define mmDCP5_GRPH_INTERRUPT_CONTROL 0x4917
+#define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18
+#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18
+#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1d18
+#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018
+#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4318
+#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4618
+#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4918
+#define mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1a19
+#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1a19
+#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1d19
+#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019
+#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4319
+#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4619
+#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4919
+#define mmGRPH_COMPRESS_PITCH 0x1a1a
+#define mmDCP0_GRPH_COMPRESS_PITCH 0x1a1a
+#define mmDCP1_GRPH_COMPRESS_PITCH 0x1d1a
+#define mmDCP2_GRPH_COMPRESS_PITCH 0x401a
+#define mmDCP3_GRPH_COMPRESS_PITCH 0x431a
+#define mmDCP4_GRPH_COMPRESS_PITCH 0x461a
+#define mmDCP5_GRPH_COMPRESS_PITCH 0x491a
+#define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b
+#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b
+#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1d1b
+#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401b
+#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x431b
+#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x461b
+#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x491b
+#define mmOVL_ENABLE 0x1a1c
+#define mmDCP0_OVL_ENABLE 0x1a1c
+#define mmDCP1_OVL_ENABLE 0x1d1c
+#define mmDCP2_OVL_ENABLE 0x401c
+#define mmDCP3_OVL_ENABLE 0x431c
+#define mmDCP4_OVL_ENABLE 0x461c
+#define mmDCP5_OVL_ENABLE 0x491c
+#define mmOVL_CONTROL1 0x1a1d
+#define mmDCP0_OVL_CONTROL1 0x1a1d
+#define mmDCP1_OVL_CONTROL1 0x1d1d
+#define mmDCP2_OVL_CONTROL1 0x401d
+#define mmDCP3_OVL_CONTROL1 0x431d
+#define mmDCP4_OVL_CONTROL1 0x461d
+#define mmDCP5_OVL_CONTROL1 0x491d
+#define mmOVL_CONTROL2 0x1a1e
+#define mmDCP0_OVL_CONTROL2 0x1a1e
+#define mmDCP1_OVL_CONTROL2 0x1d1e
+#define mmDCP2_OVL_CONTROL2 0x401e
+#define mmDCP3_OVL_CONTROL2 0x431e
+#define mmDCP4_OVL_CONTROL2 0x461e
+#define mmDCP5_OVL_CONTROL2 0x491e
+#define mmOVL_SWAP_CNTL 0x1a1f
+#define mmDCP0_OVL_SWAP_CNTL 0x1a1f
+#define mmDCP1_OVL_SWAP_CNTL 0x1d1f
+#define mmDCP2_OVL_SWAP_CNTL 0x401f
+#define mmDCP3_OVL_SWAP_CNTL 0x431f
+#define mmDCP4_OVL_SWAP_CNTL 0x461f
+#define mmDCP5_OVL_SWAP_CNTL 0x491f
+#define mmOVL_SURFACE_ADDRESS 0x1a20
+#define mmDCP0_OVL_SURFACE_ADDRESS 0x1a20
+#define mmDCP1_OVL_SURFACE_ADDRESS 0x1d20
+#define mmDCP2_OVL_SURFACE_ADDRESS 0x4020
+#define mmDCP3_OVL_SURFACE_ADDRESS 0x4320
+#define mmDCP4_OVL_SURFACE_ADDRESS 0x4620
+#define mmDCP5_OVL_SURFACE_ADDRESS 0x4920
+#define mmOVL_PITCH 0x1a21
+#define mmDCP0_OVL_PITCH 0x1a21
+#define mmDCP1_OVL_PITCH 0x1d21
+#define mmDCP2_OVL_PITCH 0x4021
+#define mmDCP3_OVL_PITCH 0x4321
+#define mmDCP4_OVL_PITCH 0x4621
+#define mmDCP5_OVL_PITCH 0x4921
+#define mmOVL_SURFACE_ADDRESS_HIGH 0x1a22
+#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH 0x1a22
+#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH 0x1d22
+#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH 0x4022
+#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH 0x4322
+#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH 0x4622
+#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH 0x4922
+#define mmOVL_SURFACE_OFFSET_X 0x1a23
+#define mmDCP0_OVL_SURFACE_OFFSET_X 0x1a23
+#define mmDCP1_OVL_SURFACE_OFFSET_X 0x1d23
+#define mmDCP2_OVL_SURFACE_OFFSET_X 0x4023
+#define mmDCP3_OVL_SURFACE_OFFSET_X 0x4323
+#define mmDCP4_OVL_SURFACE_OFFSET_X 0x4623
+#define mmDCP5_OVL_SURFACE_OFFSET_X 0x4923
+#define mmOVL_SURFACE_OFFSET_Y 0x1a24
+#define mmDCP0_OVL_SURFACE_OFFSET_Y 0x1a24
+#define mmDCP1_OVL_SURFACE_OFFSET_Y 0x1d24
+#define mmDCP2_OVL_SURFACE_OFFSET_Y 0x4024
+#define mmDCP3_OVL_SURFACE_OFFSET_Y 0x4324
+#define mmDCP4_OVL_SURFACE_OFFSET_Y 0x4624
+#define mmDCP5_OVL_SURFACE_OFFSET_Y 0x4924
+#define mmOVL_START 0x1a25
+#define mmDCP0_OVL_START 0x1a25
+#define mmDCP1_OVL_START 0x1d25
+#define mmDCP2_OVL_START 0x4025
+#define mmDCP3_OVL_START 0x4325
+#define mmDCP4_OVL_START 0x4625
+#define mmDCP5_OVL_START 0x4925
+#define mmOVL_END 0x1a26
+#define mmDCP0_OVL_END 0x1a26
+#define mmDCP1_OVL_END 0x1d26
+#define mmDCP2_OVL_END 0x4026
+#define mmDCP3_OVL_END 0x4326
+#define mmDCP4_OVL_END 0x4626
+#define mmDCP5_OVL_END 0x4926
+#define mmOVL_UPDATE 0x1a27
+#define mmDCP0_OVL_UPDATE 0x1a27
+#define mmDCP1_OVL_UPDATE 0x1d27
+#define mmDCP2_OVL_UPDATE 0x4027
+#define mmDCP3_OVL_UPDATE 0x4327
+#define mmDCP4_OVL_UPDATE 0x4627
+#define mmDCP5_OVL_UPDATE 0x4927
+#define mmOVL_SURFACE_ADDRESS_INUSE 0x1a28
+#define mmDCP0_OVL_SURFACE_ADDRESS_INUSE 0x1a28
+#define mmDCP1_OVL_SURFACE_ADDRESS_INUSE 0x1d28
+#define mmDCP2_OVL_SURFACE_ADDRESS_INUSE 0x4028
+#define mmDCP3_OVL_SURFACE_ADDRESS_INUSE 0x4328
+#define mmDCP4_OVL_SURFACE_ADDRESS_INUSE 0x4628
+#define mmDCP5_OVL_SURFACE_ADDRESS_INUSE 0x4928
+#define mmOVL_DFQ_CONTROL 0x1a29
+#define mmDCP0_OVL_DFQ_CONTROL 0x1a29
+#define mmDCP1_OVL_DFQ_CONTROL 0x1d29
+#define mmDCP2_OVL_DFQ_CONTROL 0x4029
+#define mmDCP3_OVL_DFQ_CONTROL 0x4329
+#define mmDCP4_OVL_DFQ_CONTROL 0x4629
+#define mmDCP5_OVL_DFQ_CONTROL 0x4929
+#define mmOVL_DFQ_STATUS 0x1a2a
+#define mmDCP0_OVL_DFQ_STATUS 0x1a2a
+#define mmDCP1_OVL_DFQ_STATUS 0x1d2a
+#define mmDCP2_OVL_DFQ_STATUS 0x402a
+#define mmDCP3_OVL_DFQ_STATUS 0x432a
+#define mmDCP4_OVL_DFQ_STATUS 0x462a
+#define mmDCP5_OVL_DFQ_STATUS 0x492a
+#define mmOVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b
+#define mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b
+#define mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1d2b
+#define mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x402b
+#define mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x432b
+#define mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x462b
+#define mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x492b
+#define mmOVLSCL_EDGE_PIXEL_CNTL 0x1a2c
+#define mmDCP0_OVLSCL_EDGE_PIXEL_CNTL 0x1a2c
+#define mmDCP1_OVLSCL_EDGE_PIXEL_CNTL 0x1d2c
+#define mmDCP2_OVLSCL_EDGE_PIXEL_CNTL 0x402c
+#define mmDCP3_OVLSCL_EDGE_PIXEL_CNTL 0x432c
+#define mmDCP4_OVLSCL_EDGE_PIXEL_CNTL 0x462c
+#define mmDCP5_OVLSCL_EDGE_PIXEL_CNTL 0x492c
+#define mmPRESCALE_GRPH_CONTROL 0x1a2d
+#define mmDCP0_PRESCALE_GRPH_CONTROL 0x1a2d
+#define mmDCP1_PRESCALE_GRPH_CONTROL 0x1d2d
+#define mmDCP2_PRESCALE_GRPH_CONTROL 0x402d
+#define mmDCP3_PRESCALE_GRPH_CONTROL 0x432d
+#define mmDCP4_PRESCALE_GRPH_CONTROL 0x462d
+#define mmDCP5_PRESCALE_GRPH_CONTROL 0x492d
+#define mmPRESCALE_VALUES_GRPH_R 0x1a2e
+#define mmDCP0_PRESCALE_VALUES_GRPH_R 0x1a2e
+#define mmDCP1_PRESCALE_VALUES_GRPH_R 0x1d2e
+#define mmDCP2_PRESCALE_VALUES_GRPH_R 0x402e
+#define mmDCP3_PRESCALE_VALUES_GRPH_R 0x432e
+#define mmDCP4_PRESCALE_VALUES_GRPH_R 0x462e
+#define mmDCP5_PRESCALE_VALUES_GRPH_R 0x492e
+#define mmPRESCALE_VALUES_GRPH_G 0x1a2f
+#define mmDCP0_PRESCALE_VALUES_GRPH_G 0x1a2f
+#define mmDCP1_PRESCALE_VALUES_GRPH_G 0x1d2f
+#define mmDCP2_PRESCALE_VALUES_GRPH_G 0x402f
+#define mmDCP3_PRESCALE_VALUES_GRPH_G 0x432f
+#define mmDCP4_PRESCALE_VALUES_GRPH_G 0x462f
+#define mmDCP5_PRESCALE_VALUES_GRPH_G 0x492f
+#define mmPRESCALE_VALUES_GRPH_B 0x1a30
+#define mmDCP0_PRESCALE_VALUES_GRPH_B 0x1a30
+#define mmDCP1_PRESCALE_VALUES_GRPH_B 0x1d30
+#define mmDCP2_PRESCALE_VALUES_GRPH_B 0x4030
+#define mmDCP3_PRESCALE_VALUES_GRPH_B 0x4330
+#define mmDCP4_PRESCALE_VALUES_GRPH_B 0x4630
+#define mmDCP5_PRESCALE_VALUES_GRPH_B 0x4930
+#define mmPRESCALE_OVL_CONTROL 0x1a31
+#define mmDCP0_PRESCALE_OVL_CONTROL 0x1a31
+#define mmDCP1_PRESCALE_OVL_CONTROL 0x1d31
+#define mmDCP2_PRESCALE_OVL_CONTROL 0x4031
+#define mmDCP3_PRESCALE_OVL_CONTROL 0x4331
+#define mmDCP4_PRESCALE_OVL_CONTROL 0x4631
+#define mmDCP5_PRESCALE_OVL_CONTROL 0x4931
+#define mmPRESCALE_VALUES_OVL_CB 0x1a32
+#define mmDCP0_PRESCALE_VALUES_OVL_CB 0x1a32
+#define mmDCP1_PRESCALE_VALUES_OVL_CB 0x1d32
+#define mmDCP2_PRESCALE_VALUES_OVL_CB 0x4032
+#define mmDCP3_PRESCALE_VALUES_OVL_CB 0x4332
+#define mmDCP4_PRESCALE_VALUES_OVL_CB 0x4632
+#define mmDCP5_PRESCALE_VALUES_OVL_CB 0x4932
+#define mmPRESCALE_VALUES_OVL_Y 0x1a33
+#define mmDCP0_PRESCALE_VALUES_OVL_Y 0x1a33
+#define mmDCP1_PRESCALE_VALUES_OVL_Y 0x1d33
+#define mmDCP2_PRESCALE_VALUES_OVL_Y 0x4033
+#define mmDCP3_PRESCALE_VALUES_OVL_Y 0x4333
+#define mmDCP4_PRESCALE_VALUES_OVL_Y 0x4633
+#define mmDCP5_PRESCALE_VALUES_OVL_Y 0x4933
+#define mmPRESCALE_VALUES_OVL_CR 0x1a34
+#define mmDCP0_PRESCALE_VALUES_OVL_CR 0x1a34
+#define mmDCP1_PRESCALE_VALUES_OVL_CR 0x1d34
+#define mmDCP2_PRESCALE_VALUES_OVL_CR 0x4034
+#define mmDCP3_PRESCALE_VALUES_OVL_CR 0x4334
+#define mmDCP4_PRESCALE_VALUES_OVL_CR 0x4634
+#define mmDCP5_PRESCALE_VALUES_OVL_CR 0x4934
+#define mmINPUT_CSC_CONTROL 0x1a35
+#define mmDCP0_INPUT_CSC_CONTROL 0x1a35
+#define mmDCP1_INPUT_CSC_CONTROL 0x1d35
+#define mmDCP2_INPUT_CSC_CONTROL 0x4035
+#define mmDCP3_INPUT_CSC_CONTROL 0x4335
+#define mmDCP4_INPUT_CSC_CONTROL 0x4635
+#define mmDCP5_INPUT_CSC_CONTROL 0x4935
+#define mmINPUT_CSC_C11_C12 0x1a36
+#define mmDCP0_INPUT_CSC_C11_C12 0x1a36
+#define mmDCP1_INPUT_CSC_C11_C12 0x1d36
+#define mmDCP2_INPUT_CSC_C11_C12 0x4036
+#define mmDCP3_INPUT_CSC_C11_C12 0x4336
+#define mmDCP4_INPUT_CSC_C11_C12 0x4636
+#define mmDCP5_INPUT_CSC_C11_C12 0x4936
+#define mmINPUT_CSC_C13_C14 0x1a37
+#define mmDCP0_INPUT_CSC_C13_C14 0x1a37
+#define mmDCP1_INPUT_CSC_C13_C14 0x1d37
+#define mmDCP2_INPUT_CSC_C13_C14 0x4037
+#define mmDCP3_INPUT_CSC_C13_C14 0x4337
+#define mmDCP4_INPUT_CSC_C13_C14 0x4637
+#define mmDCP5_INPUT_CSC_C13_C14 0x4937
+#define mmINPUT_CSC_C21_C22 0x1a38
+#define mmDCP0_INPUT_CSC_C21_C22 0x1a38
+#define mmDCP1_INPUT_CSC_C21_C22 0x1d38
+#define mmDCP2_INPUT_CSC_C21_C22 0x4038
+#define mmDCP3_INPUT_CSC_C21_C22 0x4338
+#define mmDCP4_INPUT_CSC_C21_C22 0x4638
+#define mmDCP5_INPUT_CSC_C21_C22 0x4938
+#define mmINPUT_CSC_C23_C24 0x1a39
+#define mmDCP0_INPUT_CSC_C23_C24 0x1a39
+#define mmDCP1_INPUT_CSC_C23_C24 0x1d39
+#define mmDCP2_INPUT_CSC_C23_C24 0x4039
+#define mmDCP3_INPUT_CSC_C23_C24 0x4339
+#define mmDCP4_INPUT_CSC_C23_C24 0x4639
+#define mmDCP5_INPUT_CSC_C23_C24 0x4939
+#define mmINPUT_CSC_C31_C32 0x1a3a
+#define mmDCP0_INPUT_CSC_C31_C32 0x1a3a
+#define mmDCP1_INPUT_CSC_C31_C32 0x1d3a
+#define mmDCP2_INPUT_CSC_C31_C32 0x403a
+#define mmDCP3_INPUT_CSC_C31_C32 0x433a
+#define mmDCP4_INPUT_CSC_C31_C32 0x463a
+#define mmDCP5_INPUT_CSC_C31_C32 0x493a
+#define mmINPUT_CSC_C33_C34 0x1a3b
+#define mmDCP0_INPUT_CSC_C33_C34 0x1a3b
+#define mmDCP1_INPUT_CSC_C33_C34 0x1d3b
+#define mmDCP2_INPUT_CSC_C33_C34 0x403b
+#define mmDCP3_INPUT_CSC_C33_C34 0x433b
+#define mmDCP4_INPUT_CSC_C33_C34 0x463b
+#define mmDCP5_INPUT_CSC_C33_C34 0x493b
+#define mmOUTPUT_CSC_CONTROL 0x1a3c
+#define mmDCP0_OUTPUT_CSC_CONTROL 0x1a3c
+#define mmDCP1_OUTPUT_CSC_CONTROL 0x1d3c
+#define mmDCP2_OUTPUT_CSC_CONTROL 0x403c
+#define mmDCP3_OUTPUT_CSC_CONTROL 0x433c
+#define mmDCP4_OUTPUT_CSC_CONTROL 0x463c
+#define mmDCP5_OUTPUT_CSC_CONTROL 0x493c
+#define mmOUTPUT_CSC_C11_C12 0x1a3d
+#define mmDCP0_OUTPUT_CSC_C11_C12 0x1a3d
+#define mmDCP1_OUTPUT_CSC_C11_C12 0x1d3d
+#define mmDCP2_OUTPUT_CSC_C11_C12 0x403d
+#define mmDCP3_OUTPUT_CSC_C11_C12 0x433d
+#define mmDCP4_OUTPUT_CSC_C11_C12 0x463d
+#define mmDCP5_OUTPUT_CSC_C11_C12 0x493d
+#define mmOUTPUT_CSC_C13_C14 0x1a3e
+#define mmDCP0_OUTPUT_CSC_C13_C14 0x1a3e
+#define mmDCP1_OUTPUT_CSC_C13_C14 0x1d3e
+#define mmDCP2_OUTPUT_CSC_C13_C14 0x403e
+#define mmDCP3_OUTPUT_CSC_C13_C14 0x433e
+#define mmDCP4_OUTPUT_CSC_C13_C14 0x463e
+#define mmDCP5_OUTPUT_CSC_C13_C14 0x493e
+#define mmOUTPUT_CSC_C21_C22 0x1a3f
+#define mmDCP0_OUTPUT_CSC_C21_C22 0x1a3f
+#define mmDCP1_OUTPUT_CSC_C21_C22 0x1d3f
+#define mmDCP2_OUTPUT_CSC_C21_C22 0x403f
+#define mmDCP3_OUTPUT_CSC_C21_C22 0x433f
+#define mmDCP4_OUTPUT_CSC_C21_C22 0x463f
+#define mmDCP5_OUTPUT_CSC_C21_C22 0x493f
+#define mmOUTPUT_CSC_C23_C24 0x1a40
+#define mmDCP0_OUTPUT_CSC_C23_C24 0x1a40
+#define mmDCP1_OUTPUT_CSC_C23_C24 0x1d40
+#define mmDCP2_OUTPUT_CSC_C23_C24 0x4040
+#define mmDCP3_OUTPUT_CSC_C23_C24 0x4340
+#define mmDCP4_OUTPUT_CSC_C23_C24 0x4640
+#define mmDCP5_OUTPUT_CSC_C23_C24 0x4940
+#define mmOUTPUT_CSC_C31_C32 0x1a41
+#define mmDCP0_OUTPUT_CSC_C31_C32 0x1a41
+#define mmDCP1_OUTPUT_CSC_C31_C32 0x1d41
+#define mmDCP2_OUTPUT_CSC_C31_C32 0x4041
+#define mmDCP3_OUTPUT_CSC_C31_C32 0x4341
+#define mmDCP4_OUTPUT_CSC_C31_C32 0x4641
+#define mmDCP5_OUTPUT_CSC_C31_C32 0x4941
+#define mmOUTPUT_CSC_C33_C34 0x1a42
+#define mmDCP0_OUTPUT_CSC_C33_C34 0x1a42
+#define mmDCP1_OUTPUT_CSC_C33_C34 0x1d42
+#define mmDCP2_OUTPUT_CSC_C33_C34 0x4042
+#define mmDCP3_OUTPUT_CSC_C33_C34 0x4342
+#define mmDCP4_OUTPUT_CSC_C33_C34 0x4642
+#define mmDCP5_OUTPUT_CSC_C33_C34 0x4942
+#define mmCOMM_MATRIXA_TRANS_C11_C12 0x1a43
+#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1a43
+#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1d43
+#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x4043
+#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4343
+#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4643
+#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4943
+#define mmCOMM_MATRIXA_TRANS_C13_C14 0x1a44
+#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1a44
+#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1d44
+#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x4044
+#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4344
+#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4644
+#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4944
+#define mmCOMM_MATRIXA_TRANS_C21_C22 0x1a45
+#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1a45
+#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1d45
+#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x4045
+#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4345
+#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4645
+#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4945
+#define mmCOMM_MATRIXA_TRANS_C23_C24 0x1a46
+#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1a46
+#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1d46
+#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x4046
+#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4346
+#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4646
+#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4946
+#define mmCOMM_MATRIXA_TRANS_C31_C32 0x1a47
+#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1a47
+#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1d47
+#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x4047
+#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4347
+#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4647
+#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4947
+#define mmCOMM_MATRIXA_TRANS_C33_C34 0x1a48
+#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1a48
+#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1d48
+#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x4048
+#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4348
+#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4648
+#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4948
+#define mmCOMM_MATRIXB_TRANS_C11_C12 0x1a49
+#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1a49
+#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1d49
+#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x4049
+#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4349
+#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4649
+#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4949
+#define mmCOMM_MATRIXB_TRANS_C13_C14 0x1a4a
+#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1a4a
+#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1d4a
+#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x404a
+#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x434a
+#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x464a
+#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x494a
+#define mmCOMM_MATRIXB_TRANS_C21_C22 0x1a4b
+#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1a4b
+#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1d4b
+#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x404b
+#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x434b
+#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x464b
+#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x494b
+#define mmCOMM_MATRIXB_TRANS_C23_C24 0x1a4c
+#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1a4c
+#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1d4c
+#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x404c
+#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x434c
+#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x464c
+#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x494c
+#define mmCOMM_MATRIXB_TRANS_C31_C32 0x1a4d
+#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1a4d
+#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1d4d
+#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x404d
+#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x434d
+#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x464d
+#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x494d
+#define mmCOMM_MATRIXB_TRANS_C33_C34 0x1a4e
+#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1a4e
+#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1d4e
+#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x404e
+#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x434e
+#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x464e
+#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x494e
+#define mmDENORM_CONTROL 0x1a50
+#define mmDCP0_DENORM_CONTROL 0x1a50
+#define mmDCP1_DENORM_CONTROL 0x1d50
+#define mmDCP2_DENORM_CONTROL 0x4050
+#define mmDCP3_DENORM_CONTROL 0x4350
+#define mmDCP4_DENORM_CONTROL 0x4650
+#define mmDCP5_DENORM_CONTROL 0x4950
+#define mmOUT_ROUND_CONTROL 0x1a51
+#define mmDCP0_OUT_ROUND_CONTROL 0x1a51
+#define mmDCP1_OUT_ROUND_CONTROL 0x1d51
+#define mmDCP2_OUT_ROUND_CONTROL 0x4051
+#define mmDCP3_OUT_ROUND_CONTROL 0x4351
+#define mmDCP4_OUT_ROUND_CONTROL 0x4651
+#define mmDCP5_OUT_ROUND_CONTROL 0x4951
+#define mmOUT_CLAMP_CONTROL_R_CR 0x1a52
+#define mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x1a52
+#define mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x1d52
+#define mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x4052
+#define mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x4352
+#define mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x4652
+#define mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x4952
+#define mmOUT_CLAMP_CONTROL_G_Y 0x1a9c
+#define mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x1a9c
+#define mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x1d9c
+#define mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x409c
+#define mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x439c
+#define mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x469c
+#define mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x499c
+#define mmOUT_CLAMP_CONTROL_B_CB 0x1a9d
+#define mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x1a9d
+#define mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x1d9d
+#define mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x409d
+#define mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x439d
+#define mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x469d
+#define mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x499d
+#define mmKEY_CONTROL 0x1a53
+#define mmDCP0_KEY_CONTROL 0x1a53
+#define mmDCP1_KEY_CONTROL 0x1d53
+#define mmDCP2_KEY_CONTROL 0x4053
+#define mmDCP3_KEY_CONTROL 0x4353
+#define mmDCP4_KEY_CONTROL 0x4653
+#define mmDCP5_KEY_CONTROL 0x4953
+#define mmKEY_RANGE_ALPHA 0x1a54
+#define mmDCP0_KEY_RANGE_ALPHA 0x1a54
+#define mmDCP1_KEY_RANGE_ALPHA 0x1d54
+#define mmDCP2_KEY_RANGE_ALPHA 0x4054
+#define mmDCP3_KEY_RANGE_ALPHA 0x4354
+#define mmDCP4_KEY_RANGE_ALPHA 0x4654
+#define mmDCP5_KEY_RANGE_ALPHA 0x4954
+#define mmKEY_RANGE_RED 0x1a55
+#define mmDCP0_KEY_RANGE_RED 0x1a55
+#define mmDCP1_KEY_RANGE_RED 0x1d55
+#define mmDCP2_KEY_RANGE_RED 0x4055
+#define mmDCP3_KEY_RANGE_RED 0x4355
+#define mmDCP4_KEY_RANGE_RED 0x4655
+#define mmDCP5_KEY_RANGE_RED 0x4955
+#define mmKEY_RANGE_GREEN 0x1a56
+#define mmDCP0_KEY_RANGE_GREEN 0x1a56
+#define mmDCP1_KEY_RANGE_GREEN 0x1d56
+#define mmDCP2_KEY_RANGE_GREEN 0x4056
+#define mmDCP3_KEY_RANGE_GREEN 0x4356
+#define mmDCP4_KEY_RANGE_GREEN 0x4656
+#define mmDCP5_KEY_RANGE_GREEN 0x4956
+#define mmKEY_RANGE_BLUE 0x1a57
+#define mmDCP0_KEY_RANGE_BLUE 0x1a57
+#define mmDCP1_KEY_RANGE_BLUE 0x1d57
+#define mmDCP2_KEY_RANGE_BLUE 0x4057
+#define mmDCP3_KEY_RANGE_BLUE 0x4357
+#define mmDCP4_KEY_RANGE_BLUE 0x4657
+#define mmDCP5_KEY_RANGE_BLUE 0x4957
+#define mmDEGAMMA_CONTROL 0x1a58
+#define mmDCP0_DEGAMMA_CONTROL 0x1a58
+#define mmDCP1_DEGAMMA_CONTROL 0x1d58
+#define mmDCP2_DEGAMMA_CONTROL 0x4058
+#define mmDCP3_DEGAMMA_CONTROL 0x4358
+#define mmDCP4_DEGAMMA_CONTROL 0x4658
+#define mmDCP5_DEGAMMA_CONTROL 0x4958
+#define mmGAMUT_REMAP_CONTROL 0x1a59
+#define mmDCP0_GAMUT_REMAP_CONTROL 0x1a59
+#define mmDCP1_GAMUT_REMAP_CONTROL 0x1d59
+#define mmDCP2_GAMUT_REMAP_CONTROL 0x4059
+#define mmDCP3_GAMUT_REMAP_CONTROL 0x4359
+#define mmDCP4_GAMUT_REMAP_CONTROL 0x4659
+#define mmDCP5_GAMUT_REMAP_CONTROL 0x4959
+#define mmGAMUT_REMAP_C11_C12 0x1a5a
+#define mmDCP0_GAMUT_REMAP_C11_C12 0x1a5a
+#define mmDCP1_GAMUT_REMAP_C11_C12 0x1d5a
+#define mmDCP2_GAMUT_REMAP_C11_C12 0x405a
+#define mmDCP3_GAMUT_REMAP_C11_C12 0x435a
+#define mmDCP4_GAMUT_REMAP_C11_C12 0x465a
+#define mmDCP5_GAMUT_REMAP_C11_C12 0x495a
+#define mmGAMUT_REMAP_C13_C14 0x1a5b
+#define mmDCP0_GAMUT_REMAP_C13_C14 0x1a5b
+#define mmDCP1_GAMUT_REMAP_C13_C14 0x1d5b
+#define mmDCP2_GAMUT_REMAP_C13_C14 0x405b
+#define mmDCP3_GAMUT_REMAP_C13_C14 0x435b
+#define mmDCP4_GAMUT_REMAP_C13_C14 0x465b
+#define mmDCP5_GAMUT_REMAP_C13_C14 0x495b
+#define mmGAMUT_REMAP_C21_C22 0x1a5c
+#define mmDCP0_GAMUT_REMAP_C21_C22 0x1a5c
+#define mmDCP1_GAMUT_REMAP_C21_C22 0x1d5c
+#define mmDCP2_GAMUT_REMAP_C21_C22 0x405c
+#define mmDCP3_GAMUT_REMAP_C21_C22 0x435c
+#define mmDCP4_GAMUT_REMAP_C21_C22 0x465c
+#define mmDCP5_GAMUT_REMAP_C21_C22 0x495c
+#define mmGAMUT_REMAP_C23_C24 0x1a5d
+#define mmDCP0_GAMUT_REMAP_C23_C24 0x1a5d
+#define mmDCP1_GAMUT_REMAP_C23_C24 0x1d5d
+#define mmDCP2_GAMUT_REMAP_C23_C24 0x405d
+#define mmDCP3_GAMUT_REMAP_C23_C24 0x435d
+#define mmDCP4_GAMUT_REMAP_C23_C24 0x465d
+#define mmDCP5_GAMUT_REMAP_C23_C24 0x495d
+#define mmGAMUT_REMAP_C31_C32 0x1a5e
+#define mmDCP0_GAMUT_REMAP_C31_C32 0x1a5e
+#define mmDCP1_GAMUT_REMAP_C31_C32 0x1d5e
+#define mmDCP2_GAMUT_REMAP_C31_C32 0x405e
+#define mmDCP3_GAMUT_REMAP_C31_C32 0x435e
+#define mmDCP4_GAMUT_REMAP_C31_C32 0x465e
+#define mmDCP5_GAMUT_REMAP_C31_C32 0x495e
+#define mmGAMUT_REMAP_C33_C34 0x1a5f
+#define mmDCP0_GAMUT_REMAP_C33_C34 0x1a5f
+#define mmDCP1_GAMUT_REMAP_C33_C34 0x1d5f
+#define mmDCP2_GAMUT_REMAP_C33_C34 0x405f
+#define mmDCP3_GAMUT_REMAP_C33_C34 0x435f
+#define mmDCP4_GAMUT_REMAP_C33_C34 0x465f
+#define mmDCP5_GAMUT_REMAP_C33_C34 0x495f
+#define mmDCP_SPATIAL_DITHER_CNTL 0x1a60
+#define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1a60
+#define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1d60
+#define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x4060
+#define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4360
+#define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4660
+#define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4960
+#define mmDCP_RANDOM_SEEDS 0x1a61
+#define mmDCP0_DCP_RANDOM_SEEDS 0x1a61
+#define mmDCP1_DCP_RANDOM_SEEDS 0x1d61
+#define mmDCP2_DCP_RANDOM_SEEDS 0x4061
+#define mmDCP3_DCP_RANDOM_SEEDS 0x4361
+#define mmDCP4_DCP_RANDOM_SEEDS 0x4661
+#define mmDCP5_DCP_RANDOM_SEEDS 0x4961
+#define mmDCP_FP_CONVERTED_FIELD 0x1a65
+#define mmDCP0_DCP_FP_CONVERTED_FIELD 0x1a65
+#define mmDCP1_DCP_FP_CONVERTED_FIELD 0x1d65
+#define mmDCP2_DCP_FP_CONVERTED_FIELD 0x4065
+#define mmDCP3_DCP_FP_CONVERTED_FIELD 0x4365
+#define mmDCP4_DCP_FP_CONVERTED_FIELD 0x4665
+#define mmDCP5_DCP_FP_CONVERTED_FIELD 0x4965
+#define mmCUR_CONTROL 0x1a66
+#define mmDCP0_CUR_CONTROL 0x1a66
+#define mmDCP1_CUR_CONTROL 0x1d66
+#define mmDCP2_CUR_CONTROL 0x4066
+#define mmDCP3_CUR_CONTROL 0x4366
+#define mmDCP4_CUR_CONTROL 0x4666
+#define mmDCP5_CUR_CONTROL 0x4966
+#define mmCUR_SURFACE_ADDRESS 0x1a67
+#define mmDCP0_CUR_SURFACE_ADDRESS 0x1a67
+#define mmDCP1_CUR_SURFACE_ADDRESS 0x1d67
+#define mmDCP2_CUR_SURFACE_ADDRESS 0x4067
+#define mmDCP3_CUR_SURFACE_ADDRESS 0x4367
+#define mmDCP4_CUR_SURFACE_ADDRESS 0x4667
+#define mmDCP5_CUR_SURFACE_ADDRESS 0x4967
+#define mmCUR_SIZE 0x1a68
+#define mmDCP0_CUR_SIZE 0x1a68
+#define mmDCP1_CUR_SIZE 0x1d68
+#define mmDCP2_CUR_SIZE 0x4068
+#define mmDCP3_CUR_SIZE 0x4368
+#define mmDCP4_CUR_SIZE 0x4668
+#define mmDCP5_CUR_SIZE 0x4968
+#define mmCUR_SURFACE_ADDRESS_HIGH 0x1a69
+#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1a69
+#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1d69
+#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x4069
+#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4369
+#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4669
+#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4969
+#define mmCUR_POSITION 0x1a6a
+#define mmDCP0_CUR_POSITION 0x1a6a
+#define mmDCP1_CUR_POSITION 0x1d6a
+#define mmDCP2_CUR_POSITION 0x406a
+#define mmDCP3_CUR_POSITION 0x436a
+#define mmDCP4_CUR_POSITION 0x466a
+#define mmDCP5_CUR_POSITION 0x496a
+#define mmCUR_HOT_SPOT 0x1a6b
+#define mmDCP0_CUR_HOT_SPOT 0x1a6b
+#define mmDCP1_CUR_HOT_SPOT 0x1d6b
+#define mmDCP2_CUR_HOT_SPOT 0x406b
+#define mmDCP3_CUR_HOT_SPOT 0x436b
+#define mmDCP4_CUR_HOT_SPOT 0x466b
+#define mmDCP5_CUR_HOT_SPOT 0x496b
+#define mmCUR_COLOR1 0x1a6c
+#define mmDCP0_CUR_COLOR1 0x1a6c
+#define mmDCP1_CUR_COLOR1 0x1d6c
+#define mmDCP2_CUR_COLOR1 0x406c
+#define mmDCP3_CUR_COLOR1 0x436c
+#define mmDCP4_CUR_COLOR1 0x466c
+#define mmDCP5_CUR_COLOR1 0x496c
+#define mmCUR_COLOR2 0x1a6d
+#define mmDCP0_CUR_COLOR2 0x1a6d
+#define mmDCP1_CUR_COLOR2 0x1d6d
+#define mmDCP2_CUR_COLOR2 0x406d
+#define mmDCP3_CUR_COLOR2 0x436d
+#define mmDCP4_CUR_COLOR2 0x466d
+#define mmDCP5_CUR_COLOR2 0x496d
+#define mmCUR_UPDATE 0x1a6e
+#define mmDCP0_CUR_UPDATE 0x1a6e
+#define mmDCP1_CUR_UPDATE 0x1d6e
+#define mmDCP2_CUR_UPDATE 0x406e
+#define mmDCP3_CUR_UPDATE 0x436e
+#define mmDCP4_CUR_UPDATE 0x466e
+#define mmDCP5_CUR_UPDATE 0x496e
+#define mmCUR2_CONTROL 0x1a6f
+#define mmDCP0_CUR2_CONTROL 0x1a6f
+#define mmDCP1_CUR2_CONTROL 0x1d6f
+#define mmDCP2_CUR2_CONTROL 0x406f
+#define mmDCP3_CUR2_CONTROL 0x436f
+#define mmDCP4_CUR2_CONTROL 0x466f
+#define mmDCP5_CUR2_CONTROL 0x496f
+#define mmCUR2_SURFACE_ADDRESS 0x1a70
+#define mmDCP0_CUR2_SURFACE_ADDRESS 0x1a70
+#define mmDCP1_CUR2_SURFACE_ADDRESS 0x1d70
+#define mmDCP2_CUR2_SURFACE_ADDRESS 0x4070
+#define mmDCP3_CUR2_SURFACE_ADDRESS 0x4370
+#define mmDCP4_CUR2_SURFACE_ADDRESS 0x4670
+#define mmDCP5_CUR2_SURFACE_ADDRESS 0x4970
+#define mmCUR2_SIZE 0x1a71
+#define mmDCP0_CUR2_SIZE 0x1a71
+#define mmDCP1_CUR2_SIZE 0x1d71
+#define mmDCP2_CUR2_SIZE 0x4071
+#define mmDCP3_CUR2_SIZE 0x4371
+#define mmDCP4_CUR2_SIZE 0x4671
+#define mmDCP5_CUR2_SIZE 0x4971
+#define mmCUR2_SURFACE_ADDRESS_HIGH 0x1a72
+#define mmDCP0_CUR2_SURFACE_ADDRESS_HIGH 0x1a72
+#define mmDCP1_CUR2_SURFACE_ADDRESS_HIGH 0x1d72
+#define mmDCP2_CUR2_SURFACE_ADDRESS_HIGH 0x4072
+#define mmDCP3_CUR2_SURFACE_ADDRESS_HIGH 0x4372
+#define mmDCP4_CUR2_SURFACE_ADDRESS_HIGH 0x4672
+#define mmDCP5_CUR2_SURFACE_ADDRESS_HIGH 0x4972
+#define mmCUR2_POSITION 0x1a73
+#define mmDCP0_CUR2_POSITION 0x1a73
+#define mmDCP1_CUR2_POSITION 0x1d73
+#define mmDCP2_CUR2_POSITION 0x4073
+#define mmDCP3_CUR2_POSITION 0x4373
+#define mmDCP4_CUR2_POSITION 0x4673
+#define mmDCP5_CUR2_POSITION 0x4973
+#define mmCUR2_HOT_SPOT 0x1a74
+#define mmDCP0_CUR2_HOT_SPOT 0x1a74
+#define mmDCP1_CUR2_HOT_SPOT 0x1d74
+#define mmDCP2_CUR2_HOT_SPOT 0x4074
+#define mmDCP3_CUR2_HOT_SPOT 0x4374
+#define mmDCP4_CUR2_HOT_SPOT 0x4674
+#define mmDCP5_CUR2_HOT_SPOT 0x4974
+#define mmCUR2_COLOR1 0x1a75
+#define mmDCP0_CUR2_COLOR1 0x1a75
+#define mmDCP1_CUR2_COLOR1 0x1d75
+#define mmDCP2_CUR2_COLOR1 0x4075
+#define mmDCP3_CUR2_COLOR1 0x4375
+#define mmDCP4_CUR2_COLOR1 0x4675
+#define mmDCP5_CUR2_COLOR1 0x4975
+#define mmCUR2_COLOR2 0x1a76
+#define mmDCP0_CUR2_COLOR2 0x1a76
+#define mmDCP1_CUR2_COLOR2 0x1d76
+#define mmDCP2_CUR2_COLOR2 0x4076
+#define mmDCP3_CUR2_COLOR2 0x4376
+#define mmDCP4_CUR2_COLOR2 0x4676
+#define mmDCP5_CUR2_COLOR2 0x4976
+#define mmCUR2_UPDATE 0x1a77
+#define mmDCP0_CUR2_UPDATE 0x1a77
+#define mmDCP1_CUR2_UPDATE 0x1d77
+#define mmDCP2_CUR2_UPDATE 0x4077
+#define mmDCP3_CUR2_UPDATE 0x4377
+#define mmDCP4_CUR2_UPDATE 0x4677
+#define mmDCP5_CUR2_UPDATE 0x4977
+#define mmCUR_REQUEST_FILTER_CNTL 0x1a99
+#define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1a99
+#define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1d99
+#define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x4099
+#define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4399
+#define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4699
+#define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4999
+#define mmCUR_STEREO_CONTROL 0x1a9a
+#define mmDCP0_CUR_STEREO_CONTROL 0x1a9a
+#define mmDCP1_CUR_STEREO_CONTROL 0x1d9a
+#define mmDCP2_CUR_STEREO_CONTROL 0x409a
+#define mmDCP3_CUR_STEREO_CONTROL 0x439a
+#define mmDCP4_CUR_STEREO_CONTROL 0x469a
+#define mmDCP5_CUR_STEREO_CONTROL 0x499a
+#define mmCUR2_STEREO_CONTROL 0x1a9b
+#define mmDCP0_CUR2_STEREO_CONTROL 0x1a9b
+#define mmDCP1_CUR2_STEREO_CONTROL 0x1d9b
+#define mmDCP2_CUR2_STEREO_CONTROL 0x409b
+#define mmDCP3_CUR2_STEREO_CONTROL 0x439b
+#define mmDCP4_CUR2_STEREO_CONTROL 0x469b
+#define mmDCP5_CUR2_STEREO_CONTROL 0x499b
+#define mmDC_LUT_RW_MODE 0x1a78
+#define mmDCP0_DC_LUT_RW_MODE 0x1a78
+#define mmDCP1_DC_LUT_RW_MODE 0x1d78
+#define mmDCP2_DC_LUT_RW_MODE 0x4078
+#define mmDCP3_DC_LUT_RW_MODE 0x4378
+#define mmDCP4_DC_LUT_RW_MODE 0x4678
+#define mmDCP5_DC_LUT_RW_MODE 0x4978
+#define mmDC_LUT_RW_INDEX 0x1a79
+#define mmDCP0_DC_LUT_RW_INDEX 0x1a79
+#define mmDCP1_DC_LUT_RW_INDEX 0x1d79
+#define mmDCP2_DC_LUT_RW_INDEX 0x4079
+#define mmDCP3_DC_LUT_RW_INDEX 0x4379
+#define mmDCP4_DC_LUT_RW_INDEX 0x4679
+#define mmDCP5_DC_LUT_RW_INDEX 0x4979
+#define mmDC_LUT_SEQ_COLOR 0x1a7a
+#define mmDCP0_DC_LUT_SEQ_COLOR 0x1a7a
+#define mmDCP1_DC_LUT_SEQ_COLOR 0x1d7a
+#define mmDCP2_DC_LUT_SEQ_COLOR 0x407a
+#define mmDCP3_DC_LUT_SEQ_COLOR 0x437a
+#define mmDCP4_DC_LUT_SEQ_COLOR 0x467a
+#define mmDCP5_DC_LUT_SEQ_COLOR 0x497a
+#define mmDC_LUT_PWL_DATA 0x1a7b
+#define mmDCP0_DC_LUT_PWL_DATA 0x1a7b
+#define mmDCP1_DC_LUT_PWL_DATA 0x1d7b
+#define mmDCP2_DC_LUT_PWL_DATA 0x407b
+#define mmDCP3_DC_LUT_PWL_DATA 0x437b
+#define mmDCP4_DC_LUT_PWL_DATA 0x467b
+#define mmDCP5_DC_LUT_PWL_DATA 0x497b
+#define mmDC_LUT_30_COLOR 0x1a7c
+#define mmDCP0_DC_LUT_30_COLOR 0x1a7c
+#define mmDCP1_DC_LUT_30_COLOR 0x1d7c
+#define mmDCP2_DC_LUT_30_COLOR 0x407c
+#define mmDCP3_DC_LUT_30_COLOR 0x437c
+#define mmDCP4_DC_LUT_30_COLOR 0x467c
+#define mmDCP5_DC_LUT_30_COLOR 0x497c
+#define mmDC_LUT_VGA_ACCESS_ENABLE 0x1a7d
+#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1a7d
+#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1d7d
+#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x407d
+#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x437d
+#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x467d
+#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x497d
+#define mmDC_LUT_WRITE_EN_MASK 0x1a7e
+#define mmDCP0_DC_LUT_WRITE_EN_MASK 0x1a7e
+#define mmDCP1_DC_LUT_WRITE_EN_MASK 0x1d7e
+#define mmDCP2_DC_LUT_WRITE_EN_MASK 0x407e
+#define mmDCP3_DC_LUT_WRITE_EN_MASK 0x437e
+#define mmDCP4_DC_LUT_WRITE_EN_MASK 0x467e
+#define mmDCP5_DC_LUT_WRITE_EN_MASK 0x497e
+#define mmDC_LUT_AUTOFILL 0x1a7f
+#define mmDCP0_DC_LUT_AUTOFILL 0x1a7f
+#define mmDCP1_DC_LUT_AUTOFILL 0x1d7f
+#define mmDCP2_DC_LUT_AUTOFILL 0x407f
+#define mmDCP3_DC_LUT_AUTOFILL 0x437f
+#define mmDCP4_DC_LUT_AUTOFILL 0x467f
+#define mmDCP5_DC_LUT_AUTOFILL 0x497f
+#define mmDC_LUT_CONTROL 0x1a80
+#define mmDCP0_DC_LUT_CONTROL 0x1a80
+#define mmDCP1_DC_LUT_CONTROL 0x1d80
+#define mmDCP2_DC_LUT_CONTROL 0x4080
+#define mmDCP3_DC_LUT_CONTROL 0x4380
+#define mmDCP4_DC_LUT_CONTROL 0x4680
+#define mmDCP5_DC_LUT_CONTROL 0x4980
+#define mmDC_LUT_BLACK_OFFSET_BLUE 0x1a81
+#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1a81
+#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1d81
+#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x4081
+#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4381
+#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4681
+#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4981
+#define mmDC_LUT_BLACK_OFFSET_GREEN 0x1a82
+#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1a82
+#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1d82
+#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x4082
+#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4382
+#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4682
+#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4982
+#define mmDC_LUT_BLACK_OFFSET_RED 0x1a83
+#define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1a83
+#define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1d83
+#define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x4083
+#define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4383
+#define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4683
+#define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4983
+#define mmDC_LUT_WHITE_OFFSET_BLUE 0x1a84
+#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1a84
+#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1d84
+#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x4084
+#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4384
+#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4684
+#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4984
+#define mmDC_LUT_WHITE_OFFSET_GREEN 0x1a85
+#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1a85
+#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1d85
+#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x4085
+#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4385
+#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4685
+#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4985
+#define mmDC_LUT_WHITE_OFFSET_RED 0x1a86
+#define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1a86
+#define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1d86
+#define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x4086
+#define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4386
+#define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4686
+#define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4986
+#define mmDCP_CRC_CONTROL 0x1a87
+#define mmDCP0_DCP_CRC_CONTROL 0x1a87
+#define mmDCP1_DCP_CRC_CONTROL 0x1d87
+#define mmDCP2_DCP_CRC_CONTROL 0x4087
+#define mmDCP3_DCP_CRC_CONTROL 0x4387
+#define mmDCP4_DCP_CRC_CONTROL 0x4687
+#define mmDCP5_DCP_CRC_CONTROL 0x4987
+#define mmDCP_CRC_MASK 0x1a88
+#define mmDCP0_DCP_CRC_MASK 0x1a88
+#define mmDCP1_DCP_CRC_MASK 0x1d88
+#define mmDCP2_DCP_CRC_MASK 0x4088
+#define mmDCP3_DCP_CRC_MASK 0x4388
+#define mmDCP4_DCP_CRC_MASK 0x4688
+#define mmDCP5_DCP_CRC_MASK 0x4988
+#define mmDCP_CRC_CURRENT 0x1a89
+#define mmDCP0_DCP_CRC_CURRENT 0x1a89
+#define mmDCP1_DCP_CRC_CURRENT 0x1d89
+#define mmDCP2_DCP_CRC_CURRENT 0x4089
+#define mmDCP3_DCP_CRC_CURRENT 0x4389
+#define mmDCP4_DCP_CRC_CURRENT 0x4689
+#define mmDCP5_DCP_CRC_CURRENT 0x4989
+#define mmDCP_CRC_LAST 0x1a8b
+#define mmDCP0_DCP_CRC_LAST 0x1a8b
+#define mmDCP1_DCP_CRC_LAST 0x1d8b
+#define mmDCP2_DCP_CRC_LAST 0x408b
+#define mmDCP3_DCP_CRC_LAST 0x438b
+#define mmDCP4_DCP_CRC_LAST 0x468b
+#define mmDCP5_DCP_CRC_LAST 0x498b
+#define mmDCP_DEBUG 0x1a8d
+#define mmDCP0_DCP_DEBUG 0x1a8d
+#define mmDCP1_DCP_DEBUG 0x1d8d
+#define mmDCP2_DCP_DEBUG 0x408d
+#define mmDCP3_DCP_DEBUG 0x438d
+#define mmDCP4_DCP_DEBUG 0x468d
+#define mmDCP5_DCP_DEBUG 0x498d
+#define mmGRPH_FLIP_RATE_CNTL 0x1a8e
+#define mmDCP0_GRPH_FLIP_RATE_CNTL 0x1a8e
+#define mmDCP1_GRPH_FLIP_RATE_CNTL 0x1d8e
+#define mmDCP2_GRPH_FLIP_RATE_CNTL 0x408e
+#define mmDCP3_GRPH_FLIP_RATE_CNTL 0x438e
+#define mmDCP4_GRPH_FLIP_RATE_CNTL 0x468e
+#define mmDCP5_GRPH_FLIP_RATE_CNTL 0x498e
+#define mmDCP_GSL_CONTROL 0x1a90
+#define mmDCP0_DCP_GSL_CONTROL 0x1a90
+#define mmDCP1_DCP_GSL_CONTROL 0x1d90
+#define mmDCP2_DCP_GSL_CONTROL 0x4090
+#define mmDCP3_DCP_GSL_CONTROL 0x4390
+#define mmDCP4_DCP_GSL_CONTROL 0x4690
+#define mmDCP5_DCP_GSL_CONTROL 0x4990
+#define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91
+#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91
+#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1d91
+#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091
+#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4391
+#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4691
+#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4991
+#define mmOVL_SECONDARY_SURFACE_ADDRESS 0x1a92
+#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS 0x1a92
+#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS 0x1d92
+#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS 0x4092
+#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS 0x4392
+#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS 0x4692
+#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS 0x4992
+#define mmOVL_STEREOSYNC_FLIP 0x1a93
+#define mmDCP0_OVL_STEREOSYNC_FLIP 0x1a93
+#define mmDCP1_OVL_STEREOSYNC_FLIP 0x1d93
+#define mmDCP2_OVL_STEREOSYNC_FLIP 0x4093
+#define mmDCP3_OVL_STEREOSYNC_FLIP 0x4393
+#define mmDCP4_OVL_STEREOSYNC_FLIP 0x4693
+#define mmDCP5_OVL_STEREOSYNC_FLIP 0x4993
+#define mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94
+#define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94
+#define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1d94
+#define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4094
+#define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4394
+#define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4694
+#define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4994
+#define mmDCP_TEST_DEBUG_INDEX 0x1a95
+#define mmDCP0_DCP_TEST_DEBUG_INDEX 0x1a95
+#define mmDCP1_DCP_TEST_DEBUG_INDEX 0x1d95
+#define mmDCP2_DCP_TEST_DEBUG_INDEX 0x4095
+#define mmDCP3_DCP_TEST_DEBUG_INDEX 0x4395
+#define mmDCP4_DCP_TEST_DEBUG_INDEX 0x4695
+#define mmDCP5_DCP_TEST_DEBUG_INDEX 0x4995
+#define mmDCP_TEST_DEBUG_DATA 0x1a96
+#define mmDCP0_DCP_TEST_DEBUG_DATA 0x1a96
+#define mmDCP1_DCP_TEST_DEBUG_DATA 0x1d96
+#define mmDCP2_DCP_TEST_DEBUG_DATA 0x4096
+#define mmDCP3_DCP_TEST_DEBUG_DATA 0x4396
+#define mmDCP4_DCP_TEST_DEBUG_DATA 0x4696
+#define mmDCP5_DCP_TEST_DEBUG_DATA 0x4996
+#define mmGRPH_STEREOSYNC_FLIP 0x1a97
+#define mmDCP0_GRPH_STEREOSYNC_FLIP 0x1a97
+#define mmDCP1_GRPH_STEREOSYNC_FLIP 0x1d97
+#define mmDCP2_GRPH_STEREOSYNC_FLIP 0x4097
+#define mmDCP3_GRPH_STEREOSYNC_FLIP 0x4397
+#define mmDCP4_GRPH_STEREOSYNC_FLIP 0x4697
+#define mmDCP5_GRPH_STEREOSYNC_FLIP 0x4997
+#define mmDCP_DEBUG2 0x1a98
+#define mmDCP0_DCP_DEBUG2 0x1a98
+#define mmDCP1_DCP_DEBUG2 0x1d98
+#define mmDCP2_DCP_DEBUG2 0x4098
+#define mmDCP3_DCP_DEBUG2 0x4398
+#define mmDCP4_DCP_DEBUG2 0x4698
+#define mmDCP5_DCP_DEBUG2 0x4998
+#define mmHW_ROTATION 0x1a9e
+#define mmDCP0_HW_ROTATION 0x1a9e
+#define mmDCP1_HW_ROTATION 0x1d9e
+#define mmDCP2_HW_ROTATION 0x409e
+#define mmDCP3_HW_ROTATION 0x439e
+#define mmDCP4_HW_ROTATION 0x469e
+#define mmDCP5_HW_ROTATION 0x499e
+#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f
+#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f
+#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1d9f
+#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x409f
+#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x439f
+#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x469f
+#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x499f
+#define mmREGAMMA_CONTROL 0x1aa0
+#define mmDCP0_REGAMMA_CONTROL 0x1aa0
+#define mmDCP1_REGAMMA_CONTROL 0x1da0
+#define mmDCP2_REGAMMA_CONTROL 0x40a0
+#define mmDCP3_REGAMMA_CONTROL 0x43a0
+#define mmDCP4_REGAMMA_CONTROL 0x46a0
+#define mmDCP5_REGAMMA_CONTROL 0x49a0
+#define mmREGAMMA_LUT_INDEX 0x1aa1
+#define mmDCP0_REGAMMA_LUT_INDEX 0x1aa1
+#define mmDCP1_REGAMMA_LUT_INDEX 0x1da1
+#define mmDCP2_REGAMMA_LUT_INDEX 0x40a1
+#define mmDCP3_REGAMMA_LUT_INDEX 0x43a1
+#define mmDCP4_REGAMMA_LUT_INDEX 0x46a1
+#define mmDCP5_REGAMMA_LUT_INDEX 0x49a1
+#define mmREGAMMA_LUT_DATA 0x1aa2
+#define mmDCP0_REGAMMA_LUT_DATA 0x1aa2
+#define mmDCP1_REGAMMA_LUT_DATA 0x1da2
+#define mmDCP2_REGAMMA_LUT_DATA 0x40a2
+#define mmDCP3_REGAMMA_LUT_DATA 0x43a2
+#define mmDCP4_REGAMMA_LUT_DATA 0x46a2
+#define mmDCP5_REGAMMA_LUT_DATA 0x49a2
+#define mmREGAMMA_LUT_WRITE_EN_MASK 0x1aa3
+#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1aa3
+#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1da3
+#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x40a3
+#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x43a3
+#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x46a3
+#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x49a3
+#define mmREGAMMA_CNTLA_START_CNTL 0x1aa4
+#define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1aa4
+#define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1da4
+#define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x40a4
+#define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x43a4
+#define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x46a4
+#define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x49a4
+#define mmREGAMMA_CNTLA_SLOPE_CNTL 0x1aa5
+#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1aa5
+#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1da5
+#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x40a5
+#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x43a5
+#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x46a5
+#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x49a5
+#define mmREGAMMA_CNTLA_END_CNTL1 0x1aa6
+#define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1aa6
+#define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1da6
+#define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x40a6
+#define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x43a6
+#define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x46a6
+#define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x49a6
+#define mmREGAMMA_CNTLA_END_CNTL2 0x1aa7
+#define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1aa7
+#define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1da7
+#define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x40a7
+#define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x43a7
+#define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x46a7
+#define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x49a7
+#define mmREGAMMA_CNTLA_REGION_0_1 0x1aa8
+#define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1aa8
+#define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1da8
+#define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x40a8
+#define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x43a8
+#define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x46a8
+#define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x49a8
+#define mmREGAMMA_CNTLA_REGION_2_3 0x1aa9
+#define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1aa9
+#define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1da9
+#define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x40a9
+#define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x43a9
+#define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x46a9
+#define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x49a9
+#define mmREGAMMA_CNTLA_REGION_4_5 0x1aaa
+#define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1aaa
+#define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1daa
+#define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x40aa
+#define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x43aa
+#define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x46aa
+#define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x49aa
+#define mmREGAMMA_CNTLA_REGION_6_7 0x1aab
+#define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1aab
+#define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1dab
+#define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x40ab
+#define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x43ab
+#define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x46ab
+#define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x49ab
+#define mmREGAMMA_CNTLA_REGION_8_9 0x1aac
+#define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1aac
+#define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1dac
+#define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x40ac
+#define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x43ac
+#define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x46ac
+#define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x49ac
+#define mmREGAMMA_CNTLA_REGION_10_11 0x1aad
+#define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1aad
+#define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1dad
+#define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x40ad
+#define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x43ad
+#define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x46ad
+#define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x49ad
+#define mmREGAMMA_CNTLA_REGION_12_13 0x1aae
+#define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1aae
+#define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1dae
+#define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x40ae
+#define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x43ae
+#define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x46ae
+#define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x49ae
+#define mmREGAMMA_CNTLA_REGION_14_15 0x1aaf
+#define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1aaf
+#define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1daf
+#define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x40af
+#define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x43af
+#define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x46af
+#define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x49af
+#define mmREGAMMA_CNTLB_START_CNTL 0x1ab0
+#define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1ab0
+#define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1db0
+#define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x40b0
+#define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x43b0
+#define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x46b0
+#define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x49b0
+#define mmREGAMMA_CNTLB_SLOPE_CNTL 0x1ab1
+#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1ab1
+#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1db1
+#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x40b1
+#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x43b1
+#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x46b1
+#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x49b1
+#define mmREGAMMA_CNTLB_END_CNTL1 0x1ab2
+#define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1ab2
+#define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1db2
+#define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x40b2
+#define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x43b2
+#define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x46b2
+#define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x49b2
+#define mmREGAMMA_CNTLB_END_CNTL2 0x1ab3
+#define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1ab3
+#define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1db3
+#define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x40b3
+#define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x43b3
+#define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x46b3
+#define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x49b3
+#define mmREGAMMA_CNTLB_REGION_0_1 0x1ab4
+#define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1ab4
+#define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1db4
+#define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x40b4
+#define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x43b4
+#define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x46b4
+#define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x49b4
+#define mmREGAMMA_CNTLB_REGION_2_3 0x1ab5
+#define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1ab5
+#define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1db5
+#define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x40b5
+#define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x43b5
+#define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x46b5
+#define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x49b5
+#define mmREGAMMA_CNTLB_REGION_4_5 0x1ab6
+#define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1ab6
+#define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1db6
+#define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x40b6
+#define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x43b6
+#define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x46b6
+#define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x49b6
+#define mmREGAMMA_CNTLB_REGION_6_7 0x1ab7
+#define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1ab7
+#define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1db7
+#define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x40b7
+#define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x43b7
+#define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x46b7
+#define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x49b7
+#define mmREGAMMA_CNTLB_REGION_8_9 0x1ab8
+#define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1ab8
+#define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1db8
+#define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x40b8
+#define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x43b8
+#define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x46b8
+#define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x49b8
+#define mmREGAMMA_CNTLB_REGION_10_11 0x1ab9
+#define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1ab9
+#define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1db9
+#define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x40b9
+#define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x43b9
+#define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x46b9
+#define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x49b9
+#define mmREGAMMA_CNTLB_REGION_12_13 0x1aba
+#define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1aba
+#define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1dba
+#define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x40ba
+#define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x43ba
+#define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x46ba
+#define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x49ba
+#define mmREGAMMA_CNTLB_REGION_14_15 0x1abb
+#define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1abb
+#define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1dbb
+#define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x40bb
+#define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x43bb
+#define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x46bb
+#define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x49bb
+#define mmALPHA_CONTROL 0x1abc
+#define mmDCP0_ALPHA_CONTROL 0x1abc
+#define mmDCP1_ALPHA_CONTROL 0x1dbc
+#define mmDCP2_ALPHA_CONTROL 0x40bc
+#define mmDCP3_ALPHA_CONTROL 0x43bc
+#define mmDCP4_ALPHA_CONTROL 0x46bc
+#define mmDCP5_ALPHA_CONTROL 0x49bc
+#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd
+#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd
+#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1dbd
+#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x40bd
+#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x43bd
+#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x46bd
+#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x49bd
+#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe
+#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe
+#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1dbe
+#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x40be
+#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x43be
+#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x46be
+#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x49be
+#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf
+#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf
+#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1dbf
+#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x40bf
+#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x43bf
+#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x46bf
+#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x49bf
+#define mmDIG_FE_CNTL 0x1c00
+#define mmDIG0_DIG_FE_CNTL 0x1c00
+#define mmDIG1_DIG_FE_CNTL 0x1f00
+#define mmDIG2_DIG_FE_CNTL 0x4200
+#define mmDIG3_DIG_FE_CNTL 0x4500
+#define mmDIG4_DIG_FE_CNTL 0x4800
+#define mmDIG5_DIG_FE_CNTL 0x4b00
+#define mmDIG6_DIG_FE_CNTL 0x4e00
+#define mmDIG_OUTPUT_CRC_CNTL 0x1c01
+#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x1c01
+#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x1f01
+#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4201
+#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4501
+#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4801
+#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4b01
+#define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x4e01
+#define mmDIG_OUTPUT_CRC_RESULT 0x1c02
+#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x1c02
+#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x1f02
+#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4202
+#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4502
+#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4802
+#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4b02
+#define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x4e02
+#define mmDIG_CLOCK_PATTERN 0x1c03
+#define mmDIG0_DIG_CLOCK_PATTERN 0x1c03
+#define mmDIG1_DIG_CLOCK_PATTERN 0x1f03
+#define mmDIG2_DIG_CLOCK_PATTERN 0x4203
+#define mmDIG3_DIG_CLOCK_PATTERN 0x4503
+#define mmDIG4_DIG_CLOCK_PATTERN 0x4803
+#define mmDIG5_DIG_CLOCK_PATTERN 0x4b03
+#define mmDIG6_DIG_CLOCK_PATTERN 0x4e03
+#define mmDIG_TEST_PATTERN 0x1c04
+#define mmDIG0_DIG_TEST_PATTERN 0x1c04
+#define mmDIG1_DIG_TEST_PATTERN 0x1f04
+#define mmDIG2_DIG_TEST_PATTERN 0x4204
+#define mmDIG3_DIG_TEST_PATTERN 0x4504
+#define mmDIG4_DIG_TEST_PATTERN 0x4804
+#define mmDIG5_DIG_TEST_PATTERN 0x4b04
+#define mmDIG6_DIG_TEST_PATTERN 0x4e04
+#define mmDIG_RANDOM_PATTERN_SEED 0x1c05
+#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x1c05
+#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x1f05
+#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4205
+#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4505
+#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4805
+#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4b05
+#define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x4e05
+#define mmDIG_FIFO_STATUS 0x1c0a
+#define mmDIG0_DIG_FIFO_STATUS 0x1c0a
+#define mmDIG1_DIG_FIFO_STATUS 0x1f0a
+#define mmDIG2_DIG_FIFO_STATUS 0x420a
+#define mmDIG3_DIG_FIFO_STATUS 0x450a
+#define mmDIG4_DIG_FIFO_STATUS 0x480a
+#define mmDIG5_DIG_FIFO_STATUS 0x4b0a
+#define mmDIG6_DIG_FIFO_STATUS 0x4e0a
+#define mmDIG_DISPCLK_SWITCH_CNTL 0x1c08
+#define mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x1c08
+#define mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x1f08
+#define mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4208
+#define mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4508
+#define mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4808
+#define mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4b08
+#define mmDIG6_DIG_DISPCLK_SWITCH_CNTL 0x4e08
+#define mmDIG_DISPCLK_SWITCH_STATUS 0x1c09
+#define mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x1c09
+#define mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x1f09
+#define mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4209
+#define mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4509
+#define mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4809
+#define mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4b09
+#define mmDIG6_DIG_DISPCLK_SWITCH_STATUS 0x4e09
+#define mmHDMI_CONTROL 0x1c0c
+#define mmDIG0_HDMI_CONTROL 0x1c0c
+#define mmDIG1_HDMI_CONTROL 0x1f0c
+#define mmDIG2_HDMI_CONTROL 0x420c
+#define mmDIG3_HDMI_CONTROL 0x450c
+#define mmDIG4_HDMI_CONTROL 0x480c
+#define mmDIG5_HDMI_CONTROL 0x4b0c
+#define mmDIG6_HDMI_CONTROL 0x4e0c
+#define mmHDMI_STATUS 0x1c0d
+#define mmDIG0_HDMI_STATUS 0x1c0d
+#define mmDIG1_HDMI_STATUS 0x1f0d
+#define mmDIG2_HDMI_STATUS 0x420d
+#define mmDIG3_HDMI_STATUS 0x450d
+#define mmDIG4_HDMI_STATUS 0x480d
+#define mmDIG5_HDMI_STATUS 0x4b0d
+#define mmDIG6_HDMI_STATUS 0x4e0d
+#define mmHDMI_AUDIO_PACKET_CONTROL 0x1c0e
+#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x1c0e
+#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x1f0e
+#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x420e
+#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x450e
+#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x480e
+#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4b0e
+#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x4e0e
+#define mmHDMI_ACR_PACKET_CONTROL 0x1c0f
+#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x1c0f
+#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x1f0f
+#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x420f
+#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x450f
+#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x480f
+#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4b0f
+#define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x4e0f
+#define mmHDMI_VBI_PACKET_CONTROL 0x1c10
+#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x1c10
+#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x1f10
+#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4210
+#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4510
+#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4810
+#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4b10
+#define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x4e10
+#define mmHDMI_INFOFRAME_CONTROL0 0x1c11
+#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x1c11
+#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x1f11
+#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4211
+#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4511
+#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4811
+#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4b11
+#define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x4e11
+#define mmHDMI_INFOFRAME_CONTROL1 0x1c12
+#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x1c12
+#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x1f12
+#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4212
+#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4512
+#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4812
+#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4b12
+#define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x4e12
+#define mmHDMI_GENERIC_PACKET_CONTROL0 0x1c13
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x1c13
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x1f13
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4213
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4513
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4813
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4b13
+#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x4e13
+#define mmAFMT_INTERRUPT_STATUS 0x1c14
+#define mmDIG0_AFMT_INTERRUPT_STATUS 0x1c14
+#define mmDIG1_AFMT_INTERRUPT_STATUS 0x1f14
+#define mmDIG2_AFMT_INTERRUPT_STATUS 0x4214
+#define mmDIG3_AFMT_INTERRUPT_STATUS 0x4514
+#define mmDIG4_AFMT_INTERRUPT_STATUS 0x4814
+#define mmDIG5_AFMT_INTERRUPT_STATUS 0x4b14
+#define mmDIG6_AFMT_INTERRUPT_STATUS 0x4e14
+#define mmHDMI_GC 0x1c16
+#define mmDIG0_HDMI_GC 0x1c16
+#define mmDIG1_HDMI_GC 0x1f16
+#define mmDIG2_HDMI_GC 0x4216
+#define mmDIG3_HDMI_GC 0x4516
+#define mmDIG4_HDMI_GC 0x4816
+#define mmDIG5_HDMI_GC 0x4b16
+#define mmDIG6_HDMI_GC 0x4e16
+#define mmAFMT_AUDIO_PACKET_CONTROL2 0x1c17
+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x1c17
+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x1f17
+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4217
+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4517
+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4817
+#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4b17
+#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x4e17
+#define mmAFMT_ISRC1_0 0x1c18
+#define mmDIG0_AFMT_ISRC1_0 0x1c18
+#define mmDIG1_AFMT_ISRC1_0 0x1f18
+#define mmDIG2_AFMT_ISRC1_0 0x4218
+#define mmDIG3_AFMT_ISRC1_0 0x4518
+#define mmDIG4_AFMT_ISRC1_0 0x4818
+#define mmDIG5_AFMT_ISRC1_0 0x4b18
+#define mmDIG6_AFMT_ISRC1_0 0x4e18
+#define mmAFMT_ISRC1_1 0x1c19
+#define mmDIG0_AFMT_ISRC1_1 0x1c19
+#define mmDIG1_AFMT_ISRC1_1 0x1f19
+#define mmDIG2_AFMT_ISRC1_1 0x4219
+#define mmDIG3_AFMT_ISRC1_1 0x4519
+#define mmDIG4_AFMT_ISRC1_1 0x4819
+#define mmDIG5_AFMT_ISRC1_1 0x4b19
+#define mmDIG6_AFMT_ISRC1_1 0x4e19
+#define mmAFMT_ISRC1_2 0x1c1a
+#define mmDIG0_AFMT_ISRC1_2 0x1c1a
+#define mmDIG1_AFMT_ISRC1_2 0x1f1a
+#define mmDIG2_AFMT_ISRC1_2 0x421a
+#define mmDIG3_AFMT_ISRC1_2 0x451a
+#define mmDIG4_AFMT_ISRC1_2 0x481a
+#define mmDIG5_AFMT_ISRC1_2 0x4b1a
+#define mmDIG6_AFMT_ISRC1_2 0x4e1a
+#define mmAFMT_ISRC1_3 0x1c1b
+#define mmDIG0_AFMT_ISRC1_3 0x1c1b
+#define mmDIG1_AFMT_ISRC1_3 0x1f1b
+#define mmDIG2_AFMT_ISRC1_3 0x421b
+#define mmDIG3_AFMT_ISRC1_3 0x451b
+#define mmDIG4_AFMT_ISRC1_3 0x481b
+#define mmDIG5_AFMT_ISRC1_3 0x4b1b
+#define mmDIG6_AFMT_ISRC1_3 0x4e1b
+#define mmAFMT_ISRC1_4 0x1c1c
+#define mmDIG0_AFMT_ISRC1_4 0x1c1c
+#define mmDIG1_AFMT_ISRC1_4 0x1f1c
+#define mmDIG2_AFMT_ISRC1_4 0x421c
+#define mmDIG3_AFMT_ISRC1_4 0x451c
+#define mmDIG4_AFMT_ISRC1_4 0x481c
+#define mmDIG5_AFMT_ISRC1_4 0x4b1c
+#define mmDIG6_AFMT_ISRC1_4 0x4e1c
+#define mmAFMT_ISRC2_0 0x1c1d
+#define mmDIG0_AFMT_ISRC2_0 0x1c1d
+#define mmDIG1_AFMT_ISRC2_0 0x1f1d
+#define mmDIG2_AFMT_ISRC2_0 0x421d
+#define mmDIG3_AFMT_ISRC2_0 0x451d
+#define mmDIG4_AFMT_ISRC2_0 0x481d
+#define mmDIG5_AFMT_ISRC2_0 0x4b1d
+#define mmDIG6_AFMT_ISRC2_0 0x4e1d
+#define mmAFMT_ISRC2_1 0x1c1e
+#define mmDIG0_AFMT_ISRC2_1 0x1c1e
+#define mmDIG1_AFMT_ISRC2_1 0x1f1e
+#define mmDIG2_AFMT_ISRC2_1 0x421e
+#define mmDIG3_AFMT_ISRC2_1 0x451e
+#define mmDIG4_AFMT_ISRC2_1 0x481e
+#define mmDIG5_AFMT_ISRC2_1 0x4b1e
+#define mmDIG6_AFMT_ISRC2_1 0x4e1e
+#define mmAFMT_ISRC2_2 0x1c1f
+#define mmDIG0_AFMT_ISRC2_2 0x1c1f
+#define mmDIG1_AFMT_ISRC2_2 0x1f1f
+#define mmDIG2_AFMT_ISRC2_2 0x421f
+#define mmDIG3_AFMT_ISRC2_2 0x451f
+#define mmDIG4_AFMT_ISRC2_2 0x481f
+#define mmDIG5_AFMT_ISRC2_2 0x4b1f
+#define mmDIG6_AFMT_ISRC2_2 0x4e1f
+#define mmAFMT_ISRC2_3 0x1c20
+#define mmDIG0_AFMT_ISRC2_3 0x1c20
+#define mmDIG1_AFMT_ISRC2_3 0x1f20
+#define mmDIG2_AFMT_ISRC2_3 0x4220
+#define mmDIG3_AFMT_ISRC2_3 0x4520
+#define mmDIG4_AFMT_ISRC2_3 0x4820
+#define mmDIG5_AFMT_ISRC2_3 0x4b20
+#define mmDIG6_AFMT_ISRC2_3 0x4e20
+#define mmAFMT_AVI_INFO0 0x1c21
+#define mmDIG0_AFMT_AVI_INFO0 0x1c21
+#define mmDIG1_AFMT_AVI_INFO0 0x1f21
+#define mmDIG2_AFMT_AVI_INFO0 0x4221
+#define mmDIG3_AFMT_AVI_INFO0 0x4521
+#define mmDIG4_AFMT_AVI_INFO0 0x4821
+#define mmDIG5_AFMT_AVI_INFO0 0x4b21
+#define mmDIG6_AFMT_AVI_INFO0 0x4e21
+#define mmAFMT_AVI_INFO1 0x1c22
+#define mmDIG0_AFMT_AVI_INFO1 0x1c22
+#define mmDIG1_AFMT_AVI_INFO1 0x1f22
+#define mmDIG2_AFMT_AVI_INFO1 0x4222
+#define mmDIG3_AFMT_AVI_INFO1 0x4522
+#define mmDIG4_AFMT_AVI_INFO1 0x4822
+#define mmDIG5_AFMT_AVI_INFO1 0x4b22
+#define mmDIG6_AFMT_AVI_INFO1 0x4e22
+#define mmAFMT_AVI_INFO2 0x1c23
+#define mmDIG0_AFMT_AVI_INFO2 0x1c23
+#define mmDIG1_AFMT_AVI_INFO2 0x1f23
+#define mmDIG2_AFMT_AVI_INFO2 0x4223
+#define mmDIG3_AFMT_AVI_INFO2 0x4523
+#define mmDIG4_AFMT_AVI_INFO2 0x4823
+#define mmDIG5_AFMT_AVI_INFO2 0x4b23
+#define mmDIG6_AFMT_AVI_INFO2 0x4e23
+#define mmAFMT_AVI_INFO3 0x1c24
+#define mmDIG0_AFMT_AVI_INFO3 0x1c24
+#define mmDIG1_AFMT_AVI_INFO3 0x1f24
+#define mmDIG2_AFMT_AVI_INFO3 0x4224
+#define mmDIG3_AFMT_AVI_INFO3 0x4524
+#define mmDIG4_AFMT_AVI_INFO3 0x4824
+#define mmDIG5_AFMT_AVI_INFO3 0x4b24
+#define mmDIG6_AFMT_AVI_INFO3 0x4e24
+#define mmAFMT_MPEG_INFO0 0x1c25
+#define mmDIG0_AFMT_MPEG_INFO0 0x1c25
+#define mmDIG1_AFMT_MPEG_INFO0 0x1f25
+#define mmDIG2_AFMT_MPEG_INFO0 0x4225
+#define mmDIG3_AFMT_MPEG_INFO0 0x4525
+#define mmDIG4_AFMT_MPEG_INFO0 0x4825
+#define mmDIG5_AFMT_MPEG_INFO0 0x4b25
+#define mmDIG6_AFMT_MPEG_INFO0 0x4e25
+#define mmAFMT_MPEG_INFO1 0x1c26
+#define mmDIG0_AFMT_MPEG_INFO1 0x1c26
+#define mmDIG1_AFMT_MPEG_INFO1 0x1f26
+#define mmDIG2_AFMT_MPEG_INFO1 0x4226
+#define mmDIG3_AFMT_MPEG_INFO1 0x4526
+#define mmDIG4_AFMT_MPEG_INFO1 0x4826
+#define mmDIG5_AFMT_MPEG_INFO1 0x4b26
+#define mmDIG6_AFMT_MPEG_INFO1 0x4e26
+#define mmAFMT_GENERIC_HDR 0x1c27
+#define mmDIG0_AFMT_GENERIC_HDR 0x1c27
+#define mmDIG1_AFMT_GENERIC_HDR 0x1f27
+#define mmDIG2_AFMT_GENERIC_HDR 0x4227
+#define mmDIG3_AFMT_GENERIC_HDR 0x4527
+#define mmDIG4_AFMT_GENERIC_HDR 0x4827
+#define mmDIG5_AFMT_GENERIC_HDR 0x4b27
+#define mmDIG6_AFMT_GENERIC_HDR 0x4e27
+#define mmAFMT_GENERIC_0 0x1c28
+#define mmDIG0_AFMT_GENERIC_0 0x1c28
+#define mmDIG1_AFMT_GENERIC_0 0x1f28
+#define mmDIG2_AFMT_GENERIC_0 0x4228
+#define mmDIG3_AFMT_GENERIC_0 0x4528
+#define mmDIG4_AFMT_GENERIC_0 0x4828
+#define mmDIG5_AFMT_GENERIC_0 0x4b28
+#define mmDIG6_AFMT_GENERIC_0 0x4e28
+#define mmAFMT_GENERIC_1 0x1c29
+#define mmDIG0_AFMT_GENERIC_1 0x1c29
+#define mmDIG1_AFMT_GENERIC_1 0x1f29
+#define mmDIG2_AFMT_GENERIC_1 0x4229
+#define mmDIG3_AFMT_GENERIC_1 0x4529
+#define mmDIG4_AFMT_GENERIC_1 0x4829
+#define mmDIG5_AFMT_GENERIC_1 0x4b29
+#define mmDIG6_AFMT_GENERIC_1 0x4e29
+#define mmAFMT_GENERIC_2 0x1c2a
+#define mmDIG0_AFMT_GENERIC_2 0x1c2a
+#define mmDIG1_AFMT_GENERIC_2 0x1f2a
+#define mmDIG2_AFMT_GENERIC_2 0x422a
+#define mmDIG3_AFMT_GENERIC_2 0x452a
+#define mmDIG4_AFMT_GENERIC_2 0x482a
+#define mmDIG5_AFMT_GENERIC_2 0x4b2a
+#define mmDIG6_AFMT_GENERIC_2 0x4e2a
+#define mmAFMT_GENERIC_3 0x1c2b
+#define mmDIG0_AFMT_GENERIC_3 0x1c2b
+#define mmDIG1_AFMT_GENERIC_3 0x1f2b
+#define mmDIG2_AFMT_GENERIC_3 0x422b
+#define mmDIG3_AFMT_GENERIC_3 0x452b
+#define mmDIG4_AFMT_GENERIC_3 0x482b
+#define mmDIG5_AFMT_GENERIC_3 0x4b2b
+#define mmDIG6_AFMT_GENERIC_3 0x4e2b
+#define mmAFMT_GENERIC_4 0x1c2c
+#define mmDIG0_AFMT_GENERIC_4 0x1c2c
+#define mmDIG1_AFMT_GENERIC_4 0x1f2c
+#define mmDIG2_AFMT_GENERIC_4 0x422c
+#define mmDIG3_AFMT_GENERIC_4 0x452c
+#define mmDIG4_AFMT_GENERIC_4 0x482c
+#define mmDIG5_AFMT_GENERIC_4 0x4b2c
+#define mmDIG6_AFMT_GENERIC_4 0x4e2c
+#define mmAFMT_GENERIC_5 0x1c2d
+#define mmDIG0_AFMT_GENERIC_5 0x1c2d
+#define mmDIG1_AFMT_GENERIC_5 0x1f2d
+#define mmDIG2_AFMT_GENERIC_5 0x422d
+#define mmDIG3_AFMT_GENERIC_5 0x452d
+#define mmDIG4_AFMT_GENERIC_5 0x482d
+#define mmDIG5_AFMT_GENERIC_5 0x4b2d
+#define mmDIG6_AFMT_GENERIC_5 0x4e2d
+#define mmAFMT_GENERIC_6 0x1c2e
+#define mmDIG0_AFMT_GENERIC_6 0x1c2e
+#define mmDIG1_AFMT_GENERIC_6 0x1f2e
+#define mmDIG2_AFMT_GENERIC_6 0x422e
+#define mmDIG3_AFMT_GENERIC_6 0x452e
+#define mmDIG4_AFMT_GENERIC_6 0x482e
+#define mmDIG5_AFMT_GENERIC_6 0x4b2e
+#define mmDIG6_AFMT_GENERIC_6 0x4e2e
+#define mmAFMT_GENERIC_7 0x1c2f
+#define mmDIG0_AFMT_GENERIC_7 0x1c2f
+#define mmDIG1_AFMT_GENERIC_7 0x1f2f
+#define mmDIG2_AFMT_GENERIC_7 0x422f
+#define mmDIG3_AFMT_GENERIC_7 0x452f
+#define mmDIG4_AFMT_GENERIC_7 0x482f
+#define mmDIG5_AFMT_GENERIC_7 0x4b2f
+#define mmDIG6_AFMT_GENERIC_7 0x4e2f
+#define mmHDMI_GENERIC_PACKET_CONTROL1 0x1c30
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x1c30
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x1f30
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4230
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4530
+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4830
+#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4b30
+#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x4e30
+#define mmHDMI_ACR_32_0 0x1c37
+#define mmDIG0_HDMI_ACR_32_0 0x1c37
+#define mmDIG1_HDMI_ACR_32_0 0x1f37
+#define mmDIG2_HDMI_ACR_32_0 0x4237
+#define mmDIG3_HDMI_ACR_32_0 0x4537
+#define mmDIG4_HDMI_ACR_32_0 0x4837
+#define mmDIG5_HDMI_ACR_32_0 0x4b37
+#define mmDIG6_HDMI_ACR_32_0 0x4e37
+#define mmHDMI_ACR_32_1 0x1c38
+#define mmDIG0_HDMI_ACR_32_1 0x1c38
+#define mmDIG1_HDMI_ACR_32_1 0x1f38
+#define mmDIG2_HDMI_ACR_32_1 0x4238
+#define mmDIG3_HDMI_ACR_32_1 0x4538
+#define mmDIG4_HDMI_ACR_32_1 0x4838
+#define mmDIG5_HDMI_ACR_32_1 0x4b38
+#define mmDIG6_HDMI_ACR_32_1 0x4e38
+#define mmHDMI_ACR_44_0 0x1c39
+#define mmDIG0_HDMI_ACR_44_0 0x1c39
+#define mmDIG1_HDMI_ACR_44_0 0x1f39
+#define mmDIG2_HDMI_ACR_44_0 0x4239
+#define mmDIG3_HDMI_ACR_44_0 0x4539
+#define mmDIG4_HDMI_ACR_44_0 0x4839
+#define mmDIG5_HDMI_ACR_44_0 0x4b39
+#define mmDIG6_HDMI_ACR_44_0 0x4e39
+#define mmHDMI_ACR_44_1 0x1c3a
+#define mmDIG0_HDMI_ACR_44_1 0x1c3a
+#define mmDIG1_HDMI_ACR_44_1 0x1f3a
+#define mmDIG2_HDMI_ACR_44_1 0x423a
+#define mmDIG3_HDMI_ACR_44_1 0x453a
+#define mmDIG4_HDMI_ACR_44_1 0x483a
+#define mmDIG5_HDMI_ACR_44_1 0x4b3a
+#define mmDIG6_HDMI_ACR_44_1 0x4e3a
+#define mmHDMI_ACR_48_0 0x1c3b
+#define mmDIG0_HDMI_ACR_48_0 0x1c3b
+#define mmDIG1_HDMI_ACR_48_0 0x1f3b
+#define mmDIG2_HDMI_ACR_48_0 0x423b
+#define mmDIG3_HDMI_ACR_48_0 0x453b
+#define mmDIG4_HDMI_ACR_48_0 0x483b
+#define mmDIG5_HDMI_ACR_48_0 0x4b3b
+#define mmDIG6_HDMI_ACR_48_0 0x4e3b
+#define mmHDMI_ACR_48_1 0x1c3c
+#define mmDIG0_HDMI_ACR_48_1 0x1c3c
+#define mmDIG1_HDMI_ACR_48_1 0x1f3c
+#define mmDIG2_HDMI_ACR_48_1 0x423c
+#define mmDIG3_HDMI_ACR_48_1 0x453c
+#define mmDIG4_HDMI_ACR_48_1 0x483c
+#define mmDIG5_HDMI_ACR_48_1 0x4b3c
+#define mmDIG6_HDMI_ACR_48_1 0x4e3c
+#define mmHDMI_ACR_STATUS_0 0x1c3d
+#define mmDIG0_HDMI_ACR_STATUS_0 0x1c3d
+#define mmDIG1_HDMI_ACR_STATUS_0 0x1f3d
+#define mmDIG2_HDMI_ACR_STATUS_0 0x423d
+#define mmDIG3_HDMI_ACR_STATUS_0 0x453d
+#define mmDIG4_HDMI_ACR_STATUS_0 0x483d
+#define mmDIG5_HDMI_ACR_STATUS_0 0x4b3d
+#define mmDIG6_HDMI_ACR_STATUS_0 0x4e3d
+#define mmHDMI_ACR_STATUS_1 0x1c3e
+#define mmDIG0_HDMI_ACR_STATUS_1 0x1c3e
+#define mmDIG1_HDMI_ACR_STATUS_1 0x1f3e
+#define mmDIG2_HDMI_ACR_STATUS_1 0x423e
+#define mmDIG3_HDMI_ACR_STATUS_1 0x453e
+#define mmDIG4_HDMI_ACR_STATUS_1 0x483e
+#define mmDIG5_HDMI_ACR_STATUS_1 0x4b3e
+#define mmDIG6_HDMI_ACR_STATUS_1 0x4e3e
+#define mmAFMT_AUDIO_INFO0 0x1c3f
+#define mmDIG0_AFMT_AUDIO_INFO0 0x1c3f
+#define mmDIG1_AFMT_AUDIO_INFO0 0x1f3f
+#define mmDIG2_AFMT_AUDIO_INFO0 0x423f
+#define mmDIG3_AFMT_AUDIO_INFO0 0x453f
+#define mmDIG4_AFMT_AUDIO_INFO0 0x483f
+#define mmDIG5_AFMT_AUDIO_INFO0 0x4b3f
+#define mmDIG6_AFMT_AUDIO_INFO0 0x4e3f
+#define mmAFMT_AUDIO_INFO1 0x1c40
+#define mmDIG0_AFMT_AUDIO_INFO1 0x1c40
+#define mmDIG1_AFMT_AUDIO_INFO1 0x1f40
+#define mmDIG2_AFMT_AUDIO_INFO1 0x4240
+#define mmDIG3_AFMT_AUDIO_INFO1 0x4540
+#define mmDIG4_AFMT_AUDIO_INFO1 0x4840
+#define mmDIG5_AFMT_AUDIO_INFO1 0x4b40
+#define mmDIG6_AFMT_AUDIO_INFO1 0x4e40
+#define mmAFMT_60958_0 0x1c41
+#define mmDIG0_AFMT_60958_0 0x1c41
+#define mmDIG1_AFMT_60958_0 0x1f41
+#define mmDIG2_AFMT_60958_0 0x4241
+#define mmDIG3_AFMT_60958_0 0x4541
+#define mmDIG4_AFMT_60958_0 0x4841
+#define mmDIG5_AFMT_60958_0 0x4b41
+#define mmDIG6_AFMT_60958_0 0x4e41
+#define mmAFMT_60958_1 0x1c42
+#define mmDIG0_AFMT_60958_1 0x1c42
+#define mmDIG1_AFMT_60958_1 0x1f42
+#define mmDIG2_AFMT_60958_1 0x4242
+#define mmDIG3_AFMT_60958_1 0x4542
+#define mmDIG4_AFMT_60958_1 0x4842
+#define mmDIG5_AFMT_60958_1 0x4b42
+#define mmDIG6_AFMT_60958_1 0x4e42
+#define mmAFMT_AUDIO_CRC_CONTROL 0x1c43
+#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x1c43
+#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x1f43
+#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4243
+#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4543
+#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4843
+#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4b43
+#define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x4e43
+#define mmAFMT_RAMP_CONTROL0 0x1c44
+#define mmDIG0_AFMT_RAMP_CONTROL0 0x1c44
+#define mmDIG1_AFMT_RAMP_CONTROL0 0x1f44
+#define mmDIG2_AFMT_RAMP_CONTROL0 0x4244
+#define mmDIG3_AFMT_RAMP_CONTROL0 0x4544
+#define mmDIG4_AFMT_RAMP_CONTROL0 0x4844
+#define mmDIG5_AFMT_RAMP_CONTROL0 0x4b44
+#define mmDIG6_AFMT_RAMP_CONTROL0 0x4e44
+#define mmAFMT_RAMP_CONTROL1 0x1c45
+#define mmDIG0_AFMT_RAMP_CONTROL1 0x1c45
+#define mmDIG1_AFMT_RAMP_CONTROL1 0x1f45
+#define mmDIG2_AFMT_RAMP_CONTROL1 0x4245
+#define mmDIG3_AFMT_RAMP_CONTROL1 0x4545
+#define mmDIG4_AFMT_RAMP_CONTROL1 0x4845
+#define mmDIG5_AFMT_RAMP_CONTROL1 0x4b45
+#define mmDIG6_AFMT_RAMP_CONTROL1 0x4e45
+#define mmAFMT_RAMP_CONTROL2 0x1c46
+#define mmDIG0_AFMT_RAMP_CONTROL2 0x1c46
+#define mmDIG1_AFMT_RAMP_CONTROL2 0x1f46
+#define mmDIG2_AFMT_RAMP_CONTROL2 0x4246
+#define mmDIG3_AFMT_RAMP_CONTROL2 0x4546
+#define mmDIG4_AFMT_RAMP_CONTROL2 0x4846
+#define mmDIG5_AFMT_RAMP_CONTROL2 0x4b46
+#define mmDIG6_AFMT_RAMP_CONTROL2 0x4e46
+#define mmAFMT_RAMP_CONTROL3 0x1c47
+#define mmDIG0_AFMT_RAMP_CONTROL3 0x1c47
+#define mmDIG1_AFMT_RAMP_CONTROL3 0x1f47
+#define mmDIG2_AFMT_RAMP_CONTROL3 0x4247
+#define mmDIG3_AFMT_RAMP_CONTROL3 0x4547
+#define mmDIG4_AFMT_RAMP_CONTROL3 0x4847
+#define mmDIG5_AFMT_RAMP_CONTROL3 0x4b47
+#define mmDIG6_AFMT_RAMP_CONTROL3 0x4e47
+#define mmAFMT_60958_2 0x1c48
+#define mmDIG0_AFMT_60958_2 0x1c48
+#define mmDIG1_AFMT_60958_2 0x1f48
+#define mmDIG2_AFMT_60958_2 0x4248
+#define mmDIG3_AFMT_60958_2 0x4548
+#define mmDIG4_AFMT_60958_2 0x4848
+#define mmDIG5_AFMT_60958_2 0x4b48
+#define mmDIG6_AFMT_60958_2 0x4e48
+#define mmAFMT_AUDIO_CRC_RESULT 0x1c49
+#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x1c49
+#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x1f49
+#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4249
+#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4549
+#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4849
+#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4b49
+#define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x4e49
+#define mmAFMT_STATUS 0x1c4a
+#define mmDIG0_AFMT_STATUS 0x1c4a
+#define mmDIG1_AFMT_STATUS 0x1f4a
+#define mmDIG2_AFMT_STATUS 0x424a
+#define mmDIG3_AFMT_STATUS 0x454a
+#define mmDIG4_AFMT_STATUS 0x484a
+#define mmDIG5_AFMT_STATUS 0x4b4a
+#define mmDIG6_AFMT_STATUS 0x4e4a
+#define mmAFMT_AUDIO_PACKET_CONTROL 0x1c4b
+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x1c4b
+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x1f4b
+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x424b
+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x454b
+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x484b
+#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4b4b
+#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x4e4b
+#define mmAFMT_VBI_PACKET_CONTROL 0x1c4c
+#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x1c4c
+#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x1f4c
+#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x424c
+#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x454c
+#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x484c
+#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4b4c
+#define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x4e4c
+#define mmAFMT_INFOFRAME_CONTROL0 0x1c4d
+#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x1c4d
+#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x1f4d
+#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x424d
+#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x454d
+#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x484d
+#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4b4d
+#define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x4e4d
+#define mmAFMT_AUDIO_SRC_CONTROL 0x1c4f
+#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x1c4f
+#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x1f4f
+#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x424f
+#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x454f
+#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x484f
+#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4b4f
+#define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x4e4f
+#define mmAFMT_AUDIO_DBG_DTO_CNTL 0x1c52
+#define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x1c52
+#define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x1f52
+#define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4252
+#define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4552
+#define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4852
+#define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4b52
+#define mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL 0x4e52
+#define mmDIG_BE_CNTL 0x1c50
+#define mmDIG0_DIG_BE_CNTL 0x1c50
+#define mmDIG1_DIG_BE_CNTL 0x1f50
+#define mmDIG2_DIG_BE_CNTL 0x4250
+#define mmDIG3_DIG_BE_CNTL 0x4550
+#define mmDIG4_DIG_BE_CNTL 0x4850
+#define mmDIG5_DIG_BE_CNTL 0x4b50
+#define mmDIG6_DIG_BE_CNTL 0x4e50
+#define mmDIG_BE_EN_CNTL 0x1c51
+#define mmDIG0_DIG_BE_EN_CNTL 0x1c51
+#define mmDIG1_DIG_BE_EN_CNTL 0x1f51
+#define mmDIG2_DIG_BE_EN_CNTL 0x4251
+#define mmDIG3_DIG_BE_EN_CNTL 0x4551
+#define mmDIG4_DIG_BE_EN_CNTL 0x4851
+#define mmDIG5_DIG_BE_EN_CNTL 0x4b51
+#define mmDIG6_DIG_BE_EN_CNTL 0x4e51
+#define mmTMDS_CNTL 0x1c7c
+#define mmDIG0_TMDS_CNTL 0x1c7c
+#define mmDIG1_TMDS_CNTL 0x1f7c
+#define mmDIG2_TMDS_CNTL 0x427c
+#define mmDIG3_TMDS_CNTL 0x457c
+#define mmDIG4_TMDS_CNTL 0x487c
+#define mmDIG5_TMDS_CNTL 0x4b7c
+#define mmDIG6_TMDS_CNTL 0x4e7c
+#define mmTMDS_CONTROL_CHAR 0x1c7d
+#define mmDIG0_TMDS_CONTROL_CHAR 0x1c7d
+#define mmDIG1_TMDS_CONTROL_CHAR 0x1f7d
+#define mmDIG2_TMDS_CONTROL_CHAR 0x427d
+#define mmDIG3_TMDS_CONTROL_CHAR 0x457d
+#define mmDIG4_TMDS_CONTROL_CHAR 0x487d
+#define mmDIG5_TMDS_CONTROL_CHAR 0x4b7d
+#define mmDIG6_TMDS_CONTROL_CHAR 0x4e7d
+#define mmTMDS_CONTROL0_FEEDBACK 0x1c7e
+#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x1c7e
+#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x1f7e
+#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x427e
+#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x457e
+#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x487e
+#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4b7e
+#define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x4e7e
+#define mmTMDS_STEREOSYNC_CTL_SEL 0x1c7f
+#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x1c7f
+#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x1f7f
+#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x427f
+#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x457f
+#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x487f
+#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4b7f
+#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x4e7f
+#define mmTMDS_SYNC_CHAR_PATTERN_0_1 0x1c80
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x1c80
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x1f80
+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4280
+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4580
+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4880
+#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4b80
+#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x4e80
+#define mmTMDS_SYNC_CHAR_PATTERN_2_3 0x1c81
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x1c81
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x1f81
+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4281
+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4581
+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4881
+#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4b81
+#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x4e81
+#define mmTMDS_DEBUG 0x1c82
+#define mmDIG0_TMDS_DEBUG 0x1c82
+#define mmDIG1_TMDS_DEBUG 0x1f82
+#define mmDIG2_TMDS_DEBUG 0x4282
+#define mmDIG3_TMDS_DEBUG 0x4582
+#define mmDIG4_TMDS_DEBUG 0x4882
+#define mmDIG5_TMDS_DEBUG 0x4b82
+#define mmDIG6_TMDS_DEBUG 0x4e82
+#define mmTMDS_CTL_BITS 0x1c83
+#define mmDIG0_TMDS_CTL_BITS 0x1c83
+#define mmDIG1_TMDS_CTL_BITS 0x1f83
+#define mmDIG2_TMDS_CTL_BITS 0x4283
+#define mmDIG3_TMDS_CTL_BITS 0x4583
+#define mmDIG4_TMDS_CTL_BITS 0x4883
+#define mmDIG5_TMDS_CTL_BITS 0x4b83
+#define mmDIG6_TMDS_CTL_BITS 0x4e83
+#define mmTMDS_DCBALANCER_CONTROL 0x1c84
+#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x1c84
+#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x1f84
+#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x4284
+#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x4584
+#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x4884
+#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4b84
+#define mmDIG6_TMDS_DCBALANCER_CONTROL 0x4e84
+#define mmTMDS_CTL0_1_GEN_CNTL 0x1c86
+#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x1c86
+#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x1f86
+#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4286
+#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4586
+#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4886
+#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4b86
+#define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x4e86
+#define mmTMDS_CTL2_3_GEN_CNTL 0x1c87
+#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x1c87
+#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x1f87
+#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4287
+#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4587
+#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4887
+#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4b87
+#define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x4e87
+#define mmLVDS_DATA_CNTL 0x1c8c
+#define mmDIG0_LVDS_DATA_CNTL 0x1c8c
+#define mmDIG1_LVDS_DATA_CNTL 0x1f8c
+#define mmDIG2_LVDS_DATA_CNTL 0x428c
+#define mmDIG3_LVDS_DATA_CNTL 0x458c
+#define mmDIG4_LVDS_DATA_CNTL 0x488c
+#define mmDIG5_LVDS_DATA_CNTL 0x4b8c
+#define mmDIG6_LVDS_DATA_CNTL 0x4e8c
+#define mmDIG_LANE_ENABLE 0x1c8d
+#define mmDIG0_DIG_LANE_ENABLE 0x1c8d
+#define mmDIG1_DIG_LANE_ENABLE 0x1f8d
+#define mmDIG2_DIG_LANE_ENABLE 0x428d
+#define mmDIG3_DIG_LANE_ENABLE 0x458d
+#define mmDIG4_DIG_LANE_ENABLE 0x488d
+#define mmDIG5_DIG_LANE_ENABLE 0x4b8d
+#define mmDIG6_DIG_LANE_ENABLE 0x4e8d
+#define mmDOUT_SCRATCH0 0x1844
+#define mmDOUT_SCRATCH1 0x1845
+#define mmDOUT_SCRATCH2 0x1846
+#define mmDOUT_SCRATCH3 0x1847
+#define mmDOUT_SCRATCH4 0x1848
+#define mmDOUT_SCRATCH5 0x1849
+#define mmDOUT_SCRATCH6 0x184a
+#define mmDOUT_SCRATCH7 0x184b
+#define mmDOUT_DCE_VCE_CONTROL 0x18ff
+#define mmDC_HPD1_INT_STATUS 0x1807
+#define mmDC_HPD1_INT_CONTROL 0x1808
+#define mmDC_HPD1_CONTROL 0x1809
+#define mmDC_HPD2_INT_STATUS 0x180a
+#define mmDC_HPD2_INT_CONTROL 0x180b
+#define mmDC_HPD2_CONTROL 0x180c
+#define mmDC_HPD3_INT_STATUS 0x180d
+#define mmDC_HPD3_INT_CONTROL 0x180e
+#define mmDC_HPD3_CONTROL 0x180f
+#define mmDC_HPD4_INT_STATUS 0x1810
+#define mmDC_HPD4_INT_CONTROL 0x1811
+#define mmDC_HPD4_CONTROL 0x1812
+#define mmDC_HPD5_INT_STATUS 0x1813
+#define mmDC_HPD5_INT_CONTROL 0x1814
+#define mmDC_HPD5_CONTROL 0x1815
+#define mmDC_HPD6_INT_STATUS 0x1816
+#define mmDC_HPD6_INT_CONTROL 0x1817
+#define mmDC_HPD6_CONTROL 0x1818
+#define mmDC_HPD1_FAST_TRAIN_CNTL 0x1864
+#define mmDC_HPD2_FAST_TRAIN_CNTL 0x1865
+#define mmDC_HPD3_FAST_TRAIN_CNTL 0x1866
+#define mmDC_HPD4_FAST_TRAIN_CNTL 0x1867
+#define mmDC_HPD5_FAST_TRAIN_CNTL 0x1868
+#define mmDC_HPD6_FAST_TRAIN_CNTL 0x1869
+#define mmDC_HPD1_TOGGLE_FILT_CNTL 0x18bc
+#define mmDC_HPD2_TOGGLE_FILT_CNTL 0x18bd
+#define mmDC_HPD3_TOGGLE_FILT_CNTL 0x18be
+#define mmDC_HPD4_TOGGLE_FILT_CNTL 0x18fc
+#define mmDC_HPD5_TOGGLE_FILT_CNTL 0x18fd
+#define mmDC_HPD6_TOGGLE_FILT_CNTL 0x18fe
+#define mmDC_I2C_CONTROL 0x1819
+#define mmDC_I2C_ARBITRATION 0x181a
+#define mmDC_I2C_INTERRUPT_CONTROL 0x181b
+#define mmDC_I2C_SW_STATUS 0x181c
+#define mmDC_I2C_DDC1_HW_STATUS 0x181d
+#define mmDC_I2C_DDC2_HW_STATUS 0x181e
+#define mmDC_I2C_DDC3_HW_STATUS 0x181f
+#define mmDC_I2C_DDC4_HW_STATUS 0x1820
+#define mmDC_I2C_DDC5_HW_STATUS 0x1821
+#define mmDC_I2C_DDC6_HW_STATUS 0x1822
+#define mmDC_I2C_DDC1_SPEED 0x1823
+#define mmDC_I2C_DDC1_SETUP 0x1824
+#define mmDC_I2C_DDC2_SPEED 0x1825
+#define mmDC_I2C_DDC2_SETUP 0x1826
+#define mmDC_I2C_DDC3_SPEED 0x1827
+#define mmDC_I2C_DDC3_SETUP 0x1828
+#define mmDC_I2C_DDC4_SPEED 0x1829
+#define mmDC_I2C_DDC4_SETUP 0x182a
+#define mmDC_I2C_DDC5_SPEED 0x182b
+#define mmDC_I2C_DDC5_SETUP 0x182c
+#define mmDC_I2C_DDC6_SPEED 0x182d
+#define mmDC_I2C_DDC6_SETUP 0x182e
+#define mmDC_I2C_TRANSACTION0 0x182f
+#define mmDC_I2C_TRANSACTION1 0x1830
+#define mmDC_I2C_TRANSACTION2 0x1831
+#define mmDC_I2C_TRANSACTION3 0x1832
+#define mmDC_I2C_DATA 0x1833
+#define mmGENERIC_I2C_CONTROL 0x1834
+#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x1835
+#define mmGENERIC_I2C_STATUS 0x1836
+#define mmGENERIC_I2C_SPEED 0x1837
+#define mmGENERIC_I2C_SETUP 0x1838
+#define mmGENERIC_I2C_TRANSACTION 0x1839
+#define mmGENERIC_I2C_DATA 0x183a
+#define mmGENERIC_I2C_PIN_SELECTION 0x183b
+#define mmGENERIC_I2C_PIN_DEBUG 0x183c
+#define mmDISP_INTERRUPT_STATUS 0x183d
+#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x183e
+#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x183f
+#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x1840
+#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x1853
+#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x1854
+#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x19e0
+#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x19e1
+#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x19e2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x19e3
+#define mmDOUT_POWER_MANAGEMENT_CNTL 0x1841
+#define mmDISP_TIMER_CONTROL 0x1842
+#define mmDC_I2C_DDCVGA_HW_STATUS 0x1855
+#define mmDC_I2C_DDCVGA_SPEED 0x1856
+#define mmDC_I2C_DDCVGA_SETUP 0x1857
+#define mmDC_I2C_EDID_DETECT_CTRL 0x186f
+#define mmDISPOUT_STEREOSYNC_SEL 0x18bf
+#define mmDOUT_TEST_DEBUG_INDEX 0x184d
+#define mmDOUT_TEST_DEBUG_DATA 0x184e
+#define ixDP_AUX1_DEBUG_A 0x10
+#define ixDP_AUX1_DEBUG_B 0x11
+#define ixDP_AUX1_DEBUG_C 0x12
+#define ixDP_AUX1_DEBUG_D 0x13
+#define ixDP_AUX1_DEBUG_E 0x14
+#define ixDP_AUX1_DEBUG_F 0x15
+#define ixDP_AUX1_DEBUG_G 0x16
+#define ixDP_AUX1_DEBUG_H 0x17
+#define ixDP_AUX1_DEBUG_I 0x18
+#define ixDP_AUX1_DEBUG_J 0x19
+#define ixDP_AUX1_DEBUG_K 0x1a
+#define ixDP_AUX1_DEBUG_L 0x1b
+#define ixDP_AUX1_DEBUG_M 0x1c
+#define ixDP_AUX1_DEBUG_N 0x1d
+#define ixDP_AUX1_DEBUG_O 0x1e
+#define ixDP_AUX1_DEBUG_P 0x1f
+#define ixDP_AUX1_DEBUG_Q 0x90
+#define ixDP_AUX2_DEBUG_A 0x20
+#define ixDP_AUX2_DEBUG_B 0x21
+#define ixDP_AUX2_DEBUG_C 0x22
+#define ixDP_AUX2_DEBUG_D 0x23
+#define ixDP_AUX2_DEBUG_E 0x24
+#define ixDP_AUX2_DEBUG_F 0x25
+#define ixDP_AUX2_DEBUG_G 0x26
+#define ixDP_AUX2_DEBUG_H 0x27
+#define ixDP_AUX2_DEBUG_I 0x28
+#define ixDP_AUX2_DEBUG_J 0x29
+#define ixDP_AUX2_DEBUG_K 0x2a
+#define ixDP_AUX2_DEBUG_L 0x2b
+#define ixDP_AUX2_DEBUG_M 0x2c
+#define ixDP_AUX2_DEBUG_N 0x2d
+#define ixDP_AUX2_DEBUG_O 0x2e
+#define ixDP_AUX2_DEBUG_P 0x2f
+#define ixDP_AUX2_DEBUG_Q 0x91
+#define ixDP_AUX3_DEBUG_A 0x30
+#define ixDP_AUX3_DEBUG_B 0x31
+#define ixDP_AUX3_DEBUG_C 0x32
+#define ixDP_AUX3_DEBUG_D 0x33
+#define ixDP_AUX3_DEBUG_E 0x34
+#define ixDP_AUX3_DEBUG_F 0x35
+#define ixDP_AUX3_DEBUG_G 0x36
+#define ixDP_AUX3_DEBUG_H 0x37
+#define ixDP_AUX3_DEBUG_I 0x38
+#define ixDP_AUX3_DEBUG_J 0x39
+#define ixDP_AUX3_DEBUG_K 0x3a
+#define ixDP_AUX3_DEBUG_L 0x3b
+#define ixDP_AUX3_DEBUG_M 0x3c
+#define ixDP_AUX3_DEBUG_N 0x3d
+#define ixDP_AUX3_DEBUG_O 0x3e
+#define ixDP_AUX3_DEBUG_P 0x3f
+#define ixDP_AUX3_DEBUG_Q 0x92
+#define ixDP_AUX4_DEBUG_A 0x40
+#define ixDP_AUX4_DEBUG_B 0x41
+#define ixDP_AUX4_DEBUG_C 0x42
+#define ixDP_AUX4_DEBUG_D 0x43
+#define ixDP_AUX4_DEBUG_E 0x44
+#define ixDP_AUX4_DEBUG_F 0x45
+#define ixDP_AUX4_DEBUG_G 0x46
+#define ixDP_AUX4_DEBUG_H 0x47
+#define ixDP_AUX4_DEBUG_I 0x48
+#define ixDP_AUX4_DEBUG_J 0x49
+#define ixDP_AUX4_DEBUG_K 0x4a
+#define ixDP_AUX4_DEBUG_L 0x4b
+#define ixDP_AUX4_DEBUG_M 0x4c
+#define ixDP_AUX4_DEBUG_N 0x4d
+#define ixDP_AUX4_DEBUG_O 0x4e
+#define ixDP_AUX4_DEBUG_P 0x4f
+#define ixDP_AUX4_DEBUG_Q 0x93
+#define ixDP_AUX5_DEBUG_A 0x70
+#define ixDP_AUX5_DEBUG_B 0x71
+#define ixDP_AUX5_DEBUG_C 0x72
+#define ixDP_AUX5_DEBUG_D 0x73
+#define ixDP_AUX5_DEBUG_E 0x74
+#define ixDP_AUX5_DEBUG_F 0x75
+#define ixDP_AUX5_DEBUG_G 0x76
+#define ixDP_AUX5_DEBUG_H 0x77
+#define ixDP_AUX5_DEBUG_I 0x78
+#define ixDP_AUX5_DEBUG_J 0x79
+#define ixDP_AUX5_DEBUG_K 0x7a
+#define ixDP_AUX5_DEBUG_L 0x7b
+#define ixDP_AUX5_DEBUG_M 0x7c
+#define ixDP_AUX5_DEBUG_N 0x7d
+#define ixDP_AUX5_DEBUG_O 0x7f
+#define ixDP_AUX5_DEBUG_P 0x94
+#define ixDP_AUX5_DEBUG_Q 0x95
+#define ixDP_AUX6_DEBUG_A 0x80
+#define ixDP_AUX6_DEBUG_B 0x81
+#define ixDP_AUX6_DEBUG_C 0x82
+#define ixDP_AUX6_DEBUG_D 0x83
+#define ixDP_AUX6_DEBUG_E 0x84
+#define ixDP_AUX6_DEBUG_F 0x85
+#define ixDP_AUX6_DEBUG_G 0x86
+#define ixDP_AUX6_DEBUG_H 0x87
+#define ixDP_AUX6_DEBUG_I 0x88
+#define ixDP_AUX6_DEBUG_J 0x89
+#define ixDP_AUX6_DEBUG_K 0x8a
+#define ixDP_AUX6_DEBUG_L 0x8b
+#define ixDP_AUX6_DEBUG_M 0x8c
+#define ixDP_AUX6_DEBUG_N 0x8d
+#define ixDP_AUX6_DEBUG_O 0x8f
+#define ixDP_AUX6_DEBUG_P 0x96
+#define ixDP_AUX6_DEBUG_Q 0x97
+#define mmDMCU_CTRL 0x1600
+#define mmDMCU_STATUS 0x1601
+#define mmDMCU_PC_START_ADDR 0x1602
+#define mmDMCU_FW_START_ADDR 0x1603
+#define mmDMCU_FW_END_ADDR 0x1604
+#define mmDMCU_FW_ISR_START_ADDR 0x1605
+#define mmDMCU_FW_CS_HI 0x1606
+#define mmDMCU_FW_CS_LO 0x1607
+#define mmDMCU_RAM_ACCESS_CTRL 0x1608
+#define mmDMCU_ERAM_WR_CTRL 0x1609
+#define mmDMCU_ERAM_WR_DATA 0x160a
+#define mmDMCU_ERAM_RD_CTRL 0x160b
+#define mmDMCU_ERAM_RD_DATA 0x160c
+#define mmDMCU_IRAM_WR_CTRL 0x160d
+#define mmDMCU_IRAM_WR_DATA 0x160e
+#define mmDMCU_IRAM_RD_CTRL 0x160f
+#define mmDMCU_IRAM_RD_DATA 0x1610
+#define mmDMCU_EVENT_TRIGGER 0x1611
+#define mmDMCU_UC_INTERNAL_INT_STATUS 0x1612
+#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x1613
+#define mmDMCU_INTERRUPT_STATUS 0x1614
+#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617
+#define mmDC_DMCU_SCRATCH 0x1618
+#define mmDMCU_INT_CNT 0x1619
+#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161a
+#define mmDMCU_UC_CLK_GATING_CNTL 0x161b
+#define mmMASTER_COMM_DATA_REG1 0x161c
+#define mmMASTER_COMM_DATA_REG2 0x161d
+#define mmMASTER_COMM_DATA_REG3 0x161e
+#define mmMASTER_COMM_CMD_REG 0x161f
+#define mmMASTER_COMM_CNTL_REG 0x1620
+#define mmSLAVE_COMM_DATA_REG1 0x1621
+#define mmSLAVE_COMM_DATA_REG2 0x1622
+#define mmSLAVE_COMM_DATA_REG3 0x1623
+#define mmSLAVE_COMM_CMD_REG 0x1624
+#define mmSLAVE_COMM_CNTL_REG 0x1625
+#define mmDMCU_TEST_DEBUG_INDEX 0x1626
+#define mmDMCU_TEST_DEBUG_DATA 0x1627
+#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x1750
+#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x1751
+#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x1752
+#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x1753
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x1754
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x1755
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x1756
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x1757
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1758
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x1759
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x175a
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x175b
+#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1 0x175c
+#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2 0x175d
+#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3 0x175e
+#define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4 0x175f
+#define mmDP_LINK_CNTL 0x1cc0
+#define mmDP0_DP_LINK_CNTL 0x1cc0
+#define mmDP1_DP_LINK_CNTL 0x1fc0
+#define mmDP2_DP_LINK_CNTL 0x42c0
+#define mmDP3_DP_LINK_CNTL 0x45c0
+#define mmDP4_DP_LINK_CNTL 0x48c0
+#define mmDP5_DP_LINK_CNTL 0x4bc0
+#define mmDP6_DP_LINK_CNTL 0x4ec0
+#define mmDP_PIXEL_FORMAT 0x1cc1
+#define mmDP0_DP_PIXEL_FORMAT 0x1cc1
+#define mmDP1_DP_PIXEL_FORMAT 0x1fc1
+#define mmDP2_DP_PIXEL_FORMAT 0x42c1
+#define mmDP3_DP_PIXEL_FORMAT 0x45c1
+#define mmDP4_DP_PIXEL_FORMAT 0x48c1
+#define mmDP5_DP_PIXEL_FORMAT 0x4bc1
+#define mmDP6_DP_PIXEL_FORMAT 0x4ec1
+#define mmDP_MSA_COLORIMETRY 0x1cda
+#define mmDP0_DP_MSA_COLORIMETRY 0x1cda
+#define mmDP1_DP_MSA_COLORIMETRY 0x1fda
+#define mmDP2_DP_MSA_COLORIMETRY 0x42da
+#define mmDP3_DP_MSA_COLORIMETRY 0x45da
+#define mmDP4_DP_MSA_COLORIMETRY 0x48da
+#define mmDP5_DP_MSA_COLORIMETRY 0x4bda
+#define mmDP6_DP_MSA_COLORIMETRY 0x4eda
+#define mmDP_CONFIG 0x1cc2
+#define mmDP0_DP_CONFIG 0x1cc2
+#define mmDP1_DP_CONFIG 0x1fc2
+#define mmDP2_DP_CONFIG 0x42c2
+#define mmDP3_DP_CONFIG 0x45c2
+#define mmDP4_DP_CONFIG 0x48c2
+#define mmDP5_DP_CONFIG 0x4bc2
+#define mmDP6_DP_CONFIG 0x4ec2
+#define mmDP_VID_STREAM_CNTL 0x1cc3
+#define mmDP0_DP_VID_STREAM_CNTL 0x1cc3
+#define mmDP1_DP_VID_STREAM_CNTL 0x1fc3
+#define mmDP2_DP_VID_STREAM_CNTL 0x42c3
+#define mmDP3_DP_VID_STREAM_CNTL 0x45c3
+#define mmDP4_DP_VID_STREAM_CNTL 0x48c3
+#define mmDP5_DP_VID_STREAM_CNTL 0x4bc3
+#define mmDP6_DP_VID_STREAM_CNTL 0x4ec3
+#define mmDP_STEER_FIFO 0x1cc4
+#define mmDP0_DP_STEER_FIFO 0x1cc4
+#define mmDP1_DP_STEER_FIFO 0x1fc4
+#define mmDP2_DP_STEER_FIFO 0x42c4
+#define mmDP3_DP_STEER_FIFO 0x45c4
+#define mmDP4_DP_STEER_FIFO 0x48c4
+#define mmDP5_DP_STEER_FIFO 0x4bc4
+#define mmDP6_DP_STEER_FIFO 0x4ec4
+#define mmDP_MSA_MISC 0x1cc5
+#define mmDP0_DP_MSA_MISC 0x1cc5
+#define mmDP1_DP_MSA_MISC 0x1fc5
+#define mmDP2_DP_MSA_MISC 0x42c5
+#define mmDP3_DP_MSA_MISC 0x45c5
+#define mmDP4_DP_MSA_MISC 0x48c5
+#define mmDP5_DP_MSA_MISC 0x4bc5
+#define mmDP6_DP_MSA_MISC 0x4ec5
+#define mmDP_VID_TIMING 0x1cc9
+#define mmDP0_DP_VID_TIMING 0x1cc9
+#define mmDP1_DP_VID_TIMING 0x1fc9
+#define mmDP2_DP_VID_TIMING 0x42c9
+#define mmDP3_DP_VID_TIMING 0x45c9
+#define mmDP4_DP_VID_TIMING 0x48c9
+#define mmDP5_DP_VID_TIMING 0x4bc9
+#define mmDP6_DP_VID_TIMING 0x4ec9
+#define mmDP_VID_N 0x1cca
+#define mmDP0_DP_VID_N 0x1cca
+#define mmDP1_DP_VID_N 0x1fca
+#define mmDP2_DP_VID_N 0x42ca
+#define mmDP3_DP_VID_N 0x45ca
+#define mmDP4_DP_VID_N 0x48ca
+#define mmDP5_DP_VID_N 0x4bca
+#define mmDP6_DP_VID_N 0x4eca
+#define mmDP_VID_M 0x1ccb
+#define mmDP0_DP_VID_M 0x1ccb
+#define mmDP1_DP_VID_M 0x1fcb
+#define mmDP2_DP_VID_M 0x42cb
+#define mmDP3_DP_VID_M 0x45cb
+#define mmDP4_DP_VID_M 0x48cb
+#define mmDP5_DP_VID_M 0x4bcb
+#define mmDP6_DP_VID_M 0x4ecb
+#define mmDP_LINK_FRAMING_CNTL 0x1ccc
+#define mmDP0_DP_LINK_FRAMING_CNTL 0x1ccc
+#define mmDP1_DP_LINK_FRAMING_CNTL 0x1fcc
+#define mmDP2_DP_LINK_FRAMING_CNTL 0x42cc
+#define mmDP3_DP_LINK_FRAMING_CNTL 0x45cc
+#define mmDP4_DP_LINK_FRAMING_CNTL 0x48cc
+#define mmDP5_DP_LINK_FRAMING_CNTL 0x4bcc
+#define mmDP6_DP_LINK_FRAMING_CNTL 0x4ecc
+#define mmDP_HBR2_EYE_PATTERN 0x1cc8
+#define mmDP0_DP_HBR2_EYE_PATTERN 0x1cc8
+#define mmDP1_DP_HBR2_EYE_PATTERN 0x1fc8
+#define mmDP2_DP_HBR2_EYE_PATTERN 0x42c8
+#define mmDP3_DP_HBR2_EYE_PATTERN 0x45c8
+#define mmDP4_DP_HBR2_EYE_PATTERN 0x48c8
+#define mmDP5_DP_HBR2_EYE_PATTERN 0x4bc8
+#define mmDP6_DP_HBR2_EYE_PATTERN 0x4ec8
+#define mmDP_VID_MSA_VBID 0x1ccd
+#define mmDP0_DP_VID_MSA_VBID 0x1ccd
+#define mmDP1_DP_VID_MSA_VBID 0x1fcd
+#define mmDP2_DP_VID_MSA_VBID 0x42cd
+#define mmDP3_DP_VID_MSA_VBID 0x45cd
+#define mmDP4_DP_VID_MSA_VBID 0x48cd
+#define mmDP5_DP_VID_MSA_VBID 0x4bcd
+#define mmDP6_DP_VID_MSA_VBID 0x4ecd
+#define mmDP_VID_INTERRUPT_CNTL 0x1ccf
+#define mmDP0_DP_VID_INTERRUPT_CNTL 0x1ccf
+#define mmDP1_DP_VID_INTERRUPT_CNTL 0x1fcf
+#define mmDP2_DP_VID_INTERRUPT_CNTL 0x42cf
+#define mmDP3_DP_VID_INTERRUPT_CNTL 0x45cf
+#define mmDP4_DP_VID_INTERRUPT_CNTL 0x48cf
+#define mmDP5_DP_VID_INTERRUPT_CNTL 0x4bcf
+#define mmDP6_DP_VID_INTERRUPT_CNTL 0x4ecf
+#define mmDP_DPHY_CNTL 0x1cd0
+#define mmDP0_DP_DPHY_CNTL 0x1cd0
+#define mmDP1_DP_DPHY_CNTL 0x1fd0
+#define mmDP2_DP_DPHY_CNTL 0x42d0
+#define mmDP3_DP_DPHY_CNTL 0x45d0
+#define mmDP4_DP_DPHY_CNTL 0x48d0
+#define mmDP5_DP_DPHY_CNTL 0x4bd0
+#define mmDP6_DP_DPHY_CNTL 0x4ed0
+#define mmDP_DPHY_TRAINING_PATTERN_SEL 0x1cd1
+#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x1cd1
+#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x1fd1
+#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x42d1
+#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x45d1
+#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x48d1
+#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4bd1
+#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x4ed1
+#define mmDP_DPHY_SYM0 0x1cd2
+#define mmDP0_DP_DPHY_SYM0 0x1cd2
+#define mmDP1_DP_DPHY_SYM0 0x1fd2
+#define mmDP2_DP_DPHY_SYM0 0x42d2
+#define mmDP3_DP_DPHY_SYM0 0x45d2
+#define mmDP4_DP_DPHY_SYM0 0x48d2
+#define mmDP5_DP_DPHY_SYM0 0x4bd2
+#define mmDP6_DP_DPHY_SYM0 0x4ed2
+#define mmDP_DPHY_SYM1 0x1ce0
+#define mmDP0_DP_DPHY_SYM1 0x1ce0
+#define mmDP1_DP_DPHY_SYM1 0x1fe0
+#define mmDP2_DP_DPHY_SYM1 0x42e0
+#define mmDP3_DP_DPHY_SYM1 0x45e0
+#define mmDP4_DP_DPHY_SYM1 0x48e0
+#define mmDP5_DP_DPHY_SYM1 0x4be0
+#define mmDP6_DP_DPHY_SYM1 0x4ee0
+#define mmDP_DPHY_SYM2 0x1cdf
+#define mmDP0_DP_DPHY_SYM2 0x1cdf
+#define mmDP1_DP_DPHY_SYM2 0x1fdf
+#define mmDP2_DP_DPHY_SYM2 0x42df
+#define mmDP3_DP_DPHY_SYM2 0x45df
+#define mmDP4_DP_DPHY_SYM2 0x48df
+#define mmDP5_DP_DPHY_SYM2 0x4bdf
+#define mmDP6_DP_DPHY_SYM2 0x4edf
+#define mmDP_DPHY_8B10B_CNTL 0x1cd3
+#define mmDP0_DP_DPHY_8B10B_CNTL 0x1cd3
+#define mmDP1_DP_DPHY_8B10B_CNTL 0x1fd3
+#define mmDP2_DP_DPHY_8B10B_CNTL 0x42d3
+#define mmDP3_DP_DPHY_8B10B_CNTL 0x45d3
+#define mmDP4_DP_DPHY_8B10B_CNTL 0x48d3
+#define mmDP5_DP_DPHY_8B10B_CNTL 0x4bd3
+#define mmDP6_DP_DPHY_8B10B_CNTL 0x4ed3
+#define mmDP_DPHY_PRBS_CNTL 0x1cd4
+#define mmDP0_DP_DPHY_PRBS_CNTL 0x1cd4
+#define mmDP1_DP_DPHY_PRBS_CNTL 0x1fd4
+#define mmDP2_DP_DPHY_PRBS_CNTL 0x42d4
+#define mmDP3_DP_DPHY_PRBS_CNTL 0x45d4
+#define mmDP4_DP_DPHY_PRBS_CNTL 0x48d4
+#define mmDP5_DP_DPHY_PRBS_CNTL 0x4bd4
+#define mmDP6_DP_DPHY_PRBS_CNTL 0x4ed4
+#define mmDP_DPHY_CRC_EN 0x1cd6
+#define mmDP0_DP_DPHY_CRC_EN 0x1cd6
+#define mmDP1_DP_DPHY_CRC_EN 0x1fd6
+#define mmDP2_DP_DPHY_CRC_EN 0x42d6
+#define mmDP3_DP_DPHY_CRC_EN 0x45d6
+#define mmDP4_DP_DPHY_CRC_EN 0x48d6
+#define mmDP5_DP_DPHY_CRC_EN 0x4bd6
+#define mmDP6_DP_DPHY_CRC_EN 0x4ed6
+#define mmDP_DPHY_CRC_CNTL 0x1cd7
+#define mmDP0_DP_DPHY_CRC_CNTL 0x1cd7
+#define mmDP1_DP_DPHY_CRC_CNTL 0x1fd7
+#define mmDP2_DP_DPHY_CRC_CNTL 0x42d7
+#define mmDP3_DP_DPHY_CRC_CNTL 0x45d7
+#define mmDP4_DP_DPHY_CRC_CNTL 0x48d7
+#define mmDP5_DP_DPHY_CRC_CNTL 0x4bd7
+#define mmDP6_DP_DPHY_CRC_CNTL 0x4ed7
+#define mmDP_DPHY_CRC_RESULT 0x1cd8
+#define mmDP0_DP_DPHY_CRC_RESULT 0x1cd8
+#define mmDP1_DP_DPHY_CRC_RESULT 0x1fd8
+#define mmDP2_DP_DPHY_CRC_RESULT 0x42d8
+#define mmDP3_DP_DPHY_CRC_RESULT 0x45d8
+#define mmDP4_DP_DPHY_CRC_RESULT 0x48d8
+#define mmDP5_DP_DPHY_CRC_RESULT 0x4bd8
+#define mmDP6_DP_DPHY_CRC_RESULT 0x4ed8
+#define mmDP_DPHY_CRC_MST_CNTL 0x1cc6
+#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x1cc6
+#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x1fc6
+#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x42c6
+#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x45c6
+#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x48c6
+#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x4bc6
+#define mmDP6_DP_DPHY_CRC_MST_CNTL 0x4ec6
+#define mmDP_DPHY_CRC_MST_STATUS 0x1cc7
+#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x1cc7
+#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x1fc7
+#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x42c7
+#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x45c7
+#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x48c7
+#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x4bc7
+#define mmDP6_DP_DPHY_CRC_MST_STATUS 0x4ec7
+#define mmDP_DPHY_FAST_TRAINING 0x1cce
+#define mmDP0_DP_DPHY_FAST_TRAINING 0x1cce
+#define mmDP1_DP_DPHY_FAST_TRAINING 0x1fce
+#define mmDP2_DP_DPHY_FAST_TRAINING 0x42ce
+#define mmDP3_DP_DPHY_FAST_TRAINING 0x45ce
+#define mmDP4_DP_DPHY_FAST_TRAINING 0x48ce
+#define mmDP5_DP_DPHY_FAST_TRAINING 0x4bce
+#define mmDP6_DP_DPHY_FAST_TRAINING 0x4ece
+#define mmDP_DPHY_FAST_TRAINING_STATUS 0x1ce9
+#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x1ce9
+#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x1fe9
+#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x42e9
+#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x45e9
+#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x48e9
+#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4be9
+#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x4ee9
+#define mmDP_MSA_V_TIMING_OVERRIDE1 0x1cea
+#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x1cea
+#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x1fea
+#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x42ea
+#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x45ea
+#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x48ea
+#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4bea
+#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x4eea
+#define mmDP_MSA_V_TIMING_OVERRIDE2 0x1ceb
+#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x1ceb
+#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x1feb
+#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x42eb
+#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x45eb
+#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x48eb
+#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4beb
+#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x4eeb
+#define mmDP_SEC_CNTL 0x1ca0
+#define mmDP0_DP_SEC_CNTL 0x1ca0
+#define mmDP1_DP_SEC_CNTL 0x1fa0
+#define mmDP2_DP_SEC_CNTL 0x42a0
+#define mmDP3_DP_SEC_CNTL 0x45a0
+#define mmDP4_DP_SEC_CNTL 0x48a0
+#define mmDP5_DP_SEC_CNTL 0x4ba0
+#define mmDP6_DP_SEC_CNTL 0x4ea0
+#define mmDP_SEC_CNTL1 0x1cab
+#define mmDP0_DP_SEC_CNTL1 0x1cab
+#define mmDP1_DP_SEC_CNTL1 0x1fab
+#define mmDP2_DP_SEC_CNTL1 0x42ab
+#define mmDP3_DP_SEC_CNTL1 0x45ab
+#define mmDP4_DP_SEC_CNTL1 0x48ab
+#define mmDP5_DP_SEC_CNTL1 0x4bab
+#define mmDP6_DP_SEC_CNTL1 0x4eab
+#define mmDP_SEC_FRAMING1 0x1ca1
+#define mmDP0_DP_SEC_FRAMING1 0x1ca1
+#define mmDP1_DP_SEC_FRAMING1 0x1fa1
+#define mmDP2_DP_SEC_FRAMING1 0x42a1
+#define mmDP3_DP_SEC_FRAMING1 0x45a1
+#define mmDP4_DP_SEC_FRAMING1 0x48a1
+#define mmDP5_DP_SEC_FRAMING1 0x4ba1
+#define mmDP6_DP_SEC_FRAMING1 0x4ea1
+#define mmDP_SEC_FRAMING2 0x1ca2
+#define mmDP0_DP_SEC_FRAMING2 0x1ca2
+#define mmDP1_DP_SEC_FRAMING2 0x1fa2
+#define mmDP2_DP_SEC_FRAMING2 0x42a2
+#define mmDP3_DP_SEC_FRAMING2 0x45a2
+#define mmDP4_DP_SEC_FRAMING2 0x48a2
+#define mmDP5_DP_SEC_FRAMING2 0x4ba2
+#define mmDP6_DP_SEC_FRAMING2 0x4ea2
+#define mmDP_SEC_FRAMING3 0x1ca3
+#define mmDP0_DP_SEC_FRAMING3 0x1ca3
+#define mmDP1_DP_SEC_FRAMING3 0x1fa3
+#define mmDP2_DP_SEC_FRAMING3 0x42a3
+#define mmDP3_DP_SEC_FRAMING3 0x45a3
+#define mmDP4_DP_SEC_FRAMING3 0x48a3
+#define mmDP5_DP_SEC_FRAMING3 0x4ba3
+#define mmDP6_DP_SEC_FRAMING3 0x4ea3
+#define mmDP_SEC_FRAMING4 0x1ca4
+#define mmDP0_DP_SEC_FRAMING4 0x1ca4
+#define mmDP1_DP_SEC_FRAMING4 0x1fa4
+#define mmDP2_DP_SEC_FRAMING4 0x42a4
+#define mmDP3_DP_SEC_FRAMING4 0x45a4
+#define mmDP4_DP_SEC_FRAMING4 0x48a4
+#define mmDP5_DP_SEC_FRAMING4 0x4ba4
+#define mmDP6_DP_SEC_FRAMING4 0x4ea4
+#define mmDP_SEC_AUD_N 0x1ca5
+#define mmDP0_DP_SEC_AUD_N 0x1ca5
+#define mmDP1_DP_SEC_AUD_N 0x1fa5
+#define mmDP2_DP_SEC_AUD_N 0x42a5
+#define mmDP3_DP_SEC_AUD_N 0x45a5
+#define mmDP4_DP_SEC_AUD_N 0x48a5
+#define mmDP5_DP_SEC_AUD_N 0x4ba5
+#define mmDP6_DP_SEC_AUD_N 0x4ea5
+#define mmDP_SEC_AUD_N_READBACK 0x1ca6
+#define mmDP0_DP_SEC_AUD_N_READBACK 0x1ca6
+#define mmDP1_DP_SEC_AUD_N_READBACK 0x1fa6
+#define mmDP2_DP_SEC_AUD_N_READBACK 0x42a6
+#define mmDP3_DP_SEC_AUD_N_READBACK 0x45a6
+#define mmDP4_DP_SEC_AUD_N_READBACK 0x48a6
+#define mmDP5_DP_SEC_AUD_N_READBACK 0x4ba6
+#define mmDP6_DP_SEC_AUD_N_READBACK 0x4ea6
+#define mmDP_SEC_AUD_M 0x1ca7
+#define mmDP0_DP_SEC_AUD_M 0x1ca7
+#define mmDP1_DP_SEC_AUD_M 0x1fa7
+#define mmDP2_DP_SEC_AUD_M 0x42a7
+#define mmDP3_DP_SEC_AUD_M 0x45a7
+#define mmDP4_DP_SEC_AUD_M 0x48a7
+#define mmDP5_DP_SEC_AUD_M 0x4ba7
+#define mmDP6_DP_SEC_AUD_M 0x4ea7
+#define mmDP_SEC_AUD_M_READBACK 0x1ca8
+#define mmDP0_DP_SEC_AUD_M_READBACK 0x1ca8
+#define mmDP1_DP_SEC_AUD_M_READBACK 0x1fa8
+#define mmDP2_DP_SEC_AUD_M_READBACK 0x42a8
+#define mmDP3_DP_SEC_AUD_M_READBACK 0x45a8
+#define mmDP4_DP_SEC_AUD_M_READBACK 0x48a8
+#define mmDP5_DP_SEC_AUD_M_READBACK 0x4ba8
+#define mmDP6_DP_SEC_AUD_M_READBACK 0x4ea8
+#define mmDP_SEC_TIMESTAMP 0x1ca9
+#define mmDP0_DP_SEC_TIMESTAMP 0x1ca9
+#define mmDP1_DP_SEC_TIMESTAMP 0x1fa9
+#define mmDP2_DP_SEC_TIMESTAMP 0x42a9
+#define mmDP3_DP_SEC_TIMESTAMP 0x45a9
+#define mmDP4_DP_SEC_TIMESTAMP 0x48a9
+#define mmDP5_DP_SEC_TIMESTAMP 0x4ba9
+#define mmDP6_DP_SEC_TIMESTAMP 0x4ea9
+#define mmDP_SEC_PACKET_CNTL 0x1caa
+#define mmDP0_DP_SEC_PACKET_CNTL 0x1caa
+#define mmDP1_DP_SEC_PACKET_CNTL 0x1faa
+#define mmDP2_DP_SEC_PACKET_CNTL 0x42aa
+#define mmDP3_DP_SEC_PACKET_CNTL 0x45aa
+#define mmDP4_DP_SEC_PACKET_CNTL 0x48aa
+#define mmDP5_DP_SEC_PACKET_CNTL 0x4baa
+#define mmDP6_DP_SEC_PACKET_CNTL 0x4eaa
+#define mmDP_MSE_RATE_CNTL 0x1ce1
+#define mmDP0_DP_MSE_RATE_CNTL 0x1ce1
+#define mmDP1_DP_MSE_RATE_CNTL 0x1fe1
+#define mmDP2_DP_MSE_RATE_CNTL 0x42e1
+#define mmDP3_DP_MSE_RATE_CNTL 0x45e1
+#define mmDP4_DP_MSE_RATE_CNTL 0x48e1
+#define mmDP5_DP_MSE_RATE_CNTL 0x4be1
+#define mmDP6_DP_MSE_RATE_CNTL 0x4ee1
+#define mmDP_MSE_RATE_UPDATE 0x1ce3
+#define mmDP0_DP_MSE_RATE_UPDATE 0x1ce3
+#define mmDP1_DP_MSE_RATE_UPDATE 0x1fe3
+#define mmDP2_DP_MSE_RATE_UPDATE 0x42e3
+#define mmDP3_DP_MSE_RATE_UPDATE 0x45e3
+#define mmDP4_DP_MSE_RATE_UPDATE 0x48e3
+#define mmDP5_DP_MSE_RATE_UPDATE 0x4be3
+#define mmDP6_DP_MSE_RATE_UPDATE 0x4ee3
+#define mmDP_MSE_SAT0 0x1ce4
+#define mmDP0_DP_MSE_SAT0 0x1ce4
+#define mmDP1_DP_MSE_SAT0 0x1fe4
+#define mmDP2_DP_MSE_SAT0 0x42e4
+#define mmDP3_DP_MSE_SAT0 0x45e4
+#define mmDP4_DP_MSE_SAT0 0x48e4
+#define mmDP5_DP_MSE_SAT0 0x4be4
+#define mmDP6_DP_MSE_SAT0 0x4ee4
+#define mmDP_MSE_SAT1 0x1ce5
+#define mmDP0_DP_MSE_SAT1 0x1ce5
+#define mmDP1_DP_MSE_SAT1 0x1fe5
+#define mmDP2_DP_MSE_SAT1 0x42e5
+#define mmDP3_DP_MSE_SAT1 0x45e5
+#define mmDP4_DP_MSE_SAT1 0x48e5
+#define mmDP5_DP_MSE_SAT1 0x4be5
+#define mmDP6_DP_MSE_SAT1 0x4ee5
+#define mmDP_MSE_SAT2 0x1ce6
+#define mmDP0_DP_MSE_SAT2 0x1ce6
+#define mmDP1_DP_MSE_SAT2 0x1fe6
+#define mmDP2_DP_MSE_SAT2 0x42e6
+#define mmDP3_DP_MSE_SAT2 0x45e6
+#define mmDP4_DP_MSE_SAT2 0x48e6
+#define mmDP5_DP_MSE_SAT2 0x4be6
+#define mmDP6_DP_MSE_SAT2 0x4ee6
+#define mmDP_MSE_SAT_UPDATE 0x1ce7
+#define mmDP0_DP_MSE_SAT_UPDATE 0x1ce7
+#define mmDP1_DP_MSE_SAT_UPDATE 0x1fe7
+#define mmDP2_DP_MSE_SAT_UPDATE 0x42e7
+#define mmDP3_DP_MSE_SAT_UPDATE 0x45e7
+#define mmDP4_DP_MSE_SAT_UPDATE 0x48e7
+#define mmDP5_DP_MSE_SAT_UPDATE 0x4be7
+#define mmDP6_DP_MSE_SAT_UPDATE 0x4ee7
+#define mmDP_MSE_LINK_TIMING 0x1ce8
+#define mmDP0_DP_MSE_LINK_TIMING 0x1ce8
+#define mmDP1_DP_MSE_LINK_TIMING 0x1fe8
+#define mmDP2_DP_MSE_LINK_TIMING 0x42e8
+#define mmDP3_DP_MSE_LINK_TIMING 0x45e8
+#define mmDP4_DP_MSE_LINK_TIMING 0x48e8
+#define mmDP5_DP_MSE_LINK_TIMING 0x4be8
+#define mmDP6_DP_MSE_LINK_TIMING 0x4ee8
+#define mmDP_MSE_MISC_CNTL 0x1cdb
+#define mmDP0_DP_MSE_MISC_CNTL 0x1cdb
+#define mmDP1_DP_MSE_MISC_CNTL 0x1fdb
+#define mmDP2_DP_MSE_MISC_CNTL 0x42db
+#define mmDP3_DP_MSE_MISC_CNTL 0x45db
+#define mmDP4_DP_MSE_MISC_CNTL 0x48db
+#define mmDP5_DP_MSE_MISC_CNTL 0x4bdb
+#define mmDP6_DP_MSE_MISC_CNTL 0x4edb
+#define mmDP_TEST_DEBUG_INDEX 0x1cfc
+#define mmDP0_DP_TEST_DEBUG_INDEX 0x1cfc
+#define mmDP1_DP_TEST_DEBUG_INDEX 0x1ffc
+#define mmDP2_DP_TEST_DEBUG_INDEX 0x42fc
+#define mmDP3_DP_TEST_DEBUG_INDEX 0x45fc
+#define mmDP4_DP_TEST_DEBUG_INDEX 0x48fc
+#define mmDP5_DP_TEST_DEBUG_INDEX 0x4bfc
+#define mmDP6_DP_TEST_DEBUG_INDEX 0x4efc
+#define mmDP_TEST_DEBUG_DATA 0x1cfd
+#define mmDP0_DP_TEST_DEBUG_DATA 0x1cfd
+#define mmDP1_DP_TEST_DEBUG_DATA 0x1ffd
+#define mmDP2_DP_TEST_DEBUG_DATA 0x42fd
+#define mmDP3_DP_TEST_DEBUG_DATA 0x45fd
+#define mmDP4_DP_TEST_DEBUG_DATA 0x48fd
+#define mmDP5_DP_TEST_DEBUG_DATA 0x4bfd
+#define mmDP6_DP_TEST_DEBUG_DATA 0x4efd
+#define mmAUX_CONTROL 0x1880
+#define mmDP_AUX0_AUX_CONTROL 0x1880
+#define mmDP_AUX1_AUX_CONTROL 0x1894
+#define mmDP_AUX2_AUX_CONTROL 0x18a8
+#define mmDP_AUX3_AUX_CONTROL 0x18c0
+#define mmDP_AUX4_AUX_CONTROL 0x18d4
+#define mmDP_AUX5_AUX_CONTROL 0x18e8
+#define mmAUX_SW_CONTROL 0x1881
+#define mmDP_AUX0_AUX_SW_CONTROL 0x1881
+#define mmDP_AUX1_AUX_SW_CONTROL 0x1895
+#define mmDP_AUX2_AUX_SW_CONTROL 0x18a9
+#define mmDP_AUX3_AUX_SW_CONTROL 0x18c1
+#define mmDP_AUX4_AUX_SW_CONTROL 0x18d5
+#define mmDP_AUX5_AUX_SW_CONTROL 0x18e9
+#define mmAUX_ARB_CONTROL 0x1882
+#define mmDP_AUX0_AUX_ARB_CONTROL 0x1882
+#define mmDP_AUX1_AUX_ARB_CONTROL 0x1896
+#define mmDP_AUX2_AUX_ARB_CONTROL 0x18aa
+#define mmDP_AUX3_AUX_ARB_CONTROL 0x18c2
+#define mmDP_AUX4_AUX_ARB_CONTROL 0x18d6
+#define mmDP_AUX5_AUX_ARB_CONTROL 0x18ea
+#define mmAUX_INTERRUPT_CONTROL 0x1883
+#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1883
+#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1897
+#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x18ab
+#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x18c3
+#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x18d7
+#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x18eb
+#define mmAUX_SW_STATUS 0x1884
+#define mmDP_AUX0_AUX_SW_STATUS 0x1884
+#define mmDP_AUX1_AUX_SW_STATUS 0x1898
+#define mmDP_AUX2_AUX_SW_STATUS 0x18ac
+#define mmDP_AUX3_AUX_SW_STATUS 0x18c4
+#define mmDP_AUX4_AUX_SW_STATUS 0x18d8
+#define mmDP_AUX5_AUX_SW_STATUS 0x18ec
+#define mmAUX_LS_STATUS 0x1885
+#define mmDP_AUX0_AUX_LS_STATUS 0x1885
+#define mmDP_AUX1_AUX_LS_STATUS 0x1899
+#define mmDP_AUX2_AUX_LS_STATUS 0x18ad
+#define mmDP_AUX3_AUX_LS_STATUS 0x18c5
+#define mmDP_AUX4_AUX_LS_STATUS 0x18d9
+#define mmDP_AUX5_AUX_LS_STATUS 0x18ed
+#define mmAUX_SW_DATA 0x1886
+#define mmDP_AUX0_AUX_SW_DATA 0x1886
+#define mmDP_AUX1_AUX_SW_DATA 0x189a
+#define mmDP_AUX2_AUX_SW_DATA 0x18ae
+#define mmDP_AUX3_AUX_SW_DATA 0x18c6
+#define mmDP_AUX4_AUX_SW_DATA 0x18da
+#define mmDP_AUX5_AUX_SW_DATA 0x18ee
+#define mmAUX_LS_DATA 0x1887
+#define mmDP_AUX0_AUX_LS_DATA 0x1887
+#define mmDP_AUX1_AUX_LS_DATA 0x189b
+#define mmDP_AUX2_AUX_LS_DATA 0x18af
+#define mmDP_AUX3_AUX_LS_DATA 0x18c7
+#define mmDP_AUX4_AUX_LS_DATA 0x18db
+#define mmDP_AUX5_AUX_LS_DATA 0x18ef
+#define mmAUX_DPHY_TX_REF_CONTROL 0x1888
+#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1888
+#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x189c
+#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x18b0
+#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x18c8
+#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x18dc
+#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x18f0
+#define mmAUX_DPHY_TX_CONTROL 0x1889
+#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1889
+#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x189d
+#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x18b1
+#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x18c9
+#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x18dd
+#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x18f1
+#define mmAUX_DPHY_RX_CONTROL0 0x188a
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x188a
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x189e
+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x18b2
+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x18ca
+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x18de
+#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x18f2
+#define mmAUX_DPHY_RX_CONTROL1 0x188b
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x188b
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x189f
+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x18b3
+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x18cb
+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x18df
+#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x18f3
+#define mmAUX_DPHY_TX_STATUS 0x188c
+#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x188c
+#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x18a0
+#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x18b4
+#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x18cc
+#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x18e0
+#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x18f4
+#define mmAUX_DPHY_RX_STATUS 0x188d
+#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x188d
+#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x18a1
+#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x18b5
+#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x18cd
+#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x18e1
+#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x18f5
+#define mmAUX_GTC_SYNC_CONTROL 0x188e
+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x188e
+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x18a2
+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x18b6
+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x18ce
+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x18e2
+#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x18f6
+#define mmAUX_GTC_SYNC_ERROR_CONTROL 0x188f
+#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x188f
+#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x18a3
+#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x18b7
+#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x18cf
+#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x18e3
+#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x18f7
+#define mmAUX_GTC_SYNC_CONTROLLER_STATUS 0x1890
+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1890
+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18a4
+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18b8
+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18d0
+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18e4
+#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x18f8
+#define mmAUX_GTC_SYNC_STATUS 0x1891
+#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1891
+#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x18a5
+#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x18b9
+#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x18d1
+#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x18e5
+#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x18f9
+#define mmAUX_GTC_SYNC_DATA 0x1892
+#define mmDP_AUX0_AUX_GTC_SYNC_DATA 0x1892
+#define mmDP_AUX1_AUX_GTC_SYNC_DATA 0x18a6
+#define mmDP_AUX2_AUX_GTC_SYNC_DATA 0x18ba
+#define mmDP_AUX3_AUX_GTC_SYNC_DATA 0x18d2
+#define mmDP_AUX4_AUX_GTC_SYNC_DATA 0x18e6
+#define mmDP_AUX5_AUX_GTC_SYNC_DATA 0x18fa
+#define mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x1893
+#define mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x1893
+#define mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18a7
+#define mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18bb
+#define mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18d3
+#define mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18e7
+#define mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x18fb
+#define mmDVO_ENABLE 0x1858
+#define mmDVO_SOURCE_SELECT 0x1859
+#define mmDVO_OUTPUT 0x185a
+#define mmDVO_CONTROL 0x185b
+#define mmDVO_CRC_EN 0x185c
+#define mmDVO_CRC2_SIG_MASK 0x185d
+#define mmDVO_CRC2_SIG_RESULT 0x185e
+#define mmDVO_FIFO_ERROR_STATUS 0x185f
+#define mmFBC_CNTL 0x16d0
+#define mmFBC_IDLE_MASK 0x16d1
+#define mmFBC_IDLE_FORCE_CLEAR_MASK 0x16d2
+#define mmFBC_START_STOP_DELAY 0x16d3
+#define mmFBC_COMP_CNTL 0x16d4
+#define mmFBC_COMP_MODE 0x16d5
+#define mmFBC_DEBUG0 0x16d6
+#define mmFBC_DEBUG1 0x16d7
+#define mmFBC_DEBUG2 0x16d8
+#define mmFBC_IND_LUT0 0x16d9
+#define mmFBC_IND_LUT1 0x16da
+#define mmFBC_IND_LUT2 0x16db
+#define mmFBC_IND_LUT3 0x16dc
+#define mmFBC_IND_LUT4 0x16dd
+#define mmFBC_IND_LUT5 0x16de
+#define mmFBC_IND_LUT6 0x16df
+#define mmFBC_IND_LUT7 0x16e0
+#define mmFBC_IND_LUT8 0x16e1
+#define mmFBC_IND_LUT9 0x16e2
+#define mmFBC_IND_LUT10 0x16e3
+#define mmFBC_IND_LUT11 0x16e4
+#define mmFBC_IND_LUT12 0x16e5
+#define mmFBC_IND_LUT13 0x16e6
+#define mmFBC_IND_LUT14 0x16e7
+#define mmFBC_IND_LUT15 0x16e8
+#define mmFBC_CSM_REGION_OFFSET_01 0x16e9
+#define mmFBC_CSM_REGION_OFFSET_23 0x16ea
+#define mmFBC_CLIENT_REGION_MASK 0x16eb
+#define mmFBC_DEBUG_COMP 0x16ec
+#define mmFBC_DEBUG_CSR 0x16ed
+#define mmFBC_DEBUG_CSR_RDATA 0x16ee
+#define mmFBC_DEBUG_CSR_WDATA 0x16ef
+#define mmFBC_DEBUG_CSR_RDATA_HI 0x16f6
+#define mmFBC_DEBUG_CSR_WDATA_HI 0x16f7
+#define mmFBC_MISC 0x16f0
+#define mmFBC_STATUS 0x16f1
+#define mmFBC_TEST_DEBUG_INDEX 0x16f4
+#define mmFBC_TEST_DEBUG_DATA 0x16f5
+#define mmFMT_CLAMP_COMPONENT_R 0x1be8
+#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x1be8
+#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1ee8
+#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x41e8
+#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x44e8
+#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x47e8
+#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x4ae8
+#define mmFMT_CLAMP_COMPONENT_G 0x1be9
+#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x1be9
+#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1ee9
+#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x41e9
+#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x44e9
+#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x47e9
+#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x4ae9
+#define mmFMT_CLAMP_COMPONENT_B 0x1bea
+#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x1bea
+#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1eea
+#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x41ea
+#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x44ea
+#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x47ea
+#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x4aea
+#define mmFMT_DYNAMIC_EXP_CNTL 0x1bed
+#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1bed
+#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1eed
+#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x41ed
+#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x44ed
+#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x47ed
+#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x4aed
+#define mmFMT_CONTROL 0x1bee
+#define mmFMT0_FMT_CONTROL 0x1bee
+#define mmFMT1_FMT_CONTROL 0x1eee
+#define mmFMT2_FMT_CONTROL 0x41ee
+#define mmFMT3_FMT_CONTROL 0x44ee
+#define mmFMT4_FMT_CONTROL 0x47ee
+#define mmFMT5_FMT_CONTROL 0x4aee
+#define mmFMT_FORCE_OUTPUT_CNTL 0x1bef
+#define mmFMT0_FMT_FORCE_OUTPUT_CNTL 0x1bef
+#define mmFMT1_FMT_FORCE_OUTPUT_CNTL 0x1eef
+#define mmFMT2_FMT_FORCE_OUTPUT_CNTL 0x41ef
+#define mmFMT3_FMT_FORCE_OUTPUT_CNTL 0x44ef
+#define mmFMT4_FMT_FORCE_OUTPUT_CNTL 0x47ef
+#define mmFMT5_FMT_FORCE_OUTPUT_CNTL 0x4aef
+#define mmFMT_FORCE_DATA_0_1 0x1bf0
+#define mmFMT0_FMT_FORCE_DATA_0_1 0x1bf0
+#define mmFMT1_FMT_FORCE_DATA_0_1 0x1ef0
+#define mmFMT2_FMT_FORCE_DATA_0_1 0x41f0
+#define mmFMT3_FMT_FORCE_DATA_0_1 0x44f0
+#define mmFMT4_FMT_FORCE_DATA_0_1 0x47f0
+#define mmFMT5_FMT_FORCE_DATA_0_1 0x4af0
+#define mmFMT_FORCE_DATA_2_3 0x1bf1
+#define mmFMT0_FMT_FORCE_DATA_2_3 0x1bf1
+#define mmFMT1_FMT_FORCE_DATA_2_3 0x1ef1
+#define mmFMT2_FMT_FORCE_DATA_2_3 0x41f1
+#define mmFMT3_FMT_FORCE_DATA_2_3 0x44f1
+#define mmFMT4_FMT_FORCE_DATA_2_3 0x47f1
+#define mmFMT5_FMT_FORCE_DATA_2_3 0x4af1
+#define mmFMT_BIT_DEPTH_CONTROL 0x1bf2
+#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1bf2
+#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1ef2
+#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x41f2
+#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x44f2
+#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x47f2
+#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x4af2
+#define mmFMT_DITHER_RAND_R_SEED 0x1bf3
+#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1bf3
+#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x1ef3
+#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x41f3
+#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x44f3
+#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x47f3
+#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x4af3
+#define mmFMT_DITHER_RAND_G_SEED 0x1bf4
+#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1bf4
+#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x1ef4
+#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x41f4
+#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x44f4
+#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x47f4
+#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x4af4
+#define mmFMT_DITHER_RAND_B_SEED 0x1bf5
+#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1bf5
+#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x1ef5
+#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x41f5
+#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x44f5
+#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x47f5
+#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x4af5
+#define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6
+#define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6
+#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1ef6
+#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41f6
+#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x44f6
+#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x47f6
+#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x4af6
+#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7
+#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7
+#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1ef7
+#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41f7
+#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x44f7
+#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x47f7
+#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x4af7
+#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8
+#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8
+#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1ef8
+#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41f8
+#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x44f8
+#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x47f8
+#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x4af8
+#define mmFMT_CLAMP_CNTL 0x1bf9
+#define mmFMT0_FMT_CLAMP_CNTL 0x1bf9
+#define mmFMT1_FMT_CLAMP_CNTL 0x1ef9
+#define mmFMT2_FMT_CLAMP_CNTL 0x41f9
+#define mmFMT3_FMT_CLAMP_CNTL 0x44f9
+#define mmFMT4_FMT_CLAMP_CNTL 0x47f9
+#define mmFMT5_FMT_CLAMP_CNTL 0x4af9
+#define mmFMT_CRC_CNTL 0x1bfa
+#define mmFMT0_FMT_CRC_CNTL 0x1bfa
+#define mmFMT1_FMT_CRC_CNTL 0x1efa
+#define mmFMT2_FMT_CRC_CNTL 0x41fa
+#define mmFMT3_FMT_CRC_CNTL 0x44fa
+#define mmFMT4_FMT_CRC_CNTL 0x47fa
+#define mmFMT5_FMT_CRC_CNTL 0x4afa
+#define mmFMT_CRC_SIG_RED_GREEN_MASK 0x1bfb
+#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1bfb
+#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1efb
+#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x41fb
+#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x44fb
+#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x47fb
+#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x4afb
+#define mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc
+#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc
+#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1efc
+#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41fc
+#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x44fc
+#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x47fc
+#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x4afc
+#define mmFMT_CRC_SIG_RED_GREEN 0x1bfd
+#define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1bfd
+#define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1efd
+#define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x41fd
+#define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x44fd
+#define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x47fd
+#define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x4afd
+#define mmFMT_CRC_SIG_BLUE_CONTROL 0x1bfe
+#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1bfe
+#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1efe
+#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x41fe
+#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x44fe
+#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x47fe
+#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x4afe
+#define mmFMT_DEBUG_CNTL 0x1bff
+#define mmFMT0_FMT_DEBUG_CNTL 0x1bff
+#define mmFMT1_FMT_DEBUG_CNTL 0x1eff
+#define mmFMT2_FMT_DEBUG_CNTL 0x41ff
+#define mmFMT3_FMT_DEBUG_CNTL 0x44ff
+#define mmFMT4_FMT_DEBUG_CNTL 0x47ff
+#define mmFMT5_FMT_DEBUG_CNTL 0x4aff
+#define mmFMT_TEST_DEBUG_INDEX 0x1beb
+#define mmFMT0_FMT_TEST_DEBUG_INDEX 0x1beb
+#define mmFMT1_FMT_TEST_DEBUG_INDEX 0x1eeb
+#define mmFMT2_FMT_TEST_DEBUG_INDEX 0x41eb
+#define mmFMT3_FMT_TEST_DEBUG_INDEX 0x44eb
+#define mmFMT4_FMT_TEST_DEBUG_INDEX 0x47eb
+#define mmFMT5_FMT_TEST_DEBUG_INDEX 0x4aeb
+#define mmFMT_TEST_DEBUG_DATA 0x1bec
+#define mmFMT0_FMT_TEST_DEBUG_DATA 0x1bec
+#define mmFMT1_FMT_TEST_DEBUG_DATA 0x1eec
+#define mmFMT2_FMT_TEST_DEBUG_DATA 0x41ec
+#define mmFMT3_FMT_TEST_DEBUG_DATA 0x44ec
+#define mmFMT4_FMT_TEST_DEBUG_DATA 0x47ec
+#define mmFMT5_FMT_TEST_DEBUG_DATA 0x4aec
+#define ixFMT_DEBUG0 0x1
+#define ixFMT_DEBUG1 0x2
+#define ixFMT_DEBUG2 0x3
+#define ixFMT_DEBUG_ID 0x0
+#define mmLB_DATA_FORMAT 0x1ac0
+#define mmLB0_LB_DATA_FORMAT 0x1ac0
+#define mmLB1_LB_DATA_FORMAT 0x1dc0
+#define mmLB2_LB_DATA_FORMAT 0x40c0
+#define mmLB3_LB_DATA_FORMAT 0x43c0
+#define mmLB4_LB_DATA_FORMAT 0x46c0
+#define mmLB5_LB_DATA_FORMAT 0x49c0
+#define mmLB_MEMORY_CTRL 0x1ac1
+#define mmLB0_LB_MEMORY_CTRL 0x1ac1
+#define mmLB1_LB_MEMORY_CTRL 0x1dc1
+#define mmLB2_LB_MEMORY_CTRL 0x40c1
+#define mmLB3_LB_MEMORY_CTRL 0x43c1
+#define mmLB4_LB_MEMORY_CTRL 0x46c1
+#define mmLB5_LB_MEMORY_CTRL 0x49c1
+#define mmLB_MEMORY_SIZE_STATUS 0x1ac2
+#define mmLB0_LB_MEMORY_SIZE_STATUS 0x1ac2
+#define mmLB1_LB_MEMORY_SIZE_STATUS 0x1dc2
+#define mmLB2_LB_MEMORY_SIZE_STATUS 0x40c2
+#define mmLB3_LB_MEMORY_SIZE_STATUS 0x43c2
+#define mmLB4_LB_MEMORY_SIZE_STATUS 0x46c2
+#define mmLB5_LB_MEMORY_SIZE_STATUS 0x49c2
+#define mmLB_DESKTOP_HEIGHT 0x1ac3
+#define mmLB0_LB_DESKTOP_HEIGHT 0x1ac3
+#define mmLB1_LB_DESKTOP_HEIGHT 0x1dc3
+#define mmLB2_LB_DESKTOP_HEIGHT 0x40c3
+#define mmLB3_LB_DESKTOP_HEIGHT 0x43c3
+#define mmLB4_LB_DESKTOP_HEIGHT 0x46c3
+#define mmLB5_LB_DESKTOP_HEIGHT 0x49c3
+#define mmLB_VLINE_START_END 0x1ac4
+#define mmLB0_LB_VLINE_START_END 0x1ac4
+#define mmLB1_LB_VLINE_START_END 0x1dc4
+#define mmLB2_LB_VLINE_START_END 0x40c4
+#define mmLB3_LB_VLINE_START_END 0x43c4
+#define mmLB4_LB_VLINE_START_END 0x46c4
+#define mmLB5_LB_VLINE_START_END 0x49c4
+#define mmLB_VLINE2_START_END 0x1ac5
+#define mmLB0_LB_VLINE2_START_END 0x1ac5
+#define mmLB1_LB_VLINE2_START_END 0x1dc5
+#define mmLB2_LB_VLINE2_START_END 0x40c5
+#define mmLB3_LB_VLINE2_START_END 0x43c5
+#define mmLB4_LB_VLINE2_START_END 0x46c5
+#define mmLB5_LB_VLINE2_START_END 0x49c5
+#define mmLB_V_COUNTER 0x1ac6
+#define mmLB0_LB_V_COUNTER 0x1ac6
+#define mmLB1_LB_V_COUNTER 0x1dc6
+#define mmLB2_LB_V_COUNTER 0x40c6
+#define mmLB3_LB_V_COUNTER 0x43c6
+#define mmLB4_LB_V_COUNTER 0x46c6
+#define mmLB5_LB_V_COUNTER 0x49c6
+#define mmLB_SNAPSHOT_V_COUNTER 0x1ac7
+#define mmLB0_LB_SNAPSHOT_V_COUNTER 0x1ac7
+#define mmLB1_LB_SNAPSHOT_V_COUNTER 0x1dc7
+#define mmLB2_LB_SNAPSHOT_V_COUNTER 0x40c7
+#define mmLB3_LB_SNAPSHOT_V_COUNTER 0x43c7
+#define mmLB4_LB_SNAPSHOT_V_COUNTER 0x46c7
+#define mmLB5_LB_SNAPSHOT_V_COUNTER 0x49c7
+#define mmLB_INTERRUPT_MASK 0x1ac8
+#define mmLB0_LB_INTERRUPT_MASK 0x1ac8
+#define mmLB1_LB_INTERRUPT_MASK 0x1dc8
+#define mmLB2_LB_INTERRUPT_MASK 0x40c8
+#define mmLB3_LB_INTERRUPT_MASK 0x43c8
+#define mmLB4_LB_INTERRUPT_MASK 0x46c8
+#define mmLB5_LB_INTERRUPT_MASK 0x49c8
+#define mmLB_VLINE_STATUS 0x1ac9
+#define mmLB0_LB_VLINE_STATUS 0x1ac9
+#define mmLB1_LB_VLINE_STATUS 0x1dc9
+#define mmLB2_LB_VLINE_STATUS 0x40c9
+#define mmLB3_LB_VLINE_STATUS 0x43c9
+#define mmLB4_LB_VLINE_STATUS 0x46c9
+#define mmLB5_LB_VLINE_STATUS 0x49c9
+#define mmLB_VLINE2_STATUS 0x1aca
+#define mmLB0_LB_VLINE2_STATUS 0x1aca
+#define mmLB1_LB_VLINE2_STATUS 0x1dca
+#define mmLB2_LB_VLINE2_STATUS 0x40ca
+#define mmLB3_LB_VLINE2_STATUS 0x43ca
+#define mmLB4_LB_VLINE2_STATUS 0x46ca
+#define mmLB5_LB_VLINE2_STATUS 0x49ca
+#define mmLB_VBLANK_STATUS 0x1acb
+#define mmLB0_LB_VBLANK_STATUS 0x1acb
+#define mmLB1_LB_VBLANK_STATUS 0x1dcb
+#define mmLB2_LB_VBLANK_STATUS 0x40cb
+#define mmLB3_LB_VBLANK_STATUS 0x43cb
+#define mmLB4_LB_VBLANK_STATUS 0x46cb
+#define mmLB5_LB_VBLANK_STATUS 0x49cb
+#define mmLB_SYNC_RESET_SEL 0x1acc
+#define mmLB0_LB_SYNC_RESET_SEL 0x1acc
+#define mmLB1_LB_SYNC_RESET_SEL 0x1dcc
+#define mmLB2_LB_SYNC_RESET_SEL 0x40cc
+#define mmLB3_LB_SYNC_RESET_SEL 0x43cc
+#define mmLB4_LB_SYNC_RESET_SEL 0x46cc
+#define mmLB5_LB_SYNC_RESET_SEL 0x49cc
+#define mmLB_BLACK_KEYER_R_CR 0x1acd
+#define mmLB0_LB_BLACK_KEYER_R_CR 0x1acd
+#define mmLB1_LB_BLACK_KEYER_R_CR 0x1dcd
+#define mmLB2_LB_BLACK_KEYER_R_CR 0x40cd
+#define mmLB3_LB_BLACK_KEYER_R_CR 0x43cd
+#define mmLB4_LB_BLACK_KEYER_R_CR 0x46cd
+#define mmLB5_LB_BLACK_KEYER_R_CR 0x49cd
+#define mmLB_BLACK_KEYER_G_Y 0x1ace
+#define mmLB0_LB_BLACK_KEYER_G_Y 0x1ace
+#define mmLB1_LB_BLACK_KEYER_G_Y 0x1dce
+#define mmLB2_LB_BLACK_KEYER_G_Y 0x40ce
+#define mmLB3_LB_BLACK_KEYER_G_Y 0x43ce
+#define mmLB4_LB_BLACK_KEYER_G_Y 0x46ce
+#define mmLB5_LB_BLACK_KEYER_G_Y 0x49ce
+#define mmLB_BLACK_KEYER_B_CB 0x1acf
+#define mmLB0_LB_BLACK_KEYER_B_CB 0x1acf
+#define mmLB1_LB_BLACK_KEYER_B_CB 0x1dcf
+#define mmLB2_LB_BLACK_KEYER_B_CB 0x40cf
+#define mmLB3_LB_BLACK_KEYER_B_CB 0x43cf
+#define mmLB4_LB_BLACK_KEYER_B_CB 0x46cf
+#define mmLB5_LB_BLACK_KEYER_B_CB 0x49cf
+#define mmLB_KEYER_COLOR_CTRL 0x1ad0
+#define mmLB0_LB_KEYER_COLOR_CTRL 0x1ad0
+#define mmLB1_LB_KEYER_COLOR_CTRL 0x1dd0
+#define mmLB2_LB_KEYER_COLOR_CTRL 0x40d0
+#define mmLB3_LB_KEYER_COLOR_CTRL 0x43d0
+#define mmLB4_LB_KEYER_COLOR_CTRL 0x46d0
+#define mmLB5_LB_KEYER_COLOR_CTRL 0x49d0
+#define mmLB_KEYER_COLOR_R_CR 0x1ad1
+#define mmLB0_LB_KEYER_COLOR_R_CR 0x1ad1
+#define mmLB1_LB_KEYER_COLOR_R_CR 0x1dd1
+#define mmLB2_LB_KEYER_COLOR_R_CR 0x40d1
+#define mmLB3_LB_KEYER_COLOR_R_CR 0x43d1
+#define mmLB4_LB_KEYER_COLOR_R_CR 0x46d1
+#define mmLB5_LB_KEYER_COLOR_R_CR 0x49d1
+#define mmLB_KEYER_COLOR_G_Y 0x1ad2
+#define mmLB0_LB_KEYER_COLOR_G_Y 0x1ad2
+#define mmLB1_LB_KEYER_COLOR_G_Y 0x1dd2
+#define mmLB2_LB_KEYER_COLOR_G_Y 0x40d2
+#define mmLB3_LB_KEYER_COLOR_G_Y 0x43d2
+#define mmLB4_LB_KEYER_COLOR_G_Y 0x46d2
+#define mmLB5_LB_KEYER_COLOR_G_Y 0x49d2
+#define mmLB_KEYER_COLOR_B_CB 0x1ad3
+#define mmLB0_LB_KEYER_COLOR_B_CB 0x1ad3
+#define mmLB1_LB_KEYER_COLOR_B_CB 0x1dd3
+#define mmLB2_LB_KEYER_COLOR_B_CB 0x40d3
+#define mmLB3_LB_KEYER_COLOR_B_CB 0x43d3
+#define mmLB4_LB_KEYER_COLOR_B_CB 0x46d3
+#define mmLB5_LB_KEYER_COLOR_B_CB 0x49d3
+#define mmLB_KEYER_COLOR_REP_R_CR 0x1ad4
+#define mmLB0_LB_KEYER_COLOR_REP_R_CR 0x1ad4
+#define mmLB1_LB_KEYER_COLOR_REP_R_CR 0x1dd4
+#define mmLB2_LB_KEYER_COLOR_REP_R_CR 0x40d4
+#define mmLB3_LB_KEYER_COLOR_REP_R_CR 0x43d4
+#define mmLB4_LB_KEYER_COLOR_REP_R_CR 0x46d4
+#define mmLB5_LB_KEYER_COLOR_REP_R_CR 0x49d4
+#define mmLB_KEYER_COLOR_REP_G_Y 0x1ad5
+#define mmLB0_LB_KEYER_COLOR_REP_G_Y 0x1ad5
+#define mmLB1_LB_KEYER_COLOR_REP_G_Y 0x1dd5
+#define mmLB2_LB_KEYER_COLOR_REP_G_Y 0x40d5
+#define mmLB3_LB_KEYER_COLOR_REP_G_Y 0x43d5
+#define mmLB4_LB_KEYER_COLOR_REP_G_Y 0x46d5
+#define mmLB5_LB_KEYER_COLOR_REP_G_Y 0x49d5
+#define mmLB_KEYER_COLOR_REP_B_CB 0x1ad6
+#define mmLB0_LB_KEYER_COLOR_REP_B_CB 0x1ad6
+#define mmLB1_LB_KEYER_COLOR_REP_B_CB 0x1dd6
+#define mmLB2_LB_KEYER_COLOR_REP_B_CB 0x40d6
+#define mmLB3_LB_KEYER_COLOR_REP_B_CB 0x43d6
+#define mmLB4_LB_KEYER_COLOR_REP_B_CB 0x46d6
+#define mmLB5_LB_KEYER_COLOR_REP_B_CB 0x49d6
+#define mmLB_BUFFER_LEVEL_STATUS 0x1ad7
+#define mmLB0_LB_BUFFER_LEVEL_STATUS 0x1ad7
+#define mmLB1_LB_BUFFER_LEVEL_STATUS 0x1dd7
+#define mmLB2_LB_BUFFER_LEVEL_STATUS 0x40d7
+#define mmLB3_LB_BUFFER_LEVEL_STATUS 0x43d7
+#define mmLB4_LB_BUFFER_LEVEL_STATUS 0x46d7
+#define mmLB5_LB_BUFFER_LEVEL_STATUS 0x49d7
+#define mmLB_BUFFER_URGENCY_CTRL 0x1ad8
+#define mmLB0_LB_BUFFER_URGENCY_CTRL 0x1ad8
+#define mmLB1_LB_BUFFER_URGENCY_CTRL 0x1dd8
+#define mmLB2_LB_BUFFER_URGENCY_CTRL 0x40d8
+#define mmLB3_LB_BUFFER_URGENCY_CTRL 0x43d8
+#define mmLB4_LB_BUFFER_URGENCY_CTRL 0x46d8
+#define mmLB5_LB_BUFFER_URGENCY_CTRL 0x49d8
+#define mmLB_BUFFER_URGENCY_STATUS 0x1ad9
+#define mmLB0_LB_BUFFER_URGENCY_STATUS 0x1ad9
+#define mmLB1_LB_BUFFER_URGENCY_STATUS 0x1dd9
+#define mmLB2_LB_BUFFER_URGENCY_STATUS 0x40d9
+#define mmLB3_LB_BUFFER_URGENCY_STATUS 0x43d9
+#define mmLB4_LB_BUFFER_URGENCY_STATUS 0x46d9
+#define mmLB5_LB_BUFFER_URGENCY_STATUS 0x49d9
+#define mmLB_BUFFER_STATUS 0x1ada
+#define mmLB0_LB_BUFFER_STATUS 0x1ada
+#define mmLB1_LB_BUFFER_STATUS 0x1dda
+#define mmLB2_LB_BUFFER_STATUS 0x40da
+#define mmLB3_LB_BUFFER_STATUS 0x43da
+#define mmLB4_LB_BUFFER_STATUS 0x46da
+#define mmLB5_LB_BUFFER_STATUS 0x49da
+#define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1adc
+#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1adc
+#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1ddc
+#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x40dc
+#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x43dc
+#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x46dc
+#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x49dc
+#define mmMVP_AFR_FLIP_MODE 0x1ae0
+#define mmLB0_MVP_AFR_FLIP_MODE 0x1ae0
+#define mmLB1_MVP_AFR_FLIP_MODE 0x1de0
+#define mmLB2_MVP_AFR_FLIP_MODE 0x40e0
+#define mmLB3_MVP_AFR_FLIP_MODE 0x43e0
+#define mmLB4_MVP_AFR_FLIP_MODE 0x46e0
+#define mmLB5_MVP_AFR_FLIP_MODE 0x49e0
+#define mmMVP_AFR_FLIP_FIFO_CNTL 0x1ae1
+#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1ae1
+#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1de1
+#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x40e1
+#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x43e1
+#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x46e1
+#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x49e1
+#define mmMVP_FLIP_LINE_NUM_INSERT 0x1ae2
+#define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ae2
+#define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1de2
+#define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x40e2
+#define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x43e2
+#define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x46e2
+#define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x49e2
+#define mmDC_MVP_LB_CONTROL 0x1ae3
+#define mmLB0_DC_MVP_LB_CONTROL 0x1ae3
+#define mmLB1_DC_MVP_LB_CONTROL 0x1de3
+#define mmLB2_DC_MVP_LB_CONTROL 0x40e3
+#define mmLB3_DC_MVP_LB_CONTROL 0x43e3
+#define mmLB4_DC_MVP_LB_CONTROL 0x46e3
+#define mmLB5_DC_MVP_LB_CONTROL 0x49e3
+#define mmLB_DEBUG 0x1ae4
+#define mmLB0_LB_DEBUG 0x1ae4
+#define mmLB1_LB_DEBUG 0x1de4
+#define mmLB2_LB_DEBUG 0x40e4
+#define mmLB3_LB_DEBUG 0x43e4
+#define mmLB4_LB_DEBUG 0x46e4
+#define mmLB5_LB_DEBUG 0x49e4
+#define mmLB_DEBUG2 0x1ae5
+#define mmLB0_LB_DEBUG2 0x1ae5
+#define mmLB1_LB_DEBUG2 0x1de5
+#define mmLB2_LB_DEBUG2 0x40e5
+#define mmLB3_LB_DEBUG2 0x43e5
+#define mmLB4_LB_DEBUG2 0x46e5
+#define mmLB5_LB_DEBUG2 0x49e5
+#define mmLB_DEBUG3 0x1ae6
+#define mmLB0_LB_DEBUG3 0x1ae6
+#define mmLB1_LB_DEBUG3 0x1de6
+#define mmLB2_LB_DEBUG3 0x40e6
+#define mmLB3_LB_DEBUG3 0x43e6
+#define mmLB4_LB_DEBUG3 0x46e6
+#define mmLB5_LB_DEBUG3 0x49e6
+#define mmLB_TEST_DEBUG_INDEX 0x1afe
+#define mmLB0_LB_TEST_DEBUG_INDEX 0x1afe
+#define mmLB1_LB_TEST_DEBUG_INDEX 0x1dfe
+#define mmLB2_LB_TEST_DEBUG_INDEX 0x40fe
+#define mmLB3_LB_TEST_DEBUG_INDEX 0x43fe
+#define mmLB4_LB_TEST_DEBUG_INDEX 0x46fe
+#define mmLB5_LB_TEST_DEBUG_INDEX 0x49fe
+#define mmLB_TEST_DEBUG_DATA 0x1aff
+#define mmLB0_LB_TEST_DEBUG_DATA 0x1aff
+#define mmLB1_LB_TEST_DEBUG_DATA 0x1dff
+#define mmLB2_LB_TEST_DEBUG_DATA 0x40ff
+#define mmLB3_LB_TEST_DEBUG_DATA 0x43ff
+#define mmLB4_LB_TEST_DEBUG_DATA 0x46ff
+#define mmLB5_LB_TEST_DEBUG_DATA 0x49ff
+#define mmMVP_CONTROL1 0x1680
+#define mmMVP_CONTROL2 0x1681
+#define mmMVP_FIFO_CONTROL 0x1682
+#define mmMVP_FIFO_STATUS 0x1683
+#define mmMVP_SLAVE_STATUS 0x1684
+#define mmMVP_INBAND_CNTL_CAP 0x1685
+#define mmMVP_BLACK_KEYER 0x1686
+#define mmMVP_CRC_CNTL 0x1687
+#define mmMVP_CRC_RESULT_BLUE_GREEN 0x1688
+#define mmMVP_CRC_RESULT_RED 0x1689
+#define mmMVP_CONTROL3 0x168a
+#define mmMVP_RECEIVE_CNT_CNTL1 0x168b
+#define mmMVP_RECEIVE_CNT_CNTL2 0x168c
+#define mmMVP_DEBUG 0x168f
+#define mmMVP_TEST_DEBUG_INDEX 0x168d
+#define mmMVP_TEST_DEBUG_DATA 0x168e
+#define ixMVP_DEBUG_12 0xc
+#define ixMVP_DEBUG_13 0xd
+#define ixMVP_DEBUG_14 0xe
+#define ixMVP_DEBUG_15 0xf
+#define ixMVP_DEBUG_16 0x10
+#define ixMVP_DEBUG_17 0x11
+#define mmSCL_COEF_RAM_SELECT 0x1b40
+#define mmSCL0_SCL_COEF_RAM_SELECT 0x1b40
+#define mmSCL1_SCL_COEF_RAM_SELECT 0x1e40
+#define mmSCL2_SCL_COEF_RAM_SELECT 0x4140
+#define mmSCL3_SCL_COEF_RAM_SELECT 0x4440
+#define mmSCL4_SCL_COEF_RAM_SELECT 0x4740
+#define mmSCL5_SCL_COEF_RAM_SELECT 0x4a40
+#define mmSCL_COEF_RAM_TAP_DATA 0x1b41
+#define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1b41
+#define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1e41
+#define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x4141
+#define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4441
+#define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4741
+#define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4a41
+#define mmSCL_MODE 0x1b42
+#define mmSCL0_SCL_MODE 0x1b42
+#define mmSCL1_SCL_MODE 0x1e42
+#define mmSCL2_SCL_MODE 0x4142
+#define mmSCL3_SCL_MODE 0x4442
+#define mmSCL4_SCL_MODE 0x4742
+#define mmSCL5_SCL_MODE 0x4a42
+#define mmSCL_TAP_CONTROL 0x1b43
+#define mmSCL0_SCL_TAP_CONTROL 0x1b43
+#define mmSCL1_SCL_TAP_CONTROL 0x1e43
+#define mmSCL2_SCL_TAP_CONTROL 0x4143
+#define mmSCL3_SCL_TAP_CONTROL 0x4443
+#define mmSCL4_SCL_TAP_CONTROL 0x4743
+#define mmSCL5_SCL_TAP_CONTROL 0x4a43
+#define mmSCL_CONTROL 0x1b44
+#define mmSCL0_SCL_CONTROL 0x1b44
+#define mmSCL1_SCL_CONTROL 0x1e44
+#define mmSCL2_SCL_CONTROL 0x4144
+#define mmSCL3_SCL_CONTROL 0x4444
+#define mmSCL4_SCL_CONTROL 0x4744
+#define mmSCL5_SCL_CONTROL 0x4a44
+#define mmSCL_BYPASS_CONTROL 0x1b45
+#define mmSCL0_SCL_BYPASS_CONTROL 0x1b45
+#define mmSCL1_SCL_BYPASS_CONTROL 0x1e45
+#define mmSCL2_SCL_BYPASS_CONTROL 0x4145
+#define mmSCL3_SCL_BYPASS_CONTROL 0x4445
+#define mmSCL4_SCL_BYPASS_CONTROL 0x4745
+#define mmSCL5_SCL_BYPASS_CONTROL 0x4a45
+#define mmSCL_MANUAL_REPLICATE_CONTROL 0x1b46
+#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1b46
+#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1e46
+#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x4146
+#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4446
+#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4746
+#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4a46
+#define mmSCL_AUTOMATIC_MODE_CONTROL 0x1b47
+#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1b47
+#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1e47
+#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x4147
+#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4447
+#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4747
+#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4a47
+#define mmSCL_HORZ_FILTER_CONTROL 0x1b48
+#define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1b48
+#define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1e48
+#define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x4148
+#define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x4448
+#define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x4748
+#define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4a48
+#define mmSCL_HORZ_FILTER_SCALE_RATIO 0x1b49
+#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1b49
+#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1e49
+#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x4149
+#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x4449
+#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x4749
+#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4a49
+#define mmSCL_HORZ_FILTER_INIT 0x1b4a
+#define mmSCL0_SCL_HORZ_FILTER_INIT 0x1b4a
+#define mmSCL1_SCL_HORZ_FILTER_INIT 0x1e4a
+#define mmSCL2_SCL_HORZ_FILTER_INIT 0x414a
+#define mmSCL3_SCL_HORZ_FILTER_INIT 0x444a
+#define mmSCL4_SCL_HORZ_FILTER_INIT 0x474a
+#define mmSCL5_SCL_HORZ_FILTER_INIT 0x4a4a
+#define mmSCL_VERT_FILTER_CONTROL 0x1b4b
+#define mmSCL0_SCL_VERT_FILTER_CONTROL 0x1b4b
+#define mmSCL1_SCL_VERT_FILTER_CONTROL 0x1e4b
+#define mmSCL2_SCL_VERT_FILTER_CONTROL 0x414b
+#define mmSCL3_SCL_VERT_FILTER_CONTROL 0x444b
+#define mmSCL4_SCL_VERT_FILTER_CONTROL 0x474b
+#define mmSCL5_SCL_VERT_FILTER_CONTROL 0x4a4b
+#define mmSCL_VERT_FILTER_SCALE_RATIO 0x1b4c
+#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1b4c
+#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1e4c
+#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x414c
+#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x444c
+#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x474c
+#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x4a4c
+#define mmSCL_VERT_FILTER_INIT 0x1b4d
+#define mmSCL0_SCL_VERT_FILTER_INIT 0x1b4d
+#define mmSCL1_SCL_VERT_FILTER_INIT 0x1e4d
+#define mmSCL2_SCL_VERT_FILTER_INIT 0x414d
+#define mmSCL3_SCL_VERT_FILTER_INIT 0x444d
+#define mmSCL4_SCL_VERT_FILTER_INIT 0x474d
+#define mmSCL5_SCL_VERT_FILTER_INIT 0x4a4d
+#define mmSCL_VERT_FILTER_INIT_BOT 0x1b4e
+#define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1b4e
+#define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1e4e
+#define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x414e
+#define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x444e
+#define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x474e
+#define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x4a4e
+#define mmSCL_ROUND_OFFSET 0x1b4f
+#define mmSCL0_SCL_ROUND_OFFSET 0x1b4f
+#define mmSCL1_SCL_ROUND_OFFSET 0x1e4f
+#define mmSCL2_SCL_ROUND_OFFSET 0x414f
+#define mmSCL3_SCL_ROUND_OFFSET 0x444f
+#define mmSCL4_SCL_ROUND_OFFSET 0x474f
+#define mmSCL5_SCL_ROUND_OFFSET 0x4a4f
+#define mmSCL_UPDATE 0x1b51
+#define mmSCL0_SCL_UPDATE 0x1b51
+#define mmSCL1_SCL_UPDATE 0x1e51
+#define mmSCL2_SCL_UPDATE 0x4151
+#define mmSCL3_SCL_UPDATE 0x4451
+#define mmSCL4_SCL_UPDATE 0x4751
+#define mmSCL5_SCL_UPDATE 0x4a51
+#define mmSCL_F_SHARP_CONTROL 0x1b53
+#define mmSCL0_SCL_F_SHARP_CONTROL 0x1b53
+#define mmSCL1_SCL_F_SHARP_CONTROL 0x1e53
+#define mmSCL2_SCL_F_SHARP_CONTROL 0x4153
+#define mmSCL3_SCL_F_SHARP_CONTROL 0x4453
+#define mmSCL4_SCL_F_SHARP_CONTROL 0x4753
+#define mmSCL5_SCL_F_SHARP_CONTROL 0x4a53
+#define mmSCL_ALU_CONTROL 0x1b54
+#define mmSCL0_SCL_ALU_CONTROL 0x1b54
+#define mmSCL1_SCL_ALU_CONTROL 0x1e54
+#define mmSCL2_SCL_ALU_CONTROL 0x4154
+#define mmSCL3_SCL_ALU_CONTROL 0x4454
+#define mmSCL4_SCL_ALU_CONTROL 0x4754
+#define mmSCL5_SCL_ALU_CONTROL 0x4a54
+#define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1b55
+#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1b55
+#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1e55
+#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x4155
+#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4455
+#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4755
+#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4a55
+#define mmVIEWPORT_START 0x1b5c
+#define mmSCL0_VIEWPORT_START 0x1b5c
+#define mmSCL1_VIEWPORT_START 0x1e5c
+#define mmSCL2_VIEWPORT_START 0x415c
+#define mmSCL3_VIEWPORT_START 0x445c
+#define mmSCL4_VIEWPORT_START 0x475c
+#define mmSCL5_VIEWPORT_START 0x4a5c
+#define mmVIEWPORT_SIZE 0x1b5d
+#define mmSCL0_VIEWPORT_SIZE 0x1b5d
+#define mmSCL1_VIEWPORT_SIZE 0x1e5d
+#define mmSCL2_VIEWPORT_SIZE 0x415d
+#define mmSCL3_VIEWPORT_SIZE 0x445d
+#define mmSCL4_VIEWPORT_SIZE 0x475d
+#define mmSCL5_VIEWPORT_SIZE 0x4a5d
+#define mmEXT_OVERSCAN_LEFT_RIGHT 0x1b5e
+#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1b5e
+#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1e5e
+#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x415e
+#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x445e
+#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x475e
+#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x4a5e
+#define mmEXT_OVERSCAN_TOP_BOTTOM 0x1b5f
+#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1b5f
+#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1e5f
+#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x415f
+#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x445f
+#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x475f
+#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x4a5f
+#define mmSCL_MODE_CHANGE_DET1 0x1b60
+#define mmSCL0_SCL_MODE_CHANGE_DET1 0x1b60
+#define mmSCL1_SCL_MODE_CHANGE_DET1 0x1e60
+#define mmSCL2_SCL_MODE_CHANGE_DET1 0x4160
+#define mmSCL3_SCL_MODE_CHANGE_DET1 0x4460
+#define mmSCL4_SCL_MODE_CHANGE_DET1 0x4760
+#define mmSCL5_SCL_MODE_CHANGE_DET1 0x4a60
+#define mmSCL_MODE_CHANGE_DET2 0x1b61
+#define mmSCL0_SCL_MODE_CHANGE_DET2 0x1b61
+#define mmSCL1_SCL_MODE_CHANGE_DET2 0x1e61
+#define mmSCL2_SCL_MODE_CHANGE_DET2 0x4161
+#define mmSCL3_SCL_MODE_CHANGE_DET2 0x4461
+#define mmSCL4_SCL_MODE_CHANGE_DET2 0x4761
+#define mmSCL5_SCL_MODE_CHANGE_DET2 0x4a61
+#define mmSCL_MODE_CHANGE_DET3 0x1b62
+#define mmSCL0_SCL_MODE_CHANGE_DET3 0x1b62
+#define mmSCL1_SCL_MODE_CHANGE_DET3 0x1e62
+#define mmSCL2_SCL_MODE_CHANGE_DET3 0x4162
+#define mmSCL3_SCL_MODE_CHANGE_DET3 0x4462
+#define mmSCL4_SCL_MODE_CHANGE_DET3 0x4762
+#define mmSCL5_SCL_MODE_CHANGE_DET3 0x4a62
+#define mmSCL_MODE_CHANGE_MASK 0x1b63
+#define mmSCL0_SCL_MODE_CHANGE_MASK 0x1b63
+#define mmSCL1_SCL_MODE_CHANGE_MASK 0x1e63
+#define mmSCL2_SCL_MODE_CHANGE_MASK 0x4163
+#define mmSCL3_SCL_MODE_CHANGE_MASK 0x4463
+#define mmSCL4_SCL_MODE_CHANGE_MASK 0x4763
+#define mmSCL5_SCL_MODE_CHANGE_MASK 0x4a63
+#define mmSCL_DEBUG2 0x1b69
+#define mmSCL0_SCL_DEBUG2 0x1b69
+#define mmSCL1_SCL_DEBUG2 0x1e69
+#define mmSCL2_SCL_DEBUG2 0x4169
+#define mmSCL3_SCL_DEBUG2 0x4469
+#define mmSCL4_SCL_DEBUG2 0x4769
+#define mmSCL5_SCL_DEBUG2 0x4a69
+#define mmSCL_DEBUG 0x1b6a
+#define mmSCL0_SCL_DEBUG 0x1b6a
+#define mmSCL1_SCL_DEBUG 0x1e6a
+#define mmSCL2_SCL_DEBUG 0x416a
+#define mmSCL3_SCL_DEBUG 0x446a
+#define mmSCL4_SCL_DEBUG 0x476a
+#define mmSCL5_SCL_DEBUG 0x4a6a
+#define mmSCL_TEST_DEBUG_INDEX 0x1b6b
+#define mmSCL0_SCL_TEST_DEBUG_INDEX 0x1b6b
+#define mmSCL1_SCL_TEST_DEBUG_INDEX 0x1e6b
+#define mmSCL2_SCL_TEST_DEBUG_INDEX 0x416b
+#define mmSCL3_SCL_TEST_DEBUG_INDEX 0x446b
+#define mmSCL4_SCL_TEST_DEBUG_INDEX 0x476b
+#define mmSCL5_SCL_TEST_DEBUG_INDEX 0x4a6b
+#define mmSCL_TEST_DEBUG_DATA 0x1b6c
+#define mmSCL0_SCL_TEST_DEBUG_DATA 0x1b6c
+#define mmSCL1_SCL_TEST_DEBUG_DATA 0x1e6c
+#define mmSCL2_SCL_TEST_DEBUG_DATA 0x416c
+#define mmSCL3_SCL_TEST_DEBUG_DATA 0x446c
+#define mmSCL4_SCL_TEST_DEBUG_DATA 0x476c
+#define mmSCL5_SCL_TEST_DEBUG_DATA 0x4a6c
+#define mmGENMO_WT 0xf0
+#define mmGENMO_RD 0xf3
+#define mmGENENB 0xf0
+#define mmGENFC_WT 0xee
+#define mmVGA0_GENFC_WT 0xee
+#define mmVGA1_GENFC_WT 0xf6
+#define mmGENFC_RD 0xf2
+#define mmGENS0 0xf0
+#define mmGENS1 0xee
+#define mmVGA0_GENS1 0xee
+#define mmVGA1_GENS1 0xf6
+#define mmDAC_DATA 0xf2
+#define mmDAC_MASK 0xf1
+#define mmDAC_R_INDEX 0xf1
+#define mmDAC_W_INDEX 0xf2
+#define mmSEQ8_IDX 0xf1
+#define mmSEQ8_DATA 0xf1
+#define ixSEQ00 0x0
+#define ixSEQ01 0x1
+#define ixSEQ02 0x2
+#define ixSEQ03 0x3
+#define ixSEQ04 0x4
+#define mmCRTC8_IDX 0xed
+#define mmVGA0_CRTC8_IDX 0xed
+#define mmVGA1_CRTC8_IDX 0xf5
+#define mmCRTC8_DATA 0xed
+#define mmVGA0_CRTC8_DATA 0xed
+#define mmVGA1_CRTC8_DATA 0xf5
+#define ixCRT00 0x0
+#define ixCRT01 0x1
+#define ixCRT02 0x2
+#define ixCRT03 0x3
+#define ixCRT04 0x4
+#define ixCRT05 0x5
+#define ixCRT06 0x6
+#define ixCRT07 0x7
+#define ixCRT08 0x8
+#define ixCRT09 0x9
+#define ixCRT0A 0xa
+#define ixCRT0B 0xb
+#define ixCRT0C 0xc
+#define ixCRT0D 0xd
+#define ixCRT0E 0xe
+#define ixCRT0F 0xf
+#define ixCRT10 0x10
+#define ixCRT11 0x11
+#define ixCRT12 0x12
+#define ixCRT13 0x13
+#define ixCRT14 0x14
+#define ixCRT15 0x15
+#define ixCRT16 0x16
+#define ixCRT17 0x17
+#define ixCRT18 0x18
+#define ixCRT1E 0x1e
+#define ixCRT1F 0x1f
+#define ixCRT22 0x22
+#define mmGRPH8_IDX 0xf3
+#define mmGRPH8_DATA 0xf3
+#define ixGRA00 0x0
+#define ixGRA01 0x1
+#define ixGRA02 0x2
+#define ixGRA03 0x3
+#define ixGRA04 0x4
+#define ixGRA05 0x5
+#define ixGRA06 0x6
+#define ixGRA07 0x7
+#define ixGRA08 0x8
+#define mmATTRX 0xf0
+#define mmATTRDW 0xf0
+#define mmATTRDR 0xf0
+#define ixATTR00 0x0
+#define ixATTR01 0x1
+#define ixATTR02 0x2
+#define ixATTR03 0x3
+#define ixATTR04 0x4
+#define ixATTR05 0x5
+#define ixATTR06 0x6
+#define ixATTR07 0x7
+#define ixATTR08 0x8
+#define ixATTR09 0x9
+#define ixATTR0A 0xa
+#define ixATTR0B 0xb
+#define ixATTR0C 0xc
+#define ixATTR0D 0xd
+#define ixATTR0E 0xe
+#define ixATTR0F 0xf
+#define ixATTR10 0x10
+#define ixATTR11 0x11
+#define ixATTR12 0x12
+#define ixATTR13 0x13
+#define ixATTR14 0x14
+#define mmVGA_RENDER_CONTROL 0xc0
+#define mmVGA_SOURCE_SELECT 0xfc
+#define mmVGA_SEQUENCER_RESET_CONTROL 0xc1
+#define mmVGA_MODE_CONTROL 0xc2
+#define mmVGA_SURFACE_PITCH_SELECT 0xc3
+#define mmVGA_MEMORY_BASE_ADDRESS 0xc4
+#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0xc9
+#define mmVGA_DISPBUF1_SURFACE_ADDR 0xc6
+#define mmVGA_DISPBUF2_SURFACE_ADDR 0xc8
+#define mmVGA_HDP_CONTROL 0xca
+#define mmVGA_CACHE_CONTROL 0xcb
+#define mmD1VGA_CONTROL 0xcc
+#define mmD2VGA_CONTROL 0xce
+#define mmD3VGA_CONTROL 0xf8
+#define mmD4VGA_CONTROL 0xf9
+#define mmD5VGA_CONTROL 0xfa
+#define mmD6VGA_CONTROL 0xfb
+#define mmVGA_HW_DEBUG 0xcf
+#define mmVGA_STATUS 0xd0
+#define mmVGA_INTERRUPT_CONTROL 0xd1
+#define mmVGA_STATUS_CLEAR 0xd2
+#define mmVGA_INTERRUPT_STATUS 0xd3
+#define mmVGA_MAIN_CONTROL 0xd4
+#define mmVGA_TEST_CONTROL 0xd5
+#define mmVGA_DEBUG_READBACK_INDEX 0xd6
+#define mmVGA_DEBUG_READBACK_DATA 0xd7
+#define mmVGA_MEM_WRITE_PAGE_ADDR 0x12
+#define mmVGA_MEM_READ_PAGE_ADDR 0x13
+#define mmVGA_TEST_DEBUG_INDEX 0xc5
+#define mmVGA_TEST_DEBUG_DATA 0xc7
+#define ixVGADCC_DBG_DCCIF_C 0x7e
+#define mmBPHYC_DAC_MACRO_CNTL 0x19fd
+#define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x19fe
+#define mmDPG_PIPE_ARBITRATION_CONTROL1 0x1b30
+#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1b30
+#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1e30
+#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x4130
+#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4430
+#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4730
+#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4a30
+#define mmDPG_PIPE_ARBITRATION_CONTROL2 0x1b31
+#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1b31
+#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1e31
+#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x4131
+#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4431
+#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4731
+#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4a31
+#define mmDPG_WATERMARK_MASK_CONTROL 0x1b32
+#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x1b32
+#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x1e32
+#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x4132
+#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x4432
+#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x4732
+#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x4a32
+#define mmDPG_PIPE_URGENCY_CONTROL 0x1b33
+#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1b33
+#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1e33
+#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x4133
+#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4433
+#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4733
+#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4a33
+#define mmDPG_PIPE_DPM_CONTROL 0x1b34
+#define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1b34
+#define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1e34
+#define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x4134
+#define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4434
+#define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4734
+#define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4a34
+#define mmDPG_PIPE_STUTTER_CONTROL 0x1b35
+#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1b35
+#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1e35
+#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x4135
+#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4435
+#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4735
+#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4a35
+#define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36
+#define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36
+#define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1e36
+#define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136
+#define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4436
+#define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736
+#define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4a36
+#define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37
+#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37
+#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1e37
+#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137
+#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4437
+#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737
+#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4a37
+#define mmDPG_REPEATER_PROGRAM 0x1b3a
+#define mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x1b3a
+#define mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x1e3a
+#define mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x413a
+#define mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x443a
+#define mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x473a
+#define mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x4a3a
+#define mmDPG_HW_DEBUG_A 0x1b3b
+#define mmDMIF_PG0_DPG_HW_DEBUG_A 0x1b3b
+#define mmDMIF_PG1_DPG_HW_DEBUG_A 0x1e3b
+#define mmDMIF_PG2_DPG_HW_DEBUG_A 0x413b
+#define mmDMIF_PG3_DPG_HW_DEBUG_A 0x443b
+#define mmDMIF_PG4_DPG_HW_DEBUG_A 0x473b
+#define mmDMIF_PG5_DPG_HW_DEBUG_A 0x4a3b
+#define mmDPG_HW_DEBUG_B 0x1b3c
+#define mmDMIF_PG0_DPG_HW_DEBUG_B 0x1b3c
+#define mmDMIF_PG1_DPG_HW_DEBUG_B 0x1e3c
+#define mmDMIF_PG2_DPG_HW_DEBUG_B 0x413c
+#define mmDMIF_PG3_DPG_HW_DEBUG_B 0x443c
+#define mmDMIF_PG4_DPG_HW_DEBUG_B 0x473c
+#define mmDMIF_PG5_DPG_HW_DEBUG_B 0x4a3c
+#define mmDPG_TEST_DEBUG_INDEX 0x1b38
+#define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1b38
+#define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1e38
+#define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x4138
+#define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4438
+#define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4738
+#define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4a38
+#define mmDPG_TEST_DEBUG_DATA 0x1b39
+#define mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1b39
+#define mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1e39
+#define mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x4139
+#define mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4439
+#define mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4739
+#define mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4a39
+#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18
+#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0xf00
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0xf02
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0xf04
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x17d2
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x17d3
+#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x17d5
+#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x17d6
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x17d7
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x17d8
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x17d9
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x17da
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x17db
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x17dc
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x17dd
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x17de
+#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x17d4
+#define mmAZALIA_F0_CODEC_DEBUG 0x17df
+#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x17e1
+#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x17e2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x17e3
+#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x17e4
+#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x17e5
+#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x17e6
+#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x17e7
+#define mmGLOBAL_CAPABILITIES 0x0
+#define mmMINOR_VERSION 0x0
+#define mmMAJOR_VERSION 0x0
+#define mmOUTPUT_PAYLOAD_CAPABILITY 0x1
+#define mmINPUT_PAYLOAD_CAPABILITY 0x1
+#define mmGLOBAL_CONTROL 0x2
+#define mmWAKE_ENABLE 0x3
+#define mmSTATE_CHANGE_STATUS 0x3
+#define mmGLOBAL_STATUS 0x4
+#define mmOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x6
+#define mmINTERRUPT_CONTROL 0x8
+#define mmINTERRUPT_STATUS 0x9
+#define mmWALL_CLOCK_COUNTER 0xc
+#define mmSTREAM_SYNCHRONIZATION 0xe
+#define mmCORB_LOWER_BASE_ADDRESS 0x10
+#define mmCORB_UPPER_BASE_ADDRESS 0x11
+#define mmCORB_WRITE_POINTER 0x12
+#define mmCORB_READ_POINTER 0x12
+#define mmCORB_CONTROL 0x13
+#define mmCORB_STATUS 0x13
+#define mmCORB_SIZE 0x13
+#define mmRIRB_LOWER_BASE_ADDRESS 0x14
+#define mmRIRB_UPPER_BASE_ADDRESS 0x15
+#define mmRIRB_WRITE_POINTER 0x16
+#define mmRESPONSE_INTERRUPT_COUNT 0x16
+#define mmRIRB_CONTROL 0x17
+#define mmRIRB_STATUS 0x17
+#define mmRIRB_SIZE 0x17
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x18
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18
+#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x19
+#define mmIMMEDIATE_COMMAND_STATUS 0x1a
+#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x1c
+#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x1d
+#define mmWALL_CLOCK_COUNTER_ALIAS 0x80c
+#define mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x20
+#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x21
+#define mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x22
+#define mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x23
+#define mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x24
+#define mmOUTPUT_STREAM_DESCRIPTOR_FORMAT 0x24
+#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x26
+#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x27
+#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x821
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e
+#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776
+#define ixAUDIO_DESCRIPTOR0 0x1
+#define ixAUDIO_DESCRIPTOR1 0x2
+#define ixAUDIO_DESCRIPTOR2 0x3
+#define ixAUDIO_DESCRIPTOR3 0x4
+#define ixAUDIO_DESCRIPTOR4 0x5
+#define ixAUDIO_DESCRIPTOR5 0x6
+#define ixAUDIO_DESCRIPTOR6 0x7
+#define ixAUDIO_DESCRIPTOR7 0x8
+#define ixAUDIO_DESCRIPTOR8 0x9
+#define ixAUDIO_DESCRIPTOR9 0xa
+#define ixAUDIO_DESCRIPTOR10 0xb
+#define ixAUDIO_DESCRIPTOR11 0xc
+#define ixAUDIO_DESCRIPTOR12 0xd
+#define ixAUDIO_DESCRIPTOR13 0xe
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x1
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x2
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x3
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x4
+#define ixSINK_DESCRIPTION0 0x5
+#define ixSINK_DESCRIPTION1 0x6
+#define ixSINK_DESCRIPTION2 0x7
+#define ixSINK_DESCRIPTION3 0x8
+#define ixSINK_DESCRIPTION4 0x9
+#define ixSINK_DESCRIPTION5 0xa
+#define ixSINK_DESCRIPTION6 0xb
+#define ixSINK_DESCRIPTION7 0xc
+#define ixSINK_DESCRIPTION8 0xd
+#define ixSINK_DESCRIPTION9 0xe
+#define ixSINK_DESCRIPTION10 0xf
+#define ixSINK_DESCRIPTION11 0x10
+#define ixSINK_DESCRIPTION12 0x11
+#define ixSINK_DESCRIPTION13 0x12
+#define ixSINK_DESCRIPTION14 0x13
+#define ixSINK_DESCRIPTION15 0x14
+#define ixSINK_DESCRIPTION16 0x15
+#define ixSINK_DESCRIPTION17 0x16
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792
+#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797
+#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x17b9
+#define mmAZALIA_AUDIO_DTO 0x17ba
+#define mmAZALIA_AUDIO_DTO_CONTROL 0x17bb
+#define mmAZALIA_SCLK_CONTROL 0x17bc
+#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17bd
+#define mmAZALIA_DATA_DMA_CONTROL 0x17be
+#define mmAZALIA_BDL_DMA_CONTROL 0x17bf
+#define mmAZALIA_RIRB_AND_DP_CONTROL 0x17c0
+#define mmAZALIA_CORB_DMA_CONTROL 0x17c1
+#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17c9
+#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x17ca
+#define mmAZALIA_GLOBAL_CAPABILITIES 0x17cb
+#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17cc
+#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17cd
+#define mmAZALIA_CONTROLLER_DEBUG 0x17cf
+#define mmAZALIA_CRC0_CONTROL0 0x17ae
+#define mmAZALIA_CRC0_CONTROL1 0x17af
+#define mmAZALIA_CRC0_CONTROL2 0x17b0
+#define mmAZALIA_CRC0_CONTROL3 0x17b1
+#define mmAZALIA_CRC0_RESULT 0x17b2
+#define ixAZALIA_CRC0_CHANNEL0 0x0
+#define ixAZALIA_CRC0_CHANNEL1 0x1
+#define ixAZALIA_CRC0_CHANNEL2 0x2
+#define ixAZALIA_CRC0_CHANNEL3 0x3
+#define ixAZALIA_CRC0_CHANNEL4 0x4
+#define ixAZALIA_CRC0_CHANNEL5 0x5
+#define ixAZALIA_CRC0_CHANNEL6 0x6
+#define ixAZALIA_CRC0_CHANNEL7 0x7
+#define mmAZALIA_CRC1_CONTROL0 0x17b3
+#define mmAZALIA_CRC1_CONTROL1 0x17b4
+#define mmAZALIA_CRC1_CONTROL2 0x17b5
+#define mmAZALIA_CRC1_CONTROL3 0x17b6
+#define mmAZALIA_CRC1_RESULT 0x17b7
+#define ixAZALIA_CRC1_CHANNEL0 0x0
+#define ixAZALIA_CRC1_CHANNEL1 0x1
+#define ixAZALIA_CRC1_CHANNEL2 0x2
+#define ixAZALIA_CRC1_CHANNEL3 0x3
+#define ixAZALIA_CRC1_CHANNEL4 0x4
+#define ixAZALIA_CRC1_CHANNEL5 0x5
+#define ixAZALIA_CRC1_CHANNEL6 0x6
+#define ixAZALIA_CRC1_CHANNEL7 0x7
+#define mmAZ_TEST_DEBUG_INDEX 0x17d0
+#define mmAZ_TEST_DEBUG_DATA 0x17d1
+#define mmAZALIA_STREAM_INDEX 0x17e8
+#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x17e8
+#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x17ec
+#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x17f0
+#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x17f4
+#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x17f8
+#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x17fc
+#define mmAZALIA_STREAM_DATA 0x17e9
+#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x17e9
+#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x17ed
+#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x17f1
+#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x17f5
+#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x17f9
+#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x17fd
+#define ixAZALIA_FIFO_SIZE_CONTROL 0x0
+#define ixAZALIA_LATENCY_COUNTER_CONTROL 0x1
+#define ixAZALIA_WORSTCASE_LATENCY_COUNT 0x2
+#define ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x3
+#define ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x4
+#define ixAZALIA_STREAM_DEBUG 0x5
+#define mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1786
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x178c
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1792
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1798
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x179e
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a4
+#define mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x1781
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1781
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1787
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x178d
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1793
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1799
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x179f
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17a5
+#define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0
+#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1
+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2
+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3
+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4
+#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x5
+#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6
+#define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x7
+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x8
+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x9
+#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG 0xa
+#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0xc
+#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0xd
+#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0xe
+#define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20
+#define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x21
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x23
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x24
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2a
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2b
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2c
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2d
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2e
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2f
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x57
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x58
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x59
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x5a
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x5b
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x5c
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x5d
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x5e
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x5f
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x60
+#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x61
+#define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x62
+#define ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x63
+#define mmBLND_CONTROL 0x1b6d
+#define mmBLND0_BLND_CONTROL 0x1b6d
+#define mmBLND1_BLND_CONTROL 0x1e6d
+#define mmBLND2_BLND_CONTROL 0x416d
+#define mmBLND3_BLND_CONTROL 0x446d
+#define mmBLND4_BLND_CONTROL 0x476d
+#define mmBLND5_BLND_CONTROL 0x4a6d
+#define mmSM_CONTROL2 0x1b6e
+#define mmBLND0_SM_CONTROL2 0x1b6e
+#define mmBLND1_SM_CONTROL2 0x1e6e
+#define mmBLND2_SM_CONTROL2 0x416e
+#define mmBLND3_SM_CONTROL2 0x446e
+#define mmBLND4_SM_CONTROL2 0x476e
+#define mmBLND5_SM_CONTROL2 0x4a6e
+#define mmPTI_CONTROL 0x1b6f
+#define mmBLND0_PTI_CONTROL 0x1b6f
+#define mmBLND1_PTI_CONTROL 0x1e6f
+#define mmBLND2_PTI_CONTROL 0x416f
+#define mmBLND3_PTI_CONTROL 0x446f
+#define mmBLND4_PTI_CONTROL 0x476f
+#define mmBLND5_PTI_CONTROL 0x4a6f
+#define mmBLND_UPDATE 0x1b70
+#define mmBLND0_BLND_UPDATE 0x1b70
+#define mmBLND1_BLND_UPDATE 0x1e70
+#define mmBLND2_BLND_UPDATE 0x4170
+#define mmBLND3_BLND_UPDATE 0x4470
+#define mmBLND4_BLND_UPDATE 0x4770
+#define mmBLND5_BLND_UPDATE 0x4a70
+#define mmBLND_UNDERFLOW_INTERRUPT 0x1b71
+#define mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x1b71
+#define mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x1e71
+#define mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x4171
+#define mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x4471
+#define mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x4771
+#define mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x4a71
+#define mmBLND_V_UPDATE_LOCK 0x1b73
+#define mmBLND0_BLND_V_UPDATE_LOCK 0x1b73
+#define mmBLND1_BLND_V_UPDATE_LOCK 0x1e73
+#define mmBLND2_BLND_V_UPDATE_LOCK 0x4173
+#define mmBLND3_BLND_V_UPDATE_LOCK 0x4473
+#define mmBLND4_BLND_V_UPDATE_LOCK 0x4773
+#define mmBLND5_BLND_V_UPDATE_LOCK 0x4a73
+#define mmBLND_REG_UPDATE_STATUS 0x1b77
+#define mmBLND0_BLND_REG_UPDATE_STATUS 0x1b77
+#define mmBLND1_BLND_REG_UPDATE_STATUS 0x1e77
+#define mmBLND2_BLND_REG_UPDATE_STATUS 0x4177
+#define mmBLND3_BLND_REG_UPDATE_STATUS 0x4477
+#define mmBLND4_BLND_REG_UPDATE_STATUS 0x4777
+#define mmBLND5_BLND_REG_UPDATE_STATUS 0x4a77
+#define mmBLND_DEBUG 0x1b74
+#define mmBLND0_BLND_DEBUG 0x1b74
+#define mmBLND1_BLND_DEBUG 0x1e74
+#define mmBLND2_BLND_DEBUG 0x4174
+#define mmBLND3_BLND_DEBUG 0x4474
+#define mmBLND4_BLND_DEBUG 0x4774
+#define mmBLND5_BLND_DEBUG 0x4a74
+#define mmBLND_TEST_DEBUG_INDEX 0x1b75
+#define mmBLND0_BLND_TEST_DEBUG_INDEX 0x1b75
+#define mmBLND1_BLND_TEST_DEBUG_INDEX 0x1e75
+#define mmBLND2_BLND_TEST_DEBUG_INDEX 0x4175
+#define mmBLND3_BLND_TEST_DEBUG_INDEX 0x4475
+#define mmBLND4_BLND_TEST_DEBUG_INDEX 0x4775
+#define mmBLND5_BLND_TEST_DEBUG_INDEX 0x4a75
+#define mmBLND_TEST_DEBUG_DATA 0x1b76
+#define mmBLND0_BLND_TEST_DEBUG_DATA 0x1b76
+#define mmBLND1_BLND_TEST_DEBUG_DATA 0x1e76
+#define mmBLND2_BLND_TEST_DEBUG_DATA 0x4176
+#define mmBLND3_BLND_TEST_DEBUG_DATA 0x4476
+#define mmBLND4_BLND_TEST_DEBUG_DATA 0x4776
+#define mmBLND5_BLND_TEST_DEBUG_DATA 0x4a76
+#define mmSI_ENABLE 0x4c00
+#define mmSI_EC_CONFIG 0x4c01
+#define mmCNV_MODE 0x4c02
+#define mmCNV_WINDOW_START 0x4c03
+#define mmCNV_WINDOW_SIZE 0x4c04
+#define mmCNV_UPDATE 0x4c05
+#define mmCNV_SOURCE_SIZE 0x4c06
+#define mmCNV_CSC_CONTROL 0x4c07
+#define mmCNV_CSC_C11_C12 0x4c08
+#define mmCNV_CSC_C13_C14 0x4c09
+#define mmCNV_CSC_C21_C22 0x4c0a
+#define mmCNV_CSC_C23_C24 0x4c0b
+#define mmCNV_CSC_C31_C32 0x4c0c
+#define mmCNV_CSC_C33_C34 0x4c0d
+#define mmCNV_CSC_ROUND_OFFSET_R 0x4c0e
+#define mmCNV_CSC_ROUND_OFFSET_G 0x4c0f
+#define mmCNV_CSC_ROUND_OFFSET_B 0x4c10
+#define mmCNV_CSC_CLAMP_R 0x4c11
+#define mmCNV_CSC_CLAMP_G 0x4c12
+#define mmCNV_CSC_CLAMP_B 0x4c13
+#define mmCNV_TEST_CNTL 0x4c14
+#define mmCNV_TEST_CRC_RED 0x4c15
+#define mmCNV_TEST_CRC_GREEN 0x4c16
+#define mmCNV_TEST_CRC_BLUE 0x4c17
+#define mmSI_DEBUG_CTRL 0x4c18
+#define mmSI_DBG_MODE 0x4c1b
+#define mmSI_HARD_DEBUG 0x4c1c
+#define mmCNV_TEST_DEBUG_INDEX 0x4c19
+#define mmCNV_TEST_DEBUG_DATA 0x4c1a
+#define mmSISCL_COEF_RAM_SELECT 0x4c20
+#define mmSISCL_COEF_RAM_TAP_DATA 0x4c21
+#define mmSISCL_MODE 0x4c22
+#define mmSISCL_TAP_CONTROL 0x4c23
+#define mmSISCL_DEST_SIZE 0x4c24
+#define mmSISCL_HORZ_FILTER_SCALE_RATIO 0x4c25
+#define mmSISCL_HORZ_FILTER_INIT_Y_RGB 0x4c26
+#define mmSISCL_HORZ_FILTER_INIT_CBCR 0x4c27
+#define mmSISCL_VERT_FILTER_SCALE_RATIO 0x4c28
+#define mmSISCL_VERT_FILTER_INIT_Y_RGB 0x4c29
+#define mmSISCL_VERT_FILTER_INIT_CBCR 0x4c2a
+#define mmSISCL_ROUND_OFFSET 0x4c2b
+#define mmSISCL_CLAMP 0x4c2c
+#define mmSISCL_OVERFLOW_STATUS 0x4c2d
+#define mmSISCL_COEF_RAM_CONFLICT_STATUS 0x4c2e
+#define mmSISCL_OUTSIDE_PIX_STRATEGY 0x4c2f
+#define mmSISCL_TEST_CNTL 0x4c30
+#define mmSISCL_TEST_CRC_RED 0x4c31
+#define mmSISCL_TEST_CRC_GREEN 0x4c32
+#define mmSISCL_TEST_CRC_BLUE 0x4c33
+#define mmSISCL_BACKPRESSURE_CNT_EN 0x4c36
+#define mmSISCL_MCIF_BACKPRESSURE_CNT 0x4c37
+#define mmSISCL_TEST_DEBUG_INDEX 0x4c34
+#define mmSISCL_TEST_DEBUG_DATA 0x4c35
+#define mmXDMA_MC_PCIE_CLIENT_CONFIG 0x3e0
+#define mmXDMA_LOCAL_SURFACE_TILING1 0x3e1
+#define mmXDMA_LOCAL_SURFACE_TILING2 0x3e2
+#define mmXDMA_INTERRUPT 0x3e3
+#define mmXDMA_CLOCK_GATING_CNTL 0x3e4
+#define mmXDMA_MEM_POWER_CNTL 0x3e6
+#define mmXDMA_IF_BIF_STATUS 0x3e7
+#define mmXDMA_PERF_MEAS_STATUS 0x3e8
+#define mmXDMA_IF_STATUS 0x3e9
+#define mmXDMA_TEST_DEBUG_INDEX 0x3ea
+#define mmXDMA_TEST_DEBUG_DATA 0x3eb
+#define mmXDMA_RBBMIF_RDWR_CNTL 0x3f8
+#define mmXDMA_PG_CONTROL 0x3f9
+#define mmXDMA_PG_WDATA 0x3fa
+#define mmXDMA_PG_STATUS 0x3fb
+#define mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc
+#define mmXDMA_AON_TEST_DEBUG_DATA 0x3fd
+
+#endif /* DCE_8_0_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h
new file mode 100644
index 000000000000..8a2930734477
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h
@@ -0,0 +1,13109 @@
+/*
+ * DCE_8_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef DCE_8_0_SH_MASK_H
+#define DCE_8_0_SH_MASK_H
+
+#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
+#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
+#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
+#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
+#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
+#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
+#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
+#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
+#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
+#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
+#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000
+#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT 0x1d
+#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xc0000000
+#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x1
+#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x0
+#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x1
+#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x0
+#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK 0xffffff
+#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT 0x0
+#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS_MASK 0x3000000
+#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS__SHIFT 0x18
+#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000
+#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x1c
+#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK 0x20000000
+#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x1d
+#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xc0000000
+#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x1
+#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x0
+#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x1
+#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x0
+#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK 0xffffff
+#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT 0x0
+#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS_MASK 0x3000000
+#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS__SHIFT 0x18
+#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000
+#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x1c
+#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK 0x20000000
+#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT 0x1d
+#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xc0000000
+#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x1
+#define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT 0x0
+#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x1
+#define PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT 0x0
+#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA_MASK 0xffffff
+#define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA__SHIFT 0x0
+#define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS_MASK 0x3000000
+#define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS__SHIFT 0x18
+#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK 0x10000000
+#define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT 0x1c
+#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE_MASK 0x20000000
+#define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE__SHIFT 0x1d
+#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK 0xc0000000
+#define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x1
+#define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT 0x0
+#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x1
+#define PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT 0x0
+#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA_MASK 0xffffff
+#define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA__SHIFT 0x0
+#define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS_MASK 0x3000000
+#define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS__SHIFT 0x18
+#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK 0x10000000
+#define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x1c
+#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE_MASK 0x20000000
+#define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE__SHIFT 0x1d
+#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK 0xc0000000
+#define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK 0x1
+#define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT 0x0
+#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK 0x1
+#define PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT 0x0
+#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA_MASK 0xffffff
+#define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA__SHIFT 0x0
+#define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS_MASK 0x3000000
+#define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS__SHIFT 0x18
+#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000
+#define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT 0x1c
+#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK 0x20000000
+#define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE__SHIFT 0x1d
+#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xc0000000
+#define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT 0x1e
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x1
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0
+#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK 0xffffffff
+#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT 0x0
+#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK 0xffffffff
+#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT 0x0
+#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK 0x1
+#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT 0x0
+#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x2
+#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT 0x1
+#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK 0x4
+#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x2
+#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK 0xffff0000
+#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x10
+#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK 0xff
+#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT 0x0
+#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x1ffff
+#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0
+#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x1ffff
+#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0
+#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x1ffff
+#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0
+#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x1ffff
+#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0
+#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x1ffff
+#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0
+#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x1ffff
+#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0
+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x1
+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0
+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x2
+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x4
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x8
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xffff0000
+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x1
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000
+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x1
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x100
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x10000
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0xe0000
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x1000000
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000
+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f
+#define DC_ABM1_CNTL__ABM1_EN_MASK 0x1
+#define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0
+#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x700
+#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8
+#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000
+#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x1f
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0xf
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0xf00
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0xf0000
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000
+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x7fff
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x7ff0000
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000
+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x7fff
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x7ff0000
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000
+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x7fff
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x7ff0000
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000
+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x7fff
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x7ff0000
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000
+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x7fff
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x7ff0000
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000
+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x3ff
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x3ff0000
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000
+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x3ff
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x3ff0000
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000
+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f
+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x1
+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0
+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x100
+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8
+#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK 0x1
+#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT 0x0
+#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x100
+#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x8
+#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK 0x10000
+#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT 0x10
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x1
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x2
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x4
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x100
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x200
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x400
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x10000
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x1000000
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000
+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x3
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x100
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x1000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x30000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10
+#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x100000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x800000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x7000000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000
+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xffffffff
+#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0
+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x3ff
+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0
+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x3ff0000
+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10
+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x3ff
+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0
+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x3ff0000
+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10
+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0xffffff
+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0
+#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0xffffff
+#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x0
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x3ff
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x3ff0000
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000
+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0xffffff
+#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0
+#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0xffffff
+#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x1
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000
+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x1
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000
+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f
+#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xffffffff
+#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0
+#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xffffffff
+#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0
+#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xffffffff
+#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0
+#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xffffffff
+#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0
+#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xffffffff
+#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0
+#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xffffffff
+#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x3ff
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x0
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0xffc00
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0xa
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3ff00000
+#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x14
+#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000
+#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f
+#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0xff
+#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x0
+#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffff
+#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x0
+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x10
+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4
+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE_MASK 0x100
+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8
+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE_MASK 0x1000
+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc
+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL_MASK 0x1f000000
+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL__SHIFT 0x18
+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE_MASK 0x80000000
+#define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE__SHIFT 0x1f
+#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x3ff
+#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0
+#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x10000
+#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10
+#define DCFE_DBG_SEL__DCFE_DBG_SEL_MASK 0xf
+#define DCFE_DBG_SEL__DCFE_DBG_SEL__SHIFT 0x0
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS_MASK 0x1
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS__SHIFT 0x0
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_LIGHT_SLEEP_DIS_MASK 0x2
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_LIGHT_SLEEP_DIS__SHIFT 0x1
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS_MASK 0x4
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS__SHIFT 0x2
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS_MASK 0x8
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS__SHIFT 0x3
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS_MASK 0x10
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS__SHIFT 0x4
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS_MASK 0x20
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS__SHIFT 0x5
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS_MASK 0x40
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS__SHIFT 0x6
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE_MASK 0x300
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x8
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_MEM_PWR_STATE_MASK 0xc00
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0xa
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE_MASK 0x3000
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE__SHIFT 0xc
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE_MASK 0xc000
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE__SHIFT 0xe
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0_MASK 0x30000
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0__SHIFT 0x10
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE_MASK 0xc0000
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE__SHIFT 0x12
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE_MASK 0x300000
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE__SHIFT 0x14
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1_MASK 0xc00000
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1__SHIFT 0x16
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2_MASK 0x3000000
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2__SHIFT 0x18
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS_MASK 0x10000000
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS__SHIFT 0x1c
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS_MASK 0x20000000
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS__SHIFT 0x1d
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS_MASK 0x40000000
+#define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS__SHIFT 0x1e
+#define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x1fff
+#define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0
+#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x1fff
+#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0
+#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x1fff0000
+#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10
+#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x1fff
+#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0
+#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x1fff0000
+#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10
+#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x1
+#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0
+#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x10000
+#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10
+#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x20000
+#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11
+#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x1fff
+#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0
+#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x1fff0000
+#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10
+#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x1
+#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0
+#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x10000
+#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10
+#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x20000
+#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11
+#define CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x1fff
+#define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0
+#define CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x1fff0000
+#define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10
+#define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x1fff
+#define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0
+#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x1fff
+#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0
+#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x1fff
+#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0
+#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x10000
+#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10
+#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x1
+#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0
+#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x10
+#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4
+#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100
+#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8
+#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x1000
+#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc
+#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x8000
+#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf
+#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000
+#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x1
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x10
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x100
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x1000
+#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc
+#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x1
+#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0
+#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x10
+#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4
+#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x1fff
+#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0
+#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x1fff0000
+#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10
+#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x1fff
+#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0
+#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x1fff0000
+#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10
+#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x1
+#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0
+#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x1fff
+#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0
+#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x1fff0000
+#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10
+#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x1
+#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0
+#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x1
+#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0
+#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x1e
+#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1
+#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x1fff
+#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0
+#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x1fff0000
+#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x1f
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0xe0
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x100
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x400
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x3000
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x30000
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x300000
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000
+#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f
+#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x1
+#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x1f
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0xe0
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x100
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x400
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x3000
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x30000
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x300000
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000
+#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f
+#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x1
+#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x3
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x10
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x100
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x10000
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x1000000
+#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x1f
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x100
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x10000
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x1000000
+#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18
+#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x3
+#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0
+#define CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x1
+#define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x10
+#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4
+#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x300
+#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8
+#define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000
+#define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc
+#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x2000
+#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd
+#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x4000
+#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe
+#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x10000
+#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10
+#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x700000
+#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14
+#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x1000000
+#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x18
+#define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000
+#define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d
+#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x1
+#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0
+#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x100
+#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8
+#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x10000
+#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10
+#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x1
+#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0
+#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x30000
+#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10
+#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x1
+#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0
+#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x2
+#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1
+#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x1
+#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0
+#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x2
+#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1
+#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0xfff
+#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0
+#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0xfff0000
+#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10
+#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0xfff
+#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0
+#define CRTC_STATUS__CRTC_V_BLANK_MASK 0x1
+#define CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0
+#define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x2
+#define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1
+#define CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x4
+#define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2
+#define CRTC_STATUS__CRTC_V_UPDATE_MASK 0x8
+#define CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3
+#define CRTC_STATUS__CRTC_V_START_LINE_MASK 0x10
+#define CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4
+#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x20
+#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5
+#define CRTC_STATUS__CRTC_H_BLANK_MASK 0x10000
+#define CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10
+#define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x20000
+#define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11
+#define CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x40000
+#define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12
+#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x1fff
+#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0
+#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x1fff0000
+#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10
+#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x1fff
+#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0
+#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0xffffff
+#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0
+#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x1fffffff
+#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0
+#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x1fffffff
+#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0
+#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x1
+#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0
+#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x1e
+#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1
+#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x1
+#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0
+#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x1
+#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0
+#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x1
+#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0
+#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x100
+#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8
+#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x30000
+#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10
+#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x1
+#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0
+#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x100
+#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8
+#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x10000
+#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10
+#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x3000000
+#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x1fff
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x8000
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x10000
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x1000000
+#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18
+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x1
+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0
+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x2
+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1
+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x4
+#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2
+#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x3
+#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0
+#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x1fff
+#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0
+#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x1fff0000
+#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10
+#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0xffffff
+#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0
+#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x1
+#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0
+#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x100
+#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x8
+#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0xf0000
+#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0x10
+#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100000
+#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x14
+#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x10000000
+#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x1c
+#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x1
+#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0
+#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x2
+#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1
+#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x10
+#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4
+#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x20
+#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x100
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x10000
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x20000
+#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x1000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x2000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x4000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x8000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b
+#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c
+#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d
+#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e
+#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000
+#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f
+#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x1
+#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0
+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x1
+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0
+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x100
+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8
+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x10000
+#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10
+#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x1
+#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x1
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x700
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x10000
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000
+#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0xf
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0xf0
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0xf00
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0xf000
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000
+#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10
+#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0xffff
+#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0
+#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x3f0000
+#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10
+#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x1
+#define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0
+#define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x100
+#define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8
+#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x7
+#define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0
+#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x30000
+#define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10
+#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x3
+#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0
+#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00
+#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8
+#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0xff
+#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0
+#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x1
+#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0
+#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x10
+#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4
+#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x10000
+#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10
+#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x100000
+#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14
+#define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x1
+#define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0
+#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0xff
+#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0
+#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x10000
+#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10
+#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x1
+#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0
+#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x100
+#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8
+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x3ff
+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0
+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0xffc00
+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa
+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000
+#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14
+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x3
+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0
+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x300
+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8
+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x30000
+#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10
+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x3ff
+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0
+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0xffc00
+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa
+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000
+#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14
+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x3
+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0
+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x300
+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8
+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x30000
+#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10
+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x3ff
+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0
+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0xffc00
+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa
+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000
+#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14
+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x3
+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0
+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x300
+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8
+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x30000
+#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10
+#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x1fff
+#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0
+#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x1fff0000
+#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x10
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x100
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x1000
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x10000
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x100000
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x1000000
+#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18
+#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x1fff
+#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x100
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x1000
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x10000
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x100000
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x1000000
+#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18
+#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x1fff
+#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x100
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x1000
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x10000
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x100000
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x1000000
+#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18
+#define CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x1
+#define CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0
+#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x10
+#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4
+#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x300
+#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8
+#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x3000
+#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc
+#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000
+#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x700000
+#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14
+#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x7000000
+#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18
+#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x1fff
+#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0
+#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x1fff0000
+#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10
+#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x1fff
+#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0
+#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x1fff0000
+#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10
+#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x1fff
+#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0
+#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x1fff0000
+#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10
+#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x1fff
+#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0
+#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x1fff0000
+#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10
+#define CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0xffff
+#define CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0
+#define CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xffff0000
+#define CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10
+#define CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0xffff
+#define CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0
+#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x1fff
+#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0
+#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x1fff0000
+#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10
+#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x1fff
+#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0
+#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x1fff0000
+#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10
+#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x1fff
+#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0
+#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x1fff0000
+#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10
+#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x1fff
+#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0
+#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x1fff0000
+#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10
+#define CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0xffff
+#define CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0
+#define CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xffff0000
+#define CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10
+#define CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0xffff
+#define CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x3
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x8
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x10
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x60
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x100
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x200
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x1000
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x2000
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x4000
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x7000000
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000
+#define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c
+#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x1fff
+#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0
+#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x1fff0000
+#define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10
+#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x1fff
+#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0
+#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x1fff0000
+#define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x1
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x10
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x100
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x10000
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x100000
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xe0000000
+#define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d
+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x1
+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0
+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x10
+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4
+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x100
+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8
+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x10000
+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10
+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x100000
+#define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14
+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x1
+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0
+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x10
+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4
+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x100
+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8
+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x10000
+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10
+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x100000
+#define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0xffff
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0xff0000
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x1000000
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x2000000
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x4000000
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x8000000
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000
+#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x1
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x10
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x300
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x1000
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x10000
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x20000
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0xc0000
+#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0xff
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0xff00
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x10000
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x60000
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x80000
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x100000
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x800000
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000
+#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18
+#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x1fff
+#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0
+#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x1fff0000
+#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10
+#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x1fff
+#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0
+#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x1f0000
+#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10
+#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000
+#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c
+#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0xff
+#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x0
+#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffff
+#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x0
+#define DAC_ENABLE__DAC_ENABLE_MASK 0x1
+#define DAC_ENABLE__DAC_ENABLE__SHIFT 0x0
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x2
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x1
+#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0xc
+#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x2
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x10
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x4
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x20
+#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x5
+#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x100
+#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x8
+#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x7
+#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x0
+#define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x8
+#define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x3
+#define DAC_CRC_EN__DAC_CRC_EN_MASK 0x1
+#define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x0
+#define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x10000
+#define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x10
+#define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x1
+#define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x0
+#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb_MASK 0x100
+#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb__SHIFT 0x8
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x3ff
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x0
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0xffc00
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0xa
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3ff00000
+#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x14
+#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x3f
+#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x0
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x3ff
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x0
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0xffc00
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0xa
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3ff00000
+#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x14
+#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x3f
+#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x0
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x1
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x0
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x100
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x8
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x10000
+#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x10
+#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x7
+#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x0
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x3
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x0
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0xff00
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x8
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x70000
+#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x10
+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0xff
+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x0
+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x100
+#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x8
+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0xff
+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x0
+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0xff00
+#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x8
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x1
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x0
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x10
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x4
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x300
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x8
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x30000
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x10
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x3000000
+#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x18
+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x1
+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x0
+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x10000
+#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x10
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x1
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x0
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x700
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x8
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x1000000
+#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x18
+#define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x3ff
+#define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x0
+#define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x1
+#define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x0
+#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x100
+#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x8
+#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x10000
+#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x10
+#define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x1000000
+#define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x18
+#define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x1
+#define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x0
+#define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x100
+#define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x8
+#define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x10000
+#define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x10
+#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x1
+#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x0
+#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x100
+#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x8
+#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x10000
+#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x10
+#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x20000
+#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x11
+#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x40000
+#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x12
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x1
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x0
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x2
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x1
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x4
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x2
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x8
+#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x3
+#define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x3
+#define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x0
+#define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x30000
+#define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x10
+#define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xffffffff
+#define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x0
+#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
+#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0xfc
+#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00
+#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0xf0000
+#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x3c00000
+#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000
+#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x1d
+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000
+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000
+#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x1ff
+#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0
+#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x3000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc
+#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x4000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xe
+#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x8000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0xf
+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x1f0000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x10
+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x200000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x15
+#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x400000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x16
+#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x800000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x17
+#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x1000000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x18
+#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x2000000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x19
+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xe0000000
+#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x3
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x4
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x30
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x40
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x300
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x400
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x3000
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x4000
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x30000
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x40000
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x300000
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x400000
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x3000000
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x4000000
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000
+#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000
+#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e
+#define PERFMON_CNTL__PERFMON_STATE_MASK 0x3
+#define PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL_MASK 0xf0
+#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL__SHIFT 0x4
+#define PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0xfffff00
+#define PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8
+#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000
+#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c
+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000
+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d
+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000
+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e
+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000
+#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x1
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x2
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x4
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x8
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x10
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x20
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x40
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x80
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x100
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x200
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x400
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x800
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x1000
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x2000
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x4000
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x8000
+#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf
+#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xffff0000
+#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10
+#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xffffffff
+#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0
+#define PERFMON_HI__PERFMON_HI_MASK 0xffff
+#define PERFMON_HI__PERFMON_HI__SHIFT 0x0
+#define PERFMON_HI__PERFMON_READ_SEL_MASK 0xe0000000
+#define PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d
+#define PERFMON_LOW__PERFMON_LOW_MASK 0xffffffff
+#define PERFMON_LOW__PERFMON_LOW__SHIFT 0x0
+#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX_MASK 0xff
+#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX__SHIFT 0x0
+#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA_MASK 0xffffffff
+#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA__SHIFT 0x0
+#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV_MASK 0x3ff
+#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV__SHIFT 0x0
+#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV_MASK 0x3ff
+#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV__SHIFT 0x0
+#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV_MASK 0x3ff
+#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV__SHIFT 0x0
+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_MASK 0xf
+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION__SHIFT 0x0
+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30
+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_MASK 0x7ff0000
+#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV__SHIFT 0x10
+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_MASK 0xf
+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION__SHIFT 0x0
+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30
+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_MASK 0x7ff0000
+#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV__SHIFT 0x10
+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_MASK 0xf
+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION__SHIFT 0x0
+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30
+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_MASK 0x7ff0000
+#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV__SHIFT 0x10
+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x7f
+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK__SHIFT 0x0
+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK_MASK 0x7f00
+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK__SHIFT 0x8
+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK_MASK 0x7f0000
+#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK__SHIFT 0x10
+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK_MASK 0x7f
+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK__SHIFT 0x0
+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK_MASK 0x7f00
+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK__SHIFT 0x8
+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK_MASK 0x7f0000
+#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK__SHIFT 0x10
+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK_MASK 0x7f
+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK__SHIFT 0x0
+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK_MASK 0x7f00
+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK__SHIFT 0x8
+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK_MASK 0x7f0000
+#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK__SHIFT 0x10
+#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK 0x1f
+#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT 0x0
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL_MASK 0x60
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL__SHIFT 0x5
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK 0xf00
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP__SHIFT 0x8
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE_MASK 0x1ff000
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE__SHIFT 0xc
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS_MASK 0xff000000
+#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS__SHIFT 0x18
+#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE_MASK 0x1f
+#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE__SHIFT 0x0
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL_MASK 0x60
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL__SHIFT 0x5
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP_MASK 0xf00
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP__SHIFT 0x8
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE_MASK 0x1ff000
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE__SHIFT 0xc
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS_MASK 0xff000000
+#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS__SHIFT 0x18
+#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE_MASK 0x1f
+#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE__SHIFT 0x0
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL_MASK 0x60
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL__SHIFT 0x5
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP_MASK 0xf00
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP__SHIFT 0x8
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE_MASK 0x1ff000
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE__SHIFT 0xc
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS_MASK 0xff000000
+#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS__SHIFT 0x18
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x7
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0
+#define DPREFCLK_CNTL__DPREFCLK_CLOCK_EN_MASK 0x10
+#define DPREFCLK_CNTL__DPREFCLK_CLOCK_EN__SHIFT 0x4
+#define SCANIN_SOFT_RESET__SCANIN_SOFT_RESET_MASK 0x1
+#define SCANIN_SOFT_RESET__SCANIN_SOFT_RESET__SHIFT 0x0
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x1
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xffffffff
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xffffffff
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xffffffff
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xffffffff
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xffffffff
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x1
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x100
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x200
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x30000
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x1000000
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x2000000
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xffffffff
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE_MASK 0x1
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE__SHIFT 0x0
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE_MASK 0x1ff0
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE__SHIFT 0x4
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED_MASK 0x10000
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED__SHIFT 0x10
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR_MASK 0x20000
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR__SHIFT 0x11
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE_MASK 0x100000
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE__SHIFT 0x14
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL_MASK 0x200000
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL__SHIFT 0x15
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_MASK 0xff000000
+#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT__SHIFT 0x18
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x1
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xffff0000
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10
+#define SMU_CONTROL__DISPLAY0_FORCE_VBI_MASK 0x1
+#define SMU_CONTROL__DISPLAY0_FORCE_VBI__SHIFT 0x0
+#define SMU_CONTROL__DISPLAY1_FORCE_VBI_MASK 0x2
+#define SMU_CONTROL__DISPLAY1_FORCE_VBI__SHIFT 0x1
+#define SMU_CONTROL__DISPLAY2_FORCE_VBI_MASK 0x4
+#define SMU_CONTROL__DISPLAY2_FORCE_VBI__SHIFT 0x2
+#define SMU_CONTROL__DISPLAY3_FORCE_VBI_MASK 0x8
+#define SMU_CONTROL__DISPLAY3_FORCE_VBI__SHIFT 0x3
+#define SMU_CONTROL__DISPLAY4_FORCE_VBI_MASK 0x10
+#define SMU_CONTROL__DISPLAY4_FORCE_VBI__SHIFT 0x4
+#define SMU_CONTROL__DISPLAY5_FORCE_VBI_MASK 0x20
+#define SMU_CONTROL__DISPLAY5_FORCE_VBI__SHIFT 0x5
+#define SMU_CONTROL__SMU_DC_INT_CLEAR_MASK 0x10000
+#define SMU_CONTROL__SMU_DC_INT_CLEAR__SHIFT 0x10
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x1
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x10
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10
+#define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x1
+#define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x0
+#define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x10
+#define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x4
+#define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x1
+#define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x0
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x1
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x2
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1
+#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x4
+#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x2
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x8
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x10
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4
+#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x20
+#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x5
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x40
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6
+#define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE_MASK 0x100
+#define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE__SHIFT 0x8
+#define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE_MASK 0x200
+#define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE__SHIFT 0x9
+#define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE_MASK 0x400
+#define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE__SHIFT 0xa
+#define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE_MASK 0x800
+#define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE__SHIFT 0xb
+#define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE_MASK 0x1000
+#define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE__SHIFT 0xc
+#define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE_MASK 0x2000
+#define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE__SHIFT 0xd
+#define DCCG_GATE_DISABLE_CNTL__SYMCLKG_GATE_DISABLE_MASK 0x4000
+#define DCCG_GATE_DISABLE_CNTL__SYMCLKG_GATE_DISABLE__SHIFT 0xe
+#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE_MASK 0x10000
+#define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE__SHIFT 0x10
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x20000
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x40000
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x80000
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE_MASK 0x100000
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE__SHIFT 0x14
+#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x200000
+#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x400000
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID_MASK 0x7000000
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID__SHIFT 0x18
+#define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID_MASK 0x70000000
+#define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID__SHIFT 0x1c
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0xf
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0xff0
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE_MASK 0x1000
+#define DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE__SHIFT 0xc
+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0xf
+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x0
+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0xff0
+#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE_MASK 0x1000
+#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE__SHIFT 0xc
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xffffffff
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0
+#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x1
+#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x0
+#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x30
+#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x4
+#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x1
+#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x0
+#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x30
+#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x4
+#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x1
+#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x0
+#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x30
+#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x4
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x7f
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x7f00
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x10000
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x20000
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x100
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8
+#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK 0x1
+#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT 0x0
+#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ_MASK 0xf0
+#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ__SHIFT 0x4
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x1
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x2
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x10
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x20
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x100
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x200
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x1000
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x2000
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x10000
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x20000
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x100000
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x200000
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x1000000
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x2000000
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x1ffff
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x3fff
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0xf0000
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x100000
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0xe000000
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f
+#define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS_MASK 0x1
+#define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS__SHIFT 0x0
+#define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS_MASK 0x100
+#define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS__SHIFT 0x8
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x1
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x2
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x4
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x8
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x10
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4
+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x20
+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x40
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x80
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7
+#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x700
+#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x8
+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xfffff800
+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x3
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x10
+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4
+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x20
+#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x100
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x8
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x200
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x9
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0xc000
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0xfff0000
+#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xffffffff
+#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0
+#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xffffffff
+#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x3
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x10
+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4
+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x20
+#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x100
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x8
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x200
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x9
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0xc000
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0xfff0000
+#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xffffffff
+#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0
+#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xffffffff
+#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x3
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x10
+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4
+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x20
+#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x100
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x8
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x200
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x9
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0xc000
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0xfff0000
+#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xffffffff
+#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0
+#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xffffffff
+#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x3
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x10
+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4
+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x20
+#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x100
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x8
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x200
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x9
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0xc000
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0xfff0000
+#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xffffffff
+#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0
+#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xffffffff
+#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x3
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x10
+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x4
+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK 0x20
+#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT 0x5
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x100
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x8
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x200
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x9
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0xc000
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0xfff0000
+#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xffffffff
+#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x0
+#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xffffffff
+#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x0
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x3
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x0
+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x10
+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x4
+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK 0x20
+#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT 0x5
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x100
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x8
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x200
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x9
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0xc000
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0xe
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0xfff0000
+#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x10
+#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xffffffff
+#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x0
+#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xffffffff
+#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x0
+#define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET_MASK 0x1
+#define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET__SHIFT 0x0
+#define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET_MASK 0x2
+#define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET__SHIFT 0x1
+#define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET_MASK 0x4
+#define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET__SHIFT 0x2
+#define DCFE0_SOFT_RESET__SCL0_SOFT_RESET_MASK 0x8
+#define DCFE0_SOFT_RESET__SCL0_SOFT_RESET__SHIFT 0x3
+#define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET_MASK 0x10
+#define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET__SHIFT 0x4
+#define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET_MASK 0x1
+#define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET__SHIFT 0x0
+#define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET_MASK 0x2
+#define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET__SHIFT 0x1
+#define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET_MASK 0x4
+#define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET__SHIFT 0x2
+#define DCFE1_SOFT_RESET__SCL1_SOFT_RESET_MASK 0x8
+#define DCFE1_SOFT_RESET__SCL1_SOFT_RESET__SHIFT 0x3
+#define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET_MASK 0x10
+#define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET__SHIFT 0x4
+#define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET_MASK 0x1
+#define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET__SHIFT 0x0
+#define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET_MASK 0x2
+#define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET__SHIFT 0x1
+#define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET_MASK 0x4
+#define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET__SHIFT 0x2
+#define DCFE2_SOFT_RESET__SCL2_SOFT_RESET_MASK 0x8
+#define DCFE2_SOFT_RESET__SCL2_SOFT_RESET__SHIFT 0x3
+#define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET_MASK 0x10
+#define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET__SHIFT 0x4
+#define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET_MASK 0x1
+#define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET__SHIFT 0x0
+#define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET_MASK 0x2
+#define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET__SHIFT 0x1
+#define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET_MASK 0x4
+#define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET__SHIFT 0x2
+#define DCFE3_SOFT_RESET__SCL3_SOFT_RESET_MASK 0x8
+#define DCFE3_SOFT_RESET__SCL3_SOFT_RESET__SHIFT 0x3
+#define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET_MASK 0x10
+#define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET__SHIFT 0x4
+#define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET_MASK 0x1
+#define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET__SHIFT 0x0
+#define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET_MASK 0x2
+#define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET__SHIFT 0x1
+#define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET_MASK 0x4
+#define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET__SHIFT 0x2
+#define DCFE4_SOFT_RESET__SCL4_SOFT_RESET_MASK 0x8
+#define DCFE4_SOFT_RESET__SCL4_SOFT_RESET__SHIFT 0x3
+#define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET_MASK 0x10
+#define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET__SHIFT 0x4
+#define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET_MASK 0x1
+#define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET__SHIFT 0x0
+#define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET_MASK 0x2
+#define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET__SHIFT 0x1
+#define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET_MASK 0x4
+#define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET__SHIFT 0x2
+#define DCFE5_SOFT_RESET__SCL5_SOFT_RESET_MASK 0x8
+#define DCFE5_SOFT_RESET__SCL5_SOFT_RESET__SHIFT 0x3
+#define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET_MASK 0x10
+#define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET__SHIFT 0x4
+#define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x1
+#define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0
+#define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x2
+#define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x1
+#define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x4
+#define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x2
+#define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x8
+#define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x3
+#define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x10
+#define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x4
+#define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x20
+#define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x5
+#define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x40
+#define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x6
+#define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x80
+#define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x7
+#define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x100
+#define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x8
+#define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x200
+#define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x9
+#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x1000
+#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0xc
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x1
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x10
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x100
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x1000
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x2000
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd
+#define DCCG_SOFT_RESET__CASCADED_AMCLK0_SOFT_RESET_MASK 0x4000
+#define DCCG_SOFT_RESET__CASCADED_AMCLK0_SOFT_RESET__SHIFT 0xe
+#define DCCG_SOFT_RESET__CASCADED_AMCLK1_SOFT_RESET_MASK 0x8000
+#define DCCG_SOFT_RESET__CASCADED_AMCLK1_SOFT_RESET__SHIFT 0xf
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x1
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x10
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x700
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x1
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x10
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x700
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x1
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x10
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x700
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x1
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x10
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x700
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x1
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x10
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x700
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x1
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x10
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x700
+#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x8
+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE_MASK 0x1
+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE__SHIFT 0x0
+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN_MASK 0x10
+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN__SHIFT 0x4
+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC_MASK 0x700
+#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC__SHIFT 0x8
+#define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x1
+#define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x0
+#define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x2
+#define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x1
+#define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x4
+#define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x2
+#define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x8
+#define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x3
+#define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x10
+#define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x4
+#define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x20
+#define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0x5
+#define UNIPHY_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x40
+#define UNIPHY_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0x6
+#define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x1
+#define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x0
+#define DCO_SOFT_RESET__DACB_SOFT_RESET_MASK 0x2
+#define DCO_SOFT_RESET__DACB_SOFT_RESET__SHIFT 0x1
+#define DCO_SOFT_RESET__SOFT_RESET_DVO_MASK 0x4
+#define DCO_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2
+#define DCO_SOFT_RESET__DVO_ENABLE_RST_MASK 0x8
+#define DCO_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3
+#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK 0x10
+#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT 0x4
+#define DCO_SOFT_RESET__I2S1_SOFT_RESET_MASK 0x20
+#define DCO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT 0x5
+#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK 0x40
+#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT 0x6
+#define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x10000
+#define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x10
+#define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x20000
+#define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x11
+#define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x40000
+#define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x12
+#define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x80000
+#define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x13
+#define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x100000
+#define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x14
+#define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x200000
+#define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x15
+#define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x1000000
+#define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x18
+#define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x2000000
+#define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x19
+#define DCO_SOFT_RESET__TVOUT_SOFT_RESET_MASK 0x4000000
+#define DCO_SOFT_RESET__TVOUT_SOFT_RESET__SHIFT 0x1a
+#define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x8000000
+#define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x1b
+#define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE_MASK 0x10000000
+#define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE__SHIFT 0x1c
+#define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET_MASK 0x20000000
+#define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET__SHIFT 0x1d
+#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK 0x7
+#define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT 0x0
+#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK 0x1f00
+#define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT 0x8
+#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK 0x10000
+#define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT 0x10
+#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK 0x20000
+#define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT 0x11
+#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK 0x40000
+#define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT 0x12
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK 0x7
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT 0x0
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK 0x1f00
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT 0x8
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK 0x10000
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT 0x10
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK 0x20000
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT 0x11
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK 0x40000
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT 0x12
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK 0x100000
+#define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT 0x14
+#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL_MASK 0x3000000
+#define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL__SHIFT 0x18
+#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL_MASK 0x30000000
+#define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT 0x1c
+#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK 0x7
+#define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT 0x0
+#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK 0x1f00
+#define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT 0x8
+#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK 0x10000
+#define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT 0x10
+#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK 0x20000
+#define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT 0x11
+#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK 0x40000
+#define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT 0x12
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x7
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x30
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x3000
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x10000
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x100000
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x1000000
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xffffffff
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xffffffff
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xffffffff
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xffffffff
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0
+#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK 0xff
+#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL_MASK 0x1000
+#define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL__SHIFT 0xc
+#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT 0x0
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x1ff
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x1000
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x1ff0000
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000
+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c
+#define PLL_REF_DIV__PLL_REF_DIV_MASK 0x3ff
+#define PLL_REF_DIV__PLL_REF_DIV__SHIFT 0x0
+#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV_MASK 0xf000
+#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV__SHIFT 0xc
+#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_MASK 0xf
+#define PLL_FB_DIV__PLL_FB_DIV_FRACTION__SHIFT 0x0
+#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL_MASK 0x30
+#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4
+#define PLL_FB_DIV__PLL_FB_DIV_MASK 0xfff0000
+#define PLL_FB_DIV__PLL_FB_DIV__SHIFT 0x10
+#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK 0x7f
+#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK__SHIFT 0x0
+#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK_MASK 0x80
+#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x7
+#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK_MASK 0x7f00
+#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK__SHIFT 0x8
+#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK_MASK 0x8000
+#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK__SHIFT 0xf
+#define PLL_POST_DIV__PLL_POST_DIV_IDCLK_MASK 0x7f0000
+#define PLL_POST_DIV__PLL_POST_DIV_IDCLK__SHIFT 0x10
+#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC_MASK 0xffff
+#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC__SHIFT 0x0
+#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV_MASK 0xff
+#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x0
+#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP_MASK 0xf00
+#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT 0x8
+#define PLL_SS_CNTL__PLL_SS_EN_MASK 0x1000
+#define PLL_SS_CNTL__PLL_SS_EN__SHIFT 0xc
+#define PLL_SS_CNTL__PLL_SS_MODE_MASK 0x2000
+#define PLL_SS_CNTL__PLL_SS_MODE__SHIFT 0xd
+#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC_MASK 0xffff0000
+#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC__SHIFT 0x10
+#define PLL_DS_CNTL__PLL_DS_FRAC_MASK 0xffff
+#define PLL_DS_CNTL__PLL_DS_FRAC__SHIFT 0x0
+#define PLL_DS_CNTL__PLL_DS_ORDER_MASK 0x30000
+#define PLL_DS_CNTL__PLL_DS_ORDER__SHIFT 0x10
+#define PLL_DS_CNTL__PLL_DS_MODE_MASK 0x40000
+#define PLL_DS_CNTL__PLL_DS_MODE__SHIFT 0x12
+#define PLL_DS_CNTL__PLL_DS_PRBS_EN_MASK 0x80000
+#define PLL_DS_CNTL__PLL_DS_PRBS_EN__SHIFT 0x13
+#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN_MASK 0x1
+#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN__SHIFT 0x0
+#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN_MASK 0x2
+#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN__SHIFT 0x1
+#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN_MASK 0x4
+#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN__SHIFT 0x2
+#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN_MASK 0x8
+#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN__SHIFT 0x3
+#define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN_MASK 0x10
+#define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN__SHIFT 0x4
+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET_MASK 0x100
+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET__SHIFT 0x8
+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT_MASK 0x1000
+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT__SHIFT 0xc
+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_MASK 0xf0000
+#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV__SHIFT 0x10
+#define PLL_IDCLK_CNTL__PLL_CUR_LTDP_MASK 0x300000
+#define PLL_IDCLK_CNTL__PLL_CUR_LTDP__SHIFT 0x14
+#define PLL_IDCLK_CNTL__PLL_CUR_PREDRV_MASK 0xc00000
+#define PLL_IDCLK_CNTL__PLL_CUR_PREDRV__SHIFT 0x16
+#define PLL_IDCLK_CNTL__PLL_CUR_TMDP_MASK 0x3000000
+#define PLL_IDCLK_CNTL__PLL_CUR_TMDP__SHIFT 0x18
+#define PLL_CNTL__PLL_RESET_MASK 0x1
+#define PLL_CNTL__PLL_RESET__SHIFT 0x0
+#define PLL_CNTL__PLL_POWER_DOWN_MASK 0x2
+#define PLL_CNTL__PLL_POWER_DOWN__SHIFT 0x1
+#define PLL_CNTL__PLL_BYPASS_CAL_MASK 0x4
+#define PLL_CNTL__PLL_BYPASS_CAL__SHIFT 0x2
+#define PLL_CNTL__PLL_POST_DIV_SRC_MASK 0x8
+#define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x3
+#define PLL_CNTL__PLL_VCOREF_MASK 0x30
+#define PLL_CNTL__PLL_VCOREF__SHIFT 0x4
+#define PLL_CNTL__PLL_PCIE_REFCLK_SEL_MASK 0x40
+#define PLL_CNTL__PLL_PCIE_REFCLK_SEL__SHIFT 0x6
+#define PLL_CNTL__PLL_ANTIGLITCH_RESETB_MASK 0x80
+#define PLL_CNTL__PLL_ANTIGLITCH_RESETB__SHIFT 0x7
+#define PLL_CNTL__PLL_CALREF_MASK 0x300
+#define PLL_CNTL__PLL_CALREF__SHIFT 0x8
+#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV_MASK 0x400
+#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV__SHIFT 0xa
+#define PLL_CNTL__PLL_REFCLK_SEL_MASK 0x1800
+#define PLL_CNTL__PLL_REFCLK_SEL__SHIFT 0xb
+#define PLL_CNTL__PLL_ANTI_GLITCH_RESET_MASK 0x2000
+#define PLL_CNTL__PLL_ANTI_GLITCH_RESET__SHIFT 0xd
+#define PLL_CNTL__PLL_XOCLK_DRV_R_EN_MASK 0x4000
+#define PLL_CNTL__PLL_XOCLK_DRV_R_EN__SHIFT 0xe
+#define PLL_CNTL__PLL_REF_DIV_SRC_MASK 0x70000
+#define PLL_CNTL__PLL_REF_DIV_SRC__SHIFT 0x10
+#define PLL_CNTL__PLL_LOCK_FREQ_SEL_MASK 0x80000
+#define PLL_CNTL__PLL_LOCK_FREQ_SEL__SHIFT 0x13
+#define PLL_CNTL__PLL_CALIB_DONE_MASK 0x100000
+#define PLL_CNTL__PLL_CALIB_DONE__SHIFT 0x14
+#define PLL_CNTL__PLL_LOCKED_MASK 0x200000
+#define PLL_CNTL__PLL_LOCKED__SHIFT 0x15
+#define PLL_CNTL__PLL_TIMING_MODE_STATUS_MASK 0x3000000
+#define PLL_CNTL__PLL_TIMING_MODE_STATUS__SHIFT 0x18
+#define PLL_CNTL__PLL_DIG_SPARE_MASK 0xfc000000
+#define PLL_CNTL__PLL_DIG_SPARE__SHIFT 0x1a
+#define PLL_ANALOG__PLL_CAL_MODE_MASK 0x1f
+#define PLL_ANALOG__PLL_CAL_MODE__SHIFT 0x0
+#define PLL_ANALOG__PLL_PFD_PULSE_SEL_MASK 0x60
+#define PLL_ANALOG__PLL_PFD_PULSE_SEL__SHIFT 0x5
+#define PLL_ANALOG__PLL_CP_MASK 0xf00
+#define PLL_ANALOG__PLL_CP__SHIFT 0x8
+#define PLL_ANALOG__PLL_LF_MODE_MASK 0x1ff000
+#define PLL_ANALOG__PLL_LF_MODE__SHIFT 0xc
+#define PLL_ANALOG__PLL_VREG_FB_TRIM_MASK 0xe00000
+#define PLL_ANALOG__PLL_VREG_FB_TRIM__SHIFT 0x15
+#define PLL_ANALOG__PLL_IBIAS_MASK 0xff000000
+#define PLL_ANALOG__PLL_IBIAS__SHIFT 0x18
+#define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN_MASK 0x1
+#define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN__SHIFT 0x0
+#define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL_MASK 0x1e
+#define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL__SHIFT 0x1
+#define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL_MASK 0x1e0
+#define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL__SHIFT 0x5
+#define PLL_VREG_CNTL__PLL_VREG_CNTL_MASK 0xfffff
+#define PLL_VREG_CNTL__PLL_VREG_CNTL__SHIFT 0x0
+#define PLL_VREG_CNTL__PLL_BG_VREG_BIAS_MASK 0x300000
+#define PLL_VREG_CNTL__PLL_BG_VREG_BIAS__SHIFT 0x14
+#define PLL_VREG_CNTL__PLL_VREF_SEL_MASK 0x4000000
+#define PLL_VREG_CNTL__PLL_VREF_SEL__SHIFT 0x1a
+#define PLL_VREG_CNTL__PLL_VREG_BIAS_MASK 0xf0000000
+#define PLL_VREG_CNTL__PLL_VREG_BIAS__SHIFT 0x1c
+#define PLL_XOR_LOCK__PLL_XOR_LOCK_MASK 0x1
+#define PLL_XOR_LOCK__PLL_XOR_LOCK__SHIFT 0x0
+#define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK_MASK 0x2
+#define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK__SHIFT 0x1
+#define PLL_XOR_LOCK__PLL_SPARE_MASK 0x3f00
+#define PLL_XOR_LOCK__PLL_SPARE__SHIFT 0x8
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE_MASK 0x1
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE__SHIFT 0x0
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT_MASK 0x2
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT__SHIFT 0x1
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS_MASK 0x4
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS__SHIFT 0x2
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR_MASK 0x8
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR__SHIFT 0x3
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT_MASK 0x70
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT__SHIFT 0x4
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST_MASK 0x80
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST__SHIFT 0x7
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK_MASK 0x100
+#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK__SHIFT 0x8
+#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE_MASK 0x1
+#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE__SHIFT 0x0
+#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL_MASK 0xf0
+#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL__SHIFT 0x4
+#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL_MASK 0x1f00
+#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL__SHIFT 0x8
+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL_MASK 0xff0000
+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL__SHIFT 0x10
+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK_MASK 0x7000000
+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK__SHIFT 0x18
+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN_MASK 0x8000000
+#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN__SHIFT 0x1b
+#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK_MASK 0x1
+#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK__SHIFT 0x0
+#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING_MASK 0x1
+#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING__SHIFT 0x0
+#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT_MASK 0x100
+#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT__SHIFT 0x8
+#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE_MASK 0x10000
+#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE__SHIFT 0x10
+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE_MASK 0x1ff
+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE__SHIFT 0x0
+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS_MASK 0x10000
+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS__SHIFT 0x10
+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE_MASK 0x60000
+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE__SHIFT 0x11
+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING_MASK 0x100000
+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING__SHIFT 0x14
+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ_MASK 0x200000
+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ__SHIFT 0x15
+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK_MASK 0x400000
+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK__SHIFT 0x16
+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY_MASK 0xff000000
+#define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY__SHIFT 0x18
+#define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE_MASK 0x1ff
+#define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE__SHIFT 0x0
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x7f
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x7f00
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x18000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x20000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x40000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x80000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x100000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x14
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x200000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x15
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x400000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x16
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7f000000
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x18
+#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK 0xffffffff
+#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT 0x0
+#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK 0xffffffff
+#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT 0x0
+#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK 0xffffffff
+#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT 0x0
+#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK 0xffffffff
+#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT 0x0
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK 0xf
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT 0x0
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK 0x1f0
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT 0x4
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK 0x1000
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT 0xc
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK 0xf0000
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT 0x10
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK 0x1f00000
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT 0x14
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK 0x10000000
+#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT 0x1c
+#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK 0x1f
+#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT 0x0
+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN_MASK 0x20
+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN__SHIFT 0x5
+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL_MASK 0x40
+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL__SHIFT 0x6
+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN_MASK 0x80
+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN__SHIFT 0x7
+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_MASK 0xfff00
+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA__SHIFT 0x8
+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL_MASK 0x300000
+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL__SHIFT 0x14
+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL_MASK 0x400000
+#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL__SHIFT 0x16
+#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK 0xffffffff
+#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT 0x0
+#define DMIF_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define DMIF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define DMIF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define DMIF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x3
+#define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x0
+#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x4
+#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x2
+#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x10
+#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x4
+#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x700
+#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x8
+#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0xf000
+#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0xc
+#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x3f0000
+#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x10
+#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1f000000
+#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x18
+#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000
+#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x1d
+#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0x3f
+#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x0
+#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0x3f00
+#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x10000
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x10
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x20000
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x11
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0x700000
+#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x14
+#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0x7000000
+#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x18
+#define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000
+#define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x1c
+#define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK 0xffffffff
+#define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT 0x0
+#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0xffff
+#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x0
+#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xffff0000
+#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x10
+#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
+#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
+#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
+#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
+#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
+#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff
+#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0
+#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK 0xff
+#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT 0x0
+#define DMIF_DEBUG02_CORE0__DB_DATA_MASK 0xffff
+#define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT 0x0
+#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK 0x10000
+#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT 0x10
+#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK 0xffe0000
+#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT 0x11
+#define DMIF_DEBUG02_CORE1__DB_DATA_MASK 0xffff
+#define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT 0x0
+#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK 0x10000
+#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT 0x10
+#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK 0xffe0000
+#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT 0x11
+#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000
+#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x1c
+#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x1
+#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x0
+#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x2
+#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x1
+#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x4
+#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x2
+#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x8
+#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x3
+#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x10
+#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x4
+#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x20
+#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x5
+#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x100
+#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x8
+#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x200
+#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x9
+#define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
+#define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
+#define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
+#define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
+#define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
+#define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff
+#define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x1
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x0
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x18
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x3
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0xe0
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x5
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x700
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x8
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x800
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0xb
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x7000
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0xc
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0xfff0000
+#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x10
+#define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK 0x3
+#define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT 0x0
+#define MCIF_CONTROL__MCIF_SCANIN_DISABLE_MASK 0x8
+#define MCIF_CONTROL__MCIF_SCANIN_DISABLE__SHIFT 0x3
+#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x10
+#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x4
+#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x100
+#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x8
+#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK 0xf000
+#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT 0xc
+#define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK 0xff0000
+#define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x10
+#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK 0x3f000000
+#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT 0x18
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0xff
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0
+#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK 0xff00
+#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT 0x8
+#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK 0xff
+#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT 0x0
+#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK 0xffffffff
+#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT 0x0
+#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff
+#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0
+#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK 0xffffffff
+#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT 0x0
+#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK 0xffffffff
+#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT 0x0
+#define MCIF_VMID__MCIF_WR_VMID_MASK 0xf
+#define MCIF_VMID__MCIF_WR_VMID__SHIFT 0x0
+#define MCIF_VMID__VIP_WR_VMID_MASK 0xf0
+#define MCIF_VMID__VIP_WR_VMID__SHIFT 0x4
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK 0x1
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT 0x0
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK 0x30
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT 0x4
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK 0xff00
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT 0x8
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK 0x70000
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT 0x10
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK 0x180000
+#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT 0x13
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x7e
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x1
+#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK 0x1
+#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT 0x0
+#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK 0x10
+#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT 0x4
+#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK 0x100
+#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT 0x8
+#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK 0x1000
+#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT 0xc
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK 0x10000
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT 0x10
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK 0x100000
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT 0x14
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK 0x1000000
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT 0x18
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK 0x10000000
+#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT 0x1c
+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY_MASK 0xf
+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY__SHIFT 0x0
+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS_MASK 0x20
+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS__SHIFT 0x5
+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY_MASK 0x3c0
+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY__SHIFT 0x6
+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS_MASK 0x800
+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS__SHIFT 0xb
+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY_MASK 0xf000
+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY__SHIFT 0xc
+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS_MASK 0x20000
+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS__SHIFT 0x11
+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY_MASK 0x3c0000
+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY__SHIFT 0x12
+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS_MASK 0x800000
+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS__SHIFT 0x17
+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY_MASK 0xf000000
+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY__SHIFT 0x18
+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS_MASK 0x20000000
+#define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS__SHIFT 0x1d
+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_DELAY_MASK 0xf
+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_DELAY__SHIFT 0x0
+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_TIMEOUT_DIS_MASK 0x20
+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_TIMEOUT_DIS__SHIFT 0x5
+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_DELAY_MASK 0x3c0
+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_DELAY__SHIFT 0x6
+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_TIMEOUT_DIS_MASK 0x800
+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_TIMEOUT_DIS__SHIFT 0xb
+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_DELAY_MASK 0xf000
+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_DELAY__SHIFT 0xc
+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_TIMEOUT_DIS_MASK 0x20000
+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_TIMEOUT_DIS__SHIFT 0x11
+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY_MASK 0x3c0000
+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY__SHIFT 0x12
+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS_MASK 0x800000
+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS__SHIFT 0x17
+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY_MASK 0xf000000
+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY__SHIFT 0x18
+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS_MASK 0x20000000
+#define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS__SHIFT 0x1d
+#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_DELAY_MASK 0xf
+#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_DELAY__SHIFT 0x0
+#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_TIMEOUT_DIS_MASK 0x20
+#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_TIMEOUT_DIS__SHIFT 0x5
+#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_TIMEOUT_DELAY_MASK 0x1ffff000
+#define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_TIMEOUT_DELAY__SHIFT 0xc
+#define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE_MASK 0x3
+#define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE__SHIFT 0x0
+#define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE_MASK 0xc
+#define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE__SHIFT 0x2
+#define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE_MASK 0x30
+#define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE__SHIFT 0x4
+#define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE_MASK 0xc0
+#define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE__SHIFT 0x6
+#define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE_MASK 0x300
+#define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE__SHIFT 0x8
+#define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE_MASK 0xc00
+#define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE__SHIFT 0xa
+#define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE_MASK 0x3000
+#define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE__SHIFT 0xc
+#define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE_MASK 0xc000
+#define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE__SHIFT 0xe
+#define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE_MASK 0x30000
+#define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE__SHIFT 0x10
+#define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE_MASK 0xc0000
+#define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE__SHIFT 0x12
+#define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE_MASK 0x300000
+#define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE__SHIFT 0x14
+#define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE_MASK 0xc00000
+#define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE__SHIFT 0x16
+#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE_MASK 0x3000000
+#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE__SHIFT 0x18
+#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE_MASK 0xc000000
+#define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE__SHIFT 0x1a
+#define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE_MASK 0x30000000
+#define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE__SHIFT 0x1c
+#define DCI_MEM_PWR_STATE__MCIFWB_MEM_PWR_STATE_MASK 0xc0000000
+#define DCI_MEM_PWR_STATE__MCIFWB_MEM_PWR_STATE__SHIFT 0x1e
+#define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE_MASK 0x3
+#define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE__SHIFT 0x0
+#define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE_MASK 0xc
+#define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE__SHIFT 0x2
+#define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE_MASK 0x30
+#define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE__SHIFT 0x4
+#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x1f
+#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x0
+#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x20
+#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x5
+#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x40
+#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x6
+#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x80
+#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x7
+#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x100
+#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8
+#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x200
+#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x9
+#define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS_MASK 0x400
+#define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS__SHIFT 0xa
+#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x800
+#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0xb
+#define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS_MASK 0x1000
+#define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS__SHIFT 0xc
+#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x2000
+#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0xd
+#define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS_MASK 0x4000
+#define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS__SHIFT 0xe
+#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x8000
+#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0xf
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x10000
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x10
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x20000
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x11
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x40000
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x12
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x80000
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x13
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x100000
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x14
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x200000
+#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x15
+#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK 0x400000
+#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT 0x16
+#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK 0x800000
+#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x17
+#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x1000000
+#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x18
+#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xf8000000
+#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x1b
+#define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL_MASK 0x1
+#define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL__SHIFT 0x0
+#define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE_MASK 0x2
+#define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x1
+#define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS_MASK 0x4
+#define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS__SHIFT 0x2
+#define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS_MASK 0x8
+#define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS__SHIFT 0x3
+#define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE_MASK 0x10
+#define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x4
+#define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE_MASK 0x20
+#define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x5
+#define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS_MASK 0x100
+#define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS__SHIFT 0x8
+#define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS_MASK 0x200
+#define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS__SHIFT 0x9
+#define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS_MASK 0x400
+#define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS__SHIFT 0xa
+#define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS_MASK 0x800
+#define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS__SHIFT 0xb
+#define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS_MASK 0x1000
+#define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS__SHIFT 0xc
+#define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS_MASK 0x2000
+#define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS__SHIFT 0xd
+#define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS_MASK 0x4000
+#define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS__SHIFT 0xe
+#define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS_MASK 0x8000
+#define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS__SHIFT 0xf
+#define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS_MASK 0x10000
+#define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS__SHIFT 0x10
+#define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE_MASK 0x20000
+#define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x11
+#define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE_MASK 0x40000
+#define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x12
+#define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS_MASK 0x80000
+#define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS__SHIFT 0x13
+#define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS_MASK 0x100000
+#define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS__SHIFT 0x14
+#define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS_MASK 0x200000
+#define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS__SHIFT 0x15
+#define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS_MASK 0x400000
+#define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS__SHIFT 0x16
+#define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS_MASK 0x800000
+#define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS__SHIFT 0x17
+#define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS_MASK 0x1000000
+#define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS__SHIFT 0x18
+#define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS_MASK 0x2000000
+#define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS__SHIFT 0x19
+#define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS_MASK 0x4000000
+#define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS__SHIFT 0x1a
+#define DCCG_VPCLK_CNTL__MCIFWB_LIGHT_SLEEP_MODE_FORCE_MASK 0x8000000
+#define DCCG_VPCLK_CNTL__MCIFWB_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x1b
+#define DCCG_VPCLK_CNTL__MCIFWB_MEM_SHUTDOWN_MODE_FORCE_MASK 0x10000000
+#define DCCG_VPCLK_CNTL__MCIFWB_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x1c
+#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS_MASK 0x1
+#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x0
+#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS_MASK 0x2
+#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x1
+#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS_MASK 0x4
+#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x2
+#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS_MASK 0x8
+#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x3
+#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS_MASK 0x10
+#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x4
+#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS_MASK 0x20
+#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x5
+#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x40
+#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x6
+#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x80
+#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x7
+#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x100
+#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x8
+#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x200
+#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x9
+#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x400
+#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0xa
+#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x800
+#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0xb
+#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x3000
+#define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0xc
+#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0xc000
+#define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0xe
+#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x30000
+#define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x10
+#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0xc0000
+#define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0x12
+#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x300000
+#define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0x14
+#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0xc00000
+#define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x16
+#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE_MASK 0x3f
+#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE__SHIFT 0x0
+#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL_MASK 0x700
+#define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL__SHIFT 0x8
+#define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING_MASK 0x10000
+#define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING__SHIFT 0x10
+#define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP_MASK 0x100000
+#define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP__SHIFT 0x14
+#define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP_MASK 0x200000
+#define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP__SHIFT 0x15
+#define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP_MASK 0x400000
+#define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP__SHIFT 0x16
+#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK 0xff
+#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT 0x0
+#define DCI_DEBUG_CONFIG__DCI_DBG_SEL_MASK 0xf
+#define DCI_DEBUG_CONFIG__DCI_DBG_SEL__SHIFT 0x0
+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
+#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
+#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
+#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
+#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
+#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7
+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0
+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10
+#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4
+#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_ENABLE_MASK 0x1
+#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_ENABLE__SHIFT 0x0
+#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_INT_EN_MASK 0x10
+#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_INT_EN__SHIFT 0x4
+#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_INT_ACK_MASK 0x20
+#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_INT_ACK__SHIFT 0x5
+#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_SLICE_INT_EN_MASK 0x40
+#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6
+#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_LOCK_MASK 0xf00
+#define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_LOCK__SHIFT 0x8
+#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_SW_INT_STATUS_MASK 0x2
+#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_SW_INT_STATUS__SHIFT 0x1
+#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_CUR_BUF_MASK 0x70
+#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_CUR_BUF__SHIFT 0x4
+#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_BUFTAG_MASK 0xf00
+#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_BUFTAG__SHIFT 0x8
+#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_CUR_LINE_MASK 0x1fff000
+#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_CUR_LINE__SHIFT 0xc
+#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_NEXT_BUF_MASK 0x70000000
+#define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_NEXT_BUF__SHIFT 0x1c
+#define MCIF_BUF_PITCH__MCIF_BUF_LUMA_PITCH_MASK 0xffff
+#define MCIF_BUF_PITCH__MCIF_BUF_LUMA_PITCH__SHIFT 0x0
+#define MCIF_BUF_PITCH__MCIF_BUF_CHROMA_PITCH_MASK 0xffff0000
+#define MCIF_BUF_PITCH__MCIF_BUF_CHROMA_PITCH__SHIFT 0x10
+#define MCIF_BUF_1_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW_MASK 0xffffffff
+#define MCIF_BUF_1_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW__SHIFT 0x0
+#define MCIF_BUF_2_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW_MASK 0xffffffff
+#define MCIF_BUF_2_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW__SHIFT 0x0
+#define MCIF_BUF_3_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW_MASK 0xffffffff
+#define MCIF_BUF_3_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW__SHIFT 0x0
+#define MCIF_BUF_4_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW_MASK 0xffffffff
+#define MCIF_BUF_4_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW__SHIFT 0x0
+#define MCIF_BUF_1_ADDR_UP__MCIF_BUF_ADDR_Y_UP_MASK 0xff
+#define MCIF_BUF_1_ADDR_UP__MCIF_BUF_ADDR_Y_UP__SHIFT 0x0
+#define MCIF_BUF_1_ADDR_UP__MCIF_BUF_ADDR_C_UP_MASK 0xff0000
+#define MCIF_BUF_1_ADDR_UP__MCIF_BUF_ADDR_C_UP__SHIFT 0x10
+#define MCIF_BUF_2_ADDR_UP__MCIF_BUF_ADDR_Y_UP_MASK 0xff
+#define MCIF_BUF_2_ADDR_UP__MCIF_BUF_ADDR_Y_UP__SHIFT 0x0
+#define MCIF_BUF_2_ADDR_UP__MCIF_BUF_ADDR_C_UP_MASK 0xff0000
+#define MCIF_BUF_2_ADDR_UP__MCIF_BUF_ADDR_C_UP__SHIFT 0x10
+#define MCIF_BUF_3_ADDR_UP__MCIF_BUF_ADDR_Y_UP_MASK 0xff
+#define MCIF_BUF_3_ADDR_UP__MCIF_BUF_ADDR_Y_UP__SHIFT 0x0
+#define MCIF_BUF_3_ADDR_UP__MCIF_BUF_ADDR_C_UP_MASK 0xff0000
+#define MCIF_BUF_3_ADDR_UP__MCIF_BUF_ADDR_C_UP__SHIFT 0x10
+#define MCIF_BUF_4_ADDR_UP__MCIF_BUF_ADDR_Y_UP_MASK 0xff
+#define MCIF_BUF_4_ADDR_UP__MCIF_BUF_ADDR_Y_UP__SHIFT 0x0
+#define MCIF_BUF_4_ADDR_UP__MCIF_BUF_ADDR_C_UP_MASK 0xff0000
+#define MCIF_BUF_4_ADDR_UP__MCIF_BUF_ADDR_C_UP__SHIFT 0x10
+#define MCIF_BUF_1_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW_MASK 0xffffffff
+#define MCIF_BUF_1_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW__SHIFT 0x0
+#define MCIF_BUF_2_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW_MASK 0xffffffff
+#define MCIF_BUF_2_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW__SHIFT 0x0
+#define MCIF_BUF_3_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW_MASK 0xffffffff
+#define MCIF_BUF_3_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW__SHIFT 0x0
+#define MCIF_BUF_4_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW_MASK 0xffffffff
+#define MCIF_BUF_4_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW__SHIFT 0x0
+#define MCIF_BUF_1_STATUS__MCIF_BUF_ACTIVE_MASK 0x1
+#define MCIF_BUF_1_STATUS__MCIF_BUF_ACTIVE__SHIFT 0x0
+#define MCIF_BUF_1_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2
+#define MCIF_BUF_1_STATUS__MCIF_BUF_SW_LOCKED__SHIFT 0x1
+#define MCIF_BUF_1_STATUS__MCIF_BUF_OVERFLOW_MASK 0x8
+#define MCIF_BUF_1_STATUS__MCIF_BUF_OVERFLOW__SHIFT 0x3
+#define MCIF_BUF_1_STATUS__MCIF_BUF_DISABLE_MASK 0x10
+#define MCIF_BUF_1_STATUS__MCIF_BUF_DISABLE__SHIFT 0x4
+#define MCIF_BUF_1_STATUS__MCIF_BUF_NEW_CONTENT_MASK 0x20
+#define MCIF_BUF_1_STATUS__MCIF_BUF_NEW_CONTENT__SHIFT 0x5
+#define MCIF_BUF_1_STATUS__MCIF_BUF_STEREOSYNC_MASK 0x40
+#define MCIF_BUF_1_STATUS__MCIF_BUF_STEREOSYNC__SHIFT 0x6
+#define MCIF_BUF_1_STATUS__MCIF_BUF_MODE_MASK 0x80
+#define MCIF_BUF_1_STATUS__MCIF_BUF_MODE__SHIFT 0x7
+#define MCIF_BUF_1_STATUS__MCIF_BUF_BUFTAG_MASK 0xf00
+#define MCIF_BUF_1_STATUS__MCIF_BUF_BUFTAG__SHIFT 0x8
+#define MCIF_BUF_1_STATUS__MCIF_BUF_NXT_BUF_MASK 0x7000
+#define MCIF_BUF_1_STATUS__MCIF_BUF_NXT_BUF__SHIFT 0xc
+#define MCIF_BUF_1_STATUS__MCIF_BUF_CUR_LINE_MASK 0x1fff0000
+#define MCIF_BUF_1_STATUS__MCIF_BUF_CUR_LINE__SHIFT 0x10
+#define MCIF_BUF_2_STATUS__MCIF_BUF_ACTIVE_MASK 0x1
+#define MCIF_BUF_2_STATUS__MCIF_BUF_ACTIVE__SHIFT 0x0
+#define MCIF_BUF_2_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2
+#define MCIF_BUF_2_STATUS__MCIF_BUF_SW_LOCKED__SHIFT 0x1
+#define MCIF_BUF_2_STATUS__MCIF_BUF_OVERFLOW_MASK 0x8
+#define MCIF_BUF_2_STATUS__MCIF_BUF_OVERFLOW__SHIFT 0x3
+#define MCIF_BUF_2_STATUS__MCIF_BUF_DISABLE_MASK 0x10
+#define MCIF_BUF_2_STATUS__MCIF_BUF_DISABLE__SHIFT 0x4
+#define MCIF_BUF_2_STATUS__MCIF_BUF_NEW_CONTENT_MASK 0x20
+#define MCIF_BUF_2_STATUS__MCIF_BUF_NEW_CONTENT__SHIFT 0x5
+#define MCIF_BUF_2_STATUS__MCIF_BUF_STEREOSYNC_MASK 0x40
+#define MCIF_BUF_2_STATUS__MCIF_BUF_STEREOSYNC__SHIFT 0x6
+#define MCIF_BUF_2_STATUS__MCIF_BUF_MODE_MASK 0x80
+#define MCIF_BUF_2_STATUS__MCIF_BUF_MODE__SHIFT 0x7
+#define MCIF_BUF_2_STATUS__MCIF_BUF_BUFTAG_MASK 0xf00
+#define MCIF_BUF_2_STATUS__MCIF_BUF_BUFTAG__SHIFT 0x8
+#define MCIF_BUF_2_STATUS__MCIF_BUF_NXT_BUF_MASK 0x7000
+#define MCIF_BUF_2_STATUS__MCIF_BUF_NXT_BUF__SHIFT 0xc
+#define MCIF_BUF_2_STATUS__MCIF_BUF_CUR_LINE_MASK 0x1fff0000
+#define MCIF_BUF_2_STATUS__MCIF_BUF_CUR_LINE__SHIFT 0x10
+#define MCIF_BUF_3_STATUS__MCIF_BUF_ACTIVE_MASK 0x1
+#define MCIF_BUF_3_STATUS__MCIF_BUF_ACTIVE__SHIFT 0x0
+#define MCIF_BUF_3_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2
+#define MCIF_BUF_3_STATUS__MCIF_BUF_SW_LOCKED__SHIFT 0x1
+#define MCIF_BUF_3_STATUS__MCIF_BUF_OVERFLOW_MASK 0x8
+#define MCIF_BUF_3_STATUS__MCIF_BUF_OVERFLOW__SHIFT 0x3
+#define MCIF_BUF_3_STATUS__MCIF_BUF_DISABLE_MASK 0x10
+#define MCIF_BUF_3_STATUS__MCIF_BUF_DISABLE__SHIFT 0x4
+#define MCIF_BUF_3_STATUS__MCIF_BUF_NEW_CONTENT_MASK 0x20
+#define MCIF_BUF_3_STATUS__MCIF_BUF_NEW_CONTENT__SHIFT 0x5
+#define MCIF_BUF_3_STATUS__MCIF_BUF_STEREOSYNC_MASK 0x40
+#define MCIF_BUF_3_STATUS__MCIF_BUF_STEREOSYNC__SHIFT 0x6
+#define MCIF_BUF_3_STATUS__MCIF_BUF_MODE_MASK 0x80
+#define MCIF_BUF_3_STATUS__MCIF_BUF_MODE__SHIFT 0x7
+#define MCIF_BUF_3_STATUS__MCIF_BUF_BUFTAG_MASK 0xf00
+#define MCIF_BUF_3_STATUS__MCIF_BUF_BUFTAG__SHIFT 0x8
+#define MCIF_BUF_3_STATUS__MCIF_BUF_NXT_BUF_MASK 0x7000
+#define MCIF_BUF_3_STATUS__MCIF_BUF_NXT_BUF__SHIFT 0xc
+#define MCIF_BUF_3_STATUS__MCIF_BUF_CUR_LINE_MASK 0x1fff0000
+#define MCIF_BUF_3_STATUS__MCIF_BUF_CUR_LINE__SHIFT 0x10
+#define MCIF_BUF_4_STATUS__MCIF_BUF_ACTIVE_MASK 0x1
+#define MCIF_BUF_4_STATUS__MCIF_BUF_ACTIVE__SHIFT 0x0
+#define MCIF_BUF_4_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2
+#define MCIF_BUF_4_STATUS__MCIF_BUF_SW_LOCKED__SHIFT 0x1
+#define MCIF_BUF_4_STATUS__MCIF_BUF_OVERFLOW_MASK 0x8
+#define MCIF_BUF_4_STATUS__MCIF_BUF_OVERFLOW__SHIFT 0x3
+#define MCIF_BUF_4_STATUS__MCIF_BUF_DISABLE_MASK 0x10
+#define MCIF_BUF_4_STATUS__MCIF_BUF_DISABLE__SHIFT 0x4
+#define MCIF_BUF_4_STATUS__MCIF_BUF_NEW_CONTENT_MASK 0x20
+#define MCIF_BUF_4_STATUS__MCIF_BUF_NEW_CONTENT__SHIFT 0x5
+#define MCIF_BUF_4_STATUS__MCIF_BUF_STEREOSYNC_MASK 0x40
+#define MCIF_BUF_4_STATUS__MCIF_BUF_STEREOSYNC__SHIFT 0x6
+#define MCIF_BUF_4_STATUS__MCIF_BUF_MODE_MASK 0x80
+#define MCIF_BUF_4_STATUS__MCIF_BUF_MODE__SHIFT 0x7
+#define MCIF_BUF_4_STATUS__MCIF_BUF_BUFTAG_MASK 0xf00
+#define MCIF_BUF_4_STATUS__MCIF_BUF_BUFTAG__SHIFT 0x8
+#define MCIF_BUF_4_STATUS__MCIF_BUF_NXT_BUF_MASK 0x7000
+#define MCIF_BUF_4_STATUS__MCIF_BUF_NXT_BUF__SHIFT 0xc
+#define MCIF_BUF_4_STATUS__MCIF_BUF_CUR_LINE_MASK 0x1fff0000
+#define MCIF_BUF_4_STATUS__MCIF_BUF_CUR_LINE__SHIFT 0x10
+#define MCIF_SI_ARBITRATION_CONTROL__MCIF_SI_CLIENT0_ARBITRATION_SLICE_MASK 0x3
+#define MCIF_SI_ARBITRATION_CONTROL__MCIF_SI_CLIENT0_ARBITRATION_SLICE__SHIFT 0x0
+#define MCIF_SI_ARBITRATION_CONTROL__MCIF_SI_CLIENT1_ARBITRATION_SLICE_MASK 0x30
+#define MCIF_SI_ARBITRATION_CONTROL__MCIF_SI_CLIENT1_ARBITRATION_SLICE__SHIFT 0x4
+#define MCIF_URGENCY_WATERMARK__MCIF_SI_CLIENT0_URGENCY_WATERMARK_MASK 0xffff
+#define MCIF_URGENCY_WATERMARK__MCIF_SI_CLIENT0_URGENCY_WATERMARK__SHIFT 0x0
+#define MCIF_URGENCY_WATERMARK__MCIF_SI_CLIENT1_URGENCY_WATERMARK_MASK 0xffff0000
+#define MCIF_URGENCY_WATERMARK__MCIF_SI_CLIENT1_URGENCY_WATERMARK__SHIFT 0x10
+#define DC_GENERICA__GENERICA_EN_MASK 0x1
+#define DC_GENERICA__GENERICA_EN__SHIFT 0x0
+#define DC_GENERICA__GENERICA_SEL_MASK 0xf00
+#define DC_GENERICA__GENERICA_SEL__SHIFT 0x8
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x7000
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x70000
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x700000
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x7000000
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18
+#define DC_GENERICB__GENERICB_EN_MASK 0x1
+#define DC_GENERICB__GENERICB_EN__SHIFT 0x0
+#define DC_GENERICB__GENERICB_SEL_MASK 0xf00
+#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x7000
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x70000
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x700000
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x7000000
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18
+#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0xf
+#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x0
+#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x30
+#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x4
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x3
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x300
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8
+#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x1
+#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x0
+#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x300
+#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x8
+#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x10000
+#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x10
+#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN_MASK 0x20000
+#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN__SHIFT 0x11
+#define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE_MASK 0x3
+#define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE__SHIFT 0x0
+#define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE_MASK 0xc
+#define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE__SHIFT 0x2
+#define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE_MASK 0x30
+#define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE__SHIFT 0x4
+#define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE_MASK 0xc0
+#define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE__SHIFT 0x6
+#define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE_MASK 0x300
+#define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE__SHIFT 0x8
+#define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE_MASK 0xc00
+#define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE__SHIFT 0xa
+#define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE_MASK 0x3000
+#define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE__SHIFT 0xc
+#define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE_MASK 0xc000
+#define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE__SHIFT 0xe
+#define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE_MASK 0x30000
+#define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE__SHIFT 0x10
+#define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE_MASK 0xc0000
+#define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE__SHIFT 0x12
+#define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE_MASK 0x300000
+#define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE__SHIFT 0x14
+#define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE_MASK 0xc00000
+#define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE__SHIFT 0x16
+#define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE_MASK 0x3000000
+#define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE__SHIFT 0x18
+#define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE_MASK 0xc000000
+#define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE__SHIFT 0x1a
+#define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE_MASK 0x30000000
+#define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE__SHIFT 0x1c
+#define DCO_MEM_POWER_STATE_2__DPG_MEM_PWR_STATE_MASK 0x3
+#define DCO_MEM_POWER_STATE_2__DPG_MEM_PWR_STATE__SHIFT 0x0
+#define DCO_MEM_POWER_STATE_2__HDMI6_MEM_PWR_STATE_MASK 0xc
+#define DCO_MEM_POWER_STATE_2__HDMI6_MEM_PWR_STATE__SHIFT 0x2
+#define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS_MASK 0x1
+#define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS__SHIFT 0x0
+#define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE_MASK 0x2
+#define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x1
+#define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS_MASK 0x4
+#define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS__SHIFT 0x2
+#define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS_MASK 0x8
+#define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS__SHIFT 0x3
+#define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS_MASK 0x10
+#define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS__SHIFT 0x4
+#define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS_MASK 0x20
+#define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS__SHIFT 0x5
+#define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS_MASK 0x40
+#define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS__SHIFT 0x6
+#define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS_MASK 0x80
+#define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS__SHIFT 0x7
+#define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS_MASK 0x100
+#define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS__SHIFT 0x8
+#define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS_MASK 0x200
+#define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS__SHIFT 0x9
+#define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS_MASK 0x400
+#define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS__SHIFT 0xa
+#define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS_MASK 0x800
+#define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS__SHIFT 0xb
+#define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS_MASK 0x1000
+#define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS__SHIFT 0xc
+#define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS_MASK 0x2000
+#define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS__SHIFT 0xd
+#define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS_MASK 0x4000
+#define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS__SHIFT 0xe
+#define DCO_LIGHT_SLEEP_DIS__HDMI6_LIGHT_SLEEP_DIS_MASK 0x8000
+#define DCO_LIGHT_SLEEP_DIS__HDMI6_LIGHT_SLEEP_DIS__SHIFT 0xf
+#define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS_MASK 0x10000
+#define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS__SHIFT 0x10
+#define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS_MASK 0x20000
+#define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS__SHIFT 0x11
+#define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS_MASK 0x40000
+#define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS__SHIFT 0x12
+#define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS_MASK 0x80000
+#define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS__SHIFT 0x13
+#define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS_MASK 0x100000
+#define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS__SHIFT 0x14
+#define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS_MASK 0x200000
+#define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS__SHIFT 0x15
+#define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS_MASK 0x400000
+#define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS__SHIFT 0x16
+#define DCO_LIGHT_SLEEP_DIS__DPG_MEM_SHUTDOWN_DIS_MASK 0x800000
+#define DCO_LIGHT_SLEEP_DIS__DPG_MEM_SHUTDOWN_DIS__SHIFT 0x17
+#define DCO_LIGHT_SLEEP_DIS__DPG_LIGHT_SLEEP_DIS_MASK 0x1000000
+#define DCO_LIGHT_SLEEP_DIS__DPG_LIGHT_SLEEP_DIS__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x1
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x100
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x200
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x400
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0xf0000
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0xf00000
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0xf000000
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000
+#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x1e
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x1
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x100
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x200
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x400
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0xf0000
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0xf00000
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0xf000000
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000
+#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x1e
+#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xffffffff
+#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x0
+#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x1
+#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x0
+#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x100
+#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x8
+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x200
+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x9
+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x400
+#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0xa
+#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0xf0000
+#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x10
+#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0xf00000
+#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x14
+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0xf000000
+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x18
+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000
+#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c
+#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x1
+#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x0
+#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x100
+#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x8
+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x200
+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x9
+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x400
+#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0xa
+#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0xf0000
+#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x10
+#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0xf00000
+#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x14
+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0xf000000
+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x18
+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000
+#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c
+#define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE_MASK 0xf
+#define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE__SHIFT 0x0
+#define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET_MASK 0x20
+#define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET__SHIFT 0x5
+#define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS_MASK 0x300
+#define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS__SHIFT 0x8
+#define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE_MASK 0x7000
+#define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE__SHIFT 0xc
+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x7fff
+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x0
+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7fff0000
+#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x1
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x100
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x200
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x400
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0xf0000
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0xf00000
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0xf000000
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000
+#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x1e
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x1
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x100
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x200
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x400
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0xf0000
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0xf00000
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0xf000000
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000
+#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x1e
+#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0xf
+#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x0
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x20
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x5
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x300
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x8
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x7000
+#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0xc
+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x7fff
+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x0
+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7fff0000
+#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x1
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x100
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x200
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x400
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0xf0000
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0xf00000
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0xf000000
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000
+#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x1e
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x1
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x0
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x100
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x8
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x200
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x9
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x400
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0xa
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0xf0000
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x10
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0xf00000
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x14
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0xf000000
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x18
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x1c
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000
+#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x1e
+#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0xf
+#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x0
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x20
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x5
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x300
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x8
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x7000
+#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0xc
+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x7fff
+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x0
+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7fff0000
+#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x10
+#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK 0x400
+#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT 0xa
+#define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE_MASK 0x800
+#define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE__SHIFT 0xb
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x2000
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0xc000
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x10000
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10
+#define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x80000
+#define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x13
+#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x100000
+#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x14
+#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x200000
+#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x15
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x1
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x2
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x10
+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x100
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x200
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x400
+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x10000
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x20000
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x40000
+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x1000000
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x2000000
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x4000000
+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x1
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x2
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x4
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x8
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x10
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0xf00
+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8
+#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0xfff
+#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0
+#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000
+#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0xff
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0xff00
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0xff0000
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xff000000
+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0xff
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0xff00
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0xff0000
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x1000000
+#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18
+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0xffff
+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0
+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000
+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e
+#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000
+#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f
+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0xffff
+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0
+#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000
+#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x1c
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000
+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0xffff
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0xf0000
+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x1
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x100
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x10000
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0xe0000
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x1000000
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000
+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x3
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x0
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x30
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x4
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x300
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x30000
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x10
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x300000
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x14
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x3000000
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x3
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x0
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x30
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x4
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x300
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x30000
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x10
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x300000
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x14
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x3000000
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18
+#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x7
+#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x0
+#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x700
+#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x8
+#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x70000
+#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x10
+#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x7
+#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x0
+#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x700
+#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x8
+#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x70000
+#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x10
+#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x7
+#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x0
+#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x700
+#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x8
+#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x70000
+#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x10
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x7
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x70
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x700
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x7000
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x70000
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x700000
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x7
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x0
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x70
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x4
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x700
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x8
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x7000
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0xc
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x70000
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x10
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x700000
+#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x14
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xffffffff
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x3f
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x700
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x3800
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x1c000
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0xe0000
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x700000
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x3800000
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17
+#define DCO_CLK_CNTL__DCO_TEST_CLK_SEL_MASK 0x1f
+#define DCO_CLK_CNTL__DCO_TEST_CLK_SEL__SHIFT 0x0
+#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x20
+#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x5
+#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x40
+#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x6
+#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x80
+#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x7
+#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x100
+#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x8
+#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x200
+#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x9
+#define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS_MASK 0x1000
+#define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS__SHIFT 0xc
+#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x10000
+#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x10
+#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x20000
+#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x11
+#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x40000
+#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x12
+#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x80000
+#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x13
+#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x100000
+#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x14
+#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x200000
+#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x15
+#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x1000000
+#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18
+#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x2000000
+#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19
+#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x4000000
+#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a
+#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x8000000
+#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b
+#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000
+#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c
+#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000
+#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d
+#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000
+#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e
+#define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS_MASK 0x20
+#define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS__SHIFT 0x5
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS_MASK 0x40
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS__SHIFT 0x6
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS_MASK 0x80
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS__SHIFT 0x7
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS_MASK 0x100
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS__SHIFT 0x8
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS_MASK 0x200
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS__SHIFT 0x9
+#define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS_MASK 0x1000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS__SHIFT 0xc
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS_MASK 0x10000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS__SHIFT 0x10
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS_MASK 0x20000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS__SHIFT 0x11
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS_MASK 0x40000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS__SHIFT 0x12
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS_MASK 0x80000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS__SHIFT 0x13
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS_MASK 0x100000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS__SHIFT 0x14
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS_MASK 0x200000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS__SHIFT 0x15
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS_MASK 0x1000000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS__SHIFT 0x18
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS_MASK 0x2000000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS__SHIFT 0x19
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS_MASK 0x4000000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS__SHIFT 0x1a
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS_MASK 0x8000000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS__SHIFT 0x1b
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS_MASK 0x10000000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS__SHIFT 0x1c
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS_MASK 0x20000000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS__SHIFT 0x1d
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGG_RAMP_DIS_MASK 0x40000000
+#define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGG_RAMP_DIS__SHIFT 0x1e
+#define DCIO_DEBUG__DCIO_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x0
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX_MASK 0x7
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX__SHIFT 0x0
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX_MASK 0x70
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX__SHIFT 0x4
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX_MASK 0x700
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX__SHIFT 0x8
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX_MASK 0x7000
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX__SHIFT 0xc
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX_MASK 0x70000
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX__SHIFT 0x10
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX_MASK 0x700000
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX__SHIFT 0x14
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK_MASK 0x7000000
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT 0x18
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK_MASK 0x70000000
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK__SHIFT 0x1c
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL_MASK 0x80000000
+#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL__SHIFT 0x1f
+#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0xff
+#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x0
+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG_MASK 0x3
+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG__SHIFT 0x0
+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG_MASK 0xc
+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x2
+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG_MASK 0x30
+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG__SHIFT 0x4
+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_MASK 0xc0
+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0__SHIFT 0x6
+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0_MASK 0x300
+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0__SHIFT 0x8
+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_MASK 0xc00
+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN__SHIFT 0xa
+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C_MASK 0x1000
+#define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C__SHIFT 0xc
+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG_MASK 0x2000
+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG__SHIFT 0xd
+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX_MASK 0x4000
+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX__SHIFT 0xe
+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_MASK 0x8000
+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0__SHIFT 0xf
+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG_MASK 0x10000
+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG__SHIFT 0x10
+#define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE_MASK 0x20000
+#define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE__SHIFT 0x11
+#define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE_MASK 0x40000
+#define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE__SHIFT 0x12
+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX_MASK 0x80000
+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX__SHIFT 0x13
+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_MASK 0x100000
+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN__SHIFT 0x14
+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX_MASK 0x200000
+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX__SHIFT 0x15
+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG_MASK 0x400000
+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG__SHIFT 0x16
+#define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE_MASK 0x800000
+#define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE__SHIFT 0x17
+#define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE_MASK 0x1000000
+#define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE__SHIFT 0x18
+#define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL_MASK 0x2000000
+#define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL__SHIFT 0x19
+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX_MASK 0x4000000
+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT 0x1a
+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_MASK 0x8000000
+#define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0__SHIFT 0x1b
+#define DCIO_DEBUG2__DCIO_DEBUG2_MASK 0xffffffff
+#define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT 0x0
+#define DCIO_DEBUG3__DCIO_DEBUG3_MASK 0xffffffff
+#define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT 0x0
+#define DCIO_DEBUG4__DCIO_DEBUG4_MASK 0xffffffff
+#define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT 0x0
+#define DCIO_DEBUG5__DCIO_DEBUG5_MASK 0xffffffff
+#define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT 0x0
+#define DCIO_DEBUG6__DCIO_DEBUG6_MASK 0xffffffff
+#define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT 0x0
+#define DCIO_DEBUG7__DCIO_DEBUG7_MASK 0xffffffff
+#define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT 0x0
+#define DCIO_DEBUG8__DCIO_DEBUG8_MASK 0xffffffff
+#define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT 0x0
+#define DCIO_DEBUG9__DCIO_DEBUG9_MASK 0xffffffff
+#define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT 0x0
+#define DCIO_DEBUGA__DCIO_DEBUGA_MASK 0xffffffff
+#define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT 0x0
+#define DCIO_DEBUGB__DCIO_DEBUGB_MASK 0xffffffff
+#define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT 0x0
+#define DCIO_DEBUGC__DCIO_DEBUGC_MASK 0xffffffff
+#define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT 0x0
+#define DCIO_DEBUGD__DCIO_DEBUGD_MASK 0xffffffff
+#define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT 0x0
+#define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT 0x0
+#define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT 0x0
+#define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT 0x0
+#define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT 0x0
+#define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT 0x0
+#define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT 0x0
+#define DCIO_DEBUG14__DCIO_DIGG_DEBUG_MASK 0xffffffff
+#define DCIO_DEBUG14__DCIO_DIGG_DEBUG__SHIFT 0x0
+#define DCIO_DEBUG15__DCIO_DEBUG15_MASK 0xffffffff
+#define DCIO_DEBUG15__DCIO_DEBUG15__SHIFT 0x0
+#define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK 0xffffffff
+#define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT 0x0
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x1
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x2
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x4
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x10
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x20
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x40
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x100
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x200
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x400
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x1000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x2000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x4000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x10000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x20000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x40000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x100000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x200000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x400000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x1000000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x2000000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x4000000
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x1
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x100
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x10000
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x100000
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x200000
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x400000
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x800000
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x1
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x100
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x10000
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x100000
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x200000
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x400000
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x800000
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x1
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x100
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x10000
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x100000
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x200000
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x400000
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x800000
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0xffffff
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x0
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x1f000000
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x18
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x20000000
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x1d
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xc0000000
+#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x1e
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0xffffff
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x0
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x1f000000
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x18
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x20000000
+#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x1d
+#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xc0000000
+#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x1e
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0xffffff
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x0
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x1f000000
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x18
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x20000000
+#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x1d
+#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xc0000000
+#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x1e
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0xffffff
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x0
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x1f000000
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x18
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x20000000
+#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x1d
+#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xc0000000
+#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x1e
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x1
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x10
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x40
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x100
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x1000
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x4000
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x10000
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10
+#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x100000
+#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x400000
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0xf000000
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xf0000000
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x1
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x100
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x1
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x100
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x1
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x100
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x1
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x10
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x40
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x100
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x1000
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x4000
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x10000
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10
+#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x100000
+#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x400000
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0xf000000
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xf0000000
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x1
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x100
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x1
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x100
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x1
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x100
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x1
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x10
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x40
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x100
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x1000
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x4000
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x10000
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10
+#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x100000
+#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x400000
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0xf000000
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xf0000000
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x1
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x100
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x1
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x100
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x1
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x100
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x1
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x10
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x40
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x100
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x1000
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x4000
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x10000
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10
+#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x100000
+#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x400000
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0xf000000
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xf0000000
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x1
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x100
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x1
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x100
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x1
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x100
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x1
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x10
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x40
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x100
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x1000
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x4000
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x10000
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10
+#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x100000
+#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x400000
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0xf000000
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xf0000000
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x1
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x100
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x1
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x100
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x1
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x100
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x1
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x10
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x4
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x40
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x100
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x1000
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x4000
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x10000
+#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x10
+#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x100000
+#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x14
+#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x400000
+#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0xf000000
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x18
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xf0000000
+#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x1
+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x0
+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x100
+#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x8
+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x1
+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x0
+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x100
+#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x8
+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x1
+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x0
+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x100
+#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x8
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x1
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x40
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x100
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x1000
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x4000
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x10000
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x100000
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x400000
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0xf000000
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xf0000000
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x1
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x100
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x1
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x100
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x1
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x100
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x1
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x0
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x10
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x4
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x40
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x6
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x100
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x8
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x1000
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0xc
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x4000
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0xe
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x7000000
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x18
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000
+#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x1c
+#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x1
+#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x0
+#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x100
+#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x8
+#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x1
+#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x0
+#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x100
+#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x8
+#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x1
+#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x0
+#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x100
+#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x8
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x1
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x2
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x4
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x2
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x8
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x100
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x200
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x400
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xa
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x800
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x10000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x20000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x40000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x12
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x80000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x1000000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x2000000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x4000000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1a
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x8000000
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x1
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x100
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x10000
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x1000000
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x1
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x100
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x10000
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x1000000
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x1
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x100
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x10000
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x1000000
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x1
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x10
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x40
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x100
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x200
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x400
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x10000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x20000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x40000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x100000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x200000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x400000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x1000000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x2000000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x4000000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0x40000000
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x1
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x100
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x10000
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x1000000
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x4000000
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x1
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x100
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x10000
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x1000000
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x18
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x4000000
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x1a
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x1
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x100
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x10000
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x1000000
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x4000000
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x1
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x10
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x40
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x100
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x1000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x4000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x10000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x100000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x400000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x1000000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x2000000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x4000000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000
+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x1
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x100
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x10000
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x1000000
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000
+#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x1
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x2
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x100
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x10000
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x1000000
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000
+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x1
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x100
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x10000
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x1000000
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000
+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0xf
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0xf0
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0xf000000
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xf0000000
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0xf
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0xf0
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x700
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x7000
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0xf0000
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0xf00000
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xc0000000
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e
+#define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x1000
+#define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0xc
+#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x4000
+#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0xe
+#define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x10000
+#define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x10
+#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x1
+#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x0
+#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x2
+#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x1
+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x1
+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x0
+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x2
+#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x1
+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x1
+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x0
+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x2
+#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x1
+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0xf
+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x0
+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0xf0
+#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x4
+#define DVO_STRENGTH_CONTROL__DVO_SP_MASK 0xf
+#define DVO_STRENGTH_CONTROL__DVO_SP__SHIFT 0x0
+#define DVO_STRENGTH_CONTROL__DVO_SN_MASK 0xf0
+#define DVO_STRENGTH_CONTROL__DVO_SN__SHIFT 0x4
+#define DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK 0xf00
+#define DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT 0x8
+#define DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK 0xf000
+#define DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT 0xc
+#define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH_MASK 0x70000
+#define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH__SHIFT 0x10
+#define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH_MASK 0x700000
+#define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH__SHIFT 0x14
+#define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH_MASK 0x7000000
+#define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH__SHIFT 0x18
+#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK 0x10000000
+#define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT 0x1c
+#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK 0x20000000
+#define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT 0x1d
+#define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x1
+#define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x0
+#define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x2
+#define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1
+#define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0xf0
+#define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x4
+#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xffffffff
+#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x0
+#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN_MASK 0x3ff
+#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN__SHIFT 0x0
+#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN_MASK 0x10000
+#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN__SHIFT 0x10
+#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL_MASK 0xe0000
+#define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL__SHIFT 0x11
+#define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED_MASK 0x7fffff
+#define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED__SHIFT 0x0
+#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN_MASK 0x3ff
+#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN__SHIFT 0x0
+#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN_MASK 0x10000
+#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN__SHIFT 0x10
+#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL_MASK 0xe0000
+#define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL__SHIFT 0x11
+#define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED_MASK 0x7fffff
+#define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED__SHIFT 0x0
+#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN_MASK 0x3ff
+#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN__SHIFT 0x0
+#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN_MASK 0x10000
+#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN__SHIFT 0x10
+#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL_MASK 0xe0000
+#define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL__SHIFT 0x11
+#define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED_MASK 0x7fffff
+#define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED__SHIFT 0x0
+#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_STATIC_TEST_PATTERN_MASK 0x3ff
+#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_STATIC_TEST_PATTERN__SHIFT 0x0
+#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_EN_MASK 0x10000
+#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_EN__SHIFT 0x10
+#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_SEL_MASK 0xe0000
+#define UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_SEL__SHIFT 0x11
+#define UNIPHYGH_TPG_SEED__UNIPHYGH_TPG_SEED_MASK 0x7fffff
+#define UNIPHYGH_TPG_SEED__UNIPHYGH_TPG_SEED__SHIFT 0x0
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK_MASK 0xf
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK__SHIFT 0x0
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK_MASK 0x10
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK__SHIFT 0x4
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK_MASK 0x20
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK__SHIFT 0x5
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK_MASK 0x40
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK__SHIFT 0x6
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK_MASK 0x80
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK__SHIFT 0x7
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK_MASK 0x100
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK__SHIFT 0x8
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK_MASK 0x200
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK__SHIFT 0x9
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK_MASK 0x400
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK__SHIFT 0xa
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK_MASK 0x800
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK__SHIFT 0xb
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK_MASK 0x1000
+#define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK__SHIFT 0xc
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A_MASK 0xf
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A__SHIFT 0x0
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A_MASK 0x10
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A__SHIFT 0x4
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A_MASK 0x20
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A__SHIFT 0x5
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A_MASK 0x40
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A__SHIFT 0x6
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A_MASK 0x80
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A__SHIFT 0x7
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A_MASK 0x100
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A__SHIFT 0x8
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A_MASK 0x200
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A__SHIFT 0x9
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A_MASK 0x400
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A__SHIFT 0xa
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A_MASK 0x800
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A__SHIFT 0xb
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A_MASK 0x1000
+#define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A__SHIFT 0xc
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN_MASK 0xf
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN__SHIFT 0x0
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN_MASK 0x10
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN__SHIFT 0x4
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN_MASK 0x20
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN__SHIFT 0x5
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN_MASK 0x40
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN__SHIFT 0x6
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN_MASK 0x80
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN__SHIFT 0x7
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN_MASK 0x100
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN__SHIFT 0x8
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN_MASK 0x200
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN__SHIFT 0x9
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN_MASK 0x400
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN__SHIFT 0xa
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN_MASK 0x800
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN__SHIFT 0xb
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN_MASK 0x1000
+#define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN__SHIFT 0xc
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y_MASK 0xf
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y__SHIFT 0x0
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y_MASK 0x10
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y__SHIFT 0x4
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y_MASK 0x20
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y__SHIFT 0x5
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y_MASK 0x40
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y__SHIFT 0x6
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y_MASK 0x80
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y__SHIFT 0x7
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y_MASK 0x100
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y__SHIFT 0x8
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y_MASK 0x200
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y__SHIFT 0x9
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y_MASK 0x400
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y__SHIFT 0xa
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y_MASK 0x800
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y__SHIFT 0xb
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y_MASK 0x1000
+#define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y__SHIFT 0xc
+#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH_MASK 0x7
+#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH__SHIFT 0x0
+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_MASK 0x700
+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH__SHIFT 0x8
+#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH_MASK 0x70000
+#define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH__SHIFT 0x10
+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_MASK 0x7000000
+#define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH__SHIFT 0x18
+#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff
+#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0_MASK 0x7
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0__SHIFT 0x0
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1_MASK 0x70
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1__SHIFT 0x4
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2_MASK 0x700
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2__SHIFT 0x8
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3_MASK 0x7000
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3__SHIFT 0xc
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4_MASK 0x70000
+#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4__SHIFT 0x10
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0_MASK 0x300000
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0__SHIFT 0x14
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1_MASK 0xc00000
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1__SHIFT 0x16
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2_MASK 0x3000000
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2__SHIFT 0x18
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3_MASK 0xc000000
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3__SHIFT 0x1a
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4_MASK 0x30000000
+#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4__SHIFT 0x1c
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC_MASK 0x3
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC__SHIFT 0x0
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC_MASK 0x30
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC__SHIFT 0x4
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC_MASK 0x300
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC__SHIFT 0x8
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC_MASK 0x3000
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC__SHIFT 0xc
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC_MASK 0x30000
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC__SHIFT 0x10
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL_MASK 0x100000
+#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL__SHIFT 0x14
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL_MASK 0x600000
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL__SHIFT 0x15
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL_MASK 0x1800000
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL__SHIFT 0x17
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL_MASK 0x6000000
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL__SHIFT 0x19
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL_MASK 0x18000000
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL__SHIFT 0x1b
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL_MASK 0x60000000
+#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL__SHIFT 0x1d
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK_MASK 0x3
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK__SHIFT 0x0
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT_MASK 0xc
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT__SHIFT 0x2
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK_MASK 0xf0
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK__SHIFT 0x4
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT_MASK 0xf00
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT__SHIFT 0x8
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK_MASK 0x7000
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK__SHIFT 0xc
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT_MASK 0x70000
+#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT__SHIFT 0x10
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0_MASK 0x100000
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0__SHIFT 0x14
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1_MASK 0x200000
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1__SHIFT 0x15
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2_MASK 0x400000
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2__SHIFT 0x16
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3_MASK 0x800000
+#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3__SHIFT 0x17
+#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ_MASK 0x1f000000
+#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ__SHIFT 0x18
+#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN_MASK 0x80000000
+#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN__SHIFT 0x1f
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK_MASK 0x1f
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK__SHIFT 0x0
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT_MASK 0x3e0
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT__SHIFT 0x5
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK_MASK 0x1f000
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT 0xc
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK 0x3e0000
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT 0x11
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK_MASK 0x7000000
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK__SHIFT 0x18
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT_MASK 0x70000000
+#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT__SHIFT 0x1c
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN_MASK 0x1
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN__SHIFT 0x0
+#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC_MASK 0x2
+#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC__SHIFT 0x1
+#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL_MASK 0x4
+#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL__SHIFT 0x2
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00_MASK 0xf00
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00__SHIFT 0x8
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25_MASK 0xf000
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25__SHIFT 0xc
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45_MASK 0xf0000
+#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45__SHIFT 0x10
+#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION_MASK 0xfffc
+#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION__SHIFT 0x2
+#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_MASK 0xfff0000
+#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV__SHIFT 0x10
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE_MASK 0x1
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE__SHIFT 0x0
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET_MASK 0x2
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET__SHIFT 0x1
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN_MASK 0x4
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN__SHIFT 0x2
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN_MASK 0x8
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN__SHIFT 0x3
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN_MASK 0xf0
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN__SHIFT 0x4
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL_MASK 0x7f00
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL__SHIFT 0x8
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL_MASK 0xff0000
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL__SHIFT 0x10
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC_MASK 0x1000000
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC__SHIFT 0x18
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN_MASK 0x2000000
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN__SHIFT 0x19
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN_MASK 0x4000000
+#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN__SHIFT 0x1a
+#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE_MASK 0x30000000
+#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE__SHIFT 0x1c
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE_MASK 0x3
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE__SHIFT 0x0
+#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL_MASK 0xc
+#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x2
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL_MASK 0x10
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL__SHIFT 0x4
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL_MASK 0x20
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL__SHIFT 0x5
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x40
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL__SHIFT 0x6
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC_MASK 0x700
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC__SHIFT 0x8
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN_MASK 0x800
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN__SHIFT 0xb
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN_MASK 0x1000
+#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN__SHIFT 0xc
+#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV_MASK 0x2000
+#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV__SHIFT 0xd
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL_MASK 0x10000
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL__SHIFT 0x10
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS_MASK 0x80000
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS__SHIFT 0x13
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL_MASK 0x100000
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL__SHIFT 0x14
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV_MASK 0x1f000000
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV__SHIFT 0x18
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL_MASK 0xe0000000
+#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL__SHIFT 0x1d
+#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE_MASK 0x3ffffff
+#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE__SHIFT 0x0
+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM_MASK 0xfff
+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM__SHIFT 0x0
+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN_MASK 0x1000
+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN__SHIFT 0xc
+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN_MASK 0x2000
+#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN__SHIFT 0xd
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL_MASK 0x1
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL__SHIFT 0x0
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL_MASK 0x30
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL__SHIFT 0x4
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR_MASK 0x40
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR__SHIFT 0x6
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT_MASK 0x100
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT__SHIFT 0x8
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE_MASK 0x1000
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE__SHIFT 0xc
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE_MASK 0x10000
+#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE__SHIFT 0x10
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL_MASK 0x1f
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x0
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_MASK 0x1e0
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL__SHIFT 0x5
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN_MASK 0x200
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN__SHIFT 0x9
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR_MASK 0x400
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR__SHIFT 0xa
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET_MASK 0x8000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET__SHIFT 0xf
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL_MASK 0x10000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL__SHIFT 0x10
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN_MASK 0x20000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN__SHIFT 0x11
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_MASK 0x1f00000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR__SHIFT 0x14
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC_MASK 0xe000000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC__SHIFT 0x19
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK_MASK 0x10000000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK__SHIFT 0x1c
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET_MASK 0x20000000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET__SHIFT 0x1d
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY_MASK 0x40000000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY__SHIFT 0x1e
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK_MASK 0x80000000
+#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK__SHIFT 0x1f
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN_MASK 0x1
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN__SHIFT 0x0
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET_MASK 0x2
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET__SHIFT 0x1
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS_MASK 0xf00
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS__SHIFT 0x8
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR_MASK 0x1f0000
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR__SHIFT 0x10
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB_MASK 0x1000000
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB__SHIFT 0x18
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN_MASK 0x2000000
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN__SHIFT 0x19
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT_MASK 0x4000000
+#define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT__SHIFT 0x1a
+#define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1
+#define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0
+#define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10
+#define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4
+#define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700
+#define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8
+#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000
+#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc
+#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000
+#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd
+#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000
+#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe
+#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000
+#define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf
+#define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x30000
+#define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x10
+#define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000
+#define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14
+#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3
+#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0
+#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300
+#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8
+#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000
+#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10
+#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000
+#define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18
+#define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX_MASK 0xffff
+#define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX__SHIFT 0x0
+#define GRPH_ENABLE__GRPH_ENABLE_MASK 0x1
+#define GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0
+#define GRPH_CONTROL__GRPH_DEPTH_MASK 0x3
+#define GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0
+#define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc
+#define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2
+#define GRPH_CONTROL__GRPH_Z_MASK 0x30
+#define GRPH_CONTROL__GRPH_Z__SHIFT 0x4
+#define GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0xc0
+#define GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x6
+#define GRPH_CONTROL__GRPH_FORMAT_MASK 0x700
+#define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8
+#define GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x1800
+#define GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0xb
+#define GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0xe000
+#define GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0xd
+#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000
+#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
+#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000
+#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
+#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0xc0000
+#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x12
+#define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000
+#define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14
+#define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000
+#define GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18
+#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK 0x60000000
+#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT 0x1d
+#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000
+#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f
+#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x100
+#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8
+#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x10000
+#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10
+#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3
+#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0
+#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30
+#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4
+#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0
+#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6
+#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300
+#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8
+#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0xc00
+#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa
+#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x1
+#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0
+#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xffffff00
+#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8
+#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x1
+#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0
+#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00
+#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
+#define GRPH_PITCH__GRPH_PITCH_MASK 0x7fff
+#define GRPH_PITCH__GRPH_PITCH__SHIFT 0x0
+#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0xff
+#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff
+#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x3fff
+#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0
+#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x3fff
+#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0
+#define GRPH_X_START__GRPH_X_START_MASK 0x3fff
+#define GRPH_X_START__GRPH_X_START__SHIFT 0x0
+#define GRPH_Y_START__GRPH_Y_START_MASK 0x3fff
+#define GRPH_Y_START__GRPH_Y_START__SHIFT 0x0
+#define GRPH_X_END__GRPH_X_END_MASK 0x7fff
+#define GRPH_X_END__GRPH_X_END__SHIFT 0x0
+#define GRPH_Y_END__GRPH_Y_END_MASK 0x7fff
+#define GRPH_Y_END__GRPH_Y_END__SHIFT 0x0
+#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x3
+#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0
+#define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE_MASK 0x30
+#define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT 0x4
+#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1
+#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0
+#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2
+#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1
+#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4
+#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2
+#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8
+#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3
+#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK 0x100
+#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT 0x8
+#define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000
+#define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10
+#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000
+#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14
+#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
+#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000
+#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c
+#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x1
+#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0
+#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xffffff00
+#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8
+#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x1
+#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0
+#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x70
+#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4
+#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x700
+#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
+#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0xf
+#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0
+#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0
+#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
+#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x100
+#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8
+#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x200
+#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9
+#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1
+#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0
+#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100
+#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8
+#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1
+#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0
+#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100
+#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8
+#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff
+#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
+#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xffffff00
+#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8
+#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x1ffc0
+#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6
+#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0xff
+#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define OVL_ENABLE__OVL_ENABLE_MASK 0x1
+#define OVL_ENABLE__OVL_ENABLE__SHIFT 0x0
+#define OVL_ENABLE__OVLSCL_EN_MASK 0x100
+#define OVL_ENABLE__OVLSCL_EN__SHIFT 0x8
+#define OVL_CONTROL1__OVL_DEPTH_MASK 0x3
+#define OVL_CONTROL1__OVL_DEPTH__SHIFT 0x0
+#define OVL_CONTROL1__OVL_NUM_BANKS_MASK 0xc
+#define OVL_CONTROL1__OVL_NUM_BANKS__SHIFT 0x2
+#define OVL_CONTROL1__OVL_Z_MASK 0x30
+#define OVL_CONTROL1__OVL_Z__SHIFT 0x4
+#define OVL_CONTROL1__OVL_BANK_WIDTH_MASK 0xc0
+#define OVL_CONTROL1__OVL_BANK_WIDTH__SHIFT 0x6
+#define OVL_CONTROL1__OVL_FORMAT_MASK 0x700
+#define OVL_CONTROL1__OVL_FORMAT__SHIFT 0x8
+#define OVL_CONTROL1__OVL_BANK_HEIGHT_MASK 0x1800
+#define OVL_CONTROL1__OVL_BANK_HEIGHT__SHIFT 0xb
+#define OVL_CONTROL1__OVL_TILE_SPLIT_MASK 0xe000
+#define OVL_CONTROL1__OVL_TILE_SPLIT__SHIFT 0xd
+#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000
+#define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10
+#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000
+#define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11
+#define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT_MASK 0xc0000
+#define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT__SHIFT 0x12
+#define OVL_CONTROL1__OVL_ARRAY_MODE_MASK 0xf00000
+#define OVL_CONTROL1__OVL_ARRAY_MODE__SHIFT 0x14
+#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE_MASK 0x1000000
+#define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE__SHIFT 0x18
+#define OVL_CONTROL1__OVL_PIPE_CONFIG_MASK 0x3e000000
+#define OVL_CONTROL1__OVL_PIPE_CONFIG__SHIFT 0x19
+#define OVL_CONTROL1__OVL_MICRO_TILE_MODE_MASK 0xc0000000
+#define OVL_CONTROL1__OVL_MICRO_TILE_MODE__SHIFT 0x1e
+#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE_MASK 0x1
+#define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE__SHIFT 0x0
+#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP_MASK 0x3
+#define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP__SHIFT 0x0
+#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR_MASK 0x30
+#define OVL_SWAP_CNTL__OVL_RED_CROSSBAR__SHIFT 0x4
+#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR_MASK 0xc0
+#define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR__SHIFT 0x6
+#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR_MASK 0x300
+#define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR__SHIFT 0x8
+#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR_MASK 0xc00
+#define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR__SHIFT 0xa
+#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE_MASK 0x1
+#define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE__SHIFT 0x0
+#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS_MASK 0xffffff00
+#define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS__SHIFT 0x8
+#define OVL_PITCH__OVL_PITCH_MASK 0x7fff
+#define OVL_PITCH__OVL_PITCH__SHIFT 0x0
+#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH_MASK 0xff
+#define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X_MASK 0x3fff
+#define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X__SHIFT 0x0
+#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y_MASK 0x3fff
+#define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y__SHIFT 0x0
+#define OVL_START__OVL_Y_START_MASK 0x3fff
+#define OVL_START__OVL_Y_START__SHIFT 0x0
+#define OVL_START__OVL_X_START_MASK 0x3fff0000
+#define OVL_START__OVL_X_START__SHIFT 0x10
+#define OVL_END__OVL_Y_END_MASK 0x7fff
+#define OVL_END__OVL_Y_END__SHIFT 0x0
+#define OVL_END__OVL_X_END_MASK 0x7fff0000
+#define OVL_END__OVL_X_END__SHIFT 0x10
+#define OVL_UPDATE__OVL_UPDATE_PENDING_MASK 0x1
+#define OVL_UPDATE__OVL_UPDATE_PENDING__SHIFT 0x0
+#define OVL_UPDATE__OVL_UPDATE_TAKEN_MASK 0x2
+#define OVL_UPDATE__OVL_UPDATE_TAKEN__SHIFT 0x1
+#define OVL_UPDATE__OVL_UPDATE_LOCK_MASK 0x10000
+#define OVL_UPDATE__OVL_UPDATE_LOCK__SHIFT 0x10
+#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
+#define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE_MASK 0xffffff00
+#define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE__SHIFT 0x8
+#define OVL_DFQ_CONTROL__OVL_DFQ_RESET_MASK 0x1
+#define OVL_DFQ_CONTROL__OVL_DFQ_RESET__SHIFT 0x0
+#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE_MASK 0x70
+#define OVL_DFQ_CONTROL__OVL_DFQ_SIZE__SHIFT 0x4
+#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES_MASK 0x700
+#define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8
+#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES_MASK 0xf
+#define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES__SHIFT 0x0
+#define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0
+#define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4
+#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG_MASK 0x100
+#define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG__SHIFT 0x8
+#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK_MASK 0x200
+#define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK__SHIFT 0x9
+#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff
+#define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0
+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB_MASK 0x3ff
+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB__SHIFT 0x0
+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY_MASK 0xffc00
+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY__SHIFT 0xa
+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR_MASK 0x3ff00000
+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR__SHIFT 0x14
+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL_MASK 0x80000000
+#define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL__SHIFT 0x1f
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x1
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x2
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x4
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x8
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x10
+#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4
+#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0xffff
+#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0
+#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xffff0000
+#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10
+#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0xffff
+#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0
+#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xffff0000
+#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10
+#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0xffff
+#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0
+#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xffff0000
+#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10
+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT_MASK 0x1
+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT__SHIFT 0x0
+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN_MASK 0x2
+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN__SHIFT 0x1
+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN_MASK 0x4
+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN__SHIFT 0x2
+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN_MASK 0x8
+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN__SHIFT 0x3
+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK 0x10
+#define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS__SHIFT 0x4
+#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB_MASK 0xffff
+#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB__SHIFT 0x0
+#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB_MASK 0xffff0000
+#define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB__SHIFT 0x10
+#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y_MASK 0xffff
+#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y__SHIFT 0x0
+#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y_MASK 0xffff0000
+#define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y__SHIFT 0x10
+#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR_MASK 0xffff
+#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR__SHIFT 0x0
+#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR_MASK 0xffff0000
+#define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR__SHIFT 0x10
+#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x3
+#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0
+#define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE_MASK 0x30
+#define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT 0x4
+#define INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0xffff
+#define INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0
+#define INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xffff0000
+#define INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10
+#define INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0xffff
+#define INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0
+#define INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xffff0000
+#define INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10
+#define INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0xffff
+#define INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0
+#define INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xffff0000
+#define INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10
+#define INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0xffff
+#define INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0
+#define INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xffff0000
+#define INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10
+#define INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0xffff
+#define INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0
+#define INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xffff0000
+#define INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10
+#define INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0xffff
+#define INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0
+#define INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xffff0000
+#define INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10
+#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x7
+#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0
+#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE_MASK 0x70
+#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT 0x4
+#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0xffff
+#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0
+#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xffff0000
+#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10
+#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0xffff
+#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0
+#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xffff0000
+#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10
+#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0xffff
+#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0
+#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xffff0000
+#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10
+#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0xffff
+#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0
+#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xffff0000
+#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10
+#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0xffff
+#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0
+#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xffff0000
+#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10
+#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0xffff
+#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0
+#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xffff0000
+#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10
+#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0xffff
+#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0
+#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xffff0000
+#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10
+#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0xffff
+#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0
+#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xffff0000
+#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10
+#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0xffff
+#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0
+#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xffff0000
+#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10
+#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0xffff
+#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0
+#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xffff0000
+#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10
+#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0xffff
+#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0
+#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xffff0000
+#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10
+#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0xffff
+#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0
+#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xffff0000
+#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10
+#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0xffff
+#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0
+#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xffff0000
+#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10
+#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0xffff
+#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0
+#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xffff0000
+#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10
+#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0xffff
+#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0
+#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xffff0000
+#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10
+#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0xffff
+#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0
+#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xffff0000
+#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10
+#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0xffff
+#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0
+#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xffff0000
+#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10
+#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0xffff
+#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0
+#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xffff0000
+#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10
+#define DENORM_CONTROL__DENORM_MODE_MASK 0x7
+#define DENORM_CONTROL__DENORM_MODE__SHIFT 0x0
+#define DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x10
+#define DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4
+#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0xf
+#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0
+#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x3fff
+#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0
+#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3fff0000
+#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10
+#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x3fff
+#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0
+#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3fff0000
+#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10
+#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x3fff
+#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0
+#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3fff0000
+#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10
+#define KEY_CONTROL__KEY_SELECT_MASK 0x1
+#define KEY_CONTROL__KEY_SELECT__SHIFT 0x0
+#define KEY_CONTROL__KEY_MODE_MASK 0x6
+#define KEY_CONTROL__KEY_MODE__SHIFT 0x1
+#define KEY_CONTROL__GRPH_OVL_HALF_BLEND_MASK 0x10000000
+#define KEY_CONTROL__GRPH_OVL_HALF_BLEND__SHIFT 0x1c
+#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0xffff
+#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0
+#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xffff0000
+#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10
+#define KEY_RANGE_RED__KEY_RED_LOW_MASK 0xffff
+#define KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0
+#define KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xffff0000
+#define KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10
+#define KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0xffff
+#define KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0
+#define KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xffff0000
+#define KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10
+#define KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0xffff
+#define KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0
+#define KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xffff0000
+#define KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10
+#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x3
+#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0
+#define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE_MASK 0x30
+#define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT 0x4
+#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x300
+#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8
+#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x3000
+#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc
+#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x3
+#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0
+#define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE_MASK 0x30
+#define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT 0x4
+#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0xffff
+#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0
+#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xffff0000
+#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10
+#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0xffff
+#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0
+#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xffff0000
+#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10
+#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0xffff
+#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0
+#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xffff0000
+#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10
+#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0xffff
+#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0
+#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xffff0000
+#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10
+#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0xffff
+#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0
+#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xffff0000
+#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10
+#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0xffff
+#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0
+#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xffff0000
+#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10
+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x1
+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0
+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x30
+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4
+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0xc0
+#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6
+#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x100
+#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8
+#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x200
+#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9
+#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x400
+#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa
+#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0xff
+#define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0
+#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0xff00
+#define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8
+#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0xff0000
+#define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10
+#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff
+#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0
+#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x7f00000
+#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14
+#define CUR_CONTROL__CURSOR_EN_MASK 0x1
+#define CUR_CONTROL__CURSOR_EN__SHIFT 0x0
+#define CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x10
+#define CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4
+#define CUR_CONTROL__CURSOR_MODE_MASK 0x300
+#define CUR_CONTROL__CURSOR_MODE__SHIFT 0x8
+#define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x10000
+#define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10
+#define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x100000
+#define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14
+#define CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x7000000
+#define CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18
+#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xffffffff
+#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0
+#define CUR_SIZE__CURSOR_HEIGHT_MASK 0x7f
+#define CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0
+#define CUR_SIZE__CURSOR_WIDTH_MASK 0x7f0000
+#define CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10
+#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0xff
+#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define CUR_POSITION__CURSOR_Y_POSITION_MASK 0x3fff
+#define CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0
+#define CUR_POSITION__CURSOR_X_POSITION_MASK 0x3fff0000
+#define CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10
+#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x7f
+#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0
+#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x7f0000
+#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10
+#define CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0xff
+#define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0
+#define CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0xff00
+#define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8
+#define CUR_COLOR1__CUR_COLOR1_RED_MASK 0xff0000
+#define CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10
+#define CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0xff
+#define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0
+#define CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0xff00
+#define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8
+#define CUR_COLOR2__CUR_COLOR2_RED_MASK 0xff0000
+#define CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10
+#define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x1
+#define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0
+#define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x2
+#define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1
+#define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x10000
+#define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10
+#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
+#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x6000000
+#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19
+#define CUR2_CONTROL__CURSOR2_EN_MASK 0x1
+#define CUR2_CONTROL__CURSOR2_EN__SHIFT 0x0
+#define CUR2_CONTROL__CUR2_INV_TRANS_CLAMP_MASK 0x10
+#define CUR2_CONTROL__CUR2_INV_TRANS_CLAMP__SHIFT 0x4
+#define CUR2_CONTROL__CURSOR2_MODE_MASK 0x300
+#define CUR2_CONTROL__CURSOR2_MODE__SHIFT 0x8
+#define CUR2_CONTROL__CURSOR2_2X_MAGNIFY_MASK 0x10000
+#define CUR2_CONTROL__CURSOR2_2X_MAGNIFY__SHIFT 0x10
+#define CUR2_CONTROL__CURSOR2_FORCE_MC_ON_MASK 0x100000
+#define CUR2_CONTROL__CURSOR2_FORCE_MC_ON__SHIFT 0x14
+#define CUR2_CONTROL__CURSOR2_URGENT_CONTROL_MASK 0x7000000
+#define CUR2_CONTROL__CURSOR2_URGENT_CONTROL__SHIFT 0x18
+#define CUR2_SURFACE_ADDRESS__CURSOR2_SURFACE_ADDRESS_MASK 0xffffffff
+#define CUR2_SURFACE_ADDRESS__CURSOR2_SURFACE_ADDRESS__SHIFT 0x0
+#define CUR2_SIZE__CURSOR2_HEIGHT_MASK 0x7f
+#define CUR2_SIZE__CURSOR2_HEIGHT__SHIFT 0x0
+#define CUR2_SIZE__CURSOR2_WIDTH_MASK 0x7f0000
+#define CUR2_SIZE__CURSOR2_WIDTH__SHIFT 0x10
+#define CUR2_SURFACE_ADDRESS_HIGH__CURSOR2_SURFACE_ADDRESS_HIGH_MASK 0xff
+#define CUR2_SURFACE_ADDRESS_HIGH__CURSOR2_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define CUR2_POSITION__CURSOR2_Y_POSITION_MASK 0x3fff
+#define CUR2_POSITION__CURSOR2_Y_POSITION__SHIFT 0x0
+#define CUR2_POSITION__CURSOR2_X_POSITION_MASK 0x3fff0000
+#define CUR2_POSITION__CURSOR2_X_POSITION__SHIFT 0x10
+#define CUR2_HOT_SPOT__CURSOR2_HOT_SPOT_Y_MASK 0x7f
+#define CUR2_HOT_SPOT__CURSOR2_HOT_SPOT_Y__SHIFT 0x0
+#define CUR2_HOT_SPOT__CURSOR2_HOT_SPOT_X_MASK 0x7f0000
+#define CUR2_HOT_SPOT__CURSOR2_HOT_SPOT_X__SHIFT 0x10
+#define CUR2_COLOR1__CUR2_COLOR1_BLUE_MASK 0xff
+#define CUR2_COLOR1__CUR2_COLOR1_BLUE__SHIFT 0x0
+#define CUR2_COLOR1__CUR2_COLOR1_GREEN_MASK 0xff00
+#define CUR2_COLOR1__CUR2_COLOR1_GREEN__SHIFT 0x8
+#define CUR2_COLOR1__CUR2_COLOR1_RED_MASK 0xff0000
+#define CUR2_COLOR1__CUR2_COLOR1_RED__SHIFT 0x10
+#define CUR2_COLOR2__CUR2_COLOR2_BLUE_MASK 0xff
+#define CUR2_COLOR2__CUR2_COLOR2_BLUE__SHIFT 0x0
+#define CUR2_COLOR2__CUR2_COLOR2_GREEN_MASK 0xff00
+#define CUR2_COLOR2__CUR2_COLOR2_GREEN__SHIFT 0x8
+#define CUR2_COLOR2__CUR2_COLOR2_RED_MASK 0xff0000
+#define CUR2_COLOR2__CUR2_COLOR2_RED__SHIFT 0x10
+#define CUR2_UPDATE__CURSOR2_UPDATE_PENDING_MASK 0x1
+#define CUR2_UPDATE__CURSOR2_UPDATE_PENDING__SHIFT 0x0
+#define CUR2_UPDATE__CURSOR2_UPDATE_TAKEN_MASK 0x2
+#define CUR2_UPDATE__CURSOR2_UPDATE_TAKEN__SHIFT 0x1
+#define CUR2_UPDATE__CURSOR2_UPDATE_LOCK_MASK 0x10000
+#define CUR2_UPDATE__CURSOR2_UPDATE_LOCK__SHIFT 0x10
+#define CUR2_UPDATE__CURSOR2_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000
+#define CUR2_UPDATE__CURSOR2_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18
+#define CUR2_UPDATE__CURSOR2_UPDATE_STEREO_MODE_MASK 0x6000000
+#define CUR2_UPDATE__CURSOR2_UPDATE_STEREO_MODE__SHIFT 0x19
+#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x1
+#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0
+#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x1
+#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0
+#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX_MASK 0x2
+#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX__SHIFT 0x1
+#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x3ff0
+#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4
+#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x3ff0000
+#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10
+#define CUR2_STEREO_CONTROL__CURSOR2_STEREO_EN_MASK 0x1
+#define CUR2_STEREO_CONTROL__CURSOR2_STEREO_EN__SHIFT 0x0
+#define CUR2_STEREO_CONTROL__CURSOR2_STEREO_OFFSET_YNX_MASK 0x2
+#define CUR2_STEREO_CONTROL__CURSOR2_STEREO_OFFSET_YNX__SHIFT 0x1
+#define CUR2_STEREO_CONTROL__CURSOR2_PRIMARY_OFFSET_MASK 0x3ff0
+#define CUR2_STEREO_CONTROL__CURSOR2_PRIMARY_OFFSET__SHIFT 0x4
+#define CUR2_STEREO_CONTROL__CURSOR2_SECONDARY_OFFSET_MASK 0x3ff0000
+#define CUR2_STEREO_CONTROL__CURSOR2_SECONDARY_OFFSET__SHIFT 0x10
+#define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x1
+#define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0
+#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0xff
+#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0
+#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0xffff
+#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0
+#define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0xffff
+#define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0
+#define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xffff0000
+#define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10
+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x3ff
+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0
+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0xffc00
+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa
+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3ff00000
+#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14
+#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x1
+#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0
+#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x7
+#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x1
+#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0
+#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x2
+#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1
+#define DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0xf
+#define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0
+#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x10
+#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4
+#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x20
+#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5
+#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0xc0
+#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6
+#define DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0xf00
+#define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8
+#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x1000
+#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc
+#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x2000
+#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd
+#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0xc000
+#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe
+#define DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0xf0000
+#define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10
+#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x100000
+#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14
+#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x200000
+#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15
+#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0xc00000
+#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16
+#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0xffff
+#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0
+#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0xffff
+#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0
+#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0xffff
+#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0
+#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0xffff
+#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0
+#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0xffff
+#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0
+#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0xffff
+#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0
+#define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x1
+#define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0
+#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x1c
+#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2
+#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x300
+#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8
+#define DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xffffffff
+#define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0
+#define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xffffffff
+#define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0
+#define DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xffffffff
+#define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0
+#define DCP_DEBUG__DCP_DEBUG_MASK 0xffffffff
+#define DCP_DEBUG__DCP_DEBUG__SHIFT 0x0
+#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x7
+#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0
+#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x8
+#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3
+#define DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x1
+#define DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0
+#define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x2
+#define DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1
+#define DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x4
+#define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2
+#define DCP_GSL_CONTROL__DCP_GSL_MODE_MASK 0x300
+#define DCP_GSL_CONTROL__DCP_GSL_MODE__SHIFT 0x8
+#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0xf000
+#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0xc
+#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x10000
+#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x10
+#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x3000000
+#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18
+#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x8000000
+#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b
+#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xf0000000
+#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c
+#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0xf
+#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0
+#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0xf0
+#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4
+#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE_MASK 0x1
+#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE__SHIFT 0x0
+#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00
+#define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8
+#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN_MASK 0x1
+#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN__SHIFT 0x0
+#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE_MASK 0x300
+#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE__SHIFT 0x8
+#define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING_MASK 0x10000
+#define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING__SHIFT 0x10
+#define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING_MASK 0x20000
+#define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING__SHIFT 0x11
+#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000
+#define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
+#define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff
+#define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK 0xff
+#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT 0x0
+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1
+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0
+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x300
+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8
+#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000
+#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10
+#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000
+#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11
+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000
+#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c
+#define DCP_DEBUG2__DCP_DEBUG2_MASK 0xffffffff
+#define DCP_DEBUG2__DCP_DEBUG2__SHIFT 0x0
+#define HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x7
+#define HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x1
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x2
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x1fff0
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4
+#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x7
+#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0
+#define REGAMMA_CONTROL__OVL_REGAMMA_MODE_MASK 0x70
+#define REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT 0x4
+#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x1ff
+#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0
+#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x7ffff
+#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0
+#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x7
+#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0
+#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x3ffff
+#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0
+#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000
+#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
+#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0xffff
+#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0
+#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff
+#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000
+#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x3ffff
+#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0
+#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000
+#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14
+#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff
+#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0
+#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0xffff
+#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0
+#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff
+#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0
+#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000
+#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x1ff
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000
+#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c
+#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x1
+#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0
+#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x2
+#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1
+#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xffffff00
+#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8
+#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0xff
+#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0xfffff
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x1000000
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x2000000
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x4000000
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000
+#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e
+#define DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x7
+#define DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0
+#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x70
+#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4
+#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x100
+#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8
+#define DIG_FE_CNTL__DIG_START_MASK 0x400
+#define DIG_FE_CNTL__DIG_START__SHIFT 0xa
+#define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x10000
+#define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x10
+#define DIG_FE_CNTL__DIG_SWAP_MASK 0x40000
+#define DIG_FE_CNTL__DIG_SWAP__SHIFT 0x12
+#define DIG_FE_CNTL__DIG_RB_SWITCH_EN_MASK 0x100000
+#define DIG_FE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x14
+#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x1000000
+#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18
+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x1
+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0
+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x10
+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4
+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x300
+#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8
+#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3fffffff
+#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0
+#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x3ff
+#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0
+#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x1
+#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0
+#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x2
+#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1
+#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA_MASK 0x4
+#define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA__SHIFT 0x2
+#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x10
+#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4
+#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x20
+#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5
+#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x40
+#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6
+#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN_MASK 0x100
+#define DIG_TEST_PATTERN__LVDS_EYE_PATTERN__SHIFT 0x8
+#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x3ff0000
+#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10
+#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0xffffff
+#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0
+#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x1000000
+#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18
+#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x1
+#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0
+#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
+#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0xfc
+#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x100
+#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8
+#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00
+#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x1f0000
+#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x3c00000
+#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000
+#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d
+#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000
+#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000
+#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK 0x1
+#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT 0x0
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK 0x1
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT 0x0
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK 0x10
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT 0x4
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK 0x100
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT 0x8
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK 0x1000
+#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0xc
+#define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x1
+#define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0
+#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x10
+#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4
+#define HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x100
+#define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8
+#define HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x200
+#define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9
+#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x1000000
+#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18
+#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000
+#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c
+#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x1
+#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0
+#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x10000
+#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10
+#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x100000
+#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14
+#define HDMI_STATUS__HDMI_ERROR_INT_MASK 0x8000000
+#define HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b
+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x30
+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4
+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x100
+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8
+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x1f0000
+#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x1
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x2
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x30
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x100
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x1000
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x70000
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000
+#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f
+#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x1
+#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0
+#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x10
+#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4
+#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x20
+#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5
+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x100
+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8
+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x200
+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9
+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x3f0000
+#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x1
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x2
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x10
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x20
+#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5
+#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x100
+#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8
+#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x200
+#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9
+#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x3f
+#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0
+#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x3f00
+#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8
+#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x3f0000
+#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x1
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x2
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x10
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x20
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x3f0000
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3f000000
+#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18
+#define HDMI_GC__HDMI_GC_AVMUTE_MASK 0x1
+#define HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0
+#define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x4
+#define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2
+#define HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x10
+#define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4
+#define HDMI_GC__HDMI_PACKING_PHASE_MASK 0xf00
+#define HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8
+#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x1000
+#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x1
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x2
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0xff00
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0xff0000
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x1000000
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000
+#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c
+#define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x7
+#define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0
+#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x40
+#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6
+#define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x80
+#define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0xff
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0xff00
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0xff0000
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xff000000
+#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0xff
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0xff00
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0xff0000
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xff000000
+#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0xff
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0xff00
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0xff0000
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xff000000
+#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0xff
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0xff00
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0xff0000
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xff000000
+#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0xff
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0xff00
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0xff0000
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xff000000
+#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0xff
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0xff00
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0xff0000
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xff000000
+#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0xff
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0xff00
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0xff0000
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xff000000
+#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0xff
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0xff00
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0xff0000
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xff000000
+#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0xff
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x300
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0xc00
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x1000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x6000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD_MASK 0x8000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD__SHIFT 0xf
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0xf0000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x300000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0xc00000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x3000000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0xc000000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000
+#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x7f
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD_MASK 0x80
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD__SHIFT 0x7
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0xf00
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x3000
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0xc000
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xffff0000
+#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10
+#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0xffff
+#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0
+#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xffff0000
+#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10
+#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0xffff
+#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0
+#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xff000000
+#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0xff
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0xff00
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0xff0000
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xff000000
+#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18
+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0xff
+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0
+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x300
+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8
+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x1000
+#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0xff
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0xff00
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0xff0000
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xff000000
+#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0xff
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0xff00
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0xff0000
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xff000000
+#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0xff
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0xff00
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0xff0000
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xff000000
+#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0xff
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0xff00
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0xff0000
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xff000000
+#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0xff
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0xff00
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0xff0000
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xff000000
+#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0xff
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0xff00
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0xff0000
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xff000000
+#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0xff
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0xff00
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0xff0000
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xff000000
+#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0xff
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0xff00
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0xff0000
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xff000000
+#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0xff
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0xff00
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0xff0000
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xff000000
+#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x1
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x2
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x10
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x20
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x3f0000
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3f000000
+#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18
+#define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xfffff000
+#define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc
+#define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0xfffff
+#define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0
+#define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xfffff000
+#define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc
+#define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0xfffff
+#define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0
+#define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xfffff000
+#define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc
+#define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0xfffff
+#define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0
+#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xfffff000
+#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc
+#define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0xfffff
+#define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0xff
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x700
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x7800
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0xff0000
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1f000000
+#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0xff
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x7800
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x8000
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x30000
+#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10
+#define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x1
+#define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0
+#define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x2
+#define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1
+#define AFMT_60958_0__AFMT_60958_CS_C_MASK 0x4
+#define AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2
+#define AFMT_60958_0__AFMT_60958_CS_D_MASK 0x38
+#define AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3
+#define AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0xc0
+#define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6
+#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0xff00
+#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8
+#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0xf0000
+#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10
+#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0xf00000
+#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14
+#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0xf000000
+#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18
+#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000
+#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c
+#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0xf
+#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0
+#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf0
+#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4
+#define AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x10000
+#define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10
+#define AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x40000
+#define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12
+#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0xf00000
+#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x1
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x10
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x100
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0xf000
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xffff0000
+#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10
+#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0xffffff
+#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0
+#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000
+#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f
+#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0xffffff
+#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0
+#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xff000000
+#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18
+#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0xffffff
+#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0
+#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0xffffff
+#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0xf
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0xf00
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0xf000
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0xf0000
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0xf00000
+#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14
+#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x1
+#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0
+#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xffffff00
+#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8
+#define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x10
+#define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4
+#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x100
+#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8
+#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x1000000
+#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18
+#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000
+#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x1
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x800
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x1000
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x4000
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x800000
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x1000000
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x4000000
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000
+#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f
+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x4
+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2
+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x8
+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3
+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xc0000000
+#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e
+#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x40
+#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6
+#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x80
+#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7
+#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x400
+#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa
+#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x7
+#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x7
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x0
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x100
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x8
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x7000
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0xc
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x70000
+#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x10
+#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x7f00
+#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8
+#define DIG_BE_CNTL__DIG_MODE_MASK 0x70000
+#define DIG_BE_CNTL__DIG_MODE__SHIFT 0x10
+#define DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000
+#define DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c
+#define DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x1
+#define DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0
+#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x100
+#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8
+#define TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x1
+#define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0
+#define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10
+#define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x4
+#define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x300
+#define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x8
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x1
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x2
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x4
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x8
+#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3
+#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x3
+#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0
+#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x300
+#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8
+#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x3
+#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0
+#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x3ff
+#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0
+#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x3ff0000
+#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10
+#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x3ff
+#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0
+#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x3ff0000
+#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10
+#define TMDS_DEBUG__TMDS_DEBUG_EN_MASK 0x1
+#define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT 0x0
+#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK 0x100
+#define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT 0x8
+#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK 0x200
+#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT 0x9
+#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK 0x10000
+#define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT 0x10
+#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK 0x20000
+#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT 0x11
+#define TMDS_DEBUG__TMDS_DEBUG_DE_MASK 0x1000000
+#define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT 0x18
+#define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK 0x2000000
+#define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT 0x19
+#define TMDS_CTL_BITS__TMDS_CTL0_MASK 0x1
+#define TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0
+#define TMDS_CTL_BITS__TMDS_CTL1_MASK 0x100
+#define TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8
+#define TMDS_CTL_BITS__TMDS_CTL2_MASK 0x10000
+#define TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10
+#define TMDS_CTL_BITS__TMDS_CTL3_MASK 0x1000000
+#define TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x1
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0
+#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x70
+#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x100
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0xf0000
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x1000000
+#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0xf
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x70
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x80
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x300
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x400
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x800
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x1000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0xf0000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x700000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x800000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x3000000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x4000000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x8000000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000
+#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0xf
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x70
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x80
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x300
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x400
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x800
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x1000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0xf0000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x700000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x800000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x3000000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x4000000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x8000000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000
+#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c
+#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE_MASK 0x1
+#define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE__SHIFT 0x0
+#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT_MASK 0x10
+#define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT__SHIFT 0x4
+#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE_MASK 0x100
+#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE__SHIFT 0x8
+#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS_MASK 0x200
+#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS__SHIFT 0x9
+#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS_MASK 0x400
+#define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS__SHIFT 0xa
+#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS_MASK 0x7000
+#define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS__SHIFT 0xc
+#define LVDS_DATA_CNTL__LVDS_FP_POL_MASK 0x10000
+#define LVDS_DATA_CNTL__LVDS_FP_POL__SHIFT 0x10
+#define LVDS_DATA_CNTL__LVDS_LP_POL_MASK 0x20000
+#define LVDS_DATA_CNTL__LVDS_LP_POL__SHIFT 0x11
+#define LVDS_DATA_CNTL__LVDS_DTMG_POL_MASK 0x40000
+#define LVDS_DATA_CNTL__LVDS_DTMG_POL__SHIFT 0x12
+#define DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x1
+#define DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0
+#define DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x2
+#define DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1
+#define DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x4
+#define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2
+#define DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x8
+#define DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3
+#define DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x100
+#define DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8
+#define DOUT_SCRATCH0__DOUT_SCRATCH0_MASK 0xffffffff
+#define DOUT_SCRATCH0__DOUT_SCRATCH0__SHIFT 0x0
+#define DOUT_SCRATCH1__DOUT_SCRATCH1_MASK 0xffffffff
+#define DOUT_SCRATCH1__DOUT_SCRATCH1__SHIFT 0x0
+#define DOUT_SCRATCH2__DOUT_SCRATCH2_MASK 0xffffffff
+#define DOUT_SCRATCH2__DOUT_SCRATCH2__SHIFT 0x0
+#define DOUT_SCRATCH3__DOUT_SCRATCH3_MASK 0xffffffff
+#define DOUT_SCRATCH3__DOUT_SCRATCH3__SHIFT 0x0
+#define DOUT_SCRATCH4__DOUT_SCRATCH4_MASK 0xffffffff
+#define DOUT_SCRATCH4__DOUT_SCRATCH4__SHIFT 0x0
+#define DOUT_SCRATCH5__DOUT_SCRATCH5_MASK 0xffffffff
+#define DOUT_SCRATCH5__DOUT_SCRATCH5__SHIFT 0x0
+#define DOUT_SCRATCH6__DOUT_SCRATCH6_MASK 0xffffffff
+#define DOUT_SCRATCH6__DOUT_SCRATCH6__SHIFT 0x0
+#define DOUT_SCRATCH7__DOUT_SCRATCH7_MASK 0xffffffff
+#define DOUT_SCRATCH7__DOUT_SCRATCH7__SHIFT 0x0
+#define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x7
+#define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x0
+#define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x70
+#define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x4
+#define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS_MASK 0x1
+#define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS__SHIFT 0x0
+#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK 0x2
+#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE__SHIFT 0x1
+#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED_MASK 0x10
+#define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED__SHIFT 0x4
+#define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS_MASK 0x100
+#define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS__SHIFT 0x8
+#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000
+#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000
+#define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK 0x1
+#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK__SHIFT 0x0
+#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK 0x100
+#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY__SHIFT 0x8
+#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK 0x10000
+#define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN__SHIFT 0x10
+#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK 0x100000
+#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK__SHIFT 0x14
+#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK 0x1000000
+#define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN__SHIFT 0x18
+#define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER_MASK 0x1fff
+#define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT 0x0
+#define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER_MASK 0x3ff0000
+#define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT 0x10
+#define DC_HPD1_CONTROL__DC_HPD1_EN_MASK 0x10000000
+#define DC_HPD1_CONTROL__DC_HPD1_EN__SHIFT 0x1c
+#define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS_MASK 0x1
+#define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS__SHIFT 0x0
+#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK 0x2
+#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE__SHIFT 0x1
+#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED_MASK 0x10
+#define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED__SHIFT 0x4
+#define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS_MASK 0x100
+#define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS__SHIFT 0x8
+#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000
+#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000
+#define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK_MASK 0x1
+#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK__SHIFT 0x0
+#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK 0x100
+#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY__SHIFT 0x8
+#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN_MASK 0x10000
+#define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN__SHIFT 0x10
+#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK_MASK 0x100000
+#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK__SHIFT 0x14
+#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN_MASK 0x1000000
+#define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN__SHIFT 0x18
+#define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER_MASK 0x1fff
+#define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER__SHIFT 0x0
+#define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER_MASK 0x3ff0000
+#define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER__SHIFT 0x10
+#define DC_HPD2_CONTROL__DC_HPD2_EN_MASK 0x10000000
+#define DC_HPD2_CONTROL__DC_HPD2_EN__SHIFT 0x1c
+#define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS_MASK 0x1
+#define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS__SHIFT 0x0
+#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK 0x2
+#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE__SHIFT 0x1
+#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED_MASK 0x10
+#define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED__SHIFT 0x4
+#define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS_MASK 0x100
+#define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS__SHIFT 0x8
+#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000
+#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000
+#define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK_MASK 0x1
+#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK__SHIFT 0x0
+#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK 0x100
+#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY__SHIFT 0x8
+#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN_MASK 0x10000
+#define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN__SHIFT 0x10
+#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK_MASK 0x100000
+#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK__SHIFT 0x14
+#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN_MASK 0x1000000
+#define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN__SHIFT 0x18
+#define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER_MASK 0x1fff
+#define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER__SHIFT 0x0
+#define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER_MASK 0x3ff0000
+#define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER__SHIFT 0x10
+#define DC_HPD3_CONTROL__DC_HPD3_EN_MASK 0x10000000
+#define DC_HPD3_CONTROL__DC_HPD3_EN__SHIFT 0x1c
+#define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS_MASK 0x1
+#define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS__SHIFT 0x0
+#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK 0x2
+#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE__SHIFT 0x1
+#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED_MASK 0x10
+#define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED__SHIFT 0x4
+#define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS_MASK 0x100
+#define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS__SHIFT 0x8
+#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000
+#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000
+#define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK_MASK 0x1
+#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK__SHIFT 0x0
+#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK 0x100
+#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY__SHIFT 0x8
+#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN_MASK 0x10000
+#define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN__SHIFT 0x10
+#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK_MASK 0x100000
+#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK__SHIFT 0x14
+#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN_MASK 0x1000000
+#define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN__SHIFT 0x18
+#define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER_MASK 0x1fff
+#define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER__SHIFT 0x0
+#define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER_MASK 0x3ff0000
+#define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER__SHIFT 0x10
+#define DC_HPD4_CONTROL__DC_HPD4_EN_MASK 0x10000000
+#define DC_HPD4_CONTROL__DC_HPD4_EN__SHIFT 0x1c
+#define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS_MASK 0x1
+#define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS__SHIFT 0x0
+#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK 0x2
+#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE__SHIFT 0x1
+#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED_MASK 0x10
+#define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED__SHIFT 0x4
+#define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS_MASK 0x100
+#define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS__SHIFT 0x8
+#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000
+#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000
+#define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK_MASK 0x1
+#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK__SHIFT 0x0
+#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK 0x100
+#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY__SHIFT 0x8
+#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN_MASK 0x10000
+#define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN__SHIFT 0x10
+#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK_MASK 0x100000
+#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK__SHIFT 0x14
+#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN_MASK 0x1000000
+#define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN__SHIFT 0x18
+#define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER_MASK 0x1fff
+#define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER__SHIFT 0x0
+#define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER_MASK 0x3ff0000
+#define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER__SHIFT 0x10
+#define DC_HPD5_CONTROL__DC_HPD5_EN_MASK 0x10000000
+#define DC_HPD5_CONTROL__DC_HPD5_EN__SHIFT 0x1c
+#define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS_MASK 0x1
+#define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS__SHIFT 0x0
+#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK 0x2
+#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE__SHIFT 0x1
+#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED_MASK 0x10
+#define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED__SHIFT 0x4
+#define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS_MASK 0x100
+#define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS__SHIFT 0x8
+#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000
+#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc
+#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000
+#define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18
+#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK_MASK 0x1
+#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK__SHIFT 0x0
+#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK 0x100
+#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY__SHIFT 0x8
+#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN_MASK 0x10000
+#define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN__SHIFT 0x10
+#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK_MASK 0x100000
+#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK__SHIFT 0x14
+#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN_MASK 0x1000000
+#define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN__SHIFT 0x18
+#define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER_MASK 0x1fff
+#define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER__SHIFT 0x0
+#define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER_MASK 0x3ff0000
+#define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER__SHIFT 0x10
+#define DC_HPD6_CONTROL__DC_HPD6_EN_MASK 0x10000000
+#define DC_HPD6_CONTROL__DC_HPD6_EN__SHIFT 0x1c
+#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY_MASK 0xff
+#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000
+#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN_MASK 0x1000000
+#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN__SHIFT 0x18
+#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN_MASK 0x10000000
+#define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY_MASK 0xff
+#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000
+#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN_MASK 0x1000000
+#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN__SHIFT 0x18
+#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN_MASK 0x10000000
+#define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY_MASK 0xff
+#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000
+#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN_MASK 0x1000000
+#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN__SHIFT 0x18
+#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN_MASK 0x10000000
+#define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY_MASK 0xff
+#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000
+#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN_MASK 0x1000000
+#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN__SHIFT 0x18
+#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN_MASK 0x10000000
+#define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY_MASK 0xff
+#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000
+#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN_MASK 0x1000000
+#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN__SHIFT 0x18
+#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN_MASK 0x10000000
+#define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY_MASK 0xff
+#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY__SHIFT 0x0
+#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000
+#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc
+#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN_MASK 0x1000000
+#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN__SHIFT 0x18
+#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN_MASK 0x10000000
+#define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c
+#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY_MASK 0xff
+#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY__SHIFT 0x0
+#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY_MASK 0xff00000
+#define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY__SHIFT 0x14
+#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY_MASK 0xff
+#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY__SHIFT 0x0
+#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY_MASK 0xff00000
+#define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY__SHIFT 0x14
+#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY_MASK 0xff
+#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY__SHIFT 0x0
+#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY_MASK 0xff00000
+#define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY__SHIFT 0x14
+#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY_MASK 0xff
+#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY__SHIFT 0x0
+#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY_MASK 0xff00000
+#define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY__SHIFT 0x14
+#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY_MASK 0xff
+#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY__SHIFT 0x0
+#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY_MASK 0xff00000
+#define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY__SHIFT 0x14
+#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY_MASK 0xff
+#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY__SHIFT 0x0
+#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY_MASK 0xff00000
+#define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY__SHIFT 0x14
+#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x1
+#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x2
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x4
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x8
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x700
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x300000
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14
+#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000
+#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x1f
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x3
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0xc
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x10
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x100
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x1000
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x100000
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x200000
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x1000000
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x2000000
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x1
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x2
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x4
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x10
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x20
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x40
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x100
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x200
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x400
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x1000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x2000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x4000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x10000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x20000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x40000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x100000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x200000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x400000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x1000000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x2000000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x4000000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x8000000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x3
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x4
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x10
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x20
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x40
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x80
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x100
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x1000
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x2000
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x4000
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x8000
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x40000
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x3
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x8
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x10000
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x20000
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x100000
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x3
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x8
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x10000
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x20000
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x100000
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x3
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x8
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x10000
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x20000
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x100000
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x3
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x8
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x10000
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x20000
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x100000
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x3
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x8
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x10000
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x20000
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x100000
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x3
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x8
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x10000
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x20000
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x11
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x100000
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000
+#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x3
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xffff0000
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x1
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x2
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x10
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x20
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x40
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x80
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0xff00
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0xff0000
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xff000000
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x3
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xffff0000
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x1
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x2
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x10
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x20
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x40
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x80
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0xff00
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0xff0000
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xff000000
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x3
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xffff0000
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x1
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x2
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x10
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x20
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x40
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x80
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0xff00
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0xff0000
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xff000000
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x3
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xffff0000
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x1
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x2
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x10
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x20
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x40
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x80
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0xff00
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0xff0000
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xff000000
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x3
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xffff0000
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x1
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x2
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x10
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x20
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x40
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x80
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0xff00
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0xff0000
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xff000000
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x3
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xffff0000
+#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x1
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x2
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x10
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x20
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x40
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x6
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x80
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0xff00
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0xff0000
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xff000000
+#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x1
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x100
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8
+#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x1000
+#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x2000
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0xff0000
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x1
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x100
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8
+#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x1000
+#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x2000
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0xff0000
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x1
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x100
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8
+#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x1000
+#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x2000
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0xff0000
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x1
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x100
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8
+#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x1000
+#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x2000
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0xff0000
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10
+#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x1
+#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0
+#define DC_I2C_DATA__DC_I2C_DATA_MASK 0xff00
+#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8
+#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0xff0000
+#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x1
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x0
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x2
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x1
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x4
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x2
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x8
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x3
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK 0x80000000
+#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT 0x1f
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x1
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x0
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x2
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x1
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x4
+#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x2
+#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0xf
+#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x0
+#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x10
+#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x4
+#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x20
+#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x5
+#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x40
+#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x6
+#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x200
+#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x9
+#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x400
+#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0xa
+#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x3
+#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x0
+#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xffff0000
+#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x10
+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x1
+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x0
+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x2
+#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x1
+#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x80
+#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x7
+#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0xff00
+#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x8
+#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xff000000
+#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x18
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x1
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x0
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x100
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x8
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x200
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x9
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x1000
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0xc
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x2000
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0xd
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0xf0000
+#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x10
+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x1
+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x0
+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0xff00
+#define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x8
+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0xf0000
+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x10
+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000
+#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x1f
+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x7f
+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x0
+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x7f00
+#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x8
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK 0x1
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT 0x0
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK 0x2
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT 0x1
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK 0x4
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT 0x2
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK 0x10
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT 0x4
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK 0x20
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT 0x5
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK 0x40
+#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
+#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x1000000
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT_MASK 0x1000000
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_HOST_CONFLICT_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_HOST_CONFLICT_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_DATA_OVERFLOW_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_DATA_OVERFLOW_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x1000000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT_MASK 0x800
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER0_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER2_INTERRUPT_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER3_INTERRUPT_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT_MASK 0x800
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER4_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER5_INTERRUPT_MASK 0x10000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER6_INTERRUPT_MASK 0x20000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER7_INTERRUPT_MASK 0x40000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT_MASK 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT_MASK 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT_MASK 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT_MASK 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT_MASK 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT_MASK 0x20
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT_MASK 0x40
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT_MASK 0x80
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT_MASK 0x200
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT_MASK 0x400
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT_MASK 0x800
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE9__SCANIN_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x8000000
+#define DISP_INTERRUPT_STATUS_CONTINUE9__SCANIN_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1b
+#define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x1
+#define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0
+#define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x100
+#define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8
+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK_MASK 0x8000000
+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK__SHIFT 0x1b
+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define DISP_TIMER_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x3
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x0
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x8
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x3
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x10000
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x10
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x20000
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x11
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x100000
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x14
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000
+#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x1c
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x3
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x0
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x10
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x4
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xffff0000
+#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x10
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x1
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x0
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x2
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x1
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x10
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x4
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x20
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x5
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x40
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x6
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x80
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x7
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0xff00
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x8
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0xff0000
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x10
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xff000000
+#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x18
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0xffff
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0xf00000
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c
+#define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x7
+#define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x0
+#define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x70000
+#define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x10
+#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX_MASK 0xff
+#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA__SHIFT 0x0
+#define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A_MASK 0xffffffff
+#define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A__SHIFT 0x0
+#define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B_MASK 0xffffffff
+#define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B__SHIFT 0x0
+#define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C_MASK 0xffffffff
+#define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C__SHIFT 0x0
+#define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D_MASK 0xffffffff
+#define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D__SHIFT 0x0
+#define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E_MASK 0xffffffff
+#define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E__SHIFT 0x0
+#define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F_MASK 0xffffffff
+#define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F__SHIFT 0x0
+#define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G_MASK 0xffffffff
+#define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G__SHIFT 0x0
+#define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H_MASK 0xffffffff
+#define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H__SHIFT 0x0
+#define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I_MASK 0xffffffff
+#define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I__SHIFT 0x0
+#define DP_AUX1_DEBUG_J__DP_AUX1_DEBUG_J_MASK 0xffffffff
+#define DP_AUX1_DEBUG_J__DP_AUX1_DEBUG_J__SHIFT 0x0
+#define DP_AUX1_DEBUG_K__DP_AUX1_DEBUG_K_MASK 0xffffffff
+#define DP_AUX1_DEBUG_K__DP_AUX1_DEBUG_K__SHIFT 0x0
+#define DP_AUX1_DEBUG_L__DP_AUX1_DEBUG_L_MASK 0xffffffff
+#define DP_AUX1_DEBUG_L__DP_AUX1_DEBUG_L__SHIFT 0x0
+#define DP_AUX1_DEBUG_M__DP_AUX1_DEBUG_M_MASK 0xffffffff
+#define DP_AUX1_DEBUG_M__DP_AUX1_DEBUG_M__SHIFT 0x0
+#define DP_AUX1_DEBUG_N__DP_AUX1_DEBUG_N_MASK 0xffffffff
+#define DP_AUX1_DEBUG_N__DP_AUX1_DEBUG_N__SHIFT 0x0
+#define DP_AUX1_DEBUG_O__DP_AUX1_DEBUG_O_MASK 0xffffffff
+#define DP_AUX1_DEBUG_O__DP_AUX1_DEBUG_O__SHIFT 0x0
+#define DP_AUX1_DEBUG_P__DP_AUX1_DEBUG_P_MASK 0xffffffff
+#define DP_AUX1_DEBUG_P__DP_AUX1_DEBUG_P__SHIFT 0x0
+#define DP_AUX1_DEBUG_Q__DP_AUX1_DEBUG_Q_MASK 0xffffffff
+#define DP_AUX1_DEBUG_Q__DP_AUX1_DEBUG_Q__SHIFT 0x0
+#define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A_MASK 0xffffffff
+#define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A__SHIFT 0x0
+#define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B_MASK 0xffffffff
+#define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B__SHIFT 0x0
+#define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C_MASK 0xffffffff
+#define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C__SHIFT 0x0
+#define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D_MASK 0xffffffff
+#define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D__SHIFT 0x0
+#define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E_MASK 0xffffffff
+#define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E__SHIFT 0x0
+#define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F_MASK 0xffffffff
+#define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F__SHIFT 0x0
+#define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G_MASK 0xffffffff
+#define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G__SHIFT 0x0
+#define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H_MASK 0xffffffff
+#define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H__SHIFT 0x0
+#define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I_MASK 0xffffffff
+#define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I__SHIFT 0x0
+#define DP_AUX2_DEBUG_J__DP_AUX2_DEBUG_J_MASK 0xffffffff
+#define DP_AUX2_DEBUG_J__DP_AUX2_DEBUG_J__SHIFT 0x0
+#define DP_AUX2_DEBUG_K__DP_AUX2_DEBUG_K_MASK 0xffffffff
+#define DP_AUX2_DEBUG_K__DP_AUX2_DEBUG_K__SHIFT 0x0
+#define DP_AUX2_DEBUG_L__DP_AUX2_DEBUG_L_MASK 0xffffffff
+#define DP_AUX2_DEBUG_L__DP_AUX2_DEBUG_L__SHIFT 0x0
+#define DP_AUX2_DEBUG_M__DP_AUX2_DEBUG_M_MASK 0xffffffff
+#define DP_AUX2_DEBUG_M__DP_AUX2_DEBUG_M__SHIFT 0x0
+#define DP_AUX2_DEBUG_N__DP_AUX2_DEBUG_N_MASK 0xffffffff
+#define DP_AUX2_DEBUG_N__DP_AUX2_DEBUG_N__SHIFT 0x0
+#define DP_AUX2_DEBUG_O__DP_AUX2_DEBUG_O_MASK 0xffffffff
+#define DP_AUX2_DEBUG_O__DP_AUX2_DEBUG_O__SHIFT 0x0
+#define DP_AUX2_DEBUG_P__DP_AUX2_DEBUG_P_MASK 0xffffffff
+#define DP_AUX2_DEBUG_P__DP_AUX2_DEBUG_P__SHIFT 0x0
+#define DP_AUX2_DEBUG_Q__DP_AUX2_DEBUG_Q_MASK 0xffffffff
+#define DP_AUX2_DEBUG_Q__DP_AUX2_DEBUG_Q__SHIFT 0x0
+#define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A_MASK 0xffffffff
+#define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A__SHIFT 0x0
+#define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B_MASK 0xffffffff
+#define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B__SHIFT 0x0
+#define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C_MASK 0xffffffff
+#define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C__SHIFT 0x0
+#define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D_MASK 0xffffffff
+#define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D__SHIFT 0x0
+#define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E_MASK 0xffffffff
+#define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E__SHIFT 0x0
+#define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F_MASK 0xffffffff
+#define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F__SHIFT 0x0
+#define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G_MASK 0xffffffff
+#define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G__SHIFT 0x0
+#define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H_MASK 0xffffffff
+#define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H__SHIFT 0x0
+#define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I_MASK 0xffffffff
+#define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I__SHIFT 0x0
+#define DP_AUX3_DEBUG_J__DP_AUX3_DEBUG_J_MASK 0xffffffff
+#define DP_AUX3_DEBUG_J__DP_AUX3_DEBUG_J__SHIFT 0x0
+#define DP_AUX3_DEBUG_K__DP_AUX3_DEBUG_K_MASK 0xffffffff
+#define DP_AUX3_DEBUG_K__DP_AUX3_DEBUG_K__SHIFT 0x0
+#define DP_AUX3_DEBUG_L__DP_AUX3_DEBUG_L_MASK 0xffffffff
+#define DP_AUX3_DEBUG_L__DP_AUX3_DEBUG_L__SHIFT 0x0
+#define DP_AUX3_DEBUG_M__DP_AUX3_DEBUG_M_MASK 0xffffffff
+#define DP_AUX3_DEBUG_M__DP_AUX3_DEBUG_M__SHIFT 0x0
+#define DP_AUX3_DEBUG_N__DP_AUX3_DEBUG_N_MASK 0xffffffff
+#define DP_AUX3_DEBUG_N__DP_AUX3_DEBUG_N__SHIFT 0x0
+#define DP_AUX3_DEBUG_O__DP_AUX3_DEBUG_O_MASK 0xffffffff
+#define DP_AUX3_DEBUG_O__DP_AUX3_DEBUG_O__SHIFT 0x0
+#define DP_AUX3_DEBUG_P__DP_AUX3_DEBUG_P_MASK 0xffffffff
+#define DP_AUX3_DEBUG_P__DP_AUX3_DEBUG_P__SHIFT 0x0
+#define DP_AUX3_DEBUG_Q__DP_AUX3_DEBUG_Q_MASK 0xffffffff
+#define DP_AUX3_DEBUG_Q__DP_AUX3_DEBUG_Q__SHIFT 0x0
+#define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A_MASK 0xffffffff
+#define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A__SHIFT 0x0
+#define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B_MASK 0xffffffff
+#define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B__SHIFT 0x0
+#define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C_MASK 0xffffffff
+#define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C__SHIFT 0x0
+#define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D_MASK 0xffffffff
+#define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D__SHIFT 0x0
+#define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E_MASK 0xffffffff
+#define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E__SHIFT 0x0
+#define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F_MASK 0xffffffff
+#define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F__SHIFT 0x0
+#define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G_MASK 0xffffffff
+#define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G__SHIFT 0x0
+#define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H_MASK 0xffffffff
+#define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H__SHIFT 0x0
+#define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I_MASK 0xffffffff
+#define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I__SHIFT 0x0
+#define DP_AUX4_DEBUG_J__DP_AUX4_DEBUG_J_MASK 0xffffffff
+#define DP_AUX4_DEBUG_J__DP_AUX4_DEBUG_J__SHIFT 0x0
+#define DP_AUX4_DEBUG_K__DP_AUX4_DEBUG_K_MASK 0xffffffff
+#define DP_AUX4_DEBUG_K__DP_AUX4_DEBUG_K__SHIFT 0x0
+#define DP_AUX4_DEBUG_L__DP_AUX4_DEBUG_L_MASK 0xffffffff
+#define DP_AUX4_DEBUG_L__DP_AUX4_DEBUG_L__SHIFT 0x0
+#define DP_AUX4_DEBUG_M__DP_AUX4_DEBUG_M_MASK 0xffffffff
+#define DP_AUX4_DEBUG_M__DP_AUX4_DEBUG_M__SHIFT 0x0
+#define DP_AUX4_DEBUG_N__DP_AUX4_DEBUG_N_MASK 0xffffffff
+#define DP_AUX4_DEBUG_N__DP_AUX4_DEBUG_N__SHIFT 0x0
+#define DP_AUX4_DEBUG_O__DP_AUX4_DEBUG_O_MASK 0xffffffff
+#define DP_AUX4_DEBUG_O__DP_AUX4_DEBUG_O__SHIFT 0x0
+#define DP_AUX4_DEBUG_P__DP_AUX4_DEBUG_P_MASK 0xffffffff
+#define DP_AUX4_DEBUG_P__DP_AUX4_DEBUG_P__SHIFT 0x0
+#define DP_AUX4_DEBUG_Q__DP_AUX4_DEBUG_Q_MASK 0xffffffff
+#define DP_AUX4_DEBUG_Q__DP_AUX4_DEBUG_Q__SHIFT 0x0
+#define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A_MASK 0xffffffff
+#define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A__SHIFT 0x0
+#define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B_MASK 0xffffffff
+#define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B__SHIFT 0x0
+#define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C_MASK 0xffffffff
+#define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C__SHIFT 0x0
+#define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D_MASK 0xffffffff
+#define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D__SHIFT 0x0
+#define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E_MASK 0xffffffff
+#define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E__SHIFT 0x0
+#define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F_MASK 0xffffffff
+#define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F__SHIFT 0x0
+#define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G_MASK 0xffffffff
+#define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G__SHIFT 0x0
+#define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H_MASK 0xffffffff
+#define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H__SHIFT 0x0
+#define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I_MASK 0xffffffff
+#define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I__SHIFT 0x0
+#define DP_AUX5_DEBUG_J__DP_AUX5_DEBUG_J_MASK 0xffffffff
+#define DP_AUX5_DEBUG_J__DP_AUX5_DEBUG_J__SHIFT 0x0
+#define DP_AUX5_DEBUG_K__DP_AUX5_DEBUG_K_MASK 0xffffffff
+#define DP_AUX5_DEBUG_K__DP_AUX5_DEBUG_K__SHIFT 0x0
+#define DP_AUX5_DEBUG_L__DP_AUX5_DEBUG_L_MASK 0xffffffff
+#define DP_AUX5_DEBUG_L__DP_AUX5_DEBUG_L__SHIFT 0x0
+#define DP_AUX5_DEBUG_M__DP_AUX5_DEBUG_M_MASK 0xffffffff
+#define DP_AUX5_DEBUG_M__DP_AUX5_DEBUG_M__SHIFT 0x0
+#define DP_AUX5_DEBUG_N__DP_AUX5_DEBUG_N_MASK 0xffffffff
+#define DP_AUX5_DEBUG_N__DP_AUX5_DEBUG_N__SHIFT 0x0
+#define DP_AUX5_DEBUG_O__DP_AUX5_DEBUG_O_MASK 0xffffffff
+#define DP_AUX5_DEBUG_O__DP_AUX5_DEBUG_O__SHIFT 0x0
+#define DP_AUX5_DEBUG_P__DP_AUX5_DEBUG_P_MASK 0xffffffff
+#define DP_AUX5_DEBUG_P__DP_AUX5_DEBUG_P__SHIFT 0x0
+#define DP_AUX5_DEBUG_Q__DP_AUX5_DEBUG_Q_MASK 0xffffffff
+#define DP_AUX5_DEBUG_Q__DP_AUX5_DEBUG_Q__SHIFT 0x0
+#define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A_MASK 0xffffffff
+#define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A__SHIFT 0x0
+#define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B_MASK 0xffffffff
+#define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B__SHIFT 0x0
+#define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C_MASK 0xffffffff
+#define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C__SHIFT 0x0
+#define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D_MASK 0xffffffff
+#define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D__SHIFT 0x0
+#define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E_MASK 0xffffffff
+#define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E__SHIFT 0x0
+#define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F_MASK 0xffffffff
+#define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F__SHIFT 0x0
+#define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G_MASK 0xffffffff
+#define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G__SHIFT 0x0
+#define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H_MASK 0xffffffff
+#define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H__SHIFT 0x0
+#define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I_MASK 0xffffffff
+#define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I__SHIFT 0x0
+#define DP_AUX6_DEBUG_J__DP_AUX6_DEBUG_J_MASK 0xffffffff
+#define DP_AUX6_DEBUG_J__DP_AUX6_DEBUG_J__SHIFT 0x0
+#define DP_AUX6_DEBUG_K__DP_AUX6_DEBUG_K_MASK 0xffffffff
+#define DP_AUX6_DEBUG_K__DP_AUX6_DEBUG_K__SHIFT 0x0
+#define DP_AUX6_DEBUG_L__DP_AUX6_DEBUG_L_MASK 0xffffffff
+#define DP_AUX6_DEBUG_L__DP_AUX6_DEBUG_L__SHIFT 0x0
+#define DP_AUX6_DEBUG_M__DP_AUX6_DEBUG_M_MASK 0xffffffff
+#define DP_AUX6_DEBUG_M__DP_AUX6_DEBUG_M__SHIFT 0x0
+#define DP_AUX6_DEBUG_N__DP_AUX6_DEBUG_N_MASK 0xffffffff
+#define DP_AUX6_DEBUG_N__DP_AUX6_DEBUG_N__SHIFT 0x0
+#define DP_AUX6_DEBUG_O__DP_AUX6_DEBUG_O_MASK 0xffffffff
+#define DP_AUX6_DEBUG_O__DP_AUX6_DEBUG_O__SHIFT 0x0
+#define DP_AUX6_DEBUG_P__DP_AUX6_DEBUG_P_MASK 0xffffffff
+#define DP_AUX6_DEBUG_P__DP_AUX6_DEBUG_P__SHIFT 0x0
+#define DP_AUX6_DEBUG_Q__DP_AUX6_DEBUG_Q_MASK 0xffffffff
+#define DP_AUX6_DEBUG_Q__DP_AUX6_DEBUG_Q__SHIFT 0x0
+#define DMCU_CTRL__RESET_UC_MASK 0x1
+#define DMCU_CTRL__RESET_UC__SHIFT 0x0
+#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x2
+#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1
+#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x4
+#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2
+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x8
+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3
+#define DMCU_CTRL__DMCU_ENABLE_MASK 0x10
+#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4
+#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xffc00000
+#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x16
+#define DMCU_STATUS__UC_IN_RESET_MASK 0x1
+#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0
+#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x2
+#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1
+#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x4
+#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2
+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0xff
+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0
+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0xff00
+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8
+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0xff
+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0
+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0xff00
+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8
+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0xff
+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0
+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0xff00
+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0xff
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0xff00
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8
+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xffffffff
+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0
+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xffffffff
+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0
+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x1
+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0
+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x2
+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1
+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x4
+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2
+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x8
+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3
+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x10
+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4
+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x20
+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5
+#define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT_MASK 0xff00
+#define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT__SHIFT 0x8
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0xffff
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0xf0000
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x100000
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14
+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xffffffff
+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0xffff
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0xf0000
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x100000
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14
+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xffffffff
+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0
+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x3ff
+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0
+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0xff
+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0
+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x3ff
+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0
+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0xff
+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0
+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x1
+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0
+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x7f0000
+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10
+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x800000
+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x1
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x2
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x4
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x8
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x10
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x20
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x40
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x80
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x100
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x200
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x400
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x800
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x1000
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x2000
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x4000
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x8000
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x1
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x2
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x4
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x8
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x10
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x20
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x40
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x80
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x100
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x200
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x400
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x800
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x2000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x4000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x4000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x8000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x10000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x10000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x20000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x40000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x40000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x80000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x100000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x100000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x200000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x400000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x400000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x800000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x1000000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x1000000
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x2
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x2
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x4
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x4
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2
+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x8
+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x100
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x100
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8
+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x200
+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x400
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x400
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x800
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x800
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x1000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0xc
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x1000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0xc
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x2000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0xd
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x2000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0xd
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x4000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0xe
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x4000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0xe
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x8000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0xf
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x8000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xf
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x10000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x10
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x10000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x10
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x20000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x11
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x20000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x11
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x40000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x40000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x12
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x80000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x80000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x13
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x100000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x100000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x14
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x200000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x200000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x15
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x400000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x400000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x16
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x800000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x800000
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x1000000
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x1000000
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x2000000
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x2000000
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x4000000
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x4000000
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x8000000
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x8000000
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x1
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x0
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x2
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x1
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x4
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x2
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x200
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x400
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x800
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK_MASK 0x1000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK__SHIFT 0xc
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK_MASK 0x2000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK__SHIFT 0xd
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK_MASK 0x4000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK__SHIFT 0xe
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK_MASK 0x8000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK__SHIFT 0xf
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK_MASK 0x10000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK__SHIFT 0x10
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK_MASK 0x20000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK__SHIFT 0x11
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK_MASK 0x40000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x12
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK_MASK 0x80000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x13
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK_MASK 0x100000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK__SHIFT 0x14
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK_MASK 0x200000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK__SHIFT 0x15
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK_MASK 0x400000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x16
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK_MASK 0x800000
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x17
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x4
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x100
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x1000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x2000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x4000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x8000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x10000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x20000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x40000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x80000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x100000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x200000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x400000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x800000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x1000000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x2000000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x4000000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x8000000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x4
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x100
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x1000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x2000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x4000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x8000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x20000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x40000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x80000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x100000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x200000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x400000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x800000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x1000000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x2000000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x4000000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x8000000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d
+#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xffffffff
+#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0
+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0xff
+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0
+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0xff00
+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8
+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0xff0000
+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x3
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0xc
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2
+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x7
+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0
+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x700
+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8
+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x10000
+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0xff
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0xff00
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0xff0000
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xff000000
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0xff
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0xff00
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0xff0000
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xff000000
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0xff
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0xff00
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0xff0000
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xff000000
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0xff
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0xff00
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0xff0000
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xff000000
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18
+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x1
+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0xff
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0xff00
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0xff0000
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xff000000
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0xff
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0xff00
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0xff0000
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xff000000
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0xff
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0xff00
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0xff0000
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xff000000
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0xff
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0xff00
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0xff0000
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xff000000
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18
+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x1
+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0
+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x100
+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8
+#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK 0xff
+#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER0_INT_MASK_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER1_INT_MASK_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER2_INT_MASK_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER3_INT_MASK_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER4_INT_MASK_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER5_INT_MASK_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER6_INT_MASK_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER7_INT_MASK_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER0_INT_MASK_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER1_INT_MASK_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER2_INT_MASK_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER3_INT_MASK_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER4_INT_MASK_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER5_INT_MASK_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER6_INT_MASK_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER7_INT_MASK_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_MASK_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_MASK_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_MASK_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_MASK_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_MASK_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_MASK_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_MASK_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_MASK_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_MASK_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_MASK_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_MASK_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_MASK_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_MASK_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_MASK_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_MASK_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_MASK_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_MASK_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_MASK_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_MASK_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_MASK_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_MASK_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_MASK_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_MASK_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_MASK_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_MASK_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_MASK_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_MASK_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_MASK_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_MASK_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_MASK_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_MASK_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_MASK_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_MASK_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_MASK_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_MASK_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_MASK_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_MASK_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_MASK_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_MASK_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_MASK_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_MASK_MASK 0x100
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_MASK_MASK 0x200
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_MASK_MASK 0x400
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_MASK_MASK 0x800
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_MASK_MASK 0x1000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_MASK_MASK 0x2000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_MASK_MASK 0x4000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_MASK_MASK 0x8000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_MASK_MASK 0x10000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_MASK_MASK 0x20000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_MASK_MASK 0x40000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_MASK_MASK 0x80000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_MASK_MASK 0x100000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_MASK_MASK 0x200000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_MASK_MASK 0x400000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_MASK_MASK 0x800000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_MASK_MASK 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_MASK_MASK 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_MASK_MASK 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_MASK_MASK 0x8
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_MASK_MASK 0x10
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_MASK_MASK 0x20
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_MASK_MASK 0x40
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_MASK_MASK 0x80
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000
+#define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18
+#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x10
+#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4
+#define DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x100
+#define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8
+#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x20000
+#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11
+#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x7
+#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0
+#define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x100
+#define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8
+#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x10000
+#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10
+#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x7000000
+#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18
+#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0xff
+#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0
+#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x100
+#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8
+#define DP_CONFIG__DP_UDI_LANES_MASK 0x3
+#define DP_CONFIG__DP_UDI_LANES__SHIFT 0x0
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x1
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x300
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x10000
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x100000
+#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14
+#define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x1
+#define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x10
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x20
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x40
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x80
+#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7
+#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x100
+#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8
+#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x1000
+#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc
+#define DP_MSA_MISC__DP_MSA_MISC1_MASK 0x78
+#define DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3
+#define DP_MSA_MISC__DP_MSA_MISC2_MASK 0xff00
+#define DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8
+#define DP_MSA_MISC__DP_MSA_MISC3_MASK 0xff0000
+#define DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10
+#define DP_MSA_MISC__DP_MSA_MISC4_MASK 0xff000000
+#define DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18
+#define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x1
+#define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0
+#define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x100
+#define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8
+#define DP_VID_TIMING__DP_VID_N_DIV_MASK 0xff000000
+#define DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18
+#define DP_VID_N__DP_VID_N_MASK 0xffffff
+#define DP_VID_N__DP_VID_N__SHIFT 0x0
+#define DP_VID_M__DP_VID_M_MASK 0xffffff
+#define DP_VID_M__DP_VID_M__SHIFT 0x0
+#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x3ffff
+#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0
+#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x1000000
+#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18
+#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000
+#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c
+#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x1
+#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0
+#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0xfff
+#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0
+#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x10000
+#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10
+#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x1000000
+#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18
+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x1
+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0
+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x2
+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1
+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x4
+#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x1
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x2
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x4
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x8
+#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3
+#define DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x10000
+#define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10
+#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x1000000
+#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18
+#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x3
+#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0
+#define DP_DPHY_SYM0__DPHY_SYM1_MASK 0x3ff
+#define DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0
+#define DP_DPHY_SYM0__DPHY_SYM2_MASK 0xffc00
+#define DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa
+#define DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3ff00000
+#define DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14
+#define DP_DPHY_SYM1__DPHY_SYM4_MASK 0x3ff
+#define DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0
+#define DP_DPHY_SYM1__DPHY_SYM5_MASK 0xffc00
+#define DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa
+#define DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3ff00000
+#define DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14
+#define DP_DPHY_SYM2__DPHY_SYM7_MASK 0x3ff
+#define DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0
+#define DP_DPHY_SYM2__DPHY_SYM8_MASK 0xffc00
+#define DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa
+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x100
+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8
+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x10000
+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10
+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x1000000
+#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18
+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x1
+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0
+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x30
+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4
+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00
+#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8
+#define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x1
+#define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0
+#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x10
+#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4
+#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x100
+#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8
+#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x1
+#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0
+#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x30
+#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4
+#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0xff0000
+#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0xff
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0xff00
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0xff0000
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xff000000
+#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18
+#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x3f
+#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0
+#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x3f00
+#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8
+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x1
+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0
+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x100
+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8
+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x10000
+#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10
+#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x1
+#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0
+#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x2
+#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1
+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x4
+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2
+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0xfff00
+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8
+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xfff00000
+#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x7
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x10
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x100
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x1000
+#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc
+#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x1
+#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0
+#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x1fff0
+#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4
+#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x1fff
+#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0
+#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x1fff0000
+#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10
+#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x1
+#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0
+#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x10
+#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4
+#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x100
+#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8
+#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x1000
+#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc
+#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x10000
+#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10
+#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x100000
+#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14
+#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x200000
+#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15
+#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x400000
+#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16
+#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x800000
+#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17
+#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x1000000
+#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18
+#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000
+#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c
+#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x1
+#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0
+#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0xfff
+#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0
+#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xffff0000
+#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0xffff
+#define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0
+#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xffff0000
+#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x3fff
+#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0
+#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xffff0000
+#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10
+#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x100000
+#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14
+#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x1000000
+#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18
+#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000
+#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c
+#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000
+#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d
+#define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0xffffff
+#define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0
+#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0xffffff
+#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0
+#define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0xffffff
+#define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0
+#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0xffffff
+#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0
+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x1
+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0
+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0xe
+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1
+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x10
+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4
+#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x3f00
+#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8
+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x10000
+#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10
+#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x3ffffff
+#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0
+#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xfc000000
+#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a
+#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x1
+#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0
+#define DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x7
+#define DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0
+#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x3f00
+#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8
+#define DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x70000
+#define DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10
+#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3f000000
+#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18
+#define DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x7
+#define DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0
+#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x3f00
+#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8
+#define DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x70000
+#define DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10
+#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3f000000
+#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18
+#define DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x7
+#define DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0
+#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x3f00
+#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8
+#define DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x70000
+#define DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10
+#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3f000000
+#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18
+#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x3
+#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0
+#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x100
+#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8
+#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x3ff
+#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0
+#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x30000
+#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10
+#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x1
+#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0
+#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x10
+#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4
+#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x100
+#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8
+#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK 0xff
+#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT 0x0
+#define AUX_CONTROL__AUX_EN_MASK 0x1
+#define AUX_CONTROL__AUX_EN__SHIFT 0x0
+#define AUX_CONTROL__AUX_LS_READ_EN_MASK 0x100
+#define AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8
+#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x1000
+#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc
+#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x10000
+#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10
+#define AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x40000
+#define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12
+#define AUX_CONTROL__AUX_HPD_SEL_MASK 0x700000
+#define AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14
+#define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x1000000
+#define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18
+#define AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000
+#define AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c
+#define AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000
+#define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d
+#define AUX_CONTROL__SPARE_0_MASK 0x40000000
+#define AUX_CONTROL__SPARE_0__SHIFT 0x1e
+#define AUX_CONTROL__SPARE_1_MASK 0x80000000
+#define AUX_CONTROL__SPARE_1__SHIFT 0x1f
+#define AUX_SW_CONTROL__AUX_SW_GO_MASK 0x1
+#define AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0
+#define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x4
+#define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2
+#define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0xf0
+#define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4
+#define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x1f0000
+#define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10
+#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x3
+#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0
+#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0xc
+#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2
+#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x100
+#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8
+#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x400
+#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa
+#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x10000
+#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10
+#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x10000
+#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10
+#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x20000
+#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11
+#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x1000000
+#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18
+#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x1000000
+#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18
+#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x2000000
+#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19
+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x1
+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0
+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x2
+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1
+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x4
+#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2
+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x10
+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4
+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x20
+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5
+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x40
+#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x100
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x200
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x400
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x1000
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x2000
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x4000
+#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe
+#define AUX_SW_STATUS__AUX_SW_DONE_MASK 0x1
+#define AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0
+#define AUX_SW_STATUS__AUX_SW_REQ_MASK 0x2
+#define AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1
+#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x70
+#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4
+#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x80
+#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7
+#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x100
+#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8
+#define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x200
+#define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9
+#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x400
+#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa
+#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x800
+#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb
+#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x1000
+#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x4000
+#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe
+#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x20000
+#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11
+#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x40000
+#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12
+#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x80000
+#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13
+#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x100000
+#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14
+#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x400000
+#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16
+#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x800000
+#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17
+#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1f000000
+#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18
+#define AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xc0000000
+#define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e
+#define AUX_LS_STATUS__AUX_LS_DONE_MASK 0x1
+#define AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0
+#define AUX_LS_STATUS__AUX_LS_REQ_MASK 0x2
+#define AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1
+#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x70
+#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4
+#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x80
+#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7
+#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x100
+#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8
+#define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x200
+#define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9
+#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x400
+#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa
+#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x800
+#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb
+#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x1000
+#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x4000
+#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe
+#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x20000
+#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11
+#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x40000
+#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12
+#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x80000
+#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13
+#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x100000
+#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14
+#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x400000
+#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16
+#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x800000
+#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17
+#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1f000000
+#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18
+#define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000
+#define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d
+#define AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000
+#define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e
+#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000
+#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f
+#define AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x1
+#define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0
+#define AUX_SW_DATA__AUX_SW_DATA_MASK 0xff00
+#define AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8
+#define AUX_SW_DATA__AUX_SW_INDEX_MASK 0x1f0000
+#define AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10
+#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000
+#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+#define AUX_LS_DATA__AUX_LS_DATA_MASK 0xff00
+#define AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8
+#define AUX_LS_DATA__AUX_LS_INDEX_MASK 0x1f0000
+#define AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10
+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x1
+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0
+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x30
+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4
+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x1ff0000
+#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10
+#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x7
+#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0
+#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x3f00
+#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8
+#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x70000
+#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x70
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x700
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x3000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x10000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x20000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x40000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x80000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x300000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x7000000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000
+#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c
+#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0xff
+#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0
+#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x1
+#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0
+#define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x70
+#define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4
+#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x1ff0000
+#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10
+#define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x7
+#define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0
+#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x1f00
+#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8
+#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x1f0000
+#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10
+#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3fe00000
+#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x1
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x10
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0xf00
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0xf000
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x70000
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x100000
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0xc00000
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x3000000
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xf0000000
+#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x1f
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x1f00
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x30000
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x300000
+#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x1
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x10
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x100
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x1e00
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x10000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x100000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x200000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x400000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x800000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x1000000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x2000000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xf0000000
+#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x1
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x2
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x70
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x80
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x100
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x200
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x400
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x800
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x1000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x4000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x20000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x40000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x80000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x100000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x400000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x800000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1f000000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000
+#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e
+#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW_MASK 0x1
+#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW__SHIFT 0x0
+#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_MASK 0xff00
+#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA__SHIFT 0x8
+#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_MASK 0x3f0000
+#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX__SHIFT 0x10
+#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE_MASK 0x80000000
+#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE__SHIFT 0x1f
+#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN_MASK 0x1
+#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN__SHIFT 0x0
+#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE_MASK 0xffff0
+#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE__SHIFT 0x4
+#define DVO_ENABLE__DVO_ENABLE_MASK 0x1
+#define DVO_ENABLE__DVO_ENABLE__SHIFT 0x0
+#define DVO_ENABLE__DVO_PIXEL_WIDTH_MASK 0x30
+#define DVO_ENABLE__DVO_PIXEL_WIDTH__SHIFT 0x4
+#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK 0x7
+#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT 0x0
+#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK 0x70000
+#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT 0x10
+#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK 0x3
+#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT 0x0
+#define DVO_OUTPUT__DVO_CLOCK_MODE_MASK 0x100
+#define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT 0x8
+#define DVO_CONTROL__DVO_RATE_SELECT_MASK 0x1
+#define DVO_CONTROL__DVO_RATE_SELECT__SHIFT 0x0
+#define DVO_CONTROL__DVO_SDRCLK_SEL_MASK 0x2
+#define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT 0x1
+#define DVO_CONTROL__DVO_DVPDATA_WIDTH_MASK 0x30
+#define DVO_CONTROL__DVO_DVPDATA_WIDTH__SHIFT 0x4
+#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK 0x100
+#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT 0x8
+#define DVO_CONTROL__DVO_RESET_FIFO_MASK 0x10000
+#define DVO_CONTROL__DVO_RESET_FIFO__SHIFT 0x10
+#define DVO_CONTROL__DVO_SYNC_PHASE_MASK 0x20000
+#define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT 0x11
+#define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK 0x40000
+#define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT 0x12
+#define DVO_CONTROL__DVO_HSYNC_POLARITY_MASK 0x100000
+#define DVO_CONTROL__DVO_HSYNC_POLARITY__SHIFT 0x14
+#define DVO_CONTROL__DVO_VSYNC_POLARITY_MASK 0x200000
+#define DVO_CONTROL__DVO_VSYNC_POLARITY__SHIFT 0x15
+#define DVO_CONTROL__DVO_DE_POLARITY_MASK 0x400000
+#define DVO_CONTROL__DVO_DE_POLARITY__SHIFT 0x16
+#define DVO_CONTROL__DVO_COLOR_FORMAT_MASK 0x3000000
+#define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT 0x18
+#define DVO_CONTROL__DVO_CTL3_MASK 0x80000000
+#define DVO_CONTROL__DVO_CTL3__SHIFT 0x1f
+#define DVO_CRC_EN__DVO_CRC2_EN_MASK 0x10000
+#define DVO_CRC_EN__DVO_CRC2_EN__SHIFT 0x10
+#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK 0x7ffffff
+#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT 0x0
+#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK 0x7ffffff
+#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT 0x0
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK 0x1
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT 0x0
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK 0xfc
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT 0x2
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK 0x100
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT 0x8
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK 0xf0000
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT 0x10
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK 0x3c00000
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT 0x16
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK 0x20000000
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT 0x1d
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000
+#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f
+#define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x1
+#define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x0
+#define FBC_CNTL__FBC_SRC_SEL_MASK 0xe
+#define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x1
+#define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x30000
+#define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x10
+#define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x2000000
+#define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x19
+#define FBC_CNTL__FBC_EN_MASK 0x80000000
+#define FBC_CNTL__FBC_EN__SHIFT 0x1f
+#define FBC_IDLE_MASK__FBC_IDLE_MASK_MASK 0xffffffff
+#define FBC_IDLE_MASK__FBC_IDLE_MASK__SHIFT 0x0
+#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xffffffff
+#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x0
+#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x1f
+#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x0
+#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x80
+#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x7
+#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x1f00
+#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x8
+#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0xf
+#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x0
+#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x10000
+#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x10
+#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x20000
+#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x11
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x40000
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x12
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x80000
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x13
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x100000
+#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x14
+#define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x1
+#define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x0
+#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x100
+#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x8
+#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x200
+#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x9
+#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x400
+#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0xa
+#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x800
+#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0xb
+#define FBC_COMP_MODE__FBC_IND_EN_MASK 0x10000
+#define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x10
+#define FBC_DEBUG0__FBC_PERF_MUX0_MASK 0xff
+#define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT 0x0
+#define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0xff00
+#define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT 0x8
+#define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK 0x10000
+#define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT 0x10
+#define FBC_DEBUG0__FBC_DEBUG0_MASK 0xfe0000
+#define FBC_DEBUG0__FBC_DEBUG0__SHIFT 0x11
+#define FBC_DEBUG0__FBC_DEBUG_MUX_MASK 0xff000000
+#define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT 0x18
+#define FBC_DEBUG1__FBC_DEBUG1_MASK 0xffffffff
+#define FBC_DEBUG1__FBC_DEBUG1__SHIFT 0x0
+#define FBC_DEBUG2__FBC_DEBUG2_MASK 0xffffffff
+#define FBC_DEBUG2__FBC_DEBUG2__SHIFT 0x0
+#define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0xffffff
+#define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x0
+#define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0xffffff
+#define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x0
+#define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0xffffff
+#define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x0
+#define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0xffffff
+#define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x0
+#define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0xffffff
+#define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x0
+#define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0xffffff
+#define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x0
+#define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0xffffff
+#define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x0
+#define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0xffffff
+#define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x0
+#define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0xffffff
+#define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x0
+#define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0xffffff
+#define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x0
+#define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0xffffff
+#define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x0
+#define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0xffffff
+#define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x0
+#define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0xffffff
+#define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x0
+#define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0xffffff
+#define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x0
+#define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0xffffff
+#define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x0
+#define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0xffffff
+#define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x0
+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0x3ff
+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x0
+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0x3ff0000
+#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x10
+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0x3ff
+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x0
+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0x3ff0000
+#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x10
+#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0xf0000
+#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x10
+#define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x3
+#define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x0
+#define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x8
+#define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x3
+#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0xf0
+#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x4
+#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x300
+#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x8
+#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x400
+#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0xa
+#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x800
+#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0xb
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK 0x3ff
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT 0x0
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA_MASK 0x10000
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA__SHIFT 0x10
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA_MASK 0x20000
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA__SHIFT 0x11
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK 0x80000000
+#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT 0x1f
+#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK 0xffffffff
+#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT 0x0
+#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK 0xffffffff
+#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT 0x0
+#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI_MASK 0xff
+#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI__SHIFT 0x0
+#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI_MASK 0xff
+#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI__SHIFT 0x0
+#define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x3
+#define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x0
+#define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x4
+#define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x2
+#define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x8
+#define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x3
+#define FBC_MISC__FBC_ERROR_PIXEL_MASK 0xf0
+#define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x4
+#define FBC_MISC__FBC_DIVIDE_X_MASK 0x300
+#define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x8
+#define FBC_MISC__FBC_DIVIDE_Y_MASK 0x400
+#define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0xa
+#define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x800
+#define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0xb
+#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x1000
+#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0xc
+#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x10000
+#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x10
+#define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x100000
+#define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x14
+#define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x200000
+#define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x15
+#define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0xf0000000
+#define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x1c
+#define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x1
+#define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x0
+#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK 0xff
+#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT 0x0
+#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK 0xffffffff
+#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT 0x0
+#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0xffff
+#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0
+#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xffff0000
+#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10
+#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0xffff
+#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0
+#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xffff0000
+#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10
+#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0xffff
+#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0
+#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xffff0000
+#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10
+#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x1
+#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0
+#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x10
+#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4
+#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x1
+#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0
+#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x10
+#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4
+#define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x10000
+#define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10
+#define FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x20000
+#define FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x11
+#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x40000
+#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x12
+#define FMT_CONTROL__FMT_SRC_SELECT_MASK 0x7000000
+#define FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18
+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN_MASK 0x1
+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN__SHIFT 0x0
+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR_MASK 0x700
+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR__SHIFT 0x8
+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT_MASK 0xf000
+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT__SHIFT 0xc
+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x10000
+#define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x10
+#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0_MASK 0xffff
+#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0__SHIFT 0x0
+#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1_MASK 0xffff0000
+#define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1__SHIFT 0x10
+#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2_MASK 0xffff
+#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2__SHIFT 0x0
+#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3_MASK 0xffff0000
+#define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3__SHIFT 0x10
+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x1
+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0
+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x2
+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1
+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x30
+#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4
+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x100
+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8
+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x600
+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9
+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x1800
+#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb
+#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x2000
+#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd
+#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x4000
+#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe
+#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x8000
+#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x10000
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x60000
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x600000
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x1000000
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x2000000
+#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19
+#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0xc000000
+#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a
+#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000
+#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c
+#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xc0000000
+#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e
+#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0xff
+#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0
+#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xffff0000
+#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10
+#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0xff
+#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0
+#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xffff0000
+#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10
+#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0xff
+#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0
+#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xffff0000
+#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10
+#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT_MASK 0x1
+#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT__SHIFT 0x0
+#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0_MASK 0x10
+#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0__SHIFT 0x4
+#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX_MASK 0xffffffff
+#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SHIFT 0x0
+#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX_MASK 0xffffffff
+#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SHIFT 0x0
+#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x1
+#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0
+#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x70000
+#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10
+#define FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x1
+#define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0
+#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x2
+#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1
+#define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x10
+#define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4
+#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb_MASK 0x100
+#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb__SHIFT 0x8
+#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x3000
+#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc
+#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000
+#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10
+#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x100000
+#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14
+#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x1000000
+#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18
+#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0xffff
+#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0
+#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xffff0000
+#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10
+#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0xffff
+#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0
+#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xffff0000
+#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10
+#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0xffff
+#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0
+#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xffff0000
+#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10
+#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0xffff
+#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0
+#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xffff0000
+#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10
+#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK 0x3
+#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT 0x0
+#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX_MASK 0xff
+#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX__SHIFT 0x0
+#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA_MASK 0xffffffff
+#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA__SHIFT 0x0
+#define FMT_DEBUG0__FMT_DEBUG0_MASK 0xffffffff
+#define FMT_DEBUG0__FMT_DEBUG0__SHIFT 0x0
+#define FMT_DEBUG1__FMT_DEBUG1_MASK 0xffffffff
+#define FMT_DEBUG1__FMT_DEBUG1__SHIFT 0x0
+#define FMT_DEBUG2__FMT_DEBUG2_MASK 0xffffffff
+#define FMT_DEBUG2__FMT_DEBUG2__SHIFT 0x0
+#define FMT_DEBUG_ID__FMT_DEBUG_ID_MASK 0xffffffff
+#define FMT_DEBUG_ID__FMT_DEBUG_ID__SHIFT 0x0
+#define LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3
+#define LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0
+#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4
+#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2
+#define LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8
+#define LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3
+#define LB_DATA_FORMAT__PREFETCH_MASK 0x1000
+#define LB_DATA_FORMAT__PREFETCH__SHIFT 0xc
+#define LB_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000
+#define LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18
+#define LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000
+#define LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f
+#define LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0xfff
+#define LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0
+#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000
+#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10
+#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000
+#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14
+#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0xfff
+#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0
+#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff
+#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0
+#define LB_VLINE_START_END__VLINE_START_MASK 0x3fff
+#define LB_VLINE_START_END__VLINE_START__SHIFT 0x0
+#define LB_VLINE_START_END__VLINE_END_MASK 0x7fff0000
+#define LB_VLINE_START_END__VLINE_END__SHIFT 0x10
+#define LB_VLINE_START_END__VLINE_INV_MASK 0x80000000
+#define LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f
+#define LB_VLINE2_START_END__VLINE2_START_MASK 0x3fff
+#define LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0
+#define LB_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000
+#define LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10
+#define LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000
+#define LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f
+#define LB_V_COUNTER__V_COUNTER_MASK 0x7fff
+#define LB_V_COUNTER__V_COUNTER__SHIFT 0x0
+#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff
+#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0
+#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1
+#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0
+#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10
+#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4
+#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100
+#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8
+#define LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1
+#define LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0
+#define LB_VLINE_STATUS__VLINE_ACK_MASK 0x10
+#define LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4
+#define LB_VLINE_STATUS__VLINE_STAT_MASK 0x1000
+#define LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc
+#define LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000
+#define LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10
+#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000
+#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11
+#define LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1
+#define LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0
+#define LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x10
+#define LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4
+#define LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000
+#define LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc
+#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000
+#define LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10
+#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000
+#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11
+#define LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1
+#define LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0
+#define LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x10
+#define LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4
+#define LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000
+#define LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc
+#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000
+#define LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10
+#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000
+#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11
+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3
+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0
+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10
+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4
+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00
+#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8
+#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000
+#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16
+#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0
+#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4
+#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0
+#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4
+#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0
+#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4
+#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1
+#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0
+#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100
+#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8
+#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0
+#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4
+#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0
+#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4
+#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0
+#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4
+#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0
+#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4
+#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0
+#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4
+#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0
+#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4
+#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f
+#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0
+#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00
+#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa
+#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000
+#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10
+#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000
+#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c
+#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff
+#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0
+#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000
+#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10
+#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff
+#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0
+#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000
+#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000
+#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc
+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000
+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10
+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000
+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14
+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000
+#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18
+#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1
+#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0
+#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x3
+#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0xf
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x10
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x100
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x1000
+#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x3
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x7fff00
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3f000000
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000
+#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e
+#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x3
+#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x100
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x1000
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x10000
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x100000
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000
+#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c
+#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000
+#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f
+#define LB_DEBUG__LB_DEBUG_MASK 0xffffffff
+#define LB_DEBUG__LB_DEBUG__SHIFT 0x0
+#define LB_DEBUG2__LB_DEBUG2_MASK 0xffffffff
+#define LB_DEBUG2__LB_DEBUG2__SHIFT 0x0
+#define LB_DEBUG3__LB_DEBUG3_MASK 0xffffffff
+#define LB_DEBUG3__LB_DEBUG3__SHIFT 0x0
+#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff
+#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0
+#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff
+#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0
+#define MVP_CONTROL1__MVP_EN_MASK 0x1
+#define MVP_CONTROL1__MVP_EN__SHIFT 0x0
+#define MVP_CONTROL1__MVP_MIXER_MODE_MASK 0x70
+#define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT 0x4
+#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK 0x100
+#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT 0x8
+#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK 0x200
+#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT 0x9
+#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK 0x400
+#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT 0xa
+#define MVP_CONTROL1__MVP_RATE_CONTROL_MASK 0x1000
+#define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT 0xc
+#define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK 0x10000
+#define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT 0x10
+#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK 0x300000
+#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT 0x14
+#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK 0x1000000
+#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT 0x18
+#define MVP_CONTROL1__MVP_30BPP_EN_MASK 0x10000000
+#define MVP_CONTROL1__MVP_30BPP_EN__SHIFT 0x1c
+#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK 0x40000000
+#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT 0x1e
+#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK 0x80000000
+#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT 0x1f
+#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK 0x1
+#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT 0x0
+#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK 0x10
+#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT 0x4
+#define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK 0x100
+#define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT 0x8
+#define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK 0x1000
+#define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT 0xc
+#define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK 0x10000
+#define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT 0x10
+#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK 0x100000
+#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT 0x14
+#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK 0x1000000
+#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT 0x18
+#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK 0x10000000
+#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT 0x1c
+#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK 0xff
+#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT 0x0
+#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK 0xff00
+#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT 0x8
+#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK 0xff0000
+#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT 0x10
+#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK 0xff
+#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT 0x0
+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK 0x100
+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT 0x8
+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK 0x1000
+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT 0xc
+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK 0x10000
+#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT 0x10
+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK 0x100000
+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT 0x14
+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK 0x1000000
+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT 0x18
+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK 0x10000000
+#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT 0x1c
+#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK 0x40000000
+#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT 0x1e
+#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK 0x80000000
+#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT 0x1f
+#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK 0x1fff
+#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT 0x0
+#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK 0x1fff0000
+#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT 0x10
+#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK 0x1
+#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT 0x0
+#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK 0x10
+#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT 0x4
+#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK 0xffffff00
+#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT 0x8
+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK 0x3ff
+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT 0x0
+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK 0xffc00
+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT 0xa
+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK 0x3ff00000
+#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT 0x14
+#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK 0xff
+#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT 0x0
+#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK 0xff00
+#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT 0x8
+#define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK 0xff0000
+#define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT 0x10
+#define MVP_CRC_CNTL__MVP_CRC_EN_MASK 0x10000000
+#define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT 0x1c
+#define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK 0x20000000
+#define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT 0x1d
+#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK 0x40000000
+#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT 0x1e
+#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK 0xffff
+#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT 0x0
+#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK 0xffff0000
+#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT 0x10
+#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK 0xffff
+#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT 0x0
+#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK 0x1
+#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT 0x0
+#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x10
+#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x4
+#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK 0x100
+#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT 0x8
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK 0x1000
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT 0xc
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK 0x10000
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT 0x10
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK 0x100000
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT 0x14
+#define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK 0x1000000
+#define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT 0x18
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK 0x10000000
+#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT 0x1c
+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK 0x1fff
+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT 0x0
+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK 0x1fff0000
+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT 0x10
+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK 0x80000000
+#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT 0x1f
+#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK 0x1fff
+#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT 0x0
+#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK 0x80000000
+#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT 0x1f
+#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN_MASK 0x1
+#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN__SHIFT 0x0
+#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK 0x2
+#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN__SHIFT 0x1
+#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL_MASK 0x4
+#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT 0x2
+#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL_MASK 0x8
+#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL__SHIFT 0x3
+#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP_MASK 0x10
+#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP__SHIFT 0x4
+#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP_MASK 0x20
+#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP__SHIFT 0x5
+#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR_MASK 0x40
+#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR__SHIFT 0x6
+#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY_MASK 0x80
+#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY__SHIFT 0x7
+#define MVP_DEBUG__MVP_DEBUG_BITS_MASK 0xffffff00
+#define MVP_DEBUG__MVP_DEBUG_BITS__SHIFT 0x8
+#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK 0xff
+#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT 0x0
+#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK 0xffffffff
+#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT 0x0
+#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION_MASK 0x6
+#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1
+#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION_MASK 0x6
+#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1
+#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK 0x1
+#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT 0x0
+#define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK 0x1fffffe
+#define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT 0x1
+#define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK 0x1
+#define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT 0x0
+#define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK 0x1fffffe
+#define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT 0x1
+#define MVP_DEBUG_13__IDED_START_READ_B_MASK 0x2000000
+#define MVP_DEBUG_13__IDED_START_READ_B__SHIFT 0x19
+#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK 0x4000000
+#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT 0x1a
+#define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK 0x38000000
+#define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT 0x1b
+#define MVP_DEBUG_14__IDEE_READ_ADD_MASK 0x7
+#define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT 0x0
+#define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK 0x38
+#define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT 0x3
+#define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK 0x1c0
+#define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT 0x6
+#define MVP_DEBUG_14__IDEE_START_READ_MASK 0x200
+#define MVP_DEBUG_14__IDEE_START_READ__SHIFT 0x9
+#define MVP_DEBUG_14__IDEE_START_READ_B_MASK 0x400
+#define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT 0xa
+#define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK 0x800
+#define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT 0xb
+#define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK 0x1000
+#define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT 0xc
+#define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK 0x2000
+#define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT 0xd
+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK 0x4000
+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT 0xe
+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK 0x8000
+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT 0xf
+#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK 0x10000
+#define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT 0x10
+#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK 0x20000
+#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT 0x11
+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK 0x40000
+#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT 0x12
+#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK 0x80000
+#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT 0x13
+#define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK 0x100000
+#define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT 0x14
+#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK 0x1
+#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT 0x0
+#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK 0xfffffff0
+#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT 0x4
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK 0x1
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT 0x0
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK 0x2
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT 0x1
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK 0x4
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT 0x2
+#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK 0x8
+#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT 0x3
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK 0xff0
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT 0x4
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK 0x1000
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT 0xc
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK 0x2000
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT 0xd
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK 0xff0000
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT 0x10
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK 0xff000000
+#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT 0x18
+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK 0x1
+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT 0x0
+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK 0x2
+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x1
+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK 0xfffffffc
+#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT 0x2
+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0xf
+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0
+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0xf00
+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8
+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x70000
+#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000
+#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+#define SCL_MODE__SCL_MODE_MASK 0x3
+#define SCL_MODE__SCL_MODE__SHIFT 0x0
+#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7
+#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0
+#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0xf00
+#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8
+#define SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1
+#define SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0
+#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x3
+#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0
+#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf
+#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0
+#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00
+#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8
+#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1
+#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0
+#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000
+#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10
+#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x1
+#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0
+#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100
+#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff
+#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0
+#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff
+#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0
+#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000
+#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18
+#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x1
+#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0
+#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100
+#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8
+#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff
+#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0
+#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff
+#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0
+#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000
+#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18
+#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff
+#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0
+#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000
+#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18
+#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff
+#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0
+#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000
+#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+#define SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x1
+#define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0
+#define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100
+#define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8
+#define SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000
+#define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10
+#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000
+#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18
+#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x7
+#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0
+#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x10
+#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4
+#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x700
+#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8
+#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x1000
+#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc
+#define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1
+#define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x1
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x100
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x1000
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x10000
+#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
+#define VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff
+#define VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0
+#define VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000
+#define VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10
+#define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x3fff
+#define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0
+#define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3fff0000
+#define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10
+#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff
+#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0
+#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000
+#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10
+#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff
+#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0
+#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000
+#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10
+#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1
+#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0
+#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10
+#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4
+#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80
+#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7
+#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff
+#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0
+#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff
+#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0
+#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000
+#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10
+#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1
+#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0
+#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1
+#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0
+#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6
+#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1
+#define SCL_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8
+#define SCL_DEBUG2__SCL_DEBUG2__SHIFT 0x3
+#define SCL_DEBUG__SCL_DEBUG_MASK 0xffffffff
+#define SCL_DEBUG__SCL_DEBUG__SHIFT 0x0
+#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff
+#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0
+#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff
+#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0
+#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x1
+#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0
+#define GENMO_WT__VGA_RAM_EN_MASK 0x2
+#define GENMO_WT__VGA_RAM_EN__SHIFT 0x1
+#define GENMO_WT__VGA_CKSEL_MASK 0xc
+#define GENMO_WT__VGA_CKSEL__SHIFT 0x2
+#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20
+#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5
+#define GENMO_WT__VGA_HSYNC_POL_MASK 0x40
+#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6
+#define GENMO_WT__VGA_VSYNC_POL_MASK 0x80
+#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7
+#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x1
+#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0
+#define GENMO_RD__VGA_RAM_EN_MASK 0x2
+#define GENMO_RD__VGA_RAM_EN__SHIFT 0x1
+#define GENMO_RD__VGA_CKSEL_MASK 0xc
+#define GENMO_RD__VGA_CKSEL__SHIFT 0x2
+#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20
+#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5
+#define GENMO_RD__VGA_HSYNC_POL_MASK 0x40
+#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6
+#define GENMO_RD__VGA_VSYNC_POL_MASK 0x80
+#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7
+#define GENENB__BLK_IO_BASE_MASK 0xff
+#define GENENB__BLK_IO_BASE__SHIFT 0x0
+#define GENFC_WT__VSYNC_SEL_W_MASK 0x8
+#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3
+#define GENFC_RD__VSYNC_SEL_R_MASK 0x8
+#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3
+#define GENS0__SENSE_SWITCH_MASK 0x10
+#define GENS0__SENSE_SWITCH__SHIFT 0x4
+#define GENS0__CRT_INTR_MASK 0x80
+#define GENS0__CRT_INTR__SHIFT 0x7
+#define GENS1__NO_DISPLAY_MASK 0x1
+#define GENS1__NO_DISPLAY__SHIFT 0x0
+#define GENS1__VGA_VSTATUS_MASK 0x8
+#define GENS1__VGA_VSTATUS__SHIFT 0x3
+#define GENS1__PIXEL_READ_BACK_MASK 0x30
+#define GENS1__PIXEL_READ_BACK__SHIFT 0x4
+#define DAC_DATA__DAC_DATA_MASK 0x3f
+#define DAC_DATA__DAC_DATA__SHIFT 0x0
+#define DAC_MASK__DAC_MASK_MASK 0xff
+#define DAC_MASK__DAC_MASK__SHIFT 0x0
+#define DAC_R_INDEX__DAC_R_INDEX_MASK 0xff
+#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0
+#define DAC_W_INDEX__DAC_W_INDEX_MASK 0xff
+#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0
+#define SEQ8_IDX__SEQ_IDX_MASK 0x7
+#define SEQ8_IDX__SEQ_IDX__SHIFT 0x0
+#define SEQ8_DATA__SEQ_DATA_MASK 0xff
+#define SEQ8_DATA__SEQ_DATA__SHIFT 0x0
+#define SEQ00__SEQ_RST0B_MASK 0x1
+#define SEQ00__SEQ_RST0B__SHIFT 0x0
+#define SEQ00__SEQ_RST1B_MASK 0x2
+#define SEQ00__SEQ_RST1B__SHIFT 0x1
+#define SEQ01__SEQ_DOT8_MASK 0x1
+#define SEQ01__SEQ_DOT8__SHIFT 0x0
+#define SEQ01__SEQ_SHIFT2_MASK 0x4
+#define SEQ01__SEQ_SHIFT2__SHIFT 0x2
+#define SEQ01__SEQ_PCLKBY2_MASK 0x8
+#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3
+#define SEQ01__SEQ_SHIFT4_MASK 0x10
+#define SEQ01__SEQ_SHIFT4__SHIFT 0x4
+#define SEQ01__SEQ_MAXBW_MASK 0x20
+#define SEQ01__SEQ_MAXBW__SHIFT 0x5
+#define SEQ02__SEQ_MAP0_EN_MASK 0x1
+#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0
+#define SEQ02__SEQ_MAP1_EN_MASK 0x2
+#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1
+#define SEQ02__SEQ_MAP2_EN_MASK 0x4
+#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2
+#define SEQ02__SEQ_MAP3_EN_MASK 0x8
+#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3
+#define SEQ03__SEQ_FONT_B1_MASK 0x1
+#define SEQ03__SEQ_FONT_B1__SHIFT 0x0
+#define SEQ03__SEQ_FONT_B2_MASK 0x2
+#define SEQ03__SEQ_FONT_B2__SHIFT 0x1
+#define SEQ03__SEQ_FONT_A1_MASK 0x4
+#define SEQ03__SEQ_FONT_A1__SHIFT 0x2
+#define SEQ03__SEQ_FONT_A2_MASK 0x8
+#define SEQ03__SEQ_FONT_A2__SHIFT 0x3
+#define SEQ03__SEQ_FONT_B0_MASK 0x10
+#define SEQ03__SEQ_FONT_B0__SHIFT 0x4
+#define SEQ03__SEQ_FONT_A0_MASK 0x20
+#define SEQ03__SEQ_FONT_A0__SHIFT 0x5
+#define SEQ04__SEQ_256K_MASK 0x2
+#define SEQ04__SEQ_256K__SHIFT 0x1
+#define SEQ04__SEQ_ODDEVEN_MASK 0x4
+#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2
+#define SEQ04__SEQ_CHAIN_MASK 0x8
+#define SEQ04__SEQ_CHAIN__SHIFT 0x3
+#define CRTC8_IDX__VCRTC_IDX_MASK 0x3f
+#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0
+#define CRTC8_DATA__VCRTC_DATA_MASK 0xff
+#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0
+#define CRT00__H_TOTAL_MASK 0xff
+#define CRT00__H_TOTAL__SHIFT 0x0
+#define CRT01__H_DISP_END_MASK 0xff
+#define CRT01__H_DISP_END__SHIFT 0x0
+#define CRT02__H_BLANK_START_MASK 0xff
+#define CRT02__H_BLANK_START__SHIFT 0x0
+#define CRT03__H_BLANK_END_MASK 0x1f
+#define CRT03__H_BLANK_END__SHIFT 0x0
+#define CRT03__H_DE_SKEW_MASK 0x60
+#define CRT03__H_DE_SKEW__SHIFT 0x5
+#define CRT03__CR10CR11_R_DIS_B_MASK 0x80
+#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7
+#define CRT04__H_SYNC_START_MASK 0xff
+#define CRT04__H_SYNC_START__SHIFT 0x0
+#define CRT05__H_SYNC_END_MASK 0x1f
+#define CRT05__H_SYNC_END__SHIFT 0x0
+#define CRT05__H_SYNC_SKEW_MASK 0x60
+#define CRT05__H_SYNC_SKEW__SHIFT 0x5
+#define CRT05__H_BLANK_END_B5_MASK 0x80
+#define CRT05__H_BLANK_END_B5__SHIFT 0x7
+#define CRT06__V_TOTAL_MASK 0xff
+#define CRT06__V_TOTAL__SHIFT 0x0
+#define CRT07__V_TOTAL_B8_MASK 0x1
+#define CRT07__V_TOTAL_B8__SHIFT 0x0
+#define CRT07__V_DISP_END_B8_MASK 0x2
+#define CRT07__V_DISP_END_B8__SHIFT 0x1
+#define CRT07__V_SYNC_START_B8_MASK 0x4
+#define CRT07__V_SYNC_START_B8__SHIFT 0x2
+#define CRT07__V_BLANK_START_B8_MASK 0x8
+#define CRT07__V_BLANK_START_B8__SHIFT 0x3
+#define CRT07__LINE_CMP_B8_MASK 0x10
+#define CRT07__LINE_CMP_B8__SHIFT 0x4
+#define CRT07__V_TOTAL_B9_MASK 0x20
+#define CRT07__V_TOTAL_B9__SHIFT 0x5
+#define CRT07__V_DISP_END_B9_MASK 0x40
+#define CRT07__V_DISP_END_B9__SHIFT 0x6
+#define CRT07__V_SYNC_START_B9_MASK 0x80
+#define CRT07__V_SYNC_START_B9__SHIFT 0x7
+#define CRT08__ROW_SCAN_START_MASK 0x1f
+#define CRT08__ROW_SCAN_START__SHIFT 0x0
+#define CRT08__BYTE_PAN_MASK 0x60
+#define CRT08__BYTE_PAN__SHIFT 0x5
+#define CRT09__MAX_ROW_SCAN_MASK 0x1f
+#define CRT09__MAX_ROW_SCAN__SHIFT 0x0
+#define CRT09__V_BLANK_START_B9_MASK 0x20
+#define CRT09__V_BLANK_START_B9__SHIFT 0x5
+#define CRT09__LINE_CMP_B9_MASK 0x40
+#define CRT09__LINE_CMP_B9__SHIFT 0x6
+#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80
+#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7
+#define CRT0A__CURSOR_START_MASK 0x1f
+#define CRT0A__CURSOR_START__SHIFT 0x0
+#define CRT0A__CURSOR_DISABLE_MASK 0x20
+#define CRT0A__CURSOR_DISABLE__SHIFT 0x5
+#define CRT0B__CURSOR_END_MASK 0x1f
+#define CRT0B__CURSOR_END__SHIFT 0x0
+#define CRT0B__CURSOR_SKEW_MASK 0x60
+#define CRT0B__CURSOR_SKEW__SHIFT 0x5
+#define CRT0C__DISP_START_MASK 0xff
+#define CRT0C__DISP_START__SHIFT 0x0
+#define CRT0D__DISP_START_MASK 0xff
+#define CRT0D__DISP_START__SHIFT 0x0
+#define CRT0E__CURSOR_LOC_HI_MASK 0xff
+#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0
+#define CRT0F__CURSOR_LOC_LO_MASK 0xff
+#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0
+#define CRT10__V_SYNC_START_MASK 0xff
+#define CRT10__V_SYNC_START__SHIFT 0x0
+#define CRT11__V_SYNC_END_MASK 0xf
+#define CRT11__V_SYNC_END__SHIFT 0x0
+#define CRT11__V_INTR_CLR_MASK 0x10
+#define CRT11__V_INTR_CLR__SHIFT 0x4
+#define CRT11__V_INTR_EN_MASK 0x20
+#define CRT11__V_INTR_EN__SHIFT 0x5
+#define CRT11__SEL5_REFRESH_CYC_MASK 0x40
+#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6
+#define CRT11__C0T7_WR_ONLY_MASK 0x80
+#define CRT11__C0T7_WR_ONLY__SHIFT 0x7
+#define CRT12__V_DISP_END_MASK 0xff
+#define CRT12__V_DISP_END__SHIFT 0x0
+#define CRT13__DISP_PITCH_MASK 0xff
+#define CRT13__DISP_PITCH__SHIFT 0x0
+#define CRT14__UNDRLN_LOC_MASK 0x1f
+#define CRT14__UNDRLN_LOC__SHIFT 0x0
+#define CRT14__ADDR_CNT_BY4_MASK 0x20
+#define CRT14__ADDR_CNT_BY4__SHIFT 0x5
+#define CRT14__DOUBLE_WORD_MASK 0x40
+#define CRT14__DOUBLE_WORD__SHIFT 0x6
+#define CRT15__V_BLANK_START_MASK 0xff
+#define CRT15__V_BLANK_START__SHIFT 0x0
+#define CRT16__V_BLANK_END_MASK 0xff
+#define CRT16__V_BLANK_END__SHIFT 0x0
+#define CRT17__RA0_AS_A13B_MASK 0x1
+#define CRT17__RA0_AS_A13B__SHIFT 0x0
+#define CRT17__RA1_AS_A14B_MASK 0x2
+#define CRT17__RA1_AS_A14B__SHIFT 0x1
+#define CRT17__VCOUNT_BY2_MASK 0x4
+#define CRT17__VCOUNT_BY2__SHIFT 0x2
+#define CRT17__ADDR_CNT_BY2_MASK 0x8
+#define CRT17__ADDR_CNT_BY2__SHIFT 0x3
+#define CRT17__WRAP_A15TOA0_MASK 0x20
+#define CRT17__WRAP_A15TOA0__SHIFT 0x5
+#define CRT17__BYTE_MODE_MASK 0x40
+#define CRT17__BYTE_MODE__SHIFT 0x6
+#define CRT17__CRTC_SYNC_EN_MASK 0x80
+#define CRT17__CRTC_SYNC_EN__SHIFT 0x7
+#define CRT18__LINE_CMP_MASK 0xff
+#define CRT18__LINE_CMP__SHIFT 0x0
+#define CRT1E__GRPH_DEC_RD1_MASK 0x2
+#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1
+#define CRT1F__GRPH_DEC_RD0_MASK 0xff
+#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0
+#define CRT22__GRPH_LATCH_DATA_MASK 0xff
+#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0
+#define GRPH8_IDX__GRPH_IDX_MASK 0xf
+#define GRPH8_IDX__GRPH_IDX__SHIFT 0x0
+#define GRPH8_DATA__GRPH_DATA_MASK 0xff
+#define GRPH8_DATA__GRPH_DATA__SHIFT 0x0
+#define GRA00__GRPH_SET_RESET0_MASK 0x1
+#define GRA00__GRPH_SET_RESET0__SHIFT 0x0
+#define GRA00__GRPH_SET_RESET1_MASK 0x2
+#define GRA00__GRPH_SET_RESET1__SHIFT 0x1
+#define GRA00__GRPH_SET_RESET2_MASK 0x4
+#define GRA00__GRPH_SET_RESET2__SHIFT 0x2
+#define GRA00__GRPH_SET_RESET3_MASK 0x8
+#define GRA00__GRPH_SET_RESET3__SHIFT 0x3
+#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x1
+#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0
+#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x2
+#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1
+#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x4
+#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2
+#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x8
+#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3
+#define GRA02__GRPH_CCOMP_MASK 0xf
+#define GRA02__GRPH_CCOMP__SHIFT 0x0
+#define GRA03__GRPH_ROTATE_MASK 0x7
+#define GRA03__GRPH_ROTATE__SHIFT 0x0
+#define GRA03__GRPH_FN_SEL_MASK 0x18
+#define GRA03__GRPH_FN_SEL__SHIFT 0x3
+#define GRA04__GRPH_RMAP_MASK 0x3
+#define GRA04__GRPH_RMAP__SHIFT 0x0
+#define GRA05__GRPH_WRITE_MODE_MASK 0x3
+#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0
+#define GRA05__GRPH_READ1_MASK 0x8
+#define GRA05__GRPH_READ1__SHIFT 0x3
+#define GRA05__CGA_ODDEVEN_MASK 0x10
+#define GRA05__CGA_ODDEVEN__SHIFT 0x4
+#define GRA05__GRPH_OES_MASK 0x20
+#define GRA05__GRPH_OES__SHIFT 0x5
+#define GRA05__GRPH_PACK_MASK 0x40
+#define GRA05__GRPH_PACK__SHIFT 0x6
+#define GRA06__GRPH_GRAPHICS_MASK 0x1
+#define GRA06__GRPH_GRAPHICS__SHIFT 0x0
+#define GRA06__GRPH_ODDEVEN_MASK 0x2
+#define GRA06__GRPH_ODDEVEN__SHIFT 0x1
+#define GRA06__GRPH_ADRSEL_MASK 0xc
+#define GRA06__GRPH_ADRSEL__SHIFT 0x2
+#define GRA07__GRPH_XCARE0_MASK 0x1
+#define GRA07__GRPH_XCARE0__SHIFT 0x0
+#define GRA07__GRPH_XCARE1_MASK 0x2
+#define GRA07__GRPH_XCARE1__SHIFT 0x1
+#define GRA07__GRPH_XCARE2_MASK 0x4
+#define GRA07__GRPH_XCARE2__SHIFT 0x2
+#define GRA07__GRPH_XCARE3_MASK 0x8
+#define GRA07__GRPH_XCARE3__SHIFT 0x3
+#define GRA08__GRPH_BMSK_MASK 0xff
+#define GRA08__GRPH_BMSK__SHIFT 0x0
+#define ATTRX__ATTR_IDX_MASK 0x1f
+#define ATTRX__ATTR_IDX__SHIFT 0x0
+#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20
+#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5
+#define ATTRDW__ATTR_DATA_MASK 0xff
+#define ATTRDW__ATTR_DATA__SHIFT 0x0
+#define ATTRDR__ATTR_DATA_MASK 0xff
+#define ATTRDR__ATTR_DATA__SHIFT 0x0
+#define ATTR00__ATTR_PAL_MASK 0x3f
+#define ATTR00__ATTR_PAL__SHIFT 0x0
+#define ATTR01__ATTR_PAL_MASK 0x3f
+#define ATTR01__ATTR_PAL__SHIFT 0x0
+#define ATTR02__ATTR_PAL_MASK 0x3f
+#define ATTR02__ATTR_PAL__SHIFT 0x0
+#define ATTR03__ATTR_PAL_MASK 0x3f
+#define ATTR03__ATTR_PAL__SHIFT 0x0
+#define ATTR04__ATTR_PAL_MASK 0x3f
+#define ATTR04__ATTR_PAL__SHIFT 0x0
+#define ATTR05__ATTR_PAL_MASK 0x3f
+#define ATTR05__ATTR_PAL__SHIFT 0x0
+#define ATTR06__ATTR_PAL_MASK 0x3f
+#define ATTR06__ATTR_PAL__SHIFT 0x0
+#define ATTR07__ATTR_PAL_MASK 0x3f
+#define ATTR07__ATTR_PAL__SHIFT 0x0
+#define ATTR08__ATTR_PAL_MASK 0x3f
+#define ATTR08__ATTR_PAL__SHIFT 0x0
+#define ATTR09__ATTR_PAL_MASK 0x3f
+#define ATTR09__ATTR_PAL__SHIFT 0x0
+#define ATTR0A__ATTR_PAL_MASK 0x3f
+#define ATTR0A__ATTR_PAL__SHIFT 0x0
+#define ATTR0B__ATTR_PAL_MASK 0x3f
+#define ATTR0B__ATTR_PAL__SHIFT 0x0
+#define ATTR0C__ATTR_PAL_MASK 0x3f
+#define ATTR0C__ATTR_PAL__SHIFT 0x0
+#define ATTR0D__ATTR_PAL_MASK 0x3f
+#define ATTR0D__ATTR_PAL__SHIFT 0x0
+#define ATTR0E__ATTR_PAL_MASK 0x3f
+#define ATTR0E__ATTR_PAL__SHIFT 0x0
+#define ATTR0F__ATTR_PAL_MASK 0x3f
+#define ATTR0F__ATTR_PAL__SHIFT 0x0
+#define ATTR10__ATTR_GRPH_MODE_MASK 0x1
+#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0
+#define ATTR10__ATTR_MONO_EN_MASK 0x2
+#define ATTR10__ATTR_MONO_EN__SHIFT 0x1
+#define ATTR10__ATTR_LGRPH_EN_MASK 0x4
+#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2
+#define ATTR10__ATTR_BLINK_EN_MASK 0x8
+#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3
+#define ATTR10__ATTR_PANTOPONLY_MASK 0x20
+#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5
+#define ATTR10__ATTR_PCLKBY2_MASK 0x40
+#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6
+#define ATTR10__ATTR_CSEL_EN_MASK 0x80
+#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7
+#define ATTR11__ATTR_OVSC_MASK 0xff
+#define ATTR11__ATTR_OVSC__SHIFT 0x0
+#define ATTR12__ATTR_MAP_EN_MASK 0xf
+#define ATTR12__ATTR_MAP_EN__SHIFT 0x0
+#define ATTR12__ATTR_VSMUX_MASK 0x30
+#define ATTR12__ATTR_VSMUX__SHIFT 0x4
+#define ATTR13__ATTR_PPAN_MASK 0xf
+#define ATTR13__ATTR_PPAN__SHIFT 0x0
+#define ATTR14__ATTR_CSEL1_MASK 0x3
+#define ATTR14__ATTR_CSEL1__SHIFT 0x0
+#define ATTR14__ATTR_CSEL2_MASK 0xc
+#define ATTR14__ATTR_CSEL2__SHIFT 0x2
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x1f
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x60
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x80
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x100
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x30000
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x1000000
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18
+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x2000000
+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x7
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x700
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x1
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x2
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x4
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x8
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x10
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x20
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x100
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x200
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x400
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x800
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x1000
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x2000
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x10000
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x20000
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0xfc0000
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x1
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x30
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x100
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x10000
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x3
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x300
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xffffffff
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0xff
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x1ffffff
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x1ffffff
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x1
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x10
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x100
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x10000
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x1000000
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x1
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x100
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x10000
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x100000
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3f000000
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x1
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x100
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x200
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x10000
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x3000000
+#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x1
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x100
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x200
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x10000
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x3000000
+#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x1
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x100
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x200
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x10000
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x3000000
+#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x1
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x100
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x200
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x10000
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x3000000
+#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x1
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x100
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x200
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x10000
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x3000000
+#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x1
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x100
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x200
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x10000
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10
+#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x3000000
+#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18
+#define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK 0xffffffff
+#define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT 0x0
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x1
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x2
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x4
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x8
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x1
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x100
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x10000
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x1000000
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x1
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x100
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x10000
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x1000000
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x1
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x2
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x4
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x8
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x3
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x18
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0xe0
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x300
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x30000
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x3000000
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x4000000
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a
+#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK 0x8000000
+#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT 0x1b
+#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK 0x10000000
+#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT 0x1c
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x1
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x100
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x10000
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x1000000
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18
+#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK 0xff
+#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT 0x0
+#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK 0xffffffff
+#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT 0x0
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x3ff
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x3ff0000
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x3ff
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x3ff0000
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
+#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK 0xff
+#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT 0x0
+#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK 0xffffffff
+#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT 0x0
+#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff
+#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x3
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x0
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x3f00
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x8
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x3f0000
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x10
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0xf000000
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x18
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000
+#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x1c
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x1
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x0
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x2
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x1
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x4
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x2
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x3ff0
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x4
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x700000
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x14
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000
+#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x1c
+#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff
+#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0
+#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000
+#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10
+#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff
+#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0
+#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000
+#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10
+#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3
+#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0
+#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300
+#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8
+#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000
+#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10
+#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff
+#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0
+#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000
+#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10
+#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1
+#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000
+#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800
+#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb
+#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7
+#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0
+#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70
+#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4
+#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff
+#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0
+#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff
+#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0
+#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0xff
+#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x0
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
+#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0xff
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0xff
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0xff
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x7
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x70
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x3f
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x7
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4
+#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK 0xffffffff
+#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xffffffff
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xffffffff
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xffffffff
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xffffffff
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xffffffff
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xffffffff
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xffffffff
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0
+#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x1
+#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0
+#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6
+#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1
+#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0xf8
+#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3
+#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0xf00
+#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8
+#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xf000
+#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc
+#define MINOR_VERSION__MINOR_VERSION_MASK 0xff
+#define MINOR_VERSION__MINOR_VERSION__SHIFT 0x0
+#define MAJOR_VERSION__MAJOR_VERSION_MASK 0xff
+#define MAJOR_VERSION__MAJOR_VERSION__SHIFT 0x0
+#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff
+#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
+#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff
+#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
+#define GLOBAL_CONTROL__CONTROLLER_RESET_MASK 0x1
+#define GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT 0x0
+#define GLOBAL_CONTROL__FLUSH_CONTROL_MASK 0x2
+#define GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT 0x1
+#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK 0x100
+#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT 0x8
+#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK 0x1
+#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT 0x0
+#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK 0x1
+#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT 0x0
+#define GLOBAL_STATUS__FLUSH_STATUS_MASK 0x2
+#define GLOBAL_STATUS__FLUSH_STATUS__SHIFT 0x1
+#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff
+#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x0
+#define INTERRUPT_CONTROL__OUTPUT_STREAM_0_INTERRUPT_ENABLE_MASK 0x1
+#define INTERRUPT_CONTROL__OUTPUT_STREAM_0_INTERRUPT_ENABLE__SHIFT 0x0
+#define INTERRUPT_CONTROL__OUTPUT_STREAM_1_INTERRUPT_ENABLE_MASK 0x2
+#define INTERRUPT_CONTROL__OUTPUT_STREAM_1_INTERRUPT_ENABLE__SHIFT 0x1
+#define INTERRUPT_CONTROL__OUTPUT_STREAM_2_INTERRUPT_ENABLE_MASK 0x4
+#define INTERRUPT_CONTROL__OUTPUT_STREAM_2_INTERRUPT_ENABLE__SHIFT 0x2
+#define INTERRUPT_CONTROL__OUTPUT_STREAM_3_INTERRUPT_ENABLE_MASK 0x8
+#define INTERRUPT_CONTROL__OUTPUT_STREAM_3_INTERRUPT_ENABLE__SHIFT 0x3
+#define INTERRUPT_CONTROL__OUTPUT_STREAM_4_INTERRUPT_ENABLE_MASK 0x10
+#define INTERRUPT_CONTROL__OUTPUT_STREAM_4_INTERRUPT_ENABLE__SHIFT 0x4
+#define INTERRUPT_CONTROL__OUTPUT_STREAM_5_INTERRUPT_ENABLE_MASK 0x20
+#define INTERRUPT_CONTROL__OUTPUT_STREAM_5_INTERRUPT_ENABLE__SHIFT 0x5
+#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000
+#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT 0x1e
+#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK 0x80000000
+#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT 0x1f
+#define INTERRUPT_STATUS__OUTPUT_STREAM_0_INTERRUPT_STATUS_MASK 0x1
+#define INTERRUPT_STATUS__OUTPUT_STREAM_0_INTERRUPT_STATUS__SHIFT 0x0
+#define INTERRUPT_STATUS__OUTPUT_STREAM_1_INTERRUPT_STATUS_MASK 0x2
+#define INTERRUPT_STATUS__OUTPUT_STREAM_1_INTERRUPT_STATUS__SHIFT 0x1
+#define INTERRUPT_STATUS__OUTPUT_STREAM_2_INTERRUPT_STATUS_MASK 0x4
+#define INTERRUPT_STATUS__OUTPUT_STREAM_2_INTERRUPT_STATUS__SHIFT 0x2
+#define INTERRUPT_STATUS__OUTPUT_STREAM_3_INTERRUPT_STATUS_MASK 0x8
+#define INTERRUPT_STATUS__OUTPUT_STREAM_3_INTERRUPT_STATUS__SHIFT 0x3
+#define INTERRUPT_STATUS__OUTPUT_STREAM_4_INTERRUPT_STATUS_MASK 0x10
+#define INTERRUPT_STATUS__OUTPUT_STREAM_4_INTERRUPT_STATUS__SHIFT 0x4
+#define INTERRUPT_STATUS__OUTPUT_STREAM_5_INTERRUPT_STATUS_MASK 0x20
+#define INTERRUPT_STATUS__OUTPUT_STREAM_5_INTERRUPT_STATUS__SHIFT 0x5
+#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK 0x40000000
+#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT 0x1e
+#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK 0x80000000
+#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT 0x1f
+#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK 0xffffffff
+#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT 0x0
+#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK 0x1
+#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT 0x0
+#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK 0x2
+#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT 0x1
+#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK 0x4
+#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT 0x2
+#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK 0x8
+#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT 0x3
+#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK 0x10
+#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT 0x4
+#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK 0x20
+#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT 0x5
+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f
+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK 0xffffff80
+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK 0xffffffff
+#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0xff
+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0
+#define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0xff
+#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0
+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000
+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf
+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x1
+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0
+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x2
+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1
+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x1
+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0
+#define CORB_SIZE__CORB_SIZE_MASK 0x3
+#define CORB_SIZE__CORB_SIZE__SHIFT 0x0
+#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0xf0
+#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xffffff80
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xffffffff
+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0xff
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf
+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0xff
+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0
+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x1
+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0
+#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2
+#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1
+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x4
+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2
+#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x1
+#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0
+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x4
+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2
+#define RIRB_SIZE__RIRB_SIZE_MASK 0x3
+#define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0
+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0xf0
+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0xfffffff
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xf0000000
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xffffffff
+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x1
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x2
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x1
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7e
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xffffff80
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xffffffff
+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xffffffff
+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x1
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x2
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x4
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x8
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x10
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x30000
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x40000
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0xf00000
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x4000000
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x8000000
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000
+#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d
+#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xffffffff
+#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xffffffff
+#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0xff
+#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xffff
+#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x70
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
+#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x7f
+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xffffff80
+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7
+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xffffffff
+#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0
+#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xffffffff
+#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x8000
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x7f
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x80
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x7f
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x100
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x200
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0xfc00
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x78
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x80
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x78
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0xff
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0xffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0xffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0xff
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0
+#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0
+#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0xff
+#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x1
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x10
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0xffff
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xffff0000
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x300
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8
+#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK 0x30
+#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT 0x4
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xffffffff
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x3
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x30
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x10000
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x20000
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x3
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x30
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x1
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x10
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x1
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x10
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xffffffff
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x1
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff0000
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0xff
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x100
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8
+#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK 0xffffffff
+#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT 0x0
+#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x1
+#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x10
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x1
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
+#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xffffffff
+#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0
+#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x1
+#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x10
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x1
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8
+#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xffffffff
+#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0
+#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK 0xff
+#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT 0x0
+#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK 0xffffffff
+#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT 0x0
+#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0xff
+#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0
+#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x100
+#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8
+#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xffffffff
+#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0
+#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x7f
+#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0
+#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x7f00
+#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8
+#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0xff0000
+#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10
+#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x1
+#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0
+#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xffffffff
+#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0
+#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xffffffff
+#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0
+#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xffffffff
+#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0
+#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xffffffff
+#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0
+#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x3fff
+#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0
+#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xffffffff
+#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000
+#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10
+#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3
+#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000
+#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x4
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG_MASK 0xffffffff
+#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xffffffff
+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xffffffff
+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0
+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xffffffff
+#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000
+#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000
+#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40
+#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x7f
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x10000
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x20000
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0xfc0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x100
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x200
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x10000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x20000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf00000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x2
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x100
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x200
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0xf000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x10000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x20000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf00000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0xffff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xffff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0xff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xffffffff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xffffffff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0xff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xff000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0xff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xff000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0xff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xff000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0xff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0xff0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xff000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0xff
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0xff00
+#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4
+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000
+#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0
+#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4
+#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff
+#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0
+#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1
+#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0
+#define BLND_CONTROL__BLND_MODE_MASK 0x300
+#define BLND_CONTROL__BLND_MODE__SHIFT 0x8
+#define BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x30000
+#define BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10
+#define BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x100000
+#define BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14
+#define BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xff000000
+#define BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18
+#define SM_CONTROL2__SM_MODE_MASK 0x7
+#define SM_CONTROL2__SM_MODE__SHIFT 0x0
+#define SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x10
+#define SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4
+#define SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x20
+#define SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5
+#define SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x300
+#define SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8
+#define SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x30000
+#define SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10
+#define SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x1000000
+#define SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18
+#define PTI_CONTROL__PTI_ENABLE_MASK 0x1
+#define PTI_CONTROL__PTI_ENABLE__SHIFT 0x0
+#define PTI_CONTROL__PTI_NEW_PIXEL_GAP_MASK 0x30
+#define PTI_CONTROL__PTI_NEW_PIXEL_GAP__SHIFT 0x4
+#define PTI_CONTROL__BLND_NEW_PIXEL_MODE_MASK 0x40
+#define PTI_CONTROL__BLND_NEW_PIXEL_MODE__SHIFT 0x6
+#define BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x1
+#define BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0
+#define BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x100
+#define BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8
+#define BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x10000
+#define BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x1
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x100
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x1000
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x30000
+#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10
+#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x1
+#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0
+#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x2
+#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1
+#define BLND_V_UPDATE_LOCK__BLND_DCP_OVL_V_UPDATE_LOCK_MASK 0x100
+#define BLND_V_UPDATE_LOCK__BLND_DCP_OVL_V_UPDATE_LOCK__SHIFT 0x8
+#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x10000
+#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10
+#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK 0x1000000
+#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT 0x18
+#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000
+#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_UPDATE_PENDING_MASK 0x1
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_UPDATE_PENDING__SHIFT 0x0
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_UPDATE_PENDING_MASK 0x2
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_UPDATE_PENDING__SHIFT 0x1
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_SURF_UPDATE_PENDING_MASK 0x4
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_SURF_UPDATE_PENDING_MASK 0x8
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_OVL_UPDATE_PENDING_MASK 0x10
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_OVL_UPDATE_PENDING__SHIFT 0x4
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_OVL_UPDATE_PENDING_MASK 0x20
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_OVL_UPDATE_PENDING__SHIFT 0x5
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_CUR_UPDATE_PENDING_MASK 0x40
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDc_CUR_UPDATE_PENDING__SHIFT 0x6
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_CUR_UPDATE_PENDING_MASK 0x80
+#define BLND_REG_UPDATE_STATUS__DCP_BLNDo_CUR_UPDATE_PENDING__SHIFT 0x7
+#define BLND_REG_UPDATE_STATUS__SCL_BLNDc_UPDATE_PENDING_MASK 0x100
+#define BLND_REG_UPDATE_STATUS__SCL_BLNDc_UPDATE_PENDING__SHIFT 0x8
+#define BLND_REG_UPDATE_STATUS__SCL_BLNDo_UPDATE_PENDING_MASK 0x200
+#define BLND_REG_UPDATE_STATUS__SCL_BLNDo_UPDATE_PENDING__SHIFT 0x9
+#define BLND_DEBUG__BLND_CNV_MUX_SELECT_MASK 0x1
+#define BLND_DEBUG__BLND_CNV_MUX_SELECT__SHIFT 0x0
+#define BLND_DEBUG__BLND_DEBUG_MASK 0xfffffffe
+#define BLND_DEBUG__BLND_DEBUG__SHIFT 0x1
+#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK 0xff
+#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT 0x0
+#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK 0xffffffff
+#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT 0x0
+#define SI_ENABLE__SI_ENABLE_MASK 0x1
+#define SI_ENABLE__SI_ENABLE__SHIFT 0x0
+#define SI_EC_CONFIG__DISPCLK_R_SCANIN_GATE_DIS_MASK 0x1
+#define SI_EC_CONFIG__DISPCLK_R_SCANIN_GATE_DIS__SHIFT 0x0
+#define SI_EC_CONFIG__DISPCLK_G_SCANIN_GATE_DIS_MASK 0x2
+#define SI_EC_CONFIG__DISPCLK_G_SCANIN_GATE_DIS__SHIFT 0x1
+#define SI_EC_CONFIG__DISPCLK_G_SISCL_GATE_DIS_MASK 0x4
+#define SI_EC_CONFIG__DISPCLK_G_SISCL_GATE_DIS__SHIFT 0x2
+#define SI_EC_CONFIG__DISPCLK_R_SCANIN_RAMP_DIS_MASK 0x8
+#define SI_EC_CONFIG__DISPCLK_R_SCANIN_RAMP_DIS__SHIFT 0x3
+#define SI_EC_CONFIG__DISPCLK_G_SCANIN_RAMP_DIS_MASK 0x10
+#define SI_EC_CONFIG__DISPCLK_G_SCANIN_RAMP_DIS__SHIFT 0x4
+#define SI_EC_CONFIG__DISPCLK_G_SISCL_RAMP_DIS_MASK 0x20
+#define SI_EC_CONFIG__DISPCLK_G_SISCL_RAMP_DIS__SHIFT 0x5
+#define SI_EC_CONFIG__SI_LB_LS_DIS_MASK 0x40
+#define SI_EC_CONFIG__SI_LB_LS_DIS__SHIFT 0x6
+#define SI_EC_CONFIG__SI_LB_SD_DIS_MASK 0x80
+#define SI_EC_CONFIG__SI_LB_SD_DIS__SHIFT 0x7
+#define SI_EC_CONFIG__SI_LUT_LS_DIS_MASK 0x100
+#define SI_EC_CONFIG__SI_LUT_LS_DIS__SHIFT 0x8
+#define SI_EC_CONFIG__SCANIN_TEST_CLK_SEL_MASK 0xf000
+#define SI_EC_CONFIG__SCANIN_TEST_CLK_SEL__SHIFT 0xc
+#define SI_EC_CONFIG__SI_RAM_PW_SAVE_MODE_MASK 0x800000
+#define SI_EC_CONFIG__SI_RAM_PW_SAVE_MODE__SHIFT 0x17
+#define SI_EC_CONFIG__LB_MEM_PWR_STATE_MASK 0x30000000
+#define SI_EC_CONFIG__LB_MEM_PWR_STATE__SHIFT 0x1c
+#define SI_EC_CONFIG__LUT_MEM_PWR_STATE_MASK 0xc0000000
+#define SI_EC_CONFIG__LUT_MEM_PWR_STATE__SHIFT 0x1e
+#define CNV_MODE__CNV_INPUT_SRC_SELECT_MASK 0x3
+#define CNV_MODE__CNV_INPUT_SRC_SELECT__SHIFT 0x0
+#define CNV_MODE__CNV_INPUT_PIPE_SELECT_MASK 0x1c
+#define CNV_MODE__CNV_INPUT_PIPE_SELECT__SHIFT 0x2
+#define CNV_MODE__CNV_FRAME_COUNT_MASK 0x300
+#define CNV_MODE__CNV_FRAME_COUNT__SHIFT 0x8
+#define CNV_MODE__CNV_WINDOW_EN_MASK 0x1000
+#define CNV_MODE__CNV_WINDOW_EN__SHIFT 0xc
+#define CNV_MODE__CNV_EYE_SELECTION_MASK 0x30000
+#define CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10
+#define CNV_MODE__CNV_STEREO_EYE_ORDER_MASK 0x40000
+#define CNV_MODE__CNV_STEREO_EYE_ORDER__SHIFT 0x12
+#define CNV_MODE__CNV_NEW_CONTENT_MASK 0x1000000
+#define CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18
+#define CNV_MODE__CNV_FRAME_EN_MASK 0x80000000
+#define CNV_MODE__CNV_FRAME_EN__SHIFT 0x1f
+#define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0xfff
+#define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0
+#define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0xfff0000
+#define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10
+#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0xfff
+#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0
+#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0xfff0000
+#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10
+#define CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x1
+#define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0
+#define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x100
+#define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8
+#define CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x10000
+#define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10
+#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x7fff
+#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0
+#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7fff0000
+#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10
+#define CNV_CSC_CONTROL__CNV_CSC_bypass_MASK 0x1
+#define CNV_CSC_CONTROL__CNV_CSC_bypass__SHIFT 0x0
+#define CNV_CSC_C11_C12__CNV_CSC_C11_MASK 0x1fff
+#define CNV_CSC_C11_C12__CNV_CSC_C11__SHIFT 0x0
+#define CNV_CSC_C11_C12__CNV_CSC_C12_MASK 0x1fff0000
+#define CNV_CSC_C11_C12__CNV_CSC_C12__SHIFT 0x10
+#define CNV_CSC_C13_C14__CNV_CSC_C13_MASK 0x1fff
+#define CNV_CSC_C13_C14__CNV_CSC_C13__SHIFT 0x0
+#define CNV_CSC_C13_C14__CNV_CSC_C14_MASK 0x7fff0000
+#define CNV_CSC_C13_C14__CNV_CSC_C14__SHIFT 0x10
+#define CNV_CSC_C21_C22__CNV_CSC_C21_MASK 0x1fff
+#define CNV_CSC_C21_C22__CNV_CSC_C21__SHIFT 0x0
+#define CNV_CSC_C21_C22__CNV_CSC_C22_MASK 0x1fff0000
+#define CNV_CSC_C21_C22__CNV_CSC_C22__SHIFT 0x10
+#define CNV_CSC_C23_C24__CNV_CSC_C23_MASK 0x1fff
+#define CNV_CSC_C23_C24__CNV_CSC_C23__SHIFT 0x0
+#define CNV_CSC_C23_C24__CNV_CSC_C24_MASK 0x7fff0000
+#define CNV_CSC_C23_C24__CNV_CSC_C24__SHIFT 0x10
+#define CNV_CSC_C31_C32__CNV_CSC_C31_MASK 0x1fff
+#define CNV_CSC_C31_C32__CNV_CSC_C31__SHIFT 0x0
+#define CNV_CSC_C31_C32__CNV_CSC_C32_MASK 0x1fff0000
+#define CNV_CSC_C31_C32__CNV_CSC_C32__SHIFT 0x10
+#define CNV_CSC_C33_C34__CNV_CSC_C33_MASK 0x1fff
+#define CNV_CSC_C33_C34__CNV_CSC_C33__SHIFT 0x0
+#define CNV_CSC_C33_C34__CNV_CSC_C34_MASK 0x7fff0000
+#define CNV_CSC_C33_C34__CNV_CSC_C34__SHIFT 0x10
+#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R_MASK 0xffff
+#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R__SHIFT 0x0
+#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G_MASK 0xffff
+#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G__SHIFT 0x0
+#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B_MASK 0xffff
+#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B__SHIFT 0x0
+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R_MASK 0xffff
+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R__SHIFT 0x0
+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R_MASK 0xffff0000
+#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R__SHIFT 0x10
+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G_MASK 0xffff
+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G__SHIFT 0x0
+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G_MASK 0xffff0000
+#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G__SHIFT 0x10
+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B_MASK 0xffff
+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B__SHIFT 0x0
+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B_MASK 0xffff0000
+#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B__SHIFT 0x10
+#define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x10
+#define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4
+#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x100
+#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8
+#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY_MASK 0x10000
+#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY__SHIFT 0x10
+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0xffff
+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x0
+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xffff0000
+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10
+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0xffff
+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x0
+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xffff0000
+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10
+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0xffff
+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x0
+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xffff0000
+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10
+#define SI_DEBUG_CTRL__SI_DEBUG_SEL_MASK 0x3
+#define SI_DEBUG_CTRL__SI_DEBUG_SEL__SHIFT 0x0
+#define SI_DBG_MODE__SI_DBG_MODE_EN_MASK 0x1
+#define SI_DBG_MODE__SI_DBG_MODE_EN__SHIFT 0x0
+#define SI_DBG_MODE__SI_DBG_DIN_FMT_MASK 0x2
+#define SI_DBG_MODE__SI_DBG_DIN_FMT__SHIFT 0x1
+#define SI_DBG_MODE__SI_DBG_36MODE_MASK 0x4
+#define SI_DBG_MODE__SI_DBG_36MODE__SHIFT 0x2
+#define SI_DBG_MODE__SI_DBG_CMAP_MASK 0x8
+#define SI_DBG_MODE__SI_DBG_CMAP__SHIFT 0x3
+#define SI_DBG_MODE__SI_DBG_PXLRATE_ERROR_MASK 0x100
+#define SI_DBG_MODE__SI_DBG_PXLRATE_ERROR__SHIFT 0x8
+#define SI_DBG_MODE__SI_DBG_SOURCE_WIDTH_MASK 0x7fff0000
+#define SI_DBG_MODE__SI_DBG_SOURCE_WIDTH__SHIFT 0x10
+#define SI_HARD_DEBUG__SI_HARD_DEBUG_MASK 0xffffffff
+#define SI_HARD_DEBUG__SI_HARD_DEBUG__SHIFT 0x0
+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX_MASK 0xff
+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX__SHIFT 0x0
+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA_MASK 0xffffffff
+#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA__SHIFT 0x0
+#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x7
+#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0
+#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_PHASE_MASK 0xf00
+#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_PHASE__SHIFT 0x8
+#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_FILTER_TYPE_MASK 0x30000
+#define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10
+#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x3fff
+#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0
+#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x8000
+#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf
+#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3fff0000
+#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10
+#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000
+#define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f
+#define SISCL_MODE__SISCL_MODE_MASK 0x3
+#define SISCL_MODE__SISCL_MODE__SHIFT 0x0
+#define SISCL_TAP_CONTROL__SISCL_V_NUM_OF_TAPS_Y_RGB_MASK 0xf
+#define SISCL_TAP_CONTROL__SISCL_V_NUM_OF_TAPS_Y_RGB__SHIFT 0x0
+#define SISCL_TAP_CONTROL__SISCL_V_NUM_OF_TAPS_CBCR_MASK 0xf0
+#define SISCL_TAP_CONTROL__SISCL_V_NUM_OF_TAPS_CBCR__SHIFT 0x4
+#define SISCL_TAP_CONTROL__SISCL_H_NUM_OF_TAPS_Y_RGB_MASK 0xf00
+#define SISCL_TAP_CONTROL__SISCL_H_NUM_OF_TAPS_Y_RGB__SHIFT 0x8
+#define SISCL_TAP_CONTROL__SISCL_H_NUM_OF_TAPS_CBCR_MASK 0xf000
+#define SISCL_TAP_CONTROL__SISCL_H_NUM_OF_TAPS_CBCR__SHIFT 0xc
+#define SISCL_DEST_SIZE__SISCL_DEST_HEIGHT_MASK 0x7fff
+#define SISCL_DEST_SIZE__SISCL_DEST_HEIGHT__SHIFT 0x0
+#define SISCL_DEST_SIZE__SISCL_DEST_WIDTH_MASK 0x7fff0000
+#define SISCL_DEST_SIZE__SISCL_DEST_WIDTH__SHIFT 0x10
+#define SISCL_HORZ_FILTER_SCALE_RATIO__SISCL_H_SCALE_RATIO_MASK 0x7ffffff
+#define SISCL_HORZ_FILTER_SCALE_RATIO__SISCL_H_SCALE_RATIO__SHIFT 0x0
+#define SISCL_HORZ_FILTER_INIT_Y_RGB__SISCL_H_INIT_FRAC_Y_RGB_MASK 0xffffff
+#define SISCL_HORZ_FILTER_INIT_Y_RGB__SISCL_H_INIT_FRAC_Y_RGB__SHIFT 0x0
+#define SISCL_HORZ_FILTER_INIT_Y_RGB__SISCL_H_INIT_INT_Y_RGB_MASK 0x1f000000
+#define SISCL_HORZ_FILTER_INIT_Y_RGB__SISCL_H_INIT_INT_Y_RGB__SHIFT 0x18
+#define SISCL_HORZ_FILTER_INIT_CBCR__SISCL_H_INIT_FRAC_CBCR_MASK 0xffffff
+#define SISCL_HORZ_FILTER_INIT_CBCR__SISCL_H_INIT_FRAC_CBCR__SHIFT 0x0
+#define SISCL_HORZ_FILTER_INIT_CBCR__SISCL_H_INIT_INT_CBCR_MASK 0x1f000000
+#define SISCL_HORZ_FILTER_INIT_CBCR__SISCL_H_INIT_INT_CBCR__SHIFT 0x18
+#define SISCL_VERT_FILTER_SCALE_RATIO__SISCL_V_SCALE_RATIO_MASK 0x7ffffff
+#define SISCL_VERT_FILTER_SCALE_RATIO__SISCL_V_SCALE_RATIO__SHIFT 0x0
+#define SISCL_VERT_FILTER_INIT_Y_RGB__SISCL_V_INIT_FRAC_Y_RGB_MASK 0xffffff
+#define SISCL_VERT_FILTER_INIT_Y_RGB__SISCL_V_INIT_FRAC_Y_RGB__SHIFT 0x0
+#define SISCL_VERT_FILTER_INIT_Y_RGB__SISCL_V_INIT_INT_Y_RGB_MASK 0x1f000000
+#define SISCL_VERT_FILTER_INIT_Y_RGB__SISCL_V_INIT_INT_Y_RGB__SHIFT 0x18
+#define SISCL_VERT_FILTER_INIT_CBCR__SISCL_V_INIT_FRAC_CBCR_MASK 0xffffff
+#define SISCL_VERT_FILTER_INIT_CBCR__SISCL_V_INIT_FRAC_CBCR__SHIFT 0x0
+#define SISCL_VERT_FILTER_INIT_CBCR__SISCL_V_INIT_INT_CBCR_MASK 0x1f000000
+#define SISCL_VERT_FILTER_INIT_CBCR__SISCL_V_INIT_INT_CBCR__SHIFT 0x18
+#define SISCL_ROUND_OFFSET__SISCL_ROUND_OFFSET_Y_RGB_MASK 0xffff
+#define SISCL_ROUND_OFFSET__SISCL_ROUND_OFFSET_Y_RGB__SHIFT 0x0
+#define SISCL_ROUND_OFFSET__SISCL_ROUND_OFFSET_CBCR_MASK 0xffff0000
+#define SISCL_ROUND_OFFSET__SISCL_ROUND_OFFSET_CBCR__SHIFT 0x10
+#define SISCL_CLAMP__SISCL_CLAMP_UPPER_Y_RGB_MASK 0xff
+#define SISCL_CLAMP__SISCL_CLAMP_UPPER_Y_RGB__SHIFT 0x0
+#define SISCL_CLAMP__SISCL_CLAMP_LOWER_Y_RGB_MASK 0xff00
+#define SISCL_CLAMP__SISCL_CLAMP_LOWER_Y_RGB__SHIFT 0x8
+#define SISCL_CLAMP__SISCL_CLAMP_UPPER_CBCR_MASK 0xff0000
+#define SISCL_CLAMP__SISCL_CLAMP_UPPER_CBCR__SHIFT 0x10
+#define SISCL_CLAMP__SISCL_CLAMP_LOWER_CBCR_MASK 0xff000000
+#define SISCL_CLAMP__SISCL_CLAMP_LOWER_CBCR__SHIFT 0x18
+#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_FLAG_MASK 0x1
+#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_FLAG__SHIFT 0x0
+#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_ACK_MASK 0x100
+#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_ACK__SHIFT 0x8
+#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_MASK_MASK 0x1000
+#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_MASK__SHIFT 0xc
+#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_INT_STATUS_MASK 0x10000
+#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_INT_STATUS__SHIFT 0x10
+#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_INT_TYPE_MASK 0x100000
+#define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_INT_TYPE__SHIFT 0x14
+#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_FLAG_MASK 0x1
+#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_FLAG__SHIFT 0x0
+#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_ACK_MASK 0x100
+#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_ACK__SHIFT 0x8
+#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_MASK_MASK 0x1000
+#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_MASK__SHIFT 0xc
+#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_INT_STATUS_MASK 0x10000
+#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10
+#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_INT_TYPE_MASK 0x100000
+#define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_INT_TYPE__SHIFT 0x14
+#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_OUTSIDE_PIX_STRATEGY_MASK 0x1
+#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_OUTSIDE_PIX_STRATEGY__SHIFT 0x0
+#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_B_CB_MASK 0xff00
+#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_B_CB__SHIFT 0x8
+#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_G_Y_MASK 0xff0000
+#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_G_Y__SHIFT 0x10
+#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_R_CR_MASK 0xff000000
+#define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_R_CR__SHIFT 0x18
+#define SISCL_TEST_CNTL__SISCL_TEST_CRC_EN_MASK 0x10
+#define SISCL_TEST_CNTL__SISCL_TEST_CRC_EN__SHIFT 0x4
+#define SISCL_TEST_CNTL__SISCL_TEST_CRC_CONT_EN_MASK 0x100
+#define SISCL_TEST_CNTL__SISCL_TEST_CRC_CONT_EN__SHIFT 0x8
+#define SISCL_TEST_CNTL__SISCL_TEST_CRC_DE_ONLY_MASK 0x10000
+#define SISCL_TEST_CNTL__SISCL_TEST_CRC_DE_ONLY__SHIFT 0x10
+#define SISCL_TEST_CRC_RED__SISCL_TEST_CRC_RED_MASK_MASK 0xffff
+#define SISCL_TEST_CRC_RED__SISCL_TEST_CRC_RED_MASK__SHIFT 0x0
+#define SISCL_TEST_CRC_RED__SISCL_TEST_CRC_SIG_RED_MASK 0xffff0000
+#define SISCL_TEST_CRC_RED__SISCL_TEST_CRC_SIG_RED__SHIFT 0x10
+#define SISCL_TEST_CRC_GREEN__SISCL_TEST_CRC_GREEN_MASK_MASK 0xffff
+#define SISCL_TEST_CRC_GREEN__SISCL_TEST_CRC_GREEN_MASK__SHIFT 0x0
+#define SISCL_TEST_CRC_GREEN__SISCL_TEST_CRC_SIG_GREEN_MASK 0xffff0000
+#define SISCL_TEST_CRC_GREEN__SISCL_TEST_CRC_SIG_GREEN__SHIFT 0x10
+#define SISCL_TEST_CRC_BLUE__SISCL_TEST_CRC_BLUE_MASK_MASK 0xffff
+#define SISCL_TEST_CRC_BLUE__SISCL_TEST_CRC_BLUE_MASK__SHIFT 0x0
+#define SISCL_TEST_CRC_BLUE__SISCL_TEST_CRC_SIG_BLUE_MASK 0xffff0000
+#define SISCL_TEST_CRC_BLUE__SISCL_TEST_CRC_SIG_BLUE__SHIFT 0x10
+#define SISCL_BACKPRESSURE_CNT_EN__SISCL_BACKPRESSURE_CNT_EN_MASK 0x1
+#define SISCL_BACKPRESSURE_CNT_EN__SISCL_BACKPRESSURE_CNT_EN__SHIFT 0x0
+#define SISCL_MCIF_BACKPRESSURE_CNT__SISCL_MCIF_Y_MAX_BACKPRESSURE_MASK 0xffff
+#define SISCL_MCIF_BACKPRESSURE_CNT__SISCL_MCIF_Y_MAX_BACKPRESSURE__SHIFT 0x0
+#define SISCL_MCIF_BACKPRESSURE_CNT__SISCL_MCIF_C_MAX_BACKPRESSURE_MASK 0xffff0000
+#define SISCL_MCIF_BACKPRESSURE_CNT__SISCL_MCIF_C_MAX_BACKPRESSURE__SHIFT 0x10
+#define SISCL_TEST_DEBUG_INDEX__SISCL_TEST_DEBUG_INDEX_MASK 0xff
+#define SISCL_TEST_DEBUG_INDEX__SISCL_TEST_DEBUG_INDEX__SHIFT 0x0
+#define SISCL_TEST_DEBUG_INDEX__SISCL_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define SISCL_TEST_DEBUG_INDEX__SISCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define SISCL_TEST_DEBUG_DATA__SISCL_TEST_DEBUG_DATA_MASK 0xffffffff
+#define SISCL_TEST_DEBUG_DATA__SISCL_TEST_DEBUG_DATA__SHIFT 0x0
+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP_MASK 0x300
+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP__SHIFT 0x8
+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID_MASK 0xf000
+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID__SHIFT 0xc
+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV_MASK 0x10000
+#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV__SHIFT 0x10
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE_MASK 0xf
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE__SHIFT 0x0
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT_MASK 0x70
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT__SHIFT 0x4
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH_MASK 0x300
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH__SHIFT 0x8
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT_MASK 0xc00
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT__SHIFT 0xa
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT_MASK 0x3000
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT__SHIFT 0xc
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS_MASK 0x300000
+#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS__SHIFT 0x14
+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE_MASK 0x7
+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE__SHIFT 0x0
+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE_MASK 0x700000
+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE__SHIFT 0x14
+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG_MASK 0xf8000000
+#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG__SHIFT 0x1b
+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT_MASK 0x100
+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT__SHIFT 0x8
+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK_MASK 0x200
+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK__SHIFT 0x9
+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK_MASK 0x400
+#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK__SHIFT 0xa
+#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT_MASK 0x1000
+#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT__SHIFT 0xc
+#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK_MASK 0x2000
+#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK__SHIFT 0xd
+#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK_MASK 0x4000
+#define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK__SHIFT 0xe
+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT_MASK 0x10000
+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT__SHIFT 0x10
+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK_MASK 0x20000
+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK__SHIFT 0x11
+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK_MASK 0x40000
+#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK__SHIFT 0x12
+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT_MASK 0x100000
+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT__SHIFT 0x14
+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK_MASK 0x200000
+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK__SHIFT 0x15
+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK_MASK 0x400000
+#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK__SHIFT 0x16
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY_MASK 0xf
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY__SHIFT 0x0
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY_MASK 0xff0
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY__SHIFT 0x4
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS_MASK 0x8000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS__SHIFT 0xf
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS_MASK 0x10000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS__SHIFT 0x10
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0_MASK 0x20000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0__SHIFT 0x11
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1_MASK 0x40000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1__SHIFT 0x12
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2_MASK 0x80000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2__SHIFT 0x13
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3_MASK 0x100000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3__SHIFT 0x14
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4_MASK 0x200000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4__SHIFT 0x15
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5_MASK 0x400000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5__SHIFT 0x16
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS_MASK 0x800000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS__SHIFT 0x17
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS_MASK 0x1000000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS__SHIFT 0x18
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS_MASK 0x2000000
+#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS__SHIFT 0x19
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS_MASK 0x1
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS_MASK 0x100
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS__SHIFT 0x8
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE_MASK 0x10000
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x10
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE_MASK 0x1000000
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x18
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE_MASK 0xc0000000
+#define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE__SHIFT 0x1e
+#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS_MASK 0xf
+#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS__SHIFT 0x0
+#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR_MASK 0x100
+#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR__SHIFT 0x8
+#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS_MASK 0xff
+#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS__SHIFT 0x0
+#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY_MASK 0x1
+#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY__SHIFT 0x0
+#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX_MASK 0xff
+#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT 0x0
+#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA_MASK 0xffffffff
+#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA__SHIFT 0x0
+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY_MASK 0x7
+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY__SHIFT 0x0
+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS_MASK 0x8
+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT 0x3
+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY_MASK 0xffff8000
+#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY__SHIFT 0xf
+#define XDMA_PG_CONTROL__XDMA_PG_CONTROL_MASK 0xffffffff
+#define XDMA_PG_CONTROL__XDMA_PG_CONTROL__SHIFT 0x0
+#define XDMA_PG_WDATA__XDMA_PG_WDATA_MASK 0xffffffff
+#define XDMA_PG_WDATA__XDMA_PG_WDATA__SHIFT 0x0
+#define XDMA_PG_STATUS__XDMA_SERDES_RDATA_MASK 0xffffff
+#define XDMA_PG_STATUS__XDMA_SERDES_RDATA__SHIFT 0x0
+#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY_MASK 0x1000000
+#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY__SHIFT 0x18
+#define XDMA_PG_STATUS__XDMA_SERDES_BUSY_MASK 0x2000000
+#define XDMA_PG_STATUS__XDMA_SERDES_BUSY__SHIFT 0x19
+#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS_MASK 0x4000000
+#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS__SHIFT 0x1a
+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX_MASK 0xff
+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX__SHIFT 0x0
+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL_MASK 0x200
+#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL__SHIFT 0x9
+#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA_MASK 0xffffffff
+#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA__SHIFT 0x0
+
+#endif /* DCE_8_0_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h
new file mode 100644
index 000000000000..b1d7cefb4bd1
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h
@@ -0,0 +1,2532 @@
+/*
+ * GFX_7_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GFX_7_0_D_H
+#define GFX_7_0_D_H
+
+#define mmCB_BLEND_RED 0xa105
+#define mmCB_BLEND_GREEN 0xa106
+#define mmCB_BLEND_BLUE 0xa107
+#define mmCB_BLEND_ALPHA 0xa108
+#define mmCB_COLOR_CONTROL 0xa202
+#define mmCB_BLEND0_CONTROL 0xa1e0
+#define mmCB_BLEND1_CONTROL 0xa1e1
+#define mmCB_BLEND2_CONTROL 0xa1e2
+#define mmCB_BLEND3_CONTROL 0xa1e3
+#define mmCB_BLEND4_CONTROL 0xa1e4
+#define mmCB_BLEND5_CONTROL 0xa1e5
+#define mmCB_BLEND6_CONTROL 0xa1e6
+#define mmCB_BLEND7_CONTROL 0xa1e7
+#define mmCB_COLOR0_BASE 0xa318
+#define mmCB_COLOR1_BASE 0xa327
+#define mmCB_COLOR2_BASE 0xa336
+#define mmCB_COLOR3_BASE 0xa345
+#define mmCB_COLOR4_BASE 0xa354
+#define mmCB_COLOR5_BASE 0xa363
+#define mmCB_COLOR6_BASE 0xa372
+#define mmCB_COLOR7_BASE 0xa381
+#define mmCB_COLOR0_PITCH 0xa319
+#define mmCB_COLOR1_PITCH 0xa328
+#define mmCB_COLOR2_PITCH 0xa337
+#define mmCB_COLOR3_PITCH 0xa346
+#define mmCB_COLOR4_PITCH 0xa355
+#define mmCB_COLOR5_PITCH 0xa364
+#define mmCB_COLOR6_PITCH 0xa373
+#define mmCB_COLOR7_PITCH 0xa382
+#define mmCB_COLOR0_SLICE 0xa31a
+#define mmCB_COLOR1_SLICE 0xa329
+#define mmCB_COLOR2_SLICE 0xa338
+#define mmCB_COLOR3_SLICE 0xa347
+#define mmCB_COLOR4_SLICE 0xa356
+#define mmCB_COLOR5_SLICE 0xa365
+#define mmCB_COLOR6_SLICE 0xa374
+#define mmCB_COLOR7_SLICE 0xa383
+#define mmCB_COLOR0_VIEW 0xa31b
+#define mmCB_COLOR1_VIEW 0xa32a
+#define mmCB_COLOR2_VIEW 0xa339
+#define mmCB_COLOR3_VIEW 0xa348
+#define mmCB_COLOR4_VIEW 0xa357
+#define mmCB_COLOR5_VIEW 0xa366
+#define mmCB_COLOR6_VIEW 0xa375
+#define mmCB_COLOR7_VIEW 0xa384
+#define mmCB_COLOR0_INFO 0xa31c
+#define mmCB_COLOR1_INFO 0xa32b
+#define mmCB_COLOR2_INFO 0xa33a
+#define mmCB_COLOR3_INFO 0xa349
+#define mmCB_COLOR4_INFO 0xa358
+#define mmCB_COLOR5_INFO 0xa367
+#define mmCB_COLOR6_INFO 0xa376
+#define mmCB_COLOR7_INFO 0xa385
+#define mmCB_COLOR0_ATTRIB 0xa31d
+#define mmCB_COLOR1_ATTRIB 0xa32c
+#define mmCB_COLOR2_ATTRIB 0xa33b
+#define mmCB_COLOR3_ATTRIB 0xa34a
+#define mmCB_COLOR4_ATTRIB 0xa359
+#define mmCB_COLOR5_ATTRIB 0xa368
+#define mmCB_COLOR6_ATTRIB 0xa377
+#define mmCB_COLOR7_ATTRIB 0xa386
+#define mmCB_COLOR0_CMASK 0xa31f
+#define mmCB_COLOR1_CMASK 0xa32e
+#define mmCB_COLOR2_CMASK 0xa33d
+#define mmCB_COLOR3_CMASK 0xa34c
+#define mmCB_COLOR4_CMASK 0xa35b
+#define mmCB_COLOR5_CMASK 0xa36a
+#define mmCB_COLOR6_CMASK 0xa379
+#define mmCB_COLOR7_CMASK 0xa388
+#define mmCB_COLOR0_CMASK_SLICE 0xa320
+#define mmCB_COLOR1_CMASK_SLICE 0xa32f
+#define mmCB_COLOR2_CMASK_SLICE 0xa33e
+#define mmCB_COLOR3_CMASK_SLICE 0xa34d
+#define mmCB_COLOR4_CMASK_SLICE 0xa35c
+#define mmCB_COLOR5_CMASK_SLICE 0xa36b
+#define mmCB_COLOR6_CMASK_SLICE 0xa37a
+#define mmCB_COLOR7_CMASK_SLICE 0xa389
+#define mmCB_COLOR0_FMASK 0xa321
+#define mmCB_COLOR1_FMASK 0xa330
+#define mmCB_COLOR2_FMASK 0xa33f
+#define mmCB_COLOR3_FMASK 0xa34e
+#define mmCB_COLOR4_FMASK 0xa35d
+#define mmCB_COLOR5_FMASK 0xa36c
+#define mmCB_COLOR6_FMASK 0xa37b
+#define mmCB_COLOR7_FMASK 0xa38a
+#define mmCB_COLOR0_FMASK_SLICE 0xa322
+#define mmCB_COLOR1_FMASK_SLICE 0xa331
+#define mmCB_COLOR2_FMASK_SLICE 0xa340
+#define mmCB_COLOR3_FMASK_SLICE 0xa34f
+#define mmCB_COLOR4_FMASK_SLICE 0xa35e
+#define mmCB_COLOR5_FMASK_SLICE 0xa36d
+#define mmCB_COLOR6_FMASK_SLICE 0xa37c
+#define mmCB_COLOR7_FMASK_SLICE 0xa38b
+#define mmCB_COLOR0_CLEAR_WORD0 0xa323
+#define mmCB_COLOR1_CLEAR_WORD0 0xa332
+#define mmCB_COLOR2_CLEAR_WORD0 0xa341
+#define mmCB_COLOR3_CLEAR_WORD0 0xa350
+#define mmCB_COLOR4_CLEAR_WORD0 0xa35f
+#define mmCB_COLOR5_CLEAR_WORD0 0xa36e
+#define mmCB_COLOR6_CLEAR_WORD0 0xa37d
+#define mmCB_COLOR7_CLEAR_WORD0 0xa38c
+#define mmCB_COLOR0_CLEAR_WORD1 0xa324
+#define mmCB_COLOR1_CLEAR_WORD1 0xa333
+#define mmCB_COLOR2_CLEAR_WORD1 0xa342
+#define mmCB_COLOR3_CLEAR_WORD1 0xa351
+#define mmCB_COLOR4_CLEAR_WORD1 0xa360
+#define mmCB_COLOR5_CLEAR_WORD1 0xa36f
+#define mmCB_COLOR6_CLEAR_WORD1 0xa37e
+#define mmCB_COLOR7_CLEAR_WORD1 0xa38d
+#define mmCB_TARGET_MASK 0xa08e
+#define mmCB_SHADER_MASK 0xa08f
+#define mmCB_HW_CONTROL 0x2684
+#define mmCB_HW_CONTROL_1 0x2685
+#define mmCB_HW_CONTROL_2 0x2686
+#define mmCB_HW_CONTROL_3 0x2683
+#define mmCB_PERFCOUNTER_FILTER 0xdc00
+#define mmCB_PERFCOUNTER0_SELECT 0xdc01
+#define mmCB_PERFCOUNTER0_SELECT1 0xdc02
+#define mmCB_PERFCOUNTER1_SELECT 0xdc03
+#define mmCB_PERFCOUNTER2_SELECT 0xdc04
+#define mmCB_PERFCOUNTER3_SELECT 0xdc05
+#define mmCB_PERFCOUNTER0_LO 0xd406
+#define mmCB_PERFCOUNTER1_LO 0xd408
+#define mmCB_PERFCOUNTER2_LO 0xd40a
+#define mmCB_PERFCOUNTER3_LO 0xd40c
+#define mmCB_PERFCOUNTER0_HI 0xd407
+#define mmCB_PERFCOUNTER1_HI 0xd409
+#define mmCB_PERFCOUNTER2_HI 0xd40b
+#define mmCB_PERFCOUNTER3_HI 0xd40d
+#define mmCB_CGTT_SCLK_CTRL 0xf0a8
+#define mmCB_DEBUG_BUS_1 0x2699
+#define mmCB_DEBUG_BUS_2 0x269a
+#define mmCB_DEBUG_BUS_3 0x269b
+#define mmCB_DEBUG_BUS_4 0x269c
+#define mmCB_DEBUG_BUS_5 0x269d
+#define mmCB_DEBUG_BUS_6 0x269e
+#define mmCB_DEBUG_BUS_7 0x269f
+#define mmCB_DEBUG_BUS_8 0x26a0
+#define mmCB_DEBUG_BUS_9 0x26a1
+#define mmCB_DEBUG_BUS_10 0x26a2
+#define mmCB_DEBUG_BUS_11 0x26a3
+#define mmCB_DEBUG_BUS_12 0x26a4
+#define mmCB_DEBUG_BUS_13 0x26a5
+#define mmCB_DEBUG_BUS_14 0x26a6
+#define mmCB_DEBUG_BUS_15 0x26a7
+#define mmCB_DEBUG_BUS_16 0x26a8
+#define mmCB_DEBUG_BUS_17 0x26a9
+#define mmCB_DEBUG_BUS_18 0x26aa
+#define mmCP_DFY_CNTL 0x3020
+#define mmCP_DFY_STAT 0x3021
+#define mmCP_DFY_ADDR_HI 0x3022
+#define mmCP_DFY_ADDR_LO 0x3023
+#define mmCP_DFY_DATA_0 0x3024
+#define mmCP_DFY_DATA_1 0x3025
+#define mmCP_DFY_DATA_2 0x3026
+#define mmCP_DFY_DATA_3 0x3027
+#define mmCP_DFY_DATA_4 0x3028
+#define mmCP_DFY_DATA_5 0x3029
+#define mmCP_DFY_DATA_6 0x302a
+#define mmCP_DFY_DATA_7 0x302b
+#define mmCP_DFY_DATA_8 0x302c
+#define mmCP_DFY_DATA_9 0x302d
+#define mmCP_DFY_DATA_10 0x302e
+#define mmCP_DFY_DATA_11 0x302f
+#define mmCP_DFY_DATA_12 0x3030
+#define mmCP_DFY_DATA_13 0x3031
+#define mmCP_DFY_DATA_14 0x3032
+#define mmCP_DFY_DATA_15 0x3033
+#define mmCP_RB0_BASE 0x3040
+#define mmCP_RB0_BASE_HI 0x30b1
+#define mmCP_RB_BASE 0x3040
+#define mmCP_RB1_BASE 0x3060
+#define mmCP_RB1_BASE_HI 0x30b2
+#define mmCP_RB2_BASE 0x3065
+#define mmCP_RB0_CNTL 0x3041
+#define mmCP_RB_CNTL 0x3041
+#define mmCP_RB1_CNTL 0x3061
+#define mmCP_RB2_CNTL 0x3066
+#define mmCP_RB_RPTR_WR 0x3042
+#define mmCP_RB0_RPTR_ADDR 0x3043
+#define mmCP_RB_RPTR_ADDR 0x3043
+#define mmCP_RB1_RPTR_ADDR 0x3062
+#define mmCP_RB2_RPTR_ADDR 0x3067
+#define mmCP_RB0_RPTR_ADDR_HI 0x3044
+#define mmCP_RB_RPTR_ADDR_HI 0x3044
+#define mmCP_RB1_RPTR_ADDR_HI 0x3063
+#define mmCP_RB2_RPTR_ADDR_HI 0x3068
+#define mmCP_RB0_WPTR 0x3045
+#define mmCP_RB_WPTR 0x3045
+#define mmCP_RB1_WPTR 0x3064
+#define mmCP_RB2_WPTR 0x3069
+#define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046
+#define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047
+#define mmGC_PRIV_MODE 0x3048
+#define mmCP_INT_CNTL 0x3049
+#define mmCP_INT_CNTL_RING0 0x306a
+#define mmCP_INT_CNTL_RING1 0x306b
+#define mmCP_INT_CNTL_RING2 0x306c
+#define mmCP_INT_STATUS 0x304a
+#define mmCP_INT_STATUS_RING0 0x306d
+#define mmCP_INT_STATUS_RING1 0x306e
+#define mmCP_INT_STATUS_RING2 0x306f
+#define mmCP_DEVICE_ID 0x304b
+#define mmCP_RING_PRIORITY_CNTS 0x304c
+#define mmCP_ME0_PIPE_PRIORITY_CNTS 0x304c
+#define mmCP_RING0_PRIORITY 0x304d
+#define mmCP_ME0_PIPE0_PRIORITY 0x304d
+#define mmCP_RING1_PRIORITY 0x304e
+#define mmCP_ME0_PIPE1_PRIORITY 0x304e
+#define mmCP_RING2_PRIORITY 0x304f
+#define mmCP_ME0_PIPE2_PRIORITY 0x304f
+#define mmCP_ENDIAN_SWAP 0x3050
+#define mmCP_RB_VMID 0x3051
+#define mmCP_PFP_UCODE_ADDR 0x3054
+#define mmCP_PFP_UCODE_DATA 0x3055
+#define mmCP_ME_RAM_RADDR 0x3056
+#define mmCP_ME_RAM_WADDR 0x3057
+#define mmCP_ME_RAM_DATA 0x3058
+#define mmCGTT_CPC_CLK_CTRL 0xf0b2
+#define mmCGTT_CPF_CLK_CTRL 0xf0b1
+#define mmCGTT_CP_CLK_CTRL 0xf0b0
+#define mmCP_CE_UCODE_ADDR 0x305a
+#define mmCP_CE_UCODE_DATA 0x305b
+#define mmCP_MEC_ME1_UCODE_ADDR 0x305c
+#define mmCP_MEC_ME1_UCODE_DATA 0x305d
+#define mmCP_MEC_ME2_UCODE_ADDR 0x305e
+#define mmCP_MEC_ME2_UCODE_DATA 0x305f
+#define mmCP_PWR_CNTL 0x3078
+#define mmCP_MEM_SLP_CNTL 0x3079
+#define mmCP_ECC_FIRSTOCCURRENCE 0x307a
+#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x307b
+#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x307c
+#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x307d
+#define mmCP_CPF_DEBUG 0x3080
+#define mmCP_FETCHER_SOURCE 0x3082
+#define mmCP_PQ_WPTR_POLL_CNTL 0x3083
+#define mmCP_PQ_WPTR_POLL_CNTL1 0x3084
+#define mmCPC_INT_CNTL 0x30b4
+#define mmCP_ME1_PIPE0_INT_CNTL 0x3085
+#define mmCP_ME1_PIPE1_INT_CNTL 0x3086
+#define mmCP_ME1_PIPE2_INT_CNTL 0x3087
+#define mmCP_ME1_PIPE3_INT_CNTL 0x3088
+#define mmCP_ME2_PIPE0_INT_CNTL 0x3089
+#define mmCP_ME2_PIPE1_INT_CNTL 0x308a
+#define mmCP_ME2_PIPE2_INT_CNTL 0x308b
+#define mmCP_ME2_PIPE3_INT_CNTL 0x308c
+#define mmCPC_INT_STATUS 0x30b5
+#define mmCP_ME1_PIPE0_INT_STATUS 0x308d
+#define mmCP_ME1_PIPE1_INT_STATUS 0x308e
+#define mmCP_ME1_PIPE2_INT_STATUS 0x308f
+#define mmCP_ME1_PIPE3_INT_STATUS 0x3090
+#define mmCP_ME2_PIPE0_INT_STATUS 0x3091
+#define mmCP_ME2_PIPE1_INT_STATUS 0x3092
+#define mmCP_ME2_PIPE2_INT_STATUS 0x3093
+#define mmCP_ME2_PIPE3_INT_STATUS 0x3094
+#define mmCP_ME1_INT_STAT_DEBUG 0x3095
+#define mmCP_ME2_INT_STAT_DEBUG 0x3096
+#define mmCP_ME1_PIPE_PRIORITY_CNTS 0x3099
+#define mmCP_ME1_PIPE0_PRIORITY 0x309a
+#define mmCP_ME1_PIPE1_PRIORITY 0x309b
+#define mmCP_ME1_PIPE2_PRIORITY 0x309c
+#define mmCP_ME1_PIPE3_PRIORITY 0x309d
+#define mmCP_ME2_PIPE_PRIORITY_CNTS 0x309e
+#define mmCP_ME2_PIPE0_PRIORITY 0x309f
+#define mmCP_ME2_PIPE1_PRIORITY 0x30a0
+#define mmCP_ME2_PIPE2_PRIORITY 0x30a1
+#define mmCP_ME2_PIPE3_PRIORITY 0x30a2
+#define mmCP_CE_PRGRM_CNTR_START 0x30a3
+#define mmCP_PFP_PRGRM_CNTR_START 0x30a4
+#define mmCP_ME_PRGRM_CNTR_START 0x30a5
+#define mmCP_MEC1_PRGRM_CNTR_START 0x30a6
+#define mmCP_MEC2_PRGRM_CNTR_START 0x30a7
+#define mmCP_CE_INTR_ROUTINE_START 0x30a8
+#define mmCP_PFP_INTR_ROUTINE_START 0x30a9
+#define mmCP_ME_INTR_ROUTINE_START 0x30aa
+#define mmCP_MEC1_INTR_ROUTINE_START 0x30ab
+#define mmCP_MEC2_INTR_ROUTINE_START 0x30ac
+#define mmCP_CONTEXT_CNTL 0x30ad
+#define mmCP_MAX_CONTEXT 0x30ae
+#define mmCP_IQ_WAIT_TIME1 0x30af
+#define mmCP_IQ_WAIT_TIME2 0x30b0
+#define mmCP_VMID_RESET 0x30b3
+#define mmCP_VMID_PREEMPT 0x30b6
+#define mmCP_PQ_STATUS 0x30b8
+#define mmCP_CPC_STATUS 0x2084
+#define mmCP_CPC_BUSY_STAT 0x2085
+#define mmCP_CPC_STALLED_STAT1 0x2086
+#define mmCP_CPF_STATUS 0x2087
+#define mmCP_CPF_BUSY_STAT 0x2088
+#define mmCP_CPF_STALLED_STAT1 0x2089
+#define mmCP_CPC_MC_CNTL 0x208a
+#define mmCP_CPC_GRBM_FREE_COUNT 0x208b
+#define mmCP_MEC_CNTL 0x208d
+#define mmCP_MEC_ME1_HEADER_DUMP 0x208e
+#define mmCP_MEC_ME2_HEADER_DUMP 0x208f
+#define mmCP_CPC_SCRATCH_INDEX 0x2090
+#define mmCP_CPC_SCRATCH_DATA 0x2091
+#define mmCPG_PERFCOUNTER1_SELECT 0xd800
+#define mmCPG_PERFCOUNTER1_LO 0xd000
+#define mmCPG_PERFCOUNTER1_HI 0xd001
+#define mmCPG_PERFCOUNTER0_SELECT1 0xd801
+#define mmCPG_PERFCOUNTER0_SELECT 0xd802
+#define mmCPG_PERFCOUNTER0_LO 0xd002
+#define mmCPG_PERFCOUNTER0_HI 0xd003
+#define mmCPC_PERFCOUNTER1_SELECT 0xd803
+#define mmCPC_PERFCOUNTER1_LO 0xd004
+#define mmCPC_PERFCOUNTER1_HI 0xd005
+#define mmCPC_PERFCOUNTER0_SELECT1 0xd804
+#define mmCPC_PERFCOUNTER0_SELECT 0xd809
+#define mmCPC_PERFCOUNTER0_LO 0xd006
+#define mmCPC_PERFCOUNTER0_HI 0xd007
+#define mmCPF_PERFCOUNTER1_SELECT 0xd805
+#define mmCPF_PERFCOUNTER1_LO 0xd008
+#define mmCPF_PERFCOUNTER1_HI 0xd009
+#define mmCPF_PERFCOUNTER0_SELECT1 0xd806
+#define mmCPF_PERFCOUNTER0_SELECT 0xd807
+#define mmCPF_PERFCOUNTER0_LO 0xd00a
+#define mmCPF_PERFCOUNTER0_HI 0xd00b
+#define mmCP_CPC_HALT_HYST_COUNT 0x20a7
+#define mmCP_CE_COMPARE_COUNT 0x20c0
+#define mmCP_CE_DE_COUNT 0x20c1
+#define mmCP_DE_CE_COUNT 0x20c2
+#define mmCP_DE_LAST_INVAL_COUNT 0x20c3
+#define mmCP_DE_DE_COUNT 0x20c4
+#define mmCP_EOP_DONE_EVENT_CNTL 0xc0d5
+#define mmCP_EOP_DONE_DATA_CNTL 0xc0d6
+#define mmCP_EOP_DONE_ADDR_LO 0xc000
+#define mmCP_EOP_DONE_ADDR_HI 0xc001
+#define mmCP_EOP_DONE_DATA_LO 0xc002
+#define mmCP_EOP_DONE_DATA_HI 0xc003
+#define mmCP_EOP_LAST_FENCE_LO 0xc004
+#define mmCP_EOP_LAST_FENCE_HI 0xc005
+#define mmCP_STREAM_OUT_ADDR_LO 0xc006
+#define mmCP_STREAM_OUT_ADDR_HI 0xc007
+#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0xc008
+#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0xc009
+#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0xc00a
+#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0xc00b
+#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0xc00c
+#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0xc00d
+#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0xc00e
+#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0xc00f
+#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0xc010
+#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0xc011
+#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0xc012
+#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0xc013
+#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0xc014
+#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0xc015
+#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0xc016
+#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0xc017
+#define mmCP_PIPE_STATS_ADDR_LO 0xc018
+#define mmCP_PIPE_STATS_ADDR_HI 0xc019
+#define mmCP_VGT_IAVERT_COUNT_LO 0xc01a
+#define mmCP_VGT_IAVERT_COUNT_HI 0xc01b
+#define mmCP_VGT_IAPRIM_COUNT_LO 0xc01c
+#define mmCP_VGT_IAPRIM_COUNT_HI 0xc01d
+#define mmCP_VGT_GSPRIM_COUNT_LO 0xc01e
+#define mmCP_VGT_GSPRIM_COUNT_HI 0xc01f
+#define mmCP_VGT_VSINVOC_COUNT_LO 0xc020
+#define mmCP_VGT_VSINVOC_COUNT_HI 0xc021
+#define mmCP_VGT_GSINVOC_COUNT_LO 0xc022
+#define mmCP_VGT_GSINVOC_COUNT_HI 0xc023
+#define mmCP_VGT_HSINVOC_COUNT_LO 0xc024
+#define mmCP_VGT_HSINVOC_COUNT_HI 0xc025
+#define mmCP_VGT_DSINVOC_COUNT_LO 0xc026
+#define mmCP_VGT_DSINVOC_COUNT_HI 0xc027
+#define mmCP_PA_CINVOC_COUNT_LO 0xc028
+#define mmCP_PA_CINVOC_COUNT_HI 0xc029
+#define mmCP_PA_CPRIM_COUNT_LO 0xc02a
+#define mmCP_PA_CPRIM_COUNT_HI 0xc02b
+#define mmCP_SC_PSINVOC_COUNT0_LO 0xc02c
+#define mmCP_SC_PSINVOC_COUNT0_HI 0xc02d
+#define mmCP_SC_PSINVOC_COUNT1_LO 0xc02e
+#define mmCP_SC_PSINVOC_COUNT1_HI 0xc02f
+#define mmCP_VGT_CSINVOC_COUNT_LO 0xc030
+#define mmCP_VGT_CSINVOC_COUNT_HI 0xc031
+#define mmCP_STRMOUT_CNTL 0xc03f
+#define mmSCRATCH_REG0 0xc040
+#define mmSCRATCH_REG1 0xc041
+#define mmSCRATCH_REG2 0xc042
+#define mmSCRATCH_REG3 0xc043
+#define mmSCRATCH_REG4 0xc044
+#define mmSCRATCH_REG5 0xc045
+#define mmSCRATCH_REG6 0xc046
+#define mmSCRATCH_REG7 0xc047
+#define mmSCRATCH_UMSK 0xc050
+#define mmSCRATCH_ADDR 0xc051
+#define mmCP_PFP_ATOMIC_PREOP_LO 0xc052
+#define mmCP_PFP_ATOMIC_PREOP_HI 0xc053
+#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0xc054
+#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0xc055
+#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0xc056
+#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0xc057
+#define mmCP_APPEND_ADDR_LO 0xc058
+#define mmCP_APPEND_ADDR_HI 0xc059
+#define mmCP_APPEND_DATA 0xc05a
+#define mmCP_APPEND_LAST_CS_FENCE 0xc05b
+#define mmCP_APPEND_LAST_PS_FENCE 0xc05c
+#define mmCP_ATOMIC_PREOP_LO 0xc05d
+#define mmCP_ME_ATOMIC_PREOP_LO 0xc05d
+#define mmCP_ATOMIC_PREOP_HI 0xc05e
+#define mmCP_ME_ATOMIC_PREOP_HI 0xc05e
+#define mmCP_GDS_ATOMIC0_PREOP_LO 0xc05f
+#define mmCP_ME_GDS_ATOMIC0_PREOP_LO 0xc05f
+#define mmCP_GDS_ATOMIC0_PREOP_HI 0xc060
+#define mmCP_ME_GDS_ATOMIC0_PREOP_HI 0xc060
+#define mmCP_GDS_ATOMIC1_PREOP_LO 0xc061
+#define mmCP_ME_GDS_ATOMIC1_PREOP_LO 0xc061
+#define mmCP_GDS_ATOMIC1_PREOP_HI 0xc062
+#define mmCP_ME_GDS_ATOMIC1_PREOP_HI 0xc062
+#define mmCP_ME_MC_WADDR_LO 0xc069
+#define mmCP_ME_MC_WADDR_HI 0xc06a
+#define mmCP_ME_MC_WDATA_LO 0xc06b
+#define mmCP_ME_MC_WDATA_HI 0xc06c
+#define mmCP_ME_MC_RADDR_LO 0xc06d
+#define mmCP_ME_MC_RADDR_HI 0xc06e
+#define mmCP_SEM_WAIT_TIMER 0xc06f
+#define mmCP_SIG_SEM_ADDR_LO 0xc070
+#define mmCP_SIG_SEM_ADDR_HI 0xc071
+#define mmCP_SEM_INCOMPLETE_TIMER_CNTL 0xc072
+#define mmCP_WAIT_SEM_STATUS 0xc073
+#define mmCP_WAIT_SEM_ADDR_LO 0xc075
+#define mmCP_WAIT_SEM_ADDR_HI 0xc076
+#define mmCP_WAIT_REG_MEM_TIMEOUT 0xc074
+#define mmCP_COHER_START_DELAY 0xc07b
+#define mmCP_COHER_CNTL 0xc07c
+#define mmCP_COHER_SIZE 0xc07d
+#define mmCP_COHER_SIZE_HI 0xc08c
+#define mmCP_COHER_BASE 0xc07e
+#define mmCP_COHER_BASE_HI 0xc079
+#define mmCP_COHER_STATUS 0xc07f
+#define mmCOHER_DEST_BASE_0 0xa092
+#define mmCOHER_DEST_BASE_1 0xa093
+#define mmCOHER_DEST_BASE_2 0xa07e
+#define mmCOHER_DEST_BASE_3 0xa07f
+#define mmCOHER_DEST_BASE_HI_0 0xa07a
+#define mmCOHER_DEST_BASE_HI_1 0xa07b
+#define mmCOHER_DEST_BASE_HI_2 0xa07c
+#define mmCOHER_DEST_BASE_HI_3 0xa07d
+#define mmCP_DMA_ME_SRC_ADDR 0xc080
+#define mmCP_DMA_ME_SRC_ADDR_HI 0xc081
+#define mmCP_DMA_ME_DST_ADDR 0xc082
+#define mmCP_DMA_ME_DST_ADDR_HI 0xc083
+#define mmCP_DMA_ME_CONTROL 0xc078
+#define mmCP_DMA_ME_COMMAND 0xc084
+#define mmCP_DMA_PFP_SRC_ADDR 0xc085
+#define mmCP_DMA_PFP_SRC_ADDR_HI 0xc086
+#define mmCP_DMA_PFP_DST_ADDR 0xc087
+#define mmCP_DMA_PFP_DST_ADDR_HI 0xc088
+#define mmCP_DMA_PFP_CONTROL 0xc077
+#define mmCP_DMA_PFP_COMMAND 0xc089
+#define mmCP_DMA_CNTL 0xc08a
+#define mmCP_DMA_READ_TAGS 0xc08b
+#define mmCP_PFP_IB_CONTROL 0xc08d
+#define mmCP_PFP_LOAD_CONTROL 0xc08e
+#define mmCP_SCRATCH_INDEX 0xc08f
+#define mmCP_SCRATCH_DATA 0xc090
+#define mmCP_RB_OFFSET 0xc091
+#define mmCP_IB1_OFFSET 0xc092
+#define mmCP_IB2_OFFSET 0xc093
+#define mmCP_IB1_PREAMBLE_BEGIN 0xc094
+#define mmCP_IB1_PREAMBLE_END 0xc095
+#define mmCP_IB2_PREAMBLE_BEGIN 0xc096
+#define mmCP_IB2_PREAMBLE_END 0xc097
+#define mmCP_STALLED_STAT1 0x219d
+#define mmCP_STALLED_STAT2 0x219e
+#define mmCP_STALLED_STAT3 0x219c
+#define mmCP_BUSY_STAT 0x219f
+#define mmCP_STAT 0x21a0
+#define mmCP_ME_HEADER_DUMP 0x21a1
+#define mmCP_PFP_HEADER_DUMP 0x21a2
+#define mmCP_GRBM_FREE_COUNT 0x21a3
+#define mmCP_CE_HEADER_DUMP 0x21a4
+#define mmCP_MC_PACK_DELAY_CNT 0x21a7
+#define mmCP_MC_TAG_CNTL 0x21a8
+#define mmCP_MC_TAG_DATA 0x21a9
+#define mmCP_CSF_STAT 0x21b4
+#define mmCP_CSF_CNTL 0x21b5
+#define mmCP_ME_CNTL 0x21b6
+#define mmCP_CNTX_STAT 0x21b8
+#define mmCP_ME_PREEMPTION 0x21b9
+#define mmCP_RB0_RPTR 0x21c0
+#define mmCP_RB_RPTR 0x21c0
+#define mmCP_RB1_RPTR 0x21bf
+#define mmCP_RB2_RPTR 0x21be
+#define mmCP_RB_WPTR_DELAY 0x21c1
+#define mmCP_RB_WPTR_POLL_CNTL 0x21c2
+#define mmCP_CE_INIT_BASE_LO 0xc0c3
+#define mmCP_CE_INIT_BASE_HI 0xc0c4
+#define mmCP_CE_INIT_BUFSZ 0xc0c5
+#define mmCP_CE_IB1_BASE_LO 0xc0c6
+#define mmCP_CE_IB1_BASE_HI 0xc0c7
+#define mmCP_CE_IB1_BUFSZ 0xc0c8
+#define mmCP_CE_IB2_BASE_LO 0xc0c9
+#define mmCP_CE_IB2_BASE_HI 0xc0ca
+#define mmCP_CE_IB2_BUFSZ 0xc0cb
+#define mmCP_IB1_BASE_LO 0xc0cc
+#define mmCP_IB1_BASE_HI 0xc0cd
+#define mmCP_IB1_BUFSZ 0xc0ce
+#define mmCP_IB2_BASE_LO 0xc0cf
+#define mmCP_IB2_BASE_HI 0xc0d0
+#define mmCP_IB2_BUFSZ 0xc0d1
+#define mmCP_ST_BASE_LO 0xc0d2
+#define mmCP_ST_BASE_HI 0xc0d3
+#define mmCP_ST_BUFSZ 0xc0d4
+#define mmCP_ROQ_THRESHOLDS 0x21bc
+#define mmCP_MEQ_STQ_THRESHOLD 0x21bd
+#define mmCP_ROQ1_THRESHOLDS 0x21d5
+#define mmCP_ROQ2_THRESHOLDS 0x21d6
+#define mmCP_STQ_THRESHOLDS 0x21d7
+#define mmCP_QUEUE_THRESHOLDS 0x21d8
+#define mmCP_MEQ_THRESHOLDS 0x21d9
+#define mmCP_ROQ_AVAIL 0x21da
+#define mmCP_STQ_AVAIL 0x21db
+#define mmCP_ROQ2_AVAIL 0x21dc
+#define mmCP_MEQ_AVAIL 0x21dd
+#define mmCP_CMD_INDEX 0x21de
+#define mmCP_CMD_DATA 0x21df
+#define mmCP_ROQ_RB_STAT 0x21e0
+#define mmCP_ROQ_IB1_STAT 0x21e1
+#define mmCP_ROQ_IB2_STAT 0x21e2
+#define mmCP_STQ_STAT 0x21e3
+#define mmCP_STQ_WR_STAT 0x21e4
+#define mmCP_MEQ_STAT 0x21e5
+#define mmCP_CEQ1_AVAIL 0x21e6
+#define mmCP_CEQ2_AVAIL 0x21e7
+#define mmCP_CE_ROQ_RB_STAT 0x21e8
+#define mmCP_CE_ROQ_IB1_STAT 0x21e9
+#define mmCP_CE_ROQ_IB2_STAT 0x21ea
+#define mmCP_INT_STAT_DEBUG 0x21f7
+#define mmCP_PERFMON_CNTL 0xd808
+#define mmCP_PERFMON_CNTX_CNTL 0xa0d8
+#define mmCP_RINGID 0xa0d9
+#define mmCP_PIPEID 0xa0d9
+#define mmCP_VMID 0xa0da
+#define mmCP_HPD_ROQ_OFFSETS 0x3240
+#define mmCP_HPD_EOP_BASE_ADDR 0x3241
+#define mmCP_HPD_EOP_BASE_ADDR_HI 0x3242
+#define mmCP_HPD_EOP_VMID 0x3243
+#define mmCP_HPD_EOP_CONTROL 0x3244
+#define mmCP_MQD_BASE_ADDR 0x3245
+#define mmCP_MQD_BASE_ADDR_HI 0x3246
+#define mmCP_HQD_ACTIVE 0x3247
+#define mmCP_HQD_VMID 0x3248
+#define mmCP_HQD_PERSISTENT_STATE 0x3249
+#define mmCP_HQD_PIPE_PRIORITY 0x324a
+#define mmCP_HQD_QUEUE_PRIORITY 0x324b
+#define mmCP_HQD_QUANTUM 0x324c
+#define mmCP_HQD_PQ_BASE 0x324d
+#define mmCP_HQD_PQ_BASE_HI 0x324e
+#define mmCP_HQD_PQ_RPTR 0x324f
+#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x3250
+#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x3251
+#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x3252
+#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x3253
+#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254
+#define mmCP_HQD_PQ_WPTR 0x3255
+#define mmCP_HQD_PQ_CONTROL 0x3256
+#define mmCP_HQD_IB_BASE_ADDR 0x3257
+#define mmCP_HQD_IB_BASE_ADDR_HI 0x3258
+#define mmCP_HQD_IB_RPTR 0x3259
+#define mmCP_HQD_IB_CONTROL 0x325a
+#define mmCP_HQD_IQ_TIMER 0x325b
+#define mmCP_HQD_IQ_RPTR 0x325c
+#define mmCP_HQD_DEQUEUE_REQUEST 0x325d
+#define mmCP_HQD_DMA_OFFLOAD 0x325e
+#define mmCP_HQD_SEMA_CMD 0x325f
+#define mmCP_HQD_MSG_TYPE 0x3260
+#define mmCP_HQD_ATOMIC0_PREOP_LO 0x3261
+#define mmCP_HQD_ATOMIC0_PREOP_HI 0x3262
+#define mmCP_HQD_ATOMIC1_PREOP_LO 0x3263
+#define mmCP_HQD_ATOMIC1_PREOP_HI 0x3264
+#define mmCP_HQD_HQ_SCHEDULER0 0x3265
+#define mmCP_HQD_HQ_SCHEDULER1 0x3266
+#define mmCP_MQD_CONTROL 0x3267
+#define mmDB_Z_READ_BASE 0xa012
+#define mmDB_STENCIL_READ_BASE 0xa013
+#define mmDB_Z_WRITE_BASE 0xa014
+#define mmDB_STENCIL_WRITE_BASE 0xa015
+#define mmDB_DEPTH_INFO 0xa00f
+#define mmDB_Z_INFO 0xa010
+#define mmDB_STENCIL_INFO 0xa011
+#define mmDB_DEPTH_SIZE 0xa016
+#define mmDB_DEPTH_SLICE 0xa017
+#define mmDB_DEPTH_VIEW 0xa002
+#define mmDB_RENDER_CONTROL 0xa000
+#define mmDB_COUNT_CONTROL 0xa001
+#define mmDB_RENDER_OVERRIDE 0xa003
+#define mmDB_RENDER_OVERRIDE2 0xa004
+#define mmDB_EQAA 0xa201
+#define mmDB_SHADER_CONTROL 0xa203
+#define mmDB_DEPTH_BOUNDS_MIN 0xa008
+#define mmDB_DEPTH_BOUNDS_MAX 0xa009
+#define mmDB_STENCIL_CLEAR 0xa00a
+#define mmDB_DEPTH_CLEAR 0xa00b
+#define mmDB_HTILE_DATA_BASE 0xa005
+#define mmDB_HTILE_SURFACE 0xa2af
+#define mmDB_PRELOAD_CONTROL 0xa2b2
+#define mmDB_STENCILREFMASK 0xa10c
+#define mmDB_STENCILREFMASK_BF 0xa10d
+#define mmDB_SRESULTS_COMPARE_STATE0 0xa2b0
+#define mmDB_SRESULTS_COMPARE_STATE1 0xa2b1
+#define mmDB_DEPTH_CONTROL 0xa200
+#define mmDB_STENCIL_CONTROL 0xa10b
+#define mmDB_ALPHA_TO_MASK 0xa2dc
+#define mmDB_PERFCOUNTER0_SELECT 0xdc40
+#define mmDB_PERFCOUNTER1_SELECT 0xdc42
+#define mmDB_PERFCOUNTER2_SELECT 0xdc44
+#define mmDB_PERFCOUNTER3_SELECT 0xdc46
+#define mmDB_PERFCOUNTER0_SELECT1 0xdc41
+#define mmDB_PERFCOUNTER1_SELECT1 0xdc43
+#define mmDB_PERFCOUNTER0_LO 0xd440
+#define mmDB_PERFCOUNTER1_LO 0xd442
+#define mmDB_PERFCOUNTER2_LO 0xd444
+#define mmDB_PERFCOUNTER3_LO 0xd446
+#define mmDB_PERFCOUNTER0_HI 0xd441
+#define mmDB_PERFCOUNTER1_HI 0xd443
+#define mmDB_PERFCOUNTER2_HI 0xd445
+#define mmDB_PERFCOUNTER3_HI 0xd447
+#define mmDB_DEBUG 0x260c
+#define mmDB_DEBUG2 0x260d
+#define mmDB_DEBUG3 0x260e
+#define mmDB_DEBUG4 0x260f
+#define mmDB_CREDIT_LIMIT 0x2614
+#define mmDB_WATERMARKS 0x2615
+#define mmDB_SUBTILE_CONTROL 0x2616
+#define mmDB_FREE_CACHELINES 0x2617
+#define mmDB_FIFO_DEPTH1 0x2618
+#define mmDB_FIFO_DEPTH2 0x2619
+#define mmDB_CGTT_CLK_CTRL_0 0xf0a4
+#define mmDB_ZPASS_COUNT_LOW 0xc3fe
+#define mmDB_ZPASS_COUNT_HI 0xc3ff
+#define mmDB_RING_CONTROL 0x261b
+#define mmDB_READ_DEBUG_0 0x2620
+#define mmDB_READ_DEBUG_1 0x2621
+#define mmDB_READ_DEBUG_2 0x2622
+#define mmDB_READ_DEBUG_3 0x2623
+#define mmDB_READ_DEBUG_4 0x2624
+#define mmDB_READ_DEBUG_5 0x2625
+#define mmDB_READ_DEBUG_6 0x2626
+#define mmDB_READ_DEBUG_7 0x2627
+#define mmDB_READ_DEBUG_8 0x2628
+#define mmDB_READ_DEBUG_9 0x2629
+#define mmDB_READ_DEBUG_A 0x262a
+#define mmDB_READ_DEBUG_B 0x262b
+#define mmDB_READ_DEBUG_C 0x262c
+#define mmDB_READ_DEBUG_D 0x262d
+#define mmDB_READ_DEBUG_E 0x262e
+#define mmDB_READ_DEBUG_F 0x262f
+#define mmDB_OCCLUSION_COUNT0_LOW 0xc3c0
+#define mmDB_OCCLUSION_COUNT0_HI 0xc3c1
+#define mmDB_OCCLUSION_COUNT1_LOW 0xc3c2
+#define mmDB_OCCLUSION_COUNT1_HI 0xc3c3
+#define mmDB_OCCLUSION_COUNT2_LOW 0xc3c4
+#define mmDB_OCCLUSION_COUNT2_HI 0xc3c5
+#define mmDB_OCCLUSION_COUNT3_LOW 0xc3c6
+#define mmDB_OCCLUSION_COUNT3_HI 0xc3c7
+#define mmCC_RB_REDUNDANCY 0x263c
+#define mmCC_RB_BACKEND_DISABLE 0x263d
+#define mmGC_USER_RB_REDUNDANCY 0x26de
+#define mmGC_USER_RB_BACKEND_DISABLE 0x26df
+#define mmGB_ADDR_CONFIG 0x263e
+#define mmGB_BACKEND_MAP 0x263f
+#define mmGB_GPU_ID 0x2640
+#define mmCC_RB_DAISY_CHAIN 0x2641
+#define mmGB_TILE_MODE0 0x2644
+#define mmGB_TILE_MODE1 0x2645
+#define mmGB_TILE_MODE2 0x2646
+#define mmGB_TILE_MODE3 0x2647
+#define mmGB_TILE_MODE4 0x2648
+#define mmGB_TILE_MODE5 0x2649
+#define mmGB_TILE_MODE6 0x264a
+#define mmGB_TILE_MODE7 0x264b
+#define mmGB_TILE_MODE8 0x264c
+#define mmGB_TILE_MODE9 0x264d
+#define mmGB_TILE_MODE10 0x264e
+#define mmGB_TILE_MODE11 0x264f
+#define mmGB_TILE_MODE12 0x2650
+#define mmGB_TILE_MODE13 0x2651
+#define mmGB_TILE_MODE14 0x2652
+#define mmGB_TILE_MODE15 0x2653
+#define mmGB_TILE_MODE16 0x2654
+#define mmGB_TILE_MODE17 0x2655
+#define mmGB_TILE_MODE18 0x2656
+#define mmGB_TILE_MODE19 0x2657
+#define mmGB_TILE_MODE20 0x2658
+#define mmGB_TILE_MODE21 0x2659
+#define mmGB_TILE_MODE22 0x265a
+#define mmGB_TILE_MODE23 0x265b
+#define mmGB_TILE_MODE24 0x265c
+#define mmGB_TILE_MODE25 0x265d
+#define mmGB_TILE_MODE26 0x265e
+#define mmGB_TILE_MODE27 0x265f
+#define mmGB_TILE_MODE28 0x2660
+#define mmGB_TILE_MODE29 0x2661
+#define mmGB_TILE_MODE30 0x2662
+#define mmGB_TILE_MODE31 0x2663
+#define mmGB_MACROTILE_MODE0 0x2664
+#define mmGB_MACROTILE_MODE1 0x2665
+#define mmGB_MACROTILE_MODE2 0x2666
+#define mmGB_MACROTILE_MODE3 0x2667
+#define mmGB_MACROTILE_MODE4 0x2668
+#define mmGB_MACROTILE_MODE5 0x2669
+#define mmGB_MACROTILE_MODE6 0x266a
+#define mmGB_MACROTILE_MODE7 0x266b
+#define mmGB_MACROTILE_MODE8 0x266c
+#define mmGB_MACROTILE_MODE9 0x266d
+#define mmGB_MACROTILE_MODE10 0x266e
+#define mmGB_MACROTILE_MODE11 0x266f
+#define mmGB_MACROTILE_MODE12 0x2670
+#define mmGB_MACROTILE_MODE13 0x2671
+#define mmGB_MACROTILE_MODE14 0x2672
+#define mmGB_MACROTILE_MODE15 0x2673
+#define mmGB_EDC_MODE 0x307e
+#define mmCC_GC_EDC_CONFIG 0x3098
+#define mmRAS_SIGNATURE_CONTROL 0x3380
+#define mmRAS_SIGNATURE_MASK 0x3381
+#define mmRAS_SX_SIGNATURE0 0x3382
+#define mmRAS_SX_SIGNATURE1 0x3383
+#define mmRAS_SX_SIGNATURE2 0x3384
+#define mmRAS_SX_SIGNATURE3 0x3385
+#define mmRAS_DB_SIGNATURE0 0x338b
+#define mmRAS_PA_SIGNATURE0 0x338c
+#define mmRAS_VGT_SIGNATURE0 0x338d
+#define mmRAS_SQ_SIGNATURE0 0x338e
+#define mmRAS_SC_SIGNATURE0 0x338f
+#define mmRAS_SC_SIGNATURE1 0x3390
+#define mmRAS_SC_SIGNATURE2 0x3391
+#define mmRAS_SC_SIGNATURE3 0x3392
+#define mmRAS_SC_SIGNATURE4 0x3393
+#define mmRAS_SC_SIGNATURE5 0x3394
+#define mmRAS_SC_SIGNATURE6 0x3395
+#define mmRAS_SC_SIGNATURE7 0x3396
+#define mmRAS_IA_SIGNATURE0 0x3397
+#define mmRAS_IA_SIGNATURE1 0x3398
+#define mmRAS_SPI_SIGNATURE0 0x3399
+#define mmRAS_SPI_SIGNATURE1 0x339a
+#define mmRAS_TA_SIGNATURE0 0x339b
+#define mmRAS_TD_SIGNATURE0 0x339c
+#define mmRAS_CB_SIGNATURE0 0x339d
+#define mmRAS_BCI_SIGNATURE0 0x339e
+#define mmRAS_BCI_SIGNATURE1 0x339f
+#define mmGRBM_CAM_INDEX 0x3000
+#define mmGRBM_CAM_DATA 0x3001
+#define mmGRBM_CNTL 0x2000
+#define mmGRBM_SKEW_CNTL 0x2001
+#define mmGRBM_PWR_CNTL 0x2003
+#define mmGRBM_STATUS 0x2004
+#define mmGRBM_STATUS2 0x2002
+#define mmGRBM_STATUS_SE0 0x2005
+#define mmGRBM_STATUS_SE1 0x2006
+#define mmGRBM_STATUS_SE2 0x200e
+#define mmGRBM_STATUS_SE3 0x200f
+#define mmGRBM_SOFT_RESET 0x2008
+#define mmGRBM_DEBUG_CNTL 0x2009
+#define mmGRBM_DEBUG_DATA 0x200a
+#define mmGRBM_GFX_INDEX 0xc200
+#define mmGRBM_GFX_CLKEN_CNTL 0x200c
+#define mmGRBM_WAIT_IDLE_CLOCKS 0x200d
+#define mmGRBM_DEBUG 0x2014
+#define mmGRBM_DEBUG_SNAPSHOT 0x2015
+#define mmGRBM_READ_ERROR 0x2016
+#define mmGRBM_READ_ERROR2 0x2017
+#define mmGRBM_INT_CNTL 0x2018
+#define mmGRBM_PERFCOUNTER0_SELECT 0xd840
+#define mmGRBM_PERFCOUNTER1_SELECT 0xd841
+#define mmGRBM_SE0_PERFCOUNTER_SELECT 0xd842
+#define mmGRBM_SE1_PERFCOUNTER_SELECT 0xd843
+#define mmGRBM_SE2_PERFCOUNTER_SELECT 0xd844
+#define mmGRBM_SE3_PERFCOUNTER_SELECT 0xd845
+#define mmGRBM_PERFCOUNTER0_LO 0xd040
+#define mmGRBM_PERFCOUNTER0_HI 0xd041
+#define mmGRBM_PERFCOUNTER1_LO 0xd043
+#define mmGRBM_PERFCOUNTER1_HI 0xd044
+#define mmGRBM_SE0_PERFCOUNTER_LO 0xd045
+#define mmGRBM_SE0_PERFCOUNTER_HI 0xd046
+#define mmGRBM_SE1_PERFCOUNTER_LO 0xd047
+#define mmGRBM_SE1_PERFCOUNTER_HI 0xd048
+#define mmGRBM_SE2_PERFCOUNTER_LO 0xd049
+#define mmGRBM_SE2_PERFCOUNTER_HI 0xd04a
+#define mmGRBM_SE3_PERFCOUNTER_LO 0xd04b
+#define mmGRBM_SE3_PERFCOUNTER_HI 0xd04c
+#define mmGRBM_SCRATCH_REG0 0x2040
+#define mmGRBM_SCRATCH_REG1 0x2041
+#define mmGRBM_SCRATCH_REG2 0x2042
+#define mmGRBM_SCRATCH_REG3 0x2043
+#define mmGRBM_SCRATCH_REG4 0x2044
+#define mmGRBM_SCRATCH_REG5 0x2045
+#define mmGRBM_SCRATCH_REG6 0x2046
+#define mmGRBM_SCRATCH_REG7 0x2047
+#define mmDEBUG_INDEX 0x203c
+#define mmDEBUG_DATA 0x203d
+#define mmGRBM_NOWHERE 0x203f
+#define mmPA_CL_VPORT_XSCALE 0xa10f
+#define mmPA_CL_VPORT_XOFFSET 0xa110
+#define mmPA_CL_VPORT_YSCALE 0xa111
+#define mmPA_CL_VPORT_YOFFSET 0xa112
+#define mmPA_CL_VPORT_ZSCALE 0xa113
+#define mmPA_CL_VPORT_ZOFFSET 0xa114
+#define mmPA_CL_VPORT_XSCALE_1 0xa115
+#define mmPA_CL_VPORT_XSCALE_2 0xa11b
+#define mmPA_CL_VPORT_XSCALE_3 0xa121
+#define mmPA_CL_VPORT_XSCALE_4 0xa127
+#define mmPA_CL_VPORT_XSCALE_5 0xa12d
+#define mmPA_CL_VPORT_XSCALE_6 0xa133
+#define mmPA_CL_VPORT_XSCALE_7 0xa139
+#define mmPA_CL_VPORT_XSCALE_8 0xa13f
+#define mmPA_CL_VPORT_XSCALE_9 0xa145
+#define mmPA_CL_VPORT_XSCALE_10 0xa14b
+#define mmPA_CL_VPORT_XSCALE_11 0xa151
+#define mmPA_CL_VPORT_XSCALE_12 0xa157
+#define mmPA_CL_VPORT_XSCALE_13 0xa15d
+#define mmPA_CL_VPORT_XSCALE_14 0xa163
+#define mmPA_CL_VPORT_XSCALE_15 0xa169
+#define mmPA_CL_VPORT_XOFFSET_1 0xa116
+#define mmPA_CL_VPORT_XOFFSET_2 0xa11c
+#define mmPA_CL_VPORT_XOFFSET_3 0xa122
+#define mmPA_CL_VPORT_XOFFSET_4 0xa128
+#define mmPA_CL_VPORT_XOFFSET_5 0xa12e
+#define mmPA_CL_VPORT_XOFFSET_6 0xa134
+#define mmPA_CL_VPORT_XOFFSET_7 0xa13a
+#define mmPA_CL_VPORT_XOFFSET_8 0xa140
+#define mmPA_CL_VPORT_XOFFSET_9 0xa146
+#define mmPA_CL_VPORT_XOFFSET_10 0xa14c
+#define mmPA_CL_VPORT_XOFFSET_11 0xa152
+#define mmPA_CL_VPORT_XOFFSET_12 0xa158
+#define mmPA_CL_VPORT_XOFFSET_13 0xa15e
+#define mmPA_CL_VPORT_XOFFSET_14 0xa164
+#define mmPA_CL_VPORT_XOFFSET_15 0xa16a
+#define mmPA_CL_VPORT_YSCALE_1 0xa117
+#define mmPA_CL_VPORT_YSCALE_2 0xa11d
+#define mmPA_CL_VPORT_YSCALE_3 0xa123
+#define mmPA_CL_VPORT_YSCALE_4 0xa129
+#define mmPA_CL_VPORT_YSCALE_5 0xa12f
+#define mmPA_CL_VPORT_YSCALE_6 0xa135
+#define mmPA_CL_VPORT_YSCALE_7 0xa13b
+#define mmPA_CL_VPORT_YSCALE_8 0xa141
+#define mmPA_CL_VPORT_YSCALE_9 0xa147
+#define mmPA_CL_VPORT_YSCALE_10 0xa14d
+#define mmPA_CL_VPORT_YSCALE_11 0xa153
+#define mmPA_CL_VPORT_YSCALE_12 0xa159
+#define mmPA_CL_VPORT_YSCALE_13 0xa15f
+#define mmPA_CL_VPORT_YSCALE_14 0xa165
+#define mmPA_CL_VPORT_YSCALE_15 0xa16b
+#define mmPA_CL_VPORT_YOFFSET_1 0xa118
+#define mmPA_CL_VPORT_YOFFSET_2 0xa11e
+#define mmPA_CL_VPORT_YOFFSET_3 0xa124
+#define mmPA_CL_VPORT_YOFFSET_4 0xa12a
+#define mmPA_CL_VPORT_YOFFSET_5 0xa130
+#define mmPA_CL_VPORT_YOFFSET_6 0xa136
+#define mmPA_CL_VPORT_YOFFSET_7 0xa13c
+#define mmPA_CL_VPORT_YOFFSET_8 0xa142
+#define mmPA_CL_VPORT_YOFFSET_9 0xa148
+#define mmPA_CL_VPORT_YOFFSET_10 0xa14e
+#define mmPA_CL_VPORT_YOFFSET_11 0xa154
+#define mmPA_CL_VPORT_YOFFSET_12 0xa15a
+#define mmPA_CL_VPORT_YOFFSET_13 0xa160
+#define mmPA_CL_VPORT_YOFFSET_14 0xa166
+#define mmPA_CL_VPORT_YOFFSET_15 0xa16c
+#define mmPA_CL_VPORT_ZSCALE_1 0xa119
+#define mmPA_CL_VPORT_ZSCALE_2 0xa11f
+#define mmPA_CL_VPORT_ZSCALE_3 0xa125
+#define mmPA_CL_VPORT_ZSCALE_4 0xa12b
+#define mmPA_CL_VPORT_ZSCALE_5 0xa131
+#define mmPA_CL_VPORT_ZSCALE_6 0xa137
+#define mmPA_CL_VPORT_ZSCALE_7 0xa13d
+#define mmPA_CL_VPORT_ZSCALE_8 0xa143
+#define mmPA_CL_VPORT_ZSCALE_9 0xa149
+#define mmPA_CL_VPORT_ZSCALE_10 0xa14f
+#define mmPA_CL_VPORT_ZSCALE_11 0xa155
+#define mmPA_CL_VPORT_ZSCALE_12 0xa15b
+#define mmPA_CL_VPORT_ZSCALE_13 0xa161
+#define mmPA_CL_VPORT_ZSCALE_14 0xa167
+#define mmPA_CL_VPORT_ZSCALE_15 0xa16d
+#define mmPA_CL_VPORT_ZOFFSET_1 0xa11a
+#define mmPA_CL_VPORT_ZOFFSET_2 0xa120
+#define mmPA_CL_VPORT_ZOFFSET_3 0xa126
+#define mmPA_CL_VPORT_ZOFFSET_4 0xa12c
+#define mmPA_CL_VPORT_ZOFFSET_5 0xa132
+#define mmPA_CL_VPORT_ZOFFSET_6 0xa138
+#define mmPA_CL_VPORT_ZOFFSET_7 0xa13e
+#define mmPA_CL_VPORT_ZOFFSET_8 0xa144
+#define mmPA_CL_VPORT_ZOFFSET_9 0xa14a
+#define mmPA_CL_VPORT_ZOFFSET_10 0xa150
+#define mmPA_CL_VPORT_ZOFFSET_11 0xa156
+#define mmPA_CL_VPORT_ZOFFSET_12 0xa15c
+#define mmPA_CL_VPORT_ZOFFSET_13 0xa162
+#define mmPA_CL_VPORT_ZOFFSET_14 0xa168
+#define mmPA_CL_VPORT_ZOFFSET_15 0xa16e
+#define mmPA_CL_VTE_CNTL 0xa206
+#define mmPA_CL_VS_OUT_CNTL 0xa207
+#define mmPA_CL_NANINF_CNTL 0xa208
+#define mmPA_CL_CLIP_CNTL 0xa204
+#define mmPA_CL_GB_VERT_CLIP_ADJ 0xa2fa
+#define mmPA_CL_GB_VERT_DISC_ADJ 0xa2fb
+#define mmPA_CL_GB_HORZ_CLIP_ADJ 0xa2fc
+#define mmPA_CL_GB_HORZ_DISC_ADJ 0xa2fd
+#define mmPA_CL_UCP_0_X 0xa16f
+#define mmPA_CL_UCP_0_Y 0xa170
+#define mmPA_CL_UCP_0_Z 0xa171
+#define mmPA_CL_UCP_0_W 0xa172
+#define mmPA_CL_UCP_1_X 0xa173
+#define mmPA_CL_UCP_1_Y 0xa174
+#define mmPA_CL_UCP_1_Z 0xa175
+#define mmPA_CL_UCP_1_W 0xa176
+#define mmPA_CL_UCP_2_X 0xa177
+#define mmPA_CL_UCP_2_Y 0xa178
+#define mmPA_CL_UCP_2_Z 0xa179
+#define mmPA_CL_UCP_2_W 0xa17a
+#define mmPA_CL_UCP_3_X 0xa17b
+#define mmPA_CL_UCP_3_Y 0xa17c
+#define mmPA_CL_UCP_3_Z 0xa17d
+#define mmPA_CL_UCP_3_W 0xa17e
+#define mmPA_CL_UCP_4_X 0xa17f
+#define mmPA_CL_UCP_4_Y 0xa180
+#define mmPA_CL_UCP_4_Z 0xa181
+#define mmPA_CL_UCP_4_W 0xa182
+#define mmPA_CL_UCP_5_X 0xa183
+#define mmPA_CL_UCP_5_Y 0xa184
+#define mmPA_CL_UCP_5_Z 0xa185
+#define mmPA_CL_UCP_5_W 0xa186
+#define mmPA_CL_POINT_X_RAD 0xa1f5
+#define mmPA_CL_POINT_Y_RAD 0xa1f6
+#define mmPA_CL_POINT_SIZE 0xa1f7
+#define mmPA_CL_POINT_CULL_RAD 0xa1f8
+#define mmPA_CL_ENHANCE 0x2285
+#define mmPA_CL_RESET_DEBUG 0x2286
+#define mmPA_SU_VTX_CNTL 0xa2f9
+#define mmPA_SU_POINT_SIZE 0xa280
+#define mmPA_SU_POINT_MINMAX 0xa281
+#define mmPA_SU_LINE_CNTL 0xa282
+#define mmPA_SU_LINE_STIPPLE_CNTL 0xa209
+#define mmPA_SU_LINE_STIPPLE_SCALE 0xa20a
+#define mmPA_SU_PRIM_FILTER_CNTL 0xa20b
+#define mmPA_SU_SC_MODE_CNTL 0xa205
+#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0xa2de
+#define mmPA_SU_POLY_OFFSET_CLAMP 0xa2df
+#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0xa2e0
+#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0xa2e1
+#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0xa2e2
+#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0xa2e3
+#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0xa08d
+#define mmPA_SU_LINE_STIPPLE_VALUE 0xc280
+#define mmPA_SU_PERFCOUNTER0_SELECT 0xd900
+#define mmPA_SU_PERFCOUNTER0_SELECT1 0xd901
+#define mmPA_SU_PERFCOUNTER1_SELECT 0xd902
+#define mmPA_SU_PERFCOUNTER1_SELECT1 0xd903
+#define mmPA_SU_PERFCOUNTER2_SELECT 0xd904
+#define mmPA_SU_PERFCOUNTER3_SELECT 0xd905
+#define mmPA_SU_PERFCOUNTER0_LO 0xd100
+#define mmPA_SU_PERFCOUNTER0_HI 0xd101
+#define mmPA_SU_PERFCOUNTER1_LO 0xd102
+#define mmPA_SU_PERFCOUNTER1_HI 0xd103
+#define mmPA_SU_PERFCOUNTER2_LO 0xd104
+#define mmPA_SU_PERFCOUNTER2_HI 0xd105
+#define mmPA_SU_PERFCOUNTER3_LO 0xd106
+#define mmPA_SU_PERFCOUNTER3_HI 0xd107
+#define mmPA_SC_AA_CONFIG 0xa2f8
+#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0xa30e
+#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0xa30f
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0xa2fe
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0xa2ff
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0xa300
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0xa301
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0xa302
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0xa303
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0xa304
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0xa305
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0xa306
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0xa307
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0xa308
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0xa309
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0xa30a
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0xa30b
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0xa30c
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0xa30d
+#define mmPA_SC_CENTROID_PRIORITY_0 0xa2f5
+#define mmPA_SC_CENTROID_PRIORITY_1 0xa2f6
+#define mmPA_SC_CLIPRECT_0_TL 0xa084
+#define mmPA_SC_CLIPRECT_0_BR 0xa085
+#define mmPA_SC_CLIPRECT_1_TL 0xa086
+#define mmPA_SC_CLIPRECT_1_BR 0xa087
+#define mmPA_SC_CLIPRECT_2_TL 0xa088
+#define mmPA_SC_CLIPRECT_2_BR 0xa089
+#define mmPA_SC_CLIPRECT_3_TL 0xa08a
+#define mmPA_SC_CLIPRECT_3_BR 0xa08b
+#define mmPA_SC_CLIPRECT_RULE 0xa083
+#define mmPA_SC_EDGERULE 0xa08c
+#define mmPA_SC_LINE_CNTL 0xa2f7
+#define mmPA_SC_LINE_STIPPLE 0xa283
+#define mmPA_SC_MODE_CNTL_0 0xa292
+#define mmPA_SC_MODE_CNTL_1 0xa293
+#define mmPA_SC_RASTER_CONFIG 0xa0d4
+#define mmPA_SC_RASTER_CONFIG_1 0xa0d5
+#define mmPA_SC_SCREEN_EXTENT_CONTROL 0xa0d6
+#define mmPA_SC_GENERIC_SCISSOR_TL 0xa090
+#define mmPA_SC_GENERIC_SCISSOR_BR 0xa091
+#define mmPA_SC_SCREEN_SCISSOR_TL 0xa00c
+#define mmPA_SC_SCREEN_SCISSOR_BR 0xa00d
+#define mmPA_SC_WINDOW_OFFSET 0xa080
+#define mmPA_SC_WINDOW_SCISSOR_TL 0xa081
+#define mmPA_SC_WINDOW_SCISSOR_BR 0xa082
+#define mmPA_SC_VPORT_SCISSOR_0_TL 0xa094
+#define mmPA_SC_VPORT_SCISSOR_1_TL 0xa096
+#define mmPA_SC_VPORT_SCISSOR_2_TL 0xa098
+#define mmPA_SC_VPORT_SCISSOR_3_TL 0xa09a
+#define mmPA_SC_VPORT_SCISSOR_4_TL 0xa09c
+#define mmPA_SC_VPORT_SCISSOR_5_TL 0xa09e
+#define mmPA_SC_VPORT_SCISSOR_6_TL 0xa0a0
+#define mmPA_SC_VPORT_SCISSOR_7_TL 0xa0a2
+#define mmPA_SC_VPORT_SCISSOR_8_TL 0xa0a4
+#define mmPA_SC_VPORT_SCISSOR_9_TL 0xa0a6
+#define mmPA_SC_VPORT_SCISSOR_10_TL 0xa0a8
+#define mmPA_SC_VPORT_SCISSOR_11_TL 0xa0aa
+#define mmPA_SC_VPORT_SCISSOR_12_TL 0xa0ac
+#define mmPA_SC_VPORT_SCISSOR_13_TL 0xa0ae
+#define mmPA_SC_VPORT_SCISSOR_14_TL 0xa0b0
+#define mmPA_SC_VPORT_SCISSOR_15_TL 0xa0b2
+#define mmPA_SC_VPORT_SCISSOR_0_BR 0xa095
+#define mmPA_SC_VPORT_SCISSOR_1_BR 0xa097
+#define mmPA_SC_VPORT_SCISSOR_2_BR 0xa099
+#define mmPA_SC_VPORT_SCISSOR_3_BR 0xa09b
+#define mmPA_SC_VPORT_SCISSOR_4_BR 0xa09d
+#define mmPA_SC_VPORT_SCISSOR_5_BR 0xa09f
+#define mmPA_SC_VPORT_SCISSOR_6_BR 0xa0a1
+#define mmPA_SC_VPORT_SCISSOR_7_BR 0xa0a3
+#define mmPA_SC_VPORT_SCISSOR_8_BR 0xa0a5
+#define mmPA_SC_VPORT_SCISSOR_9_BR 0xa0a7
+#define mmPA_SC_VPORT_SCISSOR_10_BR 0xa0a9
+#define mmPA_SC_VPORT_SCISSOR_11_BR 0xa0ab
+#define mmPA_SC_VPORT_SCISSOR_12_BR 0xa0ad
+#define mmPA_SC_VPORT_SCISSOR_13_BR 0xa0af
+#define mmPA_SC_VPORT_SCISSOR_14_BR 0xa0b1
+#define mmPA_SC_VPORT_SCISSOR_15_BR 0xa0b3
+#define mmPA_SC_VPORT_ZMIN_0 0xa0b4
+#define mmPA_SC_VPORT_ZMIN_1 0xa0b6
+#define mmPA_SC_VPORT_ZMIN_2 0xa0b8
+#define mmPA_SC_VPORT_ZMIN_3 0xa0ba
+#define mmPA_SC_VPORT_ZMIN_4 0xa0bc
+#define mmPA_SC_VPORT_ZMIN_5 0xa0be
+#define mmPA_SC_VPORT_ZMIN_6 0xa0c0
+#define mmPA_SC_VPORT_ZMIN_7 0xa0c2
+#define mmPA_SC_VPORT_ZMIN_8 0xa0c4
+#define mmPA_SC_VPORT_ZMIN_9 0xa0c6
+#define mmPA_SC_VPORT_ZMIN_10 0xa0c8
+#define mmPA_SC_VPORT_ZMIN_11 0xa0ca
+#define mmPA_SC_VPORT_ZMIN_12 0xa0cc
+#define mmPA_SC_VPORT_ZMIN_13 0xa0ce
+#define mmPA_SC_VPORT_ZMIN_14 0xa0d0
+#define mmPA_SC_VPORT_ZMIN_15 0xa0d2
+#define mmPA_SC_VPORT_ZMAX_0 0xa0b5
+#define mmPA_SC_VPORT_ZMAX_1 0xa0b7
+#define mmPA_SC_VPORT_ZMAX_2 0xa0b9
+#define mmPA_SC_VPORT_ZMAX_3 0xa0bb
+#define mmPA_SC_VPORT_ZMAX_4 0xa0bd
+#define mmPA_SC_VPORT_ZMAX_5 0xa0bf
+#define mmPA_SC_VPORT_ZMAX_6 0xa0c1
+#define mmPA_SC_VPORT_ZMAX_7 0xa0c3
+#define mmPA_SC_VPORT_ZMAX_8 0xa0c5
+#define mmPA_SC_VPORT_ZMAX_9 0xa0c7
+#define mmPA_SC_VPORT_ZMAX_10 0xa0c9
+#define mmPA_SC_VPORT_ZMAX_11 0xa0cb
+#define mmPA_SC_VPORT_ZMAX_12 0xa0cd
+#define mmPA_SC_VPORT_ZMAX_13 0xa0cf
+#define mmPA_SC_VPORT_ZMAX_14 0xa0d1
+#define mmPA_SC_VPORT_ZMAX_15 0xa0d3
+#define mmPA_SC_ENHANCE 0x22fc
+#define mmPA_SC_FIFO_SIZE 0x22f3
+#define mmPA_SC_IF_FIFO_SIZE 0x22f5
+#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x22c9
+#define mmPA_SC_LINE_STIPPLE_STATE 0xc281
+#define mmPA_SC_SCREEN_EXTENT_MIN_0 0xc284
+#define mmPA_SC_SCREEN_EXTENT_MAX_0 0xc285
+#define mmPA_SC_SCREEN_EXTENT_MIN_1 0xc286
+#define mmPA_SC_SCREEN_EXTENT_MAX_1 0xc28b
+#define mmPA_SC_PERFCOUNTER0_SELECT 0xd940
+#define mmPA_SC_PERFCOUNTER0_SELECT1 0xd941
+#define mmPA_SC_PERFCOUNTER1_SELECT 0xd942
+#define mmPA_SC_PERFCOUNTER2_SELECT 0xd943
+#define mmPA_SC_PERFCOUNTER3_SELECT 0xd944
+#define mmPA_SC_PERFCOUNTER4_SELECT 0xd945
+#define mmPA_SC_PERFCOUNTER5_SELECT 0xd946
+#define mmPA_SC_PERFCOUNTER6_SELECT 0xd947
+#define mmPA_SC_PERFCOUNTER7_SELECT 0xd948
+#define mmPA_SC_PERFCOUNTER0_LO 0xd140
+#define mmPA_SC_PERFCOUNTER0_HI 0xd141
+#define mmPA_SC_PERFCOUNTER1_LO 0xd142
+#define mmPA_SC_PERFCOUNTER1_HI 0xd143
+#define mmPA_SC_PERFCOUNTER2_LO 0xd144
+#define mmPA_SC_PERFCOUNTER2_HI 0xd145
+#define mmPA_SC_PERFCOUNTER3_LO 0xd146
+#define mmPA_SC_PERFCOUNTER3_HI 0xd147
+#define mmPA_SC_PERFCOUNTER4_LO 0xd148
+#define mmPA_SC_PERFCOUNTER4_HI 0xd149
+#define mmPA_SC_PERFCOUNTER5_LO 0xd14a
+#define mmPA_SC_PERFCOUNTER5_HI 0xd14b
+#define mmPA_SC_PERFCOUNTER6_LO 0xd14c
+#define mmPA_SC_PERFCOUNTER6_HI 0xd14d
+#define mmPA_SC_PERFCOUNTER7_LO 0xd14e
+#define mmPA_SC_PERFCOUNTER7_HI 0xd14f
+#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0xc2a0
+#define mmPA_SC_P3D_TRAP_SCREEN_H 0xc2a1
+#define mmPA_SC_P3D_TRAP_SCREEN_V 0xc2a2
+#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0xc2a3
+#define mmPA_SC_P3D_TRAP_SCREEN_COUNT 0xc2a4
+#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0xc2a8
+#define mmPA_SC_HP3D_TRAP_SCREEN_H 0xc2a9
+#define mmPA_SC_HP3D_TRAP_SCREEN_V 0xc2aa
+#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0xc2ab
+#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0xc2ac
+#define mmPA_SC_TRAP_SCREEN_HV_EN 0xc2b0
+#define mmPA_SC_TRAP_SCREEN_H 0xc2b1
+#define mmPA_SC_TRAP_SCREEN_V 0xc2b2
+#define mmPA_SC_TRAP_SCREEN_OCCURRENCE 0xc2b3
+#define mmPA_SC_TRAP_SCREEN_COUNT 0xc2b4
+#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x22c0
+#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x22c1
+#define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x22c2
+#define mmPA_CL_CNTL_STATUS 0x2284
+#define mmPA_SU_CNTL_STATUS 0x2294
+#define mmPA_SC_FIFO_DEPTH_CNTL 0x2295
+#define mmCGTT_PA_CLK_CTRL 0xf088
+#define mmCGTT_SC_CLK_CTRL 0xf089
+#define mmPA_SU_DEBUG_CNTL 0x2280
+#define mmPA_SU_DEBUG_DATA 0x2281
+#define mmPA_SC_DEBUG_CNTL 0x22f6
+#define mmPA_SC_DEBUG_DATA 0x22f7
+#define ixCLIPPER_DEBUG_REG00 0x0
+#define ixCLIPPER_DEBUG_REG01 0x1
+#define ixCLIPPER_DEBUG_REG02 0x2
+#define ixCLIPPER_DEBUG_REG03 0x3
+#define ixCLIPPER_DEBUG_REG04 0x4
+#define ixCLIPPER_DEBUG_REG05 0x5
+#define ixCLIPPER_DEBUG_REG06 0x6
+#define ixCLIPPER_DEBUG_REG07 0x7
+#define ixCLIPPER_DEBUG_REG08 0x8
+#define ixCLIPPER_DEBUG_REG09 0x9
+#define ixCLIPPER_DEBUG_REG10 0xa
+#define ixCLIPPER_DEBUG_REG11 0xb
+#define ixCLIPPER_DEBUG_REG12 0xc
+#define ixCLIPPER_DEBUG_REG13 0xd
+#define ixCLIPPER_DEBUG_REG14 0xe
+#define ixCLIPPER_DEBUG_REG15 0xf
+#define ixCLIPPER_DEBUG_REG16 0x10
+#define ixCLIPPER_DEBUG_REG17 0x11
+#define ixCLIPPER_DEBUG_REG18 0x12
+#define ixCLIPPER_DEBUG_REG19 0x13
+#define ixSXIFCCG_DEBUG_REG0 0x14
+#define ixSXIFCCG_DEBUG_REG1 0x15
+#define ixSXIFCCG_DEBUG_REG2 0x16
+#define ixSXIFCCG_DEBUG_REG3 0x17
+#define ixSETUP_DEBUG_REG0 0x18
+#define ixSETUP_DEBUG_REG1 0x19
+#define ixSETUP_DEBUG_REG2 0x1a
+#define ixSETUP_DEBUG_REG3 0x1b
+#define ixSETUP_DEBUG_REG4 0x1c
+#define ixSETUP_DEBUG_REG5 0x1d
+#define ixPA_SC_DEBUG_REG0 0x0
+#define ixPA_SC_DEBUG_REG1 0x1
+#define mmCOMPUTE_DISPATCH_INITIATOR 0x2e00
+#define mmCOMPUTE_DIM_X 0x2e01
+#define mmCOMPUTE_DIM_Y 0x2e02
+#define mmCOMPUTE_DIM_Z 0x2e03
+#define mmCOMPUTE_START_X 0x2e04
+#define mmCOMPUTE_START_Y 0x2e05
+#define mmCOMPUTE_START_Z 0x2e06
+#define mmCOMPUTE_NUM_THREAD_X 0x2e07
+#define mmCOMPUTE_NUM_THREAD_Y 0x2e08
+#define mmCOMPUTE_NUM_THREAD_Z 0x2e09
+#define mmCOMPUTE_PIPELINESTAT_ENABLE 0x2e0a
+#define mmCOMPUTE_PERFCOUNT_ENABLE 0x2e0b
+#define mmCOMPUTE_PGM_LO 0x2e0c
+#define mmCOMPUTE_PGM_HI 0x2e0d
+#define mmCOMPUTE_TBA_LO 0x2e0e
+#define mmCOMPUTE_TBA_HI 0x2e0f
+#define mmCOMPUTE_TMA_LO 0x2e10
+#define mmCOMPUTE_TMA_HI 0x2e11
+#define mmCOMPUTE_PGM_RSRC1 0x2e12
+#define mmCOMPUTE_PGM_RSRC2 0x2e13
+#define mmCOMPUTE_VMID 0x2e14
+#define mmCOMPUTE_RESOURCE_LIMITS 0x2e15
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x2e16
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x2e17
+#define mmCOMPUTE_TMPRING_SIZE 0x2e18
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x2e19
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x2e1a
+#define mmCOMPUTE_RESTART_X 0x2e1b
+#define mmCOMPUTE_RESTART_Y 0x2e1c
+#define mmCOMPUTE_RESTART_Z 0x2e1d
+#define mmCOMPUTE_THREAD_TRACE_ENABLE 0x2e1e
+#define mmCOMPUTE_MISC_RESERVED 0x2e1f
+#define mmCOMPUTE_USER_DATA_0 0x2e40
+#define mmCOMPUTE_USER_DATA_1 0x2e41
+#define mmCOMPUTE_USER_DATA_2 0x2e42
+#define mmCOMPUTE_USER_DATA_3 0x2e43
+#define mmCOMPUTE_USER_DATA_4 0x2e44
+#define mmCOMPUTE_USER_DATA_5 0x2e45
+#define mmCOMPUTE_USER_DATA_6 0x2e46
+#define mmCOMPUTE_USER_DATA_7 0x2e47
+#define mmCOMPUTE_USER_DATA_8 0x2e48
+#define mmCOMPUTE_USER_DATA_9 0x2e49
+#define mmCOMPUTE_USER_DATA_10 0x2e4a
+#define mmCOMPUTE_USER_DATA_11 0x2e4b
+#define mmCOMPUTE_USER_DATA_12 0x2e4c
+#define mmCOMPUTE_USER_DATA_13 0x2e4d
+#define mmCOMPUTE_USER_DATA_14 0x2e4e
+#define mmCOMPUTE_USER_DATA_15 0x2e4f
+#define mmCSPRIV_CONNECT 0x0
+#define mmCSPRIV_THREAD_TRACE_TG0 0x1e
+#define mmCSPRIV_THREAD_TRACE_TG1 0x1e
+#define mmCSPRIV_THREAD_TRACE_TG2 0x1e
+#define mmCSPRIV_THREAD_TRACE_TG3 0x1e
+#define mmCSPRIV_THREAD_TRACE_EVENT 0x1f
+#define mmRLC_CNTL 0x30c0
+#define mmRLC_DEBUG_SELECT 0x30c1
+#define mmRLC_DEBUG 0x30c2
+#define mmRLC_MC_CNTL 0x30c3
+#define mmRLC_STAT 0x30c4
+#define mmRLC_SAFE_MODE 0x313a
+#define mmRLC_SOFT_RESET_GPU 0x30c5
+#define mmRLC_MEM_SLP_CNTL 0x30c6
+#define mmRLC_PERFMON_CNTL 0xdcc0
+#define mmRLC_PERFCOUNTER0_SELECT 0xdcc1
+#define mmRLC_PERFCOUNTER1_SELECT 0xdcc2
+#define mmRLC_PERFCOUNTER0_LO 0xd480
+#define mmRLC_PERFCOUNTER1_LO 0xd482
+#define mmRLC_PERFCOUNTER0_HI 0xd481
+#define mmRLC_PERFCOUNTER1_HI 0xd483
+#define mmCGTT_RLC_CLK_CTRL 0xf0b8
+#define mmRLC_LB_CNTL 0x30d9
+#define mmRLC_LB_CNTR_MAX 0x30d2
+#define mmRLC_LB_CNTR_INIT 0x30db
+#define mmRLC_LOAD_BALANCE_CNTR 0x30dc
+#define mmRLC_SAVE_AND_RESTORE_BASE 0x30dd
+#define mmRLC_JUMP_TABLE_RESTORE 0x30de
+#define mmRLC_DRIVER_CPDMA_STATUS 0x30de
+#define mmRLC_PG_DELAY_2 0x30df
+#define mmRLC_GPM_DEBUG_SELECT 0x30e0
+#define mmRLC_GPM_DEBUG 0x30e1
+#define mmRLC_GPM_UCODE_ADDR 0x30e2
+#define mmRLC_GPM_UCODE_DATA 0x30e3
+#define mmRLC_GPU_CLOCK_COUNT_LSB 0x30e4
+#define mmRLC_GPU_CLOCK_COUNT_MSB 0x30e5
+#define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0x30e6
+#define mmRLC_UCODE_CNTL 0x30e7
+#define mmRLC_GPM_STAT 0x3100
+#define mmRLC_GPU_CLOCK_32_RES_SEL 0x3101
+#define mmRLC_GPU_CLOCK_32 0x3102
+#define mmRLC_PG_CNTL 0x3103
+#define mmRLC_GPM_THREAD_PRIORITY 0x3104
+#define mmRLC_GPM_THREAD_ENABLE 0x3105
+#define mmRLC_GPM_VMID_THREAD0 0x3106
+#define mmRLC_GPM_VMID_THREAD1 0x3107
+#define mmRLC_CGTT_MGCG_OVERRIDE 0x3108
+#define mmRLC_CGCG_CGLS_CTRL 0x3109
+#define mmRLC_CGCG_RAMP_CTRL 0x310a
+#define mmRLC_DYN_PG_STATUS 0x310b
+#define mmRLC_DYN_PG_REQUEST 0x310c
+#define mmRLC_PG_DELAY 0x310d
+#define mmRLC_CU_STATUS 0x310e
+#define mmRLC_LB_INIT_CU_MASK 0x310f
+#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0x3110
+#define mmRLC_LB_PARAMS 0x3111
+#define mmRLC_THREAD1_DELAY 0x3112
+#define mmRLC_PG_ALWAYS_ON_CU_MASK 0x3113
+#define mmRLC_MAX_PG_CU 0x3114
+#define mmRLC_AUTO_PG_CTRL 0x3115
+#define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0x3116
+#define mmRLC_SMU_PG_CTRL 0x3117
+#define mmRLC_SMU_PG_WAKE_UP_CTRL 0x3118
+#define mmRLC_SERDES_RD_MASTER_INDEX 0x3119
+#define mmRLC_SERDES_RD_DATA_0 0x311a
+#define mmRLC_SERDES_RD_DATA_1 0x311b
+#define mmRLC_SERDES_RD_DATA_2 0x311c
+#define mmRLC_SERDES_WR_CU_MASTER_MASK 0x311d
+#define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0x311e
+#define mmRLC_SERDES_WR_CTRL 0x311f
+#define mmRLC_SERDES_WR_DATA 0x3120
+#define mmRLC_SERDES_CU_MASTER_BUSY 0x3121
+#define mmRLC_SERDES_NONCU_MASTER_BUSY 0x3122
+#define mmRLC_GPM_GENERAL_0 0x3123
+#define mmRLC_GPM_GENERAL_1 0x3124
+#define mmRLC_GPM_GENERAL_2 0x3125
+#define mmRLC_GPM_GENERAL_3 0x3126
+#define mmRLC_GPM_GENERAL_4 0x3127
+#define mmRLC_GPM_GENERAL_5 0x3128
+#define mmRLC_GPM_GENERAL_6 0x3129
+#define mmRLC_GPM_GENERAL_7 0x312a
+#define mmRLC_GPM_CU_PD_TIMEOUT 0x312b
+#define mmRLC_GPM_SCRATCH_ADDR 0x312c
+#define mmRLC_GPM_SCRATCH_DATA 0x312d
+#define mmRLC_STATIC_PG_STATUS 0x312e
+#define mmRLC_GPM_PERF_COUNT_0 0x312f
+#define mmRLC_GPM_PERF_COUNT_1 0x3130
+#define mmRLC_GPR_REG1 0x3139
+#define mmRLC_GPR_REG2 0x313a
+#define mmRLC_SPM_VMID 0x3131
+#define mmRLC_SPM_INT_CNTL 0x3132
+#define mmRLC_SPM_INT_STATUS 0x3133
+#define mmRLC_SPM_DEBUG_SELECT 0x3134
+#define mmRLC_SPM_DEBUG 0x3135
+#define mmRLC_GPM_LOG_ADDR 0x3136
+#define mmRLC_GPM_LOG_SIZE 0x3137
+#define mmRLC_GPM_LOG_CONT 0x3138
+#define mmRLC_SPM_PERFMON_CNTL 0xdc80
+#define mmRLC_SPM_PERFMON_RING_BASE_LO 0xdc81
+#define mmRLC_SPM_PERFMON_RING_BASE_HI 0xdc82
+#define mmRLC_SPM_PERFMON_RING_SIZE 0xdc83
+#define mmRLC_SPM_PERFMON_SEGMENT_SIZE 0xdc84
+#define mmRLC_SPM_SE_MUXSEL_ADDR 0xdc85
+#define mmRLC_SPM_SE_MUXSEL_DATA 0xdc86
+#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0xdc87
+#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0xdc88
+#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0xdc89
+#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0xdc8a
+#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0xdc8b
+#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0xdc8c
+#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0xdc8d
+#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0xdc8e
+#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0xdc90
+#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0xdc91
+#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0xdc92
+#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0xdc93
+#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0xdc94
+#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0xdc95
+#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0xdc96
+#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0xdc97
+#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0xdc98
+#define mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY 0xdc99
+#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0xdc9a
+#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0xdc9b
+#define mmRLC_SPM_GLOBAL_MUXSEL_DATA 0xdc9c
+#define mmRLC_SPM_RING_RDPTR 0xdc9d
+#define mmRLC_SPM_SEGMENT_THRESHOLD 0xdc9e
+#define mmSPI_PS_INPUT_CNTL_0 0xa191
+#define mmSPI_PS_INPUT_CNTL_1 0xa192
+#define mmSPI_PS_INPUT_CNTL_2 0xa193
+#define mmSPI_PS_INPUT_CNTL_3 0xa194
+#define mmSPI_PS_INPUT_CNTL_4 0xa195
+#define mmSPI_PS_INPUT_CNTL_5 0xa196
+#define mmSPI_PS_INPUT_CNTL_6 0xa197
+#define mmSPI_PS_INPUT_CNTL_7 0xa198
+#define mmSPI_PS_INPUT_CNTL_8 0xa199
+#define mmSPI_PS_INPUT_CNTL_9 0xa19a
+#define mmSPI_PS_INPUT_CNTL_10 0xa19b
+#define mmSPI_PS_INPUT_CNTL_11 0xa19c
+#define mmSPI_PS_INPUT_CNTL_12 0xa19d
+#define mmSPI_PS_INPUT_CNTL_13 0xa19e
+#define mmSPI_PS_INPUT_CNTL_14 0xa19f
+#define mmSPI_PS_INPUT_CNTL_15 0xa1a0
+#define mmSPI_PS_INPUT_CNTL_16 0xa1a1
+#define mmSPI_PS_INPUT_CNTL_17 0xa1a2
+#define mmSPI_PS_INPUT_CNTL_18 0xa1a3
+#define mmSPI_PS_INPUT_CNTL_19 0xa1a4
+#define mmSPI_PS_INPUT_CNTL_20 0xa1a5
+#define mmSPI_PS_INPUT_CNTL_21 0xa1a6
+#define mmSPI_PS_INPUT_CNTL_22 0xa1a7
+#define mmSPI_PS_INPUT_CNTL_23 0xa1a8
+#define mmSPI_PS_INPUT_CNTL_24 0xa1a9
+#define mmSPI_PS_INPUT_CNTL_25 0xa1aa
+#define mmSPI_PS_INPUT_CNTL_26 0xa1ab
+#define mmSPI_PS_INPUT_CNTL_27 0xa1ac
+#define mmSPI_PS_INPUT_CNTL_28 0xa1ad
+#define mmSPI_PS_INPUT_CNTL_29 0xa1ae
+#define mmSPI_PS_INPUT_CNTL_30 0xa1af
+#define mmSPI_PS_INPUT_CNTL_31 0xa1b0
+#define mmSPI_VS_OUT_CONFIG 0xa1b1
+#define mmSPI_PS_INPUT_ENA 0xa1b3
+#define mmSPI_PS_INPUT_ADDR 0xa1b4
+#define mmSPI_INTERP_CONTROL_0 0xa1b5
+#define mmSPI_PS_IN_CONTROL 0xa1b6
+#define mmSPI_BARYC_CNTL 0xa1b8
+#define mmSPI_TMPRING_SIZE 0xa1ba
+#define mmSPI_SHADER_POS_FORMAT 0xa1c3
+#define mmSPI_SHADER_Z_FORMAT 0xa1c4
+#define mmSPI_SHADER_COL_FORMAT 0xa1c5
+#define mmSPI_ARB_PRIORITY 0x31c0
+#define mmSPI_ARB_CYCLES_0 0x31c1
+#define mmSPI_ARB_CYCLES_1 0x31c2
+#define mmSPI_CDBG_SYS_GFX 0x31c3
+#define mmSPI_CDBG_SYS_HP3D 0x31c4
+#define mmSPI_CDBG_SYS_CS0 0x31c5
+#define mmSPI_CDBG_SYS_CS1 0x31c6
+#define mmSPI_WCL_PIPE_PERCENT_GFX 0x31c7
+#define mmSPI_WCL_PIPE_PERCENT_HP3D 0x31c8
+#define mmSPI_WCL_PIPE_PERCENT_CS0 0x31c9
+#define mmSPI_WCL_PIPE_PERCENT_CS1 0x31ca
+#define mmSPI_WCL_PIPE_PERCENT_CS2 0x31cb
+#define mmSPI_WCL_PIPE_PERCENT_CS3 0x31cc
+#define mmSPI_WCL_PIPE_PERCENT_CS4 0x31cd
+#define mmSPI_WCL_PIPE_PERCENT_CS5 0x31ce
+#define mmSPI_WCL_PIPE_PERCENT_CS6 0x31cf
+#define mmSPI_WCL_PIPE_PERCENT_CS7 0x31d0
+#define mmSPI_GDBG_WAVE_CNTL 0x31d1
+#define mmSPI_GDBG_TRAP_CONFIG 0x31d2
+#define mmSPI_GDBG_TRAP_MASK 0x31d3
+#define mmSPI_GDBG_TBA_LO 0x31d4
+#define mmSPI_GDBG_TBA_HI 0x31d5
+#define mmSPI_GDBG_TMA_LO 0x31d6
+#define mmSPI_GDBG_TMA_HI 0x31d7
+#define mmSPI_GDBG_TRAP_DATA0 0x31d8
+#define mmSPI_GDBG_TRAP_DATA1 0x31d9
+#define mmSPI_RESET_DEBUG 0x31da
+#define mmSPI_COMPUTE_QUEUE_RESET 0x31db
+#define mmSPI_RESOURCE_RESERVE_CU_0 0x31dc
+#define mmSPI_RESOURCE_RESERVE_CU_1 0x31dd
+#define mmSPI_RESOURCE_RESERVE_CU_2 0x31de
+#define mmSPI_RESOURCE_RESERVE_CU_3 0x31df
+#define mmSPI_RESOURCE_RESERVE_CU_4 0x31e0
+#define mmSPI_RESOURCE_RESERVE_CU_5 0x31e1
+#define mmSPI_RESOURCE_RESERVE_CU_6 0x31e2
+#define mmSPI_RESOURCE_RESERVE_CU_7 0x31e3
+#define mmSPI_RESOURCE_RESERVE_CU_8 0x31e4
+#define mmSPI_RESOURCE_RESERVE_CU_9 0x31e5
+#define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x31e6
+#define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x31e7
+#define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x31e8
+#define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x31e9
+#define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x31ea
+#define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x31eb
+#define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x31ec
+#define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x31ed
+#define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x31ee
+#define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x31ef
+#define mmSPI_PS_MAX_WAVE_ID 0x243a
+#define mmSPI_CONFIG_CNTL 0x2440
+#define mmSPI_DEBUG_CNTL 0x2441
+#define mmSPI_DEBUG_READ 0x2442
+#define mmSPI_PERFCOUNTER0_SELECT 0xd980
+#define mmSPI_PERFCOUNTER1_SELECT 0xd981
+#define mmSPI_PERFCOUNTER2_SELECT 0xd982
+#define mmSPI_PERFCOUNTER3_SELECT 0xd983
+#define mmSPI_PERFCOUNTER0_SELECT1 0xd984
+#define mmSPI_PERFCOUNTER1_SELECT1 0xd985
+#define mmSPI_PERFCOUNTER2_SELECT1 0xd986
+#define mmSPI_PERFCOUNTER3_SELECT1 0xd987
+#define mmSPI_PERFCOUNTER4_SELECT 0xd988
+#define mmSPI_PERFCOUNTER5_SELECT 0xd989
+#define mmSPI_PERFCOUNTER_BINS 0xd98a
+#define mmSPI_PERFCOUNTER0_HI 0xd180
+#define mmSPI_PERFCOUNTER0_LO 0xd181
+#define mmSPI_PERFCOUNTER1_HI 0xd182
+#define mmSPI_PERFCOUNTER1_LO 0xd183
+#define mmSPI_PERFCOUNTER2_HI 0xd184
+#define mmSPI_PERFCOUNTER2_LO 0xd185
+#define mmSPI_PERFCOUNTER3_HI 0xd186
+#define mmSPI_PERFCOUNTER3_LO 0xd187
+#define mmSPI_PERFCOUNTER4_HI 0xd188
+#define mmSPI_PERFCOUNTER4_LO 0xd189
+#define mmSPI_PERFCOUNTER5_HI 0xd18a
+#define mmSPI_PERFCOUNTER5_LO 0xd18b
+#define mmSPI_CONFIG_CNTL_1 0x244f
+#define mmSPI_DEBUG_BUSY 0x2450
+#define mmCGTS_SM_CTRL_REG 0xf000
+#define mmCGTS_RD_CTRL_REG 0xf001
+#define mmCGTS_RD_REG 0xf002
+#define mmCGTS_TCC_DISABLE 0xf003
+#define mmCGTS_USER_TCC_DISABLE 0xf004
+#define mmCGTS_CU0_SP0_CTRL_REG 0xf008
+#define mmCGTS_CU0_LDS_SQ_CTRL_REG 0xf009
+#define mmCGTS_CU0_TA_SQC_CTRL_REG 0xf00a
+#define mmCGTS_CU0_SP1_CTRL_REG 0xf00b
+#define mmCGTS_CU0_TD_TCP_CTRL_REG 0xf00c
+#define mmCGTS_CU1_SP0_CTRL_REG 0xf00d
+#define mmCGTS_CU1_LDS_SQ_CTRL_REG 0xf00e
+#define mmCGTS_CU1_TA_CTRL_REG 0xf00f
+#define mmCGTS_CU1_SP1_CTRL_REG 0xf010
+#define mmCGTS_CU1_TD_TCP_CTRL_REG 0xf011
+#define mmCGTS_CU2_SP0_CTRL_REG 0xf012
+#define mmCGTS_CU2_LDS_SQ_CTRL_REG 0xf013
+#define mmCGTS_CU2_TA_CTRL_REG 0xf014
+#define mmCGTS_CU2_SP1_CTRL_REG 0xf015
+#define mmCGTS_CU2_TD_TCP_CTRL_REG 0xf016
+#define mmCGTS_CU3_SP0_CTRL_REG 0xf017
+#define mmCGTS_CU3_LDS_SQ_CTRL_REG 0xf018
+#define mmCGTS_CU3_TA_CTRL_REG 0xf019
+#define mmCGTS_CU3_SP1_CTRL_REG 0xf01a
+#define mmCGTS_CU3_TD_TCP_CTRL_REG 0xf01b
+#define mmCGTS_CU4_SP0_CTRL_REG 0xf01c
+#define mmCGTS_CU4_LDS_SQ_CTRL_REG 0xf01d
+#define mmCGTS_CU4_TA_SQC_CTRL_REG 0xf01e
+#define mmCGTS_CU4_SP1_CTRL_REG 0xf01f
+#define mmCGTS_CU4_TD_TCP_CTRL_REG 0xf020
+#define mmCGTS_CU5_SP0_CTRL_REG 0xf021
+#define mmCGTS_CU5_LDS_SQ_CTRL_REG 0xf022
+#define mmCGTS_CU5_TA_CTRL_REG 0xf023
+#define mmCGTS_CU5_SP1_CTRL_REG 0xf024
+#define mmCGTS_CU5_TD_TCP_CTRL_REG 0xf025
+#define mmCGTS_CU6_SP0_CTRL_REG 0xf026
+#define mmCGTS_CU6_LDS_SQ_CTRL_REG 0xf027
+#define mmCGTS_CU6_TA_CTRL_REG 0xf028
+#define mmCGTS_CU6_SP1_CTRL_REG 0xf029
+#define mmCGTS_CU6_TD_TCP_CTRL_REG 0xf02a
+#define mmCGTS_CU7_SP0_CTRL_REG 0xf02b
+#define mmCGTS_CU7_LDS_SQ_CTRL_REG 0xf02c
+#define mmCGTS_CU7_TA_CTRL_REG 0xf02d
+#define mmCGTS_CU7_SP1_CTRL_REG 0xf02e
+#define mmCGTS_CU7_TD_TCP_CTRL_REG 0xf02f
+#define mmCGTS_CU8_SP0_CTRL_REG 0xf030
+#define mmCGTS_CU8_LDS_SQ_CTRL_REG 0xf031
+#define mmCGTS_CU8_TA_SQC_CTRL_REG 0xf032
+#define mmCGTS_CU8_SP1_CTRL_REG 0xf033
+#define mmCGTS_CU8_TD_TCP_CTRL_REG 0xf034
+#define mmCGTS_CU9_SP0_CTRL_REG 0xf035
+#define mmCGTS_CU9_LDS_SQ_CTRL_REG 0xf036
+#define mmCGTS_CU9_TA_CTRL_REG 0xf037
+#define mmCGTS_CU9_SP1_CTRL_REG 0xf038
+#define mmCGTS_CU9_TD_TCP_CTRL_REG 0xf039
+#define mmCGTS_CU10_SP0_CTRL_REG 0xf03a
+#define mmCGTS_CU10_LDS_SQ_CTRL_REG 0xf03b
+#define mmCGTS_CU10_TA_CTRL_REG 0xf03c
+#define mmCGTS_CU10_SP1_CTRL_REG 0xf03d
+#define mmCGTS_CU10_TD_TCP_CTRL_REG 0xf03e
+#define mmCGTS_CU11_SP0_CTRL_REG 0xf03f
+#define mmCGTS_CU11_LDS_SQ_CTRL_REG 0xf040
+#define mmCGTS_CU11_TA_CTRL_REG 0xf041
+#define mmCGTS_CU11_SP1_CTRL_REG 0xf042
+#define mmCGTS_CU11_TD_TCP_CTRL_REG 0xf043
+#define mmCGTS_CU12_SP0_CTRL_REG 0xf044
+#define mmCGTS_CU12_LDS_SQ_CTRL_REG 0xf045
+#define mmCGTS_CU12_TA_SQC_CTRL_REG 0xf046
+#define mmCGTS_CU12_SP1_CTRL_REG 0xf047
+#define mmCGTS_CU12_TD_TCP_CTRL_REG 0xf048
+#define mmCGTS_CU13_SP0_CTRL_REG 0xf049
+#define mmCGTS_CU13_LDS_SQ_CTRL_REG 0xf04a
+#define mmCGTS_CU13_TA_CTRL_REG 0xf04b
+#define mmCGTS_CU13_SP1_CTRL_REG 0xf04c
+#define mmCGTS_CU13_TD_TCP_CTRL_REG 0xf04d
+#define mmCGTS_CU14_SP0_CTRL_REG 0xf04e
+#define mmCGTS_CU14_LDS_SQ_CTRL_REG 0xf04f
+#define mmCGTS_CU14_TA_CTRL_REG 0xf050
+#define mmCGTS_CU14_SP1_CTRL_REG 0xf051
+#define mmCGTS_CU14_TD_TCP_CTRL_REG 0xf052
+#define mmCGTS_CU15_SP0_CTRL_REG 0xf053
+#define mmCGTS_CU15_LDS_SQ_CTRL_REG 0xf054
+#define mmCGTS_CU15_TA_CTRL_REG 0xf055
+#define mmCGTS_CU15_SP1_CTRL_REG 0xf056
+#define mmCGTS_CU15_TD_TCP_CTRL_REG 0xf057
+#define mmCGTT_SPI_CLK_CTRL 0xf080
+#define mmCGTT_PC_CLK_CTRL 0xf081
+#define mmCGTT_BCI_CLK_CTRL 0xf082
+#define mmSPI_WF_LIFETIME_CNTL 0x24aa
+#define mmSPI_WF_LIFETIME_LIMIT_0 0x24ab
+#define mmSPI_WF_LIFETIME_LIMIT_1 0x24ac
+#define mmSPI_WF_LIFETIME_LIMIT_2 0x24ad
+#define mmSPI_WF_LIFETIME_LIMIT_3 0x24ae
+#define mmSPI_WF_LIFETIME_LIMIT_4 0x24af
+#define mmSPI_WF_LIFETIME_LIMIT_5 0x24b0
+#define mmSPI_WF_LIFETIME_LIMIT_6 0x24b1
+#define mmSPI_WF_LIFETIME_LIMIT_7 0x24b2
+#define mmSPI_WF_LIFETIME_LIMIT_8 0x24b3
+#define mmSPI_WF_LIFETIME_LIMIT_9 0x24b4
+#define mmSPI_WF_LIFETIME_STATUS_0 0x24b5
+#define mmSPI_WF_LIFETIME_STATUS_1 0x24b6
+#define mmSPI_WF_LIFETIME_STATUS_2 0x24b7
+#define mmSPI_WF_LIFETIME_STATUS_3 0x24b8
+#define mmSPI_WF_LIFETIME_STATUS_4 0x24b9
+#define mmSPI_WF_LIFETIME_STATUS_5 0x24ba
+#define mmSPI_WF_LIFETIME_STATUS_6 0x24bb
+#define mmSPI_WF_LIFETIME_STATUS_7 0x24bc
+#define mmSPI_WF_LIFETIME_STATUS_8 0x24bd
+#define mmSPI_WF_LIFETIME_STATUS_9 0x24be
+#define mmSPI_WF_LIFETIME_STATUS_10 0x24bf
+#define mmSPI_WF_LIFETIME_STATUS_11 0x24c0
+#define mmSPI_WF_LIFETIME_STATUS_12 0x24c1
+#define mmSPI_WF_LIFETIME_STATUS_13 0x24c2
+#define mmSPI_WF_LIFETIME_STATUS_14 0x24c3
+#define mmSPI_WF_LIFETIME_STATUS_15 0x24c4
+#define mmSPI_WF_LIFETIME_STATUS_16 0x24c5
+#define mmSPI_WF_LIFETIME_STATUS_17 0x24c6
+#define mmSPI_WF_LIFETIME_STATUS_18 0x24c7
+#define mmSPI_WF_LIFETIME_STATUS_19 0x24c8
+#define mmSPI_WF_LIFETIME_STATUS_20 0x24c9
+#define mmSPI_WF_LIFETIME_DEBUG 0x24ca
+#define mmSPI_SLAVE_DEBUG_BUSY 0x24d3
+#define mmSPI_LB_CTR_CTRL 0x24d4
+#define mmSPI_LB_CU_MASK 0x24d5
+#define mmSPI_LB_DATA_REG 0x24d6
+#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x24d7
+#define mmSPI_GDS_CREDITS 0x24d8
+#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x24d9
+#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x24da
+#define mmSPI_CSQ_WF_ACTIVE_STATUS 0x24db
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x24dc
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x24dd
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x24de
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x24df
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0x24e0
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0x24e1
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0x24e2
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0x24e3
+#define mmBCI_DEBUG_READ 0x24eb
+#define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x24ec
+#define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x24ed
+#define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x24ee
+#define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x24ef
+#define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x24f0
+#define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x24f1
+#define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x24f2
+#define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x24f3
+#define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x24f4
+#define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x24f5
+#define mmSPI_SHADER_TBA_LO_PS 0x2c00
+#define mmSPI_SHADER_TBA_HI_PS 0x2c01
+#define mmSPI_SHADER_TMA_LO_PS 0x2c02
+#define mmSPI_SHADER_TMA_HI_PS 0x2c03
+#define mmSPI_SHADER_PGM_LO_PS 0x2c08
+#define mmSPI_SHADER_PGM_HI_PS 0x2c09
+#define mmSPI_SHADER_PGM_RSRC1_PS 0x2c0a
+#define mmSPI_SHADER_PGM_RSRC2_PS 0x2c0b
+#define mmSPI_SHADER_PGM_RSRC3_PS 0x2c07
+#define mmSPI_SHADER_USER_DATA_PS_0 0x2c0c
+#define mmSPI_SHADER_USER_DATA_PS_1 0x2c0d
+#define mmSPI_SHADER_USER_DATA_PS_2 0x2c0e
+#define mmSPI_SHADER_USER_DATA_PS_3 0x2c0f
+#define mmSPI_SHADER_USER_DATA_PS_4 0x2c10
+#define mmSPI_SHADER_USER_DATA_PS_5 0x2c11
+#define mmSPI_SHADER_USER_DATA_PS_6 0x2c12
+#define mmSPI_SHADER_USER_DATA_PS_7 0x2c13
+#define mmSPI_SHADER_USER_DATA_PS_8 0x2c14
+#define mmSPI_SHADER_USER_DATA_PS_9 0x2c15
+#define mmSPI_SHADER_USER_DATA_PS_10 0x2c16
+#define mmSPI_SHADER_USER_DATA_PS_11 0x2c17
+#define mmSPI_SHADER_USER_DATA_PS_12 0x2c18
+#define mmSPI_SHADER_USER_DATA_PS_13 0x2c19
+#define mmSPI_SHADER_USER_DATA_PS_14 0x2c1a
+#define mmSPI_SHADER_USER_DATA_PS_15 0x2c1b
+#define mmSPI_SHADER_TBA_LO_VS 0x2c40
+#define mmSPI_SHADER_TBA_HI_VS 0x2c41
+#define mmSPI_SHADER_TMA_LO_VS 0x2c42
+#define mmSPI_SHADER_TMA_HI_VS 0x2c43
+#define mmSPI_SHADER_PGM_LO_VS 0x2c48
+#define mmSPI_SHADER_PGM_HI_VS 0x2c49
+#define mmSPI_SHADER_PGM_RSRC1_VS 0x2c4a
+#define mmSPI_SHADER_PGM_RSRC2_VS 0x2c4b
+#define mmSPI_SHADER_PGM_RSRC3_VS 0x2c46
+#define mmSPI_SHADER_LATE_ALLOC_VS 0x2c47
+#define mmSPI_SHADER_USER_DATA_VS_0 0x2c4c
+#define mmSPI_SHADER_USER_DATA_VS_1 0x2c4d
+#define mmSPI_SHADER_USER_DATA_VS_2 0x2c4e
+#define mmSPI_SHADER_USER_DATA_VS_3 0x2c4f
+#define mmSPI_SHADER_USER_DATA_VS_4 0x2c50
+#define mmSPI_SHADER_USER_DATA_VS_5 0x2c51
+#define mmSPI_SHADER_USER_DATA_VS_6 0x2c52
+#define mmSPI_SHADER_USER_DATA_VS_7 0x2c53
+#define mmSPI_SHADER_USER_DATA_VS_8 0x2c54
+#define mmSPI_SHADER_USER_DATA_VS_9 0x2c55
+#define mmSPI_SHADER_USER_DATA_VS_10 0x2c56
+#define mmSPI_SHADER_USER_DATA_VS_11 0x2c57
+#define mmSPI_SHADER_USER_DATA_VS_12 0x2c58
+#define mmSPI_SHADER_USER_DATA_VS_13 0x2c59
+#define mmSPI_SHADER_USER_DATA_VS_14 0x2c5a
+#define mmSPI_SHADER_USER_DATA_VS_15 0x2c5b
+#define mmSPI_SHADER_PGM_RSRC2_ES_VS 0x2c7c
+#define mmSPI_SHADER_PGM_RSRC2_LS_VS 0x2c7d
+#define mmSPI_SHADER_TBA_LO_GS 0x2c80
+#define mmSPI_SHADER_TBA_HI_GS 0x2c81
+#define mmSPI_SHADER_TMA_LO_GS 0x2c82
+#define mmSPI_SHADER_TMA_HI_GS 0x2c83
+#define mmSPI_SHADER_PGM_LO_GS 0x2c88
+#define mmSPI_SHADER_PGM_HI_GS 0x2c89
+#define mmSPI_SHADER_PGM_RSRC1_GS 0x2c8a
+#define mmSPI_SHADER_PGM_RSRC2_GS 0x2c8b
+#define mmSPI_SHADER_PGM_RSRC3_GS 0x2c87
+#define mmSPI_SHADER_USER_DATA_GS_0 0x2c8c
+#define mmSPI_SHADER_USER_DATA_GS_1 0x2c8d
+#define mmSPI_SHADER_USER_DATA_GS_2 0x2c8e
+#define mmSPI_SHADER_USER_DATA_GS_3 0x2c8f
+#define mmSPI_SHADER_USER_DATA_GS_4 0x2c90
+#define mmSPI_SHADER_USER_DATA_GS_5 0x2c91
+#define mmSPI_SHADER_USER_DATA_GS_6 0x2c92
+#define mmSPI_SHADER_USER_DATA_GS_7 0x2c93
+#define mmSPI_SHADER_USER_DATA_GS_8 0x2c94
+#define mmSPI_SHADER_USER_DATA_GS_9 0x2c95
+#define mmSPI_SHADER_USER_DATA_GS_10 0x2c96
+#define mmSPI_SHADER_USER_DATA_GS_11 0x2c97
+#define mmSPI_SHADER_USER_DATA_GS_12 0x2c98
+#define mmSPI_SHADER_USER_DATA_GS_13 0x2c99
+#define mmSPI_SHADER_USER_DATA_GS_14 0x2c9a
+#define mmSPI_SHADER_USER_DATA_GS_15 0x2c9b
+#define mmSPI_SHADER_PGM_RSRC2_ES_GS 0x2cbc
+#define mmSPI_SHADER_TBA_LO_ES 0x2cc0
+#define mmSPI_SHADER_TBA_HI_ES 0x2cc1
+#define mmSPI_SHADER_TMA_LO_ES 0x2cc2
+#define mmSPI_SHADER_TMA_HI_ES 0x2cc3
+#define mmSPI_SHADER_PGM_LO_ES 0x2cc8
+#define mmSPI_SHADER_PGM_HI_ES 0x2cc9
+#define mmSPI_SHADER_PGM_RSRC1_ES 0x2cca
+#define mmSPI_SHADER_PGM_RSRC2_ES 0x2ccb
+#define mmSPI_SHADER_PGM_RSRC3_ES 0x2cc7
+#define mmSPI_SHADER_USER_DATA_ES_0 0x2ccc
+#define mmSPI_SHADER_USER_DATA_ES_1 0x2ccd
+#define mmSPI_SHADER_USER_DATA_ES_2 0x2cce
+#define mmSPI_SHADER_USER_DATA_ES_3 0x2ccf
+#define mmSPI_SHADER_USER_DATA_ES_4 0x2cd0
+#define mmSPI_SHADER_USER_DATA_ES_5 0x2cd1
+#define mmSPI_SHADER_USER_DATA_ES_6 0x2cd2
+#define mmSPI_SHADER_USER_DATA_ES_7 0x2cd3
+#define mmSPI_SHADER_USER_DATA_ES_8 0x2cd4
+#define mmSPI_SHADER_USER_DATA_ES_9 0x2cd5
+#define mmSPI_SHADER_USER_DATA_ES_10 0x2cd6
+#define mmSPI_SHADER_USER_DATA_ES_11 0x2cd7
+#define mmSPI_SHADER_USER_DATA_ES_12 0x2cd8
+#define mmSPI_SHADER_USER_DATA_ES_13 0x2cd9
+#define mmSPI_SHADER_USER_DATA_ES_14 0x2cda
+#define mmSPI_SHADER_USER_DATA_ES_15 0x2cdb
+#define mmSPI_SHADER_PGM_RSRC2_LS_ES 0x2cfd
+#define mmSPI_SHADER_TBA_LO_HS 0x2d00
+#define mmSPI_SHADER_TBA_HI_HS 0x2d01
+#define mmSPI_SHADER_TMA_LO_HS 0x2d02
+#define mmSPI_SHADER_TMA_HI_HS 0x2d03
+#define mmSPI_SHADER_PGM_LO_HS 0x2d08
+#define mmSPI_SHADER_PGM_HI_HS 0x2d09
+#define mmSPI_SHADER_PGM_RSRC1_HS 0x2d0a
+#define mmSPI_SHADER_PGM_RSRC2_HS 0x2d0b
+#define mmSPI_SHADER_PGM_RSRC3_HS 0x2d07
+#define mmSPI_SHADER_USER_DATA_HS_0 0x2d0c
+#define mmSPI_SHADER_USER_DATA_HS_1 0x2d0d
+#define mmSPI_SHADER_USER_DATA_HS_2 0x2d0e
+#define mmSPI_SHADER_USER_DATA_HS_3 0x2d0f
+#define mmSPI_SHADER_USER_DATA_HS_4 0x2d10
+#define mmSPI_SHADER_USER_DATA_HS_5 0x2d11
+#define mmSPI_SHADER_USER_DATA_HS_6 0x2d12
+#define mmSPI_SHADER_USER_DATA_HS_7 0x2d13
+#define mmSPI_SHADER_USER_DATA_HS_8 0x2d14
+#define mmSPI_SHADER_USER_DATA_HS_9 0x2d15
+#define mmSPI_SHADER_USER_DATA_HS_10 0x2d16
+#define mmSPI_SHADER_USER_DATA_HS_11 0x2d17
+#define mmSPI_SHADER_USER_DATA_HS_12 0x2d18
+#define mmSPI_SHADER_USER_DATA_HS_13 0x2d19
+#define mmSPI_SHADER_USER_DATA_HS_14 0x2d1a
+#define mmSPI_SHADER_USER_DATA_HS_15 0x2d1b
+#define mmSPI_SHADER_PGM_RSRC2_LS_HS 0x2d3d
+#define mmSPI_SHADER_TBA_LO_LS 0x2d40
+#define mmSPI_SHADER_TBA_HI_LS 0x2d41
+#define mmSPI_SHADER_TMA_LO_LS 0x2d42
+#define mmSPI_SHADER_TMA_HI_LS 0x2d43
+#define mmSPI_SHADER_PGM_LO_LS 0x2d48
+#define mmSPI_SHADER_PGM_HI_LS 0x2d49
+#define mmSPI_SHADER_PGM_RSRC1_LS 0x2d4a
+#define mmSPI_SHADER_PGM_RSRC2_LS 0x2d4b
+#define mmSPI_SHADER_PGM_RSRC3_LS 0x2d47
+#define mmSPI_SHADER_USER_DATA_LS_0 0x2d4c
+#define mmSPI_SHADER_USER_DATA_LS_1 0x2d4d
+#define mmSPI_SHADER_USER_DATA_LS_2 0x2d4e
+#define mmSPI_SHADER_USER_DATA_LS_3 0x2d4f
+#define mmSPI_SHADER_USER_DATA_LS_4 0x2d50
+#define mmSPI_SHADER_USER_DATA_LS_5 0x2d51
+#define mmSPI_SHADER_USER_DATA_LS_6 0x2d52
+#define mmSPI_SHADER_USER_DATA_LS_7 0x2d53
+#define mmSPI_SHADER_USER_DATA_LS_8 0x2d54
+#define mmSPI_SHADER_USER_DATA_LS_9 0x2d55
+#define mmSPI_SHADER_USER_DATA_LS_10 0x2d56
+#define mmSPI_SHADER_USER_DATA_LS_11 0x2d57
+#define mmSPI_SHADER_USER_DATA_LS_12 0x2d58
+#define mmSPI_SHADER_USER_DATA_LS_13 0x2d59
+#define mmSPI_SHADER_USER_DATA_LS_14 0x2d5a
+#define mmSPI_SHADER_USER_DATA_LS_15 0x2d5b
+#define mmSQ_CONFIG 0x2300
+#define mmSQC_CONFIG 0x2301
+#define mmSQC_CACHES 0xc348
+#define mmSQ_RANDOM_WAVE_PRI 0x2303
+#define mmSQ_REG_CREDITS 0x2304
+#define mmSQ_FIFO_SIZES 0x2305
+#define mmSQ_INTERRUPT_AUTO_MASK 0x2314
+#define mmSQ_INTERRUPT_MSG_CTRL 0x2315
+#define mmSQ_PERFCOUNTER_CTRL 0xd9e0
+#define mmSQ_PERFCOUNTER_MASK 0xd9e1
+#define mmSQ_PERFCOUNTER_CTRL2 0xd9e2
+#define mmCC_SQC_BANK_DISABLE 0x2307
+#define mmUSER_SQC_BANK_DISABLE 0x2308
+#define mmSQ_PERFCOUNTER0_LO 0xd1c0
+#define mmSQ_PERFCOUNTER1_LO 0xd1c2
+#define mmSQ_PERFCOUNTER2_LO 0xd1c4
+#define mmSQ_PERFCOUNTER3_LO 0xd1c6
+#define mmSQ_PERFCOUNTER4_LO 0xd1c8
+#define mmSQ_PERFCOUNTER5_LO 0xd1ca
+#define mmSQ_PERFCOUNTER6_LO 0xd1cc
+#define mmSQ_PERFCOUNTER7_LO 0xd1ce
+#define mmSQ_PERFCOUNTER8_LO 0xd1d0
+#define mmSQ_PERFCOUNTER9_LO 0xd1d2
+#define mmSQ_PERFCOUNTER10_LO 0xd1d4
+#define mmSQ_PERFCOUNTER11_LO 0xd1d6
+#define mmSQ_PERFCOUNTER12_LO 0xd1d8
+#define mmSQ_PERFCOUNTER13_LO 0xd1da
+#define mmSQ_PERFCOUNTER14_LO 0xd1dc
+#define mmSQ_PERFCOUNTER15_LO 0xd1de
+#define mmSQ_PERFCOUNTER0_HI 0xd1c1
+#define mmSQ_PERFCOUNTER1_HI 0xd1c3
+#define mmSQ_PERFCOUNTER2_HI 0xd1c5
+#define mmSQ_PERFCOUNTER3_HI 0xd1c7
+#define mmSQ_PERFCOUNTER4_HI 0xd1c9
+#define mmSQ_PERFCOUNTER5_HI 0xd1cb
+#define mmSQ_PERFCOUNTER6_HI 0xd1cd
+#define mmSQ_PERFCOUNTER7_HI 0xd1cf
+#define mmSQ_PERFCOUNTER8_HI 0xd1d1
+#define mmSQ_PERFCOUNTER9_HI 0xd1d3
+#define mmSQ_PERFCOUNTER10_HI 0xd1d5
+#define mmSQ_PERFCOUNTER11_HI 0xd1d7
+#define mmSQ_PERFCOUNTER12_HI 0xd1d9
+#define mmSQ_PERFCOUNTER13_HI 0xd1db
+#define mmSQ_PERFCOUNTER14_HI 0xd1dd
+#define mmSQ_PERFCOUNTER15_HI 0xd1df
+#define mmSQ_PERFCOUNTER0_SELECT 0xd9c0
+#define mmSQ_PERFCOUNTER1_SELECT 0xd9c1
+#define mmSQ_PERFCOUNTER2_SELECT 0xd9c2
+#define mmSQ_PERFCOUNTER3_SELECT 0xd9c3
+#define mmSQ_PERFCOUNTER4_SELECT 0xd9c4
+#define mmSQ_PERFCOUNTER5_SELECT 0xd9c5
+#define mmSQ_PERFCOUNTER6_SELECT 0xd9c6
+#define mmSQ_PERFCOUNTER7_SELECT 0xd9c7
+#define mmSQ_PERFCOUNTER8_SELECT 0xd9c8
+#define mmSQ_PERFCOUNTER9_SELECT 0xd9c9
+#define mmSQ_PERFCOUNTER10_SELECT 0xd9ca
+#define mmSQ_PERFCOUNTER11_SELECT 0xd9cb
+#define mmSQ_PERFCOUNTER12_SELECT 0xd9cc
+#define mmSQ_PERFCOUNTER13_SELECT 0xd9cd
+#define mmSQ_PERFCOUNTER14_SELECT 0xd9ce
+#define mmSQ_PERFCOUNTER15_SELECT 0xd9cf
+#define mmCGTT_SQ_CLK_CTRL 0xf08c
+#define mmCGTT_SQG_CLK_CTRL 0xf08d
+#define mmSQ_ALU_CLK_CTRL 0xf08e
+#define mmSQ_TEX_CLK_CTRL 0xf08f
+#define mmSQ_LDS_CLK_CTRL 0xf090
+#define mmSQ_POWER_THROTTLE 0xf091
+#define mmSQ_POWER_THROTTLE2 0xf092
+#define mmSQ_TIME_HI 0x237c
+#define mmSQ_TIME_LO 0x237d
+#define mmSQ_THREAD_TRACE_BASE 0x2380
+#define mmSQ_THREAD_TRACE_BASE2 0x2385
+#define mmSQ_THREAD_TRACE_SIZE 0x2381
+#define mmSQ_THREAD_TRACE_MASK 0x2382
+#define mmSQ_THREAD_TRACE_USERDATA_0 0xc340
+#define mmSQ_THREAD_TRACE_USERDATA_1 0xc341
+#define mmSQ_THREAD_TRACE_USERDATA_2 0xc342
+#define mmSQ_THREAD_TRACE_USERDATA_3 0xc343
+#define mmSQ_THREAD_TRACE_MODE 0x238e
+#define mmSQ_THREAD_TRACE_CTRL 0x238f
+#define mmSQ_THREAD_TRACE_TOKEN_MASK 0x2383
+#define mmSQ_THREAD_TRACE_TOKEN_MASK2 0x2386
+#define mmSQ_THREAD_TRACE_PERF_MASK 0x2384
+#define mmSQ_THREAD_TRACE_WPTR 0x238c
+#define mmSQ_THREAD_TRACE_STATUS 0x238d
+#define mmSQ_THREAD_TRACE_CNTR 0x2390
+#define mmSQ_THREAD_TRACE_HIWATER 0x2392
+#define mmSQ_LB_CTR_CTRL 0x2398
+#define mmSQ_LB_DATA_ALU_CYCLES 0x2399
+#define mmSQ_LB_DATA_TEX_CYCLES 0x239a
+#define mmSQ_LB_DATA_ALU_STALLS 0x239b
+#define mmSQ_LB_DATA_TEX_STALLS 0x239c
+#define mmSQC_SECDED_CNT 0x23a0
+#define mmSQ_SEC_CNT 0x23a1
+#define mmSQ_DED_CNT 0x23a2
+#define mmSQ_DED_INFO 0x23a3
+#define mmSQ_BUF_RSRC_WORD0 0x23c0
+#define mmSQ_BUF_RSRC_WORD1 0x23c1
+#define mmSQ_BUF_RSRC_WORD2 0x23c2
+#define mmSQ_BUF_RSRC_WORD3 0x23c3
+#define mmSQ_IMG_RSRC_WORD0 0x23c4
+#define mmSQ_IMG_RSRC_WORD1 0x23c5
+#define mmSQ_IMG_RSRC_WORD2 0x23c6
+#define mmSQ_IMG_RSRC_WORD3 0x23c7
+#define mmSQ_IMG_RSRC_WORD4 0x23c8
+#define mmSQ_IMG_RSRC_WORD5 0x23c9
+#define mmSQ_IMG_RSRC_WORD6 0x23ca
+#define mmSQ_IMG_RSRC_WORD7 0x23cb
+#define mmSQ_IMG_SAMP_WORD0 0x23cc
+#define mmSQ_IMG_SAMP_WORD1 0x23cd
+#define mmSQ_IMG_SAMP_WORD2 0x23ce
+#define mmSQ_IMG_SAMP_WORD3 0x23cf
+#define mmSQ_FLAT_SCRATCH_WORD0 0x23d0
+#define mmSQ_FLAT_SCRATCH_WORD1 0x23d1
+#define mmSQ_IND_INDEX 0x2378
+#define mmSQ_IND_CMD 0x237a
+#define mmSQ_CMD 0x237b
+#define mmSQ_IND_DATA 0x2379
+#define mmSQ_REG_TIMESTAMP 0x2374
+#define mmSQ_CMD_TIMESTAMP 0x2375
+#define mmSQ_HV_VMID_CTRL 0xf840
+#define ixSQ_WAVE_INST_DW0 0x1a
+#define ixSQ_WAVE_INST_DW1 0x1b
+#define ixSQ_WAVE_PC_LO 0x18
+#define ixSQ_WAVE_PC_HI 0x19
+#define ixSQ_WAVE_IB_DBG0 0x1c
+#define ixSQ_WAVE_EXEC_LO 0x27e
+#define ixSQ_WAVE_EXEC_HI 0x27f
+#define ixSQ_WAVE_STATUS 0x12
+#define ixSQ_WAVE_MODE 0x11
+#define ixSQ_WAVE_TRAPSTS 0x13
+#define ixSQ_WAVE_HW_ID 0x14
+#define ixSQ_WAVE_GPR_ALLOC 0x15
+#define ixSQ_WAVE_LDS_ALLOC 0x16
+#define ixSQ_WAVE_IB_STS 0x17
+#define ixSQ_WAVE_M0 0x27c
+#define ixSQ_WAVE_TBA_LO 0x26c
+#define ixSQ_WAVE_TBA_HI 0x26d
+#define ixSQ_WAVE_TMA_LO 0x26e
+#define ixSQ_WAVE_TMA_HI 0x26f
+#define ixSQ_WAVE_TTMP0 0x270
+#define ixSQ_WAVE_TTMP1 0x271
+#define ixSQ_WAVE_TTMP2 0x272
+#define ixSQ_WAVE_TTMP3 0x273
+#define ixSQ_WAVE_TTMP4 0x274
+#define ixSQ_WAVE_TTMP5 0x275
+#define ixSQ_WAVE_TTMP6 0x276
+#define ixSQ_WAVE_TTMP7 0x277
+#define ixSQ_WAVE_TTMP8 0x278
+#define ixSQ_WAVE_TTMP9 0x279
+#define ixSQ_WAVE_TTMP10 0x27a
+#define ixSQ_WAVE_TTMP11 0x27b
+#define mmSQ_DEBUG_STS_GLOBAL 0x2309
+#define mmSQ_DEBUG_STS_GLOBAL2 0x2310
+#define mmSQ_DEBUG_STS_GLOBAL3 0x2311
+#define ixSQ_DEBUG_STS_LOCAL 0x8
+#define ixSQ_DEBUG_CTRL_LOCAL 0x9
+#define mmSH_MEM_BASES 0x230a
+#define mmSH_MEM_APE1_BASE 0x230b
+#define mmSH_MEM_APE1_LIMIT 0x230c
+#define mmSH_MEM_CONFIG 0x230d
+#define mmSQC_POLICY 0x230e
+#define mmSQC_VOLATILE 0x230f
+#define mmSQ_THREAD_TRACE_WORD_CMN 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_INST 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x23b1
+#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x23b1
+#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x23b1
+#define mmSQ_THREAD_TRACE_WORD_WAVE 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_MISC 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_EVENT 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x23b1
+#define ixSQ_INTERRUPT_WORD_CMN 0x20c0
+#define ixSQ_INTERRUPT_WORD_AUTO 0x20c0
+#define ixSQ_INTERRUPT_WORD_WAVE 0x20c0
+#define mmSQ_SOP2 0x237f
+#define mmSQ_VOP1 0x237f
+#define mmSQ_MTBUF_1 0x237f
+#define mmSQ_EXP_1 0x237f
+#define mmSQ_MUBUF_1 0x237f
+#define mmSQ_INST 0x237f
+#define mmSQ_EXP_0 0x237f
+#define mmSQ_MUBUF_0 0x237f
+#define mmSQ_VOP3_0 0x237f
+#define mmSQ_VOP2 0x237f
+#define mmSQ_MTBUF_0 0x237f
+#define mmSQ_SOPP 0x237f
+#define mmSQ_FLAT_0 0x237f
+#define mmSQ_VOP3_0_SDST_ENC 0x237f
+#define mmSQ_MIMG_1 0x237f
+#define mmSQ_SMRD 0x237f
+#define mmSQ_SOP1 0x237f
+#define mmSQ_SOPC 0x237f
+#define mmSQ_FLAT_1 0x237f
+#define mmSQ_DS_1 0x237f
+#define mmSQ_VOP3_1 0x237f
+#define mmSQ_MIMG_0 0x237f
+#define mmSQ_SOPK 0x237f
+#define mmSQ_DS_0 0x237f
+#define mmSQ_VOPC 0x237f
+#define mmSQ_VINTRP 0x237f
+#define mmCGTT_SX_CLK_CTRL0 0xf094
+#define mmCGTT_SX_CLK_CTRL1 0xf095
+#define mmCGTT_SX_CLK_CTRL2 0xf096
+#define mmCGTT_SX_CLK_CTRL3 0xf097
+#define mmCGTT_SX_CLK_CTRL4 0xf098
+#define mmSX_DEBUG_BUSY 0x2414
+#define mmSX_DEBUG_BUSY_2 0x2415
+#define mmSX_DEBUG_BUSY_3 0x2416
+#define mmSX_DEBUG_BUSY_4 0x2417
+#define mmSX_DEBUG_1 0x2418
+#define mmSX_PERFCOUNTER0_SELECT 0xda40
+#define mmSX_PERFCOUNTER1_SELECT 0xda41
+#define mmSX_PERFCOUNTER2_SELECT 0xda42
+#define mmSX_PERFCOUNTER3_SELECT 0xda43
+#define mmSX_PERFCOUNTER0_SELECT1 0xda44
+#define mmSX_PERFCOUNTER1_SELECT1 0xda45
+#define mmSX_PERFCOUNTER0_LO 0xd240
+#define mmSX_PERFCOUNTER0_HI 0xd241
+#define mmSX_PERFCOUNTER1_LO 0xd242
+#define mmSX_PERFCOUNTER1_HI 0xd243
+#define mmSX_PERFCOUNTER2_LO 0xd244
+#define mmSX_PERFCOUNTER2_HI 0xd245
+#define mmSX_PERFCOUNTER3_LO 0xd246
+#define mmSX_PERFCOUNTER3_HI 0xd247
+#define mmTCC_CTRL 0x2b80
+#define mmTCC_EDC_COUNTER 0x2b82
+#define mmTCC_REDUNDANCY 0x2b83
+#define mmTCC_CGTT_SCLK_CTRL 0xf0ac
+#define mmTCA_CGTT_SCLK_CTRL 0xf0ad
+#define mmTCS_CGTT_SCLK_CTRL 0xf0ae
+#define mmTCC_PERFCOUNTER0_SELECT 0xdb80
+#define mmTCC_PERFCOUNTER1_SELECT 0xdb82
+#define mmTCC_PERFCOUNTER0_SELECT1 0xdb81
+#define mmTCC_PERFCOUNTER1_SELECT1 0xdb83
+#define mmTCC_PERFCOUNTER2_SELECT 0xdb84
+#define mmTCC_PERFCOUNTER3_SELECT 0xdb85
+#define mmTCC_PERFCOUNTER0_LO 0xd380
+#define mmTCC_PERFCOUNTER1_LO 0xd382
+#define mmTCC_PERFCOUNTER2_LO 0xd384
+#define mmTCC_PERFCOUNTER3_LO 0xd386
+#define mmTCC_PERFCOUNTER0_HI 0xd381
+#define mmTCC_PERFCOUNTER1_HI 0xd383
+#define mmTCC_PERFCOUNTER2_HI 0xd385
+#define mmTCC_PERFCOUNTER3_HI 0xd387
+#define mmTCA_CTRL 0x2bc0
+#define mmTCA_PERFCOUNTER0_SELECT 0xdb90
+#define mmTCA_PERFCOUNTER1_SELECT 0xdb92
+#define mmTCA_PERFCOUNTER0_SELECT1 0xdb91
+#define mmTCA_PERFCOUNTER1_SELECT1 0xdb93
+#define mmTCA_PERFCOUNTER2_SELECT 0xdb94
+#define mmTCA_PERFCOUNTER3_SELECT 0xdb95
+#define mmTCA_PERFCOUNTER0_LO 0xd390
+#define mmTCA_PERFCOUNTER1_LO 0xd392
+#define mmTCA_PERFCOUNTER2_LO 0xd394
+#define mmTCA_PERFCOUNTER3_LO 0xd396
+#define mmTCA_PERFCOUNTER0_HI 0xd391
+#define mmTCA_PERFCOUNTER1_HI 0xd393
+#define mmTCA_PERFCOUNTER2_HI 0xd395
+#define mmTCA_PERFCOUNTER3_HI 0xd397
+#define mmTCS_CTRL 0x2be0
+#define mmTCS_PERFCOUNTER0_SELECT 0xdba0
+#define mmTCS_PERFCOUNTER0_SELECT1 0xdba1
+#define mmTCS_PERFCOUNTER1_SELECT 0xdba2
+#define mmTCS_PERFCOUNTER2_SELECT 0xdba3
+#define mmTCS_PERFCOUNTER3_SELECT 0xdba4
+#define mmTCS_PERFCOUNTER0_LO 0xd3a0
+#define mmTCS_PERFCOUNTER1_LO 0xd3a2
+#define mmTCS_PERFCOUNTER2_LO 0xd3a4
+#define mmTCS_PERFCOUNTER3_LO 0xd3a6
+#define mmTCS_PERFCOUNTER0_HI 0xd3a1
+#define mmTCS_PERFCOUNTER1_HI 0xd3a3
+#define mmTCS_PERFCOUNTER2_HI 0xd3a5
+#define mmTCS_PERFCOUNTER3_HI 0xd3a7
+#define mmTA_BC_BASE_ADDR 0xa020
+#define mmTA_BC_BASE_ADDR_HI 0xa021
+#define mmTD_CNTL 0x2525
+#define mmTD_STATUS 0x2526
+#define mmTD_DEBUG_INDEX 0x2528
+#define mmTD_DEBUG_DATA 0x2529
+#define mmTD_PERFCOUNTER0_SELECT 0xdb00
+#define mmTD_PERFCOUNTER1_SELECT 0xdb02
+#define mmTD_PERFCOUNTER0_SELECT1 0xdb01
+#define mmTD_PERFCOUNTER0_LO 0xd300
+#define mmTD_PERFCOUNTER1_LO 0xd302
+#define mmTD_PERFCOUNTER0_HI 0xd301
+#define mmTD_PERFCOUNTER1_HI 0xd303
+#define mmTD_SCRATCH 0x2533
+#define mmTA_CNTL 0x2541
+#define mmTA_CNTL_AUX 0x2542
+#define mmTA_RESERVED_010C 0x2543
+#define mmTA_CS_BC_BASE_ADDR 0xc380
+#define mmTA_CS_BC_BASE_ADDR_HI 0xc381
+#define mmTA_STATUS 0x2548
+#define mmTA_DEBUG_INDEX 0x254c
+#define mmTA_DEBUG_DATA 0x254d
+#define mmTA_PERFCOUNTER0_SELECT 0xdac0
+#define mmTA_PERFCOUNTER1_SELECT 0xdac2
+#define mmTA_PERFCOUNTER0_SELECT1 0xdac1
+#define mmTA_PERFCOUNTER0_LO 0xd2c0
+#define mmTA_PERFCOUNTER1_LO 0xd2c2
+#define mmTA_PERFCOUNTER0_HI 0xd2c1
+#define mmTA_PERFCOUNTER1_HI 0xd2c3
+#define mmTA_SCRATCH 0x2564
+#define mmSH_HIDDEN_PRIVATE_BASE_VMID 0x2580
+#define mmSH_STATIC_MEM_CONFIG 0x2581
+#define mmTCP_INVALIDATE 0x2b00
+#define mmTCP_STATUS 0x2b01
+#define mmTCP_CNTL 0x2b02
+#define mmTCP_CHAN_STEER_LO 0x2b03
+#define mmTCP_CHAN_STEER_HI 0x2b04
+#define mmTCP_ADDR_CONFIG 0x2b05
+#define mmTCP_CREDIT 0x2b06
+#define mmTCP_PERFCOUNTER0_SELECT 0xdb40
+#define mmTCP_PERFCOUNTER1_SELECT 0xdb42
+#define mmTCP_PERFCOUNTER0_SELECT1 0xdb41
+#define mmTCP_PERFCOUNTER1_SELECT1 0xdb43
+#define mmTCP_PERFCOUNTER2_SELECT 0xdb44
+#define mmTCP_PERFCOUNTER3_SELECT 0xdb45
+#define mmTCP_PERFCOUNTER0_LO 0xd340
+#define mmTCP_PERFCOUNTER1_LO 0xd342
+#define mmTCP_PERFCOUNTER2_LO 0xd344
+#define mmTCP_PERFCOUNTER3_LO 0xd346
+#define mmTCP_PERFCOUNTER0_HI 0xd341
+#define mmTCP_PERFCOUNTER1_HI 0xd343
+#define mmTCP_PERFCOUNTER2_HI 0xd345
+#define mmTCP_PERFCOUNTER3_HI 0xd347
+#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x2b16
+#define mmTCP_EDC_COUNTER 0x2b17
+#define mmTC_CFG_L1_LOAD_POLICY0 0x2b1a
+#define mmTC_CFG_L1_LOAD_POLICY1 0x2b1b
+#define mmTC_CFG_L1_STORE_POLICY 0x2b1c
+#define mmTC_CFG_L2_LOAD_POLICY0 0x2b1d
+#define mmTC_CFG_L2_LOAD_POLICY1 0x2b1e
+#define mmTC_CFG_L2_STORE_POLICY0 0x2b1f
+#define mmTC_CFG_L2_STORE_POLICY1 0x2b20
+#define mmTC_CFG_L2_ATOMIC_POLICY 0x2b21
+#define mmTC_CFG_L1_VOLATILE 0x2b22
+#define mmTC_CFG_L2_VOLATILE 0x2b23
+#define mmTCP_WATCH0_ADDR_H 0x32a0
+#define mmTCP_WATCH1_ADDR_H 0x32a3
+#define mmTCP_WATCH2_ADDR_H 0x32a6
+#define mmTCP_WATCH3_ADDR_H 0x32a9
+#define mmTCP_WATCH0_ADDR_L 0x32a1
+#define mmTCP_WATCH1_ADDR_L 0x32a4
+#define mmTCP_WATCH2_ADDR_L 0x32a7
+#define mmTCP_WATCH3_ADDR_L 0x32aa
+#define mmTCP_WATCH0_CNTL 0x32a2
+#define mmTCP_WATCH1_CNTL 0x32a5
+#define mmTCP_WATCH2_CNTL 0x32a8
+#define mmTCP_WATCH3_CNTL 0x32ab
+#define mmTD_CGTT_CTRL 0xf09c
+#define mmTA_CGTT_CTRL 0xf09d
+#define mmCGTT_TCP_CLK_CTRL 0xf09e
+#define mmCGTT_TCI_CLK_CTRL 0xf09f
+#define mmTCI_STATUS 0x2b61
+#define mmTCI_CNTL_1 0x2b62
+#define mmTCI_CNTL_2 0x2b63
+#define mmGDS_CONFIG 0x25c0
+#define mmGDS_CNTL_STATUS 0x25c1
+#define mmGDS_ENHANCE 0x25c2
+#define mmGDS_PROTECTION_FAULT 0x25c3
+#define mmGDS_VM_PROTECTION_FAULT 0x25c4
+#define mmGDS_SECDED_CNT 0x25c5
+#define mmGDS_GRBM_SECDED_CNT 0x25c6
+#define mmGDS_OA_DED 0x25c7
+#define mmGDS_DEBUG_CNTL 0x25c8
+#define mmGDS_DEBUG_DATA 0x25c9
+#define mmCGTT_GDS_CLK_CTRL 0xf0a0
+#define mmGDS_RD_ADDR 0xc400
+#define mmGDS_RD_DATA 0xc401
+#define mmGDS_RD_BURST_ADDR 0xc402
+#define mmGDS_RD_BURST_COUNT 0xc403
+#define mmGDS_RD_BURST_DATA 0xc404
+#define mmGDS_WR_ADDR 0xc405
+#define mmGDS_WR_DATA 0xc406
+#define mmGDS_WR_BURST_ADDR 0xc407
+#define mmGDS_WR_BURST_DATA 0xc408
+#define mmGDS_WRITE_COMPLETE 0xc409
+#define mmGDS_ATOM_CNTL 0xc40a
+#define mmGDS_ATOM_COMPLETE 0xc40b
+#define mmGDS_ATOM_BASE 0xc40c
+#define mmGDS_ATOM_SIZE 0xc40d
+#define mmGDS_ATOM_OFFSET0 0xc40e
+#define mmGDS_ATOM_OFFSET1 0xc40f
+#define mmGDS_ATOM_DST 0xc410
+#define mmGDS_ATOM_OP 0xc411
+#define mmGDS_ATOM_SRC0 0xc412
+#define mmGDS_ATOM_SRC0_U 0xc413
+#define mmGDS_ATOM_SRC1 0xc414
+#define mmGDS_ATOM_SRC1_U 0xc415
+#define mmGDS_ATOM_READ0 0xc416
+#define mmGDS_ATOM_READ0_U 0xc417
+#define mmGDS_ATOM_READ1 0xc418
+#define mmGDS_ATOM_READ1_U 0xc419
+#define mmGDS_GWS_RESOURCE_CNTL 0xc41a
+#define mmGDS_GWS_RESOURCE 0xc41b
+#define mmGDS_GWS_RESOURCE_CNT 0xc41c
+#define mmGDS_OA_CNTL 0xc41d
+#define mmGDS_OA_COUNTER 0xc41e
+#define mmGDS_OA_ADDRESS 0xc41f
+#define mmGDS_OA_INCDEC 0xc420
+#define ixGDS_DEBUG_REG0 0x0
+#define ixGDS_DEBUG_REG1 0x1
+#define ixGDS_DEBUG_REG2 0x2
+#define ixGDS_DEBUG_REG3 0x3
+#define ixGDS_DEBUG_REG4 0x4
+#define ixGDS_DEBUG_REG5 0x5
+#define ixGDS_DEBUG_REG6 0x6
+#define mmGDS_PERFCOUNTER0_SELECT 0xda80
+#define mmGDS_PERFCOUNTER1_SELECT 0xda81
+#define mmGDS_PERFCOUNTER2_SELECT 0xda82
+#define mmGDS_PERFCOUNTER3_SELECT 0xda83
+#define mmGDS_PERFCOUNTER0_LO 0xd280
+#define mmGDS_PERFCOUNTER1_LO 0xd282
+#define mmGDS_PERFCOUNTER2_LO 0xd284
+#define mmGDS_PERFCOUNTER3_LO 0xd286
+#define mmGDS_PERFCOUNTER0_HI 0xd281
+#define mmGDS_PERFCOUNTER1_HI 0xd283
+#define mmGDS_PERFCOUNTER2_HI 0xd285
+#define mmGDS_PERFCOUNTER3_HI 0xd287
+#define mmGDS_PERFCOUNTER0_SELECT1 0xda84
+#define mmGDS_VMID0_BASE 0x3300
+#define mmGDS_VMID1_BASE 0x3302
+#define mmGDS_VMID2_BASE 0x3304
+#define mmGDS_VMID3_BASE 0x3306
+#define mmGDS_VMID4_BASE 0x3308
+#define mmGDS_VMID5_BASE 0x330a
+#define mmGDS_VMID6_BASE 0x330c
+#define mmGDS_VMID7_BASE 0x330e
+#define mmGDS_VMID8_BASE 0x3310
+#define mmGDS_VMID9_BASE 0x3312
+#define mmGDS_VMID10_BASE 0x3314
+#define mmGDS_VMID11_BASE 0x3316
+#define mmGDS_VMID12_BASE 0x3318
+#define mmGDS_VMID13_BASE 0x331a
+#define mmGDS_VMID14_BASE 0x331c
+#define mmGDS_VMID15_BASE 0x331e
+#define mmGDS_VMID0_SIZE 0x3301
+#define mmGDS_VMID1_SIZE 0x3303
+#define mmGDS_VMID2_SIZE 0x3305
+#define mmGDS_VMID3_SIZE 0x3307
+#define mmGDS_VMID4_SIZE 0x3309
+#define mmGDS_VMID5_SIZE 0x330b
+#define mmGDS_VMID6_SIZE 0x330d
+#define mmGDS_VMID7_SIZE 0x330f
+#define mmGDS_VMID8_SIZE 0x3311
+#define mmGDS_VMID9_SIZE 0x3313
+#define mmGDS_VMID10_SIZE 0x3315
+#define mmGDS_VMID11_SIZE 0x3317
+#define mmGDS_VMID12_SIZE 0x3319
+#define mmGDS_VMID13_SIZE 0x331b
+#define mmGDS_VMID14_SIZE 0x331d
+#define mmGDS_VMID15_SIZE 0x331f
+#define mmGDS_GWS_VMID0 0x3320
+#define mmGDS_GWS_VMID1 0x3321
+#define mmGDS_GWS_VMID2 0x3322
+#define mmGDS_GWS_VMID3 0x3323
+#define mmGDS_GWS_VMID4 0x3324
+#define mmGDS_GWS_VMID5 0x3325
+#define mmGDS_GWS_VMID6 0x3326
+#define mmGDS_GWS_VMID7 0x3327
+#define mmGDS_GWS_VMID8 0x3328
+#define mmGDS_GWS_VMID9 0x3329
+#define mmGDS_GWS_VMID10 0x332a
+#define mmGDS_GWS_VMID11 0x332b
+#define mmGDS_GWS_VMID12 0x332c
+#define mmGDS_GWS_VMID13 0x332d
+#define mmGDS_GWS_VMID14 0x332e
+#define mmGDS_GWS_VMID15 0x332f
+#define mmGDS_OA_VMID0 0x3330
+#define mmGDS_OA_VMID1 0x3331
+#define mmGDS_OA_VMID2 0x3332
+#define mmGDS_OA_VMID3 0x3333
+#define mmGDS_OA_VMID4 0x3334
+#define mmGDS_OA_VMID5 0x3335
+#define mmGDS_OA_VMID6 0x3336
+#define mmGDS_OA_VMID7 0x3337
+#define mmGDS_OA_VMID8 0x3338
+#define mmGDS_OA_VMID9 0x3339
+#define mmGDS_OA_VMID10 0x333a
+#define mmGDS_OA_VMID11 0x333b
+#define mmGDS_OA_VMID12 0x333c
+#define mmGDS_OA_VMID13 0x333d
+#define mmGDS_OA_VMID14 0x333e
+#define mmGDS_OA_VMID15 0x333f
+#define mmGDS_GWS_RESET0 0x3344
+#define mmGDS_GWS_RESET1 0x3345
+#define mmGDS_GWS_RESOURCE_RESET 0x3346
+#define mmGDS_COMPUTE_MAX_WAVE_ID 0x3348
+#define mmGDS_OA_RESET_MASK 0x3349
+#define mmGDS_OA_RESET 0x334a
+#define mmCS_COPY_STATE 0xa1f3
+#define mmGFX_COPY_STATE 0xa1f4
+#define mmVGT_DRAW_INITIATOR 0xa1fc
+#define mmVGT_EVENT_INITIATOR 0xa2a4
+#define mmVGT_EVENT_ADDRESS_REG 0xa1fe
+#define mmVGT_DMA_BASE_HI 0xa1f9
+#define mmVGT_DMA_BASE 0xa1fa
+#define mmVGT_DMA_INDEX_TYPE 0xa29f
+#define mmVGT_DMA_NUM_INSTANCES 0xa2a2
+#define mmIA_ENHANCE 0xa29c
+#define mmVGT_DMA_SIZE 0xa29d
+#define mmVGT_DMA_MAX_SIZE 0xa29e
+#define mmVGT_DMA_PRIMITIVE_TYPE 0x2271
+#define mmVGT_DMA_CONTROL 0x2272
+#define mmVGT_IMMED_DATA 0xa1fd
+#define mmVGT_INDEX_TYPE 0xc243
+#define mmVGT_NUM_INDICES 0xc24c
+#define mmVGT_NUM_INSTANCES 0xc24d
+#define mmVGT_PRIMITIVE_TYPE 0xc242
+#define mmVGT_PRIMITIVEID_EN 0xa2a1
+#define mmVGT_PRIMITIVEID_RESET 0xa2a3
+#define mmVGT_VTX_CNT_EN 0xa2ae
+#define mmVGT_REUSE_OFF 0xa2ad
+#define mmVGT_INSTANCE_STEP_RATE_0 0xa2a8
+#define mmVGT_INSTANCE_STEP_RATE_1 0xa2a9
+#define mmVGT_MAX_VTX_INDX 0xa100
+#define mmVGT_MIN_VTX_INDX 0xa101
+#define mmVGT_INDX_OFFSET 0xa102
+#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0xa316
+#define mmVGT_OUT_DEALLOC_CNTL 0xa317
+#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0xa103
+#define mmVGT_MULTI_PRIM_IB_RESET_EN 0xa2a5
+#define mmVGT_ENHANCE 0xa294
+#define mmVGT_OUTPUT_PATH_CNTL 0xa284
+#define mmVGT_HOS_CNTL 0xa285
+#define mmVGT_HOS_MAX_TESS_LEVEL 0xa286
+#define mmVGT_HOS_MIN_TESS_LEVEL 0xa287
+#define mmVGT_HOS_REUSE_DEPTH 0xa288
+#define mmVGT_GROUP_PRIM_TYPE 0xa289
+#define mmVGT_GROUP_FIRST_DECR 0xa28a
+#define mmVGT_GROUP_DECR 0xa28b
+#define mmVGT_GROUP_VECT_0_CNTL 0xa28c
+#define mmVGT_GROUP_VECT_1_CNTL 0xa28d
+#define mmVGT_GROUP_VECT_0_FMT_CNTL 0xa28e
+#define mmVGT_GROUP_VECT_1_FMT_CNTL 0xa28f
+#define mmVGT_VTX_VECT_EJECT_REG 0x222c
+#define mmVGT_DMA_DATA_FIFO_DEPTH 0x222d
+#define mmVGT_DMA_REQ_FIFO_DEPTH 0x222e
+#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x222f
+#define mmVGT_LAST_COPY_STATE 0x2230
+#define mmCC_GC_SHADER_ARRAY_CONFIG 0x226f
+#define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270
+#define mmVGT_GS_MODE 0xa290
+#define mmVGT_GS_ONCHIP_CNTL 0xa291
+#define mmVGT_GS_OUT_PRIM_TYPE 0xa29b
+#define mmVGT_CACHE_INVALIDATION 0x2231
+#define mmVGT_RESET_DEBUG 0x2232
+#define mmVGT_STRMOUT_DELAY 0x2233
+#define mmVGT_FIFO_DEPTHS 0x2234
+#define mmVGT_GS_PER_ES 0xa295
+#define mmVGT_ES_PER_GS 0xa296
+#define mmVGT_GS_PER_VS 0xa297
+#define mmVGT_GS_VERTEX_REUSE 0x2235
+#define mmVGT_MC_LAT_CNTL 0x2236
+#define mmIA_CNTL_STATUS 0x2237
+#define mmVGT_STRMOUT_CONFIG 0xa2e5
+#define mmVGT_STRMOUT_BUFFER_SIZE_0 0xa2b4
+#define mmVGT_STRMOUT_BUFFER_SIZE_1 0xa2b8
+#define mmVGT_STRMOUT_BUFFER_SIZE_2 0xa2bc
+#define mmVGT_STRMOUT_BUFFER_SIZE_3 0xa2c0
+#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0xa2b7
+#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0xa2bb
+#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0xa2bf
+#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0xa2c3
+#define mmVGT_STRMOUT_VTX_STRIDE_0 0xa2b5
+#define mmVGT_STRMOUT_VTX_STRIDE_1 0xa2b9
+#define mmVGT_STRMOUT_VTX_STRIDE_2 0xa2bd
+#define mmVGT_STRMOUT_VTX_STRIDE_3 0xa2c1
+#define mmVGT_STRMOUT_BUFFER_CONFIG 0xa2e6
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0xc244
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0xc245
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0xc246
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0xc247
+#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0xa2ca
+#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0xa2cb
+#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0xa2cc
+#define mmVGT_GS_MAX_VERT_OUT 0xa2ce
+#define mmIA_VMID_OVERRIDE 0x2260
+#define mmVGT_SHADER_STAGES_EN 0xa2d5
+#define mmVGT_LS_HS_CONFIG 0xa2d6
+#define mmVGT_DMA_LS_HS_CONFIG 0x2273
+#define mmVGT_TF_PARAM 0xa2db
+#define mmVGT_TF_RING_SIZE 0xc24e
+#define mmVGT_SYS_CONFIG 0x2263
+#define mmVGT_HS_OFFCHIP_PARAM 0xc24f
+#define mmVGT_TF_MEMORY_BASE 0xc250
+#define mmVGT_GS_INSTANCE_CNT 0xa2e4
+#define mmIA_MULTI_VGT_PARAM 0xa2aa
+#define mmVGT_VS_MAX_WAVE_ID 0x2268
+#define mmVGT_ESGS_RING_SIZE 0xc240
+#define mmVGT_GSVS_RING_SIZE 0xc241
+#define mmVGT_GSVS_RING_OFFSET_1 0xa298
+#define mmVGT_GSVS_RING_OFFSET_2 0xa299
+#define mmVGT_GSVS_RING_OFFSET_3 0xa29a
+#define mmVGT_ESGS_RING_ITEMSIZE 0xa2ab
+#define mmVGT_GSVS_RING_ITEMSIZE 0xa2ac
+#define mmVGT_GS_VERT_ITEMSIZE 0xa2d7
+#define mmVGT_GS_VERT_ITEMSIZE_1 0xa2d8
+#define mmVGT_GS_VERT_ITEMSIZE_2 0xa2d9
+#define mmVGT_GS_VERT_ITEMSIZE_3 0xa2da
+#define mmWD_CNTL_STATUS 0x223f
+#define mmWD_ENHANCE 0xa2a0
+#define mmGFX_PIPE_CONTROL 0x226d
+#define mmGFX_PIPE_PRIORITY 0xf87f
+#define mmCGTT_VGT_CLK_CTRL 0xf084
+#define mmCGTT_IA_CLK_CTRL 0xf085
+#define mmCGTT_WD_CLK_CTRL 0xf086
+#define mmVGT_DEBUG_CNTL 0x2238
+#define mmVGT_DEBUG_DATA 0x2239
+#define mmIA_DEBUG_CNTL 0x223a
+#define mmIA_DEBUG_DATA 0x223b
+#define mmVGT_CNTL_STATUS 0x223c
+#define mmWD_DEBUG_CNTL 0x223d
+#define mmWD_DEBUG_DATA 0x223e
+#define mmCC_GC_PRIM_CONFIG 0x2240
+#define mmGC_USER_PRIM_CONFIG 0x2241
+#define ixWD_DEBUG_REG0 0x0
+#define ixWD_DEBUG_REG1 0x1
+#define ixWD_DEBUG_REG2 0x2
+#define ixWD_DEBUG_REG3 0x3
+#define ixWD_DEBUG_REG4 0x4
+#define ixWD_DEBUG_REG5 0x5
+#define ixIA_DEBUG_REG0 0x0
+#define ixIA_DEBUG_REG1 0x1
+#define ixIA_DEBUG_REG2 0x2
+#define ixIA_DEBUG_REG3 0x3
+#define ixIA_DEBUG_REG4 0x4
+#define ixIA_DEBUG_REG5 0x5
+#define ixIA_DEBUG_REG6 0x6
+#define ixIA_DEBUG_REG7 0x7
+#define ixIA_DEBUG_REG8 0x8
+#define ixIA_DEBUG_REG9 0x9
+#define ixVGT_DEBUG_REG0 0x0
+#define ixVGT_DEBUG_REG1 0x1
+#define ixVGT_DEBUG_REG2 0x1e
+#define ixVGT_DEBUG_REG3 0x1f
+#define ixVGT_DEBUG_REG4 0x20
+#define ixVGT_DEBUG_REG5 0x21
+#define ixVGT_DEBUG_REG6 0x22
+#define ixVGT_DEBUG_REG7 0x23
+#define ixVGT_DEBUG_REG8 0x8
+#define ixVGT_DEBUG_REG9 0x9
+#define ixVGT_DEBUG_REG10 0xa
+#define ixVGT_DEBUG_REG11 0xb
+#define ixVGT_DEBUG_REG12 0xc
+#define ixVGT_DEBUG_REG13 0xd
+#define ixVGT_DEBUG_REG14 0xe
+#define ixVGT_DEBUG_REG15 0xf
+#define ixVGT_DEBUG_REG16 0x10
+#define ixVGT_DEBUG_REG17 0x11
+#define ixVGT_DEBUG_REG18 0x7
+#define ixVGT_DEBUG_REG19 0x13
+#define ixVGT_DEBUG_REG20 0x14
+#define ixVGT_DEBUG_REG21 0x15
+#define ixVGT_DEBUG_REG22 0x16
+#define ixVGT_DEBUG_REG23 0x17
+#define ixVGT_DEBUG_REG24 0x18
+#define ixVGT_DEBUG_REG25 0x19
+#define ixVGT_DEBUG_REG26 0x24
+#define ixVGT_DEBUG_REG27 0x1b
+#define ixVGT_DEBUG_REG28 0x1c
+#define ixVGT_DEBUG_REG29 0x1d
+#define ixVGT_DEBUG_REG30 0x25
+#define ixVGT_DEBUG_REG31 0x26
+#define ixVGT_DEBUG_REG32 0x27
+#define ixVGT_DEBUG_REG33 0x28
+#define ixVGT_DEBUG_REG34 0x29
+#define ixVGT_DEBUG_REG35 0x2a
+#define mmVGT_PERFCOUNTER_SEID_MASK 0xd894
+#define mmVGT_PERFCOUNTER0_SELECT 0xd88c
+#define mmVGT_PERFCOUNTER1_SELECT 0xd88d
+#define mmVGT_PERFCOUNTER2_SELECT 0xd88e
+#define mmVGT_PERFCOUNTER3_SELECT 0xd88f
+#define mmVGT_PERFCOUNTER0_SELECT1 0xd890
+#define mmVGT_PERFCOUNTER1_SELECT1 0xd891
+#define mmVGT_PERFCOUNTER0_LO 0xd090
+#define mmVGT_PERFCOUNTER1_LO 0xd092
+#define mmVGT_PERFCOUNTER2_LO 0xd094
+#define mmVGT_PERFCOUNTER3_LO 0xd096
+#define mmVGT_PERFCOUNTER0_HI 0xd091
+#define mmVGT_PERFCOUNTER1_HI 0xd093
+#define mmVGT_PERFCOUNTER2_HI 0xd095
+#define mmVGT_PERFCOUNTER3_HI 0xd097
+#define mmIA_PERFCOUNTER0_SELECT 0xd884
+#define mmIA_PERFCOUNTER1_SELECT 0xd885
+#define mmIA_PERFCOUNTER2_SELECT 0xd886
+#define mmIA_PERFCOUNTER3_SELECT 0xd887
+#define mmIA_PERFCOUNTER0_SELECT1 0xd888
+#define mmIA_PERFCOUNTER0_LO 0xd088
+#define mmIA_PERFCOUNTER1_LO 0xd08a
+#define mmIA_PERFCOUNTER2_LO 0xd08c
+#define mmIA_PERFCOUNTER3_LO 0xd08e
+#define mmIA_PERFCOUNTER0_HI 0xd089
+#define mmIA_PERFCOUNTER1_HI 0xd08b
+#define mmIA_PERFCOUNTER2_HI 0xd08d
+#define mmIA_PERFCOUNTER3_HI 0xd08f
+#define mmWD_PERFCOUNTER0_SELECT 0xd880
+#define mmWD_PERFCOUNTER1_SELECT 0xd881
+#define mmWD_PERFCOUNTER2_SELECT 0xd882
+#define mmWD_PERFCOUNTER3_SELECT 0xd883
+#define mmWD_PERFCOUNTER0_LO 0xd080
+#define mmWD_PERFCOUNTER1_LO 0xd082
+#define mmWD_PERFCOUNTER2_LO 0xd084
+#define mmWD_PERFCOUNTER3_LO 0xd086
+#define mmWD_PERFCOUNTER0_HI 0xd081
+#define mmWD_PERFCOUNTER1_HI 0xd083
+#define mmWD_PERFCOUNTER2_HI 0xd085
+#define mmWD_PERFCOUNTER3_HI 0xd087
+#define mmDIDT_IND_INDEX 0x3280
+#define mmDIDT_IND_DATA 0x3281
+#define ixDIDT_SQ_CTRL0 0x0
+#define ixDIDT_SQ_CTRL1 0x1
+#define ixDIDT_SQ_CTRL2 0x2
+#define ixDIDT_SQ_WEIGHT0_3 0x10
+#define ixDIDT_SQ_WEIGHT4_7 0x11
+#define ixDIDT_SQ_WEIGHT8_11 0x12
+#define ixDIDT_DB_CTRL0 0x20
+#define ixDIDT_DB_CTRL1 0x21
+#define ixDIDT_DB_CTRL2 0x22
+#define ixDIDT_DB_WEIGHT0_3 0x30
+#define ixDIDT_DB_WEIGHT4_7 0x31
+#define ixDIDT_DB_WEIGHT8_11 0x32
+#define ixDIDT_TD_CTRL0 0x40
+#define ixDIDT_TD_CTRL1 0x41
+#define ixDIDT_TD_CTRL2 0x42
+#define ixDIDT_TD_WEIGHT0_3 0x50
+#define ixDIDT_TD_WEIGHT4_7 0x51
+#define ixDIDT_TD_WEIGHT8_11 0x52
+#define ixDIDT_TCP_CTRL0 0x60
+#define ixDIDT_TCP_CTRL1 0x61
+#define ixDIDT_TCP_CTRL2 0x62
+#define ixDIDT_TCP_WEIGHT0_3 0x70
+#define ixDIDT_TCP_WEIGHT4_7 0x71
+#define ixDIDT_TCP_WEIGHT8_11 0x72
+
+#endif /* GFX_7_0_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h
new file mode 100644
index 000000000000..290ce6aa4b71
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h
@@ -0,0 +1,2557 @@
+/*
+ * GFX_7_2 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GFX_7_2_D_H
+#define GFX_7_2_D_H
+
+#define mmCB_BLEND_RED 0xa105
+#define mmCB_BLEND_GREEN 0xa106
+#define mmCB_BLEND_BLUE 0xa107
+#define mmCB_BLEND_ALPHA 0xa108
+#define mmCB_COLOR_CONTROL 0xa202
+#define mmCB_BLEND0_CONTROL 0xa1e0
+#define mmCB_BLEND1_CONTROL 0xa1e1
+#define mmCB_BLEND2_CONTROL 0xa1e2
+#define mmCB_BLEND3_CONTROL 0xa1e3
+#define mmCB_BLEND4_CONTROL 0xa1e4
+#define mmCB_BLEND5_CONTROL 0xa1e5
+#define mmCB_BLEND6_CONTROL 0xa1e6
+#define mmCB_BLEND7_CONTROL 0xa1e7
+#define mmCB_COLOR0_BASE 0xa318
+#define mmCB_COLOR1_BASE 0xa327
+#define mmCB_COLOR2_BASE 0xa336
+#define mmCB_COLOR3_BASE 0xa345
+#define mmCB_COLOR4_BASE 0xa354
+#define mmCB_COLOR5_BASE 0xa363
+#define mmCB_COLOR6_BASE 0xa372
+#define mmCB_COLOR7_BASE 0xa381
+#define mmCB_COLOR0_PITCH 0xa319
+#define mmCB_COLOR1_PITCH 0xa328
+#define mmCB_COLOR2_PITCH 0xa337
+#define mmCB_COLOR3_PITCH 0xa346
+#define mmCB_COLOR4_PITCH 0xa355
+#define mmCB_COLOR5_PITCH 0xa364
+#define mmCB_COLOR6_PITCH 0xa373
+#define mmCB_COLOR7_PITCH 0xa382
+#define mmCB_COLOR0_SLICE 0xa31a
+#define mmCB_COLOR1_SLICE 0xa329
+#define mmCB_COLOR2_SLICE 0xa338
+#define mmCB_COLOR3_SLICE 0xa347
+#define mmCB_COLOR4_SLICE 0xa356
+#define mmCB_COLOR5_SLICE 0xa365
+#define mmCB_COLOR6_SLICE 0xa374
+#define mmCB_COLOR7_SLICE 0xa383
+#define mmCB_COLOR0_VIEW 0xa31b
+#define mmCB_COLOR1_VIEW 0xa32a
+#define mmCB_COLOR2_VIEW 0xa339
+#define mmCB_COLOR3_VIEW 0xa348
+#define mmCB_COLOR4_VIEW 0xa357
+#define mmCB_COLOR5_VIEW 0xa366
+#define mmCB_COLOR6_VIEW 0xa375
+#define mmCB_COLOR7_VIEW 0xa384
+#define mmCB_COLOR0_INFO 0xa31c
+#define mmCB_COLOR1_INFO 0xa32b
+#define mmCB_COLOR2_INFO 0xa33a
+#define mmCB_COLOR3_INFO 0xa349
+#define mmCB_COLOR4_INFO 0xa358
+#define mmCB_COLOR5_INFO 0xa367
+#define mmCB_COLOR6_INFO 0xa376
+#define mmCB_COLOR7_INFO 0xa385
+#define mmCB_COLOR0_ATTRIB 0xa31d
+#define mmCB_COLOR1_ATTRIB 0xa32c
+#define mmCB_COLOR2_ATTRIB 0xa33b
+#define mmCB_COLOR3_ATTRIB 0xa34a
+#define mmCB_COLOR4_ATTRIB 0xa359
+#define mmCB_COLOR5_ATTRIB 0xa368
+#define mmCB_COLOR6_ATTRIB 0xa377
+#define mmCB_COLOR7_ATTRIB 0xa386
+#define mmCB_COLOR0_CMASK 0xa31f
+#define mmCB_COLOR1_CMASK 0xa32e
+#define mmCB_COLOR2_CMASK 0xa33d
+#define mmCB_COLOR3_CMASK 0xa34c
+#define mmCB_COLOR4_CMASK 0xa35b
+#define mmCB_COLOR5_CMASK 0xa36a
+#define mmCB_COLOR6_CMASK 0xa379
+#define mmCB_COLOR7_CMASK 0xa388
+#define mmCB_COLOR0_CMASK_SLICE 0xa320
+#define mmCB_COLOR1_CMASK_SLICE 0xa32f
+#define mmCB_COLOR2_CMASK_SLICE 0xa33e
+#define mmCB_COLOR3_CMASK_SLICE 0xa34d
+#define mmCB_COLOR4_CMASK_SLICE 0xa35c
+#define mmCB_COLOR5_CMASK_SLICE 0xa36b
+#define mmCB_COLOR6_CMASK_SLICE 0xa37a
+#define mmCB_COLOR7_CMASK_SLICE 0xa389
+#define mmCB_COLOR0_FMASK 0xa321
+#define mmCB_COLOR1_FMASK 0xa330
+#define mmCB_COLOR2_FMASK 0xa33f
+#define mmCB_COLOR3_FMASK 0xa34e
+#define mmCB_COLOR4_FMASK 0xa35d
+#define mmCB_COLOR5_FMASK 0xa36c
+#define mmCB_COLOR6_FMASK 0xa37b
+#define mmCB_COLOR7_FMASK 0xa38a
+#define mmCB_COLOR0_FMASK_SLICE 0xa322
+#define mmCB_COLOR1_FMASK_SLICE 0xa331
+#define mmCB_COLOR2_FMASK_SLICE 0xa340
+#define mmCB_COLOR3_FMASK_SLICE 0xa34f
+#define mmCB_COLOR4_FMASK_SLICE 0xa35e
+#define mmCB_COLOR5_FMASK_SLICE 0xa36d
+#define mmCB_COLOR6_FMASK_SLICE 0xa37c
+#define mmCB_COLOR7_FMASK_SLICE 0xa38b
+#define mmCB_COLOR0_CLEAR_WORD0 0xa323
+#define mmCB_COLOR1_CLEAR_WORD0 0xa332
+#define mmCB_COLOR2_CLEAR_WORD0 0xa341
+#define mmCB_COLOR3_CLEAR_WORD0 0xa350
+#define mmCB_COLOR4_CLEAR_WORD0 0xa35f
+#define mmCB_COLOR5_CLEAR_WORD0 0xa36e
+#define mmCB_COLOR6_CLEAR_WORD0 0xa37d
+#define mmCB_COLOR7_CLEAR_WORD0 0xa38c
+#define mmCB_COLOR0_CLEAR_WORD1 0xa324
+#define mmCB_COLOR1_CLEAR_WORD1 0xa333
+#define mmCB_COLOR2_CLEAR_WORD1 0xa342
+#define mmCB_COLOR3_CLEAR_WORD1 0xa351
+#define mmCB_COLOR4_CLEAR_WORD1 0xa360
+#define mmCB_COLOR5_CLEAR_WORD1 0xa36f
+#define mmCB_COLOR6_CLEAR_WORD1 0xa37e
+#define mmCB_COLOR7_CLEAR_WORD1 0xa38d
+#define mmCB_TARGET_MASK 0xa08e
+#define mmCB_SHADER_MASK 0xa08f
+#define mmCB_HW_CONTROL 0x2684
+#define mmCB_HW_CONTROL_1 0x2685
+#define mmCB_HW_CONTROL_2 0x2686
+#define mmCB_HW_CONTROL_3 0x2683
+#define mmCB_PERFCOUNTER_FILTER 0xdc00
+#define mmCB_PERFCOUNTER0_SELECT 0xdc01
+#define mmCB_PERFCOUNTER0_SELECT1 0xdc02
+#define mmCB_PERFCOUNTER1_SELECT 0xdc03
+#define mmCB_PERFCOUNTER2_SELECT 0xdc04
+#define mmCB_PERFCOUNTER3_SELECT 0xdc05
+#define mmCB_PERFCOUNTER0_LO 0xd406
+#define mmCB_PERFCOUNTER1_LO 0xd408
+#define mmCB_PERFCOUNTER2_LO 0xd40a
+#define mmCB_PERFCOUNTER3_LO 0xd40c
+#define mmCB_PERFCOUNTER0_HI 0xd407
+#define mmCB_PERFCOUNTER1_HI 0xd409
+#define mmCB_PERFCOUNTER2_HI 0xd40b
+#define mmCB_PERFCOUNTER3_HI 0xd40d
+#define mmCB_CGTT_SCLK_CTRL 0xf0a8
+#define mmCB_DEBUG_BUS_1 0x2699
+#define mmCB_DEBUG_BUS_2 0x269a
+#define mmCB_DEBUG_BUS_3 0x269b
+#define mmCB_DEBUG_BUS_4 0x269c
+#define mmCB_DEBUG_BUS_5 0x269d
+#define mmCB_DEBUG_BUS_6 0x269e
+#define mmCB_DEBUG_BUS_7 0x269f
+#define mmCB_DEBUG_BUS_8 0x26a0
+#define mmCB_DEBUG_BUS_9 0x26a1
+#define mmCB_DEBUG_BUS_10 0x26a2
+#define mmCB_DEBUG_BUS_11 0x26a3
+#define mmCB_DEBUG_BUS_12 0x26a4
+#define mmCB_DEBUG_BUS_13 0x26a5
+#define mmCB_DEBUG_BUS_14 0x26a6
+#define mmCB_DEBUG_BUS_15 0x26a7
+#define mmCB_DEBUG_BUS_16 0x26a8
+#define mmCB_DEBUG_BUS_17 0x26a9
+#define mmCB_DEBUG_BUS_18 0x26aa
+#define mmCP_DFY_CNTL 0x3020
+#define mmCP_DFY_STAT 0x3021
+#define mmCP_DFY_ADDR_HI 0x3022
+#define mmCP_DFY_ADDR_LO 0x3023
+#define mmCP_DFY_DATA_0 0x3024
+#define mmCP_DFY_DATA_1 0x3025
+#define mmCP_DFY_DATA_2 0x3026
+#define mmCP_DFY_DATA_3 0x3027
+#define mmCP_DFY_DATA_4 0x3028
+#define mmCP_DFY_DATA_5 0x3029
+#define mmCP_DFY_DATA_6 0x302a
+#define mmCP_DFY_DATA_7 0x302b
+#define mmCP_DFY_DATA_8 0x302c
+#define mmCP_DFY_DATA_9 0x302d
+#define mmCP_DFY_DATA_10 0x302e
+#define mmCP_DFY_DATA_11 0x302f
+#define mmCP_DFY_DATA_12 0x3030
+#define mmCP_DFY_DATA_13 0x3031
+#define mmCP_DFY_DATA_14 0x3032
+#define mmCP_DFY_DATA_15 0x3033
+#define mmCP_RB0_BASE 0x3040
+#define mmCP_RB0_BASE_HI 0x30b1
+#define mmCP_RB_BASE 0x3040
+#define mmCP_RB1_BASE 0x3060
+#define mmCP_RB1_BASE_HI 0x30b2
+#define mmCP_RB2_BASE 0x3065
+#define mmCP_RB0_CNTL 0x3041
+#define mmCP_RB_CNTL 0x3041
+#define mmCP_RB1_CNTL 0x3061
+#define mmCP_RB2_CNTL 0x3066
+#define mmCP_RB_RPTR_WR 0x3042
+#define mmCP_RB0_RPTR_ADDR 0x3043
+#define mmCP_RB_RPTR_ADDR 0x3043
+#define mmCP_RB1_RPTR_ADDR 0x3062
+#define mmCP_RB2_RPTR_ADDR 0x3067
+#define mmCP_RB0_RPTR_ADDR_HI 0x3044
+#define mmCP_RB_RPTR_ADDR_HI 0x3044
+#define mmCP_RB1_RPTR_ADDR_HI 0x3063
+#define mmCP_RB2_RPTR_ADDR_HI 0x3068
+#define mmCP_RB0_WPTR 0x3045
+#define mmCP_RB_WPTR 0x3045
+#define mmCP_RB1_WPTR 0x3064
+#define mmCP_RB2_WPTR 0x3069
+#define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046
+#define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047
+#define mmGC_PRIV_MODE 0x3048
+#define mmCP_INT_CNTL 0x3049
+#define mmCP_INT_CNTL_RING0 0x306a
+#define mmCP_INT_CNTL_RING1 0x306b
+#define mmCP_INT_CNTL_RING2 0x306c
+#define mmCP_INT_STATUS 0x304a
+#define mmCP_INT_STATUS_RING0 0x306d
+#define mmCP_INT_STATUS_RING1 0x306e
+#define mmCP_INT_STATUS_RING2 0x306f
+#define mmCP_DEVICE_ID 0x304b
+#define mmCP_RING_PRIORITY_CNTS 0x304c
+#define mmCP_ME0_PIPE_PRIORITY_CNTS 0x304c
+#define mmCP_RING0_PRIORITY 0x304d
+#define mmCP_ME0_PIPE0_PRIORITY 0x304d
+#define mmCP_RING1_PRIORITY 0x304e
+#define mmCP_ME0_PIPE1_PRIORITY 0x304e
+#define mmCP_RING2_PRIORITY 0x304f
+#define mmCP_ME0_PIPE2_PRIORITY 0x304f
+#define mmCP_ENDIAN_SWAP 0x3050
+#define mmCP_RB_VMID 0x3051
+#define mmCP_ME0_PIPE0_VMID 0x3052
+#define mmCP_ME0_PIPE1_VMID 0x3053
+#define mmCP_PFP_UCODE_ADDR 0x3054
+#define mmCP_PFP_UCODE_DATA 0x3055
+#define mmCP_ME_RAM_RADDR 0x3056
+#define mmCP_ME_RAM_WADDR 0x3057
+#define mmCP_ME_RAM_DATA 0x3058
+#define mmCGTT_CPC_CLK_CTRL 0xf0b2
+#define mmCGTT_CPF_CLK_CTRL 0xf0b1
+#define mmCGTT_CP_CLK_CTRL 0xf0b0
+#define mmCP_CE_UCODE_ADDR 0x305a
+#define mmCP_CE_UCODE_DATA 0x305b
+#define mmCP_MEC_ME1_UCODE_ADDR 0x305c
+#define mmCP_MEC_ME1_UCODE_DATA 0x305d
+#define mmCP_MEC_ME2_UCODE_ADDR 0x305e
+#define mmCP_MEC_ME2_UCODE_DATA 0x305f
+#define mmCP_PWR_CNTL 0x3078
+#define mmCP_MEM_SLP_CNTL 0x3079
+#define mmCP_ECC_FIRSTOCCURRENCE 0x307a
+#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x307b
+#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x307c
+#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x307d
+#define mmCP_CPF_DEBUG 0x3080
+#define mmCP_FETCHER_SOURCE 0x3082
+#define mmCP_PQ_WPTR_POLL_CNTL 0x3083
+#define mmCP_PQ_WPTR_POLL_CNTL1 0x3084
+#define mmCPC_INT_CNTL 0x30b4
+#define mmCP_ME1_PIPE0_INT_CNTL 0x3085
+#define mmCP_ME1_PIPE1_INT_CNTL 0x3086
+#define mmCP_ME1_PIPE2_INT_CNTL 0x3087
+#define mmCP_ME1_PIPE3_INT_CNTL 0x3088
+#define mmCP_ME2_PIPE0_INT_CNTL 0x3089
+#define mmCP_ME2_PIPE1_INT_CNTL 0x308a
+#define mmCP_ME2_PIPE2_INT_CNTL 0x308b
+#define mmCP_ME2_PIPE3_INT_CNTL 0x308c
+#define mmCPC_INT_STATUS 0x30b5
+#define mmCP_ME1_PIPE0_INT_STATUS 0x308d
+#define mmCP_ME1_PIPE1_INT_STATUS 0x308e
+#define mmCP_ME1_PIPE2_INT_STATUS 0x308f
+#define mmCP_ME1_PIPE3_INT_STATUS 0x3090
+#define mmCP_ME2_PIPE0_INT_STATUS 0x3091
+#define mmCP_ME2_PIPE1_INT_STATUS 0x3092
+#define mmCP_ME2_PIPE2_INT_STATUS 0x3093
+#define mmCP_ME2_PIPE3_INT_STATUS 0x3094
+#define mmCP_ME1_INT_STAT_DEBUG 0x3095
+#define mmCP_ME2_INT_STAT_DEBUG 0x3096
+#define mmCP_ME1_PIPE_PRIORITY_CNTS 0x3099
+#define mmCP_ME1_PIPE0_PRIORITY 0x309a
+#define mmCP_ME1_PIPE1_PRIORITY 0x309b
+#define mmCP_ME1_PIPE2_PRIORITY 0x309c
+#define mmCP_ME1_PIPE3_PRIORITY 0x309d
+#define mmCP_ME2_PIPE_PRIORITY_CNTS 0x309e
+#define mmCP_ME2_PIPE0_PRIORITY 0x309f
+#define mmCP_ME2_PIPE1_PRIORITY 0x30a0
+#define mmCP_ME2_PIPE2_PRIORITY 0x30a1
+#define mmCP_ME2_PIPE3_PRIORITY 0x30a2
+#define mmCP_CE_PRGRM_CNTR_START 0x30a3
+#define mmCP_PFP_PRGRM_CNTR_START 0x30a4
+#define mmCP_ME_PRGRM_CNTR_START 0x30a5
+#define mmCP_MEC1_PRGRM_CNTR_START 0x30a6
+#define mmCP_MEC2_PRGRM_CNTR_START 0x30a7
+#define mmCP_CE_INTR_ROUTINE_START 0x30a8
+#define mmCP_PFP_INTR_ROUTINE_START 0x30a9
+#define mmCP_ME_INTR_ROUTINE_START 0x30aa
+#define mmCP_MEC1_INTR_ROUTINE_START 0x30ab
+#define mmCP_MEC2_INTR_ROUTINE_START 0x30ac
+#define mmCP_CONTEXT_CNTL 0x30ad
+#define mmCP_MAX_CONTEXT 0x30ae
+#define mmCP_IQ_WAIT_TIME1 0x30af
+#define mmCP_IQ_WAIT_TIME2 0x30b0
+#define mmCP_VMID_RESET 0x30b3
+#define mmCP_VMID_PREEMPT 0x30b6
+#define mmCPC_INT_CNTX_ID 0x30b7
+#define mmCP_PQ_STATUS 0x30b8
+#define mmCP_CPC_STATUS 0x2084
+#define mmCP_CPC_BUSY_STAT 0x2085
+#define mmCP_CPC_STALLED_STAT1 0x2086
+#define mmCP_CPF_STATUS 0x2087
+#define mmCP_CPF_BUSY_STAT 0x2088
+#define mmCP_CPF_STALLED_STAT1 0x2089
+#define mmCP_CPC_MC_CNTL 0x208a
+#define mmCP_CPC_GRBM_FREE_COUNT 0x208b
+#define mmCP_MEC_CNTL 0x208d
+#define mmCP_MEC_ME1_HEADER_DUMP 0x208e
+#define mmCP_MEC_ME2_HEADER_DUMP 0x208f
+#define mmCP_CPC_SCRATCH_INDEX 0x2090
+#define mmCP_CPC_SCRATCH_DATA 0x2091
+#define mmCPG_PERFCOUNTER1_SELECT 0xd800
+#define mmCPG_PERFCOUNTER1_LO 0xd000
+#define mmCPG_PERFCOUNTER1_HI 0xd001
+#define mmCPG_PERFCOUNTER0_SELECT1 0xd801
+#define mmCPG_PERFCOUNTER0_SELECT 0xd802
+#define mmCPG_PERFCOUNTER0_LO 0xd002
+#define mmCPG_PERFCOUNTER0_HI 0xd003
+#define mmCPC_PERFCOUNTER1_SELECT 0xd803
+#define mmCPC_PERFCOUNTER1_LO 0xd004
+#define mmCPC_PERFCOUNTER1_HI 0xd005
+#define mmCPC_PERFCOUNTER0_SELECT1 0xd804
+#define mmCPC_PERFCOUNTER0_SELECT 0xd809
+#define mmCPC_PERFCOUNTER0_LO 0xd006
+#define mmCPC_PERFCOUNTER0_HI 0xd007
+#define mmCPF_PERFCOUNTER1_SELECT 0xd805
+#define mmCPF_PERFCOUNTER1_LO 0xd008
+#define mmCPF_PERFCOUNTER1_HI 0xd009
+#define mmCPF_PERFCOUNTER0_SELECT1 0xd806
+#define mmCPF_PERFCOUNTER0_SELECT 0xd807
+#define mmCPF_PERFCOUNTER0_LO 0xd00a
+#define mmCPF_PERFCOUNTER0_HI 0xd00b
+#define mmCP_CPC_HALT_HYST_COUNT 0x20a7
+#define mmCP_DRAW_OBJECT 0xd810
+#define mmCP_DRAW_OBJECT_COUNTER 0xd811
+#define mmCP_DRAW_WINDOW_MASK_HI 0xd812
+#define mmCP_DRAW_WINDOW_HI 0xd813
+#define mmCP_DRAW_WINDOW_LO 0xd814
+#define mmCP_DRAW_WINDOW_CNTL 0xd815
+#define mmCP_PRT_LOD_STATS_CNTL0 0x20ad
+#define mmCP_PRT_LOD_STATS_CNTL1 0x20ae
+#define mmCP_PRT_LOD_STATS_CNTL2 0x20af
+#define mmCP_CE_COMPARE_COUNT 0x20c0
+#define mmCP_CE_DE_COUNT 0x20c1
+#define mmCP_DE_CE_COUNT 0x20c2
+#define mmCP_DE_LAST_INVAL_COUNT 0x20c3
+#define mmCP_DE_DE_COUNT 0x20c4
+#define mmCP_EOP_DONE_EVENT_CNTL 0xc0d5
+#define mmCP_EOP_DONE_DATA_CNTL 0xc0d6
+#define mmCP_EOP_DONE_ADDR_LO 0xc000
+#define mmCP_EOP_DONE_ADDR_HI 0xc001
+#define mmCP_EOP_DONE_DATA_LO 0xc002
+#define mmCP_EOP_DONE_DATA_HI 0xc003
+#define mmCP_EOP_LAST_FENCE_LO 0xc004
+#define mmCP_EOP_LAST_FENCE_HI 0xc005
+#define mmCP_STREAM_OUT_ADDR_LO 0xc006
+#define mmCP_STREAM_OUT_ADDR_HI 0xc007
+#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0xc008
+#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0xc009
+#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0xc00a
+#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0xc00b
+#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0xc00c
+#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0xc00d
+#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0xc00e
+#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0xc00f
+#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0xc010
+#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0xc011
+#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0xc012
+#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0xc013
+#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0xc014
+#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0xc015
+#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0xc016
+#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0xc017
+#define mmCP_PIPE_STATS_ADDR_LO 0xc018
+#define mmCP_PIPE_STATS_ADDR_HI 0xc019
+#define mmCP_VGT_IAVERT_COUNT_LO 0xc01a
+#define mmCP_VGT_IAVERT_COUNT_HI 0xc01b
+#define mmCP_VGT_IAPRIM_COUNT_LO 0xc01c
+#define mmCP_VGT_IAPRIM_COUNT_HI 0xc01d
+#define mmCP_VGT_GSPRIM_COUNT_LO 0xc01e
+#define mmCP_VGT_GSPRIM_COUNT_HI 0xc01f
+#define mmCP_VGT_VSINVOC_COUNT_LO 0xc020
+#define mmCP_VGT_VSINVOC_COUNT_HI 0xc021
+#define mmCP_VGT_GSINVOC_COUNT_LO 0xc022
+#define mmCP_VGT_GSINVOC_COUNT_HI 0xc023
+#define mmCP_VGT_HSINVOC_COUNT_LO 0xc024
+#define mmCP_VGT_HSINVOC_COUNT_HI 0xc025
+#define mmCP_VGT_DSINVOC_COUNT_LO 0xc026
+#define mmCP_VGT_DSINVOC_COUNT_HI 0xc027
+#define mmCP_PA_CINVOC_COUNT_LO 0xc028
+#define mmCP_PA_CINVOC_COUNT_HI 0xc029
+#define mmCP_PA_CPRIM_COUNT_LO 0xc02a
+#define mmCP_PA_CPRIM_COUNT_HI 0xc02b
+#define mmCP_SC_PSINVOC_COUNT0_LO 0xc02c
+#define mmCP_SC_PSINVOC_COUNT0_HI 0xc02d
+#define mmCP_SC_PSINVOC_COUNT1_LO 0xc02e
+#define mmCP_SC_PSINVOC_COUNT1_HI 0xc02f
+#define mmCP_VGT_CSINVOC_COUNT_LO 0xc030
+#define mmCP_VGT_CSINVOC_COUNT_HI 0xc031
+#define mmCP_STRMOUT_CNTL 0xc03f
+#define mmSCRATCH_REG0 0xc040
+#define mmSCRATCH_REG1 0xc041
+#define mmSCRATCH_REG2 0xc042
+#define mmSCRATCH_REG3 0xc043
+#define mmSCRATCH_REG4 0xc044
+#define mmSCRATCH_REG5 0xc045
+#define mmSCRATCH_REG6 0xc046
+#define mmSCRATCH_REG7 0xc047
+#define mmSCRATCH_UMSK 0xc050
+#define mmSCRATCH_ADDR 0xc051
+#define mmCP_PFP_ATOMIC_PREOP_LO 0xc052
+#define mmCP_PFP_ATOMIC_PREOP_HI 0xc053
+#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0xc054
+#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0xc055
+#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0xc056
+#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0xc057
+#define mmCP_APPEND_ADDR_LO 0xc058
+#define mmCP_APPEND_ADDR_HI 0xc059
+#define mmCP_APPEND_DATA 0xc05a
+#define mmCP_APPEND_LAST_CS_FENCE 0xc05b
+#define mmCP_APPEND_LAST_PS_FENCE 0xc05c
+#define mmCP_ATOMIC_PREOP_LO 0xc05d
+#define mmCP_ME_ATOMIC_PREOP_LO 0xc05d
+#define mmCP_ATOMIC_PREOP_HI 0xc05e
+#define mmCP_ME_ATOMIC_PREOP_HI 0xc05e
+#define mmCP_GDS_ATOMIC0_PREOP_LO 0xc05f
+#define mmCP_ME_GDS_ATOMIC0_PREOP_LO 0xc05f
+#define mmCP_GDS_ATOMIC0_PREOP_HI 0xc060
+#define mmCP_ME_GDS_ATOMIC0_PREOP_HI 0xc060
+#define mmCP_GDS_ATOMIC1_PREOP_LO 0xc061
+#define mmCP_ME_GDS_ATOMIC1_PREOP_LO 0xc061
+#define mmCP_GDS_ATOMIC1_PREOP_HI 0xc062
+#define mmCP_ME_GDS_ATOMIC1_PREOP_HI 0xc062
+#define mmCP_ME_MC_WADDR_LO 0xc069
+#define mmCP_ME_MC_WADDR_HI 0xc06a
+#define mmCP_ME_MC_WDATA_LO 0xc06b
+#define mmCP_ME_MC_WDATA_HI 0xc06c
+#define mmCP_ME_MC_RADDR_LO 0xc06d
+#define mmCP_ME_MC_RADDR_HI 0xc06e
+#define mmCP_SEM_WAIT_TIMER 0xc06f
+#define mmCP_SIG_SEM_ADDR_LO 0xc070
+#define mmCP_SIG_SEM_ADDR_HI 0xc071
+#define mmCP_WAIT_SEM_ADDR_LO 0xc075
+#define mmCP_WAIT_SEM_ADDR_HI 0xc076
+#define mmCP_WAIT_REG_MEM_TIMEOUT 0xc074
+#define mmCP_COHER_START_DELAY 0xc07b
+#define mmCP_COHER_CNTL 0xc07c
+#define mmCP_COHER_SIZE 0xc07d
+#define mmCP_COHER_SIZE_HI 0xc08c
+#define mmCP_COHER_BASE 0xc07e
+#define mmCP_COHER_BASE_HI 0xc079
+#define mmCP_COHER_STATUS 0xc07f
+#define mmCOHER_DEST_BASE_0 0xa092
+#define mmCOHER_DEST_BASE_1 0xa093
+#define mmCOHER_DEST_BASE_2 0xa07e
+#define mmCOHER_DEST_BASE_3 0xa07f
+#define mmCOHER_DEST_BASE_HI_0 0xa07a
+#define mmCOHER_DEST_BASE_HI_1 0xa07b
+#define mmCOHER_DEST_BASE_HI_2 0xa07c
+#define mmCOHER_DEST_BASE_HI_3 0xa07d
+#define mmCP_DMA_ME_SRC_ADDR 0xc080
+#define mmCP_DMA_ME_SRC_ADDR_HI 0xc081
+#define mmCP_DMA_ME_DST_ADDR 0xc082
+#define mmCP_DMA_ME_DST_ADDR_HI 0xc083
+#define mmCP_DMA_ME_CONTROL 0xc078
+#define mmCP_DMA_ME_COMMAND 0xc084
+#define mmCP_DMA_PFP_SRC_ADDR 0xc085
+#define mmCP_DMA_PFP_SRC_ADDR_HI 0xc086
+#define mmCP_DMA_PFP_DST_ADDR 0xc087
+#define mmCP_DMA_PFP_DST_ADDR_HI 0xc088
+#define mmCP_DMA_PFP_CONTROL 0xc077
+#define mmCP_DMA_PFP_COMMAND 0xc089
+#define mmCP_DMA_CNTL 0xc08a
+#define mmCP_DMA_READ_TAGS 0xc08b
+#define mmCP_PFP_IB_CONTROL 0xc08d
+#define mmCP_PFP_LOAD_CONTROL 0xc08e
+#define mmCP_SCRATCH_INDEX 0xc08f
+#define mmCP_SCRATCH_DATA 0xc090
+#define mmCP_RB_OFFSET 0xc091
+#define mmCP_IB1_OFFSET 0xc092
+#define mmCP_IB2_OFFSET 0xc093
+#define mmCP_IB1_PREAMBLE_BEGIN 0xc094
+#define mmCP_IB1_PREAMBLE_END 0xc095
+#define mmCP_IB2_PREAMBLE_BEGIN 0xc096
+#define mmCP_IB2_PREAMBLE_END 0xc097
+#define mmCP_CE_IB1_OFFSET 0xc098
+#define mmCP_CE_IB2_OFFSET 0xc099
+#define mmCP_CE_COUNTER 0xc09a
+#define mmCP_STALLED_STAT1 0x219d
+#define mmCP_STALLED_STAT2 0x219e
+#define mmCP_STALLED_STAT3 0x219c
+#define mmCP_BUSY_STAT 0x219f
+#define mmCP_STAT 0x21a0
+#define mmCP_ME_HEADER_DUMP 0x21a1
+#define mmCP_PFP_HEADER_DUMP 0x21a2
+#define mmCP_GRBM_FREE_COUNT 0x21a3
+#define mmCP_CE_HEADER_DUMP 0x21a4
+#define mmCP_MC_PACK_DELAY_CNT 0x21a7
+#define mmCP_MC_TAG_CNTL 0x21a8
+#define mmCP_MC_TAG_DATA 0x21a9
+#define mmCP_CSF_STAT 0x21b4
+#define mmCP_CSF_CNTL 0x21b5
+#define mmCP_ME_CNTL 0x21b6
+#define mmCP_CNTX_STAT 0x21b8
+#define mmCP_ME_PREEMPTION 0x21b9
+#define mmCP_RB0_RPTR 0x21c0
+#define mmCP_RB_RPTR 0x21c0
+#define mmCP_RB1_RPTR 0x21bf
+#define mmCP_RB2_RPTR 0x21be
+#define mmCP_RB_WPTR_DELAY 0x21c1
+#define mmCP_RB_WPTR_POLL_CNTL 0x21c2
+#define mmCP_CE_INIT_BASE_LO 0xc0c3
+#define mmCP_CE_INIT_BASE_HI 0xc0c4
+#define mmCP_CE_INIT_BUFSZ 0xc0c5
+#define mmCP_CE_IB1_BASE_LO 0xc0c6
+#define mmCP_CE_IB1_BASE_HI 0xc0c7
+#define mmCP_CE_IB1_BUFSZ 0xc0c8
+#define mmCP_CE_IB2_BASE_LO 0xc0c9
+#define mmCP_CE_IB2_BASE_HI 0xc0ca
+#define mmCP_CE_IB2_BUFSZ 0xc0cb
+#define mmCP_IB1_BASE_LO 0xc0cc
+#define mmCP_IB1_BASE_HI 0xc0cd
+#define mmCP_IB1_BUFSZ 0xc0ce
+#define mmCP_IB2_BASE_LO 0xc0cf
+#define mmCP_IB2_BASE_HI 0xc0d0
+#define mmCP_IB2_BUFSZ 0xc0d1
+#define mmCP_ST_BASE_LO 0xc0d2
+#define mmCP_ST_BASE_HI 0xc0d3
+#define mmCP_ST_BUFSZ 0xc0d4
+#define mmCP_ROQ_THRESHOLDS 0x21bc
+#define mmCP_MEQ_STQ_THRESHOLD 0x21bd
+#define mmCP_ROQ1_THRESHOLDS 0x21d5
+#define mmCP_ROQ2_THRESHOLDS 0x21d6
+#define mmCP_STQ_THRESHOLDS 0x21d7
+#define mmCP_QUEUE_THRESHOLDS 0x21d8
+#define mmCP_MEQ_THRESHOLDS 0x21d9
+#define mmCP_ROQ_AVAIL 0x21da
+#define mmCP_STQ_AVAIL 0x21db
+#define mmCP_ROQ2_AVAIL 0x21dc
+#define mmCP_MEQ_AVAIL 0x21dd
+#define mmCP_CMD_INDEX 0x21de
+#define mmCP_CMD_DATA 0x21df
+#define mmCP_ROQ_RB_STAT 0x21e0
+#define mmCP_ROQ_IB1_STAT 0x21e1
+#define mmCP_ROQ_IB2_STAT 0x21e2
+#define mmCP_STQ_STAT 0x21e3
+#define mmCP_STQ_WR_STAT 0x21e4
+#define mmCP_MEQ_STAT 0x21e5
+#define mmCP_CEQ1_AVAIL 0x21e6
+#define mmCP_CEQ2_AVAIL 0x21e7
+#define mmCP_CE_ROQ_RB_STAT 0x21e8
+#define mmCP_CE_ROQ_IB1_STAT 0x21e9
+#define mmCP_CE_ROQ_IB2_STAT 0x21ea
+#define mmCP_INT_STAT_DEBUG 0x21f7
+#define mmCP_PERFMON_CNTL 0xd808
+#define mmCP_PERFMON_CNTX_CNTL 0xa0d8
+#define mmCP_RINGID 0xa0d9
+#define mmCP_PIPEID 0xa0d9
+#define mmCP_VMID 0xa0da
+#define mmCP_HPD_ROQ_OFFSETS 0x3240
+#define mmCP_HPD_EOP_BASE_ADDR 0x3241
+#define mmCP_HPD_EOP_BASE_ADDR_HI 0x3242
+#define mmCP_HPD_EOP_VMID 0x3243
+#define mmCP_HPD_EOP_CONTROL 0x3244
+#define mmCP_MQD_BASE_ADDR 0x3245
+#define mmCP_MQD_BASE_ADDR_HI 0x3246
+#define mmCP_HQD_ACTIVE 0x3247
+#define mmCP_HQD_VMID 0x3248
+#define mmCP_HQD_PERSISTENT_STATE 0x3249
+#define mmCP_HQD_PIPE_PRIORITY 0x324a
+#define mmCP_HQD_QUEUE_PRIORITY 0x324b
+#define mmCP_HQD_QUANTUM 0x324c
+#define mmCP_HQD_PQ_BASE 0x324d
+#define mmCP_HQD_PQ_BASE_HI 0x324e
+#define mmCP_HQD_PQ_RPTR 0x324f
+#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x3250
+#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x3251
+#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x3252
+#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x3253
+#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254
+#define mmCP_HQD_PQ_WPTR 0x3255
+#define mmCP_HQD_PQ_CONTROL 0x3256
+#define mmCP_HQD_IB_BASE_ADDR 0x3257
+#define mmCP_HQD_IB_BASE_ADDR_HI 0x3258
+#define mmCP_HQD_IB_RPTR 0x3259
+#define mmCP_HQD_IB_CONTROL 0x325a
+#define mmCP_HQD_IQ_TIMER 0x325b
+#define mmCP_HQD_IQ_RPTR 0x325c
+#define mmCP_HQD_DEQUEUE_REQUEST 0x325d
+#define mmCP_HQD_DMA_OFFLOAD 0x325e
+#define mmCP_HQD_SEMA_CMD 0x325f
+#define mmCP_HQD_MSG_TYPE 0x3260
+#define mmCP_HQD_ATOMIC0_PREOP_LO 0x3261
+#define mmCP_HQD_ATOMIC0_PREOP_HI 0x3262
+#define mmCP_HQD_ATOMIC1_PREOP_LO 0x3263
+#define mmCP_HQD_ATOMIC1_PREOP_HI 0x3264
+#define mmCP_HQD_HQ_SCHEDULER0 0x3265
+#define mmCP_HQD_HQ_SCHEDULER1 0x3266
+#define mmCP_MQD_CONTROL 0x3267
+#define mmDB_Z_READ_BASE 0xa012
+#define mmDB_STENCIL_READ_BASE 0xa013
+#define mmDB_Z_WRITE_BASE 0xa014
+#define mmDB_STENCIL_WRITE_BASE 0xa015
+#define mmDB_DEPTH_INFO 0xa00f
+#define mmDB_Z_INFO 0xa010
+#define mmDB_STENCIL_INFO 0xa011
+#define mmDB_DEPTH_SIZE 0xa016
+#define mmDB_DEPTH_SLICE 0xa017
+#define mmDB_DEPTH_VIEW 0xa002
+#define mmDB_RENDER_CONTROL 0xa000
+#define mmDB_COUNT_CONTROL 0xa001
+#define mmDB_RENDER_OVERRIDE 0xa003
+#define mmDB_RENDER_OVERRIDE2 0xa004
+#define mmDB_EQAA 0xa201
+#define mmDB_SHADER_CONTROL 0xa203
+#define mmDB_DEPTH_BOUNDS_MIN 0xa008
+#define mmDB_DEPTH_BOUNDS_MAX 0xa009
+#define mmDB_STENCIL_CLEAR 0xa00a
+#define mmDB_DEPTH_CLEAR 0xa00b
+#define mmDB_HTILE_DATA_BASE 0xa005
+#define mmDB_HTILE_SURFACE 0xa2af
+#define mmDB_PRELOAD_CONTROL 0xa2b2
+#define mmDB_STENCILREFMASK 0xa10c
+#define mmDB_STENCILREFMASK_BF 0xa10d
+#define mmDB_SRESULTS_COMPARE_STATE0 0xa2b0
+#define mmDB_SRESULTS_COMPARE_STATE1 0xa2b1
+#define mmDB_DEPTH_CONTROL 0xa200
+#define mmDB_STENCIL_CONTROL 0xa10b
+#define mmDB_ALPHA_TO_MASK 0xa2dc
+#define mmDB_PERFCOUNTER0_SELECT 0xdc40
+#define mmDB_PERFCOUNTER1_SELECT 0xdc42
+#define mmDB_PERFCOUNTER2_SELECT 0xdc44
+#define mmDB_PERFCOUNTER3_SELECT 0xdc46
+#define mmDB_PERFCOUNTER0_SELECT1 0xdc41
+#define mmDB_PERFCOUNTER1_SELECT1 0xdc43
+#define mmDB_PERFCOUNTER0_LO 0xd440
+#define mmDB_PERFCOUNTER1_LO 0xd442
+#define mmDB_PERFCOUNTER2_LO 0xd444
+#define mmDB_PERFCOUNTER3_LO 0xd446
+#define mmDB_PERFCOUNTER0_HI 0xd441
+#define mmDB_PERFCOUNTER1_HI 0xd443
+#define mmDB_PERFCOUNTER2_HI 0xd445
+#define mmDB_PERFCOUNTER3_HI 0xd447
+#define mmDB_DEBUG 0x260c
+#define mmDB_DEBUG2 0x260d
+#define mmDB_DEBUG3 0x260e
+#define mmDB_DEBUG4 0x260f
+#define mmDB_CREDIT_LIMIT 0x2614
+#define mmDB_WATERMARKS 0x2615
+#define mmDB_SUBTILE_CONTROL 0x2616
+#define mmDB_FREE_CACHELINES 0x2617
+#define mmDB_FIFO_DEPTH1 0x2618
+#define mmDB_FIFO_DEPTH2 0x2619
+#define mmDB_CGTT_CLK_CTRL_0 0xf0a4
+#define mmDB_ZPASS_COUNT_LOW 0xc3fe
+#define mmDB_ZPASS_COUNT_HI 0xc3ff
+#define mmDB_RING_CONTROL 0x261b
+#define mmDB_READ_DEBUG_0 0x2620
+#define mmDB_READ_DEBUG_1 0x2621
+#define mmDB_READ_DEBUG_2 0x2622
+#define mmDB_READ_DEBUG_3 0x2623
+#define mmDB_READ_DEBUG_4 0x2624
+#define mmDB_READ_DEBUG_5 0x2625
+#define mmDB_READ_DEBUG_6 0x2626
+#define mmDB_READ_DEBUG_7 0x2627
+#define mmDB_READ_DEBUG_8 0x2628
+#define mmDB_READ_DEBUG_9 0x2629
+#define mmDB_READ_DEBUG_A 0x262a
+#define mmDB_READ_DEBUG_B 0x262b
+#define mmDB_READ_DEBUG_C 0x262c
+#define mmDB_READ_DEBUG_D 0x262d
+#define mmDB_READ_DEBUG_E 0x262e
+#define mmDB_READ_DEBUG_F 0x262f
+#define mmDB_OCCLUSION_COUNT0_LOW 0xc3c0
+#define mmDB_OCCLUSION_COUNT0_HI 0xc3c1
+#define mmDB_OCCLUSION_COUNT1_LOW 0xc3c2
+#define mmDB_OCCLUSION_COUNT1_HI 0xc3c3
+#define mmDB_OCCLUSION_COUNT2_LOW 0xc3c4
+#define mmDB_OCCLUSION_COUNT2_HI 0xc3c5
+#define mmDB_OCCLUSION_COUNT3_LOW 0xc3c6
+#define mmDB_OCCLUSION_COUNT3_HI 0xc3c7
+#define mmCC_RB_REDUNDANCY 0x263c
+#define mmCC_RB_BACKEND_DISABLE 0x263d
+#define mmGC_USER_RB_REDUNDANCY 0x26de
+#define mmGC_USER_RB_BACKEND_DISABLE 0x26df
+#define mmGB_ADDR_CONFIG 0x263e
+#define mmGB_BACKEND_MAP 0x263f
+#define mmGB_GPU_ID 0x2640
+#define mmCC_RB_DAISY_CHAIN 0x2641
+#define mmGB_TILE_MODE0 0x2644
+#define mmGB_TILE_MODE1 0x2645
+#define mmGB_TILE_MODE2 0x2646
+#define mmGB_TILE_MODE3 0x2647
+#define mmGB_TILE_MODE4 0x2648
+#define mmGB_TILE_MODE5 0x2649
+#define mmGB_TILE_MODE6 0x264a
+#define mmGB_TILE_MODE7 0x264b
+#define mmGB_TILE_MODE8 0x264c
+#define mmGB_TILE_MODE9 0x264d
+#define mmGB_TILE_MODE10 0x264e
+#define mmGB_TILE_MODE11 0x264f
+#define mmGB_TILE_MODE12 0x2650
+#define mmGB_TILE_MODE13 0x2651
+#define mmGB_TILE_MODE14 0x2652
+#define mmGB_TILE_MODE15 0x2653
+#define mmGB_TILE_MODE16 0x2654
+#define mmGB_TILE_MODE17 0x2655
+#define mmGB_TILE_MODE18 0x2656
+#define mmGB_TILE_MODE19 0x2657
+#define mmGB_TILE_MODE20 0x2658
+#define mmGB_TILE_MODE21 0x2659
+#define mmGB_TILE_MODE22 0x265a
+#define mmGB_TILE_MODE23 0x265b
+#define mmGB_TILE_MODE24 0x265c
+#define mmGB_TILE_MODE25 0x265d
+#define mmGB_TILE_MODE26 0x265e
+#define mmGB_TILE_MODE27 0x265f
+#define mmGB_TILE_MODE28 0x2660
+#define mmGB_TILE_MODE29 0x2661
+#define mmGB_TILE_MODE30 0x2662
+#define mmGB_TILE_MODE31 0x2663
+#define mmGB_MACROTILE_MODE0 0x2664
+#define mmGB_MACROTILE_MODE1 0x2665
+#define mmGB_MACROTILE_MODE2 0x2666
+#define mmGB_MACROTILE_MODE3 0x2667
+#define mmGB_MACROTILE_MODE4 0x2668
+#define mmGB_MACROTILE_MODE5 0x2669
+#define mmGB_MACROTILE_MODE6 0x266a
+#define mmGB_MACROTILE_MODE7 0x266b
+#define mmGB_MACROTILE_MODE8 0x266c
+#define mmGB_MACROTILE_MODE9 0x266d
+#define mmGB_MACROTILE_MODE10 0x266e
+#define mmGB_MACROTILE_MODE11 0x266f
+#define mmGB_MACROTILE_MODE12 0x2670
+#define mmGB_MACROTILE_MODE13 0x2671
+#define mmGB_MACROTILE_MODE14 0x2672
+#define mmGB_MACROTILE_MODE15 0x2673
+#define mmGB_EDC_MODE 0x307e
+#define mmCC_GC_EDC_CONFIG 0x3098
+#define mmRAS_SIGNATURE_CONTROL 0x3380
+#define mmRAS_SIGNATURE_MASK 0x3381
+#define mmRAS_SX_SIGNATURE0 0x3382
+#define mmRAS_SX_SIGNATURE1 0x3383
+#define mmRAS_SX_SIGNATURE2 0x3384
+#define mmRAS_SX_SIGNATURE3 0x3385
+#define mmRAS_DB_SIGNATURE0 0x338b
+#define mmRAS_PA_SIGNATURE0 0x338c
+#define mmRAS_VGT_SIGNATURE0 0x338d
+#define mmRAS_SQ_SIGNATURE0 0x338e
+#define mmRAS_SC_SIGNATURE0 0x338f
+#define mmRAS_SC_SIGNATURE1 0x3390
+#define mmRAS_SC_SIGNATURE2 0x3391
+#define mmRAS_SC_SIGNATURE3 0x3392
+#define mmRAS_SC_SIGNATURE4 0x3393
+#define mmRAS_SC_SIGNATURE5 0x3394
+#define mmRAS_SC_SIGNATURE6 0x3395
+#define mmRAS_SC_SIGNATURE7 0x3396
+#define mmRAS_IA_SIGNATURE0 0x3397
+#define mmRAS_IA_SIGNATURE1 0x3398
+#define mmRAS_SPI_SIGNATURE0 0x3399
+#define mmRAS_SPI_SIGNATURE1 0x339a
+#define mmRAS_TA_SIGNATURE0 0x339b
+#define mmRAS_TD_SIGNATURE0 0x339c
+#define mmRAS_CB_SIGNATURE0 0x339d
+#define mmRAS_BCI_SIGNATURE0 0x339e
+#define mmRAS_BCI_SIGNATURE1 0x339f
+#define mmGRBM_CAM_INDEX 0x3000
+#define mmGRBM_CAM_DATA 0x3001
+#define mmGRBM_CNTL 0x2000
+#define mmGRBM_SKEW_CNTL 0x2001
+#define mmGRBM_PWR_CNTL 0x2003
+#define mmGRBM_STATUS 0x2004
+#define mmGRBM_STATUS2 0x2002
+#define mmGRBM_STATUS_SE0 0x2005
+#define mmGRBM_STATUS_SE1 0x2006
+#define mmGRBM_STATUS_SE2 0x200e
+#define mmGRBM_STATUS_SE3 0x200f
+#define mmGRBM_SOFT_RESET 0x2008
+#define mmGRBM_DEBUG_CNTL 0x2009
+#define mmGRBM_DEBUG_DATA 0x200a
+#define mmGRBM_GFX_INDEX 0xc200
+#define mmGRBM_GFX_CLKEN_CNTL 0x200c
+#define mmGRBM_WAIT_IDLE_CLOCKS 0x200d
+#define mmGRBM_DEBUG 0x2014
+#define mmGRBM_DEBUG_SNAPSHOT 0x2015
+#define mmGRBM_READ_ERROR 0x2016
+#define mmGRBM_READ_ERROR2 0x2017
+#define mmGRBM_INT_CNTL 0x2018
+#define mmGRBM_PERFCOUNTER0_SELECT 0xd840
+#define mmGRBM_PERFCOUNTER1_SELECT 0xd841
+#define mmGRBM_SE0_PERFCOUNTER_SELECT 0xd842
+#define mmGRBM_SE1_PERFCOUNTER_SELECT 0xd843
+#define mmGRBM_SE2_PERFCOUNTER_SELECT 0xd844
+#define mmGRBM_SE3_PERFCOUNTER_SELECT 0xd845
+#define mmGRBM_PERFCOUNTER0_LO 0xd040
+#define mmGRBM_PERFCOUNTER0_HI 0xd041
+#define mmGRBM_PERFCOUNTER1_LO 0xd043
+#define mmGRBM_PERFCOUNTER1_HI 0xd044
+#define mmGRBM_SE0_PERFCOUNTER_LO 0xd045
+#define mmGRBM_SE0_PERFCOUNTER_HI 0xd046
+#define mmGRBM_SE1_PERFCOUNTER_LO 0xd047
+#define mmGRBM_SE1_PERFCOUNTER_HI 0xd048
+#define mmGRBM_SE2_PERFCOUNTER_LO 0xd049
+#define mmGRBM_SE2_PERFCOUNTER_HI 0xd04a
+#define mmGRBM_SE3_PERFCOUNTER_LO 0xd04b
+#define mmGRBM_SE3_PERFCOUNTER_HI 0xd04c
+#define mmGRBM_SCRATCH_REG0 0x2040
+#define mmGRBM_SCRATCH_REG1 0x2041
+#define mmGRBM_SCRATCH_REG2 0x2042
+#define mmGRBM_SCRATCH_REG3 0x2043
+#define mmGRBM_SCRATCH_REG4 0x2044
+#define mmGRBM_SCRATCH_REG5 0x2045
+#define mmGRBM_SCRATCH_REG6 0x2046
+#define mmGRBM_SCRATCH_REG7 0x2047
+#define mmDEBUG_INDEX 0x203c
+#define mmDEBUG_DATA 0x203d
+#define mmGRBM_NOWHERE 0x203f
+#define mmPA_CL_VPORT_XSCALE 0xa10f
+#define mmPA_CL_VPORT_XOFFSET 0xa110
+#define mmPA_CL_VPORT_YSCALE 0xa111
+#define mmPA_CL_VPORT_YOFFSET 0xa112
+#define mmPA_CL_VPORT_ZSCALE 0xa113
+#define mmPA_CL_VPORT_ZOFFSET 0xa114
+#define mmPA_CL_VPORT_XSCALE_1 0xa115
+#define mmPA_CL_VPORT_XSCALE_2 0xa11b
+#define mmPA_CL_VPORT_XSCALE_3 0xa121
+#define mmPA_CL_VPORT_XSCALE_4 0xa127
+#define mmPA_CL_VPORT_XSCALE_5 0xa12d
+#define mmPA_CL_VPORT_XSCALE_6 0xa133
+#define mmPA_CL_VPORT_XSCALE_7 0xa139
+#define mmPA_CL_VPORT_XSCALE_8 0xa13f
+#define mmPA_CL_VPORT_XSCALE_9 0xa145
+#define mmPA_CL_VPORT_XSCALE_10 0xa14b
+#define mmPA_CL_VPORT_XSCALE_11 0xa151
+#define mmPA_CL_VPORT_XSCALE_12 0xa157
+#define mmPA_CL_VPORT_XSCALE_13 0xa15d
+#define mmPA_CL_VPORT_XSCALE_14 0xa163
+#define mmPA_CL_VPORT_XSCALE_15 0xa169
+#define mmPA_CL_VPORT_XOFFSET_1 0xa116
+#define mmPA_CL_VPORT_XOFFSET_2 0xa11c
+#define mmPA_CL_VPORT_XOFFSET_3 0xa122
+#define mmPA_CL_VPORT_XOFFSET_4 0xa128
+#define mmPA_CL_VPORT_XOFFSET_5 0xa12e
+#define mmPA_CL_VPORT_XOFFSET_6 0xa134
+#define mmPA_CL_VPORT_XOFFSET_7 0xa13a
+#define mmPA_CL_VPORT_XOFFSET_8 0xa140
+#define mmPA_CL_VPORT_XOFFSET_9 0xa146
+#define mmPA_CL_VPORT_XOFFSET_10 0xa14c
+#define mmPA_CL_VPORT_XOFFSET_11 0xa152
+#define mmPA_CL_VPORT_XOFFSET_12 0xa158
+#define mmPA_CL_VPORT_XOFFSET_13 0xa15e
+#define mmPA_CL_VPORT_XOFFSET_14 0xa164
+#define mmPA_CL_VPORT_XOFFSET_15 0xa16a
+#define mmPA_CL_VPORT_YSCALE_1 0xa117
+#define mmPA_CL_VPORT_YSCALE_2 0xa11d
+#define mmPA_CL_VPORT_YSCALE_3 0xa123
+#define mmPA_CL_VPORT_YSCALE_4 0xa129
+#define mmPA_CL_VPORT_YSCALE_5 0xa12f
+#define mmPA_CL_VPORT_YSCALE_6 0xa135
+#define mmPA_CL_VPORT_YSCALE_7 0xa13b
+#define mmPA_CL_VPORT_YSCALE_8 0xa141
+#define mmPA_CL_VPORT_YSCALE_9 0xa147
+#define mmPA_CL_VPORT_YSCALE_10 0xa14d
+#define mmPA_CL_VPORT_YSCALE_11 0xa153
+#define mmPA_CL_VPORT_YSCALE_12 0xa159
+#define mmPA_CL_VPORT_YSCALE_13 0xa15f
+#define mmPA_CL_VPORT_YSCALE_14 0xa165
+#define mmPA_CL_VPORT_YSCALE_15 0xa16b
+#define mmPA_CL_VPORT_YOFFSET_1 0xa118
+#define mmPA_CL_VPORT_YOFFSET_2 0xa11e
+#define mmPA_CL_VPORT_YOFFSET_3 0xa124
+#define mmPA_CL_VPORT_YOFFSET_4 0xa12a
+#define mmPA_CL_VPORT_YOFFSET_5 0xa130
+#define mmPA_CL_VPORT_YOFFSET_6 0xa136
+#define mmPA_CL_VPORT_YOFFSET_7 0xa13c
+#define mmPA_CL_VPORT_YOFFSET_8 0xa142
+#define mmPA_CL_VPORT_YOFFSET_9 0xa148
+#define mmPA_CL_VPORT_YOFFSET_10 0xa14e
+#define mmPA_CL_VPORT_YOFFSET_11 0xa154
+#define mmPA_CL_VPORT_YOFFSET_12 0xa15a
+#define mmPA_CL_VPORT_YOFFSET_13 0xa160
+#define mmPA_CL_VPORT_YOFFSET_14 0xa166
+#define mmPA_CL_VPORT_YOFFSET_15 0xa16c
+#define mmPA_CL_VPORT_ZSCALE_1 0xa119
+#define mmPA_CL_VPORT_ZSCALE_2 0xa11f
+#define mmPA_CL_VPORT_ZSCALE_3 0xa125
+#define mmPA_CL_VPORT_ZSCALE_4 0xa12b
+#define mmPA_CL_VPORT_ZSCALE_5 0xa131
+#define mmPA_CL_VPORT_ZSCALE_6 0xa137
+#define mmPA_CL_VPORT_ZSCALE_7 0xa13d
+#define mmPA_CL_VPORT_ZSCALE_8 0xa143
+#define mmPA_CL_VPORT_ZSCALE_9 0xa149
+#define mmPA_CL_VPORT_ZSCALE_10 0xa14f
+#define mmPA_CL_VPORT_ZSCALE_11 0xa155
+#define mmPA_CL_VPORT_ZSCALE_12 0xa15b
+#define mmPA_CL_VPORT_ZSCALE_13 0xa161
+#define mmPA_CL_VPORT_ZSCALE_14 0xa167
+#define mmPA_CL_VPORT_ZSCALE_15 0xa16d
+#define mmPA_CL_VPORT_ZOFFSET_1 0xa11a
+#define mmPA_CL_VPORT_ZOFFSET_2 0xa120
+#define mmPA_CL_VPORT_ZOFFSET_3 0xa126
+#define mmPA_CL_VPORT_ZOFFSET_4 0xa12c
+#define mmPA_CL_VPORT_ZOFFSET_5 0xa132
+#define mmPA_CL_VPORT_ZOFFSET_6 0xa138
+#define mmPA_CL_VPORT_ZOFFSET_7 0xa13e
+#define mmPA_CL_VPORT_ZOFFSET_8 0xa144
+#define mmPA_CL_VPORT_ZOFFSET_9 0xa14a
+#define mmPA_CL_VPORT_ZOFFSET_10 0xa150
+#define mmPA_CL_VPORT_ZOFFSET_11 0xa156
+#define mmPA_CL_VPORT_ZOFFSET_12 0xa15c
+#define mmPA_CL_VPORT_ZOFFSET_13 0xa162
+#define mmPA_CL_VPORT_ZOFFSET_14 0xa168
+#define mmPA_CL_VPORT_ZOFFSET_15 0xa16e
+#define mmPA_CL_VTE_CNTL 0xa206
+#define mmPA_CL_VS_OUT_CNTL 0xa207
+#define mmPA_CL_NANINF_CNTL 0xa208
+#define mmPA_CL_CLIP_CNTL 0xa204
+#define mmPA_CL_GB_VERT_CLIP_ADJ 0xa2fa
+#define mmPA_CL_GB_VERT_DISC_ADJ 0xa2fb
+#define mmPA_CL_GB_HORZ_CLIP_ADJ 0xa2fc
+#define mmPA_CL_GB_HORZ_DISC_ADJ 0xa2fd
+#define mmPA_CL_UCP_0_X 0xa16f
+#define mmPA_CL_UCP_0_Y 0xa170
+#define mmPA_CL_UCP_0_Z 0xa171
+#define mmPA_CL_UCP_0_W 0xa172
+#define mmPA_CL_UCP_1_X 0xa173
+#define mmPA_CL_UCP_1_Y 0xa174
+#define mmPA_CL_UCP_1_Z 0xa175
+#define mmPA_CL_UCP_1_W 0xa176
+#define mmPA_CL_UCP_2_X 0xa177
+#define mmPA_CL_UCP_2_Y 0xa178
+#define mmPA_CL_UCP_2_Z 0xa179
+#define mmPA_CL_UCP_2_W 0xa17a
+#define mmPA_CL_UCP_3_X 0xa17b
+#define mmPA_CL_UCP_3_Y 0xa17c
+#define mmPA_CL_UCP_3_Z 0xa17d
+#define mmPA_CL_UCP_3_W 0xa17e
+#define mmPA_CL_UCP_4_X 0xa17f
+#define mmPA_CL_UCP_4_Y 0xa180
+#define mmPA_CL_UCP_4_Z 0xa181
+#define mmPA_CL_UCP_4_W 0xa182
+#define mmPA_CL_UCP_5_X 0xa183
+#define mmPA_CL_UCP_5_Y 0xa184
+#define mmPA_CL_UCP_5_Z 0xa185
+#define mmPA_CL_UCP_5_W 0xa186
+#define mmPA_CL_POINT_X_RAD 0xa1f5
+#define mmPA_CL_POINT_Y_RAD 0xa1f6
+#define mmPA_CL_POINT_SIZE 0xa1f7
+#define mmPA_CL_POINT_CULL_RAD 0xa1f8
+#define mmPA_CL_ENHANCE 0x2285
+#define mmPA_CL_RESET_DEBUG 0x2286
+#define mmPA_SU_VTX_CNTL 0xa2f9
+#define mmPA_SU_POINT_SIZE 0xa280
+#define mmPA_SU_POINT_MINMAX 0xa281
+#define mmPA_SU_LINE_CNTL 0xa282
+#define mmPA_SU_LINE_STIPPLE_CNTL 0xa209
+#define mmPA_SU_LINE_STIPPLE_SCALE 0xa20a
+#define mmPA_SU_PRIM_FILTER_CNTL 0xa20b
+#define mmPA_SU_SC_MODE_CNTL 0xa205
+#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0xa2de
+#define mmPA_SU_POLY_OFFSET_CLAMP 0xa2df
+#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0xa2e0
+#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0xa2e1
+#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0xa2e2
+#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0xa2e3
+#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0xa08d
+#define mmPA_SU_LINE_STIPPLE_VALUE 0xc280
+#define mmPA_SU_PERFCOUNTER0_SELECT 0xd900
+#define mmPA_SU_PERFCOUNTER0_SELECT1 0xd901
+#define mmPA_SU_PERFCOUNTER1_SELECT 0xd902
+#define mmPA_SU_PERFCOUNTER1_SELECT1 0xd903
+#define mmPA_SU_PERFCOUNTER2_SELECT 0xd904
+#define mmPA_SU_PERFCOUNTER3_SELECT 0xd905
+#define mmPA_SU_PERFCOUNTER0_LO 0xd100
+#define mmPA_SU_PERFCOUNTER0_HI 0xd101
+#define mmPA_SU_PERFCOUNTER1_LO 0xd102
+#define mmPA_SU_PERFCOUNTER1_HI 0xd103
+#define mmPA_SU_PERFCOUNTER2_LO 0xd104
+#define mmPA_SU_PERFCOUNTER2_HI 0xd105
+#define mmPA_SU_PERFCOUNTER3_LO 0xd106
+#define mmPA_SU_PERFCOUNTER3_HI 0xd107
+#define mmPA_SC_AA_CONFIG 0xa2f8
+#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0xa30e
+#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0xa30f
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0xa2fe
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0xa2ff
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0xa300
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0xa301
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0xa302
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0xa303
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0xa304
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0xa305
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0xa306
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0xa307
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0xa308
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0xa309
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0xa30a
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0xa30b
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0xa30c
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0xa30d
+#define mmPA_SC_CENTROID_PRIORITY_0 0xa2f5
+#define mmPA_SC_CENTROID_PRIORITY_1 0xa2f6
+#define mmPA_SC_CLIPRECT_0_TL 0xa084
+#define mmPA_SC_CLIPRECT_0_BR 0xa085
+#define mmPA_SC_CLIPRECT_1_TL 0xa086
+#define mmPA_SC_CLIPRECT_1_BR 0xa087
+#define mmPA_SC_CLIPRECT_2_TL 0xa088
+#define mmPA_SC_CLIPRECT_2_BR 0xa089
+#define mmPA_SC_CLIPRECT_3_TL 0xa08a
+#define mmPA_SC_CLIPRECT_3_BR 0xa08b
+#define mmPA_SC_CLIPRECT_RULE 0xa083
+#define mmPA_SC_EDGERULE 0xa08c
+#define mmPA_SC_LINE_CNTL 0xa2f7
+#define mmPA_SC_LINE_STIPPLE 0xa283
+#define mmPA_SC_MODE_CNTL_0 0xa292
+#define mmPA_SC_MODE_CNTL_1 0xa293
+#define mmPA_SC_RASTER_CONFIG 0xa0d4
+#define mmPA_SC_RASTER_CONFIG_1 0xa0d5
+#define mmPA_SC_SCREEN_EXTENT_CONTROL 0xa0d6
+#define mmPA_SC_GENERIC_SCISSOR_TL 0xa090
+#define mmPA_SC_GENERIC_SCISSOR_BR 0xa091
+#define mmPA_SC_SCREEN_SCISSOR_TL 0xa00c
+#define mmPA_SC_SCREEN_SCISSOR_BR 0xa00d
+#define mmPA_SC_WINDOW_OFFSET 0xa080
+#define mmPA_SC_WINDOW_SCISSOR_TL 0xa081
+#define mmPA_SC_WINDOW_SCISSOR_BR 0xa082
+#define mmPA_SC_VPORT_SCISSOR_0_TL 0xa094
+#define mmPA_SC_VPORT_SCISSOR_1_TL 0xa096
+#define mmPA_SC_VPORT_SCISSOR_2_TL 0xa098
+#define mmPA_SC_VPORT_SCISSOR_3_TL 0xa09a
+#define mmPA_SC_VPORT_SCISSOR_4_TL 0xa09c
+#define mmPA_SC_VPORT_SCISSOR_5_TL 0xa09e
+#define mmPA_SC_VPORT_SCISSOR_6_TL 0xa0a0
+#define mmPA_SC_VPORT_SCISSOR_7_TL 0xa0a2
+#define mmPA_SC_VPORT_SCISSOR_8_TL 0xa0a4
+#define mmPA_SC_VPORT_SCISSOR_9_TL 0xa0a6
+#define mmPA_SC_VPORT_SCISSOR_10_TL 0xa0a8
+#define mmPA_SC_VPORT_SCISSOR_11_TL 0xa0aa
+#define mmPA_SC_VPORT_SCISSOR_12_TL 0xa0ac
+#define mmPA_SC_VPORT_SCISSOR_13_TL 0xa0ae
+#define mmPA_SC_VPORT_SCISSOR_14_TL 0xa0b0
+#define mmPA_SC_VPORT_SCISSOR_15_TL 0xa0b2
+#define mmPA_SC_VPORT_SCISSOR_0_BR 0xa095
+#define mmPA_SC_VPORT_SCISSOR_1_BR 0xa097
+#define mmPA_SC_VPORT_SCISSOR_2_BR 0xa099
+#define mmPA_SC_VPORT_SCISSOR_3_BR 0xa09b
+#define mmPA_SC_VPORT_SCISSOR_4_BR 0xa09d
+#define mmPA_SC_VPORT_SCISSOR_5_BR 0xa09f
+#define mmPA_SC_VPORT_SCISSOR_6_BR 0xa0a1
+#define mmPA_SC_VPORT_SCISSOR_7_BR 0xa0a3
+#define mmPA_SC_VPORT_SCISSOR_8_BR 0xa0a5
+#define mmPA_SC_VPORT_SCISSOR_9_BR 0xa0a7
+#define mmPA_SC_VPORT_SCISSOR_10_BR 0xa0a9
+#define mmPA_SC_VPORT_SCISSOR_11_BR 0xa0ab
+#define mmPA_SC_VPORT_SCISSOR_12_BR 0xa0ad
+#define mmPA_SC_VPORT_SCISSOR_13_BR 0xa0af
+#define mmPA_SC_VPORT_SCISSOR_14_BR 0xa0b1
+#define mmPA_SC_VPORT_SCISSOR_15_BR 0xa0b3
+#define mmPA_SC_VPORT_ZMIN_0 0xa0b4
+#define mmPA_SC_VPORT_ZMIN_1 0xa0b6
+#define mmPA_SC_VPORT_ZMIN_2 0xa0b8
+#define mmPA_SC_VPORT_ZMIN_3 0xa0ba
+#define mmPA_SC_VPORT_ZMIN_4 0xa0bc
+#define mmPA_SC_VPORT_ZMIN_5 0xa0be
+#define mmPA_SC_VPORT_ZMIN_6 0xa0c0
+#define mmPA_SC_VPORT_ZMIN_7 0xa0c2
+#define mmPA_SC_VPORT_ZMIN_8 0xa0c4
+#define mmPA_SC_VPORT_ZMIN_9 0xa0c6
+#define mmPA_SC_VPORT_ZMIN_10 0xa0c8
+#define mmPA_SC_VPORT_ZMIN_11 0xa0ca
+#define mmPA_SC_VPORT_ZMIN_12 0xa0cc
+#define mmPA_SC_VPORT_ZMIN_13 0xa0ce
+#define mmPA_SC_VPORT_ZMIN_14 0xa0d0
+#define mmPA_SC_VPORT_ZMIN_15 0xa0d2
+#define mmPA_SC_VPORT_ZMAX_0 0xa0b5
+#define mmPA_SC_VPORT_ZMAX_1 0xa0b7
+#define mmPA_SC_VPORT_ZMAX_2 0xa0b9
+#define mmPA_SC_VPORT_ZMAX_3 0xa0bb
+#define mmPA_SC_VPORT_ZMAX_4 0xa0bd
+#define mmPA_SC_VPORT_ZMAX_5 0xa0bf
+#define mmPA_SC_VPORT_ZMAX_6 0xa0c1
+#define mmPA_SC_VPORT_ZMAX_7 0xa0c3
+#define mmPA_SC_VPORT_ZMAX_8 0xa0c5
+#define mmPA_SC_VPORT_ZMAX_9 0xa0c7
+#define mmPA_SC_VPORT_ZMAX_10 0xa0c9
+#define mmPA_SC_VPORT_ZMAX_11 0xa0cb
+#define mmPA_SC_VPORT_ZMAX_12 0xa0cd
+#define mmPA_SC_VPORT_ZMAX_13 0xa0cf
+#define mmPA_SC_VPORT_ZMAX_14 0xa0d1
+#define mmPA_SC_VPORT_ZMAX_15 0xa0d3
+#define mmPA_SC_ENHANCE 0x22fc
+#define mmPA_SC_FIFO_SIZE 0x22f3
+#define mmPA_SC_IF_FIFO_SIZE 0x22f5
+#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x22c9
+#define mmPA_SC_LINE_STIPPLE_STATE 0xc281
+#define mmPA_SC_SCREEN_EXTENT_MIN_0 0xc284
+#define mmPA_SC_SCREEN_EXTENT_MAX_0 0xc285
+#define mmPA_SC_SCREEN_EXTENT_MIN_1 0xc286
+#define mmPA_SC_SCREEN_EXTENT_MAX_1 0xc28b
+#define mmPA_SC_PERFCOUNTER0_SELECT 0xd940
+#define mmPA_SC_PERFCOUNTER0_SELECT1 0xd941
+#define mmPA_SC_PERFCOUNTER1_SELECT 0xd942
+#define mmPA_SC_PERFCOUNTER2_SELECT 0xd943
+#define mmPA_SC_PERFCOUNTER3_SELECT 0xd944
+#define mmPA_SC_PERFCOUNTER4_SELECT 0xd945
+#define mmPA_SC_PERFCOUNTER5_SELECT 0xd946
+#define mmPA_SC_PERFCOUNTER6_SELECT 0xd947
+#define mmPA_SC_PERFCOUNTER7_SELECT 0xd948
+#define mmPA_SC_PERFCOUNTER0_LO 0xd140
+#define mmPA_SC_PERFCOUNTER0_HI 0xd141
+#define mmPA_SC_PERFCOUNTER1_LO 0xd142
+#define mmPA_SC_PERFCOUNTER1_HI 0xd143
+#define mmPA_SC_PERFCOUNTER2_LO 0xd144
+#define mmPA_SC_PERFCOUNTER2_HI 0xd145
+#define mmPA_SC_PERFCOUNTER3_LO 0xd146
+#define mmPA_SC_PERFCOUNTER3_HI 0xd147
+#define mmPA_SC_PERFCOUNTER4_LO 0xd148
+#define mmPA_SC_PERFCOUNTER4_HI 0xd149
+#define mmPA_SC_PERFCOUNTER5_LO 0xd14a
+#define mmPA_SC_PERFCOUNTER5_HI 0xd14b
+#define mmPA_SC_PERFCOUNTER6_LO 0xd14c
+#define mmPA_SC_PERFCOUNTER6_HI 0xd14d
+#define mmPA_SC_PERFCOUNTER7_LO 0xd14e
+#define mmPA_SC_PERFCOUNTER7_HI 0xd14f
+#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0xc2a0
+#define mmPA_SC_P3D_TRAP_SCREEN_H 0xc2a1
+#define mmPA_SC_P3D_TRAP_SCREEN_V 0xc2a2
+#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0xc2a3
+#define mmPA_SC_P3D_TRAP_SCREEN_COUNT 0xc2a4
+#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0xc2a8
+#define mmPA_SC_HP3D_TRAP_SCREEN_H 0xc2a9
+#define mmPA_SC_HP3D_TRAP_SCREEN_V 0xc2aa
+#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0xc2ab
+#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0xc2ac
+#define mmPA_SC_TRAP_SCREEN_HV_EN 0xc2b0
+#define mmPA_SC_TRAP_SCREEN_H 0xc2b1
+#define mmPA_SC_TRAP_SCREEN_V 0xc2b2
+#define mmPA_SC_TRAP_SCREEN_OCCURRENCE 0xc2b3
+#define mmPA_SC_TRAP_SCREEN_COUNT 0xc2b4
+#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x22c0
+#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x22c1
+#define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x22c2
+#define mmPA_CL_CNTL_STATUS 0x2284
+#define mmPA_SU_CNTL_STATUS 0x2294
+#define mmPA_SC_FIFO_DEPTH_CNTL 0x2295
+#define mmCGTT_PA_CLK_CTRL 0xf088
+#define mmCGTT_SC_CLK_CTRL 0xf089
+#define mmPA_SU_DEBUG_CNTL 0x2280
+#define mmPA_SU_DEBUG_DATA 0x2281
+#define mmPA_SC_DEBUG_CNTL 0x22f6
+#define mmPA_SC_DEBUG_DATA 0x22f7
+#define ixCLIPPER_DEBUG_REG00 0x0
+#define ixCLIPPER_DEBUG_REG01 0x1
+#define ixCLIPPER_DEBUG_REG02 0x2
+#define ixCLIPPER_DEBUG_REG03 0x3
+#define ixCLIPPER_DEBUG_REG04 0x4
+#define ixCLIPPER_DEBUG_REG05 0x5
+#define ixCLIPPER_DEBUG_REG06 0x6
+#define ixCLIPPER_DEBUG_REG07 0x7
+#define ixCLIPPER_DEBUG_REG08 0x8
+#define ixCLIPPER_DEBUG_REG09 0x9
+#define ixCLIPPER_DEBUG_REG10 0xa
+#define ixCLIPPER_DEBUG_REG11 0xb
+#define ixCLIPPER_DEBUG_REG12 0xc
+#define ixCLIPPER_DEBUG_REG13 0xd
+#define ixCLIPPER_DEBUG_REG14 0xe
+#define ixCLIPPER_DEBUG_REG15 0xf
+#define ixCLIPPER_DEBUG_REG16 0x10
+#define ixCLIPPER_DEBUG_REG17 0x11
+#define ixCLIPPER_DEBUG_REG18 0x12
+#define ixCLIPPER_DEBUG_REG19 0x13
+#define ixSXIFCCG_DEBUG_REG0 0x14
+#define ixSXIFCCG_DEBUG_REG1 0x15
+#define ixSXIFCCG_DEBUG_REG2 0x16
+#define ixSXIFCCG_DEBUG_REG3 0x17
+#define ixSETUP_DEBUG_REG0 0x18
+#define ixSETUP_DEBUG_REG1 0x19
+#define ixSETUP_DEBUG_REG2 0x1a
+#define ixSETUP_DEBUG_REG3 0x1b
+#define ixSETUP_DEBUG_REG4 0x1c
+#define ixSETUP_DEBUG_REG5 0x1d
+#define ixPA_SC_DEBUG_REG0 0x0
+#define ixPA_SC_DEBUG_REG1 0x1
+#define mmCOMPUTE_DISPATCH_INITIATOR 0x2e00
+#define mmCOMPUTE_DIM_X 0x2e01
+#define mmCOMPUTE_DIM_Y 0x2e02
+#define mmCOMPUTE_DIM_Z 0x2e03
+#define mmCOMPUTE_START_X 0x2e04
+#define mmCOMPUTE_START_Y 0x2e05
+#define mmCOMPUTE_START_Z 0x2e06
+#define mmCOMPUTE_NUM_THREAD_X 0x2e07
+#define mmCOMPUTE_NUM_THREAD_Y 0x2e08
+#define mmCOMPUTE_NUM_THREAD_Z 0x2e09
+#define mmCOMPUTE_PIPELINESTAT_ENABLE 0x2e0a
+#define mmCOMPUTE_PERFCOUNT_ENABLE 0x2e0b
+#define mmCOMPUTE_PGM_LO 0x2e0c
+#define mmCOMPUTE_PGM_HI 0x2e0d
+#define mmCOMPUTE_TBA_LO 0x2e0e
+#define mmCOMPUTE_TBA_HI 0x2e0f
+#define mmCOMPUTE_TMA_LO 0x2e10
+#define mmCOMPUTE_TMA_HI 0x2e11
+#define mmCOMPUTE_PGM_RSRC1 0x2e12
+#define mmCOMPUTE_PGM_RSRC2 0x2e13
+#define mmCOMPUTE_VMID 0x2e14
+#define mmCOMPUTE_RESOURCE_LIMITS 0x2e15
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x2e16
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x2e17
+#define mmCOMPUTE_TMPRING_SIZE 0x2e18
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x2e19
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x2e1a
+#define mmCOMPUTE_RESTART_X 0x2e1b
+#define mmCOMPUTE_RESTART_Y 0x2e1c
+#define mmCOMPUTE_RESTART_Z 0x2e1d
+#define mmCOMPUTE_THREAD_TRACE_ENABLE 0x2e1e
+#define mmCOMPUTE_MISC_RESERVED 0x2e1f
+#define mmCOMPUTE_USER_DATA_0 0x2e40
+#define mmCOMPUTE_USER_DATA_1 0x2e41
+#define mmCOMPUTE_USER_DATA_2 0x2e42
+#define mmCOMPUTE_USER_DATA_3 0x2e43
+#define mmCOMPUTE_USER_DATA_4 0x2e44
+#define mmCOMPUTE_USER_DATA_5 0x2e45
+#define mmCOMPUTE_USER_DATA_6 0x2e46
+#define mmCOMPUTE_USER_DATA_7 0x2e47
+#define mmCOMPUTE_USER_DATA_8 0x2e48
+#define mmCOMPUTE_USER_DATA_9 0x2e49
+#define mmCOMPUTE_USER_DATA_10 0x2e4a
+#define mmCOMPUTE_USER_DATA_11 0x2e4b
+#define mmCOMPUTE_USER_DATA_12 0x2e4c
+#define mmCOMPUTE_USER_DATA_13 0x2e4d
+#define mmCOMPUTE_USER_DATA_14 0x2e4e
+#define mmCOMPUTE_USER_DATA_15 0x2e4f
+#define mmCSPRIV_CONNECT 0x0
+#define mmCSPRIV_THREAD_TRACE_TG0 0x1e
+#define mmCSPRIV_THREAD_TRACE_TG1 0x1e
+#define mmCSPRIV_THREAD_TRACE_TG2 0x1e
+#define mmCSPRIV_THREAD_TRACE_TG3 0x1e
+#define mmCSPRIV_THREAD_TRACE_EVENT 0x1f
+#define mmRLC_CNTL 0x30c0
+#define mmRLC_DEBUG_SELECT 0x30c1
+#define mmRLC_DEBUG 0x30c2
+#define mmRLC_MC_CNTL 0x30c3
+#define mmRLC_STAT 0x30c4
+#define mmRLC_SAFE_MODE 0x313a
+#define mmRLC_SOFT_RESET_GPU 0x30c5
+#define mmRLC_MEM_SLP_CNTL 0x30c6
+#define mmRLC_PERFMON_CNTL 0xdcc0
+#define mmRLC_PERFCOUNTER0_SELECT 0xdcc1
+#define mmRLC_PERFCOUNTER1_SELECT 0xdcc2
+#define mmRLC_PERFCOUNTER0_LO 0xd480
+#define mmRLC_PERFCOUNTER1_LO 0xd482
+#define mmRLC_PERFCOUNTER0_HI 0xd481
+#define mmRLC_PERFCOUNTER1_HI 0xd483
+#define mmCGTT_RLC_CLK_CTRL 0xf0b8
+#define mmRLC_LB_CNTL 0x30d9
+#define mmRLC_LB_CNTR_MAX 0x30d2
+#define mmRLC_LB_CNTR_INIT 0x30db
+#define mmRLC_LOAD_BALANCE_CNTR 0x30dc
+#define mmRLC_SAVE_AND_RESTORE_BASE 0x30dd
+#define mmRLC_JUMP_TABLE_RESTORE 0x30de
+#define mmRLC_DRIVER_CPDMA_STATUS 0x30de
+#define mmRLC_PG_DELAY_2 0x30df
+#define mmRLC_GPM_DEBUG_SELECT 0x30e0
+#define mmRLC_GPM_DEBUG 0x30e1
+#define mmRLC_GPM_UCODE_ADDR 0x30e2
+#define mmRLC_GPM_UCODE_DATA 0x30e3
+#define mmRLC_GPU_CLOCK_COUNT_LSB 0x30e4
+#define mmRLC_GPU_CLOCK_COUNT_MSB 0x30e5
+#define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0x30e6
+#define mmRLC_UCODE_CNTL 0x30e7
+#define mmRLC_GPM_STAT 0x3100
+#define mmRLC_GPU_CLOCK_32_RES_SEL 0x3101
+#define mmRLC_GPU_CLOCK_32 0x3102
+#define mmRLC_PG_CNTL 0x3103
+#define mmRLC_GPM_THREAD_PRIORITY 0x3104
+#define mmRLC_GPM_THREAD_ENABLE 0x3105
+#define mmRLC_GPM_VMID_THREAD0 0x3106
+#define mmRLC_GPM_VMID_THREAD1 0x3107
+#define mmRLC_CGTT_MGCG_OVERRIDE 0x3108
+#define mmRLC_CGCG_CGLS_CTRL 0x3109
+#define mmRLC_CGCG_RAMP_CTRL 0x310a
+#define mmRLC_DYN_PG_STATUS 0x310b
+#define mmRLC_DYN_PG_REQUEST 0x310c
+#define mmRLC_PG_DELAY 0x310d
+#define mmRLC_CU_STATUS 0x310e
+#define mmRLC_LB_INIT_CU_MASK 0x310f
+#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0x3110
+#define mmRLC_LB_PARAMS 0x3111
+#define mmRLC_THREAD1_DELAY 0x3112
+#define mmRLC_PG_ALWAYS_ON_CU_MASK 0x3113
+#define mmRLC_MAX_PG_CU 0x3114
+#define mmRLC_AUTO_PG_CTRL 0x3115
+#define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0x3116
+#define mmRLC_SMU_PG_CTRL 0x3117
+#define mmRLC_SMU_PG_WAKE_UP_CTRL 0x3118
+#define mmRLC_SERDES_RD_MASTER_INDEX 0x3119
+#define mmRLC_SERDES_RD_DATA_0 0x311a
+#define mmRLC_SERDES_RD_DATA_1 0x311b
+#define mmRLC_SERDES_RD_DATA_2 0x311c
+#define mmRLC_SERDES_WR_CU_MASTER_MASK 0x311d
+#define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0x311e
+#define mmRLC_SERDES_WR_CTRL 0x311f
+#define mmRLC_SERDES_WR_DATA 0x3120
+#define mmRLC_SERDES_CU_MASTER_BUSY 0x3121
+#define mmRLC_SERDES_NONCU_MASTER_BUSY 0x3122
+#define mmRLC_GPM_GENERAL_0 0x3123
+#define mmRLC_GPM_GENERAL_1 0x3124
+#define mmRLC_GPM_GENERAL_2 0x3125
+#define mmRLC_GPM_GENERAL_3 0x3126
+#define mmRLC_GPM_GENERAL_4 0x3127
+#define mmRLC_GPM_GENERAL_5 0x3128
+#define mmRLC_GPM_GENERAL_6 0x3129
+#define mmRLC_GPM_GENERAL_7 0x312a
+#define mmRLC_GPM_CU_PD_TIMEOUT 0x312b
+#define mmRLC_GPM_SCRATCH_ADDR 0x312c
+#define mmRLC_GPM_SCRATCH_DATA 0x312d
+#define mmRLC_STATIC_PG_STATUS 0x312e
+#define mmRLC_GPM_PERF_COUNT_0 0x312f
+#define mmRLC_GPM_PERF_COUNT_1 0x3130
+#define mmRLC_GPR_REG1 0x3139
+#define mmRLC_GPR_REG2 0x313a
+#define mmRLC_SPM_VMID 0x3131
+#define mmRLC_SPM_INT_CNTL 0x3132
+#define mmRLC_SPM_INT_STATUS 0x3133
+#define mmRLC_SPM_DEBUG_SELECT 0x3134
+#define mmRLC_SPM_DEBUG 0x3135
+#define mmRLC_GPM_LOG_ADDR 0x3136
+#define mmRLC_GPM_LOG_SIZE 0x3137
+#define mmRLC_GPM_LOG_CONT 0x3138
+#define mmRLC_SPM_PERFMON_CNTL 0xdc80
+#define mmRLC_SPM_PERFMON_RING_BASE_LO 0xdc81
+#define mmRLC_SPM_PERFMON_RING_BASE_HI 0xdc82
+#define mmRLC_SPM_PERFMON_RING_SIZE 0xdc83
+#define mmRLC_SPM_PERFMON_SEGMENT_SIZE 0xdc84
+#define mmRLC_SPM_SE_MUXSEL_ADDR 0xdc85
+#define mmRLC_SPM_SE_MUXSEL_DATA 0xdc86
+#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0xdc87
+#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0xdc88
+#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0xdc89
+#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0xdc8a
+#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0xdc8b
+#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0xdc8c
+#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0xdc8d
+#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0xdc8e
+#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0xdc90
+#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0xdc91
+#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0xdc92
+#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0xdc93
+#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0xdc94
+#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0xdc95
+#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0xdc96
+#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0xdc97
+#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0xdc98
+#define mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY 0xdc99
+#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0xdc9a
+#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0xdc9b
+#define mmRLC_SPM_GLOBAL_MUXSEL_DATA 0xdc9c
+#define mmRLC_SPM_RING_RDPTR 0xdc9d
+#define mmRLC_SPM_SEGMENT_THRESHOLD 0xdc9e
+#define mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY 0xdc9f
+#define mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY 0xdca0
+#define mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY 0xdca1
+#define mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY 0xdca2
+#define mmSPI_PS_INPUT_CNTL_0 0xa191
+#define mmSPI_PS_INPUT_CNTL_1 0xa192
+#define mmSPI_PS_INPUT_CNTL_2 0xa193
+#define mmSPI_PS_INPUT_CNTL_3 0xa194
+#define mmSPI_PS_INPUT_CNTL_4 0xa195
+#define mmSPI_PS_INPUT_CNTL_5 0xa196
+#define mmSPI_PS_INPUT_CNTL_6 0xa197
+#define mmSPI_PS_INPUT_CNTL_7 0xa198
+#define mmSPI_PS_INPUT_CNTL_8 0xa199
+#define mmSPI_PS_INPUT_CNTL_9 0xa19a
+#define mmSPI_PS_INPUT_CNTL_10 0xa19b
+#define mmSPI_PS_INPUT_CNTL_11 0xa19c
+#define mmSPI_PS_INPUT_CNTL_12 0xa19d
+#define mmSPI_PS_INPUT_CNTL_13 0xa19e
+#define mmSPI_PS_INPUT_CNTL_14 0xa19f
+#define mmSPI_PS_INPUT_CNTL_15 0xa1a0
+#define mmSPI_PS_INPUT_CNTL_16 0xa1a1
+#define mmSPI_PS_INPUT_CNTL_17 0xa1a2
+#define mmSPI_PS_INPUT_CNTL_18 0xa1a3
+#define mmSPI_PS_INPUT_CNTL_19 0xa1a4
+#define mmSPI_PS_INPUT_CNTL_20 0xa1a5
+#define mmSPI_PS_INPUT_CNTL_21 0xa1a6
+#define mmSPI_PS_INPUT_CNTL_22 0xa1a7
+#define mmSPI_PS_INPUT_CNTL_23 0xa1a8
+#define mmSPI_PS_INPUT_CNTL_24 0xa1a9
+#define mmSPI_PS_INPUT_CNTL_25 0xa1aa
+#define mmSPI_PS_INPUT_CNTL_26 0xa1ab
+#define mmSPI_PS_INPUT_CNTL_27 0xa1ac
+#define mmSPI_PS_INPUT_CNTL_28 0xa1ad
+#define mmSPI_PS_INPUT_CNTL_29 0xa1ae
+#define mmSPI_PS_INPUT_CNTL_30 0xa1af
+#define mmSPI_PS_INPUT_CNTL_31 0xa1b0
+#define mmSPI_VS_OUT_CONFIG 0xa1b1
+#define mmSPI_PS_INPUT_ENA 0xa1b3
+#define mmSPI_PS_INPUT_ADDR 0xa1b4
+#define mmSPI_INTERP_CONTROL_0 0xa1b5
+#define mmSPI_PS_IN_CONTROL 0xa1b6
+#define mmSPI_BARYC_CNTL 0xa1b8
+#define mmSPI_TMPRING_SIZE 0xa1ba
+#define mmSPI_SHADER_POS_FORMAT 0xa1c3
+#define mmSPI_SHADER_Z_FORMAT 0xa1c4
+#define mmSPI_SHADER_COL_FORMAT 0xa1c5
+#define mmSPI_ARB_PRIORITY 0x31c0
+#define mmSPI_ARB_CYCLES_0 0x31c1
+#define mmSPI_ARB_CYCLES_1 0x31c2
+#define mmSPI_CDBG_SYS_GFX 0x31c3
+#define mmSPI_CDBG_SYS_HP3D 0x31c4
+#define mmSPI_CDBG_SYS_CS0 0x31c5
+#define mmSPI_CDBG_SYS_CS1 0x31c6
+#define mmSPI_WCL_PIPE_PERCENT_GFX 0x31c7
+#define mmSPI_WCL_PIPE_PERCENT_HP3D 0x31c8
+#define mmSPI_WCL_PIPE_PERCENT_CS0 0x31c9
+#define mmSPI_WCL_PIPE_PERCENT_CS1 0x31ca
+#define mmSPI_WCL_PIPE_PERCENT_CS2 0x31cb
+#define mmSPI_WCL_PIPE_PERCENT_CS3 0x31cc
+#define mmSPI_WCL_PIPE_PERCENT_CS4 0x31cd
+#define mmSPI_WCL_PIPE_PERCENT_CS5 0x31ce
+#define mmSPI_WCL_PIPE_PERCENT_CS6 0x31cf
+#define mmSPI_WCL_PIPE_PERCENT_CS7 0x31d0
+#define mmSPI_GDBG_WAVE_CNTL 0x31d1
+#define mmSPI_GDBG_TRAP_CONFIG 0x31d2
+#define mmSPI_GDBG_TRAP_MASK 0x31d3
+#define mmSPI_GDBG_TBA_LO 0x31d4
+#define mmSPI_GDBG_TBA_HI 0x31d5
+#define mmSPI_GDBG_TMA_LO 0x31d6
+#define mmSPI_GDBG_TMA_HI 0x31d7
+#define mmSPI_GDBG_TRAP_DATA0 0x31d8
+#define mmSPI_GDBG_TRAP_DATA1 0x31d9
+#define mmSPI_RESET_DEBUG 0x31da
+#define mmSPI_COMPUTE_QUEUE_RESET 0x31db
+#define mmSPI_RESOURCE_RESERVE_CU_0 0x31dc
+#define mmSPI_RESOURCE_RESERVE_CU_1 0x31dd
+#define mmSPI_RESOURCE_RESERVE_CU_2 0x31de
+#define mmSPI_RESOURCE_RESERVE_CU_3 0x31df
+#define mmSPI_RESOURCE_RESERVE_CU_4 0x31e0
+#define mmSPI_RESOURCE_RESERVE_CU_5 0x31e1
+#define mmSPI_RESOURCE_RESERVE_CU_6 0x31e2
+#define mmSPI_RESOURCE_RESERVE_CU_7 0x31e3
+#define mmSPI_RESOURCE_RESERVE_CU_8 0x31e4
+#define mmSPI_RESOURCE_RESERVE_CU_9 0x31e5
+#define mmSPI_RESOURCE_RESERVE_CU_10 0x31f0
+#define mmSPI_RESOURCE_RESERVE_CU_11 0x31f1
+#define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x31e6
+#define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x31e7
+#define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x31e8
+#define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x31e9
+#define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x31ea
+#define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x31eb
+#define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x31ec
+#define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x31ed
+#define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x31ee
+#define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x31ef
+#define mmSPI_RESOURCE_RESERVE_EN_CU_10 0x31f2
+#define mmSPI_RESOURCE_RESERVE_EN_CU_11 0x31f3
+#define mmSPI_PS_MAX_WAVE_ID 0x243a
+#define mmSPI_CONFIG_CNTL 0x2440
+#define mmSPI_DEBUG_CNTL 0x2441
+#define mmSPI_DEBUG_READ 0x2442
+#define mmSPI_PERFCOUNTER0_SELECT 0xd980
+#define mmSPI_PERFCOUNTER1_SELECT 0xd981
+#define mmSPI_PERFCOUNTER2_SELECT 0xd982
+#define mmSPI_PERFCOUNTER3_SELECT 0xd983
+#define mmSPI_PERFCOUNTER0_SELECT1 0xd984
+#define mmSPI_PERFCOUNTER1_SELECT1 0xd985
+#define mmSPI_PERFCOUNTER2_SELECT1 0xd986
+#define mmSPI_PERFCOUNTER3_SELECT1 0xd987
+#define mmSPI_PERFCOUNTER4_SELECT 0xd988
+#define mmSPI_PERFCOUNTER5_SELECT 0xd989
+#define mmSPI_PERFCOUNTER_BINS 0xd98a
+#define mmSPI_PERFCOUNTER0_HI 0xd180
+#define mmSPI_PERFCOUNTER0_LO 0xd181
+#define mmSPI_PERFCOUNTER1_HI 0xd182
+#define mmSPI_PERFCOUNTER1_LO 0xd183
+#define mmSPI_PERFCOUNTER2_HI 0xd184
+#define mmSPI_PERFCOUNTER2_LO 0xd185
+#define mmSPI_PERFCOUNTER3_HI 0xd186
+#define mmSPI_PERFCOUNTER3_LO 0xd187
+#define mmSPI_PERFCOUNTER4_HI 0xd188
+#define mmSPI_PERFCOUNTER4_LO 0xd189
+#define mmSPI_PERFCOUNTER5_HI 0xd18a
+#define mmSPI_PERFCOUNTER5_LO 0xd18b
+#define mmSPI_CONFIG_CNTL_1 0x244f
+#define mmSPI_DEBUG_BUSY 0x2450
+#define mmCGTS_SM_CTRL_REG 0xf000
+#define mmCGTS_RD_CTRL_REG 0xf001
+#define mmCGTS_RD_REG 0xf002
+#define mmCGTS_TCC_DISABLE 0xf003
+#define mmCGTS_USER_TCC_DISABLE 0xf004
+#define mmCGTS_CU0_SP0_CTRL_REG 0xf008
+#define mmCGTS_CU0_LDS_SQ_CTRL_REG 0xf009
+#define mmCGTS_CU0_TA_SQC_CTRL_REG 0xf00a
+#define mmCGTS_CU0_SP1_CTRL_REG 0xf00b
+#define mmCGTS_CU0_TD_TCP_CTRL_REG 0xf00c
+#define mmCGTS_CU1_SP0_CTRL_REG 0xf00d
+#define mmCGTS_CU1_LDS_SQ_CTRL_REG 0xf00e
+#define mmCGTS_CU1_TA_CTRL_REG 0xf00f
+#define mmCGTS_CU1_SP1_CTRL_REG 0xf010
+#define mmCGTS_CU1_TD_TCP_CTRL_REG 0xf011
+#define mmCGTS_CU2_SP0_CTRL_REG 0xf012
+#define mmCGTS_CU2_LDS_SQ_CTRL_REG 0xf013
+#define mmCGTS_CU2_TA_CTRL_REG 0xf014
+#define mmCGTS_CU2_SP1_CTRL_REG 0xf015
+#define mmCGTS_CU2_TD_TCP_CTRL_REG 0xf016
+#define mmCGTS_CU3_SP0_CTRL_REG 0xf017
+#define mmCGTS_CU3_LDS_SQ_CTRL_REG 0xf018
+#define mmCGTS_CU3_TA_CTRL_REG 0xf019
+#define mmCGTS_CU3_SP1_CTRL_REG 0xf01a
+#define mmCGTS_CU3_TD_TCP_CTRL_REG 0xf01b
+#define mmCGTS_CU4_SP0_CTRL_REG 0xf01c
+#define mmCGTS_CU4_LDS_SQ_CTRL_REG 0xf01d
+#define mmCGTS_CU4_TA_SQC_CTRL_REG 0xf01e
+#define mmCGTS_CU4_SP1_CTRL_REG 0xf01f
+#define mmCGTS_CU4_TD_TCP_CTRL_REG 0xf020
+#define mmCGTS_CU5_SP0_CTRL_REG 0xf021
+#define mmCGTS_CU5_LDS_SQ_CTRL_REG 0xf022
+#define mmCGTS_CU5_TA_CTRL_REG 0xf023
+#define mmCGTS_CU5_SP1_CTRL_REG 0xf024
+#define mmCGTS_CU5_TD_TCP_CTRL_REG 0xf025
+#define mmCGTS_CU6_SP0_CTRL_REG 0xf026
+#define mmCGTS_CU6_LDS_SQ_CTRL_REG 0xf027
+#define mmCGTS_CU6_TA_CTRL_REG 0xf028
+#define mmCGTS_CU6_SP1_CTRL_REG 0xf029
+#define mmCGTS_CU6_TD_TCP_CTRL_REG 0xf02a
+#define mmCGTS_CU7_SP0_CTRL_REG 0xf02b
+#define mmCGTS_CU7_LDS_SQ_CTRL_REG 0xf02c
+#define mmCGTS_CU7_TA_CTRL_REG 0xf02d
+#define mmCGTS_CU7_SP1_CTRL_REG 0xf02e
+#define mmCGTS_CU7_TD_TCP_CTRL_REG 0xf02f
+#define mmCGTS_CU8_SP0_CTRL_REG 0xf030
+#define mmCGTS_CU8_LDS_SQ_CTRL_REG 0xf031
+#define mmCGTS_CU8_TA_SQC_CTRL_REG 0xf032
+#define mmCGTS_CU8_SP1_CTRL_REG 0xf033
+#define mmCGTS_CU8_TD_TCP_CTRL_REG 0xf034
+#define mmCGTS_CU9_SP0_CTRL_REG 0xf035
+#define mmCGTS_CU9_LDS_SQ_CTRL_REG 0xf036
+#define mmCGTS_CU9_TA_CTRL_REG 0xf037
+#define mmCGTS_CU9_SP1_CTRL_REG 0xf038
+#define mmCGTS_CU9_TD_TCP_CTRL_REG 0xf039
+#define mmCGTS_CU10_SP0_CTRL_REG 0xf03a
+#define mmCGTS_CU10_LDS_SQ_CTRL_REG 0xf03b
+#define mmCGTS_CU10_TA_CTRL_REG 0xf03c
+#define mmCGTS_CU10_SP1_CTRL_REG 0xf03d
+#define mmCGTS_CU10_TD_TCP_CTRL_REG 0xf03e
+#define mmCGTS_CU11_SP0_CTRL_REG 0xf03f
+#define mmCGTS_CU11_LDS_SQ_CTRL_REG 0xf040
+#define mmCGTS_CU11_TA_CTRL_REG 0xf041
+#define mmCGTS_CU11_SP1_CTRL_REG 0xf042
+#define mmCGTS_CU11_TD_TCP_CTRL_REG 0xf043
+#define mmCGTS_CU12_SP0_CTRL_REG 0xf044
+#define mmCGTS_CU12_LDS_SQ_CTRL_REG 0xf045
+#define mmCGTS_CU12_TA_SQC_CTRL_REG 0xf046
+#define mmCGTS_CU12_SP1_CTRL_REG 0xf047
+#define mmCGTS_CU12_TD_TCP_CTRL_REG 0xf048
+#define mmCGTS_CU13_SP0_CTRL_REG 0xf049
+#define mmCGTS_CU13_LDS_SQ_CTRL_REG 0xf04a
+#define mmCGTS_CU13_TA_CTRL_REG 0xf04b
+#define mmCGTS_CU13_SP1_CTRL_REG 0xf04c
+#define mmCGTS_CU13_TD_TCP_CTRL_REG 0xf04d
+#define mmCGTS_CU14_SP0_CTRL_REG 0xf04e
+#define mmCGTS_CU14_LDS_SQ_CTRL_REG 0xf04f
+#define mmCGTS_CU14_TA_CTRL_REG 0xf050
+#define mmCGTS_CU14_SP1_CTRL_REG 0xf051
+#define mmCGTS_CU14_TD_TCP_CTRL_REG 0xf052
+#define mmCGTS_CU15_SP0_CTRL_REG 0xf053
+#define mmCGTS_CU15_LDS_SQ_CTRL_REG 0xf054
+#define mmCGTS_CU15_TA_CTRL_REG 0xf055
+#define mmCGTS_CU15_SP1_CTRL_REG 0xf056
+#define mmCGTS_CU15_TD_TCP_CTRL_REG 0xf057
+#define mmCGTT_SPI_CLK_CTRL 0xf080
+#define mmCGTT_PC_CLK_CTRL 0xf081
+#define mmCGTT_BCI_CLK_CTRL 0xf082
+#define mmSPI_WF_LIFETIME_CNTL 0x24aa
+#define mmSPI_WF_LIFETIME_LIMIT_0 0x24ab
+#define mmSPI_WF_LIFETIME_LIMIT_1 0x24ac
+#define mmSPI_WF_LIFETIME_LIMIT_2 0x24ad
+#define mmSPI_WF_LIFETIME_LIMIT_3 0x24ae
+#define mmSPI_WF_LIFETIME_LIMIT_4 0x24af
+#define mmSPI_WF_LIFETIME_LIMIT_5 0x24b0
+#define mmSPI_WF_LIFETIME_LIMIT_6 0x24b1
+#define mmSPI_WF_LIFETIME_LIMIT_7 0x24b2
+#define mmSPI_WF_LIFETIME_LIMIT_8 0x24b3
+#define mmSPI_WF_LIFETIME_LIMIT_9 0x24b4
+#define mmSPI_WF_LIFETIME_STATUS_0 0x24b5
+#define mmSPI_WF_LIFETIME_STATUS_1 0x24b6
+#define mmSPI_WF_LIFETIME_STATUS_2 0x24b7
+#define mmSPI_WF_LIFETIME_STATUS_3 0x24b8
+#define mmSPI_WF_LIFETIME_STATUS_4 0x24b9
+#define mmSPI_WF_LIFETIME_STATUS_5 0x24ba
+#define mmSPI_WF_LIFETIME_STATUS_6 0x24bb
+#define mmSPI_WF_LIFETIME_STATUS_7 0x24bc
+#define mmSPI_WF_LIFETIME_STATUS_8 0x24bd
+#define mmSPI_WF_LIFETIME_STATUS_9 0x24be
+#define mmSPI_WF_LIFETIME_STATUS_10 0x24bf
+#define mmSPI_WF_LIFETIME_STATUS_11 0x24c0
+#define mmSPI_WF_LIFETIME_STATUS_12 0x24c1
+#define mmSPI_WF_LIFETIME_STATUS_13 0x24c2
+#define mmSPI_WF_LIFETIME_STATUS_14 0x24c3
+#define mmSPI_WF_LIFETIME_STATUS_15 0x24c4
+#define mmSPI_WF_LIFETIME_STATUS_16 0x24c5
+#define mmSPI_WF_LIFETIME_STATUS_17 0x24c6
+#define mmSPI_WF_LIFETIME_STATUS_18 0x24c7
+#define mmSPI_WF_LIFETIME_STATUS_19 0x24c8
+#define mmSPI_WF_LIFETIME_STATUS_20 0x24c9
+#define mmSPI_WF_LIFETIME_DEBUG 0x24ca
+#define mmSPI_SLAVE_DEBUG_BUSY 0x24d3
+#define mmSPI_LB_CTR_CTRL 0x24d4
+#define mmSPI_LB_CU_MASK 0x24d5
+#define mmSPI_LB_DATA_REG 0x24d6
+#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x24d7
+#define mmSPI_GDS_CREDITS 0x24d8
+#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x24d9
+#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x24da
+#define mmSPI_CSQ_WF_ACTIVE_STATUS 0x24db
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x24dc
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x24dd
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x24de
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x24df
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0x24e0
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0x24e1
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0x24e2
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0x24e3
+#define mmBCI_DEBUG_READ 0x24eb
+#define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x24ec
+#define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x24ed
+#define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x24ee
+#define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x24ef
+#define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x24f0
+#define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x24f1
+#define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x24f2
+#define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x24f3
+#define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x24f4
+#define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x24f5
+#define mmSPI_SHADER_TBA_LO_PS 0x2c00
+#define mmSPI_SHADER_TBA_HI_PS 0x2c01
+#define mmSPI_SHADER_TMA_LO_PS 0x2c02
+#define mmSPI_SHADER_TMA_HI_PS 0x2c03
+#define mmSPI_SHADER_PGM_LO_PS 0x2c08
+#define mmSPI_SHADER_PGM_HI_PS 0x2c09
+#define mmSPI_SHADER_PGM_RSRC1_PS 0x2c0a
+#define mmSPI_SHADER_PGM_RSRC2_PS 0x2c0b
+#define mmSPI_SHADER_PGM_RSRC3_PS 0x2c07
+#define mmSPI_SHADER_USER_DATA_PS_0 0x2c0c
+#define mmSPI_SHADER_USER_DATA_PS_1 0x2c0d
+#define mmSPI_SHADER_USER_DATA_PS_2 0x2c0e
+#define mmSPI_SHADER_USER_DATA_PS_3 0x2c0f
+#define mmSPI_SHADER_USER_DATA_PS_4 0x2c10
+#define mmSPI_SHADER_USER_DATA_PS_5 0x2c11
+#define mmSPI_SHADER_USER_DATA_PS_6 0x2c12
+#define mmSPI_SHADER_USER_DATA_PS_7 0x2c13
+#define mmSPI_SHADER_USER_DATA_PS_8 0x2c14
+#define mmSPI_SHADER_USER_DATA_PS_9 0x2c15
+#define mmSPI_SHADER_USER_DATA_PS_10 0x2c16
+#define mmSPI_SHADER_USER_DATA_PS_11 0x2c17
+#define mmSPI_SHADER_USER_DATA_PS_12 0x2c18
+#define mmSPI_SHADER_USER_DATA_PS_13 0x2c19
+#define mmSPI_SHADER_USER_DATA_PS_14 0x2c1a
+#define mmSPI_SHADER_USER_DATA_PS_15 0x2c1b
+#define mmSPI_SHADER_TBA_LO_VS 0x2c40
+#define mmSPI_SHADER_TBA_HI_VS 0x2c41
+#define mmSPI_SHADER_TMA_LO_VS 0x2c42
+#define mmSPI_SHADER_TMA_HI_VS 0x2c43
+#define mmSPI_SHADER_PGM_LO_VS 0x2c48
+#define mmSPI_SHADER_PGM_HI_VS 0x2c49
+#define mmSPI_SHADER_PGM_RSRC1_VS 0x2c4a
+#define mmSPI_SHADER_PGM_RSRC2_VS 0x2c4b
+#define mmSPI_SHADER_PGM_RSRC3_VS 0x2c46
+#define mmSPI_SHADER_LATE_ALLOC_VS 0x2c47
+#define mmSPI_SHADER_USER_DATA_VS_0 0x2c4c
+#define mmSPI_SHADER_USER_DATA_VS_1 0x2c4d
+#define mmSPI_SHADER_USER_DATA_VS_2 0x2c4e
+#define mmSPI_SHADER_USER_DATA_VS_3 0x2c4f
+#define mmSPI_SHADER_USER_DATA_VS_4 0x2c50
+#define mmSPI_SHADER_USER_DATA_VS_5 0x2c51
+#define mmSPI_SHADER_USER_DATA_VS_6 0x2c52
+#define mmSPI_SHADER_USER_DATA_VS_7 0x2c53
+#define mmSPI_SHADER_USER_DATA_VS_8 0x2c54
+#define mmSPI_SHADER_USER_DATA_VS_9 0x2c55
+#define mmSPI_SHADER_USER_DATA_VS_10 0x2c56
+#define mmSPI_SHADER_USER_DATA_VS_11 0x2c57
+#define mmSPI_SHADER_USER_DATA_VS_12 0x2c58
+#define mmSPI_SHADER_USER_DATA_VS_13 0x2c59
+#define mmSPI_SHADER_USER_DATA_VS_14 0x2c5a
+#define mmSPI_SHADER_USER_DATA_VS_15 0x2c5b
+#define mmSPI_SHADER_PGM_RSRC2_ES_VS 0x2c7c
+#define mmSPI_SHADER_PGM_RSRC2_LS_VS 0x2c7d
+#define mmSPI_SHADER_TBA_LO_GS 0x2c80
+#define mmSPI_SHADER_TBA_HI_GS 0x2c81
+#define mmSPI_SHADER_TMA_LO_GS 0x2c82
+#define mmSPI_SHADER_TMA_HI_GS 0x2c83
+#define mmSPI_SHADER_PGM_LO_GS 0x2c88
+#define mmSPI_SHADER_PGM_HI_GS 0x2c89
+#define mmSPI_SHADER_PGM_RSRC1_GS 0x2c8a
+#define mmSPI_SHADER_PGM_RSRC2_GS 0x2c8b
+#define mmSPI_SHADER_PGM_RSRC3_GS 0x2c87
+#define mmSPI_SHADER_USER_DATA_GS_0 0x2c8c
+#define mmSPI_SHADER_USER_DATA_GS_1 0x2c8d
+#define mmSPI_SHADER_USER_DATA_GS_2 0x2c8e
+#define mmSPI_SHADER_USER_DATA_GS_3 0x2c8f
+#define mmSPI_SHADER_USER_DATA_GS_4 0x2c90
+#define mmSPI_SHADER_USER_DATA_GS_5 0x2c91
+#define mmSPI_SHADER_USER_DATA_GS_6 0x2c92
+#define mmSPI_SHADER_USER_DATA_GS_7 0x2c93
+#define mmSPI_SHADER_USER_DATA_GS_8 0x2c94
+#define mmSPI_SHADER_USER_DATA_GS_9 0x2c95
+#define mmSPI_SHADER_USER_DATA_GS_10 0x2c96
+#define mmSPI_SHADER_USER_DATA_GS_11 0x2c97
+#define mmSPI_SHADER_USER_DATA_GS_12 0x2c98
+#define mmSPI_SHADER_USER_DATA_GS_13 0x2c99
+#define mmSPI_SHADER_USER_DATA_GS_14 0x2c9a
+#define mmSPI_SHADER_USER_DATA_GS_15 0x2c9b
+#define mmSPI_SHADER_PGM_RSRC2_ES_GS 0x2cbc
+#define mmSPI_SHADER_TBA_LO_ES 0x2cc0
+#define mmSPI_SHADER_TBA_HI_ES 0x2cc1
+#define mmSPI_SHADER_TMA_LO_ES 0x2cc2
+#define mmSPI_SHADER_TMA_HI_ES 0x2cc3
+#define mmSPI_SHADER_PGM_LO_ES 0x2cc8
+#define mmSPI_SHADER_PGM_HI_ES 0x2cc9
+#define mmSPI_SHADER_PGM_RSRC1_ES 0x2cca
+#define mmSPI_SHADER_PGM_RSRC2_ES 0x2ccb
+#define mmSPI_SHADER_PGM_RSRC3_ES 0x2cc7
+#define mmSPI_SHADER_USER_DATA_ES_0 0x2ccc
+#define mmSPI_SHADER_USER_DATA_ES_1 0x2ccd
+#define mmSPI_SHADER_USER_DATA_ES_2 0x2cce
+#define mmSPI_SHADER_USER_DATA_ES_3 0x2ccf
+#define mmSPI_SHADER_USER_DATA_ES_4 0x2cd0
+#define mmSPI_SHADER_USER_DATA_ES_5 0x2cd1
+#define mmSPI_SHADER_USER_DATA_ES_6 0x2cd2
+#define mmSPI_SHADER_USER_DATA_ES_7 0x2cd3
+#define mmSPI_SHADER_USER_DATA_ES_8 0x2cd4
+#define mmSPI_SHADER_USER_DATA_ES_9 0x2cd5
+#define mmSPI_SHADER_USER_DATA_ES_10 0x2cd6
+#define mmSPI_SHADER_USER_DATA_ES_11 0x2cd7
+#define mmSPI_SHADER_USER_DATA_ES_12 0x2cd8
+#define mmSPI_SHADER_USER_DATA_ES_13 0x2cd9
+#define mmSPI_SHADER_USER_DATA_ES_14 0x2cda
+#define mmSPI_SHADER_USER_DATA_ES_15 0x2cdb
+#define mmSPI_SHADER_PGM_RSRC2_LS_ES 0x2cfd
+#define mmSPI_SHADER_TBA_LO_HS 0x2d00
+#define mmSPI_SHADER_TBA_HI_HS 0x2d01
+#define mmSPI_SHADER_TMA_LO_HS 0x2d02
+#define mmSPI_SHADER_TMA_HI_HS 0x2d03
+#define mmSPI_SHADER_PGM_LO_HS 0x2d08
+#define mmSPI_SHADER_PGM_HI_HS 0x2d09
+#define mmSPI_SHADER_PGM_RSRC1_HS 0x2d0a
+#define mmSPI_SHADER_PGM_RSRC2_HS 0x2d0b
+#define mmSPI_SHADER_PGM_RSRC3_HS 0x2d07
+#define mmSPI_SHADER_USER_DATA_HS_0 0x2d0c
+#define mmSPI_SHADER_USER_DATA_HS_1 0x2d0d
+#define mmSPI_SHADER_USER_DATA_HS_2 0x2d0e
+#define mmSPI_SHADER_USER_DATA_HS_3 0x2d0f
+#define mmSPI_SHADER_USER_DATA_HS_4 0x2d10
+#define mmSPI_SHADER_USER_DATA_HS_5 0x2d11
+#define mmSPI_SHADER_USER_DATA_HS_6 0x2d12
+#define mmSPI_SHADER_USER_DATA_HS_7 0x2d13
+#define mmSPI_SHADER_USER_DATA_HS_8 0x2d14
+#define mmSPI_SHADER_USER_DATA_HS_9 0x2d15
+#define mmSPI_SHADER_USER_DATA_HS_10 0x2d16
+#define mmSPI_SHADER_USER_DATA_HS_11 0x2d17
+#define mmSPI_SHADER_USER_DATA_HS_12 0x2d18
+#define mmSPI_SHADER_USER_DATA_HS_13 0x2d19
+#define mmSPI_SHADER_USER_DATA_HS_14 0x2d1a
+#define mmSPI_SHADER_USER_DATA_HS_15 0x2d1b
+#define mmSPI_SHADER_PGM_RSRC2_LS_HS 0x2d3d
+#define mmSPI_SHADER_TBA_LO_LS 0x2d40
+#define mmSPI_SHADER_TBA_HI_LS 0x2d41
+#define mmSPI_SHADER_TMA_LO_LS 0x2d42
+#define mmSPI_SHADER_TMA_HI_LS 0x2d43
+#define mmSPI_SHADER_PGM_LO_LS 0x2d48
+#define mmSPI_SHADER_PGM_HI_LS 0x2d49
+#define mmSPI_SHADER_PGM_RSRC1_LS 0x2d4a
+#define mmSPI_SHADER_PGM_RSRC2_LS 0x2d4b
+#define mmSPI_SHADER_PGM_RSRC3_LS 0x2d47
+#define mmSPI_SHADER_USER_DATA_LS_0 0x2d4c
+#define mmSPI_SHADER_USER_DATA_LS_1 0x2d4d
+#define mmSPI_SHADER_USER_DATA_LS_2 0x2d4e
+#define mmSPI_SHADER_USER_DATA_LS_3 0x2d4f
+#define mmSPI_SHADER_USER_DATA_LS_4 0x2d50
+#define mmSPI_SHADER_USER_DATA_LS_5 0x2d51
+#define mmSPI_SHADER_USER_DATA_LS_6 0x2d52
+#define mmSPI_SHADER_USER_DATA_LS_7 0x2d53
+#define mmSPI_SHADER_USER_DATA_LS_8 0x2d54
+#define mmSPI_SHADER_USER_DATA_LS_9 0x2d55
+#define mmSPI_SHADER_USER_DATA_LS_10 0x2d56
+#define mmSPI_SHADER_USER_DATA_LS_11 0x2d57
+#define mmSPI_SHADER_USER_DATA_LS_12 0x2d58
+#define mmSPI_SHADER_USER_DATA_LS_13 0x2d59
+#define mmSPI_SHADER_USER_DATA_LS_14 0x2d5a
+#define mmSPI_SHADER_USER_DATA_LS_15 0x2d5b
+#define mmSQ_CONFIG 0x2300
+#define mmSQC_CONFIG 0x2301
+#define mmSQC_CACHES 0xc348
+#define mmSQ_RANDOM_WAVE_PRI 0x2303
+#define mmSQ_REG_CREDITS 0x2304
+#define mmSQ_FIFO_SIZES 0x2305
+#define mmSQ_INTERRUPT_AUTO_MASK 0x2314
+#define mmSQ_INTERRUPT_MSG_CTRL 0x2315
+#define mmSQ_PERFCOUNTER_CTRL 0xd9e0
+#define mmSQ_PERFCOUNTER_MASK 0xd9e1
+#define mmSQ_PERFCOUNTER_CTRL2 0xd9e2
+#define mmCC_SQC_BANK_DISABLE 0x2307
+#define mmUSER_SQC_BANK_DISABLE 0x2308
+#define mmSQ_PERFCOUNTER0_LO 0xd1c0
+#define mmSQ_PERFCOUNTER1_LO 0xd1c2
+#define mmSQ_PERFCOUNTER2_LO 0xd1c4
+#define mmSQ_PERFCOUNTER3_LO 0xd1c6
+#define mmSQ_PERFCOUNTER4_LO 0xd1c8
+#define mmSQ_PERFCOUNTER5_LO 0xd1ca
+#define mmSQ_PERFCOUNTER6_LO 0xd1cc
+#define mmSQ_PERFCOUNTER7_LO 0xd1ce
+#define mmSQ_PERFCOUNTER8_LO 0xd1d0
+#define mmSQ_PERFCOUNTER9_LO 0xd1d2
+#define mmSQ_PERFCOUNTER10_LO 0xd1d4
+#define mmSQ_PERFCOUNTER11_LO 0xd1d6
+#define mmSQ_PERFCOUNTER12_LO 0xd1d8
+#define mmSQ_PERFCOUNTER13_LO 0xd1da
+#define mmSQ_PERFCOUNTER14_LO 0xd1dc
+#define mmSQ_PERFCOUNTER15_LO 0xd1de
+#define mmSQ_PERFCOUNTER0_HI 0xd1c1
+#define mmSQ_PERFCOUNTER1_HI 0xd1c3
+#define mmSQ_PERFCOUNTER2_HI 0xd1c5
+#define mmSQ_PERFCOUNTER3_HI 0xd1c7
+#define mmSQ_PERFCOUNTER4_HI 0xd1c9
+#define mmSQ_PERFCOUNTER5_HI 0xd1cb
+#define mmSQ_PERFCOUNTER6_HI 0xd1cd
+#define mmSQ_PERFCOUNTER7_HI 0xd1cf
+#define mmSQ_PERFCOUNTER8_HI 0xd1d1
+#define mmSQ_PERFCOUNTER9_HI 0xd1d3
+#define mmSQ_PERFCOUNTER10_HI 0xd1d5
+#define mmSQ_PERFCOUNTER11_HI 0xd1d7
+#define mmSQ_PERFCOUNTER12_HI 0xd1d9
+#define mmSQ_PERFCOUNTER13_HI 0xd1db
+#define mmSQ_PERFCOUNTER14_HI 0xd1dd
+#define mmSQ_PERFCOUNTER15_HI 0xd1df
+#define mmSQ_PERFCOUNTER0_SELECT 0xd9c0
+#define mmSQ_PERFCOUNTER1_SELECT 0xd9c1
+#define mmSQ_PERFCOUNTER2_SELECT 0xd9c2
+#define mmSQ_PERFCOUNTER3_SELECT 0xd9c3
+#define mmSQ_PERFCOUNTER4_SELECT 0xd9c4
+#define mmSQ_PERFCOUNTER5_SELECT 0xd9c5
+#define mmSQ_PERFCOUNTER6_SELECT 0xd9c6
+#define mmSQ_PERFCOUNTER7_SELECT 0xd9c7
+#define mmSQ_PERFCOUNTER8_SELECT 0xd9c8
+#define mmSQ_PERFCOUNTER9_SELECT 0xd9c9
+#define mmSQ_PERFCOUNTER10_SELECT 0xd9ca
+#define mmSQ_PERFCOUNTER11_SELECT 0xd9cb
+#define mmSQ_PERFCOUNTER12_SELECT 0xd9cc
+#define mmSQ_PERFCOUNTER13_SELECT 0xd9cd
+#define mmSQ_PERFCOUNTER14_SELECT 0xd9ce
+#define mmSQ_PERFCOUNTER15_SELECT 0xd9cf
+#define mmCGTT_SQ_CLK_CTRL 0xf08c
+#define mmCGTT_SQG_CLK_CTRL 0xf08d
+#define mmSQ_ALU_CLK_CTRL 0xf08e
+#define mmSQ_TEX_CLK_CTRL 0xf08f
+#define mmSQ_LDS_CLK_CTRL 0xf090
+#define mmSQ_POWER_THROTTLE 0xf091
+#define mmSQ_POWER_THROTTLE2 0xf092
+#define mmSQ_TIME_HI 0x237c
+#define mmSQ_TIME_LO 0x237d
+#define mmSQ_THREAD_TRACE_BASE 0x2380
+#define mmSQ_THREAD_TRACE_BASE2 0x2385
+#define mmSQ_THREAD_TRACE_SIZE 0x2381
+#define mmSQ_THREAD_TRACE_MASK 0x2382
+#define mmSQ_THREAD_TRACE_USERDATA_0 0xc340
+#define mmSQ_THREAD_TRACE_USERDATA_1 0xc341
+#define mmSQ_THREAD_TRACE_USERDATA_2 0xc342
+#define mmSQ_THREAD_TRACE_USERDATA_3 0xc343
+#define mmSQ_THREAD_TRACE_MODE 0x238e
+#define mmSQ_THREAD_TRACE_CTRL 0x238f
+#define mmSQ_THREAD_TRACE_TOKEN_MASK 0x2383
+#define mmSQ_THREAD_TRACE_TOKEN_MASK2 0x2386
+#define mmSQ_THREAD_TRACE_PERF_MASK 0x2384
+#define mmSQ_THREAD_TRACE_WPTR 0x238c
+#define mmSQ_THREAD_TRACE_STATUS 0x238d
+#define mmSQ_THREAD_TRACE_CNTR 0x2390
+#define mmSQ_THREAD_TRACE_HIWATER 0x2392
+#define mmSQ_LB_CTR_CTRL 0x2398
+#define mmSQ_LB_DATA_ALU_CYCLES 0x2399
+#define mmSQ_LB_DATA_TEX_CYCLES 0x239a
+#define mmSQ_LB_DATA_ALU_STALLS 0x239b
+#define mmSQ_LB_DATA_TEX_STALLS 0x239c
+#define mmSQC_SECDED_CNT 0x23a0
+#define mmSQ_SEC_CNT 0x23a1
+#define mmSQ_DED_CNT 0x23a2
+#define mmSQ_DED_INFO 0x23a3
+#define mmSQ_BUF_RSRC_WORD0 0x23c0
+#define mmSQ_BUF_RSRC_WORD1 0x23c1
+#define mmSQ_BUF_RSRC_WORD2 0x23c2
+#define mmSQ_BUF_RSRC_WORD3 0x23c3
+#define mmSQ_IMG_RSRC_WORD0 0x23c4
+#define mmSQ_IMG_RSRC_WORD1 0x23c5
+#define mmSQ_IMG_RSRC_WORD2 0x23c6
+#define mmSQ_IMG_RSRC_WORD3 0x23c7
+#define mmSQ_IMG_RSRC_WORD4 0x23c8
+#define mmSQ_IMG_RSRC_WORD5 0x23c9
+#define mmSQ_IMG_RSRC_WORD6 0x23ca
+#define mmSQ_IMG_RSRC_WORD7 0x23cb
+#define mmSQ_IMG_SAMP_WORD0 0x23cc
+#define mmSQ_IMG_SAMP_WORD1 0x23cd
+#define mmSQ_IMG_SAMP_WORD2 0x23ce
+#define mmSQ_IMG_SAMP_WORD3 0x23cf
+#define mmSQ_FLAT_SCRATCH_WORD0 0x23d0
+#define mmSQ_FLAT_SCRATCH_WORD1 0x23d1
+#define mmSQ_IND_INDEX 0x2378
+#define mmSQ_IND_CMD 0x237a
+#define mmSQ_CMD 0x237b
+#define mmSQ_IND_DATA 0x2379
+#define mmSQ_REG_TIMESTAMP 0x2374
+#define mmSQ_CMD_TIMESTAMP 0x2375
+#define mmSQ_HV_VMID_CTRL 0xf840
+#define ixSQ_WAVE_INST_DW0 0x1a
+#define ixSQ_WAVE_INST_DW1 0x1b
+#define ixSQ_WAVE_PC_LO 0x18
+#define ixSQ_WAVE_PC_HI 0x19
+#define ixSQ_WAVE_IB_DBG0 0x1c
+#define ixSQ_WAVE_EXEC_LO 0x27e
+#define ixSQ_WAVE_EXEC_HI 0x27f
+#define ixSQ_WAVE_STATUS 0x12
+#define ixSQ_WAVE_MODE 0x11
+#define ixSQ_WAVE_TRAPSTS 0x13
+#define ixSQ_WAVE_HW_ID 0x14
+#define ixSQ_WAVE_GPR_ALLOC 0x15
+#define ixSQ_WAVE_LDS_ALLOC 0x16
+#define ixSQ_WAVE_IB_STS 0x17
+#define ixSQ_WAVE_M0 0x27c
+#define ixSQ_WAVE_TBA_LO 0x26c
+#define ixSQ_WAVE_TBA_HI 0x26d
+#define ixSQ_WAVE_TMA_LO 0x26e
+#define ixSQ_WAVE_TMA_HI 0x26f
+#define ixSQ_WAVE_TTMP0 0x270
+#define ixSQ_WAVE_TTMP1 0x271
+#define ixSQ_WAVE_TTMP2 0x272
+#define ixSQ_WAVE_TTMP3 0x273
+#define ixSQ_WAVE_TTMP4 0x274
+#define ixSQ_WAVE_TTMP5 0x275
+#define ixSQ_WAVE_TTMP6 0x276
+#define ixSQ_WAVE_TTMP7 0x277
+#define ixSQ_WAVE_TTMP8 0x278
+#define ixSQ_WAVE_TTMP9 0x279
+#define ixSQ_WAVE_TTMP10 0x27a
+#define ixSQ_WAVE_TTMP11 0x27b
+#define mmSQ_DEBUG_STS_GLOBAL 0x2309
+#define mmSQ_DEBUG_STS_GLOBAL2 0x2310
+#define mmSQ_DEBUG_STS_GLOBAL3 0x2311
+#define ixSQ_DEBUG_STS_LOCAL 0x8
+#define ixSQ_DEBUG_CTRL_LOCAL 0x9
+#define mmSH_MEM_BASES 0x230a
+#define mmSH_MEM_APE1_BASE 0x230b
+#define mmSH_MEM_APE1_LIMIT 0x230c
+#define mmSH_MEM_CONFIG 0x230d
+#define mmSQC_POLICY 0x230e
+#define mmSQC_VOLATILE 0x230f
+#define mmSQ_THREAD_TRACE_WORD_CMN 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_INST 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x23b1
+#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x23b1
+#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x23b1
+#define mmSQ_THREAD_TRACE_WORD_WAVE 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_MISC 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_EVENT 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x23b1
+#define ixSQ_INTERRUPT_WORD_CMN 0x20c0
+#define ixSQ_INTERRUPT_WORD_AUTO 0x20c0
+#define ixSQ_INTERRUPT_WORD_WAVE 0x20c0
+#define mmSQ_SOP2 0x237f
+#define mmSQ_VOP1 0x237f
+#define mmSQ_MTBUF_1 0x237f
+#define mmSQ_EXP_1 0x237f
+#define mmSQ_MUBUF_1 0x237f
+#define mmSQ_INST 0x237f
+#define mmSQ_EXP_0 0x237f
+#define mmSQ_MUBUF_0 0x237f
+#define mmSQ_VOP3_0 0x237f
+#define mmSQ_VOP2 0x237f
+#define mmSQ_MTBUF_0 0x237f
+#define mmSQ_SOPP 0x237f
+#define mmSQ_FLAT_0 0x237f
+#define mmSQ_VOP3_0_SDST_ENC 0x237f
+#define mmSQ_MIMG_1 0x237f
+#define mmSQ_SMRD 0x237f
+#define mmSQ_SOP1 0x237f
+#define mmSQ_SOPC 0x237f
+#define mmSQ_FLAT_1 0x237f
+#define mmSQ_DS_1 0x237f
+#define mmSQ_VOP3_1 0x237f
+#define mmSQ_MIMG_0 0x237f
+#define mmSQ_SOPK 0x237f
+#define mmSQ_DS_0 0x237f
+#define mmSQ_VOPC 0x237f
+#define mmSQ_VINTRP 0x237f
+#define mmCGTT_SX_CLK_CTRL0 0xf094
+#define mmCGTT_SX_CLK_CTRL1 0xf095
+#define mmCGTT_SX_CLK_CTRL2 0xf096
+#define mmCGTT_SX_CLK_CTRL3 0xf097
+#define mmCGTT_SX_CLK_CTRL4 0xf098
+#define mmSX_DEBUG_BUSY 0x2414
+#define mmSX_DEBUG_BUSY_2 0x2415
+#define mmSX_DEBUG_BUSY_3 0x2416
+#define mmSX_DEBUG_BUSY_4 0x2417
+#define mmSX_DEBUG_1 0x2418
+#define mmSX_PERFCOUNTER0_SELECT 0xda40
+#define mmSX_PERFCOUNTER1_SELECT 0xda41
+#define mmSX_PERFCOUNTER2_SELECT 0xda42
+#define mmSX_PERFCOUNTER3_SELECT 0xda43
+#define mmSX_PERFCOUNTER0_SELECT1 0xda44
+#define mmSX_PERFCOUNTER1_SELECT1 0xda45
+#define mmSX_PERFCOUNTER0_LO 0xd240
+#define mmSX_PERFCOUNTER0_HI 0xd241
+#define mmSX_PERFCOUNTER1_LO 0xd242
+#define mmSX_PERFCOUNTER1_HI 0xd243
+#define mmSX_PERFCOUNTER2_LO 0xd244
+#define mmSX_PERFCOUNTER2_HI 0xd245
+#define mmSX_PERFCOUNTER3_LO 0xd246
+#define mmSX_PERFCOUNTER3_HI 0xd247
+#define mmTCC_CTRL 0x2b80
+#define mmTCC_EDC_COUNTER 0x2b82
+#define mmTCC_REDUNDANCY 0x2b83
+#define mmTCC_CGTT_SCLK_CTRL 0xf0ac
+#define mmTCA_CGTT_SCLK_CTRL 0xf0ad
+#define mmTCS_CGTT_SCLK_CTRL 0xf0ae
+#define mmTCC_PERFCOUNTER0_SELECT 0xdb80
+#define mmTCC_PERFCOUNTER1_SELECT 0xdb82
+#define mmTCC_PERFCOUNTER0_SELECT1 0xdb81
+#define mmTCC_PERFCOUNTER1_SELECT1 0xdb83
+#define mmTCC_PERFCOUNTER2_SELECT 0xdb84
+#define mmTCC_PERFCOUNTER3_SELECT 0xdb85
+#define mmTCC_PERFCOUNTER0_LO 0xd380
+#define mmTCC_PERFCOUNTER1_LO 0xd382
+#define mmTCC_PERFCOUNTER2_LO 0xd384
+#define mmTCC_PERFCOUNTER3_LO 0xd386
+#define mmTCC_PERFCOUNTER0_HI 0xd381
+#define mmTCC_PERFCOUNTER1_HI 0xd383
+#define mmTCC_PERFCOUNTER2_HI 0xd385
+#define mmTCC_PERFCOUNTER3_HI 0xd387
+#define mmTCA_CTRL 0x2bc0
+#define mmTCA_PERFCOUNTER0_SELECT 0xdb90
+#define mmTCA_PERFCOUNTER1_SELECT 0xdb92
+#define mmTCA_PERFCOUNTER0_SELECT1 0xdb91
+#define mmTCA_PERFCOUNTER1_SELECT1 0xdb93
+#define mmTCA_PERFCOUNTER2_SELECT 0xdb94
+#define mmTCA_PERFCOUNTER3_SELECT 0xdb95
+#define mmTCA_PERFCOUNTER0_LO 0xd390
+#define mmTCA_PERFCOUNTER1_LO 0xd392
+#define mmTCA_PERFCOUNTER2_LO 0xd394
+#define mmTCA_PERFCOUNTER3_LO 0xd396
+#define mmTCA_PERFCOUNTER0_HI 0xd391
+#define mmTCA_PERFCOUNTER1_HI 0xd393
+#define mmTCA_PERFCOUNTER2_HI 0xd395
+#define mmTCA_PERFCOUNTER3_HI 0xd397
+#define mmTCS_CTRL 0x2be0
+#define mmTCS_PERFCOUNTER0_SELECT 0xdba0
+#define mmTCS_PERFCOUNTER0_SELECT1 0xdba1
+#define mmTCS_PERFCOUNTER1_SELECT 0xdba2
+#define mmTCS_PERFCOUNTER2_SELECT 0xdba3
+#define mmTCS_PERFCOUNTER3_SELECT 0xdba4
+#define mmTCS_PERFCOUNTER0_LO 0xd3a0
+#define mmTCS_PERFCOUNTER1_LO 0xd3a2
+#define mmTCS_PERFCOUNTER2_LO 0xd3a4
+#define mmTCS_PERFCOUNTER3_LO 0xd3a6
+#define mmTCS_PERFCOUNTER0_HI 0xd3a1
+#define mmTCS_PERFCOUNTER1_HI 0xd3a3
+#define mmTCS_PERFCOUNTER2_HI 0xd3a5
+#define mmTCS_PERFCOUNTER3_HI 0xd3a7
+#define mmTA_BC_BASE_ADDR 0xa020
+#define mmTA_BC_BASE_ADDR_HI 0xa021
+#define mmTD_CNTL 0x2525
+#define mmTD_STATUS 0x2526
+#define mmTD_DEBUG_INDEX 0x2528
+#define mmTD_DEBUG_DATA 0x2529
+#define mmTD_PERFCOUNTER0_SELECT 0xdb00
+#define mmTD_PERFCOUNTER1_SELECT 0xdb02
+#define mmTD_PERFCOUNTER0_SELECT1 0xdb01
+#define mmTD_PERFCOUNTER0_LO 0xd300
+#define mmTD_PERFCOUNTER1_LO 0xd302
+#define mmTD_PERFCOUNTER0_HI 0xd301
+#define mmTD_PERFCOUNTER1_HI 0xd303
+#define mmTD_SCRATCH 0x2533
+#define mmTA_CNTL 0x2541
+#define mmTA_CNTL_AUX 0x2542
+#define mmTA_RESERVED_010C 0x2543
+#define mmTA_CS_BC_BASE_ADDR 0xc380
+#define mmTA_CS_BC_BASE_ADDR_HI 0xc381
+#define mmTA_STATUS 0x2548
+#define mmTA_DEBUG_INDEX 0x254c
+#define mmTA_DEBUG_DATA 0x254d
+#define mmTA_PERFCOUNTER0_SELECT 0xdac0
+#define mmTA_PERFCOUNTER1_SELECT 0xdac2
+#define mmTA_PERFCOUNTER0_SELECT1 0xdac1
+#define mmTA_PERFCOUNTER0_LO 0xd2c0
+#define mmTA_PERFCOUNTER1_LO 0xd2c2
+#define mmTA_PERFCOUNTER0_HI 0xd2c1
+#define mmTA_PERFCOUNTER1_HI 0xd2c3
+#define mmTA_SCRATCH 0x2564
+#define mmSH_HIDDEN_PRIVATE_BASE_VMID 0x2580
+#define mmSH_STATIC_MEM_CONFIG 0x2581
+#define mmTCP_INVALIDATE 0x2b00
+#define mmTCP_STATUS 0x2b01
+#define mmTCP_CNTL 0x2b02
+#define mmTCP_CHAN_STEER_LO 0x2b03
+#define mmTCP_CHAN_STEER_HI 0x2b04
+#define mmTCP_ADDR_CONFIG 0x2b05
+#define mmTCP_CREDIT 0x2b06
+#define mmTCP_PERFCOUNTER0_SELECT 0xdb40
+#define mmTCP_PERFCOUNTER1_SELECT 0xdb42
+#define mmTCP_PERFCOUNTER0_SELECT1 0xdb41
+#define mmTCP_PERFCOUNTER1_SELECT1 0xdb43
+#define mmTCP_PERFCOUNTER2_SELECT 0xdb44
+#define mmTCP_PERFCOUNTER3_SELECT 0xdb45
+#define mmTCP_PERFCOUNTER0_LO 0xd340
+#define mmTCP_PERFCOUNTER1_LO 0xd342
+#define mmTCP_PERFCOUNTER2_LO 0xd344
+#define mmTCP_PERFCOUNTER3_LO 0xd346
+#define mmTCP_PERFCOUNTER0_HI 0xd341
+#define mmTCP_PERFCOUNTER1_HI 0xd343
+#define mmTCP_PERFCOUNTER2_HI 0xd345
+#define mmTCP_PERFCOUNTER3_HI 0xd347
+#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x2b16
+#define mmTCP_EDC_COUNTER 0x2b17
+#define mmTC_CFG_L1_LOAD_POLICY0 0x2b1a
+#define mmTC_CFG_L1_LOAD_POLICY1 0x2b1b
+#define mmTC_CFG_L1_STORE_POLICY 0x2b1c
+#define mmTC_CFG_L2_LOAD_POLICY0 0x2b1d
+#define mmTC_CFG_L2_LOAD_POLICY1 0x2b1e
+#define mmTC_CFG_L2_STORE_POLICY0 0x2b1f
+#define mmTC_CFG_L2_STORE_POLICY1 0x2b20
+#define mmTC_CFG_L2_ATOMIC_POLICY 0x2b21
+#define mmTC_CFG_L1_VOLATILE 0x2b22
+#define mmTC_CFG_L2_VOLATILE 0x2b23
+#define mmTCP_WATCH0_ADDR_H 0x32a0
+#define mmTCP_WATCH1_ADDR_H 0x32a3
+#define mmTCP_WATCH2_ADDR_H 0x32a6
+#define mmTCP_WATCH3_ADDR_H 0x32a9
+#define mmTCP_WATCH0_ADDR_L 0x32a1
+#define mmTCP_WATCH1_ADDR_L 0x32a4
+#define mmTCP_WATCH2_ADDR_L 0x32a7
+#define mmTCP_WATCH3_ADDR_L 0x32aa
+#define mmTCP_WATCH0_CNTL 0x32a2
+#define mmTCP_WATCH1_CNTL 0x32a5
+#define mmTCP_WATCH2_CNTL 0x32a8
+#define mmTCP_WATCH3_CNTL 0x32ab
+#define mmTD_CGTT_CTRL 0xf09c
+#define mmTA_CGTT_CTRL 0xf09d
+#define mmCGTT_TCP_CLK_CTRL 0xf09e
+#define mmCGTT_TCI_CLK_CTRL 0xf09f
+#define mmTCI_STATUS 0x2b61
+#define mmTCI_CNTL_1 0x2b62
+#define mmTCI_CNTL_2 0x2b63
+#define mmGDS_CONFIG 0x25c0
+#define mmGDS_CNTL_STATUS 0x25c1
+#define mmGDS_ENHANCE2 0x25c2
+#define mmGDS_PROTECTION_FAULT 0x25c3
+#define mmGDS_VM_PROTECTION_FAULT 0x25c4
+#define mmGDS_SECDED_CNT 0x25c5
+#define mmGDS_GRBM_SECDED_CNT 0x25c6
+#define mmGDS_OA_DED 0x25c7
+#define mmGDS_DEBUG_CNTL 0x25c8
+#define mmGDS_DEBUG_DATA 0x25c9
+#define mmCGTT_GDS_CLK_CTRL 0xf0a0
+#define mmGDS_RD_ADDR 0xc400
+#define mmGDS_RD_DATA 0xc401
+#define mmGDS_RD_BURST_ADDR 0xc402
+#define mmGDS_RD_BURST_COUNT 0xc403
+#define mmGDS_RD_BURST_DATA 0xc404
+#define mmGDS_WR_ADDR 0xc405
+#define mmGDS_WR_DATA 0xc406
+#define mmGDS_WR_BURST_ADDR 0xc407
+#define mmGDS_WR_BURST_DATA 0xc408
+#define mmGDS_WRITE_COMPLETE 0xc409
+#define mmGDS_ATOM_CNTL 0xc40a
+#define mmGDS_ATOM_COMPLETE 0xc40b
+#define mmGDS_ATOM_BASE 0xc40c
+#define mmGDS_ATOM_SIZE 0xc40d
+#define mmGDS_ATOM_OFFSET0 0xc40e
+#define mmGDS_ATOM_OFFSET1 0xc40f
+#define mmGDS_ATOM_DST 0xc410
+#define mmGDS_ATOM_OP 0xc411
+#define mmGDS_ATOM_SRC0 0xc412
+#define mmGDS_ATOM_SRC0_U 0xc413
+#define mmGDS_ATOM_SRC1 0xc414
+#define mmGDS_ATOM_SRC1_U 0xc415
+#define mmGDS_ATOM_READ0 0xc416
+#define mmGDS_ATOM_READ0_U 0xc417
+#define mmGDS_ATOM_READ1 0xc418
+#define mmGDS_ATOM_READ1_U 0xc419
+#define mmGDS_GWS_RESOURCE_CNTL 0xc41a
+#define mmGDS_GWS_RESOURCE 0xc41b
+#define mmGDS_GWS_RESOURCE_CNT 0xc41c
+#define mmGDS_OA_CNTL 0xc41d
+#define mmGDS_OA_COUNTER 0xc41e
+#define mmGDS_OA_ADDRESS 0xc41f
+#define mmGDS_OA_INCDEC 0xc420
+#define mmGDS_OA_RING_SIZE 0xc421
+#define ixGDS_DEBUG_REG0 0x0
+#define ixGDS_DEBUG_REG1 0x1
+#define ixGDS_DEBUG_REG2 0x2
+#define ixGDS_DEBUG_REG3 0x3
+#define ixGDS_DEBUG_REG4 0x4
+#define ixGDS_DEBUG_REG5 0x5
+#define ixGDS_DEBUG_REG6 0x6
+#define mmGDS_PERFCOUNTER0_SELECT 0xda80
+#define mmGDS_PERFCOUNTER1_SELECT 0xda81
+#define mmGDS_PERFCOUNTER2_SELECT 0xda82
+#define mmGDS_PERFCOUNTER3_SELECT 0xda83
+#define mmGDS_PERFCOUNTER0_LO 0xd280
+#define mmGDS_PERFCOUNTER1_LO 0xd282
+#define mmGDS_PERFCOUNTER2_LO 0xd284
+#define mmGDS_PERFCOUNTER3_LO 0xd286
+#define mmGDS_PERFCOUNTER0_HI 0xd281
+#define mmGDS_PERFCOUNTER1_HI 0xd283
+#define mmGDS_PERFCOUNTER2_HI 0xd285
+#define mmGDS_PERFCOUNTER3_HI 0xd287
+#define mmGDS_PERFCOUNTER0_SELECT1 0xda84
+#define mmGDS_VMID0_BASE 0x3300
+#define mmGDS_VMID1_BASE 0x3302
+#define mmGDS_VMID2_BASE 0x3304
+#define mmGDS_VMID3_BASE 0x3306
+#define mmGDS_VMID4_BASE 0x3308
+#define mmGDS_VMID5_BASE 0x330a
+#define mmGDS_VMID6_BASE 0x330c
+#define mmGDS_VMID7_BASE 0x330e
+#define mmGDS_VMID8_BASE 0x3310
+#define mmGDS_VMID9_BASE 0x3312
+#define mmGDS_VMID10_BASE 0x3314
+#define mmGDS_VMID11_BASE 0x3316
+#define mmGDS_VMID12_BASE 0x3318
+#define mmGDS_VMID13_BASE 0x331a
+#define mmGDS_VMID14_BASE 0x331c
+#define mmGDS_VMID15_BASE 0x331e
+#define mmGDS_VMID0_SIZE 0x3301
+#define mmGDS_VMID1_SIZE 0x3303
+#define mmGDS_VMID2_SIZE 0x3305
+#define mmGDS_VMID3_SIZE 0x3307
+#define mmGDS_VMID4_SIZE 0x3309
+#define mmGDS_VMID5_SIZE 0x330b
+#define mmGDS_VMID6_SIZE 0x330d
+#define mmGDS_VMID7_SIZE 0x330f
+#define mmGDS_VMID8_SIZE 0x3311
+#define mmGDS_VMID9_SIZE 0x3313
+#define mmGDS_VMID10_SIZE 0x3315
+#define mmGDS_VMID11_SIZE 0x3317
+#define mmGDS_VMID12_SIZE 0x3319
+#define mmGDS_VMID13_SIZE 0x331b
+#define mmGDS_VMID14_SIZE 0x331d
+#define mmGDS_VMID15_SIZE 0x331f
+#define mmGDS_GWS_VMID0 0x3320
+#define mmGDS_GWS_VMID1 0x3321
+#define mmGDS_GWS_VMID2 0x3322
+#define mmGDS_GWS_VMID3 0x3323
+#define mmGDS_GWS_VMID4 0x3324
+#define mmGDS_GWS_VMID5 0x3325
+#define mmGDS_GWS_VMID6 0x3326
+#define mmGDS_GWS_VMID7 0x3327
+#define mmGDS_GWS_VMID8 0x3328
+#define mmGDS_GWS_VMID9 0x3329
+#define mmGDS_GWS_VMID10 0x332a
+#define mmGDS_GWS_VMID11 0x332b
+#define mmGDS_GWS_VMID12 0x332c
+#define mmGDS_GWS_VMID13 0x332d
+#define mmGDS_GWS_VMID14 0x332e
+#define mmGDS_GWS_VMID15 0x332f
+#define mmGDS_OA_VMID0 0x3330
+#define mmGDS_OA_VMID1 0x3331
+#define mmGDS_OA_VMID2 0x3332
+#define mmGDS_OA_VMID3 0x3333
+#define mmGDS_OA_VMID4 0x3334
+#define mmGDS_OA_VMID5 0x3335
+#define mmGDS_OA_VMID6 0x3336
+#define mmGDS_OA_VMID7 0x3337
+#define mmGDS_OA_VMID8 0x3338
+#define mmGDS_OA_VMID9 0x3339
+#define mmGDS_OA_VMID10 0x333a
+#define mmGDS_OA_VMID11 0x333b
+#define mmGDS_OA_VMID12 0x333c
+#define mmGDS_OA_VMID13 0x333d
+#define mmGDS_OA_VMID14 0x333e
+#define mmGDS_OA_VMID15 0x333f
+#define mmGDS_GWS_RESET0 0x3344
+#define mmGDS_GWS_RESET1 0x3345
+#define mmGDS_GWS_RESOURCE_RESET 0x3346
+#define mmGDS_COMPUTE_MAX_WAVE_ID 0x3348
+#define mmGDS_OA_RESET_MASK 0x3349
+#define mmGDS_OA_RESET 0x334a
+#define mmGDS_ENHANCE 0x334b
+#define mmGDS_OA_CGPG_RESTORE 0x334c
+#define mmCS_COPY_STATE 0xa1f3
+#define mmGFX_COPY_STATE 0xa1f4
+#define mmVGT_DRAW_INITIATOR 0xa1fc
+#define mmVGT_EVENT_INITIATOR 0xa2a4
+#define mmVGT_EVENT_ADDRESS_REG 0xa1fe
+#define mmVGT_DMA_BASE_HI 0xa1f9
+#define mmVGT_DMA_BASE 0xa1fa
+#define mmVGT_DMA_INDEX_TYPE 0xa29f
+#define mmVGT_DMA_NUM_INSTANCES 0xa2a2
+#define mmIA_ENHANCE 0xa29c
+#define mmVGT_DMA_SIZE 0xa29d
+#define mmVGT_DMA_MAX_SIZE 0xa29e
+#define mmVGT_DMA_PRIMITIVE_TYPE 0x2271
+#define mmVGT_DMA_CONTROL 0x2272
+#define mmVGT_IMMED_DATA 0xa1fd
+#define mmVGT_INDEX_TYPE 0xc243
+#define mmVGT_NUM_INDICES 0xc24c
+#define mmVGT_NUM_INSTANCES 0xc24d
+#define mmVGT_PRIMITIVE_TYPE 0xc242
+#define mmVGT_PRIMITIVEID_EN 0xa2a1
+#define mmVGT_PRIMITIVEID_RESET 0xa2a3
+#define mmVGT_VTX_CNT_EN 0xa2ae
+#define mmVGT_REUSE_OFF 0xa2ad
+#define mmVGT_INSTANCE_STEP_RATE_0 0xa2a8
+#define mmVGT_INSTANCE_STEP_RATE_1 0xa2a9
+#define mmVGT_MAX_VTX_INDX 0xa100
+#define mmVGT_MIN_VTX_INDX 0xa101
+#define mmVGT_INDX_OFFSET 0xa102
+#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0xa316
+#define mmVGT_OUT_DEALLOC_CNTL 0xa317
+#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0xa103
+#define mmVGT_MULTI_PRIM_IB_RESET_EN 0xa2a5
+#define mmVGT_ENHANCE 0xa294
+#define mmVGT_OUTPUT_PATH_CNTL 0xa284
+#define mmVGT_HOS_CNTL 0xa285
+#define mmVGT_HOS_MAX_TESS_LEVEL 0xa286
+#define mmVGT_HOS_MIN_TESS_LEVEL 0xa287
+#define mmVGT_HOS_REUSE_DEPTH 0xa288
+#define mmVGT_GROUP_PRIM_TYPE 0xa289
+#define mmVGT_GROUP_FIRST_DECR 0xa28a
+#define mmVGT_GROUP_DECR 0xa28b
+#define mmVGT_GROUP_VECT_0_CNTL 0xa28c
+#define mmVGT_GROUP_VECT_1_CNTL 0xa28d
+#define mmVGT_GROUP_VECT_0_FMT_CNTL 0xa28e
+#define mmVGT_GROUP_VECT_1_FMT_CNTL 0xa28f
+#define mmVGT_VTX_VECT_EJECT_REG 0x222c
+#define mmVGT_DMA_DATA_FIFO_DEPTH 0x222d
+#define mmVGT_DMA_REQ_FIFO_DEPTH 0x222e
+#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x222f
+#define mmVGT_LAST_COPY_STATE 0x2230
+#define mmCC_GC_SHADER_ARRAY_CONFIG 0x226f
+#define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270
+#define mmVGT_GS_MODE 0xa290
+#define mmVGT_GS_ONCHIP_CNTL 0xa291
+#define mmVGT_GS_OUT_PRIM_TYPE 0xa29b
+#define mmVGT_CACHE_INVALIDATION 0x2231
+#define mmVGT_RESET_DEBUG 0x2232
+#define mmVGT_STRMOUT_DELAY 0x2233
+#define mmVGT_FIFO_DEPTHS 0x2234
+#define mmVGT_GS_PER_ES 0xa295
+#define mmVGT_ES_PER_GS 0xa296
+#define mmVGT_GS_PER_VS 0xa297
+#define mmVGT_GS_VERTEX_REUSE 0x2235
+#define mmVGT_MC_LAT_CNTL 0x2236
+#define mmIA_CNTL_STATUS 0x2237
+#define mmVGT_STRMOUT_CONFIG 0xa2e5
+#define mmVGT_STRMOUT_BUFFER_SIZE_0 0xa2b4
+#define mmVGT_STRMOUT_BUFFER_SIZE_1 0xa2b8
+#define mmVGT_STRMOUT_BUFFER_SIZE_2 0xa2bc
+#define mmVGT_STRMOUT_BUFFER_SIZE_3 0xa2c0
+#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0xa2b7
+#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0xa2bb
+#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0xa2bf
+#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0xa2c3
+#define mmVGT_STRMOUT_VTX_STRIDE_0 0xa2b5
+#define mmVGT_STRMOUT_VTX_STRIDE_1 0xa2b9
+#define mmVGT_STRMOUT_VTX_STRIDE_2 0xa2bd
+#define mmVGT_STRMOUT_VTX_STRIDE_3 0xa2c1
+#define mmVGT_STRMOUT_BUFFER_CONFIG 0xa2e6
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0xc244
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0xc245
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0xc246
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0xc247
+#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0xa2ca
+#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0xa2cb
+#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0xa2cc
+#define mmVGT_GS_MAX_VERT_OUT 0xa2ce
+#define mmIA_VMID_OVERRIDE 0x2260
+#define mmVGT_SHADER_STAGES_EN 0xa2d5
+#define mmVGT_DISPATCH_DRAW_INDEX 0xa2dd
+#define mmVGT_LS_HS_CONFIG 0xa2d6
+#define mmVGT_DMA_LS_HS_CONFIG 0x2273
+#define mmVGT_TF_PARAM 0xa2db
+#define mmVGT_TF_RING_SIZE 0xc24e
+#define mmVGT_SYS_CONFIG 0x2263
+#define mmVGT_HS_OFFCHIP_PARAM 0xc24f
+#define mmVGT_TF_MEMORY_BASE 0xc250
+#define mmVGT_GS_INSTANCE_CNT 0xa2e4
+#define mmIA_MULTI_VGT_PARAM 0xa2aa
+#define mmVGT_VS_MAX_WAVE_ID 0x2268
+#define mmVGT_ESGS_RING_SIZE 0xc240
+#define mmVGT_GSVS_RING_SIZE 0xc241
+#define mmVGT_GSVS_RING_OFFSET_1 0xa298
+#define mmVGT_GSVS_RING_OFFSET_2 0xa299
+#define mmVGT_GSVS_RING_OFFSET_3 0xa29a
+#define mmVGT_ESGS_RING_ITEMSIZE 0xa2ab
+#define mmVGT_GSVS_RING_ITEMSIZE 0xa2ac
+#define mmVGT_GS_VERT_ITEMSIZE 0xa2d7
+#define mmVGT_GS_VERT_ITEMSIZE_1 0xa2d8
+#define mmVGT_GS_VERT_ITEMSIZE_2 0xa2d9
+#define mmVGT_GS_VERT_ITEMSIZE_3 0xa2da
+#define mmWD_CNTL_STATUS 0x223f
+#define mmWD_ENHANCE 0xa2a0
+#define mmGFX_PIPE_CONTROL 0x226d
+#define mmGFX_PIPE_PRIORITY 0xf87f
+#define mmCGTT_VGT_CLK_CTRL 0xf084
+#define mmCGTT_IA_CLK_CTRL 0xf085
+#define mmCGTT_WD_CLK_CTRL 0xf086
+#define mmVGT_DEBUG_CNTL 0x2238
+#define mmVGT_DEBUG_DATA 0x2239
+#define mmIA_DEBUG_CNTL 0x223a
+#define mmIA_DEBUG_DATA 0x223b
+#define mmVGT_CNTL_STATUS 0x223c
+#define mmWD_DEBUG_CNTL 0x223d
+#define mmWD_DEBUG_DATA 0x223e
+#define mmCC_GC_PRIM_CONFIG 0x2240
+#define mmGC_USER_PRIM_CONFIG 0x2241
+#define ixWD_DEBUG_REG0 0x0
+#define ixWD_DEBUG_REG1 0x1
+#define ixWD_DEBUG_REG2 0x2
+#define ixWD_DEBUG_REG3 0x3
+#define ixWD_DEBUG_REG4 0x4
+#define ixWD_DEBUG_REG5 0x5
+#define ixIA_DEBUG_REG0 0x0
+#define ixIA_DEBUG_REG1 0x1
+#define ixIA_DEBUG_REG2 0x2
+#define ixIA_DEBUG_REG3 0x3
+#define ixIA_DEBUG_REG4 0x4
+#define ixIA_DEBUG_REG5 0x5
+#define ixIA_DEBUG_REG6 0x6
+#define ixIA_DEBUG_REG7 0x7
+#define ixIA_DEBUG_REG8 0x8
+#define ixIA_DEBUG_REG9 0x9
+#define ixVGT_DEBUG_REG0 0x0
+#define ixVGT_DEBUG_REG1 0x1
+#define ixVGT_DEBUG_REG2 0x1e
+#define ixVGT_DEBUG_REG3 0x1f
+#define ixVGT_DEBUG_REG4 0x20
+#define ixVGT_DEBUG_REG5 0x21
+#define ixVGT_DEBUG_REG6 0x22
+#define ixVGT_DEBUG_REG7 0x23
+#define ixVGT_DEBUG_REG8 0x8
+#define ixVGT_DEBUG_REG9 0x9
+#define ixVGT_DEBUG_REG10 0xa
+#define ixVGT_DEBUG_REG11 0xb
+#define ixVGT_DEBUG_REG12 0xc
+#define ixVGT_DEBUG_REG13 0xd
+#define ixVGT_DEBUG_REG14 0xe
+#define ixVGT_DEBUG_REG15 0xf
+#define ixVGT_DEBUG_REG16 0x10
+#define ixVGT_DEBUG_REG17 0x11
+#define ixVGT_DEBUG_REG18 0x7
+#define ixVGT_DEBUG_REG19 0x13
+#define ixVGT_DEBUG_REG20 0x14
+#define ixVGT_DEBUG_REG21 0x15
+#define ixVGT_DEBUG_REG22 0x16
+#define ixVGT_DEBUG_REG23 0x17
+#define ixVGT_DEBUG_REG24 0x18
+#define ixVGT_DEBUG_REG25 0x19
+#define ixVGT_DEBUG_REG26 0x24
+#define ixVGT_DEBUG_REG27 0x1b
+#define ixVGT_DEBUG_REG28 0x1c
+#define ixVGT_DEBUG_REG29 0x1d
+#define ixVGT_DEBUG_REG30 0x25
+#define ixVGT_DEBUG_REG31 0x26
+#define ixVGT_DEBUG_REG32 0x27
+#define ixVGT_DEBUG_REG33 0x28
+#define ixVGT_DEBUG_REG34 0x29
+#define ixVGT_DEBUG_REG35 0x2a
+#define mmVGT_PERFCOUNTER_SEID_MASK 0xd894
+#define mmVGT_PERFCOUNTER0_SELECT 0xd88c
+#define mmVGT_PERFCOUNTER1_SELECT 0xd88d
+#define mmVGT_PERFCOUNTER2_SELECT 0xd88e
+#define mmVGT_PERFCOUNTER3_SELECT 0xd88f
+#define mmVGT_PERFCOUNTER0_SELECT1 0xd890
+#define mmVGT_PERFCOUNTER1_SELECT1 0xd891
+#define mmVGT_PERFCOUNTER0_LO 0xd090
+#define mmVGT_PERFCOUNTER1_LO 0xd092
+#define mmVGT_PERFCOUNTER2_LO 0xd094
+#define mmVGT_PERFCOUNTER3_LO 0xd096
+#define mmVGT_PERFCOUNTER0_HI 0xd091
+#define mmVGT_PERFCOUNTER1_HI 0xd093
+#define mmVGT_PERFCOUNTER2_HI 0xd095
+#define mmVGT_PERFCOUNTER3_HI 0xd097
+#define mmIA_PERFCOUNTER0_SELECT 0xd884
+#define mmIA_PERFCOUNTER1_SELECT 0xd885
+#define mmIA_PERFCOUNTER2_SELECT 0xd886
+#define mmIA_PERFCOUNTER3_SELECT 0xd887
+#define mmIA_PERFCOUNTER0_SELECT1 0xd888
+#define mmIA_PERFCOUNTER0_LO 0xd088
+#define mmIA_PERFCOUNTER1_LO 0xd08a
+#define mmIA_PERFCOUNTER2_LO 0xd08c
+#define mmIA_PERFCOUNTER3_LO 0xd08e
+#define mmIA_PERFCOUNTER0_HI 0xd089
+#define mmIA_PERFCOUNTER1_HI 0xd08b
+#define mmIA_PERFCOUNTER2_HI 0xd08d
+#define mmIA_PERFCOUNTER3_HI 0xd08f
+#define mmWD_PERFCOUNTER0_SELECT 0xd880
+#define mmWD_PERFCOUNTER1_SELECT 0xd881
+#define mmWD_PERFCOUNTER2_SELECT 0xd882
+#define mmWD_PERFCOUNTER3_SELECT 0xd883
+#define mmWD_PERFCOUNTER0_LO 0xd080
+#define mmWD_PERFCOUNTER1_LO 0xd082
+#define mmWD_PERFCOUNTER2_LO 0xd084
+#define mmWD_PERFCOUNTER3_LO 0xd086
+#define mmWD_PERFCOUNTER0_HI 0xd081
+#define mmWD_PERFCOUNTER1_HI 0xd083
+#define mmWD_PERFCOUNTER2_HI 0xd085
+#define mmWD_PERFCOUNTER3_HI 0xd087
+#define mmDIDT_IND_INDEX 0x3280
+#define mmDIDT_IND_DATA 0x3281
+#define ixDIDT_SQ_CTRL0 0x0
+#define ixDIDT_SQ_CTRL1 0x1
+#define ixDIDT_SQ_CTRL2 0x2
+#define ixDIDT_SQ_WEIGHT0_3 0x10
+#define ixDIDT_SQ_WEIGHT4_7 0x11
+#define ixDIDT_SQ_WEIGHT8_11 0x12
+#define ixDIDT_DB_CTRL0 0x20
+#define ixDIDT_DB_CTRL1 0x21
+#define ixDIDT_DB_CTRL2 0x22
+#define ixDIDT_DB_WEIGHT0_3 0x30
+#define ixDIDT_DB_WEIGHT4_7 0x31
+#define ixDIDT_DB_WEIGHT8_11 0x32
+#define ixDIDT_TD_CTRL0 0x40
+#define ixDIDT_TD_CTRL1 0x41
+#define ixDIDT_TD_CTRL2 0x42
+#define ixDIDT_TD_WEIGHT0_3 0x50
+#define ixDIDT_TD_WEIGHT4_7 0x51
+#define ixDIDT_TD_WEIGHT8_11 0x52
+#define ixDIDT_TCP_CTRL0 0x60
+#define ixDIDT_TCP_CTRL1 0x61
+#define ixDIDT_TCP_CTRL2 0x62
+#define ixDIDT_TCP_WEIGHT0_3 0x70
+#define ixDIDT_TCP_WEIGHT4_7 0x71
+#define ixDIDT_TCP_WEIGHT8_11 0x72
+
+#endif /* GFX_7_2_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_enum.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_enum.h
new file mode 100644
index 000000000000..9d4347dd6125
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_enum.h
@@ -0,0 +1,6274 @@
+/*
+ * GFX_7_2 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GFX_7_2_ENUM_H
+#define GFX_7_2_ENUM_H
+
+typedef enum SurfaceNumber {
+ NUMBER_UNORM = 0x0,
+ NUMBER_SNORM = 0x1,
+ NUMBER_USCALED = 0x2,
+ NUMBER_SSCALED = 0x3,
+ NUMBER_UINT = 0x4,
+ NUMBER_SINT = 0x5,
+ NUMBER_SRGB = 0x6,
+ NUMBER_FLOAT = 0x7,
+} SurfaceNumber;
+typedef enum SurfaceSwap {
+ SWAP_STD = 0x0,
+ SWAP_ALT = 0x1,
+ SWAP_STD_REV = 0x2,
+ SWAP_ALT_REV = 0x3,
+} SurfaceSwap;
+typedef enum CBMode {
+ CB_DISABLE = 0x0,
+ CB_NORMAL = 0x1,
+ CB_ELIMINATE_FAST_CLEAR = 0x2,
+ CB_RESOLVE = 0x3,
+ CB_DECOMPRESS = 0x4,
+ CB_FMASK_DECOMPRESS = 0x5,
+} CBMode;
+typedef enum RoundMode {
+ ROUND_BY_HALF = 0x0,
+ ROUND_TRUNCATE = 0x1,
+} RoundMode;
+typedef enum SourceFormat {
+ EXPORT_4C_32BPC = 0x0,
+ EXPORT_4C_16BPC = 0x1,
+ EXPORT_2C_32BPC_GR = 0x2,
+ EXPORT_2C_32BPC_AR = 0x3,
+} SourceFormat;
+typedef enum BlendOp {
+ BLEND_ZERO = 0x0,
+ BLEND_ONE = 0x1,
+ BLEND_SRC_COLOR = 0x2,
+ BLEND_ONE_MINUS_SRC_COLOR = 0x3,
+ BLEND_SRC_ALPHA = 0x4,
+ BLEND_ONE_MINUS_SRC_ALPHA = 0x5,
+ BLEND_DST_ALPHA = 0x6,
+ BLEND_ONE_MINUS_DST_ALPHA = 0x7,
+ BLEND_DST_COLOR = 0x8,
+ BLEND_ONE_MINUS_DST_COLOR = 0x9,
+ BLEND_SRC_ALPHA_SATURATE = 0xa,
+ BLEND_BOTH_SRC_ALPHA = 0xb,
+ BLEND_BOTH_INV_SRC_ALPHA = 0xc,
+ BLEND_CONSTANT_COLOR = 0xd,
+ BLEND_ONE_MINUS_CONSTANT_COLOR = 0xe,
+ BLEND_SRC1_COLOR = 0xf,
+ BLEND_INV_SRC1_COLOR = 0x10,
+ BLEND_SRC1_ALPHA = 0x11,
+ BLEND_INV_SRC1_ALPHA = 0x12,
+ BLEND_CONSTANT_ALPHA = 0x13,
+ BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14,
+} BlendOp;
+typedef enum CombFunc {
+ COMB_DST_PLUS_SRC = 0x0,
+ COMB_SRC_MINUS_DST = 0x1,
+ COMB_MIN_DST_SRC = 0x2,
+ COMB_MAX_DST_SRC = 0x3,
+ COMB_DST_MINUS_SRC = 0x4,
+} CombFunc;
+typedef enum BlendOpt {
+ FORCE_OPT_AUTO = 0x0,
+ FORCE_OPT_DISABLE = 0x1,
+ FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x2,
+ FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x3,
+ FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x4,
+ FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x5,
+ FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x6,
+ FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x7,
+} BlendOpt;
+typedef enum CmaskCode {
+ CMASK_CLR00_F0 = 0x0,
+ CMASK_CLR00_F1 = 0x1,
+ CMASK_CLR00_F2 = 0x2,
+ CMASK_CLR00_FX = 0x3,
+ CMASK_CLR01_F0 = 0x4,
+ CMASK_CLR01_F1 = 0x5,
+ CMASK_CLR01_F2 = 0x6,
+ CMASK_CLR01_FX = 0x7,
+ CMASK_CLR10_F0 = 0x8,
+ CMASK_CLR10_F1 = 0x9,
+ CMASK_CLR10_F2 = 0xa,
+ CMASK_CLR10_FX = 0xb,
+ CMASK_CLR11_F0 = 0xc,
+ CMASK_CLR11_F1 = 0xd,
+ CMASK_CLR11_F2 = 0xe,
+ CMASK_CLR11_FX = 0xf,
+} CmaskCode;
+typedef enum CBPerfSel {
+ CB_PERF_SEL_NONE = 0x0,
+ CB_PERF_SEL_BUSY = 0x1,
+ CB_PERF_SEL_CORE_SCLK_VLD = 0x2,
+ CB_PERF_SEL_REG_SCLK0_VLD = 0x3,
+ CB_PERF_SEL_REG_SCLK1_VLD = 0x4,
+ CB_PERF_SEL_DRAWN_QUAD = 0x5,
+ CB_PERF_SEL_DRAWN_PIXEL = 0x6,
+ CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x7,
+ CB_PERF_SEL_DRAWN_TILE = 0x8,
+ CB_PERF_SEL_DB_CB_TILE_VALID_READY = 0x9,
+ CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0xa,
+ CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 0xb,
+ CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 0xc,
+ CB_PERF_SEL_CM_FC_TILE_VALID_READY = 0xd,
+ CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 0xe,
+ CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 0xf,
+ CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 0x10,
+ CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 0x11,
+ CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 0x12,
+ CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 0x13,
+ CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 0x14,
+ CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 0x15,
+ CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 0x16,
+ CB_PERF_SEL_LQUAD_NO_TILE = 0x17,
+ CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 0x18,
+ CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 0x19,
+ CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 0x1a,
+ CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 0x1b,
+ CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 0x1c,
+ CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x1d,
+ CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR= 0x1e,
+ CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 0x1f,
+ CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 0x20,
+ CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK= 0x21,
+ CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 0x22,
+ CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 0x23,
+ CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 0x24,
+ CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 0x25,
+ CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 0x26,
+ CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 0x27,
+ CB_PERF_SEL_FOP_IN_VALID_READY = 0x28,
+ CB_PERF_SEL_FOP_IN_VALID_READYB = 0x29,
+ CB_PERF_SEL_FOP_IN_VALIDB_READY = 0x2a,
+ CB_PERF_SEL_FOP_IN_VALIDB_READYB = 0x2b,
+ CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 0x2c,
+ CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 0x2d,
+ CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 0x2e,
+ CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 0x2f,
+ CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 0x30,
+ CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 0x31,
+ CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 0x32,
+ CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 0x33,
+ CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 0x34,
+ CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 0x35,
+ CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 0x36,
+ CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 0x37,
+ CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 0x38,
+ CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 0x39,
+ CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 0x3a,
+ CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 0x3b,
+ CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 0x3c,
+ CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 0x3d,
+ CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 0x3e,
+ CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 0x3f,
+ CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 0x40,
+ CB_PERF_SEL_CM_CACHE_HIT = 0x41,
+ CB_PERF_SEL_CM_CACHE_TAG_MISS = 0x42,
+ CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 0x43,
+ CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 0x44,
+ CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x45,
+ CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x46,
+ CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x47,
+ CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 0x48,
+ CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 0x49,
+ CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 0x4a,
+ CB_PERF_SEL_CM_CACHE_STALL = 0x4b,
+ CB_PERF_SEL_CM_CACHE_FLUSH = 0x4c,
+ CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 0x4d,
+ CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 0x4e,
+ CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 0x4f,
+ CB_PERF_SEL_FC_CACHE_HIT = 0x50,
+ CB_PERF_SEL_FC_CACHE_TAG_MISS = 0x51,
+ CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 0x52,
+ CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 0x53,
+ CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x54,
+ CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x55,
+ CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x56,
+ CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 0x57,
+ CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 0x58,
+ CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 0x59,
+ CB_PERF_SEL_FC_CACHE_STALL = 0x5a,
+ CB_PERF_SEL_FC_CACHE_FLUSH = 0x5b,
+ CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 0x5c,
+ CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 0x5d,
+ CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 0x5e,
+ CB_PERF_SEL_CC_CACHE_HIT = 0x5f,
+ CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x60,
+ CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x61,
+ CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 0x62,
+ CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x63,
+ CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x64,
+ CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x65,
+ CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x66,
+ CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x67,
+ CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x68,
+ CB_PERF_SEL_CC_CACHE_STALL = 0x69,
+ CB_PERF_SEL_CC_CACHE_FLUSH = 0x6a,
+ CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 0x6b,
+ CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x6c,
+ CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x6d,
+ CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x6e,
+ CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 0x6f,
+ CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 0x70,
+ CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 0x71,
+ CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 0x72,
+ CB_PERF_SEL_CM_MC_WRITE_REQUEST = 0x73,
+ CB_PERF_SEL_FC_MC_WRITE_REQUEST = 0x74,
+ CB_PERF_SEL_CC_MC_WRITE_REQUEST = 0x75,
+ CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 0x76,
+ CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x77,
+ CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x78,
+ CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 0x79,
+ CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 0x7a,
+ CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 0x7b,
+ CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 0x7c,
+ CB_PERF_SEL_CM_MC_READ_REQUEST = 0x7d,
+ CB_PERF_SEL_FC_MC_READ_REQUEST = 0x7e,
+ CB_PERF_SEL_CC_MC_READ_REQUEST = 0x7f,
+ CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 0x80,
+ CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 0x81,
+ CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x82,
+ CB_PERF_SEL_CM_TQ_FULL = 0x83,
+ CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 0x84,
+ CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 0x85,
+ CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 0x86,
+ CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 0x87,
+ CB_PERF_SEL_FOP_FMASK_RAW_STALL = 0x88,
+ CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 0x89,
+ CB_PERF_SEL_CC_SF_FULL = 0x8a,
+ CB_PERF_SEL_CC_RB_FULL = 0x8b,
+ CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 0x8c,
+ CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 0x8d,
+ CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 0x8e,
+ CB_PERF_SEL_EVENT = 0x8f,
+ CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 0x90,
+ CB_PERF_SEL_EVENT_CONTEXT_DONE = 0x91,
+ CB_PERF_SEL_EVENT_CACHE_FLUSH = 0x92,
+ CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x93,
+ CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x94,
+ CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x95,
+ CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 0x96,
+ CB_PERF_SEL_CC_SURFACE_SYNC = 0x97,
+ CB_PERF_SEL_CMASK_READ_DATA_0xC = 0x98,
+ CB_PERF_SEL_CMASK_READ_DATA_0xD = 0x99,
+ CB_PERF_SEL_CMASK_READ_DATA_0xE = 0x9a,
+ CB_PERF_SEL_CMASK_READ_DATA_0xF = 0x9b,
+ CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 0x9c,
+ CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 0x9d,
+ CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 0x9e,
+ CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 0x9f,
+ CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 0xa0,
+ CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 0xa1,
+ CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 0xa2,
+ CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 0xa3,
+ CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 0xa4,
+ CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 0xa5,
+ CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 0xa6,
+ CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 0xa7,
+ CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 0xa8,
+ CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 0xa9,
+ CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 0xaa,
+ CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 0xab,
+ CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 0xac,
+ CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 0xad,
+ CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 0xae,
+ CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 0xaf,
+ CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 0xb0,
+ CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 0xb1,
+ CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 0xb2,
+ CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 0xb3,
+ CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 0xb4,
+ CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 0xb5,
+ CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 0xb6,
+ CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 0xb7,
+ CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 0xb8,
+ CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 0xb9,
+ CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 0xba,
+ CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 0xbb,
+ CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 0xbc,
+ CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 0xbd,
+ CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 0xbe,
+ CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 0xbf,
+ CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 0xc0,
+ CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 0xc1,
+ CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 0xc2,
+ CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 0xc3,
+ CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 0xc4,
+ CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 0xc5,
+ CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 0xc6,
+ CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 0xc7,
+ CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 0xc8,
+ CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 0xc9,
+ CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 0xca,
+ CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 0xcb,
+ CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 0xcc,
+ CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 0xcd,
+ CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 0xce,
+ CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 0xcf,
+ CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 0xd0,
+ CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 0xd1,
+ CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 0xd2,
+ CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 0xd3,
+ CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED= 0xd4,
+ CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED= 0xd5,
+ CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 0xd6,
+ CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0xd7,
+ CB_PERF_SEL_DRAWN_BUSY = 0xd8,
+ CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 0xd9,
+ CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 0xda,
+ CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 0xdb,
+ CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 0xdc,
+ CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED= 0xdd,
+ CB_PERF_SEL_FC_SEQUENCER_CLEAR = 0xde,
+ CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 0xdf,
+ CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 0xe0,
+ CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE= 0xe1,
+} CBPerfSel;
+typedef enum CBPerfOpFilterSel {
+ CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x0,
+ CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x1,
+ CB_PERF_OP_FILTER_SEL_RESOLVE = 0x2,
+ CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x3,
+ CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x4,
+ CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x5,
+} CBPerfOpFilterSel;
+typedef enum CBPerfClearFilterSel {
+ CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x0,
+ CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x1,
+} CBPerfClearFilterSel;
+typedef enum CP_RING_ID {
+ RINGID0 = 0x0,
+ RINGID1 = 0x1,
+ RINGID2 = 0x2,
+ RINGID3 = 0x3,
+} CP_RING_ID;
+typedef enum CP_PIPE_ID {
+ PIPE_ID0 = 0x0,
+ PIPE_ID1 = 0x1,
+ PIPE_ID2 = 0x2,
+ PIPE_ID3 = 0x3,
+} CP_PIPE_ID;
+typedef enum CP_ME_ID {
+ ME_ID0 = 0x0,
+ ME_ID1 = 0x1,
+ ME_ID2 = 0x2,
+ ME_ID3 = 0x3,
+} CP_ME_ID;
+typedef enum SPM_PERFMON_STATE {
+ STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x0,
+ STRM_PERFMON_STATE_START_COUNTING = 0x1,
+ STRM_PERFMON_STATE_STOP_COUNTING = 0x2,
+ STRM_PERFMON_STATE_RESERVED_3 = 0x3,
+ STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x4,
+ STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5,
+} SPM_PERFMON_STATE;
+typedef enum CP_PERFMON_STATE {
+ CP_PERFMON_STATE_DISABLE_AND_RESET = 0x0,
+ CP_PERFMON_STATE_START_COUNTING = 0x1,
+ CP_PERFMON_STATE_STOP_COUNTING = 0x2,
+ CP_PERFMON_STATE_RESERVED_3 = 0x3,
+ CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x4,
+ CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5,
+} CP_PERFMON_STATE;
+typedef enum CP_PERFMON_ENABLE_MODE {
+ CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x0,
+ CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x1,
+ CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x2,
+ CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x3,
+} CP_PERFMON_ENABLE_MODE;
+typedef enum CPG_PERFCOUNT_SEL {
+ CPG_PERF_SEL_ALWAYS_COUNT = 0x0,
+ CPG_PERF_SEL_RBIU_FIFO_FULL = 0x1,
+ CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x2,
+ CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 0x3,
+ CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x4,
+ CPG_PERF_SEL_ME_PARSER_BUSY = 0x5,
+ CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x6,
+ CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x7,
+ CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x8,
+ CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x9,
+ CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0xa,
+ CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0xb,
+ CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0xc,
+ CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0xd,
+ CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0xe,
+ CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0xf,
+ CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x10,
+ CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x11,
+ CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x12,
+ CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x13,
+ CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x14,
+ CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x15,
+ CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x16,
+ CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x17,
+ CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x18,
+ CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x19,
+ CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x1a,
+ CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x1b,
+ CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x1c,
+ CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x1d,
+ CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x1e,
+ CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x1f,
+ CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x20,
+ CPG_PERF_SEL_REGISTER_CLK_VALID = 0x21,
+ CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT = 0x22,
+ CPG_PERF_SEL_MIU_READ_REQUEST_SENT = 0x23,
+ CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x24,
+ CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x25,
+ CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x26,
+ CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x27,
+ CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 0x28,
+ CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x29,
+ CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x2a,
+ CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x2b,
+ CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x2c,
+ CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x2d,
+} CPG_PERFCOUNT_SEL;
+typedef enum CPF_PERFCOUNT_SEL {
+ CPF_PERF_SEL_ALWAYS_COUNT = 0x0,
+ CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 0x1,
+ CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x2,
+ CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x3,
+ CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x4,
+ CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x5,
+ CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x6,
+ CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 0x7,
+ CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 0x8,
+ CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 0x9,
+ CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0xa,
+ CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0xb,
+ CPF_PERF_SEL_GRBM_DWORDS_SENT = 0xc,
+ CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0xd,
+ CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0xe,
+ CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND = 0xf,
+ CPF_PERF_SEL_MIU_READ_REQUEST_SEND = 0x10,
+} CPF_PERFCOUNT_SEL;
+typedef enum CPC_PERFCOUNT_SEL {
+ CPC_PERF_SEL_ALWAYS_COUNT = 0x0,
+ CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x1,
+ CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x2,
+ CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 0x3,
+ CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 0x4,
+ CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x5,
+ CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x6,
+ CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x7,
+ CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x8,
+ CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ = 0x9,
+ CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0xa,
+ CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0xb,
+ CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0xc,
+ CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0xd,
+ CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0xe,
+ CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0xf,
+ CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x10,
+ CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ = 0x11,
+ CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE = 0x12,
+ CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x13,
+ CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x14,
+ CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x15,
+} CPC_PERFCOUNT_SEL;
+typedef enum CP_ALPHA_TAG_RAM_SEL {
+ CPG_TAG_RAM = 0x0,
+ CPC_TAG_RAM = 0x1,
+ CPF_TAG_RAM = 0x2,
+ RSV_TAG_RAM = 0x3,
+} CP_ALPHA_TAG_RAM_SEL;
+#define SEM_ECC_ERROR 0x0
+#define SEM_RESERVED 0x1
+#define SEM_FAILED 0x2
+#define SEM_PASSED 0x3
+#define IQ_QUEUE_SLEEP 0x0
+#define IQ_OFFLOAD_RETRY 0x1
+#define IQ_SCH_WAVE_MSG 0x2
+#define IQ_SEM_REARM 0x3
+#define IQ_DEQUEUE_RETRY 0x4
+#define IQ_INTR_TYPE_PQ 0x0
+#define IQ_INTR_TYPE_IB 0x1
+#define IQ_INTR_TYPE_MQD 0x2
+#define VMID_SZ 0x4
+#define CONFIG_SPACE_START 0x2000
+#define CONFIG_SPACE_END 0x9fff
+#define CONFIG_SPACE1_START 0x2000
+#define CONFIG_SPACE1_END 0x2bff
+#define CONFIG_SPACE2_START 0x3000
+#define CONFIG_SPACE2_END 0x9fff
+#define UCONFIG_SPACE_START 0xc000
+#define UCONFIG_SPACE_END 0xffff
+#define PERSISTENT_SPACE_START 0x2c00
+#define PERSISTENT_SPACE_END 0x2fff
+#define CONTEXT_SPACE_START 0xa000
+#define CONTEXT_SPACE_END 0xbfff
+typedef enum ForceControl {
+ FORCE_OFF = 0x0,
+ FORCE_ENABLE = 0x1,
+ FORCE_DISABLE = 0x2,
+ FORCE_RESERVED = 0x3,
+} ForceControl;
+typedef enum ZSamplePosition {
+ Z_SAMPLE_CENTER = 0x0,
+ Z_SAMPLE_CENTROID = 0x1,
+} ZSamplePosition;
+typedef enum ZOrder {
+ LATE_Z = 0x0,
+ EARLY_Z_THEN_LATE_Z = 0x1,
+ RE_Z = 0x2,
+ EARLY_Z_THEN_RE_Z = 0x3,
+} ZOrder;
+typedef enum ZpassControl {
+ ZPASS_DISABLE = 0x0,
+ ZPASS_SAMPLES = 0x1,
+ ZPASS_PIXELS = 0x2,
+} ZpassControl;
+typedef enum ZModeForce {
+ NO_FORCE = 0x0,
+ FORCE_EARLY_Z = 0x1,
+ FORCE_LATE_Z = 0x2,
+ FORCE_RE_Z = 0x3,
+} ZModeForce;
+typedef enum ZLimitSumm {
+ FORCE_SUMM_OFF = 0x0,
+ FORCE_SUMM_MINZ = 0x1,
+ FORCE_SUMM_MAXZ = 0x2,
+ FORCE_SUMM_BOTH = 0x3,
+} ZLimitSumm;
+typedef enum CompareFrag {
+ FRAG_NEVER = 0x0,
+ FRAG_LESS = 0x1,
+ FRAG_EQUAL = 0x2,
+ FRAG_LEQUAL = 0x3,
+ FRAG_GREATER = 0x4,
+ FRAG_NOTEQUAL = 0x5,
+ FRAG_GEQUAL = 0x6,
+ FRAG_ALWAYS = 0x7,
+} CompareFrag;
+typedef enum StencilOp {
+ STENCIL_KEEP = 0x0,
+ STENCIL_ZERO = 0x1,
+ STENCIL_ONES = 0x2,
+ STENCIL_REPLACE_TEST = 0x3,
+ STENCIL_REPLACE_OP = 0x4,
+ STENCIL_ADD_CLAMP = 0x5,
+ STENCIL_SUB_CLAMP = 0x6,
+ STENCIL_INVERT = 0x7,
+ STENCIL_ADD_WRAP = 0x8,
+ STENCIL_SUB_WRAP = 0x9,
+ STENCIL_AND = 0xa,
+ STENCIL_OR = 0xb,
+ STENCIL_XOR = 0xc,
+ STENCIL_NAND = 0xd,
+ STENCIL_NOR = 0xe,
+ STENCIL_XNOR = 0xf,
+} StencilOp;
+typedef enum ConservativeZExport {
+ EXPORT_ANY_Z = 0x0,
+ EXPORT_LESS_THAN_Z = 0x1,
+ EXPORT_GREATER_THAN_Z = 0x2,
+ EXPORT_RESERVED = 0x3,
+} ConservativeZExport;
+typedef enum DbPSLControl {
+ PSLC_AUTO = 0x0,
+ PSLC_ON_HANG_ONLY = 0x1,
+ PSLC_ASAP = 0x2,
+ PSLC_COUNTDOWN = 0x3,
+} DbPSLControl;
+typedef enum PerfCounter_Vals {
+ DB_PERF_SEL_SC_DB_tile_sends = 0x0,
+ DB_PERF_SEL_SC_DB_tile_busy = 0x1,
+ DB_PERF_SEL_SC_DB_tile_stalls = 0x2,
+ DB_PERF_SEL_SC_DB_tile_events = 0x3,
+ DB_PERF_SEL_SC_DB_tile_tiles = 0x4,
+ DB_PERF_SEL_SC_DB_tile_covered = 0x5,
+ DB_PERF_SEL_hiz_tc_read_starved = 0x6,
+ DB_PERF_SEL_hiz_tc_write_stall = 0x7,
+ DB_PERF_SEL_hiz_qtiles_culled = 0x8,
+ DB_PERF_SEL_his_qtiles_culled = 0x9,
+ DB_PERF_SEL_DB_SC_tile_sends = 0xa,
+ DB_PERF_SEL_DB_SC_tile_busy = 0xb,
+ DB_PERF_SEL_DB_SC_tile_stalls = 0xc,
+ DB_PERF_SEL_DB_SC_tile_df_stalls = 0xd,
+ DB_PERF_SEL_DB_SC_tile_tiles = 0xe,
+ DB_PERF_SEL_DB_SC_tile_culled = 0xf,
+ DB_PERF_SEL_DB_SC_tile_hier_kill = 0x10,
+ DB_PERF_SEL_DB_SC_tile_fast_ops = 0x11,
+ DB_PERF_SEL_DB_SC_tile_no_ops = 0x12,
+ DB_PERF_SEL_DB_SC_tile_tile_rate = 0x13,
+ DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x14,
+ DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x15,
+ DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x16,
+ DB_PERF_SEL_SC_DB_quad_sends = 0x17,
+ DB_PERF_SEL_SC_DB_quad_busy = 0x18,
+ DB_PERF_SEL_SC_DB_quad_squads = 0x19,
+ DB_PERF_SEL_SC_DB_quad_tiles = 0x1a,
+ DB_PERF_SEL_SC_DB_quad_pixels = 0x1b,
+ DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x1c,
+ DB_PERF_SEL_DB_SC_quad_sends = 0x1d,
+ DB_PERF_SEL_DB_SC_quad_busy = 0x1e,
+ DB_PERF_SEL_DB_SC_quad_stalls = 0x1f,
+ DB_PERF_SEL_DB_SC_quad_tiles = 0x20,
+ DB_PERF_SEL_DB_SC_quad_lit_quad = 0x21,
+ DB_PERF_SEL_DB_CB_tile_sends = 0x22,
+ DB_PERF_SEL_DB_CB_tile_busy = 0x23,
+ DB_PERF_SEL_DB_CB_tile_stalls = 0x24,
+ DB_PERF_SEL_SX_DB_quad_sends = 0x25,
+ DB_PERF_SEL_SX_DB_quad_busy = 0x26,
+ DB_PERF_SEL_SX_DB_quad_stalls = 0x27,
+ DB_PERF_SEL_SX_DB_quad_quads = 0x28,
+ DB_PERF_SEL_SX_DB_quad_pixels = 0x29,
+ DB_PERF_SEL_SX_DB_quad_exports = 0x2a,
+ DB_PERF_SEL_SH_quads_outstanding_sum = 0x2b,
+ DB_PERF_SEL_DB_CB_lquad_sends = 0x2c,
+ DB_PERF_SEL_DB_CB_lquad_busy = 0x2d,
+ DB_PERF_SEL_DB_CB_lquad_stalls = 0x2e,
+ DB_PERF_SEL_DB_CB_lquad_quads = 0x2f,
+ DB_PERF_SEL_tile_rd_sends = 0x30,
+ DB_PERF_SEL_mi_tile_rd_outstanding_sum = 0x31,
+ DB_PERF_SEL_quad_rd_sends = 0x32,
+ DB_PERF_SEL_quad_rd_busy = 0x33,
+ DB_PERF_SEL_quad_rd_mi_stall = 0x34,
+ DB_PERF_SEL_quad_rd_rw_collision = 0x35,
+ DB_PERF_SEL_quad_rd_tag_stall = 0x36,
+ DB_PERF_SEL_quad_rd_32byte_reqs = 0x37,
+ DB_PERF_SEL_quad_rd_panic = 0x38,
+ DB_PERF_SEL_mi_quad_rd_outstanding_sum = 0x39,
+ DB_PERF_SEL_quad_rdret_sends = 0x3a,
+ DB_PERF_SEL_quad_rdret_busy = 0x3b,
+ DB_PERF_SEL_tile_wr_sends = 0x3c,
+ DB_PERF_SEL_tile_wr_acks = 0x3d,
+ DB_PERF_SEL_mi_tile_wr_outstanding_sum = 0x3e,
+ DB_PERF_SEL_quad_wr_sends = 0x3f,
+ DB_PERF_SEL_quad_wr_busy = 0x40,
+ DB_PERF_SEL_quad_wr_mi_stall = 0x41,
+ DB_PERF_SEL_quad_wr_coherency_stall = 0x42,
+ DB_PERF_SEL_quad_wr_acks = 0x43,
+ DB_PERF_SEL_mi_quad_wr_outstanding_sum = 0x44,
+ DB_PERF_SEL_Tile_Cache_misses = 0x45,
+ DB_PERF_SEL_Tile_Cache_hits = 0x46,
+ DB_PERF_SEL_Tile_Cache_flushes = 0x47,
+ DB_PERF_SEL_Tile_Cache_surface_stall = 0x48,
+ DB_PERF_SEL_Tile_Cache_starves = 0x49,
+ DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x4a,
+ DB_PERF_SEL_tcp_dispatcher_reads = 0x4b,
+ DB_PERF_SEL_tcp_prefetcher_reads = 0x4c,
+ DB_PERF_SEL_tcp_preloader_reads = 0x4d,
+ DB_PERF_SEL_tcp_dispatcher_flushes = 0x4e,
+ DB_PERF_SEL_tcp_prefetcher_flushes = 0x4f,
+ DB_PERF_SEL_tcp_preloader_flushes = 0x50,
+ DB_PERF_SEL_Depth_Tile_Cache_sends = 0x51,
+ DB_PERF_SEL_Depth_Tile_Cache_busy = 0x52,
+ DB_PERF_SEL_Depth_Tile_Cache_starves = 0x53,
+ DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x54,
+ DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x55,
+ DB_PERF_SEL_Depth_Tile_Cache_misses = 0x56,
+ DB_PERF_SEL_Depth_Tile_Cache_hits = 0x57,
+ DB_PERF_SEL_Depth_Tile_Cache_flushes = 0x58,
+ DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 0x59,
+ DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x5a,
+ DB_PERF_SEL_Depth_Tile_Cache_event = 0x5b,
+ DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 0x5c,
+ DB_PERF_SEL_Depth_Tile_Cache_data_frees = 0x5d,
+ DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x5e,
+ DB_PERF_SEL_Stencil_Cache_misses = 0x5f,
+ DB_PERF_SEL_Stencil_Cache_hits = 0x60,
+ DB_PERF_SEL_Stencil_Cache_flushes = 0x61,
+ DB_PERF_SEL_Stencil_Cache_starves = 0x62,
+ DB_PERF_SEL_Stencil_Cache_frees = 0x63,
+ DB_PERF_SEL_Z_Cache_separate_Z_misses = 0x64,
+ DB_PERF_SEL_Z_Cache_separate_Z_hits = 0x65,
+ DB_PERF_SEL_Z_Cache_separate_Z_flushes = 0x66,
+ DB_PERF_SEL_Z_Cache_separate_Z_starves = 0x67,
+ DB_PERF_SEL_Z_Cache_pmask_misses = 0x68,
+ DB_PERF_SEL_Z_Cache_pmask_hits = 0x69,
+ DB_PERF_SEL_Z_Cache_pmask_flushes = 0x6a,
+ DB_PERF_SEL_Z_Cache_pmask_starves = 0x6b,
+ DB_PERF_SEL_Z_Cache_frees = 0x6c,
+ DB_PERF_SEL_Plane_Cache_misses = 0x6d,
+ DB_PERF_SEL_Plane_Cache_hits = 0x6e,
+ DB_PERF_SEL_Plane_Cache_flushes = 0x6f,
+ DB_PERF_SEL_Plane_Cache_starves = 0x70,
+ DB_PERF_SEL_Plane_Cache_frees = 0x71,
+ DB_PERF_SEL_flush_expanded_stencil = 0x72,
+ DB_PERF_SEL_flush_compressed_stencil = 0x73,
+ DB_PERF_SEL_flush_single_stencil = 0x74,
+ DB_PERF_SEL_planes_flushed = 0x75,
+ DB_PERF_SEL_flush_1plane = 0x76,
+ DB_PERF_SEL_flush_2plane = 0x77,
+ DB_PERF_SEL_flush_3plane = 0x78,
+ DB_PERF_SEL_flush_4plane = 0x79,
+ DB_PERF_SEL_flush_5plane = 0x7a,
+ DB_PERF_SEL_flush_6plane = 0x7b,
+ DB_PERF_SEL_flush_7plane = 0x7c,
+ DB_PERF_SEL_flush_8plane = 0x7d,
+ DB_PERF_SEL_flush_9plane = 0x7e,
+ DB_PERF_SEL_flush_10plane = 0x7f,
+ DB_PERF_SEL_flush_11plane = 0x80,
+ DB_PERF_SEL_flush_12plane = 0x81,
+ DB_PERF_SEL_flush_13plane = 0x82,
+ DB_PERF_SEL_flush_14plane = 0x83,
+ DB_PERF_SEL_flush_15plane = 0x84,
+ DB_PERF_SEL_flush_16plane = 0x85,
+ DB_PERF_SEL_flush_expanded_z = 0x86,
+ DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x87,
+ DB_PERF_SEL_reZ_waiting_for_postZ_done = 0x88,
+ DB_PERF_SEL_dk_tile_sends = 0x89,
+ DB_PERF_SEL_dk_tile_busy = 0x8a,
+ DB_PERF_SEL_dk_tile_quad_starves = 0x8b,
+ DB_PERF_SEL_dk_tile_stalls = 0x8c,
+ DB_PERF_SEL_dk_squad_sends = 0x8d,
+ DB_PERF_SEL_dk_squad_busy = 0x8e,
+ DB_PERF_SEL_dk_squad_stalls = 0x8f,
+ DB_PERF_SEL_Op_Pipe_Busy = 0x90,
+ DB_PERF_SEL_Op_Pipe_MC_Read_stall = 0x91,
+ DB_PERF_SEL_qc_busy = 0x92,
+ DB_PERF_SEL_qc_xfc = 0x93,
+ DB_PERF_SEL_qc_conflicts = 0x94,
+ DB_PERF_SEL_qc_full_stall = 0x95,
+ DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x96,
+ DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x97,
+ DB_PERF_SEL_tsc_insert_summarize_stall = 0x98,
+ DB_PERF_SEL_tl_busy = 0x99,
+ DB_PERF_SEL_tl_dtc_read_starved = 0x9a,
+ DB_PERF_SEL_tl_z_fetch_stall = 0x9b,
+ DB_PERF_SEL_tl_stencil_stall = 0x9c,
+ DB_PERF_SEL_tl_z_decompress_stall = 0x9d,
+ DB_PERF_SEL_tl_stencil_locked_stall = 0x9e,
+ DB_PERF_SEL_tl_events = 0x9f,
+ DB_PERF_SEL_tl_summarize_squads = 0xa0,
+ DB_PERF_SEL_tl_flush_expand_squads = 0xa1,
+ DB_PERF_SEL_tl_expand_squads = 0xa2,
+ DB_PERF_SEL_tl_preZ_squads = 0xa3,
+ DB_PERF_SEL_tl_postZ_squads = 0xa4,
+ DB_PERF_SEL_tl_preZ_noop_squads = 0xa5,
+ DB_PERF_SEL_tl_postZ_noop_squads = 0xa6,
+ DB_PERF_SEL_tl_tile_ops = 0xa7,
+ DB_PERF_SEL_tl_in_xfc = 0xa8,
+ DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0xa9,
+ DB_PERF_SEL_tl_in_fast_z_stall = 0xaa,
+ DB_PERF_SEL_tl_out_xfc = 0xab,
+ DB_PERF_SEL_tl_out_squads = 0xac,
+ DB_PERF_SEL_zf_plane_multicycle = 0xad,
+ DB_PERF_SEL_PostZ_Samples_passing_Z = 0xae,
+ DB_PERF_SEL_PostZ_Samples_failing_Z = 0xaf,
+ DB_PERF_SEL_PostZ_Samples_failing_S = 0xb0,
+ DB_PERF_SEL_PreZ_Samples_passing_Z = 0xb1,
+ DB_PERF_SEL_PreZ_Samples_failing_Z = 0xb2,
+ DB_PERF_SEL_PreZ_Samples_failing_S = 0xb3,
+ DB_PERF_SEL_ts_tc_update_stall = 0xb4,
+ DB_PERF_SEL_sc_kick_start = 0xb5,
+ DB_PERF_SEL_sc_kick_end = 0xb6,
+ DB_PERF_SEL_clock_reg_active = 0xb7,
+ DB_PERF_SEL_clock_main_active = 0xb8,
+ DB_PERF_SEL_clock_mem_export_active = 0xb9,
+ DB_PERF_SEL_esr_ps_out_busy = 0xba,
+ DB_PERF_SEL_esr_ps_lqf_busy = 0xbb,
+ DB_PERF_SEL_esr_ps_lqf_stall = 0xbc,
+ DB_PERF_SEL_etr_out_send = 0xbd,
+ DB_PERF_SEL_etr_out_busy = 0xbe,
+ DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0xbf,
+ DB_PERF_SEL_etr_out_cb_tile_stall = 0xc0,
+ DB_PERF_SEL_etr_out_esr_stall = 0xc1,
+ DB_PERF_SEL_esr_ps_sqq_busy = 0xc2,
+ DB_PERF_SEL_esr_ps_sqq_stall = 0xc3,
+ DB_PERF_SEL_esr_eot_fwd_busy = 0xc4,
+ DB_PERF_SEL_esr_eot_fwd_holding_squad = 0xc5,
+ DB_PERF_SEL_esr_eot_fwd_forward = 0xc6,
+ DB_PERF_SEL_esr_sqq_zi_busy = 0xc7,
+ DB_PERF_SEL_esr_sqq_zi_stall = 0xc8,
+ DB_PERF_SEL_postzl_sq_pt_busy = 0xc9,
+ DB_PERF_SEL_postzl_sq_pt_stall = 0xca,
+ DB_PERF_SEL_postzl_se_busy = 0xcb,
+ DB_PERF_SEL_postzl_se_stall = 0xcc,
+ DB_PERF_SEL_postzl_partial_launch = 0xcd,
+ DB_PERF_SEL_postzl_full_launch = 0xce,
+ DB_PERF_SEL_postzl_partial_waiting = 0xcf,
+ DB_PERF_SEL_postzl_tile_mem_stall = 0xd0,
+ DB_PERF_SEL_postzl_tile_init_stall = 0xd1,
+ DB_PEFF_SEL_prezl_tile_mem_stall = 0xd2,
+ DB_PERF_SEL_prezl_tile_init_stall = 0xd3,
+ DB_PERF_SEL_dtt_sm_clash_stall = 0xd4,
+ DB_PERF_SEL_dtt_sm_slot_stall = 0xd5,
+ DB_PERF_SEL_dtt_sm_miss_stall = 0xd6,
+ DB_PERF_SEL_mi_rdreq_busy = 0xd7,
+ DB_PERF_SEL_mi_rdreq_stall = 0xd8,
+ DB_PERF_SEL_mi_wrreq_busy = 0xd9,
+ DB_PERF_SEL_mi_wrreq_stall = 0xda,
+ DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0xdb,
+ DB_PERF_SEL_dkg_tile_rate_tile = 0xdc,
+ DB_PERF_SEL_prezl_src_in_sends = 0xdd,
+ DB_PERF_SEL_prezl_src_in_stall = 0xde,
+ DB_PERF_SEL_prezl_src_in_squads = 0xdf,
+ DB_PERF_SEL_prezl_src_in_squads_unrolled = 0xe0,
+ DB_PERF_SEL_prezl_src_in_tile_rate = 0xe1,
+ DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0xe2,
+ DB_PERF_SEL_prezl_src_out_stall = 0xe3,
+ DB_PERF_SEL_postzl_src_in_sends = 0xe4,
+ DB_PERF_SEL_postzl_src_in_stall = 0xe5,
+ DB_PERF_SEL_postzl_src_in_squads = 0xe6,
+ DB_PERF_SEL_postzl_src_in_squads_unrolled = 0xe7,
+ DB_PERF_SEL_postzl_src_in_tile_rate = 0xe8,
+ DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0xe9,
+ DB_PERF_SEL_postzl_src_out_stall = 0xea,
+ DB_PERF_SEL_esr_ps_src_in_sends = 0xeb,
+ DB_PERF_SEL_esr_ps_src_in_stall = 0xec,
+ DB_PERF_SEL_esr_ps_src_in_squads = 0xed,
+ DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0xee,
+ DB_PERF_SEL_esr_ps_src_in_tile_rate = 0xef,
+ DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0xf0,
+ DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate= 0xf1,
+ DB_PERF_SEL_esr_ps_src_out_stall = 0xf2,
+ DB_PERF_SEL_depth_bounds_qtiles_culled = 0xf3,
+ DB_PERF_SEL_PreZ_Samples_failing_DB = 0xf4,
+ DB_PERF_SEL_PostZ_Samples_failing_DB = 0xf5,
+ DB_PERF_SEL_flush_compressed = 0xf6,
+ DB_PERF_SEL_flush_plane_le4 = 0xf7,
+ DB_PERF_SEL_tiles_z_fully_summarized = 0xf8,
+ DB_PERF_SEL_tiles_stencil_fully_summarized = 0xf9,
+ DB_PERF_SEL_tiles_z_clear_on_expclear = 0xfa,
+ DB_PERF_SEL_tiles_s_clear_on_expclear = 0xfb,
+ DB_PERF_SEL_tiles_decomp_on_expclear = 0xfc,
+ DB_PERF_SEL_tiles_compressed_to_decompressed = 0xfd,
+ DB_PERF_SEL_Op_Pipe_Prez_Busy = 0xfe,
+ DB_PERF_SEL_Op_Pipe_Postz_Busy = 0xff,
+ DB_PERF_SEL_di_dt_stall = 0x100,
+} PerfCounter_Vals;
+typedef enum RingCounterControl {
+ COUNTER_RING_SPLIT = 0x0,
+ COUNTER_RING_0 = 0x1,
+ COUNTER_RING_1 = 0x2,
+} RingCounterControl;
+typedef enum PixelPipeCounterId {
+ PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x0,
+ PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x1,
+ PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x2,
+ PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x3,
+ PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 0x4,
+ PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 0x5,
+ PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 0x6,
+ PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 0x7,
+} PixelPipeCounterId;
+typedef enum PixelPipeStride {
+ PIXEL_PIPE_STRIDE_32_BITS = 0x0,
+ PIXEL_PIPE_STRIDE_64_BITS = 0x1,
+ PIXEL_PIPE_STRIDE_128_BITS = 0x2,
+ PIXEL_PIPE_STRIDE_256_BITS = 0x3,
+} PixelPipeStride;
+typedef enum GB_EDC_DED_MODE {
+ GB_EDC_DED_MODE_LOG = 0x0,
+ GB_EDC_DED_MODE_HALT = 0x1,
+ GB_EDC_DED_MODE_INT_HALT = 0x2,
+} GB_EDC_DED_MODE;
+#define GB_TILING_CONFIG_TABLE_SIZE 0x20
+#define GB_TILING_CONFIG_MACROTABLE_SIZE 0x10
+typedef enum GRBM_PERF_SEL {
+ GRBM_PERF_SEL_COUNT = 0x0,
+ GRBM_PERF_SEL_USER_DEFINED = 0x1,
+ GRBM_PERF_SEL_GUI_ACTIVE = 0x2,
+ GRBM_PERF_SEL_CP_BUSY = 0x3,
+ GRBM_PERF_SEL_CP_COHER_BUSY = 0x4,
+ GRBM_PERF_SEL_CP_DMA_BUSY = 0x5,
+ GRBM_PERF_SEL_CB_BUSY = 0x6,
+ GRBM_PERF_SEL_DB_BUSY = 0x7,
+ GRBM_PERF_SEL_PA_BUSY = 0x8,
+ GRBM_PERF_SEL_SC_BUSY = 0x9,
+ GRBM_PERF_SEL_RESERVED_6 = 0xa,
+ GRBM_PERF_SEL_SPI_BUSY = 0xb,
+ GRBM_PERF_SEL_SX_BUSY = 0xc,
+ GRBM_PERF_SEL_TA_BUSY = 0xd,
+ GRBM_PERF_SEL_CB_CLEAN = 0xe,
+ GRBM_PERF_SEL_DB_CLEAN = 0xf,
+ GRBM_PERF_SEL_RESERVED_5 = 0x10,
+ GRBM_PERF_SEL_VGT_BUSY = 0x11,
+ GRBM_PERF_SEL_RESERVED_4 = 0x12,
+ GRBM_PERF_SEL_RESERVED_3 = 0x13,
+ GRBM_PERF_SEL_RESERVED_2 = 0x14,
+ GRBM_PERF_SEL_RESERVED_1 = 0x15,
+ GRBM_PERF_SEL_RESERVED_0 = 0x16,
+ GRBM_PERF_SEL_IA_BUSY = 0x17,
+ GRBM_PERF_SEL_IA_NO_DMA_BUSY = 0x18,
+ GRBM_PERF_SEL_GDS_BUSY = 0x19,
+ GRBM_PERF_SEL_BCI_BUSY = 0x1a,
+ GRBM_PERF_SEL_RLC_BUSY = 0x1b,
+ GRBM_PERF_SEL_TC_BUSY = 0x1c,
+ GRBM_PERF_SEL_CPG_BUSY = 0x1d,
+ GRBM_PERF_SEL_CPC_BUSY = 0x1e,
+ GRBM_PERF_SEL_CPF_BUSY = 0x1f,
+ GRBM_PERF_SEL_WD_BUSY = 0x20,
+ GRBM_PERF_SEL_WD_NO_DMA_BUSY = 0x21,
+} GRBM_PERF_SEL;
+typedef enum GRBM_SE0_PERF_SEL {
+ GRBM_SE0_PERF_SEL_COUNT = 0x0,
+ GRBM_SE0_PERF_SEL_USER_DEFINED = 0x1,
+ GRBM_SE0_PERF_SEL_CB_BUSY = 0x2,
+ GRBM_SE0_PERF_SEL_DB_BUSY = 0x3,
+ GRBM_SE0_PERF_SEL_SC_BUSY = 0x4,
+ GRBM_SE0_PERF_SEL_RESERVED_1 = 0x5,
+ GRBM_SE0_PERF_SEL_SPI_BUSY = 0x6,
+ GRBM_SE0_PERF_SEL_SX_BUSY = 0x7,
+ GRBM_SE0_PERF_SEL_TA_BUSY = 0x8,
+ GRBM_SE0_PERF_SEL_CB_CLEAN = 0x9,
+ GRBM_SE0_PERF_SEL_DB_CLEAN = 0xa,
+ GRBM_SE0_PERF_SEL_RESERVED_0 = 0xb,
+ GRBM_SE0_PERF_SEL_PA_BUSY = 0xc,
+ GRBM_SE0_PERF_SEL_VGT_BUSY = 0xd,
+ GRBM_SE0_PERF_SEL_BCI_BUSY = 0xe,
+} GRBM_SE0_PERF_SEL;
+typedef enum GRBM_SE1_PERF_SEL {
+ GRBM_SE1_PERF_SEL_COUNT = 0x0,
+ GRBM_SE1_PERF_SEL_USER_DEFINED = 0x1,
+ GRBM_SE1_PERF_SEL_CB_BUSY = 0x2,
+ GRBM_SE1_PERF_SEL_DB_BUSY = 0x3,
+ GRBM_SE1_PERF_SEL_SC_BUSY = 0x4,
+ GRBM_SE1_PERF_SEL_RESERVED_1 = 0x5,
+ GRBM_SE1_PERF_SEL_SPI_BUSY = 0x6,
+ GRBM_SE1_PERF_SEL_SX_BUSY = 0x7,
+ GRBM_SE1_PERF_SEL_TA_BUSY = 0x8,
+ GRBM_SE1_PERF_SEL_CB_CLEAN = 0x9,
+ GRBM_SE1_PERF_SEL_DB_CLEAN = 0xa,
+ GRBM_SE1_PERF_SEL_RESERVED_0 = 0xb,
+ GRBM_SE1_PERF_SEL_PA_BUSY = 0xc,
+ GRBM_SE1_PERF_SEL_VGT_BUSY = 0xd,
+ GRBM_SE1_PERF_SEL_BCI_BUSY = 0xe,
+} GRBM_SE1_PERF_SEL;
+typedef enum GRBM_SE2_PERF_SEL {
+ GRBM_SE2_PERF_SEL_COUNT = 0x0,
+ GRBM_SE2_PERF_SEL_USER_DEFINED = 0x1,
+ GRBM_SE2_PERF_SEL_CB_BUSY = 0x2,
+ GRBM_SE2_PERF_SEL_DB_BUSY = 0x3,
+ GRBM_SE2_PERF_SEL_SC_BUSY = 0x4,
+ GRBM_SE2_PERF_SEL_RESERVED_1 = 0x5,
+ GRBM_SE2_PERF_SEL_SPI_BUSY = 0x6,
+ GRBM_SE2_PERF_SEL_SX_BUSY = 0x7,
+ GRBM_SE2_PERF_SEL_TA_BUSY = 0x8,
+ GRBM_SE2_PERF_SEL_CB_CLEAN = 0x9,
+ GRBM_SE2_PERF_SEL_DB_CLEAN = 0xa,
+ GRBM_SE2_PERF_SEL_RESERVED_0 = 0xb,
+ GRBM_SE2_PERF_SEL_PA_BUSY = 0xc,
+ GRBM_SE2_PERF_SEL_VGT_BUSY = 0xd,
+ GRBM_SE2_PERF_SEL_BCI_BUSY = 0xe,
+} GRBM_SE2_PERF_SEL;
+typedef enum GRBM_SE3_PERF_SEL {
+ GRBM_SE3_PERF_SEL_COUNT = 0x0,
+ GRBM_SE3_PERF_SEL_USER_DEFINED = 0x1,
+ GRBM_SE3_PERF_SEL_CB_BUSY = 0x2,
+ GRBM_SE3_PERF_SEL_DB_BUSY = 0x3,
+ GRBM_SE3_PERF_SEL_SC_BUSY = 0x4,
+ GRBM_SE3_PERF_SEL_RESERVED_1 = 0x5,
+ GRBM_SE3_PERF_SEL_SPI_BUSY = 0x6,
+ GRBM_SE3_PERF_SEL_SX_BUSY = 0x7,
+ GRBM_SE3_PERF_SEL_TA_BUSY = 0x8,
+ GRBM_SE3_PERF_SEL_CB_CLEAN = 0x9,
+ GRBM_SE3_PERF_SEL_DB_CLEAN = 0xa,
+ GRBM_SE3_PERF_SEL_RESERVED_0 = 0xb,
+ GRBM_SE3_PERF_SEL_PA_BUSY = 0xc,
+ GRBM_SE3_PERF_SEL_VGT_BUSY = 0xd,
+ GRBM_SE3_PERF_SEL_BCI_BUSY = 0xe,
+} GRBM_SE3_PERF_SEL;
+typedef enum SU_PERFCNT_SEL {
+ PERF_PAPC_PASX_REQ = 0x0,
+ PERF_PAPC_PASX_DISABLE_PIPE = 0x1,
+ PERF_PAPC_PASX_FIRST_VECTOR = 0x2,
+ PERF_PAPC_PASX_SECOND_VECTOR = 0x3,
+ PERF_PAPC_PASX_FIRST_DEAD = 0x4,
+ PERF_PAPC_PASX_SECOND_DEAD = 0x5,
+ PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x6,
+ PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x7,
+ PERF_PAPC_PA_INPUT_PRIM = 0x8,
+ PERF_PAPC_PA_INPUT_NULL_PRIM = 0x9,
+ PERF_PAPC_PA_INPUT_EVENT_FLAG = 0xa,
+ PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 0xb,
+ PERF_PAPC_PA_INPUT_END_OF_PACKET = 0xc,
+ PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 0xd,
+ PERF_PAPC_CLPR_CULL_PRIM = 0xe,
+ PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0xf,
+ PERF_PAPC_CLPR_VV_CULL_PRIM = 0x10,
+ PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x11,
+ PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x12,
+ PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x13,
+ PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x14,
+ PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x15,
+ PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x16,
+ PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x17,
+ PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x18,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x19,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x1a,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x1b,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x1c,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x1d,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 0x1e,
+ PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x1f,
+ PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x20,
+ PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x21,
+ PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x22,
+ PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x23,
+ PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x24,
+ PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 0x25,
+ PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x26,
+ PERF_PAPC_CLSM_NULL_PRIM = 0x27,
+ PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x28,
+ PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x29,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x2a,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x2b,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x2c,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x2d,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x2e,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 0x2f,
+ PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x30,
+ PERF_PAPC_SU_INPUT_PRIM = 0x31,
+ PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x32,
+ PERF_PAPC_SU_INPUT_NULL_PRIM = 0x33,
+ PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x34,
+ PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x35,
+ PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x36,
+ PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x37,
+ PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x38,
+ PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x39,
+ PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x3a,
+ PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x3b,
+ PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x3c,
+ PERF_PAPC_SU_OUTPUT_PRIM = 0x3d,
+ PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x3e,
+ PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x3f,
+ PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x40,
+ PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x41,
+ PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x42,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x43,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x44,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x45,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x46,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x47,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x48,
+ PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x49,
+ PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x4a,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x4b,
+ PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x4c,
+ PERF_PAPC_PASX_REQ_IDLE = 0x4d,
+ PERF_PAPC_PASX_REQ_BUSY = 0x4e,
+ PERF_PAPC_PASX_REQ_STALLED = 0x4f,
+ PERF_PAPC_PASX_REC_IDLE = 0x50,
+ PERF_PAPC_PASX_REC_BUSY = 0x51,
+ PERF_PAPC_PASX_REC_STARVED_SX = 0x52,
+ PERF_PAPC_PASX_REC_STALLED = 0x53,
+ PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x54,
+ PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x55,
+ PERF_PAPC_CCGSM_IDLE = 0x56,
+ PERF_PAPC_CCGSM_BUSY = 0x57,
+ PERF_PAPC_CCGSM_STALLED = 0x58,
+ PERF_PAPC_CLPRIM_IDLE = 0x59,
+ PERF_PAPC_CLPRIM_BUSY = 0x5a,
+ PERF_PAPC_CLPRIM_STALLED = 0x5b,
+ PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x5c,
+ PERF_PAPC_CLIPSM_IDLE = 0x5d,
+ PERF_PAPC_CLIPSM_BUSY = 0x5e,
+ PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x5f,
+ PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x60,
+ PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x61,
+ PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x62,
+ PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x63,
+ PERF_PAPC_CLIPGA_IDLE = 0x64,
+ PERF_PAPC_CLIPGA_BUSY = 0x65,
+ PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x66,
+ PERF_PAPC_CLIPGA_STALLED = 0x67,
+ PERF_PAPC_CLIP_IDLE = 0x68,
+ PERF_PAPC_CLIP_BUSY = 0x69,
+ PERF_PAPC_SU_IDLE = 0x6a,
+ PERF_PAPC_SU_BUSY = 0x6b,
+ PERF_PAPC_SU_STARVED_CLIP = 0x6c,
+ PERF_PAPC_SU_STALLED_SC = 0x6d,
+ PERF_PAPC_CL_DYN_SCLK_VLD = 0x6e,
+ PERF_PAPC_SU_DYN_SCLK_VLD = 0x6f,
+ PERF_PAPC_PA_REG_SCLK_VLD = 0x70,
+ PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 0x71,
+ PERF_PAPC_PASX_SE0_REQ = 0x72,
+ PERF_PAPC_PASX_SE1_REQ = 0x73,
+ PERF_PAPC_PASX_SE0_FIRST_VECTOR = 0x74,
+ PERF_PAPC_PASX_SE0_SECOND_VECTOR = 0x75,
+ PERF_PAPC_PASX_SE1_FIRST_VECTOR = 0x76,
+ PERF_PAPC_PASX_SE1_SECOND_VECTOR = 0x77,
+ PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x78,
+ PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x79,
+ PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 0x7a,
+ PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x7b,
+ PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x7c,
+ PERF_PAPC_SU_SE01_OUTPUT_PRIM = 0x7d,
+ PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x7e,
+ PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x7f,
+ PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 0x80,
+ PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 0x81,
+ PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 0x82,
+ PERF_PAPC_SU_SE0_STALLED_SC = 0x83,
+ PERF_PAPC_SU_SE1_STALLED_SC = 0x84,
+ PERF_PAPC_SU_SE01_STALLED_SC = 0x85,
+ PERF_PAPC_CLSM_CLIPPING_PRIM = 0x86,
+ PERF_PAPC_SU_CULLED_PRIM = 0x87,
+ PERF_PAPC_SU_OUTPUT_EOPG = 0x88,
+ PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 0x89,
+ PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 0x8a,
+ PERF_PAPC_SU_SE2_OUTPUT_PRIM = 0x8b,
+ PERF_PAPC_SU_SE3_OUTPUT_PRIM = 0x8c,
+ PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 0x8d,
+ PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 0x8e,
+ PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 0x8f,
+ PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 0x90,
+ PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 0x91,
+ PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 0x92,
+ PERF_PAPC_SU_SE0_OUTPUT_EOPG = 0x93,
+ PERF_PAPC_SU_SE1_OUTPUT_EOPG = 0x94,
+ PERF_PAPC_SU_SE2_OUTPUT_EOPG = 0x95,
+ PERF_PAPC_SU_SE3_OUTPUT_EOPG = 0x96,
+ PERF_PAPC_SU_SE2_STALLED_SC = 0x97,
+ PERF_PAPC_SU_SE3_STALLED_SC = 0x98,
+} SU_PERFCNT_SEL;
+typedef enum SC_PERFCNT_SEL {
+ SC_SRPS_WINDOW_VALID = 0x0,
+ SC_PSSW_WINDOW_VALID = 0x1,
+ SC_TPQZ_WINDOW_VALID = 0x2,
+ SC_QZQP_WINDOW_VALID = 0x3,
+ SC_TRPK_WINDOW_VALID = 0x4,
+ SC_SRPS_WINDOW_VALID_BUSY = 0x5,
+ SC_PSSW_WINDOW_VALID_BUSY = 0x6,
+ SC_TPQZ_WINDOW_VALID_BUSY = 0x7,
+ SC_QZQP_WINDOW_VALID_BUSY = 0x8,
+ SC_TRPK_WINDOW_VALID_BUSY = 0x9,
+ SC_STARVED_BY_PA = 0xa,
+ SC_STALLED_BY_PRIMFIFO = 0xb,
+ SC_STALLED_BY_DB_TILE = 0xc,
+ SC_STARVED_BY_DB_TILE = 0xd,
+ SC_STALLED_BY_TILEORDERFIFO = 0xe,
+ SC_STALLED_BY_TILEFIFO = 0xf,
+ SC_STALLED_BY_DB_QUAD = 0x10,
+ SC_STARVED_BY_DB_QUAD = 0x11,
+ SC_STALLED_BY_QUADFIFO = 0x12,
+ SC_STALLED_BY_BCI = 0x13,
+ SC_STALLED_BY_SPI = 0x14,
+ SC_SCISSOR_DISCARD = 0x15,
+ SC_BB_DISCARD = 0x16,
+ SC_SUPERTILE_COUNT = 0x17,
+ SC_SUPERTILE_PER_PRIM_H0 = 0x18,
+ SC_SUPERTILE_PER_PRIM_H1 = 0x19,
+ SC_SUPERTILE_PER_PRIM_H2 = 0x1a,
+ SC_SUPERTILE_PER_PRIM_H3 = 0x1b,
+ SC_SUPERTILE_PER_PRIM_H4 = 0x1c,
+ SC_SUPERTILE_PER_PRIM_H5 = 0x1d,
+ SC_SUPERTILE_PER_PRIM_H6 = 0x1e,
+ SC_SUPERTILE_PER_PRIM_H7 = 0x1f,
+ SC_SUPERTILE_PER_PRIM_H8 = 0x20,
+ SC_SUPERTILE_PER_PRIM_H9 = 0x21,
+ SC_SUPERTILE_PER_PRIM_H10 = 0x22,
+ SC_SUPERTILE_PER_PRIM_H11 = 0x23,
+ SC_SUPERTILE_PER_PRIM_H12 = 0x24,
+ SC_SUPERTILE_PER_PRIM_H13 = 0x25,
+ SC_SUPERTILE_PER_PRIM_H14 = 0x26,
+ SC_SUPERTILE_PER_PRIM_H15 = 0x27,
+ SC_SUPERTILE_PER_PRIM_H16 = 0x28,
+ SC_TILE_PER_PRIM_H0 = 0x29,
+ SC_TILE_PER_PRIM_H1 = 0x2a,
+ SC_TILE_PER_PRIM_H2 = 0x2b,
+ SC_TILE_PER_PRIM_H3 = 0x2c,
+ SC_TILE_PER_PRIM_H4 = 0x2d,
+ SC_TILE_PER_PRIM_H5 = 0x2e,
+ SC_TILE_PER_PRIM_H6 = 0x2f,
+ SC_TILE_PER_PRIM_H7 = 0x30,
+ SC_TILE_PER_PRIM_H8 = 0x31,
+ SC_TILE_PER_PRIM_H9 = 0x32,
+ SC_TILE_PER_PRIM_H10 = 0x33,
+ SC_TILE_PER_PRIM_H11 = 0x34,
+ SC_TILE_PER_PRIM_H12 = 0x35,
+ SC_TILE_PER_PRIM_H13 = 0x36,
+ SC_TILE_PER_PRIM_H14 = 0x37,
+ SC_TILE_PER_PRIM_H15 = 0x38,
+ SC_TILE_PER_PRIM_H16 = 0x39,
+ SC_TILE_PER_SUPERTILE_H0 = 0x3a,
+ SC_TILE_PER_SUPERTILE_H1 = 0x3b,
+ SC_TILE_PER_SUPERTILE_H2 = 0x3c,
+ SC_TILE_PER_SUPERTILE_H3 = 0x3d,
+ SC_TILE_PER_SUPERTILE_H4 = 0x3e,
+ SC_TILE_PER_SUPERTILE_H5 = 0x3f,
+ SC_TILE_PER_SUPERTILE_H6 = 0x40,
+ SC_TILE_PER_SUPERTILE_H7 = 0x41,
+ SC_TILE_PER_SUPERTILE_H8 = 0x42,
+ SC_TILE_PER_SUPERTILE_H9 = 0x43,
+ SC_TILE_PER_SUPERTILE_H10 = 0x44,
+ SC_TILE_PER_SUPERTILE_H11 = 0x45,
+ SC_TILE_PER_SUPERTILE_H12 = 0x46,
+ SC_TILE_PER_SUPERTILE_H13 = 0x47,
+ SC_TILE_PER_SUPERTILE_H14 = 0x48,
+ SC_TILE_PER_SUPERTILE_H15 = 0x49,
+ SC_TILE_PER_SUPERTILE_H16 = 0x4a,
+ SC_TILE_PICKED_H1 = 0x4b,
+ SC_TILE_PICKED_H2 = 0x4c,
+ SC_TILE_PICKED_H3 = 0x4d,
+ SC_TILE_PICKED_H4 = 0x4e,
+ SC_QZ0_MULTI_GPU_TILE_DISCARD = 0x4f,
+ SC_QZ1_MULTI_GPU_TILE_DISCARD = 0x50,
+ SC_QZ2_MULTI_GPU_TILE_DISCARD = 0x51,
+ SC_QZ3_MULTI_GPU_TILE_DISCARD = 0x52,
+ SC_QZ0_TILE_COUNT = 0x53,
+ SC_QZ1_TILE_COUNT = 0x54,
+ SC_QZ2_TILE_COUNT = 0x55,
+ SC_QZ3_TILE_COUNT = 0x56,
+ SC_QZ0_TILE_COVERED_COUNT = 0x57,
+ SC_QZ1_TILE_COVERED_COUNT = 0x58,
+ SC_QZ2_TILE_COVERED_COUNT = 0x59,
+ SC_QZ3_TILE_COVERED_COUNT = 0x5a,
+ SC_QZ0_TILE_NOT_COVERED_COUNT = 0x5b,
+ SC_QZ1_TILE_NOT_COVERED_COUNT = 0x5c,
+ SC_QZ2_TILE_NOT_COVERED_COUNT = 0x5d,
+ SC_QZ3_TILE_NOT_COVERED_COUNT = 0x5e,
+ SC_QZ0_QUAD_PER_TILE_H0 = 0x5f,
+ SC_QZ0_QUAD_PER_TILE_H1 = 0x60,
+ SC_QZ0_QUAD_PER_TILE_H2 = 0x61,
+ SC_QZ0_QUAD_PER_TILE_H3 = 0x62,
+ SC_QZ0_QUAD_PER_TILE_H4 = 0x63,
+ SC_QZ0_QUAD_PER_TILE_H5 = 0x64,
+ SC_QZ0_QUAD_PER_TILE_H6 = 0x65,
+ SC_QZ0_QUAD_PER_TILE_H7 = 0x66,
+ SC_QZ0_QUAD_PER_TILE_H8 = 0x67,
+ SC_QZ0_QUAD_PER_TILE_H9 = 0x68,
+ SC_QZ0_QUAD_PER_TILE_H10 = 0x69,
+ SC_QZ0_QUAD_PER_TILE_H11 = 0x6a,
+ SC_QZ0_QUAD_PER_TILE_H12 = 0x6b,
+ SC_QZ0_QUAD_PER_TILE_H13 = 0x6c,
+ SC_QZ0_QUAD_PER_TILE_H14 = 0x6d,
+ SC_QZ0_QUAD_PER_TILE_H15 = 0x6e,
+ SC_QZ0_QUAD_PER_TILE_H16 = 0x6f,
+ SC_QZ1_QUAD_PER_TILE_H0 = 0x70,
+ SC_QZ1_QUAD_PER_TILE_H1 = 0x71,
+ SC_QZ1_QUAD_PER_TILE_H2 = 0x72,
+ SC_QZ1_QUAD_PER_TILE_H3 = 0x73,
+ SC_QZ1_QUAD_PER_TILE_H4 = 0x74,
+ SC_QZ1_QUAD_PER_TILE_H5 = 0x75,
+ SC_QZ1_QUAD_PER_TILE_H6 = 0x76,
+ SC_QZ1_QUAD_PER_TILE_H7 = 0x77,
+ SC_QZ1_QUAD_PER_TILE_H8 = 0x78,
+ SC_QZ1_QUAD_PER_TILE_H9 = 0x79,
+ SC_QZ1_QUAD_PER_TILE_H10 = 0x7a,
+ SC_QZ1_QUAD_PER_TILE_H11 = 0x7b,
+ SC_QZ1_QUAD_PER_TILE_H12 = 0x7c,
+ SC_QZ1_QUAD_PER_TILE_H13 = 0x7d,
+ SC_QZ1_QUAD_PER_TILE_H14 = 0x7e,
+ SC_QZ1_QUAD_PER_TILE_H15 = 0x7f,
+ SC_QZ1_QUAD_PER_TILE_H16 = 0x80,
+ SC_QZ2_QUAD_PER_TILE_H0 = 0x81,
+ SC_QZ2_QUAD_PER_TILE_H1 = 0x82,
+ SC_QZ2_QUAD_PER_TILE_H2 = 0x83,
+ SC_QZ2_QUAD_PER_TILE_H3 = 0x84,
+ SC_QZ2_QUAD_PER_TILE_H4 = 0x85,
+ SC_QZ2_QUAD_PER_TILE_H5 = 0x86,
+ SC_QZ2_QUAD_PER_TILE_H6 = 0x87,
+ SC_QZ2_QUAD_PER_TILE_H7 = 0x88,
+ SC_QZ2_QUAD_PER_TILE_H8 = 0x89,
+ SC_QZ2_QUAD_PER_TILE_H9 = 0x8a,
+ SC_QZ2_QUAD_PER_TILE_H10 = 0x8b,
+ SC_QZ2_QUAD_PER_TILE_H11 = 0x8c,
+ SC_QZ2_QUAD_PER_TILE_H12 = 0x8d,
+ SC_QZ2_QUAD_PER_TILE_H13 = 0x8e,
+ SC_QZ2_QUAD_PER_TILE_H14 = 0x8f,
+ SC_QZ2_QUAD_PER_TILE_H15 = 0x90,
+ SC_QZ2_QUAD_PER_TILE_H16 = 0x91,
+ SC_QZ3_QUAD_PER_TILE_H0 = 0x92,
+ SC_QZ3_QUAD_PER_TILE_H1 = 0x93,
+ SC_QZ3_QUAD_PER_TILE_H2 = 0x94,
+ SC_QZ3_QUAD_PER_TILE_H3 = 0x95,
+ SC_QZ3_QUAD_PER_TILE_H4 = 0x96,
+ SC_QZ3_QUAD_PER_TILE_H5 = 0x97,
+ SC_QZ3_QUAD_PER_TILE_H6 = 0x98,
+ SC_QZ3_QUAD_PER_TILE_H7 = 0x99,
+ SC_QZ3_QUAD_PER_TILE_H8 = 0x9a,
+ SC_QZ3_QUAD_PER_TILE_H9 = 0x9b,
+ SC_QZ3_QUAD_PER_TILE_H10 = 0x9c,
+ SC_QZ3_QUAD_PER_TILE_H11 = 0x9d,
+ SC_QZ3_QUAD_PER_TILE_H12 = 0x9e,
+ SC_QZ3_QUAD_PER_TILE_H13 = 0x9f,
+ SC_QZ3_QUAD_PER_TILE_H14 = 0xa0,
+ SC_QZ3_QUAD_PER_TILE_H15 = 0xa1,
+ SC_QZ3_QUAD_PER_TILE_H16 = 0xa2,
+ SC_QZ0_QUAD_COUNT = 0xa3,
+ SC_QZ1_QUAD_COUNT = 0xa4,
+ SC_QZ2_QUAD_COUNT = 0xa5,
+ SC_QZ3_QUAD_COUNT = 0xa6,
+ SC_P0_HIZ_TILE_COUNT = 0xa7,
+ SC_P1_HIZ_TILE_COUNT = 0xa8,
+ SC_P2_HIZ_TILE_COUNT = 0xa9,
+ SC_P3_HIZ_TILE_COUNT = 0xaa,
+ SC_P0_HIZ_QUAD_PER_TILE_H0 = 0xab,
+ SC_P0_HIZ_QUAD_PER_TILE_H1 = 0xac,
+ SC_P0_HIZ_QUAD_PER_TILE_H2 = 0xad,
+ SC_P0_HIZ_QUAD_PER_TILE_H3 = 0xae,
+ SC_P0_HIZ_QUAD_PER_TILE_H4 = 0xaf,
+ SC_P0_HIZ_QUAD_PER_TILE_H5 = 0xb0,
+ SC_P0_HIZ_QUAD_PER_TILE_H6 = 0xb1,
+ SC_P0_HIZ_QUAD_PER_TILE_H7 = 0xb2,
+ SC_P0_HIZ_QUAD_PER_TILE_H8 = 0xb3,
+ SC_P0_HIZ_QUAD_PER_TILE_H9 = 0xb4,
+ SC_P0_HIZ_QUAD_PER_TILE_H10 = 0xb5,
+ SC_P0_HIZ_QUAD_PER_TILE_H11 = 0xb6,
+ SC_P0_HIZ_QUAD_PER_TILE_H12 = 0xb7,
+ SC_P0_HIZ_QUAD_PER_TILE_H13 = 0xb8,
+ SC_P0_HIZ_QUAD_PER_TILE_H14 = 0xb9,
+ SC_P0_HIZ_QUAD_PER_TILE_H15 = 0xba,
+ SC_P0_HIZ_QUAD_PER_TILE_H16 = 0xbb,
+ SC_P1_HIZ_QUAD_PER_TILE_H0 = 0xbc,
+ SC_P1_HIZ_QUAD_PER_TILE_H1 = 0xbd,
+ SC_P1_HIZ_QUAD_PER_TILE_H2 = 0xbe,
+ SC_P1_HIZ_QUAD_PER_TILE_H3 = 0xbf,
+ SC_P1_HIZ_QUAD_PER_TILE_H4 = 0xc0,
+ SC_P1_HIZ_QUAD_PER_TILE_H5 = 0xc1,
+ SC_P1_HIZ_QUAD_PER_TILE_H6 = 0xc2,
+ SC_P1_HIZ_QUAD_PER_TILE_H7 = 0xc3,
+ SC_P1_HIZ_QUAD_PER_TILE_H8 = 0xc4,
+ SC_P1_HIZ_QUAD_PER_TILE_H9 = 0xc5,
+ SC_P1_HIZ_QUAD_PER_TILE_H10 = 0xc6,
+ SC_P1_HIZ_QUAD_PER_TILE_H11 = 0xc7,
+ SC_P1_HIZ_QUAD_PER_TILE_H12 = 0xc8,
+ SC_P1_HIZ_QUAD_PER_TILE_H13 = 0xc9,
+ SC_P1_HIZ_QUAD_PER_TILE_H14 = 0xca,
+ SC_P1_HIZ_QUAD_PER_TILE_H15 = 0xcb,
+ SC_P1_HIZ_QUAD_PER_TILE_H16 = 0xcc,
+ SC_P2_HIZ_QUAD_PER_TILE_H0 = 0xcd,
+ SC_P2_HIZ_QUAD_PER_TILE_H1 = 0xce,
+ SC_P2_HIZ_QUAD_PER_TILE_H2 = 0xcf,
+ SC_P2_HIZ_QUAD_PER_TILE_H3 = 0xd0,
+ SC_P2_HIZ_QUAD_PER_TILE_H4 = 0xd1,
+ SC_P2_HIZ_QUAD_PER_TILE_H5 = 0xd2,
+ SC_P2_HIZ_QUAD_PER_TILE_H6 = 0xd3,
+ SC_P2_HIZ_QUAD_PER_TILE_H7 = 0xd4,
+ SC_P2_HIZ_QUAD_PER_TILE_H8 = 0xd5,
+ SC_P2_HIZ_QUAD_PER_TILE_H9 = 0xd6,
+ SC_P2_HIZ_QUAD_PER_TILE_H10 = 0xd7,
+ SC_P2_HIZ_QUAD_PER_TILE_H11 = 0xd8,
+ SC_P2_HIZ_QUAD_PER_TILE_H12 = 0xd9,
+ SC_P2_HIZ_QUAD_PER_TILE_H13 = 0xda,
+ SC_P2_HIZ_QUAD_PER_TILE_H14 = 0xdb,
+ SC_P2_HIZ_QUAD_PER_TILE_H15 = 0xdc,
+ SC_P2_HIZ_QUAD_PER_TILE_H16 = 0xdd,
+ SC_P3_HIZ_QUAD_PER_TILE_H0 = 0xde,
+ SC_P3_HIZ_QUAD_PER_TILE_H1 = 0xdf,
+ SC_P3_HIZ_QUAD_PER_TILE_H2 = 0xe0,
+ SC_P3_HIZ_QUAD_PER_TILE_H3 = 0xe1,
+ SC_P3_HIZ_QUAD_PER_TILE_H4 = 0xe2,
+ SC_P3_HIZ_QUAD_PER_TILE_H5 = 0xe3,
+ SC_P3_HIZ_QUAD_PER_TILE_H6 = 0xe4,
+ SC_P3_HIZ_QUAD_PER_TILE_H7 = 0xe5,
+ SC_P3_HIZ_QUAD_PER_TILE_H8 = 0xe6,
+ SC_P3_HIZ_QUAD_PER_TILE_H9 = 0xe7,
+ SC_P3_HIZ_QUAD_PER_TILE_H10 = 0xe8,
+ SC_P3_HIZ_QUAD_PER_TILE_H11 = 0xe9,
+ SC_P3_HIZ_QUAD_PER_TILE_H12 = 0xea,
+ SC_P3_HIZ_QUAD_PER_TILE_H13 = 0xeb,
+ SC_P3_HIZ_QUAD_PER_TILE_H14 = 0xec,
+ SC_P3_HIZ_QUAD_PER_TILE_H15 = 0xed,
+ SC_P3_HIZ_QUAD_PER_TILE_H16 = 0xee,
+ SC_P0_HIZ_QUAD_COUNT = 0xef,
+ SC_P1_HIZ_QUAD_COUNT = 0xf0,
+ SC_P2_HIZ_QUAD_COUNT = 0xf1,
+ SC_P3_HIZ_QUAD_COUNT = 0xf2,
+ SC_P0_DETAIL_QUAD_COUNT = 0xf3,
+ SC_P1_DETAIL_QUAD_COUNT = 0xf4,
+ SC_P2_DETAIL_QUAD_COUNT = 0xf5,
+ SC_P3_DETAIL_QUAD_COUNT = 0xf6,
+ SC_P0_DETAIL_QUAD_WITH_1_PIX = 0xf7,
+ SC_P0_DETAIL_QUAD_WITH_2_PIX = 0xf8,
+ SC_P0_DETAIL_QUAD_WITH_3_PIX = 0xf9,
+ SC_P0_DETAIL_QUAD_WITH_4_PIX = 0xfa,
+ SC_P1_DETAIL_QUAD_WITH_1_PIX = 0xfb,
+ SC_P1_DETAIL_QUAD_WITH_2_PIX = 0xfc,
+ SC_P1_DETAIL_QUAD_WITH_3_PIX = 0xfd,
+ SC_P1_DETAIL_QUAD_WITH_4_PIX = 0xfe,
+ SC_P2_DETAIL_QUAD_WITH_1_PIX = 0xff,
+ SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x100,
+ SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x101,
+ SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x102,
+ SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x103,
+ SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x104,
+ SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x105,
+ SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x106,
+ SC_EARLYZ_QUAD_COUNT = 0x107,
+ SC_EARLYZ_QUAD_WITH_1_PIX = 0x108,
+ SC_EARLYZ_QUAD_WITH_2_PIX = 0x109,
+ SC_EARLYZ_QUAD_WITH_3_PIX = 0x10a,
+ SC_EARLYZ_QUAD_WITH_4_PIX = 0x10b,
+ SC_PKR_QUAD_PER_ROW_H1 = 0x10c,
+ SC_PKR_QUAD_PER_ROW_H2 = 0x10d,
+ SC_PKR_QUAD_PER_ROW_H3 = 0x10e,
+ SC_PKR_QUAD_PER_ROW_H4 = 0x10f,
+ SC_PKR_END_OF_VECTOR = 0x110,
+ SC_PKR_CONTROL_XFER = 0x111,
+ SC_PKR_DBHANG_FORCE_EOV = 0x112,
+ SC_REG_SCLK_BUSY = 0x113,
+ SC_GRP0_DYN_SCLK_BUSY = 0x114,
+ SC_GRP1_DYN_SCLK_BUSY = 0x115,
+ SC_GRP2_DYN_SCLK_BUSY = 0x116,
+ SC_GRP3_DYN_SCLK_BUSY = 0x117,
+ SC_GRP4_DYN_SCLK_BUSY = 0x118,
+ SC_PA0_SC_DATA_FIFO_RD = 0x119,
+ SC_PA0_SC_DATA_FIFO_WE = 0x11a,
+ SC_PA1_SC_DATA_FIFO_RD = 0x11b,
+ SC_PA1_SC_DATA_FIFO_WE = 0x11c,
+ SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x11d,
+ SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x11e,
+ SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x11f,
+ SC_PS_ARB_STALLED_FROM_BELOW = 0x120,
+ SC_PS_ARB_STARVED_FROM_ABOVE = 0x121,
+ SC_PS_ARB_SC_BUSY = 0x122,
+ SC_PS_ARB_PA_SC_BUSY = 0x123,
+ SC_PA2_SC_DATA_FIFO_RD = 0x124,
+ SC_PA2_SC_DATA_FIFO_WE = 0x125,
+ SC_PA3_SC_DATA_FIFO_RD = 0x126,
+ SC_PA3_SC_DATA_FIFO_WE = 0x127,
+ SC_PA_SC_DEALLOC_0_0_WE = 0x128,
+ SC_PA_SC_DEALLOC_0_1_WE = 0x129,
+ SC_PA_SC_DEALLOC_1_0_WE = 0x12a,
+ SC_PA_SC_DEALLOC_1_1_WE = 0x12b,
+ SC_PA_SC_DEALLOC_2_0_WE = 0x12c,
+ SC_PA_SC_DEALLOC_2_1_WE = 0x12d,
+ SC_PA_SC_DEALLOC_3_0_WE = 0x12e,
+ SC_PA_SC_DEALLOC_3_1_WE = 0x12f,
+ SC_PA0_SC_EOP_WE = 0x130,
+ SC_PA0_SC_EOPG_WE = 0x131,
+ SC_PA0_SC_EVENT_WE = 0x132,
+ SC_PA1_SC_EOP_WE = 0x133,
+ SC_PA1_SC_EOPG_WE = 0x134,
+ SC_PA1_SC_EVENT_WE = 0x135,
+ SC_PA2_SC_EOP_WE = 0x136,
+ SC_PA2_SC_EOPG_WE = 0x137,
+ SC_PA2_SC_EVENT_WE = 0x138,
+ SC_PA3_SC_EOP_WE = 0x139,
+ SC_PA3_SC_EOPG_WE = 0x13a,
+ SC_PA3_SC_EVENT_WE = 0x13b,
+ SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 0x13c,
+ SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 0x13d,
+ SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 0x13e,
+ SC_PS_ARB_EOP_POP_SYNC_POP = 0x13f,
+ SC_PS_ARB_EVENT_SYNC_POP = 0x140,
+ SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 0x141,
+ SC_PA0_SC_FPOV_WE = 0x142,
+ SC_PA1_SC_FPOV_WE = 0x143,
+ SC_PA2_SC_FPOV_WE = 0x144,
+ SC_PA3_SC_FPOV_WE = 0x145,
+ SC_PA0_SC_LPOV_WE = 0x146,
+ SC_PA1_SC_LPOV_WE = 0x147,
+ SC_PA2_SC_LPOV_WE = 0x148,
+ SC_PA3_SC_LPOV_WE = 0x149,
+ SC_SC_SPI_DEALLOC_0_0 = 0x14a,
+ SC_SC_SPI_DEALLOC_0_1 = 0x14b,
+ SC_SC_SPI_DEALLOC_0_2 = 0x14c,
+ SC_SC_SPI_DEALLOC_1_0 = 0x14d,
+ SC_SC_SPI_DEALLOC_1_1 = 0x14e,
+ SC_SC_SPI_DEALLOC_1_2 = 0x14f,
+ SC_SC_SPI_DEALLOC_2_0 = 0x150,
+ SC_SC_SPI_DEALLOC_2_1 = 0x151,
+ SC_SC_SPI_DEALLOC_2_2 = 0x152,
+ SC_SC_SPI_DEALLOC_3_0 = 0x153,
+ SC_SC_SPI_DEALLOC_3_1 = 0x154,
+ SC_SC_SPI_DEALLOC_3_2 = 0x155,
+ SC_SC_SPI_FPOV_0 = 0x156,
+ SC_SC_SPI_FPOV_1 = 0x157,
+ SC_SC_SPI_FPOV_2 = 0x158,
+ SC_SC_SPI_FPOV_3 = 0x159,
+ SC_SC_SPI_EVENT = 0x15a,
+ SC_PS_TS_EVENT_FIFO_PUSH = 0x15b,
+ SC_PS_TS_EVENT_FIFO_POP = 0x15c,
+ SC_PS_CTX_DONE_FIFO_PUSH = 0x15d,
+ SC_PS_CTX_DONE_FIFO_POP = 0x15e,
+ SC_MULTICYCLE_BUBBLE_FREEZE = 0x15f,
+ SC_EOP_SYNC_WINDOW = 0x160,
+ SC_PA0_SC_NULL_WE = 0x161,
+ SC_PA0_SC_NULL_DEALLOC_WE = 0x162,
+ SC_PA0_SC_DATA_FIFO_EOPG_RD = 0x163,
+ SC_PA0_SC_DATA_FIFO_EOP_RD = 0x164,
+ SC_PA0_SC_DEALLOC_0_RD = 0x165,
+ SC_PA0_SC_DEALLOC_1_RD = 0x166,
+ SC_PA1_SC_DATA_FIFO_EOPG_RD = 0x167,
+ SC_PA1_SC_DATA_FIFO_EOP_RD = 0x168,
+ SC_PA1_SC_DEALLOC_0_RD = 0x169,
+ SC_PA1_SC_DEALLOC_1_RD = 0x16a,
+ SC_PA1_SC_NULL_WE = 0x16b,
+ SC_PA1_SC_NULL_DEALLOC_WE = 0x16c,
+ SC_PA2_SC_DATA_FIFO_EOPG_RD = 0x16d,
+ SC_PA2_SC_DATA_FIFO_EOP_RD = 0x16e,
+ SC_PA2_SC_DEALLOC_0_RD = 0x16f,
+ SC_PA2_SC_DEALLOC_1_RD = 0x170,
+ SC_PA2_SC_NULL_WE = 0x171,
+ SC_PA2_SC_NULL_DEALLOC_WE = 0x172,
+ SC_PA3_SC_DATA_FIFO_EOPG_RD = 0x173,
+ SC_PA3_SC_DATA_FIFO_EOP_RD = 0x174,
+ SC_PA3_SC_DEALLOC_0_RD = 0x175,
+ SC_PA3_SC_DEALLOC_1_RD = 0x176,
+ SC_PA3_SC_NULL_WE = 0x177,
+ SC_PA3_SC_NULL_DEALLOC_WE = 0x178,
+ SC_PS_PA0_SC_FIFO_EMPTY = 0x179,
+ SC_PS_PA0_SC_FIFO_FULL = 0x17a,
+ SC_PA0_PS_DATA_SEND = 0x17b,
+ SC_PS_PA1_SC_FIFO_EMPTY = 0x17c,
+ SC_PS_PA1_SC_FIFO_FULL = 0x17d,
+ SC_PA1_PS_DATA_SEND = 0x17e,
+ SC_PS_PA2_SC_FIFO_EMPTY = 0x17f,
+ SC_PS_PA2_SC_FIFO_FULL = 0x180,
+ SC_PA2_PS_DATA_SEND = 0x181,
+ SC_PS_PA3_SC_FIFO_EMPTY = 0x182,
+ SC_PS_PA3_SC_FIFO_FULL = 0x183,
+ SC_PA3_PS_DATA_SEND = 0x184,
+ SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x185,
+ SC_BUSY_CNT_NOT_ZERO = 0x186,
+ SC_BM_BUSY = 0x187,
+ SC_BACKEND_BUSY = 0x188,
+ SC_SCF_SCB_INTERFACE_BUSY = 0x189,
+ SC_SCB_BUSY = 0x18a,
+} SC_PERFCNT_SEL;
+typedef enum SePairXsel {
+ RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x0,
+ RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x1,
+ RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x2,
+ RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x3,
+} SePairXsel;
+typedef enum SePairYsel {
+ RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x0,
+ RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x1,
+ RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x2,
+ RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x3,
+} SePairYsel;
+typedef enum SePairMap {
+ RASTER_CONFIG_SE_PAIR_MAP_0 = 0x0,
+ RASTER_CONFIG_SE_PAIR_MAP_1 = 0x1,
+ RASTER_CONFIG_SE_PAIR_MAP_2 = 0x2,
+ RASTER_CONFIG_SE_PAIR_MAP_3 = 0x3,
+} SePairMap;
+typedef enum SeXsel {
+ RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x0,
+ RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x1,
+ RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x2,
+ RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x3,
+} SeXsel;
+typedef enum SeYsel {
+ RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x0,
+ RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x1,
+ RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x2,
+ RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x3,
+} SeYsel;
+typedef enum SeMap {
+ RASTER_CONFIG_SE_MAP_0 = 0x0,
+ RASTER_CONFIG_SE_MAP_1 = 0x1,
+ RASTER_CONFIG_SE_MAP_2 = 0x2,
+ RASTER_CONFIG_SE_MAP_3 = 0x3,
+} SeMap;
+typedef enum ScXsel {
+ RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x0,
+ RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x1,
+ RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x2,
+ RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x3,
+} ScXsel;
+typedef enum ScYsel {
+ RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x0,
+ RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x1,
+ RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x2,
+ RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x3,
+} ScYsel;
+typedef enum ScMap {
+ RASTER_CONFIG_SC_MAP_0 = 0x0,
+ RASTER_CONFIG_SC_MAP_1 = 0x1,
+ RASTER_CONFIG_SC_MAP_2 = 0x2,
+ RASTER_CONFIG_SC_MAP_3 = 0x3,
+} ScMap;
+typedef enum PkrXsel2 {
+ RASTER_CONFIG_PKR_XSEL2_0 = 0x0,
+ RASTER_CONFIG_PKR_XSEL2_1 = 0x1,
+ RASTER_CONFIG_PKR_XSEL2_2 = 0x2,
+ RASTER_CONFIG_PKR_XSEL2_3 = 0x3,
+} PkrXsel2;
+typedef enum PkrXsel {
+ RASTER_CONFIG_PKR_XSEL_0 = 0x0,
+ RASTER_CONFIG_PKR_XSEL_1 = 0x1,
+ RASTER_CONFIG_PKR_XSEL_2 = 0x2,
+ RASTER_CONFIG_PKR_XSEL_3 = 0x3,
+} PkrXsel;
+typedef enum PkrYsel {
+ RASTER_CONFIG_PKR_YSEL_0 = 0x0,
+ RASTER_CONFIG_PKR_YSEL_1 = 0x1,
+ RASTER_CONFIG_PKR_YSEL_2 = 0x2,
+ RASTER_CONFIG_PKR_YSEL_3 = 0x3,
+} PkrYsel;
+typedef enum PkrMap {
+ RASTER_CONFIG_PKR_MAP_0 = 0x0,
+ RASTER_CONFIG_PKR_MAP_1 = 0x1,
+ RASTER_CONFIG_PKR_MAP_2 = 0x2,
+ RASTER_CONFIG_PKR_MAP_3 = 0x3,
+} PkrMap;
+typedef enum RbXsel {
+ RASTER_CONFIG_RB_XSEL_0 = 0x0,
+ RASTER_CONFIG_RB_XSEL_1 = 0x1,
+} RbXsel;
+typedef enum RbYsel {
+ RASTER_CONFIG_RB_YSEL_0 = 0x0,
+ RASTER_CONFIG_RB_YSEL_1 = 0x1,
+} RbYsel;
+typedef enum RbXsel2 {
+ RASTER_CONFIG_RB_XSEL2_0 = 0x0,
+ RASTER_CONFIG_RB_XSEL2_1 = 0x1,
+ RASTER_CONFIG_RB_XSEL2_2 = 0x2,
+ RASTER_CONFIG_RB_XSEL2_3 = 0x3,
+} RbXsel2;
+typedef enum RbMap {
+ RASTER_CONFIG_RB_MAP_0 = 0x0,
+ RASTER_CONFIG_RB_MAP_1 = 0x1,
+ RASTER_CONFIG_RB_MAP_2 = 0x2,
+ RASTER_CONFIG_RB_MAP_3 = 0x3,
+} RbMap;
+typedef enum CSDATA_TYPE {
+ CSDATA_TYPE_TG = 0x0,
+ CSDATA_TYPE_STATE = 0x1,
+ CSDATA_TYPE_EVENT = 0x2,
+ CSDATA_TYPE_PRIVATE = 0x3,
+} CSDATA_TYPE;
+#define CSDATA_TYPE_WIDTH 0x2
+#define CSDATA_ADDR_WIDTH 0x7
+#define CSDATA_DATA_WIDTH 0x20
+typedef enum SPI_SAMPLE_CNTL {
+ CENTROIDS_ONLY = 0x0,
+ CENTERS_ONLY = 0x1,
+ CENTROIDS_AND_CENTERS = 0x2,
+ UNDEF = 0x3,
+} SPI_SAMPLE_CNTL;
+typedef enum SPI_FOG_MODE {
+ SPI_FOG_NONE = 0x0,
+ SPI_FOG_EXP = 0x1,
+ SPI_FOG_EXP2 = 0x2,
+ SPI_FOG_LINEAR = 0x3,
+} SPI_FOG_MODE;
+typedef enum SPI_PNT_SPRITE_OVERRIDE {
+ SPI_PNT_SPRITE_SEL_0 = 0x0,
+ SPI_PNT_SPRITE_SEL_1 = 0x1,
+ SPI_PNT_SPRITE_SEL_S = 0x2,
+ SPI_PNT_SPRITE_SEL_T = 0x3,
+ SPI_PNT_SPRITE_SEL_NONE = 0x4,
+} SPI_PNT_SPRITE_OVERRIDE;
+typedef enum SPI_PERFCNT_SEL {
+ SPI_PERF_VS_WINDOW_VALID = 0x0,
+ SPI_PERF_VS_BUSY = 0x1,
+ SPI_PERF_VS_FIRST_WAVE = 0x2,
+ SPI_PERF_VS_LAST_WAVE = 0x3,
+ SPI_PERF_VS_LSHS_DEALLOC = 0x4,
+ SPI_PERF_VS_PC_STALL = 0x5,
+ SPI_PERF_VS_POS0_STALL = 0x6,
+ SPI_PERF_VS_POS1_STALL = 0x7,
+ SPI_PERF_VS_CRAWLER_STALL = 0x8,
+ SPI_PERF_VS_EVENT_WAVE = 0x9,
+ SPI_PERF_VS_WAVE = 0xa,
+ SPI_PERF_VS_PERS_UPD_FULL0 = 0xb,
+ SPI_PERF_VS_PERS_UPD_FULL1 = 0xc,
+ SPI_PERF_VS_LATE_ALLOC_FULL = 0xd,
+ SPI_PERF_VS_FIRST_SUBGRP = 0xe,
+ SPI_PERF_VS_LAST_SUBGRP = 0xf,
+ SPI_PERF_GS_WINDOW_VALID = 0x10,
+ SPI_PERF_GS_BUSY = 0x11,
+ SPI_PERF_GS_CRAWLER_STALL = 0x12,
+ SPI_PERF_GS_EVENT_WAVE = 0x13,
+ SPI_PERF_GS_WAVE = 0x14,
+ SPI_PERF_GS_PERS_UPD_FULL0 = 0x15,
+ SPI_PERF_GS_PERS_UPD_FULL1 = 0x16,
+ SPI_PERF_GS_FIRST_SUBGRP = 0x17,
+ SPI_PERF_GS_LAST_SUBGRP = 0x18,
+ SPI_PERF_ES_WINDOW_VALID = 0x19,
+ SPI_PERF_ES_BUSY = 0x1a,
+ SPI_PERF_ES_CRAWLER_STALL = 0x1b,
+ SPI_PERF_ES_FIRST_WAVE = 0x1c,
+ SPI_PERF_ES_LAST_WAVE = 0x1d,
+ SPI_PERF_ES_LSHS_DEALLOC = 0x1e,
+ SPI_PERF_ES_EVENT_WAVE = 0x1f,
+ SPI_PERF_ES_WAVE = 0x20,
+ SPI_PERF_ES_PERS_UPD_FULL0 = 0x21,
+ SPI_PERF_ES_PERS_UPD_FULL1 = 0x22,
+ SPI_PERF_ES_FIRST_SUBGRP = 0x23,
+ SPI_PERF_ES_LAST_SUBGRP = 0x24,
+ SPI_PERF_HS_WINDOW_VALID = 0x25,
+ SPI_PERF_HS_BUSY = 0x26,
+ SPI_PERF_HS_CRAWLER_STALL = 0x27,
+ SPI_PERF_HS_FIRST_WAVE = 0x28,
+ SPI_PERF_HS_LAST_WAVE = 0x29,
+ SPI_PERF_HS_LSHS_DEALLOC = 0x2a,
+ SPI_PERF_HS_EVENT_WAVE = 0x2b,
+ SPI_PERF_HS_WAVE = 0x2c,
+ SPI_PERF_HS_PERS_UPD_FULL0 = 0x2d,
+ SPI_PERF_HS_PERS_UPD_FULL1 = 0x2e,
+ SPI_PERF_LS_WINDOW_VALID = 0x2f,
+ SPI_PERF_LS_BUSY = 0x30,
+ SPI_PERF_LS_CRAWLER_STALL = 0x31,
+ SPI_PERF_LS_FIRST_WAVE = 0x32,
+ SPI_PERF_LS_LAST_WAVE = 0x33,
+ SPI_PERF_OFFCHIP_LDS_STALL_LS = 0x34,
+ SPI_PERF_LS_EVENT_WAVE = 0x35,
+ SPI_PERF_LS_WAVE = 0x36,
+ SPI_PERF_LS_PERS_UPD_FULL0 = 0x37,
+ SPI_PERF_LS_PERS_UPD_FULL1 = 0x38,
+ SPI_PERF_CSG_WINDOW_VALID = 0x39,
+ SPI_PERF_CSG_BUSY = 0x3a,
+ SPI_PERF_CSG_NUM_THREADGROUPS = 0x3b,
+ SPI_PERF_CSG_CRAWLER_STALL = 0x3c,
+ SPI_PERF_CSG_EVENT_WAVE = 0x3d,
+ SPI_PERF_CSG_WAVE = 0x3e,
+ SPI_PERF_CSN_WINDOW_VALID = 0x3f,
+ SPI_PERF_CSN_BUSY = 0x40,
+ SPI_PERF_CSN_NUM_THREADGROUPS = 0x41,
+ SPI_PERF_CSN_CRAWLER_STALL = 0x42,
+ SPI_PERF_CSN_EVENT_WAVE = 0x43,
+ SPI_PERF_CSN_WAVE = 0x44,
+ SPI_PERF_PS_CTL_WINDOW_VALID = 0x45,
+ SPI_PERF_PS_CTL_BUSY = 0x46,
+ SPI_PERF_PS_CTL_ACTIVE = 0x47,
+ SPI_PERF_PS_CTL_DEALLOC_BIN0 = 0x48,
+ SPI_PERF_PS_CTL_FPOS_BIN1_STALL = 0x49,
+ SPI_PERF_PS_CTL_EVENT_WAVE = 0x4a,
+ SPI_PERF_PS_CTL_WAVE = 0x4b,
+ SPI_PERF_PS_CTL_OPT_WAVE = 0x4c,
+ SPI_PERF_PS_CTL_PASS_BIN0 = 0x4d,
+ SPI_PERF_PS_CTL_PASS_BIN1 = 0x4e,
+ SPI_PERF_PS_CTL_FPOS_BIN2 = 0x4f,
+ SPI_PERF_PS_CTL_PRIM_BIN0 = 0x50,
+ SPI_PERF_PS_CTL_PRIM_BIN1 = 0x51,
+ SPI_PERF_PS_CTL_CNF_BIN2 = 0x52,
+ SPI_PERF_PS_CTL_CNF_BIN3 = 0x53,
+ SPI_PERF_PS_CTL_CRAWLER_STALL = 0x54,
+ SPI_PERF_PS_CTL_LDS_RES_FULL = 0x55,
+ SPI_PERF_PS_PERS_UPD_FULL0 = 0x56,
+ SPI_PERF_PS_PERS_UPD_FULL1 = 0x57,
+ SPI_PERF_PIX_ALLOC_PEND_CNT = 0x58,
+ SPI_PERF_PIX_ALLOC_SCB_STALL = 0x59,
+ SPI_PERF_PIX_ALLOC_DB0_STALL = 0x5a,
+ SPI_PERF_PIX_ALLOC_DB1_STALL = 0x5b,
+ SPI_PERF_PIX_ALLOC_DB2_STALL = 0x5c,
+ SPI_PERF_PIX_ALLOC_DB3_STALL = 0x5d,
+ SPI_PERF_LDS0_PC_VALID = 0x5e,
+ SPI_PERF_LDS1_PC_VALID = 0x5f,
+ SPI_PERF_RA_PIPE_REQ_BIN2 = 0x60,
+ SPI_PERF_RA_TASK_REQ_BIN3 = 0x61,
+ SPI_PERF_RA_WR_CTL_FULL = 0x62,
+ SPI_PERF_RA_REQ_NO_ALLOC = 0x63,
+ SPI_PERF_RA_REQ_NO_ALLOC_PS = 0x64,
+ SPI_PERF_RA_REQ_NO_ALLOC_VS = 0x65,
+ SPI_PERF_RA_REQ_NO_ALLOC_GS = 0x66,
+ SPI_PERF_RA_REQ_NO_ALLOC_ES = 0x67,
+ SPI_PERF_RA_REQ_NO_ALLOC_HS = 0x68,
+ SPI_PERF_RA_REQ_NO_ALLOC_LS = 0x69,
+ SPI_PERF_RA_REQ_NO_ALLOC_CSG = 0x6a,
+ SPI_PERF_RA_REQ_NO_ALLOC_CSN = 0x6b,
+ SPI_PERF_RA_RES_STALL_PS = 0x6c,
+ SPI_PERF_RA_RES_STALL_VS = 0x6d,
+ SPI_PERF_RA_RES_STALL_GS = 0x6e,
+ SPI_PERF_RA_RES_STALL_ES = 0x6f,
+ SPI_PERF_RA_RES_STALL_HS = 0x70,
+ SPI_PERF_RA_RES_STALL_LS = 0x71,
+ SPI_PERF_RA_RES_STALL_CSG = 0x72,
+ SPI_PERF_RA_RES_STALL_CSN = 0x73,
+ SPI_PERF_RA_TMP_STALL_PS = 0x74,
+ SPI_PERF_RA_TMP_STALL_VS = 0x75,
+ SPI_PERF_RA_TMP_STALL_GS = 0x76,
+ SPI_PERF_RA_TMP_STALL_ES = 0x77,
+ SPI_PERF_RA_TMP_STALL_HS = 0x78,
+ SPI_PERF_RA_TMP_STALL_LS = 0x79,
+ SPI_PERF_RA_TMP_STALL_CSG = 0x7a,
+ SPI_PERF_RA_TMP_STALL_CSN = 0x7b,
+ SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x7c,
+ SPI_PERF_RA_WAVE_SIMD_FULL_VS = 0x7d,
+ SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x7e,
+ SPI_PERF_RA_WAVE_SIMD_FULL_ES = 0x7f,
+ SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x80,
+ SPI_PERF_RA_WAVE_SIMD_FULL_LS = 0x81,
+ SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 0x82,
+ SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 0x83,
+ SPI_PERF_RA_VGPR_SIMD_FULL_PS = 0x84,
+ SPI_PERF_RA_VGPR_SIMD_FULL_VS = 0x85,
+ SPI_PERF_RA_VGPR_SIMD_FULL_GS = 0x86,
+ SPI_PERF_RA_VGPR_SIMD_FULL_ES = 0x87,
+ SPI_PERF_RA_VGPR_SIMD_FULL_HS = 0x88,
+ SPI_PERF_RA_VGPR_SIMD_FULL_LS = 0x89,
+ SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 0x8a,
+ SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 0x8b,
+ SPI_PERF_RA_SGPR_SIMD_FULL_PS = 0x8c,
+ SPI_PERF_RA_SGPR_SIMD_FULL_VS = 0x8d,
+ SPI_PERF_RA_SGPR_SIMD_FULL_GS = 0x8e,
+ SPI_PERF_RA_SGPR_SIMD_FULL_ES = 0x8f,
+ SPI_PERF_RA_SGPR_SIMD_FULL_HS = 0x90,
+ SPI_PERF_RA_SGPR_SIMD_FULL_LS = 0x91,
+ SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 0x92,
+ SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 0x93,
+ SPI_PERF_RA_LDS_CU_FULL_PS = 0x94,
+ SPI_PERF_RA_LDS_CU_FULL_LS = 0x95,
+ SPI_PERF_RA_LDS_CU_FULL_ES = 0x96,
+ SPI_PERF_RA_LDS_CU_FULL_CSG = 0x97,
+ SPI_PERF_RA_LDS_CU_FULL_CSN = 0x98,
+ SPI_PERF_RA_BAR_CU_FULL_HS = 0x99,
+ SPI_PERF_RA_BAR_CU_FULL_CSG = 0x9a,
+ SPI_PERF_RA_BAR_CU_FULL_CSN = 0x9b,
+ SPI_PERF_RA_BULKY_CU_FULL_CSG = 0x9c,
+ SPI_PERF_RA_BULKY_CU_FULL_CSN = 0x9d,
+ SPI_PERF_RA_TGLIM_CU_FULL_CSG = 0x9e,
+ SPI_PERF_RA_TGLIM_CU_FULL_CSN = 0x9f,
+ SPI_PERF_RA_WVLIM_STALL_PS = 0xa0,
+ SPI_PERF_RA_WVLIM_STALL_VS = 0xa1,
+ SPI_PERF_RA_WVLIM_STALL_GS = 0xa2,
+ SPI_PERF_RA_WVLIM_STALL_ES = 0xa3,
+ SPI_PERF_RA_WVLIM_STALL_HS = 0xa4,
+ SPI_PERF_RA_WVLIM_STALL_LS = 0xa5,
+ SPI_PERF_RA_WVLIM_STALL_CSG = 0xa6,
+ SPI_PERF_RA_WVLIM_STALL_CSN = 0xa7,
+ SPI_PERF_RA_PS_LOCK = 0xa8,
+ SPI_PERF_RA_VS_LOCK = 0xa9,
+ SPI_PERF_RA_GS_LOCK = 0xaa,
+ SPI_PERF_RA_ES_LOCK = 0xab,
+ SPI_PERF_RA_HS_LOCK = 0xac,
+ SPI_PERF_RA_LS_LOCK = 0xad,
+ SPI_PERF_RA_CSG_LOCK = 0xae,
+ SPI_PERF_RA_CSN_LOCK = 0xaf,
+ SPI_PERF_RA_RSV_UPD = 0xb0,
+ SPI_PERF_EXP_ARB_COL_CNT = 0xb1,
+ SPI_PERF_EXP_ARB_PAR_CNT = 0xb2,
+ SPI_PERF_EXP_ARB_POS_CNT = 0xb3,
+ SPI_PERF_EXP_ARB_GDS_CNT = 0xb4,
+ SPI_PERF_CLKGATE_BUSY_STALL = 0xb5,
+ SPI_PERF_CLKGATE_ACTIVE_STALL = 0xb6,
+ SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 0xb7,
+ SPI_PERF_CLKGATE_CGTT_DYN_ON = 0xb8,
+ SPI_PERF_CLKGATE_CGTT_REG_ON = 0xb9,
+} SPI_PERFCNT_SEL;
+typedef enum SPI_SHADER_FORMAT {
+ SPI_SHADER_NONE = 0x0,
+ SPI_SHADER_1COMP = 0x1,
+ SPI_SHADER_2COMP = 0x2,
+ SPI_SHADER_4COMPRESS = 0x3,
+ SPI_SHADER_4COMP = 0x4,
+} SPI_SHADER_FORMAT;
+typedef enum SPI_SHADER_EX_FORMAT {
+ SPI_SHADER_ZERO = 0x0,
+ SPI_SHADER_32_R = 0x1,
+ SPI_SHADER_32_GR = 0x2,
+ SPI_SHADER_32_AR = 0x3,
+ SPI_SHADER_FP16_ABGR = 0x4,
+ SPI_SHADER_UNORM16_ABGR = 0x5,
+ SPI_SHADER_SNORM16_ABGR = 0x6,
+ SPI_SHADER_UINT16_ABGR = 0x7,
+ SPI_SHADER_SINT16_ABGR = 0x8,
+ SPI_SHADER_32_ABGR = 0x9,
+} SPI_SHADER_EX_FORMAT;
+typedef enum CLKGATE_SM_MODE {
+ ON_SEQ = 0x0,
+ OFF_SEQ = 0x1,
+ PROG_SEQ = 0x2,
+ READ_SEQ = 0x3,
+ SM_MODE_RESERVED = 0x4,
+} CLKGATE_SM_MODE;
+typedef enum CLKGATE_BASE_MODE {
+ MULT_8 = 0x0,
+ MULT_16 = 0x1,
+} CLKGATE_BASE_MODE;
+typedef enum SQ_TEX_CLAMP {
+ SQ_TEX_WRAP = 0x0,
+ SQ_TEX_MIRROR = 0x1,
+ SQ_TEX_CLAMP_LAST_TEXEL = 0x2,
+ SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x3,
+ SQ_TEX_CLAMP_HALF_BORDER = 0x4,
+ SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x5,
+ SQ_TEX_CLAMP_BORDER = 0x6,
+ SQ_TEX_MIRROR_ONCE_BORDER = 0x7,
+} SQ_TEX_CLAMP;
+typedef enum SQ_TEX_XY_FILTER {
+ SQ_TEX_XY_FILTER_POINT = 0x0,
+ SQ_TEX_XY_FILTER_BILINEAR = 0x1,
+ SQ_TEX_XY_FILTER_ANISO_POINT = 0x2,
+ SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x3,
+} SQ_TEX_XY_FILTER;
+typedef enum SQ_TEX_Z_FILTER {
+ SQ_TEX_Z_FILTER_NONE = 0x0,
+ SQ_TEX_Z_FILTER_POINT = 0x1,
+ SQ_TEX_Z_FILTER_LINEAR = 0x2,
+} SQ_TEX_Z_FILTER;
+typedef enum SQ_TEX_MIP_FILTER {
+ SQ_TEX_MIP_FILTER_NONE = 0x0,
+ SQ_TEX_MIP_FILTER_POINT = 0x1,
+ SQ_TEX_MIP_FILTER_LINEAR = 0x2,
+} SQ_TEX_MIP_FILTER;
+typedef enum SQ_TEX_ANISO_RATIO {
+ SQ_TEX_ANISO_RATIO_1 = 0x0,
+ SQ_TEX_ANISO_RATIO_2 = 0x1,
+ SQ_TEX_ANISO_RATIO_4 = 0x2,
+ SQ_TEX_ANISO_RATIO_8 = 0x3,
+ SQ_TEX_ANISO_RATIO_16 = 0x4,
+} SQ_TEX_ANISO_RATIO;
+typedef enum SQ_TEX_DEPTH_COMPARE {
+ SQ_TEX_DEPTH_COMPARE_NEVER = 0x0,
+ SQ_TEX_DEPTH_COMPARE_LESS = 0x1,
+ SQ_TEX_DEPTH_COMPARE_EQUAL = 0x2,
+ SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x3,
+ SQ_TEX_DEPTH_COMPARE_GREATER = 0x4,
+ SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x5,
+ SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x6,
+ SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x7,
+} SQ_TEX_DEPTH_COMPARE;
+typedef enum SQ_TEX_BORDER_COLOR {
+ SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x0,
+ SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x1,
+ SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x2,
+ SQ_TEX_BORDER_COLOR_REGISTER = 0x3,
+} SQ_TEX_BORDER_COLOR;
+typedef enum SQ_RSRC_BUF_TYPE {
+ SQ_RSRC_BUF = 0x0,
+ SQ_RSRC_BUF_RSVD_1 = 0x1,
+ SQ_RSRC_BUF_RSVD_2 = 0x2,
+ SQ_RSRC_BUF_RSVD_3 = 0x3,
+} SQ_RSRC_BUF_TYPE;
+typedef enum SQ_RSRC_IMG_TYPE {
+ SQ_RSRC_IMG_RSVD_0 = 0x0,
+ SQ_RSRC_IMG_RSVD_1 = 0x1,
+ SQ_RSRC_IMG_RSVD_2 = 0x2,
+ SQ_RSRC_IMG_RSVD_3 = 0x3,
+ SQ_RSRC_IMG_RSVD_4 = 0x4,
+ SQ_RSRC_IMG_RSVD_5 = 0x5,
+ SQ_RSRC_IMG_RSVD_6 = 0x6,
+ SQ_RSRC_IMG_RSVD_7 = 0x7,
+ SQ_RSRC_IMG_1D = 0x8,
+ SQ_RSRC_IMG_2D = 0x9,
+ SQ_RSRC_IMG_3D = 0xa,
+ SQ_RSRC_IMG_CUBE = 0xb,
+ SQ_RSRC_IMG_1D_ARRAY = 0xc,
+ SQ_RSRC_IMG_2D_ARRAY = 0xd,
+ SQ_RSRC_IMG_2D_MSAA = 0xe,
+ SQ_RSRC_IMG_2D_MSAA_ARRAY = 0xf,
+} SQ_RSRC_IMG_TYPE;
+typedef enum SQ_RSRC_FLAT_TYPE {
+ SQ_RSRC_FLAT_RSVD_0 = 0x0,
+ SQ_RSRC_FLAT = 0x1,
+ SQ_RSRC_FLAT_RSVD_2 = 0x2,
+ SQ_RSRC_FLAT_RSVD_3 = 0x3,
+} SQ_RSRC_FLAT_TYPE;
+typedef enum SQ_IMG_FILTER_TYPE {
+ SQ_IMG_FILTER_MODE_BLEND = 0x0,
+ SQ_IMG_FILTER_MODE_MIN = 0x1,
+ SQ_IMG_FILTER_MODE_MAX = 0x2,
+} SQ_IMG_FILTER_TYPE;
+typedef enum SQ_SEL_XYZW01 {
+ SQ_SEL_0 = 0x0,
+ SQ_SEL_1 = 0x1,
+ SQ_SEL_RESERVED_0 = 0x2,
+ SQ_SEL_RESERVED_1 = 0x3,
+ SQ_SEL_X = 0x4,
+ SQ_SEL_Y = 0x5,
+ SQ_SEL_Z = 0x6,
+ SQ_SEL_W = 0x7,
+} SQ_SEL_XYZW01;
+typedef enum SQ_WAVE_TYPE {
+ SQ_WAVE_TYPE_PS = 0x0,
+ SQ_WAVE_TYPE_VS = 0x1,
+ SQ_WAVE_TYPE_GS = 0x2,
+ SQ_WAVE_TYPE_ES = 0x3,
+ SQ_WAVE_TYPE_HS = 0x4,
+ SQ_WAVE_TYPE_LS = 0x5,
+ SQ_WAVE_TYPE_CS = 0x6,
+ SQ_WAVE_TYPE_PS1 = 0x7,
+} SQ_WAVE_TYPE;
+typedef enum SQ_THREAD_TRACE_TOKEN_TYPE {
+ SQ_THREAD_TRACE_TOKEN_MISC = 0x0,
+ SQ_THREAD_TRACE_TOKEN_TIMESTAMP = 0x1,
+ SQ_THREAD_TRACE_TOKEN_REG = 0x2,
+ SQ_THREAD_TRACE_TOKEN_WAVE_START = 0x3,
+ SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC = 0x4,
+ SQ_THREAD_TRACE_TOKEN_REG_CSPRIV = 0x5,
+ SQ_THREAD_TRACE_TOKEN_WAVE_END = 0x6,
+ SQ_THREAD_TRACE_TOKEN_EVENT = 0x7,
+ SQ_THREAD_TRACE_TOKEN_EVENT_CS = 0x8,
+ SQ_THREAD_TRACE_TOKEN_EVENT_GFX1 = 0x9,
+ SQ_THREAD_TRACE_TOKEN_INST = 0xa,
+ SQ_THREAD_TRACE_TOKEN_INST_PC = 0xb,
+ SQ_THREAD_TRACE_TOKEN_INST_USERDATA = 0xc,
+ SQ_THREAD_TRACE_TOKEN_ISSUE = 0xd,
+ SQ_THREAD_TRACE_TOKEN_PERF = 0xe,
+ SQ_THREAD_TRACE_TOKEN_REG_CS = 0xf,
+} SQ_THREAD_TRACE_TOKEN_TYPE;
+typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE {
+ SQ_THREAD_TRACE_MISC_TOKEN_TIME = 0x0,
+ SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET = 0x1,
+ SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST = 0x2,
+ SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC = 0x3,
+ SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN = 0x4,
+ SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END = 0x5,
+} SQ_THREAD_TRACE_MISC_TOKEN_TYPE;
+typedef enum SQ_THREAD_TRACE_INST_TYPE {
+ SQ_THREAD_TRACE_INST_TYPE_SMEM = 0x0,
+ SQ_THREAD_TRACE_INST_TYPE_SALU = 0x1,
+ SQ_THREAD_TRACE_INST_TYPE_VMEM_RD = 0x2,
+ SQ_THREAD_TRACE_INST_TYPE_VMEM_WR = 0x3,
+ SQ_THREAD_TRACE_INST_TYPE_FLAT_WR = 0x4,
+ SQ_THREAD_TRACE_INST_TYPE_VALU = 0x5,
+ SQ_THREAD_TRACE_INST_TYPE_LDS = 0x6,
+ SQ_THREAD_TRACE_INST_TYPE_PC = 0x7,
+ SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS = 0x8,
+ SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX = 0x9,
+ SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 0xa,
+ SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 0xb,
+ SQ_THREAD_TRACE_INST_TYPE_JUMP = 0xc,
+ SQ_THREAD_TRACE_INST_TYPE_NEXT = 0xd,
+ SQ_THREAD_TRACE_INST_TYPE_FLAT_RD = 0xe,
+ SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG = 0xf,
+} SQ_THREAD_TRACE_INST_TYPE;
+typedef enum SQ_THREAD_TRACE_REG_TYPE {
+ SQ_THREAD_TRACE_REG_TYPE_EVENT = 0x0,
+ SQ_THREAD_TRACE_REG_TYPE_DRAW = 0x1,
+ SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 0x2,
+ SQ_THREAD_TRACE_REG_TYPE_USERDATA = 0x3,
+ SQ_THREAD_TRACE_REG_TYPE_MARKER = 0x4,
+ SQ_THREAD_TRACE_REG_TYPE_GFXDEC = 0x5,
+ SQ_THREAD_TRACE_REG_TYPE_SHDEC = 0x6,
+ SQ_THREAD_TRACE_REG_TYPE_OTHER = 0x7,
+} SQ_THREAD_TRACE_REG_TYPE;
+typedef enum SQ_THREAD_TRACE_REG_OP {
+ SQ_THREAD_TRACE_REG_OP_READ = 0x0,
+ SQ_THREAD_TRACE_REG_OP_WRITE = 0x1,
+} SQ_THREAD_TRACE_REG_OP;
+typedef enum SQ_THREAD_TRACE_MODE_SEL {
+ SQ_THREAD_TRACE_MODE_OFF = 0x0,
+ SQ_THREAD_TRACE_MODE_ON = 0x1,
+ SQ_THREAD_TRACE_MODE_RANDOM = 0x2,
+} SQ_THREAD_TRACE_MODE_SEL;
+typedef enum SQ_THREAD_TRACE_CAPTURE_MODE {
+ SQ_THREAD_TRACE_CAPTURE_MODE_ALL = 0x0,
+ SQ_THREAD_TRACE_CAPTURE_MODE_SELECT = 0x1,
+ SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 0x2,
+} SQ_THREAD_TRACE_CAPTURE_MODE;
+typedef enum SQ_THREAD_TRACE_VM_ID_MASK {
+ SQ_THREAD_TRACE_VM_ID_MASK_SINGLE = 0x0,
+ SQ_THREAD_TRACE_VM_ID_MASK_ALL = 0x1,
+ SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 0x2,
+} SQ_THREAD_TRACE_VM_ID_MASK;
+typedef enum SQ_THREAD_TRACE_WAVE_MASK {
+ SQ_THREAD_TRACE_WAVE_MASK_NONE = 0x0,
+ SQ_THREAD_TRACE_WAVE_MASK_ALL = 0x1,
+ SQ_THREAD_TRACE_WAVE_MASK_1_2 = 0x2,
+ SQ_THREAD_TRACE_WAVE_MASK_1_4 = 0x3,
+ SQ_THREAD_TRACE_WAVE_MASK_1_8 = 0x4,
+ SQ_THREAD_TRACE_WAVE_MASK_1_16 = 0x5,
+ SQ_THREAD_TRACE_WAVE_MASK_1_32 = 0x6,
+ SQ_THREAD_TRACE_WAVE_MASK_1_64 = 0x7,
+} SQ_THREAD_TRACE_WAVE_MASK;
+typedef enum SQ_THREAD_TRACE_ISSUE {
+ SQ_THREAD_TRACE_ISSUE_NULL = 0x0,
+ SQ_THREAD_TRACE_ISSUE_STALL = 0x1,
+ SQ_THREAD_TRACE_ISSUE_INST = 0x2,
+ SQ_THREAD_TRACE_ISSUE_IMMED = 0x3,
+} SQ_THREAD_TRACE_ISSUE;
+typedef enum SQ_THREAD_TRACE_ISSUE_MASK {
+ SQ_THREAD_TRACE_ISSUE_MASK_ALL = 0x0,
+ SQ_THREAD_TRACE_ISSUE_MASK_STALLED = 0x1,
+ SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 0x2,
+ SQ_THREAD_TRACE_ISSUE_MASK_IMMED = 0x3,
+} SQ_THREAD_TRACE_ISSUE_MASK;
+typedef enum SQ_PERF_SEL {
+ SQ_PERF_SEL_NONE = 0x0,
+ SQ_PERF_SEL_ACCUM_PREV = 0x1,
+ SQ_PERF_SEL_CYCLES = 0x2,
+ SQ_PERF_SEL_BUSY_CYCLES = 0x3,
+ SQ_PERF_SEL_WAVES = 0x4,
+ SQ_PERF_SEL_LEVEL_WAVES = 0x5,
+ SQ_PERF_SEL_WAVES_EQ_64 = 0x6,
+ SQ_PERF_SEL_WAVES_LT_64 = 0x7,
+ SQ_PERF_SEL_WAVES_LT_48 = 0x8,
+ SQ_PERF_SEL_WAVES_LT_32 = 0x9,
+ SQ_PERF_SEL_WAVES_LT_16 = 0xa,
+ SQ_PERF_SEL_WAVES_CU = 0xb,
+ SQ_PERF_SEL_LEVEL_WAVES_CU = 0xc,
+ SQ_PERF_SEL_BUSY_CU_CYCLES = 0xd,
+ SQ_PERF_SEL_ITEMS = 0xe,
+ SQ_PERF_SEL_QUADS = 0xf,
+ SQ_PERF_SEL_EVENTS = 0x10,
+ SQ_PERF_SEL_SURF_SYNCS = 0x11,
+ SQ_PERF_SEL_TTRACE_REQS = 0x12,
+ SQ_PERF_SEL_TTRACE_INFLIGHT_REQS = 0x13,
+ SQ_PERF_SEL_TTRACE_STALL = 0x14,
+ SQ_PERF_SEL_MSG_CNTR = 0x15,
+ SQ_PERF_SEL_MSG_PERF = 0x16,
+ SQ_PERF_SEL_MSG_GSCNT = 0x17,
+ SQ_PERF_SEL_MSG_INTERRUPT = 0x18,
+ SQ_PERF_SEL_INSTS = 0x19,
+ SQ_PERF_SEL_INSTS_VALU = 0x1a,
+ SQ_PERF_SEL_INSTS_VMEM_WR = 0x1b,
+ SQ_PERF_SEL_INSTS_VMEM_RD = 0x1c,
+ SQ_PERF_SEL_INSTS_VMEM = 0x1d,
+ SQ_PERF_SEL_INSTS_SALU = 0x1e,
+ SQ_PERF_SEL_INSTS_SMEM = 0x1f,
+ SQ_PERF_SEL_INSTS_FLAT = 0x20,
+ SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY = 0x21,
+ SQ_PERF_SEL_INSTS_LDS = 0x22,
+ SQ_PERF_SEL_INSTS_GDS = 0x23,
+ SQ_PERF_SEL_INSTS_EXP = 0x24,
+ SQ_PERF_SEL_INSTS_EXP_GDS = 0x25,
+ SQ_PERF_SEL_INSTS_BRANCH = 0x26,
+ SQ_PERF_SEL_INSTS_SENDMSG = 0x27,
+ SQ_PERF_SEL_INSTS_VSKIPPED = 0x28,
+ SQ_PERF_SEL_INST_LEVEL_VMEM = 0x29,
+ SQ_PERF_SEL_INST_LEVEL_SMEM = 0x2a,
+ SQ_PERF_SEL_INST_LEVEL_LDS = 0x2b,
+ SQ_PERF_SEL_INST_LEVEL_GDS = 0x2c,
+ SQ_PERF_SEL_INST_LEVEL_EXP = 0x2d,
+ SQ_PERF_SEL_WAVE_CYCLES = 0x2e,
+ SQ_PERF_SEL_WAVE_READY = 0x2f,
+ SQ_PERF_SEL_WAIT_CNT_VM = 0x30,
+ SQ_PERF_SEL_WAIT_CNT_LGKM = 0x31,
+ SQ_PERF_SEL_WAIT_CNT_EXP = 0x32,
+ SQ_PERF_SEL_WAIT_CNT_ANY = 0x33,
+ SQ_PERF_SEL_WAIT_BARRIER = 0x34,
+ SQ_PERF_SEL_WAIT_EXP_ALLOC = 0x35,
+ SQ_PERF_SEL_WAIT_SLEEP = 0x36,
+ SQ_PERF_SEL_WAIT_OTHER = 0x37,
+ SQ_PERF_SEL_WAIT_ANY = 0x38,
+ SQ_PERF_SEL_WAIT_TTRACE = 0x39,
+ SQ_PERF_SEL_WAIT_IFETCH = 0x3a,
+ SQ_PERF_SEL_WAIT_INST_VMEM = 0x3b,
+ SQ_PERF_SEL_WAIT_INST_SCA = 0x3c,
+ SQ_PERF_SEL_WAIT_INST_LDS = 0x3d,
+ SQ_PERF_SEL_WAIT_INST_VALU = 0x3e,
+ SQ_PERF_SEL_WAIT_INST_EXP_GDS = 0x3f,
+ SQ_PERF_SEL_WAIT_INST_MISC = 0x40,
+ SQ_PERF_SEL_WAIT_INST_FLAT = 0x41,
+ SQ_PERF_SEL_ACTIVE_INST_ANY = 0x42,
+ SQ_PERF_SEL_ACTIVE_INST_VMEM = 0x43,
+ SQ_PERF_SEL_ACTIVE_INST_LDS = 0x44,
+ SQ_PERF_SEL_ACTIVE_INST_VALU = 0x45,
+ SQ_PERF_SEL_ACTIVE_INST_SCA = 0x46,
+ SQ_PERF_SEL_ACTIVE_INST_EXP_GDS = 0x47,
+ SQ_PERF_SEL_ACTIVE_INST_MISC = 0x48,
+ SQ_PERF_SEL_ACTIVE_INST_FLAT = 0x49,
+ SQ_PERF_SEL_INST_CYCLES_VMEM_WR = 0x4a,
+ SQ_PERF_SEL_INST_CYCLES_VMEM_RD = 0x4b,
+ SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR = 0x4c,
+ SQ_PERF_SEL_INST_CYCLES_VMEM_DATA = 0x4d,
+ SQ_PERF_SEL_INST_CYCLES_VMEM_CMD = 0x4e,
+ SQ_PERF_SEL_INST_CYCLES_VMEM = 0x4f,
+ SQ_PERF_SEL_INST_CYCLES_LDS = 0x50,
+ SQ_PERF_SEL_INST_CYCLES_VALU = 0x51,
+ SQ_PERF_SEL_INST_CYCLES_EXP = 0x52,
+ SQ_PERF_SEL_INST_CYCLES_GDS = 0x53,
+ SQ_PERF_SEL_INST_CYCLES_SCA = 0x54,
+ SQ_PERF_SEL_INST_CYCLES_SMEM = 0x55,
+ SQ_PERF_SEL_INST_CYCLES_SALU = 0x56,
+ SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 0x57,
+ SQ_PERF_SEL_INST_CYCLES_MISC = 0x58,
+ SQ_PERF_SEL_THREAD_CYCLES_VALU = 0x59,
+ SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX = 0x5a,
+ SQ_PERF_SEL_IFETCH = 0x5b,
+ SQ_PERF_SEL_IFETCH_LEVEL = 0x5c,
+ SQ_PERF_SEL_CBRANCH_FORK = 0x5d,
+ SQ_PERF_SEL_CBRANCH_FORK_SPLIT = 0x5e,
+ SQ_PERF_SEL_VALU_LDS_DIRECT_RD = 0x5f,
+ SQ_PERF_SEL_VALU_LDS_INTERP_OP = 0x60,
+ SQ_PERF_SEL_LDS_BANK_CONFLICT = 0x61,
+ SQ_PERF_SEL_LDS_ADDR_CONFLICT = 0x62,
+ SQ_PERF_SEL_LDS_UNALIGNED_STALL = 0x63,
+ SQ_PERF_SEL_LDS_MEM_VIOLATIONS = 0x64,
+ SQ_PERF_SEL_LDS_ATOMIC_RETURN = 0x65,
+ SQ_PERF_SEL_LDS_IDX_ACTIVE = 0x66,
+ SQ_PERF_SEL_VALU_DEP_STALL = 0x67,
+ SQ_PERF_SEL_VALU_STARVE = 0x68,
+ SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 0x69,
+ SQ_PERF_SEL_LDS_BACK2BACK_STALL = 0x6a,
+ SQ_PERF_SEL_LDS_DATA_FIFO_FULL = 0x6b,
+ SQ_PERF_SEL_LDS_CMD_FIFO_FULL = 0x6c,
+ SQ_PERF_SEL_VMEM_BACK2BACK_STALL = 0x6d,
+ SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL = 0x6e,
+ SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL = 0x6f,
+ SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY = 0x70,
+ SQ_PERF_SEL_VMEM_WR_BACK2BACK_STALL = 0x71,
+ SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL = 0x72,
+ SQ_PERF_SEL_VALU_SRC_C_CONFLICT = 0x73,
+ SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT = 0x74,
+ SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT = 0x75,
+ SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT = 0x76,
+ SQ_PERF_SEL_LDS_SRC_CD_CONFLICT = 0x77,
+ SQ_PERF_SEL_SRC_CD_BUSY = 0x78,
+ SQ_PERF_SEL_PT_POWER_STALL = 0x79,
+ SQ_PERF_SEL_USER0 = 0x7a,
+ SQ_PERF_SEL_USER1 = 0x7b,
+ SQ_PERF_SEL_USER2 = 0x7c,
+ SQ_PERF_SEL_USER3 = 0x7d,
+ SQ_PERF_SEL_USER4 = 0x7e,
+ SQ_PERF_SEL_USER5 = 0x7f,
+ SQ_PERF_SEL_USER6 = 0x80,
+ SQ_PERF_SEL_USER7 = 0x81,
+ SQ_PERF_SEL_USER8 = 0x82,
+ SQ_PERF_SEL_USER9 = 0x83,
+ SQ_PERF_SEL_USER10 = 0x84,
+ SQ_PERF_SEL_USER11 = 0x85,
+ SQ_PERF_SEL_USER12 = 0x86,
+ SQ_PERF_SEL_USER13 = 0x87,
+ SQ_PERF_SEL_USER14 = 0x88,
+ SQ_PERF_SEL_USER15 = 0x89,
+ SQ_PERF_SEL_USER_LEVEL0 = 0x8a,
+ SQ_PERF_SEL_USER_LEVEL1 = 0x8b,
+ SQ_PERF_SEL_USER_LEVEL2 = 0x8c,
+ SQ_PERF_SEL_USER_LEVEL3 = 0x8d,
+ SQ_PERF_SEL_USER_LEVEL4 = 0x8e,
+ SQ_PERF_SEL_USER_LEVEL5 = 0x8f,
+ SQ_PERF_SEL_USER_LEVEL6 = 0x90,
+ SQ_PERF_SEL_USER_LEVEL7 = 0x91,
+ SQ_PERF_SEL_USER_LEVEL8 = 0x92,
+ SQ_PERF_SEL_USER_LEVEL9 = 0x93,
+ SQ_PERF_SEL_USER_LEVEL10 = 0x94,
+ SQ_PERF_SEL_USER_LEVEL11 = 0x95,
+ SQ_PERF_SEL_USER_LEVEL12 = 0x96,
+ SQ_PERF_SEL_USER_LEVEL13 = 0x97,
+ SQ_PERF_SEL_USER_LEVEL14 = 0x98,
+ SQ_PERF_SEL_USER_LEVEL15 = 0x99,
+ SQ_PERF_SEL_POWER_VALU = 0x9a,
+ SQ_PERF_SEL_POWER_VALU0 = 0x9b,
+ SQ_PERF_SEL_POWER_VALU1 = 0x9c,
+ SQ_PERF_SEL_POWER_VALU2 = 0x9d,
+ SQ_PERF_SEL_POWER_GPR_RD = 0x9e,
+ SQ_PERF_SEL_POWER_GPR_WR = 0x9f,
+ SQ_PERF_SEL_POWER_LDS_BUSY = 0xa0,
+ SQ_PERF_SEL_POWER_ALU_BUSY = 0xa1,
+ SQ_PERF_SEL_POWER_TEX_BUSY = 0xa2,
+ SQ_PERF_SEL_ACCUM_PREV_HIRES = 0xa3,
+ SQ_PERF_SEL_DUMMY_LAST = 0xa7,
+ SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 0xa8,
+ SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 0xa9,
+ SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 0xaa,
+ SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 0xab,
+ SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 0xac,
+ SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 0xad,
+ SQC_PERF_SEL_TC_REQ = 0xae,
+ SQC_PERF_SEL_TC_INST_REQ = 0xaf,
+ SQC_PERF_SEL_TC_DATA_REQ = 0xb0,
+ SQC_PERF_SEL_TC_STALL = 0xb1,
+ SQC_PERF_SEL_TC_STARVE = 0xb2,
+ SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 0xb3,
+ SQC_PERF_SEL_ICACHE_REQ = 0xb4,
+ SQC_PERF_SEL_ICACHE_HITS = 0xb5,
+ SQC_PERF_SEL_ICACHE_MISSES = 0xb6,
+ SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 0xb7,
+ SQC_PERF_SEL_ICACHE_UNCACHED = 0xb8,
+ SQC_PERF_SEL_ICACHE_VOLATILE = 0xb9,
+ SQC_PERF_SEL_ICACHE_INVAL_INST = 0xba,
+ SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 0xbb,
+ SQC_PERF_SEL_ICACHE_INVAL_VOLATILE_INST = 0xbc,
+ SQC_PERF_SEL_ICACHE_INVAL_VOLATILE_ASYNC = 0xbd,
+ SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0xbe,
+ SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0xbf,
+ SQC_PERF_SEL_ICACHE_CACHE_STALLED = 0xc0,
+ SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 0xc1,
+ SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0xc2,
+ SQC_PERF_SEL_ICACHE_CACHE_STALL_VOLATILE_MISMATCH= 0xc3,
+ SQC_PERF_SEL_ICACHE_CACHE_STALL_UNCACHED_HIT = 0xc4,
+ SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 0xc5,
+ SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xc6,
+ SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0xc7,
+ SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 0xc8,
+ SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0xc9,
+ SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 0xca,
+ SQC_PERF_SEL_DCACHE_REQ = 0xcb,
+ SQC_PERF_SEL_DCACHE_HITS = 0xcc,
+ SQC_PERF_SEL_DCACHE_MISSES = 0xcd,
+ SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 0xce,
+ SQC_PERF_SEL_DCACHE_UNCACHED = 0xcf,
+ SQC_PERF_SEL_DCACHE_VOLATILE = 0xd0,
+ SQC_PERF_SEL_DCACHE_INVAL_INST = 0xd1,
+ SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 0xd2,
+ SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST = 0xd3,
+ SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC = 0xd4,
+ SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0xd5,
+ SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0xd6,
+ SQC_PERF_SEL_DCACHE_CACHE_STALLED = 0xd7,
+ SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_NONZERO = 0xd8,
+ SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0xd9,
+ SQC_PERF_SEL_DCACHE_CACHE_STALL_VOLATILE_MISMATCH= 0xda,
+ SQC_PERF_SEL_DCACHE_CACHE_STALL_UNCACHED_HIT = 0xdb,
+ SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 0xdc,
+ SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xdd,
+ SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0xde,
+ SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 0xdf,
+ SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0xe0,
+ SQC_PERF_SEL_DCACHE_REQ_1 = 0xe1,
+ SQC_PERF_SEL_DCACHE_REQ_2 = 0xe2,
+ SQC_PERF_SEL_DCACHE_REQ_4 = 0xe3,
+ SQC_PERF_SEL_DCACHE_REQ_8 = 0xe4,
+ SQC_PERF_SEL_DCACHE_REQ_16 = 0xe5,
+ SQC_PERF_SEL_DCACHE_REQ_TIME = 0xe6,
+ SQC_PERF_SEL_SQ_DCACHE_REQS = 0xe7,
+ SQC_PERF_SEL_DCACHE_FLAT_REQ = 0xe8,
+ SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 0xe9,
+ SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 0xea,
+ SQC_PERF_SEL_ICACHE_PRE_CC_LEVEL = 0xeb,
+ SQC_PERF_SEL_ICACHE_POST_CC_LEVEL = 0xec,
+ SQC_PERF_SEL_ICACHE_POST_CC_HIT_LEVEL = 0xed,
+ SQC_PERF_SEL_ICACHE_POST_CC_MISS_LEVEL = 0xee,
+ SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 0xef,
+ SQC_PERF_SEL_DCACHE_PRE_CC_LEVEL = 0xf0,
+ SQC_PERF_SEL_DCACHE_POST_CC_LEVEL = 0xf1,
+ SQC_PERF_SEL_DCACHE_POST_CC_HIT_LEVEL = 0xf2,
+ SQC_PERF_SEL_DCACHE_POST_CC_MISS_LEVEL = 0xf3,
+ SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 0xf4,
+ SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 0xf5,
+ SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 0xf6,
+ SQC_PERF_SEL_ERR_DCACHE_REQ_2_GPR_ADDR_UNALIGNED = 0xf7,
+ SQC_PERF_SEL_ERR_DCACHE_REQ_4_GPR_ADDR_UNALIGNED = 0xf8,
+ SQC_PERF_SEL_ERR_DCACHE_REQ_8_GPR_ADDR_UNALIGNED = 0xf9,
+ SQC_PERF_SEL_ERR_DCACHE_REQ_16_GPR_ADDR_UNALIGNED= 0xfa,
+ SQC_PERF_SEL_DUMMY_LAST = 0xfb,
+} SQ_PERF_SEL;
+typedef enum SQC_DATA_CACHE_POLICIES {
+ SQC_DATA_CACHE_POLICY_HIT_LRU = 0x0,
+ SQC_DATA_CACHE_POLICY_MISS_EVICT = 0x1,
+} SQC_DATA_CACHE_POLICIES;
+typedef enum SQ_CAC_POWER_SEL {
+ SQ_CAC_POWER_VALU = 0x0,
+ SQ_CAC_POWER_VALU0 = 0x1,
+ SQ_CAC_POWER_VALU1 = 0x2,
+ SQ_CAC_POWER_VALU2 = 0x3,
+ SQ_CAC_POWER_GPR_RD = 0x4,
+ SQ_CAC_POWER_GPR_WR = 0x5,
+ SQ_CAC_POWER_LDS_BUSY = 0x6,
+ SQ_CAC_POWER_ALU_BUSY = 0x7,
+ SQ_CAC_POWER_TEX_BUSY = 0x8,
+} SQ_CAC_POWER_SEL;
+typedef enum SQ_IND_CMD_CMD {
+ SQ_IND_CMD_CMD_NULL = 0x0,
+ SQ_IND_CMD_CMD_HALT = 0x1,
+ SQ_IND_CMD_CMD_RESUME = 0x2,
+ SQ_IND_CMD_CMD_KILL = 0x3,
+ SQ_IND_CMD_CMD_DEBUG = 0x4,
+ SQ_IND_CMD_CMD_TRAP = 0x5,
+} SQ_IND_CMD_CMD;
+typedef enum SQ_IND_CMD_MODE {
+ SQ_IND_CMD_MODE_SINGLE = 0x0,
+ SQ_IND_CMD_MODE_BROADCAST = 0x1,
+ SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x2,
+ SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x3,
+ SQ_IND_CMD_MODE_BROADCAST_ME = 0x4,
+} SQ_IND_CMD_MODE;
+typedef enum SQ_DED_INFO_SOURCE {
+ SQ_DED_INFO_SOURCE_INVALID = 0x0,
+ SQ_DED_INFO_SOURCE_INST = 0x1,
+ SQ_DED_INFO_SOURCE_SGPR = 0x2,
+ SQ_DED_INFO_SOURCE_VGPR = 0x3,
+ SQ_DED_INFO_SOURCE_LDS = 0x4,
+ SQ_DED_INFO_SOURCE_GDS = 0x5,
+ SQ_DED_INFO_SOURCE_TA = 0x6,
+} SQ_DED_INFO_SOURCE;
+typedef enum SQ_ROUND_MODE {
+ SQ_ROUND_NEAREST_EVEN = 0x0,
+ SQ_ROUND_PLUS_INFINITY = 0x1,
+ SQ_ROUND_MINUS_INFINITY = 0x2,
+ SQ_ROUND_TO_ZERO = 0x3,
+} SQ_ROUND_MODE;
+typedef enum SQ_INTERRUPT_WORD_ENCODING {
+ SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0,
+ SQ_INTERRUPT_WORD_ENCODING_INST = 0x1,
+ SQ_INTERRUPT_WORD_ENCODING_ERROR = 0x2,
+} SQ_INTERRUPT_WORD_ENCODING;
+typedef enum ENUM_SQ_EXPORT_RAT_INST {
+ SQ_EXPORT_RAT_INST_NOP = 0x0,
+ SQ_EXPORT_RAT_INST_STORE_TYPED = 0x1,
+ SQ_EXPORT_RAT_INST_STORE_RAW = 0x2,
+ SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 0x3,
+ SQ_EXPORT_RAT_INST_CMPXCHG_INT = 0x4,
+ SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 0x5,
+ SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 0x6,
+ SQ_EXPORT_RAT_INST_ADD = 0x7,
+ SQ_EXPORT_RAT_INST_SUB = 0x8,
+ SQ_EXPORT_RAT_INST_RSUB = 0x9,
+ SQ_EXPORT_RAT_INST_MIN_INT = 0xa,
+ SQ_EXPORT_RAT_INST_MIN_UINT = 0xb,
+ SQ_EXPORT_RAT_INST_MAX_INT = 0xc,
+ SQ_EXPORT_RAT_INST_MAX_UINT = 0xd,
+ SQ_EXPORT_RAT_INST_AND = 0xe,
+ SQ_EXPORT_RAT_INST_OR = 0xf,
+ SQ_EXPORT_RAT_INST_XOR = 0x10,
+ SQ_EXPORT_RAT_INST_MSKOR = 0x11,
+ SQ_EXPORT_RAT_INST_INC_UINT = 0x12,
+ SQ_EXPORT_RAT_INST_DEC_UINT = 0x13,
+ SQ_EXPORT_RAT_INST_STORE_DWORD = 0x14,
+ SQ_EXPORT_RAT_INST_STORE_SHORT = 0x15,
+ SQ_EXPORT_RAT_INST_STORE_BYTE = 0x16,
+ SQ_EXPORT_RAT_INST_NOP_RTN = 0x20,
+ SQ_EXPORT_RAT_INST_XCHG_RTN = 0x22,
+ SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 0x23,
+ SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 0x24,
+ SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 0x25,
+ SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 0x26,
+ SQ_EXPORT_RAT_INST_ADD_RTN = 0x27,
+ SQ_EXPORT_RAT_INST_SUB_RTN = 0x28,
+ SQ_EXPORT_RAT_INST_RSUB_RTN = 0x29,
+ SQ_EXPORT_RAT_INST_MIN_INT_RTN = 0x2a,
+ SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 0x2b,
+ SQ_EXPORT_RAT_INST_MAX_INT_RTN = 0x2c,
+ SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 0x2d,
+ SQ_EXPORT_RAT_INST_AND_RTN = 0x2e,
+ SQ_EXPORT_RAT_INST_OR_RTN = 0x2f,
+ SQ_EXPORT_RAT_INST_XOR_RTN = 0x30,
+ SQ_EXPORT_RAT_INST_MSKOR_RTN = 0x31,
+ SQ_EXPORT_RAT_INST_INC_UINT_RTN = 0x32,
+ SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 0x33,
+} ENUM_SQ_EXPORT_RAT_INST;
+typedef enum SQ_IBUF_ST {
+ SQ_IBUF_IB_IDLE = 0x0,
+ SQ_IBUF_IB_INI_WAIT_GNT = 0x1,
+ SQ_IBUF_IB_INI_WAIT_DRET = 0x2,
+ SQ_IBUF_IB_LE_4DW = 0x3,
+ SQ_IBUF_IB_WAIT_DRET = 0x4,
+ SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x5,
+ SQ_IBUF_IB_DRET = 0x6,
+ SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x7,
+} SQ_IBUF_ST;
+typedef enum SQ_INST_STR_ST {
+ SQ_INST_STR_IB_WAVE_NORML = 0x0,
+ SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x1,
+ SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x2,
+ SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x3,
+ SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 0x4,
+ SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 0x5,
+ SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x6,
+ SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x7,
+} SQ_INST_STR_ST;
+typedef enum SQ_WAVE_IB_ECC_ST {
+ SQ_WAVE_IB_ECC_CLEAN = 0x0,
+ SQ_WAVE_IB_ECC_ERR_CONTINUE = 0x1,
+ SQ_WAVE_IB_ECC_ERR_HALT = 0x2,
+ SQ_WAVE_IB_ECC_WITH_ERR_MSG = 0x3,
+} SQ_WAVE_IB_ECC_ST;
+typedef enum SH_MEM_ALIGNMENT_MODE {
+ SH_MEM_ALIGNMENT_MODE_DWORD = 0x0,
+ SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x1,
+ SH_MEM_ALIGNMENT_MODE_STRICT = 0x2,
+ SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x3,
+} SH_MEM_ALIGNMENT_MODE;
+#define SQ_WAVE_TYPE_PS0 0x0
+#define SQ_THREAD_TRACE_LFSR_PS 0x8016
+#define SQ_THREAD_TRACE_LFSR_VS 0x801c
+#define SQ_THREAD_TRACE_LFSR_GS 0x801f
+#define SQ_THREAD_TRACE_LFSR_ES 0x8029
+#define SQ_THREAD_TRACE_LFSR_HS 0x805e
+#define SQ_THREAD_TRACE_LFSR_LS 0x806b
+#define SQ_THREAD_TRACE_LFSR_CS 0x8097
+#define SQIND_GLOBAL_REGS_OFFSET 0x0
+#define SQIND_GLOBAL_REGS_SIZE 0x8
+#define SQIND_LOCAL_REGS_OFFSET 0x8
+#define SQIND_LOCAL_REGS_SIZE 0x8
+#define SQIND_WAVE_HWREGS_OFFSET 0x10
+#define SQIND_WAVE_HWREGS_SIZE 0x1f0
+#define SQIND_WAVE_SGPRS_OFFSET 0x200
+#define SQIND_WAVE_SGPRS_SIZE 0x200
+#define SQ_GFXDEC_BEGIN 0xa000
+#define SQ_GFXDEC_END 0xc000
+#define SQ_GFXDEC_STATE_ID_SHIFT 0xa
+#define SQDEC_BEGIN 0x2300
+#define SQDEC_END 0x23ff
+#define SQPERFSDEC_BEGIN 0xd9c0
+#define SQPERFSDEC_END 0xda40
+#define SQPERFDDEC_BEGIN 0xd1c0
+#define SQPERFDDEC_END 0xd240
+#define SQGFXUDEC_BEGIN 0xc340
+#define SQGFXUDEC_END 0xc380
+#define SQPWRDEC_BEGIN 0xf08c
+#define SQPWRDEC_END 0xf094
+#define SQ_DISPATCHER_GFX_MIN 0x10
+#define SQ_DISPATCHER_GFX_CNT_PER_RING 0x8
+#define SQ_MAX_PGM_SGPRS 0x68
+#define SQ_MAX_PGM_VGPRS 0x100
+#define SQ_THREAD_TRACE_TIME_UNIT 0x4
+#define SQ_INTERRUPT_ID 0xef
+#define SQ_EX_MODE_EXCP_VALU_BASE 0x0
+#define SQ_EX_MODE_EXCP_VALU_SIZE 0x7
+#define SQ_EX_MODE_EXCP_INVALID 0x0
+#define SQ_EX_MODE_EXCP_INPUT_DENORM 0x1
+#define SQ_EX_MODE_EXCP_DIV0 0x2
+#define SQ_EX_MODE_EXCP_OVERFLOW 0x3
+#define SQ_EX_MODE_EXCP_UNDERFLOW 0x4
+#define SQ_EX_MODE_EXCP_INEXACT 0x5
+#define SQ_EX_MODE_EXCP_INT_DIV0 0x6
+#define SQ_EX_MODE_EXCP_ADDR_WATCH 0x7
+#define SQ_EX_MODE_EXCP_MEM_VIOL 0x8
+#define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0
+#define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1
+#define INST_ID_HW_TRAP 0xfffffff2
+#define INST_ID_KILL_SEQ 0xfffffff3
+#define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe
+#define SQ_ENC_SOP1_BITS 0xbe800000
+#define SQ_ENC_SOP1_MASK 0xff800000
+#define SQ_ENC_SOP1_FIELD 0x17d
+#define SQ_ENC_SOPC_BITS 0xbf000000
+#define SQ_ENC_SOPC_MASK 0xff800000
+#define SQ_ENC_SOPC_FIELD 0x17e
+#define SQ_ENC_SOPP_BITS 0xbf800000
+#define SQ_ENC_SOPP_MASK 0xff800000
+#define SQ_ENC_SOPP_FIELD 0x17f
+#define SQ_ENC_SOPK_BITS 0xb0000000
+#define SQ_ENC_SOPK_MASK 0xf0000000
+#define SQ_ENC_SOPK_FIELD 0xb
+#define SQ_ENC_SOP2_BITS 0x80000000
+#define SQ_ENC_SOP2_MASK 0xc0000000
+#define SQ_ENC_SOP2_FIELD 0x2
+#define SQ_ENC_SMRD_BITS 0xc0000000
+#define SQ_ENC_SMRD_MASK 0xf8000000
+#define SQ_ENC_SMRD_FIELD 0x18
+#define SQ_ENC_VOP1_BITS 0x7e000000
+#define SQ_ENC_VOP1_MASK 0xfe000000
+#define SQ_ENC_VOP1_FIELD 0x3f
+#define SQ_ENC_VOPC_BITS 0x7c000000
+#define SQ_ENC_VOPC_MASK 0xfe000000
+#define SQ_ENC_VOPC_FIELD 0x3e
+#define SQ_ENC_VOP2_BITS 0x0
+#define SQ_ENC_VOP2_MASK 0x80000000
+#define SQ_ENC_VOP2_FIELD 0x0
+#define SQ_ENC_VINTRP_BITS 0xc8000000
+#define SQ_ENC_VINTRP_MASK 0xfc000000
+#define SQ_ENC_VINTRP_FIELD 0x32
+#define SQ_ENC_VOP3_BITS 0xd0000000
+#define SQ_ENC_VOP3_MASK 0xfc000000
+#define SQ_ENC_VOP3_FIELD 0x34
+#define SQ_ENC_DS_BITS 0xd8000000
+#define SQ_ENC_DS_MASK 0xfc000000
+#define SQ_ENC_DS_FIELD 0x36
+#define SQ_ENC_MUBUF_BITS 0xe0000000
+#define SQ_ENC_MUBUF_MASK 0xfc000000
+#define SQ_ENC_MUBUF_FIELD 0x38
+#define SQ_ENC_MTBUF_BITS 0xe8000000
+#define SQ_ENC_MTBUF_MASK 0xfc000000
+#define SQ_ENC_MTBUF_FIELD 0x3a
+#define SQ_ENC_MIMG_BITS 0xf0000000
+#define SQ_ENC_MIMG_MASK 0xfc000000
+#define SQ_ENC_MIMG_FIELD 0x3c
+#define SQ_ENC_EXP_BITS 0xf8000000
+#define SQ_ENC_EXP_MASK 0xfc000000
+#define SQ_ENC_EXP_FIELD 0x3e
+#define SQ_ENC_FLAT_BITS 0xdc000000
+#define SQ_ENC_FLAT_MASK 0xfc000000
+#define SQ_ENC_FLAT_FIELD 0x37
+#define SQ_WAITCNT_VM_SHIFT 0x0
+#define SQ_SENDMSG_STREAMID_SIZE 0x2
+#define SQ_V_OPC_COUNT 0x100
+#define SQ_HWREG_OFFSET_SIZE 0x5
+#define SQ_HWREG_OFFSET_SHIFT 0x6
+#define SQ_NUM_ATTR 0x21
+#define SQ_NUM_VGPR 0x100
+#define SQ_SENDMSG_MSG_SIZE 0x4
+#define SQ_NUM_TTMP 0xc
+#define SQ_HWREG_ID_SIZE 0x6
+#define SQ_SENDMSG_GSOP_SIZE 0x2
+#define SQ_NUM_SGPR 0x68
+#define SQ_EXP_NUM_MRT 0x8
+#define SQ_SENDMSG_SYSTEM_SIZE 0x3
+#define SQ_WAITCNT_LGKM_SHIFT 0x8
+#define SQ_WAITCNT_EXP_SIZE 0x3
+#define SQ_SENDMSG_SYSTEM_SHIFT 0x4
+#define SQ_HWREG_SIZE_SHIFT 0xb
+#define SQ_EXP_NUM_GDS 0x5
+#define SQ_SENDMSG_MSG_SHIFT 0x0
+#define SQ_WAITCNT_EXP_SHIFT 0x4
+#define SQ_WAITCNT_VM_SIZE 0x4
+#define SQ_SENDMSG_GSOP_SHIFT 0x4
+#define SQ_SRC_VGPR_BIT 0x100
+#define SQ_V_OP2_COUNT 0x40
+#define SQ_EXP_NUM_PARAM 0x20
+#define SQ_SENDMSG_STREAMID_SHIFT 0x8
+#define SQ_V_OP1_COUNT 0x80
+#define SQ_WAITCNT_LGKM_SIZE 0x5
+#define SQ_EXP_NUM_POS 0x4
+#define SQ_HWREG_SIZE_SIZE 0x5
+#define SQ_HWREG_ID_SHIFT 0x0
+#define SQ_S_MOV_B32 0x3
+#define SQ_S_MOV_B64 0x4
+#define SQ_S_CMOV_B32 0x5
+#define SQ_S_CMOV_B64 0x6
+#define SQ_S_NOT_B32 0x7
+#define SQ_S_NOT_B64 0x8
+#define SQ_S_WQM_B32 0x9
+#define SQ_S_WQM_B64 0xa
+#define SQ_S_BREV_B32 0xb
+#define SQ_S_BREV_B64 0xc
+#define SQ_S_BCNT0_I32_B32 0xd
+#define SQ_S_BCNT0_I32_B64 0xe
+#define SQ_S_BCNT1_I32_B32 0xf
+#define SQ_S_BCNT1_I32_B64 0x10
+#define SQ_S_FF0_I32_B32 0x11
+#define SQ_S_FF0_I32_B64 0x12
+#define SQ_S_FF1_I32_B32 0x13
+#define SQ_S_FF1_I32_B64 0x14
+#define SQ_S_FLBIT_I32_B32 0x15
+#define SQ_S_FLBIT_I32_B64 0x16
+#define SQ_S_FLBIT_I32 0x17
+#define SQ_S_FLBIT_I32_I64 0x18
+#define SQ_S_SEXT_I32_I8 0x19
+#define SQ_S_SEXT_I32_I16 0x1a
+#define SQ_S_BITSET0_B32 0x1b
+#define SQ_S_BITSET0_B64 0x1c
+#define SQ_S_BITSET1_B32 0x1d
+#define SQ_S_BITSET1_B64 0x1e
+#define SQ_S_GETPC_B64 0x1f
+#define SQ_S_SETPC_B64 0x20
+#define SQ_S_SWAPPC_B64 0x21
+#define SQ_S_RFE_B64 0x22
+#define SQ_S_AND_SAVEEXEC_B64 0x24
+#define SQ_S_OR_SAVEEXEC_B64 0x25
+#define SQ_S_XOR_SAVEEXEC_B64 0x26
+#define SQ_S_ANDN2_SAVEEXEC_B64 0x27
+#define SQ_S_ORN2_SAVEEXEC_B64 0x28
+#define SQ_S_NAND_SAVEEXEC_B64 0x29
+#define SQ_S_NOR_SAVEEXEC_B64 0x2a
+#define SQ_S_XNOR_SAVEEXEC_B64 0x2b
+#define SQ_S_QUADMASK_B32 0x2c
+#define SQ_S_QUADMASK_B64 0x2d
+#define SQ_S_MOVRELS_B32 0x2e
+#define SQ_S_MOVRELS_B64 0x2f
+#define SQ_S_MOVRELD_B32 0x30
+#define SQ_S_MOVRELD_B64 0x31
+#define SQ_S_CBRANCH_JOIN 0x32
+#define SQ_S_MOV_REGRD_B32 0x33
+#define SQ_S_ABS_I32 0x34
+#define SQ_S_MOV_FED_B32 0x35
+#define SQ_ATTR0 0x0
+#define SQ_S_MOVK_I32 0x0
+#define SQ_S_CMOVK_I32 0x2
+#define SQ_S_CMPK_EQ_I32 0x3
+#define SQ_S_CMPK_LG_I32 0x4
+#define SQ_S_CMPK_GT_I32 0x5
+#define SQ_S_CMPK_GE_I32 0x6
+#define SQ_S_CMPK_LT_I32 0x7
+#define SQ_S_CMPK_LE_I32 0x8
+#define SQ_S_CMPK_EQ_U32 0x9
+#define SQ_S_CMPK_LG_U32 0xa
+#define SQ_S_CMPK_GT_U32 0xb
+#define SQ_S_CMPK_GE_U32 0xc
+#define SQ_S_CMPK_LT_U32 0xd
+#define SQ_S_CMPK_LE_U32 0xe
+#define SQ_S_ADDK_I32 0xf
+#define SQ_S_MULK_I32 0x10
+#define SQ_S_CBRANCH_I_FORK 0x11
+#define SQ_S_GETREG_B32 0x12
+#define SQ_S_SETREG_B32 0x13
+#define SQ_S_GETREG_REGRD_B32 0x14
+#define SQ_S_SETREG_IMM32_B32 0x15
+#define SQ_TBA_LO 0x6c
+#define SQ_TBA_HI 0x6d
+#define SQ_TMA_LO 0x6e
+#define SQ_TMA_HI 0x6f
+#define SQ_TTMP0 0x70
+#define SQ_TTMP1 0x71
+#define SQ_TTMP2 0x72
+#define SQ_TTMP3 0x73
+#define SQ_TTMP4 0x74
+#define SQ_TTMP5 0x75
+#define SQ_TTMP6 0x76
+#define SQ_TTMP7 0x77
+#define SQ_TTMP8 0x78
+#define SQ_TTMP9 0x79
+#define SQ_TTMP10 0x7a
+#define SQ_TTMP11 0x7b
+#define SQ_VGPR0 0x0
+#define SQ_EXP 0x0
+#define SQ_EXP_MRT0 0x0
+#define SQ_EXP_MRTZ 0x8
+#define SQ_EXP_NULL 0x9
+#define SQ_EXP_POS0 0xc
+#define SQ_EXP_PARAM0 0x20
+#define SQ_CNT1 0x0
+#define SQ_CNT2 0x1
+#define SQ_CNT3 0x2
+#define SQ_CNT4 0x3
+#define SQ_F 0x0
+#define SQ_LT 0x1
+#define SQ_EQ 0x2
+#define SQ_LE 0x3
+#define SQ_GT 0x4
+#define SQ_LG 0x5
+#define SQ_GE 0x6
+#define SQ_O 0x7
+#define SQ_U 0x8
+#define SQ_NGE 0x9
+#define SQ_NLG 0xa
+#define SQ_NGT 0xb
+#define SQ_NLE 0xc
+#define SQ_NEQ 0xd
+#define SQ_NLT 0xe
+#define SQ_TRU 0xf
+#define SQ_V_CMP_F_F32 0x0
+#define SQ_V_CMP_LT_F32 0x1
+#define SQ_V_CMP_EQ_F32 0x2
+#define SQ_V_CMP_LE_F32 0x3
+#define SQ_V_CMP_GT_F32 0x4
+#define SQ_V_CMP_LG_F32 0x5
+#define SQ_V_CMP_GE_F32 0x6
+#define SQ_V_CMP_O_F32 0x7
+#define SQ_V_CMP_U_F32 0x8
+#define SQ_V_CMP_NGE_F32 0x9
+#define SQ_V_CMP_NLG_F32 0xa
+#define SQ_V_CMP_NGT_F32 0xb
+#define SQ_V_CMP_NLE_F32 0xc
+#define SQ_V_CMP_NEQ_F32 0xd
+#define SQ_V_CMP_NLT_F32 0xe
+#define SQ_V_CMP_TRU_F32 0xf
+#define SQ_V_CMPX_F_F32 0x10
+#define SQ_V_CMPX_LT_F32 0x11
+#define SQ_V_CMPX_EQ_F32 0x12
+#define SQ_V_CMPX_LE_F32 0x13
+#define SQ_V_CMPX_GT_F32 0x14
+#define SQ_V_CMPX_LG_F32 0x15
+#define SQ_V_CMPX_GE_F32 0x16
+#define SQ_V_CMPX_O_F32 0x17
+#define SQ_V_CMPX_U_F32 0x18
+#define SQ_V_CMPX_NGE_F32 0x19
+#define SQ_V_CMPX_NLG_F32 0x1a
+#define SQ_V_CMPX_NGT_F32 0x1b
+#define SQ_V_CMPX_NLE_F32 0x1c
+#define SQ_V_CMPX_NEQ_F32 0x1d
+#define SQ_V_CMPX_NLT_F32 0x1e
+#define SQ_V_CMPX_TRU_F32 0x1f
+#define SQ_V_CMP_F_F64 0x20
+#define SQ_V_CMP_LT_F64 0x21
+#define SQ_V_CMP_EQ_F64 0x22
+#define SQ_V_CMP_LE_F64 0x23
+#define SQ_V_CMP_GT_F64 0x24
+#define SQ_V_CMP_LG_F64 0x25
+#define SQ_V_CMP_GE_F64 0x26
+#define SQ_V_CMP_O_F64 0x27
+#define SQ_V_CMP_U_F64 0x28
+#define SQ_V_CMP_NGE_F64 0x29
+#define SQ_V_CMP_NLG_F64 0x2a
+#define SQ_V_CMP_NGT_F64 0x2b
+#define SQ_V_CMP_NLE_F64 0x2c
+#define SQ_V_CMP_NEQ_F64 0x2d
+#define SQ_V_CMP_NLT_F64 0x2e
+#define SQ_V_CMP_TRU_F64 0x2f
+#define SQ_V_CMPX_F_F64 0x30
+#define SQ_V_CMPX_LT_F64 0x31
+#define SQ_V_CMPX_EQ_F64 0x32
+#define SQ_V_CMPX_LE_F64 0x33
+#define SQ_V_CMPX_GT_F64 0x34
+#define SQ_V_CMPX_LG_F64 0x35
+#define SQ_V_CMPX_GE_F64 0x36
+#define SQ_V_CMPX_O_F64 0x37
+#define SQ_V_CMPX_U_F64 0x38
+#define SQ_V_CMPX_NGE_F64 0x39
+#define SQ_V_CMPX_NLG_F64 0x3a
+#define SQ_V_CMPX_NGT_F64 0x3b
+#define SQ_V_CMPX_NLE_F64 0x3c
+#define SQ_V_CMPX_NEQ_F64 0x3d
+#define SQ_V_CMPX_NLT_F64 0x3e
+#define SQ_V_CMPX_TRU_F64 0x3f
+#define SQ_V_CMPS_F_F32 0x40
+#define SQ_V_CMPS_LT_F32 0x41
+#define SQ_V_CMPS_EQ_F32 0x42
+#define SQ_V_CMPS_LE_F32 0x43
+#define SQ_V_CMPS_GT_F32 0x44
+#define SQ_V_CMPS_LG_F32 0x45
+#define SQ_V_CMPS_GE_F32 0x46
+#define SQ_V_CMPS_O_F32 0x47
+#define SQ_V_CMPS_U_F32 0x48
+#define SQ_V_CMPS_NGE_F32 0x49
+#define SQ_V_CMPS_NLG_F32 0x4a
+#define SQ_V_CMPS_NGT_F32 0x4b
+#define SQ_V_CMPS_NLE_F32 0x4c
+#define SQ_V_CMPS_NEQ_F32 0x4d
+#define SQ_V_CMPS_NLT_F32 0x4e
+#define SQ_V_CMPS_TRU_F32 0x4f
+#define SQ_V_CMPSX_F_F32 0x50
+#define SQ_V_CMPSX_LT_F32 0x51
+#define SQ_V_CMPSX_EQ_F32 0x52
+#define SQ_V_CMPSX_LE_F32 0x53
+#define SQ_V_CMPSX_GT_F32 0x54
+#define SQ_V_CMPSX_LG_F32 0x55
+#define SQ_V_CMPSX_GE_F32 0x56
+#define SQ_V_CMPSX_O_F32 0x57
+#define SQ_V_CMPSX_U_F32 0x58
+#define SQ_V_CMPSX_NGE_F32 0x59
+#define SQ_V_CMPSX_NLG_F32 0x5a
+#define SQ_V_CMPSX_NGT_F32 0x5b
+#define SQ_V_CMPSX_NLE_F32 0x5c
+#define SQ_V_CMPSX_NEQ_F32 0x5d
+#define SQ_V_CMPSX_NLT_F32 0x5e
+#define SQ_V_CMPSX_TRU_F32 0x5f
+#define SQ_V_CMPS_F_F64 0x60
+#define SQ_V_CMPS_LT_F64 0x61
+#define SQ_V_CMPS_EQ_F64 0x62
+#define SQ_V_CMPS_LE_F64 0x63
+#define SQ_V_CMPS_GT_F64 0x64
+#define SQ_V_CMPS_LG_F64 0x65
+#define SQ_V_CMPS_GE_F64 0x66
+#define SQ_V_CMPS_O_F64 0x67
+#define SQ_V_CMPS_U_F64 0x68
+#define SQ_V_CMPS_NGE_F64 0x69
+#define SQ_V_CMPS_NLG_F64 0x6a
+#define SQ_V_CMPS_NGT_F64 0x6b
+#define SQ_V_CMPS_NLE_F64 0x6c
+#define SQ_V_CMPS_NEQ_F64 0x6d
+#define SQ_V_CMPS_NLT_F64 0x6e
+#define SQ_V_CMPS_TRU_F64 0x6f
+#define SQ_V_CMPSX_F_F64 0x70
+#define SQ_V_CMPSX_LT_F64 0x71
+#define SQ_V_CMPSX_EQ_F64 0x72
+#define SQ_V_CMPSX_LE_F64 0x73
+#define SQ_V_CMPSX_GT_F64 0x74
+#define SQ_V_CMPSX_LG_F64 0x75
+#define SQ_V_CMPSX_GE_F64 0x76
+#define SQ_V_CMPSX_O_F64 0x77
+#define SQ_V_CMPSX_U_F64 0x78
+#define SQ_V_CMPSX_NGE_F64 0x79
+#define SQ_V_CMPSX_NLG_F64 0x7a
+#define SQ_V_CMPSX_NGT_F64 0x7b
+#define SQ_V_CMPSX_NLE_F64 0x7c
+#define SQ_V_CMPSX_NEQ_F64 0x7d
+#define SQ_V_CMPSX_NLT_F64 0x7e
+#define SQ_V_CMPSX_TRU_F64 0x7f
+#define SQ_V_CMP_F_I32 0x80
+#define SQ_V_CMP_LT_I32 0x81
+#define SQ_V_CMP_EQ_I32 0x82
+#define SQ_V_CMP_LE_I32 0x83
+#define SQ_V_CMP_GT_I32 0x84
+#define SQ_V_CMP_NE_I32 0x85
+#define SQ_V_CMP_GE_I32 0x86
+#define SQ_V_CMP_T_I32 0x87
+#define SQ_V_CMPX_F_I32 0x90
+#define SQ_V_CMPX_LT_I32 0x91
+#define SQ_V_CMPX_EQ_I32 0x92
+#define SQ_V_CMPX_LE_I32 0x93
+#define SQ_V_CMPX_GT_I32 0x94
+#define SQ_V_CMPX_NE_I32 0x95
+#define SQ_V_CMPX_GE_I32 0x96
+#define SQ_V_CMPX_T_I32 0x97
+#define SQ_V_CMP_F_I64 0xa0
+#define SQ_V_CMP_LT_I64 0xa1
+#define SQ_V_CMP_EQ_I64 0xa2
+#define SQ_V_CMP_LE_I64 0xa3
+#define SQ_V_CMP_GT_I64 0xa4
+#define SQ_V_CMP_NE_I64 0xa5
+#define SQ_V_CMP_GE_I64 0xa6
+#define SQ_V_CMP_T_I64 0xa7
+#define SQ_V_CMPX_F_I64 0xb0
+#define SQ_V_CMPX_LT_I64 0xb1
+#define SQ_V_CMPX_EQ_I64 0xb2
+#define SQ_V_CMPX_LE_I64 0xb3
+#define SQ_V_CMPX_GT_I64 0xb4
+#define SQ_V_CMPX_NE_I64 0xb5
+#define SQ_V_CMPX_GE_I64 0xb6
+#define SQ_V_CMPX_T_I64 0xb7
+#define SQ_V_CMP_F_U32 0xc0
+#define SQ_V_CMP_LT_U32 0xc1
+#define SQ_V_CMP_EQ_U32 0xc2
+#define SQ_V_CMP_LE_U32 0xc3
+#define SQ_V_CMP_GT_U32 0xc4
+#define SQ_V_CMP_NE_U32 0xc5
+#define SQ_V_CMP_GE_U32 0xc6
+#define SQ_V_CMP_T_U32 0xc7
+#define SQ_V_CMPX_F_U32 0xd0
+#define SQ_V_CMPX_LT_U32 0xd1
+#define SQ_V_CMPX_EQ_U32 0xd2
+#define SQ_V_CMPX_LE_U32 0xd3
+#define SQ_V_CMPX_GT_U32 0xd4
+#define SQ_V_CMPX_NE_U32 0xd5
+#define SQ_V_CMPX_GE_U32 0xd6
+#define SQ_V_CMPX_T_U32 0xd7
+#define SQ_V_CMP_F_U64 0xe0
+#define SQ_V_CMP_LT_U64 0xe1
+#define SQ_V_CMP_EQ_U64 0xe2
+#define SQ_V_CMP_LE_U64 0xe3
+#define SQ_V_CMP_GT_U64 0xe4
+#define SQ_V_CMP_NE_U64 0xe5
+#define SQ_V_CMP_GE_U64 0xe6
+#define SQ_V_CMP_T_U64 0xe7
+#define SQ_V_CMPX_F_U64 0xf0
+#define SQ_V_CMPX_LT_U64 0xf1
+#define SQ_V_CMPX_EQ_U64 0xf2
+#define SQ_V_CMPX_LE_U64 0xf3
+#define SQ_V_CMPX_GT_U64 0xf4
+#define SQ_V_CMPX_NE_U64 0xf5
+#define SQ_V_CMPX_GE_U64 0xf6
+#define SQ_V_CMPX_T_U64 0xf7
+#define SQ_V_CMP_CLASS_F32 0x88
+#define SQ_V_CMPX_CLASS_F32 0x98
+#define SQ_V_CMP_CLASS_F64 0xa8
+#define SQ_V_CMPX_CLASS_F64 0xb8
+#define SQ_SGPR0 0x0
+#define SQ_F 0x0
+#define SQ_LT 0x1
+#define SQ_EQ 0x2
+#define SQ_LE 0x3
+#define SQ_GT 0x4
+#define SQ_NE 0x5
+#define SQ_GE 0x6
+#define SQ_T 0x7
+#define SQ_SRC_64_INT 0xc0
+#define SQ_SRC_M_1_INT 0xc1
+#define SQ_SRC_M_2_INT 0xc2
+#define SQ_SRC_M_3_INT 0xc3
+#define SQ_SRC_M_4_INT 0xc4
+#define SQ_SRC_M_5_INT 0xc5
+#define SQ_SRC_M_6_INT 0xc6
+#define SQ_SRC_M_7_INT 0xc7
+#define SQ_SRC_M_8_INT 0xc8
+#define SQ_SRC_M_9_INT 0xc9
+#define SQ_SRC_M_10_INT 0xca
+#define SQ_SRC_M_11_INT 0xcb
+#define SQ_SRC_M_12_INT 0xcc
+#define SQ_SRC_M_13_INT 0xcd
+#define SQ_SRC_M_14_INT 0xce
+#define SQ_SRC_M_15_INT 0xcf
+#define SQ_SRC_M_16_INT 0xd0
+#define SQ_SRC_0_5 0xf0
+#define SQ_SRC_M_0_5 0xf1
+#define SQ_SRC_1 0xf2
+#define SQ_SRC_M_1 0xf3
+#define SQ_SRC_2 0xf4
+#define SQ_SRC_M_2 0xf5
+#define SQ_SRC_4 0xf6
+#define SQ_SRC_M_4 0xf7
+#define SQ_SRC_0 0x80
+#define SQ_SRC_1_INT 0x81
+#define SQ_SRC_2_INT 0x82
+#define SQ_SRC_3_INT 0x83
+#define SQ_SRC_4_INT 0x84
+#define SQ_SRC_5_INT 0x85
+#define SQ_SRC_6_INT 0x86
+#define SQ_SRC_7_INT 0x87
+#define SQ_SRC_8_INT 0x88
+#define SQ_SRC_9_INT 0x89
+#define SQ_SRC_10_INT 0x8a
+#define SQ_SRC_11_INT 0x8b
+#define SQ_SRC_12_INT 0x8c
+#define SQ_SRC_13_INT 0x8d
+#define SQ_SRC_14_INT 0x8e
+#define SQ_SRC_15_INT 0x8f
+#define SQ_SRC_16_INT 0x90
+#define SQ_SRC_17_INT 0x91
+#define SQ_SRC_18_INT 0x92
+#define SQ_SRC_19_INT 0x93
+#define SQ_SRC_20_INT 0x94
+#define SQ_SRC_21_INT 0x95
+#define SQ_SRC_22_INT 0x96
+#define SQ_SRC_23_INT 0x97
+#define SQ_SRC_24_INT 0x98
+#define SQ_SRC_25_INT 0x99
+#define SQ_SRC_26_INT 0x9a
+#define SQ_SRC_27_INT 0x9b
+#define SQ_SRC_28_INT 0x9c
+#define SQ_SRC_29_INT 0x9d
+#define SQ_SRC_30_INT 0x9e
+#define SQ_SRC_31_INT 0x9f
+#define SQ_SRC_32_INT 0xa0
+#define SQ_SRC_33_INT 0xa1
+#define SQ_SRC_34_INT 0xa2
+#define SQ_SRC_35_INT 0xa3
+#define SQ_SRC_36_INT 0xa4
+#define SQ_SRC_37_INT 0xa5
+#define SQ_SRC_38_INT 0xa6
+#define SQ_SRC_39_INT 0xa7
+#define SQ_SRC_40_INT 0xa8
+#define SQ_SRC_41_INT 0xa9
+#define SQ_SRC_42_INT 0xaa
+#define SQ_SRC_43_INT 0xab
+#define SQ_SRC_44_INT 0xac
+#define SQ_SRC_45_INT 0xad
+#define SQ_SRC_46_INT 0xae
+#define SQ_SRC_47_INT 0xaf
+#define SQ_SRC_48_INT 0xb0
+#define SQ_SRC_49_INT 0xb1
+#define SQ_SRC_50_INT 0xb2
+#define SQ_SRC_51_INT 0xb3
+#define SQ_SRC_52_INT 0xb4
+#define SQ_SRC_53_INT 0xb5
+#define SQ_SRC_54_INT 0xb6
+#define SQ_SRC_55_INT 0xb7
+#define SQ_SRC_56_INT 0xb8
+#define SQ_SRC_57_INT 0xb9
+#define SQ_SRC_58_INT 0xba
+#define SQ_SRC_59_INT 0xbb
+#define SQ_SRC_60_INT 0xbc
+#define SQ_SRC_61_INT 0xbd
+#define SQ_SRC_62_INT 0xbe
+#define SQ_SRC_63_INT 0xbf
+#define SQ_BUFFER_LOAD_FORMAT_X 0x0
+#define SQ_BUFFER_LOAD_FORMAT_XY 0x1
+#define SQ_BUFFER_LOAD_FORMAT_XYZ 0x2
+#define SQ_BUFFER_LOAD_FORMAT_XYZW 0x3
+#define SQ_BUFFER_STORE_FORMAT_X 0x4
+#define SQ_BUFFER_STORE_FORMAT_XY 0x5
+#define SQ_BUFFER_STORE_FORMAT_XYZ 0x6
+#define SQ_BUFFER_STORE_FORMAT_XYZW 0x7
+#define SQ_BUFFER_LOAD_UBYTE 0x8
+#define SQ_BUFFER_LOAD_SBYTE 0x9
+#define SQ_BUFFER_LOAD_USHORT 0xa
+#define SQ_BUFFER_LOAD_SSHORT 0xb
+#define SQ_BUFFER_LOAD_DWORD 0xc
+#define SQ_BUFFER_LOAD_DWORDX2 0xd
+#define SQ_BUFFER_LOAD_DWORDX4 0xe
+#define SQ_BUFFER_LOAD_DWORDX3 0xf
+#define SQ_BUFFER_STORE_BYTE 0x18
+#define SQ_BUFFER_STORE_SHORT 0x1a
+#define SQ_BUFFER_STORE_DWORD 0x1c
+#define SQ_BUFFER_STORE_DWORDX2 0x1d
+#define SQ_BUFFER_STORE_DWORDX4 0x1e
+#define SQ_BUFFER_STORE_DWORDX3 0x1f
+#define SQ_BUFFER_ATOMIC_SWAP 0x30
+#define SQ_BUFFER_ATOMIC_CMPSWAP 0x31
+#define SQ_BUFFER_ATOMIC_ADD 0x32
+#define SQ_BUFFER_ATOMIC_SUB 0x33
+#define SQ_BUFFER_ATOMIC_SMIN 0x35
+#define SQ_BUFFER_ATOMIC_UMIN 0x36
+#define SQ_BUFFER_ATOMIC_SMAX 0x37
+#define SQ_BUFFER_ATOMIC_UMAX 0x38
+#define SQ_BUFFER_ATOMIC_AND 0x39
+#define SQ_BUFFER_ATOMIC_OR 0x3a
+#define SQ_BUFFER_ATOMIC_XOR 0x3b
+#define SQ_BUFFER_ATOMIC_INC 0x3c
+#define SQ_BUFFER_ATOMIC_DEC 0x3d
+#define SQ_BUFFER_ATOMIC_FCMPSWAP 0x3e
+#define SQ_BUFFER_ATOMIC_FMIN 0x3f
+#define SQ_BUFFER_ATOMIC_FMAX 0x40
+#define SQ_BUFFER_ATOMIC_SWAP_X2 0x50
+#define SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x51
+#define SQ_BUFFER_ATOMIC_ADD_X2 0x52
+#define SQ_BUFFER_ATOMIC_SUB_X2 0x53
+#define SQ_BUFFER_ATOMIC_SMIN_X2 0x55
+#define SQ_BUFFER_ATOMIC_UMIN_X2 0x56
+#define SQ_BUFFER_ATOMIC_SMAX_X2 0x57
+#define SQ_BUFFER_ATOMIC_UMAX_X2 0x58
+#define SQ_BUFFER_ATOMIC_AND_X2 0x59
+#define SQ_BUFFER_ATOMIC_OR_X2 0x5a
+#define SQ_BUFFER_ATOMIC_XOR_X2 0x5b
+#define SQ_BUFFER_ATOMIC_INC_X2 0x5c
+#define SQ_BUFFER_ATOMIC_DEC_X2 0x5d
+#define SQ_BUFFER_ATOMIC_FCMPSWAP_X2 0x5e
+#define SQ_BUFFER_ATOMIC_FMIN_X2 0x5f
+#define SQ_BUFFER_ATOMIC_FMAX_X2 0x60
+#define SQ_BUFFER_WBINVL1_VOL 0x70
+#define SQ_BUFFER_WBINVL1 0x71
+#define SQ_DS_ADD_U32 0x0
+#define SQ_DS_SUB_U32 0x1
+#define SQ_DS_RSUB_U32 0x2
+#define SQ_DS_INC_U32 0x3
+#define SQ_DS_DEC_U32 0x4
+#define SQ_DS_MIN_I32 0x5
+#define SQ_DS_MAX_I32 0x6
+#define SQ_DS_MIN_U32 0x7
+#define SQ_DS_MAX_U32 0x8
+#define SQ_DS_AND_B32 0x9
+#define SQ_DS_OR_B32 0xa
+#define SQ_DS_XOR_B32 0xb
+#define SQ_DS_MSKOR_B32 0xc
+#define SQ_DS_WRITE_B32 0xd
+#define SQ_DS_WRITE2_B32 0xe
+#define SQ_DS_WRITE2ST64_B32 0xf
+#define SQ_DS_CMPST_B32 0x10
+#define SQ_DS_CMPST_F32 0x11
+#define SQ_DS_MIN_F32 0x12
+#define SQ_DS_MAX_F32 0x13
+#define SQ_DS_NOP 0x14
+#define SQ_DS_GWS_SEMA_RELEASE_ALL 0x18
+#define SQ_DS_GWS_INIT 0x19
+#define SQ_DS_GWS_SEMA_V 0x1a
+#define SQ_DS_GWS_SEMA_BR 0x1b
+#define SQ_DS_GWS_SEMA_P 0x1c
+#define SQ_DS_GWS_BARRIER 0x1d
+#define SQ_DS_WRITE_B8 0x1e
+#define SQ_DS_WRITE_B16 0x1f
+#define SQ_DS_ADD_RTN_U32 0x20
+#define SQ_DS_SUB_RTN_U32 0x21
+#define SQ_DS_RSUB_RTN_U32 0x22
+#define SQ_DS_INC_RTN_U32 0x23
+#define SQ_DS_DEC_RTN_U32 0x24
+#define SQ_DS_MIN_RTN_I32 0x25
+#define SQ_DS_MAX_RTN_I32 0x26
+#define SQ_DS_MIN_RTN_U32 0x27
+#define SQ_DS_MAX_RTN_U32 0x28
+#define SQ_DS_AND_RTN_B32 0x29
+#define SQ_DS_OR_RTN_B32 0x2a
+#define SQ_DS_XOR_RTN_B32 0x2b
+#define SQ_DS_MSKOR_RTN_B32 0x2c
+#define SQ_DS_WRXCHG_RTN_B32 0x2d
+#define SQ_DS_WRXCHG2_RTN_B32 0x2e
+#define SQ_DS_WRXCHG2ST64_RTN_B32 0x2f
+#define SQ_DS_CMPST_RTN_B32 0x30
+#define SQ_DS_CMPST_RTN_F32 0x31
+#define SQ_DS_MIN_RTN_F32 0x32
+#define SQ_DS_MAX_RTN_F32 0x33
+#define SQ_DS_WRAP_RTN_B32 0x34
+#define SQ_DS_SWIZZLE_B32 0x35
+#define SQ_DS_READ_B32 0x36
+#define SQ_DS_READ2_B32 0x37
+#define SQ_DS_READ2ST64_B32 0x38
+#define SQ_DS_READ_I8 0x39
+#define SQ_DS_READ_U8 0x3a
+#define SQ_DS_READ_I16 0x3b
+#define SQ_DS_READ_U16 0x3c
+#define SQ_DS_CONSUME 0x3d
+#define SQ_DS_APPEND 0x3e
+#define SQ_DS_ORDERED_COUNT 0x3f
+#define SQ_DS_ADD_U64 0x40
+#define SQ_DS_SUB_U64 0x41
+#define SQ_DS_RSUB_U64 0x42
+#define SQ_DS_INC_U64 0x43
+#define SQ_DS_DEC_U64 0x44
+#define SQ_DS_MIN_I64 0x45
+#define SQ_DS_MAX_I64 0x46
+#define SQ_DS_MIN_U64 0x47
+#define SQ_DS_MAX_U64 0x48
+#define SQ_DS_AND_B64 0x49
+#define SQ_DS_OR_B64 0x4a
+#define SQ_DS_XOR_B64 0x4b
+#define SQ_DS_MSKOR_B64 0x4c
+#define SQ_DS_WRITE_B64 0x4d
+#define SQ_DS_WRITE2_B64 0x4e
+#define SQ_DS_WRITE2ST64_B64 0x4f
+#define SQ_DS_CMPST_B64 0x50
+#define SQ_DS_CMPST_F64 0x51
+#define SQ_DS_MIN_F64 0x52
+#define SQ_DS_MAX_F64 0x53
+#define SQ_DS_ADD_RTN_U64 0x60
+#define SQ_DS_SUB_RTN_U64 0x61
+#define SQ_DS_RSUB_RTN_U64 0x62
+#define SQ_DS_INC_RTN_U64 0x63
+#define SQ_DS_DEC_RTN_U64 0x64
+#define SQ_DS_MIN_RTN_I64 0x65
+#define SQ_DS_MAX_RTN_I64 0x66
+#define SQ_DS_MIN_RTN_U64 0x67
+#define SQ_DS_MAX_RTN_U64 0x68
+#define SQ_DS_AND_RTN_B64 0x69
+#define SQ_DS_OR_RTN_B64 0x6a
+#define SQ_DS_XOR_RTN_B64 0x6b
+#define SQ_DS_MSKOR_RTN_B64 0x6c
+#define SQ_DS_WRXCHG_RTN_B64 0x6d
+#define SQ_DS_WRXCHG2_RTN_B64 0x6e
+#define SQ_DS_WRXCHG2ST64_RTN_B64 0x6f
+#define SQ_DS_CMPST_RTN_B64 0x70
+#define SQ_DS_CMPST_RTN_F64 0x71
+#define SQ_DS_MIN_RTN_F64 0x72
+#define SQ_DS_MAX_RTN_F64 0x73
+#define SQ_DS_READ_B64 0x76
+#define SQ_DS_READ2_B64 0x77
+#define SQ_DS_READ2ST64_B64 0x78
+#define SQ_DS_CONDXCHG32_RTN_B64 0x7e
+#define SQ_DS_ADD_SRC2_U32 0x80
+#define SQ_DS_SUB_SRC2_U32 0x81
+#define SQ_DS_RSUB_SRC2_U32 0x82
+#define SQ_DS_INC_SRC2_U32 0x83
+#define SQ_DS_DEC_SRC2_U32 0x84
+#define SQ_DS_MIN_SRC2_I32 0x85
+#define SQ_DS_MAX_SRC2_I32 0x86
+#define SQ_DS_MIN_SRC2_U32 0x87
+#define SQ_DS_MAX_SRC2_U32 0x88
+#define SQ_DS_AND_SRC2_B32 0x89
+#define SQ_DS_OR_SRC2_B32 0x8a
+#define SQ_DS_XOR_SRC2_B32 0x8b
+#define SQ_DS_WRITE_SRC2_B32 0x8d
+#define SQ_DS_MIN_SRC2_F32 0x92
+#define SQ_DS_MAX_SRC2_F32 0x93
+#define SQ_DS_ADD_SRC2_U64 0xc0
+#define SQ_DS_SUB_SRC2_U64 0xc1
+#define SQ_DS_RSUB_SRC2_U64 0xc2
+#define SQ_DS_INC_SRC2_U64 0xc3
+#define SQ_DS_DEC_SRC2_U64 0xc4
+#define SQ_DS_MIN_SRC2_I64 0xc5
+#define SQ_DS_MAX_SRC2_I64 0xc6
+#define SQ_DS_MIN_SRC2_U64 0xc7
+#define SQ_DS_MAX_SRC2_U64 0xc8
+#define SQ_DS_AND_SRC2_B64 0xc9
+#define SQ_DS_OR_SRC2_B64 0xca
+#define SQ_DS_XOR_SRC2_B64 0xcb
+#define SQ_DS_WRITE_SRC2_B64 0xcd
+#define SQ_DS_MIN_SRC2_F64 0xd2
+#define SQ_DS_MAX_SRC2_F64 0xd3
+#define SQ_DS_WRITE_B96 0xde
+#define SQ_DS_WRITE_B128 0xdf
+#define SQ_DS_CONDXCHG32_RTN_B128 0xfd
+#define SQ_DS_READ_B96 0xfe
+#define SQ_DS_READ_B128 0xff
+#define SQ_SRC_SCC 0xfd
+#define SQ_OMOD_OFF 0x0
+#define SQ_OMOD_M2 0x1
+#define SQ_OMOD_M4 0x2
+#define SQ_OMOD_D2 0x3
+#define SQ_EXP_GDS0 0x18
+#define SQ_GS_OP_NOP 0x0
+#define SQ_GS_OP_CUT 0x1
+#define SQ_GS_OP_EMIT 0x2
+#define SQ_GS_OP_EMIT_CUT 0x3
+#define SQ_IMAGE_LOAD 0x0
+#define SQ_IMAGE_LOAD_MIP 0x1
+#define SQ_IMAGE_LOAD_PCK 0x2
+#define SQ_IMAGE_LOAD_PCK_SGN 0x3
+#define SQ_IMAGE_LOAD_MIP_PCK 0x4
+#define SQ_IMAGE_LOAD_MIP_PCK_SGN 0x5
+#define SQ_IMAGE_STORE 0x8
+#define SQ_IMAGE_STORE_MIP 0x9
+#define SQ_IMAGE_STORE_PCK 0xa
+#define SQ_IMAGE_STORE_MIP_PCK 0xb
+#define SQ_IMAGE_GET_RESINFO 0xe
+#define SQ_IMAGE_ATOMIC_SWAP 0xf
+#define SQ_IMAGE_ATOMIC_CMPSWAP 0x10
+#define SQ_IMAGE_ATOMIC_ADD 0x11
+#define SQ_IMAGE_ATOMIC_SUB 0x12
+#define SQ_IMAGE_ATOMIC_SMIN 0x14
+#define SQ_IMAGE_ATOMIC_UMIN 0x15
+#define SQ_IMAGE_ATOMIC_SMAX 0x16
+#define SQ_IMAGE_ATOMIC_UMAX 0x17
+#define SQ_IMAGE_ATOMIC_AND 0x18
+#define SQ_IMAGE_ATOMIC_OR 0x19
+#define SQ_IMAGE_ATOMIC_XOR 0x1a
+#define SQ_IMAGE_ATOMIC_INC 0x1b
+#define SQ_IMAGE_ATOMIC_DEC 0x1c
+#define SQ_IMAGE_ATOMIC_FCMPSWAP 0x1d
+#define SQ_IMAGE_ATOMIC_FMIN 0x1e
+#define SQ_IMAGE_ATOMIC_FMAX 0x1f
+#define SQ_IMAGE_SAMPLE 0x20
+#define SQ_IMAGE_SAMPLE_CL 0x21
+#define SQ_IMAGE_SAMPLE_D 0x22
+#define SQ_IMAGE_SAMPLE_D_CL 0x23
+#define SQ_IMAGE_SAMPLE_L 0x24
+#define SQ_IMAGE_SAMPLE_B 0x25
+#define SQ_IMAGE_SAMPLE_B_CL 0x26
+#define SQ_IMAGE_SAMPLE_LZ 0x27
+#define SQ_IMAGE_SAMPLE_C 0x28
+#define SQ_IMAGE_SAMPLE_C_CL 0x29
+#define SQ_IMAGE_SAMPLE_C_D 0x2a
+#define SQ_IMAGE_SAMPLE_C_D_CL 0x2b
+#define SQ_IMAGE_SAMPLE_C_L 0x2c
+#define SQ_IMAGE_SAMPLE_C_B 0x2d
+#define SQ_IMAGE_SAMPLE_C_B_CL 0x2e
+#define SQ_IMAGE_SAMPLE_C_LZ 0x2f
+#define SQ_IMAGE_SAMPLE_O 0x30
+#define SQ_IMAGE_SAMPLE_CL_O 0x31
+#define SQ_IMAGE_SAMPLE_D_O 0x32
+#define SQ_IMAGE_SAMPLE_D_CL_O 0x33
+#define SQ_IMAGE_SAMPLE_L_O 0x34
+#define SQ_IMAGE_SAMPLE_B_O 0x35
+#define SQ_IMAGE_SAMPLE_B_CL_O 0x36
+#define SQ_IMAGE_SAMPLE_LZ_O 0x37
+#define SQ_IMAGE_SAMPLE_C_O 0x38
+#define SQ_IMAGE_SAMPLE_C_CL_O 0x39
+#define SQ_IMAGE_SAMPLE_C_D_O 0x3a
+#define SQ_IMAGE_SAMPLE_C_D_CL_O 0x3b
+#define SQ_IMAGE_SAMPLE_C_L_O 0x3c
+#define SQ_IMAGE_SAMPLE_C_B_O 0x3d
+#define SQ_IMAGE_SAMPLE_C_B_CL_O 0x3e
+#define SQ_IMAGE_SAMPLE_C_LZ_O 0x3f
+#define SQ_IMAGE_GATHER4 0x40
+#define SQ_IMAGE_GATHER4_CL 0x41
+#define SQ_IMAGE_GATHER4_L 0x44
+#define SQ_IMAGE_GATHER4_B 0x45
+#define SQ_IMAGE_GATHER4_B_CL 0x46
+#define SQ_IMAGE_GATHER4_LZ 0x47
+#define SQ_IMAGE_GATHER4_C 0x48
+#define SQ_IMAGE_GATHER4_C_CL 0x49
+#define SQ_IMAGE_GATHER4_C_L 0x4c
+#define SQ_IMAGE_GATHER4_C_B 0x4d
+#define SQ_IMAGE_GATHER4_C_B_CL 0x4e
+#define SQ_IMAGE_GATHER4_C_LZ 0x4f
+#define SQ_IMAGE_GATHER4_O 0x50
+#define SQ_IMAGE_GATHER4_CL_O 0x51
+#define SQ_IMAGE_GATHER4_L_O 0x54
+#define SQ_IMAGE_GATHER4_B_O 0x55
+#define SQ_IMAGE_GATHER4_B_CL_O 0x56
+#define SQ_IMAGE_GATHER4_LZ_O 0x57
+#define SQ_IMAGE_GATHER4_C_O 0x58
+#define SQ_IMAGE_GATHER4_C_CL_O 0x59
+#define SQ_IMAGE_GATHER4_C_L_O 0x5c
+#define SQ_IMAGE_GATHER4_C_B_O 0x5d
+#define SQ_IMAGE_GATHER4_C_B_CL_O 0x5e
+#define SQ_IMAGE_GATHER4_C_LZ_O 0x5f
+#define SQ_IMAGE_GET_LOD 0x60
+#define SQ_IMAGE_SAMPLE_CD 0x68
+#define SQ_IMAGE_SAMPLE_CD_CL 0x69
+#define SQ_IMAGE_SAMPLE_C_CD 0x6a
+#define SQ_IMAGE_SAMPLE_C_CD_CL 0x6b
+#define SQ_IMAGE_SAMPLE_CD_O 0x6c
+#define SQ_IMAGE_SAMPLE_CD_CL_O 0x6d
+#define SQ_IMAGE_SAMPLE_C_CD_O 0x6e
+#define SQ_IMAGE_SAMPLE_C_CD_CL_O 0x6f
+#define SQ_IMAGE_RSRC256 0x7e
+#define SQ_IMAGE_SAMPLER 0x7f
+#define SQ_SRC_VCCZ 0xfb
+#define SQ_SRC_VGPR0 0x100
+#define SQ_DFMT_INVALID 0x0
+#define SQ_DFMT_8 0x1
+#define SQ_DFMT_16 0x2
+#define SQ_DFMT_8_8 0x3
+#define SQ_DFMT_32 0x4
+#define SQ_DFMT_16_16 0x5
+#define SQ_DFMT_10_11_11 0x6
+#define SQ_DFMT_11_11_10 0x7
+#define SQ_DFMT_10_10_10_2 0x8
+#define SQ_DFMT_2_10_10_10 0x9
+#define SQ_DFMT_8_8_8_8 0xa
+#define SQ_DFMT_32_32 0xb
+#define SQ_DFMT_16_16_16_16 0xc
+#define SQ_DFMT_32_32_32 0xd
+#define SQ_DFMT_32_32_32_32 0xe
+#define SQ_TBUFFER_LOAD_FORMAT_X 0x0
+#define SQ_TBUFFER_LOAD_FORMAT_XY 0x1
+#define SQ_TBUFFER_LOAD_FORMAT_XYZ 0x2
+#define SQ_TBUFFER_LOAD_FORMAT_XYZW 0x3
+#define SQ_TBUFFER_STORE_FORMAT_X 0x4
+#define SQ_TBUFFER_STORE_FORMAT_XY 0x5
+#define SQ_TBUFFER_STORE_FORMAT_XYZ 0x6
+#define SQ_TBUFFER_STORE_FORMAT_XYZW 0x7
+#define SQ_CHAN_X 0x0
+#define SQ_CHAN_Y 0x1
+#define SQ_CHAN_Z 0x2
+#define SQ_CHAN_W 0x3
+#define SQ_EXEC_LO 0x7e
+#define SQ_EXEC_HI 0x7f
+#define SQ_S_LOAD_DWORD 0x0
+#define SQ_S_LOAD_DWORDX2 0x1
+#define SQ_S_LOAD_DWORDX4 0x2
+#define SQ_S_LOAD_DWORDX8 0x3
+#define SQ_S_LOAD_DWORDX16 0x4
+#define SQ_S_BUFFER_LOAD_DWORD 0x8
+#define SQ_S_BUFFER_LOAD_DWORDX2 0x9
+#define SQ_S_BUFFER_LOAD_DWORDX4 0xa
+#define SQ_S_BUFFER_LOAD_DWORDX8 0xb
+#define SQ_S_BUFFER_LOAD_DWORDX16 0xc
+#define SQ_S_DCACHE_INV_VOL 0x1d
+#define SQ_S_MEMTIME 0x1e
+#define SQ_S_DCACHE_INV 0x1f
+#define SQ_V_NOP 0x0
+#define SQ_V_MOV_B32 0x1
+#define SQ_V_READFIRSTLANE_B32 0x2
+#define SQ_V_CVT_I32_F64 0x3
+#define SQ_V_CVT_F64_I32 0x4
+#define SQ_V_CVT_F32_I32 0x5
+#define SQ_V_CVT_F32_U32 0x6
+#define SQ_V_CVT_U32_F32 0x7
+#define SQ_V_CVT_I32_F32 0x8
+#define SQ_V_MOV_FED_B32 0x9
+#define SQ_V_CVT_F16_F32 0xa
+#define SQ_V_CVT_F32_F16 0xb
+#define SQ_V_CVT_RPI_I32_F32 0xc
+#define SQ_V_CVT_FLR_I32_F32 0xd
+#define SQ_V_CVT_OFF_F32_I4 0xe
+#define SQ_V_CVT_F32_F64 0xf
+#define SQ_V_CVT_F64_F32 0x10
+#define SQ_V_CVT_F32_UBYTE0 0x11
+#define SQ_V_CVT_F32_UBYTE1 0x12
+#define SQ_V_CVT_F32_UBYTE2 0x13
+#define SQ_V_CVT_F32_UBYTE3 0x14
+#define SQ_V_CVT_U32_F64 0x15
+#define SQ_V_CVT_F64_U32 0x16
+#define SQ_V_TRUNC_F64 0x17
+#define SQ_V_CEIL_F64 0x18
+#define SQ_V_RNDNE_F64 0x19
+#define SQ_V_FLOOR_F64 0x1a
+#define SQ_V_FRACT_F32 0x20
+#define SQ_V_TRUNC_F32 0x21
+#define SQ_V_CEIL_F32 0x22
+#define SQ_V_RNDNE_F32 0x23
+#define SQ_V_FLOOR_F32 0x24
+#define SQ_V_EXP_F32 0x25
+#define SQ_V_LOG_CLAMP_F32 0x26
+#define SQ_V_LOG_F32 0x27
+#define SQ_V_RCP_CLAMP_F32 0x28
+#define SQ_V_RCP_LEGACY_F32 0x29
+#define SQ_V_RCP_F32 0x2a
+#define SQ_V_RCP_IFLAG_F32 0x2b
+#define SQ_V_RSQ_CLAMP_F32 0x2c
+#define SQ_V_RSQ_LEGACY_F32 0x2d
+#define SQ_V_RSQ_F32 0x2e
+#define SQ_V_RCP_F64 0x2f
+#define SQ_V_RCP_CLAMP_F64 0x30
+#define SQ_V_RSQ_F64 0x31
+#define SQ_V_RSQ_CLAMP_F64 0x32
+#define SQ_V_SQRT_F32 0x33
+#define SQ_V_SQRT_F64 0x34
+#define SQ_V_SIN_F32 0x35
+#define SQ_V_COS_F32 0x36
+#define SQ_V_NOT_B32 0x37
+#define SQ_V_BFREV_B32 0x38
+#define SQ_V_FFBH_U32 0x39
+#define SQ_V_FFBL_B32 0x3a
+#define SQ_V_FFBH_I32 0x3b
+#define SQ_V_FREXP_EXP_I32_F64 0x3c
+#define SQ_V_FREXP_MANT_F64 0x3d
+#define SQ_V_FRACT_F64 0x3e
+#define SQ_V_FREXP_EXP_I32_F32 0x3f
+#define SQ_V_FREXP_MANT_F32 0x40
+#define SQ_V_CLREXCP 0x41
+#define SQ_V_MOVRELD_B32 0x42
+#define SQ_V_MOVRELS_B32 0x43
+#define SQ_V_MOVRELSD_B32 0x44
+#define SQ_V_LOG_LEGACY_F32 0x45
+#define SQ_V_EXP_LEGACY_F32 0x46
+#define SQ_NFMT_UNORM 0x0
+#define SQ_NFMT_SNORM 0x1
+#define SQ_NFMT_USCALED 0x2
+#define SQ_NFMT_SSCALED 0x3
+#define SQ_NFMT_UINT 0x4
+#define SQ_NFMT_SINT 0x5
+#define SQ_NFMT_SNORM_OGL 0x6
+#define SQ_NFMT_FLOAT 0x7
+#define SQ_V_OP1_OFFSET 0x180
+#define SQ_V_OP2_OFFSET 0x100
+#define SQ_V_OPC_OFFSET 0x0
+#define SQ_V_INTERP_P1_F32 0x0
+#define SQ_V_INTERP_P2_F32 0x1
+#define SQ_V_INTERP_MOV_F32 0x2
+#define SQ_S_NOP 0x0
+#define SQ_S_ENDPGM 0x1
+#define SQ_S_BRANCH 0x2
+#define SQ_S_CBRANCH_SCC0 0x4
+#define SQ_S_CBRANCH_SCC1 0x5
+#define SQ_S_CBRANCH_VCCZ 0x6
+#define SQ_S_CBRANCH_VCCNZ 0x7
+#define SQ_S_CBRANCH_EXECZ 0x8
+#define SQ_S_CBRANCH_EXECNZ 0x9
+#define SQ_S_BARRIER 0xa
+#define SQ_S_SETKILL 0xb
+#define SQ_S_WAITCNT 0xc
+#define SQ_S_SETHALT 0xd
+#define SQ_S_SLEEP 0xe
+#define SQ_S_SETPRIO 0xf
+#define SQ_S_SENDMSG 0x10
+#define SQ_S_SENDMSGHALT 0x11
+#define SQ_S_TRAP 0x12
+#define SQ_S_ICACHE_INV 0x13
+#define SQ_S_INCPERFLEVEL 0x14
+#define SQ_S_DECPERFLEVEL 0x15
+#define SQ_S_TTRACEDATA 0x16
+#define SQ_S_CBRANCH_CDBGSYS 0x17
+#define SQ_S_CBRANCH_CDBGUSER 0x18
+#define SQ_S_CBRANCH_CDBGSYS_OR_USER 0x19
+#define SQ_S_CBRANCH_CDBGSYS_AND_USER 0x1a
+#define SQ_SRC_LITERAL 0xff
+#define SQ_VCC_LO 0x6a
+#define SQ_VCC_HI 0x6b
+#define SQ_PARAM_P10 0x0
+#define SQ_PARAM_P20 0x1
+#define SQ_PARAM_P0 0x2
+#define SQ_SRC_LDS_DIRECT 0xfe
+#define SQ_FLAT_SCRATCH_LO 0x68
+#define SQ_FLAT_SCRATCH_HI 0x69
+#define SQ_V_CNDMASK_B32 0x0
+#define SQ_V_READLANE_B32 0x1
+#define SQ_V_WRITELANE_B32 0x2
+#define SQ_V_ADD_F32 0x3
+#define SQ_V_SUB_F32 0x4
+#define SQ_V_SUBREV_F32 0x5
+#define SQ_V_MAC_LEGACY_F32 0x6
+#define SQ_V_MUL_LEGACY_F32 0x7
+#define SQ_V_MUL_F32 0x8
+#define SQ_V_MUL_I32_I24 0x9
+#define SQ_V_MUL_HI_I32_I24 0xa
+#define SQ_V_MUL_U32_U24 0xb
+#define SQ_V_MUL_HI_U32_U24 0xc
+#define SQ_V_MIN_LEGACY_F32 0xd
+#define SQ_V_MAX_LEGACY_F32 0xe
+#define SQ_V_MIN_F32 0xf
+#define SQ_V_MAX_F32 0x10
+#define SQ_V_MIN_I32 0x11
+#define SQ_V_MAX_I32 0x12
+#define SQ_V_MIN_U32 0x13
+#define SQ_V_MAX_U32 0x14
+#define SQ_V_LSHR_B32 0x15
+#define SQ_V_LSHRREV_B32 0x16
+#define SQ_V_ASHR_I32 0x17
+#define SQ_V_ASHRREV_I32 0x18
+#define SQ_V_LSHL_B32 0x19
+#define SQ_V_LSHLREV_B32 0x1a
+#define SQ_V_AND_B32 0x1b
+#define SQ_V_OR_B32 0x1c
+#define SQ_V_XOR_B32 0x1d
+#define SQ_V_BFM_B32 0x1e
+#define SQ_V_MAC_F32 0x1f
+#define SQ_V_MADMK_F32 0x20
+#define SQ_V_MADAK_F32 0x21
+#define SQ_V_BCNT_U32_B32 0x22
+#define SQ_V_MBCNT_LO_U32_B32 0x23
+#define SQ_V_MBCNT_HI_U32_B32 0x24
+#define SQ_V_ADD_I32 0x25
+#define SQ_V_SUB_I32 0x26
+#define SQ_V_SUBREV_I32 0x27
+#define SQ_V_ADDC_U32 0x28
+#define SQ_V_SUBB_U32 0x29
+#define SQ_V_SUBBREV_U32 0x2a
+#define SQ_V_LDEXP_F32 0x2b
+#define SQ_V_CVT_PKACCUM_U8_F32 0x2c
+#define SQ_V_CVT_PKNORM_I16_F32 0x2d
+#define SQ_V_CVT_PKNORM_U16_F32 0x2e
+#define SQ_V_CVT_PKRTZ_F16_F32 0x2f
+#define SQ_V_CVT_PK_U16_U32 0x30
+#define SQ_V_CVT_PK_I16_I32 0x31
+#define SQ_FLAT_LOAD_UBYTE 0x8
+#define SQ_FLAT_LOAD_SBYTE 0x9
+#define SQ_FLAT_LOAD_USHORT 0xa
+#define SQ_FLAT_LOAD_SSHORT 0xb
+#define SQ_FLAT_LOAD_DWORD 0xc
+#define SQ_FLAT_LOAD_DWORDX2 0xd
+#define SQ_FLAT_LOAD_DWORDX4 0xe
+#define SQ_FLAT_LOAD_DWORDX3 0xf
+#define SQ_FLAT_STORE_BYTE 0x18
+#define SQ_FLAT_STORE_SHORT 0x1a
+#define SQ_FLAT_STORE_DWORD 0x1c
+#define SQ_FLAT_STORE_DWORDX2 0x1d
+#define SQ_FLAT_STORE_DWORDX4 0x1e
+#define SQ_FLAT_STORE_DWORDX3 0x1f
+#define SQ_FLAT_ATOMIC_SWAP 0x30
+#define SQ_FLAT_ATOMIC_CMPSWAP 0x31
+#define SQ_FLAT_ATOMIC_ADD 0x32
+#define SQ_FLAT_ATOMIC_SUB 0x33
+#define SQ_FLAT_ATOMIC_SMIN 0x35
+#define SQ_FLAT_ATOMIC_UMIN 0x36
+#define SQ_FLAT_ATOMIC_SMAX 0x37
+#define SQ_FLAT_ATOMIC_UMAX 0x38
+#define SQ_FLAT_ATOMIC_AND 0x39
+#define SQ_FLAT_ATOMIC_OR 0x3a
+#define SQ_FLAT_ATOMIC_XOR 0x3b
+#define SQ_FLAT_ATOMIC_INC 0x3c
+#define SQ_FLAT_ATOMIC_DEC 0x3d
+#define SQ_FLAT_ATOMIC_FCMPSWAP 0x3e
+#define SQ_FLAT_ATOMIC_FMIN 0x3f
+#define SQ_FLAT_ATOMIC_FMAX 0x40
+#define SQ_FLAT_ATOMIC_SWAP_X2 0x50
+#define SQ_FLAT_ATOMIC_CMPSWAP_X2 0x51
+#define SQ_FLAT_ATOMIC_ADD_X2 0x52
+#define SQ_FLAT_ATOMIC_SUB_X2 0x53
+#define SQ_FLAT_ATOMIC_SMIN_X2 0x55
+#define SQ_FLAT_ATOMIC_UMIN_X2 0x56
+#define SQ_FLAT_ATOMIC_SMAX_X2 0x57
+#define SQ_FLAT_ATOMIC_UMAX_X2 0x58
+#define SQ_FLAT_ATOMIC_AND_X2 0x59
+#define SQ_FLAT_ATOMIC_OR_X2 0x5a
+#define SQ_FLAT_ATOMIC_XOR_X2 0x5b
+#define SQ_FLAT_ATOMIC_INC_X2 0x5c
+#define SQ_FLAT_ATOMIC_DEC_X2 0x5d
+#define SQ_FLAT_ATOMIC_FCMPSWAP_X2 0x5e
+#define SQ_FLAT_ATOMIC_FMIN_X2 0x5f
+#define SQ_FLAT_ATOMIC_FMAX_X2 0x60
+#define SQ_S_CMP_EQ_I32 0x0
+#define SQ_S_CMP_LG_I32 0x1
+#define SQ_S_CMP_GT_I32 0x2
+#define SQ_S_CMP_GE_I32 0x3
+#define SQ_S_CMP_LT_I32 0x4
+#define SQ_S_CMP_LE_I32 0x5
+#define SQ_S_CMP_EQ_U32 0x6
+#define SQ_S_CMP_LG_U32 0x7
+#define SQ_S_CMP_GT_U32 0x8
+#define SQ_S_CMP_GE_U32 0x9
+#define SQ_S_CMP_LT_U32 0xa
+#define SQ_S_CMP_LE_U32 0xb
+#define SQ_S_BITCMP0_B32 0xc
+#define SQ_S_BITCMP1_B32 0xd
+#define SQ_S_BITCMP0_B64 0xe
+#define SQ_S_BITCMP1_B64 0xf
+#define SQ_S_SETVSKIP 0x10
+#define SQ_M0 0x7c
+#define SQ_V_MAD_LEGACY_F32 0x140
+#define SQ_V_MAD_F32 0x141
+#define SQ_V_MAD_I32_I24 0x142
+#define SQ_V_MAD_U32_U24 0x143
+#define SQ_V_CUBEID_F32 0x144
+#define SQ_V_CUBESC_F32 0x145
+#define SQ_V_CUBETC_F32 0x146
+#define SQ_V_CUBEMA_F32 0x147
+#define SQ_V_BFE_U32 0x148
+#define SQ_V_BFE_I32 0x149
+#define SQ_V_BFI_B32 0x14a
+#define SQ_V_FMA_F32 0x14b
+#define SQ_V_FMA_F64 0x14c
+#define SQ_V_LERP_U8 0x14d
+#define SQ_V_ALIGNBIT_B32 0x14e
+#define SQ_V_ALIGNBYTE_B32 0x14f
+#define SQ_V_MULLIT_F32 0x150
+#define SQ_V_MIN3_F32 0x151
+#define SQ_V_MIN3_I32 0x152
+#define SQ_V_MIN3_U32 0x153
+#define SQ_V_MAX3_F32 0x154
+#define SQ_V_MAX3_I32 0x155
+#define SQ_V_MAX3_U32 0x156
+#define SQ_V_MED3_F32 0x157
+#define SQ_V_MED3_I32 0x158
+#define SQ_V_MED3_U32 0x159
+#define SQ_V_SAD_U8 0x15a
+#define SQ_V_SAD_HI_U8 0x15b
+#define SQ_V_SAD_U16 0x15c
+#define SQ_V_SAD_U32 0x15d
+#define SQ_V_CVT_PK_U8_F32 0x15e
+#define SQ_V_DIV_FIXUP_F32 0x15f
+#define SQ_V_DIV_FIXUP_F64 0x160
+#define SQ_V_LSHL_B64 0x161
+#define SQ_V_LSHR_B64 0x162
+#define SQ_V_ASHR_I64 0x163
+#define SQ_V_ADD_F64 0x164
+#define SQ_V_MUL_F64 0x165
+#define SQ_V_MIN_F64 0x166
+#define SQ_V_MAX_F64 0x167
+#define SQ_V_LDEXP_F64 0x168
+#define SQ_V_MUL_LO_U32 0x169
+#define SQ_V_MUL_HI_U32 0x16a
+#define SQ_V_MUL_LO_I32 0x16b
+#define SQ_V_MUL_HI_I32 0x16c
+#define SQ_V_DIV_SCALE_F32 0x16d
+#define SQ_V_DIV_SCALE_F64 0x16e
+#define SQ_V_DIV_FMAS_F32 0x16f
+#define SQ_V_DIV_FMAS_F64 0x170
+#define SQ_V_MSAD_U8 0x171
+#define SQ_V_QSAD_PK_U16_U8 0x172
+#define SQ_V_MQSAD_PK_U16_U8 0x173
+#define SQ_V_TRIG_PREOP_F64 0x174
+#define SQ_V_MQSAD_U32_U8 0x175
+#define SQ_V_MAD_U64_U32 0x176
+#define SQ_V_MAD_I64_I32 0x177
+#define SQ_VCC_ALL 0x0
+#define SQ_SRC_EXECZ 0xfc
+#define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT 0x1
+#define SQ_SYSMSG_OP_REG_RD 0x2
+#define SQ_SYSMSG_OP_HOST_TRAP_ACK 0x3
+#define SQ_SYSMSG_OP_TTRACE_PC 0x4
+#define SQ_HW_REG_MODE 0x1
+#define SQ_HW_REG_STATUS 0x2
+#define SQ_HW_REG_TRAPSTS 0x3
+#define SQ_HW_REG_HW_ID 0x4
+#define SQ_HW_REG_GPR_ALLOC 0x5
+#define SQ_HW_REG_LDS_ALLOC 0x6
+#define SQ_HW_REG_IB_STS 0x7
+#define SQ_HW_REG_PC_LO 0x8
+#define SQ_HW_REG_PC_HI 0x9
+#define SQ_HW_REG_INST_DW0 0xa
+#define SQ_HW_REG_INST_DW1 0xb
+#define SQ_HW_REG_IB_DBG0 0xc
+#define SQ_S_ADD_U32 0x0
+#define SQ_S_SUB_U32 0x1
+#define SQ_S_ADD_I32 0x2
+#define SQ_S_SUB_I32 0x3
+#define SQ_S_ADDC_U32 0x4
+#define SQ_S_SUBB_U32 0x5
+#define SQ_S_MIN_I32 0x6
+#define SQ_S_MIN_U32 0x7
+#define SQ_S_MAX_I32 0x8
+#define SQ_S_MAX_U32 0x9
+#define SQ_S_CSELECT_B32 0xa
+#define SQ_S_CSELECT_B64 0xb
+#define SQ_S_AND_B32 0xe
+#define SQ_S_AND_B64 0xf
+#define SQ_S_OR_B32 0x10
+#define SQ_S_OR_B64 0x11
+#define SQ_S_XOR_B32 0x12
+#define SQ_S_XOR_B64 0x13
+#define SQ_S_ANDN2_B32 0x14
+#define SQ_S_ANDN2_B64 0x15
+#define SQ_S_ORN2_B32 0x16
+#define SQ_S_ORN2_B64 0x17
+#define SQ_S_NAND_B32 0x18
+#define SQ_S_NAND_B64 0x19
+#define SQ_S_NOR_B32 0x1a
+#define SQ_S_NOR_B64 0x1b
+#define SQ_S_XNOR_B32 0x1c
+#define SQ_S_XNOR_B64 0x1d
+#define SQ_S_LSHL_B32 0x1e
+#define SQ_S_LSHL_B64 0x1f
+#define SQ_S_LSHR_B32 0x20
+#define SQ_S_LSHR_B64 0x21
+#define SQ_S_ASHR_I32 0x22
+#define SQ_S_ASHR_I64 0x23
+#define SQ_S_BFM_B32 0x24
+#define SQ_S_BFM_B64 0x25
+#define SQ_S_MUL_I32 0x26
+#define SQ_S_BFE_U32 0x27
+#define SQ_S_BFE_I32 0x28
+#define SQ_S_BFE_U64 0x29
+#define SQ_S_BFE_I64 0x2a
+#define SQ_S_CBRANCH_G_FORK 0x2b
+#define SQ_S_ABSDIFF_I32 0x2c
+#define SQ_MSG_INTERRUPT 0x1
+#define SQ_MSG_GS 0x2
+#define SQ_MSG_GS_DONE 0x3
+#define SQ_MSG_SYSMSG 0xf
+typedef enum TEX_BORDER_COLOR_TYPE {
+ TEX_BorderColor_TransparentBlack = 0x0,
+ TEX_BorderColor_OpaqueBlack = 0x1,
+ TEX_BorderColor_OpaqueWhite = 0x2,
+ TEX_BorderColor_Register = 0x3,
+} TEX_BORDER_COLOR_TYPE;
+typedef enum TEX_CHROMA_KEY {
+ TEX_ChromaKey_Disabled = 0x0,
+ TEX_ChromaKey_Kill = 0x1,
+ TEX_ChromaKey_Blend = 0x2,
+ TEX_ChromaKey_RESERVED_3 = 0x3,
+} TEX_CHROMA_KEY;
+typedef enum TEX_CLAMP {
+ TEX_Clamp_Repeat = 0x0,
+ TEX_Clamp_Mirror = 0x1,
+ TEX_Clamp_ClampToLast = 0x2,
+ TEX_Clamp_MirrorOnceToLast = 0x3,
+ TEX_Clamp_ClampHalfToBorder = 0x4,
+ TEX_Clamp_MirrorOnceHalfToBorder = 0x5,
+ TEX_Clamp_ClampToBorder = 0x6,
+ TEX_Clamp_MirrorOnceToBorder = 0x7,
+} TEX_CLAMP;
+typedef enum TEX_COORD_TYPE {
+ TEX_CoordType_Unnormalized = 0x0,
+ TEX_CoordType_Normalized = 0x1,
+} TEX_COORD_TYPE;
+typedef enum TEX_DEPTH_COMPARE_FUNCTION {
+ TEX_DepthCompareFunction_Never = 0x0,
+ TEX_DepthCompareFunction_Less = 0x1,
+ TEX_DepthCompareFunction_Equal = 0x2,
+ TEX_DepthCompareFunction_LessEqual = 0x3,
+ TEX_DepthCompareFunction_Greater = 0x4,
+ TEX_DepthCompareFunction_NotEqual = 0x5,
+ TEX_DepthCompareFunction_GreaterEqual = 0x6,
+ TEX_DepthCompareFunction_Always = 0x7,
+} TEX_DEPTH_COMPARE_FUNCTION;
+typedef enum TEX_DIM {
+ TEX_Dim_1D = 0x0,
+ TEX_Dim_2D = 0x1,
+ TEX_Dim_3D = 0x2,
+ TEX_Dim_CubeMap = 0x3,
+ TEX_Dim_1DArray = 0x4,
+ TEX_Dim_2DArray = 0x5,
+ TEX_Dim_2D_MSAA = 0x6,
+ TEX_Dim_2DArray_MSAA = 0x7,
+} TEX_DIM;
+typedef enum TEX_FORMAT_COMP {
+ TEX_FormatComp_Unsigned = 0x0,
+ TEX_FormatComp_Signed = 0x1,
+ TEX_FormatComp_UnsignedBiased = 0x2,
+ TEX_FormatComp_RESERVED_3 = 0x3,
+} TEX_FORMAT_COMP;
+typedef enum TEX_MAX_ANISO_RATIO {
+ TEX_MaxAnisoRatio_1to1 = 0x0,
+ TEX_MaxAnisoRatio_2to1 = 0x1,
+ TEX_MaxAnisoRatio_4to1 = 0x2,
+ TEX_MaxAnisoRatio_8to1 = 0x3,
+ TEX_MaxAnisoRatio_16to1 = 0x4,
+ TEX_MaxAnisoRatio_RESERVED_5 = 0x5,
+ TEX_MaxAnisoRatio_RESERVED_6 = 0x6,
+ TEX_MaxAnisoRatio_RESERVED_7 = 0x7,
+} TEX_MAX_ANISO_RATIO;
+typedef enum TEX_MIP_FILTER {
+ TEX_MipFilter_None = 0x0,
+ TEX_MipFilter_Point = 0x1,
+ TEX_MipFilter_Linear = 0x2,
+ TEX_MipFilter_RESERVED_3 = 0x3,
+} TEX_MIP_FILTER;
+typedef enum TEX_REQUEST_SIZE {
+ TEX_RequestSize_32B = 0x0,
+ TEX_RequestSize_64B = 0x1,
+ TEX_RequestSize_128B = 0x2,
+ TEX_RequestSize_2X64B = 0x3,
+} TEX_REQUEST_SIZE;
+typedef enum TEX_SAMPLER_TYPE {
+ TEX_SamplerType_Invalid = 0x0,
+ TEX_SamplerType_Valid = 0x1,
+} TEX_SAMPLER_TYPE;
+typedef enum TEX_XY_FILTER {
+ TEX_XYFilter_Point = 0x0,
+ TEX_XYFilter_Linear = 0x1,
+ TEX_XYFilter_AnisoPoint = 0x2,
+ TEX_XYFilter_AnisoLinear = 0x3,
+} TEX_XY_FILTER;
+typedef enum TEX_Z_FILTER {
+ TEX_ZFilter_None = 0x0,
+ TEX_ZFilter_Point = 0x1,
+ TEX_ZFilter_Linear = 0x2,
+ TEX_ZFilter_RESERVED_3 = 0x3,
+} TEX_Z_FILTER;
+typedef enum VTX_CLAMP {
+ VTX_Clamp_ClampToZero = 0x0,
+ VTX_Clamp_ClampToNAN = 0x1,
+} VTX_CLAMP;
+typedef enum VTX_FETCH_TYPE {
+ VTX_FetchType_VertexData = 0x0,
+ VTX_FetchType_InstanceData = 0x1,
+ VTX_FetchType_NoIndexOffset = 0x2,
+ VTX_FetchType_RESERVED_3 = 0x3,
+} VTX_FETCH_TYPE;
+typedef enum VTX_FORMAT_COMP_ALL {
+ VTX_FormatCompAll_Unsigned = 0x0,
+ VTX_FormatCompAll_Signed = 0x1,
+} VTX_FORMAT_COMP_ALL;
+typedef enum VTX_MEM_REQUEST_SIZE {
+ VTX_MemRequestSize_32B = 0x0,
+ VTX_MemRequestSize_64B = 0x1,
+} VTX_MEM_REQUEST_SIZE;
+typedef enum TVX_DATA_FORMAT {
+ TVX_FMT_INVALID = 0x0,
+ TVX_FMT_8 = 0x1,
+ TVX_FMT_4_4 = 0x2,
+ TVX_FMT_3_3_2 = 0x3,
+ TVX_FMT_RESERVED_4 = 0x4,
+ TVX_FMT_16 = 0x5,
+ TVX_FMT_16_FLOAT = 0x6,
+ TVX_FMT_8_8 = 0x7,
+ TVX_FMT_5_6_5 = 0x8,
+ TVX_FMT_6_5_5 = 0x9,
+ TVX_FMT_1_5_5_5 = 0xa,
+ TVX_FMT_4_4_4_4 = 0xb,
+ TVX_FMT_5_5_5_1 = 0xc,
+ TVX_FMT_32 = 0xd,
+ TVX_FMT_32_FLOAT = 0xe,
+ TVX_FMT_16_16 = 0xf,
+ TVX_FMT_16_16_FLOAT = 0x10,
+ TVX_FMT_8_24 = 0x11,
+ TVX_FMT_8_24_FLOAT = 0x12,
+ TVX_FMT_24_8 = 0x13,
+ TVX_FMT_24_8_FLOAT = 0x14,
+ TVX_FMT_10_11_11 = 0x15,
+ TVX_FMT_10_11_11_FLOAT = 0x16,
+ TVX_FMT_11_11_10 = 0x17,
+ TVX_FMT_11_11_10_FLOAT = 0x18,
+ TVX_FMT_2_10_10_10 = 0x19,
+ TVX_FMT_8_8_8_8 = 0x1a,
+ TVX_FMT_10_10_10_2 = 0x1b,
+ TVX_FMT_X24_8_32_FLOAT = 0x1c,
+ TVX_FMT_32_32 = 0x1d,
+ TVX_FMT_32_32_FLOAT = 0x1e,
+ TVX_FMT_16_16_16_16 = 0x1f,
+ TVX_FMT_16_16_16_16_FLOAT = 0x20,
+ TVX_FMT_RESERVED_33 = 0x21,
+ TVX_FMT_32_32_32_32 = 0x22,
+ TVX_FMT_32_32_32_32_FLOAT = 0x23,
+ TVX_FMT_RESERVED_36 = 0x24,
+ TVX_FMT_1 = 0x25,
+ TVX_FMT_1_REVERSED = 0x26,
+ TVX_FMT_GB_GR = 0x27,
+ TVX_FMT_BG_RG = 0x28,
+ TVX_FMT_32_AS_8 = 0x29,
+ TVX_FMT_32_AS_8_8 = 0x2a,
+ TVX_FMT_5_9_9_9_SHAREDEXP = 0x2b,
+ TVX_FMT_8_8_8 = 0x2c,
+ TVX_FMT_16_16_16 = 0x2d,
+ TVX_FMT_16_16_16_FLOAT = 0x2e,
+ TVX_FMT_32_32_32 = 0x2f,
+ TVX_FMT_32_32_32_FLOAT = 0x30,
+ TVX_FMT_BC1 = 0x31,
+ TVX_FMT_BC2 = 0x32,
+ TVX_FMT_BC3 = 0x33,
+ TVX_FMT_BC4 = 0x34,
+ TVX_FMT_BC5 = 0x35,
+ TVX_FMT_APC0 = 0x36,
+ TVX_FMT_APC1 = 0x37,
+ TVX_FMT_APC2 = 0x38,
+ TVX_FMT_APC3 = 0x39,
+ TVX_FMT_APC4 = 0x3a,
+ TVX_FMT_APC5 = 0x3b,
+ TVX_FMT_APC6 = 0x3c,
+ TVX_FMT_APC7 = 0x3d,
+ TVX_FMT_CTX1 = 0x3e,
+ TVX_FMT_RESERVED_63 = 0x3f,
+} TVX_DATA_FORMAT;
+typedef enum TVX_DST_SEL {
+ TVX_DstSel_X = 0x0,
+ TVX_DstSel_Y = 0x1,
+ TVX_DstSel_Z = 0x2,
+ TVX_DstSel_W = 0x3,
+ TVX_DstSel_0f = 0x4,
+ TVX_DstSel_1f = 0x5,
+ TVX_DstSel_RESERVED_6 = 0x6,
+ TVX_DstSel_Mask = 0x7,
+} TVX_DST_SEL;
+typedef enum TVX_ENDIAN_SWAP {
+ TVX_EndianSwap_None = 0x0,
+ TVX_EndianSwap_8in16 = 0x1,
+ TVX_EndianSwap_8in32 = 0x2,
+ TVX_EndianSwap_8in64 = 0x3,
+} TVX_ENDIAN_SWAP;
+typedef enum TVX_INST {
+ TVX_Inst_NormalVertexFetch = 0x0,
+ TVX_Inst_SemanticVertexFetch = 0x1,
+ TVX_Inst_RESERVED_2 = 0x2,
+ TVX_Inst_LD = 0x3,
+ TVX_Inst_GetTextureResInfo = 0x4,
+ TVX_Inst_GetNumberOfSamples = 0x5,
+ TVX_Inst_GetLOD = 0x6,
+ TVX_Inst_GetGradientsH = 0x7,
+ TVX_Inst_GetGradientsV = 0x8,
+ TVX_Inst_SetTextureOffsets = 0x9,
+ TVX_Inst_KeepGradients = 0xa,
+ TVX_Inst_SetGradientsH = 0xb,
+ TVX_Inst_SetGradientsV = 0xc,
+ TVX_Inst_Pass = 0xd,
+ TVX_Inst_GetBufferResInfo = 0xe,
+ TVX_Inst_RESERVED_15 = 0xf,
+ TVX_Inst_Sample = 0x10,
+ TVX_Inst_Sample_L = 0x11,
+ TVX_Inst_Sample_LB = 0x12,
+ TVX_Inst_Sample_LZ = 0x13,
+ TVX_Inst_Sample_G = 0x14,
+ TVX_Inst_Gather4 = 0x15,
+ TVX_Inst_Sample_G_LB = 0x16,
+ TVX_Inst_Gather4_O = 0x17,
+ TVX_Inst_Sample_C = 0x18,
+ TVX_Inst_Sample_C_L = 0x19,
+ TVX_Inst_Sample_C_LB = 0x1a,
+ TVX_Inst_Sample_C_LZ = 0x1b,
+ TVX_Inst_Sample_C_G = 0x1c,
+ TVX_Inst_Gather4_C = 0x1d,
+ TVX_Inst_Sample_C_G_LB = 0x1e,
+ TVX_Inst_Gather4_C_O = 0x1f,
+} TVX_INST;
+typedef enum TVX_NUM_FORMAT_ALL {
+ TVX_NumFormatAll_Norm = 0x0,
+ TVX_NumFormatAll_Int = 0x1,
+ TVX_NumFormatAll_Scaled = 0x2,
+ TVX_NumFormatAll_RESERVED_3 = 0x3,
+} TVX_NUM_FORMAT_ALL;
+typedef enum TVX_SRC_SEL {
+ TVX_SrcSel_X = 0x0,
+ TVX_SrcSel_Y = 0x1,
+ TVX_SrcSel_Z = 0x2,
+ TVX_SrcSel_W = 0x3,
+ TVX_SrcSel_0f = 0x4,
+ TVX_SrcSel_1f = 0x5,
+} TVX_SRC_SEL;
+typedef enum TVX_SRF_MODE_ALL {
+ TVX_SRFModeAll_ZCMO = 0x0,
+ TVX_SRFModeAll_NZ = 0x1,
+} TVX_SRF_MODE_ALL;
+typedef enum TVX_TYPE {
+ TVX_Type_InvalidTextureResource = 0x0,
+ TVX_Type_InvalidVertexBuffer = 0x1,
+ TVX_Type_ValidTextureResource = 0x2,
+ TVX_Type_ValidVertexBuffer = 0x3,
+} TVX_TYPE;
+typedef enum TC_OP_MASKS {
+ TC_OP_MASK_FLUSH_DENROM = 0x8,
+ TC_OP_MASK_64 = 0x20,
+ TC_OP_MASK_NO_RTN = 0x40,
+} TC_OP_MASKS;
+typedef enum TC_OP {
+ TC_OP_READ = 0x0,
+ TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x1,
+ TC_OP_ATOMIC_FMIN_RTN_32 = 0x2,
+ TC_OP_ATOMIC_FMAX_RTN_32 = 0x3,
+ TC_OP_RESERVED_FOP_RTN_32_0 = 0x4,
+ TC_OP_RESERVED_FOP_RTN_32_1 = 0x5,
+ TC_OP_RESERVED_FOP_RTN_32_2 = 0x6,
+ TC_OP_ATOMIC_SWAP_RTN_32 = 0x7,
+ TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x8,
+ TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x9,
+ TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0xa,
+ TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0xb,
+ TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_0 = 0xc,
+ TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0xd,
+ TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0xe,
+ TC_OP_ATOMIC_ADD_RTN_32 = 0xf,
+ TC_OP_ATOMIC_SUB_RTN_32 = 0x10,
+ TC_OP_ATOMIC_SMIN_RTN_32 = 0x11,
+ TC_OP_ATOMIC_UMIN_RTN_32 = 0x12,
+ TC_OP_ATOMIC_SMAX_RTN_32 = 0x13,
+ TC_OP_ATOMIC_UMAX_RTN_32 = 0x14,
+ TC_OP_ATOMIC_AND_RTN_32 = 0x15,
+ TC_OP_ATOMIC_OR_RTN_32 = 0x16,
+ TC_OP_ATOMIC_XOR_RTN_32 = 0x17,
+ TC_OP_ATOMIC_INC_RTN_32 = 0x18,
+ TC_OP_ATOMIC_DEC_RTN_32 = 0x19,
+ TC_OP_WBINVL1_VOL = 0x1a,
+ TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x1b,
+ TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x1c,
+ TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x1d,
+ TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x1e,
+ TC_OP_RESERVED_NON_FLOAT_RTN_32_4 = 0x1f,
+ TC_OP_WRITE = 0x20,
+ TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x21,
+ TC_OP_ATOMIC_FMIN_RTN_64 = 0x22,
+ TC_OP_ATOMIC_FMAX_RTN_64 = 0x23,
+ TC_OP_RESERVED_FOP_RTN_64_0 = 0x24,
+ TC_OP_RESERVED_FOP_RTN_64_1 = 0x25,
+ TC_OP_RESERVED_FOP_RTN_64_2 = 0x26,
+ TC_OP_ATOMIC_SWAP_RTN_64 = 0x27,
+ TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x28,
+ TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x29,
+ TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x2a,
+ TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x2b,
+ TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x2c,
+ TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x2d,
+ TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_2 = 0x2e,
+ TC_OP_ATOMIC_ADD_RTN_64 = 0x2f,
+ TC_OP_ATOMIC_SUB_RTN_64 = 0x30,
+ TC_OP_ATOMIC_SMIN_RTN_64 = 0x31,
+ TC_OP_ATOMIC_UMIN_RTN_64 = 0x32,
+ TC_OP_ATOMIC_SMAX_RTN_64 = 0x33,
+ TC_OP_ATOMIC_UMAX_RTN_64 = 0x34,
+ TC_OP_ATOMIC_AND_RTN_64 = 0x35,
+ TC_OP_ATOMIC_OR_RTN_64 = 0x36,
+ TC_OP_ATOMIC_XOR_RTN_64 = 0x37,
+ TC_OP_ATOMIC_INC_RTN_64 = 0x38,
+ TC_OP_ATOMIC_DEC_RTN_64 = 0x39,
+ TC_OP_WBL2_VOL = 0x3a,
+ TC_OP_RESERVED_NON_FLOAT_RTN_64_0 = 0x3b,
+ TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x3c,
+ TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x3d,
+ TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x3e,
+ TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x3f,
+ TC_OP_WBINVL1 = 0x40,
+ TC_OP_ATOMIC_FCMPSWAP_32 = 0x41,
+ TC_OP_ATOMIC_FMIN_32 = 0x42,
+ TC_OP_ATOMIC_FMAX_32 = 0x43,
+ TC_OP_RESERVED_FOP_32_0 = 0x44,
+ TC_OP_RESERVED_FOP_32_1 = 0x45,
+ TC_OP_RESERVED_FOP_32_2 = 0x46,
+ TC_OP_ATOMIC_SWAP_32 = 0x47,
+ TC_OP_ATOMIC_CMPSWAP_32 = 0x48,
+ TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x49,
+ TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x4a,
+ TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x4b,
+ TC_OP_RESERVED_FOP_FLUSH_DENORM_32_0 = 0x4c,
+ TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 0x4d,
+ TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x4e,
+ TC_OP_ATOMIC_ADD_32 = 0x4f,
+ TC_OP_ATOMIC_SUB_32 = 0x50,
+ TC_OP_ATOMIC_SMIN_32 = 0x51,
+ TC_OP_ATOMIC_UMIN_32 = 0x52,
+ TC_OP_ATOMIC_SMAX_32 = 0x53,
+ TC_OP_ATOMIC_UMAX_32 = 0x54,
+ TC_OP_ATOMIC_AND_32 = 0x55,
+ TC_OP_ATOMIC_OR_32 = 0x56,
+ TC_OP_ATOMIC_XOR_32 = 0x57,
+ TC_OP_ATOMIC_INC_32 = 0x58,
+ TC_OP_ATOMIC_DEC_32 = 0x59,
+ TC_OP_INVL2_VOL = 0x5a,
+ TC_OP_RESERVED_NON_FLOAT_32_0 = 0x5b,
+ TC_OP_RESERVED_NON_FLOAT_32_1 = 0x5c,
+ TC_OP_RESERVED_NON_FLOAT_32_2 = 0x5d,
+ TC_OP_RESERVED_NON_FLOAT_32_3 = 0x5e,
+ TC_OP_RESERVED_NON_FLOAT_32_4 = 0x5f,
+ TC_OP_WBINVL2 = 0x60,
+ TC_OP_ATOMIC_FCMPSWAP_64 = 0x61,
+ TC_OP_ATOMIC_FMIN_64 = 0x62,
+ TC_OP_ATOMIC_FMAX_64 = 0x63,
+ TC_OP_RESERVED_FOP_64_0 = 0x64,
+ TC_OP_RESERVED_FOP_64_1 = 0x65,
+ TC_OP_RESERVED_FOP_64_2 = 0x66,
+ TC_OP_ATOMIC_SWAP_64 = 0x67,
+ TC_OP_ATOMIC_CMPSWAP_64 = 0x68,
+ TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x69,
+ TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x6a,
+ TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x6b,
+ TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x6c,
+ TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x6d,
+ TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x6e,
+ TC_OP_ATOMIC_ADD_64 = 0x6f,
+ TC_OP_ATOMIC_SUB_64 = 0x70,
+ TC_OP_ATOMIC_SMIN_64 = 0x71,
+ TC_OP_ATOMIC_UMIN_64 = 0x72,
+ TC_OP_ATOMIC_SMAX_64 = 0x73,
+ TC_OP_ATOMIC_UMAX_64 = 0x74,
+ TC_OP_ATOMIC_AND_64 = 0x75,
+ TC_OP_ATOMIC_OR_64 = 0x76,
+ TC_OP_ATOMIC_XOR_64 = 0x77,
+ TC_OP_ATOMIC_INC_64 = 0x78,
+ TC_OP_ATOMIC_DEC_64 = 0x79,
+ TC_OP_INVL1L2_VOL = 0x7a,
+ TC_OP_RESERVED_NON_FLOAT_64_0 = 0x7b,
+ TC_OP_RESERVED_NON_FLOAT_64_1 = 0x7c,
+ TC_OP_RESERVED_NON_FLOAT_64_2 = 0x7d,
+ TC_OP_RESERVED_NON_FLOAT_64_3 = 0x7e,
+ TC_OP_RESERVED_NON_FLOAT_64_4 = 0x7f,
+} TC_OP;
+typedef enum TC_CHUB_REQ_CREDITS_ENUM {
+ TC_CHUB_REQ_CREDITS = 0x10,
+} TC_CHUB_REQ_CREDITS_ENUM;
+typedef enum CHUB_TC_RET_CREDITS_ENUM {
+ CHUB_TC_RET_CREDITS = 0x20,
+} CHUB_TC_RET_CREDITS_ENUM;
+typedef enum TC_NACKS {
+ TC_NACK_NO_FAULT = 0x0,
+ TC_NACK_PAGE_FAULT = 0x1,
+ TC_NACK_PROTECTION_FAULT = 0x2,
+ TC_NACK_DATA_ERROR = 0x3,
+} TC_NACKS;
+typedef enum TCC_PERF_SEL {
+ TCC_PERF_SEL_NONE = 0x0,
+ TCC_PERF_SEL_CYCLE = 0x1,
+ TCC_PERF_SEL_BUSY = 0x2,
+ TCC_PERF_SEL_REQ = 0x3,
+ TCC_PERF_SEL_STREAMING_REQ = 0x4,
+ TCC_PERF_SEL_READ = 0x5,
+ TCC_PERF_SEL_WRITE = 0x6,
+ TCC_PERF_SEL_ATOMIC = 0x7,
+ TCC_PERF_SEL_WBINVL2 = 0x8,
+ TCC_PERF_SEL_WBINVL2_CYCLE = 0x9,
+ TCC_PERF_SEL_HIT = 0xa,
+ TCC_PERF_SEL_MISS = 0xb,
+ TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT = 0xc,
+ TCC_PERF_SEL_FULLY_WRITTEN_HIT = 0xd,
+ TCC_PERF_SEL_WRITEBACK = 0xe,
+ TCC_PERF_SEL_LATENCY_FIFO_FULL = 0xf,
+ TCC_PERF_SEL_SRC_FIFO_FULL = 0x10,
+ TCC_PERF_SEL_HOLE_FIFO_FULL = 0x11,
+ TCC_PERF_SEL_MC_WRREQ = 0x12,
+ TCC_PERF_SEL_MC_WRREQ_STALL = 0x13,
+ TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL = 0x14,
+ TCC_PERF_SEL_MC_WRREQ_MC_HALT_STALL = 0x15,
+ TCC_PERF_SEL_TOO_MANY_MC_WRREQS_STALL = 0x16,
+ TCC_PERF_SEL_MC_WRREQ_LEVEL = 0x17,
+ TCC_PERF_SEL_MC_RDREQ = 0x18,
+ TCC_PERF_SEL_MC_RDREQ_CREDIT_STALL = 0x19,
+ TCC_PERF_SEL_MC_RDREQ_MC_HALT_STALL = 0x1a,
+ TCC_PERF_SEL_MC_RDREQ_LEVEL = 0x1b,
+ TCC_PERF_SEL_TAG_STALL = 0x1c,
+ TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL = 0x1d,
+ TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x1e,
+ TCC_PERF_SEL_READ_RETURN_TIMEOUT = 0x1f,
+ TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT = 0x20,
+ TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE = 0x21,
+ TCC_PERF_SEL_BUBBLE = 0x22,
+ TCC_PERF_SEL_RETURN_ACK = 0x23,
+ TCC_PERF_SEL_RETURN_DATA = 0x24,
+ TCC_PERF_SEL_RETURN_HOLE = 0x25,
+ TCC_PERF_SEL_RETURN_ACK_HOLE = 0x26,
+ TCC_PERF_SEL_IB_STALL = 0x27,
+ TCC_PERF_SEL_TCA_LEVEL = 0x28,
+ TCC_PERF_SEL_HOLE_LEVEL = 0x29,
+ TCC_PERF_SEL_MC_RDRET_NACK = 0x2a,
+ TCC_PERF_SEL_MC_WRRET_NACK = 0x2b,
+ TCC_PERF_SEL_EXE_REQ = 0x2c,
+ TCC_PERF_SEL_CLIENT0_REQ = 0x40,
+ TCC_PERF_SEL_CLIENT1_REQ = 0x41,
+ TCC_PERF_SEL_CLIENT2_REQ = 0x42,
+ TCC_PERF_SEL_CLIENT3_REQ = 0x43,
+ TCC_PERF_SEL_CLIENT4_REQ = 0x44,
+ TCC_PERF_SEL_CLIENT5_REQ = 0x45,
+ TCC_PERF_SEL_CLIENT6_REQ = 0x46,
+ TCC_PERF_SEL_CLIENT7_REQ = 0x47,
+ TCC_PERF_SEL_CLIENT8_REQ = 0x48,
+ TCC_PERF_SEL_CLIENT9_REQ = 0x49,
+ TCC_PERF_SEL_CLIENT10_REQ = 0x4a,
+ TCC_PERF_SEL_CLIENT11_REQ = 0x4b,
+ TCC_PERF_SEL_CLIENT12_REQ = 0x4c,
+ TCC_PERF_SEL_CLIENT13_REQ = 0x4d,
+ TCC_PERF_SEL_CLIENT14_REQ = 0x4e,
+ TCC_PERF_SEL_CLIENT15_REQ = 0x4f,
+ TCC_PERF_SEL_CLIENT16_REQ = 0x50,
+ TCC_PERF_SEL_CLIENT17_REQ = 0x51,
+ TCC_PERF_SEL_CLIENT18_REQ = 0x52,
+ TCC_PERF_SEL_CLIENT19_REQ = 0x53,
+ TCC_PERF_SEL_CLIENT20_REQ = 0x54,
+ TCC_PERF_SEL_CLIENT21_REQ = 0x55,
+ TCC_PERF_SEL_CLIENT22_REQ = 0x56,
+ TCC_PERF_SEL_CLIENT23_REQ = 0x57,
+ TCC_PERF_SEL_CLIENT24_REQ = 0x58,
+ TCC_PERF_SEL_CLIENT25_REQ = 0x59,
+ TCC_PERF_SEL_CLIENT26_REQ = 0x5a,
+ TCC_PERF_SEL_CLIENT27_REQ = 0x5b,
+ TCC_PERF_SEL_CLIENT28_REQ = 0x5c,
+ TCC_PERF_SEL_CLIENT29_REQ = 0x5d,
+ TCC_PERF_SEL_CLIENT30_REQ = 0x5e,
+ TCC_PERF_SEL_CLIENT31_REQ = 0x5f,
+ TCC_PERF_SEL_CLIENT32_REQ = 0x60,
+ TCC_PERF_SEL_CLIENT33_REQ = 0x61,
+ TCC_PERF_SEL_CLIENT34_REQ = 0x62,
+ TCC_PERF_SEL_CLIENT35_REQ = 0x63,
+ TCC_PERF_SEL_CLIENT36_REQ = 0x64,
+ TCC_PERF_SEL_CLIENT37_REQ = 0x65,
+ TCC_PERF_SEL_CLIENT38_REQ = 0x66,
+ TCC_PERF_SEL_CLIENT39_REQ = 0x67,
+ TCC_PERF_SEL_CLIENT40_REQ = 0x68,
+ TCC_PERF_SEL_CLIENT41_REQ = 0x69,
+ TCC_PERF_SEL_CLIENT42_REQ = 0x6a,
+ TCC_PERF_SEL_CLIENT43_REQ = 0x6b,
+ TCC_PERF_SEL_CLIENT44_REQ = 0x6c,
+ TCC_PERF_SEL_CLIENT45_REQ = 0x6d,
+ TCC_PERF_SEL_CLIENT46_REQ = 0x6e,
+ TCC_PERF_SEL_CLIENT47_REQ = 0x6f,
+ TCC_PERF_SEL_CLIENT48_REQ = 0x70,
+ TCC_PERF_SEL_CLIENT49_REQ = 0x71,
+ TCC_PERF_SEL_CLIENT50_REQ = 0x72,
+ TCC_PERF_SEL_CLIENT51_REQ = 0x73,
+ TCC_PERF_SEL_CLIENT52_REQ = 0x74,
+ TCC_PERF_SEL_CLIENT53_REQ = 0x75,
+ TCC_PERF_SEL_CLIENT54_REQ = 0x76,
+ TCC_PERF_SEL_CLIENT55_REQ = 0x77,
+ TCC_PERF_SEL_CLIENT56_REQ = 0x78,
+ TCC_PERF_SEL_CLIENT57_REQ = 0x79,
+ TCC_PERF_SEL_CLIENT58_REQ = 0x7a,
+ TCC_PERF_SEL_CLIENT59_REQ = 0x7b,
+ TCC_PERF_SEL_CLIENT60_REQ = 0x7c,
+ TCC_PERF_SEL_CLIENT61_REQ = 0x7d,
+ TCC_PERF_SEL_CLIENT62_REQ = 0x7e,
+ TCC_PERF_SEL_CLIENT63_REQ = 0x7f,
+ TCC_PERF_SEL_NORMAL_WRITEBACK = 0x80,
+ TCC_PERF_SEL_TC_OP_WBL2_VOL_WRITEBACK = 0x81,
+ TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK = 0x82,
+ TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK = 0x83,
+ TCC_PERF_SEL_NORMAL_EVICT = 0x84,
+ TCC_PERF_SEL_TC_OP_INVL2_VOL_EVICT = 0x85,
+ TCC_PERF_SEL_TC_OP_INVL1L2_VOL_EVICT = 0x86,
+ TCC_PERF_SEL_TC_OP_WBL2_VOL_EVICT = 0x87,
+ TCC_PERF_SEL_TC_OP_WBINVL2_EVICT = 0x88,
+ TCC_PERF_SEL_ALL_TC_OP_INV_EVICT = 0x89,
+ TCC_PERF_SEL_ALL_TC_OP_INV_VOL_EVICT = 0x8a,
+ TCC_PERF_SEL_TC_OP_WBL2_VOL_CYCLE = 0x8b,
+ TCC_PERF_SEL_TC_OP_INVL2_VOL_CYCLE = 0x8c,
+ TCC_PERF_SEL_TC_OP_INVL1L2_VOL_CYCLE = 0x8d,
+ TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE = 0x8e,
+ TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE = 0x8f,
+ TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_CYCLE = 0x90,
+ TCC_PERF_SEL_TC_OP_WBL2_VOL_START = 0x91,
+ TCC_PERF_SEL_TC_OP_INVL2_VOL_START = 0x92,
+ TCC_PERF_SEL_TC_OP_INVL1L2_VOL_START = 0x93,
+ TCC_PERF_SEL_TC_OP_WBINVL2_START = 0x94,
+ TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 0x95,
+ TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 0x96,
+ TCC_PERF_SEL_TC_OP_WBL2_VOL_FINISH = 0x97,
+ TCC_PERF_SEL_TC_OP_INVL2_VOL_FINISH = 0x98,
+ TCC_PERF_SEL_TC_OP_INVL1L2_VOL_FINISH = 0x99,
+ TCC_PERF_SEL_TC_OP_WBINVL2_FINISH = 0x9a,
+ TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH = 0x9b,
+ TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_FINISH = 0x9c,
+ TCC_PERF_SEL_VOL_MC_WRREQ = 0x9d,
+ TCC_PERF_SEL_VOL_MC_RDREQ = 0x9e,
+ TCC_PERF_SEL_VOL_REQ = 0x9f,
+} TCC_PERF_SEL;
+typedef enum TCA_PERF_SEL {
+ TCA_PERF_SEL_NONE = 0x0,
+ TCA_PERF_SEL_CYCLE = 0x1,
+ TCA_PERF_SEL_BUSY = 0x2,
+ TCA_PERF_SEL_FORCED_HOLE_TCC0 = 0x3,
+ TCA_PERF_SEL_FORCED_HOLE_TCC1 = 0x4,
+ TCA_PERF_SEL_FORCED_HOLE_TCC2 = 0x5,
+ TCA_PERF_SEL_FORCED_HOLE_TCC3 = 0x6,
+ TCA_PERF_SEL_FORCED_HOLE_TCC4 = 0x7,
+ TCA_PERF_SEL_FORCED_HOLE_TCC5 = 0x8,
+ TCA_PERF_SEL_FORCED_HOLE_TCC6 = 0x9,
+ TCA_PERF_SEL_FORCED_HOLE_TCC7 = 0xa,
+ TCA_PERF_SEL_REQ_TCC0 = 0xb,
+ TCA_PERF_SEL_REQ_TCC1 = 0xc,
+ TCA_PERF_SEL_REQ_TCC2 = 0xd,
+ TCA_PERF_SEL_REQ_TCC3 = 0xe,
+ TCA_PERF_SEL_REQ_TCC4 = 0xf,
+ TCA_PERF_SEL_REQ_TCC5 = 0x10,
+ TCA_PERF_SEL_REQ_TCC6 = 0x11,
+ TCA_PERF_SEL_REQ_TCC7 = 0x12,
+ TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0 = 0x13,
+ TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1 = 0x14,
+ TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2 = 0x15,
+ TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3 = 0x16,
+ TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4 = 0x17,
+ TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5 = 0x18,
+ TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6 = 0x19,
+ TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7 = 0x1a,
+ TCA_PERF_SEL_CROSSBAR_STALL_TCC0 = 0x1b,
+ TCA_PERF_SEL_CROSSBAR_STALL_TCC1 = 0x1c,
+ TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 0x1d,
+ TCA_PERF_SEL_CROSSBAR_STALL_TCC3 = 0x1e,
+ TCA_PERF_SEL_CROSSBAR_STALL_TCC4 = 0x1f,
+ TCA_PERF_SEL_CROSSBAR_STALL_TCC5 = 0x20,
+ TCA_PERF_SEL_CROSSBAR_STALL_TCC6 = 0x21,
+ TCA_PERF_SEL_CROSSBAR_STALL_TCC7 = 0x22,
+ TCA_PERF_SEL_FORCED_HOLE_TCS = 0x23,
+ TCA_PERF_SEL_REQ_TCS = 0x24,
+ TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCS = 0x25,
+ TCA_PERF_SEL_CROSSBAR_STALL_TCS = 0x26,
+} TCA_PERF_SEL;
+typedef enum TCS_PERF_SEL {
+ TCS_PERF_SEL_NONE = 0x0,
+ TCS_PERF_SEL_CYCLE = 0x1,
+ TCS_PERF_SEL_BUSY = 0x2,
+ TCS_PERF_SEL_REQ = 0x3,
+ TCS_PERF_SEL_READ = 0x4,
+ TCS_PERF_SEL_WRITE = 0x5,
+ TCS_PERF_SEL_ATOMIC = 0x6,
+ TCS_PERF_SEL_HOLE_FIFO_FULL = 0x7,
+ TCS_PERF_SEL_REQ_FIFO_FULL = 0x8,
+ TCS_PERF_SEL_REQ_CREDIT_STALL = 0x9,
+ TCS_PERF_SEL_REQ_NO_SRC_DATA_STALL = 0xa,
+ TCS_PERF_SEL_REQ_STALL = 0xb,
+ TCS_PERF_SEL_TCS_CHUB_REQ_SEND = 0xc,
+ TCS_PERF_SEL_CHUB_TCS_RET_SEND = 0xd,
+ TCS_PERF_SEL_RETURN_ACK = 0xe,
+ TCS_PERF_SEL_RETURN_DATA = 0xf,
+ TCS_PERF_SEL_IB_TOTAL_REQUESTS_STALL = 0x10,
+ TCS_PERF_SEL_IB_STALL = 0x11,
+ TCS_PERF_SEL_TCA_LEVEL = 0x12,
+ TCS_PERF_SEL_HOLE_LEVEL = 0x13,
+ TCS_PERF_SEL_CHUB_LEVEL = 0x14,
+ TCS_PERF_SEL_CLIENT0_REQ = 0x40,
+ TCS_PERF_SEL_CLIENT1_REQ = 0x41,
+ TCS_PERF_SEL_CLIENT2_REQ = 0x42,
+ TCS_PERF_SEL_CLIENT3_REQ = 0x43,
+ TCS_PERF_SEL_CLIENT4_REQ = 0x44,
+ TCS_PERF_SEL_CLIENT5_REQ = 0x45,
+ TCS_PERF_SEL_CLIENT6_REQ = 0x46,
+ TCS_PERF_SEL_CLIENT7_REQ = 0x47,
+ TCS_PERF_SEL_CLIENT8_REQ = 0x48,
+ TCS_PERF_SEL_CLIENT9_REQ = 0x49,
+ TCS_PERF_SEL_CLIENT10_REQ = 0x4a,
+ TCS_PERF_SEL_CLIENT11_REQ = 0x4b,
+ TCS_PERF_SEL_CLIENT12_REQ = 0x4c,
+ TCS_PERF_SEL_CLIENT13_REQ = 0x4d,
+ TCS_PERF_SEL_CLIENT14_REQ = 0x4e,
+ TCS_PERF_SEL_CLIENT15_REQ = 0x4f,
+ TCS_PERF_SEL_CLIENT16_REQ = 0x50,
+ TCS_PERF_SEL_CLIENT17_REQ = 0x51,
+ TCS_PERF_SEL_CLIENT18_REQ = 0x52,
+ TCS_PERF_SEL_CLIENT19_REQ = 0x53,
+ TCS_PERF_SEL_CLIENT20_REQ = 0x54,
+ TCS_PERF_SEL_CLIENT21_REQ = 0x55,
+ TCS_PERF_SEL_CLIENT22_REQ = 0x56,
+ TCS_PERF_SEL_CLIENT23_REQ = 0x57,
+ TCS_PERF_SEL_CLIENT24_REQ = 0x58,
+ TCS_PERF_SEL_CLIENT25_REQ = 0x59,
+ TCS_PERF_SEL_CLIENT26_REQ = 0x5a,
+ TCS_PERF_SEL_CLIENT27_REQ = 0x5b,
+ TCS_PERF_SEL_CLIENT28_REQ = 0x5c,
+ TCS_PERF_SEL_CLIENT29_REQ = 0x5d,
+ TCS_PERF_SEL_CLIENT30_REQ = 0x5e,
+ TCS_PERF_SEL_CLIENT31_REQ = 0x5f,
+ TCS_PERF_SEL_CLIENT32_REQ = 0x60,
+ TCS_PERF_SEL_CLIENT33_REQ = 0x61,
+ TCS_PERF_SEL_CLIENT34_REQ = 0x62,
+ TCS_PERF_SEL_CLIENT35_REQ = 0x63,
+ TCS_PERF_SEL_CLIENT36_REQ = 0x64,
+ TCS_PERF_SEL_CLIENT37_REQ = 0x65,
+ TCS_PERF_SEL_CLIENT38_REQ = 0x66,
+ TCS_PERF_SEL_CLIENT39_REQ = 0x67,
+ TCS_PERF_SEL_CLIENT40_REQ = 0x68,
+ TCS_PERF_SEL_CLIENT41_REQ = 0x69,
+ TCS_PERF_SEL_CLIENT42_REQ = 0x6a,
+ TCS_PERF_SEL_CLIENT43_REQ = 0x6b,
+ TCS_PERF_SEL_CLIENT44_REQ = 0x6c,
+ TCS_PERF_SEL_CLIENT45_REQ = 0x6d,
+ TCS_PERF_SEL_CLIENT46_REQ = 0x6e,
+ TCS_PERF_SEL_CLIENT47_REQ = 0x6f,
+ TCS_PERF_SEL_CLIENT48_REQ = 0x70,
+ TCS_PERF_SEL_CLIENT49_REQ = 0x71,
+ TCS_PERF_SEL_CLIENT50_REQ = 0x72,
+ TCS_PERF_SEL_CLIENT51_REQ = 0x73,
+ TCS_PERF_SEL_CLIENT52_REQ = 0x74,
+ TCS_PERF_SEL_CLIENT53_REQ = 0x75,
+ TCS_PERF_SEL_CLIENT54_REQ = 0x76,
+ TCS_PERF_SEL_CLIENT55_REQ = 0x77,
+ TCS_PERF_SEL_CLIENT56_REQ = 0x78,
+ TCS_PERF_SEL_CLIENT57_REQ = 0x79,
+ TCS_PERF_SEL_CLIENT58_REQ = 0x7a,
+ TCS_PERF_SEL_CLIENT59_REQ = 0x7b,
+ TCS_PERF_SEL_CLIENT60_REQ = 0x7c,
+ TCS_PERF_SEL_CLIENT61_REQ = 0x7d,
+ TCS_PERF_SEL_CLIENT62_REQ = 0x7e,
+ TCS_PERF_SEL_CLIENT63_REQ = 0x7f,
+} TCS_PERF_SEL;
+typedef enum TA_TC_ADDR_MODES {
+ TA_TC_ADDR_MODE_DEFAULT = 0x0,
+ TA_TC_ADDR_MODE_COMP0 = 0x1,
+ TA_TC_ADDR_MODE_COMP1 = 0x2,
+ TA_TC_ADDR_MODE_COMP2 = 0x3,
+ TA_TC_ADDR_MODE_COMP3 = 0x4,
+ TA_TC_ADDR_MODE_UNALIGNED = 0x5,
+ TA_TC_ADDR_MODE_BORDER_COLOR = 0x6,
+} TA_TC_ADDR_MODES;
+typedef enum TA_PERFCOUNT_SEL {
+ TA_PERF_SEL_ta_busy = 0x0,
+ TA_PERF_SEL_sh_fifo_busy = 0x1,
+ TA_PERF_SEL_sh_fifo_cmd_busy = 0x2,
+ TA_PERF_SEL_sh_fifo_addr_busy = 0x3,
+ TA_PERF_SEL_sh_fifo_data_busy = 0x4,
+ TA_PERF_SEL_sh_fifo_data_sfifo_busy = 0x5,
+ TA_PERF_SEL_sh_fifo_data_tfifo_busy = 0x6,
+ TA_PERF_SEL_gradient_busy = 0x7,
+ TA_PERF_SEL_gradient_fifo_busy = 0x8,
+ TA_PERF_SEL_lod_busy = 0x9,
+ TA_PERF_SEL_lod_fifo_busy = 0xa,
+ TA_PERF_SEL_addresser_busy = 0xb,
+ TA_PERF_SEL_addresser_fifo_busy = 0xc,
+ TA_PERF_SEL_aligner_busy = 0xd,
+ TA_PERF_SEL_write_path_busy = 0xe,
+ TA_PERF_SEL_RESERVED_15 = 0xf,
+ TA_PERF_SEL_sq_ta_cmd_cycles = 0x10,
+ TA_PERF_SEL_sp_ta_addr_cycles = 0x11,
+ TA_PERF_SEL_sp_ta_data_cycles = 0x12,
+ TA_PERF_SEL_ta_fa_data_state_cycles = 0x13,
+ TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 0x14,
+ TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 0x15,
+ TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles= 0x16,
+ TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles= 0x17,
+ TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles= 0x18,
+ TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles= 0x19,
+ TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles= 0x1a,
+ TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles= 0x1b,
+ TA_PERF_SEL_RESERVED_28 = 0x1c,
+ TA_PERF_SEL_RESERVED_29 = 0x1d,
+ TA_PERF_SEL_sh_fifo_addr_cycles = 0x1e,
+ TA_PERF_SEL_sh_fifo_data_cycles = 0x1f,
+ TA_PERF_SEL_total_wavefronts = 0x20,
+ TA_PERF_SEL_gradient_cycles = 0x21,
+ TA_PERF_SEL_walker_cycles = 0x22,
+ TA_PERF_SEL_aligner_cycles = 0x23,
+ TA_PERF_SEL_image_wavefronts = 0x24,
+ TA_PERF_SEL_image_read_wavefronts = 0x25,
+ TA_PERF_SEL_image_write_wavefronts = 0x26,
+ TA_PERF_SEL_image_atomic_wavefronts = 0x27,
+ TA_PERF_SEL_image_total_cycles = 0x28,
+ TA_PERF_SEL_RESERVED_41 = 0x29,
+ TA_PERF_SEL_RESERVED_42 = 0x2a,
+ TA_PERF_SEL_RESERVED_43 = 0x2b,
+ TA_PERF_SEL_buffer_wavefronts = 0x2c,
+ TA_PERF_SEL_buffer_read_wavefronts = 0x2d,
+ TA_PERF_SEL_buffer_write_wavefronts = 0x2e,
+ TA_PERF_SEL_buffer_atomic_wavefronts = 0x2f,
+ TA_PERF_SEL_buffer_coalescable_wavefronts = 0x30,
+ TA_PERF_SEL_buffer_total_cycles = 0x31,
+ TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles= 0x32,
+ TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles= 0x33,
+ TA_PERF_SEL_buffer_coalesced_read_cycles = 0x34,
+ TA_PERF_SEL_buffer_coalesced_write_cycles = 0x35,
+ TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x36,
+ TA_PERF_SEL_addr_stalled_by_td_cycles = 0x37,
+ TA_PERF_SEL_data_stalled_by_tc_cycles = 0x38,
+ TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles= 0x39,
+ TA_PERF_SEL_addresser_stalled_cycles = 0x3a,
+ TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles= 0x3b,
+ TA_PERF_SEL_aniso_stalled_cycles = 0x3c,
+ TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x3d,
+ TA_PERF_SEL_deriv_stalled_cycles = 0x3e,
+ TA_PERF_SEL_aniso_gt1_cycle_quads = 0x3f,
+ TA_PERF_SEL_color_1_cycle_pixels = 0x40,
+ TA_PERF_SEL_color_2_cycle_pixels = 0x41,
+ TA_PERF_SEL_color_3_cycle_pixels = 0x42,
+ TA_PERF_SEL_color_4_cycle_pixels = 0x43,
+ TA_PERF_SEL_mip_1_cycle_pixels = 0x44,
+ TA_PERF_SEL_mip_2_cycle_pixels = 0x45,
+ TA_PERF_SEL_vol_1_cycle_pixels = 0x46,
+ TA_PERF_SEL_vol_2_cycle_pixels = 0x47,
+ TA_PERF_SEL_bilin_point_1_cycle_pixels = 0x48,
+ TA_PERF_SEL_mipmap_lod_0_samples = 0x49,
+ TA_PERF_SEL_mipmap_lod_1_samples = 0x4a,
+ TA_PERF_SEL_mipmap_lod_2_samples = 0x4b,
+ TA_PERF_SEL_mipmap_lod_3_samples = 0x4c,
+ TA_PERF_SEL_mipmap_lod_4_samples = 0x4d,
+ TA_PERF_SEL_mipmap_lod_5_samples = 0x4e,
+ TA_PERF_SEL_mipmap_lod_6_samples = 0x4f,
+ TA_PERF_SEL_mipmap_lod_7_samples = 0x50,
+ TA_PERF_SEL_mipmap_lod_8_samples = 0x51,
+ TA_PERF_SEL_mipmap_lod_9_samples = 0x52,
+ TA_PERF_SEL_mipmap_lod_10_samples = 0x53,
+ TA_PERF_SEL_mipmap_lod_11_samples = 0x54,
+ TA_PERF_SEL_mipmap_lod_12_samples = 0x55,
+ TA_PERF_SEL_mipmap_lod_13_samples = 0x56,
+ TA_PERF_SEL_mipmap_lod_14_samples = 0x57,
+ TA_PERF_SEL_mipmap_invalid_samples = 0x58,
+ TA_PERF_SEL_aniso_1_cycle_quads = 0x59,
+ TA_PERF_SEL_aniso_2_cycle_quads = 0x5a,
+ TA_PERF_SEL_aniso_4_cycle_quads = 0x5b,
+ TA_PERF_SEL_aniso_6_cycle_quads = 0x5c,
+ TA_PERF_SEL_aniso_8_cycle_quads = 0x5d,
+ TA_PERF_SEL_aniso_10_cycle_quads = 0x5e,
+ TA_PERF_SEL_aniso_12_cycle_quads = 0x5f,
+ TA_PERF_SEL_aniso_14_cycle_quads = 0x60,
+ TA_PERF_SEL_aniso_16_cycle_quads = 0x61,
+ TA_PERF_SEL_write_path_input_cycles = 0x62,
+ TA_PERF_SEL_write_path_output_cycles = 0x63,
+ TA_PERF_SEL_flat_wavefronts = 0x64,
+ TA_PERF_SEL_flat_read_wavefronts = 0x65,
+ TA_PERF_SEL_flat_write_wavefronts = 0x66,
+ TA_PERF_SEL_flat_atomic_wavefronts = 0x67,
+ TA_PERF_SEL_flat_coalesceable_wavefronts = 0x68,
+ TA_PERF_SEL_reg_sclk_vld = 0x69,
+ TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x6a,
+ TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x6b,
+ TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 0x6c,
+ TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x6d,
+ TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x6e,
+} TA_PERFCOUNT_SEL;
+typedef enum TD_PERFCOUNT_SEL {
+ TD_PERF_SEL_td_busy = 0x0,
+ TD_PERF_SEL_input_busy = 0x1,
+ TD_PERF_SEL_output_busy = 0x2,
+ TD_PERF_SEL_lerp_busy = 0x3,
+ TD_PERF_SEL_RESERVED_4 = 0x4,
+ TD_PERF_SEL_reg_sclk_vld = 0x5,
+ TD_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x6,
+ TD_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x7,
+ TD_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x8,
+ TD_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x9,
+ TD_PERF_SEL_tc_td_fifo_full = 0xa,
+ TD_PERF_SEL_constant_state_full = 0xb,
+ TD_PERF_SEL_sample_state_full = 0xc,
+ TD_PERF_SEL_output_fifo_full = 0xd,
+ TD_PERF_SEL_RESERVED_14 = 0xe,
+ TD_PERF_SEL_tc_stall = 0xf,
+ TD_PERF_SEL_pc_stall = 0x10,
+ TD_PERF_SEL_gds_stall = 0x11,
+ TD_PERF_SEL_RESERVED_18 = 0x12,
+ TD_PERF_SEL_RESERVED_19 = 0x13,
+ TD_PERF_SEL_gather4_wavefront = 0x14,
+ TD_PERF_SEL_sample_c_wavefront = 0x15,
+ TD_PERF_SEL_load_wavefront = 0x16,
+ TD_PERF_SEL_atomic_wavefront = 0x17,
+ TD_PERF_SEL_store_wavefront = 0x18,
+ TD_PERF_SEL_ldfptr_wavefront = 0x19,
+ TD_PERF_SEL_RESERVED_26 = 0x1a,
+ TD_PERF_SEL_RESERVED_27 = 0x1b,
+ TD_PERF_SEL_RESERVED_28 = 0x1c,
+ TD_PERF_SEL_RESERVED_29 = 0x1d,
+ TD_PERF_SEL_bypass_filter_wavefront = 0x1e,
+ TD_PERF_SEL_min_max_filter_wavefront = 0x1f,
+ TD_PERF_SEL_coalescable_wavefront = 0x20,
+ TD_PERF_SEL_coalesced_phase = 0x21,
+ TD_PERF_SEL_four_phase_wavefront = 0x22,
+ TD_PERF_SEL_eight_phase_wavefront = 0x23,
+ TD_PERF_SEL_sixteen_phase_wavefront = 0x24,
+ TD_PERF_SEL_four_phase_forward_wavefront = 0x25,
+ TD_PERF_SEL_write_ack_wavefront = 0x26,
+ TD_PERF_SEL_RESERVED_39 = 0x27,
+ TD_PERF_SEL_user_defined_border = 0x28,
+ TD_PERF_SEL_white_border = 0x29,
+ TD_PERF_SEL_opaque_black_border = 0x2a,
+ TD_PERF_SEL_RESERVED_43 = 0x2b,
+ TD_PERF_SEL_RESERVED_44 = 0x2c,
+ TD_PERF_SEL_nack = 0x2d,
+ TD_PERF_SEL_td_sp_traffic = 0x2e,
+ TD_PERF_SEL_consume_gds_traffic = 0x2f,
+ TD_PERF_SEL_addresscmd_poison = 0x30,
+ TD_PERF_SEL_data_poison = 0x31,
+ TD_PERF_SEL_start_cycle_0 = 0x32,
+ TD_PERF_SEL_start_cycle_1 = 0x33,
+ TD_PERF_SEL_start_cycle_2 = 0x34,
+ TD_PERF_SEL_start_cycle_3 = 0x35,
+ TD_PERF_SEL_null_cycle_output = 0x36,
+} TD_PERFCOUNT_SEL;
+typedef enum TCP_PERFCOUNT_SELECT {
+ TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 0x0,
+ TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 0x1,
+ TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 0x2,
+ TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 0x3,
+ TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 0x4,
+ TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 0x5,
+ TCP_PERF_SEL_LOD_STALL_CYCLES = 0x6,
+ TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 0x7,
+ TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 0x8,
+ TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 0x9,
+ TCP_PERF_SEL_ALLOC_STALL_CYCLES = 0xa,
+ TCP_PERF_SEL_LFIFO_STALL_CYCLES = 0xb,
+ TCP_PERF_SEL_RFIFO_STALL_CYCLES = 0xc,
+ TCP_PERF_SEL_TCR_RDRET_STALL = 0xd,
+ TCP_PERF_SEL_WRITE_CONFLICT_STALL = 0xe,
+ TCP_PERF_SEL_HOLE_READ_STALL = 0xf,
+ TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 0x10,
+ TCP_PERF_SEL_PENDING_STALL_CYCLES = 0x11,
+ TCP_PERF_SEL_READFIFO_STALL_CYCLES = 0x12,
+ TCP_PERF_SEL_TCP_LATENCY = 0x13,
+ TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 0x14,
+ TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 0x15,
+ TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 0x16,
+ TCP_PERF_SEL_TCC_READ_REQ = 0x17,
+ TCP_PERF_SEL_TCC_WRITE_REQ = 0x18,
+ TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 0x19,
+ TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 0x1a,
+ TCP_PERF_SEL_TOTAL_LOCAL_READ = 0x1b,
+ TCP_PERF_SEL_TOTAL_GLOBAL_READ = 0x1c,
+ TCP_PERF_SEL_TOTAL_LOCAL_WRITE = 0x1d,
+ TCP_PERF_SEL_TOTAL_GLOBAL_WRITE = 0x1e,
+ TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 0x1f,
+ TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 0x20,
+ TCP_PERF_SEL_TOTAL_WBINVL1 = 0x21,
+ TCP_PERF_SEL_IMG_READ_FMT_1 = 0x22,
+ TCP_PERF_SEL_IMG_READ_FMT_8 = 0x23,
+ TCP_PERF_SEL_IMG_READ_FMT_16 = 0x24,
+ TCP_PERF_SEL_IMG_READ_FMT_32 = 0x25,
+ TCP_PERF_SEL_IMG_READ_FMT_32_AS_8 = 0x26,
+ TCP_PERF_SEL_IMG_READ_FMT_32_AS_16 = 0x27,
+ TCP_PERF_SEL_IMG_READ_FMT_32_AS_128 = 0x28,
+ TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE = 0x29,
+ TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE = 0x2a,
+ TCP_PERF_SEL_IMG_READ_FMT_96 = 0x2b,
+ TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE = 0x2c,
+ TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE = 0x2d,
+ TCP_PERF_SEL_IMG_READ_FMT_BC1 = 0x2e,
+ TCP_PERF_SEL_IMG_READ_FMT_BC2 = 0x2f,
+ TCP_PERF_SEL_IMG_READ_FMT_BC3 = 0x30,
+ TCP_PERF_SEL_IMG_READ_FMT_BC4 = 0x31,
+ TCP_PERF_SEL_IMG_READ_FMT_BC5 = 0x32,
+ TCP_PERF_SEL_IMG_READ_FMT_BC6 = 0x33,
+ TCP_PERF_SEL_IMG_READ_FMT_BC7 = 0x34,
+ TCP_PERF_SEL_IMG_READ_FMT_I8 = 0x35,
+ TCP_PERF_SEL_IMG_READ_FMT_I16 = 0x36,
+ TCP_PERF_SEL_IMG_READ_FMT_I32 = 0x37,
+ TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8 = 0x38,
+ TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16 = 0x39,
+ TCP_PERF_SEL_IMG_READ_FMT_D8 = 0x3a,
+ TCP_PERF_SEL_IMG_READ_FMT_D16 = 0x3b,
+ TCP_PERF_SEL_IMG_READ_FMT_D32 = 0x3c,
+ TCP_PERF_SEL_IMG_WRITE_FMT_8 = 0x3d,
+ TCP_PERF_SEL_IMG_WRITE_FMT_16 = 0x3e,
+ TCP_PERF_SEL_IMG_WRITE_FMT_32 = 0x3f,
+ TCP_PERF_SEL_IMG_WRITE_FMT_64 = 0x40,
+ TCP_PERF_SEL_IMG_WRITE_FMT_128 = 0x41,
+ TCP_PERF_SEL_IMG_WRITE_FMT_D8 = 0x42,
+ TCP_PERF_SEL_IMG_WRITE_FMT_D16 = 0x43,
+ TCP_PERF_SEL_IMG_WRITE_FMT_D32 = 0x44,
+ TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32 = 0x45,
+ TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32 = 0x46,
+ TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64 = 0x47,
+ TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64 = 0x48,
+ TCP_PERF_SEL_BUF_READ_FMT_8 = 0x49,
+ TCP_PERF_SEL_BUF_READ_FMT_16 = 0x4a,
+ TCP_PERF_SEL_BUF_READ_FMT_32 = 0x4b,
+ TCP_PERF_SEL_BUF_WRITE_FMT_8 = 0x4c,
+ TCP_PERF_SEL_BUF_WRITE_FMT_16 = 0x4d,
+ TCP_PERF_SEL_BUF_WRITE_FMT_32 = 0x4e,
+ TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32 = 0x4f,
+ TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32 = 0x50,
+ TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64 = 0x51,
+ TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64 = 0x52,
+ TCP_PERF_SEL_ARR_LINEAR_GENERAL = 0x53,
+ TCP_PERF_SEL_ARR_LINEAR_ALIGNED = 0x54,
+ TCP_PERF_SEL_ARR_1D_THIN1 = 0x55,
+ TCP_PERF_SEL_ARR_1D_THICK = 0x56,
+ TCP_PERF_SEL_ARR_2D_THIN1 = 0x57,
+ TCP_PERF_SEL_ARR_2D_THICK = 0x58,
+ TCP_PERF_SEL_ARR_2D_XTHICK = 0x59,
+ TCP_PERF_SEL_ARR_3D_THIN1 = 0x5a,
+ TCP_PERF_SEL_ARR_3D_THICK = 0x5b,
+ TCP_PERF_SEL_ARR_3D_XTHICK = 0x5c,
+ TCP_PERF_SEL_DIM_1D = 0x5d,
+ TCP_PERF_SEL_DIM_2D = 0x5e,
+ TCP_PERF_SEL_DIM_3D = 0x5f,
+ TCP_PERF_SEL_DIM_1D_ARRAY = 0x60,
+ TCP_PERF_SEL_DIM_2D_ARRAY = 0x61,
+ TCP_PERF_SEL_DIM_2D_MSAA = 0x62,
+ TCP_PERF_SEL_DIM_2D_ARRAY_MSAA = 0x63,
+ TCP_PERF_SEL_DIM_CUBE_ARRAY = 0x64,
+ TCP_PERF_SEL_CP_TCP_INVALIDATE = 0x65,
+ TCP_PERF_SEL_TA_TCP_STATE_READ = 0x66,
+ TCP_PERF_SEL_TAGRAM0_REQ = 0x67,
+ TCP_PERF_SEL_TAGRAM1_REQ = 0x68,
+ TCP_PERF_SEL_TAGRAM2_REQ = 0x69,
+ TCP_PERF_SEL_TAGRAM3_REQ = 0x6a,
+ TCP_PERF_SEL_GATE_EN1 = 0x6b,
+ TCP_PERF_SEL_GATE_EN2 = 0x6c,
+ TCP_PERF_SEL_CORE_REG_SCLK_VLD = 0x6d,
+ TCP_PERF_SEL_TCC_REQ = 0x6e,
+ TCP_PERF_SEL_TCC_NON_READ_REQ = 0x6f,
+ TCP_PERF_SEL_TCC_BYPASS_READ_REQ = 0x70,
+ TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ = 0x71,
+ TCP_PERF_SEL_TCC_VOLATILE_READ_REQ = 0x72,
+ TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ = 0x73,
+ TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ = 0x74,
+ TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ = 0x75,
+ TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ = 0x76,
+ TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ = 0x77,
+ TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ = 0x78,
+ TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ = 0x79,
+ TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ = 0x7a,
+ TCP_PERF_SEL_TCC_ATOMIC_REQ = 0x7b,
+ TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ = 0x7c,
+ TCP_PERF_SEL_TCC_DATA_BUS_BUSY = 0x7d,
+ TCP_PERF_SEL_TOTAL_ACCESSES = 0x7e,
+ TCP_PERF_SEL_TOTAL_READ = 0x7f,
+ TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 0x80,
+ TCP_PERF_SEL_TOTAL_HIT_EVICT_READ = 0x81,
+ TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 0x82,
+ TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 0x83,
+ TCP_PERF_SEL_TOTAL_NON_READ = 0x84,
+ TCP_PERF_SEL_TOTAL_WRITE = 0x85,
+ TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 0x86,
+ TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 0x87,
+ TCP_PERF_SEL_TOTAL_WBINVL1_VOL = 0x88,
+ TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 0x89,
+ TCP_PERF_SEL_DISPLAY_MICROTILING = 0x8a,
+ TCP_PERF_SEL_THIN_MICROTILING = 0x8b,
+ TCP_PERF_SEL_DEPTH_MICROTILING = 0x8c,
+ TCP_PERF_SEL_ARR_PRT_THIN1 = 0x8d,
+ TCP_PERF_SEL_ARR_PRT_2D_THIN1 = 0x8e,
+ TCP_PERF_SEL_ARR_PRT_3D_THIN1 = 0x8f,
+ TCP_PERF_SEL_ARR_PRT_THICK = 0x90,
+ TCP_PERF_SEL_ARR_PRT_2D_THICK = 0x91,
+ TCP_PERF_SEL_ARR_PRT_3D_THICK = 0x92,
+ TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL = 0x93,
+ TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL = 0x94,
+ TCP_PERF_SEL_UNALIGNED = 0x95,
+ TCP_PERF_SEL_ROTATED_MICROTILING = 0x96,
+ TCP_PERF_SEL_THICK_MICROTILING = 0x97,
+ TCP_PERF_SEL_ATC = 0x98,
+ TCP_PERF_SEL_POWER_STALL = 0x99,
+} TCP_PERFCOUNT_SELECT;
+typedef enum TCP_CACHE_POLICIES {
+ TCP_CACHE_POLICY_MISS_LRU = 0x0,
+ TCP_CACHE_POLICY_MISS_EVICT = 0x1,
+ TCP_CACHE_POLICY_HIT_LRU = 0x2,
+ TCP_CACHE_POLICY_HIT_EVICT = 0x3,
+} TCP_CACHE_POLICIES;
+typedef enum TCP_CACHE_STORE_POLICIES {
+ TCP_CACHE_STORE_POLICY_MISS_LRU = 0x0,
+ TCP_CACHE_STORE_POLICY_MISS_EVICT = 0x1,
+} TCP_CACHE_STORE_POLICIES;
+typedef enum TCP_WATCH_MODES {
+ TCP_WATCH_MODE_READ = 0x0,
+ TCP_WATCH_MODE_NONREAD = 0x1,
+ TCP_WATCH_MODE_ATOMIC = 0x2,
+ TCP_WATCH_MODE_ALL = 0x3,
+} TCP_WATCH_MODES;
+typedef enum VGT_OUT_PRIM_TYPE {
+ VGT_OUT_POINT = 0x0,
+ VGT_OUT_LINE = 0x1,
+ VGT_OUT_TRI = 0x2,
+ VGT_OUT_RECT_V0 = 0x3,
+ VGT_OUT_RECT_V1 = 0x4,
+ VGT_OUT_RECT_V2 = 0x5,
+ VGT_OUT_RECT_V3 = 0x6,
+ VGT_OUT_RESERVED = 0x7,
+ VGT_TE_QUAD = 0x8,
+ VGT_TE_PRIM_INDEX_LINE = 0x9,
+ VGT_TE_PRIM_INDEX_TRI = 0xa,
+ VGT_TE_PRIM_INDEX_QUAD = 0xb,
+ VGT_OUT_LINE_ADJ = 0xc,
+ VGT_OUT_TRI_ADJ = 0xd,
+ VGT_OUT_PATCH = 0xe,
+} VGT_OUT_PRIM_TYPE;
+typedef enum VGT_DI_PRIM_TYPE {
+ DI_PT_NONE = 0x0,
+ DI_PT_POINTLIST = 0x1,
+ DI_PT_LINELIST = 0x2,
+ DI_PT_LINESTRIP = 0x3,
+ DI_PT_TRILIST = 0x4,
+ DI_PT_TRIFAN = 0x5,
+ DI_PT_TRISTRIP = 0x6,
+ DI_PT_UNUSED_0 = 0x7,
+ DI_PT_UNUSED_1 = 0x8,
+ DI_PT_PATCH = 0x9,
+ DI_PT_LINELIST_ADJ = 0xa,
+ DI_PT_LINESTRIP_ADJ = 0xb,
+ DI_PT_TRILIST_ADJ = 0xc,
+ DI_PT_TRISTRIP_ADJ = 0xd,
+ DI_PT_UNUSED_3 = 0xe,
+ DI_PT_UNUSED_4 = 0xf,
+ DI_PT_TRI_WITH_WFLAGS = 0x10,
+ DI_PT_RECTLIST = 0x11,
+ DI_PT_LINELOOP = 0x12,
+ DI_PT_QUADLIST = 0x13,
+ DI_PT_QUADSTRIP = 0x14,
+ DI_PT_POLYGON = 0x15,
+ DI_PT_2D_COPY_RECT_LIST_V0 = 0x16,
+ DI_PT_2D_COPY_RECT_LIST_V1 = 0x17,
+ DI_PT_2D_COPY_RECT_LIST_V2 = 0x18,
+ DI_PT_2D_COPY_RECT_LIST_V3 = 0x19,
+ DI_PT_2D_FILL_RECT_LIST = 0x1a,
+ DI_PT_2D_LINE_STRIP = 0x1b,
+ DI_PT_2D_TRI_STRIP = 0x1c,
+} VGT_DI_PRIM_TYPE;
+typedef enum VGT_DI_SOURCE_SELECT {
+ DI_SRC_SEL_DMA = 0x0,
+ DI_SRC_SEL_IMMEDIATE = 0x1,
+ DI_SRC_SEL_AUTO_INDEX = 0x2,
+ DI_SRC_SEL_RESERVED = 0x3,
+} VGT_DI_SOURCE_SELECT;
+typedef enum VGT_DI_MAJOR_MODE_SELECT {
+ DI_MAJOR_MODE_0 = 0x0,
+ DI_MAJOR_MODE_1 = 0x1,
+} VGT_DI_MAJOR_MODE_SELECT;
+typedef enum VGT_DI_INDEX_SIZE {
+ DI_INDEX_SIZE_16_BIT = 0x0,
+ DI_INDEX_SIZE_32_BIT = 0x1,
+} VGT_DI_INDEX_SIZE;
+typedef enum VGT_EVENT_TYPE {
+ Reserved_0x00 = 0x0,
+ SAMPLE_STREAMOUTSTATS1 = 0x1,
+ SAMPLE_STREAMOUTSTATS2 = 0x2,
+ SAMPLE_STREAMOUTSTATS3 = 0x3,
+ CACHE_FLUSH_TS = 0x4,
+ CONTEXT_DONE = 0x5,
+ CACHE_FLUSH = 0x6,
+ CS_PARTIAL_FLUSH = 0x7,
+ VGT_STREAMOUT_SYNC = 0x8,
+ Reserved_0x09 = 0x9,
+ VGT_STREAMOUT_RESET = 0xa,
+ END_OF_PIPE_INCR_DE = 0xb,
+ END_OF_PIPE_IB_END = 0xc,
+ RST_PIX_CNT = 0xd,
+ Reserved_0x0E = 0xe,
+ VS_PARTIAL_FLUSH = 0xf,
+ PS_PARTIAL_FLUSH = 0x10,
+ FLUSH_HS_OUTPUT = 0x11,
+ FLUSH_LS_OUTPUT = 0x12,
+ Reserved_0x13 = 0x13,
+ CACHE_FLUSH_AND_INV_TS_EVENT = 0x14,
+ ZPASS_DONE = 0x15,
+ CACHE_FLUSH_AND_INV_EVENT = 0x16,
+ PERFCOUNTER_START = 0x17,
+ PERFCOUNTER_STOP = 0x18,
+ PIPELINESTAT_START = 0x19,
+ PIPELINESTAT_STOP = 0x1a,
+ PERFCOUNTER_SAMPLE = 0x1b,
+ FLUSH_ES_OUTPUT = 0x1c,
+ FLUSH_GS_OUTPUT = 0x1d,
+ SAMPLE_PIPELINESTAT = 0x1e,
+ SO_VGTSTREAMOUT_FLUSH = 0x1f,
+ SAMPLE_STREAMOUTSTATS = 0x20,
+ RESET_VTX_CNT = 0x21,
+ BLOCK_CONTEXT_DONE = 0x22,
+ CS_CONTEXT_DONE = 0x23,
+ VGT_FLUSH = 0x24,
+ Reserved_0x25 = 0x25,
+ SQ_NON_EVENT = 0x26,
+ SC_SEND_DB_VPZ = 0x27,
+ BOTTOM_OF_PIPE_TS = 0x28,
+ FLUSH_SX_TS = 0x29,
+ DB_CACHE_FLUSH_AND_INV = 0x2a,
+ FLUSH_AND_INV_DB_DATA_TS = 0x2b,
+ FLUSH_AND_INV_DB_META = 0x2c,
+ FLUSH_AND_INV_CB_DATA_TS = 0x2d,
+ FLUSH_AND_INV_CB_META = 0x2e,
+ CS_DONE = 0x2f,
+ PS_DONE = 0x30,
+ FLUSH_AND_INV_CB_PIXEL_DATA = 0x31,
+ SX_CB_RAT_ACK_REQUEST = 0x32,
+ THREAD_TRACE_START = 0x33,
+ THREAD_TRACE_STOP = 0x34,
+ THREAD_TRACE_MARKER = 0x35,
+ THREAD_TRACE_FLUSH = 0x36,
+ THREAD_TRACE_FINISH = 0x37,
+ PIXEL_PIPE_STAT_CONTROL = 0x38,
+ PIXEL_PIPE_STAT_DUMP = 0x39,
+ PIXEL_PIPE_STAT_RESET = 0x3a,
+ CONTEXT_SUSPEND = 0x3b,
+} VGT_EVENT_TYPE;
+typedef enum VGT_DMA_SWAP_MODE {
+ VGT_DMA_SWAP_NONE = 0x0,
+ VGT_DMA_SWAP_16_BIT = 0x1,
+ VGT_DMA_SWAP_32_BIT = 0x2,
+ VGT_DMA_SWAP_WORD = 0x3,
+} VGT_DMA_SWAP_MODE;
+typedef enum VGT_INDEX_TYPE_MODE {
+ VGT_INDEX_16 = 0x0,
+ VGT_INDEX_32 = 0x1,
+} VGT_INDEX_TYPE_MODE;
+typedef enum VGT_DMA_BUF_TYPE {
+ VGT_DMA_BUF_MEM = 0x0,
+ VGT_DMA_BUF_RING = 0x1,
+ VGT_DMA_BUF_SETUP = 0x2,
+} VGT_DMA_BUF_TYPE;
+typedef enum VGT_OUTPATH_SELECT {
+ VGT_OUTPATH_VTX_REUSE = 0x0,
+ VGT_OUTPATH_TESS_EN = 0x1,
+ VGT_OUTPATH_PASSTHRU = 0x2,
+ VGT_OUTPATH_GS_BLOCK = 0x3,
+ VGT_OUTPATH_HS_BLOCK = 0x4,
+} VGT_OUTPATH_SELECT;
+typedef enum VGT_GRP_PRIM_TYPE {
+ VGT_GRP_3D_POINT = 0x0,
+ VGT_GRP_3D_LINE = 0x1,
+ VGT_GRP_3D_TRI = 0x2,
+ VGT_GRP_3D_RECT = 0x3,
+ VGT_GRP_3D_QUAD = 0x4,
+ VGT_GRP_2D_COPY_RECT_V0 = 0x5,
+ VGT_GRP_2D_COPY_RECT_V1 = 0x6,
+ VGT_GRP_2D_COPY_RECT_V2 = 0x7,
+ VGT_GRP_2D_COPY_RECT_V3 = 0x8,
+ VGT_GRP_2D_FILL_RECT = 0x9,
+ VGT_GRP_2D_LINE = 0xa,
+ VGT_GRP_2D_TRI = 0xb,
+ VGT_GRP_PRIM_INDEX_LINE = 0xc,
+ VGT_GRP_PRIM_INDEX_TRI = 0xd,
+ VGT_GRP_PRIM_INDEX_QUAD = 0xe,
+ VGT_GRP_3D_LINE_ADJ = 0xf,
+ VGT_GRP_3D_TRI_ADJ = 0x10,
+ VGT_GRP_3D_PATCH = 0x11,
+} VGT_GRP_PRIM_TYPE;
+typedef enum VGT_GRP_PRIM_ORDER {
+ VGT_GRP_LIST = 0x0,
+ VGT_GRP_STRIP = 0x1,
+ VGT_GRP_FAN = 0x2,
+ VGT_GRP_LOOP = 0x3,
+ VGT_GRP_POLYGON = 0x4,
+} VGT_GRP_PRIM_ORDER;
+typedef enum VGT_GROUP_CONV_SEL {
+ VGT_GRP_INDEX_16 = 0x0,
+ VGT_GRP_INDEX_32 = 0x1,
+ VGT_GRP_UINT_16 = 0x2,
+ VGT_GRP_UINT_32 = 0x3,
+ VGT_GRP_SINT_16 = 0x4,
+ VGT_GRP_SINT_32 = 0x5,
+ VGT_GRP_FLOAT_32 = 0x6,
+ VGT_GRP_AUTO_PRIM = 0x7,
+ VGT_GRP_FIX_1_23_TO_FLOAT = 0x8,
+} VGT_GROUP_CONV_SEL;
+typedef enum VGT_GS_MODE_TYPE {
+ GS_OFF = 0x0,
+ GS_SCENARIO_A = 0x1,
+ GS_SCENARIO_B = 0x2,
+ GS_SCENARIO_G = 0x3,
+ GS_SCENARIO_C = 0x4,
+ SPRITE_EN = 0x5,
+} VGT_GS_MODE_TYPE;
+typedef enum VGT_GS_CUT_MODE {
+ GS_CUT_1024 = 0x0,
+ GS_CUT_512 = 0x1,
+ GS_CUT_256 = 0x2,
+ GS_CUT_128 = 0x3,
+} VGT_GS_CUT_MODE;
+typedef enum VGT_GS_OUTPRIM_TYPE {
+ POINTLIST = 0x0,
+ LINESTRIP = 0x1,
+ TRISTRIP = 0x2,
+} VGT_GS_OUTPRIM_TYPE;
+typedef enum VGT_CACHE_INVALID_MODE {
+ VC_ONLY = 0x0,
+ TC_ONLY = 0x1,
+ VC_AND_TC = 0x2,
+} VGT_CACHE_INVALID_MODE;
+typedef enum VGT_TESS_TYPE {
+ TESS_ISOLINE = 0x0,
+ TESS_TRIANGLE = 0x1,
+ TESS_QUAD = 0x2,
+} VGT_TESS_TYPE;
+typedef enum VGT_TESS_PARTITION {
+ PART_INTEGER = 0x0,
+ PART_POW2 = 0x1,
+ PART_FRAC_ODD = 0x2,
+ PART_FRAC_EVEN = 0x3,
+} VGT_TESS_PARTITION;
+typedef enum VGT_TESS_TOPOLOGY {
+ OUTPUT_POINT = 0x0,
+ OUTPUT_LINE = 0x1,
+ OUTPUT_TRIANGLE_CW = 0x2,
+ OUTPUT_TRIANGLE_CCW = 0x3,
+} VGT_TESS_TOPOLOGY;
+typedef enum VGT_RDREQ_POLICY {
+ VGT_POLICY_LRU = 0x0,
+ VGT_POLICY_STREAM = 0x1,
+ VGT_POLICY_BYPASS = 0x2,
+ VGT_POLICY_RESERVED = 0x3,
+} VGT_RDREQ_POLICY;
+typedef enum VGT_STAGES_LS_EN {
+ LS_STAGE_OFF = 0x0,
+ LS_STAGE_ON = 0x1,
+ CS_STAGE_ON = 0x2,
+ RESERVED_LS = 0x3,
+} VGT_STAGES_LS_EN;
+typedef enum VGT_STAGES_HS_EN {
+ HS_STAGE_OFF = 0x0,
+ HS_STAGE_ON = 0x1,
+} VGT_STAGES_HS_EN;
+typedef enum VGT_STAGES_ES_EN {
+ ES_STAGE_OFF = 0x0,
+ ES_STAGE_DS = 0x1,
+ ES_STAGE_REAL = 0x2,
+ RESERVED_ES = 0x3,
+} VGT_STAGES_ES_EN;
+typedef enum VGT_STAGES_GS_EN {
+ GS_STAGE_OFF = 0x0,
+ GS_STAGE_ON = 0x1,
+} VGT_STAGES_GS_EN;
+typedef enum VGT_STAGES_VS_EN {
+ VS_STAGE_REAL = 0x0,
+ VS_STAGE_DS = 0x1,
+ VS_STAGE_COPY_SHADER = 0x2,
+ RESERVED_VS = 0x3,
+} VGT_STAGES_VS_EN;
+typedef enum VGT_PERFCOUNT_SELECT {
+ vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0x0,
+ vgt_perf_VGT_SPI_ESVERT_VALID = 0x1,
+ vgt_perf_VGT_SPI_ESVERT_EOV = 0x2,
+ vgt_perf_VGT_SPI_ESVERT_STALLED = 0x3,
+ vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY = 0x4,
+ vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE = 0x5,
+ vgt_perf_VGT_SPI_ESVERT_STATIC = 0x6,
+ vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT = 0x7,
+ vgt_perf_VGT_SPI_ESTHREAD_SEND = 0x8,
+ vgt_perf_VGT_SPI_GSPRIM_VALID = 0x9,
+ vgt_perf_VGT_SPI_GSPRIM_EOV = 0xa,
+ vgt_perf_VGT_SPI_GSPRIM_CONT = 0xb,
+ vgt_perf_VGT_SPI_GSPRIM_STALLED = 0xc,
+ vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY = 0xd,
+ vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE = 0xe,
+ vgt_perf_VGT_SPI_GSPRIM_STATIC = 0xf,
+ vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 0x10,
+ vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT = 0x11,
+ vgt_perf_VGT_SPI_GSTHREAD_SEND = 0x12,
+ vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 0x13,
+ vgt_perf_VGT_SPI_VSVERT_SEND = 0x14,
+ vgt_perf_VGT_SPI_VSVERT_EOV = 0x15,
+ vgt_perf_VGT_SPI_VSVERT_STALLED = 0x16,
+ vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY = 0x17,
+ vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE = 0x18,
+ vgt_perf_VGT_SPI_VSVERT_STATIC = 0x19,
+ vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT = 0x1a,
+ vgt_perf_VGT_SPI_VSTHREAD_SEND = 0x1b,
+ vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE = 0x1c,
+ vgt_perf_VGT_PA_CLIPV_SEND = 0x1d,
+ vgt_perf_VGT_PA_CLIPV_FIRSTVERT = 0x1e,
+ vgt_perf_VGT_PA_CLIPV_STALLED = 0x1f,
+ vgt_perf_VGT_PA_CLIPV_STARVED_BUSY = 0x20,
+ vgt_perf_VGT_PA_CLIPV_STARVED_IDLE = 0x21,
+ vgt_perf_VGT_PA_CLIPV_STATIC = 0x22,
+ vgt_perf_VGT_PA_CLIPP_SEND = 0x23,
+ vgt_perf_VGT_PA_CLIPP_EOP = 0x24,
+ vgt_perf_VGT_PA_CLIPP_IS_EVENT = 0x25,
+ vgt_perf_VGT_PA_CLIPP_NULL_PRIM = 0x26,
+ vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT = 0x27,
+ vgt_perf_VGT_PA_CLIPP_STALLED = 0x28,
+ vgt_perf_VGT_PA_CLIPP_STARVED_BUSY = 0x29,
+ vgt_perf_VGT_PA_CLIPP_STARVED_IDLE = 0x2a,
+ vgt_perf_VGT_PA_CLIPP_STATIC = 0x2b,
+ vgt_perf_VGT_PA_CLIPS_SEND = 0x2c,
+ vgt_perf_VGT_PA_CLIPS_STALLED = 0x2d,
+ vgt_perf_VGT_PA_CLIPS_STARVED_BUSY = 0x2e,
+ vgt_perf_VGT_PA_CLIPS_STARVED_IDLE = 0x2f,
+ vgt_perf_VGT_PA_CLIPS_STATIC = 0x30,
+ vgt_perf_vsvert_ds_send = 0x31,
+ vgt_perf_vsvert_api_send = 0x32,
+ vgt_perf_hs_tif_stall = 0x33,
+ vgt_perf_hs_input_stall = 0x34,
+ vgt_perf_hs_interface_stall = 0x35,
+ vgt_perf_hs_tfm_stall = 0x36,
+ vgt_perf_te11_starved = 0x37,
+ vgt_perf_gs_event_stall = 0x38,
+ vgt_perf_vgt_pa_clipp_send_not_event = 0x39,
+ vgt_perf_vgt_pa_clipp_valid_prim = 0x3a,
+ vgt_perf_reused_es_indices = 0x3b,
+ vgt_perf_vs_cache_hits = 0x3c,
+ vgt_perf_gs_cache_hits = 0x3d,
+ vgt_perf_ds_cache_hits = 0x3e,
+ vgt_perf_total_cache_hits = 0x3f,
+ vgt_perf_vgt_busy = 0x40,
+ vgt_perf_vgt_gs_busy = 0x41,
+ vgt_perf_esvert_stalled_es_tbl = 0x42,
+ vgt_perf_esvert_stalled_gs_tbl = 0x43,
+ vgt_perf_esvert_stalled_gs_event = 0x44,
+ vgt_perf_esvert_stalled_gsprim = 0x45,
+ vgt_perf_gsprim_stalled_es_tbl = 0x46,
+ vgt_perf_gsprim_stalled_gs_tbl = 0x47,
+ vgt_perf_gsprim_stalled_gs_event = 0x48,
+ vgt_perf_gsprim_stalled_esvert = 0x49,
+ vgt_perf_esthread_stalled_es_rb_full = 0x4a,
+ vgt_perf_esthread_stalled_spi_bp = 0x4b,
+ vgt_perf_counters_avail_stalled = 0x4c,
+ vgt_perf_gs_rb_space_avail_stalled = 0x4d,
+ vgt_perf_gs_issue_rtr_stalled = 0x4e,
+ vgt_perf_gsthread_stalled = 0x4f,
+ vgt_perf_strmout_stalled = 0x50,
+ vgt_perf_wait_for_es_done_stalled = 0x51,
+ vgt_perf_cm_stalled_by_gog = 0x52,
+ vgt_perf_cm_reading_stalled = 0x53,
+ vgt_perf_cm_stalled_by_gsfetch_done = 0x54,
+ vgt_perf_gog_vs_tbl_stalled = 0x55,
+ vgt_perf_gog_out_indx_stalled = 0x56,
+ vgt_perf_gog_out_prim_stalled = 0x57,
+ vgt_perf_waveid_stalled = 0x58,
+ vgt_perf_gog_busy = 0x59,
+ vgt_perf_reused_vs_indices = 0x5a,
+ vgt_perf_sclk_reg_vld_event = 0x5b,
+ vgt_perf_RESERVED0 = 0x5c,
+ vgt_perf_sclk_core_vld_event = 0x5d,
+ vgt_perf_RESERVED1 = 0x5e,
+ vgt_perf_sclk_gs_vld_event = 0x5f,
+ vgt_perf_VGT_SPI_LSVERT_VALID = 0x60,
+ vgt_perf_VGT_SPI_LSVERT_EOV = 0x61,
+ vgt_perf_VGT_SPI_LSVERT_STALLED = 0x62,
+ vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY = 0x63,
+ vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE = 0x64,
+ vgt_perf_VGT_SPI_LSVERT_STATIC = 0x65,
+ vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE = 0x66,
+ vgt_perf_VGT_SPI_LSWAVE_IS_EVENT = 0x67,
+ vgt_perf_VGT_SPI_LSWAVE_SEND = 0x68,
+ vgt_perf_VGT_SPI_HSVERT_VALID = 0x69,
+ vgt_perf_VGT_SPI_HSVERT_EOV = 0x6a,
+ vgt_perf_VGT_SPI_HSVERT_STALLED = 0x6b,
+ vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY = 0x6c,
+ vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE = 0x6d,
+ vgt_perf_VGT_SPI_HSVERT_STATIC = 0x6e,
+ vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE = 0x6f,
+ vgt_perf_VGT_SPI_HSWAVE_IS_EVENT = 0x70,
+ vgt_perf_VGT_SPI_HSWAVE_SEND = 0x71,
+ vgt_perf_ds_prims = 0x72,
+ vgt_perf_null_tess_patches = 0x73,
+ vgt_perf_ls_thread_groups = 0x74,
+ vgt_perf_hs_thread_groups = 0x75,
+ vgt_perf_es_thread_groups = 0x76,
+ vgt_perf_vs_thread_groups = 0x77,
+ vgt_perf_ls_done_latency = 0x78,
+ vgt_perf_hs_done_latency = 0x79,
+ vgt_perf_es_done_latency = 0x7a,
+ vgt_perf_gs_done_latency = 0x7b,
+ vgt_perf_vgt_hs_busy = 0x7c,
+ vgt_perf_vgt_te11_busy = 0x7d,
+ vgt_perf_ls_flush = 0x7e,
+ vgt_perf_hs_flush = 0x7f,
+ vgt_perf_es_flush = 0x80,
+ vgt_perf_gs_flush = 0x81,
+ vgt_perf_ls_done = 0x82,
+ vgt_perf_hs_done = 0x83,
+ vgt_perf_es_done = 0x84,
+ vgt_perf_gs_done = 0x85,
+ vgt_perf_vsfetch_done = 0x86,
+ vgt_perf_RESERVED2 = 0x87,
+ vgt_perf_es_ring_high_water_mark = 0x88,
+ vgt_perf_gs_ring_high_water_mark = 0x89,
+ vgt_perf_vs_table_high_water_mark = 0x8a,
+ vgt_perf_hs_tgs_active_high_water_mark = 0x8b,
+} VGT_PERFCOUNT_SELECT;
+typedef enum IA_PERFCOUNT_SELECT {
+ ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE = 0x0,
+ ia_perf_MC_LAT_BIN_0 = 0x1,
+ ia_perf_MC_LAT_BIN_1 = 0x2,
+ ia_perf_MC_LAT_BIN_2 = 0x3,
+ ia_perf_MC_LAT_BIN_3 = 0x4,
+ ia_perf_MC_LAT_BIN_4 = 0x5,
+ ia_perf_MC_LAT_BIN_5 = 0x6,
+ ia_perf_MC_LAT_BIN_6 = 0x7,
+ ia_perf_MC_LAT_BIN_7 = 0x8,
+ ia_perf_ia_busy = 0x9,
+ ia_perf_ia_sclk_reg_vld_event = 0xa,
+ ia_perf_RESERVED0 = 0xb,
+ ia_perf_ia_sclk_core_vld_event = 0xc,
+ ia_perf_RESERVED1 = 0xd,
+ ia_perf_ia_dma_return = 0xe,
+ ia_perf_shift_starved_pipe1_event = 0xf,
+ ia_perf_shift_starved_pipe0_event = 0x10,
+ ia_perf_ia_stalled = 0x11,
+} IA_PERFCOUNT_SELECT;
+typedef enum WD_PERFCOUNT_SELECT {
+ wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 0x0,
+ wd_perf_RBIU_DR_FIFO_STARVED = 0x1,
+ wd_perf_RBIU_DR_FIFO_STALLED = 0x2,
+ wd_perf_RBIU_DI_FIFO_STARVED = 0x3,
+ wd_perf_RBIU_DI_FIFO_STALLED = 0x4,
+ wd_perf_wd_busy = 0x5,
+ wd_perf_wd_sclk_reg_vld_event = 0x6,
+ wd_perf_wd_sclk_input_vld_event = 0x7,
+ wd_perf_wd_sclk_core_vld_event = 0x8,
+ wd_perf_wd_stalled = 0x9,
+} WD_PERFCOUNT_SELECT;
+typedef enum WD_IA_DRAW_TYPE {
+ WD_IA_DRAW_TYPE_DI_MM0 = 0x0,
+ WD_IA_DRAW_TYPE_DI_MM1 = 0x1,
+ WD_IA_DRAW_TYPE_EVENT_INIT = 0x2,
+ WD_IA_DRAW_TYPE_EVENT_ADDR = 0x3,
+ WD_IA_DRAW_TYPE_MIN_INDX = 0x4,
+ WD_IA_DRAW_TYPE_MAX_INDX = 0x5,
+ WD_IA_DRAW_TYPE_INDX_OFF = 0x6,
+ WD_IA_DRAW_TYPE_IMM_DATA = 0x7,
+} WD_IA_DRAW_TYPE;
+#define GSTHREADID_SIZE 0x2
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0x0,
+ ENDIAN_8IN16 = 0x1,
+ ENDIAN_8IN32 = 0x2,
+ ENDIAN_8IN64 = 0x3,
+} SurfaceEndian;
+typedef enum ArrayMode {
+ ARRAY_LINEAR_GENERAL = 0x0,
+ ARRAY_LINEAR_ALIGNED = 0x1,
+ ARRAY_1D_TILED_THIN1 = 0x2,
+ ARRAY_1D_TILED_THICK = 0x3,
+ ARRAY_2D_TILED_THIN1 = 0x4,
+ ARRAY_PRT_TILED_THIN1 = 0x5,
+ ARRAY_PRT_2D_TILED_THIN1 = 0x6,
+ ARRAY_2D_TILED_THICK = 0x7,
+ ARRAY_2D_TILED_XTHICK = 0x8,
+ ARRAY_PRT_TILED_THICK = 0x9,
+ ARRAY_PRT_2D_TILED_THICK = 0xa,
+ ARRAY_PRT_3D_TILED_THIN1 = 0xb,
+ ARRAY_3D_TILED_THIN1 = 0xc,
+ ARRAY_3D_TILED_THICK = 0xd,
+ ARRAY_3D_TILED_XTHICK = 0xe,
+ ARRAY_PRT_3D_TILED_THICK = 0xf,
+} ArrayMode;
+typedef enum PipeTiling {
+ CONFIG_1_PIPE = 0x0,
+ CONFIG_2_PIPE = 0x1,
+ CONFIG_4_PIPE = 0x2,
+ CONFIG_8_PIPE = 0x3,
+} PipeTiling;
+typedef enum BankTiling {
+ CONFIG_4_BANK = 0x0,
+ CONFIG_8_BANK = 0x1,
+} BankTiling;
+typedef enum GroupInterleave {
+ CONFIG_256B_GROUP = 0x0,
+ CONFIG_512B_GROUP = 0x1,
+} GroupInterleave;
+typedef enum RowTiling {
+ CONFIG_1KB_ROW = 0x0,
+ CONFIG_2KB_ROW = 0x1,
+ CONFIG_4KB_ROW = 0x2,
+ CONFIG_8KB_ROW = 0x3,
+ CONFIG_1KB_ROW_OPT = 0x4,
+ CONFIG_2KB_ROW_OPT = 0x5,
+ CONFIG_4KB_ROW_OPT = 0x6,
+ CONFIG_8KB_ROW_OPT = 0x7,
+} RowTiling;
+typedef enum BankSwapBytes {
+ CONFIG_128B_SWAPS = 0x0,
+ CONFIG_256B_SWAPS = 0x1,
+ CONFIG_512B_SWAPS = 0x2,
+ CONFIG_1KB_SWAPS = 0x3,
+} BankSwapBytes;
+typedef enum SampleSplitBytes {
+ CONFIG_1KB_SPLIT = 0x0,
+ CONFIG_2KB_SPLIT = 0x1,
+ CONFIG_4KB_SPLIT = 0x2,
+ CONFIG_8KB_SPLIT = 0x3,
+} SampleSplitBytes;
+typedef enum NumPipes {
+ ADDR_CONFIG_1_PIPE = 0x0,
+ ADDR_CONFIG_2_PIPE = 0x1,
+ ADDR_CONFIG_4_PIPE = 0x2,
+ ADDR_CONFIG_8_PIPE = 0x3,
+ ADDR_CONFIG_16_PIPE = 0x4,
+} NumPipes;
+typedef enum PipeInterleaveSize {
+ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
+ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
+} PipeInterleaveSize;
+typedef enum BankInterleaveSize {
+ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
+ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
+ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
+ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
+} BankInterleaveSize;
+typedef enum NumShaderEngines {
+ ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
+ ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
+} NumShaderEngines;
+typedef enum ShaderEngineTileSize {
+ ADDR_CONFIG_SE_TILE_16 = 0x0,
+ ADDR_CONFIG_SE_TILE_32 = 0x1,
+} ShaderEngineTileSize;
+typedef enum NumGPUs {
+ ADDR_CONFIG_1_GPU = 0x0,
+ ADDR_CONFIG_2_GPU = 0x1,
+ ADDR_CONFIG_4_GPU = 0x2,
+} NumGPUs;
+typedef enum MultiGPUTileSize {
+ ADDR_CONFIG_GPU_TILE_16 = 0x0,
+ ADDR_CONFIG_GPU_TILE_32 = 0x1,
+ ADDR_CONFIG_GPU_TILE_64 = 0x2,
+ ADDR_CONFIG_GPU_TILE_128 = 0x3,
+} MultiGPUTileSize;
+typedef enum RowSize {
+ ADDR_CONFIG_1KB_ROW = 0x0,
+ ADDR_CONFIG_2KB_ROW = 0x1,
+ ADDR_CONFIG_4KB_ROW = 0x2,
+} RowSize;
+typedef enum NumLowerPipes {
+ ADDR_CONFIG_1_LOWER_PIPES = 0x0,
+ ADDR_CONFIG_2_LOWER_PIPES = 0x1,
+} NumLowerPipes;
+typedef enum DebugBlockId {
+ DBG_CLIENT_BLKID_RESERVED = 0x0,
+ DBG_CLIENT_BLKID_dbg = 0x1,
+ DBG_CLIENT_BLKID_dco0 = 0x2,
+ DBG_CLIENT_BLKID_wd = 0x3,
+ DBG_CLIENT_BLKID_vmc = 0x4,
+ DBG_CLIENT_BLKID_scf2 = 0x5,
+ DBG_CLIENT_BLKID_spim3 = 0x6,
+ DBG_CLIENT_BLKID_cb3 = 0x7,
+ DBG_CLIENT_BLKID_sx0 = 0x8,
+ DBG_CLIENT_BLKID_cb2 = 0x9,
+ DBG_CLIENT_BLKID_bci1 = 0xa,
+ DBG_CLIENT_BLKID_xdma = 0xb,
+ DBG_CLIENT_BLKID_bci0 = 0xc,
+ DBG_CLIENT_BLKID_spim0 = 0xd,
+ DBG_CLIENT_BLKID_mcd0 = 0xe,
+ DBG_CLIENT_BLKID_mcc0 = 0xf,
+ DBG_CLIENT_BLKID_cb0 = 0x10,
+ DBG_CLIENT_BLKID_cb1 = 0x11,
+ DBG_CLIENT_BLKID_cpc_0 = 0x12,
+ DBG_CLIENT_BLKID_cpc_1 = 0x13,
+ DBG_CLIENT_BLKID_cpf = 0x14,
+ DBG_CLIENT_BLKID_rlc = 0x15,
+ DBG_CLIENT_BLKID_grbm = 0x16,
+ DBG_CLIENT_BLKID_bif = 0x17,
+ DBG_CLIENT_BLKID_scf1 = 0x18,
+ DBG_CLIENT_BLKID_sam = 0x19,
+ DBG_CLIENT_BLKID_mcd4 = 0x1a,
+ DBG_CLIENT_BLKID_mcc4 = 0x1b,
+ DBG_CLIENT_BLKID_gmcon = 0x1c,
+ DBG_CLIENT_BLKID_mcb = 0x1d,
+ DBG_CLIENT_BLKID_vgt0 = 0x1e,
+ DBG_CLIENT_BLKID_pc0 = 0x1f,
+ DBG_CLIENT_BLKID_spim1 = 0x20,
+ DBG_CLIENT_BLKID_bci2 = 0x21,
+ DBG_CLIENT_BLKID_mcd6 = 0x22,
+ DBG_CLIENT_BLKID_mcc6 = 0x23,
+ DBG_CLIENT_BLKID_mcd3 = 0x24,
+ DBG_CLIENT_BLKID_mcc3 = 0x25,
+ DBG_CLIENT_BLKID_uvdm_0 = 0x26,
+ DBG_CLIENT_BLKID_uvdm_1 = 0x27,
+ DBG_CLIENT_BLKID_uvdm_2 = 0x28,
+ DBG_CLIENT_BLKID_uvdm_3 = 0x29,
+ DBG_CLIENT_BLKID_spim2 = 0x2a,
+ DBG_CLIENT_BLKID_ds = 0x2b,
+ DBG_CLIENT_BLKID_srbm = 0x2c,
+ DBG_CLIENT_BLKID_ih = 0x2d,
+ DBG_CLIENT_BLKID_sem = 0x2e,
+ DBG_CLIENT_BLKID_sdma_0 = 0x2f,
+ DBG_CLIENT_BLKID_sdma_1 = 0x30,
+ DBG_CLIENT_BLKID_hdp = 0x31,
+ DBG_CLIENT_BLKID_acp_0 = 0x32,
+ DBG_CLIENT_BLKID_acp_1 = 0x33,
+ DBG_CLIENT_BLKID_vceb_0 = 0x34,
+ DBG_CLIENT_BLKID_vceb_1 = 0x35,
+ DBG_CLIENT_BLKID_vceb_2 = 0x36,
+ DBG_CLIENT_BLKID_mcd2 = 0x37,
+ DBG_CLIENT_BLKID_mcc2 = 0x38,
+ DBG_CLIENT_BLKID_scf3 = 0x39,
+ DBG_CLIENT_BLKID_bci3 = 0x3a,
+ DBG_CLIENT_BLKID_mcd5 = 0x3b,
+ DBG_CLIENT_BLKID_mcc5 = 0x3c,
+ DBG_CLIENT_BLKID_vgt2 = 0x3d,
+ DBG_CLIENT_BLKID_pc2 = 0x3e,
+ DBG_CLIENT_BLKID_smu_0 = 0x3f,
+ DBG_CLIENT_BLKID_smu_1 = 0x40,
+ DBG_CLIENT_BLKID_smu_2 = 0x41,
+ DBG_CLIENT_BLKID_vcea_0 = 0x42,
+ DBG_CLIENT_BLKID_vcea_1 = 0x43,
+ DBG_CLIENT_BLKID_vcea_2 = 0x44,
+ DBG_CLIENT_BLKID_vcea_3 = 0x45,
+ DBG_CLIENT_BLKID_vcea_4 = 0x46,
+ DBG_CLIENT_BLKID_vcea_5 = 0x47,
+ DBG_CLIENT_BLKID_vcea_6 = 0x48,
+ DBG_CLIENT_BLKID_scf0 = 0x49,
+ DBG_CLIENT_BLKID_vgt1 = 0x4a,
+ DBG_CLIENT_BLKID_pc1 = 0x4b,
+ DBG_CLIENT_BLKID_gdc_0 = 0x4c,
+ DBG_CLIENT_BLKID_gdc_1 = 0x4d,
+ DBG_CLIENT_BLKID_gdc_2 = 0x4e,
+ DBG_CLIENT_BLKID_gdc_3 = 0x4f,
+ DBG_CLIENT_BLKID_gdc_4 = 0x50,
+ DBG_CLIENT_BLKID_gdc_5 = 0x51,
+ DBG_CLIENT_BLKID_gdc_6 = 0x52,
+ DBG_CLIENT_BLKID_gdc_7 = 0x53,
+ DBG_CLIENT_BLKID_gdc_8 = 0x54,
+ DBG_CLIENT_BLKID_gdc_9 = 0x55,
+ DBG_CLIENT_BLKID_gdc_10 = 0x56,
+ DBG_CLIENT_BLKID_gdc_11 = 0x57,
+ DBG_CLIENT_BLKID_gdc_12 = 0x58,
+ DBG_CLIENT_BLKID_gdc_13 = 0x59,
+ DBG_CLIENT_BLKID_gdc_14 = 0x5a,
+ DBG_CLIENT_BLKID_gdc_15 = 0x5b,
+ DBG_CLIENT_BLKID_gdc_16 = 0x5c,
+ DBG_CLIENT_BLKID_gdc_17 = 0x5d,
+ DBG_CLIENT_BLKID_gdc_18 = 0x5e,
+ DBG_CLIENT_BLKID_gdc_19 = 0x5f,
+ DBG_CLIENT_BLKID_gdc_20 = 0x60,
+ DBG_CLIENT_BLKID_gdc_21 = 0x61,
+ DBG_CLIENT_BLKID_gdc_22 = 0x62,
+ DBG_CLIENT_BLKID_vgt3 = 0x63,
+ DBG_CLIENT_BLKID_pc3 = 0x64,
+ DBG_CLIENT_BLKID_uvdu_0 = 0x65,
+ DBG_CLIENT_BLKID_uvdu_1 = 0x66,
+ DBG_CLIENT_BLKID_uvdu_2 = 0x67,
+ DBG_CLIENT_BLKID_uvdu_3 = 0x68,
+ DBG_CLIENT_BLKID_uvdu_4 = 0x69,
+ DBG_CLIENT_BLKID_uvdu_5 = 0x6a,
+ DBG_CLIENT_BLKID_uvdu_6 = 0x6b,
+ DBG_CLIENT_BLKID_mcd7 = 0x6c,
+ DBG_CLIENT_BLKID_mcc7 = 0x6d,
+ DBG_CLIENT_BLKID_cpg_0 = 0x6e,
+ DBG_CLIENT_BLKID_cpg_1 = 0x6f,
+ DBG_CLIENT_BLKID_gck = 0x70,
+ DBG_CLIENT_BLKID_mcd1 = 0x71,
+ DBG_CLIENT_BLKID_mcc1 = 0x72,
+ DBG_CLIENT_BLKID_cb101 = 0x73,
+ DBG_CLIENT_BLKID_cb103 = 0x74,
+ DBG_CLIENT_BLKID_sx10 = 0x75,
+ DBG_CLIENT_BLKID_cb102 = 0x76,
+ DBG_CLIENT_BLKID_cb002 = 0x77,
+ DBG_CLIENT_BLKID_cb100 = 0x78,
+ DBG_CLIENT_BLKID_cb000 = 0x79,
+ DBG_CLIENT_BLKID_pa00 = 0x7a,
+ DBG_CLIENT_BLKID_pa10 = 0x7b,
+ DBG_CLIENT_BLKID_ia0 = 0x7c,
+ DBG_CLIENT_BLKID_ia1 = 0x7d,
+ DBG_CLIENT_BLKID_tmonw00 = 0x7e,
+ DBG_CLIENT_BLKID_cb001 = 0x7f,
+ DBG_CLIENT_BLKID_cb003 = 0x80,
+ DBG_CLIENT_BLKID_sx00 = 0x81,
+ DBG_CLIENT_BLKID_sx20 = 0x82,
+ DBG_CLIENT_BLKID_cb203 = 0x83,
+ DBG_CLIENT_BLKID_cb201 = 0x84,
+ DBG_CLIENT_BLKID_cb302 = 0x85,
+ DBG_CLIENT_BLKID_cb202 = 0x86,
+ DBG_CLIENT_BLKID_cb300 = 0x87,
+ DBG_CLIENT_BLKID_cb200 = 0x88,
+ DBG_CLIENT_BLKID_pa01 = 0x89,
+ DBG_CLIENT_BLKID_pa11 = 0x8a,
+ DBG_CLIENT_BLKID_sx30 = 0x8b,
+ DBG_CLIENT_BLKID_cb303 = 0x8c,
+ DBG_CLIENT_BLKID_cb301 = 0x8d,
+ DBG_CLIENT_BLKID_dco = 0x8e,
+ DBG_CLIENT_BLKID_scb0 = 0x8f,
+ DBG_CLIENT_BLKID_scb1 = 0x90,
+ DBG_CLIENT_BLKID_scb2 = 0x91,
+ DBG_CLIENT_BLKID_scb3 = 0x92,
+ DBG_CLIENT_BLKID_tmonw01 = 0x93,
+ DBG_CLIENT_BLKID_RESERVED_LAST = 0x94,
+} DebugBlockId;
+typedef enum DebugBlockId_OLD {
+ DBG_BLOCK_ID_RESERVED = 0x0,
+ DBG_BLOCK_ID_DBG = 0x1,
+ DBG_BLOCK_ID_VMC = 0x2,
+ DBG_BLOCK_ID_PDMA = 0x3,
+ DBG_BLOCK_ID_CG = 0x4,
+ DBG_BLOCK_ID_SRBM = 0x5,
+ DBG_BLOCK_ID_GRBM = 0x6,
+ DBG_BLOCK_ID_RLC = 0x7,
+ DBG_BLOCK_ID_CSC = 0x8,
+ DBG_BLOCK_ID_SEM = 0x9,
+ DBG_BLOCK_ID_IH = 0xa,
+ DBG_BLOCK_ID_SC = 0xb,
+ DBG_BLOCK_ID_SQ = 0xc,
+ DBG_BLOCK_ID_AVP = 0xd,
+ DBG_BLOCK_ID_GMCON = 0xe,
+ DBG_BLOCK_ID_SMU = 0xf,
+ DBG_BLOCK_ID_DMA0 = 0x10,
+ DBG_BLOCK_ID_DMA1 = 0x11,
+ DBG_BLOCK_ID_SPIM = 0x12,
+ DBG_BLOCK_ID_GDS = 0x13,
+ DBG_BLOCK_ID_SPIS = 0x14,
+ DBG_BLOCK_ID_UNUSED0 = 0x15,
+ DBG_BLOCK_ID_PA0 = 0x16,
+ DBG_BLOCK_ID_PA1 = 0x17,
+ DBG_BLOCK_ID_CP0 = 0x18,
+ DBG_BLOCK_ID_CP1 = 0x19,
+ DBG_BLOCK_ID_CP2 = 0x1a,
+ DBG_BLOCK_ID_UNUSED1 = 0x1b,
+ DBG_BLOCK_ID_UVDU = 0x1c,
+ DBG_BLOCK_ID_UVDM = 0x1d,
+ DBG_BLOCK_ID_VCE = 0x1e,
+ DBG_BLOCK_ID_UNUSED2 = 0x1f,
+ DBG_BLOCK_ID_VGT0 = 0x20,
+ DBG_BLOCK_ID_VGT1 = 0x21,
+ DBG_BLOCK_ID_IA = 0x22,
+ DBG_BLOCK_ID_UNUSED3 = 0x23,
+ DBG_BLOCK_ID_SCT0 = 0x24,
+ DBG_BLOCK_ID_SCT1 = 0x25,
+ DBG_BLOCK_ID_SPM0 = 0x26,
+ DBG_BLOCK_ID_SPM1 = 0x27,
+ DBG_BLOCK_ID_TCAA = 0x28,
+ DBG_BLOCK_ID_TCAB = 0x29,
+ DBG_BLOCK_ID_TCCA = 0x2a,
+ DBG_BLOCK_ID_TCCB = 0x2b,
+ DBG_BLOCK_ID_MCC0 = 0x2c,
+ DBG_BLOCK_ID_MCC1 = 0x2d,
+ DBG_BLOCK_ID_MCC2 = 0x2e,
+ DBG_BLOCK_ID_MCC3 = 0x2f,
+ DBG_BLOCK_ID_SX0 = 0x30,
+ DBG_BLOCK_ID_SX1 = 0x31,
+ DBG_BLOCK_ID_SX2 = 0x32,
+ DBG_BLOCK_ID_SX3 = 0x33,
+ DBG_BLOCK_ID_UNUSED4 = 0x34,
+ DBG_BLOCK_ID_UNUSED5 = 0x35,
+ DBG_BLOCK_ID_UNUSED6 = 0x36,
+ DBG_BLOCK_ID_UNUSED7 = 0x37,
+ DBG_BLOCK_ID_PC0 = 0x38,
+ DBG_BLOCK_ID_PC1 = 0x39,
+ DBG_BLOCK_ID_UNUSED8 = 0x3a,
+ DBG_BLOCK_ID_UNUSED9 = 0x3b,
+ DBG_BLOCK_ID_UNUSED10 = 0x3c,
+ DBG_BLOCK_ID_UNUSED11 = 0x3d,
+ DBG_BLOCK_ID_MCB = 0x3e,
+ DBG_BLOCK_ID_UNUSED12 = 0x3f,
+ DBG_BLOCK_ID_SCB0 = 0x40,
+ DBG_BLOCK_ID_SCB1 = 0x41,
+ DBG_BLOCK_ID_UNUSED13 = 0x42,
+ DBG_BLOCK_ID_UNUSED14 = 0x43,
+ DBG_BLOCK_ID_SCF0 = 0x44,
+ DBG_BLOCK_ID_SCF1 = 0x45,
+ DBG_BLOCK_ID_UNUSED15 = 0x46,
+ DBG_BLOCK_ID_UNUSED16 = 0x47,
+ DBG_BLOCK_ID_BCI0 = 0x48,
+ DBG_BLOCK_ID_BCI1 = 0x49,
+ DBG_BLOCK_ID_BCI2 = 0x4a,
+ DBG_BLOCK_ID_BCI3 = 0x4b,
+ DBG_BLOCK_ID_UNUSED17 = 0x4c,
+ DBG_BLOCK_ID_UNUSED18 = 0x4d,
+ DBG_BLOCK_ID_UNUSED19 = 0x4e,
+ DBG_BLOCK_ID_UNUSED20 = 0x4f,
+ DBG_BLOCK_ID_CB00 = 0x50,
+ DBG_BLOCK_ID_CB01 = 0x51,
+ DBG_BLOCK_ID_CB02 = 0x52,
+ DBG_BLOCK_ID_CB03 = 0x53,
+ DBG_BLOCK_ID_CB04 = 0x54,
+ DBG_BLOCK_ID_UNUSED21 = 0x55,
+ DBG_BLOCK_ID_UNUSED22 = 0x56,
+ DBG_BLOCK_ID_UNUSED23 = 0x57,
+ DBG_BLOCK_ID_CB10 = 0x58,
+ DBG_BLOCK_ID_CB11 = 0x59,
+ DBG_BLOCK_ID_CB12 = 0x5a,
+ DBG_BLOCK_ID_CB13 = 0x5b,
+ DBG_BLOCK_ID_CB14 = 0x5c,
+ DBG_BLOCK_ID_UNUSED24 = 0x5d,
+ DBG_BLOCK_ID_UNUSED25 = 0x5e,
+ DBG_BLOCK_ID_UNUSED26 = 0x5f,
+ DBG_BLOCK_ID_TCP0 = 0x60,
+ DBG_BLOCK_ID_TCP1 = 0x61,
+ DBG_BLOCK_ID_TCP2 = 0x62,
+ DBG_BLOCK_ID_TCP3 = 0x63,
+ DBG_BLOCK_ID_TCP4 = 0x64,
+ DBG_BLOCK_ID_TCP5 = 0x65,
+ DBG_BLOCK_ID_TCP6 = 0x66,
+ DBG_BLOCK_ID_TCP7 = 0x67,
+ DBG_BLOCK_ID_TCP8 = 0x68,
+ DBG_BLOCK_ID_TCP9 = 0x69,
+ DBG_BLOCK_ID_TCP10 = 0x6a,
+ DBG_BLOCK_ID_TCP11 = 0x6b,
+ DBG_BLOCK_ID_TCP12 = 0x6c,
+ DBG_BLOCK_ID_TCP13 = 0x6d,
+ DBG_BLOCK_ID_TCP14 = 0x6e,
+ DBG_BLOCK_ID_TCP15 = 0x6f,
+ DBG_BLOCK_ID_TCP16 = 0x70,
+ DBG_BLOCK_ID_TCP17 = 0x71,
+ DBG_BLOCK_ID_TCP18 = 0x72,
+ DBG_BLOCK_ID_TCP19 = 0x73,
+ DBG_BLOCK_ID_TCP20 = 0x74,
+ DBG_BLOCK_ID_TCP21 = 0x75,
+ DBG_BLOCK_ID_TCP22 = 0x76,
+ DBG_BLOCK_ID_TCP23 = 0x77,
+ DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
+ DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
+ DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
+ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
+ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
+ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
+ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
+ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
+ DBG_BLOCK_ID_DB00 = 0x80,
+ DBG_BLOCK_ID_DB01 = 0x81,
+ DBG_BLOCK_ID_DB02 = 0x82,
+ DBG_BLOCK_ID_DB03 = 0x83,
+ DBG_BLOCK_ID_DB04 = 0x84,
+ DBG_BLOCK_ID_UNUSED27 = 0x85,
+ DBG_BLOCK_ID_UNUSED28 = 0x86,
+ DBG_BLOCK_ID_UNUSED29 = 0x87,
+ DBG_BLOCK_ID_DB10 = 0x88,
+ DBG_BLOCK_ID_DB11 = 0x89,
+ DBG_BLOCK_ID_DB12 = 0x8a,
+ DBG_BLOCK_ID_DB13 = 0x8b,
+ DBG_BLOCK_ID_DB14 = 0x8c,
+ DBG_BLOCK_ID_UNUSED30 = 0x8d,
+ DBG_BLOCK_ID_UNUSED31 = 0x8e,
+ DBG_BLOCK_ID_UNUSED32 = 0x8f,
+ DBG_BLOCK_ID_TCC0 = 0x90,
+ DBG_BLOCK_ID_TCC1 = 0x91,
+ DBG_BLOCK_ID_TCC2 = 0x92,
+ DBG_BLOCK_ID_TCC3 = 0x93,
+ DBG_BLOCK_ID_TCC4 = 0x94,
+ DBG_BLOCK_ID_TCC5 = 0x95,
+ DBG_BLOCK_ID_TCC6 = 0x96,
+ DBG_BLOCK_ID_TCC7 = 0x97,
+ DBG_BLOCK_ID_SPS00 = 0x98,
+ DBG_BLOCK_ID_SPS01 = 0x99,
+ DBG_BLOCK_ID_SPS02 = 0x9a,
+ DBG_BLOCK_ID_SPS10 = 0x9b,
+ DBG_BLOCK_ID_SPS11 = 0x9c,
+ DBG_BLOCK_ID_SPS12 = 0x9d,
+ DBG_BLOCK_ID_UNUSED33 = 0x9e,
+ DBG_BLOCK_ID_UNUSED34 = 0x9f,
+ DBG_BLOCK_ID_TA00 = 0xa0,
+ DBG_BLOCK_ID_TA01 = 0xa1,
+ DBG_BLOCK_ID_TA02 = 0xa2,
+ DBG_BLOCK_ID_TA03 = 0xa3,
+ DBG_BLOCK_ID_TA04 = 0xa4,
+ DBG_BLOCK_ID_TA05 = 0xa5,
+ DBG_BLOCK_ID_TA06 = 0xa6,
+ DBG_BLOCK_ID_TA07 = 0xa7,
+ DBG_BLOCK_ID_TA08 = 0xa8,
+ DBG_BLOCK_ID_TA09 = 0xa9,
+ DBG_BLOCK_ID_TA0A = 0xaa,
+ DBG_BLOCK_ID_TA0B = 0xab,
+ DBG_BLOCK_ID_UNUSED35 = 0xac,
+ DBG_BLOCK_ID_UNUSED36 = 0xad,
+ DBG_BLOCK_ID_UNUSED37 = 0xae,
+ DBG_BLOCK_ID_UNUSED38 = 0xaf,
+ DBG_BLOCK_ID_TA10 = 0xb0,
+ DBG_BLOCK_ID_TA11 = 0xb1,
+ DBG_BLOCK_ID_TA12 = 0xb2,
+ DBG_BLOCK_ID_TA13 = 0xb3,
+ DBG_BLOCK_ID_TA14 = 0xb4,
+ DBG_BLOCK_ID_TA15 = 0xb5,
+ DBG_BLOCK_ID_TA16 = 0xb6,
+ DBG_BLOCK_ID_TA17 = 0xb7,
+ DBG_BLOCK_ID_TA18 = 0xb8,
+ DBG_BLOCK_ID_TA19 = 0xb9,
+ DBG_BLOCK_ID_TA1A = 0xba,
+ DBG_BLOCK_ID_TA1B = 0xbb,
+ DBG_BLOCK_ID_UNUSED39 = 0xbc,
+ DBG_BLOCK_ID_UNUSED40 = 0xbd,
+ DBG_BLOCK_ID_UNUSED41 = 0xbe,
+ DBG_BLOCK_ID_UNUSED42 = 0xbf,
+ DBG_BLOCK_ID_TD00 = 0xc0,
+ DBG_BLOCK_ID_TD01 = 0xc1,
+ DBG_BLOCK_ID_TD02 = 0xc2,
+ DBG_BLOCK_ID_TD03 = 0xc3,
+ DBG_BLOCK_ID_TD04 = 0xc4,
+ DBG_BLOCK_ID_TD05 = 0xc5,
+ DBG_BLOCK_ID_TD06 = 0xc6,
+ DBG_BLOCK_ID_TD07 = 0xc7,
+ DBG_BLOCK_ID_TD08 = 0xc8,
+ DBG_BLOCK_ID_TD09 = 0xc9,
+ DBG_BLOCK_ID_TD0A = 0xca,
+ DBG_BLOCK_ID_TD0B = 0xcb,
+ DBG_BLOCK_ID_UNUSED43 = 0xcc,
+ DBG_BLOCK_ID_UNUSED44 = 0xcd,
+ DBG_BLOCK_ID_UNUSED45 = 0xce,
+ DBG_BLOCK_ID_UNUSED46 = 0xcf,
+ DBG_BLOCK_ID_TD10 = 0xd0,
+ DBG_BLOCK_ID_TD11 = 0xd1,
+ DBG_BLOCK_ID_TD12 = 0xd2,
+ DBG_BLOCK_ID_TD13 = 0xd3,
+ DBG_BLOCK_ID_TD14 = 0xd4,
+ DBG_BLOCK_ID_TD15 = 0xd5,
+ DBG_BLOCK_ID_TD16 = 0xd6,
+ DBG_BLOCK_ID_TD17 = 0xd7,
+ DBG_BLOCK_ID_TD18 = 0xd8,
+ DBG_BLOCK_ID_TD19 = 0xd9,
+ DBG_BLOCK_ID_TD1A = 0xda,
+ DBG_BLOCK_ID_TD1B = 0xdb,
+ DBG_BLOCK_ID_UNUSED47 = 0xdc,
+ DBG_BLOCK_ID_UNUSED48 = 0xdd,
+ DBG_BLOCK_ID_UNUSED49 = 0xde,
+ DBG_BLOCK_ID_UNUSED50 = 0xdf,
+ DBG_BLOCK_ID_MCD0 = 0xe0,
+ DBG_BLOCK_ID_MCD1 = 0xe1,
+ DBG_BLOCK_ID_MCD2 = 0xe2,
+ DBG_BLOCK_ID_MCD3 = 0xe3,
+ DBG_BLOCK_ID_MCD4 = 0xe4,
+ DBG_BLOCK_ID_MCD5 = 0xe5,
+ DBG_BLOCK_ID_UNUSED51 = 0xe6,
+ DBG_BLOCK_ID_UNUSED52 = 0xe7,
+} DebugBlockId_OLD;
+typedef enum DebugBlockId_BY2 {
+ DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
+ DBG_BLOCK_ID_VMC_BY2 = 0x1,
+ DBG_BLOCK_ID_CG_BY2 = 0x2,
+ DBG_BLOCK_ID_GRBM_BY2 = 0x3,
+ DBG_BLOCK_ID_CSC_BY2 = 0x4,
+ DBG_BLOCK_ID_IH_BY2 = 0x5,
+ DBG_BLOCK_ID_SQ_BY2 = 0x6,
+ DBG_BLOCK_ID_GMCON_BY2 = 0x7,
+ DBG_BLOCK_ID_DMA0_BY2 = 0x8,
+ DBG_BLOCK_ID_SPIM_BY2 = 0x9,
+ DBG_BLOCK_ID_SPIS_BY2 = 0xa,
+ DBG_BLOCK_ID_PA0_BY2 = 0xb,
+ DBG_BLOCK_ID_CP0_BY2 = 0xc,
+ DBG_BLOCK_ID_CP2_BY2 = 0xd,
+ DBG_BLOCK_ID_UVDU_BY2 = 0xe,
+ DBG_BLOCK_ID_VCE_BY2 = 0xf,
+ DBG_BLOCK_ID_VGT0_BY2 = 0x10,
+ DBG_BLOCK_ID_IA_BY2 = 0x11,
+ DBG_BLOCK_ID_SCT0_BY2 = 0x12,
+ DBG_BLOCK_ID_SPM0_BY2 = 0x13,
+ DBG_BLOCK_ID_TCAA_BY2 = 0x14,
+ DBG_BLOCK_ID_TCCA_BY2 = 0x15,
+ DBG_BLOCK_ID_MCC0_BY2 = 0x16,
+ DBG_BLOCK_ID_MCC2_BY2 = 0x17,
+ DBG_BLOCK_ID_SX0_BY2 = 0x18,
+ DBG_BLOCK_ID_SX2_BY2 = 0x19,
+ DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
+ DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
+ DBG_BLOCK_ID_PC0_BY2 = 0x1c,
+ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
+ DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
+ DBG_BLOCK_ID_MCB_BY2 = 0x1f,
+ DBG_BLOCK_ID_SCB0_BY2 = 0x20,
+ DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
+ DBG_BLOCK_ID_SCF0_BY2 = 0x22,
+ DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
+ DBG_BLOCK_ID_BCI0_BY2 = 0x24,
+ DBG_BLOCK_ID_BCI2_BY2 = 0x25,
+ DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
+ DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
+ DBG_BLOCK_ID_CB00_BY2 = 0x28,
+ DBG_BLOCK_ID_CB02_BY2 = 0x29,
+ DBG_BLOCK_ID_CB04_BY2 = 0x2a,
+ DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
+ DBG_BLOCK_ID_CB10_BY2 = 0x2c,
+ DBG_BLOCK_ID_CB12_BY2 = 0x2d,
+ DBG_BLOCK_ID_CB14_BY2 = 0x2e,
+ DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
+ DBG_BLOCK_ID_TCP0_BY2 = 0x30,
+ DBG_BLOCK_ID_TCP2_BY2 = 0x31,
+ DBG_BLOCK_ID_TCP4_BY2 = 0x32,
+ DBG_BLOCK_ID_TCP6_BY2 = 0x33,
+ DBG_BLOCK_ID_TCP8_BY2 = 0x34,
+ DBG_BLOCK_ID_TCP10_BY2 = 0x35,
+ DBG_BLOCK_ID_TCP12_BY2 = 0x36,
+ DBG_BLOCK_ID_TCP14_BY2 = 0x37,
+ DBG_BLOCK_ID_TCP16_BY2 = 0x38,
+ DBG_BLOCK_ID_TCP18_BY2 = 0x39,
+ DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
+ DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
+ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
+ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
+ DBG_BLOCK_ID_DB00_BY2 = 0x40,
+ DBG_BLOCK_ID_DB02_BY2 = 0x41,
+ DBG_BLOCK_ID_DB04_BY2 = 0x42,
+ DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
+ DBG_BLOCK_ID_DB10_BY2 = 0x44,
+ DBG_BLOCK_ID_DB12_BY2 = 0x45,
+ DBG_BLOCK_ID_DB14_BY2 = 0x46,
+ DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
+ DBG_BLOCK_ID_TCC0_BY2 = 0x48,
+ DBG_BLOCK_ID_TCC2_BY2 = 0x49,
+ DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
+ DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
+ DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
+ DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
+ DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
+ DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
+ DBG_BLOCK_ID_TA00_BY2 = 0x50,
+ DBG_BLOCK_ID_TA02_BY2 = 0x51,
+ DBG_BLOCK_ID_TA04_BY2 = 0x52,
+ DBG_BLOCK_ID_TA06_BY2 = 0x53,
+ DBG_BLOCK_ID_TA08_BY2 = 0x54,
+ DBG_BLOCK_ID_TA0A_BY2 = 0x55,
+ DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
+ DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
+ DBG_BLOCK_ID_TA10_BY2 = 0x58,
+ DBG_BLOCK_ID_TA12_BY2 = 0x59,
+ DBG_BLOCK_ID_TA14_BY2 = 0x5a,
+ DBG_BLOCK_ID_TA16_BY2 = 0x5b,
+ DBG_BLOCK_ID_TA18_BY2 = 0x5c,
+ DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
+ DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
+ DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
+ DBG_BLOCK_ID_TD00_BY2 = 0x60,
+ DBG_BLOCK_ID_TD02_BY2 = 0x61,
+ DBG_BLOCK_ID_TD04_BY2 = 0x62,
+ DBG_BLOCK_ID_TD06_BY2 = 0x63,
+ DBG_BLOCK_ID_TD08_BY2 = 0x64,
+ DBG_BLOCK_ID_TD0A_BY2 = 0x65,
+ DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
+ DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
+ DBG_BLOCK_ID_TD10_BY2 = 0x68,
+ DBG_BLOCK_ID_TD12_BY2 = 0x69,
+ DBG_BLOCK_ID_TD14_BY2 = 0x6a,
+ DBG_BLOCK_ID_TD16_BY2 = 0x6b,
+ DBG_BLOCK_ID_TD18_BY2 = 0x6c,
+ DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
+ DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
+ DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
+ DBG_BLOCK_ID_MCD0_BY2 = 0x70,
+ DBG_BLOCK_ID_MCD2_BY2 = 0x71,
+ DBG_BLOCK_ID_MCD4_BY2 = 0x72,
+ DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
+} DebugBlockId_BY2;
+typedef enum DebugBlockId_BY4 {
+ DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
+ DBG_BLOCK_ID_CG_BY4 = 0x1,
+ DBG_BLOCK_ID_CSC_BY4 = 0x2,
+ DBG_BLOCK_ID_SQ_BY4 = 0x3,
+ DBG_BLOCK_ID_DMA0_BY4 = 0x4,
+ DBG_BLOCK_ID_SPIS_BY4 = 0x5,
+ DBG_BLOCK_ID_CP0_BY4 = 0x6,
+ DBG_BLOCK_ID_UVDU_BY4 = 0x7,
+ DBG_BLOCK_ID_VGT0_BY4 = 0x8,
+ DBG_BLOCK_ID_SCT0_BY4 = 0x9,
+ DBG_BLOCK_ID_TCAA_BY4 = 0xa,
+ DBG_BLOCK_ID_MCC0_BY4 = 0xb,
+ DBG_BLOCK_ID_SX0_BY4 = 0xc,
+ DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
+ DBG_BLOCK_ID_PC0_BY4 = 0xe,
+ DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
+ DBG_BLOCK_ID_SCB0_BY4 = 0x10,
+ DBG_BLOCK_ID_SCF0_BY4 = 0x11,
+ DBG_BLOCK_ID_BCI0_BY4 = 0x12,
+ DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
+ DBG_BLOCK_ID_CB00_BY4 = 0x14,
+ DBG_BLOCK_ID_CB04_BY4 = 0x15,
+ DBG_BLOCK_ID_CB10_BY4 = 0x16,
+ DBG_BLOCK_ID_CB14_BY4 = 0x17,
+ DBG_BLOCK_ID_TCP0_BY4 = 0x18,
+ DBG_BLOCK_ID_TCP4_BY4 = 0x19,
+ DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
+ DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
+ DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
+ DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
+ DBG_BLOCK_ID_DB_BY4 = 0x20,
+ DBG_BLOCK_ID_DB04_BY4 = 0x21,
+ DBG_BLOCK_ID_DB10_BY4 = 0x22,
+ DBG_BLOCK_ID_DB14_BY4 = 0x23,
+ DBG_BLOCK_ID_TCC0_BY4 = 0x24,
+ DBG_BLOCK_ID_TCC4_BY4 = 0x25,
+ DBG_BLOCK_ID_SPS00_BY4 = 0x26,
+ DBG_BLOCK_ID_SPS11_BY4 = 0x27,
+ DBG_BLOCK_ID_TA00_BY4 = 0x28,
+ DBG_BLOCK_ID_TA04_BY4 = 0x29,
+ DBG_BLOCK_ID_TA08_BY4 = 0x2a,
+ DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
+ DBG_BLOCK_ID_TA10_BY4 = 0x2c,
+ DBG_BLOCK_ID_TA14_BY4 = 0x2d,
+ DBG_BLOCK_ID_TA18_BY4 = 0x2e,
+ DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
+ DBG_BLOCK_ID_TD00_BY4 = 0x30,
+ DBG_BLOCK_ID_TD04_BY4 = 0x31,
+ DBG_BLOCK_ID_TD08_BY4 = 0x32,
+ DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
+ DBG_BLOCK_ID_TD10_BY4 = 0x34,
+ DBG_BLOCK_ID_TD14_BY4 = 0x35,
+ DBG_BLOCK_ID_TD18_BY4 = 0x36,
+ DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
+ DBG_BLOCK_ID_MCD0_BY4 = 0x38,
+ DBG_BLOCK_ID_MCD4_BY4 = 0x39,
+} DebugBlockId_BY4;
+typedef enum DebugBlockId_BY8 {
+ DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
+ DBG_BLOCK_ID_CSC_BY8 = 0x1,
+ DBG_BLOCK_ID_DMA0_BY8 = 0x2,
+ DBG_BLOCK_ID_CP0_BY8 = 0x3,
+ DBG_BLOCK_ID_VGT0_BY8 = 0x4,
+ DBG_BLOCK_ID_TCAA_BY8 = 0x5,
+ DBG_BLOCK_ID_SX0_BY8 = 0x6,
+ DBG_BLOCK_ID_PC0_BY8 = 0x7,
+ DBG_BLOCK_ID_SCB0_BY8 = 0x8,
+ DBG_BLOCK_ID_BCI0_BY8 = 0x9,
+ DBG_BLOCK_ID_CB00_BY8 = 0xa,
+ DBG_BLOCK_ID_CB10_BY8 = 0xb,
+ DBG_BLOCK_ID_TCP0_BY8 = 0xc,
+ DBG_BLOCK_ID_TCP8_BY8 = 0xd,
+ DBG_BLOCK_ID_TCP16_BY8 = 0xe,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
+ DBG_BLOCK_ID_DB00_BY8 = 0x10,
+ DBG_BLOCK_ID_DB10_BY8 = 0x11,
+ DBG_BLOCK_ID_TCC0_BY8 = 0x12,
+ DBG_BLOCK_ID_SPS00_BY8 = 0x13,
+ DBG_BLOCK_ID_TA00_BY8 = 0x14,
+ DBG_BLOCK_ID_TA08_BY8 = 0x15,
+ DBG_BLOCK_ID_TA10_BY8 = 0x16,
+ DBG_BLOCK_ID_TA18_BY8 = 0x17,
+ DBG_BLOCK_ID_TD00_BY8 = 0x18,
+ DBG_BLOCK_ID_TD08_BY8 = 0x19,
+ DBG_BLOCK_ID_TD10_BY8 = 0x1a,
+ DBG_BLOCK_ID_TD18_BY8 = 0x1b,
+ DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
+} DebugBlockId_BY8;
+typedef enum DebugBlockId_BY16 {
+ DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
+ DBG_BLOCK_ID_DMA0_BY16 = 0x1,
+ DBG_BLOCK_ID_VGT0_BY16 = 0x2,
+ DBG_BLOCK_ID_SX0_BY16 = 0x3,
+ DBG_BLOCK_ID_SCB0_BY16 = 0x4,
+ DBG_BLOCK_ID_CB00_BY16 = 0x5,
+ DBG_BLOCK_ID_TCP0_BY16 = 0x6,
+ DBG_BLOCK_ID_TCP16_BY16 = 0x7,
+ DBG_BLOCK_ID_DB00_BY16 = 0x8,
+ DBG_BLOCK_ID_TCC0_BY16 = 0x9,
+ DBG_BLOCK_ID_TA00_BY16 = 0xa,
+ DBG_BLOCK_ID_TA10_BY16 = 0xb,
+ DBG_BLOCK_ID_TD00_BY16 = 0xc,
+ DBG_BLOCK_ID_TD10_BY16 = 0xd,
+ DBG_BLOCK_ID_MCD0_BY16 = 0xe,
+} DebugBlockId_BY16;
+typedef enum CompareRef {
+ REF_NEVER = 0x0,
+ REF_LESS = 0x1,
+ REF_EQUAL = 0x2,
+ REF_LEQUAL = 0x3,
+ REF_GREATER = 0x4,
+ REF_NOTEQUAL = 0x5,
+ REF_GEQUAL = 0x6,
+ REF_ALWAYS = 0x7,
+} CompareRef;
+typedef enum ReadSize {
+ READ_256_BITS = 0x0,
+ READ_512_BITS = 0x1,
+} ReadSize;
+typedef enum DepthFormat {
+ DEPTH_INVALID = 0x0,
+ DEPTH_16 = 0x1,
+ DEPTH_X8_24 = 0x2,
+ DEPTH_8_24 = 0x3,
+ DEPTH_X8_24_FLOAT = 0x4,
+ DEPTH_8_24_FLOAT = 0x5,
+ DEPTH_32_FLOAT = 0x6,
+ DEPTH_X24_8_32_FLOAT = 0x7,
+} DepthFormat;
+typedef enum ZFormat {
+ Z_INVALID = 0x0,
+ Z_16 = 0x1,
+ Z_24 = 0x2,
+ Z_32_FLOAT = 0x3,
+} ZFormat;
+typedef enum StencilFormat {
+ STENCIL_INVALID = 0x0,
+ STENCIL_8 = 0x1,
+} StencilFormat;
+typedef enum CmaskMode {
+ CMASK_CLEAR_NONE = 0x0,
+ CMASK_CLEAR_ONE = 0x1,
+ CMASK_CLEAR_ALL = 0x2,
+ CMASK_ANY_EXPANDED = 0x3,
+ CMASK_ALPHA0_FRAG1 = 0x4,
+ CMASK_ALPHA0_FRAG2 = 0x5,
+ CMASK_ALPHA0_FRAG4 = 0x6,
+ CMASK_ALPHA0_FRAGS = 0x7,
+ CMASK_ALPHA1_FRAG1 = 0x8,
+ CMASK_ALPHA1_FRAG2 = 0x9,
+ CMASK_ALPHA1_FRAG4 = 0xa,
+ CMASK_ALPHA1_FRAGS = 0xb,
+ CMASK_ALPHAX_FRAG1 = 0xc,
+ CMASK_ALPHAX_FRAG2 = 0xd,
+ CMASK_ALPHAX_FRAG4 = 0xe,
+ CMASK_ALPHAX_FRAGS = 0xf,
+} CmaskMode;
+typedef enum QuadExportFormat {
+ EXPORT_UNUSED = 0x0,
+ EXPORT_32_R = 0x1,
+ EXPORT_32_GR = 0x2,
+ EXPORT_32_AR = 0x3,
+ EXPORT_FP16_ABGR = 0x4,
+ EXPORT_UNSIGNED16_ABGR = 0x5,
+ EXPORT_SIGNED16_ABGR = 0x6,
+ EXPORT_32_ABGR = 0x7,
+} QuadExportFormat;
+typedef enum QuadExportFormatOld {
+ EXPORT_4P_32BPC_ABGR = 0x0,
+ EXPORT_4P_16BPC_ABGR = 0x1,
+ EXPORT_4P_32BPC_GR = 0x2,
+ EXPORT_4P_32BPC_AR = 0x3,
+ EXPORT_2P_32BPC_ABGR = 0x4,
+ EXPORT_8P_32BPC_R = 0x5,
+} QuadExportFormatOld;
+typedef enum ColorFormat {
+ COLOR_INVALID = 0x0,
+ COLOR_8 = 0x1,
+ COLOR_16 = 0x2,
+ COLOR_8_8 = 0x3,
+ COLOR_32 = 0x4,
+ COLOR_16_16 = 0x5,
+ COLOR_10_11_11 = 0x6,
+ COLOR_11_11_10 = 0x7,
+ COLOR_10_10_10_2 = 0x8,
+ COLOR_2_10_10_10 = 0x9,
+ COLOR_8_8_8_8 = 0xa,
+ COLOR_32_32 = 0xb,
+ COLOR_16_16_16_16 = 0xc,
+ COLOR_RESERVED_13 = 0xd,
+ COLOR_32_32_32_32 = 0xe,
+ COLOR_RESERVED_15 = 0xf,
+ COLOR_5_6_5 = 0x10,
+ COLOR_1_5_5_5 = 0x11,
+ COLOR_5_5_5_1 = 0x12,
+ COLOR_4_4_4_4 = 0x13,
+ COLOR_8_24 = 0x14,
+ COLOR_24_8 = 0x15,
+ COLOR_X24_8_32_FLOAT = 0x16,
+ COLOR_RESERVED_23 = 0x17,
+} ColorFormat;
+typedef enum SurfaceFormat {
+ FMT_INVALID = 0x0,
+ FMT_8 = 0x1,
+ FMT_16 = 0x2,
+ FMT_8_8 = 0x3,
+ FMT_32 = 0x4,
+ FMT_16_16 = 0x5,
+ FMT_10_11_11 = 0x6,
+ FMT_11_11_10 = 0x7,
+ FMT_10_10_10_2 = 0x8,
+ FMT_2_10_10_10 = 0x9,
+ FMT_8_8_8_8 = 0xa,
+ FMT_32_32 = 0xb,
+ FMT_16_16_16_16 = 0xc,
+ FMT_32_32_32 = 0xd,
+ FMT_32_32_32_32 = 0xe,
+ FMT_RESERVED_4 = 0xf,
+ FMT_5_6_5 = 0x10,
+ FMT_1_5_5_5 = 0x11,
+ FMT_5_5_5_1 = 0x12,
+ FMT_4_4_4_4 = 0x13,
+ FMT_8_24 = 0x14,
+ FMT_24_8 = 0x15,
+ FMT_X24_8_32_FLOAT = 0x16,
+ FMT_RESERVED_33 = 0x17,
+ FMT_11_11_10_FLOAT = 0x18,
+ FMT_16_FLOAT = 0x19,
+ FMT_32_FLOAT = 0x1a,
+ FMT_16_16_FLOAT = 0x1b,
+ FMT_8_24_FLOAT = 0x1c,
+ FMT_24_8_FLOAT = 0x1d,
+ FMT_32_32_FLOAT = 0x1e,
+ FMT_10_11_11_FLOAT = 0x1f,
+ FMT_16_16_16_16_FLOAT = 0x20,
+ FMT_3_3_2 = 0x21,
+ FMT_6_5_5 = 0x22,
+ FMT_32_32_32_32_FLOAT = 0x23,
+ FMT_RESERVED_36 = 0x24,
+ FMT_1 = 0x25,
+ FMT_1_REVERSED = 0x26,
+ FMT_GB_GR = 0x27,
+ FMT_BG_RG = 0x28,
+ FMT_32_AS_8 = 0x29,
+ FMT_32_AS_8_8 = 0x2a,
+ FMT_5_9_9_9_SHAREDEXP = 0x2b,
+ FMT_8_8_8 = 0x2c,
+ FMT_16_16_16 = 0x2d,
+ FMT_16_16_16_FLOAT = 0x2e,
+ FMT_4_4 = 0x2f,
+ FMT_32_32_32_FLOAT = 0x30,
+ FMT_BC1 = 0x31,
+ FMT_BC2 = 0x32,
+ FMT_BC3 = 0x33,
+ FMT_BC4 = 0x34,
+ FMT_BC5 = 0x35,
+ FMT_BC6 = 0x36,
+ FMT_BC7 = 0x37,
+ FMT_32_AS_32_32_32_32 = 0x38,
+ FMT_APC3 = 0x39,
+ FMT_APC4 = 0x3a,
+ FMT_APC5 = 0x3b,
+ FMT_APC6 = 0x3c,
+ FMT_APC7 = 0x3d,
+ FMT_CTX1 = 0x3e,
+ FMT_RESERVED_63 = 0x3f,
+} SurfaceFormat;
+typedef enum BUF_DATA_FORMAT {
+ BUF_DATA_FORMAT_INVALID = 0x0,
+ BUF_DATA_FORMAT_8 = 0x1,
+ BUF_DATA_FORMAT_16 = 0x2,
+ BUF_DATA_FORMAT_8_8 = 0x3,
+ BUF_DATA_FORMAT_32 = 0x4,
+ BUF_DATA_FORMAT_16_16 = 0x5,
+ BUF_DATA_FORMAT_10_11_11 = 0x6,
+ BUF_DATA_FORMAT_11_11_10 = 0x7,
+ BUF_DATA_FORMAT_10_10_10_2 = 0x8,
+ BUF_DATA_FORMAT_2_10_10_10 = 0x9,
+ BUF_DATA_FORMAT_8_8_8_8 = 0xa,
+ BUF_DATA_FORMAT_32_32 = 0xb,
+ BUF_DATA_FORMAT_16_16_16_16 = 0xc,
+ BUF_DATA_FORMAT_32_32_32 = 0xd,
+ BUF_DATA_FORMAT_32_32_32_32 = 0xe,
+ BUF_DATA_FORMAT_RESERVED_15 = 0xf,
+} BUF_DATA_FORMAT;
+typedef enum IMG_DATA_FORMAT {
+ IMG_DATA_FORMAT_INVALID = 0x0,
+ IMG_DATA_FORMAT_8 = 0x1,
+ IMG_DATA_FORMAT_16 = 0x2,
+ IMG_DATA_FORMAT_8_8 = 0x3,
+ IMG_DATA_FORMAT_32 = 0x4,
+ IMG_DATA_FORMAT_16_16 = 0x5,
+ IMG_DATA_FORMAT_10_11_11 = 0x6,
+ IMG_DATA_FORMAT_11_11_10 = 0x7,
+ IMG_DATA_FORMAT_10_10_10_2 = 0x8,
+ IMG_DATA_FORMAT_2_10_10_10 = 0x9,
+ IMG_DATA_FORMAT_8_8_8_8 = 0xa,
+ IMG_DATA_FORMAT_32_32 = 0xb,
+ IMG_DATA_FORMAT_16_16_16_16 = 0xc,
+ IMG_DATA_FORMAT_32_32_32 = 0xd,
+ IMG_DATA_FORMAT_32_32_32_32 = 0xe,
+ IMG_DATA_FORMAT_RESERVED_15 = 0xf,
+ IMG_DATA_FORMAT_5_6_5 = 0x10,
+ IMG_DATA_FORMAT_1_5_5_5 = 0x11,
+ IMG_DATA_FORMAT_5_5_5_1 = 0x12,
+ IMG_DATA_FORMAT_4_4_4_4 = 0x13,
+ IMG_DATA_FORMAT_8_24 = 0x14,
+ IMG_DATA_FORMAT_24_8 = 0x15,
+ IMG_DATA_FORMAT_X24_8_32 = 0x16,
+ IMG_DATA_FORMAT_RESERVED_23 = 0x17,
+ IMG_DATA_FORMAT_RESERVED_24 = 0x18,
+ IMG_DATA_FORMAT_RESERVED_25 = 0x19,
+ IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
+ IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
+ IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
+ IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
+ IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
+ IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
+ IMG_DATA_FORMAT_GB_GR = 0x20,
+ IMG_DATA_FORMAT_BG_RG = 0x21,
+ IMG_DATA_FORMAT_5_9_9_9 = 0x22,
+ IMG_DATA_FORMAT_BC1 = 0x23,
+ IMG_DATA_FORMAT_BC2 = 0x24,
+ IMG_DATA_FORMAT_BC3 = 0x25,
+ IMG_DATA_FORMAT_BC4 = 0x26,
+ IMG_DATA_FORMAT_BC5 = 0x27,
+ IMG_DATA_FORMAT_BC6 = 0x28,
+ IMG_DATA_FORMAT_BC7 = 0x29,
+ IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
+ IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
+ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
+ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
+ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
+ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
+ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
+ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
+ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
+ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
+ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
+ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
+ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
+ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
+ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
+ IMG_DATA_FORMAT_4_4 = 0x39,
+ IMG_DATA_FORMAT_6_5_5 = 0x3a,
+ IMG_DATA_FORMAT_1 = 0x3b,
+ IMG_DATA_FORMAT_1_REVERSED = 0x3c,
+ IMG_DATA_FORMAT_32_AS_8 = 0x3d,
+ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
+ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
+} IMG_DATA_FORMAT;
+typedef enum BUF_NUM_FORMAT {
+ BUF_NUM_FORMAT_UNORM = 0x0,
+ BUF_NUM_FORMAT_SNORM = 0x1,
+ BUF_NUM_FORMAT_USCALED = 0x2,
+ BUF_NUM_FORMAT_SSCALED = 0x3,
+ BUF_NUM_FORMAT_UINT = 0x4,
+ BUF_NUM_FORMAT_SINT = 0x5,
+ BUF_NUM_FORMAT_SNORM_OGL = 0x6,
+ BUF_NUM_FORMAT_FLOAT = 0x7,
+} BUF_NUM_FORMAT;
+typedef enum IMG_NUM_FORMAT {
+ IMG_NUM_FORMAT_UNORM = 0x0,
+ IMG_NUM_FORMAT_SNORM = 0x1,
+ IMG_NUM_FORMAT_USCALED = 0x2,
+ IMG_NUM_FORMAT_SSCALED = 0x3,
+ IMG_NUM_FORMAT_UINT = 0x4,
+ IMG_NUM_FORMAT_SINT = 0x5,
+ IMG_NUM_FORMAT_SNORM_OGL = 0x6,
+ IMG_NUM_FORMAT_FLOAT = 0x7,
+ IMG_NUM_FORMAT_RESERVED_8 = 0x8,
+ IMG_NUM_FORMAT_SRGB = 0x9,
+ IMG_NUM_FORMAT_UBNORM = 0xa,
+ IMG_NUM_FORMAT_UBNORM_OGL = 0xb,
+ IMG_NUM_FORMAT_UBINT = 0xc,
+ IMG_NUM_FORMAT_UBSCALED = 0xd,
+ IMG_NUM_FORMAT_RESERVED_14 = 0xe,
+ IMG_NUM_FORMAT_RESERVED_15 = 0xf,
+} IMG_NUM_FORMAT;
+typedef enum TileType {
+ ARRAY_COLOR_TILE = 0x0,
+ ARRAY_DEPTH_TILE = 0x1,
+} TileType;
+typedef enum NonDispTilingOrder {
+ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
+ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
+} NonDispTilingOrder;
+typedef enum MicroTileMode {
+ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
+ ADDR_SURF_THIN_MICRO_TILING = 0x1,
+ ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
+ ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
+ ADDR_SURF_THICK_MICRO_TILING = 0x4,
+} MicroTileMode;
+typedef enum TileSplit {
+ ADDR_SURF_TILE_SPLIT_64B = 0x0,
+ ADDR_SURF_TILE_SPLIT_128B = 0x1,
+ ADDR_SURF_TILE_SPLIT_256B = 0x2,
+ ADDR_SURF_TILE_SPLIT_512B = 0x3,
+ ADDR_SURF_TILE_SPLIT_1KB = 0x4,
+ ADDR_SURF_TILE_SPLIT_2KB = 0x5,
+ ADDR_SURF_TILE_SPLIT_4KB = 0x6,
+} TileSplit;
+typedef enum SampleSplit {
+ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
+ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
+ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
+ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
+} SampleSplit;
+typedef enum PipeConfig {
+ ADDR_SURF_P2 = 0x0,
+ ADDR_SURF_P2_RESERVED0 = 0x1,
+ ADDR_SURF_P2_RESERVED1 = 0x2,
+ ADDR_SURF_P2_RESERVED2 = 0x3,
+ ADDR_SURF_P4_8x16 = 0x4,
+ ADDR_SURF_P4_16x16 = 0x5,
+ ADDR_SURF_P4_16x32 = 0x6,
+ ADDR_SURF_P4_32x32 = 0x7,
+ ADDR_SURF_P8_16x16_8x16 = 0x8,
+ ADDR_SURF_P8_16x32_8x16 = 0x9,
+ ADDR_SURF_P8_32x32_8x16 = 0xa,
+ ADDR_SURF_P8_16x32_16x16 = 0xb,
+ ADDR_SURF_P8_32x32_16x16 = 0xc,
+ ADDR_SURF_P8_32x32_16x32 = 0xd,
+ ADDR_SURF_P8_32x64_32x32 = 0xe,
+ ADDR_SURF_P8_RESERVED0 = 0xf,
+ ADDR_SURF_P16_32x32_8x16 = 0x10,
+ ADDR_SURF_P16_32x32_16x16 = 0x11,
+} PipeConfig;
+typedef enum NumBanks {
+ ADDR_SURF_2_BANK = 0x0,
+ ADDR_SURF_4_BANK = 0x1,
+ ADDR_SURF_8_BANK = 0x2,
+ ADDR_SURF_16_BANK = 0x3,
+} NumBanks;
+typedef enum BankWidth {
+ ADDR_SURF_BANK_WIDTH_1 = 0x0,
+ ADDR_SURF_BANK_WIDTH_2 = 0x1,
+ ADDR_SURF_BANK_WIDTH_4 = 0x2,
+ ADDR_SURF_BANK_WIDTH_8 = 0x3,
+} BankWidth;
+typedef enum BankHeight {
+ ADDR_SURF_BANK_HEIGHT_1 = 0x0,
+ ADDR_SURF_BANK_HEIGHT_2 = 0x1,
+ ADDR_SURF_BANK_HEIGHT_4 = 0x2,
+ ADDR_SURF_BANK_HEIGHT_8 = 0x3,
+} BankHeight;
+typedef enum BankWidthHeight {
+ ADDR_SURF_BANK_WH_1 = 0x0,
+ ADDR_SURF_BANK_WH_2 = 0x1,
+ ADDR_SURF_BANK_WH_4 = 0x2,
+ ADDR_SURF_BANK_WH_8 = 0x3,
+} BankWidthHeight;
+typedef enum MacroTileAspect {
+ ADDR_SURF_MACRO_ASPECT_1 = 0x0,
+ ADDR_SURF_MACRO_ASPECT_2 = 0x1,
+ ADDR_SURF_MACRO_ASPECT_4 = 0x2,
+ ADDR_SURF_MACRO_ASPECT_8 = 0x3,
+} MacroTileAspect;
+typedef enum TCC_CACHE_POLICIES {
+ TCC_CACHE_POLICY_LRU = 0x0,
+ TCC_CACHE_POLICY_STREAM = 0x1,
+ TCC_CACHE_POLICY_BYPASS = 0x2,
+} TCC_CACHE_POLICIES;
+typedef enum PERFMON_COUNTER_MODE {
+ PERFMON_COUNTER_MODE_ACCUM = 0x0,
+ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
+ PERFMON_COUNTER_MODE_MAX = 0x2,
+ PERFMON_COUNTER_MODE_DIRTY = 0x3,
+ PERFMON_COUNTER_MODE_SAMPLE = 0x4,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
+ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
+ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
+ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
+ PERFMON_COUNTER_MODE_RESERVED = 0xf,
+} PERFMON_COUNTER_MODE;
+typedef enum PERFMON_SPM_MODE {
+ PERFMON_SPM_MODE_OFF = 0x0,
+ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
+ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
+ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
+ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
+ PERFMON_SPM_MODE_RESERVED_5 = 0x5,
+ PERFMON_SPM_MODE_RESERVED_6 = 0x6,
+ PERFMON_SPM_MODE_RESERVED_7 = 0x7,
+ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
+ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
+ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
+} PERFMON_SPM_MODE;
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0x0,
+ ARRAY_TILED = 0x1,
+} SurfaceTiling;
+typedef enum SurfaceArray {
+ ARRAY_1D = 0x0,
+ ARRAY_2D = 0x1,
+ ARRAY_3D = 0x2,
+ ARRAY_3D_SLICE = 0x3,
+} SurfaceArray;
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0x0,
+ ARRAY_2D_COLOR = 0x1,
+ ARRAY_3D_SLICE_COLOR = 0x3,
+} ColorArray;
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0x0,
+ ARRAY_2D_DEPTH = 0x1,
+} DepthArray;
+
+#endif /* GFX_7_2_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h
new file mode 100644
index 000000000000..4509c8237db5
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h
@@ -0,0 +1,18444 @@
+/*
+ * GFX_7_2 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GFX_7_2_SH_MASK_H
+#define GFX_7_2_SH_MASK_H
+
+#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
+#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
+#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
+#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
+#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
+#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
+#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
+#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
+#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
+#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
+#define CB_COLOR_CONTROL__MODE_MASK 0x70
+#define CB_COLOR_CONTROL__MODE__SHIFT 0x4
+#define CB_COLOR_CONTROL__ROP3_MASK 0xff0000
+#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
+#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR0_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR1_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR2_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR3_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR4_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR5_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR6_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR7_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR0_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR0_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR0_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR1_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR1_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR1_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR2_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR2_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR2_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR3_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR3_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR3_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR4_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR4_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR4_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR5_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR5_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR5_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR6_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR6_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR6_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR7_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR7_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR7_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0xf
+#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0
+#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0xf0
+#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4
+#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0xf00
+#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8
+#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0xf000
+#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc
+#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0xf0000
+#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10
+#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0xf00000
+#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14
+#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0xf000000
+#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18
+#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000
+#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c
+#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0xf
+#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0
+#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0xf0
+#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4
+#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0xf00
+#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8
+#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0xf000
+#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc
+#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0xf0000
+#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10
+#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0xf00000
+#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14
+#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0xf000000
+#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18
+#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000
+#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c
+#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0xf
+#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0
+#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x3c0
+#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6
+#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0xf000
+#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc
+#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x10000
+#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10
+#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x40000
+#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
+#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x80000
+#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
+#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x100000
+#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x200000
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
+#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x400000
+#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
+#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x800000
+#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x1000000
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x2000000
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x4000000
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x8000000
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
+#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000
+#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
+#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000
+#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
+#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000
+#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
+#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000
+#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
+#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x1f
+#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
+#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x7e0
+#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
+#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x1f800
+#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
+#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x3fe0000
+#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
+#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000
+#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x1a
+#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0xff
+#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
+#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x7f00
+#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
+#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x7f8000
+#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
+#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xff000000
+#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x18
+#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x1
+#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x1
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0xe
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x10
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x3e0
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x400
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x1000
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0xe000
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x20000
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x1c0000
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x200000
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0xc00000
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x7fc00
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x1ff
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x7fc00
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff
+#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff
+#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff
+#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
+#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY_MASK 0x1
+#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY__SHIFT 0x0
+#define CB_DEBUG_BUS_13__MU_BUSY_MASK 0x2
+#define CB_DEBUG_BUS_13__MU_BUSY__SHIFT 0x1
+#define CB_DEBUG_BUS_13__TQ_BUSY_MASK 0x4
+#define CB_DEBUG_BUS_13__TQ_BUSY__SHIFT 0x2
+#define CB_DEBUG_BUS_13__AC_BUSY_MASK 0x8
+#define CB_DEBUG_BUS_13__AC_BUSY__SHIFT 0x3
+#define CB_DEBUG_BUS_13__CRW_BUSY_MASK 0x10
+#define CB_DEBUG_BUS_13__CRW_BUSY__SHIFT 0x4
+#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY_MASK 0x20
+#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY__SHIFT 0x5
+#define CB_DEBUG_BUS_13__MC_WR_PENDING_MASK 0x40
+#define CB_DEBUG_BUS_13__MC_WR_PENDING__SHIFT 0x6
+#define CB_DEBUG_BUS_13__FC_WR_PENDING_MASK 0x80
+#define CB_DEBUG_BUS_13__FC_WR_PENDING__SHIFT 0x7
+#define CB_DEBUG_BUS_13__FC_RD_PENDING_MASK 0x100
+#define CB_DEBUG_BUS_13__FC_RD_PENDING__SHIFT 0x8
+#define CB_DEBUG_BUS_13__EVICT_PENDING_MASK 0x200
+#define CB_DEBUG_BUS_13__EVICT_PENDING__SHIFT 0x9
+#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER_MASK 0x400
+#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER__SHIFT 0xa
+#define CB_DEBUG_BUS_13__MU_STATE_MASK 0x7f800
+#define CB_DEBUG_BUS_13__MU_STATE__SHIFT 0xb
+#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY_MASK 0x1
+#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY__SHIFT 0x0
+#define CB_DEBUG_BUS_14__FOP_BUSY_MASK 0x2
+#define CB_DEBUG_BUS_14__FOP_BUSY__SHIFT 0x1
+#define CB_DEBUG_BUS_14__LAT_BUSY_MASK 0x4
+#define CB_DEBUG_BUS_14__LAT_BUSY__SHIFT 0x2
+#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY_MASK 0x8
+#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY__SHIFT 0x3
+#define CB_DEBUG_BUS_14__ADDR_BUSY_MASK 0x10
+#define CB_DEBUG_BUS_14__ADDR_BUSY__SHIFT 0x4
+#define CB_DEBUG_BUS_14__MERGE_BUSY_MASK 0x20
+#define CB_DEBUG_BUS_14__MERGE_BUSY__SHIFT 0x5
+#define CB_DEBUG_BUS_14__QUAD_BUSY_MASK 0x40
+#define CB_DEBUG_BUS_14__QUAD_BUSY__SHIFT 0x6
+#define CB_DEBUG_BUS_14__TILE_BUSY_MASK 0x80
+#define CB_DEBUG_BUS_14__TILE_BUSY__SHIFT 0x7
+#define CB_DEBUG_BUS_14__CLEAR_BUSY_MASK 0x100
+#define CB_DEBUG_BUS_14__CLEAR_BUSY__SHIFT 0x8
+#define CB_DEBUG_BUS_15__SURF_SYNC_STATE_MASK 0x3
+#define CB_DEBUG_BUS_15__SURF_SYNC_STATE__SHIFT 0x0
+#define CB_DEBUG_BUS_15__SURF_SYNC_START_MASK 0x4
+#define CB_DEBUG_BUS_15__SURF_SYNC_START__SHIFT 0x2
+#define CB_DEBUG_BUS_15__SF_BUSY_MASK 0x8
+#define CB_DEBUG_BUS_15__SF_BUSY__SHIFT 0x3
+#define CB_DEBUG_BUS_15__CS_BUSY_MASK 0x10
+#define CB_DEBUG_BUS_15__CS_BUSY__SHIFT 0x4
+#define CB_DEBUG_BUS_15__RB_BUSY_MASK 0x20
+#define CB_DEBUG_BUS_15__RB_BUSY__SHIFT 0x5
+#define CB_DEBUG_BUS_15__DS_BUSY_MASK 0x40
+#define CB_DEBUG_BUS_15__DS_BUSY__SHIFT 0x6
+#define CB_DEBUG_BUS_15__TB_BUSY_MASK 0x80
+#define CB_DEBUG_BUS_15__TB_BUSY__SHIFT 0x7
+#define CB_DEBUG_BUS_15__IB_BUSY_MASK 0x100
+#define CB_DEBUG_BUS_15__IB_BUSY__SHIFT 0x8
+#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS_MASK 0x3f
+#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS__SHIFT 0x0
+#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC_MASK 0x3c0
+#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC__SHIFT 0x6
+#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS_MASK 0xfc00
+#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS__SHIFT 0xa
+#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC_MASK 0xf0000
+#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC__SHIFT 0x10
+#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY_MASK 0x100000
+#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY__SHIFT 0x14
+#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY_MASK 0x200000
+#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY__SHIFT 0x15
+#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY_MASK 0x400000
+#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY__SHIFT 0x16
+#define CB_DEBUG_BUS_17__CM_BUSY_MASK 0x1
+#define CB_DEBUG_BUS_17__CM_BUSY__SHIFT 0x0
+#define CB_DEBUG_BUS_17__FC_BUSY_MASK 0x2
+#define CB_DEBUG_BUS_17__FC_BUSY__SHIFT 0x1
+#define CB_DEBUG_BUS_17__CC_BUSY_MASK 0x4
+#define CB_DEBUG_BUS_17__CC_BUSY__SHIFT 0x2
+#define CB_DEBUG_BUS_17__BB_BUSY_MASK 0x8
+#define CB_DEBUG_BUS_17__BB_BUSY__SHIFT 0x3
+#define CB_DEBUG_BUS_17__MA_BUSY_MASK 0x10
+#define CB_DEBUG_BUS_17__MA_BUSY__SHIFT 0x4
+#define CB_DEBUG_BUS_17__CORE_SCLK_VLD_MASK 0x20
+#define CB_DEBUG_BUS_17__CORE_SCLK_VLD__SHIFT 0x5
+#define CB_DEBUG_BUS_17__REG_SCLK1_VLD_MASK 0x40
+#define CB_DEBUG_BUS_17__REG_SCLK1_VLD__SHIFT 0x6
+#define CB_DEBUG_BUS_17__REG_SCLK0_VLD_MASK 0x80
+#define CB_DEBUG_BUS_17__REG_SCLK0_VLD__SHIFT 0x7
+#define CB_DEBUG_BUS_18__NOT_USED_MASK 0xffffff
+#define CB_DEBUG_BUS_18__NOT_USED__SHIFT 0x0
+#define CP_DFY_CNTL__POLICY_MASK 0x300
+#define CP_DFY_CNTL__POLICY__SHIFT 0x8
+#define CP_DFY_CNTL__VOL_MASK 0x400
+#define CP_DFY_CNTL__VOL__SHIFT 0xa
+#define CP_DFY_CNTL__ATC_MASK 0x800
+#define CP_DFY_CNTL__ATC__SHIFT 0xb
+#define CP_DFY_STAT__BURST_COUNT_MASK 0xffff
+#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0
+#define CP_DFY_STAT__TAGS_PENDING_MASK 0xff0000
+#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10
+#define CP_DFY_STAT__BUSY_MASK 0x80000000
+#define CP_DFY_STAT__BUSY__SHIFT 0x1f
+#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xffffffff
+#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xffffffe0
+#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5
+#define CP_DFY_DATA_0__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_0__DATA__SHIFT 0x0
+#define CP_DFY_DATA_1__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_1__DATA__SHIFT 0x0
+#define CP_DFY_DATA_2__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_2__DATA__SHIFT 0x0
+#define CP_DFY_DATA_3__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_3__DATA__SHIFT 0x0
+#define CP_DFY_DATA_4__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_4__DATA__SHIFT 0x0
+#define CP_DFY_DATA_5__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_5__DATA__SHIFT 0x0
+#define CP_DFY_DATA_6__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_6__DATA__SHIFT 0x0
+#define CP_DFY_DATA_7__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_7__DATA__SHIFT 0x0
+#define CP_DFY_DATA_8__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_8__DATA__SHIFT 0x0
+#define CP_DFY_DATA_9__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_9__DATA__SHIFT 0x0
+#define CP_DFY_DATA_10__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_10__DATA__SHIFT 0x0
+#define CP_DFY_DATA_11__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_11__DATA__SHIFT 0x0
+#define CP_DFY_DATA_12__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_12__DATA__SHIFT 0x0
+#define CP_DFY_DATA_13__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_13__DATA__SHIFT 0x0
+#define CP_DFY_DATA_14__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_14__DATA__SHIFT 0x0
+#define CP_DFY_DATA_15__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_15__DATA__SHIFT 0x0
+#define CP_RB0_BASE__RB_BASE_MASK 0xffffffff
+#define CP_RB0_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0xff
+#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0
+#define CP_RB_BASE__RB_BASE_MASK 0xffffffff
+#define CP_RB_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB1_BASE__RB_BASE_MASK 0xffffffff
+#define CP_RB1_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0xff
+#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0
+#define CP_RB2_BASE__RB_BASE_MASK 0xffffffff
+#define CP_RB2_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x3f
+#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x3f00
+#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB0_CNTL__BUF_SWAP_MASK 0x30000
+#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x10
+#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x300000
+#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
+#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x3000000
+#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB0_CNTL__RB_VOLATILE_MASK 0x4000000
+#define CP_RB0_CNTL__RB_VOLATILE__SHIFT 0x1a
+#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x8000000
+#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
+#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB_CNTL__RB_BUFSZ_MASK 0x3f
+#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB_CNTL__RB_BLKSZ_MASK 0x3f00
+#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB_CNTL__BUF_SWAP_MASK 0x30000
+#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x10
+#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x300000
+#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
+#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB_CNTL__CACHE_POLICY_MASK 0x3000000
+#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB_CNTL__RB_VOLATILE_MASK 0x4000000
+#define CP_RB_CNTL__RB_VOLATILE__SHIFT 0x1a
+#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x8000000
+#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
+#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x3f
+#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x3f00
+#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x300000
+#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
+#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x3000000
+#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB1_CNTL__RB_VOLATILE_MASK 0x4000000
+#define CP_RB1_CNTL__RB_VOLATILE__SHIFT 0x1a
+#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x8000000
+#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
+#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x3f
+#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x3f00
+#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x300000
+#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
+#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x3000000
+#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB2_CNTL__RB_VOLATILE_MASK 0x4000000
+#define CP_RB2_CNTL__RB_VOLATILE__SHIFT 0x1a
+#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x8000000
+#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
+#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0xfffff
+#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0
+#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
+#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
+#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
+#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
+#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
+#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
+#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
+#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
+#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
+#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
+#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
+#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
+#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
+#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB0_WPTR__RB_WPTR_MASK 0xfffff
+#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB_WPTR__RB_WPTR_MASK 0xfffff
+#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB1_WPTR__RB_WPTR_MASK 0xfffff
+#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB2_WPTR__RB_WPTR_MASK 0xfffff
+#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE_MASK 0xfffffffc
+#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE__SHIFT 0x2
+#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE_MASK 0xff
+#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE__SHIFT 0x0
+#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x80000
+#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
+#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000
+#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000
+#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
+#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000
+#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x80000
+#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
+#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000
+#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x80000
+#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
+#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x400000
+#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x4000
+#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
+#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x80000
+#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x100000
+#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x400000
+#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000
+#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x1000000
+#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x4000000
+#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000
+#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000
+#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000
+#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x4000
+#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
+#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT_MASK 0x80000
+#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x100000
+#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x400000
+#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x800000
+#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x1000000
+#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x4000000
+#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
+#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000
+#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000
+#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000
+#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x4000
+#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
+#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x80000
+#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x100000
+#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x400000
+#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x800000
+#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x1000000
+#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x4000000
+#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
+#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000
+#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000
+#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000
+#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x4000
+#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
+#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x80000
+#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x100000
+#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x400000
+#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x800000
+#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x1000000
+#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x4000000
+#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
+#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000
+#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000
+#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000
+#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_DEVICE_ID__DEVICE_ID_MASK 0xff
+#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
+#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
+#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
+#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
+#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_RING0_PRIORITY__PRIORITY_MASK 0x3
+#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_RING1_PRIORITY__PRIORITY_MASK 0x3
+#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_RING2_PRIORITY__PRIORITY_MASK 0x3
+#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x3
+#define CP_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0
+#define CP_RB_VMID__RB0_VMID_MASK 0xf
+#define CP_RB_VMID__RB0_VMID__SHIFT 0x0
+#define CP_RB_VMID__RB1_VMID_MASK 0xf00
+#define CP_RB_VMID__RB1_VMID__SHIFT 0x8
+#define CP_RB_VMID__RB2_VMID_MASK 0xf0000
+#define CP_RB_VMID__RB2_VMID__SHIFT 0x10
+#define CP_ME0_PIPE0_VMID__VMID_MASK 0xf
+#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0
+#define CP_ME0_PIPE1_VMID__VMID_MASK 0xf
+#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
+#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0xfff
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0xfff
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0
+#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffff
+#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0
+#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
+#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
+#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff
+#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
+#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff
+#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
+#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
+#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
+#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
+#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
+#define CP_PWR_CNTL__GFX_CLK_HALT_MASK 0x1
+#define CP_PWR_CNTL__GFX_CLK_HALT__SHIFT 0x0
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0
+#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x2
+#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1
+#define CP_MEM_SLP_CNTL__RESERVED_MASK 0xfc
+#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0xff00
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0xff0000
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10
+#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
+#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
+#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x3
+#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0
+#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT_MASK 0xf0
+#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT__SHIFT 0x4
+#define CP_ECC_FIRSTOCCURRENCE__RING_ID_MASK 0x3c00
+#define CP_ECC_FIRSTOCCURRENCE__RING_ID__SHIFT 0xa
+#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0xf0000
+#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10
+#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE_MASK 0x3
+#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE__SHIFT 0x0
+#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT_MASK 0xf0
+#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT__SHIFT 0x4
+#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID_MASK 0x3c00
+#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID__SHIFT 0xa
+#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID_MASK 0xf0000
+#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID__SHIFT 0x10
+#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE_MASK 0x3
+#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE__SHIFT 0x0
+#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT_MASK 0xf0
+#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT__SHIFT 0x4
+#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID_MASK 0x3c00
+#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID__SHIFT 0xa
+#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID_MASK 0xf0000
+#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID__SHIFT 0x10
+#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE_MASK 0x3
+#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE__SHIFT 0x0
+#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT_MASK 0xf0
+#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT__SHIFT 0x4
+#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID_MASK 0x3c00
+#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID__SHIFT 0xa
+#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID_MASK 0xf0000
+#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID__SHIFT 0x10
+#define CP_FETCHER_SOURCE__ME_SRC_MASK 0x1
+#define CP_FETCHER_SOURCE__ME_SRC__SHIFT 0x0
+#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0xff
+#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0
+#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000
+#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e
+#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000
+#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f
+#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xffffffff
+#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0
+#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
+#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
+#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
+#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
+#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
+#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
+#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
+#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
+#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
+#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
+#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
+#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
+#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
+#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
+#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
+#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
+#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
+#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
+#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
+#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
+#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
+#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
+#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
+#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
+#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
+#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
+#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
+#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
+#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
+#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
+#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
+#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
+#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
+#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
+#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
+#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
+#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
+#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
+#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
+#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x7ff
+#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x7ff
+#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x7ff
+#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0xfff
+#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0xfff
+#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x7ff
+#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x7ff
+#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x7ff
+#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0xfff
+#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0xfff
+#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x7
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x70
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x70000
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x700000
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14
+#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x7
+#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0
+#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0xff
+#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0
+#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0xff00
+#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8
+#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0xff0000
+#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10
+#define CP_IQ_WAIT_TIME1__GWS_MASK 0xff000000
+#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18
+#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0xff
+#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0
+#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0xff00
+#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8
+#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0xff0000
+#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10
+#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xff000000
+#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18
+#define CP_VMID_RESET__RESET_REQUEST_MASK 0xffff
+#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0
+#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000
+#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x10
+#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0xffff
+#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0
+#define CP_VMID_PREEMPT__PREEMPT_STATUS_MASK 0xffff0000
+#define CP_VMID_PREEMPT__PREEMPT_STATUS__SHIFT 0x10
+#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xffff
+#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0
+#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x1
+#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0
+#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x2
+#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1
+#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x1
+#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
+#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x2
+#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
+#define CP_CPC_STATUS__DC0_BUSY_MASK 0x4
+#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
+#define CP_CPC_STATUS__DC1_BUSY_MASK 0x8
+#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
+#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x10
+#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
+#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x20
+#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
+#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x40
+#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
+#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x80
+#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
+#define CP_CPC_STATUS__MIU_RDREQ_BUSY_MASK 0x100
+#define CP_CPC_STATUS__MIU_RDREQ_BUSY__SHIFT 0x8
+#define CP_CPC_STATUS__MIU_WRREQ_BUSY_MASK 0x200
+#define CP_CPC_STATUS__MIU_WRREQ_BUSY__SHIFT 0x9
+#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x400
+#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
+#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x800
+#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
+#define CP_CPC_STATUS__QU_BUSY_MASK 0x1000
+#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
+#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000
+#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
+#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000
+#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
+#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000
+#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
+#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x1
+#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
+#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x2
+#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
+#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x4
+#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
+#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x8
+#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
+#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x10
+#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
+#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20
+#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
+#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x40
+#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
+#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x80
+#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
+#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x100
+#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
+#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x200
+#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
+#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400
+#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
+#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800
+#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
+#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x1000
+#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
+#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x2000
+#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
+#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x10000
+#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
+#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x20000
+#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
+#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x40000
+#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
+#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x80000
+#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
+#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x100000
+#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
+#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x200000
+#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
+#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x400000
+#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
+#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x800000
+#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
+#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x1000000
+#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
+#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x2000000
+#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
+#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x4000000
+#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
+#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x8000000
+#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
+#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000
+#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
+#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000
+#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
+#define CP_CPC_STALLED_STAT1__MIU_RDREQ_FREE_STALL_MASK 0x1
+#define CP_CPC_STALLED_STAT1__MIU_RDREQ_FREE_STALL__SHIFT 0x0
+#define CP_CPC_STALLED_STAT1__MIU_WRREQ_FREE_STALL_MASK 0x2
+#define CP_CPC_STALLED_STAT1__MIU_WRREQ_FREE_STALL__SHIFT 0x1
+#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x8
+#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
+#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x10
+#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
+#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x40
+#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
+#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x100
+#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x200
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x400
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_READ_MASK 0x800
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_READ__SHIFT 0xb
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_WR_ACK_MASK 0x1000
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_WR_ACK__SHIFT 0xc
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x2000
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
+#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x10000
+#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x20000
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x40000
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_READ_MASK 0x80000
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_READ__SHIFT 0x13
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_WR_ACK_MASK 0x100000
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_WR_ACK__SHIFT 0x14
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
+#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x1
+#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
+#define CP_CPF_STATUS__CSF_BUSY_MASK 0x2
+#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
+#define CP_CPF_STATUS__MIU_RDREQ_BUSY_MASK 0x4
+#define CP_CPF_STATUS__MIU_RDREQ_BUSY__SHIFT 0x2
+#define CP_CPF_STATUS__MIU_WRREQ_BUSY_MASK 0x8
+#define CP_CPF_STATUS__MIU_WRREQ_BUSY__SHIFT 0x3
+#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x10
+#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
+#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x20
+#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
+#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x40
+#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
+#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x80
+#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
+#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x100
+#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
+#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x200
+#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x400
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x800
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
+#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x1000
+#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
+#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x2000
+#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
+#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x4000
+#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
+#define CP_CPF_STATUS__HQD_BUSY_MASK 0x8000
+#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
+#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000
+#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
+#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000
+#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
+#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
+#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
+#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x2
+#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x4
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x8
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
+#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x10
+#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x20
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x40
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
+#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x80
+#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
+#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x100
+#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
+#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x200
+#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9
+#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x800
+#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
+#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x1000
+#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
+#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x2000
+#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
+#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x4000
+#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
+#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x8000
+#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
+#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x10000
+#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
+#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x20000
+#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
+#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x40000
+#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
+#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x80000
+#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
+#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x100000
+#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
+#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x200000
+#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
+#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x400000
+#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
+#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x800000
+#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
+#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x1000000
+#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
+#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x2000000
+#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x4000000
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
+#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x8000000
+#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
+#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000
+#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
+#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000
+#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
+#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000
+#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
+#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x1
+#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
+#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x2
+#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
+#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x4
+#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
+#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x8
+#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
+#define CP_CPF_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK 0x10
+#define CP_CPF_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT 0x4
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x20
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x40
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
+#define CP_CPC_MC_CNTL__PACK_DELAY_CNT_MASK 0x1f
+#define CP_CPC_MC_CNTL__PACK_DELAY_CNT__SHIFT 0x0
+#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
+#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
+#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x10
+#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4
+#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000
+#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
+#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000
+#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
+#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000
+#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
+#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000
+#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
+#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
+#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
+#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
+#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
+#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff
+#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
+#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
+#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
+#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
+#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
+#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
+#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
+#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
+#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
+#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
+#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
+#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
+#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
+#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
+#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
+#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
+#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
+#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
+#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0xf
+#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
+#define CP_DRAW_OBJECT__OBJECT_MASK 0xffffffff
+#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0
+#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0xffff
+#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0
+#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xffffffff
+#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0
+#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xffffffff
+#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0
+#define CP_DRAW_WINDOW_LO__MIN_MASK 0xffff
+#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0
+#define CP_DRAW_WINDOW_LO__MAX_MASK 0xffff0000
+#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x1
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x2
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x4
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2
+#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x100
+#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8
+#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xffffffff
+#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0
+#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xffffffff
+#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0
+#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x3
+#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0
+#define CP_PRT_LOD_STATS_CNTL2__INTERVAL_MASK 0x3fc
+#define CP_PRT_LOD_STATS_CNTL2__INTERVAL__SHIFT 0x2
+#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT_MASK 0x3fc00
+#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT__SHIFT 0xa
+#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE_MASK 0x40000
+#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE__SHIFT 0x12
+#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET_MASK 0x80000
+#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET__SHIFT 0x13
+#define CP_PRT_LOD_STATS_CNTL2__MC_ENDIAN_SWAP_MASK 0x300000
+#define CP_PRT_LOD_STATS_CNTL2__MC_ENDIAN_SWAP__SHIFT 0x14
+#define CP_PRT_LOD_STATS_CNTL2__MC_VMID_MASK 0x7800000
+#define CP_PRT_LOD_STATS_CNTL2__MC_VMID__SHIFT 0x17
+#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xffffffff
+#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
+#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
+#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
+#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xffffffff
+#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
+#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xffffffff
+#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
+#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
+#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
+#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x7f
+#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0
+#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x3f000
+#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc
+#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK 0x6000000
+#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL__SHIFT 0x19
+#define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE_MASK 0x8000000
+#define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE__SHIFT 0x1b
+#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0xffff
+#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x0
+#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x30000
+#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10
+#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x7000000
+#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18
+#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000
+#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d
+#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP_MASK 0x3
+#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP__SHIFT 0x0
+#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffc
+#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2
+#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0xffff
+#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffff
+#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0
+#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffff
+#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0
+#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffff
+#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0
+#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffff
+#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0
+#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP_MASK 0x3
+#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP__SHIFT 0x0
+#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffc
+#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2
+#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffff
+#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0
+#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP_MASK 0x3
+#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP__SHIFT 0x0
+#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffc
+#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2
+#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffff
+#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0
+#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0
+#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0
+#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0
+#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0
+#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0
+#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0
+#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffff
+#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0
+#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffff
+#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0
+#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffff
+#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0
+#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffff
+#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffff
+#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffff
+#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffff
+#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffff
+#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0
+#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x1
+#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0
+#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
+#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
+#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
+#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
+#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
+#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
+#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
+#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
+#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
+#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
+#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
+#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
+#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
+#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
+#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
+#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
+#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0xff
+#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0
+#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x30000
+#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10
+#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffff
+#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0
+#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
+#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
+#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
+#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
+#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
+#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
+#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
+#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffc
+#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2
+#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0xffff
+#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0
+#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x10000
+#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10
+#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000
+#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d
+#define CP_APPEND_DATA__DATA_MASK 0xffffffff
+#define CP_APPEND_DATA__DATA__SHIFT 0x0
+#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffff
+#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0
+#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffff
+#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0
+#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
+#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
+#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
+#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
+#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
+#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
+#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
+#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
+#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
+#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
+#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
+#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
+#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
+#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
+#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
+#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
+#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x3
+#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x0
+#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffc
+#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2
+#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0xffff
+#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0
+#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffff
+#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0
+#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffff
+#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0
+#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x3
+#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x0
+#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffc
+#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2
+#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0xffff
+#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0
+#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffff
+#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
+#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
+#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
+#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
+#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
+#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
+#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
+#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
+#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
+#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
+#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
+#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
+#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
+#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
+#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
+#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
+#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
+#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
+#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
+#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
+#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
+#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffff
+#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0
+#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x3f
+#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0
+#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x1
+#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0
+#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x2
+#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1
+#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x40
+#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6
+#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x80
+#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7
+#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x100
+#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8
+#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x200
+#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9
+#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x400
+#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
+#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x800
+#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb
+#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x1000
+#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc
+#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x2000
+#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd
+#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x4000
+#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe
+#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x8000
+#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf
+#define CP_COHER_CNTL__TC_VOL_ACTION_ENA_MASK 0x10000
+#define CP_COHER_CNTL__TC_VOL_ACTION_ENA__SHIFT 0x10
+#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x40000
+#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12
+#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x80000
+#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13
+#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x200000
+#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15
+#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x400000
+#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16
+#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x800000
+#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17
+#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x2000000
+#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19
+#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x4000000
+#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a
+#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x8000000
+#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b
+#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000
+#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c
+#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000
+#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d
+#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffff
+#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
+#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0xff
+#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
+#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffff
+#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
+#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0xff
+#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
+#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0xff
+#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0
+#define CP_COHER_STATUS__MEID_MASK 0x3000000
+#define CP_COHER_STATUS__MEID__SHIFT 0x18
+#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000
+#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x1e
+#define CP_COHER_STATUS__STATUS_MASK 0x80000000
+#define CP_COHER_STATUS__STATUS__SHIFT 0x1f
+#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0
+#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
+#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0
+#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
+#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
+#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffff
+#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0
+#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
+#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
+#define CP_DMA_ME_CONTROL__SRC_ATC_MASK 0x1000
+#define CP_DMA_ME_CONTROL__SRC_ATC__SHIFT 0xc
+#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x6000
+#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
+#define CP_DMA_ME_CONTROL__SRC_VOLATILE_MASK 0x8000
+#define CP_DMA_ME_CONTROL__SRC_VOLATILE__SHIFT 0xf
+#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x300000
+#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14
+#define CP_DMA_ME_CONTROL__DST_ATC_MASK 0x1000000
+#define CP_DMA_ME_CONTROL__DST_ATC__SHIFT 0x18
+#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x6000000
+#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
+#define CP_DMA_ME_CONTROL__DST_VOLATILE_MASK 0x8000000
+#define CP_DMA_ME_CONTROL__DST_VOLATILE__SHIFT 0x1b
+#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000
+#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d
+#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x1fffff
+#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0
+#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x200000
+#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x15
+#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0xc00000
+#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x16
+#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x3000000
+#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x18
+#define CP_DMA_ME_COMMAND__SAS_MASK 0x4000000
+#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a
+#define CP_DMA_ME_COMMAND__DAS_MASK 0x8000000
+#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b
+#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000
+#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c
+#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000
+#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d
+#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000
+#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e
+#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
+#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0
+#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
+#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
+#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffff
+#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0
+#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
+#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
+#define CP_DMA_PFP_CONTROL__SRC_ATC_MASK 0x1000
+#define CP_DMA_PFP_CONTROL__SRC_ATC__SHIFT 0xc
+#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x6000
+#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
+#define CP_DMA_PFP_CONTROL__SRC_VOLATILE_MASK 0x8000
+#define CP_DMA_PFP_CONTROL__SRC_VOLATILE__SHIFT 0xf
+#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x300000
+#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14
+#define CP_DMA_PFP_CONTROL__DST_ATC_MASK 0x1000000
+#define CP_DMA_PFP_CONTROL__DST_ATC__SHIFT 0x18
+#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x6000000
+#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
+#define CP_DMA_PFP_CONTROL__DST_VOLATILE_MASK 0x8000000
+#define CP_DMA_PFP_CONTROL__DST_VOLATILE__SHIFT 0x1b
+#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000
+#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d
+#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x1fffff
+#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0
+#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x200000
+#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x15
+#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0xc00000
+#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x16
+#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x3000000
+#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x18
+#define CP_DMA_PFP_COMMAND__SAS_MASK 0x4000000
+#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a
+#define CP_DMA_PFP_COMMAND__DAS_MASK 0x8000000
+#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b
+#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000
+#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c
+#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000
+#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d
+#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000
+#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e
+#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x30
+#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4
+#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0xf0000
+#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10
+#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000
+#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c
+#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000
+#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d
+#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000
+#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e
+#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x3ffffff
+#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0
+#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000
+#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c
+#define CP_PFP_IB_CONTROL__IB_EN_MASK 0xff
+#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0
+#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x1
+#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0
+#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x2
+#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1
+#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK 0x8000
+#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT 0xf
+#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x10000
+#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10
+#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x1000000
+#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18
+#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff
+#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
+#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
+#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
+#define CP_RB_OFFSET__RB_OFFSET_MASK 0xfffff
+#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0
+#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
+#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
+#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
+#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
+#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0xfffff
+#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0
+#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0xfffff
+#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0
+#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0xfffff
+#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0
+#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0xfffff
+#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0
+#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
+#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
+#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
+#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
+#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xffffffff
+#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0
+#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x1
+#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
+#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x4
+#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
+#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x10
+#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x400
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x800
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
+#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x1000
+#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
+#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x2000
+#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
+#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA_MASK 0x4000
+#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA__SHIFT 0xe
+#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x8000
+#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
+#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK 0x10000
+#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT 0x10
+#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE_MASK 0x20000
+#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE__SHIFT 0x11
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x800000
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x1000000
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x2000000
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x4000000
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x8000000
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
+#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000
+#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
+#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
+#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
+#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x2
+#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
+#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x4
+#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
+#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x10
+#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
+#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x20
+#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
+#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING_MASK 0x40
+#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING__SHIFT 0x6
+#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x80
+#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x7
+#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x100
+#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
+#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x200
+#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
+#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x400
+#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
+#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x800
+#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
+#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x1000
+#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
+#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x2000
+#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x4000
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
+#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x8000
+#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
+#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x10000
+#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
+#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x20000
+#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x40000
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
+#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x80000
+#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
+#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x100000
+#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x200000
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x400000
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
+#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x800000
+#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
+#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x1000000
+#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x2000000
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x4000000
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
+#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x8000000
+#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
+#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000
+#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
+#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000
+#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
+#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
+#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x2
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
+#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x4
+#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x8
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
+#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x10
+#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
+#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x20
+#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
+#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x40
+#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
+#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x80
+#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
+#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x100
+#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x8
+#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x400
+#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
+#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x800
+#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x1000
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x2000
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x4000
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x8000
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
+#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
+#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
+#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x40
+#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6
+#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x80
+#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7
+#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x100
+#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8
+#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x200
+#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9
+#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x400
+#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
+#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x1000
+#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc
+#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x2000
+#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd
+#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x4000
+#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
+#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x8000
+#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf
+#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x20000
+#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11
+#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x40000
+#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12
+#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x80000
+#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13
+#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x100000
+#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
+#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x200000
+#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15
+#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x400000
+#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16
+#define CP_STAT__MIU_RDREQ_BUSY_MASK 0x80
+#define CP_STAT__MIU_RDREQ_BUSY__SHIFT 0x7
+#define CP_STAT__MIU_WRREQ_BUSY_MASK 0x100
+#define CP_STAT__MIU_WRREQ_BUSY__SHIFT 0x8
+#define CP_STAT__ROQ_RING_BUSY_MASK 0x200
+#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9
+#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x400
+#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
+#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x800
+#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb
+#define CP_STAT__ROQ_STATE_BUSY_MASK 0x1000
+#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc
+#define CP_STAT__DC_BUSY_MASK 0x2000
+#define CP_STAT__DC_BUSY__SHIFT 0xd
+#define CP_STAT__PFP_BUSY_MASK 0x8000
+#define CP_STAT__PFP_BUSY__SHIFT 0xf
+#define CP_STAT__MEQ_BUSY_MASK 0x10000
+#define CP_STAT__MEQ_BUSY__SHIFT 0x10
+#define CP_STAT__ME_BUSY_MASK 0x20000
+#define CP_STAT__ME_BUSY__SHIFT 0x11
+#define CP_STAT__QUERY_BUSY_MASK 0x40000
+#define CP_STAT__QUERY_BUSY__SHIFT 0x12
+#define CP_STAT__SEMAPHORE_BUSY_MASK 0x80000
+#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13
+#define CP_STAT__INTERRUPT_BUSY_MASK 0x100000
+#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
+#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x200000
+#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15
+#define CP_STAT__DMA_BUSY_MASK 0x400000
+#define CP_STAT__DMA_BUSY__SHIFT 0x16
+#define CP_STAT__RCIU_BUSY_MASK 0x800000
+#define CP_STAT__RCIU_BUSY__SHIFT 0x17
+#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x1000000
+#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18
+#define CP_STAT__CPC_CPG_BUSY_MASK 0x2000000
+#define CP_STAT__CPC_CPG_BUSY__SHIFT 0x19
+#define CP_STAT__CE_BUSY_MASK 0x4000000
+#define CP_STAT__CE_BUSY__SHIFT 0x1a
+#define CP_STAT__TCIU_BUSY_MASK 0x8000000
+#define CP_STAT__TCIU_BUSY__SHIFT 0x1b
+#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000
+#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c
+#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000
+#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d
+#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000
+#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e
+#define CP_STAT__CP_BUSY_MASK 0x80000000
+#define CP_STAT__CP_BUSY__SHIFT 0x1f
+#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffff
+#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0
+#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffff
+#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
+#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x3f00
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x3f0000
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10
+#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffff
+#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0
+#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT_MASK 0x1f
+#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT__SHIFT 0x0
+#define CP_MC_TAG_CNTL__TAG_RAM_INDEX_MASK 0x3f
+#define CP_MC_TAG_CNTL__TAG_RAM_INDEX__SHIFT 0x0
+#define CP_MC_TAG_CNTL__TAG_RAM_SEL_MASK 0x30000
+#define CP_MC_TAG_CNTL__TAG_RAM_SEL__SHIFT 0x10
+#define CP_MC_TAG_DATA__TAG_RAM_DATA_MASK 0xffffffff
+#define CP_MC_TAG_DATA__TAG_RAM_DATA__SHIFT 0x0
+#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0xf
+#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x0
+#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x3f00
+#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8
+#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0xf
+#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x0
+#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x10
+#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4
+#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x40
+#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6
+#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x100
+#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8
+#define CP_ME_CNTL__CE_HALT_MASK 0x1000000
+#define CP_ME_CNTL__CE_HALT__SHIFT 0x18
+#define CP_ME_CNTL__CE_STEP_MASK 0x2000000
+#define CP_ME_CNTL__CE_STEP__SHIFT 0x19
+#define CP_ME_CNTL__PFP_HALT_MASK 0x4000000
+#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a
+#define CP_ME_CNTL__PFP_STEP_MASK 0x8000000
+#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b
+#define CP_ME_CNTL__ME_HALT_MASK 0x10000000
+#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c
+#define CP_ME_CNTL__ME_STEP_MASK 0x20000000
+#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d
+#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0xff
+#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0
+#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x700
+#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8
+#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0xff00000
+#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
+#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000
+#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c
+#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION_MASK 0x1
+#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION__SHIFT 0x0
+#define CP_RB0_RPTR__RB_RPTR_MASK 0xfffff
+#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB_RPTR__RB_RPTR_MASK 0xfffff
+#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB1_RPTR__RB_RPTR_MASK 0xfffff
+#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB2_RPTR__RB_RPTR_MASK 0xfffff
+#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0xfffffff
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c
+#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0xffff
+#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0
+#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0
+#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5
+#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0xffff
+#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0
+#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0xfff
+#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0
+#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
+#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
+#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
+#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
+#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
+#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
+#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
+#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
+#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
+#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
+#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
+#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
+#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
+#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
+#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
+#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
+#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
+#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
+#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
+#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
+#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
+#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
+#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
+#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
+#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffc
+#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2
+#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0xffff
+#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0
+#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0xfffff
+#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0
+#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0xff
+#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0
+#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0xff00
+#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8
+#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0xff
+#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0
+#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0xff
+#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0
+#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0xff00
+#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8
+#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0xff0000
+#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10
+#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000
+#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18
+#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0xff
+#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0
+#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0xff00
+#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8
+#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0xff0000
+#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10
+#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000
+#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18
+#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0xff
+#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0
+#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0xff00
+#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8
+#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0xff0000
+#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10
+#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x3f
+#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0
+#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x3f00
+#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8
+#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0xff
+#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0
+#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0xff00
+#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8
+#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x7ff
+#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0
+#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x7ff0000
+#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
+#define CP_STQ_AVAIL__STQ_CNT_MASK 0x1ff
+#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0
+#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x7ff
+#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0
+#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x3ff
+#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0
+#define CP_CMD_INDEX__CMD_INDEX_MASK 0x7ff
+#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0
+#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x3000
+#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc
+#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x30000
+#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10
+#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffff
+#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0
+#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x3ff
+#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0
+#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x3ff0000
+#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10
+#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x3ff
+#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0
+#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x3ff0000
+#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10
+#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x3ff
+#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0
+#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x3ff0000
+#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10
+#define CP_STQ_STAT__STQ_RPTR_MASK 0x3ff
+#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0
+#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x3ff
+#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0
+#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x3ff
+#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0
+#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x3ff0000
+#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10
+#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x7ff
+#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0
+#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x7ff0000
+#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10
+#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x7ff
+#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0
+#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x3ff
+#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
+#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000
+#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
+#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x3ff
+#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0
+#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x3ff0000
+#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
+#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x3ff
+#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0
+#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x3ff0000
+#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10
+#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
+#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
+#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
+#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
+#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x80000
+#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13
+#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x100000
+#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14
+#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x400000
+#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16
+#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
+#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
+#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
+#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
+#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
+#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
+#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
+#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
+#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
+#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
+#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
+#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
+#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
+#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
+#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0xf
+#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0xf0
+#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
+#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
+#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
+#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000
+#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f
+#define CP_RINGID__RINGID_MASK 0x3
+#define CP_RINGID__RINGID__SHIFT 0x0
+#define CP_PIPEID__PIPE_ID_MASK 0x3
+#define CP_PIPEID__PIPE_ID__SHIFT 0x0
+#define CP_VMID__VMID_MASK 0xf
+#define CP_VMID__VMID__SHIFT 0x0
+#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x7
+#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0
+#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x3f00
+#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8
+#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x3f0000
+#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10
+#define CP_HPD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xffffffff
+#define CP_HPD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define CP_HPD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xff
+#define CP_HPD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
+#define CP_HPD_EOP_VMID__VMID_MASK 0xf
+#define CP_HPD_EOP_VMID__VMID__SHIFT 0x0
+#define CP_HPD_EOP_CONTROL__EOP_SIZE_MASK 0x3f
+#define CP_HPD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0
+#define CP_HPD_EOP_CONTROL__PROCESSING_EOP_MASK 0x100
+#define CP_HPD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8
+#define CP_HPD_EOP_CONTROL__PROCESSING_QID_MASK 0xe00
+#define CP_HPD_EOP_CONTROL__PROCESSING_QID__SHIFT 0x9
+#define CP_HPD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x1000
+#define CP_HPD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc
+#define CP_HPD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x2000
+#define CP_HPD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd
+#define CP_HPD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x4000
+#define CP_HPD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe
+#define CP_HPD_EOP_CONTROL__EOP_ATC_MASK 0x800000
+#define CP_HPD_EOP_CONTROL__EOP_ATC__SHIFT 0x17
+#define CP_HPD_EOP_CONTROL__CACHE_POLICY_MASK 0x3000000
+#define CP_HPD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18
+#define CP_HPD_EOP_CONTROL__EOP_VOLATILE_MASK 0x4000000
+#define CP_HPD_EOP_CONTROL__EOP_VOLATILE__SHIFT 0x1a
+#define CP_HPD_EOP_CONTROL__PEND_Q_SEM_MASK 0x70000000
+#define CP_HPD_EOP_CONTROL__PEND_Q_SEM__SHIFT 0x1c
+#define CP_HPD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000
+#define CP_HPD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f
+#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xfffffffc
+#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
+#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xffff
+#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
+#define CP_HQD_ACTIVE__ACTIVE_MASK 0x1
+#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0
+#define CP_HQD_VMID__VMID_MASK 0xf
+#define CP_HQD_VMID__VMID__SHIFT 0x0
+#define CP_HQD_VMID__IB_VMID_MASK 0xf00
+#define CP_HQD_VMID__IB_VMID__SHIFT 0x8
+#define CP_HQD_VMID__VQID_MASK 0x3ff0000
+#define CP_HQD_VMID__VQID__SHIFT 0x10
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x1
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x3ff00
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8
+#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000
+#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f
+#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x3
+#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0
+#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0xf
+#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0
+#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x1
+#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0
+#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x10
+#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4
+#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x3f00
+#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8
+#define CP_HQD_PQ_BASE__ADDR_MASK 0xffffffff
+#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0
+#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0xff
+#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0
+#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xffffffff
+#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0
+#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xfffffffc
+#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2
+#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0xffff
+#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0
+#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xfffffffc
+#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x2
+#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0xffff
+#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
+#define CP_HQD_PQ_WPTR__OFFSET_MASK 0xffffffff
+#define CP_HQD_PQ_WPTR__OFFSET__SHIFT 0x0
+#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f
+#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0
+#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x3f00
+#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8
+#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x30000
+#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x10
+#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x300000
+#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14
+#define CP_HQD_PQ_CONTROL__PQ_ATC_MASK 0x800000
+#define CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT 0x17
+#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x3000000
+#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18
+#define CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK 0x4000000
+#define CP_HQD_PQ_CONTROL__PQ_VOLATILE__SHIFT 0x1a
+#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x8000000
+#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b
+#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000
+#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c
+#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000
+#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d
+#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000
+#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e
+#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000
+#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f
+#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xfffffffc
+#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2
+#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0xffff
+#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0
+#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0xfffff
+#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0
+#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0xfffff
+#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0
+#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x300000
+#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14
+#define CP_HQD_IB_CONTROL__IB_ATC_MASK 0x800000
+#define CP_HQD_IB_CONTROL__IB_ATC__SHIFT 0x17
+#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x3000000
+#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18
+#define CP_HQD_IB_CONTROL__IB_VOLATILE_MASK 0x4000000
+#define CP_HQD_IB_CONTROL__IB_VOLATILE__SHIFT 0x1a
+#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000
+#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f
+#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0xff
+#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0
+#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x700
+#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8
+#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x3000
+#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc
+#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x3f0000
+#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10
+#define CP_HQD_IQ_TIMER__IQ_ATC_MASK 0x800000
+#define CP_HQD_IQ_TIMER__IQ_ATC__SHIFT 0x17
+#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x3000000
+#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18
+#define CP_HQD_IQ_TIMER__IQ_VOLATILE_MASK 0x4000000
+#define CP_HQD_IQ_TIMER__IQ_VOLATILE__SHIFT 0x1a
+#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000
+#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d
+#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000
+#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e
+#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000
+#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f
+#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x3f
+#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x3
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0
+#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x10
+#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x100
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8
+#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x1
+#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
+#define CP_HQD_SEMA_CMD__RETRY_MASK 0x1
+#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0
+#define CP_HQD_SEMA_CMD__RESULT_MASK 0x6
+#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1
+#define CP_HQD_MSG_TYPE__ACTION_MASK 0x3
+#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0
+#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xffffffff
+#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xffffffff
+#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xffffffff
+#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xffffffff
+#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_STATUS_MASK 0x3
+#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_STATUS__SHIFT 0x0
+#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_RETRY_CNT_MASK 0xc
+#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_RETRY_CNT__SHIFT 0x2
+#define CP_HQD_HQ_SCHEDULER0__RSV_5_4_MASK 0x30
+#define CP_HQD_HQ_SCHEDULER0__RSV_5_4__SHIFT 0x4
+#define CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE_MASK 0x40
+#define CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE__SHIFT 0x6
+#define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT_MASK 0x80
+#define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT__SHIFT 0x7
+#define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY_MASK 0x100
+#define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY__SHIFT 0x8
+#define CP_HQD_HQ_SCHEDULER0__PG_ACTIVATED_MASK 0x200
+#define CP_HQD_HQ_SCHEDULER0__PG_ACTIVATED__SHIFT 0x9
+#define CP_HQD_HQ_SCHEDULER0__CG_ACTIVATED_MASK 0x400
+#define CP_HQD_HQ_SCHEDULER0__CG_ACTIVATED__SHIFT 0xa
+#define CP_HQD_HQ_SCHEDULER0__RSVR_31_11_MASK 0xfffff800
+#define CP_HQD_HQ_SCHEDULER0__RSVR_31_11__SHIFT 0xb
+#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xffffffff
+#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0
+#define CP_MQD_CONTROL__VMID_MASK 0xf
+#define CP_MQD_CONTROL__VMID__SHIFT 0x0
+#define CP_MQD_CONTROL__MQD_ATC_MASK 0x800000
+#define CP_MQD_CONTROL__MQD_ATC__SHIFT 0x17
+#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x3000000
+#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
+#define CP_MQD_CONTROL__MQD_VOLATILE_MASK 0x4000000
+#define CP_MQD_CONTROL__MQD_VOLATILE__SHIFT 0x1a
+#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffff
+#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0
+#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffff
+#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0
+#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffff
+#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0
+#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffff
+#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0
+#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0xf
+#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x0
+#define DB_DEPTH_INFO__ARRAY_MODE_MASK 0xf0
+#define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x4
+#define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x1f00
+#define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x8
+#define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x6000
+#define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0xd
+#define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x18000
+#define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0xf
+#define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x60000
+#define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x11
+#define DB_DEPTH_INFO__NUM_BANKS_MASK 0x180000
+#define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x13
+#define DB_Z_INFO__FORMAT_MASK 0x3
+#define DB_Z_INFO__FORMAT__SHIFT 0x0
+#define DB_Z_INFO__NUM_SAMPLES_MASK 0xc
+#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2
+#define DB_Z_INFO__TILE_SPLIT_MASK 0xe000
+#define DB_Z_INFO__TILE_SPLIT__SHIFT 0xd
+#define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x700000
+#define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x14
+#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
+#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
+#define DB_Z_INFO__READ_SIZE_MASK 0x10000000
+#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c
+#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000
+#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d
+#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000
+#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f
+#define DB_STENCIL_INFO__FORMAT_MASK 0x1
+#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0
+#define DB_STENCIL_INFO__TILE_SPLIT_MASK 0xe000
+#define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0xd
+#define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x700000
+#define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x14
+#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
+#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
+#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000
+#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d
+#define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x7ff
+#define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x0
+#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x3ff800
+#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0xb
+#define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x3fffff
+#define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x0
+#define DB_DEPTH_VIEW__SLICE_START_MASK 0x7ff
+#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0
+#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0xffe000
+#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd
+#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x1000000
+#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18
+#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x2000000
+#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19
+#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x1
+#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0
+#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x2
+#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1
+#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x4
+#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2
+#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x8
+#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3
+#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x10
+#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4
+#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x20
+#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5
+#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x40
+#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6
+#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x80
+#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7
+#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0xf00
+#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8
+#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x1
+#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0
+#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x2
+#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1
+#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x70
+#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4
+#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0xf00
+#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8
+#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0xf000
+#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc
+#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000
+#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10
+#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0xf00000
+#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14
+#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0xf000000
+#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18
+#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000
+#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c
+#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x3
+#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0xc
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x30
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4
+#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x40
+#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6
+#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x80
+#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7
+#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x100
+#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8
+#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x200
+#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9
+#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x400
+#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
+#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x800
+#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x1000
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc
+#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x6000
+#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd
+#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x8000
+#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf
+#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x10000
+#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10
+#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x20000
+#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11
+#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x40000
+#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12
+#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x180000
+#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13
+#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x3e00000
+#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15
+#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x4000000
+#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a
+#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x8000000
+#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c
+#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000
+#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e
+#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000
+#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x3
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x1c
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2
+#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x20
+#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5
+#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x40
+#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6
+#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x80
+#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7
+#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x100
+#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8
+#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x200
+#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9
+#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x400
+#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
+#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x800
+#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb
+#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x7000
+#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x38000
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x1c0000
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12
+#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x200000
+#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15
+#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x400000
+#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16
+#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x800000
+#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17
+#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x7
+#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0
+#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x70
+#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4
+#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x700
+#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8
+#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x7000
+#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc
+#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x10000
+#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10
+#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x20000
+#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11
+#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x40000
+#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12
+#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x80000
+#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13
+#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x100000
+#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14
+#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x200000
+#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15
+#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x7000000
+#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18
+#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x8000000
+#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b
+#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x1
+#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0
+#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x2
+#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1
+#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x4
+#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2
+#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x30
+#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4
+#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x40
+#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6
+#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x80
+#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7
+#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x100
+#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8
+#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x200
+#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9
+#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x400
+#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
+#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x800
+#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb
+#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x1000
+#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc
+#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x6000
+#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd
+#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffff
+#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0
+#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffff
+#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0
+#define DB_STENCIL_CLEAR__CLEAR_MASK 0xff
+#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0
+#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffff
+#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0
+#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffff
+#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0
+#define DB_HTILE_SURFACE__LINEAR_MASK 0x1
+#define DB_HTILE_SURFACE__LINEAR__SHIFT 0x0
+#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x2
+#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1
+#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x4
+#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2
+#define DB_HTILE_SURFACE__PRELOAD_MASK 0x8
+#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3
+#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x3f0
+#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4
+#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0xfc00
+#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa
+#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x10000
+#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10
+#define DB_PRELOAD_CONTROL__START_X_MASK 0xff
+#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0
+#define DB_PRELOAD_CONTROL__START_Y_MASK 0xff00
+#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8
+#define DB_PRELOAD_CONTROL__MAX_X_MASK 0xff0000
+#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10
+#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000
+#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18
+#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0xff
+#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0
+#define DB_STENCILREFMASK__STENCILMASK_MASK 0xff00
+#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8
+#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0xff0000
+#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10
+#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000
+#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18
+#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0xff
+#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0
+#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0xff00
+#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8
+#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0xff0000
+#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10
+#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000
+#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x7
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0xff0
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0xff000
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc
+#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x1000000
+#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x7
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0xff0
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0xff000
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc
+#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x1000000
+#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18
+#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x1
+#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0
+#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x2
+#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1
+#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x4
+#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2
+#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x8
+#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3
+#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x70
+#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4
+#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x80
+#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7
+#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x700
+#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8
+#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x700000
+#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14
+#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000
+#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e
+#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000
+#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f
+#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0xf
+#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0
+#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0xf0
+#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4
+#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0xf00
+#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8
+#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0xf000
+#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc
+#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0xf0000
+#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10
+#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0xf00000
+#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x1
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x300
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0xc00
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x3000
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0xc000
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe
+#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x10000
+#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xf000000
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xf000000
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x1
+#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0
+#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x2
+#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1
+#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x4
+#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2
+#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x8
+#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3
+#define DB_DEBUG__FORCE_Z_MODE_MASK 0x30
+#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4
+#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x40
+#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6
+#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x80
+#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7
+#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x300
+#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0xc00
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x3000
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc
+#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x4000
+#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe
+#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x8000
+#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf
+#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x10000
+#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10
+#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x20000
+#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11
+#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x40000
+#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12
+#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x180000
+#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13
+#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x200000
+#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15
+#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x400000
+#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16
+#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x800000
+#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17
+#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0xf000000
+#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18
+#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000
+#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c
+#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000
+#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d
+#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000
+#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e
+#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000
+#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f
+#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x1
+#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0
+#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x2
+#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1
+#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x4
+#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2
+#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x8
+#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3
+#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x10
+#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
+#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x20
+#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x5
+#define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x40
+#define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x6
+#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x80
+#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x7
+#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x100
+#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x8
+#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x3e00
+#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9
+#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x4000
+#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe
+#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x8000
+#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf
+#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x10000
+#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10
+#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x20000
+#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11
+#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x40000
+#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12
+#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x80000
+#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13
+#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000
+#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c
+#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000
+#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d
+#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000
+#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e
+#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000
+#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f
+#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x4
+#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2
+#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x8
+#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3
+#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x10
+#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4
+#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x20
+#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5
+#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x40
+#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6
+#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x80
+#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7
+#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x100
+#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8
+#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x200
+#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9
+#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x400
+#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
+#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x800
+#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb
+#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x1000
+#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc
+#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x2000
+#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd
+#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x4000
+#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe
+#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x8000
+#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf
+#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x10000
+#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10
+#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x20000
+#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11
+#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x40000
+#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12
+#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x80000
+#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13
+#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x100000
+#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14
+#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x200000
+#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15
+#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x400000
+#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16
+#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x800000
+#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17
+#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x1000000
+#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18
+#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x2000000
+#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19
+#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x4000000
+#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a
+#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x8000000
+#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b
+#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000
+#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c
+#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000
+#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d
+#define DB_DEBUG3__DB_EXTRA_DEBUG3_MASK 0xc0000000
+#define DB_DEBUG3__DB_EXTRA_DEBUG3__SHIFT 0x1e
+#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x1
+#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0
+#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x2
+#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1
+#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x4
+#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2
+#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x8
+#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3
+#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xfffffff0
+#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x4
+#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x1f
+#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0
+#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x3e0
+#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5
+#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x1c00
+#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
+#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000
+#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18
+#define DB_WATERMARKS__DEPTH_FREE_MASK 0x1f
+#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0
+#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x7e0
+#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5
+#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x7800
+#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb
+#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0xf8000
+#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf
+#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x7f00000
+#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14
+#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x8000000
+#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x1b
+#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000
+#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x1c
+#define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000
+#define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x1d
+#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000
+#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e
+#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000
+#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f
+#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x3
+#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0
+#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0xc
+#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2
+#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x30
+#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4
+#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0xc0
+#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6
+#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x300
+#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8
+#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0xc00
+#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
+#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x3000
+#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc
+#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0xc000
+#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe
+#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x30000
+#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10
+#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0xc0000
+#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12
+#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x7f
+#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0
+#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x3f80
+#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7
+#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x1fc000
+#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe
+#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x1e00000
+#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x15
+#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000
+#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x19
+#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x1f
+#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0
+#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x3e0
+#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x5
+#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0xfc00
+#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa
+#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x1f0000
+#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10
+#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000
+#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15
+#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0xff
+#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0
+#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x7f00
+#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8
+#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x1ff8000
+#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf
+#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000
+#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19
+#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0xf
+#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0
+#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0xff0
+#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4
+#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0xfff000
+#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x1000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x2000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x4000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x8000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f
+#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffff
+#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffff
+#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0
+#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x3
+#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0
+#define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffff
+#define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x0
+#define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffff
+#define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x0
+#define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffff
+#define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x0
+#define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x0
+#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xffffffff
+#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7fffffff
+#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0
+#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xffffffff
+#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7fffffff
+#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0
+#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xffffffff
+#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7fffffff
+#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0
+#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xffffffff
+#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7fffffff
+#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0
+#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
+#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
+#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
+#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
+#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
+#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
+#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
+#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
+#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
+#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
+#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
+#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
+#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffff
+#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0
+#define GB_GPU_ID__GPU_ID_MASK 0xf
+#define GB_GPU_ID__GPU_ID__SHIFT 0x0
+#define CC_RB_DAISY_CHAIN__RB_0_MASK 0xf
+#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0
+#define CC_RB_DAISY_CHAIN__RB_1_MASK 0xf0
+#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4
+#define CC_RB_DAISY_CHAIN__RB_2_MASK 0xf00
+#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8
+#define CC_RB_DAISY_CHAIN__RB_3_MASK 0xf000
+#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc
+#define CC_RB_DAISY_CHAIN__RB_4_MASK 0xf0000
+#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10
+#define CC_RB_DAISY_CHAIN__RB_5_MASK 0xf00000
+#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14
+#define CC_RB_DAISY_CHAIN__RB_6_MASK 0xf000000
+#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18
+#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000
+#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c
+#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6
+#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x10000
+#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x10
+#define GB_EDC_MODE__DED_MODE_MASK 0x300000
+#define GB_EDC_MODE__DED_MODE__SHIFT 0x14
+#define GB_EDC_MODE__PROP_FED_MASK 0x20000000
+#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d
+#define GB_EDC_MODE__BYPASS_MASK 0x80000000
+#define GB_EDC_MODE__BYPASS__SHIFT 0x1f
+#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x2
+#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x1
+#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0
+#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffff
+#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0
+#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffff
+#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0
+#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffff
+#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0
+#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffff
+#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0
+#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0
+#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffff
+#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0
+#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffff
+#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0
+#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffff
+#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0
+#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x7
+#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
+#define GRBM_CAM_DATA__CAM_ADDR_MASK 0xffff
+#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
+#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
+#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
+#define GRBM_CNTL__READ_TIMEOUT_MASK 0xff
+#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
+#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x3f
+#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
+#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0xfc0
+#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6
+#define GRBM_PWR_CNTL__REQ_TYPE_MASK 0xf
+#define GRBM_PWR_CNTL__REQ_TYPE__SHIFT 0x0
+#define GRBM_PWR_CNTL__RSP_TYPE_MASK 0xf0
+#define GRBM_PWR_CNTL__RSP_TYPE__SHIFT 0x4
+#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0xf
+#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0
+#define GRBM_STATUS__SRBM_RQ_PENDING_MASK 0x20
+#define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT 0x5
+#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x80
+#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7
+#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x100
+#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8
+#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x200
+#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9
+#define GRBM_STATUS__DB_CLEAN_MASK 0x1000
+#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc
+#define GRBM_STATUS__CB_CLEAN_MASK 0x2000
+#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd
+#define GRBM_STATUS__TA_BUSY_MASK 0x4000
+#define GRBM_STATUS__TA_BUSY__SHIFT 0xe
+#define GRBM_STATUS__GDS_BUSY_MASK 0x8000
+#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf
+#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x10000
+#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10
+#define GRBM_STATUS__VGT_BUSY_MASK 0x20000
+#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11
+#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x40000
+#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12
+#define GRBM_STATUS__IA_BUSY_MASK 0x80000
+#define GRBM_STATUS__IA_BUSY__SHIFT 0x13
+#define GRBM_STATUS__SX_BUSY_MASK 0x100000
+#define GRBM_STATUS__SX_BUSY__SHIFT 0x14
+#define GRBM_STATUS__WD_BUSY_MASK 0x200000
+#define GRBM_STATUS__WD_BUSY__SHIFT 0x15
+#define GRBM_STATUS__SPI_BUSY_MASK 0x400000
+#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16
+#define GRBM_STATUS__BCI_BUSY_MASK 0x800000
+#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17
+#define GRBM_STATUS__SC_BUSY_MASK 0x1000000
+#define GRBM_STATUS__SC_BUSY__SHIFT 0x18
+#define GRBM_STATUS__PA_BUSY_MASK 0x2000000
+#define GRBM_STATUS__PA_BUSY__SHIFT 0x19
+#define GRBM_STATUS__DB_BUSY_MASK 0x4000000
+#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a
+#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000
+#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c
+#define GRBM_STATUS__CP_BUSY_MASK 0x20000000
+#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d
+#define GRBM_STATUS__CB_BUSY_MASK 0x40000000
+#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000
+#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f
+#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0xf
+#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
+#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x10
+#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
+#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x20
+#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5
+#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x40
+#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6
+#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x80
+#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7
+#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x100
+#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8
+#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x200
+#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9
+#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x400
+#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
+#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x800
+#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb
+#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x1000
+#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc
+#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x2000
+#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd
+#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x4000
+#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe
+#define GRBM_STATUS2__RLC_BUSY_MASK 0x1000000
+#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18
+#define GRBM_STATUS2__TC_BUSY_MASK 0x2000000
+#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19
+#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000
+#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c
+#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000
+#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000
+#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x2
+#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x4
+#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x400000
+#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x800000
+#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17
+#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x1000000
+#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x2000000
+#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x4000000
+#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x8000000
+#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000
+#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000
+#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000
+#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f
+#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x2
+#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x4
+#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x400000
+#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x800000
+#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17
+#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x1000000
+#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x2000000
+#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x4000000
+#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x8000000
+#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000
+#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000
+#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000
+#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f
+#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x2
+#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x4
+#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x400000
+#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x800000
+#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17
+#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x1000000
+#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x2000000
+#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x4000000
+#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x8000000
+#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000
+#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000
+#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000
+#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f
+#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x2
+#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x4
+#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x400000
+#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x800000
+#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17
+#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x1000000
+#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x2000000
+#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x4000000
+#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x8000000
+#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000
+#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000
+#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000
+#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f
+#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x1
+#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0
+#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x4
+#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2
+#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x10000
+#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10
+#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x20000
+#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11
+#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x40000
+#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12
+#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x80000
+#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13
+#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x3f
+#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x0
+#define GRBM_DEBUG_DATA__DATA_MASK 0xffffffff
+#define GRBM_DEBUG_DATA__DATA__SHIFT 0x0
+#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0xff
+#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0
+#define GRBM_GFX_INDEX__SH_INDEX_MASK 0xff00
+#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8
+#define GRBM_GFX_INDEX__SE_INDEX_MASK 0xff0000
+#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10
+#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000
+#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d
+#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000
+#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
+#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000
+#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f
+#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0xff
+#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0
+#define GRBM_DEBUG__IGNORE_RDY_MASK 0x2
+#define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x1
+#define GRBM_DEBUG__IGNORE_FAO_MASK 0x20
+#define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x5
+#define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x40
+#define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x6
+#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x80
+#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x7
+#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0xf00
+#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x8
+#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x1000
+#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xc
+#define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK 0x1
+#define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT 0x0
+#define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK 0x2
+#define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT 0x1
+#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK 0x4
+#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT 0x2
+#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK 0x8
+#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT 0x3
+#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK 0x10
+#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT 0x4
+#define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK 0x20
+#define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT 0x5
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK 0x40
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT 0x6
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK 0x80
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT 0x7
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK 0x100
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT 0x8
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK 0x200
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT 0x9
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK 0x400
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT 0xa
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK 0x800
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT 0xb
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK 0x1000
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT 0xc
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK 0x2000
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT 0xd
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK 0x4000
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT 0xe
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK 0x8000
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT 0xf
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK 0x10000
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT 0x10
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK 0x20000
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT 0x11
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK 0x40000
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT 0x12
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK 0x80000
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT 0x13
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK 0x100000
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x14
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK 0x200000
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT 0x15
+#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc
+#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
+#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x300000
+#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14
+#define GRBM_READ_ERROR__READ_MEID_MASK 0xc00000
+#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16
+#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000
+#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
+#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK 0x20000
+#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT 0x11
+#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x40000
+#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12
+#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x80000
+#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x100000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x200000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x400000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x800000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x1000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x2000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x4000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x8000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f
+#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x1
+#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0
+#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x80000
+#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13
+#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
+#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
+#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
+#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000
+#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000
+#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000
+#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
+#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000
+#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000
+#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000
+#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000
+#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000
+#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000
+#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000
+#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000
+#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
+#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000
+#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
+#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000
+#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
+#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000
+#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
+#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000
+#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
+#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000
+#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
+#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
+#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
+#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
+#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000
+#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000
+#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000
+#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
+#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000
+#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000
+#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000
+#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000
+#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000
+#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000
+#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000
+#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000
+#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
+#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000
+#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
+#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000
+#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
+#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000
+#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
+#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000
+#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
+#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000
+#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
+#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
+#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
+#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
+#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
+#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
+#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
+#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
+#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
+#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
+#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
+#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
+#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
+#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
+#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
+#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
+#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
+#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
+#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
+#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
+#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
+#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
+#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
+#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
+#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
+#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
+#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
+#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
+#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
+#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
+#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
+#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
+#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
+#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
+#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
+#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
+#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
+#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
+#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
+#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
+#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
+#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
+#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
+#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
+#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
+#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
+#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
+#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
+#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
+#define DEBUG_INDEX__DEBUG_INDEX_MASK 0x3ffff
+#define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x0
+#define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffff
+#define DEBUG_DATA__DEBUG_DATA__SHIFT 0x0
+#define GRBM_NOWHERE__DATA_MASK 0xffffffff
+#define GRBM_NOWHERE__DATA__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x1
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x2
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x4
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x8
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x10
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x20
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5
+#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x100
+#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8
+#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x200
+#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9
+#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x400
+#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x800
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x1
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x2
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x4
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x8
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x10
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x20
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x40
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x80
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x100
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x200
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x400
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x800
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x1000
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x2000
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x4000
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x8000
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf
+#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x10000
+#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10
+#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x20000
+#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11
+#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x40000
+#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12
+#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x80000
+#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13
+#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x100000
+#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x200000
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x400000
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x800000
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x1000000
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18
+#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x2000000
+#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19
+#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x1
+#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0
+#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x2
+#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1
+#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x4
+#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2
+#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x8
+#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3
+#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x10
+#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4
+#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x20
+#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5
+#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x40
+#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6
+#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x80
+#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7
+#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x100
+#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8
+#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x200
+#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9
+#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x400
+#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa
+#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x800
+#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb
+#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x1000
+#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc
+#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x2000
+#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd
+#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x4000
+#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe
+#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x100000
+#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14
+#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1
+#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0
+#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x2
+#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1
+#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x4
+#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2
+#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x8
+#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3
+#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x10
+#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4
+#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20
+#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5
+#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x2000
+#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd
+#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0xc000
+#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x10000
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10
+#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x20000
+#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x40000
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x80000
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x100000
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x200000
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15
+#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x400000
+#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16
+#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x1000000
+#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18
+#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x2000000
+#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19
+#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x4000000
+#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a
+#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x8000000
+#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x1
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0
+#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x6
+#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1
+#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x8
+#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3
+#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x10
+#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4
+#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x20
+#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5
+#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000
+#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c
+#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000
+#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d
+#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000
+#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e
+#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000
+#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f
+#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x1
+#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0
+#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x1
+#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0
+#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x6
+#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1
+#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x38
+#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3
+#define PA_SU_POINT_SIZE__HEIGHT_MASK 0xffff
+#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0
+#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000
+#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10
+#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0xffff
+#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0
+#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000
+#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10
+#define PA_SU_LINE_CNTL__WIDTH_MASK 0xffff
+#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0
+#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x3
+#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0
+#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x4
+#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2
+#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x8
+#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3
+#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x10
+#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4
+#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffff
+#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x1
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0
+#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x2
+#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1
+#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x4
+#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x8
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x10
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4
+#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x20
+#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5
+#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x40
+#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x80
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7
+#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0xff00
+#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8
+#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000
+#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e
+#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000
+#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x1
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0
+#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x2
+#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1
+#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x4
+#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2
+#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x18
+#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0xe0
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x700
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x800
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x1000
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x2000
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x10000
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x80000
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x100000
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x200000
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0xff
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x100
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8
+#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffff
+#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffff
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffff
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffff
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffff
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x1ff
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x1ff0000
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10
+#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0xffffff
+#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffff
+#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffff
+#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffff
+#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffff
+#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x7
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0
+#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x10
+#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x1e000
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd
+#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x700000
+#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14
+#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x3000000
+#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0xffff
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0xffff
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0xf
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0xf0
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0xf00
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0xf000
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0xf0000
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0xf00000
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0xf000000
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0xf
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0xf0
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0xf00
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0xf000
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0xf0000
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0xf00000
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0xf000000
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c
+#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0xffff
+#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0
+#define PA_SC_EDGERULE__ER_TRI_MASK 0xf
+#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0
+#define PA_SC_EDGERULE__ER_POINT_MASK 0xf0
+#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4
+#define PA_SC_EDGERULE__ER_RECT_MASK 0xf00
+#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8
+#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x3f000
+#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc
+#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0xfc0000
+#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12
+#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0xf000000
+#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18
+#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000
+#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x200
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9
+#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x400
+#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa
+#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x800
+#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb
+#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x1000
+#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0xffff
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0xff0000
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d
+#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x1
+#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0
+#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x2
+#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1
+#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x4
+#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2
+#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x8
+#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3
+#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x1
+#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0
+#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x2
+#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1
+#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x4
+#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x8
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x70
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4
+#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x80
+#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7
+#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x100
+#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8
+#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x200
+#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9
+#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x400
+#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x800
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x1000
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc
+#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x2000
+#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x4000
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x8000
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf
+#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x10000
+#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10
+#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x20000
+#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x40000
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x80000
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0xf00000
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x1000000
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x2000000
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x4000000
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x8000000
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x3
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0xc
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2
+#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x30
+#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4
+#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x40
+#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6
+#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x80
+#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7
+#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x300
+#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8
+#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0xc00
+#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa
+#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x3000
+#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc
+#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0xc000
+#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe
+#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x30000
+#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10
+#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0xc0000
+#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12
+#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x300000
+#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14
+#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x3000000
+#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18
+#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0xc000000
+#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a
+#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000
+#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x3
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0xc
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x30
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x3
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0xc
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2
+#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x7fff
+#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0
+#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10
+#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x7fff
+#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0
+#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0xffff
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0xffff
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0xffff
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x7fff
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x7fff
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x1
+#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0
+#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x2
+#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1
+#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x4
+#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x8
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x10
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4
+#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x20
+#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5
+#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK 0xc0
+#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT 0x6
+#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x100
+#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x8
+#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x200
+#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x9
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0xa
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x800
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0xb
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x1000
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xc
+#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x2000
+#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xd
+#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x4000
+#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xe
+#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x8000
+#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xf
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x10000
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0x10
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x20000
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0x11
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x40000
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x12
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x80000
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x13
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x100000
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x14
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x200000
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x15
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x400000
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x16
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x800000
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x17
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x1000000
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x18
+#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x2000000
+#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x19
+#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x4000000
+#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x1a
+#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x8000000
+#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x1b
+#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x10000000
+#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1c
+#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x20000000
+#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1d
+#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000
+#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x1e
+#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000
+#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x1f
+#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x3f
+#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0
+#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x7fc0
+#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6
+#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x1f8000
+#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf
+#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xff800000
+#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x17
+#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x3f
+#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0
+#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0xfc0
+#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6
+#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x3f000
+#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc
+#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0xfc0000
+#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0xffff
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0xf
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0xff00
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8
+#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0xffff
+#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xffff0000
+#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10
+#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0xffff
+#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xffff0000
+#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10
+#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0xffff
+#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xffff0000
+#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10
+#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0xffff
+#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xffff0000
+#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
+#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
+#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
+#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
+#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
+#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
+#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
+#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
+#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
+#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
+#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
+#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
+#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
+#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
+#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
+#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
+#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
+#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
+#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
+#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
+#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
+#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000
+#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f
+#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000
+#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f
+#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x3ff
+#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0
+#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000
+#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d
+#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000
+#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e
+#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000
+#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f
+#define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x1f
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x0
+#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffff
+#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x0
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x3f
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x0
+#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffff
+#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x0
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xff
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x0
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x100
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x8
+#define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x600
+#define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x9
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x800
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0xb
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x1000
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0xc
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x2000
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0xd
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x4000
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0xe
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x8000
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0xf
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x10000
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x10
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x20000
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x11
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x40000
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x12
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x80000
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x13
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x100000
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x14
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x200000
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x15
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x400000
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x16
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x800000
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x17
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x1000000
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x18
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x2000000
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x19
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x4000000
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x1a
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x8000000
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x0
+#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x700
+#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x8
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x3800
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0xb
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x1c000
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0xe
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0xe0000
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x11
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x100000
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x14
+#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x200000
+#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x15
+#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x400000
+#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x16
+#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x800000
+#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x17
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x1000000
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x18
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x2000000
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x19
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0xc000000
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x1a
+#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000
+#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000
+#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000
+#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000
+#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x7
+#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x0
+#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x38
+#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x3
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0xc0
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x6
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0xf00
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x8
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0xf000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0xc
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0xf0000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x10
+#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x100000
+#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x14
+#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x200000
+#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x15
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x400000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x16
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x800000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x17
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x1000000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x18
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x2000000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x19
+#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x4000000
+#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x1a
+#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x8000000
+#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000
+#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000
+#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x3fff
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x0
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0xfc000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0xe
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x700000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x14
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x800000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x17
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x7000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x18
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x3fff
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x0
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0xfc000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0xe
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x700000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x14
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x800000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x17
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x7000000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x18
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x3fff
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x0
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0xfc000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0xe
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x700000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x14
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x800000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x17
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x7000000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x18
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x3fff
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x0
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0xfc000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0xe
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x700000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x14
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x800000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x17
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x7000000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x18
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x1
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x0
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x2
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x1
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x4
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x2
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x8
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x3
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x10
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x4
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x20
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x5
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x40
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x6
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x80
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x7
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x8
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf000
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0xc
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf0000
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x10
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00000
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x14
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x1000000
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x18
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x2000000
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x19
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x4000000
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x1a
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x8000000
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000
+#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000
+#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000
+#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000
+#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0xff
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x0
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x1f00
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x8
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x3e000
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0xd
+#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0xc0000
+#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x12
+#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x300000
+#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x14
+#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0xc00000
+#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x16
+#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x1000000
+#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x18
+#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x2000000
+#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x19
+#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x4000000
+#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x1a
+#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x8000000
+#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000
+#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000
+#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x7
+#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x0
+#define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x8
+#define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x3
+#define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x10
+#define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x4
+#define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x20
+#define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x5
+#define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x40
+#define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x6
+#define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x80
+#define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x7
+#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0xf00
+#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x8
+#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x3000
+#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0xc
+#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x4000
+#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0xe
+#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x8000
+#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0xf
+#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x10000
+#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x10
+#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x1e0000
+#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x11
+#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x600000
+#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x15
+#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x800000
+#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x17
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x18
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x3f
+#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x0
+#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0xfc0
+#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x6
+#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x3f000
+#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0xc
+#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x40000
+#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x12
+#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x80000
+#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x13
+#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x100000
+#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x14
+#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0xe00000
+#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x15
+#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000
+#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x18
+#define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000
+#define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0xffff
+#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x0
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x1f0000
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x10
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x3e00000
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x15
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x1a
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x7f
+#define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x0
+#define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x80
+#define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x7
+#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x1f00
+#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x8
+#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x3e000
+#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0xd
+#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x40000
+#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x12
+#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x80000
+#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x13
+#define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x7f00000
+#define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x14
+#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
+#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000
+#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000
+#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000
+#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x7f
+#define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x0
+#define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x80
+#define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x7
+#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x1f00
+#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x8
+#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x3e000
+#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0xd
+#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x40000
+#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x12
+#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x80000
+#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x13
+#define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x7f00000
+#define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x14
+#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
+#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000
+#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000
+#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000
+#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x7f
+#define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x0
+#define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x80
+#define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x7
+#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x1f00
+#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x8
+#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x3e000
+#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0xd
+#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x40000
+#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x12
+#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x80000
+#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x13
+#define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x7f00000
+#define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x14
+#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
+#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000
+#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000
+#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000
+#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x7f
+#define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x0
+#define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x80
+#define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x7
+#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x1f00
+#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x8
+#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x3e000
+#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0xd
+#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x40000
+#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x12
+#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x80000
+#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x13
+#define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x7f00000
+#define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x14
+#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
+#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000
+#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000
+#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000
+#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x3f
+#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x0
+#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x1c0
+#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x6
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0xe00
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x9
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0xf000
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0xc
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3ff0000
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x10
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0xc000000
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x1a
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x1c
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x1e
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x1f
+#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x7f
+#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x0
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x380
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x7
+#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x7c00
+#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0xa
+#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x8000
+#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0xf
+#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0xf0000
+#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x10
+#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x300000
+#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x14
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x400000
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x16
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x800000
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x17
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0xf000000
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x18
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x1c
+#define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x7f
+#define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x0
+#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x180
+#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x7
+#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x7e00
+#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x9
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x8000
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0xf
+#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x7f0000
+#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x10
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x3800000
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x17
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x1a
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0xff
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x0
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0xf00
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x8
+#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x1000
+#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0xc
+#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x2000
+#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0xd
+#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x1fc000
+#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0xe
+#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x600000
+#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x15
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x800000
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x17
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x1000000
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x18
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x2000000
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x19
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x4000000
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x1a
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x8000000
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x1b
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x1c
+#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000
+#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x1d
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x1e
+#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000
+#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x1f
+#define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x3
+#define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x0
+#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x3c
+#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x2
+#define SETUP_DEBUG_REG0__pmode_state_MASK 0x3f00
+#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x8
+#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x4000
+#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0xe
+#define SETUP_DEBUG_REG0__geom_enable_MASK 0x8000
+#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0xf
+#define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x30000
+#define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x10
+#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x40000
+#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x12
+#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x80000
+#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x13
+#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x100000
+#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x14
+#define SETUP_DEBUG_REG0__geom_busy_MASK 0x200000
+#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x15
+#define SETUP_DEBUG_REG0__event_id_gated_MASK 0xfc00000
+#define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x16
+#define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000
+#define SETUP_DEBUG_REG0__event_gated__SHIFT 0x1c
+#define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000
+#define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x1d
+#define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000
+#define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x1e
+#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000
+#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x1f
+#define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0xffff
+#define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x0
+#define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000
+#define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x10
+#define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0xffff
+#define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x0
+#define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000
+#define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x10
+#define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0xffff
+#define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x0
+#define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000
+#define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x10
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x3fff
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x0
+#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x4000
+#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0xe
+#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x8000
+#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0xf
+#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x70000
+#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x10
+#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x80000
+#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x13
+#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x700000
+#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x14
+#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x800000
+#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x17
+#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x3000000
+#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x18
+#define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000
+#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x1a
+#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000
+#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x1d
+#define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000
+#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x1f
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x3fff
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x0
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0xfffc000
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0xe
+#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000
+#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x1c
+#define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000
+#define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x1e
+#define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000
+#define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x1f
+#define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x3
+#define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x0
+#define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0xc
+#define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x2
+#define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x3
+#define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x0
+#define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0xc
+#define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x2
+#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x1
+#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0
+#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x2
+#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1
+#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x4
+#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x8
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x10
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4
+#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x20
+#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5
+#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x40
+#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6
+#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x380
+#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x7
+#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x400
+#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa
+#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x800
+#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb
+#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x1000
+#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0xc
+#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x4000
+#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe
+#define COMPUTE_DIM_X__SIZE_MASK 0xffffffff
+#define COMPUTE_DIM_X__SIZE__SHIFT 0x0
+#define COMPUTE_DIM_Y__SIZE_MASK 0xffffffff
+#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0
+#define COMPUTE_DIM_Z__SIZE_MASK 0xffffffff
+#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0
+#define COMPUTE_START_X__START_MASK 0xffffffff
+#define COMPUTE_START_X__START__SHIFT 0x0
+#define COMPUTE_START_Y__START_MASK 0xffffffff
+#define COMPUTE_START_Y__START__SHIFT 0x0
+#define COMPUTE_START_Z__START_MASK 0xffffffff
+#define COMPUTE_START_Z__START__SHIFT 0x0
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0xffff
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0xffff
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0xffff
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10
+#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x1
+#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0
+#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x1
+#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0
+#define COMPUTE_PGM_LO__DATA_MASK 0xffffffff
+#define COMPUTE_PGM_LO__DATA__SHIFT 0x0
+#define COMPUTE_PGM_HI__DATA_MASK 0xff
+#define COMPUTE_PGM_HI__DATA__SHIFT 0x0
+#define COMPUTE_PGM_HI__INST_ATC_MASK 0x100
+#define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x8
+#define COMPUTE_TBA_LO__DATA_MASK 0xffffffff
+#define COMPUTE_TBA_LO__DATA__SHIFT 0x0
+#define COMPUTE_TBA_HI__DATA_MASK 0xff
+#define COMPUTE_TBA_HI__DATA__SHIFT 0x0
+#define COMPUTE_TMA_LO__DATA_MASK 0xffffffff
+#define COMPUTE_TMA_LO__DATA__SHIFT 0x0
+#define COMPUTE_TMA_HI__DATA_MASK 0xff
+#define COMPUTE_TMA_HI__DATA__SHIFT 0x0
+#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x3f
+#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0
+#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x3c0
+#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6
+#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0xc00
+#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa
+#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0xff000
+#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc
+#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x100000
+#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14
+#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x200000
+#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15
+#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x400000
+#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16
+#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x800000
+#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17
+#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x1000000
+#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18
+#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x2000000
+#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19
+#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x1
+#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0
+#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x3e
+#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1
+#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x40
+#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6
+#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x80
+#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7
+#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x100
+#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8
+#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x200
+#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9
+#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x400
+#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa
+#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x1800
+#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb
+#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x6000
+#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd
+#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0xff8000
+#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf
+#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000
+#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18
+#define COMPUTE_VMID__DATA_MASK 0xf
+#define COMPUTE_VMID__DATA__SHIFT 0x0
+#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x3ff
+#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0
+#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0xf000
+#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc
+#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x3f0000
+#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10
+#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x400000
+#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16
+#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x800000
+#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17
+#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x7000000
+#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0xffff
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0xffff
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0xfff
+#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0
+#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000
+#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0xffff
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xffff0000
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0xffff
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xffff0000
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_RESTART_X__RESTART_MASK 0xffffffff
+#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0
+#define COMPUTE_RESTART_Y__RESTART_MASK 0xffffffff
+#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0
+#define COMPUTE_RESTART_Z__RESTART_MASK 0xffffffff
+#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0
+#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x1
+#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0
+#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x3
+#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0
+#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x4
+#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2
+#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x8
+#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3
+#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x10
+#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4
+#define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0
+#define CSPRIV_CONNECT__DOORBELL_OFFSET_MASK 0x1fffff
+#define CSPRIV_CONNECT__DOORBELL_OFFSET__SHIFT 0x0
+#define CSPRIV_CONNECT__QUEUE_ID_MASK 0xe00000
+#define CSPRIV_CONNECT__QUEUE_ID__SHIFT 0x15
+#define CSPRIV_CONNECT__VMID_MASK 0x3c000000
+#define CSPRIV_CONNECT__VMID__SHIFT 0x1a
+#define CSPRIV_CONNECT__UNORD_DISP_MASK 0x80000000
+#define CSPRIV_CONNECT__UNORD_DISP__SHIFT 0x1f
+#define CSPRIV_THREAD_TRACE_TG0__TGID_X_MASK 0xffffffff
+#define CSPRIV_THREAD_TRACE_TG0__TGID_X__SHIFT 0x0
+#define CSPRIV_THREAD_TRACE_TG1__TGID_Y_MASK 0xffffffff
+#define CSPRIV_THREAD_TRACE_TG1__TGID_Y__SHIFT 0x0
+#define CSPRIV_THREAD_TRACE_TG2__TGID_Z_MASK 0xffffffff
+#define CSPRIV_THREAD_TRACE_TG2__TGID_Z__SHIFT 0x0
+#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE_MASK 0xfff
+#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE__SHIFT 0x0
+#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP_MASK 0xfff000
+#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP__SHIFT 0xc
+#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG_MASK 0x1000000
+#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG__SHIFT 0x18
+#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG_MASK 0x2000000
+#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG__SHIFT 0x19
+#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG_MASK 0x4000000
+#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG__SHIFT 0x1a
+#define CSPRIV_THREAD_TRACE_TG3__LAST_TG_MASK 0x8000000
+#define CSPRIV_THREAD_TRACE_TG3__LAST_TG__SHIFT 0x1b
+#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG_MASK 0x10000000
+#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG__SHIFT 0x1c
+#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID_MASK 0x1f
+#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID__SHIFT 0x0
+#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1
+#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0
+#define RLC_CNTL__FORCE_RETRY_MASK 0x2
+#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1
+#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x4
+#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2
+#define RLC_CNTL__RLC_STEP_F32_MASK 0x8
+#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3
+#define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK 0x10
+#define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT 0x4
+#define RLC_CNTL__RESERVED_MASK 0xffffff00
+#define RLC_CNTL__RESERVED__SHIFT 0x8
+#define RLC_DEBUG_SELECT__SELECT_MASK 0xff
+#define RLC_DEBUG_SELECT__SELECT__SHIFT 0x0
+#define RLC_DEBUG_SELECT__RESERVED_MASK 0xffffff00
+#define RLC_DEBUG_SELECT__RESERVED__SHIFT 0x8
+#define RLC_DEBUG__DATA_MASK 0xffffffff
+#define RLC_DEBUG__DATA__SHIFT 0x0
+#define RLC_MC_CNTL__WRREQ_SWAP_MASK 0x3
+#define RLC_MC_CNTL__WRREQ_SWAP__SHIFT 0x0
+#define RLC_MC_CNTL__WRREQ_TRAN_MASK 0x4
+#define RLC_MC_CNTL__WRREQ_TRAN__SHIFT 0x2
+#define RLC_MC_CNTL__WRREQ_PRIV_MASK 0x8
+#define RLC_MC_CNTL__WRREQ_PRIV__SHIFT 0x3
+#define RLC_MC_CNTL__WRNFO_STALL_MASK 0x10
+#define RLC_MC_CNTL__WRNFO_STALL__SHIFT 0x4
+#define RLC_MC_CNTL__WRNFO_URG_MASK 0x1e0
+#define RLC_MC_CNTL__WRNFO_URG__SHIFT 0x5
+#define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK 0x1e00
+#define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT 0x9
+#define RLC_MC_CNTL__RESERVED_B_MASK 0xfe000
+#define RLC_MC_CNTL__RESERVED_B__SHIFT 0xd
+#define RLC_MC_CNTL__RDNFO_URG_MASK 0xf00000
+#define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x14
+#define RLC_MC_CNTL__RDREQ_SWAP_MASK 0x3000000
+#define RLC_MC_CNTL__RDREQ_SWAP__SHIFT 0x18
+#define RLC_MC_CNTL__RDREQ_TRAN_MASK 0x4000000
+#define RLC_MC_CNTL__RDREQ_TRAN__SHIFT 0x1a
+#define RLC_MC_CNTL__RDREQ_PRIV_MASK 0x8000000
+#define RLC_MC_CNTL__RDREQ_PRIV__SHIFT 0x1b
+#define RLC_MC_CNTL__RDNFO_STALL_MASK 0x10000000
+#define RLC_MC_CNTL__RDNFO_STALL__SHIFT 0x1c
+#define RLC_MC_CNTL__RESERVED_MASK 0xe0000000
+#define RLC_MC_CNTL__RESERVED__SHIFT 0x1d
+#define RLC_STAT__RLC_BUSY_MASK 0x1
+#define RLC_STAT__RLC_BUSY__SHIFT 0x0
+#define RLC_STAT__RLC_GPM_BUSY_MASK 0x2
+#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1
+#define RLC_STAT__RLC_SPM_BUSY_MASK 0x4
+#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2
+#define RLC_STAT__RESERVED_MASK 0xfffffff8
+#define RLC_STAT__RESERVED__SHIFT 0x3
+#define RLC_SAFE_MODE__REQ_MASK 0x1
+#define RLC_SAFE_MODE__REQ__SHIFT 0x0
+#define RLC_SAFE_MODE__MESSAGE_MASK 0x1e
+#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1
+#define RLC_SAFE_MODE__RESERVED_MASK 0xffffffe0
+#define RLC_SAFE_MODE__RESERVED__SHIFT 0x5
+#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU_MASK 0x1
+#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU__SHIFT 0x0
+#define RLC_SOFT_RESET_GPU__RESERVED_MASK 0xfffffffe
+#define RLC_SOFT_RESET_GPU__RESERVED__SHIFT 0x1
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0
+#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x2
+#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1
+#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0xfc
+#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0xff00
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0xff0000
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10
+#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
+#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
+#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x7
+#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
+#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
+#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0xff
+#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0xff
+#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x1
+#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0
+#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x2
+#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1
+#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x4
+#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2
+#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x8
+#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3
+#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0xff0
+#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4
+#define RLC_LB_CNTL__RESERVED_MASK 0xfffff000
+#define RLC_LB_CNTL__RESERVED__SHIFT 0xc
+#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffff
+#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0
+#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffff
+#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0
+#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffff
+#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0
+#define RLC_SAVE_AND_RESTORE_BASE__BASE_MASK 0xffffffff
+#define RLC_SAVE_AND_RESTORE_BASE__BASE__SHIFT 0x0
+#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xffffffff
+#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0
+#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST_MASK 0x1
+#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST__SHIFT 0x0
+#define RLC_DRIVER_CPDMA_STATUS__RESERVED1_MASK 0xe
+#define RLC_DRIVER_CPDMA_STATUS__RESERVED1__SHIFT 0x1
+#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK_MASK 0x10
+#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK__SHIFT 0x4
+#define RLC_DRIVER_CPDMA_STATUS__RESERVED_MASK 0xffffffe0
+#define RLC_DRIVER_CPDMA_STATUS__RESERVED__SHIFT 0x5
+#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0xff
+#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0
+#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0xff00
+#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8
+#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xffff0000
+#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10
+#define RLC_GPM_DEBUG_SELECT__SELECT_MASK 0xff
+#define RLC_GPM_DEBUG_SELECT__SELECT__SHIFT 0x0
+#define RLC_GPM_DEBUG_SELECT__RESERVED_MASK 0xffffff00
+#define RLC_GPM_DEBUG_SELECT__RESERVED__SHIFT 0x8
+#define RLC_GPM_DEBUG__DATA_MASK 0xffffffff
+#define RLC_GPM_DEBUG__DATA__SHIFT 0x0
+#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
+#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000
+#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc
+#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
+#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffff
+#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0
+#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffff
+#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x1
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffe
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1
+#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffff
+#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0
+#define RLC_GPM_STAT__RLC_BUSY_MASK 0x1
+#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0
+#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x2
+#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1
+#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x4
+#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2
+#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x8
+#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3
+#define RLC_GPM_STAT__RESERVED_MASK 0xfffffff0
+#define RLC_GPM_STAT__RESERVED__SHIFT 0x4
+#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x3f
+#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0
+#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0
+#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6
+#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffff
+#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0
+#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1
+#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0
+#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x2
+#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1
+#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x4
+#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2
+#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x8
+#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3
+#define RLC_PG_CNTL__RESERVED_MASK 0xfff0
+#define RLC_PG_CNTL__RESERVED__SHIFT 0x4
+#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x10000
+#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10
+#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x20000
+#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11
+#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x40000
+#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12
+#define RLC_PG_CNTL__RESERVED1_MASK 0xf80000
+#define RLC_PG_CNTL__RESERVED1__SHIFT 0x13
+#define RLC_PG_CNTL__PG_ERROR_STATUS_MASK 0xff000000
+#define RLC_PG_CNTL__PG_ERROR_STATUS__SHIFT 0x18
+#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0xff
+#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0
+#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0xff00
+#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8
+#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0xff0000
+#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10
+#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xff000000
+#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18
+#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x1
+#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0
+#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x2
+#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1
+#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x4
+#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2
+#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x8
+#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3
+#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xfffffff0
+#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4
+#define RLC_GPM_VMID_THREAD0__RLC_VMID_MASK 0xf
+#define RLC_GPM_VMID_THREAD0__RLC_VMID__SHIFT 0x0
+#define RLC_GPM_VMID_THREAD0__RESERVED_MASK 0xfffffff0
+#define RLC_GPM_VMID_THREAD0__RESERVED__SHIFT 0x4
+#define RLC_GPM_VMID_THREAD1__RLC_VMID_MASK 0xf
+#define RLC_GPM_VMID_THREAD1__RLC_VMID__SHIFT 0x0
+#define RLC_GPM_VMID_THREAD1__RESERVED_MASK 0xfffffff0
+#define RLC_GPM_VMID_THREAD1__RESERVED__SHIFT 0x4
+#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK 0xffffffff
+#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT 0x0
+#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1
+#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0
+#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2
+#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1
+#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0xfc
+#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
+#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x7ffff00
+#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
+#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x8000000
+#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b
+#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000
+#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c
+#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000
+#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d
+#define RLC_CGCG_CGLS_CTRL__SPARE_MASK 0x80000000
+#define RLC_CGCG_CGLS_CTRL__SPARE__SHIFT 0x1f
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0xf
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0xf0
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0xf00
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0xf000
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0xfff0000
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c
+#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff
+#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
+#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xffffffff
+#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0
+#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0xff
+#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0
+#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0xff00
+#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8
+#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0xff0000
+#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10
+#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xff000000
+#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18
+#define RLC_CU_STATUS__WORK_PENDING_MASK 0xffffffff
+#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0
+#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xffffffff
+#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0
+#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xffffffff
+#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0
+#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x1
+#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0
+#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0xfe
+#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0xff00
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10
+#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0xff
+#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0
+#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0xff00
+#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8
+#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0xff0000
+#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10
+#define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000
+#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18
+#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xffffffff
+#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0
+#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0xff
+#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0
+#define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00
+#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8
+#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x1
+#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0
+#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x2
+#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1
+#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x4
+#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2
+#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x7fff8
+#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3
+#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000
+#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13
+#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x1
+#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0
+#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffe
+#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1
+#define RLC_SMU_PG_CTRL__START_PG_MASK 0x1
+#define RLC_SMU_PG_CTRL__START_PG__SHIFT 0x0
+#define RLC_SMU_PG_CTRL__SPARE_MASK 0xfffffffe
+#define RLC_SMU_PG_CTRL__SPARE__SHIFT 0x1
+#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP_MASK 0x1
+#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP__SHIFT 0x0
+#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE_MASK 0xfffffffe
+#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE__SHIFT 0x1
+#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0xf
+#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0
+#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x30
+#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4
+#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x1c0
+#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6
+#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x200
+#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9
+#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x400
+#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xa
+#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x3800
+#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xb
+#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0xc000
+#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0xe
+#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xffff0000
+#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x10
+#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffff
+#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0
+#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffff
+#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0
+#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffff
+#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0
+#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xffffffff
+#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0xffff
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x10000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x20000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x11
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x40000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x12
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x80000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x13
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x100000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x14
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x200000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x15
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x400000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x16
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xff800000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x17
+#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0xff
+#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0
+#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x100
+#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8
+#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x200
+#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9
+#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x400
+#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa
+#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x800
+#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb
+#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x1000
+#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc
+#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x2000
+#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd
+#define RLC_SERDES_WR_CTRL__RESERVED_1_MASK 0xc000
+#define RLC_SERDES_WR_CTRL__RESERVED_1__SHIFT 0xe
+#define RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK 0x10000
+#define RLC_SERDES_WR_CTRL__CGLS_ENABLE__SHIFT 0x10
+#define RLC_SERDES_WR_CTRL__CGLS_DISABLE_MASK 0x20000
+#define RLC_SERDES_WR_CTRL__CGLS_DISABLE__SHIFT 0x11
+#define RLC_SERDES_WR_CTRL__CGLS_ON_MASK 0x40000
+#define RLC_SERDES_WR_CTRL__CGLS_ON__SHIFT 0x12
+#define RLC_SERDES_WR_CTRL__CGLS_OFF_MASK 0x80000
+#define RLC_SERDES_WR_CTRL__CGLS_OFF__SHIFT 0x13
+#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK 0x100000
+#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0__SHIFT 0x14
+#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1_MASK 0x200000
+#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1__SHIFT 0x15
+#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK 0x400000
+#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0__SHIFT 0x16
+#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK 0x800000
+#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1__SHIFT 0x17
+#define RLC_SERDES_WR_CTRL__RESERVED_2_MASK 0xf000000
+#define RLC_SERDES_WR_CTRL__RESERVED_2__SHIFT 0x18
+#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000
+#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c
+#define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffff
+#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0
+#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xffffffff
+#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0
+#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0xffff
+#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0
+#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x10000
+#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x20000
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x11
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x40000
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x12
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x80000
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x13
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x100000
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x14
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x200000
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x15
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x400000
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x16
+#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xff800000
+#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x17
+#define RLC_GPM_GENERAL_0__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_1__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_2__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_3__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_4__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_5__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_6__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_7__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0
+#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT_MASK 0xffffffff
+#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT__SHIFT 0x0
+#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x1ff
+#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0
+#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00
+#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9
+#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xffffffff
+#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0
+#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff
+#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
+#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0xf
+#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0
+#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0xf0
+#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4
+#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0xf00
+#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8
+#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0xf000
+#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc
+#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x30000
+#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10
+#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0xc0000
+#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12
+#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x100000
+#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14
+#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xffe00000
+#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15
+#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0xf
+#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0
+#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0xf0
+#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4
+#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0xf00
+#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8
+#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0xf000
+#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc
+#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x30000
+#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10
+#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0xc0000
+#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12
+#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x100000
+#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14
+#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xffe00000
+#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15
+#define RLC_GPR_REG1__DATA_MASK 0xffffffff
+#define RLC_GPR_REG1__DATA__SHIFT 0x0
+#define RLC_GPR_REG2__DATA_MASK 0xffffffff
+#define RLC_GPR_REG2__DATA__SHIFT 0x0
+#define RLC_SPM_VMID__RLC_SPM_VMID_MASK 0xf
+#define RLC_SPM_VMID__RLC_SPM_VMID__SHIFT 0x0
+#define RLC_SPM_VMID__RESERVED_MASK 0xfffffff0
+#define RLC_SPM_VMID__RESERVED__SHIFT 0x4
+#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x1
+#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0
+#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xfffffffe
+#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1
+#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x1
+#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0
+#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xfffffffe
+#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1
+#define RLC_SPM_DEBUG_SELECT__SELECT_MASK 0xff
+#define RLC_SPM_DEBUG_SELECT__SELECT__SHIFT 0x0
+#define RLC_SPM_DEBUG_SELECT__RESERVED_MASK 0x7f00
+#define RLC_SPM_DEBUG_SELECT__RESERVED__SHIFT 0x8
+#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE_MASK 0x8000
+#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE__SHIFT 0xf
+#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE_MASK 0xffff0000
+#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE__SHIFT 0x10
+#define RLC_SPM_DEBUG__DATA_MASK 0xffffffff
+#define RLC_SPM_DEBUG__DATA__SHIFT 0x0
+#define RLC_GPM_LOG_ADDR__ADDR_MASK 0xffffffff
+#define RLC_GPM_LOG_ADDR__ADDR__SHIFT 0x0
+#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xffffffff
+#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0
+#define RLC_GPM_LOG_CONT__CONT_MASK 0xffffffff
+#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0
+#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0xfff
+#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0
+#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x3000
+#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc
+#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0xc000
+#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe
+#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xffff0000
+#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10
+#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xffffffff
+#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0
+#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0xffff
+#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0
+#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xffff0000
+#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10
+#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xffffffff
+#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0xff
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x700
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0xf800
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x1f0000
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x3e00000
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7c000000
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f
+#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff
+#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
+#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff
+#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
+#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff
+#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
+#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff
+#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
+#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xffffffff
+#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0
+#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xffffffff
+#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0
+#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12
+#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x3e
+#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1
+#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x40
+#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6
+#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x1
+#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0
+#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x2
+#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1
+#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x4
+#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2
+#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x8
+#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3
+#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x10
+#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4
+#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x20
+#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5
+#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x40
+#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6
+#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x80
+#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
+#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x100
+#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8
+#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x200
+#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9
+#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x400
+#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa
+#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x800
+#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb
+#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x1000
+#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc
+#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x2000
+#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd
+#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x4000
+#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe
+#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x8000
+#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf
+#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x1
+#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0
+#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x2
+#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1
+#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x4
+#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2
+#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x8
+#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3
+#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x10
+#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x20
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x40
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6
+#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x80
+#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
+#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x100
+#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8
+#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x200
+#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9
+#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x400
+#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa
+#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x800
+#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb
+#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x1000
+#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc
+#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x2000
+#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd
+#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x4000
+#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe
+#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x8000
+#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf
+#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x1
+#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x2
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x1c
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0xe0
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x700
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x3800
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x4000
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe
+#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f
+#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0
+#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x40
+#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6
+#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x4000
+#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe
+#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x1
+#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0
+#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x10
+#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4
+#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x100
+#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8
+#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x1000
+#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc
+#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x30000
+#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10
+#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x100000
+#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14
+#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x1000000
+#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18
+#define SPI_TMPRING_SIZE__WAVES_MASK 0xfff
+#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0
+#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000
+#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
+#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0xf
+#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0
+#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0xf0
+#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4
+#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0xf00
+#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8
+#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0xf000
+#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc
+#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0xf
+#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0
+#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0xf
+#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0
+#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0xf0
+#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4
+#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0xf00
+#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8
+#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0xf000
+#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc
+#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0xf0000
+#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10
+#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0xf00000
+#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14
+#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0xf000000
+#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18
+#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xf0000000
+#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x7
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x38
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x1c0
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0xe00
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9
+#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x3000
+#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc
+#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0xc000
+#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe
+#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x30000
+#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10
+#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0xc0000
+#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12
+#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0xffff
+#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0
+#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xffff0000
+#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10
+#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0xffff
+#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0
+#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xffff0000
+#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10
+#define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x1
+#define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0
+#define SPI_CDBG_SYS_GFX__VS_EN_MASK 0x2
+#define SPI_CDBG_SYS_GFX__VS_EN__SHIFT 0x1
+#define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x4
+#define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2
+#define SPI_CDBG_SYS_GFX__ES_EN_MASK 0x8
+#define SPI_CDBG_SYS_GFX__ES_EN__SHIFT 0x3
+#define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x10
+#define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4
+#define SPI_CDBG_SYS_GFX__LS_EN_MASK 0x20
+#define SPI_CDBG_SYS_GFX__LS_EN__SHIFT 0x5
+#define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x40
+#define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6
+#define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x1
+#define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0
+#define SPI_CDBG_SYS_HP3D__VS_EN_MASK 0x2
+#define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT 0x1
+#define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x4
+#define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2
+#define SPI_CDBG_SYS_HP3D__ES_EN_MASK 0x8
+#define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT 0x3
+#define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x10
+#define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4
+#define SPI_CDBG_SYS_HP3D__LS_EN_MASK 0x20
+#define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT 0x5
+#define SPI_CDBG_SYS_CS0__PIPE0_MASK 0xff
+#define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0
+#define SPI_CDBG_SYS_CS0__PIPE1_MASK 0xff00
+#define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8
+#define SPI_CDBG_SYS_CS0__PIPE2_MASK 0xff0000
+#define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10
+#define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xff000000
+#define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18
+#define SPI_CDBG_SYS_CS1__PIPE0_MASK 0xff
+#define SPI_CDBG_SYS_CS1__PIPE0__SHIFT 0x0
+#define SPI_CDBG_SYS_CS1__PIPE1_MASK 0xff00
+#define SPI_CDBG_SYS_CS1__PIPE1__SHIFT 0x8
+#define SPI_CDBG_SYS_CS1__PIPE2_MASK 0xff0000
+#define SPI_CDBG_SYS_CS1__PIPE2__SHIFT 0x10
+#define SPI_CDBG_SYS_CS1__PIPE3_MASK 0xff000000
+#define SPI_CDBG_SYS_CS1__PIPE3__SHIFT 0x18
+#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x1f
+#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x1f
+#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x1f
+#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x1f
+#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x1f
+#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x1f
+#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x1f
+#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x1f
+#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x1f
+#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x1f
+#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0
+#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x1
+#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0
+#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x3
+#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0
+#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0xc
+#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2
+#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x70
+#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4
+#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x80
+#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7
+#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x100
+#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8
+#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x200
+#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9
+#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x8000
+#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf
+#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xffff0000
+#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10
+#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x1ff
+#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0
+#define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x200
+#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9
+#define SPI_GDBG_TBA_LO__MEM_BASE_MASK 0xffffffff
+#define SPI_GDBG_TBA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_GDBG_TBA_HI__MEM_BASE_MASK 0xff
+#define SPI_GDBG_TBA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_GDBG_TMA_LO__MEM_BASE_MASK 0xffffffff
+#define SPI_GDBG_TMA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_GDBG_TMA_HI__MEM_BASE_MASK 0xff
+#define SPI_GDBG_TMA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xffffffff
+#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0
+#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xffffffff
+#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x1
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x0
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x2
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x1
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x4
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x2
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x8
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x3
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x10
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x4
+#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x1
+#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
+#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
+#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x1fffff
+#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0
+#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0xe00000
+#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15
+#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x1000000
+#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18
+#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x2000000
+#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19
+#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x4000000
+#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a
+#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x8000000
+#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b
+#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE_MASK 0x1
+#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE__SHIFT 0x0
+#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK 0xe
+#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x1
+#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK 0x3f0
+#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT 0x4
+#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0xfc00
+#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0xa
+#define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x10000
+#define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x10
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x20000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x11
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x40000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x12
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2_MASK 0x80000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2__SHIFT 0x13
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x100000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x14
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4_MASK 0x200000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4__SHIFT 0x15
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5_MASK 0x400000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5__SHIFT 0x16
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6_MASK 0x800000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6__SHIFT 0x17
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7_MASK 0x1000000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7__SHIFT 0x18
+#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK 0xe000000
+#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT 0x19
+#define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000
+#define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x1f
+#define SPI_DEBUG_READ__DATA_MASK 0xffffff
+#define SPI_DEBUG_READ__DATA__SHIFT 0x0
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x3ff
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0xffc00
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x3ff
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0xffc00
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0xff
+#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0xff
+#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0xf
+#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0
+#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0xf0
+#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4
+#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0xf00
+#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8
+#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0xf000
+#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc
+#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0xf0000
+#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10
+#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0xf00000
+#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14
+#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0xf000000
+#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18
+#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xf0000000
+#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c
+#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0xf
+#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0
+#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x10
+#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x40
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x80
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7
+#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x100
+#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x200
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x3c00
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xffff0000
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10
+#define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x1
+#define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x0
+#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x2
+#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x1
+#define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x4
+#define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x2
+#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x8
+#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x3
+#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x10
+#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x4
+#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x20
+#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x5
+#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x40
+#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x6
+#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x80
+#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x7
+#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x100
+#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x8
+#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x200
+#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x9
+#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x400
+#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0xa
+#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x800
+#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0xb
+#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x1000
+#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xc
+#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x2000
+#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xd
+#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x4000
+#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xe
+#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x8000
+#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xf
+#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x10000
+#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x10
+#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x20000
+#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x11
+#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x40000
+#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x12
+#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x80000
+#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x13
+#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x100000
+#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x14
+#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x200000
+#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x15
+#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x400000
+#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x16
+#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x800000
+#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x17
+#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0xf
+#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0
+#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0xff0
+#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4
+#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x1000
+#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc
+#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x10000
+#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10
+#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0xe0000
+#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11
+#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x100000
+#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14
+#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x200000
+#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15
+#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x400000
+#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16
+#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x800000
+#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17
+#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000
+#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18
+#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x1f
+#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0
+#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x1f00
+#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8
+#define CGTS_RD_REG__READ_DATA_MASK 0x3fff
+#define CGTS_RD_REG__READ_DATA__SHIFT 0x0
+#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000
+#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
+#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000
+#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
+#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU1_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU1_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU2_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU2_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU3_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU3_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU5_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU5_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU6_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU6_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU7_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU7_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU9_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU9_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU10_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU10_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU11_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU11_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU13_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU13_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU14_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU14_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU15_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU15_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000
+#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
+#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000
+#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
+#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x4000000
+#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x1a
+#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x8000000
+#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b
+#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000
+#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c
+#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000
+#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d
+#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000
+#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e
+#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
+#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE_MASK 0x2000000
+#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE__SHIFT 0x19
+#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE_MASK 0x4000000
+#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE__SHIFT 0x1a
+#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000
+#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
+#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000
+#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
+#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000
+#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
+#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000
+#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
+#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0xfff000
+#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc
+#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x1000000
+#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18
+#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x2000000
+#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19
+#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x4000000
+#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a
+#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000
+#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
+#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000
+#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
+#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000
+#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
+#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000
+#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
+#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0xf
+#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0
+#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x10
+#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4
+#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x0
+#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000
+#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x1f
+#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK 0x1
+#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT 0x0
+#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK 0x2
+#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT 0x1
+#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK 0x4
+#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT 0x2
+#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK 0x8
+#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT 0x3
+#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY_MASK 0x10
+#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY__SHIFT 0x4
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK 0x20
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT 0x5
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK 0x40
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT 0x6
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY_MASK 0x80
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY__SHIFT 0x7
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY_MASK 0x100
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY__SHIFT 0x8
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK 0x200
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT 0x9
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK 0x400
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT 0xa
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY_MASK 0x800
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY__SHIFT 0xb
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY_MASK 0x1000
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY__SHIFT 0xc
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY_MASK 0x2000
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY__SHIFT 0xd
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY_MASK 0x4000
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY__SHIFT 0xe
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY_MASK 0x8000
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY__SHIFT 0xf
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY_MASK 0x10000
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY__SHIFT 0x10
+#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY_MASK 0x20000
+#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY__SHIFT 0x11
+#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY_MASK 0x40000
+#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY__SHIFT 0x12
+#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY_MASK 0x80000
+#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY__SHIFT 0x13
+#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY_MASK 0x100000
+#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY__SHIFT 0x14
+#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK 0x200000
+#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT 0x15
+#define SPI_LB_CTR_CTRL__LOAD_MASK 0x1
+#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0
+#define SPI_LB_CU_MASK__CU_MASK_MASK 0xffff
+#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0
+#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xffffffff
+#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0
+#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xffff
+#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0
+#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0xff
+#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0
+#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0xff00
+#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8
+#define SPI_GDS_CREDITS__UNUSED_MASK 0xffff0000
+#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10
+#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0xffff
+#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0
+#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xffff0000
+#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0xffff
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xffff0000
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xffffffff
+#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0
+#define BCI_DEBUG_READ__DATA_MASK 0xffffff
+#define BCI_DEBUG_READ__DATA__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff
+#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff
+#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff
+#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff
+#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
+#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff
+#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff
+#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff
+#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff
+#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
+#define SPI_SHADER_TBA_LO_PS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TBA_LO_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TBA_HI_PS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TBA_HI_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_LO_PS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TMA_LO_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_HI_PS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TMA_HI_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x3f
+#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x3c0
+#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0xc00
+#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0xff000
+#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x100000
+#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x200000
+#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x400000
+#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x800000
+#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x1000000
+#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL_MASK 0xe000000
+#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL__SHIFT 0x19
+#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000
+#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x80
+#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0xff00
+#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x1ff0000
+#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0xffff
+#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x3f0000
+#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
+#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0
+#define SPI_SHADER_TBA_LO_VS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TBA_LO_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TBA_HI_VS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TBA_HI_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_LO_VS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TMA_LO_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_HI_VS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TMA_HI_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x3f
+#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x3c0
+#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0xc00
+#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0xff000
+#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x100000
+#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x200000
+#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x400000
+#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x800000
+#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x3000000
+#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x4000000
+#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL_MASK 0x38000000
+#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000
+#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x1e
+#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x80
+#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x100
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x200
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x400
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x800
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb
+#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x1000
+#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x3fe000
+#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd
+#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0xffff
+#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x3f0000
+#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
+#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x3f
+#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK 0x80
+#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK 0x1ff00
+#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK 0x1ff00000
+#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK 0xff80
+#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK 0x1ff0000
+#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT 0x10
+#define SPI_SHADER_TBA_LO_GS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TBA_LO_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TBA_HI_GS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TBA_HI_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_LO_GS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TMA_LO_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_HI_GS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TMA_HI_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x3f
+#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x3c0
+#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0xc00
+#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0xff000
+#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x100000
+#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x200000
+#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x400000
+#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x800000
+#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x1000000
+#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL_MASK 0xe000000
+#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL__SHIFT 0x19
+#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000
+#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0xff80
+#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0xffff
+#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x3f0000
+#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
+#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK 0x80
+#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK 0x1ff00
+#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK 0x1ff00000
+#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT 0x14
+#define SPI_SHADER_TBA_LO_ES__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TBA_LO_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TBA_HI_ES__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TBA_HI_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_LO_ES__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TMA_LO_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_HI_ES__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TMA_HI_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xff
+#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK 0x3f
+#define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK 0x3c0
+#define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK 0xc00
+#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK 0xff000
+#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK 0x100000
+#define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK 0x200000
+#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE_MASK 0x400000
+#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK 0x800000
+#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK 0x3000000
+#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK 0x4000000
+#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL_MASK 0x38000000
+#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER_MASK 0x40000000
+#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER__SHIFT 0x1e
+#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK 0x80
+#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK 0x1ff00
+#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK 0x1ff00000
+#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC3_ES__CU_EN_MASK 0xffff
+#define SPI_SHADER_PGM_RSRC3_ES__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT_MASK 0x3f0000
+#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD_MASK 0x3c00000
+#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK 0xff80
+#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK 0x1ff0000
+#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT 0x10
+#define SPI_SHADER_TBA_LO_HS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TBA_LO_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TBA_HI_HS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TBA_HI_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_LO_HS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TMA_LO_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_HI_HS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TMA_HI_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x3f
+#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x3c0
+#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0xc00
+#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0xff000
+#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x100000
+#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x200000
+#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x400000
+#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x800000
+#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL_MASK 0x7000000
+#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x8000000
+#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x80
+#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x100
+#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x3fe00
+#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x9
+#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x3f
+#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x3c0
+#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6
+#define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK 0xff80
+#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK 0x1ff0000
+#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT 0x10
+#define SPI_SHADER_TBA_LO_LS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TBA_LO_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TBA_HI_LS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TBA_HI_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_LO_LS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TMA_LO_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_HI_LS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TMA_HI_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK 0x3f
+#define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK 0x3c0
+#define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK 0xc00
+#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK 0xff000
+#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK 0x100000
+#define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK 0x200000
+#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE_MASK 0x400000
+#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK 0x800000
+#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK 0x3000000
+#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL_MASK 0x1c000000
+#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER_MASK 0x20000000
+#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT 0x1d
+#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK 0xff80
+#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK 0x1ff0000
+#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_LS__CU_EN_MASK 0xffff
+#define SPI_SHADER_PGM_RSRC3_LS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT_MASK 0x3f0000
+#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
+#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0
+#define SQ_CONFIG__UNUSED_MASK 0xff
+#define SQ_CONFIG__UNUSED__SHIFT 0x0
+#define SQ_CONFIG__DEBUG_EN_MASK 0x100
+#define SQ_CONFIG__DEBUG_EN__SHIFT 0x8
+#define SQ_CONFIG__DISABLE_SCA_BYPASS_MASK 0x200
+#define SQ_CONFIG__DISABLE_SCA_BYPASS__SHIFT 0x9
+#define SQ_CONFIG__DISABLE_IB_DEP_CHECK_MASK 0x400
+#define SQ_CONFIG__DISABLE_IB_DEP_CHECK__SHIFT 0xa
+#define SQ_CONFIG__ENABLE_SOFT_CLAUSE_MASK 0x800
+#define SQ_CONFIG__ENABLE_SOFT_CLAUSE__SHIFT 0xb
+#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x1000
+#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc
+#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x2000
+#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd
+#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x4000
+#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe
+#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x8000
+#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf
+#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x3
+#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0
+#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0xc
+#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2
+#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x30
+#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4
+#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x40
+#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6
+#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x80
+#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7
+#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x100
+#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8
+#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x200
+#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9
+#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x400
+#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa
+#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x800
+#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb
+#define SQC_CACHES__INST_INVALIDATE_MASK 0x1
+#define SQC_CACHES__INST_INVALIDATE__SHIFT 0x0
+#define SQC_CACHES__DATA_INVALIDATE_MASK 0x2
+#define SQC_CACHES__DATA_INVALIDATE__SHIFT 0x1
+#define SQC_CACHES__INVALIDATE_VOLATILE_MASK 0x4
+#define SQC_CACHES__INVALIDATE_VOLATILE__SHIFT 0x2
+#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x7f
+#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0
+#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x380
+#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7
+#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x1ffc00
+#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa
+#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x3f
+#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0
+#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0xf00
+#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8
+#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000
+#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c
+#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000
+#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d
+#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000
+#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e
+#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000
+#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f
+#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0xf
+#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0
+#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0xf00
+#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8
+#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x30000
+#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10
+#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0xc0000
+#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12
+#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0xffffff
+#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0
+#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x1
+#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0
+#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x1
+#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0
+#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x2
+#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1
+#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x4
+#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2
+#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x8
+#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3
+#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x10
+#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4
+#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x20
+#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5
+#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x40
+#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6
+#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x1f00
+#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8
+#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x2000
+#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd
+#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0xffff
+#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0
+#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xffff0000
+#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x1
+#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0
+#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000
+#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10
+#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000
+#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14
+#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000
+#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18
+#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000
+#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c
+#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000
+#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10
+#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000
+#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14
+#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000
+#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18
+#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000
+#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c
+#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0xff
+#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0xff
+#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0xff
+#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0xff
+#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0xff
+#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0xff
+#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0xff
+#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0xff
+#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0xff
+#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0xff
+#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0xff
+#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0xff
+#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c
+#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
+#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
+#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
+#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
+#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
+#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
+#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
+#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
+#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
+#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
+#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
+#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
+#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
+#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
+#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
+#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
+#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x3fff
+#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0
+#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3fff0000
+#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10
+#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xc0000000
+#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e
+#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x3fff
+#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0
+#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
+#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
+#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000
+#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f
+#define SQ_TIME_HI__TIME_MASK 0xffffffff
+#define SQ_TIME_HI__TIME__SHIFT 0x0
+#define SQ_TIME_LO__TIME_MASK 0xffffffff
+#define SQ_TIME_LO__TIME__SHIFT 0x0
+#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xffffffff
+#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0
+#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0xf
+#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_BASE2__ATC_MASK 0x10
+#define SQ_THREAD_TRACE_BASE2__ATC__SHIFT 0x4
+#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x3fffff
+#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0
+#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x1f
+#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0
+#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x20
+#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5
+#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x80
+#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7
+#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0xf00
+#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8
+#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x3000
+#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc
+#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x4000
+#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe
+#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x8000
+#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf
+#define SQ_THREAD_TRACE_MASK__RANDOM_SEED_MASK 0xffff0000
+#define SQ_THREAD_TRACE_MASK__RANDOM_SEED__SHIFT 0x10
+#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xffffffff
+#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xffffffff
+#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xffffffff
+#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xffffffff
+#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x7
+#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0
+#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x38
+#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3
+#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x1c0
+#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6
+#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0xe00
+#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9
+#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x7000
+#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc
+#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x38000
+#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf
+#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x1c0000
+#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12
+#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x600000
+#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15
+#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x1800000
+#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17
+#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x2000000
+#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19
+#define SQ_THREAD_TRACE_MODE__PRIV_MASK 0x4000000
+#define SQ_THREAD_TRACE_MODE__PRIV__SHIFT 0x1a
+#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000
+#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b
+#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000
+#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d
+#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000
+#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e
+#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000
+#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f
+#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000
+#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f
+#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0xffff
+#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0xff0000
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x1000000
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18
+#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xffff
+#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0
+#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0xffff
+#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0
+#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xffff0000
+#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10
+#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3fffffff
+#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0
+#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xc0000000
+#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e
+#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x3ff
+#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0
+#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x3ff0000
+#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10
+#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000
+#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d
+#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000
+#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e
+#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000
+#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f
+#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xffffffff
+#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0
+#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x7
+#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0
+#define SQ_LB_CTR_CTRL__START_MASK 0x1
+#define SQ_LB_CTR_CTRL__START__SHIFT 0x0
+#define SQ_LB_CTR_CTRL__LOAD_MASK 0x2
+#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1
+#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x4
+#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2
+#define SQ_LB_DATA_ALU_CYCLES__DATA_MASK 0xffffffff
+#define SQ_LB_DATA_ALU_CYCLES__DATA__SHIFT 0x0
+#define SQ_LB_DATA_TEX_CYCLES__DATA_MASK 0xffffffff
+#define SQ_LB_DATA_TEX_CYCLES__DATA__SHIFT 0x0
+#define SQ_LB_DATA_ALU_STALLS__DATA_MASK 0xffffffff
+#define SQ_LB_DATA_ALU_STALLS__DATA__SHIFT 0x0
+#define SQ_LB_DATA_TEX_STALLS__DATA_MASK 0xffffffff
+#define SQ_LB_DATA_TEX_STALLS__DATA__SHIFT 0x0
+#define SQC_SECDED_CNT__INST_SEC_MASK 0xff
+#define SQC_SECDED_CNT__INST_SEC__SHIFT 0x0
+#define SQC_SECDED_CNT__INST_DED_MASK 0xff00
+#define SQC_SECDED_CNT__INST_DED__SHIFT 0x8
+#define SQC_SECDED_CNT__DATA_SEC_MASK 0xff0000
+#define SQC_SECDED_CNT__DATA_SEC__SHIFT 0x10
+#define SQC_SECDED_CNT__DATA_DED_MASK 0xff000000
+#define SQC_SECDED_CNT__DATA_DED__SHIFT 0x18
+#define SQ_SEC_CNT__LDS_SEC_MASK 0x3f
+#define SQ_SEC_CNT__LDS_SEC__SHIFT 0x0
+#define SQ_SEC_CNT__SGPR_SEC_MASK 0x1f00
+#define SQ_SEC_CNT__SGPR_SEC__SHIFT 0x8
+#define SQ_SEC_CNT__VGPR_SEC_MASK 0x1ff0000
+#define SQ_SEC_CNT__VGPR_SEC__SHIFT 0x10
+#define SQ_DED_CNT__LDS_DED_MASK 0x3f
+#define SQ_DED_CNT__LDS_DED__SHIFT 0x0
+#define SQ_DED_CNT__SGPR_DED_MASK 0x1f00
+#define SQ_DED_CNT__SGPR_DED__SHIFT 0x8
+#define SQ_DED_CNT__VGPR_DED_MASK 0x1ff0000
+#define SQ_DED_CNT__VGPR_DED__SHIFT 0x10
+#define SQ_DED_INFO__WAVE_ID_MASK 0xf
+#define SQ_DED_INFO__WAVE_ID__SHIFT 0x0
+#define SQ_DED_INFO__SIMD_ID_MASK 0x30
+#define SQ_DED_INFO__SIMD_ID__SHIFT 0x4
+#define SQ_DED_INFO__SOURCE_MASK 0x1c0
+#define SQ_DED_INFO__SOURCE__SHIFT 0x6
+#define SQ_DED_INFO__VM_ID_MASK 0x1e00
+#define SQ_DED_INFO__VM_ID__SHIFT 0x9
+#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff
+#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
+#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xffff
+#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
+#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3fff0000
+#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10
+#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000
+#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e
+#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000
+#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f
+#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffff
+#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0
+#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x7
+#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
+#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x38
+#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
+#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0
+#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
+#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0xe00
+#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
+#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x7000
+#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc
+#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x78000
+#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf
+#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE_MASK 0x180000
+#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE__SHIFT 0x13
+#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x600000
+#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15
+#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x800000
+#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17
+#define SQ_BUF_RSRC_WORD3__ATC_MASK 0x1000000
+#define SQ_BUF_RSRC_WORD3__ATC__SHIFT 0x18
+#define SQ_BUF_RSRC_WORD3__HASH_ENABLE_MASK 0x2000000
+#define SQ_BUF_RSRC_WORD3__HASH_ENABLE__SHIFT 0x19
+#define SQ_BUF_RSRC_WORD3__HEAP_MASK 0x4000000
+#define SQ_BUF_RSRC_WORD3__HEAP__SHIFT 0x1a
+#define SQ_BUF_RSRC_WORD3__MTYPE_MASK 0x38000000
+#define SQ_BUF_RSRC_WORD3__MTYPE__SHIFT 0x1b
+#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xc0000000
+#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e
+#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff
+#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xff
+#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0xfff00
+#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8
+#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x3f00000
+#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14
+#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3c000000
+#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a
+#define SQ_IMG_RSRC_WORD1__MTYPE_MASK 0xc0000000
+#define SQ_IMG_RSRC_WORD1__MTYPE__SHIFT 0x1e
+#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x3fff
+#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0xfffc000
+#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe
+#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000
+#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c
+#define SQ_IMG_RSRC_WORD2__INTERLACED_MASK 0x80000000
+#define SQ_IMG_RSRC_WORD2__INTERLACED__SHIFT 0x1f
+#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x7
+#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x38
+#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
+#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0
+#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
+#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0xe00
+#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
+#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0xf000
+#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc
+#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0xf0000
+#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10
+#define SQ_IMG_RSRC_WORD3__TILING_INDEX_MASK 0x1f00000
+#define SQ_IMG_RSRC_WORD3__TILING_INDEX__SHIFT 0x14
+#define SQ_IMG_RSRC_WORD3__POW2_PAD_MASK 0x2000000
+#define SQ_IMG_RSRC_WORD3__POW2_PAD__SHIFT 0x19
+#define SQ_IMG_RSRC_WORD3__MTYPE_MASK 0x4000000
+#define SQ_IMG_RSRC_WORD3__MTYPE__SHIFT 0x1a
+#define SQ_IMG_RSRC_WORD3__ATC_MASK 0x8000000
+#define SQ_IMG_RSRC_WORD3__ATC__SHIFT 0x1b
+#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xf0000000
+#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c
+#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x1fff
+#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x7ffe000
+#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd
+#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x1fff
+#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD5__LAST_ARRAY_MASK 0x3ffe000
+#define SQ_IMG_RSRC_WORD5__LAST_ARRAY__SHIFT 0xd
+#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0xfff
+#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0xff000
+#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc
+#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x100000
+#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14
+#define SQ_IMG_RSRC_WORD6__UNUNSED_MASK 0xffe00000
+#define SQ_IMG_RSRC_WORD6__UNUNSED__SHIFT 0x15
+#define SQ_IMG_RSRC_WORD7__UNUNSED_MASK 0xffffffff
+#define SQ_IMG_RSRC_WORD7__UNUNSED__SHIFT 0x0
+#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x7
+#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0
+#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x38
+#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3
+#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x1c0
+#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6
+#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0xe00
+#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9
+#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x7000
+#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc
+#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x8000
+#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf
+#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x70000
+#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10
+#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x80000
+#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13
+#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x100000
+#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14
+#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x7e00000
+#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15
+#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x8000000
+#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b
+#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000
+#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c
+#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000
+#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d
+#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0xfff
+#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0
+#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0xfff000
+#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc
+#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0xf000000
+#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18
+#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xf0000000
+#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c
+#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x3fff
+#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0
+#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0xfc000
+#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe
+#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x300000
+#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14
+#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0xc00000
+#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16
+#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x3000000
+#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18
+#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0xc000000
+#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a
+#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000
+#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c
+#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL_MASK 0x20000000
+#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT 0x1d
+#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000
+#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e
+#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0xfff
+#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0
+#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xc0000000
+#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e
+#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x7ffff
+#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0
+#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0xffffff
+#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0
+#define SQ_IND_INDEX__WAVE_ID_MASK 0xf
+#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0
+#define SQ_IND_INDEX__SIMD_ID_MASK 0x30
+#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4
+#define SQ_IND_INDEX__THREAD_ID_MASK 0xfc0
+#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6
+#define SQ_IND_INDEX__AUTO_INCR_MASK 0x1000
+#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc
+#define SQ_IND_INDEX__FORCE_READ_MASK 0x2000
+#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd
+#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x4000
+#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe
+#define SQ_IND_INDEX__UNINDEXED_MASK 0x8000
+#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf
+#define SQ_IND_INDEX__INDEX_MASK 0xffff0000
+#define SQ_IND_INDEX__INDEX__SHIFT 0x10
+#define SQ_CMD__CMD_MASK 0x7
+#define SQ_CMD__CMD__SHIFT 0x0
+#define SQ_CMD__MODE_MASK 0x70
+#define SQ_CMD__MODE__SHIFT 0x4
+#define SQ_CMD__CHECK_VMID_MASK 0x80
+#define SQ_CMD__CHECK_VMID__SHIFT 0x7
+#define SQ_CMD__TRAP_ID_MASK 0x700
+#define SQ_CMD__TRAP_ID__SHIFT 0x8
+#define SQ_CMD__WAVE_ID_MASK 0xf0000
+#define SQ_CMD__WAVE_ID__SHIFT 0x10
+#define SQ_CMD__SIMD_ID_MASK 0x300000
+#define SQ_CMD__SIMD_ID__SHIFT 0x14
+#define SQ_CMD__QUEUE_ID_MASK 0x7000000
+#define SQ_CMD__QUEUE_ID__SHIFT 0x18
+#define SQ_CMD__VM_ID_MASK 0xf0000000
+#define SQ_CMD__VM_ID__SHIFT 0x1c
+#define SQ_IND_DATA__DATA_MASK 0xffffffff
+#define SQ_IND_DATA__DATA__SHIFT 0x0
+#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0xff
+#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0
+#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0xff
+#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0
+#define SQ_HV_VMID_CTRL__DEFAULT_VMID_MASK 0xf
+#define SQ_HV_VMID_CTRL__DEFAULT_VMID__SHIFT 0x0
+#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK_MASK 0xffff0
+#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK__SHIFT 0x4
+#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xffffffff
+#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0
+#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffff
+#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0
+#define SQ_WAVE_PC_LO__PC_LO_MASK 0xffffffff
+#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0
+#define SQ_WAVE_PC_HI__PC_HI_MASK 0xff
+#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0
+#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x7
+#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0
+#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x8
+#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3
+#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x10
+#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4
+#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0xe0
+#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5
+#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x300
+#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8
+#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0xc00
+#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa
+#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x70000
+#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10
+#define SQ_WAVE_IB_DBG0__MISC_CNT_MASK 0x380000
+#define SQ_WAVE_IB_DBG0__MISC_CNT__SHIFT 0x13
+#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0xc00000
+#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x16
+#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x1000000
+#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x18
+#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x6000000
+#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x19
+#define SQ_WAVE_IB_DBG0__KILL_MASK 0x8000000
+#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1b
+#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x10000000
+#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1c
+#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xffffffff
+#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0
+#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xffffffff
+#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0
+#define SQ_WAVE_STATUS__SCC_MASK 0x1
+#define SQ_WAVE_STATUS__SCC__SHIFT 0x0
+#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x6
+#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1
+#define SQ_WAVE_STATUS__WAVE_PRIO_MASK 0x18
+#define SQ_WAVE_STATUS__WAVE_PRIO__SHIFT 0x3
+#define SQ_WAVE_STATUS__PRIV_MASK 0x20
+#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5
+#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x40
+#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6
+#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x80
+#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7
+#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x100
+#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8
+#define SQ_WAVE_STATUS__EXECZ_MASK 0x200
+#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9
+#define SQ_WAVE_STATUS__VCCZ_MASK 0x400
+#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa
+#define SQ_WAVE_STATUS__IN_TG_MASK 0x800
+#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb
+#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x1000
+#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc
+#define SQ_WAVE_STATUS__HALT_MASK 0x2000
+#define SQ_WAVE_STATUS__HALT__SHIFT 0xd
+#define SQ_WAVE_STATUS__TRAP_MASK 0x4000
+#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe
+#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x8000
+#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf
+#define SQ_WAVE_STATUS__VALID_MASK 0x10000
+#define SQ_WAVE_STATUS__VALID__SHIFT 0x10
+#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x20000
+#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11
+#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x40000
+#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12
+#define SQ_WAVE_STATUS__PERF_EN_MASK 0x80000
+#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13
+#define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x100000
+#define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x14
+#define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x200000
+#define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x15
+#define SQ_WAVE_STATUS__DATA_ATC_MASK 0x400000
+#define SQ_WAVE_STATUS__DATA_ATC__SHIFT 0x16
+#define SQ_WAVE_STATUS__INST_ATC_MASK 0x800000
+#define SQ_WAVE_STATUS__INST_ATC__SHIFT 0x17
+#define SQ_WAVE_STATUS__DISPATCH_CACHE_CTRL_MASK 0x7000000
+#define SQ_WAVE_STATUS__DISPATCH_CACHE_CTRL__SHIFT 0x18
+#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x8000000
+#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b
+#define SQ_WAVE_MODE__FP_ROUND_MASK 0xf
+#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0
+#define SQ_WAVE_MODE__FP_DENORM_MASK 0xf0
+#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4
+#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x100
+#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8
+#define SQ_WAVE_MODE__IEEE_MASK 0x200
+#define SQ_WAVE_MODE__IEEE__SHIFT 0x9
+#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x400
+#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa
+#define SQ_WAVE_MODE__DEBUG_EN_MASK 0x800
+#define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0xb
+#define SQ_WAVE_MODE__EXCP_EN_MASK 0x1ff000
+#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc
+#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000
+#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c
+#define SQ_WAVE_MODE__CSP_MASK 0xe0000000
+#define SQ_WAVE_MODE__CSP__SHIFT 0x1d
+#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x1ff
+#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0
+#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x3f0000
+#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10
+#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xe0000000
+#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d
+#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0xf
+#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0
+#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x30
+#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4
+#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0xc0
+#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6
+#define SQ_WAVE_HW_ID__CU_ID_MASK 0xf00
+#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8
+#define SQ_WAVE_HW_ID__SH_ID_MASK 0x1000
+#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc
+#define SQ_WAVE_HW_ID__SE_ID_MASK 0x6000
+#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd
+#define SQ_WAVE_HW_ID__TG_ID_MASK 0xf0000
+#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10
+#define SQ_WAVE_HW_ID__VM_ID_MASK 0xf00000
+#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14
+#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x7000000
+#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18
+#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000
+#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b
+#define SQ_WAVE_HW_ID__ME_ID_MASK 0xc0000000
+#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e
+#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x3f
+#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0
+#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x3f00
+#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8
+#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x3f0000
+#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10
+#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0xf000000
+#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18
+#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0xff
+#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0
+#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x1ff000
+#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc
+#define SQ_WAVE_IB_STS__VM_CNT_MASK 0xf
+#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0
+#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x70
+#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4
+#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0xf00
+#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8
+#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x7000
+#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc
+#define SQ_WAVE_M0__M0_MASK 0xffffffff
+#define SQ_WAVE_M0__M0__SHIFT 0x0
+#define SQ_WAVE_TBA_LO__ADDR_LO_MASK 0xffffffff
+#define SQ_WAVE_TBA_LO__ADDR_LO__SHIFT 0x0
+#define SQ_WAVE_TBA_HI__ADDR_HI_MASK 0xff
+#define SQ_WAVE_TBA_HI__ADDR_HI__SHIFT 0x0
+#define SQ_WAVE_TMA_LO__ADDR_LO_MASK 0xffffffff
+#define SQ_WAVE_TMA_LO__ADDR_LO__SHIFT 0x0
+#define SQ_WAVE_TMA_HI__ADDR_HI_MASK 0xff
+#define SQ_WAVE_TMA_HI__ADDR_HI__SHIFT 0x0
+#define SQ_WAVE_TTMP0__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP1__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP2__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP3__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP4__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP5__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP6__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP7__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP8__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP9__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP10__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP11__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0
+#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x1
+#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x0
+#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x2
+#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x1
+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0xfff0
+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x4
+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0xfff0000
+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x10
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0xff
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x0
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0xff00
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x8
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0xff0000
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x10
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x18
+#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0xf
+#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x0
+#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0xf0
+#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x4
+#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x1
+#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x0
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x3f0
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x4
+#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0xff
+#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x0
+#define SH_MEM_BASES__PRIVATE_BASE_MASK 0xffff
+#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0
+#define SH_MEM_BASES__SHARED_BASE_MASK 0xffff0000
+#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10
+#define SH_MEM_APE1_BASE__BASE_MASK 0xffffffff
+#define SH_MEM_APE1_BASE__BASE__SHIFT 0x0
+#define SH_MEM_APE1_LIMIT__LIMIT_MASK 0xffffffff
+#define SH_MEM_APE1_LIMIT__LIMIT__SHIFT 0x0
+#define SH_MEM_CONFIG__PTR32_MASK 0x1
+#define SH_MEM_CONFIG__PTR32__SHIFT 0x0
+#define SH_MEM_CONFIG__PRIVATE_ATC_MASK 0x2
+#define SH_MEM_CONFIG__PRIVATE_ATC__SHIFT 0x1
+#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0xc
+#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x2
+#define SH_MEM_CONFIG__DEFAULT_MTYPE_MASK 0x70
+#define SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT 0x4
+#define SH_MEM_CONFIG__APE1_MTYPE_MASK 0x380
+#define SH_MEM_CONFIG__APE1_MTYPE__SHIFT 0x7
+#define SQC_POLICY__DATA_L1_POLICY_0_MASK 0x1
+#define SQC_POLICY__DATA_L1_POLICY_0__SHIFT 0x0
+#define SQC_POLICY__DATA_L1_POLICY_1_MASK 0x2
+#define SQC_POLICY__DATA_L1_POLICY_1__SHIFT 0x1
+#define SQC_POLICY__DATA_L1_POLICY_2_MASK 0x4
+#define SQC_POLICY__DATA_L1_POLICY_2__SHIFT 0x2
+#define SQC_POLICY__DATA_L1_POLICY_3_MASK 0x8
+#define SQC_POLICY__DATA_L1_POLICY_3__SHIFT 0x3
+#define SQC_POLICY__DATA_L1_POLICY_4_MASK 0x10
+#define SQC_POLICY__DATA_L1_POLICY_4__SHIFT 0x4
+#define SQC_POLICY__DATA_L1_POLICY_5_MASK 0x20
+#define SQC_POLICY__DATA_L1_POLICY_5__SHIFT 0x5
+#define SQC_POLICY__DATA_L1_POLICY_6_MASK 0x40
+#define SQC_POLICY__DATA_L1_POLICY_6__SHIFT 0x6
+#define SQC_POLICY__DATA_L1_POLICY_7_MASK 0x80
+#define SQC_POLICY__DATA_L1_POLICY_7__SHIFT 0x7
+#define SQC_POLICY__DATA_L2_POLICY_0_MASK 0x300
+#define SQC_POLICY__DATA_L2_POLICY_0__SHIFT 0x8
+#define SQC_POLICY__DATA_L2_POLICY_1_MASK 0xc00
+#define SQC_POLICY__DATA_L2_POLICY_1__SHIFT 0xa
+#define SQC_POLICY__DATA_L2_POLICY_2_MASK 0x3000
+#define SQC_POLICY__DATA_L2_POLICY_2__SHIFT 0xc
+#define SQC_POLICY__DATA_L2_POLICY_3_MASK 0xc000
+#define SQC_POLICY__DATA_L2_POLICY_3__SHIFT 0xe
+#define SQC_POLICY__DATA_L2_POLICY_4_MASK 0x30000
+#define SQC_POLICY__DATA_L2_POLICY_4__SHIFT 0x10
+#define SQC_POLICY__DATA_L2_POLICY_5_MASK 0xc0000
+#define SQC_POLICY__DATA_L2_POLICY_5__SHIFT 0x12
+#define SQC_POLICY__DATA_L2_POLICY_6_MASK 0x300000
+#define SQC_POLICY__DATA_L2_POLICY_6__SHIFT 0x14
+#define SQC_POLICY__DATA_L2_POLICY_7_MASK 0xc00000
+#define SQC_POLICY__DATA_L2_POLICY_7__SHIFT 0x16
+#define SQC_POLICY__INST_L2_POLICY_MASK 0x3000000
+#define SQC_POLICY__INST_L2_POLICY__SHIFT 0x18
+#define SQC_VOLATILE__DATA_L1_MASK 0xf
+#define SQC_VOLATILE__DATA_L1__SHIFT 0x0
+#define SQC_VOLATILE__DATA_L2_MASK 0xf0
+#define SQC_VOLATILE__DATA_L2__SHIFT 0x4
+#define SQC_VOLATILE__INST_L2_MASK 0x100
+#define SQC_VOLATILE__INST_L2__SHIFT 0x8
+#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x1e0
+#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x600
+#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9
+#define SQ_THREAD_TRACE_WORD_INST__SIZE_MASK 0x800
+#define SQ_THREAD_TRACE_WORD_INST__SIZE__SHIFT 0xb
+#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xf000
+#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xc
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x1e0
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x600
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xffff0000
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0xffffff
+#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x20
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x3c0
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x3c00
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0xc000
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xffff0000
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xffff
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xffff0000
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xffffffff
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x20
+#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x3c0
+#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3c00
+#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xc000
+#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0xff0
+#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000
+#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc
+#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xe000
+#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x20
+#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x3c0
+#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x3c00
+#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0xc000
+#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x1f0000
+#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x200000
+#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15
+#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1fc00000
+#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xe0000000
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x60
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x180
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x200
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x1c00
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x4000
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x8000
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xffff0000
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xffffffff
+#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x60
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x180
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0xfe00
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xffff0000
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0xffff
+#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x20
+#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x1c0
+#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xfc00
+#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x60
+#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x300
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0xc00
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x3000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0xc000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x30000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0xc0000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x300000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0xc00000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x3000000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0xc000000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x20
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x3c0
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0xc00
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x1fff000
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xfe000000
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x3f
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x7ffc0
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xfff80000
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13
+#define SQ_INTERRUPT_WORD_CMN__SE_ID_MASK 0x3000000
+#define SQ_INTERRUPT_WORD_CMN__SE_ID__SHIFT 0x18
+#define SQ_INTERRUPT_WORD_CMN__ENCODING_MASK 0xc000000
+#define SQ_INTERRUPT_WORD_CMN__ENCODING__SHIFT 0x1a
+#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK 0x1
+#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT 0x0
+#define SQ_INTERRUPT_WORD_AUTO__WLT_MASK 0x2
+#define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT 0x1
+#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL_MASK 0x4
+#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL__SHIFT 0x2
+#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP_MASK 0x8
+#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP__SHIFT 0x3
+#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP_MASK 0x10
+#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP__SHIFT 0x4
+#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW_MASK 0x20
+#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW__SHIFT 0x5
+#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW_MASK 0x40
+#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW__SHIFT 0x6
+#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW_MASK 0x80
+#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW__SHIFT 0x7
+#define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK 0x3000000
+#define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT 0x18
+#define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK 0xc000000
+#define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT 0x1a
+#define SQ_INTERRUPT_WORD_WAVE__DATA_MASK 0xff
+#define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT 0x0
+#define SQ_INTERRUPT_WORD_WAVE__SH_ID_MASK 0x100
+#define SQ_INTERRUPT_WORD_WAVE__SH_ID__SHIFT 0x8
+#define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK 0x200
+#define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT 0x9
+#define SQ_INTERRUPT_WORD_WAVE__VM_ID_MASK 0x3c00
+#define SQ_INTERRUPT_WORD_WAVE__VM_ID__SHIFT 0xa
+#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK 0x3c000
+#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT 0xe
+#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK 0xc0000
+#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT 0x12
+#define SQ_INTERRUPT_WORD_WAVE__CU_ID_MASK 0xf00000
+#define SQ_INTERRUPT_WORD_WAVE__CU_ID__SHIFT 0x14
+#define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK 0x3000000
+#define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT 0x18
+#define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK 0xc000000
+#define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT 0x1a
+#define SQ_SOP2__SSRC0_MASK 0xff
+#define SQ_SOP2__SSRC0__SHIFT 0x0
+#define SQ_SOP2__SSRC1_MASK 0xff00
+#define SQ_SOP2__SSRC1__SHIFT 0x8
+#define SQ_SOP2__SDST_MASK 0x7f0000
+#define SQ_SOP2__SDST__SHIFT 0x10
+#define SQ_SOP2__OP_MASK 0x3f800000
+#define SQ_SOP2__OP__SHIFT 0x17
+#define SQ_SOP2__ENCODING_MASK 0xc0000000
+#define SQ_SOP2__ENCODING__SHIFT 0x1e
+#define SQ_VOP1__SRC0_MASK 0x1ff
+#define SQ_VOP1__SRC0__SHIFT 0x0
+#define SQ_VOP1__OP_MASK 0x1fe00
+#define SQ_VOP1__OP__SHIFT 0x9
+#define SQ_VOP1__VDST_MASK 0x1fe0000
+#define SQ_VOP1__VDST__SHIFT 0x11
+#define SQ_VOP1__ENCODING_MASK 0xfe000000
+#define SQ_VOP1__ENCODING__SHIFT 0x19
+#define SQ_MTBUF_1__VADDR_MASK 0xff
+#define SQ_MTBUF_1__VADDR__SHIFT 0x0
+#define SQ_MTBUF_1__VDATA_MASK 0xff00
+#define SQ_MTBUF_1__VDATA__SHIFT 0x8
+#define SQ_MTBUF_1__SRSRC_MASK 0x1f0000
+#define SQ_MTBUF_1__SRSRC__SHIFT 0x10
+#define SQ_MTBUF_1__SLC_MASK 0x400000
+#define SQ_MTBUF_1__SLC__SHIFT 0x16
+#define SQ_MTBUF_1__TFE_MASK 0x800000
+#define SQ_MTBUF_1__TFE__SHIFT 0x17
+#define SQ_MTBUF_1__SOFFSET_MASK 0xff000000
+#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18
+#define SQ_EXP_1__VSRC0_MASK 0xff
+#define SQ_EXP_1__VSRC0__SHIFT 0x0
+#define SQ_EXP_1__VSRC1_MASK 0xff00
+#define SQ_EXP_1__VSRC1__SHIFT 0x8
+#define SQ_EXP_1__VSRC2_MASK 0xff0000
+#define SQ_EXP_1__VSRC2__SHIFT 0x10
+#define SQ_EXP_1__VSRC3_MASK 0xff000000
+#define SQ_EXP_1__VSRC3__SHIFT 0x18
+#define SQ_MUBUF_1__VADDR_MASK 0xff
+#define SQ_MUBUF_1__VADDR__SHIFT 0x0
+#define SQ_MUBUF_1__VDATA_MASK 0xff00
+#define SQ_MUBUF_1__VDATA__SHIFT 0x8
+#define SQ_MUBUF_1__SRSRC_MASK 0x1f0000
+#define SQ_MUBUF_1__SRSRC__SHIFT 0x10
+#define SQ_MUBUF_1__SLC_MASK 0x400000
+#define SQ_MUBUF_1__SLC__SHIFT 0x16
+#define SQ_MUBUF_1__TFE_MASK 0x800000
+#define SQ_MUBUF_1__TFE__SHIFT 0x17
+#define SQ_MUBUF_1__SOFFSET_MASK 0xff000000
+#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18
+#define SQ_INST__ENCODING_MASK 0xffffffff
+#define SQ_INST__ENCODING__SHIFT 0x0
+#define SQ_EXP_0__EN_MASK 0xf
+#define SQ_EXP_0__EN__SHIFT 0x0
+#define SQ_EXP_0__TGT_MASK 0x3f0
+#define SQ_EXP_0__TGT__SHIFT 0x4
+#define SQ_EXP_0__COMPR_MASK 0x400
+#define SQ_EXP_0__COMPR__SHIFT 0xa
+#define SQ_EXP_0__DONE_MASK 0x800
+#define SQ_EXP_0__DONE__SHIFT 0xb
+#define SQ_EXP_0__VM_MASK 0x1000
+#define SQ_EXP_0__VM__SHIFT 0xc
+#define SQ_EXP_0__ENCODING_MASK 0xfc000000
+#define SQ_EXP_0__ENCODING__SHIFT 0x1a
+#define SQ_MUBUF_0__OFFSET_MASK 0xfff
+#define SQ_MUBUF_0__OFFSET__SHIFT 0x0
+#define SQ_MUBUF_0__OFFEN_MASK 0x1000
+#define SQ_MUBUF_0__OFFEN__SHIFT 0xc
+#define SQ_MUBUF_0__IDXEN_MASK 0x2000
+#define SQ_MUBUF_0__IDXEN__SHIFT 0xd
+#define SQ_MUBUF_0__GLC_MASK 0x4000
+#define SQ_MUBUF_0__GLC__SHIFT 0xe
+#define SQ_MUBUF_0__ADDR64_MASK 0x8000
+#define SQ_MUBUF_0__ADDR64__SHIFT 0xf
+#define SQ_MUBUF_0__LDS_MASK 0x10000
+#define SQ_MUBUF_0__LDS__SHIFT 0x10
+#define SQ_MUBUF_0__OP_MASK 0x1fc0000
+#define SQ_MUBUF_0__OP__SHIFT 0x12
+#define SQ_MUBUF_0__ENCODING_MASK 0xfc000000
+#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a
+#define SQ_VOP3_0__VDST_MASK 0xff
+#define SQ_VOP3_0__VDST__SHIFT 0x0
+#define SQ_VOP3_0__ABS_MASK 0x700
+#define SQ_VOP3_0__ABS__SHIFT 0x8
+#define SQ_VOP3_0__CLAMP_MASK 0x800
+#define SQ_VOP3_0__CLAMP__SHIFT 0xb
+#define SQ_VOP3_0__OP_MASK 0x3fe0000
+#define SQ_VOP3_0__OP__SHIFT 0x11
+#define SQ_VOP3_0__ENCODING_MASK 0xfc000000
+#define SQ_VOP3_0__ENCODING__SHIFT 0x1a
+#define SQ_VOP2__SRC0_MASK 0x1ff
+#define SQ_VOP2__SRC0__SHIFT 0x0
+#define SQ_VOP2__VSRC1_MASK 0x1fe00
+#define SQ_VOP2__VSRC1__SHIFT 0x9
+#define SQ_VOP2__VDST_MASK 0x1fe0000
+#define SQ_VOP2__VDST__SHIFT 0x11
+#define SQ_VOP2__OP_MASK 0x7e000000
+#define SQ_VOP2__OP__SHIFT 0x19
+#define SQ_VOP2__ENCODING_MASK 0x80000000
+#define SQ_VOP2__ENCODING__SHIFT 0x1f
+#define SQ_MTBUF_0__OFFSET_MASK 0xfff
+#define SQ_MTBUF_0__OFFSET__SHIFT 0x0
+#define SQ_MTBUF_0__OFFEN_MASK 0x1000
+#define SQ_MTBUF_0__OFFEN__SHIFT 0xc
+#define SQ_MTBUF_0__IDXEN_MASK 0x2000
+#define SQ_MTBUF_0__IDXEN__SHIFT 0xd
+#define SQ_MTBUF_0__GLC_MASK 0x4000
+#define SQ_MTBUF_0__GLC__SHIFT 0xe
+#define SQ_MTBUF_0__ADDR64_MASK 0x8000
+#define SQ_MTBUF_0__ADDR64__SHIFT 0xf
+#define SQ_MTBUF_0__OP_MASK 0x70000
+#define SQ_MTBUF_0__OP__SHIFT 0x10
+#define SQ_MTBUF_0__DFMT_MASK 0x780000
+#define SQ_MTBUF_0__DFMT__SHIFT 0x13
+#define SQ_MTBUF_0__NFMT_MASK 0x3800000
+#define SQ_MTBUF_0__NFMT__SHIFT 0x17
+#define SQ_MTBUF_0__ENCODING_MASK 0xfc000000
+#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a
+#define SQ_SOPP__SIMM16_MASK 0xffff
+#define SQ_SOPP__SIMM16__SHIFT 0x0
+#define SQ_SOPP__OP_MASK 0x7f0000
+#define SQ_SOPP__OP__SHIFT 0x10
+#define SQ_SOPP__ENCODING_MASK 0xff800000
+#define SQ_SOPP__ENCODING__SHIFT 0x17
+#define SQ_FLAT_0__GLC_MASK 0x10000
+#define SQ_FLAT_0__GLC__SHIFT 0x10
+#define SQ_FLAT_0__SLC_MASK 0x20000
+#define SQ_FLAT_0__SLC__SHIFT 0x11
+#define SQ_FLAT_0__OP_MASK 0x1fc0000
+#define SQ_FLAT_0__OP__SHIFT 0x12
+#define SQ_FLAT_0__ENCODING_MASK 0xfc000000
+#define SQ_FLAT_0__ENCODING__SHIFT 0x1a
+#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0xff
+#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0
+#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x7f00
+#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8
+#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x3fe0000
+#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x11
+#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xfc000000
+#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a
+#define SQ_MIMG_1__VADDR_MASK 0xff
+#define SQ_MIMG_1__VADDR__SHIFT 0x0
+#define SQ_MIMG_1__VDATA_MASK 0xff00
+#define SQ_MIMG_1__VDATA__SHIFT 0x8
+#define SQ_MIMG_1__SRSRC_MASK 0x1f0000
+#define SQ_MIMG_1__SRSRC__SHIFT 0x10
+#define SQ_MIMG_1__SSAMP_MASK 0x3e00000
+#define SQ_MIMG_1__SSAMP__SHIFT 0x15
+#define SQ_SMRD__OFFSET_MASK 0xff
+#define SQ_SMRD__OFFSET__SHIFT 0x0
+#define SQ_SMRD__IMM_MASK 0x100
+#define SQ_SMRD__IMM__SHIFT 0x8
+#define SQ_SMRD__SBASE_MASK 0x7e00
+#define SQ_SMRD__SBASE__SHIFT 0x9
+#define SQ_SMRD__SDST_MASK 0x3f8000
+#define SQ_SMRD__SDST__SHIFT 0xf
+#define SQ_SMRD__OP_MASK 0x7c00000
+#define SQ_SMRD__OP__SHIFT 0x16
+#define SQ_SMRD__ENCODING_MASK 0xf8000000
+#define SQ_SMRD__ENCODING__SHIFT 0x1b
+#define SQ_SOP1__SSRC0_MASK 0xff
+#define SQ_SOP1__SSRC0__SHIFT 0x0
+#define SQ_SOP1__OP_MASK 0xff00
+#define SQ_SOP1__OP__SHIFT 0x8
+#define SQ_SOP1__SDST_MASK 0x7f0000
+#define SQ_SOP1__SDST__SHIFT 0x10
+#define SQ_SOP1__ENCODING_MASK 0xff800000
+#define SQ_SOP1__ENCODING__SHIFT 0x17
+#define SQ_SOPC__SSRC0_MASK 0xff
+#define SQ_SOPC__SSRC0__SHIFT 0x0
+#define SQ_SOPC__SSRC1_MASK 0xff00
+#define SQ_SOPC__SSRC1__SHIFT 0x8
+#define SQ_SOPC__OP_MASK 0x7f0000
+#define SQ_SOPC__OP__SHIFT 0x10
+#define SQ_SOPC__ENCODING_MASK 0xff800000
+#define SQ_SOPC__ENCODING__SHIFT 0x17
+#define SQ_FLAT_1__ADDR_MASK 0xff
+#define SQ_FLAT_1__ADDR__SHIFT 0x0
+#define SQ_FLAT_1__DATA_MASK 0xff00
+#define SQ_FLAT_1__DATA__SHIFT 0x8
+#define SQ_FLAT_1__TFE_MASK 0x800000
+#define SQ_FLAT_1__TFE__SHIFT 0x17
+#define SQ_FLAT_1__VDST_MASK 0xff000000
+#define SQ_FLAT_1__VDST__SHIFT 0x18
+#define SQ_DS_1__ADDR_MASK 0xff
+#define SQ_DS_1__ADDR__SHIFT 0x0
+#define SQ_DS_1__DATA0_MASK 0xff00
+#define SQ_DS_1__DATA0__SHIFT 0x8
+#define SQ_DS_1__DATA1_MASK 0xff0000
+#define SQ_DS_1__DATA1__SHIFT 0x10
+#define SQ_DS_1__VDST_MASK 0xff000000
+#define SQ_DS_1__VDST__SHIFT 0x18
+#define SQ_VOP3_1__SRC0_MASK 0x1ff
+#define SQ_VOP3_1__SRC0__SHIFT 0x0
+#define SQ_VOP3_1__SRC1_MASK 0x3fe00
+#define SQ_VOP3_1__SRC1__SHIFT 0x9
+#define SQ_VOP3_1__SRC2_MASK 0x7fc0000
+#define SQ_VOP3_1__SRC2__SHIFT 0x12
+#define SQ_VOP3_1__OMOD_MASK 0x18000000
+#define SQ_VOP3_1__OMOD__SHIFT 0x1b
+#define SQ_VOP3_1__NEG_MASK 0xe0000000
+#define SQ_VOP3_1__NEG__SHIFT 0x1d
+#define SQ_MIMG_0__DMASK_MASK 0xf00
+#define SQ_MIMG_0__DMASK__SHIFT 0x8
+#define SQ_MIMG_0__UNORM_MASK 0x1000
+#define SQ_MIMG_0__UNORM__SHIFT 0xc
+#define SQ_MIMG_0__GLC_MASK 0x2000
+#define SQ_MIMG_0__GLC__SHIFT 0xd
+#define SQ_MIMG_0__DA_MASK 0x4000
+#define SQ_MIMG_0__DA__SHIFT 0xe
+#define SQ_MIMG_0__R128_MASK 0x8000
+#define SQ_MIMG_0__R128__SHIFT 0xf
+#define SQ_MIMG_0__TFE_MASK 0x10000
+#define SQ_MIMG_0__TFE__SHIFT 0x10
+#define SQ_MIMG_0__LWE_MASK 0x20000
+#define SQ_MIMG_0__LWE__SHIFT 0x11
+#define SQ_MIMG_0__OP_MASK 0x1fc0000
+#define SQ_MIMG_0__OP__SHIFT 0x12
+#define SQ_MIMG_0__SLC_MASK 0x2000000
+#define SQ_MIMG_0__SLC__SHIFT 0x19
+#define SQ_MIMG_0__ENCODING_MASK 0xfc000000
+#define SQ_MIMG_0__ENCODING__SHIFT 0x1a
+#define SQ_SOPK__SIMM16_MASK 0xffff
+#define SQ_SOPK__SIMM16__SHIFT 0x0
+#define SQ_SOPK__SDST_MASK 0x7f0000
+#define SQ_SOPK__SDST__SHIFT 0x10
+#define SQ_SOPK__OP_MASK 0xf800000
+#define SQ_SOPK__OP__SHIFT 0x17
+#define SQ_SOPK__ENCODING_MASK 0xf0000000
+#define SQ_SOPK__ENCODING__SHIFT 0x1c
+#define SQ_DS_0__OFFSET0_MASK 0xff
+#define SQ_DS_0__OFFSET0__SHIFT 0x0
+#define SQ_DS_0__OFFSET1_MASK 0xff00
+#define SQ_DS_0__OFFSET1__SHIFT 0x8
+#define SQ_DS_0__GDS_MASK 0x20000
+#define SQ_DS_0__GDS__SHIFT 0x11
+#define SQ_DS_0__OP_MASK 0x3fc0000
+#define SQ_DS_0__OP__SHIFT 0x12
+#define SQ_DS_0__ENCODING_MASK 0xfc000000
+#define SQ_DS_0__ENCODING__SHIFT 0x1a
+#define SQ_VOPC__SRC0_MASK 0x1ff
+#define SQ_VOPC__SRC0__SHIFT 0x0
+#define SQ_VOPC__VSRC1_MASK 0x1fe00
+#define SQ_VOPC__VSRC1__SHIFT 0x9
+#define SQ_VOPC__OP_MASK 0x1fe0000
+#define SQ_VOPC__OP__SHIFT 0x11
+#define SQ_VOPC__ENCODING_MASK 0xfe000000
+#define SQ_VOPC__ENCODING__SHIFT 0x19
+#define SQ_VINTRP__VSRC_MASK 0xff
+#define SQ_VINTRP__VSRC__SHIFT 0x0
+#define SQ_VINTRP__ATTRCHAN_MASK 0x300
+#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8
+#define SQ_VINTRP__ATTR_MASK 0xfc00
+#define SQ_VINTRP__ATTR__SHIFT 0xa
+#define SQ_VINTRP__OP_MASK 0x30000
+#define SQ_VINTRP__OP__SHIFT 0x10
+#define SQ_VINTRP__VDST_MASK 0x3fc0000
+#define SQ_VINTRP__VDST__SHIFT 0x12
+#define SQ_VINTRP__ENCODING_MASK 0xfc000000
+#define SQ_VINTRP__ENCODING__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0xf
+#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0xfff000
+#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0xf
+#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0xfff000
+#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0xf
+#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0xfff000
+#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0xf
+#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0xfff000
+#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0xf
+#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0xfff000
+#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f
+#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x1
+#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x0
+#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x2
+#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x1
+#define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x4
+#define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x2
+#define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x8
+#define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x3
+#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x10
+#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x4
+#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x20
+#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x5
+#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x40
+#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x6
+#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x80
+#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x7
+#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x100
+#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x8
+#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x200
+#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x9
+#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x400
+#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0xa
+#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x800
+#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0xb
+#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x1000
+#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0xc
+#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x2000
+#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0xd
+#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x4000
+#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0xe
+#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x8000
+#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0xf
+#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x10000
+#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x10
+#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x20000
+#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x11
+#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x40000
+#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x12
+#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x80000
+#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x13
+#define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x100000
+#define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x14
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x200000
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x15
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x400000
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x16
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x800000
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x17
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x1000000
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x18
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x2000000
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x19
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x4000000
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x1a
+#define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x8000000
+#define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x1b
+#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000
+#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x1c
+#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000
+#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d
+#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000
+#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x1e
+#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000
+#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x1f
+#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY_MASK 0x1
+#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY__SHIFT 0x0
+#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK 0x2
+#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT 0x1
+#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK 0x4
+#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT 0x2
+#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK 0x8
+#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT 0x3
+#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK 0x10
+#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT 0x4
+#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK 0x20
+#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT 0x5
+#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK 0x40
+#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT 0x6
+#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK 0x80
+#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT 0x7
+#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK 0x100
+#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT 0x8
+#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK 0x200
+#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT 0x9
+#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK 0x400
+#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT 0xa
+#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK 0x800
+#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT 0xb
+#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK 0x1000
+#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT 0xc
+#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK 0x2000
+#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT 0xd
+#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK 0x4000
+#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT 0xe
+#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID_MASK 0x8000
+#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID__SHIFT 0xf
+#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK 0x10000
+#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x10
+#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK 0x20000
+#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT 0x11
+#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID_MASK 0x40000
+#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID__SHIFT 0x12
+#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK 0x80000
+#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x13
+#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK 0x100000
+#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x14
+#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID_MASK 0x200000
+#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID__SHIFT 0x15
+#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK 0x400000
+#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x16
+#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK 0x800000
+#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT 0x17
+#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID_MASK 0x1000000
+#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID__SHIFT 0x18
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x2000000
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x19
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x4000000
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x1a
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x8000000
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x1b
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x10000000
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x1c
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x20000000
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x1d
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x40000000
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x1e
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x80000000
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x1f
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x1
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x0
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x2
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x1
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x4
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x2
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x8
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x3
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x10
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x4
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x20
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x5
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x40
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x6
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x80
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x7
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x100
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x8
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x200
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x9
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x400
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0xa
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x800
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0xb
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x1000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0xc
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x2000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0xd
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x4000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0xe
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x8000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0xf
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x10000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x10
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x20000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x11
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x40000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x12
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x80000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x13
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x100000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x14
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x200000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x15
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x400000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x16
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x800000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x17
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x1000000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x18
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x2000000
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x19
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x4000000
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x1a
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x8000000
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x1b
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x10000000
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x1c
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x20000000
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x1d
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x40000000
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x1e
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x80000000
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x1f
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x1
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x0
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x2
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x1
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x4
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x2
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x8
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x3
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x10
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x4
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x20
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x5
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x40
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x6
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x80
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x7
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x100
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x8
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x200
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x9
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x400
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0xa
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x800
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0xb
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x1000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0xc
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x2000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0xd
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x4000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0xe
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x8000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0xf
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x10000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x10
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x20000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x11
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x40000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x12
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x80000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x13
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x100000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x14
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x200000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x15
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x400000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x16
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x800000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x17
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x1000000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x18
+#define SX_DEBUG_BUSY_4__RESERVED_MASK 0xfe000000
+#define SX_DEBUG_BUSY_4__RESERVED__SHIFT 0x19
+#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x7f
+#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0
+#define SX_DEBUG_1__DEBUG_DATA_MASK 0xffffff80
+#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x7
+#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
+#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
+#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
+#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
+#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
+#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
+#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
+#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
+#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCC_CTRL__CACHE_SIZE_MASK 0x3
+#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0
+#define TCC_CTRL__RATE_MASK 0xc
+#define TCC_CTRL__RATE__SHIFT 0x2
+#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0xf0
+#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4
+#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0xf000
+#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc
+#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0xf0000
+#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10
+#define TCC_CTRL__WB_OR_INV_ALL_VMIDS_MASK 0x100000
+#define TCC_CTRL__WB_OR_INV_ALL_VMIDS__SHIFT 0x14
+#define TCC_EDC_COUNTER__SEC_COUNT_MASK 0xf
+#define TCC_EDC_COUNTER__SEC_COUNT__SHIFT 0x0
+#define TCC_EDC_COUNTER__DED_COUNT_MASK 0xf0000
+#define TCC_EDC_COUNTER__DED_COUNT__SHIFT 0x10
+#define TCC_REDUNDANCY__MC_SEL0_MASK 0x1
+#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0
+#define TCC_REDUNDANCY__MC_SEL1_MASK 0x2
+#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1
+#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
+#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
+#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
+#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
+#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define TCS_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
+#define TCS_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
+#define TCS_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define TCS_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
+#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
+#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000
+#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
+#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000
+#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
+#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
+#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000
+#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
+#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000
+#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
+#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
+#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCA_CTRL__HOLE_TIMEOUT_MASK 0xf
+#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0
+#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
+#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
+#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000
+#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
+#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000
+#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
+#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
+#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000
+#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
+#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000
+#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
+#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
+#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCS_CTRL__RATE_MASK 0x3
+#define TCS_CTRL__RATE__SHIFT 0x0
+#define TCS_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define TCS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TCS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define TCS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define TCS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCS_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define TCS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define TCS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000
+#define TCS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
+#define TCS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000
+#define TCS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define TCS_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define TCS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TCS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCS_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCS_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
+#define TCS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define TCS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCS_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCS_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
+#define TCS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define TCS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCS_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff
+#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
+#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff
+#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
+#define TD_CNTL__SYNC_PHASE_SH_MASK 0x3
+#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0
+#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x30
+#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4
+#define TD_CNTL__PAD_STALL_EN_MASK 0x100
+#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8
+#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x600
+#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9
+#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x1800
+#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb
+#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x8000
+#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf
+#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x10000
+#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10
+#define TD_CNTL__LD_FLOAT_MODE_MASK 0x40000
+#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12
+#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x80000
+#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13
+#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x100000
+#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14
+#define TD_STATUS__BUSY_MASK 0x80000000
+#define TD_STATUS__BUSY__SHIFT 0x1f
+#define TD_DEBUG_INDEX__INDEX_MASK 0x1f
+#define TD_DEBUG_INDEX__INDEX__SHIFT 0x0
+#define TD_DEBUG_DATA__DATA_MASK 0xffffffff
+#define TD_DEBUG_DATA__DATA__SHIFT 0x0
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
+#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00
+#define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
+#define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TD_SCRATCH__SCRATCH_MASK 0xffffffff
+#define TD_SCRATCH__SCRATCH__SHIFT 0x0
+#define TA_CNTL__TC_DATA_CREDIT_MASK 0xe000
+#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd
+#define TA_CNTL__ALIGNER_CREDIT_MASK 0x1f0000
+#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10
+#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xffc00000
+#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16
+#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x1
+#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0
+#define TA_CNTL_AUX__RESERVED_MASK 0xe
+#define TA_CNTL_AUX__RESERVED__SHIFT 0x1
+#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x10000
+#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10
+#define TA_RESERVED_010C__Unused_MASK 0xffffffff
+#define TA_RESERVED_010C__Unused__SHIFT 0x0
+#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff
+#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
+#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff
+#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
+#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x1000
+#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc
+#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x2000
+#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd
+#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x4000
+#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe
+#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x10000
+#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10
+#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x20000
+#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11
+#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x40000
+#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12
+#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x100000
+#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14
+#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x200000
+#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15
+#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x400000
+#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16
+#define TA_STATUS__IN_BUSY_MASK 0x1000000
+#define TA_STATUS__IN_BUSY__SHIFT 0x18
+#define TA_STATUS__FG_BUSY_MASK 0x2000000
+#define TA_STATUS__FG_BUSY__SHIFT 0x19
+#define TA_STATUS__LA_BUSY_MASK 0x4000000
+#define TA_STATUS__LA_BUSY__SHIFT 0x1a
+#define TA_STATUS__FL_BUSY_MASK 0x8000000
+#define TA_STATUS__FL_BUSY__SHIFT 0x1b
+#define TA_STATUS__TA_BUSY_MASK 0x10000000
+#define TA_STATUS__TA_BUSY__SHIFT 0x1c
+#define TA_STATUS__FA_BUSY_MASK 0x20000000
+#define TA_STATUS__FA_BUSY__SHIFT 0x1d
+#define TA_STATUS__AL_BUSY_MASK 0x40000000
+#define TA_STATUS__AL_BUSY__SHIFT 0x1e
+#define TA_STATUS__BUSY_MASK 0x80000000
+#define TA_STATUS__BUSY__SHIFT 0x1f
+#define TA_DEBUG_INDEX__INDEX_MASK 0x1f
+#define TA_DEBUG_INDEX__INDEX__SHIFT 0x0
+#define TA_DEBUG_DATA__DATA_MASK 0xffffffff
+#define TA_DEBUG_DATA__DATA__SHIFT 0x0
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
+#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00
+#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
+#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TA_SCRATCH__SCRATCH_MASK 0xffffffff
+#define TA_SCRATCH__SCRATCH__SHIFT 0x0
+#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS_MASK 0xffffffff
+#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS__SHIFT 0x0
+#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE_MASK 0x1
+#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE__SHIFT 0x0
+#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE_MASK 0x6
+#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE__SHIFT 0x1
+#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE_MASK 0x18
+#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE__SHIFT 0x3
+#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE_MASK 0xe0
+#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE__SHIFT 0x5
+#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL_MASK 0xff00
+#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL__SHIFT 0x8
+#define TCP_INVALIDATE__START_MASK 0x1
+#define TCP_INVALIDATE__START__SHIFT 0x0
+#define TCP_STATUS__TCP_BUSY_MASK 0x1
+#define TCP_STATUS__TCP_BUSY__SHIFT 0x0
+#define TCP_CNTL__FORCE_HIT_MASK 0x1
+#define TCP_CNTL__FORCE_HIT__SHIFT 0x0
+#define TCP_CNTL__FORCE_MISS_MASK 0x2
+#define TCP_CNTL__FORCE_MISS__SHIFT 0x1
+#define TCP_CNTL__L1_SIZE_MASK 0xc
+#define TCP_CNTL__L1_SIZE__SHIFT 0x2
+#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x10
+#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4
+#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x20
+#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5
+#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x1f8000
+#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf
+#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0xfc00000
+#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16
+#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000
+#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c
+#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000
+#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d
+#define TCP_CHAN_STEER_LO__CHAN0_MASK 0xf
+#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0
+#define TCP_CHAN_STEER_LO__CHAN1_MASK 0xf0
+#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4
+#define TCP_CHAN_STEER_LO__CHAN2_MASK 0xf00
+#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8
+#define TCP_CHAN_STEER_LO__CHAN3_MASK 0xf000
+#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc
+#define TCP_CHAN_STEER_LO__CHAN4_MASK 0xf0000
+#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10
+#define TCP_CHAN_STEER_LO__CHAN5_MASK 0xf00000
+#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14
+#define TCP_CHAN_STEER_LO__CHAN6_MASK 0xf000000
+#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18
+#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xf0000000
+#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c
+#define TCP_CHAN_STEER_HI__CHAN8_MASK 0xf
+#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0
+#define TCP_CHAN_STEER_HI__CHAN9_MASK 0xf0
+#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4
+#define TCP_CHAN_STEER_HI__CHANA_MASK 0xf00
+#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8
+#define TCP_CHAN_STEER_HI__CHANB_MASK 0xf000
+#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc
+#define TCP_CHAN_STEER_HI__CHANC_MASK 0xf0000
+#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10
+#define TCP_CHAN_STEER_HI__CHAND_MASK 0xf00000
+#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14
+#define TCP_CHAN_STEER_HI__CHANE_MASK 0xf000000
+#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18
+#define TCP_CHAN_STEER_HI__CHANF_MASK 0xf0000000
+#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c
+#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0xf
+#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0
+#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x30
+#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4
+#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x1c0
+#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6
+#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x200
+#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9
+#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x3ff
+#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0
+#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x7f0000
+#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10
+#define TCP_CREDIT__TD_CREDIT_MASK 0xe0000000
+#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
+#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
+#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x7
+#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0
+#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x700
+#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8
+#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x70000
+#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10
+#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x7000000
+#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18
+#define TCP_EDC_COUNTER__SEC_COUNT_MASK 0xf
+#define TCP_EDC_COUNTER__SEC_COUNT__SHIFT 0x0
+#define TCP_EDC_COUNTER__DED_COUNT_MASK 0xf0000
+#define TCP_EDC_COUNTER__DED_COUNT__SHIFT 0x10
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x3
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0xc
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x30
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0xc0
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x300
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0xc00
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x3000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0xc000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x30000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0xc0000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x300000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0xc00000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x3000000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0xc000000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xc0000000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x3
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0xc
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x30
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0xc0
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x300
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0xc00
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x3000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0xc000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x30000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0xc0000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x300000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0xc00000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x3000000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0xc000000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xc0000000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
+#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x1
+#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0
+#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x2
+#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1
+#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x4
+#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2
+#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x8
+#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3
+#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x10
+#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4
+#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x20
+#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5
+#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x40
+#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6
+#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x80
+#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7
+#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x100
+#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8
+#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x200
+#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9
+#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x400
+#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa
+#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x800
+#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb
+#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x1000
+#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc
+#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x2000
+#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd
+#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x4000
+#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe
+#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x8000
+#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf
+#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x10000
+#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10
+#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x20000
+#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11
+#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x40000
+#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12
+#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x80000
+#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13
+#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x100000
+#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14
+#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x200000
+#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15
+#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x400000
+#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16
+#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x800000
+#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17
+#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x1000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18
+#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x2000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19
+#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x4000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a
+#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x8000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b
+#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c
+#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d
+#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e
+#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x3
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0xc
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x30
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0xc0
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x300
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0xc00
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x3000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0xc000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x30000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0xc0000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x300000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0xc00000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x3000000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0xc000000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xc0000000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x3
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0xc
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x30
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0xc0
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x300
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0xc00
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x3000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0xc000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x30000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0xc0000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x300000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0xc00000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x3000000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0xc000000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xc0000000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
+#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x3
+#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0
+#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0xc
+#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2
+#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x30
+#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4
+#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0xc0
+#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6
+#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x300
+#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8
+#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0xc00
+#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa
+#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x3000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc
+#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0xc000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe
+#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x30000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10
+#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0xc0000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12
+#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x300000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14
+#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0xc00000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16
+#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x3000000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18
+#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0xc000000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a
+#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c
+#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xc0000000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e
+#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x3
+#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0
+#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0xc
+#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2
+#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x30
+#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4
+#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0xc0
+#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6
+#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x300
+#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8
+#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0xc00
+#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa
+#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x3000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc
+#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0xc000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe
+#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x30000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10
+#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0xc0000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12
+#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x300000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14
+#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0xc00000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16
+#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x3000000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18
+#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0xc000000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a
+#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c
+#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xc0000000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x3
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0xc
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x30
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0xc0
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x300
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0xc00
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x3000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0xc000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x30000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0xc0000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x300000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0xc00000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x3000000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0xc000000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xc0000000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e
+#define TC_CFG_L1_VOLATILE__VOL_MASK 0xf
+#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0
+#define TC_CFG_L2_VOLATILE__VOL_MASK 0xf
+#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0
+#define TCP_WATCH0_ADDR_H__ADDR_MASK 0xffff
+#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH1_ADDR_H__ADDR_MASK 0xffff
+#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH2_ADDR_H__ADDR_MASK 0xffff
+#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH3_ADDR_H__ADDR_MASK 0xffff
+#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xffffffc0
+#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6
+#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xffffffc0
+#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6
+#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xffffffc0
+#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6
+#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xffffffc0
+#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6
+#define TCP_WATCH0_CNTL__MASK_MASK 0xffffff
+#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH0_CNTL__VMID_MASK 0xf000000
+#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000
+#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000
+#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f
+#define TCP_WATCH1_CNTL__MASK_MASK 0xffffff
+#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH1_CNTL__VMID_MASK 0xf000000
+#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000
+#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000
+#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f
+#define TCP_WATCH2_CNTL__MASK_MASK 0xffffff
+#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH2_CNTL__VMID_MASK 0xf000000
+#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000
+#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000
+#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f
+#define TCP_WATCH3_CNTL__MASK_MASK 0xffffff
+#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH3_CNTL__VMID_MASK 0xf000000
+#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000
+#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000
+#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f
+#define TD_CGTT_CTRL__ON_DELAY_MASK 0xf
+#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0
+#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define TA_CGTT_CTRL__ON_DELAY_MASK 0xf
+#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0
+#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_TCP_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_TCP_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define TCI_STATUS__TCI_BUSY_MASK 0x1
+#define TCI_STATUS__TCI_BUSY__SHIFT 0x0
+#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0xffff
+#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0
+#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0xff0000
+#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10
+#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xff000000
+#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18
+#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x1
+#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0
+#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x1fe
+#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1
+#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x6
+#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1
+#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x18
+#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3
+#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x60
+#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5
+#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x180
+#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7
+#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x1
+#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0
+#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x2
+#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1
+#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x4
+#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2
+#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x8
+#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3
+#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x10
+#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4
+#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x20
+#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5
+#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x40
+#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6
+#define GDS_ENHANCE2__MISC_MASK 0xffff
+#define GDS_ENHANCE2__MISC__SHIFT 0x0
+#define GDS_ENHANCE2__UNUSED_MASK 0xffff0000
+#define GDS_ENHANCE2__UNUSED__SHIFT 0x10
+#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x1
+#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
+#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2
+#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
+#define GDS_PROTECTION_FAULT__GRBM_MASK 0x4
+#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2
+#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x38
+#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3
+#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x3c0
+#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6
+#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0xc00
+#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa
+#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0xf000
+#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc
+#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000
+#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
+#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x1
+#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
+#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2
+#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
+#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x4
+#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2
+#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x8
+#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3
+#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x10
+#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4
+#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0xf00
+#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8
+#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000
+#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
+#define GDS_SECDED_CNT__DED_MASK 0xffff
+#define GDS_SECDED_CNT__DED__SHIFT 0x0
+#define GDS_SECDED_CNT__SEC_MASK 0xffff0000
+#define GDS_SECDED_CNT__SEC__SHIFT 0x10
+#define GDS_GRBM_SECDED_CNT__DED_MASK 0xffff
+#define GDS_GRBM_SECDED_CNT__DED__SHIFT 0x0
+#define GDS_GRBM_SECDED_CNT__SEC_MASK 0xffff0000
+#define GDS_GRBM_SECDED_CNT__SEC__SHIFT 0x10
+#define GDS_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x1
+#define GDS_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0
+#define GDS_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x2
+#define GDS_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1
+#define GDS_OA_DED__ME0_CS_DED_MASK 0x4
+#define GDS_OA_DED__ME0_CS_DED__SHIFT 0x2
+#define GDS_OA_DED__UNUSED0_MASK 0x8
+#define GDS_OA_DED__UNUSED0__SHIFT 0x3
+#define GDS_OA_DED__ME1_PIPE0_DED_MASK 0x10
+#define GDS_OA_DED__ME1_PIPE0_DED__SHIFT 0x4
+#define GDS_OA_DED__ME1_PIPE1_DED_MASK 0x20
+#define GDS_OA_DED__ME1_PIPE1_DED__SHIFT 0x5
+#define GDS_OA_DED__ME1_PIPE2_DED_MASK 0x40
+#define GDS_OA_DED__ME1_PIPE2_DED__SHIFT 0x6
+#define GDS_OA_DED__ME1_PIPE3_DED_MASK 0x80
+#define GDS_OA_DED__ME1_PIPE3_DED__SHIFT 0x7
+#define GDS_OA_DED__ME2_PIPE0_DED_MASK 0x100
+#define GDS_OA_DED__ME2_PIPE0_DED__SHIFT 0x8
+#define GDS_OA_DED__ME2_PIPE1_DED_MASK 0x200
+#define GDS_OA_DED__ME2_PIPE1_DED__SHIFT 0x9
+#define GDS_OA_DED__ME2_PIPE2_DED_MASK 0x400
+#define GDS_OA_DED__ME2_PIPE2_DED__SHIFT 0xa
+#define GDS_OA_DED__ME2_PIPE3_DED_MASK 0x800
+#define GDS_OA_DED__ME2_PIPE3_DED__SHIFT 0xb
+#define GDS_OA_DED__UNUSED1_MASK 0xfffff000
+#define GDS_OA_DED__UNUSED1__SHIFT 0xc
+#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK 0x1f
+#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT 0x0
+#define GDS_DEBUG_CNTL__UNUSED_MASK 0xffffffe0
+#define GDS_DEBUG_CNTL__UNUSED__SHIFT 0x5
+#define GDS_DEBUG_DATA__DATA_MASK 0xffffffff
+#define GDS_DEBUG_DATA__DATA__SHIFT 0x0
+#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define GDS_RD_ADDR__READ_ADDR_MASK 0xffffffff
+#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0
+#define GDS_RD_DATA__READ_DATA_MASK 0xffffffff
+#define GDS_RD_DATA__READ_DATA__SHIFT 0x0
+#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xffffffff
+#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0
+#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xffffffff
+#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0
+#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xffffffff
+#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0
+#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xffffffff
+#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0
+#define GDS_WR_DATA__WRITE_DATA_MASK 0xffffffff
+#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0
+#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xffffffff
+#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0
+#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xffffffff
+#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0
+#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xffffffff
+#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0
+#define GDS_ATOM_CNTL__AINC_MASK 0x3f
+#define GDS_ATOM_CNTL__AINC__SHIFT 0x0
+#define GDS_ATOM_CNTL__UNUSED1_MASK 0xc0
+#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6
+#define GDS_ATOM_CNTL__DMODE_MASK 0x100
+#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8
+#define GDS_ATOM_CNTL__UNUSED2_MASK 0xfffffe00
+#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0x9
+#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x1
+#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0
+#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xfffffffe
+#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1
+#define GDS_ATOM_BASE__BASE_MASK 0xffff
+#define GDS_ATOM_BASE__BASE__SHIFT 0x0
+#define GDS_ATOM_BASE__UNUSED_MASK 0xffff0000
+#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10
+#define GDS_ATOM_SIZE__SIZE_MASK 0xffff
+#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0
+#define GDS_ATOM_SIZE__UNUSED_MASK 0xffff0000
+#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10
+#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0xff
+#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0
+#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xffffff00
+#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8
+#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0xff
+#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0
+#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xffffff00
+#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8
+#define GDS_ATOM_DST__DST_MASK 0xffffffff
+#define GDS_ATOM_DST__DST__SHIFT 0x0
+#define GDS_ATOM_OP__OP_MASK 0xff
+#define GDS_ATOM_OP__OP__SHIFT 0x0
+#define GDS_ATOM_OP__UNUSED_MASK 0xffffff00
+#define GDS_ATOM_OP__UNUSED__SHIFT 0x8
+#define GDS_ATOM_SRC0__DATA_MASK 0xffffffff
+#define GDS_ATOM_SRC0__DATA__SHIFT 0x0
+#define GDS_ATOM_SRC0_U__DATA_MASK 0xffffffff
+#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0
+#define GDS_ATOM_SRC1__DATA_MASK 0xffffffff
+#define GDS_ATOM_SRC1__DATA__SHIFT 0x0
+#define GDS_ATOM_SRC1_U__DATA_MASK 0xffffffff
+#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0
+#define GDS_ATOM_READ0__DATA_MASK 0xffffffff
+#define GDS_ATOM_READ0__DATA__SHIFT 0x0
+#define GDS_ATOM_READ0_U__DATA_MASK 0xffffffff
+#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0
+#define GDS_ATOM_READ1__DATA_MASK 0xffffffff
+#define GDS_ATOM_READ1__DATA__SHIFT 0x0
+#define GDS_ATOM_READ1_U__DATA_MASK 0xffffffff
+#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0
+#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x3f
+#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0
+#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xffffffc0
+#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6
+#define GDS_GWS_RESOURCE__FLAG_MASK 0x1
+#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0
+#define GDS_GWS_RESOURCE__COUNTER_MASK 0x1ffe
+#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1
+#define GDS_GWS_RESOURCE__TYPE_MASK 0x2000
+#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd
+#define GDS_GWS_RESOURCE__DED_MASK 0x4000
+#define GDS_GWS_RESOURCE__DED__SHIFT 0xe
+#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x8000
+#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf
+#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x7ff0000
+#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10
+#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x8000000
+#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1b
+#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x10000000
+#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1c
+#define GDS_GWS_RESOURCE__UNUSED1_MASK 0xe0000000
+#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1d
+#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0xffff
+#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0
+#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xffff0000
+#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10
+#define GDS_OA_CNTL__INDEX_MASK 0xf
+#define GDS_OA_CNTL__INDEX__SHIFT 0x0
+#define GDS_OA_CNTL__UNUSED_MASK 0xfffffff0
+#define GDS_OA_CNTL__UNUSED__SHIFT 0x4
+#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xffffffff
+#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0
+#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0xffff
+#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0
+#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0xf0000
+#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x10
+#define GDS_OA_ADDRESS__CRAWLER_MASK 0xf00000
+#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x14
+#define GDS_OA_ADDRESS__UNUSED_MASK 0x3f000000
+#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x18
+#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000
+#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e
+#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000
+#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f
+#define GDS_OA_INCDEC__VALUE_MASK 0x7fffffff
+#define GDS_OA_INCDEC__VALUE__SHIFT 0x0
+#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000
+#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f
+#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xffffffff
+#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0
+#define GDS_DEBUG_REG0__spare1_MASK 0x3f
+#define GDS_DEBUG_REG0__spare1__SHIFT 0x0
+#define GDS_DEBUG_REG0__write_buff_valid_MASK 0x40
+#define GDS_DEBUG_REG0__write_buff_valid__SHIFT 0x6
+#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK 0xf80
+#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT 0x7
+#define GDS_DEBUG_REG0__last_pixel_ptr_MASK 0x1000
+#define GDS_DEBUG_REG0__last_pixel_ptr__SHIFT 0xc
+#define GDS_DEBUG_REG0__cstate_MASK 0x1e000
+#define GDS_DEBUG_REG0__cstate__SHIFT 0xd
+#define GDS_DEBUG_REG0__buff_write_MASK 0x20000
+#define GDS_DEBUG_REG0__buff_write__SHIFT 0x11
+#define GDS_DEBUG_REG0__flush_request_MASK 0x40000
+#define GDS_DEBUG_REG0__flush_request__SHIFT 0x12
+#define GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK 0x80000
+#define GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT 0x13
+#define GDS_DEBUG_REG0__wbuf_fifo_empty_MASK 0x100000
+#define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT 0x14
+#define GDS_DEBUG_REG0__wbuf_fifo_full_MASK 0x200000
+#define GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT 0x15
+#define GDS_DEBUG_REG0__spare_MASK 0xffc00000
+#define GDS_DEBUG_REG0__spare__SHIFT 0x16
+#define GDS_DEBUG_REG1__tag_hit_MASK 0x1
+#define GDS_DEBUG_REG1__tag_hit__SHIFT 0x0
+#define GDS_DEBUG_REG1__tag_miss_MASK 0x2
+#define GDS_DEBUG_REG1__tag_miss__SHIFT 0x1
+#define GDS_DEBUG_REG1__pixel_addr_MASK 0x1fffc
+#define GDS_DEBUG_REG1__pixel_addr__SHIFT 0x2
+#define GDS_DEBUG_REG1__pixel_vld_MASK 0x20000
+#define GDS_DEBUG_REG1__pixel_vld__SHIFT 0x11
+#define GDS_DEBUG_REG1__data_ready_MASK 0x40000
+#define GDS_DEBUG_REG1__data_ready__SHIFT 0x12
+#define GDS_DEBUG_REG1__awaiting_data_MASK 0x80000
+#define GDS_DEBUG_REG1__awaiting_data__SHIFT 0x13
+#define GDS_DEBUG_REG1__addr_fifo_full_MASK 0x100000
+#define GDS_DEBUG_REG1__addr_fifo_full__SHIFT 0x14
+#define GDS_DEBUG_REG1__addr_fifo_empty_MASK 0x200000
+#define GDS_DEBUG_REG1__addr_fifo_empty__SHIFT 0x15
+#define GDS_DEBUG_REG1__buffer_loaded_MASK 0x400000
+#define GDS_DEBUG_REG1__buffer_loaded__SHIFT 0x16
+#define GDS_DEBUG_REG1__buffer_invalid_MASK 0x800000
+#define GDS_DEBUG_REG1__buffer_invalid__SHIFT 0x17
+#define GDS_DEBUG_REG1__spare_MASK 0xff000000
+#define GDS_DEBUG_REG1__spare__SHIFT 0x18
+#define GDS_DEBUG_REG2__ds_full_MASK 0x1
+#define GDS_DEBUG_REG2__ds_full__SHIFT 0x0
+#define GDS_DEBUG_REG2__ds_credit_avail_MASK 0x2
+#define GDS_DEBUG_REG2__ds_credit_avail__SHIFT 0x1
+#define GDS_DEBUG_REG2__ord_idx_free_MASK 0x4
+#define GDS_DEBUG_REG2__ord_idx_free__SHIFT 0x2
+#define GDS_DEBUG_REG2__cmd_write_MASK 0x8
+#define GDS_DEBUG_REG2__cmd_write__SHIFT 0x3
+#define GDS_DEBUG_REG2__app_sel_MASK 0xf0
+#define GDS_DEBUG_REG2__app_sel__SHIFT 0x4
+#define GDS_DEBUG_REG2__req_MASK 0x7fff00
+#define GDS_DEBUG_REG2__req__SHIFT 0x8
+#define GDS_DEBUG_REG2__spare_MASK 0xff800000
+#define GDS_DEBUG_REG2__spare__SHIFT 0x17
+#define GDS_DEBUG_REG3__pipe_num_busy_MASK 0x7ff
+#define GDS_DEBUG_REG3__pipe_num_busy__SHIFT 0x0
+#define GDS_DEBUG_REG3__pipe0_busy_num_MASK 0x7800
+#define GDS_DEBUG_REG3__pipe0_busy_num__SHIFT 0xb
+#define GDS_DEBUG_REG3__spare_MASK 0xffff8000
+#define GDS_DEBUG_REG3__spare__SHIFT 0xf
+#define GDS_DEBUG_REG4__gws_busy_MASK 0x1
+#define GDS_DEBUG_REG4__gws_busy__SHIFT 0x0
+#define GDS_DEBUG_REG4__gws_req_MASK 0x2
+#define GDS_DEBUG_REG4__gws_req__SHIFT 0x1
+#define GDS_DEBUG_REG4__gws_out_stall_MASK 0x4
+#define GDS_DEBUG_REG4__gws_out_stall__SHIFT 0x2
+#define GDS_DEBUG_REG4__cur_reso_MASK 0x1f8
+#define GDS_DEBUG_REG4__cur_reso__SHIFT 0x3
+#define GDS_DEBUG_REG4__cur_reso_head_valid_MASK 0x200
+#define GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT 0x9
+#define GDS_DEBUG_REG4__cur_reso_head_dirty_MASK 0x400
+#define GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT 0xa
+#define GDS_DEBUG_REG4__cur_reso_head_flag_MASK 0x800
+#define GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT 0xb
+#define GDS_DEBUG_REG4__cur_reso_fed_MASK 0x1000
+#define GDS_DEBUG_REG4__cur_reso_fed__SHIFT 0xc
+#define GDS_DEBUG_REG4__cur_reso_barrier_MASK 0x2000
+#define GDS_DEBUG_REG4__cur_reso_barrier__SHIFT 0xd
+#define GDS_DEBUG_REG4__cur_reso_flag_MASK 0x4000
+#define GDS_DEBUG_REG4__cur_reso_flag__SHIFT 0xe
+#define GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK 0x8000
+#define GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT 0xf
+#define GDS_DEBUG_REG4__credit_cnt_gt0_MASK 0x10000
+#define GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT 0x10
+#define GDS_DEBUG_REG4__cmd_write_MASK 0x20000
+#define GDS_DEBUG_REG4__cmd_write__SHIFT 0x11
+#define GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK 0x40000
+#define GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT 0x12
+#define GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK 0x80000
+#define GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT 0x13
+#define GDS_DEBUG_REG4__ram_read_busy_MASK 0x100000
+#define GDS_DEBUG_REG4__ram_read_busy__SHIFT 0x14
+#define GDS_DEBUG_REG4__gws_bulkfree_MASK 0x200000
+#define GDS_DEBUG_REG4__gws_bulkfree__SHIFT 0x15
+#define GDS_DEBUG_REG4__ram_gws_re_MASK 0x400000
+#define GDS_DEBUG_REG4__ram_gws_re__SHIFT 0x16
+#define GDS_DEBUG_REG4__ram_gws_we_MASK 0x800000
+#define GDS_DEBUG_REG4__ram_gws_we__SHIFT 0x17
+#define GDS_DEBUG_REG4__spare_MASK 0xff000000
+#define GDS_DEBUG_REG4__spare__SHIFT 0x18
+#define GDS_DEBUG_REG5__write_dis_MASK 0x1
+#define GDS_DEBUG_REG5__write_dis__SHIFT 0x0
+#define GDS_DEBUG_REG5__dec_error_MASK 0x2
+#define GDS_DEBUG_REG5__dec_error__SHIFT 0x1
+#define GDS_DEBUG_REG5__alloc_opco_error_MASK 0x4
+#define GDS_DEBUG_REG5__alloc_opco_error__SHIFT 0x2
+#define GDS_DEBUG_REG5__dealloc_opco_error_MASK 0x8
+#define GDS_DEBUG_REG5__dealloc_opco_error__SHIFT 0x3
+#define GDS_DEBUG_REG5__wrap_opco_error_MASK 0x10
+#define GDS_DEBUG_REG5__wrap_opco_error__SHIFT 0x4
+#define GDS_DEBUG_REG5__spare_MASK 0xe0
+#define GDS_DEBUG_REG5__spare__SHIFT 0x5
+#define GDS_DEBUG_REG5__error_ds_address_MASK 0x3fff00
+#define GDS_DEBUG_REG5__error_ds_address__SHIFT 0x8
+#define GDS_DEBUG_REG5__spare1_MASK 0xffc00000
+#define GDS_DEBUG_REG5__spare1__SHIFT 0x16
+#define GDS_DEBUG_REG6__oa_busy_MASK 0x1
+#define GDS_DEBUG_REG6__oa_busy__SHIFT 0x0
+#define GDS_DEBUG_REG6__counters_enabled_MASK 0x1e
+#define GDS_DEBUG_REG6__counters_enabled__SHIFT 0x1
+#define GDS_DEBUG_REG6__counters_busy_MASK 0x1fffe0
+#define GDS_DEBUG_REG6__counters_busy__SHIFT 0x5
+#define GDS_DEBUG_REG6__spare_MASK 0xffe00000
+#define GDS_DEBUG_REG6__spare__SHIFT 0x15
+#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
+#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
+#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
+#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
+#define GDS_VMID0_BASE__BASE_MASK 0xffff
+#define GDS_VMID0_BASE__BASE__SHIFT 0x0
+#define GDS_VMID1_BASE__BASE_MASK 0xffff
+#define GDS_VMID1_BASE__BASE__SHIFT 0x0
+#define GDS_VMID2_BASE__BASE_MASK 0xffff
+#define GDS_VMID2_BASE__BASE__SHIFT 0x0
+#define GDS_VMID3_BASE__BASE_MASK 0xffff
+#define GDS_VMID3_BASE__BASE__SHIFT 0x0
+#define GDS_VMID4_BASE__BASE_MASK 0xffff
+#define GDS_VMID4_BASE__BASE__SHIFT 0x0
+#define GDS_VMID5_BASE__BASE_MASK 0xffff
+#define GDS_VMID5_BASE__BASE__SHIFT 0x0
+#define GDS_VMID6_BASE__BASE_MASK 0xffff
+#define GDS_VMID6_BASE__BASE__SHIFT 0x0
+#define GDS_VMID7_BASE__BASE_MASK 0xffff
+#define GDS_VMID7_BASE__BASE__SHIFT 0x0
+#define GDS_VMID8_BASE__BASE_MASK 0xffff
+#define GDS_VMID8_BASE__BASE__SHIFT 0x0
+#define GDS_VMID9_BASE__BASE_MASK 0xffff
+#define GDS_VMID9_BASE__BASE__SHIFT 0x0
+#define GDS_VMID10_BASE__BASE_MASK 0xffff
+#define GDS_VMID10_BASE__BASE__SHIFT 0x0
+#define GDS_VMID11_BASE__BASE_MASK 0xffff
+#define GDS_VMID11_BASE__BASE__SHIFT 0x0
+#define GDS_VMID12_BASE__BASE_MASK 0xffff
+#define GDS_VMID12_BASE__BASE__SHIFT 0x0
+#define GDS_VMID13_BASE__BASE_MASK 0xffff
+#define GDS_VMID13_BASE__BASE__SHIFT 0x0
+#define GDS_VMID14_BASE__BASE_MASK 0xffff
+#define GDS_VMID14_BASE__BASE__SHIFT 0x0
+#define GDS_VMID15_BASE__BASE_MASK 0xffff
+#define GDS_VMID15_BASE__BASE__SHIFT 0x0
+#define GDS_VMID0_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID1_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID2_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID3_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID4_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID5_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID6_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID7_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID8_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID9_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID10_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID11_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID12_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID13_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID14_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID15_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0
+#define GDS_GWS_VMID0__BASE_MASK 0x3f
+#define GDS_GWS_VMID0__BASE__SHIFT 0x0
+#define GDS_GWS_VMID0__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID0__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID1__BASE_MASK 0x3f
+#define GDS_GWS_VMID1__BASE__SHIFT 0x0
+#define GDS_GWS_VMID1__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID1__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID2__BASE_MASK 0x3f
+#define GDS_GWS_VMID2__BASE__SHIFT 0x0
+#define GDS_GWS_VMID2__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID2__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID3__BASE_MASK 0x3f
+#define GDS_GWS_VMID3__BASE__SHIFT 0x0
+#define GDS_GWS_VMID3__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID3__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID4__BASE_MASK 0x3f
+#define GDS_GWS_VMID4__BASE__SHIFT 0x0
+#define GDS_GWS_VMID4__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID4__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID5__BASE_MASK 0x3f
+#define GDS_GWS_VMID5__BASE__SHIFT 0x0
+#define GDS_GWS_VMID5__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID5__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID6__BASE_MASK 0x3f
+#define GDS_GWS_VMID6__BASE__SHIFT 0x0
+#define GDS_GWS_VMID6__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID6__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID7__BASE_MASK 0x3f
+#define GDS_GWS_VMID7__BASE__SHIFT 0x0
+#define GDS_GWS_VMID7__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID7__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID8__BASE_MASK 0x3f
+#define GDS_GWS_VMID8__BASE__SHIFT 0x0
+#define GDS_GWS_VMID8__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID8__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID9__BASE_MASK 0x3f
+#define GDS_GWS_VMID9__BASE__SHIFT 0x0
+#define GDS_GWS_VMID9__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID9__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID10__BASE_MASK 0x3f
+#define GDS_GWS_VMID10__BASE__SHIFT 0x0
+#define GDS_GWS_VMID10__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID10__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID11__BASE_MASK 0x3f
+#define GDS_GWS_VMID11__BASE__SHIFT 0x0
+#define GDS_GWS_VMID11__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID11__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID12__BASE_MASK 0x3f
+#define GDS_GWS_VMID12__BASE__SHIFT 0x0
+#define GDS_GWS_VMID12__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID12__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID13__BASE_MASK 0x3f
+#define GDS_GWS_VMID13__BASE__SHIFT 0x0
+#define GDS_GWS_VMID13__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID13__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID14__BASE_MASK 0x3f
+#define GDS_GWS_VMID14__BASE__SHIFT 0x0
+#define GDS_GWS_VMID14__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID14__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID15__BASE_MASK 0x3f
+#define GDS_GWS_VMID15__BASE__SHIFT 0x0
+#define GDS_GWS_VMID15__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID15__SIZE__SHIFT 0x10
+#define GDS_OA_VMID0__MASK_MASK 0xffff
+#define GDS_OA_VMID0__MASK__SHIFT 0x0
+#define GDS_OA_VMID0__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID0__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID1__MASK_MASK 0xffff
+#define GDS_OA_VMID1__MASK__SHIFT 0x0
+#define GDS_OA_VMID1__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID1__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID2__MASK_MASK 0xffff
+#define GDS_OA_VMID2__MASK__SHIFT 0x0
+#define GDS_OA_VMID2__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID2__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID3__MASK_MASK 0xffff
+#define GDS_OA_VMID3__MASK__SHIFT 0x0
+#define GDS_OA_VMID3__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID3__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID4__MASK_MASK 0xffff
+#define GDS_OA_VMID4__MASK__SHIFT 0x0
+#define GDS_OA_VMID4__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID4__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID5__MASK_MASK 0xffff
+#define GDS_OA_VMID5__MASK__SHIFT 0x0
+#define GDS_OA_VMID5__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID5__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID6__MASK_MASK 0xffff
+#define GDS_OA_VMID6__MASK__SHIFT 0x0
+#define GDS_OA_VMID6__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID6__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID7__MASK_MASK 0xffff
+#define GDS_OA_VMID7__MASK__SHIFT 0x0
+#define GDS_OA_VMID7__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID7__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID8__MASK_MASK 0xffff
+#define GDS_OA_VMID8__MASK__SHIFT 0x0
+#define GDS_OA_VMID8__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID8__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID9__MASK_MASK 0xffff
+#define GDS_OA_VMID9__MASK__SHIFT 0x0
+#define GDS_OA_VMID9__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID9__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID10__MASK_MASK 0xffff
+#define GDS_OA_VMID10__MASK__SHIFT 0x0
+#define GDS_OA_VMID10__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID10__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID11__MASK_MASK 0xffff
+#define GDS_OA_VMID11__MASK__SHIFT 0x0
+#define GDS_OA_VMID11__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID11__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID12__MASK_MASK 0xffff
+#define GDS_OA_VMID12__MASK__SHIFT 0x0
+#define GDS_OA_VMID12__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID12__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID13__MASK_MASK 0xffff
+#define GDS_OA_VMID13__MASK__SHIFT 0x0
+#define GDS_OA_VMID13__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID13__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID14__MASK_MASK 0xffff
+#define GDS_OA_VMID14__MASK__SHIFT 0x0
+#define GDS_OA_VMID14__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID14__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID15__MASK_MASK 0xffff
+#define GDS_OA_VMID15__MASK__SHIFT 0x0
+#define GDS_OA_VMID15__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID15__UNUSED__SHIFT 0x10
+#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x1
+#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0
+#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x2
+#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1
+#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x4
+#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2
+#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x8
+#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3
+#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x10
+#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4
+#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x20
+#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5
+#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x40
+#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6
+#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x80
+#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7
+#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x100
+#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8
+#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x200
+#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9
+#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x400
+#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa
+#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x800
+#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb
+#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x1000
+#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc
+#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x2000
+#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd
+#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x4000
+#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe
+#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x8000
+#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf
+#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x10000
+#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10
+#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x20000
+#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11
+#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x40000
+#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12
+#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x80000
+#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13
+#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x100000
+#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14
+#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x200000
+#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15
+#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x400000
+#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16
+#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x800000
+#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17
+#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x1000000
+#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18
+#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x2000000
+#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19
+#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x4000000
+#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a
+#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x8000000
+#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b
+#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000
+#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c
+#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000
+#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d
+#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000
+#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e
+#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000
+#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f
+#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x1
+#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0
+#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x2
+#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1
+#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x4
+#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2
+#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x8
+#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3
+#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x10
+#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4
+#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x20
+#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5
+#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x40
+#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6
+#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x80
+#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7
+#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x100
+#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8
+#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x200
+#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9
+#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x400
+#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa
+#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x800
+#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb
+#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x1000
+#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc
+#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x2000
+#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd
+#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x4000
+#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe
+#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x8000
+#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf
+#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x10000
+#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10
+#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x20000
+#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11
+#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x40000
+#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12
+#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x80000
+#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13
+#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x100000
+#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14
+#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x200000
+#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15
+#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x400000
+#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16
+#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x800000
+#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17
+#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x1000000
+#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18
+#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x2000000
+#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19
+#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x4000000
+#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a
+#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x8000000
+#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b
+#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000
+#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c
+#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000
+#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d
+#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000
+#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e
+#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000
+#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f
+#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x1
+#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0
+#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0xff00
+#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8
+#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
+#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x1
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x2
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1
+#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x4
+#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2
+#define GDS_OA_RESET_MASK__UNUSED0_MASK 0x8
+#define GDS_OA_RESET_MASK__UNUSED0__SHIFT 0x3
+#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x10
+#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4
+#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x20
+#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5
+#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x40
+#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6
+#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x80
+#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7
+#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x100
+#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8
+#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x200
+#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9
+#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x400
+#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa
+#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x800
+#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb
+#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xfffff000
+#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc
+#define GDS_OA_RESET__RESET_MASK 0x1
+#define GDS_OA_RESET__RESET__SHIFT 0x0
+#define GDS_OA_RESET__PIPE_ID_MASK 0xff00
+#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8
+#define GDS_ENHANCE__MISC_MASK 0xffff
+#define GDS_ENHANCE__MISC__SHIFT 0x0
+#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x10000
+#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10
+#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x20000
+#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11
+#define GDS_ENHANCE__UNUSED_MASK 0xfffc0000
+#define GDS_ENHANCE__UNUSED__SHIFT 0x12
+#define GDS_OA_CGPG_RESTORE__VMID_MASK 0xff
+#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0
+#define GDS_OA_CGPG_RESTORE__MEID_MASK 0xf00
+#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8
+#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0xf000
+#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc
+#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xffff0000
+#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x10
+#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x7
+#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
+#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x7
+#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x3
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0
+#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0xc
+#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2
+#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x10
+#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4
+#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x20
+#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5
+#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x40
+#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6
+#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x3f
+#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0
+#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x7fc0000
+#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0x12
+#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x8000000
+#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b
+#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0xfffffff
+#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0
+#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0xff
+#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0
+#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffff
+#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0
+#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x3
+#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
+#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0xc
+#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2
+#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x30
+#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4
+#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0xc0
+#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6
+#define VGT_DMA_INDEX_TYPE__ATC_MASK 0x100
+#define VGT_DMA_INDEX_TYPE__ATC__SHIFT 0x8
+#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x200
+#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9
+#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x400
+#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa
+#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff
+#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
+#define IA_ENHANCE__MISC_MASK 0xffffffff
+#define IA_ENHANCE__MISC__SHIFT 0x0
+#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xffffffff
+#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0
+#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xffffffff
+#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0
+#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f
+#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
+#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0xffff
+#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0
+#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x20000
+#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11
+#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x100000
+#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14
+#define VGT_IMMED_DATA__DATA_MASK 0xffffffff
+#define VGT_IMMED_DATA__DATA__SHIFT 0x0
+#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x3
+#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
+#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xffffffff
+#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0
+#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff
+#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
+#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f
+#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
+#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x1
+#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0
+#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x2
+#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1
+#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xffffffff
+#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0
+#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x1
+#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0
+#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x1
+#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0
+#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xffffffff
+#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0
+#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xffffffff
+#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0
+#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xffffffff
+#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0
+#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xffffffff
+#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0
+#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xffffffff
+#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0xff
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x7f
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xffffffff
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0
+#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x1
+#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0
+#define VGT_ENHANCE__MISC_MASK 0xffffffff
+#define VGT_ENHANCE__MISC__SHIFT 0x0
+#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x7
+#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0
+#define VGT_HOS_CNTL__TESS_MODE_MASK 0x3
+#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0
+#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xffffffff
+#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0
+#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xffffffff
+#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0
+#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0xff
+#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0
+#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x1f
+#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0
+#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x4000
+#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe
+#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x8000
+#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf
+#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x70000
+#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10
+#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0xf
+#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0
+#define VGT_GROUP_DECR__DECR_MASK 0xf
+#define VGT_GROUP_DECR__DECR__SHIFT 0x0
+#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x1
+#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0
+#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x2
+#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1
+#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x4
+#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2
+#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x8
+#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3
+#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0xff00
+#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8
+#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0xff0000
+#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10
+#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x1
+#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0
+#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x2
+#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1
+#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x4
+#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2
+#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x8
+#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3
+#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0xff00
+#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8
+#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0xff0000
+#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0xf
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0xf0
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0xf00
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0xf000
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0xf0000
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0xf00000
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0xf000000
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xf0000000
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0xf
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0xf0
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0xf00
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0xf000
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0xf0000
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0xf00000
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0xf000000
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xf0000000
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x3ff
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0
+#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x1ff
+#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0
+#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x3f
+#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0
+#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x3f
+#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x7
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
+#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x70000
+#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10
+#define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK 0x6
+#define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT 0x1
+#define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8
+#define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
+#define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS_MASK 0x10
+#define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT 0x4
+#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000
+#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
+#define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK 0x6
+#define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT 0x1
+#define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8
+#define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
+#define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS_MASK 0x10
+#define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT 0x4
+#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000
+#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
+#define VGT_GS_MODE__MODE_MASK 0x7
+#define VGT_GS_MODE__MODE__SHIFT 0x0
+#define VGT_GS_MODE__RESERVED_0_MASK 0x8
+#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3
+#define VGT_GS_MODE__CUT_MODE_MASK 0x30
+#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4
+#define VGT_GS_MODE__RESERVED_1_MASK 0x7c0
+#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6
+#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x800
+#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb
+#define VGT_GS_MODE__RESERVED_2_MASK 0x1000
+#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc
+#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x2000
+#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd
+#define VGT_GS_MODE__COMPUTE_MODE_MASK 0x4000
+#define VGT_GS_MODE__COMPUTE_MODE__SHIFT 0xe
+#define VGT_GS_MODE__FAST_COMPUTE_MODE_MASK 0x8000
+#define VGT_GS_MODE__FAST_COMPUTE_MODE__SHIFT 0xf
+#define VGT_GS_MODE__ELEMENT_INFO_EN_MASK 0x10000
+#define VGT_GS_MODE__ELEMENT_INFO_EN__SHIFT 0x10
+#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x20000
+#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11
+#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x40000
+#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12
+#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x80000
+#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13
+#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x100000
+#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14
+#define VGT_GS_MODE__ONCHIP_MASK 0x600000
+#define VGT_GS_MODE__ONCHIP__SHIFT 0x15
+#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x7ff
+#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0
+#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x3ff800
+#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x3f
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x3f00
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x3f0000
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0xfc00000
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16
+#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000
+#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f
+#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x3
+#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0
+#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x20
+#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5
+#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0xc0
+#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6
+#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x200
+#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9
+#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x800
+#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb
+#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x1000
+#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc
+#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x2000
+#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd
+#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x1f0000
+#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10
+#define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x1
+#define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0
+#define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x2
+#define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1
+#define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x4
+#define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2
+#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0xff
+#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0
+#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x700
+#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8
+#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x3800
+#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb
+#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x1c000
+#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe
+#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0xe0000
+#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11
+#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x7f
+#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0
+#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x80
+#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7
+#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x3fff00
+#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8
+#define VGT_FIFO_DEPTHS__RESERVED_1_MASK 0x400000
+#define VGT_FIFO_DEPTHS__RESERVED_1__SHIFT 0x16
+#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x7ff
+#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0
+#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x7ff
+#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0
+#define VGT_GS_PER_VS__GS_PER_VS_MASK 0xf
+#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0
+#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x1f
+#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0
+#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x3
+#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0
+#define IA_CNTL_STATUS__IA_BUSY_MASK 0x1
+#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0
+#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x2
+#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1
+#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x4
+#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2
+#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x8
+#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3
+#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x10
+#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4
+#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x1
+#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0
+#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x2
+#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1
+#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x4
+#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2
+#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x8
+#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3
+#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x70
+#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4
+#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0xf00
+#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8
+#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000
+#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f
+#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x3ff
+#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x3ff
+#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x3ff
+#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x3ff
+#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0xf
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0xf0
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0xf00
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0xf000
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xffffffff
+#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x1ff
+#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0
+#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x7ff
+#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0
+#define IA_VMID_OVERRIDE__ENABLE_MASK 0x1
+#define IA_VMID_OVERRIDE__ENABLE__SHIFT 0x0
+#define IA_VMID_OVERRIDE__VMID_MASK 0x1e
+#define IA_VMID_OVERRIDE__VMID__SHIFT 0x1
+#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x3
+#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0
+#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x4
+#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2
+#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x18
+#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3
+#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x20
+#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5
+#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0xc0
+#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6
+#define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x100
+#define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x8
+#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xffffffff
+#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0
+#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0xff
+#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0
+#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00
+#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
+#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0xfc000
+#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe
+#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00
+#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
+#define VGT_TF_PARAM__TYPE_MASK 0x3
+#define VGT_TF_PARAM__TYPE__SHIFT 0x0
+#define VGT_TF_PARAM__PARTITIONING_MASK 0x1c
+#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2
+#define VGT_TF_PARAM__TOPOLOGY_MASK 0xe0
+#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5
+#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x100
+#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8
+#define VGT_TF_PARAM__DEPRECATED_MASK 0x200
+#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9
+#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x3c00
+#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0xa
+#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x4000
+#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe
+#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x18000
+#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf
+#define VGT_TF_RING_SIZE__SIZE_MASK 0xffff
+#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0
+#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x1
+#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0
+#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x7e
+#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1
+#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x80
+#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x1ff
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x600
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9
+#define VGT_TF_MEMORY_BASE__BASE_MASK 0xffffffff
+#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0
+#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x1
+#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0
+#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x1fc
+#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2
+#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0xffff
+#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0
+#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x10000
+#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x20000
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11
+#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x40000
+#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x80000
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13
+#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x100000
+#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14
+#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
+#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
+#define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xffffffff
+#define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x0
+#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffff
+#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0
+#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x7fff
+#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0
+#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x7fff
+#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0
+#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x7fff
+#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0
+#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff
+#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
+#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff
+#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x7fff
+#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x7fff
+#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x7fff
+#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x7fff
+#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0
+#define WD_CNTL_STATUS__WD_BUSY_MASK 0x1
+#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0
+#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x2
+#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1
+#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x4
+#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2
+#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x8
+#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3
+#define WD_ENHANCE__MISC_MASK 0xffffffff
+#define WD_ENHANCE__MISC__SHIFT 0x0
+#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x1fff
+#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0
+#define GFX_PIPE_CONTROL__RESERVED_MASK 0xe000
+#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd
+#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x10000
+#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10
+#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT_MASK 0x1
+#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT__SHIFT 0x0
+#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
+#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
+#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
+#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000
+#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d
+#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
+#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
+#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
+#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
+#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
+#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
+#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
+#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
+#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
+#define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
+#define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
+#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_WD_CLK_CTRL__ADC_OVERRIDE_MASK 0x10000000
+#define CGTT_WD_CLK_CTRL__ADC_OVERRIDE__SHIFT 0x1c
+#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000
+#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d
+#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000
+#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e
+#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x3f
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x0
+#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B_MASK 0x40
+#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B__SHIFT 0x6
+#define VGT_DEBUG_DATA__DATA_MASK 0xffffffff
+#define VGT_DEBUG_DATA__DATA__SHIFT 0x0
+#define IA_DEBUG_CNTL__IA_DEBUG_INDX_MASK 0x3f
+#define IA_DEBUG_CNTL__IA_DEBUG_INDX__SHIFT 0x0
+#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B_MASK 0x40
+#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B__SHIFT 0x6
+#define IA_DEBUG_DATA__DATA_MASK 0xffffffff
+#define IA_DEBUG_DATA__DATA__SHIFT 0x0
+#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x1
+#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x2
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x4
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2
+#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x8
+#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3
+#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x10
+#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4
+#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x20
+#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5
+#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x40
+#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6
+#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x80
+#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7
+#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x100
+#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8
+#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x200
+#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9
+#define WD_DEBUG_CNTL__WD_DEBUG_INDX_MASK 0x3f
+#define WD_DEBUG_CNTL__WD_DEBUG_INDX__SHIFT 0x0
+#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B_MASK 0x40
+#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B__SHIFT 0x6
+#define WD_DEBUG_DATA__DATA_MASK 0xffffffff
+#define WD_DEBUG_DATA__DATA__SHIFT 0x0
+#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000
+#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
+#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000
+#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
+#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000
+#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
+#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000
+#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
+#define WD_DEBUG_REG0__wd_busy_extended_MASK 0x1
+#define WD_DEBUG_REG0__wd_busy_extended__SHIFT 0x0
+#define WD_DEBUG_REG0__wd_nodma_busy_extended_MASK 0x2
+#define WD_DEBUG_REG0__wd_nodma_busy_extended__SHIFT 0x1
+#define WD_DEBUG_REG0__wd_busy_MASK 0x4
+#define WD_DEBUG_REG0__wd_busy__SHIFT 0x2
+#define WD_DEBUG_REG0__wd_nodma_busy_MASK 0x8
+#define WD_DEBUG_REG0__wd_nodma_busy__SHIFT 0x3
+#define WD_DEBUG_REG0__rbiu_busy_MASK 0x10
+#define WD_DEBUG_REG0__rbiu_busy__SHIFT 0x4
+#define WD_DEBUG_REG0__spl_dma_busy_MASK 0x20
+#define WD_DEBUG_REG0__spl_dma_busy__SHIFT 0x5
+#define WD_DEBUG_REG0__spl_di_busy_MASK 0x40
+#define WD_DEBUG_REG0__spl_di_busy__SHIFT 0x6
+#define WD_DEBUG_REG0__vgt0_active_q_MASK 0x80
+#define WD_DEBUG_REG0__vgt0_active_q__SHIFT 0x7
+#define WD_DEBUG_REG0__vgt1_active_q_MASK 0x100
+#define WD_DEBUG_REG0__vgt1_active_q__SHIFT 0x8
+#define WD_DEBUG_REG0__spl_dma_p1_busy_MASK 0x200
+#define WD_DEBUG_REG0__spl_dma_p1_busy__SHIFT 0x9
+#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy_MASK 0x400
+#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy__SHIFT 0xa
+#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy_MASK 0x800
+#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy__SHIFT 0xb
+#define WD_DEBUG_REG0__SPARE2_MASK 0x1000
+#define WD_DEBUG_REG0__SPARE2__SHIFT 0xc
+#define WD_DEBUG_REG0__rbiu_dr_fifo_busy_MASK 0x2000
+#define WD_DEBUG_REG0__rbiu_dr_fifo_busy__SHIFT 0xd
+#define WD_DEBUG_REG0__rbiu_spl_dr_valid_MASK 0x4000
+#define WD_DEBUG_REG0__rbiu_spl_dr_valid__SHIFT 0xe
+#define WD_DEBUG_REG0__spl_rbiu_dr_read_MASK 0x8000
+#define WD_DEBUG_REG0__spl_rbiu_dr_read__SHIFT 0xf
+#define WD_DEBUG_REG0__SPARE3_MASK 0x10000
+#define WD_DEBUG_REG0__SPARE3__SHIFT 0x10
+#define WD_DEBUG_REG0__rbiu_di_fifo_busy_MASK 0x20000
+#define WD_DEBUG_REG0__rbiu_di_fifo_busy__SHIFT 0x11
+#define WD_DEBUG_REG0__rbiu_spl_di_valid_MASK 0x40000
+#define WD_DEBUG_REG0__rbiu_spl_di_valid__SHIFT 0x12
+#define WD_DEBUG_REG0__spl_rbiu_di_read_MASK 0x80000
+#define WD_DEBUG_REG0__spl_rbiu_di_read__SHIFT 0x13
+#define WD_DEBUG_REG0__se0_synced_q_MASK 0x100000
+#define WD_DEBUG_REG0__se0_synced_q__SHIFT 0x14
+#define WD_DEBUG_REG0__se1_synced_q_MASK 0x200000
+#define WD_DEBUG_REG0__se1_synced_q__SHIFT 0x15
+#define WD_DEBUG_REG0__se2_synced_q_MASK 0x400000
+#define WD_DEBUG_REG0__se2_synced_q__SHIFT 0x16
+#define WD_DEBUG_REG0__se3_synced_q_MASK 0x800000
+#define WD_DEBUG_REG0__se3_synced_q__SHIFT 0x17
+#define WD_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
+#define WD_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
+#define WD_DEBUG_REG0__input_clk_busy_MASK 0x2000000
+#define WD_DEBUG_REG0__input_clk_busy__SHIFT 0x19
+#define WD_DEBUG_REG0__core_clk_busy_MASK 0x4000000
+#define WD_DEBUG_REG0__core_clk_busy__SHIFT 0x1a
+#define WD_DEBUG_REG0__vgt2_active_q_MASK 0x8000000
+#define WD_DEBUG_REG0__vgt2_active_q__SHIFT 0x1b
+#define WD_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000
+#define WD_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c
+#define WD_DEBUG_REG0__sclk_input_vld_MASK 0x20000000
+#define WD_DEBUG_REG0__sclk_input_vld__SHIFT 0x1d
+#define WD_DEBUG_REG0__sclk_core_vld_MASK 0x40000000
+#define WD_DEBUG_REG0__sclk_core_vld__SHIFT 0x1e
+#define WD_DEBUG_REG0__vgt3_active_q_MASK 0x80000000
+#define WD_DEBUG_REG0__vgt3_active_q__SHIFT 0x1f
+#define WD_DEBUG_REG1__grbm_fifo_empty_MASK 0x1
+#define WD_DEBUG_REG1__grbm_fifo_empty__SHIFT 0x0
+#define WD_DEBUG_REG1__grbm_fifo_full_MASK 0x2
+#define WD_DEBUG_REG1__grbm_fifo_full__SHIFT 0x1
+#define WD_DEBUG_REG1__grbm_fifo_we_MASK 0x4
+#define WD_DEBUG_REG1__grbm_fifo_we__SHIFT 0x2
+#define WD_DEBUG_REG1__grbm_fifo_re_MASK 0x8
+#define WD_DEBUG_REG1__grbm_fifo_re__SHIFT 0x3
+#define WD_DEBUG_REG1__draw_initiator_valid_q_MASK 0x10
+#define WD_DEBUG_REG1__draw_initiator_valid_q__SHIFT 0x4
+#define WD_DEBUG_REG1__event_initiator_valid_q_MASK 0x20
+#define WD_DEBUG_REG1__event_initiator_valid_q__SHIFT 0x5
+#define WD_DEBUG_REG1__event_addr_valid_q_MASK 0x40
+#define WD_DEBUG_REG1__event_addr_valid_q__SHIFT 0x6
+#define WD_DEBUG_REG1__dma_request_valid_q_MASK 0x80
+#define WD_DEBUG_REG1__dma_request_valid_q__SHIFT 0x7
+#define WD_DEBUG_REG1__SPARE0_MASK 0x100
+#define WD_DEBUG_REG1__SPARE0__SHIFT 0x8
+#define WD_DEBUG_REG1__min_indx_valid_q_MASK 0x200
+#define WD_DEBUG_REG1__min_indx_valid_q__SHIFT 0x9
+#define WD_DEBUG_REG1__max_indx_valid_q_MASK 0x400
+#define WD_DEBUG_REG1__max_indx_valid_q__SHIFT 0xa
+#define WD_DEBUG_REG1__indx_offset_valid_q_MASK 0x800
+#define WD_DEBUG_REG1__indx_offset_valid_q__SHIFT 0xb
+#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id_MASK 0x1f000
+#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id__SHIFT 0xc
+#define WD_DEBUG_REG1__grbm_fifo_rdata_state_MASK 0xe0000
+#define WD_DEBUG_REG1__grbm_fifo_rdata_state__SHIFT 0x11
+#define WD_DEBUG_REG1__free_cnt_q_MASK 0x3f00000
+#define WD_DEBUG_REG1__free_cnt_q__SHIFT 0x14
+#define WD_DEBUG_REG1__rbiu_di_fifo_we_MASK 0x4000000
+#define WD_DEBUG_REG1__rbiu_di_fifo_we__SHIFT 0x1a
+#define WD_DEBUG_REG1__rbiu_dr_fifo_we_MASK 0x8000000
+#define WD_DEBUG_REG1__rbiu_dr_fifo_we__SHIFT 0x1b
+#define WD_DEBUG_REG1__rbiu_di_fifo_empty_MASK 0x10000000
+#define WD_DEBUG_REG1__rbiu_di_fifo_empty__SHIFT 0x1c
+#define WD_DEBUG_REG1__rbiu_di_fifo_full_MASK 0x20000000
+#define WD_DEBUG_REG1__rbiu_di_fifo_full__SHIFT 0x1d
+#define WD_DEBUG_REG1__rbiu_dr_fifo_empty_MASK 0x40000000
+#define WD_DEBUG_REG1__rbiu_dr_fifo_empty__SHIFT 0x1e
+#define WD_DEBUG_REG1__rbiu_dr_fifo_full_MASK 0x80000000
+#define WD_DEBUG_REG1__rbiu_dr_fifo_full__SHIFT 0x1f
+#define WD_DEBUG_REG2__p1_grbm_fifo_empty_MASK 0x1
+#define WD_DEBUG_REG2__p1_grbm_fifo_empty__SHIFT 0x0
+#define WD_DEBUG_REG2__p1_grbm_fifo_full_MASK 0x2
+#define WD_DEBUG_REG2__p1_grbm_fifo_full__SHIFT 0x1
+#define WD_DEBUG_REG2__p1_grbm_fifo_we_MASK 0x4
+#define WD_DEBUG_REG2__p1_grbm_fifo_we__SHIFT 0x2
+#define WD_DEBUG_REG2__p1_grbm_fifo_re_MASK 0x8
+#define WD_DEBUG_REG2__p1_grbm_fifo_re__SHIFT 0x3
+#define WD_DEBUG_REG2__p1_draw_initiator_valid_q_MASK 0x10
+#define WD_DEBUG_REG2__p1_draw_initiator_valid_q__SHIFT 0x4
+#define WD_DEBUG_REG2__p1_event_initiator_valid_q_MASK 0x20
+#define WD_DEBUG_REG2__p1_event_initiator_valid_q__SHIFT 0x5
+#define WD_DEBUG_REG2__p1_event_addr_valid_q_MASK 0x40
+#define WD_DEBUG_REG2__p1_event_addr_valid_q__SHIFT 0x6
+#define WD_DEBUG_REG2__p1_dma_request_valid_q_MASK 0x80
+#define WD_DEBUG_REG2__p1_dma_request_valid_q__SHIFT 0x7
+#define WD_DEBUG_REG2__SPARE0_MASK 0x100
+#define WD_DEBUG_REG2__SPARE0__SHIFT 0x8
+#define WD_DEBUG_REG2__p1_min_indx_valid_q_MASK 0x200
+#define WD_DEBUG_REG2__p1_min_indx_valid_q__SHIFT 0x9
+#define WD_DEBUG_REG2__p1_max_indx_valid_q_MASK 0x400
+#define WD_DEBUG_REG2__p1_max_indx_valid_q__SHIFT 0xa
+#define WD_DEBUG_REG2__p1_indx_offset_valid_q_MASK 0x800
+#define WD_DEBUG_REG2__p1_indx_offset_valid_q__SHIFT 0xb
+#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id_MASK 0x1f000
+#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id__SHIFT 0xc
+#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state_MASK 0xe0000
+#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state__SHIFT 0x11
+#define WD_DEBUG_REG2__p1_free_cnt_q_MASK 0x3f00000
+#define WD_DEBUG_REG2__p1_free_cnt_q__SHIFT 0x14
+#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we_MASK 0x4000000
+#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we__SHIFT 0x1a
+#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we_MASK 0x8000000
+#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we__SHIFT 0x1b
+#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty_MASK 0x10000000
+#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty__SHIFT 0x1c
+#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full_MASK 0x20000000
+#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full__SHIFT 0x1d
+#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty_MASK 0x40000000
+#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty__SHIFT 0x1e
+#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full_MASK 0x80000000
+#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full__SHIFT 0x1f
+#define WD_DEBUG_REG3__rbiu_spl_dr_valid_MASK 0x1
+#define WD_DEBUG_REG3__rbiu_spl_dr_valid__SHIFT 0x0
+#define WD_DEBUG_REG3__SPARE0_MASK 0x2
+#define WD_DEBUG_REG3__SPARE0__SHIFT 0x1
+#define WD_DEBUG_REG3__pipe0_dr_MASK 0x4
+#define WD_DEBUG_REG3__pipe0_dr__SHIFT 0x2
+#define WD_DEBUG_REG3__pipe0_rtr_MASK 0x8
+#define WD_DEBUG_REG3__pipe0_rtr__SHIFT 0x3
+#define WD_DEBUG_REG3__pipe1_dr_MASK 0x10
+#define WD_DEBUG_REG3__pipe1_dr__SHIFT 0x4
+#define WD_DEBUG_REG3__pipe1_rtr_MASK 0x20
+#define WD_DEBUG_REG3__pipe1_rtr__SHIFT 0x5
+#define WD_DEBUG_REG3__wd_subdma_fifo_empty_MASK 0x40
+#define WD_DEBUG_REG3__wd_subdma_fifo_empty__SHIFT 0x6
+#define WD_DEBUG_REG3__wd_subdma_fifo_full_MASK 0x80
+#define WD_DEBUG_REG3__wd_subdma_fifo_full__SHIFT 0x7
+#define WD_DEBUG_REG3__dma_buf_type_p0_q_MASK 0x300
+#define WD_DEBUG_REG3__dma_buf_type_p0_q__SHIFT 0x8
+#define WD_DEBUG_REG3__dma_zero_indices_p0_q_MASK 0x400
+#define WD_DEBUG_REG3__dma_zero_indices_p0_q__SHIFT 0xa
+#define WD_DEBUG_REG3__dma_req_path_p3_q_MASK 0x800
+#define WD_DEBUG_REG3__dma_req_path_p3_q__SHIFT 0xb
+#define WD_DEBUG_REG3__dma_not_eop_p1_q_MASK 0x1000
+#define WD_DEBUG_REG3__dma_not_eop_p1_q__SHIFT 0xc
+#define WD_DEBUG_REG3__out_of_range_p4_MASK 0x2000
+#define WD_DEBUG_REG3__out_of_range_p4__SHIFT 0xd
+#define WD_DEBUG_REG3__last_sub_dma_p3_q_MASK 0x4000
+#define WD_DEBUG_REG3__last_sub_dma_p3_q__SHIFT 0xe
+#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4_MASK 0x8000
+#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4__SHIFT 0xf
+#define WD_DEBUG_REG3__WD_IA_dma_send_d_MASK 0x10000
+#define WD_DEBUG_REG3__WD_IA_dma_send_d__SHIFT 0x10
+#define WD_DEBUG_REG3__WD_IA_dma_rtr_MASK 0x20000
+#define WD_DEBUG_REG3__WD_IA_dma_rtr__SHIFT 0x11
+#define WD_DEBUG_REG3__WD_IA1_dma_send_d_MASK 0x40000
+#define WD_DEBUG_REG3__WD_IA1_dma_send_d__SHIFT 0x12
+#define WD_DEBUG_REG3__WD_IA1_dma_rtr_MASK 0x80000
+#define WD_DEBUG_REG3__WD_IA1_dma_rtr__SHIFT 0x13
+#define WD_DEBUG_REG3__last_inst_of_dma_p2_MASK 0x100000
+#define WD_DEBUG_REG3__last_inst_of_dma_p2__SHIFT 0x14
+#define WD_DEBUG_REG3__last_sd_of_inst_p2_MASK 0x200000
+#define WD_DEBUG_REG3__last_sd_of_inst_p2__SHIFT 0x15
+#define WD_DEBUG_REG3__last_sd_of_dma_p2_MASK 0x400000
+#define WD_DEBUG_REG3__last_sd_of_dma_p2__SHIFT 0x16
+#define WD_DEBUG_REG3__SPARE1_MASK 0x800000
+#define WD_DEBUG_REG3__SPARE1__SHIFT 0x17
+#define WD_DEBUG_REG3__WD_IA_dma_busy_MASK 0x1000000
+#define WD_DEBUG_REG3__WD_IA_dma_busy__SHIFT 0x18
+#define WD_DEBUG_REG3__WD_IA1_dma_busy_MASK 0x2000000
+#define WD_DEBUG_REG3__WD_IA1_dma_busy__SHIFT 0x19
+#define WD_DEBUG_REG3__send_to_ia1_p3_q_MASK 0x4000000
+#define WD_DEBUG_REG3__send_to_ia1_p3_q__SHIFT 0x1a
+#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q_MASK 0x8000000
+#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q__SHIFT 0x1b
+#define WD_DEBUG_REG3__pipe3_dr_MASK 0x10000000
+#define WD_DEBUG_REG3__pipe3_dr__SHIFT 0x1c
+#define WD_DEBUG_REG3__pipe3_rtr_MASK 0x20000000
+#define WD_DEBUG_REG3__pipe3_rtr__SHIFT 0x1d
+#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty_MASK 0x40000000
+#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty__SHIFT 0x1e
+#define WD_DEBUG_REG3__wd_dma2draw_fifo_full_MASK 0x80000000
+#define WD_DEBUG_REG3__wd_dma2draw_fifo_full__SHIFT 0x1f
+#define WD_DEBUG_REG4__rbiu_spl_di_valid_MASK 0x1
+#define WD_DEBUG_REG4__rbiu_spl_di_valid__SHIFT 0x0
+#define WD_DEBUG_REG4__spl_rbiu_di_read_MASK 0x2
+#define WD_DEBUG_REG4__spl_rbiu_di_read__SHIFT 0x1
+#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid_MASK 0x4
+#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid__SHIFT 0x2
+#define WD_DEBUG_REG4__spl_rbiu_p1_di_read_MASK 0x8
+#define WD_DEBUG_REG4__spl_rbiu_p1_di_read__SHIFT 0x3
+#define WD_DEBUG_REG4__pipe0_dr_MASK 0x10
+#define WD_DEBUG_REG4__pipe0_dr__SHIFT 0x4
+#define WD_DEBUG_REG4__pipe0_rtr_MASK 0x20
+#define WD_DEBUG_REG4__pipe0_rtr__SHIFT 0x5
+#define WD_DEBUG_REG4__pipe1_dr_MASK 0x40
+#define WD_DEBUG_REG4__pipe1_dr__SHIFT 0x6
+#define WD_DEBUG_REG4__pipe1_rtr_MASK 0x80
+#define WD_DEBUG_REG4__pipe1_rtr__SHIFT 0x7
+#define WD_DEBUG_REG4__pipe2_dr_MASK 0x100
+#define WD_DEBUG_REG4__pipe2_dr__SHIFT 0x8
+#define WD_DEBUG_REG4__pipe2_rtr_MASK 0x200
+#define WD_DEBUG_REG4__pipe2_rtr__SHIFT 0x9
+#define WD_DEBUG_REG4__pipe3_ld_MASK 0x400
+#define WD_DEBUG_REG4__pipe3_ld__SHIFT 0xa
+#define WD_DEBUG_REG4__pipe3_rtr_MASK 0x800
+#define WD_DEBUG_REG4__pipe3_rtr__SHIFT 0xb
+#define WD_DEBUG_REG4__WD_IA_draw_send_d_MASK 0x1000
+#define WD_DEBUG_REG4__WD_IA_draw_send_d__SHIFT 0xc
+#define WD_DEBUG_REG4__WD_IA_draw_rtr_MASK 0x2000
+#define WD_DEBUG_REG4__WD_IA_draw_rtr__SHIFT 0xd
+#define WD_DEBUG_REG4__di_type_p0_MASK 0xc000
+#define WD_DEBUG_REG4__di_type_p0__SHIFT 0xe
+#define WD_DEBUG_REG4__di_state_sel_p1_q_MASK 0x70000
+#define WD_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x10
+#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q_MASK 0x80000
+#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q__SHIFT 0x13
+#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout_MASK 0x100000
+#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout__SHIFT 0x14
+#define WD_DEBUG_REG4__last_inst_of_di_p2_MASK 0x200000
+#define WD_DEBUG_REG4__last_inst_of_di_p2__SHIFT 0x15
+#define WD_DEBUG_REG4__last_sd_of_inst_p2_MASK 0x400000
+#define WD_DEBUG_REG4__last_sd_of_inst_p2__SHIFT 0x16
+#define WD_DEBUG_REG4__last_sd_of_di_p2_MASK 0x800000
+#define WD_DEBUG_REG4__last_sd_of_di_p2__SHIFT 0x17
+#define WD_DEBUG_REG4__not_eop_wait_p1_q_MASK 0x1000000
+#define WD_DEBUG_REG4__not_eop_wait_p1_q__SHIFT 0x18
+#define WD_DEBUG_REG4__not_eop_wait_q_MASK 0x2000000
+#define WD_DEBUG_REG4__not_eop_wait_q__SHIFT 0x19
+#define WD_DEBUG_REG4__ext_event_wait_p1_q_MASK 0x4000000
+#define WD_DEBUG_REG4__ext_event_wait_p1_q__SHIFT 0x1a
+#define WD_DEBUG_REG4__ext_event_wait_q_MASK 0x8000000
+#define WD_DEBUG_REG4__ext_event_wait_q__SHIFT 0x1b
+#define WD_DEBUG_REG4__WD_IA1_draw_send_d_MASK 0x10000000
+#define WD_DEBUG_REG4__WD_IA1_draw_send_d__SHIFT 0x1c
+#define WD_DEBUG_REG4__WD_IA1_draw_rtr_MASK 0x20000000
+#define WD_DEBUG_REG4__WD_IA1_draw_rtr__SHIFT 0x1d
+#define WD_DEBUG_REG4__send_to_ia1_q_MASK 0x40000000
+#define WD_DEBUG_REG4__send_to_ia1_q__SHIFT 0x1e
+#define WD_DEBUG_REG4__dual_ia_mode_MASK 0x80000000
+#define WD_DEBUG_REG4__dual_ia_mode__SHIFT 0x1f
+#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid_MASK 0x1
+#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid__SHIFT 0x0
+#define WD_DEBUG_REG5__SPARE0_MASK 0x2
+#define WD_DEBUG_REG5__SPARE0__SHIFT 0x1
+#define WD_DEBUG_REG5__p1_pipe0_dr_MASK 0x4
+#define WD_DEBUG_REG5__p1_pipe0_dr__SHIFT 0x2
+#define WD_DEBUG_REG5__p1_pipe0_rtr_MASK 0x8
+#define WD_DEBUG_REG5__p1_pipe0_rtr__SHIFT 0x3
+#define WD_DEBUG_REG5__p1_pipe1_dr_MASK 0x10
+#define WD_DEBUG_REG5__p1_pipe1_dr__SHIFT 0x4
+#define WD_DEBUG_REG5__p1_pipe1_rtr_MASK 0x20
+#define WD_DEBUG_REG5__p1_pipe1_rtr__SHIFT 0x5
+#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty_MASK 0x40
+#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty__SHIFT 0x6
+#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full_MASK 0x80
+#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full__SHIFT 0x7
+#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q_MASK 0x300
+#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q__SHIFT 0x8
+#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q_MASK 0x400
+#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q__SHIFT 0xa
+#define WD_DEBUG_REG5__p1_dma_req_path_p3_q_MASK 0x800
+#define WD_DEBUG_REG5__p1_dma_req_path_p3_q__SHIFT 0xb
+#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q_MASK 0x1000
+#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q__SHIFT 0xc
+#define WD_DEBUG_REG5__p1_out_of_range_p4_MASK 0x2000
+#define WD_DEBUG_REG5__p1_out_of_range_p4__SHIFT 0xd
+#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q_MASK 0x4000
+#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q__SHIFT 0xe
+#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4_MASK 0x8000
+#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4__SHIFT 0xf
+#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d_MASK 0x10000
+#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d__SHIFT 0x10
+#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr_MASK 0x20000
+#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr__SHIFT 0x11
+#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d_MASK 0x40000
+#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d__SHIFT 0x12
+#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr_MASK 0x80000
+#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr__SHIFT 0x13
+#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2_MASK 0x100000
+#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2__SHIFT 0x14
+#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2_MASK 0x200000
+#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2__SHIFT 0x15
+#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2_MASK 0x400000
+#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2__SHIFT 0x16
+#define WD_DEBUG_REG5__SPARE1_MASK 0x800000
+#define WD_DEBUG_REG5__SPARE1__SHIFT 0x17
+#define WD_DEBUG_REG5__p1_WD_IA_dma_busy_MASK 0x1000000
+#define WD_DEBUG_REG5__p1_WD_IA_dma_busy__SHIFT 0x18
+#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy_MASK 0x2000000
+#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy__SHIFT 0x19
+#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q_MASK 0x4000000
+#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q__SHIFT 0x1a
+#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q_MASK 0x8000000
+#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q__SHIFT 0x1b
+#define WD_DEBUG_REG5__p1_pipe3_dr_MASK 0x10000000
+#define WD_DEBUG_REG5__p1_pipe3_dr__SHIFT 0x1c
+#define WD_DEBUG_REG5__p1_pipe3_rtr_MASK 0x20000000
+#define WD_DEBUG_REG5__p1_pipe3_rtr__SHIFT 0x1d
+#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty_MASK 0x40000000
+#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty__SHIFT 0x1e
+#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full_MASK 0x80000000
+#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full__SHIFT 0x1f
+#define IA_DEBUG_REG0__ia_busy_extended_MASK 0x1
+#define IA_DEBUG_REG0__ia_busy_extended__SHIFT 0x0
+#define IA_DEBUG_REG0__ia_nodma_busy_extended_MASK 0x2
+#define IA_DEBUG_REG0__ia_nodma_busy_extended__SHIFT 0x1
+#define IA_DEBUG_REG0__ia_busy_MASK 0x4
+#define IA_DEBUG_REG0__ia_busy__SHIFT 0x2
+#define IA_DEBUG_REG0__ia_nodma_busy_MASK 0x8
+#define IA_DEBUG_REG0__ia_nodma_busy__SHIFT 0x3
+#define IA_DEBUG_REG0__SPARE0_MASK 0x10
+#define IA_DEBUG_REG0__SPARE0__SHIFT 0x4
+#define IA_DEBUG_REG0__dma_req_busy_MASK 0x20
+#define IA_DEBUG_REG0__dma_req_busy__SHIFT 0x5
+#define IA_DEBUG_REG0__dma_busy_MASK 0x40
+#define IA_DEBUG_REG0__dma_busy__SHIFT 0x6
+#define IA_DEBUG_REG0__mc_xl8r_busy_MASK 0x80
+#define IA_DEBUG_REG0__mc_xl8r_busy__SHIFT 0x7
+#define IA_DEBUG_REG0__grp_busy_MASK 0x100
+#define IA_DEBUG_REG0__grp_busy__SHIFT 0x8
+#define IA_DEBUG_REG0__SPARE1_MASK 0x200
+#define IA_DEBUG_REG0__SPARE1__SHIFT 0x9
+#define IA_DEBUG_REG0__dma_grp_valid_MASK 0x400
+#define IA_DEBUG_REG0__dma_grp_valid__SHIFT 0xa
+#define IA_DEBUG_REG0__grp_dma_read_MASK 0x800
+#define IA_DEBUG_REG0__grp_dma_read__SHIFT 0xb
+#define IA_DEBUG_REG0__dma_grp_hp_valid_MASK 0x1000
+#define IA_DEBUG_REG0__dma_grp_hp_valid__SHIFT 0xc
+#define IA_DEBUG_REG0__grp_dma_hp_read_MASK 0x2000
+#define IA_DEBUG_REG0__grp_dma_hp_read__SHIFT 0xd
+#define IA_DEBUG_REG0__SPARE2_MASK 0xffc000
+#define IA_DEBUG_REG0__SPARE2__SHIFT 0xe
+#define IA_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
+#define IA_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
+#define IA_DEBUG_REG0__core_clk_busy_MASK 0x2000000
+#define IA_DEBUG_REG0__core_clk_busy__SHIFT 0x19
+#define IA_DEBUG_REG0__SPARE3_MASK 0x4000000
+#define IA_DEBUG_REG0__SPARE3__SHIFT 0x1a
+#define IA_DEBUG_REG0__SPARE4_MASK 0x8000000
+#define IA_DEBUG_REG0__SPARE4__SHIFT 0x1b
+#define IA_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000
+#define IA_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c
+#define IA_DEBUG_REG0__sclk_core_vld_MASK 0x20000000
+#define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d
+#define IA_DEBUG_REG0__SPARE5_MASK 0x40000000
+#define IA_DEBUG_REG0__SPARE5__SHIFT 0x1e
+#define IA_DEBUG_REG0__SPARE6_MASK 0x80000000
+#define IA_DEBUG_REG0__SPARE6__SHIFT 0x1f
+#define IA_DEBUG_REG1__dma_input_fifo_empty_MASK 0x1
+#define IA_DEBUG_REG1__dma_input_fifo_empty__SHIFT 0x0
+#define IA_DEBUG_REG1__dma_input_fifo_full_MASK 0x2
+#define IA_DEBUG_REG1__dma_input_fifo_full__SHIFT 0x1
+#define IA_DEBUG_REG1__start_new_packet_MASK 0x4
+#define IA_DEBUG_REG1__start_new_packet__SHIFT 0x2
+#define IA_DEBUG_REG1__dma_rdreq_dr_q_MASK 0x8
+#define IA_DEBUG_REG1__dma_rdreq_dr_q__SHIFT 0x3
+#define IA_DEBUG_REG1__dma_zero_indices_q_MASK 0x10
+#define IA_DEBUG_REG1__dma_zero_indices_q__SHIFT 0x4
+#define IA_DEBUG_REG1__dma_buf_type_q_MASK 0x60
+#define IA_DEBUG_REG1__dma_buf_type_q__SHIFT 0x5
+#define IA_DEBUG_REG1__dma_req_path_q_MASK 0x80
+#define IA_DEBUG_REG1__dma_req_path_q__SHIFT 0x7
+#define IA_DEBUG_REG1__discard_1st_chunk_MASK 0x100
+#define IA_DEBUG_REG1__discard_1st_chunk__SHIFT 0x8
+#define IA_DEBUG_REG1__discard_2nd_chunk_MASK 0x200
+#define IA_DEBUG_REG1__discard_2nd_chunk__SHIFT 0x9
+#define IA_DEBUG_REG1__second_tc_ret_data_q_MASK 0x400
+#define IA_DEBUG_REG1__second_tc_ret_data_q__SHIFT 0xa
+#define IA_DEBUG_REG1__dma_tc_ret_sel_q_MASK 0x800
+#define IA_DEBUG_REG1__dma_tc_ret_sel_q__SHIFT 0xb
+#define IA_DEBUG_REG1__last_rdreq_in_dma_op_MASK 0x1000
+#define IA_DEBUG_REG1__last_rdreq_in_dma_op__SHIFT 0xc
+#define IA_DEBUG_REG1__dma_mask_fifo_empty_MASK 0x2000
+#define IA_DEBUG_REG1__dma_mask_fifo_empty__SHIFT 0xd
+#define IA_DEBUG_REG1__dma_data_fifo_empty_q_MASK 0x4000
+#define IA_DEBUG_REG1__dma_data_fifo_empty_q__SHIFT 0xe
+#define IA_DEBUG_REG1__dma_data_fifo_full_MASK 0x8000
+#define IA_DEBUG_REG1__dma_data_fifo_full__SHIFT 0xf
+#define IA_DEBUG_REG1__dma_req_fifo_empty_MASK 0x10000
+#define IA_DEBUG_REG1__dma_req_fifo_empty__SHIFT 0x10
+#define IA_DEBUG_REG1__dma_req_fifo_full_MASK 0x20000
+#define IA_DEBUG_REG1__dma_req_fifo_full__SHIFT 0x11
+#define IA_DEBUG_REG1__stage2_dr_MASK 0x40000
+#define IA_DEBUG_REG1__stage2_dr__SHIFT 0x12
+#define IA_DEBUG_REG1__stage2_rtr_MASK 0x80000
+#define IA_DEBUG_REG1__stage2_rtr__SHIFT 0x13
+#define IA_DEBUG_REG1__stage3_dr_MASK 0x100000
+#define IA_DEBUG_REG1__stage3_dr__SHIFT 0x14
+#define IA_DEBUG_REG1__stage3_rtr_MASK 0x200000
+#define IA_DEBUG_REG1__stage3_rtr__SHIFT 0x15
+#define IA_DEBUG_REG1__stage4_dr_MASK 0x400000
+#define IA_DEBUG_REG1__stage4_dr__SHIFT 0x16
+#define IA_DEBUG_REG1__stage4_rtr_MASK 0x800000
+#define IA_DEBUG_REG1__stage4_rtr__SHIFT 0x17
+#define IA_DEBUG_REG1__dma_skid_fifo_empty_MASK 0x1000000
+#define IA_DEBUG_REG1__dma_skid_fifo_empty__SHIFT 0x18
+#define IA_DEBUG_REG1__dma_skid_fifo_full_MASK 0x2000000
+#define IA_DEBUG_REG1__dma_skid_fifo_full__SHIFT 0x19
+#define IA_DEBUG_REG1__dma_grp_valid_MASK 0x4000000
+#define IA_DEBUG_REG1__dma_grp_valid__SHIFT 0x1a
+#define IA_DEBUG_REG1__grp_dma_read_MASK 0x8000000
+#define IA_DEBUG_REG1__grp_dma_read__SHIFT 0x1b
+#define IA_DEBUG_REG1__current_data_valid_MASK 0x10000000
+#define IA_DEBUG_REG1__current_data_valid__SHIFT 0x1c
+#define IA_DEBUG_REG1__out_of_range_r2_q_MASK 0x20000000
+#define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT 0x1d
+#define IA_DEBUG_REG1__dma_mask_fifo_we_MASK 0x40000000
+#define IA_DEBUG_REG1__dma_mask_fifo_we__SHIFT 0x1e
+#define IA_DEBUG_REG1__dma_ret_data_we_q_MASK 0x80000000
+#define IA_DEBUG_REG1__dma_ret_data_we_q__SHIFT 0x1f
+#define IA_DEBUG_REG2__hp_dma_input_fifo_empty_MASK 0x1
+#define IA_DEBUG_REG2__hp_dma_input_fifo_empty__SHIFT 0x0
+#define IA_DEBUG_REG2__hp_dma_input_fifo_full_MASK 0x2
+#define IA_DEBUG_REG2__hp_dma_input_fifo_full__SHIFT 0x1
+#define IA_DEBUG_REG2__hp_start_new_packet_MASK 0x4
+#define IA_DEBUG_REG2__hp_start_new_packet__SHIFT 0x2
+#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q_MASK 0x8
+#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q__SHIFT 0x3
+#define IA_DEBUG_REG2__hp_dma_zero_indices_q_MASK 0x10
+#define IA_DEBUG_REG2__hp_dma_zero_indices_q__SHIFT 0x4
+#define IA_DEBUG_REG2__hp_dma_buf_type_q_MASK 0x60
+#define IA_DEBUG_REG2__hp_dma_buf_type_q__SHIFT 0x5
+#define IA_DEBUG_REG2__hp_dma_req_path_q_MASK 0x80
+#define IA_DEBUG_REG2__hp_dma_req_path_q__SHIFT 0x7
+#define IA_DEBUG_REG2__hp_discard_1st_chunk_MASK 0x100
+#define IA_DEBUG_REG2__hp_discard_1st_chunk__SHIFT 0x8
+#define IA_DEBUG_REG2__hp_discard_2nd_chunk_MASK 0x200
+#define IA_DEBUG_REG2__hp_discard_2nd_chunk__SHIFT 0x9
+#define IA_DEBUG_REG2__hp_second_tc_ret_data_q_MASK 0x400
+#define IA_DEBUG_REG2__hp_second_tc_ret_data_q__SHIFT 0xa
+#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q_MASK 0x800
+#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q__SHIFT 0xb
+#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op_MASK 0x1000
+#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op__SHIFT 0xc
+#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty_MASK 0x2000
+#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty__SHIFT 0xd
+#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q_MASK 0x4000
+#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q__SHIFT 0xe
+#define IA_DEBUG_REG2__hp_dma_data_fifo_full_MASK 0x8000
+#define IA_DEBUG_REG2__hp_dma_data_fifo_full__SHIFT 0xf
+#define IA_DEBUG_REG2__hp_dma_req_fifo_empty_MASK 0x10000
+#define IA_DEBUG_REG2__hp_dma_req_fifo_empty__SHIFT 0x10
+#define IA_DEBUG_REG2__hp_dma_req_fifo_full_MASK 0x20000
+#define IA_DEBUG_REG2__hp_dma_req_fifo_full__SHIFT 0x11
+#define IA_DEBUG_REG2__hp_stage2_dr_MASK 0x40000
+#define IA_DEBUG_REG2__hp_stage2_dr__SHIFT 0x12
+#define IA_DEBUG_REG2__hp_stage2_rtr_MASK 0x80000
+#define IA_DEBUG_REG2__hp_stage2_rtr__SHIFT 0x13
+#define IA_DEBUG_REG2__hp_stage3_dr_MASK 0x100000
+#define IA_DEBUG_REG2__hp_stage3_dr__SHIFT 0x14
+#define IA_DEBUG_REG2__hp_stage3_rtr_MASK 0x200000
+#define IA_DEBUG_REG2__hp_stage3_rtr__SHIFT 0x15
+#define IA_DEBUG_REG2__hp_stage4_dr_MASK 0x400000
+#define IA_DEBUG_REG2__hp_stage4_dr__SHIFT 0x16
+#define IA_DEBUG_REG2__hp_stage4_rtr_MASK 0x800000
+#define IA_DEBUG_REG2__hp_stage4_rtr__SHIFT 0x17
+#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty_MASK 0x1000000
+#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty__SHIFT 0x18
+#define IA_DEBUG_REG2__hp_dma_skid_fifo_full_MASK 0x2000000
+#define IA_DEBUG_REG2__hp_dma_skid_fifo_full__SHIFT 0x19
+#define IA_DEBUG_REG2__hp_dma_grp_valid_MASK 0x4000000
+#define IA_DEBUG_REG2__hp_dma_grp_valid__SHIFT 0x1a
+#define IA_DEBUG_REG2__hp_grp_dma_read_MASK 0x8000000
+#define IA_DEBUG_REG2__hp_grp_dma_read__SHIFT 0x1b
+#define IA_DEBUG_REG2__hp_current_data_valid_MASK 0x10000000
+#define IA_DEBUG_REG2__hp_current_data_valid__SHIFT 0x1c
+#define IA_DEBUG_REG2__hp_out_of_range_r2_q_MASK 0x20000000
+#define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT 0x1d
+#define IA_DEBUG_REG2__hp_dma_mask_fifo_we_MASK 0x40000000
+#define IA_DEBUG_REG2__hp_dma_mask_fifo_we__SHIFT 0x1e
+#define IA_DEBUG_REG2__hp_dma_ret_data_we_q_MASK 0x80000000
+#define IA_DEBUG_REG2__hp_dma_ret_data_we_q__SHIFT 0x1f
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid_MASK 0x1
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid__SHIFT 0x0
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_read_MASK 0x2
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_read__SHIFT 0x1
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out_MASK 0x4
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out__SHIFT 0x2
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out_MASK 0x8
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out__SHIFT 0x3
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out_MASK 0x10
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out__SHIFT 0x4
+#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0_MASK 0x20
+#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0__SHIFT 0x5
+#define IA_DEBUG_REG3__must_service_pipe0_req_MASK 0x40
+#define IA_DEBUG_REG3__must_service_pipe0_req__SHIFT 0x6
+#define IA_DEBUG_REG3__send_pipe1_req_MASK 0x80
+#define IA_DEBUG_REG3__send_pipe1_req__SHIFT 0x7
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid_MASK 0x100
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid__SHIFT 0x8
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_read_MASK 0x200
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_read__SHIFT 0x9
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out_MASK 0x400
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out__SHIFT 0xa
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out_MASK 0x800
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out__SHIFT 0xb
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out_MASK 0x1000
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out__SHIFT 0xc
+#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q_MASK 0x2000
+#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q__SHIFT 0xd
+#define IA_DEBUG_REG3__mc_out_rtr_MASK 0x4000
+#define IA_DEBUG_REG3__mc_out_rtr__SHIFT 0xe
+#define IA_DEBUG_REG3__dma_rdreq_send_out_MASK 0x8000
+#define IA_DEBUG_REG3__dma_rdreq_send_out__SHIFT 0xf
+#define IA_DEBUG_REG3__pipe0_dr_MASK 0x10000
+#define IA_DEBUG_REG3__pipe0_dr__SHIFT 0x10
+#define IA_DEBUG_REG3__pipe0_rtr_MASK 0x20000
+#define IA_DEBUG_REG3__pipe0_rtr__SHIFT 0x11
+#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q_MASK 0x40000
+#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q__SHIFT 0x12
+#define IA_DEBUG_REG3__tc_out_rtr_MASK 0x80000
+#define IA_DEBUG_REG3__tc_out_rtr__SHIFT 0x13
+#define IA_DEBUG_REG3__pair0_valid_p1_MASK 0x100000
+#define IA_DEBUG_REG3__pair0_valid_p1__SHIFT 0x14
+#define IA_DEBUG_REG3__pair1_valid_p1_MASK 0x200000
+#define IA_DEBUG_REG3__pair1_valid_p1__SHIFT 0x15
+#define IA_DEBUG_REG3__pair2_valid_p1_MASK 0x400000
+#define IA_DEBUG_REG3__pair2_valid_p1__SHIFT 0x16
+#define IA_DEBUG_REG3__pair3_valid_p1_MASK 0x800000
+#define IA_DEBUG_REG3__pair3_valid_p1__SHIFT 0x17
+#define IA_DEBUG_REG3__tc_req_count_q_MASK 0x3000000
+#define IA_DEBUG_REG3__tc_req_count_q__SHIFT 0x18
+#define IA_DEBUG_REG3__discard_1st_chunk_MASK 0x4000000
+#define IA_DEBUG_REG3__discard_1st_chunk__SHIFT 0x1a
+#define IA_DEBUG_REG3__discard_2nd_chunk_MASK 0x8000000
+#define IA_DEBUG_REG3__discard_2nd_chunk__SHIFT 0x1b
+#define IA_DEBUG_REG3__last_tc_req_p1_MASK 0x10000000
+#define IA_DEBUG_REG3__last_tc_req_p1__SHIFT 0x1c
+#define IA_DEBUG_REG3__IA_TC_rdreq_send_out_MASK 0x20000000
+#define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT 0x1d
+#define IA_DEBUG_REG3__TC_IA_rdret_valid_in_MASK 0x40000000
+#define IA_DEBUG_REG3__TC_IA_rdret_valid_in__SHIFT 0x1e
+#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in_MASK 0x80000000
+#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in__SHIFT 0x1f
+#define IA_DEBUG_REG4__pipe0_dr_MASK 0x1
+#define IA_DEBUG_REG4__pipe0_dr__SHIFT 0x0
+#define IA_DEBUG_REG4__pipe1_dr_MASK 0x2
+#define IA_DEBUG_REG4__pipe1_dr__SHIFT 0x1
+#define IA_DEBUG_REG4__pipe2_dr_MASK 0x4
+#define IA_DEBUG_REG4__pipe2_dr__SHIFT 0x2
+#define IA_DEBUG_REG4__pipe3_dr_MASK 0x8
+#define IA_DEBUG_REG4__pipe3_dr__SHIFT 0x3
+#define IA_DEBUG_REG4__pipe4_dr_MASK 0x10
+#define IA_DEBUG_REG4__pipe4_dr__SHIFT 0x4
+#define IA_DEBUG_REG4__pipe5_dr_MASK 0x20
+#define IA_DEBUG_REG4__pipe5_dr__SHIFT 0x5
+#define IA_DEBUG_REG4__grp_se0_fifo_empty_MASK 0x40
+#define IA_DEBUG_REG4__grp_se0_fifo_empty__SHIFT 0x6
+#define IA_DEBUG_REG4__grp_se0_fifo_full_MASK 0x80
+#define IA_DEBUG_REG4__grp_se0_fifo_full__SHIFT 0x7
+#define IA_DEBUG_REG4__pipe0_rtr_MASK 0x100
+#define IA_DEBUG_REG4__pipe0_rtr__SHIFT 0x8
+#define IA_DEBUG_REG4__pipe1_rtr_MASK 0x200
+#define IA_DEBUG_REG4__pipe1_rtr__SHIFT 0x9
+#define IA_DEBUG_REG4__pipe2_rtr_MASK 0x400
+#define IA_DEBUG_REG4__pipe2_rtr__SHIFT 0xa
+#define IA_DEBUG_REG4__pipe3_rtr_MASK 0x800
+#define IA_DEBUG_REG4__pipe3_rtr__SHIFT 0xb
+#define IA_DEBUG_REG4__pipe4_rtr_MASK 0x1000
+#define IA_DEBUG_REG4__pipe4_rtr__SHIFT 0xc
+#define IA_DEBUG_REG4__pipe5_rtr_MASK 0x2000
+#define IA_DEBUG_REG4__pipe5_rtr__SHIFT 0xd
+#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q_MASK 0x4000
+#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q__SHIFT 0xe
+#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q_MASK 0x8000
+#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q__SHIFT 0xf
+#define IA_DEBUG_REG4__di_major_mode_p1_q_MASK 0x10000
+#define IA_DEBUG_REG4__di_major_mode_p1_q__SHIFT 0x10
+#define IA_DEBUG_REG4__gs_mode_p1_q_MASK 0xe0000
+#define IA_DEBUG_REG4__gs_mode_p1_q__SHIFT 0x11
+#define IA_DEBUG_REG4__di_event_flag_p1_q_MASK 0x100000
+#define IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT 0x14
+#define IA_DEBUG_REG4__di_state_sel_p1_q_MASK 0xe00000
+#define IA_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x15
+#define IA_DEBUG_REG4__draw_opaq_en_p1_q_MASK 0x1000000
+#define IA_DEBUG_REG4__draw_opaq_en_p1_q__SHIFT 0x18
+#define IA_DEBUG_REG4__draw_opaq_active_q_MASK 0x2000000
+#define IA_DEBUG_REG4__draw_opaq_active_q__SHIFT 0x19
+#define IA_DEBUG_REG4__di_source_select_p1_q_MASK 0xc000000
+#define IA_DEBUG_REG4__di_source_select_p1_q__SHIFT 0x1a
+#define IA_DEBUG_REG4__ready_to_read_di_MASK 0x10000000
+#define IA_DEBUG_REG4__ready_to_read_di__SHIFT 0x1c
+#define IA_DEBUG_REG4__di_first_group_of_draw_q_MASK 0x20000000
+#define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT 0x1d
+#define IA_DEBUG_REG4__last_shift_of_draw_MASK 0x40000000
+#define IA_DEBUG_REG4__last_shift_of_draw__SHIFT 0x1e
+#define IA_DEBUG_REG4__current_shift_is_vect1_q_MASK 0x80000000
+#define IA_DEBUG_REG4__current_shift_is_vect1_q__SHIFT 0x1f
+#define IA_DEBUG_REG5__di_index_counter_q_15_0_MASK 0xffff
+#define IA_DEBUG_REG5__di_index_counter_q_15_0__SHIFT 0x0
+#define IA_DEBUG_REG5__instanceid_13_0_MASK 0x3fff0000
+#define IA_DEBUG_REG5__instanceid_13_0__SHIFT 0x10
+#define IA_DEBUG_REG5__draw_input_fifo_full_MASK 0x40000000
+#define IA_DEBUG_REG5__draw_input_fifo_full__SHIFT 0x1e
+#define IA_DEBUG_REG5__draw_input_fifo_empty_MASK 0x80000000
+#define IA_DEBUG_REG5__draw_input_fifo_empty__SHIFT 0x1f
+#define IA_DEBUG_REG6__current_shift_q_MASK 0xf
+#define IA_DEBUG_REG6__current_shift_q__SHIFT 0x0
+#define IA_DEBUG_REG6__current_stride_pre_MASK 0xf0
+#define IA_DEBUG_REG6__current_stride_pre__SHIFT 0x4
+#define IA_DEBUG_REG6__current_stride_q_MASK 0x1f00
+#define IA_DEBUG_REG6__current_stride_q__SHIFT 0x8
+#define IA_DEBUG_REG6__first_group_partial_MASK 0x2000
+#define IA_DEBUG_REG6__first_group_partial__SHIFT 0xd
+#define IA_DEBUG_REG6__second_group_partial_MASK 0x4000
+#define IA_DEBUG_REG6__second_group_partial__SHIFT 0xe
+#define IA_DEBUG_REG6__curr_prim_partial_MASK 0x8000
+#define IA_DEBUG_REG6__curr_prim_partial__SHIFT 0xf
+#define IA_DEBUG_REG6__next_stride_q_MASK 0x1f0000
+#define IA_DEBUG_REG6__next_stride_q__SHIFT 0x10
+#define IA_DEBUG_REG6__next_group_partial_MASK 0x200000
+#define IA_DEBUG_REG6__next_group_partial__SHIFT 0x15
+#define IA_DEBUG_REG6__after_group_partial_MASK 0x400000
+#define IA_DEBUG_REG6__after_group_partial__SHIFT 0x16
+#define IA_DEBUG_REG6__extract_group_MASK 0x800000
+#define IA_DEBUG_REG6__extract_group__SHIFT 0x17
+#define IA_DEBUG_REG6__grp_shift_debug_data_MASK 0xff000000
+#define IA_DEBUG_REG6__grp_shift_debug_data__SHIFT 0x18
+#define IA_DEBUG_REG7__reset_indx_state_q_MASK 0xf
+#define IA_DEBUG_REG7__reset_indx_state_q__SHIFT 0x0
+#define IA_DEBUG_REG7__shift_vect_valid_p2_q_MASK 0xf0
+#define IA_DEBUG_REG7__shift_vect_valid_p2_q__SHIFT 0x4
+#define IA_DEBUG_REG7__shift_vect1_valid_p2_q_MASK 0xf00
+#define IA_DEBUG_REG7__shift_vect1_valid_p2_q__SHIFT 0x8
+#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q_MASK 0xf000
+#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q__SHIFT 0xc
+#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q_MASK 0xf0000
+#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q__SHIFT 0x10
+#define IA_DEBUG_REG7__num_indx_in_group_p2_q_MASK 0x700000
+#define IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT 0x14
+#define IA_DEBUG_REG7__last_group_of_draw_p2_q_MASK 0x800000
+#define IA_DEBUG_REG7__last_group_of_draw_p2_q__SHIFT 0x17
+#define IA_DEBUG_REG7__shift_event_flag_p2_q_MASK 0x1000000
+#define IA_DEBUG_REG7__shift_event_flag_p2_q__SHIFT 0x18
+#define IA_DEBUG_REG7__indx_shift_is_one_p2_q_MASK 0x2000000
+#define IA_DEBUG_REG7__indx_shift_is_one_p2_q__SHIFT 0x19
+#define IA_DEBUG_REG7__indx_shift_is_two_p2_q_MASK 0x4000000
+#define IA_DEBUG_REG7__indx_shift_is_two_p2_q__SHIFT 0x1a
+#define IA_DEBUG_REG7__indx_stride_is_four_p2_q_MASK 0x8000000
+#define IA_DEBUG_REG7__indx_stride_is_four_p2_q__SHIFT 0x1b
+#define IA_DEBUG_REG7__shift_prim1_reset_p3_q_MASK 0x10000000
+#define IA_DEBUG_REG7__shift_prim1_reset_p3_q__SHIFT 0x1c
+#define IA_DEBUG_REG7__shift_prim1_partial_p3_q_MASK 0x20000000
+#define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x1d
+#define IA_DEBUG_REG7__shift_prim0_reset_p3_q_MASK 0x40000000
+#define IA_DEBUG_REG7__shift_prim0_reset_p3_q__SHIFT 0x1e
+#define IA_DEBUG_REG7__shift_prim0_partial_p3_q_MASK 0x80000000
+#define IA_DEBUG_REG7__shift_prim0_partial_p3_q__SHIFT 0x1f
+#define IA_DEBUG_REG8__di_prim_type_p1_q_MASK 0x1f
+#define IA_DEBUG_REG8__di_prim_type_p1_q__SHIFT 0x0
+#define IA_DEBUG_REG8__two_cycle_xfer_p1_q_MASK 0x20
+#define IA_DEBUG_REG8__two_cycle_xfer_p1_q__SHIFT 0x5
+#define IA_DEBUG_REG8__two_prim_input_p1_q_MASK 0x40
+#define IA_DEBUG_REG8__two_prim_input_p1_q__SHIFT 0x6
+#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q_MASK 0x80
+#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q__SHIFT 0x7
+#define IA_DEBUG_REG8__last_group_of_inst_p5_q_MASK 0x100
+#define IA_DEBUG_REG8__last_group_of_inst_p5_q__SHIFT 0x8
+#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q_MASK 0x200
+#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q__SHIFT 0x9
+#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q_MASK 0x400
+#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q__SHIFT 0xa
+#define IA_DEBUG_REG8__grp_continued_MASK 0x800
+#define IA_DEBUG_REG8__grp_continued__SHIFT 0xb
+#define IA_DEBUG_REG8__grp_state_sel_MASK 0x7000
+#define IA_DEBUG_REG8__grp_state_sel__SHIFT 0xc
+#define IA_DEBUG_REG8__grp_sub_prim_type_MASK 0x1f8000
+#define IA_DEBUG_REG8__grp_sub_prim_type__SHIFT 0xf
+#define IA_DEBUG_REG8__grp_output_path_MASK 0xe00000
+#define IA_DEBUG_REG8__grp_output_path__SHIFT 0x15
+#define IA_DEBUG_REG8__grp_null_primitive_MASK 0x1000000
+#define IA_DEBUG_REG8__grp_null_primitive__SHIFT 0x18
+#define IA_DEBUG_REG8__grp_eop_MASK 0x2000000
+#define IA_DEBUG_REG8__grp_eop__SHIFT 0x19
+#define IA_DEBUG_REG8__grp_eopg_MASK 0x4000000
+#define IA_DEBUG_REG8__grp_eopg__SHIFT 0x1a
+#define IA_DEBUG_REG8__grp_event_flag_MASK 0x8000000
+#define IA_DEBUG_REG8__grp_event_flag__SHIFT 0x1b
+#define IA_DEBUG_REG8__grp_components_valid_MASK 0xf0000000
+#define IA_DEBUG_REG8__grp_components_valid__SHIFT 0x1c
+#define IA_DEBUG_REG9__send_to_se1_p6_MASK 0x1
+#define IA_DEBUG_REG9__send_to_se1_p6__SHIFT 0x0
+#define IA_DEBUG_REG9__gfx_se_switch_p6_MASK 0x2
+#define IA_DEBUG_REG9__gfx_se_switch_p6__SHIFT 0x1
+#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6_MASK 0x4
+#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6__SHIFT 0x2
+#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6_MASK 0x8
+#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6__SHIFT 0x3
+#define IA_DEBUG_REG9__prim1_eoi_p6_MASK 0x10
+#define IA_DEBUG_REG9__prim1_eoi_p6__SHIFT 0x4
+#define IA_DEBUG_REG9__prim0_eoi_p6_MASK 0x20
+#define IA_DEBUG_REG9__prim0_eoi_p6__SHIFT 0x5
+#define IA_DEBUG_REG9__prim1_valid_eopg_p6_MASK 0x40
+#define IA_DEBUG_REG9__prim1_valid_eopg_p6__SHIFT 0x6
+#define IA_DEBUG_REG9__prim0_valid_eopg_p6_MASK 0x80
+#define IA_DEBUG_REG9__prim0_valid_eopg_p6__SHIFT 0x7
+#define IA_DEBUG_REG9__prim1_to_other_se_p6_MASK 0x100
+#define IA_DEBUG_REG9__prim1_to_other_se_p6__SHIFT 0x8
+#define IA_DEBUG_REG9__eopg_on_last_prim_p6_MASK 0x200
+#define IA_DEBUG_REG9__eopg_on_last_prim_p6__SHIFT 0x9
+#define IA_DEBUG_REG9__eopg_between_prims_p6_MASK 0x400
+#define IA_DEBUG_REG9__eopg_between_prims_p6__SHIFT 0xa
+#define IA_DEBUG_REG9__prim_count_eq_group_size_p6_MASK 0x800
+#define IA_DEBUG_REG9__prim_count_eq_group_size_p6__SHIFT 0xb
+#define IA_DEBUG_REG9__prim_count_gt_group_size_p6_MASK 0x1000
+#define IA_DEBUG_REG9__prim_count_gt_group_size_p6__SHIFT 0xc
+#define IA_DEBUG_REG9__two_prim_output_p5_q_MASK 0x2000
+#define IA_DEBUG_REG9__two_prim_output_p5_q__SHIFT 0xd
+#define IA_DEBUG_REG9__SPARE0_MASK 0x4000
+#define IA_DEBUG_REG9__SPARE0__SHIFT 0xe
+#define IA_DEBUG_REG9__SPARE1_MASK 0x8000
+#define IA_DEBUG_REG9__SPARE1__SHIFT 0xf
+#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q_MASK 0x10000
+#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q__SHIFT 0x10
+#define IA_DEBUG_REG9__prim1_xfer_p6_MASK 0x20000
+#define IA_DEBUG_REG9__prim1_xfer_p6__SHIFT 0x11
+#define IA_DEBUG_REG9__grp_se1_fifo_empty_MASK 0x40000
+#define IA_DEBUG_REG9__grp_se1_fifo_empty__SHIFT 0x12
+#define IA_DEBUG_REG9__grp_se1_fifo_full_MASK 0x80000
+#define IA_DEBUG_REG9__grp_se1_fifo_full__SHIFT 0x13
+#define IA_DEBUG_REG9__prim_counter_q_MASK 0xfff00000
+#define IA_DEBUG_REG9__prim_counter_q__SHIFT 0x14
+#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x1
+#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0
+#define VGT_DEBUG_REG0__SPARE9_MASK 0x2
+#define VGT_DEBUG_REG0__SPARE9__SHIFT 0x1
+#define VGT_DEBUG_REG0__vgt_busy_MASK 0x4
+#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x2
+#define VGT_DEBUG_REG0__SPARE8_MASK 0x8
+#define VGT_DEBUG_REG0__SPARE8__SHIFT 0x3
+#define VGT_DEBUG_REG0__SPARE7_MASK 0x10
+#define VGT_DEBUG_REG0__SPARE7__SHIFT 0x4
+#define VGT_DEBUG_REG0__SPARE6_MASK 0x20
+#define VGT_DEBUG_REG0__SPARE6__SHIFT 0x5
+#define VGT_DEBUG_REG0__SPARE5_MASK 0x40
+#define VGT_DEBUG_REG0__SPARE5__SHIFT 0x6
+#define VGT_DEBUG_REG0__SPARE4_MASK 0x80
+#define VGT_DEBUG_REG0__SPARE4__SHIFT 0x7
+#define VGT_DEBUG_REG0__pi_busy_MASK 0x100
+#define VGT_DEBUG_REG0__pi_busy__SHIFT 0x8
+#define VGT_DEBUG_REG0__vr_pi_busy_MASK 0x200
+#define VGT_DEBUG_REG0__vr_pi_busy__SHIFT 0x9
+#define VGT_DEBUG_REG0__pt_pi_busy_MASK 0x400
+#define VGT_DEBUG_REG0__pt_pi_busy__SHIFT 0xa
+#define VGT_DEBUG_REG0__te_pi_busy_MASK 0x800
+#define VGT_DEBUG_REG0__te_pi_busy__SHIFT 0xb
+#define VGT_DEBUG_REG0__gs_busy_MASK 0x1000
+#define VGT_DEBUG_REG0__gs_busy__SHIFT 0xc
+#define VGT_DEBUG_REG0__rcm_busy_MASK 0x2000
+#define VGT_DEBUG_REG0__rcm_busy__SHIFT 0xd
+#define VGT_DEBUG_REG0__tm_busy_MASK 0x4000
+#define VGT_DEBUG_REG0__tm_busy__SHIFT 0xe
+#define VGT_DEBUG_REG0__cm_busy_MASK 0x8000
+#define VGT_DEBUG_REG0__cm_busy__SHIFT 0xf
+#define VGT_DEBUG_REG0__gog_busy_MASK 0x10000
+#define VGT_DEBUG_REG0__gog_busy__SHIFT 0x10
+#define VGT_DEBUG_REG0__frmt_busy_MASK 0x20000
+#define VGT_DEBUG_REG0__frmt_busy__SHIFT 0x11
+#define VGT_DEBUG_REG0__SPARE10_MASK 0x40000
+#define VGT_DEBUG_REG0__SPARE10__SHIFT 0x12
+#define VGT_DEBUG_REG0__te11_pi_busy_MASK 0x80000
+#define VGT_DEBUG_REG0__te11_pi_busy__SHIFT 0x13
+#define VGT_DEBUG_REG0__SPARE3_MASK 0x100000
+#define VGT_DEBUG_REG0__SPARE3__SHIFT 0x14
+#define VGT_DEBUG_REG0__combined_out_busy_MASK 0x200000
+#define VGT_DEBUG_REG0__combined_out_busy__SHIFT 0x15
+#define VGT_DEBUG_REG0__spi_vs_interfaces_busy_MASK 0x400000
+#define VGT_DEBUG_REG0__spi_vs_interfaces_busy__SHIFT 0x16
+#define VGT_DEBUG_REG0__pa_interfaces_busy_MASK 0x800000
+#define VGT_DEBUG_REG0__pa_interfaces_busy__SHIFT 0x17
+#define VGT_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
+#define VGT_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
+#define VGT_DEBUG_REG0__SPARE2_MASK 0x2000000
+#define VGT_DEBUG_REG0__SPARE2__SHIFT 0x19
+#define VGT_DEBUG_REG0__core_clk_busy_MASK 0x4000000
+#define VGT_DEBUG_REG0__core_clk_busy__SHIFT 0x1a
+#define VGT_DEBUG_REG0__gs_clk_busy_MASK 0x8000000
+#define VGT_DEBUG_REG0__gs_clk_busy__SHIFT 0x1b
+#define VGT_DEBUG_REG0__SPARE1_MASK 0x10000000
+#define VGT_DEBUG_REG0__SPARE1__SHIFT 0x1c
+#define VGT_DEBUG_REG0__sclk_core_vld_MASK 0x20000000
+#define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d
+#define VGT_DEBUG_REG0__sclk_gs_vld_MASK 0x40000000
+#define VGT_DEBUG_REG0__sclk_gs_vld__SHIFT 0x1e
+#define VGT_DEBUG_REG0__SPARE0_MASK 0x80000000
+#define VGT_DEBUG_REG0__SPARE0__SHIFT 0x1f
+#define VGT_DEBUG_REG1__SPARE9_MASK 0x1
+#define VGT_DEBUG_REG1__SPARE9__SHIFT 0x0
+#define VGT_DEBUG_REG1__SPARE8_MASK 0x2
+#define VGT_DEBUG_REG1__SPARE8__SHIFT 0x1
+#define VGT_DEBUG_REG1__SPARE7_MASK 0x4
+#define VGT_DEBUG_REG1__SPARE7__SHIFT 0x2
+#define VGT_DEBUG_REG1__SPARE6_MASK 0x8
+#define VGT_DEBUG_REG1__SPARE6__SHIFT 0x3
+#define VGT_DEBUG_REG1__SPARE5_MASK 0x10
+#define VGT_DEBUG_REG1__SPARE5__SHIFT 0x4
+#define VGT_DEBUG_REG1__SPARE4_MASK 0x20
+#define VGT_DEBUG_REG1__SPARE4__SHIFT 0x5
+#define VGT_DEBUG_REG1__SPARE3_MASK 0x40
+#define VGT_DEBUG_REG1__SPARE3__SHIFT 0x6
+#define VGT_DEBUG_REG1__SPARE2_MASK 0x80
+#define VGT_DEBUG_REG1__SPARE2__SHIFT 0x7
+#define VGT_DEBUG_REG1__SPARE1_MASK 0x100
+#define VGT_DEBUG_REG1__SPARE1__SHIFT 0x8
+#define VGT_DEBUG_REG1__SPARE0_MASK 0x200
+#define VGT_DEBUG_REG1__SPARE0__SHIFT 0x9
+#define VGT_DEBUG_REG1__pi_vr_valid_MASK 0x400
+#define VGT_DEBUG_REG1__pi_vr_valid__SHIFT 0xa
+#define VGT_DEBUG_REG1__vr_pi_read_MASK 0x800
+#define VGT_DEBUG_REG1__vr_pi_read__SHIFT 0xb
+#define VGT_DEBUG_REG1__pi_pt_valid_MASK 0x1000
+#define VGT_DEBUG_REG1__pi_pt_valid__SHIFT 0xc
+#define VGT_DEBUG_REG1__pt_pi_read_MASK 0x2000
+#define VGT_DEBUG_REG1__pt_pi_read__SHIFT 0xd
+#define VGT_DEBUG_REG1__pi_te_valid_MASK 0x4000
+#define VGT_DEBUG_REG1__pi_te_valid__SHIFT 0xe
+#define VGT_DEBUG_REG1__te_grp_read_MASK 0x8000
+#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0xf
+#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x10000
+#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x10
+#define VGT_DEBUG_REG1__SPARE12_MASK 0x20000
+#define VGT_DEBUG_REG1__SPARE12__SHIFT 0x11
+#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x40000
+#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x12
+#define VGT_DEBUG_REG1__SPARE11_MASK 0x80000
+#define VGT_DEBUG_REG1__SPARE11__SHIFT 0x13
+#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x100000
+#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x14
+#define VGT_DEBUG_REG1__SPARE10_MASK 0x200000
+#define VGT_DEBUG_REG1__SPARE10__SHIFT 0x15
+#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x400000
+#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x16
+#define VGT_DEBUG_REG1__SPARE23_MASK 0x800000
+#define VGT_DEBUG_REG1__SPARE23__SHIFT 0x17
+#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x1000000
+#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x18
+#define VGT_DEBUG_REG1__SPARE25_MASK 0x2000000
+#define VGT_DEBUG_REG1__SPARE25__SHIFT 0x19
+#define VGT_DEBUG_REG1__pi_gs_valid_MASK 0x4000000
+#define VGT_DEBUG_REG1__pi_gs_valid__SHIFT 0x1a
+#define VGT_DEBUG_REG1__gs_pi_read_MASK 0x8000000
+#define VGT_DEBUG_REG1__gs_pi_read__SHIFT 0x1b
+#define VGT_DEBUG_REG1__gog_out_indx_valid_MASK 0x10000000
+#define VGT_DEBUG_REG1__gog_out_indx_valid__SHIFT 0x1c
+#define VGT_DEBUG_REG1__out_indx_read_MASK 0x20000000
+#define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x1d
+#define VGT_DEBUG_REG1__gog_out_prim_valid_MASK 0x40000000
+#define VGT_DEBUG_REG1__gog_out_prim_valid__SHIFT 0x1e
+#define VGT_DEBUG_REG1__out_prim_read_MASK 0x80000000
+#define VGT_DEBUG_REG1__out_prim_read__SHIFT 0x1f
+#define VGT_DEBUG_REG2__hs_grp_busy_MASK 0x1
+#define VGT_DEBUG_REG2__hs_grp_busy__SHIFT 0x0
+#define VGT_DEBUG_REG2__hs_noif_busy_MASK 0x2
+#define VGT_DEBUG_REG2__hs_noif_busy__SHIFT 0x1
+#define VGT_DEBUG_REG2__tfmmIsBusy_MASK 0x4
+#define VGT_DEBUG_REG2__tfmmIsBusy__SHIFT 0x2
+#define VGT_DEBUG_REG2__lsVertIfBusy_0_MASK 0x8
+#define VGT_DEBUG_REG2__lsVertIfBusy_0__SHIFT 0x3
+#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr_MASK 0x10
+#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr__SHIFT 0x4
+#define VGT_DEBUG_REG2__lsWaveIfBusy_0_MASK 0x20
+#define VGT_DEBUG_REG2__lsWaveIfBusy_0__SHIFT 0x5
+#define VGT_DEBUG_REG2__hs_te11_tess_input_rts_MASK 0x40
+#define VGT_DEBUG_REG2__hs_te11_tess_input_rts__SHIFT 0x6
+#define VGT_DEBUG_REG2__grpModBusy_MASK 0x80
+#define VGT_DEBUG_REG2__grpModBusy__SHIFT 0x7
+#define VGT_DEBUG_REG2__lsVertFifoEmpty_MASK 0x100
+#define VGT_DEBUG_REG2__lsVertFifoEmpty__SHIFT 0x8
+#define VGT_DEBUG_REG2__lsWaveFifoEmpty_MASK 0x200
+#define VGT_DEBUG_REG2__lsWaveFifoEmpty__SHIFT 0x9
+#define VGT_DEBUG_REG2__hsVertFifoEmpty_MASK 0x400
+#define VGT_DEBUG_REG2__hsVertFifoEmpty__SHIFT 0xa
+#define VGT_DEBUG_REG2__hsWaveFifoEmpty_MASK 0x800
+#define VGT_DEBUG_REG2__hsWaveFifoEmpty__SHIFT 0xb
+#define VGT_DEBUG_REG2__hsInputFifoEmpty_MASK 0x1000
+#define VGT_DEBUG_REG2__hsInputFifoEmpty__SHIFT 0xc
+#define VGT_DEBUG_REG2__hsTifFifoEmpty_MASK 0x2000
+#define VGT_DEBUG_REG2__hsTifFifoEmpty__SHIFT 0xd
+#define VGT_DEBUG_REG2__lsVertFifoFull_MASK 0x4000
+#define VGT_DEBUG_REG2__lsVertFifoFull__SHIFT 0xe
+#define VGT_DEBUG_REG2__lsWaveFifoFull_MASK 0x8000
+#define VGT_DEBUG_REG2__lsWaveFifoFull__SHIFT 0xf
+#define VGT_DEBUG_REG2__hsVertFifoFull_MASK 0x10000
+#define VGT_DEBUG_REG2__hsVertFifoFull__SHIFT 0x10
+#define VGT_DEBUG_REG2__hsWaveFifoFull_MASK 0x20000
+#define VGT_DEBUG_REG2__hsWaveFifoFull__SHIFT 0x11
+#define VGT_DEBUG_REG2__hsInputFifoFull_MASK 0x40000
+#define VGT_DEBUG_REG2__hsInputFifoFull__SHIFT 0x12
+#define VGT_DEBUG_REG2__hsTifFifoFull_MASK 0x80000
+#define VGT_DEBUG_REG2__hsTifFifoFull__SHIFT 0x13
+#define VGT_DEBUG_REG2__p0_rtr_MASK 0x100000
+#define VGT_DEBUG_REG2__p0_rtr__SHIFT 0x14
+#define VGT_DEBUG_REG2__p1_rtr_MASK 0x200000
+#define VGT_DEBUG_REG2__p1_rtr__SHIFT 0x15
+#define VGT_DEBUG_REG2__p0_dr_MASK 0x400000
+#define VGT_DEBUG_REG2__p0_dr__SHIFT 0x16
+#define VGT_DEBUG_REG2__p1_dr_MASK 0x800000
+#define VGT_DEBUG_REG2__p1_dr__SHIFT 0x17
+#define VGT_DEBUG_REG2__p0_rts_MASK 0x1000000
+#define VGT_DEBUG_REG2__p0_rts__SHIFT 0x18
+#define VGT_DEBUG_REG2__p1_rts_MASK 0x2000000
+#define VGT_DEBUG_REG2__p1_rts__SHIFT 0x19
+#define VGT_DEBUG_REG2__ls_sh_id_MASK 0x4000000
+#define VGT_DEBUG_REG2__ls_sh_id__SHIFT 0x1a
+#define VGT_DEBUG_REG2__lsFwaveFlag_MASK 0x8000000
+#define VGT_DEBUG_REG2__lsFwaveFlag__SHIFT 0x1b
+#define VGT_DEBUG_REG2__lsWaveSendFlush_MASK 0x10000000
+#define VGT_DEBUG_REG2__lsWaveSendFlush__SHIFT 0x1c
+#define VGT_DEBUG_REG2__SPARE_MASK 0xe0000000
+#define VGT_DEBUG_REG2__SPARE__SHIFT 0x1d
+#define VGT_DEBUG_REG3__lsTgRelInd_MASK 0xfff
+#define VGT_DEBUG_REG3__lsTgRelInd__SHIFT 0x0
+#define VGT_DEBUG_REG3__lsWaveRelInd_MASK 0x3f000
+#define VGT_DEBUG_REG3__lsWaveRelInd__SHIFT 0xc
+#define VGT_DEBUG_REG3__lsPatchCnt_MASK 0x3fc0000
+#define VGT_DEBUG_REG3__lsPatchCnt__SHIFT 0x12
+#define VGT_DEBUG_REG3__hsWaveRelInd_MASK 0xfc000000
+#define VGT_DEBUG_REG3__hsWaveRelInd__SHIFT 0x1a
+#define VGT_DEBUG_REG4__hsPatchCnt_MASK 0xff
+#define VGT_DEBUG_REG4__hsPatchCnt__SHIFT 0x0
+#define VGT_DEBUG_REG4__hsPrimId_15_0_MASK 0xffff00
+#define VGT_DEBUG_REG4__hsPrimId_15_0__SHIFT 0x8
+#define VGT_DEBUG_REG4__hsCpCnt_MASK 0x1f000000
+#define VGT_DEBUG_REG4__hsCpCnt__SHIFT 0x18
+#define VGT_DEBUG_REG4__hsWaveSendFlush_MASK 0x20000000
+#define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT 0x1d
+#define VGT_DEBUG_REG4__hsFwaveFlag_MASK 0x40000000
+#define VGT_DEBUG_REG4__hsFwaveFlag__SHIFT 0x1e
+#define VGT_DEBUG_REG4__SPARE_MASK 0x80000000
+#define VGT_DEBUG_REG4__SPARE__SHIFT 0x1f
+#define VGT_DEBUG_REG5__SPARE4_MASK 0x7
+#define VGT_DEBUG_REG5__SPARE4__SHIFT 0x0
+#define VGT_DEBUG_REG5__hsWaveCreditCnt_0_MASK 0xf8
+#define VGT_DEBUG_REG5__hsWaveCreditCnt_0__SHIFT 0x3
+#define VGT_DEBUG_REG5__SPARE3_MASK 0x700
+#define VGT_DEBUG_REG5__SPARE3__SHIFT 0x8
+#define VGT_DEBUG_REG5__hsVertCreditCnt_0_MASK 0xf800
+#define VGT_DEBUG_REG5__hsVertCreditCnt_0__SHIFT 0xb
+#define VGT_DEBUG_REG5__SPARE2_MASK 0x70000
+#define VGT_DEBUG_REG5__SPARE2__SHIFT 0x10
+#define VGT_DEBUG_REG5__lsWaveCreditCnt_0_MASK 0xf80000
+#define VGT_DEBUG_REG5__lsWaveCreditCnt_0__SHIFT 0x13
+#define VGT_DEBUG_REG5__SPARE1_MASK 0x7000000
+#define VGT_DEBUG_REG5__SPARE1__SHIFT 0x18
+#define VGT_DEBUG_REG5__lsVertCreditCnt_0_MASK 0xf8000000
+#define VGT_DEBUG_REG5__lsVertCreditCnt_0__SHIFT 0x1b
+#define VGT_DEBUG_REG6__debug_BASE_MASK 0xffff
+#define VGT_DEBUG_REG6__debug_BASE__SHIFT 0x0
+#define VGT_DEBUG_REG6__debug_SIZE_MASK 0xffff0000
+#define VGT_DEBUG_REG6__debug_SIZE__SHIFT 0x10
+#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty_MASK 0x1
+#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty__SHIFT 0x0
+#define VGT_DEBUG_REG7__debug_tfmmFifoFull_MASK 0x2
+#define VGT_DEBUG_REG7__debug_tfmmFifoFull__SHIFT 0x1
+#define VGT_DEBUG_REG7__hs_pipe0_dr_MASK 0x4
+#define VGT_DEBUG_REG7__hs_pipe0_dr__SHIFT 0x2
+#define VGT_DEBUG_REG7__hs_pipe0_rtr_MASK 0x8
+#define VGT_DEBUG_REG7__hs_pipe0_rtr__SHIFT 0x3
+#define VGT_DEBUG_REG7__hs_pipe1_rtr_MASK 0x10
+#define VGT_DEBUG_REG7__hs_pipe1_rtr__SHIFT 0x4
+#define VGT_DEBUG_REG7__SPARE_MASK 0xffe0
+#define VGT_DEBUG_REG7__SPARE__SHIFT 0x5
+#define VGT_DEBUG_REG7__TF_addr_MASK 0xffff0000
+#define VGT_DEBUG_REG7__TF_addr__SHIFT 0x10
+#define VGT_DEBUG_REG8__rcm_busy_q_MASK 0x1
+#define VGT_DEBUG_REG8__rcm_busy_q__SHIFT 0x0
+#define VGT_DEBUG_REG8__rcm_noif_busy_q_MASK 0x2
+#define VGT_DEBUG_REG8__rcm_noif_busy_q__SHIFT 0x1
+#define VGT_DEBUG_REG8__r1_inst_rtr_MASK 0x4
+#define VGT_DEBUG_REG8__r1_inst_rtr__SHIFT 0x2
+#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q_MASK 0x8
+#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q__SHIFT 0x3
+#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q_MASK 0x10
+#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q__SHIFT 0x4
+#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q_MASK 0x20
+#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q__SHIFT 0x5
+#define VGT_DEBUG_REG8__valid_r0_q_MASK 0x40
+#define VGT_DEBUG_REG8__valid_r0_q__SHIFT 0x6
+#define VGT_DEBUG_REG8__valid_r1_q_MASK 0x80
+#define VGT_DEBUG_REG8__valid_r1_q__SHIFT 0x7
+#define VGT_DEBUG_REG8__valid_r2_MASK 0x100
+#define VGT_DEBUG_REG8__valid_r2__SHIFT 0x8
+#define VGT_DEBUG_REG8__valid_r2_q_MASK 0x200
+#define VGT_DEBUG_REG8__valid_r2_q__SHIFT 0x9
+#define VGT_DEBUG_REG8__r0_rtr_MASK 0x400
+#define VGT_DEBUG_REG8__r0_rtr__SHIFT 0xa
+#define VGT_DEBUG_REG8__r1_rtr_MASK 0x800
+#define VGT_DEBUG_REG8__r1_rtr__SHIFT 0xb
+#define VGT_DEBUG_REG8__r2_indx_rtr_MASK 0x1000
+#define VGT_DEBUG_REG8__r2_indx_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG8__r2_rtr_MASK 0x2000
+#define VGT_DEBUG_REG8__r2_rtr__SHIFT 0xd
+#define VGT_DEBUG_REG8__es_gs_rtr_MASK 0x4000
+#define VGT_DEBUG_REG8__es_gs_rtr__SHIFT 0xe
+#define VGT_DEBUG_REG8__gs_event_fifo_rtr_MASK 0x8000
+#define VGT_DEBUG_REG8__gs_event_fifo_rtr__SHIFT 0xf
+#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr_MASK 0x10000
+#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr__SHIFT 0x10
+#define VGT_DEBUG_REG8__gs_tbl_r3_rtr_MASK 0x20000
+#define VGT_DEBUG_REG8__gs_tbl_r3_rtr__SHIFT 0x11
+#define VGT_DEBUG_REG8__prim_skid_fifo_empty_MASK 0x40000
+#define VGT_DEBUG_REG8__prim_skid_fifo_empty__SHIFT 0x12
+#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q_MASK 0x80000
+#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q__SHIFT 0x13
+#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr_MASK 0x100000
+#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT 0x14
+#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr_MASK 0x200000
+#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr__SHIFT 0x15
+#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q_MASK 0x400000
+#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q__SHIFT 0x16
+#define VGT_DEBUG_REG8__r2_no_bp_rtr_MASK 0x800000
+#define VGT_DEBUG_REG8__r2_no_bp_rtr__SHIFT 0x17
+#define VGT_DEBUG_REG8__hold_for_es_flush_MASK 0x1000000
+#define VGT_DEBUG_REG8__hold_for_es_flush__SHIFT 0x18
+#define VGT_DEBUG_REG8__gs_event_fifo_empty_MASK 0x2000000
+#define VGT_DEBUG_REG8__gs_event_fifo_empty__SHIFT 0x19
+#define VGT_DEBUG_REG8__gsprim_buff_empty_q_MASK 0x4000000
+#define VGT_DEBUG_REG8__gsprim_buff_empty_q__SHIFT 0x1a
+#define VGT_DEBUG_REG8__gsprim_buff_full_q_MASK 0x8000000
+#define VGT_DEBUG_REG8__gsprim_buff_full_q__SHIFT 0x1b
+#define VGT_DEBUG_REG8__te_prim_fifo_empty_MASK 0x10000000
+#define VGT_DEBUG_REG8__te_prim_fifo_empty__SHIFT 0x1c
+#define VGT_DEBUG_REG8__te_prim_fifo_full_MASK 0x20000000
+#define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x1d
+#define VGT_DEBUG_REG8__te_vert_fifo_empty_MASK 0x40000000
+#define VGT_DEBUG_REG8__te_vert_fifo_empty__SHIFT 0x1e
+#define VGT_DEBUG_REG8__te_vert_fifo_full_MASK 0x80000000
+#define VGT_DEBUG_REG8__te_vert_fifo_full__SHIFT 0x1f
+#define VGT_DEBUG_REG9__indices_to_send_r2_q_MASK 0x3
+#define VGT_DEBUG_REG9__indices_to_send_r2_q__SHIFT 0x0
+#define VGT_DEBUG_REG9__valid_indices_r3_MASK 0x4
+#define VGT_DEBUG_REG9__valid_indices_r3__SHIFT 0x2
+#define VGT_DEBUG_REG9__gs_eov_r3_MASK 0x8
+#define VGT_DEBUG_REG9__gs_eov_r3__SHIFT 0x3
+#define VGT_DEBUG_REG9__eop_indx_r3_MASK 0x10
+#define VGT_DEBUG_REG9__eop_indx_r3__SHIFT 0x4
+#define VGT_DEBUG_REG9__eop_prim_r3_MASK 0x20
+#define VGT_DEBUG_REG9__eop_prim_r3__SHIFT 0x5
+#define VGT_DEBUG_REG9__es_eov_r3_MASK 0x40
+#define VGT_DEBUG_REG9__es_eov_r3__SHIFT 0x6
+#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0_MASK 0x80
+#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0__SHIFT 0x7
+#define VGT_DEBUG_REG9__pending_es_send_r3_q_MASK 0x100
+#define VGT_DEBUG_REG9__pending_es_send_r3_q__SHIFT 0x8
+#define VGT_DEBUG_REG9__pending_es_flush_r3_MASK 0x200
+#define VGT_DEBUG_REG9__pending_es_flush_r3__SHIFT 0x9
+#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0_MASK 0x400
+#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT 0xa
+#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q_MASK 0x3f800
+#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q__SHIFT 0xb
+#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q_MASK 0x40000
+#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q__SHIFT 0x12
+#define VGT_DEBUG_REG9__gs_tbl_state_r3_q_MASK 0x380000
+#define VGT_DEBUG_REG9__gs_tbl_state_r3_q__SHIFT 0x13
+#define VGT_DEBUG_REG9__gs_pending_state_r3_q_MASK 0x400000
+#define VGT_DEBUG_REG9__gs_pending_state_r3_q__SHIFT 0x16
+#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q_MASK 0x800000
+#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q__SHIFT 0x17
+#define VGT_DEBUG_REG9__gs_instancing_state_q_MASK 0x1000000
+#define VGT_DEBUG_REG9__gs_instancing_state_q__SHIFT 0x18
+#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0_MASK 0x2000000
+#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0__SHIFT 0x19
+#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0_MASK 0x4000000
+#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0__SHIFT 0x1a
+#define VGT_DEBUG_REG9__pre_r0_rtr_MASK 0x8000000
+#define VGT_DEBUG_REG9__pre_r0_rtr__SHIFT 0x1b
+#define VGT_DEBUG_REG9__valid_r3_q_MASK 0x10000000
+#define VGT_DEBUG_REG9__valid_r3_q__SHIFT 0x1c
+#define VGT_DEBUG_REG9__valid_pre_r0_q_MASK 0x20000000
+#define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x1d
+#define VGT_DEBUG_REG9__SPARE0_MASK 0x40000000
+#define VGT_DEBUG_REG9__SPARE0__SHIFT 0x1e
+#define VGT_DEBUG_REG9__off_chip_hs_r2_q_MASK 0x80000000
+#define VGT_DEBUG_REG9__off_chip_hs_r2_q__SHIFT 0x1f
+#define VGT_DEBUG_REG10__index_buffer_depth_r1_q_MASK 0x1f
+#define VGT_DEBUG_REG10__index_buffer_depth_r1_q__SHIFT 0x0
+#define VGT_DEBUG_REG10__eopg_r2_q_MASK 0x20
+#define VGT_DEBUG_REG10__eopg_r2_q__SHIFT 0x5
+#define VGT_DEBUG_REG10__eotg_r2_q_MASK 0x40
+#define VGT_DEBUG_REG10__eotg_r2_q__SHIFT 0x6
+#define VGT_DEBUG_REG10__onchip_gs_en_r0_q_MASK 0x180
+#define VGT_DEBUG_REG10__onchip_gs_en_r0_q__SHIFT 0x7
+#define VGT_DEBUG_REG10__SPARE2_MASK 0x600
+#define VGT_DEBUG_REG10__SPARE2__SHIFT 0x9
+#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq_MASK 0x800
+#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq__SHIFT 0xb
+#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q_MASK 0x1000
+#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q__SHIFT 0xc
+#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0_MASK 0x7fe000
+#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0__SHIFT 0xd
+#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0_MASK 0xff800000
+#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0__SHIFT 0x17
+#define VGT_DEBUG_REG11__tm_busy_q_MASK 0x1
+#define VGT_DEBUG_REG11__tm_busy_q__SHIFT 0x0
+#define VGT_DEBUG_REG11__tm_noif_busy_q_MASK 0x2
+#define VGT_DEBUG_REG11__tm_noif_busy_q__SHIFT 0x1
+#define VGT_DEBUG_REG11__tm_out_busy_q_MASK 0x4
+#define VGT_DEBUG_REG11__tm_out_busy_q__SHIFT 0x2
+#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy_MASK 0x8
+#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy__SHIFT 0x3
+#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy_MASK 0x10
+#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy__SHIFT 0x4
+#define VGT_DEBUG_REG11__SPARE1_MASK 0x20
+#define VGT_DEBUG_REG11__SPARE1__SHIFT 0x5
+#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy_MASK 0x40
+#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy__SHIFT 0x6
+#define VGT_DEBUG_REG11__spi_esthread_fifo_busy_MASK 0x80
+#define VGT_DEBUG_REG11__spi_esthread_fifo_busy__SHIFT 0x7
+#define VGT_DEBUG_REG11__hold_eswave_MASK 0x100
+#define VGT_DEBUG_REG11__hold_eswave__SHIFT 0x8
+#define VGT_DEBUG_REG11__es_rb_roll_over_r3_MASK 0x200
+#define VGT_DEBUG_REG11__es_rb_roll_over_r3__SHIFT 0x9
+#define VGT_DEBUG_REG11__counters_busy_r0_MASK 0x400
+#define VGT_DEBUG_REG11__counters_busy_r0__SHIFT 0xa
+#define VGT_DEBUG_REG11__counters_avail_r0_MASK 0x800
+#define VGT_DEBUG_REG11__counters_avail_r0__SHIFT 0xb
+#define VGT_DEBUG_REG11__counters_available_r0_MASK 0x1000
+#define VGT_DEBUG_REG11__counters_available_r0__SHIFT 0xc
+#define VGT_DEBUG_REG11__vs_event_fifo_rtr_MASK 0x2000
+#define VGT_DEBUG_REG11__vs_event_fifo_rtr__SHIFT 0xd
+#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q_MASK 0x4000
+#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q__SHIFT 0xe
+#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q_MASK 0x8000
+#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q__SHIFT 0xf
+#define VGT_DEBUG_REG11__gs_issue_rtr_MASK 0x10000
+#define VGT_DEBUG_REG11__gs_issue_rtr__SHIFT 0x10
+#define VGT_DEBUG_REG11__tm_pt_event_rtr_MASK 0x20000
+#define VGT_DEBUG_REG11__tm_pt_event_rtr__SHIFT 0x11
+#define VGT_DEBUG_REG11__SPARE0_MASK 0x40000
+#define VGT_DEBUG_REG11__SPARE0__SHIFT 0x12
+#define VGT_DEBUG_REG11__gs_r0_rtr_MASK 0x80000
+#define VGT_DEBUG_REG11__gs_r0_rtr__SHIFT 0x13
+#define VGT_DEBUG_REG11__es_r0_rtr_MASK 0x100000
+#define VGT_DEBUG_REG11__es_r0_rtr__SHIFT 0x14
+#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr_MASK 0x200000
+#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr__SHIFT 0x15
+#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr_MASK 0x400000
+#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr__SHIFT 0x16
+#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr_MASK 0x800000
+#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr__SHIFT 0x17
+#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr_MASK 0x1000000
+#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr__SHIFT 0x18
+#define VGT_DEBUG_REG11__vs_event_fifo_empty_MASK 0x2000000
+#define VGT_DEBUG_REG11__vs_event_fifo_empty__SHIFT 0x19
+#define VGT_DEBUG_REG11__vs_event_fifo_full_MASK 0x4000000
+#define VGT_DEBUG_REG11__vs_event_fifo_full__SHIFT 0x1a
+#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full_MASK 0x8000000
+#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full__SHIFT 0x1b
+#define VGT_DEBUG_REG11__vs_dealloc_tbl_full_MASK 0x10000000
+#define VGT_DEBUG_REG11__vs_dealloc_tbl_full__SHIFT 0x1c
+#define VGT_DEBUG_REG11__send_event_q_MASK 0x20000000
+#define VGT_DEBUG_REG11__send_event_q__SHIFT 0x1d
+#define VGT_DEBUG_REG11__es_tbl_empty_MASK 0x40000000
+#define VGT_DEBUG_REG11__es_tbl_empty__SHIFT 0x1e
+#define VGT_DEBUG_REG11__no_active_states_r0_MASK 0x80000000
+#define VGT_DEBUG_REG11__no_active_states_r0__SHIFT 0x1f
+#define VGT_DEBUG_REG12__gs_state0_r0_q_MASK 0x7
+#define VGT_DEBUG_REG12__gs_state0_r0_q__SHIFT 0x0
+#define VGT_DEBUG_REG12__gs_state1_r0_q_MASK 0x38
+#define VGT_DEBUG_REG12__gs_state1_r0_q__SHIFT 0x3
+#define VGT_DEBUG_REG12__gs_state2_r0_q_MASK 0x1c0
+#define VGT_DEBUG_REG12__gs_state2_r0_q__SHIFT 0x6
+#define VGT_DEBUG_REG12__gs_state3_r0_q_MASK 0xe00
+#define VGT_DEBUG_REG12__gs_state3_r0_q__SHIFT 0x9
+#define VGT_DEBUG_REG12__gs_state4_r0_q_MASK 0x7000
+#define VGT_DEBUG_REG12__gs_state4_r0_q__SHIFT 0xc
+#define VGT_DEBUG_REG12__gs_state5_r0_q_MASK 0x38000
+#define VGT_DEBUG_REG12__gs_state5_r0_q__SHIFT 0xf
+#define VGT_DEBUG_REG12__gs_state6_r0_q_MASK 0x1c0000
+#define VGT_DEBUG_REG12__gs_state6_r0_q__SHIFT 0x12
+#define VGT_DEBUG_REG12__gs_state7_r0_q_MASK 0xe00000
+#define VGT_DEBUG_REG12__gs_state7_r0_q__SHIFT 0x15
+#define VGT_DEBUG_REG12__gs_state8_r0_q_MASK 0x7000000
+#define VGT_DEBUG_REG12__gs_state8_r0_q__SHIFT 0x18
+#define VGT_DEBUG_REG12__gs_state9_r0_q_MASK 0x38000000
+#define VGT_DEBUG_REG12__gs_state9_r0_q__SHIFT 0x1b
+#define VGT_DEBUG_REG12__hold_eswave_eop_MASK 0x40000000
+#define VGT_DEBUG_REG12__hold_eswave_eop__SHIFT 0x1e
+#define VGT_DEBUG_REG12__SPARE0_MASK 0x80000000
+#define VGT_DEBUG_REG12__SPARE0__SHIFT 0x1f
+#define VGT_DEBUG_REG13__gs_state10_r0_q_MASK 0x7
+#define VGT_DEBUG_REG13__gs_state10_r0_q__SHIFT 0x0
+#define VGT_DEBUG_REG13__gs_state11_r0_q_MASK 0x38
+#define VGT_DEBUG_REG13__gs_state11_r0_q__SHIFT 0x3
+#define VGT_DEBUG_REG13__gs_state12_r0_q_MASK 0x1c0
+#define VGT_DEBUG_REG13__gs_state12_r0_q__SHIFT 0x6
+#define VGT_DEBUG_REG13__gs_state13_r0_q_MASK 0xe00
+#define VGT_DEBUG_REG13__gs_state13_r0_q__SHIFT 0x9
+#define VGT_DEBUG_REG13__gs_state14_r0_q_MASK 0x7000
+#define VGT_DEBUG_REG13__gs_state14_r0_q__SHIFT 0xc
+#define VGT_DEBUG_REG13__gs_state15_r0_q_MASK 0x38000
+#define VGT_DEBUG_REG13__gs_state15_r0_q__SHIFT 0xf
+#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0_MASK 0x3c0000
+#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0__SHIFT 0x12
+#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0_MASK 0x400000
+#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0__SHIFT 0x16
+#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0_MASK 0x800000
+#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0__SHIFT 0x17
+#define VGT_DEBUG_REG13__es_tbl_full_MASK 0x1000000
+#define VGT_DEBUG_REG13__es_tbl_full__SHIFT 0x18
+#define VGT_DEBUG_REG13__SPARE1_MASK 0x2000000
+#define VGT_DEBUG_REG13__SPARE1__SHIFT 0x19
+#define VGT_DEBUG_REG13__SPARE0_MASK 0x4000000
+#define VGT_DEBUG_REG13__SPARE0__SHIFT 0x1a
+#define VGT_DEBUG_REG13__active_cm_sm_r0_q_MASK 0xf8000000
+#define VGT_DEBUG_REG13__active_cm_sm_r0_q__SHIFT 0x1b
+#define VGT_DEBUG_REG14__SPARE3_MASK 0xf
+#define VGT_DEBUG_REG14__SPARE3__SHIFT 0x0
+#define VGT_DEBUG_REG14__gsfetch_done_fifo_full_MASK 0x10
+#define VGT_DEBUG_REG14__gsfetch_done_fifo_full__SHIFT 0x4
+#define VGT_DEBUG_REG14__gs_rb_space_avail_r0_MASK 0x20
+#define VGT_DEBUG_REG14__gs_rb_space_avail_r0__SHIFT 0x5
+#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0_MASK 0x40
+#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0__SHIFT 0x6
+#define VGT_DEBUG_REG14__SPARE8_MASK 0x180
+#define VGT_DEBUG_REG14__SPARE8__SHIFT 0x7
+#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0_MASK 0x200
+#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0__SHIFT 0x9
+#define VGT_DEBUG_REG14__es_flush_cnt_busy_q_MASK 0x400
+#define VGT_DEBUG_REG14__es_flush_cnt_busy_q__SHIFT 0xa
+#define VGT_DEBUG_REG14__gs_tbl_full_r0_MASK 0x800
+#define VGT_DEBUG_REG14__gs_tbl_full_r0__SHIFT 0xb
+#define VGT_DEBUG_REG14__SPARE2_MASK 0x1ff000
+#define VGT_DEBUG_REG14__SPARE2__SHIFT 0xc
+#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy_MASK 0x200000
+#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy__SHIFT 0x15
+#define VGT_DEBUG_REG14__SPARE_MASK 0x1c00000
+#define VGT_DEBUG_REG14__SPARE__SHIFT 0x16
+#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q_MASK 0x2000000
+#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q__SHIFT 0x19
+#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0_MASK 0x4000000
+#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0__SHIFT 0x1a
+#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy_MASK 0x8000000
+#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy__SHIFT 0x1b
+#define VGT_DEBUG_REG14__SPARE1_MASK 0x10000000
+#define VGT_DEBUG_REG14__SPARE1__SHIFT 0x1c
+#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0_MASK 0x20000000
+#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x1d
+#define VGT_DEBUG_REG14__SPARE0_MASK 0x40000000
+#define VGT_DEBUG_REG14__SPARE0__SHIFT 0x1e
+#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q_MASK 0x80000000
+#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x1f
+#define VGT_DEBUG_REG15__cm_busy_q_MASK 0x1
+#define VGT_DEBUG_REG15__cm_busy_q__SHIFT 0x0
+#define VGT_DEBUG_REG15__counters_busy_q_MASK 0x2
+#define VGT_DEBUG_REG15__counters_busy_q__SHIFT 0x1
+#define VGT_DEBUG_REG15__output_fifo_empty_MASK 0x4
+#define VGT_DEBUG_REG15__output_fifo_empty__SHIFT 0x2
+#define VGT_DEBUG_REG15__output_fifo_full_MASK 0x8
+#define VGT_DEBUG_REG15__output_fifo_full__SHIFT 0x3
+#define VGT_DEBUG_REG15__counters_full_MASK 0x10
+#define VGT_DEBUG_REG15__counters_full__SHIFT 0x4
+#define VGT_DEBUG_REG15__active_sm_q_MASK 0x3e0
+#define VGT_DEBUG_REG15__active_sm_q__SHIFT 0x5
+#define VGT_DEBUG_REG15__entry_rdptr_q_MASK 0x7c00
+#define VGT_DEBUG_REG15__entry_rdptr_q__SHIFT 0xa
+#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q_MASK 0xf8000
+#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q__SHIFT 0xf
+#define VGT_DEBUG_REG15__SPARE25_MASK 0x3f00000
+#define VGT_DEBUG_REG15__SPARE25__SHIFT 0x14
+#define VGT_DEBUG_REG15__st_cut_mode_q_MASK 0xc000000
+#define VGT_DEBUG_REG15__st_cut_mode_q__SHIFT 0x1a
+#define VGT_DEBUG_REG15__gs_done_array_q_not_0_MASK 0x10000000
+#define VGT_DEBUG_REG15__gs_done_array_q_not_0__SHIFT 0x1c
+#define VGT_DEBUG_REG15__SPARE31_MASK 0xe0000000
+#define VGT_DEBUG_REG15__SPARE31__SHIFT 0x1d
+#define VGT_DEBUG_REG16__gog_busy_MASK 0x1
+#define VGT_DEBUG_REG16__gog_busy__SHIFT 0x0
+#define VGT_DEBUG_REG16__gog_state_q_MASK 0xe
+#define VGT_DEBUG_REG16__gog_state_q__SHIFT 0x1
+#define VGT_DEBUG_REG16__r0_rtr_MASK 0x10
+#define VGT_DEBUG_REG16__r0_rtr__SHIFT 0x4
+#define VGT_DEBUG_REG16__r1_rtr_MASK 0x20
+#define VGT_DEBUG_REG16__r1_rtr__SHIFT 0x5
+#define VGT_DEBUG_REG16__r1_upstream_rtr_MASK 0x40
+#define VGT_DEBUG_REG16__r1_upstream_rtr__SHIFT 0x6
+#define VGT_DEBUG_REG16__r2_vs_tbl_rtr_MASK 0x80
+#define VGT_DEBUG_REG16__r2_vs_tbl_rtr__SHIFT 0x7
+#define VGT_DEBUG_REG16__r2_prim_rtr_MASK 0x100
+#define VGT_DEBUG_REG16__r2_prim_rtr__SHIFT 0x8
+#define VGT_DEBUG_REG16__r2_indx_rtr_MASK 0x200
+#define VGT_DEBUG_REG16__r2_indx_rtr__SHIFT 0x9
+#define VGT_DEBUG_REG16__r2_rtr_MASK 0x400
+#define VGT_DEBUG_REG16__r2_rtr__SHIFT 0xa
+#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr_MASK 0x800
+#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr__SHIFT 0xb
+#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr_MASK 0x1000
+#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG16__indx_valid_r2_q_MASK 0x2000
+#define VGT_DEBUG_REG16__indx_valid_r2_q__SHIFT 0xd
+#define VGT_DEBUG_REG16__prim_valid_r2_q_MASK 0x4000
+#define VGT_DEBUG_REG16__prim_valid_r2_q__SHIFT 0xe
+#define VGT_DEBUG_REG16__valid_r2_q_MASK 0x8000
+#define VGT_DEBUG_REG16__valid_r2_q__SHIFT 0xf
+#define VGT_DEBUG_REG16__prim_valid_r1_q_MASK 0x10000
+#define VGT_DEBUG_REG16__prim_valid_r1_q__SHIFT 0x10
+#define VGT_DEBUG_REG16__indx_valid_r1_q_MASK 0x20000
+#define VGT_DEBUG_REG16__indx_valid_r1_q__SHIFT 0x11
+#define VGT_DEBUG_REG16__valid_r1_q_MASK 0x40000
+#define VGT_DEBUG_REG16__valid_r1_q__SHIFT 0x12
+#define VGT_DEBUG_REG16__indx_valid_r0_q_MASK 0x80000
+#define VGT_DEBUG_REG16__indx_valid_r0_q__SHIFT 0x13
+#define VGT_DEBUG_REG16__prim_valid_r0_q_MASK 0x100000
+#define VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT 0x14
+#define VGT_DEBUG_REG16__valid_r0_q_MASK 0x200000
+#define VGT_DEBUG_REG16__valid_r0_q__SHIFT 0x15
+#define VGT_DEBUG_REG16__send_event_q_MASK 0x400000
+#define VGT_DEBUG_REG16__send_event_q__SHIFT 0x16
+#define VGT_DEBUG_REG16__SPARE24_MASK 0x800000
+#define VGT_DEBUG_REG16__SPARE24__SHIFT 0x17
+#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q_MASK 0x1000000
+#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q__SHIFT 0x18
+#define VGT_DEBUG_REG16__gog_out_prim_state_sel_MASK 0xe000000
+#define VGT_DEBUG_REG16__gog_out_prim_state_sel__SHIFT 0x19
+#define VGT_DEBUG_REG16__multiple_streams_en_r1_q_MASK 0x10000000
+#define VGT_DEBUG_REG16__multiple_streams_en_r1_q__SHIFT 0x1c
+#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0_MASK 0x20000000
+#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT 0x1d
+#define VGT_DEBUG_REG16__num_gs_r2_q_not_0_MASK 0x40000000
+#define VGT_DEBUG_REG16__num_gs_r2_q_not_0__SHIFT 0x1e
+#define VGT_DEBUG_REG16__new_vs_thread_r2_MASK 0x80000000
+#define VGT_DEBUG_REG16__new_vs_thread_r2__SHIFT 0x1f
+#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0_MASK 0x3f
+#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0__SHIFT 0x0
+#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0_MASK 0xfc0
+#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0__SHIFT 0x6
+#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0_MASK 0x3f000
+#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0__SHIFT 0xc
+#define VGT_DEBUG_REG17__gog_out_indx_13_0_MASK 0xfffc0000
+#define VGT_DEBUG_REG17__gog_out_indx_13_0__SHIFT 0x12
+#define VGT_DEBUG_REG18__grp_vr_valid_MASK 0x1
+#define VGT_DEBUG_REG18__grp_vr_valid__SHIFT 0x0
+#define VGT_DEBUG_REG18__pipe0_dr_MASK 0x2
+#define VGT_DEBUG_REG18__pipe0_dr__SHIFT 0x1
+#define VGT_DEBUG_REG18__pipe1_dr_MASK 0x4
+#define VGT_DEBUG_REG18__pipe1_dr__SHIFT 0x2
+#define VGT_DEBUG_REG18__vr_grp_read_MASK 0x8
+#define VGT_DEBUG_REG18__vr_grp_read__SHIFT 0x3
+#define VGT_DEBUG_REG18__pipe0_rtr_MASK 0x10
+#define VGT_DEBUG_REG18__pipe0_rtr__SHIFT 0x4
+#define VGT_DEBUG_REG18__pipe1_rtr_MASK 0x20
+#define VGT_DEBUG_REG18__pipe1_rtr__SHIFT 0x5
+#define VGT_DEBUG_REG18__out_vr_indx_read_MASK 0x40
+#define VGT_DEBUG_REG18__out_vr_indx_read__SHIFT 0x6
+#define VGT_DEBUG_REG18__out_vr_prim_read_MASK 0x80
+#define VGT_DEBUG_REG18__out_vr_prim_read__SHIFT 0x7
+#define VGT_DEBUG_REG18__indices_to_send_q_MASK 0x700
+#define VGT_DEBUG_REG18__indices_to_send_q__SHIFT 0x8
+#define VGT_DEBUG_REG18__valid_indices_MASK 0x800
+#define VGT_DEBUG_REG18__valid_indices__SHIFT 0xb
+#define VGT_DEBUG_REG18__last_indx_of_prim_MASK 0x1000
+#define VGT_DEBUG_REG18__last_indx_of_prim__SHIFT 0xc
+#define VGT_DEBUG_REG18__indx0_new_d_MASK 0x2000
+#define VGT_DEBUG_REG18__indx0_new_d__SHIFT 0xd
+#define VGT_DEBUG_REG18__indx1_new_d_MASK 0x4000
+#define VGT_DEBUG_REG18__indx1_new_d__SHIFT 0xe
+#define VGT_DEBUG_REG18__indx2_new_d_MASK 0x8000
+#define VGT_DEBUG_REG18__indx2_new_d__SHIFT 0xf
+#define VGT_DEBUG_REG18__indx2_hit_d_MASK 0x10000
+#define VGT_DEBUG_REG18__indx2_hit_d__SHIFT 0x10
+#define VGT_DEBUG_REG18__indx1_hit_d_MASK 0x20000
+#define VGT_DEBUG_REG18__indx1_hit_d__SHIFT 0x11
+#define VGT_DEBUG_REG18__indx0_hit_d_MASK 0x40000
+#define VGT_DEBUG_REG18__indx0_hit_d__SHIFT 0x12
+#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q_MASK 0x80000
+#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q__SHIFT 0x13
+#define VGT_DEBUG_REG18__last_group_of_instance_r0_q_MASK 0x100000
+#define VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT 0x14
+#define VGT_DEBUG_REG18__null_primitive_r0_q_MASK 0x200000
+#define VGT_DEBUG_REG18__null_primitive_r0_q__SHIFT 0x15
+#define VGT_DEBUG_REG18__eop_r0_q_MASK 0x400000
+#define VGT_DEBUG_REG18__eop_r0_q__SHIFT 0x16
+#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d_MASK 0x800000
+#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d__SHIFT 0x17
+#define VGT_DEBUG_REG18__sub_prim_type_r0_q_MASK 0x7000000
+#define VGT_DEBUG_REG18__sub_prim_type_r0_q__SHIFT 0x18
+#define VGT_DEBUG_REG18__gs_scenario_a_r0_q_MASK 0x8000000
+#define VGT_DEBUG_REG18__gs_scenario_a_r0_q__SHIFT 0x1b
+#define VGT_DEBUG_REG18__gs_scenario_b_r0_q_MASK 0x10000000
+#define VGT_DEBUG_REG18__gs_scenario_b_r0_q__SHIFT 0x1c
+#define VGT_DEBUG_REG18__components_valid_r0_q_MASK 0xe0000000
+#define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT 0x1d
+#define VGT_DEBUG_REG19__separate_out_busy_q_MASK 0x1
+#define VGT_DEBUG_REG19__separate_out_busy_q__SHIFT 0x0
+#define VGT_DEBUG_REG19__separate_out_indx_busy_q_MASK 0x2
+#define VGT_DEBUG_REG19__separate_out_indx_busy_q__SHIFT 0x1
+#define VGT_DEBUG_REG19__prim_buffer_empty_MASK 0x4
+#define VGT_DEBUG_REG19__prim_buffer_empty__SHIFT 0x2
+#define VGT_DEBUG_REG19__prim_buffer_full_MASK 0x8
+#define VGT_DEBUG_REG19__prim_buffer_full__SHIFT 0x3
+#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q_MASK 0x10
+#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q__SHIFT 0x4
+#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q_MASK 0x20
+#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q__SHIFT 0x5
+#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q_MASK 0x40
+#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q__SHIFT 0x6
+#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q_MASK 0x80
+#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q__SHIFT 0x7
+#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q_MASK 0x100
+#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q__SHIFT 0x8
+#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q_MASK 0x200
+#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q__SHIFT 0x9
+#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q_MASK 0x400
+#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q__SHIFT 0xa
+#define VGT_DEBUG_REG19__hold_prim_MASK 0x800
+#define VGT_DEBUG_REG19__hold_prim__SHIFT 0xb
+#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q_MASK 0x1000
+#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q__SHIFT 0xc
+#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q_MASK 0x2000
+#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q__SHIFT 0xd
+#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q_MASK 0x4000
+#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q__SHIFT 0xe
+#define VGT_DEBUG_REG19__new_packet_q_MASK 0x8000
+#define VGT_DEBUG_REG19__new_packet_q__SHIFT 0xf
+#define VGT_DEBUG_REG19__buffered_prim_event_MASK 0x10000
+#define VGT_DEBUG_REG19__buffered_prim_event__SHIFT 0x10
+#define VGT_DEBUG_REG19__buffered_prim_null_primitive_MASK 0x20000
+#define VGT_DEBUG_REG19__buffered_prim_null_primitive__SHIFT 0x11
+#define VGT_DEBUG_REG19__buffered_prim_eop_MASK 0x40000
+#define VGT_DEBUG_REG19__buffered_prim_eop__SHIFT 0x12
+#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect_MASK 0x80000
+#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect__SHIFT 0x13
+#define VGT_DEBUG_REG19__buffered_prim_type_event_MASK 0x3f00000
+#define VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT 0x14
+#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q_MASK 0x4000000
+#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q__SHIFT 0x1a
+#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q_MASK 0x8000000
+#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q__SHIFT 0x1b
+#define VGT_DEBUG_REG19__num_new_unique_rel_indx_MASK 0x30000000
+#define VGT_DEBUG_REG19__num_new_unique_rel_indx__SHIFT 0x1c
+#define VGT_DEBUG_REG19__null_terminate_vtx_vector_MASK 0x40000000
+#define VGT_DEBUG_REG19__null_terminate_vtx_vector__SHIFT 0x1e
+#define VGT_DEBUG_REG19__filter_event_MASK 0x80000000
+#define VGT_DEBUG_REG19__filter_event__SHIFT 0x1f
+#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex_MASK 0xffff
+#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex__SHIFT 0x0
+#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK 0x10000
+#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT 0x10
+#define VGT_DEBUG_REG20__SPARE17_MASK 0x20000
+#define VGT_DEBUG_REG20__SPARE17__SHIFT 0x11
+#define VGT_DEBUG_REG20__alloc_counter_q_MASK 0x3c0000
+#define VGT_DEBUG_REG20__alloc_counter_q__SHIFT 0x12
+#define VGT_DEBUG_REG20__curr_dealloc_distance_q_MASK 0x1fc00000
+#define VGT_DEBUG_REG20__curr_dealloc_distance_q__SHIFT 0x16
+#define VGT_DEBUG_REG20__new_allocate_q_MASK 0x20000000
+#define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x1d
+#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0_MASK 0x40000000
+#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0__SHIFT 0x1e
+#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0_MASK 0x80000000
+#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0__SHIFT 0x1f
+#define VGT_DEBUG_REG21__out_indx_fifo_empty_MASK 0x1
+#define VGT_DEBUG_REG21__out_indx_fifo_empty__SHIFT 0x0
+#define VGT_DEBUG_REG21__indx_side_fifo_empty_MASK 0x2
+#define VGT_DEBUG_REG21__indx_side_fifo_empty__SHIFT 0x1
+#define VGT_DEBUG_REG21__pipe0_dr_MASK 0x4
+#define VGT_DEBUG_REG21__pipe0_dr__SHIFT 0x2
+#define VGT_DEBUG_REG21__pipe1_dr_MASK 0x8
+#define VGT_DEBUG_REG21__pipe1_dr__SHIFT 0x3
+#define VGT_DEBUG_REG21__pipe2_dr_MASK 0x10
+#define VGT_DEBUG_REG21__pipe2_dr__SHIFT 0x4
+#define VGT_DEBUG_REG21__vsthread_buff_empty_MASK 0x20
+#define VGT_DEBUG_REG21__vsthread_buff_empty__SHIFT 0x5
+#define VGT_DEBUG_REG21__out_indx_fifo_full_MASK 0x40
+#define VGT_DEBUG_REG21__out_indx_fifo_full__SHIFT 0x6
+#define VGT_DEBUG_REG21__indx_side_fifo_full_MASK 0x80
+#define VGT_DEBUG_REG21__indx_side_fifo_full__SHIFT 0x7
+#define VGT_DEBUG_REG21__pipe0_rtr_MASK 0x100
+#define VGT_DEBUG_REG21__pipe0_rtr__SHIFT 0x8
+#define VGT_DEBUG_REG21__pipe1_rtr_MASK 0x200
+#define VGT_DEBUG_REG21__pipe1_rtr__SHIFT 0x9
+#define VGT_DEBUG_REG21__pipe2_rtr_MASK 0x400
+#define VGT_DEBUG_REG21__pipe2_rtr__SHIFT 0xa
+#define VGT_DEBUG_REG21__vsthread_buff_full_MASK 0x800
+#define VGT_DEBUG_REG21__vsthread_buff_full__SHIFT 0xb
+#define VGT_DEBUG_REG21__interfaces_rtr_MASK 0x1000
+#define VGT_DEBUG_REG21__interfaces_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG21__indx_count_q_not_0_MASK 0x2000
+#define VGT_DEBUG_REG21__indx_count_q_not_0__SHIFT 0xd
+#define VGT_DEBUG_REG21__wait_for_external_eopg_q_MASK 0x4000
+#define VGT_DEBUG_REG21__wait_for_external_eopg_q__SHIFT 0xe
+#define VGT_DEBUG_REG21__full_state_p1_q_MASK 0x8000
+#define VGT_DEBUG_REG21__full_state_p1_q__SHIFT 0xf
+#define VGT_DEBUG_REG21__indx_side_indx_valid_MASK 0x10000
+#define VGT_DEBUG_REG21__indx_side_indx_valid__SHIFT 0x10
+#define VGT_DEBUG_REG21__stateid_p0_q_MASK 0xe0000
+#define VGT_DEBUG_REG21__stateid_p0_q__SHIFT 0x11
+#define VGT_DEBUG_REG21__is_event_p0_q_MASK 0x100000
+#define VGT_DEBUG_REG21__is_event_p0_q__SHIFT 0x14
+#define VGT_DEBUG_REG21__lshs_dealloc_p1_MASK 0x200000
+#define VGT_DEBUG_REG21__lshs_dealloc_p1__SHIFT 0x15
+#define VGT_DEBUG_REG21__stream_id_r2_q_MASK 0x400000
+#define VGT_DEBUG_REG21__stream_id_r2_q__SHIFT 0x16
+#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0_MASK 0x800000
+#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0__SHIFT 0x17
+#define VGT_DEBUG_REG21__buff_full_p1_MASK 0x1000000
+#define VGT_DEBUG_REG21__buff_full_p1__SHIFT 0x18
+#define VGT_DEBUG_REG21__strmout_valid_p1_MASK 0x2000000
+#define VGT_DEBUG_REG21__strmout_valid_p1__SHIFT 0x19
+#define VGT_DEBUG_REG21__eotg_r2_q_MASK 0x4000000
+#define VGT_DEBUG_REG21__eotg_r2_q__SHIFT 0x1a
+#define VGT_DEBUG_REG21__null_r2_q_MASK 0x8000000
+#define VGT_DEBUG_REG21__null_r2_q__SHIFT 0x1b
+#define VGT_DEBUG_REG21__p0_dr_MASK 0x10000000
+#define VGT_DEBUG_REG21__p0_dr__SHIFT 0x1c
+#define VGT_DEBUG_REG21__p0_rtr_MASK 0x20000000
+#define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x1d
+#define VGT_DEBUG_REG21__eopg_p0_q_MASK 0x40000000
+#define VGT_DEBUG_REG21__eopg_p0_q__SHIFT 0x1e
+#define VGT_DEBUG_REG21__p0_nobp_MASK 0x80000000
+#define VGT_DEBUG_REG21__p0_nobp__SHIFT 0x1f
+#define VGT_DEBUG_REG22__cm_state16_MASK 0x3
+#define VGT_DEBUG_REG22__cm_state16__SHIFT 0x0
+#define VGT_DEBUG_REG22__cm_state17_MASK 0xc
+#define VGT_DEBUG_REG22__cm_state17__SHIFT 0x2
+#define VGT_DEBUG_REG22__cm_state18_MASK 0x30
+#define VGT_DEBUG_REG22__cm_state18__SHIFT 0x4
+#define VGT_DEBUG_REG22__cm_state19_MASK 0xc0
+#define VGT_DEBUG_REG22__cm_state19__SHIFT 0x6
+#define VGT_DEBUG_REG22__cm_state20_MASK 0x300
+#define VGT_DEBUG_REG22__cm_state20__SHIFT 0x8
+#define VGT_DEBUG_REG22__cm_state21_MASK 0xc00
+#define VGT_DEBUG_REG22__cm_state21__SHIFT 0xa
+#define VGT_DEBUG_REG22__cm_state22_MASK 0x3000
+#define VGT_DEBUG_REG22__cm_state22__SHIFT 0xc
+#define VGT_DEBUG_REG22__cm_state23_MASK 0xc000
+#define VGT_DEBUG_REG22__cm_state23__SHIFT 0xe
+#define VGT_DEBUG_REG22__cm_state24_MASK 0x30000
+#define VGT_DEBUG_REG22__cm_state24__SHIFT 0x10
+#define VGT_DEBUG_REG22__cm_state25_MASK 0xc0000
+#define VGT_DEBUG_REG22__cm_state25__SHIFT 0x12
+#define VGT_DEBUG_REG22__cm_state26_MASK 0x300000
+#define VGT_DEBUG_REG22__cm_state26__SHIFT 0x14
+#define VGT_DEBUG_REG22__cm_state27_MASK 0xc00000
+#define VGT_DEBUG_REG22__cm_state27__SHIFT 0x16
+#define VGT_DEBUG_REG22__cm_state28_MASK 0x3000000
+#define VGT_DEBUG_REG22__cm_state28__SHIFT 0x18
+#define VGT_DEBUG_REG22__cm_state29_MASK 0xc000000
+#define VGT_DEBUG_REG22__cm_state29__SHIFT 0x1a
+#define VGT_DEBUG_REG22__cm_state30_MASK 0x30000000
+#define VGT_DEBUG_REG22__cm_state30__SHIFT 0x1c
+#define VGT_DEBUG_REG22__cm_state31_MASK 0xc0000000
+#define VGT_DEBUG_REG22__cm_state31__SHIFT 0x1e
+#define VGT_DEBUG_REG23__frmt_busy_MASK 0x1
+#define VGT_DEBUG_REG23__frmt_busy__SHIFT 0x0
+#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr_MASK 0x2
+#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr__SHIFT 0x1
+#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr_MASK 0x4
+#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr__SHIFT 0x2
+#define VGT_DEBUG_REG23__prim_r3_rtr_MASK 0x8
+#define VGT_DEBUG_REG23__prim_r3_rtr__SHIFT 0x3
+#define VGT_DEBUG_REG23__prim_r2_rtr_MASK 0x10
+#define VGT_DEBUG_REG23__prim_r2_rtr__SHIFT 0x4
+#define VGT_DEBUG_REG23__vert_r3_rtr_MASK 0x20
+#define VGT_DEBUG_REG23__vert_r3_rtr__SHIFT 0x5
+#define VGT_DEBUG_REG23__vert_r2_rtr_MASK 0x40
+#define VGT_DEBUG_REG23__vert_r2_rtr__SHIFT 0x6
+#define VGT_DEBUG_REG23__vert_r1_rtr_MASK 0x80
+#define VGT_DEBUG_REG23__vert_r1_rtr__SHIFT 0x7
+#define VGT_DEBUG_REG23__vert_r0_rtr_MASK 0x100
+#define VGT_DEBUG_REG23__vert_r0_rtr__SHIFT 0x8
+#define VGT_DEBUG_REG23__prim_fifo_empty_MASK 0x200
+#define VGT_DEBUG_REG23__prim_fifo_empty__SHIFT 0x9
+#define VGT_DEBUG_REG23__prim_fifo_full_MASK 0x400
+#define VGT_DEBUG_REG23__prim_fifo_full__SHIFT 0xa
+#define VGT_DEBUG_REG23__vert_dr_r2_q_MASK 0x800
+#define VGT_DEBUG_REG23__vert_dr_r2_q__SHIFT 0xb
+#define VGT_DEBUG_REG23__prim_dr_r2_q_MASK 0x1000
+#define VGT_DEBUG_REG23__prim_dr_r2_q__SHIFT 0xc
+#define VGT_DEBUG_REG23__vert_dr_r1_q_MASK 0x2000
+#define VGT_DEBUG_REG23__vert_dr_r1_q__SHIFT 0xd
+#define VGT_DEBUG_REG23__vert_dr_r0_q_MASK 0x4000
+#define VGT_DEBUG_REG23__vert_dr_r0_q__SHIFT 0xe
+#define VGT_DEBUG_REG23__new_verts_r2_q_MASK 0x18000
+#define VGT_DEBUG_REG23__new_verts_r2_q__SHIFT 0xf
+#define VGT_DEBUG_REG23__verts_sent_r2_q_MASK 0x1e0000
+#define VGT_DEBUG_REG23__verts_sent_r2_q__SHIFT 0x11
+#define VGT_DEBUG_REG23__prim_state_sel_r2_q_MASK 0xe00000
+#define VGT_DEBUG_REG23__prim_state_sel_r2_q__SHIFT 0x15
+#define VGT_DEBUG_REG23__SPARE_MASK 0xff000000
+#define VGT_DEBUG_REG23__SPARE__SHIFT 0x18
+#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0_MASK 0xffffff
+#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0__SHIFT 0x0
+#define VGT_DEBUG_REG24__dependent_st_cut_mode_q_MASK 0x3000000
+#define VGT_DEBUG_REG24__dependent_st_cut_mode_q__SHIFT 0x18
+#define VGT_DEBUG_REG24__SPARE31_MASK 0xfc000000
+#define VGT_DEBUG_REG24__SPARE31__SHIFT 0x1a
+#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x3ffffff
+#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0__SHIFT 0x0
+#define VGT_DEBUG_REG25__active_sm_r0_q_MASK 0x3c000000
+#define VGT_DEBUG_REG25__active_sm_r0_q__SHIFT 0x1a
+#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q_MASK 0x40000000
+#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q__SHIFT 0x1e
+#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q_MASK 0x80000000
+#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q__SHIFT 0x1f
+#define VGT_DEBUG_REG26__cm_state0_MASK 0x3
+#define VGT_DEBUG_REG26__cm_state0__SHIFT 0x0
+#define VGT_DEBUG_REG26__cm_state1_MASK 0xc
+#define VGT_DEBUG_REG26__cm_state1__SHIFT 0x2
+#define VGT_DEBUG_REG26__cm_state2_MASK 0x30
+#define VGT_DEBUG_REG26__cm_state2__SHIFT 0x4
+#define VGT_DEBUG_REG26__cm_state3_MASK 0xc0
+#define VGT_DEBUG_REG26__cm_state3__SHIFT 0x6
+#define VGT_DEBUG_REG26__cm_state4_MASK 0x300
+#define VGT_DEBUG_REG26__cm_state4__SHIFT 0x8
+#define VGT_DEBUG_REG26__cm_state5_MASK 0xc00
+#define VGT_DEBUG_REG26__cm_state5__SHIFT 0xa
+#define VGT_DEBUG_REG26__cm_state6_MASK 0x3000
+#define VGT_DEBUG_REG26__cm_state6__SHIFT 0xc
+#define VGT_DEBUG_REG26__cm_state7_MASK 0xc000
+#define VGT_DEBUG_REG26__cm_state7__SHIFT 0xe
+#define VGT_DEBUG_REG26__cm_state8_MASK 0x30000
+#define VGT_DEBUG_REG26__cm_state8__SHIFT 0x10
+#define VGT_DEBUG_REG26__cm_state9_MASK 0xc0000
+#define VGT_DEBUG_REG26__cm_state9__SHIFT 0x12
+#define VGT_DEBUG_REG26__cm_state10_MASK 0x300000
+#define VGT_DEBUG_REG26__cm_state10__SHIFT 0x14
+#define VGT_DEBUG_REG26__cm_state11_MASK 0xc00000
+#define VGT_DEBUG_REG26__cm_state11__SHIFT 0x16
+#define VGT_DEBUG_REG26__cm_state12_MASK 0x3000000
+#define VGT_DEBUG_REG26__cm_state12__SHIFT 0x18
+#define VGT_DEBUG_REG26__cm_state13_MASK 0xc000000
+#define VGT_DEBUG_REG26__cm_state13__SHIFT 0x1a
+#define VGT_DEBUG_REG26__cm_state14_MASK 0x30000000
+#define VGT_DEBUG_REG26__cm_state14__SHIFT 0x1c
+#define VGT_DEBUG_REG26__cm_state15_MASK 0xc0000000
+#define VGT_DEBUG_REG26__cm_state15__SHIFT 0x1e
+#define VGT_DEBUG_REG27__pipe0_dr_MASK 0x1
+#define VGT_DEBUG_REG27__pipe0_dr__SHIFT 0x0
+#define VGT_DEBUG_REG27__gsc0_dr_MASK 0x2
+#define VGT_DEBUG_REG27__gsc0_dr__SHIFT 0x1
+#define VGT_DEBUG_REG27__pipe1_dr_MASK 0x4
+#define VGT_DEBUG_REG27__pipe1_dr__SHIFT 0x2
+#define VGT_DEBUG_REG27__tm_pt_event_rtr_MASK 0x8
+#define VGT_DEBUG_REG27__tm_pt_event_rtr__SHIFT 0x3
+#define VGT_DEBUG_REG27__pipe0_rtr_MASK 0x10
+#define VGT_DEBUG_REG27__pipe0_rtr__SHIFT 0x4
+#define VGT_DEBUG_REG27__gsc0_rtr_MASK 0x20
+#define VGT_DEBUG_REG27__gsc0_rtr__SHIFT 0x5
+#define VGT_DEBUG_REG27__pipe1_rtr_MASK 0x40
+#define VGT_DEBUG_REG27__pipe1_rtr__SHIFT 0x6
+#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q_MASK 0x80
+#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q__SHIFT 0x7
+#define VGT_DEBUG_REG27__indices_to_send_p0_q_MASK 0x300
+#define VGT_DEBUG_REG27__indices_to_send_p0_q__SHIFT 0x8
+#define VGT_DEBUG_REG27__event_flag_p1_q_MASK 0x400
+#define VGT_DEBUG_REG27__event_flag_p1_q__SHIFT 0xa
+#define VGT_DEBUG_REG27__eop_p1_q_MASK 0x800
+#define VGT_DEBUG_REG27__eop_p1_q__SHIFT 0xb
+#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q_MASK 0x3000
+#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q__SHIFT 0xc
+#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q_MASK 0x4000
+#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q__SHIFT 0xe
+#define VGT_DEBUG_REG27__gsc_eop_p0_q_MASK 0x8000
+#define VGT_DEBUG_REG27__gsc_eop_p0_q__SHIFT 0xf
+#define VGT_DEBUG_REG27__gsc_2cycle_output_MASK 0x10000
+#define VGT_DEBUG_REG27__gsc_2cycle_output__SHIFT 0x10
+#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q_MASK 0x20000
+#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q__SHIFT 0x11
+#define VGT_DEBUG_REG27__last_indx_of_vsprim_MASK 0x40000
+#define VGT_DEBUG_REG27__last_indx_of_vsprim__SHIFT 0x12
+#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q_MASK 0x80000
+#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q__SHIFT 0x13
+#define VGT_DEBUG_REG27__gsc_indx_count_p0_q_MASK 0x7ff00000
+#define VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT 0x14
+#define VGT_DEBUG_REG27__last_vsprim_of_gsprim_MASK 0x80000000
+#define VGT_DEBUG_REG27__last_vsprim_of_gsprim__SHIFT 0x1f
+#define VGT_DEBUG_REG28__con_state_q_MASK 0xf
+#define VGT_DEBUG_REG28__con_state_q__SHIFT 0x0
+#define VGT_DEBUG_REG28__second_cycle_q_MASK 0x10
+#define VGT_DEBUG_REG28__second_cycle_q__SHIFT 0x4
+#define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x20
+#define VGT_DEBUG_REG28__process_tri_middle_p0_q__SHIFT 0x5
+#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q_MASK 0x40
+#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
+#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q_MASK 0x80
+#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q__SHIFT 0x7
+#define VGT_DEBUG_REG28__pipe0_patch_dr_MASK 0x100
+#define VGT_DEBUG_REG28__pipe0_patch_dr__SHIFT 0x8
+#define VGT_DEBUG_REG28__pipe0_edge_dr_MASK 0x200
+#define VGT_DEBUG_REG28__pipe0_edge_dr__SHIFT 0x9
+#define VGT_DEBUG_REG28__pipe1_dr_MASK 0x400
+#define VGT_DEBUG_REG28__pipe1_dr__SHIFT 0xa
+#define VGT_DEBUG_REG28__pipe0_patch_rtr_MASK 0x800
+#define VGT_DEBUG_REG28__pipe0_patch_rtr__SHIFT 0xb
+#define VGT_DEBUG_REG28__pipe0_edge_rtr_MASK 0x1000
+#define VGT_DEBUG_REG28__pipe0_edge_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG28__pipe1_rtr_MASK 0x2000
+#define VGT_DEBUG_REG28__pipe1_rtr__SHIFT 0xd
+#define VGT_DEBUG_REG28__outer_parity_p0_q_MASK 0x4000
+#define VGT_DEBUG_REG28__outer_parity_p0_q__SHIFT 0xe
+#define VGT_DEBUG_REG28__parallel_parity_p0_q_MASK 0x8000
+#define VGT_DEBUG_REG28__parallel_parity_p0_q__SHIFT 0xf
+#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q_MASK 0x10000
+#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q__SHIFT 0x10
+#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q_MASK 0x20000
+#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q__SHIFT 0x11
+#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q_MASK 0x40000
+#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q__SHIFT 0x12
+#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1_MASK 0x80000
+#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1__SHIFT 0x13
+#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1_MASK 0x100000
+#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT 0x14
+#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q_MASK 0x200000
+#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
+#define VGT_DEBUG_REG28__advance_outer_point_p1_MASK 0x400000
+#define VGT_DEBUG_REG28__advance_outer_point_p1__SHIFT 0x16
+#define VGT_DEBUG_REG28__advance_inner_point_p1_MASK 0x800000
+#define VGT_DEBUG_REG28__advance_inner_point_p1__SHIFT 0x17
+#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q_MASK 0x1000000
+#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q__SHIFT 0x18
+#define VGT_DEBUG_REG28__pipe1_outer1_rtr_MASK 0x2000000
+#define VGT_DEBUG_REG28__pipe1_outer1_rtr__SHIFT 0x19
+#define VGT_DEBUG_REG28__pipe1_outer2_rtr_MASK 0x4000000
+#define VGT_DEBUG_REG28__pipe1_outer2_rtr__SHIFT 0x1a
+#define VGT_DEBUG_REG28__pipe1_inner1_rtr_MASK 0x8000000
+#define VGT_DEBUG_REG28__pipe1_inner1_rtr__SHIFT 0x1b
+#define VGT_DEBUG_REG28__pipe1_inner2_rtr_MASK 0x10000000
+#define VGT_DEBUG_REG28__pipe1_inner2_rtr__SHIFT 0x1c
+#define VGT_DEBUG_REG28__pipe1_patch_rtr_MASK 0x20000000
+#define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x1d
+#define VGT_DEBUG_REG28__pipe1_edge_rtr_MASK 0x40000000
+#define VGT_DEBUG_REG28__pipe1_edge_rtr__SHIFT 0x1e
+#define VGT_DEBUG_REG28__use_stored_inner_q_ring2_MASK 0x80000000
+#define VGT_DEBUG_REG28__use_stored_inner_q_ring2__SHIFT 0x1f
+#define VGT_DEBUG_REG29__con_state_q_MASK 0xf
+#define VGT_DEBUG_REG29__con_state_q__SHIFT 0x0
+#define VGT_DEBUG_REG29__second_cycle_q_MASK 0x10
+#define VGT_DEBUG_REG29__second_cycle_q__SHIFT 0x4
+#define VGT_DEBUG_REG29__process_tri_middle_p0_q_MASK 0x20
+#define VGT_DEBUG_REG29__process_tri_middle_p0_q__SHIFT 0x5
+#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q_MASK 0x40
+#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
+#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q_MASK 0x80
+#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q__SHIFT 0x7
+#define VGT_DEBUG_REG29__pipe0_patch_dr_MASK 0x100
+#define VGT_DEBUG_REG29__pipe0_patch_dr__SHIFT 0x8
+#define VGT_DEBUG_REG29__pipe0_edge_dr_MASK 0x200
+#define VGT_DEBUG_REG29__pipe0_edge_dr__SHIFT 0x9
+#define VGT_DEBUG_REG29__pipe1_dr_MASK 0x400
+#define VGT_DEBUG_REG29__pipe1_dr__SHIFT 0xa
+#define VGT_DEBUG_REG29__pipe0_patch_rtr_MASK 0x800
+#define VGT_DEBUG_REG29__pipe0_patch_rtr__SHIFT 0xb
+#define VGT_DEBUG_REG29__pipe0_edge_rtr_MASK 0x1000
+#define VGT_DEBUG_REG29__pipe0_edge_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG29__pipe1_rtr_MASK 0x2000
+#define VGT_DEBUG_REG29__pipe1_rtr__SHIFT 0xd
+#define VGT_DEBUG_REG29__outer_parity_p0_q_MASK 0x4000
+#define VGT_DEBUG_REG29__outer_parity_p0_q__SHIFT 0xe
+#define VGT_DEBUG_REG29__parallel_parity_p0_q_MASK 0x8000
+#define VGT_DEBUG_REG29__parallel_parity_p0_q__SHIFT 0xf
+#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q_MASK 0x10000
+#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q__SHIFT 0x10
+#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q_MASK 0x20000
+#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q__SHIFT 0x11
+#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q_MASK 0x40000
+#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q__SHIFT 0x12
+#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1_MASK 0x80000
+#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1__SHIFT 0x13
+#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1_MASK 0x100000
+#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT 0x14
+#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q_MASK 0x200000
+#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
+#define VGT_DEBUG_REG29__advance_outer_point_p1_MASK 0x400000
+#define VGT_DEBUG_REG29__advance_outer_point_p1__SHIFT 0x16
+#define VGT_DEBUG_REG29__advance_inner_point_p1_MASK 0x800000
+#define VGT_DEBUG_REG29__advance_inner_point_p1__SHIFT 0x17
+#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q_MASK 0x1000000
+#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q__SHIFT 0x18
+#define VGT_DEBUG_REG29__pipe1_outer1_rtr_MASK 0x2000000
+#define VGT_DEBUG_REG29__pipe1_outer1_rtr__SHIFT 0x19
+#define VGT_DEBUG_REG29__pipe1_outer2_rtr_MASK 0x4000000
+#define VGT_DEBUG_REG29__pipe1_outer2_rtr__SHIFT 0x1a
+#define VGT_DEBUG_REG29__pipe1_inner1_rtr_MASK 0x8000000
+#define VGT_DEBUG_REG29__pipe1_inner1_rtr__SHIFT 0x1b
+#define VGT_DEBUG_REG29__pipe1_inner2_rtr_MASK 0x10000000
+#define VGT_DEBUG_REG29__pipe1_inner2_rtr__SHIFT 0x1c
+#define VGT_DEBUG_REG29__pipe1_patch_rtr_MASK 0x20000000
+#define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x1d
+#define VGT_DEBUG_REG29__pipe1_edge_rtr_MASK 0x40000000
+#define VGT_DEBUG_REG29__pipe1_edge_rtr__SHIFT 0x1e
+#define VGT_DEBUG_REG29__use_stored_inner_q_ring3_MASK 0x80000000
+#define VGT_DEBUG_REG29__use_stored_inner_q_ring3__SHIFT 0x1f
+#define VGT_DEBUG_REG30__pipe0_dr_MASK 0x1
+#define VGT_DEBUG_REG30__pipe0_dr__SHIFT 0x0
+#define VGT_DEBUG_REG30__pipe0_tf_dr_MASK 0x2
+#define VGT_DEBUG_REG30__pipe0_tf_dr__SHIFT 0x1
+#define VGT_DEBUG_REG30__pipe2_dr_MASK 0x4
+#define VGT_DEBUG_REG30__pipe2_dr__SHIFT 0x2
+#define VGT_DEBUG_REG30__event_or_null_p0_q_MASK 0x8
+#define VGT_DEBUG_REG30__event_or_null_p0_q__SHIFT 0x3
+#define VGT_DEBUG_REG30__pipe0_rtr_MASK 0x10
+#define VGT_DEBUG_REG30__pipe0_rtr__SHIFT 0x4
+#define VGT_DEBUG_REG30__pipe1_rtr_MASK 0x20
+#define VGT_DEBUG_REG30__pipe1_rtr__SHIFT 0x5
+#define VGT_DEBUG_REG30__pipe1_tf_rtr_MASK 0x40
+#define VGT_DEBUG_REG30__pipe1_tf_rtr__SHIFT 0x6
+#define VGT_DEBUG_REG30__pipe2_rtr_MASK 0x80
+#define VGT_DEBUG_REG30__pipe2_rtr__SHIFT 0x7
+#define VGT_DEBUG_REG30__ttp_patch_fifo_full_MASK 0x100
+#define VGT_DEBUG_REG30__ttp_patch_fifo_full__SHIFT 0x8
+#define VGT_DEBUG_REG30__ttp_patch_fifo_empty_MASK 0x200
+#define VGT_DEBUG_REG30__ttp_patch_fifo_empty__SHIFT 0x9
+#define VGT_DEBUG_REG30__ttp_tf0_fifo_empty_MASK 0x400
+#define VGT_DEBUG_REG30__ttp_tf0_fifo_empty__SHIFT 0xa
+#define VGT_DEBUG_REG30__ttp_tf1_fifo_empty_MASK 0x800
+#define VGT_DEBUG_REG30__ttp_tf1_fifo_empty__SHIFT 0xb
+#define VGT_DEBUG_REG30__ttp_tf2_fifo_empty_MASK 0x1000
+#define VGT_DEBUG_REG30__ttp_tf2_fifo_empty__SHIFT 0xc
+#define VGT_DEBUG_REG30__ttp_tf3_fifo_empty_MASK 0x2000
+#define VGT_DEBUG_REG30__ttp_tf3_fifo_empty__SHIFT 0xd
+#define VGT_DEBUG_REG30__ttp_tf4_fifo_empty_MASK 0x4000
+#define VGT_DEBUG_REG30__ttp_tf4_fifo_empty__SHIFT 0xe
+#define VGT_DEBUG_REG30__ttp_tf5_fifo_empty_MASK 0x8000
+#define VGT_DEBUG_REG30__ttp_tf5_fifo_empty__SHIFT 0xf
+#define VGT_DEBUG_REG30__tf_fetch_state_q_MASK 0x70000
+#define VGT_DEBUG_REG30__tf_fetch_state_q__SHIFT 0x10
+#define VGT_DEBUG_REG30__last_tf_of_tg_MASK 0x80000
+#define VGT_DEBUG_REG30__last_tf_of_tg__SHIFT 0x13
+#define VGT_DEBUG_REG30__tf_pointer_p0_q_MASK 0xf00000
+#define VGT_DEBUG_REG30__tf_pointer_p0_q__SHIFT 0x14
+#define VGT_DEBUG_REG30__dynamic_hs_p0_q_MASK 0x1000000
+#define VGT_DEBUG_REG30__dynamic_hs_p0_q__SHIFT 0x18
+#define VGT_DEBUG_REG30__first_fetch_of_tg_p0_q_MASK 0x2000000
+#define VGT_DEBUG_REG30__first_fetch_of_tg_p0_q__SHIFT 0x19
+#define VGT_DEBUG_REG30__first_data_ret_of_req_p0_q_MASK 0x4000000
+#define VGT_DEBUG_REG30__first_data_ret_of_req_p0_q__SHIFT 0x1a
+#define VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q_MASK 0x8000000
+#define VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q__SHIFT 0x1b
+#define VGT_DEBUG_REG30__tf_xfer_count_p2_q_MASK 0x30000000
+#define VGT_DEBUG_REG30__tf_xfer_count_p2_q__SHIFT 0x1c
+#define VGT_DEBUG_REG30__pipe4_dr_MASK 0x40000000
+#define VGT_DEBUG_REG30__pipe4_dr__SHIFT 0x1e
+#define VGT_DEBUG_REG30__pipe4_rtr_MASK 0x80000000
+#define VGT_DEBUG_REG30__pipe4_rtr__SHIFT 0x1f
+#define VGT_DEBUG_REG31__pipe0_dr_MASK 0x1
+#define VGT_DEBUG_REG31__pipe0_dr__SHIFT 0x0
+#define VGT_DEBUG_REG31__pipe0_rtr_MASK 0x2
+#define VGT_DEBUG_REG31__pipe0_rtr__SHIFT 0x1
+#define VGT_DEBUG_REG31__pipe1_outer_dr_MASK 0x4
+#define VGT_DEBUG_REG31__pipe1_outer_dr__SHIFT 0x2
+#define VGT_DEBUG_REG31__pipe1_inner_dr_MASK 0x8
+#define VGT_DEBUG_REG31__pipe1_inner_dr__SHIFT 0x3
+#define VGT_DEBUG_REG31__pipe2_outer_dr_MASK 0x10
+#define VGT_DEBUG_REG31__pipe2_outer_dr__SHIFT 0x4
+#define VGT_DEBUG_REG31__pipe2_inner_dr_MASK 0x20
+#define VGT_DEBUG_REG31__pipe2_inner_dr__SHIFT 0x5
+#define VGT_DEBUG_REG31__pipe3_outer_dr_MASK 0x40
+#define VGT_DEBUG_REG31__pipe3_outer_dr__SHIFT 0x6
+#define VGT_DEBUG_REG31__pipe3_inner_dr_MASK 0x80
+#define VGT_DEBUG_REG31__pipe3_inner_dr__SHIFT 0x7
+#define VGT_DEBUG_REG31__pipe4_outer_dr_MASK 0x100
+#define VGT_DEBUG_REG31__pipe4_outer_dr__SHIFT 0x8
+#define VGT_DEBUG_REG31__pipe4_inner_dr_MASK 0x200
+#define VGT_DEBUG_REG31__pipe4_inner_dr__SHIFT 0x9
+#define VGT_DEBUG_REG31__pipe5_outer_dr_MASK 0x400
+#define VGT_DEBUG_REG31__pipe5_outer_dr__SHIFT 0xa
+#define VGT_DEBUG_REG31__pipe5_inner_dr_MASK 0x800
+#define VGT_DEBUG_REG31__pipe5_inner_dr__SHIFT 0xb
+#define VGT_DEBUG_REG31__pipe2_outer_rtr_MASK 0x1000
+#define VGT_DEBUG_REG31__pipe2_outer_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG31__pipe2_inner_rtr_MASK 0x2000
+#define VGT_DEBUG_REG31__pipe2_inner_rtr__SHIFT 0xd
+#define VGT_DEBUG_REG31__pipe3_outer_rtr_MASK 0x4000
+#define VGT_DEBUG_REG31__pipe3_outer_rtr__SHIFT 0xe
+#define VGT_DEBUG_REG31__pipe3_inner_rtr_MASK 0x8000
+#define VGT_DEBUG_REG31__pipe3_inner_rtr__SHIFT 0xf
+#define VGT_DEBUG_REG31__pipe4_outer_rtr_MASK 0x10000
+#define VGT_DEBUG_REG31__pipe4_outer_rtr__SHIFT 0x10
+#define VGT_DEBUG_REG31__pipe4_inner_rtr_MASK 0x20000
+#define VGT_DEBUG_REG31__pipe4_inner_rtr__SHIFT 0x11
+#define VGT_DEBUG_REG31__pipe5_outer_rtr_MASK 0x40000
+#define VGT_DEBUG_REG31__pipe5_outer_rtr__SHIFT 0x12
+#define VGT_DEBUG_REG31__pipe5_inner_rtr_MASK 0x80000
+#define VGT_DEBUG_REG31__pipe5_inner_rtr__SHIFT 0x13
+#define VGT_DEBUG_REG31__pg_con_outer_point1_rts_MASK 0x100000
+#define VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT 0x14
+#define VGT_DEBUG_REG31__pg_con_outer_point2_rts_MASK 0x200000
+#define VGT_DEBUG_REG31__pg_con_outer_point2_rts__SHIFT 0x15
+#define VGT_DEBUG_REG31__pg_con_inner_point1_rts_MASK 0x400000
+#define VGT_DEBUG_REG31__pg_con_inner_point1_rts__SHIFT 0x16
+#define VGT_DEBUG_REG31__pg_con_inner_point2_rts_MASK 0x800000
+#define VGT_DEBUG_REG31__pg_con_inner_point2_rts__SHIFT 0x17
+#define VGT_DEBUG_REG31__pg_patch_fifo_empty_MASK 0x1000000
+#define VGT_DEBUG_REG31__pg_patch_fifo_empty__SHIFT 0x18
+#define VGT_DEBUG_REG31__pg_edge_fifo_empty_MASK 0x2000000
+#define VGT_DEBUG_REG31__pg_edge_fifo_empty__SHIFT 0x19
+#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty_MASK 0x4000000
+#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty__SHIFT 0x1a
+#define VGT_DEBUG_REG31__pg_patch_fifo_full_MASK 0x8000000
+#define VGT_DEBUG_REG31__pg_patch_fifo_full__SHIFT 0x1b
+#define VGT_DEBUG_REG31__pg_edge_fifo_full_MASK 0x10000000
+#define VGT_DEBUG_REG31__pg_edge_fifo_full__SHIFT 0x1c
+#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full_MASK 0x20000000
+#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT 0x1d
+#define VGT_DEBUG_REG31__outer_ring_done_q_MASK 0x40000000
+#define VGT_DEBUG_REG31__outer_ring_done_q__SHIFT 0x1e
+#define VGT_DEBUG_REG31__inner_ring_done_q_MASK 0x80000000
+#define VGT_DEBUG_REG31__inner_ring_done_q__SHIFT 0x1f
+#define VGT_DEBUG_REG32__first_ring_of_patch_MASK 0x1
+#define VGT_DEBUG_REG32__first_ring_of_patch__SHIFT 0x0
+#define VGT_DEBUG_REG32__last_ring_of_patch_MASK 0x2
+#define VGT_DEBUG_REG32__last_ring_of_patch__SHIFT 0x1
+#define VGT_DEBUG_REG32__last_edge_of_outer_ring_MASK 0x4
+#define VGT_DEBUG_REG32__last_edge_of_outer_ring__SHIFT 0x2
+#define VGT_DEBUG_REG32__last_point_of_outer_edge_MASK 0x8
+#define VGT_DEBUG_REG32__last_point_of_outer_edge__SHIFT 0x3
+#define VGT_DEBUG_REG32__last_edge_of_inner_ring_MASK 0x10
+#define VGT_DEBUG_REG32__last_edge_of_inner_ring__SHIFT 0x4
+#define VGT_DEBUG_REG32__last_point_of_inner_edge_MASK 0x20
+#define VGT_DEBUG_REG32__last_point_of_inner_edge__SHIFT 0x5
+#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q_MASK 0x40
+#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q__SHIFT 0x6
+#define VGT_DEBUG_REG32__event_null_special_p0_q_MASK 0x80
+#define VGT_DEBUG_REG32__event_null_special_p0_q__SHIFT 0x7
+#define VGT_DEBUG_REG32__event_flag_p5_q_MASK 0x100
+#define VGT_DEBUG_REG32__event_flag_p5_q__SHIFT 0x8
+#define VGT_DEBUG_REG32__first_point_of_patch_p5_q_MASK 0x200
+#define VGT_DEBUG_REG32__first_point_of_patch_p5_q__SHIFT 0x9
+#define VGT_DEBUG_REG32__first_point_of_edge_p5_q_MASK 0x400
+#define VGT_DEBUG_REG32__first_point_of_edge_p5_q__SHIFT 0xa
+#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q_MASK 0x800
+#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q__SHIFT 0xb
+#define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x3000
+#define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0xc
+#define VGT_DEBUG_REG32__pipe5_inner3_rtr_MASK 0x4000
+#define VGT_DEBUG_REG32__pipe5_inner3_rtr__SHIFT 0xe
+#define VGT_DEBUG_REG32__pipe5_inner2_rtr_MASK 0x8000
+#define VGT_DEBUG_REG32__pipe5_inner2_rtr__SHIFT 0xf
+#define VGT_DEBUG_REG32__pg_edge_fifo3_full_MASK 0x10000
+#define VGT_DEBUG_REG32__pg_edge_fifo3_full__SHIFT 0x10
+#define VGT_DEBUG_REG32__pg_edge_fifo2_full_MASK 0x20000
+#define VGT_DEBUG_REG32__pg_edge_fifo2_full__SHIFT 0x11
+#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full_MASK 0x40000
+#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full__SHIFT 0x12
+#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full_MASK 0x80000
+#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full__SHIFT 0x13
+#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full_MASK 0x100000
+#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT 0x14
+#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full_MASK 0x200000
+#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full__SHIFT 0x15
+#define VGT_DEBUG_REG32__pg_inner_point_fifo_full_MASK 0x400000
+#define VGT_DEBUG_REG32__pg_inner_point_fifo_full__SHIFT 0x16
+#define VGT_DEBUG_REG32__pg_outer_point_fifo_full_MASK 0x800000
+#define VGT_DEBUG_REG32__pg_outer_point_fifo_full__SHIFT 0x17
+#define VGT_DEBUG_REG32__inner2_fifos_rtr_MASK 0x1000000
+#define VGT_DEBUG_REG32__inner2_fifos_rtr__SHIFT 0x18
+#define VGT_DEBUG_REG32__inner_fifos_rtr_MASK 0x2000000
+#define VGT_DEBUG_REG32__inner_fifos_rtr__SHIFT 0x19
+#define VGT_DEBUG_REG32__outer_fifos_rtr_MASK 0x4000000
+#define VGT_DEBUG_REG32__outer_fifos_rtr__SHIFT 0x1a
+#define VGT_DEBUG_REG32__fifos_rtr_MASK 0x8000000
+#define VGT_DEBUG_REG32__fifos_rtr__SHIFT 0x1b
+#define VGT_DEBUG_REG32__SPARE_MASK 0xf0000000
+#define VGT_DEBUG_REG32__SPARE__SHIFT 0x1c
+#define VGT_DEBUG_REG33__pipe0_patch_dr_MASK 0x1
+#define VGT_DEBUG_REG33__pipe0_patch_dr__SHIFT 0x0
+#define VGT_DEBUG_REG33__ring3_pipe1_dr_MASK 0x2
+#define VGT_DEBUG_REG33__ring3_pipe1_dr__SHIFT 0x1
+#define VGT_DEBUG_REG33__pipe1_dr_MASK 0x4
+#define VGT_DEBUG_REG33__pipe1_dr__SHIFT 0x2
+#define VGT_DEBUG_REG33__pipe2_dr_MASK 0x8
+#define VGT_DEBUG_REG33__pipe2_dr__SHIFT 0x3
+#define VGT_DEBUG_REG33__pipe0_patch_rtr_MASK 0x10
+#define VGT_DEBUG_REG33__pipe0_patch_rtr__SHIFT 0x4
+#define VGT_DEBUG_REG33__ring2_pipe1_dr_MASK 0x20
+#define VGT_DEBUG_REG33__ring2_pipe1_dr__SHIFT 0x5
+#define VGT_DEBUG_REG33__ring1_pipe1_dr_MASK 0x40
+#define VGT_DEBUG_REG33__ring1_pipe1_dr__SHIFT 0x6
+#define VGT_DEBUG_REG33__pipe2_rtr_MASK 0x80
+#define VGT_DEBUG_REG33__pipe2_rtr__SHIFT 0x7
+#define VGT_DEBUG_REG33__pipe3_dr_MASK 0x100
+#define VGT_DEBUG_REG33__pipe3_dr__SHIFT 0x8
+#define VGT_DEBUG_REG33__pipe3_rtr_MASK 0x200
+#define VGT_DEBUG_REG33__pipe3_rtr__SHIFT 0x9
+#define VGT_DEBUG_REG33__ring2_in_sync_q_MASK 0x400
+#define VGT_DEBUG_REG33__ring2_in_sync_q__SHIFT 0xa
+#define VGT_DEBUG_REG33__ring1_in_sync_q_MASK 0x800
+#define VGT_DEBUG_REG33__ring1_in_sync_q__SHIFT 0xb
+#define VGT_DEBUG_REG33__pipe1_patch_rtr_MASK 0x1000
+#define VGT_DEBUG_REG33__pipe1_patch_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG33__ring3_in_sync_q_MASK 0x2000
+#define VGT_DEBUG_REG33__ring3_in_sync_q__SHIFT 0xd
+#define VGT_DEBUG_REG33__tm_te11_event_rtr_MASK 0x4000
+#define VGT_DEBUG_REG33__tm_te11_event_rtr__SHIFT 0xe
+#define VGT_DEBUG_REG33__first_prim_of_patch_q_MASK 0x8000
+#define VGT_DEBUG_REG33__first_prim_of_patch_q__SHIFT 0xf
+#define VGT_DEBUG_REG33__con_prim_fifo_full_MASK 0x10000
+#define VGT_DEBUG_REG33__con_prim_fifo_full__SHIFT 0x10
+#define VGT_DEBUG_REG33__con_vert_fifo_full_MASK 0x20000
+#define VGT_DEBUG_REG33__con_vert_fifo_full__SHIFT 0x11
+#define VGT_DEBUG_REG33__con_prim_fifo_empty_MASK 0x40000
+#define VGT_DEBUG_REG33__con_prim_fifo_empty__SHIFT 0x12
+#define VGT_DEBUG_REG33__con_vert_fifo_empty_MASK 0x80000
+#define VGT_DEBUG_REG33__con_vert_fifo_empty__SHIFT 0x13
+#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q_MASK 0x100000
+#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT 0x14
+#define VGT_DEBUG_REG33__ring3_valid_p2_MASK 0x200000
+#define VGT_DEBUG_REG33__ring3_valid_p2__SHIFT 0x15
+#define VGT_DEBUG_REG33__ring2_valid_p2_MASK 0x400000
+#define VGT_DEBUG_REG33__ring2_valid_p2__SHIFT 0x16
+#define VGT_DEBUG_REG33__ring1_valid_p2_MASK 0x800000
+#define VGT_DEBUG_REG33__ring1_valid_p2__SHIFT 0x17
+#define VGT_DEBUG_REG33__tess_type_p0_q_MASK 0x3000000
+#define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x18
+#define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0xc000000
+#define VGT_DEBUG_REG33__tess_topology_p0_q__SHIFT 0x1a
+#define VGT_DEBUG_REG33__te11_out_vert_gs_en_MASK 0x10000000
+#define VGT_DEBUG_REG33__te11_out_vert_gs_en__SHIFT 0x1c
+#define VGT_DEBUG_REG33__con_ring3_busy_MASK 0x20000000
+#define VGT_DEBUG_REG33__con_ring3_busy__SHIFT 0x1d
+#define VGT_DEBUG_REG33__con_ring2_busy_MASK 0x40000000
+#define VGT_DEBUG_REG33__con_ring2_busy__SHIFT 0x1e
+#define VGT_DEBUG_REG33__con_ring1_busy_MASK 0x80000000
+#define VGT_DEBUG_REG33__con_ring1_busy__SHIFT 0x1f
+#define VGT_DEBUG_REG34__con_state_q_MASK 0xf
+#define VGT_DEBUG_REG34__con_state_q__SHIFT 0x0
+#define VGT_DEBUG_REG34__second_cycle_q_MASK 0x10
+#define VGT_DEBUG_REG34__second_cycle_q__SHIFT 0x4
+#define VGT_DEBUG_REG34__process_tri_middle_p0_q_MASK 0x20
+#define VGT_DEBUG_REG34__process_tri_middle_p0_q__SHIFT 0x5
+#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q_MASK 0x40
+#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
+#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q_MASK 0x80
+#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q__SHIFT 0x7
+#define VGT_DEBUG_REG34__pipe0_patch_dr_MASK 0x100
+#define VGT_DEBUG_REG34__pipe0_patch_dr__SHIFT 0x8
+#define VGT_DEBUG_REG34__pipe0_edge_dr_MASK 0x200
+#define VGT_DEBUG_REG34__pipe0_edge_dr__SHIFT 0x9
+#define VGT_DEBUG_REG34__pipe1_dr_MASK 0x400
+#define VGT_DEBUG_REG34__pipe1_dr__SHIFT 0xa
+#define VGT_DEBUG_REG34__pipe0_patch_rtr_MASK 0x800
+#define VGT_DEBUG_REG34__pipe0_patch_rtr__SHIFT 0xb
+#define VGT_DEBUG_REG34__pipe0_edge_rtr_MASK 0x1000
+#define VGT_DEBUG_REG34__pipe0_edge_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG34__pipe1_rtr_MASK 0x2000
+#define VGT_DEBUG_REG34__pipe1_rtr__SHIFT 0xd
+#define VGT_DEBUG_REG34__outer_parity_p0_q_MASK 0x4000
+#define VGT_DEBUG_REG34__outer_parity_p0_q__SHIFT 0xe
+#define VGT_DEBUG_REG34__parallel_parity_p0_q_MASK 0x8000
+#define VGT_DEBUG_REG34__parallel_parity_p0_q__SHIFT 0xf
+#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q_MASK 0x10000
+#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q__SHIFT 0x10
+#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q_MASK 0x20000
+#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q__SHIFT 0x11
+#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q_MASK 0x40000
+#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q__SHIFT 0x12
+#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1_MASK 0x80000
+#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1__SHIFT 0x13
+#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1_MASK 0x100000
+#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT 0x14
+#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q_MASK 0x200000
+#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
+#define VGT_DEBUG_REG34__advance_outer_point_p1_MASK 0x400000
+#define VGT_DEBUG_REG34__advance_outer_point_p1__SHIFT 0x16
+#define VGT_DEBUG_REG34__advance_inner_point_p1_MASK 0x800000
+#define VGT_DEBUG_REG34__advance_inner_point_p1__SHIFT 0x17
+#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q_MASK 0x1000000
+#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q__SHIFT 0x18
+#define VGT_DEBUG_REG34__pipe1_outer1_rtr_MASK 0x2000000
+#define VGT_DEBUG_REG34__pipe1_outer1_rtr__SHIFT 0x19
+#define VGT_DEBUG_REG34__pipe1_outer2_rtr_MASK 0x4000000
+#define VGT_DEBUG_REG34__pipe1_outer2_rtr__SHIFT 0x1a
+#define VGT_DEBUG_REG34__pipe1_inner1_rtr_MASK 0x8000000
+#define VGT_DEBUG_REG34__pipe1_inner1_rtr__SHIFT 0x1b
+#define VGT_DEBUG_REG34__pipe1_inner2_rtr_MASK 0x10000000
+#define VGT_DEBUG_REG34__pipe1_inner2_rtr__SHIFT 0x1c
+#define VGT_DEBUG_REG34__pipe1_patch_rtr_MASK 0x20000000
+#define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT 0x1d
+#define VGT_DEBUG_REG34__pipe1_edge_rtr_MASK 0x40000000
+#define VGT_DEBUG_REG34__pipe1_edge_rtr__SHIFT 0x1e
+#define VGT_DEBUG_REG34__use_stored_inner_q_ring1_MASK 0x80000000
+#define VGT_DEBUG_REG34__use_stored_inner_q_ring1__SHIFT 0x1f
+#define VGT_DEBUG_REG35__pipe0_dr_MASK 0x1
+#define VGT_DEBUG_REG35__pipe0_dr__SHIFT 0x0
+#define VGT_DEBUG_REG35__pipe1_dr_MASK 0x2
+#define VGT_DEBUG_REG35__pipe1_dr__SHIFT 0x1
+#define VGT_DEBUG_REG35__pipe0_rtr_MASK 0x4
+#define VGT_DEBUG_REG35__pipe0_rtr__SHIFT 0x2
+#define VGT_DEBUG_REG35__pipe1_rtr_MASK 0x8
+#define VGT_DEBUG_REG35__pipe1_rtr__SHIFT 0x3
+#define VGT_DEBUG_REG35__tfreq_tg_fifo_empty_MASK 0x10
+#define VGT_DEBUG_REG35__tfreq_tg_fifo_empty__SHIFT 0x4
+#define VGT_DEBUG_REG35__tfreq_tg_fifo_full_MASK 0x20
+#define VGT_DEBUG_REG35__tfreq_tg_fifo_full__SHIFT 0x5
+#define VGT_DEBUG_REG35__tf_data_fifo_busy_q_MASK 0x40
+#define VGT_DEBUG_REG35__tf_data_fifo_busy_q__SHIFT 0x6
+#define VGT_DEBUG_REG35__tf_data_fifo_rtr_q_MASK 0x80
+#define VGT_DEBUG_REG35__tf_data_fifo_rtr_q__SHIFT 0x7
+#define VGT_DEBUG_REG35__tf_skid_fifo_empty_MASK 0x100
+#define VGT_DEBUG_REG35__tf_skid_fifo_empty__SHIFT 0x8
+#define VGT_DEBUG_REG35__tf_skid_fifo_full_MASK 0x200
+#define VGT_DEBUG_REG35__tf_skid_fifo_full__SHIFT 0x9
+#define VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q_MASK 0x400
+#define VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q__SHIFT 0xa
+#define VGT_DEBUG_REG35__last_req_of_tg_p2_MASK 0x800
+#define VGT_DEBUG_REG35__last_req_of_tg_p2__SHIFT 0xb
+#define VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q_MASK 0x3f000
+#define VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q__SHIFT 0xc
+#define VGT_DEBUG_REG35__event_flag_p1_q_MASK 0x40000
+#define VGT_DEBUG_REG35__event_flag_p1_q__SHIFT 0x12
+#define VGT_DEBUG_REG35__null_flag_p1_q_MASK 0x80000
+#define VGT_DEBUG_REG35__null_flag_p1_q__SHIFT 0x13
+#define VGT_DEBUG_REG35__tf_data_fifo_cnt_q_MASK 0x7f00000
+#define VGT_DEBUG_REG35__tf_data_fifo_cnt_q__SHIFT 0x14
+#define VGT_DEBUG_REG35__second_tf_ret_data_q_MASK 0x8000000
+#define VGT_DEBUG_REG35__second_tf_ret_data_q__SHIFT 0x1b
+#define VGT_DEBUG_REG35__first_req_of_tg_p1_q_MASK 0x10000000
+#define VGT_DEBUG_REG35__first_req_of_tg_p1_q__SHIFT 0x1c
+#define VGT_DEBUG_REG35__VGT_TC_rdreq_send_out_MASK 0x20000000
+#define VGT_DEBUG_REG35__VGT_TC_rdreq_send_out__SHIFT 0x1d
+#define VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out_MASK 0x40000000
+#define VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out__SHIFT 0x1e
+#define VGT_DEBUG_REG35__TC_VGT_rdret_data_in_MASK 0x80000000
+#define VGT_DEBUG_REG35__TC_VGT_rdret_data_in__SHIFT 0x1f
+#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0xff
+#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
+#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
+#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
+#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
+#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
+#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
+#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
+#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
+#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
+#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
+#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
+#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
+#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
+#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xffffffff
+#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0
+#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xffffffff
+#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0
+#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x1
+#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK 0x2
+#define DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT 0x1
+#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc
+#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x2
+#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x10
+#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
+#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
+#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
+#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0xffff
+#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xffff0000
+#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
+#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
+#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
+#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0xff
+#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0xff00
+#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0xff0000
+#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xff000000
+#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0xff
+#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0xff00
+#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0xff0000
+#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xff000000
+#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0xff
+#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0xff00
+#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0xff0000
+#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xff000000
+#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x1
+#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_DB_CTRL0__USE_REF_CLOCK_MASK 0x2
+#define DIDT_DB_CTRL0__USE_REF_CLOCK__SHIFT 0x1
+#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0xc
+#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x2
+#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x10
+#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
+#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
+#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
+#define DIDT_DB_CTRL1__MIN_POWER_MASK 0xffff
+#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xffff0000
+#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
+#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
+#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
+#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0xff
+#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0xff00
+#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0xff0000
+#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xff000000
+#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0xff
+#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0xff00
+#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0xff0000
+#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xff000000
+#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0xff
+#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0xff00
+#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0xff0000
+#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xff000000
+#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x1
+#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_TD_CTRL0__USE_REF_CLOCK_MASK 0x2
+#define DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT 0x1
+#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0xc
+#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x2
+#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x10
+#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
+#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
+#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
+#define DIDT_TD_CTRL1__MIN_POWER_MASK 0xffff
+#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xffff0000
+#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
+#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
+#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
+#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0xff
+#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0xff00
+#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0xff0000
+#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xff000000
+#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0xff
+#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0xff00
+#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0xff0000
+#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xff000000
+#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0xff
+#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0xff00
+#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0xff0000
+#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xff000000
+#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x1
+#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK 0x2
+#define DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT 0x1
+#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0xc
+#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x2
+#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x10
+#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
+#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
+#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
+#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0xffff
+#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xffff0000
+#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
+#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
+#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
+#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0xff
+#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0xff00
+#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0xff0000
+#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xff000000
+#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0xff
+#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0xff00
+#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0xff0000
+#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xff000000
+#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0xff
+#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0xff00
+#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0xff0000
+#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xff000000
+#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+
+#endif /* GFX_7_2_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h
new file mode 100644
index 000000000000..daf763ba1a8f
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h
@@ -0,0 +1,2811 @@
+/*
+ * GFX_8_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GFX_8_0_D_H
+#define GFX_8_0_D_H
+
+#define mmCB_BLEND_RED 0xa105
+#define mmCB_BLEND_GREEN 0xa106
+#define mmCB_BLEND_BLUE 0xa107
+#define mmCB_BLEND_ALPHA 0xa108
+#define mmCB_DCC_CONTROL 0xa109
+#define mmCB_COLOR_CONTROL 0xa202
+#define mmCB_BLEND0_CONTROL 0xa1e0
+#define mmCB_BLEND1_CONTROL 0xa1e1
+#define mmCB_BLEND2_CONTROL 0xa1e2
+#define mmCB_BLEND3_CONTROL 0xa1e3
+#define mmCB_BLEND4_CONTROL 0xa1e4
+#define mmCB_BLEND5_CONTROL 0xa1e5
+#define mmCB_BLEND6_CONTROL 0xa1e6
+#define mmCB_BLEND7_CONTROL 0xa1e7
+#define mmCB_COLOR0_BASE 0xa318
+#define mmCB_COLOR1_BASE 0xa327
+#define mmCB_COLOR2_BASE 0xa336
+#define mmCB_COLOR3_BASE 0xa345
+#define mmCB_COLOR4_BASE 0xa354
+#define mmCB_COLOR5_BASE 0xa363
+#define mmCB_COLOR6_BASE 0xa372
+#define mmCB_COLOR7_BASE 0xa381
+#define mmCB_COLOR0_PITCH 0xa319
+#define mmCB_COLOR1_PITCH 0xa328
+#define mmCB_COLOR2_PITCH 0xa337
+#define mmCB_COLOR3_PITCH 0xa346
+#define mmCB_COLOR4_PITCH 0xa355
+#define mmCB_COLOR5_PITCH 0xa364
+#define mmCB_COLOR6_PITCH 0xa373
+#define mmCB_COLOR7_PITCH 0xa382
+#define mmCB_COLOR0_SLICE 0xa31a
+#define mmCB_COLOR1_SLICE 0xa329
+#define mmCB_COLOR2_SLICE 0xa338
+#define mmCB_COLOR3_SLICE 0xa347
+#define mmCB_COLOR4_SLICE 0xa356
+#define mmCB_COLOR5_SLICE 0xa365
+#define mmCB_COLOR6_SLICE 0xa374
+#define mmCB_COLOR7_SLICE 0xa383
+#define mmCB_COLOR0_VIEW 0xa31b
+#define mmCB_COLOR1_VIEW 0xa32a
+#define mmCB_COLOR2_VIEW 0xa339
+#define mmCB_COLOR3_VIEW 0xa348
+#define mmCB_COLOR4_VIEW 0xa357
+#define mmCB_COLOR5_VIEW 0xa366
+#define mmCB_COLOR6_VIEW 0xa375
+#define mmCB_COLOR7_VIEW 0xa384
+#define mmCB_COLOR0_INFO 0xa31c
+#define mmCB_COLOR1_INFO 0xa32b
+#define mmCB_COLOR2_INFO 0xa33a
+#define mmCB_COLOR3_INFO 0xa349
+#define mmCB_COLOR4_INFO 0xa358
+#define mmCB_COLOR5_INFO 0xa367
+#define mmCB_COLOR6_INFO 0xa376
+#define mmCB_COLOR7_INFO 0xa385
+#define mmCB_COLOR0_ATTRIB 0xa31d
+#define mmCB_COLOR1_ATTRIB 0xa32c
+#define mmCB_COLOR2_ATTRIB 0xa33b
+#define mmCB_COLOR3_ATTRIB 0xa34a
+#define mmCB_COLOR4_ATTRIB 0xa359
+#define mmCB_COLOR5_ATTRIB 0xa368
+#define mmCB_COLOR6_ATTRIB 0xa377
+#define mmCB_COLOR7_ATTRIB 0xa386
+#define mmCB_COLOR0_DCC_CONTROL 0xa31e
+#define mmCB_COLOR1_DCC_CONTROL 0xa32d
+#define mmCB_COLOR2_DCC_CONTROL 0xa33c
+#define mmCB_COLOR3_DCC_CONTROL 0xa34b
+#define mmCB_COLOR4_DCC_CONTROL 0xa35a
+#define mmCB_COLOR5_DCC_CONTROL 0xa369
+#define mmCB_COLOR6_DCC_CONTROL 0xa378
+#define mmCB_COLOR7_DCC_CONTROL 0xa387
+#define mmCB_COLOR0_CMASK 0xa31f
+#define mmCB_COLOR1_CMASK 0xa32e
+#define mmCB_COLOR2_CMASK 0xa33d
+#define mmCB_COLOR3_CMASK 0xa34c
+#define mmCB_COLOR4_CMASK 0xa35b
+#define mmCB_COLOR5_CMASK 0xa36a
+#define mmCB_COLOR6_CMASK 0xa379
+#define mmCB_COLOR7_CMASK 0xa388
+#define mmCB_COLOR0_CMASK_SLICE 0xa320
+#define mmCB_COLOR1_CMASK_SLICE 0xa32f
+#define mmCB_COLOR2_CMASK_SLICE 0xa33e
+#define mmCB_COLOR3_CMASK_SLICE 0xa34d
+#define mmCB_COLOR4_CMASK_SLICE 0xa35c
+#define mmCB_COLOR5_CMASK_SLICE 0xa36b
+#define mmCB_COLOR6_CMASK_SLICE 0xa37a
+#define mmCB_COLOR7_CMASK_SLICE 0xa389
+#define mmCB_COLOR0_FMASK 0xa321
+#define mmCB_COLOR1_FMASK 0xa330
+#define mmCB_COLOR2_FMASK 0xa33f
+#define mmCB_COLOR3_FMASK 0xa34e
+#define mmCB_COLOR4_FMASK 0xa35d
+#define mmCB_COLOR5_FMASK 0xa36c
+#define mmCB_COLOR6_FMASK 0xa37b
+#define mmCB_COLOR7_FMASK 0xa38a
+#define mmCB_COLOR0_FMASK_SLICE 0xa322
+#define mmCB_COLOR1_FMASK_SLICE 0xa331
+#define mmCB_COLOR2_FMASK_SLICE 0xa340
+#define mmCB_COLOR3_FMASK_SLICE 0xa34f
+#define mmCB_COLOR4_FMASK_SLICE 0xa35e
+#define mmCB_COLOR5_FMASK_SLICE 0xa36d
+#define mmCB_COLOR6_FMASK_SLICE 0xa37c
+#define mmCB_COLOR7_FMASK_SLICE 0xa38b
+#define mmCB_COLOR0_CLEAR_WORD0 0xa323
+#define mmCB_COLOR1_CLEAR_WORD0 0xa332
+#define mmCB_COLOR2_CLEAR_WORD0 0xa341
+#define mmCB_COLOR3_CLEAR_WORD0 0xa350
+#define mmCB_COLOR4_CLEAR_WORD0 0xa35f
+#define mmCB_COLOR5_CLEAR_WORD0 0xa36e
+#define mmCB_COLOR6_CLEAR_WORD0 0xa37d
+#define mmCB_COLOR7_CLEAR_WORD0 0xa38c
+#define mmCB_COLOR0_CLEAR_WORD1 0xa324
+#define mmCB_COLOR1_CLEAR_WORD1 0xa333
+#define mmCB_COLOR2_CLEAR_WORD1 0xa342
+#define mmCB_COLOR3_CLEAR_WORD1 0xa351
+#define mmCB_COLOR4_CLEAR_WORD1 0xa360
+#define mmCB_COLOR5_CLEAR_WORD1 0xa36f
+#define mmCB_COLOR6_CLEAR_WORD1 0xa37e
+#define mmCB_COLOR7_CLEAR_WORD1 0xa38d
+#define mmCB_COLOR0_DCC_BASE 0xa325
+#define mmCB_COLOR1_DCC_BASE 0xa334
+#define mmCB_COLOR2_DCC_BASE 0xa343
+#define mmCB_COLOR3_DCC_BASE 0xa352
+#define mmCB_COLOR4_DCC_BASE 0xa361
+#define mmCB_COLOR5_DCC_BASE 0xa370
+#define mmCB_COLOR6_DCC_BASE 0xa37f
+#define mmCB_COLOR7_DCC_BASE 0xa38e
+#define mmCB_TARGET_MASK 0xa08e
+#define mmCB_SHADER_MASK 0xa08f
+#define mmCB_HW_CONTROL 0x2684
+#define mmCB_HW_CONTROL_1 0x2685
+#define mmCB_HW_CONTROL_2 0x2686
+#define mmCB_HW_CONTROL_3 0x2683
+#define mmCB_DCC_CONFIG 0x2687
+#define mmCB_PERFCOUNTER_FILTER 0xdc00
+#define mmCB_PERFCOUNTER0_SELECT 0xdc01
+#define mmCB_PERFCOUNTER0_SELECT1 0xdc02
+#define mmCB_PERFCOUNTER1_SELECT 0xdc03
+#define mmCB_PERFCOUNTER2_SELECT 0xdc04
+#define mmCB_PERFCOUNTER3_SELECT 0xdc05
+#define mmCB_PERFCOUNTER0_LO 0xd406
+#define mmCB_PERFCOUNTER1_LO 0xd408
+#define mmCB_PERFCOUNTER2_LO 0xd40a
+#define mmCB_PERFCOUNTER3_LO 0xd40c
+#define mmCB_PERFCOUNTER0_HI 0xd407
+#define mmCB_PERFCOUNTER1_HI 0xd409
+#define mmCB_PERFCOUNTER2_HI 0xd40b
+#define mmCB_PERFCOUNTER3_HI 0xd40d
+#define mmCB_CGTT_SCLK_CTRL 0xf0a8
+#define mmCB_DEBUG_BUS_1 0x2699
+#define mmCB_DEBUG_BUS_2 0x269a
+#define mmCB_DEBUG_BUS_3 0x269b
+#define mmCB_DEBUG_BUS_4 0x269c
+#define mmCB_DEBUG_BUS_5 0x269d
+#define mmCB_DEBUG_BUS_6 0x269e
+#define mmCB_DEBUG_BUS_7 0x269f
+#define mmCB_DEBUG_BUS_8 0x26a0
+#define mmCB_DEBUG_BUS_9 0x26a1
+#define mmCB_DEBUG_BUS_10 0x26a2
+#define mmCB_DEBUG_BUS_11 0x26a3
+#define mmCB_DEBUG_BUS_12 0x26a4
+#define mmCB_DEBUG_BUS_13 0x26a5
+#define mmCB_DEBUG_BUS_14 0x26a6
+#define mmCB_DEBUG_BUS_15 0x26a7
+#define mmCB_DEBUG_BUS_16 0x26a8
+#define mmCB_DEBUG_BUS_17 0x26a9
+#define mmCB_DEBUG_BUS_18 0x26aa
+#define mmCB_DEBUG_BUS_19 0x26ab
+#define mmCB_DEBUG_BUS_20 0x26ac
+#define mmCB_DEBUG_BUS_21 0x26ad
+#define mmCB_DEBUG_BUS_22 0x26ae
+#define mmCP_DFY_CNTL 0x3020
+#define mmCP_DFY_STAT 0x3021
+#define mmCP_DFY_ADDR_HI 0x3022
+#define mmCP_DFY_ADDR_LO 0x3023
+#define mmCP_DFY_DATA_0 0x3024
+#define mmCP_DFY_DATA_1 0x3025
+#define mmCP_DFY_DATA_2 0x3026
+#define mmCP_DFY_DATA_3 0x3027
+#define mmCP_DFY_DATA_4 0x3028
+#define mmCP_DFY_DATA_5 0x3029
+#define mmCP_DFY_DATA_6 0x302a
+#define mmCP_DFY_DATA_7 0x302b
+#define mmCP_DFY_DATA_8 0x302c
+#define mmCP_DFY_DATA_9 0x302d
+#define mmCP_DFY_DATA_10 0x302e
+#define mmCP_DFY_DATA_11 0x302f
+#define mmCP_DFY_DATA_12 0x3030
+#define mmCP_DFY_DATA_13 0x3031
+#define mmCP_DFY_DATA_14 0x3032
+#define mmCP_DFY_DATA_15 0x3033
+#define mmCP_DFY_CMD 0x3034
+#define mmCP_CPC_MGCG_SYNC_CNTL 0x3036
+#define mmCP_RB0_BASE 0x3040
+#define mmCP_RB0_BASE_HI 0x30b1
+#define mmCP_RB_BASE 0x3040
+#define mmCP_RB1_BASE 0x3060
+#define mmCP_RB1_BASE_HI 0x30b2
+#define mmCP_RB2_BASE 0x3065
+#define mmCP_RB0_CNTL 0x3041
+#define mmCP_RB_CNTL 0x3041
+#define mmCP_RB1_CNTL 0x3061
+#define mmCP_RB2_CNTL 0x3066
+#define mmCP_RB_RPTR_WR 0x3042
+#define mmCP_RB0_RPTR_ADDR 0x3043
+#define mmCP_RB_RPTR_ADDR 0x3043
+#define mmCP_RB1_RPTR_ADDR 0x3062
+#define mmCP_RB2_RPTR_ADDR 0x3067
+#define mmCP_RB0_RPTR_ADDR_HI 0x3044
+#define mmCP_RB_RPTR_ADDR_HI 0x3044
+#define mmCP_RB1_RPTR_ADDR_HI 0x3063
+#define mmCP_RB2_RPTR_ADDR_HI 0x3068
+#define mmCP_RB0_WPTR 0x3045
+#define mmCP_RB_WPTR 0x3045
+#define mmCP_RB1_WPTR 0x3064
+#define mmCP_RB2_WPTR 0x3069
+#define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046
+#define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047
+#define mmGC_PRIV_MODE 0x3048
+#define mmCP_INT_CNTL 0x3049
+#define mmCP_INT_CNTL_RING0 0x306a
+#define mmCP_INT_CNTL_RING1 0x306b
+#define mmCP_INT_CNTL_RING2 0x306c
+#define mmCP_INT_STATUS 0x304a
+#define mmCP_INT_STATUS_RING0 0x306d
+#define mmCP_INT_STATUS_RING1 0x306e
+#define mmCP_INT_STATUS_RING2 0x306f
+#define mmCP_DEVICE_ID 0x304b
+#define mmCP_RING_PRIORITY_CNTS 0x304c
+#define mmCP_ME0_PIPE_PRIORITY_CNTS 0x304c
+#define mmCP_RING0_PRIORITY 0x304d
+#define mmCP_ME0_PIPE0_PRIORITY 0x304d
+#define mmCP_RING1_PRIORITY 0x304e
+#define mmCP_ME0_PIPE1_PRIORITY 0x304e
+#define mmCP_RING2_PRIORITY 0x304f
+#define mmCP_ME0_PIPE2_PRIORITY 0x304f
+#define mmCP_ENDIAN_SWAP 0x3050
+#define mmCP_RB_VMID 0x3051
+#define mmCP_ME0_PIPE0_VMID 0x3052
+#define mmCP_ME0_PIPE1_VMID 0x3053
+#define mmCP_RB_DOORBELL_CONTROL 0x3059
+#define mmCP_RB_DOORBELL_RANGE_LOWER 0x305a
+#define mmCP_RB_DOORBELL_RANGE_UPPER 0x305b
+#define mmCP_MEC_DOORBELL_RANGE_LOWER 0x305c
+#define mmCP_MEC_DOORBELL_RANGE_UPPER 0x305d
+#define mmCP_PFP_UCODE_ADDR 0xf814
+#define mmCP_PFP_UCODE_DATA 0xf815
+#define mmCP_ME_RAM_RADDR 0xf816
+#define mmCP_ME_RAM_WADDR 0xf816
+#define mmCP_ME_RAM_DATA 0xf817
+#define mmCGTT_CPC_CLK_CTRL 0xf0b2
+#define mmCGTT_CPF_CLK_CTRL 0xf0b1
+#define mmCGTT_CP_CLK_CTRL 0xf0b0
+#define mmCP_CE_UCODE_ADDR 0xf818
+#define mmCP_CE_UCODE_DATA 0xf819
+#define mmCP_MEC_ME1_UCODE_ADDR 0xf81a
+#define mmCP_MEC_ME1_UCODE_DATA 0xf81b
+#define mmCP_MEC_ME2_UCODE_ADDR 0xf81c
+#define mmCP_MEC_ME2_UCODE_DATA 0xf81d
+#define mmCP_MEC1_F32_INT_DIS 0x30bd
+#define mmCP_MEC2_F32_INT_DIS 0x30be
+#define mmCP_VIRT_STATUS 0x3038
+#define mmCP_PWR_CNTL 0x3078
+#define mmCP_MEM_SLP_CNTL 0x3079
+#define mmCP_ECC_FIRSTOCCURRENCE 0x307a
+#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x307b
+#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x307c
+#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x307d
+#define mmCP_CPF_DEBUG 0x3080
+#define mmCP_PQ_WPTR_POLL_CNTL 0x3083
+#define mmCP_PQ_WPTR_POLL_CNTL1 0x3084
+#define mmCPC_INT_CNTL 0x30b4
+#define mmCP_ME1_PIPE0_INT_CNTL 0x3085
+#define mmCP_ME1_PIPE1_INT_CNTL 0x3086
+#define mmCP_ME1_PIPE2_INT_CNTL 0x3087
+#define mmCP_ME1_PIPE3_INT_CNTL 0x3088
+#define mmCP_ME2_PIPE0_INT_CNTL 0x3089
+#define mmCP_ME2_PIPE1_INT_CNTL 0x308a
+#define mmCP_ME2_PIPE2_INT_CNTL 0x308b
+#define mmCP_ME2_PIPE3_INT_CNTL 0x308c
+#define mmCPC_INT_STATUS 0x30b5
+#define mmCP_ME1_PIPE0_INT_STATUS 0x308d
+#define mmCP_ME1_PIPE1_INT_STATUS 0x308e
+#define mmCP_ME1_PIPE2_INT_STATUS 0x308f
+#define mmCP_ME1_PIPE3_INT_STATUS 0x3090
+#define mmCP_ME2_PIPE0_INT_STATUS 0x3091
+#define mmCP_ME2_PIPE1_INT_STATUS 0x3092
+#define mmCP_ME2_PIPE2_INT_STATUS 0x3093
+#define mmCP_ME2_PIPE3_INT_STATUS 0x3094
+#define mmCP_ME1_INT_STAT_DEBUG 0x3095
+#define mmCP_ME2_INT_STAT_DEBUG 0x3096
+#define mmCP_ME1_PIPE_PRIORITY_CNTS 0x3099
+#define mmCP_ME1_PIPE0_PRIORITY 0x309a
+#define mmCP_ME1_PIPE1_PRIORITY 0x309b
+#define mmCP_ME1_PIPE2_PRIORITY 0x309c
+#define mmCP_ME1_PIPE3_PRIORITY 0x309d
+#define mmCP_ME2_PIPE_PRIORITY_CNTS 0x309e
+#define mmCP_ME2_PIPE0_PRIORITY 0x309f
+#define mmCP_ME2_PIPE1_PRIORITY 0x30a0
+#define mmCP_ME2_PIPE2_PRIORITY 0x30a1
+#define mmCP_ME2_PIPE3_PRIORITY 0x30a2
+#define mmCP_CE_PRGRM_CNTR_START 0x30a3
+#define mmCP_PFP_PRGRM_CNTR_START 0x30a4
+#define mmCP_ME_PRGRM_CNTR_START 0x30a5
+#define mmCP_MEC1_PRGRM_CNTR_START 0x30a6
+#define mmCP_MEC2_PRGRM_CNTR_START 0x30a7
+#define mmCP_CE_INTR_ROUTINE_START 0x30a8
+#define mmCP_PFP_INTR_ROUTINE_START 0x30a9
+#define mmCP_ME_INTR_ROUTINE_START 0x30aa
+#define mmCP_MEC1_INTR_ROUTINE_START 0x30ab
+#define mmCP_MEC2_INTR_ROUTINE_START 0x30ac
+#define mmCP_CONTEXT_CNTL 0x30ad
+#define mmCP_MAX_CONTEXT 0x30ae
+#define mmCP_IQ_WAIT_TIME1 0x30af
+#define mmCP_IQ_WAIT_TIME2 0x30b0
+#define mmCP_VMID_RESET 0x30b3
+#define mmCP_VMID_PREEMPT 0x30b6
+#define mmCP_VMID_STATUS 0x30bf
+#define mmCPC_INT_CNTX_ID 0x30b7
+#define mmCP_PQ_STATUS 0x30b8
+#define mmCP_CPC_IC_BASE_LO 0x30b9
+#define mmCP_CPC_IC_BASE_HI 0x30ba
+#define mmCP_CPC_IC_BASE_CNTL 0x30bb
+#define mmCP_CPC_IC_OP_CNTL 0x30bc
+#define mmCP_CPC_STATUS 0x2084
+#define mmCP_CPC_BUSY_STAT 0x2085
+#define mmCP_CPC_STALLED_STAT1 0x2086
+#define mmCP_CPF_STATUS 0x2087
+#define mmCP_CPF_BUSY_STAT 0x2088
+#define mmCP_CPF_STALLED_STAT1 0x2089
+#define mmCP_CPC_GRBM_FREE_COUNT 0x208b
+#define mmCP_MEC_CNTL 0x208d
+#define mmCP_MEC_ME1_HEADER_DUMP 0x208e
+#define mmCP_MEC_ME2_HEADER_DUMP 0x208f
+#define mmCP_CPC_SCRATCH_INDEX 0x2090
+#define mmCP_CPC_SCRATCH_DATA 0x2091
+#define mmCPG_PERFCOUNTER1_SELECT 0xd800
+#define mmCPG_PERFCOUNTER1_LO 0xd000
+#define mmCPG_PERFCOUNTER1_HI 0xd001
+#define mmCPG_PERFCOUNTER0_SELECT1 0xd801
+#define mmCPG_PERFCOUNTER0_SELECT 0xd802
+#define mmCPG_PERFCOUNTER0_LO 0xd002
+#define mmCPG_PERFCOUNTER0_HI 0xd003
+#define mmCPC_PERFCOUNTER1_SELECT 0xd803
+#define mmCPC_PERFCOUNTER1_LO 0xd004
+#define mmCPC_PERFCOUNTER1_HI 0xd005
+#define mmCPC_PERFCOUNTER0_SELECT1 0xd804
+#define mmCPC_PERFCOUNTER0_SELECT 0xd809
+#define mmCPC_PERFCOUNTER0_LO 0xd006
+#define mmCPC_PERFCOUNTER0_HI 0xd007
+#define mmCPF_PERFCOUNTER1_SELECT 0xd805
+#define mmCPF_PERFCOUNTER1_LO 0xd008
+#define mmCPF_PERFCOUNTER1_HI 0xd009
+#define mmCPF_PERFCOUNTER0_SELECT1 0xd806
+#define mmCPF_PERFCOUNTER0_SELECT 0xd807
+#define mmCPF_PERFCOUNTER0_LO 0xd00a
+#define mmCPF_PERFCOUNTER0_HI 0xd00b
+#define mmCP_CPC_HALT_HYST_COUNT 0x20a7
+#define mmCP_DRAW_OBJECT 0xd810
+#define mmCP_DRAW_OBJECT_COUNTER 0xd811
+#define mmCP_DRAW_WINDOW_MASK_HI 0xd812
+#define mmCP_DRAW_WINDOW_HI 0xd813
+#define mmCP_DRAW_WINDOW_LO 0xd814
+#define mmCP_DRAW_WINDOW_CNTL 0xd815
+#define mmCP_PRT_LOD_STATS_CNTL0 0x20ad
+#define mmCP_PRT_LOD_STATS_CNTL1 0x20ae
+#define mmCP_PRT_LOD_STATS_CNTL2 0x20af
+#define mmCP_CE_COMPARE_COUNT 0x20c0
+#define mmCP_CE_DE_COUNT 0x20c1
+#define mmCP_DE_CE_COUNT 0x20c2
+#define mmCP_DE_LAST_INVAL_COUNT 0x20c3
+#define mmCP_DE_DE_COUNT 0x20c4
+#define mmCP_EOP_DONE_EVENT_CNTL 0xc0d5
+#define mmCP_EOP_DONE_DATA_CNTL 0xc0d6
+#define mmCP_EOP_DONE_CNTX_ID 0xc0d7
+#define mmCP_EOP_DONE_ADDR_LO 0xc000
+#define mmCP_EOP_DONE_ADDR_HI 0xc001
+#define mmCP_EOP_DONE_DATA_LO 0xc002
+#define mmCP_EOP_DONE_DATA_HI 0xc003
+#define mmCP_EOP_LAST_FENCE_LO 0xc004
+#define mmCP_EOP_LAST_FENCE_HI 0xc005
+#define mmCP_STREAM_OUT_ADDR_LO 0xc006
+#define mmCP_STREAM_OUT_ADDR_HI 0xc007
+#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0xc008
+#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0xc009
+#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0xc00a
+#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0xc00b
+#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0xc00c
+#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0xc00d
+#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0xc00e
+#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0xc00f
+#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0xc010
+#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0xc011
+#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0xc012
+#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0xc013
+#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0xc014
+#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0xc015
+#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0xc016
+#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0xc017
+#define mmCP_PIPE_STATS_ADDR_LO 0xc018
+#define mmCP_PIPE_STATS_ADDR_HI 0xc019
+#define mmCP_VGT_IAVERT_COUNT_LO 0xc01a
+#define mmCP_VGT_IAVERT_COUNT_HI 0xc01b
+#define mmCP_VGT_IAPRIM_COUNT_LO 0xc01c
+#define mmCP_VGT_IAPRIM_COUNT_HI 0xc01d
+#define mmCP_VGT_GSPRIM_COUNT_LO 0xc01e
+#define mmCP_VGT_GSPRIM_COUNT_HI 0xc01f
+#define mmCP_VGT_VSINVOC_COUNT_LO 0xc020
+#define mmCP_VGT_VSINVOC_COUNT_HI 0xc021
+#define mmCP_VGT_GSINVOC_COUNT_LO 0xc022
+#define mmCP_VGT_GSINVOC_COUNT_HI 0xc023
+#define mmCP_VGT_HSINVOC_COUNT_LO 0xc024
+#define mmCP_VGT_HSINVOC_COUNT_HI 0xc025
+#define mmCP_VGT_DSINVOC_COUNT_LO 0xc026
+#define mmCP_VGT_DSINVOC_COUNT_HI 0xc027
+#define mmCP_PA_CINVOC_COUNT_LO 0xc028
+#define mmCP_PA_CINVOC_COUNT_HI 0xc029
+#define mmCP_PA_CPRIM_COUNT_LO 0xc02a
+#define mmCP_PA_CPRIM_COUNT_HI 0xc02b
+#define mmCP_SC_PSINVOC_COUNT0_LO 0xc02c
+#define mmCP_SC_PSINVOC_COUNT0_HI 0xc02d
+#define mmCP_SC_PSINVOC_COUNT1_LO 0xc02e
+#define mmCP_SC_PSINVOC_COUNT1_HI 0xc02f
+#define mmCP_VGT_CSINVOC_COUNT_LO 0xc030
+#define mmCP_VGT_CSINVOC_COUNT_HI 0xc031
+#define mmCP_PIPE_STATS_CONTROL 0xc03d
+#define mmCP_STREAM_OUT_CONTROL 0xc03e
+#define mmCP_STRMOUT_CNTL 0xc03f
+#define mmSCRATCH_REG0 0xc040
+#define mmSCRATCH_REG1 0xc041
+#define mmSCRATCH_REG2 0xc042
+#define mmSCRATCH_REG3 0xc043
+#define mmSCRATCH_REG4 0xc044
+#define mmSCRATCH_REG5 0xc045
+#define mmSCRATCH_REG6 0xc046
+#define mmSCRATCH_REG7 0xc047
+#define mmSCRATCH_UMSK 0xc050
+#define mmSCRATCH_ADDR 0xc051
+#define mmCP_PFP_ATOMIC_PREOP_LO 0xc052
+#define mmCP_PFP_ATOMIC_PREOP_HI 0xc053
+#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0xc054
+#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0xc055
+#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0xc056
+#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0xc057
+#define mmCP_APPEND_ADDR_LO 0xc058
+#define mmCP_APPEND_ADDR_HI 0xc059
+#define mmCP_APPEND_DATA 0xc05a
+#define mmCP_APPEND_LAST_CS_FENCE 0xc05b
+#define mmCP_APPEND_LAST_PS_FENCE 0xc05c
+#define mmCP_ATOMIC_PREOP_LO 0xc05d
+#define mmCP_ME_ATOMIC_PREOP_LO 0xc05d
+#define mmCP_ATOMIC_PREOP_HI 0xc05e
+#define mmCP_ME_ATOMIC_PREOP_HI 0xc05e
+#define mmCP_GDS_ATOMIC0_PREOP_LO 0xc05f
+#define mmCP_ME_GDS_ATOMIC0_PREOP_LO 0xc05f
+#define mmCP_GDS_ATOMIC0_PREOP_HI 0xc060
+#define mmCP_ME_GDS_ATOMIC0_PREOP_HI 0xc060
+#define mmCP_GDS_ATOMIC1_PREOP_LO 0xc061
+#define mmCP_ME_GDS_ATOMIC1_PREOP_LO 0xc061
+#define mmCP_GDS_ATOMIC1_PREOP_HI 0xc062
+#define mmCP_ME_GDS_ATOMIC1_PREOP_HI 0xc062
+#define mmCP_ME_MC_WADDR_LO 0xc069
+#define mmCP_ME_MC_WADDR_HI 0xc06a
+#define mmCP_ME_MC_WDATA_LO 0xc06b
+#define mmCP_ME_MC_WDATA_HI 0xc06c
+#define mmCP_ME_MC_RADDR_LO 0xc06d
+#define mmCP_ME_MC_RADDR_HI 0xc06e
+#define mmCP_SEM_WAIT_TIMER 0xc06f
+#define mmCP_SIG_SEM_ADDR_LO 0xc070
+#define mmCP_SIG_SEM_ADDR_HI 0xc071
+#define mmCP_WAIT_SEM_ADDR_LO 0xc075
+#define mmCP_WAIT_SEM_ADDR_HI 0xc076
+#define mmCP_WAIT_REG_MEM_TIMEOUT 0xc074
+#define mmCP_COHER_START_DELAY 0xc07b
+#define mmCP_COHER_CNTL 0xc07c
+#define mmCP_COHER_SIZE 0xc07d
+#define mmCP_COHER_SIZE_HI 0xc08c
+#define mmCP_COHER_BASE 0xc07e
+#define mmCP_COHER_BASE_HI 0xc079
+#define mmCP_COHER_STATUS 0xc07f
+#define mmCOHER_DEST_BASE_0 0xa092
+#define mmCOHER_DEST_BASE_1 0xa093
+#define mmCOHER_DEST_BASE_2 0xa07e
+#define mmCOHER_DEST_BASE_3 0xa07f
+#define mmCOHER_DEST_BASE_HI_0 0xa07a
+#define mmCOHER_DEST_BASE_HI_1 0xa07b
+#define mmCOHER_DEST_BASE_HI_2 0xa07c
+#define mmCOHER_DEST_BASE_HI_3 0xa07d
+#define mmCP_DMA_ME_SRC_ADDR 0xc080
+#define mmCP_DMA_ME_SRC_ADDR_HI 0xc081
+#define mmCP_DMA_ME_DST_ADDR 0xc082
+#define mmCP_DMA_ME_DST_ADDR_HI 0xc083
+#define mmCP_DMA_ME_CONTROL 0xc078
+#define mmCP_DMA_ME_COMMAND 0xc084
+#define mmCP_DMA_PFP_SRC_ADDR 0xc085
+#define mmCP_DMA_PFP_SRC_ADDR_HI 0xc086
+#define mmCP_DMA_PFP_DST_ADDR 0xc087
+#define mmCP_DMA_PFP_DST_ADDR_HI 0xc088
+#define mmCP_DMA_PFP_CONTROL 0xc077
+#define mmCP_DMA_PFP_COMMAND 0xc089
+#define mmCP_DMA_CNTL 0xc08a
+#define mmCP_DMA_READ_TAGS 0xc08b
+#define mmCP_PFP_IB_CONTROL 0xc08d
+#define mmCP_PFP_LOAD_CONTROL 0xc08e
+#define mmCP_SCRATCH_INDEX 0xc08f
+#define mmCP_SCRATCH_DATA 0xc090
+#define mmCP_RB_OFFSET 0xc091
+#define mmCP_IB1_OFFSET 0xc092
+#define mmCP_IB2_OFFSET 0xc093
+#define mmCP_IB1_PREAMBLE_BEGIN 0xc094
+#define mmCP_IB1_PREAMBLE_END 0xc095
+#define mmCP_IB2_PREAMBLE_BEGIN 0xc096
+#define mmCP_IB2_PREAMBLE_END 0xc097
+#define mmCP_CE_IB1_OFFSET 0xc098
+#define mmCP_CE_IB2_OFFSET 0xc099
+#define mmCP_CE_COUNTER 0xc09a
+#define mmCP_CE_RB_OFFSET 0xc09b
+#define mmCP_PFP_COMPLETION_STATUS 0xc0ec
+#define mmCP_CE_COMPLETION_STATUS 0xc0ed
+#define mmCP_PRED_NOT_VISIBLE 0xc0ee
+#define mmCP_PFP_METADATA_BASE_ADDR 0xc0f0
+#define mmCP_PFP_METADATA_BASE_ADDR_HI 0xc0f1
+#define mmCP_CE_METADATA_BASE_ADDR 0xc0f2
+#define mmCP_CE_METADATA_BASE_ADDR_HI 0xc0f3
+#define mmCP_DRAW_INDX_INDR_ADDR 0xc0f4
+#define mmCP_DRAW_INDX_INDR_ADDR_HI 0xc0f5
+#define mmCP_DISPATCH_INDR_ADDR 0xc0f6
+#define mmCP_DISPATCH_INDR_ADDR_HI 0xc0f7
+#define mmCP_INDEX_BASE_ADDR 0xc0f8
+#define mmCP_INDEX_BASE_ADDR_HI 0xc0f9
+#define mmCP_INDEX_TYPE 0xc0fa
+#define mmCP_GDS_BKUP_ADDR 0xc0fb
+#define mmCP_GDS_BKUP_ADDR_HI 0xc0fc
+#define mmCP_SAMPLE_STATUS 0xc0fd
+#define mmCP_STALLED_STAT1 0x219d
+#define mmCP_STALLED_STAT2 0x219e
+#define mmCP_STALLED_STAT3 0x219c
+#define mmCP_BUSY_STAT 0x219f
+#define mmCP_STAT 0x21a0
+#define mmCP_ME_HEADER_DUMP 0x21a1
+#define mmCP_PFP_HEADER_DUMP 0x21a2
+#define mmCP_GRBM_FREE_COUNT 0x21a3
+#define mmCP_CE_HEADER_DUMP 0x21a4
+#define mmCP_CSF_STAT 0x21b4
+#define mmCP_CSF_CNTL 0x21b5
+#define mmCP_ME_CNTL 0x21b6
+#define mmCP_CNTX_STAT 0x21b8
+#define mmCP_ME_PREEMPTION 0x21b9
+#define mmCP_RB0_RPTR 0x21c0
+#define mmCP_RB_RPTR 0x21c0
+#define mmCP_RB1_RPTR 0x21bf
+#define mmCP_RB2_RPTR 0x21be
+#define mmCP_RB_WPTR_DELAY 0x21c1
+#define mmCP_RB_WPTR_POLL_CNTL 0x21c2
+#define mmCP_CE_INIT_BASE_LO 0xc0c3
+#define mmCP_CE_INIT_BASE_HI 0xc0c4
+#define mmCP_CE_INIT_BUFSZ 0xc0c5
+#define mmCP_CE_IB1_BASE_LO 0xc0c6
+#define mmCP_CE_IB1_BASE_HI 0xc0c7
+#define mmCP_CE_IB1_BUFSZ 0xc0c8
+#define mmCP_CE_IB2_BASE_LO 0xc0c9
+#define mmCP_CE_IB2_BASE_HI 0xc0ca
+#define mmCP_CE_IB2_BUFSZ 0xc0cb
+#define mmCP_IB1_BASE_LO 0xc0cc
+#define mmCP_IB1_BASE_HI 0xc0cd
+#define mmCP_IB1_BUFSZ 0xc0ce
+#define mmCP_IB2_BASE_LO 0xc0cf
+#define mmCP_IB2_BASE_HI 0xc0d0
+#define mmCP_IB2_BUFSZ 0xc0d1
+#define mmCP_ST_BASE_LO 0xc0d2
+#define mmCP_ST_BASE_HI 0xc0d3
+#define mmCP_ST_BUFSZ 0xc0d4
+#define mmCP_ROQ_THRESHOLDS 0x21bc
+#define mmCP_MEQ_STQ_THRESHOLD 0x21bd
+#define mmCP_ROQ1_THRESHOLDS 0x21d5
+#define mmCP_ROQ2_THRESHOLDS 0x21d6
+#define mmCP_STQ_THRESHOLDS 0x21d7
+#define mmCP_QUEUE_THRESHOLDS 0x21d8
+#define mmCP_MEQ_THRESHOLDS 0x21d9
+#define mmCP_ROQ_AVAIL 0x21da
+#define mmCP_STQ_AVAIL 0x21db
+#define mmCP_ROQ2_AVAIL 0x21dc
+#define mmCP_MEQ_AVAIL 0x21dd
+#define mmCP_CMD_INDEX 0x21de
+#define mmCP_CMD_DATA 0x21df
+#define mmCP_ROQ_RB_STAT 0x21e0
+#define mmCP_ROQ_IB1_STAT 0x21e1
+#define mmCP_ROQ_IB2_STAT 0x21e2
+#define mmCP_STQ_STAT 0x21e3
+#define mmCP_STQ_WR_STAT 0x21e4
+#define mmCP_MEQ_STAT 0x21e5
+#define mmCP_CEQ1_AVAIL 0x21e6
+#define mmCP_CEQ2_AVAIL 0x21e7
+#define mmCP_CE_ROQ_RB_STAT 0x21e8
+#define mmCP_CE_ROQ_IB1_STAT 0x21e9
+#define mmCP_CE_ROQ_IB2_STAT 0x21ea
+#define mmCP_INT_STAT_DEBUG 0x21f7
+#define mmCP_PERFMON_CNTL 0xd808
+#define mmCP_PERFMON_CNTX_CNTL 0xa0d8
+#define mmCP_RINGID 0xa0d9
+#define mmCP_PIPEID 0xa0d9
+#define mmCP_VMID 0xa0da
+#define mmCP_HPD_ROQ_OFFSETS 0x3240
+#define mmCP_HPD_STATUS0 0x3241
+#define mmCP_MQD_BASE_ADDR 0x3245
+#define mmCP_MQD_BASE_ADDR_HI 0x3246
+#define mmCP_HQD_ACTIVE 0x3247
+#define mmCP_HQD_VMID 0x3248
+#define mmCP_HQD_PERSISTENT_STATE 0x3249
+#define mmCP_HQD_PIPE_PRIORITY 0x324a
+#define mmCP_HQD_QUEUE_PRIORITY 0x324b
+#define mmCP_HQD_QUANTUM 0x324c
+#define mmCP_HQD_PQ_BASE 0x324d
+#define mmCP_HQD_PQ_BASE_HI 0x324e
+#define mmCP_HQD_PQ_RPTR 0x324f
+#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x3250
+#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x3251
+#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x3252
+#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x3253
+#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254
+#define mmCP_HQD_PQ_WPTR 0x3255
+#define mmCP_HQD_PQ_CONTROL 0x3256
+#define mmCP_HQD_IB_BASE_ADDR 0x3257
+#define mmCP_HQD_IB_BASE_ADDR_HI 0x3258
+#define mmCP_HQD_IB_RPTR 0x3259
+#define mmCP_HQD_IB_CONTROL 0x325a
+#define mmCP_HQD_IQ_TIMER 0x325b
+#define mmCP_HQD_IQ_RPTR 0x325c
+#define mmCP_HQD_DEQUEUE_REQUEST 0x325d
+#define mmCP_HQD_DMA_OFFLOAD 0x325e
+#define mmCP_HQD_OFFLOAD 0x325e
+#define mmCP_HQD_SEMA_CMD 0x325f
+#define mmCP_HQD_MSG_TYPE 0x3260
+#define mmCP_HQD_ATOMIC0_PREOP_LO 0x3261
+#define mmCP_HQD_ATOMIC0_PREOP_HI 0x3262
+#define mmCP_HQD_ATOMIC1_PREOP_LO 0x3263
+#define mmCP_HQD_ATOMIC1_PREOP_HI 0x3264
+#define mmCP_HQD_HQ_SCHEDULER0 0x3265
+#define mmCP_HQD_HQ_STATUS0 0x3265
+#define mmCP_HQD_HQ_SCHEDULER1 0x3266
+#define mmCP_HQD_HQ_CONTROL0 0x3266
+#define mmCP_MQD_CONTROL 0x3267
+#define mmCP_HQD_HQ_STATUS1 0x3268
+#define mmCP_HQD_HQ_CONTROL1 0x3269
+#define mmCP_HQD_EOP_BASE_ADDR 0x326a
+#define mmCP_HQD_EOP_BASE_ADDR_HI 0x326b
+#define mmCP_HQD_EOP_CONTROL 0x326c
+#define mmCP_HQD_EOP_RPTR 0x326d
+#define mmCP_HQD_EOP_WPTR 0x326e
+#define mmCP_HQD_EOP_EVENTS 0x326f
+#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x3270
+#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x3271
+#define mmCP_HQD_CTX_SAVE_CONTROL 0x3272
+#define mmCP_HQD_CNTL_STACK_OFFSET 0x3273
+#define mmCP_HQD_CNTL_STACK_SIZE 0x3274
+#define mmCP_HQD_WG_STATE_OFFSET 0x3275
+#define mmCP_HQD_CTX_SAVE_SIZE 0x3276
+#define mmCP_HQD_GDS_RESOURCE_STATE 0x3277
+#define mmCP_HQD_ERROR 0x3278
+#define mmCP_HQD_EOP_WPTR_MEM 0x3279
+#define mmCP_HQD_EOP_DONES 0x327a
+#define mmDB_Z_READ_BASE 0xa012
+#define mmDB_STENCIL_READ_BASE 0xa013
+#define mmDB_Z_WRITE_BASE 0xa014
+#define mmDB_STENCIL_WRITE_BASE 0xa015
+#define mmDB_DEPTH_INFO 0xa00f
+#define mmDB_Z_INFO 0xa010
+#define mmDB_STENCIL_INFO 0xa011
+#define mmDB_DEPTH_SIZE 0xa016
+#define mmDB_DEPTH_SLICE 0xa017
+#define mmDB_DEPTH_VIEW 0xa002
+#define mmDB_RENDER_CONTROL 0xa000
+#define mmDB_COUNT_CONTROL 0xa001
+#define mmDB_RENDER_OVERRIDE 0xa003
+#define mmDB_RENDER_OVERRIDE2 0xa004
+#define mmDB_EQAA 0xa201
+#define mmDB_SHADER_CONTROL 0xa203
+#define mmDB_DEPTH_BOUNDS_MIN 0xa008
+#define mmDB_DEPTH_BOUNDS_MAX 0xa009
+#define mmDB_STENCIL_CLEAR 0xa00a
+#define mmDB_DEPTH_CLEAR 0xa00b
+#define mmDB_HTILE_DATA_BASE 0xa005
+#define mmDB_HTILE_SURFACE 0xa2af
+#define mmDB_PRELOAD_CONTROL 0xa2b2
+#define mmDB_STENCILREFMASK 0xa10c
+#define mmDB_STENCILREFMASK_BF 0xa10d
+#define mmDB_SRESULTS_COMPARE_STATE0 0xa2b0
+#define mmDB_SRESULTS_COMPARE_STATE1 0xa2b1
+#define mmDB_DEPTH_CONTROL 0xa200
+#define mmDB_STENCIL_CONTROL 0xa10b
+#define mmDB_ALPHA_TO_MASK 0xa2dc
+#define mmDB_PERFCOUNTER0_SELECT 0xdc40
+#define mmDB_PERFCOUNTER1_SELECT 0xdc42
+#define mmDB_PERFCOUNTER2_SELECT 0xdc44
+#define mmDB_PERFCOUNTER3_SELECT 0xdc46
+#define mmDB_PERFCOUNTER0_SELECT1 0xdc41
+#define mmDB_PERFCOUNTER1_SELECT1 0xdc43
+#define mmDB_PERFCOUNTER0_LO 0xd440
+#define mmDB_PERFCOUNTER1_LO 0xd442
+#define mmDB_PERFCOUNTER2_LO 0xd444
+#define mmDB_PERFCOUNTER3_LO 0xd446
+#define mmDB_PERFCOUNTER0_HI 0xd441
+#define mmDB_PERFCOUNTER1_HI 0xd443
+#define mmDB_PERFCOUNTER2_HI 0xd445
+#define mmDB_PERFCOUNTER3_HI 0xd447
+#define mmDB_DEBUG 0x260c
+#define mmDB_DEBUG2 0x260d
+#define mmDB_DEBUG3 0x260e
+#define mmDB_DEBUG4 0x260f
+#define mmDB_CREDIT_LIMIT 0x2614
+#define mmDB_WATERMARKS 0x2615
+#define mmDB_SUBTILE_CONTROL 0x2616
+#define mmDB_FREE_CACHELINES 0x2617
+#define mmDB_FIFO_DEPTH1 0x2618
+#define mmDB_FIFO_DEPTH2 0x2619
+#define mmDB_CGTT_CLK_CTRL_0 0xf0a4
+#define mmDB_ZPASS_COUNT_LOW 0xc3fe
+#define mmDB_ZPASS_COUNT_HI 0xc3ff
+#define mmDB_RING_CONTROL 0x261b
+#define mmDB_READ_DEBUG_0 0x2620
+#define mmDB_READ_DEBUG_1 0x2621
+#define mmDB_READ_DEBUG_2 0x2622
+#define mmDB_READ_DEBUG_3 0x2623
+#define mmDB_READ_DEBUG_4 0x2624
+#define mmDB_READ_DEBUG_5 0x2625
+#define mmDB_READ_DEBUG_6 0x2626
+#define mmDB_READ_DEBUG_7 0x2627
+#define mmDB_READ_DEBUG_8 0x2628
+#define mmDB_READ_DEBUG_9 0x2629
+#define mmDB_READ_DEBUG_A 0x262a
+#define mmDB_READ_DEBUG_B 0x262b
+#define mmDB_READ_DEBUG_C 0x262c
+#define mmDB_READ_DEBUG_D 0x262d
+#define mmDB_READ_DEBUG_E 0x262e
+#define mmDB_READ_DEBUG_F 0x262f
+#define mmDB_OCCLUSION_COUNT0_LOW 0xc3c0
+#define mmDB_OCCLUSION_COUNT0_HI 0xc3c1
+#define mmDB_OCCLUSION_COUNT1_LOW 0xc3c2
+#define mmDB_OCCLUSION_COUNT1_HI 0xc3c3
+#define mmDB_OCCLUSION_COUNT2_LOW 0xc3c4
+#define mmDB_OCCLUSION_COUNT2_HI 0xc3c5
+#define mmDB_OCCLUSION_COUNT3_LOW 0xc3c6
+#define mmDB_OCCLUSION_COUNT3_HI 0xc3c7
+#define mmCC_RB_REDUNDANCY 0x263c
+#define mmCC_RB_BACKEND_DISABLE 0x263d
+#define mmGC_USER_RB_REDUNDANCY 0x26de
+#define mmGC_USER_RB_BACKEND_DISABLE 0x26df
+#define mmGB_ADDR_CONFIG 0x263e
+#define mmGB_BACKEND_MAP 0x263f
+#define mmGB_GPU_ID 0x2640
+#define mmCC_RB_DAISY_CHAIN 0x2641
+#define mmGB_TILE_MODE0 0x2644
+#define mmGB_TILE_MODE1 0x2645
+#define mmGB_TILE_MODE2 0x2646
+#define mmGB_TILE_MODE3 0x2647
+#define mmGB_TILE_MODE4 0x2648
+#define mmGB_TILE_MODE5 0x2649
+#define mmGB_TILE_MODE6 0x264a
+#define mmGB_TILE_MODE7 0x264b
+#define mmGB_TILE_MODE8 0x264c
+#define mmGB_TILE_MODE9 0x264d
+#define mmGB_TILE_MODE10 0x264e
+#define mmGB_TILE_MODE11 0x264f
+#define mmGB_TILE_MODE12 0x2650
+#define mmGB_TILE_MODE13 0x2651
+#define mmGB_TILE_MODE14 0x2652
+#define mmGB_TILE_MODE15 0x2653
+#define mmGB_TILE_MODE16 0x2654
+#define mmGB_TILE_MODE17 0x2655
+#define mmGB_TILE_MODE18 0x2656
+#define mmGB_TILE_MODE19 0x2657
+#define mmGB_TILE_MODE20 0x2658
+#define mmGB_TILE_MODE21 0x2659
+#define mmGB_TILE_MODE22 0x265a
+#define mmGB_TILE_MODE23 0x265b
+#define mmGB_TILE_MODE24 0x265c
+#define mmGB_TILE_MODE25 0x265d
+#define mmGB_TILE_MODE26 0x265e
+#define mmGB_TILE_MODE27 0x265f
+#define mmGB_TILE_MODE28 0x2660
+#define mmGB_TILE_MODE29 0x2661
+#define mmGB_TILE_MODE30 0x2662
+#define mmGB_TILE_MODE31 0x2663
+#define mmGB_MACROTILE_MODE0 0x2664
+#define mmGB_MACROTILE_MODE1 0x2665
+#define mmGB_MACROTILE_MODE2 0x2666
+#define mmGB_MACROTILE_MODE3 0x2667
+#define mmGB_MACROTILE_MODE4 0x2668
+#define mmGB_MACROTILE_MODE5 0x2669
+#define mmGB_MACROTILE_MODE6 0x266a
+#define mmGB_MACROTILE_MODE7 0x266b
+#define mmGB_MACROTILE_MODE8 0x266c
+#define mmGB_MACROTILE_MODE9 0x266d
+#define mmGB_MACROTILE_MODE10 0x266e
+#define mmGB_MACROTILE_MODE11 0x266f
+#define mmGB_MACROTILE_MODE12 0x2670
+#define mmGB_MACROTILE_MODE13 0x2671
+#define mmGB_MACROTILE_MODE14 0x2672
+#define mmGB_MACROTILE_MODE15 0x2673
+#define mmGB_EDC_MODE 0x307e
+#define mmCC_GC_EDC_CONFIG 0x3098
+#define mmRAS_SIGNATURE_CONTROL 0x3380
+#define mmRAS_SIGNATURE_MASK 0x3381
+#define mmRAS_SX_SIGNATURE0 0x3382
+#define mmRAS_SX_SIGNATURE1 0x3383
+#define mmRAS_SX_SIGNATURE2 0x3384
+#define mmRAS_SX_SIGNATURE3 0x3385
+#define mmRAS_DB_SIGNATURE0 0x338b
+#define mmRAS_PA_SIGNATURE0 0x338c
+#define mmRAS_VGT_SIGNATURE0 0x338d
+#define mmRAS_SQ_SIGNATURE0 0x338e
+#define mmRAS_SC_SIGNATURE0 0x338f
+#define mmRAS_SC_SIGNATURE1 0x3390
+#define mmRAS_SC_SIGNATURE2 0x3391
+#define mmRAS_SC_SIGNATURE3 0x3392
+#define mmRAS_SC_SIGNATURE4 0x3393
+#define mmRAS_SC_SIGNATURE5 0x3394
+#define mmRAS_SC_SIGNATURE6 0x3395
+#define mmRAS_SC_SIGNATURE7 0x3396
+#define mmRAS_IA_SIGNATURE0 0x3397
+#define mmRAS_IA_SIGNATURE1 0x3398
+#define mmRAS_SPI_SIGNATURE0 0x3399
+#define mmRAS_SPI_SIGNATURE1 0x339a
+#define mmRAS_TA_SIGNATURE0 0x339b
+#define mmRAS_TD_SIGNATURE0 0x339c
+#define mmRAS_CB_SIGNATURE0 0x339d
+#define mmRAS_BCI_SIGNATURE0 0x339e
+#define mmRAS_BCI_SIGNATURE1 0x339f
+#define mmRAS_TA_SIGNATURE1 0x33a0
+#define mmGRBM_HYP_CAM_INDEX 0xf83e
+#define mmGRBM_CAM_INDEX 0xf83e
+#define mmGRBM_HYP_CAM_DATA 0xf83f
+#define mmGRBM_CAM_DATA 0xf83f
+#define mmGRBM_CNTL 0x2000
+#define mmGRBM_SKEW_CNTL 0x2001
+#define mmGRBM_PWR_CNTL 0x2003
+#define mmGRBM_STATUS 0x2004
+#define mmGRBM_STATUS2 0x2002
+#define mmGRBM_STATUS_SE0 0x2005
+#define mmGRBM_STATUS_SE1 0x2006
+#define mmGRBM_STATUS_SE2 0x200e
+#define mmGRBM_STATUS_SE3 0x200f
+#define mmGRBM_SOFT_RESET 0x2008
+#define mmGRBM_DEBUG_CNTL 0x2009
+#define mmGRBM_DEBUG_DATA 0x200a
+#define mmGRBM_GFX_INDEX 0xc200
+#define mmGRBM_GFX_CLKEN_CNTL 0x200c
+#define mmGRBM_WAIT_IDLE_CLOCKS 0x200d
+#define mmGRBM_DEBUG 0x2014
+#define mmGRBM_DEBUG_SNAPSHOT 0x2015
+#define mmGRBM_READ_ERROR 0x2016
+#define mmGRBM_READ_ERROR2 0x2017
+#define mmGRBM_INT_CNTL 0x2018
+#define mmGRBM_TRAP_OP 0x2019
+#define mmGRBM_TRAP_ADDR 0x201a
+#define mmGRBM_TRAP_ADDR_MSK 0x201b
+#define mmGRBM_TRAP_WD 0x201c
+#define mmGRBM_TRAP_WD_MSK 0x201d
+#define mmGRBM_DSM_BYPASS 0x201e
+#define mmGRBM_WRITE_ERROR 0x201f
+#define mmGRBM_PERFCOUNTER0_SELECT 0xd840
+#define mmGRBM_PERFCOUNTER1_SELECT 0xd841
+#define mmGRBM_SE0_PERFCOUNTER_SELECT 0xd842
+#define mmGRBM_SE1_PERFCOUNTER_SELECT 0xd843
+#define mmGRBM_SE2_PERFCOUNTER_SELECT 0xd844
+#define mmGRBM_SE3_PERFCOUNTER_SELECT 0xd845
+#define mmGRBM_PERFCOUNTER0_LO 0xd040
+#define mmGRBM_PERFCOUNTER0_HI 0xd041
+#define mmGRBM_PERFCOUNTER1_LO 0xd043
+#define mmGRBM_PERFCOUNTER1_HI 0xd044
+#define mmGRBM_SE0_PERFCOUNTER_LO 0xd045
+#define mmGRBM_SE0_PERFCOUNTER_HI 0xd046
+#define mmGRBM_SE1_PERFCOUNTER_LO 0xd047
+#define mmGRBM_SE1_PERFCOUNTER_HI 0xd048
+#define mmGRBM_SE2_PERFCOUNTER_LO 0xd049
+#define mmGRBM_SE2_PERFCOUNTER_HI 0xd04a
+#define mmGRBM_SE3_PERFCOUNTER_LO 0xd04b
+#define mmGRBM_SE3_PERFCOUNTER_HI 0xd04c
+#define mmGRBM_SCRATCH_REG0 0x2040
+#define mmGRBM_SCRATCH_REG1 0x2041
+#define mmGRBM_SCRATCH_REG2 0x2042
+#define mmGRBM_SCRATCH_REG3 0x2043
+#define mmGRBM_SCRATCH_REG4 0x2044
+#define mmGRBM_SCRATCH_REG5 0x2045
+#define mmGRBM_SCRATCH_REG6 0x2046
+#define mmGRBM_SCRATCH_REG7 0x2047
+#define mmDEBUG_INDEX 0x203c
+#define mmDEBUG_DATA 0x203d
+#define mmGRBM_NOWHERE 0x203f
+#define mmPA_CL_VPORT_XSCALE 0xa10f
+#define mmPA_CL_VPORT_XOFFSET 0xa110
+#define mmPA_CL_VPORT_YSCALE 0xa111
+#define mmPA_CL_VPORT_YOFFSET 0xa112
+#define mmPA_CL_VPORT_ZSCALE 0xa113
+#define mmPA_CL_VPORT_ZOFFSET 0xa114
+#define mmPA_CL_VPORT_XSCALE_1 0xa115
+#define mmPA_CL_VPORT_XSCALE_2 0xa11b
+#define mmPA_CL_VPORT_XSCALE_3 0xa121
+#define mmPA_CL_VPORT_XSCALE_4 0xa127
+#define mmPA_CL_VPORT_XSCALE_5 0xa12d
+#define mmPA_CL_VPORT_XSCALE_6 0xa133
+#define mmPA_CL_VPORT_XSCALE_7 0xa139
+#define mmPA_CL_VPORT_XSCALE_8 0xa13f
+#define mmPA_CL_VPORT_XSCALE_9 0xa145
+#define mmPA_CL_VPORT_XSCALE_10 0xa14b
+#define mmPA_CL_VPORT_XSCALE_11 0xa151
+#define mmPA_CL_VPORT_XSCALE_12 0xa157
+#define mmPA_CL_VPORT_XSCALE_13 0xa15d
+#define mmPA_CL_VPORT_XSCALE_14 0xa163
+#define mmPA_CL_VPORT_XSCALE_15 0xa169
+#define mmPA_CL_VPORT_XOFFSET_1 0xa116
+#define mmPA_CL_VPORT_XOFFSET_2 0xa11c
+#define mmPA_CL_VPORT_XOFFSET_3 0xa122
+#define mmPA_CL_VPORT_XOFFSET_4 0xa128
+#define mmPA_CL_VPORT_XOFFSET_5 0xa12e
+#define mmPA_CL_VPORT_XOFFSET_6 0xa134
+#define mmPA_CL_VPORT_XOFFSET_7 0xa13a
+#define mmPA_CL_VPORT_XOFFSET_8 0xa140
+#define mmPA_CL_VPORT_XOFFSET_9 0xa146
+#define mmPA_CL_VPORT_XOFFSET_10 0xa14c
+#define mmPA_CL_VPORT_XOFFSET_11 0xa152
+#define mmPA_CL_VPORT_XOFFSET_12 0xa158
+#define mmPA_CL_VPORT_XOFFSET_13 0xa15e
+#define mmPA_CL_VPORT_XOFFSET_14 0xa164
+#define mmPA_CL_VPORT_XOFFSET_15 0xa16a
+#define mmPA_CL_VPORT_YSCALE_1 0xa117
+#define mmPA_CL_VPORT_YSCALE_2 0xa11d
+#define mmPA_CL_VPORT_YSCALE_3 0xa123
+#define mmPA_CL_VPORT_YSCALE_4 0xa129
+#define mmPA_CL_VPORT_YSCALE_5 0xa12f
+#define mmPA_CL_VPORT_YSCALE_6 0xa135
+#define mmPA_CL_VPORT_YSCALE_7 0xa13b
+#define mmPA_CL_VPORT_YSCALE_8 0xa141
+#define mmPA_CL_VPORT_YSCALE_9 0xa147
+#define mmPA_CL_VPORT_YSCALE_10 0xa14d
+#define mmPA_CL_VPORT_YSCALE_11 0xa153
+#define mmPA_CL_VPORT_YSCALE_12 0xa159
+#define mmPA_CL_VPORT_YSCALE_13 0xa15f
+#define mmPA_CL_VPORT_YSCALE_14 0xa165
+#define mmPA_CL_VPORT_YSCALE_15 0xa16b
+#define mmPA_CL_VPORT_YOFFSET_1 0xa118
+#define mmPA_CL_VPORT_YOFFSET_2 0xa11e
+#define mmPA_CL_VPORT_YOFFSET_3 0xa124
+#define mmPA_CL_VPORT_YOFFSET_4 0xa12a
+#define mmPA_CL_VPORT_YOFFSET_5 0xa130
+#define mmPA_CL_VPORT_YOFFSET_6 0xa136
+#define mmPA_CL_VPORT_YOFFSET_7 0xa13c
+#define mmPA_CL_VPORT_YOFFSET_8 0xa142
+#define mmPA_CL_VPORT_YOFFSET_9 0xa148
+#define mmPA_CL_VPORT_YOFFSET_10 0xa14e
+#define mmPA_CL_VPORT_YOFFSET_11 0xa154
+#define mmPA_CL_VPORT_YOFFSET_12 0xa15a
+#define mmPA_CL_VPORT_YOFFSET_13 0xa160
+#define mmPA_CL_VPORT_YOFFSET_14 0xa166
+#define mmPA_CL_VPORT_YOFFSET_15 0xa16c
+#define mmPA_CL_VPORT_ZSCALE_1 0xa119
+#define mmPA_CL_VPORT_ZSCALE_2 0xa11f
+#define mmPA_CL_VPORT_ZSCALE_3 0xa125
+#define mmPA_CL_VPORT_ZSCALE_4 0xa12b
+#define mmPA_CL_VPORT_ZSCALE_5 0xa131
+#define mmPA_CL_VPORT_ZSCALE_6 0xa137
+#define mmPA_CL_VPORT_ZSCALE_7 0xa13d
+#define mmPA_CL_VPORT_ZSCALE_8 0xa143
+#define mmPA_CL_VPORT_ZSCALE_9 0xa149
+#define mmPA_CL_VPORT_ZSCALE_10 0xa14f
+#define mmPA_CL_VPORT_ZSCALE_11 0xa155
+#define mmPA_CL_VPORT_ZSCALE_12 0xa15b
+#define mmPA_CL_VPORT_ZSCALE_13 0xa161
+#define mmPA_CL_VPORT_ZSCALE_14 0xa167
+#define mmPA_CL_VPORT_ZSCALE_15 0xa16d
+#define mmPA_CL_VPORT_ZOFFSET_1 0xa11a
+#define mmPA_CL_VPORT_ZOFFSET_2 0xa120
+#define mmPA_CL_VPORT_ZOFFSET_3 0xa126
+#define mmPA_CL_VPORT_ZOFFSET_4 0xa12c
+#define mmPA_CL_VPORT_ZOFFSET_5 0xa132
+#define mmPA_CL_VPORT_ZOFFSET_6 0xa138
+#define mmPA_CL_VPORT_ZOFFSET_7 0xa13e
+#define mmPA_CL_VPORT_ZOFFSET_8 0xa144
+#define mmPA_CL_VPORT_ZOFFSET_9 0xa14a
+#define mmPA_CL_VPORT_ZOFFSET_10 0xa150
+#define mmPA_CL_VPORT_ZOFFSET_11 0xa156
+#define mmPA_CL_VPORT_ZOFFSET_12 0xa15c
+#define mmPA_CL_VPORT_ZOFFSET_13 0xa162
+#define mmPA_CL_VPORT_ZOFFSET_14 0xa168
+#define mmPA_CL_VPORT_ZOFFSET_15 0xa16e
+#define mmPA_CL_VTE_CNTL 0xa206
+#define mmPA_CL_VS_OUT_CNTL 0xa207
+#define mmPA_CL_NANINF_CNTL 0xa208
+#define mmPA_CL_CLIP_CNTL 0xa204
+#define mmPA_CL_GB_VERT_CLIP_ADJ 0xa2fa
+#define mmPA_CL_GB_VERT_DISC_ADJ 0xa2fb
+#define mmPA_CL_GB_HORZ_CLIP_ADJ 0xa2fc
+#define mmPA_CL_GB_HORZ_DISC_ADJ 0xa2fd
+#define mmPA_CL_UCP_0_X 0xa16f
+#define mmPA_CL_UCP_0_Y 0xa170
+#define mmPA_CL_UCP_0_Z 0xa171
+#define mmPA_CL_UCP_0_W 0xa172
+#define mmPA_CL_UCP_1_X 0xa173
+#define mmPA_CL_UCP_1_Y 0xa174
+#define mmPA_CL_UCP_1_Z 0xa175
+#define mmPA_CL_UCP_1_W 0xa176
+#define mmPA_CL_UCP_2_X 0xa177
+#define mmPA_CL_UCP_2_Y 0xa178
+#define mmPA_CL_UCP_2_Z 0xa179
+#define mmPA_CL_UCP_2_W 0xa17a
+#define mmPA_CL_UCP_3_X 0xa17b
+#define mmPA_CL_UCP_3_Y 0xa17c
+#define mmPA_CL_UCP_3_Z 0xa17d
+#define mmPA_CL_UCP_3_W 0xa17e
+#define mmPA_CL_UCP_4_X 0xa17f
+#define mmPA_CL_UCP_4_Y 0xa180
+#define mmPA_CL_UCP_4_Z 0xa181
+#define mmPA_CL_UCP_4_W 0xa182
+#define mmPA_CL_UCP_5_X 0xa183
+#define mmPA_CL_UCP_5_Y 0xa184
+#define mmPA_CL_UCP_5_Z 0xa185
+#define mmPA_CL_UCP_5_W 0xa186
+#define mmPA_CL_POINT_X_RAD 0xa1f5
+#define mmPA_CL_POINT_Y_RAD 0xa1f6
+#define mmPA_CL_POINT_SIZE 0xa1f7
+#define mmPA_CL_POINT_CULL_RAD 0xa1f8
+#define mmPA_CL_ENHANCE 0x2285
+#define mmPA_CL_RESET_DEBUG 0x2286
+#define mmPA_SU_VTX_CNTL 0xa2f9
+#define mmPA_SU_POINT_SIZE 0xa280
+#define mmPA_SU_POINT_MINMAX 0xa281
+#define mmPA_SU_LINE_CNTL 0xa282
+#define mmPA_SU_LINE_STIPPLE_CNTL 0xa209
+#define mmPA_SU_LINE_STIPPLE_SCALE 0xa20a
+#define mmPA_SU_PRIM_FILTER_CNTL 0xa20b
+#define mmPA_SU_SC_MODE_CNTL 0xa205
+#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0xa2de
+#define mmPA_SU_POLY_OFFSET_CLAMP 0xa2df
+#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0xa2e0
+#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0xa2e1
+#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0xa2e2
+#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0xa2e3
+#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0xa08d
+#define mmPA_SU_LINE_STIPPLE_VALUE 0xc280
+#define mmPA_SU_PERFCOUNTER0_SELECT 0xd900
+#define mmPA_SU_PERFCOUNTER0_SELECT1 0xd901
+#define mmPA_SU_PERFCOUNTER1_SELECT 0xd902
+#define mmPA_SU_PERFCOUNTER1_SELECT1 0xd903
+#define mmPA_SU_PERFCOUNTER2_SELECT 0xd904
+#define mmPA_SU_PERFCOUNTER3_SELECT 0xd905
+#define mmPA_SU_PERFCOUNTER0_LO 0xd100
+#define mmPA_SU_PERFCOUNTER0_HI 0xd101
+#define mmPA_SU_PERFCOUNTER1_LO 0xd102
+#define mmPA_SU_PERFCOUNTER1_HI 0xd103
+#define mmPA_SU_PERFCOUNTER2_LO 0xd104
+#define mmPA_SU_PERFCOUNTER2_HI 0xd105
+#define mmPA_SU_PERFCOUNTER3_LO 0xd106
+#define mmPA_SU_PERFCOUNTER3_HI 0xd107
+#define mmPA_SC_AA_CONFIG 0xa2f8
+#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0xa30e
+#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0xa30f
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0xa2fe
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0xa2ff
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0xa300
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0xa301
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0xa302
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0xa303
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0xa304
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0xa305
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0xa306
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0xa307
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0xa308
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0xa309
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0xa30a
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0xa30b
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0xa30c
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0xa30d
+#define mmPA_SC_CENTROID_PRIORITY_0 0xa2f5
+#define mmPA_SC_CENTROID_PRIORITY_1 0xa2f6
+#define mmPA_SC_CLIPRECT_0_TL 0xa084
+#define mmPA_SC_CLIPRECT_0_BR 0xa085
+#define mmPA_SC_CLIPRECT_1_TL 0xa086
+#define mmPA_SC_CLIPRECT_1_BR 0xa087
+#define mmPA_SC_CLIPRECT_2_TL 0xa088
+#define mmPA_SC_CLIPRECT_2_BR 0xa089
+#define mmPA_SC_CLIPRECT_3_TL 0xa08a
+#define mmPA_SC_CLIPRECT_3_BR 0xa08b
+#define mmPA_SC_CLIPRECT_RULE 0xa083
+#define mmPA_SC_EDGERULE 0xa08c
+#define mmPA_SC_LINE_CNTL 0xa2f7
+#define mmPA_SC_LINE_STIPPLE 0xa283
+#define mmPA_SC_MODE_CNTL_0 0xa292
+#define mmPA_SC_MODE_CNTL_1 0xa293
+#define mmPA_SC_RASTER_CONFIG 0xa0d4
+#define mmPA_SC_RASTER_CONFIG_1 0xa0d5
+#define mmPA_SC_SCREEN_EXTENT_CONTROL 0xa0d6
+#define mmPA_SC_GENERIC_SCISSOR_TL 0xa090
+#define mmPA_SC_GENERIC_SCISSOR_BR 0xa091
+#define mmPA_SC_SCREEN_SCISSOR_TL 0xa00c
+#define mmPA_SC_SCREEN_SCISSOR_BR 0xa00d
+#define mmPA_SC_WINDOW_OFFSET 0xa080
+#define mmPA_SC_WINDOW_SCISSOR_TL 0xa081
+#define mmPA_SC_WINDOW_SCISSOR_BR 0xa082
+#define mmPA_SC_VPORT_SCISSOR_0_TL 0xa094
+#define mmPA_SC_VPORT_SCISSOR_1_TL 0xa096
+#define mmPA_SC_VPORT_SCISSOR_2_TL 0xa098
+#define mmPA_SC_VPORT_SCISSOR_3_TL 0xa09a
+#define mmPA_SC_VPORT_SCISSOR_4_TL 0xa09c
+#define mmPA_SC_VPORT_SCISSOR_5_TL 0xa09e
+#define mmPA_SC_VPORT_SCISSOR_6_TL 0xa0a0
+#define mmPA_SC_VPORT_SCISSOR_7_TL 0xa0a2
+#define mmPA_SC_VPORT_SCISSOR_8_TL 0xa0a4
+#define mmPA_SC_VPORT_SCISSOR_9_TL 0xa0a6
+#define mmPA_SC_VPORT_SCISSOR_10_TL 0xa0a8
+#define mmPA_SC_VPORT_SCISSOR_11_TL 0xa0aa
+#define mmPA_SC_VPORT_SCISSOR_12_TL 0xa0ac
+#define mmPA_SC_VPORT_SCISSOR_13_TL 0xa0ae
+#define mmPA_SC_VPORT_SCISSOR_14_TL 0xa0b0
+#define mmPA_SC_VPORT_SCISSOR_15_TL 0xa0b2
+#define mmPA_SC_VPORT_SCISSOR_0_BR 0xa095
+#define mmPA_SC_VPORT_SCISSOR_1_BR 0xa097
+#define mmPA_SC_VPORT_SCISSOR_2_BR 0xa099
+#define mmPA_SC_VPORT_SCISSOR_3_BR 0xa09b
+#define mmPA_SC_VPORT_SCISSOR_4_BR 0xa09d
+#define mmPA_SC_VPORT_SCISSOR_5_BR 0xa09f
+#define mmPA_SC_VPORT_SCISSOR_6_BR 0xa0a1
+#define mmPA_SC_VPORT_SCISSOR_7_BR 0xa0a3
+#define mmPA_SC_VPORT_SCISSOR_8_BR 0xa0a5
+#define mmPA_SC_VPORT_SCISSOR_9_BR 0xa0a7
+#define mmPA_SC_VPORT_SCISSOR_10_BR 0xa0a9
+#define mmPA_SC_VPORT_SCISSOR_11_BR 0xa0ab
+#define mmPA_SC_VPORT_SCISSOR_12_BR 0xa0ad
+#define mmPA_SC_VPORT_SCISSOR_13_BR 0xa0af
+#define mmPA_SC_VPORT_SCISSOR_14_BR 0xa0b1
+#define mmPA_SC_VPORT_SCISSOR_15_BR 0xa0b3
+#define mmPA_SC_VPORT_ZMIN_0 0xa0b4
+#define mmPA_SC_VPORT_ZMIN_1 0xa0b6
+#define mmPA_SC_VPORT_ZMIN_2 0xa0b8
+#define mmPA_SC_VPORT_ZMIN_3 0xa0ba
+#define mmPA_SC_VPORT_ZMIN_4 0xa0bc
+#define mmPA_SC_VPORT_ZMIN_5 0xa0be
+#define mmPA_SC_VPORT_ZMIN_6 0xa0c0
+#define mmPA_SC_VPORT_ZMIN_7 0xa0c2
+#define mmPA_SC_VPORT_ZMIN_8 0xa0c4
+#define mmPA_SC_VPORT_ZMIN_9 0xa0c6
+#define mmPA_SC_VPORT_ZMIN_10 0xa0c8
+#define mmPA_SC_VPORT_ZMIN_11 0xa0ca
+#define mmPA_SC_VPORT_ZMIN_12 0xa0cc
+#define mmPA_SC_VPORT_ZMIN_13 0xa0ce
+#define mmPA_SC_VPORT_ZMIN_14 0xa0d0
+#define mmPA_SC_VPORT_ZMIN_15 0xa0d2
+#define mmPA_SC_VPORT_ZMAX_0 0xa0b5
+#define mmPA_SC_VPORT_ZMAX_1 0xa0b7
+#define mmPA_SC_VPORT_ZMAX_2 0xa0b9
+#define mmPA_SC_VPORT_ZMAX_3 0xa0bb
+#define mmPA_SC_VPORT_ZMAX_4 0xa0bd
+#define mmPA_SC_VPORT_ZMAX_5 0xa0bf
+#define mmPA_SC_VPORT_ZMAX_6 0xa0c1
+#define mmPA_SC_VPORT_ZMAX_7 0xa0c3
+#define mmPA_SC_VPORT_ZMAX_8 0xa0c5
+#define mmPA_SC_VPORT_ZMAX_9 0xa0c7
+#define mmPA_SC_VPORT_ZMAX_10 0xa0c9
+#define mmPA_SC_VPORT_ZMAX_11 0xa0cb
+#define mmPA_SC_VPORT_ZMAX_12 0xa0cd
+#define mmPA_SC_VPORT_ZMAX_13 0xa0cf
+#define mmPA_SC_VPORT_ZMAX_14 0xa0d1
+#define mmPA_SC_VPORT_ZMAX_15 0xa0d3
+#define mmPA_SC_ENHANCE 0x22fc
+#define mmPA_SC_FIFO_SIZE 0x22f3
+#define mmPA_SC_IF_FIFO_SIZE 0x22f5
+#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x22c9
+#define mmPA_SC_LINE_STIPPLE_STATE 0xc281
+#define mmPA_SC_SCREEN_EXTENT_MIN_0 0xc284
+#define mmPA_SC_SCREEN_EXTENT_MAX_0 0xc285
+#define mmPA_SC_SCREEN_EXTENT_MIN_1 0xc286
+#define mmPA_SC_SCREEN_EXTENT_MAX_1 0xc28b
+#define mmPA_SC_PERFCOUNTER0_SELECT 0xd940
+#define mmPA_SC_PERFCOUNTER0_SELECT1 0xd941
+#define mmPA_SC_PERFCOUNTER1_SELECT 0xd942
+#define mmPA_SC_PERFCOUNTER2_SELECT 0xd943
+#define mmPA_SC_PERFCOUNTER3_SELECT 0xd944
+#define mmPA_SC_PERFCOUNTER4_SELECT 0xd945
+#define mmPA_SC_PERFCOUNTER5_SELECT 0xd946
+#define mmPA_SC_PERFCOUNTER6_SELECT 0xd947
+#define mmPA_SC_PERFCOUNTER7_SELECT 0xd948
+#define mmPA_SC_PERFCOUNTER0_LO 0xd140
+#define mmPA_SC_PERFCOUNTER0_HI 0xd141
+#define mmPA_SC_PERFCOUNTER1_LO 0xd142
+#define mmPA_SC_PERFCOUNTER1_HI 0xd143
+#define mmPA_SC_PERFCOUNTER2_LO 0xd144
+#define mmPA_SC_PERFCOUNTER2_HI 0xd145
+#define mmPA_SC_PERFCOUNTER3_LO 0xd146
+#define mmPA_SC_PERFCOUNTER3_HI 0xd147
+#define mmPA_SC_PERFCOUNTER4_LO 0xd148
+#define mmPA_SC_PERFCOUNTER4_HI 0xd149
+#define mmPA_SC_PERFCOUNTER5_LO 0xd14a
+#define mmPA_SC_PERFCOUNTER5_HI 0xd14b
+#define mmPA_SC_PERFCOUNTER6_LO 0xd14c
+#define mmPA_SC_PERFCOUNTER6_HI 0xd14d
+#define mmPA_SC_PERFCOUNTER7_LO 0xd14e
+#define mmPA_SC_PERFCOUNTER7_HI 0xd14f
+#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0xc2a0
+#define mmPA_SC_P3D_TRAP_SCREEN_H 0xc2a1
+#define mmPA_SC_P3D_TRAP_SCREEN_V 0xc2a2
+#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0xc2a3
+#define mmPA_SC_P3D_TRAP_SCREEN_COUNT 0xc2a4
+#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0xc2a8
+#define mmPA_SC_HP3D_TRAP_SCREEN_H 0xc2a9
+#define mmPA_SC_HP3D_TRAP_SCREEN_V 0xc2aa
+#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0xc2ab
+#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0xc2ac
+#define mmPA_SC_TRAP_SCREEN_HV_EN 0xc2b0
+#define mmPA_SC_TRAP_SCREEN_H 0xc2b1
+#define mmPA_SC_TRAP_SCREEN_V 0xc2b2
+#define mmPA_SC_TRAP_SCREEN_OCCURRENCE 0xc2b3
+#define mmPA_SC_TRAP_SCREEN_COUNT 0xc2b4
+#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x22c0
+#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x22c1
+#define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x22c2
+#define mmPA_CL_CNTL_STATUS 0x2284
+#define mmPA_SU_CNTL_STATUS 0x2294
+#define mmPA_SC_FIFO_DEPTH_CNTL 0x2295
+#define mmCGTT_PA_CLK_CTRL 0xf088
+#define mmCGTT_SC_CLK_CTRL 0xf089
+#define mmPA_SU_DEBUG_CNTL 0x2280
+#define mmPA_SU_DEBUG_DATA 0x2281
+#define mmPA_SC_DEBUG_CNTL 0x22f6
+#define mmPA_SC_DEBUG_DATA 0x22f7
+#define ixCLIPPER_DEBUG_REG00 0x0
+#define ixCLIPPER_DEBUG_REG01 0x1
+#define ixCLIPPER_DEBUG_REG02 0x2
+#define ixCLIPPER_DEBUG_REG03 0x3
+#define ixCLIPPER_DEBUG_REG04 0x4
+#define ixCLIPPER_DEBUG_REG05 0x5
+#define ixCLIPPER_DEBUG_REG06 0x6
+#define ixCLIPPER_DEBUG_REG07 0x7
+#define ixCLIPPER_DEBUG_REG08 0x8
+#define ixCLIPPER_DEBUG_REG09 0x9
+#define ixCLIPPER_DEBUG_REG10 0xa
+#define ixCLIPPER_DEBUG_REG11 0xb
+#define ixCLIPPER_DEBUG_REG12 0xc
+#define ixCLIPPER_DEBUG_REG13 0xd
+#define ixCLIPPER_DEBUG_REG14 0xe
+#define ixCLIPPER_DEBUG_REG15 0xf
+#define ixCLIPPER_DEBUG_REG16 0x10
+#define ixCLIPPER_DEBUG_REG17 0x11
+#define ixCLIPPER_DEBUG_REG18 0x12
+#define ixCLIPPER_DEBUG_REG19 0x13
+#define ixSXIFCCG_DEBUG_REG0 0x14
+#define ixSXIFCCG_DEBUG_REG1 0x15
+#define ixSXIFCCG_DEBUG_REG2 0x16
+#define ixSXIFCCG_DEBUG_REG3 0x17
+#define ixSETUP_DEBUG_REG0 0x18
+#define ixSETUP_DEBUG_REG1 0x19
+#define ixSETUP_DEBUG_REG2 0x1a
+#define ixSETUP_DEBUG_REG3 0x1b
+#define ixSETUP_DEBUG_REG4 0x1c
+#define ixSETUP_DEBUG_REG5 0x1d
+#define ixPA_SC_DEBUG_REG0 0x0
+#define ixPA_SC_DEBUG_REG1 0x1
+#define mmCOMPUTE_DISPATCH_INITIATOR 0x2e00
+#define mmCOMPUTE_DIM_X 0x2e01
+#define mmCOMPUTE_DIM_Y 0x2e02
+#define mmCOMPUTE_DIM_Z 0x2e03
+#define mmCOMPUTE_START_X 0x2e04
+#define mmCOMPUTE_START_Y 0x2e05
+#define mmCOMPUTE_START_Z 0x2e06
+#define mmCOMPUTE_NUM_THREAD_X 0x2e07
+#define mmCOMPUTE_NUM_THREAD_Y 0x2e08
+#define mmCOMPUTE_NUM_THREAD_Z 0x2e09
+#define mmCOMPUTE_PIPELINESTAT_ENABLE 0x2e0a
+#define mmCOMPUTE_PERFCOUNT_ENABLE 0x2e0b
+#define mmCOMPUTE_PGM_LO 0x2e0c
+#define mmCOMPUTE_PGM_HI 0x2e0d
+#define mmCOMPUTE_TBA_LO 0x2e0e
+#define mmCOMPUTE_TBA_HI 0x2e0f
+#define mmCOMPUTE_TMA_LO 0x2e10
+#define mmCOMPUTE_TMA_HI 0x2e11
+#define mmCOMPUTE_PGM_RSRC1 0x2e12
+#define mmCOMPUTE_PGM_RSRC2 0x2e13
+#define mmCOMPUTE_VMID 0x2e14
+#define mmCOMPUTE_RESOURCE_LIMITS 0x2e15
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x2e16
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x2e17
+#define mmCOMPUTE_TMPRING_SIZE 0x2e18
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x2e19
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x2e1a
+#define mmCOMPUTE_RESTART_X 0x2e1b
+#define mmCOMPUTE_RESTART_Y 0x2e1c
+#define mmCOMPUTE_RESTART_Z 0x2e1d
+#define mmCOMPUTE_THREAD_TRACE_ENABLE 0x2e1e
+#define mmCOMPUTE_MISC_RESERVED 0x2e1f
+#define mmCOMPUTE_DISPATCH_ID 0x2e20
+#define mmCOMPUTE_THREADGROUP_ID 0x2e21
+#define mmCOMPUTE_RELAUNCH 0x2e22
+#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO 0x2e23
+#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI 0x2e24
+#define mmCOMPUTE_WAVE_RESTORE_CONTROL 0x2e25
+#define mmCOMPUTE_USER_DATA_0 0x2e40
+#define mmCOMPUTE_USER_DATA_1 0x2e41
+#define mmCOMPUTE_USER_DATA_2 0x2e42
+#define mmCOMPUTE_USER_DATA_3 0x2e43
+#define mmCOMPUTE_USER_DATA_4 0x2e44
+#define mmCOMPUTE_USER_DATA_5 0x2e45
+#define mmCOMPUTE_USER_DATA_6 0x2e46
+#define mmCOMPUTE_USER_DATA_7 0x2e47
+#define mmCOMPUTE_USER_DATA_8 0x2e48
+#define mmCOMPUTE_USER_DATA_9 0x2e49
+#define mmCOMPUTE_USER_DATA_10 0x2e4a
+#define mmCOMPUTE_USER_DATA_11 0x2e4b
+#define mmCOMPUTE_USER_DATA_12 0x2e4c
+#define mmCOMPUTE_USER_DATA_13 0x2e4d
+#define mmCOMPUTE_USER_DATA_14 0x2e4e
+#define mmCOMPUTE_USER_DATA_15 0x2e4f
+#define mmCOMPUTE_NOWHERE 0x2e7f
+#define mmCSPRIV_CONNECT 0x0
+#define mmCSPRIV_THREAD_TRACE_TG0 0x1e
+#define mmCSPRIV_THREAD_TRACE_TG1 0x1e
+#define mmCSPRIV_THREAD_TRACE_TG2 0x1e
+#define mmCSPRIV_THREAD_TRACE_TG3 0x1e
+#define mmCSPRIV_THREAD_TRACE_EVENT 0x1f
+#define mmRLC_CNTL 0xec00
+#define mmRLC_DEBUG_SELECT 0xec01
+#define mmRLC_DEBUG 0xec02
+#define mmRLC_MC_CNTL 0xec03
+#define mmRLC_STAT 0xec04
+#define mmRLC_SAFE_MODE 0xec05
+#define mmRLC_SOFT_RESET_GPU 0xec05
+#define mmRLC_MEM_SLP_CNTL 0xec06
+#define mmSMU_RLC_RESPONSE 0xec07
+#define mmRLC_RLCV_SAFE_MODE 0xec08
+#define mmRLC_SMU_SAFE_MODE 0xec09
+#define mmRLC_RLCV_COMMAND 0xec0a
+#define mmRLC_PERFMON_CLK_CNTL 0xdcbf
+#define mmRLC_PERFMON_CNTL 0xdcc0
+#define mmRLC_PERFCOUNTER0_SELECT 0xdcc1
+#define mmRLC_PERFCOUNTER1_SELECT 0xdcc2
+#define mmRLC_PERFCOUNTER0_LO 0xd480
+#define mmRLC_PERFCOUNTER1_LO 0xd482
+#define mmRLC_PERFCOUNTER0_HI 0xd481
+#define mmRLC_PERFCOUNTER1_HI 0xd483
+#define mmCGTT_RLC_CLK_CTRL 0xf0b8
+#define mmRLC_LB_CNTL 0xec19
+#define mmRLC_LB_CNTR_MAX 0xec12
+#define mmRLC_LB_CNTR_INIT 0xec1b
+#define mmRLC_LOAD_BALANCE_CNTR 0xec1c
+#define mmRLC_SAVE_AND_RESTORE_BASE 0xec1d
+#define mmRLC_JUMP_TABLE_RESTORE 0xec1e
+#define mmRLC_DRIVER_CPDMA_STATUS 0xec1e
+#define mmRLC_PG_DELAY_2 0xec1f
+#define mmRLC_GPM_DEBUG_SELECT 0xec20
+#define mmRLC_GPM_DEBUG 0xec21
+#define mmRLC_HYP_GPM_UCODE_ADDR 0xf83c
+#define mmRLC_GPM_UCODE_ADDR 0xf83c
+#define mmRLC_HYP_GPM_UCODE_DATA 0xf83d
+#define mmRLC_GPM_UCODE_DATA 0xf83d
+#define mmGPU_BIST_CONTROL 0xf835
+#define mmRLC_ROM_CNTL 0xf836
+#define mmRLC_GPU_CLOCK_COUNT_LSB 0xec24
+#define mmRLC_GPU_CLOCK_COUNT_MSB 0xec25
+#define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0xec26
+#define mmRLC_UCODE_CNTL 0xec27
+#define mmRLC_GPM_STAT 0xec40
+#define mmRLC_GPU_CLOCK_32_RES_SEL 0xec41
+#define mmRLC_GPU_CLOCK_32 0xec42
+#define mmRLC_PG_CNTL 0xec43
+#define mmRLC_GPM_THREAD_PRIORITY 0xec44
+#define mmRLC_GPM_THREAD_ENABLE 0xec45
+#define mmRLC_GPM_VMID_THREAD0 0xec46
+#define mmRLC_GPM_VMID_THREAD1 0xec47
+#define mmRLC_CGTT_MGCG_OVERRIDE 0xec48
+#define mmRLC_CGCG_CGLS_CTRL 0xec49
+#define mmRLC_CGCG_RAMP_CTRL 0xec4a
+#define mmRLC_DYN_PG_STATUS 0xec4b
+#define mmRLC_DYN_PG_REQUEST 0xec4c
+#define mmRLC_PG_DELAY 0xec4d
+#define mmRLC_CU_STATUS 0xec4e
+#define mmRLC_LB_INIT_CU_MASK 0xec4f
+#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0xec50
+#define mmRLC_LB_PARAMS 0xec51
+#define mmRLC_THREAD1_DELAY 0xec52
+#define mmRLC_PG_ALWAYS_ON_CU_MASK 0xec53
+#define mmRLC_MAX_PG_CU 0xec54
+#define mmRLC_AUTO_PG_CTRL 0xec55
+#define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0xec56
+#define mmRLC_SMU_PG_CTRL 0xec57
+#define mmRLC_SMU_PG_WAKE_UP_CTRL 0xec58
+#define mmRLC_SERDES_RD_MASTER_INDEX 0xec59
+#define mmRLC_SERDES_RD_DATA_0 0xec5a
+#define mmRLC_SERDES_RD_DATA_1 0xec5b
+#define mmRLC_SERDES_RD_DATA_2 0xec5c
+#define mmRLC_SERDES_WR_CU_MASTER_MASK 0xec5d
+#define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0xec5e
+#define mmRLC_SERDES_WR_CTRL 0xec5f
+#define mmRLC_SERDES_WR_DATA 0xec60
+#define mmRLC_SERDES_CU_MASTER_BUSY 0xec61
+#define mmRLC_SERDES_NONCU_MASTER_BUSY 0xec62
+#define mmRLC_GPM_GENERAL_0 0xec63
+#define mmRLC_GPM_GENERAL_1 0xec64
+#define mmRLC_GPM_GENERAL_2 0xec65
+#define mmRLC_GPM_GENERAL_3 0xec66
+#define mmRLC_GPM_GENERAL_4 0xec67
+#define mmRLC_GPM_GENERAL_5 0xec68
+#define mmRLC_GPM_GENERAL_6 0xec69
+#define mmRLC_GPM_GENERAL_7 0xec6a
+#define mmRLC_GPM_CU_PD_TIMEOUT 0xec6b
+#define mmRLC_GPM_SCRATCH_ADDR 0xec6c
+#define mmRLC_GPM_SCRATCH_DATA 0xec6d
+#define mmRLC_STATIC_PG_STATUS 0xec6e
+#define mmRLC_GPM_PERF_COUNT_0 0xec6f
+#define mmRLC_GPM_PERF_COUNT_1 0xec70
+#define mmRLC_GPR_REG1 0xec79
+#define mmRLC_GPR_REG2 0xec7a
+#define mmRLC_MGCG_CTRL 0xec1a
+#define mmRLC_GPM_THREAD_RESET 0xec28
+#define mmRLC_SPM_VMID 0xec71
+#define mmRLC_SPM_INT_CNTL 0xec72
+#define mmRLC_SPM_INT_STATUS 0xec73
+#define mmRLC_SPM_DEBUG_SELECT 0xec74
+#define mmRLC_SPM_DEBUG 0xec75
+#define mmRLC_GPM_LOG_ADDR 0xec76
+#define mmRLC_SMU_MESSAGE 0xec76
+#define mmRLC_GPM_LOG_SIZE 0xec77
+#define mmRLC_GPM_LOG_CONT 0xec7b
+#define mmRLC_PG_DELAY_3 0xec78
+#define mmRLC_GPM_INT_DISABLE_TH0 0xec7c
+#define mmRLC_GPM_INT_DISABLE_TH1 0xec7d
+#define mmRLC_GPM_INT_FORCE_TH0 0xec7e
+#define mmRLC_GPM_INT_FORCE_TH1 0xec7f
+#define mmRLC_SRM_CNTL 0xec80
+#define mmRLC_SRM_DEBUG_SELECT 0xec81
+#define mmRLC_SRM_DEBUG 0xec82
+#define mmRLC_SRM_ARAM_ADDR 0xec83
+#define mmRLC_SRM_ARAM_DATA 0xec84
+#define mmRLC_SRM_DRAM_ADDR 0xec85
+#define mmRLC_SRM_DRAM_DATA 0xec86
+#define mmRLC_SRM_GPM_COMMAND 0xec87
+#define mmRLC_SRM_GPM_COMMAND_STATUS 0xec88
+#define mmRLC_SRM_RLCV_COMMAND 0xec89
+#define mmRLC_SRM_RLCV_COMMAND_STATUS 0xec8a
+#define mmRLC_SRM_INDEX_CNTL_ADDR_0 0xec8b
+#define mmRLC_SRM_INDEX_CNTL_ADDR_1 0xec8c
+#define mmRLC_SRM_INDEX_CNTL_ADDR_2 0xec8d
+#define mmRLC_SRM_INDEX_CNTL_ADDR_3 0xec8e
+#define mmRLC_SRM_INDEX_CNTL_ADDR_4 0xec8f
+#define mmRLC_SRM_INDEX_CNTL_ADDR_5 0xec90
+#define mmRLC_SRM_INDEX_CNTL_ADDR_6 0xec91
+#define mmRLC_SRM_INDEX_CNTL_ADDR_7 0xec92
+#define mmRLC_SRM_INDEX_CNTL_DATA_0 0xec93
+#define mmRLC_SRM_INDEX_CNTL_DATA_1 0xec94
+#define mmRLC_SRM_INDEX_CNTL_DATA_2 0xec95
+#define mmRLC_SRM_INDEX_CNTL_DATA_3 0xec96
+#define mmRLC_SRM_INDEX_CNTL_DATA_4 0xec97
+#define mmRLC_SRM_INDEX_CNTL_DATA_5 0xec98
+#define mmRLC_SRM_INDEX_CNTL_DATA_6 0xec99
+#define mmRLC_SRM_INDEX_CNTL_DATA_7 0xec9a
+#define mmRLC_SRM_STAT 0xec9b
+#define mmRLC_SRM_GPM_ABORT 0xec9c
+#define mmRLC_CSIB_ADDR_LO 0xeca2
+#define mmRLC_CSIB_ADDR_HI 0xeca3
+#define mmRLC_CSIB_LENGTH 0xeca4
+#define mmRLC_CP_RESPONSE0 0xeca5
+#define mmRLC_CP_RESPONSE1 0xeca6
+#define mmRLC_CP_RESPONSE2 0xeca7
+#define mmRLC_CP_RESPONSE3 0xeca8
+#define mmRLC_SMU_COMMAND 0xeca9
+#define mmRLC_CP_SCHEDULERS 0xecaa
+#define mmRLC_SPM_PERFMON_CNTL 0xdc80
+#define mmRLC_SPM_PERFMON_RING_BASE_LO 0xdc81
+#define mmRLC_SPM_PERFMON_RING_BASE_HI 0xdc82
+#define mmRLC_SPM_PERFMON_RING_SIZE 0xdc83
+#define mmRLC_SPM_PERFMON_SEGMENT_SIZE 0xdc84
+#define mmRLC_SPM_SE_MUXSEL_ADDR 0xdc85
+#define mmRLC_SPM_SE_MUXSEL_DATA 0xdc86
+#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0xdc87
+#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0xdc88
+#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0xdc89
+#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0xdc8a
+#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0xdc8b
+#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0xdc8c
+#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0xdc8d
+#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0xdc8e
+#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0xdc90
+#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0xdc91
+#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0xdc92
+#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0xdc93
+#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0xdc94
+#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0xdc95
+#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0xdc96
+#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0xdc97
+#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0xdc98
+#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0xdc9a
+#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0xdc9b
+#define mmRLC_SPM_GLOBAL_MUXSEL_DATA 0xdc9c
+#define mmRLC_SPM_RING_RDPTR 0xdc9d
+#define mmRLC_SPM_SEGMENT_THRESHOLD 0xdc9e
+#define mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY 0xdc9f
+#define mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY 0xdca0
+#define mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY 0xdca1
+#define mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY 0xdca2
+#define mmRLC_GPU_IOV_VF_ENABLE 0xfb00
+#define mmRLC_GPU_IOV_CFG_REG1 0xfb01
+#define mmRLC_GPU_IOV_CFG_REG2 0xfb02
+#define mmRLC_GPU_IOV_CFG_REG6 0xfb06
+#define mmRLC_GPU_IOV_CFG_REG8 0xfb08
+#define mmRLC_GPU_IOV_CFG_REG9 0xfb21
+#define mmRLC_GPU_IOV_CFG_REG10 0xfb22
+#define mmRLC_GPU_IOV_CFG_REG11 0xfb23
+#define mmRLC_GPU_IOV_CFG_REG12 0xfb24
+#define mmRLC_GPU_IOV_CFG_REG13 0xfb25
+#define mmRLC_GPU_IOV_CFG_REG14 0xfb26
+#define mmRLC_GPU_IOV_CFG_REG15 0xfb27
+#define mmRLC_GPU_IOV_ACTIVE_FCN_ID 0xfb40
+#define mmRLC_GPM_VMID_THREAD2 0xfb41
+#define mmRLC_GPU_IOV_UCODE_ADDR 0xfb42
+#define mmRLC_GPU_IOV_UCODE_DATA 0xfb43
+#define mmRLC_GPU_IOV_SCRATCH_ADDR 0xfb44
+#define mmRLC_GPU_IOV_SCRATCH_DATA 0xfb45
+#define mmRLC_GPU_IOV_F32_CNTL 0xfb46
+#define mmRLC_GPU_IOV_F32_RESET 0xfb47
+#define mmRLC_GPU_IOV_SDMA0_STATUS 0xfb48
+#define mmRLC_GPU_IOV_SDMA1_STATUS 0xfb49
+#define mmRLC_GPU_IOV_SMU_RESPONSE 0xfb4a
+#define mmRLC_GPU_IOV_VIRT_RESET_REQ 0xfb4c
+#define mmRLC_GPU_IOV_RLC_RESPONSE 0xfb4d
+#define mmRLC_GPU_IOV_INT_DISABLE 0xfb4e
+#define mmRLC_GPU_IOV_INT_FORCE 0xfb4f
+#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS 0xfb50
+#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS 0xfb51
+#define mmRLC_GPU_IOV_SCH_0 0xfb52
+#define mmRLC_GPU_IOV_SCH_1 0xfb53
+#define mmRLC_GPU_IOV_SCH_2 0xfb54
+#define mmRLC_GPU_IOV_SCH_3 0xfb55
+#define mmRLC_GPU_IOV_SCH_INT 0xfb56
+#define mmSPI_PS_INPUT_CNTL_0 0xa191
+#define mmSPI_PS_INPUT_CNTL_1 0xa192
+#define mmSPI_PS_INPUT_CNTL_2 0xa193
+#define mmSPI_PS_INPUT_CNTL_3 0xa194
+#define mmSPI_PS_INPUT_CNTL_4 0xa195
+#define mmSPI_PS_INPUT_CNTL_5 0xa196
+#define mmSPI_PS_INPUT_CNTL_6 0xa197
+#define mmSPI_PS_INPUT_CNTL_7 0xa198
+#define mmSPI_PS_INPUT_CNTL_8 0xa199
+#define mmSPI_PS_INPUT_CNTL_9 0xa19a
+#define mmSPI_PS_INPUT_CNTL_10 0xa19b
+#define mmSPI_PS_INPUT_CNTL_11 0xa19c
+#define mmSPI_PS_INPUT_CNTL_12 0xa19d
+#define mmSPI_PS_INPUT_CNTL_13 0xa19e
+#define mmSPI_PS_INPUT_CNTL_14 0xa19f
+#define mmSPI_PS_INPUT_CNTL_15 0xa1a0
+#define mmSPI_PS_INPUT_CNTL_16 0xa1a1
+#define mmSPI_PS_INPUT_CNTL_17 0xa1a2
+#define mmSPI_PS_INPUT_CNTL_18 0xa1a3
+#define mmSPI_PS_INPUT_CNTL_19 0xa1a4
+#define mmSPI_PS_INPUT_CNTL_20 0xa1a5
+#define mmSPI_PS_INPUT_CNTL_21 0xa1a6
+#define mmSPI_PS_INPUT_CNTL_22 0xa1a7
+#define mmSPI_PS_INPUT_CNTL_23 0xa1a8
+#define mmSPI_PS_INPUT_CNTL_24 0xa1a9
+#define mmSPI_PS_INPUT_CNTL_25 0xa1aa
+#define mmSPI_PS_INPUT_CNTL_26 0xa1ab
+#define mmSPI_PS_INPUT_CNTL_27 0xa1ac
+#define mmSPI_PS_INPUT_CNTL_28 0xa1ad
+#define mmSPI_PS_INPUT_CNTL_29 0xa1ae
+#define mmSPI_PS_INPUT_CNTL_30 0xa1af
+#define mmSPI_PS_INPUT_CNTL_31 0xa1b0
+#define mmSPI_VS_OUT_CONFIG 0xa1b1
+#define mmSPI_PS_INPUT_ENA 0xa1b3
+#define mmSPI_PS_INPUT_ADDR 0xa1b4
+#define mmSPI_INTERP_CONTROL_0 0xa1b5
+#define mmSPI_PS_IN_CONTROL 0xa1b6
+#define mmSPI_BARYC_CNTL 0xa1b8
+#define mmSPI_TMPRING_SIZE 0xa1ba
+#define mmSPI_SHADER_POS_FORMAT 0xa1c3
+#define mmSPI_SHADER_Z_FORMAT 0xa1c4
+#define mmSPI_SHADER_COL_FORMAT 0xa1c5
+#define mmSPI_ARB_PRIORITY 0x31c0
+#define mmSPI_ARB_CYCLES_0 0x31c1
+#define mmSPI_ARB_CYCLES_1 0x31c2
+#define mmSPI_CDBG_SYS_GFX 0x31c3
+#define mmSPI_CDBG_SYS_HP3D 0x31c4
+#define mmSPI_CDBG_SYS_CS0 0x31c5
+#define mmSPI_CDBG_SYS_CS1 0x31c6
+#define mmSPI_WCL_PIPE_PERCENT_GFX 0x31c7
+#define mmSPI_WCL_PIPE_PERCENT_HP3D 0x31c8
+#define mmSPI_WCL_PIPE_PERCENT_CS0 0x31c9
+#define mmSPI_WCL_PIPE_PERCENT_CS1 0x31ca
+#define mmSPI_WCL_PIPE_PERCENT_CS2 0x31cb
+#define mmSPI_WCL_PIPE_PERCENT_CS3 0x31cc
+#define mmSPI_WCL_PIPE_PERCENT_CS4 0x31cd
+#define mmSPI_WCL_PIPE_PERCENT_CS5 0x31ce
+#define mmSPI_WCL_PIPE_PERCENT_CS6 0x31cf
+#define mmSPI_WCL_PIPE_PERCENT_CS7 0x31d0
+#define mmSPI_GDBG_WAVE_CNTL 0x31d1
+#define mmSPI_GDBG_TRAP_CONFIG 0x31d2
+#define mmSPI_GDBG_TRAP_MASK 0x31d3
+#define mmSPI_GDBG_TBA_LO 0x31d4
+#define mmSPI_GDBG_TBA_HI 0x31d5
+#define mmSPI_GDBG_TMA_LO 0x31d6
+#define mmSPI_GDBG_TMA_HI 0x31d7
+#define mmSPI_GDBG_TRAP_DATA0 0x31d8
+#define mmSPI_GDBG_TRAP_DATA1 0x31d9
+#define mmSPI_RESET_DEBUG 0x31da
+#define mmSPI_COMPUTE_QUEUE_RESET 0x31db
+#define mmSPI_RESOURCE_RESERVE_CU_0 0x31dc
+#define mmSPI_RESOURCE_RESERVE_CU_1 0x31dd
+#define mmSPI_RESOURCE_RESERVE_CU_2 0x31de
+#define mmSPI_RESOURCE_RESERVE_CU_3 0x31df
+#define mmSPI_RESOURCE_RESERVE_CU_4 0x31e0
+#define mmSPI_RESOURCE_RESERVE_CU_5 0x31e1
+#define mmSPI_RESOURCE_RESERVE_CU_6 0x31e2
+#define mmSPI_RESOURCE_RESERVE_CU_7 0x31e3
+#define mmSPI_RESOURCE_RESERVE_CU_8 0x31e4
+#define mmSPI_RESOURCE_RESERVE_CU_9 0x31e5
+#define mmSPI_RESOURCE_RESERVE_CU_10 0x31f0
+#define mmSPI_RESOURCE_RESERVE_CU_11 0x31f1
+#define mmSPI_RESOURCE_RESERVE_CU_12 0x31f4
+#define mmSPI_RESOURCE_RESERVE_CU_13 0x31f5
+#define mmSPI_RESOURCE_RESERVE_CU_14 0x31f6
+#define mmSPI_RESOURCE_RESERVE_CU_15 0x31f7
+#define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x31e6
+#define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x31e7
+#define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x31e8
+#define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x31e9
+#define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x31ea
+#define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x31eb
+#define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x31ec
+#define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x31ed
+#define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x31ee
+#define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x31ef
+#define mmSPI_RESOURCE_RESERVE_EN_CU_10 0x31f2
+#define mmSPI_RESOURCE_RESERVE_EN_CU_11 0x31f3
+#define mmSPI_RESOURCE_RESERVE_EN_CU_12 0x31f8
+#define mmSPI_RESOURCE_RESERVE_EN_CU_13 0x31f9
+#define mmSPI_RESOURCE_RESERVE_EN_CU_14 0x31fa
+#define mmSPI_RESOURCE_RESERVE_EN_CU_15 0x31fb
+#define mmSPI_COMPUTE_WF_CTX_SAVE 0x31fc
+#define mmSPI_PS_MAX_WAVE_ID 0x243a
+#define mmSPI_START_PHASE 0x243b
+#define mmSPI_GFX_CNTL 0x243c
+#define mmSPI_CONFIG_CNTL 0x2440
+#define mmSPI_DEBUG_CNTL 0x2441
+#define mmSPI_DEBUG_READ 0x2442
+#define mmSPI_DSM_CNTL 0x2443
+#define mmSPI_EDC_CNT 0x2444
+#define mmSPI_PERFCOUNTER0_SELECT 0xd980
+#define mmSPI_PERFCOUNTER1_SELECT 0xd981
+#define mmSPI_PERFCOUNTER2_SELECT 0xd982
+#define mmSPI_PERFCOUNTER3_SELECT 0xd983
+#define mmSPI_PERFCOUNTER0_SELECT1 0xd984
+#define mmSPI_PERFCOUNTER1_SELECT1 0xd985
+#define mmSPI_PERFCOUNTER2_SELECT1 0xd986
+#define mmSPI_PERFCOUNTER3_SELECT1 0xd987
+#define mmSPI_PERFCOUNTER4_SELECT 0xd988
+#define mmSPI_PERFCOUNTER5_SELECT 0xd989
+#define mmSPI_PERFCOUNTER_BINS 0xd98a
+#define mmSPI_PERFCOUNTER0_HI 0xd180
+#define mmSPI_PERFCOUNTER0_LO 0xd181
+#define mmSPI_PERFCOUNTER1_HI 0xd182
+#define mmSPI_PERFCOUNTER1_LO 0xd183
+#define mmSPI_PERFCOUNTER2_HI 0xd184
+#define mmSPI_PERFCOUNTER2_LO 0xd185
+#define mmSPI_PERFCOUNTER3_HI 0xd186
+#define mmSPI_PERFCOUNTER3_LO 0xd187
+#define mmSPI_PERFCOUNTER4_HI 0xd188
+#define mmSPI_PERFCOUNTER4_LO 0xd189
+#define mmSPI_PERFCOUNTER5_HI 0xd18a
+#define mmSPI_PERFCOUNTER5_LO 0xd18b
+#define mmSPI_CONFIG_CNTL_1 0x244f
+#define mmSPI_DEBUG_BUSY 0x2450
+#define mmSPI_CONFIG_CNTL_2 0x2451
+#define mmCGTS_SM_CTRL_REG 0xf000
+#define mmCGTS_RD_CTRL_REG 0xf001
+#define mmCGTS_RD_REG 0xf002
+#define mmCGTS_TCC_DISABLE 0xf003
+#define mmCGTS_USER_TCC_DISABLE 0xf004
+#define mmCGTS_CU0_SP0_CTRL_REG 0xf008
+#define mmCGTS_CU0_LDS_SQ_CTRL_REG 0xf009
+#define mmCGTS_CU0_TA_SQC_CTRL_REG 0xf00a
+#define mmCGTS_CU0_SP1_CTRL_REG 0xf00b
+#define mmCGTS_CU0_TD_TCP_CTRL_REG 0xf00c
+#define mmCGTS_CU1_SP0_CTRL_REG 0xf00d
+#define mmCGTS_CU1_LDS_SQ_CTRL_REG 0xf00e
+#define mmCGTS_CU1_TA_CTRL_REG 0xf00f
+#define mmCGTS_CU1_SP1_CTRL_REG 0xf010
+#define mmCGTS_CU1_TD_TCP_CTRL_REG 0xf011
+#define mmCGTS_CU2_SP0_CTRL_REG 0xf012
+#define mmCGTS_CU2_LDS_SQ_CTRL_REG 0xf013
+#define mmCGTS_CU2_TA_CTRL_REG 0xf014
+#define mmCGTS_CU2_SP1_CTRL_REG 0xf015
+#define mmCGTS_CU2_TD_TCP_CTRL_REG 0xf016
+#define mmCGTS_CU3_SP0_CTRL_REG 0xf017
+#define mmCGTS_CU3_LDS_SQ_CTRL_REG 0xf018
+#define mmCGTS_CU3_TA_CTRL_REG 0xf019
+#define mmCGTS_CU3_SP1_CTRL_REG 0xf01a
+#define mmCGTS_CU3_TD_TCP_CTRL_REG 0xf01b
+#define mmCGTS_CU4_SP0_CTRL_REG 0xf01c
+#define mmCGTS_CU4_LDS_SQ_CTRL_REG 0xf01d
+#define mmCGTS_CU4_TA_SQC_CTRL_REG 0xf01e
+#define mmCGTS_CU4_SP1_CTRL_REG 0xf01f
+#define mmCGTS_CU4_TD_TCP_CTRL_REG 0xf020
+#define mmCGTS_CU5_SP0_CTRL_REG 0xf021
+#define mmCGTS_CU5_LDS_SQ_CTRL_REG 0xf022
+#define mmCGTS_CU5_TA_CTRL_REG 0xf023
+#define mmCGTS_CU5_SP1_CTRL_REG 0xf024
+#define mmCGTS_CU5_TD_TCP_CTRL_REG 0xf025
+#define mmCGTS_CU6_SP0_CTRL_REG 0xf026
+#define mmCGTS_CU6_LDS_SQ_CTRL_REG 0xf027
+#define mmCGTS_CU6_TA_CTRL_REG 0xf028
+#define mmCGTS_CU6_SP1_CTRL_REG 0xf029
+#define mmCGTS_CU6_TD_TCP_CTRL_REG 0xf02a
+#define mmCGTS_CU7_SP0_CTRL_REG 0xf02b
+#define mmCGTS_CU7_LDS_SQ_CTRL_REG 0xf02c
+#define mmCGTS_CU7_TA_CTRL_REG 0xf02d
+#define mmCGTS_CU7_SP1_CTRL_REG 0xf02e
+#define mmCGTS_CU7_TD_TCP_CTRL_REG 0xf02f
+#define mmCGTS_CU8_SP0_CTRL_REG 0xf030
+#define mmCGTS_CU8_LDS_SQ_CTRL_REG 0xf031
+#define mmCGTS_CU8_TA_SQC_CTRL_REG 0xf032
+#define mmCGTS_CU8_SP1_CTRL_REG 0xf033
+#define mmCGTS_CU8_TD_TCP_CTRL_REG 0xf034
+#define mmCGTS_CU9_SP0_CTRL_REG 0xf035
+#define mmCGTS_CU9_LDS_SQ_CTRL_REG 0xf036
+#define mmCGTS_CU9_TA_CTRL_REG 0xf037
+#define mmCGTS_CU9_SP1_CTRL_REG 0xf038
+#define mmCGTS_CU9_TD_TCP_CTRL_REG 0xf039
+#define mmCGTS_CU10_SP0_CTRL_REG 0xf03a
+#define mmCGTS_CU10_LDS_SQ_CTRL_REG 0xf03b
+#define mmCGTS_CU10_TA_CTRL_REG 0xf03c
+#define mmCGTS_CU10_SP1_CTRL_REG 0xf03d
+#define mmCGTS_CU10_TD_TCP_CTRL_REG 0xf03e
+#define mmCGTS_CU11_SP0_CTRL_REG 0xf03f
+#define mmCGTS_CU11_LDS_SQ_CTRL_REG 0xf040
+#define mmCGTS_CU11_TA_CTRL_REG 0xf041
+#define mmCGTS_CU11_SP1_CTRL_REG 0xf042
+#define mmCGTS_CU11_TD_TCP_CTRL_REG 0xf043
+#define mmCGTS_CU12_SP0_CTRL_REG 0xf044
+#define mmCGTS_CU12_LDS_SQ_CTRL_REG 0xf045
+#define mmCGTS_CU12_TA_SQC_CTRL_REG 0xf046
+#define mmCGTS_CU12_SP1_CTRL_REG 0xf047
+#define mmCGTS_CU12_TD_TCP_CTRL_REG 0xf048
+#define mmCGTS_CU13_SP0_CTRL_REG 0xf049
+#define mmCGTS_CU13_LDS_SQ_CTRL_REG 0xf04a
+#define mmCGTS_CU13_TA_CTRL_REG 0xf04b
+#define mmCGTS_CU13_SP1_CTRL_REG 0xf04c
+#define mmCGTS_CU13_TD_TCP_CTRL_REG 0xf04d
+#define mmCGTS_CU14_SP0_CTRL_REG 0xf04e
+#define mmCGTS_CU14_LDS_SQ_CTRL_REG 0xf04f
+#define mmCGTS_CU14_TA_CTRL_REG 0xf050
+#define mmCGTS_CU14_SP1_CTRL_REG 0xf051
+#define mmCGTS_CU14_TD_TCP_CTRL_REG 0xf052
+#define mmCGTS_CU15_SP0_CTRL_REG 0xf053
+#define mmCGTS_CU15_LDS_SQ_CTRL_REG 0xf054
+#define mmCGTS_CU15_TA_CTRL_REG 0xf055
+#define mmCGTS_CU15_SP1_CTRL_REG 0xf056
+#define mmCGTS_CU15_TD_TCP_CTRL_REG 0xf057
+#define mmCGTT_SPI_CLK_CTRL 0xf080
+#define mmCGTT_PC_CLK_CTRL 0xf081
+#define mmCGTT_BCI_CLK_CTRL 0xf082
+#define mmSPI_WF_LIFETIME_CNTL 0x24aa
+#define mmSPI_WF_LIFETIME_LIMIT_0 0x24ab
+#define mmSPI_WF_LIFETIME_LIMIT_1 0x24ac
+#define mmSPI_WF_LIFETIME_LIMIT_2 0x24ad
+#define mmSPI_WF_LIFETIME_LIMIT_3 0x24ae
+#define mmSPI_WF_LIFETIME_LIMIT_4 0x24af
+#define mmSPI_WF_LIFETIME_LIMIT_5 0x24b0
+#define mmSPI_WF_LIFETIME_LIMIT_6 0x24b1
+#define mmSPI_WF_LIFETIME_LIMIT_7 0x24b2
+#define mmSPI_WF_LIFETIME_LIMIT_8 0x24b3
+#define mmSPI_WF_LIFETIME_LIMIT_9 0x24b4
+#define mmSPI_WF_LIFETIME_STATUS_0 0x24b5
+#define mmSPI_WF_LIFETIME_STATUS_1 0x24b6
+#define mmSPI_WF_LIFETIME_STATUS_2 0x24b7
+#define mmSPI_WF_LIFETIME_STATUS_3 0x24b8
+#define mmSPI_WF_LIFETIME_STATUS_4 0x24b9
+#define mmSPI_WF_LIFETIME_STATUS_5 0x24ba
+#define mmSPI_WF_LIFETIME_STATUS_6 0x24bb
+#define mmSPI_WF_LIFETIME_STATUS_7 0x24bc
+#define mmSPI_WF_LIFETIME_STATUS_8 0x24bd
+#define mmSPI_WF_LIFETIME_STATUS_9 0x24be
+#define mmSPI_WF_LIFETIME_STATUS_10 0x24bf
+#define mmSPI_WF_LIFETIME_STATUS_11 0x24c0
+#define mmSPI_WF_LIFETIME_STATUS_12 0x24c1
+#define mmSPI_WF_LIFETIME_STATUS_13 0x24c2
+#define mmSPI_WF_LIFETIME_STATUS_14 0x24c3
+#define mmSPI_WF_LIFETIME_STATUS_15 0x24c4
+#define mmSPI_WF_LIFETIME_STATUS_16 0x24c5
+#define mmSPI_WF_LIFETIME_STATUS_17 0x24c6
+#define mmSPI_WF_LIFETIME_STATUS_18 0x24c7
+#define mmSPI_WF_LIFETIME_STATUS_19 0x24c8
+#define mmSPI_WF_LIFETIME_STATUS_20 0x24c9
+#define mmSPI_WF_LIFETIME_DEBUG 0x24ca
+#define mmSPI_SLAVE_DEBUG_BUSY 0x24d3
+#define mmSPI_LB_CTR_CTRL 0x24d4
+#define mmSPI_LB_CU_MASK 0x24d5
+#define mmSPI_LB_DATA_REG 0x24d6
+#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x24d7
+#define mmSPI_GDS_CREDITS 0x24d8
+#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x24d9
+#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x24da
+#define mmSPI_CSQ_WF_ACTIVE_STATUS 0x24db
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x24dc
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x24dd
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x24de
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x24df
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0x24e0
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0x24e1
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0x24e2
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0x24e3
+#define mmBCI_DEBUG_READ 0x24eb
+#define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x24ec
+#define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x24ed
+#define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x24ee
+#define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x24ef
+#define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x24f0
+#define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x24f1
+#define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x24f2
+#define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x24f3
+#define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x24f4
+#define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x24f5
+#define mmSPI_SHADER_TBA_LO_PS 0x2c00
+#define mmSPI_SHADER_TBA_HI_PS 0x2c01
+#define mmSPI_SHADER_TMA_LO_PS 0x2c02
+#define mmSPI_SHADER_TMA_HI_PS 0x2c03
+#define mmSPI_SHADER_PGM_LO_PS 0x2c08
+#define mmSPI_SHADER_PGM_HI_PS 0x2c09
+#define mmSPI_SHADER_PGM_RSRC1_PS 0x2c0a
+#define mmSPI_SHADER_PGM_RSRC2_PS 0x2c0b
+#define mmSPI_SHADER_PGM_RSRC3_PS 0x2c07
+#define mmSPI_SHADER_USER_DATA_PS_0 0x2c0c
+#define mmSPI_SHADER_USER_DATA_PS_1 0x2c0d
+#define mmSPI_SHADER_USER_DATA_PS_2 0x2c0e
+#define mmSPI_SHADER_USER_DATA_PS_3 0x2c0f
+#define mmSPI_SHADER_USER_DATA_PS_4 0x2c10
+#define mmSPI_SHADER_USER_DATA_PS_5 0x2c11
+#define mmSPI_SHADER_USER_DATA_PS_6 0x2c12
+#define mmSPI_SHADER_USER_DATA_PS_7 0x2c13
+#define mmSPI_SHADER_USER_DATA_PS_8 0x2c14
+#define mmSPI_SHADER_USER_DATA_PS_9 0x2c15
+#define mmSPI_SHADER_USER_DATA_PS_10 0x2c16
+#define mmSPI_SHADER_USER_DATA_PS_11 0x2c17
+#define mmSPI_SHADER_USER_DATA_PS_12 0x2c18
+#define mmSPI_SHADER_USER_DATA_PS_13 0x2c19
+#define mmSPI_SHADER_USER_DATA_PS_14 0x2c1a
+#define mmSPI_SHADER_USER_DATA_PS_15 0x2c1b
+#define mmSPI_SHADER_TBA_LO_VS 0x2c40
+#define mmSPI_SHADER_TBA_HI_VS 0x2c41
+#define mmSPI_SHADER_TMA_LO_VS 0x2c42
+#define mmSPI_SHADER_TMA_HI_VS 0x2c43
+#define mmSPI_SHADER_PGM_LO_VS 0x2c48
+#define mmSPI_SHADER_PGM_HI_VS 0x2c49
+#define mmSPI_SHADER_PGM_RSRC1_VS 0x2c4a
+#define mmSPI_SHADER_PGM_RSRC2_VS 0x2c4b
+#define mmSPI_SHADER_PGM_RSRC3_VS 0x2c46
+#define mmSPI_SHADER_LATE_ALLOC_VS 0x2c47
+#define mmSPI_SHADER_USER_DATA_VS_0 0x2c4c
+#define mmSPI_SHADER_USER_DATA_VS_1 0x2c4d
+#define mmSPI_SHADER_USER_DATA_VS_2 0x2c4e
+#define mmSPI_SHADER_USER_DATA_VS_3 0x2c4f
+#define mmSPI_SHADER_USER_DATA_VS_4 0x2c50
+#define mmSPI_SHADER_USER_DATA_VS_5 0x2c51
+#define mmSPI_SHADER_USER_DATA_VS_6 0x2c52
+#define mmSPI_SHADER_USER_DATA_VS_7 0x2c53
+#define mmSPI_SHADER_USER_DATA_VS_8 0x2c54
+#define mmSPI_SHADER_USER_DATA_VS_9 0x2c55
+#define mmSPI_SHADER_USER_DATA_VS_10 0x2c56
+#define mmSPI_SHADER_USER_DATA_VS_11 0x2c57
+#define mmSPI_SHADER_USER_DATA_VS_12 0x2c58
+#define mmSPI_SHADER_USER_DATA_VS_13 0x2c59
+#define mmSPI_SHADER_USER_DATA_VS_14 0x2c5a
+#define mmSPI_SHADER_USER_DATA_VS_15 0x2c5b
+#define mmSPI_SHADER_PGM_RSRC2_ES_VS 0x2c7c
+#define mmSPI_SHADER_PGM_RSRC2_LS_VS 0x2c7d
+#define mmSPI_SHADER_TBA_LO_GS 0x2c80
+#define mmSPI_SHADER_TBA_HI_GS 0x2c81
+#define mmSPI_SHADER_TMA_LO_GS 0x2c82
+#define mmSPI_SHADER_TMA_HI_GS 0x2c83
+#define mmSPI_SHADER_PGM_LO_GS 0x2c88
+#define mmSPI_SHADER_PGM_HI_GS 0x2c89
+#define mmSPI_SHADER_PGM_RSRC1_GS 0x2c8a
+#define mmSPI_SHADER_PGM_RSRC2_GS 0x2c8b
+#define mmSPI_SHADER_PGM_RSRC3_GS 0x2c87
+#define mmSPI_SHADER_USER_DATA_GS_0 0x2c8c
+#define mmSPI_SHADER_USER_DATA_GS_1 0x2c8d
+#define mmSPI_SHADER_USER_DATA_GS_2 0x2c8e
+#define mmSPI_SHADER_USER_DATA_GS_3 0x2c8f
+#define mmSPI_SHADER_USER_DATA_GS_4 0x2c90
+#define mmSPI_SHADER_USER_DATA_GS_5 0x2c91
+#define mmSPI_SHADER_USER_DATA_GS_6 0x2c92
+#define mmSPI_SHADER_USER_DATA_GS_7 0x2c93
+#define mmSPI_SHADER_USER_DATA_GS_8 0x2c94
+#define mmSPI_SHADER_USER_DATA_GS_9 0x2c95
+#define mmSPI_SHADER_USER_DATA_GS_10 0x2c96
+#define mmSPI_SHADER_USER_DATA_GS_11 0x2c97
+#define mmSPI_SHADER_USER_DATA_GS_12 0x2c98
+#define mmSPI_SHADER_USER_DATA_GS_13 0x2c99
+#define mmSPI_SHADER_USER_DATA_GS_14 0x2c9a
+#define mmSPI_SHADER_USER_DATA_GS_15 0x2c9b
+#define mmSPI_SHADER_PGM_RSRC2_ES_GS 0x2cbc
+#define mmSPI_SHADER_TBA_LO_ES 0x2cc0
+#define mmSPI_SHADER_TBA_HI_ES 0x2cc1
+#define mmSPI_SHADER_TMA_LO_ES 0x2cc2
+#define mmSPI_SHADER_TMA_HI_ES 0x2cc3
+#define mmSPI_SHADER_PGM_LO_ES 0x2cc8
+#define mmSPI_SHADER_PGM_HI_ES 0x2cc9
+#define mmSPI_SHADER_PGM_RSRC1_ES 0x2cca
+#define mmSPI_SHADER_PGM_RSRC2_ES 0x2ccb
+#define mmSPI_SHADER_PGM_RSRC3_ES 0x2cc7
+#define mmSPI_SHADER_USER_DATA_ES_0 0x2ccc
+#define mmSPI_SHADER_USER_DATA_ES_1 0x2ccd
+#define mmSPI_SHADER_USER_DATA_ES_2 0x2cce
+#define mmSPI_SHADER_USER_DATA_ES_3 0x2ccf
+#define mmSPI_SHADER_USER_DATA_ES_4 0x2cd0
+#define mmSPI_SHADER_USER_DATA_ES_5 0x2cd1
+#define mmSPI_SHADER_USER_DATA_ES_6 0x2cd2
+#define mmSPI_SHADER_USER_DATA_ES_7 0x2cd3
+#define mmSPI_SHADER_USER_DATA_ES_8 0x2cd4
+#define mmSPI_SHADER_USER_DATA_ES_9 0x2cd5
+#define mmSPI_SHADER_USER_DATA_ES_10 0x2cd6
+#define mmSPI_SHADER_USER_DATA_ES_11 0x2cd7
+#define mmSPI_SHADER_USER_DATA_ES_12 0x2cd8
+#define mmSPI_SHADER_USER_DATA_ES_13 0x2cd9
+#define mmSPI_SHADER_USER_DATA_ES_14 0x2cda
+#define mmSPI_SHADER_USER_DATA_ES_15 0x2cdb
+#define mmSPI_SHADER_PGM_RSRC2_LS_ES 0x2cfd
+#define mmSPI_SHADER_TBA_LO_HS 0x2d00
+#define mmSPI_SHADER_TBA_HI_HS 0x2d01
+#define mmSPI_SHADER_TMA_LO_HS 0x2d02
+#define mmSPI_SHADER_TMA_HI_HS 0x2d03
+#define mmSPI_SHADER_PGM_LO_HS 0x2d08
+#define mmSPI_SHADER_PGM_HI_HS 0x2d09
+#define mmSPI_SHADER_PGM_RSRC1_HS 0x2d0a
+#define mmSPI_SHADER_PGM_RSRC2_HS 0x2d0b
+#define mmSPI_SHADER_PGM_RSRC3_HS 0x2d07
+#define mmSPI_SHADER_USER_DATA_HS_0 0x2d0c
+#define mmSPI_SHADER_USER_DATA_HS_1 0x2d0d
+#define mmSPI_SHADER_USER_DATA_HS_2 0x2d0e
+#define mmSPI_SHADER_USER_DATA_HS_3 0x2d0f
+#define mmSPI_SHADER_USER_DATA_HS_4 0x2d10
+#define mmSPI_SHADER_USER_DATA_HS_5 0x2d11
+#define mmSPI_SHADER_USER_DATA_HS_6 0x2d12
+#define mmSPI_SHADER_USER_DATA_HS_7 0x2d13
+#define mmSPI_SHADER_USER_DATA_HS_8 0x2d14
+#define mmSPI_SHADER_USER_DATA_HS_9 0x2d15
+#define mmSPI_SHADER_USER_DATA_HS_10 0x2d16
+#define mmSPI_SHADER_USER_DATA_HS_11 0x2d17
+#define mmSPI_SHADER_USER_DATA_HS_12 0x2d18
+#define mmSPI_SHADER_USER_DATA_HS_13 0x2d19
+#define mmSPI_SHADER_USER_DATA_HS_14 0x2d1a
+#define mmSPI_SHADER_USER_DATA_HS_15 0x2d1b
+#define mmSPI_SHADER_PGM_RSRC2_LS_HS 0x2d3d
+#define mmSPI_SHADER_TBA_LO_LS 0x2d40
+#define mmSPI_SHADER_TBA_HI_LS 0x2d41
+#define mmSPI_SHADER_TMA_LO_LS 0x2d42
+#define mmSPI_SHADER_TMA_HI_LS 0x2d43
+#define mmSPI_SHADER_PGM_LO_LS 0x2d48
+#define mmSPI_SHADER_PGM_HI_LS 0x2d49
+#define mmSPI_SHADER_PGM_RSRC1_LS 0x2d4a
+#define mmSPI_SHADER_PGM_RSRC2_LS 0x2d4b
+#define mmSPI_SHADER_PGM_RSRC3_LS 0x2d47
+#define mmSPI_SHADER_USER_DATA_LS_0 0x2d4c
+#define mmSPI_SHADER_USER_DATA_LS_1 0x2d4d
+#define mmSPI_SHADER_USER_DATA_LS_2 0x2d4e
+#define mmSPI_SHADER_USER_DATA_LS_3 0x2d4f
+#define mmSPI_SHADER_USER_DATA_LS_4 0x2d50
+#define mmSPI_SHADER_USER_DATA_LS_5 0x2d51
+#define mmSPI_SHADER_USER_DATA_LS_6 0x2d52
+#define mmSPI_SHADER_USER_DATA_LS_7 0x2d53
+#define mmSPI_SHADER_USER_DATA_LS_8 0x2d54
+#define mmSPI_SHADER_USER_DATA_LS_9 0x2d55
+#define mmSPI_SHADER_USER_DATA_LS_10 0x2d56
+#define mmSPI_SHADER_USER_DATA_LS_11 0x2d57
+#define mmSPI_SHADER_USER_DATA_LS_12 0x2d58
+#define mmSPI_SHADER_USER_DATA_LS_13 0x2d59
+#define mmSPI_SHADER_USER_DATA_LS_14 0x2d5a
+#define mmSPI_SHADER_USER_DATA_LS_15 0x2d5b
+#define mmSQ_CONFIG 0x2300
+#define mmSQC_CONFIG 0x2301
+#define mmSQC_CACHES 0xc348
+#define mmSQC_WRITEBACK 0xc349
+#define mmSQC_DSM_CNTL 0x230f
+#define mmSQ_RANDOM_WAVE_PRI 0x2303
+#define mmSQ_REG_CREDITS 0x2304
+#define mmSQ_FIFO_SIZES 0x2305
+#define mmSQ_DSM_CNTL 0x2306
+#define mmCC_GC_SHADER_RATE_CONFIG 0x2312
+#define mmGC_USER_SHADER_RATE_CONFIG 0x2313
+#define mmSQ_INTERRUPT_AUTO_MASK 0x2314
+#define mmSQ_INTERRUPT_MSG_CTRL 0x2315
+#define mmSQ_PERFCOUNTER_CTRL 0xd9e0
+#define mmSQ_PERFCOUNTER_MASK 0xd9e1
+#define mmSQ_PERFCOUNTER_CTRL2 0xd9e2
+#define mmCC_SQC_BANK_DISABLE 0x2307
+#define mmUSER_SQC_BANK_DISABLE 0x2308
+#define mmSQ_PERFCOUNTER0_LO 0xd1c0
+#define mmSQ_PERFCOUNTER1_LO 0xd1c2
+#define mmSQ_PERFCOUNTER2_LO 0xd1c4
+#define mmSQ_PERFCOUNTER3_LO 0xd1c6
+#define mmSQ_PERFCOUNTER4_LO 0xd1c8
+#define mmSQ_PERFCOUNTER5_LO 0xd1ca
+#define mmSQ_PERFCOUNTER6_LO 0xd1cc
+#define mmSQ_PERFCOUNTER7_LO 0xd1ce
+#define mmSQ_PERFCOUNTER8_LO 0xd1d0
+#define mmSQ_PERFCOUNTER9_LO 0xd1d2
+#define mmSQ_PERFCOUNTER10_LO 0xd1d4
+#define mmSQ_PERFCOUNTER11_LO 0xd1d6
+#define mmSQ_PERFCOUNTER12_LO 0xd1d8
+#define mmSQ_PERFCOUNTER13_LO 0xd1da
+#define mmSQ_PERFCOUNTER14_LO 0xd1dc
+#define mmSQ_PERFCOUNTER15_LO 0xd1de
+#define mmSQ_PERFCOUNTER0_HI 0xd1c1
+#define mmSQ_PERFCOUNTER1_HI 0xd1c3
+#define mmSQ_PERFCOUNTER2_HI 0xd1c5
+#define mmSQ_PERFCOUNTER3_HI 0xd1c7
+#define mmSQ_PERFCOUNTER4_HI 0xd1c9
+#define mmSQ_PERFCOUNTER5_HI 0xd1cb
+#define mmSQ_PERFCOUNTER6_HI 0xd1cd
+#define mmSQ_PERFCOUNTER7_HI 0xd1cf
+#define mmSQ_PERFCOUNTER8_HI 0xd1d1
+#define mmSQ_PERFCOUNTER9_HI 0xd1d3
+#define mmSQ_PERFCOUNTER10_HI 0xd1d5
+#define mmSQ_PERFCOUNTER11_HI 0xd1d7
+#define mmSQ_PERFCOUNTER12_HI 0xd1d9
+#define mmSQ_PERFCOUNTER13_HI 0xd1db
+#define mmSQ_PERFCOUNTER14_HI 0xd1dd
+#define mmSQ_PERFCOUNTER15_HI 0xd1df
+#define mmSQ_PERFCOUNTER0_SELECT 0xd9c0
+#define mmSQ_PERFCOUNTER1_SELECT 0xd9c1
+#define mmSQ_PERFCOUNTER2_SELECT 0xd9c2
+#define mmSQ_PERFCOUNTER3_SELECT 0xd9c3
+#define mmSQ_PERFCOUNTER4_SELECT 0xd9c4
+#define mmSQ_PERFCOUNTER5_SELECT 0xd9c5
+#define mmSQ_PERFCOUNTER6_SELECT 0xd9c6
+#define mmSQ_PERFCOUNTER7_SELECT 0xd9c7
+#define mmSQ_PERFCOUNTER8_SELECT 0xd9c8
+#define mmSQ_PERFCOUNTER9_SELECT 0xd9c9
+#define mmSQ_PERFCOUNTER10_SELECT 0xd9ca
+#define mmSQ_PERFCOUNTER11_SELECT 0xd9cb
+#define mmSQ_PERFCOUNTER12_SELECT 0xd9cc
+#define mmSQ_PERFCOUNTER13_SELECT 0xd9cd
+#define mmSQ_PERFCOUNTER14_SELECT 0xd9ce
+#define mmSQ_PERFCOUNTER15_SELECT 0xd9cf
+#define mmCGTT_SQ_CLK_CTRL 0xf08c
+#define mmCGTT_SQG_CLK_CTRL 0xf08d
+#define mmSQ_ALU_CLK_CTRL 0xf08e
+#define mmSQ_TEX_CLK_CTRL 0xf08f
+#define mmSQ_LDS_CLK_CTRL 0xf090
+#define mmSQ_POWER_THROTTLE 0xf091
+#define mmSQ_POWER_THROTTLE2 0xf092
+#define mmSQ_TIME_HI 0x237c
+#define mmSQ_TIME_LO 0x237d
+#define mmSQ_THREAD_TRACE_BASE 0xc330
+#define mmSQ_THREAD_TRACE_BASE2 0xc337
+#define mmSQ_THREAD_TRACE_SIZE 0xc331
+#define mmSQ_THREAD_TRACE_MASK 0xc332
+#define mmSQ_THREAD_TRACE_USERDATA_0 0xc340
+#define mmSQ_THREAD_TRACE_USERDATA_1 0xc341
+#define mmSQ_THREAD_TRACE_USERDATA_2 0xc342
+#define mmSQ_THREAD_TRACE_USERDATA_3 0xc343
+#define mmSQ_THREAD_TRACE_MODE 0xc336
+#define mmSQ_THREAD_TRACE_CTRL 0xc335
+#define mmSQ_THREAD_TRACE_TOKEN_MASK 0xc333
+#define mmSQ_THREAD_TRACE_TOKEN_MASK2 0xc338
+#define mmSQ_THREAD_TRACE_PERF_MASK 0xc334
+#define mmSQ_THREAD_TRACE_WPTR 0xc339
+#define mmSQ_THREAD_TRACE_STATUS 0xc33a
+#define mmSQ_THREAD_TRACE_CNTR 0x2390
+#define mmSQ_THREAD_TRACE_HIWATER 0xc33b
+#define mmSQ_LB_CTR_CTRL 0x2398
+#define mmSQ_LB_DATA_ALU_CYCLES 0x2399
+#define mmSQ_LB_DATA_TEX_CYCLES 0x239a
+#define mmSQ_LB_DATA_ALU_STALLS 0x239b
+#define mmSQ_LB_DATA_TEX_STALLS 0x239c
+#define mmSQC_EDC_CNT 0x23a0
+#define mmSQ_EDC_SEC_CNT 0x23a1
+#define mmSQ_EDC_DED_CNT 0x23a2
+#define mmSQ_EDC_INFO 0x23a3
+#define mmSQ_BUF_RSRC_WORD0 0x23c0
+#define mmSQ_BUF_RSRC_WORD1 0x23c1
+#define mmSQ_BUF_RSRC_WORD2 0x23c2
+#define mmSQ_BUF_RSRC_WORD3 0x23c3
+#define mmSQ_IMG_RSRC_WORD0 0x23c4
+#define mmSQ_IMG_RSRC_WORD1 0x23c5
+#define mmSQ_IMG_RSRC_WORD2 0x23c6
+#define mmSQ_IMG_RSRC_WORD3 0x23c7
+#define mmSQ_IMG_RSRC_WORD4 0x23c8
+#define mmSQ_IMG_RSRC_WORD5 0x23c9
+#define mmSQ_IMG_RSRC_WORD6 0x23ca
+#define mmSQ_IMG_RSRC_WORD7 0x23cb
+#define mmSQ_IMG_SAMP_WORD0 0x23cc
+#define mmSQ_IMG_SAMP_WORD1 0x23cd
+#define mmSQ_IMG_SAMP_WORD2 0x23ce
+#define mmSQ_IMG_SAMP_WORD3 0x23cf
+#define mmSQ_FLAT_SCRATCH_WORD0 0x23d0
+#define mmSQ_FLAT_SCRATCH_WORD1 0x23d1
+#define mmSQ_M0_GPR_IDX_WORD 0x23d2
+#define mmSQ_IND_INDEX 0x2378
+#define mmSQ_CMD 0x237b
+#define mmSQ_IND_DATA 0x2379
+#define mmSQ_REG_TIMESTAMP 0x2374
+#define mmSQ_CMD_TIMESTAMP 0x2375
+#define mmSQ_HV_VMID_CTRL 0xf840
+#define ixSQ_WAVE_INST_DW0 0x1a
+#define ixSQ_WAVE_INST_DW1 0x1b
+#define ixSQ_WAVE_PC_LO 0x18
+#define ixSQ_WAVE_PC_HI 0x19
+#define ixSQ_WAVE_IB_DBG0 0x1c
+#define ixSQ_WAVE_IB_DBG1 0x1d
+#define ixSQ_WAVE_EXEC_LO 0x27e
+#define ixSQ_WAVE_EXEC_HI 0x27f
+#define ixSQ_WAVE_STATUS 0x12
+#define ixSQ_WAVE_MODE 0x11
+#define ixSQ_WAVE_TRAPSTS 0x13
+#define ixSQ_WAVE_HW_ID 0x14
+#define ixSQ_WAVE_GPR_ALLOC 0x15
+#define ixSQ_WAVE_LDS_ALLOC 0x16
+#define ixSQ_WAVE_IB_STS 0x17
+#define ixSQ_WAVE_M0 0x27c
+#define ixSQ_WAVE_TBA_LO 0x26c
+#define ixSQ_WAVE_TBA_HI 0x26d
+#define ixSQ_WAVE_TMA_LO 0x26e
+#define ixSQ_WAVE_TMA_HI 0x26f
+#define ixSQ_WAVE_TTMP0 0x270
+#define ixSQ_WAVE_TTMP1 0x271
+#define ixSQ_WAVE_TTMP2 0x272
+#define ixSQ_WAVE_TTMP3 0x273
+#define ixSQ_WAVE_TTMP4 0x274
+#define ixSQ_WAVE_TTMP5 0x275
+#define ixSQ_WAVE_TTMP6 0x276
+#define ixSQ_WAVE_TTMP7 0x277
+#define ixSQ_WAVE_TTMP8 0x278
+#define ixSQ_WAVE_TTMP9 0x279
+#define ixSQ_WAVE_TTMP10 0x27a
+#define ixSQ_WAVE_TTMP11 0x27b
+#define mmSQ_DEBUG_STS_GLOBAL 0x2309
+#define mmSQ_DEBUG_STS_GLOBAL2 0x2310
+#define mmSQ_DEBUG_STS_GLOBAL3 0x2311
+#define ixSQ_DEBUG_STS_LOCAL 0x8
+#define ixSQ_DEBUG_CTRL_LOCAL 0x9
+#define mmSH_MEM_BASES 0x230a
+#define mmSH_MEM_APE1_BASE 0x230b
+#define mmSH_MEM_APE1_LIMIT 0x230c
+#define mmSH_MEM_CONFIG 0x230d
+#define mmSQ_THREAD_TRACE_WORD_CMN 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_INST 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x23b1
+#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x23b1
+#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x23b1
+#define mmSQ_THREAD_TRACE_WORD_WAVE 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_MISC 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_EVENT 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x23b1
+#define mmSQ_WREXEC_EXEC_LO 0x23b1
+#define mmSQ_WREXEC_EXEC_HI 0x23b1
+#define mmSQC_GATCL1_CNTL 0x23b2
+#define mmSQC_ATC_EDC_GATCL1_CNT 0x23b3
+#define ixSQ_INTERRUPT_WORD_CMN 0x20c0
+#define ixSQ_INTERRUPT_WORD_AUTO 0x20c0
+#define ixSQ_INTERRUPT_WORD_WAVE 0x20c0
+#define mmSQ_SOP2 0x237f
+#define mmSQ_VOP1 0x237f
+#define mmSQ_MTBUF_1 0x237f
+#define mmSQ_EXP_1 0x237f
+#define mmSQ_MUBUF_1 0x237f
+#define mmSQ_SMEM_1 0x237f
+#define mmSQ_INST 0x237f
+#define mmSQ_EXP_0 0x237f
+#define mmSQ_MUBUF_0 0x237f
+#define mmSQ_VOP_SDWA 0x237f
+#define mmSQ_VOP3_0 0x237f
+#define mmSQ_VOP2 0x237f
+#define mmSQ_MTBUF_0 0x237f
+#define mmSQ_SOPP 0x237f
+#define mmSQ_FLAT_0 0x237f
+#define mmSQ_VOP3_0_SDST_ENC 0x237f
+#define mmSQ_MIMG_1 0x237f
+#define mmSQ_SOP1 0x237f
+#define mmSQ_SOPC 0x237f
+#define mmSQ_FLAT_1 0x237f
+#define mmSQ_DS_1 0x237f
+#define mmSQ_VOP3_1 0x237f
+#define mmSQ_SMEM_0 0x237f
+#define mmSQ_MIMG_0 0x237f
+#define mmSQ_SOPK 0x237f
+#define mmSQ_DS_0 0x237f
+#define mmSQ_VOP_DPP 0x237f
+#define mmSQ_VOPC 0x237f
+#define mmSQ_VINTRP 0x237f
+#define mmCGTT_SX_CLK_CTRL0 0xf094
+#define mmCGTT_SX_CLK_CTRL1 0xf095
+#define mmCGTT_SX_CLK_CTRL2 0xf096
+#define mmCGTT_SX_CLK_CTRL3 0xf097
+#define mmCGTT_SX_CLK_CTRL4 0xf098
+#define mmSX_DEBUG_BUSY 0x2414
+#define mmSX_DEBUG_BUSY_2 0x2415
+#define mmSX_DEBUG_BUSY_3 0x2416
+#define mmSX_DEBUG_BUSY_4 0x2417
+#define mmSX_DEBUG_1 0x2418
+#define mmSX_PERFCOUNTER0_SELECT 0xda40
+#define mmSX_PERFCOUNTER1_SELECT 0xda41
+#define mmSX_PERFCOUNTER2_SELECT 0xda42
+#define mmSX_PERFCOUNTER3_SELECT 0xda43
+#define mmSX_PERFCOUNTER0_SELECT1 0xda44
+#define mmSX_PERFCOUNTER1_SELECT1 0xda45
+#define mmSX_PERFCOUNTER0_LO 0xd240
+#define mmSX_PERFCOUNTER0_HI 0xd241
+#define mmSX_PERFCOUNTER1_LO 0xd242
+#define mmSX_PERFCOUNTER1_HI 0xd243
+#define mmSX_PERFCOUNTER2_LO 0xd244
+#define mmSX_PERFCOUNTER2_HI 0xd245
+#define mmSX_PERFCOUNTER3_LO 0xd246
+#define mmSX_PERFCOUNTER3_HI 0xd247
+#define mmTCC_CTRL 0x2b80
+#define mmTCC_EDC_CNT 0x2b82
+#define mmTCC_REDUNDANCY 0x2b83
+#define mmTCC_EXE_DISABLE 0x2b84
+#define mmTCC_DSM_CNTL 0x2b85
+#define mmTCC_CGTT_SCLK_CTRL 0xf0ac
+#define mmTCA_CGTT_SCLK_CTRL 0xf0ad
+#define mmTCC_PERFCOUNTER0_SELECT 0xdb80
+#define mmTCC_PERFCOUNTER1_SELECT 0xdb82
+#define mmTCC_PERFCOUNTER0_SELECT1 0xdb81
+#define mmTCC_PERFCOUNTER1_SELECT1 0xdb83
+#define mmTCC_PERFCOUNTER2_SELECT 0xdb84
+#define mmTCC_PERFCOUNTER3_SELECT 0xdb85
+#define mmTCC_PERFCOUNTER0_LO 0xd380
+#define mmTCC_PERFCOUNTER1_LO 0xd382
+#define mmTCC_PERFCOUNTER2_LO 0xd384
+#define mmTCC_PERFCOUNTER3_LO 0xd386
+#define mmTCC_PERFCOUNTER0_HI 0xd381
+#define mmTCC_PERFCOUNTER1_HI 0xd383
+#define mmTCC_PERFCOUNTER2_HI 0xd385
+#define mmTCC_PERFCOUNTER3_HI 0xd387
+#define mmTCA_CTRL 0x2bc0
+#define mmTCA_PERFCOUNTER0_SELECT 0xdb90
+#define mmTCA_PERFCOUNTER1_SELECT 0xdb92
+#define mmTCA_PERFCOUNTER0_SELECT1 0xdb91
+#define mmTCA_PERFCOUNTER1_SELECT1 0xdb93
+#define mmTCA_PERFCOUNTER2_SELECT 0xdb94
+#define mmTCA_PERFCOUNTER3_SELECT 0xdb95
+#define mmTCA_PERFCOUNTER0_LO 0xd390
+#define mmTCA_PERFCOUNTER1_LO 0xd392
+#define mmTCA_PERFCOUNTER2_LO 0xd394
+#define mmTCA_PERFCOUNTER3_LO 0xd396
+#define mmTCA_PERFCOUNTER0_HI 0xd391
+#define mmTCA_PERFCOUNTER1_HI 0xd393
+#define mmTCA_PERFCOUNTER2_HI 0xd395
+#define mmTCA_PERFCOUNTER3_HI 0xd397
+#define mmTA_BC_BASE_ADDR 0xa020
+#define mmTA_BC_BASE_ADDR_HI 0xa021
+#define mmTD_CNTL 0x2525
+#define mmTD_STATUS 0x2526
+#define mmTD_DEBUG_INDEX 0x2528
+#define mmTD_DEBUG_DATA 0x2529
+#define mmTD_DSM_CNTL 0x252f
+#define mmTD_PERFCOUNTER0_SELECT 0xdb00
+#define mmTD_PERFCOUNTER1_SELECT 0xdb02
+#define mmTD_PERFCOUNTER0_SELECT1 0xdb01
+#define mmTD_PERFCOUNTER0_LO 0xd300
+#define mmTD_PERFCOUNTER1_LO 0xd302
+#define mmTD_PERFCOUNTER0_HI 0xd301
+#define mmTD_PERFCOUNTER1_HI 0xd303
+#define mmTD_SCRATCH 0x2533
+#define mmTA_CNTL 0x2541
+#define mmTA_CNTL_AUX 0x2542
+#define mmTA_RESERVED_010C 0x2543
+#define mmTA_CS_BC_BASE_ADDR 0xc380
+#define mmTA_CS_BC_BASE_ADDR_HI 0xc381
+#define mmTA_STATUS 0x2548
+#define mmTA_DEBUG_INDEX 0x254c
+#define mmTA_DEBUG_DATA 0x254d
+#define mmTA_PERFCOUNTER0_SELECT 0xdac0
+#define mmTA_PERFCOUNTER1_SELECT 0xdac2
+#define mmTA_PERFCOUNTER0_SELECT1 0xdac1
+#define mmTA_PERFCOUNTER0_LO 0xd2c0
+#define mmTA_PERFCOUNTER1_LO 0xd2c2
+#define mmTA_PERFCOUNTER0_HI 0xd2c1
+#define mmTA_PERFCOUNTER1_HI 0xd2c3
+#define mmTA_SCRATCH 0x2564
+#define mmSH_HIDDEN_PRIVATE_BASE_VMID 0x2580
+#define mmSH_STATIC_MEM_CONFIG 0x2581
+#define mmTCP_INVALIDATE 0x2b00
+#define mmTCP_STATUS 0x2b01
+#define mmTCP_CNTL 0x2b02
+#define mmTCP_CHAN_STEER_LO 0x2b03
+#define mmTCP_CHAN_STEER_HI 0x2b04
+#define mmTCP_ADDR_CONFIG 0x2b05
+#define mmTCP_CREDIT 0x2b06
+#define mmTCP_PERFCOUNTER0_SELECT 0xdb40
+#define mmTCP_PERFCOUNTER1_SELECT 0xdb42
+#define mmTCP_PERFCOUNTER0_SELECT1 0xdb41
+#define mmTCP_PERFCOUNTER1_SELECT1 0xdb43
+#define mmTCP_PERFCOUNTER2_SELECT 0xdb44
+#define mmTCP_PERFCOUNTER3_SELECT 0xdb45
+#define mmTCP_PERFCOUNTER0_LO 0xd340
+#define mmTCP_PERFCOUNTER1_LO 0xd342
+#define mmTCP_PERFCOUNTER2_LO 0xd344
+#define mmTCP_PERFCOUNTER3_LO 0xd346
+#define mmTCP_PERFCOUNTER0_HI 0xd341
+#define mmTCP_PERFCOUNTER1_HI 0xd343
+#define mmTCP_PERFCOUNTER2_HI 0xd345
+#define mmTCP_PERFCOUNTER3_HI 0xd347
+#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x2b16
+#define mmTCP_EDC_CNT 0x2b17
+#define mmTC_CFG_L1_LOAD_POLICY0 0x2b1a
+#define mmTC_CFG_L1_LOAD_POLICY1 0x2b1b
+#define mmTC_CFG_L1_STORE_POLICY 0x2b1c
+#define mmTC_CFG_L2_LOAD_POLICY0 0x2b1d
+#define mmTC_CFG_L2_LOAD_POLICY1 0x2b1e
+#define mmTC_CFG_L2_STORE_POLICY0 0x2b1f
+#define mmTC_CFG_L2_STORE_POLICY1 0x2b20
+#define mmTC_CFG_L2_ATOMIC_POLICY 0x2b21
+#define mmTC_CFG_L1_VOLATILE 0x2b22
+#define mmTC_CFG_L2_VOLATILE 0x2b23
+#define mmTCP_WATCH0_ADDR_H 0x32a0
+#define mmTCP_WATCH1_ADDR_H 0x32a3
+#define mmTCP_WATCH2_ADDR_H 0x32a6
+#define mmTCP_WATCH3_ADDR_H 0x32a9
+#define mmTCP_WATCH0_ADDR_L 0x32a1
+#define mmTCP_WATCH1_ADDR_L 0x32a4
+#define mmTCP_WATCH2_ADDR_L 0x32a7
+#define mmTCP_WATCH3_ADDR_L 0x32aa
+#define mmTCP_WATCH0_CNTL 0x32a2
+#define mmTCP_WATCH1_CNTL 0x32a5
+#define mmTCP_WATCH2_CNTL 0x32a8
+#define mmTCP_WATCH3_CNTL 0x32ab
+#define mmTCP_GATCL1_CNTL 0x32b0
+#define mmTCP_ATC_EDC_GATCL1_CNT 0x32b1
+#define mmTCP_GATCL1_DSM_CNTL 0x32b2
+#define mmTCP_DSM_CNTL 0x32b3
+#define mmTCP_CNTL2 0x32b4
+#define mmTD_CGTT_CTRL 0xf09c
+#define mmTA_CGTT_CTRL 0xf09d
+#define mmCGTT_TCP_CLK_CTRL 0xf09e
+#define mmCGTT_TCI_CLK_CTRL 0xf09f
+#define mmTCI_STATUS 0x2b61
+#define mmTCI_CNTL_1 0x2b62
+#define mmTCI_CNTL_2 0x2b63
+#define mmGDS_CONFIG 0x25c0
+#define mmGDS_CNTL_STATUS 0x25c1
+#define mmGDS_ENHANCE2 0x25c2
+#define mmGDS_PROTECTION_FAULT 0x25c3
+#define mmGDS_VM_PROTECTION_FAULT 0x25c4
+#define mmGDS_EDC_CNT 0x25c5
+#define mmGDS_EDC_GRBM_CNT 0x25c6
+#define mmGDS_EDC_OA_DED 0x25c7
+#define mmGDS_DEBUG_CNTL 0x25c8
+#define mmGDS_DEBUG_DATA 0x25c9
+#define mmGDS_DSM_CNTL 0x25ca
+#define mmCGTT_GDS_CLK_CTRL 0xf0a0
+#define mmGDS_RD_ADDR 0xc400
+#define mmGDS_RD_DATA 0xc401
+#define mmGDS_RD_BURST_ADDR 0xc402
+#define mmGDS_RD_BURST_COUNT 0xc403
+#define mmGDS_RD_BURST_DATA 0xc404
+#define mmGDS_WR_ADDR 0xc405
+#define mmGDS_WR_DATA 0xc406
+#define mmGDS_WR_BURST_ADDR 0xc407
+#define mmGDS_WR_BURST_DATA 0xc408
+#define mmGDS_WRITE_COMPLETE 0xc409
+#define mmGDS_ATOM_CNTL 0xc40a
+#define mmGDS_ATOM_COMPLETE 0xc40b
+#define mmGDS_ATOM_BASE 0xc40c
+#define mmGDS_ATOM_SIZE 0xc40d
+#define mmGDS_ATOM_OFFSET0 0xc40e
+#define mmGDS_ATOM_OFFSET1 0xc40f
+#define mmGDS_ATOM_DST 0xc410
+#define mmGDS_ATOM_OP 0xc411
+#define mmGDS_ATOM_SRC0 0xc412
+#define mmGDS_ATOM_SRC0_U 0xc413
+#define mmGDS_ATOM_SRC1 0xc414
+#define mmGDS_ATOM_SRC1_U 0xc415
+#define mmGDS_ATOM_READ0 0xc416
+#define mmGDS_ATOM_READ0_U 0xc417
+#define mmGDS_ATOM_READ1 0xc418
+#define mmGDS_ATOM_READ1_U 0xc419
+#define mmGDS_GWS_RESOURCE_CNTL 0xc41a
+#define mmGDS_GWS_RESOURCE 0xc41b
+#define mmGDS_GWS_RESOURCE_CNT 0xc41c
+#define mmGDS_OA_CNTL 0xc41d
+#define mmGDS_OA_COUNTER 0xc41e
+#define mmGDS_OA_ADDRESS 0xc41f
+#define mmGDS_OA_INCDEC 0xc420
+#define mmGDS_OA_RING_SIZE 0xc421
+#define ixGDS_DEBUG_REG0 0x0
+#define ixGDS_DEBUG_REG1 0x1
+#define ixGDS_DEBUG_REG2 0x2
+#define ixGDS_DEBUG_REG3 0x3
+#define ixGDS_DEBUG_REG4 0x4
+#define ixGDS_DEBUG_REG5 0x5
+#define ixGDS_DEBUG_REG6 0x6
+#define mmGDS_PERFCOUNTER0_SELECT 0xda80
+#define mmGDS_PERFCOUNTER1_SELECT 0xda81
+#define mmGDS_PERFCOUNTER2_SELECT 0xda82
+#define mmGDS_PERFCOUNTER3_SELECT 0xda83
+#define mmGDS_PERFCOUNTER0_LO 0xd280
+#define mmGDS_PERFCOUNTER1_LO 0xd282
+#define mmGDS_PERFCOUNTER2_LO 0xd284
+#define mmGDS_PERFCOUNTER3_LO 0xd286
+#define mmGDS_PERFCOUNTER0_HI 0xd281
+#define mmGDS_PERFCOUNTER1_HI 0xd283
+#define mmGDS_PERFCOUNTER2_HI 0xd285
+#define mmGDS_PERFCOUNTER3_HI 0xd287
+#define mmGDS_PERFCOUNTER0_SELECT1 0xda84
+#define mmGDS_VMID0_BASE 0x3300
+#define mmGDS_VMID1_BASE 0x3302
+#define mmGDS_VMID2_BASE 0x3304
+#define mmGDS_VMID3_BASE 0x3306
+#define mmGDS_VMID4_BASE 0x3308
+#define mmGDS_VMID5_BASE 0x330a
+#define mmGDS_VMID6_BASE 0x330c
+#define mmGDS_VMID7_BASE 0x330e
+#define mmGDS_VMID8_BASE 0x3310
+#define mmGDS_VMID9_BASE 0x3312
+#define mmGDS_VMID10_BASE 0x3314
+#define mmGDS_VMID11_BASE 0x3316
+#define mmGDS_VMID12_BASE 0x3318
+#define mmGDS_VMID13_BASE 0x331a
+#define mmGDS_VMID14_BASE 0x331c
+#define mmGDS_VMID15_BASE 0x331e
+#define mmGDS_VMID0_SIZE 0x3301
+#define mmGDS_VMID1_SIZE 0x3303
+#define mmGDS_VMID2_SIZE 0x3305
+#define mmGDS_VMID3_SIZE 0x3307
+#define mmGDS_VMID4_SIZE 0x3309
+#define mmGDS_VMID5_SIZE 0x330b
+#define mmGDS_VMID6_SIZE 0x330d
+#define mmGDS_VMID7_SIZE 0x330f
+#define mmGDS_VMID8_SIZE 0x3311
+#define mmGDS_VMID9_SIZE 0x3313
+#define mmGDS_VMID10_SIZE 0x3315
+#define mmGDS_VMID11_SIZE 0x3317
+#define mmGDS_VMID12_SIZE 0x3319
+#define mmGDS_VMID13_SIZE 0x331b
+#define mmGDS_VMID14_SIZE 0x331d
+#define mmGDS_VMID15_SIZE 0x331f
+#define mmGDS_GWS_VMID0 0x3320
+#define mmGDS_GWS_VMID1 0x3321
+#define mmGDS_GWS_VMID2 0x3322
+#define mmGDS_GWS_VMID3 0x3323
+#define mmGDS_GWS_VMID4 0x3324
+#define mmGDS_GWS_VMID5 0x3325
+#define mmGDS_GWS_VMID6 0x3326
+#define mmGDS_GWS_VMID7 0x3327
+#define mmGDS_GWS_VMID8 0x3328
+#define mmGDS_GWS_VMID9 0x3329
+#define mmGDS_GWS_VMID10 0x332a
+#define mmGDS_GWS_VMID11 0x332b
+#define mmGDS_GWS_VMID12 0x332c
+#define mmGDS_GWS_VMID13 0x332d
+#define mmGDS_GWS_VMID14 0x332e
+#define mmGDS_GWS_VMID15 0x332f
+#define mmGDS_OA_VMID0 0x3330
+#define mmGDS_OA_VMID1 0x3331
+#define mmGDS_OA_VMID2 0x3332
+#define mmGDS_OA_VMID3 0x3333
+#define mmGDS_OA_VMID4 0x3334
+#define mmGDS_OA_VMID5 0x3335
+#define mmGDS_OA_VMID6 0x3336
+#define mmGDS_OA_VMID7 0x3337
+#define mmGDS_OA_VMID8 0x3338
+#define mmGDS_OA_VMID9 0x3339
+#define mmGDS_OA_VMID10 0x333a
+#define mmGDS_OA_VMID11 0x333b
+#define mmGDS_OA_VMID12 0x333c
+#define mmGDS_OA_VMID13 0x333d
+#define mmGDS_OA_VMID14 0x333e
+#define mmGDS_OA_VMID15 0x333f
+#define mmGDS_GWS_RESET0 0x3344
+#define mmGDS_GWS_RESET1 0x3345
+#define mmGDS_GWS_RESOURCE_RESET 0x3346
+#define mmGDS_COMPUTE_MAX_WAVE_ID 0x3348
+#define mmGDS_OA_RESET_MASK 0x3349
+#define mmGDS_OA_RESET 0x334a
+#define mmGDS_ENHANCE 0x334b
+#define mmGDS_OA_CGPG_RESTORE 0x334c
+#define mmGDS_CS_CTXSW_STATUS 0x334d
+#define mmGDS_CS_CTXSW_CNT0 0x334e
+#define mmGDS_CS_CTXSW_CNT1 0x334f
+#define mmGDS_CS_CTXSW_CNT2 0x3350
+#define mmGDS_CS_CTXSW_CNT3 0x3351
+#define mmGDS_GFX_CTXSW_STATUS 0x3352
+#define mmGDS_VS_CTXSW_CNT0 0x3353
+#define mmGDS_VS_CTXSW_CNT1 0x3354
+#define mmGDS_VS_CTXSW_CNT2 0x3355
+#define mmGDS_VS_CTXSW_CNT3 0x3356
+#define mmGDS_PS0_CTXSW_CNT0 0x3357
+#define mmGDS_PS1_CTXSW_CNT0 0x335b
+#define mmGDS_PS2_CTXSW_CNT0 0x335f
+#define mmGDS_PS3_CTXSW_CNT0 0x3363
+#define mmGDS_PS4_CTXSW_CNT0 0x3367
+#define mmGDS_PS5_CTXSW_CNT0 0x336b
+#define mmGDS_PS6_CTXSW_CNT0 0x336f
+#define mmGDS_PS7_CTXSW_CNT0 0x3373
+#define mmGDS_PS0_CTXSW_CNT1 0x3358
+#define mmGDS_PS1_CTXSW_CNT1 0x335c
+#define mmGDS_PS2_CTXSW_CNT1 0x3360
+#define mmGDS_PS3_CTXSW_CNT1 0x3364
+#define mmGDS_PS4_CTXSW_CNT1 0x3368
+#define mmGDS_PS5_CTXSW_CNT1 0x336c
+#define mmGDS_PS6_CTXSW_CNT1 0x3370
+#define mmGDS_PS7_CTXSW_CNT1 0x3374
+#define mmGDS_PS0_CTXSW_CNT2 0x3359
+#define mmGDS_PS1_CTXSW_CNT2 0x335d
+#define mmGDS_PS2_CTXSW_CNT2 0x3361
+#define mmGDS_PS3_CTXSW_CNT2 0x3365
+#define mmGDS_PS4_CTXSW_CNT2 0x3369
+#define mmGDS_PS5_CTXSW_CNT2 0x336d
+#define mmGDS_PS6_CTXSW_CNT2 0x3371
+#define mmGDS_PS7_CTXSW_CNT2 0x3375
+#define mmGDS_PS0_CTXSW_CNT3 0x335a
+#define mmGDS_PS1_CTXSW_CNT3 0x335e
+#define mmGDS_PS2_CTXSW_CNT3 0x3362
+#define mmGDS_PS3_CTXSW_CNT3 0x3366
+#define mmGDS_PS4_CTXSW_CNT3 0x336a
+#define mmGDS_PS5_CTXSW_CNT3 0x336e
+#define mmGDS_PS6_CTXSW_CNT3 0x3372
+#define mmGDS_PS7_CTXSW_CNT3 0x3376
+#define mmCS_COPY_STATE 0xa1f3
+#define mmGFX_COPY_STATE 0xa1f4
+#define mmVGT_DRAW_INITIATOR 0xa1fc
+#define mmVGT_EVENT_INITIATOR 0xa2a4
+#define mmVGT_EVENT_ADDRESS_REG 0xa1fe
+#define mmVGT_DMA_BASE_HI 0xa1f9
+#define mmVGT_DMA_BASE 0xa1fa
+#define mmVGT_DMA_INDEX_TYPE 0xa29f
+#define mmVGT_DMA_NUM_INSTANCES 0xa2a2
+#define mmIA_ENHANCE 0xa29c
+#define mmVGT_DMA_SIZE 0xa29d
+#define mmVGT_DMA_MAX_SIZE 0xa29e
+#define mmVGT_DMA_PRIMITIVE_TYPE 0x2271
+#define mmVGT_DMA_CONTROL 0x2272
+#define mmVGT_IMMED_DATA 0xa1fd
+#define mmVGT_INDEX_TYPE 0xc243
+#define mmVGT_NUM_INDICES 0xc24c
+#define mmVGT_NUM_INSTANCES 0xc24d
+#define mmVGT_PRIMITIVE_TYPE 0xc242
+#define mmVGT_PRIMITIVEID_EN 0xa2a1
+#define mmVGT_PRIMITIVEID_RESET 0xa2a3
+#define mmVGT_VTX_CNT_EN 0xa2ae
+#define mmVGT_REUSE_OFF 0xa2ad
+#define mmVGT_INSTANCE_STEP_RATE_0 0xa2a8
+#define mmVGT_INSTANCE_STEP_RATE_1 0xa2a9
+#define mmVGT_MAX_VTX_INDX 0xa100
+#define mmVGT_MIN_VTX_INDX 0xa101
+#define mmVGT_INDX_OFFSET 0xa102
+#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0xa316
+#define mmVGT_OUT_DEALLOC_CNTL 0xa317
+#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0xa103
+#define mmVGT_MULTI_PRIM_IB_RESET_EN 0xa2a5
+#define mmVGT_ENHANCE 0xa294
+#define mmVGT_OUTPUT_PATH_CNTL 0xa284
+#define mmVGT_HOS_CNTL 0xa285
+#define mmVGT_HOS_MAX_TESS_LEVEL 0xa286
+#define mmVGT_HOS_MIN_TESS_LEVEL 0xa287
+#define mmVGT_HOS_REUSE_DEPTH 0xa288
+#define mmVGT_GROUP_PRIM_TYPE 0xa289
+#define mmVGT_GROUP_FIRST_DECR 0xa28a
+#define mmVGT_GROUP_DECR 0xa28b
+#define mmVGT_GROUP_VECT_0_CNTL 0xa28c
+#define mmVGT_GROUP_VECT_1_CNTL 0xa28d
+#define mmVGT_GROUP_VECT_0_FMT_CNTL 0xa28e
+#define mmVGT_GROUP_VECT_1_FMT_CNTL 0xa28f
+#define mmVGT_VTX_VECT_EJECT_REG 0x222c
+#define mmVGT_DMA_DATA_FIFO_DEPTH 0x222d
+#define mmVGT_DMA_REQ_FIFO_DEPTH 0x222e
+#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x222f
+#define mmVGT_LAST_COPY_STATE 0x2230
+#define mmCC_GC_SHADER_ARRAY_CONFIG 0x226f
+#define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270
+#define mmVGT_GS_MODE 0xa290
+#define mmVGT_GS_ONCHIP_CNTL 0xa291
+#define mmVGT_GS_OUT_PRIM_TYPE 0xa29b
+#define mmVGT_CACHE_INVALIDATION 0x2231
+#define mmVGT_RESET_DEBUG 0x2232
+#define mmVGT_STRMOUT_DELAY 0x2233
+#define mmVGT_FIFO_DEPTHS 0x2234
+#define mmVGT_GS_PER_ES 0xa295
+#define mmVGT_ES_PER_GS 0xa296
+#define mmVGT_GS_PER_VS 0xa297
+#define mmVGT_GS_VERTEX_REUSE 0x2235
+#define mmVGT_MC_LAT_CNTL 0x2236
+#define mmIA_CNTL_STATUS 0x2237
+#define mmVGT_STRMOUT_CONFIG 0xa2e5
+#define mmVGT_STRMOUT_BUFFER_SIZE_0 0xa2b4
+#define mmVGT_STRMOUT_BUFFER_SIZE_1 0xa2b8
+#define mmVGT_STRMOUT_BUFFER_SIZE_2 0xa2bc
+#define mmVGT_STRMOUT_BUFFER_SIZE_3 0xa2c0
+#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0xa2b7
+#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0xa2bb
+#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0xa2bf
+#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0xa2c3
+#define mmVGT_STRMOUT_VTX_STRIDE_0 0xa2b5
+#define mmVGT_STRMOUT_VTX_STRIDE_1 0xa2b9
+#define mmVGT_STRMOUT_VTX_STRIDE_2 0xa2bd
+#define mmVGT_STRMOUT_VTX_STRIDE_3 0xa2c1
+#define mmVGT_STRMOUT_BUFFER_CONFIG 0xa2e6
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0xc244
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0xc245
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0xc246
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0xc247
+#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0xa2ca
+#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0xa2cb
+#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0xa2cc
+#define mmVGT_GS_MAX_VERT_OUT 0xa2ce
+#define mmVGT_SHADER_STAGES_EN 0xa2d5
+#define mmVGT_DISPATCH_DRAW_INDEX 0xa2dd
+#define mmVGT_LS_HS_CONFIG 0xa2d6
+#define mmVGT_DMA_LS_HS_CONFIG 0x2273
+#define mmVGT_TF_PARAM 0xa2db
+#define mmVGT_TESS_DISTRIBUTION 0xa2d4
+#define mmVGT_TF_RING_SIZE 0xc24e
+#define mmVGT_SYS_CONFIG 0x2263
+#define mmVGT_HS_OFFCHIP_PARAM 0xc24f
+#define mmVGT_TF_MEMORY_BASE 0xc250
+#define mmVGT_GS_INSTANCE_CNT 0xa2e4
+#define mmIA_MULTI_VGT_PARAM 0xa2aa
+#define mmVGT_VS_MAX_WAVE_ID 0x2268
+#define mmVGT_ESGS_RING_SIZE 0xc240
+#define mmVGT_GSVS_RING_SIZE 0xc241
+#define mmVGT_GSVS_RING_OFFSET_1 0xa298
+#define mmVGT_GSVS_RING_OFFSET_2 0xa299
+#define mmVGT_GSVS_RING_OFFSET_3 0xa29a
+#define mmVGT_ESGS_RING_ITEMSIZE 0xa2ab
+#define mmVGT_GSVS_RING_ITEMSIZE 0xa2ac
+#define mmVGT_GS_VERT_ITEMSIZE 0xa2d7
+#define mmVGT_GS_VERT_ITEMSIZE_1 0xa2d8
+#define mmVGT_GS_VERT_ITEMSIZE_2 0xa2d9
+#define mmVGT_GS_VERT_ITEMSIZE_3 0xa2da
+#define mmWD_CNTL_STATUS 0x223f
+#define mmWD_ENHANCE 0xa2a0
+#define mmGFX_PIPE_CONTROL 0x226d
+#define mmGFX_PIPE_PRIORITY 0xf87f
+#define mmCGTT_VGT_CLK_CTRL 0xf084
+#define mmCGTT_IA_CLK_CTRL 0xf085
+#define mmCGTT_WD_CLK_CTRL 0xf086
+#define mmVGT_DEBUG_CNTL 0x2238
+#define mmVGT_DEBUG_DATA 0x2239
+#define mmIA_DEBUG_CNTL 0x223a
+#define mmIA_DEBUG_DATA 0x223b
+#define mmVGT_CNTL_STATUS 0x223c
+#define mmWD_DEBUG_CNTL 0x223d
+#define mmWD_DEBUG_DATA 0x223e
+#define mmWD_QOS 0x2242
+#define mmCC_GC_PRIM_CONFIG 0x2240
+#define mmGC_USER_PRIM_CONFIG 0x2241
+#define ixWD_DEBUG_REG0 0x0
+#define ixWD_DEBUG_REG1 0x1
+#define ixWD_DEBUG_REG2 0x2
+#define ixWD_DEBUG_REG3 0x3
+#define ixWD_DEBUG_REG4 0x4
+#define ixWD_DEBUG_REG5 0x5
+#define ixWD_DEBUG_REG6 0x6
+#define ixWD_DEBUG_REG7 0x7
+#define ixWD_DEBUG_REG8 0x8
+#define ixWD_DEBUG_REG9 0x9
+#define ixWD_DEBUG_REG10 0xa
+#define ixIA_DEBUG_REG0 0x0
+#define ixIA_DEBUG_REG1 0x1
+#define ixIA_DEBUG_REG2 0x2
+#define ixIA_DEBUG_REG3 0x3
+#define ixIA_DEBUG_REG4 0x4
+#define ixIA_DEBUG_REG5 0x5
+#define ixIA_DEBUG_REG6 0x6
+#define ixIA_DEBUG_REG7 0x7
+#define ixIA_DEBUG_REG8 0x8
+#define ixIA_DEBUG_REG9 0x9
+#define ixVGT_DEBUG_REG0 0x0
+#define ixVGT_DEBUG_REG1 0x1
+#define ixVGT_DEBUG_REG2 0x1e
+#define ixVGT_DEBUG_REG3 0x1f
+#define ixVGT_DEBUG_REG4 0x20
+#define ixVGT_DEBUG_REG5 0x21
+#define ixVGT_DEBUG_REG6 0x22
+#define ixVGT_DEBUG_REG7 0x23
+#define ixVGT_DEBUG_REG8 0x8
+#define ixVGT_DEBUG_REG9 0x9
+#define ixVGT_DEBUG_REG10 0xa
+#define ixVGT_DEBUG_REG11 0xb
+#define ixVGT_DEBUG_REG12 0xc
+#define ixVGT_DEBUG_REG13 0xd
+#define ixVGT_DEBUG_REG14 0xe
+#define ixVGT_DEBUG_REG15 0xf
+#define ixVGT_DEBUG_REG16 0x10
+#define ixVGT_DEBUG_REG17 0x11
+#define ixVGT_DEBUG_REG18 0x7
+#define ixVGT_DEBUG_REG19 0x13
+#define ixVGT_DEBUG_REG20 0x14
+#define ixVGT_DEBUG_REG21 0x15
+#define ixVGT_DEBUG_REG22 0x16
+#define ixVGT_DEBUG_REG23 0x17
+#define ixVGT_DEBUG_REG24 0x18
+#define ixVGT_DEBUG_REG25 0x19
+#define ixVGT_DEBUG_REG26 0x24
+#define ixVGT_DEBUG_REG27 0x1b
+#define ixVGT_DEBUG_REG28 0x1c
+#define ixVGT_DEBUG_REG29 0x1d
+#define ixVGT_DEBUG_REG31 0x26
+#define ixVGT_DEBUG_REG32 0x27
+#define ixVGT_DEBUG_REG33 0x28
+#define ixVGT_DEBUG_REG34 0x29
+#define ixVGT_DEBUG_REG36 0x2b
+#define mmVGT_PERFCOUNTER_SEID_MASK 0xd894
+#define mmVGT_PERFCOUNTER0_SELECT 0xd88c
+#define mmVGT_PERFCOUNTER1_SELECT 0xd88d
+#define mmVGT_PERFCOUNTER2_SELECT 0xd88e
+#define mmVGT_PERFCOUNTER3_SELECT 0xd88f
+#define mmVGT_PERFCOUNTER0_SELECT1 0xd890
+#define mmVGT_PERFCOUNTER1_SELECT1 0xd891
+#define mmVGT_PERFCOUNTER0_LO 0xd090
+#define mmVGT_PERFCOUNTER1_LO 0xd092
+#define mmVGT_PERFCOUNTER2_LO 0xd094
+#define mmVGT_PERFCOUNTER3_LO 0xd096
+#define mmVGT_PERFCOUNTER0_HI 0xd091
+#define mmVGT_PERFCOUNTER1_HI 0xd093
+#define mmVGT_PERFCOUNTER2_HI 0xd095
+#define mmVGT_PERFCOUNTER3_HI 0xd097
+#define mmIA_PERFCOUNTER0_SELECT 0xd884
+#define mmIA_PERFCOUNTER1_SELECT 0xd885
+#define mmIA_PERFCOUNTER2_SELECT 0xd886
+#define mmIA_PERFCOUNTER3_SELECT 0xd887
+#define mmIA_PERFCOUNTER0_SELECT1 0xd888
+#define mmIA_PERFCOUNTER0_LO 0xd088
+#define mmIA_PERFCOUNTER1_LO 0xd08a
+#define mmIA_PERFCOUNTER2_LO 0xd08c
+#define mmIA_PERFCOUNTER3_LO 0xd08e
+#define mmIA_PERFCOUNTER0_HI 0xd089
+#define mmIA_PERFCOUNTER1_HI 0xd08b
+#define mmIA_PERFCOUNTER2_HI 0xd08d
+#define mmIA_PERFCOUNTER3_HI 0xd08f
+#define mmWD_PERFCOUNTER0_SELECT 0xd880
+#define mmWD_PERFCOUNTER1_SELECT 0xd881
+#define mmWD_PERFCOUNTER2_SELECT 0xd882
+#define mmWD_PERFCOUNTER3_SELECT 0xd883
+#define mmWD_PERFCOUNTER0_LO 0xd080
+#define mmWD_PERFCOUNTER1_LO 0xd082
+#define mmWD_PERFCOUNTER2_LO 0xd084
+#define mmWD_PERFCOUNTER3_LO 0xd086
+#define mmWD_PERFCOUNTER0_HI 0xd081
+#define mmWD_PERFCOUNTER1_HI 0xd083
+#define mmWD_PERFCOUNTER2_HI 0xd085
+#define mmWD_PERFCOUNTER3_HI 0xd087
+#define mmDIDT_IND_INDEX 0x3280
+#define mmDIDT_IND_DATA 0x3281
+#define ixDIDT_SQ_CTRL0 0x0
+#define ixDIDT_SQ_CTRL1 0x1
+#define ixDIDT_SQ_CTRL2 0x2
+#define ixDIDT_SQ_CTRL_OCP 0x3
+#define ixDIDT_SQ_WEIGHT0_3 0x10
+#define ixDIDT_SQ_WEIGHT4_7 0x11
+#define ixDIDT_SQ_WEIGHT8_11 0x12
+#define ixDIDT_DB_CTRL0 0x20
+#define ixDIDT_DB_CTRL1 0x21
+#define ixDIDT_DB_CTRL2 0x22
+#define ixDIDT_DB_CTRL_OCP 0x23
+#define ixDIDT_DB_WEIGHT0_3 0x30
+#define ixDIDT_DB_WEIGHT4_7 0x31
+#define ixDIDT_DB_WEIGHT8_11 0x32
+#define ixDIDT_TD_CTRL0 0x40
+#define ixDIDT_TD_CTRL1 0x41
+#define ixDIDT_TD_CTRL2 0x42
+#define ixDIDT_TD_CTRL_OCP 0x43
+#define ixDIDT_TD_WEIGHT0_3 0x50
+#define ixDIDT_TD_WEIGHT4_7 0x51
+#define ixDIDT_TD_WEIGHT8_11 0x52
+#define ixDIDT_TCP_CTRL0 0x60
+#define ixDIDT_TCP_CTRL1 0x61
+#define ixDIDT_TCP_CTRL2 0x62
+#define ixDIDT_TCP_CTRL_OCP 0x63
+#define ixDIDT_TCP_WEIGHT0_3 0x70
+#define ixDIDT_TCP_WEIGHT4_7 0x71
+#define ixDIDT_TCP_WEIGHT8_11 0x72
+#define ixDIDT_DBR_CTRL0 0x80
+#define ixDIDT_DBR_CTRL1 0x81
+#define ixDIDT_DBR_CTRL2 0x82
+#define ixDIDT_DBR_CTRL_OCP 0x83
+#define ixDIDT_DBR_WEIGHT0_3 0x90
+#define ixDIDT_DBR_WEIGHT4_7 0x91
+#define ixDIDT_DBR_WEIGHT8_11 0x92
+
+#endif /* GFX_8_0_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_enum.h
new file mode 100644
index 000000000000..43386c24c17c
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_enum.h
@@ -0,0 +1,6858 @@
+/*
+ * GFX_8_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GFX_8_0_ENUM_H
+#define GFX_8_0_ENUM_H
+
+typedef enum SurfaceNumber {
+ NUMBER_UNORM = 0x0,
+ NUMBER_SNORM = 0x1,
+ NUMBER_USCALED = 0x2,
+ NUMBER_SSCALED = 0x3,
+ NUMBER_UINT = 0x4,
+ NUMBER_SINT = 0x5,
+ NUMBER_SRGB = 0x6,
+ NUMBER_FLOAT = 0x7,
+} SurfaceNumber;
+typedef enum SurfaceSwap {
+ SWAP_STD = 0x0,
+ SWAP_ALT = 0x1,
+ SWAP_STD_REV = 0x2,
+ SWAP_ALT_REV = 0x3,
+} SurfaceSwap;
+typedef enum CBMode {
+ CB_DISABLE = 0x0,
+ CB_NORMAL = 0x1,
+ CB_ELIMINATE_FAST_CLEAR = 0x2,
+ CB_RESOLVE = 0x3,
+ CB_DECOMPRESS = 0x4,
+ CB_FMASK_DECOMPRESS = 0x5,
+ CB_DCC_DECOMPRESS = 0x6,
+} CBMode;
+typedef enum RoundMode {
+ ROUND_BY_HALF = 0x0,
+ ROUND_TRUNCATE = 0x1,
+} RoundMode;
+typedef enum SourceFormat {
+ EXPORT_4C_32BPC = 0x0,
+ EXPORT_4C_16BPC = 0x1,
+ EXPORT_2C_32BPC_GR = 0x2,
+ EXPORT_2C_32BPC_AR = 0x3,
+} SourceFormat;
+typedef enum BlendOp {
+ BLEND_ZERO = 0x0,
+ BLEND_ONE = 0x1,
+ BLEND_SRC_COLOR = 0x2,
+ BLEND_ONE_MINUS_SRC_COLOR = 0x3,
+ BLEND_SRC_ALPHA = 0x4,
+ BLEND_ONE_MINUS_SRC_ALPHA = 0x5,
+ BLEND_DST_ALPHA = 0x6,
+ BLEND_ONE_MINUS_DST_ALPHA = 0x7,
+ BLEND_DST_COLOR = 0x8,
+ BLEND_ONE_MINUS_DST_COLOR = 0x9,
+ BLEND_SRC_ALPHA_SATURATE = 0xa,
+ BLEND_BOTH_SRC_ALPHA = 0xb,
+ BLEND_BOTH_INV_SRC_ALPHA = 0xc,
+ BLEND_CONSTANT_COLOR = 0xd,
+ BLEND_ONE_MINUS_CONSTANT_COLOR = 0xe,
+ BLEND_SRC1_COLOR = 0xf,
+ BLEND_INV_SRC1_COLOR = 0x10,
+ BLEND_SRC1_ALPHA = 0x11,
+ BLEND_INV_SRC1_ALPHA = 0x12,
+ BLEND_CONSTANT_ALPHA = 0x13,
+ BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14,
+} BlendOp;
+typedef enum CombFunc {
+ COMB_DST_PLUS_SRC = 0x0,
+ COMB_SRC_MINUS_DST = 0x1,
+ COMB_MIN_DST_SRC = 0x2,
+ COMB_MAX_DST_SRC = 0x3,
+ COMB_DST_MINUS_SRC = 0x4,
+} CombFunc;
+typedef enum BlendOpt {
+ FORCE_OPT_AUTO = 0x0,
+ FORCE_OPT_DISABLE = 0x1,
+ FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x2,
+ FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x3,
+ FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x4,
+ FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x5,
+ FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x6,
+ FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x7,
+} BlendOpt;
+typedef enum CmaskCode {
+ CMASK_CLR00_F0 = 0x0,
+ CMASK_CLR00_F1 = 0x1,
+ CMASK_CLR00_F2 = 0x2,
+ CMASK_CLR00_FX = 0x3,
+ CMASK_CLR01_F0 = 0x4,
+ CMASK_CLR01_F1 = 0x5,
+ CMASK_CLR01_F2 = 0x6,
+ CMASK_CLR01_FX = 0x7,
+ CMASK_CLR10_F0 = 0x8,
+ CMASK_CLR10_F1 = 0x9,
+ CMASK_CLR10_F2 = 0xa,
+ CMASK_CLR10_FX = 0xb,
+ CMASK_CLR11_F0 = 0xc,
+ CMASK_CLR11_F1 = 0xd,
+ CMASK_CLR11_F2 = 0xe,
+ CMASK_CLR11_FX = 0xf,
+} CmaskCode;
+typedef enum CmaskAddr {
+ CMASK_ADDR_TILED = 0x0,
+ CMASK_ADDR_LINEAR = 0x1,
+ CMASK_ADDR_COMPATIBLE = 0x2,
+} CmaskAddr;
+typedef enum CBPerfSel {
+ CB_PERF_SEL_NONE = 0x0,
+ CB_PERF_SEL_BUSY = 0x1,
+ CB_PERF_SEL_CORE_SCLK_VLD = 0x2,
+ CB_PERF_SEL_REG_SCLK0_VLD = 0x3,
+ CB_PERF_SEL_REG_SCLK1_VLD = 0x4,
+ CB_PERF_SEL_DRAWN_QUAD = 0x5,
+ CB_PERF_SEL_DRAWN_PIXEL = 0x6,
+ CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x7,
+ CB_PERF_SEL_DRAWN_TILE = 0x8,
+ CB_PERF_SEL_DB_CB_TILE_VALID_READY = 0x9,
+ CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0xa,
+ CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 0xb,
+ CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 0xc,
+ CB_PERF_SEL_CM_FC_TILE_VALID_READY = 0xd,
+ CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 0xe,
+ CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 0xf,
+ CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 0x10,
+ CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 0x11,
+ CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 0x12,
+ CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 0x13,
+ CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 0x14,
+ CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 0x15,
+ CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 0x16,
+ CB_PERF_SEL_LQUAD_NO_TILE = 0x17,
+ CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 0x18,
+ CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 0x19,
+ CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 0x1a,
+ CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 0x1b,
+ CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 0x1c,
+ CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x1d,
+ CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR= 0x1e,
+ CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 0x1f,
+ CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 0x20,
+ CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK= 0x21,
+ CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 0x22,
+ CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 0x23,
+ CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 0x24,
+ CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 0x25,
+ CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 0x26,
+ CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 0x27,
+ CB_PERF_SEL_FOP_IN_VALID_READY = 0x28,
+ CB_PERF_SEL_FOP_IN_VALID_READYB = 0x29,
+ CB_PERF_SEL_FOP_IN_VALIDB_READY = 0x2a,
+ CB_PERF_SEL_FOP_IN_VALIDB_READYB = 0x2b,
+ CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 0x2c,
+ CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 0x2d,
+ CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 0x2e,
+ CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 0x2f,
+ CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 0x30,
+ CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 0x31,
+ CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 0x32,
+ CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 0x33,
+ CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 0x34,
+ CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 0x35,
+ CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 0x36,
+ CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 0x37,
+ CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 0x38,
+ CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 0x39,
+ CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 0x3a,
+ CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 0x3b,
+ CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 0x3c,
+ CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 0x3d,
+ CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 0x3e,
+ CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 0x3f,
+ CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 0x40,
+ CB_PERF_SEL_CM_CACHE_HIT = 0x41,
+ CB_PERF_SEL_CM_CACHE_TAG_MISS = 0x42,
+ CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 0x43,
+ CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 0x44,
+ CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x45,
+ CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x46,
+ CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x47,
+ CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 0x48,
+ CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 0x49,
+ CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 0x4a,
+ CB_PERF_SEL_CM_CACHE_STALL = 0x4b,
+ CB_PERF_SEL_CM_CACHE_FLUSH = 0x4c,
+ CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 0x4d,
+ CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 0x4e,
+ CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 0x4f,
+ CB_PERF_SEL_FC_CACHE_HIT = 0x50,
+ CB_PERF_SEL_FC_CACHE_TAG_MISS = 0x51,
+ CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 0x52,
+ CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 0x53,
+ CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x54,
+ CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x55,
+ CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x56,
+ CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 0x57,
+ CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 0x58,
+ CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 0x59,
+ CB_PERF_SEL_FC_CACHE_STALL = 0x5a,
+ CB_PERF_SEL_FC_CACHE_FLUSH = 0x5b,
+ CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 0x5c,
+ CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 0x5d,
+ CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 0x5e,
+ CB_PERF_SEL_CC_CACHE_HIT = 0x5f,
+ CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x60,
+ CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x61,
+ CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 0x62,
+ CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x63,
+ CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x64,
+ CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x65,
+ CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x66,
+ CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x67,
+ CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x68,
+ CB_PERF_SEL_CC_CACHE_STALL = 0x69,
+ CB_PERF_SEL_CC_CACHE_FLUSH = 0x6a,
+ CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 0x6b,
+ CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x6c,
+ CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x6d,
+ CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x6e,
+ CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 0x6f,
+ CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 0x70,
+ CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 0x71,
+ CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 0x72,
+ CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 0x73,
+ CB_PERF_SEL_CM_MC_WRITE_REQUEST = 0x74,
+ CB_PERF_SEL_FC_MC_WRITE_REQUEST = 0x75,
+ CB_PERF_SEL_CC_MC_WRITE_REQUEST = 0x76,
+ CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 0x77,
+ CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x78,
+ CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x79,
+ CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 0x7a,
+ CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 0x7b,
+ CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 0x7c,
+ CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 0x7d,
+ CB_PERF_SEL_CM_MC_READ_REQUEST = 0x7e,
+ CB_PERF_SEL_FC_MC_READ_REQUEST = 0x7f,
+ CB_PERF_SEL_CC_MC_READ_REQUEST = 0x80,
+ CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 0x81,
+ CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 0x82,
+ CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x83,
+ CB_PERF_SEL_CM_TQ_FULL = 0x84,
+ CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 0x85,
+ CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 0x86,
+ CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 0x87,
+ CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 0x88,
+ CB_PERF_SEL_FOP_FMASK_RAW_STALL = 0x89,
+ CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 0x8a,
+ CB_PERF_SEL_CC_SF_FULL = 0x8b,
+ CB_PERF_SEL_CC_RB_FULL = 0x8c,
+ CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 0x8d,
+ CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 0x8e,
+ CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 0x8f,
+ CB_PERF_SEL_EVENT = 0x90,
+ CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 0x91,
+ CB_PERF_SEL_EVENT_CONTEXT_DONE = 0x92,
+ CB_PERF_SEL_EVENT_CACHE_FLUSH = 0x93,
+ CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x94,
+ CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x95,
+ CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x96,
+ CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 0x97,
+ CB_PERF_SEL_CC_SURFACE_SYNC = 0x98,
+ CB_PERF_SEL_CMASK_READ_DATA_0xC = 0x99,
+ CB_PERF_SEL_CMASK_READ_DATA_0xD = 0x9a,
+ CB_PERF_SEL_CMASK_READ_DATA_0xE = 0x9b,
+ CB_PERF_SEL_CMASK_READ_DATA_0xF = 0x9c,
+ CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 0x9d,
+ CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 0x9e,
+ CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 0x9f,
+ CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 0xa0,
+ CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 0xa1,
+ CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 0xa2,
+ CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 0xa3,
+ CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 0xa4,
+ CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 0xa5,
+ CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 0xa6,
+ CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 0xa7,
+ CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 0xa8,
+ CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 0xa9,
+ CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 0xaa,
+ CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 0xab,
+ CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 0xac,
+ CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 0xad,
+ CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 0xae,
+ CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 0xaf,
+ CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 0xb0,
+ CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 0xb1,
+ CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 0xb2,
+ CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 0xb3,
+ CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 0xb4,
+ CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 0xb5,
+ CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 0xb6,
+ CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 0xb7,
+ CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 0xb8,
+ CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 0xb9,
+ CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 0xba,
+ CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 0xbb,
+ CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 0xbc,
+ CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 0xbd,
+ CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 0xbe,
+ CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 0xbf,
+ CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 0xc0,
+ CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 0xc1,
+ CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 0xc2,
+ CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 0xc3,
+ CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 0xc4,
+ CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 0xc5,
+ CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 0xc6,
+ CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 0xc7,
+ CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 0xc8,
+ CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 0xc9,
+ CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 0xca,
+ CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 0xcb,
+ CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 0xcc,
+ CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 0xcd,
+ CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 0xce,
+ CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 0xcf,
+ CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 0xd0,
+ CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 0xd1,
+ CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 0xd2,
+ CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 0xd3,
+ CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 0xd4,
+ CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED= 0xd5,
+ CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED= 0xd6,
+ CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 0xd7,
+ CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0xd8,
+ CB_PERF_SEL_DRAWN_BUSY = 0xd9,
+ CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 0xda,
+ CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 0xdb,
+ CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 0xdc,
+ CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 0xdd,
+ CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED= 0xde,
+ CB_PERF_SEL_FC_SEQUENCER_CLEAR = 0xdf,
+ CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 0xe0,
+ CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 0xe1,
+ CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE= 0xe2,
+ CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL = 0xe3,
+ CB_PERF_SEL_FC_DOC_IS_STALLED = 0xe4,
+ CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED = 0xe5,
+ CB_PERF_SEL_FC_DOC_MRTS_COMBINED = 0xe6,
+ CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS = 0xe7,
+ CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT = 0xe8,
+ CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS = 0xe9,
+ CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT = 0xea,
+ CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL = 0xeb,
+ CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR = 0xec,
+ CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS = 0xed,
+ CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS = 0xee,
+ CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS = 0xef,
+ CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS = 0xf0,
+ CB_PERF_SEL_FC_DCC_CACHE_HIT = 0xf1,
+ CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS = 0xf2,
+ CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS = 0xf3,
+ CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL = 0xf4,
+ CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0xf5,
+ CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL= 0xf6,
+ CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0xf7,
+ CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL = 0xf8,
+ CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL = 0xf9,
+ CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL = 0xfa,
+ CB_PERF_SEL_FC_DCC_CACHE_STALL = 0xfb,
+ CB_PERF_SEL_FC_DCC_CACHE_FLUSH = 0xfc,
+ CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED = 0xfd,
+ CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED = 0xfe,
+ CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 0xff,
+ CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT = 0x100,
+ CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST = 0x101,
+ CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT = 0x102,
+ CB_PERF_SEL_FC_MC_DCC_READ_REQUEST = 0x103,
+ CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT = 0x104,
+ CB_PERF_SEL_CC_DCC_RDREQ_STALL = 0x105,
+ CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN = 0x106,
+ CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT = 0x107,
+ CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN = 0x108,
+ CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT = 0x109,
+ CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR = 0x10a,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1 = 0x10b,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2= 0x10c,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x10d,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1= 0x10e,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1= 0x10f,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2= 0x110,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1= 0x111,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x112,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x113,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1= 0x114,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2= 0x115,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2= 0x116,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2= 0x117,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x118,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1= 0x119,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1 = 0x11a,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2= 0x11b,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3= 0x11c,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4= 0x11d,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1= 0x11e,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2 = 0x11f,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3= 0x120,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4= 0x121,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1= 0x122,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2= 0x123,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3 = 0x124,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4= 0x125,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1= 0x126,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2= 0x127,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3= 0x128,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1= 0x129,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2= 0x12a,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3= 0x12b,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4= 0x12c,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1= 0x12d,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2= 0x12e,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3= 0x12f,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4= 0x130,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1= 0x131,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2= 0x132,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3= 0x133,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4= 0x134,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1= 0x135,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2= 0x136,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3= 0x137,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1= 0x138,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1= 0x139,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1= 0x13a,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1= 0x13b,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1= 0x13c,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1= 0x13d,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1= 0x13e,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1= 0x13f,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2= 0x140,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2= 0x141,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2= 0x142,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2= 0x143,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2= 0x144,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2= 0x145,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2= 0x146,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1= 0x147,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1= 0x148,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1= 0x149,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1= 0x14a,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2= 0x14b,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2= 0x14c,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2= 0x14d,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2= 0x14e,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x14f,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2= 0x150,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2= 0x151,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x152,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1= 0x153,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1= 0x154,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1= 0x155,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1= 0x156,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2= 0x157,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3= 0x158,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4= 0x159,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5= 0x15a,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6= 0x15b,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0 = 0x15c,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1 = 0x15d,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1= 0x15e,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2= 0x15f,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3= 0x160,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4= 0x161,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5= 0x162,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0 = 0x163,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1 = 0x164,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1= 0x165,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1= 0x166,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1= 0x167,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1= 0x168,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1= 0x169,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1= 0x16a,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1 = 0x16b,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1 = 0x16c,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2= 0x16d,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2= 0x16e,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2= 0x16f,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2= 0x170,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2= 0x171,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2 = 0x172,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2 = 0x173,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1 = 0x174,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2 = 0x175,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3 = 0x176,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4 = 0x177,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5 = 0x178,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6 = 0x179,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7 = 0x17a,
+ CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED = 0x17b,
+ CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1 = 0x17c,
+ CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1 = 0x17d,
+ CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2 = 0x17e,
+ CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3 = 0x17f,
+ CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1 = 0x180,
+ CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2 = 0x181,
+ CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3 = 0x182,
+ CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4 = 0x183,
+ CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5 = 0x184,
+ CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1 = 0x185,
+ CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2 = 0x186,
+ CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3 = 0x187,
+ CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4 = 0x188,
+ CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5 = 0x189,
+ CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6 = 0x18a,
+ CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7 = 0x18b,
+} CBPerfSel;
+typedef enum CBPerfOpFilterSel {
+ CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x0,
+ CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x1,
+ CB_PERF_OP_FILTER_SEL_RESOLVE = 0x2,
+ CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x3,
+ CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x4,
+ CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x5,
+} CBPerfOpFilterSel;
+typedef enum CBPerfClearFilterSel {
+ CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x0,
+ CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x1,
+} CBPerfClearFilterSel;
+typedef enum CP_RING_ID {
+ RINGID0 = 0x0,
+ RINGID1 = 0x1,
+ RINGID2 = 0x2,
+ RINGID3 = 0x3,
+} CP_RING_ID;
+typedef enum CP_PIPE_ID {
+ PIPE_ID0 = 0x0,
+ PIPE_ID1 = 0x1,
+ PIPE_ID2 = 0x2,
+ PIPE_ID3 = 0x3,
+} CP_PIPE_ID;
+typedef enum CP_ME_ID {
+ ME_ID0 = 0x0,
+ ME_ID1 = 0x1,
+ ME_ID2 = 0x2,
+ ME_ID3 = 0x3,
+} CP_ME_ID;
+typedef enum SPM_PERFMON_STATE {
+ STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x0,
+ STRM_PERFMON_STATE_START_COUNTING = 0x1,
+ STRM_PERFMON_STATE_STOP_COUNTING = 0x2,
+ STRM_PERFMON_STATE_RESERVED_3 = 0x3,
+ STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x4,
+ STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5,
+} SPM_PERFMON_STATE;
+typedef enum CP_PERFMON_STATE {
+ CP_PERFMON_STATE_DISABLE_AND_RESET = 0x0,
+ CP_PERFMON_STATE_START_COUNTING = 0x1,
+ CP_PERFMON_STATE_STOP_COUNTING = 0x2,
+ CP_PERFMON_STATE_RESERVED_3 = 0x3,
+ CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x4,
+ CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5,
+} CP_PERFMON_STATE;
+typedef enum CP_PERFMON_ENABLE_MODE {
+ CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x0,
+ CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x1,
+ CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x2,
+ CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x3,
+} CP_PERFMON_ENABLE_MODE;
+typedef enum CPG_PERFCOUNT_SEL {
+ CPG_PERF_SEL_ALWAYS_COUNT = 0x0,
+ CPG_PERF_SEL_RBIU_FIFO_FULL = 0x1,
+ CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x2,
+ CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 0x3,
+ CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x4,
+ CPG_PERF_SEL_ME_PARSER_BUSY = 0x5,
+ CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x6,
+ CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x7,
+ CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x8,
+ CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x9,
+ CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0xa,
+ CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0xb,
+ CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0xc,
+ CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0xd,
+ CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0xe,
+ CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0xf,
+ CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x10,
+ CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x11,
+ CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x12,
+ CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x13,
+ CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x14,
+ CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x15,
+ CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x16,
+ CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x17,
+ CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x18,
+ CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x19,
+ CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x1a,
+ CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x1b,
+ CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x1c,
+ CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x1d,
+ CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x1e,
+ CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x1f,
+ CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x20,
+ CPG_PERF_SEL_REGISTER_CLK_VALID = 0x21,
+ CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT = 0x22,
+ CPG_PERF_SEL_MIU_READ_REQUEST_SENT = 0x23,
+ CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x24,
+ CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x25,
+ CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x26,
+ CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x27,
+ CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 0x28,
+ CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x29,
+ CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x2a,
+ CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x2b,
+ CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x2c,
+ CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x2d,
+ CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE = 0x2e,
+ CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS = 0x2f,
+ CPG_PERF_SEL_ATCL1_STALL_ON_TRANSLATION = 0x30,
+} CPG_PERFCOUNT_SEL;
+typedef enum CPF_PERFCOUNT_SEL {
+ CPF_PERF_SEL_ALWAYS_COUNT = 0x0,
+ CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 0x1,
+ CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x2,
+ CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x3,
+ CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x4,
+ CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x5,
+ CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x6,
+ CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 0x7,
+ CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 0x8,
+ CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 0x9,
+ CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0xa,
+ CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0xb,
+ CPF_PERF_SEL_GRBM_DWORDS_SENT = 0xc,
+ CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0xd,
+ CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0xe,
+ CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND = 0xf,
+ CPF_PERF_SEL_MIU_READ_REQUEST_SEND = 0x10,
+ CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE = 0x11,
+ CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS = 0x12,
+ CPF_PERF_SEL_ATCL1_STALL_ON_TRANSLATION = 0x13,
+} CPF_PERFCOUNT_SEL;
+typedef enum CPC_PERFCOUNT_SEL {
+ CPC_PERF_SEL_ALWAYS_COUNT = 0x0,
+ CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x1,
+ CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x2,
+ CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 0x3,
+ CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 0x4,
+ CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x5,
+ CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x6,
+ CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x7,
+ CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x8,
+ CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ = 0x9,
+ CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0xa,
+ CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0xb,
+ CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0xc,
+ CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0xd,
+ CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0xe,
+ CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0xf,
+ CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x10,
+ CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ = 0x11,
+ CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE = 0x12,
+ CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x13,
+ CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x14,
+ CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x15,
+ CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE = 0x16,
+ CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS = 0x17,
+ CPC_PERF_SEL_ATCL1_STALL_ON_TRANSLATION = 0x18,
+} CPC_PERFCOUNT_SEL;
+typedef enum CP_ALPHA_TAG_RAM_SEL {
+ CPG_TAG_RAM = 0x0,
+ CPC_TAG_RAM = 0x1,
+ CPF_TAG_RAM = 0x2,
+ RSV_TAG_RAM = 0x3,
+} CP_ALPHA_TAG_RAM_SEL;
+#define SEM_ECC_ERROR 0x0
+#define SEM_RESERVED 0x1
+#define SEM_FAILED 0x2
+#define SEM_PASSED 0x3
+#define IQ_QUEUE_SLEEP 0x0
+#define IQ_OFFLOAD_RETRY 0x1
+#define IQ_SCH_WAVE_MSG 0x2
+#define IQ_SEM_REARM 0x3
+#define IQ_DEQUEUE_RETRY 0x4
+#define IQ_INTR_TYPE_PQ 0x0
+#define IQ_INTR_TYPE_IB 0x1
+#define IQ_INTR_TYPE_MQD 0x2
+#define VMID_SZ 0x4
+#define CONFIG_SPACE_START 0x2000
+#define CONFIG_SPACE_END 0x9fff
+#define CONFIG_SPACE1_START 0x2000
+#define CONFIG_SPACE1_END 0x2bff
+#define CONFIG_SPACE2_START 0x3000
+#define CONFIG_SPACE2_END 0x9fff
+#define UCONFIG_SPACE_START 0xc000
+#define UCONFIG_SPACE_END 0xffff
+#define PERSISTENT_SPACE_START 0x2c00
+#define PERSISTENT_SPACE_END 0x2fff
+#define CONTEXT_SPACE_START 0xa000
+#define CONTEXT_SPACE_END 0xbfff
+typedef enum ForceControl {
+ FORCE_OFF = 0x0,
+ FORCE_ENABLE = 0x1,
+ FORCE_DISABLE = 0x2,
+ FORCE_RESERVED = 0x3,
+} ForceControl;
+typedef enum ZSamplePosition {
+ Z_SAMPLE_CENTER = 0x0,
+ Z_SAMPLE_CENTROID = 0x1,
+} ZSamplePosition;
+typedef enum ZOrder {
+ LATE_Z = 0x0,
+ EARLY_Z_THEN_LATE_Z = 0x1,
+ RE_Z = 0x2,
+ EARLY_Z_THEN_RE_Z = 0x3,
+} ZOrder;
+typedef enum ZpassControl {
+ ZPASS_DISABLE = 0x0,
+ ZPASS_SAMPLES = 0x1,
+ ZPASS_PIXELS = 0x2,
+} ZpassControl;
+typedef enum ZModeForce {
+ NO_FORCE = 0x0,
+ FORCE_EARLY_Z = 0x1,
+ FORCE_LATE_Z = 0x2,
+ FORCE_RE_Z = 0x3,
+} ZModeForce;
+typedef enum ZLimitSumm {
+ FORCE_SUMM_OFF = 0x0,
+ FORCE_SUMM_MINZ = 0x1,
+ FORCE_SUMM_MAXZ = 0x2,
+ FORCE_SUMM_BOTH = 0x3,
+} ZLimitSumm;
+typedef enum CompareFrag {
+ FRAG_NEVER = 0x0,
+ FRAG_LESS = 0x1,
+ FRAG_EQUAL = 0x2,
+ FRAG_LEQUAL = 0x3,
+ FRAG_GREATER = 0x4,
+ FRAG_NOTEQUAL = 0x5,
+ FRAG_GEQUAL = 0x6,
+ FRAG_ALWAYS = 0x7,
+} CompareFrag;
+typedef enum StencilOp {
+ STENCIL_KEEP = 0x0,
+ STENCIL_ZERO = 0x1,
+ STENCIL_ONES = 0x2,
+ STENCIL_REPLACE_TEST = 0x3,
+ STENCIL_REPLACE_OP = 0x4,
+ STENCIL_ADD_CLAMP = 0x5,
+ STENCIL_SUB_CLAMP = 0x6,
+ STENCIL_INVERT = 0x7,
+ STENCIL_ADD_WRAP = 0x8,
+ STENCIL_SUB_WRAP = 0x9,
+ STENCIL_AND = 0xa,
+ STENCIL_OR = 0xb,
+ STENCIL_XOR = 0xc,
+ STENCIL_NAND = 0xd,
+ STENCIL_NOR = 0xe,
+ STENCIL_XNOR = 0xf,
+} StencilOp;
+typedef enum ConservativeZExport {
+ EXPORT_ANY_Z = 0x0,
+ EXPORT_LESS_THAN_Z = 0x1,
+ EXPORT_GREATER_THAN_Z = 0x2,
+ EXPORT_RESERVED = 0x3,
+} ConservativeZExport;
+typedef enum DbPSLControl {
+ PSLC_AUTO = 0x0,
+ PSLC_ON_HANG_ONLY = 0x1,
+ PSLC_ASAP = 0x2,
+ PSLC_COUNTDOWN = 0x3,
+} DbPSLControl;
+typedef enum PerfCounter_Vals {
+ DB_PERF_SEL_SC_DB_tile_sends = 0x0,
+ DB_PERF_SEL_SC_DB_tile_busy = 0x1,
+ DB_PERF_SEL_SC_DB_tile_stalls = 0x2,
+ DB_PERF_SEL_SC_DB_tile_events = 0x3,
+ DB_PERF_SEL_SC_DB_tile_tiles = 0x4,
+ DB_PERF_SEL_SC_DB_tile_covered = 0x5,
+ DB_PERF_SEL_hiz_tc_read_starved = 0x6,
+ DB_PERF_SEL_hiz_tc_write_stall = 0x7,
+ DB_PERF_SEL_hiz_qtiles_culled = 0x8,
+ DB_PERF_SEL_his_qtiles_culled = 0x9,
+ DB_PERF_SEL_DB_SC_tile_sends = 0xa,
+ DB_PERF_SEL_DB_SC_tile_busy = 0xb,
+ DB_PERF_SEL_DB_SC_tile_stalls = 0xc,
+ DB_PERF_SEL_DB_SC_tile_df_stalls = 0xd,
+ DB_PERF_SEL_DB_SC_tile_tiles = 0xe,
+ DB_PERF_SEL_DB_SC_tile_culled = 0xf,
+ DB_PERF_SEL_DB_SC_tile_hier_kill = 0x10,
+ DB_PERF_SEL_DB_SC_tile_fast_ops = 0x11,
+ DB_PERF_SEL_DB_SC_tile_no_ops = 0x12,
+ DB_PERF_SEL_DB_SC_tile_tile_rate = 0x13,
+ DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x14,
+ DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x15,
+ DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x16,
+ DB_PERF_SEL_SC_DB_quad_sends = 0x17,
+ DB_PERF_SEL_SC_DB_quad_busy = 0x18,
+ DB_PERF_SEL_SC_DB_quad_squads = 0x19,
+ DB_PERF_SEL_SC_DB_quad_tiles = 0x1a,
+ DB_PERF_SEL_SC_DB_quad_pixels = 0x1b,
+ DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x1c,
+ DB_PERF_SEL_DB_SC_quad_sends = 0x1d,
+ DB_PERF_SEL_DB_SC_quad_busy = 0x1e,
+ DB_PERF_SEL_DB_SC_quad_stalls = 0x1f,
+ DB_PERF_SEL_DB_SC_quad_tiles = 0x20,
+ DB_PERF_SEL_DB_SC_quad_lit_quad = 0x21,
+ DB_PERF_SEL_DB_CB_tile_sends = 0x22,
+ DB_PERF_SEL_DB_CB_tile_busy = 0x23,
+ DB_PERF_SEL_DB_CB_tile_stalls = 0x24,
+ DB_PERF_SEL_SX_DB_quad_sends = 0x25,
+ DB_PERF_SEL_SX_DB_quad_busy = 0x26,
+ DB_PERF_SEL_SX_DB_quad_stalls = 0x27,
+ DB_PERF_SEL_SX_DB_quad_quads = 0x28,
+ DB_PERF_SEL_SX_DB_quad_pixels = 0x29,
+ DB_PERF_SEL_SX_DB_quad_exports = 0x2a,
+ DB_PERF_SEL_SH_quads_outstanding_sum = 0x2b,
+ DB_PERF_SEL_DB_CB_lquad_sends = 0x2c,
+ DB_PERF_SEL_DB_CB_lquad_busy = 0x2d,
+ DB_PERF_SEL_DB_CB_lquad_stalls = 0x2e,
+ DB_PERF_SEL_DB_CB_lquad_quads = 0x2f,
+ DB_PERF_SEL_tile_rd_sends = 0x30,
+ DB_PERF_SEL_mi_tile_rd_outstanding_sum = 0x31,
+ DB_PERF_SEL_quad_rd_sends = 0x32,
+ DB_PERF_SEL_quad_rd_busy = 0x33,
+ DB_PERF_SEL_quad_rd_mi_stall = 0x34,
+ DB_PERF_SEL_quad_rd_rw_collision = 0x35,
+ DB_PERF_SEL_quad_rd_tag_stall = 0x36,
+ DB_PERF_SEL_quad_rd_32byte_reqs = 0x37,
+ DB_PERF_SEL_quad_rd_panic = 0x38,
+ DB_PERF_SEL_mi_quad_rd_outstanding_sum = 0x39,
+ DB_PERF_SEL_quad_rdret_sends = 0x3a,
+ DB_PERF_SEL_quad_rdret_busy = 0x3b,
+ DB_PERF_SEL_tile_wr_sends = 0x3c,
+ DB_PERF_SEL_tile_wr_acks = 0x3d,
+ DB_PERF_SEL_mi_tile_wr_outstanding_sum = 0x3e,
+ DB_PERF_SEL_quad_wr_sends = 0x3f,
+ DB_PERF_SEL_quad_wr_busy = 0x40,
+ DB_PERF_SEL_quad_wr_mi_stall = 0x41,
+ DB_PERF_SEL_quad_wr_coherency_stall = 0x42,
+ DB_PERF_SEL_quad_wr_acks = 0x43,
+ DB_PERF_SEL_mi_quad_wr_outstanding_sum = 0x44,
+ DB_PERF_SEL_Tile_Cache_misses = 0x45,
+ DB_PERF_SEL_Tile_Cache_hits = 0x46,
+ DB_PERF_SEL_Tile_Cache_flushes = 0x47,
+ DB_PERF_SEL_Tile_Cache_surface_stall = 0x48,
+ DB_PERF_SEL_Tile_Cache_starves = 0x49,
+ DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x4a,
+ DB_PERF_SEL_tcp_dispatcher_reads = 0x4b,
+ DB_PERF_SEL_tcp_prefetcher_reads = 0x4c,
+ DB_PERF_SEL_tcp_preloader_reads = 0x4d,
+ DB_PERF_SEL_tcp_dispatcher_flushes = 0x4e,
+ DB_PERF_SEL_tcp_prefetcher_flushes = 0x4f,
+ DB_PERF_SEL_tcp_preloader_flushes = 0x50,
+ DB_PERF_SEL_Depth_Tile_Cache_sends = 0x51,
+ DB_PERF_SEL_Depth_Tile_Cache_busy = 0x52,
+ DB_PERF_SEL_Depth_Tile_Cache_starves = 0x53,
+ DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x54,
+ DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x55,
+ DB_PERF_SEL_Depth_Tile_Cache_misses = 0x56,
+ DB_PERF_SEL_Depth_Tile_Cache_hits = 0x57,
+ DB_PERF_SEL_Depth_Tile_Cache_flushes = 0x58,
+ DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 0x59,
+ DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x5a,
+ DB_PERF_SEL_Depth_Tile_Cache_event = 0x5b,
+ DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 0x5c,
+ DB_PERF_SEL_Depth_Tile_Cache_data_frees = 0x5d,
+ DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x5e,
+ DB_PERF_SEL_Stencil_Cache_misses = 0x5f,
+ DB_PERF_SEL_Stencil_Cache_hits = 0x60,
+ DB_PERF_SEL_Stencil_Cache_flushes = 0x61,
+ DB_PERF_SEL_Stencil_Cache_starves = 0x62,
+ DB_PERF_SEL_Stencil_Cache_frees = 0x63,
+ DB_PERF_SEL_Z_Cache_separate_Z_misses = 0x64,
+ DB_PERF_SEL_Z_Cache_separate_Z_hits = 0x65,
+ DB_PERF_SEL_Z_Cache_separate_Z_flushes = 0x66,
+ DB_PERF_SEL_Z_Cache_separate_Z_starves = 0x67,
+ DB_PERF_SEL_Z_Cache_pmask_misses = 0x68,
+ DB_PERF_SEL_Z_Cache_pmask_hits = 0x69,
+ DB_PERF_SEL_Z_Cache_pmask_flushes = 0x6a,
+ DB_PERF_SEL_Z_Cache_pmask_starves = 0x6b,
+ DB_PERF_SEL_Z_Cache_frees = 0x6c,
+ DB_PERF_SEL_Plane_Cache_misses = 0x6d,
+ DB_PERF_SEL_Plane_Cache_hits = 0x6e,
+ DB_PERF_SEL_Plane_Cache_flushes = 0x6f,
+ DB_PERF_SEL_Plane_Cache_starves = 0x70,
+ DB_PERF_SEL_Plane_Cache_frees = 0x71,
+ DB_PERF_SEL_flush_expanded_stencil = 0x72,
+ DB_PERF_SEL_flush_compressed_stencil = 0x73,
+ DB_PERF_SEL_flush_single_stencil = 0x74,
+ DB_PERF_SEL_planes_flushed = 0x75,
+ DB_PERF_SEL_flush_1plane = 0x76,
+ DB_PERF_SEL_flush_2plane = 0x77,
+ DB_PERF_SEL_flush_3plane = 0x78,
+ DB_PERF_SEL_flush_4plane = 0x79,
+ DB_PERF_SEL_flush_5plane = 0x7a,
+ DB_PERF_SEL_flush_6plane = 0x7b,
+ DB_PERF_SEL_flush_7plane = 0x7c,
+ DB_PERF_SEL_flush_8plane = 0x7d,
+ DB_PERF_SEL_flush_9plane = 0x7e,
+ DB_PERF_SEL_flush_10plane = 0x7f,
+ DB_PERF_SEL_flush_11plane = 0x80,
+ DB_PERF_SEL_flush_12plane = 0x81,
+ DB_PERF_SEL_flush_13plane = 0x82,
+ DB_PERF_SEL_flush_14plane = 0x83,
+ DB_PERF_SEL_flush_15plane = 0x84,
+ DB_PERF_SEL_flush_16plane = 0x85,
+ DB_PERF_SEL_flush_expanded_z = 0x86,
+ DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x87,
+ DB_PERF_SEL_reZ_waiting_for_postZ_done = 0x88,
+ DB_PERF_SEL_dk_tile_sends = 0x89,
+ DB_PERF_SEL_dk_tile_busy = 0x8a,
+ DB_PERF_SEL_dk_tile_quad_starves = 0x8b,
+ DB_PERF_SEL_dk_tile_stalls = 0x8c,
+ DB_PERF_SEL_dk_squad_sends = 0x8d,
+ DB_PERF_SEL_dk_squad_busy = 0x8e,
+ DB_PERF_SEL_dk_squad_stalls = 0x8f,
+ DB_PERF_SEL_Op_Pipe_Busy = 0x90,
+ DB_PERF_SEL_Op_Pipe_MC_Read_stall = 0x91,
+ DB_PERF_SEL_qc_busy = 0x92,
+ DB_PERF_SEL_qc_xfc = 0x93,
+ DB_PERF_SEL_qc_conflicts = 0x94,
+ DB_PERF_SEL_qc_full_stall = 0x95,
+ DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x96,
+ DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x97,
+ DB_PERF_SEL_tsc_insert_summarize_stall = 0x98,
+ DB_PERF_SEL_tl_busy = 0x99,
+ DB_PERF_SEL_tl_dtc_read_starved = 0x9a,
+ DB_PERF_SEL_tl_z_fetch_stall = 0x9b,
+ DB_PERF_SEL_tl_stencil_stall = 0x9c,
+ DB_PERF_SEL_tl_z_decompress_stall = 0x9d,
+ DB_PERF_SEL_tl_stencil_locked_stall = 0x9e,
+ DB_PERF_SEL_tl_events = 0x9f,
+ DB_PERF_SEL_tl_summarize_squads = 0xa0,
+ DB_PERF_SEL_tl_flush_expand_squads = 0xa1,
+ DB_PERF_SEL_tl_expand_squads = 0xa2,
+ DB_PERF_SEL_tl_preZ_squads = 0xa3,
+ DB_PERF_SEL_tl_postZ_squads = 0xa4,
+ DB_PERF_SEL_tl_preZ_noop_squads = 0xa5,
+ DB_PERF_SEL_tl_postZ_noop_squads = 0xa6,
+ DB_PERF_SEL_tl_tile_ops = 0xa7,
+ DB_PERF_SEL_tl_in_xfc = 0xa8,
+ DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0xa9,
+ DB_PERF_SEL_tl_in_fast_z_stall = 0xaa,
+ DB_PERF_SEL_tl_out_xfc = 0xab,
+ DB_PERF_SEL_tl_out_squads = 0xac,
+ DB_PERF_SEL_zf_plane_multicycle = 0xad,
+ DB_PERF_SEL_PostZ_Samples_passing_Z = 0xae,
+ DB_PERF_SEL_PostZ_Samples_failing_Z = 0xaf,
+ DB_PERF_SEL_PostZ_Samples_failing_S = 0xb0,
+ DB_PERF_SEL_PreZ_Samples_passing_Z = 0xb1,
+ DB_PERF_SEL_PreZ_Samples_failing_Z = 0xb2,
+ DB_PERF_SEL_PreZ_Samples_failing_S = 0xb3,
+ DB_PERF_SEL_ts_tc_update_stall = 0xb4,
+ DB_PERF_SEL_sc_kick_start = 0xb5,
+ DB_PERF_SEL_sc_kick_end = 0xb6,
+ DB_PERF_SEL_clock_reg_active = 0xb7,
+ DB_PERF_SEL_clock_main_active = 0xb8,
+ DB_PERF_SEL_clock_mem_export_active = 0xb9,
+ DB_PERF_SEL_esr_ps_out_busy = 0xba,
+ DB_PERF_SEL_esr_ps_lqf_busy = 0xbb,
+ DB_PERF_SEL_esr_ps_lqf_stall = 0xbc,
+ DB_PERF_SEL_etr_out_send = 0xbd,
+ DB_PERF_SEL_etr_out_busy = 0xbe,
+ DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0xbf,
+ DB_PERF_SEL_etr_out_cb_tile_stall = 0xc0,
+ DB_PERF_SEL_etr_out_esr_stall = 0xc1,
+ DB_PERF_SEL_esr_ps_sqq_busy = 0xc2,
+ DB_PERF_SEL_esr_ps_sqq_stall = 0xc3,
+ DB_PERF_SEL_esr_eot_fwd_busy = 0xc4,
+ DB_PERF_SEL_esr_eot_fwd_holding_squad = 0xc5,
+ DB_PERF_SEL_esr_eot_fwd_forward = 0xc6,
+ DB_PERF_SEL_esr_sqq_zi_busy = 0xc7,
+ DB_PERF_SEL_esr_sqq_zi_stall = 0xc8,
+ DB_PERF_SEL_postzl_sq_pt_busy = 0xc9,
+ DB_PERF_SEL_postzl_sq_pt_stall = 0xca,
+ DB_PERF_SEL_postzl_se_busy = 0xcb,
+ DB_PERF_SEL_postzl_se_stall = 0xcc,
+ DB_PERF_SEL_postzl_partial_launch = 0xcd,
+ DB_PERF_SEL_postzl_full_launch = 0xce,
+ DB_PERF_SEL_postzl_partial_waiting = 0xcf,
+ DB_PERF_SEL_postzl_tile_mem_stall = 0xd0,
+ DB_PERF_SEL_postzl_tile_init_stall = 0xd1,
+ DB_PEFF_SEL_prezl_tile_mem_stall = 0xd2,
+ DB_PERF_SEL_prezl_tile_init_stall = 0xd3,
+ DB_PERF_SEL_dtt_sm_clash_stall = 0xd4,
+ DB_PERF_SEL_dtt_sm_slot_stall = 0xd5,
+ DB_PERF_SEL_dtt_sm_miss_stall = 0xd6,
+ DB_PERF_SEL_mi_rdreq_busy = 0xd7,
+ DB_PERF_SEL_mi_rdreq_stall = 0xd8,
+ DB_PERF_SEL_mi_wrreq_busy = 0xd9,
+ DB_PERF_SEL_mi_wrreq_stall = 0xda,
+ DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0xdb,
+ DB_PERF_SEL_dkg_tile_rate_tile = 0xdc,
+ DB_PERF_SEL_prezl_src_in_sends = 0xdd,
+ DB_PERF_SEL_prezl_src_in_stall = 0xde,
+ DB_PERF_SEL_prezl_src_in_squads = 0xdf,
+ DB_PERF_SEL_prezl_src_in_squads_unrolled = 0xe0,
+ DB_PERF_SEL_prezl_src_in_tile_rate = 0xe1,
+ DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0xe2,
+ DB_PERF_SEL_prezl_src_out_stall = 0xe3,
+ DB_PERF_SEL_postzl_src_in_sends = 0xe4,
+ DB_PERF_SEL_postzl_src_in_stall = 0xe5,
+ DB_PERF_SEL_postzl_src_in_squads = 0xe6,
+ DB_PERF_SEL_postzl_src_in_squads_unrolled = 0xe7,
+ DB_PERF_SEL_postzl_src_in_tile_rate = 0xe8,
+ DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0xe9,
+ DB_PERF_SEL_postzl_src_out_stall = 0xea,
+ DB_PERF_SEL_esr_ps_src_in_sends = 0xeb,
+ DB_PERF_SEL_esr_ps_src_in_stall = 0xec,
+ DB_PERF_SEL_esr_ps_src_in_squads = 0xed,
+ DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0xee,
+ DB_PERF_SEL_esr_ps_src_in_tile_rate = 0xef,
+ DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0xf0,
+ DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate= 0xf1,
+ DB_PERF_SEL_esr_ps_src_out_stall = 0xf2,
+ DB_PERF_SEL_depth_bounds_qtiles_culled = 0xf3,
+ DB_PERF_SEL_PreZ_Samples_failing_DB = 0xf4,
+ DB_PERF_SEL_PostZ_Samples_failing_DB = 0xf5,
+ DB_PERF_SEL_flush_compressed = 0xf6,
+ DB_PERF_SEL_flush_plane_le4 = 0xf7,
+ DB_PERF_SEL_tiles_z_fully_summarized = 0xf8,
+ DB_PERF_SEL_tiles_stencil_fully_summarized = 0xf9,
+ DB_PERF_SEL_tiles_z_clear_on_expclear = 0xfa,
+ DB_PERF_SEL_tiles_s_clear_on_expclear = 0xfb,
+ DB_PERF_SEL_tiles_decomp_on_expclear = 0xfc,
+ DB_PERF_SEL_tiles_compressed_to_decompressed = 0xfd,
+ DB_PERF_SEL_Op_Pipe_Prez_Busy = 0xfe,
+ DB_PERF_SEL_Op_Pipe_Postz_Busy = 0xff,
+ DB_PERF_SEL_di_dt_stall = 0x100,
+} PerfCounter_Vals;
+typedef enum RingCounterControl {
+ COUNTER_RING_SPLIT = 0x0,
+ COUNTER_RING_0 = 0x1,
+ COUNTER_RING_1 = 0x2,
+} RingCounterControl;
+typedef enum PixelPipeCounterId {
+ PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x0,
+ PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x1,
+ PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x2,
+ PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x3,
+ PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 0x4,
+ PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 0x5,
+ PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 0x6,
+ PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 0x7,
+} PixelPipeCounterId;
+typedef enum PixelPipeStride {
+ PIXEL_PIPE_STRIDE_32_BITS = 0x0,
+ PIXEL_PIPE_STRIDE_64_BITS = 0x1,
+ PIXEL_PIPE_STRIDE_128_BITS = 0x2,
+ PIXEL_PIPE_STRIDE_256_BITS = 0x3,
+} PixelPipeStride;
+typedef enum GB_EDC_DED_MODE {
+ GB_EDC_DED_MODE_LOG = 0x0,
+ GB_EDC_DED_MODE_HALT = 0x1,
+ GB_EDC_DED_MODE_INT_HALT = 0x2,
+} GB_EDC_DED_MODE;
+#define GB_TILING_CONFIG_TABLE_SIZE 0x20
+#define GB_TILING_CONFIG_MACROTABLE_SIZE 0x10
+typedef enum GRBM_PERF_SEL {
+ GRBM_PERF_SEL_COUNT = 0x0,
+ GRBM_PERF_SEL_USER_DEFINED = 0x1,
+ GRBM_PERF_SEL_GUI_ACTIVE = 0x2,
+ GRBM_PERF_SEL_CP_BUSY = 0x3,
+ GRBM_PERF_SEL_CP_COHER_BUSY = 0x4,
+ GRBM_PERF_SEL_CP_DMA_BUSY = 0x5,
+ GRBM_PERF_SEL_CB_BUSY = 0x6,
+ GRBM_PERF_SEL_DB_BUSY = 0x7,
+ GRBM_PERF_SEL_PA_BUSY = 0x8,
+ GRBM_PERF_SEL_SC_BUSY = 0x9,
+ GRBM_PERF_SEL_RESERVED_6 = 0xa,
+ GRBM_PERF_SEL_SPI_BUSY = 0xb,
+ GRBM_PERF_SEL_SX_BUSY = 0xc,
+ GRBM_PERF_SEL_TA_BUSY = 0xd,
+ GRBM_PERF_SEL_CB_CLEAN = 0xe,
+ GRBM_PERF_SEL_DB_CLEAN = 0xf,
+ GRBM_PERF_SEL_RESERVED_5 = 0x10,
+ GRBM_PERF_SEL_VGT_BUSY = 0x11,
+ GRBM_PERF_SEL_RESERVED_4 = 0x12,
+ GRBM_PERF_SEL_RESERVED_3 = 0x13,
+ GRBM_PERF_SEL_RESERVED_2 = 0x14,
+ GRBM_PERF_SEL_RESERVED_1 = 0x15,
+ GRBM_PERF_SEL_RESERVED_0 = 0x16,
+ GRBM_PERF_SEL_IA_BUSY = 0x17,
+ GRBM_PERF_SEL_IA_NO_DMA_BUSY = 0x18,
+ GRBM_PERF_SEL_GDS_BUSY = 0x19,
+ GRBM_PERF_SEL_BCI_BUSY = 0x1a,
+ GRBM_PERF_SEL_RLC_BUSY = 0x1b,
+ GRBM_PERF_SEL_TC_BUSY = 0x1c,
+ GRBM_PERF_SEL_CPG_BUSY = 0x1d,
+ GRBM_PERF_SEL_CPC_BUSY = 0x1e,
+ GRBM_PERF_SEL_CPF_BUSY = 0x1f,
+ GRBM_PERF_SEL_WD_BUSY = 0x20,
+ GRBM_PERF_SEL_WD_NO_DMA_BUSY = 0x21,
+} GRBM_PERF_SEL;
+typedef enum GRBM_SE0_PERF_SEL {
+ GRBM_SE0_PERF_SEL_COUNT = 0x0,
+ GRBM_SE0_PERF_SEL_USER_DEFINED = 0x1,
+ GRBM_SE0_PERF_SEL_CB_BUSY = 0x2,
+ GRBM_SE0_PERF_SEL_DB_BUSY = 0x3,
+ GRBM_SE0_PERF_SEL_SC_BUSY = 0x4,
+ GRBM_SE0_PERF_SEL_RESERVED_1 = 0x5,
+ GRBM_SE0_PERF_SEL_SPI_BUSY = 0x6,
+ GRBM_SE0_PERF_SEL_SX_BUSY = 0x7,
+ GRBM_SE0_PERF_SEL_TA_BUSY = 0x8,
+ GRBM_SE0_PERF_SEL_CB_CLEAN = 0x9,
+ GRBM_SE0_PERF_SEL_DB_CLEAN = 0xa,
+ GRBM_SE0_PERF_SEL_RESERVED_0 = 0xb,
+ GRBM_SE0_PERF_SEL_PA_BUSY = 0xc,
+ GRBM_SE0_PERF_SEL_VGT_BUSY = 0xd,
+ GRBM_SE0_PERF_SEL_BCI_BUSY = 0xe,
+} GRBM_SE0_PERF_SEL;
+typedef enum GRBM_SE1_PERF_SEL {
+ GRBM_SE1_PERF_SEL_COUNT = 0x0,
+ GRBM_SE1_PERF_SEL_USER_DEFINED = 0x1,
+ GRBM_SE1_PERF_SEL_CB_BUSY = 0x2,
+ GRBM_SE1_PERF_SEL_DB_BUSY = 0x3,
+ GRBM_SE1_PERF_SEL_SC_BUSY = 0x4,
+ GRBM_SE1_PERF_SEL_RESERVED_1 = 0x5,
+ GRBM_SE1_PERF_SEL_SPI_BUSY = 0x6,
+ GRBM_SE1_PERF_SEL_SX_BUSY = 0x7,
+ GRBM_SE1_PERF_SEL_TA_BUSY = 0x8,
+ GRBM_SE1_PERF_SEL_CB_CLEAN = 0x9,
+ GRBM_SE1_PERF_SEL_DB_CLEAN = 0xa,
+ GRBM_SE1_PERF_SEL_RESERVED_0 = 0xb,
+ GRBM_SE1_PERF_SEL_PA_BUSY = 0xc,
+ GRBM_SE1_PERF_SEL_VGT_BUSY = 0xd,
+ GRBM_SE1_PERF_SEL_BCI_BUSY = 0xe,
+} GRBM_SE1_PERF_SEL;
+typedef enum GRBM_SE2_PERF_SEL {
+ GRBM_SE2_PERF_SEL_COUNT = 0x0,
+ GRBM_SE2_PERF_SEL_USER_DEFINED = 0x1,
+ GRBM_SE2_PERF_SEL_CB_BUSY = 0x2,
+ GRBM_SE2_PERF_SEL_DB_BUSY = 0x3,
+ GRBM_SE2_PERF_SEL_SC_BUSY = 0x4,
+ GRBM_SE2_PERF_SEL_RESERVED_1 = 0x5,
+ GRBM_SE2_PERF_SEL_SPI_BUSY = 0x6,
+ GRBM_SE2_PERF_SEL_SX_BUSY = 0x7,
+ GRBM_SE2_PERF_SEL_TA_BUSY = 0x8,
+ GRBM_SE2_PERF_SEL_CB_CLEAN = 0x9,
+ GRBM_SE2_PERF_SEL_DB_CLEAN = 0xa,
+ GRBM_SE2_PERF_SEL_RESERVED_0 = 0xb,
+ GRBM_SE2_PERF_SEL_PA_BUSY = 0xc,
+ GRBM_SE2_PERF_SEL_VGT_BUSY = 0xd,
+ GRBM_SE2_PERF_SEL_BCI_BUSY = 0xe,
+} GRBM_SE2_PERF_SEL;
+typedef enum GRBM_SE3_PERF_SEL {
+ GRBM_SE3_PERF_SEL_COUNT = 0x0,
+ GRBM_SE3_PERF_SEL_USER_DEFINED = 0x1,
+ GRBM_SE3_PERF_SEL_CB_BUSY = 0x2,
+ GRBM_SE3_PERF_SEL_DB_BUSY = 0x3,
+ GRBM_SE3_PERF_SEL_SC_BUSY = 0x4,
+ GRBM_SE3_PERF_SEL_RESERVED_1 = 0x5,
+ GRBM_SE3_PERF_SEL_SPI_BUSY = 0x6,
+ GRBM_SE3_PERF_SEL_SX_BUSY = 0x7,
+ GRBM_SE3_PERF_SEL_TA_BUSY = 0x8,
+ GRBM_SE3_PERF_SEL_CB_CLEAN = 0x9,
+ GRBM_SE3_PERF_SEL_DB_CLEAN = 0xa,
+ GRBM_SE3_PERF_SEL_RESERVED_0 = 0xb,
+ GRBM_SE3_PERF_SEL_PA_BUSY = 0xc,
+ GRBM_SE3_PERF_SEL_VGT_BUSY = 0xd,
+ GRBM_SE3_PERF_SEL_BCI_BUSY = 0xe,
+} GRBM_SE3_PERF_SEL;
+typedef enum SU_PERFCNT_SEL {
+ PERF_PAPC_PASX_REQ = 0x0,
+ PERF_PAPC_PASX_DISABLE_PIPE = 0x1,
+ PERF_PAPC_PASX_FIRST_VECTOR = 0x2,
+ PERF_PAPC_PASX_SECOND_VECTOR = 0x3,
+ PERF_PAPC_PASX_FIRST_DEAD = 0x4,
+ PERF_PAPC_PASX_SECOND_DEAD = 0x5,
+ PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x6,
+ PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x7,
+ PERF_PAPC_PA_INPUT_PRIM = 0x8,
+ PERF_PAPC_PA_INPUT_NULL_PRIM = 0x9,
+ PERF_PAPC_PA_INPUT_EVENT_FLAG = 0xa,
+ PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 0xb,
+ PERF_PAPC_PA_INPUT_END_OF_PACKET = 0xc,
+ PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 0xd,
+ PERF_PAPC_CLPR_CULL_PRIM = 0xe,
+ PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0xf,
+ PERF_PAPC_CLPR_VV_CULL_PRIM = 0x10,
+ PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x11,
+ PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x12,
+ PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x13,
+ PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x14,
+ PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x15,
+ PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x16,
+ PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x17,
+ PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x18,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x19,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x1a,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x1b,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x1c,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x1d,
+ PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 0x1e,
+ PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x1f,
+ PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x20,
+ PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x21,
+ PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x22,
+ PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x23,
+ PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x24,
+ PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 0x25,
+ PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x26,
+ PERF_PAPC_CLSM_NULL_PRIM = 0x27,
+ PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x28,
+ PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x29,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x2a,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x2b,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x2c,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x2d,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x2e,
+ PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 0x2f,
+ PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x30,
+ PERF_PAPC_SU_INPUT_PRIM = 0x31,
+ PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x32,
+ PERF_PAPC_SU_INPUT_NULL_PRIM = 0x33,
+ PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x34,
+ PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x35,
+ PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x36,
+ PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x37,
+ PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x38,
+ PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x39,
+ PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x3a,
+ PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x3b,
+ PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x3c,
+ PERF_PAPC_SU_OUTPUT_PRIM = 0x3d,
+ PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x3e,
+ PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x3f,
+ PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x40,
+ PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x41,
+ PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x42,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x43,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x44,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x45,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x46,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x47,
+ PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x48,
+ PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x49,
+ PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x4a,
+ PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x4b,
+ PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x4c,
+ PERF_PAPC_PASX_REQ_IDLE = 0x4d,
+ PERF_PAPC_PASX_REQ_BUSY = 0x4e,
+ PERF_PAPC_PASX_REQ_STALLED = 0x4f,
+ PERF_PAPC_PASX_REC_IDLE = 0x50,
+ PERF_PAPC_PASX_REC_BUSY = 0x51,
+ PERF_PAPC_PASX_REC_STARVED_SX = 0x52,
+ PERF_PAPC_PASX_REC_STALLED = 0x53,
+ PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x54,
+ PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x55,
+ PERF_PAPC_CCGSM_IDLE = 0x56,
+ PERF_PAPC_CCGSM_BUSY = 0x57,
+ PERF_PAPC_CCGSM_STALLED = 0x58,
+ PERF_PAPC_CLPRIM_IDLE = 0x59,
+ PERF_PAPC_CLPRIM_BUSY = 0x5a,
+ PERF_PAPC_CLPRIM_STALLED = 0x5b,
+ PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x5c,
+ PERF_PAPC_CLIPSM_IDLE = 0x5d,
+ PERF_PAPC_CLIPSM_BUSY = 0x5e,
+ PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x5f,
+ PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x60,
+ PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x61,
+ PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x62,
+ PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x63,
+ PERF_PAPC_CLIPGA_IDLE = 0x64,
+ PERF_PAPC_CLIPGA_BUSY = 0x65,
+ PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x66,
+ PERF_PAPC_CLIPGA_STALLED = 0x67,
+ PERF_PAPC_CLIP_IDLE = 0x68,
+ PERF_PAPC_CLIP_BUSY = 0x69,
+ PERF_PAPC_SU_IDLE = 0x6a,
+ PERF_PAPC_SU_BUSY = 0x6b,
+ PERF_PAPC_SU_STARVED_CLIP = 0x6c,
+ PERF_PAPC_SU_STALLED_SC = 0x6d,
+ PERF_PAPC_CL_DYN_SCLK_VLD = 0x6e,
+ PERF_PAPC_SU_DYN_SCLK_VLD = 0x6f,
+ PERF_PAPC_PA_REG_SCLK_VLD = 0x70,
+ PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 0x71,
+ PERF_PAPC_PASX_SE0_REQ = 0x72,
+ PERF_PAPC_PASX_SE1_REQ = 0x73,
+ PERF_PAPC_PASX_SE0_FIRST_VECTOR = 0x74,
+ PERF_PAPC_PASX_SE0_SECOND_VECTOR = 0x75,
+ PERF_PAPC_PASX_SE1_FIRST_VECTOR = 0x76,
+ PERF_PAPC_PASX_SE1_SECOND_VECTOR = 0x77,
+ PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x78,
+ PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x79,
+ PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 0x7a,
+ PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x7b,
+ PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x7c,
+ PERF_PAPC_SU_SE01_OUTPUT_PRIM = 0x7d,
+ PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x7e,
+ PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x7f,
+ PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 0x80,
+ PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 0x81,
+ PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 0x82,
+ PERF_PAPC_SU_SE0_STALLED_SC = 0x83,
+ PERF_PAPC_SU_SE1_STALLED_SC = 0x84,
+ PERF_PAPC_SU_SE01_STALLED_SC = 0x85,
+ PERF_PAPC_CLSM_CLIPPING_PRIM = 0x86,
+ PERF_PAPC_SU_CULLED_PRIM = 0x87,
+ PERF_PAPC_SU_OUTPUT_EOPG = 0x88,
+ PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 0x89,
+ PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 0x8a,
+ PERF_PAPC_SU_SE2_OUTPUT_PRIM = 0x8b,
+ PERF_PAPC_SU_SE3_OUTPUT_PRIM = 0x8c,
+ PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 0x8d,
+ PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 0x8e,
+ PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 0x8f,
+ PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 0x90,
+ PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 0x91,
+ PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 0x92,
+ PERF_PAPC_SU_SE0_OUTPUT_EOPG = 0x93,
+ PERF_PAPC_SU_SE1_OUTPUT_EOPG = 0x94,
+ PERF_PAPC_SU_SE2_OUTPUT_EOPG = 0x95,
+ PERF_PAPC_SU_SE3_OUTPUT_EOPG = 0x96,
+ PERF_PAPC_SU_SE2_STALLED_SC = 0x97,
+ PERF_PAPC_SU_SE3_STALLED_SC = 0x98,
+} SU_PERFCNT_SEL;
+typedef enum SC_PERFCNT_SEL {
+ SC_SRPS_WINDOW_VALID = 0x0,
+ SC_PSSW_WINDOW_VALID = 0x1,
+ SC_TPQZ_WINDOW_VALID = 0x2,
+ SC_QZQP_WINDOW_VALID = 0x3,
+ SC_TRPK_WINDOW_VALID = 0x4,
+ SC_SRPS_WINDOW_VALID_BUSY = 0x5,
+ SC_PSSW_WINDOW_VALID_BUSY = 0x6,
+ SC_TPQZ_WINDOW_VALID_BUSY = 0x7,
+ SC_QZQP_WINDOW_VALID_BUSY = 0x8,
+ SC_TRPK_WINDOW_VALID_BUSY = 0x9,
+ SC_STARVED_BY_PA = 0xa,
+ SC_STALLED_BY_PRIMFIFO = 0xb,
+ SC_STALLED_BY_DB_TILE = 0xc,
+ SC_STARVED_BY_DB_TILE = 0xd,
+ SC_STALLED_BY_TILEORDERFIFO = 0xe,
+ SC_STALLED_BY_TILEFIFO = 0xf,
+ SC_STALLED_BY_DB_QUAD = 0x10,
+ SC_STARVED_BY_DB_QUAD = 0x11,
+ SC_STALLED_BY_QUADFIFO = 0x12,
+ SC_STALLED_BY_BCI = 0x13,
+ SC_STALLED_BY_SPI = 0x14,
+ SC_SCISSOR_DISCARD = 0x15,
+ SC_BB_DISCARD = 0x16,
+ SC_SUPERTILE_COUNT = 0x17,
+ SC_SUPERTILE_PER_PRIM_H0 = 0x18,
+ SC_SUPERTILE_PER_PRIM_H1 = 0x19,
+ SC_SUPERTILE_PER_PRIM_H2 = 0x1a,
+ SC_SUPERTILE_PER_PRIM_H3 = 0x1b,
+ SC_SUPERTILE_PER_PRIM_H4 = 0x1c,
+ SC_SUPERTILE_PER_PRIM_H5 = 0x1d,
+ SC_SUPERTILE_PER_PRIM_H6 = 0x1e,
+ SC_SUPERTILE_PER_PRIM_H7 = 0x1f,
+ SC_SUPERTILE_PER_PRIM_H8 = 0x20,
+ SC_SUPERTILE_PER_PRIM_H9 = 0x21,
+ SC_SUPERTILE_PER_PRIM_H10 = 0x22,
+ SC_SUPERTILE_PER_PRIM_H11 = 0x23,
+ SC_SUPERTILE_PER_PRIM_H12 = 0x24,
+ SC_SUPERTILE_PER_PRIM_H13 = 0x25,
+ SC_SUPERTILE_PER_PRIM_H14 = 0x26,
+ SC_SUPERTILE_PER_PRIM_H15 = 0x27,
+ SC_SUPERTILE_PER_PRIM_H16 = 0x28,
+ SC_TILE_PER_PRIM_H0 = 0x29,
+ SC_TILE_PER_PRIM_H1 = 0x2a,
+ SC_TILE_PER_PRIM_H2 = 0x2b,
+ SC_TILE_PER_PRIM_H3 = 0x2c,
+ SC_TILE_PER_PRIM_H4 = 0x2d,
+ SC_TILE_PER_PRIM_H5 = 0x2e,
+ SC_TILE_PER_PRIM_H6 = 0x2f,
+ SC_TILE_PER_PRIM_H7 = 0x30,
+ SC_TILE_PER_PRIM_H8 = 0x31,
+ SC_TILE_PER_PRIM_H9 = 0x32,
+ SC_TILE_PER_PRIM_H10 = 0x33,
+ SC_TILE_PER_PRIM_H11 = 0x34,
+ SC_TILE_PER_PRIM_H12 = 0x35,
+ SC_TILE_PER_PRIM_H13 = 0x36,
+ SC_TILE_PER_PRIM_H14 = 0x37,
+ SC_TILE_PER_PRIM_H15 = 0x38,
+ SC_TILE_PER_PRIM_H16 = 0x39,
+ SC_TILE_PER_SUPERTILE_H0 = 0x3a,
+ SC_TILE_PER_SUPERTILE_H1 = 0x3b,
+ SC_TILE_PER_SUPERTILE_H2 = 0x3c,
+ SC_TILE_PER_SUPERTILE_H3 = 0x3d,
+ SC_TILE_PER_SUPERTILE_H4 = 0x3e,
+ SC_TILE_PER_SUPERTILE_H5 = 0x3f,
+ SC_TILE_PER_SUPERTILE_H6 = 0x40,
+ SC_TILE_PER_SUPERTILE_H7 = 0x41,
+ SC_TILE_PER_SUPERTILE_H8 = 0x42,
+ SC_TILE_PER_SUPERTILE_H9 = 0x43,
+ SC_TILE_PER_SUPERTILE_H10 = 0x44,
+ SC_TILE_PER_SUPERTILE_H11 = 0x45,
+ SC_TILE_PER_SUPERTILE_H12 = 0x46,
+ SC_TILE_PER_SUPERTILE_H13 = 0x47,
+ SC_TILE_PER_SUPERTILE_H14 = 0x48,
+ SC_TILE_PER_SUPERTILE_H15 = 0x49,
+ SC_TILE_PER_SUPERTILE_H16 = 0x4a,
+ SC_TILE_PICKED_H1 = 0x4b,
+ SC_TILE_PICKED_H2 = 0x4c,
+ SC_TILE_PICKED_H3 = 0x4d,
+ SC_TILE_PICKED_H4 = 0x4e,
+ SC_QZ0_MULTI_GPU_TILE_DISCARD = 0x4f,
+ SC_QZ1_MULTI_GPU_TILE_DISCARD = 0x50,
+ SC_QZ2_MULTI_GPU_TILE_DISCARD = 0x51,
+ SC_QZ3_MULTI_GPU_TILE_DISCARD = 0x52,
+ SC_QZ0_TILE_COUNT = 0x53,
+ SC_QZ1_TILE_COUNT = 0x54,
+ SC_QZ2_TILE_COUNT = 0x55,
+ SC_QZ3_TILE_COUNT = 0x56,
+ SC_QZ0_TILE_COVERED_COUNT = 0x57,
+ SC_QZ1_TILE_COVERED_COUNT = 0x58,
+ SC_QZ2_TILE_COVERED_COUNT = 0x59,
+ SC_QZ3_TILE_COVERED_COUNT = 0x5a,
+ SC_QZ0_TILE_NOT_COVERED_COUNT = 0x5b,
+ SC_QZ1_TILE_NOT_COVERED_COUNT = 0x5c,
+ SC_QZ2_TILE_NOT_COVERED_COUNT = 0x5d,
+ SC_QZ3_TILE_NOT_COVERED_COUNT = 0x5e,
+ SC_QZ0_QUAD_PER_TILE_H0 = 0x5f,
+ SC_QZ0_QUAD_PER_TILE_H1 = 0x60,
+ SC_QZ0_QUAD_PER_TILE_H2 = 0x61,
+ SC_QZ0_QUAD_PER_TILE_H3 = 0x62,
+ SC_QZ0_QUAD_PER_TILE_H4 = 0x63,
+ SC_QZ0_QUAD_PER_TILE_H5 = 0x64,
+ SC_QZ0_QUAD_PER_TILE_H6 = 0x65,
+ SC_QZ0_QUAD_PER_TILE_H7 = 0x66,
+ SC_QZ0_QUAD_PER_TILE_H8 = 0x67,
+ SC_QZ0_QUAD_PER_TILE_H9 = 0x68,
+ SC_QZ0_QUAD_PER_TILE_H10 = 0x69,
+ SC_QZ0_QUAD_PER_TILE_H11 = 0x6a,
+ SC_QZ0_QUAD_PER_TILE_H12 = 0x6b,
+ SC_QZ0_QUAD_PER_TILE_H13 = 0x6c,
+ SC_QZ0_QUAD_PER_TILE_H14 = 0x6d,
+ SC_QZ0_QUAD_PER_TILE_H15 = 0x6e,
+ SC_QZ0_QUAD_PER_TILE_H16 = 0x6f,
+ SC_QZ1_QUAD_PER_TILE_H0 = 0x70,
+ SC_QZ1_QUAD_PER_TILE_H1 = 0x71,
+ SC_QZ1_QUAD_PER_TILE_H2 = 0x72,
+ SC_QZ1_QUAD_PER_TILE_H3 = 0x73,
+ SC_QZ1_QUAD_PER_TILE_H4 = 0x74,
+ SC_QZ1_QUAD_PER_TILE_H5 = 0x75,
+ SC_QZ1_QUAD_PER_TILE_H6 = 0x76,
+ SC_QZ1_QUAD_PER_TILE_H7 = 0x77,
+ SC_QZ1_QUAD_PER_TILE_H8 = 0x78,
+ SC_QZ1_QUAD_PER_TILE_H9 = 0x79,
+ SC_QZ1_QUAD_PER_TILE_H10 = 0x7a,
+ SC_QZ1_QUAD_PER_TILE_H11 = 0x7b,
+ SC_QZ1_QUAD_PER_TILE_H12 = 0x7c,
+ SC_QZ1_QUAD_PER_TILE_H13 = 0x7d,
+ SC_QZ1_QUAD_PER_TILE_H14 = 0x7e,
+ SC_QZ1_QUAD_PER_TILE_H15 = 0x7f,
+ SC_QZ1_QUAD_PER_TILE_H16 = 0x80,
+ SC_QZ2_QUAD_PER_TILE_H0 = 0x81,
+ SC_QZ2_QUAD_PER_TILE_H1 = 0x82,
+ SC_QZ2_QUAD_PER_TILE_H2 = 0x83,
+ SC_QZ2_QUAD_PER_TILE_H3 = 0x84,
+ SC_QZ2_QUAD_PER_TILE_H4 = 0x85,
+ SC_QZ2_QUAD_PER_TILE_H5 = 0x86,
+ SC_QZ2_QUAD_PER_TILE_H6 = 0x87,
+ SC_QZ2_QUAD_PER_TILE_H7 = 0x88,
+ SC_QZ2_QUAD_PER_TILE_H8 = 0x89,
+ SC_QZ2_QUAD_PER_TILE_H9 = 0x8a,
+ SC_QZ2_QUAD_PER_TILE_H10 = 0x8b,
+ SC_QZ2_QUAD_PER_TILE_H11 = 0x8c,
+ SC_QZ2_QUAD_PER_TILE_H12 = 0x8d,
+ SC_QZ2_QUAD_PER_TILE_H13 = 0x8e,
+ SC_QZ2_QUAD_PER_TILE_H14 = 0x8f,
+ SC_QZ2_QUAD_PER_TILE_H15 = 0x90,
+ SC_QZ2_QUAD_PER_TILE_H16 = 0x91,
+ SC_QZ3_QUAD_PER_TILE_H0 = 0x92,
+ SC_QZ3_QUAD_PER_TILE_H1 = 0x93,
+ SC_QZ3_QUAD_PER_TILE_H2 = 0x94,
+ SC_QZ3_QUAD_PER_TILE_H3 = 0x95,
+ SC_QZ3_QUAD_PER_TILE_H4 = 0x96,
+ SC_QZ3_QUAD_PER_TILE_H5 = 0x97,
+ SC_QZ3_QUAD_PER_TILE_H6 = 0x98,
+ SC_QZ3_QUAD_PER_TILE_H7 = 0x99,
+ SC_QZ3_QUAD_PER_TILE_H8 = 0x9a,
+ SC_QZ3_QUAD_PER_TILE_H9 = 0x9b,
+ SC_QZ3_QUAD_PER_TILE_H10 = 0x9c,
+ SC_QZ3_QUAD_PER_TILE_H11 = 0x9d,
+ SC_QZ3_QUAD_PER_TILE_H12 = 0x9e,
+ SC_QZ3_QUAD_PER_TILE_H13 = 0x9f,
+ SC_QZ3_QUAD_PER_TILE_H14 = 0xa0,
+ SC_QZ3_QUAD_PER_TILE_H15 = 0xa1,
+ SC_QZ3_QUAD_PER_TILE_H16 = 0xa2,
+ SC_QZ0_QUAD_COUNT = 0xa3,
+ SC_QZ1_QUAD_COUNT = 0xa4,
+ SC_QZ2_QUAD_COUNT = 0xa5,
+ SC_QZ3_QUAD_COUNT = 0xa6,
+ SC_P0_HIZ_TILE_COUNT = 0xa7,
+ SC_P1_HIZ_TILE_COUNT = 0xa8,
+ SC_P2_HIZ_TILE_COUNT = 0xa9,
+ SC_P3_HIZ_TILE_COUNT = 0xaa,
+ SC_P0_HIZ_QUAD_PER_TILE_H0 = 0xab,
+ SC_P0_HIZ_QUAD_PER_TILE_H1 = 0xac,
+ SC_P0_HIZ_QUAD_PER_TILE_H2 = 0xad,
+ SC_P0_HIZ_QUAD_PER_TILE_H3 = 0xae,
+ SC_P0_HIZ_QUAD_PER_TILE_H4 = 0xaf,
+ SC_P0_HIZ_QUAD_PER_TILE_H5 = 0xb0,
+ SC_P0_HIZ_QUAD_PER_TILE_H6 = 0xb1,
+ SC_P0_HIZ_QUAD_PER_TILE_H7 = 0xb2,
+ SC_P0_HIZ_QUAD_PER_TILE_H8 = 0xb3,
+ SC_P0_HIZ_QUAD_PER_TILE_H9 = 0xb4,
+ SC_P0_HIZ_QUAD_PER_TILE_H10 = 0xb5,
+ SC_P0_HIZ_QUAD_PER_TILE_H11 = 0xb6,
+ SC_P0_HIZ_QUAD_PER_TILE_H12 = 0xb7,
+ SC_P0_HIZ_QUAD_PER_TILE_H13 = 0xb8,
+ SC_P0_HIZ_QUAD_PER_TILE_H14 = 0xb9,
+ SC_P0_HIZ_QUAD_PER_TILE_H15 = 0xba,
+ SC_P0_HIZ_QUAD_PER_TILE_H16 = 0xbb,
+ SC_P1_HIZ_QUAD_PER_TILE_H0 = 0xbc,
+ SC_P1_HIZ_QUAD_PER_TILE_H1 = 0xbd,
+ SC_P1_HIZ_QUAD_PER_TILE_H2 = 0xbe,
+ SC_P1_HIZ_QUAD_PER_TILE_H3 = 0xbf,
+ SC_P1_HIZ_QUAD_PER_TILE_H4 = 0xc0,
+ SC_P1_HIZ_QUAD_PER_TILE_H5 = 0xc1,
+ SC_P1_HIZ_QUAD_PER_TILE_H6 = 0xc2,
+ SC_P1_HIZ_QUAD_PER_TILE_H7 = 0xc3,
+ SC_P1_HIZ_QUAD_PER_TILE_H8 = 0xc4,
+ SC_P1_HIZ_QUAD_PER_TILE_H9 = 0xc5,
+ SC_P1_HIZ_QUAD_PER_TILE_H10 = 0xc6,
+ SC_P1_HIZ_QUAD_PER_TILE_H11 = 0xc7,
+ SC_P1_HIZ_QUAD_PER_TILE_H12 = 0xc8,
+ SC_P1_HIZ_QUAD_PER_TILE_H13 = 0xc9,
+ SC_P1_HIZ_QUAD_PER_TILE_H14 = 0xca,
+ SC_P1_HIZ_QUAD_PER_TILE_H15 = 0xcb,
+ SC_P1_HIZ_QUAD_PER_TILE_H16 = 0xcc,
+ SC_P2_HIZ_QUAD_PER_TILE_H0 = 0xcd,
+ SC_P2_HIZ_QUAD_PER_TILE_H1 = 0xce,
+ SC_P2_HIZ_QUAD_PER_TILE_H2 = 0xcf,
+ SC_P2_HIZ_QUAD_PER_TILE_H3 = 0xd0,
+ SC_P2_HIZ_QUAD_PER_TILE_H4 = 0xd1,
+ SC_P2_HIZ_QUAD_PER_TILE_H5 = 0xd2,
+ SC_P2_HIZ_QUAD_PER_TILE_H6 = 0xd3,
+ SC_P2_HIZ_QUAD_PER_TILE_H7 = 0xd4,
+ SC_P2_HIZ_QUAD_PER_TILE_H8 = 0xd5,
+ SC_P2_HIZ_QUAD_PER_TILE_H9 = 0xd6,
+ SC_P2_HIZ_QUAD_PER_TILE_H10 = 0xd7,
+ SC_P2_HIZ_QUAD_PER_TILE_H11 = 0xd8,
+ SC_P2_HIZ_QUAD_PER_TILE_H12 = 0xd9,
+ SC_P2_HIZ_QUAD_PER_TILE_H13 = 0xda,
+ SC_P2_HIZ_QUAD_PER_TILE_H14 = 0xdb,
+ SC_P2_HIZ_QUAD_PER_TILE_H15 = 0xdc,
+ SC_P2_HIZ_QUAD_PER_TILE_H16 = 0xdd,
+ SC_P3_HIZ_QUAD_PER_TILE_H0 = 0xde,
+ SC_P3_HIZ_QUAD_PER_TILE_H1 = 0xdf,
+ SC_P3_HIZ_QUAD_PER_TILE_H2 = 0xe0,
+ SC_P3_HIZ_QUAD_PER_TILE_H3 = 0xe1,
+ SC_P3_HIZ_QUAD_PER_TILE_H4 = 0xe2,
+ SC_P3_HIZ_QUAD_PER_TILE_H5 = 0xe3,
+ SC_P3_HIZ_QUAD_PER_TILE_H6 = 0xe4,
+ SC_P3_HIZ_QUAD_PER_TILE_H7 = 0xe5,
+ SC_P3_HIZ_QUAD_PER_TILE_H8 = 0xe6,
+ SC_P3_HIZ_QUAD_PER_TILE_H9 = 0xe7,
+ SC_P3_HIZ_QUAD_PER_TILE_H10 = 0xe8,
+ SC_P3_HIZ_QUAD_PER_TILE_H11 = 0xe9,
+ SC_P3_HIZ_QUAD_PER_TILE_H12 = 0xea,
+ SC_P3_HIZ_QUAD_PER_TILE_H13 = 0xeb,
+ SC_P3_HIZ_QUAD_PER_TILE_H14 = 0xec,
+ SC_P3_HIZ_QUAD_PER_TILE_H15 = 0xed,
+ SC_P3_HIZ_QUAD_PER_TILE_H16 = 0xee,
+ SC_P0_HIZ_QUAD_COUNT = 0xef,
+ SC_P1_HIZ_QUAD_COUNT = 0xf0,
+ SC_P2_HIZ_QUAD_COUNT = 0xf1,
+ SC_P3_HIZ_QUAD_COUNT = 0xf2,
+ SC_P0_DETAIL_QUAD_COUNT = 0xf3,
+ SC_P1_DETAIL_QUAD_COUNT = 0xf4,
+ SC_P2_DETAIL_QUAD_COUNT = 0xf5,
+ SC_P3_DETAIL_QUAD_COUNT = 0xf6,
+ SC_P0_DETAIL_QUAD_WITH_1_PIX = 0xf7,
+ SC_P0_DETAIL_QUAD_WITH_2_PIX = 0xf8,
+ SC_P0_DETAIL_QUAD_WITH_3_PIX = 0xf9,
+ SC_P0_DETAIL_QUAD_WITH_4_PIX = 0xfa,
+ SC_P1_DETAIL_QUAD_WITH_1_PIX = 0xfb,
+ SC_P1_DETAIL_QUAD_WITH_2_PIX = 0xfc,
+ SC_P1_DETAIL_QUAD_WITH_3_PIX = 0xfd,
+ SC_P1_DETAIL_QUAD_WITH_4_PIX = 0xfe,
+ SC_P2_DETAIL_QUAD_WITH_1_PIX = 0xff,
+ SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x100,
+ SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x101,
+ SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x102,
+ SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x103,
+ SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x104,
+ SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x105,
+ SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x106,
+ SC_EARLYZ_QUAD_COUNT = 0x107,
+ SC_EARLYZ_QUAD_WITH_1_PIX = 0x108,
+ SC_EARLYZ_QUAD_WITH_2_PIX = 0x109,
+ SC_EARLYZ_QUAD_WITH_3_PIX = 0x10a,
+ SC_EARLYZ_QUAD_WITH_4_PIX = 0x10b,
+ SC_PKR_QUAD_PER_ROW_H1 = 0x10c,
+ SC_PKR_QUAD_PER_ROW_H2 = 0x10d,
+ SC_PKR_QUAD_PER_ROW_H3 = 0x10e,
+ SC_PKR_QUAD_PER_ROW_H4 = 0x10f,
+ SC_PKR_END_OF_VECTOR = 0x110,
+ SC_PKR_CONTROL_XFER = 0x111,
+ SC_PKR_DBHANG_FORCE_EOV = 0x112,
+ SC_REG_SCLK_BUSY = 0x113,
+ SC_GRP0_DYN_SCLK_BUSY = 0x114,
+ SC_GRP1_DYN_SCLK_BUSY = 0x115,
+ SC_GRP2_DYN_SCLK_BUSY = 0x116,
+ SC_GRP3_DYN_SCLK_BUSY = 0x117,
+ SC_GRP4_DYN_SCLK_BUSY = 0x118,
+ SC_PA0_SC_DATA_FIFO_RD = 0x119,
+ SC_PA0_SC_DATA_FIFO_WE = 0x11a,
+ SC_PA1_SC_DATA_FIFO_RD = 0x11b,
+ SC_PA1_SC_DATA_FIFO_WE = 0x11c,
+ SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x11d,
+ SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x11e,
+ SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x11f,
+ SC_PS_ARB_STALLED_FROM_BELOW = 0x120,
+ SC_PS_ARB_STARVED_FROM_ABOVE = 0x121,
+ SC_PS_ARB_SC_BUSY = 0x122,
+ SC_PS_ARB_PA_SC_BUSY = 0x123,
+ SC_PA2_SC_DATA_FIFO_RD = 0x124,
+ SC_PA2_SC_DATA_FIFO_WE = 0x125,
+ SC_PA3_SC_DATA_FIFO_RD = 0x126,
+ SC_PA3_SC_DATA_FIFO_WE = 0x127,
+ SC_PA_SC_DEALLOC_0_0_WE = 0x128,
+ SC_PA_SC_DEALLOC_0_1_WE = 0x129,
+ SC_PA_SC_DEALLOC_1_0_WE = 0x12a,
+ SC_PA_SC_DEALLOC_1_1_WE = 0x12b,
+ SC_PA_SC_DEALLOC_2_0_WE = 0x12c,
+ SC_PA_SC_DEALLOC_2_1_WE = 0x12d,
+ SC_PA_SC_DEALLOC_3_0_WE = 0x12e,
+ SC_PA_SC_DEALLOC_3_1_WE = 0x12f,
+ SC_PA0_SC_EOP_WE = 0x130,
+ SC_PA0_SC_EOPG_WE = 0x131,
+ SC_PA0_SC_EVENT_WE = 0x132,
+ SC_PA1_SC_EOP_WE = 0x133,
+ SC_PA1_SC_EOPG_WE = 0x134,
+ SC_PA1_SC_EVENT_WE = 0x135,
+ SC_PA2_SC_EOP_WE = 0x136,
+ SC_PA2_SC_EOPG_WE = 0x137,
+ SC_PA2_SC_EVENT_WE = 0x138,
+ SC_PA3_SC_EOP_WE = 0x139,
+ SC_PA3_SC_EOPG_WE = 0x13a,
+ SC_PA3_SC_EVENT_WE = 0x13b,
+ SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 0x13c,
+ SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 0x13d,
+ SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 0x13e,
+ SC_PS_ARB_EOP_POP_SYNC_POP = 0x13f,
+ SC_PS_ARB_EVENT_SYNC_POP = 0x140,
+ SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 0x141,
+ SC_PA0_SC_FPOV_WE = 0x142,
+ SC_PA1_SC_FPOV_WE = 0x143,
+ SC_PA2_SC_FPOV_WE = 0x144,
+ SC_PA3_SC_FPOV_WE = 0x145,
+ SC_PA0_SC_LPOV_WE = 0x146,
+ SC_PA1_SC_LPOV_WE = 0x147,
+ SC_PA2_SC_LPOV_WE = 0x148,
+ SC_PA3_SC_LPOV_WE = 0x149,
+ SC_SC_SPI_DEALLOC_0_0 = 0x14a,
+ SC_SC_SPI_DEALLOC_0_1 = 0x14b,
+ SC_SC_SPI_DEALLOC_0_2 = 0x14c,
+ SC_SC_SPI_DEALLOC_1_0 = 0x14d,
+ SC_SC_SPI_DEALLOC_1_1 = 0x14e,
+ SC_SC_SPI_DEALLOC_1_2 = 0x14f,
+ SC_SC_SPI_DEALLOC_2_0 = 0x150,
+ SC_SC_SPI_DEALLOC_2_1 = 0x151,
+ SC_SC_SPI_DEALLOC_2_2 = 0x152,
+ SC_SC_SPI_DEALLOC_3_0 = 0x153,
+ SC_SC_SPI_DEALLOC_3_1 = 0x154,
+ SC_SC_SPI_DEALLOC_3_2 = 0x155,
+ SC_SC_SPI_FPOV_0 = 0x156,
+ SC_SC_SPI_FPOV_1 = 0x157,
+ SC_SC_SPI_FPOV_2 = 0x158,
+ SC_SC_SPI_FPOV_3 = 0x159,
+ SC_SC_SPI_EVENT = 0x15a,
+ SC_PS_TS_EVENT_FIFO_PUSH = 0x15b,
+ SC_PS_TS_EVENT_FIFO_POP = 0x15c,
+ SC_PS_CTX_DONE_FIFO_PUSH = 0x15d,
+ SC_PS_CTX_DONE_FIFO_POP = 0x15e,
+ SC_MULTICYCLE_BUBBLE_FREEZE = 0x15f,
+ SC_EOP_SYNC_WINDOW = 0x160,
+ SC_PA0_SC_NULL_WE = 0x161,
+ SC_PA0_SC_NULL_DEALLOC_WE = 0x162,
+ SC_PA0_SC_DATA_FIFO_EOPG_RD = 0x163,
+ SC_PA0_SC_DATA_FIFO_EOP_RD = 0x164,
+ SC_PA0_SC_DEALLOC_0_RD = 0x165,
+ SC_PA0_SC_DEALLOC_1_RD = 0x166,
+ SC_PA1_SC_DATA_FIFO_EOPG_RD = 0x167,
+ SC_PA1_SC_DATA_FIFO_EOP_RD = 0x168,
+ SC_PA1_SC_DEALLOC_0_RD = 0x169,
+ SC_PA1_SC_DEALLOC_1_RD = 0x16a,
+ SC_PA1_SC_NULL_WE = 0x16b,
+ SC_PA1_SC_NULL_DEALLOC_WE = 0x16c,
+ SC_PA2_SC_DATA_FIFO_EOPG_RD = 0x16d,
+ SC_PA2_SC_DATA_FIFO_EOP_RD = 0x16e,
+ SC_PA2_SC_DEALLOC_0_RD = 0x16f,
+ SC_PA2_SC_DEALLOC_1_RD = 0x170,
+ SC_PA2_SC_NULL_WE = 0x171,
+ SC_PA2_SC_NULL_DEALLOC_WE = 0x172,
+ SC_PA3_SC_DATA_FIFO_EOPG_RD = 0x173,
+ SC_PA3_SC_DATA_FIFO_EOP_RD = 0x174,
+ SC_PA3_SC_DEALLOC_0_RD = 0x175,
+ SC_PA3_SC_DEALLOC_1_RD = 0x176,
+ SC_PA3_SC_NULL_WE = 0x177,
+ SC_PA3_SC_NULL_DEALLOC_WE = 0x178,
+ SC_PS_PA0_SC_FIFO_EMPTY = 0x179,
+ SC_PS_PA0_SC_FIFO_FULL = 0x17a,
+ SC_PA0_PS_DATA_SEND = 0x17b,
+ SC_PS_PA1_SC_FIFO_EMPTY = 0x17c,
+ SC_PS_PA1_SC_FIFO_FULL = 0x17d,
+ SC_PA1_PS_DATA_SEND = 0x17e,
+ SC_PS_PA2_SC_FIFO_EMPTY = 0x17f,
+ SC_PS_PA2_SC_FIFO_FULL = 0x180,
+ SC_PA2_PS_DATA_SEND = 0x181,
+ SC_PS_PA3_SC_FIFO_EMPTY = 0x182,
+ SC_PS_PA3_SC_FIFO_FULL = 0x183,
+ SC_PA3_PS_DATA_SEND = 0x184,
+ SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x185,
+ SC_BUSY_CNT_NOT_ZERO = 0x186,
+ SC_BM_BUSY = 0x187,
+ SC_BACKEND_BUSY = 0x188,
+ SC_SCF_SCB_INTERFACE_BUSY = 0x189,
+ SC_SCB_BUSY = 0x18a,
+ SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 0x18b,
+ SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 0x18c,
+} SC_PERFCNT_SEL;
+typedef enum SePairXsel {
+ RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x0,
+ RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x1,
+ RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x2,
+ RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x3,
+} SePairXsel;
+typedef enum SePairYsel {
+ RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x0,
+ RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x1,
+ RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x2,
+ RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x3,
+} SePairYsel;
+typedef enum SePairMap {
+ RASTER_CONFIG_SE_PAIR_MAP_0 = 0x0,
+ RASTER_CONFIG_SE_PAIR_MAP_1 = 0x1,
+ RASTER_CONFIG_SE_PAIR_MAP_2 = 0x2,
+ RASTER_CONFIG_SE_PAIR_MAP_3 = 0x3,
+} SePairMap;
+typedef enum SeXsel {
+ RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x0,
+ RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x1,
+ RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x2,
+ RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x3,
+} SeXsel;
+typedef enum SeYsel {
+ RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x0,
+ RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x1,
+ RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x2,
+ RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x3,
+} SeYsel;
+typedef enum SeMap {
+ RASTER_CONFIG_SE_MAP_0 = 0x0,
+ RASTER_CONFIG_SE_MAP_1 = 0x1,
+ RASTER_CONFIG_SE_MAP_2 = 0x2,
+ RASTER_CONFIG_SE_MAP_3 = 0x3,
+} SeMap;
+typedef enum ScXsel {
+ RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x0,
+ RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x1,
+ RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x2,
+ RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x3,
+} ScXsel;
+typedef enum ScYsel {
+ RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x0,
+ RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x1,
+ RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x2,
+ RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x3,
+} ScYsel;
+typedef enum ScMap {
+ RASTER_CONFIG_SC_MAP_0 = 0x0,
+ RASTER_CONFIG_SC_MAP_1 = 0x1,
+ RASTER_CONFIG_SC_MAP_2 = 0x2,
+ RASTER_CONFIG_SC_MAP_3 = 0x3,
+} ScMap;
+typedef enum PkrXsel2 {
+ RASTER_CONFIG_PKR_XSEL2_0 = 0x0,
+ RASTER_CONFIG_PKR_XSEL2_1 = 0x1,
+ RASTER_CONFIG_PKR_XSEL2_2 = 0x2,
+ RASTER_CONFIG_PKR_XSEL2_3 = 0x3,
+} PkrXsel2;
+typedef enum PkrXsel {
+ RASTER_CONFIG_PKR_XSEL_0 = 0x0,
+ RASTER_CONFIG_PKR_XSEL_1 = 0x1,
+ RASTER_CONFIG_PKR_XSEL_2 = 0x2,
+ RASTER_CONFIG_PKR_XSEL_3 = 0x3,
+} PkrXsel;
+typedef enum PkrYsel {
+ RASTER_CONFIG_PKR_YSEL_0 = 0x0,
+ RASTER_CONFIG_PKR_YSEL_1 = 0x1,
+ RASTER_CONFIG_PKR_YSEL_2 = 0x2,
+ RASTER_CONFIG_PKR_YSEL_3 = 0x3,
+} PkrYsel;
+typedef enum PkrMap {
+ RASTER_CONFIG_PKR_MAP_0 = 0x0,
+ RASTER_CONFIG_PKR_MAP_1 = 0x1,
+ RASTER_CONFIG_PKR_MAP_2 = 0x2,
+ RASTER_CONFIG_PKR_MAP_3 = 0x3,
+} PkrMap;
+typedef enum RbXsel {
+ RASTER_CONFIG_RB_XSEL_0 = 0x0,
+ RASTER_CONFIG_RB_XSEL_1 = 0x1,
+} RbXsel;
+typedef enum RbYsel {
+ RASTER_CONFIG_RB_YSEL_0 = 0x0,
+ RASTER_CONFIG_RB_YSEL_1 = 0x1,
+} RbYsel;
+typedef enum RbXsel2 {
+ RASTER_CONFIG_RB_XSEL2_0 = 0x0,
+ RASTER_CONFIG_RB_XSEL2_1 = 0x1,
+ RASTER_CONFIG_RB_XSEL2_2 = 0x2,
+ RASTER_CONFIG_RB_XSEL2_3 = 0x3,
+} RbXsel2;
+typedef enum RbMap {
+ RASTER_CONFIG_RB_MAP_0 = 0x0,
+ RASTER_CONFIG_RB_MAP_1 = 0x1,
+ RASTER_CONFIG_RB_MAP_2 = 0x2,
+ RASTER_CONFIG_RB_MAP_3 = 0x3,
+} RbMap;
+typedef enum CSDATA_TYPE {
+ CSDATA_TYPE_TG = 0x0,
+ CSDATA_TYPE_STATE = 0x1,
+ CSDATA_TYPE_EVENT = 0x2,
+ CSDATA_TYPE_PRIVATE = 0x3,
+} CSDATA_TYPE;
+#define CSDATA_TYPE_WIDTH 0x2
+#define CSDATA_ADDR_WIDTH 0x7
+#define CSDATA_DATA_WIDTH 0x20
+typedef enum SPI_SAMPLE_CNTL {
+ CENTROIDS_ONLY = 0x0,
+ CENTERS_ONLY = 0x1,
+ CENTROIDS_AND_CENTERS = 0x2,
+ UNDEF = 0x3,
+} SPI_SAMPLE_CNTL;
+typedef enum SPI_FOG_MODE {
+ SPI_FOG_NONE = 0x0,
+ SPI_FOG_EXP = 0x1,
+ SPI_FOG_EXP2 = 0x2,
+ SPI_FOG_LINEAR = 0x3,
+} SPI_FOG_MODE;
+typedef enum SPI_PNT_SPRITE_OVERRIDE {
+ SPI_PNT_SPRITE_SEL_0 = 0x0,
+ SPI_PNT_SPRITE_SEL_1 = 0x1,
+ SPI_PNT_SPRITE_SEL_S = 0x2,
+ SPI_PNT_SPRITE_SEL_T = 0x3,
+ SPI_PNT_SPRITE_SEL_NONE = 0x4,
+} SPI_PNT_SPRITE_OVERRIDE;
+typedef enum SPI_PERFCNT_SEL {
+ SPI_PERF_VS_WINDOW_VALID = 0x0,
+ SPI_PERF_VS_BUSY = 0x1,
+ SPI_PERF_VS_FIRST_WAVE = 0x2,
+ SPI_PERF_VS_LAST_WAVE = 0x3,
+ SPI_PERF_VS_LSHS_DEALLOC = 0x4,
+ SPI_PERF_VS_PC_STALL = 0x5,
+ SPI_PERF_VS_POS0_STALL = 0x6,
+ SPI_PERF_VS_POS1_STALL = 0x7,
+ SPI_PERF_VS_CRAWLER_STALL = 0x8,
+ SPI_PERF_VS_EVENT_WAVE = 0x9,
+ SPI_PERF_VS_WAVE = 0xa,
+ SPI_PERF_VS_PERS_UPD_FULL0 = 0xb,
+ SPI_PERF_VS_PERS_UPD_FULL1 = 0xc,
+ SPI_PERF_VS_LATE_ALLOC_FULL = 0xd,
+ SPI_PERF_VS_FIRST_SUBGRP = 0xe,
+ SPI_PERF_VS_LAST_SUBGRP = 0xf,
+ SPI_PERF_GS_WINDOW_VALID = 0x10,
+ SPI_PERF_GS_BUSY = 0x11,
+ SPI_PERF_GS_CRAWLER_STALL = 0x12,
+ SPI_PERF_GS_EVENT_WAVE = 0x13,
+ SPI_PERF_GS_WAVE = 0x14,
+ SPI_PERF_GS_PERS_UPD_FULL0 = 0x15,
+ SPI_PERF_GS_PERS_UPD_FULL1 = 0x16,
+ SPI_PERF_GS_FIRST_SUBGRP = 0x17,
+ SPI_PERF_GS_LAST_SUBGRP = 0x18,
+ SPI_PERF_ES_WINDOW_VALID = 0x19,
+ SPI_PERF_ES_BUSY = 0x1a,
+ SPI_PERF_ES_CRAWLER_STALL = 0x1b,
+ SPI_PERF_ES_FIRST_WAVE = 0x1c,
+ SPI_PERF_ES_LAST_WAVE = 0x1d,
+ SPI_PERF_ES_LSHS_DEALLOC = 0x1e,
+ SPI_PERF_ES_EVENT_WAVE = 0x1f,
+ SPI_PERF_ES_WAVE = 0x20,
+ SPI_PERF_ES_PERS_UPD_FULL0 = 0x21,
+ SPI_PERF_ES_PERS_UPD_FULL1 = 0x22,
+ SPI_PERF_ES_FIRST_SUBGRP = 0x23,
+ SPI_PERF_ES_LAST_SUBGRP = 0x24,
+ SPI_PERF_HS_WINDOW_VALID = 0x25,
+ SPI_PERF_HS_BUSY = 0x26,
+ SPI_PERF_HS_CRAWLER_STALL = 0x27,
+ SPI_PERF_HS_FIRST_WAVE = 0x28,
+ SPI_PERF_HS_LAST_WAVE = 0x29,
+ SPI_PERF_HS_LSHS_DEALLOC = 0x2a,
+ SPI_PERF_HS_EVENT_WAVE = 0x2b,
+ SPI_PERF_HS_WAVE = 0x2c,
+ SPI_PERF_HS_PERS_UPD_FULL0 = 0x2d,
+ SPI_PERF_HS_PERS_UPD_FULL1 = 0x2e,
+ SPI_PERF_LS_WINDOW_VALID = 0x2f,
+ SPI_PERF_LS_BUSY = 0x30,
+ SPI_PERF_LS_CRAWLER_STALL = 0x31,
+ SPI_PERF_LS_FIRST_WAVE = 0x32,
+ SPI_PERF_LS_LAST_WAVE = 0x33,
+ SPI_PERF_OFFCHIP_LDS_STALL_LS = 0x34,
+ SPI_PERF_LS_EVENT_WAVE = 0x35,
+ SPI_PERF_LS_WAVE = 0x36,
+ SPI_PERF_LS_PERS_UPD_FULL0 = 0x37,
+ SPI_PERF_LS_PERS_UPD_FULL1 = 0x38,
+ SPI_PERF_CSG_WINDOW_VALID = 0x39,
+ SPI_PERF_CSG_BUSY = 0x3a,
+ SPI_PERF_CSG_NUM_THREADGROUPS = 0x3b,
+ SPI_PERF_CSG_CRAWLER_STALL = 0x3c,
+ SPI_PERF_CSG_EVENT_WAVE = 0x3d,
+ SPI_PERF_CSG_WAVE = 0x3e,
+ SPI_PERF_CSN_WINDOW_VALID = 0x3f,
+ SPI_PERF_CSN_BUSY = 0x40,
+ SPI_PERF_CSN_NUM_THREADGROUPS = 0x41,
+ SPI_PERF_CSN_CRAWLER_STALL = 0x42,
+ SPI_PERF_CSN_EVENT_WAVE = 0x43,
+ SPI_PERF_CSN_WAVE = 0x44,
+ SPI_PERF_PS_CTL_WINDOW_VALID = 0x45,
+ SPI_PERF_PS_CTL_BUSY = 0x46,
+ SPI_PERF_PS_CTL_ACTIVE = 0x47,
+ SPI_PERF_PS_CTL_DEALLOC_BIN0 = 0x48,
+ SPI_PERF_PS_CTL_FPOS_BIN1_STALL = 0x49,
+ SPI_PERF_PS_CTL_EVENT_WAVE = 0x4a,
+ SPI_PERF_PS_CTL_WAVE = 0x4b,
+ SPI_PERF_PS_CTL_OPT_WAVE = 0x4c,
+ SPI_PERF_PS_CTL_PASS_BIN0 = 0x4d,
+ SPI_PERF_PS_CTL_PASS_BIN1 = 0x4e,
+ SPI_PERF_PS_CTL_FPOS_BIN2 = 0x4f,
+ SPI_PERF_PS_CTL_PRIM_BIN0 = 0x50,
+ SPI_PERF_PS_CTL_PRIM_BIN1 = 0x51,
+ SPI_PERF_PS_CTL_CNF_BIN2 = 0x52,
+ SPI_PERF_PS_CTL_CNF_BIN3 = 0x53,
+ SPI_PERF_PS_CTL_CRAWLER_STALL = 0x54,
+ SPI_PERF_PS_CTL_LDS_RES_FULL = 0x55,
+ SPI_PERF_PS_PERS_UPD_FULL0 = 0x56,
+ SPI_PERF_PS_PERS_UPD_FULL1 = 0x57,
+ SPI_PERF_PIX_ALLOC_PEND_CNT = 0x58,
+ SPI_PERF_PIX_ALLOC_SCB_STALL = 0x59,
+ SPI_PERF_PIX_ALLOC_DB0_STALL = 0x5a,
+ SPI_PERF_PIX_ALLOC_DB1_STALL = 0x5b,
+ SPI_PERF_PIX_ALLOC_DB2_STALL = 0x5c,
+ SPI_PERF_PIX_ALLOC_DB3_STALL = 0x5d,
+ SPI_PERF_LDS0_PC_VALID = 0x5e,
+ SPI_PERF_LDS1_PC_VALID = 0x5f,
+ SPI_PERF_RA_PIPE_REQ_BIN2 = 0x60,
+ SPI_PERF_RA_TASK_REQ_BIN3 = 0x61,
+ SPI_PERF_RA_WR_CTL_FULL = 0x62,
+ SPI_PERF_RA_REQ_NO_ALLOC = 0x63,
+ SPI_PERF_RA_REQ_NO_ALLOC_PS = 0x64,
+ SPI_PERF_RA_REQ_NO_ALLOC_VS = 0x65,
+ SPI_PERF_RA_REQ_NO_ALLOC_GS = 0x66,
+ SPI_PERF_RA_REQ_NO_ALLOC_ES = 0x67,
+ SPI_PERF_RA_REQ_NO_ALLOC_HS = 0x68,
+ SPI_PERF_RA_REQ_NO_ALLOC_LS = 0x69,
+ SPI_PERF_RA_REQ_NO_ALLOC_CSG = 0x6a,
+ SPI_PERF_RA_REQ_NO_ALLOC_CSN = 0x6b,
+ SPI_PERF_RA_RES_STALL_PS = 0x6c,
+ SPI_PERF_RA_RES_STALL_VS = 0x6d,
+ SPI_PERF_RA_RES_STALL_GS = 0x6e,
+ SPI_PERF_RA_RES_STALL_ES = 0x6f,
+ SPI_PERF_RA_RES_STALL_HS = 0x70,
+ SPI_PERF_RA_RES_STALL_LS = 0x71,
+ SPI_PERF_RA_RES_STALL_CSG = 0x72,
+ SPI_PERF_RA_RES_STALL_CSN = 0x73,
+ SPI_PERF_RA_TMP_STALL_PS = 0x74,
+ SPI_PERF_RA_TMP_STALL_VS = 0x75,
+ SPI_PERF_RA_TMP_STALL_GS = 0x76,
+ SPI_PERF_RA_TMP_STALL_ES = 0x77,
+ SPI_PERF_RA_TMP_STALL_HS = 0x78,
+ SPI_PERF_RA_TMP_STALL_LS = 0x79,
+ SPI_PERF_RA_TMP_STALL_CSG = 0x7a,
+ SPI_PERF_RA_TMP_STALL_CSN = 0x7b,
+ SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x7c,
+ SPI_PERF_RA_WAVE_SIMD_FULL_VS = 0x7d,
+ SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x7e,
+ SPI_PERF_RA_WAVE_SIMD_FULL_ES = 0x7f,
+ SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x80,
+ SPI_PERF_RA_WAVE_SIMD_FULL_LS = 0x81,
+ SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 0x82,
+ SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 0x83,
+ SPI_PERF_RA_VGPR_SIMD_FULL_PS = 0x84,
+ SPI_PERF_RA_VGPR_SIMD_FULL_VS = 0x85,
+ SPI_PERF_RA_VGPR_SIMD_FULL_GS = 0x86,
+ SPI_PERF_RA_VGPR_SIMD_FULL_ES = 0x87,
+ SPI_PERF_RA_VGPR_SIMD_FULL_HS = 0x88,
+ SPI_PERF_RA_VGPR_SIMD_FULL_LS = 0x89,
+ SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 0x8a,
+ SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 0x8b,
+ SPI_PERF_RA_SGPR_SIMD_FULL_PS = 0x8c,
+ SPI_PERF_RA_SGPR_SIMD_FULL_VS = 0x8d,
+ SPI_PERF_RA_SGPR_SIMD_FULL_GS = 0x8e,
+ SPI_PERF_RA_SGPR_SIMD_FULL_ES = 0x8f,
+ SPI_PERF_RA_SGPR_SIMD_FULL_HS = 0x90,
+ SPI_PERF_RA_SGPR_SIMD_FULL_LS = 0x91,
+ SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 0x92,
+ SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 0x93,
+ SPI_PERF_RA_LDS_CU_FULL_PS = 0x94,
+ SPI_PERF_RA_LDS_CU_FULL_LS = 0x95,
+ SPI_PERF_RA_LDS_CU_FULL_ES = 0x96,
+ SPI_PERF_RA_LDS_CU_FULL_CSG = 0x97,
+ SPI_PERF_RA_LDS_CU_FULL_CSN = 0x98,
+ SPI_PERF_RA_BAR_CU_FULL_HS = 0x99,
+ SPI_PERF_RA_BAR_CU_FULL_CSG = 0x9a,
+ SPI_PERF_RA_BAR_CU_FULL_CSN = 0x9b,
+ SPI_PERF_RA_BULKY_CU_FULL_CSG = 0x9c,
+ SPI_PERF_RA_BULKY_CU_FULL_CSN = 0x9d,
+ SPI_PERF_RA_TGLIM_CU_FULL_CSG = 0x9e,
+ SPI_PERF_RA_TGLIM_CU_FULL_CSN = 0x9f,
+ SPI_PERF_RA_WVLIM_STALL_PS = 0xa0,
+ SPI_PERF_RA_WVLIM_STALL_VS = 0xa1,
+ SPI_PERF_RA_WVLIM_STALL_GS = 0xa2,
+ SPI_PERF_RA_WVLIM_STALL_ES = 0xa3,
+ SPI_PERF_RA_WVLIM_STALL_HS = 0xa4,
+ SPI_PERF_RA_WVLIM_STALL_LS = 0xa5,
+ SPI_PERF_RA_WVLIM_STALL_CSG = 0xa6,
+ SPI_PERF_RA_WVLIM_STALL_CSN = 0xa7,
+ SPI_PERF_RA_PS_LOCK_NA = 0xa8,
+ SPI_PERF_RA_VS_LOCK = 0xa9,
+ SPI_PERF_RA_GS_LOCK = 0xaa,
+ SPI_PERF_RA_ES_LOCK = 0xab,
+ SPI_PERF_RA_HS_LOCK = 0xac,
+ SPI_PERF_RA_LS_LOCK = 0xad,
+ SPI_PERF_RA_CSG_LOCK = 0xae,
+ SPI_PERF_RA_CSN_LOCK = 0xaf,
+ SPI_PERF_RA_RSV_UPD = 0xb0,
+ SPI_PERF_EXP_ARB_COL_CNT = 0xb1,
+ SPI_PERF_EXP_ARB_PAR_CNT = 0xb2,
+ SPI_PERF_EXP_ARB_POS_CNT = 0xb3,
+ SPI_PERF_EXP_ARB_GDS_CNT = 0xb4,
+ SPI_PERF_CLKGATE_BUSY_STALL = 0xb5,
+ SPI_PERF_CLKGATE_ACTIVE_STALL = 0xb6,
+ SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 0xb7,
+ SPI_PERF_CLKGATE_CGTT_DYN_ON = 0xb8,
+ SPI_PERF_CLKGATE_CGTT_REG_ON = 0xb9,
+ SPI_PERF_NUM_VS_POS_EXPORTS = 0xba,
+ SPI_PERF_NUM_VS_PARAM_EXPORTS = 0xbb,
+ SPI_PERF_NUM_PS_COL_EXPORTS = 0xbc,
+ SPI_PERF_ES_GRP_FIFO_FULL = 0xbd,
+ SPI_PERF_GS_GRP_FIFO_FULL = 0xbe,
+ SPI_PERF_HS_GRP_FIFO_FULL = 0xbf,
+ SPI_PERF_LS_GRP_FIFO_FULL = 0xc0,
+ SPI_PERF_VS_ALLOC_CNT = 0xc1,
+ SPI_PERF_VS_LATE_ALLOC_ACCUM = 0xc2,
+ SPI_PERF_PC_ALLOC_CNT = 0xc3,
+ SPI_PERF_PC_ALLOC_ACCUM = 0xc4,
+} SPI_PERFCNT_SEL;
+typedef enum SPI_SHADER_FORMAT {
+ SPI_SHADER_NONE = 0x0,
+ SPI_SHADER_1COMP = 0x1,
+ SPI_SHADER_2COMP = 0x2,
+ SPI_SHADER_4COMPRESS = 0x3,
+ SPI_SHADER_4COMP = 0x4,
+} SPI_SHADER_FORMAT;
+typedef enum SPI_SHADER_EX_FORMAT {
+ SPI_SHADER_ZERO = 0x0,
+ SPI_SHADER_32_R = 0x1,
+ SPI_SHADER_32_GR = 0x2,
+ SPI_SHADER_32_AR = 0x3,
+ SPI_SHADER_FP16_ABGR = 0x4,
+ SPI_SHADER_UNORM16_ABGR = 0x5,
+ SPI_SHADER_SNORM16_ABGR = 0x6,
+ SPI_SHADER_UINT16_ABGR = 0x7,
+ SPI_SHADER_SINT16_ABGR = 0x8,
+ SPI_SHADER_32_ABGR = 0x9,
+} SPI_SHADER_EX_FORMAT;
+typedef enum CLKGATE_SM_MODE {
+ ON_SEQ = 0x0,
+ OFF_SEQ = 0x1,
+ PROG_SEQ = 0x2,
+ READ_SEQ = 0x3,
+ SM_MODE_RESERVED = 0x4,
+} CLKGATE_SM_MODE;
+typedef enum CLKGATE_BASE_MODE {
+ MULT_8 = 0x0,
+ MULT_16 = 0x1,
+} CLKGATE_BASE_MODE;
+typedef enum SQ_TEX_CLAMP {
+ SQ_TEX_WRAP = 0x0,
+ SQ_TEX_MIRROR = 0x1,
+ SQ_TEX_CLAMP_LAST_TEXEL = 0x2,
+ SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x3,
+ SQ_TEX_CLAMP_HALF_BORDER = 0x4,
+ SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x5,
+ SQ_TEX_CLAMP_BORDER = 0x6,
+ SQ_TEX_MIRROR_ONCE_BORDER = 0x7,
+} SQ_TEX_CLAMP;
+typedef enum SQ_TEX_XY_FILTER {
+ SQ_TEX_XY_FILTER_POINT = 0x0,
+ SQ_TEX_XY_FILTER_BILINEAR = 0x1,
+ SQ_TEX_XY_FILTER_ANISO_POINT = 0x2,
+ SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x3,
+} SQ_TEX_XY_FILTER;
+typedef enum SQ_TEX_Z_FILTER {
+ SQ_TEX_Z_FILTER_NONE = 0x0,
+ SQ_TEX_Z_FILTER_POINT = 0x1,
+ SQ_TEX_Z_FILTER_LINEAR = 0x2,
+} SQ_TEX_Z_FILTER;
+typedef enum SQ_TEX_MIP_FILTER {
+ SQ_TEX_MIP_FILTER_NONE = 0x0,
+ SQ_TEX_MIP_FILTER_POINT = 0x1,
+ SQ_TEX_MIP_FILTER_LINEAR = 0x2,
+ SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 0x3,
+} SQ_TEX_MIP_FILTER;
+typedef enum SQ_TEX_ANISO_RATIO {
+ SQ_TEX_ANISO_RATIO_1 = 0x0,
+ SQ_TEX_ANISO_RATIO_2 = 0x1,
+ SQ_TEX_ANISO_RATIO_4 = 0x2,
+ SQ_TEX_ANISO_RATIO_8 = 0x3,
+ SQ_TEX_ANISO_RATIO_16 = 0x4,
+} SQ_TEX_ANISO_RATIO;
+typedef enum SQ_TEX_DEPTH_COMPARE {
+ SQ_TEX_DEPTH_COMPARE_NEVER = 0x0,
+ SQ_TEX_DEPTH_COMPARE_LESS = 0x1,
+ SQ_TEX_DEPTH_COMPARE_EQUAL = 0x2,
+ SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x3,
+ SQ_TEX_DEPTH_COMPARE_GREATER = 0x4,
+ SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x5,
+ SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x6,
+ SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x7,
+} SQ_TEX_DEPTH_COMPARE;
+typedef enum SQ_TEX_BORDER_COLOR {
+ SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x0,
+ SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x1,
+ SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x2,
+ SQ_TEX_BORDER_COLOR_REGISTER = 0x3,
+} SQ_TEX_BORDER_COLOR;
+typedef enum SQ_RSRC_BUF_TYPE {
+ SQ_RSRC_BUF = 0x0,
+ SQ_RSRC_BUF_RSVD_1 = 0x1,
+ SQ_RSRC_BUF_RSVD_2 = 0x2,
+ SQ_RSRC_BUF_RSVD_3 = 0x3,
+} SQ_RSRC_BUF_TYPE;
+typedef enum SQ_RSRC_IMG_TYPE {
+ SQ_RSRC_IMG_RSVD_0 = 0x0,
+ SQ_RSRC_IMG_RSVD_1 = 0x1,
+ SQ_RSRC_IMG_RSVD_2 = 0x2,
+ SQ_RSRC_IMG_RSVD_3 = 0x3,
+ SQ_RSRC_IMG_RSVD_4 = 0x4,
+ SQ_RSRC_IMG_RSVD_5 = 0x5,
+ SQ_RSRC_IMG_RSVD_6 = 0x6,
+ SQ_RSRC_IMG_RSVD_7 = 0x7,
+ SQ_RSRC_IMG_1D = 0x8,
+ SQ_RSRC_IMG_2D = 0x9,
+ SQ_RSRC_IMG_3D = 0xa,
+ SQ_RSRC_IMG_CUBE = 0xb,
+ SQ_RSRC_IMG_1D_ARRAY = 0xc,
+ SQ_RSRC_IMG_2D_ARRAY = 0xd,
+ SQ_RSRC_IMG_2D_MSAA = 0xe,
+ SQ_RSRC_IMG_2D_MSAA_ARRAY = 0xf,
+} SQ_RSRC_IMG_TYPE;
+typedef enum SQ_RSRC_FLAT_TYPE {
+ SQ_RSRC_FLAT_RSVD_0 = 0x0,
+ SQ_RSRC_FLAT = 0x1,
+ SQ_RSRC_FLAT_RSVD_2 = 0x2,
+ SQ_RSRC_FLAT_RSVD_3 = 0x3,
+} SQ_RSRC_FLAT_TYPE;
+typedef enum SQ_IMG_FILTER_TYPE {
+ SQ_IMG_FILTER_MODE_BLEND = 0x0,
+ SQ_IMG_FILTER_MODE_MIN = 0x1,
+ SQ_IMG_FILTER_MODE_MAX = 0x2,
+} SQ_IMG_FILTER_TYPE;
+typedef enum SQ_SEL_XYZW01 {
+ SQ_SEL_0 = 0x0,
+ SQ_SEL_1 = 0x1,
+ SQ_SEL_RESERVED_0 = 0x2,
+ SQ_SEL_RESERVED_1 = 0x3,
+ SQ_SEL_X = 0x4,
+ SQ_SEL_Y = 0x5,
+ SQ_SEL_Z = 0x6,
+ SQ_SEL_W = 0x7,
+} SQ_SEL_XYZW01;
+typedef enum SQ_WAVE_TYPE {
+ SQ_WAVE_TYPE_PS = 0x0,
+ SQ_WAVE_TYPE_VS = 0x1,
+ SQ_WAVE_TYPE_GS = 0x2,
+ SQ_WAVE_TYPE_ES = 0x3,
+ SQ_WAVE_TYPE_HS = 0x4,
+ SQ_WAVE_TYPE_LS = 0x5,
+ SQ_WAVE_TYPE_CS = 0x6,
+ SQ_WAVE_TYPE_PS1 = 0x7,
+} SQ_WAVE_TYPE;
+typedef enum SQ_THREAD_TRACE_TOKEN_TYPE {
+ SQ_THREAD_TRACE_TOKEN_MISC = 0x0,
+ SQ_THREAD_TRACE_TOKEN_TIMESTAMP = 0x1,
+ SQ_THREAD_TRACE_TOKEN_REG = 0x2,
+ SQ_THREAD_TRACE_TOKEN_WAVE_START = 0x3,
+ SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC = 0x4,
+ SQ_THREAD_TRACE_TOKEN_REG_CSPRIV = 0x5,
+ SQ_THREAD_TRACE_TOKEN_WAVE_END = 0x6,
+ SQ_THREAD_TRACE_TOKEN_EVENT = 0x7,
+ SQ_THREAD_TRACE_TOKEN_EVENT_CS = 0x8,
+ SQ_THREAD_TRACE_TOKEN_EVENT_GFX1 = 0x9,
+ SQ_THREAD_TRACE_TOKEN_INST = 0xa,
+ SQ_THREAD_TRACE_TOKEN_INST_PC = 0xb,
+ SQ_THREAD_TRACE_TOKEN_INST_USERDATA = 0xc,
+ SQ_THREAD_TRACE_TOKEN_ISSUE = 0xd,
+ SQ_THREAD_TRACE_TOKEN_PERF = 0xe,
+ SQ_THREAD_TRACE_TOKEN_REG_CS = 0xf,
+} SQ_THREAD_TRACE_TOKEN_TYPE;
+typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE {
+ SQ_THREAD_TRACE_MISC_TOKEN_TIME = 0x0,
+ SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET = 0x1,
+ SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST = 0x2,
+ SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC = 0x3,
+ SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN = 0x4,
+ SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END = 0x5,
+ SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX = 0x6,
+ SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN = 0x7,
+} SQ_THREAD_TRACE_MISC_TOKEN_TYPE;
+typedef enum SQ_THREAD_TRACE_INST_TYPE {
+ SQ_THREAD_TRACE_INST_TYPE_SMEM_RD = 0x0,
+ SQ_THREAD_TRACE_INST_TYPE_SALU_32 = 0x1,
+ SQ_THREAD_TRACE_INST_TYPE_VMEM_RD = 0x2,
+ SQ_THREAD_TRACE_INST_TYPE_VMEM_WR = 0x3,
+ SQ_THREAD_TRACE_INST_TYPE_FLAT_WR = 0x4,
+ SQ_THREAD_TRACE_INST_TYPE_VALU_32 = 0x5,
+ SQ_THREAD_TRACE_INST_TYPE_LDS = 0x6,
+ SQ_THREAD_TRACE_INST_TYPE_PC = 0x7,
+ SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS = 0x8,
+ SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX = 0x9,
+ SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 0xa,
+ SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 0xb,
+ SQ_THREAD_TRACE_INST_TYPE_JUMP = 0xc,
+ SQ_THREAD_TRACE_INST_TYPE_NEXT = 0xd,
+ SQ_THREAD_TRACE_INST_TYPE_FLAT_RD = 0xe,
+ SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG = 0xf,
+ SQ_THREAD_TRACE_INST_TYPE_SMEM_WR = 0x10,
+ SQ_THREAD_TRACE_INST_TYPE_SALU_64 = 0x11,
+ SQ_THREAD_TRACE_INST_TYPE_VALU_64 = 0x12,
+ SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY = 0x13,
+ SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY = 0x14,
+ SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY = 0x15,
+ SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY = 0x16,
+ SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY = 0x17,
+ SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY = 0x18,
+} SQ_THREAD_TRACE_INST_TYPE;
+typedef enum SQ_THREAD_TRACE_REG_TYPE {
+ SQ_THREAD_TRACE_REG_TYPE_EVENT = 0x0,
+ SQ_THREAD_TRACE_REG_TYPE_DRAW = 0x1,
+ SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 0x2,
+ SQ_THREAD_TRACE_REG_TYPE_USERDATA = 0x3,
+ SQ_THREAD_TRACE_REG_TYPE_MARKER = 0x4,
+ SQ_THREAD_TRACE_REG_TYPE_GFXDEC = 0x5,
+ SQ_THREAD_TRACE_REG_TYPE_SHDEC = 0x6,
+ SQ_THREAD_TRACE_REG_TYPE_OTHER = 0x7,
+} SQ_THREAD_TRACE_REG_TYPE;
+typedef enum SQ_THREAD_TRACE_REG_OP {
+ SQ_THREAD_TRACE_REG_OP_READ = 0x0,
+ SQ_THREAD_TRACE_REG_OP_WRITE = 0x1,
+} SQ_THREAD_TRACE_REG_OP;
+typedef enum SQ_THREAD_TRACE_MODE_SEL {
+ SQ_THREAD_TRACE_MODE_OFF = 0x0,
+ SQ_THREAD_TRACE_MODE_ON = 0x1,
+} SQ_THREAD_TRACE_MODE_SEL;
+typedef enum SQ_THREAD_TRACE_CAPTURE_MODE {
+ SQ_THREAD_TRACE_CAPTURE_MODE_ALL = 0x0,
+ SQ_THREAD_TRACE_CAPTURE_MODE_SELECT = 0x1,
+ SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 0x2,
+} SQ_THREAD_TRACE_CAPTURE_MODE;
+typedef enum SQ_THREAD_TRACE_VM_ID_MASK {
+ SQ_THREAD_TRACE_VM_ID_MASK_SINGLE = 0x0,
+ SQ_THREAD_TRACE_VM_ID_MASK_ALL = 0x1,
+ SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 0x2,
+} SQ_THREAD_TRACE_VM_ID_MASK;
+typedef enum SQ_THREAD_TRACE_WAVE_MASK {
+ SQ_THREAD_TRACE_WAVE_MASK_NONE = 0x0,
+ SQ_THREAD_TRACE_WAVE_MASK_ALL = 0x1,
+} SQ_THREAD_TRACE_WAVE_MASK;
+typedef enum SQ_THREAD_TRACE_ISSUE {
+ SQ_THREAD_TRACE_ISSUE_NULL = 0x0,
+ SQ_THREAD_TRACE_ISSUE_STALL = 0x1,
+ SQ_THREAD_TRACE_ISSUE_INST = 0x2,
+ SQ_THREAD_TRACE_ISSUE_IMMED = 0x3,
+} SQ_THREAD_TRACE_ISSUE;
+typedef enum SQ_THREAD_TRACE_ISSUE_MASK {
+ SQ_THREAD_TRACE_ISSUE_MASK_ALL = 0x0,
+ SQ_THREAD_TRACE_ISSUE_MASK_STALLED = 0x1,
+ SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 0x2,
+ SQ_THREAD_TRACE_ISSUE_MASK_IMMED = 0x3,
+} SQ_THREAD_TRACE_ISSUE_MASK;
+typedef enum SQ_PERF_SEL {
+ SQ_PERF_SEL_NONE = 0x0,
+ SQ_PERF_SEL_ACCUM_PREV = 0x1,
+ SQ_PERF_SEL_CYCLES = 0x2,
+ SQ_PERF_SEL_BUSY_CYCLES = 0x3,
+ SQ_PERF_SEL_WAVES = 0x4,
+ SQ_PERF_SEL_LEVEL_WAVES = 0x5,
+ SQ_PERF_SEL_WAVES_EQ_64 = 0x6,
+ SQ_PERF_SEL_WAVES_LT_64 = 0x7,
+ SQ_PERF_SEL_WAVES_LT_48 = 0x8,
+ SQ_PERF_SEL_WAVES_LT_32 = 0x9,
+ SQ_PERF_SEL_WAVES_LT_16 = 0xa,
+ SQ_PERF_SEL_WAVES_CU = 0xb,
+ SQ_PERF_SEL_LEVEL_WAVES_CU = 0xc,
+ SQ_PERF_SEL_BUSY_CU_CYCLES = 0xd,
+ SQ_PERF_SEL_ITEMS = 0xe,
+ SQ_PERF_SEL_QUADS = 0xf,
+ SQ_PERF_SEL_EVENTS = 0x10,
+ SQ_PERF_SEL_SURF_SYNCS = 0x11,
+ SQ_PERF_SEL_TTRACE_REQS = 0x12,
+ SQ_PERF_SEL_TTRACE_INFLIGHT_REQS = 0x13,
+ SQ_PERF_SEL_TTRACE_STALL = 0x14,
+ SQ_PERF_SEL_MSG_CNTR = 0x15,
+ SQ_PERF_SEL_MSG_PERF = 0x16,
+ SQ_PERF_SEL_MSG_GSCNT = 0x17,
+ SQ_PERF_SEL_MSG_INTERRUPT = 0x18,
+ SQ_PERF_SEL_INSTS = 0x19,
+ SQ_PERF_SEL_INSTS_VALU = 0x1a,
+ SQ_PERF_SEL_INSTS_VMEM_WR = 0x1b,
+ SQ_PERF_SEL_INSTS_VMEM_RD = 0x1c,
+ SQ_PERF_SEL_INSTS_VMEM = 0x1d,
+ SQ_PERF_SEL_INSTS_SALU = 0x1e,
+ SQ_PERF_SEL_INSTS_SMEM = 0x1f,
+ SQ_PERF_SEL_INSTS_FLAT = 0x20,
+ SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY = 0x21,
+ SQ_PERF_SEL_INSTS_LDS = 0x22,
+ SQ_PERF_SEL_INSTS_GDS = 0x23,
+ SQ_PERF_SEL_INSTS_EXP = 0x24,
+ SQ_PERF_SEL_INSTS_EXP_GDS = 0x25,
+ SQ_PERF_SEL_INSTS_BRANCH = 0x26,
+ SQ_PERF_SEL_INSTS_SENDMSG = 0x27,
+ SQ_PERF_SEL_INSTS_VSKIPPED = 0x28,
+ SQ_PERF_SEL_INST_LEVEL_VMEM = 0x29,
+ SQ_PERF_SEL_INST_LEVEL_SMEM = 0x2a,
+ SQ_PERF_SEL_INST_LEVEL_LDS = 0x2b,
+ SQ_PERF_SEL_INST_LEVEL_GDS = 0x2c,
+ SQ_PERF_SEL_INST_LEVEL_EXP = 0x2d,
+ SQ_PERF_SEL_WAVE_CYCLES = 0x2e,
+ SQ_PERF_SEL_WAVE_READY = 0x2f,
+ SQ_PERF_SEL_WAIT_CNT_VM = 0x30,
+ SQ_PERF_SEL_WAIT_CNT_LGKM = 0x31,
+ SQ_PERF_SEL_WAIT_CNT_EXP = 0x32,
+ SQ_PERF_SEL_WAIT_CNT_ANY = 0x33,
+ SQ_PERF_SEL_WAIT_BARRIER = 0x34,
+ SQ_PERF_SEL_WAIT_EXP_ALLOC = 0x35,
+ SQ_PERF_SEL_WAIT_SLEEP = 0x36,
+ SQ_PERF_SEL_WAIT_OTHER = 0x37,
+ SQ_PERF_SEL_WAIT_ANY = 0x38,
+ SQ_PERF_SEL_WAIT_TTRACE = 0x39,
+ SQ_PERF_SEL_WAIT_IFETCH = 0x3a,
+ SQ_PERF_SEL_WAIT_INST_VMEM = 0x3b,
+ SQ_PERF_SEL_WAIT_INST_SCA = 0x3c,
+ SQ_PERF_SEL_WAIT_INST_LDS = 0x3d,
+ SQ_PERF_SEL_WAIT_INST_VALU = 0x3e,
+ SQ_PERF_SEL_WAIT_INST_EXP_GDS = 0x3f,
+ SQ_PERF_SEL_WAIT_INST_MISC = 0x40,
+ SQ_PERF_SEL_WAIT_INST_FLAT = 0x41,
+ SQ_PERF_SEL_ACTIVE_INST_ANY = 0x42,
+ SQ_PERF_SEL_ACTIVE_INST_VMEM = 0x43,
+ SQ_PERF_SEL_ACTIVE_INST_LDS = 0x44,
+ SQ_PERF_SEL_ACTIVE_INST_VALU = 0x45,
+ SQ_PERF_SEL_ACTIVE_INST_SCA = 0x46,
+ SQ_PERF_SEL_ACTIVE_INST_EXP_GDS = 0x47,
+ SQ_PERF_SEL_ACTIVE_INST_MISC = 0x48,
+ SQ_PERF_SEL_ACTIVE_INST_FLAT = 0x49,
+ SQ_PERF_SEL_INST_CYCLES_VMEM_WR = 0x4a,
+ SQ_PERF_SEL_INST_CYCLES_VMEM_RD = 0x4b,
+ SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR = 0x4c,
+ SQ_PERF_SEL_INST_CYCLES_VMEM_DATA = 0x4d,
+ SQ_PERF_SEL_INST_CYCLES_VMEM_CMD = 0x4e,
+ SQ_PERF_SEL_INST_CYCLES_VMEM = 0x4f,
+ SQ_PERF_SEL_INST_CYCLES_LDS = 0x50,
+ SQ_PERF_SEL_INST_CYCLES_VALU = 0x51,
+ SQ_PERF_SEL_INST_CYCLES_EXP = 0x52,
+ SQ_PERF_SEL_INST_CYCLES_GDS = 0x53,
+ SQ_PERF_SEL_INST_CYCLES_SCA = 0x54,
+ SQ_PERF_SEL_INST_CYCLES_SMEM = 0x55,
+ SQ_PERF_SEL_INST_CYCLES_SALU = 0x56,
+ SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 0x57,
+ SQ_PERF_SEL_INST_CYCLES_MISC = 0x58,
+ SQ_PERF_SEL_THREAD_CYCLES_VALU = 0x59,
+ SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX = 0x5a,
+ SQ_PERF_SEL_IFETCH = 0x5b,
+ SQ_PERF_SEL_IFETCH_LEVEL = 0x5c,
+ SQ_PERF_SEL_CBRANCH_FORK = 0x5d,
+ SQ_PERF_SEL_CBRANCH_FORK_SPLIT = 0x5e,
+ SQ_PERF_SEL_VALU_LDS_DIRECT_RD = 0x5f,
+ SQ_PERF_SEL_VALU_LDS_INTERP_OP = 0x60,
+ SQ_PERF_SEL_LDS_BANK_CONFLICT = 0x61,
+ SQ_PERF_SEL_LDS_ADDR_CONFLICT = 0x62,
+ SQ_PERF_SEL_LDS_UNALIGNED_STALL = 0x63,
+ SQ_PERF_SEL_LDS_MEM_VIOLATIONS = 0x64,
+ SQ_PERF_SEL_LDS_ATOMIC_RETURN = 0x65,
+ SQ_PERF_SEL_LDS_IDX_ACTIVE = 0x66,
+ SQ_PERF_SEL_VALU_DEP_STALL = 0x67,
+ SQ_PERF_SEL_VALU_STARVE = 0x68,
+ SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 0x69,
+ SQ_PERF_SEL_LDS_BACK2BACK_STALL = 0x6a,
+ SQ_PERF_SEL_LDS_DATA_FIFO_FULL = 0x6b,
+ SQ_PERF_SEL_LDS_CMD_FIFO_FULL = 0x6c,
+ SQ_PERF_SEL_VMEM_BACK2BACK_STALL = 0x6d,
+ SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL = 0x6e,
+ SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL = 0x6f,
+ SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY = 0x70,
+ SQ_PERF_SEL_VMEM_WR_BACK2BACK_STALL = 0x71,
+ SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL = 0x72,
+ SQ_PERF_SEL_VALU_SRC_C_CONFLICT = 0x73,
+ SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT = 0x74,
+ SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT = 0x75,
+ SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT = 0x76,
+ SQ_PERF_SEL_LDS_SRC_CD_CONFLICT = 0x77,
+ SQ_PERF_SEL_SRC_CD_BUSY = 0x78,
+ SQ_PERF_SEL_PT_POWER_STALL = 0x79,
+ SQ_PERF_SEL_USER0 = 0x7a,
+ SQ_PERF_SEL_USER1 = 0x7b,
+ SQ_PERF_SEL_USER2 = 0x7c,
+ SQ_PERF_SEL_USER3 = 0x7d,
+ SQ_PERF_SEL_USER4 = 0x7e,
+ SQ_PERF_SEL_USER5 = 0x7f,
+ SQ_PERF_SEL_USER6 = 0x80,
+ SQ_PERF_SEL_USER7 = 0x81,
+ SQ_PERF_SEL_USER8 = 0x82,
+ SQ_PERF_SEL_USER9 = 0x83,
+ SQ_PERF_SEL_USER10 = 0x84,
+ SQ_PERF_SEL_USER11 = 0x85,
+ SQ_PERF_SEL_USER12 = 0x86,
+ SQ_PERF_SEL_USER13 = 0x87,
+ SQ_PERF_SEL_USER14 = 0x88,
+ SQ_PERF_SEL_USER15 = 0x89,
+ SQ_PERF_SEL_USER_LEVEL0 = 0x8a,
+ SQ_PERF_SEL_USER_LEVEL1 = 0x8b,
+ SQ_PERF_SEL_USER_LEVEL2 = 0x8c,
+ SQ_PERF_SEL_USER_LEVEL3 = 0x8d,
+ SQ_PERF_SEL_USER_LEVEL4 = 0x8e,
+ SQ_PERF_SEL_USER_LEVEL5 = 0x8f,
+ SQ_PERF_SEL_USER_LEVEL6 = 0x90,
+ SQ_PERF_SEL_USER_LEVEL7 = 0x91,
+ SQ_PERF_SEL_USER_LEVEL8 = 0x92,
+ SQ_PERF_SEL_USER_LEVEL9 = 0x93,
+ SQ_PERF_SEL_USER_LEVEL10 = 0x94,
+ SQ_PERF_SEL_USER_LEVEL11 = 0x95,
+ SQ_PERF_SEL_USER_LEVEL12 = 0x96,
+ SQ_PERF_SEL_USER_LEVEL13 = 0x97,
+ SQ_PERF_SEL_USER_LEVEL14 = 0x98,
+ SQ_PERF_SEL_USER_LEVEL15 = 0x99,
+ SQ_PERF_SEL_POWER_VALU = 0x9a,
+ SQ_PERF_SEL_POWER_VALU0 = 0x9b,
+ SQ_PERF_SEL_POWER_VALU1 = 0x9c,
+ SQ_PERF_SEL_POWER_VALU2 = 0x9d,
+ SQ_PERF_SEL_POWER_GPR_RD = 0x9e,
+ SQ_PERF_SEL_POWER_GPR_WR = 0x9f,
+ SQ_PERF_SEL_POWER_LDS_BUSY = 0xa0,
+ SQ_PERF_SEL_POWER_ALU_BUSY = 0xa1,
+ SQ_PERF_SEL_POWER_TEX_BUSY = 0xa2,
+ SQ_PERF_SEL_ACCUM_PREV_HIRES = 0xa3,
+ SQ_PERF_SEL_WAVES_RESTORED = 0xa4,
+ SQ_PERF_SEL_WAVES_SAVED = 0xa5,
+ SQ_PERF_SEL_DUMMY_LAST = 0xa7,
+ SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 0xa8,
+ SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 0xa9,
+ SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 0xaa,
+ SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 0xab,
+ SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 0xac,
+ SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 0xad,
+ SQC_PERF_SEL_TC_REQ = 0xae,
+ SQC_PERF_SEL_TC_INST_REQ = 0xaf,
+ SQC_PERF_SEL_TC_DATA_READ_REQ = 0xb0,
+ SQC_PERF_SEL_TC_DATA_WRITE_REQ = 0xb1,
+ SQC_PERF_SEL_TC_DATA_ATOMIC_REQ = 0xb2,
+ SQC_PERF_SEL_TC_STALL = 0xb3,
+ SQC_PERF_SEL_TC_STARVE = 0xb4,
+ SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 0xb5,
+ SQC_PERF_SEL_ICACHE_REQ = 0xb6,
+ SQC_PERF_SEL_ICACHE_HITS = 0xb7,
+ SQC_PERF_SEL_ICACHE_MISSES = 0xb8,
+ SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 0xb9,
+ SQC_PERF_SEL_ICACHE_INVAL_INST = 0xba,
+ SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 0xbb,
+ SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0xbc,
+ SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0xbd,
+ SQC_PERF_SEL_ICACHE_CACHE_STALLED = 0xbe,
+ SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 0xbf,
+ SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0xc0,
+ SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 0xc1,
+ SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xc2,
+ SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0xc3,
+ SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 0xc4,
+ SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0xc5,
+ SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 0xc6,
+ SQC_PERF_SEL_DCACHE_REQ = 0xc7,
+ SQC_PERF_SEL_DCACHE_HITS = 0xc8,
+ SQC_PERF_SEL_DCACHE_MISSES = 0xc9,
+ SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 0xca,
+ SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 0xcb,
+ SQC_PERF_SEL_DCACHE_MISS_EVICT_READ = 0xcc,
+ SQC_PERF_SEL_DCACHE_WC_LRU_WRITE = 0xcd,
+ SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE = 0xce,
+ SQC_PERF_SEL_DCACHE_ATOMIC = 0xcf,
+ SQC_PERF_SEL_DCACHE_VOLATILE = 0xd0,
+ SQC_PERF_SEL_DCACHE_INVAL_INST = 0xd1,
+ SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 0xd2,
+ SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST = 0xd3,
+ SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC = 0xd4,
+ SQC_PERF_SEL_DCACHE_WB_INST = 0xd5,
+ SQC_PERF_SEL_DCACHE_WB_ASYNC = 0xd6,
+ SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST = 0xd7,
+ SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC = 0xd8,
+ SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0xd9,
+ SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0xda,
+ SQC_PERF_SEL_DCACHE_CACHE_STALLED = 0xdb,
+ SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0xdc,
+ SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 0xdd,
+ SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT = 0xde,
+ SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED = 0xdf,
+ SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE= 0xe0,
+ SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT = 0xe1,
+ SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH = 0xe2,
+ SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE = 0xe3,
+ SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xe4,
+ SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0xe5,
+ SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 0xe6,
+ SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0xe7,
+ SQC_PERF_SEL_DCACHE_REQ_READ_1 = 0xe8,
+ SQC_PERF_SEL_DCACHE_REQ_READ_2 = 0xe9,
+ SQC_PERF_SEL_DCACHE_REQ_READ_4 = 0xea,
+ SQC_PERF_SEL_DCACHE_REQ_READ_8 = 0xeb,
+ SQC_PERF_SEL_DCACHE_REQ_READ_16 = 0xec,
+ SQC_PERF_SEL_DCACHE_REQ_TIME = 0xed,
+ SQC_PERF_SEL_DCACHE_REQ_WRITE_1 = 0xee,
+ SQC_PERF_SEL_DCACHE_REQ_WRITE_2 = 0xef,
+ SQC_PERF_SEL_DCACHE_REQ_WRITE_4 = 0xf0,
+ SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 0xf1,
+ SQC_PERF_SEL_SQ_DCACHE_REQS = 0xf2,
+ SQC_PERF_SEL_DCACHE_FLAT_REQ = 0xf3,
+ SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 0xf4,
+ SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 0xf5,
+ SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 0xf6,
+ SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 0xf7,
+ SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 0xf8,
+ SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 0xf9,
+ SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS = 0xfa,
+ SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS = 0xfb,
+ SQC_PERF_SEL_ICACHE_GATCL1_REQUEST = 0xfc,
+ SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX = 0xfd,
+ SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT = 0xfe,
+ SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL = 0xff,
+ SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x100,
+ SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0x101,
+ SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT = 0x102,
+ SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL = 0x103,
+ SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS = 0x104,
+ SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS = 0x105,
+ SQC_PERF_SEL_DCACHE_GATCL1_REQUEST = 0x106,
+ SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX = 0x107,
+ SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT = 0x108,
+ SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL = 0x109,
+ SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x10a,
+ SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0x10b,
+ SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT = 0x10c,
+ SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL = 0x10d,
+ SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS = 0x10e,
+ SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL = 0x10f,
+ SQC_PERF_SEL_DUMMY_LAST = 0x110,
+ SQ_PERF_SEL_INSTS_SMEM_NORM = 0x111,
+ SQ_PERF_SEL_ATC_INSTS_VMEM = 0x112,
+ SQ_PERF_SEL_ATC_INST_LEVEL_VMEM = 0x113,
+ SQ_PERF_SEL_ATC_XNACK_FIRST = 0x114,
+ SQ_PERF_SEL_ATC_XNACK_ALL = 0x115,
+ SQ_PERF_SEL_ATC_XNACK_FIFO_FULL = 0x116,
+ SQ_PERF_SEL_ATC_INSTS_SMEM = 0x117,
+ SQ_PERF_SEL_ATC_INST_LEVEL_SMEM = 0x118,
+ SQ_PERF_SEL_IFETCH_XNACK = 0x119,
+ SQ_PERF_SEL_TLB_SHOOTDOWN = 0x11a,
+ SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES = 0x11b,
+ SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY = 0x11c,
+ SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY = 0x11d,
+ SQ_PERF_SEL_INSTS_VMEM_REPLAY = 0x11e,
+ SQ_PERF_SEL_INSTS_SMEM_REPLAY = 0x11f,
+ SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY = 0x120,
+ SQ_PERF_SEL_INSTS_FLAT_REPLAY = 0x121,
+ SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY = 0x122,
+ SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY = 0x123,
+ SQ_PERF_SEL_DUMMY_LAST1 = 0x12a,
+} SQ_PERF_SEL;
+typedef enum SQ_CAC_POWER_SEL {
+ SQ_CAC_POWER_VALU = 0x0,
+ SQ_CAC_POWER_VALU0 = 0x1,
+ SQ_CAC_POWER_VALU1 = 0x2,
+ SQ_CAC_POWER_VALU2 = 0x3,
+ SQ_CAC_POWER_GPR_RD = 0x4,
+ SQ_CAC_POWER_GPR_WR = 0x5,
+ SQ_CAC_POWER_LDS_BUSY = 0x6,
+ SQ_CAC_POWER_ALU_BUSY = 0x7,
+ SQ_CAC_POWER_TEX_BUSY = 0x8,
+} SQ_CAC_POWER_SEL;
+typedef enum SQ_IND_CMD_CMD {
+ SQ_IND_CMD_CMD_NULL = 0x0,
+ SQ_IND_CMD_CMD_SETHALT = 0x1,
+ SQ_IND_CMD_CMD_SAVECTX = 0x2,
+ SQ_IND_CMD_CMD_KILL = 0x3,
+ SQ_IND_CMD_CMD_DEBUG = 0x4,
+ SQ_IND_CMD_CMD_TRAP = 0x5,
+ SQ_IND_CMD_CMD_SET_SPI_PRIO = 0x6,
+} SQ_IND_CMD_CMD;
+typedef enum SQ_IND_CMD_MODE {
+ SQ_IND_CMD_MODE_SINGLE = 0x0,
+ SQ_IND_CMD_MODE_BROADCAST = 0x1,
+ SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x2,
+ SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x3,
+ SQ_IND_CMD_MODE_BROADCAST_ME = 0x4,
+} SQ_IND_CMD_MODE;
+typedef enum SQ_EDC_INFO_SOURCE {
+ SQ_EDC_INFO_SOURCE_INVALID = 0x0,
+ SQ_EDC_INFO_SOURCE_INST = 0x1,
+ SQ_EDC_INFO_SOURCE_SGPR = 0x2,
+ SQ_EDC_INFO_SOURCE_VGPR = 0x3,
+ SQ_EDC_INFO_SOURCE_LDS = 0x4,
+ SQ_EDC_INFO_SOURCE_GDS = 0x5,
+ SQ_EDC_INFO_SOURCE_TA = 0x6,
+} SQ_EDC_INFO_SOURCE;
+typedef enum SQ_ROUND_MODE {
+ SQ_ROUND_NEAREST_EVEN = 0x0,
+ SQ_ROUND_PLUS_INFINITY = 0x1,
+ SQ_ROUND_MINUS_INFINITY = 0x2,
+ SQ_ROUND_TO_ZERO = 0x3,
+} SQ_ROUND_MODE;
+typedef enum SQ_INTERRUPT_WORD_ENCODING {
+ SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0,
+ SQ_INTERRUPT_WORD_ENCODING_INST = 0x1,
+ SQ_INTERRUPT_WORD_ENCODING_ERROR = 0x2,
+} SQ_INTERRUPT_WORD_ENCODING;
+typedef enum ENUM_SQ_EXPORT_RAT_INST {
+ SQ_EXPORT_RAT_INST_NOP = 0x0,
+ SQ_EXPORT_RAT_INST_STORE_TYPED = 0x1,
+ SQ_EXPORT_RAT_INST_STORE_RAW = 0x2,
+ SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 0x3,
+ SQ_EXPORT_RAT_INST_CMPXCHG_INT = 0x4,
+ SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 0x5,
+ SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 0x6,
+ SQ_EXPORT_RAT_INST_ADD = 0x7,
+ SQ_EXPORT_RAT_INST_SUB = 0x8,
+ SQ_EXPORT_RAT_INST_RSUB = 0x9,
+ SQ_EXPORT_RAT_INST_MIN_INT = 0xa,
+ SQ_EXPORT_RAT_INST_MIN_UINT = 0xb,
+ SQ_EXPORT_RAT_INST_MAX_INT = 0xc,
+ SQ_EXPORT_RAT_INST_MAX_UINT = 0xd,
+ SQ_EXPORT_RAT_INST_AND = 0xe,
+ SQ_EXPORT_RAT_INST_OR = 0xf,
+ SQ_EXPORT_RAT_INST_XOR = 0x10,
+ SQ_EXPORT_RAT_INST_MSKOR = 0x11,
+ SQ_EXPORT_RAT_INST_INC_UINT = 0x12,
+ SQ_EXPORT_RAT_INST_DEC_UINT = 0x13,
+ SQ_EXPORT_RAT_INST_STORE_DWORD = 0x14,
+ SQ_EXPORT_RAT_INST_STORE_SHORT = 0x15,
+ SQ_EXPORT_RAT_INST_STORE_BYTE = 0x16,
+ SQ_EXPORT_RAT_INST_NOP_RTN = 0x20,
+ SQ_EXPORT_RAT_INST_XCHG_RTN = 0x22,
+ SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 0x23,
+ SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 0x24,
+ SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 0x25,
+ SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 0x26,
+ SQ_EXPORT_RAT_INST_ADD_RTN = 0x27,
+ SQ_EXPORT_RAT_INST_SUB_RTN = 0x28,
+ SQ_EXPORT_RAT_INST_RSUB_RTN = 0x29,
+ SQ_EXPORT_RAT_INST_MIN_INT_RTN = 0x2a,
+ SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 0x2b,
+ SQ_EXPORT_RAT_INST_MAX_INT_RTN = 0x2c,
+ SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 0x2d,
+ SQ_EXPORT_RAT_INST_AND_RTN = 0x2e,
+ SQ_EXPORT_RAT_INST_OR_RTN = 0x2f,
+ SQ_EXPORT_RAT_INST_XOR_RTN = 0x30,
+ SQ_EXPORT_RAT_INST_MSKOR_RTN = 0x31,
+ SQ_EXPORT_RAT_INST_INC_UINT_RTN = 0x32,
+ SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 0x33,
+} ENUM_SQ_EXPORT_RAT_INST;
+typedef enum SQ_IBUF_ST {
+ SQ_IBUF_IB_IDLE = 0x0,
+ SQ_IBUF_IB_INI_WAIT_GNT = 0x1,
+ SQ_IBUF_IB_INI_WAIT_DRET = 0x2,
+ SQ_IBUF_IB_LE_4DW = 0x3,
+ SQ_IBUF_IB_WAIT_DRET = 0x4,
+ SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x5,
+ SQ_IBUF_IB_DRET = 0x6,
+ SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x7,
+} SQ_IBUF_ST;
+typedef enum SQ_INST_STR_ST {
+ SQ_INST_STR_IB_WAVE_NORML = 0x0,
+ SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x1,
+ SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x2,
+ SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x3,
+ SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 0x4,
+ SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 0x5,
+ SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x6,
+ SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x7,
+} SQ_INST_STR_ST;
+typedef enum SQ_WAVE_IB_ECC_ST {
+ SQ_WAVE_IB_ECC_CLEAN = 0x0,
+ SQ_WAVE_IB_ECC_ERR_CONTINUE = 0x1,
+ SQ_WAVE_IB_ECC_ERR_HALT = 0x2,
+ SQ_WAVE_IB_ECC_WITH_ERR_MSG = 0x3,
+} SQ_WAVE_IB_ECC_ST;
+typedef enum SH_MEM_ADDRESS_MODE {
+ SH_MEM_ADDRESS_MODE_GPUVM64 = 0x0,
+ SH_MEM_ADDRESS_MODE_GPUVM32 = 0x1,
+ SH_MEM_ADDRESS_MODE_HSA64 = 0x2,
+ SH_MEM_ADDRESS_MODE_HSA32 = 0x3,
+} SH_MEM_ADDRESS_MODE;
+typedef enum SH_MEM_ALIGNMENT_MODE {
+ SH_MEM_ALIGNMENT_MODE_DWORD = 0x0,
+ SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x1,
+ SH_MEM_ALIGNMENT_MODE_STRICT = 0x2,
+ SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x3,
+} SH_MEM_ALIGNMENT_MODE;
+typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX {
+ SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC = 0x18,
+ SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE = 0x19,
+} SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX;
+#define SQ_WAVE_TYPE_PS0 0x0
+#define SQIND_GLOBAL_REGS_OFFSET 0x0
+#define SQIND_GLOBAL_REGS_SIZE 0x8
+#define SQIND_LOCAL_REGS_OFFSET 0x8
+#define SQIND_LOCAL_REGS_SIZE 0x8
+#define SQIND_WAVE_HWREGS_OFFSET 0x10
+#define SQIND_WAVE_HWREGS_SIZE 0x1f0
+#define SQIND_WAVE_SGPRS_OFFSET 0x200
+#define SQIND_WAVE_SGPRS_SIZE 0x200
+#define SQ_GFXDEC_BEGIN 0xa000
+#define SQ_GFXDEC_END 0xc000
+#define SQ_GFXDEC_STATE_ID_SHIFT 0xa
+#define SQDEC_BEGIN 0x2300
+#define SQDEC_END 0x23ff
+#define SQPERFSDEC_BEGIN 0xd9c0
+#define SQPERFSDEC_END 0xda40
+#define SQPERFDDEC_BEGIN 0xd1c0
+#define SQPERFDDEC_END 0xd240
+#define SQGFXUDEC_BEGIN 0xc330
+#define SQGFXUDEC_END 0xc380
+#define SQPWRDEC_BEGIN 0xf08c
+#define SQPWRDEC_END 0xf094
+#define SQ_DISPATCHER_GFX_MIN 0x10
+#define SQ_DISPATCHER_GFX_CNT_PER_RING 0x8
+#define SQ_MAX_PGM_SGPRS 0x68
+#define SQ_MAX_PGM_VGPRS 0x100
+#define SQ_THREAD_TRACE_TIME_UNIT 0x4
+#define SQ_EX_MODE_EXCP_VALU_BASE 0x0
+#define SQ_EX_MODE_EXCP_VALU_SIZE 0x7
+#define SQ_EX_MODE_EXCP_INVALID 0x0
+#define SQ_EX_MODE_EXCP_INPUT_DENORM 0x1
+#define SQ_EX_MODE_EXCP_DIV0 0x2
+#define SQ_EX_MODE_EXCP_OVERFLOW 0x3
+#define SQ_EX_MODE_EXCP_UNDERFLOW 0x4
+#define SQ_EX_MODE_EXCP_INEXACT 0x5
+#define SQ_EX_MODE_EXCP_INT_DIV0 0x6
+#define SQ_EX_MODE_EXCP_ADDR_WATCH 0x7
+#define SQ_EX_MODE_EXCP_MEM_VIOL 0x8
+#define INST_ID_PRIV_START 0x80000000
+#define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0
+#define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1
+#define INST_ID_HW_TRAP 0xfffffff2
+#define INST_ID_KILL_SEQ 0xfffffff3
+#define INST_ID_SPI_WREXEC 0xfffffff4
+#define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe
+#define SQ_ENC_SOP1_BITS 0xbe800000
+#define SQ_ENC_SOP1_MASK 0xff800000
+#define SQ_ENC_SOP1_FIELD 0x17d
+#define SQ_ENC_SOPC_BITS 0xbf000000
+#define SQ_ENC_SOPC_MASK 0xff800000
+#define SQ_ENC_SOPC_FIELD 0x17e
+#define SQ_ENC_SOPP_BITS 0xbf800000
+#define SQ_ENC_SOPP_MASK 0xff800000
+#define SQ_ENC_SOPP_FIELD 0x17f
+#define SQ_ENC_SOPK_BITS 0xb0000000
+#define SQ_ENC_SOPK_MASK 0xf0000000
+#define SQ_ENC_SOPK_FIELD 0xb
+#define SQ_ENC_SOP2_BITS 0x80000000
+#define SQ_ENC_SOP2_MASK 0xc0000000
+#define SQ_ENC_SOP2_FIELD 0x2
+#define SQ_ENC_SMEM_BITS 0xc0000000
+#define SQ_ENC_SMEM_MASK 0xfc000000
+#define SQ_ENC_SMEM_FIELD 0x30
+#define SQ_ENC_VOP1_BITS 0x7e000000
+#define SQ_ENC_VOP1_MASK 0xfe000000
+#define SQ_ENC_VOP1_FIELD 0x3f
+#define SQ_ENC_VOPC_BITS 0x7c000000
+#define SQ_ENC_VOPC_MASK 0xfe000000
+#define SQ_ENC_VOPC_FIELD 0x3e
+#define SQ_ENC_VOP2_BITS 0x0
+#define SQ_ENC_VOP2_MASK 0x80000000
+#define SQ_ENC_VOP2_FIELD 0x0
+#define SQ_ENC_VINTRP_BITS 0xd4000000
+#define SQ_ENC_VINTRP_MASK 0xfc000000
+#define SQ_ENC_VINTRP_FIELD 0x35
+#define SQ_ENC_VOP3_BITS 0xd0000000
+#define SQ_ENC_VOP3_MASK 0xfc000000
+#define SQ_ENC_VOP3_FIELD 0x34
+#define SQ_ENC_DS_BITS 0xd8000000
+#define SQ_ENC_DS_MASK 0xfc000000
+#define SQ_ENC_DS_FIELD 0x36
+#define SQ_ENC_MUBUF_BITS 0xe0000000
+#define SQ_ENC_MUBUF_MASK 0xfc000000
+#define SQ_ENC_MUBUF_FIELD 0x38
+#define SQ_ENC_MTBUF_BITS 0xe8000000
+#define SQ_ENC_MTBUF_MASK 0xfc000000
+#define SQ_ENC_MTBUF_FIELD 0x3a
+#define SQ_ENC_MIMG_BITS 0xf0000000
+#define SQ_ENC_MIMG_MASK 0xfc000000
+#define SQ_ENC_MIMG_FIELD 0x3c
+#define SQ_ENC_EXP_BITS 0xc4000000
+#define SQ_ENC_EXP_MASK 0xfc000000
+#define SQ_ENC_EXP_FIELD 0x31
+#define SQ_ENC_FLAT_BITS 0xdc000000
+#define SQ_ENC_FLAT_MASK 0xfc000000
+#define SQ_ENC_FLAT_FIELD 0x37
+#define SQ_V_OP3_INTRP_OFFSET 0x274
+#define SQ_WAITCNT_VM_SHIFT 0x0
+#define SQ_SENDMSG_STREAMID_SIZE 0x2
+#define SQ_V_OPC_COUNT 0x100
+#define SQ_V_OP3_INTRP_COUNT 0xc
+#define SQ_XLATE_VOP3_TO_VOP2_OFFSET 0x100
+#define SQ_HWREG_OFFSET_SIZE 0x5
+#define SQ_HWREG_OFFSET_SHIFT 0x6
+#define SQ_V_OP3_3IN_OFFSET 0x1c0
+#define SQ_NUM_ATTR 0x21
+#define SQ_NUM_VGPR 0x100
+#define SQ_XLATE_VOP3_TO_VINTRP_COUNT 0x4
+#define SQ_SENDMSG_MSG_SIZE 0x4
+#define SQ_NUM_TTMP 0xc
+#define SQ_HWREG_ID_SIZE 0x6
+#define SQ_SENDMSG_GSOP_SIZE 0x2
+#define SQ_NUM_SGPR 0x66
+#define SQ_EXP_NUM_MRT 0x8
+#define SQ_SENDMSG_SYSTEM_SIZE 0x3
+#define SQ_WAITCNT_LGKM_SHIFT 0x8
+#define SQ_XLATE_VOP3_TO_VOP2_COUNT 0x40
+#define SQ_V_OP3_3IN_COUNT 0xb0
+#define SQ_V_INTRP_COUNT 0x4
+#define SQ_WAITCNT_EXP_SIZE 0x3
+#define SQ_SENDMSG_SYSTEM_SHIFT 0x4
+#define SQ_EXP_NUM_GDS 0x5
+#define SQ_HWREG_SIZE_SHIFT 0xb
+#define SQ_XLATE_VOP3_TO_VOPC_OFFSET 0x0
+#define SQ_V_OP3_2IN_COUNT 0x80
+#define SQ_XLATE_VOP3_TO_VINTRP_OFFSET 0x270
+#define SQ_SENDMSG_MSG_SHIFT 0x0
+#define SQ_WAITCNT_EXP_SHIFT 0x4
+#define SQ_WAITCNT_VM_SIZE 0x4
+#define SQ_XLATE_VOP3_TO_VOP1_OFFSET 0x140
+#define SQ_SENDMSG_GSOP_SHIFT 0x4
+#define SQ_XLATE_VOP3_TO_VOP1_COUNT 0x80
+#define SQ_SRC_VGPR_BIT 0x100
+#define SQ_V_OP2_COUNT 0x40
+#define SQ_EXP_NUM_PARAM 0x20
+#define SQ_V_OP1_COUNT 0x80
+#define SQ_SENDMSG_STREAMID_SHIFT 0x8
+#define SQ_V_OP3_2IN_OFFSET 0x280
+#define SQ_WAITCNT_LGKM_SIZE 0x4
+#define SQ_XLATE_VOP3_TO_VOPC_COUNT 0x100
+#define SQ_EXP_NUM_POS 0x4
+#define SQ_HWREG_SIZE_SIZE 0x5
+#define SQ_HWREG_ID_SHIFT 0x0
+#define SQ_S_MOV_B32 0x0
+#define SQ_S_MOV_B64 0x1
+#define SQ_S_CMOV_B32 0x2
+#define SQ_S_CMOV_B64 0x3
+#define SQ_S_NOT_B32 0x4
+#define SQ_S_NOT_B64 0x5
+#define SQ_S_WQM_B32 0x6
+#define SQ_S_WQM_B64 0x7
+#define SQ_S_BREV_B32 0x8
+#define SQ_S_BREV_B64 0x9
+#define SQ_S_BCNT0_I32_B32 0xa
+#define SQ_S_BCNT0_I32_B64 0xb
+#define SQ_S_BCNT1_I32_B32 0xc
+#define SQ_S_BCNT1_I32_B64 0xd
+#define SQ_S_FF0_I32_B32 0xe
+#define SQ_S_FF0_I32_B64 0xf
+#define SQ_S_FF1_I32_B32 0x10
+#define SQ_S_FF1_I32_B64 0x11
+#define SQ_S_FLBIT_I32_B32 0x12
+#define SQ_S_FLBIT_I32_B64 0x13
+#define SQ_S_FLBIT_I32 0x14
+#define SQ_S_FLBIT_I32_I64 0x15
+#define SQ_S_SEXT_I32_I8 0x16
+#define SQ_S_SEXT_I32_I16 0x17
+#define SQ_S_BITSET0_B32 0x18
+#define SQ_S_BITSET0_B64 0x19
+#define SQ_S_BITSET1_B32 0x1a
+#define SQ_S_BITSET1_B64 0x1b
+#define SQ_S_GETPC_B64 0x1c
+#define SQ_S_SETPC_B64 0x1d
+#define SQ_S_SWAPPC_B64 0x1e
+#define SQ_S_RFE_B64 0x1f
+#define SQ_S_AND_SAVEEXEC_B64 0x20
+#define SQ_S_OR_SAVEEXEC_B64 0x21
+#define SQ_S_XOR_SAVEEXEC_B64 0x22
+#define SQ_S_ANDN2_SAVEEXEC_B64 0x23
+#define SQ_S_ORN2_SAVEEXEC_B64 0x24
+#define SQ_S_NAND_SAVEEXEC_B64 0x25
+#define SQ_S_NOR_SAVEEXEC_B64 0x26
+#define SQ_S_XNOR_SAVEEXEC_B64 0x27
+#define SQ_S_QUADMASK_B32 0x28
+#define SQ_S_QUADMASK_B64 0x29
+#define SQ_S_MOVRELS_B32 0x2a
+#define SQ_S_MOVRELS_B64 0x2b
+#define SQ_S_MOVRELD_B32 0x2c
+#define SQ_S_MOVRELD_B64 0x2d
+#define SQ_S_CBRANCH_JOIN 0x2e
+#define SQ_S_MOV_REGRD_B32 0x2f
+#define SQ_S_ABS_I32 0x30
+#define SQ_S_MOV_FED_B32 0x31
+#define SQ_S_SET_GPR_IDX_IDX 0x32
+#define SQ_ATTR0 0x0
+#define SQ_S_MOVK_I32 0x0
+#define SQ_S_CMOVK_I32 0x1
+#define SQ_S_CMPK_EQ_I32 0x2
+#define SQ_S_CMPK_LG_I32 0x3
+#define SQ_S_CMPK_GT_I32 0x4
+#define SQ_S_CMPK_GE_I32 0x5
+#define SQ_S_CMPK_LT_I32 0x6
+#define SQ_S_CMPK_LE_I32 0x7
+#define SQ_S_CMPK_EQ_U32 0x8
+#define SQ_S_CMPK_LG_U32 0x9
+#define SQ_S_CMPK_GT_U32 0xa
+#define SQ_S_CMPK_GE_U32 0xb
+#define SQ_S_CMPK_LT_U32 0xc
+#define SQ_S_CMPK_LE_U32 0xd
+#define SQ_S_ADDK_I32 0xe
+#define SQ_S_MULK_I32 0xf
+#define SQ_S_CBRANCH_I_FORK 0x10
+#define SQ_S_GETREG_B32 0x11
+#define SQ_S_SETREG_B32 0x12
+#define SQ_S_GETREG_REGRD_B32 0x13
+#define SQ_S_SETREG_IMM32_B32 0x14
+#define SQ_TBA_LO 0x6c
+#define SQ_TBA_HI 0x6d
+#define SQ_TMA_LO 0x6e
+#define SQ_TMA_HI 0x6f
+#define SQ_TTMP0 0x70
+#define SQ_TTMP1 0x71
+#define SQ_TTMP2 0x72
+#define SQ_TTMP3 0x73
+#define SQ_TTMP4 0x74
+#define SQ_TTMP5 0x75
+#define SQ_TTMP6 0x76
+#define SQ_TTMP7 0x77
+#define SQ_TTMP8 0x78
+#define SQ_TTMP9 0x79
+#define SQ_TTMP10 0x7a
+#define SQ_TTMP11 0x7b
+#define SQ_VGPR0 0x0
+#define SQ_EXP 0x0
+#define SQ_EXP_MRT0 0x0
+#define SQ_EXP_MRTZ 0x8
+#define SQ_EXP_NULL 0x9
+#define SQ_EXP_POS0 0xc
+#define SQ_EXP_PARAM0 0x20
+#define SQ_CNT1 0x0
+#define SQ_CNT2 0x1
+#define SQ_CNT3 0x2
+#define SQ_CNT4 0x3
+#define SQ_S_LOAD_DWORD 0x0
+#define SQ_S_LOAD_DWORDX2 0x1
+#define SQ_S_LOAD_DWORDX4 0x2
+#define SQ_S_LOAD_DWORDX8 0x3
+#define SQ_S_LOAD_DWORDX16 0x4
+#define SQ_S_BUFFER_LOAD_DWORD 0x8
+#define SQ_S_BUFFER_LOAD_DWORDX2 0x9
+#define SQ_S_BUFFER_LOAD_DWORDX4 0xa
+#define SQ_S_BUFFER_LOAD_DWORDX8 0xb
+#define SQ_S_BUFFER_LOAD_DWORDX16 0xc
+#define SQ_S_STORE_DWORD 0x10
+#define SQ_S_STORE_DWORDX2 0x11
+#define SQ_S_STORE_DWORDX4 0x12
+#define SQ_S_BUFFER_STORE_DWORD 0x18
+#define SQ_S_BUFFER_STORE_DWORDX2 0x19
+#define SQ_S_BUFFER_STORE_DWORDX4 0x1a
+#define SQ_S_DCACHE_INV 0x20
+#define SQ_S_DCACHE_WB 0x21
+#define SQ_S_DCACHE_INV_VOL 0x22
+#define SQ_S_DCACHE_WB_VOL 0x23
+#define SQ_S_MEMTIME 0x24
+#define SQ_S_MEMREALTIME 0x25
+#define SQ_S_ATC_PROBE 0x26
+#define SQ_S_ATC_PROBE_BUFFER 0x27
+#define SQ_S_BUFFER_ATOMIC_SWAP 0x40
+#define SQ_S_BUFFER_ATOMIC_CMPSWAP 0x41
+#define SQ_S_BUFFER_ATOMIC_ADD 0x42
+#define SQ_S_BUFFER_ATOMIC_SUB 0x43
+#define SQ_S_BUFFER_ATOMIC_SMIN 0x44
+#define SQ_S_BUFFER_ATOMIC_UMIN 0x45
+#define SQ_S_BUFFER_ATOMIC_SMAX 0x46
+#define SQ_S_BUFFER_ATOMIC_UMAX 0x47
+#define SQ_S_BUFFER_ATOMIC_AND 0x48
+#define SQ_S_BUFFER_ATOMIC_OR 0x49
+#define SQ_S_BUFFER_ATOMIC_XOR 0x4a
+#define SQ_S_BUFFER_ATOMIC_INC 0x4b
+#define SQ_S_BUFFER_ATOMIC_DEC 0x4c
+#define SQ_S_BUFFER_ATOMIC_SWAP_X2 0x60
+#define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2 0x61
+#define SQ_S_BUFFER_ATOMIC_ADD_X2 0x62
+#define SQ_S_BUFFER_ATOMIC_SUB_X2 0x63
+#define SQ_S_BUFFER_ATOMIC_SMIN_X2 0x64
+#define SQ_S_BUFFER_ATOMIC_UMIN_X2 0x65
+#define SQ_S_BUFFER_ATOMIC_SMAX_X2 0x66
+#define SQ_S_BUFFER_ATOMIC_UMAX_X2 0x67
+#define SQ_S_BUFFER_ATOMIC_AND_X2 0x68
+#define SQ_S_BUFFER_ATOMIC_OR_X2 0x69
+#define SQ_S_BUFFER_ATOMIC_XOR_X2 0x6a
+#define SQ_S_BUFFER_ATOMIC_INC_X2 0x6b
+#define SQ_S_BUFFER_ATOMIC_DEC_X2 0x6c
+#define SQ_F 0x0
+#define SQ_LT 0x1
+#define SQ_EQ 0x2
+#define SQ_LE 0x3
+#define SQ_GT 0x4
+#define SQ_LG 0x5
+#define SQ_GE 0x6
+#define SQ_O 0x7
+#define SQ_U 0x8
+#define SQ_NGE 0x9
+#define SQ_NLG 0xa
+#define SQ_NGT 0xb
+#define SQ_NLE 0xc
+#define SQ_NEQ 0xd
+#define SQ_NLT 0xe
+#define SQ_TRU 0xf
+#define SQ_V_CMP_CLASS_F32 0x10
+#define SQ_V_CMPX_CLASS_F32 0x11
+#define SQ_V_CMP_CLASS_F64 0x12
+#define SQ_V_CMPX_CLASS_F64 0x13
+#define SQ_V_CMP_CLASS_F16 0x14
+#define SQ_V_CMPX_CLASS_F16 0x15
+#define SQ_V_CMP_F_F16 0x20
+#define SQ_V_CMP_LT_F16 0x21
+#define SQ_V_CMP_EQ_F16 0x22
+#define SQ_V_CMP_LE_F16 0x23
+#define SQ_V_CMP_GT_F16 0x24
+#define SQ_V_CMP_LG_F16 0x25
+#define SQ_V_CMP_GE_F16 0x26
+#define SQ_V_CMP_O_F16 0x27
+#define SQ_V_CMP_U_F16 0x28
+#define SQ_V_CMP_NGE_F16 0x29
+#define SQ_V_CMP_NLG_F16 0x2a
+#define SQ_V_CMP_NGT_F16 0x2b
+#define SQ_V_CMP_NLE_F16 0x2c
+#define SQ_V_CMP_NEQ_F16 0x2d
+#define SQ_V_CMP_NLT_F16 0x2e
+#define SQ_V_CMP_TRU_F16 0x2f
+#define SQ_V_CMPX_F_F16 0x30
+#define SQ_V_CMPX_LT_F16 0x31
+#define SQ_V_CMPX_EQ_F16 0x32
+#define SQ_V_CMPX_LE_F16 0x33
+#define SQ_V_CMPX_GT_F16 0x34
+#define SQ_V_CMPX_LG_F16 0x35
+#define SQ_V_CMPX_GE_F16 0x36
+#define SQ_V_CMPX_O_F16 0x37
+#define SQ_V_CMPX_U_F16 0x38
+#define SQ_V_CMPX_NGE_F16 0x39
+#define SQ_V_CMPX_NLG_F16 0x3a
+#define SQ_V_CMPX_NGT_F16 0x3b
+#define SQ_V_CMPX_NLE_F16 0x3c
+#define SQ_V_CMPX_NEQ_F16 0x3d
+#define SQ_V_CMPX_NLT_F16 0x3e
+#define SQ_V_CMPX_TRU_F16 0x3f
+#define SQ_V_CMP_F_F32 0x40
+#define SQ_V_CMP_LT_F32 0x41
+#define SQ_V_CMP_EQ_F32 0x42
+#define SQ_V_CMP_LE_F32 0x43
+#define SQ_V_CMP_GT_F32 0x44
+#define SQ_V_CMP_LG_F32 0x45
+#define SQ_V_CMP_GE_F32 0x46
+#define SQ_V_CMP_O_F32 0x47
+#define SQ_V_CMP_U_F32 0x48
+#define SQ_V_CMP_NGE_F32 0x49
+#define SQ_V_CMP_NLG_F32 0x4a
+#define SQ_V_CMP_NGT_F32 0x4b
+#define SQ_V_CMP_NLE_F32 0x4c
+#define SQ_V_CMP_NEQ_F32 0x4d
+#define SQ_V_CMP_NLT_F32 0x4e
+#define SQ_V_CMP_TRU_F32 0x4f
+#define SQ_V_CMPX_F_F32 0x50
+#define SQ_V_CMPX_LT_F32 0x51
+#define SQ_V_CMPX_EQ_F32 0x52
+#define SQ_V_CMPX_LE_F32 0x53
+#define SQ_V_CMPX_GT_F32 0x54
+#define SQ_V_CMPX_LG_F32 0x55
+#define SQ_V_CMPX_GE_F32 0x56
+#define SQ_V_CMPX_O_F32 0x57
+#define SQ_V_CMPX_U_F32 0x58
+#define SQ_V_CMPX_NGE_F32 0x59
+#define SQ_V_CMPX_NLG_F32 0x5a
+#define SQ_V_CMPX_NGT_F32 0x5b
+#define SQ_V_CMPX_NLE_F32 0x5c
+#define SQ_V_CMPX_NEQ_F32 0x5d
+#define SQ_V_CMPX_NLT_F32 0x5e
+#define SQ_V_CMPX_TRU_F32 0x5f
+#define SQ_V_CMP_F_F64 0x60
+#define SQ_V_CMP_LT_F64 0x61
+#define SQ_V_CMP_EQ_F64 0x62
+#define SQ_V_CMP_LE_F64 0x63
+#define SQ_V_CMP_GT_F64 0x64
+#define SQ_V_CMP_LG_F64 0x65
+#define SQ_V_CMP_GE_F64 0x66
+#define SQ_V_CMP_O_F64 0x67
+#define SQ_V_CMP_U_F64 0x68
+#define SQ_V_CMP_NGE_F64 0x69
+#define SQ_V_CMP_NLG_F64 0x6a
+#define SQ_V_CMP_NGT_F64 0x6b
+#define SQ_V_CMP_NLE_F64 0x6c
+#define SQ_V_CMP_NEQ_F64 0x6d
+#define SQ_V_CMP_NLT_F64 0x6e
+#define SQ_V_CMP_TRU_F64 0x6f
+#define SQ_V_CMPX_F_F64 0x70
+#define SQ_V_CMPX_LT_F64 0x71
+#define SQ_V_CMPX_EQ_F64 0x72
+#define SQ_V_CMPX_LE_F64 0x73
+#define SQ_V_CMPX_GT_F64 0x74
+#define SQ_V_CMPX_LG_F64 0x75
+#define SQ_V_CMPX_GE_F64 0x76
+#define SQ_V_CMPX_O_F64 0x77
+#define SQ_V_CMPX_U_F64 0x78
+#define SQ_V_CMPX_NGE_F64 0x79
+#define SQ_V_CMPX_NLG_F64 0x7a
+#define SQ_V_CMPX_NGT_F64 0x7b
+#define SQ_V_CMPX_NLE_F64 0x7c
+#define SQ_V_CMPX_NEQ_F64 0x7d
+#define SQ_V_CMPX_NLT_F64 0x7e
+#define SQ_V_CMPX_TRU_F64 0x7f
+#define SQ_V_CMP_F_I16 0xa0
+#define SQ_V_CMP_LT_I16 0xa1
+#define SQ_V_CMP_EQ_I16 0xa2
+#define SQ_V_CMP_LE_I16 0xa3
+#define SQ_V_CMP_GT_I16 0xa4
+#define SQ_V_CMP_NE_I16 0xa5
+#define SQ_V_CMP_GE_I16 0xa6
+#define SQ_V_CMP_T_I16 0xa7
+#define SQ_V_CMP_F_U16 0xa8
+#define SQ_V_CMP_LT_U16 0xa9
+#define SQ_V_CMP_EQ_U16 0xaa
+#define SQ_V_CMP_LE_U16 0xab
+#define SQ_V_CMP_GT_U16 0xac
+#define SQ_V_CMP_NE_U16 0xad
+#define SQ_V_CMP_GE_U16 0xae
+#define SQ_V_CMP_T_U16 0xaf
+#define SQ_V_CMPX_F_I16 0xb0
+#define SQ_V_CMPX_LT_I16 0xb1
+#define SQ_V_CMPX_EQ_I16 0xb2
+#define SQ_V_CMPX_LE_I16 0xb3
+#define SQ_V_CMPX_GT_I16 0xb4
+#define SQ_V_CMPX_NE_I16 0xb5
+#define SQ_V_CMPX_GE_I16 0xb6
+#define SQ_V_CMPX_T_I16 0xb7
+#define SQ_V_CMPX_F_U16 0xb8
+#define SQ_V_CMPX_LT_U16 0xb9
+#define SQ_V_CMPX_EQ_U16 0xba
+#define SQ_V_CMPX_LE_U16 0xbb
+#define SQ_V_CMPX_GT_U16 0xbc
+#define SQ_V_CMPX_NE_U16 0xbd
+#define SQ_V_CMPX_GE_U16 0xbe
+#define SQ_V_CMPX_T_U16 0xbf
+#define SQ_V_CMP_F_I32 0xc0
+#define SQ_V_CMP_LT_I32 0xc1
+#define SQ_V_CMP_EQ_I32 0xc2
+#define SQ_V_CMP_LE_I32 0xc3
+#define SQ_V_CMP_GT_I32 0xc4
+#define SQ_V_CMP_NE_I32 0xc5
+#define SQ_V_CMP_GE_I32 0xc6
+#define SQ_V_CMP_T_I32 0xc7
+#define SQ_V_CMP_F_U32 0xc8
+#define SQ_V_CMP_LT_U32 0xc9
+#define SQ_V_CMP_EQ_U32 0xca
+#define SQ_V_CMP_LE_U32 0xcb
+#define SQ_V_CMP_GT_U32 0xcc
+#define SQ_V_CMP_NE_U32 0xcd
+#define SQ_V_CMP_GE_U32 0xce
+#define SQ_V_CMP_T_U32 0xcf
+#define SQ_V_CMPX_F_I32 0xd0
+#define SQ_V_CMPX_LT_I32 0xd1
+#define SQ_V_CMPX_EQ_I32 0xd2
+#define SQ_V_CMPX_LE_I32 0xd3
+#define SQ_V_CMPX_GT_I32 0xd4
+#define SQ_V_CMPX_NE_I32 0xd5
+#define SQ_V_CMPX_GE_I32 0xd6
+#define SQ_V_CMPX_T_I32 0xd7
+#define SQ_V_CMPX_F_U32 0xd8
+#define SQ_V_CMPX_LT_U32 0xd9
+#define SQ_V_CMPX_EQ_U32 0xda
+#define SQ_V_CMPX_LE_U32 0xdb
+#define SQ_V_CMPX_GT_U32 0xdc
+#define SQ_V_CMPX_NE_U32 0xdd
+#define SQ_V_CMPX_GE_U32 0xde
+#define SQ_V_CMPX_T_U32 0xdf
+#define SQ_V_CMP_F_I64 0xe0
+#define SQ_V_CMP_LT_I64 0xe1
+#define SQ_V_CMP_EQ_I64 0xe2
+#define SQ_V_CMP_LE_I64 0xe3
+#define SQ_V_CMP_GT_I64 0xe4
+#define SQ_V_CMP_NE_I64 0xe5
+#define SQ_V_CMP_GE_I64 0xe6
+#define SQ_V_CMP_T_I64 0xe7
+#define SQ_V_CMP_F_U64 0xe8
+#define SQ_V_CMP_LT_U64 0xe9
+#define SQ_V_CMP_EQ_U64 0xea
+#define SQ_V_CMP_LE_U64 0xeb
+#define SQ_V_CMP_GT_U64 0xec
+#define SQ_V_CMP_NE_U64 0xed
+#define SQ_V_CMP_GE_U64 0xee
+#define SQ_V_CMP_T_U64 0xef
+#define SQ_V_CMPX_F_I64 0xf0
+#define SQ_V_CMPX_LT_I64 0xf1
+#define SQ_V_CMPX_EQ_I64 0xf2
+#define SQ_V_CMPX_LE_I64 0xf3
+#define SQ_V_CMPX_GT_I64 0xf4
+#define SQ_V_CMPX_NE_I64 0xf5
+#define SQ_V_CMPX_GE_I64 0xf6
+#define SQ_V_CMPX_T_I64 0xf7
+#define SQ_V_CMPX_F_U64 0xf8
+#define SQ_V_CMPX_LT_U64 0xf9
+#define SQ_V_CMPX_EQ_U64 0xfa
+#define SQ_V_CMPX_LE_U64 0xfb
+#define SQ_V_CMPX_GT_U64 0xfc
+#define SQ_V_CMPX_NE_U64 0xfd
+#define SQ_V_CMPX_GE_U64 0xfe
+#define SQ_V_CMPX_T_U64 0xff
+#define SQ_L1 0x1
+#define SQ_L2 0x2
+#define SQ_L3 0x3
+#define SQ_L4 0x4
+#define SQ_L5 0x5
+#define SQ_L6 0x6
+#define SQ_L7 0x7
+#define SQ_L8 0x8
+#define SQ_L9 0x9
+#define SQ_L10 0xa
+#define SQ_L11 0xb
+#define SQ_L12 0xc
+#define SQ_L13 0xd
+#define SQ_L14 0xe
+#define SQ_L15 0xf
+#define SQ_SGPR0 0x0
+#define SQ_SDWA_UNUSED_PAD 0x0
+#define SQ_SDWA_UNUSED_SEXT 0x1
+#define SQ_SDWA_UNUSED_PRESERVE 0x2
+#define SQ_F 0x0
+#define SQ_LT 0x1
+#define SQ_EQ 0x2
+#define SQ_LE 0x3
+#define SQ_GT 0x4
+#define SQ_NE 0x5
+#define SQ_GE 0x6
+#define SQ_T 0x7
+#define SQ_SRC_64_INT 0xc0
+#define SQ_SRC_M_1_INT 0xc1
+#define SQ_SRC_M_2_INT 0xc2
+#define SQ_SRC_M_3_INT 0xc3
+#define SQ_SRC_M_4_INT 0xc4
+#define SQ_SRC_M_5_INT 0xc5
+#define SQ_SRC_M_6_INT 0xc6
+#define SQ_SRC_M_7_INT 0xc7
+#define SQ_SRC_M_8_INT 0xc8
+#define SQ_SRC_M_9_INT 0xc9
+#define SQ_SRC_M_10_INT 0xca
+#define SQ_SRC_M_11_INT 0xcb
+#define SQ_SRC_M_12_INT 0xcc
+#define SQ_SRC_M_13_INT 0xcd
+#define SQ_SRC_M_14_INT 0xce
+#define SQ_SRC_M_15_INT 0xcf
+#define SQ_SRC_M_16_INT 0xd0
+#define SQ_SRC_0_5 0xf0
+#define SQ_SRC_M_0_5 0xf1
+#define SQ_SRC_1 0xf2
+#define SQ_SRC_M_1 0xf3
+#define SQ_SRC_2 0xf4
+#define SQ_SRC_M_2 0xf5
+#define SQ_SRC_4 0xf6
+#define SQ_SRC_M_4 0xf7
+#define SQ_SRC_INV_2PI 0xf8
+#define SQ_SRC_0 0x80
+#define SQ_SRC_1_INT 0x81
+#define SQ_SRC_2_INT 0x82
+#define SQ_SRC_3_INT 0x83
+#define SQ_SRC_4_INT 0x84
+#define SQ_SRC_5_INT 0x85
+#define SQ_SRC_6_INT 0x86
+#define SQ_SRC_7_INT 0x87
+#define SQ_SRC_8_INT 0x88
+#define SQ_SRC_9_INT 0x89
+#define SQ_SRC_10_INT 0x8a
+#define SQ_SRC_11_INT 0x8b
+#define SQ_SRC_12_INT 0x8c
+#define SQ_SRC_13_INT 0x8d
+#define SQ_SRC_14_INT 0x8e
+#define SQ_SRC_15_INT 0x8f
+#define SQ_SRC_16_INT 0x90
+#define SQ_SRC_17_INT 0x91
+#define SQ_SRC_18_INT 0x92
+#define SQ_SRC_19_INT 0x93
+#define SQ_SRC_20_INT 0x94
+#define SQ_SRC_21_INT 0x95
+#define SQ_SRC_22_INT 0x96
+#define SQ_SRC_23_INT 0x97
+#define SQ_SRC_24_INT 0x98
+#define SQ_SRC_25_INT 0x99
+#define SQ_SRC_26_INT 0x9a
+#define SQ_SRC_27_INT 0x9b
+#define SQ_SRC_28_INT 0x9c
+#define SQ_SRC_29_INT 0x9d
+#define SQ_SRC_30_INT 0x9e
+#define SQ_SRC_31_INT 0x9f
+#define SQ_SRC_32_INT 0xa0
+#define SQ_SRC_33_INT 0xa1
+#define SQ_SRC_34_INT 0xa2
+#define SQ_SRC_35_INT 0xa3
+#define SQ_SRC_36_INT 0xa4
+#define SQ_SRC_37_INT 0xa5
+#define SQ_SRC_38_INT 0xa6
+#define SQ_SRC_39_INT 0xa7
+#define SQ_SRC_40_INT 0xa8
+#define SQ_SRC_41_INT 0xa9
+#define SQ_SRC_42_INT 0xaa
+#define SQ_SRC_43_INT 0xab
+#define SQ_SRC_44_INT 0xac
+#define SQ_SRC_45_INT 0xad
+#define SQ_SRC_46_INT 0xae
+#define SQ_SRC_47_INT 0xaf
+#define SQ_SRC_48_INT 0xb0
+#define SQ_SRC_49_INT 0xb1
+#define SQ_SRC_50_INT 0xb2
+#define SQ_SRC_51_INT 0xb3
+#define SQ_SRC_52_INT 0xb4
+#define SQ_SRC_53_INT 0xb5
+#define SQ_SRC_54_INT 0xb6
+#define SQ_SRC_55_INT 0xb7
+#define SQ_SRC_56_INT 0xb8
+#define SQ_SRC_57_INT 0xb9
+#define SQ_SRC_58_INT 0xba
+#define SQ_SRC_59_INT 0xbb
+#define SQ_SRC_60_INT 0xbc
+#define SQ_SRC_61_INT 0xbd
+#define SQ_SRC_62_INT 0xbe
+#define SQ_SRC_63_INT 0xbf
+#define SQ_DS_ADD_U32 0x0
+#define SQ_DS_SUB_U32 0x1
+#define SQ_DS_RSUB_U32 0x2
+#define SQ_DS_INC_U32 0x3
+#define SQ_DS_DEC_U32 0x4
+#define SQ_DS_MIN_I32 0x5
+#define SQ_DS_MAX_I32 0x6
+#define SQ_DS_MIN_U32 0x7
+#define SQ_DS_MAX_U32 0x8
+#define SQ_DS_AND_B32 0x9
+#define SQ_DS_OR_B32 0xa
+#define SQ_DS_XOR_B32 0xb
+#define SQ_DS_MSKOR_B32 0xc
+#define SQ_DS_WRITE_B32 0xd
+#define SQ_DS_WRITE2_B32 0xe
+#define SQ_DS_WRITE2ST64_B32 0xf
+#define SQ_DS_CMPST_B32 0x10
+#define SQ_DS_CMPST_F32 0x11
+#define SQ_DS_MIN_F32 0x12
+#define SQ_DS_MAX_F32 0x13
+#define SQ_DS_NOP 0x14
+#define SQ_DS_ADD_F32 0x15
+#define SQ_DS_WRITE_B8 0x1e
+#define SQ_DS_WRITE_B16 0x1f
+#define SQ_DS_ADD_RTN_U32 0x20
+#define SQ_DS_SUB_RTN_U32 0x21
+#define SQ_DS_RSUB_RTN_U32 0x22
+#define SQ_DS_INC_RTN_U32 0x23
+#define SQ_DS_DEC_RTN_U32 0x24
+#define SQ_DS_MIN_RTN_I32 0x25
+#define SQ_DS_MAX_RTN_I32 0x26
+#define SQ_DS_MIN_RTN_U32 0x27
+#define SQ_DS_MAX_RTN_U32 0x28
+#define SQ_DS_AND_RTN_B32 0x29
+#define SQ_DS_OR_RTN_B32 0x2a
+#define SQ_DS_XOR_RTN_B32 0x2b
+#define SQ_DS_MSKOR_RTN_B32 0x2c
+#define SQ_DS_WRXCHG_RTN_B32 0x2d
+#define SQ_DS_WRXCHG2_RTN_B32 0x2e
+#define SQ_DS_WRXCHG2ST64_RTN_B32 0x2f
+#define SQ_DS_CMPST_RTN_B32 0x30
+#define SQ_DS_CMPST_RTN_F32 0x31
+#define SQ_DS_MIN_RTN_F32 0x32
+#define SQ_DS_MAX_RTN_F32 0x33
+#define SQ_DS_WRAP_RTN_B32 0x34
+#define SQ_DS_ADD_RTN_F32 0x35
+#define SQ_DS_READ_B32 0x36
+#define SQ_DS_READ2_B32 0x37
+#define SQ_DS_READ2ST64_B32 0x38
+#define SQ_DS_READ_I8 0x39
+#define SQ_DS_READ_U8 0x3a
+#define SQ_DS_READ_I16 0x3b
+#define SQ_DS_READ_U16 0x3c
+#define SQ_DS_SWIZZLE_B32 0x3d
+#define SQ_DS_PERMUTE_B32 0x3e
+#define SQ_DS_BPERMUTE_B32 0x3f
+#define SQ_DS_ADD_U64 0x40
+#define SQ_DS_SUB_U64 0x41
+#define SQ_DS_RSUB_U64 0x42
+#define SQ_DS_INC_U64 0x43
+#define SQ_DS_DEC_U64 0x44
+#define SQ_DS_MIN_I64 0x45
+#define SQ_DS_MAX_I64 0x46
+#define SQ_DS_MIN_U64 0x47
+#define SQ_DS_MAX_U64 0x48
+#define SQ_DS_AND_B64 0x49
+#define SQ_DS_OR_B64 0x4a
+#define SQ_DS_XOR_B64 0x4b
+#define SQ_DS_MSKOR_B64 0x4c
+#define SQ_DS_WRITE_B64 0x4d
+#define SQ_DS_WRITE2_B64 0x4e
+#define SQ_DS_WRITE2ST64_B64 0x4f
+#define SQ_DS_CMPST_B64 0x50
+#define SQ_DS_CMPST_F64 0x51
+#define SQ_DS_MIN_F64 0x52
+#define SQ_DS_MAX_F64 0x53
+#define SQ_DS_ADD_RTN_U64 0x60
+#define SQ_DS_SUB_RTN_U64 0x61
+#define SQ_DS_RSUB_RTN_U64 0x62
+#define SQ_DS_INC_RTN_U64 0x63
+#define SQ_DS_DEC_RTN_U64 0x64
+#define SQ_DS_MIN_RTN_I64 0x65
+#define SQ_DS_MAX_RTN_I64 0x66
+#define SQ_DS_MIN_RTN_U64 0x67
+#define SQ_DS_MAX_RTN_U64 0x68
+#define SQ_DS_AND_RTN_B64 0x69
+#define SQ_DS_OR_RTN_B64 0x6a
+#define SQ_DS_XOR_RTN_B64 0x6b
+#define SQ_DS_MSKOR_RTN_B64 0x6c
+#define SQ_DS_WRXCHG_RTN_B64 0x6d
+#define SQ_DS_WRXCHG2_RTN_B64 0x6e
+#define SQ_DS_WRXCHG2ST64_RTN_B64 0x6f
+#define SQ_DS_CMPST_RTN_B64 0x70
+#define SQ_DS_CMPST_RTN_F64 0x71
+#define SQ_DS_MIN_RTN_F64 0x72
+#define SQ_DS_MAX_RTN_F64 0x73
+#define SQ_DS_READ_B64 0x76
+#define SQ_DS_READ2_B64 0x77
+#define SQ_DS_READ2ST64_B64 0x78
+#define SQ_DS_CONDXCHG32_RTN_B64 0x7e
+#define SQ_DS_ADD_SRC2_U32 0x80
+#define SQ_DS_SUB_SRC2_U32 0x81
+#define SQ_DS_RSUB_SRC2_U32 0x82
+#define SQ_DS_INC_SRC2_U32 0x83
+#define SQ_DS_DEC_SRC2_U32 0x84
+#define SQ_DS_MIN_SRC2_I32 0x85
+#define SQ_DS_MAX_SRC2_I32 0x86
+#define SQ_DS_MIN_SRC2_U32 0x87
+#define SQ_DS_MAX_SRC2_U32 0x88
+#define SQ_DS_AND_SRC2_B32 0x89
+#define SQ_DS_OR_SRC2_B32 0x8a
+#define SQ_DS_XOR_SRC2_B32 0x8b
+#define SQ_DS_WRITE_SRC2_B32 0x8d
+#define SQ_DS_MIN_SRC2_F32 0x92
+#define SQ_DS_MAX_SRC2_F32 0x93
+#define SQ_DS_ADD_SRC2_F32 0x95
+#define SQ_DS_GWS_SEMA_RELEASE_ALL 0x98
+#define SQ_DS_GWS_INIT 0x99
+#define SQ_DS_GWS_SEMA_V 0x9a
+#define SQ_DS_GWS_SEMA_BR 0x9b
+#define SQ_DS_GWS_SEMA_P 0x9c
+#define SQ_DS_GWS_BARRIER 0x9d
+#define SQ_DS_CONSUME 0xbd
+#define SQ_DS_APPEND 0xbe
+#define SQ_DS_ORDERED_COUNT 0xbf
+#define SQ_DS_ADD_SRC2_U64 0xc0
+#define SQ_DS_SUB_SRC2_U64 0xc1
+#define SQ_DS_RSUB_SRC2_U64 0xc2
+#define SQ_DS_INC_SRC2_U64 0xc3
+#define SQ_DS_DEC_SRC2_U64 0xc4
+#define SQ_DS_MIN_SRC2_I64 0xc5
+#define SQ_DS_MAX_SRC2_I64 0xc6
+#define SQ_DS_MIN_SRC2_U64 0xc7
+#define SQ_DS_MAX_SRC2_U64 0xc8
+#define SQ_DS_AND_SRC2_B64 0xc9
+#define SQ_DS_OR_SRC2_B64 0xca
+#define SQ_DS_XOR_SRC2_B64 0xcb
+#define SQ_DS_WRITE_SRC2_B64 0xcd
+#define SQ_DS_MIN_SRC2_F64 0xd2
+#define SQ_DS_MAX_SRC2_F64 0xd3
+#define SQ_DS_WRITE_B96 0xde
+#define SQ_DS_WRITE_B128 0xdf
+#define SQ_DS_CONDXCHG32_RTN_B128 0xfd
+#define SQ_DS_READ_B96 0xfe
+#define SQ_DS_READ_B128 0xff
+#define SQ_BUFFER_LOAD_FORMAT_X 0x0
+#define SQ_BUFFER_LOAD_FORMAT_XY 0x1
+#define SQ_BUFFER_LOAD_FORMAT_XYZ 0x2
+#define SQ_BUFFER_LOAD_FORMAT_XYZW 0x3
+#define SQ_BUFFER_STORE_FORMAT_X 0x4
+#define SQ_BUFFER_STORE_FORMAT_XY 0x5
+#define SQ_BUFFER_STORE_FORMAT_XYZ 0x6
+#define SQ_BUFFER_STORE_FORMAT_XYZW 0x7
+#define SQ_BUFFER_LOAD_FORMAT_D16_X 0x8
+#define SQ_BUFFER_LOAD_FORMAT_D16_XY 0x9
+#define SQ_BUFFER_LOAD_FORMAT_D16_XYZ 0xa
+#define SQ_BUFFER_LOAD_FORMAT_D16_XYZW 0xb
+#define SQ_BUFFER_STORE_FORMAT_D16_X 0xc
+#define SQ_BUFFER_STORE_FORMAT_D16_XY 0xd
+#define SQ_BUFFER_STORE_FORMAT_D16_XYZ 0xe
+#define SQ_BUFFER_STORE_FORMAT_D16_XYZW 0xf
+#define SQ_BUFFER_LOAD_UBYTE 0x10
+#define SQ_BUFFER_LOAD_SBYTE 0x11
+#define SQ_BUFFER_LOAD_USHORT 0x12
+#define SQ_BUFFER_LOAD_SSHORT 0x13
+#define SQ_BUFFER_LOAD_DWORD 0x14
+#define SQ_BUFFER_LOAD_DWORDX2 0x15
+#define SQ_BUFFER_LOAD_DWORDX3 0x16
+#define SQ_BUFFER_LOAD_DWORDX4 0x17
+#define SQ_BUFFER_STORE_BYTE 0x18
+#define SQ_BUFFER_STORE_SHORT 0x1a
+#define SQ_BUFFER_STORE_DWORD 0x1c
+#define SQ_BUFFER_STORE_DWORDX2 0x1d
+#define SQ_BUFFER_STORE_DWORDX3 0x1e
+#define SQ_BUFFER_STORE_DWORDX4 0x1f
+#define SQ_BUFFER_STORE_LDS_DWORD 0x3d
+#define SQ_BUFFER_WBINVL1 0x3e
+#define SQ_BUFFER_WBINVL1_VOL 0x3f
+#define SQ_BUFFER_ATOMIC_SWAP 0x40
+#define SQ_BUFFER_ATOMIC_CMPSWAP 0x41
+#define SQ_BUFFER_ATOMIC_ADD 0x42
+#define SQ_BUFFER_ATOMIC_SUB 0x43
+#define SQ_BUFFER_ATOMIC_SMIN 0x44
+#define SQ_BUFFER_ATOMIC_UMIN 0x45
+#define SQ_BUFFER_ATOMIC_SMAX 0x46
+#define SQ_BUFFER_ATOMIC_UMAX 0x47
+#define SQ_BUFFER_ATOMIC_AND 0x48
+#define SQ_BUFFER_ATOMIC_OR 0x49
+#define SQ_BUFFER_ATOMIC_XOR 0x4a
+#define SQ_BUFFER_ATOMIC_INC 0x4b
+#define SQ_BUFFER_ATOMIC_DEC 0x4c
+#define SQ_BUFFER_ATOMIC_SWAP_X2 0x60
+#define SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x61
+#define SQ_BUFFER_ATOMIC_ADD_X2 0x62
+#define SQ_BUFFER_ATOMIC_SUB_X2 0x63
+#define SQ_BUFFER_ATOMIC_SMIN_X2 0x64
+#define SQ_BUFFER_ATOMIC_UMIN_X2 0x65
+#define SQ_BUFFER_ATOMIC_SMAX_X2 0x66
+#define SQ_BUFFER_ATOMIC_UMAX_X2 0x67
+#define SQ_BUFFER_ATOMIC_AND_X2 0x68
+#define SQ_BUFFER_ATOMIC_OR_X2 0x69
+#define SQ_BUFFER_ATOMIC_XOR_X2 0x6a
+#define SQ_BUFFER_ATOMIC_INC_X2 0x6b
+#define SQ_BUFFER_ATOMIC_DEC_X2 0x6c
+#define SQ_EXEC_LO 0x7e
+#define SQ_EXEC_HI 0x7f
+#define SQ_SRC_SCC 0xfd
+#define SQ_OMOD_OFF 0x0
+#define SQ_OMOD_M2 0x1
+#define SQ_OMOD_M4 0x2
+#define SQ_OMOD_D2 0x3
+#define SQ_DPP_QUAD_PERM 0x0
+#define SQ_DPP_ROW_SL1 0x101
+#define SQ_DPP_ROW_SL2 0x102
+#define SQ_DPP_ROW_SL3 0x103
+#define SQ_DPP_ROW_SL4 0x104
+#define SQ_DPP_ROW_SL5 0x105
+#define SQ_DPP_ROW_SL6 0x106
+#define SQ_DPP_ROW_SL7 0x107
+#define SQ_DPP_ROW_SL8 0x108
+#define SQ_DPP_ROW_SL9 0x109
+#define SQ_DPP_ROW_SL10 0x10a
+#define SQ_DPP_ROW_SL11 0x10b
+#define SQ_DPP_ROW_SL12 0x10c
+#define SQ_DPP_ROW_SL13 0x10d
+#define SQ_DPP_ROW_SL14 0x10e
+#define SQ_DPP_ROW_SL15 0x10f
+#define SQ_DPP_ROW_SR1 0x111
+#define SQ_DPP_ROW_SR2 0x112
+#define SQ_DPP_ROW_SR3 0x113
+#define SQ_DPP_ROW_SR4 0x114
+#define SQ_DPP_ROW_SR5 0x115
+#define SQ_DPP_ROW_SR6 0x116
+#define SQ_DPP_ROW_SR7 0x117
+#define SQ_DPP_ROW_SR8 0x118
+#define SQ_DPP_ROW_SR9 0x119
+#define SQ_DPP_ROW_SR10 0x11a
+#define SQ_DPP_ROW_SR11 0x11b
+#define SQ_DPP_ROW_SR12 0x11c
+#define SQ_DPP_ROW_SR13 0x11d
+#define SQ_DPP_ROW_SR14 0x11e
+#define SQ_DPP_ROW_SR15 0x11f
+#define SQ_DPP_ROW_RR1 0x121
+#define SQ_DPP_ROW_RR2 0x122
+#define SQ_DPP_ROW_RR3 0x123
+#define SQ_DPP_ROW_RR4 0x124
+#define SQ_DPP_ROW_RR5 0x125
+#define SQ_DPP_ROW_RR6 0x126
+#define SQ_DPP_ROW_RR7 0x127
+#define SQ_DPP_ROW_RR8 0x128
+#define SQ_DPP_ROW_RR9 0x129
+#define SQ_DPP_ROW_RR10 0x12a
+#define SQ_DPP_ROW_RR11 0x12b
+#define SQ_DPP_ROW_RR12 0x12c
+#define SQ_DPP_ROW_RR13 0x12d
+#define SQ_DPP_ROW_RR14 0x12e
+#define SQ_DPP_ROW_RR15 0x12f
+#define SQ_DPP_WF_SL1 0x130
+#define SQ_DPP_WF_RL1 0x134
+#define SQ_DPP_WF_SR1 0x138
+#define SQ_DPP_WF_RR1 0x13c
+#define SQ_DPP_ROW_MIRROR 0x140
+#define SQ_DPP_ROW_HALF_MIRROR 0x141
+#define SQ_DPP_ROW_BCAST15 0x142
+#define SQ_DPP_ROW_BCAST31 0x143
+#define SQ_EXP_GDS0 0x18
+#define SQ_GS_OP_NOP 0x0
+#define SQ_GS_OP_CUT 0x1
+#define SQ_GS_OP_EMIT 0x2
+#define SQ_GS_OP_EMIT_CUT 0x3
+#define SQ_IMAGE_LOAD 0x0
+#define SQ_IMAGE_LOAD_MIP 0x1
+#define SQ_IMAGE_LOAD_PCK 0x2
+#define SQ_IMAGE_LOAD_PCK_SGN 0x3
+#define SQ_IMAGE_LOAD_MIP_PCK 0x4
+#define SQ_IMAGE_LOAD_MIP_PCK_SGN 0x5
+#define SQ_IMAGE_STORE 0x8
+#define SQ_IMAGE_STORE_MIP 0x9
+#define SQ_IMAGE_STORE_PCK 0xa
+#define SQ_IMAGE_STORE_MIP_PCK 0xb
+#define SQ_IMAGE_GET_RESINFO 0xe
+#define SQ_IMAGE_ATOMIC_SWAP 0x10
+#define SQ_IMAGE_ATOMIC_CMPSWAP 0x11
+#define SQ_IMAGE_ATOMIC_ADD 0x12
+#define SQ_IMAGE_ATOMIC_SUB 0x13
+#define SQ_IMAGE_ATOMIC_SMIN 0x14
+#define SQ_IMAGE_ATOMIC_UMIN 0x15
+#define SQ_IMAGE_ATOMIC_SMAX 0x16
+#define SQ_IMAGE_ATOMIC_UMAX 0x17
+#define SQ_IMAGE_ATOMIC_AND 0x18
+#define SQ_IMAGE_ATOMIC_OR 0x19
+#define SQ_IMAGE_ATOMIC_XOR 0x1a
+#define SQ_IMAGE_ATOMIC_INC 0x1b
+#define SQ_IMAGE_ATOMIC_DEC 0x1c
+#define SQ_IMAGE_SAMPLE 0x20
+#define SQ_IMAGE_SAMPLE_CL 0x21
+#define SQ_IMAGE_SAMPLE_D 0x22
+#define SQ_IMAGE_SAMPLE_D_CL 0x23
+#define SQ_IMAGE_SAMPLE_L 0x24
+#define SQ_IMAGE_SAMPLE_B 0x25
+#define SQ_IMAGE_SAMPLE_B_CL 0x26
+#define SQ_IMAGE_SAMPLE_LZ 0x27
+#define SQ_IMAGE_SAMPLE_C 0x28
+#define SQ_IMAGE_SAMPLE_C_CL 0x29
+#define SQ_IMAGE_SAMPLE_C_D 0x2a
+#define SQ_IMAGE_SAMPLE_C_D_CL 0x2b
+#define SQ_IMAGE_SAMPLE_C_L 0x2c
+#define SQ_IMAGE_SAMPLE_C_B 0x2d
+#define SQ_IMAGE_SAMPLE_C_B_CL 0x2e
+#define SQ_IMAGE_SAMPLE_C_LZ 0x2f
+#define SQ_IMAGE_SAMPLE_O 0x30
+#define SQ_IMAGE_SAMPLE_CL_O 0x31
+#define SQ_IMAGE_SAMPLE_D_O 0x32
+#define SQ_IMAGE_SAMPLE_D_CL_O 0x33
+#define SQ_IMAGE_SAMPLE_L_O 0x34
+#define SQ_IMAGE_SAMPLE_B_O 0x35
+#define SQ_IMAGE_SAMPLE_B_CL_O 0x36
+#define SQ_IMAGE_SAMPLE_LZ_O 0x37
+#define SQ_IMAGE_SAMPLE_C_O 0x38
+#define SQ_IMAGE_SAMPLE_C_CL_O 0x39
+#define SQ_IMAGE_SAMPLE_C_D_O 0x3a
+#define SQ_IMAGE_SAMPLE_C_D_CL_O 0x3b
+#define SQ_IMAGE_SAMPLE_C_L_O 0x3c
+#define SQ_IMAGE_SAMPLE_C_B_O 0x3d
+#define SQ_IMAGE_SAMPLE_C_B_CL_O 0x3e
+#define SQ_IMAGE_SAMPLE_C_LZ_O 0x3f
+#define SQ_IMAGE_GATHER4 0x40
+#define SQ_IMAGE_GATHER4_CL 0x41
+#define SQ_IMAGE_GATHER4_L 0x44
+#define SQ_IMAGE_GATHER4_B 0x45
+#define SQ_IMAGE_GATHER4_B_CL 0x46
+#define SQ_IMAGE_GATHER4_LZ 0x47
+#define SQ_IMAGE_GATHER4_C 0x48
+#define SQ_IMAGE_GATHER4_C_CL 0x49
+#define SQ_IMAGE_GATHER4_C_L 0x4c
+#define SQ_IMAGE_GATHER4_C_B 0x4d
+#define SQ_IMAGE_GATHER4_C_B_CL 0x4e
+#define SQ_IMAGE_GATHER4_C_LZ 0x4f
+#define SQ_IMAGE_GATHER4_O 0x50
+#define SQ_IMAGE_GATHER4_CL_O 0x51
+#define SQ_IMAGE_GATHER4_L_O 0x54
+#define SQ_IMAGE_GATHER4_B_O 0x55
+#define SQ_IMAGE_GATHER4_B_CL_O 0x56
+#define SQ_IMAGE_GATHER4_LZ_O 0x57
+#define SQ_IMAGE_GATHER4_C_O 0x58
+#define SQ_IMAGE_GATHER4_C_CL_O 0x59
+#define SQ_IMAGE_GATHER4_C_L_O 0x5c
+#define SQ_IMAGE_GATHER4_C_B_O 0x5d
+#define SQ_IMAGE_GATHER4_C_B_CL_O 0x5e
+#define SQ_IMAGE_GATHER4_C_LZ_O 0x5f
+#define SQ_IMAGE_GET_LOD 0x60
+#define SQ_IMAGE_SAMPLE_CD 0x68
+#define SQ_IMAGE_SAMPLE_CD_CL 0x69
+#define SQ_IMAGE_SAMPLE_C_CD 0x6a
+#define SQ_IMAGE_SAMPLE_C_CD_CL 0x6b
+#define SQ_IMAGE_SAMPLE_CD_O 0x6c
+#define SQ_IMAGE_SAMPLE_CD_CL_O 0x6d
+#define SQ_IMAGE_SAMPLE_C_CD_O 0x6e
+#define SQ_IMAGE_SAMPLE_C_CD_CL_O 0x6f
+#define SQ_IMAGE_RSRC256 0x7e
+#define SQ_IMAGE_SAMPLER 0x7f
+#define SQ_SRC_VCCZ 0xfb
+#define SQ_SRC_VGPR0 0x100
+#define SQ_SDWA_BYTE_0 0x0
+#define SQ_SDWA_BYTE_1 0x1
+#define SQ_SDWA_BYTE_2 0x2
+#define SQ_SDWA_BYTE_3 0x3
+#define SQ_SDWA_WORD_0 0x4
+#define SQ_SDWA_WORD_1 0x5
+#define SQ_SDWA_DWORD 0x6
+#define SQ_XNACK_MASK_LO 0x68
+#define SQ_XNACK_MASK_HI 0x69
+#define SQ_TBUFFER_LOAD_FORMAT_X 0x0
+#define SQ_TBUFFER_LOAD_FORMAT_XY 0x1
+#define SQ_TBUFFER_LOAD_FORMAT_XYZ 0x2
+#define SQ_TBUFFER_LOAD_FORMAT_XYZW 0x3
+#define SQ_TBUFFER_STORE_FORMAT_X 0x4
+#define SQ_TBUFFER_STORE_FORMAT_XY 0x5
+#define SQ_TBUFFER_STORE_FORMAT_XYZ 0x6
+#define SQ_TBUFFER_STORE_FORMAT_XYZW 0x7
+#define SQ_TBUFFER_LOAD_FORMAT_D16_X 0x8
+#define SQ_TBUFFER_LOAD_FORMAT_D16_XY 0x9
+#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ 0xa
+#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW 0xb
+#define SQ_TBUFFER_STORE_FORMAT_D16_X 0xc
+#define SQ_TBUFFER_STORE_FORMAT_D16_XY 0xd
+#define SQ_TBUFFER_STORE_FORMAT_D16_XYZ 0xe
+#define SQ_TBUFFER_STORE_FORMAT_D16_XYZW 0xf
+#define SQ_CHAN_X 0x0
+#define SQ_CHAN_Y 0x1
+#define SQ_CHAN_Z 0x2
+#define SQ_CHAN_W 0x3
+#define SQ_V_NOP 0x0
+#define SQ_V_MOV_B32 0x1
+#define SQ_V_READFIRSTLANE_B32 0x2
+#define SQ_V_CVT_I32_F64 0x3
+#define SQ_V_CVT_F64_I32 0x4
+#define SQ_V_CVT_F32_I32 0x5
+#define SQ_V_CVT_F32_U32 0x6
+#define SQ_V_CVT_U32_F32 0x7
+#define SQ_V_CVT_I32_F32 0x8
+#define SQ_V_MOV_FED_B32 0x9
+#define SQ_V_CVT_F16_F32 0xa
+#define SQ_V_CVT_F32_F16 0xb
+#define SQ_V_CVT_RPI_I32_F32 0xc
+#define SQ_V_CVT_FLR_I32_F32 0xd
+#define SQ_V_CVT_OFF_F32_I4 0xe
+#define SQ_V_CVT_F32_F64 0xf
+#define SQ_V_CVT_F64_F32 0x10
+#define SQ_V_CVT_F32_UBYTE0 0x11
+#define SQ_V_CVT_F32_UBYTE1 0x12
+#define SQ_V_CVT_F32_UBYTE2 0x13
+#define SQ_V_CVT_F32_UBYTE3 0x14
+#define SQ_V_CVT_U32_F64 0x15
+#define SQ_V_CVT_F64_U32 0x16
+#define SQ_V_TRUNC_F64 0x17
+#define SQ_V_CEIL_F64 0x18
+#define SQ_V_RNDNE_F64 0x19
+#define SQ_V_FLOOR_F64 0x1a
+#define SQ_V_FRACT_F32 0x1b
+#define SQ_V_TRUNC_F32 0x1c
+#define SQ_V_CEIL_F32 0x1d
+#define SQ_V_RNDNE_F32 0x1e
+#define SQ_V_FLOOR_F32 0x1f
+#define SQ_V_EXP_F32 0x20
+#define SQ_V_LOG_F32 0x21
+#define SQ_V_RCP_F32 0x22
+#define SQ_V_RCP_IFLAG_F32 0x23
+#define SQ_V_RSQ_F32 0x24
+#define SQ_V_RCP_F64 0x25
+#define SQ_V_RSQ_F64 0x26
+#define SQ_V_SQRT_F32 0x27
+#define SQ_V_SQRT_F64 0x28
+#define SQ_V_SIN_F32 0x29
+#define SQ_V_COS_F32 0x2a
+#define SQ_V_NOT_B32 0x2b
+#define SQ_V_BFREV_B32 0x2c
+#define SQ_V_FFBH_U32 0x2d
+#define SQ_V_FFBL_B32 0x2e
+#define SQ_V_FFBH_I32 0x2f
+#define SQ_V_FREXP_EXP_I32_F64 0x30
+#define SQ_V_FREXP_MANT_F64 0x31
+#define SQ_V_FRACT_F64 0x32
+#define SQ_V_FREXP_EXP_I32_F32 0x33
+#define SQ_V_FREXP_MANT_F32 0x34
+#define SQ_V_CLREXCP 0x35
+#define SQ_V_MOVRELD_B32 0x36
+#define SQ_V_MOVRELS_B32 0x37
+#define SQ_V_MOVRELSD_B32 0x38
+#define SQ_V_CVT_F16_U16 0x39
+#define SQ_V_CVT_F16_I16 0x3a
+#define SQ_V_CVT_U16_F16 0x3b
+#define SQ_V_CVT_I16_F16 0x3c
+#define SQ_V_RCP_F16 0x3d
+#define SQ_V_SQRT_F16 0x3e
+#define SQ_V_RSQ_F16 0x3f
+#define SQ_V_LOG_F16 0x40
+#define SQ_V_EXP_F16 0x41
+#define SQ_V_FREXP_MANT_F16 0x42
+#define SQ_V_FREXP_EXP_I16_F16 0x43
+#define SQ_V_FLOOR_F16 0x44
+#define SQ_V_CEIL_F16 0x45
+#define SQ_V_TRUNC_F16 0x46
+#define SQ_V_RNDNE_F16 0x47
+#define SQ_V_FRACT_F16 0x48
+#define SQ_V_SIN_F16 0x49
+#define SQ_V_COS_F16 0x4a
+#define SQ_V_EXP_LEGACY_F32 0x4b
+#define SQ_V_LOG_LEGACY_F32 0x4c
+#define SQ_SRC_SDWA 0xf9
+#define SQ_V_OPC_OFFSET 0x0
+#define SQ_V_OP2_OFFSET 0x100
+#define SQ_V_OP1_OFFSET 0x140
+#define SQ_V_INTRP_OFFSET 0x270
+#define SQ_V_INTERP_P1_F32 0x0
+#define SQ_V_INTERP_P2_F32 0x1
+#define SQ_V_INTERP_MOV_F32 0x2
+#define SQ_S_NOP 0x0
+#define SQ_S_ENDPGM 0x1
+#define SQ_S_BRANCH 0x2
+#define SQ_S_WAKEUP 0x3
+#define SQ_S_CBRANCH_SCC0 0x4
+#define SQ_S_CBRANCH_SCC1 0x5
+#define SQ_S_CBRANCH_VCCZ 0x6
+#define SQ_S_CBRANCH_VCCNZ 0x7
+#define SQ_S_CBRANCH_EXECZ 0x8
+#define SQ_S_CBRANCH_EXECNZ 0x9
+#define SQ_S_BARRIER 0xa
+#define SQ_S_SETKILL 0xb
+#define SQ_S_WAITCNT 0xc
+#define SQ_S_SETHALT 0xd
+#define SQ_S_SLEEP 0xe
+#define SQ_S_SETPRIO 0xf
+#define SQ_S_SENDMSG 0x10
+#define SQ_S_SENDMSGHALT 0x11
+#define SQ_S_TRAP 0x12
+#define SQ_S_ICACHE_INV 0x13
+#define SQ_S_INCPERFLEVEL 0x14
+#define SQ_S_DECPERFLEVEL 0x15
+#define SQ_S_TTRACEDATA 0x16
+#define SQ_S_CBRANCH_CDBGSYS 0x17
+#define SQ_S_CBRANCH_CDBGUSER 0x18
+#define SQ_S_CBRANCH_CDBGSYS_OR_USER 0x19
+#define SQ_S_CBRANCH_CDBGSYS_AND_USER 0x1a
+#define SQ_S_ENDPGM_SAVED 0x1b
+#define SQ_S_SET_GPR_IDX_OFF 0x1c
+#define SQ_S_SET_GPR_IDX_MODE 0x1d
+#define SQ_SRC_DPP 0xfa
+#define SQ_SRC_LITERAL 0xff
+#define SQ_VCC_LO 0x6a
+#define SQ_VCC_HI 0x6b
+#define SQ_PARAM_P10 0x0
+#define SQ_PARAM_P20 0x1
+#define SQ_PARAM_P0 0x2
+#define SQ_SRC_LDS_DIRECT 0xfe
+#define SQ_V_CNDMASK_B32 0x0
+#define SQ_V_ADD_F32 0x1
+#define SQ_V_SUB_F32 0x2
+#define SQ_V_SUBREV_F32 0x3
+#define SQ_V_MUL_LEGACY_F32 0x4
+#define SQ_V_MUL_F32 0x5
+#define SQ_V_MUL_I32_I24 0x6
+#define SQ_V_MUL_HI_I32_I24 0x7
+#define SQ_V_MUL_U32_U24 0x8
+#define SQ_V_MUL_HI_U32_U24 0x9
+#define SQ_V_MIN_F32 0xa
+#define SQ_V_MAX_F32 0xb
+#define SQ_V_MIN_I32 0xc
+#define SQ_V_MAX_I32 0xd
+#define SQ_V_MIN_U32 0xe
+#define SQ_V_MAX_U32 0xf
+#define SQ_V_LSHRREV_B32 0x10
+#define SQ_V_ASHRREV_I32 0x11
+#define SQ_V_LSHLREV_B32 0x12
+#define SQ_V_AND_B32 0x13
+#define SQ_V_OR_B32 0x14
+#define SQ_V_XOR_B32 0x15
+#define SQ_V_MAC_F32 0x16
+#define SQ_V_MADMK_F32 0x17
+#define SQ_V_MADAK_F32 0x18
+#define SQ_V_ADD_U32 0x19
+#define SQ_V_SUB_U32 0x1a
+#define SQ_V_SUBREV_U32 0x1b
+#define SQ_V_ADDC_U32 0x1c
+#define SQ_V_SUBB_U32 0x1d
+#define SQ_V_SUBBREV_U32 0x1e
+#define SQ_V_ADD_F16 0x1f
+#define SQ_V_SUB_F16 0x20
+#define SQ_V_SUBREV_F16 0x21
+#define SQ_V_MUL_F16 0x22
+#define SQ_V_MAC_F16 0x23
+#define SQ_V_MADMK_F16 0x24
+#define SQ_V_MADAK_F16 0x25
+#define SQ_V_ADD_U16 0x26
+#define SQ_V_SUB_U16 0x27
+#define SQ_V_SUBREV_U16 0x28
+#define SQ_V_MUL_LO_U16 0x29
+#define SQ_V_LSHLREV_B16 0x2a
+#define SQ_V_LSHRREV_B16 0x2b
+#define SQ_V_ASHRREV_I16 0x2c
+#define SQ_V_MAX_F16 0x2d
+#define SQ_V_MIN_F16 0x2e
+#define SQ_V_MAX_U16 0x2f
+#define SQ_V_MAX_I16 0x30
+#define SQ_V_MIN_U16 0x31
+#define SQ_V_MIN_I16 0x32
+#define SQ_V_LDEXP_F16 0x33
+#define SQ_FLAT_LOAD_UBYTE 0x10
+#define SQ_FLAT_LOAD_SBYTE 0x11
+#define SQ_FLAT_LOAD_USHORT 0x12
+#define SQ_FLAT_LOAD_SSHORT 0x13
+#define SQ_FLAT_LOAD_DWORD 0x14
+#define SQ_FLAT_LOAD_DWORDX2 0x15
+#define SQ_FLAT_LOAD_DWORDX3 0x16
+#define SQ_FLAT_LOAD_DWORDX4 0x17
+#define SQ_FLAT_STORE_BYTE 0x18
+#define SQ_FLAT_STORE_SHORT 0x1a
+#define SQ_FLAT_STORE_DWORD 0x1c
+#define SQ_FLAT_STORE_DWORDX2 0x1d
+#define SQ_FLAT_STORE_DWORDX3 0x1e
+#define SQ_FLAT_STORE_DWORDX4 0x1f
+#define SQ_FLAT_ATOMIC_SWAP 0x40
+#define SQ_FLAT_ATOMIC_CMPSWAP 0x41
+#define SQ_FLAT_ATOMIC_ADD 0x42
+#define SQ_FLAT_ATOMIC_SUB 0x43
+#define SQ_FLAT_ATOMIC_SMIN 0x44
+#define SQ_FLAT_ATOMIC_UMIN 0x45
+#define SQ_FLAT_ATOMIC_SMAX 0x46
+#define SQ_FLAT_ATOMIC_UMAX 0x47
+#define SQ_FLAT_ATOMIC_AND 0x48
+#define SQ_FLAT_ATOMIC_OR 0x49
+#define SQ_FLAT_ATOMIC_XOR 0x4a
+#define SQ_FLAT_ATOMIC_INC 0x4b
+#define SQ_FLAT_ATOMIC_DEC 0x4c
+#define SQ_FLAT_ATOMIC_SWAP_X2 0x60
+#define SQ_FLAT_ATOMIC_CMPSWAP_X2 0x61
+#define SQ_FLAT_ATOMIC_ADD_X2 0x62
+#define SQ_FLAT_ATOMIC_SUB_X2 0x63
+#define SQ_FLAT_ATOMIC_SMIN_X2 0x64
+#define SQ_FLAT_ATOMIC_UMIN_X2 0x65
+#define SQ_FLAT_ATOMIC_SMAX_X2 0x66
+#define SQ_FLAT_ATOMIC_UMAX_X2 0x67
+#define SQ_FLAT_ATOMIC_AND_X2 0x68
+#define SQ_FLAT_ATOMIC_OR_X2 0x69
+#define SQ_FLAT_ATOMIC_XOR_X2 0x6a
+#define SQ_FLAT_ATOMIC_INC_X2 0x6b
+#define SQ_FLAT_ATOMIC_DEC_X2 0x6c
+#define SQ_S_CMP_EQ_I32 0x0
+#define SQ_S_CMP_LG_I32 0x1
+#define SQ_S_CMP_GT_I32 0x2
+#define SQ_S_CMP_GE_I32 0x3
+#define SQ_S_CMP_LT_I32 0x4
+#define SQ_S_CMP_LE_I32 0x5
+#define SQ_S_CMP_EQ_U32 0x6
+#define SQ_S_CMP_LG_U32 0x7
+#define SQ_S_CMP_GT_U32 0x8
+#define SQ_S_CMP_GE_U32 0x9
+#define SQ_S_CMP_LT_U32 0xa
+#define SQ_S_CMP_LE_U32 0xb
+#define SQ_S_BITCMP0_B32 0xc
+#define SQ_S_BITCMP1_B32 0xd
+#define SQ_S_BITCMP0_B64 0xe
+#define SQ_S_BITCMP1_B64 0xf
+#define SQ_S_SETVSKIP 0x10
+#define SQ_S_SET_GPR_IDX_ON 0x11
+#define SQ_S_CMP_EQ_U64 0x12
+#define SQ_S_CMP_LG_U64 0x13
+#define SQ_M0 0x7c
+#define SQ_V_MAD_LEGACY_F32 0x1c0
+#define SQ_V_MAD_F32 0x1c1
+#define SQ_V_MAD_I32_I24 0x1c2
+#define SQ_V_MAD_U32_U24 0x1c3
+#define SQ_V_CUBEID_F32 0x1c4
+#define SQ_V_CUBESC_F32 0x1c5
+#define SQ_V_CUBETC_F32 0x1c6
+#define SQ_V_CUBEMA_F32 0x1c7
+#define SQ_V_BFE_U32 0x1c8
+#define SQ_V_BFE_I32 0x1c9
+#define SQ_V_BFI_B32 0x1ca
+#define SQ_V_FMA_F32 0x1cb
+#define SQ_V_FMA_F64 0x1cc
+#define SQ_V_LERP_U8 0x1cd
+#define SQ_V_ALIGNBIT_B32 0x1ce
+#define SQ_V_ALIGNBYTE_B32 0x1cf
+#define SQ_V_MIN3_F32 0x1d0
+#define SQ_V_MIN3_I32 0x1d1
+#define SQ_V_MIN3_U32 0x1d2
+#define SQ_V_MAX3_F32 0x1d3
+#define SQ_V_MAX3_I32 0x1d4
+#define SQ_V_MAX3_U32 0x1d5
+#define SQ_V_MED3_F32 0x1d6
+#define SQ_V_MED3_I32 0x1d7
+#define SQ_V_MED3_U32 0x1d8
+#define SQ_V_SAD_U8 0x1d9
+#define SQ_V_SAD_HI_U8 0x1da
+#define SQ_V_SAD_U16 0x1db
+#define SQ_V_SAD_U32 0x1dc
+#define SQ_V_CVT_PK_U8_F32 0x1dd
+#define SQ_V_DIV_FIXUP_F32 0x1de
+#define SQ_V_DIV_FIXUP_F64 0x1df
+#define SQ_V_DIV_SCALE_F32 0x1e0
+#define SQ_V_DIV_SCALE_F64 0x1e1
+#define SQ_V_DIV_FMAS_F32 0x1e2
+#define SQ_V_DIV_FMAS_F64 0x1e3
+#define SQ_V_MSAD_U8 0x1e4
+#define SQ_V_QSAD_PK_U16_U8 0x1e5
+#define SQ_V_MQSAD_PK_U16_U8 0x1e6
+#define SQ_V_MQSAD_U32_U8 0x1e7
+#define SQ_V_MAD_U64_U32 0x1e8
+#define SQ_V_MAD_I64_I32 0x1e9
+#define SQ_V_MAD_F16 0x1ea
+#define SQ_V_MAD_U16 0x1eb
+#define SQ_V_MAD_I16 0x1ec
+#define SQ_V_PERM_B32 0x1ed
+#define SQ_V_FMA_F16 0x1ee
+#define SQ_V_DIV_FIXUP_F16 0x1ef
+#define SQ_V_CVT_PKACCUM_U8_F32 0x1f0
+#define SQ_V_INTERP_P1LL_F16 0x274
+#define SQ_V_INTERP_P1LV_F16 0x275
+#define SQ_V_INTERP_P2_F16 0x276
+#define SQ_V_ADD_F64 0x280
+#define SQ_V_MUL_F64 0x281
+#define SQ_V_MIN_F64 0x282
+#define SQ_V_MAX_F64 0x283
+#define SQ_V_LDEXP_F64 0x284
+#define SQ_V_MUL_LO_U32 0x285
+#define SQ_V_MUL_HI_U32 0x286
+#define SQ_V_MUL_HI_I32 0x287
+#define SQ_V_LDEXP_F32 0x288
+#define SQ_V_READLANE_B32 0x289
+#define SQ_V_WRITELANE_B32 0x28a
+#define SQ_V_BCNT_U32_B32 0x28b
+#define SQ_V_MBCNT_LO_U32_B32 0x28c
+#define SQ_V_MBCNT_HI_U32_B32 0x28d
+#define SQ_V_MAC_LEGACY_F32 0x28e
+#define SQ_V_LSHLREV_B64 0x28f
+#define SQ_V_LSHRREV_B64 0x290
+#define SQ_V_ASHRREV_I64 0x291
+#define SQ_V_TRIG_PREOP_F64 0x292
+#define SQ_V_BFM_B32 0x293
+#define SQ_V_CVT_PKNORM_I16_F32 0x294
+#define SQ_V_CVT_PKNORM_U16_F32 0x295
+#define SQ_V_CVT_PKRTZ_F16_F32 0x296
+#define SQ_V_CVT_PK_U16_U32 0x297
+#define SQ_V_CVT_PK_I16_I32 0x298
+#define SQ_VCC_ALL 0x0
+#define SQ_SRC_EXECZ 0xfc
+#define SQ_FLAT_SCRATCH_LO 0x66
+#define SQ_FLAT_SCRATCH_HI 0x67
+#define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT 0x1
+#define SQ_SYSMSG_OP_REG_RD 0x2
+#define SQ_SYSMSG_OP_HOST_TRAP_ACK 0x3
+#define SQ_SYSMSG_OP_TTRACE_PC 0x4
+#define SQ_HW_REG_MODE 0x1
+#define SQ_HW_REG_STATUS 0x2
+#define SQ_HW_REG_TRAPSTS 0x3
+#define SQ_HW_REG_HW_ID 0x4
+#define SQ_HW_REG_GPR_ALLOC 0x5
+#define SQ_HW_REG_LDS_ALLOC 0x6
+#define SQ_HW_REG_IB_STS 0x7
+#define SQ_HW_REG_PC_LO 0x8
+#define SQ_HW_REG_PC_HI 0x9
+#define SQ_HW_REG_INST_DW0 0xa
+#define SQ_HW_REG_INST_DW1 0xb
+#define SQ_HW_REG_IB_DBG0 0xc
+#define SQ_HW_REG_IB_DBG1 0xd
+#define SQ_DPP_BOUND_OFF 0x0
+#define SQ_DPP_BOUND_ZERO 0x1
+#define SQ_R1 0x1
+#define SQ_R2 0x2
+#define SQ_R3 0x3
+#define SQ_R4 0x4
+#define SQ_R5 0x5
+#define SQ_R6 0x6
+#define SQ_R7 0x7
+#define SQ_R8 0x8
+#define SQ_R9 0x9
+#define SQ_R10 0xa
+#define SQ_R11 0xb
+#define SQ_R12 0xc
+#define SQ_R13 0xd
+#define SQ_R14 0xe
+#define SQ_R15 0xf
+#define SQ_S_ADD_U32 0x0
+#define SQ_S_SUB_U32 0x1
+#define SQ_S_ADD_I32 0x2
+#define SQ_S_SUB_I32 0x3
+#define SQ_S_ADDC_U32 0x4
+#define SQ_S_SUBB_U32 0x5
+#define SQ_S_MIN_I32 0x6
+#define SQ_S_MIN_U32 0x7
+#define SQ_S_MAX_I32 0x8
+#define SQ_S_MAX_U32 0x9
+#define SQ_S_CSELECT_B32 0xa
+#define SQ_S_CSELECT_B64 0xb
+#define SQ_S_AND_B32 0xc
+#define SQ_S_AND_B64 0xd
+#define SQ_S_OR_B32 0xe
+#define SQ_S_OR_B64 0xf
+#define SQ_S_XOR_B32 0x10
+#define SQ_S_XOR_B64 0x11
+#define SQ_S_ANDN2_B32 0x12
+#define SQ_S_ANDN2_B64 0x13
+#define SQ_S_ORN2_B32 0x14
+#define SQ_S_ORN2_B64 0x15
+#define SQ_S_NAND_B32 0x16
+#define SQ_S_NAND_B64 0x17
+#define SQ_S_NOR_B32 0x18
+#define SQ_S_NOR_B64 0x19
+#define SQ_S_XNOR_B32 0x1a
+#define SQ_S_XNOR_B64 0x1b
+#define SQ_S_LSHL_B32 0x1c
+#define SQ_S_LSHL_B64 0x1d
+#define SQ_S_LSHR_B32 0x1e
+#define SQ_S_LSHR_B64 0x1f
+#define SQ_S_ASHR_I32 0x20
+#define SQ_S_ASHR_I64 0x21
+#define SQ_S_BFM_B32 0x22
+#define SQ_S_BFM_B64 0x23
+#define SQ_S_MUL_I32 0x24
+#define SQ_S_BFE_U32 0x25
+#define SQ_S_BFE_I32 0x26
+#define SQ_S_BFE_U64 0x27
+#define SQ_S_BFE_I64 0x28
+#define SQ_S_CBRANCH_G_FORK 0x29
+#define SQ_S_ABSDIFF_I32 0x2a
+#define SQ_S_RFE_RESTORE_B64 0x2b
+#define SQ_MSG_INTERRUPT 0x1
+#define SQ_MSG_GS 0x2
+#define SQ_MSG_GS_DONE 0x3
+#define SQ_MSG_SAVEWAVE 0x4
+#define SQ_MSG_SYSMSG 0xf
+typedef enum TEX_BORDER_COLOR_TYPE {
+ TEX_BorderColor_TransparentBlack = 0x0,
+ TEX_BorderColor_OpaqueBlack = 0x1,
+ TEX_BorderColor_OpaqueWhite = 0x2,
+ TEX_BorderColor_Register = 0x3,
+} TEX_BORDER_COLOR_TYPE;
+typedef enum TEX_CHROMA_KEY {
+ TEX_ChromaKey_Disabled = 0x0,
+ TEX_ChromaKey_Kill = 0x1,
+ TEX_ChromaKey_Blend = 0x2,
+ TEX_ChromaKey_RESERVED_3 = 0x3,
+} TEX_CHROMA_KEY;
+typedef enum TEX_CLAMP {
+ TEX_Clamp_Repeat = 0x0,
+ TEX_Clamp_Mirror = 0x1,
+ TEX_Clamp_ClampToLast = 0x2,
+ TEX_Clamp_MirrorOnceToLast = 0x3,
+ TEX_Clamp_ClampHalfToBorder = 0x4,
+ TEX_Clamp_MirrorOnceHalfToBorder = 0x5,
+ TEX_Clamp_ClampToBorder = 0x6,
+ TEX_Clamp_MirrorOnceToBorder = 0x7,
+} TEX_CLAMP;
+typedef enum TEX_COORD_TYPE {
+ TEX_CoordType_Unnormalized = 0x0,
+ TEX_CoordType_Normalized = 0x1,
+} TEX_COORD_TYPE;
+typedef enum TEX_DEPTH_COMPARE_FUNCTION {
+ TEX_DepthCompareFunction_Never = 0x0,
+ TEX_DepthCompareFunction_Less = 0x1,
+ TEX_DepthCompareFunction_Equal = 0x2,
+ TEX_DepthCompareFunction_LessEqual = 0x3,
+ TEX_DepthCompareFunction_Greater = 0x4,
+ TEX_DepthCompareFunction_NotEqual = 0x5,
+ TEX_DepthCompareFunction_GreaterEqual = 0x6,
+ TEX_DepthCompareFunction_Always = 0x7,
+} TEX_DEPTH_COMPARE_FUNCTION;
+typedef enum TEX_DIM {
+ TEX_Dim_1D = 0x0,
+ TEX_Dim_2D = 0x1,
+ TEX_Dim_3D = 0x2,
+ TEX_Dim_CubeMap = 0x3,
+ TEX_Dim_1DArray = 0x4,
+ TEX_Dim_2DArray = 0x5,
+ TEX_Dim_2D_MSAA = 0x6,
+ TEX_Dim_2DArray_MSAA = 0x7,
+} TEX_DIM;
+typedef enum TEX_FORMAT_COMP {
+ TEX_FormatComp_Unsigned = 0x0,
+ TEX_FormatComp_Signed = 0x1,
+ TEX_FormatComp_UnsignedBiased = 0x2,
+ TEX_FormatComp_RESERVED_3 = 0x3,
+} TEX_FORMAT_COMP;
+typedef enum TEX_MAX_ANISO_RATIO {
+ TEX_MaxAnisoRatio_1to1 = 0x0,
+ TEX_MaxAnisoRatio_2to1 = 0x1,
+ TEX_MaxAnisoRatio_4to1 = 0x2,
+ TEX_MaxAnisoRatio_8to1 = 0x3,
+ TEX_MaxAnisoRatio_16to1 = 0x4,
+ TEX_MaxAnisoRatio_RESERVED_5 = 0x5,
+ TEX_MaxAnisoRatio_RESERVED_6 = 0x6,
+ TEX_MaxAnisoRatio_RESERVED_7 = 0x7,
+} TEX_MAX_ANISO_RATIO;
+typedef enum TEX_MIP_FILTER {
+ TEX_MipFilter_None = 0x0,
+ TEX_MipFilter_Point = 0x1,
+ TEX_MipFilter_Linear = 0x2,
+ TEX_MipFilter_Point_Aniso_Adj = 0x3,
+} TEX_MIP_FILTER;
+typedef enum TEX_REQUEST_SIZE {
+ TEX_RequestSize_32B = 0x0,
+ TEX_RequestSize_64B = 0x1,
+ TEX_RequestSize_128B = 0x2,
+ TEX_RequestSize_2X64B = 0x3,
+} TEX_REQUEST_SIZE;
+typedef enum TEX_SAMPLER_TYPE {
+ TEX_SamplerType_Invalid = 0x0,
+ TEX_SamplerType_Valid = 0x1,
+} TEX_SAMPLER_TYPE;
+typedef enum TEX_XY_FILTER {
+ TEX_XYFilter_Point = 0x0,
+ TEX_XYFilter_Linear = 0x1,
+ TEX_XYFilter_AnisoPoint = 0x2,
+ TEX_XYFilter_AnisoLinear = 0x3,
+} TEX_XY_FILTER;
+typedef enum TEX_Z_FILTER {
+ TEX_ZFilter_None = 0x0,
+ TEX_ZFilter_Point = 0x1,
+ TEX_ZFilter_Linear = 0x2,
+ TEX_ZFilter_RESERVED_3 = 0x3,
+} TEX_Z_FILTER;
+typedef enum VTX_CLAMP {
+ VTX_Clamp_ClampToZero = 0x0,
+ VTX_Clamp_ClampToNAN = 0x1,
+} VTX_CLAMP;
+typedef enum VTX_FETCH_TYPE {
+ VTX_FetchType_VertexData = 0x0,
+ VTX_FetchType_InstanceData = 0x1,
+ VTX_FetchType_NoIndexOffset = 0x2,
+ VTX_FetchType_RESERVED_3 = 0x3,
+} VTX_FETCH_TYPE;
+typedef enum VTX_FORMAT_COMP_ALL {
+ VTX_FormatCompAll_Unsigned = 0x0,
+ VTX_FormatCompAll_Signed = 0x1,
+} VTX_FORMAT_COMP_ALL;
+typedef enum VTX_MEM_REQUEST_SIZE {
+ VTX_MemRequestSize_32B = 0x0,
+ VTX_MemRequestSize_64B = 0x1,
+} VTX_MEM_REQUEST_SIZE;
+typedef enum TVX_DATA_FORMAT {
+ TVX_FMT_INVALID = 0x0,
+ TVX_FMT_8 = 0x1,
+ TVX_FMT_4_4 = 0x2,
+ TVX_FMT_3_3_2 = 0x3,
+ TVX_FMT_RESERVED_4 = 0x4,
+ TVX_FMT_16 = 0x5,
+ TVX_FMT_16_FLOAT = 0x6,
+ TVX_FMT_8_8 = 0x7,
+ TVX_FMT_5_6_5 = 0x8,
+ TVX_FMT_6_5_5 = 0x9,
+ TVX_FMT_1_5_5_5 = 0xa,
+ TVX_FMT_4_4_4_4 = 0xb,
+ TVX_FMT_5_5_5_1 = 0xc,
+ TVX_FMT_32 = 0xd,
+ TVX_FMT_32_FLOAT = 0xe,
+ TVX_FMT_16_16 = 0xf,
+ TVX_FMT_16_16_FLOAT = 0x10,
+ TVX_FMT_8_24 = 0x11,
+ TVX_FMT_8_24_FLOAT = 0x12,
+ TVX_FMT_24_8 = 0x13,
+ TVX_FMT_24_8_FLOAT = 0x14,
+ TVX_FMT_10_11_11 = 0x15,
+ TVX_FMT_10_11_11_FLOAT = 0x16,
+ TVX_FMT_11_11_10 = 0x17,
+ TVX_FMT_11_11_10_FLOAT = 0x18,
+ TVX_FMT_2_10_10_10 = 0x19,
+ TVX_FMT_8_8_8_8 = 0x1a,
+ TVX_FMT_10_10_10_2 = 0x1b,
+ TVX_FMT_X24_8_32_FLOAT = 0x1c,
+ TVX_FMT_32_32 = 0x1d,
+ TVX_FMT_32_32_FLOAT = 0x1e,
+ TVX_FMT_16_16_16_16 = 0x1f,
+ TVX_FMT_16_16_16_16_FLOAT = 0x20,
+ TVX_FMT_RESERVED_33 = 0x21,
+ TVX_FMT_32_32_32_32 = 0x22,
+ TVX_FMT_32_32_32_32_FLOAT = 0x23,
+ TVX_FMT_RESERVED_36 = 0x24,
+ TVX_FMT_1 = 0x25,
+ TVX_FMT_1_REVERSED = 0x26,
+ TVX_FMT_GB_GR = 0x27,
+ TVX_FMT_BG_RG = 0x28,
+ TVX_FMT_32_AS_8 = 0x29,
+ TVX_FMT_32_AS_8_8 = 0x2a,
+ TVX_FMT_5_9_9_9_SHAREDEXP = 0x2b,
+ TVX_FMT_8_8_8 = 0x2c,
+ TVX_FMT_16_16_16 = 0x2d,
+ TVX_FMT_16_16_16_FLOAT = 0x2e,
+ TVX_FMT_32_32_32 = 0x2f,
+ TVX_FMT_32_32_32_FLOAT = 0x30,
+ TVX_FMT_BC1 = 0x31,
+ TVX_FMT_BC2 = 0x32,
+ TVX_FMT_BC3 = 0x33,
+ TVX_FMT_BC4 = 0x34,
+ TVX_FMT_BC5 = 0x35,
+ TVX_FMT_APC0 = 0x36,
+ TVX_FMT_APC1 = 0x37,
+ TVX_FMT_APC2 = 0x38,
+ TVX_FMT_APC3 = 0x39,
+ TVX_FMT_APC4 = 0x3a,
+ TVX_FMT_APC5 = 0x3b,
+ TVX_FMT_APC6 = 0x3c,
+ TVX_FMT_APC7 = 0x3d,
+ TVX_FMT_CTX1 = 0x3e,
+ TVX_FMT_RESERVED_63 = 0x3f,
+} TVX_DATA_FORMAT;
+typedef enum TVX_DST_SEL {
+ TVX_DstSel_X = 0x0,
+ TVX_DstSel_Y = 0x1,
+ TVX_DstSel_Z = 0x2,
+ TVX_DstSel_W = 0x3,
+ TVX_DstSel_0f = 0x4,
+ TVX_DstSel_1f = 0x5,
+ TVX_DstSel_RESERVED_6 = 0x6,
+ TVX_DstSel_Mask = 0x7,
+} TVX_DST_SEL;
+typedef enum TVX_ENDIAN_SWAP {
+ TVX_EndianSwap_None = 0x0,
+ TVX_EndianSwap_8in16 = 0x1,
+ TVX_EndianSwap_8in32 = 0x2,
+ TVX_EndianSwap_8in64 = 0x3,
+} TVX_ENDIAN_SWAP;
+typedef enum TVX_INST {
+ TVX_Inst_NormalVertexFetch = 0x0,
+ TVX_Inst_SemanticVertexFetch = 0x1,
+ TVX_Inst_RESERVED_2 = 0x2,
+ TVX_Inst_LD = 0x3,
+ TVX_Inst_GetTextureResInfo = 0x4,
+ TVX_Inst_GetNumberOfSamples = 0x5,
+ TVX_Inst_GetLOD = 0x6,
+ TVX_Inst_GetGradientsH = 0x7,
+ TVX_Inst_GetGradientsV = 0x8,
+ TVX_Inst_SetTextureOffsets = 0x9,
+ TVX_Inst_KeepGradients = 0xa,
+ TVX_Inst_SetGradientsH = 0xb,
+ TVX_Inst_SetGradientsV = 0xc,
+ TVX_Inst_Pass = 0xd,
+ TVX_Inst_GetBufferResInfo = 0xe,
+ TVX_Inst_RESERVED_15 = 0xf,
+ TVX_Inst_Sample = 0x10,
+ TVX_Inst_Sample_L = 0x11,
+ TVX_Inst_Sample_LB = 0x12,
+ TVX_Inst_Sample_LZ = 0x13,
+ TVX_Inst_Sample_G = 0x14,
+ TVX_Inst_Gather4 = 0x15,
+ TVX_Inst_Sample_G_LB = 0x16,
+ TVX_Inst_Gather4_O = 0x17,
+ TVX_Inst_Sample_C = 0x18,
+ TVX_Inst_Sample_C_L = 0x19,
+ TVX_Inst_Sample_C_LB = 0x1a,
+ TVX_Inst_Sample_C_LZ = 0x1b,
+ TVX_Inst_Sample_C_G = 0x1c,
+ TVX_Inst_Gather4_C = 0x1d,
+ TVX_Inst_Sample_C_G_LB = 0x1e,
+ TVX_Inst_Gather4_C_O = 0x1f,
+} TVX_INST;
+typedef enum TVX_NUM_FORMAT_ALL {
+ TVX_NumFormatAll_Norm = 0x0,
+ TVX_NumFormatAll_Int = 0x1,
+ TVX_NumFormatAll_Scaled = 0x2,
+ TVX_NumFormatAll_RESERVED_3 = 0x3,
+} TVX_NUM_FORMAT_ALL;
+typedef enum TVX_SRC_SEL {
+ TVX_SrcSel_X = 0x0,
+ TVX_SrcSel_Y = 0x1,
+ TVX_SrcSel_Z = 0x2,
+ TVX_SrcSel_W = 0x3,
+ TVX_SrcSel_0f = 0x4,
+ TVX_SrcSel_1f = 0x5,
+} TVX_SRC_SEL;
+typedef enum TVX_SRF_MODE_ALL {
+ TVX_SRFModeAll_ZCMO = 0x0,
+ TVX_SRFModeAll_NZ = 0x1,
+} TVX_SRF_MODE_ALL;
+typedef enum TVX_TYPE {
+ TVX_Type_InvalidTextureResource = 0x0,
+ TVX_Type_InvalidVertexBuffer = 0x1,
+ TVX_Type_ValidTextureResource = 0x2,
+ TVX_Type_ValidVertexBuffer = 0x3,
+} TVX_TYPE;
+typedef enum TC_OP_MASKS {
+ TC_OP_MASK_FLUSH_DENROM = 0x8,
+ TC_OP_MASK_64 = 0x20,
+ TC_OP_MASK_NO_RTN = 0x40,
+} TC_OP_MASKS;
+typedef enum TC_OP {
+ TC_OP_READ = 0x0,
+ TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x1,
+ TC_OP_ATOMIC_FMIN_RTN_32 = 0x2,
+ TC_OP_ATOMIC_FMAX_RTN_32 = 0x3,
+ TC_OP_RESERVED_FOP_RTN_32_0 = 0x4,
+ TC_OP_RESERVED_FOP_RTN_32_1 = 0x5,
+ TC_OP_RESERVED_FOP_RTN_32_2 = 0x6,
+ TC_OP_ATOMIC_SWAP_RTN_32 = 0x7,
+ TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x8,
+ TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x9,
+ TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0xa,
+ TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0xb,
+ TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_0 = 0xc,
+ TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0xd,
+ TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0xe,
+ TC_OP_ATOMIC_ADD_RTN_32 = 0xf,
+ TC_OP_ATOMIC_SUB_RTN_32 = 0x10,
+ TC_OP_ATOMIC_SMIN_RTN_32 = 0x11,
+ TC_OP_ATOMIC_UMIN_RTN_32 = 0x12,
+ TC_OP_ATOMIC_SMAX_RTN_32 = 0x13,
+ TC_OP_ATOMIC_UMAX_RTN_32 = 0x14,
+ TC_OP_ATOMIC_AND_RTN_32 = 0x15,
+ TC_OP_ATOMIC_OR_RTN_32 = 0x16,
+ TC_OP_ATOMIC_XOR_RTN_32 = 0x17,
+ TC_OP_ATOMIC_INC_RTN_32 = 0x18,
+ TC_OP_ATOMIC_DEC_RTN_32 = 0x19,
+ TC_OP_WBINVL1_VOL = 0x1a,
+ TC_OP_WBINVL1_SD = 0x1b,
+ TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x1c,
+ TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x1d,
+ TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x1e,
+ TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x1f,
+ TC_OP_WRITE = 0x20,
+ TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x21,
+ TC_OP_ATOMIC_FMIN_RTN_64 = 0x22,
+ TC_OP_ATOMIC_FMAX_RTN_64 = 0x23,
+ TC_OP_RESERVED_FOP_RTN_64_0 = 0x24,
+ TC_OP_RESERVED_FOP_RTN_64_1 = 0x25,
+ TC_OP_RESERVED_FOP_RTN_64_2 = 0x26,
+ TC_OP_ATOMIC_SWAP_RTN_64 = 0x27,
+ TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x28,
+ TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x29,
+ TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x2a,
+ TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x2b,
+ TC_OP_WBINVL2_SD = 0x2c,
+ TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x2d,
+ TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x2e,
+ TC_OP_ATOMIC_ADD_RTN_64 = 0x2f,
+ TC_OP_ATOMIC_SUB_RTN_64 = 0x30,
+ TC_OP_ATOMIC_SMIN_RTN_64 = 0x31,
+ TC_OP_ATOMIC_UMIN_RTN_64 = 0x32,
+ TC_OP_ATOMIC_SMAX_RTN_64 = 0x33,
+ TC_OP_ATOMIC_UMAX_RTN_64 = 0x34,
+ TC_OP_ATOMIC_AND_RTN_64 = 0x35,
+ TC_OP_ATOMIC_OR_RTN_64 = 0x36,
+ TC_OP_ATOMIC_XOR_RTN_64 = 0x37,
+ TC_OP_ATOMIC_INC_RTN_64 = 0x38,
+ TC_OP_ATOMIC_DEC_RTN_64 = 0x39,
+ TC_OP_WBL2_NC = 0x3a,
+ TC_OP_RESERVED_NON_FLOAT_RTN_64_0 = 0x3b,
+ TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x3c,
+ TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x3d,
+ TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x3e,
+ TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x3f,
+ TC_OP_WBINVL1 = 0x40,
+ TC_OP_ATOMIC_FCMPSWAP_32 = 0x41,
+ TC_OP_ATOMIC_FMIN_32 = 0x42,
+ TC_OP_ATOMIC_FMAX_32 = 0x43,
+ TC_OP_RESERVED_FOP_32_0 = 0x44,
+ TC_OP_RESERVED_FOP_32_1 = 0x45,
+ TC_OP_RESERVED_FOP_32_2 = 0x46,
+ TC_OP_ATOMIC_SWAP_32 = 0x47,
+ TC_OP_ATOMIC_CMPSWAP_32 = 0x48,
+ TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x49,
+ TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x4a,
+ TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x4b,
+ TC_OP_RESERVED_FOP_FLUSH_DENORM_32_0 = 0x4c,
+ TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 0x4d,
+ TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x4e,
+ TC_OP_ATOMIC_ADD_32 = 0x4f,
+ TC_OP_ATOMIC_SUB_32 = 0x50,
+ TC_OP_ATOMIC_SMIN_32 = 0x51,
+ TC_OP_ATOMIC_UMIN_32 = 0x52,
+ TC_OP_ATOMIC_SMAX_32 = 0x53,
+ TC_OP_ATOMIC_UMAX_32 = 0x54,
+ TC_OP_ATOMIC_AND_32 = 0x55,
+ TC_OP_ATOMIC_OR_32 = 0x56,
+ TC_OP_ATOMIC_XOR_32 = 0x57,
+ TC_OP_ATOMIC_INC_32 = 0x58,
+ TC_OP_ATOMIC_DEC_32 = 0x59,
+ TC_OP_INVL2_NC = 0x5a,
+ TC_OP_RESERVED_NON_FLOAT_32_0 = 0x5b,
+ TC_OP_RESERVED_NON_FLOAT_32_1 = 0x5c,
+ TC_OP_RESERVED_NON_FLOAT_32_2 = 0x5d,
+ TC_OP_RESERVED_NON_FLOAT_32_3 = 0x5e,
+ TC_OP_RESERVED_NON_FLOAT_32_4 = 0x5f,
+ TC_OP_WBINVL2 = 0x60,
+ TC_OP_ATOMIC_FCMPSWAP_64 = 0x61,
+ TC_OP_ATOMIC_FMIN_64 = 0x62,
+ TC_OP_ATOMIC_FMAX_64 = 0x63,
+ TC_OP_RESERVED_FOP_64_0 = 0x64,
+ TC_OP_RESERVED_FOP_64_1 = 0x65,
+ TC_OP_RESERVED_FOP_64_2 = 0x66,
+ TC_OP_ATOMIC_SWAP_64 = 0x67,
+ TC_OP_ATOMIC_CMPSWAP_64 = 0x68,
+ TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x69,
+ TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x6a,
+ TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x6b,
+ TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x6c,
+ TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x6d,
+ TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x6e,
+ TC_OP_ATOMIC_ADD_64 = 0x6f,
+ TC_OP_ATOMIC_SUB_64 = 0x70,
+ TC_OP_ATOMIC_SMIN_64 = 0x71,
+ TC_OP_ATOMIC_UMIN_64 = 0x72,
+ TC_OP_ATOMIC_SMAX_64 = 0x73,
+ TC_OP_ATOMIC_UMAX_64 = 0x74,
+ TC_OP_ATOMIC_AND_64 = 0x75,
+ TC_OP_ATOMIC_OR_64 = 0x76,
+ TC_OP_ATOMIC_XOR_64 = 0x77,
+ TC_OP_ATOMIC_INC_64 = 0x78,
+ TC_OP_ATOMIC_DEC_64 = 0x79,
+ TC_OP_WBINVL2_NC = 0x7a,
+ TC_OP_RESERVED_NON_FLOAT_64_0 = 0x7b,
+ TC_OP_RESERVED_NON_FLOAT_64_1 = 0x7c,
+ TC_OP_RESERVED_NON_FLOAT_64_2 = 0x7d,
+ TC_OP_RESERVED_NON_FLOAT_64_3 = 0x7e,
+ TC_OP_RESERVED_NON_FLOAT_64_4 = 0x7f,
+} TC_OP;
+typedef enum TC_CHUB_REQ_CREDITS_ENUM {
+ TC_CHUB_REQ_CREDITS = 0x10,
+} TC_CHUB_REQ_CREDITS_ENUM;
+typedef enum CHUB_TC_RET_CREDITS_ENUM {
+ CHUB_TC_RET_CREDITS = 0x20,
+} CHUB_TC_RET_CREDITS_ENUM;
+typedef enum TC_NACKS {
+ TC_NACK_NO_FAULT = 0x0,
+ TC_NACK_PAGE_FAULT = 0x1,
+ TC_NACK_PROTECTION_FAULT = 0x2,
+ TC_NACK_DATA_ERROR = 0x3,
+} TC_NACKS;
+typedef enum TCC_PERF_SEL {
+ TCC_PERF_SEL_NONE = 0x0,
+ TCC_PERF_SEL_CYCLE = 0x1,
+ TCC_PERF_SEL_BUSY = 0x2,
+ TCC_PERF_SEL_REQ = 0x3,
+ TCC_PERF_SEL_STREAMING_REQ = 0x4,
+ TCC_PERF_SEL_EXE_REQ = 0x5,
+ TCC_PERF_SEL_COMPRESSED_REQ = 0x6,
+ TCC_PERF_SEL_COMPRESSED_0_REQ = 0x7,
+ TCC_PERF_SEL_METADATA_REQ = 0x8,
+ TCC_PERF_SEL_NC_VIRTUAL_REQ = 0x9,
+ TCC_PERF_SEL_NC_PHYSICAL_REQ = 0xa,
+ TCC_PERF_SEL_UC_VIRTUAL_REQ = 0xb,
+ TCC_PERF_SEL_UC_PHYSICAL_REQ = 0xc,
+ TCC_PERF_SEL_CC_PHYSICAL_REQ = 0xd,
+ TCC_PERF_SEL_PROBE = 0xe,
+ TCC_PERF_SEL_READ = 0xf,
+ TCC_PERF_SEL_WRITE = 0x10,
+ TCC_PERF_SEL_ATOMIC = 0x11,
+ TCC_PERF_SEL_HIT = 0x12,
+ TCC_PERF_SEL_MISS = 0x13,
+ TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT = 0x14,
+ TCC_PERF_SEL_FULLY_WRITTEN_HIT = 0x15,
+ TCC_PERF_SEL_WRITEBACK = 0x16,
+ TCC_PERF_SEL_LATENCY_FIFO_FULL = 0x17,
+ TCC_PERF_SEL_SRC_FIFO_FULL = 0x18,
+ TCC_PERF_SEL_HOLE_FIFO_FULL = 0x19,
+ TCC_PERF_SEL_MC_WRREQ = 0x1a,
+ TCC_PERF_SEL_MC_WRREQ_UNCACHED = 0x1b,
+ TCC_PERF_SEL_MC_WRREQ_STALL = 0x1c,
+ TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL = 0x1d,
+ TCC_PERF_SEL_MC_WRREQ_MC_HALT_STALL = 0x1e,
+ TCC_PERF_SEL_TOO_MANY_MC_WRREQS_STALL = 0x1f,
+ TCC_PERF_SEL_MC_WRREQ_LEVEL = 0x20,
+ TCC_PERF_SEL_MC_ATOMIC = 0x21,
+ TCC_PERF_SEL_MC_ATOMIC_LEVEL = 0x22,
+ TCC_PERF_SEL_MC_RDREQ = 0x23,
+ TCC_PERF_SEL_MC_RDREQ_UNCACHED = 0x24,
+ TCC_PERF_SEL_MC_RDREQ_MDC = 0x25,
+ TCC_PERF_SEL_MC_RDREQ_COMPRESSED = 0x26,
+ TCC_PERF_SEL_MC_RDREQ_CREDIT_STALL = 0x27,
+ TCC_PERF_SEL_MC_RDREQ_MC_HALT_STALL = 0x28,
+ TCC_PERF_SEL_MC_RDREQ_LEVEL = 0x29,
+ TCC_PERF_SEL_TAG_STALL = 0x2a,
+ TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 0x2b,
+ TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x2c,
+ TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL= 0x2d,
+ TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL= 0x2e,
+ TCC_PERF_SEL_TAG_PROBE_STALL = 0x2f,
+ TCC_PERF_SEL_TAG_PROBE_FILTER_STALL = 0x30,
+ TCC_PERF_SEL_READ_RETURN_TIMEOUT = 0x31,
+ TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT = 0x32,
+ TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE = 0x33,
+ TCC_PERF_SEL_BUBBLE = 0x34,
+ TCC_PERF_SEL_RETURN_ACK = 0x35,
+ TCC_PERF_SEL_RETURN_DATA = 0x36,
+ TCC_PERF_SEL_RETURN_HOLE = 0x37,
+ TCC_PERF_SEL_RETURN_ACK_HOLE = 0x38,
+ TCC_PERF_SEL_IB_REQ = 0x39,
+ TCC_PERF_SEL_IB_STALL = 0x3a,
+ TCC_PERF_SEL_IB_TAG_STALL = 0x3b,
+ TCC_PERF_SEL_IB_MDC_STALL = 0x3c,
+ TCC_PERF_SEL_TCA_LEVEL = 0x3d,
+ TCC_PERF_SEL_HOLE_LEVEL = 0x3e,
+ TCC_PERF_SEL_MC_RDRET_NACK = 0x3f,
+ TCC_PERF_SEL_MC_WRRET_NACK = 0x40,
+ TCC_PERF_SEL_NORMAL_WRITEBACK = 0x41,
+ TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK = 0x42,
+ TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK = 0x43,
+ TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK = 0x44,
+ TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK = 0x45,
+ TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK = 0x46,
+ TCC_PERF_SEL_NORMAL_EVICT = 0x47,
+ TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT = 0x48,
+ TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT = 0x49,
+ TCC_PERF_SEL_TC_OP_WBINVL2_EVICT = 0x4a,
+ TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT = 0x4b,
+ TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT = 0x4c,
+ TCC_PERF_SEL_ALL_TC_OP_INV_EVICT = 0x4d,
+ TCC_PERF_SEL_PROBE_EVICT = 0x4e,
+ TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE = 0x4f,
+ TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE = 0x50,
+ TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE = 0x51,
+ TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE = 0x52,
+ TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE = 0x53,
+ TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE = 0x54,
+ TCC_PERF_SEL_TC_OP_WBL2_NC_START = 0x55,
+ TCC_PERF_SEL_TC_OP_INVL2_NC_START = 0x56,
+ TCC_PERF_SEL_TC_OP_WBINVL2_START = 0x57,
+ TCC_PERF_SEL_TC_OP_WBINVL2_NC_START = 0x58,
+ TCC_PERF_SEL_TC_OP_WBINVL2_SD_START = 0x59,
+ TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 0x5a,
+ TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH = 0x5b,
+ TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH = 0x5c,
+ TCC_PERF_SEL_TC_OP_WBINVL2_FINISH = 0x5d,
+ TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH = 0x5e,
+ TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH = 0x5f,
+ TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH = 0x60,
+ TCC_PERF_SEL_MDC_REQ = 0x61,
+ TCC_PERF_SEL_MDC_LEVEL = 0x62,
+ TCC_PERF_SEL_MDC_TAG_HIT = 0x63,
+ TCC_PERF_SEL_MDC_SECTOR_HIT = 0x64,
+ TCC_PERF_SEL_MDC_SECTOR_MISS = 0x65,
+ TCC_PERF_SEL_MDC_TAG_STALL = 0x66,
+ TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL= 0x67,
+ TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL= 0x68,
+ TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL= 0x69,
+ TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 0x6a,
+ TCC_PERF_SEL_PROBE_FILTER_DISABLED = 0x6b,
+ TCC_PERF_SEL_CLIENT0_REQ = 0x80,
+ TCC_PERF_SEL_CLIENT1_REQ = 0x81,
+ TCC_PERF_SEL_CLIENT2_REQ = 0x82,
+ TCC_PERF_SEL_CLIENT3_REQ = 0x83,
+ TCC_PERF_SEL_CLIENT4_REQ = 0x84,
+ TCC_PERF_SEL_CLIENT5_REQ = 0x85,
+ TCC_PERF_SEL_CLIENT6_REQ = 0x86,
+ TCC_PERF_SEL_CLIENT7_REQ = 0x87,
+ TCC_PERF_SEL_CLIENT8_REQ = 0x88,
+ TCC_PERF_SEL_CLIENT9_REQ = 0x89,
+ TCC_PERF_SEL_CLIENT10_REQ = 0x8a,
+ TCC_PERF_SEL_CLIENT11_REQ = 0x8b,
+ TCC_PERF_SEL_CLIENT12_REQ = 0x8c,
+ TCC_PERF_SEL_CLIENT13_REQ = 0x8d,
+ TCC_PERF_SEL_CLIENT14_REQ = 0x8e,
+ TCC_PERF_SEL_CLIENT15_REQ = 0x8f,
+ TCC_PERF_SEL_CLIENT16_REQ = 0x90,
+ TCC_PERF_SEL_CLIENT17_REQ = 0x91,
+ TCC_PERF_SEL_CLIENT18_REQ = 0x92,
+ TCC_PERF_SEL_CLIENT19_REQ = 0x93,
+ TCC_PERF_SEL_CLIENT20_REQ = 0x94,
+ TCC_PERF_SEL_CLIENT21_REQ = 0x95,
+ TCC_PERF_SEL_CLIENT22_REQ = 0x96,
+ TCC_PERF_SEL_CLIENT23_REQ = 0x97,
+ TCC_PERF_SEL_CLIENT24_REQ = 0x98,
+ TCC_PERF_SEL_CLIENT25_REQ = 0x99,
+ TCC_PERF_SEL_CLIENT26_REQ = 0x9a,
+ TCC_PERF_SEL_CLIENT27_REQ = 0x9b,
+ TCC_PERF_SEL_CLIENT28_REQ = 0x9c,
+ TCC_PERF_SEL_CLIENT29_REQ = 0x9d,
+ TCC_PERF_SEL_CLIENT30_REQ = 0x9e,
+ TCC_PERF_SEL_CLIENT31_REQ = 0x9f,
+ TCC_PERF_SEL_CLIENT32_REQ = 0xa0,
+ TCC_PERF_SEL_CLIENT33_REQ = 0xa1,
+ TCC_PERF_SEL_CLIENT34_REQ = 0xa2,
+ TCC_PERF_SEL_CLIENT35_REQ = 0xa3,
+ TCC_PERF_SEL_CLIENT36_REQ = 0xa4,
+ TCC_PERF_SEL_CLIENT37_REQ = 0xa5,
+ TCC_PERF_SEL_CLIENT38_REQ = 0xa6,
+ TCC_PERF_SEL_CLIENT39_REQ = 0xa7,
+ TCC_PERF_SEL_CLIENT40_REQ = 0xa8,
+ TCC_PERF_SEL_CLIENT41_REQ = 0xa9,
+ TCC_PERF_SEL_CLIENT42_REQ = 0xaa,
+ TCC_PERF_SEL_CLIENT43_REQ = 0xab,
+ TCC_PERF_SEL_CLIENT44_REQ = 0xac,
+ TCC_PERF_SEL_CLIENT45_REQ = 0xad,
+ TCC_PERF_SEL_CLIENT46_REQ = 0xae,
+ TCC_PERF_SEL_CLIENT47_REQ = 0xaf,
+ TCC_PERF_SEL_CLIENT48_REQ = 0xb0,
+ TCC_PERF_SEL_CLIENT49_REQ = 0xb1,
+ TCC_PERF_SEL_CLIENT50_REQ = 0xb2,
+ TCC_PERF_SEL_CLIENT51_REQ = 0xb3,
+ TCC_PERF_SEL_CLIENT52_REQ = 0xb4,
+ TCC_PERF_SEL_CLIENT53_REQ = 0xb5,
+ TCC_PERF_SEL_CLIENT54_REQ = 0xb6,
+ TCC_PERF_SEL_CLIENT55_REQ = 0xb7,
+ TCC_PERF_SEL_CLIENT56_REQ = 0xb8,
+ TCC_PERF_SEL_CLIENT57_REQ = 0xb9,
+ TCC_PERF_SEL_CLIENT58_REQ = 0xba,
+ TCC_PERF_SEL_CLIENT59_REQ = 0xbb,
+ TCC_PERF_SEL_CLIENT60_REQ = 0xbc,
+ TCC_PERF_SEL_CLIENT61_REQ = 0xbd,
+ TCC_PERF_SEL_CLIENT62_REQ = 0xbe,
+ TCC_PERF_SEL_CLIENT63_REQ = 0xbf,
+ TCC_PERF_SEL_CLIENT64_REQ = 0xc0,
+ TCC_PERF_SEL_CLIENT65_REQ = 0xc1,
+ TCC_PERF_SEL_CLIENT66_REQ = 0xc2,
+ TCC_PERF_SEL_CLIENT67_REQ = 0xc3,
+ TCC_PERF_SEL_CLIENT68_REQ = 0xc4,
+ TCC_PERF_SEL_CLIENT69_REQ = 0xc5,
+ TCC_PERF_SEL_CLIENT70_REQ = 0xc6,
+ TCC_PERF_SEL_CLIENT71_REQ = 0xc7,
+ TCC_PERF_SEL_CLIENT72_REQ = 0xc8,
+ TCC_PERF_SEL_CLIENT73_REQ = 0xc9,
+ TCC_PERF_SEL_CLIENT74_REQ = 0xca,
+ TCC_PERF_SEL_CLIENT75_REQ = 0xcb,
+ TCC_PERF_SEL_CLIENT76_REQ = 0xcc,
+ TCC_PERF_SEL_CLIENT77_REQ = 0xcd,
+ TCC_PERF_SEL_CLIENT78_REQ = 0xce,
+ TCC_PERF_SEL_CLIENT79_REQ = 0xcf,
+ TCC_PERF_SEL_CLIENT80_REQ = 0xd0,
+ TCC_PERF_SEL_CLIENT81_REQ = 0xd1,
+ TCC_PERF_SEL_CLIENT82_REQ = 0xd2,
+ TCC_PERF_SEL_CLIENT83_REQ = 0xd3,
+ TCC_PERF_SEL_CLIENT84_REQ = 0xd4,
+ TCC_PERF_SEL_CLIENT85_REQ = 0xd5,
+ TCC_PERF_SEL_CLIENT86_REQ = 0xd6,
+ TCC_PERF_SEL_CLIENT87_REQ = 0xd7,
+ TCC_PERF_SEL_CLIENT88_REQ = 0xd8,
+ TCC_PERF_SEL_CLIENT89_REQ = 0xd9,
+ TCC_PERF_SEL_CLIENT90_REQ = 0xda,
+ TCC_PERF_SEL_CLIENT91_REQ = 0xdb,
+ TCC_PERF_SEL_CLIENT92_REQ = 0xdc,
+ TCC_PERF_SEL_CLIENT93_REQ = 0xdd,
+ TCC_PERF_SEL_CLIENT94_REQ = 0xde,
+ TCC_PERF_SEL_CLIENT95_REQ = 0xdf,
+ TCC_PERF_SEL_CLIENT96_REQ = 0xe0,
+ TCC_PERF_SEL_CLIENT97_REQ = 0xe1,
+ TCC_PERF_SEL_CLIENT98_REQ = 0xe2,
+ TCC_PERF_SEL_CLIENT99_REQ = 0xe3,
+ TCC_PERF_SEL_CLIENT100_REQ = 0xe4,
+ TCC_PERF_SEL_CLIENT101_REQ = 0xe5,
+ TCC_PERF_SEL_CLIENT102_REQ = 0xe6,
+ TCC_PERF_SEL_CLIENT103_REQ = 0xe7,
+ TCC_PERF_SEL_CLIENT104_REQ = 0xe8,
+ TCC_PERF_SEL_CLIENT105_REQ = 0xe9,
+ TCC_PERF_SEL_CLIENT106_REQ = 0xea,
+ TCC_PERF_SEL_CLIENT107_REQ = 0xeb,
+ TCC_PERF_SEL_CLIENT108_REQ = 0xec,
+ TCC_PERF_SEL_CLIENT109_REQ = 0xed,
+ TCC_PERF_SEL_CLIENT110_REQ = 0xee,
+ TCC_PERF_SEL_CLIENT111_REQ = 0xef,
+ TCC_PERF_SEL_CLIENT112_REQ = 0xf0,
+ TCC_PERF_SEL_CLIENT113_REQ = 0xf1,
+ TCC_PERF_SEL_CLIENT114_REQ = 0xf2,
+ TCC_PERF_SEL_CLIENT115_REQ = 0xf3,
+ TCC_PERF_SEL_CLIENT116_REQ = 0xf4,
+ TCC_PERF_SEL_CLIENT117_REQ = 0xf5,
+ TCC_PERF_SEL_CLIENT118_REQ = 0xf6,
+ TCC_PERF_SEL_CLIENT119_REQ = 0xf7,
+ TCC_PERF_SEL_CLIENT120_REQ = 0xf8,
+ TCC_PERF_SEL_CLIENT121_REQ = 0xf9,
+ TCC_PERF_SEL_CLIENT122_REQ = 0xfa,
+ TCC_PERF_SEL_CLIENT123_REQ = 0xfb,
+ TCC_PERF_SEL_CLIENT124_REQ = 0xfc,
+ TCC_PERF_SEL_CLIENT125_REQ = 0xfd,
+ TCC_PERF_SEL_CLIENT126_REQ = 0xfe,
+ TCC_PERF_SEL_CLIENT127_REQ = 0xff,
+} TCC_PERF_SEL;
+typedef enum TCA_PERF_SEL {
+ TCA_PERF_SEL_NONE = 0x0,
+ TCA_PERF_SEL_CYCLE = 0x1,
+ TCA_PERF_SEL_BUSY = 0x2,
+ TCA_PERF_SEL_FORCED_HOLE_TCC0 = 0x3,
+ TCA_PERF_SEL_FORCED_HOLE_TCC1 = 0x4,
+ TCA_PERF_SEL_FORCED_HOLE_TCC2 = 0x5,
+ TCA_PERF_SEL_FORCED_HOLE_TCC3 = 0x6,
+ TCA_PERF_SEL_FORCED_HOLE_TCC4 = 0x7,
+ TCA_PERF_SEL_FORCED_HOLE_TCC5 = 0x8,
+ TCA_PERF_SEL_FORCED_HOLE_TCC6 = 0x9,
+ TCA_PERF_SEL_FORCED_HOLE_TCC7 = 0xa,
+ TCA_PERF_SEL_REQ_TCC0 = 0xb,
+ TCA_PERF_SEL_REQ_TCC1 = 0xc,
+ TCA_PERF_SEL_REQ_TCC2 = 0xd,
+ TCA_PERF_SEL_REQ_TCC3 = 0xe,
+ TCA_PERF_SEL_REQ_TCC4 = 0xf,
+ TCA_PERF_SEL_REQ_TCC5 = 0x10,
+ TCA_PERF_SEL_REQ_TCC6 = 0x11,
+ TCA_PERF_SEL_REQ_TCC7 = 0x12,
+ TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0 = 0x13,
+ TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1 = 0x14,
+ TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2 = 0x15,
+ TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3 = 0x16,
+ TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4 = 0x17,
+ TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5 = 0x18,
+ TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6 = 0x19,
+ TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7 = 0x1a,
+ TCA_PERF_SEL_CROSSBAR_STALL_TCC0 = 0x1b,
+ TCA_PERF_SEL_CROSSBAR_STALL_TCC1 = 0x1c,
+ TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 0x1d,
+ TCA_PERF_SEL_CROSSBAR_STALL_TCC3 = 0x1e,
+ TCA_PERF_SEL_CROSSBAR_STALL_TCC4 = 0x1f,
+ TCA_PERF_SEL_CROSSBAR_STALL_TCC5 = 0x20,
+ TCA_PERF_SEL_CROSSBAR_STALL_TCC6 = 0x21,
+ TCA_PERF_SEL_CROSSBAR_STALL_TCC7 = 0x22,
+} TCA_PERF_SEL;
+typedef enum TA_TC_ADDR_MODES {
+ TA_TC_ADDR_MODE_DEFAULT = 0x0,
+ TA_TC_ADDR_MODE_COMP0 = 0x1,
+ TA_TC_ADDR_MODE_COMP1 = 0x2,
+ TA_TC_ADDR_MODE_COMP2 = 0x3,
+ TA_TC_ADDR_MODE_COMP3 = 0x4,
+ TA_TC_ADDR_MODE_UNALIGNED = 0x5,
+ TA_TC_ADDR_MODE_BORDER_COLOR = 0x6,
+} TA_TC_ADDR_MODES;
+typedef enum TA_PERFCOUNT_SEL {
+ TA_PERF_SEL_NULL = 0x0,
+ TA_PERF_SEL_sh_fifo_busy = 0x1,
+ TA_PERF_SEL_sh_fifo_cmd_busy = 0x2,
+ TA_PERF_SEL_sh_fifo_addr_busy = 0x3,
+ TA_PERF_SEL_sh_fifo_data_busy = 0x4,
+ TA_PERF_SEL_sh_fifo_data_sfifo_busy = 0x5,
+ TA_PERF_SEL_sh_fifo_data_tfifo_busy = 0x6,
+ TA_PERF_SEL_gradient_busy = 0x7,
+ TA_PERF_SEL_gradient_fifo_busy = 0x8,
+ TA_PERF_SEL_lod_busy = 0x9,
+ TA_PERF_SEL_lod_fifo_busy = 0xa,
+ TA_PERF_SEL_addresser_busy = 0xb,
+ TA_PERF_SEL_addresser_fifo_busy = 0xc,
+ TA_PERF_SEL_aligner_busy = 0xd,
+ TA_PERF_SEL_write_path_busy = 0xe,
+ TA_PERF_SEL_ta_busy = 0xf,
+ TA_PERF_SEL_sq_ta_cmd_cycles = 0x10,
+ TA_PERF_SEL_sp_ta_addr_cycles = 0x11,
+ TA_PERF_SEL_sp_ta_data_cycles = 0x12,
+ TA_PERF_SEL_ta_fa_data_state_cycles = 0x13,
+ TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 0x14,
+ TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 0x15,
+ TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles= 0x16,
+ TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles= 0x17,
+ TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles= 0x18,
+ TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles= 0x19,
+ TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles= 0x1a,
+ TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles= 0x1b,
+ TA_PERF_SEL_RESERVED_28 = 0x1c,
+ TA_PERF_SEL_RESERVED_29 = 0x1d,
+ TA_PERF_SEL_sh_fifo_addr_cycles = 0x1e,
+ TA_PERF_SEL_sh_fifo_data_cycles = 0x1f,
+ TA_PERF_SEL_total_wavefronts = 0x20,
+ TA_PERF_SEL_gradient_cycles = 0x21,
+ TA_PERF_SEL_walker_cycles = 0x22,
+ TA_PERF_SEL_aligner_cycles = 0x23,
+ TA_PERF_SEL_image_wavefronts = 0x24,
+ TA_PERF_SEL_image_read_wavefronts = 0x25,
+ TA_PERF_SEL_image_write_wavefronts = 0x26,
+ TA_PERF_SEL_image_atomic_wavefronts = 0x27,
+ TA_PERF_SEL_image_total_cycles = 0x28,
+ TA_PERF_SEL_RESERVED_41 = 0x29,
+ TA_PERF_SEL_RESERVED_42 = 0x2a,
+ TA_PERF_SEL_RESERVED_43 = 0x2b,
+ TA_PERF_SEL_buffer_wavefronts = 0x2c,
+ TA_PERF_SEL_buffer_read_wavefronts = 0x2d,
+ TA_PERF_SEL_buffer_write_wavefronts = 0x2e,
+ TA_PERF_SEL_buffer_atomic_wavefronts = 0x2f,
+ TA_PERF_SEL_buffer_coalescable_wavefronts = 0x30,
+ TA_PERF_SEL_buffer_total_cycles = 0x31,
+ TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles= 0x32,
+ TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles= 0x33,
+ TA_PERF_SEL_buffer_coalesced_read_cycles = 0x34,
+ TA_PERF_SEL_buffer_coalesced_write_cycles = 0x35,
+ TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x36,
+ TA_PERF_SEL_addr_stalled_by_td_cycles = 0x37,
+ TA_PERF_SEL_data_stalled_by_tc_cycles = 0x38,
+ TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles= 0x39,
+ TA_PERF_SEL_addresser_stalled_cycles = 0x3a,
+ TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles= 0x3b,
+ TA_PERF_SEL_aniso_stalled_cycles = 0x3c,
+ TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x3d,
+ TA_PERF_SEL_deriv_stalled_cycles = 0x3e,
+ TA_PERF_SEL_aniso_gt1_cycle_quads = 0x3f,
+ TA_PERF_SEL_color_1_cycle_pixels = 0x40,
+ TA_PERF_SEL_color_2_cycle_pixels = 0x41,
+ TA_PERF_SEL_color_3_cycle_pixels = 0x42,
+ TA_PERF_SEL_color_4_cycle_pixels = 0x43,
+ TA_PERF_SEL_mip_1_cycle_pixels = 0x44,
+ TA_PERF_SEL_mip_2_cycle_pixels = 0x45,
+ TA_PERF_SEL_vol_1_cycle_pixels = 0x46,
+ TA_PERF_SEL_vol_2_cycle_pixels = 0x47,
+ TA_PERF_SEL_bilin_point_1_cycle_pixels = 0x48,
+ TA_PERF_SEL_mipmap_lod_0_samples = 0x49,
+ TA_PERF_SEL_mipmap_lod_1_samples = 0x4a,
+ TA_PERF_SEL_mipmap_lod_2_samples = 0x4b,
+ TA_PERF_SEL_mipmap_lod_3_samples = 0x4c,
+ TA_PERF_SEL_mipmap_lod_4_samples = 0x4d,
+ TA_PERF_SEL_mipmap_lod_5_samples = 0x4e,
+ TA_PERF_SEL_mipmap_lod_6_samples = 0x4f,
+ TA_PERF_SEL_mipmap_lod_7_samples = 0x50,
+ TA_PERF_SEL_mipmap_lod_8_samples = 0x51,
+ TA_PERF_SEL_mipmap_lod_9_samples = 0x52,
+ TA_PERF_SEL_mipmap_lod_10_samples = 0x53,
+ TA_PERF_SEL_mipmap_lod_11_samples = 0x54,
+ TA_PERF_SEL_mipmap_lod_12_samples = 0x55,
+ TA_PERF_SEL_mipmap_lod_13_samples = 0x56,
+ TA_PERF_SEL_mipmap_lod_14_samples = 0x57,
+ TA_PERF_SEL_mipmap_invalid_samples = 0x58,
+ TA_PERF_SEL_aniso_1_cycle_quads = 0x59,
+ TA_PERF_SEL_aniso_2_cycle_quads = 0x5a,
+ TA_PERF_SEL_aniso_4_cycle_quads = 0x5b,
+ TA_PERF_SEL_aniso_6_cycle_quads = 0x5c,
+ TA_PERF_SEL_aniso_8_cycle_quads = 0x5d,
+ TA_PERF_SEL_aniso_10_cycle_quads = 0x5e,
+ TA_PERF_SEL_aniso_12_cycle_quads = 0x5f,
+ TA_PERF_SEL_aniso_14_cycle_quads = 0x60,
+ TA_PERF_SEL_aniso_16_cycle_quads = 0x61,
+ TA_PERF_SEL_write_path_input_cycles = 0x62,
+ TA_PERF_SEL_write_path_output_cycles = 0x63,
+ TA_PERF_SEL_flat_wavefronts = 0x64,
+ TA_PERF_SEL_flat_read_wavefronts = 0x65,
+ TA_PERF_SEL_flat_write_wavefronts = 0x66,
+ TA_PERF_SEL_flat_atomic_wavefronts = 0x67,
+ TA_PERF_SEL_flat_coalesceable_wavefronts = 0x68,
+ TA_PERF_SEL_reg_sclk_vld = 0x69,
+ TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x6a,
+ TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x6b,
+ TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 0x6c,
+ TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x6d,
+ TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x6e,
+ TA_PERF_SEL_xnack_on_phase0 = 0x6f,
+ TA_PERF_SEL_xnack_on_phase1 = 0x70,
+ TA_PERF_SEL_xnack_on_phase2 = 0x71,
+ TA_PERF_SEL_xnack_on_phase3 = 0x72,
+ TA_PERF_SEL_first_xnack_on_phase0 = 0x73,
+ TA_PERF_SEL_first_xnack_on_phase1 = 0x74,
+ TA_PERF_SEL_first_xnack_on_phase2 = 0x75,
+ TA_PERF_SEL_first_xnack_on_phase3 = 0x76,
+} TA_PERFCOUNT_SEL;
+typedef enum TD_PERFCOUNT_SEL {
+ TD_PERF_SEL_none = 0x0,
+ TD_PERF_SEL_td_busy = 0x1,
+ TD_PERF_SEL_input_busy = 0x2,
+ TD_PERF_SEL_output_busy = 0x3,
+ TD_PERF_SEL_lerp_busy = 0x4,
+ TD_PERF_SEL_reg_sclk_vld = 0x5,
+ TD_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x6,
+ TD_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x7,
+ TD_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x8,
+ TD_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x9,
+ TD_PERF_SEL_tc_td_fifo_full = 0xa,
+ TD_PERF_SEL_constant_state_full = 0xb,
+ TD_PERF_SEL_sample_state_full = 0xc,
+ TD_PERF_SEL_output_fifo_full = 0xd,
+ TD_PERF_SEL_RESERVED_14 = 0xe,
+ TD_PERF_SEL_tc_stall = 0xf,
+ TD_PERF_SEL_pc_stall = 0x10,
+ TD_PERF_SEL_gds_stall = 0x11,
+ TD_PERF_SEL_RESERVED_18 = 0x12,
+ TD_PERF_SEL_RESERVED_19 = 0x13,
+ TD_PERF_SEL_gather4_wavefront = 0x14,
+ TD_PERF_SEL_sample_c_wavefront = 0x15,
+ TD_PERF_SEL_load_wavefront = 0x16,
+ TD_PERF_SEL_atomic_wavefront = 0x17,
+ TD_PERF_SEL_store_wavefront = 0x18,
+ TD_PERF_SEL_ldfptr_wavefront = 0x19,
+ TD_PERF_SEL_RESERVED_26 = 0x1a,
+ TD_PERF_SEL_RESERVED_27 = 0x1b,
+ TD_PERF_SEL_d16_en_wavefront = 0x1c,
+ TD_PERF_SEL_bicubic_filter_wavefront = 0x1d,
+ TD_PERF_SEL_bypass_filter_wavefront = 0x1e,
+ TD_PERF_SEL_min_max_filter_wavefront = 0x1f,
+ TD_PERF_SEL_coalescable_wavefront = 0x20,
+ TD_PERF_SEL_coalesced_phase = 0x21,
+ TD_PERF_SEL_four_phase_wavefront = 0x22,
+ TD_PERF_SEL_eight_phase_wavefront = 0x23,
+ TD_PERF_SEL_sixteen_phase_wavefront = 0x24,
+ TD_PERF_SEL_four_phase_forward_wavefront = 0x25,
+ TD_PERF_SEL_write_ack_wavefront = 0x26,
+ TD_PERF_SEL_RESERVED_39 = 0x27,
+ TD_PERF_SEL_user_defined_border = 0x28,
+ TD_PERF_SEL_white_border = 0x29,
+ TD_PERF_SEL_opaque_black_border = 0x2a,
+ TD_PERF_SEL_RESERVED_43 = 0x2b,
+ TD_PERF_SEL_RESERVED_44 = 0x2c,
+ TD_PERF_SEL_nack = 0x2d,
+ TD_PERF_SEL_td_sp_traffic = 0x2e,
+ TD_PERF_SEL_consume_gds_traffic = 0x2f,
+ TD_PERF_SEL_addresscmd_poison = 0x30,
+ TD_PERF_SEL_data_poison = 0x31,
+ TD_PERF_SEL_start_cycle_0 = 0x32,
+ TD_PERF_SEL_start_cycle_1 = 0x33,
+ TD_PERF_SEL_start_cycle_2 = 0x34,
+ TD_PERF_SEL_start_cycle_3 = 0x35,
+ TD_PERF_SEL_null_cycle_output = 0x36,
+} TD_PERFCOUNT_SEL;
+typedef enum TCP_PERFCOUNT_SELECT {
+ TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 0x0,
+ TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 0x1,
+ TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 0x2,
+ TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 0x3,
+ TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 0x4,
+ TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 0x5,
+ TCP_PERF_SEL_LOD_STALL_CYCLES = 0x6,
+ TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 0x7,
+ TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 0x8,
+ TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 0x9,
+ TCP_PERF_SEL_ALLOC_STALL_CYCLES = 0xa,
+ TCP_PERF_SEL_LFIFO_STALL_CYCLES = 0xb,
+ TCP_PERF_SEL_RFIFO_STALL_CYCLES = 0xc,
+ TCP_PERF_SEL_TCR_RDRET_STALL = 0xd,
+ TCP_PERF_SEL_WRITE_CONFLICT_STALL = 0xe,
+ TCP_PERF_SEL_HOLE_READ_STALL = 0xf,
+ TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 0x10,
+ TCP_PERF_SEL_PENDING_STALL_CYCLES = 0x11,
+ TCP_PERF_SEL_READFIFO_STALL_CYCLES = 0x12,
+ TCP_PERF_SEL_TCP_LATENCY = 0x13,
+ TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 0x14,
+ TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 0x15,
+ TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 0x16,
+ TCP_PERF_SEL_TCC_READ_REQ = 0x17,
+ TCP_PERF_SEL_TCC_WRITE_REQ = 0x18,
+ TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 0x19,
+ TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 0x1a,
+ TCP_PERF_SEL_TOTAL_LOCAL_READ = 0x1b,
+ TCP_PERF_SEL_TOTAL_GLOBAL_READ = 0x1c,
+ TCP_PERF_SEL_TOTAL_LOCAL_WRITE = 0x1d,
+ TCP_PERF_SEL_TOTAL_GLOBAL_WRITE = 0x1e,
+ TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 0x1f,
+ TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 0x20,
+ TCP_PERF_SEL_TOTAL_WBINVL1 = 0x21,
+ TCP_PERF_SEL_IMG_READ_FMT_1 = 0x22,
+ TCP_PERF_SEL_IMG_READ_FMT_8 = 0x23,
+ TCP_PERF_SEL_IMG_READ_FMT_16 = 0x24,
+ TCP_PERF_SEL_IMG_READ_FMT_32 = 0x25,
+ TCP_PERF_SEL_IMG_READ_FMT_32_AS_8 = 0x26,
+ TCP_PERF_SEL_IMG_READ_FMT_32_AS_16 = 0x27,
+ TCP_PERF_SEL_IMG_READ_FMT_32_AS_128 = 0x28,
+ TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE = 0x29,
+ TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE = 0x2a,
+ TCP_PERF_SEL_IMG_READ_FMT_96 = 0x2b,
+ TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE = 0x2c,
+ TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE = 0x2d,
+ TCP_PERF_SEL_IMG_READ_FMT_BC1 = 0x2e,
+ TCP_PERF_SEL_IMG_READ_FMT_BC2 = 0x2f,
+ TCP_PERF_SEL_IMG_READ_FMT_BC3 = 0x30,
+ TCP_PERF_SEL_IMG_READ_FMT_BC4 = 0x31,
+ TCP_PERF_SEL_IMG_READ_FMT_BC5 = 0x32,
+ TCP_PERF_SEL_IMG_READ_FMT_BC6 = 0x33,
+ TCP_PERF_SEL_IMG_READ_FMT_BC7 = 0x34,
+ TCP_PERF_SEL_IMG_READ_FMT_I8 = 0x35,
+ TCP_PERF_SEL_IMG_READ_FMT_I16 = 0x36,
+ TCP_PERF_SEL_IMG_READ_FMT_I32 = 0x37,
+ TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8 = 0x38,
+ TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16 = 0x39,
+ TCP_PERF_SEL_IMG_READ_FMT_D8 = 0x3a,
+ TCP_PERF_SEL_IMG_READ_FMT_D16 = 0x3b,
+ TCP_PERF_SEL_IMG_READ_FMT_D32 = 0x3c,
+ TCP_PERF_SEL_IMG_WRITE_FMT_8 = 0x3d,
+ TCP_PERF_SEL_IMG_WRITE_FMT_16 = 0x3e,
+ TCP_PERF_SEL_IMG_WRITE_FMT_32 = 0x3f,
+ TCP_PERF_SEL_IMG_WRITE_FMT_64 = 0x40,
+ TCP_PERF_SEL_IMG_WRITE_FMT_128 = 0x41,
+ TCP_PERF_SEL_IMG_WRITE_FMT_D8 = 0x42,
+ TCP_PERF_SEL_IMG_WRITE_FMT_D16 = 0x43,
+ TCP_PERF_SEL_IMG_WRITE_FMT_D32 = 0x44,
+ TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32 = 0x45,
+ TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32 = 0x46,
+ TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64 = 0x47,
+ TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64 = 0x48,
+ TCP_PERF_SEL_BUF_READ_FMT_8 = 0x49,
+ TCP_PERF_SEL_BUF_READ_FMT_16 = 0x4a,
+ TCP_PERF_SEL_BUF_READ_FMT_32 = 0x4b,
+ TCP_PERF_SEL_BUF_WRITE_FMT_8 = 0x4c,
+ TCP_PERF_SEL_BUF_WRITE_FMT_16 = 0x4d,
+ TCP_PERF_SEL_BUF_WRITE_FMT_32 = 0x4e,
+ TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32 = 0x4f,
+ TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32 = 0x50,
+ TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64 = 0x51,
+ TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64 = 0x52,
+ TCP_PERF_SEL_ARR_LINEAR_GENERAL = 0x53,
+ TCP_PERF_SEL_ARR_LINEAR_ALIGNED = 0x54,
+ TCP_PERF_SEL_ARR_1D_THIN1 = 0x55,
+ TCP_PERF_SEL_ARR_1D_THICK = 0x56,
+ TCP_PERF_SEL_ARR_2D_THIN1 = 0x57,
+ TCP_PERF_SEL_ARR_2D_THICK = 0x58,
+ TCP_PERF_SEL_ARR_2D_XTHICK = 0x59,
+ TCP_PERF_SEL_ARR_3D_THIN1 = 0x5a,
+ TCP_PERF_SEL_ARR_3D_THICK = 0x5b,
+ TCP_PERF_SEL_ARR_3D_XTHICK = 0x5c,
+ TCP_PERF_SEL_DIM_1D = 0x5d,
+ TCP_PERF_SEL_DIM_2D = 0x5e,
+ TCP_PERF_SEL_DIM_3D = 0x5f,
+ TCP_PERF_SEL_DIM_1D_ARRAY = 0x60,
+ TCP_PERF_SEL_DIM_2D_ARRAY = 0x61,
+ TCP_PERF_SEL_DIM_2D_MSAA = 0x62,
+ TCP_PERF_SEL_DIM_2D_ARRAY_MSAA = 0x63,
+ TCP_PERF_SEL_DIM_CUBE_ARRAY = 0x64,
+ TCP_PERF_SEL_CP_TCP_INVALIDATE = 0x65,
+ TCP_PERF_SEL_TA_TCP_STATE_READ = 0x66,
+ TCP_PERF_SEL_TAGRAM0_REQ = 0x67,
+ TCP_PERF_SEL_TAGRAM1_REQ = 0x68,
+ TCP_PERF_SEL_TAGRAM2_REQ = 0x69,
+ TCP_PERF_SEL_TAGRAM3_REQ = 0x6a,
+ TCP_PERF_SEL_GATE_EN1 = 0x6b,
+ TCP_PERF_SEL_GATE_EN2 = 0x6c,
+ TCP_PERF_SEL_CORE_REG_SCLK_VLD = 0x6d,
+ TCP_PERF_SEL_TCC_REQ = 0x6e,
+ TCP_PERF_SEL_TCC_NON_READ_REQ = 0x6f,
+ TCP_PERF_SEL_TCC_BYPASS_READ_REQ = 0x70,
+ TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ = 0x71,
+ TCP_PERF_SEL_TCC_VOLATILE_READ_REQ = 0x72,
+ TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ = 0x73,
+ TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ = 0x74,
+ TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ = 0x75,
+ TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ = 0x76,
+ TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ = 0x77,
+ TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ = 0x78,
+ TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ = 0x79,
+ TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ = 0x7a,
+ TCP_PERF_SEL_TCC_ATOMIC_REQ = 0x7b,
+ TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ = 0x7c,
+ TCP_PERF_SEL_TCC_DATA_BUS_BUSY = 0x7d,
+ TCP_PERF_SEL_TOTAL_ACCESSES = 0x7e,
+ TCP_PERF_SEL_TOTAL_READ = 0x7f,
+ TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 0x80,
+ TCP_PERF_SEL_TOTAL_HIT_EVICT_READ = 0x81,
+ TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 0x82,
+ TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 0x83,
+ TCP_PERF_SEL_TOTAL_NON_READ = 0x84,
+ TCP_PERF_SEL_TOTAL_WRITE = 0x85,
+ TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 0x86,
+ TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 0x87,
+ TCP_PERF_SEL_TOTAL_WBINVL1_VOL = 0x88,
+ TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 0x89,
+ TCP_PERF_SEL_DISPLAY_MICROTILING = 0x8a,
+ TCP_PERF_SEL_THIN_MICROTILING = 0x8b,
+ TCP_PERF_SEL_DEPTH_MICROTILING = 0x8c,
+ TCP_PERF_SEL_ARR_PRT_THIN1 = 0x8d,
+ TCP_PERF_SEL_ARR_PRT_2D_THIN1 = 0x8e,
+ TCP_PERF_SEL_ARR_PRT_3D_THIN1 = 0x8f,
+ TCP_PERF_SEL_ARR_PRT_THICK = 0x90,
+ TCP_PERF_SEL_ARR_PRT_2D_THICK = 0x91,
+ TCP_PERF_SEL_ARR_PRT_3D_THICK = 0x92,
+ TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL = 0x93,
+ TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL = 0x94,
+ TCP_PERF_SEL_UNALIGNED = 0x95,
+ TCP_PERF_SEL_ROTATED_MICROTILING = 0x96,
+ TCP_PERF_SEL_THICK_MICROTILING = 0x97,
+ TCP_PERF_SEL_ATC = 0x98,
+ TCP_PERF_SEL_POWER_STALL = 0x99,
+ TCP_PERF_SEL_RESERVED_154 = 0x9a,
+ TCP_PERF_SEL_TCC_LRU_REQ = 0x9b,
+ TCP_PERF_SEL_TCC_STREAM_REQ = 0x9c,
+ TCP_PERF_SEL_TCC_NC_READ_REQ = 0x9d,
+ TCP_PERF_SEL_TCC_NC_WRITE_REQ = 0x9e,
+ TCP_PERF_SEL_TCC_NC_ATOMIC_REQ = 0x9f,
+ TCP_PERF_SEL_TCC_UC_READ_REQ = 0xa0,
+ TCP_PERF_SEL_TCC_UC_WRITE_REQ = 0xa1,
+ TCP_PERF_SEL_TCC_UC_ATOMIC_REQ = 0xa2,
+ TCP_PERF_SEL_TCC_CC_READ_REQ = 0xa3,
+ TCP_PERF_SEL_TCC_CC_WRITE_REQ = 0xa4,
+ TCP_PERF_SEL_TCC_CC_ATOMIC_REQ = 0xa5,
+ TCP_PERF_SEL_TCC_DCC_REQ = 0xa6,
+ TCP_PERF_SEL_TCC_PHYSICAL_REQ = 0xa7,
+ TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 0xa8,
+ TCP_PERF_SEL_VOLATILE = 0xa9,
+ TCP_PERF_SEL_TC_TA_XNACK_STALL = 0xaa,
+ TCP_PERF_SEL_ATCL1_SERIALIZATION_STALL = 0xab,
+ TCP_PERF_SEL_SHOOTDOWN = 0xac,
+ TCP_PERF_SEL_GATCL1_TRANSLATION_MISS = 0xad,
+ TCP_PERF_SEL_GATCL1_PERMISSION_MISS = 0xae,
+ TCP_PERF_SEL_GATCL1_REQUEST = 0xaf,
+ TCP_PERF_SEL_GATCL1_STALL_INFLIGHT_MAX = 0xb0,
+ TCP_PERF_SEL_GATCL1_STALL_LRU_INFLIGHT = 0xb1,
+ TCP_PERF_SEL_GATCL1_LFIFO_FULL = 0xb2,
+ TCP_PERF_SEL_GATCL1_STALL_LFIFO_NOT_RES = 0xb3,
+ TCP_PERF_SEL_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0xb4,
+ TCP_PERF_SEL_GATCL1_ATCL2_INFLIGHT = 0xb5,
+ TCP_PERF_SEL_GATCL1_STALL_MISSFIFO_FULL = 0xb6,
+} TCP_PERFCOUNT_SELECT;
+typedef enum TCP_CACHE_POLICIES {
+ TCP_CACHE_POLICY_MISS_LRU = 0x0,
+ TCP_CACHE_POLICY_MISS_EVICT = 0x1,
+ TCP_CACHE_POLICY_HIT_LRU = 0x2,
+ TCP_CACHE_POLICY_HIT_EVICT = 0x3,
+} TCP_CACHE_POLICIES;
+typedef enum TCP_CACHE_STORE_POLICIES {
+ TCP_CACHE_STORE_POLICY_WT_LRU = 0x0,
+ TCP_CACHE_STORE_POLICY_WT_EVICT = 0x1,
+} TCP_CACHE_STORE_POLICIES;
+typedef enum TCP_WATCH_MODES {
+ TCP_WATCH_MODE_READ = 0x0,
+ TCP_WATCH_MODE_NONREAD = 0x1,
+ TCP_WATCH_MODE_ATOMIC = 0x2,
+ TCP_WATCH_MODE_ALL = 0x3,
+} TCP_WATCH_MODES;
+typedef enum TCP_DSM_DATA_SEL {
+ TCP_DSM_DISABLE = 0x0,
+ TCP_DSM_SEL0 = 0x1,
+ TCP_DSM_SEL1 = 0x2,
+ TCP_DSM_SEL_BOTH = 0x3,
+} TCP_DSM_DATA_SEL;
+typedef enum TCP_DSM_SINGLE_WRITE {
+ TCP_DSM_SINGLE_WRITE_EN = 0x1,
+} TCP_DSM_SINGLE_WRITE;
+typedef enum VGT_OUT_PRIM_TYPE {
+ VGT_OUT_POINT = 0x0,
+ VGT_OUT_LINE = 0x1,
+ VGT_OUT_TRI = 0x2,
+ VGT_OUT_RECT_V0 = 0x3,
+ VGT_OUT_RECT_V1 = 0x4,
+ VGT_OUT_RECT_V2 = 0x5,
+ VGT_OUT_RECT_V3 = 0x6,
+ VGT_OUT_RESERVED = 0x7,
+ VGT_TE_QUAD = 0x8,
+ VGT_TE_PRIM_INDEX_LINE = 0x9,
+ VGT_TE_PRIM_INDEX_TRI = 0xa,
+ VGT_TE_PRIM_INDEX_QUAD = 0xb,
+ VGT_OUT_LINE_ADJ = 0xc,
+ VGT_OUT_TRI_ADJ = 0xd,
+ VGT_OUT_PATCH = 0xe,
+} VGT_OUT_PRIM_TYPE;
+typedef enum VGT_DI_PRIM_TYPE {
+ DI_PT_NONE = 0x0,
+ DI_PT_POINTLIST = 0x1,
+ DI_PT_LINELIST = 0x2,
+ DI_PT_LINESTRIP = 0x3,
+ DI_PT_TRILIST = 0x4,
+ DI_PT_TRIFAN = 0x5,
+ DI_PT_TRISTRIP = 0x6,
+ DI_PT_UNUSED_0 = 0x7,
+ DI_PT_UNUSED_1 = 0x8,
+ DI_PT_PATCH = 0x9,
+ DI_PT_LINELIST_ADJ = 0xa,
+ DI_PT_LINESTRIP_ADJ = 0xb,
+ DI_PT_TRILIST_ADJ = 0xc,
+ DI_PT_TRISTRIP_ADJ = 0xd,
+ DI_PT_UNUSED_3 = 0xe,
+ DI_PT_UNUSED_4 = 0xf,
+ DI_PT_TRI_WITH_WFLAGS = 0x10,
+ DI_PT_RECTLIST = 0x11,
+ DI_PT_LINELOOP = 0x12,
+ DI_PT_QUADLIST = 0x13,
+ DI_PT_QUADSTRIP = 0x14,
+ DI_PT_POLYGON = 0x15,
+ DI_PT_2D_COPY_RECT_LIST_V0 = 0x16,
+ DI_PT_2D_COPY_RECT_LIST_V1 = 0x17,
+ DI_PT_2D_COPY_RECT_LIST_V2 = 0x18,
+ DI_PT_2D_COPY_RECT_LIST_V3 = 0x19,
+ DI_PT_2D_FILL_RECT_LIST = 0x1a,
+ DI_PT_2D_LINE_STRIP = 0x1b,
+ DI_PT_2D_TRI_STRIP = 0x1c,
+} VGT_DI_PRIM_TYPE;
+typedef enum VGT_DI_SOURCE_SELECT {
+ DI_SRC_SEL_DMA = 0x0,
+ DI_SRC_SEL_IMMEDIATE = 0x1,
+ DI_SRC_SEL_AUTO_INDEX = 0x2,
+ DI_SRC_SEL_RESERVED = 0x3,
+} VGT_DI_SOURCE_SELECT;
+typedef enum VGT_DI_MAJOR_MODE_SELECT {
+ DI_MAJOR_MODE_0 = 0x0,
+ DI_MAJOR_MODE_1 = 0x1,
+} VGT_DI_MAJOR_MODE_SELECT;
+typedef enum VGT_DI_INDEX_SIZE {
+ DI_INDEX_SIZE_16_BIT = 0x0,
+ DI_INDEX_SIZE_32_BIT = 0x1,
+ DI_INDEX_SIZE_8_BIT = 0x2,
+} VGT_DI_INDEX_SIZE;
+typedef enum VGT_EVENT_TYPE {
+ Reserved_0x00 = 0x0,
+ SAMPLE_STREAMOUTSTATS1 = 0x1,
+ SAMPLE_STREAMOUTSTATS2 = 0x2,
+ SAMPLE_STREAMOUTSTATS3 = 0x3,
+ CACHE_FLUSH_TS = 0x4,
+ CONTEXT_DONE = 0x5,
+ CACHE_FLUSH = 0x6,
+ CS_PARTIAL_FLUSH = 0x7,
+ VGT_STREAMOUT_SYNC = 0x8,
+ Reserved_0x09 = 0x9,
+ VGT_STREAMOUT_RESET = 0xa,
+ END_OF_PIPE_INCR_DE = 0xb,
+ END_OF_PIPE_IB_END = 0xc,
+ RST_PIX_CNT = 0xd,
+ Reserved_0x0E = 0xe,
+ VS_PARTIAL_FLUSH = 0xf,
+ PS_PARTIAL_FLUSH = 0x10,
+ FLUSH_HS_OUTPUT = 0x11,
+ FLUSH_LS_OUTPUT = 0x12,
+ Reserved_0x13 = 0x13,
+ CACHE_FLUSH_AND_INV_TS_EVENT = 0x14,
+ ZPASS_DONE = 0x15,
+ CACHE_FLUSH_AND_INV_EVENT = 0x16,
+ PERFCOUNTER_START = 0x17,
+ PERFCOUNTER_STOP = 0x18,
+ PIPELINESTAT_START = 0x19,
+ PIPELINESTAT_STOP = 0x1a,
+ PERFCOUNTER_SAMPLE = 0x1b,
+ FLUSH_ES_OUTPUT = 0x1c,
+ FLUSH_GS_OUTPUT = 0x1d,
+ SAMPLE_PIPELINESTAT = 0x1e,
+ SO_VGTSTREAMOUT_FLUSH = 0x1f,
+ SAMPLE_STREAMOUTSTATS = 0x20,
+ RESET_VTX_CNT = 0x21,
+ BLOCK_CONTEXT_DONE = 0x22,
+ CS_CONTEXT_DONE = 0x23,
+ VGT_FLUSH = 0x24,
+ TGID_ROLLOVER = 0x25,
+ SQ_NON_EVENT = 0x26,
+ SC_SEND_DB_VPZ = 0x27,
+ BOTTOM_OF_PIPE_TS = 0x28,
+ FLUSH_SX_TS = 0x29,
+ DB_CACHE_FLUSH_AND_INV = 0x2a,
+ FLUSH_AND_INV_DB_DATA_TS = 0x2b,
+ FLUSH_AND_INV_DB_META = 0x2c,
+ FLUSH_AND_INV_CB_DATA_TS = 0x2d,
+ FLUSH_AND_INV_CB_META = 0x2e,
+ CS_DONE = 0x2f,
+ PS_DONE = 0x30,
+ FLUSH_AND_INV_CB_PIXEL_DATA = 0x31,
+ SX_CB_RAT_ACK_REQUEST = 0x32,
+ THREAD_TRACE_START = 0x33,
+ THREAD_TRACE_STOP = 0x34,
+ THREAD_TRACE_MARKER = 0x35,
+ THREAD_TRACE_FLUSH = 0x36,
+ THREAD_TRACE_FINISH = 0x37,
+ PIXEL_PIPE_STAT_CONTROL = 0x38,
+ PIXEL_PIPE_STAT_DUMP = 0x39,
+ PIXEL_PIPE_STAT_RESET = 0x3a,
+ CONTEXT_SUSPEND = 0x3b,
+ OFFCHIP_HS_DEALLOC = 0x3c,
+} VGT_EVENT_TYPE;
+typedef enum VGT_DMA_SWAP_MODE {
+ VGT_DMA_SWAP_NONE = 0x0,
+ VGT_DMA_SWAP_16_BIT = 0x1,
+ VGT_DMA_SWAP_32_BIT = 0x2,
+ VGT_DMA_SWAP_WORD = 0x3,
+} VGT_DMA_SWAP_MODE;
+typedef enum VGT_INDEX_TYPE_MODE {
+ VGT_INDEX_16 = 0x0,
+ VGT_INDEX_32 = 0x1,
+ VGT_INDEX_8 = 0x2,
+} VGT_INDEX_TYPE_MODE;
+typedef enum VGT_DMA_BUF_TYPE {
+ VGT_DMA_BUF_MEM = 0x0,
+ VGT_DMA_BUF_RING = 0x1,
+ VGT_DMA_BUF_SETUP = 0x2,
+ VGT_DMA_PTR_UPDATE = 0x3,
+} VGT_DMA_BUF_TYPE;
+typedef enum VGT_OUTPATH_SELECT {
+ VGT_OUTPATH_VTX_REUSE = 0x0,
+ VGT_OUTPATH_TESS_EN = 0x1,
+ VGT_OUTPATH_PASSTHRU = 0x2,
+ VGT_OUTPATH_GS_BLOCK = 0x3,
+ VGT_OUTPATH_HS_BLOCK = 0x4,
+} VGT_OUTPATH_SELECT;
+typedef enum VGT_GRP_PRIM_TYPE {
+ VGT_GRP_3D_POINT = 0x0,
+ VGT_GRP_3D_LINE = 0x1,
+ VGT_GRP_3D_TRI = 0x2,
+ VGT_GRP_3D_RECT = 0x3,
+ VGT_GRP_3D_QUAD = 0x4,
+ VGT_GRP_2D_COPY_RECT_V0 = 0x5,
+ VGT_GRP_2D_COPY_RECT_V1 = 0x6,
+ VGT_GRP_2D_COPY_RECT_V2 = 0x7,
+ VGT_GRP_2D_COPY_RECT_V3 = 0x8,
+ VGT_GRP_2D_FILL_RECT = 0x9,
+ VGT_GRP_2D_LINE = 0xa,
+ VGT_GRP_2D_TRI = 0xb,
+ VGT_GRP_PRIM_INDEX_LINE = 0xc,
+ VGT_GRP_PRIM_INDEX_TRI = 0xd,
+ VGT_GRP_PRIM_INDEX_QUAD = 0xe,
+ VGT_GRP_3D_LINE_ADJ = 0xf,
+ VGT_GRP_3D_TRI_ADJ = 0x10,
+ VGT_GRP_3D_PATCH = 0x11,
+} VGT_GRP_PRIM_TYPE;
+typedef enum VGT_GRP_PRIM_ORDER {
+ VGT_GRP_LIST = 0x0,
+ VGT_GRP_STRIP = 0x1,
+ VGT_GRP_FAN = 0x2,
+ VGT_GRP_LOOP = 0x3,
+ VGT_GRP_POLYGON = 0x4,
+} VGT_GRP_PRIM_ORDER;
+typedef enum VGT_GROUP_CONV_SEL {
+ VGT_GRP_INDEX_16 = 0x0,
+ VGT_GRP_INDEX_32 = 0x1,
+ VGT_GRP_UINT_16 = 0x2,
+ VGT_GRP_UINT_32 = 0x3,
+ VGT_GRP_SINT_16 = 0x4,
+ VGT_GRP_SINT_32 = 0x5,
+ VGT_GRP_FLOAT_32 = 0x6,
+ VGT_GRP_AUTO_PRIM = 0x7,
+ VGT_GRP_FIX_1_23_TO_FLOAT = 0x8,
+} VGT_GROUP_CONV_SEL;
+typedef enum VGT_GS_MODE_TYPE {
+ GS_OFF = 0x0,
+ GS_SCENARIO_A = 0x1,
+ GS_SCENARIO_B = 0x2,
+ GS_SCENARIO_G = 0x3,
+ GS_SCENARIO_C = 0x4,
+ SPRITE_EN = 0x5,
+} VGT_GS_MODE_TYPE;
+typedef enum VGT_GS_CUT_MODE {
+ GS_CUT_1024 = 0x0,
+ GS_CUT_512 = 0x1,
+ GS_CUT_256 = 0x2,
+ GS_CUT_128 = 0x3,
+} VGT_GS_CUT_MODE;
+typedef enum VGT_GS_OUTPRIM_TYPE {
+ POINTLIST = 0x0,
+ LINESTRIP = 0x1,
+ TRISTRIP = 0x2,
+} VGT_GS_OUTPRIM_TYPE;
+typedef enum VGT_CACHE_INVALID_MODE {
+ VC_ONLY = 0x0,
+ TC_ONLY = 0x1,
+ VC_AND_TC = 0x2,
+} VGT_CACHE_INVALID_MODE;
+typedef enum VGT_TESS_TYPE {
+ TESS_ISOLINE = 0x0,
+ TESS_TRIANGLE = 0x1,
+ TESS_QUAD = 0x2,
+} VGT_TESS_TYPE;
+typedef enum VGT_TESS_PARTITION {
+ PART_INTEGER = 0x0,
+ PART_POW2 = 0x1,
+ PART_FRAC_ODD = 0x2,
+ PART_FRAC_EVEN = 0x3,
+} VGT_TESS_PARTITION;
+typedef enum VGT_TESS_TOPOLOGY {
+ OUTPUT_POINT = 0x0,
+ OUTPUT_LINE = 0x1,
+ OUTPUT_TRIANGLE_CW = 0x2,
+ OUTPUT_TRIANGLE_CCW = 0x3,
+} VGT_TESS_TOPOLOGY;
+typedef enum VGT_RDREQ_POLICY {
+ VGT_POLICY_LRU = 0x0,
+ VGT_POLICY_STREAM = 0x1,
+} VGT_RDREQ_POLICY;
+typedef enum VGT_DIST_MODE {
+ NO_DIST = 0x0,
+ PATCHES = 0x1,
+ DONUTS = 0x2,
+} VGT_DIST_MODE;
+typedef enum VGT_STAGES_LS_EN {
+ LS_STAGE_OFF = 0x0,
+ LS_STAGE_ON = 0x1,
+ CS_STAGE_ON = 0x2,
+ RESERVED_LS = 0x3,
+} VGT_STAGES_LS_EN;
+typedef enum VGT_STAGES_HS_EN {
+ HS_STAGE_OFF = 0x0,
+ HS_STAGE_ON = 0x1,
+} VGT_STAGES_HS_EN;
+typedef enum VGT_STAGES_ES_EN {
+ ES_STAGE_OFF = 0x0,
+ ES_STAGE_DS = 0x1,
+ ES_STAGE_REAL = 0x2,
+ RESERVED_ES = 0x3,
+} VGT_STAGES_ES_EN;
+typedef enum VGT_STAGES_GS_EN {
+ GS_STAGE_OFF = 0x0,
+ GS_STAGE_ON = 0x1,
+} VGT_STAGES_GS_EN;
+typedef enum VGT_STAGES_VS_EN {
+ VS_STAGE_REAL = 0x0,
+ VS_STAGE_DS = 0x1,
+ VS_STAGE_COPY_SHADER = 0x2,
+ RESERVED_VS = 0x3,
+} VGT_STAGES_VS_EN;
+typedef enum VGT_PERFCOUNT_SELECT {
+ vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0x0,
+ vgt_perf_VGT_SPI_ESVERT_VALID = 0x1,
+ vgt_perf_VGT_SPI_ESVERT_EOV = 0x2,
+ vgt_perf_VGT_SPI_ESVERT_STALLED = 0x3,
+ vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY = 0x4,
+ vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE = 0x5,
+ vgt_perf_VGT_SPI_ESVERT_STATIC = 0x6,
+ vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT = 0x7,
+ vgt_perf_VGT_SPI_ESTHREAD_SEND = 0x8,
+ vgt_perf_VGT_SPI_GSPRIM_VALID = 0x9,
+ vgt_perf_VGT_SPI_GSPRIM_EOV = 0xa,
+ vgt_perf_VGT_SPI_GSPRIM_CONT = 0xb,
+ vgt_perf_VGT_SPI_GSPRIM_STALLED = 0xc,
+ vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY = 0xd,
+ vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE = 0xe,
+ vgt_perf_VGT_SPI_GSPRIM_STATIC = 0xf,
+ vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 0x10,
+ vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT = 0x11,
+ vgt_perf_VGT_SPI_GSTHREAD_SEND = 0x12,
+ vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 0x13,
+ vgt_perf_VGT_SPI_VSVERT_SEND = 0x14,
+ vgt_perf_VGT_SPI_VSVERT_EOV = 0x15,
+ vgt_perf_VGT_SPI_VSVERT_STALLED = 0x16,
+ vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY = 0x17,
+ vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE = 0x18,
+ vgt_perf_VGT_SPI_VSVERT_STATIC = 0x19,
+ vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT = 0x1a,
+ vgt_perf_VGT_SPI_VSTHREAD_SEND = 0x1b,
+ vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE = 0x1c,
+ vgt_perf_VGT_PA_CLIPV_SEND = 0x1d,
+ vgt_perf_VGT_PA_CLIPV_FIRSTVERT = 0x1e,
+ vgt_perf_VGT_PA_CLIPV_STALLED = 0x1f,
+ vgt_perf_VGT_PA_CLIPV_STARVED_BUSY = 0x20,
+ vgt_perf_VGT_PA_CLIPV_STARVED_IDLE = 0x21,
+ vgt_perf_VGT_PA_CLIPV_STATIC = 0x22,
+ vgt_perf_VGT_PA_CLIPP_SEND = 0x23,
+ vgt_perf_VGT_PA_CLIPP_EOP = 0x24,
+ vgt_perf_VGT_PA_CLIPP_IS_EVENT = 0x25,
+ vgt_perf_VGT_PA_CLIPP_NULL_PRIM = 0x26,
+ vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT = 0x27,
+ vgt_perf_VGT_PA_CLIPP_STALLED = 0x28,
+ vgt_perf_VGT_PA_CLIPP_STARVED_BUSY = 0x29,
+ vgt_perf_VGT_PA_CLIPP_STARVED_IDLE = 0x2a,
+ vgt_perf_VGT_PA_CLIPP_STATIC = 0x2b,
+ vgt_perf_VGT_PA_CLIPS_SEND = 0x2c,
+ vgt_perf_VGT_PA_CLIPS_STALLED = 0x2d,
+ vgt_perf_VGT_PA_CLIPS_STARVED_BUSY = 0x2e,
+ vgt_perf_VGT_PA_CLIPS_STARVED_IDLE = 0x2f,
+ vgt_perf_VGT_PA_CLIPS_STATIC = 0x30,
+ vgt_perf_vsvert_ds_send = 0x31,
+ vgt_perf_vsvert_api_send = 0x32,
+ vgt_perf_hs_tif_stall = 0x33,
+ vgt_perf_hs_input_stall = 0x34,
+ vgt_perf_hs_interface_stall = 0x35,
+ vgt_perf_hs_tfm_stall = 0x36,
+ vgt_perf_te11_starved = 0x37,
+ vgt_perf_gs_event_stall = 0x38,
+ vgt_perf_vgt_pa_clipp_send_not_event = 0x39,
+ vgt_perf_vgt_pa_clipp_valid_prim = 0x3a,
+ vgt_perf_reused_es_indices = 0x3b,
+ vgt_perf_vs_cache_hits = 0x3c,
+ vgt_perf_gs_cache_hits = 0x3d,
+ vgt_perf_ds_cache_hits = 0x3e,
+ vgt_perf_total_cache_hits = 0x3f,
+ vgt_perf_vgt_busy = 0x40,
+ vgt_perf_vgt_gs_busy = 0x41,
+ vgt_perf_esvert_stalled_es_tbl = 0x42,
+ vgt_perf_esvert_stalled_gs_tbl = 0x43,
+ vgt_perf_esvert_stalled_gs_event = 0x44,
+ vgt_perf_esvert_stalled_gsprim = 0x45,
+ vgt_perf_gsprim_stalled_es_tbl = 0x46,
+ vgt_perf_gsprim_stalled_gs_tbl = 0x47,
+ vgt_perf_gsprim_stalled_gs_event = 0x48,
+ vgt_perf_gsprim_stalled_esvert = 0x49,
+ vgt_perf_esthread_stalled_es_rb_full = 0x4a,
+ vgt_perf_esthread_stalled_spi_bp = 0x4b,
+ vgt_perf_counters_avail_stalled = 0x4c,
+ vgt_perf_gs_rb_space_avail_stalled = 0x4d,
+ vgt_perf_gs_issue_rtr_stalled = 0x4e,
+ vgt_perf_gsthread_stalled = 0x4f,
+ vgt_perf_strmout_stalled = 0x50,
+ vgt_perf_wait_for_es_done_stalled = 0x51,
+ vgt_perf_cm_stalled_by_gog = 0x52,
+ vgt_perf_cm_reading_stalled = 0x53,
+ vgt_perf_cm_stalled_by_gsfetch_done = 0x54,
+ vgt_perf_gog_vs_tbl_stalled = 0x55,
+ vgt_perf_gog_out_indx_stalled = 0x56,
+ vgt_perf_gog_out_prim_stalled = 0x57,
+ vgt_perf_waveid_stalled = 0x58,
+ vgt_perf_gog_busy = 0x59,
+ vgt_perf_reused_vs_indices = 0x5a,
+ vgt_perf_sclk_reg_vld_event = 0x5b,
+ vgt_perf_vs_conflicting_indices = 0x5c,
+ vgt_perf_sclk_core_vld_event = 0x5d,
+ vgt_perf_hswave_stalled = 0x5e,
+ vgt_perf_sclk_gs_vld_event = 0x5f,
+ vgt_perf_VGT_SPI_LSVERT_VALID = 0x60,
+ vgt_perf_VGT_SPI_LSVERT_EOV = 0x61,
+ vgt_perf_VGT_SPI_LSVERT_STALLED = 0x62,
+ vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY = 0x63,
+ vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE = 0x64,
+ vgt_perf_VGT_SPI_LSVERT_STATIC = 0x65,
+ vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE = 0x66,
+ vgt_perf_VGT_SPI_LSWAVE_IS_EVENT = 0x67,
+ vgt_perf_VGT_SPI_LSWAVE_SEND = 0x68,
+ vgt_perf_VGT_SPI_HSVERT_VALID = 0x69,
+ vgt_perf_VGT_SPI_HSVERT_EOV = 0x6a,
+ vgt_perf_VGT_SPI_HSVERT_STALLED = 0x6b,
+ vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY = 0x6c,
+ vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE = 0x6d,
+ vgt_perf_VGT_SPI_HSVERT_STATIC = 0x6e,
+ vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE = 0x6f,
+ vgt_perf_VGT_SPI_HSWAVE_IS_EVENT = 0x70,
+ vgt_perf_VGT_SPI_HSWAVE_SEND = 0x71,
+ vgt_perf_ds_prims = 0x72,
+ vgt_perf_ls_thread_groups = 0x73,
+ vgt_perf_hs_thread_groups = 0x74,
+ vgt_perf_es_thread_groups = 0x75,
+ vgt_perf_vs_thread_groups = 0x76,
+ vgt_perf_ls_done_latency = 0x77,
+ vgt_perf_hs_done_latency = 0x78,
+ vgt_perf_es_done_latency = 0x79,
+ vgt_perf_gs_done_latency = 0x7a,
+ vgt_perf_vgt_hs_busy = 0x7b,
+ vgt_perf_vgt_te11_busy = 0x7c,
+ vgt_perf_ls_flush = 0x7d,
+ vgt_perf_hs_flush = 0x7e,
+ vgt_perf_es_flush = 0x7f,
+ vgt_perf_vgt_pa_clipp_eopg = 0x80,
+ vgt_perf_ls_done = 0x81,
+ vgt_perf_hs_done = 0x82,
+ vgt_perf_es_done = 0x83,
+ vgt_perf_gs_done = 0x84,
+ vgt_perf_vsfetch_done = 0x85,
+ vgt_perf_gs_done_received = 0x86,
+ vgt_perf_es_ring_high_water_mark = 0x87,
+ vgt_perf_gs_ring_high_water_mark = 0x88,
+ vgt_perf_vs_table_high_water_mark = 0x89,
+ vgt_perf_hs_tgs_active_high_water_mark = 0x8a,
+ vgt_perf_pa_clipp_dealloc = 0x8b,
+ vgt_perf_cut_mem_flush_stalled = 0x8c,
+ vgt_perf_vsvert_work_received = 0x8d,
+ vgt_perf_vgt_pa_clipp_starved_after_work = 0x8e,
+ vgt_perf_te11_con_starved_after_work = 0x8f,
+ vgt_perf_hs_waiting_on_ls_done_stall = 0x90,
+ vgt_spi_vsvert_valid = 0x91,
+} VGT_PERFCOUNT_SELECT;
+typedef enum IA_PERFCOUNT_SELECT {
+ ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE = 0x0,
+ ia_perf_dma_data_fifo_full = 0x1,
+ ia_perf_RESERVED1 = 0x2,
+ ia_perf_RESERVED2 = 0x3,
+ ia_perf_RESERVED3 = 0x4,
+ ia_perf_RESERVED4 = 0x5,
+ ia_perf_RESERVED5 = 0x6,
+ ia_perf_MC_LAT_BIN_0 = 0x7,
+ ia_perf_MC_LAT_BIN_1 = 0x8,
+ ia_perf_MC_LAT_BIN_2 = 0x9,
+ ia_perf_MC_LAT_BIN_3 = 0xa,
+ ia_perf_MC_LAT_BIN_4 = 0xb,
+ ia_perf_MC_LAT_BIN_5 = 0xc,
+ ia_perf_MC_LAT_BIN_6 = 0xd,
+ ia_perf_MC_LAT_BIN_7 = 0xe,
+ ia_perf_ia_busy = 0xf,
+ ia_perf_ia_sclk_reg_vld_event = 0x10,
+ ia_perf_RESERVED6 = 0x11,
+ ia_perf_ia_sclk_core_vld_event = 0x12,
+ ia_perf_RESERVED7 = 0x13,
+ ia_perf_ia_dma_return = 0x14,
+ ia_perf_ia_stalled = 0x15,
+ ia_perf_shift_starved_pipe0_event = 0x16,
+ ia_perf_shift_starved_pipe1_event = 0x17,
+} IA_PERFCOUNT_SELECT;
+typedef enum WD_PERFCOUNT_SELECT {
+ wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 0x0,
+ wd_perf_RBIU_DR_FIFO_STARVED = 0x1,
+ wd_perf_RBIU_DR_FIFO_STALLED = 0x2,
+ wd_perf_RBIU_DI_FIFO_STARVED = 0x3,
+ wd_perf_RBIU_DI_FIFO_STALLED = 0x4,
+ wd_perf_wd_busy = 0x5,
+ wd_perf_wd_sclk_reg_vld_event = 0x6,
+ wd_perf_wd_sclk_input_vld_event = 0x7,
+ wd_perf_wd_sclk_core_vld_event = 0x8,
+ wd_perf_wd_stalled = 0x9,
+ wd_perf_inside_tf_bin_0 = 0xa,
+ wd_perf_inside_tf_bin_1 = 0xb,
+ wd_perf_inside_tf_bin_2 = 0xc,
+ wd_perf_inside_tf_bin_3 = 0xd,
+ wd_perf_inside_tf_bin_4 = 0xe,
+ wd_perf_inside_tf_bin_5 = 0xf,
+ wd_perf_inside_tf_bin_6 = 0x10,
+ wd_perf_inside_tf_bin_7 = 0x11,
+ wd_perf_inside_tf_bin_8 = 0x12,
+ wd_perf_tfreq_lat_bin_0 = 0x13,
+ wd_perf_tfreq_lat_bin_1 = 0x14,
+ wd_perf_tfreq_lat_bin_2 = 0x15,
+ wd_perf_tfreq_lat_bin_3 = 0x16,
+ wd_perf_tfreq_lat_bin_4 = 0x17,
+ wd_perf_tfreq_lat_bin_5 = 0x18,
+ wd_perf_tfreq_lat_bin_6 = 0x19,
+ wd_perf_tfreq_lat_bin_7 = 0x1a,
+ wd_starved_on_hs_done = 0x1b,
+ wd_perf_se0_hs_done_latency = 0x1c,
+ wd_perf_se1_hs_done_latency = 0x1d,
+ wd_perf_se2_hs_done_latency = 0x1e,
+ wd_perf_se3_hs_done_latency = 0x1f,
+ wd_perf_hs_done_se0 = 0x20,
+ wd_perf_hs_done_se1 = 0x21,
+ wd_perf_hs_done_se2 = 0x22,
+ wd_perf_hs_done_se3 = 0x23,
+ wd_perf_null_patches = 0x24,
+} WD_PERFCOUNT_SELECT;
+typedef enum WD_IA_DRAW_TYPE {
+ WD_IA_DRAW_TYPE_DI_MM0 = 0x0,
+ WD_IA_DRAW_TYPE_DI_MM1 = 0x1,
+ WD_IA_DRAW_TYPE_EVENT_INIT = 0x2,
+ WD_IA_DRAW_TYPE_EVENT_ADDR = 0x3,
+ WD_IA_DRAW_TYPE_MIN_INDX = 0x4,
+ WD_IA_DRAW_TYPE_MAX_INDX = 0x5,
+ WD_IA_DRAW_TYPE_INDX_OFF = 0x6,
+ WD_IA_DRAW_TYPE_IMM_DATA = 0x7,
+} WD_IA_DRAW_TYPE;
+typedef enum WD_IA_DRAW_SOURCE {
+ WD_IA_DRAW_SOURCE_DMA = 0x0,
+ WD_IA_DRAW_SOURCE_IMMD = 0x1,
+ WD_IA_DRAW_SOURCE_AUTO = 0x2,
+ WD_IA_DRAW_SOURCE_OPAQ = 0x3,
+} WD_IA_DRAW_SOURCE;
+#define GSTHREADID_SIZE 0x2
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0x0,
+ ENDIAN_8IN16 = 0x1,
+ ENDIAN_8IN32 = 0x2,
+ ENDIAN_8IN64 = 0x3,
+} SurfaceEndian;
+typedef enum ArrayMode {
+ ARRAY_LINEAR_GENERAL = 0x0,
+ ARRAY_LINEAR_ALIGNED = 0x1,
+ ARRAY_1D_TILED_THIN1 = 0x2,
+ ARRAY_1D_TILED_THICK = 0x3,
+ ARRAY_2D_TILED_THIN1 = 0x4,
+ ARRAY_PRT_TILED_THIN1 = 0x5,
+ ARRAY_PRT_2D_TILED_THIN1 = 0x6,
+ ARRAY_2D_TILED_THICK = 0x7,
+ ARRAY_2D_TILED_XTHICK = 0x8,
+ ARRAY_PRT_TILED_THICK = 0x9,
+ ARRAY_PRT_2D_TILED_THICK = 0xa,
+ ARRAY_PRT_3D_TILED_THIN1 = 0xb,
+ ARRAY_3D_TILED_THIN1 = 0xc,
+ ARRAY_3D_TILED_THICK = 0xd,
+ ARRAY_3D_TILED_XTHICK = 0xe,
+ ARRAY_PRT_3D_TILED_THICK = 0xf,
+} ArrayMode;
+typedef enum PipeTiling {
+ CONFIG_1_PIPE = 0x0,
+ CONFIG_2_PIPE = 0x1,
+ CONFIG_4_PIPE = 0x2,
+ CONFIG_8_PIPE = 0x3,
+} PipeTiling;
+typedef enum BankTiling {
+ CONFIG_4_BANK = 0x0,
+ CONFIG_8_BANK = 0x1,
+} BankTiling;
+typedef enum GroupInterleave {
+ CONFIG_256B_GROUP = 0x0,
+ CONFIG_512B_GROUP = 0x1,
+} GroupInterleave;
+typedef enum RowTiling {
+ CONFIG_1KB_ROW = 0x0,
+ CONFIG_2KB_ROW = 0x1,
+ CONFIG_4KB_ROW = 0x2,
+ CONFIG_8KB_ROW = 0x3,
+ CONFIG_1KB_ROW_OPT = 0x4,
+ CONFIG_2KB_ROW_OPT = 0x5,
+ CONFIG_4KB_ROW_OPT = 0x6,
+ CONFIG_8KB_ROW_OPT = 0x7,
+} RowTiling;
+typedef enum BankSwapBytes {
+ CONFIG_128B_SWAPS = 0x0,
+ CONFIG_256B_SWAPS = 0x1,
+ CONFIG_512B_SWAPS = 0x2,
+ CONFIG_1KB_SWAPS = 0x3,
+} BankSwapBytes;
+typedef enum SampleSplitBytes {
+ CONFIG_1KB_SPLIT = 0x0,
+ CONFIG_2KB_SPLIT = 0x1,
+ CONFIG_4KB_SPLIT = 0x2,
+ CONFIG_8KB_SPLIT = 0x3,
+} SampleSplitBytes;
+typedef enum NumPipes {
+ ADDR_CONFIG_1_PIPE = 0x0,
+ ADDR_CONFIG_2_PIPE = 0x1,
+ ADDR_CONFIG_4_PIPE = 0x2,
+ ADDR_CONFIG_8_PIPE = 0x3,
+} NumPipes;
+typedef enum PipeInterleaveSize {
+ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
+ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
+} PipeInterleaveSize;
+typedef enum BankInterleaveSize {
+ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
+ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
+ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
+ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
+} BankInterleaveSize;
+typedef enum NumShaderEngines {
+ ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
+ ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
+} NumShaderEngines;
+typedef enum ShaderEngineTileSize {
+ ADDR_CONFIG_SE_TILE_16 = 0x0,
+ ADDR_CONFIG_SE_TILE_32 = 0x1,
+} ShaderEngineTileSize;
+typedef enum NumGPUs {
+ ADDR_CONFIG_1_GPU = 0x0,
+ ADDR_CONFIG_2_GPU = 0x1,
+ ADDR_CONFIG_4_GPU = 0x2,
+} NumGPUs;
+typedef enum MultiGPUTileSize {
+ ADDR_CONFIG_GPU_TILE_16 = 0x0,
+ ADDR_CONFIG_GPU_TILE_32 = 0x1,
+ ADDR_CONFIG_GPU_TILE_64 = 0x2,
+ ADDR_CONFIG_GPU_TILE_128 = 0x3,
+} MultiGPUTileSize;
+typedef enum RowSize {
+ ADDR_CONFIG_1KB_ROW = 0x0,
+ ADDR_CONFIG_2KB_ROW = 0x1,
+ ADDR_CONFIG_4KB_ROW = 0x2,
+} RowSize;
+typedef enum NumLowerPipes {
+ ADDR_CONFIG_1_LOWER_PIPES = 0x0,
+ ADDR_CONFIG_2_LOWER_PIPES = 0x1,
+} NumLowerPipes;
+typedef enum DebugBlockId {
+ DBG_CLIENT_BLKID_RESERVED = 0x0,
+ DBG_CLIENT_BLKID_dbg = 0x1,
+ DBG_CLIENT_BLKID_scf2 = 0x2,
+ DBG_CLIENT_BLKID_mcd5 = 0x3,
+ DBG_CLIENT_BLKID_vmc = 0x4,
+ DBG_CLIENT_BLKID_sx30 = 0x5,
+ DBG_CLIENT_BLKID_mcd2 = 0x6,
+ DBG_CLIENT_BLKID_bci1 = 0x7,
+ DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8,
+ DBG_CLIENT_BLKID_mcc0 = 0x9,
+ DBG_CLIENT_BLKID_uvdf_0 = 0xa,
+ DBG_CLIENT_BLKID_uvdf_1 = 0xb,
+ DBG_CLIENT_BLKID_uvdf_2 = 0xc,
+ DBG_CLIENT_BLKID_uvdi_0 = 0xd,
+ DBG_CLIENT_BLKID_bci0 = 0xe,
+ DBG_CLIENT_BLKID_vcec0_0 = 0xf,
+ DBG_CLIENT_BLKID_cb100 = 0x10,
+ DBG_CLIENT_BLKID_cb001 = 0x11,
+ DBG_CLIENT_BLKID_mcd4 = 0x12,
+ DBG_CLIENT_BLKID_tmonw00 = 0x13,
+ DBG_CLIENT_BLKID_cb101 = 0x14,
+ DBG_CLIENT_BLKID_sx10 = 0x15,
+ DBG_CLIENT_BLKID_cb301 = 0x16,
+ DBG_CLIENT_BLKID_tmonw01 = 0x17,
+ DBG_CLIENT_BLKID_vcea0_0 = 0x18,
+ DBG_CLIENT_BLKID_vcea0_1 = 0x19,
+ DBG_CLIENT_BLKID_vcea0_2 = 0x1a,
+ DBG_CLIENT_BLKID_vcea0_3 = 0x1b,
+ DBG_CLIENT_BLKID_scf1 = 0x1c,
+ DBG_CLIENT_BLKID_sx20 = 0x1d,
+ DBG_CLIENT_BLKID_spim1 = 0x1e,
+ DBG_CLIENT_BLKID_pa10 = 0x1f,
+ DBG_CLIENT_BLKID_pa00 = 0x20,
+ DBG_CLIENT_BLKID_gmcon = 0x21,
+ DBG_CLIENT_BLKID_mcb = 0x22,
+ DBG_CLIENT_BLKID_vgt0 = 0x23,
+ DBG_CLIENT_BLKID_pc0 = 0x24,
+ DBG_CLIENT_BLKID_bci2 = 0x25,
+ DBG_CLIENT_BLKID_uvdb_0 = 0x26,
+ DBG_CLIENT_BLKID_spim3 = 0x27,
+ DBG_CLIENT_BLKID_cpc_0 = 0x28,
+ DBG_CLIENT_BLKID_cpc_1 = 0x29,
+ DBG_CLIENT_BLKID_uvdm_0 = 0x2a,
+ DBG_CLIENT_BLKID_uvdm_1 = 0x2b,
+ DBG_CLIENT_BLKID_uvdm_2 = 0x2c,
+ DBG_CLIENT_BLKID_uvdm_3 = 0x2d,
+ DBG_CLIENT_BLKID_cb000 = 0x2e,
+ DBG_CLIENT_BLKID_spim0 = 0x2f,
+ DBG_CLIENT_BLKID_mcc2 = 0x30,
+ DBG_CLIENT_BLKID_ds0 = 0x31,
+ DBG_CLIENT_BLKID_srbm = 0x32,
+ DBG_CLIENT_BLKID_ih = 0x33,
+ DBG_CLIENT_BLKID_sem = 0x34,
+ DBG_CLIENT_BLKID_sdma_0 = 0x35,
+ DBG_CLIENT_BLKID_sdma_1 = 0x36,
+ DBG_CLIENT_BLKID_hdp = 0x37,
+ DBG_CLIENT_BLKID_acp_0 = 0x38,
+ DBG_CLIENT_BLKID_acp_1 = 0x39,
+ DBG_CLIENT_BLKID_cb200 = 0x3a,
+ DBG_CLIENT_BLKID_scf3 = 0x3b,
+ DBG_CLIENT_BLKID_vceb1_0 = 0x3c,
+ DBG_CLIENT_BLKID_vcea1_0 = 0x3d,
+ DBG_CLIENT_BLKID_vcea1_1 = 0x3e,
+ DBG_CLIENT_BLKID_vcea1_2 = 0x3f,
+ DBG_CLIENT_BLKID_vcea1_3 = 0x40,
+ DBG_CLIENT_BLKID_bci3 = 0x41,
+ DBG_CLIENT_BLKID_mcd0 = 0x42,
+ DBG_CLIENT_BLKID_pa11 = 0x43,
+ DBG_CLIENT_BLKID_pa01 = 0x44,
+ DBG_CLIENT_BLKID_cb201 = 0x45,
+ DBG_CLIENT_BLKID_spim2 = 0x46,
+ DBG_CLIENT_BLKID_vgt2 = 0x47,
+ DBG_CLIENT_BLKID_pc2 = 0x48,
+ DBG_CLIENT_BLKID_smu_0 = 0x49,
+ DBG_CLIENT_BLKID_smu_1 = 0x4a,
+ DBG_CLIENT_BLKID_smu_2 = 0x4b,
+ DBG_CLIENT_BLKID_cb1 = 0x4c,
+ DBG_CLIENT_BLKID_ia0 = 0x4d,
+ DBG_CLIENT_BLKID_wd = 0x4e,
+ DBG_CLIENT_BLKID_ia1 = 0x4f,
+ DBG_CLIENT_BLKID_vcec1_0 = 0x50,
+ DBG_CLIENT_BLKID_scf0 = 0x51,
+ DBG_CLIENT_BLKID_vgt1 = 0x52,
+ DBG_CLIENT_BLKID_pc1 = 0x53,
+ DBG_CLIENT_BLKID_cb0 = 0x54,
+ DBG_CLIENT_BLKID_gdc_one_0 = 0x55,
+ DBG_CLIENT_BLKID_gdc_one_1 = 0x56,
+ DBG_CLIENT_BLKID_gdc_one_2 = 0x57,
+ DBG_CLIENT_BLKID_gdc_one_3 = 0x58,
+ DBG_CLIENT_BLKID_gdc_one_4 = 0x59,
+ DBG_CLIENT_BLKID_gdc_one_5 = 0x5a,
+ DBG_CLIENT_BLKID_gdc_one_6 = 0x5b,
+ DBG_CLIENT_BLKID_gdc_one_7 = 0x5c,
+ DBG_CLIENT_BLKID_gdc_one_8 = 0x5d,
+ DBG_CLIENT_BLKID_gdc_one_9 = 0x5e,
+ DBG_CLIENT_BLKID_gdc_one_10 = 0x5f,
+ DBG_CLIENT_BLKID_gdc_one_11 = 0x60,
+ DBG_CLIENT_BLKID_gdc_one_12 = 0x61,
+ DBG_CLIENT_BLKID_gdc_one_13 = 0x62,
+ DBG_CLIENT_BLKID_gdc_one_14 = 0x63,
+ DBG_CLIENT_BLKID_gdc_one_15 = 0x64,
+ DBG_CLIENT_BLKID_gdc_one_16 = 0x65,
+ DBG_CLIENT_BLKID_gdc_one_17 = 0x66,
+ DBG_CLIENT_BLKID_gdc_one_18 = 0x67,
+ DBG_CLIENT_BLKID_gdc_one_19 = 0x68,
+ DBG_CLIENT_BLKID_gdc_one_20 = 0x69,
+ DBG_CLIENT_BLKID_gdc_one_21 = 0x6a,
+ DBG_CLIENT_BLKID_gdc_one_22 = 0x6b,
+ DBG_CLIENT_BLKID_gdc_one_23 = 0x6c,
+ DBG_CLIENT_BLKID_gdc_one_24 = 0x6d,
+ DBG_CLIENT_BLKID_gdc_one_25 = 0x6e,
+ DBG_CLIENT_BLKID_gdc_one_26 = 0x6f,
+ DBG_CLIENT_BLKID_gdc_one_27 = 0x70,
+ DBG_CLIENT_BLKID_gdc_one_28 = 0x71,
+ DBG_CLIENT_BLKID_gdc_one_29 = 0x72,
+ DBG_CLIENT_BLKID_gdc_one_30 = 0x73,
+ DBG_CLIENT_BLKID_gdc_one_31 = 0x74,
+ DBG_CLIENT_BLKID_gdc_one_32 = 0x75,
+ DBG_CLIENT_BLKID_gdc_one_33 = 0x76,
+ DBG_CLIENT_BLKID_gdc_one_34 = 0x77,
+ DBG_CLIENT_BLKID_gdc_one_35 = 0x78,
+ DBG_CLIENT_BLKID_vceb0_0 = 0x79,
+ DBG_CLIENT_BLKID_vgt3 = 0x7a,
+ DBG_CLIENT_BLKID_pc3 = 0x7b,
+ DBG_CLIENT_BLKID_mcd3 = 0x7c,
+ DBG_CLIENT_BLKID_uvdu_0 = 0x7d,
+ DBG_CLIENT_BLKID_uvdu_1 = 0x7e,
+ DBG_CLIENT_BLKID_uvdu_2 = 0x7f,
+ DBG_CLIENT_BLKID_uvdu_3 = 0x80,
+ DBG_CLIENT_BLKID_uvdu_4 = 0x81,
+ DBG_CLIENT_BLKID_uvdu_5 = 0x82,
+ DBG_CLIENT_BLKID_uvdu_6 = 0x83,
+ DBG_CLIENT_BLKID_cb300 = 0x84,
+ DBG_CLIENT_BLKID_mcd1 = 0x85,
+ DBG_CLIENT_BLKID_sx00 = 0x86,
+ DBG_CLIENT_BLKID_uvdc_0 = 0x87,
+ DBG_CLIENT_BLKID_uvdc_1 = 0x88,
+ DBG_CLIENT_BLKID_mcc3 = 0x89,
+ DBG_CLIENT_BLKID_cpg_0 = 0x8a,
+ DBG_CLIENT_BLKID_cpg_1 = 0x8b,
+ DBG_CLIENT_BLKID_gck = 0x8c,
+ DBG_CLIENT_BLKID_mcc1 = 0x8d,
+ DBG_CLIENT_BLKID_cpf_0 = 0x8e,
+ DBG_CLIENT_BLKID_cpf_1 = 0x8f,
+ DBG_CLIENT_BLKID_rlc = 0x90,
+ DBG_CLIENT_BLKID_grbm = 0x91,
+ DBG_CLIENT_BLKID_sammsp = 0x92,
+ DBG_CLIENT_BLKID_dci_pg = 0x93,
+ DBG_CLIENT_BLKID_dci_0 = 0x94,
+ DBG_CLIENT_BLKID_dccg0_0 = 0x95,
+ DBG_CLIENT_BLKID_dccg0_1 = 0x96,
+ DBG_CLIENT_BLKID_dcfe01_0 = 0x97,
+ DBG_CLIENT_BLKID_dcfe02_0 = 0x98,
+ DBG_CLIENT_BLKID_dcfe03_0 = 0x99,
+ DBG_CLIENT_BLKID_dcfe04_0 = 0x9a,
+ DBG_CLIENT_BLKID_dcfe05_0 = 0x9b,
+ DBG_CLIENT_BLKID_dcfe06_0 = 0x9c,
+ DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d,
+} DebugBlockId;
+typedef enum DebugBlockId_OLD {
+ DBG_BLOCK_ID_RESERVED = 0x0,
+ DBG_BLOCK_ID_DBG = 0x1,
+ DBG_BLOCK_ID_VMC = 0x2,
+ DBG_BLOCK_ID_PDMA = 0x3,
+ DBG_BLOCK_ID_CG = 0x4,
+ DBG_BLOCK_ID_SRBM = 0x5,
+ DBG_BLOCK_ID_GRBM = 0x6,
+ DBG_BLOCK_ID_RLC = 0x7,
+ DBG_BLOCK_ID_CSC = 0x8,
+ DBG_BLOCK_ID_SEM = 0x9,
+ DBG_BLOCK_ID_IH = 0xa,
+ DBG_BLOCK_ID_SC = 0xb,
+ DBG_BLOCK_ID_SQ = 0xc,
+ DBG_BLOCK_ID_AVP = 0xd,
+ DBG_BLOCK_ID_GMCON = 0xe,
+ DBG_BLOCK_ID_SMU = 0xf,
+ DBG_BLOCK_ID_DMA0 = 0x10,
+ DBG_BLOCK_ID_DMA1 = 0x11,
+ DBG_BLOCK_ID_SPIM = 0x12,
+ DBG_BLOCK_ID_GDS = 0x13,
+ DBG_BLOCK_ID_SPIS = 0x14,
+ DBG_BLOCK_ID_UNUSED0 = 0x15,
+ DBG_BLOCK_ID_PA0 = 0x16,
+ DBG_BLOCK_ID_PA1 = 0x17,
+ DBG_BLOCK_ID_CP0 = 0x18,
+ DBG_BLOCK_ID_CP1 = 0x19,
+ DBG_BLOCK_ID_CP2 = 0x1a,
+ DBG_BLOCK_ID_UNUSED1 = 0x1b,
+ DBG_BLOCK_ID_UVDU = 0x1c,
+ DBG_BLOCK_ID_UVDM = 0x1d,
+ DBG_BLOCK_ID_VCE = 0x1e,
+ DBG_BLOCK_ID_UNUSED2 = 0x1f,
+ DBG_BLOCK_ID_VGT0 = 0x20,
+ DBG_BLOCK_ID_VGT1 = 0x21,
+ DBG_BLOCK_ID_IA = 0x22,
+ DBG_BLOCK_ID_UNUSED3 = 0x23,
+ DBG_BLOCK_ID_SCT0 = 0x24,
+ DBG_BLOCK_ID_SCT1 = 0x25,
+ DBG_BLOCK_ID_SPM0 = 0x26,
+ DBG_BLOCK_ID_SPM1 = 0x27,
+ DBG_BLOCK_ID_TCAA = 0x28,
+ DBG_BLOCK_ID_TCAB = 0x29,
+ DBG_BLOCK_ID_TCCA = 0x2a,
+ DBG_BLOCK_ID_TCCB = 0x2b,
+ DBG_BLOCK_ID_MCC0 = 0x2c,
+ DBG_BLOCK_ID_MCC1 = 0x2d,
+ DBG_BLOCK_ID_MCC2 = 0x2e,
+ DBG_BLOCK_ID_MCC3 = 0x2f,
+ DBG_BLOCK_ID_SX0 = 0x30,
+ DBG_BLOCK_ID_SX1 = 0x31,
+ DBG_BLOCK_ID_SX2 = 0x32,
+ DBG_BLOCK_ID_SX3 = 0x33,
+ DBG_BLOCK_ID_UNUSED4 = 0x34,
+ DBG_BLOCK_ID_UNUSED5 = 0x35,
+ DBG_BLOCK_ID_UNUSED6 = 0x36,
+ DBG_BLOCK_ID_UNUSED7 = 0x37,
+ DBG_BLOCK_ID_PC0 = 0x38,
+ DBG_BLOCK_ID_PC1 = 0x39,
+ DBG_BLOCK_ID_UNUSED8 = 0x3a,
+ DBG_BLOCK_ID_UNUSED9 = 0x3b,
+ DBG_BLOCK_ID_UNUSED10 = 0x3c,
+ DBG_BLOCK_ID_UNUSED11 = 0x3d,
+ DBG_BLOCK_ID_MCB = 0x3e,
+ DBG_BLOCK_ID_UNUSED12 = 0x3f,
+ DBG_BLOCK_ID_SCB0 = 0x40,
+ DBG_BLOCK_ID_SCB1 = 0x41,
+ DBG_BLOCK_ID_UNUSED13 = 0x42,
+ DBG_BLOCK_ID_UNUSED14 = 0x43,
+ DBG_BLOCK_ID_SCF0 = 0x44,
+ DBG_BLOCK_ID_SCF1 = 0x45,
+ DBG_BLOCK_ID_UNUSED15 = 0x46,
+ DBG_BLOCK_ID_UNUSED16 = 0x47,
+ DBG_BLOCK_ID_BCI0 = 0x48,
+ DBG_BLOCK_ID_BCI1 = 0x49,
+ DBG_BLOCK_ID_BCI2 = 0x4a,
+ DBG_BLOCK_ID_BCI3 = 0x4b,
+ DBG_BLOCK_ID_UNUSED17 = 0x4c,
+ DBG_BLOCK_ID_UNUSED18 = 0x4d,
+ DBG_BLOCK_ID_UNUSED19 = 0x4e,
+ DBG_BLOCK_ID_UNUSED20 = 0x4f,
+ DBG_BLOCK_ID_CB00 = 0x50,
+ DBG_BLOCK_ID_CB01 = 0x51,
+ DBG_BLOCK_ID_CB02 = 0x52,
+ DBG_BLOCK_ID_CB03 = 0x53,
+ DBG_BLOCK_ID_CB04 = 0x54,
+ DBG_BLOCK_ID_UNUSED21 = 0x55,
+ DBG_BLOCK_ID_UNUSED22 = 0x56,
+ DBG_BLOCK_ID_UNUSED23 = 0x57,
+ DBG_BLOCK_ID_CB10 = 0x58,
+ DBG_BLOCK_ID_CB11 = 0x59,
+ DBG_BLOCK_ID_CB12 = 0x5a,
+ DBG_BLOCK_ID_CB13 = 0x5b,
+ DBG_BLOCK_ID_CB14 = 0x5c,
+ DBG_BLOCK_ID_UNUSED24 = 0x5d,
+ DBG_BLOCK_ID_UNUSED25 = 0x5e,
+ DBG_BLOCK_ID_UNUSED26 = 0x5f,
+ DBG_BLOCK_ID_TCP0 = 0x60,
+ DBG_BLOCK_ID_TCP1 = 0x61,
+ DBG_BLOCK_ID_TCP2 = 0x62,
+ DBG_BLOCK_ID_TCP3 = 0x63,
+ DBG_BLOCK_ID_TCP4 = 0x64,
+ DBG_BLOCK_ID_TCP5 = 0x65,
+ DBG_BLOCK_ID_TCP6 = 0x66,
+ DBG_BLOCK_ID_TCP7 = 0x67,
+ DBG_BLOCK_ID_TCP8 = 0x68,
+ DBG_BLOCK_ID_TCP9 = 0x69,
+ DBG_BLOCK_ID_TCP10 = 0x6a,
+ DBG_BLOCK_ID_TCP11 = 0x6b,
+ DBG_BLOCK_ID_TCP12 = 0x6c,
+ DBG_BLOCK_ID_TCP13 = 0x6d,
+ DBG_BLOCK_ID_TCP14 = 0x6e,
+ DBG_BLOCK_ID_TCP15 = 0x6f,
+ DBG_BLOCK_ID_TCP16 = 0x70,
+ DBG_BLOCK_ID_TCP17 = 0x71,
+ DBG_BLOCK_ID_TCP18 = 0x72,
+ DBG_BLOCK_ID_TCP19 = 0x73,
+ DBG_BLOCK_ID_TCP20 = 0x74,
+ DBG_BLOCK_ID_TCP21 = 0x75,
+ DBG_BLOCK_ID_TCP22 = 0x76,
+ DBG_BLOCK_ID_TCP23 = 0x77,
+ DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
+ DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
+ DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
+ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
+ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
+ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
+ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
+ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
+ DBG_BLOCK_ID_DB00 = 0x80,
+ DBG_BLOCK_ID_DB01 = 0x81,
+ DBG_BLOCK_ID_DB02 = 0x82,
+ DBG_BLOCK_ID_DB03 = 0x83,
+ DBG_BLOCK_ID_DB04 = 0x84,
+ DBG_BLOCK_ID_UNUSED27 = 0x85,
+ DBG_BLOCK_ID_UNUSED28 = 0x86,
+ DBG_BLOCK_ID_UNUSED29 = 0x87,
+ DBG_BLOCK_ID_DB10 = 0x88,
+ DBG_BLOCK_ID_DB11 = 0x89,
+ DBG_BLOCK_ID_DB12 = 0x8a,
+ DBG_BLOCK_ID_DB13 = 0x8b,
+ DBG_BLOCK_ID_DB14 = 0x8c,
+ DBG_BLOCK_ID_UNUSED30 = 0x8d,
+ DBG_BLOCK_ID_UNUSED31 = 0x8e,
+ DBG_BLOCK_ID_UNUSED32 = 0x8f,
+ DBG_BLOCK_ID_TCC0 = 0x90,
+ DBG_BLOCK_ID_TCC1 = 0x91,
+ DBG_BLOCK_ID_TCC2 = 0x92,
+ DBG_BLOCK_ID_TCC3 = 0x93,
+ DBG_BLOCK_ID_TCC4 = 0x94,
+ DBG_BLOCK_ID_TCC5 = 0x95,
+ DBG_BLOCK_ID_TCC6 = 0x96,
+ DBG_BLOCK_ID_TCC7 = 0x97,
+ DBG_BLOCK_ID_SPS00 = 0x98,
+ DBG_BLOCK_ID_SPS01 = 0x99,
+ DBG_BLOCK_ID_SPS02 = 0x9a,
+ DBG_BLOCK_ID_SPS10 = 0x9b,
+ DBG_BLOCK_ID_SPS11 = 0x9c,
+ DBG_BLOCK_ID_SPS12 = 0x9d,
+ DBG_BLOCK_ID_UNUSED33 = 0x9e,
+ DBG_BLOCK_ID_UNUSED34 = 0x9f,
+ DBG_BLOCK_ID_TA00 = 0xa0,
+ DBG_BLOCK_ID_TA01 = 0xa1,
+ DBG_BLOCK_ID_TA02 = 0xa2,
+ DBG_BLOCK_ID_TA03 = 0xa3,
+ DBG_BLOCK_ID_TA04 = 0xa4,
+ DBG_BLOCK_ID_TA05 = 0xa5,
+ DBG_BLOCK_ID_TA06 = 0xa6,
+ DBG_BLOCK_ID_TA07 = 0xa7,
+ DBG_BLOCK_ID_TA08 = 0xa8,
+ DBG_BLOCK_ID_TA09 = 0xa9,
+ DBG_BLOCK_ID_TA0A = 0xaa,
+ DBG_BLOCK_ID_TA0B = 0xab,
+ DBG_BLOCK_ID_UNUSED35 = 0xac,
+ DBG_BLOCK_ID_UNUSED36 = 0xad,
+ DBG_BLOCK_ID_UNUSED37 = 0xae,
+ DBG_BLOCK_ID_UNUSED38 = 0xaf,
+ DBG_BLOCK_ID_TA10 = 0xb0,
+ DBG_BLOCK_ID_TA11 = 0xb1,
+ DBG_BLOCK_ID_TA12 = 0xb2,
+ DBG_BLOCK_ID_TA13 = 0xb3,
+ DBG_BLOCK_ID_TA14 = 0xb4,
+ DBG_BLOCK_ID_TA15 = 0xb5,
+ DBG_BLOCK_ID_TA16 = 0xb6,
+ DBG_BLOCK_ID_TA17 = 0xb7,
+ DBG_BLOCK_ID_TA18 = 0xb8,
+ DBG_BLOCK_ID_TA19 = 0xb9,
+ DBG_BLOCK_ID_TA1A = 0xba,
+ DBG_BLOCK_ID_TA1B = 0xbb,
+ DBG_BLOCK_ID_UNUSED39 = 0xbc,
+ DBG_BLOCK_ID_UNUSED40 = 0xbd,
+ DBG_BLOCK_ID_UNUSED41 = 0xbe,
+ DBG_BLOCK_ID_UNUSED42 = 0xbf,
+ DBG_BLOCK_ID_TD00 = 0xc0,
+ DBG_BLOCK_ID_TD01 = 0xc1,
+ DBG_BLOCK_ID_TD02 = 0xc2,
+ DBG_BLOCK_ID_TD03 = 0xc3,
+ DBG_BLOCK_ID_TD04 = 0xc4,
+ DBG_BLOCK_ID_TD05 = 0xc5,
+ DBG_BLOCK_ID_TD06 = 0xc6,
+ DBG_BLOCK_ID_TD07 = 0xc7,
+ DBG_BLOCK_ID_TD08 = 0xc8,
+ DBG_BLOCK_ID_TD09 = 0xc9,
+ DBG_BLOCK_ID_TD0A = 0xca,
+ DBG_BLOCK_ID_TD0B = 0xcb,
+ DBG_BLOCK_ID_UNUSED43 = 0xcc,
+ DBG_BLOCK_ID_UNUSED44 = 0xcd,
+ DBG_BLOCK_ID_UNUSED45 = 0xce,
+ DBG_BLOCK_ID_UNUSED46 = 0xcf,
+ DBG_BLOCK_ID_TD10 = 0xd0,
+ DBG_BLOCK_ID_TD11 = 0xd1,
+ DBG_BLOCK_ID_TD12 = 0xd2,
+ DBG_BLOCK_ID_TD13 = 0xd3,
+ DBG_BLOCK_ID_TD14 = 0xd4,
+ DBG_BLOCK_ID_TD15 = 0xd5,
+ DBG_BLOCK_ID_TD16 = 0xd6,
+ DBG_BLOCK_ID_TD17 = 0xd7,
+ DBG_BLOCK_ID_TD18 = 0xd8,
+ DBG_BLOCK_ID_TD19 = 0xd9,
+ DBG_BLOCK_ID_TD1A = 0xda,
+ DBG_BLOCK_ID_TD1B = 0xdb,
+ DBG_BLOCK_ID_UNUSED47 = 0xdc,
+ DBG_BLOCK_ID_UNUSED48 = 0xdd,
+ DBG_BLOCK_ID_UNUSED49 = 0xde,
+ DBG_BLOCK_ID_UNUSED50 = 0xdf,
+ DBG_BLOCK_ID_MCD0 = 0xe0,
+ DBG_BLOCK_ID_MCD1 = 0xe1,
+ DBG_BLOCK_ID_MCD2 = 0xe2,
+ DBG_BLOCK_ID_MCD3 = 0xe3,
+ DBG_BLOCK_ID_MCD4 = 0xe4,
+ DBG_BLOCK_ID_MCD5 = 0xe5,
+ DBG_BLOCK_ID_UNUSED51 = 0xe6,
+ DBG_BLOCK_ID_UNUSED52 = 0xe7,
+} DebugBlockId_OLD;
+typedef enum DebugBlockId_BY2 {
+ DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
+ DBG_BLOCK_ID_VMC_BY2 = 0x1,
+ DBG_BLOCK_ID_CG_BY2 = 0x2,
+ DBG_BLOCK_ID_GRBM_BY2 = 0x3,
+ DBG_BLOCK_ID_CSC_BY2 = 0x4,
+ DBG_BLOCK_ID_IH_BY2 = 0x5,
+ DBG_BLOCK_ID_SQ_BY2 = 0x6,
+ DBG_BLOCK_ID_GMCON_BY2 = 0x7,
+ DBG_BLOCK_ID_DMA0_BY2 = 0x8,
+ DBG_BLOCK_ID_SPIM_BY2 = 0x9,
+ DBG_BLOCK_ID_SPIS_BY2 = 0xa,
+ DBG_BLOCK_ID_PA0_BY2 = 0xb,
+ DBG_BLOCK_ID_CP0_BY2 = 0xc,
+ DBG_BLOCK_ID_CP2_BY2 = 0xd,
+ DBG_BLOCK_ID_UVDU_BY2 = 0xe,
+ DBG_BLOCK_ID_VCE_BY2 = 0xf,
+ DBG_BLOCK_ID_VGT0_BY2 = 0x10,
+ DBG_BLOCK_ID_IA_BY2 = 0x11,
+ DBG_BLOCK_ID_SCT0_BY2 = 0x12,
+ DBG_BLOCK_ID_SPM0_BY2 = 0x13,
+ DBG_BLOCK_ID_TCAA_BY2 = 0x14,
+ DBG_BLOCK_ID_TCCA_BY2 = 0x15,
+ DBG_BLOCK_ID_MCC0_BY2 = 0x16,
+ DBG_BLOCK_ID_MCC2_BY2 = 0x17,
+ DBG_BLOCK_ID_SX0_BY2 = 0x18,
+ DBG_BLOCK_ID_SX2_BY2 = 0x19,
+ DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
+ DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
+ DBG_BLOCK_ID_PC0_BY2 = 0x1c,
+ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
+ DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
+ DBG_BLOCK_ID_MCB_BY2 = 0x1f,
+ DBG_BLOCK_ID_SCB0_BY2 = 0x20,
+ DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
+ DBG_BLOCK_ID_SCF0_BY2 = 0x22,
+ DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
+ DBG_BLOCK_ID_BCI0_BY2 = 0x24,
+ DBG_BLOCK_ID_BCI2_BY2 = 0x25,
+ DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
+ DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
+ DBG_BLOCK_ID_CB00_BY2 = 0x28,
+ DBG_BLOCK_ID_CB02_BY2 = 0x29,
+ DBG_BLOCK_ID_CB04_BY2 = 0x2a,
+ DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
+ DBG_BLOCK_ID_CB10_BY2 = 0x2c,
+ DBG_BLOCK_ID_CB12_BY2 = 0x2d,
+ DBG_BLOCK_ID_CB14_BY2 = 0x2e,
+ DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
+ DBG_BLOCK_ID_TCP0_BY2 = 0x30,
+ DBG_BLOCK_ID_TCP2_BY2 = 0x31,
+ DBG_BLOCK_ID_TCP4_BY2 = 0x32,
+ DBG_BLOCK_ID_TCP6_BY2 = 0x33,
+ DBG_BLOCK_ID_TCP8_BY2 = 0x34,
+ DBG_BLOCK_ID_TCP10_BY2 = 0x35,
+ DBG_BLOCK_ID_TCP12_BY2 = 0x36,
+ DBG_BLOCK_ID_TCP14_BY2 = 0x37,
+ DBG_BLOCK_ID_TCP16_BY2 = 0x38,
+ DBG_BLOCK_ID_TCP18_BY2 = 0x39,
+ DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
+ DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
+ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
+ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
+ DBG_BLOCK_ID_DB00_BY2 = 0x40,
+ DBG_BLOCK_ID_DB02_BY2 = 0x41,
+ DBG_BLOCK_ID_DB04_BY2 = 0x42,
+ DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
+ DBG_BLOCK_ID_DB10_BY2 = 0x44,
+ DBG_BLOCK_ID_DB12_BY2 = 0x45,
+ DBG_BLOCK_ID_DB14_BY2 = 0x46,
+ DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
+ DBG_BLOCK_ID_TCC0_BY2 = 0x48,
+ DBG_BLOCK_ID_TCC2_BY2 = 0x49,
+ DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
+ DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
+ DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
+ DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
+ DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
+ DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
+ DBG_BLOCK_ID_TA00_BY2 = 0x50,
+ DBG_BLOCK_ID_TA02_BY2 = 0x51,
+ DBG_BLOCK_ID_TA04_BY2 = 0x52,
+ DBG_BLOCK_ID_TA06_BY2 = 0x53,
+ DBG_BLOCK_ID_TA08_BY2 = 0x54,
+ DBG_BLOCK_ID_TA0A_BY2 = 0x55,
+ DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
+ DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
+ DBG_BLOCK_ID_TA10_BY2 = 0x58,
+ DBG_BLOCK_ID_TA12_BY2 = 0x59,
+ DBG_BLOCK_ID_TA14_BY2 = 0x5a,
+ DBG_BLOCK_ID_TA16_BY2 = 0x5b,
+ DBG_BLOCK_ID_TA18_BY2 = 0x5c,
+ DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
+ DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
+ DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
+ DBG_BLOCK_ID_TD00_BY2 = 0x60,
+ DBG_BLOCK_ID_TD02_BY2 = 0x61,
+ DBG_BLOCK_ID_TD04_BY2 = 0x62,
+ DBG_BLOCK_ID_TD06_BY2 = 0x63,
+ DBG_BLOCK_ID_TD08_BY2 = 0x64,
+ DBG_BLOCK_ID_TD0A_BY2 = 0x65,
+ DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
+ DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
+ DBG_BLOCK_ID_TD10_BY2 = 0x68,
+ DBG_BLOCK_ID_TD12_BY2 = 0x69,
+ DBG_BLOCK_ID_TD14_BY2 = 0x6a,
+ DBG_BLOCK_ID_TD16_BY2 = 0x6b,
+ DBG_BLOCK_ID_TD18_BY2 = 0x6c,
+ DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
+ DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
+ DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
+ DBG_BLOCK_ID_MCD0_BY2 = 0x70,
+ DBG_BLOCK_ID_MCD2_BY2 = 0x71,
+ DBG_BLOCK_ID_MCD4_BY2 = 0x72,
+ DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
+} DebugBlockId_BY2;
+typedef enum DebugBlockId_BY4 {
+ DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
+ DBG_BLOCK_ID_CG_BY4 = 0x1,
+ DBG_BLOCK_ID_CSC_BY4 = 0x2,
+ DBG_BLOCK_ID_SQ_BY4 = 0x3,
+ DBG_BLOCK_ID_DMA0_BY4 = 0x4,
+ DBG_BLOCK_ID_SPIS_BY4 = 0x5,
+ DBG_BLOCK_ID_CP0_BY4 = 0x6,
+ DBG_BLOCK_ID_UVDU_BY4 = 0x7,
+ DBG_BLOCK_ID_VGT0_BY4 = 0x8,
+ DBG_BLOCK_ID_SCT0_BY4 = 0x9,
+ DBG_BLOCK_ID_TCAA_BY4 = 0xa,
+ DBG_BLOCK_ID_MCC0_BY4 = 0xb,
+ DBG_BLOCK_ID_SX0_BY4 = 0xc,
+ DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
+ DBG_BLOCK_ID_PC0_BY4 = 0xe,
+ DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
+ DBG_BLOCK_ID_SCB0_BY4 = 0x10,
+ DBG_BLOCK_ID_SCF0_BY4 = 0x11,
+ DBG_BLOCK_ID_BCI0_BY4 = 0x12,
+ DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
+ DBG_BLOCK_ID_CB00_BY4 = 0x14,
+ DBG_BLOCK_ID_CB04_BY4 = 0x15,
+ DBG_BLOCK_ID_CB10_BY4 = 0x16,
+ DBG_BLOCK_ID_CB14_BY4 = 0x17,
+ DBG_BLOCK_ID_TCP0_BY4 = 0x18,
+ DBG_BLOCK_ID_TCP4_BY4 = 0x19,
+ DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
+ DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
+ DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
+ DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
+ DBG_BLOCK_ID_DB_BY4 = 0x20,
+ DBG_BLOCK_ID_DB04_BY4 = 0x21,
+ DBG_BLOCK_ID_DB10_BY4 = 0x22,
+ DBG_BLOCK_ID_DB14_BY4 = 0x23,
+ DBG_BLOCK_ID_TCC0_BY4 = 0x24,
+ DBG_BLOCK_ID_TCC4_BY4 = 0x25,
+ DBG_BLOCK_ID_SPS00_BY4 = 0x26,
+ DBG_BLOCK_ID_SPS11_BY4 = 0x27,
+ DBG_BLOCK_ID_TA00_BY4 = 0x28,
+ DBG_BLOCK_ID_TA04_BY4 = 0x29,
+ DBG_BLOCK_ID_TA08_BY4 = 0x2a,
+ DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
+ DBG_BLOCK_ID_TA10_BY4 = 0x2c,
+ DBG_BLOCK_ID_TA14_BY4 = 0x2d,
+ DBG_BLOCK_ID_TA18_BY4 = 0x2e,
+ DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
+ DBG_BLOCK_ID_TD00_BY4 = 0x30,
+ DBG_BLOCK_ID_TD04_BY4 = 0x31,
+ DBG_BLOCK_ID_TD08_BY4 = 0x32,
+ DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
+ DBG_BLOCK_ID_TD10_BY4 = 0x34,
+ DBG_BLOCK_ID_TD14_BY4 = 0x35,
+ DBG_BLOCK_ID_TD18_BY4 = 0x36,
+ DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
+ DBG_BLOCK_ID_MCD0_BY4 = 0x38,
+ DBG_BLOCK_ID_MCD4_BY4 = 0x39,
+} DebugBlockId_BY4;
+typedef enum DebugBlockId_BY8 {
+ DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
+ DBG_BLOCK_ID_CSC_BY8 = 0x1,
+ DBG_BLOCK_ID_DMA0_BY8 = 0x2,
+ DBG_BLOCK_ID_CP0_BY8 = 0x3,
+ DBG_BLOCK_ID_VGT0_BY8 = 0x4,
+ DBG_BLOCK_ID_TCAA_BY8 = 0x5,
+ DBG_BLOCK_ID_SX0_BY8 = 0x6,
+ DBG_BLOCK_ID_PC0_BY8 = 0x7,
+ DBG_BLOCK_ID_SCB0_BY8 = 0x8,
+ DBG_BLOCK_ID_BCI0_BY8 = 0x9,
+ DBG_BLOCK_ID_CB00_BY8 = 0xa,
+ DBG_BLOCK_ID_CB10_BY8 = 0xb,
+ DBG_BLOCK_ID_TCP0_BY8 = 0xc,
+ DBG_BLOCK_ID_TCP8_BY8 = 0xd,
+ DBG_BLOCK_ID_TCP16_BY8 = 0xe,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
+ DBG_BLOCK_ID_DB00_BY8 = 0x10,
+ DBG_BLOCK_ID_DB10_BY8 = 0x11,
+ DBG_BLOCK_ID_TCC0_BY8 = 0x12,
+ DBG_BLOCK_ID_SPS00_BY8 = 0x13,
+ DBG_BLOCK_ID_TA00_BY8 = 0x14,
+ DBG_BLOCK_ID_TA08_BY8 = 0x15,
+ DBG_BLOCK_ID_TA10_BY8 = 0x16,
+ DBG_BLOCK_ID_TA18_BY8 = 0x17,
+ DBG_BLOCK_ID_TD00_BY8 = 0x18,
+ DBG_BLOCK_ID_TD08_BY8 = 0x19,
+ DBG_BLOCK_ID_TD10_BY8 = 0x1a,
+ DBG_BLOCK_ID_TD18_BY8 = 0x1b,
+ DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
+} DebugBlockId_BY8;
+typedef enum DebugBlockId_BY16 {
+ DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
+ DBG_BLOCK_ID_DMA0_BY16 = 0x1,
+ DBG_BLOCK_ID_VGT0_BY16 = 0x2,
+ DBG_BLOCK_ID_SX0_BY16 = 0x3,
+ DBG_BLOCK_ID_SCB0_BY16 = 0x4,
+ DBG_BLOCK_ID_CB00_BY16 = 0x5,
+ DBG_BLOCK_ID_TCP0_BY16 = 0x6,
+ DBG_BLOCK_ID_TCP16_BY16 = 0x7,
+ DBG_BLOCK_ID_DB00_BY16 = 0x8,
+ DBG_BLOCK_ID_TCC0_BY16 = 0x9,
+ DBG_BLOCK_ID_TA00_BY16 = 0xa,
+ DBG_BLOCK_ID_TA10_BY16 = 0xb,
+ DBG_BLOCK_ID_TD00_BY16 = 0xc,
+ DBG_BLOCK_ID_TD10_BY16 = 0xd,
+ DBG_BLOCK_ID_MCD0_BY16 = 0xe,
+} DebugBlockId_BY16;
+typedef enum ColorTransform {
+ DCC_CT_AUTO = 0x0,
+ DCC_CT_NONE = 0x1,
+ ABGR_TO_A_BG_G_RB = 0x2,
+ BGRA_TO_BG_G_RB_A = 0x3,
+} ColorTransform;
+typedef enum CompareRef {
+ REF_NEVER = 0x0,
+ REF_LESS = 0x1,
+ REF_EQUAL = 0x2,
+ REF_LEQUAL = 0x3,
+ REF_GREATER = 0x4,
+ REF_NOTEQUAL = 0x5,
+ REF_GEQUAL = 0x6,
+ REF_ALWAYS = 0x7,
+} CompareRef;
+typedef enum ReadSize {
+ READ_256_BITS = 0x0,
+ READ_512_BITS = 0x1,
+} ReadSize;
+typedef enum DepthFormat {
+ DEPTH_INVALID = 0x0,
+ DEPTH_16 = 0x1,
+ DEPTH_X8_24 = 0x2,
+ DEPTH_8_24 = 0x3,
+ DEPTH_X8_24_FLOAT = 0x4,
+ DEPTH_8_24_FLOAT = 0x5,
+ DEPTH_32_FLOAT = 0x6,
+ DEPTH_X24_8_32_FLOAT = 0x7,
+} DepthFormat;
+typedef enum ZFormat {
+ Z_INVALID = 0x0,
+ Z_16 = 0x1,
+ Z_24 = 0x2,
+ Z_32_FLOAT = 0x3,
+} ZFormat;
+typedef enum StencilFormat {
+ STENCIL_INVALID = 0x0,
+ STENCIL_8 = 0x1,
+} StencilFormat;
+typedef enum CmaskMode {
+ CMASK_CLEAR_NONE = 0x0,
+ CMASK_CLEAR_ONE = 0x1,
+ CMASK_CLEAR_ALL = 0x2,
+ CMASK_ANY_EXPANDED = 0x3,
+ CMASK_ALPHA0_FRAG1 = 0x4,
+ CMASK_ALPHA0_FRAG2 = 0x5,
+ CMASK_ALPHA0_FRAG4 = 0x6,
+ CMASK_ALPHA0_FRAGS = 0x7,
+ CMASK_ALPHA1_FRAG1 = 0x8,
+ CMASK_ALPHA1_FRAG2 = 0x9,
+ CMASK_ALPHA1_FRAG4 = 0xa,
+ CMASK_ALPHA1_FRAGS = 0xb,
+ CMASK_ALPHAX_FRAG1 = 0xc,
+ CMASK_ALPHAX_FRAG2 = 0xd,
+ CMASK_ALPHAX_FRAG4 = 0xe,
+ CMASK_ALPHAX_FRAGS = 0xf,
+} CmaskMode;
+typedef enum QuadExportFormat {
+ EXPORT_UNUSED = 0x0,
+ EXPORT_32_R = 0x1,
+ EXPORT_32_GR = 0x2,
+ EXPORT_32_AR = 0x3,
+ EXPORT_FP16_ABGR = 0x4,
+ EXPORT_UNSIGNED16_ABGR = 0x5,
+ EXPORT_SIGNED16_ABGR = 0x6,
+ EXPORT_32_ABGR = 0x7,
+} QuadExportFormat;
+typedef enum QuadExportFormatOld {
+ EXPORT_4P_32BPC_ABGR = 0x0,
+ EXPORT_4P_16BPC_ABGR = 0x1,
+ EXPORT_4P_32BPC_GR = 0x2,
+ EXPORT_4P_32BPC_AR = 0x3,
+ EXPORT_2P_32BPC_ABGR = 0x4,
+ EXPORT_8P_32BPC_R = 0x5,
+} QuadExportFormatOld;
+typedef enum ColorFormat {
+ COLOR_INVALID = 0x0,
+ COLOR_8 = 0x1,
+ COLOR_16 = 0x2,
+ COLOR_8_8 = 0x3,
+ COLOR_32 = 0x4,
+ COLOR_16_16 = 0x5,
+ COLOR_10_11_11 = 0x6,
+ COLOR_11_11_10 = 0x7,
+ COLOR_10_10_10_2 = 0x8,
+ COLOR_2_10_10_10 = 0x9,
+ COLOR_8_8_8_8 = 0xa,
+ COLOR_32_32 = 0xb,
+ COLOR_16_16_16_16 = 0xc,
+ COLOR_RESERVED_13 = 0xd,
+ COLOR_32_32_32_32 = 0xe,
+ COLOR_RESERVED_15 = 0xf,
+ COLOR_5_6_5 = 0x10,
+ COLOR_1_5_5_5 = 0x11,
+ COLOR_5_5_5_1 = 0x12,
+ COLOR_4_4_4_4 = 0x13,
+ COLOR_8_24 = 0x14,
+ COLOR_24_8 = 0x15,
+ COLOR_X24_8_32_FLOAT = 0x16,
+ COLOR_RESERVED_23 = 0x17,
+} ColorFormat;
+typedef enum SurfaceFormat {
+ FMT_INVALID = 0x0,
+ FMT_8 = 0x1,
+ FMT_16 = 0x2,
+ FMT_8_8 = 0x3,
+ FMT_32 = 0x4,
+ FMT_16_16 = 0x5,
+ FMT_10_11_11 = 0x6,
+ FMT_11_11_10 = 0x7,
+ FMT_10_10_10_2 = 0x8,
+ FMT_2_10_10_10 = 0x9,
+ FMT_8_8_8_8 = 0xa,
+ FMT_32_32 = 0xb,
+ FMT_16_16_16_16 = 0xc,
+ FMT_32_32_32 = 0xd,
+ FMT_32_32_32_32 = 0xe,
+ FMT_RESERVED_4 = 0xf,
+ FMT_5_6_5 = 0x10,
+ FMT_1_5_5_5 = 0x11,
+ FMT_5_5_5_1 = 0x12,
+ FMT_4_4_4_4 = 0x13,
+ FMT_8_24 = 0x14,
+ FMT_24_8 = 0x15,
+ FMT_X24_8_32_FLOAT = 0x16,
+ FMT_RESERVED_33 = 0x17,
+ FMT_11_11_10_FLOAT = 0x18,
+ FMT_16_FLOAT = 0x19,
+ FMT_32_FLOAT = 0x1a,
+ FMT_16_16_FLOAT = 0x1b,
+ FMT_8_24_FLOAT = 0x1c,
+ FMT_24_8_FLOAT = 0x1d,
+ FMT_32_32_FLOAT = 0x1e,
+ FMT_10_11_11_FLOAT = 0x1f,
+ FMT_16_16_16_16_FLOAT = 0x20,
+ FMT_3_3_2 = 0x21,
+ FMT_6_5_5 = 0x22,
+ FMT_32_32_32_32_FLOAT = 0x23,
+ FMT_RESERVED_36 = 0x24,
+ FMT_1 = 0x25,
+ FMT_1_REVERSED = 0x26,
+ FMT_GB_GR = 0x27,
+ FMT_BG_RG = 0x28,
+ FMT_32_AS_8 = 0x29,
+ FMT_32_AS_8_8 = 0x2a,
+ FMT_5_9_9_9_SHAREDEXP = 0x2b,
+ FMT_8_8_8 = 0x2c,
+ FMT_16_16_16 = 0x2d,
+ FMT_16_16_16_FLOAT = 0x2e,
+ FMT_4_4 = 0x2f,
+ FMT_32_32_32_FLOAT = 0x30,
+ FMT_BC1 = 0x31,
+ FMT_BC2 = 0x32,
+ FMT_BC3 = 0x33,
+ FMT_BC4 = 0x34,
+ FMT_BC5 = 0x35,
+ FMT_BC6 = 0x36,
+ FMT_BC7 = 0x37,
+ FMT_32_AS_32_32_32_32 = 0x38,
+ FMT_APC3 = 0x39,
+ FMT_APC4 = 0x3a,
+ FMT_APC5 = 0x3b,
+ FMT_APC6 = 0x3c,
+ FMT_APC7 = 0x3d,
+ FMT_CTX1 = 0x3e,
+ FMT_RESERVED_63 = 0x3f,
+} SurfaceFormat;
+typedef enum BUF_DATA_FORMAT {
+ BUF_DATA_FORMAT_INVALID = 0x0,
+ BUF_DATA_FORMAT_8 = 0x1,
+ BUF_DATA_FORMAT_16 = 0x2,
+ BUF_DATA_FORMAT_8_8 = 0x3,
+ BUF_DATA_FORMAT_32 = 0x4,
+ BUF_DATA_FORMAT_16_16 = 0x5,
+ BUF_DATA_FORMAT_10_11_11 = 0x6,
+ BUF_DATA_FORMAT_11_11_10 = 0x7,
+ BUF_DATA_FORMAT_10_10_10_2 = 0x8,
+ BUF_DATA_FORMAT_2_10_10_10 = 0x9,
+ BUF_DATA_FORMAT_8_8_8_8 = 0xa,
+ BUF_DATA_FORMAT_32_32 = 0xb,
+ BUF_DATA_FORMAT_16_16_16_16 = 0xc,
+ BUF_DATA_FORMAT_32_32_32 = 0xd,
+ BUF_DATA_FORMAT_32_32_32_32 = 0xe,
+ BUF_DATA_FORMAT_RESERVED_15 = 0xf,
+} BUF_DATA_FORMAT;
+typedef enum IMG_DATA_FORMAT {
+ IMG_DATA_FORMAT_INVALID = 0x0,
+ IMG_DATA_FORMAT_8 = 0x1,
+ IMG_DATA_FORMAT_16 = 0x2,
+ IMG_DATA_FORMAT_8_8 = 0x3,
+ IMG_DATA_FORMAT_32 = 0x4,
+ IMG_DATA_FORMAT_16_16 = 0x5,
+ IMG_DATA_FORMAT_10_11_11 = 0x6,
+ IMG_DATA_FORMAT_11_11_10 = 0x7,
+ IMG_DATA_FORMAT_10_10_10_2 = 0x8,
+ IMG_DATA_FORMAT_2_10_10_10 = 0x9,
+ IMG_DATA_FORMAT_8_8_8_8 = 0xa,
+ IMG_DATA_FORMAT_32_32 = 0xb,
+ IMG_DATA_FORMAT_16_16_16_16 = 0xc,
+ IMG_DATA_FORMAT_32_32_32 = 0xd,
+ IMG_DATA_FORMAT_32_32_32_32 = 0xe,
+ IMG_DATA_FORMAT_RESERVED_15 = 0xf,
+ IMG_DATA_FORMAT_5_6_5 = 0x10,
+ IMG_DATA_FORMAT_1_5_5_5 = 0x11,
+ IMG_DATA_FORMAT_5_5_5_1 = 0x12,
+ IMG_DATA_FORMAT_4_4_4_4 = 0x13,
+ IMG_DATA_FORMAT_8_24 = 0x14,
+ IMG_DATA_FORMAT_24_8 = 0x15,
+ IMG_DATA_FORMAT_X24_8_32 = 0x16,
+ IMG_DATA_FORMAT_RESERVED_23 = 0x17,
+ IMG_DATA_FORMAT_RESERVED_24 = 0x18,
+ IMG_DATA_FORMAT_RESERVED_25 = 0x19,
+ IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
+ IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
+ IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
+ IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
+ IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
+ IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
+ IMG_DATA_FORMAT_GB_GR = 0x20,
+ IMG_DATA_FORMAT_BG_RG = 0x21,
+ IMG_DATA_FORMAT_5_9_9_9 = 0x22,
+ IMG_DATA_FORMAT_BC1 = 0x23,
+ IMG_DATA_FORMAT_BC2 = 0x24,
+ IMG_DATA_FORMAT_BC3 = 0x25,
+ IMG_DATA_FORMAT_BC4 = 0x26,
+ IMG_DATA_FORMAT_BC5 = 0x27,
+ IMG_DATA_FORMAT_BC6 = 0x28,
+ IMG_DATA_FORMAT_BC7 = 0x29,
+ IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
+ IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
+ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
+ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
+ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
+ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
+ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
+ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
+ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
+ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
+ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
+ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
+ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
+ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
+ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
+ IMG_DATA_FORMAT_4_4 = 0x39,
+ IMG_DATA_FORMAT_6_5_5 = 0x3a,
+ IMG_DATA_FORMAT_1 = 0x3b,
+ IMG_DATA_FORMAT_1_REVERSED = 0x3c,
+ IMG_DATA_FORMAT_32_AS_8 = 0x3d,
+ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
+ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
+} IMG_DATA_FORMAT;
+typedef enum BUF_NUM_FORMAT {
+ BUF_NUM_FORMAT_UNORM = 0x0,
+ BUF_NUM_FORMAT_SNORM = 0x1,
+ BUF_NUM_FORMAT_USCALED = 0x2,
+ BUF_NUM_FORMAT_SSCALED = 0x3,
+ BUF_NUM_FORMAT_UINT = 0x4,
+ BUF_NUM_FORMAT_SINT = 0x5,
+ BUF_NUM_FORMAT_RESERVED_6 = 0x6,
+ BUF_NUM_FORMAT_FLOAT = 0x7,
+} BUF_NUM_FORMAT;
+typedef enum IMG_NUM_FORMAT {
+ IMG_NUM_FORMAT_UNORM = 0x0,
+ IMG_NUM_FORMAT_SNORM = 0x1,
+ IMG_NUM_FORMAT_USCALED = 0x2,
+ IMG_NUM_FORMAT_SSCALED = 0x3,
+ IMG_NUM_FORMAT_UINT = 0x4,
+ IMG_NUM_FORMAT_SINT = 0x5,
+ IMG_NUM_FORMAT_RESERVED_6 = 0x6,
+ IMG_NUM_FORMAT_FLOAT = 0x7,
+ IMG_NUM_FORMAT_RESERVED_8 = 0x8,
+ IMG_NUM_FORMAT_SRGB = 0x9,
+ IMG_NUM_FORMAT_RESERVED_10 = 0xa,
+ IMG_NUM_FORMAT_RESERVED_11 = 0xb,
+ IMG_NUM_FORMAT_RESERVED_12 = 0xc,
+ IMG_NUM_FORMAT_RESERVED_13 = 0xd,
+ IMG_NUM_FORMAT_RESERVED_14 = 0xe,
+ IMG_NUM_FORMAT_RESERVED_15 = 0xf,
+} IMG_NUM_FORMAT;
+typedef enum TileType {
+ ARRAY_COLOR_TILE = 0x0,
+ ARRAY_DEPTH_TILE = 0x1,
+} TileType;
+typedef enum NonDispTilingOrder {
+ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
+ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
+} NonDispTilingOrder;
+typedef enum MicroTileMode {
+ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
+ ADDR_SURF_THIN_MICRO_TILING = 0x1,
+ ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
+ ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
+ ADDR_SURF_THICK_MICRO_TILING = 0x4,
+} MicroTileMode;
+typedef enum TileSplit {
+ ADDR_SURF_TILE_SPLIT_64B = 0x0,
+ ADDR_SURF_TILE_SPLIT_128B = 0x1,
+ ADDR_SURF_TILE_SPLIT_256B = 0x2,
+ ADDR_SURF_TILE_SPLIT_512B = 0x3,
+ ADDR_SURF_TILE_SPLIT_1KB = 0x4,
+ ADDR_SURF_TILE_SPLIT_2KB = 0x5,
+ ADDR_SURF_TILE_SPLIT_4KB = 0x6,
+} TileSplit;
+typedef enum SampleSplit {
+ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
+ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
+ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
+ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
+} SampleSplit;
+typedef enum PipeConfig {
+ ADDR_SURF_P2 = 0x0,
+ ADDR_SURF_P2_RESERVED0 = 0x1,
+ ADDR_SURF_P2_RESERVED1 = 0x2,
+ ADDR_SURF_P2_RESERVED2 = 0x3,
+ ADDR_SURF_P4_8x16 = 0x4,
+ ADDR_SURF_P4_16x16 = 0x5,
+ ADDR_SURF_P4_16x32 = 0x6,
+ ADDR_SURF_P4_32x32 = 0x7,
+ ADDR_SURF_P8_16x16_8x16 = 0x8,
+ ADDR_SURF_P8_16x32_8x16 = 0x9,
+ ADDR_SURF_P8_32x32_8x16 = 0xa,
+ ADDR_SURF_P8_16x32_16x16 = 0xb,
+ ADDR_SURF_P8_32x32_16x16 = 0xc,
+ ADDR_SURF_P8_32x32_16x32 = 0xd,
+ ADDR_SURF_P8_32x64_32x32 = 0xe,
+ ADDR_SURF_P8_RESERVED0 = 0xf,
+ ADDR_SURF_P16_32x32_8x16 = 0x10,
+ ADDR_SURF_P16_32x32_16x16 = 0x11,
+} PipeConfig;
+typedef enum NumBanks {
+ ADDR_SURF_2_BANK = 0x0,
+ ADDR_SURF_4_BANK = 0x1,
+ ADDR_SURF_8_BANK = 0x2,
+ ADDR_SURF_16_BANK = 0x3,
+} NumBanks;
+typedef enum BankWidth {
+ ADDR_SURF_BANK_WIDTH_1 = 0x0,
+ ADDR_SURF_BANK_WIDTH_2 = 0x1,
+ ADDR_SURF_BANK_WIDTH_4 = 0x2,
+ ADDR_SURF_BANK_WIDTH_8 = 0x3,
+} BankWidth;
+typedef enum BankHeight {
+ ADDR_SURF_BANK_HEIGHT_1 = 0x0,
+ ADDR_SURF_BANK_HEIGHT_2 = 0x1,
+ ADDR_SURF_BANK_HEIGHT_4 = 0x2,
+ ADDR_SURF_BANK_HEIGHT_8 = 0x3,
+} BankHeight;
+typedef enum BankWidthHeight {
+ ADDR_SURF_BANK_WH_1 = 0x0,
+ ADDR_SURF_BANK_WH_2 = 0x1,
+ ADDR_SURF_BANK_WH_4 = 0x2,
+ ADDR_SURF_BANK_WH_8 = 0x3,
+} BankWidthHeight;
+typedef enum MacroTileAspect {
+ ADDR_SURF_MACRO_ASPECT_1 = 0x0,
+ ADDR_SURF_MACRO_ASPECT_2 = 0x1,
+ ADDR_SURF_MACRO_ASPECT_4 = 0x2,
+ ADDR_SURF_MACRO_ASPECT_8 = 0x3,
+} MacroTileAspect;
+typedef enum GATCL1RequestType {
+ GATCL1_TYPE_NORMAL = 0x0,
+ GATCL1_TYPE_SHOOTDOWN = 0x1,
+ GATCL1_TYPE_BYPASS = 0x2,
+} GATCL1RequestType;
+typedef enum TCC_CACHE_POLICIES {
+ TCC_CACHE_POLICY_LRU = 0x0,
+ TCC_CACHE_POLICY_STREAM = 0x1,
+} TCC_CACHE_POLICIES;
+typedef enum MTYPE {
+ MTYPE_NC_NV = 0x0,
+ MTYPE_NC = 0x1,
+ MTYPE_CC = 0x2,
+ MTYPE_UC = 0x3,
+} MTYPE;
+typedef enum PERFMON_COUNTER_MODE {
+ PERFMON_COUNTER_MODE_ACCUM = 0x0,
+ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
+ PERFMON_COUNTER_MODE_MAX = 0x2,
+ PERFMON_COUNTER_MODE_DIRTY = 0x3,
+ PERFMON_COUNTER_MODE_SAMPLE = 0x4,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
+ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
+ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
+ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
+ PERFMON_COUNTER_MODE_RESERVED = 0xf,
+} PERFMON_COUNTER_MODE;
+typedef enum PERFMON_SPM_MODE {
+ PERFMON_SPM_MODE_OFF = 0x0,
+ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
+ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
+ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
+ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
+ PERFMON_SPM_MODE_RESERVED_5 = 0x5,
+ PERFMON_SPM_MODE_RESERVED_6 = 0x6,
+ PERFMON_SPM_MODE_RESERVED_7 = 0x7,
+ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
+ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
+ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
+} PERFMON_SPM_MODE;
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0x0,
+ ARRAY_TILED = 0x1,
+} SurfaceTiling;
+typedef enum SurfaceArray {
+ ARRAY_1D = 0x0,
+ ARRAY_2D = 0x1,
+ ARRAY_3D = 0x2,
+ ARRAY_3D_SLICE = 0x3,
+} SurfaceArray;
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0x0,
+ ARRAY_2D_COLOR = 0x1,
+ ARRAY_3D_SLICE_COLOR = 0x3,
+} ColorArray;
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0x0,
+ ARRAY_2D_DEPTH = 0x1,
+} DepthArray;
+typedef enum ENUM_NUM_SIMD_PER_CU {
+ NUM_SIMD_PER_CU = 0x4,
+} ENUM_NUM_SIMD_PER_CU;
+typedef enum MEM_PWR_FORCE_CTRL {
+ NO_FORCE_REQUEST = 0x0,
+ FORCE_LIGHT_SLEEP_REQUEST = 0x1,
+ FORCE_DEEP_SLEEP_REQUEST = 0x2,
+ FORCE_SHUT_DOWN_REQUEST = 0x3,
+} MEM_PWR_FORCE_CTRL;
+typedef enum MEM_PWR_FORCE_CTRL2 {
+ NO_FORCE_REQ = 0x0,
+ FORCE_LIGHT_SLEEP_REQ = 0x1,
+} MEM_PWR_FORCE_CTRL2;
+typedef enum MEM_PWR_DIS_CTRL {
+ ENABLE_MEM_PWR_CTRL = 0x0,
+ DISABLE_MEM_PWR_CTRL = 0x1,
+} MEM_PWR_DIS_CTRL;
+typedef enum MEM_PWR_SEL_CTRL {
+ DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
+ DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
+ DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
+} MEM_PWR_SEL_CTRL;
+typedef enum MEM_PWR_SEL_CTRL2 {
+ DYNAMIC_DEEP_SLEEP_EN = 0x0,
+ DYNAMIC_LIGHT_SLEEP_EN = 0x1,
+} MEM_PWR_SEL_CTRL2;
+
+#endif /* GFX_8_0_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h
new file mode 100644
index 000000000000..7d722458d9f5
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h
@@ -0,0 +1,20776 @@
+/*
+ * GFX_8_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GFX_8_0_SH_MASK_H
+#define GFX_8_0_SH_MASK_H
+
+#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
+#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
+#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
+#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
+#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
+#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
+#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
+#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x2
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x7c
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2
+#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
+#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
+#define CB_COLOR_CONTROL__MODE_MASK 0x70
+#define CB_COLOR_CONTROL__MODE__SHIFT 0x4
+#define CB_COLOR_CONTROL__ROP3_MASK 0xff0000
+#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
+#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR0_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR1_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR2_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR3_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR4_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR5_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR6_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR7_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR0_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR0_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR0_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
+#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000
+#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
+#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR1_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR1_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR1_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
+#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000
+#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
+#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR2_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR2_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR2_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
+#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000
+#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
+#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR3_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR3_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR3_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
+#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000
+#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
+#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR4_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR4_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR4_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
+#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000
+#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
+#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR5_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR5_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR5_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
+#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000
+#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
+#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR6_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR6_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR6_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
+#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000
+#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
+#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR7_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR7_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR7_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
+#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000
+#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
+#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
+#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
+#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
+#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
+#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
+#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
+#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
+#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
+#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
+#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
+#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
+#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
+#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
+#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
+#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
+#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
+#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
+#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
+#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
+#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
+#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
+#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
+#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
+#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
+#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
+#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
+#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
+#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
+#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
+#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
+#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
+#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
+#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
+#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
+#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
+#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
+#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
+#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
+#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
+#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
+#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
+#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
+#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
+#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
+#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
+#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
+#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
+#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
+#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
+#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
+#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
+#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
+#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
+#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
+#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
+#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
+#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
+#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
+#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
+#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
+#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
+#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
+#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
+#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
+#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
+#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
+#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
+#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
+#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
+#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
+#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
+#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
+#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0xf
+#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0
+#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0xf0
+#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4
+#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0xf00
+#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8
+#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0xf000
+#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc
+#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0xf0000
+#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10
+#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0xf00000
+#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14
+#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0xf000000
+#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18
+#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000
+#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c
+#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0xf
+#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0
+#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0xf0
+#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4
+#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0xf00
+#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8
+#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0xf000
+#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc
+#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0xf0000
+#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10
+#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0xf00000
+#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14
+#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0xf000000
+#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18
+#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000
+#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c
+#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0xf
+#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0
+#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x3c0
+#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6
+#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0xf000
+#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc
+#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x10000
+#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10
+#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x40000
+#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
+#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x80000
+#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
+#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x100000
+#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x200000
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
+#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x400000
+#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
+#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x800000
+#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x1000000
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x2000000
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x4000000
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x8000000
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
+#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000
+#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
+#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000
+#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
+#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000
+#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
+#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000
+#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
+#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x1f
+#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
+#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x7e0
+#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
+#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x1f800
+#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
+#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x3fe0000
+#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
+#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000
+#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x1a
+#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0xff
+#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
+#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x7f00
+#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
+#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x7f8000
+#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
+#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0xf000000
+#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18
+#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xf0000000
+#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c
+#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x1
+#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
+#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x2
+#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1
+#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x4
+#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2
+#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x8
+#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3
+#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x10
+#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x20
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK 0x40
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT 0x6
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x80
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7
+#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x100
+#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x1f
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x20
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x40
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6
+#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0xff00
+#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8
+#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x7f0000
+#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10
+#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0xf000000
+#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18
+#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xf0000000
+#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x1
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0xe
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x10
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x3e0
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x400
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x1000
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0xe000
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x20000
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x1c0000
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x200000
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0xc00000
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x7fc00
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x1ff
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x7fc00
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff
+#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff
+#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff
+#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
+#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY_MASK 0x1
+#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY__SHIFT 0x0
+#define CB_DEBUG_BUS_17__MU_BUSY_MASK 0x2
+#define CB_DEBUG_BUS_17__MU_BUSY__SHIFT 0x1
+#define CB_DEBUG_BUS_17__TQ_BUSY_MASK 0x4
+#define CB_DEBUG_BUS_17__TQ_BUSY__SHIFT 0x2
+#define CB_DEBUG_BUS_17__AC_BUSY_MASK 0x8
+#define CB_DEBUG_BUS_17__AC_BUSY__SHIFT 0x3
+#define CB_DEBUG_BUS_17__CRW_BUSY_MASK 0x10
+#define CB_DEBUG_BUS_17__CRW_BUSY__SHIFT 0x4
+#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY_MASK 0x20
+#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY__SHIFT 0x5
+#define CB_DEBUG_BUS_17__MC_WR_PENDING_MASK 0x40
+#define CB_DEBUG_BUS_17__MC_WR_PENDING__SHIFT 0x6
+#define CB_DEBUG_BUS_17__FC_WR_PENDING_MASK 0x80
+#define CB_DEBUG_BUS_17__FC_WR_PENDING__SHIFT 0x7
+#define CB_DEBUG_BUS_17__FC_RD_PENDING_MASK 0x100
+#define CB_DEBUG_BUS_17__FC_RD_PENDING__SHIFT 0x8
+#define CB_DEBUG_BUS_17__EVICT_PENDING_MASK 0x200
+#define CB_DEBUG_BUS_17__EVICT_PENDING__SHIFT 0x9
+#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER_MASK 0x400
+#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER__SHIFT 0xa
+#define CB_DEBUG_BUS_17__MU_STATE_MASK 0x7f800
+#define CB_DEBUG_BUS_17__MU_STATE__SHIFT 0xb
+#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY_MASK 0x1
+#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY__SHIFT 0x0
+#define CB_DEBUG_BUS_18__FOP_BUSY_MASK 0x2
+#define CB_DEBUG_BUS_18__FOP_BUSY__SHIFT 0x1
+#define CB_DEBUG_BUS_18__CLEAR_BUSY_MASK 0x4
+#define CB_DEBUG_BUS_18__CLEAR_BUSY__SHIFT 0x2
+#define CB_DEBUG_BUS_18__LAT_BUSY_MASK 0x8
+#define CB_DEBUG_BUS_18__LAT_BUSY__SHIFT 0x3
+#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY_MASK 0x10
+#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY__SHIFT 0x4
+#define CB_DEBUG_BUS_18__ADDR_BUSY_MASK 0x20
+#define CB_DEBUG_BUS_18__ADDR_BUSY__SHIFT 0x5
+#define CB_DEBUG_BUS_18__MERGE_BUSY_MASK 0x40
+#define CB_DEBUG_BUS_18__MERGE_BUSY__SHIFT 0x6
+#define CB_DEBUG_BUS_18__QUAD_BUSY_MASK 0x80
+#define CB_DEBUG_BUS_18__QUAD_BUSY__SHIFT 0x7
+#define CB_DEBUG_BUS_18__TILE_BUSY_MASK 0x100
+#define CB_DEBUG_BUS_18__TILE_BUSY__SHIFT 0x8
+#define CB_DEBUG_BUS_18__DCC_BUSY_MASK 0x200
+#define CB_DEBUG_BUS_18__DCC_BUSY__SHIFT 0x9
+#define CB_DEBUG_BUS_18__DOC_BUSY_MASK 0x400
+#define CB_DEBUG_BUS_18__DOC_BUSY__SHIFT 0xa
+#define CB_DEBUG_BUS_18__DAG_BUSY_MASK 0x800
+#define CB_DEBUG_BUS_18__DAG_BUSY__SHIFT 0xb
+#define CB_DEBUG_BUS_18__DOC_STALL_MASK 0x1000
+#define CB_DEBUG_BUS_18__DOC_STALL__SHIFT 0xc
+#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL_MASK 0x2000
+#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL__SHIFT 0xd
+#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL_MASK 0x4000
+#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL__SHIFT 0xe
+#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL_MASK 0x8000
+#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL__SHIFT 0xf
+#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL_MASK 0x10000
+#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL__SHIFT 0x10
+#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST_MASK 0x20000
+#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST__SHIFT 0x11
+#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING_MASK 0x40000
+#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING__SHIFT 0x12
+#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING_MASK 0x80000
+#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING__SHIFT 0x13
+#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING_MASK 0x100000
+#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING__SHIFT 0x14
+#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING_MASK 0x200000
+#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING__SHIFT 0x15
+#define CB_DEBUG_BUS_19__SURF_SYNC_STATE_MASK 0x3
+#define CB_DEBUG_BUS_19__SURF_SYNC_STATE__SHIFT 0x0
+#define CB_DEBUG_BUS_19__SURF_SYNC_START_MASK 0x4
+#define CB_DEBUG_BUS_19__SURF_SYNC_START__SHIFT 0x2
+#define CB_DEBUG_BUS_19__SF_BUSY_MASK 0x8
+#define CB_DEBUG_BUS_19__SF_BUSY__SHIFT 0x3
+#define CB_DEBUG_BUS_19__CS_BUSY_MASK 0x10
+#define CB_DEBUG_BUS_19__CS_BUSY__SHIFT 0x4
+#define CB_DEBUG_BUS_19__RB_BUSY_MASK 0x20
+#define CB_DEBUG_BUS_19__RB_BUSY__SHIFT 0x5
+#define CB_DEBUG_BUS_19__DS_BUSY_MASK 0x40
+#define CB_DEBUG_BUS_19__DS_BUSY__SHIFT 0x6
+#define CB_DEBUG_BUS_19__TB_BUSY_MASK 0x80
+#define CB_DEBUG_BUS_19__TB_BUSY__SHIFT 0x7
+#define CB_DEBUG_BUS_19__IB_BUSY_MASK 0x100
+#define CB_DEBUG_BUS_19__IB_BUSY__SHIFT 0x8
+#define CB_DEBUG_BUS_19__DRR_BUSY_MASK 0x200
+#define CB_DEBUG_BUS_19__DRR_BUSY__SHIFT 0x9
+#define CB_DEBUG_BUS_19__DF_BUSY_MASK 0x400
+#define CB_DEBUG_BUS_19__DF_BUSY__SHIFT 0xa
+#define CB_DEBUG_BUS_19__DD_BUSY_MASK 0x800
+#define CB_DEBUG_BUS_19__DD_BUSY__SHIFT 0xb
+#define CB_DEBUG_BUS_19__DC_BUSY_MASK 0x1000
+#define CB_DEBUG_BUS_19__DC_BUSY__SHIFT 0xc
+#define CB_DEBUG_BUS_19__DK_BUSY_MASK 0x2000
+#define CB_DEBUG_BUS_19__DK_BUSY__SHIFT 0xd
+#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY_MASK 0x4000
+#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY__SHIFT 0xe
+#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY_MASK 0x8000
+#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY__SHIFT 0xf
+#define CB_DEBUG_BUS_19__DD_READY_MASK 0x10000
+#define CB_DEBUG_BUS_19__DD_READY__SHIFT 0x10
+#define CB_DEBUG_BUS_19__DC_FIFO_FULL_MASK 0x20000
+#define CB_DEBUG_BUS_19__DC_FIFO_FULL__SHIFT 0x11
+#define CB_DEBUG_BUS_19__DC_READY_MASK 0x40000
+#define CB_DEBUG_BUS_19__DC_READY__SHIFT 0x12
+#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS_MASK 0x3f
+#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS__SHIFT 0x0
+#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS_MASK 0xfc0
+#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS__SHIFT 0x6
+#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN_MASK 0x1000
+#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN__SHIFT 0xc
+#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN_MASK 0x2000
+#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN__SHIFT 0xd
+#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN_MASK 0x4000
+#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN__SHIFT 0xe
+#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN_MASK 0x10000
+#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN__SHIFT 0x10
+#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN_MASK 0x20000
+#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN__SHIFT 0x11
+#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN_MASK 0x40000
+#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN__SHIFT 0x12
+#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY_MASK 0x100000
+#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY__SHIFT 0x14
+#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY_MASK 0x200000
+#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY__SHIFT 0x15
+#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY_MASK 0x400000
+#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY__SHIFT 0x16
+#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY_MASK 0x800000
+#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY__SHIFT 0x17
+#define CB_DEBUG_BUS_21__CM_BUSY_MASK 0x1
+#define CB_DEBUG_BUS_21__CM_BUSY__SHIFT 0x0
+#define CB_DEBUG_BUS_21__FC_BUSY_MASK 0x2
+#define CB_DEBUG_BUS_21__FC_BUSY__SHIFT 0x1
+#define CB_DEBUG_BUS_21__CC_BUSY_MASK 0x4
+#define CB_DEBUG_BUS_21__CC_BUSY__SHIFT 0x2
+#define CB_DEBUG_BUS_21__BB_BUSY_MASK 0x8
+#define CB_DEBUG_BUS_21__BB_BUSY__SHIFT 0x3
+#define CB_DEBUG_BUS_21__MA_BUSY_MASK 0x10
+#define CB_DEBUG_BUS_21__MA_BUSY__SHIFT 0x4
+#define CB_DEBUG_BUS_21__CORE_SCLK_VLD_MASK 0x20
+#define CB_DEBUG_BUS_21__CORE_SCLK_VLD__SHIFT 0x5
+#define CB_DEBUG_BUS_21__REG_SCLK1_VLD_MASK 0x40
+#define CB_DEBUG_BUS_21__REG_SCLK1_VLD__SHIFT 0x6
+#define CB_DEBUG_BUS_21__REG_SCLK0_VLD_MASK 0x80
+#define CB_DEBUG_BUS_21__REG_SCLK0_VLD__SHIFT 0x7
+#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS_MASK 0xfff
+#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS__SHIFT 0x0
+#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES_MASK 0xfff000
+#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES__SHIFT 0xc
+#define CP_DFY_CNTL__POLICY_MASK 0x1
+#define CP_DFY_CNTL__POLICY__SHIFT 0x0
+#define CP_DFY_CNTL__MTYPE_MASK 0xc
+#define CP_DFY_CNTL__MTYPE__SHIFT 0x2
+#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000
+#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c
+#define CP_DFY_CNTL__MODE_MASK 0x60000000
+#define CP_DFY_CNTL__MODE__SHIFT 0x1d
+#define CP_DFY_CNTL__ENABLE_MASK 0x80000000
+#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f
+#define CP_DFY_STAT__BURST_COUNT_MASK 0xffff
+#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0
+#define CP_DFY_STAT__TAGS_PENDING_MASK 0x1ff0000
+#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10
+#define CP_DFY_STAT__BUSY_MASK 0x80000000
+#define CP_DFY_STAT__BUSY__SHIFT 0x1f
+#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xffffffff
+#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xffffffe0
+#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5
+#define CP_DFY_DATA_0__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_0__DATA__SHIFT 0x0
+#define CP_DFY_DATA_1__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_1__DATA__SHIFT 0x0
+#define CP_DFY_DATA_2__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_2__DATA__SHIFT 0x0
+#define CP_DFY_DATA_3__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_3__DATA__SHIFT 0x0
+#define CP_DFY_DATA_4__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_4__DATA__SHIFT 0x0
+#define CP_DFY_DATA_5__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_5__DATA__SHIFT 0x0
+#define CP_DFY_DATA_6__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_6__DATA__SHIFT 0x0
+#define CP_DFY_DATA_7__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_7__DATA__SHIFT 0x0
+#define CP_DFY_DATA_8__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_8__DATA__SHIFT 0x0
+#define CP_DFY_DATA_9__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_9__DATA__SHIFT 0x0
+#define CP_DFY_DATA_10__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_10__DATA__SHIFT 0x0
+#define CP_DFY_DATA_11__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_11__DATA__SHIFT 0x0
+#define CP_DFY_DATA_12__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_12__DATA__SHIFT 0x0
+#define CP_DFY_DATA_13__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_13__DATA__SHIFT 0x0
+#define CP_DFY_DATA_14__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_14__DATA__SHIFT 0x0
+#define CP_DFY_DATA_15__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_15__DATA__SHIFT 0x0
+#define CP_DFY_CMD__OFFSET_MASK 0x1ff
+#define CP_DFY_CMD__OFFSET__SHIFT 0x0
+#define CP_DFY_CMD__SIZE_MASK 0xffff0000
+#define CP_DFY_CMD__SIZE__SHIFT 0x10
+#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0xff
+#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0
+#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0xff00
+#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8
+#define CP_RB0_BASE__RB_BASE_MASK 0xffffffff
+#define CP_RB0_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0xff
+#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0
+#define CP_RB_BASE__RB_BASE_MASK 0xffffffff
+#define CP_RB_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB1_BASE__RB_BASE_MASK 0xffffffff
+#define CP_RB1_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0xff
+#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0
+#define CP_RB2_BASE__RB_BASE_MASK 0xffffffff
+#define CP_RB2_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x3f
+#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x3f00
+#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB0_CNTL__MTYPE_MASK 0x18000
+#define CP_RB0_CNTL__MTYPE__SHIFT 0xf
+#define CP_RB0_CNTL__BUF_SWAP_MASK 0x60000
+#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11
+#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x300000
+#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
+#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x1000000
+#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x8000000
+#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
+#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB_CNTL__RB_BUFSZ_MASK 0x3f
+#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB_CNTL__RB_BLKSZ_MASK 0x3f00
+#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB_CNTL__MTYPE_MASK 0x18000
+#define CP_RB_CNTL__MTYPE__SHIFT 0xf
+#define CP_RB_CNTL__BUF_SWAP_MASK 0x60000
+#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x11
+#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x300000
+#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
+#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB_CNTL__CACHE_POLICY_MASK 0x1000000
+#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x8000000
+#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
+#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x3f
+#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x3f00
+#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB1_CNTL__MTYPE_MASK 0x18000
+#define CP_RB1_CNTL__MTYPE__SHIFT 0xf
+#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x300000
+#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
+#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x1000000
+#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x8000000
+#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
+#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x3f
+#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x3f00
+#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB2_CNTL__MTYPE_MASK 0x18000
+#define CP_RB2_CNTL__MTYPE__SHIFT 0xf
+#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x300000
+#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
+#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x1000000
+#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x8000000
+#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
+#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0xfffff
+#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0
+#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
+#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
+#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
+#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
+#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
+#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
+#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
+#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
+#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
+#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
+#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
+#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
+#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
+#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB0_WPTR__RB_WPTR_MASK 0xfffff
+#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB_WPTR__RB_WPTR_MASK 0xfffff
+#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB1_WPTR__RB_WPTR_MASK 0xfffff
+#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB2_WPTR__RB_WPTR_MASK 0xfffff
+#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xfffffffc
+#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2
+#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0xff
+#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0
+#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
+#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
+#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x40000
+#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12
+#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x80000
+#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
+#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x200000
+#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15
+#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000
+#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
+#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
+#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x40000
+#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12
+#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000
+#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
+#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x200000
+#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15
+#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000
+#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
+#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
+#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x40000
+#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12
+#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x80000
+#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
+#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x200000
+#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15
+#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000
+#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
+#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
+#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x40000
+#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12
+#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x80000
+#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
+#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x200000
+#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15
+#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x400000
+#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
+#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
+#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x4000
+#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
+#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x40000
+#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12
+#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x80000
+#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x100000
+#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x200000
+#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15
+#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x400000
+#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000
+#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x1000000
+#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x4000000
+#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000
+#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000
+#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000
+#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
+#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
+#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x4000
+#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
+#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x40000
+#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12
+#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x80000
+#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x100000
+#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x200000
+#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15
+#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x400000
+#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x800000
+#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x1000000
+#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x4000000
+#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
+#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000
+#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000
+#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000
+#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
+#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
+#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x4000
+#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
+#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x40000
+#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12
+#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x80000
+#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x100000
+#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x200000
+#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15
+#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x400000
+#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x800000
+#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x1000000
+#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x4000000
+#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
+#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000
+#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000
+#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000
+#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
+#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
+#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x4000
+#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
+#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x40000
+#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12
+#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x80000
+#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x100000
+#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x200000
+#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15
+#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x400000
+#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x800000
+#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x1000000
+#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x4000000
+#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
+#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000
+#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000
+#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000
+#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_DEVICE_ID__DEVICE_ID_MASK 0xff
+#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
+#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
+#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
+#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
+#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_RING0_PRIORITY__PRIORITY_MASK 0x3
+#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_RING1_PRIORITY__PRIORITY_MASK 0x3
+#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_RING2_PRIORITY__PRIORITY_MASK 0x3
+#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x3
+#define CP_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0
+#define CP_RB_VMID__RB0_VMID_MASK 0xf
+#define CP_RB_VMID__RB0_VMID__SHIFT 0x0
+#define CP_RB_VMID__RB1_VMID_MASK 0xf00
+#define CP_RB_VMID__RB1_VMID__SHIFT 0x8
+#define CP_RB_VMID__RB2_VMID_MASK 0xf0000
+#define CP_RB_VMID__RB2_VMID__SHIFT 0x10
+#define CP_ME0_PIPE0_VMID__VMID_MASK 0xf
+#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0
+#define CP_ME0_PIPE1_VMID__VMID_MASK 0xf
+#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
+#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc
+#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
+#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc
+#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
+#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc
+#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
+#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc
+#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
+#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x1fff
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x1fff
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0
+#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffff
+#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0
+#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
+#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
+#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff
+#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
+#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff
+#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
+#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
+#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
+#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
+#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1
+#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
+#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x2
+#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4
+#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
+#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8
+#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
+#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10
+#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
+#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20
+#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
+#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40
+#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
+#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80
+#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
+#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100
+#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
+#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200
+#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
+#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1
+#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
+#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x2
+#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4
+#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
+#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8
+#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
+#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10
+#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
+#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20
+#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
+#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40
+#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
+#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80
+#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
+#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100
+#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
+#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200
+#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
+#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xffffffff
+#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0
+#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x1
+#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0
+#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x2
+#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x100
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x200
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x400
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x800
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x10000
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x20000
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x40000
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x80000
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0
+#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x2
+#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1
+#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x7c
+#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
+#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x80
+#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0xff00
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0xff0000
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10
+#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
+#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
+#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x3
+#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0
+#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0xf0
+#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4
+#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x300
+#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8
+#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0xc00
+#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa
+#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x7000
+#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc
+#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0xf0000
+#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10
+#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xffffffff
+#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0
+#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xffffffff
+#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0
+#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xffffffff
+#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0
+#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0xff
+#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0
+#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000
+#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e
+#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000
+#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f
+#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xffffffff
+#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0
+#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
+#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
+#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
+#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
+#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
+#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
+#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
+#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
+#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
+#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
+#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
+#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
+#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
+#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
+#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
+#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
+#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
+#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
+#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
+#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
+#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
+#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
+#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
+#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
+#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
+#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
+#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
+#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
+#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
+#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
+#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
+#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
+#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
+#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
+#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
+#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
+#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000
+#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
+#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
+#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
+#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
+#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
+#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000
+#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
+#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
+#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
+#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
+#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
+#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
+#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
+#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
+#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
+#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
+#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
+#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
+#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
+#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
+#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
+#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
+#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000
+#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
+#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
+#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
+#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
+#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
+#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000
+#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
+#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
+#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
+#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
+#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
+#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
+#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
+#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
+#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
+#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
+#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
+#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
+#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
+#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
+#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
+#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x7ff
+#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0xfff
+#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0xfff
+#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0xffff
+#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0xffff
+#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x7ff
+#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0xfff
+#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0xfff
+#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0xffff
+#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0xffff
+#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x7
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x70
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x70000
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x700000
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14
+#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x7
+#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0
+#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0xff
+#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0
+#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0xff00
+#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8
+#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0xff0000
+#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10
+#define CP_IQ_WAIT_TIME1__GWS_MASK 0xff000000
+#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18
+#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0xff
+#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0
+#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0xff00
+#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8
+#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0xff0000
+#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10
+#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xff000000
+#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18
+#define CP_VMID_RESET__RESET_REQUEST_MASK 0xffff
+#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0
+#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000
+#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x10
+#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0xffff
+#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0
+#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0xf0000
+#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10
+#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0xffff
+#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0
+#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xffff0000
+#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10
+#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xfffffff
+#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0
+#define CPC_INT_CNTX_ID__QUEUE_ID_MASK 0x70000000
+#define CPC_INT_CNTX_ID__QUEUE_ID__SHIFT 0x1c
+#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x1
+#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0
+#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x2
+#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1
+#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xfffff000
+#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc
+#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0xffff
+#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0
+#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0xf
+#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0
+#define CP_CPC_IC_BASE_CNTL__ATC_MASK 0x800000
+#define CP_CPC_IC_BASE_CNTL__ATC__SHIFT 0x17
+#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x1000000
+#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_CPC_IC_BASE_CNTL__MTYPE_MASK 0x18000000
+#define CP_CPC_IC_BASE_CNTL__MTYPE__SHIFT 0x1b
+#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x1
+#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0
+#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x10
+#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4
+#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x20
+#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5
+#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x1
+#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
+#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x2
+#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
+#define CP_CPC_STATUS__DC0_BUSY_MASK 0x4
+#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
+#define CP_CPC_STATUS__DC1_BUSY_MASK 0x8
+#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
+#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x10
+#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
+#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x20
+#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
+#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x40
+#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
+#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x80
+#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
+#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x400
+#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
+#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x800
+#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
+#define CP_CPC_STATUS__QU_BUSY_MASK 0x1000
+#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
+#define CP_CPC_STATUS__ATCL2IU_BUSY_MASK 0x2000
+#define CP_CPC_STATUS__ATCL2IU_BUSY__SHIFT 0xd
+#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000
+#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
+#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000
+#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
+#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000
+#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
+#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x1
+#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
+#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x2
+#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
+#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x4
+#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
+#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x8
+#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
+#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x10
+#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
+#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20
+#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
+#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x40
+#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
+#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x80
+#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
+#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x100
+#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
+#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x200
+#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
+#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400
+#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
+#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800
+#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
+#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x1000
+#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
+#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x2000
+#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
+#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x10000
+#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
+#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x20000
+#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
+#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x40000
+#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
+#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x80000
+#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
+#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x100000
+#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
+#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x200000
+#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
+#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x400000
+#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
+#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x800000
+#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
+#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x1000000
+#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
+#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x2000000
+#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
+#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x4000000
+#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
+#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x8000000
+#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
+#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000
+#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
+#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000
+#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
+#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x8
+#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
+#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x10
+#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
+#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x40
+#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
+#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x100
+#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x200
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x400
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x2000
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
+#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x10000
+#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x20000
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x40000
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
+#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x400000
+#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x16
+#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x800000
+#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x17
+#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x1000000
+#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x18
+#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x1
+#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
+#define CP_CPF_STATUS__CSF_BUSY_MASK 0x2
+#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
+#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x10
+#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
+#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x20
+#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
+#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x40
+#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
+#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x80
+#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
+#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x100
+#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
+#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x200
+#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x400
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x800
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
+#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x1000
+#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
+#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x2000
+#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
+#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x4000
+#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
+#define CP_CPF_STATUS__HQD_BUSY_MASK 0x8000
+#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
+#define CP_CPF_STATUS__PRT_BUSY_MASK 0x10000
+#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10
+#define CP_CPF_STATUS__ATCL2IU_BUSY_MASK 0x20000
+#define CP_CPF_STATUS__ATCL2IU_BUSY__SHIFT 0x11
+#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x4000000
+#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a
+#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x8000000
+#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b
+#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000
+#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c
+#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000
+#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
+#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000
+#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
+#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
+#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
+#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x2
+#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x4
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x8
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
+#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x10
+#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x20
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x40
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
+#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x80
+#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
+#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x100
+#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
+#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x200
+#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9
+#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x800
+#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
+#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x1000
+#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
+#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x2000
+#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
+#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x4000
+#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
+#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x8000
+#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
+#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x10000
+#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
+#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x20000
+#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
+#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x40000
+#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
+#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x80000
+#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
+#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x100000
+#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
+#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x200000
+#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
+#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x400000
+#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
+#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x800000
+#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
+#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x1000000
+#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
+#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x2000000
+#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x4000000
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
+#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x8000000
+#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
+#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000
+#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
+#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000
+#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
+#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000
+#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
+#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x1
+#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
+#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x2
+#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
+#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x4
+#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
+#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x8
+#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x20
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x40
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
+#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x80
+#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x7
+#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x100
+#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x8
+#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x200
+#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x9
+#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
+#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
+#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x10
+#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4
+#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x10000
+#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10
+#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x20000
+#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11
+#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x40000
+#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12
+#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x80000
+#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13
+#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x100000
+#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14
+#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x200000
+#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15
+#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000
+#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
+#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000
+#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
+#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000
+#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
+#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000
+#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
+#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
+#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
+#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
+#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
+#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x1ff
+#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
+#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
+#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
+#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
+#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
+#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
+#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
+#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
+#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
+#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
+#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
+#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
+#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
+#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
+#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
+#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
+#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
+#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
+#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0xf
+#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
+#define CP_DRAW_OBJECT__OBJECT_MASK 0xffffffff
+#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0
+#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0xffff
+#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0
+#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xffffffff
+#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0
+#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xffffffff
+#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0
+#define CP_DRAW_WINDOW_LO__MIN_MASK 0xffff
+#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0
+#define CP_DRAW_WINDOW_LO__MAX_MASK 0xffff0000
+#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x1
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x2
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x4
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2
+#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x100
+#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8
+#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xffffffff
+#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0
+#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xffffffff
+#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0
+#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x3
+#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0
+#define CP_PRT_LOD_STATS_CNTL2__INTERVAL_MASK 0x3fc
+#define CP_PRT_LOD_STATS_CNTL2__INTERVAL__SHIFT 0x2
+#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT_MASK 0x3fc00
+#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT__SHIFT 0xa
+#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE_MASK 0x40000
+#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE__SHIFT 0x12
+#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET_MASK 0x80000
+#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET__SHIFT 0x13
+#define CP_PRT_LOD_STATS_CNTL2__MC_VMID_MASK 0x7800000
+#define CP_PRT_LOD_STATS_CNTL2__MC_VMID__SHIFT 0x17
+#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY_MASK 0x10000000
+#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY__SHIFT 0x1c
+#define CP_PRT_LOD_STATS_CNTL2__MTYPE_MASK 0xc0000000
+#define CP_PRT_LOD_STATS_CNTL2__MTYPE__SHIFT 0x1e
+#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xffffffff
+#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
+#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
+#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
+#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xffffffff
+#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
+#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xffffffff
+#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
+#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
+#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
+#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x7f
+#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0
+#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x3f000
+#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc
+#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK 0x2000000
+#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL__SHIFT 0x19
+#define CP_EOP_DONE_EVENT_CNTL__MTYPE_MASK 0x18000000
+#define CP_EOP_DONE_EVENT_CNTL__MTYPE__SHIFT 0x1b
+#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0xffff
+#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x0
+#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x30000
+#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10
+#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x7000000
+#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18
+#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000
+#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d
+#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xfffffff
+#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0
+#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffc
+#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2
+#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0xffff
+#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffff
+#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0
+#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffff
+#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0
+#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffff
+#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0
+#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffff
+#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0
+#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffc
+#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2
+#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffff
+#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0
+#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffc
+#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2
+#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffff
+#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0
+#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0
+#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0
+#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0
+#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0
+#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0
+#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0
+#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffff
+#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0
+#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffff
+#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0
+#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffff
+#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0
+#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffff
+#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffff
+#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffff
+#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffff
+#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffff
+#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0
+#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL_MASK 0x2000000
+#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL__SHIFT 0x19
+#define CP_PIPE_STATS_CONTROL__MTYPE_MASK 0x18000000
+#define CP_PIPE_STATS_CONTROL__MTYPE__SHIFT 0x1b
+#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL_MASK 0x2000000
+#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL__SHIFT 0x19
+#define CP_STREAM_OUT_CONTROL__MTYPE_MASK 0x18000000
+#define CP_STREAM_OUT_CONTROL__MTYPE__SHIFT 0x1b
+#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x1
+#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0
+#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
+#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
+#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
+#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
+#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
+#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
+#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
+#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
+#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
+#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
+#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
+#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
+#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
+#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
+#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
+#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
+#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0xff
+#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0
+#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x30000
+#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10
+#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffff
+#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0
+#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
+#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
+#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
+#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
+#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
+#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
+#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
+#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffc
+#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2
+#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0xffff
+#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0
+#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x10000
+#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10
+#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x2000000
+#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19
+#define CP_APPEND_ADDR_HI__MTYPE_MASK 0x18000000
+#define CP_APPEND_ADDR_HI__MTYPE__SHIFT 0x1b
+#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000
+#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d
+#define CP_APPEND_DATA__DATA_MASK 0xffffffff
+#define CP_APPEND_DATA__DATA__SHIFT 0x0
+#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffff
+#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0
+#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffff
+#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0
+#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
+#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
+#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
+#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
+#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
+#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
+#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
+#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
+#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
+#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
+#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
+#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
+#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
+#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
+#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
+#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
+#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x3
+#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x0
+#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffc
+#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2
+#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0xffff
+#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0
+#define CP_ME_MC_WADDR_HI__MTYPE_MASK 0x300000
+#define CP_ME_MC_WADDR_HI__MTYPE__SHIFT 0x14
+#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x400000
+#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16
+#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffff
+#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0
+#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffff
+#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0
+#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x3
+#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x0
+#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffc
+#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2
+#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0xffff
+#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0
+#define CP_ME_MC_RADDR_HI__MTYPE_MASK 0x300000
+#define CP_ME_MC_RADDR_HI__MTYPE__SHIFT 0x14
+#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x400000
+#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16
+#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffff
+#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
+#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
+#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
+#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
+#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
+#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
+#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
+#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
+#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
+#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
+#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
+#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
+#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
+#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
+#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
+#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
+#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
+#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
+#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
+#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
+#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
+#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffff
+#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0
+#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x3f
+#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0
+#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x1
+#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0
+#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x2
+#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1
+#define CP_COHER_CNTL__TC_SD_ACTION_ENA_MASK 0x4
+#define CP_COHER_CNTL__TC_SD_ACTION_ENA__SHIFT 0x2
+#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x8
+#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3
+#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x40
+#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6
+#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x80
+#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7
+#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x100
+#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8
+#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x200
+#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9
+#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x400
+#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
+#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x800
+#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb
+#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x1000
+#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc
+#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x2000
+#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd
+#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x4000
+#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe
+#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x8000
+#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf
+#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x40000
+#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12
+#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x80000
+#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13
+#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x200000
+#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15
+#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x400000
+#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16
+#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x800000
+#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17
+#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x2000000
+#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19
+#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x4000000
+#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a
+#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x8000000
+#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b
+#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000
+#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c
+#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000
+#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d
+#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000
+#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e
+#define CP_COHER_CNTL__SH_SD_ACTION_ENA_MASK 0x80000000
+#define CP_COHER_CNTL__SH_SD_ACTION_ENA__SHIFT 0x1f
+#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffff
+#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
+#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0xff
+#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
+#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffff
+#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
+#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0xff
+#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
+#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0xff
+#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0
+#define CP_COHER_STATUS__MEID_MASK 0x3000000
+#define CP_COHER_STATUS__MEID__SHIFT 0x18
+#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000
+#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x1e
+#define CP_COHER_STATUS__STATUS_MASK 0x80000000
+#define CP_COHER_STATUS__STATUS__SHIFT 0x1f
+#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0
+#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
+#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0
+#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
+#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
+#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffff
+#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0
+#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
+#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
+#define CP_DMA_ME_CONTROL__SRC_MTYPE_MASK 0xc00
+#define CP_DMA_ME_CONTROL__SRC_MTYPE__SHIFT 0xa
+#define CP_DMA_ME_CONTROL__SRC_ATC_MASK 0x1000
+#define CP_DMA_ME_CONTROL__SRC_ATC__SHIFT 0xc
+#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x2000
+#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
+#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x300000
+#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14
+#define CP_DMA_ME_CONTROL__DST_MTYPE_MASK 0xc00000
+#define CP_DMA_ME_CONTROL__DST_MTYPE__SHIFT 0x16
+#define CP_DMA_ME_CONTROL__DST_ATC_MASK 0x1000000
+#define CP_DMA_ME_CONTROL__DST_ATC__SHIFT 0x18
+#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x2000000
+#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
+#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000
+#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d
+#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x1fffff
+#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0
+#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x200000
+#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x15
+#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0xc00000
+#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x16
+#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x3000000
+#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x18
+#define CP_DMA_ME_COMMAND__SAS_MASK 0x4000000
+#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a
+#define CP_DMA_ME_COMMAND__DAS_MASK 0x8000000
+#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b
+#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000
+#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c
+#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000
+#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d
+#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000
+#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e
+#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
+#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0
+#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
+#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
+#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffff
+#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0
+#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
+#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
+#define CP_DMA_PFP_CONTROL__SRC_MTYPE_MASK 0xc00
+#define CP_DMA_PFP_CONTROL__SRC_MTYPE__SHIFT 0xa
+#define CP_DMA_PFP_CONTROL__SRC_ATC_MASK 0x1000
+#define CP_DMA_PFP_CONTROL__SRC_ATC__SHIFT 0xc
+#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x2000
+#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
+#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x300000
+#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14
+#define CP_DMA_PFP_CONTROL__DST_MTYPE_MASK 0xc00000
+#define CP_DMA_PFP_CONTROL__DST_MTYPE__SHIFT 0x16
+#define CP_DMA_PFP_CONTROL__DST_ATC_MASK 0x1000000
+#define CP_DMA_PFP_CONTROL__DST_ATC__SHIFT 0x18
+#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x2000000
+#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
+#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000
+#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d
+#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x1fffff
+#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0
+#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x200000
+#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x15
+#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0xc00000
+#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x16
+#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x3000000
+#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x18
+#define CP_DMA_PFP_COMMAND__SAS_MASK 0x4000000
+#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a
+#define CP_DMA_PFP_COMMAND__DAS_MASK 0x8000000
+#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b
+#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000
+#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c
+#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000
+#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d
+#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000
+#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e
+#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x30
+#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4
+#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0xf0000
+#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10
+#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000
+#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c
+#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000
+#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d
+#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000
+#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e
+#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x3ffffff
+#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0
+#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000
+#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c
+#define CP_PFP_IB_CONTROL__IB_EN_MASK 0xff
+#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0
+#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x1
+#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0
+#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x2
+#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1
+#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x10000
+#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10
+#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x1000000
+#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18
+#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff
+#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
+#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
+#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
+#define CP_RB_OFFSET__RB_OFFSET_MASK 0xfffff
+#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0
+#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
+#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
+#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
+#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
+#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0xfffff
+#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0
+#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0xfffff
+#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0
+#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0xfffff
+#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0
+#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0xfffff
+#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0
+#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
+#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
+#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
+#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
+#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xffffffff
+#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0
+#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0xfffff
+#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0
+#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x3
+#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0
+#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x3
+#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0
+#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x1
+#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0
+#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff
+#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
+#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff
+#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
+#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xffffffff
+#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0xffff
+#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xffffffff
+#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0xffff
+#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xffffffff
+#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
+#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x3
+#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
+#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xffffffff
+#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0xffff
+#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x1
+#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0
+#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x2
+#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1
+#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x4
+#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2
+#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x8
+#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3
+#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x10
+#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4
+#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x20
+#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5
+#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x40
+#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6
+#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x80
+#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7
+#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x1
+#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
+#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x4
+#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
+#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x10
+#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x400
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x800
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
+#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x1000
+#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
+#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x2000
+#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
+#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x4000
+#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe
+#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x8000
+#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x800000
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x1000000
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x2000000
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x4000000
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x8000000
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
+#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000
+#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
+#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
+#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
+#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x2
+#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
+#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x4
+#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
+#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x10
+#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
+#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x20
+#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
+#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x100
+#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
+#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x200
+#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
+#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x400
+#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
+#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x800
+#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
+#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x1000
+#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
+#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x2000
+#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x4000
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
+#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x8000
+#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
+#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x10000
+#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
+#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x20000
+#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x40000
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
+#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x80000
+#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
+#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x100000
+#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x200000
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x400000
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
+#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x800000
+#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
+#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x1000000
+#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x2000000
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x4000000
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
+#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x8000000
+#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
+#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000
+#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
+#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000
+#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
+#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
+#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x2
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
+#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x4
+#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x8
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
+#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x10
+#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
+#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x20
+#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
+#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x40
+#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
+#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x80
+#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
+#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x400
+#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
+#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x800
+#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x1000
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x2000
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x4000
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x8000
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
+#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x10000
+#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10
+#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x20000
+#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11
+#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE_MASK 0x40000
+#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE__SHIFT 0x12
+#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS_MASK 0x80000
+#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x13
+#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS_MASK 0x100000
+#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS__SHIFT 0x14
+#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
+#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
+#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x40
+#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6
+#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x80
+#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7
+#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x100
+#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8
+#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x200
+#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9
+#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x400
+#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
+#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x1000
+#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc
+#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x2000
+#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd
+#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x4000
+#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
+#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x8000
+#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf
+#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x20000
+#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11
+#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x40000
+#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12
+#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x80000
+#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13
+#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x100000
+#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
+#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x200000
+#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15
+#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x400000
+#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16
+#define CP_STAT__ROQ_RING_BUSY_MASK 0x200
+#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9
+#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x400
+#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
+#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x800
+#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb
+#define CP_STAT__ROQ_STATE_BUSY_MASK 0x1000
+#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc
+#define CP_STAT__DC_BUSY_MASK 0x2000
+#define CP_STAT__DC_BUSY__SHIFT 0xd
+#define CP_STAT__ATCL2IU_BUSY_MASK 0x4000
+#define CP_STAT__ATCL2IU_BUSY__SHIFT 0xe
+#define CP_STAT__PFP_BUSY_MASK 0x8000
+#define CP_STAT__PFP_BUSY__SHIFT 0xf
+#define CP_STAT__MEQ_BUSY_MASK 0x10000
+#define CP_STAT__MEQ_BUSY__SHIFT 0x10
+#define CP_STAT__ME_BUSY_MASK 0x20000
+#define CP_STAT__ME_BUSY__SHIFT 0x11
+#define CP_STAT__QUERY_BUSY_MASK 0x40000
+#define CP_STAT__QUERY_BUSY__SHIFT 0x12
+#define CP_STAT__SEMAPHORE_BUSY_MASK 0x80000
+#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13
+#define CP_STAT__INTERRUPT_BUSY_MASK 0x100000
+#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
+#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x200000
+#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15
+#define CP_STAT__DMA_BUSY_MASK 0x400000
+#define CP_STAT__DMA_BUSY__SHIFT 0x16
+#define CP_STAT__RCIU_BUSY_MASK 0x800000
+#define CP_STAT__RCIU_BUSY__SHIFT 0x17
+#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x1000000
+#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18
+#define CP_STAT__CPC_CPG_BUSY_MASK 0x2000000
+#define CP_STAT__CPC_CPG_BUSY__SHIFT 0x19
+#define CP_STAT__CE_BUSY_MASK 0x4000000
+#define CP_STAT__CE_BUSY__SHIFT 0x1a
+#define CP_STAT__TCIU_BUSY_MASK 0x8000000
+#define CP_STAT__TCIU_BUSY__SHIFT 0x1b
+#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000
+#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c
+#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000
+#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d
+#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000
+#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e
+#define CP_STAT__CP_BUSY_MASK 0x80000000
+#define CP_STAT__CP_BUSY__SHIFT 0x1f
+#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffff
+#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0
+#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffff
+#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
+#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x3f00
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x3f0000
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10
+#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffff
+#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0
+#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0xf
+#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x0
+#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x1ff00
+#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8
+#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0xf
+#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x0
+#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x10
+#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4
+#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x40
+#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6
+#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x100
+#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8
+#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x10000
+#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10
+#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x40000
+#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12
+#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x100000
+#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14
+#define CP_ME_CNTL__CE_HALT_MASK 0x1000000
+#define CP_ME_CNTL__CE_HALT__SHIFT 0x18
+#define CP_ME_CNTL__CE_STEP_MASK 0x2000000
+#define CP_ME_CNTL__CE_STEP__SHIFT 0x19
+#define CP_ME_CNTL__PFP_HALT_MASK 0x4000000
+#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a
+#define CP_ME_CNTL__PFP_STEP_MASK 0x8000000
+#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b
+#define CP_ME_CNTL__ME_HALT_MASK 0x10000000
+#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c
+#define CP_ME_CNTL__ME_STEP_MASK 0x20000000
+#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d
+#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0xff
+#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0
+#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x700
+#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8
+#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0xff00000
+#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
+#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000
+#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c
+#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x1
+#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0
+#define CP_RB0_RPTR__RB_RPTR_MASK 0xfffff
+#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB_RPTR__RB_RPTR_MASK 0xfffff
+#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB1_RPTR__RB_RPTR_MASK 0xfffff
+#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB2_RPTR__RB_RPTR_MASK 0xfffff
+#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0xfffffff
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c
+#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0xffff
+#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0
+#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0
+#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5
+#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0xffff
+#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0
+#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0xfff
+#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0
+#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
+#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
+#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
+#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
+#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
+#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
+#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
+#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
+#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
+#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
+#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
+#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
+#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
+#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
+#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
+#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
+#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
+#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
+#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
+#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
+#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
+#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
+#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
+#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
+#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffc
+#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2
+#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0xffff
+#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0
+#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0xfffff
+#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0
+#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0xff
+#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0
+#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0xff00
+#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8
+#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0xff
+#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0
+#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0xff
+#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0
+#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0xff00
+#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8
+#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0xff0000
+#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10
+#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000
+#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18
+#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0xff
+#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0
+#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0xff00
+#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8
+#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0xff0000
+#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10
+#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000
+#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18
+#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0xff
+#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0
+#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0xff00
+#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8
+#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0xff0000
+#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10
+#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x3f
+#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0
+#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x3f00
+#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8
+#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0xff
+#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0
+#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0xff00
+#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8
+#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x7ff
+#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0
+#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x7ff0000
+#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
+#define CP_STQ_AVAIL__STQ_CNT_MASK 0x1ff
+#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0
+#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x7ff
+#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0
+#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x3ff
+#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0
+#define CP_CMD_INDEX__CMD_INDEX_MASK 0x7ff
+#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0
+#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x3000
+#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc
+#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x70000
+#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10
+#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffff
+#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0
+#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x3ff
+#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0
+#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x3ff0000
+#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10
+#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x3ff
+#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0
+#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x3ff0000
+#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10
+#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x3ff
+#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0
+#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x3ff0000
+#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10
+#define CP_STQ_STAT__STQ_RPTR_MASK 0x3ff
+#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0
+#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x3ff
+#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0
+#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x3ff
+#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0
+#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x3ff0000
+#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10
+#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x7ff
+#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0
+#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x7ff0000
+#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10
+#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x7ff
+#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0
+#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x3ff
+#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
+#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000
+#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
+#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x3ff
+#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0
+#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x3ff0000
+#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
+#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x3ff
+#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0
+#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x3ff0000
+#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10
+#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK 0x800
+#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT 0xb
+#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
+#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
+#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
+#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
+#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK 0x40000
+#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT 0x12
+#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x80000
+#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13
+#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x100000
+#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14
+#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK 0x200000
+#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT 0x15
+#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x400000
+#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16
+#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
+#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
+#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
+#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
+#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
+#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
+#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
+#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
+#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
+#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
+#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
+#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
+#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
+#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
+#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0xf
+#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0xf0
+#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
+#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
+#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
+#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000
+#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f
+#define CP_RINGID__RINGID_MASK 0x3
+#define CP_RINGID__RINGID__SHIFT 0x0
+#define CP_PIPEID__PIPE_ID_MASK 0x3
+#define CP_PIPEID__PIPE_ID__SHIFT 0x0
+#define CP_VMID__VMID_MASK 0xf
+#define CP_VMID__VMID__SHIFT 0x0
+#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x7
+#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0
+#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x3f00
+#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8
+#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x3f0000
+#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10
+#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x1f
+#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0
+#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0xe0
+#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5
+#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0xff00
+#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8
+#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xfffffffc
+#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
+#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xffff
+#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
+#define CP_HQD_ACTIVE__ACTIVE_MASK 0x1
+#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0
+#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x2
+#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1
+#define CP_HQD_VMID__VMID_MASK 0xf
+#define CP_HQD_VMID__VMID__SHIFT 0x0
+#define CP_HQD_VMID__IB_VMID_MASK 0xf00
+#define CP_HQD_VMID__IB_VMID__SHIFT 0x8
+#define CP_HQD_VMID__VQID_MASK 0x3ff0000
+#define CP_HQD_VMID__VQID__SHIFT 0x10
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x1
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x3ff00
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8
+#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000
+#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c
+#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000
+#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d
+#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000
+#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e
+#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000
+#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f
+#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x3
+#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0
+#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0xf
+#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0
+#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x1
+#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0
+#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x10
+#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4
+#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x3f00
+#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8
+#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000
+#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f
+#define CP_HQD_PQ_BASE__ADDR_MASK 0xffffffff
+#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0
+#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0xff
+#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0
+#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xffffffff
+#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0
+#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xfffffffc
+#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2
+#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0xffff
+#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0
+#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xfffffffc
+#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x2
+#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0xffff
+#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x1
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x2
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS_MASK 0x3800000
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS__SHIFT 0x17
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
+#define CP_HQD_PQ_WPTR__OFFSET_MASK 0xffffffff
+#define CP_HQD_PQ_WPTR__OFFSET__SHIFT 0x0
+#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f
+#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0
+#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x3f00
+#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8
+#define CP_HQD_PQ_CONTROL__MTYPE_MASK 0x18000
+#define CP_HQD_PQ_CONTROL__MTYPE__SHIFT 0xf
+#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x60000
+#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11
+#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x300000
+#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14
+#define CP_HQD_PQ_CONTROL__PQ_ATC_MASK 0x800000
+#define CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT 0x17
+#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x1000000
+#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18
+#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x6000000
+#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19
+#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x8000000
+#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b
+#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000
+#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c
+#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000
+#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d
+#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000
+#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e
+#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000
+#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f
+#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xfffffffc
+#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2
+#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0xffff
+#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0
+#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0xfffff
+#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0
+#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0xfffff
+#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0
+#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x300000
+#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14
+#define CP_HQD_IB_CONTROL__IB_ATC_MASK 0x800000
+#define CP_HQD_IB_CONTROL__IB_ATC__SHIFT 0x17
+#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x1000000
+#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18
+#define CP_HQD_IB_CONTROL__MTYPE_MASK 0x18000000
+#define CP_HQD_IB_CONTROL__MTYPE__SHIFT 0x1b
+#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000
+#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f
+#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0xff
+#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0
+#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x700
+#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8
+#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x800
+#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb
+#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x3000
+#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc
+#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0xc000
+#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe
+#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x3f0000
+#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10
+#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x400000
+#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16
+#define CP_HQD_IQ_TIMER__IQ_ATC_MASK 0x800000
+#define CP_HQD_IQ_TIMER__IQ_ATC__SHIFT 0x17
+#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x1000000
+#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18
+#define CP_HQD_IQ_TIMER__MTYPE_MASK 0x18000000
+#define CP_HQD_IQ_TIMER__MTYPE__SHIFT 0x1b
+#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000
+#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d
+#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000
+#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e
+#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000
+#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f
+#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x3f
+#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x7
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0
+#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x10
+#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x100
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8
+#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x200
+#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x400
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa
+#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x1
+#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
+#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x1
+#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
+#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x2
+#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1
+#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x10
+#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4
+#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x20
+#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5
+#define CP_HQD_SEMA_CMD__RETRY_MASK 0x1
+#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0
+#define CP_HQD_SEMA_CMD__RESULT_MASK 0x6
+#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1
+#define CP_HQD_MSG_TYPE__ACTION_MASK 0x7
+#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0
+#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x70
+#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4
+#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xffffffff
+#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xffffffff
+#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xffffffff
+#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xffffffff
+#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xffffffff
+#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0
+#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x3
+#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0
+#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0xc
+#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2
+#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x70
+#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4
+#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x80
+#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7
+#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x100
+#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8
+#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x200
+#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9
+#define CP_HQD_HQ_STATUS0__RSVR_31_10_MASK 0xfffffc00
+#define CP_HQD_HQ_STATUS0__RSVR_31_10__SHIFT 0xa
+#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xffffffff
+#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0
+#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xffffffff
+#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0
+#define CP_MQD_CONTROL__VMID_MASK 0xf
+#define CP_MQD_CONTROL__VMID__SHIFT 0x0
+#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x1000
+#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc
+#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x2000
+#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd
+#define CP_MQD_CONTROL__MQD_ATC_MASK 0x800000
+#define CP_MQD_CONTROL__MQD_ATC__SHIFT 0x17
+#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x1000000
+#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
+#define CP_MQD_CONTROL__MTYPE_MASK 0x18000000
+#define CP_MQD_CONTROL__MTYPE__SHIFT 0x1b
+#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xffffffff
+#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0
+#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xffffffff
+#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0
+#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xffffffff
+#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xff
+#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
+#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x3f
+#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0
+#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x100
+#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8
+#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x1000
+#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc
+#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x2000
+#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd
+#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x4000
+#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe
+#define CP_HQD_EOP_CONTROL__MTYPE_MASK 0x18000
+#define CP_HQD_EOP_CONTROL__MTYPE__SHIFT 0xf
+#define CP_HQD_EOP_CONTROL__EOP_ATC_MASK 0x800000
+#define CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT 0x17
+#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x1000000
+#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18
+#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000
+#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d
+#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000
+#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f
+#define CP_HQD_EOP_RPTR__RPTR_MASK 0x1fff
+#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0
+#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000
+#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e
+#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000
+#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f
+#define CP_HQD_EOP_WPTR__WPTR_MASK 0x1fff
+#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0
+#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1fff0000
+#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10
+#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0xfff
+#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0
+#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x10000
+#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10
+#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xfffff000
+#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc
+#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
+#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_HQD_CTX_SAVE_CONTROL__ATC_MASK 0x1
+#define CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT 0x0
+#define CP_HQD_CTX_SAVE_CONTROL__MTYPE_MASK 0x6
+#define CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT 0x1
+#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x8
+#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3
+#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x7ffc
+#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2
+#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x7000
+#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc
+#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x1fffffc
+#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2
+#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x1fff000
+#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc
+#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x1
+#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0
+#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x2
+#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1
+#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x3f0
+#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4
+#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x3f000
+#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc
+#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0xf
+#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0
+#define CP_HQD_ERROR__SUA_ERROR_MASK 0x10
+#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4
+#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x1fff
+#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0
+#define CP_HQD_EOP_DONES__DONE_COUNT_MASK 0xffffffff
+#define CP_HQD_EOP_DONES__DONE_COUNT__SHIFT 0x0
+#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffff
+#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0
+#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffff
+#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0
+#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffff
+#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0
+#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffff
+#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0
+#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0xf
+#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x0
+#define DB_DEPTH_INFO__ARRAY_MODE_MASK 0xf0
+#define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x4
+#define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x1f00
+#define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x8
+#define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x6000
+#define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0xd
+#define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x18000
+#define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0xf
+#define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x60000
+#define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x11
+#define DB_DEPTH_INFO__NUM_BANKS_MASK 0x180000
+#define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x13
+#define DB_Z_INFO__FORMAT_MASK 0x3
+#define DB_Z_INFO__FORMAT__SHIFT 0x0
+#define DB_Z_INFO__NUM_SAMPLES_MASK 0xc
+#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2
+#define DB_Z_INFO__TILE_SPLIT_MASK 0xe000
+#define DB_Z_INFO__TILE_SPLIT__SHIFT 0xd
+#define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x700000
+#define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x14
+#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x7800000
+#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17
+#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
+#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
+#define DB_Z_INFO__READ_SIZE_MASK 0x10000000
+#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c
+#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000
+#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d
+#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000
+#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
+#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000
+#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f
+#define DB_STENCIL_INFO__FORMAT_MASK 0x1
+#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0
+#define DB_STENCIL_INFO__TILE_SPLIT_MASK 0xe000
+#define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0xd
+#define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x700000
+#define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x14
+#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
+#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
+#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000
+#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d
+#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000
+#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
+#define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x7ff
+#define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x0
+#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x3ff800
+#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0xb
+#define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x3fffff
+#define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x0
+#define DB_DEPTH_VIEW__SLICE_START_MASK 0x7ff
+#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0
+#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0xffe000
+#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd
+#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x1000000
+#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18
+#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x2000000
+#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19
+#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x1
+#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0
+#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x2
+#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1
+#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x4
+#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2
+#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x8
+#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3
+#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x10
+#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4
+#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x20
+#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5
+#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x40
+#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6
+#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x80
+#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7
+#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0xf00
+#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8
+#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x1000
+#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc
+#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x1
+#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0
+#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x2
+#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1
+#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x70
+#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4
+#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0xf00
+#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8
+#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0xf000
+#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc
+#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000
+#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10
+#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0xf00000
+#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14
+#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0xf000000
+#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18
+#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000
+#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c
+#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x3
+#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0xc
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x30
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4
+#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x40
+#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6
+#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x80
+#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7
+#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x100
+#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8
+#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x200
+#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9
+#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x400
+#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
+#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x800
+#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x1000
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc
+#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x6000
+#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd
+#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x8000
+#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf
+#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x10000
+#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10
+#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x20000
+#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11
+#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x40000
+#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12
+#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x180000
+#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13
+#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x3e00000
+#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15
+#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x4000000
+#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a
+#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x8000000
+#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c
+#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000
+#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e
+#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000
+#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x3
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x1c
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2
+#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x20
+#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5
+#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x40
+#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6
+#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x80
+#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7
+#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x100
+#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8
+#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x200
+#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9
+#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x400
+#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
+#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x800
+#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb
+#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x7000
+#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x38000
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x1c0000
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12
+#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x200000
+#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15
+#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x400000
+#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16
+#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x800000
+#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17
+#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x7
+#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0
+#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x70
+#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4
+#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x700
+#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8
+#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x7000
+#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc
+#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x10000
+#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10
+#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x20000
+#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11
+#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x40000
+#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12
+#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x80000
+#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13
+#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x100000
+#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14
+#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x200000
+#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15
+#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x7000000
+#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18
+#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x8000000
+#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b
+#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x1
+#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0
+#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x2
+#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1
+#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x4
+#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2
+#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x30
+#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4
+#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x40
+#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6
+#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x80
+#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7
+#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x100
+#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8
+#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x200
+#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9
+#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x400
+#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
+#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x800
+#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb
+#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x1000
+#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc
+#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x6000
+#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd
+#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffff
+#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0
+#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffff
+#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0
+#define DB_STENCIL_CLEAR__CLEAR_MASK 0xff
+#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0
+#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffff
+#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0
+#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffff
+#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0
+#define DB_HTILE_SURFACE__LINEAR_MASK 0x1
+#define DB_HTILE_SURFACE__LINEAR__SHIFT 0x0
+#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x2
+#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1
+#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x4
+#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2
+#define DB_HTILE_SURFACE__PRELOAD_MASK 0x8
+#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3
+#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x3f0
+#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4
+#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0xfc00
+#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa
+#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x10000
+#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10
+#define DB_HTILE_SURFACE__TC_COMPATIBLE_MASK 0x20000
+#define DB_HTILE_SURFACE__TC_COMPATIBLE__SHIFT 0x11
+#define DB_PRELOAD_CONTROL__START_X_MASK 0xff
+#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0
+#define DB_PRELOAD_CONTROL__START_Y_MASK 0xff00
+#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8
+#define DB_PRELOAD_CONTROL__MAX_X_MASK 0xff0000
+#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10
+#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000
+#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18
+#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0xff
+#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0
+#define DB_STENCILREFMASK__STENCILMASK_MASK 0xff00
+#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8
+#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0xff0000
+#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10
+#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000
+#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18
+#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0xff
+#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0
+#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0xff00
+#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8
+#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0xff0000
+#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10
+#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000
+#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x7
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0xff0
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0xff000
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc
+#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x1000000
+#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x7
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0xff0
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0xff000
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc
+#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x1000000
+#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18
+#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x1
+#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0
+#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x2
+#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1
+#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x4
+#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2
+#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x8
+#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3
+#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x70
+#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4
+#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x80
+#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7
+#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x700
+#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8
+#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x700000
+#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14
+#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000
+#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e
+#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000
+#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f
+#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0xf
+#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0
+#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0xf0
+#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4
+#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0xf00
+#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8
+#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0xf000
+#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc
+#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0xf0000
+#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10
+#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0xf00000
+#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x1
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x300
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0xc00
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x3000
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0xc000
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe
+#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x10000
+#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xf000000
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xf000000
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x1
+#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0
+#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x2
+#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1
+#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x4
+#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2
+#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x8
+#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3
+#define DB_DEBUG__FORCE_Z_MODE_MASK 0x30
+#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4
+#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x40
+#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6
+#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x80
+#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7
+#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x300
+#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0xc00
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x3000
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc
+#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x4000
+#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe
+#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x8000
+#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf
+#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x10000
+#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10
+#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x20000
+#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11
+#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x40000
+#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12
+#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x180000
+#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13
+#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x200000
+#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15
+#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x400000
+#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16
+#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x800000
+#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17
+#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0xf000000
+#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18
+#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000
+#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c
+#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000
+#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d
+#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000
+#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e
+#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000
+#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f
+#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x1
+#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0
+#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x2
+#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1
+#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x4
+#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2
+#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x8
+#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3
+#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x10
+#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
+#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x20
+#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x5
+#define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x40
+#define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x6
+#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x80
+#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x7
+#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x100
+#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x8
+#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x3e00
+#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9
+#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x4000
+#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe
+#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x8000
+#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf
+#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x10000
+#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10
+#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x20000
+#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11
+#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x40000
+#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12
+#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x80000
+#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13
+#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000
+#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c
+#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000
+#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d
+#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000
+#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e
+#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000
+#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f
+#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x4
+#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2
+#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x8
+#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3
+#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x10
+#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4
+#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x20
+#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5
+#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x40
+#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6
+#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x80
+#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7
+#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x100
+#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8
+#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x200
+#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9
+#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x400
+#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
+#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x800
+#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb
+#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x1000
+#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc
+#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x2000
+#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd
+#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x4000
+#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe
+#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x8000
+#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf
+#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x10000
+#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10
+#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x20000
+#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11
+#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x40000
+#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12
+#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x80000
+#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13
+#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x100000
+#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14
+#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x200000
+#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15
+#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x400000
+#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16
+#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x800000
+#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17
+#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x1000000
+#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18
+#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x2000000
+#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19
+#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x4000000
+#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a
+#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x8000000
+#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b
+#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000
+#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c
+#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000
+#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d
+#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000
+#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e
+#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000
+#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f
+#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x1
+#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0
+#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x2
+#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1
+#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x4
+#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2
+#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x8
+#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3
+#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xfffffff0
+#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x4
+#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x1f
+#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0
+#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x3e0
+#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5
+#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x1c00
+#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
+#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000
+#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18
+#define DB_WATERMARKS__DEPTH_FREE_MASK 0x1f
+#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0
+#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x7e0
+#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5
+#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x7800
+#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb
+#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0xf8000
+#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf
+#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x7f00000
+#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14
+#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x8000000
+#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x1b
+#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000
+#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x1c
+#define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000
+#define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x1d
+#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000
+#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e
+#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000
+#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f
+#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x3
+#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0
+#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0xc
+#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2
+#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x30
+#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4
+#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0xc0
+#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6
+#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x300
+#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8
+#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0xc00
+#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
+#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x3000
+#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc
+#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0xc000
+#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe
+#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x30000
+#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10
+#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0xc0000
+#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12
+#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x7f
+#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0
+#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x3f80
+#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7
+#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x1fc000
+#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe
+#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x1e00000
+#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x15
+#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000
+#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x19
+#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x1f
+#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0
+#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x3e0
+#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x5
+#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0xfc00
+#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa
+#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x1f0000
+#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10
+#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000
+#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15
+#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0xff
+#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0
+#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x7f00
+#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8
+#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x1ff8000
+#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf
+#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000
+#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19
+#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0xf
+#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0
+#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0xff0
+#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4
+#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0xfff000
+#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x1000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x2000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x4000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x8000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f
+#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffff
+#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffff
+#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0
+#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x3
+#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0
+#define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffff
+#define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x0
+#define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffff
+#define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x0
+#define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffff
+#define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x0
+#define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x0
+#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xffffffff
+#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7fffffff
+#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0
+#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xffffffff
+#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7fffffff
+#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0
+#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xffffffff
+#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7fffffff
+#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0
+#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xffffffff
+#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7fffffff
+#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0
+#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
+#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
+#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
+#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
+#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
+#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
+#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
+#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
+#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
+#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
+#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
+#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
+#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffff
+#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0
+#define GB_GPU_ID__GPU_ID_MASK 0xf
+#define GB_GPU_ID__GPU_ID__SHIFT 0x0
+#define CC_RB_DAISY_CHAIN__RB_0_MASK 0xf
+#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0
+#define CC_RB_DAISY_CHAIN__RB_1_MASK 0xf0
+#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4
+#define CC_RB_DAISY_CHAIN__RB_2_MASK 0xf00
+#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8
+#define CC_RB_DAISY_CHAIN__RB_3_MASK 0xf000
+#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc
+#define CC_RB_DAISY_CHAIN__RB_4_MASK 0xf0000
+#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10
+#define CC_RB_DAISY_CHAIN__RB_5_MASK 0xf00000
+#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14
+#define CC_RB_DAISY_CHAIN__RB_6_MASK 0xf000000
+#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18
+#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000
+#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c
+#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6
+#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x10000
+#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x10
+#define GB_EDC_MODE__DED_MODE_MASK 0x300000
+#define GB_EDC_MODE__DED_MODE__SHIFT 0x14
+#define GB_EDC_MODE__PROP_FED_MASK 0x20000000
+#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d
+#define GB_EDC_MODE__BYPASS_MASK 0x80000000
+#define GB_EDC_MODE__BYPASS__SHIFT 0x1f
+#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x2
+#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x1
+#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0
+#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffff
+#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0
+#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffff
+#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0
+#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffff
+#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0
+#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffff
+#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0
+#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0
+#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffff
+#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0
+#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffff
+#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0
+#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffff
+#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0
+#define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xffffffff
+#define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x0
+#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x7
+#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0
+#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x7
+#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
+#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0xffff
+#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0
+#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
+#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
+#define GRBM_CAM_DATA__CAM_ADDR_MASK 0xffff
+#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
+#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
+#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
+#define GRBM_CNTL__READ_TIMEOUT_MASK 0xff
+#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
+#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000
+#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f
+#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x3f
+#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
+#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0xfc0
+#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6
+#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x3
+#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0
+#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0xc
+#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2
+#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x30
+#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4
+#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0xc0
+#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6
+#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x4000
+#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe
+#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x8000
+#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf
+#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0xf
+#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0
+#define GRBM_STATUS__SRBM_RQ_PENDING_MASK 0x20
+#define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT 0x5
+#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x80
+#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7
+#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x100
+#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8
+#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x200
+#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9
+#define GRBM_STATUS__DB_CLEAN_MASK 0x1000
+#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc
+#define GRBM_STATUS__CB_CLEAN_MASK 0x2000
+#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd
+#define GRBM_STATUS__TA_BUSY_MASK 0x4000
+#define GRBM_STATUS__TA_BUSY__SHIFT 0xe
+#define GRBM_STATUS__GDS_BUSY_MASK 0x8000
+#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf
+#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x10000
+#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10
+#define GRBM_STATUS__VGT_BUSY_MASK 0x20000
+#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11
+#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x40000
+#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12
+#define GRBM_STATUS__IA_BUSY_MASK 0x80000
+#define GRBM_STATUS__IA_BUSY__SHIFT 0x13
+#define GRBM_STATUS__SX_BUSY_MASK 0x100000
+#define GRBM_STATUS__SX_BUSY__SHIFT 0x14
+#define GRBM_STATUS__WD_BUSY_MASK 0x200000
+#define GRBM_STATUS__WD_BUSY__SHIFT 0x15
+#define GRBM_STATUS__SPI_BUSY_MASK 0x400000
+#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16
+#define GRBM_STATUS__BCI_BUSY_MASK 0x800000
+#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17
+#define GRBM_STATUS__SC_BUSY_MASK 0x1000000
+#define GRBM_STATUS__SC_BUSY__SHIFT 0x18
+#define GRBM_STATUS__PA_BUSY_MASK 0x2000000
+#define GRBM_STATUS__PA_BUSY__SHIFT 0x19
+#define GRBM_STATUS__DB_BUSY_MASK 0x4000000
+#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a
+#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000
+#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c
+#define GRBM_STATUS__CP_BUSY_MASK 0x20000000
+#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d
+#define GRBM_STATUS__CB_BUSY_MASK 0x40000000
+#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000
+#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f
+#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0xf
+#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
+#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x10
+#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
+#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x20
+#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5
+#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x40
+#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6
+#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x80
+#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7
+#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x100
+#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8
+#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x200
+#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9
+#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x400
+#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
+#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x800
+#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb
+#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x1000
+#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc
+#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x2000
+#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd
+#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x4000
+#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe
+#define GRBM_STATUS2__RLC_BUSY_MASK 0x1000000
+#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18
+#define GRBM_STATUS2__TC_BUSY_MASK 0x2000000
+#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19
+#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x4000000
+#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a
+#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000
+#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c
+#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000
+#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000
+#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x2
+#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x4
+#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x400000
+#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x800000
+#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17
+#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x1000000
+#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x2000000
+#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x4000000
+#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x8000000
+#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000
+#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000
+#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000
+#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f
+#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x2
+#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x4
+#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x400000
+#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x800000
+#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17
+#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x1000000
+#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x2000000
+#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x4000000
+#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x8000000
+#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000
+#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000
+#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000
+#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f
+#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x2
+#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x4
+#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x400000
+#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x800000
+#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17
+#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x1000000
+#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x2000000
+#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x4000000
+#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x8000000
+#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000
+#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000
+#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000
+#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f
+#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x2
+#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x4
+#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x400000
+#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x800000
+#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17
+#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x1000000
+#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x2000000
+#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x4000000
+#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x8000000
+#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000
+#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000
+#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000
+#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f
+#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x1
+#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0
+#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x4
+#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2
+#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x10000
+#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10
+#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x20000
+#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11
+#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x40000
+#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12
+#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x80000
+#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13
+#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x100000
+#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14
+#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x3f
+#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x0
+#define GRBM_DEBUG_DATA__DATA_MASK 0xffffffff
+#define GRBM_DEBUG_DATA__DATA__SHIFT 0x0
+#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0xff
+#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0
+#define GRBM_GFX_INDEX__SH_INDEX_MASK 0xff00
+#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8
+#define GRBM_GFX_INDEX__SE_INDEX_MASK 0xff0000
+#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10
+#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000
+#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d
+#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000
+#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
+#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000
+#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f
+#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0xff
+#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0
+#define GRBM_DEBUG__IGNORE_RDY_MASK 0x2
+#define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x1
+#define GRBM_DEBUG__IGNORE_FAO_MASK 0x20
+#define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x5
+#define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x40
+#define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x6
+#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x80
+#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x7
+#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0xf00
+#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x8
+#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x1000
+#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xc
+#define GRBM_DEBUG__GRBM_TRAP_ENABLE_MASK 0x2000
+#define GRBM_DEBUG__GRBM_TRAP_ENABLE__SHIFT 0xd
+#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN_MASK 0x80000000
+#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN__SHIFT 0x1f
+#define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK 0x1
+#define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT 0x0
+#define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK 0x2
+#define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT 0x1
+#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK 0x4
+#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT 0x2
+#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK 0x8
+#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT 0x3
+#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK 0x10
+#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT 0x4
+#define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK 0x20
+#define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT 0x5
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK 0x40
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT 0x6
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK 0x80
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT 0x7
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK 0x100
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT 0x8
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK 0x200
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT 0x9
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK 0x400
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT 0xa
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK 0x800
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT 0xb
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK 0x1000
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT 0xc
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK 0x2000
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT 0xd
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK 0x4000
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT 0xe
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK 0x8000
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT 0xf
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK 0x10000
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT 0x10
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK 0x20000
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT 0x11
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK 0x40000
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT 0x12
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK 0x80000
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT 0x13
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK 0x100000
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x14
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK 0x200000
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT 0x15
+#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc
+#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
+#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x300000
+#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14
+#define GRBM_READ_ERROR__READ_MEID_MASK 0xc00000
+#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16
+#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000
+#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
+#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK 0x20000
+#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT 0x11
+#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x40000
+#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12
+#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x80000
+#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x100000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x200000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x400000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x800000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x1000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x2000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x4000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x8000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f
+#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x1
+#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0
+#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x80000
+#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13
+#define GRBM_TRAP_OP__RW_MASK 0x1
+#define GRBM_TRAP_OP__RW__SHIFT 0x0
+#define GRBM_TRAP_ADDR__DATA_MASK 0xffff
+#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0
+#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0xffff
+#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0
+#define GRBM_TRAP_WD__DATA_MASK 0xffffffff
+#define GRBM_TRAP_WD__DATA__SHIFT 0x0
+#define GRBM_TRAP_WD_MSK__DATA_MASK 0xffffffff
+#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0
+#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x3
+#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0
+#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x4
+#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2
+#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x1
+#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0
+#define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM_MASK 0x2
+#define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM__SHIFT 0x1
+#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x1c
+#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2
+#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x1e0
+#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5
+#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x1000
+#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc
+#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x1e000
+#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd
+#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x300000
+#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14
+#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0xc00000
+#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16
+#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000
+#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f
+#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
+#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
+#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
+#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000
+#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000
+#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000
+#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
+#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000
+#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000
+#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000
+#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000
+#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000
+#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000
+#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000
+#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000
+#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
+#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000
+#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
+#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000
+#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
+#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000
+#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
+#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000
+#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
+#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000
+#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
+#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
+#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
+#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
+#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000
+#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000
+#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000
+#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
+#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000
+#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000
+#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000
+#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000
+#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000
+#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000
+#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000
+#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000
+#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
+#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000
+#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
+#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000
+#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
+#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000
+#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
+#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000
+#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
+#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000
+#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
+#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
+#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
+#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
+#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
+#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
+#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
+#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
+#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
+#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
+#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
+#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
+#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
+#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
+#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
+#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
+#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
+#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
+#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
+#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
+#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
+#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
+#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
+#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
+#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
+#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
+#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
+#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
+#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
+#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
+#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
+#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
+#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
+#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
+#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
+#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
+#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
+#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
+#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
+#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
+#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
+#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
+#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
+#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
+#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
+#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
+#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
+#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
+#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
+#define DEBUG_INDEX__DEBUG_INDEX_MASK 0x3ffff
+#define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x0
+#define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffff
+#define DEBUG_DATA__DEBUG_DATA__SHIFT 0x0
+#define GRBM_NOWHERE__DATA_MASK 0xffffffff
+#define GRBM_NOWHERE__DATA__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x1
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x2
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x4
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x8
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x10
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x20
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5
+#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x100
+#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8
+#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x200
+#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9
+#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x400
+#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x800
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x1
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x2
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x4
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x8
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x10
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x20
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x40
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x80
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x100
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x200
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x400
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x800
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x1000
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x2000
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x4000
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x8000
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf
+#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x10000
+#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10
+#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x20000
+#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11
+#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x40000
+#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12
+#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x80000
+#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13
+#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x100000
+#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x200000
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x400000
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x800000
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x1000000
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18
+#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x2000000
+#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19
+#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x4000000
+#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a
+#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x1
+#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0
+#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x2
+#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1
+#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x4
+#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2
+#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x8
+#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3
+#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x10
+#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4
+#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x20
+#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5
+#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x40
+#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6
+#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x80
+#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7
+#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x100
+#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8
+#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x200
+#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9
+#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x400
+#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa
+#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x800
+#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb
+#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x1000
+#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc
+#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x2000
+#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd
+#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x4000
+#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe
+#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x100000
+#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14
+#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1
+#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0
+#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x2
+#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1
+#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x4
+#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2
+#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x8
+#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3
+#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x10
+#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4
+#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20
+#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5
+#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x2000
+#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd
+#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0xc000
+#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x10000
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10
+#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x20000
+#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x40000
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x80000
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x100000
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x200000
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15
+#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x400000
+#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16
+#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x1000000
+#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18
+#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x2000000
+#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19
+#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x4000000
+#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a
+#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x8000000
+#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x1
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0
+#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x6
+#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1
+#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x8
+#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3
+#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x10
+#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4
+#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x20
+#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5
+#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000
+#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c
+#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000
+#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d
+#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000
+#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e
+#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000
+#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f
+#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x1
+#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0
+#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x1
+#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0
+#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x6
+#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1
+#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x38
+#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3
+#define PA_SU_POINT_SIZE__HEIGHT_MASK 0xffff
+#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0
+#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000
+#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10
+#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0xffff
+#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0
+#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000
+#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10
+#define PA_SU_LINE_CNTL__WIDTH_MASK 0xffff
+#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0
+#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x3
+#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0
+#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x4
+#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2
+#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x8
+#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3
+#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x10
+#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4
+#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffff
+#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x1
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0
+#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x2
+#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1
+#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x4
+#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x8
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x10
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4
+#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x20
+#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5
+#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x40
+#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x80
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7
+#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0xff00
+#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8
+#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000
+#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e
+#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000
+#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x1
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0
+#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x2
+#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1
+#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x4
+#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2
+#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x18
+#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0xe0
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x700
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x800
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x1000
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x2000
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x10000
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x80000
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x100000
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x200000
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0xff
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x100
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8
+#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffff
+#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffff
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffff
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffff
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffff
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x1ff
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x1ff0000
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10
+#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0xffffff
+#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffff
+#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffff
+#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffff
+#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffff
+#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x7
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0
+#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x10
+#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x1e000
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd
+#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x700000
+#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14
+#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x3000000
+#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0xffff
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0xffff
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0xf
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0xf0
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0xf00
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0xf000
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0xf0000
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0xf00000
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0xf000000
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0xf
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0xf0
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0xf00
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0xf000
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0xf0000
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0xf00000
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0xf000000
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c
+#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0xffff
+#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0
+#define PA_SC_EDGERULE__ER_TRI_MASK 0xf
+#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0
+#define PA_SC_EDGERULE__ER_POINT_MASK 0xf0
+#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4
+#define PA_SC_EDGERULE__ER_RECT_MASK 0xf00
+#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8
+#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x3f000
+#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc
+#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0xfc0000
+#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12
+#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0xf000000
+#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18
+#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000
+#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x200
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9
+#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x400
+#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa
+#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x800
+#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb
+#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x1000
+#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0xffff
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0xff0000
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d
+#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x1
+#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0
+#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x2
+#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1
+#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x4
+#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2
+#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x8
+#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3
+#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x1
+#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0
+#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x2
+#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1
+#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x4
+#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x8
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x70
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4
+#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x80
+#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7
+#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x100
+#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8
+#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x200
+#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9
+#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x400
+#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x800
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x1000
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc
+#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x2000
+#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x4000
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x8000
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf
+#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x10000
+#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10
+#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x20000
+#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x40000
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x80000
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0xf00000
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x1000000
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x2000000
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x4000000
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x8000000
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x3
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0xc
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2
+#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x30
+#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4
+#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x40
+#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6
+#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x80
+#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7
+#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x300
+#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8
+#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0xc00
+#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa
+#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x3000
+#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc
+#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0xc000
+#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe
+#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x30000
+#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10
+#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0xc0000
+#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12
+#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x300000
+#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14
+#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x3000000
+#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18
+#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0xc000000
+#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a
+#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000
+#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x3
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0xc
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x30
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x3
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0xc
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2
+#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x7fff
+#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0
+#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10
+#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x7fff
+#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0
+#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0xffff
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0xffff
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0xffff
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x7fff
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x7fff
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x1
+#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0
+#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x2
+#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1
+#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x4
+#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x8
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x10
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4
+#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x20
+#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5
+#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK 0xc0
+#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT 0x6
+#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x100
+#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x8
+#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x200
+#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x9
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0xa
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x800
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0xb
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x1000
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xc
+#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x2000
+#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xd
+#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x4000
+#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xe
+#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x8000
+#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xf
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x10000
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0x10
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x20000
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0x11
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x40000
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x12
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x80000
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x13
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x100000
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x14
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x200000
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x15
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x400000
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x16
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x800000
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x17
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x1000000
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x18
+#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x2000000
+#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x19
+#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x4000000
+#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x1a
+#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x8000000
+#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x1b
+#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x10000000
+#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1c
+#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x20000000
+#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1d
+#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000
+#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x1e
+#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000
+#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x1f
+#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x3f
+#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0
+#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x7fc0
+#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6
+#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x1f8000
+#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf
+#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xff800000
+#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x17
+#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x3f
+#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0
+#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0xfc0
+#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6
+#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x3f000
+#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc
+#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0xfc0000
+#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0xffff
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0xf
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0xff00
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8
+#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0xffff
+#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xffff0000
+#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10
+#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0xffff
+#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xffff0000
+#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10
+#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0xffff
+#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xffff0000
+#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10
+#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0xffff
+#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xffff0000
+#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
+#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
+#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
+#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
+#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
+#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
+#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
+#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
+#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
+#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
+#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
+#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
+#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
+#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
+#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
+#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
+#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
+#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
+#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
+#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
+#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
+#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000
+#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f
+#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000
+#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f
+#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x3ff
+#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0
+#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000
+#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d
+#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000
+#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e
+#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000
+#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f
+#define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x1f
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x0
+#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffff
+#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x0
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x3f
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x0
+#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffff
+#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x0
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xff
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x0
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x100
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x8
+#define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x600
+#define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x9
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x800
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0xb
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x1000
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0xc
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x2000
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0xd
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x4000
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0xe
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x8000
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0xf
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x10000
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x10
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x20000
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x11
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x40000
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x12
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x80000
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x13
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x100000
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x14
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x200000
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x15
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x400000
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x16
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x800000
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x17
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x1000000
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x18
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x2000000
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x19
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x4000000
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x1a
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x8000000
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x0
+#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x700
+#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x8
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x3800
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0xb
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x1c000
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0xe
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0xe0000
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x11
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x100000
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x14
+#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x200000
+#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x15
+#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x400000
+#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x16
+#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x800000
+#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x17
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x1000000
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x18
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x2000000
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x19
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0xc000000
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x1a
+#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000
+#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000
+#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000
+#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000
+#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x7
+#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x0
+#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x38
+#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x3
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0xc0
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x6
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0xf00
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x8
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0xf000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0xc
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0xf0000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x10
+#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x100000
+#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x14
+#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x200000
+#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x15
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x400000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x16
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x800000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x17
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x1000000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x18
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x2000000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x19
+#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x4000000
+#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x1a
+#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x8000000
+#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000
+#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000
+#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x3fff
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x0
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0xfc000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0xe
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x700000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x14
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x800000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x17
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x7000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x18
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x3fff
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x0
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0xfc000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0xe
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x700000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x14
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x800000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x17
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x7000000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x18
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x3fff
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x0
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0xfc000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0xe
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x700000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x14
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x800000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x17
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x7000000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x18
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x3fff
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x0
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0xfc000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0xe
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x700000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x14
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x800000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x17
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x7000000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x18
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x1
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x0
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x2
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x1
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x4
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x2
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x8
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x3
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x10
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x4
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x20
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x5
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x40
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x6
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x80
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x7
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x8
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf000
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0xc
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf0000
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x10
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00000
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x14
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x1000000
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x18
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x2000000
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x19
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x4000000
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x1a
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x8000000
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000
+#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000
+#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000
+#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000
+#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0xff
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x0
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x1f00
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x8
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x3e000
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0xd
+#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0xc0000
+#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x12
+#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x300000
+#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x14
+#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0xc00000
+#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x16
+#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x1000000
+#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x18
+#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x2000000
+#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x19
+#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x4000000
+#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x1a
+#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x8000000
+#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000
+#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000
+#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x7
+#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x0
+#define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x8
+#define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x3
+#define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x10
+#define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x4
+#define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x20
+#define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x5
+#define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x40
+#define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x6
+#define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x80
+#define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x7
+#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0xf00
+#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x8
+#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x3000
+#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0xc
+#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x4000
+#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0xe
+#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x8000
+#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0xf
+#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x10000
+#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x10
+#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x1e0000
+#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x11
+#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x600000
+#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x15
+#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x800000
+#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x17
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x18
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x3f
+#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x0
+#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0xfc0
+#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x6
+#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x3f000
+#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0xc
+#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x40000
+#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x12
+#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x80000
+#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x13
+#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x100000
+#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x14
+#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0xe00000
+#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x15
+#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000
+#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x18
+#define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000
+#define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0xffff
+#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x0
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x1f0000
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x10
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x3e00000
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x15
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x1a
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x7f
+#define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x0
+#define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x80
+#define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x7
+#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x1f00
+#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x8
+#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x3e000
+#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0xd
+#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x40000
+#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x12
+#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x80000
+#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x13
+#define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x7f00000
+#define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x14
+#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
+#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000
+#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000
+#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000
+#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x7f
+#define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x0
+#define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x80
+#define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x7
+#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x1f00
+#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x8
+#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x3e000
+#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0xd
+#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x40000
+#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x12
+#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x80000
+#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x13
+#define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x7f00000
+#define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x14
+#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
+#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000
+#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000
+#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000
+#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x7f
+#define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x0
+#define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x80
+#define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x7
+#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x1f00
+#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x8
+#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x3e000
+#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0xd
+#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x40000
+#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x12
+#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x80000
+#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x13
+#define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x7f00000
+#define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x14
+#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
+#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000
+#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000
+#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000
+#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x7f
+#define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x0
+#define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x80
+#define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x7
+#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x1f00
+#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x8
+#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x3e000
+#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0xd
+#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x40000
+#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x12
+#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x80000
+#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x13
+#define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x7f00000
+#define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x14
+#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
+#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000
+#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000
+#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000
+#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x3f
+#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x0
+#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x1c0
+#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x6
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0xe00
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x9
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0xf000
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0xc
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3ff0000
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x10
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0xc000000
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x1a
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x1c
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x1e
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x1f
+#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x7f
+#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x0
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x380
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x7
+#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x7c00
+#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0xa
+#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x8000
+#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0xf
+#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0xf0000
+#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x10
+#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x300000
+#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x14
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x400000
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x16
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x800000
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x17
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0xf000000
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x18
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x1c
+#define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x7f
+#define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x0
+#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x180
+#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x7
+#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x7e00
+#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x9
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x8000
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0xf
+#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x7f0000
+#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x10
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x3800000
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x17
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x1a
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0xff
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x0
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0xf00
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x8
+#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x1000
+#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0xc
+#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x2000
+#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0xd
+#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x1fc000
+#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0xe
+#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x600000
+#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x15
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x800000
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x17
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x1000000
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x18
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x2000000
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x19
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x4000000
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x1a
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x8000000
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x1b
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x1c
+#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000
+#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x1d
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x1e
+#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000
+#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x1f
+#define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x3
+#define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x0
+#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x3c
+#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x2
+#define SETUP_DEBUG_REG0__pmode_state_MASK 0x3f00
+#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x8
+#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x4000
+#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0xe
+#define SETUP_DEBUG_REG0__geom_enable_MASK 0x8000
+#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0xf
+#define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x30000
+#define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x10
+#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x40000
+#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x12
+#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x80000
+#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x13
+#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x100000
+#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x14
+#define SETUP_DEBUG_REG0__geom_busy_MASK 0x200000
+#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x15
+#define SETUP_DEBUG_REG0__event_id_gated_MASK 0xfc00000
+#define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x16
+#define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000
+#define SETUP_DEBUG_REG0__event_gated__SHIFT 0x1c
+#define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000
+#define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x1d
+#define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000
+#define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x1e
+#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000
+#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x1f
+#define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0xffff
+#define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x0
+#define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000
+#define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x10
+#define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0xffff
+#define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x0
+#define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000
+#define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x10
+#define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0xffff
+#define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x0
+#define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000
+#define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x10
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x3fff
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x0
+#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x4000
+#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0xe
+#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x8000
+#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0xf
+#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x70000
+#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x10
+#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x80000
+#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x13
+#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x700000
+#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x14
+#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x800000
+#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x17
+#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x3000000
+#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x18
+#define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000
+#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x1a
+#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000
+#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x1d
+#define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000
+#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x1f
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x3fff
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x0
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0xfffc000
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0xe
+#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000
+#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x1c
+#define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000
+#define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x1e
+#define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000
+#define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x1f
+#define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x3
+#define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x0
+#define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0xc
+#define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x2
+#define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x3
+#define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x0
+#define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0xc
+#define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x2
+#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x1
+#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0
+#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x2
+#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1
+#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x4
+#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x8
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x10
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4
+#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x20
+#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5
+#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x40
+#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6
+#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x380
+#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x7
+#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x400
+#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa
+#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x800
+#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb
+#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x1000
+#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0xc
+#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x4000
+#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe
+#define COMPUTE_DIM_X__SIZE_MASK 0xffffffff
+#define COMPUTE_DIM_X__SIZE__SHIFT 0x0
+#define COMPUTE_DIM_Y__SIZE_MASK 0xffffffff
+#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0
+#define COMPUTE_DIM_Z__SIZE_MASK 0xffffffff
+#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0
+#define COMPUTE_START_X__START_MASK 0xffffffff
+#define COMPUTE_START_X__START__SHIFT 0x0
+#define COMPUTE_START_Y__START_MASK 0xffffffff
+#define COMPUTE_START_Y__START__SHIFT 0x0
+#define COMPUTE_START_Z__START_MASK 0xffffffff
+#define COMPUTE_START_Z__START__SHIFT 0x0
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0xffff
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0xffff
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0xffff
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10
+#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x1
+#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0
+#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x1
+#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0
+#define COMPUTE_PGM_LO__DATA_MASK 0xffffffff
+#define COMPUTE_PGM_LO__DATA__SHIFT 0x0
+#define COMPUTE_PGM_HI__DATA_MASK 0xff
+#define COMPUTE_PGM_HI__DATA__SHIFT 0x0
+#define COMPUTE_PGM_HI__INST_ATC_MASK 0x100
+#define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x8
+#define COMPUTE_TBA_LO__DATA_MASK 0xffffffff
+#define COMPUTE_TBA_LO__DATA__SHIFT 0x0
+#define COMPUTE_TBA_HI__DATA_MASK 0xff
+#define COMPUTE_TBA_HI__DATA__SHIFT 0x0
+#define COMPUTE_TMA_LO__DATA_MASK 0xffffffff
+#define COMPUTE_TMA_LO__DATA__SHIFT 0x0
+#define COMPUTE_TMA_HI__DATA_MASK 0xff
+#define COMPUTE_TMA_HI__DATA__SHIFT 0x0
+#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x3f
+#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0
+#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x3c0
+#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6
+#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0xc00
+#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa
+#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0xff000
+#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc
+#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x100000
+#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14
+#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x200000
+#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15
+#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x400000
+#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16
+#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x800000
+#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17
+#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x1000000
+#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18
+#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x2000000
+#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19
+#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x1
+#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0
+#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x3e
+#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1
+#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x40
+#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6
+#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x80
+#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7
+#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x100
+#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8
+#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x200
+#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9
+#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x400
+#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa
+#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x1800
+#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb
+#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x6000
+#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd
+#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0xff8000
+#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf
+#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000
+#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18
+#define COMPUTE_VMID__DATA_MASK 0xf
+#define COMPUTE_VMID__DATA__SHIFT 0x0
+#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x3ff
+#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0
+#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0xf000
+#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc
+#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x3f0000
+#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10
+#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x400000
+#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16
+#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x800000
+#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17
+#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x7000000
+#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0xffff
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0xffff
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0xfff
+#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0
+#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000
+#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0xffff
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xffff0000
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0xffff
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xffff0000
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_RESTART_X__RESTART_MASK 0xffffffff
+#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0
+#define COMPUTE_RESTART_Y__RESTART_MASK 0xffffffff
+#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0
+#define COMPUTE_RESTART_Z__RESTART_MASK 0xffffffff
+#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0
+#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x1
+#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0
+#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x3
+#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0
+#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x4
+#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2
+#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x8
+#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3
+#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x10
+#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4
+#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x1ffe0
+#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5
+#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xffffffff
+#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0
+#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xffffffff
+#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0
+#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3fffffff
+#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0
+#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000
+#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e
+#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000
+#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f
+#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xffffffff
+#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0
+#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xffff
+#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0
+#define COMPUTE_WAVE_RESTORE_CONTROL__ATC_MASK 0x1
+#define COMPUTE_WAVE_RESTORE_CONTROL__ATC__SHIFT 0x0
+#define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE_MASK 0x6
+#define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE__SHIFT 0x1
+#define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0
+#define COMPUTE_NOWHERE__DATA_MASK 0xffffffff
+#define COMPUTE_NOWHERE__DATA__SHIFT 0x0
+#define CSPRIV_CONNECT__DOORBELL_OFFSET_MASK 0x1fffff
+#define CSPRIV_CONNECT__DOORBELL_OFFSET__SHIFT 0x0
+#define CSPRIV_CONNECT__QUEUE_ID_MASK 0xe00000
+#define CSPRIV_CONNECT__QUEUE_ID__SHIFT 0x15
+#define CSPRIV_CONNECT__VMID_MASK 0x3c000000
+#define CSPRIV_CONNECT__VMID__SHIFT 0x1a
+#define CSPRIV_CONNECT__UNORD_DISP_MASK 0x80000000
+#define CSPRIV_CONNECT__UNORD_DISP__SHIFT 0x1f
+#define CSPRIV_THREAD_TRACE_TG0__TGID_X_MASK 0xffffffff
+#define CSPRIV_THREAD_TRACE_TG0__TGID_X__SHIFT 0x0
+#define CSPRIV_THREAD_TRACE_TG1__TGID_Y_MASK 0xffffffff
+#define CSPRIV_THREAD_TRACE_TG1__TGID_Y__SHIFT 0x0
+#define CSPRIV_THREAD_TRACE_TG2__TGID_Z_MASK 0xffffffff
+#define CSPRIV_THREAD_TRACE_TG2__TGID_Z__SHIFT 0x0
+#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE_MASK 0xfff
+#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE__SHIFT 0x0
+#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP_MASK 0xfff000
+#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP__SHIFT 0xc
+#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG_MASK 0x1000000
+#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG__SHIFT 0x18
+#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG_MASK 0x2000000
+#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG__SHIFT 0x19
+#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG_MASK 0x4000000
+#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG__SHIFT 0x1a
+#define CSPRIV_THREAD_TRACE_TG3__LAST_TG_MASK 0x8000000
+#define CSPRIV_THREAD_TRACE_TG3__LAST_TG__SHIFT 0x1b
+#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG_MASK 0x10000000
+#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG__SHIFT 0x1c
+#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID_MASK 0x1f
+#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID__SHIFT 0x0
+#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1
+#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0
+#define RLC_CNTL__FORCE_RETRY_MASK 0x2
+#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1
+#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x4
+#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2
+#define RLC_CNTL__RLC_STEP_F32_MASK 0x8
+#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3
+#define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK 0x10
+#define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT 0x4
+#define RLC_CNTL__RESERVED_MASK 0xffffff00
+#define RLC_CNTL__RESERVED__SHIFT 0x8
+#define RLC_DEBUG_SELECT__SELECT_MASK 0xff
+#define RLC_DEBUG_SELECT__SELECT__SHIFT 0x0
+#define RLC_DEBUG_SELECT__RESERVED_MASK 0xffffff00
+#define RLC_DEBUG_SELECT__RESERVED__SHIFT 0x8
+#define RLC_DEBUG__DATA_MASK 0xffffffff
+#define RLC_DEBUG__DATA__SHIFT 0x0
+#define RLC_MC_CNTL__WRREQ_SWAP_MASK 0x3
+#define RLC_MC_CNTL__WRREQ_SWAP__SHIFT 0x0
+#define RLC_MC_CNTL__WRREQ_TRAN_MASK 0x4
+#define RLC_MC_CNTL__WRREQ_TRAN__SHIFT 0x2
+#define RLC_MC_CNTL__WRREQ_PRIV_MASK 0x8
+#define RLC_MC_CNTL__WRREQ_PRIV__SHIFT 0x3
+#define RLC_MC_CNTL__WRNFO_STALL_MASK 0x10
+#define RLC_MC_CNTL__WRNFO_STALL__SHIFT 0x4
+#define RLC_MC_CNTL__WRNFO_URG_MASK 0x1e0
+#define RLC_MC_CNTL__WRNFO_URG__SHIFT 0x5
+#define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK 0x1e00
+#define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT 0x9
+#define RLC_MC_CNTL__RESERVED_B_MASK 0xfe000
+#define RLC_MC_CNTL__RESERVED_B__SHIFT 0xd
+#define RLC_MC_CNTL__RDNFO_URG_MASK 0xf00000
+#define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x14
+#define RLC_MC_CNTL__RDREQ_SWAP_MASK 0x3000000
+#define RLC_MC_CNTL__RDREQ_SWAP__SHIFT 0x18
+#define RLC_MC_CNTL__RDREQ_TRAN_MASK 0x4000000
+#define RLC_MC_CNTL__RDREQ_TRAN__SHIFT 0x1a
+#define RLC_MC_CNTL__RDREQ_PRIV_MASK 0x8000000
+#define RLC_MC_CNTL__RDREQ_PRIV__SHIFT 0x1b
+#define RLC_MC_CNTL__RDNFO_STALL_MASK 0x10000000
+#define RLC_MC_CNTL__RDNFO_STALL__SHIFT 0x1c
+#define RLC_MC_CNTL__RESERVED_MASK 0xe0000000
+#define RLC_MC_CNTL__RESERVED__SHIFT 0x1d
+#define RLC_STAT__RLC_BUSY_MASK 0x1
+#define RLC_STAT__RLC_BUSY__SHIFT 0x0
+#define RLC_STAT__RLC_GPM_BUSY_MASK 0x2
+#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1
+#define RLC_STAT__RLC_SPM_BUSY_MASK 0x4
+#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2
+#define RLC_STAT__RESERVED_MASK 0xfffffff8
+#define RLC_STAT__RESERVED__SHIFT 0x3
+#define RLC_SAFE_MODE__CMD_MASK 0x1
+#define RLC_SAFE_MODE__CMD__SHIFT 0x0
+#define RLC_SAFE_MODE__MESSAGE_MASK 0x1e
+#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1
+#define RLC_SAFE_MODE__RESERVED1_MASK 0xe0
+#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5
+#define RLC_SAFE_MODE__RESPONSE_MASK 0xf00
+#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8
+#define RLC_SAFE_MODE__RESERVED_MASK 0xfffff000
+#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc
+#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU_MASK 0x1
+#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU__SHIFT 0x0
+#define RLC_SOFT_RESET_GPU__RESERVED_MASK 0xfffffffe
+#define RLC_SOFT_RESET_GPU__RESERVED__SHIFT 0x1
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0
+#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x2
+#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1
+#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x7c
+#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
+#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x80
+#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0xff00
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0xff0000
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10
+#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
+#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
+#define SMU_RLC_RESPONSE__RESP_MASK 0xffffffff
+#define SMU_RLC_RESPONSE__RESP__SHIFT 0x0
+#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x1
+#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0
+#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x1e
+#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1
+#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0xe0
+#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5
+#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0xf00
+#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8
+#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xfffff000
+#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc
+#define RLC_SMU_SAFE_MODE__CMD_MASK 0x1
+#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0
+#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x1e
+#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1
+#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0xe0
+#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5
+#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0xf00
+#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8
+#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xfffff000
+#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc
+#define RLC_RLCV_COMMAND__CMD_MASK 0xf
+#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0
+#define RLC_RLCV_COMMAND__RESERVED_MASK 0xfffffff0
+#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4
+#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x1
+#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0
+#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x7
+#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
+#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
+#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0xff
+#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0xff
+#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x1
+#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0
+#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x2
+#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1
+#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x4
+#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2
+#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x8
+#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3
+#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0xff0
+#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4
+#define RLC_LB_CNTL__RESERVED_MASK 0xfffff000
+#define RLC_LB_CNTL__RESERVED__SHIFT 0xc
+#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffff
+#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0
+#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffff
+#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0
+#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffff
+#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0
+#define RLC_SAVE_AND_RESTORE_BASE__BASE_MASK 0xffffffff
+#define RLC_SAVE_AND_RESTORE_BASE__BASE__SHIFT 0x0
+#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xffffffff
+#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0
+#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST_MASK 0x1
+#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST__SHIFT 0x0
+#define RLC_DRIVER_CPDMA_STATUS__RESERVED1_MASK 0xe
+#define RLC_DRIVER_CPDMA_STATUS__RESERVED1__SHIFT 0x1
+#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK_MASK 0x10
+#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK__SHIFT 0x4
+#define RLC_DRIVER_CPDMA_STATUS__RESERVED_MASK 0xffffffe0
+#define RLC_DRIVER_CPDMA_STATUS__RESERVED__SHIFT 0x5
+#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0xff
+#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0
+#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0xff00
+#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8
+#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xffff0000
+#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10
+#define RLC_GPM_DEBUG_SELECT__SELECT_MASK 0xff
+#define RLC_GPM_DEBUG_SELECT__SELECT__SHIFT 0x0
+#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT_MASK 0x300
+#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT__SHIFT 0x8
+#define RLC_GPM_DEBUG_SELECT__RESERVED_MASK 0xfffffc00
+#define RLC_GPM_DEBUG_SELECT__RESERVED__SHIFT 0xa
+#define RLC_GPM_DEBUG__DATA_MASK 0xffffffff
+#define RLC_GPM_DEBUG__DATA__SHIFT 0x0
+#define RLC_HYP_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
+#define RLC_HYP_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define RLC_HYP_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000
+#define RLC_HYP_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc
+#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
+#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000
+#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc
+#define RLC_HYP_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
+#define RLC_HYP_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
+#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define GPU_BIST_CONTROL__STOP_ON_FAIL_HW_MASK 0x1
+#define GPU_BIST_CONTROL__STOP_ON_FAIL_HW__SHIFT 0x0
+#define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV_MASK 0x2
+#define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV__SHIFT 0x1
+#define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT_MASK 0x3c
+#define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT__SHIFT 0x2
+#define GPU_BIST_CONTROL__RESERVED_MASK 0xffff80
+#define GPU_BIST_CONTROL__RESERVED__SHIFT 0x7
+#define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT_MASK 0xff000000
+#define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT__SHIFT 0x18
+#define RLC_ROM_CNTL__USE_ROM_MASK 0x1
+#define RLC_ROM_CNTL__USE_ROM__SHIFT 0x0
+#define RLC_ROM_CNTL__SLP_MODE_EN_MASK 0x2
+#define RLC_ROM_CNTL__SLP_MODE_EN__SHIFT 0x1
+#define RLC_ROM_CNTL__EFUSE_DISTRIB_EN_MASK 0x4
+#define RLC_ROM_CNTL__EFUSE_DISTRIB_EN__SHIFT 0x2
+#define RLC_ROM_CNTL__HELLOWORLD_EN_MASK 0x8
+#define RLC_ROM_CNTL__HELLOWORLD_EN__SHIFT 0x3
+#define RLC_ROM_CNTL__CU_HARVEST_EN_MASK 0x10
+#define RLC_ROM_CNTL__CU_HARVEST_EN__SHIFT 0x4
+#define RLC_ROM_CNTL__RESERVED_MASK 0xffffffe0
+#define RLC_ROM_CNTL__RESERVED__SHIFT 0x5
+#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffff
+#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0
+#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffff
+#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x1
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffe
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1
+#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffff
+#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0
+#define RLC_GPM_STAT__RLC_BUSY_MASK 0x1
+#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0
+#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x2
+#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1
+#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x4
+#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2
+#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x8
+#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3
+#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x10
+#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4
+#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x20
+#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5
+#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x40
+#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6
+#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x80
+#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7
+#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x100
+#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8
+#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x200
+#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9
+#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x400
+#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa
+#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x800
+#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb
+#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x1000
+#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc
+#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x2000
+#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd
+#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x4000
+#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe
+#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x8000
+#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf
+#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x10000
+#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10
+#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x20000
+#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11
+#define RLC_GPM_STAT__RESERVED_MASK 0xfc0000
+#define RLC_GPM_STAT__RESERVED__SHIFT 0x12
+#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xff000000
+#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18
+#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x3f
+#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0
+#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0
+#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6
+#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffff
+#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0
+#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1
+#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0
+#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x2
+#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1
+#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x4
+#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2
+#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x8
+#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3
+#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x10
+#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4
+#define RLC_PG_CNTL__RESERVED_MASK 0x3fe0
+#define RLC_PG_CNTL__RESERVED__SHIFT 0x5
+#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x4000
+#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe
+#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x8000
+#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf
+#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x10000
+#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10
+#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x20000
+#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11
+#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x40000
+#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12
+#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x80000
+#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13
+#define RLC_PG_CNTL__RESERVED1_MASK 0xf00000
+#define RLC_PG_CNTL__RESERVED1__SHIFT 0x14
+#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0xff
+#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0
+#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0xff00
+#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8
+#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0xff0000
+#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10
+#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xff000000
+#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18
+#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x1
+#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0
+#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x2
+#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1
+#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x4
+#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2
+#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x8
+#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3
+#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xfffffff0
+#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4
+#define RLC_GPM_VMID_THREAD0__RLC_VMID_MASK 0xf
+#define RLC_GPM_VMID_THREAD0__RLC_VMID__SHIFT 0x0
+#define RLC_GPM_VMID_THREAD0__RESERVED0_MASK 0xf0
+#define RLC_GPM_VMID_THREAD0__RESERVED0__SHIFT 0x4
+#define RLC_GPM_VMID_THREAD0__RLC_QUEUEID_MASK 0x700
+#define RLC_GPM_VMID_THREAD0__RLC_QUEUEID__SHIFT 0x8
+#define RLC_GPM_VMID_THREAD0__RESERVED1_MASK 0xfffff800
+#define RLC_GPM_VMID_THREAD0__RESERVED1__SHIFT 0xb
+#define RLC_GPM_VMID_THREAD1__RLC_VMID_MASK 0xf
+#define RLC_GPM_VMID_THREAD1__RLC_VMID__SHIFT 0x0
+#define RLC_GPM_VMID_THREAD1__RESERVED0_MASK 0xf0
+#define RLC_GPM_VMID_THREAD1__RESERVED0__SHIFT 0x4
+#define RLC_GPM_VMID_THREAD1__RLC_QUEUEID_MASK 0x700
+#define RLC_GPM_VMID_THREAD1__RLC_QUEUEID__SHIFT 0x8
+#define RLC_GPM_VMID_THREAD1__RESERVED1_MASK 0xfffff800
+#define RLC_GPM_VMID_THREAD1__RESERVED1__SHIFT 0xb
+#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK 0xffffffff
+#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT 0x0
+#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1
+#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0
+#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2
+#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1
+#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0xfc
+#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
+#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x7ffff00
+#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
+#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x8000000
+#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b
+#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000
+#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c
+#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000
+#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d
+#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000
+#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0xf
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0xf0
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0xf00
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0xf000
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0xfff0000
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c
+#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff
+#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
+#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xffffffff
+#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0
+#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0xff
+#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0
+#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0xff00
+#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8
+#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0xff0000
+#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10
+#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xff000000
+#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18
+#define RLC_CU_STATUS__WORK_PENDING_MASK 0xffffffff
+#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0
+#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xffffffff
+#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0
+#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xffffffff
+#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0
+#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x1
+#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0
+#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0xfe
+#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0xff00
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10
+#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0xff
+#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0
+#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0xff00
+#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8
+#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0xff0000
+#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10
+#define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000
+#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18
+#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xffffffff
+#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0
+#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0xff
+#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0
+#define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00
+#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8
+#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x1
+#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0
+#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x2
+#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1
+#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x4
+#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2
+#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x7fff8
+#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3
+#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000
+#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13
+#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x1
+#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0
+#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffe
+#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1
+#define RLC_SMU_PG_CTRL__START_PG_MASK 0x1
+#define RLC_SMU_PG_CTRL__START_PG__SHIFT 0x0
+#define RLC_SMU_PG_CTRL__SPARE_MASK 0xfffffffe
+#define RLC_SMU_PG_CTRL__SPARE__SHIFT 0x1
+#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP_MASK 0x1
+#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP__SHIFT 0x0
+#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE_MASK 0xfffffffe
+#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE__SHIFT 0x1
+#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0xf
+#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0
+#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x30
+#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4
+#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x1c0
+#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6
+#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x200
+#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9
+#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x400
+#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xa
+#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x7800
+#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xb
+#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x18000
+#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0xf
+#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xfffe0000
+#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x11
+#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffff
+#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0
+#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffff
+#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0
+#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffff
+#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0
+#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xffffffff
+#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0xffff
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x10000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x20000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x40000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x80000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x100000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x200000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x400000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x800000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xff000000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x18
+#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0xff
+#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0
+#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x100
+#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8
+#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x200
+#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9
+#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x400
+#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa
+#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x800
+#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb
+#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x1000
+#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc
+#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x2000
+#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd
+#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x4000
+#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe
+#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x8000
+#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf
+#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x3ff0000
+#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10
+#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x4000000
+#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a
+#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x8000000
+#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b
+#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000
+#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c
+#define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffff
+#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0
+#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xffffffff
+#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0
+#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0xffff
+#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0
+#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x10000
+#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10
+#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x20000
+#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x40000
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x80000
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x100000
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x200000
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x400000
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x800000
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17
+#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xff000000
+#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x18
+#define RLC_GPM_GENERAL_0__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_1__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_2__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_3__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_4__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_5__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_6__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_7__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0
+#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT_MASK 0xffffffff
+#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT__SHIFT 0x0
+#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x1ff
+#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0
+#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00
+#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9
+#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xffffffff
+#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0
+#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff
+#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
+#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0xf
+#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0
+#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0xf0
+#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4
+#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0xf00
+#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8
+#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0xf000
+#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc
+#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x30000
+#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10
+#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0xc0000
+#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12
+#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x100000
+#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14
+#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xffe00000
+#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15
+#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0xf
+#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0
+#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0xf0
+#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4
+#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0xf00
+#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8
+#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0xf000
+#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc
+#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x30000
+#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10
+#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0xc0000
+#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12
+#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x100000
+#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14
+#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xffe00000
+#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15
+#define RLC_GPR_REG1__DATA_MASK 0xffffffff
+#define RLC_GPR_REG1__DATA__SHIFT 0x0
+#define RLC_GPR_REG2__DATA_MASK 0xffffffff
+#define RLC_GPR_REG2__DATA__SHIFT 0x0
+#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x1
+#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0
+#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x2
+#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1
+#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x4
+#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2
+#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x78
+#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3
+#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x7f80
+#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7
+#define RLC_MGCG_CTRL__SPARE_MASK 0xffff8000
+#define RLC_MGCG_CTRL__SPARE__SHIFT 0xf
+#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x1
+#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0
+#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x2
+#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1
+#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x4
+#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2
+#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x8
+#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3
+#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xfffffff0
+#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4
+#define RLC_SPM_VMID__RLC_SPM_VMID_MASK 0xf
+#define RLC_SPM_VMID__RLC_SPM_VMID__SHIFT 0x0
+#define RLC_SPM_VMID__RESERVED_MASK 0xfffffff0
+#define RLC_SPM_VMID__RESERVED__SHIFT 0x4
+#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x1
+#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0
+#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xfffffffe
+#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1
+#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x1
+#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0
+#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xfffffffe
+#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1
+#define RLC_SPM_DEBUG_SELECT__SELECT_MASK 0xff
+#define RLC_SPM_DEBUG_SELECT__SELECT__SHIFT 0x0
+#define RLC_SPM_DEBUG_SELECT__RESERVED_MASK 0x7f00
+#define RLC_SPM_DEBUG_SELECT__RESERVED__SHIFT 0x8
+#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE_MASK 0x8000
+#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE__SHIFT 0xf
+#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE_MASK 0xffff0000
+#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE__SHIFT 0x10
+#define RLC_SPM_DEBUG__DATA_MASK 0xffffffff
+#define RLC_SPM_DEBUG__DATA__SHIFT 0x0
+#define RLC_GPM_LOG_ADDR__ADDR_MASK 0xffffffff
+#define RLC_GPM_LOG_ADDR__ADDR__SHIFT 0x0
+#define RLC_SMU_MESSAGE__CMD_MASK 0xffffffff
+#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0
+#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xffffffff
+#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0
+#define RLC_GPM_LOG_CONT__CONT_MASK 0xffffffff
+#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0
+#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0xff
+#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0
+#define RLC_PG_DELAY_3__RESERVED_MASK 0xffffff00
+#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8
+#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xffffffff
+#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0
+#define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK 0xffffffff
+#define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT 0x0
+#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xffffffff
+#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0
+#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xffffffff
+#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0
+#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x1
+#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0
+#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x2
+#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1
+#define RLC_SRM_CNTL__RESERVED_MASK 0xfffffffc
+#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2
+#define RLC_SRM_DEBUG_SELECT__SELECT_MASK 0xff
+#define RLC_SRM_DEBUG_SELECT__SELECT__SHIFT 0x0
+#define RLC_SRM_DEBUG_SELECT__RESERVED_MASK 0xffffff00
+#define RLC_SRM_DEBUG_SELECT__RESERVED__SHIFT 0x8
+#define RLC_SRM_DEBUG__DATA_MASK 0xffffffff
+#define RLC_SRM_DEBUG__DATA__SHIFT 0x0
+#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x3ff
+#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0
+#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xfffffc00
+#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xa
+#define RLC_SRM_ARAM_DATA__DATA_MASK 0xffffffff
+#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0
+#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x3ff
+#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0
+#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xfffffc00
+#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xa
+#define RLC_SRM_DRAM_DATA__DATA_MASK 0xffffffff
+#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0
+#define RLC_SRM_GPM_COMMAND__OP_MASK 0x1
+#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0
+#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x2
+#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1
+#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x1c
+#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2
+#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x1ffe0
+#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5
+#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1ffe0000
+#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11
+#define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000
+#define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d
+#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000
+#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f
+#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1
+#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
+#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x2
+#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
+#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xfffffffc
+#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2
+#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x1
+#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0
+#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0xe
+#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1
+#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0xfff0
+#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4
+#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0xfff0000
+#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10
+#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000
+#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c
+#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000
+#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f
+#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1
+#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
+#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x2
+#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
+#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xfffffffc
+#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2
+#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0xffff
+#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xffff0000
+#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0xffff
+#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xffff0000
+#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0xffff
+#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xffff0000
+#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0xffff
+#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xffff0000
+#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0xffff
+#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xffff0000
+#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0xffff
+#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xffff0000
+#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0xffff
+#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xffff0000
+#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0xffff
+#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xffff0000
+#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xffffffff
+#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xffffffff
+#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xffffffff
+#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xffffffff
+#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xffffffff
+#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xffffffff
+#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xffffffff
+#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xffffffff
+#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0
+#define RLC_SRM_STAT__SRM_STATUS_MASK 0x1
+#define RLC_SRM_STAT__SRM_STATUS__SHIFT 0x0
+#define RLC_SRM_STAT__RESERVED_MASK 0xfffffffe
+#define RLC_SRM_STAT__RESERVED__SHIFT 0x1
+#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x1
+#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0
+#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xfffffffe
+#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1
+#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xffffffff
+#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0
+#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0xffff
+#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0
+#define RLC_CSIB_LENGTH__LENGTH_MASK 0xffffffff
+#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0
+#define RLC_CP_RESPONSE0__RESPONSE_MASK 0xffffffff
+#define RLC_CP_RESPONSE0__RESPONSE__SHIFT 0x0
+#define RLC_CP_RESPONSE1__RESPONSE_MASK 0xffffffff
+#define RLC_CP_RESPONSE1__RESPONSE__SHIFT 0x0
+#define RLC_CP_RESPONSE2__RESPONSE_MASK 0xffffffff
+#define RLC_CP_RESPONSE2__RESPONSE__SHIFT 0x0
+#define RLC_CP_RESPONSE3__RESPONSE_MASK 0xffffffff
+#define RLC_CP_RESPONSE3__RESPONSE__SHIFT 0x0
+#define RLC_SMU_COMMAND__CMD_MASK 0xffffffff
+#define RLC_SMU_COMMAND__CMD__SHIFT 0x0
+#define RLC_CP_SCHEDULERS__scheduler0_MASK 0xff
+#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0
+#define RLC_CP_SCHEDULERS__scheduler1_MASK 0xff00
+#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8
+#define RLC_CP_SCHEDULERS__scheduler2_MASK 0xff0000
+#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10
+#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xff000000
+#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18
+#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0xfff
+#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0
+#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x3000
+#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc
+#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0xc000
+#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe
+#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xffff0000
+#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10
+#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xffffffff
+#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0
+#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0xffff
+#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0
+#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xffff0000
+#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10
+#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xffffffff
+#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0xff
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x700
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0xf800
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x1f0000
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x3e00000
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7c000000
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f
+#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff
+#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
+#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff
+#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
+#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff
+#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
+#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff
+#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
+#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xffffffff
+#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0
+#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xffffffff
+#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0
+#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x1
+#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0xfffe
+#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xffff0000
+#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10
+#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0xf
+#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x10
+#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4
+#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x20
+#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5
+#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0xc0
+#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6
+#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0xff00
+#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8
+#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0xff0000
+#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10
+#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xff000000
+#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18
+#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0xf
+#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xfffffff0
+#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x7f
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x80
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7
+#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x300
+#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xfffffc00
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa
+#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xffffffff
+#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_MASK 0xff
+#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_STATUS_MASK 0xf00
+#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_STATUS__SHIFT 0x8
+#define RLC_GPU_IOV_CFG_REG9__RESERVED_MASK 0xfffff000
+#define RLC_GPU_IOV_CFG_REG9__RESERVED__SHIFT 0xc
+#define RLC_GPU_IOV_CFG_REG10__TIME_QUANTA_PF_MASK 0xffff
+#define RLC_GPU_IOV_CFG_REG10__TIME_QUANTA_PF__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG10__RESERVED_MASK 0xffff0000
+#define RLC_GPU_IOV_CFG_REG10__RESERVED__SHIFT 0x10
+#define RLC_GPU_IOV_CFG_REG11__YIELD_MASK 0xffffffff
+#define RLC_GPU_IOV_CFG_REG11__YIELD__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF0_MASK 0xff
+#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF0__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF1_MASK 0xff00
+#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF1__SHIFT 0x8
+#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF2_MASK 0xff0000
+#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF2__SHIFT 0x10
+#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF3_MASK 0xff000000
+#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF3__SHIFT 0x18
+#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF4_MASK 0xff
+#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF4__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF5_MASK 0xff00
+#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF5__SHIFT 0x8
+#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF6_MASK 0xff0000
+#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF6__SHIFT 0x10
+#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF7_MASK 0xff000000
+#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF7__SHIFT 0x18
+#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF8_MASK 0xff
+#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF8__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF9_MASK 0xff00
+#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF9__SHIFT 0x8
+#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF10_MASK 0xff0000
+#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF10__SHIFT 0x10
+#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF11_MASK 0xff000000
+#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF11__SHIFT 0x18
+#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF12_MASK 0xff
+#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF12__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF13_MASK 0xff00
+#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF13__SHIFT 0x8
+#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF14_MASK 0xff0000
+#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF14__SHIFT 0x10
+#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF15_MASK 0xff000000
+#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF15__SHIFT 0x18
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0xf
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7ffffff0
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f
+#define RLC_GPM_VMID_THREAD2__RLC_VMID_MASK 0xf
+#define RLC_GPM_VMID_THREAD2__RLC_VMID__SHIFT 0x0
+#define RLC_GPM_VMID_THREAD2__RESERVED0_MASK 0xf0
+#define RLC_GPM_VMID_THREAD2__RESERVED0__SHIFT 0x4
+#define RLC_GPM_VMID_THREAD2__RLC_QUEUEID_MASK 0x700
+#define RLC_GPM_VMID_THREAD2__RLC_QUEUEID__SHIFT 0x8
+#define RLC_GPM_VMID_THREAD2__RESERVED1_MASK 0xfffff800
+#define RLC_GPM_VMID_THREAD2__RESERVED1__SHIFT 0xb
+#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
+#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xfffff000
+#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc
+#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
+#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x1ff
+#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0
+#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00
+#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT 0x9
+#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xffffffff
+#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x1
+#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0
+#define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK 0xfffffffe
+#define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x1
+#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0
+#define RLC_GPU_IOV_F32_RESET__RESERVED_MASK 0xfffffffe
+#define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x1
+#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK 0xfe
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x100
+#define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK 0xe00
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT 0x9
+#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x1000
+#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK 0xffffe000
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT 0xd
+#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x1
+#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK 0xfe
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x100
+#define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK 0xe00
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT 0x9
+#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x1000
+#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK 0xffffe000
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT 0xd
+#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xffffffff
+#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0
+#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0xffff
+#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0
+#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7fff0000
+#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10
+#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000
+#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f
+#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xffffffff
+#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0
+#define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xffffffff
+#define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0
+#define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xffffffff
+#define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffff
+#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffff
+#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_0__DATA_MASK 0xffffffff
+#define RLC_GPU_IOV_SCH_0__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xffffffff
+#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xffffffff
+#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_3__DATA_MASK 0xffffffff
+#define RLC_GPU_IOV_SCH_3__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_INT__interrupt_MASK 0xffffffff
+#define RLC_GPU_IOV_SCH_INT__interrupt__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19
+#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x3e
+#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1
+#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x40
+#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6
+#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x1
+#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0
+#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x2
+#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1
+#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x4
+#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2
+#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x8
+#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3
+#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x10
+#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4
+#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x20
+#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5
+#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x40
+#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6
+#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x80
+#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
+#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x100
+#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8
+#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x200
+#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9
+#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x400
+#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa
+#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x800
+#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb
+#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x1000
+#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc
+#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x2000
+#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd
+#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x4000
+#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe
+#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x8000
+#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf
+#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x1
+#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0
+#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x2
+#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1
+#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x4
+#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2
+#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x8
+#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3
+#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x10
+#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x20
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x40
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6
+#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x80
+#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
+#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x100
+#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8
+#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x200
+#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9
+#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x400
+#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa
+#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x800
+#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb
+#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x1000
+#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc
+#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x2000
+#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd
+#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x4000
+#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe
+#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x8000
+#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf
+#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x1
+#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x2
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x1c
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0xe0
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x700
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x3800
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x4000
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe
+#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f
+#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0
+#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x40
+#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6
+#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x4000
+#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe
+#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x1
+#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0
+#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x10
+#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4
+#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x100
+#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8
+#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x1000
+#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc
+#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x30000
+#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10
+#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x100000
+#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14
+#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x1000000
+#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18
+#define SPI_TMPRING_SIZE__WAVES_MASK 0xfff
+#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0
+#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000
+#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
+#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0xf
+#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0
+#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0xf0
+#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4
+#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0xf00
+#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8
+#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0xf000
+#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc
+#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0xf
+#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0
+#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0xf
+#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0
+#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0xf0
+#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4
+#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0xf00
+#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8
+#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0xf000
+#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc
+#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0xf0000
+#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10
+#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0xf00000
+#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14
+#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0xf000000
+#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18
+#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xf0000000
+#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x7
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x38
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x1c0
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0xe00
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9
+#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x3000
+#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc
+#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0xc000
+#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe
+#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x30000
+#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10
+#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0xc0000
+#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12
+#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0xffff
+#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0
+#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xffff0000
+#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10
+#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0xffff
+#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0
+#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xffff0000
+#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10
+#define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x1
+#define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0
+#define SPI_CDBG_SYS_GFX__VS_EN_MASK 0x2
+#define SPI_CDBG_SYS_GFX__VS_EN__SHIFT 0x1
+#define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x4
+#define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2
+#define SPI_CDBG_SYS_GFX__ES_EN_MASK 0x8
+#define SPI_CDBG_SYS_GFX__ES_EN__SHIFT 0x3
+#define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x10
+#define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4
+#define SPI_CDBG_SYS_GFX__LS_EN_MASK 0x20
+#define SPI_CDBG_SYS_GFX__LS_EN__SHIFT 0x5
+#define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x40
+#define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6
+#define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x1
+#define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0
+#define SPI_CDBG_SYS_HP3D__VS_EN_MASK 0x2
+#define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT 0x1
+#define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x4
+#define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2
+#define SPI_CDBG_SYS_HP3D__ES_EN_MASK 0x8
+#define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT 0x3
+#define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x10
+#define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4
+#define SPI_CDBG_SYS_HP3D__LS_EN_MASK 0x20
+#define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT 0x5
+#define SPI_CDBG_SYS_CS0__PIPE0_MASK 0xff
+#define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0
+#define SPI_CDBG_SYS_CS0__PIPE1_MASK 0xff00
+#define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8
+#define SPI_CDBG_SYS_CS0__PIPE2_MASK 0xff0000
+#define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10
+#define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xff000000
+#define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18
+#define SPI_CDBG_SYS_CS1__PIPE0_MASK 0xff
+#define SPI_CDBG_SYS_CS1__PIPE0__SHIFT 0x0
+#define SPI_CDBG_SYS_CS1__PIPE1_MASK 0xff00
+#define SPI_CDBG_SYS_CS1__PIPE1__SHIFT 0x8
+#define SPI_CDBG_SYS_CS1__PIPE2_MASK 0xff0000
+#define SPI_CDBG_SYS_CS1__PIPE2__SHIFT 0x10
+#define SPI_CDBG_SYS_CS1__PIPE3_MASK 0xff000000
+#define SPI_CDBG_SYS_CS1__PIPE3__SHIFT 0x18
+#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x7f
+#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0xf80
+#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7
+#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x1f000
+#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc
+#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x3e0000
+#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11
+#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x7c00000
+#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16
+#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x7f
+#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE_MASK 0xf80
+#define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE__SHIFT 0x7
+#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x1f000
+#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc
+#define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE_MASK 0x3e0000
+#define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE__SHIFT 0x11
+#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x7c00000
+#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16
+#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7f
+#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7f
+#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7f
+#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7f
+#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7f
+#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7f
+#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7f
+#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7f
+#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0
+#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x1
+#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0
+#define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK 0x1fffe
+#define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT 0x1
+#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x3
+#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0
+#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0xc
+#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2
+#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x70
+#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4
+#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x80
+#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7
+#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x100
+#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8
+#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x200
+#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9
+#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x8000
+#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf
+#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xffff0000
+#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10
+#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x1ff
+#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0
+#define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x200
+#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9
+#define SPI_GDBG_TBA_LO__MEM_BASE_MASK 0xffffffff
+#define SPI_GDBG_TBA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_GDBG_TBA_HI__MEM_BASE_MASK 0xff
+#define SPI_GDBG_TBA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_GDBG_TMA_LO__MEM_BASE_MASK 0xffffffff
+#define SPI_GDBG_TMA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_GDBG_TMA_HI__MEM_BASE_MASK 0xff
+#define SPI_GDBG_TMA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xffffffff
+#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0
+#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xffffffff
+#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x1
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x0
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x2
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x1
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x4
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x2
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x8
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x3
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x10
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x4
+#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x1
+#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x1
+#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0
+#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x2
+#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1
+#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x4
+#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2
+#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000
+#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e
+#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000
+#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f
+#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
+#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
+#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x3
+#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0
+#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0xc
+#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2
+#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x30
+#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4
+#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x1
+#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0
+#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x1fffff
+#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0
+#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0xe00000
+#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15
+#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x1000000
+#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18
+#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x2000000
+#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19
+#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x4000000
+#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a
+#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x8000000
+#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b
+#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE_MASK 0x1
+#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE__SHIFT 0x0
+#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK 0xe
+#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x1
+#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK 0x3f0
+#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT 0x4
+#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0xfc00
+#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0xa
+#define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x10000
+#define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x10
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x20000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x11
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x40000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x12
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2_MASK 0x80000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2__SHIFT 0x13
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x100000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x14
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4_MASK 0x200000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4__SHIFT 0x15
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5_MASK 0x400000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5__SHIFT 0x16
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6_MASK 0x800000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6__SHIFT 0x17
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7_MASK 0x1000000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7__SHIFT 0x18
+#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK 0xe000000
+#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT 0x19
+#define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000
+#define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x1f
+#define SPI_DEBUG_READ__DATA_MASK 0xffffff
+#define SPI_DEBUG_READ__DATA__SHIFT 0x0
+#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data0_MASK 0x1
+#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data0__SHIFT 0x0
+#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data1_MASK 0x2
+#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data1__SHIFT 0x1
+#define SPI_DSM_CNTL__SPI_Enable_Single_Write_MASK 0x4
+#define SPI_DSM_CNTL__SPI_Enable_Single_Write__SHIFT 0x2
+#define SPI_DSM_CNTL__UNUSED_MASK 0xfffffff8
+#define SPI_DSM_CNTL__UNUSED__SHIFT 0x3
+#define SPI_EDC_CNT__SED_MASK 0xff
+#define SPI_EDC_CNT__SED__SHIFT 0x0
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x3ff
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0xffc00
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x3ff
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0xffc00
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0xff
+#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0xff
+#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0xf
+#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0
+#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0xf0
+#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4
+#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0xf00
+#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8
+#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0xf000
+#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc
+#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0xf0000
+#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10
+#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0xf00000
+#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14
+#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0xf000000
+#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18
+#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xf0000000
+#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c
+#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0xf
+#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0
+#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x10
+#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x40
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x80
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7
+#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x100
+#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x200
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x3c00
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xffff0000
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10
+#define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x1
+#define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x0
+#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x2
+#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x1
+#define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x4
+#define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x2
+#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x8
+#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x3
+#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x10
+#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x4
+#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x20
+#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x5
+#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x40
+#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x6
+#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x80
+#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x7
+#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x100
+#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x8
+#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x200
+#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x9
+#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x400
+#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0xa
+#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x800
+#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0xb
+#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x1000
+#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xc
+#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x2000
+#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xd
+#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x4000
+#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xe
+#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x8000
+#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xf
+#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x10000
+#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x10
+#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x20000
+#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x11
+#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x40000
+#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x12
+#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x80000
+#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x13
+#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x100000
+#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x14
+#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x200000
+#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x15
+#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x400000
+#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x16
+#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x800000
+#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x17
+#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0xf
+#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0
+#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0xf0
+#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4
+#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0xf
+#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0
+#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0xff0
+#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4
+#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x1000
+#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc
+#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x10000
+#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10
+#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0xe0000
+#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11
+#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x100000
+#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14
+#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x200000
+#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15
+#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x400000
+#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16
+#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x800000
+#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17
+#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000
+#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18
+#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x1f
+#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0
+#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x1f00
+#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8
+#define CGTS_RD_REG__READ_DATA_MASK 0x3fff
+#define CGTS_RD_REG__READ_DATA__SHIFT 0x0
+#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000
+#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
+#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000
+#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
+#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU1_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU1_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU2_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU2_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU3_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU3_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU5_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU5_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU6_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU6_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU7_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU7_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU9_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU9_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU10_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU10_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU11_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU11_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU13_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU13_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU14_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU14_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU15_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU15_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000
+#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
+#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000
+#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
+#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x4000000
+#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x1a
+#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x8000000
+#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b
+#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000
+#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c
+#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000
+#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d
+#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000
+#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e
+#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
+#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE_MASK 0x2000000
+#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE__SHIFT 0x19
+#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE_MASK 0x4000000
+#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE__SHIFT 0x1a
+#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000
+#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
+#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000
+#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
+#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000
+#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
+#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000
+#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
+#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0xfff000
+#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc
+#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x1000000
+#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18
+#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x2000000
+#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19
+#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x4000000
+#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a
+#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000
+#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
+#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000
+#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
+#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000
+#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
+#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000
+#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
+#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0xf
+#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0
+#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x10
+#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4
+#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x0
+#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000
+#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x1f
+#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK 0x1
+#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT 0x0
+#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK 0x2
+#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT 0x1
+#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK 0x4
+#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT 0x2
+#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK 0x8
+#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT 0x3
+#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY_MASK 0x10
+#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY__SHIFT 0x4
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK 0x20
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT 0x5
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK 0x40
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT 0x6
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY_MASK 0x80
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY__SHIFT 0x7
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY_MASK 0x100
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY__SHIFT 0x8
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK 0x200
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT 0x9
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK 0x400
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT 0xa
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY_MASK 0x800
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY__SHIFT 0xb
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY_MASK 0x1000
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY__SHIFT 0xc
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY_MASK 0x2000
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY__SHIFT 0xd
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY_MASK 0x4000
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY__SHIFT 0xe
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY_MASK 0x8000
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY__SHIFT 0xf
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY_MASK 0x10000
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY__SHIFT 0x10
+#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY_MASK 0x20000
+#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY__SHIFT 0x11
+#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY_MASK 0x40000
+#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY__SHIFT 0x12
+#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY_MASK 0x80000
+#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY__SHIFT 0x13
+#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY_MASK 0x100000
+#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY__SHIFT 0x14
+#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK 0x200000
+#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT 0x15
+#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY_MASK 0x400000
+#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY__SHIFT 0x16
+#define SPI_LB_CTR_CTRL__LOAD_MASK 0x1
+#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0
+#define SPI_LB_CU_MASK__CU_MASK_MASK 0xffff
+#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0
+#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xffffffff
+#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0
+#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xffff
+#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0
+#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0xff
+#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0
+#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0xff00
+#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8
+#define SPI_GDS_CREDITS__UNUSED_MASK 0xffff0000
+#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10
+#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0xffff
+#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0
+#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xffff0000
+#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0xffff
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xffff0000
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xffffffff
+#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0
+#define BCI_DEBUG_READ__DATA_MASK 0xffffff
+#define BCI_DEBUG_READ__DATA__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff
+#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff
+#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff
+#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff
+#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
+#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff
+#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff
+#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff
+#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff
+#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
+#define SPI_SHADER_TBA_LO_PS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TBA_LO_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TBA_HI_PS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TBA_HI_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_LO_PS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TMA_LO_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_HI_PS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TMA_HI_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x3f
+#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x3c0
+#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0xc00
+#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0xff000
+#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x100000
+#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x200000
+#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x400000
+#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x800000
+#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x1000000
+#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL_MASK 0xe000000
+#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL__SHIFT 0x19
+#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000
+#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x80
+#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0xff00
+#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x1ff0000
+#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0xffff
+#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x3f0000
+#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
+#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0
+#define SPI_SHADER_TBA_LO_VS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TBA_LO_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TBA_HI_VS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TBA_HI_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_LO_VS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TMA_LO_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_HI_VS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TMA_HI_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x3f
+#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x3c0
+#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0xc00
+#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0xff000
+#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x100000
+#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x200000
+#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x400000
+#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x800000
+#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x3000000
+#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x4000000
+#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL_MASK 0x38000000
+#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000
+#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x1e
+#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x80
+#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x100
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x200
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x400
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x800
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb
+#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x1000
+#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x3fe000
+#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd
+#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x1000000
+#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0xffff
+#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x3f0000
+#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
+#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x3f
+#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK 0x80
+#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK 0x1ff00
+#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK 0x1ff00000
+#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK 0xff80
+#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK 0x1ff0000
+#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT 0x10
+#define SPI_SHADER_TBA_LO_GS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TBA_LO_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TBA_HI_GS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TBA_HI_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_LO_GS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TMA_LO_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_HI_GS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TMA_HI_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x3f
+#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x3c0
+#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0xc00
+#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0xff000
+#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x100000
+#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x200000
+#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x400000
+#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x800000
+#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x1000000
+#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL_MASK 0xe000000
+#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL__SHIFT 0x19
+#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000
+#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0xff80
+#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0xffff
+#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x3f0000
+#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
+#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH_MASK 0xfc000000
+#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH__SHIFT 0x1a
+#define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK 0x80
+#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK 0x1ff00
+#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK 0x1ff00000
+#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT 0x14
+#define SPI_SHADER_TBA_LO_ES__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TBA_LO_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TBA_HI_ES__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TBA_HI_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_LO_ES__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TMA_LO_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_HI_ES__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TMA_HI_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xff
+#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK 0x3f
+#define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK 0x3c0
+#define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK 0xc00
+#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK 0xff000
+#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK 0x100000
+#define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK 0x200000
+#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE_MASK 0x400000
+#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK 0x800000
+#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK 0x3000000
+#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK 0x4000000
+#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL_MASK 0x38000000
+#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER_MASK 0x40000000
+#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER__SHIFT 0x1e
+#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK 0x80
+#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK 0x1ff00
+#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK 0x1ff00000
+#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC3_ES__CU_EN_MASK 0xffff
+#define SPI_SHADER_PGM_RSRC3_ES__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT_MASK 0x3f0000
+#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD_MASK 0x3c00000
+#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH_MASK 0xfc000000
+#define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH__SHIFT 0x1a
+#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK 0xff80
+#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK 0x1ff0000
+#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT 0x10
+#define SPI_SHADER_TBA_LO_HS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TBA_LO_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TBA_HI_HS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TBA_HI_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_LO_HS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TMA_LO_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_HI_HS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TMA_HI_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x3f
+#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x3c0
+#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0xc00
+#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0xff000
+#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x100000
+#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x200000
+#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x400000
+#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x800000
+#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL_MASK 0x7000000
+#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x8000000
+#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x80
+#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x100
+#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x3fe00
+#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x9
+#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x3f
+#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x3c0
+#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH_MASK 0xfc00
+#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH__SHIFT 0xa
+#define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK 0xff80
+#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK 0x1ff0000
+#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT 0x10
+#define SPI_SHADER_TBA_LO_LS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TBA_LO_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TBA_HI_LS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TBA_HI_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_LO_LS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TMA_LO_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_HI_LS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TMA_HI_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK 0x3f
+#define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK 0x3c0
+#define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK 0xc00
+#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK 0xff000
+#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK 0x100000
+#define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK 0x200000
+#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE_MASK 0x400000
+#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK 0x800000
+#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK 0x3000000
+#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL_MASK 0x1c000000
+#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER_MASK 0x20000000
+#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT 0x1d
+#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK 0xff80
+#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK 0x1ff0000
+#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_LS__CU_EN_MASK 0xffff
+#define SPI_SHADER_PGM_RSRC3_LS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT_MASK 0x3f0000
+#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
+#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH_MASK 0xfc000000
+#define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH__SHIFT 0x1a
+#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0
+#define SQ_CONFIG__UNUSED_MASK 0xff
+#define SQ_CONFIG__UNUSED__SHIFT 0x0
+#define SQ_CONFIG__DEBUG_EN_MASK 0x100
+#define SQ_CONFIG__DEBUG_EN__SHIFT 0x8
+#define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK 0x200
+#define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT 0x9
+#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK 0x400
+#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT 0xa
+#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x1000
+#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc
+#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x2000
+#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd
+#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x4000
+#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe
+#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x8000
+#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf
+#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x10000
+#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10
+#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x20000
+#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11
+#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x40000
+#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12
+#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x180000
+#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13
+#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x1e00000
+#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15
+#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x3
+#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0
+#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0xc
+#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2
+#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x30
+#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4
+#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x40
+#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6
+#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x80
+#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7
+#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x100
+#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8
+#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x200
+#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9
+#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x400
+#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa
+#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x800
+#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb
+#define SQC_CONFIG__EVICT_LRU_MASK 0x3000
+#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc
+#define SQC_CONFIG__FORCE_2_BANK_MASK 0x4000
+#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe
+#define SQC_CONFIG__FORCE_1_BANK_MASK 0x8000
+#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf
+#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0xff0000
+#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10
+#define SQC_CACHES__TARGET_INST_MASK 0x1
+#define SQC_CACHES__TARGET_INST__SHIFT 0x0
+#define SQC_CACHES__TARGET_DATA_MASK 0x2
+#define SQC_CACHES__TARGET_DATA__SHIFT 0x1
+#define SQC_CACHES__INVALIDATE_MASK 0x4
+#define SQC_CACHES__INVALIDATE__SHIFT 0x2
+#define SQC_CACHES__WRITEBACK_MASK 0x8
+#define SQC_CACHES__WRITEBACK__SHIFT 0x3
+#define SQC_CACHES__VOL_MASK 0x10
+#define SQC_CACHES__VOL__SHIFT 0x4
+#define SQC_CACHES__COMPLETE_MASK 0x10000
+#define SQC_CACHES__COMPLETE__SHIFT 0x10
+#define SQC_WRITEBACK__DWB_MASK 0x1
+#define SQC_WRITEBACK__DWB__SHIFT 0x0
+#define SQC_WRITEBACK__DIRTY_MASK 0x2
+#define SQC_WRITEBACK__DIRTY__SHIFT 0x1
+#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKA_MASK 0x3
+#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKA__SHIFT 0x0
+#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKA_MASK 0x4
+#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKA__SHIFT 0x2
+#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKB_MASK 0x18
+#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKB__SHIFT 0x3
+#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKB_MASK 0x20
+#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKB__SHIFT 0x5
+#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKC_MASK 0xc0
+#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKC__SHIFT 0x6
+#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKC_MASK 0x100
+#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKC__SHIFT 0x8
+#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKD_MASK 0x600
+#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKD__SHIFT 0x9
+#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKD_MASK 0x800
+#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKD__SHIFT 0xb
+#define SQC_DSM_CNTL__SEL_DATA_ICACHE_GATCL1_MASK 0x3000
+#define SQC_DSM_CNTL__SEL_DATA_ICACHE_GATCL1__SHIFT 0xc
+#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_GATCL1_MASK 0x4000
+#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_GATCL1__SHIFT 0xe
+#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKA_MASK 0x18000
+#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKA__SHIFT 0xf
+#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKA_MASK 0x20000
+#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKA__SHIFT 0x11
+#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKB_MASK 0xc0000
+#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKB__SHIFT 0x12
+#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKB_MASK 0x100000
+#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKB__SHIFT 0x14
+#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKC_MASK 0x600000
+#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKC__SHIFT 0x15
+#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKC_MASK 0x800000
+#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKC__SHIFT 0x17
+#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKD_MASK 0x3000000
+#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKD__SHIFT 0x18
+#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKD_MASK 0x4000000
+#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKD__SHIFT 0x1a
+#define SQC_DSM_CNTL__SEL_DATA_DCACHE_GATCL1_MASK 0x18000000
+#define SQC_DSM_CNTL__SEL_DATA_DCACHE_GATCL1__SHIFT 0x1b
+#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1_MASK 0x20000000
+#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1__SHIFT 0x1d
+#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x7f
+#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0
+#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x380
+#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7
+#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x1ffc00
+#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa
+#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x3f
+#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0
+#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0xf00
+#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8
+#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000
+#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c
+#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000
+#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d
+#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000
+#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e
+#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000
+#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f
+#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0xf
+#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0
+#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0xf00
+#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8
+#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x30000
+#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10
+#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0xc0000
+#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12
+#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x1
+#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0
+#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x2
+#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1
+#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x4
+#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2
+#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x8
+#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3
+#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x100
+#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8
+#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x200
+#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9
+#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x400
+#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x10000
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x20000
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11
+#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x40000
+#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x80000
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x100000
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14
+#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x200000
+#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15
+#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x1000000
+#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18
+#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x2000000
+#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19
+#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x4000000
+#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a
+#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x6
+#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
+#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8
+#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
+#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x10
+#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
+#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x6
+#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
+#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8
+#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
+#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x10
+#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
+#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0xffffff
+#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0
+#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x1
+#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0
+#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x1
+#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0
+#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x2
+#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1
+#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x4
+#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2
+#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x8
+#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3
+#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x10
+#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4
+#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x20
+#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5
+#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x40
+#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6
+#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x1f00
+#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8
+#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x2000
+#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd
+#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0xffff
+#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0
+#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xffff0000
+#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x1
+#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0
+#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000
+#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10
+#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000
+#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14
+#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000
+#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18
+#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000
+#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c
+#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000
+#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10
+#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000
+#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14
+#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000
+#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18
+#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000
+#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c
+#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c
+#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000
+#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
+#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
+#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
+#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000
+#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c
+#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000
+#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
+#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
+#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
+#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
+#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
+#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
+#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
+#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
+#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
+#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
+#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
+#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
+#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
+#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
+#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
+#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x3fff
+#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0
+#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3fff0000
+#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10
+#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xc0000000
+#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e
+#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x3fff
+#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0
+#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
+#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
+#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000
+#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f
+#define SQ_TIME_HI__TIME_MASK 0xffffffff
+#define SQ_TIME_HI__TIME__SHIFT 0x0
+#define SQ_TIME_LO__TIME_MASK 0xffffffff
+#define SQ_TIME_LO__TIME__SHIFT 0x0
+#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xffffffff
+#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0
+#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0xf
+#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x3fffff
+#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0
+#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x1f
+#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0
+#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x20
+#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5
+#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x80
+#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7
+#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0xf00
+#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8
+#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x3000
+#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc
+#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x4000
+#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe
+#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x8000
+#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf
+#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xffffffff
+#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xffffffff
+#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xffffffff
+#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xffffffff
+#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x7
+#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0
+#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x38
+#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3
+#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x1c0
+#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6
+#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0xe00
+#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9
+#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x7000
+#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc
+#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x38000
+#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf
+#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x1c0000
+#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12
+#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x600000
+#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15
+#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x1800000
+#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17
+#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x2000000
+#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19
+#define SQ_THREAD_TRACE_MODE__PRIV_MASK 0x4000000
+#define SQ_THREAD_TRACE_MODE__PRIV__SHIFT 0x1a
+#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000
+#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b
+#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000
+#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d
+#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000
+#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e
+#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000
+#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f
+#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000
+#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f
+#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0xffff
+#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0xff0000
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x1000000
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18
+#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xffffffff
+#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0
+#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0xffff
+#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0
+#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xffff0000
+#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10
+#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3fffffff
+#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0
+#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xc0000000
+#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e
+#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x3ff
+#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0
+#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x3ff0000
+#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10
+#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000
+#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d
+#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000
+#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e
+#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000
+#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f
+#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xffffffff
+#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0
+#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x7
+#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0
+#define SQ_LB_CTR_CTRL__START_MASK 0x1
+#define SQ_LB_CTR_CTRL__START__SHIFT 0x0
+#define SQ_LB_CTR_CTRL__LOAD_MASK 0x2
+#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1
+#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x4
+#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2
+#define SQ_LB_DATA_ALU_CYCLES__DATA_MASK 0xffffffff
+#define SQ_LB_DATA_ALU_CYCLES__DATA__SHIFT 0x0
+#define SQ_LB_DATA_TEX_CYCLES__DATA_MASK 0xffffffff
+#define SQ_LB_DATA_TEX_CYCLES__DATA__SHIFT 0x0
+#define SQ_LB_DATA_ALU_STALLS__DATA_MASK 0xffffffff
+#define SQ_LB_DATA_ALU_STALLS__DATA__SHIFT 0x0
+#define SQ_LB_DATA_TEX_STALLS__DATA_MASK 0xffffffff
+#define SQ_LB_DATA_TEX_STALLS__DATA__SHIFT 0x0
+#define SQC_EDC_CNT__INST_SEC_MASK 0xff
+#define SQC_EDC_CNT__INST_SEC__SHIFT 0x0
+#define SQC_EDC_CNT__INST_DED_MASK 0xff00
+#define SQC_EDC_CNT__INST_DED__SHIFT 0x8
+#define SQC_EDC_CNT__DATA_SEC_MASK 0xff0000
+#define SQC_EDC_CNT__DATA_SEC__SHIFT 0x10
+#define SQC_EDC_CNT__DATA_DED_MASK 0xff000000
+#define SQC_EDC_CNT__DATA_DED__SHIFT 0x18
+#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0xff
+#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0
+#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0xff00
+#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8
+#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0xff0000
+#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10
+#define SQ_EDC_DED_CNT__LDS_DED_MASK 0xff
+#define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0
+#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0xff00
+#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8
+#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0xff0000
+#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10
+#define SQ_EDC_INFO__WAVE_ID_MASK 0xf
+#define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0
+#define SQ_EDC_INFO__SIMD_ID_MASK 0x30
+#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4
+#define SQ_EDC_INFO__SOURCE_MASK 0x1c0
+#define SQ_EDC_INFO__SOURCE__SHIFT 0x6
+#define SQ_EDC_INFO__VM_ID_MASK 0x1e00
+#define SQ_EDC_INFO__VM_ID__SHIFT 0x9
+#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff
+#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
+#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xffff
+#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
+#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3fff0000
+#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10
+#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000
+#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e
+#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000
+#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f
+#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffff
+#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0
+#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x7
+#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
+#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x38
+#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
+#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0
+#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
+#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0xe00
+#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
+#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x7000
+#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc
+#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x78000
+#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf
+#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE_MASK 0x180000
+#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE__SHIFT 0x13
+#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x600000
+#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15
+#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x800000
+#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17
+#define SQ_BUF_RSRC_WORD3__ATC_MASK 0x1000000
+#define SQ_BUF_RSRC_WORD3__ATC__SHIFT 0x18
+#define SQ_BUF_RSRC_WORD3__HASH_ENABLE_MASK 0x2000000
+#define SQ_BUF_RSRC_WORD3__HASH_ENABLE__SHIFT 0x19
+#define SQ_BUF_RSRC_WORD3__HEAP_MASK 0x4000000
+#define SQ_BUF_RSRC_WORD3__HEAP__SHIFT 0x1a
+#define SQ_BUF_RSRC_WORD3__MTYPE_MASK 0x38000000
+#define SQ_BUF_RSRC_WORD3__MTYPE__SHIFT 0x1b
+#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xc0000000
+#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e
+#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff
+#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xff
+#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0xfff00
+#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8
+#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x3f00000
+#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14
+#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3c000000
+#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a
+#define SQ_IMG_RSRC_WORD1__MTYPE_MASK 0xc0000000
+#define SQ_IMG_RSRC_WORD1__MTYPE__SHIFT 0x1e
+#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x3fff
+#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0xfffc000
+#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe
+#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000
+#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c
+#define SQ_IMG_RSRC_WORD2__INTERLACED_MASK 0x80000000
+#define SQ_IMG_RSRC_WORD2__INTERLACED__SHIFT 0x1f
+#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x7
+#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x38
+#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
+#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0
+#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
+#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0xe00
+#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
+#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0xf000
+#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc
+#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0xf0000
+#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10
+#define SQ_IMG_RSRC_WORD3__TILING_INDEX_MASK 0x1f00000
+#define SQ_IMG_RSRC_WORD3__TILING_INDEX__SHIFT 0x14
+#define SQ_IMG_RSRC_WORD3__POW2_PAD_MASK 0x2000000
+#define SQ_IMG_RSRC_WORD3__POW2_PAD__SHIFT 0x19
+#define SQ_IMG_RSRC_WORD3__MTYPE_MASK 0x4000000
+#define SQ_IMG_RSRC_WORD3__MTYPE__SHIFT 0x1a
+#define SQ_IMG_RSRC_WORD3__ATC_MASK 0x8000000
+#define SQ_IMG_RSRC_WORD3__ATC__SHIFT 0x1b
+#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xf0000000
+#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c
+#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x1fff
+#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x7ffe000
+#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd
+#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x1fff
+#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD5__LAST_ARRAY_MASK 0x3ffe000
+#define SQ_IMG_RSRC_WORD5__LAST_ARRAY__SHIFT 0xd
+#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0xfff
+#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0xff000
+#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc
+#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x100000
+#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14
+#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x200000
+#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15
+#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x400000
+#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16
+#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x800000
+#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17
+#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0xf000000
+#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18
+#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xf0000000
+#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c
+#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xffffffff
+#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0
+#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x7
+#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0
+#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x38
+#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3
+#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x1c0
+#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6
+#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0xe00
+#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9
+#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x7000
+#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc
+#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x8000
+#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf
+#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x70000
+#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10
+#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x80000
+#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13
+#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x100000
+#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14
+#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x7e00000
+#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15
+#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x8000000
+#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b
+#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000
+#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c
+#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000
+#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d
+#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000
+#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f
+#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0xfff
+#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0
+#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0xfff000
+#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc
+#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0xf000000
+#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18
+#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xf0000000
+#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c
+#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x3fff
+#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0
+#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0xfc000
+#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe
+#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x300000
+#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14
+#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0xc00000
+#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16
+#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x3000000
+#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18
+#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0xc000000
+#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a
+#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000
+#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c
+#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL_MASK 0x20000000
+#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT 0x1d
+#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000
+#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e
+#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000
+#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f
+#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0xfff
+#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0
+#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xc0000000
+#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e
+#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x7ffff
+#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0
+#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0xffffff
+#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0
+#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0xff
+#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0
+#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x1000
+#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc
+#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x2000
+#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd
+#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x4000
+#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe
+#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x8000
+#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf
+#define SQ_IND_INDEX__WAVE_ID_MASK 0xf
+#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0
+#define SQ_IND_INDEX__SIMD_ID_MASK 0x30
+#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4
+#define SQ_IND_INDEX__THREAD_ID_MASK 0xfc0
+#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6
+#define SQ_IND_INDEX__AUTO_INCR_MASK 0x1000
+#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc
+#define SQ_IND_INDEX__FORCE_READ_MASK 0x2000
+#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd
+#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x4000
+#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe
+#define SQ_IND_INDEX__UNINDEXED_MASK 0x8000
+#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf
+#define SQ_IND_INDEX__INDEX_MASK 0xffff0000
+#define SQ_IND_INDEX__INDEX__SHIFT 0x10
+#define SQ_CMD__CMD_MASK 0x7
+#define SQ_CMD__CMD__SHIFT 0x0
+#define SQ_CMD__MODE_MASK 0x70
+#define SQ_CMD__MODE__SHIFT 0x4
+#define SQ_CMD__CHECK_VMID_MASK 0x80
+#define SQ_CMD__CHECK_VMID__SHIFT 0x7
+#define SQ_CMD__DATA_MASK 0x700
+#define SQ_CMD__DATA__SHIFT 0x8
+#define SQ_CMD__WAVE_ID_MASK 0xf0000
+#define SQ_CMD__WAVE_ID__SHIFT 0x10
+#define SQ_CMD__SIMD_ID_MASK 0x300000
+#define SQ_CMD__SIMD_ID__SHIFT 0x14
+#define SQ_CMD__QUEUE_ID_MASK 0x7000000
+#define SQ_CMD__QUEUE_ID__SHIFT 0x18
+#define SQ_CMD__VM_ID_MASK 0xf0000000
+#define SQ_CMD__VM_ID__SHIFT 0x1c
+#define SQ_IND_DATA__DATA_MASK 0xffffffff
+#define SQ_IND_DATA__DATA__SHIFT 0x0
+#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0xff
+#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0
+#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0xff
+#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0
+#define SQ_HV_VMID_CTRL__DEFAULT_VMID_MASK 0xf
+#define SQ_HV_VMID_CTRL__DEFAULT_VMID__SHIFT 0x0
+#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK_MASK 0xffff0
+#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK__SHIFT 0x4
+#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xffffffff
+#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0
+#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffff
+#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0
+#define SQ_WAVE_PC_LO__PC_LO_MASK 0xffffffff
+#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0
+#define SQ_WAVE_PC_HI__PC_HI_MASK 0xff
+#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0
+#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x7
+#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0
+#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x8
+#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3
+#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x10
+#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4
+#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0xe0
+#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5
+#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x300
+#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8
+#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0xc00
+#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa
+#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0xf0000
+#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10
+#define SQ_WAVE_IB_DBG0__MISC_CNT_MASK 0xf00000
+#define SQ_WAVE_IB_DBG0__MISC_CNT__SHIFT 0x14
+#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x3000000
+#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18
+#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x4000000
+#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a
+#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000
+#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b
+#define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000
+#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d
+#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000
+#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e
+#define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x1
+#define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0
+#define SQ_WAVE_IB_DBG1__XNACK_MASK 0x2
+#define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1
+#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x4
+#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2
+#define SQ_WAVE_IB_DBG1__XCNT_MASK 0xf0
+#define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4
+#define SQ_WAVE_IB_DBG1__QCNT_MASK 0xf00
+#define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0x8
+#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xffffffff
+#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0
+#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xffffffff
+#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0
+#define SQ_WAVE_STATUS__SCC_MASK 0x1
+#define SQ_WAVE_STATUS__SCC__SHIFT 0x0
+#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x6
+#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1
+#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x18
+#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3
+#define SQ_WAVE_STATUS__PRIV_MASK 0x20
+#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5
+#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x40
+#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6
+#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x80
+#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7
+#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x100
+#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8
+#define SQ_WAVE_STATUS__EXECZ_MASK 0x200
+#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9
+#define SQ_WAVE_STATUS__VCCZ_MASK 0x400
+#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa
+#define SQ_WAVE_STATUS__IN_TG_MASK 0x800
+#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb
+#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x1000
+#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc
+#define SQ_WAVE_STATUS__HALT_MASK 0x2000
+#define SQ_WAVE_STATUS__HALT__SHIFT 0xd
+#define SQ_WAVE_STATUS__TRAP_MASK 0x4000
+#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe
+#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x8000
+#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf
+#define SQ_WAVE_STATUS__VALID_MASK 0x10000
+#define SQ_WAVE_STATUS__VALID__SHIFT 0x10
+#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x20000
+#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11
+#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x40000
+#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12
+#define SQ_WAVE_STATUS__PERF_EN_MASK 0x80000
+#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13
+#define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x100000
+#define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x14
+#define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x200000
+#define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x15
+#define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x400000
+#define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16
+#define SQ_WAVE_STATUS__INST_ATC_MASK 0x800000
+#define SQ_WAVE_STATUS__INST_ATC__SHIFT 0x17
+#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x8000000
+#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b
+#define SQ_WAVE_MODE__FP_ROUND_MASK 0xf
+#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0
+#define SQ_WAVE_MODE__FP_DENORM_MASK 0xf0
+#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4
+#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x100
+#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8
+#define SQ_WAVE_MODE__IEEE_MASK 0x200
+#define SQ_WAVE_MODE__IEEE__SHIFT 0x9
+#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x400
+#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa
+#define SQ_WAVE_MODE__DEBUG_EN_MASK 0x800
+#define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0xb
+#define SQ_WAVE_MODE__EXCP_EN_MASK 0x1ff000
+#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc
+#define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x8000000
+#define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b
+#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000
+#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c
+#define SQ_WAVE_MODE__CSP_MASK 0xe0000000
+#define SQ_WAVE_MODE__CSP__SHIFT 0x1d
+#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x1ff
+#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0
+#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x400
+#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa
+#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x3f0000
+#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10
+#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xe0000000
+#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d
+#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0xf
+#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0
+#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x30
+#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4
+#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0xc0
+#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6
+#define SQ_WAVE_HW_ID__CU_ID_MASK 0xf00
+#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8
+#define SQ_WAVE_HW_ID__SH_ID_MASK 0x1000
+#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc
+#define SQ_WAVE_HW_ID__SE_ID_MASK 0x6000
+#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd
+#define SQ_WAVE_HW_ID__TG_ID_MASK 0xf0000
+#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10
+#define SQ_WAVE_HW_ID__VM_ID_MASK 0xf00000
+#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14
+#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x7000000
+#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18
+#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000
+#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b
+#define SQ_WAVE_HW_ID__ME_ID_MASK 0xc0000000
+#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e
+#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x3f
+#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0
+#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x3f00
+#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8
+#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x3f0000
+#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10
+#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0xf000000
+#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18
+#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0xff
+#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0
+#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x1ff000
+#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc
+#define SQ_WAVE_IB_STS__VM_CNT_MASK 0xf
+#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0
+#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x70
+#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4
+#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0xf00
+#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8
+#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x7000
+#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc
+#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x8000
+#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf
+#define SQ_WAVE_IB_STS__RCNT_MASK 0xf0000
+#define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10
+#define SQ_WAVE_M0__M0_MASK 0xffffffff
+#define SQ_WAVE_M0__M0__SHIFT 0x0
+#define SQ_WAVE_TBA_LO__ADDR_LO_MASK 0xffffffff
+#define SQ_WAVE_TBA_LO__ADDR_LO__SHIFT 0x0
+#define SQ_WAVE_TBA_HI__ADDR_HI_MASK 0xff
+#define SQ_WAVE_TBA_HI__ADDR_HI__SHIFT 0x0
+#define SQ_WAVE_TMA_LO__ADDR_LO_MASK 0xffffffff
+#define SQ_WAVE_TMA_LO__ADDR_LO__SHIFT 0x0
+#define SQ_WAVE_TMA_HI__ADDR_HI_MASK 0xff
+#define SQ_WAVE_TMA_HI__ADDR_HI__SHIFT 0x0
+#define SQ_WAVE_TTMP0__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP1__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP2__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP3__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP4__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP5__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP6__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP7__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP8__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP9__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP10__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP11__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0
+#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x1
+#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x0
+#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x2
+#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x1
+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0xfff0
+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x4
+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0xfff0000
+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x10
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0xff
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x0
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0xff00
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x8
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0xff0000
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x10
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x18
+#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0xf
+#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x0
+#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x3f0
+#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x4
+#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x1
+#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x0
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x3f0
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x4
+#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0xff
+#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x0
+#define SH_MEM_BASES__PRIVATE_BASE_MASK 0xffff
+#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0
+#define SH_MEM_BASES__SHARED_BASE_MASK 0xffff0000
+#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10
+#define SH_MEM_APE1_BASE__BASE_MASK 0xffffffff
+#define SH_MEM_APE1_BASE__BASE__SHIFT 0x0
+#define SH_MEM_APE1_LIMIT__LIMIT_MASK 0xffffffff
+#define SH_MEM_APE1_LIMIT__LIMIT__SHIFT 0x0
+#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x3
+#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0
+#define SH_MEM_CONFIG__PRIVATE_ATC_MASK 0x4
+#define SH_MEM_CONFIG__PRIVATE_ATC__SHIFT 0x2
+#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x18
+#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3
+#define SH_MEM_CONFIG__DEFAULT_MTYPE_MASK 0xe0
+#define SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT 0x5
+#define SH_MEM_CONFIG__APE1_MTYPE_MASK 0x700
+#define SH_MEM_CONFIG__APE1_MTYPE__SHIFT 0x8
+#define SH_MEM_CONFIG__APE1_ATC_MASK 0x800
+#define SH_MEM_CONFIG__APE1_ATC__SHIFT 0xb
+#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x1e0
+#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x600
+#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9
+#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xf800
+#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x1e0
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x600
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xffff0000
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0xffffff
+#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x20
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x3c0
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x3c00
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0xc000
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xffff0000
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xffff
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xffff0000
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xffffffff
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x20
+#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x3c0
+#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3c00
+#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xc000
+#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0xff0
+#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000
+#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc
+#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xe000
+#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x20
+#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x3c0
+#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x3c00
+#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0xc000
+#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x1f0000
+#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x200000
+#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15
+#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1fc00000
+#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xe0000000
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x60
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x180
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x200
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x1c00
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x4000
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x8000
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xffff0000
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xffffffff
+#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x60
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x180
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0xfe00
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xffff0000
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0xffff
+#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x20
+#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x1c0
+#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xfc00
+#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x60
+#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x300
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0xc00
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x3000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0xc000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x30000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0xc0000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x300000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0xc00000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x3000000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0xc000000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x20
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x3c0
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0xc00
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x1fff000
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xfe000000
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x3f
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x7ffc0
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xfff80000
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13
+#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xffffffff
+#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0
+#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0xffff
+#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0
+#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x4000000
+#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a
+#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x8000000
+#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b
+#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000
+#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c
+#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000
+#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f
+#define SQC_GATCL1_CNTL__RESERVED_MASK 0x3ffff
+#define SQC_GATCL1_CNTL__RESERVED__SHIFT 0x0
+#define SQC_GATCL1_CNTL__DCACHE_INVALIDATE_ALL_VMID_MASK 0x40000
+#define SQC_GATCL1_CNTL__DCACHE_INVALIDATE_ALL_VMID__SHIFT 0x12
+#define SQC_GATCL1_CNTL__DCACHE_FORCE_MISS_MASK 0x80000
+#define SQC_GATCL1_CNTL__DCACHE_FORCE_MISS__SHIFT 0x13
+#define SQC_GATCL1_CNTL__DCACHE_FORCE_IN_ORDER_MASK 0x100000
+#define SQC_GATCL1_CNTL__DCACHE_FORCE_IN_ORDER__SHIFT 0x14
+#define SQC_GATCL1_CNTL__DCACHE_REDUCE_FIFO_DEPTH_BY_2_MASK 0x600000
+#define SQC_GATCL1_CNTL__DCACHE_REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x15
+#define SQC_GATCL1_CNTL__DCACHE_REDUCE_CACHE_SIZE_BY_2_MASK 0x1800000
+#define SQC_GATCL1_CNTL__DCACHE_REDUCE_CACHE_SIZE_BY_2__SHIFT 0x17
+#define SQC_GATCL1_CNTL__ICACHE_INVALIDATE_ALL_VMID_MASK 0x2000000
+#define SQC_GATCL1_CNTL__ICACHE_INVALIDATE_ALL_VMID__SHIFT 0x19
+#define SQC_GATCL1_CNTL__ICACHE_FORCE_MISS_MASK 0x4000000
+#define SQC_GATCL1_CNTL__ICACHE_FORCE_MISS__SHIFT 0x1a
+#define SQC_GATCL1_CNTL__ICACHE_FORCE_IN_ORDER_MASK 0x8000000
+#define SQC_GATCL1_CNTL__ICACHE_FORCE_IN_ORDER__SHIFT 0x1b
+#define SQC_GATCL1_CNTL__ICACHE_REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000
+#define SQC_GATCL1_CNTL__ICACHE_REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
+#define SQC_GATCL1_CNTL__ICACHE_REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000
+#define SQC_GATCL1_CNTL__ICACHE_REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
+#define SQC_ATC_EDC_GATCL1_CNT__ICACHE_DATA_SEC_MASK 0xff
+#define SQC_ATC_EDC_GATCL1_CNT__ICACHE_DATA_SEC__SHIFT 0x0
+#define SQC_ATC_EDC_GATCL1_CNT__DCACHE_DATA_SEC_MASK 0xff0000
+#define SQC_ATC_EDC_GATCL1_CNT__DCACHE_DATA_SEC__SHIFT 0x10
+#define SQ_INTERRUPT_WORD_CMN__SE_ID_MASK 0x3000000
+#define SQ_INTERRUPT_WORD_CMN__SE_ID__SHIFT 0x18
+#define SQ_INTERRUPT_WORD_CMN__ENCODING_MASK 0xc000000
+#define SQ_INTERRUPT_WORD_CMN__ENCODING__SHIFT 0x1a
+#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK 0x1
+#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT 0x0
+#define SQ_INTERRUPT_WORD_AUTO__WLT_MASK 0x2
+#define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT 0x1
+#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL_MASK 0x4
+#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL__SHIFT 0x2
+#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP_MASK 0x8
+#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP__SHIFT 0x3
+#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP_MASK 0x10
+#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP__SHIFT 0x4
+#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW_MASK 0x20
+#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW__SHIFT 0x5
+#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW_MASK 0x40
+#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW__SHIFT 0x6
+#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW_MASK 0x80
+#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW__SHIFT 0x7
+#define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK 0x3000000
+#define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT 0x18
+#define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK 0xc000000
+#define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT 0x1a
+#define SQ_INTERRUPT_WORD_WAVE__DATA_MASK 0xff
+#define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT 0x0
+#define SQ_INTERRUPT_WORD_WAVE__SH_ID_MASK 0x100
+#define SQ_INTERRUPT_WORD_WAVE__SH_ID__SHIFT 0x8
+#define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK 0x200
+#define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT 0x9
+#define SQ_INTERRUPT_WORD_WAVE__VM_ID_MASK 0x3c00
+#define SQ_INTERRUPT_WORD_WAVE__VM_ID__SHIFT 0xa
+#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK 0x3c000
+#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT 0xe
+#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK 0xc0000
+#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT 0x12
+#define SQ_INTERRUPT_WORD_WAVE__CU_ID_MASK 0xf00000
+#define SQ_INTERRUPT_WORD_WAVE__CU_ID__SHIFT 0x14
+#define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK 0x3000000
+#define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT 0x18
+#define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK 0xc000000
+#define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT 0x1a
+#define SQ_SOP2__SSRC0_MASK 0xff
+#define SQ_SOP2__SSRC0__SHIFT 0x0
+#define SQ_SOP2__SSRC1_MASK 0xff00
+#define SQ_SOP2__SSRC1__SHIFT 0x8
+#define SQ_SOP2__SDST_MASK 0x7f0000
+#define SQ_SOP2__SDST__SHIFT 0x10
+#define SQ_SOP2__OP_MASK 0x3f800000
+#define SQ_SOP2__OP__SHIFT 0x17
+#define SQ_SOP2__ENCODING_MASK 0xc0000000
+#define SQ_SOP2__ENCODING__SHIFT 0x1e
+#define SQ_VOP1__SRC0_MASK 0x1ff
+#define SQ_VOP1__SRC0__SHIFT 0x0
+#define SQ_VOP1__OP_MASK 0x1fe00
+#define SQ_VOP1__OP__SHIFT 0x9
+#define SQ_VOP1__VDST_MASK 0x1fe0000
+#define SQ_VOP1__VDST__SHIFT 0x11
+#define SQ_VOP1__ENCODING_MASK 0xfe000000
+#define SQ_VOP1__ENCODING__SHIFT 0x19
+#define SQ_MTBUF_1__VADDR_MASK 0xff
+#define SQ_MTBUF_1__VADDR__SHIFT 0x0
+#define SQ_MTBUF_1__VDATA_MASK 0xff00
+#define SQ_MTBUF_1__VDATA__SHIFT 0x8
+#define SQ_MTBUF_1__SRSRC_MASK 0x1f0000
+#define SQ_MTBUF_1__SRSRC__SHIFT 0x10
+#define SQ_MTBUF_1__SLC_MASK 0x400000
+#define SQ_MTBUF_1__SLC__SHIFT 0x16
+#define SQ_MTBUF_1__TFE_MASK 0x800000
+#define SQ_MTBUF_1__TFE__SHIFT 0x17
+#define SQ_MTBUF_1__SOFFSET_MASK 0xff000000
+#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18
+#define SQ_EXP_1__VSRC0_MASK 0xff
+#define SQ_EXP_1__VSRC0__SHIFT 0x0
+#define SQ_EXP_1__VSRC1_MASK 0xff00
+#define SQ_EXP_1__VSRC1__SHIFT 0x8
+#define SQ_EXP_1__VSRC2_MASK 0xff0000
+#define SQ_EXP_1__VSRC2__SHIFT 0x10
+#define SQ_EXP_1__VSRC3_MASK 0xff000000
+#define SQ_EXP_1__VSRC3__SHIFT 0x18
+#define SQ_MUBUF_1__VADDR_MASK 0xff
+#define SQ_MUBUF_1__VADDR__SHIFT 0x0
+#define SQ_MUBUF_1__VDATA_MASK 0xff00
+#define SQ_MUBUF_1__VDATA__SHIFT 0x8
+#define SQ_MUBUF_1__SRSRC_MASK 0x1f0000
+#define SQ_MUBUF_1__SRSRC__SHIFT 0x10
+#define SQ_MUBUF_1__TFE_MASK 0x800000
+#define SQ_MUBUF_1__TFE__SHIFT 0x17
+#define SQ_MUBUF_1__SOFFSET_MASK 0xff000000
+#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18
+#define SQ_SMEM_1__OFFSET_MASK 0xfffff
+#define SQ_SMEM_1__OFFSET__SHIFT 0x0
+#define SQ_INST__ENCODING_MASK 0xffffffff
+#define SQ_INST__ENCODING__SHIFT 0x0
+#define SQ_EXP_0__EN_MASK 0xf
+#define SQ_EXP_0__EN__SHIFT 0x0
+#define SQ_EXP_0__TGT_MASK 0x3f0
+#define SQ_EXP_0__TGT__SHIFT 0x4
+#define SQ_EXP_0__COMPR_MASK 0x400
+#define SQ_EXP_0__COMPR__SHIFT 0xa
+#define SQ_EXP_0__DONE_MASK 0x800
+#define SQ_EXP_0__DONE__SHIFT 0xb
+#define SQ_EXP_0__VM_MASK 0x1000
+#define SQ_EXP_0__VM__SHIFT 0xc
+#define SQ_EXP_0__ENCODING_MASK 0xfc000000
+#define SQ_EXP_0__ENCODING__SHIFT 0x1a
+#define SQ_MUBUF_0__OFFSET_MASK 0xfff
+#define SQ_MUBUF_0__OFFSET__SHIFT 0x0
+#define SQ_MUBUF_0__OFFEN_MASK 0x1000
+#define SQ_MUBUF_0__OFFEN__SHIFT 0xc
+#define SQ_MUBUF_0__IDXEN_MASK 0x2000
+#define SQ_MUBUF_0__IDXEN__SHIFT 0xd
+#define SQ_MUBUF_0__GLC_MASK 0x4000
+#define SQ_MUBUF_0__GLC__SHIFT 0xe
+#define SQ_MUBUF_0__LDS_MASK 0x10000
+#define SQ_MUBUF_0__LDS__SHIFT 0x10
+#define SQ_MUBUF_0__SLC_MASK 0x20000
+#define SQ_MUBUF_0__SLC__SHIFT 0x11
+#define SQ_MUBUF_0__OP_MASK 0x1fc0000
+#define SQ_MUBUF_0__OP__SHIFT 0x12
+#define SQ_MUBUF_0__ENCODING_MASK 0xfc000000
+#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a
+#define SQ_VOP_SDWA__SRC0_MASK 0xff
+#define SQ_VOP_SDWA__SRC0__SHIFT 0x0
+#define SQ_VOP_SDWA__DST_SEL_MASK 0x700
+#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8
+#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x1800
+#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb
+#define SQ_VOP_SDWA__CLAMP_MASK 0x2000
+#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd
+#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x70000
+#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10
+#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x80000
+#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13
+#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x100000
+#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14
+#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x200000
+#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15
+#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x7000000
+#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18
+#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x8000000
+#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b
+#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000
+#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c
+#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000
+#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d
+#define SQ_VOP3_0__VDST_MASK 0xff
+#define SQ_VOP3_0__VDST__SHIFT 0x0
+#define SQ_VOP3_0__ABS_MASK 0x700
+#define SQ_VOP3_0__ABS__SHIFT 0x8
+#define SQ_VOP3_0__CLAMP_MASK 0x8000
+#define SQ_VOP3_0__CLAMP__SHIFT 0xf
+#define SQ_VOP3_0__OP_MASK 0x3ff0000
+#define SQ_VOP3_0__OP__SHIFT 0x10
+#define SQ_VOP3_0__ENCODING_MASK 0xfc000000
+#define SQ_VOP3_0__ENCODING__SHIFT 0x1a
+#define SQ_VOP2__SRC0_MASK 0x1ff
+#define SQ_VOP2__SRC0__SHIFT 0x0
+#define SQ_VOP2__VSRC1_MASK 0x1fe00
+#define SQ_VOP2__VSRC1__SHIFT 0x9
+#define SQ_VOP2__VDST_MASK 0x1fe0000
+#define SQ_VOP2__VDST__SHIFT 0x11
+#define SQ_VOP2__OP_MASK 0x7e000000
+#define SQ_VOP2__OP__SHIFT 0x19
+#define SQ_VOP2__ENCODING_MASK 0x80000000
+#define SQ_VOP2__ENCODING__SHIFT 0x1f
+#define SQ_MTBUF_0__OFFSET_MASK 0xfff
+#define SQ_MTBUF_0__OFFSET__SHIFT 0x0
+#define SQ_MTBUF_0__OFFEN_MASK 0x1000
+#define SQ_MTBUF_0__OFFEN__SHIFT 0xc
+#define SQ_MTBUF_0__IDXEN_MASK 0x2000
+#define SQ_MTBUF_0__IDXEN__SHIFT 0xd
+#define SQ_MTBUF_0__GLC_MASK 0x4000
+#define SQ_MTBUF_0__GLC__SHIFT 0xe
+#define SQ_MTBUF_0__OP_MASK 0x78000
+#define SQ_MTBUF_0__OP__SHIFT 0xf
+#define SQ_MTBUF_0__DFMT_MASK 0x780000
+#define SQ_MTBUF_0__DFMT__SHIFT 0x13
+#define SQ_MTBUF_0__NFMT_MASK 0x3800000
+#define SQ_MTBUF_0__NFMT__SHIFT 0x17
+#define SQ_MTBUF_0__ENCODING_MASK 0xfc000000
+#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a
+#define SQ_SOPP__SIMM16_MASK 0xffff
+#define SQ_SOPP__SIMM16__SHIFT 0x0
+#define SQ_SOPP__OP_MASK 0x7f0000
+#define SQ_SOPP__OP__SHIFT 0x10
+#define SQ_SOPP__ENCODING_MASK 0xff800000
+#define SQ_SOPP__ENCODING__SHIFT 0x17
+#define SQ_FLAT_0__GLC_MASK 0x10000
+#define SQ_FLAT_0__GLC__SHIFT 0x10
+#define SQ_FLAT_0__SLC_MASK 0x20000
+#define SQ_FLAT_0__SLC__SHIFT 0x11
+#define SQ_FLAT_0__OP_MASK 0x1fc0000
+#define SQ_FLAT_0__OP__SHIFT 0x12
+#define SQ_FLAT_0__ENCODING_MASK 0xfc000000
+#define SQ_FLAT_0__ENCODING__SHIFT 0x1a
+#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0xff
+#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0
+#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x7f00
+#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8
+#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x8000
+#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf
+#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x3ff0000
+#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10
+#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xfc000000
+#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a
+#define SQ_MIMG_1__VADDR_MASK 0xff
+#define SQ_MIMG_1__VADDR__SHIFT 0x0
+#define SQ_MIMG_1__VDATA_MASK 0xff00
+#define SQ_MIMG_1__VDATA__SHIFT 0x8
+#define SQ_MIMG_1__SRSRC_MASK 0x1f0000
+#define SQ_MIMG_1__SRSRC__SHIFT 0x10
+#define SQ_MIMG_1__SSAMP_MASK 0x3e00000
+#define SQ_MIMG_1__SSAMP__SHIFT 0x15
+#define SQ_MIMG_1__D16_MASK 0x80000000
+#define SQ_MIMG_1__D16__SHIFT 0x1f
+#define SQ_SOP1__SSRC0_MASK 0xff
+#define SQ_SOP1__SSRC0__SHIFT 0x0
+#define SQ_SOP1__OP_MASK 0xff00
+#define SQ_SOP1__OP__SHIFT 0x8
+#define SQ_SOP1__SDST_MASK 0x7f0000
+#define SQ_SOP1__SDST__SHIFT 0x10
+#define SQ_SOP1__ENCODING_MASK 0xff800000
+#define SQ_SOP1__ENCODING__SHIFT 0x17
+#define SQ_SOPC__SSRC0_MASK 0xff
+#define SQ_SOPC__SSRC0__SHIFT 0x0
+#define SQ_SOPC__SSRC1_MASK 0xff00
+#define SQ_SOPC__SSRC1__SHIFT 0x8
+#define SQ_SOPC__OP_MASK 0x7f0000
+#define SQ_SOPC__OP__SHIFT 0x10
+#define SQ_SOPC__ENCODING_MASK 0xff800000
+#define SQ_SOPC__ENCODING__SHIFT 0x17
+#define SQ_FLAT_1__ADDR_MASK 0xff
+#define SQ_FLAT_1__ADDR__SHIFT 0x0
+#define SQ_FLAT_1__DATA_MASK 0xff00
+#define SQ_FLAT_1__DATA__SHIFT 0x8
+#define SQ_FLAT_1__TFE_MASK 0x800000
+#define SQ_FLAT_1__TFE__SHIFT 0x17
+#define SQ_FLAT_1__VDST_MASK 0xff000000
+#define SQ_FLAT_1__VDST__SHIFT 0x18
+#define SQ_DS_1__ADDR_MASK 0xff
+#define SQ_DS_1__ADDR__SHIFT 0x0
+#define SQ_DS_1__DATA0_MASK 0xff00
+#define SQ_DS_1__DATA0__SHIFT 0x8
+#define SQ_DS_1__DATA1_MASK 0xff0000
+#define SQ_DS_1__DATA1__SHIFT 0x10
+#define SQ_DS_1__VDST_MASK 0xff000000
+#define SQ_DS_1__VDST__SHIFT 0x18
+#define SQ_VOP3_1__SRC0_MASK 0x1ff
+#define SQ_VOP3_1__SRC0__SHIFT 0x0
+#define SQ_VOP3_1__SRC1_MASK 0x3fe00
+#define SQ_VOP3_1__SRC1__SHIFT 0x9
+#define SQ_VOP3_1__SRC2_MASK 0x7fc0000
+#define SQ_VOP3_1__SRC2__SHIFT 0x12
+#define SQ_VOP3_1__OMOD_MASK 0x18000000
+#define SQ_VOP3_1__OMOD__SHIFT 0x1b
+#define SQ_VOP3_1__NEG_MASK 0xe0000000
+#define SQ_VOP3_1__NEG__SHIFT 0x1d
+#define SQ_SMEM_0__SBASE_MASK 0x3f
+#define SQ_SMEM_0__SBASE__SHIFT 0x0
+#define SQ_SMEM_0__SDATA_MASK 0x1fc0
+#define SQ_SMEM_0__SDATA__SHIFT 0x6
+#define SQ_SMEM_0__GLC_MASK 0x10000
+#define SQ_SMEM_0__GLC__SHIFT 0x10
+#define SQ_SMEM_0__IMM_MASK 0x20000
+#define SQ_SMEM_0__IMM__SHIFT 0x11
+#define SQ_SMEM_0__OP_MASK 0x3fc0000
+#define SQ_SMEM_0__OP__SHIFT 0x12
+#define SQ_SMEM_0__ENCODING_MASK 0xfc000000
+#define SQ_SMEM_0__ENCODING__SHIFT 0x1a
+#define SQ_MIMG_0__DMASK_MASK 0xf00
+#define SQ_MIMG_0__DMASK__SHIFT 0x8
+#define SQ_MIMG_0__UNORM_MASK 0x1000
+#define SQ_MIMG_0__UNORM__SHIFT 0xc
+#define SQ_MIMG_0__GLC_MASK 0x2000
+#define SQ_MIMG_0__GLC__SHIFT 0xd
+#define SQ_MIMG_0__DA_MASK 0x4000
+#define SQ_MIMG_0__DA__SHIFT 0xe
+#define SQ_MIMG_0__R128_MASK 0x8000
+#define SQ_MIMG_0__R128__SHIFT 0xf
+#define SQ_MIMG_0__TFE_MASK 0x10000
+#define SQ_MIMG_0__TFE__SHIFT 0x10
+#define SQ_MIMG_0__LWE_MASK 0x20000
+#define SQ_MIMG_0__LWE__SHIFT 0x11
+#define SQ_MIMG_0__OP_MASK 0x1fc0000
+#define SQ_MIMG_0__OP__SHIFT 0x12
+#define SQ_MIMG_0__SLC_MASK 0x2000000
+#define SQ_MIMG_0__SLC__SHIFT 0x19
+#define SQ_MIMG_0__ENCODING_MASK 0xfc000000
+#define SQ_MIMG_0__ENCODING__SHIFT 0x1a
+#define SQ_SOPK__SIMM16_MASK 0xffff
+#define SQ_SOPK__SIMM16__SHIFT 0x0
+#define SQ_SOPK__SDST_MASK 0x7f0000
+#define SQ_SOPK__SDST__SHIFT 0x10
+#define SQ_SOPK__OP_MASK 0xf800000
+#define SQ_SOPK__OP__SHIFT 0x17
+#define SQ_SOPK__ENCODING_MASK 0xf0000000
+#define SQ_SOPK__ENCODING__SHIFT 0x1c
+#define SQ_DS_0__OFFSET0_MASK 0xff
+#define SQ_DS_0__OFFSET0__SHIFT 0x0
+#define SQ_DS_0__OFFSET1_MASK 0xff00
+#define SQ_DS_0__OFFSET1__SHIFT 0x8
+#define SQ_DS_0__GDS_MASK 0x10000
+#define SQ_DS_0__GDS__SHIFT 0x10
+#define SQ_DS_0__OP_MASK 0x1fe0000
+#define SQ_DS_0__OP__SHIFT 0x11
+#define SQ_DS_0__ENCODING_MASK 0xfc000000
+#define SQ_DS_0__ENCODING__SHIFT 0x1a
+#define SQ_VOP_DPP__SRC0_MASK 0xff
+#define SQ_VOP_DPP__SRC0__SHIFT 0x0
+#define SQ_VOP_DPP__DPP_CTRL_MASK 0x1ff00
+#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8
+#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x80000
+#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13
+#define SQ_VOP_DPP__SRC0_NEG_MASK 0x100000
+#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14
+#define SQ_VOP_DPP__SRC0_ABS_MASK 0x200000
+#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15
+#define SQ_VOP_DPP__SRC1_NEG_MASK 0x400000
+#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16
+#define SQ_VOP_DPP__SRC1_ABS_MASK 0x800000
+#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17
+#define SQ_VOP_DPP__BANK_MASK_MASK 0xf000000
+#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18
+#define SQ_VOP_DPP__ROW_MASK_MASK 0xf0000000
+#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c
+#define SQ_VOPC__SRC0_MASK 0x1ff
+#define SQ_VOPC__SRC0__SHIFT 0x0
+#define SQ_VOPC__VSRC1_MASK 0x1fe00
+#define SQ_VOPC__VSRC1__SHIFT 0x9
+#define SQ_VOPC__OP_MASK 0x1fe0000
+#define SQ_VOPC__OP__SHIFT 0x11
+#define SQ_VOPC__ENCODING_MASK 0xfe000000
+#define SQ_VOPC__ENCODING__SHIFT 0x19
+#define SQ_VINTRP__VSRC_MASK 0xff
+#define SQ_VINTRP__VSRC__SHIFT 0x0
+#define SQ_VINTRP__ATTRCHAN_MASK 0x300
+#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8
+#define SQ_VINTRP__ATTR_MASK 0xfc00
+#define SQ_VINTRP__ATTR__SHIFT 0xa
+#define SQ_VINTRP__OP_MASK 0x30000
+#define SQ_VINTRP__OP__SHIFT 0x10
+#define SQ_VINTRP__VDST_MASK 0x3fc0000
+#define SQ_VINTRP__VDST__SHIFT 0x12
+#define SQ_VINTRP__ENCODING_MASK 0xfc000000
+#define SQ_VINTRP__ENCODING__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0xf
+#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0xfff000
+#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0xf
+#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0xfff000
+#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0xf
+#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0xfff000
+#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0xf
+#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0xfff000
+#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0xf
+#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0xfff000
+#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f
+#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x1
+#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x0
+#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x2
+#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x1
+#define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x4
+#define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x2
+#define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x8
+#define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x3
+#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x10
+#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x4
+#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x20
+#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x5
+#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x40
+#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x6
+#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x80
+#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x7
+#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x100
+#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x8
+#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x200
+#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x9
+#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x400
+#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0xa
+#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x800
+#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0xb
+#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x1000
+#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0xc
+#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x2000
+#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0xd
+#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x4000
+#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0xe
+#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x8000
+#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0xf
+#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x10000
+#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x10
+#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x20000
+#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x11
+#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x40000
+#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x12
+#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x80000
+#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x13
+#define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x100000
+#define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x14
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x200000
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x15
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x400000
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x16
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x800000
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x17
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x1000000
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x18
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x2000000
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x19
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x4000000
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x1a
+#define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x8000000
+#define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x1b
+#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000
+#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x1c
+#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000
+#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d
+#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000
+#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x1e
+#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000
+#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x1f
+#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY_MASK 0x1
+#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY__SHIFT 0x0
+#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK 0x2
+#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT 0x1
+#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK 0x4
+#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT 0x2
+#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK 0x8
+#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT 0x3
+#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK 0x10
+#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT 0x4
+#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK 0x20
+#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT 0x5
+#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK 0x40
+#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT 0x6
+#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK 0x80
+#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT 0x7
+#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK 0x100
+#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT 0x8
+#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK 0x200
+#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT 0x9
+#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK 0x400
+#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT 0xa
+#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK 0x800
+#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT 0xb
+#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK 0x1000
+#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT 0xc
+#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK 0x2000
+#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT 0xd
+#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK 0x4000
+#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT 0xe
+#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID_MASK 0x8000
+#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID__SHIFT 0xf
+#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK 0x10000
+#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x10
+#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK 0x20000
+#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT 0x11
+#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID_MASK 0x40000
+#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID__SHIFT 0x12
+#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK 0x80000
+#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x13
+#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK 0x100000
+#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x14
+#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID_MASK 0x200000
+#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID__SHIFT 0x15
+#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK 0x400000
+#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x16
+#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK 0x800000
+#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT 0x17
+#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID_MASK 0x1000000
+#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID__SHIFT 0x18
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x2000000
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x19
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x4000000
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x1a
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x8000000
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x1b
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x10000000
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x1c
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x20000000
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x1d
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x40000000
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x1e
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x80000000
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x1f
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x1
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x0
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x2
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x1
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x4
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x2
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x8
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x3
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x10
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x4
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x20
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x5
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x40
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x6
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x80
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x7
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x100
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x8
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x200
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x9
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x400
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0xa
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x800
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0xb
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x1000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0xc
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x2000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0xd
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x4000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0xe
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x8000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0xf
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x10000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x10
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x20000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x11
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x40000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x12
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x80000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x13
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x100000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x14
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x200000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x15
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x400000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x16
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x800000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x17
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x1000000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x18
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x2000000
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x19
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x4000000
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x1a
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x8000000
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x1b
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x10000000
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x1c
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x20000000
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x1d
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x40000000
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x1e
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x80000000
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x1f
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x1
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x0
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x2
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x1
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x4
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x2
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x8
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x3
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x10
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x4
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x20
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x5
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x40
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x6
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x80
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x7
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x100
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x8
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x200
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x9
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x400
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0xa
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x800
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0xb
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x1000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0xc
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x2000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0xd
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x4000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0xe
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x8000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0xf
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x10000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x10
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x20000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x11
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x40000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x12
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x80000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x13
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x100000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x14
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x200000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x15
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x400000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x16
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x800000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x17
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x1000000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x18
+#define SX_DEBUG_BUSY_4__RESERVED_MASK 0xfe000000
+#define SX_DEBUG_BUSY_4__RESERVED__SHIFT 0x19
+#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x7f
+#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0
+#define SX_DEBUG_1__DEBUG_DATA_MASK 0xffffff80
+#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x7
+#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
+#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
+#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
+#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
+#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
+#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
+#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
+#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
+#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCC_CTRL__CACHE_SIZE_MASK 0x3
+#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0
+#define TCC_CTRL__RATE_MASK 0xc
+#define TCC_CTRL__RATE__SHIFT 0x2
+#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0xf0
+#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4
+#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0xf00
+#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8
+#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0xf000
+#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc
+#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0xf0000
+#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10
+#define TCC_CTRL__WB_OR_INV_ALL_VMIDS_MASK 0x100000
+#define TCC_CTRL__WB_OR_INV_ALL_VMIDS__SHIFT 0x14
+#define TCC_CTRL__MDC_SIZE_MASK 0x3000000
+#define TCC_CTRL__MDC_SIZE__SHIFT 0x18
+#define TCC_CTRL__MDC_SECTOR_SIZE_MASK 0xc000000
+#define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT 0x1a
+#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xf0000000
+#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c
+#define TCC_EDC_CNT__SEC_COUNT_MASK 0xff
+#define TCC_EDC_CNT__SEC_COUNT__SHIFT 0x0
+#define TCC_EDC_CNT__DED_COUNT_MASK 0xff0000
+#define TCC_EDC_CNT__DED_COUNT__SHIFT 0x10
+#define TCC_REDUNDANCY__MC_SEL0_MASK 0x1
+#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0
+#define TCC_REDUNDANCY__MC_SEL1_MASK 0x2
+#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1
+#define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x2
+#define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x1
+#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x3
+#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0
+#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x4
+#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
+#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
+#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
+#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
+#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
+#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
+#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
+#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000
+#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
+#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000
+#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
+#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
+#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000
+#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
+#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000
+#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
+#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
+#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCA_CTRL__HOLE_TIMEOUT_MASK 0xf
+#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0
+#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
+#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
+#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000
+#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
+#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000
+#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
+#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
+#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000
+#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
+#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000
+#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
+#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
+#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff
+#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
+#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff
+#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
+#define TD_CNTL__SYNC_PHASE_SH_MASK 0x3
+#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0
+#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x30
+#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4
+#define TD_CNTL__PAD_STALL_EN_MASK 0x100
+#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8
+#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x600
+#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9
+#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x1800
+#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb
+#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x8000
+#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf
+#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x10000
+#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10
+#define TD_CNTL__LD_FLOAT_MODE_MASK 0x40000
+#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12
+#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x80000
+#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13
+#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x100000
+#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14
+#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x200000
+#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15
+#define TD_STATUS__BUSY_MASK 0x80000000
+#define TD_STATUS__BUSY__SHIFT 0x1f
+#define TD_DEBUG_INDEX__INDEX_MASK 0x1f
+#define TD_DEBUG_INDEX__INDEX__SHIFT 0x0
+#define TD_DEBUG_DATA__DATA_MASK 0xffffffff
+#define TD_DEBUG_DATA__DATA__SHIFT 0x0
+#define TD_DSM_CNTL__FORCE_SEDB_0_MASK 0x1
+#define TD_DSM_CNTL__FORCE_SEDB_0__SHIFT 0x0
+#define TD_DSM_CNTL__FORCE_SEDB_1_MASK 0x2
+#define TD_DSM_CNTL__FORCE_SEDB_1__SHIFT 0x1
+#define TD_DSM_CNTL__EN_SINGLE_WR_SEDB_MASK 0x4
+#define TD_DSM_CNTL__EN_SINGLE_WR_SEDB__SHIFT 0x2
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
+#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00
+#define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
+#define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TD_SCRATCH__SCRATCH_MASK 0xffffffff
+#define TD_SCRATCH__SCRATCH__SHIFT 0x0
+#define TA_CNTL__TC_DATA_CREDIT_MASK 0xe000
+#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd
+#define TA_CNTL__ALIGNER_CREDIT_MASK 0x1f0000
+#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10
+#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xffc00000
+#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16
+#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x1
+#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0
+#define TA_CNTL_AUX__RESERVED_MASK 0xe
+#define TA_CNTL_AUX__RESERVED__SHIFT 0x1
+#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x10000
+#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10
+#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x20000
+#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11
+#define TA_CNTL_AUX__ANISO_TAP_MASK 0x40000
+#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12
+#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x80000
+#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13
+#define TA_RESERVED_010C__Unused_MASK 0xffffffff
+#define TA_RESERVED_010C__Unused__SHIFT 0x0
+#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff
+#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
+#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff
+#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
+#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x1000
+#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc
+#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x2000
+#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd
+#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x4000
+#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe
+#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x10000
+#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10
+#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x20000
+#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11
+#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x40000
+#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12
+#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x100000
+#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14
+#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x200000
+#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15
+#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x400000
+#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16
+#define TA_STATUS__IN_BUSY_MASK 0x1000000
+#define TA_STATUS__IN_BUSY__SHIFT 0x18
+#define TA_STATUS__FG_BUSY_MASK 0x2000000
+#define TA_STATUS__FG_BUSY__SHIFT 0x19
+#define TA_STATUS__LA_BUSY_MASK 0x4000000
+#define TA_STATUS__LA_BUSY__SHIFT 0x1a
+#define TA_STATUS__FL_BUSY_MASK 0x8000000
+#define TA_STATUS__FL_BUSY__SHIFT 0x1b
+#define TA_STATUS__TA_BUSY_MASK 0x10000000
+#define TA_STATUS__TA_BUSY__SHIFT 0x1c
+#define TA_STATUS__FA_BUSY_MASK 0x20000000
+#define TA_STATUS__FA_BUSY__SHIFT 0x1d
+#define TA_STATUS__AL_BUSY_MASK 0x40000000
+#define TA_STATUS__AL_BUSY__SHIFT 0x1e
+#define TA_STATUS__BUSY_MASK 0x80000000
+#define TA_STATUS__BUSY__SHIFT 0x1f
+#define TA_DEBUG_INDEX__INDEX_MASK 0x1f
+#define TA_DEBUG_INDEX__INDEX__SHIFT 0x0
+#define TA_DEBUG_DATA__DATA_MASK 0xffffffff
+#define TA_DEBUG_DATA__DATA__SHIFT 0x0
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
+#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00
+#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
+#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TA_SCRATCH__SCRATCH_MASK 0xffffffff
+#define TA_SCRATCH__SCRATCH__SHIFT 0x0
+#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS_MASK 0xffffffff
+#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS__SHIFT 0x0
+#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE_MASK 0x1
+#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE__SHIFT 0x0
+#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE_MASK 0x6
+#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE__SHIFT 0x1
+#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE_MASK 0x18
+#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE__SHIFT 0x3
+#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE_MASK 0xe0
+#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE__SHIFT 0x5
+#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL_MASK 0xff00
+#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL__SHIFT 0x8
+#define TCP_INVALIDATE__START_MASK 0x1
+#define TCP_INVALIDATE__START__SHIFT 0x0
+#define TCP_STATUS__TCP_BUSY_MASK 0x1
+#define TCP_STATUS__TCP_BUSY__SHIFT 0x0
+#define TCP_STATUS__INPUT_BUSY_MASK 0x2
+#define TCP_STATUS__INPUT_BUSY__SHIFT 0x1
+#define TCP_STATUS__ADRS_BUSY_MASK 0x4
+#define TCP_STATUS__ADRS_BUSY__SHIFT 0x2
+#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x8
+#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3
+#define TCP_STATUS__CNTRL_BUSY_MASK 0x10
+#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4
+#define TCP_STATUS__LFIFO_BUSY_MASK 0x20
+#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5
+#define TCP_STATUS__READ_BUSY_MASK 0x40
+#define TCP_STATUS__READ_BUSY__SHIFT 0x6
+#define TCP_STATUS__FORMAT_BUSY_MASK 0x80
+#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7
+#define TCP_CNTL__FORCE_HIT_MASK 0x1
+#define TCP_CNTL__FORCE_HIT__SHIFT 0x0
+#define TCP_CNTL__FORCE_MISS_MASK 0x2
+#define TCP_CNTL__FORCE_MISS__SHIFT 0x1
+#define TCP_CNTL__L1_SIZE_MASK 0xc
+#define TCP_CNTL__L1_SIZE__SHIFT 0x2
+#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x10
+#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4
+#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x20
+#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5
+#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x1f8000
+#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf
+#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0xfc00000
+#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16
+#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000
+#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c
+#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000
+#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d
+#define TCP_CHAN_STEER_LO__CHAN0_MASK 0xf
+#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0
+#define TCP_CHAN_STEER_LO__CHAN1_MASK 0xf0
+#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4
+#define TCP_CHAN_STEER_LO__CHAN2_MASK 0xf00
+#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8
+#define TCP_CHAN_STEER_LO__CHAN3_MASK 0xf000
+#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc
+#define TCP_CHAN_STEER_LO__CHAN4_MASK 0xf0000
+#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10
+#define TCP_CHAN_STEER_LO__CHAN5_MASK 0xf00000
+#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14
+#define TCP_CHAN_STEER_LO__CHAN6_MASK 0xf000000
+#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18
+#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xf0000000
+#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c
+#define TCP_CHAN_STEER_HI__CHAN8_MASK 0xf
+#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0
+#define TCP_CHAN_STEER_HI__CHAN9_MASK 0xf0
+#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4
+#define TCP_CHAN_STEER_HI__CHANA_MASK 0xf00
+#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8
+#define TCP_CHAN_STEER_HI__CHANB_MASK 0xf000
+#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc
+#define TCP_CHAN_STEER_HI__CHANC_MASK 0xf0000
+#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10
+#define TCP_CHAN_STEER_HI__CHAND_MASK 0xf00000
+#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14
+#define TCP_CHAN_STEER_HI__CHANE_MASK 0xf000000
+#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18
+#define TCP_CHAN_STEER_HI__CHANF_MASK 0xf0000000
+#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c
+#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0xf
+#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0
+#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x30
+#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4
+#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x1c0
+#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6
+#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x200
+#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9
+#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x3ff
+#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0
+#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x7f0000
+#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10
+#define TCP_CREDIT__TD_CREDIT_MASK 0xe0000000
+#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
+#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
+#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x7
+#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0
+#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x700
+#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8
+#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x70000
+#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10
+#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x7000000
+#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18
+#define TCP_EDC_CNT__SEC_COUNT_MASK 0xff
+#define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0
+#define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0xff00
+#define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8
+#define TCP_EDC_CNT__DED_COUNT_MASK 0xff0000
+#define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10
+#define TCP_EDC_CNT__UNUSED_MASK 0xff000000
+#define TCP_EDC_CNT__UNUSED__SHIFT 0x18
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x3
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0xc
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x30
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0xc0
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x300
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0xc00
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x3000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0xc000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x30000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0xc0000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x300000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0xc00000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x3000000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0xc000000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xc0000000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x3
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0xc
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x30
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0xc0
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x300
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0xc00
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x3000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0xc000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x30000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0xc0000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x300000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0xc00000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x3000000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0xc000000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xc0000000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
+#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x1
+#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0
+#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x2
+#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1
+#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x4
+#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2
+#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x8
+#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3
+#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x10
+#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4
+#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x20
+#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5
+#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x40
+#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6
+#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x80
+#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7
+#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x100
+#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8
+#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x200
+#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9
+#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x400
+#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa
+#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x800
+#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb
+#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x1000
+#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc
+#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x2000
+#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd
+#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x4000
+#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe
+#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x8000
+#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf
+#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x10000
+#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10
+#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x20000
+#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11
+#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x40000
+#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12
+#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x80000
+#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13
+#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x100000
+#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14
+#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x200000
+#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15
+#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x400000
+#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16
+#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x800000
+#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17
+#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x1000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18
+#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x2000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19
+#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x4000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a
+#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x8000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b
+#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c
+#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d
+#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e
+#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x3
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0xc
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x30
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0xc0
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x300
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0xc00
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x3000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0xc000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x30000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0xc0000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x300000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0xc00000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x3000000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0xc000000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xc0000000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x3
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0xc
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x30
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0xc0
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x300
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0xc00
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x3000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0xc000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x30000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0xc0000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x300000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0xc00000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x3000000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0xc000000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xc0000000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
+#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x3
+#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0
+#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0xc
+#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2
+#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x30
+#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4
+#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0xc0
+#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6
+#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x300
+#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8
+#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0xc00
+#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa
+#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x3000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc
+#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0xc000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe
+#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x30000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10
+#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0xc0000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12
+#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x300000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14
+#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0xc00000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16
+#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x3000000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18
+#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0xc000000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a
+#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c
+#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xc0000000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e
+#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x3
+#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0
+#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0xc
+#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2
+#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x30
+#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4
+#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0xc0
+#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6
+#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x300
+#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8
+#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0xc00
+#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa
+#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x3000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc
+#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0xc000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe
+#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x30000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10
+#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0xc0000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12
+#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x300000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14
+#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0xc00000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16
+#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x3000000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18
+#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0xc000000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a
+#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c
+#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xc0000000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x3
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0xc
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x30
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0xc0
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x300
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0xc00
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x3000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0xc000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x30000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0xc0000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x300000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0xc00000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x3000000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0xc000000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xc0000000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e
+#define TC_CFG_L1_VOLATILE__VOL_MASK 0xf
+#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0
+#define TC_CFG_L2_VOLATILE__VOL_MASK 0xf
+#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0
+#define TCP_WATCH0_ADDR_H__ADDR_MASK 0xffff
+#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH1_ADDR_H__ADDR_MASK 0xffff
+#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH2_ADDR_H__ADDR_MASK 0xffff
+#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH3_ADDR_H__ADDR_MASK 0xffff
+#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xffffffc0
+#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6
+#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xffffffc0
+#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6
+#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xffffffc0
+#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6
+#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xffffffc0
+#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6
+#define TCP_WATCH0_CNTL__MASK_MASK 0xffffff
+#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH0_CNTL__VMID_MASK 0xf000000
+#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000
+#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000
+#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f
+#define TCP_WATCH1_CNTL__MASK_MASK 0xffffff
+#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH1_CNTL__VMID_MASK 0xf000000
+#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000
+#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000
+#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f
+#define TCP_WATCH2_CNTL__MASK_MASK 0xffffff
+#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH2_CNTL__VMID_MASK 0xf000000
+#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000
+#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000
+#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f
+#define TCP_WATCH3_CNTL__MASK_MASK 0xffffff
+#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH3_CNTL__VMID_MASK 0xf000000
+#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000
+#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000
+#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f
+#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x2000000
+#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19
+#define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x4000000
+#define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a
+#define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x8000000
+#define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b
+#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000
+#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
+#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000
+#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
+#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0xff
+#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0
+#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x1
+#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0
+#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x2
+#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1
+#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x4
+#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2
+#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x3
+#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0
+#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x4
+#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
+#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL_MASK 0x18
+#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL__SHIFT 0x3
+#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x20
+#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
+#define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0xff
+#define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0
+#define TD_CGTT_CTRL__ON_DELAY_MASK 0xf
+#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0
+#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define TA_CGTT_CTRL__ON_DELAY_MASK 0xf
+#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0
+#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_TCP_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_TCP_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define TCI_STATUS__TCI_BUSY_MASK 0x1
+#define TCI_STATUS__TCI_BUSY__SHIFT 0x0
+#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0xffff
+#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0
+#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0xff0000
+#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10
+#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xff000000
+#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18
+#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x1
+#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0
+#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x1fe
+#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1
+#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x6
+#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1
+#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x18
+#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3
+#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x60
+#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5
+#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x180
+#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7
+#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x1
+#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0
+#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x2
+#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1
+#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x4
+#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2
+#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x8
+#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3
+#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x10
+#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4
+#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x20
+#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5
+#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x40
+#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6
+#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x80
+#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7
+#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x100
+#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8
+#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x200
+#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9
+#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x400
+#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa
+#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x800
+#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb
+#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x1000
+#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc
+#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x2000
+#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd
+#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x4000
+#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe
+#define GDS_ENHANCE2__MISC_MASK 0xffff
+#define GDS_ENHANCE2__MISC__SHIFT 0x0
+#define GDS_ENHANCE2__UNUSED_MASK 0xffff0000
+#define GDS_ENHANCE2__UNUSED__SHIFT 0x10
+#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x1
+#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
+#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2
+#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
+#define GDS_PROTECTION_FAULT__GRBM_MASK 0x4
+#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2
+#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x38
+#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3
+#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x3c0
+#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6
+#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0xc00
+#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa
+#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0xf000
+#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc
+#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000
+#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
+#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x1
+#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
+#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2
+#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
+#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x4
+#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2
+#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x8
+#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3
+#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x10
+#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4
+#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0xf00
+#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8
+#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000
+#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
+#define GDS_EDC_CNT__DED_MASK 0xff
+#define GDS_EDC_CNT__DED__SHIFT 0x0
+#define GDS_EDC_CNT__SED_MASK 0xff00
+#define GDS_EDC_CNT__SED__SHIFT 0x8
+#define GDS_EDC_CNT__SEC_MASK 0xff0000
+#define GDS_EDC_CNT__SEC__SHIFT 0x10
+#define GDS_EDC_GRBM_CNT__DED_MASK 0xff
+#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0
+#define GDS_EDC_GRBM_CNT__SEC_MASK 0xff0000
+#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x10
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x1
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x2
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1
+#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x4
+#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2
+#define GDS_EDC_OA_DED__UNUSED0_MASK 0x8
+#define GDS_EDC_OA_DED__UNUSED0__SHIFT 0x3
+#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x10
+#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4
+#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x20
+#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5
+#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x40
+#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6
+#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x80
+#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7
+#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x100
+#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8
+#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x200
+#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9
+#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x400
+#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa
+#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x800
+#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb
+#define GDS_EDC_OA_DED__UNUSED1_MASK 0xfffff000
+#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc
+#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK 0x1f
+#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT 0x0
+#define GDS_DEBUG_CNTL__UNUSED_MASK 0xffffffe0
+#define GDS_DEBUG_CNTL__UNUSED__SHIFT 0x5
+#define GDS_DEBUG_DATA__DATA_MASK 0xffffffff
+#define GDS_DEBUG_DATA__DATA__SHIFT 0x0
+#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0_MASK 0x1
+#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0__SHIFT 0x0
+#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1_MASK 0x2
+#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1__SHIFT 0x1
+#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A_MASK 0x4
+#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A__SHIFT 0x2
+#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0_MASK 0x8
+#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0__SHIFT 0x3
+#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1_MASK 0x10
+#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1__SHIFT 0x4
+#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B_MASK 0x20
+#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B__SHIFT 0x5
+#define GDS_DSM_CNTL__UNUSED_MASK 0xffffffc0
+#define GDS_DSM_CNTL__UNUSED__SHIFT 0x6
+#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define GDS_RD_ADDR__READ_ADDR_MASK 0xffffffff
+#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0
+#define GDS_RD_DATA__READ_DATA_MASK 0xffffffff
+#define GDS_RD_DATA__READ_DATA__SHIFT 0x0
+#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xffffffff
+#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0
+#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xffffffff
+#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0
+#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xffffffff
+#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0
+#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xffffffff
+#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0
+#define GDS_WR_DATA__WRITE_DATA_MASK 0xffffffff
+#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0
+#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xffffffff
+#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0
+#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xffffffff
+#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0
+#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xffffffff
+#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0
+#define GDS_ATOM_CNTL__AINC_MASK 0x3f
+#define GDS_ATOM_CNTL__AINC__SHIFT 0x0
+#define GDS_ATOM_CNTL__UNUSED1_MASK 0xc0
+#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6
+#define GDS_ATOM_CNTL__DMODE_MASK 0x300
+#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8
+#define GDS_ATOM_CNTL__UNUSED2_MASK 0xfffffc00
+#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa
+#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x1
+#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0
+#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xfffffffe
+#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1
+#define GDS_ATOM_BASE__BASE_MASK 0xffff
+#define GDS_ATOM_BASE__BASE__SHIFT 0x0
+#define GDS_ATOM_BASE__UNUSED_MASK 0xffff0000
+#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10
+#define GDS_ATOM_SIZE__SIZE_MASK 0xffff
+#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0
+#define GDS_ATOM_SIZE__UNUSED_MASK 0xffff0000
+#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10
+#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0xff
+#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0
+#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xffffff00
+#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8
+#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0xff
+#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0
+#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xffffff00
+#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8
+#define GDS_ATOM_DST__DST_MASK 0xffffffff
+#define GDS_ATOM_DST__DST__SHIFT 0x0
+#define GDS_ATOM_OP__OP_MASK 0xff
+#define GDS_ATOM_OP__OP__SHIFT 0x0
+#define GDS_ATOM_OP__UNUSED_MASK 0xffffff00
+#define GDS_ATOM_OP__UNUSED__SHIFT 0x8
+#define GDS_ATOM_SRC0__DATA_MASK 0xffffffff
+#define GDS_ATOM_SRC0__DATA__SHIFT 0x0
+#define GDS_ATOM_SRC0_U__DATA_MASK 0xffffffff
+#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0
+#define GDS_ATOM_SRC1__DATA_MASK 0xffffffff
+#define GDS_ATOM_SRC1__DATA__SHIFT 0x0
+#define GDS_ATOM_SRC1_U__DATA_MASK 0xffffffff
+#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0
+#define GDS_ATOM_READ0__DATA_MASK 0xffffffff
+#define GDS_ATOM_READ0__DATA__SHIFT 0x0
+#define GDS_ATOM_READ0_U__DATA_MASK 0xffffffff
+#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0
+#define GDS_ATOM_READ1__DATA_MASK 0xffffffff
+#define GDS_ATOM_READ1__DATA__SHIFT 0x0
+#define GDS_ATOM_READ1_U__DATA_MASK 0xffffffff
+#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0
+#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x3f
+#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0
+#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xffffffc0
+#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6
+#define GDS_GWS_RESOURCE__FLAG_MASK 0x1
+#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0
+#define GDS_GWS_RESOURCE__COUNTER_MASK 0x1ffe
+#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1
+#define GDS_GWS_RESOURCE__TYPE_MASK 0x2000
+#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd
+#define GDS_GWS_RESOURCE__DED_MASK 0x4000
+#define GDS_GWS_RESOURCE__DED__SHIFT 0xe
+#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x8000
+#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf
+#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x7ff0000
+#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10
+#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x8000000
+#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1b
+#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x10000000
+#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1c
+#define GDS_GWS_RESOURCE__UNUSED1_MASK 0xe0000000
+#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1d
+#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0xffff
+#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0
+#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xffff0000
+#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10
+#define GDS_OA_CNTL__INDEX_MASK 0xf
+#define GDS_OA_CNTL__INDEX__SHIFT 0x0
+#define GDS_OA_CNTL__UNUSED_MASK 0xfffffff0
+#define GDS_OA_CNTL__UNUSED__SHIFT 0x4
+#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xffffffff
+#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0
+#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0xffff
+#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0
+#define GDS_OA_ADDRESS__CRAWLER_MASK 0xf0000
+#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10
+#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x300000
+#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14
+#define GDS_OA_ADDRESS__UNUSED_MASK 0x3fc00000
+#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16
+#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000
+#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e
+#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000
+#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f
+#define GDS_OA_INCDEC__VALUE_MASK 0x7fffffff
+#define GDS_OA_INCDEC__VALUE__SHIFT 0x0
+#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000
+#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f
+#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xffffffff
+#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0
+#define GDS_DEBUG_REG0__spare1_MASK 0x3f
+#define GDS_DEBUG_REG0__spare1__SHIFT 0x0
+#define GDS_DEBUG_REG0__write_buff_valid_MASK 0x40
+#define GDS_DEBUG_REG0__write_buff_valid__SHIFT 0x6
+#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK 0xf80
+#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT 0x7
+#define GDS_DEBUG_REG0__last_pixel_ptr_MASK 0x1000
+#define GDS_DEBUG_REG0__last_pixel_ptr__SHIFT 0xc
+#define GDS_DEBUG_REG0__cstate_MASK 0x1e000
+#define GDS_DEBUG_REG0__cstate__SHIFT 0xd
+#define GDS_DEBUG_REG0__buff_write_MASK 0x20000
+#define GDS_DEBUG_REG0__buff_write__SHIFT 0x11
+#define GDS_DEBUG_REG0__flush_request_MASK 0x40000
+#define GDS_DEBUG_REG0__flush_request__SHIFT 0x12
+#define GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK 0x80000
+#define GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT 0x13
+#define GDS_DEBUG_REG0__wbuf_fifo_empty_MASK 0x100000
+#define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT 0x14
+#define GDS_DEBUG_REG0__wbuf_fifo_full_MASK 0x200000
+#define GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT 0x15
+#define GDS_DEBUG_REG0__spare_MASK 0xffc00000
+#define GDS_DEBUG_REG0__spare__SHIFT 0x16
+#define GDS_DEBUG_REG1__tag_hit_MASK 0x1
+#define GDS_DEBUG_REG1__tag_hit__SHIFT 0x0
+#define GDS_DEBUG_REG1__tag_miss_MASK 0x2
+#define GDS_DEBUG_REG1__tag_miss__SHIFT 0x1
+#define GDS_DEBUG_REG1__pixel_addr_MASK 0x1fffc
+#define GDS_DEBUG_REG1__pixel_addr__SHIFT 0x2
+#define GDS_DEBUG_REG1__pixel_vld_MASK 0x20000
+#define GDS_DEBUG_REG1__pixel_vld__SHIFT 0x11
+#define GDS_DEBUG_REG1__data_ready_MASK 0x40000
+#define GDS_DEBUG_REG1__data_ready__SHIFT 0x12
+#define GDS_DEBUG_REG1__awaiting_data_MASK 0x80000
+#define GDS_DEBUG_REG1__awaiting_data__SHIFT 0x13
+#define GDS_DEBUG_REG1__addr_fifo_full_MASK 0x100000
+#define GDS_DEBUG_REG1__addr_fifo_full__SHIFT 0x14
+#define GDS_DEBUG_REG1__addr_fifo_empty_MASK 0x200000
+#define GDS_DEBUG_REG1__addr_fifo_empty__SHIFT 0x15
+#define GDS_DEBUG_REG1__buffer_loaded_MASK 0x400000
+#define GDS_DEBUG_REG1__buffer_loaded__SHIFT 0x16
+#define GDS_DEBUG_REG1__buffer_invalid_MASK 0x800000
+#define GDS_DEBUG_REG1__buffer_invalid__SHIFT 0x17
+#define GDS_DEBUG_REG1__spare_MASK 0xff000000
+#define GDS_DEBUG_REG1__spare__SHIFT 0x18
+#define GDS_DEBUG_REG2__ds_full_MASK 0x1
+#define GDS_DEBUG_REG2__ds_full__SHIFT 0x0
+#define GDS_DEBUG_REG2__ds_credit_avail_MASK 0x2
+#define GDS_DEBUG_REG2__ds_credit_avail__SHIFT 0x1
+#define GDS_DEBUG_REG2__ord_idx_free_MASK 0x4
+#define GDS_DEBUG_REG2__ord_idx_free__SHIFT 0x2
+#define GDS_DEBUG_REG2__cmd_write_MASK 0x8
+#define GDS_DEBUG_REG2__cmd_write__SHIFT 0x3
+#define GDS_DEBUG_REG2__app_sel_MASK 0xf0
+#define GDS_DEBUG_REG2__app_sel__SHIFT 0x4
+#define GDS_DEBUG_REG2__req_MASK 0x7fff00
+#define GDS_DEBUG_REG2__req__SHIFT 0x8
+#define GDS_DEBUG_REG2__spare_MASK 0xff800000
+#define GDS_DEBUG_REG2__spare__SHIFT 0x17
+#define GDS_DEBUG_REG3__pipe_num_busy_MASK 0x7ff
+#define GDS_DEBUG_REG3__pipe_num_busy__SHIFT 0x0
+#define GDS_DEBUG_REG3__pipe0_busy_num_MASK 0x7800
+#define GDS_DEBUG_REG3__pipe0_busy_num__SHIFT 0xb
+#define GDS_DEBUG_REG3__spare_MASK 0xffff8000
+#define GDS_DEBUG_REG3__spare__SHIFT 0xf
+#define GDS_DEBUG_REG4__gws_busy_MASK 0x1
+#define GDS_DEBUG_REG4__gws_busy__SHIFT 0x0
+#define GDS_DEBUG_REG4__gws_req_MASK 0x2
+#define GDS_DEBUG_REG4__gws_req__SHIFT 0x1
+#define GDS_DEBUG_REG4__gws_out_stall_MASK 0x4
+#define GDS_DEBUG_REG4__gws_out_stall__SHIFT 0x2
+#define GDS_DEBUG_REG4__cur_reso_MASK 0x1f8
+#define GDS_DEBUG_REG4__cur_reso__SHIFT 0x3
+#define GDS_DEBUG_REG4__cur_reso_head_valid_MASK 0x200
+#define GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT 0x9
+#define GDS_DEBUG_REG4__cur_reso_head_dirty_MASK 0x400
+#define GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT 0xa
+#define GDS_DEBUG_REG4__cur_reso_head_flag_MASK 0x800
+#define GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT 0xb
+#define GDS_DEBUG_REG4__cur_reso_fed_MASK 0x1000
+#define GDS_DEBUG_REG4__cur_reso_fed__SHIFT 0xc
+#define GDS_DEBUG_REG4__cur_reso_barrier_MASK 0x2000
+#define GDS_DEBUG_REG4__cur_reso_barrier__SHIFT 0xd
+#define GDS_DEBUG_REG4__cur_reso_flag_MASK 0x4000
+#define GDS_DEBUG_REG4__cur_reso_flag__SHIFT 0xe
+#define GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK 0x8000
+#define GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT 0xf
+#define GDS_DEBUG_REG4__credit_cnt_gt0_MASK 0x10000
+#define GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT 0x10
+#define GDS_DEBUG_REG4__cmd_write_MASK 0x20000
+#define GDS_DEBUG_REG4__cmd_write__SHIFT 0x11
+#define GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK 0x40000
+#define GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT 0x12
+#define GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK 0x80000
+#define GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT 0x13
+#define GDS_DEBUG_REG4__ram_read_busy_MASK 0x100000
+#define GDS_DEBUG_REG4__ram_read_busy__SHIFT 0x14
+#define GDS_DEBUG_REG4__gws_bulkfree_MASK 0x200000
+#define GDS_DEBUG_REG4__gws_bulkfree__SHIFT 0x15
+#define GDS_DEBUG_REG4__ram_gws_re_MASK 0x400000
+#define GDS_DEBUG_REG4__ram_gws_re__SHIFT 0x16
+#define GDS_DEBUG_REG4__ram_gws_we_MASK 0x800000
+#define GDS_DEBUG_REG4__ram_gws_we__SHIFT 0x17
+#define GDS_DEBUG_REG4__spare_MASK 0xff000000
+#define GDS_DEBUG_REG4__spare__SHIFT 0x18
+#define GDS_DEBUG_REG5__write_dis_MASK 0x1
+#define GDS_DEBUG_REG5__write_dis__SHIFT 0x0
+#define GDS_DEBUG_REG5__dec_error_MASK 0x2
+#define GDS_DEBUG_REG5__dec_error__SHIFT 0x1
+#define GDS_DEBUG_REG5__alloc_opco_error_MASK 0x4
+#define GDS_DEBUG_REG5__alloc_opco_error__SHIFT 0x2
+#define GDS_DEBUG_REG5__dealloc_opco_error_MASK 0x8
+#define GDS_DEBUG_REG5__dealloc_opco_error__SHIFT 0x3
+#define GDS_DEBUG_REG5__wrap_opco_error_MASK 0x10
+#define GDS_DEBUG_REG5__wrap_opco_error__SHIFT 0x4
+#define GDS_DEBUG_REG5__spare_MASK 0xe0
+#define GDS_DEBUG_REG5__spare__SHIFT 0x5
+#define GDS_DEBUG_REG5__error_ds_address_MASK 0x3fff00
+#define GDS_DEBUG_REG5__error_ds_address__SHIFT 0x8
+#define GDS_DEBUG_REG5__spare1_MASK 0xffc00000
+#define GDS_DEBUG_REG5__spare1__SHIFT 0x16
+#define GDS_DEBUG_REG6__oa_busy_MASK 0x1
+#define GDS_DEBUG_REG6__oa_busy__SHIFT 0x0
+#define GDS_DEBUG_REG6__counters_enabled_MASK 0x1e
+#define GDS_DEBUG_REG6__counters_enabled__SHIFT 0x1
+#define GDS_DEBUG_REG6__counters_busy_MASK 0x1fffe0
+#define GDS_DEBUG_REG6__counters_busy__SHIFT 0x5
+#define GDS_DEBUG_REG6__spare_MASK 0xffe00000
+#define GDS_DEBUG_REG6__spare__SHIFT 0x15
+#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
+#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
+#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
+#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
+#define GDS_VMID0_BASE__BASE_MASK 0xffff
+#define GDS_VMID0_BASE__BASE__SHIFT 0x0
+#define GDS_VMID1_BASE__BASE_MASK 0xffff
+#define GDS_VMID1_BASE__BASE__SHIFT 0x0
+#define GDS_VMID2_BASE__BASE_MASK 0xffff
+#define GDS_VMID2_BASE__BASE__SHIFT 0x0
+#define GDS_VMID3_BASE__BASE_MASK 0xffff
+#define GDS_VMID3_BASE__BASE__SHIFT 0x0
+#define GDS_VMID4_BASE__BASE_MASK 0xffff
+#define GDS_VMID4_BASE__BASE__SHIFT 0x0
+#define GDS_VMID5_BASE__BASE_MASK 0xffff
+#define GDS_VMID5_BASE__BASE__SHIFT 0x0
+#define GDS_VMID6_BASE__BASE_MASK 0xffff
+#define GDS_VMID6_BASE__BASE__SHIFT 0x0
+#define GDS_VMID7_BASE__BASE_MASK 0xffff
+#define GDS_VMID7_BASE__BASE__SHIFT 0x0
+#define GDS_VMID8_BASE__BASE_MASK 0xffff
+#define GDS_VMID8_BASE__BASE__SHIFT 0x0
+#define GDS_VMID9_BASE__BASE_MASK 0xffff
+#define GDS_VMID9_BASE__BASE__SHIFT 0x0
+#define GDS_VMID10_BASE__BASE_MASK 0xffff
+#define GDS_VMID10_BASE__BASE__SHIFT 0x0
+#define GDS_VMID11_BASE__BASE_MASK 0xffff
+#define GDS_VMID11_BASE__BASE__SHIFT 0x0
+#define GDS_VMID12_BASE__BASE_MASK 0xffff
+#define GDS_VMID12_BASE__BASE__SHIFT 0x0
+#define GDS_VMID13_BASE__BASE_MASK 0xffff
+#define GDS_VMID13_BASE__BASE__SHIFT 0x0
+#define GDS_VMID14_BASE__BASE_MASK 0xffff
+#define GDS_VMID14_BASE__BASE__SHIFT 0x0
+#define GDS_VMID15_BASE__BASE_MASK 0xffff
+#define GDS_VMID15_BASE__BASE__SHIFT 0x0
+#define GDS_VMID0_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID1_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID2_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID3_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID4_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID5_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID6_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID7_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID8_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID9_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID10_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID11_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID12_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID13_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID14_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID15_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0
+#define GDS_GWS_VMID0__BASE_MASK 0x3f
+#define GDS_GWS_VMID0__BASE__SHIFT 0x0
+#define GDS_GWS_VMID0__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID0__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID1__BASE_MASK 0x3f
+#define GDS_GWS_VMID1__BASE__SHIFT 0x0
+#define GDS_GWS_VMID1__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID1__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID2__BASE_MASK 0x3f
+#define GDS_GWS_VMID2__BASE__SHIFT 0x0
+#define GDS_GWS_VMID2__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID2__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID3__BASE_MASK 0x3f
+#define GDS_GWS_VMID3__BASE__SHIFT 0x0
+#define GDS_GWS_VMID3__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID3__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID4__BASE_MASK 0x3f
+#define GDS_GWS_VMID4__BASE__SHIFT 0x0
+#define GDS_GWS_VMID4__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID4__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID5__BASE_MASK 0x3f
+#define GDS_GWS_VMID5__BASE__SHIFT 0x0
+#define GDS_GWS_VMID5__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID5__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID6__BASE_MASK 0x3f
+#define GDS_GWS_VMID6__BASE__SHIFT 0x0
+#define GDS_GWS_VMID6__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID6__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID7__BASE_MASK 0x3f
+#define GDS_GWS_VMID7__BASE__SHIFT 0x0
+#define GDS_GWS_VMID7__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID7__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID8__BASE_MASK 0x3f
+#define GDS_GWS_VMID8__BASE__SHIFT 0x0
+#define GDS_GWS_VMID8__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID8__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID9__BASE_MASK 0x3f
+#define GDS_GWS_VMID9__BASE__SHIFT 0x0
+#define GDS_GWS_VMID9__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID9__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID10__BASE_MASK 0x3f
+#define GDS_GWS_VMID10__BASE__SHIFT 0x0
+#define GDS_GWS_VMID10__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID10__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID11__BASE_MASK 0x3f
+#define GDS_GWS_VMID11__BASE__SHIFT 0x0
+#define GDS_GWS_VMID11__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID11__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID12__BASE_MASK 0x3f
+#define GDS_GWS_VMID12__BASE__SHIFT 0x0
+#define GDS_GWS_VMID12__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID12__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID13__BASE_MASK 0x3f
+#define GDS_GWS_VMID13__BASE__SHIFT 0x0
+#define GDS_GWS_VMID13__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID13__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID14__BASE_MASK 0x3f
+#define GDS_GWS_VMID14__BASE__SHIFT 0x0
+#define GDS_GWS_VMID14__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID14__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID15__BASE_MASK 0x3f
+#define GDS_GWS_VMID15__BASE__SHIFT 0x0
+#define GDS_GWS_VMID15__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID15__SIZE__SHIFT 0x10
+#define GDS_OA_VMID0__MASK_MASK 0xffff
+#define GDS_OA_VMID0__MASK__SHIFT 0x0
+#define GDS_OA_VMID0__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID0__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID1__MASK_MASK 0xffff
+#define GDS_OA_VMID1__MASK__SHIFT 0x0
+#define GDS_OA_VMID1__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID1__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID2__MASK_MASK 0xffff
+#define GDS_OA_VMID2__MASK__SHIFT 0x0
+#define GDS_OA_VMID2__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID2__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID3__MASK_MASK 0xffff
+#define GDS_OA_VMID3__MASK__SHIFT 0x0
+#define GDS_OA_VMID3__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID3__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID4__MASK_MASK 0xffff
+#define GDS_OA_VMID4__MASK__SHIFT 0x0
+#define GDS_OA_VMID4__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID4__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID5__MASK_MASK 0xffff
+#define GDS_OA_VMID5__MASK__SHIFT 0x0
+#define GDS_OA_VMID5__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID5__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID6__MASK_MASK 0xffff
+#define GDS_OA_VMID6__MASK__SHIFT 0x0
+#define GDS_OA_VMID6__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID6__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID7__MASK_MASK 0xffff
+#define GDS_OA_VMID7__MASK__SHIFT 0x0
+#define GDS_OA_VMID7__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID7__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID8__MASK_MASK 0xffff
+#define GDS_OA_VMID8__MASK__SHIFT 0x0
+#define GDS_OA_VMID8__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID8__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID9__MASK_MASK 0xffff
+#define GDS_OA_VMID9__MASK__SHIFT 0x0
+#define GDS_OA_VMID9__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID9__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID10__MASK_MASK 0xffff
+#define GDS_OA_VMID10__MASK__SHIFT 0x0
+#define GDS_OA_VMID10__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID10__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID11__MASK_MASK 0xffff
+#define GDS_OA_VMID11__MASK__SHIFT 0x0
+#define GDS_OA_VMID11__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID11__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID12__MASK_MASK 0xffff
+#define GDS_OA_VMID12__MASK__SHIFT 0x0
+#define GDS_OA_VMID12__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID12__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID13__MASK_MASK 0xffff
+#define GDS_OA_VMID13__MASK__SHIFT 0x0
+#define GDS_OA_VMID13__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID13__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID14__MASK_MASK 0xffff
+#define GDS_OA_VMID14__MASK__SHIFT 0x0
+#define GDS_OA_VMID14__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID14__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID15__MASK_MASK 0xffff
+#define GDS_OA_VMID15__MASK__SHIFT 0x0
+#define GDS_OA_VMID15__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID15__UNUSED__SHIFT 0x10
+#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x1
+#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0
+#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x2
+#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1
+#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x4
+#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2
+#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x8
+#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3
+#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x10
+#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4
+#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x20
+#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5
+#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x40
+#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6
+#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x80
+#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7
+#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x100
+#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8
+#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x200
+#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9
+#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x400
+#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa
+#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x800
+#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb
+#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x1000
+#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc
+#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x2000
+#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd
+#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x4000
+#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe
+#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x8000
+#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf
+#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x10000
+#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10
+#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x20000
+#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11
+#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x40000
+#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12
+#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x80000
+#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13
+#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x100000
+#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14
+#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x200000
+#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15
+#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x400000
+#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16
+#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x800000
+#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17
+#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x1000000
+#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18
+#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x2000000
+#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19
+#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x4000000
+#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a
+#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x8000000
+#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b
+#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000
+#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c
+#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000
+#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d
+#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000
+#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e
+#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000
+#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f
+#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x1
+#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0
+#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x2
+#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1
+#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x4
+#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2
+#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x8
+#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3
+#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x10
+#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4
+#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x20
+#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5
+#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x40
+#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6
+#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x80
+#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7
+#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x100
+#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8
+#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x200
+#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9
+#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x400
+#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa
+#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x800
+#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb
+#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x1000
+#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc
+#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x2000
+#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd
+#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x4000
+#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe
+#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x8000
+#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf
+#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x10000
+#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10
+#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x20000
+#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11
+#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x40000
+#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12
+#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x80000
+#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13
+#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x100000
+#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14
+#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x200000
+#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15
+#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x400000
+#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16
+#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x800000
+#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17
+#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x1000000
+#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18
+#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x2000000
+#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19
+#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x4000000
+#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a
+#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x8000000
+#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b
+#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000
+#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c
+#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000
+#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d
+#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000
+#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e
+#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000
+#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f
+#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x1
+#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0
+#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0xff00
+#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8
+#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
+#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x1
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x2
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1
+#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x4
+#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2
+#define GDS_OA_RESET_MASK__UNUSED0_MASK 0x8
+#define GDS_OA_RESET_MASK__UNUSED0__SHIFT 0x3
+#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x10
+#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4
+#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x20
+#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5
+#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x40
+#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6
+#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x80
+#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7
+#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x100
+#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8
+#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x200
+#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9
+#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x400
+#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa
+#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x800
+#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb
+#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xfffff000
+#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc
+#define GDS_OA_RESET__RESET_MASK 0x1
+#define GDS_OA_RESET__RESET__SHIFT 0x0
+#define GDS_OA_RESET__PIPE_ID_MASK 0xff00
+#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8
+#define GDS_ENHANCE__MISC_MASK 0xffff
+#define GDS_ENHANCE__MISC__SHIFT 0x0
+#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x10000
+#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10
+#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x20000
+#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11
+#define GDS_ENHANCE__UNUSED_MASK 0xfffc0000
+#define GDS_ENHANCE__UNUSED__SHIFT 0x12
+#define GDS_OA_CGPG_RESTORE__VMID_MASK 0xff
+#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0
+#define GDS_OA_CGPG_RESTORE__MEID_MASK 0xf00
+#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8
+#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0xf000
+#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc
+#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0xf0000
+#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10
+#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xfff00000
+#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14
+#define GDS_CS_CTXSW_STATUS__R_MASK 0x1
+#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0
+#define GDS_CS_CTXSW_STATUS__W_MASK 0x2
+#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1
+#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xfffffffc
+#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2
+#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0xffff
+#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xffff0000
+#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0xffff
+#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xffff0000
+#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0xffff
+#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xffff0000
+#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0xffff
+#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xffff0000
+#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_GFX_CTXSW_STATUS__R_MASK 0x1
+#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0
+#define GDS_GFX_CTXSW_STATUS__W_MASK 0x2
+#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1
+#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xfffffffc
+#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2
+#define GDS_VS_CTXSW_CNT0__UPDN_MASK 0xffff
+#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_VS_CTXSW_CNT0__PTR_MASK 0xffff0000
+#define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_VS_CTXSW_CNT1__UPDN_MASK 0xffff
+#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_VS_CTXSW_CNT1__PTR_MASK 0xffff0000
+#define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_VS_CTXSW_CNT2__UPDN_MASK 0xffff
+#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_VS_CTXSW_CNT2__PTR_MASK 0xffff0000
+#define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_VS_CTXSW_CNT3__UPDN_MASK 0xffff
+#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_VS_CTXSW_CNT3__PTR_MASK 0xffff0000
+#define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0xffff
+#define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xffff0000
+#define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0xffff
+#define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xffff0000
+#define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0xffff
+#define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xffff0000
+#define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0xffff
+#define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xffff0000
+#define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0xffff
+#define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xffff0000
+#define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0xffff
+#define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xffff0000
+#define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0xffff
+#define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xffff0000
+#define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0xffff
+#define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xffff0000
+#define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0xffff
+#define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xffff0000
+#define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0xffff
+#define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xffff0000
+#define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0xffff
+#define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xffff0000
+#define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0xffff
+#define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xffff0000
+#define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0xffff
+#define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xffff0000
+#define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0xffff
+#define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xffff0000
+#define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0xffff
+#define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xffff0000
+#define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0xffff
+#define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xffff0000
+#define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0xffff
+#define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xffff0000
+#define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0xffff
+#define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xffff0000
+#define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0xffff
+#define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xffff0000
+#define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0xffff
+#define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xffff0000
+#define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0xffff
+#define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xffff0000
+#define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0xffff
+#define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xffff0000
+#define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0xffff
+#define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xffff0000
+#define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0xffff
+#define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xffff0000
+#define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0xffff
+#define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xffff0000
+#define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0xffff
+#define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xffff0000
+#define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0xffff
+#define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xffff0000
+#define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0xffff
+#define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xffff0000
+#define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0xffff
+#define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xffff0000
+#define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0xffff
+#define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xffff0000
+#define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0xffff
+#define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xffff0000
+#define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0xffff
+#define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xffff0000
+#define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10
+#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x7
+#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
+#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x7
+#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x3
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0
+#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0xc
+#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2
+#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x10
+#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4
+#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x20
+#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5
+#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x40
+#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6
+#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x3f
+#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0
+#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x7fc0000
+#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0x12
+#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x8000000
+#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b
+#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0xfffffff
+#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0
+#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0xff
+#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0
+#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffff
+#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0
+#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x3
+#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
+#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0xc
+#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2
+#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x30
+#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4
+#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x40
+#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6
+#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x200
+#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9
+#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x400
+#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa
+#define VGT_DMA_INDEX_TYPE__MTYPE_MASK 0x1800
+#define VGT_DMA_INDEX_TYPE__MTYPE__SHIFT 0xb
+#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff
+#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
+#define IA_ENHANCE__MISC_MASK 0xffffffff
+#define IA_ENHANCE__MISC__SHIFT 0x0
+#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xffffffff
+#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0
+#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xffffffff
+#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0
+#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f
+#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
+#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0xffff
+#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0
+#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x20000
+#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11
+#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x100000
+#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14
+#define VGT_IMMED_DATA__DATA_MASK 0xffffffff
+#define VGT_IMMED_DATA__DATA__SHIFT 0x0
+#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x3
+#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
+#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xffffffff
+#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0
+#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff
+#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
+#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f
+#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
+#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x1
+#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0
+#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x2
+#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1
+#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xffffffff
+#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0
+#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x1
+#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0
+#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x1
+#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0
+#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xffffffff
+#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0
+#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xffffffff
+#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0
+#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xffffffff
+#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0
+#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xffffffff
+#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0
+#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xffffffff
+#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0xff
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x7f
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xffffffff
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0
+#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x1
+#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0
+#define VGT_ENHANCE__MISC_MASK 0xffffffff
+#define VGT_ENHANCE__MISC__SHIFT 0x0
+#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x7
+#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0
+#define VGT_HOS_CNTL__TESS_MODE_MASK 0x3
+#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0
+#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xffffffff
+#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0
+#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xffffffff
+#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0
+#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0xff
+#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0
+#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x1f
+#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0
+#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x4000
+#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe
+#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x8000
+#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf
+#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x70000
+#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10
+#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0xf
+#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0
+#define VGT_GROUP_DECR__DECR_MASK 0xf
+#define VGT_GROUP_DECR__DECR__SHIFT 0x0
+#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x1
+#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0
+#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x2
+#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1
+#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x4
+#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2
+#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x8
+#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3
+#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0xff00
+#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8
+#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0xff0000
+#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10
+#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x1
+#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0
+#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x2
+#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1
+#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x4
+#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2
+#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x8
+#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3
+#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0xff00
+#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8
+#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0xff0000
+#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0xf
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0xf0
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0xf00
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0xf000
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0xf0000
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0xf00000
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0xf000000
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xf0000000
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0xf
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0xf0
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0xf00
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0xf000
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0xf0000
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0xf00000
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0xf000000
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xf0000000
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x3ff
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0
+#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x1ff
+#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0
+#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x3f
+#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0
+#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x3f
+#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x7
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
+#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x70000
+#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10
+#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000
+#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
+#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000
+#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
+#define VGT_GS_MODE__MODE_MASK 0x7
+#define VGT_GS_MODE__MODE__SHIFT 0x0
+#define VGT_GS_MODE__RESERVED_0_MASK 0x8
+#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3
+#define VGT_GS_MODE__CUT_MODE_MASK 0x30
+#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4
+#define VGT_GS_MODE__RESERVED_1_MASK 0x7c0
+#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6
+#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x800
+#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb
+#define VGT_GS_MODE__RESERVED_2_MASK 0x1000
+#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc
+#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x2000
+#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd
+#define VGT_GS_MODE__RESERVED_3_MASK 0x4000
+#define VGT_GS_MODE__RESERVED_3__SHIFT 0xe
+#define VGT_GS_MODE__RESERVED_4_MASK 0x8000
+#define VGT_GS_MODE__RESERVED_4__SHIFT 0xf
+#define VGT_GS_MODE__RESERVED_5_MASK 0x10000
+#define VGT_GS_MODE__RESERVED_5__SHIFT 0x10
+#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x20000
+#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11
+#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x40000
+#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12
+#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x80000
+#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13
+#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x100000
+#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14
+#define VGT_GS_MODE__ONCHIP_MASK 0x600000
+#define VGT_GS_MODE__ONCHIP__SHIFT 0x15
+#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x7ff
+#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0
+#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x3ff800
+#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x3f
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x3f00
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x3f0000
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0xfc00000
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16
+#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000
+#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f
+#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x3
+#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0
+#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x10
+#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4
+#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x20
+#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5
+#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0xc0
+#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6
+#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x200
+#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9
+#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x800
+#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb
+#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x1000
+#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc
+#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x2000
+#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd
+#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x1f0000
+#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10
+#define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x1
+#define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0
+#define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x2
+#define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1
+#define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x4
+#define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2
+#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0xff
+#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0
+#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x700
+#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8
+#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x3800
+#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb
+#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x1c000
+#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe
+#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0xe0000
+#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11
+#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x7f
+#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0
+#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x80
+#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7
+#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x3fff00
+#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8
+#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0xfc00000
+#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16
+#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x7ff
+#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0
+#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x7ff
+#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0
+#define VGT_GS_PER_VS__GS_PER_VS_MASK 0xf
+#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0
+#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x1f
+#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0
+#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x3
+#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0
+#define IA_CNTL_STATUS__IA_BUSY_MASK 0x1
+#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0
+#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x2
+#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1
+#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x4
+#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2
+#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x8
+#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3
+#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x10
+#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4
+#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x1
+#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0
+#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x2
+#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1
+#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x4
+#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2
+#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x8
+#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3
+#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x70
+#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4
+#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0xf00
+#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8
+#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000
+#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f
+#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x3ff
+#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x3ff
+#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x3ff
+#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x3ff
+#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0xf
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0xf0
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0xf00
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0xf000
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xffffffff
+#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x1ff
+#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0
+#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x7ff
+#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0
+#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x3
+#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0
+#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x4
+#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2
+#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x18
+#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3
+#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x20
+#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5
+#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0xc0
+#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6
+#define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x100
+#define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x8
+#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x200
+#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9
+#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x400
+#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa
+#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x800
+#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb
+#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x1000
+#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc
+#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xffffffff
+#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0
+#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0xff
+#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0
+#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00
+#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
+#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0xfc000
+#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe
+#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00
+#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
+#define VGT_TF_PARAM__TYPE_MASK 0x3
+#define VGT_TF_PARAM__TYPE__SHIFT 0x0
+#define VGT_TF_PARAM__PARTITIONING_MASK 0x1c
+#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2
+#define VGT_TF_PARAM__TOPOLOGY_MASK 0xe0
+#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5
+#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x100
+#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8
+#define VGT_TF_PARAM__DEPRECATED_MASK 0x200
+#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9
+#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x3c00
+#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0xa
+#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x4000
+#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe
+#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x8000
+#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf
+#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x60000
+#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11
+#define VGT_TF_PARAM__MTYPE_MASK 0x180000
+#define VGT_TF_PARAM__MTYPE__SHIFT 0x13
+#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0xff
+#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0
+#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0xff00
+#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8
+#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0xff0000
+#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10
+#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0xff000000
+#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18
+#define VGT_TF_RING_SIZE__SIZE_MASK 0xffff
+#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0
+#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x1
+#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0
+#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x7e
+#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1
+#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x80
+#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x1ff
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x600
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9
+#define VGT_TF_MEMORY_BASE__BASE_MASK 0xffffffff
+#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0
+#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x1
+#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0
+#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x1fc
+#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2
+#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0xffff
+#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0
+#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x10000
+#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x20000
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11
+#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x40000
+#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x80000
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13
+#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x100000
+#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14
+#define IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE_MASK 0xf0000000
+#define IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE__SHIFT 0x1c
+#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
+#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
+#define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xffffffff
+#define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x0
+#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffff
+#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0
+#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x7fff
+#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0
+#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x7fff
+#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0
+#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x7fff
+#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0
+#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff
+#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
+#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff
+#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x7fff
+#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x7fff
+#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x7fff
+#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x7fff
+#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0
+#define WD_CNTL_STATUS__WD_BUSY_MASK 0x1
+#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0
+#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x2
+#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1
+#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x4
+#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2
+#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x8
+#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3
+#define WD_ENHANCE__MISC_MASK 0xffffffff
+#define WD_ENHANCE__MISC__SHIFT 0x0
+#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x1fff
+#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0
+#define GFX_PIPE_CONTROL__RESERVED_MASK 0xe000
+#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd
+#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x10000
+#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10
+#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT_MASK 0x1
+#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT__SHIFT 0x0
+#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
+#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
+#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
+#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000
+#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d
+#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
+#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
+#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
+#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
+#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
+#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
+#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
+#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
+#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
+#define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
+#define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
+#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_WD_CLK_CTRL__ADC_OVERRIDE_MASK 0x10000000
+#define CGTT_WD_CLK_CTRL__ADC_OVERRIDE__SHIFT 0x1c
+#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000
+#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d
+#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000
+#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e
+#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x3f
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x0
+#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B_MASK 0x40
+#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B__SHIFT 0x6
+#define VGT_DEBUG_DATA__DATA_MASK 0xffffffff
+#define VGT_DEBUG_DATA__DATA__SHIFT 0x0
+#define IA_DEBUG_CNTL__IA_DEBUG_INDX_MASK 0x3f
+#define IA_DEBUG_CNTL__IA_DEBUG_INDX__SHIFT 0x0
+#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B_MASK 0x40
+#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B__SHIFT 0x6
+#define IA_DEBUG_DATA__DATA_MASK 0xffffffff
+#define IA_DEBUG_DATA__DATA__SHIFT 0x0
+#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x1
+#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x2
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x4
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2
+#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x8
+#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3
+#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x10
+#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4
+#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x20
+#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5
+#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x40
+#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6
+#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x80
+#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7
+#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x100
+#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8
+#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x200
+#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9
+#define WD_DEBUG_CNTL__WD_DEBUG_INDX_MASK 0x3f
+#define WD_DEBUG_CNTL__WD_DEBUG_INDX__SHIFT 0x0
+#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B_MASK 0x40
+#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B__SHIFT 0x6
+#define WD_DEBUG_DATA__DATA_MASK 0xffffffff
+#define WD_DEBUG_DATA__DATA__SHIFT 0x0
+#define WD_QOS__DRAW_STALL_MASK 0x1
+#define WD_QOS__DRAW_STALL__SHIFT 0x0
+#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000
+#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
+#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000
+#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
+#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000
+#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
+#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000
+#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
+#define WD_DEBUG_REG0__wd_busy_extended_MASK 0x1
+#define WD_DEBUG_REG0__wd_busy_extended__SHIFT 0x0
+#define WD_DEBUG_REG0__wd_nodma_busy_extended_MASK 0x2
+#define WD_DEBUG_REG0__wd_nodma_busy_extended__SHIFT 0x1
+#define WD_DEBUG_REG0__wd_busy_MASK 0x4
+#define WD_DEBUG_REG0__wd_busy__SHIFT 0x2
+#define WD_DEBUG_REG0__wd_nodma_busy_MASK 0x8
+#define WD_DEBUG_REG0__wd_nodma_busy__SHIFT 0x3
+#define WD_DEBUG_REG0__rbiu_busy_MASK 0x10
+#define WD_DEBUG_REG0__rbiu_busy__SHIFT 0x4
+#define WD_DEBUG_REG0__spl_dma_busy_MASK 0x20
+#define WD_DEBUG_REG0__spl_dma_busy__SHIFT 0x5
+#define WD_DEBUG_REG0__spl_di_busy_MASK 0x40
+#define WD_DEBUG_REG0__spl_di_busy__SHIFT 0x6
+#define WD_DEBUG_REG0__vgt0_active_q_MASK 0x80
+#define WD_DEBUG_REG0__vgt0_active_q__SHIFT 0x7
+#define WD_DEBUG_REG0__vgt1_active_q_MASK 0x100
+#define WD_DEBUG_REG0__vgt1_active_q__SHIFT 0x8
+#define WD_DEBUG_REG0__spl_dma_p1_busy_MASK 0x200
+#define WD_DEBUG_REG0__spl_dma_p1_busy__SHIFT 0x9
+#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy_MASK 0x400
+#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy__SHIFT 0xa
+#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy_MASK 0x800
+#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy__SHIFT 0xb
+#define WD_DEBUG_REG0__SPARE2_MASK 0x1000
+#define WD_DEBUG_REG0__SPARE2__SHIFT 0xc
+#define WD_DEBUG_REG0__rbiu_dr_fifo_busy_MASK 0x2000
+#define WD_DEBUG_REG0__rbiu_dr_fifo_busy__SHIFT 0xd
+#define WD_DEBUG_REG0__rbiu_spl_dr_valid_MASK 0x4000
+#define WD_DEBUG_REG0__rbiu_spl_dr_valid__SHIFT 0xe
+#define WD_DEBUG_REG0__spl_rbiu_dr_read_MASK 0x8000
+#define WD_DEBUG_REG0__spl_rbiu_dr_read__SHIFT 0xf
+#define WD_DEBUG_REG0__SPARE3_MASK 0x10000
+#define WD_DEBUG_REG0__SPARE3__SHIFT 0x10
+#define WD_DEBUG_REG0__rbiu_di_fifo_busy_MASK 0x20000
+#define WD_DEBUG_REG0__rbiu_di_fifo_busy__SHIFT 0x11
+#define WD_DEBUG_REG0__rbiu_spl_di_valid_MASK 0x40000
+#define WD_DEBUG_REG0__rbiu_spl_di_valid__SHIFT 0x12
+#define WD_DEBUG_REG0__spl_rbiu_di_read_MASK 0x80000
+#define WD_DEBUG_REG0__spl_rbiu_di_read__SHIFT 0x13
+#define WD_DEBUG_REG0__se0_synced_q_MASK 0x100000
+#define WD_DEBUG_REG0__se0_synced_q__SHIFT 0x14
+#define WD_DEBUG_REG0__se1_synced_q_MASK 0x200000
+#define WD_DEBUG_REG0__se1_synced_q__SHIFT 0x15
+#define WD_DEBUG_REG0__se2_synced_q_MASK 0x400000
+#define WD_DEBUG_REG0__se2_synced_q__SHIFT 0x16
+#define WD_DEBUG_REG0__se3_synced_q_MASK 0x800000
+#define WD_DEBUG_REG0__se3_synced_q__SHIFT 0x17
+#define WD_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
+#define WD_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
+#define WD_DEBUG_REG0__input_clk_busy_MASK 0x2000000
+#define WD_DEBUG_REG0__input_clk_busy__SHIFT 0x19
+#define WD_DEBUG_REG0__core_clk_busy_MASK 0x4000000
+#define WD_DEBUG_REG0__core_clk_busy__SHIFT 0x1a
+#define WD_DEBUG_REG0__vgt2_active_q_MASK 0x8000000
+#define WD_DEBUG_REG0__vgt2_active_q__SHIFT 0x1b
+#define WD_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000
+#define WD_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c
+#define WD_DEBUG_REG0__sclk_input_vld_MASK 0x20000000
+#define WD_DEBUG_REG0__sclk_input_vld__SHIFT 0x1d
+#define WD_DEBUG_REG0__sclk_core_vld_MASK 0x40000000
+#define WD_DEBUG_REG0__sclk_core_vld__SHIFT 0x1e
+#define WD_DEBUG_REG0__vgt3_active_q_MASK 0x80000000
+#define WD_DEBUG_REG0__vgt3_active_q__SHIFT 0x1f
+#define WD_DEBUG_REG1__grbm_fifo_empty_MASK 0x1
+#define WD_DEBUG_REG1__grbm_fifo_empty__SHIFT 0x0
+#define WD_DEBUG_REG1__grbm_fifo_full_MASK 0x2
+#define WD_DEBUG_REG1__grbm_fifo_full__SHIFT 0x1
+#define WD_DEBUG_REG1__grbm_fifo_we_MASK 0x4
+#define WD_DEBUG_REG1__grbm_fifo_we__SHIFT 0x2
+#define WD_DEBUG_REG1__grbm_fifo_re_MASK 0x8
+#define WD_DEBUG_REG1__grbm_fifo_re__SHIFT 0x3
+#define WD_DEBUG_REG1__draw_initiator_valid_q_MASK 0x10
+#define WD_DEBUG_REG1__draw_initiator_valid_q__SHIFT 0x4
+#define WD_DEBUG_REG1__event_initiator_valid_q_MASK 0x20
+#define WD_DEBUG_REG1__event_initiator_valid_q__SHIFT 0x5
+#define WD_DEBUG_REG1__event_addr_valid_q_MASK 0x40
+#define WD_DEBUG_REG1__event_addr_valid_q__SHIFT 0x6
+#define WD_DEBUG_REG1__dma_request_valid_q_MASK 0x80
+#define WD_DEBUG_REG1__dma_request_valid_q__SHIFT 0x7
+#define WD_DEBUG_REG1__SPARE0_MASK 0x100
+#define WD_DEBUG_REG1__SPARE0__SHIFT 0x8
+#define WD_DEBUG_REG1__min_indx_valid_q_MASK 0x200
+#define WD_DEBUG_REG1__min_indx_valid_q__SHIFT 0x9
+#define WD_DEBUG_REG1__max_indx_valid_q_MASK 0x400
+#define WD_DEBUG_REG1__max_indx_valid_q__SHIFT 0xa
+#define WD_DEBUG_REG1__indx_offset_valid_q_MASK 0x800
+#define WD_DEBUG_REG1__indx_offset_valid_q__SHIFT 0xb
+#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id_MASK 0x1f000
+#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id__SHIFT 0xc
+#define WD_DEBUG_REG1__grbm_fifo_rdata_state_MASK 0xe0000
+#define WD_DEBUG_REG1__grbm_fifo_rdata_state__SHIFT 0x11
+#define WD_DEBUG_REG1__free_cnt_q_MASK 0x3f00000
+#define WD_DEBUG_REG1__free_cnt_q__SHIFT 0x14
+#define WD_DEBUG_REG1__rbiu_di_fifo_we_MASK 0x4000000
+#define WD_DEBUG_REG1__rbiu_di_fifo_we__SHIFT 0x1a
+#define WD_DEBUG_REG1__rbiu_dr_fifo_we_MASK 0x8000000
+#define WD_DEBUG_REG1__rbiu_dr_fifo_we__SHIFT 0x1b
+#define WD_DEBUG_REG1__rbiu_di_fifo_empty_MASK 0x10000000
+#define WD_DEBUG_REG1__rbiu_di_fifo_empty__SHIFT 0x1c
+#define WD_DEBUG_REG1__rbiu_di_fifo_full_MASK 0x20000000
+#define WD_DEBUG_REG1__rbiu_di_fifo_full__SHIFT 0x1d
+#define WD_DEBUG_REG1__rbiu_dr_fifo_empty_MASK 0x40000000
+#define WD_DEBUG_REG1__rbiu_dr_fifo_empty__SHIFT 0x1e
+#define WD_DEBUG_REG1__rbiu_dr_fifo_full_MASK 0x80000000
+#define WD_DEBUG_REG1__rbiu_dr_fifo_full__SHIFT 0x1f
+#define WD_DEBUG_REG2__p1_grbm_fifo_empty_MASK 0x1
+#define WD_DEBUG_REG2__p1_grbm_fifo_empty__SHIFT 0x0
+#define WD_DEBUG_REG2__p1_grbm_fifo_full_MASK 0x2
+#define WD_DEBUG_REG2__p1_grbm_fifo_full__SHIFT 0x1
+#define WD_DEBUG_REG2__p1_grbm_fifo_we_MASK 0x4
+#define WD_DEBUG_REG2__p1_grbm_fifo_we__SHIFT 0x2
+#define WD_DEBUG_REG2__p1_grbm_fifo_re_MASK 0x8
+#define WD_DEBUG_REG2__p1_grbm_fifo_re__SHIFT 0x3
+#define WD_DEBUG_REG2__p1_draw_initiator_valid_q_MASK 0x10
+#define WD_DEBUG_REG2__p1_draw_initiator_valid_q__SHIFT 0x4
+#define WD_DEBUG_REG2__p1_event_initiator_valid_q_MASK 0x20
+#define WD_DEBUG_REG2__p1_event_initiator_valid_q__SHIFT 0x5
+#define WD_DEBUG_REG2__p1_event_addr_valid_q_MASK 0x40
+#define WD_DEBUG_REG2__p1_event_addr_valid_q__SHIFT 0x6
+#define WD_DEBUG_REG2__p1_dma_request_valid_q_MASK 0x80
+#define WD_DEBUG_REG2__p1_dma_request_valid_q__SHIFT 0x7
+#define WD_DEBUG_REG2__SPARE0_MASK 0x100
+#define WD_DEBUG_REG2__SPARE0__SHIFT 0x8
+#define WD_DEBUG_REG2__p1_min_indx_valid_q_MASK 0x200
+#define WD_DEBUG_REG2__p1_min_indx_valid_q__SHIFT 0x9
+#define WD_DEBUG_REG2__p1_max_indx_valid_q_MASK 0x400
+#define WD_DEBUG_REG2__p1_max_indx_valid_q__SHIFT 0xa
+#define WD_DEBUG_REG2__p1_indx_offset_valid_q_MASK 0x800
+#define WD_DEBUG_REG2__p1_indx_offset_valid_q__SHIFT 0xb
+#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id_MASK 0x1f000
+#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id__SHIFT 0xc
+#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state_MASK 0xe0000
+#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state__SHIFT 0x11
+#define WD_DEBUG_REG2__p1_free_cnt_q_MASK 0x3f00000
+#define WD_DEBUG_REG2__p1_free_cnt_q__SHIFT 0x14
+#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we_MASK 0x4000000
+#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we__SHIFT 0x1a
+#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we_MASK 0x8000000
+#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we__SHIFT 0x1b
+#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty_MASK 0x10000000
+#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty__SHIFT 0x1c
+#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full_MASK 0x20000000
+#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full__SHIFT 0x1d
+#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty_MASK 0x40000000
+#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty__SHIFT 0x1e
+#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full_MASK 0x80000000
+#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full__SHIFT 0x1f
+#define WD_DEBUG_REG3__rbiu_spl_dr_valid_MASK 0x1
+#define WD_DEBUG_REG3__rbiu_spl_dr_valid__SHIFT 0x0
+#define WD_DEBUG_REG3__SPARE0_MASK 0x2
+#define WD_DEBUG_REG3__SPARE0__SHIFT 0x1
+#define WD_DEBUG_REG3__pipe0_dr_MASK 0x4
+#define WD_DEBUG_REG3__pipe0_dr__SHIFT 0x2
+#define WD_DEBUG_REG3__pipe0_rtr_MASK 0x8
+#define WD_DEBUG_REG3__pipe0_rtr__SHIFT 0x3
+#define WD_DEBUG_REG3__pipe1_dr_MASK 0x10
+#define WD_DEBUG_REG3__pipe1_dr__SHIFT 0x4
+#define WD_DEBUG_REG3__pipe1_rtr_MASK 0x20
+#define WD_DEBUG_REG3__pipe1_rtr__SHIFT 0x5
+#define WD_DEBUG_REG3__wd_subdma_fifo_empty_MASK 0x40
+#define WD_DEBUG_REG3__wd_subdma_fifo_empty__SHIFT 0x6
+#define WD_DEBUG_REG3__wd_subdma_fifo_full_MASK 0x80
+#define WD_DEBUG_REG3__wd_subdma_fifo_full__SHIFT 0x7
+#define WD_DEBUG_REG3__dma_buf_type_p0_q_MASK 0x300
+#define WD_DEBUG_REG3__dma_buf_type_p0_q__SHIFT 0x8
+#define WD_DEBUG_REG3__dma_zero_indices_p0_q_MASK 0x400
+#define WD_DEBUG_REG3__dma_zero_indices_p0_q__SHIFT 0xa
+#define WD_DEBUG_REG3__dma_req_path_p3_q_MASK 0x800
+#define WD_DEBUG_REG3__dma_req_path_p3_q__SHIFT 0xb
+#define WD_DEBUG_REG3__dma_not_eop_p1_q_MASK 0x1000
+#define WD_DEBUG_REG3__dma_not_eop_p1_q__SHIFT 0xc
+#define WD_DEBUG_REG3__out_of_range_p4_MASK 0x2000
+#define WD_DEBUG_REG3__out_of_range_p4__SHIFT 0xd
+#define WD_DEBUG_REG3__last_sub_dma_p3_q_MASK 0x4000
+#define WD_DEBUG_REG3__last_sub_dma_p3_q__SHIFT 0xe
+#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4_MASK 0x8000
+#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4__SHIFT 0xf
+#define WD_DEBUG_REG3__WD_IA_dma_send_d_MASK 0x10000
+#define WD_DEBUG_REG3__WD_IA_dma_send_d__SHIFT 0x10
+#define WD_DEBUG_REG3__WD_IA_dma_rtr_MASK 0x20000
+#define WD_DEBUG_REG3__WD_IA_dma_rtr__SHIFT 0x11
+#define WD_DEBUG_REG3__WD_IA1_dma_send_d_MASK 0x40000
+#define WD_DEBUG_REG3__WD_IA1_dma_send_d__SHIFT 0x12
+#define WD_DEBUG_REG3__WD_IA1_dma_rtr_MASK 0x80000
+#define WD_DEBUG_REG3__WD_IA1_dma_rtr__SHIFT 0x13
+#define WD_DEBUG_REG3__last_inst_of_dma_p2_MASK 0x100000
+#define WD_DEBUG_REG3__last_inst_of_dma_p2__SHIFT 0x14
+#define WD_DEBUG_REG3__last_sd_of_inst_p2_MASK 0x200000
+#define WD_DEBUG_REG3__last_sd_of_inst_p2__SHIFT 0x15
+#define WD_DEBUG_REG3__last_sd_of_dma_p2_MASK 0x400000
+#define WD_DEBUG_REG3__last_sd_of_dma_p2__SHIFT 0x16
+#define WD_DEBUG_REG3__SPARE1_MASK 0x800000
+#define WD_DEBUG_REG3__SPARE1__SHIFT 0x17
+#define WD_DEBUG_REG3__WD_IA_dma_busy_MASK 0x1000000
+#define WD_DEBUG_REG3__WD_IA_dma_busy__SHIFT 0x18
+#define WD_DEBUG_REG3__WD_IA1_dma_busy_MASK 0x2000000
+#define WD_DEBUG_REG3__WD_IA1_dma_busy__SHIFT 0x19
+#define WD_DEBUG_REG3__send_to_ia1_p3_q_MASK 0x4000000
+#define WD_DEBUG_REG3__send_to_ia1_p3_q__SHIFT 0x1a
+#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q_MASK 0x8000000
+#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q__SHIFT 0x1b
+#define WD_DEBUG_REG3__pipe3_dr_MASK 0x10000000
+#define WD_DEBUG_REG3__pipe3_dr__SHIFT 0x1c
+#define WD_DEBUG_REG3__pipe3_rtr_MASK 0x20000000
+#define WD_DEBUG_REG3__pipe3_rtr__SHIFT 0x1d
+#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty_MASK 0x40000000
+#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty__SHIFT 0x1e
+#define WD_DEBUG_REG3__wd_dma2draw_fifo_full_MASK 0x80000000
+#define WD_DEBUG_REG3__wd_dma2draw_fifo_full__SHIFT 0x1f
+#define WD_DEBUG_REG4__rbiu_spl_di_valid_MASK 0x1
+#define WD_DEBUG_REG4__rbiu_spl_di_valid__SHIFT 0x0
+#define WD_DEBUG_REG4__spl_rbiu_di_read_MASK 0x2
+#define WD_DEBUG_REG4__spl_rbiu_di_read__SHIFT 0x1
+#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid_MASK 0x4
+#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid__SHIFT 0x2
+#define WD_DEBUG_REG4__spl_rbiu_p1_di_read_MASK 0x8
+#define WD_DEBUG_REG4__spl_rbiu_p1_di_read__SHIFT 0x3
+#define WD_DEBUG_REG4__pipe0_dr_MASK 0x10
+#define WD_DEBUG_REG4__pipe0_dr__SHIFT 0x4
+#define WD_DEBUG_REG4__pipe0_rtr_MASK 0x20
+#define WD_DEBUG_REG4__pipe0_rtr__SHIFT 0x5
+#define WD_DEBUG_REG4__pipe1_dr_MASK 0x40
+#define WD_DEBUG_REG4__pipe1_dr__SHIFT 0x6
+#define WD_DEBUG_REG4__pipe1_rtr_MASK 0x80
+#define WD_DEBUG_REG4__pipe1_rtr__SHIFT 0x7
+#define WD_DEBUG_REG4__pipe2_dr_MASK 0x100
+#define WD_DEBUG_REG4__pipe2_dr__SHIFT 0x8
+#define WD_DEBUG_REG4__pipe2_rtr_MASK 0x200
+#define WD_DEBUG_REG4__pipe2_rtr__SHIFT 0x9
+#define WD_DEBUG_REG4__pipe3_ld_MASK 0x400
+#define WD_DEBUG_REG4__pipe3_ld__SHIFT 0xa
+#define WD_DEBUG_REG4__pipe3_rtr_MASK 0x800
+#define WD_DEBUG_REG4__pipe3_rtr__SHIFT 0xb
+#define WD_DEBUG_REG4__WD_IA_draw_send_d_MASK 0x1000
+#define WD_DEBUG_REG4__WD_IA_draw_send_d__SHIFT 0xc
+#define WD_DEBUG_REG4__WD_IA_draw_rtr_MASK 0x2000
+#define WD_DEBUG_REG4__WD_IA_draw_rtr__SHIFT 0xd
+#define WD_DEBUG_REG4__di_type_p0_MASK 0xc000
+#define WD_DEBUG_REG4__di_type_p0__SHIFT 0xe
+#define WD_DEBUG_REG4__di_state_sel_p1_q_MASK 0x70000
+#define WD_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x10
+#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q_MASK 0x80000
+#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q__SHIFT 0x13
+#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout_MASK 0x100000
+#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout__SHIFT 0x14
+#define WD_DEBUG_REG4__last_inst_of_di_p2_MASK 0x200000
+#define WD_DEBUG_REG4__last_inst_of_di_p2__SHIFT 0x15
+#define WD_DEBUG_REG4__last_sd_of_inst_p2_MASK 0x400000
+#define WD_DEBUG_REG4__last_sd_of_inst_p2__SHIFT 0x16
+#define WD_DEBUG_REG4__last_sd_of_di_p2_MASK 0x800000
+#define WD_DEBUG_REG4__last_sd_of_di_p2__SHIFT 0x17
+#define WD_DEBUG_REG4__not_eop_wait_p1_q_MASK 0x1000000
+#define WD_DEBUG_REG4__not_eop_wait_p1_q__SHIFT 0x18
+#define WD_DEBUG_REG4__not_eop_wait_q_MASK 0x2000000
+#define WD_DEBUG_REG4__not_eop_wait_q__SHIFT 0x19
+#define WD_DEBUG_REG4__ext_event_wait_p1_q_MASK 0x4000000
+#define WD_DEBUG_REG4__ext_event_wait_p1_q__SHIFT 0x1a
+#define WD_DEBUG_REG4__ext_event_wait_q_MASK 0x8000000
+#define WD_DEBUG_REG4__ext_event_wait_q__SHIFT 0x1b
+#define WD_DEBUG_REG4__WD_IA1_draw_send_d_MASK 0x10000000
+#define WD_DEBUG_REG4__WD_IA1_draw_send_d__SHIFT 0x1c
+#define WD_DEBUG_REG4__WD_IA1_draw_rtr_MASK 0x20000000
+#define WD_DEBUG_REG4__WD_IA1_draw_rtr__SHIFT 0x1d
+#define WD_DEBUG_REG4__send_to_ia1_q_MASK 0x40000000
+#define WD_DEBUG_REG4__send_to_ia1_q__SHIFT 0x1e
+#define WD_DEBUG_REG4__dual_ia_mode_MASK 0x80000000
+#define WD_DEBUG_REG4__dual_ia_mode__SHIFT 0x1f
+#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid_MASK 0x1
+#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid__SHIFT 0x0
+#define WD_DEBUG_REG5__SPARE0_MASK 0x2
+#define WD_DEBUG_REG5__SPARE0__SHIFT 0x1
+#define WD_DEBUG_REG5__p1_pipe0_dr_MASK 0x4
+#define WD_DEBUG_REG5__p1_pipe0_dr__SHIFT 0x2
+#define WD_DEBUG_REG5__p1_pipe0_rtr_MASK 0x8
+#define WD_DEBUG_REG5__p1_pipe0_rtr__SHIFT 0x3
+#define WD_DEBUG_REG5__p1_pipe1_dr_MASK 0x10
+#define WD_DEBUG_REG5__p1_pipe1_dr__SHIFT 0x4
+#define WD_DEBUG_REG5__p1_pipe1_rtr_MASK 0x20
+#define WD_DEBUG_REG5__p1_pipe1_rtr__SHIFT 0x5
+#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty_MASK 0x40
+#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty__SHIFT 0x6
+#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full_MASK 0x80
+#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full__SHIFT 0x7
+#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q_MASK 0x300
+#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q__SHIFT 0x8
+#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q_MASK 0x400
+#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q__SHIFT 0xa
+#define WD_DEBUG_REG5__p1_dma_req_path_p3_q_MASK 0x800
+#define WD_DEBUG_REG5__p1_dma_req_path_p3_q__SHIFT 0xb
+#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q_MASK 0x1000
+#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q__SHIFT 0xc
+#define WD_DEBUG_REG5__p1_out_of_range_p4_MASK 0x2000
+#define WD_DEBUG_REG5__p1_out_of_range_p4__SHIFT 0xd
+#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q_MASK 0x4000
+#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q__SHIFT 0xe
+#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4_MASK 0x8000
+#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4__SHIFT 0xf
+#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d_MASK 0x10000
+#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d__SHIFT 0x10
+#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr_MASK 0x20000
+#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr__SHIFT 0x11
+#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d_MASK 0x40000
+#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d__SHIFT 0x12
+#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr_MASK 0x80000
+#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr__SHIFT 0x13
+#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2_MASK 0x100000
+#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2__SHIFT 0x14
+#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2_MASK 0x200000
+#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2__SHIFT 0x15
+#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2_MASK 0x400000
+#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2__SHIFT 0x16
+#define WD_DEBUG_REG5__SPARE1_MASK 0x800000
+#define WD_DEBUG_REG5__SPARE1__SHIFT 0x17
+#define WD_DEBUG_REG5__p1_WD_IA_dma_busy_MASK 0x1000000
+#define WD_DEBUG_REG5__p1_WD_IA_dma_busy__SHIFT 0x18
+#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy_MASK 0x2000000
+#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy__SHIFT 0x19
+#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q_MASK 0x4000000
+#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q__SHIFT 0x1a
+#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q_MASK 0x8000000
+#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q__SHIFT 0x1b
+#define WD_DEBUG_REG5__p1_pipe3_dr_MASK 0x10000000
+#define WD_DEBUG_REG5__p1_pipe3_dr__SHIFT 0x1c
+#define WD_DEBUG_REG5__p1_pipe3_rtr_MASK 0x20000000
+#define WD_DEBUG_REG5__p1_pipe3_rtr__SHIFT 0x1d
+#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty_MASK 0x40000000
+#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty__SHIFT 0x1e
+#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full_MASK 0x80000000
+#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full__SHIFT 0x1f
+#define WD_DEBUG_REG6__WD_IA_draw_eop_MASK 0xffffffff
+#define WD_DEBUG_REG6__WD_IA_draw_eop__SHIFT 0x0
+#define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in_MASK 0x1
+#define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in__SHIFT 0x0
+#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re_MASK 0x2
+#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re__SHIFT 0x1
+#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty_MASK 0x4
+#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty__SHIFT 0x2
+#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full_MASK 0x8
+#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full__SHIFT 0x3
+#define WD_DEBUG_REG7__SPARE0_MASK 0xf0
+#define WD_DEBUG_REG7__SPARE0__SHIFT 0x4
+#define WD_DEBUG_REG7__SPARE1_MASK 0xf00
+#define WD_DEBUG_REG7__SPARE1__SHIFT 0x8
+#define WD_DEBUG_REG7__SPARE2_MASK 0xf000
+#define WD_DEBUG_REG7__SPARE2__SHIFT 0xc
+#define WD_DEBUG_REG7__SPARE3_MASK 0xf0000
+#define WD_DEBUG_REG7__SPARE3__SHIFT 0x10
+#define WD_DEBUG_REG7__se0_thdgrp_is_event_MASK 0x100000
+#define WD_DEBUG_REG7__se0_thdgrp_is_event__SHIFT 0x14
+#define WD_DEBUG_REG7__se0_thdgrp_eop_MASK 0x200000
+#define WD_DEBUG_REG7__se0_thdgrp_eop__SHIFT 0x15
+#define WD_DEBUG_REG7__SPARE4_MASK 0xfc00000
+#define WD_DEBUG_REG7__SPARE4__SHIFT 0x16
+#define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr_MASK 0x10000000
+#define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr__SHIFT 0x1c
+#define WD_DEBUG_REG7__arb_tfreq_tgroup_rts_MASK 0x20000000
+#define WD_DEBUG_REG7__arb_tfreq_tgroup_rts__SHIFT 0x1d
+#define WD_DEBUG_REG7__arb_tfreq_tgroup_event_MASK 0x40000000
+#define WD_DEBUG_REG7__arb_tfreq_tgroup_event__SHIFT 0x1e
+#define WD_DEBUG_REG7__te11_arb_busy_MASK 0x80000000
+#define WD_DEBUG_REG7__te11_arb_busy__SHIFT 0x1f
+#define WD_DEBUG_REG8__pipe0_dr_MASK 0x1
+#define WD_DEBUG_REG8__pipe0_dr__SHIFT 0x0
+#define WD_DEBUG_REG8__pipe1_dr_MASK 0x2
+#define WD_DEBUG_REG8__pipe1_dr__SHIFT 0x1
+#define WD_DEBUG_REG8__pipe0_rtr_MASK 0x4
+#define WD_DEBUG_REG8__pipe0_rtr__SHIFT 0x2
+#define WD_DEBUG_REG8__pipe1_rtr_MASK 0x8
+#define WD_DEBUG_REG8__pipe1_rtr__SHIFT 0x3
+#define WD_DEBUG_REG8__tfreq_tg_fifo_empty_MASK 0x10
+#define WD_DEBUG_REG8__tfreq_tg_fifo_empty__SHIFT 0x4
+#define WD_DEBUG_REG8__tfreq_tg_fifo_full_MASK 0x20
+#define WD_DEBUG_REG8__tfreq_tg_fifo_full__SHIFT 0x5
+#define WD_DEBUG_REG8__tf_data_fifo_busy_q_MASK 0x40
+#define WD_DEBUG_REG8__tf_data_fifo_busy_q__SHIFT 0x6
+#define WD_DEBUG_REG8__tf_data_fifo_rtr_q_MASK 0x80
+#define WD_DEBUG_REG8__tf_data_fifo_rtr_q__SHIFT 0x7
+#define WD_DEBUG_REG8__tf_skid_fifo_empty_MASK 0x100
+#define WD_DEBUG_REG8__tf_skid_fifo_empty__SHIFT 0x8
+#define WD_DEBUG_REG8__tf_skid_fifo_full_MASK 0x200
+#define WD_DEBUG_REG8__tf_skid_fifo_full__SHIFT 0x9
+#define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q_MASK 0x400
+#define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q__SHIFT 0xa
+#define WD_DEBUG_REG8__last_req_of_tg_p2_MASK 0x800
+#define WD_DEBUG_REG8__last_req_of_tg_p2__SHIFT 0xb
+#define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q_MASK 0x3f000
+#define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q__SHIFT 0xc
+#define WD_DEBUG_REG8__event_flag_p1_q_MASK 0x40000
+#define WD_DEBUG_REG8__event_flag_p1_q__SHIFT 0x12
+#define WD_DEBUG_REG8__null_flag_p1_q_MASK 0x80000
+#define WD_DEBUG_REG8__null_flag_p1_q__SHIFT 0x13
+#define WD_DEBUG_REG8__tf_data_fifo_cnt_q_MASK 0x7f00000
+#define WD_DEBUG_REG8__tf_data_fifo_cnt_q__SHIFT 0x14
+#define WD_DEBUG_REG8__second_tf_ret_data_q_MASK 0x8000000
+#define WD_DEBUG_REG8__second_tf_ret_data_q__SHIFT 0x1b
+#define WD_DEBUG_REG8__first_req_of_tg_p1_q_MASK 0x10000000
+#define WD_DEBUG_REG8__first_req_of_tg_p1_q__SHIFT 0x1c
+#define WD_DEBUG_REG8__WD_TC_rdreq_send_out_MASK 0x20000000
+#define WD_DEBUG_REG8__WD_TC_rdreq_send_out__SHIFT 0x1d
+#define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out_MASK 0x40000000
+#define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out__SHIFT 0x1e
+#define WD_DEBUG_REG8__TC_WD_rdret_valid_in_MASK 0x80000000
+#define WD_DEBUG_REG8__TC_WD_rdret_valid_in__SHIFT 0x1f
+#define WD_DEBUG_REG9__pipe0_dr_MASK 0x1
+#define WD_DEBUG_REG9__pipe0_dr__SHIFT 0x0
+#define WD_DEBUG_REG9__pipec_tf_dr_MASK 0x2
+#define WD_DEBUG_REG9__pipec_tf_dr__SHIFT 0x1
+#define WD_DEBUG_REG9__pipe2_dr_MASK 0x4
+#define WD_DEBUG_REG9__pipe2_dr__SHIFT 0x2
+#define WD_DEBUG_REG9__event_or_null_flags_p0_q_MASK 0x8
+#define WD_DEBUG_REG9__event_or_null_flags_p0_q__SHIFT 0x3
+#define WD_DEBUG_REG9__pipe0_rtr_MASK 0x10
+#define WD_DEBUG_REG9__pipe0_rtr__SHIFT 0x4
+#define WD_DEBUG_REG9__pipe1_rtr_MASK 0x20
+#define WD_DEBUG_REG9__pipe1_rtr__SHIFT 0x5
+#define WD_DEBUG_REG9__pipec_tf_rtr_MASK 0x40
+#define WD_DEBUG_REG9__pipec_tf_rtr__SHIFT 0x6
+#define WD_DEBUG_REG9__pipe2_rtr_MASK 0x80
+#define WD_DEBUG_REG9__pipe2_rtr__SHIFT 0x7
+#define WD_DEBUG_REG9__ttp_patch_fifo_full_MASK 0x100
+#define WD_DEBUG_REG9__ttp_patch_fifo_full__SHIFT 0x8
+#define WD_DEBUG_REG9__ttp_patch_fifo_empty_MASK 0x200
+#define WD_DEBUG_REG9__ttp_patch_fifo_empty__SHIFT 0x9
+#define WD_DEBUG_REG9__ttp_tf_fifo_empty_MASK 0x400
+#define WD_DEBUG_REG9__ttp_tf_fifo_empty__SHIFT 0xa
+#define WD_DEBUG_REG9__SPARE0_MASK 0xf800
+#define WD_DEBUG_REG9__SPARE0__SHIFT 0xb
+#define WD_DEBUG_REG9__tf_fetch_state_q_MASK 0x70000
+#define WD_DEBUG_REG9__tf_fetch_state_q__SHIFT 0x10
+#define WD_DEBUG_REG9__last_patch_of_tg_MASK 0x80000
+#define WD_DEBUG_REG9__last_patch_of_tg__SHIFT 0x13
+#define WD_DEBUG_REG9__tf_pointer_p0_q_MASK 0xf00000
+#define WD_DEBUG_REG9__tf_pointer_p0_q__SHIFT 0x14
+#define WD_DEBUG_REG9__dynamic_hs_p0_q_MASK 0x1000000
+#define WD_DEBUG_REG9__dynamic_hs_p0_q__SHIFT 0x18
+#define WD_DEBUG_REG9__first_fetch_of_tg_p0_q_MASK 0x2000000
+#define WD_DEBUG_REG9__first_fetch_of_tg_p0_q__SHIFT 0x19
+#define WD_DEBUG_REG9__mem_is_even_MASK 0x4000000
+#define WD_DEBUG_REG9__mem_is_even__SHIFT 0x1a
+#define WD_DEBUG_REG9__SPARE1_MASK 0x8000000
+#define WD_DEBUG_REG9__SPARE1__SHIFT 0x1b
+#define WD_DEBUG_REG9__SPARE2_MASK 0x30000000
+#define WD_DEBUG_REG9__SPARE2__SHIFT 0x1c
+#define WD_DEBUG_REG9__pipe4_dr_MASK 0x40000000
+#define WD_DEBUG_REG9__pipe4_dr__SHIFT 0x1e
+#define WD_DEBUG_REG9__pipe4_rtr_MASK 0x80000000
+#define WD_DEBUG_REG9__pipe4_rtr__SHIFT 0x1f
+#define WD_DEBUG_REG10__ttp_pd_patch_rts_MASK 0x1
+#define WD_DEBUG_REG10__ttp_pd_patch_rts__SHIFT 0x0
+#define WD_DEBUG_REG10__ttp_pd_is_event_MASK 0x2
+#define WD_DEBUG_REG10__ttp_pd_is_event__SHIFT 0x1
+#define WD_DEBUG_REG10__ttp_pd_eopg_MASK 0x4
+#define WD_DEBUG_REG10__ttp_pd_eopg__SHIFT 0x2
+#define WD_DEBUG_REG10__ttp_pd_eop_MASK 0x8
+#define WD_DEBUG_REG10__ttp_pd_eop__SHIFT 0x3
+#define WD_DEBUG_REG10__pipe0_dr_MASK 0x10
+#define WD_DEBUG_REG10__pipe0_dr__SHIFT 0x4
+#define WD_DEBUG_REG10__pipe1_dr_MASK 0x20
+#define WD_DEBUG_REG10__pipe1_dr__SHIFT 0x5
+#define WD_DEBUG_REG10__pipe0_rtr_MASK 0x40
+#define WD_DEBUG_REG10__pipe0_rtr__SHIFT 0x6
+#define WD_DEBUG_REG10__pipe1_rtr_MASK 0x80
+#define WD_DEBUG_REG10__pipe1_rtr__SHIFT 0x7
+#define WD_DEBUG_REG10__donut_en_p1_q_MASK 0x100
+#define WD_DEBUG_REG10__donut_en_p1_q__SHIFT 0x8
+#define WD_DEBUG_REG10__donut_se_switch_p2_MASK 0x200
+#define WD_DEBUG_REG10__donut_se_switch_p2__SHIFT 0x9
+#define WD_DEBUG_REG10__patch_se_switch_p2_MASK 0x400
+#define WD_DEBUG_REG10__patch_se_switch_p2__SHIFT 0xa
+#define WD_DEBUG_REG10__last_donut_switch_p2_MASK 0x800
+#define WD_DEBUG_REG10__last_donut_switch_p2__SHIFT 0xb
+#define WD_DEBUG_REG10__last_donut_of_patch_p2_MASK 0x1000
+#define WD_DEBUG_REG10__last_donut_of_patch_p2__SHIFT 0xc
+#define WD_DEBUG_REG10__is_event_p1_q_MASK 0x2000
+#define WD_DEBUG_REG10__is_event_p1_q__SHIFT 0xd
+#define WD_DEBUG_REG10__eopg_p1_q_MASK 0x4000
+#define WD_DEBUG_REG10__eopg_p1_q__SHIFT 0xe
+#define WD_DEBUG_REG10__eop_p1_q_MASK 0x8000
+#define WD_DEBUG_REG10__eop_p1_q__SHIFT 0xf
+#define WD_DEBUG_REG10__patch_accum_q_MASK 0xff0000
+#define WD_DEBUG_REG10__patch_accum_q__SHIFT 0x10
+#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full_MASK 0x1000000
+#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full__SHIFT 0x18
+#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty_MASK 0x2000000
+#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty__SHIFT 0x19
+#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full_MASK 0x4000000
+#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full__SHIFT 0x1a
+#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty_MASK 0x8000000
+#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty__SHIFT 0x1b
+#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full_MASK 0x10000000
+#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full__SHIFT 0x1c
+#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty_MASK 0x20000000
+#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty__SHIFT 0x1d
+#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full_MASK 0x40000000
+#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full__SHIFT 0x1e
+#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty_MASK 0x80000000
+#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty__SHIFT 0x1f
+#define IA_DEBUG_REG0__ia_busy_extended_MASK 0x1
+#define IA_DEBUG_REG0__ia_busy_extended__SHIFT 0x0
+#define IA_DEBUG_REG0__ia_nodma_busy_extended_MASK 0x2
+#define IA_DEBUG_REG0__ia_nodma_busy_extended__SHIFT 0x1
+#define IA_DEBUG_REG0__ia_busy_MASK 0x4
+#define IA_DEBUG_REG0__ia_busy__SHIFT 0x2
+#define IA_DEBUG_REG0__ia_nodma_busy_MASK 0x8
+#define IA_DEBUG_REG0__ia_nodma_busy__SHIFT 0x3
+#define IA_DEBUG_REG0__SPARE0_MASK 0x10
+#define IA_DEBUG_REG0__SPARE0__SHIFT 0x4
+#define IA_DEBUG_REG0__dma_req_busy_MASK 0x20
+#define IA_DEBUG_REG0__dma_req_busy__SHIFT 0x5
+#define IA_DEBUG_REG0__dma_busy_MASK 0x40
+#define IA_DEBUG_REG0__dma_busy__SHIFT 0x6
+#define IA_DEBUG_REG0__mc_xl8r_busy_MASK 0x80
+#define IA_DEBUG_REG0__mc_xl8r_busy__SHIFT 0x7
+#define IA_DEBUG_REG0__grp_busy_MASK 0x100
+#define IA_DEBUG_REG0__grp_busy__SHIFT 0x8
+#define IA_DEBUG_REG0__SPARE1_MASK 0x200
+#define IA_DEBUG_REG0__SPARE1__SHIFT 0x9
+#define IA_DEBUG_REG0__dma_grp_valid_MASK 0x400
+#define IA_DEBUG_REG0__dma_grp_valid__SHIFT 0xa
+#define IA_DEBUG_REG0__grp_dma_read_MASK 0x800
+#define IA_DEBUG_REG0__grp_dma_read__SHIFT 0xb
+#define IA_DEBUG_REG0__dma_grp_hp_valid_MASK 0x1000
+#define IA_DEBUG_REG0__dma_grp_hp_valid__SHIFT 0xc
+#define IA_DEBUG_REG0__grp_dma_hp_read_MASK 0x2000
+#define IA_DEBUG_REG0__grp_dma_hp_read__SHIFT 0xd
+#define IA_DEBUG_REG0__SPARE2_MASK 0xffc000
+#define IA_DEBUG_REG0__SPARE2__SHIFT 0xe
+#define IA_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
+#define IA_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
+#define IA_DEBUG_REG0__core_clk_busy_MASK 0x2000000
+#define IA_DEBUG_REG0__core_clk_busy__SHIFT 0x19
+#define IA_DEBUG_REG0__SPARE3_MASK 0x4000000
+#define IA_DEBUG_REG0__SPARE3__SHIFT 0x1a
+#define IA_DEBUG_REG0__SPARE4_MASK 0x8000000
+#define IA_DEBUG_REG0__SPARE4__SHIFT 0x1b
+#define IA_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000
+#define IA_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c
+#define IA_DEBUG_REG0__sclk_core_vld_MASK 0x20000000
+#define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d
+#define IA_DEBUG_REG0__SPARE5_MASK 0x40000000
+#define IA_DEBUG_REG0__SPARE5__SHIFT 0x1e
+#define IA_DEBUG_REG0__SPARE6_MASK 0x80000000
+#define IA_DEBUG_REG0__SPARE6__SHIFT 0x1f
+#define IA_DEBUG_REG1__dma_input_fifo_empty_MASK 0x1
+#define IA_DEBUG_REG1__dma_input_fifo_empty__SHIFT 0x0
+#define IA_DEBUG_REG1__dma_input_fifo_full_MASK 0x2
+#define IA_DEBUG_REG1__dma_input_fifo_full__SHIFT 0x1
+#define IA_DEBUG_REG1__start_new_packet_MASK 0x4
+#define IA_DEBUG_REG1__start_new_packet__SHIFT 0x2
+#define IA_DEBUG_REG1__dma_rdreq_dr_q_MASK 0x8
+#define IA_DEBUG_REG1__dma_rdreq_dr_q__SHIFT 0x3
+#define IA_DEBUG_REG1__dma_zero_indices_q_MASK 0x10
+#define IA_DEBUG_REG1__dma_zero_indices_q__SHIFT 0x4
+#define IA_DEBUG_REG1__dma_buf_type_q_MASK 0x60
+#define IA_DEBUG_REG1__dma_buf_type_q__SHIFT 0x5
+#define IA_DEBUG_REG1__dma_req_path_q_MASK 0x80
+#define IA_DEBUG_REG1__dma_req_path_q__SHIFT 0x7
+#define IA_DEBUG_REG1__discard_1st_chunk_MASK 0x100
+#define IA_DEBUG_REG1__discard_1st_chunk__SHIFT 0x8
+#define IA_DEBUG_REG1__discard_2nd_chunk_MASK 0x200
+#define IA_DEBUG_REG1__discard_2nd_chunk__SHIFT 0x9
+#define IA_DEBUG_REG1__second_tc_ret_data_q_MASK 0x400
+#define IA_DEBUG_REG1__second_tc_ret_data_q__SHIFT 0xa
+#define IA_DEBUG_REG1__dma_tc_ret_sel_q_MASK 0x800
+#define IA_DEBUG_REG1__dma_tc_ret_sel_q__SHIFT 0xb
+#define IA_DEBUG_REG1__last_rdreq_in_dma_op_MASK 0x1000
+#define IA_DEBUG_REG1__last_rdreq_in_dma_op__SHIFT 0xc
+#define IA_DEBUG_REG1__dma_mask_fifo_empty_MASK 0x2000
+#define IA_DEBUG_REG1__dma_mask_fifo_empty__SHIFT 0xd
+#define IA_DEBUG_REG1__dma_data_fifo_empty_q_MASK 0x4000
+#define IA_DEBUG_REG1__dma_data_fifo_empty_q__SHIFT 0xe
+#define IA_DEBUG_REG1__dma_data_fifo_full_MASK 0x8000
+#define IA_DEBUG_REG1__dma_data_fifo_full__SHIFT 0xf
+#define IA_DEBUG_REG1__dma_req_fifo_empty_MASK 0x10000
+#define IA_DEBUG_REG1__dma_req_fifo_empty__SHIFT 0x10
+#define IA_DEBUG_REG1__dma_req_fifo_full_MASK 0x20000
+#define IA_DEBUG_REG1__dma_req_fifo_full__SHIFT 0x11
+#define IA_DEBUG_REG1__stage2_dr_MASK 0x40000
+#define IA_DEBUG_REG1__stage2_dr__SHIFT 0x12
+#define IA_DEBUG_REG1__stage2_rtr_MASK 0x80000
+#define IA_DEBUG_REG1__stage2_rtr__SHIFT 0x13
+#define IA_DEBUG_REG1__stage3_dr_MASK 0x100000
+#define IA_DEBUG_REG1__stage3_dr__SHIFT 0x14
+#define IA_DEBUG_REG1__stage3_rtr_MASK 0x200000
+#define IA_DEBUG_REG1__stage3_rtr__SHIFT 0x15
+#define IA_DEBUG_REG1__stage4_dr_MASK 0x400000
+#define IA_DEBUG_REG1__stage4_dr__SHIFT 0x16
+#define IA_DEBUG_REG1__stage4_rtr_MASK 0x800000
+#define IA_DEBUG_REG1__stage4_rtr__SHIFT 0x17
+#define IA_DEBUG_REG1__dma_skid_fifo_empty_MASK 0x1000000
+#define IA_DEBUG_REG1__dma_skid_fifo_empty__SHIFT 0x18
+#define IA_DEBUG_REG1__dma_skid_fifo_full_MASK 0x2000000
+#define IA_DEBUG_REG1__dma_skid_fifo_full__SHIFT 0x19
+#define IA_DEBUG_REG1__dma_grp_valid_MASK 0x4000000
+#define IA_DEBUG_REG1__dma_grp_valid__SHIFT 0x1a
+#define IA_DEBUG_REG1__grp_dma_read_MASK 0x8000000
+#define IA_DEBUG_REG1__grp_dma_read__SHIFT 0x1b
+#define IA_DEBUG_REG1__current_data_valid_MASK 0x10000000
+#define IA_DEBUG_REG1__current_data_valid__SHIFT 0x1c
+#define IA_DEBUG_REG1__out_of_range_r2_q_MASK 0x20000000
+#define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT 0x1d
+#define IA_DEBUG_REG1__dma_mask_fifo_we_MASK 0x40000000
+#define IA_DEBUG_REG1__dma_mask_fifo_we__SHIFT 0x1e
+#define IA_DEBUG_REG1__dma_ret_data_we_q_MASK 0x80000000
+#define IA_DEBUG_REG1__dma_ret_data_we_q__SHIFT 0x1f
+#define IA_DEBUG_REG2__hp_dma_input_fifo_empty_MASK 0x1
+#define IA_DEBUG_REG2__hp_dma_input_fifo_empty__SHIFT 0x0
+#define IA_DEBUG_REG2__hp_dma_input_fifo_full_MASK 0x2
+#define IA_DEBUG_REG2__hp_dma_input_fifo_full__SHIFT 0x1
+#define IA_DEBUG_REG2__hp_start_new_packet_MASK 0x4
+#define IA_DEBUG_REG2__hp_start_new_packet__SHIFT 0x2
+#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q_MASK 0x8
+#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q__SHIFT 0x3
+#define IA_DEBUG_REG2__hp_dma_zero_indices_q_MASK 0x10
+#define IA_DEBUG_REG2__hp_dma_zero_indices_q__SHIFT 0x4
+#define IA_DEBUG_REG2__hp_dma_buf_type_q_MASK 0x60
+#define IA_DEBUG_REG2__hp_dma_buf_type_q__SHIFT 0x5
+#define IA_DEBUG_REG2__hp_dma_req_path_q_MASK 0x80
+#define IA_DEBUG_REG2__hp_dma_req_path_q__SHIFT 0x7
+#define IA_DEBUG_REG2__hp_discard_1st_chunk_MASK 0x100
+#define IA_DEBUG_REG2__hp_discard_1st_chunk__SHIFT 0x8
+#define IA_DEBUG_REG2__hp_discard_2nd_chunk_MASK 0x200
+#define IA_DEBUG_REG2__hp_discard_2nd_chunk__SHIFT 0x9
+#define IA_DEBUG_REG2__hp_second_tc_ret_data_q_MASK 0x400
+#define IA_DEBUG_REG2__hp_second_tc_ret_data_q__SHIFT 0xa
+#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q_MASK 0x800
+#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q__SHIFT 0xb
+#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op_MASK 0x1000
+#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op__SHIFT 0xc
+#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty_MASK 0x2000
+#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty__SHIFT 0xd
+#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q_MASK 0x4000
+#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q__SHIFT 0xe
+#define IA_DEBUG_REG2__hp_dma_data_fifo_full_MASK 0x8000
+#define IA_DEBUG_REG2__hp_dma_data_fifo_full__SHIFT 0xf
+#define IA_DEBUG_REG2__hp_dma_req_fifo_empty_MASK 0x10000
+#define IA_DEBUG_REG2__hp_dma_req_fifo_empty__SHIFT 0x10
+#define IA_DEBUG_REG2__hp_dma_req_fifo_full_MASK 0x20000
+#define IA_DEBUG_REG2__hp_dma_req_fifo_full__SHIFT 0x11
+#define IA_DEBUG_REG2__hp_stage2_dr_MASK 0x40000
+#define IA_DEBUG_REG2__hp_stage2_dr__SHIFT 0x12
+#define IA_DEBUG_REG2__hp_stage2_rtr_MASK 0x80000
+#define IA_DEBUG_REG2__hp_stage2_rtr__SHIFT 0x13
+#define IA_DEBUG_REG2__hp_stage3_dr_MASK 0x100000
+#define IA_DEBUG_REG2__hp_stage3_dr__SHIFT 0x14
+#define IA_DEBUG_REG2__hp_stage3_rtr_MASK 0x200000
+#define IA_DEBUG_REG2__hp_stage3_rtr__SHIFT 0x15
+#define IA_DEBUG_REG2__hp_stage4_dr_MASK 0x400000
+#define IA_DEBUG_REG2__hp_stage4_dr__SHIFT 0x16
+#define IA_DEBUG_REG2__hp_stage4_rtr_MASK 0x800000
+#define IA_DEBUG_REG2__hp_stage4_rtr__SHIFT 0x17
+#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty_MASK 0x1000000
+#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty__SHIFT 0x18
+#define IA_DEBUG_REG2__hp_dma_skid_fifo_full_MASK 0x2000000
+#define IA_DEBUG_REG2__hp_dma_skid_fifo_full__SHIFT 0x19
+#define IA_DEBUG_REG2__hp_dma_grp_valid_MASK 0x4000000
+#define IA_DEBUG_REG2__hp_dma_grp_valid__SHIFT 0x1a
+#define IA_DEBUG_REG2__hp_grp_dma_read_MASK 0x8000000
+#define IA_DEBUG_REG2__hp_grp_dma_read__SHIFT 0x1b
+#define IA_DEBUG_REG2__hp_current_data_valid_MASK 0x10000000
+#define IA_DEBUG_REG2__hp_current_data_valid__SHIFT 0x1c
+#define IA_DEBUG_REG2__hp_out_of_range_r2_q_MASK 0x20000000
+#define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT 0x1d
+#define IA_DEBUG_REG2__hp_dma_mask_fifo_we_MASK 0x40000000
+#define IA_DEBUG_REG2__hp_dma_mask_fifo_we__SHIFT 0x1e
+#define IA_DEBUG_REG2__hp_dma_ret_data_we_q_MASK 0x80000000
+#define IA_DEBUG_REG2__hp_dma_ret_data_we_q__SHIFT 0x1f
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid_MASK 0x1
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid__SHIFT 0x0
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_read_MASK 0x2
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_read__SHIFT 0x1
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out_MASK 0x4
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out__SHIFT 0x2
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out_MASK 0x8
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out__SHIFT 0x3
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out_MASK 0x10
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out__SHIFT 0x4
+#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0_MASK 0x20
+#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0__SHIFT 0x5
+#define IA_DEBUG_REG3__must_service_pipe0_req_MASK 0x40
+#define IA_DEBUG_REG3__must_service_pipe0_req__SHIFT 0x6
+#define IA_DEBUG_REG3__send_pipe1_req_MASK 0x80
+#define IA_DEBUG_REG3__send_pipe1_req__SHIFT 0x7
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid_MASK 0x100
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid__SHIFT 0x8
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_read_MASK 0x200
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_read__SHIFT 0x9
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out_MASK 0x400
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out__SHIFT 0xa
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out_MASK 0x800
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out__SHIFT 0xb
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out_MASK 0x1000
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out__SHIFT 0xc
+#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q_MASK 0x2000
+#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q__SHIFT 0xd
+#define IA_DEBUG_REG3__mc_out_rtr_MASK 0x4000
+#define IA_DEBUG_REG3__mc_out_rtr__SHIFT 0xe
+#define IA_DEBUG_REG3__dma_rdreq_send_out_MASK 0x8000
+#define IA_DEBUG_REG3__dma_rdreq_send_out__SHIFT 0xf
+#define IA_DEBUG_REG3__pipe0_dr_MASK 0x10000
+#define IA_DEBUG_REG3__pipe0_dr__SHIFT 0x10
+#define IA_DEBUG_REG3__pipe0_rtr_MASK 0x20000
+#define IA_DEBUG_REG3__pipe0_rtr__SHIFT 0x11
+#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q_MASK 0x40000
+#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q__SHIFT 0x12
+#define IA_DEBUG_REG3__tc_out_rtr_MASK 0x80000
+#define IA_DEBUG_REG3__tc_out_rtr__SHIFT 0x13
+#define IA_DEBUG_REG3__pair0_valid_p1_MASK 0x100000
+#define IA_DEBUG_REG3__pair0_valid_p1__SHIFT 0x14
+#define IA_DEBUG_REG3__pair1_valid_p1_MASK 0x200000
+#define IA_DEBUG_REG3__pair1_valid_p1__SHIFT 0x15
+#define IA_DEBUG_REG3__pair2_valid_p1_MASK 0x400000
+#define IA_DEBUG_REG3__pair2_valid_p1__SHIFT 0x16
+#define IA_DEBUG_REG3__pair3_valid_p1_MASK 0x800000
+#define IA_DEBUG_REG3__pair3_valid_p1__SHIFT 0x17
+#define IA_DEBUG_REG3__tc_req_count_q_MASK 0x3000000
+#define IA_DEBUG_REG3__tc_req_count_q__SHIFT 0x18
+#define IA_DEBUG_REG3__discard_1st_chunk_MASK 0x4000000
+#define IA_DEBUG_REG3__discard_1st_chunk__SHIFT 0x1a
+#define IA_DEBUG_REG3__discard_2nd_chunk_MASK 0x8000000
+#define IA_DEBUG_REG3__discard_2nd_chunk__SHIFT 0x1b
+#define IA_DEBUG_REG3__last_tc_req_p1_MASK 0x10000000
+#define IA_DEBUG_REG3__last_tc_req_p1__SHIFT 0x1c
+#define IA_DEBUG_REG3__IA_TC_rdreq_send_out_MASK 0x20000000
+#define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT 0x1d
+#define IA_DEBUG_REG3__TC_IA_rdret_valid_in_MASK 0x40000000
+#define IA_DEBUG_REG3__TC_IA_rdret_valid_in__SHIFT 0x1e
+#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in_MASK 0x80000000
+#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in__SHIFT 0x1f
+#define IA_DEBUG_REG4__pipe0_dr_MASK 0x1
+#define IA_DEBUG_REG4__pipe0_dr__SHIFT 0x0
+#define IA_DEBUG_REG4__pipe1_dr_MASK 0x2
+#define IA_DEBUG_REG4__pipe1_dr__SHIFT 0x1
+#define IA_DEBUG_REG4__pipe2_dr_MASK 0x4
+#define IA_DEBUG_REG4__pipe2_dr__SHIFT 0x2
+#define IA_DEBUG_REG4__pipe3_dr_MASK 0x8
+#define IA_DEBUG_REG4__pipe3_dr__SHIFT 0x3
+#define IA_DEBUG_REG4__pipe4_dr_MASK 0x10
+#define IA_DEBUG_REG4__pipe4_dr__SHIFT 0x4
+#define IA_DEBUG_REG4__pipe5_dr_MASK 0x20
+#define IA_DEBUG_REG4__pipe5_dr__SHIFT 0x5
+#define IA_DEBUG_REG4__grp_se0_fifo_empty_MASK 0x40
+#define IA_DEBUG_REG4__grp_se0_fifo_empty__SHIFT 0x6
+#define IA_DEBUG_REG4__grp_se0_fifo_full_MASK 0x80
+#define IA_DEBUG_REG4__grp_se0_fifo_full__SHIFT 0x7
+#define IA_DEBUG_REG4__pipe0_rtr_MASK 0x100
+#define IA_DEBUG_REG4__pipe0_rtr__SHIFT 0x8
+#define IA_DEBUG_REG4__pipe1_rtr_MASK 0x200
+#define IA_DEBUG_REG4__pipe1_rtr__SHIFT 0x9
+#define IA_DEBUG_REG4__pipe2_rtr_MASK 0x400
+#define IA_DEBUG_REG4__pipe2_rtr__SHIFT 0xa
+#define IA_DEBUG_REG4__pipe3_rtr_MASK 0x800
+#define IA_DEBUG_REG4__pipe3_rtr__SHIFT 0xb
+#define IA_DEBUG_REG4__pipe4_rtr_MASK 0x1000
+#define IA_DEBUG_REG4__pipe4_rtr__SHIFT 0xc
+#define IA_DEBUG_REG4__pipe5_rtr_MASK 0x2000
+#define IA_DEBUG_REG4__pipe5_rtr__SHIFT 0xd
+#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q_MASK 0x4000
+#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q__SHIFT 0xe
+#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q_MASK 0x8000
+#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q__SHIFT 0xf
+#define IA_DEBUG_REG4__di_major_mode_p1_q_MASK 0x10000
+#define IA_DEBUG_REG4__di_major_mode_p1_q__SHIFT 0x10
+#define IA_DEBUG_REG4__gs_mode_p1_q_MASK 0xe0000
+#define IA_DEBUG_REG4__gs_mode_p1_q__SHIFT 0x11
+#define IA_DEBUG_REG4__di_event_flag_p1_q_MASK 0x100000
+#define IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT 0x14
+#define IA_DEBUG_REG4__di_state_sel_p1_q_MASK 0xe00000
+#define IA_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x15
+#define IA_DEBUG_REG4__draw_opaq_en_p1_q_MASK 0x1000000
+#define IA_DEBUG_REG4__draw_opaq_en_p1_q__SHIFT 0x18
+#define IA_DEBUG_REG4__draw_opaq_active_q_MASK 0x2000000
+#define IA_DEBUG_REG4__draw_opaq_active_q__SHIFT 0x19
+#define IA_DEBUG_REG4__di_source_select_p1_q_MASK 0xc000000
+#define IA_DEBUG_REG4__di_source_select_p1_q__SHIFT 0x1a
+#define IA_DEBUG_REG4__ready_to_read_di_MASK 0x10000000
+#define IA_DEBUG_REG4__ready_to_read_di__SHIFT 0x1c
+#define IA_DEBUG_REG4__di_first_group_of_draw_q_MASK 0x20000000
+#define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT 0x1d
+#define IA_DEBUG_REG4__last_shift_of_draw_MASK 0x40000000
+#define IA_DEBUG_REG4__last_shift_of_draw__SHIFT 0x1e
+#define IA_DEBUG_REG4__current_shift_is_vect1_q_MASK 0x80000000
+#define IA_DEBUG_REG4__current_shift_is_vect1_q__SHIFT 0x1f
+#define IA_DEBUG_REG5__di_index_counter_q_15_0_MASK 0xffff
+#define IA_DEBUG_REG5__di_index_counter_q_15_0__SHIFT 0x0
+#define IA_DEBUG_REG5__instanceid_13_0_MASK 0x3fff0000
+#define IA_DEBUG_REG5__instanceid_13_0__SHIFT 0x10
+#define IA_DEBUG_REG5__draw_input_fifo_full_MASK 0x40000000
+#define IA_DEBUG_REG5__draw_input_fifo_full__SHIFT 0x1e
+#define IA_DEBUG_REG5__draw_input_fifo_empty_MASK 0x80000000
+#define IA_DEBUG_REG5__draw_input_fifo_empty__SHIFT 0x1f
+#define IA_DEBUG_REG6__current_shift_q_MASK 0xf
+#define IA_DEBUG_REG6__current_shift_q__SHIFT 0x0
+#define IA_DEBUG_REG6__current_stride_pre_MASK 0xf0
+#define IA_DEBUG_REG6__current_stride_pre__SHIFT 0x4
+#define IA_DEBUG_REG6__current_stride_q_MASK 0x1f00
+#define IA_DEBUG_REG6__current_stride_q__SHIFT 0x8
+#define IA_DEBUG_REG6__first_group_partial_MASK 0x2000
+#define IA_DEBUG_REG6__first_group_partial__SHIFT 0xd
+#define IA_DEBUG_REG6__second_group_partial_MASK 0x4000
+#define IA_DEBUG_REG6__second_group_partial__SHIFT 0xe
+#define IA_DEBUG_REG6__curr_prim_partial_MASK 0x8000
+#define IA_DEBUG_REG6__curr_prim_partial__SHIFT 0xf
+#define IA_DEBUG_REG6__next_stride_q_MASK 0x1f0000
+#define IA_DEBUG_REG6__next_stride_q__SHIFT 0x10
+#define IA_DEBUG_REG6__next_group_partial_MASK 0x200000
+#define IA_DEBUG_REG6__next_group_partial__SHIFT 0x15
+#define IA_DEBUG_REG6__after_group_partial_MASK 0x400000
+#define IA_DEBUG_REG6__after_group_partial__SHIFT 0x16
+#define IA_DEBUG_REG6__extract_group_MASK 0x800000
+#define IA_DEBUG_REG6__extract_group__SHIFT 0x17
+#define IA_DEBUG_REG6__grp_shift_debug_data_MASK 0xff000000
+#define IA_DEBUG_REG6__grp_shift_debug_data__SHIFT 0x18
+#define IA_DEBUG_REG7__reset_indx_state_q_MASK 0xf
+#define IA_DEBUG_REG7__reset_indx_state_q__SHIFT 0x0
+#define IA_DEBUG_REG7__shift_vect_valid_p2_q_MASK 0xf0
+#define IA_DEBUG_REG7__shift_vect_valid_p2_q__SHIFT 0x4
+#define IA_DEBUG_REG7__shift_vect1_valid_p2_q_MASK 0xf00
+#define IA_DEBUG_REG7__shift_vect1_valid_p2_q__SHIFT 0x8
+#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q_MASK 0xf000
+#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q__SHIFT 0xc
+#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q_MASK 0xf0000
+#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q__SHIFT 0x10
+#define IA_DEBUG_REG7__num_indx_in_group_p2_q_MASK 0x700000
+#define IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT 0x14
+#define IA_DEBUG_REG7__last_group_of_draw_p2_q_MASK 0x800000
+#define IA_DEBUG_REG7__last_group_of_draw_p2_q__SHIFT 0x17
+#define IA_DEBUG_REG7__shift_event_flag_p2_q_MASK 0x1000000
+#define IA_DEBUG_REG7__shift_event_flag_p2_q__SHIFT 0x18
+#define IA_DEBUG_REG7__indx_shift_is_one_p2_q_MASK 0x2000000
+#define IA_DEBUG_REG7__indx_shift_is_one_p2_q__SHIFT 0x19
+#define IA_DEBUG_REG7__indx_shift_is_two_p2_q_MASK 0x4000000
+#define IA_DEBUG_REG7__indx_shift_is_two_p2_q__SHIFT 0x1a
+#define IA_DEBUG_REG7__indx_stride_is_four_p2_q_MASK 0x8000000
+#define IA_DEBUG_REG7__indx_stride_is_four_p2_q__SHIFT 0x1b
+#define IA_DEBUG_REG7__shift_prim1_reset_p3_q_MASK 0x10000000
+#define IA_DEBUG_REG7__shift_prim1_reset_p3_q__SHIFT 0x1c
+#define IA_DEBUG_REG7__shift_prim1_partial_p3_q_MASK 0x20000000
+#define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x1d
+#define IA_DEBUG_REG7__shift_prim0_reset_p3_q_MASK 0x40000000
+#define IA_DEBUG_REG7__shift_prim0_reset_p3_q__SHIFT 0x1e
+#define IA_DEBUG_REG7__shift_prim0_partial_p3_q_MASK 0x80000000
+#define IA_DEBUG_REG7__shift_prim0_partial_p3_q__SHIFT 0x1f
+#define IA_DEBUG_REG8__di_prim_type_p1_q_MASK 0x1f
+#define IA_DEBUG_REG8__di_prim_type_p1_q__SHIFT 0x0
+#define IA_DEBUG_REG8__two_cycle_xfer_p1_q_MASK 0x20
+#define IA_DEBUG_REG8__two_cycle_xfer_p1_q__SHIFT 0x5
+#define IA_DEBUG_REG8__two_prim_input_p1_q_MASK 0x40
+#define IA_DEBUG_REG8__two_prim_input_p1_q__SHIFT 0x6
+#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q_MASK 0x80
+#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q__SHIFT 0x7
+#define IA_DEBUG_REG8__last_group_of_inst_p5_q_MASK 0x100
+#define IA_DEBUG_REG8__last_group_of_inst_p5_q__SHIFT 0x8
+#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q_MASK 0x200
+#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q__SHIFT 0x9
+#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q_MASK 0x400
+#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q__SHIFT 0xa
+#define IA_DEBUG_REG8__grp_continued_MASK 0x800
+#define IA_DEBUG_REG8__grp_continued__SHIFT 0xb
+#define IA_DEBUG_REG8__grp_state_sel_MASK 0x7000
+#define IA_DEBUG_REG8__grp_state_sel__SHIFT 0xc
+#define IA_DEBUG_REG8__grp_sub_prim_type_MASK 0x1f8000
+#define IA_DEBUG_REG8__grp_sub_prim_type__SHIFT 0xf
+#define IA_DEBUG_REG8__grp_output_path_MASK 0xe00000
+#define IA_DEBUG_REG8__grp_output_path__SHIFT 0x15
+#define IA_DEBUG_REG8__grp_null_primitive_MASK 0x1000000
+#define IA_DEBUG_REG8__grp_null_primitive__SHIFT 0x18
+#define IA_DEBUG_REG8__grp_eop_MASK 0x2000000
+#define IA_DEBUG_REG8__grp_eop__SHIFT 0x19
+#define IA_DEBUG_REG8__grp_eopg_MASK 0x4000000
+#define IA_DEBUG_REG8__grp_eopg__SHIFT 0x1a
+#define IA_DEBUG_REG8__grp_event_flag_MASK 0x8000000
+#define IA_DEBUG_REG8__grp_event_flag__SHIFT 0x1b
+#define IA_DEBUG_REG8__grp_components_valid_MASK 0xf0000000
+#define IA_DEBUG_REG8__grp_components_valid__SHIFT 0x1c
+#define IA_DEBUG_REG9__send_to_se1_p6_MASK 0x1
+#define IA_DEBUG_REG9__send_to_se1_p6__SHIFT 0x0
+#define IA_DEBUG_REG9__gfx_se_switch_p6_MASK 0x2
+#define IA_DEBUG_REG9__gfx_se_switch_p6__SHIFT 0x1
+#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6_MASK 0x4
+#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6__SHIFT 0x2
+#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6_MASK 0x8
+#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6__SHIFT 0x3
+#define IA_DEBUG_REG9__prim1_eoi_p6_MASK 0x10
+#define IA_DEBUG_REG9__prim1_eoi_p6__SHIFT 0x4
+#define IA_DEBUG_REG9__prim0_eoi_p6_MASK 0x20
+#define IA_DEBUG_REG9__prim0_eoi_p6__SHIFT 0x5
+#define IA_DEBUG_REG9__prim1_valid_eopg_p6_MASK 0x40
+#define IA_DEBUG_REG9__prim1_valid_eopg_p6__SHIFT 0x6
+#define IA_DEBUG_REG9__prim0_valid_eopg_p6_MASK 0x80
+#define IA_DEBUG_REG9__prim0_valid_eopg_p6__SHIFT 0x7
+#define IA_DEBUG_REG9__prim1_to_other_se_p6_MASK 0x100
+#define IA_DEBUG_REG9__prim1_to_other_se_p6__SHIFT 0x8
+#define IA_DEBUG_REG9__eopg_on_last_prim_p6_MASK 0x200
+#define IA_DEBUG_REG9__eopg_on_last_prim_p6__SHIFT 0x9
+#define IA_DEBUG_REG9__eopg_between_prims_p6_MASK 0x400
+#define IA_DEBUG_REG9__eopg_between_prims_p6__SHIFT 0xa
+#define IA_DEBUG_REG9__prim_count_eq_group_size_p6_MASK 0x800
+#define IA_DEBUG_REG9__prim_count_eq_group_size_p6__SHIFT 0xb
+#define IA_DEBUG_REG9__prim_count_gt_group_size_p6_MASK 0x1000
+#define IA_DEBUG_REG9__prim_count_gt_group_size_p6__SHIFT 0xc
+#define IA_DEBUG_REG9__two_prim_output_p5_q_MASK 0x2000
+#define IA_DEBUG_REG9__two_prim_output_p5_q__SHIFT 0xd
+#define IA_DEBUG_REG9__SPARE0_MASK 0x4000
+#define IA_DEBUG_REG9__SPARE0__SHIFT 0xe
+#define IA_DEBUG_REG9__SPARE1_MASK 0x8000
+#define IA_DEBUG_REG9__SPARE1__SHIFT 0xf
+#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q_MASK 0x10000
+#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q__SHIFT 0x10
+#define IA_DEBUG_REG9__prim1_xfer_p6_MASK 0x20000
+#define IA_DEBUG_REG9__prim1_xfer_p6__SHIFT 0x11
+#define IA_DEBUG_REG9__grp_se1_fifo_empty_MASK 0x40000
+#define IA_DEBUG_REG9__grp_se1_fifo_empty__SHIFT 0x12
+#define IA_DEBUG_REG9__grp_se1_fifo_full_MASK 0x80000
+#define IA_DEBUG_REG9__grp_se1_fifo_full__SHIFT 0x13
+#define IA_DEBUG_REG9__prim_counter_q_MASK 0xfff00000
+#define IA_DEBUG_REG9__prim_counter_q__SHIFT 0x14
+#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x1
+#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0
+#define VGT_DEBUG_REG0__SPARE9_MASK 0x2
+#define VGT_DEBUG_REG0__SPARE9__SHIFT 0x1
+#define VGT_DEBUG_REG0__vgt_busy_MASK 0x4
+#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x2
+#define VGT_DEBUG_REG0__SPARE8_MASK 0x8
+#define VGT_DEBUG_REG0__SPARE8__SHIFT 0x3
+#define VGT_DEBUG_REG0__SPARE7_MASK 0x10
+#define VGT_DEBUG_REG0__SPARE7__SHIFT 0x4
+#define VGT_DEBUG_REG0__SPARE6_MASK 0x20
+#define VGT_DEBUG_REG0__SPARE6__SHIFT 0x5
+#define VGT_DEBUG_REG0__SPARE5_MASK 0x40
+#define VGT_DEBUG_REG0__SPARE5__SHIFT 0x6
+#define VGT_DEBUG_REG0__SPARE4_MASK 0x80
+#define VGT_DEBUG_REG0__SPARE4__SHIFT 0x7
+#define VGT_DEBUG_REG0__pi_busy_MASK 0x100
+#define VGT_DEBUG_REG0__pi_busy__SHIFT 0x8
+#define VGT_DEBUG_REG0__vr_pi_busy_MASK 0x200
+#define VGT_DEBUG_REG0__vr_pi_busy__SHIFT 0x9
+#define VGT_DEBUG_REG0__pt_pi_busy_MASK 0x400
+#define VGT_DEBUG_REG0__pt_pi_busy__SHIFT 0xa
+#define VGT_DEBUG_REG0__te_pi_busy_MASK 0x800
+#define VGT_DEBUG_REG0__te_pi_busy__SHIFT 0xb
+#define VGT_DEBUG_REG0__gs_busy_MASK 0x1000
+#define VGT_DEBUG_REG0__gs_busy__SHIFT 0xc
+#define VGT_DEBUG_REG0__rcm_busy_MASK 0x2000
+#define VGT_DEBUG_REG0__rcm_busy__SHIFT 0xd
+#define VGT_DEBUG_REG0__tm_busy_MASK 0x4000
+#define VGT_DEBUG_REG0__tm_busy__SHIFT 0xe
+#define VGT_DEBUG_REG0__cm_busy_MASK 0x8000
+#define VGT_DEBUG_REG0__cm_busy__SHIFT 0xf
+#define VGT_DEBUG_REG0__gog_busy_MASK 0x10000
+#define VGT_DEBUG_REG0__gog_busy__SHIFT 0x10
+#define VGT_DEBUG_REG0__frmt_busy_MASK 0x20000
+#define VGT_DEBUG_REG0__frmt_busy__SHIFT 0x11
+#define VGT_DEBUG_REG0__SPARE10_MASK 0x40000
+#define VGT_DEBUG_REG0__SPARE10__SHIFT 0x12
+#define VGT_DEBUG_REG0__te11_pi_busy_MASK 0x80000
+#define VGT_DEBUG_REG0__te11_pi_busy__SHIFT 0x13
+#define VGT_DEBUG_REG0__SPARE3_MASK 0x100000
+#define VGT_DEBUG_REG0__SPARE3__SHIFT 0x14
+#define VGT_DEBUG_REG0__combined_out_busy_MASK 0x200000
+#define VGT_DEBUG_REG0__combined_out_busy__SHIFT 0x15
+#define VGT_DEBUG_REG0__spi_vs_interfaces_busy_MASK 0x400000
+#define VGT_DEBUG_REG0__spi_vs_interfaces_busy__SHIFT 0x16
+#define VGT_DEBUG_REG0__pa_interfaces_busy_MASK 0x800000
+#define VGT_DEBUG_REG0__pa_interfaces_busy__SHIFT 0x17
+#define VGT_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
+#define VGT_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
+#define VGT_DEBUG_REG0__SPARE2_MASK 0x2000000
+#define VGT_DEBUG_REG0__SPARE2__SHIFT 0x19
+#define VGT_DEBUG_REG0__core_clk_busy_MASK 0x4000000
+#define VGT_DEBUG_REG0__core_clk_busy__SHIFT 0x1a
+#define VGT_DEBUG_REG0__gs_clk_busy_MASK 0x8000000
+#define VGT_DEBUG_REG0__gs_clk_busy__SHIFT 0x1b
+#define VGT_DEBUG_REG0__SPARE1_MASK 0x10000000
+#define VGT_DEBUG_REG0__SPARE1__SHIFT 0x1c
+#define VGT_DEBUG_REG0__sclk_core_vld_MASK 0x20000000
+#define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d
+#define VGT_DEBUG_REG0__sclk_gs_vld_MASK 0x40000000
+#define VGT_DEBUG_REG0__sclk_gs_vld__SHIFT 0x1e
+#define VGT_DEBUG_REG0__SPARE0_MASK 0x80000000
+#define VGT_DEBUG_REG0__SPARE0__SHIFT 0x1f
+#define VGT_DEBUG_REG1__SPARE9_MASK 0x1
+#define VGT_DEBUG_REG1__SPARE9__SHIFT 0x0
+#define VGT_DEBUG_REG1__SPARE8_MASK 0x2
+#define VGT_DEBUG_REG1__SPARE8__SHIFT 0x1
+#define VGT_DEBUG_REG1__SPARE7_MASK 0x4
+#define VGT_DEBUG_REG1__SPARE7__SHIFT 0x2
+#define VGT_DEBUG_REG1__SPARE6_MASK 0x8
+#define VGT_DEBUG_REG1__SPARE6__SHIFT 0x3
+#define VGT_DEBUG_REG1__SPARE5_MASK 0x10
+#define VGT_DEBUG_REG1__SPARE5__SHIFT 0x4
+#define VGT_DEBUG_REG1__SPARE4_MASK 0x20
+#define VGT_DEBUG_REG1__SPARE4__SHIFT 0x5
+#define VGT_DEBUG_REG1__SPARE3_MASK 0x40
+#define VGT_DEBUG_REG1__SPARE3__SHIFT 0x6
+#define VGT_DEBUG_REG1__SPARE2_MASK 0x80
+#define VGT_DEBUG_REG1__SPARE2__SHIFT 0x7
+#define VGT_DEBUG_REG1__SPARE1_MASK 0x100
+#define VGT_DEBUG_REG1__SPARE1__SHIFT 0x8
+#define VGT_DEBUG_REG1__SPARE0_MASK 0x200
+#define VGT_DEBUG_REG1__SPARE0__SHIFT 0x9
+#define VGT_DEBUG_REG1__pi_vr_valid_MASK 0x400
+#define VGT_DEBUG_REG1__pi_vr_valid__SHIFT 0xa
+#define VGT_DEBUG_REG1__vr_pi_read_MASK 0x800
+#define VGT_DEBUG_REG1__vr_pi_read__SHIFT 0xb
+#define VGT_DEBUG_REG1__pi_pt_valid_MASK 0x1000
+#define VGT_DEBUG_REG1__pi_pt_valid__SHIFT 0xc
+#define VGT_DEBUG_REG1__pt_pi_read_MASK 0x2000
+#define VGT_DEBUG_REG1__pt_pi_read__SHIFT 0xd
+#define VGT_DEBUG_REG1__pi_te_valid_MASK 0x4000
+#define VGT_DEBUG_REG1__pi_te_valid__SHIFT 0xe
+#define VGT_DEBUG_REG1__te_grp_read_MASK 0x8000
+#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0xf
+#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x10000
+#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x10
+#define VGT_DEBUG_REG1__SPARE12_MASK 0x20000
+#define VGT_DEBUG_REG1__SPARE12__SHIFT 0x11
+#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x40000
+#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x12
+#define VGT_DEBUG_REG1__SPARE11_MASK 0x80000
+#define VGT_DEBUG_REG1__SPARE11__SHIFT 0x13
+#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x100000
+#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x14
+#define VGT_DEBUG_REG1__SPARE10_MASK 0x200000
+#define VGT_DEBUG_REG1__SPARE10__SHIFT 0x15
+#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x400000
+#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x16
+#define VGT_DEBUG_REG1__SPARE23_MASK 0x800000
+#define VGT_DEBUG_REG1__SPARE23__SHIFT 0x17
+#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x1000000
+#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x18
+#define VGT_DEBUG_REG1__SPARE25_MASK 0x2000000
+#define VGT_DEBUG_REG1__SPARE25__SHIFT 0x19
+#define VGT_DEBUG_REG1__pi_gs_valid_MASK 0x4000000
+#define VGT_DEBUG_REG1__pi_gs_valid__SHIFT 0x1a
+#define VGT_DEBUG_REG1__gs_pi_read_MASK 0x8000000
+#define VGT_DEBUG_REG1__gs_pi_read__SHIFT 0x1b
+#define VGT_DEBUG_REG1__gog_out_indx_valid_MASK 0x10000000
+#define VGT_DEBUG_REG1__gog_out_indx_valid__SHIFT 0x1c
+#define VGT_DEBUG_REG1__out_indx_read_MASK 0x20000000
+#define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x1d
+#define VGT_DEBUG_REG1__gog_out_prim_valid_MASK 0x40000000
+#define VGT_DEBUG_REG1__gog_out_prim_valid__SHIFT 0x1e
+#define VGT_DEBUG_REG1__out_prim_read_MASK 0x80000000
+#define VGT_DEBUG_REG1__out_prim_read__SHIFT 0x1f
+#define VGT_DEBUG_REG2__hs_grp_busy_MASK 0x1
+#define VGT_DEBUG_REG2__hs_grp_busy__SHIFT 0x0
+#define VGT_DEBUG_REG2__hs_noif_busy_MASK 0x2
+#define VGT_DEBUG_REG2__hs_noif_busy__SHIFT 0x1
+#define VGT_DEBUG_REG2__tfmmIsBusy_MASK 0x4
+#define VGT_DEBUG_REG2__tfmmIsBusy__SHIFT 0x2
+#define VGT_DEBUG_REG2__lsVertIfBusy_0_MASK 0x8
+#define VGT_DEBUG_REG2__lsVertIfBusy_0__SHIFT 0x3
+#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr_MASK 0x10
+#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr__SHIFT 0x4
+#define VGT_DEBUG_REG2__lsWaveIfBusy_0_MASK 0x20
+#define VGT_DEBUG_REG2__lsWaveIfBusy_0__SHIFT 0x5
+#define VGT_DEBUG_REG2__hs_te11_tess_input_rts_MASK 0x40
+#define VGT_DEBUG_REG2__hs_te11_tess_input_rts__SHIFT 0x6
+#define VGT_DEBUG_REG2__grpModBusy_MASK 0x80
+#define VGT_DEBUG_REG2__grpModBusy__SHIFT 0x7
+#define VGT_DEBUG_REG2__lsVertFifoEmpty_MASK 0x100
+#define VGT_DEBUG_REG2__lsVertFifoEmpty__SHIFT 0x8
+#define VGT_DEBUG_REG2__lsWaveFifoEmpty_MASK 0x200
+#define VGT_DEBUG_REG2__lsWaveFifoEmpty__SHIFT 0x9
+#define VGT_DEBUG_REG2__hsVertFifoEmpty_MASK 0x400
+#define VGT_DEBUG_REG2__hsVertFifoEmpty__SHIFT 0xa
+#define VGT_DEBUG_REG2__hsWaveFifoEmpty_MASK 0x800
+#define VGT_DEBUG_REG2__hsWaveFifoEmpty__SHIFT 0xb
+#define VGT_DEBUG_REG2__hsInputFifoEmpty_MASK 0x1000
+#define VGT_DEBUG_REG2__hsInputFifoEmpty__SHIFT 0xc
+#define VGT_DEBUG_REG2__hsTifFifoEmpty_MASK 0x2000
+#define VGT_DEBUG_REG2__hsTifFifoEmpty__SHIFT 0xd
+#define VGT_DEBUG_REG2__lsVertFifoFull_MASK 0x4000
+#define VGT_DEBUG_REG2__lsVertFifoFull__SHIFT 0xe
+#define VGT_DEBUG_REG2__lsWaveFifoFull_MASK 0x8000
+#define VGT_DEBUG_REG2__lsWaveFifoFull__SHIFT 0xf
+#define VGT_DEBUG_REG2__hsVertFifoFull_MASK 0x10000
+#define VGT_DEBUG_REG2__hsVertFifoFull__SHIFT 0x10
+#define VGT_DEBUG_REG2__hsWaveFifoFull_MASK 0x20000
+#define VGT_DEBUG_REG2__hsWaveFifoFull__SHIFT 0x11
+#define VGT_DEBUG_REG2__hsInputFifoFull_MASK 0x40000
+#define VGT_DEBUG_REG2__hsInputFifoFull__SHIFT 0x12
+#define VGT_DEBUG_REG2__hsTifFifoFull_MASK 0x80000
+#define VGT_DEBUG_REG2__hsTifFifoFull__SHIFT 0x13
+#define VGT_DEBUG_REG2__p0_rtr_MASK 0x100000
+#define VGT_DEBUG_REG2__p0_rtr__SHIFT 0x14
+#define VGT_DEBUG_REG2__p1_rtr_MASK 0x200000
+#define VGT_DEBUG_REG2__p1_rtr__SHIFT 0x15
+#define VGT_DEBUG_REG2__p0_dr_MASK 0x400000
+#define VGT_DEBUG_REG2__p0_dr__SHIFT 0x16
+#define VGT_DEBUG_REG2__p1_dr_MASK 0x800000
+#define VGT_DEBUG_REG2__p1_dr__SHIFT 0x17
+#define VGT_DEBUG_REG2__p0_rts_MASK 0x1000000
+#define VGT_DEBUG_REG2__p0_rts__SHIFT 0x18
+#define VGT_DEBUG_REG2__p1_rts_MASK 0x2000000
+#define VGT_DEBUG_REG2__p1_rts__SHIFT 0x19
+#define VGT_DEBUG_REG2__ls_sh_id_MASK 0x4000000
+#define VGT_DEBUG_REG2__ls_sh_id__SHIFT 0x1a
+#define VGT_DEBUG_REG2__lsFwaveFlag_MASK 0x8000000
+#define VGT_DEBUG_REG2__lsFwaveFlag__SHIFT 0x1b
+#define VGT_DEBUG_REG2__lsWaveSendFlush_MASK 0x10000000
+#define VGT_DEBUG_REG2__lsWaveSendFlush__SHIFT 0x1c
+#define VGT_DEBUG_REG2__SPARE_MASK 0xe0000000
+#define VGT_DEBUG_REG2__SPARE__SHIFT 0x1d
+#define VGT_DEBUG_REG3__lsTgRelInd_MASK 0xfff
+#define VGT_DEBUG_REG3__lsTgRelInd__SHIFT 0x0
+#define VGT_DEBUG_REG3__lsWaveRelInd_MASK 0x3f000
+#define VGT_DEBUG_REG3__lsWaveRelInd__SHIFT 0xc
+#define VGT_DEBUG_REG3__lsPatchCnt_MASK 0x3fc0000
+#define VGT_DEBUG_REG3__lsPatchCnt__SHIFT 0x12
+#define VGT_DEBUG_REG3__hsWaveRelInd_MASK 0xfc000000
+#define VGT_DEBUG_REG3__hsWaveRelInd__SHIFT 0x1a
+#define VGT_DEBUG_REG4__hsPatchCnt_MASK 0xff
+#define VGT_DEBUG_REG4__hsPatchCnt__SHIFT 0x0
+#define VGT_DEBUG_REG4__hsPrimId_15_0_MASK 0xffff00
+#define VGT_DEBUG_REG4__hsPrimId_15_0__SHIFT 0x8
+#define VGT_DEBUG_REG4__hsCpCnt_MASK 0x1f000000
+#define VGT_DEBUG_REG4__hsCpCnt__SHIFT 0x18
+#define VGT_DEBUG_REG4__hsWaveSendFlush_MASK 0x20000000
+#define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT 0x1d
+#define VGT_DEBUG_REG4__hsFwaveFlag_MASK 0x40000000
+#define VGT_DEBUG_REG4__hsFwaveFlag__SHIFT 0x1e
+#define VGT_DEBUG_REG4__SPARE_MASK 0x80000000
+#define VGT_DEBUG_REG4__SPARE__SHIFT 0x1f
+#define VGT_DEBUG_REG5__SPARE4_MASK 0x7
+#define VGT_DEBUG_REG5__SPARE4__SHIFT 0x0
+#define VGT_DEBUG_REG5__hsWaveCreditCnt_0_MASK 0xf8
+#define VGT_DEBUG_REG5__hsWaveCreditCnt_0__SHIFT 0x3
+#define VGT_DEBUG_REG5__SPARE3_MASK 0x700
+#define VGT_DEBUG_REG5__SPARE3__SHIFT 0x8
+#define VGT_DEBUG_REG5__hsVertCreditCnt_0_MASK 0xf800
+#define VGT_DEBUG_REG5__hsVertCreditCnt_0__SHIFT 0xb
+#define VGT_DEBUG_REG5__SPARE2_MASK 0x70000
+#define VGT_DEBUG_REG5__SPARE2__SHIFT 0x10
+#define VGT_DEBUG_REG5__lsWaveCreditCnt_0_MASK 0xf80000
+#define VGT_DEBUG_REG5__lsWaveCreditCnt_0__SHIFT 0x13
+#define VGT_DEBUG_REG5__SPARE1_MASK 0x7000000
+#define VGT_DEBUG_REG5__SPARE1__SHIFT 0x18
+#define VGT_DEBUG_REG5__lsVertCreditCnt_0_MASK 0xf8000000
+#define VGT_DEBUG_REG5__lsVertCreditCnt_0__SHIFT 0x1b
+#define VGT_DEBUG_REG6__debug_BASE_MASK 0xffff
+#define VGT_DEBUG_REG6__debug_BASE__SHIFT 0x0
+#define VGT_DEBUG_REG6__debug_SIZE_MASK 0xffff0000
+#define VGT_DEBUG_REG6__debug_SIZE__SHIFT 0x10
+#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty_MASK 0x1
+#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty__SHIFT 0x0
+#define VGT_DEBUG_REG7__debug_tfmmFifoFull_MASK 0x2
+#define VGT_DEBUG_REG7__debug_tfmmFifoFull__SHIFT 0x1
+#define VGT_DEBUG_REG7__hs_pipe0_dr_MASK 0x4
+#define VGT_DEBUG_REG7__hs_pipe0_dr__SHIFT 0x2
+#define VGT_DEBUG_REG7__hs_pipe0_rtr_MASK 0x8
+#define VGT_DEBUG_REG7__hs_pipe0_rtr__SHIFT 0x3
+#define VGT_DEBUG_REG7__hs_pipe1_rtr_MASK 0x10
+#define VGT_DEBUG_REG7__hs_pipe1_rtr__SHIFT 0x4
+#define VGT_DEBUG_REG7__SPARE_MASK 0xffe0
+#define VGT_DEBUG_REG7__SPARE__SHIFT 0x5
+#define VGT_DEBUG_REG7__TF_addr_MASK 0xffff0000
+#define VGT_DEBUG_REG7__TF_addr__SHIFT 0x10
+#define VGT_DEBUG_REG8__rcm_busy_q_MASK 0x1
+#define VGT_DEBUG_REG8__rcm_busy_q__SHIFT 0x0
+#define VGT_DEBUG_REG8__rcm_noif_busy_q_MASK 0x2
+#define VGT_DEBUG_REG8__rcm_noif_busy_q__SHIFT 0x1
+#define VGT_DEBUG_REG8__r1_inst_rtr_MASK 0x4
+#define VGT_DEBUG_REG8__r1_inst_rtr__SHIFT 0x2
+#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q_MASK 0x8
+#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q__SHIFT 0x3
+#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q_MASK 0x10
+#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q__SHIFT 0x4
+#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q_MASK 0x20
+#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q__SHIFT 0x5
+#define VGT_DEBUG_REG8__valid_r0_q_MASK 0x40
+#define VGT_DEBUG_REG8__valid_r0_q__SHIFT 0x6
+#define VGT_DEBUG_REG8__valid_r1_q_MASK 0x80
+#define VGT_DEBUG_REG8__valid_r1_q__SHIFT 0x7
+#define VGT_DEBUG_REG8__valid_r2_MASK 0x100
+#define VGT_DEBUG_REG8__valid_r2__SHIFT 0x8
+#define VGT_DEBUG_REG8__valid_r2_q_MASK 0x200
+#define VGT_DEBUG_REG8__valid_r2_q__SHIFT 0x9
+#define VGT_DEBUG_REG8__r0_rtr_MASK 0x400
+#define VGT_DEBUG_REG8__r0_rtr__SHIFT 0xa
+#define VGT_DEBUG_REG8__r1_rtr_MASK 0x800
+#define VGT_DEBUG_REG8__r1_rtr__SHIFT 0xb
+#define VGT_DEBUG_REG8__r2_indx_rtr_MASK 0x1000
+#define VGT_DEBUG_REG8__r2_indx_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG8__r2_rtr_MASK 0x2000
+#define VGT_DEBUG_REG8__r2_rtr__SHIFT 0xd
+#define VGT_DEBUG_REG8__es_gs_rtr_MASK 0x4000
+#define VGT_DEBUG_REG8__es_gs_rtr__SHIFT 0xe
+#define VGT_DEBUG_REG8__gs_event_fifo_rtr_MASK 0x8000
+#define VGT_DEBUG_REG8__gs_event_fifo_rtr__SHIFT 0xf
+#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr_MASK 0x10000
+#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr__SHIFT 0x10
+#define VGT_DEBUG_REG8__gs_tbl_r3_rtr_MASK 0x20000
+#define VGT_DEBUG_REG8__gs_tbl_r3_rtr__SHIFT 0x11
+#define VGT_DEBUG_REG8__prim_skid_fifo_empty_MASK 0x40000
+#define VGT_DEBUG_REG8__prim_skid_fifo_empty__SHIFT 0x12
+#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q_MASK 0x80000
+#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q__SHIFT 0x13
+#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr_MASK 0x100000
+#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT 0x14
+#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr_MASK 0x200000
+#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr__SHIFT 0x15
+#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q_MASK 0x400000
+#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q__SHIFT 0x16
+#define VGT_DEBUG_REG8__r2_no_bp_rtr_MASK 0x800000
+#define VGT_DEBUG_REG8__r2_no_bp_rtr__SHIFT 0x17
+#define VGT_DEBUG_REG8__hold_for_es_flush_MASK 0x1000000
+#define VGT_DEBUG_REG8__hold_for_es_flush__SHIFT 0x18
+#define VGT_DEBUG_REG8__gs_event_fifo_empty_MASK 0x2000000
+#define VGT_DEBUG_REG8__gs_event_fifo_empty__SHIFT 0x19
+#define VGT_DEBUG_REG8__gsprim_buff_empty_q_MASK 0x4000000
+#define VGT_DEBUG_REG8__gsprim_buff_empty_q__SHIFT 0x1a
+#define VGT_DEBUG_REG8__gsprim_buff_full_q_MASK 0x8000000
+#define VGT_DEBUG_REG8__gsprim_buff_full_q__SHIFT 0x1b
+#define VGT_DEBUG_REG8__te_prim_fifo_empty_MASK 0x10000000
+#define VGT_DEBUG_REG8__te_prim_fifo_empty__SHIFT 0x1c
+#define VGT_DEBUG_REG8__te_prim_fifo_full_MASK 0x20000000
+#define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x1d
+#define VGT_DEBUG_REG8__te_vert_fifo_empty_MASK 0x40000000
+#define VGT_DEBUG_REG8__te_vert_fifo_empty__SHIFT 0x1e
+#define VGT_DEBUG_REG8__te_vert_fifo_full_MASK 0x80000000
+#define VGT_DEBUG_REG8__te_vert_fifo_full__SHIFT 0x1f
+#define VGT_DEBUG_REG9__indices_to_send_r2_q_MASK 0x3
+#define VGT_DEBUG_REG9__indices_to_send_r2_q__SHIFT 0x0
+#define VGT_DEBUG_REG9__valid_indices_r3_MASK 0x4
+#define VGT_DEBUG_REG9__valid_indices_r3__SHIFT 0x2
+#define VGT_DEBUG_REG9__gs_eov_r3_MASK 0x8
+#define VGT_DEBUG_REG9__gs_eov_r3__SHIFT 0x3
+#define VGT_DEBUG_REG9__eop_indx_r3_MASK 0x10
+#define VGT_DEBUG_REG9__eop_indx_r3__SHIFT 0x4
+#define VGT_DEBUG_REG9__eop_prim_r3_MASK 0x20
+#define VGT_DEBUG_REG9__eop_prim_r3__SHIFT 0x5
+#define VGT_DEBUG_REG9__es_eov_r3_MASK 0x40
+#define VGT_DEBUG_REG9__es_eov_r3__SHIFT 0x6
+#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0_MASK 0x80
+#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0__SHIFT 0x7
+#define VGT_DEBUG_REG9__pending_es_send_r3_q_MASK 0x100
+#define VGT_DEBUG_REG9__pending_es_send_r3_q__SHIFT 0x8
+#define VGT_DEBUG_REG9__pending_es_flush_r3_MASK 0x200
+#define VGT_DEBUG_REG9__pending_es_flush_r3__SHIFT 0x9
+#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0_MASK 0x400
+#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT 0xa
+#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q_MASK 0x3f800
+#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q__SHIFT 0xb
+#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q_MASK 0x40000
+#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q__SHIFT 0x12
+#define VGT_DEBUG_REG9__gs_tbl_state_r3_q_MASK 0x380000
+#define VGT_DEBUG_REG9__gs_tbl_state_r3_q__SHIFT 0x13
+#define VGT_DEBUG_REG9__gs_pending_state_r3_q_MASK 0x400000
+#define VGT_DEBUG_REG9__gs_pending_state_r3_q__SHIFT 0x16
+#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q_MASK 0x800000
+#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q__SHIFT 0x17
+#define VGT_DEBUG_REG9__gs_instancing_state_q_MASK 0x1000000
+#define VGT_DEBUG_REG9__gs_instancing_state_q__SHIFT 0x18
+#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0_MASK 0x2000000
+#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0__SHIFT 0x19
+#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0_MASK 0x4000000
+#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0__SHIFT 0x1a
+#define VGT_DEBUG_REG9__pre_r0_rtr_MASK 0x8000000
+#define VGT_DEBUG_REG9__pre_r0_rtr__SHIFT 0x1b
+#define VGT_DEBUG_REG9__valid_r3_q_MASK 0x10000000
+#define VGT_DEBUG_REG9__valid_r3_q__SHIFT 0x1c
+#define VGT_DEBUG_REG9__valid_pre_r0_q_MASK 0x20000000
+#define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x1d
+#define VGT_DEBUG_REG9__SPARE0_MASK 0x40000000
+#define VGT_DEBUG_REG9__SPARE0__SHIFT 0x1e
+#define VGT_DEBUG_REG9__off_chip_hs_r2_q_MASK 0x80000000
+#define VGT_DEBUG_REG9__off_chip_hs_r2_q__SHIFT 0x1f
+#define VGT_DEBUG_REG10__index_buffer_depth_r1_q_MASK 0x1f
+#define VGT_DEBUG_REG10__index_buffer_depth_r1_q__SHIFT 0x0
+#define VGT_DEBUG_REG10__eopg_r2_q_MASK 0x20
+#define VGT_DEBUG_REG10__eopg_r2_q__SHIFT 0x5
+#define VGT_DEBUG_REG10__eotg_r2_q_MASK 0x40
+#define VGT_DEBUG_REG10__eotg_r2_q__SHIFT 0x6
+#define VGT_DEBUG_REG10__onchip_gs_en_r0_q_MASK 0x180
+#define VGT_DEBUG_REG10__onchip_gs_en_r0_q__SHIFT 0x7
+#define VGT_DEBUG_REG10__SPARE2_MASK 0x600
+#define VGT_DEBUG_REG10__SPARE2__SHIFT 0x9
+#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq_MASK 0x800
+#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq__SHIFT 0xb
+#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q_MASK 0x1000
+#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q__SHIFT 0xc
+#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0_MASK 0x7fe000
+#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0__SHIFT 0xd
+#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0_MASK 0xff800000
+#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0__SHIFT 0x17
+#define VGT_DEBUG_REG11__tm_busy_q_MASK 0x1
+#define VGT_DEBUG_REG11__tm_busy_q__SHIFT 0x0
+#define VGT_DEBUG_REG11__tm_noif_busy_q_MASK 0x2
+#define VGT_DEBUG_REG11__tm_noif_busy_q__SHIFT 0x1
+#define VGT_DEBUG_REG11__tm_out_busy_q_MASK 0x4
+#define VGT_DEBUG_REG11__tm_out_busy_q__SHIFT 0x2
+#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy_MASK 0x8
+#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy__SHIFT 0x3
+#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy_MASK 0x10
+#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy__SHIFT 0x4
+#define VGT_DEBUG_REG11__SPARE1_MASK 0x20
+#define VGT_DEBUG_REG11__SPARE1__SHIFT 0x5
+#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy_MASK 0x40
+#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy__SHIFT 0x6
+#define VGT_DEBUG_REG11__spi_esthread_fifo_busy_MASK 0x80
+#define VGT_DEBUG_REG11__spi_esthread_fifo_busy__SHIFT 0x7
+#define VGT_DEBUG_REG11__hold_eswave_MASK 0x100
+#define VGT_DEBUG_REG11__hold_eswave__SHIFT 0x8
+#define VGT_DEBUG_REG11__es_rb_roll_over_r3_MASK 0x200
+#define VGT_DEBUG_REG11__es_rb_roll_over_r3__SHIFT 0x9
+#define VGT_DEBUG_REG11__counters_busy_r0_MASK 0x400
+#define VGT_DEBUG_REG11__counters_busy_r0__SHIFT 0xa
+#define VGT_DEBUG_REG11__counters_avail_r0_MASK 0x800
+#define VGT_DEBUG_REG11__counters_avail_r0__SHIFT 0xb
+#define VGT_DEBUG_REG11__counters_available_r0_MASK 0x1000
+#define VGT_DEBUG_REG11__counters_available_r0__SHIFT 0xc
+#define VGT_DEBUG_REG11__vs_event_fifo_rtr_MASK 0x2000
+#define VGT_DEBUG_REG11__vs_event_fifo_rtr__SHIFT 0xd
+#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q_MASK 0x4000
+#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q__SHIFT 0xe
+#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q_MASK 0x8000
+#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q__SHIFT 0xf
+#define VGT_DEBUG_REG11__gs_issue_rtr_MASK 0x10000
+#define VGT_DEBUG_REG11__gs_issue_rtr__SHIFT 0x10
+#define VGT_DEBUG_REG11__tm_pt_event_rtr_MASK 0x20000
+#define VGT_DEBUG_REG11__tm_pt_event_rtr__SHIFT 0x11
+#define VGT_DEBUG_REG11__SPARE0_MASK 0x40000
+#define VGT_DEBUG_REG11__SPARE0__SHIFT 0x12
+#define VGT_DEBUG_REG11__gs_r0_rtr_MASK 0x80000
+#define VGT_DEBUG_REG11__gs_r0_rtr__SHIFT 0x13
+#define VGT_DEBUG_REG11__es_r0_rtr_MASK 0x100000
+#define VGT_DEBUG_REG11__es_r0_rtr__SHIFT 0x14
+#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr_MASK 0x200000
+#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr__SHIFT 0x15
+#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr_MASK 0x400000
+#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr__SHIFT 0x16
+#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr_MASK 0x800000
+#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr__SHIFT 0x17
+#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr_MASK 0x1000000
+#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr__SHIFT 0x18
+#define VGT_DEBUG_REG11__vs_event_fifo_empty_MASK 0x2000000
+#define VGT_DEBUG_REG11__vs_event_fifo_empty__SHIFT 0x19
+#define VGT_DEBUG_REG11__vs_event_fifo_full_MASK 0x4000000
+#define VGT_DEBUG_REG11__vs_event_fifo_full__SHIFT 0x1a
+#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full_MASK 0x8000000
+#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full__SHIFT 0x1b
+#define VGT_DEBUG_REG11__vs_dealloc_tbl_full_MASK 0x10000000
+#define VGT_DEBUG_REG11__vs_dealloc_tbl_full__SHIFT 0x1c
+#define VGT_DEBUG_REG11__send_event_q_MASK 0x20000000
+#define VGT_DEBUG_REG11__send_event_q__SHIFT 0x1d
+#define VGT_DEBUG_REG11__es_tbl_empty_MASK 0x40000000
+#define VGT_DEBUG_REG11__es_tbl_empty__SHIFT 0x1e
+#define VGT_DEBUG_REG11__no_active_states_r0_MASK 0x80000000
+#define VGT_DEBUG_REG11__no_active_states_r0__SHIFT 0x1f
+#define VGT_DEBUG_REG12__gs_state0_r0_q_MASK 0x7
+#define VGT_DEBUG_REG12__gs_state0_r0_q__SHIFT 0x0
+#define VGT_DEBUG_REG12__gs_state1_r0_q_MASK 0x38
+#define VGT_DEBUG_REG12__gs_state1_r0_q__SHIFT 0x3
+#define VGT_DEBUG_REG12__gs_state2_r0_q_MASK 0x1c0
+#define VGT_DEBUG_REG12__gs_state2_r0_q__SHIFT 0x6
+#define VGT_DEBUG_REG12__gs_state3_r0_q_MASK 0xe00
+#define VGT_DEBUG_REG12__gs_state3_r0_q__SHIFT 0x9
+#define VGT_DEBUG_REG12__gs_state4_r0_q_MASK 0x7000
+#define VGT_DEBUG_REG12__gs_state4_r0_q__SHIFT 0xc
+#define VGT_DEBUG_REG12__gs_state5_r0_q_MASK 0x38000
+#define VGT_DEBUG_REG12__gs_state5_r0_q__SHIFT 0xf
+#define VGT_DEBUG_REG12__gs_state6_r0_q_MASK 0x1c0000
+#define VGT_DEBUG_REG12__gs_state6_r0_q__SHIFT 0x12
+#define VGT_DEBUG_REG12__gs_state7_r0_q_MASK 0xe00000
+#define VGT_DEBUG_REG12__gs_state7_r0_q__SHIFT 0x15
+#define VGT_DEBUG_REG12__gs_state8_r0_q_MASK 0x7000000
+#define VGT_DEBUG_REG12__gs_state8_r0_q__SHIFT 0x18
+#define VGT_DEBUG_REG12__gs_state9_r0_q_MASK 0x38000000
+#define VGT_DEBUG_REG12__gs_state9_r0_q__SHIFT 0x1b
+#define VGT_DEBUG_REG12__hold_eswave_eop_MASK 0x40000000
+#define VGT_DEBUG_REG12__hold_eswave_eop__SHIFT 0x1e
+#define VGT_DEBUG_REG12__SPARE0_MASK 0x80000000
+#define VGT_DEBUG_REG12__SPARE0__SHIFT 0x1f
+#define VGT_DEBUG_REG13__gs_state10_r0_q_MASK 0x7
+#define VGT_DEBUG_REG13__gs_state10_r0_q__SHIFT 0x0
+#define VGT_DEBUG_REG13__gs_state11_r0_q_MASK 0x38
+#define VGT_DEBUG_REG13__gs_state11_r0_q__SHIFT 0x3
+#define VGT_DEBUG_REG13__gs_state12_r0_q_MASK 0x1c0
+#define VGT_DEBUG_REG13__gs_state12_r0_q__SHIFT 0x6
+#define VGT_DEBUG_REG13__gs_state13_r0_q_MASK 0xe00
+#define VGT_DEBUG_REG13__gs_state13_r0_q__SHIFT 0x9
+#define VGT_DEBUG_REG13__gs_state14_r0_q_MASK 0x7000
+#define VGT_DEBUG_REG13__gs_state14_r0_q__SHIFT 0xc
+#define VGT_DEBUG_REG13__gs_state15_r0_q_MASK 0x38000
+#define VGT_DEBUG_REG13__gs_state15_r0_q__SHIFT 0xf
+#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0_MASK 0x3c0000
+#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0__SHIFT 0x12
+#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0_MASK 0x400000
+#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0__SHIFT 0x16
+#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0_MASK 0x800000
+#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0__SHIFT 0x17
+#define VGT_DEBUG_REG13__es_tbl_full_MASK 0x1000000
+#define VGT_DEBUG_REG13__es_tbl_full__SHIFT 0x18
+#define VGT_DEBUG_REG13__SPARE1_MASK 0x2000000
+#define VGT_DEBUG_REG13__SPARE1__SHIFT 0x19
+#define VGT_DEBUG_REG13__SPARE0_MASK 0x4000000
+#define VGT_DEBUG_REG13__SPARE0__SHIFT 0x1a
+#define VGT_DEBUG_REG13__active_cm_sm_r0_q_MASK 0xf8000000
+#define VGT_DEBUG_REG13__active_cm_sm_r0_q__SHIFT 0x1b
+#define VGT_DEBUG_REG14__SPARE3_MASK 0xf
+#define VGT_DEBUG_REG14__SPARE3__SHIFT 0x0
+#define VGT_DEBUG_REG14__gsfetch_done_fifo_full_MASK 0x10
+#define VGT_DEBUG_REG14__gsfetch_done_fifo_full__SHIFT 0x4
+#define VGT_DEBUG_REG14__gs_rb_space_avail_r0_MASK 0x20
+#define VGT_DEBUG_REG14__gs_rb_space_avail_r0__SHIFT 0x5
+#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0_MASK 0x40
+#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0__SHIFT 0x6
+#define VGT_DEBUG_REG14__SPARE8_MASK 0x180
+#define VGT_DEBUG_REG14__SPARE8__SHIFT 0x7
+#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0_MASK 0x200
+#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0__SHIFT 0x9
+#define VGT_DEBUG_REG14__es_flush_cnt_busy_q_MASK 0x400
+#define VGT_DEBUG_REG14__es_flush_cnt_busy_q__SHIFT 0xa
+#define VGT_DEBUG_REG14__gs_tbl_full_r0_MASK 0x800
+#define VGT_DEBUG_REG14__gs_tbl_full_r0__SHIFT 0xb
+#define VGT_DEBUG_REG14__SPARE2_MASK 0x1ff000
+#define VGT_DEBUG_REG14__SPARE2__SHIFT 0xc
+#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy_MASK 0x200000
+#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy__SHIFT 0x15
+#define VGT_DEBUG_REG14__SPARE_MASK 0x1c00000
+#define VGT_DEBUG_REG14__SPARE__SHIFT 0x16
+#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q_MASK 0x2000000
+#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q__SHIFT 0x19
+#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0_MASK 0x4000000
+#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0__SHIFT 0x1a
+#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy_MASK 0x8000000
+#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy__SHIFT 0x1b
+#define VGT_DEBUG_REG14__SPARE1_MASK 0x10000000
+#define VGT_DEBUG_REG14__SPARE1__SHIFT 0x1c
+#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0_MASK 0x20000000
+#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x1d
+#define VGT_DEBUG_REG14__SPARE0_MASK 0x40000000
+#define VGT_DEBUG_REG14__SPARE0__SHIFT 0x1e
+#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q_MASK 0x80000000
+#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x1f
+#define VGT_DEBUG_REG15__cm_busy_q_MASK 0x1
+#define VGT_DEBUG_REG15__cm_busy_q__SHIFT 0x0
+#define VGT_DEBUG_REG15__counters_busy_q_MASK 0x2
+#define VGT_DEBUG_REG15__counters_busy_q__SHIFT 0x1
+#define VGT_DEBUG_REG15__output_fifo_empty_MASK 0x4
+#define VGT_DEBUG_REG15__output_fifo_empty__SHIFT 0x2
+#define VGT_DEBUG_REG15__output_fifo_full_MASK 0x8
+#define VGT_DEBUG_REG15__output_fifo_full__SHIFT 0x3
+#define VGT_DEBUG_REG15__counters_full_MASK 0x10
+#define VGT_DEBUG_REG15__counters_full__SHIFT 0x4
+#define VGT_DEBUG_REG15__active_sm_q_MASK 0x3e0
+#define VGT_DEBUG_REG15__active_sm_q__SHIFT 0x5
+#define VGT_DEBUG_REG15__entry_rdptr_q_MASK 0x7c00
+#define VGT_DEBUG_REG15__entry_rdptr_q__SHIFT 0xa
+#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q_MASK 0xf8000
+#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q__SHIFT 0xf
+#define VGT_DEBUG_REG15__SPARE25_MASK 0x3f00000
+#define VGT_DEBUG_REG15__SPARE25__SHIFT 0x14
+#define VGT_DEBUG_REG15__st_cut_mode_q_MASK 0xc000000
+#define VGT_DEBUG_REG15__st_cut_mode_q__SHIFT 0x1a
+#define VGT_DEBUG_REG15__gs_done_array_q_not_0_MASK 0x10000000
+#define VGT_DEBUG_REG15__gs_done_array_q_not_0__SHIFT 0x1c
+#define VGT_DEBUG_REG15__SPARE31_MASK 0xe0000000
+#define VGT_DEBUG_REG15__SPARE31__SHIFT 0x1d
+#define VGT_DEBUG_REG16__gog_busy_MASK 0x1
+#define VGT_DEBUG_REG16__gog_busy__SHIFT 0x0
+#define VGT_DEBUG_REG16__gog_state_q_MASK 0xe
+#define VGT_DEBUG_REG16__gog_state_q__SHIFT 0x1
+#define VGT_DEBUG_REG16__r0_rtr_MASK 0x10
+#define VGT_DEBUG_REG16__r0_rtr__SHIFT 0x4
+#define VGT_DEBUG_REG16__r1_rtr_MASK 0x20
+#define VGT_DEBUG_REG16__r1_rtr__SHIFT 0x5
+#define VGT_DEBUG_REG16__r1_upstream_rtr_MASK 0x40
+#define VGT_DEBUG_REG16__r1_upstream_rtr__SHIFT 0x6
+#define VGT_DEBUG_REG16__r2_vs_tbl_rtr_MASK 0x80
+#define VGT_DEBUG_REG16__r2_vs_tbl_rtr__SHIFT 0x7
+#define VGT_DEBUG_REG16__r2_prim_rtr_MASK 0x100
+#define VGT_DEBUG_REG16__r2_prim_rtr__SHIFT 0x8
+#define VGT_DEBUG_REG16__r2_indx_rtr_MASK 0x200
+#define VGT_DEBUG_REG16__r2_indx_rtr__SHIFT 0x9
+#define VGT_DEBUG_REG16__r2_rtr_MASK 0x400
+#define VGT_DEBUG_REG16__r2_rtr__SHIFT 0xa
+#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr_MASK 0x800
+#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr__SHIFT 0xb
+#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr_MASK 0x1000
+#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG16__indx_valid_r2_q_MASK 0x2000
+#define VGT_DEBUG_REG16__indx_valid_r2_q__SHIFT 0xd
+#define VGT_DEBUG_REG16__prim_valid_r2_q_MASK 0x4000
+#define VGT_DEBUG_REG16__prim_valid_r2_q__SHIFT 0xe
+#define VGT_DEBUG_REG16__valid_r2_q_MASK 0x8000
+#define VGT_DEBUG_REG16__valid_r2_q__SHIFT 0xf
+#define VGT_DEBUG_REG16__prim_valid_r1_q_MASK 0x10000
+#define VGT_DEBUG_REG16__prim_valid_r1_q__SHIFT 0x10
+#define VGT_DEBUG_REG16__indx_valid_r1_q_MASK 0x20000
+#define VGT_DEBUG_REG16__indx_valid_r1_q__SHIFT 0x11
+#define VGT_DEBUG_REG16__valid_r1_q_MASK 0x40000
+#define VGT_DEBUG_REG16__valid_r1_q__SHIFT 0x12
+#define VGT_DEBUG_REG16__indx_valid_r0_q_MASK 0x80000
+#define VGT_DEBUG_REG16__indx_valid_r0_q__SHIFT 0x13
+#define VGT_DEBUG_REG16__prim_valid_r0_q_MASK 0x100000
+#define VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT 0x14
+#define VGT_DEBUG_REG16__valid_r0_q_MASK 0x200000
+#define VGT_DEBUG_REG16__valid_r0_q__SHIFT 0x15
+#define VGT_DEBUG_REG16__send_event_q_MASK 0x400000
+#define VGT_DEBUG_REG16__send_event_q__SHIFT 0x16
+#define VGT_DEBUG_REG16__SPARE24_MASK 0x800000
+#define VGT_DEBUG_REG16__SPARE24__SHIFT 0x17
+#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q_MASK 0x1000000
+#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q__SHIFT 0x18
+#define VGT_DEBUG_REG16__gog_out_prim_state_sel_MASK 0xe000000
+#define VGT_DEBUG_REG16__gog_out_prim_state_sel__SHIFT 0x19
+#define VGT_DEBUG_REG16__multiple_streams_en_r1_q_MASK 0x10000000
+#define VGT_DEBUG_REG16__multiple_streams_en_r1_q__SHIFT 0x1c
+#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0_MASK 0x20000000
+#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT 0x1d
+#define VGT_DEBUG_REG16__num_gs_r2_q_not_0_MASK 0x40000000
+#define VGT_DEBUG_REG16__num_gs_r2_q_not_0__SHIFT 0x1e
+#define VGT_DEBUG_REG16__new_vs_thread_r2_MASK 0x80000000
+#define VGT_DEBUG_REG16__new_vs_thread_r2__SHIFT 0x1f
+#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0_MASK 0x3f
+#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0__SHIFT 0x0
+#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0_MASK 0xfc0
+#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0__SHIFT 0x6
+#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0_MASK 0x3f000
+#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0__SHIFT 0xc
+#define VGT_DEBUG_REG17__gog_out_indx_13_0_MASK 0xfffc0000
+#define VGT_DEBUG_REG17__gog_out_indx_13_0__SHIFT 0x12
+#define VGT_DEBUG_REG18__grp_vr_valid_MASK 0x1
+#define VGT_DEBUG_REG18__grp_vr_valid__SHIFT 0x0
+#define VGT_DEBUG_REG18__pipe0_dr_MASK 0x2
+#define VGT_DEBUG_REG18__pipe0_dr__SHIFT 0x1
+#define VGT_DEBUG_REG18__pipe1_dr_MASK 0x4
+#define VGT_DEBUG_REG18__pipe1_dr__SHIFT 0x2
+#define VGT_DEBUG_REG18__vr_grp_read_MASK 0x8
+#define VGT_DEBUG_REG18__vr_grp_read__SHIFT 0x3
+#define VGT_DEBUG_REG18__pipe0_rtr_MASK 0x10
+#define VGT_DEBUG_REG18__pipe0_rtr__SHIFT 0x4
+#define VGT_DEBUG_REG18__pipe1_rtr_MASK 0x20
+#define VGT_DEBUG_REG18__pipe1_rtr__SHIFT 0x5
+#define VGT_DEBUG_REG18__out_vr_indx_read_MASK 0x40
+#define VGT_DEBUG_REG18__out_vr_indx_read__SHIFT 0x6
+#define VGT_DEBUG_REG18__out_vr_prim_read_MASK 0x80
+#define VGT_DEBUG_REG18__out_vr_prim_read__SHIFT 0x7
+#define VGT_DEBUG_REG18__indices_to_send_q_MASK 0x700
+#define VGT_DEBUG_REG18__indices_to_send_q__SHIFT 0x8
+#define VGT_DEBUG_REG18__valid_indices_MASK 0x800
+#define VGT_DEBUG_REG18__valid_indices__SHIFT 0xb
+#define VGT_DEBUG_REG18__last_indx_of_prim_MASK 0x1000
+#define VGT_DEBUG_REG18__last_indx_of_prim__SHIFT 0xc
+#define VGT_DEBUG_REG18__indx0_new_d_MASK 0x2000
+#define VGT_DEBUG_REG18__indx0_new_d__SHIFT 0xd
+#define VGT_DEBUG_REG18__indx1_new_d_MASK 0x4000
+#define VGT_DEBUG_REG18__indx1_new_d__SHIFT 0xe
+#define VGT_DEBUG_REG18__indx2_new_d_MASK 0x8000
+#define VGT_DEBUG_REG18__indx2_new_d__SHIFT 0xf
+#define VGT_DEBUG_REG18__indx2_hit_d_MASK 0x10000
+#define VGT_DEBUG_REG18__indx2_hit_d__SHIFT 0x10
+#define VGT_DEBUG_REG18__indx1_hit_d_MASK 0x20000
+#define VGT_DEBUG_REG18__indx1_hit_d__SHIFT 0x11
+#define VGT_DEBUG_REG18__indx0_hit_d_MASK 0x40000
+#define VGT_DEBUG_REG18__indx0_hit_d__SHIFT 0x12
+#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q_MASK 0x80000
+#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q__SHIFT 0x13
+#define VGT_DEBUG_REG18__last_group_of_instance_r0_q_MASK 0x100000
+#define VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT 0x14
+#define VGT_DEBUG_REG18__null_primitive_r0_q_MASK 0x200000
+#define VGT_DEBUG_REG18__null_primitive_r0_q__SHIFT 0x15
+#define VGT_DEBUG_REG18__eop_r0_q_MASK 0x400000
+#define VGT_DEBUG_REG18__eop_r0_q__SHIFT 0x16
+#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d_MASK 0x800000
+#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d__SHIFT 0x17
+#define VGT_DEBUG_REG18__sub_prim_type_r0_q_MASK 0x7000000
+#define VGT_DEBUG_REG18__sub_prim_type_r0_q__SHIFT 0x18
+#define VGT_DEBUG_REG18__gs_scenario_a_r0_q_MASK 0x8000000
+#define VGT_DEBUG_REG18__gs_scenario_a_r0_q__SHIFT 0x1b
+#define VGT_DEBUG_REG18__gs_scenario_b_r0_q_MASK 0x10000000
+#define VGT_DEBUG_REG18__gs_scenario_b_r0_q__SHIFT 0x1c
+#define VGT_DEBUG_REG18__components_valid_r0_q_MASK 0xe0000000
+#define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT 0x1d
+#define VGT_DEBUG_REG19__separate_out_busy_q_MASK 0x1
+#define VGT_DEBUG_REG19__separate_out_busy_q__SHIFT 0x0
+#define VGT_DEBUG_REG19__separate_out_indx_busy_q_MASK 0x2
+#define VGT_DEBUG_REG19__separate_out_indx_busy_q__SHIFT 0x1
+#define VGT_DEBUG_REG19__prim_buffer_empty_MASK 0x4
+#define VGT_DEBUG_REG19__prim_buffer_empty__SHIFT 0x2
+#define VGT_DEBUG_REG19__prim_buffer_full_MASK 0x8
+#define VGT_DEBUG_REG19__prim_buffer_full__SHIFT 0x3
+#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q_MASK 0x10
+#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q__SHIFT 0x4
+#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q_MASK 0x20
+#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q__SHIFT 0x5
+#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q_MASK 0x40
+#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q__SHIFT 0x6
+#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q_MASK 0x80
+#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q__SHIFT 0x7
+#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q_MASK 0x100
+#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q__SHIFT 0x8
+#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q_MASK 0x200
+#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q__SHIFT 0x9
+#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q_MASK 0x400
+#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q__SHIFT 0xa
+#define VGT_DEBUG_REG19__hold_prim_MASK 0x800
+#define VGT_DEBUG_REG19__hold_prim__SHIFT 0xb
+#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q_MASK 0x1000
+#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q__SHIFT 0xc
+#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q_MASK 0x2000
+#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q__SHIFT 0xd
+#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q_MASK 0x4000
+#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q__SHIFT 0xe
+#define VGT_DEBUG_REG19__new_packet_q_MASK 0x8000
+#define VGT_DEBUG_REG19__new_packet_q__SHIFT 0xf
+#define VGT_DEBUG_REG19__buffered_prim_event_MASK 0x10000
+#define VGT_DEBUG_REG19__buffered_prim_event__SHIFT 0x10
+#define VGT_DEBUG_REG19__buffered_prim_null_primitive_MASK 0x20000
+#define VGT_DEBUG_REG19__buffered_prim_null_primitive__SHIFT 0x11
+#define VGT_DEBUG_REG19__buffered_prim_eop_MASK 0x40000
+#define VGT_DEBUG_REG19__buffered_prim_eop__SHIFT 0x12
+#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect_MASK 0x80000
+#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect__SHIFT 0x13
+#define VGT_DEBUG_REG19__buffered_prim_type_event_MASK 0x3f00000
+#define VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT 0x14
+#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q_MASK 0x4000000
+#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q__SHIFT 0x1a
+#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q_MASK 0x8000000
+#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q__SHIFT 0x1b
+#define VGT_DEBUG_REG19__num_new_unique_rel_indx_MASK 0x30000000
+#define VGT_DEBUG_REG19__num_new_unique_rel_indx__SHIFT 0x1c
+#define VGT_DEBUG_REG19__null_terminate_vtx_vector_MASK 0x40000000
+#define VGT_DEBUG_REG19__null_terminate_vtx_vector__SHIFT 0x1e
+#define VGT_DEBUG_REG19__filter_event_MASK 0x80000000
+#define VGT_DEBUG_REG19__filter_event__SHIFT 0x1f
+#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex_MASK 0xffff
+#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex__SHIFT 0x0
+#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK 0x10000
+#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT 0x10
+#define VGT_DEBUG_REG20__SPARE17_MASK 0x20000
+#define VGT_DEBUG_REG20__SPARE17__SHIFT 0x11
+#define VGT_DEBUG_REG20__alloc_counter_q_MASK 0x3c0000
+#define VGT_DEBUG_REG20__alloc_counter_q__SHIFT 0x12
+#define VGT_DEBUG_REG20__curr_dealloc_distance_q_MASK 0x1fc00000
+#define VGT_DEBUG_REG20__curr_dealloc_distance_q__SHIFT 0x16
+#define VGT_DEBUG_REG20__new_allocate_q_MASK 0x20000000
+#define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x1d
+#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0_MASK 0x40000000
+#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0__SHIFT 0x1e
+#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0_MASK 0x80000000
+#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0__SHIFT 0x1f
+#define VGT_DEBUG_REG21__out_indx_fifo_empty_MASK 0x1
+#define VGT_DEBUG_REG21__out_indx_fifo_empty__SHIFT 0x0
+#define VGT_DEBUG_REG21__indx_side_fifo_empty_MASK 0x2
+#define VGT_DEBUG_REG21__indx_side_fifo_empty__SHIFT 0x1
+#define VGT_DEBUG_REG21__pipe0_dr_MASK 0x4
+#define VGT_DEBUG_REG21__pipe0_dr__SHIFT 0x2
+#define VGT_DEBUG_REG21__pipe1_dr_MASK 0x8
+#define VGT_DEBUG_REG21__pipe1_dr__SHIFT 0x3
+#define VGT_DEBUG_REG21__pipe2_dr_MASK 0x10
+#define VGT_DEBUG_REG21__pipe2_dr__SHIFT 0x4
+#define VGT_DEBUG_REG21__vsthread_buff_empty_MASK 0x20
+#define VGT_DEBUG_REG21__vsthread_buff_empty__SHIFT 0x5
+#define VGT_DEBUG_REG21__out_indx_fifo_full_MASK 0x40
+#define VGT_DEBUG_REG21__out_indx_fifo_full__SHIFT 0x6
+#define VGT_DEBUG_REG21__indx_side_fifo_full_MASK 0x80
+#define VGT_DEBUG_REG21__indx_side_fifo_full__SHIFT 0x7
+#define VGT_DEBUG_REG21__pipe0_rtr_MASK 0x100
+#define VGT_DEBUG_REG21__pipe0_rtr__SHIFT 0x8
+#define VGT_DEBUG_REG21__pipe1_rtr_MASK 0x200
+#define VGT_DEBUG_REG21__pipe1_rtr__SHIFT 0x9
+#define VGT_DEBUG_REG21__pipe2_rtr_MASK 0x400
+#define VGT_DEBUG_REG21__pipe2_rtr__SHIFT 0xa
+#define VGT_DEBUG_REG21__vsthread_buff_full_MASK 0x800
+#define VGT_DEBUG_REG21__vsthread_buff_full__SHIFT 0xb
+#define VGT_DEBUG_REG21__interfaces_rtr_MASK 0x1000
+#define VGT_DEBUG_REG21__interfaces_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG21__indx_count_q_not_0_MASK 0x2000
+#define VGT_DEBUG_REG21__indx_count_q_not_0__SHIFT 0xd
+#define VGT_DEBUG_REG21__wait_for_external_eopg_q_MASK 0x4000
+#define VGT_DEBUG_REG21__wait_for_external_eopg_q__SHIFT 0xe
+#define VGT_DEBUG_REG21__full_state_p1_q_MASK 0x8000
+#define VGT_DEBUG_REG21__full_state_p1_q__SHIFT 0xf
+#define VGT_DEBUG_REG21__indx_side_indx_valid_MASK 0x10000
+#define VGT_DEBUG_REG21__indx_side_indx_valid__SHIFT 0x10
+#define VGT_DEBUG_REG21__stateid_p0_q_MASK 0xe0000
+#define VGT_DEBUG_REG21__stateid_p0_q__SHIFT 0x11
+#define VGT_DEBUG_REG21__is_event_p0_q_MASK 0x100000
+#define VGT_DEBUG_REG21__is_event_p0_q__SHIFT 0x14
+#define VGT_DEBUG_REG21__lshs_dealloc_p1_MASK 0x200000
+#define VGT_DEBUG_REG21__lshs_dealloc_p1__SHIFT 0x15
+#define VGT_DEBUG_REG21__stream_id_r2_q_MASK 0x400000
+#define VGT_DEBUG_REG21__stream_id_r2_q__SHIFT 0x16
+#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0_MASK 0x800000
+#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0__SHIFT 0x17
+#define VGT_DEBUG_REG21__buff_full_p1_MASK 0x1000000
+#define VGT_DEBUG_REG21__buff_full_p1__SHIFT 0x18
+#define VGT_DEBUG_REG21__strmout_valid_p1_MASK 0x2000000
+#define VGT_DEBUG_REG21__strmout_valid_p1__SHIFT 0x19
+#define VGT_DEBUG_REG21__eotg_r2_q_MASK 0x4000000
+#define VGT_DEBUG_REG21__eotg_r2_q__SHIFT 0x1a
+#define VGT_DEBUG_REG21__null_r2_q_MASK 0x8000000
+#define VGT_DEBUG_REG21__null_r2_q__SHIFT 0x1b
+#define VGT_DEBUG_REG21__p0_dr_MASK 0x10000000
+#define VGT_DEBUG_REG21__p0_dr__SHIFT 0x1c
+#define VGT_DEBUG_REG21__p0_rtr_MASK 0x20000000
+#define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x1d
+#define VGT_DEBUG_REG21__eopg_p0_q_MASK 0x40000000
+#define VGT_DEBUG_REG21__eopg_p0_q__SHIFT 0x1e
+#define VGT_DEBUG_REG21__p0_nobp_MASK 0x80000000
+#define VGT_DEBUG_REG21__p0_nobp__SHIFT 0x1f
+#define VGT_DEBUG_REG22__cm_state16_MASK 0x3
+#define VGT_DEBUG_REG22__cm_state16__SHIFT 0x0
+#define VGT_DEBUG_REG22__cm_state17_MASK 0xc
+#define VGT_DEBUG_REG22__cm_state17__SHIFT 0x2
+#define VGT_DEBUG_REG22__cm_state18_MASK 0x30
+#define VGT_DEBUG_REG22__cm_state18__SHIFT 0x4
+#define VGT_DEBUG_REG22__cm_state19_MASK 0xc0
+#define VGT_DEBUG_REG22__cm_state19__SHIFT 0x6
+#define VGT_DEBUG_REG22__cm_state20_MASK 0x300
+#define VGT_DEBUG_REG22__cm_state20__SHIFT 0x8
+#define VGT_DEBUG_REG22__cm_state21_MASK 0xc00
+#define VGT_DEBUG_REG22__cm_state21__SHIFT 0xa
+#define VGT_DEBUG_REG22__cm_state22_MASK 0x3000
+#define VGT_DEBUG_REG22__cm_state22__SHIFT 0xc
+#define VGT_DEBUG_REG22__cm_state23_MASK 0xc000
+#define VGT_DEBUG_REG22__cm_state23__SHIFT 0xe
+#define VGT_DEBUG_REG22__cm_state24_MASK 0x30000
+#define VGT_DEBUG_REG22__cm_state24__SHIFT 0x10
+#define VGT_DEBUG_REG22__cm_state25_MASK 0xc0000
+#define VGT_DEBUG_REG22__cm_state25__SHIFT 0x12
+#define VGT_DEBUG_REG22__cm_state26_MASK 0x300000
+#define VGT_DEBUG_REG22__cm_state26__SHIFT 0x14
+#define VGT_DEBUG_REG22__cm_state27_MASK 0xc00000
+#define VGT_DEBUG_REG22__cm_state27__SHIFT 0x16
+#define VGT_DEBUG_REG22__cm_state28_MASK 0x3000000
+#define VGT_DEBUG_REG22__cm_state28__SHIFT 0x18
+#define VGT_DEBUG_REG22__cm_state29_MASK 0xc000000
+#define VGT_DEBUG_REG22__cm_state29__SHIFT 0x1a
+#define VGT_DEBUG_REG22__cm_state30_MASK 0x30000000
+#define VGT_DEBUG_REG22__cm_state30__SHIFT 0x1c
+#define VGT_DEBUG_REG22__cm_state31_MASK 0xc0000000
+#define VGT_DEBUG_REG22__cm_state31__SHIFT 0x1e
+#define VGT_DEBUG_REG23__frmt_busy_MASK 0x1
+#define VGT_DEBUG_REG23__frmt_busy__SHIFT 0x0
+#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr_MASK 0x2
+#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr__SHIFT 0x1
+#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr_MASK 0x4
+#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr__SHIFT 0x2
+#define VGT_DEBUG_REG23__prim_r3_rtr_MASK 0x8
+#define VGT_DEBUG_REG23__prim_r3_rtr__SHIFT 0x3
+#define VGT_DEBUG_REG23__prim_r2_rtr_MASK 0x10
+#define VGT_DEBUG_REG23__prim_r2_rtr__SHIFT 0x4
+#define VGT_DEBUG_REG23__vert_r3_rtr_MASK 0x20
+#define VGT_DEBUG_REG23__vert_r3_rtr__SHIFT 0x5
+#define VGT_DEBUG_REG23__vert_r2_rtr_MASK 0x40
+#define VGT_DEBUG_REG23__vert_r2_rtr__SHIFT 0x6
+#define VGT_DEBUG_REG23__vert_r1_rtr_MASK 0x80
+#define VGT_DEBUG_REG23__vert_r1_rtr__SHIFT 0x7
+#define VGT_DEBUG_REG23__vert_r0_rtr_MASK 0x100
+#define VGT_DEBUG_REG23__vert_r0_rtr__SHIFT 0x8
+#define VGT_DEBUG_REG23__prim_fifo_empty_MASK 0x200
+#define VGT_DEBUG_REG23__prim_fifo_empty__SHIFT 0x9
+#define VGT_DEBUG_REG23__prim_fifo_full_MASK 0x400
+#define VGT_DEBUG_REG23__prim_fifo_full__SHIFT 0xa
+#define VGT_DEBUG_REG23__vert_dr_r2_q_MASK 0x800
+#define VGT_DEBUG_REG23__vert_dr_r2_q__SHIFT 0xb
+#define VGT_DEBUG_REG23__prim_dr_r2_q_MASK 0x1000
+#define VGT_DEBUG_REG23__prim_dr_r2_q__SHIFT 0xc
+#define VGT_DEBUG_REG23__vert_dr_r1_q_MASK 0x2000
+#define VGT_DEBUG_REG23__vert_dr_r1_q__SHIFT 0xd
+#define VGT_DEBUG_REG23__vert_dr_r0_q_MASK 0x4000
+#define VGT_DEBUG_REG23__vert_dr_r0_q__SHIFT 0xe
+#define VGT_DEBUG_REG23__new_verts_r2_q_MASK 0x18000
+#define VGT_DEBUG_REG23__new_verts_r2_q__SHIFT 0xf
+#define VGT_DEBUG_REG23__verts_sent_r2_q_MASK 0x1e0000
+#define VGT_DEBUG_REG23__verts_sent_r2_q__SHIFT 0x11
+#define VGT_DEBUG_REG23__prim_state_sel_r2_q_MASK 0xe00000
+#define VGT_DEBUG_REG23__prim_state_sel_r2_q__SHIFT 0x15
+#define VGT_DEBUG_REG23__SPARE_MASK 0xff000000
+#define VGT_DEBUG_REG23__SPARE__SHIFT 0x18
+#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0_MASK 0xffffff
+#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0__SHIFT 0x0
+#define VGT_DEBUG_REG24__dependent_st_cut_mode_q_MASK 0x3000000
+#define VGT_DEBUG_REG24__dependent_st_cut_mode_q__SHIFT 0x18
+#define VGT_DEBUG_REG24__SPARE31_MASK 0xfc000000
+#define VGT_DEBUG_REG24__SPARE31__SHIFT 0x1a
+#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x3ffffff
+#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0__SHIFT 0x0
+#define VGT_DEBUG_REG25__active_sm_r0_q_MASK 0x3c000000
+#define VGT_DEBUG_REG25__active_sm_r0_q__SHIFT 0x1a
+#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q_MASK 0x40000000
+#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q__SHIFT 0x1e
+#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q_MASK 0x80000000
+#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q__SHIFT 0x1f
+#define VGT_DEBUG_REG26__cm_state0_MASK 0x3
+#define VGT_DEBUG_REG26__cm_state0__SHIFT 0x0
+#define VGT_DEBUG_REG26__cm_state1_MASK 0xc
+#define VGT_DEBUG_REG26__cm_state1__SHIFT 0x2
+#define VGT_DEBUG_REG26__cm_state2_MASK 0x30
+#define VGT_DEBUG_REG26__cm_state2__SHIFT 0x4
+#define VGT_DEBUG_REG26__cm_state3_MASK 0xc0
+#define VGT_DEBUG_REG26__cm_state3__SHIFT 0x6
+#define VGT_DEBUG_REG26__cm_state4_MASK 0x300
+#define VGT_DEBUG_REG26__cm_state4__SHIFT 0x8
+#define VGT_DEBUG_REG26__cm_state5_MASK 0xc00
+#define VGT_DEBUG_REG26__cm_state5__SHIFT 0xa
+#define VGT_DEBUG_REG26__cm_state6_MASK 0x3000
+#define VGT_DEBUG_REG26__cm_state6__SHIFT 0xc
+#define VGT_DEBUG_REG26__cm_state7_MASK 0xc000
+#define VGT_DEBUG_REG26__cm_state7__SHIFT 0xe
+#define VGT_DEBUG_REG26__cm_state8_MASK 0x30000
+#define VGT_DEBUG_REG26__cm_state8__SHIFT 0x10
+#define VGT_DEBUG_REG26__cm_state9_MASK 0xc0000
+#define VGT_DEBUG_REG26__cm_state9__SHIFT 0x12
+#define VGT_DEBUG_REG26__cm_state10_MASK 0x300000
+#define VGT_DEBUG_REG26__cm_state10__SHIFT 0x14
+#define VGT_DEBUG_REG26__cm_state11_MASK 0xc00000
+#define VGT_DEBUG_REG26__cm_state11__SHIFT 0x16
+#define VGT_DEBUG_REG26__cm_state12_MASK 0x3000000
+#define VGT_DEBUG_REG26__cm_state12__SHIFT 0x18
+#define VGT_DEBUG_REG26__cm_state13_MASK 0xc000000
+#define VGT_DEBUG_REG26__cm_state13__SHIFT 0x1a
+#define VGT_DEBUG_REG26__cm_state14_MASK 0x30000000
+#define VGT_DEBUG_REG26__cm_state14__SHIFT 0x1c
+#define VGT_DEBUG_REG26__cm_state15_MASK 0xc0000000
+#define VGT_DEBUG_REG26__cm_state15__SHIFT 0x1e
+#define VGT_DEBUG_REG27__pipe0_dr_MASK 0x1
+#define VGT_DEBUG_REG27__pipe0_dr__SHIFT 0x0
+#define VGT_DEBUG_REG27__gsc0_dr_MASK 0x2
+#define VGT_DEBUG_REG27__gsc0_dr__SHIFT 0x1
+#define VGT_DEBUG_REG27__pipe1_dr_MASK 0x4
+#define VGT_DEBUG_REG27__pipe1_dr__SHIFT 0x2
+#define VGT_DEBUG_REG27__tm_pt_event_rtr_MASK 0x8
+#define VGT_DEBUG_REG27__tm_pt_event_rtr__SHIFT 0x3
+#define VGT_DEBUG_REG27__pipe0_rtr_MASK 0x10
+#define VGT_DEBUG_REG27__pipe0_rtr__SHIFT 0x4
+#define VGT_DEBUG_REG27__gsc0_rtr_MASK 0x20
+#define VGT_DEBUG_REG27__gsc0_rtr__SHIFT 0x5
+#define VGT_DEBUG_REG27__pipe1_rtr_MASK 0x40
+#define VGT_DEBUG_REG27__pipe1_rtr__SHIFT 0x6
+#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q_MASK 0x80
+#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q__SHIFT 0x7
+#define VGT_DEBUG_REG27__indices_to_send_p0_q_MASK 0x300
+#define VGT_DEBUG_REG27__indices_to_send_p0_q__SHIFT 0x8
+#define VGT_DEBUG_REG27__event_flag_p1_q_MASK 0x400
+#define VGT_DEBUG_REG27__event_flag_p1_q__SHIFT 0xa
+#define VGT_DEBUG_REG27__eop_p1_q_MASK 0x800
+#define VGT_DEBUG_REG27__eop_p1_q__SHIFT 0xb
+#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q_MASK 0x3000
+#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q__SHIFT 0xc
+#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q_MASK 0x4000
+#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q__SHIFT 0xe
+#define VGT_DEBUG_REG27__gsc_eop_p0_q_MASK 0x8000
+#define VGT_DEBUG_REG27__gsc_eop_p0_q__SHIFT 0xf
+#define VGT_DEBUG_REG27__gsc_2cycle_output_MASK 0x10000
+#define VGT_DEBUG_REG27__gsc_2cycle_output__SHIFT 0x10
+#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q_MASK 0x20000
+#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q__SHIFT 0x11
+#define VGT_DEBUG_REG27__last_indx_of_vsprim_MASK 0x40000
+#define VGT_DEBUG_REG27__last_indx_of_vsprim__SHIFT 0x12
+#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q_MASK 0x80000
+#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q__SHIFT 0x13
+#define VGT_DEBUG_REG27__gsc_indx_count_p0_q_MASK 0x7ff00000
+#define VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT 0x14
+#define VGT_DEBUG_REG27__last_vsprim_of_gsprim_MASK 0x80000000
+#define VGT_DEBUG_REG27__last_vsprim_of_gsprim__SHIFT 0x1f
+#define VGT_DEBUG_REG28__con_state_q_MASK 0xf
+#define VGT_DEBUG_REG28__con_state_q__SHIFT 0x0
+#define VGT_DEBUG_REG28__second_cycle_q_MASK 0x10
+#define VGT_DEBUG_REG28__second_cycle_q__SHIFT 0x4
+#define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x20
+#define VGT_DEBUG_REG28__process_tri_middle_p0_q__SHIFT 0x5
+#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q_MASK 0x40
+#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
+#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q_MASK 0x80
+#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q__SHIFT 0x7
+#define VGT_DEBUG_REG28__pipe0_patch_dr_MASK 0x100
+#define VGT_DEBUG_REG28__pipe0_patch_dr__SHIFT 0x8
+#define VGT_DEBUG_REG28__pipe0_edge_dr_MASK 0x200
+#define VGT_DEBUG_REG28__pipe0_edge_dr__SHIFT 0x9
+#define VGT_DEBUG_REG28__pipe1_dr_MASK 0x400
+#define VGT_DEBUG_REG28__pipe1_dr__SHIFT 0xa
+#define VGT_DEBUG_REG28__pipe0_patch_rtr_MASK 0x800
+#define VGT_DEBUG_REG28__pipe0_patch_rtr__SHIFT 0xb
+#define VGT_DEBUG_REG28__pipe0_edge_rtr_MASK 0x1000
+#define VGT_DEBUG_REG28__pipe0_edge_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG28__pipe1_rtr_MASK 0x2000
+#define VGT_DEBUG_REG28__pipe1_rtr__SHIFT 0xd
+#define VGT_DEBUG_REG28__outer_parity_p0_q_MASK 0x4000
+#define VGT_DEBUG_REG28__outer_parity_p0_q__SHIFT 0xe
+#define VGT_DEBUG_REG28__parallel_parity_p0_q_MASK 0x8000
+#define VGT_DEBUG_REG28__parallel_parity_p0_q__SHIFT 0xf
+#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q_MASK 0x10000
+#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q__SHIFT 0x10
+#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q_MASK 0x20000
+#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q__SHIFT 0x11
+#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q_MASK 0x40000
+#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q__SHIFT 0x12
+#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1_MASK 0x80000
+#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1__SHIFT 0x13
+#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1_MASK 0x100000
+#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT 0x14
+#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q_MASK 0x200000
+#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
+#define VGT_DEBUG_REG28__advance_outer_point_p1_MASK 0x400000
+#define VGT_DEBUG_REG28__advance_outer_point_p1__SHIFT 0x16
+#define VGT_DEBUG_REG28__advance_inner_point_p1_MASK 0x800000
+#define VGT_DEBUG_REG28__advance_inner_point_p1__SHIFT 0x17
+#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q_MASK 0x1000000
+#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q__SHIFT 0x18
+#define VGT_DEBUG_REG28__pipe1_outer1_rtr_MASK 0x2000000
+#define VGT_DEBUG_REG28__pipe1_outer1_rtr__SHIFT 0x19
+#define VGT_DEBUG_REG28__pipe1_outer2_rtr_MASK 0x4000000
+#define VGT_DEBUG_REG28__pipe1_outer2_rtr__SHIFT 0x1a
+#define VGT_DEBUG_REG28__pipe1_inner1_rtr_MASK 0x8000000
+#define VGT_DEBUG_REG28__pipe1_inner1_rtr__SHIFT 0x1b
+#define VGT_DEBUG_REG28__pipe1_inner2_rtr_MASK 0x10000000
+#define VGT_DEBUG_REG28__pipe1_inner2_rtr__SHIFT 0x1c
+#define VGT_DEBUG_REG28__pipe1_patch_rtr_MASK 0x20000000
+#define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x1d
+#define VGT_DEBUG_REG28__pipe1_edge_rtr_MASK 0x40000000
+#define VGT_DEBUG_REG28__pipe1_edge_rtr__SHIFT 0x1e
+#define VGT_DEBUG_REG28__use_stored_inner_q_ring2_MASK 0x80000000
+#define VGT_DEBUG_REG28__use_stored_inner_q_ring2__SHIFT 0x1f
+#define VGT_DEBUG_REG29__con_state_q_MASK 0xf
+#define VGT_DEBUG_REG29__con_state_q__SHIFT 0x0
+#define VGT_DEBUG_REG29__second_cycle_q_MASK 0x10
+#define VGT_DEBUG_REG29__second_cycle_q__SHIFT 0x4
+#define VGT_DEBUG_REG29__process_tri_middle_p0_q_MASK 0x20
+#define VGT_DEBUG_REG29__process_tri_middle_p0_q__SHIFT 0x5
+#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q_MASK 0x40
+#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
+#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q_MASK 0x80
+#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q__SHIFT 0x7
+#define VGT_DEBUG_REG29__pipe0_patch_dr_MASK 0x100
+#define VGT_DEBUG_REG29__pipe0_patch_dr__SHIFT 0x8
+#define VGT_DEBUG_REG29__pipe0_edge_dr_MASK 0x200
+#define VGT_DEBUG_REG29__pipe0_edge_dr__SHIFT 0x9
+#define VGT_DEBUG_REG29__pipe1_dr_MASK 0x400
+#define VGT_DEBUG_REG29__pipe1_dr__SHIFT 0xa
+#define VGT_DEBUG_REG29__pipe0_patch_rtr_MASK 0x800
+#define VGT_DEBUG_REG29__pipe0_patch_rtr__SHIFT 0xb
+#define VGT_DEBUG_REG29__pipe0_edge_rtr_MASK 0x1000
+#define VGT_DEBUG_REG29__pipe0_edge_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG29__pipe1_rtr_MASK 0x2000
+#define VGT_DEBUG_REG29__pipe1_rtr__SHIFT 0xd
+#define VGT_DEBUG_REG29__outer_parity_p0_q_MASK 0x4000
+#define VGT_DEBUG_REG29__outer_parity_p0_q__SHIFT 0xe
+#define VGT_DEBUG_REG29__parallel_parity_p0_q_MASK 0x8000
+#define VGT_DEBUG_REG29__parallel_parity_p0_q__SHIFT 0xf
+#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q_MASK 0x10000
+#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q__SHIFT 0x10
+#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q_MASK 0x20000
+#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q__SHIFT 0x11
+#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q_MASK 0x40000
+#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q__SHIFT 0x12
+#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1_MASK 0x80000
+#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1__SHIFT 0x13
+#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1_MASK 0x100000
+#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT 0x14
+#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q_MASK 0x200000
+#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
+#define VGT_DEBUG_REG29__advance_outer_point_p1_MASK 0x400000
+#define VGT_DEBUG_REG29__advance_outer_point_p1__SHIFT 0x16
+#define VGT_DEBUG_REG29__advance_inner_point_p1_MASK 0x800000
+#define VGT_DEBUG_REG29__advance_inner_point_p1__SHIFT 0x17
+#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q_MASK 0x1000000
+#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q__SHIFT 0x18
+#define VGT_DEBUG_REG29__pipe1_outer1_rtr_MASK 0x2000000
+#define VGT_DEBUG_REG29__pipe1_outer1_rtr__SHIFT 0x19
+#define VGT_DEBUG_REG29__pipe1_outer2_rtr_MASK 0x4000000
+#define VGT_DEBUG_REG29__pipe1_outer2_rtr__SHIFT 0x1a
+#define VGT_DEBUG_REG29__pipe1_inner1_rtr_MASK 0x8000000
+#define VGT_DEBUG_REG29__pipe1_inner1_rtr__SHIFT 0x1b
+#define VGT_DEBUG_REG29__pipe1_inner2_rtr_MASK 0x10000000
+#define VGT_DEBUG_REG29__pipe1_inner2_rtr__SHIFT 0x1c
+#define VGT_DEBUG_REG29__pipe1_patch_rtr_MASK 0x20000000
+#define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x1d
+#define VGT_DEBUG_REG29__pipe1_edge_rtr_MASK 0x40000000
+#define VGT_DEBUG_REG29__pipe1_edge_rtr__SHIFT 0x1e
+#define VGT_DEBUG_REG29__use_stored_inner_q_ring3_MASK 0x80000000
+#define VGT_DEBUG_REG29__use_stored_inner_q_ring3__SHIFT 0x1f
+#define VGT_DEBUG_REG31__pipe0_dr_MASK 0x1
+#define VGT_DEBUG_REG31__pipe0_dr__SHIFT 0x0
+#define VGT_DEBUG_REG31__pipe0_rtr_MASK 0x2
+#define VGT_DEBUG_REG31__pipe0_rtr__SHIFT 0x1
+#define VGT_DEBUG_REG31__pipe1_outer_dr_MASK 0x4
+#define VGT_DEBUG_REG31__pipe1_outer_dr__SHIFT 0x2
+#define VGT_DEBUG_REG31__pipe1_inner_dr_MASK 0x8
+#define VGT_DEBUG_REG31__pipe1_inner_dr__SHIFT 0x3
+#define VGT_DEBUG_REG31__pipe2_outer_dr_MASK 0x10
+#define VGT_DEBUG_REG31__pipe2_outer_dr__SHIFT 0x4
+#define VGT_DEBUG_REG31__pipe2_inner_dr_MASK 0x20
+#define VGT_DEBUG_REG31__pipe2_inner_dr__SHIFT 0x5
+#define VGT_DEBUG_REG31__pipe3_outer_dr_MASK 0x40
+#define VGT_DEBUG_REG31__pipe3_outer_dr__SHIFT 0x6
+#define VGT_DEBUG_REG31__pipe3_inner_dr_MASK 0x80
+#define VGT_DEBUG_REG31__pipe3_inner_dr__SHIFT 0x7
+#define VGT_DEBUG_REG31__pipe4_outer_dr_MASK 0x100
+#define VGT_DEBUG_REG31__pipe4_outer_dr__SHIFT 0x8
+#define VGT_DEBUG_REG31__pipe4_inner_dr_MASK 0x200
+#define VGT_DEBUG_REG31__pipe4_inner_dr__SHIFT 0x9
+#define VGT_DEBUG_REG31__pipe5_outer_dr_MASK 0x400
+#define VGT_DEBUG_REG31__pipe5_outer_dr__SHIFT 0xa
+#define VGT_DEBUG_REG31__pipe5_inner_dr_MASK 0x800
+#define VGT_DEBUG_REG31__pipe5_inner_dr__SHIFT 0xb
+#define VGT_DEBUG_REG31__pipe2_outer_rtr_MASK 0x1000
+#define VGT_DEBUG_REG31__pipe2_outer_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG31__pipe2_inner_rtr_MASK 0x2000
+#define VGT_DEBUG_REG31__pipe2_inner_rtr__SHIFT 0xd
+#define VGT_DEBUG_REG31__pipe3_outer_rtr_MASK 0x4000
+#define VGT_DEBUG_REG31__pipe3_outer_rtr__SHIFT 0xe
+#define VGT_DEBUG_REG31__pipe3_inner_rtr_MASK 0x8000
+#define VGT_DEBUG_REG31__pipe3_inner_rtr__SHIFT 0xf
+#define VGT_DEBUG_REG31__pipe4_outer_rtr_MASK 0x10000
+#define VGT_DEBUG_REG31__pipe4_outer_rtr__SHIFT 0x10
+#define VGT_DEBUG_REG31__pipe4_inner_rtr_MASK 0x20000
+#define VGT_DEBUG_REG31__pipe4_inner_rtr__SHIFT 0x11
+#define VGT_DEBUG_REG31__pipe5_outer_rtr_MASK 0x40000
+#define VGT_DEBUG_REG31__pipe5_outer_rtr__SHIFT 0x12
+#define VGT_DEBUG_REG31__pipe5_inner_rtr_MASK 0x80000
+#define VGT_DEBUG_REG31__pipe5_inner_rtr__SHIFT 0x13
+#define VGT_DEBUG_REG31__pg_con_outer_point1_rts_MASK 0x100000
+#define VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT 0x14
+#define VGT_DEBUG_REG31__pg_con_outer_point2_rts_MASK 0x200000
+#define VGT_DEBUG_REG31__pg_con_outer_point2_rts__SHIFT 0x15
+#define VGT_DEBUG_REG31__pg_con_inner_point1_rts_MASK 0x400000
+#define VGT_DEBUG_REG31__pg_con_inner_point1_rts__SHIFT 0x16
+#define VGT_DEBUG_REG31__pg_con_inner_point2_rts_MASK 0x800000
+#define VGT_DEBUG_REG31__pg_con_inner_point2_rts__SHIFT 0x17
+#define VGT_DEBUG_REG31__pg_patch_fifo_empty_MASK 0x1000000
+#define VGT_DEBUG_REG31__pg_patch_fifo_empty__SHIFT 0x18
+#define VGT_DEBUG_REG31__pg_edge_fifo_empty_MASK 0x2000000
+#define VGT_DEBUG_REG31__pg_edge_fifo_empty__SHIFT 0x19
+#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty_MASK 0x4000000
+#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty__SHIFT 0x1a
+#define VGT_DEBUG_REG31__pg_patch_fifo_full_MASK 0x8000000
+#define VGT_DEBUG_REG31__pg_patch_fifo_full__SHIFT 0x1b
+#define VGT_DEBUG_REG31__pg_edge_fifo_full_MASK 0x10000000
+#define VGT_DEBUG_REG31__pg_edge_fifo_full__SHIFT 0x1c
+#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full_MASK 0x20000000
+#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT 0x1d
+#define VGT_DEBUG_REG31__outer_ring_done_q_MASK 0x40000000
+#define VGT_DEBUG_REG31__outer_ring_done_q__SHIFT 0x1e
+#define VGT_DEBUG_REG31__inner_ring_done_q_MASK 0x80000000
+#define VGT_DEBUG_REG31__inner_ring_done_q__SHIFT 0x1f
+#define VGT_DEBUG_REG32__first_ring_of_patch_MASK 0x1
+#define VGT_DEBUG_REG32__first_ring_of_patch__SHIFT 0x0
+#define VGT_DEBUG_REG32__last_ring_of_patch_MASK 0x2
+#define VGT_DEBUG_REG32__last_ring_of_patch__SHIFT 0x1
+#define VGT_DEBUG_REG32__last_edge_of_outer_ring_MASK 0x4
+#define VGT_DEBUG_REG32__last_edge_of_outer_ring__SHIFT 0x2
+#define VGT_DEBUG_REG32__last_point_of_outer_edge_MASK 0x8
+#define VGT_DEBUG_REG32__last_point_of_outer_edge__SHIFT 0x3
+#define VGT_DEBUG_REG32__last_edge_of_inner_ring_MASK 0x10
+#define VGT_DEBUG_REG32__last_edge_of_inner_ring__SHIFT 0x4
+#define VGT_DEBUG_REG32__last_point_of_inner_edge_MASK 0x20
+#define VGT_DEBUG_REG32__last_point_of_inner_edge__SHIFT 0x5
+#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q_MASK 0x40
+#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q__SHIFT 0x6
+#define VGT_DEBUG_REG32__event_null_special_p0_q_MASK 0x80
+#define VGT_DEBUG_REG32__event_null_special_p0_q__SHIFT 0x7
+#define VGT_DEBUG_REG32__event_flag_p5_q_MASK 0x100
+#define VGT_DEBUG_REG32__event_flag_p5_q__SHIFT 0x8
+#define VGT_DEBUG_REG32__first_point_of_patch_p5_q_MASK 0x200
+#define VGT_DEBUG_REG32__first_point_of_patch_p5_q__SHIFT 0x9
+#define VGT_DEBUG_REG32__first_point_of_edge_p5_q_MASK 0x400
+#define VGT_DEBUG_REG32__first_point_of_edge_p5_q__SHIFT 0xa
+#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q_MASK 0x800
+#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q__SHIFT 0xb
+#define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x3000
+#define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0xc
+#define VGT_DEBUG_REG32__pipe5_inner3_rtr_MASK 0x4000
+#define VGT_DEBUG_REG32__pipe5_inner3_rtr__SHIFT 0xe
+#define VGT_DEBUG_REG32__pipe5_inner2_rtr_MASK 0x8000
+#define VGT_DEBUG_REG32__pipe5_inner2_rtr__SHIFT 0xf
+#define VGT_DEBUG_REG32__pg_edge_fifo3_full_MASK 0x10000
+#define VGT_DEBUG_REG32__pg_edge_fifo3_full__SHIFT 0x10
+#define VGT_DEBUG_REG32__pg_edge_fifo2_full_MASK 0x20000
+#define VGT_DEBUG_REG32__pg_edge_fifo2_full__SHIFT 0x11
+#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full_MASK 0x40000
+#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full__SHIFT 0x12
+#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full_MASK 0x80000
+#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full__SHIFT 0x13
+#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full_MASK 0x100000
+#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT 0x14
+#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full_MASK 0x200000
+#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full__SHIFT 0x15
+#define VGT_DEBUG_REG32__pg_inner_point_fifo_full_MASK 0x400000
+#define VGT_DEBUG_REG32__pg_inner_point_fifo_full__SHIFT 0x16
+#define VGT_DEBUG_REG32__pg_outer_point_fifo_full_MASK 0x800000
+#define VGT_DEBUG_REG32__pg_outer_point_fifo_full__SHIFT 0x17
+#define VGT_DEBUG_REG32__inner2_fifos_rtr_MASK 0x1000000
+#define VGT_DEBUG_REG32__inner2_fifos_rtr__SHIFT 0x18
+#define VGT_DEBUG_REG32__inner_fifos_rtr_MASK 0x2000000
+#define VGT_DEBUG_REG32__inner_fifos_rtr__SHIFT 0x19
+#define VGT_DEBUG_REG32__outer_fifos_rtr_MASK 0x4000000
+#define VGT_DEBUG_REG32__outer_fifos_rtr__SHIFT 0x1a
+#define VGT_DEBUG_REG32__fifos_rtr_MASK 0x8000000
+#define VGT_DEBUG_REG32__fifos_rtr__SHIFT 0x1b
+#define VGT_DEBUG_REG32__SPARE_MASK 0xf0000000
+#define VGT_DEBUG_REG32__SPARE__SHIFT 0x1c
+#define VGT_DEBUG_REG33__pipe0_patch_dr_MASK 0x1
+#define VGT_DEBUG_REG33__pipe0_patch_dr__SHIFT 0x0
+#define VGT_DEBUG_REG33__ring3_pipe1_dr_MASK 0x2
+#define VGT_DEBUG_REG33__ring3_pipe1_dr__SHIFT 0x1
+#define VGT_DEBUG_REG33__pipe1_dr_MASK 0x4
+#define VGT_DEBUG_REG33__pipe1_dr__SHIFT 0x2
+#define VGT_DEBUG_REG33__pipe2_dr_MASK 0x8
+#define VGT_DEBUG_REG33__pipe2_dr__SHIFT 0x3
+#define VGT_DEBUG_REG33__pipe0_patch_rtr_MASK 0x10
+#define VGT_DEBUG_REG33__pipe0_patch_rtr__SHIFT 0x4
+#define VGT_DEBUG_REG33__ring2_pipe1_dr_MASK 0x20
+#define VGT_DEBUG_REG33__ring2_pipe1_dr__SHIFT 0x5
+#define VGT_DEBUG_REG33__ring1_pipe1_dr_MASK 0x40
+#define VGT_DEBUG_REG33__ring1_pipe1_dr__SHIFT 0x6
+#define VGT_DEBUG_REG33__pipe2_rtr_MASK 0x80
+#define VGT_DEBUG_REG33__pipe2_rtr__SHIFT 0x7
+#define VGT_DEBUG_REG33__pipe3_dr_MASK 0x100
+#define VGT_DEBUG_REG33__pipe3_dr__SHIFT 0x8
+#define VGT_DEBUG_REG33__pipe3_rtr_MASK 0x200
+#define VGT_DEBUG_REG33__pipe3_rtr__SHIFT 0x9
+#define VGT_DEBUG_REG33__ring2_in_sync_q_MASK 0x400
+#define VGT_DEBUG_REG33__ring2_in_sync_q__SHIFT 0xa
+#define VGT_DEBUG_REG33__ring1_in_sync_q_MASK 0x800
+#define VGT_DEBUG_REG33__ring1_in_sync_q__SHIFT 0xb
+#define VGT_DEBUG_REG33__pipe1_patch_rtr_MASK 0x1000
+#define VGT_DEBUG_REG33__pipe1_patch_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG33__ring3_in_sync_q_MASK 0x2000
+#define VGT_DEBUG_REG33__ring3_in_sync_q__SHIFT 0xd
+#define VGT_DEBUG_REG33__tm_te11_event_rtr_MASK 0x4000
+#define VGT_DEBUG_REG33__tm_te11_event_rtr__SHIFT 0xe
+#define VGT_DEBUG_REG33__first_prim_of_patch_q_MASK 0x8000
+#define VGT_DEBUG_REG33__first_prim_of_patch_q__SHIFT 0xf
+#define VGT_DEBUG_REG33__con_prim_fifo_full_MASK 0x10000
+#define VGT_DEBUG_REG33__con_prim_fifo_full__SHIFT 0x10
+#define VGT_DEBUG_REG33__con_vert_fifo_full_MASK 0x20000
+#define VGT_DEBUG_REG33__con_vert_fifo_full__SHIFT 0x11
+#define VGT_DEBUG_REG33__con_prim_fifo_empty_MASK 0x40000
+#define VGT_DEBUG_REG33__con_prim_fifo_empty__SHIFT 0x12
+#define VGT_DEBUG_REG33__con_vert_fifo_empty_MASK 0x80000
+#define VGT_DEBUG_REG33__con_vert_fifo_empty__SHIFT 0x13
+#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q_MASK 0x100000
+#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT 0x14
+#define VGT_DEBUG_REG33__ring3_valid_p2_MASK 0x200000
+#define VGT_DEBUG_REG33__ring3_valid_p2__SHIFT 0x15
+#define VGT_DEBUG_REG33__ring2_valid_p2_MASK 0x400000
+#define VGT_DEBUG_REG33__ring2_valid_p2__SHIFT 0x16
+#define VGT_DEBUG_REG33__ring1_valid_p2_MASK 0x800000
+#define VGT_DEBUG_REG33__ring1_valid_p2__SHIFT 0x17
+#define VGT_DEBUG_REG33__tess_type_p0_q_MASK 0x3000000
+#define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x18
+#define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0xc000000
+#define VGT_DEBUG_REG33__tess_topology_p0_q__SHIFT 0x1a
+#define VGT_DEBUG_REG33__te11_out_vert_gs_en_MASK 0x10000000
+#define VGT_DEBUG_REG33__te11_out_vert_gs_en__SHIFT 0x1c
+#define VGT_DEBUG_REG33__con_ring3_busy_MASK 0x20000000
+#define VGT_DEBUG_REG33__con_ring3_busy__SHIFT 0x1d
+#define VGT_DEBUG_REG33__con_ring2_busy_MASK 0x40000000
+#define VGT_DEBUG_REG33__con_ring2_busy__SHIFT 0x1e
+#define VGT_DEBUG_REG33__con_ring1_busy_MASK 0x80000000
+#define VGT_DEBUG_REG33__con_ring1_busy__SHIFT 0x1f
+#define VGT_DEBUG_REG34__con_state_q_MASK 0xf
+#define VGT_DEBUG_REG34__con_state_q__SHIFT 0x0
+#define VGT_DEBUG_REG34__second_cycle_q_MASK 0x10
+#define VGT_DEBUG_REG34__second_cycle_q__SHIFT 0x4
+#define VGT_DEBUG_REG34__process_tri_middle_p0_q_MASK 0x20
+#define VGT_DEBUG_REG34__process_tri_middle_p0_q__SHIFT 0x5
+#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q_MASK 0x40
+#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
+#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q_MASK 0x80
+#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q__SHIFT 0x7
+#define VGT_DEBUG_REG34__pipe0_patch_dr_MASK 0x100
+#define VGT_DEBUG_REG34__pipe0_patch_dr__SHIFT 0x8
+#define VGT_DEBUG_REG34__pipe0_edge_dr_MASK 0x200
+#define VGT_DEBUG_REG34__pipe0_edge_dr__SHIFT 0x9
+#define VGT_DEBUG_REG34__pipe1_dr_MASK 0x400
+#define VGT_DEBUG_REG34__pipe1_dr__SHIFT 0xa
+#define VGT_DEBUG_REG34__pipe0_patch_rtr_MASK 0x800
+#define VGT_DEBUG_REG34__pipe0_patch_rtr__SHIFT 0xb
+#define VGT_DEBUG_REG34__pipe0_edge_rtr_MASK 0x1000
+#define VGT_DEBUG_REG34__pipe0_edge_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG34__pipe1_rtr_MASK 0x2000
+#define VGT_DEBUG_REG34__pipe1_rtr__SHIFT 0xd
+#define VGT_DEBUG_REG34__outer_parity_p0_q_MASK 0x4000
+#define VGT_DEBUG_REG34__outer_parity_p0_q__SHIFT 0xe
+#define VGT_DEBUG_REG34__parallel_parity_p0_q_MASK 0x8000
+#define VGT_DEBUG_REG34__parallel_parity_p0_q__SHIFT 0xf
+#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q_MASK 0x10000
+#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q__SHIFT 0x10
+#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q_MASK 0x20000
+#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q__SHIFT 0x11
+#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q_MASK 0x40000
+#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q__SHIFT 0x12
+#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1_MASK 0x80000
+#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1__SHIFT 0x13
+#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1_MASK 0x100000
+#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT 0x14
+#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q_MASK 0x200000
+#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
+#define VGT_DEBUG_REG34__advance_outer_point_p1_MASK 0x400000
+#define VGT_DEBUG_REG34__advance_outer_point_p1__SHIFT 0x16
+#define VGT_DEBUG_REG34__advance_inner_point_p1_MASK 0x800000
+#define VGT_DEBUG_REG34__advance_inner_point_p1__SHIFT 0x17
+#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q_MASK 0x1000000
+#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q__SHIFT 0x18
+#define VGT_DEBUG_REG34__pipe1_outer1_rtr_MASK 0x2000000
+#define VGT_DEBUG_REG34__pipe1_outer1_rtr__SHIFT 0x19
+#define VGT_DEBUG_REG34__pipe1_outer2_rtr_MASK 0x4000000
+#define VGT_DEBUG_REG34__pipe1_outer2_rtr__SHIFT 0x1a
+#define VGT_DEBUG_REG34__pipe1_inner1_rtr_MASK 0x8000000
+#define VGT_DEBUG_REG34__pipe1_inner1_rtr__SHIFT 0x1b
+#define VGT_DEBUG_REG34__pipe1_inner2_rtr_MASK 0x10000000
+#define VGT_DEBUG_REG34__pipe1_inner2_rtr__SHIFT 0x1c
+#define VGT_DEBUG_REG34__pipe1_patch_rtr_MASK 0x20000000
+#define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT 0x1d
+#define VGT_DEBUG_REG34__pipe1_edge_rtr_MASK 0x40000000
+#define VGT_DEBUG_REG34__pipe1_edge_rtr__SHIFT 0x1e
+#define VGT_DEBUG_REG34__use_stored_inner_q_ring1_MASK 0x80000000
+#define VGT_DEBUG_REG34__use_stored_inner_q_ring1__SHIFT 0x1f
+#define VGT_DEBUG_REG36__VGT_PA_clipp_eop_MASK 0xffffffff
+#define VGT_DEBUG_REG36__VGT_PA_clipp_eop__SHIFT 0x0
+#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0xff
+#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
+#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
+#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
+#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
+#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
+#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
+#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
+#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
+#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
+#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
+#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
+#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
+#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
+#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xffffffff
+#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0
+#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xffffffff
+#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0
+#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x1
+#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK 0x2
+#define DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT 0x1
+#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc
+#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x2
+#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x10
+#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
+#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
+#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
+#define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xffffffc0
+#define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x6
+#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0xffff
+#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xffff0000
+#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
+#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_SQ_CTRL2__UNUSED_0_MASK 0xc000
+#define DIDT_SQ_CTRL2__UNUSED_0__SHIFT 0xe
+#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
+#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_SQ_CTRL2__UNUSED_1_MASK 0x4000000
+#define DIDT_SQ_CTRL2__UNUSED_1__SHIFT 0x1a
+#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
+#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_SQ_CTRL2__UNUSED_2_MASK 0x80000000
+#define DIDT_SQ_CTRL2__UNUSED_2__SHIFT 0x1f
+#define DIDT_SQ_CTRL_OCP__UNUSED_0_MASK 0xffff
+#define DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT 0x0
+#define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
+#define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
+#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0xff
+#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0xff00
+#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0xff0000
+#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xff000000
+#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0xff
+#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0xff00
+#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0xff0000
+#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xff000000
+#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0xff
+#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0xff00
+#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0xff0000
+#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xff000000
+#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x1
+#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_DB_CTRL0__USE_REF_CLOCK_MASK 0x2
+#define DIDT_DB_CTRL0__USE_REF_CLOCK__SHIFT 0x1
+#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0xc
+#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x2
+#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x10
+#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
+#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
+#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
+#define DIDT_DB_CTRL0__UNUSED_0_MASK 0xffffffc0
+#define DIDT_DB_CTRL0__UNUSED_0__SHIFT 0x6
+#define DIDT_DB_CTRL1__MIN_POWER_MASK 0xffff
+#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xffff0000
+#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
+#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_DB_CTRL2__UNUSED_0_MASK 0xc000
+#define DIDT_DB_CTRL2__UNUSED_0__SHIFT 0xe
+#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
+#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_DB_CTRL2__UNUSED_1_MASK 0x4000000
+#define DIDT_DB_CTRL2__UNUSED_1__SHIFT 0x1a
+#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
+#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_DB_CTRL2__UNUSED_2_MASK 0x80000000
+#define DIDT_DB_CTRL2__UNUSED_2__SHIFT 0x1f
+#define DIDT_DB_CTRL_OCP__UNUSED_0_MASK 0xffff
+#define DIDT_DB_CTRL_OCP__UNUSED_0__SHIFT 0x0
+#define DIDT_DB_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
+#define DIDT_DB_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
+#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0xff
+#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0xff00
+#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0xff0000
+#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xff000000
+#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0xff
+#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0xff00
+#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0xff0000
+#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xff000000
+#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0xff
+#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0xff00
+#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0xff0000
+#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xff000000
+#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x1
+#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_TD_CTRL0__USE_REF_CLOCK_MASK 0x2
+#define DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT 0x1
+#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0xc
+#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x2
+#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x10
+#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
+#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
+#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
+#define DIDT_TD_CTRL0__UNUSED_0_MASK 0xffffffc0
+#define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x6
+#define DIDT_TD_CTRL1__MIN_POWER_MASK 0xffff
+#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xffff0000
+#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
+#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_TD_CTRL2__UNUSED_0_MASK 0xc000
+#define DIDT_TD_CTRL2__UNUSED_0__SHIFT 0xe
+#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
+#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_TD_CTRL2__UNUSED_1_MASK 0x4000000
+#define DIDT_TD_CTRL2__UNUSED_1__SHIFT 0x1a
+#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
+#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_TD_CTRL2__UNUSED_2_MASK 0x80000000
+#define DIDT_TD_CTRL2__UNUSED_2__SHIFT 0x1f
+#define DIDT_TD_CTRL_OCP__UNUSED_0_MASK 0xffff
+#define DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT 0x0
+#define DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
+#define DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
+#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0xff
+#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0xff00
+#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0xff0000
+#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xff000000
+#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0xff
+#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0xff00
+#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0xff0000
+#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xff000000
+#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0xff
+#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0xff00
+#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0xff0000
+#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xff000000
+#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x1
+#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK 0x2
+#define DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT 0x1
+#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0xc
+#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x2
+#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x10
+#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
+#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
+#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
+#define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xffffffc0
+#define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x6
+#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0xffff
+#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xffff0000
+#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
+#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_TCP_CTRL2__UNUSED_0_MASK 0xc000
+#define DIDT_TCP_CTRL2__UNUSED_0__SHIFT 0xe
+#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
+#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_TCP_CTRL2__UNUSED_1_MASK 0x4000000
+#define DIDT_TCP_CTRL2__UNUSED_1__SHIFT 0x1a
+#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
+#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_TCP_CTRL2__UNUSED_2_MASK 0x80000000
+#define DIDT_TCP_CTRL2__UNUSED_2__SHIFT 0x1f
+#define DIDT_TCP_CTRL_OCP__UNUSED_0_MASK 0xffff
+#define DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT 0x0
+#define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
+#define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
+#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0xff
+#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0xff00
+#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0xff0000
+#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xff000000
+#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0xff
+#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0xff00
+#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0xff0000
+#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xff000000
+#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0xff
+#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0xff00
+#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0xff0000
+#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xff000000
+#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK 0x1
+#define DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_DBR_CTRL0__USE_REF_CLOCK_MASK 0x2
+#define DIDT_DBR_CTRL0__USE_REF_CLOCK__SHIFT 0x1
+#define DIDT_DBR_CTRL0__PHASE_OFFSET_MASK 0xc
+#define DIDT_DBR_CTRL0__PHASE_OFFSET__SHIFT 0x2
+#define DIDT_DBR_CTRL0__DIDT_CTRL_RST_MASK 0x10
+#define DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
+#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
+#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
+#define DIDT_DBR_CTRL0__UNUSED_0_MASK 0xffffffc0
+#define DIDT_DBR_CTRL0__UNUSED_0__SHIFT 0x6
+#define DIDT_DBR_CTRL1__MIN_POWER_MASK 0xffff
+#define DIDT_DBR_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_DBR_CTRL1__MAX_POWER_MASK 0xffff0000
+#define DIDT_DBR_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_DBR_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
+#define DIDT_DBR_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_DBR_CTRL2__UNUSED_0_MASK 0xc000
+#define DIDT_DBR_CTRL2__UNUSED_0__SHIFT 0xe
+#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
+#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_DBR_CTRL2__UNUSED_1_MASK 0x4000000
+#define DIDT_DBR_CTRL2__UNUSED_1__SHIFT 0x1a
+#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
+#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_DBR_CTRL2__UNUSED_2_MASK 0x80000000
+#define DIDT_DBR_CTRL2__UNUSED_2__SHIFT 0x1f
+#define DIDT_DBR_CTRL_OCP__UNUSED_0_MASK 0xffff
+#define DIDT_DBR_CTRL_OCP__UNUSED_0__SHIFT 0x0
+#define DIDT_DBR_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
+#define DIDT_DBR_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
+#define DIDT_DBR_WEIGHT0_3__WEIGHT0_MASK 0xff
+#define DIDT_DBR_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_DBR_WEIGHT0_3__WEIGHT1_MASK 0xff00
+#define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_DBR_WEIGHT0_3__WEIGHT2_MASK 0xff0000
+#define DIDT_DBR_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_DBR_WEIGHT0_3__WEIGHT3_MASK 0xff000000
+#define DIDT_DBR_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_DBR_WEIGHT4_7__WEIGHT4_MASK 0xff
+#define DIDT_DBR_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_DBR_WEIGHT4_7__WEIGHT5_MASK 0xff00
+#define DIDT_DBR_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_DBR_WEIGHT4_7__WEIGHT6_MASK 0xff0000
+#define DIDT_DBR_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_DBR_WEIGHT4_7__WEIGHT7_MASK 0xff000000
+#define DIDT_DBR_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_DBR_WEIGHT8_11__WEIGHT8_MASK 0xff
+#define DIDT_DBR_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_DBR_WEIGHT8_11__WEIGHT9_MASK 0xff00
+#define DIDT_DBR_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_DBR_WEIGHT8_11__WEIGHT10_MASK 0xff0000
+#define DIDT_DBR_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_DBR_WEIGHT8_11__WEIGHT11_MASK 0xff000000
+#define DIDT_DBR_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+
+#endif /* GFX_8_0_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_d.h
new file mode 100644
index 000000000000..1940e7a7c979
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_d.h
@@ -0,0 +1,657 @@
+/*
+ * GMC_7_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GMC_7_0_D_H
+#define GMC_7_0_D_H
+
+#define mmMC_CONFIG 0x800
+#define mmMC_ARB_AGE_CNTL 0x9bf
+#define mmMC_ARB_RET_CREDITS2 0x9c0
+#define mmMC_ARB_FED_CNTL 0x9c1
+#define mmMC_ARB_GECC2_STATUS 0x9c2
+#define mmMC_ARB_GECC2_MISC 0x9c3
+#define mmMC_ARB_GECC2_DEBUG 0x9c4
+#define mmMC_ARB_GECC2_DEBUG2 0x9c5
+#define mmMC_ARB_GECC2 0x9c9
+#define mmMC_ARB_GECC2_CLI 0x9ca
+#define mmMC_ARB_ADDR_SWIZ0 0x9cb
+#define mmMC_ARB_ADDR_SWIZ1 0x9cc
+#define mmMC_ARB_MISC3 0x9cd
+#define mmMC_ARB_WCDR_2 0x9ce
+#define mmMC_ARB_RTT_DATA 0x9cf
+#define mmMC_ARB_RTT_CNTL0 0x9d0
+#define mmMC_ARB_RTT_CNTL1 0x9d1
+#define mmMC_ARB_RTT_CNTL2 0x9d2
+#define mmMC_ARB_RTT_DEBUG 0x9d3
+#define mmMC_ARB_CAC_CNTL 0x9d4
+#define mmMC_ARB_MISC2 0x9d5
+#define mmMC_ARB_MISC 0x9d6
+#define mmMC_ARB_BANKMAP 0x9d7
+#define mmMC_ARB_RAMCFG 0x9d8
+#define mmMC_ARB_POP 0x9d9
+#define mmMC_ARB_MINCLKS 0x9da
+#define mmMC_ARB_SQM_CNTL 0x9db
+#define mmMC_ARB_ADDR_HASH 0x9dc
+#define mmMC_ARB_DRAM_TIMING 0x9dd
+#define mmMC_ARB_DRAM_TIMING2 0x9de
+#define mmMC_ARB_WTM_CNTL_RD 0x9df
+#define mmMC_ARB_WTM_CNTL_WR 0x9e0
+#define mmMC_ARB_WTM_GRPWT_RD 0x9e1
+#define mmMC_ARB_WTM_GRPWT_WR 0x9e2
+#define mmMC_ARB_TM_CNTL_RD 0x9e3
+#define mmMC_ARB_TM_CNTL_WR 0x9e4
+#define mmMC_ARB_LAZY0_RD 0x9e5
+#define mmMC_ARB_LAZY0_WR 0x9e6
+#define mmMC_ARB_LAZY1_RD 0x9e7
+#define mmMC_ARB_LAZY1_WR 0x9e8
+#define mmMC_ARB_AGE_RD 0x9e9
+#define mmMC_ARB_AGE_WR 0x9ea
+#define mmMC_ARB_RFSH_CNTL 0x9eb
+#define mmMC_ARB_RFSH_RATE 0x9ec
+#define mmMC_ARB_PM_CNTL 0x9ed
+#define mmMC_ARB_GDEC_RD_CNTL 0x9ee
+#define mmMC_ARB_GDEC_WR_CNTL 0x9ef
+#define mmMC_ARB_LM_RD 0x9f0
+#define mmMC_ARB_LM_WR 0x9f1
+#define mmMC_ARB_REMREQ 0x9f2
+#define mmMC_ARB_REPLAY 0x9f3
+#define mmMC_ARB_RET_CREDITS_RD 0x9f4
+#define mmMC_ARB_RET_CREDITS_WR 0x9f5
+#define mmMC_ARB_MAX_LAT_CID 0x9f6
+#define mmMC_ARB_MAX_LAT_RSLT0 0x9f7
+#define mmMC_ARB_MAX_LAT_RSLT1 0x9f8
+#define mmMC_ARB_SSM 0x9f9
+#define mmMC_ARB_CG 0x9fa
+#define mmMC_ARB_WCDR 0x9fb
+#define mmMC_ARB_DRAM_TIMING_1 0x9fc
+#define mmMC_ARB_BUSY_STATUS 0x9fd
+#define mmMC_ARB_DRAM_TIMING2_1 0x9ff
+#define mmMC_ARB_BURST_TIME 0xa02
+#define mmMC_CITF_XTRA_ENABLE 0x96d
+#define mmCC_MC_MAX_CHANNEL 0x96e
+#define mmMC_CG_CONFIG 0x96f
+#define mmMC_CITF_CNTL 0x970
+#define mmMC_CITF_CREDITS_VM 0x971
+#define mmMC_CITF_CREDITS_ARB_RD 0x972
+#define mmMC_CITF_CREDITS_ARB_WR 0x973
+#define mmMC_CITF_DAGB_CNTL 0x974
+#define mmMC_CITF_INT_CREDITS 0x975
+#define mmMC_CITF_RET_MODE 0x976
+#define mmMC_CITF_DAGB_DLY 0x977
+#define mmMC_RD_GRP_EXT 0x978
+#define mmMC_WR_GRP_EXT 0x979
+#define mmMC_CITF_REMREQ 0x97a
+#define mmMC_WR_TC0 0x97b
+#define mmMC_WR_TC1 0x97c
+#define mmMC_CITF_INT_CREDITS_WR 0x97d
+#define mmMC_CITF_WTM_RD_CNTL 0x97f
+#define mmMC_CITF_WTM_WR_CNTL 0x980
+#define mmMC_RD_CB 0x981
+#define mmMC_RD_DB 0x982
+#define mmMC_RD_TC0 0x983
+#define mmMC_RD_TC1 0x984
+#define mmMC_RD_HUB 0x985
+#define mmMC_WR_CB 0x986
+#define mmMC_WR_DB 0x987
+#define mmMC_WR_HUB 0x988
+#define mmMC_CITF_CREDITS_XBAR 0x989
+#define mmMC_RD_GRP_LCL 0x98a
+#define mmMC_WR_GRP_LCL 0x98b
+#define mmMC_CITF_PERF_MON_CNTL2 0x98e
+#define mmMC_CITF_PERF_MON_RSLT2 0x991
+#define mmMC_CITF_MISC_RD_CG 0x992
+#define mmMC_CITF_MISC_WR_CG 0x993
+#define mmMC_CITF_MISC_VM_CG 0x994
+#define mmMC_HUB_MISC_POWER 0x82d
+#define mmMC_HUB_MISC_HUB_CG 0x82e
+#define mmMC_HUB_MISC_VM_CG 0x82f
+#define mmMC_HUB_MISC_SIP_CG 0x830
+#define mmMC_HUB_MISC_DBG 0x831
+#define mmMC_HUB_MISC_STATUS 0x832
+#define mmMC_HUB_MISC_OVERRIDE 0x833
+#define mmMC_HUB_MISC_FRAMING 0x834
+#define mmMC_HUB_WDP_CNTL 0x835
+#define mmMC_HUB_WDP_ERR 0x836
+#define mmMC_HUB_WDP_BP 0x837
+#define mmMC_HUB_WDP_STATUS 0x838
+#define mmMC_HUB_RDREQ_STATUS 0x839
+#define mmMC_HUB_WRRET_STATUS 0x83a
+#define mmMC_HUB_RDREQ_CNTL 0x83b
+#define mmMC_HUB_WRRET_CNTL 0x83c
+#define mmMC_HUB_RDREQ_WTM_CNTL 0x83d
+#define mmMC_HUB_WDP_WTM_CNTL 0x83e
+#define mmMC_HUB_WDP_CREDITS 0x83f
+#define mmMC_HUB_WDP_MGPU2 0x840
+#define mmMC_HUB_WDP_GBL0 0x841
+#define mmMC_HUB_WDP_GBL1 0x842
+#define mmMC_HUB_WDP_MGPU 0x843
+#define mmMC_HUB_RDREQ_CREDITS 0x844
+#define mmMC_HUB_RDREQ_CREDITS2 0x845
+#define mmMC_HUB_SHARED_DAGB_DLY 0x846
+#define mmMC_HUB_MISC_IDLE_STATUS 0x847
+#define mmMC_HUB_RDREQ_DMIF_LIMIT 0x848
+#define mmMC_HUB_RDREQ_ACPG_LIMIT 0x849
+#define mmMC_HUB_WDP_SH2 0x84d
+#define mmMC_HUB_WDP_SH3 0x84e
+#define mmMC_HUB_RDREQ_IA0 0x84f
+#define mmMC_HUB_RDREQ_IA1 0x850
+#define mmMC_HUB_RDREQ_MCDW 0x851
+#define mmMC_HUB_RDREQ_MCDX 0x852
+#define mmMC_HUB_RDREQ_MCDY 0x853
+#define mmMC_HUB_RDREQ_MCDZ 0x854
+#define mmMC_HUB_RDREQ_SIP 0x855
+#define mmMC_HUB_RDREQ_GBL0 0x856
+#define mmMC_HUB_RDREQ_GBL1 0x857
+#define mmMC_HUB_RDREQ_SMU 0x858
+#define mmMC_HUB_RDREQ_CPG 0x859
+#define mmMC_HUB_RDREQ_SDMA0 0x85a
+#define mmMC_HUB_RDREQ_HDP 0x85b
+#define mmMC_HUB_RDREQ_SDMA1 0x85c
+#define mmMC_HUB_RDREQ_RLC 0x85d
+#define mmMC_HUB_RDREQ_SEM 0x85e
+#define mmMC_HUB_RDREQ_VCE 0x85f
+#define mmMC_HUB_RDREQ_UMC 0x860
+#define mmMC_HUB_RDREQ_UVD 0x861
+#define mmMC_HUB_RDREQ_IA 0x862
+#define mmMC_HUB_RDREQ_DMIF 0x863
+#define mmMC_HUB_RDREQ_MCIF 0x864
+#define mmMC_HUB_RDREQ_VMC 0x865
+#define mmMC_HUB_RDREQ_VCEU 0x866
+#define mmMC_HUB_WDP_MCDW 0x867
+#define mmMC_HUB_WDP_MCDX 0x868
+#define mmMC_HUB_WDP_MCDY 0x869
+#define mmMC_HUB_WDP_MCDZ 0x86a
+#define mmMC_HUB_WDP_SIP 0x86b
+#define mmMC_HUB_WDP_CPG 0x86c
+#define mmMC_HUB_WDP_SDMA1 0x86d
+#define mmMC_HUB_WDP_SH0 0x86e
+#define mmMC_HUB_WDP_MCIF 0x86f
+#define mmMC_HUB_WDP_VCE 0x870
+#define mmMC_HUB_WDP_XDP 0x871
+#define mmMC_HUB_WDP_IH 0x872
+#define mmMC_HUB_WDP_RLC 0x873
+#define mmMC_HUB_WDP_SEM 0x874
+#define mmMC_HUB_WDP_SMU 0x875
+#define mmMC_HUB_WDP_SH1 0x876
+#define mmMC_HUB_WDP_UMC 0x877
+#define mmMC_HUB_WDP_UVD 0x878
+#define mmMC_HUB_WDP_HDP 0x879
+#define mmMC_HUB_WDP_SDMA0 0x87a
+#define mmMC_HUB_WRRET_MCDW 0x87b
+#define mmMC_HUB_WRRET_MCDX 0x87c
+#define mmMC_HUB_WRRET_MCDY 0x87d
+#define mmMC_HUB_WRRET_MCDZ 0x87e
+#define mmMC_HUB_WDP_VCEU 0x87f
+#define mmMC_HUB_WDP_XDMAM 0x880
+#define mmMC_HUB_WDP_XDMA 0x881
+#define mmMC_HUB_RDREQ_XDMAM 0x882
+#define mmMC_HUB_RDREQ_ACPG 0x883
+#define mmMC_HUB_RDREQ_ACPO 0x884
+#define mmMC_HUB_RDREQ_SAM 0x885
+#define mmMC_HUB_WDP_ACPG 0x886
+#define mmMC_HUB_WDP_ACPO 0x887
+#define mmMC_HUB_WDP_SAM 0x888
+#define mmMC_HUB_RDREQ_CPC 0x889
+#define mmMC_HUB_RDREQ_CPF 0x88a
+#define mmMC_HUB_WDP_CPC 0x88b
+#define mmMC_HUB_WDP_CPF 0x88c
+#define mmMC_RPB_CONF 0x94d
+#define mmMC_RPB_IF_CONF 0x94e
+#define mmMC_RPB_DBG1 0x94f
+#define mmMC_RPB_EFF_CNTL 0x950
+#define mmMC_RPB_ARB_CNTL 0x951
+#define mmMC_RPB_BIF_CNTL 0x952
+#define mmMC_RPB_WR_SWITCH_CNTL 0x953
+#define mmMC_RPB_WR_COMBINE_CNTL 0x954
+#define mmMC_RPB_RD_SWITCH_CNTL 0x955
+#define mmMC_RPB_CID_QUEUE_WR 0x956
+#define mmMC_RPB_CID_QUEUE_RD 0x957
+#define mmMC_RPB_PERF_COUNTER_CNTL 0x958
+#define mmMC_RPB_PERF_COUNTER_STATUS 0x959
+#define mmMC_RPB_CID_QUEUE_EX 0x95a
+#define mmMC_RPB_CID_QUEUE_EX_DATA 0x95b
+#define mmMC_SHARED_CHMAP 0x801
+#define mmMC_SHARED_CHREMAP 0x802
+#define mmMC_RD_GRP_GFX 0x803
+#define mmMC_WR_GRP_GFX 0x804
+#define mmMC_RD_GRP_SYS 0x805
+#define mmMC_WR_GRP_SYS 0x806
+#define mmMC_RD_GRP_OTH 0x807
+#define mmMC_WR_GRP_OTH 0x808
+#define mmMC_VM_FB_LOCATION 0x809
+#define mmMC_VM_AGP_TOP 0x80a
+#define mmMC_VM_AGP_BOT 0x80b
+#define mmMC_VM_AGP_BASE 0x80c
+#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80d
+#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80e
+#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80f
+#define mmMC_VM_DC_WRITE_CNTL 0x810
+#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0x811
+#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0x812
+#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0x813
+#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0x814
+#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0x815
+#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0x816
+#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0x817
+#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0x818
+#define mmMC_VM_MX_L1_TLB_CNTL 0x819
+#define mmMC_VM_FB_OFFSET 0x81a
+#define mmMC_VM_STEERING 0x81b
+#define mmMC_CONFIG_MCD 0x828
+#define mmMC_CG_CONFIG_MCD 0x829
+#define mmMC_MEM_POWER_LS 0x82a
+#define mmMC_SHARED_BLACKOUT_CNTL 0x82b
+#define mmMC_VM_MB_L1_TLB0_DEBUG 0x891
+#define mmMC_VM_MB_L1_TLB2_DEBUG 0x893
+#define mmMC_VM_MB_L1_TLB0_STATUS 0x895
+#define mmMC_VM_MB_L1_TLB1_STATUS 0x896
+#define mmMC_VM_MB_L1_TLB2_STATUS 0x897
+#define mmMC_VM_MB_L2ARBITER_L2_CREDITS 0x8a1
+#define mmMC_VM_MB_L1_TLB3_DEBUG 0x8a5
+#define mmMC_VM_MB_L1_TLB3_STATUS 0x8a6
+#define mmMC_VM_MD_L1_TLB0_DEBUG 0x998
+#define mmMC_VM_MD_L1_TLB1_DEBUG 0x999
+#define mmMC_VM_MD_L1_TLB2_DEBUG 0x99a
+#define mmMC_VM_MD_L1_TLB0_STATUS 0x99b
+#define mmMC_VM_MD_L1_TLB1_STATUS 0x99c
+#define mmMC_VM_MD_L1_TLB2_STATUS 0x99d
+#define mmMC_VM_MD_L2ARBITER_L2_CREDITS 0x9a4
+#define mmMC_VM_MD_L1_TLB3_DEBUG 0x9a7
+#define mmMC_VM_MD_L1_TLB3_STATUS 0x9a8
+#define mmMC_XPB_RTR_SRC_APRTR0 0x8cd
+#define mmMC_XPB_RTR_SRC_APRTR1 0x8ce
+#define mmMC_XPB_RTR_SRC_APRTR2 0x8cf
+#define mmMC_XPB_RTR_SRC_APRTR3 0x8d0
+#define mmMC_XPB_RTR_SRC_APRTR4 0x8d1
+#define mmMC_XPB_RTR_SRC_APRTR5 0x8d2
+#define mmMC_XPB_RTR_SRC_APRTR6 0x8d3
+#define mmMC_XPB_RTR_SRC_APRTR7 0x8d4
+#define mmMC_XPB_RTR_SRC_APRTR8 0x8d5
+#define mmMC_XPB_RTR_SRC_APRTR9 0x8d6
+#define mmMC_XPB_XDMA_RTR_SRC_APRTR0 0x8d7
+#define mmMC_XPB_XDMA_RTR_SRC_APRTR1 0x8d8
+#define mmMC_XPB_XDMA_RTR_SRC_APRTR2 0x8d9
+#define mmMC_XPB_XDMA_RTR_SRC_APRTR3 0x8da
+#define mmMC_XPB_RTR_DEST_MAP0 0x8db
+#define mmMC_XPB_RTR_DEST_MAP1 0x8dc
+#define mmMC_XPB_RTR_DEST_MAP2 0x8dd
+#define mmMC_XPB_RTR_DEST_MAP3 0x8de
+#define mmMC_XPB_RTR_DEST_MAP4 0x8df
+#define mmMC_XPB_RTR_DEST_MAP5 0x8e0
+#define mmMC_XPB_RTR_DEST_MAP6 0x8e1
+#define mmMC_XPB_RTR_DEST_MAP7 0x8e2
+#define mmMC_XPB_RTR_DEST_MAP8 0x8e3
+#define mmMC_XPB_RTR_DEST_MAP9 0x8e4
+#define mmMC_XPB_XDMA_RTR_DEST_MAP0 0x8e5
+#define mmMC_XPB_XDMA_RTR_DEST_MAP1 0x8e6
+#define mmMC_XPB_XDMA_RTR_DEST_MAP2 0x8e7
+#define mmMC_XPB_XDMA_RTR_DEST_MAP3 0x8e8
+#define mmMC_XPB_CLG_CFG0 0x8e9
+#define mmMC_XPB_CLG_CFG1 0x8ea
+#define mmMC_XPB_CLG_CFG2 0x8eb
+#define mmMC_XPB_CLG_CFG3 0x8ec
+#define mmMC_XPB_CLG_CFG4 0x8ed
+#define mmMC_XPB_CLG_CFG5 0x8ee
+#define mmMC_XPB_CLG_CFG6 0x8ef
+#define mmMC_XPB_CLG_CFG7 0x8f0
+#define mmMC_XPB_CLG_CFG8 0x8f1
+#define mmMC_XPB_CLG_CFG9 0x8f2
+#define mmMC_XPB_CLG_CFG10 0x8f3
+#define mmMC_XPB_CLG_CFG11 0x8f4
+#define mmMC_XPB_CLG_CFG12 0x8f5
+#define mmMC_XPB_CLG_CFG13 0x8f6
+#define mmMC_XPB_CLG_CFG14 0x8f7
+#define mmMC_XPB_CLG_CFG15 0x8f8
+#define mmMC_XPB_CLG_CFG16 0x8f9
+#define mmMC_XPB_CLG_CFG17 0x8fa
+#define mmMC_XPB_CLG_CFG18 0x8fb
+#define mmMC_XPB_CLG_CFG19 0x8fc
+#define mmMC_XPB_CLG_EXTRA 0x8fd
+#define mmMC_XPB_LB_ADDR 0x8fe
+#define mmMC_XPB_UNC_THRESH_HST 0x8ff
+#define mmMC_XPB_UNC_THRESH_SID 0x900
+#define mmMC_XPB_WCB_STS 0x901
+#define mmMC_XPB_WCB_CFG 0x902
+#define mmMC_XPB_P2P_BAR_CFG 0x903
+#define mmMC_XPB_P2P_BAR0 0x904
+#define mmMC_XPB_P2P_BAR1 0x905
+#define mmMC_XPB_P2P_BAR2 0x906
+#define mmMC_XPB_P2P_BAR3 0x907
+#define mmMC_XPB_P2P_BAR4 0x908
+#define mmMC_XPB_P2P_BAR5 0x909
+#define mmMC_XPB_P2P_BAR6 0x90a
+#define mmMC_XPB_P2P_BAR7 0x90b
+#define mmMC_XPB_P2P_BAR_SETUP 0x90c
+#define mmMC_XPB_P2P_BAR_DEBUG 0x90d
+#define mmMC_XPB_P2P_BAR_DELTA_ABOVE 0x90e
+#define mmMC_XPB_P2P_BAR_DELTA_BELOW 0x90f
+#define mmMC_XPB_PEER_SYS_BAR0 0x910
+#define mmMC_XPB_PEER_SYS_BAR1 0x911
+#define mmMC_XPB_PEER_SYS_BAR2 0x912
+#define mmMC_XPB_PEER_SYS_BAR3 0x913
+#define mmMC_XPB_PEER_SYS_BAR4 0x914
+#define mmMC_XPB_PEER_SYS_BAR5 0x915
+#define mmMC_XPB_PEER_SYS_BAR6 0x916
+#define mmMC_XPB_PEER_SYS_BAR7 0x917
+#define mmMC_XPB_PEER_SYS_BAR8 0x918
+#define mmMC_XPB_PEER_SYS_BAR9 0x919
+#define mmMC_XPB_XDMA_PEER_SYS_BAR0 0x91a
+#define mmMC_XPB_XDMA_PEER_SYS_BAR1 0x91b
+#define mmMC_XPB_XDMA_PEER_SYS_BAR2 0x91c
+#define mmMC_XPB_XDMA_PEER_SYS_BAR3 0x91d
+#define mmMC_XPB_CLK_GAT 0x91e
+#define mmMC_XPB_INTF_CFG 0x91f
+#define mmMC_XPB_INTF_STS 0x920
+#define mmMC_XPB_PIPE_STS 0x921
+#define mmMC_XPB_SUB_CTRL 0x922
+#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0x923
+#define mmMC_XPB_PERF_KNOBS 0x924
+#define mmMC_XPB_STICKY 0x925
+#define mmMC_XPB_STICKY_W1C 0x926
+#define mmMC_XPB_MISC_CFG 0x927
+#define mmMC_XPB_CLG_CFG20 0x928
+#define mmMC_XPB_CLG_CFG21 0x929
+#define mmMC_XPB_CLG_CFG22 0x92a
+#define mmMC_XPB_CLG_CFG23 0x92b
+#define mmMC_XPB_CLG_CFG24 0x92c
+#define mmMC_XPB_CLG_CFG25 0x92d
+#define mmMC_XPB_CLG_CFG26 0x92e
+#define mmMC_XPB_CLG_CFG27 0x92f
+#define mmMC_XPB_CLG_CFG28 0x930
+#define mmMC_XPB_CLG_CFG29 0x931
+#define mmMC_XPB_CLG_CFG30 0x932
+#define mmMC_XPB_CLG_CFG31 0x933
+#define mmMC_XPB_INTF_CFG2 0x934
+#define mmMC_XPB_CLG_EXTRA_RD 0x935
+#define mmMC_XPB_CLG_CFG32 0x936
+#define mmMC_XPB_CLG_CFG33 0x937
+#define mmMC_XPB_CLG_CFG34 0x938
+#define mmMC_XPB_CLG_CFG35 0x939
+#define mmMC_XPB_CLG_CFG36 0x93a
+#define mmMC_XBAR_ADDR_DEC 0xc80
+#define mmMC_XBAR_REMOTE 0xc81
+#define mmMC_XBAR_WRREQ_CREDIT 0xc82
+#define mmMC_XBAR_RDREQ_CREDIT 0xc83
+#define mmMC_XBAR_RDREQ_PRI_CREDIT 0xc84
+#define mmMC_XBAR_WRRET_CREDIT1 0xc85
+#define mmMC_XBAR_WRRET_CREDIT2 0xc86
+#define mmMC_XBAR_RDRET_CREDIT1 0xc87
+#define mmMC_XBAR_RDRET_CREDIT2 0xc88
+#define mmMC_XBAR_RDRET_PRI_CREDIT1 0xc89
+#define mmMC_XBAR_RDRET_PRI_CREDIT2 0xc8a
+#define mmMC_XBAR_CHTRIREMAP 0xc8b
+#define mmMC_XBAR_TWOCHAN 0xc8c
+#define mmMC_XBAR_ARB 0xc8d
+#define mmMC_XBAR_ARB_MAX_BURST 0xc8e
+#define mmMC_XBAR_PERF_MON_CNTL0 0xc8f
+#define mmMC_XBAR_PERF_MON_CNTL1 0xc90
+#define mmMC_XBAR_PERF_MON_CNTL2 0xc91
+#define mmMC_XBAR_PERF_MON_RSLT0 0xc92
+#define mmMC_XBAR_PERF_MON_RSLT1 0xc93
+#define mmMC_XBAR_PERF_MON_RSLT2 0xc94
+#define mmMC_XBAR_PERF_MON_RSLT3 0xc95
+#define mmMC_XBAR_PERF_MON_MAX_THSH 0xc96
+#define mmMC_XBAR_SPARE0 0xc97
+#define mmMC_XBAR_SPARE1 0xc98
+#define mmMC_CITF_PERFCOUNTER_LO 0x7a0
+#define mmMC_HUB_PERFCOUNTER_LO 0x7a1
+#define mmMC_RPB_PERFCOUNTER_LO 0x7a2
+#define mmMC_MCBVM_PERFCOUNTER_LO 0x7a3
+#define mmMC_MCDVM_PERFCOUNTER_LO 0x7a4
+#define mmMC_VM_L2_PERFCOUNTER_LO 0x7a5
+#define mmMC_ARB_PERFCOUNTER_LO 0x7a6
+#define mmATC_PERFCOUNTER_LO 0x7a7
+#define mmMC_CITF_PERFCOUNTER_HI 0x7a8
+#define mmMC_HUB_PERFCOUNTER_HI 0x7a9
+#define mmMC_MCBVM_PERFCOUNTER_HI 0x7aa
+#define mmMC_MCDVM_PERFCOUNTER_HI 0x7ab
+#define mmMC_RPB_PERFCOUNTER_HI 0x7ac
+#define mmMC_VM_L2_PERFCOUNTER_HI 0x7ad
+#define mmMC_ARB_PERFCOUNTER_HI 0x7ae
+#define mmATC_PERFCOUNTER_HI 0x7af
+#define mmMC_CITF_PERFCOUNTER0_CFG 0x7b0
+#define mmMC_CITF_PERFCOUNTER1_CFG 0x7b1
+#define mmMC_CITF_PERFCOUNTER2_CFG 0x7b2
+#define mmMC_CITF_PERFCOUNTER3_CFG 0x7b3
+#define mmMC_HUB_PERFCOUNTER0_CFG 0x7b4
+#define mmMC_HUB_PERFCOUNTER1_CFG 0x7b5
+#define mmMC_HUB_PERFCOUNTER2_CFG 0x7b6
+#define mmMC_HUB_PERFCOUNTER3_CFG 0x7b7
+#define mmMC_RPB_PERFCOUNTER0_CFG 0x7b8
+#define mmMC_RPB_PERFCOUNTER1_CFG 0x7b9
+#define mmMC_RPB_PERFCOUNTER2_CFG 0x7ba
+#define mmMC_RPB_PERFCOUNTER3_CFG 0x7bb
+#define mmMC_ARB_PERFCOUNTER0_CFG 0x7bc
+#define mmMC_ARB_PERFCOUNTER1_CFG 0x7bd
+#define mmMC_ARB_PERFCOUNTER2_CFG 0x7be
+#define mmMC_ARB_PERFCOUNTER3_CFG 0x7bf
+#define mmMC_MCBVM_PERFCOUNTER0_CFG 0x7c0
+#define mmMC_MCBVM_PERFCOUNTER1_CFG 0x7c1
+#define mmMC_MCBVM_PERFCOUNTER2_CFG 0x7c2
+#define mmMC_MCBVM_PERFCOUNTER3_CFG 0x7c3
+#define mmMC_MCDVM_PERFCOUNTER0_CFG 0x7c4
+#define mmMC_MCDVM_PERFCOUNTER1_CFG 0x7c5
+#define mmMC_MCDVM_PERFCOUNTER2_CFG 0x7c6
+#define mmMC_MCDVM_PERFCOUNTER3_CFG 0x7c7
+#define mmATC_PERFCOUNTER0_CFG 0x7c8
+#define mmATC_PERFCOUNTER1_CFG 0x7c9
+#define mmATC_PERFCOUNTER2_CFG 0x7ca
+#define mmATC_PERFCOUNTER3_CFG 0x7cb
+#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x7cc
+#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x7cd
+#define mmMC_CITF_PERFCOUNTER_RSLT_CNTL 0x7ce
+#define mmMC_HUB_PERFCOUNTER_RSLT_CNTL 0x7cf
+#define mmMC_RPB_PERFCOUNTER_RSLT_CNTL 0x7d0
+#define mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL 0x7d1
+#define mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL 0x7d2
+#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x7d3
+#define mmMC_ARB_PERFCOUNTER_RSLT_CNTL 0x7d4
+#define mmATC_PERFCOUNTER_RSLT_CNTL 0x7d5
+#define mmCHUB_ATC_PERFCOUNTER_LO 0x7d6
+#define mmCHUB_ATC_PERFCOUNTER_HI 0x7d7
+#define mmCHUB_ATC_PERFCOUNTER0_CFG 0x7d8
+#define mmCHUB_ATC_PERFCOUNTER1_CFG 0x7d9
+#define mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL 0x7da
+#define mmMC_ARB_PERF_MON_CNTL0_ECC 0x7db
+#define mmATC_VM_APERTURE0_LOW_ADDR 0xcc0
+#define mmATC_VM_APERTURE1_LOW_ADDR 0xcc1
+#define mmATC_VM_APERTURE0_HIGH_ADDR 0xcc2
+#define mmATC_VM_APERTURE1_HIGH_ADDR 0xcc3
+#define mmATC_VM_APERTURE0_CNTL 0xcc4
+#define mmATC_VM_APERTURE1_CNTL 0xcc5
+#define mmATC_VM_APERTURE0_CNTL2 0xcc6
+#define mmATC_VM_APERTURE1_CNTL2 0xcc7
+#define mmATC_ATS_CNTL 0xcc9
+#define mmATC_ATS_DEBUG 0xcca
+#define mmATC_ATS_FAULT_DEBUG 0xccb
+#define mmATC_ATS_STATUS 0xccc
+#define mmATC_ATS_FAULT_CNTL 0xccd
+#define mmATC_ATS_FAULT_STATUS_INFO 0xcce
+#define mmATC_ATS_FAULT_STATUS_ADDR 0xccf
+#define mmATC_ATS_DEFAULT_PAGE_LOW 0xcd0
+#define mmATC_ATS_DEFAULT_PAGE_CNTL 0xcd1
+#define mmATC_MISC_CG 0xcd4
+#define mmATC_L2_CNTL 0xcd5
+#define mmATC_L2_CNTL2 0xcd6
+#define mmATC_L2_DEBUG 0xcd7
+#define mmATC_L2_DEBUG2 0xcd8
+#define mmATC_L1_CNTL 0xcdc
+#define mmATC_L1_ADDRESS_OFFSET 0xcdd
+#define mmATC_L1RD_DEBUG_TLB 0xcde
+#define mmATC_L1WR_DEBUG_TLB 0xcdf
+#define mmATC_L1RD_STATUS 0xce0
+#define mmATC_L1WR_STATUS 0xce1
+#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0xce6
+#define mmATC_VMID0_PASID_MAPPING 0xce7
+#define mmATC_VMID1_PASID_MAPPING 0xce8
+#define mmATC_VMID2_PASID_MAPPING 0xce9
+#define mmATC_VMID3_PASID_MAPPING 0xcea
+#define mmATC_VMID4_PASID_MAPPING 0xceb
+#define mmATC_VMID5_PASID_MAPPING 0xcec
+#define mmATC_VMID6_PASID_MAPPING 0xced
+#define mmATC_VMID7_PASID_MAPPING 0xcee
+#define mmATC_VMID8_PASID_MAPPING 0xcef
+#define mmATC_VMID9_PASID_MAPPING 0xcf0
+#define mmATC_VMID10_PASID_MAPPING 0xcf1
+#define mmATC_VMID11_PASID_MAPPING 0xcf2
+#define mmATC_VMID12_PASID_MAPPING 0xcf3
+#define mmATC_VMID13_PASID_MAPPING 0xcf4
+#define mmATC_VMID14_PASID_MAPPING 0xcf5
+#define mmATC_VMID15_PASID_MAPPING 0xcf6
+#define mmGMCON_RENG_RAM_INDEX 0xd40
+#define mmGMCON_RENG_RAM_DATA 0xd41
+#define mmGMCON_RENG_EXECUTE 0xd42
+#define mmGMCON_MISC 0xd43
+#define mmGMCON_MISC2 0xd44
+#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 0xd45
+#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 0xd46
+#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 0xd47
+#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 0xd48
+#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 0xd49
+#define mmGMCON_PERF_MON_CNTL0 0xd4a
+#define mmGMCON_PERF_MON_CNTL1 0xd4b
+#define mmGMCON_PERF_MON_RSLT0 0xd4c
+#define mmGMCON_PERF_MON_RSLT1 0xd4d
+#define mmGMCON_PGFSM_CONFIG 0xd4e
+#define mmGMCON_PGFSM_WRITE 0xd4f
+#define mmGMCON_PGFSM_READ 0xd50
+#define mmGMCON_MISC3 0xd51
+#define mmGMCON_MASK 0xd52
+#define mmGMCON_DEBUG 0xd5f
+#define mmVM_L2_CNTL 0x500
+#define mmVM_L2_CNTL2 0x501
+#define mmVM_L2_CNTL3 0x502
+#define mmVM_L2_STATUS 0x503
+#define mmVM_CONTEXT0_CNTL 0x504
+#define mmVM_CONTEXT1_CNTL 0x505
+#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x506
+#define mmVM_DUMMY_PAGE_FAULT_ADDR 0x507
+#define mmVM_CONTEXT0_CNTL2 0x50c
+#define mmVM_CONTEXT1_CNTL2 0x50d
+#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x50e
+#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x50f
+#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x510
+#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x511
+#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x512
+#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x513
+#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x514
+#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x515
+#define mmVM_INVALIDATE_REQUEST 0x51e
+#define mmVM_INVALIDATE_RESPONSE 0x51f
+#define mmVM_PRT_APERTURE0_LOW_ADDR 0x52c
+#define mmVM_PRT_APERTURE1_LOW_ADDR 0x52d
+#define mmVM_PRT_APERTURE2_LOW_ADDR 0x52e
+#define mmVM_PRT_APERTURE3_LOW_ADDR 0x52f
+#define mmVM_PRT_APERTURE0_HIGH_ADDR 0x530
+#define mmVM_PRT_APERTURE1_HIGH_ADDR 0x531
+#define mmVM_PRT_APERTURE2_HIGH_ADDR 0x532
+#define mmVM_PRT_APERTURE3_HIGH_ADDR 0x533
+#define mmVM_PRT_CNTL 0x534
+#define mmVM_CONTEXTS_DISABLE 0x535
+#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0x536
+#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0x537
+#define mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT 0x538
+#define mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x539
+#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0x53e
+#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0x53f
+#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x546
+#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x547
+#define mmVM_FAULT_CLIENT_ID 0x54e
+#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f
+#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x550
+#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x551
+#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x552
+#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x553
+#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x554
+#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x555
+#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x556
+#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0x557
+#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0x558
+#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0x55f
+#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0x560
+#define mmVM_DEBUG 0x56f
+#define mmVM_L2_CG 0x570
+#define mmVM_L2_BANK_SELECT_MASKA 0x572
+#define mmVM_L2_BANK_SELECT_MASKB 0x573
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0x575
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0x576
+#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0x577
+#define mmMC_ARB_HARSH_EN_RD 0xdc0
+#define mmMC_ARB_HARSH_EN_WR 0xdc1
+#define mmMC_ARB_HARSH_TX_HI0_RD 0xdc2
+#define mmMC_ARB_HARSH_TX_HI0_WR 0xdc3
+#define mmMC_ARB_HARSH_TX_HI1_RD 0xdc4
+#define mmMC_ARB_HARSH_TX_HI1_WR 0xdc5
+#define mmMC_ARB_HARSH_TX_LO0_RD 0xdc6
+#define mmMC_ARB_HARSH_TX_LO0_WR 0xdc7
+#define mmMC_ARB_HARSH_TX_LO1_RD 0xdc8
+#define mmMC_ARB_HARSH_TX_LO1_WR 0xdc9
+#define mmMC_ARB_HARSH_BWPERIOD0_RD 0xdca
+#define mmMC_ARB_HARSH_BWPERIOD0_WR 0xdcb
+#define mmMC_ARB_HARSH_BWPERIOD1_RD 0xdcc
+#define mmMC_ARB_HARSH_BWPERIOD1_WR 0xdcd
+#define mmMC_ARB_HARSH_BWCNT0_RD 0xdce
+#define mmMC_ARB_HARSH_BWCNT0_WR 0xdcf
+#define mmMC_ARB_HARSH_BWCNT1_RD 0xdd0
+#define mmMC_ARB_HARSH_BWCNT1_WR 0xdd1
+#define mmMC_ARB_HARSH_SAT0_RD 0xdd2
+#define mmMC_ARB_HARSH_SAT0_WR 0xdd3
+#define mmMC_ARB_HARSH_SAT1_RD 0xdd4
+#define mmMC_ARB_HARSH_SAT1_WR 0xdd5
+#define mmMC_ARB_HARSH_CTL_RD 0xdd6
+#define mmMC_ARB_HARSH_CTL_WR 0xdd7
+#define mmMC_FUS_DRAM0_CS0_BASE 0xa05
+#define mmMC_FUS_DRAM1_CS0_BASE 0xa06
+#define mmMC_FUS_DRAM0_CS1_BASE 0xa07
+#define mmMC_FUS_DRAM1_CS1_BASE 0xa08
+#define mmMC_FUS_DRAM0_CS2_BASE 0xa09
+#define mmMC_FUS_DRAM1_CS2_BASE 0xa0a
+#define mmMC_FUS_DRAM0_CS3_BASE 0xa0b
+#define mmMC_FUS_DRAM1_CS3_BASE 0xa0c
+#define mmMC_FUS_DRAM0_CS01_MASK 0xa0d
+#define mmMC_FUS_DRAM1_CS01_MASK 0xa0e
+#define mmMC_FUS_DRAM0_CS23_MASK 0xa0f
+#define mmMC_FUS_DRAM1_CS23_MASK 0xa10
+#define mmMC_FUS_DRAM0_BANK_ADDR_MAPPING 0xa11
+#define mmMC_FUS_DRAM1_BANK_ADDR_MAPPING 0xa12
+#define mmMC_FUS_DRAM0_CTL_BASE 0xa13
+#define mmMC_FUS_DRAM1_CTL_BASE 0xa14
+#define mmMC_FUS_DRAM0_CTL_LIMIT 0xa15
+#define mmMC_FUS_DRAM1_CTL_LIMIT 0xa16
+#define mmMC_FUS_DRAM_CTL_HIGH_01 0xa17
+#define mmMC_FUS_DRAM_CTL_HIGH_23 0xa18
+#define mmMC_FUS_DRAM_MODE 0xa19
+#define mmMC_FUS_DRAM_APER_BASE 0xa1a
+#define mmMC_FUS_DRAM_APER_TOP 0xa1b
+#define mmMC_FUS_DRAM_C6SAVE_APER_BASE 0xa1c
+#define mmMC_FUS_DRAM_C6SAVE_APER_TOP 0xa1d
+#define mmMC_FUS_DRAM_APER_DEF 0xa1e
+#define mmMC_FUS_ARB_GARLIC_ISOC_PRI 0xa1f
+#define mmMC_FUS_ARB_GARLIC_CNTL 0xa20
+#define mmMC_FUS_ARB_GARLIC_WR_PRI 0xa21
+#define mmMC_FUS_ARB_GARLIC_WR_PRI2 0xa22
+#define mmMC_CG_DATAPORT 0xa32
+#define mmCHUB_ATC_L1_DEBUG_TLB 0x8c00
+#define mmCHUB_ATC_L1_STATUS 0x8c01
+
+#endif /* GMC_7_0_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h
new file mode 100644
index 000000000000..64d3c2356e09
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h
@@ -0,0 +1,6116 @@
+/*
+ * GMC_7_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GMC_7_0_SH_MASK_H
+#define GMC_7_0_SH_MASK_H
+
+#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
+#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
+#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
+#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
+#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
+#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
+#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
+#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
+#define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
+#define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
+#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000
+#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x1f
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0_MASK 0x1
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0__SHIFT 0x0
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1_MASK 0x2
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1__SHIFT 0x1
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2_MASK 0x4
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2__SHIFT 0x2
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3__SHIFT 0x3
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4__SHIFT 0x4
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5_MASK 0x20
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5__SHIFT 0x5
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6_MASK 0x40
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6__SHIFT 0x6
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7_MASK 0x80
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7__SHIFT 0x7
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0_MASK 0x100
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1_MASK 0x200
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1__SHIFT 0x9
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2_MASK 0x400
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x800
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3__SHIFT 0xb
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4_MASK 0x1000
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4__SHIFT 0xc
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5_MASK 0x2000
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5__SHIFT 0xd
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6_MASK 0x4000
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT 0xe
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7_MASK 0x8000
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7__SHIFT 0xf
+#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD_MASK 0x70000
+#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10
+#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR_MASK 0x380000
+#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR__SHIFT 0x13
+#define MC_ARB_RET_CREDITS2__ACP_WR_MASK 0xff
+#define MC_ARB_RET_CREDITS2__ACP_WR__SHIFT 0x0
+#define MC_ARB_FED_CNTL__MODE_MASK 0x3
+#define MC_ARB_FED_CNTL__MODE__SHIFT 0x0
+#define MC_ARB_FED_CNTL__WR_ERR_MASK 0xc
+#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x2
+#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10
+#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x4
+#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK_MASK 0x20
+#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK__SHIFT 0x5
+#define MC_ARB_FED_CNTL__USE_LEGACY_NACK_MASK 0x40
+#define MC_ARB_FED_CNTL__USE_LEGACY_NACK__SHIFT 0x6
+#define MC_ARB_FED_CNTL__DEBUG_RSV_MASK 0xffffff80
+#define MC_ARB_FED_CNTL__DEBUG_RSV__SHIFT 0x7
+#define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x1
+#define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x0
+#define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x2
+#define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x1
+#define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x4
+#define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x2
+#define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8
+#define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x3
+#define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10
+#define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x4
+#define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x20
+#define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x5
+#define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x40
+#define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x6
+#define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x80
+#define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x7
+#define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x100
+#define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8
+#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x200
+#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x9
+#define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x400
+#define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa
+#define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x800
+#define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0xb
+#define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x1000
+#define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0xc
+#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x2000
+#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0xd
+#define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x4000
+#define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0xe
+#define MC_ARB_GECC2_STATUS__RSVD3_MASK 0x8000
+#define MC_ARB_GECC2_STATUS__RSVD3__SHIFT 0xf
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0_MASK 0x10000
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0_MASK 0x20000
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0__SHIFT 0x11
+#define MC_ARB_GECC2_STATUS__RSVD4_MASK 0xc0000
+#define MC_ARB_GECC2_STATUS__RSVD4__SHIFT 0x12
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1_MASK 0x100000
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1__SHIFT 0x14
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1_MASK 0x200000
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1__SHIFT 0x15
+#define MC_ARB_GECC2_STATUS__RSVD5_MASK 0xc00000
+#define MC_ARB_GECC2_STATUS__RSVD5__SHIFT 0x16
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0_MASK 0x1000000
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0__SHIFT 0x18
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0_MASK 0x2000000
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0__SHIFT 0x19
+#define MC_ARB_GECC2_STATUS__RSVD6_MASK 0xc000000
+#define MC_ARB_GECC2_STATUS__RSVD6__SHIFT 0x1a
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1_MASK 0x10000000
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1__SHIFT 0x1c
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1_MASK 0x20000000
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d
+#define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0xf
+#define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x0
+#define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10
+#define MC_ARB_GECC2_MISC__COL10_HACK__SHIFT 0x4
+#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY_MASK 0x20
+#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY__SHIFT 0x5
+#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY_MASK 0x40
+#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY__SHIFT 0x6
+#define MC_ARB_GECC2_MISC__DEBUG_RSV_MASK 0xffffff80
+#define MC_ARB_GECC2_MISC__DEBUG_RSV__SHIFT 0x7
+#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x3
+#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x0
+#define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x4
+#define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x2
+#define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x18
+#define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x3
+#define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x20
+#define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x5
+#define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0xff
+#define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x0
+#define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0xff00
+#define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8
+#define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0xff0000
+#define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10
+#define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000
+#define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x18
+#define MC_ARB_GECC2__ENABLE_MASK 0x1
+#define MC_ARB_GECC2__ENABLE__SHIFT 0x0
+#define MC_ARB_GECC2__ECC_MODE_MASK 0x6
+#define MC_ARB_GECC2__ECC_MODE__SHIFT 0x1
+#define MC_ARB_GECC2__PAGE_BIT0_MASK 0x18
+#define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x3
+#define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x60
+#define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x5
+#define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x780
+#define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x7
+#define MC_ARB_GECC2__READ_ERR_MASK 0x3800
+#define MC_ARB_GECC2__READ_ERR__SHIFT 0xb
+#define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x4000
+#define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0xe
+#define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x1f8000
+#define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0xf
+#define MC_ARB_GECC2__WRADDR_CONV_MASK 0x200000
+#define MC_ARB_GECC2__WRADDR_CONV__SHIFT 0x15
+#define MC_ARB_GECC2__RMWRD_UNCOR_POISON_MASK 0x400000
+#define MC_ARB_GECC2__RMWRD_UNCOR_POISON__SHIFT 0x16
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0xff
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x0
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0xff00
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x8
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0xff0000
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x10
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x18
+#define MC_ARB_ADDR_SWIZ0__A8_MASK 0xf
+#define MC_ARB_ADDR_SWIZ0__A8__SHIFT 0x0
+#define MC_ARB_ADDR_SWIZ0__A9_MASK 0xf0
+#define MC_ARB_ADDR_SWIZ0__A9__SHIFT 0x4
+#define MC_ARB_ADDR_SWIZ0__A10_MASK 0xf00
+#define MC_ARB_ADDR_SWIZ0__A10__SHIFT 0x8
+#define MC_ARB_ADDR_SWIZ0__A11_MASK 0xf000
+#define MC_ARB_ADDR_SWIZ0__A11__SHIFT 0xc
+#define MC_ARB_ADDR_SWIZ0__A12_MASK 0xf0000
+#define MC_ARB_ADDR_SWIZ0__A12__SHIFT 0x10
+#define MC_ARB_ADDR_SWIZ0__A13_MASK 0xf00000
+#define MC_ARB_ADDR_SWIZ0__A13__SHIFT 0x14
+#define MC_ARB_ADDR_SWIZ0__A14_MASK 0xf000000
+#define MC_ARB_ADDR_SWIZ0__A14__SHIFT 0x18
+#define MC_ARB_ADDR_SWIZ0__A15_MASK 0xf0000000
+#define MC_ARB_ADDR_SWIZ0__A15__SHIFT 0x1c
+#define MC_ARB_ADDR_SWIZ1__A16_MASK 0xf
+#define MC_ARB_ADDR_SWIZ1__A16__SHIFT 0x0
+#define MC_ARB_ADDR_SWIZ1__A17_MASK 0xf0
+#define MC_ARB_ADDR_SWIZ1__A17__SHIFT 0x4
+#define MC_ARB_ADDR_SWIZ1__A18_MASK 0xf00
+#define MC_ARB_ADDR_SWIZ1__A18__SHIFT 0x8
+#define MC_ARB_ADDR_SWIZ1__A19_MASK 0xf000
+#define MC_ARB_ADDR_SWIZ1__A19__SHIFT 0xc
+#define MC_ARB_MISC3__NO_GECC_EXT_EOB_MASK 0x1
+#define MC_ARB_MISC3__NO_GECC_EXT_EOB__SHIFT 0x0
+#define MC_ARB_MISC3__TBD_FIELD_MASK 0xfffffffe
+#define MC_ARB_MISC3__TBD_FIELD__SHIFT 0x1
+#define MC_ARB_WCDR_2__WPRE_INC_STEP_MASK 0xf
+#define MC_ARB_WCDR_2__WPRE_INC_STEP__SHIFT 0x0
+#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD_MASK 0x1f0
+#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD__SHIFT 0x4
+#define MC_ARB_WCDR_2__DEBUG_0_MASK 0x200
+#define MC_ARB_WCDR_2__DEBUG_0__SHIFT 0x9
+#define MC_ARB_WCDR_2__DEBUG_1_MASK 0x400
+#define MC_ARB_WCDR_2__DEBUG_1__SHIFT 0xa
+#define MC_ARB_WCDR_2__DEBUG_2_MASK 0x800
+#define MC_ARB_WCDR_2__DEBUG_2__SHIFT 0xb
+#define MC_ARB_WCDR_2__DEBUG_3_MASK 0x1000
+#define MC_ARB_WCDR_2__DEBUG_3__SHIFT 0xc
+#define MC_ARB_WCDR_2__DEBUG_4_MASK 0x2000
+#define MC_ARB_WCDR_2__DEBUG_4__SHIFT 0xd
+#define MC_ARB_WCDR_2__DEBUG_5_MASK 0x4000
+#define MC_ARB_WCDR_2__DEBUG_5__SHIFT 0xe
+#define MC_ARB_RTT_DATA__PATTERN_MASK 0xff
+#define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x0
+#define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x1
+#define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x0
+#define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x2
+#define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x1
+#define MC_ARB_RTT_CNTL0__START_R2W_MASK 0xc
+#define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x2
+#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x10
+#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x4
+#define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x20
+#define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x5
+#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x40
+#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x6
+#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x80
+#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x7
+#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x100
+#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x8
+#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x200
+#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x9
+#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x400
+#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa
+#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x3800
+#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0xb
+#define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x4000
+#define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0xe
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x8000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0xf
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x10000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x10
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x20000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x11
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x40000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x12
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x80000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x13
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x100000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x14
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x200000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x15
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x400000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x16
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x800000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x17
+#define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x1000000
+#define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x18
+#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x2000000
+#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x19
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x1f
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x0
+#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x20
+#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x5
+#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x1fc0
+#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x6
+#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0xfe000
+#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0xd
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x1f00000
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x14
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x19
+#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000
+#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x1e
+#define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x3f
+#define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x0
+#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0xfc0
+#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x6
+#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x1000
+#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0xc
+#define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x2000
+#define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0xd
+#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x3
+#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x0
+#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0xc
+#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x2
+#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0xff0
+#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x4
+#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x1f000
+#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0xc
+#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x1fe0000
+#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x11
+#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000
+#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x19
+#define MC_ARB_CAC_CNTL__ENABLE_MASK 0x1
+#define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x0
+#define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x7e
+#define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x1
+#define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x1f80
+#define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x7
+#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x2000
+#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0xd
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x20
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x5
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x40
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x6
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x80
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x7
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x100
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x8
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x200
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x9
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x400
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa
+#define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x800
+#define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0xb
+#define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x1000
+#define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0xc
+#define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x2000
+#define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0xd
+#define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x3c000
+#define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0xe
+#define MC_ARB_MISC2__GECC_MASK 0x40000
+#define MC_ARB_MISC2__GECC__SHIFT 0x12
+#define MC_ARB_MISC2__GECC_RST_MASK 0x80000
+#define MC_ARB_MISC2__GECC_RST__SHIFT 0x13
+#define MC_ARB_MISC2__GECC_STATUS_MASK 0x100000
+#define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x14
+#define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x1e00000
+#define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x15
+#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0xe000000
+#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x19
+#define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000
+#define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x1c
+#define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000
+#define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d
+#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000
+#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x1e
+#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000
+#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x1f
+#define MC_ARB_MISC__STICKY_RFSH_MASK 0x1
+#define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x0
+#define MC_ARB_MISC__IDLE_RFSH_MASK 0x2
+#define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x1
+#define MC_ARB_MISC__STUTTER_RFSH_MASK 0x4
+#define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x2
+#define MC_ARB_MISC__CHAN_COUPLE_MASK 0x7f8
+#define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x3
+#define MC_ARB_MISC__HARSHNESS_MASK 0x7f800
+#define MC_ARB_MISC__HARSHNESS__SHIFT 0xb
+#define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x80000
+#define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x13
+#define MC_ARB_MISC__CALI_ENABLE_MASK 0x100000
+#define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x14
+#define MC_ARB_MISC__CALI_RATES_MASK 0x600000
+#define MC_ARB_MISC__CALI_RATES__SHIFT 0x15
+#define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x800000
+#define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x17
+#define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x1000000
+#define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x18
+#define MC_ARB_MISC__DISPURG_STALL_MASK 0x2000000
+#define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x19
+#define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000
+#define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x1a
+#define MC_ARB_MISC__EXTEND_WEIGHT_MASK 0x40000000
+#define MC_ARB_MISC__EXTEND_WEIGHT__SHIFT 0x1e
+#define MC_ARB_MISC__ACPURG_STALL_MASK 0x80000000
+#define MC_ARB_MISC__ACPURG_STALL__SHIFT 0x1f
+#define MC_ARB_BANKMAP__BANK0_MASK 0xf
+#define MC_ARB_BANKMAP__BANK0__SHIFT 0x0
+#define MC_ARB_BANKMAP__BANK1_MASK 0xf0
+#define MC_ARB_BANKMAP__BANK1__SHIFT 0x4
+#define MC_ARB_BANKMAP__BANK2_MASK 0xf00
+#define MC_ARB_BANKMAP__BANK2__SHIFT 0x8
+#define MC_ARB_BANKMAP__BANK3_MASK 0xf000
+#define MC_ARB_BANKMAP__BANK3__SHIFT 0xc
+#define MC_ARB_BANKMAP__RANK_MASK 0xf0000
+#define MC_ARB_BANKMAP__RANK__SHIFT 0x10
+#define MC_ARB_RAMCFG__NOOFBANK_MASK 0x3
+#define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x0
+#define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x4
+#define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x2
+#define MC_ARB_RAMCFG__NOOFROWS_MASK 0x38
+#define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x3
+#define MC_ARB_RAMCFG__NOOFCOLS_MASK 0xc0
+#define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x6
+#define MC_ARB_RAMCFG__CHANSIZE_MASK 0x100
+#define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x8
+#define MC_ARB_RAMCFG__RSV_1_MASK 0x200
+#define MC_ARB_RAMCFG__RSV_1__SHIFT 0x9
+#define MC_ARB_RAMCFG__RSV_2_MASK 0x400
+#define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa
+#define MC_ARB_RAMCFG__RSV_3_MASK 0x800
+#define MC_ARB_RAMCFG__RSV_3__SHIFT 0xb
+#define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x1000
+#define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0xc
+#define MC_ARB_RAMCFG__RSV_4_MASK 0x3e000
+#define MC_ARB_RAMCFG__RSV_4__SHIFT 0xd
+#define MC_ARB_POP__ENABLE_ARB_MASK 0x1
+#define MC_ARB_POP__ENABLE_ARB__SHIFT 0x0
+#define MC_ARB_POP__SPEC_OPEN_MASK 0x2
+#define MC_ARB_POP__SPEC_OPEN__SHIFT 0x1
+#define MC_ARB_POP__POP_DEPTH_MASK 0x3c
+#define MC_ARB_POP__POP_DEPTH__SHIFT 0x2
+#define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0xfc0
+#define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x6
+#define MC_ARB_POP__SKID_DEPTH_MASK 0x7000
+#define MC_ARB_POP__SKID_DEPTH__SHIFT 0xc
+#define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x18000
+#define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0xf
+#define MC_ARB_POP__QUICK_STOP_MASK 0x20000
+#define MC_ARB_POP__QUICK_STOP__SHIFT 0x11
+#define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x40000
+#define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x12
+#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x80000
+#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x13
+#define MC_ARB_MINCLKS__READ_CLKS_MASK 0xff
+#define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x0
+#define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0xff00
+#define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x8
+#define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x10000
+#define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x10
+#define MC_ARB_MINCLKS__RW_SWITCH_HARSH_MASK 0x60000
+#define MC_ARB_MINCLKS__RW_SWITCH_HARSH__SHIFT 0x11
+#define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0xff
+#define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x0
+#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x100
+#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x8
+#define MC_ARB_SQM_CNTL__SQM_RDY16_MASK 0x200
+#define MC_ARB_SQM_CNTL__SQM_RDY16__SHIFT 0x9
+#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0xfc00
+#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa
+#define MC_ARB_SQM_CNTL__RATIO_MASK 0xff0000
+#define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x10
+#define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000
+#define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x18
+#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0xf
+#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x0
+#define MC_ARB_ADDR_HASH__COL_XOR_MASK 0xff0
+#define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x4
+#define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0xffff000
+#define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0xc
+#define MC_ARB_DRAM_TIMING__ACTRD_MASK 0xff
+#define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x0
+#define MC_ARB_DRAM_TIMING__ACTWR_MASK 0xff00
+#define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x8
+#define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0xff0000
+#define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x10
+#define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000
+#define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x18
+#define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0xff
+#define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x0
+#define MC_ARB_DRAM_TIMING2__RP_MASK 0xff00
+#define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x8
+#define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0xff0000
+#define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x10
+#define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000
+#define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x18
+#define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x3
+#define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x0
+#define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x4
+#define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x2
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x8
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x3
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x10
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x4
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x20
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x5
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x40
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x6
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x80
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x7
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x100
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x8
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x200
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x9
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x400
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa
+#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK 0x800
+#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI__SHIFT 0xb
+#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP_MASK 0x1000
+#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP__SHIFT 0xc
+#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG_MASK 0x2000
+#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG__SHIFT 0xd
+#define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x3
+#define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x0
+#define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x4
+#define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x2
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x8
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x3
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x10
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x4
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x20
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x5
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x40
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x6
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x80
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x7
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x100
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x8
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x200
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x9
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x400
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa
+#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK 0x800
+#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI__SHIFT 0xb
+#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP_MASK 0x1000
+#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP__SHIFT 0xc
+#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG_MASK 0x2000
+#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG__SHIFT 0xd
+#define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x3
+#define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x0
+#define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0xc
+#define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x2
+#define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x30
+#define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x4
+#define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0xc0
+#define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x6
+#define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x300
+#define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x8
+#define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0xc00
+#define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0xa
+#define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x3000
+#define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0xc
+#define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0xc000
+#define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0xe
+#define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0xff0000
+#define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x10
+#define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x3
+#define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x0
+#define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0xc
+#define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x2
+#define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x30
+#define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x4
+#define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0xc0
+#define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x6
+#define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x300
+#define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x8
+#define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0xc00
+#define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0xa
+#define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x3000
+#define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0xc
+#define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0xc000
+#define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0xe
+#define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0xff0000
+#define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x10
+#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x1
+#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x0
+#define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x6
+#define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x1
+#define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x8
+#define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x3
+#define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x10
+#define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x4
+#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x1
+#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x0
+#define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x6
+#define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x1
+#define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x8
+#define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x3
+#define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x10
+#define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x4
+#define MC_ARB_LAZY0_RD__GROUP0_MASK 0xff
+#define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_LAZY0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_LAZY0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_LAZY0_WR__GROUP0_MASK 0xff
+#define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_LAZY0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_LAZY0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_LAZY1_RD__GROUP4_MASK 0xff
+#define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_LAZY1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_LAZY1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_LAZY1_WR__GROUP4_MASK 0xff
+#define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_LAZY1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_LAZY1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x3
+#define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x0
+#define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0xc
+#define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x2
+#define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x30
+#define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x4
+#define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0xc0
+#define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x6
+#define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x300
+#define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x8
+#define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0xc00
+#define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0xa
+#define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x3000
+#define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0xc
+#define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0xc000
+#define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0xe
+#define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x10000
+#define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x10
+#define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x20000
+#define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x11
+#define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x40000
+#define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x12
+#define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x80000
+#define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x13
+#define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x100000
+#define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x14
+#define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x200000
+#define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x15
+#define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x400000
+#define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x16
+#define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x800000
+#define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x17
+#define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x1000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x18
+#define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x2000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x19
+#define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x4000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x1a
+#define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x8000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x1b
+#define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x1c
+#define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d
+#define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x1e
+#define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x1f
+#define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x3
+#define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x0
+#define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0xc
+#define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x2
+#define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x30
+#define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x4
+#define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0xc0
+#define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x6
+#define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x300
+#define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x8
+#define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0xc00
+#define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0xa
+#define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x3000
+#define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0xc
+#define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0xc000
+#define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0xe
+#define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x10000
+#define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x10
+#define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x20000
+#define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x11
+#define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x40000
+#define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x12
+#define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x80000
+#define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x13
+#define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x100000
+#define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x14
+#define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x200000
+#define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x15
+#define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x400000
+#define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x16
+#define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x800000
+#define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x17
+#define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x1000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x18
+#define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x2000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x19
+#define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x4000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x1a
+#define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x8000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x1b
+#define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x1c
+#define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d
+#define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x1e
+#define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x1f
+#define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x1
+#define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x0
+#define MC_ARB_RFSH_CNTL__URG0_MASK 0x3e
+#define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x1
+#define MC_ARB_RFSH_CNTL__URG1_MASK 0x7c0
+#define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x6
+#define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x800
+#define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0xb
+#define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0xff
+#define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x0
+#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x3
+#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x0
+#define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x4
+#define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x2
+#define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x8
+#define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x3
+#define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x10
+#define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x4
+#define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x20
+#define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x5
+#define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x40
+#define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x6
+#define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x80
+#define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x7
+#define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x300
+#define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x8
+#define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x400
+#define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0xa
+#define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x800
+#define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb
+#define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x1000
+#define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0xc
+#define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x2000
+#define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd
+#define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x4000
+#define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0xe
+#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000
+#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf
+#define MC_ARB_PM_CNTL__RSV_0_MASK 0x30000
+#define MC_ARB_PM_CNTL__RSV_0__SHIFT 0x10
+#define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x40000
+#define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x12
+#define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x80000
+#define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x13
+#define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0xf00000
+#define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x14
+#define MC_ARB_PM_CNTL__RSV_1_MASK 0x1000000
+#define MC_ARB_PM_CNTL__RSV_1__SHIFT 0x18
+#define MC_ARB_PM_CNTL__RSV_2_MASK 0x2000000
+#define MC_ARB_PM_CNTL__RSV_2__SHIFT 0x19
+#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0xf
+#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x0
+#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0xf0
+#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x4
+#define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x100
+#define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x8
+#define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x200
+#define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x9
+#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
+#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
+#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0xf
+#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x0
+#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0xf0
+#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x4
+#define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x100
+#define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x8
+#define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x200
+#define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x9
+#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
+#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
+#define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0xff
+#define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x0
+#define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0xff00
+#define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x8
+#define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x10000
+#define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x10
+#define MC_ARB_LM_RD__STREAK_UBER_MASK 0x20000
+#define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x11
+#define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x40000
+#define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x12
+#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x80000
+#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x13
+#define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x100000
+#define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x14
+#define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0xe00000
+#define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x15
+#define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0xff
+#define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x0
+#define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0xff00
+#define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x8
+#define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x10000
+#define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x10
+#define MC_ARB_LM_WR__STREAK_UBER_MASK 0x20000
+#define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x11
+#define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x40000
+#define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x12
+#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x80000
+#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x13
+#define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x100000
+#define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x14
+#define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0xe00000
+#define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x15
+#define MC_ARB_REMREQ__RD_WATER_MASK 0xff
+#define MC_ARB_REMREQ__RD_WATER__SHIFT 0x0
+#define MC_ARB_REMREQ__WR_WATER_MASK 0xff00
+#define MC_ARB_REMREQ__WR_WATER__SHIFT 0x8
+#define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0xf0000
+#define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x10
+#define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0xf00000
+#define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x14
+#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ_MASK 0x1000000
+#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ__SHIFT 0x18
+#define MC_ARB_REPLAY__ENABLE_RD_MASK 0x1
+#define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x0
+#define MC_ARB_REPLAY__ENABLE_WR_MASK 0x2
+#define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x1
+#define MC_ARB_REPLAY__WRACK_MODE_MASK 0x4
+#define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x2
+#define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x8
+#define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x3
+#define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x10
+#define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x4
+#define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x20
+#define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x5
+#define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x40
+#define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x6
+#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x80
+#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x7
+#define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x7f00
+#define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x8
+#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START_MASK 0x8000
+#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START__SHIFT 0xf
+#define MC_ARB_RET_CREDITS_RD__LCL_MASK 0xff
+#define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x0
+#define MC_ARB_RET_CREDITS_RD__HUB_MASK 0xff00
+#define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x8
+#define MC_ARB_RET_CREDITS_RD__DISP_MASK 0xff0000
+#define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x10
+#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000
+#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x18
+#define MC_ARB_RET_CREDITS_WR__LCL_MASK 0xff
+#define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x0
+#define MC_ARB_RET_CREDITS_WR__HUB_MASK 0xff00
+#define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x8
+#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0xff0000
+#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x10
+#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0xf000000
+#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x18
+#define MC_ARB_MAX_LAT_CID__CID_CH0_MASK 0xff
+#define MC_ARB_MAX_LAT_CID__CID_CH0__SHIFT 0x0
+#define MC_ARB_MAX_LAT_CID__CID_CH1_MASK 0xff00
+#define MC_ARB_MAX_LAT_CID__CID_CH1__SHIFT 0x8
+#define MC_ARB_MAX_LAT_CID__WRITE_CH0_MASK 0x10000
+#define MC_ARB_MAX_LAT_CID__WRITE_CH0__SHIFT 0x10
+#define MC_ARB_MAX_LAT_CID__WRITE_CH1_MASK 0x20000
+#define MC_ARB_MAX_LAT_CID__WRITE_CH1__SHIFT 0x11
+#define MC_ARB_MAX_LAT_CID__REALTIME_CH0_MASK 0x40000
+#define MC_ARB_MAX_LAT_CID__REALTIME_CH0__SHIFT 0x12
+#define MC_ARB_MAX_LAT_CID__REALTIME_CH1_MASK 0x80000
+#define MC_ARB_MAX_LAT_CID__REALTIME_CH1__SHIFT 0x13
+#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY_MASK 0xffffffff
+#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY__SHIFT 0x0
+#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY_MASK 0xffffffff
+#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY__SHIFT 0x0
+#define MC_ARB_SSM__FORMAT_MASK 0x1f
+#define MC_ARB_SSM__FORMAT__SHIFT 0x0
+#define MC_ARB_CG__CG_ARB_REQ_MASK 0xff
+#define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x0
+#define MC_ARB_CG__CG_ARB_RESP_MASK 0xff00
+#define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x8
+#define MC_ARB_CG__RSV_0_MASK 0xff0000
+#define MC_ARB_CG__RSV_0__SHIFT 0x10
+#define MC_ARB_CG__RSV_1_MASK 0xff000000
+#define MC_ARB_CG__RSV_1__SHIFT 0x18
+#define MC_ARB_WCDR__IDLE_ENABLE_MASK 0x1
+#define MC_ARB_WCDR__IDLE_ENABLE__SHIFT 0x0
+#define MC_ARB_WCDR__SEQ_IDLE_MASK 0x2
+#define MC_ARB_WCDR__SEQ_IDLE__SHIFT 0x1
+#define MC_ARB_WCDR__IDLE_PERIOD_MASK 0x7c
+#define MC_ARB_WCDR__IDLE_PERIOD__SHIFT 0x2
+#define MC_ARB_WCDR__IDLE_BURST_MASK 0x1f80
+#define MC_ARB_WCDR__IDLE_BURST__SHIFT 0x7
+#define MC_ARB_WCDR__IDLE_BURST_MODE_MASK 0x2000
+#define MC_ARB_WCDR__IDLE_BURST_MODE__SHIFT 0xd
+#define MC_ARB_WCDR__IDLE_WAKEUP_MASK 0xc000
+#define MC_ARB_WCDR__IDLE_WAKEUP__SHIFT 0xe
+#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE_MASK 0x10000
+#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE__SHIFT 0x10
+#define MC_ARB_WCDR__WPRE_ENABLE_MASK 0x20000
+#define MC_ARB_WCDR__WPRE_ENABLE__SHIFT 0x11
+#define MC_ARB_WCDR__WPRE_THRESHOLD_MASK 0x3c0000
+#define MC_ARB_WCDR__WPRE_THRESHOLD__SHIFT 0x12
+#define MC_ARB_WCDR__WPRE_MAX_BURST_MASK 0x1c00000
+#define MC_ARB_WCDR__WPRE_MAX_BURST__SHIFT 0x16
+#define MC_ARB_WCDR__WPRE_INC_READ_MASK 0x2000000
+#define MC_ARB_WCDR__WPRE_INC_READ__SHIFT 0x19
+#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE_MASK 0x4000000
+#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE__SHIFT 0x1a
+#define MC_ARB_WCDR__WPRE_INC_SEQIDLE_MASK 0x8000000
+#define MC_ARB_WCDR__WPRE_INC_SEQIDLE__SHIFT 0x1b
+#define MC_ARB_WCDR__WPRE_TWOPAGE_MASK 0x10000000
+#define MC_ARB_WCDR__WPRE_TWOPAGE__SHIFT 0x1c
+#define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0xff
+#define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x0
+#define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0xff00
+#define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x8
+#define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0xff0000
+#define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x10
+#define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000
+#define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x18
+#define MC_ARB_BUSY_STATUS__LM_RD0_MASK 0x1
+#define MC_ARB_BUSY_STATUS__LM_RD0__SHIFT 0x0
+#define MC_ARB_BUSY_STATUS__LM_RD1_MASK 0x2
+#define MC_ARB_BUSY_STATUS__LM_RD1__SHIFT 0x1
+#define MC_ARB_BUSY_STATUS__LM_WR0_MASK 0x4
+#define MC_ARB_BUSY_STATUS__LM_WR0__SHIFT 0x2
+#define MC_ARB_BUSY_STATUS__LM_WR1_MASK 0x8
+#define MC_ARB_BUSY_STATUS__LM_WR1__SHIFT 0x3
+#define MC_ARB_BUSY_STATUS__HM_RD0_MASK 0x10
+#define MC_ARB_BUSY_STATUS__HM_RD0__SHIFT 0x4
+#define MC_ARB_BUSY_STATUS__HM_RD1_MASK 0x20
+#define MC_ARB_BUSY_STATUS__HM_RD1__SHIFT 0x5
+#define MC_ARB_BUSY_STATUS__HM_WR0_MASK 0x40
+#define MC_ARB_BUSY_STATUS__HM_WR0__SHIFT 0x6
+#define MC_ARB_BUSY_STATUS__HM_WR1_MASK 0x80
+#define MC_ARB_BUSY_STATUS__HM_WR1__SHIFT 0x7
+#define MC_ARB_BUSY_STATUS__WDE_RD0_MASK 0x100
+#define MC_ARB_BUSY_STATUS__WDE_RD0__SHIFT 0x8
+#define MC_ARB_BUSY_STATUS__WDE_RD1_MASK 0x200
+#define MC_ARB_BUSY_STATUS__WDE_RD1__SHIFT 0x9
+#define MC_ARB_BUSY_STATUS__WDE_WR0_MASK 0x400
+#define MC_ARB_BUSY_STATUS__WDE_WR0__SHIFT 0xa
+#define MC_ARB_BUSY_STATUS__WDE_WR1_MASK 0x800
+#define MC_ARB_BUSY_STATUS__WDE_WR1__SHIFT 0xb
+#define MC_ARB_BUSY_STATUS__POP0_MASK 0x1000
+#define MC_ARB_BUSY_STATUS__POP0__SHIFT 0xc
+#define MC_ARB_BUSY_STATUS__POP1_MASK 0x2000
+#define MC_ARB_BUSY_STATUS__POP1__SHIFT 0xd
+#define MC_ARB_BUSY_STATUS__TAGFIFO0_MASK 0x4000
+#define MC_ARB_BUSY_STATUS__TAGFIFO0__SHIFT 0xe
+#define MC_ARB_BUSY_STATUS__TAGFIFO1_MASK 0x8000
+#define MC_ARB_BUSY_STATUS__TAGFIFO1__SHIFT 0xf
+#define MC_ARB_BUSY_STATUS__REPLAY0_MASK 0x10000
+#define MC_ARB_BUSY_STATUS__REPLAY0__SHIFT 0x10
+#define MC_ARB_BUSY_STATUS__REPLAY1_MASK 0x20000
+#define MC_ARB_BUSY_STATUS__REPLAY1__SHIFT 0x11
+#define MC_ARB_BUSY_STATUS__RDRET0_MASK 0x40000
+#define MC_ARB_BUSY_STATUS__RDRET0__SHIFT 0x12
+#define MC_ARB_BUSY_STATUS__RDRET1_MASK 0x80000
+#define MC_ARB_BUSY_STATUS__RDRET1__SHIFT 0x13
+#define MC_ARB_BUSY_STATUS__GECC2_RD0_MASK 0x100000
+#define MC_ARB_BUSY_STATUS__GECC2_RD0__SHIFT 0x14
+#define MC_ARB_BUSY_STATUS__GECC2_RD1_MASK 0x200000
+#define MC_ARB_BUSY_STATUS__GECC2_RD1__SHIFT 0x15
+#define MC_ARB_BUSY_STATUS__GECC2_WR0_MASK 0x400000
+#define MC_ARB_BUSY_STATUS__GECC2_WR0__SHIFT 0x16
+#define MC_ARB_BUSY_STATUS__GECC2_WR1_MASK 0x800000
+#define MC_ARB_BUSY_STATUS__GECC2_WR1__SHIFT 0x17
+#define MC_ARB_BUSY_STATUS__WCDR0_MASK 0x1000000
+#define MC_ARB_BUSY_STATUS__WCDR0__SHIFT 0x18
+#define MC_ARB_BUSY_STATUS__WCDR1_MASK 0x2000000
+#define MC_ARB_BUSY_STATUS__WCDR1__SHIFT 0x19
+#define MC_ARB_BUSY_STATUS__RTT0_MASK 0x4000000
+#define MC_ARB_BUSY_STATUS__RTT0__SHIFT 0x1a
+#define MC_ARB_BUSY_STATUS__RTT1_MASK 0x8000000
+#define MC_ARB_BUSY_STATUS__RTT1__SHIFT 0x1b
+#define MC_ARB_BUSY_STATUS__REM_RD0_MASK 0x10000000
+#define MC_ARB_BUSY_STATUS__REM_RD0__SHIFT 0x1c
+#define MC_ARB_BUSY_STATUS__REM_RD1_MASK 0x20000000
+#define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d
+#define MC_ARB_BUSY_STATUS__REM_WR0_MASK 0x40000000
+#define MC_ARB_BUSY_STATUS__REM_WR0__SHIFT 0x1e
+#define MC_ARB_BUSY_STATUS__REM_WR1_MASK 0x80000000
+#define MC_ARB_BUSY_STATUS__REM_WR1__SHIFT 0x1f
+#define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0xff
+#define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x0
+#define MC_ARB_DRAM_TIMING2_1__RP_MASK 0xff00
+#define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x8
+#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0xff0000
+#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x10
+#define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000
+#define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x18
+#define MC_ARB_BURST_TIME__STATE0_MASK 0x1f
+#define MC_ARB_BURST_TIME__STATE0__SHIFT 0x0
+#define MC_ARB_BURST_TIME__STATE1_MASK 0x3e0
+#define MC_ARB_BURST_TIME__STATE1__SHIFT 0x5
+#define MC_ARB_BURST_TIME__STATE2_MASK 0x7c00
+#define MC_ARB_BURST_TIME__STATE2__SHIFT 0xa
+#define MC_ARB_BURST_TIME__STATE3_MASK 0xf8000
+#define MC_ARB_BURST_TIME__STATE3__SHIFT 0xf
+#define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x1
+#define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x0
+#define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x2
+#define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x1
+#define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x4
+#define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x2
+#define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x8
+#define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x3
+#define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x10
+#define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x4
+#define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0xf00
+#define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x8
+#define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x1000
+#define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0xc
+#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL_MASK 0x6000
+#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL__SHIFT 0xd
+#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL_MASK 0x18000
+#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL__SHIFT 0xf
+#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL_MASK 0x60000
+#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL__SHIFT 0x11
+#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL_MASK 0x180000
+#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL__SHIFT 0x13
+#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL_MASK 0x600000
+#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL__SHIFT 0x15
+#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL_MASK 0x1800000
+#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL__SHIFT 0x17
+#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE_MASK 0x2000000
+#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE__SHIFT 0x19
+#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE_MASK 0x4000000
+#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE__SHIFT 0x1a
+#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE_MASK 0x8000000
+#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE__SHIFT 0x1b
+#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE_MASK 0x10000000
+#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE__SHIFT 0x1c
+#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE_MASK 0x60000000
+#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d
+#define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x1e
+#define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x1
+#define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x1
+#define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
+#define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x2
+#define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
+#define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x4
+#define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
+#define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
+#define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
+#define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x30
+#define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x4
+#define MC_CG_CONFIG__INDEX_MASK 0x3fffc0
+#define MC_CG_CONFIG__INDEX__SHIFT 0x6
+#define MC_CITF_CNTL__IGNOREPM_MASK 0x4
+#define MC_CITF_CNTL__IGNOREPM__SHIFT 0x2
+#define MC_CITF_CNTL__EXEMPTPM_MASK 0x8
+#define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x3
+#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x30
+#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x4
+#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x40
+#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x6
+#define MC_CITF_CNTL__CNTR_CHMAP_MODE_MASK 0x80
+#define MC_CITF_CNTL__CNTR_CHMAP_MODE__SHIFT 0x7
+#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE_MASK 0x100
+#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE__SHIFT 0x8
+#define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x3f
+#define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x0
+#define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0xfc0
+#define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x6
+#define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0xff
+#define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x0
+#define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0xff00
+#define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x8
+#define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0xff0000
+#define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x10
+#define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x1000000
+#define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x18
+#define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x2000000
+#define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x19
+#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0xff
+#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x0
+#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0xff00
+#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x8
+#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x10000
+#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x10
+#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x20000
+#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x11
+#define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x1
+#define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x0
+#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x1e
+#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x1
+#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x20
+#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x5
+#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x3c0
+#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x6
+#define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x3f
+#define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x0
+#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x3f000
+#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0xc
+#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0xfc0000
+#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x12
+#define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000
+#define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x18
+#define MC_CITF_RET_MODE__INORDER_RD_MASK 0x1
+#define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x0
+#define MC_CITF_RET_MODE__INORDER_WR_MASK 0x2
+#define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x1
+#define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x4
+#define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x2
+#define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x8
+#define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x3
+#define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x10
+#define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x4
+#define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x20
+#define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x5
+#define MC_CITF_DAGB_DLY__DLY_MASK 0x1f
+#define MC_CITF_DAGB_DLY__DLY__SHIFT 0x0
+#define MC_CITF_DAGB_DLY__CLI_MASK 0x1f0000
+#define MC_CITF_DAGB_DLY__CLI__SHIFT 0x10
+#define MC_CITF_DAGB_DLY__POS_MASK 0x1f000000
+#define MC_CITF_DAGB_DLY__POS__SHIFT 0x18
+#define MC_RD_GRP_EXT__DBSTEN0_MASK 0xf
+#define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x0
+#define MC_RD_GRP_EXT__TC0_MASK 0xf0
+#define MC_RD_GRP_EXT__TC0__SHIFT 0x4
+#define MC_WR_GRP_EXT__DBSTEN0_MASK 0xf
+#define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x0
+#define MC_WR_GRP_EXT__TC0_MASK 0xf0
+#define MC_WR_GRP_EXT__TC0__SHIFT 0x4
+#define MC_CITF_REMREQ__READ_CREDITS_MASK 0x7f
+#define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x0
+#define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x3f80
+#define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x7
+#define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x4000
+#define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0xe
+#define MC_WR_TC0__ENABLE_MASK 0x1
+#define MC_WR_TC0__ENABLE__SHIFT 0x0
+#define MC_WR_TC0__PRESCALE_MASK 0x6
+#define MC_WR_TC0__PRESCALE__SHIFT 0x1
+#define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_WR_TC0__STALL_MODE_MASK 0x30
+#define MC_WR_TC0__STALL_MODE__SHIFT 0x4
+#define MC_WR_TC0__STALL_OVERRIDE_MASK 0x40
+#define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_WR_TC0__MAX_BURST_MASK 0x780
+#define MC_WR_TC0__MAX_BURST__SHIFT 0x7
+#define MC_WR_TC0__LAZY_TIMER_MASK 0x7800
+#define MC_WR_TC0__LAZY_TIMER__SHIFT 0xb
+#define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_WR_TC1__ENABLE_MASK 0x1
+#define MC_WR_TC1__ENABLE__SHIFT 0x0
+#define MC_WR_TC1__PRESCALE_MASK 0x6
+#define MC_WR_TC1__PRESCALE__SHIFT 0x1
+#define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_WR_TC1__STALL_MODE_MASK 0x30
+#define MC_WR_TC1__STALL_MODE__SHIFT 0x4
+#define MC_WR_TC1__STALL_OVERRIDE_MASK 0x40
+#define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_WR_TC1__MAX_BURST_MASK 0x780
+#define MC_WR_TC1__MAX_BURST__SHIFT 0x7
+#define MC_WR_TC1__LAZY_TIMER_MASK 0x7800
+#define MC_WR_TC1__LAZY_TIMER__SHIFT 0xb
+#define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x3f
+#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x0
+#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0xfc0
+#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x6
+#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x7
+#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x0
+#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x38
+#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x3
+#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x1c0
+#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x6
+#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0xe00
+#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x9
+#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x7000
+#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0xc
+#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x38000
+#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0xf
+#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
+#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x12
+#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0xe00000
+#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x15
+#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x1000000
+#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x18
+#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL_MASK 0x2000000
+#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL__SHIFT 0x19
+#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x7
+#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x0
+#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x38
+#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x3
+#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x1c0
+#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x6
+#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0xe00
+#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x9
+#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x7000
+#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0xc
+#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x38000
+#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0xf
+#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
+#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x12
+#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0xe00000
+#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x15
+#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x1000000
+#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x18
+#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL_MASK 0x2000000
+#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL__SHIFT 0x19
+#define MC_RD_CB__ENABLE_MASK 0x1
+#define MC_RD_CB__ENABLE__SHIFT 0x0
+#define MC_RD_CB__PRESCALE_MASK 0x6
+#define MC_RD_CB__PRESCALE__SHIFT 0x1
+#define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_RD_CB__STALL_MODE_MASK 0x30
+#define MC_RD_CB__STALL_MODE__SHIFT 0x4
+#define MC_RD_CB__STALL_OVERRIDE_MASK 0x40
+#define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_RD_CB__MAX_BURST_MASK 0x780
+#define MC_RD_CB__MAX_BURST__SHIFT 0x7
+#define MC_RD_CB__LAZY_TIMER_MASK 0x7800
+#define MC_RD_CB__LAZY_TIMER__SHIFT 0xb
+#define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_RD_DB__ENABLE_MASK 0x1
+#define MC_RD_DB__ENABLE__SHIFT 0x0
+#define MC_RD_DB__PRESCALE_MASK 0x6
+#define MC_RD_DB__PRESCALE__SHIFT 0x1
+#define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_RD_DB__STALL_MODE_MASK 0x30
+#define MC_RD_DB__STALL_MODE__SHIFT 0x4
+#define MC_RD_DB__STALL_OVERRIDE_MASK 0x40
+#define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_RD_DB__MAX_BURST_MASK 0x780
+#define MC_RD_DB__MAX_BURST__SHIFT 0x7
+#define MC_RD_DB__LAZY_TIMER_MASK 0x7800
+#define MC_RD_DB__LAZY_TIMER__SHIFT 0xb
+#define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_RD_TC0__ENABLE_MASK 0x1
+#define MC_RD_TC0__ENABLE__SHIFT 0x0
+#define MC_RD_TC0__PRESCALE_MASK 0x6
+#define MC_RD_TC0__PRESCALE__SHIFT 0x1
+#define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_RD_TC0__STALL_MODE_MASK 0x30
+#define MC_RD_TC0__STALL_MODE__SHIFT 0x4
+#define MC_RD_TC0__STALL_OVERRIDE_MASK 0x40
+#define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_RD_TC0__MAX_BURST_MASK 0x780
+#define MC_RD_TC0__MAX_BURST__SHIFT 0x7
+#define MC_RD_TC0__LAZY_TIMER_MASK 0x7800
+#define MC_RD_TC0__LAZY_TIMER__SHIFT 0xb
+#define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_RD_TC1__ENABLE_MASK 0x1
+#define MC_RD_TC1__ENABLE__SHIFT 0x0
+#define MC_RD_TC1__PRESCALE_MASK 0x6
+#define MC_RD_TC1__PRESCALE__SHIFT 0x1
+#define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_RD_TC1__STALL_MODE_MASK 0x30
+#define MC_RD_TC1__STALL_MODE__SHIFT 0x4
+#define MC_RD_TC1__STALL_OVERRIDE_MASK 0x40
+#define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_RD_TC1__MAX_BURST_MASK 0x780
+#define MC_RD_TC1__MAX_BURST__SHIFT 0x7
+#define MC_RD_TC1__LAZY_TIMER_MASK 0x7800
+#define MC_RD_TC1__LAZY_TIMER__SHIFT 0xb
+#define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_RD_HUB__ENABLE_MASK 0x1
+#define MC_RD_HUB__ENABLE__SHIFT 0x0
+#define MC_RD_HUB__PRESCALE_MASK 0x6
+#define MC_RD_HUB__PRESCALE__SHIFT 0x1
+#define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_RD_HUB__STALL_MODE_MASK 0x30
+#define MC_RD_HUB__STALL_MODE__SHIFT 0x4
+#define MC_RD_HUB__STALL_OVERRIDE_MASK 0x40
+#define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_RD_HUB__MAX_BURST_MASK 0x780
+#define MC_RD_HUB__MAX_BURST__SHIFT 0x7
+#define MC_RD_HUB__LAZY_TIMER_MASK 0x7800
+#define MC_RD_HUB__LAZY_TIMER__SHIFT 0xb
+#define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_WR_CB__ENABLE_MASK 0x1
+#define MC_WR_CB__ENABLE__SHIFT 0x0
+#define MC_WR_CB__PRESCALE_MASK 0x6
+#define MC_WR_CB__PRESCALE__SHIFT 0x1
+#define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_WR_CB__STALL_MODE_MASK 0x30
+#define MC_WR_CB__STALL_MODE__SHIFT 0x4
+#define MC_WR_CB__STALL_OVERRIDE_MASK 0x40
+#define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_WR_CB__MAX_BURST_MASK 0x780
+#define MC_WR_CB__MAX_BURST__SHIFT 0x7
+#define MC_WR_CB__LAZY_TIMER_MASK 0x7800
+#define MC_WR_CB__LAZY_TIMER__SHIFT 0xb
+#define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_WR_DB__ENABLE_MASK 0x1
+#define MC_WR_DB__ENABLE__SHIFT 0x0
+#define MC_WR_DB__PRESCALE_MASK 0x6
+#define MC_WR_DB__PRESCALE__SHIFT 0x1
+#define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_WR_DB__STALL_MODE_MASK 0x30
+#define MC_WR_DB__STALL_MODE__SHIFT 0x4
+#define MC_WR_DB__STALL_OVERRIDE_MASK 0x40
+#define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_WR_DB__MAX_BURST_MASK 0x780
+#define MC_WR_DB__MAX_BURST__SHIFT 0x7
+#define MC_WR_DB__LAZY_TIMER_MASK 0x7800
+#define MC_WR_DB__LAZY_TIMER__SHIFT 0xb
+#define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_WR_HUB__ENABLE_MASK 0x1
+#define MC_WR_HUB__ENABLE__SHIFT 0x0
+#define MC_WR_HUB__PRESCALE_MASK 0x6
+#define MC_WR_HUB__PRESCALE__SHIFT 0x1
+#define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_WR_HUB__STALL_MODE_MASK 0x30
+#define MC_WR_HUB__STALL_MODE__SHIFT 0x4
+#define MC_WR_HUB__STALL_OVERRIDE_MASK 0x40
+#define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_WR_HUB__MAX_BURST_MASK 0x780
+#define MC_WR_HUB__MAX_BURST__SHIFT 0x7
+#define MC_WR_HUB__LAZY_TIMER_MASK 0x7800
+#define MC_WR_HUB__LAZY_TIMER__SHIFT 0xb
+#define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0xff
+#define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x0
+#define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0xff00
+#define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x8
+#define MC_RD_GRP_LCL__CB0_MASK 0xf000
+#define MC_RD_GRP_LCL__CB0__SHIFT 0xc
+#define MC_RD_GRP_LCL__CBCMASK0_MASK 0xf0000
+#define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x10
+#define MC_RD_GRP_LCL__CBFMASK0_MASK 0xf00000
+#define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x14
+#define MC_RD_GRP_LCL__DB0_MASK 0xf000000
+#define MC_RD_GRP_LCL__DB0__SHIFT 0x18
+#define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000
+#define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x1c
+#define MC_WR_GRP_LCL__CB0_MASK 0xf
+#define MC_WR_GRP_LCL__CB0__SHIFT 0x0
+#define MC_WR_GRP_LCL__CBCMASK0_MASK 0xf0
+#define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x4
+#define MC_WR_GRP_LCL__CBFMASK0_MASK 0xf00
+#define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x8
+#define MC_WR_GRP_LCL__DB0_MASK 0xf000
+#define MC_WR_GRP_LCL__DB0__SHIFT 0xc
+#define MC_WR_GRP_LCL__DBHTILE0_MASK 0xf0000
+#define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x10
+#define MC_WR_GRP_LCL__SX0_MASK 0xf00000
+#define MC_WR_GRP_LCL__SX0__SHIFT 0x14
+#define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000
+#define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x1c
+#define MC_CITF_PERF_MON_CNTL2__CID_MASK 0xff
+#define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x0
+#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x40
+#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x6
+#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x80
+#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x7
+#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x100
+#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x8
+#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x200
+#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x9
+#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x400
+#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0xa
+#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x800
+#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0xb
+#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x1000
+#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0xc
+#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x2000
+#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0xd
+#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x4000
+#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0xe
+#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x8000
+#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0xf
+#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x10000
+#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0x10
+#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x20000
+#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0x11
+#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x40000
+#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0x12
+#define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x3f
+#define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x0
+#define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0xfc0
+#define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x6
+#define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x3f000
+#define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0xc
+#define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x40000
+#define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x12
+#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x3f
+#define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x0
+#define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0xfc0
+#define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x6
+#define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x3f000
+#define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0xc
+#define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x40000
+#define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x12
+#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x3f
+#define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x0
+#define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0xfc0
+#define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x6
+#define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x3f000
+#define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0xc
+#define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x40000
+#define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x12
+#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x4
+#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x2
+#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x18
+#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x3
+#define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x3f
+#define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x0
+#define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0xfc0
+#define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x6
+#define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x3f000
+#define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0xc
+#define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x40000
+#define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x12
+#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x3f
+#define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x0
+#define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0xfc0
+#define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x6
+#define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x3f000
+#define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0xc
+#define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x40000
+#define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x12
+#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x3f
+#define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x0
+#define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0xfc0
+#define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x6
+#define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x3f000
+#define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0xc
+#define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x40000
+#define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x12
+#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_HUB_MISC_DBG__SELECT0_MASK 0xf
+#define MC_HUB_MISC_DBG__SELECT0__SHIFT 0x0
+#define MC_HUB_MISC_DBG__SELECT1_MASK 0xf0
+#define MC_HUB_MISC_DBG__SELECT1__SHIFT 0x4
+#define MC_HUB_MISC_DBG__CTRL0_MASK 0x1f00
+#define MC_HUB_MISC_DBG__CTRL0__SHIFT 0x8
+#define MC_HUB_MISC_DBG__CTRL1_MASK 0x3e000
+#define MC_HUB_MISC_DBG__CTRL1__SHIFT 0xd
+#define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x1
+#define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x0
+#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x2
+#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x1
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x4
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x2
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x8
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x3
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x10
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x4
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x20
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x5
+#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x40
+#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x6
+#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x80
+#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0x7
+#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x100
+#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0x8
+#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x200
+#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0x9
+#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x400
+#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0xa
+#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x800
+#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0xb
+#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x1000
+#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0xc
+#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x2000
+#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0xd
+#define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x3
+#define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x0
+#define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffff
+#define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x0
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x2
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x1
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x4
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x2
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x8
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x3
+#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
+#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
+#define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x1fe0
+#define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x5
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x2000
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0xd
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x4000
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0xe
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x8000
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0xf
+#define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x10000
+#define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x10
+#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x20000
+#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x11
+#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x40000
+#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x12
+#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x80000
+#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x13
+#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x100000
+#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x14
+#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x1
+#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x0
+#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x2
+#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x1
+#define MC_HUB_WDP_BP__ENABLE_MASK 0x1
+#define MC_HUB_WDP_BP__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_BP__RDRET_MASK 0x3fffe
+#define MC_HUB_WDP_BP__RDRET__SHIFT 0x1
+#define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000
+#define MC_HUB_WDP_BP__WRREQ__SHIFT 0x12
+#define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x1
+#define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x0
+#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x2
+#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
+#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x4
+#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
+#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x8
+#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
+#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x10
+#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
+#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x20
+#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x5
+#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x40
+#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x6
+#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80
+#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x7
+#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x100
+#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x8
+#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x200
+#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x9
+#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400
+#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xa
+#define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x1
+#define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x0
+#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x2
+#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
+#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x4
+#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
+#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x8
+#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
+#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x10
+#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
+#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x20
+#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x5
+#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x40
+#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0x6
+#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80
+#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x7
+#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x100
+#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0x8
+#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x200
+#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0x9
+#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400
+#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xa
+#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x800
+#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0xb
+#define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x1
+#define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x0
+#define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x2
+#define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x1
+#define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x4
+#define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x2
+#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x8
+#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x3
+#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x1
+#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x0
+#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x4
+#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x2
+#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x8
+#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x3
+#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
+#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
+#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x20
+#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x5
+#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x40
+#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x6
+#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x80
+#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x7
+#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x100
+#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x8
+#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x200
+#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0x9
+#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x1fc00
+#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0xa
+#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x20000
+#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x11
+#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x40000
+#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x12
+#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x80000
+#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x13
+#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE_MASK 0x100000
+#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE__SHIFT 0x14
+#define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x1
+#define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x0
+#define MC_HUB_WRRET_CNTL__BP_MASK 0x1ffffe
+#define MC_HUB_WRRET_CNTL__BP__SHIFT 0x1
+#define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x200000
+#define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x15
+#define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000
+#define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x16
+#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000
+#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x1e
+#define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000
+#define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x1f
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
+#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
+#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
+#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
+#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
+#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
+#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
+#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
+#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
+#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
+#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
+#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
+#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
+#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
+#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
+#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
+#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
+#define MC_HUB_WDP_CREDITS__VM0_MASK 0xff
+#define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS__VM1_MASK 0xff00
+#define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x8
+#define MC_HUB_WDP_CREDITS__STOR0_MASK 0xff0000
+#define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x10
+#define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000
+#define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x18
+#define MC_HUB_WDP_MGPU2__CID2_MASK 0xff
+#define MC_HUB_WDP_MGPU2__CID2__SHIFT 0x0
+#define MC_HUB_WDP_GBL0__MAXBURST_MASK 0xf
+#define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x0
+#define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0xf0
+#define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x4
+#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0xff00
+#define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x8
+#define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x10000
+#define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x10
+#define MC_HUB_WDP_GBL1__MAXBURST_MASK 0xf
+#define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x0
+#define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0xf0
+#define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x4
+#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0xff00
+#define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x8
+#define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x10000
+#define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x10
+#define MC_HUB_WDP_MGPU__STOR_MASK 0xff
+#define MC_HUB_WDP_MGPU__STOR__SHIFT 0x0
+#define MC_HUB_WDP_MGPU__CID_MASK 0xff00
+#define MC_HUB_WDP_MGPU__CID__SHIFT 0x8
+#define MC_HUB_WDP_MGPU__MGPU_PRIORITY_TIME_MASK 0x7f0000
+#define MC_HUB_WDP_MGPU__MGPU_PRIORITY_TIME__SHIFT 0x10
+#define MC_HUB_WDP_MGPU__ENABLE_MASK 0x800000
+#define MC_HUB_WDP_MGPU__ENABLE__SHIFT 0x17
+#define MC_HUB_WDP_MGPU__OTH_PRIORITY_TIME_MASK 0x7f000000
+#define MC_HUB_WDP_MGPU__OTH_PRIORITY_TIME__SHIFT 0x18
+#define MC_HUB_RDREQ_CREDITS__VM0_MASK 0xff
+#define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x0
+#define MC_HUB_RDREQ_CREDITS__VM1_MASK 0xff00
+#define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x8
+#define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0xff0000
+#define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x10
+#define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000
+#define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x18
+#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0xff
+#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x0
+#define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x3f
+#define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x0
+#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x1f0000
+#define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x10
+#define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000
+#define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x18
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x1
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x0
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x2
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x1
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x4
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x2
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x8
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x3
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ_MASK 0x10
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ__SHIFT 0x4
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE_MASK 0x20
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE__SHIFT 0x5
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ_MASK 0x40
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ__SHIFT 0x6
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE_MASK 0x80
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE__SHIFT 0x7
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x100
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x8
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x200
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x9
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x400
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0xa
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x800
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0xb
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x1000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0xc
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x2000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0xd
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x4000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0xe
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x8000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0xf
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x10000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x10
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x20000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x11
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x40000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x12
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x80000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x13
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_READ_MASK 0x100000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_READ__SHIFT 0x14
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_WRITE_MASK 0x200000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_WRITE__SHIFT 0x15
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x400000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x16
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x800000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x17
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ_MASK 0x1000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ__SHIFT 0x18
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE_MASK 0x2000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE__SHIFT 0x19
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ_MASK 0x4000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ__SHIFT 0x1a
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE_MASK 0x8000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE__SHIFT 0x1b
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ_MASK 0x10000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ__SHIFT 0x1c
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE_MASK 0x20000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT 0x1d
+#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x3
+#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x7c
+#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x2
+#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE_MASK 0x3
+#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT_MASK 0x7c
+#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT__SHIFT 0x2
+#define MC_HUB_WDP_SH2__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SH2__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SH2__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SH2__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SH2__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SH2__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SH2__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SH2__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SH2__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SH2__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SH2__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SH2__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SH3__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SH3__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SH3__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SH3__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SH3__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SH3__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SH3__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SH3__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SH3__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SH3__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SH3__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SH3__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_IA0__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_IA0__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_IA0__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_IA0__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_IA0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_IA0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_IA0__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_IA0__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_IA0__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_IA0__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_IA0__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_IA0__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_IA1__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_IA1__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_IA1__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_IA1__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_IA1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_IA1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_IA1__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_IA1__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_IA1__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_IA1__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_IA1__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_IA1__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDW__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD__SHIFT 0x19
+#define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDX__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD__SHIFT 0x19
+#define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDY__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD__SHIFT 0x19
+#define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD__SHIFT 0x19
+#define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x7f
+#define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x0
+#define MC_HUB_RDREQ_SIP__DUMMY_MASK 0x80
+#define MC_HUB_RDREQ_SIP__DUMMY__SHIFT 0x7
+#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x7f00
+#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x8
+#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0xff
+#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x0
+#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0xff
+#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x0
+#define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_CPG__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_CPG__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_CPG__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_CPG__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_CPG__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_CPG__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_CPG__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_CPG__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_CPG__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_CPG__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_CPG__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_CPG__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_SDMA0__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_SDMA0__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_SDMA0__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_SDMA0__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_SDMA0__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_SDMA0__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_SDMA0__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_SDMA0__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_SDMA1__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_SDMA1__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_SDMA1__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_SDMA1__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_SDMA1__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_SDMA1__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_SDMA1__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_SDMA1__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_VCE__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_VCE__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_VCE__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_VCE__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_VCE__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_VCE__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_VCE__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_VCE__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_VCE__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_VCE__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x10000
+#define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x10
+#define MC_HUB_RDREQ_IA__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_IA__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_IA__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_IA__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_IA__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_IA__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_IA__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_IA__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_IA__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_IA__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_IA__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_IA__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_IA__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_VCEU__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_VCEU__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_VCEU__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_VCEU__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_VCEU__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_VCEU__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_VCEU__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_VCEU__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_VCEU__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_VCEU__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_MCDW__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_MCDX__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_MCDY__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x3
+#define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x1fc
+#define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x2
+#define MC_HUB_WDP_CPG__ENABLE_MASK 0x1
+#define MC_HUB_WDP_CPG__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_CPG__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_CPG__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_CPG__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_CPG__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_CPG__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_CPG__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_CPG__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_CPG__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_CPG__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_CPG__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_CPG__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_CPG__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_CPG__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_CPG__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SDMA1__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SDMA1__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SDMA1__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SDMA1__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SDMA1__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SDMA1__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SDMA1__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SDMA1__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SDMA1__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SDMA1__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SH0__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SH0__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SH0__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_MCIF__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_VCE__ENABLE_MASK 0x1
+#define MC_HUB_WDP_VCE__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_VCE__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_VCE__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_VCE__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_VCE__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_VCE__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_VCE__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_VCE__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_VCE__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_VCE__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_VCE__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_XDP__ENABLE_MASK 0x1
+#define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_XDP__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_XDP__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_IH__ENABLE_MASK 0x1
+#define MC_HUB_WDP_IH__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_IH__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_IH__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_IH__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_RLC__ENABLE_MASK 0x1
+#define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_RLC__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_RLC__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SEM__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SEM__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SEM__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SMU__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SMU__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SMU__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SH1__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SH1__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SH1__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_UMC__ENABLE_MASK 0x1
+#define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_UMC__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_UMC__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_UVD__ENABLE_MASK 0x1
+#define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_UVD__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_UVD__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x10000
+#define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x10
+#define MC_HUB_WDP_HDP__ENABLE_MASK 0x1
+#define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_HDP__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_HDP__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SDMA0__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SDMA0__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SDMA0__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SDMA0__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SDMA0__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SDMA0__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SDMA0__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SDMA0__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SDMA0__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SDMA0__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WDP_VCEU__ENABLE_MASK 0x1
+#define MC_HUB_WDP_VCEU__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_VCEU__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_VCEU__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_VCEU__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_VCEU__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_VCEU__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_VCEU__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_VCEU__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_VCEU__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_VCEU__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x1
+#define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_XDMA__ENABLE_MASK 0x1
+#define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_ACPG__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_ACPG__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_ACPG__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_ACPG__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_ACPG__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_ACPG__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_ACPG__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_ACPG__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_ACPG__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_ACPG__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_RDREQ_ACPO__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_ACPO__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_ACPO__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_ACPO__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_ACPO__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_ACPO__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_ACPO__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_ACPO__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_ACPO__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_ACPO__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_RDREQ_SAM__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_SAM__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_SAM__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_SAM__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_SAM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_SAM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_SAM__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_SAM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_SAM__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_SAM__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_SAM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_SAM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_ACPG__ENABLE_MASK 0x1
+#define MC_HUB_WDP_ACPG__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_ACPG__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_ACPG__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_ACPG__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_ACPG__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_ACPG__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_ACPG__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_ACPG__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_ACPG__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_ACPG__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_WDP_ACPG__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_WDP_ACPG__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_WDP_ACPO__ENABLE_MASK 0x1
+#define MC_HUB_WDP_ACPO__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_ACPO__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_ACPO__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_ACPO__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_ACPO__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_ACPO__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_ACPO__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_ACPO__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_ACPO__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_ACPO__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_WDP_ACPO__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_WDP_ACPO__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_WDP_SAM__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SAM__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SAM__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SAM__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SAM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SAM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SAM__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SAM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SAM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SAM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SAM__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SAM__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SAM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SAM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SAM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SAM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_CPC__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_CPC__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_CPC__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_CPC__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_CPC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_CPC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_CPC__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_CPC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_CPC__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_CPC__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_CPC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_CPC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_CPF__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_CPF__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_CPF__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_CPF__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_CPF__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_CPF__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_CPF__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_CPF__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_CPF__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_CPF__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_CPF__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_CPF__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_CPC__ENABLE_MASK 0x1
+#define MC_HUB_WDP_CPC__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_CPC__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_CPC__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_CPC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_CPC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_CPC__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_CPC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_CPC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_CPC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_CPC__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_CPC__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_CPC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_CPC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_CPC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_CPC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_CPF__ENABLE_MASK 0x1
+#define MC_HUB_WDP_CPF__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_CPF__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_CPF__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_CPF__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_CPF__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_CPF__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_CPF__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_CPF__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_CPF__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_CPF__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_CPF__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_CPF__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_CPF__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_CPF__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_CPF__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x8000
+#define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0xf
+#define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x10000
+#define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x10
+#define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x20000
+#define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x11
+#define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0xff
+#define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x0
+#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0xff00
+#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x8
+#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0xff
+#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x0
+#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0xfff00
+#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x8
+#define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000
+#define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x14
+#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0xff
+#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0
+#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0xff00
+#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8
+#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0xff
+#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x0
+#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0xff00
+#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x8
+#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0xff0000
+#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x10
+#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0xff
+#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x0
+#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0xff00
+#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x8
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
+#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x1
+#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x0
+#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x6
+#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x1
+#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x78
+#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x3
+#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x80
+#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x7
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
+#define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0xff
+#define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x0
+#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x100
+#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x8
+#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x600
+#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x9
+#define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x1800
+#define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xb
+#define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x2000
+#define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd
+#define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0xff
+#define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x0
+#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x300
+#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x8
+#define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0xc00
+#define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xa
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x3
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x4
+#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2
+#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x8
+#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3
+#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x10
+#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4
+#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x1e0
+#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x3e00
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x7c000
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0xf80000
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18
+#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffff
+#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0
+#define MC_RPB_CID_QUEUE_EX__START_MASK 0x1
+#define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x0
+#define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x3e
+#define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1
+#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0xffff
+#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0
+#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000
+#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10
+#define MC_SHARED_CHMAP__CHAN0_MASK 0xf
+#define MC_SHARED_CHMAP__CHAN0__SHIFT 0x0
+#define MC_SHARED_CHMAP__CHAN1_MASK 0xf0
+#define MC_SHARED_CHMAP__CHAN1__SHIFT 0x4
+#define MC_SHARED_CHMAP__CHAN2_MASK 0xf00
+#define MC_SHARED_CHMAP__CHAN2__SHIFT 0x8
+#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000
+#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc
+#define MC_SHARED_CHREMAP__CHAN0_MASK 0x7
+#define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x0
+#define MC_SHARED_CHREMAP__CHAN1_MASK 0x38
+#define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x3
+#define MC_SHARED_CHREMAP__CHAN2_MASK 0x1c0
+#define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x6
+#define MC_SHARED_CHREMAP__CHAN3_MASK 0xe00
+#define MC_SHARED_CHREMAP__CHAN3__SHIFT 0x9
+#define MC_SHARED_CHREMAP__CHAN4_MASK 0x7000
+#define MC_SHARED_CHREMAP__CHAN4__SHIFT 0xc
+#define MC_SHARED_CHREMAP__CHAN5_MASK 0x38000
+#define MC_SHARED_CHREMAP__CHAN5__SHIFT 0xf
+#define MC_SHARED_CHREMAP__CHAN6_MASK 0x1c0000
+#define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x12
+#define MC_SHARED_CHREMAP__CHAN7_MASK 0xe00000
+#define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x15
+#define MC_RD_GRP_GFX__CP_MASK 0xf
+#define MC_RD_GRP_GFX__CP__SHIFT 0x0
+#define MC_RD_GRP_GFX__SH_MASK 0xf0
+#define MC_RD_GRP_GFX__SH__SHIFT 0x4
+#define MC_RD_GRP_GFX__IA_MASK 0xf00
+#define MC_RD_GRP_GFX__IA__SHIFT 0x8
+#define MC_RD_GRP_GFX__ACPG_MASK 0xf000
+#define MC_RD_GRP_GFX__ACPG__SHIFT 0xc
+#define MC_RD_GRP_GFX__ACPO_MASK 0xf0000
+#define MC_RD_GRP_GFX__ACPO__SHIFT 0x10
+#define MC_RD_GRP_GFX__XDMAM_MASK 0xf00000
+#define MC_RD_GRP_GFX__XDMAM__SHIFT 0x14
+#define MC_WR_GRP_GFX__CP_MASK 0xf
+#define MC_WR_GRP_GFX__CP__SHIFT 0x0
+#define MC_WR_GRP_GFX__SH_MASK 0xf0
+#define MC_WR_GRP_GFX__SH__SHIFT 0x4
+#define MC_WR_GRP_GFX__ACPG_MASK 0xf00
+#define MC_WR_GRP_GFX__ACPG__SHIFT 0x8
+#define MC_WR_GRP_GFX__ACPO_MASK 0xf000
+#define MC_WR_GRP_GFX__ACPO__SHIFT 0xc
+#define MC_WR_GRP_GFX__XDMA_MASK 0xf0000
+#define MC_WR_GRP_GFX__XDMA__SHIFT 0x10
+#define MC_WR_GRP_GFX__XDMAM_MASK 0xf00000
+#define MC_WR_GRP_GFX__XDMAM__SHIFT 0x14
+#define MC_RD_GRP_SYS__RLC_MASK 0xf
+#define MC_RD_GRP_SYS__RLC__SHIFT 0x0
+#define MC_RD_GRP_SYS__VMC_MASK 0xf0
+#define MC_RD_GRP_SYS__VMC__SHIFT 0x4
+#define MC_RD_GRP_SYS__SDMA1_MASK 0xf00
+#define MC_RD_GRP_SYS__SDMA1__SHIFT 0x8
+#define MC_RD_GRP_SYS__DMIF_MASK 0xf000
+#define MC_RD_GRP_SYS__DMIF__SHIFT 0xc
+#define MC_RD_GRP_SYS__MCIF_MASK 0xf0000
+#define MC_RD_GRP_SYS__MCIF__SHIFT 0x10
+#define MC_RD_GRP_SYS__SMU_MASK 0xf00000
+#define MC_RD_GRP_SYS__SMU__SHIFT 0x14
+#define MC_RD_GRP_SYS__VCE_MASK 0xf000000
+#define MC_RD_GRP_SYS__VCE__SHIFT 0x18
+#define MC_RD_GRP_SYS__VCEU_MASK 0xf0000000
+#define MC_RD_GRP_SYS__VCEU__SHIFT 0x1c
+#define MC_WR_GRP_SYS__IH_MASK 0xf
+#define MC_WR_GRP_SYS__IH__SHIFT 0x0
+#define MC_WR_GRP_SYS__MCIF_MASK 0xf0
+#define MC_WR_GRP_SYS__MCIF__SHIFT 0x4
+#define MC_WR_GRP_SYS__RLC_MASK 0xf00
+#define MC_WR_GRP_SYS__RLC__SHIFT 0x8
+#define MC_WR_GRP_SYS__SAM_MASK 0xf000
+#define MC_WR_GRP_SYS__SAM__SHIFT 0xc
+#define MC_WR_GRP_SYS__SMU_MASK 0xf0000
+#define MC_WR_GRP_SYS__SMU__SHIFT 0x10
+#define MC_WR_GRP_SYS__SDMA1_MASK 0xf00000
+#define MC_WR_GRP_SYS__SDMA1__SHIFT 0x14
+#define MC_WR_GRP_SYS__VCE_MASK 0xf000000
+#define MC_WR_GRP_SYS__VCE__SHIFT 0x18
+#define MC_WR_GRP_SYS__VCEU_MASK 0xf0000000
+#define MC_WR_GRP_SYS__VCEU__SHIFT 0x1c
+#define MC_RD_GRP_OTH__UVD_EXT0_MASK 0xf
+#define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x0
+#define MC_RD_GRP_OTH__SDMA0_MASK 0xf0
+#define MC_RD_GRP_OTH__SDMA0__SHIFT 0x4
+#define MC_RD_GRP_OTH__HDP_MASK 0xf00
+#define MC_RD_GRP_OTH__HDP__SHIFT 0x8
+#define MC_RD_GRP_OTH__SEM_MASK 0xf000
+#define MC_RD_GRP_OTH__SEM__SHIFT 0xc
+#define MC_RD_GRP_OTH__UMC_MASK 0xf0000
+#define MC_RD_GRP_OTH__UMC__SHIFT 0x10
+#define MC_RD_GRP_OTH__UVD_MASK 0xf00000
+#define MC_RD_GRP_OTH__UVD__SHIFT 0x14
+#define MC_RD_GRP_OTH__UVD_EXT1_MASK 0xf000000
+#define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x18
+#define MC_RD_GRP_OTH__SAM_MASK 0xf0000000
+#define MC_RD_GRP_OTH__SAM__SHIFT 0x1c
+#define MC_WR_GRP_OTH__UVD_EXT0_MASK 0xf
+#define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x0
+#define MC_WR_GRP_OTH__SDMA0_MASK 0xf0
+#define MC_WR_GRP_OTH__SDMA0__SHIFT 0x4
+#define MC_WR_GRP_OTH__HDP_MASK 0xf00
+#define MC_WR_GRP_OTH__HDP__SHIFT 0x8
+#define MC_WR_GRP_OTH__SEM_MASK 0xf000
+#define MC_WR_GRP_OTH__SEM__SHIFT 0xc
+#define MC_WR_GRP_OTH__UMC_MASK 0xf0000
+#define MC_WR_GRP_OTH__UMC__SHIFT 0x10
+#define MC_WR_GRP_OTH__UVD_MASK 0xf00000
+#define MC_WR_GRP_OTH__UVD__SHIFT 0x14
+#define MC_WR_GRP_OTH__XDP_MASK 0xf000000
+#define MC_WR_GRP_OTH__XDP__SHIFT 0x18
+#define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000
+#define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x1c
+#define MC_VM_FB_LOCATION__FB_BASE_MASK 0xffff
+#define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x0
+#define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000
+#define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x10
+#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x3ffff
+#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
+#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x3ffff
+#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
+#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x3ffff
+#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x3
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x0
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0xc
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x2
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x30
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x4
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0xc0
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x6
+#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x100
+#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x8
+#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x200
+#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x9
+#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x1
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x2
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x1
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x18
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x20
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x40
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
+#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x780
+#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
+#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x3ffff
+#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
+#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x3
+#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
+#define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
+#define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
+#define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
+#define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
+#define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
+#define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
+#define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
+#define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
+#define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
+#define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
+#define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
+#define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
+#define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
+#define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
+#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000
+#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x1f
+#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
+#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
+#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
+#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
+#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
+#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
+#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
+#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
+#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
+#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
+#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
+#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
+#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
+#define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
+#define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000
+#define MC_CG_CONFIG_MCD__INDEX__SHIFT 0xd
+#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x3f
+#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
+#define MC_MEM_POWER_LS__LS_HOLD_MASK 0xfc0
+#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
+#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x7
+#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x0
+#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x1
+#define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x1
+#define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x1
+#define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
+#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
+#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x1
+#define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x1
+#define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x1
+#define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x1
+#define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
+#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
+#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x1
+#define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
+#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
+#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
+#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
+#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
+#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
+#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
+#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
+#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_EXTRA__CMP0_MASK 0xff
+#define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x0
+#define MC_XPB_CLG_EXTRA__MSK0_MASK 0xff00
+#define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x8
+#define MC_XPB_CLG_EXTRA__VLD0_MASK 0x10000
+#define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x10
+#define MC_XPB_CLG_EXTRA__CMP1_MASK 0x1fe0000
+#define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x11
+#define MC_XPB_CLG_EXTRA__VLD1_MASK 0x2000000
+#define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x19
+#define MC_XPB_LB_ADDR__CMP0_MASK 0x3ff
+#define MC_XPB_LB_ADDR__CMP0__SHIFT 0x0
+#define MC_XPB_LB_ADDR__MASK0_MASK 0xffc00
+#define MC_XPB_LB_ADDR__MASK0__SHIFT 0xa
+#define MC_XPB_LB_ADDR__CMP1_MASK 0x3f00000
+#define MC_XPB_LB_ADDR__CMP1__SHIFT 0x14
+#define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000
+#define MC_XPB_LB_ADDR__MASK1__SHIFT 0x1a
+#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x3f
+#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x0
+#define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0xfc0
+#define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x6
+#define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x3f000
+#define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0xc
+#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x3f
+#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x0
+#define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0xfc0
+#define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x6
+#define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x3f000
+#define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0xc
+#define MC_XPB_WCB_STS__PBUF_VLD_MASK 0xffff
+#define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x0
+#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x7f0000
+#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10
+#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000
+#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17
+#define MC_XPB_WCB_CFG__TIMEOUT_MASK 0xffff
+#define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x0
+#define MC_XPB_WCB_CFG__HST_MAX_MASK 0x30000
+#define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x10
+#define MC_XPB_WCB_CFG__SID_MAX_MASK 0xc0000
+#define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x12
+#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0xf
+#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0
+#define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x30
+#define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x40
+#define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6
+#define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x80
+#define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7
+#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x100
+#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8
+#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x200
+#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9
+#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x400
+#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa
+#define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x800
+#define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb
+#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x1000
+#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc
+#define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR0__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR0__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR0__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR1__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR1__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR1__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR2__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR2__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR2__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR3__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR3__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR3__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR4__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR4__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR4__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR5__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR5__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR5__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR6__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR6__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR6__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR7__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR7__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR7__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0xff
+#define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0
+#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0xff
+#define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x0
+#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0xf00
+#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x8
+#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0xf000
+#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0xc
+#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0xff
+#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0
+#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0xfffff00
+#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8
+#define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0xff
+#define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0
+#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0xfffff00
+#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8
+#define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0
+#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
+#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0
+#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
+#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0
+#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
+#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0
+#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
+#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x2
+#define MC_XPB_CLK_GAT__ONDLY_MASK 0x3f
+#define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x0
+#define MC_XPB_CLK_GAT__OFFDLY_MASK 0xfc0
+#define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x6
+#define MC_XPB_CLK_GAT__RDYDLY_MASK 0x3f000
+#define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0xc
+#define MC_XPB_CLK_GAT__ENABLE_MASK 0x40000
+#define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x12
+#define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x80000
+#define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0xff
+#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0
+#define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0xff00
+#define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8
+#define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x7f0000
+#define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10
+#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x800000
+#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17
+#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x1000000
+#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18
+#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x2000000
+#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19
+#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x4000000
+#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a
+#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000
+#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b
+#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000
+#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d
+#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000
+#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e
+#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000
+#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f
+#define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0xff
+#define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0
+#define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x7f00
+#define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8
+#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x8000
+#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf
+#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x10000
+#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10
+#define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x20000
+#define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11
+#define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x40000
+#define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12
+#define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x7f80000
+#define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13
+#define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x1
+#define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0
+#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0xfe
+#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1
+#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x7f00
+#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8
+#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x8000
+#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf
+#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x10000
+#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10
+#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x20000
+#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11
+#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x40000
+#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12
+#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x80000
+#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13
+#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x100000
+#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14
+#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x200000
+#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15
+#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x400000
+#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16
+#define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x800000
+#define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17
+#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000
+#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18
+#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x1
+#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0
+#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x2
+#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1
+#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x4
+#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2
+#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x8
+#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3
+#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x10
+#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4
+#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x20
+#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5
+#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x40
+#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6
+#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x80
+#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7
+#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x100
+#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8
+#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x200
+#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9
+#define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x400
+#define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa
+#define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x800
+#define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb
+#define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x1000
+#define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0xc
+#define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x2000
+#define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd
+#define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x4000
+#define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe
+#define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x8000
+#define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0xf
+#define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x10000
+#define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10
+#define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x20000
+#define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x11
+#define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x40000
+#define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12
+#define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x80000
+#define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13
+#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0xffff
+#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0
+#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x3f
+#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0
+#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0xfc0
+#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6
+#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x3f000
+#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc
+#define MC_XPB_STICKY__BITS_MASK 0xffffffff
+#define MC_XPB_STICKY__BITS__SHIFT 0x0
+#define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffff
+#define MC_XPB_STICKY_W1C__BITS__SHIFT 0x0
+#define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0xff
+#define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0
+#define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0xff00
+#define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8
+#define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0xff0000
+#define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10
+#define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000
+#define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18
+#define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000
+#define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f
+#define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0xff
+#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0
+#define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0xff
+#define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x0
+#define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0xff00
+#define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x8
+#define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x10000
+#define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x10
+#define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x1fe0000
+#define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x11
+#define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x2000000
+#define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x19
+#define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0xe
+#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x1
+#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3__SHIFT 0x0
+#define MC_XBAR_ADDR_DEC__GECC_MASK 0x2
+#define MC_XBAR_ADDR_DEC__GECC__SHIFT 0x1
+#define MC_XBAR_ADDR_DEC__RB_SPLIT_MASK 0x4
+#define MC_XBAR_ADDR_DEC__RB_SPLIT__SHIFT 0x2
+#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI_MASK 0x8
+#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI__SHIFT 0x3
+#define MC_XBAR_REMOTE__WRREQ_EN_GOQ_MASK 0x1
+#define MC_XBAR_REMOTE__WRREQ_EN_GOQ__SHIFT 0x0
+#define MC_XBAR_REMOTE__RDREQ_EN_GOQ_MASK 0x2
+#define MC_XBAR_REMOTE__RDREQ_EN_GOQ__SHIFT 0x1
+#define MC_XBAR_WRREQ_CREDIT__OUT0_MASK 0xff
+#define MC_XBAR_WRREQ_CREDIT__OUT0__SHIFT 0x0
+#define MC_XBAR_WRREQ_CREDIT__OUT1_MASK 0xff00
+#define MC_XBAR_WRREQ_CREDIT__OUT1__SHIFT 0x8
+#define MC_XBAR_WRREQ_CREDIT__OUT2_MASK 0xff0000
+#define MC_XBAR_WRREQ_CREDIT__OUT2__SHIFT 0x10
+#define MC_XBAR_WRREQ_CREDIT__OUT3_MASK 0xff000000
+#define MC_XBAR_WRREQ_CREDIT__OUT3__SHIFT 0x18
+#define MC_XBAR_RDREQ_CREDIT__OUT0_MASK 0xff
+#define MC_XBAR_RDREQ_CREDIT__OUT0__SHIFT 0x0
+#define MC_XBAR_RDREQ_CREDIT__OUT1_MASK 0xff00
+#define MC_XBAR_RDREQ_CREDIT__OUT1__SHIFT 0x8
+#define MC_XBAR_RDREQ_CREDIT__OUT2_MASK 0xff0000
+#define MC_XBAR_RDREQ_CREDIT__OUT2__SHIFT 0x10
+#define MC_XBAR_RDREQ_CREDIT__OUT3_MASK 0xff000000
+#define MC_XBAR_RDREQ_CREDIT__OUT3__SHIFT 0x18
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0_MASK 0xff
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0__SHIFT 0x0
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1_MASK 0xff00
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1__SHIFT 0x8
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2_MASK 0xff0000
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2__SHIFT 0x10
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3_MASK 0xff000000
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3__SHIFT 0x18
+#define MC_XBAR_WRRET_CREDIT1__OUT0_MASK 0xff
+#define MC_XBAR_WRRET_CREDIT1__OUT0__SHIFT 0x0
+#define MC_XBAR_WRRET_CREDIT1__OUT1_MASK 0xff00
+#define MC_XBAR_WRRET_CREDIT1__OUT1__SHIFT 0x8
+#define MC_XBAR_WRRET_CREDIT1__OUT2_MASK 0xff0000
+#define MC_XBAR_WRRET_CREDIT1__OUT2__SHIFT 0x10
+#define MC_XBAR_WRRET_CREDIT1__OUT3_MASK 0xff000000
+#define MC_XBAR_WRRET_CREDIT1__OUT3__SHIFT 0x18
+#define MC_XBAR_WRRET_CREDIT2__OUT4_MASK 0xff
+#define MC_XBAR_WRRET_CREDIT2__OUT4__SHIFT 0x0
+#define MC_XBAR_WRRET_CREDIT2__OUT5_MASK 0xff00
+#define MC_XBAR_WRRET_CREDIT2__OUT5__SHIFT 0x8
+#define MC_XBAR_RDRET_CREDIT1__OUT0_MASK 0xff
+#define MC_XBAR_RDRET_CREDIT1__OUT0__SHIFT 0x0
+#define MC_XBAR_RDRET_CREDIT1__OUT1_MASK 0xff00
+#define MC_XBAR_RDRET_CREDIT1__OUT1__SHIFT 0x8
+#define MC_XBAR_RDRET_CREDIT1__OUT2_MASK 0xff0000
+#define MC_XBAR_RDRET_CREDIT1__OUT2__SHIFT 0x10
+#define MC_XBAR_RDRET_CREDIT1__OUT3_MASK 0xff000000
+#define MC_XBAR_RDRET_CREDIT1__OUT3__SHIFT 0x18
+#define MC_XBAR_RDRET_CREDIT2__OUT4_MASK 0xff
+#define MC_XBAR_RDRET_CREDIT2__OUT4__SHIFT 0x0
+#define MC_XBAR_RDRET_CREDIT2__OUT5_MASK 0xff00
+#define MC_XBAR_RDRET_CREDIT2__OUT5__SHIFT 0x8
+#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID_MASK 0xff0000
+#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID__SHIFT 0x10
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0_MASK 0xff
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0__SHIFT 0x0
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1_MASK 0xff00
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1__SHIFT 0x8
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2_MASK 0xff0000
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2__SHIFT 0x10
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3_MASK 0xff000000
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3__SHIFT 0x18
+#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4_MASK 0xff
+#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4__SHIFT 0x0
+#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5_MASK 0xff00
+#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5__SHIFT 0x8
+#define MC_XBAR_CHTRIREMAP__CH0_MASK 0x3
+#define MC_XBAR_CHTRIREMAP__CH0__SHIFT 0x0
+#define MC_XBAR_CHTRIREMAP__CH1_MASK 0xc
+#define MC_XBAR_CHTRIREMAP__CH1__SHIFT 0x2
+#define MC_XBAR_CHTRIREMAP__CH2_MASK 0x30
+#define MC_XBAR_CHTRIREMAP__CH2__SHIFT 0x4
+#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT_MASK 0x1
+#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT__SHIFT 0x0
+#define MC_XBAR_TWOCHAN__CH0_MASK 0x6
+#define MC_XBAR_TWOCHAN__CH0__SHIFT 0x1
+#define MC_XBAR_TWOCHAN__CH1_MASK 0x18
+#define MC_XBAR_TWOCHAN__CH1__SHIFT 0x3
+#define MC_XBAR_ARB__HUBRD_HIGHEST_MASK 0x1
+#define MC_XBAR_ARB__HUBRD_HIGHEST__SHIFT 0x0
+#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST_MASK 0x2
+#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST__SHIFT 0x1
+#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE_MASK 0x4
+#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE__SHIFT 0x2
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT0_MASK 0xf
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT0__SHIFT 0x0
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT1_MASK 0xf0
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT1__SHIFT 0x4
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT2_MASK 0xf00
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT2__SHIFT 0x8
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT3_MASK 0xf000
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT3__SHIFT 0xc
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT0_MASK 0xf0000
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT0__SHIFT 0x10
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT1_MASK 0xf00000
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT1__SHIFT 0x14
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT2_MASK 0xf000000
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT2__SHIFT 0x18
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT3_MASK 0xf0000000
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT3__SHIFT 0x1c
+#define MC_XBAR_PERF_MON_CNTL0__START_THRESH_MASK 0xfff
+#define MC_XBAR_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0
+#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000
+#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc
+#define MC_XBAR_PERF_MON_CNTL0__START_MODE_MASK 0x3000000
+#define MC_XBAR_PERF_MON_CNTL0__START_MODE__SHIFT 0x18
+#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000
+#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a
+#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000
+#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c
+#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0xff
+#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0
+#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xff00
+#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x8
+#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0xff0000
+#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x10
+#define MC_XBAR_PERF_MON_CNTL2__MON0_ID_MASK 0xff
+#define MC_XBAR_PERF_MON_CNTL2__MON0_ID__SHIFT 0x0
+#define MC_XBAR_PERF_MON_CNTL2__MON1_ID_MASK 0xff00
+#define MC_XBAR_PERF_MON_CNTL2__MON1_ID__SHIFT 0x8
+#define MC_XBAR_PERF_MON_CNTL2__MON2_ID_MASK 0xff0000
+#define MC_XBAR_PERF_MON_CNTL2__MON2_ID__SHIFT 0x10
+#define MC_XBAR_PERF_MON_CNTL2__MON3_ID_MASK 0xff000000
+#define MC_XBAR_PERF_MON_CNTL2__MON3_ID__SHIFT 0x18
+#define MC_XBAR_PERF_MON_RSLT0__COUNT_MASK 0xffffffff
+#define MC_XBAR_PERF_MON_RSLT0__COUNT__SHIFT 0x0
+#define MC_XBAR_PERF_MON_RSLT1__COUNT_MASK 0xffffffff
+#define MC_XBAR_PERF_MON_RSLT1__COUNT__SHIFT 0x0
+#define MC_XBAR_PERF_MON_RSLT2__COUNT_MASK 0xffffffff
+#define MC_XBAR_PERF_MON_RSLT2__COUNT__SHIFT 0x0
+#define MC_XBAR_PERF_MON_RSLT3__COUNT_MASK 0xffffffff
+#define MC_XBAR_PERF_MON_RSLT3__COUNT__SHIFT 0x0
+#define MC_XBAR_PERF_MON_MAX_THSH__MON0_MASK 0xff
+#define MC_XBAR_PERF_MON_MAX_THSH__MON0__SHIFT 0x0
+#define MC_XBAR_PERF_MON_MAX_THSH__MON1_MASK 0xff00
+#define MC_XBAR_PERF_MON_MAX_THSH__MON1__SHIFT 0x8
+#define MC_XBAR_PERF_MON_MAX_THSH__MON2_MASK 0xff0000
+#define MC_XBAR_PERF_MON_MAX_THSH__MON2__SHIFT 0x10
+#define MC_XBAR_PERF_MON_MAX_THSH__MON3_MASK 0xff000000
+#define MC_XBAR_PERF_MON_MAX_THSH__MON3__SHIFT 0x18
+#define MC_XBAR_SPARE0__BIT_MASK 0xffffffff
+#define MC_XBAR_SPARE0__BIT__SHIFT 0x0
+#define MC_XBAR_SPARE1__BIT_MASK 0xffffffff
+#define MC_XBAR_SPARE1__BIT__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_CITF_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_CITF_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_CITF_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_CITF_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_CITF_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_CITF_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_CITF_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_CITF_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_CITF_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_CITF_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_CITF_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_CITF_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_CITF_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_CITF_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_CITF_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_CITF_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_HUB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_HUB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_HUB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_HUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_HUB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_HUB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_HUB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_HUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_HUB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_HUB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_HUB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_HUB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_HUB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_HUB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_HUB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_HUB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_ARB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_ARB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_ARB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_ARB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_ARB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_ARB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_ARB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_ARB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_ARB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_ARB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_ARB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_ARB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_ARB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_ARB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_ARB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_ARB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_ARB_PERF_MON_CNTL0_ECC__ALLOW_WRAP_MASK 0x1
+#define MC_ARB_PERF_MON_CNTL0_ECC__ALLOW_WRAP__SHIFT 0x0
+#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
+#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
+#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
+#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
+#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
+#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
+#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
+#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
+#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x3
+#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x0
+#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x3
+#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x0
+#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0xffff
+#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0
+#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0xffff
+#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0
+#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x1
+#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0
+#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x2
+#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1
+#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x4
+#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2
+#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x3f00
+#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
+#define ATC_ATS_CNTL__DEBUG_ECO_MASK 0xf0000
+#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x10
+#define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x1
+#define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x0
+#define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x2
+#define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x1
+#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x4
+#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x2
+#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x20
+#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x5
+#define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x40
+#define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x6
+#define ATC_ATS_DEBUG__EXE_BIT_MASK 0x80
+#define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x7
+#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x100
+#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x8
+#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x200
+#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x9
+#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x3c00
+#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0xa
+#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x4000
+#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0xe
+#define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x8000
+#define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0xf
+#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x10000
+#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x10
+#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT_MASK 0x20000
+#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT__SHIFT 0x11
+#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x1f
+#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x0
+#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x100
+#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x8
+#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x10000
+#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x10
+#define ATC_ATS_STATUS__BUSY_MASK 0x1
+#define ATC_ATS_STATUS__BUSY__SHIFT 0x0
+#define ATC_ATS_STATUS__CRASHED_MASK 0x2
+#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1
+#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x4
+#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2
+#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x3f
+#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0
+#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0xfc00
+#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa
+#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x3f00000
+#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14
+#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x3f
+#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0
+#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x7c00
+#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x8000
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x10000
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10
+#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x20000
+#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x40000
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12
+#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0xf80000
+#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0xf000000
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18
+#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffff
+#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0
+#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xffffffff
+#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0
+#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x1
+#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x0
+#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH_MASK 0x3c
+#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH__SHIFT 0x2
+#define ATC_MISC_CG__OFFDLY_MASK 0xfc0
+#define ATC_MISC_CG__OFFDLY__SHIFT 0x6
+#define ATC_MISC_CG__ENABLE_MASK 0x40000
+#define ATC_MISC_CG__ENABLE__SHIFT 0x12
+#define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x80000
+#define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x3
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x30
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x4
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x100
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x8
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x200
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x9
+#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x3f
+#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0xc0
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6
+#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x100
+#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8
+#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0xe00
+#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9
+#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x7000
+#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f8000
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf
+#define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x3f
+#define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x0
+#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE_MASK 0x1f
+#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE__SHIFT 0x0
+#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0xe0
+#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x5
+#define ATC_L2_DEBUG2__FORCE_CACHE_MISS_MASK 0x100
+#define ATC_L2_DEBUG2__FORCE_CACHE_MISS__SHIFT 0x8
+#define ATC_L2_DEBUG2__INVALIDATE_ALL_MASK 0x200
+#define ATC_L2_DEBUG2__INVALIDATE_ALL__SHIFT 0x9
+#define ATC_L2_DEBUG2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x400
+#define ATC_L2_DEBUG2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0xa
+#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_READ_RETURNS_MASK 0x800
+#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_READ_RETURNS__SHIFT 0xb
+#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS_MASK 0x1000
+#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS__SHIFT 0xc
+#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS_MASK 0x4000
+#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0xe
+#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT_MASK 0x18000
+#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT__SHIFT 0xf
+#define ATC_L2_DEBUG2__DEBUG_ECO_MASK 0x60000
+#define ATC_L2_DEBUG2__DEBUG_ECO__SHIFT 0x11
+#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x3
+#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x0
+#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x4
+#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x2
+#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x10
+#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x4
+#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffff
+#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x0
+#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
+#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
+#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
+#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
+#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
+#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
+#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
+#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
+#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
+#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
+#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
+#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
+#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
+#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
+#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
+#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
+#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000
+#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f
+#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
+#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
+#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
+#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
+#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
+#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
+#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
+#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
+#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
+#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
+#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
+#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
+#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
+#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
+#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
+#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
+#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000
+#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f
+#define ATC_L1RD_STATUS__BUSY_MASK 0x1
+#define ATC_L1RD_STATUS__BUSY__SHIFT 0x0
+#define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x2
+#define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
+#define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x100
+#define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x8
+#define ATC_L1WR_STATUS__BUSY_MASK 0x1
+#define ATC_L1WR_STATUS__BUSY__SHIFT 0x0
+#define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x2
+#define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
+#define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x100
+#define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x8
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x1
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x2
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x4
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x8
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x10
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x20
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x40
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x80
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x100
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x200
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x400
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x800
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x1000
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x2000
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x4000
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x8000
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf
+#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f
+#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x3ff
+#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0
+#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffff
+#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x1
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x2
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0xffc
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x3ff000
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0xc
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc00000
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x16
+#define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x400
+#define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0xa
+#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x800
+#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0xb
+#define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0xf000
+#define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0xc
+#define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x10000
+#define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x10
+#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x60000
+#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x11
+#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x180000
+#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x13
+#define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x200000
+#define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x15
+#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x400000
+#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x16
+#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x800000
+#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x17
+#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x1000000
+#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x18
+#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x2000000
+#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x19
+#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x4000000
+#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x1a
+#define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x8000000
+#define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x1b
+#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x70000000
+#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1c
+#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x80000000
+#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x1f
+#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0_MASK 0x7
+#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0__SHIFT 0x0
+#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1_MASK 0x38
+#define GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1__SHIFT 0x3
+#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD_MASK 0x7c0
+#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD__SHIFT 0x6
+#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x1f800
+#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0xb
+#define GMCON_MISC2__STCTRL_LPT_TARGET_MASK 0x1ffe0000
+#define GMCON_MISC2__STCTRL_LPT_TARGET__SHIFT 0x11
+#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x20000000
+#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x1d
+#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x40000000
+#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x1e
+#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE_MASK 0x80000000
+#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE__SHIFT 0x1f
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0xffff
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x0
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff0000
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x10
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0xffff
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x0
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff0000
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x10
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0xffff
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x0
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff0000
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x10
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0xffff
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff0000
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0xffff
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff0000
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10
+#define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0xfff
+#define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0
+#define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000
+#define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc
+#define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x3000000
+#define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x18
+#define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000
+#define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a
+#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000
+#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c
+#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x3f
+#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0
+#define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xfc0
+#define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x6
+#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x3f000
+#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0xc
+#define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0xfc0000
+#define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x12
+#define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0x3f000000
+#define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x18
+#define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffff
+#define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x0
+#define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffff
+#define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x0
+#define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0xff
+#define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
+#define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x100
+#define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
+#define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x200
+#define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
+#define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x400
+#define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
+#define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x800
+#define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
+#define GMCON_PGFSM_CONFIG__WRITE_MASK 0x1000
+#define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0xc
+#define GMCON_PGFSM_CONFIG__READ_MASK 0x2000
+#define GMCON_PGFSM_CONFIG__READ__SHIFT 0xd
+#define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x7ffc000
+#define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0xe
+#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000
+#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
+#define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000
+#define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
+#define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffff
+#define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x0
+#define GMCON_PGFSM_READ__READ_VALUE_MASK 0xffffff
+#define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x0
+#define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0xf000000
+#define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x18
+#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x10000000
+#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x1c
+#define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0x3f
+#define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x0
+#define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0xfc0
+#define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x6
+#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0xfff000
+#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xc
+#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER_MASK 0x1000000
+#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER__SHIFT 0x18
+#define GMCON_MISC3__RENG_MEM_LS_ENABLE_MASK 0x2000000
+#define GMCON_MISC3__RENG_MEM_LS_ENABLE__SHIFT 0x19
+#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS_MASK 0x4000000
+#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS__SHIFT 0x1a
+#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD_MASK 0x1
+#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD__SHIFT 0x0
+#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR_MASK 0x2
+#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR__SHIFT 0x1
+#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD_MASK 0x4
+#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD__SHIFT 0x2
+#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR_MASK 0x8
+#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR__SHIFT 0x3
+#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK_MASK 0x3f0
+#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK__SHIFT 0x4
+#define GMCON_DEBUG__GFX_STALL_MASK 0x1
+#define GMCON_DEBUG__GFX_STALL__SHIFT 0x0
+#define GMCON_DEBUG__GFX_CLEAR_MASK 0x2
+#define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x1
+#define GMCON_DEBUG__MISC_FLAGS_MASK 0x3ffffffc
+#define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x2
+#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x1
+#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
+#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x2
+#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
+#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0xc
+#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
+#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x30
+#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
+#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x100
+#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
+#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x200
+#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
+#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400
+#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
+#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x800
+#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
+#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x7000
+#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
+#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x38000
+#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
+#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x40000
+#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
+#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x180000
+#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
+#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x3e00000
+#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
+#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0xc000000
+#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a
+#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000
+#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c
+#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x1
+#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
+#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x2
+#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
+#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x200000
+#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
+#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x400000
+#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
+#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x3800000
+#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17
+#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0xc000000
+#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
+#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000
+#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
+#define VM_L2_CNTL3__BANK_SELECT_MASK 0x3f
+#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0xc0
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f00
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0xf8000
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
+#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x100000
+#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
+#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0xe00000
+#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
+#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0xf000000
+#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
+#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000
+#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
+#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000
+#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
+#define VM_L2_STATUS__L2_BUSY_MASK 0x1
+#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0
+#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x1fffe
+#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
+#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x1
+#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x6
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14
+#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000
+#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000
+#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000
+#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18
+#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x1
+#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x6
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14
+#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000
+#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000
+#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000
+#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x1
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x2
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK 0xc
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT 0x2
+#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK 0xfffffff
+#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT 0x0
+#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1
+#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
+#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2
+#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1
+#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4
+#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2
+#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8
+#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3
+#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10
+#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4
+#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1
+#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
+#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2
+#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1
+#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4
+#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2
+#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8
+#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3
+#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10
+#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK 0x1
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT 0x0
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK 0x2
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT 0x1
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK 0x4
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT 0x2
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK 0x8
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT 0x3
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK 0x10
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT 0x4
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK 0x20
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT 0x5
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK 0x40
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT 0x6
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK 0x80
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT 0x7
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK 0x100
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT 0x8
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK 0x200
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT 0x9
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK 0x400
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT 0xa
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK 0x800
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT 0xb
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK 0x1000
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT 0xc
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK 0x2000
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT 0xd
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK 0x4000
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT 0xe
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK 0x8000
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT 0xf
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK 0x1
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT 0x0
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK 0x2
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT 0x1
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK 0x4
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT 0x2
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK 0x8
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT 0x3
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK 0x10
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT 0x4
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK 0x20
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT 0x5
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK 0x40
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT 0x6
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK 0x80
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT 0x7
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK 0x100
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT 0x8
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK 0x200
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT 0x9
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK 0x400
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT 0xa
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK 0x800
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT 0xb
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK 0x1000
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT 0xc
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK 0x2000
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT 0xd
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK 0x4000
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT 0xe
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK 0x8000
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT 0xf
+#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x1
+#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x0
+#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x2
+#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x1
+#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x4
+#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x2
+#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK 0x8
+#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x3
+#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x10
+#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x4
+#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x20
+#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x5
+#define VM_PRT_CNTL__MASK_PDE0_FAULT_MASK 0x40
+#define VM_PRT_CNTL__MASK_PDE0_FAULT__SHIFT 0x6
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x1
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x2
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x4
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x8
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x10
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x20
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x40
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x80
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x100
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x200
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x400
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x800
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x1000
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x2000
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x4000
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x8000
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0xff000
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0xff000
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
+#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff
+#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0
+#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff
+#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0
+#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
+#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
+#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
+#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
+#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff
+#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0
+#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff
+#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK 0x1ff
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT 0x0
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK 0x3fe00
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT 0x9
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_DEBUG__FLAGS_MASK 0xffffffff
+#define VM_DEBUG__FLAGS__SHIFT 0x0
+#define VM_L2_CG__OFFDLY_MASK 0xfc0
+#define VM_L2_CG__OFFDLY__SHIFT 0x6
+#define VM_L2_CG__ENABLE_MASK 0x40000
+#define VM_L2_CG__ENABLE__SHIFT 0x12
+#define VM_L2_CG__MEM_LS_ENABLE_MASK 0x80000
+#define VM_L2_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK 0xfffffff
+#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT 0x0
+#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK 0xff
+#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK 0xfffffff
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT 0x0
+#define MC_ARB_HARSH_EN_RD__TX_PRI_MASK 0xff
+#define MC_ARB_HARSH_EN_RD__TX_PRI__SHIFT 0x0
+#define MC_ARB_HARSH_EN_RD__BW_PRI_MASK 0xff00
+#define MC_ARB_HARSH_EN_RD__BW_PRI__SHIFT 0x8
+#define MC_ARB_HARSH_EN_RD__FIX_PRI_MASK 0xff0000
+#define MC_ARB_HARSH_EN_RD__FIX_PRI__SHIFT 0x10
+#define MC_ARB_HARSH_EN_RD__ST_PRI_MASK 0xff000000
+#define MC_ARB_HARSH_EN_RD__ST_PRI__SHIFT 0x18
+#define MC_ARB_HARSH_EN_WR__TX_PRI_MASK 0xff
+#define MC_ARB_HARSH_EN_WR__TX_PRI__SHIFT 0x0
+#define MC_ARB_HARSH_EN_WR__BW_PRI_MASK 0xff00
+#define MC_ARB_HARSH_EN_WR__BW_PRI__SHIFT 0x8
+#define MC_ARB_HARSH_EN_WR__FIX_PRI_MASK 0xff0000
+#define MC_ARB_HARSH_EN_WR__FIX_PRI__SHIFT 0x10
+#define MC_ARB_HARSH_EN_WR__ST_PRI_MASK 0xff000000
+#define MC_ARB_HARSH_EN_WR__ST_PRI__SHIFT 0x18
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_SAT0_RD__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_SAT0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_SAT0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_SAT0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_SAT0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_SAT0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_SAT0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_SAT0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_SAT0_WR__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_SAT0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_SAT0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_SAT0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_SAT0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_SAT0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_SAT0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_SAT0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_SAT1_RD__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_SAT1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_SAT1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_SAT1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_SAT1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_SAT1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_SAT1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_SAT1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_SAT1_WR__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_SAT1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_SAT1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_SAT1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_SAT1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_SAT1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_SAT1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_SAT1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST_MASK 0xff
+#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST__SHIFT 0x0
+#define MC_ARB_HARSH_CTL_RD__HARSH_RR_MASK 0x100
+#define MC_ARB_HARSH_CTL_RD__HARSH_RR__SHIFT 0x8
+#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY_MASK 0x200
+#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY__SHIFT 0x9
+#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH_MASK 0x400
+#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH__SHIFT 0xa
+#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP_MASK 0x800
+#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP__SHIFT 0xb
+#define MC_ARB_HARSH_CTL_RD__ST_MODE_MASK 0x3000
+#define MC_ARB_HARSH_CTL_RD__ST_MODE__SHIFT 0xc
+#define MC_ARB_HARSH_CTL_RD__FORCE_STALL_MASK 0x3fc000
+#define MC_ARB_HARSH_CTL_RD__FORCE_STALL__SHIFT 0xe
+#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL_MASK 0x1c00000
+#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL__SHIFT 0x16
+#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST_MASK 0xff
+#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST__SHIFT 0x0
+#define MC_ARB_HARSH_CTL_WR__HARSH_RR_MASK 0x100
+#define MC_ARB_HARSH_CTL_WR__HARSH_RR__SHIFT 0x8
+#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY_MASK 0x200
+#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY__SHIFT 0x9
+#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH_MASK 0x400
+#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH__SHIFT 0xa
+#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP_MASK 0x800
+#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP__SHIFT 0xb
+#define MC_ARB_HARSH_CTL_WR__ST_MODE_MASK 0x3000
+#define MC_ARB_HARSH_CTL_WR__ST_MODE__SHIFT 0xc
+#define MC_ARB_HARSH_CTL_WR__FORCE_STALL_MASK 0x3fc000
+#define MC_ARB_HARSH_CTL_WR__FORCE_STALL__SHIFT 0xe
+#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL_MASK 0x1c00000
+#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL__SHIFT 0x16
+#define MC_FUS_DRAM0_CS0_BASE__CSENABLE_MASK 0x1
+#define MC_FUS_DRAM0_CS0_BASE__CSENABLE__SHIFT 0x0
+#define MC_FUS_DRAM0_CS0_BASE__BASEADDR21_11_MASK 0xffe0
+#define MC_FUS_DRAM0_CS0_BASE__BASEADDR21_11__SHIFT 0x5
+#define MC_FUS_DRAM0_CS0_BASE__BASEADDR38_27_MASK 0x7ff80000
+#define MC_FUS_DRAM0_CS0_BASE__BASEADDR38_27__SHIFT 0x13
+#define MC_FUS_DRAM1_CS0_BASE__CSENABLE_MASK 0x1
+#define MC_FUS_DRAM1_CS0_BASE__CSENABLE__SHIFT 0x0
+#define MC_FUS_DRAM1_CS0_BASE__BASEADDR21_11_MASK 0xffe0
+#define MC_FUS_DRAM1_CS0_BASE__BASEADDR21_11__SHIFT 0x5
+#define MC_FUS_DRAM1_CS0_BASE__BASEADDR38_27_MASK 0x7ff80000
+#define MC_FUS_DRAM1_CS0_BASE__BASEADDR38_27__SHIFT 0x13
+#define MC_FUS_DRAM0_CS1_BASE__CSENABLE_MASK 0x1
+#define MC_FUS_DRAM0_CS1_BASE__CSENABLE__SHIFT 0x0
+#define MC_FUS_DRAM0_CS1_BASE__BASEADDR21_11_MASK 0xffe0
+#define MC_FUS_DRAM0_CS1_BASE__BASEADDR21_11__SHIFT 0x5
+#define MC_FUS_DRAM0_CS1_BASE__BASEADDR38_27_MASK 0x7ff80000
+#define MC_FUS_DRAM0_CS1_BASE__BASEADDR38_27__SHIFT 0x13
+#define MC_FUS_DRAM1_CS1_BASE__CSENABLE_MASK 0x1
+#define MC_FUS_DRAM1_CS1_BASE__CSENABLE__SHIFT 0x0
+#define MC_FUS_DRAM1_CS1_BASE__BASEADDR21_11_MASK 0xffe0
+#define MC_FUS_DRAM1_CS1_BASE__BASEADDR21_11__SHIFT 0x5
+#define MC_FUS_DRAM1_CS1_BASE__BASEADDR38_27_MASK 0x7ff80000
+#define MC_FUS_DRAM1_CS1_BASE__BASEADDR38_27__SHIFT 0x13
+#define MC_FUS_DRAM0_CS2_BASE__CSENABLE_MASK 0x1
+#define MC_FUS_DRAM0_CS2_BASE__CSENABLE__SHIFT 0x0
+#define MC_FUS_DRAM0_CS2_BASE__BASEADDR21_11_MASK 0xffe0
+#define MC_FUS_DRAM0_CS2_BASE__BASEADDR21_11__SHIFT 0x5
+#define MC_FUS_DRAM0_CS2_BASE__BASEADDR38_27_MASK 0x7ff80000
+#define MC_FUS_DRAM0_CS2_BASE__BASEADDR38_27__SHIFT 0x13
+#define MC_FUS_DRAM1_CS2_BASE__CSENABLE_MASK 0x1
+#define MC_FUS_DRAM1_CS2_BASE__CSENABLE__SHIFT 0x0
+#define MC_FUS_DRAM1_CS2_BASE__BASEADDR21_11_MASK 0xffe0
+#define MC_FUS_DRAM1_CS2_BASE__BASEADDR21_11__SHIFT 0x5
+#define MC_FUS_DRAM1_CS2_BASE__BASEADDR38_27_MASK 0x7ff80000
+#define MC_FUS_DRAM1_CS2_BASE__BASEADDR38_27__SHIFT 0x13
+#define MC_FUS_DRAM0_CS3_BASE__CSENABLE_MASK 0x1
+#define MC_FUS_DRAM0_CS3_BASE__CSENABLE__SHIFT 0x0
+#define MC_FUS_DRAM0_CS3_BASE__BASEADDR21_11_MASK 0xffe0
+#define MC_FUS_DRAM0_CS3_BASE__BASEADDR21_11__SHIFT 0x5
+#define MC_FUS_DRAM0_CS3_BASE__BASEADDR38_27_MASK 0x7ff80000
+#define MC_FUS_DRAM0_CS3_BASE__BASEADDR38_27__SHIFT 0x13
+#define MC_FUS_DRAM1_CS3_BASE__CSENABLE_MASK 0x1
+#define MC_FUS_DRAM1_CS3_BASE__CSENABLE__SHIFT 0x0
+#define MC_FUS_DRAM1_CS3_BASE__BASEADDR21_11_MASK 0xffe0
+#define MC_FUS_DRAM1_CS3_BASE__BASEADDR21_11__SHIFT 0x5
+#define MC_FUS_DRAM1_CS3_BASE__BASEADDR38_27_MASK 0x7ff80000
+#define MC_FUS_DRAM1_CS3_BASE__BASEADDR38_27__SHIFT 0x13
+#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM0ADDRMAP_MASK 0xf
+#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM0ADDRMAP__SHIFT 0x0
+#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM1ADDRMAP_MASK 0xf0
+#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM1ADDRMAP__SHIFT 0x4
+#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWIZZLEMODE_MASK 0x100
+#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWIZZLEMODE__SHIFT 0x8
+#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWAP_MASK 0x200
+#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWAP__SHIFT 0x9
+#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM0ADDRMAP_MASK 0xf
+#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM0ADDRMAP__SHIFT 0x0
+#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM1ADDRMAP_MASK 0xf0
+#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM1ADDRMAP__SHIFT 0x4
+#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWIZZLEMODE_MASK 0x100
+#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWIZZLEMODE__SHIFT 0x8
+#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWAP_MASK 0x200
+#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWAP__SHIFT 0x9
+#define MC_FUS_DRAM0_CTL_BASE__DCTSEL_MASK 0x7
+#define MC_FUS_DRAM0_CTL_BASE__DCTSEL__SHIFT 0x0
+#define MC_FUS_DRAM0_CTL_BASE__DCTINTLVEN_MASK 0x78
+#define MC_FUS_DRAM0_CTL_BASE__DCTINTLVEN__SHIFT 0x3
+#define MC_FUS_DRAM0_CTL_BASE__DCTBASEADDR_MASK 0xfffff80
+#define MC_FUS_DRAM0_CTL_BASE__DCTBASEADDR__SHIFT 0x7
+#define MC_FUS_DRAM0_CTL_BASE__DCTOFFSETEN_MASK 0x10000000
+#define MC_FUS_DRAM0_CTL_BASE__DCTOFFSETEN__SHIFT 0x1c
+#define MC_FUS_DRAM1_CTL_BASE__DCTSEL_MASK 0x7
+#define MC_FUS_DRAM1_CTL_BASE__DCTSEL__SHIFT 0x0
+#define MC_FUS_DRAM1_CTL_BASE__DCTINTLVEN_MASK 0x78
+#define MC_FUS_DRAM1_CTL_BASE__DCTINTLVEN__SHIFT 0x3
+#define MC_FUS_DRAM1_CTL_BASE__DCTBASEADDR_MASK 0xfffff80
+#define MC_FUS_DRAM1_CTL_BASE__DCTBASEADDR__SHIFT 0x7
+#define MC_FUS_DRAM1_CTL_BASE__DCTOFFSETEN_MASK 0x10000000
+#define MC_FUS_DRAM1_CTL_BASE__DCTOFFSETEN__SHIFT 0x1c
+#define MC_FUS_DRAM0_CTL_LIMIT__DCTLIMITADDR_MASK 0x1fffff
+#define MC_FUS_DRAM0_CTL_LIMIT__DCTLIMITADDR__SHIFT 0x0
+#define MC_FUS_DRAM0_CTL_LIMIT__DRAMHOLEVALID_MASK 0x200000
+#define MC_FUS_DRAM0_CTL_LIMIT__DRAMHOLEVALID__SHIFT 0x15
+#define MC_FUS_DRAM1_CTL_LIMIT__DCTLIMITADDR_MASK 0x1fffff
+#define MC_FUS_DRAM1_CTL_LIMIT__DCTLIMITADDR__SHIFT 0x0
+#define MC_FUS_DRAM1_CTL_LIMIT__DRAMHOLEVALID_MASK 0x200000
+#define MC_FUS_DRAM1_CTL_LIMIT__DRAMHOLEVALID__SHIFT 0x15
+#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF0_MASK 0xfff
+#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF0__SHIFT 0x0
+#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF1_MASK 0xfff000
+#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF1__SHIFT 0xc
+#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF2_MASK 0xfff
+#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF2__SHIFT 0x0
+#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF3_MASK 0xfff000
+#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF3__SHIFT 0xc
+#define MC_FUS_DRAM_MODE__DCTSELINTLVADDR_MASK 0x7
+#define MC_FUS_DRAM_MODE__DCTSELINTLVADDR__SHIFT 0x0
+#define MC_FUS_DRAM_MODE__GDDR5EN_MASK 0x8
+#define MC_FUS_DRAM_MODE__GDDR5EN__SHIFT 0x3
+#define MC_FUS_DRAM_MODE__DRAMHOLEOFFSET_MASK 0x1ff0
+#define MC_FUS_DRAM_MODE__DRAMHOLEOFFSET__SHIFT 0x4
+#define MC_FUS_DRAM_APER_BASE__BASE_MASK 0xfffff
+#define MC_FUS_DRAM_APER_BASE__BASE__SHIFT 0x0
+#define MC_FUS_DRAM_APER_TOP__TOP_MASK 0xfffff
+#define MC_FUS_DRAM_APER_TOP__TOP__SHIFT 0x0
+#define MC_FUS_DRAM_C6SAVE_APER_BASE__BASE_MASK 0xfffff
+#define MC_FUS_DRAM_C6SAVE_APER_BASE__BASE__SHIFT 0x0
+#define MC_FUS_DRAM_C6SAVE_APER_TOP__TOP_MASK 0xfffff
+#define MC_FUS_DRAM_C6SAVE_APER_TOP__TOP__SHIFT 0x0
+#define MC_FUS_DRAM_APER_DEF__DEF_MASK 0xfffffff
+#define MC_FUS_DRAM_APER_DEF__DEF__SHIFT 0x0
+#define MC_FUS_DRAM_APER_DEF__LOCK_MC_FUS_DRAM_REGS_MASK 0x10000000
+#define MC_FUS_DRAM_APER_DEF__LOCK_MC_FUS_DRAM_REGS__SHIFT 0x1c
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_TOKURG_EN_MASK 0x1
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_TOKURG_EN__SHIFT 0x0
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_TOKURG_EN_MASK 0x2
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_TOKURG_EN__SHIFT 0x1
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_TOKURG_EN_MASK 0x4
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_TOKURG_EN__SHIFT 0x2
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_TOKURG_EN_MASK 0x8
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_TOKURG_EN__SHIFT 0x3
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_PRIURG_EN_MASK 0x10
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_PRIURG_EN__SHIFT 0x4
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_PRIURG_EN_MASK 0x20
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_PRIURG_EN__SHIFT 0x5
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_PRIURG_EN_MASK 0x40
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_PRIURG_EN__SHIFT 0x6
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_PRIURG_EN_MASK 0x80
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_PRIURG_EN__SHIFT 0x7
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_ISOC_EN_MASK 0x100
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_ISOC_EN__SHIFT 0x8
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_ISOC_EN_MASK 0x200
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_ISOC_EN__SHIFT 0x9
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_ISOC_EN_MASK 0x400
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_ISOC_EN__SHIFT 0xa
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__MCIF_RD_ISOC_EN_MASK 0x800
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__MCIF_RD_ISOC_EN__SHIFT 0xb
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__UMC_RD_ISOC_EN_MASK 0x1000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__UMC_RD_ISOC_EN__SHIFT 0xc
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCEU_RD_ISOC_EN_MASK 0x2000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCEU_RD_ISOC_EN__SHIFT 0xd
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_ISOC_EN_MASK 0x4000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_ISOC_EN__SHIFT 0xe
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_EN_MASK 0x8000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_EN__SHIFT 0xf
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_VAL_MASK 0x30000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_VAL__SHIFT 0x10
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_EN_MASK 0x40000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_EN__SHIFT 0x12
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_EN_MASK 0x80000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_EN__SHIFT 0x13
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_EN_MASK 0x100000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_EN__SHIFT 0x14
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_VAL_MASK 0x200000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_VAL__SHIFT 0x15
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_VAL_MASK 0x400000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_VAL__SHIFT 0x16
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_VAL_MASK 0x800000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_VAL__SHIFT 0x17
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__GARLIC_REQ_CREDITS_MASK 0x1f000000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__GARLIC_REQ_CREDITS__SHIFT 0x18
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__MM_REL_LATE_MASK 0x20000000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__MM_REL_LATE__SHIFT 0x1d
+#define MC_FUS_ARB_GARLIC_CNTL__RX_RDRESP_FIFO_PTR_INIT_VALUE_MASK 0xff
+#define MC_FUS_ARB_GARLIC_CNTL__RX_RDRESP_FIFO_PTR_INIT_VALUE__SHIFT 0x0
+#define MC_FUS_ARB_GARLIC_CNTL__RX_WRRESP_FIFO_PTR_INIT_VALUE_MASK 0x7f00
+#define MC_FUS_ARB_GARLIC_CNTL__RX_WRRESP_FIFO_PTR_INIT_VALUE__SHIFT 0x8
+#define MC_FUS_ARB_GARLIC_CNTL__EN_64_BYTE_WRITE_MASK 0x8000
+#define MC_FUS_ARB_GARLIC_CNTL__EN_64_BYTE_WRITE__SHIFT 0xf
+#define MC_FUS_ARB_GARLIC_CNTL__EDC_RESPONSE_ENABLE_MASK 0x10000
+#define MC_FUS_ARB_GARLIC_CNTL__EDC_RESPONSE_ENABLE__SHIFT 0x10
+#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_RDRESP_LIMIT_MASK 0x3fe0000
+#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_RDRESP_LIMIT__SHIFT 0x11
+#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_WRRESP_LIMIT_MASK 0xfc000000
+#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_WRRESP_LIMIT__SHIFT 0x1a
+#define MC_FUS_ARB_GARLIC_WR_PRI__CB_WR_PRI_MASK 0x3
+#define MC_FUS_ARB_GARLIC_WR_PRI__CB_WR_PRI__SHIFT 0x0
+#define MC_FUS_ARB_GARLIC_WR_PRI__DB_WR_PRI_MASK 0xc
+#define MC_FUS_ARB_GARLIC_WR_PRI__DB_WR_PRI__SHIFT 0x2
+#define MC_FUS_ARB_GARLIC_WR_PRI__TC_WR_PRI_MASK 0x30
+#define MC_FUS_ARB_GARLIC_WR_PRI__TC_WR_PRI__SHIFT 0x4
+#define MC_FUS_ARB_GARLIC_WR_PRI__CP_WR_PRI_MASK 0xc0
+#define MC_FUS_ARB_GARLIC_WR_PRI__CP_WR_PRI__SHIFT 0x6
+#define MC_FUS_ARB_GARLIC_WR_PRI__HDP_WR_PRI_MASK 0x300
+#define MC_FUS_ARB_GARLIC_WR_PRI__HDP_WR_PRI__SHIFT 0x8
+#define MC_FUS_ARB_GARLIC_WR_PRI__XDP_WR_PRI_MASK 0xc00
+#define MC_FUS_ARB_GARLIC_WR_PRI__XDP_WR_PRI__SHIFT 0xa
+#define MC_FUS_ARB_GARLIC_WR_PRI__UMC_WR_PRI_MASK 0x3000
+#define MC_FUS_ARB_GARLIC_WR_PRI__UMC_WR_PRI__SHIFT 0xc
+#define MC_FUS_ARB_GARLIC_WR_PRI__UVD_WR_PRI_MASK 0xc000
+#define MC_FUS_ARB_GARLIC_WR_PRI__UVD_WR_PRI__SHIFT 0xe
+#define MC_FUS_ARB_GARLIC_WR_PRI__RLC_WR_PRI_MASK 0x30000
+#define MC_FUS_ARB_GARLIC_WR_PRI__RLC_WR_PRI__SHIFT 0x10
+#define MC_FUS_ARB_GARLIC_WR_PRI__IH_WR_PRI_MASK 0xc0000
+#define MC_FUS_ARB_GARLIC_WR_PRI__IH_WR_PRI__SHIFT 0x12
+#define MC_FUS_ARB_GARLIC_WR_PRI__SDMA_WR_PRI_MASK 0x300000
+#define MC_FUS_ARB_GARLIC_WR_PRI__SDMA_WR_PRI__SHIFT 0x14
+#define MC_FUS_ARB_GARLIC_WR_PRI__SEM_WR_PRI_MASK 0xc00000
+#define MC_FUS_ARB_GARLIC_WR_PRI__SEM_WR_PRI__SHIFT 0x16
+#define MC_FUS_ARB_GARLIC_WR_PRI__SH_WR_PRI_MASK 0x3000000
+#define MC_FUS_ARB_GARLIC_WR_PRI__SH_WR_PRI__SHIFT 0x18
+#define MC_FUS_ARB_GARLIC_WR_PRI__MCIF_WR_PRI_MASK 0xc000000
+#define MC_FUS_ARB_GARLIC_WR_PRI__MCIF_WR_PRI__SHIFT 0x1a
+#define MC_FUS_ARB_GARLIC_WR_PRI__VCE_WR_PRI_MASK 0x30000000
+#define MC_FUS_ARB_GARLIC_WR_PRI__VCE_WR_PRI__SHIFT 0x1c
+#define MC_FUS_ARB_GARLIC_WR_PRI__VCEU_WR_PRI_MASK 0xc0000000
+#define MC_FUS_ARB_GARLIC_WR_PRI__VCEU_WR_PRI__SHIFT 0x1e
+#define MC_FUS_ARB_GARLIC_WR_PRI2__SMU_WR_PRI_MASK 0x3
+#define MC_FUS_ARB_GARLIC_WR_PRI2__SMU_WR_PRI__SHIFT 0x0
+#define MC_FUS_ARB_GARLIC_WR_PRI2__SAM_WR_PRI_MASK 0xc
+#define MC_FUS_ARB_GARLIC_WR_PRI2__SAM_WR_PRI__SHIFT 0x2
+#define MC_FUS_ARB_GARLIC_WR_PRI2__ACP_WR_PRI_MASK 0x30
+#define MC_FUS_ARB_GARLIC_WR_PRI2__ACP_WR_PRI__SHIFT 0x4
+#define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffff
+#define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x0
+#define CHUB_ATC_L1_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
+#define CHUB_ATC_L1_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
+#define CHUB_ATC_L1_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
+#define CHUB_ATC_L1_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
+#define CHUB_ATC_L1_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
+#define CHUB_ATC_L1_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
+#define CHUB_ATC_L1_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
+#define CHUB_ATC_L1_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
+#define CHUB_ATC_L1_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
+#define CHUB_ATC_L1_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
+#define CHUB_ATC_L1_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
+#define CHUB_ATC_L1_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
+#define CHUB_ATC_L1_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
+#define CHUB_ATC_L1_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
+#define CHUB_ATC_L1_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
+#define CHUB_ATC_L1_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
+#define CHUB_ATC_L1_DEBUG_TLB__DISABLE_CACHING_UNTRANSLATED_RETURNS_MASK 0x80000000
+#define CHUB_ATC_L1_DEBUG_TLB__DISABLE_CACHING_UNTRANSLATED_RETURNS__SHIFT 0x1f
+#define CHUB_ATC_L1_STATUS__BUSY_MASK 0x1
+#define CHUB_ATC_L1_STATUS__BUSY__SHIFT 0x0
+#define CHUB_ATC_L1_STATUS__DEADLOCK_DETECTION_MASK 0x2
+#define CHUB_ATC_L1_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
+#define CHUB_ATC_L1_STATUS__BAD_NEED_ATS_MASK 0x100
+#define CHUB_ATC_L1_STATUS__BAD_NEED_ATS__SHIFT 0x8
+
+#endif /* GMC_7_0_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_d.h
new file mode 100644
index 000000000000..9da033dc1a34
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_d.h
@@ -0,0 +1,1464 @@
+/*
+ * GMC_7_1 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GMC_7_1_D_H
+#define GMC_7_1_D_H
+
+#define mmMC_CONFIG 0x800
+#define mmMC_ARB_AGE_CNTL 0x9bf
+#define mmMC_ARB_RET_CREDITS2 0x9c0
+#define mmMC_ARB_FED_CNTL 0x9c1
+#define mmMC_ARB_GECC2_STATUS 0x9c2
+#define mmMC_ARB_GECC2_MISC 0x9c3
+#define mmMC_ARB_GECC2_DEBUG 0x9c4
+#define mmMC_ARB_GECC2_DEBUG2 0x9c5
+#define mmMC_ARB_PERF_CID 0x9c6
+#define mmMC_ARB_GECC2 0x9c9
+#define mmMC_ARB_GECC2_CLI 0x9ca
+#define mmMC_ARB_ADDR_SWIZ0 0x9cb
+#define mmMC_ARB_ADDR_SWIZ1 0x9cc
+#define mmMC_ARB_MISC3 0x9cd
+#define mmMC_ARB_WCDR_2 0x9ce
+#define mmMC_ARB_RTT_DATA 0x9cf
+#define mmMC_ARB_RTT_CNTL0 0x9d0
+#define mmMC_ARB_RTT_CNTL1 0x9d1
+#define mmMC_ARB_RTT_CNTL2 0x9d2
+#define mmMC_ARB_RTT_DEBUG 0x9d3
+#define mmMC_ARB_CAC_CNTL 0x9d4
+#define mmMC_ARB_MISC2 0x9d5
+#define mmMC_ARB_MISC 0x9d6
+#define mmMC_ARB_BANKMAP 0x9d7
+#define mmMC_ARB_RAMCFG 0x9d8
+#define mmMC_ARB_POP 0x9d9
+#define mmMC_ARB_MINCLKS 0x9da
+#define mmMC_ARB_SQM_CNTL 0x9db
+#define mmMC_ARB_ADDR_HASH 0x9dc
+#define mmMC_ARB_DRAM_TIMING 0x9dd
+#define mmMC_ARB_DRAM_TIMING2 0x9de
+#define mmMC_ARB_WTM_CNTL_RD 0x9df
+#define mmMC_ARB_WTM_CNTL_WR 0x9e0
+#define mmMC_ARB_WTM_GRPWT_RD 0x9e1
+#define mmMC_ARB_WTM_GRPWT_WR 0x9e2
+#define mmMC_ARB_TM_CNTL_RD 0x9e3
+#define mmMC_ARB_TM_CNTL_WR 0x9e4
+#define mmMC_ARB_LAZY0_RD 0x9e5
+#define mmMC_ARB_LAZY0_WR 0x9e6
+#define mmMC_ARB_LAZY1_RD 0x9e7
+#define mmMC_ARB_LAZY1_WR 0x9e8
+#define mmMC_ARB_AGE_RD 0x9e9
+#define mmMC_ARB_AGE_WR 0x9ea
+#define mmMC_ARB_RFSH_CNTL 0x9eb
+#define mmMC_ARB_RFSH_RATE 0x9ec
+#define mmMC_ARB_PM_CNTL 0x9ed
+#define mmMC_ARB_GDEC_RD_CNTL 0x9ee
+#define mmMC_ARB_GDEC_WR_CNTL 0x9ef
+#define mmMC_ARB_LM_RD 0x9f0
+#define mmMC_ARB_LM_WR 0x9f1
+#define mmMC_ARB_REMREQ 0x9f2
+#define mmMC_ARB_REPLAY 0x9f3
+#define mmMC_ARB_RET_CREDITS_RD 0x9f4
+#define mmMC_ARB_RET_CREDITS_WR 0x9f5
+#define mmMC_ARB_MAX_LAT_CID 0x9f6
+#define mmMC_ARB_MAX_LAT_RSLT0 0x9f7
+#define mmMC_ARB_MAX_LAT_RSLT1 0x9f8
+#define mmMC_ARB_SSM 0x9f9
+#define mmMC_ARB_CG 0x9fa
+#define mmMC_ARB_WCDR 0x9fb
+#define mmMC_ARB_DRAM_TIMING_1 0x9fc
+#define mmMC_ARB_BUSY_STATUS 0x9fd
+#define mmMC_ARB_DRAM_TIMING2_1 0x9ff
+#define mmMC_ARB_BURST_TIME 0xa02
+#define mmMC_CITF_XTRA_ENABLE 0x96d
+#define mmCC_MC_MAX_CHANNEL 0x96e
+#define mmMC_CG_CONFIG 0x96f
+#define mmMC_CITF_CNTL 0x970
+#define mmMC_CITF_CREDITS_VM 0x971
+#define mmMC_CITF_CREDITS_ARB_RD 0x972
+#define mmMC_CITF_CREDITS_ARB_WR 0x973
+#define mmMC_CITF_DAGB_CNTL 0x974
+#define mmMC_CITF_INT_CREDITS 0x975
+#define mmMC_CITF_RET_MODE 0x976
+#define mmMC_CITF_DAGB_DLY 0x977
+#define mmMC_RD_GRP_EXT 0x978
+#define mmMC_WR_GRP_EXT 0x979
+#define mmMC_CITF_REMREQ 0x97a
+#define mmMC_WR_TC0 0x97b
+#define mmMC_WR_TC1 0x97c
+#define mmMC_CITF_INT_CREDITS_WR 0x97d
+#define mmMC_CITF_WTM_RD_CNTL 0x97f
+#define mmMC_CITF_WTM_WR_CNTL 0x980
+#define mmMC_RD_CB 0x981
+#define mmMC_RD_DB 0x982
+#define mmMC_RD_TC0 0x983
+#define mmMC_RD_TC1 0x984
+#define mmMC_RD_HUB 0x985
+#define mmMC_WR_CB 0x986
+#define mmMC_WR_DB 0x987
+#define mmMC_WR_HUB 0x988
+#define mmMC_CITF_CREDITS_XBAR 0x989
+#define mmMC_RD_GRP_LCL 0x98a
+#define mmMC_WR_GRP_LCL 0x98b
+#define mmMC_CITF_PERF_MON_CNTL2 0x98e
+#define mmMC_CITF_PERF_MON_RSLT2 0x991
+#define mmMC_CITF_MISC_RD_CG 0x992
+#define mmMC_CITF_MISC_WR_CG 0x993
+#define mmMC_CITF_MISC_VM_CG 0x994
+#define mmMC_HUB_MISC_POWER 0x82d
+#define mmMC_HUB_MISC_HUB_CG 0x82e
+#define mmMC_HUB_MISC_VM_CG 0x82f
+#define mmMC_HUB_MISC_SIP_CG 0x830
+#define mmMC_HUB_MISC_STATUS 0x832
+#define mmMC_HUB_MISC_OVERRIDE 0x833
+#define mmMC_HUB_MISC_FRAMING 0x834
+#define mmMC_HUB_WDP_CNTL 0x835
+#define mmMC_HUB_WDP_ERR 0x836
+#define mmMC_HUB_WDP_BP 0x837
+#define mmMC_HUB_WDP_STATUS 0x838
+#define mmMC_HUB_RDREQ_STATUS 0x839
+#define mmMC_HUB_WRRET_STATUS 0x83a
+#define mmMC_HUB_RDREQ_CNTL 0x83b
+#define mmMC_HUB_WRRET_CNTL 0x83c
+#define mmMC_HUB_RDREQ_WTM_CNTL 0x83d
+#define mmMC_HUB_WDP_WTM_CNTL 0x83e
+#define mmMC_HUB_WDP_CREDITS 0x83f
+#define mmMC_HUB_WDP_CREDITS2 0x840
+#define mmMC_HUB_WDP_GBL0 0x841
+#define mmMC_HUB_WDP_GBL1 0x842
+#define mmMC_HUB_RDREQ_CREDITS 0x844
+#define mmMC_HUB_RDREQ_CREDITS2 0x845
+#define mmMC_HUB_SHARED_DAGB_DLY 0x846
+#define mmMC_HUB_MISC_IDLE_STATUS 0x847
+#define mmMC_HUB_RDREQ_DMIF_LIMIT 0x848
+#define mmMC_HUB_RDREQ_ACPG_LIMIT 0x849
+#define mmMC_HUB_WDP_BYPASS_GBL0 0x84a
+#define mmMC_HUB_WDP_BYPASS_GBL1 0x84b
+#define mmMC_HUB_RDREQ_BYPASS_GBL0 0x84c
+#define mmMC_HUB_WDP_SH2 0x84d
+#define mmMC_HUB_WDP_SH3 0x84e
+#define mmMC_HUB_RDREQ_IA0 0x84f
+#define mmMC_HUB_RDREQ_IA1 0x850
+#define mmMC_HUB_RDREQ_MCDW 0x851
+#define mmMC_HUB_RDREQ_MCDX 0x852
+#define mmMC_HUB_RDREQ_MCDY 0x853
+#define mmMC_HUB_RDREQ_MCDZ 0x854
+#define mmMC_HUB_RDREQ_SIP 0x855
+#define mmMC_HUB_RDREQ_GBL0 0x856
+#define mmMC_HUB_RDREQ_GBL1 0x857
+#define mmMC_HUB_RDREQ_SMU 0x858
+#define mmMC_HUB_RDREQ_CPG 0x859
+#define mmMC_HUB_RDREQ_SDMA0 0x85a
+#define mmMC_HUB_RDREQ_HDP 0x85b
+#define mmMC_HUB_RDREQ_SDMA1 0x85c
+#define mmMC_HUB_RDREQ_RLC 0x85d
+#define mmMC_HUB_RDREQ_SEM 0x85e
+#define mmMC_HUB_RDREQ_VCE 0x85f
+#define mmMC_HUB_RDREQ_UMC 0x860
+#define mmMC_HUB_RDREQ_UVD 0x861
+#define mmMC_HUB_RDREQ_IA 0x862
+#define mmMC_HUB_RDREQ_DMIF 0x863
+#define mmMC_HUB_RDREQ_MCIF 0x864
+#define mmMC_HUB_RDREQ_VMC 0x865
+#define mmMC_HUB_RDREQ_VCEU 0x866
+#define mmMC_HUB_WDP_MCDW 0x867
+#define mmMC_HUB_WDP_MCDX 0x868
+#define mmMC_HUB_WDP_MCDY 0x869
+#define mmMC_HUB_WDP_MCDZ 0x86a
+#define mmMC_HUB_WDP_SIP 0x86b
+#define mmMC_HUB_WDP_CPG 0x86c
+#define mmMC_HUB_WDP_SDMA1 0x86d
+#define mmMC_HUB_WDP_SH0 0x86e
+#define mmMC_HUB_WDP_MCIF 0x86f
+#define mmMC_HUB_WDP_VCE 0x870
+#define mmMC_HUB_WDP_XDP 0x871
+#define mmMC_HUB_WDP_IH 0x872
+#define mmMC_HUB_WDP_RLC 0x873
+#define mmMC_HUB_WDP_SEM 0x874
+#define mmMC_HUB_WDP_SMU 0x875
+#define mmMC_HUB_WDP_SH1 0x876
+#define mmMC_HUB_WDP_UMC 0x877
+#define mmMC_HUB_WDP_UVD 0x878
+#define mmMC_HUB_WDP_HDP 0x879
+#define mmMC_HUB_WDP_SDMA0 0x87a
+#define mmMC_HUB_WRRET_MCDW 0x87b
+#define mmMC_HUB_WRRET_MCDX 0x87c
+#define mmMC_HUB_WRRET_MCDY 0x87d
+#define mmMC_HUB_WRRET_MCDZ 0x87e
+#define mmMC_HUB_WDP_VCEU 0x87f
+#define mmMC_HUB_WDP_XDMAM 0x880
+#define mmMC_HUB_WDP_XDMA 0x881
+#define mmMC_HUB_RDREQ_XDMAM 0x882
+#define mmMC_HUB_RDREQ_ACPG 0x883
+#define mmMC_HUB_RDREQ_ACPO 0x884
+#define mmMC_HUB_RDREQ_SAM 0x885
+#define mmMC_HUB_WDP_ACPG 0x886
+#define mmMC_HUB_WDP_ACPO 0x887
+#define mmMC_HUB_WDP_SAM 0x888
+#define mmMC_HUB_RDREQ_CPC 0x889
+#define mmMC_HUB_RDREQ_CPF 0x88a
+#define mmMC_HUB_WDP_CPC 0x88b
+#define mmMC_HUB_WDP_CPF 0x88c
+#define mmMC_HUB_RDREQ_ISP_SPM 0xde0
+#define mmMC_HUB_RDREQ_ISP_MPM 0xde1
+#define mmMC_HUB_RDREQ_ISP_CCPU 0xde2
+#define mmMC_HUB_WDP_ISP_SPM 0xde3
+#define mmMC_HUB_WDP_ISP_MPS 0xde4
+#define mmMC_HUB_WDP_ISP_MPM 0xde5
+#define mmMC_HUB_WDP_ISP_CCPU 0xde6
+#define mmMC_HUB_RDREQ_MCDS 0xde7
+#define mmMC_HUB_RDREQ_MCDT 0xde8
+#define mmMC_HUB_RDREQ_MCDU 0xde9
+#define mmMC_HUB_RDREQ_MCDV 0xdea
+#define mmMC_HUB_WDP_MCDS 0xdeb
+#define mmMC_HUB_WDP_MCDT 0xdec
+#define mmMC_HUB_WDP_MCDU 0xded
+#define mmMC_HUB_WDP_MCDV 0xdee
+#define mmMC_HUB_WRRET_MCDS 0xdef
+#define mmMC_HUB_WRRET_MCDT 0xdf0
+#define mmMC_HUB_WRRET_MCDU 0xdf1
+#define mmMC_HUB_WRRET_MCDV 0xdf2
+#define mmMC_HUB_WDP_CREDITS_MCDW 0xdf3
+#define mmMC_HUB_WDP_CREDITS_MCDX 0xdf4
+#define mmMC_HUB_WDP_CREDITS_MCDY 0xdf5
+#define mmMC_HUB_WDP_CREDITS_MCDZ 0xdf6
+#define mmMC_HUB_WDP_CREDITS_MCDS 0xdf7
+#define mmMC_HUB_WDP_CREDITS_MCDT 0xdf8
+#define mmMC_HUB_WDP_CREDITS_MCDU 0xdf9
+#define mmMC_HUB_WDP_CREDITS_MCDV 0xdfa
+#define mmMC_HUB_WDP_BP2 0xdfb
+#define mmMC_RPB_CONF 0x94d
+#define mmMC_RPB_IF_CONF 0x94e
+#define mmMC_RPB_DBG1 0x94f
+#define mmMC_RPB_EFF_CNTL 0x950
+#define mmMC_RPB_ARB_CNTL 0x951
+#define mmMC_RPB_BIF_CNTL 0x952
+#define mmMC_RPB_WR_SWITCH_CNTL 0x953
+#define mmMC_RPB_WR_COMBINE_CNTL 0x954
+#define mmMC_RPB_RD_SWITCH_CNTL 0x955
+#define mmMC_RPB_CID_QUEUE_WR 0x956
+#define mmMC_RPB_CID_QUEUE_RD 0x957
+#define mmMC_RPB_PERF_COUNTER_CNTL 0x958
+#define mmMC_RPB_PERF_COUNTER_STATUS 0x959
+#define mmMC_RPB_CID_QUEUE_EX 0x95a
+#define mmMC_RPB_CID_QUEUE_EX_DATA 0x95b
+#define mmMC_RPB_TCI_CNTL 0x95c
+#define mmMC_SHARED_CHMAP 0x801
+#define mmMC_SHARED_CHREMAP 0x802
+#define mmMC_RD_GRP_GFX 0x803
+#define mmMC_WR_GRP_GFX 0x804
+#define mmMC_RD_GRP_SYS 0x805
+#define mmMC_WR_GRP_SYS 0x806
+#define mmMC_RD_GRP_OTH 0x807
+#define mmMC_WR_GRP_OTH 0x808
+#define mmMC_VM_FB_LOCATION 0x809
+#define mmMC_VM_AGP_TOP 0x80a
+#define mmMC_VM_AGP_BOT 0x80b
+#define mmMC_VM_AGP_BASE 0x80c
+#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80d
+#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80e
+#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80f
+#define mmMC_VM_DC_WRITE_CNTL 0x810
+#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0x811
+#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0x812
+#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0x813
+#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0x814
+#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0x815
+#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0x816
+#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0x817
+#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0x818
+#define mmMC_VM_MX_L1_TLB_CNTL 0x819
+#define mmMC_VM_FB_OFFSET 0x81a
+#define mmMC_VM_STEERING 0x81b
+#define mmMC_SHARED_CHREMAP2 0x81c
+#define mmMC_CONFIG_MCD 0x828
+#define mmMC_CG_CONFIG_MCD 0x829
+#define mmMC_MEM_POWER_LS 0x82a
+#define mmMC_SHARED_BLACKOUT_CNTL 0x82b
+#define mmMC_VM_MB_L1_TLB0_DEBUG 0x891
+#define mmMC_VM_MB_L1_TLB2_DEBUG 0x893
+#define mmMC_VM_MB_L1_TLB0_STATUS 0x895
+#define mmMC_VM_MB_L1_TLB1_STATUS 0x896
+#define mmMC_VM_MB_L1_TLB2_STATUS 0x897
+#define mmMC_VM_MB_L2ARBITER_L2_CREDITS 0x8a1
+#define mmMC_VM_MB_L1_TLB3_DEBUG 0x8a5
+#define mmMC_VM_MB_L1_TLB3_STATUS 0x8a6
+#define mmMC_VM_MD_L1_TLB0_DEBUG 0x998
+#define mmMC_VM_MD_L1_TLB1_DEBUG 0x999
+#define mmMC_VM_MD_L1_TLB2_DEBUG 0x99a
+#define mmMC_VM_MD_L1_TLB0_STATUS 0x99b
+#define mmMC_VM_MD_L1_TLB1_STATUS 0x99c
+#define mmMC_VM_MD_L1_TLB2_STATUS 0x99d
+#define mmMC_VM_MD_L2ARBITER_L2_CREDITS 0x9a4
+#define mmMC_VM_MD_L1_TLB3_DEBUG 0x9a7
+#define mmMC_VM_MD_L1_TLB3_STATUS 0x9a8
+#define mmMC_XPB_RTR_SRC_APRTR0 0x8cd
+#define mmMC_XPB_RTR_SRC_APRTR1 0x8ce
+#define mmMC_XPB_RTR_SRC_APRTR2 0x8cf
+#define mmMC_XPB_RTR_SRC_APRTR3 0x8d0
+#define mmMC_XPB_RTR_SRC_APRTR4 0x8d1
+#define mmMC_XPB_RTR_SRC_APRTR5 0x8d2
+#define mmMC_XPB_RTR_SRC_APRTR6 0x8d3
+#define mmMC_XPB_RTR_SRC_APRTR7 0x8d4
+#define mmMC_XPB_RTR_SRC_APRTR8 0x8d5
+#define mmMC_XPB_RTR_SRC_APRTR9 0x8d6
+#define mmMC_XPB_XDMA_RTR_SRC_APRTR0 0x8d7
+#define mmMC_XPB_XDMA_RTR_SRC_APRTR1 0x8d8
+#define mmMC_XPB_XDMA_RTR_SRC_APRTR2 0x8d9
+#define mmMC_XPB_XDMA_RTR_SRC_APRTR3 0x8da
+#define mmMC_XPB_RTR_DEST_MAP0 0x8db
+#define mmMC_XPB_RTR_DEST_MAP1 0x8dc
+#define mmMC_XPB_RTR_DEST_MAP2 0x8dd
+#define mmMC_XPB_RTR_DEST_MAP3 0x8de
+#define mmMC_XPB_RTR_DEST_MAP4 0x8df
+#define mmMC_XPB_RTR_DEST_MAP5 0x8e0
+#define mmMC_XPB_RTR_DEST_MAP6 0x8e1
+#define mmMC_XPB_RTR_DEST_MAP7 0x8e2
+#define mmMC_XPB_RTR_DEST_MAP8 0x8e3
+#define mmMC_XPB_RTR_DEST_MAP9 0x8e4
+#define mmMC_XPB_XDMA_RTR_DEST_MAP0 0x8e5
+#define mmMC_XPB_XDMA_RTR_DEST_MAP1 0x8e6
+#define mmMC_XPB_XDMA_RTR_DEST_MAP2 0x8e7
+#define mmMC_XPB_XDMA_RTR_DEST_MAP3 0x8e8
+#define mmMC_XPB_CLG_CFG0 0x8e9
+#define mmMC_XPB_CLG_CFG1 0x8ea
+#define mmMC_XPB_CLG_CFG2 0x8eb
+#define mmMC_XPB_CLG_CFG3 0x8ec
+#define mmMC_XPB_CLG_CFG4 0x8ed
+#define mmMC_XPB_CLG_CFG5 0x8ee
+#define mmMC_XPB_CLG_CFG6 0x8ef
+#define mmMC_XPB_CLG_CFG7 0x8f0
+#define mmMC_XPB_CLG_CFG8 0x8f1
+#define mmMC_XPB_CLG_CFG9 0x8f2
+#define mmMC_XPB_CLG_CFG10 0x8f3
+#define mmMC_XPB_CLG_CFG11 0x8f4
+#define mmMC_XPB_CLG_CFG12 0x8f5
+#define mmMC_XPB_CLG_CFG13 0x8f6
+#define mmMC_XPB_CLG_CFG14 0x8f7
+#define mmMC_XPB_CLG_CFG15 0x8f8
+#define mmMC_XPB_CLG_CFG16 0x8f9
+#define mmMC_XPB_CLG_CFG17 0x8fa
+#define mmMC_XPB_CLG_CFG18 0x8fb
+#define mmMC_XPB_CLG_CFG19 0x8fc
+#define mmMC_XPB_CLG_EXTRA 0x8fd
+#define mmMC_XPB_LB_ADDR 0x8fe
+#define mmMC_XPB_UNC_THRESH_HST 0x8ff
+#define mmMC_XPB_UNC_THRESH_SID 0x900
+#define mmMC_XPB_WCB_STS 0x901
+#define mmMC_XPB_WCB_CFG 0x902
+#define mmMC_XPB_P2P_BAR_CFG 0x903
+#define mmMC_XPB_P2P_BAR0 0x904
+#define mmMC_XPB_P2P_BAR1 0x905
+#define mmMC_XPB_P2P_BAR2 0x906
+#define mmMC_XPB_P2P_BAR3 0x907
+#define mmMC_XPB_P2P_BAR4 0x908
+#define mmMC_XPB_P2P_BAR5 0x909
+#define mmMC_XPB_P2P_BAR6 0x90a
+#define mmMC_XPB_P2P_BAR7 0x90b
+#define mmMC_XPB_P2P_BAR_SETUP 0x90c
+#define mmMC_XPB_P2P_BAR_DEBUG 0x90d
+#define mmMC_XPB_P2P_BAR_DELTA_ABOVE 0x90e
+#define mmMC_XPB_P2P_BAR_DELTA_BELOW 0x90f
+#define mmMC_XPB_PEER_SYS_BAR0 0x910
+#define mmMC_XPB_PEER_SYS_BAR1 0x911
+#define mmMC_XPB_PEER_SYS_BAR2 0x912
+#define mmMC_XPB_PEER_SYS_BAR3 0x913
+#define mmMC_XPB_PEER_SYS_BAR4 0x914
+#define mmMC_XPB_PEER_SYS_BAR5 0x915
+#define mmMC_XPB_PEER_SYS_BAR6 0x916
+#define mmMC_XPB_PEER_SYS_BAR7 0x917
+#define mmMC_XPB_PEER_SYS_BAR8 0x918
+#define mmMC_XPB_PEER_SYS_BAR9 0x919
+#define mmMC_XPB_XDMA_PEER_SYS_BAR0 0x91a
+#define mmMC_XPB_XDMA_PEER_SYS_BAR1 0x91b
+#define mmMC_XPB_XDMA_PEER_SYS_BAR2 0x91c
+#define mmMC_XPB_XDMA_PEER_SYS_BAR3 0x91d
+#define mmMC_XPB_CLK_GAT 0x91e
+#define mmMC_XPB_INTF_CFG 0x91f
+#define mmMC_XPB_INTF_STS 0x920
+#define mmMC_XPB_PIPE_STS 0x921
+#define mmMC_XPB_SUB_CTRL 0x922
+#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0x923
+#define mmMC_XPB_PERF_KNOBS 0x924
+#define mmMC_XPB_STICKY 0x925
+#define mmMC_XPB_STICKY_W1C 0x926
+#define mmMC_XPB_MISC_CFG 0x927
+#define mmMC_XPB_CLG_CFG20 0x928
+#define mmMC_XPB_CLG_CFG21 0x929
+#define mmMC_XPB_CLG_CFG22 0x92a
+#define mmMC_XPB_CLG_CFG23 0x92b
+#define mmMC_XPB_CLG_CFG24 0x92c
+#define mmMC_XPB_CLG_CFG25 0x92d
+#define mmMC_XPB_CLG_CFG26 0x92e
+#define mmMC_XPB_CLG_CFG27 0x92f
+#define mmMC_XPB_CLG_CFG28 0x930
+#define mmMC_XPB_CLG_CFG29 0x931
+#define mmMC_XPB_CLG_CFG30 0x932
+#define mmMC_XPB_CLG_CFG31 0x933
+#define mmMC_XPB_INTF_CFG2 0x934
+#define mmMC_XPB_CLG_EXTRA_RD 0x935
+#define mmMC_XPB_CLG_CFG32 0x936
+#define mmMC_XPB_CLG_CFG33 0x937
+#define mmMC_XPB_CLG_CFG34 0x938
+#define mmMC_XPB_CLG_CFG35 0x939
+#define mmMC_XPB_CLG_CFG36 0x93a
+#define mmMC_XBAR_ADDR_DEC 0xc80
+#define mmMC_XBAR_REMOTE 0xc81
+#define mmMC_XBAR_WRREQ_CREDIT 0xc82
+#define mmMC_XBAR_RDREQ_CREDIT 0xc83
+#define mmMC_XBAR_RDREQ_PRI_CREDIT 0xc84
+#define mmMC_XBAR_WRRET_CREDIT1 0xc85
+#define mmMC_XBAR_WRRET_CREDIT2 0xc86
+#define mmMC_XBAR_RDRET_CREDIT1 0xc87
+#define mmMC_XBAR_RDRET_CREDIT2 0xc88
+#define mmMC_XBAR_RDRET_PRI_CREDIT1 0xc89
+#define mmMC_XBAR_RDRET_PRI_CREDIT2 0xc8a
+#define mmMC_XBAR_CHTRIREMAP 0xc8b
+#define mmMC_XBAR_TWOCHAN 0xc8c
+#define mmMC_XBAR_ARB 0xc8d
+#define mmMC_XBAR_ARB_MAX_BURST 0xc8e
+#define mmMC_XBAR_PERF_MON_CNTL0 0xc8f
+#define mmMC_XBAR_PERF_MON_CNTL1 0xc90
+#define mmMC_XBAR_PERF_MON_CNTL2 0xc91
+#define mmMC_XBAR_PERF_MON_RSLT0 0xc92
+#define mmMC_XBAR_PERF_MON_RSLT1 0xc93
+#define mmMC_XBAR_PERF_MON_RSLT2 0xc94
+#define mmMC_XBAR_PERF_MON_RSLT3 0xc95
+#define mmMC_XBAR_PERF_MON_MAX_THSH 0xc96
+#define mmMC_XBAR_SPARE0 0xc97
+#define mmMC_XBAR_SPARE1 0xc98
+#define mmMC_CITF_PERFCOUNTER_LO 0x7a0
+#define mmMC_HUB_PERFCOUNTER_LO 0x7a1
+#define mmMC_RPB_PERFCOUNTER_LO 0x7a2
+#define mmMC_MCBVM_PERFCOUNTER_LO 0x7a3
+#define mmMC_MCDVM_PERFCOUNTER_LO 0x7a4
+#define mmMC_VM_L2_PERFCOUNTER_LO 0x7a5
+#define mmMC_ARB_PERFCOUNTER_LO 0x7a6
+#define mmATC_PERFCOUNTER_LO 0x7a7
+#define mmMC_CITF_PERFCOUNTER_HI 0x7a8
+#define mmMC_HUB_PERFCOUNTER_HI 0x7a9
+#define mmMC_MCBVM_PERFCOUNTER_HI 0x7aa
+#define mmMC_MCDVM_PERFCOUNTER_HI 0x7ab
+#define mmMC_RPB_PERFCOUNTER_HI 0x7ac
+#define mmMC_VM_L2_PERFCOUNTER_HI 0x7ad
+#define mmMC_ARB_PERFCOUNTER_HI 0x7ae
+#define mmATC_PERFCOUNTER_HI 0x7af
+#define mmMC_CITF_PERFCOUNTER0_CFG 0x7b0
+#define mmMC_CITF_PERFCOUNTER1_CFG 0x7b1
+#define mmMC_CITF_PERFCOUNTER2_CFG 0x7b2
+#define mmMC_CITF_PERFCOUNTER3_CFG 0x7b3
+#define mmMC_HUB_PERFCOUNTER0_CFG 0x7b4
+#define mmMC_HUB_PERFCOUNTER1_CFG 0x7b5
+#define mmMC_HUB_PERFCOUNTER2_CFG 0x7b6
+#define mmMC_HUB_PERFCOUNTER3_CFG 0x7b7
+#define mmMC_RPB_PERFCOUNTER0_CFG 0x7b8
+#define mmMC_RPB_PERFCOUNTER1_CFG 0x7b9
+#define mmMC_RPB_PERFCOUNTER2_CFG 0x7ba
+#define mmMC_RPB_PERFCOUNTER3_CFG 0x7bb
+#define mmMC_ARB_PERFCOUNTER0_CFG 0x7bc
+#define mmMC_ARB_PERFCOUNTER1_CFG 0x7bd
+#define mmMC_ARB_PERFCOUNTER2_CFG 0x7be
+#define mmMC_ARB_PERFCOUNTER3_CFG 0x7bf
+#define mmMC_MCBVM_PERFCOUNTER0_CFG 0x7c0
+#define mmMC_MCBVM_PERFCOUNTER1_CFG 0x7c1
+#define mmMC_MCBVM_PERFCOUNTER2_CFG 0x7c2
+#define mmMC_MCBVM_PERFCOUNTER3_CFG 0x7c3
+#define mmMC_MCDVM_PERFCOUNTER0_CFG 0x7c4
+#define mmMC_MCDVM_PERFCOUNTER1_CFG 0x7c5
+#define mmMC_MCDVM_PERFCOUNTER2_CFG 0x7c6
+#define mmMC_MCDVM_PERFCOUNTER3_CFG 0x7c7
+#define mmATC_PERFCOUNTER0_CFG 0x7c8
+#define mmATC_PERFCOUNTER1_CFG 0x7c9
+#define mmATC_PERFCOUNTER2_CFG 0x7ca
+#define mmATC_PERFCOUNTER3_CFG 0x7cb
+#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x7cc
+#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x7cd
+#define mmMC_CITF_PERFCOUNTER_RSLT_CNTL 0x7ce
+#define mmMC_HUB_PERFCOUNTER_RSLT_CNTL 0x7cf
+#define mmMC_RPB_PERFCOUNTER_RSLT_CNTL 0x7d0
+#define mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL 0x7d1
+#define mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL 0x7d2
+#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x7d3
+#define mmMC_ARB_PERFCOUNTER_RSLT_CNTL 0x7d4
+#define mmATC_PERFCOUNTER_RSLT_CNTL 0x7d5
+#define mmCHUB_ATC_PERFCOUNTER_LO 0x7d6
+#define mmCHUB_ATC_PERFCOUNTER_HI 0x7d7
+#define mmCHUB_ATC_PERFCOUNTER0_CFG 0x7d8
+#define mmCHUB_ATC_PERFCOUNTER1_CFG 0x7d9
+#define mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL 0x7da
+#define mmMC_ARB_PERF_MON_CNTL0_ECC 0x7db
+#define mmATC_VM_APERTURE0_LOW_ADDR 0xcc0
+#define mmATC_VM_APERTURE1_LOW_ADDR 0xcc1
+#define mmATC_VM_APERTURE0_HIGH_ADDR 0xcc2
+#define mmATC_VM_APERTURE1_HIGH_ADDR 0xcc3
+#define mmATC_VM_APERTURE0_CNTL 0xcc4
+#define mmATC_VM_APERTURE1_CNTL 0xcc5
+#define mmATC_VM_APERTURE0_CNTL2 0xcc6
+#define mmATC_VM_APERTURE1_CNTL2 0xcc7
+#define mmATC_ATS_CNTL 0xcc9
+#define mmATC_ATS_DEBUG 0xcca
+#define mmATC_ATS_FAULT_DEBUG 0xccb
+#define mmATC_ATS_STATUS 0xccc
+#define mmATC_ATS_FAULT_CNTL 0xccd
+#define mmATC_ATS_FAULT_STATUS_INFO 0xcce
+#define mmATC_ATS_FAULT_STATUS_ADDR 0xccf
+#define mmATC_ATS_DEFAULT_PAGE_LOW 0xcd0
+#define mmATC_ATS_DEFAULT_PAGE_CNTL 0xcd1
+#define mmATC_MISC_CG 0xcd4
+#define mmATC_L2_CNTL 0xcd5
+#define mmATC_L2_CNTL2 0xcd6
+#define mmATC_L2_DEBUG 0xcd7
+#define mmATC_L2_DEBUG2 0xcd8
+#define mmATC_L1_CNTL 0xcdc
+#define mmATC_L1_ADDRESS_OFFSET 0xcdd
+#define mmATC_L1RD_DEBUG_TLB 0xcde
+#define mmATC_L1WR_DEBUG_TLB 0xcdf
+#define mmATC_L1RD_STATUS 0xce0
+#define mmATC_L1WR_STATUS 0xce1
+#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0xce6
+#define mmATC_VMID0_PASID_MAPPING 0xce7
+#define mmATC_VMID1_PASID_MAPPING 0xce8
+#define mmATC_VMID2_PASID_MAPPING 0xce9
+#define mmATC_VMID3_PASID_MAPPING 0xcea
+#define mmATC_VMID4_PASID_MAPPING 0xceb
+#define mmATC_VMID5_PASID_MAPPING 0xcec
+#define mmATC_VMID6_PASID_MAPPING 0xced
+#define mmATC_VMID7_PASID_MAPPING 0xcee
+#define mmATC_VMID8_PASID_MAPPING 0xcef
+#define mmATC_VMID9_PASID_MAPPING 0xcf0
+#define mmATC_VMID10_PASID_MAPPING 0xcf1
+#define mmATC_VMID11_PASID_MAPPING 0xcf2
+#define mmATC_VMID12_PASID_MAPPING 0xcf3
+#define mmATC_VMID13_PASID_MAPPING 0xcf4
+#define mmATC_VMID14_PASID_MAPPING 0xcf5
+#define mmATC_VMID15_PASID_MAPPING 0xcf6
+#define mmGMCON_RENG_RAM_INDEX 0xd40
+#define mmGMCON_RENG_RAM_DATA 0xd41
+#define mmGMCON_RENG_EXECUTE 0xd42
+#define mmGMCON_MISC 0xd43
+#define mmGMCON_MISC2 0xd44
+#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 0xd45
+#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 0xd46
+#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 0xd47
+#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 0xd48
+#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 0xd49
+#define mmGMCON_PERF_MON_CNTL0 0xd4a
+#define mmGMCON_PERF_MON_CNTL1 0xd4b
+#define mmGMCON_PERF_MON_RSLT0 0xd4c
+#define mmGMCON_PERF_MON_RSLT1 0xd4d
+#define mmGMCON_PGFSM_CONFIG 0xd4e
+#define mmGMCON_PGFSM_WRITE 0xd4f
+#define mmGMCON_PGFSM_READ 0xd50
+#define mmGMCON_MISC3 0xd51
+#define mmGMCON_MASK 0xd52
+#define mmGMCON_LPT_TARGET 0xd53
+#define mmGMCON_DEBUG 0xd5f
+#define mmVM_L2_CNTL 0x500
+#define mmVM_L2_CNTL2 0x501
+#define mmVM_L2_CNTL3 0x502
+#define mmVM_L2_STATUS 0x503
+#define mmVM_CONTEXT0_CNTL 0x504
+#define mmVM_CONTEXT1_CNTL 0x505
+#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x506
+#define mmVM_DUMMY_PAGE_FAULT_ADDR 0x507
+#define mmVM_CONTEXT0_CNTL2 0x50c
+#define mmVM_CONTEXT1_CNTL2 0x50d
+#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x50e
+#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x50f
+#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x510
+#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x511
+#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x512
+#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x513
+#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x514
+#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x515
+#define mmVM_INVALIDATE_REQUEST 0x51e
+#define mmVM_INVALIDATE_RESPONSE 0x51f
+#define mmVM_PRT_APERTURE0_LOW_ADDR 0x52c
+#define mmVM_PRT_APERTURE1_LOW_ADDR 0x52d
+#define mmVM_PRT_APERTURE2_LOW_ADDR 0x52e
+#define mmVM_PRT_APERTURE3_LOW_ADDR 0x52f
+#define mmVM_PRT_APERTURE0_HIGH_ADDR 0x530
+#define mmVM_PRT_APERTURE1_HIGH_ADDR 0x531
+#define mmVM_PRT_APERTURE2_HIGH_ADDR 0x532
+#define mmVM_PRT_APERTURE3_HIGH_ADDR 0x533
+#define mmVM_PRT_CNTL 0x534
+#define mmVM_CONTEXTS_DISABLE 0x535
+#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0x536
+#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0x537
+#define mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT 0x538
+#define mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x539
+#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0x53e
+#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0x53f
+#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x546
+#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x547
+#define mmVM_FAULT_CLIENT_ID 0x54e
+#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f
+#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x550
+#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x551
+#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x552
+#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x553
+#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x554
+#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x555
+#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x556
+#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0x557
+#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0x558
+#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0x55f
+#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0x560
+#define mmVM_DEBUG 0x56f
+#define mmVM_L2_CG 0x570
+#define mmVM_L2_BANK_SELECT_MASKA 0x572
+#define mmVM_L2_BANK_SELECT_MASKB 0x573
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0x575
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0x576
+#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0x577
+#define mmMC_SEQ_CNTL 0xa25
+#define mmMC_SEQ_CNTL_2 0xad4
+#define mmMC_SEQ_DRAM 0xa26
+#define mmMC_SEQ_DRAM_2 0xa27
+#define mmMC_SEQ_RAS_TIMING 0xa28
+#define mmMC_SEQ_CAS_TIMING 0xa29
+#define mmMC_SEQ_MISC_TIMING 0xa2a
+#define mmMC_SEQ_MISC_TIMING2 0xa2b
+#define mmMC_SEQ_PMG_TIMING 0xa2c
+#define mmMC_SEQ_RD_CTL_D0 0xa2d
+#define mmMC_SEQ_RD_CTL_D1 0xa2e
+#define mmMC_SEQ_WR_CTL_D0 0xa2f
+#define mmMC_SEQ_WR_CTL_D1 0xa30
+#define mmMC_SEQ_WR_CTL_2 0xad5
+#define mmMC_SEQ_CMD 0xa31
+#define mmMC_PMG_CMD_EMRS 0xa83
+#define mmMC_PMG_CMD_MRS 0xaab
+#define mmMC_PMG_CMD_MRS1 0xad1
+#define mmMC_PMG_CMD_MRS2 0xad7
+#define mmMC_PMG_CFG 0xa84
+#define mmMC_PMG_AUTO_CMD 0xa34
+#define mmMC_PMG_AUTO_CFG 0xa35
+#define mmMC_IMP_CNTL 0xa36
+#define mmMC_IMP_DEBUG 0xa37
+#define mmMC_IMP_STATUS 0xa38
+#define mmMC_IMP_DQ_STATUS 0xabc
+#define mmMC_SEQ_WCDR_CTRL 0xa39
+#define mmMC_SEQ_TRAIN_WAKEUP_CNTL 0xa3a
+#define mmMC_SEQ_TRAIN_EDC_THRESHOLD 0xa3b
+#define mmMC_SEQ_TRAIN_EDC_THRESHOLD2 0xafe
+#define mmMC_SEQ_TRAIN_EDC_THRESHOLD3 0xaff
+#define mmMC_SEQ_TRAIN_WAKEUP_EDGE 0xa3c
+#define mmMC_SEQ_TRAIN_WAKEUP_MASK 0xa3d
+#define mmMC_SEQ_TRAIN_CAPTURE 0xa3e
+#define mmMC_SEQ_TRAIN_WAKEUP_CLEAR 0xa3f
+#define mmMC_SEQ_TRAIN_TIMING 0xa40
+#define mmMC_TRAIN_EDCCDR_R_D0 0xa41
+#define mmMC_TRAIN_EDCCDR_R_D1 0xa42
+#define mmMC_TRAIN_PRBSERR_0_D0 0xa43
+#define mmMC_TRAIN_PRBSERR_1_D0 0xa44
+#define mmMC_TRAIN_PRBSERR_2_D0 0xafb
+#define mmMC_TRAIN_EDC_STATUS_D0 0xa45
+#define mmMC_TRAIN_PRBSERR_0_D1 0xa46
+#define mmMC_TRAIN_PRBSERR_1_D1 0xa47
+#define mmMC_TRAIN_PRBSERR_2_D1 0xafc
+#define mmMC_TRAIN_EDC_STATUS_D1 0xa48
+#define mmMC_IO_TXCNTL_DPHY0_D0 0xa49
+#define mmMC_IO_TXCNTL_DPHY1_D0 0xa4a
+#define mmMC_IO_TXCNTL_APHY_D0 0xa4b
+#define mmMC_IO_RXCNTL_DPHY0_D0 0xa4c
+#define mmMC_IO_RXCNTL1_DPHY0_D0 0xadf
+#define mmMC_IO_RXCNTL_DPHY1_D0 0xa4d
+#define mmMC_IO_RXCNTL1_DPHY1_D0 0xae0
+#define mmMC_IO_DPHY_STR_CNTL_D0 0xa4e
+#define mmMC_IO_APHY_STR_CNTL_D0 0xa97
+#define mmMC_IO_TXCNTL_DPHY0_D1 0xa4f
+#define mmMC_IO_TXCNTL_DPHY1_D1 0xa50
+#define mmMC_IO_TXCNTL_APHY_D1 0xa51
+#define mmMC_IO_RXCNTL_DPHY0_D1 0xa52
+#define mmMC_IO_RXCNTL1_DPHY0_D1 0xae1
+#define mmMC_IO_RXCNTL_DPHY1_D1 0xa53
+#define mmMC_IO_RXCNTL1_DPHY1_D1 0xae2
+#define mmMC_IO_DPHY_STR_CNTL_D1 0xa54
+#define mmMC_IO_APHY_STR_CNTL_D1 0xa98
+#define mmMC_IO_CDRCNTL_D0 0xa55
+#define mmMC_IO_CDRCNTL1_D0 0xadd
+#define mmMC_IO_CDRCNTL2_D0 0xae4
+#define mmMC_IO_CDRCNTL_D1 0xa56
+#define mmMC_IO_CDRCNTL1_D1 0xade
+#define mmMC_IO_CDRCNTL2_D1 0xae5
+#define mmMC_SEQ_FIFO_CTL 0xa57
+#define mmMC_SEQ_TXFRAMING_BYTE0_D0 0xa58
+#define mmMC_SEQ_TXFRAMING_BYTE1_D0 0xa59
+#define mmMC_SEQ_TXFRAMING_BYTE2_D0 0xa5a
+#define mmMC_SEQ_TXFRAMING_BYTE3_D0 0xa5b
+#define mmMC_SEQ_TXFRAMING_DBI_D0 0xa5c
+#define mmMC_SEQ_TXFRAMING_EDC_D0 0xa5d
+#define mmMC_SEQ_TXFRAMING_FCK_D0 0xa5e
+#define mmMC_SEQ_TXFRAMING_BYTE0_D1 0xa60
+#define mmMC_SEQ_TXFRAMING_BYTE1_D1 0xa61
+#define mmMC_SEQ_TXFRAMING_BYTE2_D1 0xa62
+#define mmMC_SEQ_TXFRAMING_BYTE3_D1 0xa63
+#define mmMC_SEQ_TXFRAMING_DBI_D1 0xa64
+#define mmMC_SEQ_TXFRAMING_EDC_D1 0xa65
+#define mmMC_SEQ_TXFRAMING_FCK_D1 0xa66
+#define mmMC_SEQ_RXFRAMING_BYTE0_D0 0xa67
+#define mmMC_SEQ_RXFRAMING_BYTE1_D0 0xa68
+#define mmMC_SEQ_RXFRAMING_BYTE2_D0 0xa69
+#define mmMC_SEQ_RXFRAMING_BYTE3_D0 0xa6a
+#define mmMC_SEQ_RXFRAMING_DBI_D0 0xa6b
+#define mmMC_SEQ_RXFRAMING_EDC_D0 0xa6c
+#define mmMC_SEQ_RXFRAMING_BYTE0_D1 0xa6d
+#define mmMC_SEQ_RXFRAMING_BYTE1_D1 0xa6e
+#define mmMC_SEQ_RXFRAMING_BYTE2_D1 0xa6f
+#define mmMC_SEQ_RXFRAMING_BYTE3_D1 0xa70
+#define mmMC_SEQ_RXFRAMING_DBI_D1 0xa71
+#define mmMC_SEQ_RXFRAMING_EDC_D1 0xa72
+#define mmMC_IO_PAD_CNTL 0xa73
+#define mmMC_IO_PAD_CNTL_D0 0xa74
+#define mmMC_IO_PAD_CNTL_D1 0xa75
+#define mmMC_NPL_STATUS 0xa76
+#define mmMC_BIST_CMD_CNTL 0xa8e
+#define mmMC_BIST_CNTL 0xa05
+#define mmMC_BIST_AUTO_CNTL 0xa06
+#define mmMC_BIST_DIR_CNTL 0xa07
+#define mmMC_BIST_SADDR 0xa08
+#define mmMC_BIST_EADDR 0xa09
+#define mmMC_BIST_CMP_CNTL 0xa8d
+#define mmMC_BIST_CMP_CNTL_2 0xab6
+#define mmMC_BIST_DATA_WORD0 0xa0a
+#define mmMC_BIST_DATA_WORD1 0xa0b
+#define mmMC_BIST_DATA_WORD2 0xa0c
+#define mmMC_BIST_DATA_WORD3 0xa0d
+#define mmMC_BIST_DATA_WORD4 0xa0e
+#define mmMC_BIST_DATA_WORD5 0xa0f
+#define mmMC_BIST_DATA_WORD6 0xa10
+#define mmMC_BIST_DATA_WORD7 0xa11
+#define mmMC_BIST_DATA_MASK 0xa12
+#define mmMC_BIST_MISMATCH_ADDR 0xa13
+#define mmMC_BIST_RDATA_WORD0 0xa14
+#define mmMC_BIST_RDATA_WORD1 0xa15
+#define mmMC_BIST_RDATA_WORD2 0xa16
+#define mmMC_BIST_RDATA_WORD3 0xa17
+#define mmMC_BIST_RDATA_WORD4 0xa18
+#define mmMC_BIST_RDATA_WORD5 0xa19
+#define mmMC_BIST_RDATA_WORD6 0xa1a
+#define mmMC_BIST_RDATA_WORD7 0xa1b
+#define mmMC_BIST_RDATA_MASK 0xa1c
+#define mmMC_BIST_RDATA_EDC 0xa1d
+#define mmMC_SEQ_PERF_CNTL 0xa77
+#define mmMC_SEQ_PERF_CNTL_1 0xafd
+#define mmMC_SEQ_PERF_SEQ_CTL 0xa78
+#define mmMC_SEQ_PERF_SEQ_CNT_A_I0 0xa79
+#define mmMC_SEQ_PERF_SEQ_CNT_A_I1 0xa7a
+#define mmMC_SEQ_PERF_SEQ_CNT_B_I0 0xa7b
+#define mmMC_SEQ_PERF_SEQ_CNT_B_I1 0xa7c
+#define mmMC_SEQ_PERF_SEQ_CNT_C_I0 0xad9
+#define mmMC_SEQ_PERF_SEQ_CNT_C_I1 0xada
+#define mmMC_SEQ_PERF_SEQ_CNT_D_I0 0xadb
+#define mmMC_SEQ_PERF_SEQ_CNT_D_I1 0xadc
+#define mmMC_SEQ_STATUS_M 0xa7d
+#define mmMC_SEQ_STATUS_S 0xa20
+#define mmMC_CG_DATAPORT 0xa21
+#define mmMC_SEQ_VENDOR_ID_I0 0xa7e
+#define mmMC_SEQ_VENDOR_ID_I1 0xa7f
+#define mmMC_SEQ_MISC0 0xa80
+#define mmMC_SEQ_MISC1 0xa81
+#define mmMC_SEQ_RESERVE_0_S 0xa1e
+#define mmMC_SEQ_RESERVE_1_S 0xa1f
+#define mmMC_SEQ_RESERVE_M 0xa82
+#define mmMC_SEQ_IO_RESERVE_D0 0xab7
+#define mmMC_SEQ_IO_RESERVE_D1 0xab8
+#define mmMC_SEQ_SUP_CNTL 0xa32
+#define mmMC_SEQ_SUP_PGM 0xa33
+#define mmMC_SEQ_SUP_GP0_STAT 0xa8f
+#define mmMC_SEQ_SUP_GP1_STAT 0xa90
+#define mmMC_SEQ_SUP_GP2_STAT 0xa85
+#define mmMC_SEQ_SUP_GP3_STAT 0xa86
+#define mmMC_SEQ_SUP_IR_STAT 0xa87
+#define mmMC_SEQ_SUP_DEC_STAT 0xa88
+#define mmMC_SEQ_SUP_PGM_STAT 0xa89
+#define mmMC_SEQ_SUP_R_PGM 0xa8a
+#define mmMC_SEQ_MISC3 0xa8b
+#define mmMC_SEQ_MISC4 0xa8c
+#define mmMC_SEQ_MISC5 0xa95
+#define mmMC_SEQ_MISC6 0xa96
+#define mmMC_SEQ_MISC7 0xa99
+#define mmMC_SEQ_MISC8 0xa5f
+#define mmMC_SEQ_MISC9 0xae7
+#define mmMC_SEQ_CG 0xa9a
+#define mmMC_SEQ_BYTE_REMAP_D0 0xa93
+#define mmMC_SEQ_BYTE_REMAP_D1 0xa94
+#define mmMC_SEQ_BIT_REMAP_B0_D0 0xaa3
+#define mmMC_SEQ_BIT_REMAP_B1_D0 0xaa4
+#define mmMC_SEQ_BIT_REMAP_B2_D0 0xaa5
+#define mmMC_SEQ_BIT_REMAP_B3_D0 0xaa6
+#define mmMC_SEQ_BIT_REMAP_B0_D1 0xaa7
+#define mmMC_SEQ_BIT_REMAP_B1_D1 0xaa8
+#define mmMC_SEQ_BIT_REMAP_B2_D1 0xaa9
+#define mmMC_SEQ_BIT_REMAP_B3_D1 0xaaa
+#define mmMC_SEQ_RAS_TIMING_LP 0xa9b
+#define mmMC_SEQ_CAS_TIMING_LP 0xa9c
+#define mmMC_SEQ_MISC_TIMING_LP 0xa9d
+#define mmMC_SEQ_MISC_TIMING2_LP 0xa9e
+#define mmMC_SEQ_RD_CTL_D0_LP 0xac7
+#define mmMC_SEQ_RD_CTL_D1_LP 0xac8
+#define mmMC_SEQ_WR_CTL_D0_LP 0xa9f
+#define mmMC_SEQ_WR_CTL_D1_LP 0xaa0
+#define mmMC_SEQ_WR_CTL_2_LP 0xad6
+#define mmMC_SEQ_PMG_CMD_EMRS_LP 0xaa1
+#define mmMC_SEQ_PMG_CMD_MRS_LP 0xaa2
+#define mmMC_SEQ_PMG_CMD_MRS1_LP 0xad2
+#define mmMC_SEQ_PMG_CMD_MRS2_LP 0xad8
+#define mmMC_SEQ_PMG_TIMING_LP 0xad3
+#define mmMC_SEQ_IO_RWORD0 0xaac
+#define mmMC_SEQ_IO_RWORD1 0xaad
+#define mmMC_SEQ_IO_RWORD2 0xaae
+#define mmMC_SEQ_IO_RWORD3 0xaaf
+#define mmMC_SEQ_IO_RWORD4 0xab0
+#define mmMC_SEQ_IO_RWORD5 0xab1
+#define mmMC_SEQ_IO_RWORD6 0xab2
+#define mmMC_SEQ_IO_RWORD7 0xab3
+#define mmMC_SEQ_IO_RDBI 0xab4
+#define mmMC_SEQ_IO_REDC 0xab5
+#define mmMC_SEQ_TCG_CNTL 0xabd
+#define mmMC_SEQ_TSM_CTRL 0xabe
+#define mmMC_SEQ_TSM_GCNT 0xabf
+#define mmMC_SEQ_TSM_OCNT 0xac0
+#define mmMC_SEQ_TSM_NCNT 0xac1
+#define mmMC_SEQ_TSM_BCNT 0xac2
+#define mmMC_SEQ_TSM_FLAG 0xac3
+#define mmMC_SEQ_TSM_UPDATE 0xac4
+#define mmMC_SEQ_TSM_EDC 0xac5
+#define mmMC_SEQ_TSM_DBI 0xac6
+#define mmMC_SEQ_TSM_WCDR 0xae3
+#define mmMC_SEQ_TSM_MISC 0xae6
+#define mmMC_SEQ_TIMER_WR 0xac9
+#define mmMC_SEQ_TIMER_RD 0xaca
+#define mmMC_SEQ_DRAM_ERROR_INSERTION 0xacb
+#define mmMC_PHY_TIMING_D0 0xacc
+#define mmMC_PHY_TIMING_D1 0xacd
+#define mmMC_PHY_TIMING_2 0xace
+#define mmMC_SEQ_MPLL_OVERRIDE 0xa22
+#define mmMCLK_PWRMGT_CNTL 0xae8
+#define mmDLL_CNTL 0xae9
+#define mmMPLL_SEQ_UCODE_1 0xaea
+#define mmMPLL_SEQ_UCODE_2 0xaeb
+#define mmMPLL_CNTL_MODE 0xaec
+#define mmMPLL_FUNC_CNTL 0xaed
+#define mmMPLL_FUNC_CNTL_1 0xaee
+#define mmMPLL_FUNC_CNTL_2 0xaef
+#define mmMPLL_AD_FUNC_CNTL 0xaf0
+#define mmMPLL_DQ_FUNC_CNTL 0xaf1
+#define mmMPLL_TIME 0xaf2
+#define mmMPLL_SS1 0xaf3
+#define mmMPLL_SS2 0xaf4
+#define mmMPLL_CONTROL 0xaf5
+#define mmMPLL_AD_STATUS 0xaf6
+#define mmMPLL_DQ_0_0_STATUS 0xaf7
+#define mmMPLL_DQ_0_1_STATUS 0xaf8
+#define mmMPLL_DQ_1_0_STATUS 0xaf9
+#define mmMPLL_DQ_1_1_STATUS 0xafa
+#define mmMC_SEQ_PMG_PG_HWCNTL 0xab9
+#define mmMC_SEQ_PMG_PG_SWCNTL_0 0xaba
+#define mmMC_SEQ_PMG_PG_SWCNTL_1 0xabb
+#define mmMC_SEQ_TSM_DEBUG_INDEX 0xacf
+#define mmMC_SEQ_TSM_DEBUG_DATA 0xad0
+#define ixMC_TSM_DEBUG_GCNT 0x0
+#define ixMC_TSM_DEBUG_FLAG 0x1
+#define ixMC_TSM_DEBUG_MISC 0x2
+#define ixMC_TSM_DEBUG_BCNT0 0x3
+#define ixMC_TSM_DEBUG_BCNT1 0x4
+#define ixMC_TSM_DEBUG_BCNT2 0x5
+#define ixMC_TSM_DEBUG_BCNT3 0x6
+#define ixMC_TSM_DEBUG_BCNT4 0x7
+#define ixMC_TSM_DEBUG_BCNT5 0x8
+#define ixMC_TSM_DEBUG_BCNT6 0x9
+#define ixMC_TSM_DEBUG_BCNT7 0xa
+#define ixMC_TSM_DEBUG_BCNT8 0xb
+#define ixMC_TSM_DEBUG_BCNT9 0xc
+#define ixMC_TSM_DEBUG_BCNT10 0xd
+#define ixMC_TSM_DEBUG_ST01 0x10
+#define ixMC_TSM_DEBUG_ST23 0x11
+#define ixMC_TSM_DEBUG_ST45 0x12
+#define ixMC_TSM_DEBUG_BKPT 0x13
+#define mmMC_SEQ_IO_DEBUG_INDEX 0xa91
+#define mmMC_SEQ_IO_DEBUG_DATA 0xa92
+#define ixMC_IO_DEBUG_UP_0 0x0
+#define ixMC_IO_DEBUG_UP_1 0x1
+#define ixMC_IO_DEBUG_UP_2 0x2
+#define ixMC_IO_DEBUG_UP_3 0x3
+#define ixMC_IO_DEBUG_UP_4 0x4
+#define ixMC_IO_DEBUG_UP_5 0x5
+#define ixMC_IO_DEBUG_UP_6 0x6
+#define ixMC_IO_DEBUG_UP_7 0x7
+#define ixMC_IO_DEBUG_UP_8 0x8
+#define ixMC_IO_DEBUG_UP_9 0x9
+#define ixMC_IO_DEBUG_UP_10 0xa
+#define ixMC_IO_DEBUG_UP_11 0xb
+#define ixMC_IO_DEBUG_UP_12 0xc
+#define ixMC_IO_DEBUG_UP_13 0xd
+#define ixMC_IO_DEBUG_UP_14 0xe
+#define ixMC_IO_DEBUG_UP_15 0xf
+#define ixMC_IO_DEBUG_UP_16 0x10
+#define ixMC_IO_DEBUG_UP_17 0x11
+#define ixMC_IO_DEBUG_UP_18 0x12
+#define ixMC_IO_DEBUG_UP_19 0x13
+#define ixMC_IO_DEBUG_UP_20 0x14
+#define ixMC_IO_DEBUG_UP_21 0x15
+#define ixMC_IO_DEBUG_UP_22 0x16
+#define ixMC_IO_DEBUG_UP_23 0x17
+#define ixMC_IO_DEBUG_UP_24 0x18
+#define ixMC_IO_DEBUG_UP_25 0x19
+#define ixMC_IO_DEBUG_UP_26 0x1a
+#define ixMC_IO_DEBUG_UP_27 0x1b
+#define ixMC_IO_DEBUG_UP_28 0x1c
+#define ixMC_IO_DEBUG_UP_29 0x1d
+#define ixMC_IO_DEBUG_UP_30 0x1e
+#define ixMC_IO_DEBUG_UP_31 0x1f
+#define ixMC_IO_DEBUG_UP_32 0x20
+#define ixMC_IO_DEBUG_UP_33 0x21
+#define ixMC_IO_DEBUG_UP_34 0x22
+#define ixMC_IO_DEBUG_UP_35 0x23
+#define ixMC_IO_DEBUG_UP_36 0x24
+#define ixMC_IO_DEBUG_UP_37 0x25
+#define ixMC_IO_DEBUG_UP_38 0x26
+#define ixMC_IO_DEBUG_UP_39 0x27
+#define ixMC_IO_DEBUG_UP_40 0x28
+#define ixMC_IO_DEBUG_UP_41 0x29
+#define ixMC_IO_DEBUG_UP_42 0x2a
+#define ixMC_IO_DEBUG_UP_43 0x2b
+#define ixMC_IO_DEBUG_UP_44 0x2c
+#define ixMC_IO_DEBUG_UP_45 0x2d
+#define ixMC_IO_DEBUG_UP_46 0x2e
+#define ixMC_IO_DEBUG_UP_47 0x2f
+#define ixMC_IO_DEBUG_UP_48 0x30
+#define ixMC_IO_DEBUG_UP_49 0x31
+#define ixMC_IO_DEBUG_UP_50 0x32
+#define ixMC_IO_DEBUG_UP_51 0x33
+#define ixMC_IO_DEBUG_UP_52 0x34
+#define ixMC_IO_DEBUG_UP_53 0x35
+#define ixMC_IO_DEBUG_UP_54 0x36
+#define ixMC_IO_DEBUG_UP_55 0x37
+#define ixMC_IO_DEBUG_UP_56 0x38
+#define ixMC_IO_DEBUG_UP_57 0x39
+#define ixMC_IO_DEBUG_UP_58 0x3a
+#define ixMC_IO_DEBUG_UP_59 0x3b
+#define ixMC_IO_DEBUG_UP_60 0x3c
+#define ixMC_IO_DEBUG_UP_61 0x3d
+#define ixMC_IO_DEBUG_UP_62 0x3e
+#define ixMC_IO_DEBUG_UP_63 0x3f
+#define ixMC_IO_DEBUG_UP_64 0x40
+#define ixMC_IO_DEBUG_UP_65 0x41
+#define ixMC_IO_DEBUG_UP_66 0x42
+#define ixMC_IO_DEBUG_UP_67 0x43
+#define ixMC_IO_DEBUG_UP_68 0x44
+#define ixMC_IO_DEBUG_UP_69 0x45
+#define ixMC_IO_DEBUG_UP_70 0x46
+#define ixMC_IO_DEBUG_UP_71 0x47
+#define ixMC_IO_DEBUG_UP_72 0x48
+#define ixMC_IO_DEBUG_UP_73 0x49
+#define ixMC_IO_DEBUG_UP_74 0x4a
+#define ixMC_IO_DEBUG_UP_75 0x4b
+#define ixMC_IO_DEBUG_UP_76 0x4c
+#define ixMC_IO_DEBUG_UP_77 0x4d
+#define ixMC_IO_DEBUG_UP_78 0x4e
+#define ixMC_IO_DEBUG_UP_79 0x4f
+#define ixMC_IO_DEBUG_UP_80 0x50
+#define ixMC_IO_DEBUG_UP_81 0x51
+#define ixMC_IO_DEBUG_UP_82 0x52
+#define ixMC_IO_DEBUG_UP_83 0x53
+#define ixMC_IO_DEBUG_UP_84 0x54
+#define ixMC_IO_DEBUG_UP_85 0x55
+#define ixMC_IO_DEBUG_UP_86 0x56
+#define ixMC_IO_DEBUG_UP_87 0x57
+#define ixMC_IO_DEBUG_UP_88 0x58
+#define ixMC_IO_DEBUG_UP_89 0x59
+#define ixMC_IO_DEBUG_UP_90 0x5a
+#define ixMC_IO_DEBUG_UP_91 0x5b
+#define ixMC_IO_DEBUG_UP_92 0x5c
+#define ixMC_IO_DEBUG_UP_93 0x5d
+#define ixMC_IO_DEBUG_UP_94 0x5e
+#define ixMC_IO_DEBUG_UP_95 0x5f
+#define ixMC_IO_DEBUG_UP_96 0x60
+#define ixMC_IO_DEBUG_UP_97 0x61
+#define ixMC_IO_DEBUG_UP_98 0x62
+#define ixMC_IO_DEBUG_UP_99 0x63
+#define ixMC_IO_DEBUG_UP_100 0x64
+#define ixMC_IO_DEBUG_UP_101 0x65
+#define ixMC_IO_DEBUG_UP_102 0x66
+#define ixMC_IO_DEBUG_UP_103 0x67
+#define ixMC_IO_DEBUG_UP_104 0x68
+#define ixMC_IO_DEBUG_UP_105 0x69
+#define ixMC_IO_DEBUG_UP_106 0x6a
+#define ixMC_IO_DEBUG_UP_107 0x6b
+#define ixMC_IO_DEBUG_UP_108 0x6c
+#define ixMC_IO_DEBUG_UP_109 0x6d
+#define ixMC_IO_DEBUG_UP_110 0x6e
+#define ixMC_IO_DEBUG_UP_111 0x6f
+#define ixMC_IO_DEBUG_UP_112 0x70
+#define ixMC_IO_DEBUG_UP_113 0x71
+#define ixMC_IO_DEBUG_UP_114 0x72
+#define ixMC_IO_DEBUG_UP_115 0x73
+#define ixMC_IO_DEBUG_UP_116 0x74
+#define ixMC_IO_DEBUG_UP_117 0x75
+#define ixMC_IO_DEBUG_UP_118 0x76
+#define ixMC_IO_DEBUG_UP_119 0x77
+#define ixMC_IO_DEBUG_UP_120 0x78
+#define ixMC_IO_DEBUG_UP_121 0x79
+#define ixMC_IO_DEBUG_UP_122 0x7a
+#define ixMC_IO_DEBUG_UP_123 0x7b
+#define ixMC_IO_DEBUG_UP_124 0x7c
+#define ixMC_IO_DEBUG_UP_125 0x7d
+#define ixMC_IO_DEBUG_UP_126 0x7e
+#define ixMC_IO_DEBUG_UP_127 0x7f
+#define ixMC_IO_DEBUG_UP_128 0x80
+#define ixMC_IO_DEBUG_UP_129 0x81
+#define ixMC_IO_DEBUG_UP_130 0x82
+#define ixMC_IO_DEBUG_UP_131 0x83
+#define ixMC_IO_DEBUG_UP_132 0x84
+#define ixMC_IO_DEBUG_UP_133 0x85
+#define ixMC_IO_DEBUG_UP_134 0x86
+#define ixMC_IO_DEBUG_UP_135 0x87
+#define ixMC_IO_DEBUG_UP_136 0x88
+#define ixMC_IO_DEBUG_UP_137 0x89
+#define ixMC_IO_DEBUG_UP_138 0x8a
+#define ixMC_IO_DEBUG_UP_139 0x8b
+#define ixMC_IO_DEBUG_UP_140 0x8c
+#define ixMC_IO_DEBUG_UP_141 0x8d
+#define ixMC_IO_DEBUG_UP_142 0x8e
+#define ixMC_IO_DEBUG_UP_143 0x8f
+#define ixMC_IO_DEBUG_UP_144 0x90
+#define ixMC_IO_DEBUG_UP_145 0x91
+#define ixMC_IO_DEBUG_UP_146 0x92
+#define ixMC_IO_DEBUG_UP_147 0x93
+#define ixMC_IO_DEBUG_UP_148 0x94
+#define ixMC_IO_DEBUG_UP_149 0x95
+#define ixMC_IO_DEBUG_UP_150 0x96
+#define ixMC_IO_DEBUG_UP_151 0x97
+#define ixMC_IO_DEBUG_UP_152 0x98
+#define ixMC_IO_DEBUG_UP_153 0x99
+#define ixMC_IO_DEBUG_UP_154 0x9a
+#define ixMC_IO_DEBUG_UP_155 0x9b
+#define ixMC_IO_DEBUG_UP_156 0x9c
+#define ixMC_IO_DEBUG_UP_157 0x9d
+#define ixMC_IO_DEBUG_UP_158 0x9e
+#define ixMC_IO_DEBUG_UP_159 0x9f
+#define ixMC_IO_DEBUG_DQB0L_MISC_D0 0xa0
+#define ixMC_IO_DEBUG_DQB0H_MISC_D0 0xa1
+#define ixMC_IO_DEBUG_DQB1L_MISC_D0 0xa2
+#define ixMC_IO_DEBUG_DQB1H_MISC_D0 0xa3
+#define ixMC_IO_DEBUG_DQB2L_MISC_D0 0xa4
+#define ixMC_IO_DEBUG_DQB2H_MISC_D0 0xa5
+#define ixMC_IO_DEBUG_DQB3L_MISC_D0 0xa6
+#define ixMC_IO_DEBUG_DQB3H_MISC_D0 0xa7
+#define ixMC_IO_DEBUG_DBI_MISC_D0 0xa8
+#define ixMC_IO_DEBUG_EDC_MISC_D0 0xa9
+#define ixMC_IO_DEBUG_WCK_MISC_D0 0xaa
+#define ixMC_IO_DEBUG_CK_MISC_D0 0xab
+#define ixMC_IO_DEBUG_ADDRL_MISC_D0 0xac
+#define ixMC_IO_DEBUG_ADDRH_MISC_D0 0xad
+#define ixMC_IO_DEBUG_ACMD_MISC_D0 0xae
+#define ixMC_IO_DEBUG_CMD_MISC_D0 0xaf
+#define ixMC_IO_DEBUG_DQB0L_MISC_D1 0xb0
+#define ixMC_IO_DEBUG_DQB0H_MISC_D1 0xb1
+#define ixMC_IO_DEBUG_DQB1L_MISC_D1 0xb2
+#define ixMC_IO_DEBUG_DQB1H_MISC_D1 0xb3
+#define ixMC_IO_DEBUG_DQB2L_MISC_D1 0xb4
+#define ixMC_IO_DEBUG_DQB2H_MISC_D1 0xb5
+#define ixMC_IO_DEBUG_DQB3L_MISC_D1 0xb6
+#define ixMC_IO_DEBUG_DQB3H_MISC_D1 0xb7
+#define ixMC_IO_DEBUG_DBI_MISC_D1 0xb8
+#define ixMC_IO_DEBUG_EDC_MISC_D1 0xb9
+#define ixMC_IO_DEBUG_WCK_MISC_D1 0xba
+#define ixMC_IO_DEBUG_CK_MISC_D1 0xbb
+#define ixMC_IO_DEBUG_ADDRL_MISC_D1 0xbc
+#define ixMC_IO_DEBUG_ADDRH_MISC_D1 0xbd
+#define ixMC_IO_DEBUG_ACMD_MISC_D1 0xbe
+#define ixMC_IO_DEBUG_CMD_MISC_D1 0xbf
+#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D0 0xc0
+#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D0 0xc1
+#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D0 0xc2
+#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D0 0xc3
+#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D0 0xc4
+#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D0 0xc5
+#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D0 0xc6
+#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D0 0xc7
+#define ixMC_IO_DEBUG_DBI_CLKSEL_D0 0xc8
+#define ixMC_IO_DEBUG_EDC_CLKSEL_D0 0xc9
+#define ixMC_IO_DEBUG_WCK_CLKSEL_D0 0xca
+#define ixMC_IO_DEBUG_CK_CLKSEL_D0 0xcb
+#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D0 0xcc
+#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D0 0xcd
+#define ixMC_IO_DEBUG_ACMD_CLKSEL_D0 0xce
+#define ixMC_IO_DEBUG_CMD_CLKSEL_D0 0xcf
+#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D1 0xd0
+#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D1 0xd1
+#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D1 0xd2
+#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D1 0xd3
+#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D1 0xd4
+#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D1 0xd5
+#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D1 0xd6
+#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D1 0xd7
+#define ixMC_IO_DEBUG_DBI_CLKSEL_D1 0xd8
+#define ixMC_IO_DEBUG_EDC_CLKSEL_D1 0xd9
+#define ixMC_IO_DEBUG_WCK_CLKSEL_D1 0xda
+#define ixMC_IO_DEBUG_CK_CLKSEL_D1 0xdb
+#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D1 0xdc
+#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D1 0xdd
+#define ixMC_IO_DEBUG_ACMD_CLKSEL_D1 0xde
+#define ixMC_IO_DEBUG_CMD_CLKSEL_D1 0xdf
+#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D0 0xe0
+#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D0 0xe1
+#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D0 0xe2
+#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D0 0xe3
+#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D0 0xe4
+#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D0 0xe5
+#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D0 0xe6
+#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D0 0xe7
+#define ixMC_IO_DEBUG_DBI_OFSCAL_D0 0xe8
+#define ixMC_IO_DEBUG_EDC_OFSCAL_D0 0xe9
+#define ixMC_IO_DEBUG_WCK_OFSCAL_D0 0xea
+#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0 0xeb
+#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0 0xec
+#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0 0xed
+#define ixMC_IO_DEBUG_ACMD_OFSCAL_D0 0xee
+#define ixMC_IO_DEBUG_CMD_OFSCAL_D0 0xef
+#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D1 0xf0
+#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D1 0xf1
+#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D1 0xf2
+#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D1 0xf3
+#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D1 0xf4
+#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D1 0xf5
+#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D1 0xf6
+#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D1 0xf7
+#define ixMC_IO_DEBUG_DBI_OFSCAL_D1 0xf8
+#define ixMC_IO_DEBUG_EDC_OFSCAL_D1 0xf9
+#define ixMC_IO_DEBUG_WCK_OFSCAL_D1 0xfa
+#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1 0xfb
+#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1 0xfc
+#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1 0xfd
+#define ixMC_IO_DEBUG_ACMD_OFSCAL_D1 0xfe
+#define ixMC_IO_DEBUG_CMD_OFSCAL_D1 0xff
+#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D0 0x100
+#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D0 0x101
+#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D0 0x102
+#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D0 0x103
+#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D0 0x104
+#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D0 0x105
+#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D0 0x106
+#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D0 0x107
+#define ixMC_IO_DEBUG_DBI_RXPHASE_D0 0x108
+#define ixMC_IO_DEBUG_EDC_RXPHASE_D0 0x109
+#define ixMC_IO_DEBUG_WCK_RXPHASE_D0 0x10a
+#define ixMC_IO_DEBUG_CK_RXPHASE_D0 0x10b
+#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D0 0x10c
+#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D0 0x10d
+#define ixMC_IO_DEBUG_ACMD_RXPHASE_D0 0x10e
+#define ixMC_IO_DEBUG_CMD_RXPHASE_D0 0x10f
+#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D1 0x110
+#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D1 0x111
+#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D1 0x112
+#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D1 0x113
+#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D1 0x114
+#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D1 0x115
+#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D1 0x116
+#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D1 0x117
+#define ixMC_IO_DEBUG_DBI_RXPHASE_D1 0x118
+#define ixMC_IO_DEBUG_EDC_RXPHASE_D1 0x119
+#define ixMC_IO_DEBUG_WCK_RXPHASE_D1 0x11a
+#define ixMC_IO_DEBUG_CK_RXPHASE_D1 0x11b
+#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D1 0x11c
+#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D1 0x11d
+#define ixMC_IO_DEBUG_ACMD_RXPHASE_D1 0x11e
+#define ixMC_IO_DEBUG_CMD_RXPHASE_D1 0x11f
+#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D0 0x120
+#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D0 0x121
+#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D0 0x122
+#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D0 0x123
+#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D0 0x124
+#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D0 0x125
+#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D0 0x126
+#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D0 0x127
+#define ixMC_IO_DEBUG_DBI_TXPHASE_D0 0x128
+#define ixMC_IO_DEBUG_EDC_TXPHASE_D0 0x129
+#define ixMC_IO_DEBUG_WCK_TXPHASE_D0 0x12a
+#define ixMC_IO_DEBUG_CK_TXPHASE_D0 0x12b
+#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D0 0x12c
+#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D0 0x12d
+#define ixMC_IO_DEBUG_ACMD_TXPHASE_D0 0x12e
+#define ixMC_IO_DEBUG_CMD_TXPHASE_D0 0x12f
+#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D1 0x130
+#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D1 0x131
+#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D1 0x132
+#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D1 0x133
+#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D1 0x134
+#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D1 0x135
+#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D1 0x136
+#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D1 0x137
+#define ixMC_IO_DEBUG_DBI_TXPHASE_D1 0x138
+#define ixMC_IO_DEBUG_EDC_TXPHASE_D1 0x139
+#define ixMC_IO_DEBUG_WCK_TXPHASE_D1 0x13a
+#define ixMC_IO_DEBUG_CK_TXPHASE_D1 0x13b
+#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D1 0x13c
+#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D1 0x13d
+#define ixMC_IO_DEBUG_ACMD_TXPHASE_D1 0x13e
+#define ixMC_IO_DEBUG_CMD_TXPHASE_D1 0x13f
+#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0 0x140
+#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0 0x141
+#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0 0x142
+#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0 0x143
+#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0 0x144
+#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0 0x145
+#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0 0x146
+#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0 0x147
+#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0 0x148
+#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0 0x149
+#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0 0x14a
+#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0 0x14b
+#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0 0x14c
+#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0 0x14d
+#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0 0x14e
+#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0 0x14f
+#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1 0x150
+#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1 0x151
+#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1 0x152
+#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1 0x153
+#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1 0x154
+#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1 0x155
+#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1 0x156
+#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1 0x157
+#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1 0x158
+#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1 0x159
+#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1 0x15a
+#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1 0x15b
+#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1 0x15c
+#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1 0x15d
+#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1 0x15e
+#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1 0x15f
+#define ixMC_IO_DEBUG_DQB0L_TXSLF_D0 0x160
+#define ixMC_IO_DEBUG_DQB0H_TXSLF_D0 0x161
+#define ixMC_IO_DEBUG_DQB1L_TXSLF_D0 0x162
+#define ixMC_IO_DEBUG_DQB1H_TXSLF_D0 0x163
+#define ixMC_IO_DEBUG_DQB2L_TXSLF_D0 0x164
+#define ixMC_IO_DEBUG_DQB2H_TXSLF_D0 0x165
+#define ixMC_IO_DEBUG_DQB3L_TXSLF_D0 0x166
+#define ixMC_IO_DEBUG_DQB3H_TXSLF_D0 0x167
+#define ixMC_IO_DEBUG_DBI_TXSLF_D0 0x168
+#define ixMC_IO_DEBUG_EDC_TXSLF_D0 0x169
+#define ixMC_IO_DEBUG_WCK_TXSLF_D0 0x16a
+#define ixMC_IO_DEBUG_CK_TXSLF_D0 0x16b
+#define ixMC_IO_DEBUG_ADDRL_TXSLF_D0 0x16c
+#define ixMC_IO_DEBUG_ADDRH_TXSLF_D0 0x16d
+#define ixMC_IO_DEBUG_ACMD_TXSLF_D0 0x16e
+#define ixMC_IO_DEBUG_CMD_TXSLF_D0 0x16f
+#define ixMC_IO_DEBUG_DQB0L_TXSLF_D1 0x170
+#define ixMC_IO_DEBUG_DQB0H_TXSLF_D1 0x171
+#define ixMC_IO_DEBUG_DQB1L_TXSLF_D1 0x172
+#define ixMC_IO_DEBUG_DQB1H_TXSLF_D1 0x173
+#define ixMC_IO_DEBUG_DQB2L_TXSLF_D1 0x174
+#define ixMC_IO_DEBUG_DQB2H_TXSLF_D1 0x175
+#define ixMC_IO_DEBUG_DQB3L_TXSLF_D1 0x176
+#define ixMC_IO_DEBUG_DQB3H_TXSLF_D1 0x177
+#define ixMC_IO_DEBUG_DBI_TXSLF_D1 0x178
+#define ixMC_IO_DEBUG_EDC_TXSLF_D1 0x179
+#define ixMC_IO_DEBUG_WCK_TXSLF_D1 0x17a
+#define ixMC_IO_DEBUG_CK_TXSLF_D1 0x17b
+#define ixMC_IO_DEBUG_ADDRL_TXSLF_D1 0x17c
+#define ixMC_IO_DEBUG_ADDRH_TXSLF_D1 0x17d
+#define ixMC_IO_DEBUG_ACMD_TXSLF_D1 0x17e
+#define ixMC_IO_DEBUG_CMD_TXSLF_D1 0x17f
+#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0 0x180
+#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0 0x181
+#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0 0x182
+#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0 0x183
+#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0 0x184
+#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0 0x185
+#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0 0x186
+#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0 0x187
+#define ixMC_IO_DEBUG_DBI_TXBST_PD_D0 0x188
+#define ixMC_IO_DEBUG_EDC_TXBST_PD_D0 0x189
+#define ixMC_IO_DEBUG_WCK_TXBST_PD_D0 0x18a
+#define ixMC_IO_DEBUG_CK_TXBST_PD_D0 0x18b
+#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0 0x18c
+#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0 0x18d
+#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D0 0x18e
+#define ixMC_IO_DEBUG_CMD_TXBST_PD_D0 0x18f
+#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1 0x190
+#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1 0x191
+#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1 0x192
+#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1 0x193
+#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1 0x194
+#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1 0x195
+#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1 0x196
+#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1 0x197
+#define ixMC_IO_DEBUG_DBI_TXBST_PD_D1 0x198
+#define ixMC_IO_DEBUG_EDC_TXBST_PD_D1 0x199
+#define ixMC_IO_DEBUG_WCK_TXBST_PD_D1 0x19a
+#define ixMC_IO_DEBUG_CK_TXBST_PD_D1 0x19b
+#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1 0x19c
+#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1 0x19d
+#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D1 0x19e
+#define ixMC_IO_DEBUG_CMD_TXBST_PD_D1 0x19f
+#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0 0x1a0
+#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0 0x1a1
+#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0 0x1a2
+#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0 0x1a3
+#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0 0x1a4
+#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0 0x1a5
+#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0 0x1a6
+#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0 0x1a7
+#define ixMC_IO_DEBUG_DBI_TXBST_PU_D0 0x1a8
+#define ixMC_IO_DEBUG_EDC_TXBST_PU_D0 0x1a9
+#define ixMC_IO_DEBUG_WCK_TXBST_PU_D0 0x1aa
+#define ixMC_IO_DEBUG_CK_TXBST_PU_D0 0x1ab
+#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0 0x1ac
+#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0 0x1ad
+#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D0 0x1ae
+#define ixMC_IO_DEBUG_CMD_TXBST_PU_D0 0x1af
+#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1 0x1b0
+#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1 0x1b1
+#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1 0x1b2
+#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1 0x1b3
+#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1 0x1b4
+#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1 0x1b5
+#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1 0x1b6
+#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1 0x1b7
+#define ixMC_IO_DEBUG_DBI_TXBST_PU_D1 0x1b8
+#define ixMC_IO_DEBUG_EDC_TXBST_PU_D1 0x1b9
+#define ixMC_IO_DEBUG_WCK_TXBST_PU_D1 0x1ba
+#define ixMC_IO_DEBUG_CK_TXBST_PU_D1 0x1bb
+#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1 0x1bc
+#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1 0x1bd
+#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D1 0x1be
+#define ixMC_IO_DEBUG_CMD_TXBST_PU_D1 0x1bf
+#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D0 0x1c0
+#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D0 0x1c1
+#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D0 0x1c2
+#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D0 0x1c3
+#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D0 0x1c4
+#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D0 0x1c5
+#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D0 0x1c6
+#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D0 0x1c7
+#define ixMC_IO_DEBUG_DBI_RX_EQ_D0 0x1c8
+#define ixMC_IO_DEBUG_EDC_RX_EQ_D0 0x1c9
+#define ixMC_IO_DEBUG_WCK_RX_EQ_D0 0x1ca
+#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0 0x1cb
+#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0 0x1cc
+#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0 0x1cd
+#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0 0x1ce
+#define ixMC_IO_DEBUG_CMD_RX_EQ_D0 0x1cf
+#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D1 0x1d0
+#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D1 0x1d1
+#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D1 0x1d2
+#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D1 0x1d3
+#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D1 0x1d4
+#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D1 0x1d5
+#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D1 0x1d6
+#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D1 0x1d7
+#define ixMC_IO_DEBUG_DBI_RX_EQ_D1 0x1d8
+#define ixMC_IO_DEBUG_EDC_RX_EQ_D1 0x1d9
+#define ixMC_IO_DEBUG_WCK_RX_EQ_D1 0x1da
+#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1 0x1db
+#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1 0x1dc
+#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1 0x1dd
+#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1 0x1de
+#define ixMC_IO_DEBUG_CMD_RX_EQ_D1 0x1df
+#define ixMC_IO_DEBUG_WCDR_MISC_D0 0x1e0
+#define ixMC_IO_DEBUG_WCDR_CLKSEL_D0 0x1e1
+#define ixMC_IO_DEBUG_WCDR_OFSCAL_D0 0x1e2
+#define ixMC_IO_DEBUG_WCDR_RXPHASE_D0 0x1e3
+#define ixMC_IO_DEBUG_WCDR_TXPHASE_D0 0x1e4
+#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0 0x1e5
+#define ixMC_IO_DEBUG_WCDR_TXSLF_D0 0x1e6
+#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D0 0x1e7
+#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D0 0x1e8
+#define ixMC_IO_DEBUG_WCDR_RX_EQ_D0 0x1e9
+#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0 0x1ea
+#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0 0x1eb
+#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0 0x1ec
+#define ixMC_IO_DEBUG_WCDR_MISC_D1 0x1f0
+#define ixMC_IO_DEBUG_WCDR_CLKSEL_D1 0x1f1
+#define ixMC_IO_DEBUG_WCDR_OFSCAL_D1 0x1f2
+#define ixMC_IO_DEBUG_WCDR_RXPHASE_D1 0x1f3
+#define ixMC_IO_DEBUG_WCDR_TXPHASE_D1 0x1f4
+#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1 0x1f5
+#define ixMC_IO_DEBUG_WCDR_TXSLF_D1 0x1f6
+#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D1 0x1f7
+#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D1 0x1f8
+#define ixMC_IO_DEBUG_WCDR_RX_EQ_D1 0x1f9
+#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1 0x1fa
+#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1 0x1fb
+#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1 0x1fc
+#define mmMC_SEQ_CNTL_3 0xd80
+#define mmMC_SEQ_G5PDX_CTRL 0xd81
+#define mmMC_SEQ_G5PDX_CTRL_LP 0xd82
+#define mmMC_SEQ_G5PDX_CMD0 0xd83
+#define mmMC_SEQ_G5PDX_CMD0_LP 0xd84
+#define mmMC_SEQ_G5PDX_CMD1 0xd85
+#define mmMC_SEQ_G5PDX_CMD1_LP 0xd86
+#define mmMC_SEQ_SREG_READ 0xd87
+#define mmMC_SEQ_SREG_STATUS 0xd88
+#define mmMC_SEQ_PHYREG_BCAST 0xd89
+#define mmMC_SEQ_PMG_DVS_CTL 0xd8a
+#define mmMC_SEQ_PMG_DVS_CTL_LP 0xd8b
+#define mmMC_SEQ_PMG_DVS_CMD 0xd8c
+#define mmMC_SEQ_PMG_DVS_CMD_LP 0xd8d
+#define mmMC_SEQ_DLL_STBY 0xd8e
+#define mmMC_SEQ_DLL_STBY_LP 0xd8f
+#define mmMC_DLB_MISCCTRL0 0xd90
+#define mmMC_DLB_MISCCTRL1 0xd91
+#define mmMC_DLB_MISCCTRL2 0xd92
+#define mmMC_DLB_CONFIG0 0xd93
+#define mmMC_DLB_CONFIG1 0xd94
+#define mmMC_DLB_SETUP 0xd95
+#define mmMC_DLB_SETUPSWEEP 0xd96
+#define mmMC_DLB_SETUPFIFO 0xd97
+#define mmMC_DLB_WRITE_MASK 0xd98
+#define mmMC_DLB_STATUS 0xd99
+#define mmMC_DLB_STATUS_MISC0 0xd9a
+#define mmMC_DLB_STATUS_MISC1 0xd9b
+#define mmMC_DLB_STATUS_MISC2 0xd9c
+#define mmMC_DLB_STATUS_MISC3 0xd9d
+#define mmMC_DLB_STATUS_MISC4 0xd9e
+#define mmMC_DLB_STATUS_MISC5 0xd9f
+#define mmMC_DLB_STATUS_MISC6 0xda0
+#define mmMC_DLB_STATUS_MISC7 0xda1
+#define mmMC_ARB_HARSH_EN_RD 0xdc0
+#define mmMC_ARB_HARSH_EN_WR 0xdc1
+#define mmMC_ARB_HARSH_TX_HI0_RD 0xdc2
+#define mmMC_ARB_HARSH_TX_HI0_WR 0xdc3
+#define mmMC_ARB_HARSH_TX_HI1_RD 0xdc4
+#define mmMC_ARB_HARSH_TX_HI1_WR 0xdc5
+#define mmMC_ARB_HARSH_TX_LO0_RD 0xdc6
+#define mmMC_ARB_HARSH_TX_LO0_WR 0xdc7
+#define mmMC_ARB_HARSH_TX_LO1_RD 0xdc8
+#define mmMC_ARB_HARSH_TX_LO1_WR 0xdc9
+#define mmMC_ARB_HARSH_BWPERIOD0_RD 0xdca
+#define mmMC_ARB_HARSH_BWPERIOD0_WR 0xdcb
+#define mmMC_ARB_HARSH_BWPERIOD1_RD 0xdcc
+#define mmMC_ARB_HARSH_BWPERIOD1_WR 0xdcd
+#define mmMC_ARB_HARSH_BWCNT0_RD 0xdce
+#define mmMC_ARB_HARSH_BWCNT0_WR 0xdcf
+#define mmMC_ARB_HARSH_BWCNT1_RD 0xdd0
+#define mmMC_ARB_HARSH_BWCNT1_WR 0xdd1
+#define mmMC_ARB_HARSH_SAT0_RD 0xdd2
+#define mmMC_ARB_HARSH_SAT0_WR 0xdd3
+#define mmMC_ARB_HARSH_SAT1_RD 0xdd4
+#define mmMC_ARB_HARSH_SAT1_WR 0xdd5
+#define mmMC_ARB_HARSH_CTL_RD 0xdd6
+#define mmMC_ARB_HARSH_CTL_WR 0xdd7
+
+#endif /* GMC_7_1_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h
new file mode 100644
index 000000000000..3a202b69d5aa
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h
@@ -0,0 +1,14416 @@
+/*
+ * GMC_7_1 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GMC_7_1_SH_MASK_H
+#define GMC_7_1_SH_MASK_H
+
+#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
+#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
+#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
+#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
+#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
+#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
+#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
+#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
+#define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
+#define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
+#define MC_CONFIG__MCDT_WR_ENABLE_MASK 0x20
+#define MC_CONFIG__MCDT_WR_ENABLE__SHIFT 0x5
+#define MC_CONFIG__MCDU_WR_ENABLE_MASK 0x40
+#define MC_CONFIG__MCDU_WR_ENABLE__SHIFT 0x6
+#define MC_CONFIG__MCDV_WR_ENABLE_MASK 0x80
+#define MC_CONFIG__MCDV_WR_ENABLE__SHIFT 0x7
+#define MC_CONFIG__MC_RD_ENABLE_MASK 0x700
+#define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x8
+#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000
+#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x1f
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0_MASK 0x1
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0__SHIFT 0x0
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1_MASK 0x2
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1__SHIFT 0x1
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2_MASK 0x4
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2__SHIFT 0x2
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3__SHIFT 0x3
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4__SHIFT 0x4
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5_MASK 0x20
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5__SHIFT 0x5
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6_MASK 0x40
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6__SHIFT 0x6
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7_MASK 0x80
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7__SHIFT 0x7
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0_MASK 0x100
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1_MASK 0x200
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1__SHIFT 0x9
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2_MASK 0x400
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x800
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3__SHIFT 0xb
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4_MASK 0x1000
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4__SHIFT 0xc
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5_MASK 0x2000
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5__SHIFT 0xd
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6_MASK 0x4000
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT 0xe
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7_MASK 0x8000
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7__SHIFT 0xf
+#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD_MASK 0x70000
+#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10
+#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR_MASK 0x380000
+#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR__SHIFT 0x13
+#define MC_ARB_AGE_CNTL__TIMER_STALL_RD_MASK 0x400000
+#define MC_ARB_AGE_CNTL__TIMER_STALL_RD__SHIFT 0x16
+#define MC_ARB_AGE_CNTL__TIMER_STALL_WR_MASK 0x800000
+#define MC_ARB_AGE_CNTL__TIMER_STALL_WR__SHIFT 0x17
+#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD_MASK 0x1000000
+#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD__SHIFT 0x18
+#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR_MASK 0x2000000
+#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR__SHIFT 0x19
+#define MC_ARB_RET_CREDITS2__ACP_WR_MASK 0xff
+#define MC_ARB_RET_CREDITS2__ACP_WR__SHIFT 0x0
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD_MASK 0x100
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT 0x8
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR_MASK 0x200
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR__SHIFT 0x9
+#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG_MASK 0x400
+#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG__SHIFT 0xa
+#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG_MASK 0x800
+#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG__SHIFT 0xb
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD_MASK 0x1000
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD__SHIFT 0xc
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR_MASK 0x2000
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR__SHIFT 0xd
+#define MC_ARB_FED_CNTL__MODE_MASK 0x3
+#define MC_ARB_FED_CNTL__MODE__SHIFT 0x0
+#define MC_ARB_FED_CNTL__WR_ERR_MASK 0xc
+#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x2
+#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10
+#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x4
+#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK_MASK 0x20
+#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK__SHIFT 0x5
+#define MC_ARB_FED_CNTL__USE_LEGACY_NACK_MASK 0x40
+#define MC_ARB_FED_CNTL__USE_LEGACY_NACK__SHIFT 0x6
+#define MC_ARB_FED_CNTL__DEBUG_RSV_MASK 0xffffff80
+#define MC_ARB_FED_CNTL__DEBUG_RSV__SHIFT 0x7
+#define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x1
+#define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x0
+#define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x2
+#define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x1
+#define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x4
+#define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x2
+#define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8
+#define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x3
+#define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10
+#define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x4
+#define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x20
+#define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x5
+#define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x40
+#define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x6
+#define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x80
+#define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x7
+#define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x100
+#define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8
+#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x200
+#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x9
+#define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x400
+#define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa
+#define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x800
+#define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0xb
+#define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x1000
+#define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0xc
+#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x2000
+#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0xd
+#define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x4000
+#define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0xe
+#define MC_ARB_GECC2_STATUS__RSVD3_MASK 0x8000
+#define MC_ARB_GECC2_STATUS__RSVD3__SHIFT 0xf
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0_MASK 0x10000
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0_MASK 0x20000
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0__SHIFT 0x11
+#define MC_ARB_GECC2_STATUS__RSVD4_MASK 0xc0000
+#define MC_ARB_GECC2_STATUS__RSVD4__SHIFT 0x12
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1_MASK 0x100000
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1__SHIFT 0x14
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1_MASK 0x200000
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1__SHIFT 0x15
+#define MC_ARB_GECC2_STATUS__RSVD5_MASK 0xc00000
+#define MC_ARB_GECC2_STATUS__RSVD5__SHIFT 0x16
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0_MASK 0x1000000
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0__SHIFT 0x18
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0_MASK 0x2000000
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0__SHIFT 0x19
+#define MC_ARB_GECC2_STATUS__RSVD6_MASK 0xc000000
+#define MC_ARB_GECC2_STATUS__RSVD6__SHIFT 0x1a
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1_MASK 0x10000000
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1__SHIFT 0x1c
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1_MASK 0x20000000
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d
+#define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0xf
+#define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x0
+#define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10
+#define MC_ARB_GECC2_MISC__COL10_HACK__SHIFT 0x4
+#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY_MASK 0x20
+#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY__SHIFT 0x5
+#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY_MASK 0x40
+#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY__SHIFT 0x6
+#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL_MASK 0x80
+#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL__SHIFT 0x7
+#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE_MASK 0x100
+#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE__SHIFT 0x8
+#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY_MASK 0x200
+#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY__SHIFT 0x9
+#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN_MASK 0x400
+#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN__SHIFT 0xa
+#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN_MASK 0x800
+#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN__SHIFT 0xb
+#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY_MASK 0x1000
+#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY__SHIFT 0xc
+#define MC_ARB_GECC2_MISC__DEBUG_RSV_MASK 0xffffe000
+#define MC_ARB_GECC2_MISC__DEBUG_RSV__SHIFT 0xd
+#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x3
+#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x0
+#define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x4
+#define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x2
+#define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x18
+#define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x3
+#define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x20
+#define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x5
+#define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0xff
+#define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x0
+#define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0xff00
+#define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8
+#define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0xff0000
+#define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10
+#define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000
+#define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x18
+#define MC_ARB_PERF_CID__CH0_MASK 0xff
+#define MC_ARB_PERF_CID__CH0__SHIFT 0x0
+#define MC_ARB_PERF_CID__CH1_MASK 0xff00
+#define MC_ARB_PERF_CID__CH1__SHIFT 0x8
+#define MC_ARB_PERF_CID__CH0_EN_MASK 0x10000
+#define MC_ARB_PERF_CID__CH0_EN__SHIFT 0x10
+#define MC_ARB_PERF_CID__CH1_EN_MASK 0x20000
+#define MC_ARB_PERF_CID__CH1_EN__SHIFT 0x11
+#define MC_ARB_GECC2__ENABLE_MASK 0x1
+#define MC_ARB_GECC2__ENABLE__SHIFT 0x0
+#define MC_ARB_GECC2__ECC_MODE_MASK 0x6
+#define MC_ARB_GECC2__ECC_MODE__SHIFT 0x1
+#define MC_ARB_GECC2__PAGE_BIT0_MASK 0x18
+#define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x3
+#define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x60
+#define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x5
+#define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x780
+#define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x7
+#define MC_ARB_GECC2__READ_ERR_MASK 0x3800
+#define MC_ARB_GECC2__READ_ERR__SHIFT 0xb
+#define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x4000
+#define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0xe
+#define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x1f8000
+#define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0xf
+#define MC_ARB_GECC2__WRADDR_CONV_MASK 0x200000
+#define MC_ARB_GECC2__WRADDR_CONV__SHIFT 0x15
+#define MC_ARB_GECC2__RMWRD_UNCOR_POISON_MASK 0x400000
+#define MC_ARB_GECC2__RMWRD_UNCOR_POISON__SHIFT 0x16
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0xff
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x0
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0xff00
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x8
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0xff0000
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x10
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x18
+#define MC_ARB_ADDR_SWIZ0__A8_MASK 0xf
+#define MC_ARB_ADDR_SWIZ0__A8__SHIFT 0x0
+#define MC_ARB_ADDR_SWIZ0__A9_MASK 0xf0
+#define MC_ARB_ADDR_SWIZ0__A9__SHIFT 0x4
+#define MC_ARB_ADDR_SWIZ0__A10_MASK 0xf00
+#define MC_ARB_ADDR_SWIZ0__A10__SHIFT 0x8
+#define MC_ARB_ADDR_SWIZ0__A11_MASK 0xf000
+#define MC_ARB_ADDR_SWIZ0__A11__SHIFT 0xc
+#define MC_ARB_ADDR_SWIZ0__A12_MASK 0xf0000
+#define MC_ARB_ADDR_SWIZ0__A12__SHIFT 0x10
+#define MC_ARB_ADDR_SWIZ0__A13_MASK 0xf00000
+#define MC_ARB_ADDR_SWIZ0__A13__SHIFT 0x14
+#define MC_ARB_ADDR_SWIZ0__A14_MASK 0xf000000
+#define MC_ARB_ADDR_SWIZ0__A14__SHIFT 0x18
+#define MC_ARB_ADDR_SWIZ0__A15_MASK 0xf0000000
+#define MC_ARB_ADDR_SWIZ0__A15__SHIFT 0x1c
+#define MC_ARB_ADDR_SWIZ1__A16_MASK 0xf
+#define MC_ARB_ADDR_SWIZ1__A16__SHIFT 0x0
+#define MC_ARB_ADDR_SWIZ1__A17_MASK 0xf0
+#define MC_ARB_ADDR_SWIZ1__A17__SHIFT 0x4
+#define MC_ARB_ADDR_SWIZ1__A18_MASK 0xf00
+#define MC_ARB_ADDR_SWIZ1__A18__SHIFT 0x8
+#define MC_ARB_ADDR_SWIZ1__A19_MASK 0xf000
+#define MC_ARB_ADDR_SWIZ1__A19__SHIFT 0xc
+#define MC_ARB_MISC3__NO_GECC_EXT_EOB_MASK 0x1
+#define MC_ARB_MISC3__NO_GECC_EXT_EOB__SHIFT 0x0
+#define MC_ARB_MISC3__CHAN4_EN_MASK 0x2
+#define MC_ARB_MISC3__CHAN4_EN__SHIFT 0x1
+#define MC_ARB_MISC3__CHAN4_ARB_SEL_MASK 0x4
+#define MC_ARB_MISC3__CHAN4_ARB_SEL__SHIFT 0x2
+#define MC_ARB_MISC3__TBD_FIELD_MASK 0xfffffff8
+#define MC_ARB_MISC3__TBD_FIELD__SHIFT 0x3
+#define MC_ARB_WCDR_2__WPRE_INC_STEP_MASK 0xf
+#define MC_ARB_WCDR_2__WPRE_INC_STEP__SHIFT 0x0
+#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD_MASK 0x1f0
+#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD__SHIFT 0x4
+#define MC_ARB_WCDR_2__DEBUG_0_MASK 0x200
+#define MC_ARB_WCDR_2__DEBUG_0__SHIFT 0x9
+#define MC_ARB_WCDR_2__DEBUG_1_MASK 0x400
+#define MC_ARB_WCDR_2__DEBUG_1__SHIFT 0xa
+#define MC_ARB_WCDR_2__DEBUG_2_MASK 0x800
+#define MC_ARB_WCDR_2__DEBUG_2__SHIFT 0xb
+#define MC_ARB_WCDR_2__DEBUG_3_MASK 0x1000
+#define MC_ARB_WCDR_2__DEBUG_3__SHIFT 0xc
+#define MC_ARB_WCDR_2__DEBUG_4_MASK 0x2000
+#define MC_ARB_WCDR_2__DEBUG_4__SHIFT 0xd
+#define MC_ARB_WCDR_2__DEBUG_5_MASK 0x4000
+#define MC_ARB_WCDR_2__DEBUG_5__SHIFT 0xe
+#define MC_ARB_RTT_DATA__PATTERN_MASK 0xff
+#define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x0
+#define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x1
+#define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x0
+#define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x2
+#define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x1
+#define MC_ARB_RTT_CNTL0__START_R2W_MASK 0xc
+#define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x2
+#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x10
+#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x4
+#define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x20
+#define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x5
+#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x40
+#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x6
+#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x80
+#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x7
+#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x100
+#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x8
+#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x200
+#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x9
+#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x400
+#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa
+#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x3800
+#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0xb
+#define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x4000
+#define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0xe
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x8000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0xf
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x10000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x10
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x20000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x11
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x40000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x12
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x80000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x13
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x100000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x14
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x200000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x15
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x400000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x16
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x800000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x17
+#define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x1000000
+#define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x18
+#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x2000000
+#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x19
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x1f
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x0
+#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x20
+#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x5
+#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x1fc0
+#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x6
+#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0xfe000
+#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0xd
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x1f00000
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x14
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x19
+#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000
+#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x1e
+#define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x3f
+#define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x0
+#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0xfc0
+#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x6
+#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x1000
+#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0xc
+#define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x2000
+#define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0xd
+#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x3
+#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x0
+#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0xc
+#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x2
+#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0xff0
+#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x4
+#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x1f000
+#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0xc
+#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x1fe0000
+#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x11
+#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000
+#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x19
+#define MC_ARB_CAC_CNTL__ENABLE_MASK 0x1
+#define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x0
+#define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x7e
+#define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x1
+#define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x1f80
+#define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x7
+#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x2000
+#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0xd
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x20
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x5
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x40
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x6
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x80
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x7
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x100
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x8
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x200
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x9
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x400
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa
+#define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x800
+#define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0xb
+#define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x1000
+#define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0xc
+#define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x2000
+#define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0xd
+#define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x3c000
+#define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0xe
+#define MC_ARB_MISC2__GECC_MASK 0x40000
+#define MC_ARB_MISC2__GECC__SHIFT 0x12
+#define MC_ARB_MISC2__GECC_RST_MASK 0x80000
+#define MC_ARB_MISC2__GECC_RST__SHIFT 0x13
+#define MC_ARB_MISC2__GECC_STATUS_MASK 0x100000
+#define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x14
+#define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x1e00000
+#define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x15
+#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0xe000000
+#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x19
+#define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000
+#define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x1c
+#define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000
+#define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d
+#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000
+#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x1e
+#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000
+#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x1f
+#define MC_ARB_MISC__STICKY_RFSH_MASK 0x1
+#define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x0
+#define MC_ARB_MISC__IDLE_RFSH_MASK 0x2
+#define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x1
+#define MC_ARB_MISC__STUTTER_RFSH_MASK 0x4
+#define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x2
+#define MC_ARB_MISC__CHAN_COUPLE_MASK 0x7f8
+#define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x3
+#define MC_ARB_MISC__HARSHNESS_MASK 0x7f800
+#define MC_ARB_MISC__HARSHNESS__SHIFT 0xb
+#define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x80000
+#define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x13
+#define MC_ARB_MISC__CALI_ENABLE_MASK 0x100000
+#define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x14
+#define MC_ARB_MISC__CALI_RATES_MASK 0x600000
+#define MC_ARB_MISC__CALI_RATES__SHIFT 0x15
+#define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x800000
+#define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x17
+#define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x1000000
+#define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x18
+#define MC_ARB_MISC__DISPURG_STALL_MASK 0x2000000
+#define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x19
+#define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000
+#define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x1a
+#define MC_ARB_MISC__EXTEND_WEIGHT_MASK 0x40000000
+#define MC_ARB_MISC__EXTEND_WEIGHT__SHIFT 0x1e
+#define MC_ARB_MISC__ACPURG_STALL_MASK 0x80000000
+#define MC_ARB_MISC__ACPURG_STALL__SHIFT 0x1f
+#define MC_ARB_BANKMAP__BANK0_MASK 0xf
+#define MC_ARB_BANKMAP__BANK0__SHIFT 0x0
+#define MC_ARB_BANKMAP__BANK1_MASK 0xf0
+#define MC_ARB_BANKMAP__BANK1__SHIFT 0x4
+#define MC_ARB_BANKMAP__BANK2_MASK 0xf00
+#define MC_ARB_BANKMAP__BANK2__SHIFT 0x8
+#define MC_ARB_BANKMAP__BANK3_MASK 0xf000
+#define MC_ARB_BANKMAP__BANK3__SHIFT 0xc
+#define MC_ARB_BANKMAP__RANK_MASK 0xf0000
+#define MC_ARB_BANKMAP__RANK__SHIFT 0x10
+#define MC_ARB_RAMCFG__NOOFBANK_MASK 0x3
+#define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x0
+#define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x4
+#define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x2
+#define MC_ARB_RAMCFG__NOOFROWS_MASK 0x38
+#define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x3
+#define MC_ARB_RAMCFG__NOOFCOLS_MASK 0xc0
+#define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x6
+#define MC_ARB_RAMCFG__CHANSIZE_MASK 0x100
+#define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x8
+#define MC_ARB_RAMCFG__RSV_1_MASK 0x200
+#define MC_ARB_RAMCFG__RSV_1__SHIFT 0x9
+#define MC_ARB_RAMCFG__RSV_2_MASK 0x400
+#define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa
+#define MC_ARB_RAMCFG__RSV_3_MASK 0x800
+#define MC_ARB_RAMCFG__RSV_3__SHIFT 0xb
+#define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x1000
+#define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0xc
+#define MC_ARB_RAMCFG__RSV_4_MASK 0x3e000
+#define MC_ARB_RAMCFG__RSV_4__SHIFT 0xd
+#define MC_ARB_POP__ENABLE_ARB_MASK 0x1
+#define MC_ARB_POP__ENABLE_ARB__SHIFT 0x0
+#define MC_ARB_POP__SPEC_OPEN_MASK 0x2
+#define MC_ARB_POP__SPEC_OPEN__SHIFT 0x1
+#define MC_ARB_POP__POP_DEPTH_MASK 0x3c
+#define MC_ARB_POP__POP_DEPTH__SHIFT 0x2
+#define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0xfc0
+#define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x6
+#define MC_ARB_POP__SKID_DEPTH_MASK 0x7000
+#define MC_ARB_POP__SKID_DEPTH__SHIFT 0xc
+#define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x18000
+#define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0xf
+#define MC_ARB_POP__QUICK_STOP_MASK 0x20000
+#define MC_ARB_POP__QUICK_STOP__SHIFT 0x11
+#define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x40000
+#define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x12
+#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x80000
+#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x13
+#define MC_ARB_MINCLKS__READ_CLKS_MASK 0xff
+#define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x0
+#define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0xff00
+#define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x8
+#define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x10000
+#define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x10
+#define MC_ARB_MINCLKS__RW_SWITCH_HARSH_MASK 0x60000
+#define MC_ARB_MINCLKS__RW_SWITCH_HARSH__SHIFT 0x11
+#define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0xff
+#define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x0
+#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x100
+#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x8
+#define MC_ARB_SQM_CNTL__SQM_RDY16_MASK 0x200
+#define MC_ARB_SQM_CNTL__SQM_RDY16__SHIFT 0x9
+#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0xfc00
+#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa
+#define MC_ARB_SQM_CNTL__RATIO_MASK 0xff0000
+#define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x10
+#define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000
+#define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x18
+#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0xf
+#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x0
+#define MC_ARB_ADDR_HASH__COL_XOR_MASK 0xff0
+#define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x4
+#define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0xffff000
+#define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0xc
+#define MC_ARB_DRAM_TIMING__ACTRD_MASK 0xff
+#define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x0
+#define MC_ARB_DRAM_TIMING__ACTWR_MASK 0xff00
+#define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x8
+#define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0xff0000
+#define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x10
+#define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000
+#define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x18
+#define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0xff
+#define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x0
+#define MC_ARB_DRAM_TIMING2__RP_MASK 0xff00
+#define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x8
+#define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0xff0000
+#define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x10
+#define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000
+#define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x18
+#define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x3
+#define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x0
+#define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x4
+#define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x2
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x8
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x3
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x10
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x4
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x20
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x5
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x40
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x6
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x80
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x7
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x100
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x8
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x200
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x9
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x400
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa
+#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK 0x800
+#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI__SHIFT 0xb
+#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP_MASK 0x1000
+#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP__SHIFT 0xc
+#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG_MASK 0x2000
+#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG__SHIFT 0xd
+#define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x3
+#define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x0
+#define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x4
+#define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x2
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x8
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x3
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x10
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x4
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x20
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x5
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x40
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x6
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x80
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x7
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x100
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x8
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x200
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x9
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x400
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa
+#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK 0x800
+#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI__SHIFT 0xb
+#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP_MASK 0x1000
+#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP__SHIFT 0xc
+#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG_MASK 0x2000
+#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG__SHIFT 0xd
+#define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x3
+#define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x0
+#define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0xc
+#define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x2
+#define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x30
+#define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x4
+#define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0xc0
+#define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x6
+#define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x300
+#define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x8
+#define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0xc00
+#define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0xa
+#define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x3000
+#define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0xc
+#define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0xc000
+#define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0xe
+#define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0xff0000
+#define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x10
+#define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x3
+#define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x0
+#define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0xc
+#define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x2
+#define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x30
+#define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x4
+#define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0xc0
+#define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x6
+#define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x300
+#define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x8
+#define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0xc00
+#define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0xa
+#define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x3000
+#define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0xc
+#define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0xc000
+#define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0xe
+#define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0xff0000
+#define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x10
+#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x1
+#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x0
+#define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x6
+#define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x1
+#define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x8
+#define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x3
+#define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x10
+#define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x4
+#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x1
+#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x0
+#define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x6
+#define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x1
+#define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x8
+#define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x3
+#define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x10
+#define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x4
+#define MC_ARB_LAZY0_RD__GROUP0_MASK 0xff
+#define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_LAZY0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_LAZY0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_LAZY0_WR__GROUP0_MASK 0xff
+#define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_LAZY0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_LAZY0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_LAZY1_RD__GROUP4_MASK 0xff
+#define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_LAZY1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_LAZY1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_LAZY1_WR__GROUP4_MASK 0xff
+#define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_LAZY1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_LAZY1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x3
+#define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x0
+#define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0xc
+#define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x2
+#define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x30
+#define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x4
+#define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0xc0
+#define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x6
+#define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x300
+#define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x8
+#define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0xc00
+#define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0xa
+#define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x3000
+#define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0xc
+#define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0xc000
+#define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0xe
+#define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x10000
+#define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x10
+#define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x20000
+#define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x11
+#define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x40000
+#define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x12
+#define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x80000
+#define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x13
+#define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x100000
+#define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x14
+#define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x200000
+#define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x15
+#define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x400000
+#define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x16
+#define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x800000
+#define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x17
+#define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x1000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x18
+#define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x2000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x19
+#define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x4000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x1a
+#define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x8000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x1b
+#define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x1c
+#define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d
+#define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x1e
+#define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x1f
+#define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x3
+#define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x0
+#define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0xc
+#define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x2
+#define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x30
+#define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x4
+#define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0xc0
+#define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x6
+#define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x300
+#define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x8
+#define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0xc00
+#define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0xa
+#define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x3000
+#define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0xc
+#define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0xc000
+#define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0xe
+#define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x10000
+#define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x10
+#define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x20000
+#define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x11
+#define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x40000
+#define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x12
+#define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x80000
+#define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x13
+#define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x100000
+#define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x14
+#define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x200000
+#define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x15
+#define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x400000
+#define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x16
+#define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x800000
+#define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x17
+#define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x1000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x18
+#define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x2000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x19
+#define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x4000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x1a
+#define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x8000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x1b
+#define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x1c
+#define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d
+#define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x1e
+#define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x1f
+#define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x1
+#define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x0
+#define MC_ARB_RFSH_CNTL__URG0_MASK 0x3e
+#define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x1
+#define MC_ARB_RFSH_CNTL__URG1_MASK 0x7c0
+#define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x6
+#define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x800
+#define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0xb
+#define MC_ARB_RFSH_CNTL__SINGLE_BANK_MASK 0x1000
+#define MC_ARB_RFSH_CNTL__SINGLE_BANK__SHIFT 0xc
+#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH_MASK 0x2000
+#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH__SHIFT 0xd
+#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL_MASK 0x1c000
+#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL__SHIFT 0xe
+#define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0xff
+#define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x0
+#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x3
+#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x0
+#define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x4
+#define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x2
+#define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x8
+#define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x3
+#define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x10
+#define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x4
+#define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x20
+#define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x5
+#define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x40
+#define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x6
+#define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x80
+#define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x7
+#define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x300
+#define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x8
+#define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x400
+#define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0xa
+#define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x800
+#define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb
+#define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x1000
+#define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0xc
+#define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x2000
+#define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd
+#define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x4000
+#define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0xe
+#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000
+#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf
+#define MC_ARB_PM_CNTL__RSV_0_MASK 0x30000
+#define MC_ARB_PM_CNTL__RSV_0__SHIFT 0x10
+#define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x40000
+#define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x12
+#define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x80000
+#define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x13
+#define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0xf00000
+#define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x14
+#define MC_ARB_PM_CNTL__RSV_1_MASK 0x1000000
+#define MC_ARB_PM_CNTL__RSV_1__SHIFT 0x18
+#define MC_ARB_PM_CNTL__RSV_2_MASK 0x2000000
+#define MC_ARB_PM_CNTL__RSV_2__SHIFT 0x19
+#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0xf
+#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x0
+#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0xf0
+#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x4
+#define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x100
+#define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x8
+#define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x200
+#define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x9
+#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
+#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
+#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0xf
+#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x0
+#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0xf0
+#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x4
+#define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x100
+#define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x8
+#define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x200
+#define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x9
+#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
+#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
+#define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0xff
+#define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x0
+#define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0xff00
+#define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x8
+#define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x10000
+#define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x10
+#define MC_ARB_LM_RD__STREAK_UBER_MASK 0x20000
+#define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x11
+#define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x40000
+#define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x12
+#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x80000
+#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x13
+#define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x100000
+#define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x14
+#define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0xe00000
+#define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x15
+#define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0xff
+#define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x0
+#define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0xff00
+#define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x8
+#define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x10000
+#define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x10
+#define MC_ARB_LM_WR__STREAK_UBER_MASK 0x20000
+#define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x11
+#define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x40000
+#define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x12
+#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x80000
+#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x13
+#define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x100000
+#define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x14
+#define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0xe00000
+#define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x15
+#define MC_ARB_LM_WR__MASKWR_LM_EOB_MASK 0x1000000
+#define MC_ARB_LM_WR__MASKWR_LM_EOB__SHIFT 0x18
+#define MC_ARB_REMREQ__RD_WATER_MASK 0xff
+#define MC_ARB_REMREQ__RD_WATER__SHIFT 0x0
+#define MC_ARB_REMREQ__WR_WATER_MASK 0xff00
+#define MC_ARB_REMREQ__WR_WATER__SHIFT 0x8
+#define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0xf0000
+#define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x10
+#define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0xf00000
+#define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x14
+#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ_MASK 0x1000000
+#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ__SHIFT 0x18
+#define MC_ARB_REPLAY__ENABLE_RD_MASK 0x1
+#define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x0
+#define MC_ARB_REPLAY__ENABLE_WR_MASK 0x2
+#define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x1
+#define MC_ARB_REPLAY__WRACK_MODE_MASK 0x4
+#define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x2
+#define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x8
+#define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x3
+#define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x10
+#define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x4
+#define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x20
+#define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x5
+#define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x40
+#define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x6
+#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x80
+#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x7
+#define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x7f00
+#define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x8
+#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START_MASK 0x8000
+#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START__SHIFT 0xf
+#define MC_ARB_RET_CREDITS_RD__LCL_MASK 0xff
+#define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x0
+#define MC_ARB_RET_CREDITS_RD__HUB_MASK 0xff00
+#define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x8
+#define MC_ARB_RET_CREDITS_RD__DISP_MASK 0xff0000
+#define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x10
+#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000
+#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x18
+#define MC_ARB_RET_CREDITS_WR__LCL_MASK 0xff
+#define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x0
+#define MC_ARB_RET_CREDITS_WR__HUB_MASK 0xff00
+#define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x8
+#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0xff0000
+#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x10
+#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0xf000000
+#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x18
+#define MC_ARB_RET_CREDITS_WR__WRRET_BP_MASK 0x10000000
+#define MC_ARB_RET_CREDITS_WR__WRRET_BP__SHIFT 0x1c
+#define MC_ARB_MAX_LAT_CID__CID_CH0_MASK 0xff
+#define MC_ARB_MAX_LAT_CID__CID_CH0__SHIFT 0x0
+#define MC_ARB_MAX_LAT_CID__CID_CH1_MASK 0xff00
+#define MC_ARB_MAX_LAT_CID__CID_CH1__SHIFT 0x8
+#define MC_ARB_MAX_LAT_CID__WRITE_CH0_MASK 0x10000
+#define MC_ARB_MAX_LAT_CID__WRITE_CH0__SHIFT 0x10
+#define MC_ARB_MAX_LAT_CID__WRITE_CH1_MASK 0x20000
+#define MC_ARB_MAX_LAT_CID__WRITE_CH1__SHIFT 0x11
+#define MC_ARB_MAX_LAT_CID__REALTIME_CH0_MASK 0x40000
+#define MC_ARB_MAX_LAT_CID__REALTIME_CH0__SHIFT 0x12
+#define MC_ARB_MAX_LAT_CID__REALTIME_CH1_MASK 0x80000
+#define MC_ARB_MAX_LAT_CID__REALTIME_CH1__SHIFT 0x13
+#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY_MASK 0xffffffff
+#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY__SHIFT 0x0
+#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY_MASK 0xffffffff
+#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY__SHIFT 0x0
+#define MC_ARB_SSM__FORMAT_MASK 0x1f
+#define MC_ARB_SSM__FORMAT__SHIFT 0x0
+#define MC_ARB_CG__CG_ARB_REQ_MASK 0xff
+#define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x0
+#define MC_ARB_CG__CG_ARB_RESP_MASK 0xff00
+#define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x8
+#define MC_ARB_CG__RSV_0_MASK 0xff0000
+#define MC_ARB_CG__RSV_0__SHIFT 0x10
+#define MC_ARB_CG__RSV_1_MASK 0xff000000
+#define MC_ARB_CG__RSV_1__SHIFT 0x18
+#define MC_ARB_WCDR__IDLE_ENABLE_MASK 0x1
+#define MC_ARB_WCDR__IDLE_ENABLE__SHIFT 0x0
+#define MC_ARB_WCDR__SEQ_IDLE_MASK 0x2
+#define MC_ARB_WCDR__SEQ_IDLE__SHIFT 0x1
+#define MC_ARB_WCDR__IDLE_PERIOD_MASK 0x7c
+#define MC_ARB_WCDR__IDLE_PERIOD__SHIFT 0x2
+#define MC_ARB_WCDR__IDLE_BURST_MASK 0x1f80
+#define MC_ARB_WCDR__IDLE_BURST__SHIFT 0x7
+#define MC_ARB_WCDR__IDLE_BURST_MODE_MASK 0x2000
+#define MC_ARB_WCDR__IDLE_BURST_MODE__SHIFT 0xd
+#define MC_ARB_WCDR__IDLE_WAKEUP_MASK 0xc000
+#define MC_ARB_WCDR__IDLE_WAKEUP__SHIFT 0xe
+#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE_MASK 0x10000
+#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE__SHIFT 0x10
+#define MC_ARB_WCDR__WPRE_ENABLE_MASK 0x20000
+#define MC_ARB_WCDR__WPRE_ENABLE__SHIFT 0x11
+#define MC_ARB_WCDR__WPRE_THRESHOLD_MASK 0x3c0000
+#define MC_ARB_WCDR__WPRE_THRESHOLD__SHIFT 0x12
+#define MC_ARB_WCDR__WPRE_MAX_BURST_MASK 0x1c00000
+#define MC_ARB_WCDR__WPRE_MAX_BURST__SHIFT 0x16
+#define MC_ARB_WCDR__WPRE_INC_READ_MASK 0x2000000
+#define MC_ARB_WCDR__WPRE_INC_READ__SHIFT 0x19
+#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE_MASK 0x4000000
+#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE__SHIFT 0x1a
+#define MC_ARB_WCDR__WPRE_INC_SEQIDLE_MASK 0x8000000
+#define MC_ARB_WCDR__WPRE_INC_SEQIDLE__SHIFT 0x1b
+#define MC_ARB_WCDR__WPRE_TWOPAGE_MASK 0x10000000
+#define MC_ARB_WCDR__WPRE_TWOPAGE__SHIFT 0x1c
+#define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0xff
+#define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x0
+#define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0xff00
+#define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x8
+#define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0xff0000
+#define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x10
+#define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000
+#define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x18
+#define MC_ARB_BUSY_STATUS__LM_RD0_MASK 0x1
+#define MC_ARB_BUSY_STATUS__LM_RD0__SHIFT 0x0
+#define MC_ARB_BUSY_STATUS__LM_RD1_MASK 0x2
+#define MC_ARB_BUSY_STATUS__LM_RD1__SHIFT 0x1
+#define MC_ARB_BUSY_STATUS__LM_WR0_MASK 0x4
+#define MC_ARB_BUSY_STATUS__LM_WR0__SHIFT 0x2
+#define MC_ARB_BUSY_STATUS__LM_WR1_MASK 0x8
+#define MC_ARB_BUSY_STATUS__LM_WR1__SHIFT 0x3
+#define MC_ARB_BUSY_STATUS__HM_RD0_MASK 0x10
+#define MC_ARB_BUSY_STATUS__HM_RD0__SHIFT 0x4
+#define MC_ARB_BUSY_STATUS__HM_RD1_MASK 0x20
+#define MC_ARB_BUSY_STATUS__HM_RD1__SHIFT 0x5
+#define MC_ARB_BUSY_STATUS__HM_WR0_MASK 0x40
+#define MC_ARB_BUSY_STATUS__HM_WR0__SHIFT 0x6
+#define MC_ARB_BUSY_STATUS__HM_WR1_MASK 0x80
+#define MC_ARB_BUSY_STATUS__HM_WR1__SHIFT 0x7
+#define MC_ARB_BUSY_STATUS__WDE_RD0_MASK 0x100
+#define MC_ARB_BUSY_STATUS__WDE_RD0__SHIFT 0x8
+#define MC_ARB_BUSY_STATUS__WDE_RD1_MASK 0x200
+#define MC_ARB_BUSY_STATUS__WDE_RD1__SHIFT 0x9
+#define MC_ARB_BUSY_STATUS__WDE_WR0_MASK 0x400
+#define MC_ARB_BUSY_STATUS__WDE_WR0__SHIFT 0xa
+#define MC_ARB_BUSY_STATUS__WDE_WR1_MASK 0x800
+#define MC_ARB_BUSY_STATUS__WDE_WR1__SHIFT 0xb
+#define MC_ARB_BUSY_STATUS__POP0_MASK 0x1000
+#define MC_ARB_BUSY_STATUS__POP0__SHIFT 0xc
+#define MC_ARB_BUSY_STATUS__POP1_MASK 0x2000
+#define MC_ARB_BUSY_STATUS__POP1__SHIFT 0xd
+#define MC_ARB_BUSY_STATUS__TAGFIFO0_MASK 0x4000
+#define MC_ARB_BUSY_STATUS__TAGFIFO0__SHIFT 0xe
+#define MC_ARB_BUSY_STATUS__TAGFIFO1_MASK 0x8000
+#define MC_ARB_BUSY_STATUS__TAGFIFO1__SHIFT 0xf
+#define MC_ARB_BUSY_STATUS__REPLAY0_MASK 0x10000
+#define MC_ARB_BUSY_STATUS__REPLAY0__SHIFT 0x10
+#define MC_ARB_BUSY_STATUS__REPLAY1_MASK 0x20000
+#define MC_ARB_BUSY_STATUS__REPLAY1__SHIFT 0x11
+#define MC_ARB_BUSY_STATUS__RDRET0_MASK 0x40000
+#define MC_ARB_BUSY_STATUS__RDRET0__SHIFT 0x12
+#define MC_ARB_BUSY_STATUS__RDRET1_MASK 0x80000
+#define MC_ARB_BUSY_STATUS__RDRET1__SHIFT 0x13
+#define MC_ARB_BUSY_STATUS__GECC2_RD0_MASK 0x100000
+#define MC_ARB_BUSY_STATUS__GECC2_RD0__SHIFT 0x14
+#define MC_ARB_BUSY_STATUS__GECC2_RD1_MASK 0x200000
+#define MC_ARB_BUSY_STATUS__GECC2_RD1__SHIFT 0x15
+#define MC_ARB_BUSY_STATUS__GECC2_WR0_MASK 0x400000
+#define MC_ARB_BUSY_STATUS__GECC2_WR0__SHIFT 0x16
+#define MC_ARB_BUSY_STATUS__GECC2_WR1_MASK 0x800000
+#define MC_ARB_BUSY_STATUS__GECC2_WR1__SHIFT 0x17
+#define MC_ARB_BUSY_STATUS__WCDR0_MASK 0x1000000
+#define MC_ARB_BUSY_STATUS__WCDR0__SHIFT 0x18
+#define MC_ARB_BUSY_STATUS__WCDR1_MASK 0x2000000
+#define MC_ARB_BUSY_STATUS__WCDR1__SHIFT 0x19
+#define MC_ARB_BUSY_STATUS__RTT0_MASK 0x4000000
+#define MC_ARB_BUSY_STATUS__RTT0__SHIFT 0x1a
+#define MC_ARB_BUSY_STATUS__RTT1_MASK 0x8000000
+#define MC_ARB_BUSY_STATUS__RTT1__SHIFT 0x1b
+#define MC_ARB_BUSY_STATUS__REM_RD0_MASK 0x10000000
+#define MC_ARB_BUSY_STATUS__REM_RD0__SHIFT 0x1c
+#define MC_ARB_BUSY_STATUS__REM_RD1_MASK 0x20000000
+#define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d
+#define MC_ARB_BUSY_STATUS__REM_WR0_MASK 0x40000000
+#define MC_ARB_BUSY_STATUS__REM_WR0__SHIFT 0x1e
+#define MC_ARB_BUSY_STATUS__REM_WR1_MASK 0x80000000
+#define MC_ARB_BUSY_STATUS__REM_WR1__SHIFT 0x1f
+#define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0xff
+#define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x0
+#define MC_ARB_DRAM_TIMING2_1__RP_MASK 0xff00
+#define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x8
+#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0xff0000
+#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x10
+#define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000
+#define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x18
+#define MC_ARB_BURST_TIME__STATE0_MASK 0x1f
+#define MC_ARB_BURST_TIME__STATE0__SHIFT 0x0
+#define MC_ARB_BURST_TIME__STATE1_MASK 0x3e0
+#define MC_ARB_BURST_TIME__STATE1__SHIFT 0x5
+#define MC_ARB_BURST_TIME__STATE2_MASK 0x7c00
+#define MC_ARB_BURST_TIME__STATE2__SHIFT 0xa
+#define MC_ARB_BURST_TIME__STATE3_MASK 0xf8000
+#define MC_ARB_BURST_TIME__STATE3__SHIFT 0xf
+#define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x1
+#define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x0
+#define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x2
+#define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x1
+#define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x4
+#define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x2
+#define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x8
+#define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x3
+#define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x10
+#define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x4
+#define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0xf00
+#define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x8
+#define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x1000
+#define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0xc
+#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL_MASK 0x6000
+#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL__SHIFT 0xd
+#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL_MASK 0x18000
+#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL__SHIFT 0xf
+#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL_MASK 0x60000
+#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL__SHIFT 0x11
+#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL_MASK 0x180000
+#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL__SHIFT 0x13
+#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL_MASK 0x600000
+#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL__SHIFT 0x15
+#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL_MASK 0x1800000
+#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL__SHIFT 0x17
+#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE_MASK 0x2000000
+#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE__SHIFT 0x19
+#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE_MASK 0x4000000
+#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE__SHIFT 0x1a
+#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE_MASK 0x8000000
+#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE__SHIFT 0x1b
+#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE_MASK 0x10000000
+#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE__SHIFT 0x1c
+#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE_MASK 0x60000000
+#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d
+#define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x1e
+#define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x1
+#define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x1
+#define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
+#define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x2
+#define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
+#define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x4
+#define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
+#define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
+#define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
+#define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x30
+#define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x4
+#define MC_CG_CONFIG__INDEX_MASK 0x3fffc0
+#define MC_CG_CONFIG__INDEX__SHIFT 0x6
+#define MC_CITF_CNTL__IGNOREPM_MASK 0x4
+#define MC_CITF_CNTL__IGNOREPM__SHIFT 0x2
+#define MC_CITF_CNTL__EXEMPTPM_MASK 0x8
+#define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x3
+#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x30
+#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x4
+#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x40
+#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x6
+#define MC_CITF_CNTL__CNTR_CHMAP_MODE_MASK 0x180
+#define MC_CITF_CNTL__CNTR_CHMAP_MODE__SHIFT 0x7
+#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE_MASK 0x200
+#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE__SHIFT 0x9
+#define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x3f
+#define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x0
+#define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0xfc0
+#define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x6
+#define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0xff
+#define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x0
+#define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0xff00
+#define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x8
+#define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0xff0000
+#define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x10
+#define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x1000000
+#define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x18
+#define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x2000000
+#define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x19
+#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0xff
+#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x0
+#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0xff00
+#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x8
+#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI_MASK 0xff0000
+#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI__SHIFT 0x10
+#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x1000000
+#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x18
+#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x2000000
+#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x19
+#define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x1
+#define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x0
+#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x1e
+#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x1
+#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x20
+#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x5
+#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x3c0
+#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x6
+#define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x3f
+#define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x0
+#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x3f000
+#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0xc
+#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0xfc0000
+#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x12
+#define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000
+#define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x18
+#define MC_CITF_RET_MODE__INORDER_RD_MASK 0x1
+#define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x0
+#define MC_CITF_RET_MODE__INORDER_WR_MASK 0x2
+#define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x1
+#define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x4
+#define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x2
+#define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x8
+#define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x3
+#define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x10
+#define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x4
+#define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x20
+#define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x5
+#define MC_CITF_RET_MODE__RDRET_STALL_EN_MASK 0x40
+#define MC_CITF_RET_MODE__RDRET_STALL_EN__SHIFT 0x6
+#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD_MASK 0x7f80
+#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD__SHIFT 0x7
+#define MC_CITF_DAGB_DLY__DLY_MASK 0x1f
+#define MC_CITF_DAGB_DLY__DLY__SHIFT 0x0
+#define MC_CITF_DAGB_DLY__CLI_MASK 0x3f0000
+#define MC_CITF_DAGB_DLY__CLI__SHIFT 0x10
+#define MC_CITF_DAGB_DLY__POS_MASK 0x1f000000
+#define MC_CITF_DAGB_DLY__POS__SHIFT 0x18
+#define MC_RD_GRP_EXT__DBSTEN0_MASK 0xf
+#define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x0
+#define MC_RD_GRP_EXT__TC0_MASK 0xf0
+#define MC_RD_GRP_EXT__TC0__SHIFT 0x4
+#define MC_WR_GRP_EXT__DBSTEN0_MASK 0xf
+#define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x0
+#define MC_WR_GRP_EXT__TC0_MASK 0xf0
+#define MC_WR_GRP_EXT__TC0__SHIFT 0x4
+#define MC_CITF_REMREQ__READ_CREDITS_MASK 0x7f
+#define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x0
+#define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x3f80
+#define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x7
+#define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x4000
+#define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0xe
+#define MC_WR_TC0__ENABLE_MASK 0x1
+#define MC_WR_TC0__ENABLE__SHIFT 0x0
+#define MC_WR_TC0__PRESCALE_MASK 0x6
+#define MC_WR_TC0__PRESCALE__SHIFT 0x1
+#define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_WR_TC0__STALL_MODE_MASK 0x30
+#define MC_WR_TC0__STALL_MODE__SHIFT 0x4
+#define MC_WR_TC0__STALL_OVERRIDE_MASK 0x40
+#define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_WR_TC0__MAX_BURST_MASK 0x780
+#define MC_WR_TC0__MAX_BURST__SHIFT 0x7
+#define MC_WR_TC0__LAZY_TIMER_MASK 0x7800
+#define MC_WR_TC0__LAZY_TIMER__SHIFT 0xb
+#define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_WR_TC1__ENABLE_MASK 0x1
+#define MC_WR_TC1__ENABLE__SHIFT 0x0
+#define MC_WR_TC1__PRESCALE_MASK 0x6
+#define MC_WR_TC1__PRESCALE__SHIFT 0x1
+#define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_WR_TC1__STALL_MODE_MASK 0x30
+#define MC_WR_TC1__STALL_MODE__SHIFT 0x4
+#define MC_WR_TC1__STALL_OVERRIDE_MASK 0x40
+#define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_WR_TC1__MAX_BURST_MASK 0x780
+#define MC_WR_TC1__MAX_BURST__SHIFT 0x7
+#define MC_WR_TC1__LAZY_TIMER_MASK 0x7800
+#define MC_WR_TC1__LAZY_TIMER__SHIFT 0xb
+#define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x3f
+#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x0
+#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0xfc0
+#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x6
+#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x7
+#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x0
+#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x38
+#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x3
+#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x1c0
+#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x6
+#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0xe00
+#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x9
+#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x7000
+#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0xc
+#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x38000
+#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0xf
+#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
+#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x12
+#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0xe00000
+#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x15
+#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x1000000
+#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x18
+#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL_MASK 0x2000000
+#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL__SHIFT 0x19
+#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x7
+#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x0
+#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x38
+#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x3
+#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x1c0
+#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x6
+#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0xe00
+#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x9
+#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x7000
+#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0xc
+#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x38000
+#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0xf
+#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
+#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x12
+#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0xe00000
+#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x15
+#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x1000000
+#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x18
+#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL_MASK 0x2000000
+#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL__SHIFT 0x19
+#define MC_RD_CB__ENABLE_MASK 0x1
+#define MC_RD_CB__ENABLE__SHIFT 0x0
+#define MC_RD_CB__PRESCALE_MASK 0x6
+#define MC_RD_CB__PRESCALE__SHIFT 0x1
+#define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_RD_CB__STALL_MODE_MASK 0x30
+#define MC_RD_CB__STALL_MODE__SHIFT 0x4
+#define MC_RD_CB__STALL_OVERRIDE_MASK 0x40
+#define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_RD_CB__MAX_BURST_MASK 0x780
+#define MC_RD_CB__MAX_BURST__SHIFT 0x7
+#define MC_RD_CB__LAZY_TIMER_MASK 0x7800
+#define MC_RD_CB__LAZY_TIMER__SHIFT 0xb
+#define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_RD_DB__ENABLE_MASK 0x1
+#define MC_RD_DB__ENABLE__SHIFT 0x0
+#define MC_RD_DB__PRESCALE_MASK 0x6
+#define MC_RD_DB__PRESCALE__SHIFT 0x1
+#define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_RD_DB__STALL_MODE_MASK 0x30
+#define MC_RD_DB__STALL_MODE__SHIFT 0x4
+#define MC_RD_DB__STALL_OVERRIDE_MASK 0x40
+#define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_RD_DB__MAX_BURST_MASK 0x780
+#define MC_RD_DB__MAX_BURST__SHIFT 0x7
+#define MC_RD_DB__LAZY_TIMER_MASK 0x7800
+#define MC_RD_DB__LAZY_TIMER__SHIFT 0xb
+#define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_RD_TC0__ENABLE_MASK 0x1
+#define MC_RD_TC0__ENABLE__SHIFT 0x0
+#define MC_RD_TC0__PRESCALE_MASK 0x6
+#define MC_RD_TC0__PRESCALE__SHIFT 0x1
+#define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_RD_TC0__STALL_MODE_MASK 0x30
+#define MC_RD_TC0__STALL_MODE__SHIFT 0x4
+#define MC_RD_TC0__STALL_OVERRIDE_MASK 0x40
+#define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_RD_TC0__MAX_BURST_MASK 0x780
+#define MC_RD_TC0__MAX_BURST__SHIFT 0x7
+#define MC_RD_TC0__LAZY_TIMER_MASK 0x7800
+#define MC_RD_TC0__LAZY_TIMER__SHIFT 0xb
+#define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_RD_TC1__ENABLE_MASK 0x1
+#define MC_RD_TC1__ENABLE__SHIFT 0x0
+#define MC_RD_TC1__PRESCALE_MASK 0x6
+#define MC_RD_TC1__PRESCALE__SHIFT 0x1
+#define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_RD_TC1__STALL_MODE_MASK 0x30
+#define MC_RD_TC1__STALL_MODE__SHIFT 0x4
+#define MC_RD_TC1__STALL_OVERRIDE_MASK 0x40
+#define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_RD_TC1__MAX_BURST_MASK 0x780
+#define MC_RD_TC1__MAX_BURST__SHIFT 0x7
+#define MC_RD_TC1__LAZY_TIMER_MASK 0x7800
+#define MC_RD_TC1__LAZY_TIMER__SHIFT 0xb
+#define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_RD_HUB__ENABLE_MASK 0x1
+#define MC_RD_HUB__ENABLE__SHIFT 0x0
+#define MC_RD_HUB__PRESCALE_MASK 0x6
+#define MC_RD_HUB__PRESCALE__SHIFT 0x1
+#define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_RD_HUB__STALL_MODE_MASK 0x30
+#define MC_RD_HUB__STALL_MODE__SHIFT 0x4
+#define MC_RD_HUB__STALL_OVERRIDE_MASK 0x40
+#define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_RD_HUB__MAX_BURST_MASK 0x780
+#define MC_RD_HUB__MAX_BURST__SHIFT 0x7
+#define MC_RD_HUB__LAZY_TIMER_MASK 0x7800
+#define MC_RD_HUB__LAZY_TIMER__SHIFT 0xb
+#define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_WR_CB__ENABLE_MASK 0x1
+#define MC_WR_CB__ENABLE__SHIFT 0x0
+#define MC_WR_CB__PRESCALE_MASK 0x6
+#define MC_WR_CB__PRESCALE__SHIFT 0x1
+#define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_WR_CB__STALL_MODE_MASK 0x30
+#define MC_WR_CB__STALL_MODE__SHIFT 0x4
+#define MC_WR_CB__STALL_OVERRIDE_MASK 0x40
+#define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_WR_CB__MAX_BURST_MASK 0x780
+#define MC_WR_CB__MAX_BURST__SHIFT 0x7
+#define MC_WR_CB__LAZY_TIMER_MASK 0x7800
+#define MC_WR_CB__LAZY_TIMER__SHIFT 0xb
+#define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_WR_DB__ENABLE_MASK 0x1
+#define MC_WR_DB__ENABLE__SHIFT 0x0
+#define MC_WR_DB__PRESCALE_MASK 0x6
+#define MC_WR_DB__PRESCALE__SHIFT 0x1
+#define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_WR_DB__STALL_MODE_MASK 0x30
+#define MC_WR_DB__STALL_MODE__SHIFT 0x4
+#define MC_WR_DB__STALL_OVERRIDE_MASK 0x40
+#define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_WR_DB__MAX_BURST_MASK 0x780
+#define MC_WR_DB__MAX_BURST__SHIFT 0x7
+#define MC_WR_DB__LAZY_TIMER_MASK 0x7800
+#define MC_WR_DB__LAZY_TIMER__SHIFT 0xb
+#define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_WR_HUB__ENABLE_MASK 0x1
+#define MC_WR_HUB__ENABLE__SHIFT 0x0
+#define MC_WR_HUB__PRESCALE_MASK 0x6
+#define MC_WR_HUB__PRESCALE__SHIFT 0x1
+#define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_WR_HUB__STALL_MODE_MASK 0x30
+#define MC_WR_HUB__STALL_MODE__SHIFT 0x4
+#define MC_WR_HUB__STALL_OVERRIDE_MASK 0x40
+#define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_WR_HUB__MAX_BURST_MASK 0x780
+#define MC_WR_HUB__MAX_BURST__SHIFT 0x7
+#define MC_WR_HUB__LAZY_TIMER_MASK 0x7800
+#define MC_WR_HUB__LAZY_TIMER__SHIFT 0xb
+#define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0xff
+#define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x0
+#define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0xff00
+#define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x8
+#define MC_RD_GRP_LCL__CB0_MASK 0xf000
+#define MC_RD_GRP_LCL__CB0__SHIFT 0xc
+#define MC_RD_GRP_LCL__CBCMASK0_MASK 0xf0000
+#define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x10
+#define MC_RD_GRP_LCL__CBFMASK0_MASK 0xf00000
+#define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x14
+#define MC_RD_GRP_LCL__DB0_MASK 0xf000000
+#define MC_RD_GRP_LCL__DB0__SHIFT 0x18
+#define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000
+#define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x1c
+#define MC_WR_GRP_LCL__CB0_MASK 0xf
+#define MC_WR_GRP_LCL__CB0__SHIFT 0x0
+#define MC_WR_GRP_LCL__CBCMASK0_MASK 0xf0
+#define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x4
+#define MC_WR_GRP_LCL__CBFMASK0_MASK 0xf00
+#define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x8
+#define MC_WR_GRP_LCL__DB0_MASK 0xf000
+#define MC_WR_GRP_LCL__DB0__SHIFT 0xc
+#define MC_WR_GRP_LCL__DBHTILE0_MASK 0xf0000
+#define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x10
+#define MC_WR_GRP_LCL__SX0_MASK 0xf00000
+#define MC_WR_GRP_LCL__SX0__SHIFT 0x14
+#define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000
+#define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x1c
+#define MC_CITF_PERF_MON_CNTL2__CID_MASK 0xff
+#define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x0
+#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x40
+#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x6
+#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x80
+#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x7
+#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x100
+#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x8
+#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x200
+#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x9
+#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x400
+#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0xa
+#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x800
+#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0xb
+#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x1000
+#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0xc
+#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x2000
+#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0xd
+#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x4000
+#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0xe
+#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x8000
+#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0xf
+#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x10000
+#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0x10
+#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x20000
+#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0x11
+#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x40000
+#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0x12
+#define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x3f
+#define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x0
+#define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0xfc0
+#define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x6
+#define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x3f000
+#define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0xc
+#define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x40000
+#define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x12
+#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x3f
+#define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x0
+#define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0xfc0
+#define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x6
+#define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x3f000
+#define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0xc
+#define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x40000
+#define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x12
+#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x3f
+#define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x0
+#define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0xfc0
+#define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x6
+#define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x3f000
+#define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0xc
+#define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x40000
+#define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x12
+#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x4
+#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x2
+#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x18
+#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x3
+#define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x3f
+#define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x0
+#define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0xfc0
+#define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x6
+#define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x3f000
+#define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0xc
+#define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x40000
+#define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x12
+#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x3f
+#define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x0
+#define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0xfc0
+#define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x6
+#define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x3f000
+#define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0xc
+#define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x40000
+#define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x12
+#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x3f
+#define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x0
+#define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0xfc0
+#define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x6
+#define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x3f000
+#define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0xc
+#define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x40000
+#define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x12
+#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x1
+#define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x0
+#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x2
+#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x1
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x4
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x2
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x8
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x3
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x10
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x4
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x20
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x5
+#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x40
+#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x6
+#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x80
+#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0x7
+#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x100
+#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0x8
+#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x200
+#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0x9
+#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x400
+#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0xa
+#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x800
+#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0xb
+#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x1000
+#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0xc
+#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x2000
+#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0xd
+#define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x3
+#define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x0
+#define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffff
+#define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x0
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x2
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x1
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x4
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x2
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x8
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x3
+#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
+#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
+#define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x1fe0
+#define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x5
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x2000
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0xd
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x4000
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0xe
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x8000
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0xf
+#define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x10000
+#define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x10
+#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x20000
+#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x11
+#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x40000
+#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x12
+#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x80000
+#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x13
+#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x100000
+#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x14
+#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN_MASK 0x200000
+#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN__SHIFT 0x15
+#define MC_HUB_WDP_CNTL__WRITE_PRI_EN_MASK 0x400000
+#define MC_HUB_WDP_CNTL__WRITE_PRI_EN__SHIFT 0x16
+#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x1
+#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x0
+#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x2
+#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x1
+#define MC_HUB_WDP_BP__ENABLE_MASK 0x1
+#define MC_HUB_WDP_BP__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_BP__RDRET_MASK 0x3fffe
+#define MC_HUB_WDP_BP__RDRET__SHIFT 0x1
+#define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000
+#define MC_HUB_WDP_BP__WRREQ__SHIFT 0x12
+#define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x1
+#define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x0
+#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x2
+#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
+#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x4
+#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
+#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x8
+#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
+#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x10
+#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
+#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL_MASK 0x20
+#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL__SHIFT 0x5
+#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL_MASK 0x40
+#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL__SHIFT 0x6
+#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL_MASK 0x80
+#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL__SHIFT 0x7
+#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL_MASK 0x100
+#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL__SHIFT 0x8
+#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK 0x200
+#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT 0x9
+#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK 0x400
+#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT 0xa
+#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK 0x800
+#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT 0xb
+#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK 0x1000
+#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT 0xc
+#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL_MASK 0x2000
+#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL__SHIFT 0xd
+#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL_MASK 0x4000
+#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL__SHIFT 0xe
+#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL_MASK 0x8000
+#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL__SHIFT 0xf
+#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL_MASK 0x10000
+#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL__SHIFT 0x10
+#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x20000
+#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x11
+#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x40000
+#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x12
+#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80000
+#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x13
+#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x100000
+#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x14
+#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x200000
+#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x15
+#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400000
+#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x16
+#define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x1
+#define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x0
+#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x2
+#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
+#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x4
+#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
+#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x8
+#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
+#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x10
+#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
+#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL_MASK 0x20
+#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL__SHIFT 0x5
+#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL_MASK 0x40
+#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL__SHIFT 0x6
+#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL_MASK 0x80
+#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL__SHIFT 0x7
+#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL_MASK 0x100
+#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL__SHIFT 0x8
+#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x200
+#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x9
+#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x400
+#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0xa
+#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x800
+#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0xb
+#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x1000
+#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0xc
+#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x2000
+#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0xd
+#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x4000
+#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xe
+#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x8000
+#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0xf
+#define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x1
+#define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x0
+#define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x2
+#define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x1
+#define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x4
+#define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x2
+#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x8
+#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x3
+#define MC_HUB_WRRET_STATUS__MCDS_AVAIL_MASK 0x10
+#define MC_HUB_WRRET_STATUS__MCDS_AVAIL__SHIFT 0x4
+#define MC_HUB_WRRET_STATUS__MCDT_AVAIL_MASK 0x20
+#define MC_HUB_WRRET_STATUS__MCDT_AVAIL__SHIFT 0x5
+#define MC_HUB_WRRET_STATUS__MCDU_AVAIL_MASK 0x40
+#define MC_HUB_WRRET_STATUS__MCDU_AVAIL__SHIFT 0x6
+#define MC_HUB_WRRET_STATUS__MCDV_AVAIL_MASK 0x80
+#define MC_HUB_WRRET_STATUS__MCDV_AVAIL__SHIFT 0x7
+#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x1
+#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x0
+#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x4
+#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x2
+#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x8
+#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x3
+#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
+#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
+#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x20
+#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x5
+#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x40
+#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x6
+#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x80
+#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x7
+#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x100
+#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x8
+#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE_MASK 0x200
+#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE__SHIFT 0x9
+#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE_MASK 0x400
+#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE__SHIFT 0xa
+#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE_MASK 0x800
+#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE__SHIFT 0xb
+#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE_MASK 0x1000
+#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE__SHIFT 0xc
+#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x2000
+#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0xd
+#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x1fc000
+#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0xe
+#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x200000
+#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x15
+#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x400000
+#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x16
+#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x800000
+#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x17
+#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE_MASK 0x1000000
+#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE__SHIFT 0x18
+#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE_MASK 0x2000000
+#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE__SHIFT 0x19
+#define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x1
+#define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x0
+#define MC_HUB_WRRET_CNTL__BP_MASK 0x1ffffe
+#define MC_HUB_WRRET_CNTL__BP__SHIFT 0x1
+#define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x200000
+#define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x15
+#define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000
+#define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x16
+#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000
+#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x1e
+#define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000
+#define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x1f
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
+#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
+#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
+#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
+#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
+#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
+#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
+#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
+#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
+#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
+#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
+#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
+#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
+#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
+#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
+#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
+#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
+#define MC_HUB_WDP_CREDITS__VM0_MASK 0xff
+#define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS__VM1_MASK 0xff00
+#define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x8
+#define MC_HUB_WDP_CREDITS__STOR0_MASK 0xff0000
+#define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x10
+#define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000
+#define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x18
+#define MC_HUB_WDP_CREDITS2__STOR0_PRI_MASK 0xff
+#define MC_HUB_WDP_CREDITS2__STOR0_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS2__STOR1_PRI_MASK 0xff00
+#define MC_HUB_WDP_CREDITS2__STOR1_PRI__SHIFT 0x8
+#define MC_HUB_WDP_GBL0__MAXBURST_MASK 0xf
+#define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x0
+#define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0xf0
+#define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x4
+#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0xff00
+#define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x8
+#define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x10000
+#define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x10
+#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI_MASK 0x1fe0000
+#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x11
+#define MC_HUB_WDP_GBL1__MAXBURST_MASK 0xf
+#define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x0
+#define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0xf0
+#define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x4
+#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0xff00
+#define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x8
+#define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x10000
+#define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x10
+#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI_MASK 0x1fe0000
+#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x11
+#define MC_HUB_RDREQ_CREDITS__VM0_MASK 0xff
+#define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x0
+#define MC_HUB_RDREQ_CREDITS__VM1_MASK 0xff00
+#define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x8
+#define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0xff0000
+#define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x10
+#define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000
+#define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x18
+#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI_MASK 0xff
+#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI__SHIFT 0x0
+#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0xff00
+#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x8
+#define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x3f
+#define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x0
+#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x3f0000
+#define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x10
+#define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000
+#define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x18
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x1
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x0
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x2
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x1
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x4
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x2
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x8
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x3
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ_MASK 0x10
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ__SHIFT 0x4
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE_MASK 0x20
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE__SHIFT 0x5
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ_MASK 0x40
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ__SHIFT 0x6
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE_MASK 0x80
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE__SHIFT 0x7
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x100
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x8
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x200
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x9
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x400
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0xa
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x800
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0xb
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x1000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0xc
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x2000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0xd
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x4000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0xe
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x8000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0xf
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x10000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x10
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x20000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x11
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x40000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x12
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x80000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x13
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_READ_MASK 0x100000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_READ__SHIFT 0x14
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_WRITE_MASK 0x200000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_WRITE__SHIFT 0x15
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x400000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x16
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x800000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x17
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ_MASK 0x1000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ__SHIFT 0x18
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE_MASK 0x2000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE__SHIFT 0x19
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ_MASK 0x4000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ__SHIFT 0x1a
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE_MASK 0x8000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE__SHIFT 0x1b
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ_MASK 0x10000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ__SHIFT 0x1c
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE_MASK 0x20000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT 0x1d
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ_MASK 0x40000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ__SHIFT 0x1e
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE_MASK 0x80000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE__SHIFT 0x1f
+#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x3
+#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x7c
+#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x2
+#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE_MASK 0x3
+#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT_MASK 0x7c
+#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT__SHIFT 0x2
+#define MC_HUB_WDP_BYPASS_GBL0__ENABLE_MASK 0x1
+#define MC_HUB_WDP_BYPASS_GBL0__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_BYPASS_GBL0__CID1_MASK 0x1fe
+#define MC_HUB_WDP_BYPASS_GBL0__CID1__SHIFT 0x1
+#define MC_HUB_WDP_BYPASS_GBL0__CID2_MASK 0x1fe00
+#define MC_HUB_WDP_BYPASS_GBL0__CID2__SHIFT 0x9
+#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME_MASK 0xfe0000
+#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME__SHIFT 0x11
+#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME_MASK 0x7f000000
+#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME__SHIFT 0x18
+#define MC_HUB_WDP_BYPASS_GBL1__ENABLE_MASK 0x1
+#define MC_HUB_WDP_BYPASS_GBL1__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_BYPASS_GBL1__CID1_MASK 0x1fe
+#define MC_HUB_WDP_BYPASS_GBL1__CID1__SHIFT 0x1
+#define MC_HUB_WDP_BYPASS_GBL1__CID2_MASK 0x1fe00
+#define MC_HUB_WDP_BYPASS_GBL1__CID2__SHIFT 0x9
+#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME_MASK 0xfe0000
+#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME__SHIFT 0x11
+#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME_MASK 0x7f000000
+#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME__SHIFT 0x18
+#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_BYPASS_GBL0__CID1_MASK 0x1fe
+#define MC_HUB_RDREQ_BYPASS_GBL0__CID1__SHIFT 0x1
+#define MC_HUB_RDREQ_BYPASS_GBL0__CID2_MASK 0x1fe00
+#define MC_HUB_RDREQ_BYPASS_GBL0__CID2__SHIFT 0x9
+#define MC_HUB_WDP_SH2__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SH2__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SH2__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SH2__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SH2__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SH2__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SH2__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SH2__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SH2__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SH2__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SH2__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SH2__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_SH3__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SH3__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SH3__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SH3__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SH3__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SH3__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SH3__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SH3__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SH3__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SH3__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SH3__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SH3__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_IA0__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_IA0__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_IA0__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_IA0__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_IA0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_IA0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_IA0__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_IA0__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_IA0__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_IA0__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_IA0__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_IA0__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_IA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_IA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_IA1__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_IA1__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_IA1__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_IA1__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_IA1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_IA1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_IA1__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_IA1__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_IA1__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_IA1__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_IA1__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_IA1__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_IA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_IA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDW__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD__SHIFT 0x19
+#define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDX__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD__SHIFT 0x19
+#define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDY__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD__SHIFT 0x19
+#define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD__SHIFT 0x19
+#define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x7f
+#define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x0
+#define MC_HUB_RDREQ_SIP__DUMMY_MASK 0x80
+#define MC_HUB_RDREQ_SIP__DUMMY__SHIFT 0x7
+#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x7f00
+#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x8
+#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0xff
+#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x0
+#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI_MASK 0xff00
+#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x8
+#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0xff
+#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x0
+#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI_MASK 0xff00
+#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x8
+#define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_CPG__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_CPG__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_CPG__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_CPG__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_CPG__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_CPG__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_CPG__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_CPG__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_CPG__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_CPG__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_CPG__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_CPG__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_CPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_CPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_SDMA0__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_SDMA0__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_SDMA0__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_SDMA0__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_SDMA0__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_SDMA0__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_SDMA0__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_SDMA0__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_SDMA1__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_SDMA1__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_SDMA1__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_SDMA1__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_SDMA1__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_SDMA1__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_SDMA1__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_SDMA1__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_VCE__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_VCE__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_VCE__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_VCE__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_VCE__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_VCE__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_VCE__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_VCE__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_VCE__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_VCE__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_VCE__VM_BYPASS_MASK 0x10000
+#define MC_HUB_RDREQ_VCE__VM_BYPASS__SHIFT 0x10
+#define MC_HUB_RDREQ_VCE__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_RDREQ_VCE__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_UMC__VM_BYPASS_MASK 0x10000
+#define MC_HUB_RDREQ_UMC__VM_BYPASS__SHIFT 0x10
+#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x10000
+#define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x10
+#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_RDREQ_IA__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_IA__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_IA__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_IA__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_IA__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_IA__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_IA__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_IA__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_IA__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_IA__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_IA__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_IA__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_IA__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_IA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_IA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_VCEU__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_VCEU__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_VCEU__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_VCEU__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_VCEU__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_VCEU__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_VCEU__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_VCEU__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_VCEU__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_VCEU__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_VCEU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_VCEU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_MCDW__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_MCDX__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_MCDY__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x3
+#define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x1fc
+#define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x2
+#define MC_HUB_WDP_CPG__ENABLE_MASK 0x1
+#define MC_HUB_WDP_CPG__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_CPG__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_CPG__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_CPG__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_CPG__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_CPG__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_CPG__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_CPG__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_CPG__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_CPG__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_CPG__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_CPG__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_CPG__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_CPG__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_CPG__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_CPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_CPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_SDMA1__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SDMA1__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SDMA1__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SDMA1__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SDMA1__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SDMA1__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SDMA1__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SDMA1__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SDMA1__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SDMA1__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_SH0__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SH0__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SH0__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_MCIF__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_VCE__ENABLE_MASK 0x1
+#define MC_HUB_WDP_VCE__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_VCE__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_VCE__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_VCE__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_VCE__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_VCE__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_VCE__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_VCE__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_VCE__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_VCE__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_VCE__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_VCE__VM_BYPASS_MASK 0x10000
+#define MC_HUB_WDP_VCE__VM_BYPASS__SHIFT 0x10
+#define MC_HUB_WDP_VCE__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_VCE__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_XDP__ENABLE_MASK 0x1
+#define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_XDP__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_XDP__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_IH__ENABLE_MASK 0x1
+#define MC_HUB_WDP_IH__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_IH__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_IH__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_IH__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_RLC__ENABLE_MASK 0x1
+#define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_RLC__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_RLC__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_SEM__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SEM__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SEM__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_SMU__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SMU__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SMU__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_SH1__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SH1__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SH1__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_UMC__ENABLE_MASK 0x1
+#define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_UMC__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_UMC__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_UVD__ENABLE_MASK 0x1
+#define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_UVD__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_UVD__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x10000
+#define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x10
+#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_HDP__ENABLE_MASK 0x1
+#define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_HDP__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_HDP__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_SDMA0__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SDMA0__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SDMA0__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SDMA0__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SDMA0__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SDMA0__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SDMA0__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SDMA0__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SDMA0__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SDMA0__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WDP_VCEU__ENABLE_MASK 0x1
+#define MC_HUB_WDP_VCEU__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_VCEU__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_VCEU__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_VCEU__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_VCEU__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_VCEU__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_VCEU__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_VCEU__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_VCEU__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_VCEU__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_VCEU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_VCEU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x1
+#define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_XDMA__ENABLE_MASK 0x1
+#define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_ACPG__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_ACPG__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_ACPG__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_ACPG__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_ACPG__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_ACPG__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_ACPG__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_ACPG__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_ACPG__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_ACPG__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_RDREQ_ACPO__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_ACPO__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_ACPO__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_ACPO__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_ACPO__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_ACPO__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_ACPO__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_ACPO__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_ACPO__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_ACPO__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_RDREQ_SAM__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_SAM__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_SAM__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_SAM__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_SAM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_SAM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_SAM__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_SAM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_SAM__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_SAM__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_SAM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_SAM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_SAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_SAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_ACPG__ENABLE_MASK 0x1
+#define MC_HUB_WDP_ACPG__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_ACPG__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_ACPG__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_ACPG__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_ACPG__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_ACPG__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_ACPG__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_ACPG__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_ACPG__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_ACPG__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_WDP_ACPG__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_WDP_ACPG__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_WDP_ACPO__ENABLE_MASK 0x1
+#define MC_HUB_WDP_ACPO__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_ACPO__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_ACPO__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_ACPO__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_ACPO__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_ACPO__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_ACPO__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_ACPO__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_ACPO__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_ACPO__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_WDP_ACPO__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_WDP_ACPO__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_WDP_SAM__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SAM__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SAM__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SAM__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SAM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SAM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SAM__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SAM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SAM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SAM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SAM__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SAM__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SAM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SAM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SAM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SAM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_CPC__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_CPC__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_CPC__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_CPC__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_CPC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_CPC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_CPC__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_CPC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_CPC__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_CPC__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_CPC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_CPC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_CPC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_CPC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_CPF__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_CPF__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_CPF__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_CPF__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_CPF__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_CPF__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_CPF__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_CPF__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_CPF__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_CPF__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_CPF__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_CPF__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_CPF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_CPF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_CPC__ENABLE_MASK 0x1
+#define MC_HUB_WDP_CPC__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_CPC__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_CPC__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_CPC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_CPC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_CPC__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_CPC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_CPC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_CPC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_CPC__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_CPC__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_CPC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_CPC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_CPC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_CPC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_CPC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_CPC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_CPF__ENABLE_MASK 0x1
+#define MC_HUB_WDP_CPF__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_CPF__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_CPF__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_CPF__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_CPF__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_CPF__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_CPF__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_CPF__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_CPF__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_CPF__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_CPF__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_CPF__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_CPF__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_CPF__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_CPF__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_CPF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_CPF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_ISP_SPM__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_ISP_SPM__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_ISP_SPM__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_ISP_SPM__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_ISP_SPM__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_ISP_SPM__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_RDREQ_ISP_MPM__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_ISP_MPM__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_ISP_MPM__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_ISP_MPM__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_ISP_MPM__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_ISP_MPM__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_RDREQ_ISP_CCPU__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_ISP_CCPU__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_WDP_ISP_SPM__ENABLE_MASK 0x1
+#define MC_HUB_WDP_ISP_SPM__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_ISP_SPM__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_ISP_SPM__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_ISP_SPM__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_ISP_SPM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_ISP_SPM__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_ISP_SPM__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_WDP_ISP_MPS__ENABLE_MASK 0x1
+#define MC_HUB_WDP_ISP_MPS__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_ISP_MPS__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_ISP_MPS__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_ISP_MPS__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_ISP_MPS__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_ISP_MPS__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_ISP_MPS__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_WDP_ISP_MPM__ENABLE_MASK 0x1
+#define MC_HUB_WDP_ISP_MPM__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_ISP_MPM__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_ISP_MPM__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_ISP_MPM__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_ISP_MPM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_ISP_MPM__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_ISP_MPM__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_WDP_ISP_CCPU__ENABLE_MASK 0x1
+#define MC_HUB_WDP_ISP_CCPU__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_ISP_CCPU__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_ISP_CCPU__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_ISP_CCPU__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_ISP_CCPU__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_ISP_CCPU__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_ISP_CCPU__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_RDREQ_MCDS__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDS__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDS__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDS__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDS__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDS__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDS__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDS__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDS__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDS__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD__SHIFT 0x19
+#define MC_HUB_RDREQ_MCDT__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDT__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDT__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDT__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDT__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDT__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDT__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDT__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDT__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDT__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD__SHIFT 0x19
+#define MC_HUB_RDREQ_MCDU__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDU__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDU__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDU__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDU__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDU__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDU__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDU__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDU__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDU__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD__SHIFT 0x19
+#define MC_HUB_RDREQ_MCDV__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDV__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDV__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDV__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDV__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDV__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDV__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDV__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDV__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDV__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD__SHIFT 0x19
+#define MC_HUB_WDP_MCDS__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDS__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDS__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDS__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDS__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDS__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDS__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDS__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDS__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDS__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDS__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDS__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDS__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDS__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_MCDT__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDT__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDT__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDT__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDT__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDT__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDT__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDT__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDT__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDT__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDT__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDT__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDT__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDT__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_MCDU__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDU__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDU__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDU__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDU__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDU__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDU__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDU__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDU__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDU__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDU__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDU__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDU__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDU__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_MCDV__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDV__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDV__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDV__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDV__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDV__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDV__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDV__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDV__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDV__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDV__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDV__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDV__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDV__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WRRET_MCDS__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDS__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDS__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDS__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WRRET_MCDT__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDT__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDT__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDT__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WRRET_MCDU__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDU__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDU__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDU__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WRRET_MCDV__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDV__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDV__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDV__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_BP2__RDRET_MASK 0xffff
+#define MC_HUB_WDP_BP2__RDRET__SHIFT 0x0
+#define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x8000
+#define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0xf
+#define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x10000
+#define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x10
+#define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x20000
+#define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x11
+#define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0xff
+#define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x0
+#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0xff00
+#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x8
+#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0xff
+#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x0
+#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0xfff00
+#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x8
+#define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000
+#define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x14
+#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0xff
+#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0
+#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0xff00
+#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8
+#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0xff
+#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x0
+#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0xff00
+#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x8
+#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0xff0000
+#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x10
+#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0xff
+#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x0
+#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0xff00
+#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x8
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
+#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x1
+#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x0
+#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x6
+#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x1
+#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x78
+#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x3
+#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x80
+#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x7
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
+#define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0xff
+#define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x0
+#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x100
+#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x8
+#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x600
+#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x9
+#define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x1800
+#define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xb
+#define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x2000
+#define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd
+#define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0xff
+#define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x0
+#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x300
+#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x8
+#define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0xc00
+#define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xa
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x3
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x4
+#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2
+#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x8
+#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3
+#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x10
+#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4
+#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x1e0
+#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x3e00
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x7c000
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0xf80000
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18
+#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffff
+#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0
+#define MC_RPB_CID_QUEUE_EX__START_MASK 0x1
+#define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x0
+#define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x3e
+#define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1
+#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0xffff
+#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0
+#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000
+#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10
+#define MC_RPB_TCI_CNTL__TCI_ENABLE_MASK 0x1
+#define MC_RPB_TCI_CNTL__TCI_ENABLE__SHIFT 0x0
+#define MC_RPB_TCI_CNTL__TCI_POLICY_MASK 0x6
+#define MC_RPB_TCI_CNTL__TCI_POLICY__SHIFT 0x1
+#define MC_RPB_TCI_CNTL__TCI_VOL_MASK 0x8
+#define MC_RPB_TCI_CNTL__TCI_VOL__SHIFT 0x3
+#define MC_RPB_TCI_CNTL__TCI_VMID_MASK 0xf0
+#define MC_RPB_TCI_CNTL__TCI_VMID__SHIFT 0x4
+#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS_MASK 0xff00
+#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS__SHIFT 0x8
+#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES_MASK 0xff0000
+#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES__SHIFT 0x10
+#define MC_RPB_TCI_CNTL__TCI_MAX_READS_MASK 0xff000000
+#define MC_RPB_TCI_CNTL__TCI_MAX_READS__SHIFT 0x18
+#define MC_SHARED_CHMAP__CHAN0_MASK 0xf
+#define MC_SHARED_CHMAP__CHAN0__SHIFT 0x0
+#define MC_SHARED_CHMAP__CHAN1_MASK 0xf0
+#define MC_SHARED_CHMAP__CHAN1__SHIFT 0x4
+#define MC_SHARED_CHMAP__CHAN2_MASK 0xf00
+#define MC_SHARED_CHMAP__CHAN2__SHIFT 0x8
+#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000
+#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc
+#define MC_SHARED_CHMAP__CHAN3_MASK 0xf0000
+#define MC_SHARED_CHMAP__CHAN3__SHIFT 0x10
+#define MC_SHARED_CHMAP__CHAN4_MASK 0xf00000
+#define MC_SHARED_CHMAP__CHAN4__SHIFT 0x14
+#define MC_SHARED_CHREMAP__CHAN0_MASK 0xf
+#define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x0
+#define MC_SHARED_CHREMAP__CHAN1_MASK 0xf0
+#define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x4
+#define MC_SHARED_CHREMAP__CHAN2_MASK 0xf00
+#define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x8
+#define MC_SHARED_CHREMAP__CHAN3_MASK 0xf000
+#define MC_SHARED_CHREMAP__CHAN3__SHIFT 0xc
+#define MC_SHARED_CHREMAP__CHAN4_MASK 0xf0000
+#define MC_SHARED_CHREMAP__CHAN4__SHIFT 0x10
+#define MC_SHARED_CHREMAP__CHAN5_MASK 0xf00000
+#define MC_SHARED_CHREMAP__CHAN5__SHIFT 0x14
+#define MC_SHARED_CHREMAP__CHAN6_MASK 0xf000000
+#define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x18
+#define MC_SHARED_CHREMAP__CHAN7_MASK 0xf0000000
+#define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x1c
+#define MC_RD_GRP_GFX__CP_MASK 0xf
+#define MC_RD_GRP_GFX__CP__SHIFT 0x0
+#define MC_RD_GRP_GFX__SH_MASK 0xf0
+#define MC_RD_GRP_GFX__SH__SHIFT 0x4
+#define MC_RD_GRP_GFX__IA_MASK 0xf00
+#define MC_RD_GRP_GFX__IA__SHIFT 0x8
+#define MC_RD_GRP_GFX__ACPG_MASK 0xf000
+#define MC_RD_GRP_GFX__ACPG__SHIFT 0xc
+#define MC_RD_GRP_GFX__ACPO_MASK 0xf0000
+#define MC_RD_GRP_GFX__ACPO__SHIFT 0x10
+#define MC_RD_GRP_GFX__ISP_MASK 0xf00000
+#define MC_RD_GRP_GFX__ISP__SHIFT 0x14
+#define MC_RD_GRP_GFX__XDMAM_MASK 0xf000000
+#define MC_RD_GRP_GFX__XDMAM__SHIFT 0x18
+#define MC_WR_GRP_GFX__CP_MASK 0xf
+#define MC_WR_GRP_GFX__CP__SHIFT 0x0
+#define MC_WR_GRP_GFX__SH_MASK 0xf0
+#define MC_WR_GRP_GFX__SH__SHIFT 0x4
+#define MC_WR_GRP_GFX__ACPG_MASK 0xf00
+#define MC_WR_GRP_GFX__ACPG__SHIFT 0x8
+#define MC_WR_GRP_GFX__ACPO_MASK 0xf000
+#define MC_WR_GRP_GFX__ACPO__SHIFT 0xc
+#define MC_WR_GRP_GFX__ISP_MASK 0xf0000
+#define MC_WR_GRP_GFX__ISP__SHIFT 0x10
+#define MC_WR_GRP_GFX__XDMA_MASK 0xf00000
+#define MC_WR_GRP_GFX__XDMA__SHIFT 0x14
+#define MC_WR_GRP_GFX__XDMAM_MASK 0xf000000
+#define MC_WR_GRP_GFX__XDMAM__SHIFT 0x18
+#define MC_RD_GRP_SYS__RLC_MASK 0xf
+#define MC_RD_GRP_SYS__RLC__SHIFT 0x0
+#define MC_RD_GRP_SYS__VMC_MASK 0xf0
+#define MC_RD_GRP_SYS__VMC__SHIFT 0x4
+#define MC_RD_GRP_SYS__SDMA1_MASK 0xf00
+#define MC_RD_GRP_SYS__SDMA1__SHIFT 0x8
+#define MC_RD_GRP_SYS__DMIF_MASK 0xf000
+#define MC_RD_GRP_SYS__DMIF__SHIFT 0xc
+#define MC_RD_GRP_SYS__MCIF_MASK 0xf0000
+#define MC_RD_GRP_SYS__MCIF__SHIFT 0x10
+#define MC_RD_GRP_SYS__SMU_MASK 0xf00000
+#define MC_RD_GRP_SYS__SMU__SHIFT 0x14
+#define MC_RD_GRP_SYS__VCE_MASK 0xf000000
+#define MC_RD_GRP_SYS__VCE__SHIFT 0x18
+#define MC_RD_GRP_SYS__VCEU_MASK 0xf0000000
+#define MC_RD_GRP_SYS__VCEU__SHIFT 0x1c
+#define MC_WR_GRP_SYS__IH_MASK 0xf
+#define MC_WR_GRP_SYS__IH__SHIFT 0x0
+#define MC_WR_GRP_SYS__MCIF_MASK 0xf0
+#define MC_WR_GRP_SYS__MCIF__SHIFT 0x4
+#define MC_WR_GRP_SYS__RLC_MASK 0xf00
+#define MC_WR_GRP_SYS__RLC__SHIFT 0x8
+#define MC_WR_GRP_SYS__SAM_MASK 0xf000
+#define MC_WR_GRP_SYS__SAM__SHIFT 0xc
+#define MC_WR_GRP_SYS__SMU_MASK 0xf0000
+#define MC_WR_GRP_SYS__SMU__SHIFT 0x10
+#define MC_WR_GRP_SYS__SDMA1_MASK 0xf00000
+#define MC_WR_GRP_SYS__SDMA1__SHIFT 0x14
+#define MC_WR_GRP_SYS__VCE_MASK 0xf000000
+#define MC_WR_GRP_SYS__VCE__SHIFT 0x18
+#define MC_WR_GRP_SYS__VCEU_MASK 0xf0000000
+#define MC_WR_GRP_SYS__VCEU__SHIFT 0x1c
+#define MC_RD_GRP_OTH__UVD_EXT0_MASK 0xf
+#define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x0
+#define MC_RD_GRP_OTH__SDMA0_MASK 0xf0
+#define MC_RD_GRP_OTH__SDMA0__SHIFT 0x4
+#define MC_RD_GRP_OTH__HDP_MASK 0xf00
+#define MC_RD_GRP_OTH__HDP__SHIFT 0x8
+#define MC_RD_GRP_OTH__SEM_MASK 0xf000
+#define MC_RD_GRP_OTH__SEM__SHIFT 0xc
+#define MC_RD_GRP_OTH__UMC_MASK 0xf0000
+#define MC_RD_GRP_OTH__UMC__SHIFT 0x10
+#define MC_RD_GRP_OTH__UVD_MASK 0xf00000
+#define MC_RD_GRP_OTH__UVD__SHIFT 0x14
+#define MC_RD_GRP_OTH__UVD_EXT1_MASK 0xf000000
+#define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x18
+#define MC_RD_GRP_OTH__SAM_MASK 0xf0000000
+#define MC_RD_GRP_OTH__SAM__SHIFT 0x1c
+#define MC_WR_GRP_OTH__UVD_EXT0_MASK 0xf
+#define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x0
+#define MC_WR_GRP_OTH__SDMA0_MASK 0xf0
+#define MC_WR_GRP_OTH__SDMA0__SHIFT 0x4
+#define MC_WR_GRP_OTH__HDP_MASK 0xf00
+#define MC_WR_GRP_OTH__HDP__SHIFT 0x8
+#define MC_WR_GRP_OTH__SEM_MASK 0xf000
+#define MC_WR_GRP_OTH__SEM__SHIFT 0xc
+#define MC_WR_GRP_OTH__UMC_MASK 0xf0000
+#define MC_WR_GRP_OTH__UMC__SHIFT 0x10
+#define MC_WR_GRP_OTH__UVD_MASK 0xf00000
+#define MC_WR_GRP_OTH__UVD__SHIFT 0x14
+#define MC_WR_GRP_OTH__XDP_MASK 0xf000000
+#define MC_WR_GRP_OTH__XDP__SHIFT 0x18
+#define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000
+#define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x1c
+#define MC_VM_FB_LOCATION__FB_BASE_MASK 0xffff
+#define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x0
+#define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000
+#define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x10
+#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x3ffff
+#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
+#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x3ffff
+#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
+#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x3ffff
+#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x3
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x0
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0xc
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x2
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x30
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x4
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0xc0
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x6
+#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x100
+#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x8
+#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x200
+#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x9
+#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x1
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x2
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x1
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x18
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x20
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x40
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
+#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x780
+#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
+#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x3ffff
+#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
+#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x3
+#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
+#define MC_SHARED_CHREMAP2__CHAN8_MASK 0xf
+#define MC_SHARED_CHREMAP2__CHAN8__SHIFT 0x0
+#define MC_SHARED_CHREMAP2__CHAN9_MASK 0xf0
+#define MC_SHARED_CHREMAP2__CHAN9__SHIFT 0x4
+#define MC_SHARED_CHREMAP2__CHAN10_MASK 0xf00
+#define MC_SHARED_CHREMAP2__CHAN10__SHIFT 0x8
+#define MC_SHARED_CHREMAP2__CHAN11_MASK 0xf000
+#define MC_SHARED_CHREMAP2__CHAN11__SHIFT 0xc
+#define MC_SHARED_CHREMAP2__CHAN12_MASK 0xf0000
+#define MC_SHARED_CHREMAP2__CHAN12__SHIFT 0x10
+#define MC_SHARED_CHREMAP2__CHAN13_MASK 0xf00000
+#define MC_SHARED_CHREMAP2__CHAN13__SHIFT 0x14
+#define MC_SHARED_CHREMAP2__CHAN14_MASK 0xf000000
+#define MC_SHARED_CHREMAP2__CHAN14__SHIFT 0x18
+#define MC_SHARED_CHREMAP2__CHAN15_MASK 0xf0000000
+#define MC_SHARED_CHREMAP2__CHAN15__SHIFT 0x1c
+#define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
+#define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
+#define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
+#define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
+#define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
+#define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
+#define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
+#define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
+#define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
+#define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
+#define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
+#define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
+#define MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40
+#define MC_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6
+#define MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80
+#define MC_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7
+#define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
+#define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
+#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800
+#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb
+#define MC_CONFIG_MCD__ARB0_WR_ENABLE_MASK 0x1000
+#define MC_CONFIG_MCD__ARB0_WR_ENABLE__SHIFT 0xc
+#define MC_CONFIG_MCD__ARB1_WR_ENABLE_MASK 0x2000
+#define MC_CONFIG_MCD__ARB1_WR_ENABLE__SHIFT 0xd
+#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000
+#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x1f
+#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
+#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
+#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
+#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
+#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
+#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
+#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
+#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
+#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
+#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
+#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
+#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
+#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40
+#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6
+#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80
+#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7
+#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
+#define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
+#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800
+#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb
+#define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000
+#define MC_CG_CONFIG_MCD__INDEX__SHIFT 0xd
+#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x3f
+#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
+#define MC_MEM_POWER_LS__LS_HOLD_MASK 0xfc0
+#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
+#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x7
+#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x0
+#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x1
+#define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x1
+#define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x1
+#define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
+#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
+#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x1
+#define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x1
+#define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x1
+#define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x1
+#define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
+#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
+#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x1
+#define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
+#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
+#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
+#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
+#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
+#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
+#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
+#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
+#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_EXTRA__CMP0_MASK 0xff
+#define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x0
+#define MC_XPB_CLG_EXTRA__MSK0_MASK 0xff00
+#define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x8
+#define MC_XPB_CLG_EXTRA__VLD0_MASK 0x10000
+#define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x10
+#define MC_XPB_CLG_EXTRA__CMP1_MASK 0x1fe0000
+#define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x11
+#define MC_XPB_CLG_EXTRA__VLD1_MASK 0x2000000
+#define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x19
+#define MC_XPB_LB_ADDR__CMP0_MASK 0x3ff
+#define MC_XPB_LB_ADDR__CMP0__SHIFT 0x0
+#define MC_XPB_LB_ADDR__MASK0_MASK 0xffc00
+#define MC_XPB_LB_ADDR__MASK0__SHIFT 0xa
+#define MC_XPB_LB_ADDR__CMP1_MASK 0x3f00000
+#define MC_XPB_LB_ADDR__CMP1__SHIFT 0x14
+#define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000
+#define MC_XPB_LB_ADDR__MASK1__SHIFT 0x1a
+#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x3f
+#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x0
+#define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0xfc0
+#define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x6
+#define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x3f000
+#define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0xc
+#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x3f
+#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x0
+#define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0xfc0
+#define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x6
+#define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x3f000
+#define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0xc
+#define MC_XPB_WCB_STS__PBUF_VLD_MASK 0xffff
+#define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x0
+#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x7f0000
+#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10
+#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000
+#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17
+#define MC_XPB_WCB_CFG__TIMEOUT_MASK 0xffff
+#define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x0
+#define MC_XPB_WCB_CFG__HST_MAX_MASK 0x30000
+#define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x10
+#define MC_XPB_WCB_CFG__SID_MAX_MASK 0xc0000
+#define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x12
+#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0xf
+#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0
+#define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x30
+#define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x40
+#define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6
+#define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x80
+#define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7
+#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x100
+#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8
+#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x200
+#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9
+#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x400
+#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa
+#define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x800
+#define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb
+#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x1000
+#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc
+#define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR0__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR0__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR0__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR1__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR1__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR1__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR2__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR2__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR2__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR3__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR3__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR3__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR4__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR4__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR4__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR5__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR5__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR5__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR6__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR6__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR6__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR7__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR7__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR7__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0xff
+#define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0
+#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0xff
+#define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x0
+#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0xf00
+#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x8
+#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0xf000
+#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0xc
+#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0xff
+#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0
+#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0xfffff00
+#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8
+#define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0xff
+#define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0
+#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0xfffff00
+#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8
+#define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0
+#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
+#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0
+#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
+#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0
+#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
+#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0
+#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
+#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x2
+#define MC_XPB_CLK_GAT__ONDLY_MASK 0x3f
+#define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x0
+#define MC_XPB_CLK_GAT__OFFDLY_MASK 0xfc0
+#define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x6
+#define MC_XPB_CLK_GAT__RDYDLY_MASK 0x3f000
+#define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0xc
+#define MC_XPB_CLK_GAT__ENABLE_MASK 0x40000
+#define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x12
+#define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x80000
+#define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0xff
+#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0
+#define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0xff00
+#define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8
+#define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x7f0000
+#define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10
+#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x800000
+#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17
+#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x1000000
+#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18
+#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x2000000
+#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19
+#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x4000000
+#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a
+#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000
+#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b
+#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000
+#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d
+#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000
+#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e
+#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000
+#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f
+#define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0xff
+#define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0
+#define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x7f00
+#define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8
+#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x8000
+#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf
+#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x10000
+#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10
+#define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x20000
+#define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11
+#define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x40000
+#define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12
+#define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x7f80000
+#define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13
+#define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x1
+#define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0
+#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0xfe
+#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1
+#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x7f00
+#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8
+#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x8000
+#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf
+#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x10000
+#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10
+#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x20000
+#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11
+#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x40000
+#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12
+#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x80000
+#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13
+#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x100000
+#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14
+#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x200000
+#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15
+#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x400000
+#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16
+#define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x800000
+#define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17
+#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000
+#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18
+#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x1
+#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0
+#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x2
+#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1
+#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x4
+#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2
+#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x8
+#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3
+#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x10
+#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4
+#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x20
+#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5
+#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x40
+#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6
+#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x80
+#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7
+#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x100
+#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8
+#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x200
+#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9
+#define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x400
+#define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa
+#define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x800
+#define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb
+#define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x1000
+#define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0xc
+#define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x2000
+#define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd
+#define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x4000
+#define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe
+#define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x8000
+#define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0xf
+#define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x10000
+#define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10
+#define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x20000
+#define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x11
+#define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x40000
+#define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12
+#define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x80000
+#define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13
+#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0xffff
+#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0
+#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x3f
+#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0
+#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0xfc0
+#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6
+#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x3f000
+#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc
+#define MC_XPB_STICKY__BITS_MASK 0xffffffff
+#define MC_XPB_STICKY__BITS__SHIFT 0x0
+#define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffff
+#define MC_XPB_STICKY_W1C__BITS__SHIFT 0x0
+#define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0xff
+#define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0
+#define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0xff00
+#define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8
+#define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0xff0000
+#define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10
+#define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000
+#define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18
+#define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000
+#define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f
+#define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0xff
+#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0
+#define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0xff
+#define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x0
+#define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0xff00
+#define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x8
+#define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x10000
+#define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x10
+#define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x1fe0000
+#define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x11
+#define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x2000000
+#define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x19
+#define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0xe
+#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x1
+#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3__SHIFT 0x0
+#define MC_XBAR_ADDR_DEC__GECC_MASK 0x2
+#define MC_XBAR_ADDR_DEC__GECC__SHIFT 0x1
+#define MC_XBAR_ADDR_DEC__RB_SPLIT_MASK 0x4
+#define MC_XBAR_ADDR_DEC__RB_SPLIT__SHIFT 0x2
+#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI_MASK 0x8
+#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI__SHIFT 0x3
+#define MC_XBAR_REMOTE__WRREQ_EN_GOQ_MASK 0x1
+#define MC_XBAR_REMOTE__WRREQ_EN_GOQ__SHIFT 0x0
+#define MC_XBAR_REMOTE__RDREQ_EN_GOQ_MASK 0x2
+#define MC_XBAR_REMOTE__RDREQ_EN_GOQ__SHIFT 0x1
+#define MC_XBAR_WRREQ_CREDIT__OUT0_MASK 0xff
+#define MC_XBAR_WRREQ_CREDIT__OUT0__SHIFT 0x0
+#define MC_XBAR_WRREQ_CREDIT__OUT1_MASK 0xff00
+#define MC_XBAR_WRREQ_CREDIT__OUT1__SHIFT 0x8
+#define MC_XBAR_WRREQ_CREDIT__OUT2_MASK 0xff0000
+#define MC_XBAR_WRREQ_CREDIT__OUT2__SHIFT 0x10
+#define MC_XBAR_WRREQ_CREDIT__OUT3_MASK 0xff000000
+#define MC_XBAR_WRREQ_CREDIT__OUT3__SHIFT 0x18
+#define MC_XBAR_RDREQ_CREDIT__OUT0_MASK 0xff
+#define MC_XBAR_RDREQ_CREDIT__OUT0__SHIFT 0x0
+#define MC_XBAR_RDREQ_CREDIT__OUT1_MASK 0xff00
+#define MC_XBAR_RDREQ_CREDIT__OUT1__SHIFT 0x8
+#define MC_XBAR_RDREQ_CREDIT__OUT2_MASK 0xff0000
+#define MC_XBAR_RDREQ_CREDIT__OUT2__SHIFT 0x10
+#define MC_XBAR_RDREQ_CREDIT__OUT3_MASK 0xff000000
+#define MC_XBAR_RDREQ_CREDIT__OUT3__SHIFT 0x18
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0_MASK 0xff
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0__SHIFT 0x0
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1_MASK 0xff00
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1__SHIFT 0x8
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2_MASK 0xff0000
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2__SHIFT 0x10
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3_MASK 0xff000000
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3__SHIFT 0x18
+#define MC_XBAR_WRRET_CREDIT1__OUT0_MASK 0xff
+#define MC_XBAR_WRRET_CREDIT1__OUT0__SHIFT 0x0
+#define MC_XBAR_WRRET_CREDIT1__OUT1_MASK 0xff00
+#define MC_XBAR_WRRET_CREDIT1__OUT1__SHIFT 0x8
+#define MC_XBAR_WRRET_CREDIT1__OUT2_MASK 0xff0000
+#define MC_XBAR_WRRET_CREDIT1__OUT2__SHIFT 0x10
+#define MC_XBAR_WRRET_CREDIT1__OUT3_MASK 0xff000000
+#define MC_XBAR_WRRET_CREDIT1__OUT3__SHIFT 0x18
+#define MC_XBAR_WRRET_CREDIT2__OUT4_MASK 0xff
+#define MC_XBAR_WRRET_CREDIT2__OUT4__SHIFT 0x0
+#define MC_XBAR_WRRET_CREDIT2__OUT5_MASK 0xff00
+#define MC_XBAR_WRRET_CREDIT2__OUT5__SHIFT 0x8
+#define MC_XBAR_RDRET_CREDIT1__OUT0_MASK 0xff
+#define MC_XBAR_RDRET_CREDIT1__OUT0__SHIFT 0x0
+#define MC_XBAR_RDRET_CREDIT1__OUT1_MASK 0xff00
+#define MC_XBAR_RDRET_CREDIT1__OUT1__SHIFT 0x8
+#define MC_XBAR_RDRET_CREDIT1__OUT2_MASK 0xff0000
+#define MC_XBAR_RDRET_CREDIT1__OUT2__SHIFT 0x10
+#define MC_XBAR_RDRET_CREDIT1__OUT3_MASK 0xff000000
+#define MC_XBAR_RDRET_CREDIT1__OUT3__SHIFT 0x18
+#define MC_XBAR_RDRET_CREDIT2__OUT4_MASK 0xff
+#define MC_XBAR_RDRET_CREDIT2__OUT4__SHIFT 0x0
+#define MC_XBAR_RDRET_CREDIT2__OUT5_MASK 0xff00
+#define MC_XBAR_RDRET_CREDIT2__OUT5__SHIFT 0x8
+#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID_MASK 0xff0000
+#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID__SHIFT 0x10
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0_MASK 0xff
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0__SHIFT 0x0
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1_MASK 0xff00
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1__SHIFT 0x8
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2_MASK 0xff0000
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2__SHIFT 0x10
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3_MASK 0xff000000
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3__SHIFT 0x18
+#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4_MASK 0xff
+#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4__SHIFT 0x0
+#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5_MASK 0xff00
+#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5__SHIFT 0x8
+#define MC_XBAR_CHTRIREMAP__CH0_MASK 0x3
+#define MC_XBAR_CHTRIREMAP__CH0__SHIFT 0x0
+#define MC_XBAR_CHTRIREMAP__CH1_MASK 0xc
+#define MC_XBAR_CHTRIREMAP__CH1__SHIFT 0x2
+#define MC_XBAR_CHTRIREMAP__CH2_MASK 0x30
+#define MC_XBAR_CHTRIREMAP__CH2__SHIFT 0x4
+#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT_MASK 0x1
+#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT__SHIFT 0x0
+#define MC_XBAR_TWOCHAN__CH0_MASK 0x6
+#define MC_XBAR_TWOCHAN__CH0__SHIFT 0x1
+#define MC_XBAR_TWOCHAN__CH1_MASK 0x18
+#define MC_XBAR_TWOCHAN__CH1__SHIFT 0x3
+#define MC_XBAR_ARB__HUBRD_HIGHEST_MASK 0x1
+#define MC_XBAR_ARB__HUBRD_HIGHEST__SHIFT 0x0
+#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST_MASK 0x2
+#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST__SHIFT 0x1
+#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE_MASK 0x4
+#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE__SHIFT 0x2
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT0_MASK 0xf
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT0__SHIFT 0x0
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT1_MASK 0xf0
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT1__SHIFT 0x4
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT2_MASK 0xf00
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT2__SHIFT 0x8
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT3_MASK 0xf000
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT3__SHIFT 0xc
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT0_MASK 0xf0000
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT0__SHIFT 0x10
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT1_MASK 0xf00000
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT1__SHIFT 0x14
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT2_MASK 0xf000000
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT2__SHIFT 0x18
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT3_MASK 0xf0000000
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT3__SHIFT 0x1c
+#define MC_XBAR_PERF_MON_CNTL0__START_THRESH_MASK 0xfff
+#define MC_XBAR_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0
+#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000
+#define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc
+#define MC_XBAR_PERF_MON_CNTL0__START_MODE_MASK 0x3000000
+#define MC_XBAR_PERF_MON_CNTL0__START_MODE__SHIFT 0x18
+#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000
+#define MC_XBAR_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a
+#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000
+#define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c
+#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0xff
+#define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0
+#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xff00
+#define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x8
+#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0xff0000
+#define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x10
+#define MC_XBAR_PERF_MON_CNTL2__MON0_ID_MASK 0xff
+#define MC_XBAR_PERF_MON_CNTL2__MON0_ID__SHIFT 0x0
+#define MC_XBAR_PERF_MON_CNTL2__MON1_ID_MASK 0xff00
+#define MC_XBAR_PERF_MON_CNTL2__MON1_ID__SHIFT 0x8
+#define MC_XBAR_PERF_MON_CNTL2__MON2_ID_MASK 0xff0000
+#define MC_XBAR_PERF_MON_CNTL2__MON2_ID__SHIFT 0x10
+#define MC_XBAR_PERF_MON_CNTL2__MON3_ID_MASK 0xff000000
+#define MC_XBAR_PERF_MON_CNTL2__MON3_ID__SHIFT 0x18
+#define MC_XBAR_PERF_MON_RSLT0__COUNT_MASK 0xffffffff
+#define MC_XBAR_PERF_MON_RSLT0__COUNT__SHIFT 0x0
+#define MC_XBAR_PERF_MON_RSLT1__COUNT_MASK 0xffffffff
+#define MC_XBAR_PERF_MON_RSLT1__COUNT__SHIFT 0x0
+#define MC_XBAR_PERF_MON_RSLT2__COUNT_MASK 0xffffffff
+#define MC_XBAR_PERF_MON_RSLT2__COUNT__SHIFT 0x0
+#define MC_XBAR_PERF_MON_RSLT3__COUNT_MASK 0xffffffff
+#define MC_XBAR_PERF_MON_RSLT3__COUNT__SHIFT 0x0
+#define MC_XBAR_PERF_MON_MAX_THSH__MON0_MASK 0xff
+#define MC_XBAR_PERF_MON_MAX_THSH__MON0__SHIFT 0x0
+#define MC_XBAR_PERF_MON_MAX_THSH__MON1_MASK 0xff00
+#define MC_XBAR_PERF_MON_MAX_THSH__MON1__SHIFT 0x8
+#define MC_XBAR_PERF_MON_MAX_THSH__MON2_MASK 0xff0000
+#define MC_XBAR_PERF_MON_MAX_THSH__MON2__SHIFT 0x10
+#define MC_XBAR_PERF_MON_MAX_THSH__MON3_MASK 0xff000000
+#define MC_XBAR_PERF_MON_MAX_THSH__MON3__SHIFT 0x18
+#define MC_XBAR_SPARE0__BIT_MASK 0xffffffff
+#define MC_XBAR_SPARE0__BIT__SHIFT 0x0
+#define MC_XBAR_SPARE1__BIT_MASK 0xffffffff
+#define MC_XBAR_SPARE1__BIT__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_CITF_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_CITF_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_CITF_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_CITF_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_CITF_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_CITF_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_CITF_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_CITF_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_CITF_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_CITF_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_CITF_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_CITF_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_CITF_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_CITF_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_CITF_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_CITF_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_HUB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_HUB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_HUB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_HUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_HUB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_HUB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_HUB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_HUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_HUB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_HUB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_HUB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_HUB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_HUB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_HUB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_HUB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_HUB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_ARB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_ARB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_ARB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_ARB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_ARB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_ARB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_ARB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_ARB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_ARB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_ARB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_ARB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_ARB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_ARB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_ARB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_ARB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_ARB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_ARB_PERF_MON_CNTL0_ECC__ALLOW_WRAP_MASK 0x1
+#define MC_ARB_PERF_MON_CNTL0_ECC__ALLOW_WRAP__SHIFT 0x0
+#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
+#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
+#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
+#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
+#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
+#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
+#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
+#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
+#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x3
+#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x0
+#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x3
+#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x0
+#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0xffff
+#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0
+#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0xffff
+#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0
+#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x1
+#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0
+#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x2
+#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1
+#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x4
+#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2
+#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x3f00
+#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
+#define ATC_ATS_CNTL__DEBUG_ECO_MASK 0xf0000
+#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x10
+#define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x1
+#define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x0
+#define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x2
+#define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x1
+#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x4
+#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x2
+#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x20
+#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x5
+#define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x40
+#define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x6
+#define ATC_ATS_DEBUG__EXE_BIT_MASK 0x80
+#define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x7
+#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x100
+#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x8
+#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x200
+#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x9
+#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x3c00
+#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0xa
+#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x4000
+#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0xe
+#define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x8000
+#define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0xf
+#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x10000
+#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x10
+#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT_MASK 0x20000
+#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT__SHIFT 0x11
+#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x40000
+#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x12
+#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x1f
+#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x0
+#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x100
+#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x8
+#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x10000
+#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x10
+#define ATC_ATS_STATUS__BUSY_MASK 0x1
+#define ATC_ATS_STATUS__BUSY__SHIFT 0x0
+#define ATC_ATS_STATUS__CRASHED_MASK 0x2
+#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1
+#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x4
+#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2
+#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x3f
+#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0
+#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0xfc00
+#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa
+#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x3f00000
+#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14
+#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x3f
+#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0
+#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x7c00
+#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x8000
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x10000
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10
+#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x20000
+#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x40000
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12
+#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0xf80000
+#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0xf000000
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18
+#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffff
+#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0
+#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xffffffff
+#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0
+#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x1
+#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x0
+#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH_MASK 0x3c
+#define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH__SHIFT 0x2
+#define ATC_MISC_CG__OFFDLY_MASK 0xfc0
+#define ATC_MISC_CG__OFFDLY__SHIFT 0x6
+#define ATC_MISC_CG__ENABLE_MASK 0x40000
+#define ATC_MISC_CG__ENABLE__SHIFT 0x12
+#define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x80000
+#define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x3
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x30
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x4
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x100
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x8
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x200
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x9
+#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x3f
+#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0xc0
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6
+#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x100
+#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8
+#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0xe00
+#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9
+#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x7000
+#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f8000
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf
+#define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x3f
+#define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x0
+#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE_MASK 0x1f
+#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE__SHIFT 0x0
+#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0xe0
+#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x5
+#define ATC_L2_DEBUG2__FORCE_CACHE_MISS_MASK 0x100
+#define ATC_L2_DEBUG2__FORCE_CACHE_MISS__SHIFT 0x8
+#define ATC_L2_DEBUG2__INVALIDATE_ALL_MASK 0x200
+#define ATC_L2_DEBUG2__INVALIDATE_ALL__SHIFT 0x9
+#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_READ_RETURNS_MASK 0x800
+#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_READ_RETURNS__SHIFT 0xb
+#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS_MASK 0x1000
+#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS__SHIFT 0xc
+#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS_MASK 0x4000
+#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0xe
+#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT_MASK 0x18000
+#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT__SHIFT 0xf
+#define ATC_L2_DEBUG2__DEBUG_ECO_MASK 0x60000
+#define ATC_L2_DEBUG2__DEBUG_ECO__SHIFT 0x11
+#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x3
+#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x0
+#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x4
+#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x2
+#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x10
+#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x4
+#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffff
+#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x0
+#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
+#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
+#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
+#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
+#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
+#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
+#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
+#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
+#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
+#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
+#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
+#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
+#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
+#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
+#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
+#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
+#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000
+#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f
+#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
+#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
+#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
+#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
+#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
+#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
+#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
+#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
+#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
+#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
+#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
+#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
+#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
+#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
+#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
+#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
+#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000
+#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f
+#define ATC_L1RD_STATUS__BUSY_MASK 0x1
+#define ATC_L1RD_STATUS__BUSY__SHIFT 0x0
+#define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x2
+#define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
+#define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x100
+#define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x8
+#define ATC_L1WR_STATUS__BUSY_MASK 0x1
+#define ATC_L1WR_STATUS__BUSY__SHIFT 0x0
+#define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x2
+#define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
+#define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x100
+#define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x8
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x1
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x2
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x4
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x8
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x10
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x20
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x40
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x80
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x100
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x200
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x400
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x800
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x1000
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x2000
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x4000
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x8000
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf
+#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f
+#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x3ff
+#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0
+#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffff
+#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x1
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x2
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0xffc
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x3ff000
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0xc
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc00000
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x16
+#define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x400
+#define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0xa
+#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x800
+#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0xb
+#define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0xf000
+#define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0xc
+#define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x10000
+#define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x10
+#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x60000
+#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x11
+#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x180000
+#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x13
+#define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x200000
+#define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x15
+#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x400000
+#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x16
+#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x800000
+#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x17
+#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x1000000
+#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x18
+#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x2000000
+#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x19
+#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x4000000
+#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x1a
+#define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x8000000
+#define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x1b
+#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x70000000
+#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1c
+#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x80000000
+#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x1f
+#define GMCON_MISC2__GMCON_MISC2_RESERVED0_MASK 0x3f
+#define GMCON_MISC2__GMCON_MISC2_RESERVED0__SHIFT 0x0
+#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD_MASK 0x7c0
+#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD__SHIFT 0x6
+#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x1f800
+#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0xb
+#define GMCON_MISC2__GMCON_MISC2_RESERVED1_MASK 0x1ffe0000
+#define GMCON_MISC2__GMCON_MISC2_RESERVED1__SHIFT 0x11
+#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x20000000
+#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x1d
+#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x40000000
+#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x1e
+#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE_MASK 0x80000000
+#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE__SHIFT 0x1f
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0xffff
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x0
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff0000
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x10
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0xffff
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x0
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff0000
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x10
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0xffff
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x0
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff0000
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x10
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0xffff
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff0000
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0xffff
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff0000
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10
+#define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0xfff
+#define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0
+#define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000
+#define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc
+#define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x3000000
+#define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x18
+#define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000
+#define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a
+#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000
+#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c
+#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT_MASK 0x20000000
+#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT__SHIFT 0x1d
+#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT_MASK 0x40000000
+#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT__SHIFT 0x1e
+#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT_MASK 0x80000000
+#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT__SHIFT 0x1f
+#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x3f
+#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0
+#define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xfc0
+#define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x6
+#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x3f000
+#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0xc
+#define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0x1fc0000
+#define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x12
+#define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0xfe000000
+#define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x19
+#define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffff
+#define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x0
+#define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffff
+#define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x0
+#define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0xff
+#define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
+#define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x100
+#define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
+#define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x200
+#define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
+#define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x400
+#define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
+#define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x800
+#define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
+#define GMCON_PGFSM_CONFIG__WRITE_MASK 0x1000
+#define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0xc
+#define GMCON_PGFSM_CONFIG__READ_MASK 0x2000
+#define GMCON_PGFSM_CONFIG__READ__SHIFT 0xd
+#define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x7ffc000
+#define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0xe
+#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000
+#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
+#define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000
+#define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
+#define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffff
+#define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x0
+#define GMCON_PGFSM_READ__READ_VALUE_MASK 0xffffff
+#define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x0
+#define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0xf000000
+#define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x18
+#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x10000000
+#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x1c
+#define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0xff
+#define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x0
+#define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0xff00
+#define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x8
+#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0xfff0000
+#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10
+#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER_MASK 0x10000000
+#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER__SHIFT 0x1c
+#define GMCON_MISC3__RENG_MEM_LS_ENABLE_MASK 0x20000000
+#define GMCON_MISC3__RENG_MEM_LS_ENABLE__SHIFT 0x1d
+#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS_MASK 0x40000000
+#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS__SHIFT 0x1e
+#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD_MASK 0x1
+#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD__SHIFT 0x0
+#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR_MASK 0x2
+#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR__SHIFT 0x1
+#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD_MASK 0x4
+#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD__SHIFT 0x2
+#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR_MASK 0x8
+#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR__SHIFT 0x3
+#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK_MASK 0xff0
+#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK__SHIFT 0x4
+#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET_MASK 0xffffffff
+#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET__SHIFT 0x0
+#define GMCON_DEBUG__GFX_STALL_MASK 0x1
+#define GMCON_DEBUG__GFX_STALL__SHIFT 0x0
+#define GMCON_DEBUG__GFX_CLEAR_MASK 0x2
+#define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x1
+#define GMCON_DEBUG__MISC_FLAGS_MASK 0x3ffffffc
+#define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x2
+#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x1
+#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
+#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x2
+#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
+#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0xc
+#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
+#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x30
+#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
+#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x100
+#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
+#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x200
+#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
+#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400
+#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
+#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x800
+#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
+#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x7000
+#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
+#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x38000
+#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
+#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x40000
+#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
+#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x180000
+#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
+#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x3e00000
+#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
+#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0xc000000
+#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a
+#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000
+#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c
+#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x1
+#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
+#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x2
+#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
+#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x200000
+#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
+#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x400000
+#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
+#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x3800000
+#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17
+#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0xc000000
+#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
+#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000
+#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
+#define VM_L2_CNTL3__BANK_SELECT_MASK 0x3f
+#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0xc0
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f00
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0xf8000
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
+#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x100000
+#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
+#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0xe00000
+#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
+#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0xf000000
+#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
+#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000
+#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
+#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000
+#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
+#define VM_L2_STATUS__L2_BUSY_MASK 0x1
+#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0
+#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x1fffe
+#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
+#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x1
+#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x6
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14
+#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000
+#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000
+#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000
+#define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18
+#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x1
+#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x6
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14
+#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000
+#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000
+#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000
+#define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x1
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x2
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK 0xc
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT 0x2
+#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK 0xfffffff
+#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT 0x0
+#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1
+#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
+#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2
+#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1
+#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4
+#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2
+#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8
+#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3
+#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10
+#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4
+#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1
+#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
+#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2
+#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1
+#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4
+#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2
+#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8
+#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3
+#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10
+#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK 0x1
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT 0x0
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK 0x2
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT 0x1
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK 0x4
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT 0x2
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK 0x8
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT 0x3
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK 0x10
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT 0x4
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK 0x20
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT 0x5
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK 0x40
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT 0x6
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK 0x80
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT 0x7
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK 0x100
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT 0x8
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK 0x200
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT 0x9
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK 0x400
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT 0xa
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK 0x800
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT 0xb
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK 0x1000
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT 0xc
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK 0x2000
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT 0xd
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK 0x4000
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT 0xe
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK 0x8000
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT 0xf
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK 0x1
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT 0x0
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK 0x2
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT 0x1
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK 0x4
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT 0x2
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK 0x8
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT 0x3
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK 0x10
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT 0x4
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK 0x20
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT 0x5
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK 0x40
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT 0x6
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK 0x80
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT 0x7
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK 0x100
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT 0x8
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK 0x200
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT 0x9
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK 0x400
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT 0xa
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK 0x800
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT 0xb
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK 0x1000
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT 0xc
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK 0x2000
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT 0xd
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK 0x4000
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT 0xe
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK 0x8000
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT 0xf
+#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x1
+#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x0
+#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x2
+#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x1
+#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x4
+#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x2
+#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK 0x8
+#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x3
+#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x10
+#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x4
+#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x20
+#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x5
+#define VM_PRT_CNTL__MASK_PDE0_FAULT_MASK 0x40
+#define VM_PRT_CNTL__MASK_PDE0_FAULT__SHIFT 0x6
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x1
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x2
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x4
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x8
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x10
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x20
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x40
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x80
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x100
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x200
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x400
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x800
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x1000
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x2000
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x4000
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x8000
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
+#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff
+#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0
+#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff
+#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0
+#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
+#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
+#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
+#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
+#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff
+#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0
+#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff
+#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK 0x1ff
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT 0x0
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK 0x3fe00
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT 0x9
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_DEBUG__FLAGS_MASK 0xffffffff
+#define VM_DEBUG__FLAGS__SHIFT 0x0
+#define VM_L2_CG__OFFDLY_MASK 0xfc0
+#define VM_L2_CG__OFFDLY__SHIFT 0x6
+#define VM_L2_CG__ENABLE_MASK 0x40000
+#define VM_L2_CG__ENABLE__SHIFT 0x12
+#define VM_L2_CG__MEM_LS_ENABLE_MASK 0x80000
+#define VM_L2_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK 0xfffffff
+#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT 0x0
+#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK 0x1ff
+#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK 0xfffffff
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT 0x0
+#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS_MASK 0x3
+#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS__SHIFT 0x0
+#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK_MASK 0xc
+#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK__SHIFT 0x2
+#define MC_SEQ_CNTL__SAFE_MODE_MASK 0x30
+#define MC_SEQ_CNTL__SAFE_MODE__SHIFT 0x4
+#define MC_SEQ_CNTL__DAT_INV_MASK 0x40
+#define MC_SEQ_CNTL__DAT_INV__SHIFT 0x6
+#define MC_SEQ_CNTL__MSK_DF1_MASK 0x80
+#define MC_SEQ_CNTL__MSK_DF1__SHIFT 0x7
+#define MC_SEQ_CNTL__CHANNEL_DISABLE_MASK 0x300
+#define MC_SEQ_CNTL__CHANNEL_DISABLE__SHIFT 0x8
+#define MC_SEQ_CNTL__MSKOFF_DAT_TL_MASK 0x4000
+#define MC_SEQ_CNTL__MSKOFF_DAT_TL__SHIFT 0xe
+#define MC_SEQ_CNTL__MSKOFF_DAT_TH_MASK 0x8000
+#define MC_SEQ_CNTL__MSKOFF_DAT_TH__SHIFT 0xf
+#define MC_SEQ_CNTL__RET_HOLD_EOP_MASK 0x10000
+#define MC_SEQ_CNTL__RET_HOLD_EOP__SHIFT 0x10
+#define MC_SEQ_CNTL__BANKGROUP_SIZE_MASK 0x20000
+#define MC_SEQ_CNTL__BANKGROUP_SIZE__SHIFT 0x11
+#define MC_SEQ_CNTL__BANKGROUP_ENB_MASK 0x40000
+#define MC_SEQ_CNTL__BANKGROUP_ENB__SHIFT 0x12
+#define MC_SEQ_CNTL__RTR_OVERRIDE_MASK 0x80000
+#define MC_SEQ_CNTL__RTR_OVERRIDE__SHIFT 0x13
+#define MC_SEQ_CNTL__ARB_REQCMD_WMK_MASK 0xf00000
+#define MC_SEQ_CNTL__ARB_REQCMD_WMK__SHIFT 0x14
+#define MC_SEQ_CNTL__ARB_REQDAT_WMK_MASK 0xf000000
+#define MC_SEQ_CNTL__ARB_REQDAT_WMK__SHIFT 0x18
+#define MC_SEQ_CNTL__ARB_RTDAT_WMK_MASK 0xf0000000
+#define MC_SEQ_CNTL__ARB_RTDAT_WMK__SHIFT 0x1c
+#define MC_SEQ_CNTL_2__DRST_PDRV_MASK 0xf
+#define MC_SEQ_CNTL_2__DRST_PDRV__SHIFT 0x0
+#define MC_SEQ_CNTL_2__DRST_PU_MASK 0x10
+#define MC_SEQ_CNTL_2__DRST_PU__SHIFT 0x4
+#define MC_SEQ_CNTL_2__DRST_PD_MASK 0x20
+#define MC_SEQ_CNTL_2__DRST_PD__SHIFT 0x5
+#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB_MASK 0x300
+#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB__SHIFT 0x8
+#define MC_SEQ_CNTL_2__DRST_NSTR_MASK 0xfc00
+#define MC_SEQ_CNTL_2__DRST_NSTR__SHIFT 0xa
+#define MC_SEQ_CNTL_2__DRST_PSTR_MASK 0x3f0000
+#define MC_SEQ_CNTL_2__DRST_PSTR__SHIFT 0x10
+#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0_MASK 0x400000
+#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0__SHIFT 0x16
+#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1_MASK 0x800000
+#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1__SHIFT 0x17
+#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0_MASK 0xf000000
+#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0__SHIFT 0x18
+#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1_MASK 0xf0000000
+#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1__SHIFT 0x1c
+#define MC_SEQ_DRAM__ADR_2CK_MASK 0x1
+#define MC_SEQ_DRAM__ADR_2CK__SHIFT 0x0
+#define MC_SEQ_DRAM__ADR_MUX_MASK 0x2
+#define MC_SEQ_DRAM__ADR_MUX__SHIFT 0x1
+#define MC_SEQ_DRAM__ADR_DF1_MASK 0x4
+#define MC_SEQ_DRAM__ADR_DF1__SHIFT 0x2
+#define MC_SEQ_DRAM__AP8_MASK 0x8
+#define MC_SEQ_DRAM__AP8__SHIFT 0x3
+#define MC_SEQ_DRAM__DAT_DF1_MASK 0x10
+#define MC_SEQ_DRAM__DAT_DF1__SHIFT 0x4
+#define MC_SEQ_DRAM__DQS_DF1_MASK 0x20
+#define MC_SEQ_DRAM__DQS_DF1__SHIFT 0x5
+#define MC_SEQ_DRAM__DQM_DF1_MASK 0x40
+#define MC_SEQ_DRAM__DQM_DF1__SHIFT 0x6
+#define MC_SEQ_DRAM__DQM_ACT_MASK 0x80
+#define MC_SEQ_DRAM__DQM_ACT__SHIFT 0x7
+#define MC_SEQ_DRAM__STB_CNT_MASK 0xf00
+#define MC_SEQ_DRAM__STB_CNT__SHIFT 0x8
+#define MC_SEQ_DRAM__CKE_DYN_MASK 0x1000
+#define MC_SEQ_DRAM__CKE_DYN__SHIFT 0xc
+#define MC_SEQ_DRAM__CKE_ACT_MASK 0x2000
+#define MC_SEQ_DRAM__CKE_ACT__SHIFT 0xd
+#define MC_SEQ_DRAM__BO4_MASK 0x4000
+#define MC_SEQ_DRAM__BO4__SHIFT 0xe
+#define MC_SEQ_DRAM__DLL_CLR_MASK 0x8000
+#define MC_SEQ_DRAM__DLL_CLR__SHIFT 0xf
+#define MC_SEQ_DRAM__DLL_CNT_MASK 0xff0000
+#define MC_SEQ_DRAM__DLL_CNT__SHIFT 0x10
+#define MC_SEQ_DRAM__DAT_INV_MASK 0x1000000
+#define MC_SEQ_DRAM__DAT_INV__SHIFT 0x18
+#define MC_SEQ_DRAM__INV_ACM_MASK 0x2000000
+#define MC_SEQ_DRAM__INV_ACM__SHIFT 0x19
+#define MC_SEQ_DRAM__ODT_ENB_MASK 0x4000000
+#define MC_SEQ_DRAM__ODT_ENB__SHIFT 0x1a
+#define MC_SEQ_DRAM__ODT_ACT_MASK 0x8000000
+#define MC_SEQ_DRAM__ODT_ACT__SHIFT 0x1b
+#define MC_SEQ_DRAM__RST_CTL_MASK 0x10000000
+#define MC_SEQ_DRAM__RST_CTL__SHIFT 0x1c
+#define MC_SEQ_DRAM__TRI_MIO_DYN_MASK 0x20000000
+#define MC_SEQ_DRAM__TRI_MIO_DYN__SHIFT 0x1d
+#define MC_SEQ_DRAM__TRI_CKE_MASK 0x40000000
+#define MC_SEQ_DRAM__TRI_CKE__SHIFT 0x1e
+#define MC_SEQ_DRAM__RDSTRB_RSYC_DIS_MASK 0x80000000
+#define MC_SEQ_DRAM__RDSTRB_RSYC_DIS__SHIFT 0x1f
+#define MC_SEQ_DRAM_2__ADR_DDR_MASK 0x1
+#define MC_SEQ_DRAM_2__ADR_DDR__SHIFT 0x0
+#define MC_SEQ_DRAM_2__ADR_DBI_MASK 0x2
+#define MC_SEQ_DRAM_2__ADR_DBI__SHIFT 0x1
+#define MC_SEQ_DRAM_2__ADR_DBI_ACM_MASK 0x4
+#define MC_SEQ_DRAM_2__ADR_DBI_ACM__SHIFT 0x2
+#define MC_SEQ_DRAM_2__CMD_QDR_MASK 0x8
+#define MC_SEQ_DRAM_2__CMD_QDR__SHIFT 0x3
+#define MC_SEQ_DRAM_2__DAT_QDR_MASK 0x10
+#define MC_SEQ_DRAM_2__DAT_QDR__SHIFT 0x4
+#define MC_SEQ_DRAM_2__WDAT_EDC_MASK 0x20
+#define MC_SEQ_DRAM_2__WDAT_EDC__SHIFT 0x5
+#define MC_SEQ_DRAM_2__RDAT_EDC_MASK 0x40
+#define MC_SEQ_DRAM_2__RDAT_EDC__SHIFT 0x6
+#define MC_SEQ_DRAM_2__DQM_EST_MASK 0x80
+#define MC_SEQ_DRAM_2__DQM_EST__SHIFT 0x7
+#define MC_SEQ_DRAM_2__RD_DQS_MASK 0x100
+#define MC_SEQ_DRAM_2__RD_DQS__SHIFT 0x8
+#define MC_SEQ_DRAM_2__WR_DQS_MASK 0x200
+#define MC_SEQ_DRAM_2__WR_DQS__SHIFT 0x9
+#define MC_SEQ_DRAM_2__PLL_EST_MASK 0x400
+#define MC_SEQ_DRAM_2__PLL_EST__SHIFT 0xa
+#define MC_SEQ_DRAM_2__PLL_CLR_MASK 0x800
+#define MC_SEQ_DRAM_2__PLL_CLR__SHIFT 0xb
+#define MC_SEQ_DRAM_2__DLL_EST_MASK 0x1000
+#define MC_SEQ_DRAM_2__DLL_EST__SHIFT 0xc
+#define MC_SEQ_DRAM_2__BNK_MRS_MASK 0x2000
+#define MC_SEQ_DRAM_2__BNK_MRS__SHIFT 0xd
+#define MC_SEQ_DRAM_2__DBI_OVR_MASK 0x4000
+#define MC_SEQ_DRAM_2__DBI_OVR__SHIFT 0xe
+#define MC_SEQ_DRAM_2__TRI_CLK_MASK 0x8000
+#define MC_SEQ_DRAM_2__TRI_CLK__SHIFT 0xf
+#define MC_SEQ_DRAM_2__PLL_CNT_MASK 0xff0000
+#define MC_SEQ_DRAM_2__PLL_CNT__SHIFT 0x10
+#define MC_SEQ_DRAM_2__PCH_BNK_MASK 0x1000000
+#define MC_SEQ_DRAM_2__PCH_BNK__SHIFT 0x18
+#define MC_SEQ_DRAM_2__ADBI_DF1_MASK 0x2000000
+#define MC_SEQ_DRAM_2__ADBI_DF1__SHIFT 0x19
+#define MC_SEQ_DRAM_2__ADBI_ACT_MASK 0x4000000
+#define MC_SEQ_DRAM_2__ADBI_ACT__SHIFT 0x1a
+#define MC_SEQ_DRAM_2__DBI_DF1_MASK 0x8000000
+#define MC_SEQ_DRAM_2__DBI_DF1__SHIFT 0x1b
+#define MC_SEQ_DRAM_2__DBI_ACT_MASK 0x10000000
+#define MC_SEQ_DRAM_2__DBI_ACT__SHIFT 0x1c
+#define MC_SEQ_DRAM_2__DBI_EDC_DF1_MASK 0x20000000
+#define MC_SEQ_DRAM_2__DBI_EDC_DF1__SHIFT 0x1d
+#define MC_SEQ_DRAM_2__TESTCHIP_EN_MASK 0x40000000
+#define MC_SEQ_DRAM_2__TESTCHIP_EN__SHIFT 0x1e
+#define MC_SEQ_DRAM_2__CS_BY16_MASK 0x80000000
+#define MC_SEQ_DRAM_2__CS_BY16__SHIFT 0x1f
+#define MC_SEQ_RAS_TIMING__TRCDW_MASK 0x1f
+#define MC_SEQ_RAS_TIMING__TRCDW__SHIFT 0x0
+#define MC_SEQ_RAS_TIMING__TRCDWA_MASK 0x3e0
+#define MC_SEQ_RAS_TIMING__TRCDWA__SHIFT 0x5
+#define MC_SEQ_RAS_TIMING__TRCDR_MASK 0x7c00
+#define MC_SEQ_RAS_TIMING__TRCDR__SHIFT 0xa
+#define MC_SEQ_RAS_TIMING__TRCDRA_MASK 0xf8000
+#define MC_SEQ_RAS_TIMING__TRCDRA__SHIFT 0xf
+#define MC_SEQ_RAS_TIMING__TRRD_MASK 0xf00000
+#define MC_SEQ_RAS_TIMING__TRRD__SHIFT 0x14
+#define MC_SEQ_RAS_TIMING__TRC_MASK 0x7f000000
+#define MC_SEQ_RAS_TIMING__TRC__SHIFT 0x18
+#define MC_SEQ_CAS_TIMING__TNOPW_MASK 0x3
+#define MC_SEQ_CAS_TIMING__TNOPW__SHIFT 0x0
+#define MC_SEQ_CAS_TIMING__TNOPR_MASK 0xc
+#define MC_SEQ_CAS_TIMING__TNOPR__SHIFT 0x2
+#define MC_SEQ_CAS_TIMING__TR2W_MASK 0x1f0
+#define MC_SEQ_CAS_TIMING__TR2W__SHIFT 0x4
+#define MC_SEQ_CAS_TIMING__TCCDL_MASK 0xe00
+#define MC_SEQ_CAS_TIMING__TCCDL__SHIFT 0x9
+#define MC_SEQ_CAS_TIMING__TR2R_MASK 0xf000
+#define MC_SEQ_CAS_TIMING__TR2R__SHIFT 0xc
+#define MC_SEQ_CAS_TIMING__TW2R_MASK 0x1f0000
+#define MC_SEQ_CAS_TIMING__TW2R__SHIFT 0x10
+#define MC_SEQ_CAS_TIMING__TCL_MASK 0x1f000000
+#define MC_SEQ_CAS_TIMING__TCL__SHIFT 0x18
+#define MC_SEQ_MISC_TIMING__TRP_WRA_MASK 0x3f
+#define MC_SEQ_MISC_TIMING__TRP_WRA__SHIFT 0x0
+#define MC_SEQ_MISC_TIMING__TRP_RDA_MASK 0x3f00
+#define MC_SEQ_MISC_TIMING__TRP_RDA__SHIFT 0x8
+#define MC_SEQ_MISC_TIMING__TRP_MASK 0xf8000
+#define MC_SEQ_MISC_TIMING__TRP__SHIFT 0xf
+#define MC_SEQ_MISC_TIMING__TRFC_MASK 0x1ff00000
+#define MC_SEQ_MISC_TIMING__TRFC__SHIFT 0x14
+#define MC_SEQ_MISC_TIMING2__PA2RDATA_MASK 0x7
+#define MC_SEQ_MISC_TIMING2__PA2RDATA__SHIFT 0x0
+#define MC_SEQ_MISC_TIMING2__PA2WDATA_MASK 0x70
+#define MC_SEQ_MISC_TIMING2__PA2WDATA__SHIFT 0x4
+#define MC_SEQ_MISC_TIMING2__FAW_MASK 0x1f00
+#define MC_SEQ_MISC_TIMING2__FAW__SHIFT 0x8
+#define MC_SEQ_MISC_TIMING2__TREDC_MASK 0xe000
+#define MC_SEQ_MISC_TIMING2__TREDC__SHIFT 0xd
+#define MC_SEQ_MISC_TIMING2__TWEDC_MASK 0x1f0000
+#define MC_SEQ_MISC_TIMING2__TWEDC__SHIFT 0x10
+#define MC_SEQ_MISC_TIMING2__T32AW_MASK 0x1e00000
+#define MC_SEQ_MISC_TIMING2__T32AW__SHIFT 0x15
+#define MC_SEQ_MISC_TIMING2__TWDATATR_MASK 0xf0000000
+#define MC_SEQ_MISC_TIMING2__TWDATATR__SHIFT 0x1c
+#define MC_SEQ_PMG_TIMING__TCKSRE_MASK 0x7
+#define MC_SEQ_PMG_TIMING__TCKSRE__SHIFT 0x0
+#define MC_SEQ_PMG_TIMING__TCKSRX_MASK 0x70
+#define MC_SEQ_PMG_TIMING__TCKSRX__SHIFT 0x4
+#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MASK 0xf00
+#define MC_SEQ_PMG_TIMING__TCKE_PULSE__SHIFT 0x8
+#define MC_SEQ_PMG_TIMING__TCKE_MASK 0x3f000
+#define MC_SEQ_PMG_TIMING__TCKE__SHIFT 0xc
+#define MC_SEQ_PMG_TIMING__SEQ_IDLE_MASK 0x1c0000
+#define MC_SEQ_PMG_TIMING__SEQ_IDLE__SHIFT 0x12
+#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB_MASK 0x800000
+#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB__SHIFT 0x17
+#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS_MASK 0xff000000
+#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS__SHIFT 0x18
+#define MC_SEQ_RD_CTL_D0__RCV_DLY_MASK 0x7
+#define MC_SEQ_RD_CTL_D0__RCV_DLY__SHIFT 0x0
+#define MC_SEQ_RD_CTL_D0__RCV_EXT_MASK 0xf8
+#define MC_SEQ_RD_CTL_D0__RCV_EXT__SHIFT 0x3
+#define MC_SEQ_RD_CTL_D0__RST_SEL_MASK 0x300
+#define MC_SEQ_RD_CTL_D0__RST_SEL__SHIFT 0x8
+#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY_MASK 0xc00
+#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY__SHIFT 0xa
+#define MC_SEQ_RD_CTL_D0__RST_HLD_MASK 0xf000
+#define MC_SEQ_RD_CTL_D0__RST_HLD__SHIFT 0xc
+#define MC_SEQ_RD_CTL_D0__STR_PRE_MASK 0x10000
+#define MC_SEQ_RD_CTL_D0__STR_PRE__SHIFT 0x10
+#define MC_SEQ_RD_CTL_D0__STR_PST_MASK 0x20000
+#define MC_SEQ_RD_CTL_D0__STR_PST__SHIFT 0x11
+#define MC_SEQ_RD_CTL_D0__RBS_DLY_MASK 0x1f00000
+#define MC_SEQ_RD_CTL_D0__RBS_DLY__SHIFT 0x14
+#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY_MASK 0x3e000000
+#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY__SHIFT 0x19
+#define MC_SEQ_RD_CTL_D1__RCV_DLY_MASK 0x7
+#define MC_SEQ_RD_CTL_D1__RCV_DLY__SHIFT 0x0
+#define MC_SEQ_RD_CTL_D1__RCV_EXT_MASK 0xf8
+#define MC_SEQ_RD_CTL_D1__RCV_EXT__SHIFT 0x3
+#define MC_SEQ_RD_CTL_D1__RST_SEL_MASK 0x300
+#define MC_SEQ_RD_CTL_D1__RST_SEL__SHIFT 0x8
+#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY_MASK 0xc00
+#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY__SHIFT 0xa
+#define MC_SEQ_RD_CTL_D1__RST_HLD_MASK 0xf000
+#define MC_SEQ_RD_CTL_D1__RST_HLD__SHIFT 0xc
+#define MC_SEQ_RD_CTL_D1__STR_PRE_MASK 0x10000
+#define MC_SEQ_RD_CTL_D1__STR_PRE__SHIFT 0x10
+#define MC_SEQ_RD_CTL_D1__STR_PST_MASK 0x20000
+#define MC_SEQ_RD_CTL_D1__STR_PST__SHIFT 0x11
+#define MC_SEQ_RD_CTL_D1__RBS_DLY_MASK 0x1f00000
+#define MC_SEQ_RD_CTL_D1__RBS_DLY__SHIFT 0x14
+#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY_MASK 0x3e000000
+#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY__SHIFT 0x19
+#define MC_SEQ_WR_CTL_D0__DAT_DLY_MASK 0xf
+#define MC_SEQ_WR_CTL_D0__DAT_DLY__SHIFT 0x0
+#define MC_SEQ_WR_CTL_D0__DQS_DLY_MASK 0xf0
+#define MC_SEQ_WR_CTL_D0__DQS_DLY__SHIFT 0x4
+#define MC_SEQ_WR_CTL_D0__DQS_XTR_MASK 0x100
+#define MC_SEQ_WR_CTL_D0__DQS_XTR__SHIFT 0x8
+#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY_MASK 0x200
+#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY__SHIFT 0x9
+#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY_MASK 0x400
+#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY__SHIFT 0xa
+#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY_MASK 0x800
+#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY__SHIFT 0xb
+#define MC_SEQ_WR_CTL_D0__OEN_DLY_MASK 0xf000
+#define MC_SEQ_WR_CTL_D0__OEN_DLY__SHIFT 0xc
+#define MC_SEQ_WR_CTL_D0__OEN_EXT_MASK 0xf0000
+#define MC_SEQ_WR_CTL_D0__OEN_EXT__SHIFT 0x10
+#define MC_SEQ_WR_CTL_D0__OEN_SEL_MASK 0x300000
+#define MC_SEQ_WR_CTL_D0__OEN_SEL__SHIFT 0x14
+#define MC_SEQ_WR_CTL_D0__ODT_DLY_MASK 0xf000000
+#define MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT 0x18
+#define MC_SEQ_WR_CTL_D0__ODT_EXT_MASK 0x10000000
+#define MC_SEQ_WR_CTL_D0__ODT_EXT__SHIFT 0x1c
+#define MC_SEQ_WR_CTL_D0__ADR_DLY_MASK 0x20000000
+#define MC_SEQ_WR_CTL_D0__ADR_DLY__SHIFT 0x1d
+#define MC_SEQ_WR_CTL_D0__CMD_DLY_MASK 0x40000000
+#define MC_SEQ_WR_CTL_D0__CMD_DLY__SHIFT 0x1e
+#define MC_SEQ_WR_CTL_D1__DAT_DLY_MASK 0xf
+#define MC_SEQ_WR_CTL_D1__DAT_DLY__SHIFT 0x0
+#define MC_SEQ_WR_CTL_D1__DQS_DLY_MASK 0xf0
+#define MC_SEQ_WR_CTL_D1__DQS_DLY__SHIFT 0x4
+#define MC_SEQ_WR_CTL_D1__DQS_XTR_MASK 0x100
+#define MC_SEQ_WR_CTL_D1__DQS_XTR__SHIFT 0x8
+#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY_MASK 0x200
+#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY__SHIFT 0x9
+#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY_MASK 0x400
+#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY__SHIFT 0xa
+#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY_MASK 0x800
+#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY__SHIFT 0xb
+#define MC_SEQ_WR_CTL_D1__OEN_DLY_MASK 0xf000
+#define MC_SEQ_WR_CTL_D1__OEN_DLY__SHIFT 0xc
+#define MC_SEQ_WR_CTL_D1__OEN_EXT_MASK 0xf0000
+#define MC_SEQ_WR_CTL_D1__OEN_EXT__SHIFT 0x10
+#define MC_SEQ_WR_CTL_D1__OEN_SEL_MASK 0x300000
+#define MC_SEQ_WR_CTL_D1__OEN_SEL__SHIFT 0x14
+#define MC_SEQ_WR_CTL_D1__ODT_DLY_MASK 0xf000000
+#define MC_SEQ_WR_CTL_D1__ODT_DLY__SHIFT 0x18
+#define MC_SEQ_WR_CTL_D1__ODT_EXT_MASK 0x10000000
+#define MC_SEQ_WR_CTL_D1__ODT_EXT__SHIFT 0x1c
+#define MC_SEQ_WR_CTL_D1__ADR_DLY_MASK 0x20000000
+#define MC_SEQ_WR_CTL_D1__ADR_DLY__SHIFT 0x1d
+#define MC_SEQ_WR_CTL_D1__CMD_DLY_MASK 0x40000000
+#define MC_SEQ_WR_CTL_D1__CMD_DLY__SHIFT 0x1e
+#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0_MASK 0x1
+#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0__SHIFT 0x0
+#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0_MASK 0x2
+#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0__SHIFT 0x1
+#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0_MASK 0x4
+#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0__SHIFT 0x2
+#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1_MASK 0x8
+#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1__SHIFT 0x3
+#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1_MASK 0x10
+#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1__SHIFT 0x4
+#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1_MASK 0x20
+#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1__SHIFT 0x5
+#define MC_SEQ_WR_CTL_2__WCDR_EN_MASK 0x40
+#define MC_SEQ_WR_CTL_2__WCDR_EN__SHIFT 0x6
+#define MC_SEQ_CMD__ADR_MASK 0xffff
+#define MC_SEQ_CMD__ADR__SHIFT 0x0
+#define MC_SEQ_CMD__MOP_MASK 0xf0000
+#define MC_SEQ_CMD__MOP__SHIFT 0x10
+#define MC_SEQ_CMD__END_MASK 0x100000
+#define MC_SEQ_CMD__END__SHIFT 0x14
+#define MC_SEQ_CMD__CSB_MASK 0x600000
+#define MC_SEQ_CMD__CSB__SHIFT 0x15
+#define MC_SEQ_CMD__CHAN0_MASK 0x1000000
+#define MC_SEQ_CMD__CHAN0__SHIFT 0x18
+#define MC_SEQ_CMD__CHAN1_MASK 0x2000000
+#define MC_SEQ_CMD__CHAN1__SHIFT 0x19
+#define MC_SEQ_CMD__ADR_MSB1_MASK 0x10000000
+#define MC_SEQ_CMD__ADR_MSB1__SHIFT 0x1c
+#define MC_SEQ_CMD__ADR_MSB0_MASK 0x20000000
+#define MC_SEQ_CMD__ADR_MSB0__SHIFT 0x1d
+#define MC_PMG_CMD_EMRS__ADR_MASK 0xffff
+#define MC_PMG_CMD_EMRS__ADR__SHIFT 0x0
+#define MC_PMG_CMD_EMRS__MOP_MASK 0x70000
+#define MC_PMG_CMD_EMRS__MOP__SHIFT 0x10
+#define MC_PMG_CMD_EMRS__BNK_MSB_MASK 0x80000
+#define MC_PMG_CMD_EMRS__BNK_MSB__SHIFT 0x13
+#define MC_PMG_CMD_EMRS__END_MASK 0x100000
+#define MC_PMG_CMD_EMRS__END__SHIFT 0x14
+#define MC_PMG_CMD_EMRS__CSB_MASK 0x600000
+#define MC_PMG_CMD_EMRS__CSB__SHIFT 0x15
+#define MC_PMG_CMD_EMRS__ADR_MSB1_MASK 0x10000000
+#define MC_PMG_CMD_EMRS__ADR_MSB1__SHIFT 0x1c
+#define MC_PMG_CMD_EMRS__ADR_MSB0_MASK 0x20000000
+#define MC_PMG_CMD_EMRS__ADR_MSB0__SHIFT 0x1d
+#define MC_PMG_CMD_MRS__ADR_MASK 0xffff
+#define MC_PMG_CMD_MRS__ADR__SHIFT 0x0
+#define MC_PMG_CMD_MRS__MOP_MASK 0x70000
+#define MC_PMG_CMD_MRS__MOP__SHIFT 0x10
+#define MC_PMG_CMD_MRS__BNK_MSB_MASK 0x80000
+#define MC_PMG_CMD_MRS__BNK_MSB__SHIFT 0x13
+#define MC_PMG_CMD_MRS__END_MASK 0x100000
+#define MC_PMG_CMD_MRS__END__SHIFT 0x14
+#define MC_PMG_CMD_MRS__CSB_MASK 0x600000
+#define MC_PMG_CMD_MRS__CSB__SHIFT 0x15
+#define MC_PMG_CMD_MRS__ADR_MSB1_MASK 0x10000000
+#define MC_PMG_CMD_MRS__ADR_MSB1__SHIFT 0x1c
+#define MC_PMG_CMD_MRS__ADR_MSB0_MASK 0x20000000
+#define MC_PMG_CMD_MRS__ADR_MSB0__SHIFT 0x1d
+#define MC_PMG_CMD_MRS1__ADR_MASK 0xffff
+#define MC_PMG_CMD_MRS1__ADR__SHIFT 0x0
+#define MC_PMG_CMD_MRS1__MOP_MASK 0x70000
+#define MC_PMG_CMD_MRS1__MOP__SHIFT 0x10
+#define MC_PMG_CMD_MRS1__BNK_MSB_MASK 0x80000
+#define MC_PMG_CMD_MRS1__BNK_MSB__SHIFT 0x13
+#define MC_PMG_CMD_MRS1__END_MASK 0x100000
+#define MC_PMG_CMD_MRS1__END__SHIFT 0x14
+#define MC_PMG_CMD_MRS1__CSB_MASK 0x600000
+#define MC_PMG_CMD_MRS1__CSB__SHIFT 0x15
+#define MC_PMG_CMD_MRS1__ADR_MSB1_MASK 0x10000000
+#define MC_PMG_CMD_MRS1__ADR_MSB1__SHIFT 0x1c
+#define MC_PMG_CMD_MRS1__ADR_MSB0_MASK 0x20000000
+#define MC_PMG_CMD_MRS1__ADR_MSB0__SHIFT 0x1d
+#define MC_PMG_CMD_MRS2__ADR_MASK 0xffff
+#define MC_PMG_CMD_MRS2__ADR__SHIFT 0x0
+#define MC_PMG_CMD_MRS2__MOP_MASK 0x70000
+#define MC_PMG_CMD_MRS2__MOP__SHIFT 0x10
+#define MC_PMG_CMD_MRS2__BNK_MSB_MASK 0x80000
+#define MC_PMG_CMD_MRS2__BNK_MSB__SHIFT 0x13
+#define MC_PMG_CMD_MRS2__END_MASK 0x100000
+#define MC_PMG_CMD_MRS2__END__SHIFT 0x14
+#define MC_PMG_CMD_MRS2__CSB_MASK 0x600000
+#define MC_PMG_CMD_MRS2__CSB__SHIFT 0x15
+#define MC_PMG_CMD_MRS2__ADR_MSB1_MASK 0x10000000
+#define MC_PMG_CMD_MRS2__ADR_MSB1__SHIFT 0x1c
+#define MC_PMG_CMD_MRS2__ADR_MSB0_MASK 0x20000000
+#define MC_PMG_CMD_MRS2__ADR_MSB0__SHIFT 0x1d
+#define MC_PMG_CFG__SYC_CLK_MASK 0x1
+#define MC_PMG_CFG__SYC_CLK__SHIFT 0x0
+#define MC_PMG_CFG__RST_MRS_MASK 0x2
+#define MC_PMG_CFG__RST_MRS__SHIFT 0x1
+#define MC_PMG_CFG__RST_EMRS_MASK 0x4
+#define MC_PMG_CFG__RST_EMRS__SHIFT 0x2
+#define MC_PMG_CFG__TRI_MIO_MASK 0x8
+#define MC_PMG_CFG__TRI_MIO__SHIFT 0x3
+#define MC_PMG_CFG__XSR_TMR_MASK 0xf0
+#define MC_PMG_CFG__XSR_TMR__SHIFT 0x4
+#define MC_PMG_CFG__RST_MRS1_MASK 0x100
+#define MC_PMG_CFG__RST_MRS1__SHIFT 0x8
+#define MC_PMG_CFG__RST_MRS2_MASK 0x200
+#define MC_PMG_CFG__RST_MRS2__SHIFT 0x9
+#define MC_PMG_CFG__DPM_WAKE_MASK 0x400
+#define MC_PMG_CFG__DPM_WAKE__SHIFT 0xa
+#define MC_PMG_CFG__RFS_SRX_MASK 0x1000
+#define MC_PMG_CFG__RFS_SRX__SHIFT 0xc
+#define MC_PMG_CFG__PREA_SRX_MASK 0x2000
+#define MC_PMG_CFG__PREA_SRX__SHIFT 0xd
+#define MC_PMG_CFG__MRS_WAIT_CNT_MASK 0xf0000
+#define MC_PMG_CFG__MRS_WAIT_CNT__SHIFT 0x10
+#define MC_PMG_CFG__WRITE_DURING_DLOCK_MASK 0x100000
+#define MC_PMG_CFG__WRITE_DURING_DLOCK__SHIFT 0x14
+#define MC_PMG_CFG__YCLK_ON_MASK 0x200000
+#define MC_PMG_CFG__YCLK_ON__SHIFT 0x15
+#define MC_PMG_CFG__EARLY_ACK_ACPI_MASK 0x400000
+#define MC_PMG_CFG__EARLY_ACK_ACPI__SHIFT 0x16
+#define MC_PMG_CFG__RXPDNB_MASK 0x2000000
+#define MC_PMG_CFG__RXPDNB__SHIFT 0x19
+#define MC_PMG_CFG__ZQCL_SEND_MASK 0xc000000
+#define MC_PMG_CFG__ZQCL_SEND__SHIFT 0x1a
+#define MC_PMG_AUTO_CMD__ADR_MASK 0x1ffff
+#define MC_PMG_AUTO_CMD__ADR__SHIFT 0x0
+#define MC_PMG_AUTO_CMD__ADR_MSB1_MASK 0x10000000
+#define MC_PMG_AUTO_CMD__ADR_MSB1__SHIFT 0x1c
+#define MC_PMG_AUTO_CMD__ADR_MSB0_MASK 0x20000000
+#define MC_PMG_AUTO_CMD__ADR_MSB0__SHIFT 0x1d
+#define MC_PMG_AUTO_CFG__SYC_CLK_MASK 0x1
+#define MC_PMG_AUTO_CFG__SYC_CLK__SHIFT 0x0
+#define MC_PMG_AUTO_CFG__RST_MRS_MASK 0x2
+#define MC_PMG_AUTO_CFG__RST_MRS__SHIFT 0x1
+#define MC_PMG_AUTO_CFG__TRI_MIO_MASK 0x4
+#define MC_PMG_AUTO_CFG__TRI_MIO__SHIFT 0x2
+#define MC_PMG_AUTO_CFG__XSR_TMR_MASK 0xf0
+#define MC_PMG_AUTO_CFG__XSR_TMR__SHIFT 0x4
+#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF_MASK 0x100
+#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF__SHIFT 0x8
+#define MC_PMG_AUTO_CFG__SS_S_SLF_MASK 0x200
+#define MC_PMG_AUTO_CFG__SS_S_SLF__SHIFT 0x9
+#define MC_PMG_AUTO_CFG__SCDS_MODE_MASK 0x400
+#define MC_PMG_AUTO_CFG__SCDS_MODE__SHIFT 0xa
+#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP_MASK 0x800
+#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP__SHIFT 0xb
+#define MC_PMG_AUTO_CFG__RFS_SRX_MASK 0x1000
+#define MC_PMG_AUTO_CFG__RFS_SRX__SHIFT 0xc
+#define MC_PMG_AUTO_CFG__PREA_SRX_MASK 0x2000
+#define MC_PMG_AUTO_CFG__PREA_SRX__SHIFT 0xd
+#define MC_PMG_AUTO_CFG__STUTTER_EN_MASK 0x4000
+#define MC_PMG_AUTO_CFG__STUTTER_EN__SHIFT 0xe
+#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0_MASK 0x8000
+#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0__SHIFT 0xf
+#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT_MASK 0xf0000
+#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT__SHIFT 0x10
+#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK_MASK 0x100000
+#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK__SHIFT 0x14
+#define MC_PMG_AUTO_CFG__YCLK_ON_MASK 0x200000
+#define MC_PMG_AUTO_CFG__YCLK_ON__SHIFT 0x15
+#define MC_PMG_AUTO_CFG__RXPDNB_MASK 0x400000
+#define MC_PMG_AUTO_CFG__RXPDNB__SHIFT 0x16
+#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1_MASK 0x800000
+#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1__SHIFT 0x17
+#define MC_PMG_AUTO_CFG__DLL_CNT_MASK 0xff000000
+#define MC_PMG_AUTO_CFG__DLL_CNT__SHIFT 0x18
+#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE_MASK 0x1f
+#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE__SHIFT 0x0
+#define MC_IMP_CNTL__CAL_VREF_SEL_MASK 0x20
+#define MC_IMP_CNTL__CAL_VREF_SEL__SHIFT 0x5
+#define MC_IMP_CNTL__CAL_VREFMODE_MASK 0x40
+#define MC_IMP_CNTL__CAL_VREFMODE__SHIFT 0x6
+#define MC_IMP_CNTL__TIMEOUT_ERR_MASK 0x100
+#define MC_IMP_CNTL__TIMEOUT_ERR__SHIFT 0x8
+#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR_MASK 0x200
+#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR__SHIFT 0x9
+#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT_MASK 0xe000
+#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT__SHIFT 0xd
+#define MC_IMP_CNTL__CAL_VREF_MASK 0x7f0000
+#define MC_IMP_CNTL__CAL_VREF__SHIFT 0x10
+#define MC_IMP_CNTL__CAL_WHEN_IDLE_MASK 0x20000000
+#define MC_IMP_CNTL__CAL_WHEN_IDLE__SHIFT 0x1d
+#define MC_IMP_CNTL__CAL_WHEN_REFRESH_MASK 0x40000000
+#define MC_IMP_CNTL__CAL_WHEN_REFRESH__SHIFT 0x1e
+#define MC_IMP_CNTL__CAL_PWRON_MASK 0x80000000
+#define MC_IMP_CNTL__CAL_PWRON__SHIFT 0x1f
+#define MC_IMP_DEBUG__TSTARTUP_CNTR_MASK 0xff
+#define MC_IMP_DEBUG__TSTARTUP_CNTR__SHIFT 0x0
+#define MC_IMP_DEBUG__TIMEOUT_CNTR_MASK 0xff00
+#define MC_IMP_DEBUG__TIMEOUT_CNTR__SHIFT 0x8
+#define MC_IMP_DEBUG__PMVCAL_RESERVED_MASK 0xfff0000
+#define MC_IMP_DEBUG__PMVCAL_RESERVED__SHIFT 0x10
+#define MC_IMP_DEBUG__DEBUG_CAL_EN_MASK 0x10000000
+#define MC_IMP_DEBUG__DEBUG_CAL_EN__SHIFT 0x1c
+#define MC_IMP_DEBUG__DEBUG_CAL_START_MASK 0x20000000
+#define MC_IMP_DEBUG__DEBUG_CAL_START__SHIFT 0x1d
+#define MC_IMP_DEBUG__DEBUG_CAL_INTR_MASK 0x40000000
+#define MC_IMP_DEBUG__DEBUG_CAL_INTR__SHIFT 0x1e
+#define MC_IMP_DEBUG__DEBUG_CAL_DONE_MASK 0x80000000
+#define MC_IMP_DEBUG__DEBUG_CAL_DONE__SHIFT 0x1f
+#define MC_IMP_STATUS__PSTR_CAL_MASK 0xff
+#define MC_IMP_STATUS__PSTR_CAL__SHIFT 0x0
+#define MC_IMP_STATUS__PSTR_ACCUM_VAL_MASK 0xff00
+#define MC_IMP_STATUS__PSTR_ACCUM_VAL__SHIFT 0x8
+#define MC_IMP_STATUS__NSTR_CAL_MASK 0xff0000
+#define MC_IMP_STATUS__NSTR_CAL__SHIFT 0x10
+#define MC_IMP_STATUS__NSTR_ACCUM_VAL_MASK 0xff000000
+#define MC_IMP_STATUS__NSTR_ACCUM_VAL__SHIFT 0x18
+#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR_MASK 0xff
+#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR__SHIFT 0x0
+#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR_MASK 0xff00
+#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR__SHIFT 0x8
+#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR_MASK 0xff0000
+#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR__SHIFT 0x10
+#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR_MASK 0xff000000
+#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR__SHIFT 0x18
+#define MC_SEQ_WCDR_CTRL__WCDR_PRE_MASK 0xff
+#define MC_SEQ_WCDR_CTRL__WCDR_PRE__SHIFT 0x0
+#define MC_SEQ_WCDR_CTRL__WCDR_TIM_MASK 0xf00
+#define MC_SEQ_WCDR_CTRL__WCDR_TIM__SHIFT 0x8
+#define MC_SEQ_WCDR_CTRL__WR_EN_MASK 0x1000
+#define MC_SEQ_WCDR_CTRL__WR_EN__SHIFT 0xc
+#define MC_SEQ_WCDR_CTRL__RD_EN_MASK 0x2000
+#define MC_SEQ_WCDR_CTRL__RD_EN__SHIFT 0xd
+#define MC_SEQ_WCDR_CTRL__AREF_EN_MASK 0x4000
+#define MC_SEQ_WCDR_CTRL__AREF_EN__SHIFT 0xe
+#define MC_SEQ_WCDR_CTRL__TRAIN_EN_MASK 0x8000
+#define MC_SEQ_WCDR_CTRL__TRAIN_EN__SHIFT 0xf
+#define MC_SEQ_WCDR_CTRL__TWCDRL_MASK 0xf0000
+#define MC_SEQ_WCDR_CTRL__TWCDRL__SHIFT 0x10
+#define MC_SEQ_WCDR_CTRL__PRBS_EN_MASK 0x100000
+#define MC_SEQ_WCDR_CTRL__PRBS_EN__SHIFT 0x14
+#define MC_SEQ_WCDR_CTRL__PRBS_RST_MASK 0x200000
+#define MC_SEQ_WCDR_CTRL__PRBS_RST__SHIFT 0x15
+#define MC_SEQ_WCDR_CTRL__PREAMBLE_MASK 0xf000000
+#define MC_SEQ_WCDR_CTRL__PREAMBLE__SHIFT 0x18
+#define MC_SEQ_WCDR_CTRL__PRE_MASK_MASK 0xf0000000
+#define MC_SEQ_WCDR_CTRL__PRE_MASK__SHIFT 0x1c
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN_MASK 0x1
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN__SHIFT 0x0
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN_MASK 0x2
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN__SHIFT 0x1
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN_MASK 0x4
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN__SHIFT 0x2
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN_MASK 0x8
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN__SHIFT 0x3
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN_MASK 0x10
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN__SHIFT 0x4
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN_MASK 0x20
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN__SHIFT 0x5
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN_MASK 0x40
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN__SHIFT 0x6
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN_MASK 0x80
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN__SHIFT 0x7
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN_MASK 0x100
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN__SHIFT 0x8
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN_MASK 0x200
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN__SHIFT 0x9
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN_MASK 0x400
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN__SHIFT 0xa
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN_MASK 0x800
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN__SHIFT 0xb
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN_MASK 0x1000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN__SHIFT 0xc
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN_MASK 0x2000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN__SHIFT 0xd
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN_MASK 0x4000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN__SHIFT 0xe
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN_MASK 0x8000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN__SHIFT 0xf
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN_MASK 0x10000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN__SHIFT 0x10
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN_MASK 0x20000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN__SHIFT 0x11
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN_MASK 0x40000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN__SHIFT 0x12
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN_MASK 0x80000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN__SHIFT 0x13
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY_MASK 0x100000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY__SHIFT 0x14
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0_MASK 0x200000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0__SHIFT 0x15
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1_MASK 0x400000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1__SHIFT 0x16
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0_MASK 0x1000000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0__SHIFT 0x18
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0_MASK 0x2000000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0__SHIFT 0x19
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1_MASK 0x4000000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1__SHIFT 0x1a
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1_MASK 0x8000000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1__SHIFT 0x1b
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP_MASK 0x10000000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP__SHIFT 0x1c
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP_MASK 0x20000000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP__SHIFT 0x1d
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK 0x40000000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0__SHIFT 0x1e
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK 0x80000000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1__SHIFT 0x1f
+#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD_MASK 0xffff
+#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD__SHIFT 0x0
+#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD_MASK 0xffff0000
+#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD__SHIFT 0x10
+#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD_MASK 0xffffffff
+#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD__SHIFT 0x0
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS_MASK 0x1
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS__SHIFT 0x0
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS_MASK 0x2
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS__SHIFT 0x1
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS_MASK 0x4
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS__SHIFT 0x2
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI_MASK 0x8
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI__SHIFT 0x3
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR_MASK 0x30
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR__SHIFT 0x4
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS_MASK 0x100
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x8
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS_MASK 0x200
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x9
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP_MASK 0x1
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP__SHIFT 0x0
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP_MASK 0x2
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP__SHIFT 0x1
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP_MASK 0x4
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP__SHIFT 0x2
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP_MASK 0x8
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP__SHIFT 0x3
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP_MASK 0x10
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP__SHIFT 0x4
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP_MASK 0x20
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP__SHIFT 0x5
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP_MASK 0x80
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP_MASK 0x2000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP__SHIFT 0xd
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP_MASK 0x4000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP__SHIFT 0xe
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP_MASK 0x8000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP__SHIFT 0xf
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP_MASK 0x20000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP__SHIFT 0x11
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP_MASK 0x40000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP__SHIFT 0x12
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP_MASK 0x80000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP__SHIFT 0x13
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP_MASK 0x100000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP__SHIFT 0x14
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP_MASK 0x200000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP_MASK 0x400000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP_MASK 0x800000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP__SHIFT 0x17
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP_MASK 0x1000000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP__SHIFT 0x18
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP_MASK 0x2000000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP__SHIFT 0x19
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP_MASK 0x4000000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP__SHIFT 0x1a
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__SREG_WAKEUP_MASK 0x8000000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__SREG_WAKEUP__SHIFT 0x1b
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP_MASK 0x1
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP__SHIFT 0x0
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP_MASK 0x2
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP__SHIFT 0x1
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP_MASK 0x4
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP__SHIFT 0x2
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP_MASK 0x8
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP__SHIFT 0x3
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP_MASK 0x10
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP__SHIFT 0x4
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP_MASK 0x20
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP__SHIFT 0x5
+#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
+#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
+#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP_MASK 0x80
+#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
+#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
+#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP_MASK 0x2000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP__SHIFT 0xd
+#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP_MASK 0x4000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP__SHIFT 0xe
+#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP_MASK 0x8000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP__SHIFT 0xf
+#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP_MASK 0x20000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP__SHIFT 0x11
+#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP_MASK 0x40000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP__SHIFT 0x12
+#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP_MASK 0x80000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP__SHIFT 0x13
+#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP_MASK 0x100000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP__SHIFT 0x14
+#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP_MASK 0x200000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
+#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP_MASK 0x400000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
+#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP_MASK 0x800000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP__SHIFT 0x17
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP_MASK 0x1000000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP__SHIFT 0x18
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP_MASK 0x2000000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP__SHIFT 0x19
+#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP_MASK 0x4000000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP__SHIFT 0x1a
+#define MC_SEQ_TRAIN_WAKEUP_MASK__SREG_WAKEUP_MASK 0x8000000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__SREG_WAKEUP__SHIFT 0x1b
+#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP_MASK 0x1
+#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP__SHIFT 0x0
+#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP_MASK 0x2
+#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP__SHIFT 0x1
+#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP_MASK 0x4
+#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP__SHIFT 0x2
+#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP_MASK 0x8
+#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP__SHIFT 0x3
+#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP_MASK 0x10
+#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP__SHIFT 0x4
+#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP_MASK 0x20
+#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP__SHIFT 0x5
+#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
+#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
+#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP_MASK 0x80
+#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
+#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
+#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
+#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
+#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
+#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
+#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
+#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
+#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
+#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
+#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
+#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP_MASK 0x2000
+#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP__SHIFT 0xd
+#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP_MASK 0x4000
+#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP__SHIFT 0xe
+#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP_MASK 0x8000
+#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP__SHIFT 0xf
+#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP_MASK 0x20000
+#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP__SHIFT 0x11
+#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP_MASK 0x40000
+#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP__SHIFT 0x12
+#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP_MASK 0x80000
+#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP__SHIFT 0x13
+#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP_MASK 0x100000
+#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP__SHIFT 0x14
+#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP_MASK 0x200000
+#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
+#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP_MASK 0x400000
+#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
+#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP_MASK 0x800000
+#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP__SHIFT 0x17
+#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP_MASK 0x1000000
+#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP__SHIFT 0x18
+#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP_MASK 0x2000000
+#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP__SHIFT 0x19
+#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP_MASK 0x4000000
+#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP__SHIFT 0x1a
+#define MC_SEQ_TRAIN_CAPTURE__SREG_WAKEUP_MASK 0x8000000
+#define MC_SEQ_TRAIN_CAPTURE__SREG_WAKEUP__SHIFT 0x1b
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP_MASK 0x1
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP__SHIFT 0x0
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP_MASK 0x2
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP__SHIFT 0x1
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP_MASK 0x4
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP__SHIFT 0x2
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP_MASK 0x8
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP__SHIFT 0x3
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP_MASK 0x10
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP__SHIFT 0x4
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP_MASK 0x20
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP__SHIFT 0x5
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP_MASK 0x80
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP_MASK 0x2000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP__SHIFT 0xd
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP_MASK 0x4000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP__SHIFT 0xe
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP_MASK 0x8000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP__SHIFT 0xf
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL_MASK 0x10000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL__SHIFT 0x10
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP_MASK 0x20000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP__SHIFT 0x11
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP_MASK 0x40000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP__SHIFT 0x12
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP_MASK 0x80000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP__SHIFT 0x13
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP_MASK 0x100000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP__SHIFT 0x14
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP_MASK 0x200000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP_MASK 0x400000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP_MASK 0x800000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP__SHIFT 0x17
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP_MASK 0x1000000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP__SHIFT 0x18
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP_MASK 0x2000000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP__SHIFT 0x19
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP_MASK 0x4000000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP__SHIFT 0x1a
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SREG_WAKEUP_MASK 0x8000000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SREG_WAKEUP__SHIFT 0x1b
+#define MC_SEQ_TRAIN_TIMING__TWT2RT_MASK 0x1f
+#define MC_SEQ_TRAIN_TIMING__TWT2RT__SHIFT 0x0
+#define MC_SEQ_TRAIN_TIMING__TARF2T_MASK 0x3e0
+#define MC_SEQ_TRAIN_TIMING__TARF2T__SHIFT 0x5
+#define MC_SEQ_TRAIN_TIMING__TT2ROW_MASK 0x7c00
+#define MC_SEQ_TRAIN_TIMING__TT2ROW__SHIFT 0xa
+#define MC_SEQ_TRAIN_TIMING__TLD2LD_MASK 0xf8000
+#define MC_SEQ_TRAIN_TIMING__TLD2LD__SHIFT 0xf
+#define MC_TRAIN_EDCCDR_R_D0__EDC0_MASK 0xff
+#define MC_TRAIN_EDCCDR_R_D0__EDC0__SHIFT 0x0
+#define MC_TRAIN_EDCCDR_R_D0__EDC1_MASK 0xff00
+#define MC_TRAIN_EDCCDR_R_D0__EDC1__SHIFT 0x8
+#define MC_TRAIN_EDCCDR_R_D0__EDC2_MASK 0xff0000
+#define MC_TRAIN_EDCCDR_R_D0__EDC2__SHIFT 0x10
+#define MC_TRAIN_EDCCDR_R_D0__EDC3_MASK 0xff000000
+#define MC_TRAIN_EDCCDR_R_D0__EDC3__SHIFT 0x18
+#define MC_TRAIN_EDCCDR_R_D1__EDC0_MASK 0xff
+#define MC_TRAIN_EDCCDR_R_D1__EDC0__SHIFT 0x0
+#define MC_TRAIN_EDCCDR_R_D1__EDC1_MASK 0xff00
+#define MC_TRAIN_EDCCDR_R_D1__EDC1__SHIFT 0x8
+#define MC_TRAIN_EDCCDR_R_D1__EDC2_MASK 0xff0000
+#define MC_TRAIN_EDCCDR_R_D1__EDC2__SHIFT 0x10
+#define MC_TRAIN_EDCCDR_R_D1__EDC3_MASK 0xff000000
+#define MC_TRAIN_EDCCDR_R_D1__EDC3__SHIFT 0x18
+#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS_MASK 0xffffffff
+#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS__SHIFT 0x0
+#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS_MASK 0xf
+#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS__SHIFT 0x0
+#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS_MASK 0xf0
+#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS__SHIFT 0x4
+#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS_MASK 0xf00
+#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS__SHIFT 0x8
+#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS_MASK 0xf000
+#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS__SHIFT 0xc
+#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR_MASK 0x10000000
+#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR__SHIFT 0x1c
+#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR_MASK 0x20000000
+#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR__SHIFT 0x1d
+#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR_MASK 0x40000000
+#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR__SHIFT 0x1e
+#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS_MASK 0x1
+#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS__SHIFT 0x0
+#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS_MASK 0x2
+#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS__SHIFT 0x1
+#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS_MASK 0x30
+#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS__SHIFT 0x4
+#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS_MASK 0x100
+#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS__SHIFT 0x8
+#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS_MASK 0x200
+#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS__SHIFT 0x9
+#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS_MASK 0x400
+#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS__SHIFT 0xa
+#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS_MASK 0x800
+#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS__SHIFT 0xb
+#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS_MASK 0x3ff0000
+#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS__SHIFT 0x10
+#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS_MASK 0x10000000
+#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS__SHIFT 0x1c
+#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT_MASK 0xffff
+#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT__SHIFT 0x0
+#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT_MASK 0xffff0000
+#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT__SHIFT 0x10
+#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS_MASK 0xffffffff
+#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS__SHIFT 0x0
+#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS_MASK 0xf
+#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS__SHIFT 0x0
+#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS_MASK 0xf0
+#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS__SHIFT 0x4
+#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS_MASK 0xf00
+#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS__SHIFT 0x8
+#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS_MASK 0xf000
+#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS__SHIFT 0xc
+#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR_MASK 0x10000000
+#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR__SHIFT 0x1c
+#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR_MASK 0x20000000
+#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR__SHIFT 0x1d
+#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR_MASK 0x40000000
+#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR__SHIFT 0x1e
+#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS_MASK 0x1
+#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS__SHIFT 0x0
+#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS_MASK 0x2
+#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS__SHIFT 0x1
+#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS_MASK 0x30
+#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS__SHIFT 0x4
+#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS_MASK 0x100
+#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS__SHIFT 0x8
+#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS_MASK 0x200
+#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS__SHIFT 0x9
+#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS_MASK 0x400
+#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS__SHIFT 0xa
+#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS_MASK 0x800
+#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS__SHIFT 0xb
+#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS_MASK 0x3ff0000
+#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS__SHIFT 0x10
+#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS_MASK 0x10000000
+#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS__SHIFT 0x1c
+#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT_MASK 0xffff
+#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT__SHIFT 0x0
+#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT_MASK 0xffff0000
+#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT__SHIFT 0x10
+#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL_MASK 0x3
+#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL__SHIFT 0x0
+#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY_MASK 0xc
+#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY__SHIFT 0x2
+#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN_MASK 0x10
+#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN__SHIFT 0x4
+#define MC_IO_TXCNTL_DPHY0_D0__QDR_MASK 0x20
+#define MC_IO_TXCNTL_DPHY0_D0__QDR__SHIFT 0x5
+#define MC_IO_TXCNTL_DPHY0_D0__EMPH_MASK 0x40
+#define MC_IO_TXCNTL_DPHY0_D0__EMPH__SHIFT 0x6
+#define MC_IO_TXCNTL_DPHY0_D0__TXPD_MASK 0x80
+#define MC_IO_TXCNTL_DPHY0_D0__TXPD__SHIFT 0x7
+#define MC_IO_TXCNTL_DPHY0_D0__PTERM_MASK 0xf00
+#define MC_IO_TXCNTL_DPHY0_D0__PTERM__SHIFT 0x8
+#define MC_IO_TXCNTL_DPHY0_D0__NTERM_MASK 0xf000
+#define MC_IO_TXCNTL_DPHY0_D0__NTERM__SHIFT 0xc
+#define MC_IO_TXCNTL_DPHY0_D0__PDRV_MASK 0xf0000
+#define MC_IO_TXCNTL_DPHY0_D0__PDRV__SHIFT 0x10
+#define MC_IO_TXCNTL_DPHY0_D0__NDRV_MASK 0xf00000
+#define MC_IO_TXCNTL_DPHY0_D0__NDRV__SHIFT 0x14
+#define MC_IO_TXCNTL_DPHY0_D0__TSTEN_MASK 0x1000000
+#define MC_IO_TXCNTL_DPHY0_D0__TSTEN__SHIFT 0x18
+#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN_MASK 0x2000000
+#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN__SHIFT 0x19
+#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_MASK 0x4000000
+#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS__SHIFT 0x1a
+#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK_MASK 0x8000000
+#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK__SHIFT 0x1b
+#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA_MASK 0xf0000000
+#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA__SHIFT 0x1c
+#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL_MASK 0x3
+#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL__SHIFT 0x0
+#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY_MASK 0xc
+#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY__SHIFT 0x2
+#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN_MASK 0x10
+#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN__SHIFT 0x4
+#define MC_IO_TXCNTL_DPHY1_D0__QDR_MASK 0x20
+#define MC_IO_TXCNTL_DPHY1_D0__QDR__SHIFT 0x5
+#define MC_IO_TXCNTL_DPHY1_D0__EMPH_MASK 0x40
+#define MC_IO_TXCNTL_DPHY1_D0__EMPH__SHIFT 0x6
+#define MC_IO_TXCNTL_DPHY1_D0__TXPD_MASK 0x80
+#define MC_IO_TXCNTL_DPHY1_D0__TXPD__SHIFT 0x7
+#define MC_IO_TXCNTL_DPHY1_D0__PTERM_MASK 0xf00
+#define MC_IO_TXCNTL_DPHY1_D0__PTERM__SHIFT 0x8
+#define MC_IO_TXCNTL_DPHY1_D0__NTERM_MASK 0xf000
+#define MC_IO_TXCNTL_DPHY1_D0__NTERM__SHIFT 0xc
+#define MC_IO_TXCNTL_DPHY1_D0__PDRV_MASK 0xf0000
+#define MC_IO_TXCNTL_DPHY1_D0__PDRV__SHIFT 0x10
+#define MC_IO_TXCNTL_DPHY1_D0__NDRV_MASK 0xf00000
+#define MC_IO_TXCNTL_DPHY1_D0__NDRV__SHIFT 0x14
+#define MC_IO_TXCNTL_DPHY1_D0__TSTEN_MASK 0x1000000
+#define MC_IO_TXCNTL_DPHY1_D0__TSTEN__SHIFT 0x18
+#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN_MASK 0x2000000
+#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN__SHIFT 0x19
+#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_MASK 0x4000000
+#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS__SHIFT 0x1a
+#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK_MASK 0x8000000
+#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK__SHIFT 0x1b
+#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA_MASK 0xf0000000
+#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA__SHIFT 0x1c
+#define MC_IO_TXCNTL_APHY_D0__BIASSEL_MASK 0x3
+#define MC_IO_TXCNTL_APHY_D0__BIASSEL__SHIFT 0x0
+#define MC_IO_TXCNTL_APHY_D0__DRVDUTY_MASK 0xc
+#define MC_IO_TXCNTL_APHY_D0__DRVDUTY__SHIFT 0x2
+#define MC_IO_TXCNTL_APHY_D0__LOWCMEN_MASK 0x10
+#define MC_IO_TXCNTL_APHY_D0__LOWCMEN__SHIFT 0x4
+#define MC_IO_TXCNTL_APHY_D0__QDR_MASK 0x20
+#define MC_IO_TXCNTL_APHY_D0__QDR__SHIFT 0x5
+#define MC_IO_TXCNTL_APHY_D0__EMPH_MASK 0x40
+#define MC_IO_TXCNTL_APHY_D0__EMPH__SHIFT 0x6
+#define MC_IO_TXCNTL_APHY_D0__TXPD_MASK 0x80
+#define MC_IO_TXCNTL_APHY_D0__TXPD__SHIFT 0x7
+#define MC_IO_TXCNTL_APHY_D0__PTERM_MASK 0xf00
+#define MC_IO_TXCNTL_APHY_D0__PTERM__SHIFT 0x8
+#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL_MASK 0x1000
+#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL__SHIFT 0xc
+#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK_MASK 0xe000
+#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK__SHIFT 0xd
+#define MC_IO_TXCNTL_APHY_D0__PDRV_MASK 0xf0000
+#define MC_IO_TXCNTL_APHY_D0__PDRV__SHIFT 0x10
+#define MC_IO_TXCNTL_APHY_D0__NDRV_MASK 0x700000
+#define MC_IO_TXCNTL_APHY_D0__NDRV__SHIFT 0x14
+#define MC_IO_TXCNTL_APHY_D0__YCLKON_MASK 0x800000
+#define MC_IO_TXCNTL_APHY_D0__YCLKON__SHIFT 0x17
+#define MC_IO_TXCNTL_APHY_D0__TSTEN_MASK 0x1000000
+#define MC_IO_TXCNTL_APHY_D0__TSTEN__SHIFT 0x18
+#define MC_IO_TXCNTL_APHY_D0__TXRESET_MASK 0x2000000
+#define MC_IO_TXCNTL_APHY_D0__TXRESET__SHIFT 0x19
+#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_MASK 0x4000000
+#define MC_IO_TXCNTL_APHY_D0__TXBYPASS__SHIFT 0x1a
+#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA_MASK 0x38000000
+#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA__SHIFT 0x1b
+#define MC_IO_TXCNTL_APHY_D0__CKE_BIT_MASK 0x40000000
+#define MC_IO_TXCNTL_APHY_D0__CKE_BIT__SHIFT 0x1e
+#define MC_IO_TXCNTL_APHY_D0__CKE_SEL_MASK 0x80000000
+#define MC_IO_TXCNTL_APHY_D0__CKE_SEL__SHIFT 0x1f
+#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL_MASK 0x3
+#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL__SHIFT 0x0
+#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL_MASK 0x4
+#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL__SHIFT 0x2
+#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB_MASK 0x8
+#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB__SHIFT 0x3
+#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY_MASK 0x30
+#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY__SHIFT 0x4
+#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB_MASK 0x40
+#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB__SHIFT 0x6
+#define MC_IO_RXCNTL_DPHY0_D0__RXLP_MASK 0x80
+#define MC_IO_RXCNTL_DPHY0_D0__RXLP__SHIFT 0x7
+#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_MASK 0xf00
+#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL__SHIFT 0x8
+#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR_MASK 0xf000
+#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR__SHIFT 0xc
+#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL_MASK 0x10000
+#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL__SHIFT 0x10
+#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL_MASK 0xc0000
+#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL__SHIFT 0x12
+#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0_MASK 0x700000
+#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0__SHIFT 0x14
+#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1_MASK 0x7000000
+#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1__SHIFT 0x18
+#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M_MASK 0x10000000
+#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M__SHIFT 0x1c
+#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON_MASK 0x20000000
+#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON__SHIFT 0x1d
+#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL_MASK 0xc0000000
+#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL__SHIFT 0x1e
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB_MASK 0xf
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB__SHIFT 0x0
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB_MASK 0xf0
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB__SHIFT 0x4
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3_MASK 0xff00
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3__SHIFT 0x8
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2_MASK 0x10000
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2__SHIFT 0x10
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3_MASK 0x20000
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3__SHIFT 0x11
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1_MASK 0x40000
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1__SHIFT 0x12
+#define MC_IO_RXCNTL1_DPHY0_D0__DLL_PWRGOOD_OVR_MASK 0x80000
+#define MC_IO_RXCNTL1_DPHY0_D0__DLL_PWRGOOD_OVR__SHIFT 0x13
+#define MC_IO_RXCNTL1_DPHY0_D0__DLL_VCTRLADC_EN_MASK 0x100000
+#define MC_IO_RXCNTL1_DPHY0_D0__DLL_VCTRLADC_EN__SHIFT 0x14
+#define MC_IO_RXCNTL1_DPHY0_D0__DLL_MSTR_STBY_MASK 0x200000
+#define MC_IO_RXCNTL1_DPHY0_D0__DLL_MSTR_STBY__SHIFT 0x15
+#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_EN_MASK 0x400000
+#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_EN__SHIFT 0x16
+#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_NXT_MASK 0x800000
+#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_NXT__SHIFT 0x17
+#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK_MASK 0xe000000
+#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK__SHIFT 0x19
+#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV_MASK 0xf0000000
+#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV__SHIFT 0x1c
+#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL_MASK 0x3
+#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL__SHIFT 0x0
+#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL_MASK 0x4
+#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL__SHIFT 0x2
+#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB_MASK 0x8
+#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB__SHIFT 0x3
+#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY_MASK 0x30
+#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY__SHIFT 0x4
+#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB_MASK 0x40
+#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB__SHIFT 0x6
+#define MC_IO_RXCNTL_DPHY1_D0__RXLP_MASK 0x80
+#define MC_IO_RXCNTL_DPHY1_D0__RXLP__SHIFT 0x7
+#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_MASK 0xf00
+#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL__SHIFT 0x8
+#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR_MASK 0xf000
+#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR__SHIFT 0xc
+#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL_MASK 0x10000
+#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL__SHIFT 0x10
+#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL_MASK 0xc0000
+#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL__SHIFT 0x12
+#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0_MASK 0x700000
+#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0__SHIFT 0x14
+#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1_MASK 0x7000000
+#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1__SHIFT 0x18
+#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M_MASK 0x10000000
+#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M__SHIFT 0x1c
+#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON_MASK 0x20000000
+#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON__SHIFT 0x1d
+#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL_MASK 0xc0000000
+#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL__SHIFT 0x1e
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB_MASK 0xf
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB__SHIFT 0x0
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB_MASK 0xf0
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB__SHIFT 0x4
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3_MASK 0xff00
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3__SHIFT 0x8
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2_MASK 0x10000
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2__SHIFT 0x10
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3_MASK 0x20000
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3__SHIFT 0x11
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1_MASK 0x40000
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1__SHIFT 0x12
+#define MC_IO_RXCNTL1_DPHY1_D0__DLL_PWRGOOD_OVR_MASK 0x80000
+#define MC_IO_RXCNTL1_DPHY1_D0__DLL_PWRGOOD_OVR__SHIFT 0x13
+#define MC_IO_RXCNTL1_DPHY1_D0__DLL_VCTRLADC_EN_MASK 0x100000
+#define MC_IO_RXCNTL1_DPHY1_D0__DLL_VCTRLADC_EN__SHIFT 0x14
+#define MC_IO_RXCNTL1_DPHY1_D0__DLL_MSTR_STBY_MASK 0x200000
+#define MC_IO_RXCNTL1_DPHY1_D0__DLL_MSTR_STBY__SHIFT 0x15
+#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_EN_MASK 0x400000
+#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_EN__SHIFT 0x16
+#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_NXT_MASK 0x800000
+#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_NXT__SHIFT 0x17
+#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK_MASK 0xe000000
+#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK__SHIFT 0x19
+#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV_MASK 0xf0000000
+#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV__SHIFT 0x1c
+#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D_MASK 0x3f
+#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D__SHIFT 0x0
+#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D_MASK 0xfc0
+#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D__SHIFT 0x6
+#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S_MASK 0x3f000
+#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S__SHIFT 0xc
+#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S_MASK 0xfc0000
+#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S__SHIFT 0x12
+#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL_MASK 0x1000000
+#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL__SHIFT 0x18
+#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL_MASK 0x2000000
+#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL__SHIFT 0x19
+#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL_MASK 0xc000000
+#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x1a
+#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR_MASK 0x10000000
+#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR__SHIFT 0x1c
+#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR_MASK 0x20000000
+#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR__SHIFT 0x1d
+#define MC_IO_DPHY_STR_CNTL_D0__AUTO_LD_STR_MASK 0x40000000
+#define MC_IO_DPHY_STR_CNTL_D0__AUTO_LD_STR__SHIFT 0x1e
+#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A_MASK 0x3f
+#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A__SHIFT 0x0
+#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A_MASK 0xfc0
+#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A__SHIFT 0x6
+#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD_MASK 0x3f000
+#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD__SHIFT 0xc
+#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL_MASK 0x1000000
+#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL__SHIFT 0x18
+#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL_MASK 0x2000000
+#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL__SHIFT 0x19
+#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL_MASK 0xc000000
+#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x1a
+#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR_MASK 0x10000000
+#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR__SHIFT 0x1c
+#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR_MASK 0x20000000
+#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR__SHIFT 0x1d
+#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL_MASK 0x3
+#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL__SHIFT 0x0
+#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY_MASK 0xc
+#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY__SHIFT 0x2
+#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN_MASK 0x10
+#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN__SHIFT 0x4
+#define MC_IO_TXCNTL_DPHY0_D1__QDR_MASK 0x20
+#define MC_IO_TXCNTL_DPHY0_D1__QDR__SHIFT 0x5
+#define MC_IO_TXCNTL_DPHY0_D1__EMPH_MASK 0x40
+#define MC_IO_TXCNTL_DPHY0_D1__EMPH__SHIFT 0x6
+#define MC_IO_TXCNTL_DPHY0_D1__TXPD_MASK 0x80
+#define MC_IO_TXCNTL_DPHY0_D1__TXPD__SHIFT 0x7
+#define MC_IO_TXCNTL_DPHY0_D1__PTERM_MASK 0xf00
+#define MC_IO_TXCNTL_DPHY0_D1__PTERM__SHIFT 0x8
+#define MC_IO_TXCNTL_DPHY0_D1__NTERM_MASK 0xf000
+#define MC_IO_TXCNTL_DPHY0_D1__NTERM__SHIFT 0xc
+#define MC_IO_TXCNTL_DPHY0_D1__PDRV_MASK 0xf0000
+#define MC_IO_TXCNTL_DPHY0_D1__PDRV__SHIFT 0x10
+#define MC_IO_TXCNTL_DPHY0_D1__NDRV_MASK 0xf00000
+#define MC_IO_TXCNTL_DPHY0_D1__NDRV__SHIFT 0x14
+#define MC_IO_TXCNTL_DPHY0_D1__TSTEN_MASK 0x1000000
+#define MC_IO_TXCNTL_DPHY0_D1__TSTEN__SHIFT 0x18
+#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN_MASK 0x2000000
+#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN__SHIFT 0x19
+#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_MASK 0x4000000
+#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS__SHIFT 0x1a
+#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK_MASK 0x8000000
+#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK__SHIFT 0x1b
+#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA_MASK 0xf0000000
+#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA__SHIFT 0x1c
+#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL_MASK 0x3
+#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL__SHIFT 0x0
+#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY_MASK 0xc
+#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY__SHIFT 0x2
+#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN_MASK 0x10
+#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN__SHIFT 0x4
+#define MC_IO_TXCNTL_DPHY1_D1__QDR_MASK 0x20
+#define MC_IO_TXCNTL_DPHY1_D1__QDR__SHIFT 0x5
+#define MC_IO_TXCNTL_DPHY1_D1__EMPH_MASK 0x40
+#define MC_IO_TXCNTL_DPHY1_D1__EMPH__SHIFT 0x6
+#define MC_IO_TXCNTL_DPHY1_D1__TXPD_MASK 0x80
+#define MC_IO_TXCNTL_DPHY1_D1__TXPD__SHIFT 0x7
+#define MC_IO_TXCNTL_DPHY1_D1__PTERM_MASK 0xf00
+#define MC_IO_TXCNTL_DPHY1_D1__PTERM__SHIFT 0x8
+#define MC_IO_TXCNTL_DPHY1_D1__NTERM_MASK 0xf000
+#define MC_IO_TXCNTL_DPHY1_D1__NTERM__SHIFT 0xc
+#define MC_IO_TXCNTL_DPHY1_D1__PDRV_MASK 0xf0000
+#define MC_IO_TXCNTL_DPHY1_D1__PDRV__SHIFT 0x10
+#define MC_IO_TXCNTL_DPHY1_D1__NDRV_MASK 0xf00000
+#define MC_IO_TXCNTL_DPHY1_D1__NDRV__SHIFT 0x14
+#define MC_IO_TXCNTL_DPHY1_D1__TSTEN_MASK 0x1000000
+#define MC_IO_TXCNTL_DPHY1_D1__TSTEN__SHIFT 0x18
+#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN_MASK 0x2000000
+#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN__SHIFT 0x19
+#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_MASK 0x4000000
+#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS__SHIFT 0x1a
+#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK_MASK 0x8000000
+#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK__SHIFT 0x1b
+#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA_MASK 0xf0000000
+#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA__SHIFT 0x1c
+#define MC_IO_TXCNTL_APHY_D1__BIASSEL_MASK 0x3
+#define MC_IO_TXCNTL_APHY_D1__BIASSEL__SHIFT 0x0
+#define MC_IO_TXCNTL_APHY_D1__DRVDUTY_MASK 0xc
+#define MC_IO_TXCNTL_APHY_D1__DRVDUTY__SHIFT 0x2
+#define MC_IO_TXCNTL_APHY_D1__LOWCMEN_MASK 0x10
+#define MC_IO_TXCNTL_APHY_D1__LOWCMEN__SHIFT 0x4
+#define MC_IO_TXCNTL_APHY_D1__QDR_MASK 0x20
+#define MC_IO_TXCNTL_APHY_D1__QDR__SHIFT 0x5
+#define MC_IO_TXCNTL_APHY_D1__EMPH_MASK 0x40
+#define MC_IO_TXCNTL_APHY_D1__EMPH__SHIFT 0x6
+#define MC_IO_TXCNTL_APHY_D1__TXPD_MASK 0x80
+#define MC_IO_TXCNTL_APHY_D1__TXPD__SHIFT 0x7
+#define MC_IO_TXCNTL_APHY_D1__PTERM_MASK 0xf00
+#define MC_IO_TXCNTL_APHY_D1__PTERM__SHIFT 0x8
+#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL_MASK 0x1000
+#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL__SHIFT 0xc
+#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK_MASK 0xe000
+#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK__SHIFT 0xd
+#define MC_IO_TXCNTL_APHY_D1__PDRV_MASK 0xf0000
+#define MC_IO_TXCNTL_APHY_D1__PDRV__SHIFT 0x10
+#define MC_IO_TXCNTL_APHY_D1__NDRV_MASK 0x700000
+#define MC_IO_TXCNTL_APHY_D1__NDRV__SHIFT 0x14
+#define MC_IO_TXCNTL_APHY_D1__YCLKON_MASK 0x800000
+#define MC_IO_TXCNTL_APHY_D1__YCLKON__SHIFT 0x17
+#define MC_IO_TXCNTL_APHY_D1__TSTEN_MASK 0x1000000
+#define MC_IO_TXCNTL_APHY_D1__TSTEN__SHIFT 0x18
+#define MC_IO_TXCNTL_APHY_D1__TXRESET_MASK 0x2000000
+#define MC_IO_TXCNTL_APHY_D1__TXRESET__SHIFT 0x19
+#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_MASK 0x4000000
+#define MC_IO_TXCNTL_APHY_D1__TXBYPASS__SHIFT 0x1a
+#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA_MASK 0x38000000
+#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA__SHIFT 0x1b
+#define MC_IO_TXCNTL_APHY_D1__CKE_BIT_MASK 0x40000000
+#define MC_IO_TXCNTL_APHY_D1__CKE_BIT__SHIFT 0x1e
+#define MC_IO_TXCNTL_APHY_D1__CKE_SEL_MASK 0x80000000
+#define MC_IO_TXCNTL_APHY_D1__CKE_SEL__SHIFT 0x1f
+#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL_MASK 0x3
+#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL__SHIFT 0x0
+#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL_MASK 0x4
+#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL__SHIFT 0x2
+#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB_MASK 0x8
+#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB__SHIFT 0x3
+#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY_MASK 0x30
+#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY__SHIFT 0x4
+#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB_MASK 0x40
+#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB__SHIFT 0x6
+#define MC_IO_RXCNTL_DPHY0_D1__RXLP_MASK 0x80
+#define MC_IO_RXCNTL_DPHY0_D1__RXLP__SHIFT 0x7
+#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_MASK 0xf00
+#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL__SHIFT 0x8
+#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR_MASK 0xf000
+#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR__SHIFT 0xc
+#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL_MASK 0x10000
+#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL__SHIFT 0x10
+#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL_MASK 0xc0000
+#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL__SHIFT 0x12
+#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0_MASK 0x700000
+#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0__SHIFT 0x14
+#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1_MASK 0x7000000
+#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1__SHIFT 0x18
+#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M_MASK 0x10000000
+#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M__SHIFT 0x1c
+#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON_MASK 0x20000000
+#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON__SHIFT 0x1d
+#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL_MASK 0xc0000000
+#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL__SHIFT 0x1e
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB_MASK 0xf
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB__SHIFT 0x0
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB_MASK 0xf0
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB__SHIFT 0x4
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3_MASK 0xff00
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3__SHIFT 0x8
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2_MASK 0x10000
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2__SHIFT 0x10
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3_MASK 0x20000
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3__SHIFT 0x11
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1_MASK 0x40000
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1__SHIFT 0x12
+#define MC_IO_RXCNTL1_DPHY0_D1__DLL_PWRGOOD_OVR_MASK 0x80000
+#define MC_IO_RXCNTL1_DPHY0_D1__DLL_PWRGOOD_OVR__SHIFT 0x13
+#define MC_IO_RXCNTL1_DPHY0_D1__DLL_VCTRLADC_EN_MASK 0x100000
+#define MC_IO_RXCNTL1_DPHY0_D1__DLL_VCTRLADC_EN__SHIFT 0x14
+#define MC_IO_RXCNTL1_DPHY0_D1__DLL_MSTR_STBY_MASK 0x200000
+#define MC_IO_RXCNTL1_DPHY0_D1__DLL_MSTR_STBY__SHIFT 0x15
+#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_EN_MASK 0x400000
+#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_EN__SHIFT 0x16
+#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_NXT_MASK 0x800000
+#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_NXT__SHIFT 0x17
+#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK_MASK 0xe000000
+#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK__SHIFT 0x19
+#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV_MASK 0xf0000000
+#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV__SHIFT 0x1c
+#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL_MASK 0x3
+#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL__SHIFT 0x0
+#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL_MASK 0x4
+#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL__SHIFT 0x2
+#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB_MASK 0x8
+#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB__SHIFT 0x3
+#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY_MASK 0x30
+#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY__SHIFT 0x4
+#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB_MASK 0x40
+#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB__SHIFT 0x6
+#define MC_IO_RXCNTL_DPHY1_D1__RXLP_MASK 0x80
+#define MC_IO_RXCNTL_DPHY1_D1__RXLP__SHIFT 0x7
+#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_MASK 0xf00
+#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL__SHIFT 0x8
+#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR_MASK 0xf000
+#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR__SHIFT 0xc
+#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL_MASK 0x10000
+#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL__SHIFT 0x10
+#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL_MASK 0xc0000
+#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL__SHIFT 0x12
+#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0_MASK 0x700000
+#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0__SHIFT 0x14
+#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1_MASK 0x7000000
+#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1__SHIFT 0x18
+#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M_MASK 0x10000000
+#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M__SHIFT 0x1c
+#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON_MASK 0x20000000
+#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON__SHIFT 0x1d
+#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL_MASK 0xc0000000
+#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL__SHIFT 0x1e
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB_MASK 0xf
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB__SHIFT 0x0
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB_MASK 0xf0
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB__SHIFT 0x4
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3_MASK 0xff00
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3__SHIFT 0x8
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2_MASK 0x10000
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2__SHIFT 0x10
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3_MASK 0x20000
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3__SHIFT 0x11
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1_MASK 0x40000
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1__SHIFT 0x12
+#define MC_IO_RXCNTL1_DPHY1_D1__DLL_PWRGOOD_OVR_MASK 0x80000
+#define MC_IO_RXCNTL1_DPHY1_D1__DLL_PWRGOOD_OVR__SHIFT 0x13
+#define MC_IO_RXCNTL1_DPHY1_D1__DLL_VCTRLADC_EN_MASK 0x100000
+#define MC_IO_RXCNTL1_DPHY1_D1__DLL_VCTRLADC_EN__SHIFT 0x14
+#define MC_IO_RXCNTL1_DPHY1_D1__DLL_MSTR_STBY_MASK 0x200000
+#define MC_IO_RXCNTL1_DPHY1_D1__DLL_MSTR_STBY__SHIFT 0x15
+#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_EN_MASK 0x400000
+#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_EN__SHIFT 0x16
+#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_NXT_MASK 0x800000
+#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_NXT__SHIFT 0x17
+#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK_MASK 0xe000000
+#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK__SHIFT 0x19
+#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV_MASK 0xf0000000
+#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV__SHIFT 0x1c
+#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D_MASK 0x3f
+#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D__SHIFT 0x0
+#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D_MASK 0xfc0
+#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D__SHIFT 0x6
+#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S_MASK 0x3f000
+#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S__SHIFT 0xc
+#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S_MASK 0xfc0000
+#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S__SHIFT 0x12
+#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL_MASK 0x1000000
+#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL__SHIFT 0x18
+#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL_MASK 0x2000000
+#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL__SHIFT 0x19
+#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL_MASK 0xc000000
+#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x1a
+#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR_MASK 0x10000000
+#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR__SHIFT 0x1c
+#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR_MASK 0x20000000
+#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR__SHIFT 0x1d
+#define MC_IO_DPHY_STR_CNTL_D1__AUTO_LD_STR_MASK 0x40000000
+#define MC_IO_DPHY_STR_CNTL_D1__AUTO_LD_STR__SHIFT 0x1e
+#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A_MASK 0x3f
+#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A__SHIFT 0x0
+#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A_MASK 0xfc0
+#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A__SHIFT 0x6
+#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD_MASK 0x3f000
+#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD__SHIFT 0xc
+#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL_MASK 0x1000000
+#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL__SHIFT 0x18
+#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL_MASK 0x2000000
+#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL__SHIFT 0x19
+#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL_MASK 0xc000000
+#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x1a
+#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR_MASK 0x10000000
+#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR__SHIFT 0x1c
+#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR_MASK 0x20000000
+#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR__SHIFT 0x1d
+#define MC_IO_CDRCNTL_D0__RXPHASE_B01_MASK 0xf
+#define MC_IO_CDRCNTL_D0__RXPHASE_B01__SHIFT 0x0
+#define MC_IO_CDRCNTL_D0__RXPHASE_B23_MASK 0xf0
+#define MC_IO_CDRCNTL_D0__RXPHASE_B23__SHIFT 0x4
+#define MC_IO_CDRCNTL_D0__RXCDREN_B01_MASK 0x100
+#define MC_IO_CDRCNTL_D0__RXCDREN_B01__SHIFT 0x8
+#define MC_IO_CDRCNTL_D0__RXCDREN_B23_MASK 0x200
+#define MC_IO_CDRCNTL_D0__RXCDREN_B23__SHIFT 0x9
+#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01_MASK 0x400
+#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01__SHIFT 0xa
+#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23_MASK 0x800
+#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23__SHIFT 0xb
+#define MC_IO_CDRCNTL_D0__RXPHASE1_B01_MASK 0xf000
+#define MC_IO_CDRCNTL_D0__RXPHASE1_B01__SHIFT 0xc
+#define MC_IO_CDRCNTL_D0__RXPHASE1_B23_MASK 0xf0000
+#define MC_IO_CDRCNTL_D0__RXPHASE1_B23__SHIFT 0x10
+#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0_MASK 0x100000
+#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0__SHIFT 0x14
+#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1_MASK 0x200000
+#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1__SHIFT 0x15
+#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0_MASK 0x400000
+#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0__SHIFT 0x16
+#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1_MASK 0x800000
+#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1__SHIFT 0x17
+#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0_MASK 0x1000000
+#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0__SHIFT 0x18
+#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1_MASK 0x2000000
+#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1__SHIFT 0x19
+#define MC_IO_CDRCNTL_D0__WCDREDC_B0_MASK 0x4000000
+#define MC_IO_CDRCNTL_D0__WCDREDC_B0__SHIFT 0x1a
+#define MC_IO_CDRCNTL_D0__WCDREDC_B1_MASK 0x8000000
+#define MC_IO_CDRCNTL_D0__WCDREDC_B1__SHIFT 0x1b
+#define MC_IO_CDRCNTL_D0__DQRXSEL_B0_MASK 0x10000000
+#define MC_IO_CDRCNTL_D0__DQRXSEL_B0__SHIFT 0x1c
+#define MC_IO_CDRCNTL_D0__DQRXSEL_B1_MASK 0x20000000
+#define MC_IO_CDRCNTL_D0__DQRXSEL_B1__SHIFT 0x1d
+#define MC_IO_CDRCNTL_D0__DQTXSEL_B0_MASK 0x40000000
+#define MC_IO_CDRCNTL_D0__DQTXSEL_B0__SHIFT 0x1e
+#define MC_IO_CDRCNTL_D0__DQTXSEL_B1_MASK 0x80000000
+#define MC_IO_CDRCNTL_D0__DQTXSEL_B1__SHIFT 0x1f
+#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0_MASK 0xff
+#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0__SHIFT 0x0
+#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1_MASK 0xff00
+#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1__SHIFT 0x8
+#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0_MASK 0xff0000
+#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0__SHIFT 0x10
+#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1_MASK 0xff000000
+#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1__SHIFT 0x18
+#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0_MASK 0x1
+#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0__SHIFT 0x0
+#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1_MASK 0x2
+#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1__SHIFT 0x1
+#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0_MASK 0x4
+#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0__SHIFT 0x2
+#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1_MASK 0x8
+#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1__SHIFT 0x3
+#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0_MASK 0x10
+#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0__SHIFT 0x4
+#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1_MASK 0x20
+#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1__SHIFT 0x5
+#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0_MASK 0x40
+#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0__SHIFT 0x6
+#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1_MASK 0x80
+#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1__SHIFT 0x7
+#define MC_IO_CDRCNTL2_D0__WCDRTXPWRON_MASK 0xf00
+#define MC_IO_CDRCNTL2_D0__WCDRTXPWRON__SHIFT 0x8
+#define MC_IO_CDRCNTL2_D0__WCDRTXSEL_MASK 0xf000
+#define MC_IO_CDRCNTL2_D0__WCDRTXSEL__SHIFT 0xc
+#define MC_IO_CDRCNTL2_D0__WCDRTRACK01_MASK 0xf0000
+#define MC_IO_CDRCNTL2_D0__WCDRTRACK01__SHIFT 0x10
+#define MC_IO_CDRCNTL_D1__RXPHASE_B01_MASK 0xf
+#define MC_IO_CDRCNTL_D1__RXPHASE_B01__SHIFT 0x0
+#define MC_IO_CDRCNTL_D1__RXPHASE_B23_MASK 0xf0
+#define MC_IO_CDRCNTL_D1__RXPHASE_B23__SHIFT 0x4
+#define MC_IO_CDRCNTL_D1__RXCDREN_B01_MASK 0x100
+#define MC_IO_CDRCNTL_D1__RXCDREN_B01__SHIFT 0x8
+#define MC_IO_CDRCNTL_D1__RXCDREN_B23_MASK 0x200
+#define MC_IO_CDRCNTL_D1__RXCDREN_B23__SHIFT 0x9
+#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01_MASK 0x400
+#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01__SHIFT 0xa
+#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23_MASK 0x800
+#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23__SHIFT 0xb
+#define MC_IO_CDRCNTL_D1__RXPHASE1_B01_MASK 0xf000
+#define MC_IO_CDRCNTL_D1__RXPHASE1_B01__SHIFT 0xc
+#define MC_IO_CDRCNTL_D1__RXPHASE1_B23_MASK 0xf0000
+#define MC_IO_CDRCNTL_D1__RXPHASE1_B23__SHIFT 0x10
+#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0_MASK 0x100000
+#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0__SHIFT 0x14
+#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1_MASK 0x200000
+#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1__SHIFT 0x15
+#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0_MASK 0x400000
+#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0__SHIFT 0x16
+#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1_MASK 0x800000
+#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1__SHIFT 0x17
+#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0_MASK 0x1000000
+#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0__SHIFT 0x18
+#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1_MASK 0x2000000
+#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1__SHIFT 0x19
+#define MC_IO_CDRCNTL_D1__WCDREDC_B0_MASK 0x4000000
+#define MC_IO_CDRCNTL_D1__WCDREDC_B0__SHIFT 0x1a
+#define MC_IO_CDRCNTL_D1__WCDREDC_B1_MASK 0x8000000
+#define MC_IO_CDRCNTL_D1__WCDREDC_B1__SHIFT 0x1b
+#define MC_IO_CDRCNTL_D1__DQRXSEL_B0_MASK 0x10000000
+#define MC_IO_CDRCNTL_D1__DQRXSEL_B0__SHIFT 0x1c
+#define MC_IO_CDRCNTL_D1__DQRXSEL_B1_MASK 0x20000000
+#define MC_IO_CDRCNTL_D1__DQRXSEL_B1__SHIFT 0x1d
+#define MC_IO_CDRCNTL_D1__DQTXSEL_B0_MASK 0x40000000
+#define MC_IO_CDRCNTL_D1__DQTXSEL_B0__SHIFT 0x1e
+#define MC_IO_CDRCNTL_D1__DQTXSEL_B1_MASK 0x80000000
+#define MC_IO_CDRCNTL_D1__DQTXSEL_B1__SHIFT 0x1f
+#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0_MASK 0xff
+#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0__SHIFT 0x0
+#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1_MASK 0xff00
+#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1__SHIFT 0x8
+#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0_MASK 0xff0000
+#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0__SHIFT 0x10
+#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1_MASK 0xff000000
+#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1__SHIFT 0x18
+#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0_MASK 0x1
+#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0__SHIFT 0x0
+#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1_MASK 0x2
+#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1__SHIFT 0x1
+#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0_MASK 0x4
+#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0__SHIFT 0x2
+#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1_MASK 0x8
+#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1__SHIFT 0x3
+#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0_MASK 0x10
+#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0__SHIFT 0x4
+#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1_MASK 0x20
+#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1__SHIFT 0x5
+#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0_MASK 0x40
+#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0__SHIFT 0x6
+#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1_MASK 0x80
+#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1__SHIFT 0x7
+#define MC_IO_CDRCNTL2_D1__WCDRTXPWRON_MASK 0xf00
+#define MC_IO_CDRCNTL2_D1__WCDRTXPWRON__SHIFT 0x8
+#define MC_IO_CDRCNTL2_D1__WCDRTXSEL_MASK 0xf000
+#define MC_IO_CDRCNTL2_D1__WCDRTXSEL__SHIFT 0xc
+#define MC_IO_CDRCNTL2_D1__WCDRTRACK01_MASK 0xf0000
+#define MC_IO_CDRCNTL2_D1__WCDRTRACK01__SHIFT 0x10
+#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0_MASK 0x3
+#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0__SHIFT 0x0
+#define MC_SEQ_FIFO_CTL__W_SYC_SEL_MASK 0xc
+#define MC_SEQ_FIFO_CTL__W_SYC_SEL__SHIFT 0x2
+#define MC_SEQ_FIFO_CTL__R_LD_INIT_MASK 0x30
+#define MC_SEQ_FIFO_CTL__R_LD_INIT__SHIFT 0x4
+#define MC_SEQ_FIFO_CTL__R_SYC_SEL_MASK 0xc0
+#define MC_SEQ_FIFO_CTL__R_SYC_SEL__SHIFT 0x6
+#define MC_SEQ_FIFO_CTL__CG_DIS_D0_MASK 0x100
+#define MC_SEQ_FIFO_CTL__CG_DIS_D0__SHIFT 0x8
+#define MC_SEQ_FIFO_CTL__CG_DIS_D1_MASK 0x200
+#define MC_SEQ_FIFO_CTL__CG_DIS_D1__SHIFT 0x9
+#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1_MASK 0xc00
+#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1__SHIFT 0xa
+#define MC_SEQ_FIFO_CTL__SYC_DLY_MASK 0x7000
+#define MC_SEQ_FIFO_CTL__SYC_DLY__SHIFT 0xc
+#define MC_SEQ_FIFO_CTL__W_ASYC_EXT_MASK 0x30000
+#define MC_SEQ_FIFO_CTL__W_ASYC_EXT__SHIFT 0x10
+#define MC_SEQ_FIFO_CTL__W_DSYC_EXT_MASK 0xc0000
+#define MC_SEQ_FIFO_CTL__W_DSYC_EXT__SHIFT 0x12
+#define MC_SEQ_FIFO_CTL__R_DQS_LD_INIT_MASK 0xf00000
+#define MC_SEQ_FIFO_CTL__R_DQS_LD_INIT__SHIFT 0x14
+#define MC_SEQ_FIFO_CTL__R_DQS_STEP_MASK 0xf000000
+#define MC_SEQ_FIFO_CTL__R_DQS_STEP__SHIFT 0x18
+#define MC_SEQ_FIFO_CTL__R_DQS_FRC_MASK 0x10000000
+#define MC_SEQ_FIFO_CTL__R_DQS_FRC__SHIFT 0x1c
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0_MASK 0xf
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4_MASK 0xf0000
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4__SHIFT 0x10
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5_MASK 0xf00000
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5__SHIFT 0x14
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6_MASK 0xf000000
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6__SHIFT 0x18
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7__SHIFT 0x1c
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0_MASK 0xf
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4_MASK 0xf0000
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4__SHIFT 0x10
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5_MASK 0xf00000
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5__SHIFT 0x14
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6_MASK 0xf000000
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6__SHIFT 0x18
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7__SHIFT 0x1c
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0_MASK 0xf
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4_MASK 0xf0000
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4__SHIFT 0x10
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5_MASK 0xf00000
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5__SHIFT 0x14
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6_MASK 0xf000000
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6__SHIFT 0x18
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7__SHIFT 0x1c
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0_MASK 0xf
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4_MASK 0xf0000
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4__SHIFT 0x10
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5_MASK 0xf00000
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5__SHIFT 0x14
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6_MASK 0xf000000
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6__SHIFT 0x18
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7__SHIFT 0x1c
+#define MC_SEQ_TXFRAMING_DBI_D0__DBI0_MASK 0xf
+#define MC_SEQ_TXFRAMING_DBI_D0__DBI0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_DBI_D0__DBI1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_DBI_D0__DBI1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_DBI_D0__DBI2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_DBI_D0__DBI2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_DBI_D0__DBI3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_DBI_D0__DBI3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_EDC_D0__EDC0_MASK 0xf
+#define MC_SEQ_TXFRAMING_EDC_D0__EDC0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_EDC_D0__EDC1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_EDC_D0__EDC1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_EDC_D0__EDC2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_EDC_D0__EDC2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_EDC_D0__EDC3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_EDC_D0__EDC3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0_MASK 0xf0000
+#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0__SHIFT 0x10
+#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1_MASK 0xf00000
+#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1__SHIFT 0x14
+#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2_MASK 0xf000000
+#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2__SHIFT 0x18
+#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000
+#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3__SHIFT 0x1c
+#define MC_SEQ_TXFRAMING_FCK_D0__FCK0_MASK 0xf
+#define MC_SEQ_TXFRAMING_FCK_D0__FCK0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_FCK_D0__FCK1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_FCK_D0__FCK1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_FCK_D0__FCK2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_FCK_D0__FCK2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_FCK_D0__FCK3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_FCK_D0__FCK3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0_MASK 0xf
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4_MASK 0xf0000
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4__SHIFT 0x10
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5_MASK 0xf00000
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5__SHIFT 0x14
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6_MASK 0xf000000
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6__SHIFT 0x18
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7__SHIFT 0x1c
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0_MASK 0xf
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4_MASK 0xf0000
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4__SHIFT 0x10
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5_MASK 0xf00000
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5__SHIFT 0x14
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6_MASK 0xf000000
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6__SHIFT 0x18
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7__SHIFT 0x1c
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0_MASK 0xf
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4_MASK 0xf0000
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4__SHIFT 0x10
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5_MASK 0xf00000
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5__SHIFT 0x14
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6_MASK 0xf000000
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6__SHIFT 0x18
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7__SHIFT 0x1c
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0_MASK 0xf
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4_MASK 0xf0000
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4__SHIFT 0x10
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5_MASK 0xf00000
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5__SHIFT 0x14
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6_MASK 0xf000000
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6__SHIFT 0x18
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7__SHIFT 0x1c
+#define MC_SEQ_TXFRAMING_DBI_D1__DBI0_MASK 0xf
+#define MC_SEQ_TXFRAMING_DBI_D1__DBI0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_DBI_D1__DBI1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_DBI_D1__DBI1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_DBI_D1__DBI2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_DBI_D1__DBI2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_DBI_D1__DBI3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_DBI_D1__DBI3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_EDC_D1__EDC0_MASK 0xf
+#define MC_SEQ_TXFRAMING_EDC_D1__EDC0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_EDC_D1__EDC1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_EDC_D1__EDC1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_EDC_D1__EDC2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_EDC_D1__EDC2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_EDC_D1__EDC3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_EDC_D1__EDC3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0_MASK 0xf0000
+#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0__SHIFT 0x10
+#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1_MASK 0xf00000
+#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1__SHIFT 0x14
+#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2_MASK 0xf000000
+#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2__SHIFT 0x18
+#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000
+#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3__SHIFT 0x1c
+#define MC_SEQ_TXFRAMING_FCK_D1__FCK0_MASK 0xf
+#define MC_SEQ_TXFRAMING_FCK_D1__FCK0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_FCK_D1__FCK1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_FCK_D1__FCK1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_FCK_D1__FCK2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_FCK_D1__FCK2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_FCK_D1__FCK3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_FCK_D1__FCK3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0_MASK 0xf
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4_MASK 0xf0000
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4__SHIFT 0x10
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5_MASK 0xf00000
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5__SHIFT 0x14
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6_MASK 0xf000000
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6__SHIFT 0x18
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7__SHIFT 0x1c
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0_MASK 0xf
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4_MASK 0xf0000
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4__SHIFT 0x10
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5_MASK 0xf00000
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5__SHIFT 0x14
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6_MASK 0xf000000
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6__SHIFT 0x18
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7__SHIFT 0x1c
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0_MASK 0xf
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4_MASK 0xf0000
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4__SHIFT 0x10
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5_MASK 0xf00000
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5__SHIFT 0x14
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6_MASK 0xf000000
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6__SHIFT 0x18
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7__SHIFT 0x1c
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0_MASK 0xf
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4_MASK 0xf0000
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4__SHIFT 0x10
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5_MASK 0xf00000
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5__SHIFT 0x14
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6_MASK 0xf000000
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6__SHIFT 0x18
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7__SHIFT 0x1c
+#define MC_SEQ_RXFRAMING_DBI_D0__DBI0_MASK 0xf
+#define MC_SEQ_RXFRAMING_DBI_D0__DBI0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_DBI_D0__DBI1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_DBI_D0__DBI1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_DBI_D0__DBI2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_DBI_D0__DBI2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_DBI_D0__DBI3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_DBI_D0__DBI3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_EDC_D0__EDC0_MASK 0xf
+#define MC_SEQ_RXFRAMING_EDC_D0__EDC0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_EDC_D0__EDC1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_EDC_D0__EDC1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_EDC_D0__EDC2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_EDC_D0__EDC2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_EDC_D0__EDC3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_EDC_D0__EDC3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0_MASK 0xf0000
+#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0__SHIFT 0x10
+#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1_MASK 0xf00000
+#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1__SHIFT 0x14
+#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2_MASK 0xf000000
+#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2__SHIFT 0x18
+#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000
+#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3__SHIFT 0x1c
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0_MASK 0xf
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4_MASK 0xf0000
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4__SHIFT 0x10
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5_MASK 0xf00000
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5__SHIFT 0x14
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6_MASK 0xf000000
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6__SHIFT 0x18
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7__SHIFT 0x1c
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0_MASK 0xf
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4_MASK 0xf0000
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4__SHIFT 0x10
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5_MASK 0xf00000
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5__SHIFT 0x14
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6_MASK 0xf000000
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6__SHIFT 0x18
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7__SHIFT 0x1c
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0_MASK 0xf
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4_MASK 0xf0000
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4__SHIFT 0x10
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5_MASK 0xf00000
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5__SHIFT 0x14
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6_MASK 0xf000000
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6__SHIFT 0x18
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7__SHIFT 0x1c
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0_MASK 0xf
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4_MASK 0xf0000
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4__SHIFT 0x10
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5_MASK 0xf00000
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5__SHIFT 0x14
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6_MASK 0xf000000
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6__SHIFT 0x18
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7__SHIFT 0x1c
+#define MC_SEQ_RXFRAMING_DBI_D1__DBI0_MASK 0xf
+#define MC_SEQ_RXFRAMING_DBI_D1__DBI0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_DBI_D1__DBI1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_DBI_D1__DBI1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_DBI_D1__DBI2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_DBI_D1__DBI2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_DBI_D1__DBI3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_DBI_D1__DBI3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_EDC_D1__EDC0_MASK 0xf
+#define MC_SEQ_RXFRAMING_EDC_D1__EDC0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_EDC_D1__EDC1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_EDC_D1__EDC1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_EDC_D1__EDC2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_EDC_D1__EDC2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_EDC_D1__EDC3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_EDC_D1__EDC3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0_MASK 0xf0000
+#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0__SHIFT 0x10
+#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1_MASK 0xf00000
+#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1__SHIFT 0x14
+#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2_MASK 0xf000000
+#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2__SHIFT 0x18
+#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000
+#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3__SHIFT 0x1c
+#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN_MASK 0xff
+#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN__SHIFT 0x0
+#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX_MASK 0xff00
+#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX__SHIFT 0x8
+#define MC_IO_PAD_CNTL__TXPHASE_GRAY_MASK 0x10000
+#define MC_IO_PAD_CNTL__TXPHASE_GRAY__SHIFT 0x10
+#define MC_IO_PAD_CNTL__RXPHASE_GRAY_MASK 0x20000
+#define MC_IO_PAD_CNTL__RXPHASE_GRAY__SHIFT 0x11
+#define MC_IO_PAD_CNTL__OVL_YCLKON_D0_MASK 0x40000
+#define MC_IO_PAD_CNTL__OVL_YCLKON_D0__SHIFT 0x12
+#define MC_IO_PAD_CNTL__OVL_YCLKON_D1_MASK 0x80000
+#define MC_IO_PAD_CNTL__OVL_YCLKON_D1__SHIFT 0x13
+#define MC_IO_PAD_CNTL__ATBSEL_MASK 0xf00000
+#define MC_IO_PAD_CNTL__ATBSEL__SHIFT 0x14
+#define MC_IO_PAD_CNTL__ATBEN_MASK 0x3f000000
+#define MC_IO_PAD_CNTL__ATBEN__SHIFT 0x18
+#define MC_IO_PAD_CNTL__ATBSEL_D1_MASK 0x40000000
+#define MC_IO_PAD_CNTL__ATBSEL_D1__SHIFT 0x1e
+#define MC_IO_PAD_CNTL__ATBSEL_D0_MASK 0x80000000
+#define MC_IO_PAD_CNTL__ATBSEL_D0__SHIFT 0x1f
+#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC_MASK 0x4
+#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC__SHIFT 0x2
+#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC_MASK 0x8
+#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC__SHIFT 0x3
+#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC_MASK 0x10
+#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC__SHIFT 0x4
+#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK_MASK 0x80
+#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK__SHIFT 0x7
+#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD_MASK 0x100
+#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD__SHIFT 0x8
+#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR_MASK 0x200
+#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR__SHIFT 0x9
+#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR_MASK 0x400
+#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR__SHIFT 0xa
+#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY_MASK 0x800
+#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY__SHIFT 0xb
+#define MC_IO_PAD_CNTL_D0__DISABLE_CMD_MASK 0x1000
+#define MC_IO_PAD_CNTL_D0__DISABLE_CMD__SHIFT 0xc
+#define MC_IO_PAD_CNTL_D0__DISABLE_ADR_MASK 0x2000
+#define MC_IO_PAD_CNTL_D0__DISABLE_ADR__SHIFT 0xd
+#define MC_IO_PAD_CNTL_D0__VREFI_EN_MASK 0x4000
+#define MC_IO_PAD_CNTL_D0__VREFI_EN__SHIFT 0xe
+#define MC_IO_PAD_CNTL_D0__VREFI_SEL_MASK 0xf8000
+#define MC_IO_PAD_CNTL_D0__VREFI_SEL__SHIFT 0xf
+#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN_MASK 0x100000
+#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN__SHIFT 0x14
+#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL_MASK 0x200000
+#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL__SHIFT 0x15
+#define MC_IO_PAD_CNTL_D0__CK_DELAY_N_MASK 0xc00000
+#define MC_IO_PAD_CNTL_D0__CK_DELAY_N__SHIFT 0x16
+#define MC_IO_PAD_CNTL_D0__CK_DELAY_P_MASK 0x3000000
+#define MC_IO_PAD_CNTL_D0__CK_DELAY_P__SHIFT 0x18
+#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE_MASK 0x8000000
+#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE__SHIFT 0x1b
+#define MC_IO_PAD_CNTL_D0__UNI_STR_MASK 0x10000000
+#define MC_IO_PAD_CNTL_D0__UNI_STR__SHIFT 0x1c
+#define MC_IO_PAD_CNTL_D0__DIFF_STR_MASK 0x20000000
+#define MC_IO_PAD_CNTL_D0__DIFF_STR__SHIFT 0x1d
+#define MC_IO_PAD_CNTL_D0__GDDR_PWRON_MASK 0x40000000
+#define MC_IO_PAD_CNTL_D0__GDDR_PWRON__SHIFT 0x1e
+#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK_MASK 0x80000000
+#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK__SHIFT 0x1f
+#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC_MASK 0x1
+#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC__SHIFT 0x0
+#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC_MASK 0x2
+#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC__SHIFT 0x1
+#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC_MASK 0x4
+#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC__SHIFT 0x2
+#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC_MASK 0x8
+#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC__SHIFT 0x3
+#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC_MASK 0x10
+#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC__SHIFT 0x4
+#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA_MASK 0x20
+#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA__SHIFT 0x5
+#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR_MASK 0x40
+#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR__SHIFT 0x6
+#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK_MASK 0x80
+#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK__SHIFT 0x7
+#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD_MASK 0x100
+#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD__SHIFT 0x8
+#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR_MASK 0x200
+#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR__SHIFT 0x9
+#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR_MASK 0x400
+#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR__SHIFT 0xa
+#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY_MASK 0x800
+#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY__SHIFT 0xb
+#define MC_IO_PAD_CNTL_D1__DISABLE_CMD_MASK 0x1000
+#define MC_IO_PAD_CNTL_D1__DISABLE_CMD__SHIFT 0xc
+#define MC_IO_PAD_CNTL_D1__DISABLE_ADR_MASK 0x2000
+#define MC_IO_PAD_CNTL_D1__DISABLE_ADR__SHIFT 0xd
+#define MC_IO_PAD_CNTL_D1__VREFI_EN_MASK 0x4000
+#define MC_IO_PAD_CNTL_D1__VREFI_EN__SHIFT 0xe
+#define MC_IO_PAD_CNTL_D1__VREFI_SEL_MASK 0xf8000
+#define MC_IO_PAD_CNTL_D1__VREFI_SEL__SHIFT 0xf
+#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN_MASK 0x100000
+#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN__SHIFT 0x14
+#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL_MASK 0x200000
+#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL__SHIFT 0x15
+#define MC_IO_PAD_CNTL_D1__CK_DELAY_N_MASK 0xc00000
+#define MC_IO_PAD_CNTL_D1__CK_DELAY_N__SHIFT 0x16
+#define MC_IO_PAD_CNTL_D1__CK_DELAY_P_MASK 0x3000000
+#define MC_IO_PAD_CNTL_D1__CK_DELAY_P__SHIFT 0x18
+#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE_MASK 0x8000000
+#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE__SHIFT 0x1b
+#define MC_IO_PAD_CNTL_D1__UNI_STR_MASK 0x10000000
+#define MC_IO_PAD_CNTL_D1__UNI_STR__SHIFT 0x1c
+#define MC_IO_PAD_CNTL_D1__DIFF_STR_MASK 0x20000000
+#define MC_IO_PAD_CNTL_D1__DIFF_STR__SHIFT 0x1d
+#define MC_IO_PAD_CNTL_D1__GDDR_PWRON_MASK 0x40000000
+#define MC_IO_PAD_CNTL_D1__GDDR_PWRON__SHIFT 0x1e
+#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK_MASK 0x80000000
+#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK__SHIFT 0x1f
+#define MC_NPL_STATUS__D0_PDELAY_MASK 0x3
+#define MC_NPL_STATUS__D0_PDELAY__SHIFT 0x0
+#define MC_NPL_STATUS__D0_NDELAY_MASK 0xc
+#define MC_NPL_STATUS__D0_NDELAY__SHIFT 0x2
+#define MC_NPL_STATUS__D0_PEARLY_MASK 0x10
+#define MC_NPL_STATUS__D0_PEARLY__SHIFT 0x4
+#define MC_NPL_STATUS__D0_NEARLY_MASK 0x20
+#define MC_NPL_STATUS__D0_NEARLY__SHIFT 0x5
+#define MC_NPL_STATUS__D1_PDELAY_MASK 0xc0
+#define MC_NPL_STATUS__D1_PDELAY__SHIFT 0x6
+#define MC_NPL_STATUS__D1_NDELAY_MASK 0x300
+#define MC_NPL_STATUS__D1_NDELAY__SHIFT 0x8
+#define MC_NPL_STATUS__D1_PEARLY_MASK 0x400
+#define MC_NPL_STATUS__D1_PEARLY__SHIFT 0xa
+#define MC_NPL_STATUS__D1_NEARLY_MASK 0x800
+#define MC_NPL_STATUS__D1_NEARLY__SHIFT 0xb
+#define MC_BIST_CMD_CNTL__RESET_MASK 0x1
+#define MC_BIST_CMD_CNTL__RESET__SHIFT 0x0
+#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_MASK 0x2
+#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE__SHIFT 0x1
+#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP_MASK 0x4
+#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP__SHIFT 0x2
+#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION_MASK 0x8
+#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION__SHIFT 0x3
+#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX_MASK 0xfff0
+#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX__SHIFT 0x4
+#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U_MASK 0x10000
+#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U__SHIFT 0x10
+#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN_MASK 0x20000
+#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN__SHIFT 0x11
+#define MC_BIST_CMD_CNTL__LOOP_CNT_RD_MASK 0xffc0000
+#define MC_BIST_CMD_CNTL__LOOP_CNT_RD__SHIFT 0x12
+#define MC_BIST_CMD_CNTL__ENABLE_D0_MASK 0x10000000
+#define MC_BIST_CMD_CNTL__ENABLE_D0__SHIFT 0x1c
+#define MC_BIST_CMD_CNTL__ENABLE_D1_MASK 0x20000000
+#define MC_BIST_CMD_CNTL__ENABLE_D1__SHIFT 0x1d
+#define MC_BIST_CMD_CNTL__STATUS_CH_MASK 0x40000000
+#define MC_BIST_CMD_CNTL__STATUS_CH__SHIFT 0x1e
+#define MC_BIST_CMD_CNTL__DONE_MASK 0x80000000
+#define MC_BIST_CMD_CNTL__DONE__SHIFT 0x1f
+#define MC_BIST_CNTL__RESET_MASK 0x1
+#define MC_BIST_CNTL__RESET__SHIFT 0x0
+#define MC_BIST_CNTL__RUN_MASK 0x2
+#define MC_BIST_CNTL__RUN__SHIFT 0x1
+#define MC_BIST_CNTL__PTR_RST_D0_MASK 0x4
+#define MC_BIST_CNTL__PTR_RST_D0__SHIFT 0x2
+#define MC_BIST_CNTL__PTR_RST_D1_MASK 0x8
+#define MC_BIST_CNTL__PTR_RST_D1__SHIFT 0x3
+#define MC_BIST_CNTL__MOP_MODE_MASK 0x10
+#define MC_BIST_CNTL__MOP_MODE__SHIFT 0x4
+#define MC_BIST_CNTL__ADR_MODE_MASK 0x20
+#define MC_BIST_CNTL__ADR_MODE__SHIFT 0x5
+#define MC_BIST_CNTL__DAT_MODE_MASK 0x40
+#define MC_BIST_CNTL__DAT_MODE__SHIFT 0x6
+#define MC_BIST_CNTL__LOOP_MASK 0xc00
+#define MC_BIST_CNTL__LOOP__SHIFT 0xa
+#define MC_BIST_CNTL__ENABLE_D0_MASK 0x1000
+#define MC_BIST_CNTL__ENABLE_D0__SHIFT 0xc
+#define MC_BIST_CNTL__ENABLE_D1_MASK 0x2000
+#define MC_BIST_CNTL__ENABLE_D1__SHIFT 0xd
+#define MC_BIST_CNTL__LOAD_RTDATA_CH_MASK 0x4000
+#define MC_BIST_CNTL__LOAD_RTDATA_CH__SHIFT 0xe
+#define MC_BIST_CNTL__LOOP_CNT_MASK 0xfff0000
+#define MC_BIST_CNTL__LOOP_CNT__SHIFT 0x10
+#define MC_BIST_CNTL__DONE_MASK 0x40000000
+#define MC_BIST_CNTL__DONE__SHIFT 0x1e
+#define MC_BIST_CNTL__LOAD_RTDATA_MASK 0x80000000
+#define MC_BIST_CNTL__LOAD_RTDATA__SHIFT 0x1f
+#define MC_BIST_AUTO_CNTL__MOP_MASK 0x3
+#define MC_BIST_AUTO_CNTL__MOP__SHIFT 0x0
+#define MC_BIST_AUTO_CNTL__ADR_GEN_MASK 0xf0
+#define MC_BIST_AUTO_CNTL__ADR_GEN__SHIFT 0x4
+#define MC_BIST_AUTO_CNTL__LFSR_KEY_MASK 0xffff00
+#define MC_BIST_AUTO_CNTL__LFSR_KEY__SHIFT 0x8
+#define MC_BIST_AUTO_CNTL__LFSR_RESET_MASK 0x1000000
+#define MC_BIST_AUTO_CNTL__LFSR_RESET__SHIFT 0x18
+#define MC_BIST_AUTO_CNTL__ADR_RESET_MASK 0x2000000
+#define MC_BIST_AUTO_CNTL__ADR_RESET__SHIFT 0x19
+#define MC_BIST_DIR_CNTL__MOP_MASK 0x7
+#define MC_BIST_DIR_CNTL__MOP__SHIFT 0x0
+#define MC_BIST_DIR_CNTL__EOB_MASK 0x8
+#define MC_BIST_DIR_CNTL__EOB__SHIFT 0x3
+#define MC_BIST_DIR_CNTL__MOP_LOAD_MASK 0x10
+#define MC_BIST_DIR_CNTL__MOP_LOAD__SHIFT 0x4
+#define MC_BIST_DIR_CNTL__DATA_LOAD_MASK 0x20
+#define MC_BIST_DIR_CNTL__DATA_LOAD__SHIFT 0x5
+#define MC_BIST_DIR_CNTL__CMD_RTR_D0_MASK 0x40
+#define MC_BIST_DIR_CNTL__CMD_RTR_D0__SHIFT 0x6
+#define MC_BIST_DIR_CNTL__DAT_RTR_D0_MASK 0x80
+#define MC_BIST_DIR_CNTL__DAT_RTR_D0__SHIFT 0x7
+#define MC_BIST_DIR_CNTL__CMD_RTR_D1_MASK 0x100
+#define MC_BIST_DIR_CNTL__CMD_RTR_D1__SHIFT 0x8
+#define MC_BIST_DIR_CNTL__DAT_RTR_D1_MASK 0x200
+#define MC_BIST_DIR_CNTL__DAT_RTR_D1__SHIFT 0x9
+#define MC_BIST_DIR_CNTL__MOP3_MASK 0x400
+#define MC_BIST_DIR_CNTL__MOP3__SHIFT 0xa
+#define MC_BIST_SADDR__COL_MASK 0x3ff
+#define MC_BIST_SADDR__COL__SHIFT 0x0
+#define MC_BIST_SADDR__ROW_MASK 0xfffc00
+#define MC_BIST_SADDR__ROW__SHIFT 0xa
+#define MC_BIST_SADDR__BANK_MASK 0xf000000
+#define MC_BIST_SADDR__BANK__SHIFT 0x18
+#define MC_BIST_SADDR__RANK_MASK 0x10000000
+#define MC_BIST_SADDR__RANK__SHIFT 0x1c
+#define MC_BIST_SADDR__COLH_MASK 0x20000000
+#define MC_BIST_SADDR__COLH__SHIFT 0x1d
+#define MC_BIST_SADDR__ROWH_MASK 0xc0000000
+#define MC_BIST_SADDR__ROWH__SHIFT 0x1e
+#define MC_BIST_EADDR__COL_MASK 0x3ff
+#define MC_BIST_EADDR__COL__SHIFT 0x0
+#define MC_BIST_EADDR__ROW_MASK 0xfffc00
+#define MC_BIST_EADDR__ROW__SHIFT 0xa
+#define MC_BIST_EADDR__BANK_MASK 0xf000000
+#define MC_BIST_EADDR__BANK__SHIFT 0x18
+#define MC_BIST_EADDR__RANK_MASK 0x10000000
+#define MC_BIST_EADDR__RANK__SHIFT 0x1c
+#define MC_BIST_EADDR__COLH_MASK 0x20000000
+#define MC_BIST_EADDR__COLH__SHIFT 0x1d
+#define MC_BIST_EADDR__ROWH_MASK 0xc0000000
+#define MC_BIST_EADDR__ROWH__SHIFT 0x1e
+#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE_MASK 0xf
+#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE__SHIFT 0x0
+#define MC_BIST_CMP_CNTL__CMP_MASK_BIT_MASK 0xff0
+#define MC_BIST_CMP_CNTL__CMP_MASK_BIT__SHIFT 0x4
+#define MC_BIST_CMP_CNTL__LOAD_RTEDC_MASK 0x1000
+#define MC_BIST_CMP_CNTL__LOAD_RTEDC__SHIFT 0xc
+#define MC_BIST_CMP_CNTL__DATA_STORE_SEL_MASK 0x2000
+#define MC_BIST_CMP_CNTL__DATA_STORE_SEL__SHIFT 0xd
+#define MC_BIST_CMP_CNTL__EDC_STORE_SEL_MASK 0x4000
+#define MC_BIST_CMP_CNTL__EDC_STORE_SEL__SHIFT 0xe
+#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO_MASK 0x8000
+#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO__SHIFT 0xf
+#define MC_BIST_CMP_CNTL__CMP_MASK 0x30000
+#define MC_BIST_CMP_CNTL__CMP__SHIFT 0x10
+#define MC_BIST_CMP_CNTL__DAT_MODE_MASK 0x40000
+#define MC_BIST_CMP_CNTL__DAT_MODE__SHIFT 0x12
+#define MC_BIST_CMP_CNTL__EDC_STORE_MODE_MASK 0x80000
+#define MC_BIST_CMP_CNTL__EDC_STORE_MODE__SHIFT 0x13
+#define MC_BIST_CMP_CNTL__DATA_STORE_MODE_MASK 0x300000
+#define MC_BIST_CMP_CNTL__DATA_STORE_MODE__SHIFT 0x14
+#define MC_BIST_CMP_CNTL__MISMATCH_CNT_MASK 0xffc00000
+#define MC_BIST_CMP_CNTL__MISMATCH_CNT__SHIFT 0x16
+#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_MASK 0x1f
+#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT__SHIFT 0x0
+#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST_MASK 0x100
+#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST__SHIFT 0x8
+#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_MASK 0x1f000
+#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT__SHIFT 0xc
+#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST_MASK 0x100000
+#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST__SHIFT 0x14
+#define MC_BIST_DATA_WORD0__DATA_MASK 0xffffffff
+#define MC_BIST_DATA_WORD0__DATA__SHIFT 0x0
+#define MC_BIST_DATA_WORD1__DATA_MASK 0xffffffff
+#define MC_BIST_DATA_WORD1__DATA__SHIFT 0x0
+#define MC_BIST_DATA_WORD2__DATA_MASK 0xffffffff
+#define MC_BIST_DATA_WORD2__DATA__SHIFT 0x0
+#define MC_BIST_DATA_WORD3__DATA_MASK 0xffffffff
+#define MC_BIST_DATA_WORD3__DATA__SHIFT 0x0
+#define MC_BIST_DATA_WORD4__DATA_MASK 0xffffffff
+#define MC_BIST_DATA_WORD4__DATA__SHIFT 0x0
+#define MC_BIST_DATA_WORD5__DATA_MASK 0xffffffff
+#define MC_BIST_DATA_WORD5__DATA__SHIFT 0x0
+#define MC_BIST_DATA_WORD6__DATA_MASK 0xffffffff
+#define MC_BIST_DATA_WORD6__DATA__SHIFT 0x0
+#define MC_BIST_DATA_WORD7__DATA_MASK 0xffffffff
+#define MC_BIST_DATA_WORD7__DATA__SHIFT 0x0
+#define MC_BIST_DATA_MASK__MASK_MASK 0xffffffff
+#define MC_BIST_DATA_MASK__MASK__SHIFT 0x0
+#define MC_BIST_MISMATCH_ADDR__COL_MASK 0x3ff
+#define MC_BIST_MISMATCH_ADDR__COL__SHIFT 0x0
+#define MC_BIST_MISMATCH_ADDR__ROW_MASK 0xfffc00
+#define MC_BIST_MISMATCH_ADDR__ROW__SHIFT 0xa
+#define MC_BIST_MISMATCH_ADDR__BANK_MASK 0xf000000
+#define MC_BIST_MISMATCH_ADDR__BANK__SHIFT 0x18
+#define MC_BIST_MISMATCH_ADDR__RANK_MASK 0x10000000
+#define MC_BIST_MISMATCH_ADDR__RANK__SHIFT 0x1c
+#define MC_BIST_MISMATCH_ADDR__COLH_MASK 0x20000000
+#define MC_BIST_MISMATCH_ADDR__COLH__SHIFT 0x1d
+#define MC_BIST_MISMATCH_ADDR__ROWH_MASK 0xc0000000
+#define MC_BIST_MISMATCH_ADDR__ROWH__SHIFT 0x1e
+#define MC_BIST_RDATA_WORD0__RDATA_MASK 0xffffffff
+#define MC_BIST_RDATA_WORD0__RDATA__SHIFT 0x0
+#define MC_BIST_RDATA_WORD1__RDATA_MASK 0xffffffff
+#define MC_BIST_RDATA_WORD1__RDATA__SHIFT 0x0
+#define MC_BIST_RDATA_WORD2__RDATA_MASK 0xffffffff
+#define MC_BIST_RDATA_WORD2__RDATA__SHIFT 0x0
+#define MC_BIST_RDATA_WORD3__RDATA_MASK 0xffffffff
+#define MC_BIST_RDATA_WORD3__RDATA__SHIFT 0x0
+#define MC_BIST_RDATA_WORD4__RDATA_MASK 0xffffffff
+#define MC_BIST_RDATA_WORD4__RDATA__SHIFT 0x0
+#define MC_BIST_RDATA_WORD5__RDATA_MASK 0xffffffff
+#define MC_BIST_RDATA_WORD5__RDATA__SHIFT 0x0
+#define MC_BIST_RDATA_WORD6__RDATA_MASK 0xffffffff
+#define MC_BIST_RDATA_WORD6__RDATA__SHIFT 0x0
+#define MC_BIST_RDATA_WORD7__RDATA_MASK 0xffffffff
+#define MC_BIST_RDATA_WORD7__RDATA__SHIFT 0x0
+#define MC_BIST_RDATA_MASK__MASK_MASK 0xffffffff
+#define MC_BIST_RDATA_MASK__MASK__SHIFT 0x0
+#define MC_BIST_RDATA_EDC__EDC_MASK 0xffffffff
+#define MC_BIST_RDATA_EDC__EDC__SHIFT 0x0
+#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD_MASK 0x3fffffff
+#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD__SHIFT 0x0
+#define MC_SEQ_PERF_CNTL__CNTL_MASK 0xc0000000
+#define MC_SEQ_PERF_CNTL__CNTL__SHIFT 0x1e
+#define MC_SEQ_PERF_CNTL_1__PAUSE_MASK 0x1
+#define MC_SEQ_PERF_CNTL_1__PAUSE__SHIFT 0x0
+#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB_MASK 0x100
+#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB__SHIFT 0x8
+#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB_MASK 0x200
+#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB__SHIFT 0x9
+#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB_MASK 0x400
+#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB__SHIFT 0xa
+#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB_MASK 0x800
+#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB__SHIFT 0xb
+#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB_MASK 0x1000
+#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB__SHIFT 0xc
+#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB_MASK 0x2000
+#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB__SHIFT 0xd
+#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB_MASK 0x4000
+#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB__SHIFT 0xe
+#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB_MASK 0x8000
+#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB__SHIFT 0xf
+#define MC_SEQ_PERF_SEQ_CTL__SEL_A_MASK 0xf
+#define MC_SEQ_PERF_SEQ_CTL__SEL_A__SHIFT 0x0
+#define MC_SEQ_PERF_SEQ_CTL__SEL_B_MASK 0xf0
+#define MC_SEQ_PERF_SEQ_CTL__SEL_B__SHIFT 0x4
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C_MASK 0xf00
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C__SHIFT 0x8
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D_MASK 0xf000
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D__SHIFT 0xc
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A_MASK 0xf0000
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A__SHIFT 0x10
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B_MASK 0xf00000
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B__SHIFT 0x14
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C_MASK 0xf000000
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C__SHIFT 0x18
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D_MASK 0xf0000000
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D__SHIFT 0x1c
+#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE_MASK 0xffffffff
+#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE__SHIFT 0x0
+#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE_MASK 0xffffffff
+#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE__SHIFT 0x0
+#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE_MASK 0xffffffff
+#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE__SHIFT 0x0
+#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE_MASK 0xffffffff
+#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE__SHIFT 0x0
+#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE_MASK 0xffffffff
+#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE__SHIFT 0x0
+#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE_MASK 0xffffffff
+#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE__SHIFT 0x0
+#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE_MASK 0xffffffff
+#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE__SHIFT 0x0
+#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE_MASK 0xffffffff
+#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE__SHIFT 0x0
+#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0_MASK 0x1
+#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0__SHIFT 0x0
+#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1_MASK 0x2
+#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1__SHIFT 0x1
+#define MC_SEQ_STATUS_M__CMD_RDY_D0_MASK 0x4
+#define MC_SEQ_STATUS_M__CMD_RDY_D0__SHIFT 0x2
+#define MC_SEQ_STATUS_M__CMD_RDY_D1_MASK 0x8
+#define MC_SEQ_STATUS_M__CMD_RDY_D1__SHIFT 0x3
+#define MC_SEQ_STATUS_M__SLF_D0_MASK 0x10
+#define MC_SEQ_STATUS_M__SLF_D0__SHIFT 0x4
+#define MC_SEQ_STATUS_M__SLF_D1_MASK 0x20
+#define MC_SEQ_STATUS_M__SLF_D1__SHIFT 0x5
+#define MC_SEQ_STATUS_M__SS_SLF_D0_MASK 0x40
+#define MC_SEQ_STATUS_M__SS_SLF_D0__SHIFT 0x6
+#define MC_SEQ_STATUS_M__SS_SLF_D1_MASK 0x80
+#define MC_SEQ_STATUS_M__SS_SLF_D1__SHIFT 0x7
+#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY_MASK 0x100
+#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY__SHIFT 0x8
+#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY_MASK 0x200
+#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY__SHIFT 0x9
+#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL_MASK 0x1000
+#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL__SHIFT 0xc
+#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL_MASK 0x2000
+#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL__SHIFT 0xd
+#define MC_SEQ_STATUS_M__SEQ0_BUSY_MASK 0x4000
+#define MC_SEQ_STATUS_M__SEQ0_BUSY__SHIFT 0xe
+#define MC_SEQ_STATUS_M__SEQ1_BUSY_MASK 0x8000
+#define MC_SEQ_STATUS_M__SEQ1_BUSY__SHIFT 0xf
+#define MC_SEQ_STATUS_M__PMG_PWRSTATE_MASK 0x10000
+#define MC_SEQ_STATUS_M__PMG_PWRSTATE__SHIFT 0x10
+#define MC_SEQ_STATUS_M__PMG_FSMSTATE_MASK 0x1f00000
+#define MC_SEQ_STATUS_M__PMG_FSMSTATE__SHIFT 0x14
+#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS_MASK 0x2000000
+#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS__SHIFT 0x19
+#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS_MASK 0x4000000
+#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS__SHIFT 0x1a
+#define MC_SEQ_STATUS_M__SEQ0_ALLOWSTOP_MASK 0x8000000
+#define MC_SEQ_STATUS_M__SEQ0_ALLOWSTOP__SHIFT 0x1b
+#define MC_SEQ_STATUS_M__SEQ1_ALLOWSTOP_MASK 0x10000000
+#define MC_SEQ_STATUS_M__SEQ1_ALLOWSTOP__SHIFT 0x1c
+#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL_MASK 0x1
+#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL__SHIFT 0x0
+#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL_MASK 0x2
+#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL__SHIFT 0x1
+#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL_MASK 0x10
+#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL__SHIFT 0x4
+#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL_MASK 0x20
+#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL__SHIFT 0x5
+#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY_MASK 0x100
+#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY__SHIFT 0x8
+#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY_MASK 0x200
+#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY__SHIFT 0x9
+#define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffff
+#define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x0
+#define MC_SEQ_VENDOR_ID_I0__VALUE_MASK 0xffffffff
+#define MC_SEQ_VENDOR_ID_I0__VALUE__SHIFT 0x0
+#define MC_SEQ_VENDOR_ID_I1__VALUE_MASK 0xffffffff
+#define MC_SEQ_VENDOR_ID_I1__VALUE__SHIFT 0x0
+#define MC_SEQ_MISC0__VALUE_MASK 0xffffffff
+#define MC_SEQ_MISC0__VALUE__SHIFT 0x0
+#define MC_SEQ_MISC1__VALUE_MASK 0xffffffff
+#define MC_SEQ_MISC1__VALUE__SHIFT 0x0
+#define MC_SEQ_RESERVE_0_S__MCLK_GCK_SEL_MASK 0x1
+#define MC_SEQ_RESERVE_0_S__MCLK_GCK_SEL__SHIFT 0x0
+#define MC_SEQ_RESERVE_0_S__SCLK_FIELD_MASK 0xfffffffe
+#define MC_SEQ_RESERVE_0_S__SCLK_FIELD__SHIFT 0x1
+#define MC_SEQ_RESERVE_1_S__SCLK_FIELD_MASK 0xffffffff
+#define MC_SEQ_RESERVE_1_S__SCLK_FIELD__SHIFT 0x0
+#define MC_SEQ_RESERVE_M__MCLK_FIELD_MASK 0xffffffff
+#define MC_SEQ_RESERVE_M__MCLK_FIELD__SHIFT 0x0
+#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV_MASK 0xfff
+#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV__SHIFT 0x0
+#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV_MASK 0xfff000
+#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV__SHIFT 0xc
+#define MC_SEQ_IO_RESERVE_D0__APHY_RSV_MASK 0xff000000
+#define MC_SEQ_IO_RESERVE_D0__APHY_RSV__SHIFT 0x18
+#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV_MASK 0xfff
+#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV__SHIFT 0x0
+#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV_MASK 0xfff000
+#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV__SHIFT 0xc
+#define MC_SEQ_IO_RESERVE_D1__APHY_RSV_MASK 0xff000000
+#define MC_SEQ_IO_RESERVE_D1__APHY_RSV__SHIFT 0x18
+#define MC_SEQ_SUP_CNTL__RUN_MASK 0x1
+#define MC_SEQ_SUP_CNTL__RUN__SHIFT 0x0
+#define MC_SEQ_SUP_CNTL__SINGLE_STEP_MASK 0x2
+#define MC_SEQ_SUP_CNTL__SINGLE_STEP__SHIFT 0x1
+#define MC_SEQ_SUP_CNTL__SW_WAKE_MASK 0x4
+#define MC_SEQ_SUP_CNTL__SW_WAKE__SHIFT 0x2
+#define MC_SEQ_SUP_CNTL__RESET_PC_MASK 0x8
+#define MC_SEQ_SUP_CNTL__RESET_PC__SHIFT 0x3
+#define MC_SEQ_SUP_CNTL__PGM_WRITE_MASK 0x10
+#define MC_SEQ_SUP_CNTL__PGM_WRITE__SHIFT 0x4
+#define MC_SEQ_SUP_CNTL__PGM_READ_MASK 0x20
+#define MC_SEQ_SUP_CNTL__PGM_READ__SHIFT 0x5
+#define MC_SEQ_SUP_CNTL__FAST_WRITE_MASK 0x40
+#define MC_SEQ_SUP_CNTL__FAST_WRITE__SHIFT 0x6
+#define MC_SEQ_SUP_CNTL__BKPT_CLEAR_MASK 0x80
+#define MC_SEQ_SUP_CNTL__BKPT_CLEAR__SHIFT 0x7
+#define MC_SEQ_SUP_CNTL__PGM_CHKSUM_MASK 0xff800000
+#define MC_SEQ_SUP_CNTL__PGM_CHKSUM__SHIFT 0x17
+#define MC_SEQ_SUP_PGM__CNTL_MASK 0xffffffff
+#define MC_SEQ_SUP_PGM__CNTL__SHIFT 0x0
+#define MC_SEQ_SUP_GP0_STAT__STATUS_MASK 0xffffffff
+#define MC_SEQ_SUP_GP0_STAT__STATUS__SHIFT 0x0
+#define MC_SEQ_SUP_GP1_STAT__STATUS_MASK 0xffffffff
+#define MC_SEQ_SUP_GP1_STAT__STATUS__SHIFT 0x0
+#define MC_SEQ_SUP_GP2_STAT__STATUS_MASK 0xffffffff
+#define MC_SEQ_SUP_GP2_STAT__STATUS__SHIFT 0x0
+#define MC_SEQ_SUP_GP3_STAT__STATUS_MASK 0xffffffff
+#define MC_SEQ_SUP_GP3_STAT__STATUS__SHIFT 0x0
+#define MC_SEQ_SUP_IR_STAT__STATUS_MASK 0xffffffff
+#define MC_SEQ_SUP_IR_STAT__STATUS__SHIFT 0x0
+#define MC_SEQ_SUP_DEC_STAT__STATUS_MASK 0xffffffff
+#define MC_SEQ_SUP_DEC_STAT__STATUS__SHIFT 0x0
+#define MC_SEQ_SUP_PGM_STAT__STATUS_MASK 0xffffffff
+#define MC_SEQ_SUP_PGM_STAT__STATUS__SHIFT 0x0
+#define MC_SEQ_SUP_R_PGM__PGM_MASK 0xffffffff
+#define MC_SEQ_SUP_R_PGM__PGM__SHIFT 0x0
+#define MC_SEQ_MISC3__VALUE_MASK 0xffffffff
+#define MC_SEQ_MISC3__VALUE__SHIFT 0x0
+#define MC_SEQ_MISC4__VALUE_MASK 0xffffffff
+#define MC_SEQ_MISC4__VALUE__SHIFT 0x0
+#define MC_SEQ_MISC5__VALUE_MASK 0xffffffff
+#define MC_SEQ_MISC5__VALUE__SHIFT 0x0
+#define MC_SEQ_MISC6__VALUE_MASK 0xffffffff
+#define MC_SEQ_MISC6__VALUE__SHIFT 0x0
+#define MC_SEQ_MISC7__VALUE_MASK 0xffffffff
+#define MC_SEQ_MISC7__VALUE__SHIFT 0x0
+#define MC_SEQ_MISC8__VALUE_MASK 0xffffffff
+#define MC_SEQ_MISC8__VALUE__SHIFT 0x0
+#define MC_SEQ_MISC9__VALUE_MASK 0xffffffff
+#define MC_SEQ_MISC9__VALUE__SHIFT 0x0
+#define MC_SEQ_CG__CG_SEQ_REQ_MASK 0xff
+#define MC_SEQ_CG__CG_SEQ_REQ__SHIFT 0x0
+#define MC_SEQ_CG__CG_SEQ_RESP_MASK 0xff00
+#define MC_SEQ_CG__CG_SEQ_RESP__SHIFT 0x8
+#define MC_SEQ_CG__SEQ_CG_REQ_MASK 0xff0000
+#define MC_SEQ_CG__SEQ_CG_REQ__SHIFT 0x10
+#define MC_SEQ_CG__SEQ_CG_RESP_MASK 0xff000000
+#define MC_SEQ_CG__SEQ_CG_RESP__SHIFT 0x18
+#define MC_SEQ_BYTE_REMAP_D0__BYTE0_MASK 0x3
+#define MC_SEQ_BYTE_REMAP_D0__BYTE0__SHIFT 0x0
+#define MC_SEQ_BYTE_REMAP_D0__BYTE1_MASK 0xc
+#define MC_SEQ_BYTE_REMAP_D0__BYTE1__SHIFT 0x2
+#define MC_SEQ_BYTE_REMAP_D0__BYTE2_MASK 0x30
+#define MC_SEQ_BYTE_REMAP_D0__BYTE2__SHIFT 0x4
+#define MC_SEQ_BYTE_REMAP_D0__BYTE3_MASK 0xc0
+#define MC_SEQ_BYTE_REMAP_D0__BYTE3__SHIFT 0x6
+#define MC_SEQ_BYTE_REMAP_D1__BYTE0_MASK 0x3
+#define MC_SEQ_BYTE_REMAP_D1__BYTE0__SHIFT 0x0
+#define MC_SEQ_BYTE_REMAP_D1__BYTE1_MASK 0xc
+#define MC_SEQ_BYTE_REMAP_D1__BYTE1__SHIFT 0x2
+#define MC_SEQ_BYTE_REMAP_D1__BYTE2_MASK 0x30
+#define MC_SEQ_BYTE_REMAP_D1__BYTE2__SHIFT 0x4
+#define MC_SEQ_BYTE_REMAP_D1__BYTE3_MASK 0xc0
+#define MC_SEQ_BYTE_REMAP_D1__BYTE3__SHIFT 0x6
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT0_MASK 0x7
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT0__SHIFT 0x0
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT1_MASK 0x38
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT1__SHIFT 0x3
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT2_MASK 0x1c0
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT2__SHIFT 0x6
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT3_MASK 0xe00
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT3__SHIFT 0x9
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT4_MASK 0x7000
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT4__SHIFT 0xc
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT5_MASK 0x38000
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT5__SHIFT 0xf
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT6_MASK 0x1c0000
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT6__SHIFT 0x12
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT7_MASK 0xe00000
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT7__SHIFT 0x15
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT0_MASK 0x7
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT0__SHIFT 0x0
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT1_MASK 0x38
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT1__SHIFT 0x3
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT2_MASK 0x1c0
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT2__SHIFT 0x6
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT3_MASK 0xe00
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT3__SHIFT 0x9
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT4_MASK 0x7000
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT4__SHIFT 0xc
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT5_MASK 0x38000
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT5__SHIFT 0xf
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT6_MASK 0x1c0000
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT6__SHIFT 0x12
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT7_MASK 0xe00000
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT7__SHIFT 0x15
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT0_MASK 0x7
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT0__SHIFT 0x0
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT1_MASK 0x38
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT1__SHIFT 0x3
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT2_MASK 0x1c0
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT2__SHIFT 0x6
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT3_MASK 0xe00
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT3__SHIFT 0x9
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT4_MASK 0x7000
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT4__SHIFT 0xc
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT5_MASK 0x38000
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT5__SHIFT 0xf
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT6_MASK 0x1c0000
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT6__SHIFT 0x12
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT7_MASK 0xe00000
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT7__SHIFT 0x15
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT0_MASK 0x7
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT0__SHIFT 0x0
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT1_MASK 0x38
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT1__SHIFT 0x3
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT2_MASK 0x1c0
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT2__SHIFT 0x6
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT3_MASK 0xe00
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT3__SHIFT 0x9
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT4_MASK 0x7000
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT4__SHIFT 0xc
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT5_MASK 0x38000
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT5__SHIFT 0xf
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT6_MASK 0x1c0000
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT6__SHIFT 0x12
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT7_MASK 0xe00000
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT7__SHIFT 0x15
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT0_MASK 0x7
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT0__SHIFT 0x0
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT1_MASK 0x38
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT1__SHIFT 0x3
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT2_MASK 0x1c0
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT2__SHIFT 0x6
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT3_MASK 0xe00
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT3__SHIFT 0x9
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT4_MASK 0x7000
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT4__SHIFT 0xc
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT5_MASK 0x38000
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT5__SHIFT 0xf
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT6_MASK 0x1c0000
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT6__SHIFT 0x12
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT7_MASK 0xe00000
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT7__SHIFT 0x15
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT0_MASK 0x7
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT0__SHIFT 0x0
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT1_MASK 0x38
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT1__SHIFT 0x3
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT2_MASK 0x1c0
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT2__SHIFT 0x6
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT3_MASK 0xe00
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT3__SHIFT 0x9
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT4_MASK 0x7000
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT4__SHIFT 0xc
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT5_MASK 0x38000
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT5__SHIFT 0xf
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT6_MASK 0x1c0000
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT6__SHIFT 0x12
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT7_MASK 0xe00000
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT7__SHIFT 0x15
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT0_MASK 0x7
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT0__SHIFT 0x0
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT1_MASK 0x38
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT1__SHIFT 0x3
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT2_MASK 0x1c0
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT2__SHIFT 0x6
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT3_MASK 0xe00
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT3__SHIFT 0x9
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT4_MASK 0x7000
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT4__SHIFT 0xc
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT5_MASK 0x38000
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT5__SHIFT 0xf
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT6_MASK 0x1c0000
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT6__SHIFT 0x12
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT7_MASK 0xe00000
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT7__SHIFT 0x15
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT0_MASK 0x7
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT0__SHIFT 0x0
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT1_MASK 0x38
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT1__SHIFT 0x3
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT2_MASK 0x1c0
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT2__SHIFT 0x6
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT3_MASK 0xe00
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT3__SHIFT 0x9
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT4_MASK 0x7000
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT4__SHIFT 0xc
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT5_MASK 0x38000
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT5__SHIFT 0xf
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT6_MASK 0x1c0000
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT6__SHIFT 0x12
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT7_MASK 0xe00000
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT7__SHIFT 0x15
+#define MC_SEQ_RAS_TIMING_LP__TRCDW_MASK 0x1f
+#define MC_SEQ_RAS_TIMING_LP__TRCDW__SHIFT 0x0
+#define MC_SEQ_RAS_TIMING_LP__TRCDWA_MASK 0x3e0
+#define MC_SEQ_RAS_TIMING_LP__TRCDWA__SHIFT 0x5
+#define MC_SEQ_RAS_TIMING_LP__TRCDR_MASK 0x7c00
+#define MC_SEQ_RAS_TIMING_LP__TRCDR__SHIFT 0xa
+#define MC_SEQ_RAS_TIMING_LP__TRCDRA_MASK 0xf8000
+#define MC_SEQ_RAS_TIMING_LP__TRCDRA__SHIFT 0xf
+#define MC_SEQ_RAS_TIMING_LP__TRRD_MASK 0xf00000
+#define MC_SEQ_RAS_TIMING_LP__TRRD__SHIFT 0x14
+#define MC_SEQ_RAS_TIMING_LP__TRC_MASK 0x7f000000
+#define MC_SEQ_RAS_TIMING_LP__TRC__SHIFT 0x18
+#define MC_SEQ_CAS_TIMING_LP__TNOPW_MASK 0x3
+#define MC_SEQ_CAS_TIMING_LP__TNOPW__SHIFT 0x0
+#define MC_SEQ_CAS_TIMING_LP__TNOPR_MASK 0xc
+#define MC_SEQ_CAS_TIMING_LP__TNOPR__SHIFT 0x2
+#define MC_SEQ_CAS_TIMING_LP__TR2W_MASK 0x1f0
+#define MC_SEQ_CAS_TIMING_LP__TR2W__SHIFT 0x4
+#define MC_SEQ_CAS_TIMING_LP__TCCDL_MASK 0xe00
+#define MC_SEQ_CAS_TIMING_LP__TCCDL__SHIFT 0x9
+#define MC_SEQ_CAS_TIMING_LP__TR2R_MASK 0xf000
+#define MC_SEQ_CAS_TIMING_LP__TR2R__SHIFT 0xc
+#define MC_SEQ_CAS_TIMING_LP__TW2R_MASK 0x1f0000
+#define MC_SEQ_CAS_TIMING_LP__TW2R__SHIFT 0x10
+#define MC_SEQ_CAS_TIMING_LP__TCL_MASK 0x1f000000
+#define MC_SEQ_CAS_TIMING_LP__TCL__SHIFT 0x18
+#define MC_SEQ_MISC_TIMING_LP__TRP_WRA_MASK 0x3f
+#define MC_SEQ_MISC_TIMING_LP__TRP_WRA__SHIFT 0x0
+#define MC_SEQ_MISC_TIMING_LP__TRP_RDA_MASK 0x3f00
+#define MC_SEQ_MISC_TIMING_LP__TRP_RDA__SHIFT 0x8
+#define MC_SEQ_MISC_TIMING_LP__TRP_MASK 0xf8000
+#define MC_SEQ_MISC_TIMING_LP__TRP__SHIFT 0xf
+#define MC_SEQ_MISC_TIMING_LP__TRFC_MASK 0x1ff00000
+#define MC_SEQ_MISC_TIMING_LP__TRFC__SHIFT 0x14
+#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA_MASK 0x7
+#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA__SHIFT 0x0
+#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA_MASK 0x70
+#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA__SHIFT 0x4
+#define MC_SEQ_MISC_TIMING2_LP__FAW_MASK 0x1f00
+#define MC_SEQ_MISC_TIMING2_LP__FAW__SHIFT 0x8
+#define MC_SEQ_MISC_TIMING2_LP__TREDC_MASK 0xe000
+#define MC_SEQ_MISC_TIMING2_LP__TREDC__SHIFT 0xd
+#define MC_SEQ_MISC_TIMING2_LP__TWEDC_MASK 0x1f0000
+#define MC_SEQ_MISC_TIMING2_LP__TWEDC__SHIFT 0x10
+#define MC_SEQ_MISC_TIMING2_LP__TADR_MASK 0xe00000
+#define MC_SEQ_MISC_TIMING2_LP__TADR__SHIFT 0x15
+#define MC_SEQ_MISC_TIMING2_LP__TFCKTR_MASK 0xf000000
+#define MC_SEQ_MISC_TIMING2_LP__TFCKTR__SHIFT 0x18
+#define MC_SEQ_MISC_TIMING2_LP__TWDATATR_MASK 0xf0000000
+#define MC_SEQ_MISC_TIMING2_LP__TWDATATR__SHIFT 0x1c
+#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY_MASK 0x7
+#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY__SHIFT 0x0
+#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT_MASK 0xf8
+#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT__SHIFT 0x3
+#define MC_SEQ_RD_CTL_D0_LP__RST_SEL_MASK 0x300
+#define MC_SEQ_RD_CTL_D0_LP__RST_SEL__SHIFT 0x8
+#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY_MASK 0xc00
+#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY__SHIFT 0xa
+#define MC_SEQ_RD_CTL_D0_LP__RST_HLD_MASK 0xf000
+#define MC_SEQ_RD_CTL_D0_LP__RST_HLD__SHIFT 0xc
+#define MC_SEQ_RD_CTL_D0_LP__STR_PRE_MASK 0x10000
+#define MC_SEQ_RD_CTL_D0_LP__STR_PRE__SHIFT 0x10
+#define MC_SEQ_RD_CTL_D0_LP__STR_PST_MASK 0x20000
+#define MC_SEQ_RD_CTL_D0_LP__STR_PST__SHIFT 0x11
+#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY_MASK 0x1f00000
+#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY__SHIFT 0x14
+#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY_MASK 0x3e000000
+#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY__SHIFT 0x19
+#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY_MASK 0x7
+#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY__SHIFT 0x0
+#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT_MASK 0xf8
+#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT__SHIFT 0x3
+#define MC_SEQ_RD_CTL_D1_LP__RST_SEL_MASK 0x300
+#define MC_SEQ_RD_CTL_D1_LP__RST_SEL__SHIFT 0x8
+#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY_MASK 0xc00
+#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY__SHIFT 0xa
+#define MC_SEQ_RD_CTL_D1_LP__RST_HLD_MASK 0xf000
+#define MC_SEQ_RD_CTL_D1_LP__RST_HLD__SHIFT 0xc
+#define MC_SEQ_RD_CTL_D1_LP__STR_PRE_MASK 0x10000
+#define MC_SEQ_RD_CTL_D1_LP__STR_PRE__SHIFT 0x10
+#define MC_SEQ_RD_CTL_D1_LP__STR_PST_MASK 0x20000
+#define MC_SEQ_RD_CTL_D1_LP__STR_PST__SHIFT 0x11
+#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY_MASK 0x1f00000
+#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY__SHIFT 0x14
+#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY_MASK 0x3e000000
+#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY__SHIFT 0x19
+#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY_MASK 0xf
+#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY__SHIFT 0x0
+#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY_MASK 0xf0
+#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY__SHIFT 0x4
+#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR_MASK 0x100
+#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR__SHIFT 0x8
+#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY_MASK 0x200
+#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY__SHIFT 0x9
+#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY_MASK 0x400
+#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY__SHIFT 0xa
+#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY_MASK 0x800
+#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY__SHIFT 0xb
+#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY_MASK 0xf000
+#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY__SHIFT 0xc
+#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT_MASK 0xf0000
+#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT__SHIFT 0x10
+#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL_MASK 0x300000
+#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL__SHIFT 0x14
+#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY_MASK 0xf000000
+#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY__SHIFT 0x18
+#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT_MASK 0x10000000
+#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT__SHIFT 0x1c
+#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY_MASK 0x20000000
+#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY__SHIFT 0x1d
+#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY_MASK 0x40000000
+#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY__SHIFT 0x1e
+#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY_MASK 0xf
+#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY__SHIFT 0x0
+#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY_MASK 0xf0
+#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY__SHIFT 0x4
+#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR_MASK 0x100
+#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR__SHIFT 0x8
+#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY_MASK 0x200
+#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY__SHIFT 0x9
+#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY_MASK 0x400
+#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY__SHIFT 0xa
+#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY_MASK 0x800
+#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY__SHIFT 0xb
+#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY_MASK 0xf000
+#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY__SHIFT 0xc
+#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT_MASK 0xf0000
+#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT__SHIFT 0x10
+#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL_MASK 0x300000
+#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL__SHIFT 0x14
+#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY_MASK 0xf000000
+#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY__SHIFT 0x18
+#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT_MASK 0x10000000
+#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT__SHIFT 0x1c
+#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY_MASK 0x20000000
+#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY__SHIFT 0x1d
+#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY_MASK 0x40000000
+#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY__SHIFT 0x1e
+#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0_MASK 0x1
+#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0__SHIFT 0x0
+#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0_MASK 0x2
+#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0__SHIFT 0x1
+#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0_MASK 0x4
+#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0__SHIFT 0x2
+#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1_MASK 0x8
+#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1__SHIFT 0x3
+#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1_MASK 0x10
+#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1__SHIFT 0x4
+#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1_MASK 0x20
+#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1__SHIFT 0x5
+#define MC_SEQ_WR_CTL_2_LP__WCDR_EN_MASK 0x40
+#define MC_SEQ_WR_CTL_2_LP__WCDR_EN__SHIFT 0x6
+#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MASK 0xffff
+#define MC_SEQ_PMG_CMD_EMRS_LP__ADR__SHIFT 0x0
+#define MC_SEQ_PMG_CMD_EMRS_LP__MOP_MASK 0x70000
+#define MC_SEQ_PMG_CMD_EMRS_LP__MOP__SHIFT 0x10
+#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB_MASK 0x80000
+#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB__SHIFT 0x13
+#define MC_SEQ_PMG_CMD_EMRS_LP__END_MASK 0x100000
+#define MC_SEQ_PMG_CMD_EMRS_LP__END__SHIFT 0x14
+#define MC_SEQ_PMG_CMD_EMRS_LP__CSB_MASK 0x600000
+#define MC_SEQ_PMG_CMD_EMRS_LP__CSB__SHIFT 0x15
+#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1_MASK 0x10000000
+#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1__SHIFT 0x1c
+#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0_MASK 0x20000000
+#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0__SHIFT 0x1d
+#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MASK 0xffff
+#define MC_SEQ_PMG_CMD_MRS_LP__ADR__SHIFT 0x0
+#define MC_SEQ_PMG_CMD_MRS_LP__MOP_MASK 0x70000
+#define MC_SEQ_PMG_CMD_MRS_LP__MOP__SHIFT 0x10
+#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB_MASK 0x80000
+#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB__SHIFT 0x13
+#define MC_SEQ_PMG_CMD_MRS_LP__END_MASK 0x100000
+#define MC_SEQ_PMG_CMD_MRS_LP__END__SHIFT 0x14
+#define MC_SEQ_PMG_CMD_MRS_LP__CSB_MASK 0x600000
+#define MC_SEQ_PMG_CMD_MRS_LP__CSB__SHIFT 0x15
+#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1_MASK 0x10000000
+#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1__SHIFT 0x1c
+#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0_MASK 0x20000000
+#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0__SHIFT 0x1d
+#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MASK 0xffff
+#define MC_SEQ_PMG_CMD_MRS1_LP__ADR__SHIFT 0x0
+#define MC_SEQ_PMG_CMD_MRS1_LP__MOP_MASK 0x70000
+#define MC_SEQ_PMG_CMD_MRS1_LP__MOP__SHIFT 0x10
+#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB_MASK 0x80000
+#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB__SHIFT 0x13
+#define MC_SEQ_PMG_CMD_MRS1_LP__END_MASK 0x100000
+#define MC_SEQ_PMG_CMD_MRS1_LP__END__SHIFT 0x14
+#define MC_SEQ_PMG_CMD_MRS1_LP__CSB_MASK 0x600000
+#define MC_SEQ_PMG_CMD_MRS1_LP__CSB__SHIFT 0x15
+#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1_MASK 0x10000000
+#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1__SHIFT 0x1c
+#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0_MASK 0x20000000
+#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0__SHIFT 0x1d
+#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MASK 0xffff
+#define MC_SEQ_PMG_CMD_MRS2_LP__ADR__SHIFT 0x0
+#define MC_SEQ_PMG_CMD_MRS2_LP__MOP_MASK 0x70000
+#define MC_SEQ_PMG_CMD_MRS2_LP__MOP__SHIFT 0x10
+#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB_MASK 0x80000
+#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB__SHIFT 0x13
+#define MC_SEQ_PMG_CMD_MRS2_LP__END_MASK 0x100000
+#define MC_SEQ_PMG_CMD_MRS2_LP__END__SHIFT 0x14
+#define MC_SEQ_PMG_CMD_MRS2_LP__CSB_MASK 0x600000
+#define MC_SEQ_PMG_CMD_MRS2_LP__CSB__SHIFT 0x15
+#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1_MASK 0x10000000
+#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1__SHIFT 0x1c
+#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0_MASK 0x20000000
+#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0__SHIFT 0x1d
+#define MC_SEQ_PMG_TIMING_LP__TCKSRE_MASK 0x7
+#define MC_SEQ_PMG_TIMING_LP__TCKSRE__SHIFT 0x0
+#define MC_SEQ_PMG_TIMING_LP__TCKSRX_MASK 0x70
+#define MC_SEQ_PMG_TIMING_LP__TCKSRX__SHIFT 0x4
+#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MASK 0xf00
+#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE__SHIFT 0x8
+#define MC_SEQ_PMG_TIMING_LP__TCKE_MASK 0x3f000
+#define MC_SEQ_PMG_TIMING_LP__TCKE__SHIFT 0xc
+#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_MASK 0x1c0000
+#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE__SHIFT 0x12
+#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB_MASK 0x800000
+#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB__SHIFT 0x17
+#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS_MASK 0xff000000
+#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS__SHIFT 0x18
+#define MC_SEQ_IO_RWORD0__RDATA_MASK 0xffffffff
+#define MC_SEQ_IO_RWORD0__RDATA__SHIFT 0x0
+#define MC_SEQ_IO_RWORD1__RDATA_MASK 0xffffffff
+#define MC_SEQ_IO_RWORD1__RDATA__SHIFT 0x0
+#define MC_SEQ_IO_RWORD2__RDATA_MASK 0xffffffff
+#define MC_SEQ_IO_RWORD2__RDATA__SHIFT 0x0
+#define MC_SEQ_IO_RWORD3__RDATA_MASK 0xffffffff
+#define MC_SEQ_IO_RWORD3__RDATA__SHIFT 0x0
+#define MC_SEQ_IO_RWORD4__RDATA_MASK 0xffffffff
+#define MC_SEQ_IO_RWORD4__RDATA__SHIFT 0x0
+#define MC_SEQ_IO_RWORD5__RDATA_MASK 0xffffffff
+#define MC_SEQ_IO_RWORD5__RDATA__SHIFT 0x0
+#define MC_SEQ_IO_RWORD6__RDATA_MASK 0xffffffff
+#define MC_SEQ_IO_RWORD6__RDATA__SHIFT 0x0
+#define MC_SEQ_IO_RWORD7__RDATA_MASK 0xffffffff
+#define MC_SEQ_IO_RWORD7__RDATA__SHIFT 0x0
+#define MC_SEQ_IO_RDBI__MASK_MASK 0xffffffff
+#define MC_SEQ_IO_RDBI__MASK__SHIFT 0x0
+#define MC_SEQ_IO_REDC__EDC_MASK 0xffffffff
+#define MC_SEQ_IO_REDC__EDC__SHIFT 0x0
+#define MC_SEQ_TCG_CNTL__RESET_MASK 0x1
+#define MC_SEQ_TCG_CNTL__RESET__SHIFT 0x0
+#define MC_SEQ_TCG_CNTL__ENABLE_D0_MASK 0x2
+#define MC_SEQ_TCG_CNTL__ENABLE_D0__SHIFT 0x1
+#define MC_SEQ_TCG_CNTL__ENABLE_D1_MASK 0x4
+#define MC_SEQ_TCG_CNTL__ENABLE_D1__SHIFT 0x2
+#define MC_SEQ_TCG_CNTL__START_MASK 0x8
+#define MC_SEQ_TCG_CNTL__START__SHIFT 0x3
+#define MC_SEQ_TCG_CNTL__NFIFO_MASK 0x70
+#define MC_SEQ_TCG_CNTL__NFIFO__SHIFT 0x4
+#define MC_SEQ_TCG_CNTL__INFINITE_CMD_MASK 0x80
+#define MC_SEQ_TCG_CNTL__INFINITE_CMD__SHIFT 0x7
+#define MC_SEQ_TCG_CNTL__MOP_MASK 0xf00
+#define MC_SEQ_TCG_CNTL__MOP__SHIFT 0x8
+#define MC_SEQ_TCG_CNTL__DATA_CNT_MASK 0xf000
+#define MC_SEQ_TCG_CNTL__DATA_CNT__SHIFT 0xc
+#define MC_SEQ_TCG_CNTL__LOAD_FIFO_MASK 0x10000
+#define MC_SEQ_TCG_CNTL__LOAD_FIFO__SHIFT 0x10
+#define MC_SEQ_TCG_CNTL__SHORT_LDFF_MASK 0x20000
+#define MC_SEQ_TCG_CNTL__SHORT_LDFF__SHIFT 0x11
+#define MC_SEQ_TCG_CNTL__FRAME_TRAIN_MASK 0x40000
+#define MC_SEQ_TCG_CNTL__FRAME_TRAIN__SHIFT 0x12
+#define MC_SEQ_TCG_CNTL__BURST_NUM_MASK 0x380000
+#define MC_SEQ_TCG_CNTL__BURST_NUM__SHIFT 0x13
+#define MC_SEQ_TCG_CNTL__ISSUE_AREF_MASK 0x400000
+#define MC_SEQ_TCG_CNTL__ISSUE_AREF__SHIFT 0x16
+#define MC_SEQ_TCG_CNTL__TXDBI_CNTL_MASK 0x800000
+#define MC_SEQ_TCG_CNTL__TXDBI_CNTL__SHIFT 0x17
+#define MC_SEQ_TCG_CNTL__VPTR_MASK_MASK 0x1000000
+#define MC_SEQ_TCG_CNTL__VPTR_MASK__SHIFT 0x18
+#define MC_SEQ_TCG_CNTL__AREF_LAST_MASK 0x2000000
+#define MC_SEQ_TCG_CNTL__AREF_LAST__SHIFT 0x19
+#define MC_SEQ_TCG_CNTL__AREF_BOTH_MASK 0x4000000
+#define MC_SEQ_TCG_CNTL__AREF_BOTH__SHIFT 0x1a
+#define MC_SEQ_TCG_CNTL__LD_RTDATA_OVR_MASK 0x10000000
+#define MC_SEQ_TCG_CNTL__LD_RTDATA_OVR__SHIFT 0x1c
+#define MC_SEQ_TCG_CNTL__LD_RTDATA_CH_MASK 0x20000000
+#define MC_SEQ_TCG_CNTL__LD_RTDATA_CH__SHIFT 0x1d
+#define MC_SEQ_TCG_CNTL__DONE_MASK 0x80000000
+#define MC_SEQ_TCG_CNTL__DONE__SHIFT 0x1f
+#define MC_SEQ_TSM_CTRL__START_MASK 0x1
+#define MC_SEQ_TSM_CTRL__START__SHIFT 0x0
+#define MC_SEQ_TSM_CTRL__CAPTURE_START_MASK 0x2
+#define MC_SEQ_TSM_CTRL__CAPTURE_START__SHIFT 0x1
+#define MC_SEQ_TSM_CTRL__DONE_MASK 0x4
+#define MC_SEQ_TSM_CTRL__DONE__SHIFT 0x2
+#define MC_SEQ_TSM_CTRL__ERR_MASK 0x8
+#define MC_SEQ_TSM_CTRL__ERR__SHIFT 0x3
+#define MC_SEQ_TSM_CTRL__STEP_MASK 0x10
+#define MC_SEQ_TSM_CTRL__STEP__SHIFT 0x4
+#define MC_SEQ_TSM_CTRL__DIRECTION_MASK 0x20
+#define MC_SEQ_TSM_CTRL__DIRECTION__SHIFT 0x5
+#define MC_SEQ_TSM_CTRL__INVERT_MASK 0x40
+#define MC_SEQ_TSM_CTRL__INVERT__SHIFT 0x6
+#define MC_SEQ_TSM_CTRL__MASK_BITS_MASK 0x80
+#define MC_SEQ_TSM_CTRL__MASK_BITS__SHIFT 0x7
+#define MC_SEQ_TSM_CTRL__UPDATE_LOOP_MASK 0x300
+#define MC_SEQ_TSM_CTRL__UPDATE_LOOP__SHIFT 0x8
+#define MC_SEQ_TSM_CTRL__ROT_INV_MASK 0x400
+#define MC_SEQ_TSM_CTRL__ROT_INV__SHIFT 0xa
+#define MC_SEQ_TSM_CTRL__DUAL_CH_EN_MASK 0x800
+#define MC_SEQ_TSM_CTRL__DUAL_CH_EN__SHIFT 0xb
+#define MC_SEQ_TSM_CTRL__DONE0_MASK 0x1000
+#define MC_SEQ_TSM_CTRL__DONE0__SHIFT 0xc
+#define MC_SEQ_TSM_CTRL__DONE1_MASK 0x2000
+#define MC_SEQ_TSM_CTRL__DONE1__SHIFT 0xd
+#define MC_SEQ_TSM_CTRL__POINTER_MASK 0xffff0000
+#define MC_SEQ_TSM_CTRL__POINTER__SHIFT 0x10
+#define MC_SEQ_TSM_GCNT__TRUE_ACT_MASK 0xf
+#define MC_SEQ_TSM_GCNT__TRUE_ACT__SHIFT 0x0
+#define MC_SEQ_TSM_GCNT__FALSE_ACT_MASK 0xf0
+#define MC_SEQ_TSM_GCNT__FALSE_ACT__SHIFT 0x4
+#define MC_SEQ_TSM_GCNT__TESTS_MASK 0xff00
+#define MC_SEQ_TSM_GCNT__TESTS__SHIFT 0x8
+#define MC_SEQ_TSM_GCNT__COMP_VALUE_MASK 0xffff0000
+#define MC_SEQ_TSM_GCNT__COMP_VALUE__SHIFT 0x10
+#define MC_SEQ_TSM_OCNT__TRUE_ACT_MASK 0xf
+#define MC_SEQ_TSM_OCNT__TRUE_ACT__SHIFT 0x0
+#define MC_SEQ_TSM_OCNT__FALSE_ACT_MASK 0xf0
+#define MC_SEQ_TSM_OCNT__FALSE_ACT__SHIFT 0x4
+#define MC_SEQ_TSM_OCNT__TESTS_MASK 0xff00
+#define MC_SEQ_TSM_OCNT__TESTS__SHIFT 0x8
+#define MC_SEQ_TSM_OCNT__CMP_VALUE_MASK 0xffff0000
+#define MC_SEQ_TSM_OCNT__CMP_VALUE__SHIFT 0x10
+#define MC_SEQ_TSM_NCNT__TRUE_ACT_MASK 0xf
+#define MC_SEQ_TSM_NCNT__TRUE_ACT__SHIFT 0x0
+#define MC_SEQ_TSM_NCNT__FALSE_ACT_MASK 0xf0
+#define MC_SEQ_TSM_NCNT__FALSE_ACT__SHIFT 0x4
+#define MC_SEQ_TSM_NCNT__TESTS_MASK 0xff00
+#define MC_SEQ_TSM_NCNT__TESTS__SHIFT 0x8
+#define MC_SEQ_TSM_NCNT__RANGE_LOW_MASK 0xf0000
+#define MC_SEQ_TSM_NCNT__RANGE_LOW__SHIFT 0x10
+#define MC_SEQ_TSM_NCNT__RANGE_HIGH_MASK 0xf00000
+#define MC_SEQ_TSM_NCNT__RANGE_HIGH__SHIFT 0x14
+#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP_MASK 0xf000000
+#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP__SHIFT 0x18
+#define MC_SEQ_TSM_BCNT__TRUE_ACT_MASK 0xf
+#define MC_SEQ_TSM_BCNT__TRUE_ACT__SHIFT 0x0
+#define MC_SEQ_TSM_BCNT__FALSE_ACT_MASK 0xf0
+#define MC_SEQ_TSM_BCNT__FALSE_ACT__SHIFT 0x4
+#define MC_SEQ_TSM_BCNT__BCNT_TESTS_MASK 0xff00
+#define MC_SEQ_TSM_BCNT__BCNT_TESTS__SHIFT 0x8
+#define MC_SEQ_TSM_BCNT__COMP_VALUE_MASK 0xff0000
+#define MC_SEQ_TSM_BCNT__COMP_VALUE__SHIFT 0x10
+#define MC_SEQ_TSM_BCNT__DONE_TESTS_MASK 0xff000000
+#define MC_SEQ_TSM_BCNT__DONE_TESTS__SHIFT 0x18
+#define MC_SEQ_TSM_FLAG__TRUE_ACT_MASK 0xf
+#define MC_SEQ_TSM_FLAG__TRUE_ACT__SHIFT 0x0
+#define MC_SEQ_TSM_FLAG__FALSE_ACT_MASK 0xf0
+#define MC_SEQ_TSM_FLAG__FALSE_ACT__SHIFT 0x4
+#define MC_SEQ_TSM_FLAG__FLAG_TESTS_MASK 0xff00
+#define MC_SEQ_TSM_FLAG__FLAG_TESTS__SHIFT 0x8
+#define MC_SEQ_TSM_FLAG__NBBL_MASK_MASK 0xf0000
+#define MC_SEQ_TSM_FLAG__NBBL_MASK__SHIFT 0x10
+#define MC_SEQ_TSM_FLAG__ERROR_TESTS_MASK 0xff000000
+#define MC_SEQ_TSM_FLAG__ERROR_TESTS__SHIFT 0x18
+#define MC_SEQ_TSM_UPDATE__TRUE_ACT_MASK 0xf
+#define MC_SEQ_TSM_UPDATE__TRUE_ACT__SHIFT 0x0
+#define MC_SEQ_TSM_UPDATE__FALSE_ACT_MASK 0xf0
+#define MC_SEQ_TSM_UPDATE__FALSE_ACT__SHIFT 0x4
+#define MC_SEQ_TSM_UPDATE__UPDT_TESTS_MASK 0xff00
+#define MC_SEQ_TSM_UPDATE__UPDT_TESTS__SHIFT 0x8
+#define MC_SEQ_TSM_UPDATE__AREF_COUNT_MASK 0xff0000
+#define MC_SEQ_TSM_UPDATE__AREF_COUNT__SHIFT 0x10
+#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS_MASK 0xff000000
+#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS__SHIFT 0x18
+#define MC_SEQ_TSM_EDC__EDC_MASK 0xffffffff
+#define MC_SEQ_TSM_EDC__EDC__SHIFT 0x0
+#define MC_SEQ_TSM_DBI__DBI_MASK 0xffffffff
+#define MC_SEQ_TSM_DBI__DBI__SHIFT 0x0
+#define MC_SEQ_TSM_WCDR__WCDR_MASK 0xffffffff
+#define MC_SEQ_TSM_WCDR__WCDR__SHIFT 0x0
+#define MC_SEQ_TSM_MISC__WCDR_PTR_MASK 0xffff
+#define MC_SEQ_TSM_MISC__WCDR_PTR__SHIFT 0x0
+#define MC_SEQ_TSM_MISC__WCDR_MASK_MASK 0xf0000
+#define MC_SEQ_TSM_MISC__WCDR_MASK__SHIFT 0x10
+#define MC_SEQ_TSM_MISC__CH1_OFFSET_MASK 0x3f00000
+#define MC_SEQ_TSM_MISC__CH1_OFFSET__SHIFT 0x14
+#define MC_SEQ_TSM_MISC__CH1_WCDR_OFFSET_MASK 0xfc000000
+#define MC_SEQ_TSM_MISC__CH1_WCDR_OFFSET__SHIFT 0x1a
+#define MC_SEQ_TIMER_WR__COUNTER_MASK 0xffffffff
+#define MC_SEQ_TIMER_WR__COUNTER__SHIFT 0x0
+#define MC_SEQ_TIMER_RD__COUNTER_MASK 0xffffffff
+#define MC_SEQ_TIMER_RD__COUNTER__SHIFT 0x0
+#define MC_SEQ_DRAM_ERROR_INSERTION__TX_MASK 0xffff
+#define MC_SEQ_DRAM_ERROR_INSERTION__TX__SHIFT 0x0
+#define MC_SEQ_DRAM_ERROR_INSERTION__RX_MASK 0xffff0000
+#define MC_SEQ_DRAM_ERROR_INSERTION__RX__SHIFT 0x10
+#define MC_PHY_TIMING_D0__RXC0_DLY_MASK 0xf
+#define MC_PHY_TIMING_D0__RXC0_DLY__SHIFT 0x0
+#define MC_PHY_TIMING_D0__RXC0_EXT_MASK 0xf0
+#define MC_PHY_TIMING_D0__RXC0_EXT__SHIFT 0x4
+#define MC_PHY_TIMING_D0__RXC1_DLY_MASK 0xf00
+#define MC_PHY_TIMING_D0__RXC1_DLY__SHIFT 0x8
+#define MC_PHY_TIMING_D0__RXC1_EXT_MASK 0xf000
+#define MC_PHY_TIMING_D0__RXC1_EXT__SHIFT 0xc
+#define MC_PHY_TIMING_D0__TXC0_DLY_MASK 0x70000
+#define MC_PHY_TIMING_D0__TXC0_DLY__SHIFT 0x10
+#define MC_PHY_TIMING_D0__TXC0_EXT_MASK 0xf00000
+#define MC_PHY_TIMING_D0__TXC0_EXT__SHIFT 0x14
+#define MC_PHY_TIMING_D0__TXC1_DLY_MASK 0x7000000
+#define MC_PHY_TIMING_D0__TXC1_DLY__SHIFT 0x18
+#define MC_PHY_TIMING_D0__TXC1_EXT_MASK 0xf0000000
+#define MC_PHY_TIMING_D0__TXC1_EXT__SHIFT 0x1c
+#define MC_PHY_TIMING_D1__RXC0_DLY_MASK 0xf
+#define MC_PHY_TIMING_D1__RXC0_DLY__SHIFT 0x0
+#define MC_PHY_TIMING_D1__RXC0_EXT_MASK 0xf0
+#define MC_PHY_TIMING_D1__RXC0_EXT__SHIFT 0x4
+#define MC_PHY_TIMING_D1__RXC1_DLY_MASK 0xf00
+#define MC_PHY_TIMING_D1__RXC1_DLY__SHIFT 0x8
+#define MC_PHY_TIMING_D1__RXC1_EXT_MASK 0xf000
+#define MC_PHY_TIMING_D1__RXC1_EXT__SHIFT 0xc
+#define MC_PHY_TIMING_D1__TXC0_DLY_MASK 0x70000
+#define MC_PHY_TIMING_D1__TXC0_DLY__SHIFT 0x10
+#define MC_PHY_TIMING_D1__TXC0_EXT_MASK 0xf00000
+#define MC_PHY_TIMING_D1__TXC0_EXT__SHIFT 0x14
+#define MC_PHY_TIMING_D1__TXC1_DLY_MASK 0x7000000
+#define MC_PHY_TIMING_D1__TXC1_DLY__SHIFT 0x18
+#define MC_PHY_TIMING_D1__TXC1_EXT_MASK 0xf0000000
+#define MC_PHY_TIMING_D1__TXC1_EXT__SHIFT 0x1c
+#define MC_PHY_TIMING_2__IND_LD_CNT_MASK 0x7f
+#define MC_PHY_TIMING_2__IND_LD_CNT__SHIFT 0x0
+#define MC_PHY_TIMING_2__RXC0_INV_MASK 0x100
+#define MC_PHY_TIMING_2__RXC0_INV__SHIFT 0x8
+#define MC_PHY_TIMING_2__RXC1_INV_MASK 0x200
+#define MC_PHY_TIMING_2__RXC1_INV__SHIFT 0x9
+#define MC_PHY_TIMING_2__TXC0_INV_MASK 0x400
+#define MC_PHY_TIMING_2__TXC0_INV__SHIFT 0xa
+#define MC_PHY_TIMING_2__TXC1_INV_MASK 0x800
+#define MC_PHY_TIMING_2__TXC1_INV__SHIFT 0xb
+#define MC_PHY_TIMING_2__RXC0_FRC_MASK 0x1000
+#define MC_PHY_TIMING_2__RXC0_FRC__SHIFT 0xc
+#define MC_PHY_TIMING_2__RXC1_FRC_MASK 0x2000
+#define MC_PHY_TIMING_2__RXC1_FRC__SHIFT 0xd
+#define MC_PHY_TIMING_2__TXC0_FRC_MASK 0x4000
+#define MC_PHY_TIMING_2__TXC0_FRC__SHIFT 0xe
+#define MC_PHY_TIMING_2__TXC1_FRC_MASK 0x8000
+#define MC_PHY_TIMING_2__TXC1_FRC__SHIFT 0xf
+#define MC_PHY_TIMING_2__TX_CDREN_D0_MASK 0x10000
+#define MC_PHY_TIMING_2__TX_CDREN_D0__SHIFT 0x10
+#define MC_PHY_TIMING_2__TX_CDREN_D1_MASK 0x20000
+#define MC_PHY_TIMING_2__TX_CDREN_D1__SHIFT 0x11
+#define MC_PHY_TIMING_2__ADR_CLKEN_D0_MASK 0x40000
+#define MC_PHY_TIMING_2__ADR_CLKEN_D0__SHIFT 0x12
+#define MC_PHY_TIMING_2__ADR_CLKEN_D1_MASK 0x80000
+#define MC_PHY_TIMING_2__ADR_CLKEN_D1__SHIFT 0x13
+#define MC_PHY_TIMING_2__WR_DLY_MASK 0xf00000
+#define MC_PHY_TIMING_2__WR_DLY__SHIFT 0x14
+#define MC_PHY_TIMING_2__RXDPWRONC0_FRC_MASK 0x1000000
+#define MC_PHY_TIMING_2__RXDPWRONC0_FRC__SHIFT 0x18
+#define MC_PHY_TIMING_2__RXDPWRONC1_FRC_MASK 0x2000000
+#define MC_PHY_TIMING_2__RXDPWRONC1_FRC__SHIFT 0x19
+#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE_MASK 0x1
+#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE__SHIFT 0x0
+#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE_MASK 0x2
+#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE__SHIFT 0x1
+#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE_MASK 0x4
+#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE__SHIFT 0x2
+#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE_MASK 0x8
+#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE__SHIFT 0x3
+#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE_MASK 0x10
+#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE__SHIFT 0x4
+#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE_MASK 0x20
+#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE__SHIFT 0x5
+#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE_MASK 0x40
+#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE__SHIFT 0x6
+#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE_MASK 0x80
+#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE__SHIFT 0x7
+#define MCLK_PWRMGT_CNTL__DLL_SPEED_MASK 0x1f
+#define MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT 0x0
+#define MCLK_PWRMGT_CNTL__DLL_READY_MASK 0x40
+#define MCLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x6
+#define MCLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x80
+#define MCLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x7
+#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK 0x100
+#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB__SHIFT 0x8
+#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK 0x200
+#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB__SHIFT 0x9
+#define MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK 0x10000
+#define MCLK_PWRMGT_CNTL__MRDCK0_RESET__SHIFT 0x10
+#define MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK 0x20000
+#define MCLK_PWRMGT_CNTL__MRDCK1_RESET__SHIFT 0x11
+#define MCLK_PWRMGT_CNTL__DLL_READY_READ_MASK 0x1000000
+#define MCLK_PWRMGT_CNTL__DLL_READY_READ__SHIFT 0x18
+#define DLL_CNTL__DLL_RESET_TIME_MASK 0x3ff
+#define DLL_CNTL__DLL_RESET_TIME__SHIFT 0x0
+#define DLL_CNTL__DLL_LOCK_TIME_MASK 0x3ff000
+#define DLL_CNTL__DLL_LOCK_TIME__SHIFT 0xc
+#define DLL_CNTL__MRDCK0_BYPASS_MASK 0x1000000
+#define DLL_CNTL__MRDCK0_BYPASS__SHIFT 0x18
+#define DLL_CNTL__MRDCK1_BYPASS_MASK 0x2000000
+#define DLL_CNTL__MRDCK1_BYPASS__SHIFT 0x19
+#define DLL_CNTL__PWR2_MODE_MASK 0x4000000
+#define DLL_CNTL__PWR2_MODE__SHIFT 0x1a
+#define MPLL_SEQ_UCODE_1__INSTR0_MASK 0xf
+#define MPLL_SEQ_UCODE_1__INSTR0__SHIFT 0x0
+#define MPLL_SEQ_UCODE_1__INSTR1_MASK 0xf0
+#define MPLL_SEQ_UCODE_1__INSTR1__SHIFT 0x4
+#define MPLL_SEQ_UCODE_1__INSTR2_MASK 0xf00
+#define MPLL_SEQ_UCODE_1__INSTR2__SHIFT 0x8
+#define MPLL_SEQ_UCODE_1__INSTR3_MASK 0xf000
+#define MPLL_SEQ_UCODE_1__INSTR3__SHIFT 0xc
+#define MPLL_SEQ_UCODE_1__INSTR4_MASK 0xf0000
+#define MPLL_SEQ_UCODE_1__INSTR4__SHIFT 0x10
+#define MPLL_SEQ_UCODE_1__INSTR5_MASK 0xf00000
+#define MPLL_SEQ_UCODE_1__INSTR5__SHIFT 0x14
+#define MPLL_SEQ_UCODE_1__INSTR6_MASK 0xf000000
+#define MPLL_SEQ_UCODE_1__INSTR6__SHIFT 0x18
+#define MPLL_SEQ_UCODE_1__INSTR7_MASK 0xf0000000
+#define MPLL_SEQ_UCODE_1__INSTR7__SHIFT 0x1c
+#define MPLL_SEQ_UCODE_2__INSTR8_MASK 0xf
+#define MPLL_SEQ_UCODE_2__INSTR8__SHIFT 0x0
+#define MPLL_SEQ_UCODE_2__INSTR9_MASK 0xf0
+#define MPLL_SEQ_UCODE_2__INSTR9__SHIFT 0x4
+#define MPLL_SEQ_UCODE_2__INSTR10_MASK 0xf00
+#define MPLL_SEQ_UCODE_2__INSTR10__SHIFT 0x8
+#define MPLL_SEQ_UCODE_2__INSTR11_MASK 0xf000
+#define MPLL_SEQ_UCODE_2__INSTR11__SHIFT 0xc
+#define MPLL_SEQ_UCODE_2__INSTR12_MASK 0xf0000
+#define MPLL_SEQ_UCODE_2__INSTR12__SHIFT 0x10
+#define MPLL_SEQ_UCODE_2__INSTR13_MASK 0xf00000
+#define MPLL_SEQ_UCODE_2__INSTR13__SHIFT 0x14
+#define MPLL_SEQ_UCODE_2__INSTR14_MASK 0xf000000
+#define MPLL_SEQ_UCODE_2__INSTR14__SHIFT 0x18
+#define MPLL_SEQ_UCODE_2__INSTR15_MASK 0xf0000000
+#define MPLL_SEQ_UCODE_2__INSTR15__SHIFT 0x1c
+#define MPLL_CNTL_MODE__INSTR_DELAY_MASK 0xff
+#define MPLL_CNTL_MODE__INSTR_DELAY__SHIFT 0x0
+#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK 0x100
+#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT 0x8
+#define MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK 0x800
+#define MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT 0xb
+#define MPLL_CNTL_MODE__SPARE_1_MASK 0x1000
+#define MPLL_CNTL_MODE__SPARE_1__SHIFT 0xc
+#define MPLL_CNTL_MODE__QDR_MASK 0x2000
+#define MPLL_CNTL_MODE__QDR__SHIFT 0xd
+#define MPLL_CNTL_MODE__MPLL_CTLREQ_MASK 0x4000
+#define MPLL_CNTL_MODE__MPLL_CTLREQ__SHIFT 0xe
+#define MPLL_CNTL_MODE__MPLL_CHG_STATUS_MASK 0x10000
+#define MPLL_CNTL_MODE__MPLL_CHG_STATUS__SHIFT 0x10
+#define MPLL_CNTL_MODE__FORCE_TESTMODE_MASK 0x20000
+#define MPLL_CNTL_MODE__FORCE_TESTMODE__SHIFT 0x11
+#define MPLL_CNTL_MODE__FAST_LOCK_EN_MASK 0x100000
+#define MPLL_CNTL_MODE__FAST_LOCK_EN__SHIFT 0x14
+#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL_MASK 0x600000
+#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL__SHIFT 0x15
+#define MPLL_CNTL_MODE__SPARE_2_MASK 0x800000
+#define MPLL_CNTL_MODE__SPARE_2__SHIFT 0x17
+#define MPLL_CNTL_MODE__SS_SSEN_MASK 0x3000000
+#define MPLL_CNTL_MODE__SS_SSEN__SHIFT 0x18
+#define MPLL_CNTL_MODE__SS_DSMODE_EN_MASK 0x4000000
+#define MPLL_CNTL_MODE__SS_DSMODE_EN__SHIFT 0x1a
+#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL_MASK 0x8000000
+#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL__SHIFT 0x1b
+#define MPLL_CNTL_MODE__SPARE_3_MASK 0x70000000
+#define MPLL_CNTL_MODE__SPARE_3__SHIFT 0x1c
+#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET_MASK 0x80000000
+#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET__SHIFT 0x1f
+#define MPLL_FUNC_CNTL__SPARE_0_MASK 0x20
+#define MPLL_FUNC_CNTL__SPARE_0__SHIFT 0x5
+#define MPLL_FUNC_CNTL__BG_100ADJ_MASK 0xf00
+#define MPLL_FUNC_CNTL__BG_100ADJ__SHIFT 0x8
+#define MPLL_FUNC_CNTL__BG_135ADJ_MASK 0xf0000
+#define MPLL_FUNC_CNTL__BG_135ADJ__SHIFT 0x10
+#define MPLL_FUNC_CNTL__BWCTRL_MASK 0xff00000
+#define MPLL_FUNC_CNTL__BWCTRL__SHIFT 0x14
+#define MPLL_FUNC_CNTL__REG_BIAS_MASK 0xc0000000
+#define MPLL_FUNC_CNTL__REG_BIAS__SHIFT 0x1e
+#define MPLL_FUNC_CNTL_1__VCO_MODE_MASK 0x3
+#define MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT 0x0
+#define MPLL_FUNC_CNTL_1__SPARE_0_MASK 0xc
+#define MPLL_FUNC_CNTL_1__SPARE_0__SHIFT 0x2
+#define MPLL_FUNC_CNTL_1__CLKFRAC_MASK 0xfff0
+#define MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT 0x4
+#define MPLL_FUNC_CNTL_1__CLKF_MASK 0xfff0000
+#define MPLL_FUNC_CNTL_1__CLKF__SHIFT 0x10
+#define MPLL_FUNC_CNTL_1__SPARE_1_MASK 0xf0000000
+#define MPLL_FUNC_CNTL_1__SPARE_1__SHIFT 0x1c
+#define MPLL_FUNC_CNTL_2__VCTRLADC_EN_MASK 0x1
+#define MPLL_FUNC_CNTL_2__VCTRLADC_EN__SHIFT 0x0
+#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN_MASK 0x2
+#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN__SHIFT 0x1
+#define MPLL_FUNC_CNTL_2__RESET_EN_MASK 0x4
+#define MPLL_FUNC_CNTL_2__RESET_EN__SHIFT 0x2
+#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN_MASK 0x8
+#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN__SHIFT 0x3
+#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC_MASK 0x10
+#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC__SHIFT 0x4
+#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS_MASK 0x20
+#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS__SHIFT 0x5
+#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK_MASK 0x40
+#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK__SHIFT 0x6
+#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR_MASK 0x80
+#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR__SHIFT 0x7
+#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL_MASK 0x100
+#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL__SHIFT 0x8
+#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS_MASK 0x200
+#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS__SHIFT 0x9
+#define MPLL_FUNC_CNTL_2__RESET_TIMER_MASK 0xc00
+#define MPLL_FUNC_CNTL_2__RESET_TIMER__SHIFT 0xa
+#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL_MASK 0x3000
+#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL__SHIFT 0xc
+#define MPLL_FUNC_CNTL_2__RISEFBVCO_EN_MASK 0x4000
+#define MPLL_FUNC_CNTL_2__RISEFBVCO_EN__SHIFT 0xe
+#define MPLL_FUNC_CNTL_2__PWRGOOD_OVR_MASK 0x8000
+#define MPLL_FUNC_CNTL_2__PWRGOOD_OVR__SHIFT 0xf
+#define MPLL_FUNC_CNTL_2__ISO_DIS_P_MASK 0x10000
+#define MPLL_FUNC_CNTL_2__ISO_DIS_P__SHIFT 0x10
+#define MPLL_FUNC_CNTL_2__BACKUP_2_MASK 0xe0000
+#define MPLL_FUNC_CNTL_2__BACKUP_2__SHIFT 0x11
+#define MPLL_FUNC_CNTL_2__LF_CNTRL_MASK 0x7f00000
+#define MPLL_FUNC_CNTL_2__LF_CNTRL__SHIFT 0x14
+#define MPLL_FUNC_CNTL_2__BACKUP_MASK 0xf8000000
+#define MPLL_FUNC_CNTL_2__BACKUP__SHIFT 0x1b
+#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK 0x7
+#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x0
+#define MPLL_AD_FUNC_CNTL__SPARE_MASK 0xfffffff8
+#define MPLL_AD_FUNC_CNTL__SPARE__SHIFT 0x3
+#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV_MASK 0x7
+#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x0
+#define MPLL_DQ_FUNC_CNTL__SPARE_0_MASK 0x8
+#define MPLL_DQ_FUNC_CNTL__SPARE_0__SHIFT 0x3
+#define MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK 0x10
+#define MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT 0x4
+#define MPLL_DQ_FUNC_CNTL__SPARE_MASK 0xffffffe0
+#define MPLL_DQ_FUNC_CNTL__SPARE__SHIFT 0x5
+#define MPLL_TIME__MPLL_LOCK_TIME_MASK 0xffff
+#define MPLL_TIME__MPLL_LOCK_TIME__SHIFT 0x0
+#define MPLL_TIME__MPLL_RESET_TIME_MASK 0xffff0000
+#define MPLL_TIME__MPLL_RESET_TIME__SHIFT 0x10
+#define MPLL_SS1__CLKV_MASK 0x3ffffff
+#define MPLL_SS1__CLKV__SHIFT 0x0
+#define MPLL_SS1__SPARE_MASK 0xfc000000
+#define MPLL_SS1__SPARE__SHIFT 0x1a
+#define MPLL_SS2__CLKS_MASK 0xfff
+#define MPLL_SS2__CLKS__SHIFT 0x0
+#define MPLL_SS2__SPARE_MASK 0xfffff000
+#define MPLL_SS2__SPARE__SHIFT 0xc
+#define MPLL_CONTROL__GDDR_PWRON_MASK 0x1
+#define MPLL_CONTROL__GDDR_PWRON__SHIFT 0x0
+#define MPLL_CONTROL__REFCLK_PWRON_MASK 0x2
+#define MPLL_CONTROL__REFCLK_PWRON__SHIFT 0x1
+#define MPLL_CONTROL__PLL_BUF_PWRON_TX_MASK 0x4
+#define MPLL_CONTROL__PLL_BUF_PWRON_TX__SHIFT 0x2
+#define MPLL_CONTROL__AD_BG_PWRON_MASK 0x1000
+#define MPLL_CONTROL__AD_BG_PWRON__SHIFT 0xc
+#define MPLL_CONTROL__AD_PLL_PWRON_MASK 0x2000
+#define MPLL_CONTROL__AD_PLL_PWRON__SHIFT 0xd
+#define MPLL_CONTROL__AD_PLL_RESET_MASK 0x4000
+#define MPLL_CONTROL__AD_PLL_RESET__SHIFT 0xe
+#define MPLL_CONTROL__SPARE_AD_0_MASK 0x8000
+#define MPLL_CONTROL__SPARE_AD_0__SHIFT 0xf
+#define MPLL_CONTROL__DQ_0_0_BG_PWRON_MASK 0x10000
+#define MPLL_CONTROL__DQ_0_0_BG_PWRON__SHIFT 0x10
+#define MPLL_CONTROL__DQ_0_0_PLL_PWRON_MASK 0x20000
+#define MPLL_CONTROL__DQ_0_0_PLL_PWRON__SHIFT 0x11
+#define MPLL_CONTROL__DQ_0_0_PLL_RESET_MASK 0x40000
+#define MPLL_CONTROL__DQ_0_0_PLL_RESET__SHIFT 0x12
+#define MPLL_CONTROL__SPARE_DQ_0_0_MASK 0x80000
+#define MPLL_CONTROL__SPARE_DQ_0_0__SHIFT 0x13
+#define MPLL_CONTROL__DQ_0_1_BG_PWRON_MASK 0x100000
+#define MPLL_CONTROL__DQ_0_1_BG_PWRON__SHIFT 0x14
+#define MPLL_CONTROL__DQ_0_1_PLL_PWRON_MASK 0x200000
+#define MPLL_CONTROL__DQ_0_1_PLL_PWRON__SHIFT 0x15
+#define MPLL_CONTROL__DQ_0_1_PLL_RESET_MASK 0x400000
+#define MPLL_CONTROL__DQ_0_1_PLL_RESET__SHIFT 0x16
+#define MPLL_CONTROL__SPARE_DQ_0_1_MASK 0x800000
+#define MPLL_CONTROL__SPARE_DQ_0_1__SHIFT 0x17
+#define MPLL_CONTROL__DQ_1_0_BG_PWRON_MASK 0x1000000
+#define MPLL_CONTROL__DQ_1_0_BG_PWRON__SHIFT 0x18
+#define MPLL_CONTROL__DQ_1_0_PLL_PWRON_MASK 0x2000000
+#define MPLL_CONTROL__DQ_1_0_PLL_PWRON__SHIFT 0x19
+#define MPLL_CONTROL__DQ_1_0_PLL_RESET_MASK 0x4000000
+#define MPLL_CONTROL__DQ_1_0_PLL_RESET__SHIFT 0x1a
+#define MPLL_CONTROL__SPARE_DQ_1_0_MASK 0x8000000
+#define MPLL_CONTROL__SPARE_DQ_1_0__SHIFT 0x1b
+#define MPLL_CONTROL__DQ_1_1_BG_PWRON_MASK 0x10000000
+#define MPLL_CONTROL__DQ_1_1_BG_PWRON__SHIFT 0x1c
+#define MPLL_CONTROL__DQ_1_1_PLL_PWRON_MASK 0x20000000
+#define MPLL_CONTROL__DQ_1_1_PLL_PWRON__SHIFT 0x1d
+#define MPLL_CONTROL__DQ_1_1_PLL_RESET_MASK 0x40000000
+#define MPLL_CONTROL__DQ_1_1_PLL_RESET__SHIFT 0x1e
+#define MPLL_CONTROL__SPARE_DQ_1_1_MASK 0x80000000
+#define MPLL_CONTROL__SPARE_DQ_1_1__SHIFT 0x1f
+#define MPLL_AD_STATUS__VCTRLADC_MASK 0x7
+#define MPLL_AD_STATUS__VCTRLADC__SHIFT 0x0
+#define MPLL_AD_STATUS__TEST_FBDIV_FRAC_MASK 0x70
+#define MPLL_AD_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
+#define MPLL_AD_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
+#define MPLL_AD_STATUS__TEST_FBDIV_INT__SHIFT 0x7
+#define MPLL_AD_STATUS__OINT_RESET_MASK 0x20000
+#define MPLL_AD_STATUS__OINT_RESET__SHIFT 0x11
+#define MPLL_AD_STATUS__FREQ_LOCK_MASK 0x40000
+#define MPLL_AD_STATUS__FREQ_LOCK__SHIFT 0x12
+#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
+#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
+#define MPLL_DQ_0_0_STATUS__VCTRLADC_MASK 0x7
+#define MPLL_DQ_0_0_STATUS__VCTRLADC__SHIFT 0x0
+#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC_MASK 0x70
+#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
+#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
+#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT__SHIFT 0x7
+#define MPLL_DQ_0_0_STATUS__OINT_RESET_MASK 0x20000
+#define MPLL_DQ_0_0_STATUS__OINT_RESET__SHIFT 0x11
+#define MPLL_DQ_0_0_STATUS__FREQ_LOCK_MASK 0x40000
+#define MPLL_DQ_0_0_STATUS__FREQ_LOCK__SHIFT 0x12
+#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
+#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
+#define MPLL_DQ_0_1_STATUS__VCTRLADC_MASK 0x7
+#define MPLL_DQ_0_1_STATUS__VCTRLADC__SHIFT 0x0
+#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC_MASK 0x70
+#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
+#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
+#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT__SHIFT 0x7
+#define MPLL_DQ_0_1_STATUS__OINT_RESET_MASK 0x20000
+#define MPLL_DQ_0_1_STATUS__OINT_RESET__SHIFT 0x11
+#define MPLL_DQ_0_1_STATUS__FREQ_LOCK_MASK 0x40000
+#define MPLL_DQ_0_1_STATUS__FREQ_LOCK__SHIFT 0x12
+#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
+#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
+#define MPLL_DQ_1_0_STATUS__VCTRLADC_MASK 0x7
+#define MPLL_DQ_1_0_STATUS__VCTRLADC__SHIFT 0x0
+#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC_MASK 0x70
+#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
+#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
+#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT__SHIFT 0x7
+#define MPLL_DQ_1_0_STATUS__OINT_RESET_MASK 0x20000
+#define MPLL_DQ_1_0_STATUS__OINT_RESET__SHIFT 0x11
+#define MPLL_DQ_1_0_STATUS__FREQ_LOCK_MASK 0x40000
+#define MPLL_DQ_1_0_STATUS__FREQ_LOCK__SHIFT 0x12
+#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
+#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
+#define MPLL_DQ_1_1_STATUS__VCTRLADC_MASK 0x7
+#define MPLL_DQ_1_1_STATUS__VCTRLADC__SHIFT 0x0
+#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC_MASK 0x70
+#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
+#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
+#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT__SHIFT 0x7
+#define MPLL_DQ_1_1_STATUS__OINT_RESET_MASK 0x20000
+#define MPLL_DQ_1_1_STATUS__OINT_RESET__SHIFT 0x11
+#define MPLL_DQ_1_1_STATUS__FREQ_LOCK_MASK 0x40000
+#define MPLL_DQ_1_1_STATUS__FREQ_LOCK__SHIFT 0x12
+#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
+#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
+#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN_MASK 0x1
+#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN__SHIFT 0x0
+#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN_MASK 0x2
+#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN__SHIFT 0x1
+#define MC_SEQ_PMG_PG_HWCNTL__TPGCG_MASK 0x3c
+#define MC_SEQ_PMG_PG_HWCNTL__TPGCG__SHIFT 0x2
+#define MC_SEQ_PMG_PG_HWCNTL__D_DLY_MASK 0xc0
+#define MC_SEQ_PMG_PG_HWCNTL__D_DLY__SHIFT 0x6
+#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY_MASK 0x300
+#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY__SHIFT 0x8
+#define MC_SEQ_PMG_PG_HWCNTL__G_DLY_MASK 0x3c00
+#define MC_SEQ_PMG_PG_HWCNTL__G_DLY__SHIFT 0xa
+#define MC_SEQ_PMG_PG_HWCNTL__TXAO_MASK 0x10000
+#define MC_SEQ_PMG_PG_HWCNTL__TXAO__SHIFT 0x10
+#define MC_SEQ_PMG_PG_HWCNTL__RXAO_MASK 0x20000
+#define MC_SEQ_PMG_PG_HWCNTL__RXAO__SHIFT 0x11
+#define MC_SEQ_PMG_PG_HWCNTL__ACAO_MASK 0x40000
+#define MC_SEQ_PMG_PG_HWCNTL__ACAO__SHIFT 0x12
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB_MASK 0x1
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB__SHIFT 0x0
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB_MASK 0x2
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB__SHIFT 0x1
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB_MASK 0x4
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB__SHIFT 0x2
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB_MASK 0x8
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB__SHIFT 0x3
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB_MASK 0x10
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB__SHIFT 0x4
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB_MASK 0x20
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB__SHIFT 0x5
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB_MASK 0x40
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB__SHIFT 0x6
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB_MASK 0x80
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB__SHIFT 0x7
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB_MASK 0x100
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB__SHIFT 0x8
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB_MASK 0x200
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB__SHIFT 0x9
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB_MASK 0x400
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB__SHIFT 0xa
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB_MASK 0x800
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB__SHIFT 0xb
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB_MASK 0x1000
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB__SHIFT 0xc
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB_MASK 0x2000
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB__SHIFT 0xd
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB_MASK 0x4000
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB__SHIFT 0xe
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB_MASK 0x8000
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB__SHIFT 0xf
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB_MASK 0x10000
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB__SHIFT 0x10
+#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT_MASK 0x80000000
+#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT__SHIFT 0x1f
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB_MASK 0x1
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB__SHIFT 0x0
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB_MASK 0x2
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB__SHIFT 0x1
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB_MASK 0x4
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB__SHIFT 0x2
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB_MASK 0x8
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB__SHIFT 0x3
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB_MASK 0x10
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB__SHIFT 0x4
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB_MASK 0x20
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB__SHIFT 0x5
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB_MASK 0x40
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB__SHIFT 0x6
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB_MASK 0x80
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB__SHIFT 0x7
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB_MASK 0x100
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB__SHIFT 0x8
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB_MASK 0x200
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB__SHIFT 0x9
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB_MASK 0x400
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB__SHIFT 0xa
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB_MASK 0x800
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB__SHIFT 0xb
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB_MASK 0x1000
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB__SHIFT 0xc
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB_MASK 0x2000
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB__SHIFT 0xd
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB_MASK 0x4000
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB__SHIFT 0xe
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB_MASK 0x8000
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB__SHIFT 0xf
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB_MASK 0x10000
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB__SHIFT 0x10
+#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT_MASK 0x80000000
+#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT__SHIFT 0x1f
+#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX_MASK 0x1f
+#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX__SHIFT 0x0
+#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA_MASK 0xffffffff
+#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA__SHIFT 0x0
+#define MC_TSM_DEBUG_GCNT__DATA_MASK 0xffffffff
+#define MC_TSM_DEBUG_GCNT__DATA__SHIFT 0x0
+#define MC_TSM_DEBUG_FLAG__DATA_MASK 0xffffffff
+#define MC_TSM_DEBUG_FLAG__DATA__SHIFT 0x0
+#define MC_TSM_DEBUG_MISC__FLAG_MASK 0xff
+#define MC_TSM_DEBUG_MISC__FLAG__SHIFT 0x0
+#define MC_TSM_DEBUG_MISC__NCNT_RD_MASK 0xf00
+#define MC_TSM_DEBUG_MISC__NCNT_RD__SHIFT 0x8
+#define MC_TSM_DEBUG_MISC__NCNT_WR_MASK 0xf000
+#define MC_TSM_DEBUG_MISC__NCNT_WR__SHIFT 0xc
+#define MC_TSM_DEBUG_BCNT0__BYTE0_MASK 0xff
+#define MC_TSM_DEBUG_BCNT0__BYTE0__SHIFT 0x0
+#define MC_TSM_DEBUG_BCNT0__BYTE1_MASK 0xff00
+#define MC_TSM_DEBUG_BCNT0__BYTE1__SHIFT 0x8
+#define MC_TSM_DEBUG_BCNT0__BYTE2_MASK 0xff0000
+#define MC_TSM_DEBUG_BCNT0__BYTE2__SHIFT 0x10
+#define MC_TSM_DEBUG_BCNT0__BYTE3_MASK 0xff000000
+#define MC_TSM_DEBUG_BCNT0__BYTE3__SHIFT 0x18
+#define MC_TSM_DEBUG_BCNT1__BYTE0_MASK 0xff
+#define MC_TSM_DEBUG_BCNT1__BYTE0__SHIFT 0x0
+#define MC_TSM_DEBUG_BCNT1__BYTE1_MASK 0xff00
+#define MC_TSM_DEBUG_BCNT1__BYTE1__SHIFT 0x8
+#define MC_TSM_DEBUG_BCNT1__BYTE2_MASK 0xff0000
+#define MC_TSM_DEBUG_BCNT1__BYTE2__SHIFT 0x10
+#define MC_TSM_DEBUG_BCNT1__BYTE3_MASK 0xff000000
+#define MC_TSM_DEBUG_BCNT1__BYTE3__SHIFT 0x18
+#define MC_TSM_DEBUG_BCNT2__BYTE0_MASK 0xff
+#define MC_TSM_DEBUG_BCNT2__BYTE0__SHIFT 0x0
+#define MC_TSM_DEBUG_BCNT2__BYTE1_MASK 0xff00
+#define MC_TSM_DEBUG_BCNT2__BYTE1__SHIFT 0x8
+#define MC_TSM_DEBUG_BCNT2__BYTE2_MASK 0xff0000
+#define MC_TSM_DEBUG_BCNT2__BYTE2__SHIFT 0x10
+#define MC_TSM_DEBUG_BCNT2__BYTE3_MASK 0xff000000
+#define MC_TSM_DEBUG_BCNT2__BYTE3__SHIFT 0x18
+#define MC_TSM_DEBUG_BCNT3__BYTE0_MASK 0xff
+#define MC_TSM_DEBUG_BCNT3__BYTE0__SHIFT 0x0
+#define MC_TSM_DEBUG_BCNT3__BYTE1_MASK 0xff00
+#define MC_TSM_DEBUG_BCNT3__BYTE1__SHIFT 0x8
+#define MC_TSM_DEBUG_BCNT3__BYTE2_MASK 0xff0000
+#define MC_TSM_DEBUG_BCNT3__BYTE2__SHIFT 0x10
+#define MC_TSM_DEBUG_BCNT3__BYTE3_MASK 0xff000000
+#define MC_TSM_DEBUG_BCNT3__BYTE3__SHIFT 0x18
+#define MC_TSM_DEBUG_BCNT4__BYTE0_MASK 0xff
+#define MC_TSM_DEBUG_BCNT4__BYTE0__SHIFT 0x0
+#define MC_TSM_DEBUG_BCNT4__BYTE1_MASK 0xff00
+#define MC_TSM_DEBUG_BCNT4__BYTE1__SHIFT 0x8
+#define MC_TSM_DEBUG_BCNT4__BYTE2_MASK 0xff0000
+#define MC_TSM_DEBUG_BCNT4__BYTE2__SHIFT 0x10
+#define MC_TSM_DEBUG_BCNT4__BYTE3_MASK 0xff000000
+#define MC_TSM_DEBUG_BCNT4__BYTE3__SHIFT 0x18
+#define MC_TSM_DEBUG_BCNT5__BYTE0_MASK 0xff
+#define MC_TSM_DEBUG_BCNT5__BYTE0__SHIFT 0x0
+#define MC_TSM_DEBUG_BCNT5__BYTE1_MASK 0xff00
+#define MC_TSM_DEBUG_BCNT5__BYTE1__SHIFT 0x8
+#define MC_TSM_DEBUG_BCNT5__BYTE2_MASK 0xff0000
+#define MC_TSM_DEBUG_BCNT5__BYTE2__SHIFT 0x10
+#define MC_TSM_DEBUG_BCNT5__BYTE3_MASK 0xff000000
+#define MC_TSM_DEBUG_BCNT5__BYTE3__SHIFT 0x18
+#define MC_TSM_DEBUG_BCNT6__BYTE0_MASK 0xff
+#define MC_TSM_DEBUG_BCNT6__BYTE0__SHIFT 0x0
+#define MC_TSM_DEBUG_BCNT6__BYTE1_MASK 0xff00
+#define MC_TSM_DEBUG_BCNT6__BYTE1__SHIFT 0x8
+#define MC_TSM_DEBUG_BCNT6__BYTE2_MASK 0xff0000
+#define MC_TSM_DEBUG_BCNT6__BYTE2__SHIFT 0x10
+#define MC_TSM_DEBUG_BCNT6__BYTE3_MASK 0xff000000
+#define MC_TSM_DEBUG_BCNT6__BYTE3__SHIFT 0x18
+#define MC_TSM_DEBUG_BCNT7__BYTE0_MASK 0xff
+#define MC_TSM_DEBUG_BCNT7__BYTE0__SHIFT 0x0
+#define MC_TSM_DEBUG_BCNT7__BYTE1_MASK 0xff00
+#define MC_TSM_DEBUG_BCNT7__BYTE1__SHIFT 0x8
+#define MC_TSM_DEBUG_BCNT7__BYTE2_MASK 0xff0000
+#define MC_TSM_DEBUG_BCNT7__BYTE2__SHIFT 0x10
+#define MC_TSM_DEBUG_BCNT7__BYTE3_MASK 0xff000000
+#define MC_TSM_DEBUG_BCNT7__BYTE3__SHIFT 0x18
+#define MC_TSM_DEBUG_BCNT8__BYTE0_MASK 0xff
+#define MC_TSM_DEBUG_BCNT8__BYTE0__SHIFT 0x0
+#define MC_TSM_DEBUG_BCNT8__BYTE1_MASK 0xff00
+#define MC_TSM_DEBUG_BCNT8__BYTE1__SHIFT 0x8
+#define MC_TSM_DEBUG_BCNT8__BYTE2_MASK 0xff0000
+#define MC_TSM_DEBUG_BCNT8__BYTE2__SHIFT 0x10
+#define MC_TSM_DEBUG_BCNT8__BYTE3_MASK 0xff000000
+#define MC_TSM_DEBUG_BCNT8__BYTE3__SHIFT 0x18
+#define MC_TSM_DEBUG_BCNT9__BYTE0_MASK 0xff
+#define MC_TSM_DEBUG_BCNT9__BYTE0__SHIFT 0x0
+#define MC_TSM_DEBUG_BCNT9__BYTE1_MASK 0xff00
+#define MC_TSM_DEBUG_BCNT9__BYTE1__SHIFT 0x8
+#define MC_TSM_DEBUG_BCNT9__BYTE2_MASK 0xff0000
+#define MC_TSM_DEBUG_BCNT9__BYTE2__SHIFT 0x10
+#define MC_TSM_DEBUG_BCNT9__BYTE3_MASK 0xff000000
+#define MC_TSM_DEBUG_BCNT9__BYTE3__SHIFT 0x18
+#define MC_TSM_DEBUG_BCNT10__BYTE0_MASK 0xff
+#define MC_TSM_DEBUG_BCNT10__BYTE0__SHIFT 0x0
+#define MC_TSM_DEBUG_BCNT10__BYTE1_MASK 0xff00
+#define MC_TSM_DEBUG_BCNT10__BYTE1__SHIFT 0x8
+#define MC_TSM_DEBUG_BCNT10__BYTE2_MASK 0xff0000
+#define MC_TSM_DEBUG_BCNT10__BYTE2__SHIFT 0x10
+#define MC_TSM_DEBUG_BCNT10__BYTE3_MASK 0xff000000
+#define MC_TSM_DEBUG_BCNT10__BYTE3__SHIFT 0x18
+#define MC_TSM_DEBUG_ST01__DATA_MASK 0xffffffff
+#define MC_TSM_DEBUG_ST01__DATA__SHIFT 0x0
+#define MC_TSM_DEBUG_ST23__DATA_MASK 0xffffffff
+#define MC_TSM_DEBUG_ST23__DATA__SHIFT 0x0
+#define MC_TSM_DEBUG_ST45__DATA_MASK 0xffffffff
+#define MC_TSM_DEBUG_ST45__DATA__SHIFT 0x0
+#define MC_TSM_DEBUG_BKPT__DATA_MASK 0xffffffff
+#define MC_TSM_DEBUG_BKPT__DATA__SHIFT 0x0
+#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX_MASK 0x1ff
+#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX__SHIFT 0x0
+#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA_MASK 0xffffffff
+#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA__SHIFT 0x0
+#define MC_IO_DEBUG_UP_0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_2__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_2__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_2__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_2__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_2__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_2__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_2__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_2__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_3__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_3__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_3__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_3__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_3__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_3__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_3__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_3__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_4__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_4__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_4__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_4__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_4__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_4__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_4__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_4__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_5__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_5__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_5__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_5__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_5__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_5__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_5__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_5__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_6__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_6__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_6__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_6__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_6__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_6__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_6__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_6__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_7__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_7__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_7__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_7__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_7__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_7__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_7__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_7__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_8__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_8__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_8__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_8__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_8__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_8__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_8__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_8__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_9__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_9__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_9__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_9__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_9__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_9__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_9__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_9__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_10__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_10__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_10__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_10__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_10__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_10__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_10__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_10__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_11__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_11__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_11__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_11__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_11__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_11__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_11__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_11__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_12__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_12__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_12__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_12__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_12__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_12__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_12__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_12__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_13__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_13__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_13__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_13__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_13__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_13__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_13__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_13__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_14__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_14__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_14__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_14__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_14__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_14__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_14__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_14__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_15__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_15__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_15__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_15__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_15__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_15__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_15__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_15__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_16__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_16__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_16__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_16__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_16__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_16__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_16__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_16__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_17__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_17__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_17__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_17__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_17__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_17__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_17__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_17__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_18__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_18__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_18__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_18__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_18__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_18__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_18__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_18__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_19__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_19__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_19__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_19__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_19__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_19__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_19__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_19__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_20__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_20__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_20__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_20__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_20__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_20__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_20__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_20__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_21__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_21__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_21__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_21__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_21__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_21__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_21__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_21__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_22__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_22__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_22__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_22__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_22__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_22__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_22__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_22__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_23__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_23__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_23__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_23__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_23__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_23__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_23__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_23__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_24__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_24__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_24__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_24__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_24__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_24__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_24__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_24__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_25__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_25__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_25__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_25__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_25__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_25__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_25__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_25__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_26__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_26__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_26__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_26__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_26__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_26__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_26__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_26__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_27__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_27__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_27__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_27__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_27__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_27__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_27__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_27__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_28__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_28__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_28__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_28__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_28__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_28__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_28__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_28__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_29__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_29__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_29__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_29__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_29__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_29__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_29__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_29__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_30__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_30__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_30__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_30__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_30__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_30__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_30__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_30__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_31__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_31__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_31__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_31__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_31__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_31__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_31__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_31__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_32__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_32__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_32__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_32__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_32__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_32__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_32__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_32__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_33__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_33__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_33__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_33__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_33__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_33__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_33__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_33__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_34__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_34__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_34__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_34__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_34__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_34__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_34__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_34__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_35__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_35__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_35__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_35__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_35__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_35__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_35__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_35__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_36__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_36__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_36__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_36__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_36__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_36__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_36__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_36__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_37__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_37__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_37__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_37__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_37__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_37__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_37__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_37__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_38__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_38__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_38__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_38__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_38__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_38__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_38__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_38__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_39__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_39__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_39__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_39__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_39__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_39__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_39__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_39__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_40__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_40__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_40__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_40__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_40__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_40__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_40__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_40__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_41__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_41__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_41__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_41__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_41__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_41__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_41__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_41__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_42__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_42__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_42__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_42__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_42__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_42__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_42__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_42__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_43__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_43__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_43__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_43__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_43__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_43__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_43__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_43__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_44__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_44__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_44__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_44__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_44__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_44__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_44__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_44__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_45__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_45__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_45__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_45__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_45__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_45__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_45__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_45__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_46__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_46__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_46__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_46__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_46__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_46__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_46__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_46__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_47__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_47__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_47__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_47__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_47__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_47__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_47__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_47__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_48__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_48__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_48__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_48__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_48__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_48__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_48__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_48__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_49__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_49__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_49__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_49__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_49__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_49__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_49__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_49__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_50__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_50__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_50__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_50__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_50__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_50__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_50__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_50__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_51__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_51__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_51__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_51__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_51__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_51__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_51__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_51__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_52__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_52__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_52__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_52__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_52__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_52__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_52__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_52__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_53__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_53__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_53__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_53__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_53__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_53__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_53__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_53__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_54__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_54__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_54__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_54__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_54__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_54__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_54__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_54__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_55__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_55__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_55__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_55__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_55__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_55__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_55__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_55__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_56__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_56__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_56__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_56__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_56__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_56__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_56__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_56__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_57__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_57__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_57__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_57__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_57__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_57__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_57__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_57__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_58__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_58__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_58__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_58__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_58__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_58__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_58__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_58__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_59__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_59__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_59__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_59__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_59__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_59__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_59__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_59__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_60__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_60__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_60__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_60__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_60__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_60__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_60__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_60__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_61__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_61__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_61__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_61__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_61__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_61__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_61__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_61__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_62__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_62__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_62__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_62__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_62__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_62__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_62__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_62__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_63__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_63__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_63__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_63__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_63__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_63__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_63__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_63__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_64__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_64__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_64__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_64__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_64__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_64__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_64__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_64__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_65__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_65__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_65__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_65__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_65__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_65__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_65__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_65__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_66__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_66__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_66__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_66__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_66__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_66__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_66__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_66__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_67__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_67__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_67__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_67__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_67__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_67__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_67__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_67__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_68__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_68__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_68__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_68__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_68__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_68__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_68__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_68__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_69__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_69__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_69__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_69__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_69__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_69__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_69__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_69__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_70__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_70__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_70__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_70__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_70__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_70__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_70__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_70__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_71__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_71__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_71__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_71__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_71__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_71__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_71__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_71__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_72__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_72__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_72__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_72__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_72__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_72__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_72__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_72__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_73__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_73__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_73__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_73__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_73__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_73__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_73__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_73__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_74__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_74__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_74__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_74__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_74__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_74__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_74__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_74__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_75__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_75__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_75__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_75__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_75__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_75__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_75__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_75__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_76__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_76__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_76__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_76__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_76__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_76__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_76__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_76__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_77__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_77__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_77__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_77__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_77__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_77__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_77__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_77__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_78__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_78__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_78__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_78__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_78__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_78__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_78__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_78__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_79__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_79__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_79__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_79__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_79__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_79__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_79__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_79__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_80__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_80__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_80__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_80__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_80__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_80__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_80__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_80__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_81__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_81__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_81__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_81__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_81__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_81__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_81__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_81__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_82__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_82__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_82__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_82__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_82__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_82__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_82__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_82__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_83__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_83__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_83__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_83__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_83__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_83__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_83__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_83__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_84__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_84__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_84__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_84__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_84__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_84__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_84__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_84__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_85__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_85__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_85__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_85__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_85__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_85__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_85__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_85__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_86__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_86__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_86__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_86__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_86__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_86__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_86__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_86__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_87__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_87__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_87__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_87__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_87__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_87__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_87__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_87__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_88__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_88__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_88__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_88__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_88__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_88__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_88__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_88__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_89__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_89__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_89__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_89__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_89__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_89__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_89__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_89__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_90__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_90__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_90__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_90__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_90__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_90__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_90__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_90__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_91__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_91__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_91__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_91__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_91__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_91__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_91__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_91__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_92__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_92__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_92__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_92__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_92__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_92__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_92__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_92__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_93__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_93__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_93__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_93__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_93__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_93__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_93__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_93__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_94__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_94__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_94__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_94__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_94__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_94__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_94__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_94__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_95__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_95__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_95__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_95__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_95__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_95__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_95__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_95__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_96__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_96__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_96__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_96__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_96__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_96__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_96__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_96__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_97__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_97__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_97__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_97__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_97__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_97__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_97__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_97__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_98__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_98__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_98__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_98__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_98__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_98__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_98__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_98__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_99__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_99__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_99__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_99__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_99__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_99__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_99__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_99__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_100__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_100__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_100__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_100__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_100__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_100__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_100__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_100__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_101__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_101__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_101__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_101__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_101__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_101__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_101__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_101__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_102__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_102__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_102__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_102__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_102__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_102__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_102__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_102__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_103__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_103__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_103__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_103__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_103__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_103__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_103__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_103__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_104__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_104__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_104__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_104__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_104__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_104__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_104__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_104__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_105__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_105__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_105__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_105__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_105__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_105__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_105__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_105__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_106__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_106__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_106__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_106__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_106__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_106__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_106__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_106__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_107__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_107__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_107__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_107__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_107__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_107__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_107__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_107__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_108__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_108__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_108__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_108__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_108__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_108__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_108__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_108__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_109__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_109__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_109__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_109__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_109__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_109__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_109__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_109__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_110__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_110__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_110__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_110__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_110__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_110__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_110__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_110__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_111__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_111__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_111__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_111__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_111__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_111__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_111__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_111__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_112__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_112__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_112__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_112__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_112__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_112__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_112__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_112__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_113__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_113__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_113__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_113__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_113__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_113__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_113__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_113__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_114__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_114__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_114__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_114__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_114__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_114__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_114__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_114__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_115__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_115__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_115__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_115__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_115__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_115__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_115__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_115__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_116__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_116__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_116__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_116__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_116__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_116__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_116__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_116__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_117__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_117__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_117__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_117__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_117__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_117__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_117__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_117__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_118__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_118__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_118__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_118__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_118__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_118__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_118__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_118__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_119__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_119__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_119__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_119__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_119__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_119__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_119__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_119__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_120__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_120__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_120__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_120__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_120__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_120__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_120__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_120__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_121__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_121__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_121__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_121__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_121__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_121__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_121__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_121__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_122__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_122__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_122__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_122__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_122__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_122__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_122__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_122__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_123__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_123__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_123__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_123__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_123__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_123__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_123__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_123__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_124__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_124__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_124__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_124__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_124__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_124__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_124__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_124__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_125__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_125__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_125__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_125__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_125__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_125__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_125__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_125__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_126__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_126__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_126__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_126__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_126__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_126__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_126__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_126__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_127__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_127__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_127__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_127__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_127__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_127__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_127__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_127__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_128__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_128__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_128__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_128__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_128__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_128__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_128__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_128__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_129__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_129__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_129__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_129__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_129__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_129__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_129__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_129__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_130__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_130__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_130__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_130__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_130__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_130__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_130__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_130__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_131__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_131__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_131__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_131__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_131__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_131__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_131__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_131__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_132__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_132__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_132__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_132__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_132__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_132__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_132__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_132__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_133__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_133__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_133__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_133__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_133__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_133__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_133__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_133__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_134__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_134__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_134__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_134__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_134__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_134__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_134__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_134__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_135__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_135__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_135__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_135__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_135__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_135__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_135__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_135__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_136__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_136__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_136__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_136__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_136__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_136__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_136__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_136__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_137__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_137__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_137__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_137__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_137__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_137__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_137__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_137__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_138__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_138__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_138__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_138__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_138__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_138__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_138__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_138__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_139__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_139__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_139__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_139__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_139__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_139__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_139__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_139__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_140__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_140__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_140__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_140__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_140__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_140__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_140__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_140__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_141__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_141__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_141__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_141__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_141__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_141__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_141__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_141__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_142__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_142__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_142__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_142__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_142__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_142__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_142__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_142__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_143__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_143__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_143__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_143__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_143__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_143__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_143__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_143__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_144__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_144__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_144__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_144__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_144__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_144__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_144__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_144__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_145__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_145__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_145__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_145__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_145__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_145__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_145__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_145__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_146__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_146__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_146__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_146__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_146__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_146__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_146__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_146__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_147__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_147__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_147__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_147__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_147__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_147__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_147__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_147__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_148__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_148__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_148__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_148__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_148__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_148__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_148__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_148__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_149__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_149__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_149__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_149__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_149__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_149__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_149__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_149__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_150__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_150__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_150__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_150__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_150__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_150__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_150__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_150__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_151__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_151__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_151__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_151__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_151__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_151__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_151__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_151__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_152__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_152__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_152__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_152__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_152__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_152__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_152__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_152__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_153__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_153__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_153__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_153__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_153__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_153__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_153__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_153__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_154__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_154__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_154__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_154__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_154__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_154__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_154__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_154__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_155__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_155__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_155__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_155__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_155__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_155__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_155__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_155__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_156__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_156__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_156__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_156__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_156__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_156__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_156__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_156__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_157__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_157__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_157__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_157__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_157__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_157__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_157__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_157__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_158__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_158__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_158__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_158__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_158__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_158__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_158__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_158__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_159__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_159__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_159__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_159__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_159__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_159__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_159__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_159__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
+#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D0_MASK 0x7
+#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D0__SHIFT 0x0
+#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D0_MASK 0x38
+#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D0__SHIFT 0x3
+#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D1_MASK 0x1c0
+#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D1__SHIFT 0x6
+#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D1_MASK 0xe00
+#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D1__SHIFT 0x9
+#define MC_SEQ_CNTL_3__REPCG_EN_D0_MASK 0x1000
+#define MC_SEQ_CNTL_3__REPCG_EN_D0__SHIFT 0xc
+#define MC_SEQ_CNTL_3__REPCG_EN_D1_MASK 0x2000
+#define MC_SEQ_CNTL_3__REPCG_EN_D1__SHIFT 0xd
+#define MC_SEQ_CNTL_3__REPCG_OFF_DLY_MASK 0xf0000
+#define MC_SEQ_CNTL_3__REPCG_OFF_DLY__SHIFT 0x10
+#define MC_SEQ_CNTL_3__FCK_FRC_MASK 0x100000
+#define MC_SEQ_CNTL_3__FCK_FRC__SHIFT 0x14
+#define MC_SEQ_CNTL_3__DBI_FRC_MASK 0x200000
+#define MC_SEQ_CNTL_3__DBI_FRC__SHIFT 0x15
+#define MC_SEQ_CNTL_3__PRGRM_CDC_MASK 0x400000
+#define MC_SEQ_CNTL_3__PRGRM_CDC__SHIFT 0x16
+#define MC_SEQ_CNTL_3__DQS_FRC_MASK 0x800000
+#define MC_SEQ_CNTL_3__DQS_FRC__SHIFT 0x17
+#define MC_SEQ_CNTL_3__DQS_FRC_PAT_MASK 0xf000000
+#define MC_SEQ_CNTL_3__DQS_FRC_PAT__SHIFT 0x18
+#define MC_SEQ_CNTL_3__IDSC_EN_MASK 0x40000000
+#define MC_SEQ_CNTL_3__IDSC_EN__SHIFT 0x1e
+#define MC_SEQ_CNTL_3__CAC_EN_MASK 0x80000000
+#define MC_SEQ_CNTL_3__CAC_EN__SHIFT 0x1f
+#define MC_SEQ_G5PDX_CTRL__CH0_ENABLE_MASK 0x1
+#define MC_SEQ_G5PDX_CTRL__CH0_ENABLE__SHIFT 0x0
+#define MC_SEQ_G5PDX_CTRL__CH1_ENABLE_MASK 0x2
+#define MC_SEQ_G5PDX_CTRL__CH1_ENABLE__SHIFT 0x1
+#define MC_SEQ_G5PDX_CTRL__WCKOFF_EARLY_MASK 0x4
+#define MC_SEQ_G5PDX_CTRL__WCKOFF_EARLY__SHIFT 0x2
+#define MC_SEQ_G5PDX_CTRL__WCKOFF_LATE_MASK 0x8
+#define MC_SEQ_G5PDX_CTRL__WCKOFF_LATE__SHIFT 0x3
+#define MC_SEQ_G5PDX_CTRL__TPD2MRS_MASK 0x3f0
+#define MC_SEQ_G5PDX_CTRL__TPD2MRS__SHIFT 0x4
+#define MC_SEQ_G5PDX_CTRL__TMRS2WCK_MASK 0xf000
+#define MC_SEQ_G5PDX_CTRL__TMRS2WCK__SHIFT 0xc
+#define MC_SEQ_G5PDX_CTRL__TWCK2MRS_MASK 0xf0000
+#define MC_SEQ_G5PDX_CTRL__TWCK2MRS__SHIFT 0x10
+#define MC_SEQ_G5PDX_CTRL__TMRD_MASK 0xf00000
+#define MC_SEQ_G5PDX_CTRL__TMRD__SHIFT 0x14
+#define MC_SEQ_G5PDX_CTRL_LP__CH0_ENABLE_MASK 0x1
+#define MC_SEQ_G5PDX_CTRL_LP__CH0_ENABLE__SHIFT 0x0
+#define MC_SEQ_G5PDX_CTRL_LP__CH1_ENABLE_MASK 0x2
+#define MC_SEQ_G5PDX_CTRL_LP__CH1_ENABLE__SHIFT 0x1
+#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_EARLY_MASK 0x4
+#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_EARLY__SHIFT 0x2
+#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_LATE_MASK 0x8
+#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_LATE__SHIFT 0x3
+#define MC_SEQ_G5PDX_CTRL_LP__TPD2MRS_MASK 0x3f0
+#define MC_SEQ_G5PDX_CTRL_LP__TPD2MRS__SHIFT 0x4
+#define MC_SEQ_G5PDX_CTRL_LP__TMRS2WCK_MASK 0xf000
+#define MC_SEQ_G5PDX_CTRL_LP__TMRS2WCK__SHIFT 0xc
+#define MC_SEQ_G5PDX_CTRL_LP__TWCK2MRS_MASK 0xf0000
+#define MC_SEQ_G5PDX_CTRL_LP__TWCK2MRS__SHIFT 0x10
+#define MC_SEQ_G5PDX_CTRL_LP__TMRD_MASK 0xf00000
+#define MC_SEQ_G5PDX_CTRL_LP__TMRD__SHIFT 0x14
+#define MC_SEQ_G5PDX_CMD0__CMD_MASK 0xffffffff
+#define MC_SEQ_G5PDX_CMD0__CMD__SHIFT 0x0
+#define MC_SEQ_G5PDX_CMD0_LP__CMD_MASK 0xffffffff
+#define MC_SEQ_G5PDX_CMD0_LP__CMD__SHIFT 0x0
+#define MC_SEQ_G5PDX_CMD1__CMD_MASK 0xffffffff
+#define MC_SEQ_G5PDX_CMD1__CMD__SHIFT 0x0
+#define MC_SEQ_G5PDX_CMD1_LP__CMD_MASK 0xffffffff
+#define MC_SEQ_G5PDX_CMD1_LP__CMD__SHIFT 0x0
+#define MC_SEQ_SREG_READ__DATA_MASK 0xffffffff
+#define MC_SEQ_SREG_READ__DATA__SHIFT 0x0
+#define MC_SEQ_SREG_STATUS__AVAIL_RTN_MASK 0xf
+#define MC_SEQ_SREG_STATUS__AVAIL_RTN__SHIFT 0x0
+#define MC_SEQ_SREG_STATUS__PND_RD_MASK 0xf00
+#define MC_SEQ_SREG_STATUS__PND_RD__SHIFT 0x8
+#define MC_SEQ_SREG_STATUS__PND_WR_MASK 0xf000
+#define MC_SEQ_SREG_STATUS__PND_WR__SHIFT 0xc
+#define MC_SEQ_PHYREG_BCAST__CH0_EN_MASK 0x1
+#define MC_SEQ_PHYREG_BCAST__CH0_EN__SHIFT 0x0
+#define MC_SEQ_PHYREG_BCAST__CH1_EN_MASK 0x2
+#define MC_SEQ_PHYREG_BCAST__CH1_EN__SHIFT 0x1
+#define MC_SEQ_PHYREG_BCAST__CKE_MASK_MASK 0x80
+#define MC_SEQ_PHYREG_BCAST__CKE_MASK__SHIFT 0x7
+#define MC_SEQ_PHYREG_BCAST__DQ_MASK_MASK 0x100
+#define MC_SEQ_PHYREG_BCAST__DQ_MASK__SHIFT 0x8
+#define MC_SEQ_PHYREG_BCAST__DBI_MASK_MASK 0x200
+#define MC_SEQ_PHYREG_BCAST__DBI_MASK__SHIFT 0x9
+#define MC_SEQ_PHYREG_BCAST__EDC_MASK_MASK 0x400
+#define MC_SEQ_PHYREG_BCAST__EDC_MASK__SHIFT 0xa
+#define MC_SEQ_PHYREG_BCAST__WCK_MASK_MASK 0x800
+#define MC_SEQ_PHYREG_BCAST__WCK_MASK__SHIFT 0xb
+#define MC_SEQ_PHYREG_BCAST__WCDR_MASK_MASK 0x1000
+#define MC_SEQ_PHYREG_BCAST__WCDR_MASK__SHIFT 0xc
+#define MC_SEQ_PHYREG_BCAST__CLK_MASK_MASK 0x2000
+#define MC_SEQ_PHYREG_BCAST__CLK_MASK__SHIFT 0xd
+#define MC_SEQ_PHYREG_BCAST__CMD_MASK_MASK 0x4000
+#define MC_SEQ_PHYREG_BCAST__CMD_MASK__SHIFT 0xe
+#define MC_SEQ_PHYREG_BCAST__ADR_MASK_MASK 0x8000
+#define MC_SEQ_PHYREG_BCAST__ADR_MASK__SHIFT 0xf
+#define MC_SEQ_PMG_DVS_CTL__ENABLE_MASK 0x1
+#define MC_SEQ_PMG_DVS_CTL__ENABLE__SHIFT 0x0
+#define MC_SEQ_PMG_DVS_CTL__TDVS_MASK 0x3e
+#define MC_SEQ_PMG_DVS_CTL__TDVS__SHIFT 0x1
+#define MC_SEQ_PMG_DVS_CTL_LP__ENABLE_MASK 0x1
+#define MC_SEQ_PMG_DVS_CTL_LP__ENABLE__SHIFT 0x0
+#define MC_SEQ_PMG_DVS_CTL_LP__TDVS_MASK 0x3e
+#define MC_SEQ_PMG_DVS_CTL_LP__TDVS__SHIFT 0x1
+#define MC_SEQ_PMG_DVS_CMD__ADR_MASK 0xffff
+#define MC_SEQ_PMG_DVS_CMD__ADR__SHIFT 0x0
+#define MC_SEQ_PMG_DVS_CMD__MOP_MASK 0x70000
+#define MC_SEQ_PMG_DVS_CMD__MOP__SHIFT 0x10
+#define MC_SEQ_PMG_DVS_CMD__BNK_MSB_MASK 0x80000
+#define MC_SEQ_PMG_DVS_CMD__BNK_MSB__SHIFT 0x13
+#define MC_SEQ_PMG_DVS_CMD__END_MASK 0x100000
+#define MC_SEQ_PMG_DVS_CMD__END__SHIFT 0x14
+#define MC_SEQ_PMG_DVS_CMD__CSB_MASK 0x600000
+#define MC_SEQ_PMG_DVS_CMD__CSB__SHIFT 0x15
+#define MC_SEQ_PMG_DVS_CMD__ADR_MSB1_MASK 0x800000
+#define MC_SEQ_PMG_DVS_CMD__ADR_MSB1__SHIFT 0x17
+#define MC_SEQ_PMG_DVS_CMD__ADR_MSB0_MASK 0x1000000
+#define MC_SEQ_PMG_DVS_CMD__ADR_MSB0__SHIFT 0x18
+#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MASK 0xffff
+#define MC_SEQ_PMG_DVS_CMD_LP__ADR__SHIFT 0x0
+#define MC_SEQ_PMG_DVS_CMD_LP__MOP_MASK 0x70000
+#define MC_SEQ_PMG_DVS_CMD_LP__MOP__SHIFT 0x10
+#define MC_SEQ_PMG_DVS_CMD_LP__BNK_MSB_MASK 0x80000
+#define MC_SEQ_PMG_DVS_CMD_LP__BNK_MSB__SHIFT 0x13
+#define MC_SEQ_PMG_DVS_CMD_LP__END_MASK 0x100000
+#define MC_SEQ_PMG_DVS_CMD_LP__END__SHIFT 0x14
+#define MC_SEQ_PMG_DVS_CMD_LP__CSB_MASK 0x600000
+#define MC_SEQ_PMG_DVS_CMD_LP__CSB__SHIFT 0x15
+#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB1_MASK 0x800000
+#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB1__SHIFT 0x17
+#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB0_MASK 0x1000000
+#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB0__SHIFT 0x18
+#define MC_SEQ_DLL_STBY__EN_MASK 0x1
+#define MC_SEQ_DLL_STBY__EN__SHIFT 0x0
+#define MC_SEQ_DLL_STBY__VCTRLADC_FRC_MASK 0x2
+#define MC_SEQ_DLL_STBY__VCTRLADC_FRC__SHIFT 0x1
+#define MC_SEQ_DLL_STBY__VCTRLADC_VAL_MASK 0x4
+#define MC_SEQ_DLL_STBY__VCTRLADC_VAL__SHIFT 0x2
+#define MC_SEQ_DLL_STBY__MSTRSTBY_FRC_MASK 0x8
+#define MC_SEQ_DLL_STBY__MSTRSTBY_FRC__SHIFT 0x3
+#define MC_SEQ_DLL_STBY__MSTRSTBY_VAL_MASK 0x10
+#define MC_SEQ_DLL_STBY__MSTRSTBY_VAL__SHIFT 0x4
+#define MC_SEQ_DLL_STBY__ENTR_DLY_MASK 0xe0
+#define MC_SEQ_DLL_STBY__ENTR_DLY__SHIFT 0x5
+#define MC_SEQ_DLL_STBY__STBY_DLY_MASK 0xf00
+#define MC_SEQ_DLL_STBY__STBY_DLY__SHIFT 0x8
+#define MC_SEQ_DLL_STBY__TCKE_PULSE_EXTN_MASK 0xf000
+#define MC_SEQ_DLL_STBY__TCKE_PULSE_EXTN__SHIFT 0xc
+#define MC_SEQ_DLL_STBY__TCKE_EXTN_MASK 0xff0000
+#define MC_SEQ_DLL_STBY__TCKE_EXTN__SHIFT 0x10
+#define MC_SEQ_DLL_STBY__EXIT_DLY_MASK 0x3f000000
+#define MC_SEQ_DLL_STBY__EXIT_DLY__SHIFT 0x18
+#define MC_SEQ_DLL_STBY_LP__EN_MASK 0x1
+#define MC_SEQ_DLL_STBY_LP__EN__SHIFT 0x0
+#define MC_SEQ_DLL_STBY_LP__VCTRLADC_FRC_MASK 0x2
+#define MC_SEQ_DLL_STBY_LP__VCTRLADC_FRC__SHIFT 0x1
+#define MC_SEQ_DLL_STBY_LP__VCTRLADC_VAL_MASK 0x4
+#define MC_SEQ_DLL_STBY_LP__VCTRLADC_VAL__SHIFT 0x2
+#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_FRC_MASK 0x8
+#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_FRC__SHIFT 0x3
+#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_VAL_MASK 0x10
+#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_VAL__SHIFT 0x4
+#define MC_SEQ_DLL_STBY_LP__ENTR_DLY_MASK 0xe0
+#define MC_SEQ_DLL_STBY_LP__ENTR_DLY__SHIFT 0x5
+#define MC_SEQ_DLL_STBY_LP__STBY_DLY_MASK 0xf00
+#define MC_SEQ_DLL_STBY_LP__STBY_DLY__SHIFT 0x8
+#define MC_SEQ_DLL_STBY_LP__TCKE_PULSE_EXTN_MASK 0xf000
+#define MC_SEQ_DLL_STBY_LP__TCKE_PULSE_EXTN__SHIFT 0xc
+#define MC_SEQ_DLL_STBY_LP__TCKE_EXTN_MASK 0xff0000
+#define MC_SEQ_DLL_STBY_LP__TCKE_EXTN__SHIFT 0x10
+#define MC_SEQ_DLL_STBY_LP__EXIT_DLY_MASK 0x3f000000
+#define MC_SEQ_DLL_STBY_LP__EXIT_DLY__SHIFT 0x18
+#define MC_DLB_MISCCTRL0__UDD_ON_STATUS_BITS_MASK 0x1
+#define MC_DLB_MISCCTRL0__UDD_ON_STATUS_BITS__SHIFT 0x0
+#define MC_DLB_MISCCTRL0__LOAD_DATA_SEL_MASK 0x2
+#define MC_DLB_MISCCTRL0__LOAD_DATA_SEL__SHIFT 0x1
+#define MC_DLB_MISCCTRL0__LOAD_UDD_MASK 0x4
+#define MC_DLB_MISCCTRL0__LOAD_UDD__SHIFT 0x2
+#define MC_DLB_MISCCTRL0__ADR_STATUS_SEL_MASK 0x8
+#define MC_DLB_MISCCTRL0__ADR_STATUS_SEL__SHIFT 0x3
+#define MC_DLB_MISCCTRL0__DATA_SEL_MASK 0xf0
+#define MC_DLB_MISCCTRL0__DATA_SEL__SHIFT 0x4
+#define MC_DLB_MISCCTRL0__PRBS_CHK_LOAD_CNT_MASK 0x7f00
+#define MC_DLB_MISCCTRL0__PRBS_CHK_LOAD_CNT__SHIFT 0x8
+#define MC_DLB_MISCCTRL0__UDD_MASK 0xffff0000
+#define MC_DLB_MISCCTRL0__UDD__SHIFT 0x10
+#define MC_DLB_MISCCTRL1__PRBS_ERR_CNT_LIMIT_MASK 0xffffffff
+#define MC_DLB_MISCCTRL1__PRBS_ERR_CNT_LIMIT__SHIFT 0x0
+#define MC_DLB_MISCCTRL2__PRBS_RUN_LENGTH_MASK 0x1ffff
+#define MC_DLB_MISCCTRL2__PRBS_RUN_LENGTH__SHIFT 0x0
+#define MC_DLB_MISCCTRL2__PRBS_FREERUN_MASK 0x20000
+#define MC_DLB_MISCCTRL2__PRBS_FREERUN__SHIFT 0x11
+#define MC_DLB_MISCCTRL2__PRBS15_MODE_MASK 0x40000
+#define MC_DLB_MISCCTRL2__PRBS15_MODE__SHIFT 0x12
+#define MC_DLB_MISCCTRL2__PRBS23_MODE_MASK 0x80000
+#define MC_DLB_MISCCTRL2__PRBS23_MODE__SHIFT 0x13
+#define MC_DLB_MISCCTRL2__STOP_ON_NEXT_ERR_MASK 0x100000
+#define MC_DLB_MISCCTRL2__STOP_ON_NEXT_ERR__SHIFT 0x14
+#define MC_DLB_MISCCTRL2__STOP_CLK_MASK 0x200000
+#define MC_DLB_MISCCTRL2__STOP_CLK__SHIFT 0x15
+#define MC_DLB_MISCCTRL2__SWEEP_DLY_MASK 0x3000000
+#define MC_DLB_MISCCTRL2__SWEEP_DLY__SHIFT 0x18
+#define MC_DLB_MISCCTRL2__GRAY_CODE_EN_MASK 0x4000000
+#define MC_DLB_MISCCTRL2__GRAY_CODE_EN__SHIFT 0x1a
+#define MC_DLB_MISCCTRL2__SEL_PHY_PRBS_CHK_MASK 0x10000000
+#define MC_DLB_MISCCTRL2__SEL_PHY_PRBS_CHK__SHIFT 0x1c
+#define MC_DLB_MISCCTRL2__SEL_AC_PRBS_CHK_MASK 0x20000000
+#define MC_DLB_MISCCTRL2__SEL_AC_PRBS_CHK__SHIFT 0x1d
+#define MC_DLB_MISCCTRL2__STATUS_SEL_MASK 0x40000000
+#define MC_DLB_MISCCTRL2__STATUS_SEL__SHIFT 0x1e
+#define MC_DLB_CONFIG0__CONF_EN_CH0_MASK 0x1
+#define MC_DLB_CONFIG0__CONF_EN_CH0__SHIFT 0x0
+#define MC_DLB_CONFIG0__CONF_EN_CH1_MASK 0x2
+#define MC_DLB_CONFIG0__CONF_EN_CH1__SHIFT 0x1
+#define MC_DLB_CONFIG0__CONF_AUTO_EN_MASK 0x4
+#define MC_DLB_CONFIG0__CONF_AUTO_EN__SHIFT 0x2
+#define MC_DLB_CONFIG0__MASK_MASK 0xf0
+#define MC_DLB_CONFIG0__MASK__SHIFT 0x4
+#define MC_DLB_CONFIG0__PTR_MASK 0x3ff00
+#define MC_DLB_CONFIG0__PTR__SHIFT 0x8
+#define MC_DLB_CONFIG1__DATA_MASK 0xffffffff
+#define MC_DLB_CONFIG1__DATA__SHIFT 0x0
+#define MC_DLB_SETUP__DLB_EN_MASK 0x1
+#define MC_DLB_SETUP__DLB_EN__SHIFT 0x0
+#define MC_DLB_SETUP__DLB_FIFO_EN_MASK 0x2
+#define MC_DLB_SETUP__DLB_FIFO_EN__SHIFT 0x1
+#define MC_DLB_SETUP__DLB_STATUS_EN_MASK 0x4
+#define MC_DLB_SETUP__DLB_STATUS_EN__SHIFT 0x2
+#define MC_DLB_SETUP__DLB_CONFIG_EN_MASK 0x8
+#define MC_DLB_SETUP__DLB_CONFIG_EN__SHIFT 0x3
+#define MC_DLB_SETUP__DLB_PRBS_EN_MASK 0x10
+#define MC_DLB_SETUP__DLB_PRBS_EN__SHIFT 0x4
+#define MC_DLB_SETUP__PRBS_GEN_RST_MASK 0x20
+#define MC_DLB_SETUP__PRBS_GEN_RST__SHIFT 0x5
+#define MC_DLB_SETUP__PRBS_CHK_RST_MASK 0x40
+#define MC_DLB_SETUP__PRBS_CHK_RST__SHIFT 0x6
+#define MC_DLB_SETUP__PRBS_PHY_RST_MASK 0x80
+#define MC_DLB_SETUP__PRBS_PHY_RST__SHIFT 0x7
+#define MC_DLB_SETUP__QDR_MODE_MASK 0x100
+#define MC_DLB_SETUP__QDR_MODE__SHIFT 0x8
+#define MC_DLB_SETUP__CHK_DATA_BITS_MASK 0xff0000
+#define MC_DLB_SETUP__CHK_DATA_BITS__SHIFT 0x10
+#define MC_DLB_SETUP__MEM_BIT_SEL_MASK 0x1f000000
+#define MC_DLB_SETUP__MEM_BIT_SEL__SHIFT 0x18
+#define MC_DLB_SETUP__RXTXLP_EN_MASK 0x80000000
+#define MC_DLB_SETUP__RXTXLP_EN__SHIFT 0x1f
+#define MC_DLB_SETUPSWEEP__DLL_RST_MASK 0x1
+#define MC_DLB_SETUPSWEEP__DLL_RST__SHIFT 0x0
+#define MC_DLB_SETUPSWEEP__CONFIG_MASK 0x2
+#define MC_DLB_SETUPSWEEP__CONFIG__SHIFT 0x1
+#define MC_DLB_SETUPSWEEP__MASTER_MASK 0x4
+#define MC_DLB_SETUPSWEEP__MASTER__SHIFT 0x2
+#define MC_DLB_SETUPSWEEP__DLLDLY_MASK 0xf0
+#define MC_DLB_SETUPSWEEP__DLLDLY__SHIFT 0x4
+#define MC_DLB_SETUPSWEEP__DLLSTEPS_MASK 0x1f00
+#define MC_DLB_SETUPSWEEP__DLLSTEPS__SHIFT 0x8
+#define MC_DLB_SETUPFIFO__WRITE_FIFO_RST_MASK 0x1
+#define MC_DLB_SETUPFIFO__WRITE_FIFO_RST__SHIFT 0x0
+#define MC_DLB_SETUPFIFO__READ_FIFO_RST_MASK 0x2
+#define MC_DLB_SETUPFIFO__READ_FIFO_RST__SHIFT 0x1
+#define MC_DLB_SETUPFIFO__BOTH_FIFO_RST_MASK 0x4
+#define MC_DLB_SETUPFIFO__BOTH_FIFO_RST__SHIFT 0x2
+#define MC_DLB_SETUPFIFO__SYNC_RST_MASK 0x8
+#define MC_DLB_SETUPFIFO__SYNC_RST__SHIFT 0x3
+#define MC_DLB_SETUPFIFO__SYNC_RST_MASK_MASK 0x30
+#define MC_DLB_SETUPFIFO__SYNC_RST_MASK__SHIFT 0x4
+#define MC_DLB_SETUPFIFO__OUTPUT_EN_RST_MASK 0x40
+#define MC_DLB_SETUPFIFO__OUTPUT_EN_RST__SHIFT 0x6
+#define MC_DLB_SETUPFIFO__SHIFT_WR_FIFO_PTR_MASK 0x300
+#define MC_DLB_SETUPFIFO__SHIFT_WR_FIFO_PTR__SHIFT 0x8
+#define MC_DLB_SETUPFIFO__DELAY_RD_FIFO_PTR_MASK 0x1c00
+#define MC_DLB_SETUPFIFO__DELAY_RD_FIFO_PTR__SHIFT 0xa
+#define MC_DLB_SETUPFIFO__STROBE_MASK 0xf0000
+#define MC_DLB_SETUPFIFO__STROBE__SHIFT 0x10
+#define MC_DLB_WRITE_MASK__BIT_MASK_MASK 0x3fffff
+#define MC_DLB_WRITE_MASK__BIT_MASK__SHIFT 0x0
+#define MC_DLB_WRITE_MASK__CH_MASK_MASK 0xf000000
+#define MC_DLB_WRITE_MASK__CH_MASK__SHIFT 0x18
+#define MC_DLB_STATUS__STICK_ERROR_MASK 0xf
+#define MC_DLB_STATUS__STICK_ERROR__SHIFT 0x0
+#define MC_DLB_STATUS__LOCK_MASK 0xf0
+#define MC_DLB_STATUS__LOCK__SHIFT 0x4
+#define MC_DLB_STATUS__SWEEP_DONE_MASK 0xf00
+#define MC_DLB_STATUS__SWEEP_DONE__SHIFT 0x8
+#define MC_DLB_STATUS_MISC0__DATA_MASK 0xffffffff
+#define MC_DLB_STATUS_MISC0__DATA__SHIFT 0x0
+#define MC_DLB_STATUS_MISC1__DATA_MASK 0xffffffff
+#define MC_DLB_STATUS_MISC1__DATA__SHIFT 0x0
+#define MC_DLB_STATUS_MISC2__DATA_MASK 0xffffffff
+#define MC_DLB_STATUS_MISC2__DATA__SHIFT 0x0
+#define MC_DLB_STATUS_MISC3__DATA_MASK 0xffffffff
+#define MC_DLB_STATUS_MISC3__DATA__SHIFT 0x0
+#define MC_DLB_STATUS_MISC4__DATA_MASK 0xffffffff
+#define MC_DLB_STATUS_MISC4__DATA__SHIFT 0x0
+#define MC_DLB_STATUS_MISC5__DATA_MASK 0xffffffff
+#define MC_DLB_STATUS_MISC5__DATA__SHIFT 0x0
+#define MC_DLB_STATUS_MISC6__DATA_MASK 0xffffffff
+#define MC_DLB_STATUS_MISC6__DATA__SHIFT 0x0
+#define MC_DLB_STATUS_MISC7__DATA_MASK 0xffffffff
+#define MC_DLB_STATUS_MISC7__DATA__SHIFT 0x0
+#define MC_ARB_HARSH_EN_RD__TX_PRI_MASK 0xff
+#define MC_ARB_HARSH_EN_RD__TX_PRI__SHIFT 0x0
+#define MC_ARB_HARSH_EN_RD__BW_PRI_MASK 0xff00
+#define MC_ARB_HARSH_EN_RD__BW_PRI__SHIFT 0x8
+#define MC_ARB_HARSH_EN_RD__FIX_PRI_MASK 0xff0000
+#define MC_ARB_HARSH_EN_RD__FIX_PRI__SHIFT 0x10
+#define MC_ARB_HARSH_EN_RD__ST_PRI_MASK 0xff000000
+#define MC_ARB_HARSH_EN_RD__ST_PRI__SHIFT 0x18
+#define MC_ARB_HARSH_EN_WR__TX_PRI_MASK 0xff
+#define MC_ARB_HARSH_EN_WR__TX_PRI__SHIFT 0x0
+#define MC_ARB_HARSH_EN_WR__BW_PRI_MASK 0xff00
+#define MC_ARB_HARSH_EN_WR__BW_PRI__SHIFT 0x8
+#define MC_ARB_HARSH_EN_WR__FIX_PRI_MASK 0xff0000
+#define MC_ARB_HARSH_EN_WR__FIX_PRI__SHIFT 0x10
+#define MC_ARB_HARSH_EN_WR__ST_PRI_MASK 0xff000000
+#define MC_ARB_HARSH_EN_WR__ST_PRI__SHIFT 0x18
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_SAT0_RD__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_SAT0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_SAT0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_SAT0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_SAT0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_SAT0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_SAT0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_SAT0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_SAT0_WR__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_SAT0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_SAT0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_SAT0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_SAT0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_SAT0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_SAT0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_SAT0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_SAT1_RD__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_SAT1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_SAT1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_SAT1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_SAT1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_SAT1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_SAT1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_SAT1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_SAT1_WR__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_SAT1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_SAT1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_SAT1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_SAT1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_SAT1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_SAT1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_SAT1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST_MASK 0xff
+#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST__SHIFT 0x0
+#define MC_ARB_HARSH_CTL_RD__HARSH_RR_MASK 0x100
+#define MC_ARB_HARSH_CTL_RD__HARSH_RR__SHIFT 0x8
+#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY_MASK 0x200
+#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY__SHIFT 0x9
+#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH_MASK 0x400
+#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH__SHIFT 0xa
+#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP_MASK 0x800
+#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP__SHIFT 0xb
+#define MC_ARB_HARSH_CTL_RD__ST_MODE_MASK 0x3000
+#define MC_ARB_HARSH_CTL_RD__ST_MODE__SHIFT 0xc
+#define MC_ARB_HARSH_CTL_RD__FORCE_STALL_MASK 0x3fc000
+#define MC_ARB_HARSH_CTL_RD__FORCE_STALL__SHIFT 0xe
+#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL_MASK 0x1c00000
+#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL__SHIFT 0x16
+#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST_MASK 0xff
+#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST__SHIFT 0x0
+#define MC_ARB_HARSH_CTL_WR__HARSH_RR_MASK 0x100
+#define MC_ARB_HARSH_CTL_WR__HARSH_RR__SHIFT 0x8
+#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY_MASK 0x200
+#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY__SHIFT 0x9
+#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH_MASK 0x400
+#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH__SHIFT 0xa
+#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP_MASK 0x800
+#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP__SHIFT 0xb
+#define MC_ARB_HARSH_CTL_WR__ST_MODE_MASK 0x3000
+#define MC_ARB_HARSH_CTL_WR__ST_MODE__SHIFT 0xc
+#define MC_ARB_HARSH_CTL_WR__FORCE_STALL_MASK 0x3fc000
+#define MC_ARB_HARSH_CTL_WR__FORCE_STALL__SHIFT 0xe
+#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL_MASK 0x1c00000
+#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL__SHIFT 0x16
+
+#endif /* GMC_7_1_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_d.h
new file mode 100644
index 000000000000..8c2412e6681e
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_d.h
@@ -0,0 +1,1708 @@
+/*
+ * GMC_8_1 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GMC_8_1_D_H
+#define GMC_8_1_D_H
+
+#define mmMC_CONFIG 0x800
+#define mmMC_ARB_ATOMIC 0x9be
+#define mmMC_ARB_AGE_CNTL 0x9bf
+#define mmMC_ARB_RET_CREDITS2 0x9c0
+#define mmMC_ARB_FED_CNTL 0x9c1
+#define mmMC_ARB_GECC2_STATUS 0x9c2
+#define mmMC_ARB_GECC2_MISC 0x9c3
+#define mmMC_ARB_GECC2_DEBUG 0x9c4
+#define mmMC_ARB_GECC2_DEBUG2 0x9c5
+#define mmMC_ARB_PERF_CID 0x9c6
+#define mmMC_ARB_SNOOP 0x9c7
+#define mmMC_ARB_GRUB 0x9c8
+#define mmMC_ARB_GECC2 0x9c9
+#define mmMC_ARB_GECC2_CLI 0x9ca
+#define mmMC_ARB_ADDR_SWIZ0 0x9cb
+#define mmMC_ARB_ADDR_SWIZ1 0x9cc
+#define mmMC_ARB_MISC3 0x9cd
+#define mmMC_ARB_GRUB_PROMOTE 0x9ce
+#define mmMC_ARB_RTT_DATA 0x9cf
+#define mmMC_ARB_RTT_CNTL0 0x9d0
+#define mmMC_ARB_RTT_CNTL1 0x9d1
+#define mmMC_ARB_RTT_CNTL2 0x9d2
+#define mmMC_ARB_RTT_DEBUG 0x9d3
+#define mmMC_ARB_CAC_CNTL 0x9d4
+#define mmMC_ARB_MISC2 0x9d5
+#define mmMC_ARB_MISC 0x9d6
+#define mmMC_ARB_BANKMAP 0x9d7
+#define mmMC_ARB_RAMCFG 0x9d8
+#define mmMC_ARB_POP 0x9d9
+#define mmMC_ARB_MINCLKS 0x9da
+#define mmMC_ARB_SQM_CNTL 0x9db
+#define mmMC_ARB_ADDR_HASH 0x9dc
+#define mmMC_ARB_DRAM_TIMING 0x9dd
+#define mmMC_ARB_DRAM_TIMING2 0x9de
+#define mmMC_ARB_WTM_CNTL_RD 0x9df
+#define mmMC_ARB_WTM_CNTL_WR 0x9e0
+#define mmMC_ARB_WTM_GRPWT_RD 0x9e1
+#define mmMC_ARB_WTM_GRPWT_WR 0x9e2
+#define mmMC_ARB_TM_CNTL_RD 0x9e3
+#define mmMC_ARB_TM_CNTL_WR 0x9e4
+#define mmMC_ARB_LAZY0_RD 0x9e5
+#define mmMC_ARB_LAZY0_WR 0x9e6
+#define mmMC_ARB_LAZY1_RD 0x9e7
+#define mmMC_ARB_LAZY1_WR 0x9e8
+#define mmMC_ARB_AGE_RD 0x9e9
+#define mmMC_ARB_AGE_WR 0x9ea
+#define mmMC_ARB_RFSH_CNTL 0x9eb
+#define mmMC_ARB_RFSH_RATE 0x9ec
+#define mmMC_ARB_PM_CNTL 0x9ed
+#define mmMC_ARB_GDEC_RD_CNTL 0x9ee
+#define mmMC_ARB_GDEC_WR_CNTL 0x9ef
+#define mmMC_ARB_LM_RD 0x9f0
+#define mmMC_ARB_LM_WR 0x9f1
+#define mmMC_ARB_REMREQ 0x9f2
+#define mmMC_ARB_REPLAY 0x9f3
+#define mmMC_ARB_RET_CREDITS_RD 0x9f4
+#define mmMC_ARB_RET_CREDITS_WR 0x9f5
+#define mmMC_ARB_MAX_LAT_CID 0x9f6
+#define mmMC_ARB_MAX_LAT_RSLT0 0x9f7
+#define mmMC_ARB_MAX_LAT_RSLT1 0x9f8
+#define mmMC_ARB_GRUB_REALTIME_RD 0x9f9
+#define mmMC_ARB_CG 0x9fa
+#define mmMC_ARB_GRUB_REALTIME_WR 0x9fb
+#define mmMC_ARB_DRAM_TIMING_1 0x9fc
+#define mmMC_ARB_BUSY_STATUS 0x9fd
+#define mmMC_ARB_DRAM_TIMING2_1 0x9ff
+#define mmMC_ARB_GRUB2 0xa01
+#define mmMC_ARB_BURST_TIME 0xa02
+#define mmMC_CITF_XTRA_ENABLE 0x96d
+#define mmCC_MC_MAX_CHANNEL 0x96e
+#define mmMC_CG_CONFIG 0x96f
+#define mmMC_CITF_CNTL 0x970
+#define mmMC_CITF_CREDITS_VM 0x971
+#define mmMC_CITF_CREDITS_ARB_RD 0x972
+#define mmMC_CITF_CREDITS_ARB_WR 0x973
+#define mmMC_CITF_DAGB_CNTL 0x974
+#define mmMC_CITF_INT_CREDITS 0x975
+#define mmMC_CITF_RET_MODE 0x976
+#define mmMC_CITF_DAGB_DLY 0x977
+#define mmMC_RD_GRP_EXT 0x978
+#define mmMC_WR_GRP_EXT 0x979
+#define mmMC_CITF_REMREQ 0x97a
+#define mmMC_WR_TC0 0x97b
+#define mmMC_WR_TC1 0x97c
+#define mmMC_CITF_INT_CREDITS_WR 0x97d
+#define mmMC_CITF_CREDITS_ARB_RD2 0x97e
+#define mmMC_CITF_WTM_RD_CNTL 0x97f
+#define mmMC_CITF_WTM_WR_CNTL 0x980
+#define mmMC_RD_CB 0x981
+#define mmMC_RD_DB 0x982
+#define mmMC_RD_TC0 0x983
+#define mmMC_RD_TC1 0x984
+#define mmMC_RD_HUB 0x985
+#define mmMC_WR_CB 0x986
+#define mmMC_WR_DB 0x987
+#define mmMC_WR_HUB 0x988
+#define mmMC_CITF_CREDITS_XBAR 0x989
+#define mmMC_RD_GRP_LCL 0x98a
+#define mmMC_WR_GRP_LCL 0x98b
+#define mmMC_CITF_PERF_MON_CNTL2 0x98e
+#define mmMC_CITF_PERF_MON_RSLT2 0x991
+#define mmMC_CITF_MISC_RD_CG 0x992
+#define mmMC_CITF_MISC_WR_CG 0x993
+#define mmMC_CITF_MISC_VM_CG 0x994
+#define mmMC_HUB_MISC_POWER 0x82d
+#define mmMC_HUB_MISC_HUB_CG 0x82e
+#define mmMC_HUB_MISC_VM_CG 0x82f
+#define mmMC_HUB_MISC_SIP_CG 0x830
+#define mmMC_HUB_MISC_STATUS 0x832
+#define mmMC_HUB_MISC_OVERRIDE 0x833
+#define mmMC_HUB_MISC_FRAMING 0x834
+#define mmMC_HUB_WDP_CNTL 0x835
+#define mmMC_HUB_WDP_ERR 0x836
+#define mmMC_HUB_WDP_BP 0x837
+#define mmMC_HUB_WDP_STATUS 0x838
+#define mmMC_HUB_RDREQ_STATUS 0x839
+#define mmMC_HUB_WRRET_STATUS 0x83a
+#define mmMC_HUB_RDREQ_CNTL 0x83b
+#define mmMC_HUB_WRRET_CNTL 0x83c
+#define mmMC_HUB_RDREQ_WTM_CNTL 0x83d
+#define mmMC_HUB_WDP_WTM_CNTL 0x83e
+#define mmMC_HUB_WDP_CREDITS 0x83f
+#define mmMC_HUB_WDP_CREDITS2 0x840
+#define mmMC_HUB_WDP_GBL0 0x841
+#define mmMC_HUB_WDP_GBL1 0x842
+#define mmMC_HUB_WDP_CREDITS3 0x843
+#define mmMC_HUB_RDREQ_CREDITS 0x844
+#define mmMC_HUB_RDREQ_CREDITS2 0x845
+#define mmMC_HUB_SHARED_DAGB_DLY 0x846
+#define mmMC_HUB_MISC_IDLE_STATUS 0x847
+#define mmMC_HUB_RDREQ_DMIF_LIMIT 0x848
+#define mmMC_HUB_RDREQ_ACPG_LIMIT 0x849
+#define mmMC_HUB_WDP_BYPASS_GBL0 0x84a
+#define mmMC_HUB_WDP_BYPASS_GBL1 0x84b
+#define mmMC_HUB_RDREQ_BYPASS_GBL0 0x84c
+#define mmMC_HUB_WDP_SH2 0x84d
+#define mmMC_HUB_WDP_SH3 0x84e
+#define mmMC_HUB_MISC_ATOMIC_IDLE_STATUS 0x84f
+#define mmMC_HUB_WDP_VIN0 0x850
+#define mmMC_HUB_RDREQ_MCDW 0x851
+#define mmMC_HUB_RDREQ_MCDX 0x852
+#define mmMC_HUB_RDREQ_MCDY 0x853
+#define mmMC_HUB_RDREQ_MCDZ 0x854
+#define mmMC_HUB_RDREQ_SIP 0x855
+#define mmMC_HUB_RDREQ_GBL0 0x856
+#define mmMC_HUB_RDREQ_GBL1 0x857
+#define mmMC_HUB_RDREQ_SMU 0x858
+#define mmMC_HUB_RDREQ_SDMA0 0x859
+#define mmMC_HUB_RDREQ_HDP 0x85a
+#define mmMC_HUB_RDREQ_SDMA1 0x85b
+#define mmMC_HUB_RDREQ_RLC 0x85c
+#define mmMC_HUB_RDREQ_SEM 0x85d
+#define mmMC_HUB_RDREQ_VCE0 0x85e
+#define mmMC_HUB_RDREQ_UMC 0x85f
+#define mmMC_HUB_RDREQ_UVD 0x860
+#define mmMC_HUB_RDREQ_TLS 0x861
+#define mmMC_HUB_RDREQ_DMIF 0x862
+#define mmMC_HUB_RDREQ_MCIF 0x863
+#define mmMC_HUB_RDREQ_VMC 0x864
+#define mmMC_HUB_RDREQ_VCEU0 0x865
+#define mmMC_HUB_WDP_MCDW 0x866
+#define mmMC_HUB_WDP_MCDX 0x867
+#define mmMC_HUB_WDP_MCDY 0x868
+#define mmMC_HUB_WDP_MCDZ 0x869
+#define mmMC_HUB_WDP_SIP 0x86a
+#define mmMC_HUB_WDP_SDMA1 0x86b
+#define mmMC_HUB_WDP_SH0 0x86c
+#define mmMC_HUB_WDP_MCIF 0x86d
+#define mmMC_HUB_WDP_VCE0 0x86e
+#define mmMC_HUB_WDP_XDP 0x86f
+#define mmMC_HUB_WDP_IH 0x870
+#define mmMC_HUB_WDP_RLC 0x871
+#define mmMC_HUB_WDP_SEM 0x872
+#define mmMC_HUB_WDP_SMU 0x873
+#define mmMC_HUB_WDP_SH1 0x874
+#define mmMC_HUB_WDP_UMC 0x875
+#define mmMC_HUB_WDP_UVD 0x876
+#define mmMC_HUB_WDP_HDP 0x877
+#define mmMC_HUB_WDP_SDMA0 0x878
+#define mmMC_HUB_WRRET_MCDW 0x879
+#define mmMC_HUB_WRRET_MCDX 0x87a
+#define mmMC_HUB_WRRET_MCDY 0x87b
+#define mmMC_HUB_WRRET_MCDZ 0x87c
+#define mmMC_HUB_WDP_VCEU0 0x87d
+#define mmMC_HUB_WDP_XDMAM 0x87e
+#define mmMC_HUB_WDP_XDMA 0x87f
+#define mmMC_HUB_RDREQ_XDMAM 0x880
+#define mmMC_HUB_RDREQ_ACPG 0x881
+#define mmMC_HUB_RDREQ_ACPO 0x882
+#define mmMC_HUB_RDREQ_SAMMSP 0x883
+#define mmMC_HUB_RDREQ_VP8 0x884
+#define mmMC_HUB_RDREQ_VP8U 0x885
+#define mmMC_HUB_WDP_ACPG 0x886
+#define mmMC_HUB_WDP_ACPO 0x887
+#define mmMC_HUB_WDP_SAMMSP 0x888
+#define mmMC_HUB_WDP_VP8 0x889
+#define mmMC_HUB_WDP_VP8U 0x88a
+#define mmMC_HUB_RDREQ_ISP_SPM 0xde0
+#define mmMC_HUB_RDREQ_ISP_MPM 0xde1
+#define mmMC_HUB_RDREQ_ISP_CCPU 0xde2
+#define mmMC_HUB_WDP_ISP_SPM 0xde3
+#define mmMC_HUB_WDP_ISP_MPS 0xde4
+#define mmMC_HUB_WDP_ISP_MPM 0xde5
+#define mmMC_HUB_WDP_ISP_CCPU 0xde6
+#define mmMC_HUB_RDREQ_MCDS 0xde7
+#define mmMC_HUB_RDREQ_MCDT 0xde8
+#define mmMC_HUB_RDREQ_MCDU 0xde9
+#define mmMC_HUB_RDREQ_MCDV 0xdea
+#define mmMC_HUB_WDP_MCDS 0xdeb
+#define mmMC_HUB_WDP_MCDT 0xdec
+#define mmMC_HUB_WDP_MCDU 0xded
+#define mmMC_HUB_WDP_MCDV 0xdee
+#define mmMC_HUB_WRRET_MCDS 0xdef
+#define mmMC_HUB_WRRET_MCDT 0xdf0
+#define mmMC_HUB_WRRET_MCDU 0xdf1
+#define mmMC_HUB_WRRET_MCDV 0xdf2
+#define mmMC_HUB_WDP_CREDITS_MCDW 0xdf3
+#define mmMC_HUB_WDP_CREDITS_MCDX 0xdf4
+#define mmMC_HUB_WDP_CREDITS_MCDY 0xdf5
+#define mmMC_HUB_WDP_CREDITS_MCDZ 0xdf6
+#define mmMC_HUB_WDP_CREDITS_MCDS 0xdf7
+#define mmMC_HUB_WDP_CREDITS_MCDT 0xdf8
+#define mmMC_HUB_WDP_CREDITS_MCDU 0xdf9
+#define mmMC_HUB_WDP_CREDITS_MCDV 0xdfa
+#define mmMC_HUB_WDP_BP2 0xdfb
+#define mmMC_HUB_RDREQ_VCE1 0xdfc
+#define mmMC_HUB_RDREQ_VCEU1 0xdfd
+#define mmMC_HUB_WDP_VCE1 0xdfe
+#define mmMC_HUB_WDP_VCEU1 0xdff
+#define mmMC_RPB_CONF 0x94d
+#define mmMC_RPB_IF_CONF 0x94e
+#define mmMC_RPB_DBG1 0x94f
+#define mmMC_RPB_EFF_CNTL 0x950
+#define mmMC_RPB_ARB_CNTL 0x951
+#define mmMC_RPB_BIF_CNTL 0x952
+#define mmMC_RPB_WR_SWITCH_CNTL 0x953
+#define mmMC_RPB_WR_COMBINE_CNTL 0x954
+#define mmMC_RPB_RD_SWITCH_CNTL 0x955
+#define mmMC_RPB_CID_QUEUE_WR 0x956
+#define mmMC_RPB_CID_QUEUE_RD 0x957
+#define mmMC_RPB_PERF_COUNTER_CNTL 0x958
+#define mmMC_RPB_PERF_COUNTER_STATUS 0x959
+#define mmMC_RPB_CID_QUEUE_EX 0x95a
+#define mmMC_RPB_CID_QUEUE_EX_DATA 0x95b
+#define mmMC_RPB_TCI_CNTL 0x95c
+#define mmMC_RPB_TCI_CNTL2 0x95d
+#define mmMC_SHARED_CHMAP 0x801
+#define mmMC_SHARED_CHREMAP 0x802
+#define mmMC_RD_GRP_GFX 0x803
+#define mmMC_WR_GRP_GFX 0x804
+#define mmMC_RD_GRP_SYS 0x805
+#define mmMC_WR_GRP_SYS 0x806
+#define mmMC_RD_GRP_OTH 0x807
+#define mmMC_WR_GRP_OTH 0x808
+#define mmMC_VM_FB_LOCATION 0x809
+#define mmMC_VM_AGP_TOP 0x80a
+#define mmMC_VM_AGP_BOT 0x80b
+#define mmMC_VM_AGP_BASE 0x80c
+#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80d
+#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80e
+#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80f
+#define mmMC_VM_DC_WRITE_CNTL 0x810
+#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0x811
+#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0x812
+#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0x813
+#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0x814
+#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0x815
+#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0x816
+#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0x817
+#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0x818
+#define mmMC_VM_MX_L1_TLB_CNTL 0x819
+#define mmMC_VM_FB_OFFSET 0x81a
+#define mmMC_VM_STEERING 0x81b
+#define mmMC_SHARED_CHREMAP2 0x81c
+#define mmMC_SHARED_VF_ENABLE 0x81d
+#define mmMC_SHARED_VIRT_RESET_REQ 0x81e
+#define mmMC_SHARED_ACTIVE_FCN_ID 0x81f
+#define mmMC_CONFIG_MCD 0x828
+#define mmMC_CG_CONFIG_MCD 0x829
+#define mmMC_MEM_POWER_LS 0x82a
+#define mmMC_SHARED_BLACKOUT_CNTL 0x82b
+#define mmMC_VM_MB_L1_TLB0_DEBUG 0x891
+#define mmMC_VM_MB_L1_TLB1_DEBUG 0x892
+#define mmMC_VM_MB_L1_TLB2_DEBUG 0x893
+#define mmMC_VM_MB_L1_TLB0_STATUS 0x895
+#define mmMC_VM_MB_L1_TLB1_STATUS 0x896
+#define mmMC_VM_MB_L1_TLB2_STATUS 0x897
+#define mmMC_VM_MB_L2ARBITER_L2_CREDITS 0x8a1
+#define mmMC_VM_MB_L1_TLB3_DEBUG 0x8a5
+#define mmMC_VM_MB_L1_TLB3_STATUS 0x8a6
+#define mmMC_VM_MD_L1_TLB0_DEBUG 0x998
+#define mmMC_VM_MD_L1_TLB1_DEBUG 0x999
+#define mmMC_VM_MD_L1_TLB2_DEBUG 0x99a
+#define mmMC_VM_MD_L1_TLB0_STATUS 0x99b
+#define mmMC_VM_MD_L1_TLB1_STATUS 0x99c
+#define mmMC_VM_MD_L1_TLB2_STATUS 0x99d
+#define mmMC_VM_MD_L2ARBITER_L2_CREDITS 0x9a4
+#define mmMC_VM_MD_L1_TLB3_DEBUG 0x9a7
+#define mmMC_VM_MD_L1_TLB3_STATUS 0x9a8
+#define mmMC_XPB_RTR_SRC_APRTR0 0x8cd
+#define mmMC_XPB_RTR_SRC_APRTR1 0x8ce
+#define mmMC_XPB_RTR_SRC_APRTR2 0x8cf
+#define mmMC_XPB_RTR_SRC_APRTR3 0x8d0
+#define mmMC_XPB_RTR_SRC_APRTR4 0x8d1
+#define mmMC_XPB_RTR_SRC_APRTR5 0x8d2
+#define mmMC_XPB_RTR_SRC_APRTR6 0x8d3
+#define mmMC_XPB_RTR_SRC_APRTR7 0x8d4
+#define mmMC_XPB_RTR_SRC_APRTR8 0x8d5
+#define mmMC_XPB_RTR_SRC_APRTR9 0x8d6
+#define mmMC_XPB_XDMA_RTR_SRC_APRTR0 0x8d7
+#define mmMC_XPB_XDMA_RTR_SRC_APRTR1 0x8d8
+#define mmMC_XPB_XDMA_RTR_SRC_APRTR2 0x8d9
+#define mmMC_XPB_XDMA_RTR_SRC_APRTR3 0x8da
+#define mmMC_XPB_RTR_DEST_MAP0 0x8db
+#define mmMC_XPB_RTR_DEST_MAP1 0x8dc
+#define mmMC_XPB_RTR_DEST_MAP2 0x8dd
+#define mmMC_XPB_RTR_DEST_MAP3 0x8de
+#define mmMC_XPB_RTR_DEST_MAP4 0x8df
+#define mmMC_XPB_RTR_DEST_MAP5 0x8e0
+#define mmMC_XPB_RTR_DEST_MAP6 0x8e1
+#define mmMC_XPB_RTR_DEST_MAP7 0x8e2
+#define mmMC_XPB_RTR_DEST_MAP8 0x8e3
+#define mmMC_XPB_RTR_DEST_MAP9 0x8e4
+#define mmMC_XPB_XDMA_RTR_DEST_MAP0 0x8e5
+#define mmMC_XPB_XDMA_RTR_DEST_MAP1 0x8e6
+#define mmMC_XPB_XDMA_RTR_DEST_MAP2 0x8e7
+#define mmMC_XPB_XDMA_RTR_DEST_MAP3 0x8e8
+#define mmMC_XPB_CLG_CFG0 0x8e9
+#define mmMC_XPB_CLG_CFG1 0x8ea
+#define mmMC_XPB_CLG_CFG2 0x8eb
+#define mmMC_XPB_CLG_CFG3 0x8ec
+#define mmMC_XPB_CLG_CFG4 0x8ed
+#define mmMC_XPB_CLG_CFG5 0x8ee
+#define mmMC_XPB_CLG_CFG6 0x8ef
+#define mmMC_XPB_CLG_CFG7 0x8f0
+#define mmMC_XPB_CLG_CFG8 0x8f1
+#define mmMC_XPB_CLG_CFG9 0x8f2
+#define mmMC_XPB_CLG_CFG10 0x8f3
+#define mmMC_XPB_CLG_CFG11 0x8f4
+#define mmMC_XPB_CLG_CFG12 0x8f5
+#define mmMC_XPB_CLG_CFG13 0x8f6
+#define mmMC_XPB_CLG_CFG14 0x8f7
+#define mmMC_XPB_CLG_CFG15 0x8f8
+#define mmMC_XPB_CLG_CFG16 0x8f9
+#define mmMC_XPB_CLG_CFG17 0x8fa
+#define mmMC_XPB_CLG_CFG18 0x8fb
+#define mmMC_XPB_CLG_CFG19 0x8fc
+#define mmMC_XPB_CLG_EXTRA 0x8fd
+#define mmMC_XPB_LB_ADDR 0x8fe
+#define mmMC_XPB_UNC_THRESH_HST 0x8ff
+#define mmMC_XPB_UNC_THRESH_SID 0x900
+#define mmMC_XPB_WCB_STS 0x901
+#define mmMC_XPB_WCB_CFG 0x902
+#define mmMC_XPB_P2P_BAR_CFG 0x903
+#define mmMC_XPB_P2P_BAR0 0x904
+#define mmMC_XPB_P2P_BAR1 0x905
+#define mmMC_XPB_P2P_BAR2 0x906
+#define mmMC_XPB_P2P_BAR3 0x907
+#define mmMC_XPB_P2P_BAR4 0x908
+#define mmMC_XPB_P2P_BAR5 0x909
+#define mmMC_XPB_P2P_BAR6 0x90a
+#define mmMC_XPB_P2P_BAR7 0x90b
+#define mmMC_XPB_P2P_BAR_SETUP 0x90c
+#define mmMC_XPB_P2P_BAR_DEBUG 0x90d
+#define mmMC_XPB_P2P_BAR_DELTA_ABOVE 0x90e
+#define mmMC_XPB_P2P_BAR_DELTA_BELOW 0x90f
+#define mmMC_XPB_PEER_SYS_BAR0 0x910
+#define mmMC_XPB_PEER_SYS_BAR1 0x911
+#define mmMC_XPB_PEER_SYS_BAR2 0x912
+#define mmMC_XPB_PEER_SYS_BAR3 0x913
+#define mmMC_XPB_PEER_SYS_BAR4 0x914
+#define mmMC_XPB_PEER_SYS_BAR5 0x915
+#define mmMC_XPB_PEER_SYS_BAR6 0x916
+#define mmMC_XPB_PEER_SYS_BAR7 0x917
+#define mmMC_XPB_PEER_SYS_BAR8 0x918
+#define mmMC_XPB_PEER_SYS_BAR9 0x919
+#define mmMC_XPB_XDMA_PEER_SYS_BAR0 0x91a
+#define mmMC_XPB_XDMA_PEER_SYS_BAR1 0x91b
+#define mmMC_XPB_XDMA_PEER_SYS_BAR2 0x91c
+#define mmMC_XPB_XDMA_PEER_SYS_BAR3 0x91d
+#define mmMC_XPB_CLK_GAT 0x91e
+#define mmMC_XPB_INTF_CFG 0x91f
+#define mmMC_XPB_INTF_STS 0x920
+#define mmMC_XPB_PIPE_STS 0x921
+#define mmMC_XPB_SUB_CTRL 0x922
+#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0x923
+#define mmMC_XPB_PERF_KNOBS 0x924
+#define mmMC_XPB_STICKY 0x925
+#define mmMC_XPB_STICKY_W1C 0x926
+#define mmMC_XPB_MISC_CFG 0x927
+#define mmMC_XPB_CLG_CFG20 0x928
+#define mmMC_XPB_CLG_CFG21 0x929
+#define mmMC_XPB_CLG_CFG22 0x92a
+#define mmMC_XPB_CLG_CFG23 0x92b
+#define mmMC_XPB_CLG_CFG24 0x92c
+#define mmMC_XPB_CLG_CFG25 0x92d
+#define mmMC_XPB_CLG_CFG26 0x92e
+#define mmMC_XPB_CLG_CFG27 0x92f
+#define mmMC_XPB_CLG_CFG28 0x930
+#define mmMC_XPB_CLG_CFG29 0x931
+#define mmMC_XPB_CLG_CFG30 0x932
+#define mmMC_XPB_CLG_CFG31 0x933
+#define mmMC_XPB_INTF_CFG2 0x934
+#define mmMC_XPB_CLG_EXTRA_RD 0x935
+#define mmMC_XPB_CLG_CFG32 0x936
+#define mmMC_XPB_CLG_CFG33 0x937
+#define mmMC_XPB_CLG_CFG34 0x938
+#define mmMC_XPB_CLG_CFG35 0x939
+#define mmMC_XPB_CLG_CFG36 0x93a
+#define mmMC_XBAR_ADDR_DEC 0xc80
+#define mmMC_XBAR_REMOTE 0xc81
+#define mmMC_XBAR_WRREQ_CREDIT 0xc82
+#define mmMC_XBAR_RDREQ_CREDIT 0xc83
+#define mmMC_XBAR_RDREQ_PRI_CREDIT 0xc84
+#define mmMC_XBAR_WRRET_CREDIT1 0xc85
+#define mmMC_XBAR_WRRET_CREDIT2 0xc86
+#define mmMC_XBAR_RDRET_CREDIT1 0xc87
+#define mmMC_XBAR_RDRET_CREDIT2 0xc88
+#define mmMC_XBAR_RDRET_PRI_CREDIT1 0xc89
+#define mmMC_XBAR_RDRET_PRI_CREDIT2 0xc8a
+#define mmMC_XBAR_CHTRIREMAP 0xc8b
+#define mmMC_XBAR_TWOCHAN 0xc8c
+#define mmMC_XBAR_ARB 0xc8d
+#define mmMC_XBAR_ARB_MAX_BURST 0xc8e
+#define mmMC_XBAR_FIFO_MON_CNTL0 0xc8f
+#define mmMC_XBAR_FIFO_MON_CNTL1 0xc90
+#define mmMC_XBAR_FIFO_MON_CNTL2 0xc91
+#define mmMC_XBAR_FIFO_MON_RSLT0 0xc92
+#define mmMC_XBAR_FIFO_MON_RSLT1 0xc93
+#define mmMC_XBAR_FIFO_MON_RSLT2 0xc94
+#define mmMC_XBAR_FIFO_MON_RSLT3 0xc95
+#define mmMC_XBAR_FIFO_MON_MAX_THSH 0xc96
+#define mmMC_XBAR_SPARE0 0xc97
+#define mmMC_XBAR_SPARE1 0xc98
+#define mmMC_CITF_PERFCOUNTER_LO 0x7a0
+#define mmMC_HUB_PERFCOUNTER_LO 0x7a1
+#define mmMC_RPB_PERFCOUNTER_LO 0x7a2
+#define mmMC_MCBVM_PERFCOUNTER_LO 0x7a3
+#define mmMC_MCDVM_PERFCOUNTER_LO 0x7a4
+#define mmMC_VM_L2_PERFCOUNTER_LO 0x7a5
+#define mmMC_ARB_PERFCOUNTER_LO 0x7a6
+#define mmATC_PERFCOUNTER_LO 0x7a7
+#define mmMC_CITF_PERFCOUNTER_HI 0x7a8
+#define mmMC_HUB_PERFCOUNTER_HI 0x7a9
+#define mmMC_MCBVM_PERFCOUNTER_HI 0x7aa
+#define mmMC_MCDVM_PERFCOUNTER_HI 0x7ab
+#define mmMC_RPB_PERFCOUNTER_HI 0x7ac
+#define mmMC_VM_L2_PERFCOUNTER_HI 0x7ad
+#define mmMC_ARB_PERFCOUNTER_HI 0x7ae
+#define mmATC_PERFCOUNTER_HI 0x7af
+#define mmMC_CITF_PERFCOUNTER0_CFG 0x7b0
+#define mmMC_CITF_PERFCOUNTER1_CFG 0x7b1
+#define mmMC_CITF_PERFCOUNTER2_CFG 0x7b2
+#define mmMC_CITF_PERFCOUNTER3_CFG 0x7b3
+#define mmMC_HUB_PERFCOUNTER0_CFG 0x7b4
+#define mmMC_HUB_PERFCOUNTER1_CFG 0x7b5
+#define mmMC_HUB_PERFCOUNTER2_CFG 0x7b6
+#define mmMC_HUB_PERFCOUNTER3_CFG 0x7b7
+#define mmMC_RPB_PERFCOUNTER0_CFG 0x7b8
+#define mmMC_RPB_PERFCOUNTER1_CFG 0x7b9
+#define mmMC_RPB_PERFCOUNTER2_CFG 0x7ba
+#define mmMC_RPB_PERFCOUNTER3_CFG 0x7bb
+#define mmMC_ARB_PERFCOUNTER0_CFG 0x7bc
+#define mmMC_ARB_PERFCOUNTER1_CFG 0x7bd
+#define mmMC_ARB_PERFCOUNTER2_CFG 0x7be
+#define mmMC_ARB_PERFCOUNTER3_CFG 0x7bf
+#define mmMC_MCBVM_PERFCOUNTER0_CFG 0x7c0
+#define mmMC_MCBVM_PERFCOUNTER1_CFG 0x7c1
+#define mmMC_MCBVM_PERFCOUNTER2_CFG 0x7c2
+#define mmMC_MCBVM_PERFCOUNTER3_CFG 0x7c3
+#define mmMC_MCDVM_PERFCOUNTER0_CFG 0x7c4
+#define mmMC_MCDVM_PERFCOUNTER1_CFG 0x7c5
+#define mmMC_MCDVM_PERFCOUNTER2_CFG 0x7c6
+#define mmMC_MCDVM_PERFCOUNTER3_CFG 0x7c7
+#define mmATC_PERFCOUNTER0_CFG 0x7c8
+#define mmATC_PERFCOUNTER1_CFG 0x7c9
+#define mmATC_PERFCOUNTER2_CFG 0x7ca
+#define mmATC_PERFCOUNTER3_CFG 0x7cb
+#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x7cc
+#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x7cd
+#define mmMC_CITF_PERFCOUNTER_RSLT_CNTL 0x7ce
+#define mmMC_HUB_PERFCOUNTER_RSLT_CNTL 0x7cf
+#define mmMC_RPB_PERFCOUNTER_RSLT_CNTL 0x7d0
+#define mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL 0x7d1
+#define mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL 0x7d2
+#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x7d3
+#define mmMC_ARB_PERFCOUNTER_RSLT_CNTL 0x7d4
+#define mmATC_PERFCOUNTER_RSLT_CNTL 0x7d5
+#define mmCHUB_ATC_PERFCOUNTER_LO 0x7d6
+#define mmCHUB_ATC_PERFCOUNTER_HI 0x7d7
+#define mmCHUB_ATC_PERFCOUNTER0_CFG 0x7d8
+#define mmCHUB_ATC_PERFCOUNTER1_CFG 0x7d9
+#define mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL 0x7da
+#define mmATC_VM_APERTURE0_LOW_ADDR 0xcc0
+#define mmATC_VM_APERTURE1_LOW_ADDR 0xcc1
+#define mmATC_VM_APERTURE0_HIGH_ADDR 0xcc2
+#define mmATC_VM_APERTURE1_HIGH_ADDR 0xcc3
+#define mmATC_VM_APERTURE0_CNTL 0xcc4
+#define mmATC_VM_APERTURE1_CNTL 0xcc5
+#define mmATC_VM_APERTURE0_CNTL2 0xcc6
+#define mmATC_VM_APERTURE1_CNTL2 0xcc7
+#define mmATC_ATS_CNTL 0xcc9
+#define mmATC_ATS_DEBUG 0xcca
+#define mmATC_ATS_FAULT_DEBUG 0xccb
+#define mmATC_ATS_STATUS 0xccc
+#define mmATC_ATS_FAULT_CNTL 0xccd
+#define mmATC_ATS_FAULT_STATUS_INFO 0xcce
+#define mmATC_ATS_FAULT_STATUS_ADDR 0xccf
+#define mmATC_ATS_DEFAULT_PAGE_LOW 0xcd0
+#define mmATC_ATS_DEFAULT_PAGE_CNTL 0xcd1
+#define mmATC_ATS_FAULT_STATUS_INFO2 0xcd2
+#define mmATC_MISC_CG 0xcd4
+#define mmATC_L2_CNTL 0xcd5
+#define mmATC_L2_CNTL2 0xcd6
+#define mmATC_L2_DEBUG 0xcd7
+#define mmATC_L2_DEBUG2 0xcd8
+#define mmATC_L2_CACHE_DATA0 0xcd9
+#define mmATC_L2_CACHE_DATA1 0xcda
+#define mmATC_L2_CACHE_DATA2 0xcdb
+#define mmATC_L1_CNTL 0xcdc
+#define mmATC_L1_ADDRESS_OFFSET 0xcdd
+#define mmATC_L1RD_DEBUG_TLB 0xcde
+#define mmATC_L1WR_DEBUG_TLB 0xcdf
+#define mmATC_L1RD_STATUS 0xce0
+#define mmATC_L1WR_STATUS 0xce1
+#define mmATC_L1RD_DEBUG2_TLB 0xce2
+#define mmATC_L1WR_DEBUG2_TLB 0xce3
+#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0xce6
+#define mmATC_VMID0_PASID_MAPPING 0xce7
+#define mmATC_VMID1_PASID_MAPPING 0xce8
+#define mmATC_VMID2_PASID_MAPPING 0xce9
+#define mmATC_VMID3_PASID_MAPPING 0xcea
+#define mmATC_VMID4_PASID_MAPPING 0xceb
+#define mmATC_VMID5_PASID_MAPPING 0xcec
+#define mmATC_VMID6_PASID_MAPPING 0xced
+#define mmATC_VMID7_PASID_MAPPING 0xcee
+#define mmATC_VMID8_PASID_MAPPING 0xcef
+#define mmATC_VMID9_PASID_MAPPING 0xcf0
+#define mmATC_VMID10_PASID_MAPPING 0xcf1
+#define mmATC_VMID11_PASID_MAPPING 0xcf2
+#define mmATC_VMID12_PASID_MAPPING 0xcf3
+#define mmATC_VMID13_PASID_MAPPING 0xcf4
+#define mmATC_VMID14_PASID_MAPPING 0xcf5
+#define mmATC_VMID15_PASID_MAPPING 0xcf6
+#define mmATC_ATS_VMID_STATUS 0xd07
+#define mmATC_ATS_SMU_STATUS 0xd08
+#define mmATC_L2_CNTL3 0xd09
+#define mmATC_L2_STATUS 0xd0a
+#define mmATC_L2_STATUS2 0xd0b
+#define mmGMCON_RENG_RAM_INDEX 0xd40
+#define mmGMCON_RENG_RAM_DATA 0xd41
+#define mmGMCON_RENG_EXECUTE 0xd42
+#define mmGMCON_MISC 0xd43
+#define mmGMCON_MISC2 0xd44
+#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 0xd45
+#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 0xd46
+#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 0xd47
+#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 0xd48
+#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 0xd49
+#define mmGMCON_PERF_MON_CNTL0 0xd4a
+#define mmGMCON_PERF_MON_CNTL1 0xd4b
+#define mmGMCON_PERF_MON_RSLT0 0xd4c
+#define mmGMCON_PERF_MON_RSLT1 0xd4d
+#define mmGMCON_PGFSM_CONFIG 0xd4e
+#define mmGMCON_PGFSM_WRITE 0xd4f
+#define mmGMCON_PGFSM_READ 0xd50
+#define mmGMCON_MISC3 0xd51
+#define mmGMCON_MASK 0xd52
+#define mmGMCON_LPT_TARGET 0xd53
+#define mmGMCON_DEBUG 0xd5f
+#define mmVM_L2_CNTL 0x500
+#define mmVM_L2_CNTL2 0x501
+#define mmVM_L2_CNTL3 0x502
+#define mmVM_L2_STATUS 0x503
+#define mmVM_CONTEXT0_CNTL 0x504
+#define mmVM_CONTEXT1_CNTL 0x505
+#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x506
+#define mmVM_DUMMY_PAGE_FAULT_ADDR 0x507
+#define mmVM_CONTEXT0_CNTL2 0x50c
+#define mmVM_CONTEXT1_CNTL2 0x50d
+#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x50e
+#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x50f
+#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x510
+#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x511
+#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x512
+#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x513
+#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x514
+#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x515
+#define mmVM_INVALIDATE_REQUEST 0x51e
+#define mmVM_INVALIDATE_RESPONSE 0x51f
+#define mmVM_PRT_APERTURE0_LOW_ADDR 0x52c
+#define mmVM_PRT_APERTURE1_LOW_ADDR 0x52d
+#define mmVM_PRT_APERTURE2_LOW_ADDR 0x52e
+#define mmVM_PRT_APERTURE3_LOW_ADDR 0x52f
+#define mmVM_PRT_APERTURE0_HIGH_ADDR 0x530
+#define mmVM_PRT_APERTURE1_HIGH_ADDR 0x531
+#define mmVM_PRT_APERTURE2_HIGH_ADDR 0x532
+#define mmVM_PRT_APERTURE3_HIGH_ADDR 0x533
+#define mmVM_PRT_CNTL 0x534
+#define mmVM_CONTEXTS_DISABLE 0x535
+#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0x536
+#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0x537
+#define mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT 0x538
+#define mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x539
+#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0x53e
+#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0x53f
+#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x546
+#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x547
+#define mmVM_FAULT_CLIENT_ID 0x54e
+#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f
+#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x550
+#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x551
+#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x552
+#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x553
+#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x554
+#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x555
+#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x556
+#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0x557
+#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0x558
+#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0x55f
+#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0x560
+#define mmVM_DEBUG 0x56f
+#define mmVM_L2_CG 0x570
+#define mmVM_L2_BANK_SELECT_MASKA 0x572
+#define mmVM_L2_BANK_SELECT_MASKB 0x573
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0x575
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0x576
+#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0x577
+#define mmVM_L2_CNTL4 0x578
+#define mmVM_L2_BANK_SELECT_RESERVED_CID 0x579
+#define mmVM_L2_BANK_SELECT_RESERVED_CID2 0x57a
+#define mmMC_VM_FB_SIZE_OFFSET_VF0 0xf980
+#define mmMC_VM_FB_SIZE_OFFSET_VF1 0xf981
+#define mmMC_VM_FB_SIZE_OFFSET_VF2 0xf982
+#define mmMC_VM_FB_SIZE_OFFSET_VF3 0xf983
+#define mmMC_VM_FB_SIZE_OFFSET_VF4 0xf984
+#define mmMC_VM_FB_SIZE_OFFSET_VF5 0xf985
+#define mmMC_VM_FB_SIZE_OFFSET_VF6 0xf986
+#define mmMC_VM_FB_SIZE_OFFSET_VF7 0xf987
+#define mmMC_VM_FB_SIZE_OFFSET_VF8 0xf988
+#define mmMC_VM_FB_SIZE_OFFSET_VF9 0xf989
+#define mmMC_VM_FB_SIZE_OFFSET_VF10 0xf98a
+#define mmMC_VM_FB_SIZE_OFFSET_VF11 0xf98b
+#define mmMC_VM_FB_SIZE_OFFSET_VF12 0xf98c
+#define mmMC_VM_FB_SIZE_OFFSET_VF13 0xf98d
+#define mmMC_VM_FB_SIZE_OFFSET_VF14 0xf98e
+#define mmMC_VM_FB_SIZE_OFFSET_VF15 0xf98f
+#define mmMC_VM_NB_MMIOBASE 0xf990
+#define mmMC_VM_NB_MMIOLIMIT 0xf991
+#define mmMC_VM_NB_PCI_CTRL 0xf992
+#define mmMC_VM_NB_PCI_ARB 0xf993
+#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0xf994
+#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0xf995
+#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0xf996
+#define mmMC_VM_NB_TOP_OF_DRAM3 0xf997
+#define mmMC_VM_MARC_BASE_LO_0 0xf998
+#define mmMC_VM_MARC_BASE_LO_1 0xf99e
+#define mmMC_VM_MARC_BASE_LO_2 0xf9a4
+#define mmMC_VM_MARC_BASE_LO_3 0xf9aa
+#define mmMC_VM_MARC_BASE_HI_0 0xf999
+#define mmMC_VM_MARC_BASE_HI_1 0xf99f
+#define mmMC_VM_MARC_BASE_HI_2 0xf9a5
+#define mmMC_VM_MARC_BASE_HI_3 0xf9ab
+#define mmMC_VM_MARC_RELOC_LO_0 0xf99a
+#define mmMC_VM_MARC_RELOC_LO_1 0xf9a0
+#define mmMC_VM_MARC_RELOC_LO_2 0xf9a6
+#define mmMC_VM_MARC_RELOC_LO_3 0xf9ac
+#define mmMC_VM_MARC_RELOC_HI_0 0xf99b
+#define mmMC_VM_MARC_RELOC_HI_1 0xf9a1
+#define mmMC_VM_MARC_RELOC_HI_2 0xf9a7
+#define mmMC_VM_MARC_RELOC_HI_3 0xf9ad
+#define mmMC_VM_MARC_LEN_LO_0 0xf99c
+#define mmMC_VM_MARC_LEN_LO_1 0xf9a2
+#define mmMC_VM_MARC_LEN_LO_2 0xf9a8
+#define mmMC_VM_MARC_LEN_LO_3 0xf9ae
+#define mmMC_VM_MARC_LEN_HI_0 0xf99d
+#define mmMC_VM_MARC_LEN_HI_1 0xf9a3
+#define mmMC_VM_MARC_LEN_HI_2 0xf9a9
+#define mmMC_VM_MARC_LEN_HI_3 0xf9af
+#define mmMC_VM_MARC_CNTL 0xf9b0
+#define mmMC_VM_MB_L1_TLS0_CNTL0 0xf9b1
+#define mmMC_VM_MB_L1_TLS0_CNTL1 0xf9b4
+#define mmMC_VM_MB_L1_TLS0_CNTL2 0xf9b7
+#define mmMC_VM_MB_L1_TLS0_CNTL3 0xf9ba
+#define mmMC_VM_MB_L1_TLS0_CNTL4 0xf9bd
+#define mmMC_VM_MB_L1_TLS0_CNTL5 0xf9c0
+#define mmMC_VM_MB_L1_TLS0_CNTL6 0xf9c3
+#define mmMC_VM_MB_L1_TLS0_CNTL7 0xf9c6
+#define mmMC_VM_MB_L1_TLS0_CNTL8 0xf9c9
+#define mmMC_VM_MB_L1_TLS0_START_ADDR0 0xf9b2
+#define mmMC_VM_MB_L1_TLS0_START_ADDR1 0xf9b5
+#define mmMC_VM_MB_L1_TLS0_START_ADDR2 0xf9b8
+#define mmMC_VM_MB_L1_TLS0_START_ADDR3 0xf9bb
+#define mmMC_VM_MB_L1_TLS0_START_ADDR4 0xf9be
+#define mmMC_VM_MB_L1_TLS0_START_ADDR5 0xf9c1
+#define mmMC_VM_MB_L1_TLS0_START_ADDR6 0xf9c4
+#define mmMC_VM_MB_L1_TLS0_START_ADDR7 0xf9c7
+#define mmMC_VM_MB_L1_TLS0_START_ADDR8 0xf9ca
+#define mmMC_VM_MB_L1_TLS0_END_ADDR0 0xf9b3
+#define mmMC_VM_MB_L1_TLS0_END_ADDR1 0xf9b6
+#define mmMC_VM_MB_L1_TLS0_END_ADDR2 0xf9b9
+#define mmMC_VM_MB_L1_TLS0_END_ADDR3 0xf9bc
+#define mmMC_VM_MB_L1_TLS0_END_ADDR4 0xf9bf
+#define mmMC_VM_MB_L1_TLS0_END_ADDR5 0xf9c2
+#define mmMC_VM_MB_L1_TLS0_END_ADDR6 0xf9c5
+#define mmMC_VM_MB_L1_TLS0_END_ADDR7 0xf9c8
+#define mmMC_VM_MB_L1_TLS0_END_ADDR8 0xf9cb
+#define mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS 0xf9cc
+#define mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR 0xf9cd
+#define mmMC_SEQ_CNTL 0xa25
+#define mmMC_SEQ_CNTL_2 0xad4
+#define mmMC_SEQ_DRAM 0xa26
+#define mmMC_SEQ_DRAM_2 0xa27
+#define mmMC_SEQ_RAS_TIMING 0xa28
+#define mmMC_SEQ_CAS_TIMING 0xa29
+#define mmMC_SEQ_MISC_TIMING 0xa2a
+#define mmMC_SEQ_MISC_TIMING2 0xa2b
+#define mmMC_SEQ_PMG_TIMING 0xa2c
+#define mmMC_SEQ_RD_CTL_D0 0xa2d
+#define mmMC_SEQ_RD_CTL_D1 0xa2e
+#define mmMC_SEQ_WR_CTL_D0 0xa2f
+#define mmMC_SEQ_WR_CTL_D1 0xa30
+#define mmMC_SEQ_WR_CTL_2 0xad5
+#define mmMC_SEQ_CMD 0xa31
+#define mmMC_PMG_CMD_EMRS 0xa83
+#define mmMC_PMG_CMD_MRS 0xaab
+#define mmMC_PMG_CMD_MRS1 0xad1
+#define mmMC_PMG_CMD_MRS2 0xad7
+#define mmMC_PMG_CFG 0xa84
+#define mmMC_PMG_AUTO_CMD 0xa34
+#define mmMC_PMG_AUTO_CFG 0xa35
+#define mmMC_IMP_CNTL 0xa36
+#define mmMC_IMP_DEBUG 0xa37
+#define mmMC_IMP_STATUS 0xa38
+#define mmMC_IMP_DQ_STATUS 0xabc
+#define mmMC_SEQ_WCDR_CTRL 0xa39
+#define mmMC_SEQ_TRAIN_WAKEUP_CNTL 0xa3a
+#define mmMC_SEQ_TRAIN_EDC_THRESHOLD 0xa3b
+#define mmMC_SEQ_TRAIN_EDC_THRESHOLD2 0xafe
+#define mmMC_SEQ_TRAIN_EDC_THRESHOLD3 0xaff
+#define mmMC_SEQ_TRAIN_WAKEUP_EDGE 0xa3c
+#define mmMC_SEQ_TRAIN_WAKEUP_MASK 0xa3d
+#define mmMC_SEQ_TRAIN_CAPTURE 0xa3e
+#define mmMC_SEQ_TRAIN_WAKEUP_CLEAR 0xa3f
+#define mmMC_SEQ_TRAIN_TIMING 0xa40
+#define mmMC_TRAIN_EDCCDR_R_D0 0xa41
+#define mmMC_TRAIN_EDCCDR_R_D1 0xa42
+#define mmMC_TRAIN_PRBSERR_0_D0 0xa43
+#define mmMC_TRAIN_PRBSERR_1_D0 0xa44
+#define mmMC_TRAIN_PRBSERR_2_D0 0xafb
+#define mmMC_TRAIN_EDC_STATUS_D0 0xa45
+#define mmMC_TRAIN_PRBSERR_0_D1 0xa46
+#define mmMC_TRAIN_PRBSERR_1_D1 0xa47
+#define mmMC_TRAIN_PRBSERR_2_D1 0xafc
+#define mmMC_TRAIN_EDC_STATUS_D1 0xa48
+#define mmMC_IO_TXCNTL_DPHY0_D0 0xa49
+#define mmMC_IO_TXCNTL_DPHY1_D0 0xa4a
+#define mmMC_IO_TXCNTL_APHY_D0 0xa4b
+#define mmMC_IO_RXCNTL_DPHY0_D0 0xa4c
+#define mmMC_IO_RXCNTL1_DPHY0_D0 0xadf
+#define mmMC_IO_RXCNTL_DPHY1_D0 0xa4d
+#define mmMC_IO_RXCNTL1_DPHY1_D0 0xae0
+#define mmMC_IO_DPHY_STR_CNTL_D0 0xa4e
+#define mmMC_IO_APHY_STR_CNTL_D0 0xa97
+#define mmMC_IO_TXCNTL_DPHY0_D1 0xa4f
+#define mmMC_IO_TXCNTL_DPHY1_D1 0xa50
+#define mmMC_IO_TXCNTL_APHY_D1 0xa51
+#define mmMC_IO_RXCNTL_DPHY0_D1 0xa52
+#define mmMC_IO_RXCNTL1_DPHY0_D1 0xae1
+#define mmMC_IO_RXCNTL_DPHY1_D1 0xa53
+#define mmMC_IO_RXCNTL1_DPHY1_D1 0xae2
+#define mmMC_IO_DPHY_STR_CNTL_D1 0xa54
+#define mmMC_IO_APHY_STR_CNTL_D1 0xa98
+#define mmMC_IO_CDRCNTL_D0 0xa55
+#define mmMC_IO_CDRCNTL1_D0 0xadd
+#define mmMC_IO_CDRCNTL2_D0 0xae4
+#define mmMC_IO_CDRCNTL_D1 0xa56
+#define mmMC_IO_CDRCNTL1_D1 0xade
+#define mmMC_IO_CDRCNTL2_D1 0xae5
+#define mmMC_SEQ_FIFO_CTL 0xa57
+#define mmMC_SEQ_TXFRAMING_BYTE0_D0 0xa58
+#define mmMC_SEQ_TXFRAMING_BYTE1_D0 0xa59
+#define mmMC_SEQ_TXFRAMING_BYTE2_D0 0xa5a
+#define mmMC_SEQ_TXFRAMING_BYTE3_D0 0xa5b
+#define mmMC_SEQ_TXFRAMING_DBI_D0 0xa5c
+#define mmMC_SEQ_TXFRAMING_EDC_D0 0xa5d
+#define mmMC_SEQ_TXFRAMING_FCK_D0 0xa5e
+#define mmMC_SEQ_TXFRAMING_BYTE0_D1 0xa60
+#define mmMC_SEQ_TXFRAMING_BYTE1_D1 0xa61
+#define mmMC_SEQ_TXFRAMING_BYTE2_D1 0xa62
+#define mmMC_SEQ_TXFRAMING_BYTE3_D1 0xa63
+#define mmMC_SEQ_TXFRAMING_DBI_D1 0xa64
+#define mmMC_SEQ_TXFRAMING_EDC_D1 0xa65
+#define mmMC_SEQ_TXFRAMING_FCK_D1 0xa66
+#define mmMC_SEQ_RXFRAMING_BYTE0_D0 0xa67
+#define mmMC_SEQ_RXFRAMING_BYTE1_D0 0xa68
+#define mmMC_SEQ_RXFRAMING_BYTE2_D0 0xa69
+#define mmMC_SEQ_RXFRAMING_BYTE3_D0 0xa6a
+#define mmMC_SEQ_RXFRAMING_DBI_D0 0xa6b
+#define mmMC_SEQ_RXFRAMING_EDC_D0 0xa6c
+#define mmMC_SEQ_RXFRAMING_BYTE0_D1 0xa6d
+#define mmMC_SEQ_RXFRAMING_BYTE1_D1 0xa6e
+#define mmMC_SEQ_RXFRAMING_BYTE2_D1 0xa6f
+#define mmMC_SEQ_RXFRAMING_BYTE3_D1 0xa70
+#define mmMC_SEQ_RXFRAMING_DBI_D1 0xa71
+#define mmMC_SEQ_RXFRAMING_EDC_D1 0xa72
+#define mmMC_IO_PAD_CNTL 0xa73
+#define mmMC_IO_PAD_CNTL_D0 0xa74
+#define mmMC_IO_PAD_CNTL_D1 0xa75
+#define mmMC_NPL_STATUS 0xa76
+#define mmMC_BIST_CMD_CNTL 0xa8e
+#define mmMC_BIST_CNTL 0xa05
+#define mmMC_BIST_AUTO_CNTL 0xa06
+#define mmMC_BIST_DIR_CNTL 0xa07
+#define mmMC_BIST_SADDR 0xa08
+#define mmMC_BIST_EADDR 0xa09
+#define mmMC_BIST_CMP_CNTL 0xa8d
+#define mmMC_BIST_CMP_CNTL_2 0xab6
+#define mmMC_BIST_DATA_WORD0 0xa0a
+#define mmMC_BIST_DATA_WORD1 0xa0b
+#define mmMC_BIST_DATA_WORD2 0xa0c
+#define mmMC_BIST_DATA_WORD3 0xa0d
+#define mmMC_BIST_DATA_WORD4 0xa0e
+#define mmMC_BIST_DATA_WORD5 0xa0f
+#define mmMC_BIST_DATA_WORD6 0xa10
+#define mmMC_BIST_DATA_WORD7 0xa11
+#define mmMC_BIST_DATA_MASK 0xa12
+#define mmMC_BIST_MISMATCH_ADDR 0xa13
+#define mmMC_BIST_RDATA_WORD0 0xa14
+#define mmMC_BIST_RDATA_WORD1 0xa15
+#define mmMC_BIST_RDATA_WORD2 0xa16
+#define mmMC_BIST_RDATA_WORD3 0xa17
+#define mmMC_BIST_RDATA_WORD4 0xa18
+#define mmMC_BIST_RDATA_WORD5 0xa19
+#define mmMC_BIST_RDATA_WORD6 0xa1a
+#define mmMC_BIST_RDATA_WORD7 0xa1b
+#define mmMC_BIST_RDATA_MASK 0xa1c
+#define mmMC_BIST_RDATA_EDC 0xa1d
+#define mmMC_SEQ_PERF_CNTL 0xa77
+#define mmMC_SEQ_PERF_CNTL_1 0xafd
+#define mmMC_SEQ_PERF_SEQ_CTL 0xa78
+#define mmMC_SEQ_PERF_SEQ_CNT_A_I0 0xa79
+#define mmMC_SEQ_PERF_SEQ_CNT_A_I1 0xa7a
+#define mmMC_SEQ_PERF_SEQ_CNT_B_I0 0xa7b
+#define mmMC_SEQ_PERF_SEQ_CNT_B_I1 0xa7c
+#define mmMC_SEQ_PERF_SEQ_CNT_C_I0 0xad9
+#define mmMC_SEQ_PERF_SEQ_CNT_C_I1 0xada
+#define mmMC_SEQ_PERF_SEQ_CNT_D_I0 0xadb
+#define mmMC_SEQ_PERF_SEQ_CNT_D_I1 0xadc
+#define mmMC_SEQ_STATUS_M 0xa7d
+#define mmMC_SEQ_STATUS_S 0xa20
+#define mmMC_CG_DATAPORT 0xa21
+#define mmMC_SEQ_VENDOR_ID_I0 0xa7e
+#define mmMC_SEQ_VENDOR_ID_I1 0xa7f
+#define mmMC_SEQ_MISC0 0xa80
+#define mmMC_SEQ_MISC1 0xa81
+#define mmMC_SEQ_RESERVE_0_S 0xa1e
+#define mmMC_SEQ_RESERVE_1_S 0xa1f
+#define mmMC_SEQ_RESERVE_M 0xa82
+#define mmMC_SEQ_IO_RESERVE_D0 0xab7
+#define mmMC_SEQ_IO_RESERVE_D1 0xab8
+#define mmMC_SEQ_SUP_CNTL 0xa32
+#define mmMC_SEQ_SUP_PGM 0xa33
+#define mmMC_SEQ_SUP_GP0_STAT 0xa8f
+#define mmMC_SEQ_SUP_GP1_STAT 0xa90
+#define mmMC_SEQ_SUP_GP2_STAT 0xa85
+#define mmMC_SEQ_SUP_GP3_STAT 0xa86
+#define mmMC_SEQ_SUP_IR_STAT 0xa87
+#define mmMC_SEQ_SUP_DEC_STAT 0xa88
+#define mmMC_SEQ_SUP_PGM_STAT 0xa89
+#define mmMC_SEQ_SUP_R_PGM 0xa8a
+#define mmMC_SEQ_MISC3 0xa8b
+#define mmMC_SEQ_MISC4 0xa8c
+#define mmMC_SEQ_MISC5 0xa95
+#define mmMC_SEQ_MISC6 0xa96
+#define mmMC_SEQ_MISC7 0xa99
+#define mmMC_SEQ_MISC8 0xa5f
+#define mmMC_SEQ_MISC9 0xae7
+#define mmMC_SEQ_CG 0xa9a
+#define mmMC_SEQ_BYTE_REMAP_D0 0xa93
+#define mmMC_SEQ_BYTE_REMAP_D1 0xa94
+#define mmMC_SEQ_BIT_REMAP_B0_D0 0xaa3
+#define mmMC_SEQ_BIT_REMAP_B1_D0 0xaa4
+#define mmMC_SEQ_BIT_REMAP_B2_D0 0xaa5
+#define mmMC_SEQ_BIT_REMAP_B3_D0 0xaa6
+#define mmMC_SEQ_BIT_REMAP_B0_D1 0xaa7
+#define mmMC_SEQ_BIT_REMAP_B1_D1 0xaa8
+#define mmMC_SEQ_BIT_REMAP_B2_D1 0xaa9
+#define mmMC_SEQ_BIT_REMAP_B3_D1 0xaaa
+#define mmMC_SEQ_RAS_TIMING_LP 0xa9b
+#define mmMC_SEQ_CAS_TIMING_LP 0xa9c
+#define mmMC_SEQ_MISC_TIMING_LP 0xa9d
+#define mmMC_SEQ_MISC_TIMING2_LP 0xa9e
+#define mmMC_SEQ_RD_CTL_D0_LP 0xac7
+#define mmMC_SEQ_RD_CTL_D1_LP 0xac8
+#define mmMC_SEQ_WR_CTL_D0_LP 0xa9f
+#define mmMC_SEQ_WR_CTL_D1_LP 0xaa0
+#define mmMC_SEQ_WR_CTL_2_LP 0xad6
+#define mmMC_SEQ_PMG_CMD_EMRS_LP 0xaa1
+#define mmMC_SEQ_PMG_CMD_MRS_LP 0xaa2
+#define mmMC_SEQ_PMG_CMD_MRS1_LP 0xad2
+#define mmMC_SEQ_PMG_CMD_MRS2_LP 0xad8
+#define mmMC_SEQ_PMG_TIMING_LP 0xad3
+#define mmMC_SEQ_IO_RWORD0 0xaac
+#define mmMC_SEQ_IO_RWORD1 0xaad
+#define mmMC_SEQ_IO_RWORD2 0xaae
+#define mmMC_SEQ_IO_RWORD3 0xaaf
+#define mmMC_SEQ_IO_RWORD4 0xab0
+#define mmMC_SEQ_IO_RWORD5 0xab1
+#define mmMC_SEQ_IO_RWORD6 0xab2
+#define mmMC_SEQ_IO_RWORD7 0xab3
+#define mmMC_SEQ_IO_RDBI 0xab4
+#define mmMC_SEQ_IO_REDC 0xab5
+#define mmMC_SEQ_TCG_CNTL 0xabd
+#define mmMC_SEQ_TSM_CTRL 0xabe
+#define mmMC_SEQ_TSM_GCNT 0xabf
+#define mmMC_SEQ_TSM_OCNT 0xac0
+#define mmMC_SEQ_TSM_NCNT 0xac1
+#define mmMC_SEQ_TSM_BCNT 0xac2
+#define mmMC_SEQ_TSM_FLAG 0xac3
+#define mmMC_SEQ_TSM_UPDATE 0xac4
+#define mmMC_SEQ_TSM_EDC 0xac5
+#define mmMC_SEQ_TSM_DBI 0xac6
+#define mmMC_SEQ_TSM_WCDR 0xae3
+#define mmMC_SEQ_TSM_MISC 0xae6
+#define mmMC_SEQ_TIMER_WR 0xac9
+#define mmMC_SEQ_TIMER_RD 0xaca
+#define mmMC_SEQ_DRAM_ERROR_INSERTION 0xacb
+#define mmMC_PHY_TIMING_D0 0xacc
+#define mmMC_PHY_TIMING_D1 0xacd
+#define mmMC_PHY_TIMING_2 0xace
+#define mmMC_SEQ_MPLL_OVERRIDE 0xa22
+#define mmMCLK_PWRMGT_CNTL 0xae8
+#define mmDLL_CNTL 0xae9
+#define mmMPLL_SEQ_UCODE_1 0xaea
+#define mmMPLL_SEQ_UCODE_2 0xaeb
+#define mmMPLL_CNTL_MODE 0xaec
+#define mmMPLL_FUNC_CNTL 0xaed
+#define mmMPLL_FUNC_CNTL_1 0xaee
+#define mmMPLL_FUNC_CNTL_2 0xaef
+#define mmMPLL_AD_FUNC_CNTL 0xaf0
+#define mmMPLL_DQ_FUNC_CNTL 0xaf1
+#define mmMPLL_TIME 0xaf2
+#define mmMPLL_SS1 0xaf3
+#define mmMPLL_SS2 0xaf4
+#define mmMPLL_CONTROL 0xaf5
+#define mmMPLL_AD_STATUS 0xaf6
+#define mmMPLL_DQ_0_0_STATUS 0xaf7
+#define mmMPLL_DQ_0_1_STATUS 0xaf8
+#define mmMPLL_DQ_1_0_STATUS 0xaf9
+#define mmMPLL_DQ_1_1_STATUS 0xafa
+#define mmMC_SEQ_PMG_PG_HWCNTL 0xab9
+#define mmMC_SEQ_PMG_PG_SWCNTL_0 0xaba
+#define mmMC_SEQ_PMG_PG_SWCNTL_1 0xabb
+#define mmMC_SEQ_TSM_DEBUG_INDEX 0xacf
+#define mmMC_SEQ_TSM_DEBUG_DATA 0xad0
+#define ixMC_TSM_DEBUG_GCNT 0x0
+#define ixMC_TSM_DEBUG_FLAG 0x1
+#define ixMC_TSM_DEBUG_MISC 0x2
+#define ixMC_TSM_DEBUG_BCNT0 0x3
+#define ixMC_TSM_DEBUG_BCNT1 0x4
+#define ixMC_TSM_DEBUG_BCNT2 0x5
+#define ixMC_TSM_DEBUG_BCNT3 0x6
+#define ixMC_TSM_DEBUG_BCNT4 0x7
+#define ixMC_TSM_DEBUG_BCNT5 0x8
+#define ixMC_TSM_DEBUG_BCNT6 0x9
+#define ixMC_TSM_DEBUG_BCNT7 0xa
+#define ixMC_TSM_DEBUG_BCNT8 0xb
+#define ixMC_TSM_DEBUG_BCNT9 0xc
+#define ixMC_TSM_DEBUG_BCNT10 0xd
+#define ixMC_TSM_DEBUG_ST01 0x10
+#define ixMC_TSM_DEBUG_ST23 0x11
+#define ixMC_TSM_DEBUG_ST45 0x12
+#define ixMC_TSM_DEBUG_BKPT 0x13
+#define mmMC_SEQ_IO_DEBUG_INDEX 0xa91
+#define mmMC_SEQ_IO_DEBUG_DATA 0xa92
+#define ixMC_IO_DEBUG_UP_0 0x0
+#define ixMC_IO_DEBUG_UP_1 0x1
+#define ixMC_IO_DEBUG_UP_2 0x2
+#define ixMC_IO_DEBUG_UP_3 0x3
+#define ixMC_IO_DEBUG_UP_4 0x4
+#define ixMC_IO_DEBUG_UP_5 0x5
+#define ixMC_IO_DEBUG_UP_6 0x6
+#define ixMC_IO_DEBUG_UP_7 0x7
+#define ixMC_IO_DEBUG_UP_8 0x8
+#define ixMC_IO_DEBUG_UP_9 0x9
+#define ixMC_IO_DEBUG_UP_10 0xa
+#define ixMC_IO_DEBUG_UP_11 0xb
+#define ixMC_IO_DEBUG_UP_12 0xc
+#define ixMC_IO_DEBUG_UP_13 0xd
+#define ixMC_IO_DEBUG_UP_14 0xe
+#define ixMC_IO_DEBUG_UP_15 0xf
+#define ixMC_IO_DEBUG_UP_16 0x10
+#define ixMC_IO_DEBUG_UP_17 0x11
+#define ixMC_IO_DEBUG_UP_18 0x12
+#define ixMC_IO_DEBUG_UP_19 0x13
+#define ixMC_IO_DEBUG_UP_20 0x14
+#define ixMC_IO_DEBUG_UP_21 0x15
+#define ixMC_IO_DEBUG_UP_22 0x16
+#define ixMC_IO_DEBUG_UP_23 0x17
+#define ixMC_IO_DEBUG_UP_24 0x18
+#define ixMC_IO_DEBUG_UP_25 0x19
+#define ixMC_IO_DEBUG_UP_26 0x1a
+#define ixMC_IO_DEBUG_UP_27 0x1b
+#define ixMC_IO_DEBUG_UP_28 0x1c
+#define ixMC_IO_DEBUG_UP_29 0x1d
+#define ixMC_IO_DEBUG_UP_30 0x1e
+#define ixMC_IO_DEBUG_UP_31 0x1f
+#define ixMC_IO_DEBUG_UP_32 0x20
+#define ixMC_IO_DEBUG_UP_33 0x21
+#define ixMC_IO_DEBUG_UP_34 0x22
+#define ixMC_IO_DEBUG_UP_35 0x23
+#define ixMC_IO_DEBUG_UP_36 0x24
+#define ixMC_IO_DEBUG_UP_37 0x25
+#define ixMC_IO_DEBUG_UP_38 0x26
+#define ixMC_IO_DEBUG_UP_39 0x27
+#define ixMC_IO_DEBUG_UP_40 0x28
+#define ixMC_IO_DEBUG_UP_41 0x29
+#define ixMC_IO_DEBUG_UP_42 0x2a
+#define ixMC_IO_DEBUG_UP_43 0x2b
+#define ixMC_IO_DEBUG_UP_44 0x2c
+#define ixMC_IO_DEBUG_UP_45 0x2d
+#define ixMC_IO_DEBUG_UP_46 0x2e
+#define ixMC_IO_DEBUG_UP_47 0x2f
+#define ixMC_IO_DEBUG_UP_48 0x30
+#define ixMC_IO_DEBUG_UP_49 0x31
+#define ixMC_IO_DEBUG_UP_50 0x32
+#define ixMC_IO_DEBUG_UP_51 0x33
+#define ixMC_IO_DEBUG_UP_52 0x34
+#define ixMC_IO_DEBUG_UP_53 0x35
+#define ixMC_IO_DEBUG_UP_54 0x36
+#define ixMC_IO_DEBUG_UP_55 0x37
+#define ixMC_IO_DEBUG_UP_56 0x38
+#define ixMC_IO_DEBUG_UP_57 0x39
+#define ixMC_IO_DEBUG_UP_58 0x3a
+#define ixMC_IO_DEBUG_UP_59 0x3b
+#define ixMC_IO_DEBUG_UP_60 0x3c
+#define ixMC_IO_DEBUG_UP_61 0x3d
+#define ixMC_IO_DEBUG_UP_62 0x3e
+#define ixMC_IO_DEBUG_UP_63 0x3f
+#define ixMC_IO_DEBUG_UP_64 0x40
+#define ixMC_IO_DEBUG_UP_65 0x41
+#define ixMC_IO_DEBUG_UP_66 0x42
+#define ixMC_IO_DEBUG_UP_67 0x43
+#define ixMC_IO_DEBUG_UP_68 0x44
+#define ixMC_IO_DEBUG_UP_69 0x45
+#define ixMC_IO_DEBUG_UP_70 0x46
+#define ixMC_IO_DEBUG_UP_71 0x47
+#define ixMC_IO_DEBUG_UP_72 0x48
+#define ixMC_IO_DEBUG_UP_73 0x49
+#define ixMC_IO_DEBUG_UP_74 0x4a
+#define ixMC_IO_DEBUG_UP_75 0x4b
+#define ixMC_IO_DEBUG_UP_76 0x4c
+#define ixMC_IO_DEBUG_UP_77 0x4d
+#define ixMC_IO_DEBUG_UP_78 0x4e
+#define ixMC_IO_DEBUG_UP_79 0x4f
+#define ixMC_IO_DEBUG_UP_80 0x50
+#define ixMC_IO_DEBUG_UP_81 0x51
+#define ixMC_IO_DEBUG_UP_82 0x52
+#define ixMC_IO_DEBUG_UP_83 0x53
+#define ixMC_IO_DEBUG_UP_84 0x54
+#define ixMC_IO_DEBUG_UP_85 0x55
+#define ixMC_IO_DEBUG_UP_86 0x56
+#define ixMC_IO_DEBUG_UP_87 0x57
+#define ixMC_IO_DEBUG_UP_88 0x58
+#define ixMC_IO_DEBUG_UP_89 0x59
+#define ixMC_IO_DEBUG_UP_90 0x5a
+#define ixMC_IO_DEBUG_UP_91 0x5b
+#define ixMC_IO_DEBUG_UP_92 0x5c
+#define ixMC_IO_DEBUG_UP_93 0x5d
+#define ixMC_IO_DEBUG_UP_94 0x5e
+#define ixMC_IO_DEBUG_UP_95 0x5f
+#define ixMC_IO_DEBUG_UP_96 0x60
+#define ixMC_IO_DEBUG_UP_97 0x61
+#define ixMC_IO_DEBUG_UP_98 0x62
+#define ixMC_IO_DEBUG_UP_99 0x63
+#define ixMC_IO_DEBUG_UP_100 0x64
+#define ixMC_IO_DEBUG_UP_101 0x65
+#define ixMC_IO_DEBUG_UP_102 0x66
+#define ixMC_IO_DEBUG_UP_103 0x67
+#define ixMC_IO_DEBUG_UP_104 0x68
+#define ixMC_IO_DEBUG_UP_105 0x69
+#define ixMC_IO_DEBUG_UP_106 0x6a
+#define ixMC_IO_DEBUG_UP_107 0x6b
+#define ixMC_IO_DEBUG_UP_108 0x6c
+#define ixMC_IO_DEBUG_UP_109 0x6d
+#define ixMC_IO_DEBUG_UP_110 0x6e
+#define ixMC_IO_DEBUG_UP_111 0x6f
+#define ixMC_IO_DEBUG_UP_112 0x70
+#define ixMC_IO_DEBUG_UP_113 0x71
+#define ixMC_IO_DEBUG_UP_114 0x72
+#define ixMC_IO_DEBUG_UP_115 0x73
+#define ixMC_IO_DEBUG_UP_116 0x74
+#define ixMC_IO_DEBUG_UP_117 0x75
+#define ixMC_IO_DEBUG_UP_118 0x76
+#define ixMC_IO_DEBUG_UP_119 0x77
+#define ixMC_IO_DEBUG_UP_120 0x78
+#define ixMC_IO_DEBUG_UP_121 0x79
+#define ixMC_IO_DEBUG_UP_122 0x7a
+#define ixMC_IO_DEBUG_UP_123 0x7b
+#define ixMC_IO_DEBUG_UP_124 0x7c
+#define ixMC_IO_DEBUG_UP_125 0x7d
+#define ixMC_IO_DEBUG_UP_126 0x7e
+#define ixMC_IO_DEBUG_UP_127 0x7f
+#define ixMC_IO_DEBUG_UP_128 0x80
+#define ixMC_IO_DEBUG_UP_129 0x81
+#define ixMC_IO_DEBUG_UP_130 0x82
+#define ixMC_IO_DEBUG_UP_131 0x83
+#define ixMC_IO_DEBUG_UP_132 0x84
+#define ixMC_IO_DEBUG_UP_133 0x85
+#define ixMC_IO_DEBUG_UP_134 0x86
+#define ixMC_IO_DEBUG_UP_135 0x87
+#define ixMC_IO_DEBUG_UP_136 0x88
+#define ixMC_IO_DEBUG_UP_137 0x89
+#define ixMC_IO_DEBUG_UP_138 0x8a
+#define ixMC_IO_DEBUG_UP_139 0x8b
+#define ixMC_IO_DEBUG_UP_140 0x8c
+#define ixMC_IO_DEBUG_UP_141 0x8d
+#define ixMC_IO_DEBUG_UP_142 0x8e
+#define ixMC_IO_DEBUG_UP_143 0x8f
+#define ixMC_IO_DEBUG_UP_144 0x90
+#define ixMC_IO_DEBUG_UP_145 0x91
+#define ixMC_IO_DEBUG_UP_146 0x92
+#define ixMC_IO_DEBUG_UP_147 0x93
+#define ixMC_IO_DEBUG_UP_148 0x94
+#define ixMC_IO_DEBUG_UP_149 0x95
+#define ixMC_IO_DEBUG_UP_150 0x96
+#define ixMC_IO_DEBUG_UP_151 0x97
+#define ixMC_IO_DEBUG_UP_152 0x98
+#define ixMC_IO_DEBUG_UP_153 0x99
+#define ixMC_IO_DEBUG_UP_154 0x9a
+#define ixMC_IO_DEBUG_UP_155 0x9b
+#define ixMC_IO_DEBUG_UP_156 0x9c
+#define ixMC_IO_DEBUG_UP_157 0x9d
+#define ixMC_IO_DEBUG_UP_158 0x9e
+#define ixMC_IO_DEBUG_UP_159 0x9f
+#define ixMC_IO_DEBUG_DQB0L_MISC_D0 0xa0
+#define ixMC_IO_DEBUG_DQB0H_MISC_D0 0xa1
+#define ixMC_IO_DEBUG_DQB1L_MISC_D0 0xa2
+#define ixMC_IO_DEBUG_DQB1H_MISC_D0 0xa3
+#define ixMC_IO_DEBUG_DQB2L_MISC_D0 0xa4
+#define ixMC_IO_DEBUG_DQB2H_MISC_D0 0xa5
+#define ixMC_IO_DEBUG_DQB3L_MISC_D0 0xa6
+#define ixMC_IO_DEBUG_DQB3H_MISC_D0 0xa7
+#define ixMC_IO_DEBUG_DBI_MISC_D0 0xa8
+#define ixMC_IO_DEBUG_EDC_MISC_D0 0xa9
+#define ixMC_IO_DEBUG_WCK_MISC_D0 0xaa
+#define ixMC_IO_DEBUG_CK_MISC_D0 0xab
+#define ixMC_IO_DEBUG_ADDRL_MISC_D0 0xac
+#define ixMC_IO_DEBUG_ADDRH_MISC_D0 0xad
+#define ixMC_IO_DEBUG_ACMD_MISC_D0 0xae
+#define ixMC_IO_DEBUG_CMD_MISC_D0 0xaf
+#define ixMC_IO_DEBUG_DQB0L_MISC_D1 0xb0
+#define ixMC_IO_DEBUG_DQB0H_MISC_D1 0xb1
+#define ixMC_IO_DEBUG_DQB1L_MISC_D1 0xb2
+#define ixMC_IO_DEBUG_DQB1H_MISC_D1 0xb3
+#define ixMC_IO_DEBUG_DQB2L_MISC_D1 0xb4
+#define ixMC_IO_DEBUG_DQB2H_MISC_D1 0xb5
+#define ixMC_IO_DEBUG_DQB3L_MISC_D1 0xb6
+#define ixMC_IO_DEBUG_DQB3H_MISC_D1 0xb7
+#define ixMC_IO_DEBUG_DBI_MISC_D1 0xb8
+#define ixMC_IO_DEBUG_EDC_MISC_D1 0xb9
+#define ixMC_IO_DEBUG_WCK_MISC_D1 0xba
+#define ixMC_IO_DEBUG_CK_MISC_D1 0xbb
+#define ixMC_IO_DEBUG_ADDRL_MISC_D1 0xbc
+#define ixMC_IO_DEBUG_ADDRH_MISC_D1 0xbd
+#define ixMC_IO_DEBUG_ACMD_MISC_D1 0xbe
+#define ixMC_IO_DEBUG_CMD_MISC_D1 0xbf
+#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D0 0xc0
+#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D0 0xc1
+#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D0 0xc2
+#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D0 0xc3
+#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D0 0xc4
+#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D0 0xc5
+#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D0 0xc6
+#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D0 0xc7
+#define ixMC_IO_DEBUG_DBI_CLKSEL_D0 0xc8
+#define ixMC_IO_DEBUG_EDC_CLKSEL_D0 0xc9
+#define ixMC_IO_DEBUG_WCK_CLKSEL_D0 0xca
+#define ixMC_IO_DEBUG_CK_CLKSEL_D0 0xcb
+#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D0 0xcc
+#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D0 0xcd
+#define ixMC_IO_DEBUG_ACMD_CLKSEL_D0 0xce
+#define ixMC_IO_DEBUG_CMD_CLKSEL_D0 0xcf
+#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D1 0xd0
+#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D1 0xd1
+#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D1 0xd2
+#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D1 0xd3
+#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D1 0xd4
+#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D1 0xd5
+#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D1 0xd6
+#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D1 0xd7
+#define ixMC_IO_DEBUG_DBI_CLKSEL_D1 0xd8
+#define ixMC_IO_DEBUG_EDC_CLKSEL_D1 0xd9
+#define ixMC_IO_DEBUG_WCK_CLKSEL_D1 0xda
+#define ixMC_IO_DEBUG_CK_CLKSEL_D1 0xdb
+#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D1 0xdc
+#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D1 0xdd
+#define ixMC_IO_DEBUG_ACMD_CLKSEL_D1 0xde
+#define ixMC_IO_DEBUG_CMD_CLKSEL_D1 0xdf
+#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D0 0xe0
+#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D0 0xe1
+#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D0 0xe2
+#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D0 0xe3
+#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D0 0xe4
+#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D0 0xe5
+#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D0 0xe6
+#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D0 0xe7
+#define ixMC_IO_DEBUG_DBI_OFSCAL_D0 0xe8
+#define ixMC_IO_DEBUG_EDC_OFSCAL_D0 0xe9
+#define ixMC_IO_DEBUG_WCK_OFSCAL_D0 0xea
+#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0 0xeb
+#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0 0xec
+#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0 0xed
+#define ixMC_IO_DEBUG_ACMD_OFSCAL_D0 0xee
+#define ixMC_IO_DEBUG_CMD_OFSCAL_D0 0xef
+#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D1 0xf0
+#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D1 0xf1
+#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D1 0xf2
+#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D1 0xf3
+#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D1 0xf4
+#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D1 0xf5
+#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D1 0xf6
+#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D1 0xf7
+#define ixMC_IO_DEBUG_DBI_OFSCAL_D1 0xf8
+#define ixMC_IO_DEBUG_EDC_OFSCAL_D1 0xf9
+#define ixMC_IO_DEBUG_WCK_OFSCAL_D1 0xfa
+#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1 0xfb
+#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1 0xfc
+#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1 0xfd
+#define ixMC_IO_DEBUG_ACMD_OFSCAL_D1 0xfe
+#define ixMC_IO_DEBUG_CMD_OFSCAL_D1 0xff
+#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D0 0x100
+#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D0 0x101
+#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D0 0x102
+#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D0 0x103
+#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D0 0x104
+#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D0 0x105
+#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D0 0x106
+#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D0 0x107
+#define ixMC_IO_DEBUG_DBI_RXPHASE_D0 0x108
+#define ixMC_IO_DEBUG_EDC_RXPHASE_D0 0x109
+#define ixMC_IO_DEBUG_WCK_RXPHASE_D0 0x10a
+#define ixMC_IO_DEBUG_CK_RXPHASE_D0 0x10b
+#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D0 0x10c
+#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D0 0x10d
+#define ixMC_IO_DEBUG_ACMD_RXPHASE_D0 0x10e
+#define ixMC_IO_DEBUG_CMD_RXPHASE_D0 0x10f
+#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D1 0x110
+#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D1 0x111
+#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D1 0x112
+#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D1 0x113
+#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D1 0x114
+#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D1 0x115
+#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D1 0x116
+#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D1 0x117
+#define ixMC_IO_DEBUG_DBI_RXPHASE_D1 0x118
+#define ixMC_IO_DEBUG_EDC_RXPHASE_D1 0x119
+#define ixMC_IO_DEBUG_WCK_RXPHASE_D1 0x11a
+#define ixMC_IO_DEBUG_CK_RXPHASE_D1 0x11b
+#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D1 0x11c
+#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D1 0x11d
+#define ixMC_IO_DEBUG_ACMD_RXPHASE_D1 0x11e
+#define ixMC_IO_DEBUG_CMD_RXPHASE_D1 0x11f
+#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D0 0x120
+#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D0 0x121
+#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D0 0x122
+#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D0 0x123
+#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D0 0x124
+#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D0 0x125
+#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D0 0x126
+#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D0 0x127
+#define ixMC_IO_DEBUG_DBI_TXPHASE_D0 0x128
+#define ixMC_IO_DEBUG_EDC_TXPHASE_D0 0x129
+#define ixMC_IO_DEBUG_WCK_TXPHASE_D0 0x12a
+#define ixMC_IO_DEBUG_CK_TXPHASE_D0 0x12b
+#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D0 0x12c
+#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D0 0x12d
+#define ixMC_IO_DEBUG_ACMD_TXPHASE_D0 0x12e
+#define ixMC_IO_DEBUG_CMD_TXPHASE_D0 0x12f
+#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D1 0x130
+#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D1 0x131
+#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D1 0x132
+#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D1 0x133
+#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D1 0x134
+#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D1 0x135
+#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D1 0x136
+#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D1 0x137
+#define ixMC_IO_DEBUG_DBI_TXPHASE_D1 0x138
+#define ixMC_IO_DEBUG_EDC_TXPHASE_D1 0x139
+#define ixMC_IO_DEBUG_WCK_TXPHASE_D1 0x13a
+#define ixMC_IO_DEBUG_CK_TXPHASE_D1 0x13b
+#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D1 0x13c
+#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D1 0x13d
+#define ixMC_IO_DEBUG_ACMD_TXPHASE_D1 0x13e
+#define ixMC_IO_DEBUG_CMD_TXPHASE_D1 0x13f
+#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0 0x140
+#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0 0x141
+#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0 0x142
+#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0 0x143
+#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0 0x144
+#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0 0x145
+#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0 0x146
+#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0 0x147
+#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0 0x148
+#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0 0x149
+#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0 0x14a
+#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0 0x14b
+#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0 0x14c
+#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0 0x14d
+#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0 0x14e
+#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0 0x14f
+#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1 0x150
+#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1 0x151
+#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1 0x152
+#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1 0x153
+#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1 0x154
+#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1 0x155
+#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1 0x156
+#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1 0x157
+#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1 0x158
+#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1 0x159
+#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1 0x15a
+#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1 0x15b
+#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1 0x15c
+#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1 0x15d
+#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1 0x15e
+#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1 0x15f
+#define ixMC_IO_DEBUG_DQB0L_TXSLF_D0 0x160
+#define ixMC_IO_DEBUG_DQB0H_TXSLF_D0 0x161
+#define ixMC_IO_DEBUG_DQB1L_TXSLF_D0 0x162
+#define ixMC_IO_DEBUG_DQB1H_TXSLF_D0 0x163
+#define ixMC_IO_DEBUG_DQB2L_TXSLF_D0 0x164
+#define ixMC_IO_DEBUG_DQB2H_TXSLF_D0 0x165
+#define ixMC_IO_DEBUG_DQB3L_TXSLF_D0 0x166
+#define ixMC_IO_DEBUG_DQB3H_TXSLF_D0 0x167
+#define ixMC_IO_DEBUG_DBI_TXSLF_D0 0x168
+#define ixMC_IO_DEBUG_EDC_TXSLF_D0 0x169
+#define ixMC_IO_DEBUG_WCK_TXSLF_D0 0x16a
+#define ixMC_IO_DEBUG_CK_TXSLF_D0 0x16b
+#define ixMC_IO_DEBUG_ADDRL_TXSLF_D0 0x16c
+#define ixMC_IO_DEBUG_ADDRH_TXSLF_D0 0x16d
+#define ixMC_IO_DEBUG_ACMD_TXSLF_D0 0x16e
+#define ixMC_IO_DEBUG_CMD_TXSLF_D0 0x16f
+#define ixMC_IO_DEBUG_DQB0L_TXSLF_D1 0x170
+#define ixMC_IO_DEBUG_DQB0H_TXSLF_D1 0x171
+#define ixMC_IO_DEBUG_DQB1L_TXSLF_D1 0x172
+#define ixMC_IO_DEBUG_DQB1H_TXSLF_D1 0x173
+#define ixMC_IO_DEBUG_DQB2L_TXSLF_D1 0x174
+#define ixMC_IO_DEBUG_DQB2H_TXSLF_D1 0x175
+#define ixMC_IO_DEBUG_DQB3L_TXSLF_D1 0x176
+#define ixMC_IO_DEBUG_DQB3H_TXSLF_D1 0x177
+#define ixMC_IO_DEBUG_DBI_TXSLF_D1 0x178
+#define ixMC_IO_DEBUG_EDC_TXSLF_D1 0x179
+#define ixMC_IO_DEBUG_WCK_TXSLF_D1 0x17a
+#define ixMC_IO_DEBUG_CK_TXSLF_D1 0x17b
+#define ixMC_IO_DEBUG_ADDRL_TXSLF_D1 0x17c
+#define ixMC_IO_DEBUG_ADDRH_TXSLF_D1 0x17d
+#define ixMC_IO_DEBUG_ACMD_TXSLF_D1 0x17e
+#define ixMC_IO_DEBUG_CMD_TXSLF_D1 0x17f
+#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0 0x180
+#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0 0x181
+#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0 0x182
+#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0 0x183
+#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0 0x184
+#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0 0x185
+#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0 0x186
+#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0 0x187
+#define ixMC_IO_DEBUG_DBI_TXBST_PD_D0 0x188
+#define ixMC_IO_DEBUG_EDC_TXBST_PD_D0 0x189
+#define ixMC_IO_DEBUG_WCK_TXBST_PD_D0 0x18a
+#define ixMC_IO_DEBUG_CK_TXBST_PD_D0 0x18b
+#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0 0x18c
+#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0 0x18d
+#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D0 0x18e
+#define ixMC_IO_DEBUG_CMD_TXBST_PD_D0 0x18f
+#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1 0x190
+#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1 0x191
+#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1 0x192
+#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1 0x193
+#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1 0x194
+#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1 0x195
+#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1 0x196
+#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1 0x197
+#define ixMC_IO_DEBUG_DBI_TXBST_PD_D1 0x198
+#define ixMC_IO_DEBUG_EDC_TXBST_PD_D1 0x199
+#define ixMC_IO_DEBUG_WCK_TXBST_PD_D1 0x19a
+#define ixMC_IO_DEBUG_CK_TXBST_PD_D1 0x19b
+#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1 0x19c
+#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1 0x19d
+#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D1 0x19e
+#define ixMC_IO_DEBUG_CMD_TXBST_PD_D1 0x19f
+#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0 0x1a0
+#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0 0x1a1
+#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0 0x1a2
+#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0 0x1a3
+#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0 0x1a4
+#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0 0x1a5
+#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0 0x1a6
+#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0 0x1a7
+#define ixMC_IO_DEBUG_DBI_TXBST_PU_D0 0x1a8
+#define ixMC_IO_DEBUG_EDC_TXBST_PU_D0 0x1a9
+#define ixMC_IO_DEBUG_WCK_TXBST_PU_D0 0x1aa
+#define ixMC_IO_DEBUG_CK_TXBST_PU_D0 0x1ab
+#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0 0x1ac
+#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0 0x1ad
+#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D0 0x1ae
+#define ixMC_IO_DEBUG_CMD_TXBST_PU_D0 0x1af
+#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1 0x1b0
+#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1 0x1b1
+#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1 0x1b2
+#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1 0x1b3
+#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1 0x1b4
+#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1 0x1b5
+#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1 0x1b6
+#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1 0x1b7
+#define ixMC_IO_DEBUG_DBI_TXBST_PU_D1 0x1b8
+#define ixMC_IO_DEBUG_EDC_TXBST_PU_D1 0x1b9
+#define ixMC_IO_DEBUG_WCK_TXBST_PU_D1 0x1ba
+#define ixMC_IO_DEBUG_CK_TXBST_PU_D1 0x1bb
+#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1 0x1bc
+#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1 0x1bd
+#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D1 0x1be
+#define ixMC_IO_DEBUG_CMD_TXBST_PU_D1 0x1bf
+#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D0 0x1c0
+#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D0 0x1c1
+#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D0 0x1c2
+#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D0 0x1c3
+#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D0 0x1c4
+#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D0 0x1c5
+#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D0 0x1c6
+#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D0 0x1c7
+#define ixMC_IO_DEBUG_DBI_RX_EQ_D0 0x1c8
+#define ixMC_IO_DEBUG_EDC_RX_EQ_D0 0x1c9
+#define ixMC_IO_DEBUG_WCK_RX_EQ_D0 0x1ca
+#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0 0x1cb
+#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0 0x1cc
+#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0 0x1cd
+#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0 0x1ce
+#define ixMC_IO_DEBUG_CMD_RX_EQ_D0 0x1cf
+#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D1 0x1d0
+#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D1 0x1d1
+#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D1 0x1d2
+#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D1 0x1d3
+#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D1 0x1d4
+#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D1 0x1d5
+#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D1 0x1d6
+#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D1 0x1d7
+#define ixMC_IO_DEBUG_DBI_RX_EQ_D1 0x1d8
+#define ixMC_IO_DEBUG_EDC_RX_EQ_D1 0x1d9
+#define ixMC_IO_DEBUG_WCK_RX_EQ_D1 0x1da
+#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1 0x1db
+#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1 0x1dc
+#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1 0x1dd
+#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1 0x1de
+#define ixMC_IO_DEBUG_CMD_RX_EQ_D1 0x1df
+#define ixMC_IO_DEBUG_WCDR_MISC_D0 0x1e0
+#define ixMC_IO_DEBUG_WCDR_CLKSEL_D0 0x1e1
+#define ixMC_IO_DEBUG_WCDR_OFSCAL_D0 0x1e2
+#define ixMC_IO_DEBUG_WCDR_RXPHASE_D0 0x1e3
+#define ixMC_IO_DEBUG_WCDR_TXPHASE_D0 0x1e4
+#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0 0x1e5
+#define ixMC_IO_DEBUG_WCDR_TXSLF_D0 0x1e6
+#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D0 0x1e7
+#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D0 0x1e8
+#define ixMC_IO_DEBUG_WCDR_RX_EQ_D0 0x1e9
+#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0 0x1ea
+#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0 0x1eb
+#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0 0x1ec
+#define ixMC_IO_DEBUG_WCDR_MISC_D1 0x1f0
+#define ixMC_IO_DEBUG_WCDR_CLKSEL_D1 0x1f1
+#define ixMC_IO_DEBUG_WCDR_OFSCAL_D1 0x1f2
+#define ixMC_IO_DEBUG_WCDR_RXPHASE_D1 0x1f3
+#define ixMC_IO_DEBUG_WCDR_TXPHASE_D1 0x1f4
+#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1 0x1f5
+#define ixMC_IO_DEBUG_WCDR_TXSLF_D1 0x1f6
+#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D1 0x1f7
+#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D1 0x1f8
+#define ixMC_IO_DEBUG_WCDR_RX_EQ_D1 0x1f9
+#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1 0x1fa
+#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1 0x1fb
+#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1 0x1fc
+#define mmMC_SEQ_CNTL_3 0xd80
+#define mmMC_SEQ_G5PDX_CTRL 0xd81
+#define mmMC_SEQ_G5PDX_CTRL_LP 0xd82
+#define mmMC_SEQ_G5PDX_CMD0 0xd83
+#define mmMC_SEQ_G5PDX_CMD0_LP 0xd84
+#define mmMC_SEQ_G5PDX_CMD1 0xd85
+#define mmMC_SEQ_G5PDX_CMD1_LP 0xd86
+#define mmMC_SEQ_SREG_READ 0xd87
+#define mmMC_SEQ_SREG_STATUS 0xd88
+#define mmMC_SEQ_PHYREG_BCAST 0xd89
+#define mmMC_SEQ_PMG_DVS_CTL 0xd8a
+#define mmMC_SEQ_PMG_DVS_CTL_LP 0xd8b
+#define mmMC_SEQ_PMG_DVS_CMD 0xd8c
+#define mmMC_SEQ_PMG_DVS_CMD_LP 0xd8d
+#define mmMC_SEQ_DLL_STBY 0xd8e
+#define mmMC_SEQ_DLL_STBY_LP 0xd8f
+#define mmMC_DLB_MISCCTRL0 0xd90
+#define mmMC_DLB_MISCCTRL1 0xd91
+#define mmMC_DLB_MISCCTRL2 0xd92
+#define mmMC_DLB_CONFIG0 0xd93
+#define mmMC_DLB_CONFIG1 0xd94
+#define mmMC_DLB_SETUP 0xd95
+#define mmMC_DLB_SETUPSWEEP 0xd96
+#define mmMC_DLB_SETUPFIFO 0xd97
+#define mmMC_DLB_WRITE_MASK 0xd98
+#define mmMC_DLB_STATUS 0xd99
+#define mmMC_DLB_STATUS_MISC0 0xd9a
+#define mmMC_DLB_STATUS_MISC1 0xd9b
+#define mmMC_DLB_STATUS_MISC2 0xd9c
+#define mmMC_DLB_STATUS_MISC3 0xd9d
+#define mmMC_DLB_STATUS_MISC4 0xd9e
+#define mmMC_DLB_STATUS_MISC5 0xd9f
+#define mmMC_DLB_STATUS_MISC6 0xda0
+#define mmMC_DLB_STATUS_MISC7 0xda1
+#define mmMC_ARB_HARSH_EN_RD 0xdc0
+#define mmMC_ARB_HARSH_EN_WR 0xdc1
+#define mmMC_ARB_HARSH_TX_HI0_RD 0xdc2
+#define mmMC_ARB_HARSH_TX_HI0_WR 0xdc3
+#define mmMC_ARB_HARSH_TX_HI1_RD 0xdc4
+#define mmMC_ARB_HARSH_TX_HI1_WR 0xdc5
+#define mmMC_ARB_HARSH_TX_LO0_RD 0xdc6
+#define mmMC_ARB_HARSH_TX_LO0_WR 0xdc7
+#define mmMC_ARB_HARSH_TX_LO1_RD 0xdc8
+#define mmMC_ARB_HARSH_TX_LO1_WR 0xdc9
+#define mmMC_ARB_HARSH_BWPERIOD0_RD 0xdca
+#define mmMC_ARB_HARSH_BWPERIOD0_WR 0xdcb
+#define mmMC_ARB_HARSH_BWPERIOD1_RD 0xdcc
+#define mmMC_ARB_HARSH_BWPERIOD1_WR 0xdcd
+#define mmMC_ARB_HARSH_BWCNT0_RD 0xdce
+#define mmMC_ARB_HARSH_BWCNT0_WR 0xdcf
+#define mmMC_ARB_HARSH_BWCNT1_RD 0xdd0
+#define mmMC_ARB_HARSH_BWCNT1_WR 0xdd1
+#define mmMC_ARB_HARSH_SAT0_RD 0xdd2
+#define mmMC_ARB_HARSH_SAT0_WR 0xdd3
+#define mmMC_ARB_HARSH_SAT1_RD 0xdd4
+#define mmMC_ARB_HARSH_SAT1_WR 0xdd5
+#define mmMC_ARB_HARSH_CTL_RD 0xdd6
+#define mmMC_ARB_HARSH_CTL_WR 0xdd7
+#define mmMC_ARB_GRUB_PRIORITY1_RD 0xdd8
+#define mmMC_ARB_GRUB_PRIORITY1_WR 0xdd9
+#define mmMC_ARB_GRUB_PRIORITY2_RD 0xdda
+#define mmMC_ARB_GRUB_PRIORITY2_WR 0xddb
+#define mmMCIF_WB_BUFMGR_SW_CONTROL 0x5e78
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x5e78
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x5eb8
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0x5ef8
+#define mmMCIF_WB_BUFMGR_CUR_LINE_R 0x5e79
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x5e79
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x5eb9
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0x5ef9
+#define mmMCIF_WB_BUFMGR_STATUS 0x5e7a
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x5e7a
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x5eba
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0x5efa
+#define mmMCIF_WB_BUF_PITCH 0x5e7b
+#define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x5e7b
+#define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x5ebb
+#define mmMCIF_WB2_MCIF_WB_BUF_PITCH 0x5efb
+#define mmMCIF_WB_BUF_1_STATUS 0x5e7c
+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x5e7c
+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x5ebc
+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0x5efc
+#define mmMCIF_WB_BUF_1_STATUS2 0x5e7d
+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x5e7d
+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x5ebd
+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0x5efd
+#define mmMCIF_WB_BUF_2_STATUS 0x5e7e
+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x5e7e
+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x5ebe
+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0x5efe
+#define mmMCIF_WB_BUF_2_STATUS2 0x5e7f
+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x5e7f
+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x5ebf
+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0x5eff
+#define mmMCIF_WB_BUF_3_STATUS 0x5e80
+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x5e80
+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x5ec0
+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0x5f00
+#define mmMCIF_WB_BUF_3_STATUS2 0x5e81
+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x5e81
+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x5ec1
+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0x5f01
+#define mmMCIF_WB_BUF_4_STATUS 0x5e82
+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x5e82
+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x5ec2
+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0x5f02
+#define mmMCIF_WB_BUF_4_STATUS2 0x5e83
+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x5e83
+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x5ec3
+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0x5f03
+#define mmMCIF_WB_ARBITRATION_CONTROL 0x5e84
+#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x5e84
+#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x5ec4
+#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0x5f04
+#define mmMCIF_WB_URGENCY_WATERMARK 0x5e85
+#define mmMCIF_WB0_MCIF_WB_URGENCY_WATERMARK 0x5e85
+#define mmMCIF_WB1_MCIF_WB_URGENCY_WATERMARK 0x5ec5
+#define mmMCIF_WB2_MCIF_WB_URGENCY_WATERMARK 0x5f05
+#define mmMCIF_WB_TEST_DEBUG_INDEX 0x5e86
+#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX 0x5e86
+#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX 0x5ec6
+#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX 0x5f06
+#define mmMCIF_WB_TEST_DEBUG_DATA 0x5e87
+#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA 0x5e87
+#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA 0x5ec7
+#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA 0x5f07
+#define mmMCIF_WB_BUF_1_ADDR_Y 0x5e88
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x5e88
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x5ec8
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0x5f08
+#define mmMCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5e89
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5e89
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5ec9
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5f09
+#define mmMCIF_WB_BUF_1_ADDR_C 0x5e8a
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x5e8a
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x5eca
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0x5f0a
+#define mmMCIF_WB_BUF_1_ADDR_C_OFFSET 0x5e8b
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5e8b
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5ecb
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5f0b
+#define mmMCIF_WB_BUF_2_ADDR_Y 0x5e8c
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x5e8c
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x5ecc
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0x5f0c
+#define mmMCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5e8d
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5e8d
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5ecd
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5f0d
+#define mmMCIF_WB_BUF_2_ADDR_C 0x5e8e
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x5e8e
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x5ece
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0x5f0e
+#define mmMCIF_WB_BUF_2_ADDR_C_OFFSET 0x5e8f
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5e8f
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5ecf
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5f0f
+#define mmMCIF_WB_BUF_3_ADDR_Y 0x5e90
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x5e90
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x5ed0
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0x5f10
+#define mmMCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5e91
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5e91
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5ed1
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5f11
+#define mmMCIF_WB_BUF_3_ADDR_C 0x5e92
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x5e92
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x5ed2
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0x5f12
+#define mmMCIF_WB_BUF_3_ADDR_C_OFFSET 0x5e93
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5e93
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5ed3
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5f13
+#define mmMCIF_WB_BUF_4_ADDR_Y 0x5e94
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x5e94
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x5ed4
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0x5f14
+#define mmMCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5e95
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5e95
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5ed5
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5f15
+#define mmMCIF_WB_BUF_4_ADDR_C 0x5e96
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x5e96
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x5ed6
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0x5f16
+#define mmMCIF_WB_BUF_4_ADDR_C_OFFSET 0x5e97
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5e97
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5ed7
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5f17
+#define mmMCIF_WB_BUFMGR_VCE_CONTROL 0x5e98
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x5e98
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x5ed8
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0x5f18
+#define mmMCIF_WB_HVVMID_CONTROL 0x5e99
+#define mmMCIF_WB0_MCIF_WB_HVVMID_CONTROL 0x5e99
+#define mmMCIF_WB1_MCIF_WB_HVVMID_CONTROL 0x5ed9
+#define mmMCIF_WB2_MCIF_WB_HVVMID_CONTROL 0x5f19
+
+#endif /* GMC_8_1_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_enum.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_enum.h
new file mode 100644
index 000000000000..05b80f2bb147
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_enum.h
@@ -0,0 +1,1198 @@
+/*
+ * GMC_8_1 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GMC_8_1_ENUM_H
+#define GMC_8_1_ENUM_H
+
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0x0,
+ ENDIAN_8IN16 = 0x1,
+ ENDIAN_8IN32 = 0x2,
+ ENDIAN_8IN64 = 0x3,
+} SurfaceEndian;
+typedef enum ArrayMode {
+ ARRAY_LINEAR_GENERAL = 0x0,
+ ARRAY_LINEAR_ALIGNED = 0x1,
+ ARRAY_1D_TILED_THIN1 = 0x2,
+ ARRAY_1D_TILED_THICK = 0x3,
+ ARRAY_2D_TILED_THIN1 = 0x4,
+ ARRAY_PRT_TILED_THIN1 = 0x5,
+ ARRAY_PRT_2D_TILED_THIN1 = 0x6,
+ ARRAY_2D_TILED_THICK = 0x7,
+ ARRAY_2D_TILED_XTHICK = 0x8,
+ ARRAY_PRT_TILED_THICK = 0x9,
+ ARRAY_PRT_2D_TILED_THICK = 0xa,
+ ARRAY_PRT_3D_TILED_THIN1 = 0xb,
+ ARRAY_3D_TILED_THIN1 = 0xc,
+ ARRAY_3D_TILED_THICK = 0xd,
+ ARRAY_3D_TILED_XTHICK = 0xe,
+ ARRAY_PRT_3D_TILED_THICK = 0xf,
+} ArrayMode;
+typedef enum PipeTiling {
+ CONFIG_1_PIPE = 0x0,
+ CONFIG_2_PIPE = 0x1,
+ CONFIG_4_PIPE = 0x2,
+ CONFIG_8_PIPE = 0x3,
+} PipeTiling;
+typedef enum BankTiling {
+ CONFIG_4_BANK = 0x0,
+ CONFIG_8_BANK = 0x1,
+} BankTiling;
+typedef enum GroupInterleave {
+ CONFIG_256B_GROUP = 0x0,
+ CONFIG_512B_GROUP = 0x1,
+} GroupInterleave;
+typedef enum RowTiling {
+ CONFIG_1KB_ROW = 0x0,
+ CONFIG_2KB_ROW = 0x1,
+ CONFIG_4KB_ROW = 0x2,
+ CONFIG_8KB_ROW = 0x3,
+ CONFIG_1KB_ROW_OPT = 0x4,
+ CONFIG_2KB_ROW_OPT = 0x5,
+ CONFIG_4KB_ROW_OPT = 0x6,
+ CONFIG_8KB_ROW_OPT = 0x7,
+} RowTiling;
+typedef enum BankSwapBytes {
+ CONFIG_128B_SWAPS = 0x0,
+ CONFIG_256B_SWAPS = 0x1,
+ CONFIG_512B_SWAPS = 0x2,
+ CONFIG_1KB_SWAPS = 0x3,
+} BankSwapBytes;
+typedef enum SampleSplitBytes {
+ CONFIG_1KB_SPLIT = 0x0,
+ CONFIG_2KB_SPLIT = 0x1,
+ CONFIG_4KB_SPLIT = 0x2,
+ CONFIG_8KB_SPLIT = 0x3,
+} SampleSplitBytes;
+typedef enum NumPipes {
+ ADDR_CONFIG_1_PIPE = 0x0,
+ ADDR_CONFIG_2_PIPE = 0x1,
+ ADDR_CONFIG_4_PIPE = 0x2,
+ ADDR_CONFIG_8_PIPE = 0x3,
+} NumPipes;
+typedef enum PipeInterleaveSize {
+ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
+ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
+} PipeInterleaveSize;
+typedef enum BankInterleaveSize {
+ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
+ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
+ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
+ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
+} BankInterleaveSize;
+typedef enum NumShaderEngines {
+ ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
+ ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
+} NumShaderEngines;
+typedef enum ShaderEngineTileSize {
+ ADDR_CONFIG_SE_TILE_16 = 0x0,
+ ADDR_CONFIG_SE_TILE_32 = 0x1,
+} ShaderEngineTileSize;
+typedef enum NumGPUs {
+ ADDR_CONFIG_1_GPU = 0x0,
+ ADDR_CONFIG_2_GPU = 0x1,
+ ADDR_CONFIG_4_GPU = 0x2,
+} NumGPUs;
+typedef enum MultiGPUTileSize {
+ ADDR_CONFIG_GPU_TILE_16 = 0x0,
+ ADDR_CONFIG_GPU_TILE_32 = 0x1,
+ ADDR_CONFIG_GPU_TILE_64 = 0x2,
+ ADDR_CONFIG_GPU_TILE_128 = 0x3,
+} MultiGPUTileSize;
+typedef enum RowSize {
+ ADDR_CONFIG_1KB_ROW = 0x0,
+ ADDR_CONFIG_2KB_ROW = 0x1,
+ ADDR_CONFIG_4KB_ROW = 0x2,
+} RowSize;
+typedef enum NumLowerPipes {
+ ADDR_CONFIG_1_LOWER_PIPES = 0x0,
+ ADDR_CONFIG_2_LOWER_PIPES = 0x1,
+} NumLowerPipes;
+typedef enum DebugBlockId {
+ DBG_CLIENT_BLKID_RESERVED = 0x0,
+ DBG_CLIENT_BLKID_dbg = 0x1,
+ DBG_CLIENT_BLKID_scf2 = 0x2,
+ DBG_CLIENT_BLKID_mcd5 = 0x3,
+ DBG_CLIENT_BLKID_vmc = 0x4,
+ DBG_CLIENT_BLKID_sx30 = 0x5,
+ DBG_CLIENT_BLKID_mcd2 = 0x6,
+ DBG_CLIENT_BLKID_bci1 = 0x7,
+ DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8,
+ DBG_CLIENT_BLKID_mcc0 = 0x9,
+ DBG_CLIENT_BLKID_uvdf_0 = 0xa,
+ DBG_CLIENT_BLKID_uvdf_1 = 0xb,
+ DBG_CLIENT_BLKID_uvdf_2 = 0xc,
+ DBG_CLIENT_BLKID_uvdi_0 = 0xd,
+ DBG_CLIENT_BLKID_bci0 = 0xe,
+ DBG_CLIENT_BLKID_vcec0_0 = 0xf,
+ DBG_CLIENT_BLKID_cb100 = 0x10,
+ DBG_CLIENT_BLKID_cb001 = 0x11,
+ DBG_CLIENT_BLKID_mcd4 = 0x12,
+ DBG_CLIENT_BLKID_tmonw00 = 0x13,
+ DBG_CLIENT_BLKID_cb101 = 0x14,
+ DBG_CLIENT_BLKID_sx10 = 0x15,
+ DBG_CLIENT_BLKID_cb301 = 0x16,
+ DBG_CLIENT_BLKID_tmonw01 = 0x17,
+ DBG_CLIENT_BLKID_vcea0_0 = 0x18,
+ DBG_CLIENT_BLKID_vcea0_1 = 0x19,
+ DBG_CLIENT_BLKID_vcea0_2 = 0x1a,
+ DBG_CLIENT_BLKID_vcea0_3 = 0x1b,
+ DBG_CLIENT_BLKID_scf1 = 0x1c,
+ DBG_CLIENT_BLKID_sx20 = 0x1d,
+ DBG_CLIENT_BLKID_spim1 = 0x1e,
+ DBG_CLIENT_BLKID_pa10 = 0x1f,
+ DBG_CLIENT_BLKID_pa00 = 0x20,
+ DBG_CLIENT_BLKID_gmcon = 0x21,
+ DBG_CLIENT_BLKID_mcb = 0x22,
+ DBG_CLIENT_BLKID_vgt0 = 0x23,
+ DBG_CLIENT_BLKID_pc0 = 0x24,
+ DBG_CLIENT_BLKID_bci2 = 0x25,
+ DBG_CLIENT_BLKID_uvdb_0 = 0x26,
+ DBG_CLIENT_BLKID_spim3 = 0x27,
+ DBG_CLIENT_BLKID_cpc_0 = 0x28,
+ DBG_CLIENT_BLKID_cpc_1 = 0x29,
+ DBG_CLIENT_BLKID_uvdm_0 = 0x2a,
+ DBG_CLIENT_BLKID_uvdm_1 = 0x2b,
+ DBG_CLIENT_BLKID_uvdm_2 = 0x2c,
+ DBG_CLIENT_BLKID_uvdm_3 = 0x2d,
+ DBG_CLIENT_BLKID_cb000 = 0x2e,
+ DBG_CLIENT_BLKID_spim0 = 0x2f,
+ DBG_CLIENT_BLKID_mcc2 = 0x30,
+ DBG_CLIENT_BLKID_ds0 = 0x31,
+ DBG_CLIENT_BLKID_srbm = 0x32,
+ DBG_CLIENT_BLKID_ih = 0x33,
+ DBG_CLIENT_BLKID_sem = 0x34,
+ DBG_CLIENT_BLKID_sdma_0 = 0x35,
+ DBG_CLIENT_BLKID_sdma_1 = 0x36,
+ DBG_CLIENT_BLKID_hdp = 0x37,
+ DBG_CLIENT_BLKID_acp_0 = 0x38,
+ DBG_CLIENT_BLKID_acp_1 = 0x39,
+ DBG_CLIENT_BLKID_cb200 = 0x3a,
+ DBG_CLIENT_BLKID_scf3 = 0x3b,
+ DBG_CLIENT_BLKID_vceb1_0 = 0x3c,
+ DBG_CLIENT_BLKID_vcea1_0 = 0x3d,
+ DBG_CLIENT_BLKID_vcea1_1 = 0x3e,
+ DBG_CLIENT_BLKID_vcea1_2 = 0x3f,
+ DBG_CLIENT_BLKID_vcea1_3 = 0x40,
+ DBG_CLIENT_BLKID_bci3 = 0x41,
+ DBG_CLIENT_BLKID_mcd0 = 0x42,
+ DBG_CLIENT_BLKID_pa11 = 0x43,
+ DBG_CLIENT_BLKID_pa01 = 0x44,
+ DBG_CLIENT_BLKID_cb201 = 0x45,
+ DBG_CLIENT_BLKID_spim2 = 0x46,
+ DBG_CLIENT_BLKID_vgt2 = 0x47,
+ DBG_CLIENT_BLKID_pc2 = 0x48,
+ DBG_CLIENT_BLKID_smu_0 = 0x49,
+ DBG_CLIENT_BLKID_smu_1 = 0x4a,
+ DBG_CLIENT_BLKID_smu_2 = 0x4b,
+ DBG_CLIENT_BLKID_cb1 = 0x4c,
+ DBG_CLIENT_BLKID_ia0 = 0x4d,
+ DBG_CLIENT_BLKID_wd = 0x4e,
+ DBG_CLIENT_BLKID_ia1 = 0x4f,
+ DBG_CLIENT_BLKID_vcec1_0 = 0x50,
+ DBG_CLIENT_BLKID_scf0 = 0x51,
+ DBG_CLIENT_BLKID_vgt1 = 0x52,
+ DBG_CLIENT_BLKID_pc1 = 0x53,
+ DBG_CLIENT_BLKID_cb0 = 0x54,
+ DBG_CLIENT_BLKID_gdc_one_0 = 0x55,
+ DBG_CLIENT_BLKID_gdc_one_1 = 0x56,
+ DBG_CLIENT_BLKID_gdc_one_2 = 0x57,
+ DBG_CLIENT_BLKID_gdc_one_3 = 0x58,
+ DBG_CLIENT_BLKID_gdc_one_4 = 0x59,
+ DBG_CLIENT_BLKID_gdc_one_5 = 0x5a,
+ DBG_CLIENT_BLKID_gdc_one_6 = 0x5b,
+ DBG_CLIENT_BLKID_gdc_one_7 = 0x5c,
+ DBG_CLIENT_BLKID_gdc_one_8 = 0x5d,
+ DBG_CLIENT_BLKID_gdc_one_9 = 0x5e,
+ DBG_CLIENT_BLKID_gdc_one_10 = 0x5f,
+ DBG_CLIENT_BLKID_gdc_one_11 = 0x60,
+ DBG_CLIENT_BLKID_gdc_one_12 = 0x61,
+ DBG_CLIENT_BLKID_gdc_one_13 = 0x62,
+ DBG_CLIENT_BLKID_gdc_one_14 = 0x63,
+ DBG_CLIENT_BLKID_gdc_one_15 = 0x64,
+ DBG_CLIENT_BLKID_gdc_one_16 = 0x65,
+ DBG_CLIENT_BLKID_gdc_one_17 = 0x66,
+ DBG_CLIENT_BLKID_gdc_one_18 = 0x67,
+ DBG_CLIENT_BLKID_gdc_one_19 = 0x68,
+ DBG_CLIENT_BLKID_gdc_one_20 = 0x69,
+ DBG_CLIENT_BLKID_gdc_one_21 = 0x6a,
+ DBG_CLIENT_BLKID_gdc_one_22 = 0x6b,
+ DBG_CLIENT_BLKID_gdc_one_23 = 0x6c,
+ DBG_CLIENT_BLKID_gdc_one_24 = 0x6d,
+ DBG_CLIENT_BLKID_gdc_one_25 = 0x6e,
+ DBG_CLIENT_BLKID_gdc_one_26 = 0x6f,
+ DBG_CLIENT_BLKID_gdc_one_27 = 0x70,
+ DBG_CLIENT_BLKID_gdc_one_28 = 0x71,
+ DBG_CLIENT_BLKID_gdc_one_29 = 0x72,
+ DBG_CLIENT_BLKID_gdc_one_30 = 0x73,
+ DBG_CLIENT_BLKID_gdc_one_31 = 0x74,
+ DBG_CLIENT_BLKID_gdc_one_32 = 0x75,
+ DBG_CLIENT_BLKID_gdc_one_33 = 0x76,
+ DBG_CLIENT_BLKID_gdc_one_34 = 0x77,
+ DBG_CLIENT_BLKID_gdc_one_35 = 0x78,
+ DBG_CLIENT_BLKID_vceb0_0 = 0x79,
+ DBG_CLIENT_BLKID_vgt3 = 0x7a,
+ DBG_CLIENT_BLKID_pc3 = 0x7b,
+ DBG_CLIENT_BLKID_mcd3 = 0x7c,
+ DBG_CLIENT_BLKID_uvdu_0 = 0x7d,
+ DBG_CLIENT_BLKID_uvdu_1 = 0x7e,
+ DBG_CLIENT_BLKID_uvdu_2 = 0x7f,
+ DBG_CLIENT_BLKID_uvdu_3 = 0x80,
+ DBG_CLIENT_BLKID_uvdu_4 = 0x81,
+ DBG_CLIENT_BLKID_uvdu_5 = 0x82,
+ DBG_CLIENT_BLKID_uvdu_6 = 0x83,
+ DBG_CLIENT_BLKID_cb300 = 0x84,
+ DBG_CLIENT_BLKID_mcd1 = 0x85,
+ DBG_CLIENT_BLKID_sx00 = 0x86,
+ DBG_CLIENT_BLKID_uvdc_0 = 0x87,
+ DBG_CLIENT_BLKID_uvdc_1 = 0x88,
+ DBG_CLIENT_BLKID_mcc3 = 0x89,
+ DBG_CLIENT_BLKID_cpg_0 = 0x8a,
+ DBG_CLIENT_BLKID_cpg_1 = 0x8b,
+ DBG_CLIENT_BLKID_gck = 0x8c,
+ DBG_CLIENT_BLKID_mcc1 = 0x8d,
+ DBG_CLIENT_BLKID_cpf_0 = 0x8e,
+ DBG_CLIENT_BLKID_cpf_1 = 0x8f,
+ DBG_CLIENT_BLKID_rlc = 0x90,
+ DBG_CLIENT_BLKID_grbm = 0x91,
+ DBG_CLIENT_BLKID_sammsp = 0x92,
+ DBG_CLIENT_BLKID_dci_pg = 0x93,
+ DBG_CLIENT_BLKID_dci_0 = 0x94,
+ DBG_CLIENT_BLKID_dccg0_0 = 0x95,
+ DBG_CLIENT_BLKID_dccg0_1 = 0x96,
+ DBG_CLIENT_BLKID_dcfe01_0 = 0x97,
+ DBG_CLIENT_BLKID_dcfe02_0 = 0x98,
+ DBG_CLIENT_BLKID_dcfe03_0 = 0x99,
+ DBG_CLIENT_BLKID_dcfe04_0 = 0x9a,
+ DBG_CLIENT_BLKID_dcfe05_0 = 0x9b,
+ DBG_CLIENT_BLKID_dcfe06_0 = 0x9c,
+ DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d,
+} DebugBlockId;
+typedef enum DebugBlockId_OLD {
+ DBG_BLOCK_ID_RESERVED = 0x0,
+ DBG_BLOCK_ID_DBG = 0x1,
+ DBG_BLOCK_ID_VMC = 0x2,
+ DBG_BLOCK_ID_PDMA = 0x3,
+ DBG_BLOCK_ID_CG = 0x4,
+ DBG_BLOCK_ID_SRBM = 0x5,
+ DBG_BLOCK_ID_GRBM = 0x6,
+ DBG_BLOCK_ID_RLC = 0x7,
+ DBG_BLOCK_ID_CSC = 0x8,
+ DBG_BLOCK_ID_SEM = 0x9,
+ DBG_BLOCK_ID_IH = 0xa,
+ DBG_BLOCK_ID_SC = 0xb,
+ DBG_BLOCK_ID_SQ = 0xc,
+ DBG_BLOCK_ID_AVP = 0xd,
+ DBG_BLOCK_ID_GMCON = 0xe,
+ DBG_BLOCK_ID_SMU = 0xf,
+ DBG_BLOCK_ID_DMA0 = 0x10,
+ DBG_BLOCK_ID_DMA1 = 0x11,
+ DBG_BLOCK_ID_SPIM = 0x12,
+ DBG_BLOCK_ID_GDS = 0x13,
+ DBG_BLOCK_ID_SPIS = 0x14,
+ DBG_BLOCK_ID_UNUSED0 = 0x15,
+ DBG_BLOCK_ID_PA0 = 0x16,
+ DBG_BLOCK_ID_PA1 = 0x17,
+ DBG_BLOCK_ID_CP0 = 0x18,
+ DBG_BLOCK_ID_CP1 = 0x19,
+ DBG_BLOCK_ID_CP2 = 0x1a,
+ DBG_BLOCK_ID_UNUSED1 = 0x1b,
+ DBG_BLOCK_ID_UVDU = 0x1c,
+ DBG_BLOCK_ID_UVDM = 0x1d,
+ DBG_BLOCK_ID_VCE = 0x1e,
+ DBG_BLOCK_ID_UNUSED2 = 0x1f,
+ DBG_BLOCK_ID_VGT0 = 0x20,
+ DBG_BLOCK_ID_VGT1 = 0x21,
+ DBG_BLOCK_ID_IA = 0x22,
+ DBG_BLOCK_ID_UNUSED3 = 0x23,
+ DBG_BLOCK_ID_SCT0 = 0x24,
+ DBG_BLOCK_ID_SCT1 = 0x25,
+ DBG_BLOCK_ID_SPM0 = 0x26,
+ DBG_BLOCK_ID_SPM1 = 0x27,
+ DBG_BLOCK_ID_TCAA = 0x28,
+ DBG_BLOCK_ID_TCAB = 0x29,
+ DBG_BLOCK_ID_TCCA = 0x2a,
+ DBG_BLOCK_ID_TCCB = 0x2b,
+ DBG_BLOCK_ID_MCC0 = 0x2c,
+ DBG_BLOCK_ID_MCC1 = 0x2d,
+ DBG_BLOCK_ID_MCC2 = 0x2e,
+ DBG_BLOCK_ID_MCC3 = 0x2f,
+ DBG_BLOCK_ID_SX0 = 0x30,
+ DBG_BLOCK_ID_SX1 = 0x31,
+ DBG_BLOCK_ID_SX2 = 0x32,
+ DBG_BLOCK_ID_SX3 = 0x33,
+ DBG_BLOCK_ID_UNUSED4 = 0x34,
+ DBG_BLOCK_ID_UNUSED5 = 0x35,
+ DBG_BLOCK_ID_UNUSED6 = 0x36,
+ DBG_BLOCK_ID_UNUSED7 = 0x37,
+ DBG_BLOCK_ID_PC0 = 0x38,
+ DBG_BLOCK_ID_PC1 = 0x39,
+ DBG_BLOCK_ID_UNUSED8 = 0x3a,
+ DBG_BLOCK_ID_UNUSED9 = 0x3b,
+ DBG_BLOCK_ID_UNUSED10 = 0x3c,
+ DBG_BLOCK_ID_UNUSED11 = 0x3d,
+ DBG_BLOCK_ID_MCB = 0x3e,
+ DBG_BLOCK_ID_UNUSED12 = 0x3f,
+ DBG_BLOCK_ID_SCB0 = 0x40,
+ DBG_BLOCK_ID_SCB1 = 0x41,
+ DBG_BLOCK_ID_UNUSED13 = 0x42,
+ DBG_BLOCK_ID_UNUSED14 = 0x43,
+ DBG_BLOCK_ID_SCF0 = 0x44,
+ DBG_BLOCK_ID_SCF1 = 0x45,
+ DBG_BLOCK_ID_UNUSED15 = 0x46,
+ DBG_BLOCK_ID_UNUSED16 = 0x47,
+ DBG_BLOCK_ID_BCI0 = 0x48,
+ DBG_BLOCK_ID_BCI1 = 0x49,
+ DBG_BLOCK_ID_BCI2 = 0x4a,
+ DBG_BLOCK_ID_BCI3 = 0x4b,
+ DBG_BLOCK_ID_UNUSED17 = 0x4c,
+ DBG_BLOCK_ID_UNUSED18 = 0x4d,
+ DBG_BLOCK_ID_UNUSED19 = 0x4e,
+ DBG_BLOCK_ID_UNUSED20 = 0x4f,
+ DBG_BLOCK_ID_CB00 = 0x50,
+ DBG_BLOCK_ID_CB01 = 0x51,
+ DBG_BLOCK_ID_CB02 = 0x52,
+ DBG_BLOCK_ID_CB03 = 0x53,
+ DBG_BLOCK_ID_CB04 = 0x54,
+ DBG_BLOCK_ID_UNUSED21 = 0x55,
+ DBG_BLOCK_ID_UNUSED22 = 0x56,
+ DBG_BLOCK_ID_UNUSED23 = 0x57,
+ DBG_BLOCK_ID_CB10 = 0x58,
+ DBG_BLOCK_ID_CB11 = 0x59,
+ DBG_BLOCK_ID_CB12 = 0x5a,
+ DBG_BLOCK_ID_CB13 = 0x5b,
+ DBG_BLOCK_ID_CB14 = 0x5c,
+ DBG_BLOCK_ID_UNUSED24 = 0x5d,
+ DBG_BLOCK_ID_UNUSED25 = 0x5e,
+ DBG_BLOCK_ID_UNUSED26 = 0x5f,
+ DBG_BLOCK_ID_TCP0 = 0x60,
+ DBG_BLOCK_ID_TCP1 = 0x61,
+ DBG_BLOCK_ID_TCP2 = 0x62,
+ DBG_BLOCK_ID_TCP3 = 0x63,
+ DBG_BLOCK_ID_TCP4 = 0x64,
+ DBG_BLOCK_ID_TCP5 = 0x65,
+ DBG_BLOCK_ID_TCP6 = 0x66,
+ DBG_BLOCK_ID_TCP7 = 0x67,
+ DBG_BLOCK_ID_TCP8 = 0x68,
+ DBG_BLOCK_ID_TCP9 = 0x69,
+ DBG_BLOCK_ID_TCP10 = 0x6a,
+ DBG_BLOCK_ID_TCP11 = 0x6b,
+ DBG_BLOCK_ID_TCP12 = 0x6c,
+ DBG_BLOCK_ID_TCP13 = 0x6d,
+ DBG_BLOCK_ID_TCP14 = 0x6e,
+ DBG_BLOCK_ID_TCP15 = 0x6f,
+ DBG_BLOCK_ID_TCP16 = 0x70,
+ DBG_BLOCK_ID_TCP17 = 0x71,
+ DBG_BLOCK_ID_TCP18 = 0x72,
+ DBG_BLOCK_ID_TCP19 = 0x73,
+ DBG_BLOCK_ID_TCP20 = 0x74,
+ DBG_BLOCK_ID_TCP21 = 0x75,
+ DBG_BLOCK_ID_TCP22 = 0x76,
+ DBG_BLOCK_ID_TCP23 = 0x77,
+ DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
+ DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
+ DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
+ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
+ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
+ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
+ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
+ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
+ DBG_BLOCK_ID_DB00 = 0x80,
+ DBG_BLOCK_ID_DB01 = 0x81,
+ DBG_BLOCK_ID_DB02 = 0x82,
+ DBG_BLOCK_ID_DB03 = 0x83,
+ DBG_BLOCK_ID_DB04 = 0x84,
+ DBG_BLOCK_ID_UNUSED27 = 0x85,
+ DBG_BLOCK_ID_UNUSED28 = 0x86,
+ DBG_BLOCK_ID_UNUSED29 = 0x87,
+ DBG_BLOCK_ID_DB10 = 0x88,
+ DBG_BLOCK_ID_DB11 = 0x89,
+ DBG_BLOCK_ID_DB12 = 0x8a,
+ DBG_BLOCK_ID_DB13 = 0x8b,
+ DBG_BLOCK_ID_DB14 = 0x8c,
+ DBG_BLOCK_ID_UNUSED30 = 0x8d,
+ DBG_BLOCK_ID_UNUSED31 = 0x8e,
+ DBG_BLOCK_ID_UNUSED32 = 0x8f,
+ DBG_BLOCK_ID_TCC0 = 0x90,
+ DBG_BLOCK_ID_TCC1 = 0x91,
+ DBG_BLOCK_ID_TCC2 = 0x92,
+ DBG_BLOCK_ID_TCC3 = 0x93,
+ DBG_BLOCK_ID_TCC4 = 0x94,
+ DBG_BLOCK_ID_TCC5 = 0x95,
+ DBG_BLOCK_ID_TCC6 = 0x96,
+ DBG_BLOCK_ID_TCC7 = 0x97,
+ DBG_BLOCK_ID_SPS00 = 0x98,
+ DBG_BLOCK_ID_SPS01 = 0x99,
+ DBG_BLOCK_ID_SPS02 = 0x9a,
+ DBG_BLOCK_ID_SPS10 = 0x9b,
+ DBG_BLOCK_ID_SPS11 = 0x9c,
+ DBG_BLOCK_ID_SPS12 = 0x9d,
+ DBG_BLOCK_ID_UNUSED33 = 0x9e,
+ DBG_BLOCK_ID_UNUSED34 = 0x9f,
+ DBG_BLOCK_ID_TA00 = 0xa0,
+ DBG_BLOCK_ID_TA01 = 0xa1,
+ DBG_BLOCK_ID_TA02 = 0xa2,
+ DBG_BLOCK_ID_TA03 = 0xa3,
+ DBG_BLOCK_ID_TA04 = 0xa4,
+ DBG_BLOCK_ID_TA05 = 0xa5,
+ DBG_BLOCK_ID_TA06 = 0xa6,
+ DBG_BLOCK_ID_TA07 = 0xa7,
+ DBG_BLOCK_ID_TA08 = 0xa8,
+ DBG_BLOCK_ID_TA09 = 0xa9,
+ DBG_BLOCK_ID_TA0A = 0xaa,
+ DBG_BLOCK_ID_TA0B = 0xab,
+ DBG_BLOCK_ID_UNUSED35 = 0xac,
+ DBG_BLOCK_ID_UNUSED36 = 0xad,
+ DBG_BLOCK_ID_UNUSED37 = 0xae,
+ DBG_BLOCK_ID_UNUSED38 = 0xaf,
+ DBG_BLOCK_ID_TA10 = 0xb0,
+ DBG_BLOCK_ID_TA11 = 0xb1,
+ DBG_BLOCK_ID_TA12 = 0xb2,
+ DBG_BLOCK_ID_TA13 = 0xb3,
+ DBG_BLOCK_ID_TA14 = 0xb4,
+ DBG_BLOCK_ID_TA15 = 0xb5,
+ DBG_BLOCK_ID_TA16 = 0xb6,
+ DBG_BLOCK_ID_TA17 = 0xb7,
+ DBG_BLOCK_ID_TA18 = 0xb8,
+ DBG_BLOCK_ID_TA19 = 0xb9,
+ DBG_BLOCK_ID_TA1A = 0xba,
+ DBG_BLOCK_ID_TA1B = 0xbb,
+ DBG_BLOCK_ID_UNUSED39 = 0xbc,
+ DBG_BLOCK_ID_UNUSED40 = 0xbd,
+ DBG_BLOCK_ID_UNUSED41 = 0xbe,
+ DBG_BLOCK_ID_UNUSED42 = 0xbf,
+ DBG_BLOCK_ID_TD00 = 0xc0,
+ DBG_BLOCK_ID_TD01 = 0xc1,
+ DBG_BLOCK_ID_TD02 = 0xc2,
+ DBG_BLOCK_ID_TD03 = 0xc3,
+ DBG_BLOCK_ID_TD04 = 0xc4,
+ DBG_BLOCK_ID_TD05 = 0xc5,
+ DBG_BLOCK_ID_TD06 = 0xc6,
+ DBG_BLOCK_ID_TD07 = 0xc7,
+ DBG_BLOCK_ID_TD08 = 0xc8,
+ DBG_BLOCK_ID_TD09 = 0xc9,
+ DBG_BLOCK_ID_TD0A = 0xca,
+ DBG_BLOCK_ID_TD0B = 0xcb,
+ DBG_BLOCK_ID_UNUSED43 = 0xcc,
+ DBG_BLOCK_ID_UNUSED44 = 0xcd,
+ DBG_BLOCK_ID_UNUSED45 = 0xce,
+ DBG_BLOCK_ID_UNUSED46 = 0xcf,
+ DBG_BLOCK_ID_TD10 = 0xd0,
+ DBG_BLOCK_ID_TD11 = 0xd1,
+ DBG_BLOCK_ID_TD12 = 0xd2,
+ DBG_BLOCK_ID_TD13 = 0xd3,
+ DBG_BLOCK_ID_TD14 = 0xd4,
+ DBG_BLOCK_ID_TD15 = 0xd5,
+ DBG_BLOCK_ID_TD16 = 0xd6,
+ DBG_BLOCK_ID_TD17 = 0xd7,
+ DBG_BLOCK_ID_TD18 = 0xd8,
+ DBG_BLOCK_ID_TD19 = 0xd9,
+ DBG_BLOCK_ID_TD1A = 0xda,
+ DBG_BLOCK_ID_TD1B = 0xdb,
+ DBG_BLOCK_ID_UNUSED47 = 0xdc,
+ DBG_BLOCK_ID_UNUSED48 = 0xdd,
+ DBG_BLOCK_ID_UNUSED49 = 0xde,
+ DBG_BLOCK_ID_UNUSED50 = 0xdf,
+ DBG_BLOCK_ID_MCD0 = 0xe0,
+ DBG_BLOCK_ID_MCD1 = 0xe1,
+ DBG_BLOCK_ID_MCD2 = 0xe2,
+ DBG_BLOCK_ID_MCD3 = 0xe3,
+ DBG_BLOCK_ID_MCD4 = 0xe4,
+ DBG_BLOCK_ID_MCD5 = 0xe5,
+ DBG_BLOCK_ID_UNUSED51 = 0xe6,
+ DBG_BLOCK_ID_UNUSED52 = 0xe7,
+} DebugBlockId_OLD;
+typedef enum DebugBlockId_BY2 {
+ DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
+ DBG_BLOCK_ID_VMC_BY2 = 0x1,
+ DBG_BLOCK_ID_CG_BY2 = 0x2,
+ DBG_BLOCK_ID_GRBM_BY2 = 0x3,
+ DBG_BLOCK_ID_CSC_BY2 = 0x4,
+ DBG_BLOCK_ID_IH_BY2 = 0x5,
+ DBG_BLOCK_ID_SQ_BY2 = 0x6,
+ DBG_BLOCK_ID_GMCON_BY2 = 0x7,
+ DBG_BLOCK_ID_DMA0_BY2 = 0x8,
+ DBG_BLOCK_ID_SPIM_BY2 = 0x9,
+ DBG_BLOCK_ID_SPIS_BY2 = 0xa,
+ DBG_BLOCK_ID_PA0_BY2 = 0xb,
+ DBG_BLOCK_ID_CP0_BY2 = 0xc,
+ DBG_BLOCK_ID_CP2_BY2 = 0xd,
+ DBG_BLOCK_ID_UVDU_BY2 = 0xe,
+ DBG_BLOCK_ID_VCE_BY2 = 0xf,
+ DBG_BLOCK_ID_VGT0_BY2 = 0x10,
+ DBG_BLOCK_ID_IA_BY2 = 0x11,
+ DBG_BLOCK_ID_SCT0_BY2 = 0x12,
+ DBG_BLOCK_ID_SPM0_BY2 = 0x13,
+ DBG_BLOCK_ID_TCAA_BY2 = 0x14,
+ DBG_BLOCK_ID_TCCA_BY2 = 0x15,
+ DBG_BLOCK_ID_MCC0_BY2 = 0x16,
+ DBG_BLOCK_ID_MCC2_BY2 = 0x17,
+ DBG_BLOCK_ID_SX0_BY2 = 0x18,
+ DBG_BLOCK_ID_SX2_BY2 = 0x19,
+ DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
+ DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
+ DBG_BLOCK_ID_PC0_BY2 = 0x1c,
+ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
+ DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
+ DBG_BLOCK_ID_MCB_BY2 = 0x1f,
+ DBG_BLOCK_ID_SCB0_BY2 = 0x20,
+ DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
+ DBG_BLOCK_ID_SCF0_BY2 = 0x22,
+ DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
+ DBG_BLOCK_ID_BCI0_BY2 = 0x24,
+ DBG_BLOCK_ID_BCI2_BY2 = 0x25,
+ DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
+ DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
+ DBG_BLOCK_ID_CB00_BY2 = 0x28,
+ DBG_BLOCK_ID_CB02_BY2 = 0x29,
+ DBG_BLOCK_ID_CB04_BY2 = 0x2a,
+ DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
+ DBG_BLOCK_ID_CB10_BY2 = 0x2c,
+ DBG_BLOCK_ID_CB12_BY2 = 0x2d,
+ DBG_BLOCK_ID_CB14_BY2 = 0x2e,
+ DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
+ DBG_BLOCK_ID_TCP0_BY2 = 0x30,
+ DBG_BLOCK_ID_TCP2_BY2 = 0x31,
+ DBG_BLOCK_ID_TCP4_BY2 = 0x32,
+ DBG_BLOCK_ID_TCP6_BY2 = 0x33,
+ DBG_BLOCK_ID_TCP8_BY2 = 0x34,
+ DBG_BLOCK_ID_TCP10_BY2 = 0x35,
+ DBG_BLOCK_ID_TCP12_BY2 = 0x36,
+ DBG_BLOCK_ID_TCP14_BY2 = 0x37,
+ DBG_BLOCK_ID_TCP16_BY2 = 0x38,
+ DBG_BLOCK_ID_TCP18_BY2 = 0x39,
+ DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
+ DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
+ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
+ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
+ DBG_BLOCK_ID_DB00_BY2 = 0x40,
+ DBG_BLOCK_ID_DB02_BY2 = 0x41,
+ DBG_BLOCK_ID_DB04_BY2 = 0x42,
+ DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
+ DBG_BLOCK_ID_DB10_BY2 = 0x44,
+ DBG_BLOCK_ID_DB12_BY2 = 0x45,
+ DBG_BLOCK_ID_DB14_BY2 = 0x46,
+ DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
+ DBG_BLOCK_ID_TCC0_BY2 = 0x48,
+ DBG_BLOCK_ID_TCC2_BY2 = 0x49,
+ DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
+ DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
+ DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
+ DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
+ DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
+ DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
+ DBG_BLOCK_ID_TA00_BY2 = 0x50,
+ DBG_BLOCK_ID_TA02_BY2 = 0x51,
+ DBG_BLOCK_ID_TA04_BY2 = 0x52,
+ DBG_BLOCK_ID_TA06_BY2 = 0x53,
+ DBG_BLOCK_ID_TA08_BY2 = 0x54,
+ DBG_BLOCK_ID_TA0A_BY2 = 0x55,
+ DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
+ DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
+ DBG_BLOCK_ID_TA10_BY2 = 0x58,
+ DBG_BLOCK_ID_TA12_BY2 = 0x59,
+ DBG_BLOCK_ID_TA14_BY2 = 0x5a,
+ DBG_BLOCK_ID_TA16_BY2 = 0x5b,
+ DBG_BLOCK_ID_TA18_BY2 = 0x5c,
+ DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
+ DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
+ DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
+ DBG_BLOCK_ID_TD00_BY2 = 0x60,
+ DBG_BLOCK_ID_TD02_BY2 = 0x61,
+ DBG_BLOCK_ID_TD04_BY2 = 0x62,
+ DBG_BLOCK_ID_TD06_BY2 = 0x63,
+ DBG_BLOCK_ID_TD08_BY2 = 0x64,
+ DBG_BLOCK_ID_TD0A_BY2 = 0x65,
+ DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
+ DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
+ DBG_BLOCK_ID_TD10_BY2 = 0x68,
+ DBG_BLOCK_ID_TD12_BY2 = 0x69,
+ DBG_BLOCK_ID_TD14_BY2 = 0x6a,
+ DBG_BLOCK_ID_TD16_BY2 = 0x6b,
+ DBG_BLOCK_ID_TD18_BY2 = 0x6c,
+ DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
+ DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
+ DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
+ DBG_BLOCK_ID_MCD0_BY2 = 0x70,
+ DBG_BLOCK_ID_MCD2_BY2 = 0x71,
+ DBG_BLOCK_ID_MCD4_BY2 = 0x72,
+ DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
+} DebugBlockId_BY2;
+typedef enum DebugBlockId_BY4 {
+ DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
+ DBG_BLOCK_ID_CG_BY4 = 0x1,
+ DBG_BLOCK_ID_CSC_BY4 = 0x2,
+ DBG_BLOCK_ID_SQ_BY4 = 0x3,
+ DBG_BLOCK_ID_DMA0_BY4 = 0x4,
+ DBG_BLOCK_ID_SPIS_BY4 = 0x5,
+ DBG_BLOCK_ID_CP0_BY4 = 0x6,
+ DBG_BLOCK_ID_UVDU_BY4 = 0x7,
+ DBG_BLOCK_ID_VGT0_BY4 = 0x8,
+ DBG_BLOCK_ID_SCT0_BY4 = 0x9,
+ DBG_BLOCK_ID_TCAA_BY4 = 0xa,
+ DBG_BLOCK_ID_MCC0_BY4 = 0xb,
+ DBG_BLOCK_ID_SX0_BY4 = 0xc,
+ DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
+ DBG_BLOCK_ID_PC0_BY4 = 0xe,
+ DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
+ DBG_BLOCK_ID_SCB0_BY4 = 0x10,
+ DBG_BLOCK_ID_SCF0_BY4 = 0x11,
+ DBG_BLOCK_ID_BCI0_BY4 = 0x12,
+ DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
+ DBG_BLOCK_ID_CB00_BY4 = 0x14,
+ DBG_BLOCK_ID_CB04_BY4 = 0x15,
+ DBG_BLOCK_ID_CB10_BY4 = 0x16,
+ DBG_BLOCK_ID_CB14_BY4 = 0x17,
+ DBG_BLOCK_ID_TCP0_BY4 = 0x18,
+ DBG_BLOCK_ID_TCP4_BY4 = 0x19,
+ DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
+ DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
+ DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
+ DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
+ DBG_BLOCK_ID_DB_BY4 = 0x20,
+ DBG_BLOCK_ID_DB04_BY4 = 0x21,
+ DBG_BLOCK_ID_DB10_BY4 = 0x22,
+ DBG_BLOCK_ID_DB14_BY4 = 0x23,
+ DBG_BLOCK_ID_TCC0_BY4 = 0x24,
+ DBG_BLOCK_ID_TCC4_BY4 = 0x25,
+ DBG_BLOCK_ID_SPS00_BY4 = 0x26,
+ DBG_BLOCK_ID_SPS11_BY4 = 0x27,
+ DBG_BLOCK_ID_TA00_BY4 = 0x28,
+ DBG_BLOCK_ID_TA04_BY4 = 0x29,
+ DBG_BLOCK_ID_TA08_BY4 = 0x2a,
+ DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
+ DBG_BLOCK_ID_TA10_BY4 = 0x2c,
+ DBG_BLOCK_ID_TA14_BY4 = 0x2d,
+ DBG_BLOCK_ID_TA18_BY4 = 0x2e,
+ DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
+ DBG_BLOCK_ID_TD00_BY4 = 0x30,
+ DBG_BLOCK_ID_TD04_BY4 = 0x31,
+ DBG_BLOCK_ID_TD08_BY4 = 0x32,
+ DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
+ DBG_BLOCK_ID_TD10_BY4 = 0x34,
+ DBG_BLOCK_ID_TD14_BY4 = 0x35,
+ DBG_BLOCK_ID_TD18_BY4 = 0x36,
+ DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
+ DBG_BLOCK_ID_MCD0_BY4 = 0x38,
+ DBG_BLOCK_ID_MCD4_BY4 = 0x39,
+} DebugBlockId_BY4;
+typedef enum DebugBlockId_BY8 {
+ DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
+ DBG_BLOCK_ID_CSC_BY8 = 0x1,
+ DBG_BLOCK_ID_DMA0_BY8 = 0x2,
+ DBG_BLOCK_ID_CP0_BY8 = 0x3,
+ DBG_BLOCK_ID_VGT0_BY8 = 0x4,
+ DBG_BLOCK_ID_TCAA_BY8 = 0x5,
+ DBG_BLOCK_ID_SX0_BY8 = 0x6,
+ DBG_BLOCK_ID_PC0_BY8 = 0x7,
+ DBG_BLOCK_ID_SCB0_BY8 = 0x8,
+ DBG_BLOCK_ID_BCI0_BY8 = 0x9,
+ DBG_BLOCK_ID_CB00_BY8 = 0xa,
+ DBG_BLOCK_ID_CB10_BY8 = 0xb,
+ DBG_BLOCK_ID_TCP0_BY8 = 0xc,
+ DBG_BLOCK_ID_TCP8_BY8 = 0xd,
+ DBG_BLOCK_ID_TCP16_BY8 = 0xe,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
+ DBG_BLOCK_ID_DB00_BY8 = 0x10,
+ DBG_BLOCK_ID_DB10_BY8 = 0x11,
+ DBG_BLOCK_ID_TCC0_BY8 = 0x12,
+ DBG_BLOCK_ID_SPS00_BY8 = 0x13,
+ DBG_BLOCK_ID_TA00_BY8 = 0x14,
+ DBG_BLOCK_ID_TA08_BY8 = 0x15,
+ DBG_BLOCK_ID_TA10_BY8 = 0x16,
+ DBG_BLOCK_ID_TA18_BY8 = 0x17,
+ DBG_BLOCK_ID_TD00_BY8 = 0x18,
+ DBG_BLOCK_ID_TD08_BY8 = 0x19,
+ DBG_BLOCK_ID_TD10_BY8 = 0x1a,
+ DBG_BLOCK_ID_TD18_BY8 = 0x1b,
+ DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
+} DebugBlockId_BY8;
+typedef enum DebugBlockId_BY16 {
+ DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
+ DBG_BLOCK_ID_DMA0_BY16 = 0x1,
+ DBG_BLOCK_ID_VGT0_BY16 = 0x2,
+ DBG_BLOCK_ID_SX0_BY16 = 0x3,
+ DBG_BLOCK_ID_SCB0_BY16 = 0x4,
+ DBG_BLOCK_ID_CB00_BY16 = 0x5,
+ DBG_BLOCK_ID_TCP0_BY16 = 0x6,
+ DBG_BLOCK_ID_TCP16_BY16 = 0x7,
+ DBG_BLOCK_ID_DB00_BY16 = 0x8,
+ DBG_BLOCK_ID_TCC0_BY16 = 0x9,
+ DBG_BLOCK_ID_TA00_BY16 = 0xa,
+ DBG_BLOCK_ID_TA10_BY16 = 0xb,
+ DBG_BLOCK_ID_TD00_BY16 = 0xc,
+ DBG_BLOCK_ID_TD10_BY16 = 0xd,
+ DBG_BLOCK_ID_MCD0_BY16 = 0xe,
+} DebugBlockId_BY16;
+typedef enum ColorTransform {
+ DCC_CT_AUTO = 0x0,
+ DCC_CT_NONE = 0x1,
+ ABGR_TO_A_BG_G_RB = 0x2,
+ BGRA_TO_BG_G_RB_A = 0x3,
+} ColorTransform;
+typedef enum CompareRef {
+ REF_NEVER = 0x0,
+ REF_LESS = 0x1,
+ REF_EQUAL = 0x2,
+ REF_LEQUAL = 0x3,
+ REF_GREATER = 0x4,
+ REF_NOTEQUAL = 0x5,
+ REF_GEQUAL = 0x6,
+ REF_ALWAYS = 0x7,
+} CompareRef;
+typedef enum ReadSize {
+ READ_256_BITS = 0x0,
+ READ_512_BITS = 0x1,
+} ReadSize;
+typedef enum DepthFormat {
+ DEPTH_INVALID = 0x0,
+ DEPTH_16 = 0x1,
+ DEPTH_X8_24 = 0x2,
+ DEPTH_8_24 = 0x3,
+ DEPTH_X8_24_FLOAT = 0x4,
+ DEPTH_8_24_FLOAT = 0x5,
+ DEPTH_32_FLOAT = 0x6,
+ DEPTH_X24_8_32_FLOAT = 0x7,
+} DepthFormat;
+typedef enum ZFormat {
+ Z_INVALID = 0x0,
+ Z_16 = 0x1,
+ Z_24 = 0x2,
+ Z_32_FLOAT = 0x3,
+} ZFormat;
+typedef enum StencilFormat {
+ STENCIL_INVALID = 0x0,
+ STENCIL_8 = 0x1,
+} StencilFormat;
+typedef enum CmaskMode {
+ CMASK_CLEAR_NONE = 0x0,
+ CMASK_CLEAR_ONE = 0x1,
+ CMASK_CLEAR_ALL = 0x2,
+ CMASK_ANY_EXPANDED = 0x3,
+ CMASK_ALPHA0_FRAG1 = 0x4,
+ CMASK_ALPHA0_FRAG2 = 0x5,
+ CMASK_ALPHA0_FRAG4 = 0x6,
+ CMASK_ALPHA0_FRAGS = 0x7,
+ CMASK_ALPHA1_FRAG1 = 0x8,
+ CMASK_ALPHA1_FRAG2 = 0x9,
+ CMASK_ALPHA1_FRAG4 = 0xa,
+ CMASK_ALPHA1_FRAGS = 0xb,
+ CMASK_ALPHAX_FRAG1 = 0xc,
+ CMASK_ALPHAX_FRAG2 = 0xd,
+ CMASK_ALPHAX_FRAG4 = 0xe,
+ CMASK_ALPHAX_FRAGS = 0xf,
+} CmaskMode;
+typedef enum QuadExportFormat {
+ EXPORT_UNUSED = 0x0,
+ EXPORT_32_R = 0x1,
+ EXPORT_32_GR = 0x2,
+ EXPORT_32_AR = 0x3,
+ EXPORT_FP16_ABGR = 0x4,
+ EXPORT_UNSIGNED16_ABGR = 0x5,
+ EXPORT_SIGNED16_ABGR = 0x6,
+ EXPORT_32_ABGR = 0x7,
+} QuadExportFormat;
+typedef enum QuadExportFormatOld {
+ EXPORT_4P_32BPC_ABGR = 0x0,
+ EXPORT_4P_16BPC_ABGR = 0x1,
+ EXPORT_4P_32BPC_GR = 0x2,
+ EXPORT_4P_32BPC_AR = 0x3,
+ EXPORT_2P_32BPC_ABGR = 0x4,
+ EXPORT_8P_32BPC_R = 0x5,
+} QuadExportFormatOld;
+typedef enum ColorFormat {
+ COLOR_INVALID = 0x0,
+ COLOR_8 = 0x1,
+ COLOR_16 = 0x2,
+ COLOR_8_8 = 0x3,
+ COLOR_32 = 0x4,
+ COLOR_16_16 = 0x5,
+ COLOR_10_11_11 = 0x6,
+ COLOR_11_11_10 = 0x7,
+ COLOR_10_10_10_2 = 0x8,
+ COLOR_2_10_10_10 = 0x9,
+ COLOR_8_8_8_8 = 0xa,
+ COLOR_32_32 = 0xb,
+ COLOR_16_16_16_16 = 0xc,
+ COLOR_RESERVED_13 = 0xd,
+ COLOR_32_32_32_32 = 0xe,
+ COLOR_RESERVED_15 = 0xf,
+ COLOR_5_6_5 = 0x10,
+ COLOR_1_5_5_5 = 0x11,
+ COLOR_5_5_5_1 = 0x12,
+ COLOR_4_4_4_4 = 0x13,
+ COLOR_8_24 = 0x14,
+ COLOR_24_8 = 0x15,
+ COLOR_X24_8_32_FLOAT = 0x16,
+ COLOR_RESERVED_23 = 0x17,
+} ColorFormat;
+typedef enum SurfaceFormat {
+ FMT_INVALID = 0x0,
+ FMT_8 = 0x1,
+ FMT_16 = 0x2,
+ FMT_8_8 = 0x3,
+ FMT_32 = 0x4,
+ FMT_16_16 = 0x5,
+ FMT_10_11_11 = 0x6,
+ FMT_11_11_10 = 0x7,
+ FMT_10_10_10_2 = 0x8,
+ FMT_2_10_10_10 = 0x9,
+ FMT_8_8_8_8 = 0xa,
+ FMT_32_32 = 0xb,
+ FMT_16_16_16_16 = 0xc,
+ FMT_32_32_32 = 0xd,
+ FMT_32_32_32_32 = 0xe,
+ FMT_RESERVED_4 = 0xf,
+ FMT_5_6_5 = 0x10,
+ FMT_1_5_5_5 = 0x11,
+ FMT_5_5_5_1 = 0x12,
+ FMT_4_4_4_4 = 0x13,
+ FMT_8_24 = 0x14,
+ FMT_24_8 = 0x15,
+ FMT_X24_8_32_FLOAT = 0x16,
+ FMT_RESERVED_33 = 0x17,
+ FMT_11_11_10_FLOAT = 0x18,
+ FMT_16_FLOAT = 0x19,
+ FMT_32_FLOAT = 0x1a,
+ FMT_16_16_FLOAT = 0x1b,
+ FMT_8_24_FLOAT = 0x1c,
+ FMT_24_8_FLOAT = 0x1d,
+ FMT_32_32_FLOAT = 0x1e,
+ FMT_10_11_11_FLOAT = 0x1f,
+ FMT_16_16_16_16_FLOAT = 0x20,
+ FMT_3_3_2 = 0x21,
+ FMT_6_5_5 = 0x22,
+ FMT_32_32_32_32_FLOAT = 0x23,
+ FMT_RESERVED_36 = 0x24,
+ FMT_1 = 0x25,
+ FMT_1_REVERSED = 0x26,
+ FMT_GB_GR = 0x27,
+ FMT_BG_RG = 0x28,
+ FMT_32_AS_8 = 0x29,
+ FMT_32_AS_8_8 = 0x2a,
+ FMT_5_9_9_9_SHAREDEXP = 0x2b,
+ FMT_8_8_8 = 0x2c,
+ FMT_16_16_16 = 0x2d,
+ FMT_16_16_16_FLOAT = 0x2e,
+ FMT_4_4 = 0x2f,
+ FMT_32_32_32_FLOAT = 0x30,
+ FMT_BC1 = 0x31,
+ FMT_BC2 = 0x32,
+ FMT_BC3 = 0x33,
+ FMT_BC4 = 0x34,
+ FMT_BC5 = 0x35,
+ FMT_BC6 = 0x36,
+ FMT_BC7 = 0x37,
+ FMT_32_AS_32_32_32_32 = 0x38,
+ FMT_APC3 = 0x39,
+ FMT_APC4 = 0x3a,
+ FMT_APC5 = 0x3b,
+ FMT_APC6 = 0x3c,
+ FMT_APC7 = 0x3d,
+ FMT_CTX1 = 0x3e,
+ FMT_RESERVED_63 = 0x3f,
+} SurfaceFormat;
+typedef enum BUF_DATA_FORMAT {
+ BUF_DATA_FORMAT_INVALID = 0x0,
+ BUF_DATA_FORMAT_8 = 0x1,
+ BUF_DATA_FORMAT_16 = 0x2,
+ BUF_DATA_FORMAT_8_8 = 0x3,
+ BUF_DATA_FORMAT_32 = 0x4,
+ BUF_DATA_FORMAT_16_16 = 0x5,
+ BUF_DATA_FORMAT_10_11_11 = 0x6,
+ BUF_DATA_FORMAT_11_11_10 = 0x7,
+ BUF_DATA_FORMAT_10_10_10_2 = 0x8,
+ BUF_DATA_FORMAT_2_10_10_10 = 0x9,
+ BUF_DATA_FORMAT_8_8_8_8 = 0xa,
+ BUF_DATA_FORMAT_32_32 = 0xb,
+ BUF_DATA_FORMAT_16_16_16_16 = 0xc,
+ BUF_DATA_FORMAT_32_32_32 = 0xd,
+ BUF_DATA_FORMAT_32_32_32_32 = 0xe,
+ BUF_DATA_FORMAT_RESERVED_15 = 0xf,
+} BUF_DATA_FORMAT;
+typedef enum IMG_DATA_FORMAT {
+ IMG_DATA_FORMAT_INVALID = 0x0,
+ IMG_DATA_FORMAT_8 = 0x1,
+ IMG_DATA_FORMAT_16 = 0x2,
+ IMG_DATA_FORMAT_8_8 = 0x3,
+ IMG_DATA_FORMAT_32 = 0x4,
+ IMG_DATA_FORMAT_16_16 = 0x5,
+ IMG_DATA_FORMAT_10_11_11 = 0x6,
+ IMG_DATA_FORMAT_11_11_10 = 0x7,
+ IMG_DATA_FORMAT_10_10_10_2 = 0x8,
+ IMG_DATA_FORMAT_2_10_10_10 = 0x9,
+ IMG_DATA_FORMAT_8_8_8_8 = 0xa,
+ IMG_DATA_FORMAT_32_32 = 0xb,
+ IMG_DATA_FORMAT_16_16_16_16 = 0xc,
+ IMG_DATA_FORMAT_32_32_32 = 0xd,
+ IMG_DATA_FORMAT_32_32_32_32 = 0xe,
+ IMG_DATA_FORMAT_RESERVED_15 = 0xf,
+ IMG_DATA_FORMAT_5_6_5 = 0x10,
+ IMG_DATA_FORMAT_1_5_5_5 = 0x11,
+ IMG_DATA_FORMAT_5_5_5_1 = 0x12,
+ IMG_DATA_FORMAT_4_4_4_4 = 0x13,
+ IMG_DATA_FORMAT_8_24 = 0x14,
+ IMG_DATA_FORMAT_24_8 = 0x15,
+ IMG_DATA_FORMAT_X24_8_32 = 0x16,
+ IMG_DATA_FORMAT_RESERVED_23 = 0x17,
+ IMG_DATA_FORMAT_RESERVED_24 = 0x18,
+ IMG_DATA_FORMAT_RESERVED_25 = 0x19,
+ IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
+ IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
+ IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
+ IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
+ IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
+ IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
+ IMG_DATA_FORMAT_GB_GR = 0x20,
+ IMG_DATA_FORMAT_BG_RG = 0x21,
+ IMG_DATA_FORMAT_5_9_9_9 = 0x22,
+ IMG_DATA_FORMAT_BC1 = 0x23,
+ IMG_DATA_FORMAT_BC2 = 0x24,
+ IMG_DATA_FORMAT_BC3 = 0x25,
+ IMG_DATA_FORMAT_BC4 = 0x26,
+ IMG_DATA_FORMAT_BC5 = 0x27,
+ IMG_DATA_FORMAT_BC6 = 0x28,
+ IMG_DATA_FORMAT_BC7 = 0x29,
+ IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
+ IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
+ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
+ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
+ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
+ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
+ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
+ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
+ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
+ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
+ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
+ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
+ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
+ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
+ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
+ IMG_DATA_FORMAT_4_4 = 0x39,
+ IMG_DATA_FORMAT_6_5_5 = 0x3a,
+ IMG_DATA_FORMAT_1 = 0x3b,
+ IMG_DATA_FORMAT_1_REVERSED = 0x3c,
+ IMG_DATA_FORMAT_32_AS_8 = 0x3d,
+ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
+ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
+} IMG_DATA_FORMAT;
+typedef enum BUF_NUM_FORMAT {
+ BUF_NUM_FORMAT_UNORM = 0x0,
+ BUF_NUM_FORMAT_SNORM = 0x1,
+ BUF_NUM_FORMAT_USCALED = 0x2,
+ BUF_NUM_FORMAT_SSCALED = 0x3,
+ BUF_NUM_FORMAT_UINT = 0x4,
+ BUF_NUM_FORMAT_SINT = 0x5,
+ BUF_NUM_FORMAT_RESERVED_6 = 0x6,
+ BUF_NUM_FORMAT_FLOAT = 0x7,
+} BUF_NUM_FORMAT;
+typedef enum IMG_NUM_FORMAT {
+ IMG_NUM_FORMAT_UNORM = 0x0,
+ IMG_NUM_FORMAT_SNORM = 0x1,
+ IMG_NUM_FORMAT_USCALED = 0x2,
+ IMG_NUM_FORMAT_SSCALED = 0x3,
+ IMG_NUM_FORMAT_UINT = 0x4,
+ IMG_NUM_FORMAT_SINT = 0x5,
+ IMG_NUM_FORMAT_RESERVED_6 = 0x6,
+ IMG_NUM_FORMAT_FLOAT = 0x7,
+ IMG_NUM_FORMAT_RESERVED_8 = 0x8,
+ IMG_NUM_FORMAT_SRGB = 0x9,
+ IMG_NUM_FORMAT_RESERVED_10 = 0xa,
+ IMG_NUM_FORMAT_RESERVED_11 = 0xb,
+ IMG_NUM_FORMAT_RESERVED_12 = 0xc,
+ IMG_NUM_FORMAT_RESERVED_13 = 0xd,
+ IMG_NUM_FORMAT_RESERVED_14 = 0xe,
+ IMG_NUM_FORMAT_RESERVED_15 = 0xf,
+} IMG_NUM_FORMAT;
+typedef enum TileType {
+ ARRAY_COLOR_TILE = 0x0,
+ ARRAY_DEPTH_TILE = 0x1,
+} TileType;
+typedef enum NonDispTilingOrder {
+ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
+ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
+} NonDispTilingOrder;
+typedef enum MicroTileMode {
+ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
+ ADDR_SURF_THIN_MICRO_TILING = 0x1,
+ ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
+ ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
+ ADDR_SURF_THICK_MICRO_TILING = 0x4,
+} MicroTileMode;
+typedef enum TileSplit {
+ ADDR_SURF_TILE_SPLIT_64B = 0x0,
+ ADDR_SURF_TILE_SPLIT_128B = 0x1,
+ ADDR_SURF_TILE_SPLIT_256B = 0x2,
+ ADDR_SURF_TILE_SPLIT_512B = 0x3,
+ ADDR_SURF_TILE_SPLIT_1KB = 0x4,
+ ADDR_SURF_TILE_SPLIT_2KB = 0x5,
+ ADDR_SURF_TILE_SPLIT_4KB = 0x6,
+} TileSplit;
+typedef enum SampleSplit {
+ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
+ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
+ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
+ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
+} SampleSplit;
+typedef enum PipeConfig {
+ ADDR_SURF_P2 = 0x0,
+ ADDR_SURF_P2_RESERVED0 = 0x1,
+ ADDR_SURF_P2_RESERVED1 = 0x2,
+ ADDR_SURF_P2_RESERVED2 = 0x3,
+ ADDR_SURF_P4_8x16 = 0x4,
+ ADDR_SURF_P4_16x16 = 0x5,
+ ADDR_SURF_P4_16x32 = 0x6,
+ ADDR_SURF_P4_32x32 = 0x7,
+ ADDR_SURF_P8_16x16_8x16 = 0x8,
+ ADDR_SURF_P8_16x32_8x16 = 0x9,
+ ADDR_SURF_P8_32x32_8x16 = 0xa,
+ ADDR_SURF_P8_16x32_16x16 = 0xb,
+ ADDR_SURF_P8_32x32_16x16 = 0xc,
+ ADDR_SURF_P8_32x32_16x32 = 0xd,
+ ADDR_SURF_P8_32x64_32x32 = 0xe,
+ ADDR_SURF_P8_RESERVED0 = 0xf,
+ ADDR_SURF_P16_32x32_8x16 = 0x10,
+ ADDR_SURF_P16_32x32_16x16 = 0x11,
+} PipeConfig;
+typedef enum NumBanks {
+ ADDR_SURF_2_BANK = 0x0,
+ ADDR_SURF_4_BANK = 0x1,
+ ADDR_SURF_8_BANK = 0x2,
+ ADDR_SURF_16_BANK = 0x3,
+} NumBanks;
+typedef enum BankWidth {
+ ADDR_SURF_BANK_WIDTH_1 = 0x0,
+ ADDR_SURF_BANK_WIDTH_2 = 0x1,
+ ADDR_SURF_BANK_WIDTH_4 = 0x2,
+ ADDR_SURF_BANK_WIDTH_8 = 0x3,
+} BankWidth;
+typedef enum BankHeight {
+ ADDR_SURF_BANK_HEIGHT_1 = 0x0,
+ ADDR_SURF_BANK_HEIGHT_2 = 0x1,
+ ADDR_SURF_BANK_HEIGHT_4 = 0x2,
+ ADDR_SURF_BANK_HEIGHT_8 = 0x3,
+} BankHeight;
+typedef enum BankWidthHeight {
+ ADDR_SURF_BANK_WH_1 = 0x0,
+ ADDR_SURF_BANK_WH_2 = 0x1,
+ ADDR_SURF_BANK_WH_4 = 0x2,
+ ADDR_SURF_BANK_WH_8 = 0x3,
+} BankWidthHeight;
+typedef enum MacroTileAspect {
+ ADDR_SURF_MACRO_ASPECT_1 = 0x0,
+ ADDR_SURF_MACRO_ASPECT_2 = 0x1,
+ ADDR_SURF_MACRO_ASPECT_4 = 0x2,
+ ADDR_SURF_MACRO_ASPECT_8 = 0x3,
+} MacroTileAspect;
+typedef enum GATCL1RequestType {
+ GATCL1_TYPE_NORMAL = 0x0,
+ GATCL1_TYPE_SHOOTDOWN = 0x1,
+ GATCL1_TYPE_BYPASS = 0x2,
+} GATCL1RequestType;
+typedef enum TCC_CACHE_POLICIES {
+ TCC_CACHE_POLICY_LRU = 0x0,
+ TCC_CACHE_POLICY_STREAM = 0x1,
+} TCC_CACHE_POLICIES;
+typedef enum MTYPE {
+ MTYPE_NC_NV = 0x0,
+ MTYPE_NC = 0x1,
+ MTYPE_CC = 0x2,
+ MTYPE_UC = 0x3,
+} MTYPE;
+typedef enum PERFMON_COUNTER_MODE {
+ PERFMON_COUNTER_MODE_ACCUM = 0x0,
+ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
+ PERFMON_COUNTER_MODE_MAX = 0x2,
+ PERFMON_COUNTER_MODE_DIRTY = 0x3,
+ PERFMON_COUNTER_MODE_SAMPLE = 0x4,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
+ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
+ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
+ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
+ PERFMON_COUNTER_MODE_RESERVED = 0xf,
+} PERFMON_COUNTER_MODE;
+typedef enum PERFMON_SPM_MODE {
+ PERFMON_SPM_MODE_OFF = 0x0,
+ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
+ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
+ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
+ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
+ PERFMON_SPM_MODE_RESERVED_5 = 0x5,
+ PERFMON_SPM_MODE_RESERVED_6 = 0x6,
+ PERFMON_SPM_MODE_RESERVED_7 = 0x7,
+ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
+ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
+ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
+} PERFMON_SPM_MODE;
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0x0,
+ ARRAY_TILED = 0x1,
+} SurfaceTiling;
+typedef enum SurfaceArray {
+ ARRAY_1D = 0x0,
+ ARRAY_2D = 0x1,
+ ARRAY_3D = 0x2,
+ ARRAY_3D_SLICE = 0x3,
+} SurfaceArray;
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0x0,
+ ARRAY_2D_COLOR = 0x1,
+ ARRAY_3D_SLICE_COLOR = 0x3,
+} ColorArray;
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0x0,
+ ARRAY_2D_DEPTH = 0x1,
+} DepthArray;
+typedef enum ENUM_NUM_SIMD_PER_CU {
+ NUM_SIMD_PER_CU = 0x4,
+} ENUM_NUM_SIMD_PER_CU;
+typedef enum MEM_PWR_FORCE_CTRL {
+ NO_FORCE_REQUEST = 0x0,
+ FORCE_LIGHT_SLEEP_REQUEST = 0x1,
+ FORCE_DEEP_SLEEP_REQUEST = 0x2,
+ FORCE_SHUT_DOWN_REQUEST = 0x3,
+} MEM_PWR_FORCE_CTRL;
+typedef enum MEM_PWR_FORCE_CTRL2 {
+ NO_FORCE_REQ = 0x0,
+ FORCE_LIGHT_SLEEP_REQ = 0x1,
+} MEM_PWR_FORCE_CTRL2;
+typedef enum MEM_PWR_DIS_CTRL {
+ ENABLE_MEM_PWR_CTRL = 0x0,
+ DISABLE_MEM_PWR_CTRL = 0x1,
+} MEM_PWR_DIS_CTRL;
+typedef enum MEM_PWR_SEL_CTRL {
+ DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
+ DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
+ DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
+} MEM_PWR_SEL_CTRL;
+typedef enum MEM_PWR_SEL_CTRL2 {
+ DYNAMIC_DEEP_SLEEP_EN = 0x0,
+ DYNAMIC_LIGHT_SLEEP_EN = 0x1,
+} MEM_PWR_SEL_CTRL2;
+
+#endif /* GMC_8_1_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h
new file mode 100644
index 000000000000..7d3963f36a6b
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h
@@ -0,0 +1,15682 @@
+/*
+ * GMC_8_1 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GMC_8_1_SH_MASK_H
+#define GMC_8_1_SH_MASK_H
+
+#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
+#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
+#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
+#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
+#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
+#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
+#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
+#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
+#define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
+#define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
+#define MC_CONFIG__MCDT_WR_ENABLE_MASK 0x20
+#define MC_CONFIG__MCDT_WR_ENABLE__SHIFT 0x5
+#define MC_CONFIG__MCDU_WR_ENABLE_MASK 0x40
+#define MC_CONFIG__MCDU_WR_ENABLE__SHIFT 0x6
+#define MC_CONFIG__MCDV_WR_ENABLE_MASK 0x80
+#define MC_CONFIG__MCDV_WR_ENABLE__SHIFT 0x7
+#define MC_CONFIG__MC_RD_ENABLE_MASK 0x700
+#define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x8
+#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000
+#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x1f
+#define MC_ARB_ATOMIC__TC_GRP_MASK 0x7
+#define MC_ARB_ATOMIC__TC_GRP__SHIFT 0x0
+#define MC_ARB_ATOMIC__TC_GRP_EN_MASK 0x8
+#define MC_ARB_ATOMIC__TC_GRP_EN__SHIFT 0x3
+#define MC_ARB_ATOMIC__SDMA_GRP_MASK 0x70
+#define MC_ARB_ATOMIC__SDMA_GRP__SHIFT 0x4
+#define MC_ARB_ATOMIC__SDMA_GRP_EN_MASK 0x80
+#define MC_ARB_ATOMIC__SDMA_GRP_EN__SHIFT 0x7
+#define MC_ARB_ATOMIC__OUTSTANDING_MASK 0xff00
+#define MC_ARB_ATOMIC__OUTSTANDING__SHIFT 0x8
+#define MC_ARB_ATOMIC__ATOMIC_RTN_GRP_MASK 0xff0000
+#define MC_ARB_ATOMIC__ATOMIC_RTN_GRP__SHIFT 0x10
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0_MASK 0x1
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0__SHIFT 0x0
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1_MASK 0x2
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1__SHIFT 0x1
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2_MASK 0x4
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2__SHIFT 0x2
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3__SHIFT 0x3
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4__SHIFT 0x4
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5_MASK 0x20
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5__SHIFT 0x5
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6_MASK 0x40
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6__SHIFT 0x6
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7_MASK 0x80
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7__SHIFT 0x7
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0_MASK 0x100
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1_MASK 0x200
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1__SHIFT 0x9
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2_MASK 0x400
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x800
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3__SHIFT 0xb
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4_MASK 0x1000
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4__SHIFT 0xc
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5_MASK 0x2000
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5__SHIFT 0xd
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6_MASK 0x4000
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT 0xe
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7_MASK 0x8000
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7__SHIFT 0xf
+#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD_MASK 0x70000
+#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10
+#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR_MASK 0x380000
+#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR__SHIFT 0x13
+#define MC_ARB_AGE_CNTL__TIMER_STALL_RD_MASK 0x400000
+#define MC_ARB_AGE_CNTL__TIMER_STALL_RD__SHIFT 0x16
+#define MC_ARB_AGE_CNTL__TIMER_STALL_WR_MASK 0x800000
+#define MC_ARB_AGE_CNTL__TIMER_STALL_WR__SHIFT 0x17
+#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD_MASK 0x1000000
+#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD__SHIFT 0x18
+#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR_MASK 0x2000000
+#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR__SHIFT 0x19
+#define MC_ARB_RET_CREDITS2__ACP_WR_MASK 0xff
+#define MC_ARB_RET_CREDITS2__ACP_WR__SHIFT 0x0
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD_MASK 0x100
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT 0x8
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR_MASK 0x200
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR__SHIFT 0x9
+#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG_MASK 0x400
+#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG__SHIFT 0xa
+#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG_MASK 0x800
+#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG__SHIFT 0xb
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD_MASK 0x1000
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD__SHIFT 0xc
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR_MASK 0x2000
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR__SHIFT 0xd
+#define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD_MASK 0x4000
+#define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD__SHIFT 0xe
+#define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR_MASK 0x8000
+#define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR__SHIFT 0xf
+#define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED_MASK 0xff0000
+#define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED__SHIFT 0x10
+#define MC_ARB_FED_CNTL__MODE_MASK 0x3
+#define MC_ARB_FED_CNTL__MODE__SHIFT 0x0
+#define MC_ARB_FED_CNTL__WR_ERR_MASK 0xc
+#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x2
+#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10
+#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x4
+#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK_MASK 0x20
+#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK__SHIFT 0x5
+#define MC_ARB_FED_CNTL__USE_LEGACY_NACK_MASK 0x40
+#define MC_ARB_FED_CNTL__USE_LEGACY_NACK__SHIFT 0x6
+#define MC_ARB_FED_CNTL__DEBUG_RSV_MASK 0xffffff80
+#define MC_ARB_FED_CNTL__DEBUG_RSV__SHIFT 0x7
+#define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x1
+#define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x0
+#define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x2
+#define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x1
+#define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x4
+#define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x2
+#define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8
+#define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x3
+#define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10
+#define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x4
+#define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x20
+#define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x5
+#define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x40
+#define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x6
+#define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x80
+#define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x7
+#define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x100
+#define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8
+#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x200
+#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x9
+#define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x400
+#define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa
+#define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x800
+#define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0xb
+#define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x1000
+#define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0xc
+#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x2000
+#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0xd
+#define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x4000
+#define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0xe
+#define MC_ARB_GECC2_STATUS__RSVD3_MASK 0x8000
+#define MC_ARB_GECC2_STATUS__RSVD3__SHIFT 0xf
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0_MASK 0x10000
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0_MASK 0x20000
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0__SHIFT 0x11
+#define MC_ARB_GECC2_STATUS__RSVD4_MASK 0xc0000
+#define MC_ARB_GECC2_STATUS__RSVD4__SHIFT 0x12
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1_MASK 0x100000
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1__SHIFT 0x14
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1_MASK 0x200000
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1__SHIFT 0x15
+#define MC_ARB_GECC2_STATUS__RSVD5_MASK 0xc00000
+#define MC_ARB_GECC2_STATUS__RSVD5__SHIFT 0x16
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0_MASK 0x1000000
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0__SHIFT 0x18
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0_MASK 0x2000000
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0__SHIFT 0x19
+#define MC_ARB_GECC2_STATUS__RSVD6_MASK 0xc000000
+#define MC_ARB_GECC2_STATUS__RSVD6__SHIFT 0x1a
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1_MASK 0x10000000
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1__SHIFT 0x1c
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1_MASK 0x20000000
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d
+#define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0xf
+#define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x0
+#define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10
+#define MC_ARB_GECC2_MISC__COL10_HACK__SHIFT 0x4
+#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY_MASK 0x20
+#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY__SHIFT 0x5
+#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY_MASK 0x40
+#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY__SHIFT 0x6
+#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL_MASK 0x80
+#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL__SHIFT 0x7
+#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE_MASK 0x100
+#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE__SHIFT 0x8
+#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY_MASK 0x200
+#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY__SHIFT 0x9
+#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN_MASK 0x400
+#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN__SHIFT 0xa
+#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN_MASK 0x800
+#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN__SHIFT 0xb
+#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY_MASK 0x1000
+#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY__SHIFT 0xc
+#define MC_ARB_GECC2_MISC__DEBUG_RSV_MASK 0xffffe000
+#define MC_ARB_GECC2_MISC__DEBUG_RSV__SHIFT 0xd
+#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x3
+#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x0
+#define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x4
+#define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x2
+#define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x18
+#define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x3
+#define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x20
+#define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x5
+#define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0xff
+#define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x0
+#define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0xff00
+#define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8
+#define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0xff0000
+#define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10
+#define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000
+#define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x18
+#define MC_ARB_PERF_CID__CH0_MASK 0xff
+#define MC_ARB_PERF_CID__CH0__SHIFT 0x0
+#define MC_ARB_PERF_CID__CH1_MASK 0xff00
+#define MC_ARB_PERF_CID__CH1__SHIFT 0x8
+#define MC_ARB_PERF_CID__CH0_EN_MASK 0x10000
+#define MC_ARB_PERF_CID__CH0_EN__SHIFT 0x10
+#define MC_ARB_PERF_CID__CH1_EN_MASK 0x20000
+#define MC_ARB_PERF_CID__CH1_EN__SHIFT 0x11
+#define MC_ARB_SNOOP__TC_GRP_RD_MASK 0x7
+#define MC_ARB_SNOOP__TC_GRP_RD__SHIFT 0x0
+#define MC_ARB_SNOOP__TC_GRP_RD_EN_MASK 0x8
+#define MC_ARB_SNOOP__TC_GRP_RD_EN__SHIFT 0x3
+#define MC_ARB_SNOOP__TC_GRP_WR_MASK 0x70
+#define MC_ARB_SNOOP__TC_GRP_WR__SHIFT 0x4
+#define MC_ARB_SNOOP__TC_GRP_WR_EN_MASK 0x80
+#define MC_ARB_SNOOP__TC_GRP_WR_EN__SHIFT 0x7
+#define MC_ARB_SNOOP__SDMA_GRP_RD_MASK 0x700
+#define MC_ARB_SNOOP__SDMA_GRP_RD__SHIFT 0x8
+#define MC_ARB_SNOOP__SDMA_GRP_RD_EN_MASK 0x800
+#define MC_ARB_SNOOP__SDMA_GRP_RD_EN__SHIFT 0xb
+#define MC_ARB_SNOOP__SDMA_GRP_WR_MASK 0x7000
+#define MC_ARB_SNOOP__SDMA_GRP_WR__SHIFT 0xc
+#define MC_ARB_SNOOP__SDMA_GRP_WR_EN_MASK 0x8000
+#define MC_ARB_SNOOP__SDMA_GRP_WR_EN__SHIFT 0xf
+#define MC_ARB_SNOOP__OUTSTANDING_RD_MASK 0xff0000
+#define MC_ARB_SNOOP__OUTSTANDING_RD__SHIFT 0x10
+#define MC_ARB_SNOOP__OUTSTANDING_WR_MASK 0xff000000
+#define MC_ARB_SNOOP__OUTSTANDING_WR__SHIFT 0x18
+#define MC_ARB_GRUB__GRUB_WATERMARK_MASK 0xff
+#define MC_ARB_GRUB__GRUB_WATERMARK__SHIFT 0x0
+#define MC_ARB_GRUB__GRUB_WATERMARK_PRI_MASK 0xff00
+#define MC_ARB_GRUB__GRUB_WATERMARK_PRI__SHIFT 0x8
+#define MC_ARB_GRUB__GRUB_WATERMARK_MED_MASK 0xff0000
+#define MC_ARB_GRUB__GRUB_WATERMARK_MED__SHIFT 0x10
+#define MC_ARB_GRUB__REG_WR_EN_MASK 0x3000000
+#define MC_ARB_GRUB__REG_WR_EN__SHIFT 0x18
+#define MC_ARB_GRUB__REG_RD_SEL_MASK 0x4000000
+#define MC_ARB_GRUB__REG_RD_SEL__SHIFT 0x1a
+#define MC_ARB_GECC2__ENABLE_MASK 0x1
+#define MC_ARB_GECC2__ENABLE__SHIFT 0x0
+#define MC_ARB_GECC2__ECC_MODE_MASK 0x6
+#define MC_ARB_GECC2__ECC_MODE__SHIFT 0x1
+#define MC_ARB_GECC2__PAGE_BIT0_MASK 0x18
+#define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x3
+#define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x60
+#define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x5
+#define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x780
+#define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x7
+#define MC_ARB_GECC2__READ_ERR_MASK 0x3800
+#define MC_ARB_GECC2__READ_ERR__SHIFT 0xb
+#define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x4000
+#define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0xe
+#define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x1f8000
+#define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0xf
+#define MC_ARB_GECC2__WRADDR_CONV_MASK 0x200000
+#define MC_ARB_GECC2__WRADDR_CONV__SHIFT 0x15
+#define MC_ARB_GECC2__RMWRD_UNCOR_POISON_MASK 0x400000
+#define MC_ARB_GECC2__RMWRD_UNCOR_POISON__SHIFT 0x16
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0xff
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x0
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0xff00
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x8
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0xff0000
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x10
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x18
+#define MC_ARB_ADDR_SWIZ0__A8_MASK 0xf
+#define MC_ARB_ADDR_SWIZ0__A8__SHIFT 0x0
+#define MC_ARB_ADDR_SWIZ0__A9_MASK 0xf0
+#define MC_ARB_ADDR_SWIZ0__A9__SHIFT 0x4
+#define MC_ARB_ADDR_SWIZ0__A10_MASK 0xf00
+#define MC_ARB_ADDR_SWIZ0__A10__SHIFT 0x8
+#define MC_ARB_ADDR_SWIZ0__A11_MASK 0xf000
+#define MC_ARB_ADDR_SWIZ0__A11__SHIFT 0xc
+#define MC_ARB_ADDR_SWIZ0__A12_MASK 0xf0000
+#define MC_ARB_ADDR_SWIZ0__A12__SHIFT 0x10
+#define MC_ARB_ADDR_SWIZ0__A13_MASK 0xf00000
+#define MC_ARB_ADDR_SWIZ0__A13__SHIFT 0x14
+#define MC_ARB_ADDR_SWIZ0__A14_MASK 0xf000000
+#define MC_ARB_ADDR_SWIZ0__A14__SHIFT 0x18
+#define MC_ARB_ADDR_SWIZ0__A15_MASK 0xf0000000
+#define MC_ARB_ADDR_SWIZ0__A15__SHIFT 0x1c
+#define MC_ARB_ADDR_SWIZ1__A16_MASK 0xf
+#define MC_ARB_ADDR_SWIZ1__A16__SHIFT 0x0
+#define MC_ARB_ADDR_SWIZ1__A17_MASK 0xf0
+#define MC_ARB_ADDR_SWIZ1__A17__SHIFT 0x4
+#define MC_ARB_ADDR_SWIZ1__A18_MASK 0xf00
+#define MC_ARB_ADDR_SWIZ1__A18__SHIFT 0x8
+#define MC_ARB_ADDR_SWIZ1__A19_MASK 0xf000
+#define MC_ARB_ADDR_SWIZ1__A19__SHIFT 0xc
+#define MC_ARB_MISC3__NO_GECC_EXT_EOB_MASK 0x1
+#define MC_ARB_MISC3__NO_GECC_EXT_EOB__SHIFT 0x0
+#define MC_ARB_MISC3__CHAN4_EN_MASK 0x2
+#define MC_ARB_MISC3__CHAN4_EN__SHIFT 0x1
+#define MC_ARB_MISC3__CHAN4_ARB_SEL_MASK 0x4
+#define MC_ARB_MISC3__CHAN4_ARB_SEL__SHIFT 0x2
+#define MC_ARB_MISC3__UVD_URG_MODE_MASK 0x8
+#define MC_ARB_MISC3__UVD_URG_MODE__SHIFT 0x3
+#define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN_MASK 0x10
+#define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN__SHIFT 0x4
+#define MC_ARB_MISC3__TBD_FIELD_MASK 0xffffffe0
+#define MC_ARB_MISC3__TBD_FIELD__SHIFT 0x5
+#define MC_ARB_GRUB_PROMOTE__URGENT_RD_MASK 0xff
+#define MC_ARB_GRUB_PROMOTE__URGENT_RD__SHIFT 0x0
+#define MC_ARB_GRUB_PROMOTE__URGENT_WR_MASK 0xff00
+#define MC_ARB_GRUB_PROMOTE__URGENT_WR__SHIFT 0x8
+#define MC_ARB_GRUB_PROMOTE__PROMOTE_RD_MASK 0xff0000
+#define MC_ARB_GRUB_PROMOTE__PROMOTE_RD__SHIFT 0x10
+#define MC_ARB_GRUB_PROMOTE__PROMOTE_WR_MASK 0xff000000
+#define MC_ARB_GRUB_PROMOTE__PROMOTE_WR__SHIFT 0x18
+#define MC_ARB_RTT_DATA__PATTERN_MASK 0xff
+#define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x0
+#define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x1
+#define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x0
+#define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x2
+#define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x1
+#define MC_ARB_RTT_CNTL0__START_R2W_MASK 0xc
+#define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x2
+#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x10
+#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x4
+#define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x20
+#define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x5
+#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x40
+#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x6
+#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x80
+#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x7
+#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x100
+#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x8
+#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x200
+#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x9
+#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x400
+#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa
+#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x3800
+#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0xb
+#define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x4000
+#define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0xe
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x8000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0xf
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x10000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x10
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x20000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x11
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x40000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x12
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x80000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x13
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x100000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x14
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x200000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x15
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x400000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x16
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x800000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x17
+#define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x1000000
+#define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x18
+#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x2000000
+#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x19
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x1f
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x0
+#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x20
+#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x5
+#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x1fc0
+#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x6
+#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0xfe000
+#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0xd
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x1f00000
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x14
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x19
+#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000
+#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x1e
+#define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x3f
+#define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x0
+#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0xfc0
+#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x6
+#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x1000
+#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0xc
+#define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x2000
+#define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0xd
+#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x3
+#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x0
+#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0xc
+#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x2
+#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0xff0
+#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x4
+#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x1f000
+#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0xc
+#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x1fe0000
+#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x11
+#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000
+#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x19
+#define MC_ARB_CAC_CNTL__ENABLE_MASK 0x1
+#define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x0
+#define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x7e
+#define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x1
+#define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x1f80
+#define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x7
+#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x2000
+#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0xd
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x20
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x5
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x40
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x6
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x80
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x7
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x100
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x8
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x200
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x9
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x400
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa
+#define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x800
+#define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0xb
+#define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x1000
+#define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0xc
+#define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x2000
+#define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0xd
+#define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x3c000
+#define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0xe
+#define MC_ARB_MISC2__GECC_MASK 0x40000
+#define MC_ARB_MISC2__GECC__SHIFT 0x12
+#define MC_ARB_MISC2__GECC_RST_MASK 0x80000
+#define MC_ARB_MISC2__GECC_RST__SHIFT 0x13
+#define MC_ARB_MISC2__GECC_STATUS_MASK 0x100000
+#define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x14
+#define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x1e00000
+#define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x15
+#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0xe000000
+#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x19
+#define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000
+#define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x1c
+#define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000
+#define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d
+#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000
+#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x1e
+#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000
+#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x1f
+#define MC_ARB_MISC__STICKY_RFSH_MASK 0x1
+#define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x0
+#define MC_ARB_MISC__IDLE_RFSH_MASK 0x2
+#define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x1
+#define MC_ARB_MISC__STUTTER_RFSH_MASK 0x4
+#define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x2
+#define MC_ARB_MISC__CHAN_COUPLE_MASK 0x7f8
+#define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x3
+#define MC_ARB_MISC__HARSHNESS_MASK 0x7f800
+#define MC_ARB_MISC__HARSHNESS__SHIFT 0xb
+#define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x80000
+#define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x13
+#define MC_ARB_MISC__CALI_ENABLE_MASK 0x100000
+#define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x14
+#define MC_ARB_MISC__CALI_RATES_MASK 0x600000
+#define MC_ARB_MISC__CALI_RATES__SHIFT 0x15
+#define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x800000
+#define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x17
+#define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x1000000
+#define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x18
+#define MC_ARB_MISC__DISPURG_STALL_MASK 0x2000000
+#define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x19
+#define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000
+#define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x1a
+#define MC_ARB_MISC__EXTEND_WEIGHT_MASK 0x40000000
+#define MC_ARB_MISC__EXTEND_WEIGHT__SHIFT 0x1e
+#define MC_ARB_MISC__ACPURG_STALL_MASK 0x80000000
+#define MC_ARB_MISC__ACPURG_STALL__SHIFT 0x1f
+#define MC_ARB_BANKMAP__BANK0_MASK 0xf
+#define MC_ARB_BANKMAP__BANK0__SHIFT 0x0
+#define MC_ARB_BANKMAP__BANK1_MASK 0xf0
+#define MC_ARB_BANKMAP__BANK1__SHIFT 0x4
+#define MC_ARB_BANKMAP__BANK2_MASK 0xf00
+#define MC_ARB_BANKMAP__BANK2__SHIFT 0x8
+#define MC_ARB_BANKMAP__BANK3_MASK 0xf000
+#define MC_ARB_BANKMAP__BANK3__SHIFT 0xc
+#define MC_ARB_BANKMAP__RANK_MASK 0xf0000
+#define MC_ARB_BANKMAP__RANK__SHIFT 0x10
+#define MC_ARB_RAMCFG__NOOFBANK_MASK 0x3
+#define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x0
+#define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x4
+#define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x2
+#define MC_ARB_RAMCFG__NOOFROWS_MASK 0x38
+#define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x3
+#define MC_ARB_RAMCFG__NOOFCOLS_MASK 0xc0
+#define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x6
+#define MC_ARB_RAMCFG__CHANSIZE_MASK 0x100
+#define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x8
+#define MC_ARB_RAMCFG__RSV_1_MASK 0x200
+#define MC_ARB_RAMCFG__RSV_1__SHIFT 0x9
+#define MC_ARB_RAMCFG__RSV_2_MASK 0x400
+#define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa
+#define MC_ARB_RAMCFG__RSV_3_MASK 0x800
+#define MC_ARB_RAMCFG__RSV_3__SHIFT 0xb
+#define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x1000
+#define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0xc
+#define MC_ARB_RAMCFG__RSV_4_MASK 0x3e000
+#define MC_ARB_RAMCFG__RSV_4__SHIFT 0xd
+#define MC_ARB_POP__ENABLE_ARB_MASK 0x1
+#define MC_ARB_POP__ENABLE_ARB__SHIFT 0x0
+#define MC_ARB_POP__SPEC_OPEN_MASK 0x2
+#define MC_ARB_POP__SPEC_OPEN__SHIFT 0x1
+#define MC_ARB_POP__POP_DEPTH_MASK 0x3c
+#define MC_ARB_POP__POP_DEPTH__SHIFT 0x2
+#define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0xfc0
+#define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x6
+#define MC_ARB_POP__SKID_DEPTH_MASK 0x7000
+#define MC_ARB_POP__SKID_DEPTH__SHIFT 0xc
+#define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x18000
+#define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0xf
+#define MC_ARB_POP__QUICK_STOP_MASK 0x20000
+#define MC_ARB_POP__QUICK_STOP__SHIFT 0x11
+#define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x40000
+#define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x12
+#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x80000
+#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x13
+#define MC_ARB_MINCLKS__READ_CLKS_MASK 0xff
+#define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x0
+#define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0xff00
+#define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x8
+#define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x10000
+#define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x10
+#define MC_ARB_MINCLKS__RW_SWITCH_HARSH_MASK 0x60000
+#define MC_ARB_MINCLKS__RW_SWITCH_HARSH__SHIFT 0x11
+#define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0xff
+#define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x0
+#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x100
+#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x8
+#define MC_ARB_SQM_CNTL__SQM_RDY16_MASK 0x200
+#define MC_ARB_SQM_CNTL__SQM_RDY16__SHIFT 0x9
+#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0xfc00
+#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa
+#define MC_ARB_SQM_CNTL__RATIO_MASK 0xff0000
+#define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x10
+#define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000
+#define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x18
+#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0xf
+#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x0
+#define MC_ARB_ADDR_HASH__COL_XOR_MASK 0xff0
+#define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x4
+#define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0xffff000
+#define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0xc
+#define MC_ARB_DRAM_TIMING__ACTRD_MASK 0xff
+#define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x0
+#define MC_ARB_DRAM_TIMING__ACTWR_MASK 0xff00
+#define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x8
+#define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0xff0000
+#define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x10
+#define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000
+#define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x18
+#define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0xff
+#define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x0
+#define MC_ARB_DRAM_TIMING2__RP_MASK 0xff00
+#define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x8
+#define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0xff0000
+#define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x10
+#define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000
+#define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x18
+#define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x3
+#define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x0
+#define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x4
+#define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x2
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x8
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x3
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x10
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x4
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x20
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x5
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x40
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x6
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x80
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x7
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x100
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x8
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x200
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x9
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x400
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa
+#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK 0x800
+#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI__SHIFT 0xb
+#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP_MASK 0x1000
+#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP__SHIFT 0xc
+#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG_MASK 0x2000
+#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG__SHIFT 0xd
+#define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x3
+#define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x0
+#define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x4
+#define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x2
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x8
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x3
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x10
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x4
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x20
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x5
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x40
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x6
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x80
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x7
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x100
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x8
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x200
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x9
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x400
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa
+#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK 0x800
+#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI__SHIFT 0xb
+#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP_MASK 0x1000
+#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP__SHIFT 0xc
+#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG_MASK 0x2000
+#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG__SHIFT 0xd
+#define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x3
+#define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x0
+#define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0xc
+#define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x2
+#define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x30
+#define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x4
+#define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0xc0
+#define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x6
+#define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x300
+#define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x8
+#define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0xc00
+#define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0xa
+#define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x3000
+#define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0xc
+#define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0xc000
+#define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0xe
+#define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0xff0000
+#define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x10
+#define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x3
+#define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x0
+#define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0xc
+#define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x2
+#define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x30
+#define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x4
+#define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0xc0
+#define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x6
+#define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x300
+#define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x8
+#define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0xc00
+#define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0xa
+#define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x3000
+#define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0xc
+#define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0xc000
+#define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0xe
+#define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0xff0000
+#define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x10
+#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x1
+#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x0
+#define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x6
+#define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x1
+#define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x8
+#define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x3
+#define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x10
+#define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x4
+#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x1
+#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x0
+#define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x6
+#define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x1
+#define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x8
+#define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x3
+#define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x10
+#define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x4
+#define MC_ARB_LAZY0_RD__GROUP0_MASK 0xff
+#define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_LAZY0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_LAZY0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_LAZY0_WR__GROUP0_MASK 0xff
+#define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_LAZY0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_LAZY0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_LAZY1_RD__GROUP4_MASK 0xff
+#define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_LAZY1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_LAZY1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_LAZY1_WR__GROUP4_MASK 0xff
+#define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_LAZY1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_LAZY1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x3
+#define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x0
+#define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0xc
+#define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x2
+#define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x30
+#define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x4
+#define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0xc0
+#define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x6
+#define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x300
+#define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x8
+#define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0xc00
+#define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0xa
+#define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x3000
+#define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0xc
+#define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0xc000
+#define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0xe
+#define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x10000
+#define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x10
+#define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x20000
+#define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x11
+#define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x40000
+#define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x12
+#define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x80000
+#define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x13
+#define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x100000
+#define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x14
+#define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x200000
+#define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x15
+#define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x400000
+#define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x16
+#define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x800000
+#define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x17
+#define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x1000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x18
+#define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x2000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x19
+#define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x4000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x1a
+#define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x8000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x1b
+#define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x1c
+#define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d
+#define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x1e
+#define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x1f
+#define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x3
+#define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x0
+#define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0xc
+#define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x2
+#define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x30
+#define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x4
+#define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0xc0
+#define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x6
+#define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x300
+#define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x8
+#define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0xc00
+#define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0xa
+#define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x3000
+#define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0xc
+#define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0xc000
+#define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0xe
+#define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x10000
+#define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x10
+#define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x20000
+#define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x11
+#define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x40000
+#define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x12
+#define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x80000
+#define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x13
+#define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x100000
+#define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x14
+#define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x200000
+#define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x15
+#define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x400000
+#define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x16
+#define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x800000
+#define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x17
+#define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x1000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x18
+#define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x2000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x19
+#define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x4000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x1a
+#define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x8000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x1b
+#define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x1c
+#define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d
+#define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x1e
+#define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x1f
+#define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x1
+#define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x0
+#define MC_ARB_RFSH_CNTL__URG0_MASK 0x3e
+#define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x1
+#define MC_ARB_RFSH_CNTL__URG1_MASK 0x7c0
+#define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x6
+#define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x800
+#define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0xb
+#define MC_ARB_RFSH_CNTL__SINGLE_BANK_MASK 0x1000
+#define MC_ARB_RFSH_CNTL__SINGLE_BANK__SHIFT 0xc
+#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH_MASK 0x2000
+#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH__SHIFT 0xd
+#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL_MASK 0x1c000
+#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL__SHIFT 0xe
+#define MC_ARB_RFSH_CNTL__REFSB_PER_PAGE_MASK 0x20000
+#define MC_ARB_RFSH_CNTL__REFSB_PER_PAGE__SHIFT 0x11
+#define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0xff
+#define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x0
+#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x3
+#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x0
+#define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x4
+#define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x2
+#define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x8
+#define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x3
+#define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x10
+#define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x4
+#define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x20
+#define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x5
+#define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x40
+#define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x6
+#define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x80
+#define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x7
+#define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x300
+#define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x8
+#define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x400
+#define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0xa
+#define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x800
+#define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb
+#define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x1000
+#define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0xc
+#define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x2000
+#define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd
+#define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x4000
+#define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0xe
+#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000
+#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf
+#define MC_ARB_PM_CNTL__OVRR_RD0_BUSY_MASK 0x10000
+#define MC_ARB_PM_CNTL__OVRR_RD0_BUSY__SHIFT 0x10
+#define MC_ARB_PM_CNTL__OVRR_RD1_BUSY_MASK 0x20000
+#define MC_ARB_PM_CNTL__OVRR_RD1_BUSY__SHIFT 0x11
+#define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x40000
+#define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x12
+#define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x80000
+#define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x13
+#define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0xf00000
+#define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x14
+#define MC_ARB_PM_CNTL__OVRR_WR0_BUSY_MASK 0x1000000
+#define MC_ARB_PM_CNTL__OVRR_WR0_BUSY__SHIFT 0x18
+#define MC_ARB_PM_CNTL__OVRR_WR1_BUSY_MASK 0x2000000
+#define MC_ARB_PM_CNTL__OVRR_WR1_BUSY__SHIFT 0x19
+#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0xf
+#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x0
+#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0xf0
+#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x4
+#define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x100
+#define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x8
+#define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x200
+#define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x9
+#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
+#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
+#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0xf
+#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x0
+#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0xf0
+#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x4
+#define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x100
+#define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x8
+#define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x200
+#define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x9
+#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
+#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
+#define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0xff
+#define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x0
+#define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0xff00
+#define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x8
+#define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x10000
+#define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x10
+#define MC_ARB_LM_RD__STREAK_UBER_MASK 0x20000
+#define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x11
+#define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x40000
+#define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x12
+#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x80000
+#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x13
+#define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x100000
+#define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x14
+#define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0xe00000
+#define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x15
+#define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0xff
+#define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x0
+#define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0xff00
+#define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x8
+#define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x10000
+#define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x10
+#define MC_ARB_LM_WR__STREAK_UBER_MASK 0x20000
+#define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x11
+#define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x40000
+#define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x12
+#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x80000
+#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x13
+#define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x100000
+#define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x14
+#define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0xe00000
+#define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x15
+#define MC_ARB_LM_WR__MASKWR_LM_EOB_MASK 0x1000000
+#define MC_ARB_LM_WR__MASKWR_LM_EOB__SHIFT 0x18
+#define MC_ARB_LM_WR__ATOMIC_LM_EOB_MASK 0x2000000
+#define MC_ARB_LM_WR__ATOMIC_LM_EOB__SHIFT 0x19
+#define MC_ARB_LM_WR__ATOMIC_RTN_LM_EOB_MASK 0x4000000
+#define MC_ARB_LM_WR__ATOMIC_RTN_LM_EOB__SHIFT 0x1a
+#define MC_ARB_REMREQ__RD_WATER_MASK 0xff
+#define MC_ARB_REMREQ__RD_WATER__SHIFT 0x0
+#define MC_ARB_REMREQ__WR_WATER_MASK 0xff00
+#define MC_ARB_REMREQ__WR_WATER__SHIFT 0x8
+#define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0xf0000
+#define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x10
+#define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0xf00000
+#define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x14
+#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ_MASK 0x1000000
+#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ__SHIFT 0x18
+#define MC_ARB_REPLAY__ENABLE_RD_MASK 0x1
+#define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x0
+#define MC_ARB_REPLAY__ENABLE_WR_MASK 0x2
+#define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x1
+#define MC_ARB_REPLAY__WRACK_MODE_MASK 0x4
+#define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x2
+#define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x8
+#define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x3
+#define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x10
+#define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x4
+#define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x20
+#define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x5
+#define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x40
+#define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x6
+#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x80
+#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x7
+#define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x7f00
+#define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x8
+#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START_MASK 0x8000
+#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START__SHIFT 0xf
+#define MC_ARB_RET_CREDITS_RD__LCL_MASK 0xff
+#define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x0
+#define MC_ARB_RET_CREDITS_RD__HUB_MASK 0xff00
+#define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x8
+#define MC_ARB_RET_CREDITS_RD__DISP_MASK 0xff0000
+#define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x10
+#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000
+#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x18
+#define MC_ARB_RET_CREDITS_WR__LCL_MASK 0xff
+#define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x0
+#define MC_ARB_RET_CREDITS_WR__HUB_MASK 0xff00
+#define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x8
+#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0xff0000
+#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x10
+#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0xf000000
+#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x18
+#define MC_ARB_RET_CREDITS_WR__WRRET_BP_MASK 0x10000000
+#define MC_ARB_RET_CREDITS_WR__WRRET_BP__SHIFT 0x1c
+#define MC_ARB_MAX_LAT_CID__CID_CH0_MASK 0xff
+#define MC_ARB_MAX_LAT_CID__CID_CH0__SHIFT 0x0
+#define MC_ARB_MAX_LAT_CID__CID_CH1_MASK 0xff00
+#define MC_ARB_MAX_LAT_CID__CID_CH1__SHIFT 0x8
+#define MC_ARB_MAX_LAT_CID__WRITE_CH0_MASK 0x10000
+#define MC_ARB_MAX_LAT_CID__WRITE_CH0__SHIFT 0x10
+#define MC_ARB_MAX_LAT_CID__WRITE_CH1_MASK 0x20000
+#define MC_ARB_MAX_LAT_CID__WRITE_CH1__SHIFT 0x11
+#define MC_ARB_MAX_LAT_CID__REALTIME_CH0_MASK 0x40000
+#define MC_ARB_MAX_LAT_CID__REALTIME_CH0__SHIFT 0x12
+#define MC_ARB_MAX_LAT_CID__REALTIME_CH1_MASK 0x80000
+#define MC_ARB_MAX_LAT_CID__REALTIME_CH1__SHIFT 0x13
+#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY_MASK 0xffffffff
+#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY__SHIFT 0x0
+#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY_MASK 0xffffffff
+#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY__SHIFT 0x0
+#define MC_ARB_GRUB_REALTIME_RD__CB0_MASK 0x1
+#define MC_ARB_GRUB_REALTIME_RD__CB0__SHIFT 0x0
+#define MC_ARB_GRUB_REALTIME_RD__CBCMASK0_MASK 0x2
+#define MC_ARB_GRUB_REALTIME_RD__CBCMASK0__SHIFT 0x1
+#define MC_ARB_GRUB_REALTIME_RD__CBFMASK0_MASK 0x4
+#define MC_ARB_GRUB_REALTIME_RD__CBFMASK0__SHIFT 0x2
+#define MC_ARB_GRUB_REALTIME_RD__DB0_MASK 0x8
+#define MC_ARB_GRUB_REALTIME_RD__DB0__SHIFT 0x3
+#define MC_ARB_GRUB_REALTIME_RD__DBHTILE0_MASK 0x10
+#define MC_ARB_GRUB_REALTIME_RD__DBHTILE0__SHIFT 0x4
+#define MC_ARB_GRUB_REALTIME_RD__DBSTEN0_MASK 0x20
+#define MC_ARB_GRUB_REALTIME_RD__DBSTEN0__SHIFT 0x5
+#define MC_ARB_GRUB_REALTIME_RD__TC0_MASK 0x40
+#define MC_ARB_GRUB_REALTIME_RD__TC0__SHIFT 0x6
+#define MC_ARB_GRUB_REALTIME_RD__IA_MASK 0x80
+#define MC_ARB_GRUB_REALTIME_RD__IA__SHIFT 0x7
+#define MC_ARB_GRUB_REALTIME_RD__ACPG_MASK 0x100
+#define MC_ARB_GRUB_REALTIME_RD__ACPG__SHIFT 0x8
+#define MC_ARB_GRUB_REALTIME_RD__ACPO_MASK 0x200
+#define MC_ARB_GRUB_REALTIME_RD__ACPO__SHIFT 0x9
+#define MC_ARB_GRUB_REALTIME_RD__DMIF_MASK 0x400
+#define MC_ARB_GRUB_REALTIME_RD__DMIF__SHIFT 0xa
+#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0_MASK 0x800
+#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0__SHIFT 0xb
+#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1_MASK 0x1000
+#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1__SHIFT 0xc
+#define MC_ARB_GRUB_REALTIME_RD__DMIF_TW_MASK 0x2000
+#define MC_ARB_GRUB_REALTIME_RD__DMIF_TW__SHIFT 0xd
+#define MC_ARB_GRUB_REALTIME_RD__MCIF_MASK 0x4000
+#define MC_ARB_GRUB_REALTIME_RD__MCIF__SHIFT 0xe
+#define MC_ARB_GRUB_REALTIME_RD__RLC_MASK 0x8000
+#define MC_ARB_GRUB_REALTIME_RD__RLC__SHIFT 0xf
+#define MC_ARB_GRUB_REALTIME_RD__VMC_MASK 0x10000
+#define MC_ARB_GRUB_REALTIME_RD__VMC__SHIFT 0x10
+#define MC_ARB_GRUB_REALTIME_RD__SDMA1_MASK 0x20000
+#define MC_ARB_GRUB_REALTIME_RD__SDMA1__SHIFT 0x11
+#define MC_ARB_GRUB_REALTIME_RD__SMU_MASK 0x40000
+#define MC_ARB_GRUB_REALTIME_RD__SMU__SHIFT 0x12
+#define MC_ARB_GRUB_REALTIME_RD__VCE0_MASK 0x80000
+#define MC_ARB_GRUB_REALTIME_RD__VCE0__SHIFT 0x13
+#define MC_ARB_GRUB_REALTIME_RD__VCE1_MASK 0x100000
+#define MC_ARB_GRUB_REALTIME_RD__VCE1__SHIFT 0x14
+#define MC_ARB_GRUB_REALTIME_RD__XDMAM_MASK 0x200000
+#define MC_ARB_GRUB_REALTIME_RD__XDMAM__SHIFT 0x15
+#define MC_ARB_GRUB_REALTIME_RD__SDMA0_MASK 0x400000
+#define MC_ARB_GRUB_REALTIME_RD__SDMA0__SHIFT 0x16
+#define MC_ARB_GRUB_REALTIME_RD__HDP_MASK 0x800000
+#define MC_ARB_GRUB_REALTIME_RD__HDP__SHIFT 0x17
+#define MC_ARB_GRUB_REALTIME_RD__UMC_MASK 0x1000000
+#define MC_ARB_GRUB_REALTIME_RD__UMC__SHIFT 0x18
+#define MC_ARB_GRUB_REALTIME_RD__UVD_MASK 0x2000000
+#define MC_ARB_GRUB_REALTIME_RD__UVD__SHIFT 0x19
+#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0_MASK 0x4000000
+#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0__SHIFT 0x1a
+#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1_MASK 0x8000000
+#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1__SHIFT 0x1b
+#define MC_ARB_GRUB_REALTIME_RD__SEM_MASK 0x10000000
+#define MC_ARB_GRUB_REALTIME_RD__SEM__SHIFT 0x1c
+#define MC_ARB_GRUB_REALTIME_RD__SAMMSP_MASK 0x20000000
+#define MC_ARB_GRUB_REALTIME_RD__SAMMSP__SHIFT 0x1d
+#define MC_ARB_GRUB_REALTIME_RD__VP8_MASK 0x40000000
+#define MC_ARB_GRUB_REALTIME_RD__VP8__SHIFT 0x1e
+#define MC_ARB_GRUB_REALTIME_RD__ISP_MASK 0x80000000
+#define MC_ARB_GRUB_REALTIME_RD__ISP__SHIFT 0x1f
+#define MC_ARB_CG__CG_ARB_REQ_MASK 0xff
+#define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x0
+#define MC_ARB_CG__CG_ARB_RESP_MASK 0xff00
+#define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x8
+#define MC_ARB_CG__RSV_0_MASK 0xff0000
+#define MC_ARB_CG__RSV_0__SHIFT 0x10
+#define MC_ARB_CG__RSV_1_MASK 0xff000000
+#define MC_ARB_CG__RSV_1__SHIFT 0x18
+#define MC_ARB_GRUB_REALTIME_WR__CB0_MASK 0x1
+#define MC_ARB_GRUB_REALTIME_WR__CB0__SHIFT 0x0
+#define MC_ARB_GRUB_REALTIME_WR__CBCMASK0_MASK 0x2
+#define MC_ARB_GRUB_REALTIME_WR__CBCMASK0__SHIFT 0x1
+#define MC_ARB_GRUB_REALTIME_WR__CBFMASK0_MASK 0x4
+#define MC_ARB_GRUB_REALTIME_WR__CBFMASK0__SHIFT 0x2
+#define MC_ARB_GRUB_REALTIME_WR__CBIMMED0_MASK 0x8
+#define MC_ARB_GRUB_REALTIME_WR__CBIMMED0__SHIFT 0x3
+#define MC_ARB_GRUB_REALTIME_WR__DB0_MASK 0x10
+#define MC_ARB_GRUB_REALTIME_WR__DB0__SHIFT 0x4
+#define MC_ARB_GRUB_REALTIME_WR__DBHTILE0_MASK 0x20
+#define MC_ARB_GRUB_REALTIME_WR__DBHTILE0__SHIFT 0x5
+#define MC_ARB_GRUB_REALTIME_WR__DBSTEN0_MASK 0x40
+#define MC_ARB_GRUB_REALTIME_WR__DBSTEN0__SHIFT 0x6
+#define MC_ARB_GRUB_REALTIME_WR__TC0_MASK 0x80
+#define MC_ARB_GRUB_REALTIME_WR__TC0__SHIFT 0x7
+#define MC_ARB_GRUB_REALTIME_WR__SH_MASK 0x100
+#define MC_ARB_GRUB_REALTIME_WR__SH__SHIFT 0x8
+#define MC_ARB_GRUB_REALTIME_WR__ACPG_MASK 0x200
+#define MC_ARB_GRUB_REALTIME_WR__ACPG__SHIFT 0x9
+#define MC_ARB_GRUB_REALTIME_WR__ACPO_MASK 0x400
+#define MC_ARB_GRUB_REALTIME_WR__ACPO__SHIFT 0xa
+#define MC_ARB_GRUB_REALTIME_WR__MCIF_MASK 0x800
+#define MC_ARB_GRUB_REALTIME_WR__MCIF__SHIFT 0xb
+#define MC_ARB_GRUB_REALTIME_WR__RLC_MASK 0x1000
+#define MC_ARB_GRUB_REALTIME_WR__RLC__SHIFT 0xc
+#define MC_ARB_GRUB_REALTIME_WR__SDMA1_MASK 0x2000
+#define MC_ARB_GRUB_REALTIME_WR__SDMA1__SHIFT 0xd
+#define MC_ARB_GRUB_REALTIME_WR__SMU_MASK 0x4000
+#define MC_ARB_GRUB_REALTIME_WR__SMU__SHIFT 0xe
+#define MC_ARB_GRUB_REALTIME_WR__VCE0_MASK 0x8000
+#define MC_ARB_GRUB_REALTIME_WR__VCE0__SHIFT 0xf
+#define MC_ARB_GRUB_REALTIME_WR__VCE1_MASK 0x10000
+#define MC_ARB_GRUB_REALTIME_WR__VCE1__SHIFT 0x10
+#define MC_ARB_GRUB_REALTIME_WR__SAMMSP_MASK 0x20000
+#define MC_ARB_GRUB_REALTIME_WR__SAMMSP__SHIFT 0x11
+#define MC_ARB_GRUB_REALTIME_WR__XDMA_MASK 0x40000
+#define MC_ARB_GRUB_REALTIME_WR__XDMA__SHIFT 0x12
+#define MC_ARB_GRUB_REALTIME_WR__XDMAM_MASK 0x80000
+#define MC_ARB_GRUB_REALTIME_WR__XDMAM__SHIFT 0x13
+#define MC_ARB_GRUB_REALTIME_WR__SDMA0_MASK 0x100000
+#define MC_ARB_GRUB_REALTIME_WR__SDMA0__SHIFT 0x14
+#define MC_ARB_GRUB_REALTIME_WR__HDP_MASK 0x200000
+#define MC_ARB_GRUB_REALTIME_WR__HDP__SHIFT 0x15
+#define MC_ARB_GRUB_REALTIME_WR__UMC_MASK 0x400000
+#define MC_ARB_GRUB_REALTIME_WR__UMC__SHIFT 0x16
+#define MC_ARB_GRUB_REALTIME_WR__UVD_MASK 0x800000
+#define MC_ARB_GRUB_REALTIME_WR__UVD__SHIFT 0x17
+#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0_MASK 0x1000000
+#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0__SHIFT 0x18
+#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1_MASK 0x2000000
+#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1__SHIFT 0x19
+#define MC_ARB_GRUB_REALTIME_WR__XDP_MASK 0x4000000
+#define MC_ARB_GRUB_REALTIME_WR__XDP__SHIFT 0x1a
+#define MC_ARB_GRUB_REALTIME_WR__SEM_MASK 0x8000000
+#define MC_ARB_GRUB_REALTIME_WR__SEM__SHIFT 0x1b
+#define MC_ARB_GRUB_REALTIME_WR__IH_MASK 0x10000000
+#define MC_ARB_GRUB_REALTIME_WR__IH__SHIFT 0x1c
+#define MC_ARB_GRUB_REALTIME_WR__VP8_MASK 0x20000000
+#define MC_ARB_GRUB_REALTIME_WR__VP8__SHIFT 0x1d
+#define MC_ARB_GRUB_REALTIME_WR__ISP_MASK 0x40000000
+#define MC_ARB_GRUB_REALTIME_WR__ISP__SHIFT 0x1e
+#define MC_ARB_GRUB_REALTIME_WR__VIN0_MASK 0x80000000
+#define MC_ARB_GRUB_REALTIME_WR__VIN0__SHIFT 0x1f
+#define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0xff
+#define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x0
+#define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0xff00
+#define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x8
+#define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0xff0000
+#define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x10
+#define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000
+#define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x18
+#define MC_ARB_BUSY_STATUS__LM_RD0_MASK 0x1
+#define MC_ARB_BUSY_STATUS__LM_RD0__SHIFT 0x0
+#define MC_ARB_BUSY_STATUS__LM_RD1_MASK 0x2
+#define MC_ARB_BUSY_STATUS__LM_RD1__SHIFT 0x1
+#define MC_ARB_BUSY_STATUS__LM_WR0_MASK 0x4
+#define MC_ARB_BUSY_STATUS__LM_WR0__SHIFT 0x2
+#define MC_ARB_BUSY_STATUS__LM_WR1_MASK 0x8
+#define MC_ARB_BUSY_STATUS__LM_WR1__SHIFT 0x3
+#define MC_ARB_BUSY_STATUS__HM_RD0_MASK 0x10
+#define MC_ARB_BUSY_STATUS__HM_RD0__SHIFT 0x4
+#define MC_ARB_BUSY_STATUS__HM_RD1_MASK 0x20
+#define MC_ARB_BUSY_STATUS__HM_RD1__SHIFT 0x5
+#define MC_ARB_BUSY_STATUS__HM_WR0_MASK 0x40
+#define MC_ARB_BUSY_STATUS__HM_WR0__SHIFT 0x6
+#define MC_ARB_BUSY_STATUS__HM_WR1_MASK 0x80
+#define MC_ARB_BUSY_STATUS__HM_WR1__SHIFT 0x7
+#define MC_ARB_BUSY_STATUS__WDE_RD0_MASK 0x100
+#define MC_ARB_BUSY_STATUS__WDE_RD0__SHIFT 0x8
+#define MC_ARB_BUSY_STATUS__WDE_RD1_MASK 0x200
+#define MC_ARB_BUSY_STATUS__WDE_RD1__SHIFT 0x9
+#define MC_ARB_BUSY_STATUS__WDE_WR0_MASK 0x400
+#define MC_ARB_BUSY_STATUS__WDE_WR0__SHIFT 0xa
+#define MC_ARB_BUSY_STATUS__WDE_WR1_MASK 0x800
+#define MC_ARB_BUSY_STATUS__WDE_WR1__SHIFT 0xb
+#define MC_ARB_BUSY_STATUS__POP0_MASK 0x1000
+#define MC_ARB_BUSY_STATUS__POP0__SHIFT 0xc
+#define MC_ARB_BUSY_STATUS__POP1_MASK 0x2000
+#define MC_ARB_BUSY_STATUS__POP1__SHIFT 0xd
+#define MC_ARB_BUSY_STATUS__TAGFIFO0_MASK 0x4000
+#define MC_ARB_BUSY_STATUS__TAGFIFO0__SHIFT 0xe
+#define MC_ARB_BUSY_STATUS__TAGFIFO1_MASK 0x8000
+#define MC_ARB_BUSY_STATUS__TAGFIFO1__SHIFT 0xf
+#define MC_ARB_BUSY_STATUS__REPLAY0_MASK 0x10000
+#define MC_ARB_BUSY_STATUS__REPLAY0__SHIFT 0x10
+#define MC_ARB_BUSY_STATUS__REPLAY1_MASK 0x20000
+#define MC_ARB_BUSY_STATUS__REPLAY1__SHIFT 0x11
+#define MC_ARB_BUSY_STATUS__RDRET0_MASK 0x40000
+#define MC_ARB_BUSY_STATUS__RDRET0__SHIFT 0x12
+#define MC_ARB_BUSY_STATUS__RDRET1_MASK 0x80000
+#define MC_ARB_BUSY_STATUS__RDRET1__SHIFT 0x13
+#define MC_ARB_BUSY_STATUS__GECC2_RD0_MASK 0x100000
+#define MC_ARB_BUSY_STATUS__GECC2_RD0__SHIFT 0x14
+#define MC_ARB_BUSY_STATUS__GECC2_RD1_MASK 0x200000
+#define MC_ARB_BUSY_STATUS__GECC2_RD1__SHIFT 0x15
+#define MC_ARB_BUSY_STATUS__GECC2_WR0_MASK 0x400000
+#define MC_ARB_BUSY_STATUS__GECC2_WR0__SHIFT 0x16
+#define MC_ARB_BUSY_STATUS__GECC2_WR1_MASK 0x800000
+#define MC_ARB_BUSY_STATUS__GECC2_WR1__SHIFT 0x17
+#define MC_ARB_BUSY_STATUS__WRRET0_MASK 0x1000000
+#define MC_ARB_BUSY_STATUS__WRRET0__SHIFT 0x18
+#define MC_ARB_BUSY_STATUS__WRRET1_MASK 0x2000000
+#define MC_ARB_BUSY_STATUS__WRRET1__SHIFT 0x19
+#define MC_ARB_BUSY_STATUS__RTT0_MASK 0x4000000
+#define MC_ARB_BUSY_STATUS__RTT0__SHIFT 0x1a
+#define MC_ARB_BUSY_STATUS__RTT1_MASK 0x8000000
+#define MC_ARB_BUSY_STATUS__RTT1__SHIFT 0x1b
+#define MC_ARB_BUSY_STATUS__REM_RD0_MASK 0x10000000
+#define MC_ARB_BUSY_STATUS__REM_RD0__SHIFT 0x1c
+#define MC_ARB_BUSY_STATUS__REM_RD1_MASK 0x20000000
+#define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d
+#define MC_ARB_BUSY_STATUS__REM_WR0_MASK 0x40000000
+#define MC_ARB_BUSY_STATUS__REM_WR0__SHIFT 0x1e
+#define MC_ARB_BUSY_STATUS__REM_WR1_MASK 0x80000000
+#define MC_ARB_BUSY_STATUS__REM_WR1__SHIFT 0x1f
+#define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0xff
+#define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x0
+#define MC_ARB_DRAM_TIMING2_1__RP_MASK 0xff00
+#define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x8
+#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0xff0000
+#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x10
+#define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000
+#define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x18
+#define MC_ARB_GRUB2__REALTIME_GRP_RD_MASK 0xff
+#define MC_ARB_GRUB2__REALTIME_GRP_RD__SHIFT 0x0
+#define MC_ARB_GRUB2__REALTIME_GRP_WR_MASK 0xff00
+#define MC_ARB_GRUB2__REALTIME_GRP_WR__SHIFT 0x8
+#define MC_ARB_GRUB2__DISP_RD_STALL_EN_MASK 0x10000
+#define MC_ARB_GRUB2__DISP_RD_STALL_EN__SHIFT 0x10
+#define MC_ARB_GRUB2__ACP_RD_STALL_EN_MASK 0x20000
+#define MC_ARB_GRUB2__ACP_RD_STALL_EN__SHIFT 0x11
+#define MC_ARB_GRUB2__UVD_RD_STALL_EN_MASK 0x40000
+#define MC_ARB_GRUB2__UVD_RD_STALL_EN__SHIFT 0x12
+#define MC_ARB_GRUB2__VCE0_RD_STALL_EN_MASK 0x80000
+#define MC_ARB_GRUB2__VCE0_RD_STALL_EN__SHIFT 0x13
+#define MC_ARB_GRUB2__VCE1_RD_STALL_EN_MASK 0x100000
+#define MC_ARB_GRUB2__VCE1_RD_STALL_EN__SHIFT 0x14
+#define MC_ARB_GRUB2__REALTIME_RD_WTS_MASK 0x200000
+#define MC_ARB_GRUB2__REALTIME_RD_WTS__SHIFT 0x15
+#define MC_ARB_GRUB2__REALTIME_WR_WTS_MASK 0x400000
+#define MC_ARB_GRUB2__REALTIME_WR_WTS__SHIFT 0x16
+#define MC_ARB_GRUB2__URGENT_BY_DISP_STALL_MASK 0x800000
+#define MC_ARB_GRUB2__URGENT_BY_DISP_STALL__SHIFT 0x17
+#define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG_MASK 0x1000000
+#define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG__SHIFT 0x18
+#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_RD_MASK 0x2000000
+#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_RD__SHIFT 0x19
+#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD_MASK 0x4000000
+#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD__SHIFT 0x1a
+#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_WR_MASK 0x8000000
+#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_WR__SHIFT 0x1b
+#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR_MASK 0x10000000
+#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR__SHIFT 0x1c
+#define MC_ARB_BURST_TIME__STATE0_MASK 0x1f
+#define MC_ARB_BURST_TIME__STATE0__SHIFT 0x0
+#define MC_ARB_BURST_TIME__STATE1_MASK 0x3e0
+#define MC_ARB_BURST_TIME__STATE1__SHIFT 0x5
+#define MC_ARB_BURST_TIME__TRRDS0_MASK 0x7c00
+#define MC_ARB_BURST_TIME__TRRDS0__SHIFT 0xa
+#define MC_ARB_BURST_TIME__TRRDS1_MASK 0xf8000
+#define MC_ARB_BURST_TIME__TRRDS1__SHIFT 0xf
+#define MC_ARB_BURST_TIME__TRRDL0_MASK 0x1f00000
+#define MC_ARB_BURST_TIME__TRRDL0__SHIFT 0x14
+#define MC_ARB_BURST_TIME__TRRDL1_MASK 0x3e000000
+#define MC_ARB_BURST_TIME__TRRDL1__SHIFT 0x19
+#define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x1
+#define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x0
+#define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x2
+#define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x1
+#define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x4
+#define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x2
+#define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x8
+#define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x3
+#define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x10
+#define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x4
+#define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0xf00
+#define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x8
+#define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x1000
+#define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0xc
+#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL_MASK 0x6000
+#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL__SHIFT 0xd
+#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL_MASK 0x18000
+#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL__SHIFT 0xf
+#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL_MASK 0x60000
+#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL__SHIFT 0x11
+#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL_MASK 0x180000
+#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL__SHIFT 0x13
+#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL_MASK 0x600000
+#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL__SHIFT 0x15
+#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL_MASK 0x1800000
+#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL__SHIFT 0x17
+#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE_MASK 0x2000000
+#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE__SHIFT 0x19
+#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE_MASK 0x4000000
+#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE__SHIFT 0x1a
+#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE_MASK 0x8000000
+#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE__SHIFT 0x1b
+#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE_MASK 0x10000000
+#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE__SHIFT 0x1c
+#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE_MASK 0x60000000
+#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d
+#define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x1e
+#define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x1
+#define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x1
+#define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
+#define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x2
+#define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
+#define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x4
+#define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
+#define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
+#define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
+#define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x30
+#define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x4
+#define MC_CG_CONFIG__INDEX_MASK 0x3fffc0
+#define MC_CG_CONFIG__INDEX__SHIFT 0x6
+#define MC_CITF_CNTL__IGNOREPM_MASK 0x4
+#define MC_CITF_CNTL__IGNOREPM__SHIFT 0x2
+#define MC_CITF_CNTL__EXEMPTPM_MASK 0x8
+#define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x3
+#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x30
+#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x4
+#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x40
+#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x6
+#define MC_CITF_CNTL__CNTR_CHMAP_MODE_MASK 0x180
+#define MC_CITF_CNTL__CNTR_CHMAP_MODE__SHIFT 0x7
+#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE_MASK 0x200
+#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE__SHIFT 0x9
+#define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x3f
+#define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x0
+#define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0xfc0
+#define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x6
+#define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0xff
+#define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x0
+#define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0xff00
+#define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x8
+#define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0xff0000
+#define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x10
+#define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x1000000
+#define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x18
+#define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x2000000
+#define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x19
+#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0xff
+#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x0
+#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0xff00
+#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x8
+#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI_MASK 0xff0000
+#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI__SHIFT 0x10
+#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x1000000
+#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x18
+#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x2000000
+#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x19
+#define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x1
+#define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x0
+#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x1e
+#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x1
+#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x20
+#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x5
+#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x3c0
+#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x6
+#define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x3f
+#define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x0
+#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x3f000
+#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0xc
+#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0xfc0000
+#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x12
+#define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000
+#define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x18
+#define MC_CITF_RET_MODE__INORDER_RD_MASK 0x1
+#define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x0
+#define MC_CITF_RET_MODE__INORDER_WR_MASK 0x2
+#define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x1
+#define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x4
+#define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x2
+#define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x8
+#define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x3
+#define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x10
+#define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x4
+#define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x20
+#define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x5
+#define MC_CITF_RET_MODE__RDRET_STALL_EN_MASK 0x40
+#define MC_CITF_RET_MODE__RDRET_STALL_EN__SHIFT 0x6
+#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD_MASK 0x7f80
+#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD__SHIFT 0x7
+#define MC_CITF_DAGB_DLY__DLY_MASK 0x1f
+#define MC_CITF_DAGB_DLY__DLY__SHIFT 0x0
+#define MC_CITF_DAGB_DLY__CLI_MASK 0x3f0000
+#define MC_CITF_DAGB_DLY__CLI__SHIFT 0x10
+#define MC_CITF_DAGB_DLY__POS_MASK 0x3f000000
+#define MC_CITF_DAGB_DLY__POS__SHIFT 0x18
+#define MC_RD_GRP_EXT__DBSTEN0_MASK 0xf
+#define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x0
+#define MC_RD_GRP_EXT__TC0_MASK 0xf0
+#define MC_RD_GRP_EXT__TC0__SHIFT 0x4
+#define MC_WR_GRP_EXT__DBSTEN0_MASK 0xf
+#define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x0
+#define MC_WR_GRP_EXT__TC0_MASK 0xf0
+#define MC_WR_GRP_EXT__TC0__SHIFT 0x4
+#define MC_CITF_REMREQ__READ_CREDITS_MASK 0x7f
+#define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x0
+#define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x3f80
+#define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x7
+#define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x4000
+#define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0xe
+#define MC_WR_TC0__ENABLE_MASK 0x1
+#define MC_WR_TC0__ENABLE__SHIFT 0x0
+#define MC_WR_TC0__PRESCALE_MASK 0x6
+#define MC_WR_TC0__PRESCALE__SHIFT 0x1
+#define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_WR_TC0__STALL_MODE_MASK 0x30
+#define MC_WR_TC0__STALL_MODE__SHIFT 0x4
+#define MC_WR_TC0__STALL_OVERRIDE_MASK 0x40
+#define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_WR_TC0__MAX_BURST_MASK 0x780
+#define MC_WR_TC0__MAX_BURST__SHIFT 0x7
+#define MC_WR_TC0__LAZY_TIMER_MASK 0x7800
+#define MC_WR_TC0__LAZY_TIMER__SHIFT 0xb
+#define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_WR_TC1__ENABLE_MASK 0x1
+#define MC_WR_TC1__ENABLE__SHIFT 0x0
+#define MC_WR_TC1__PRESCALE_MASK 0x6
+#define MC_WR_TC1__PRESCALE__SHIFT 0x1
+#define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_WR_TC1__STALL_MODE_MASK 0x30
+#define MC_WR_TC1__STALL_MODE__SHIFT 0x4
+#define MC_WR_TC1__STALL_OVERRIDE_MASK 0x40
+#define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_WR_TC1__MAX_BURST_MASK 0x780
+#define MC_WR_TC1__MAX_BURST__SHIFT 0x7
+#define MC_WR_TC1__LAZY_TIMER_MASK 0x7800
+#define MC_WR_TC1__LAZY_TIMER__SHIFT 0xb
+#define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x3f
+#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x0
+#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0xfc0
+#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x6
+#define MC_CITF_CREDITS_ARB_RD2__READ_MED_MASK 0xff
+#define MC_CITF_CREDITS_ARB_RD2__READ_MED__SHIFT 0x0
+#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x7
+#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x0
+#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x38
+#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x3
+#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x1c0
+#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x6
+#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0xe00
+#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x9
+#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x7000
+#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0xc
+#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x38000
+#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0xf
+#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
+#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x12
+#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0xe00000
+#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x15
+#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x1000000
+#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x18
+#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL_MASK 0x2000000
+#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL__SHIFT 0x19
+#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x7
+#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x0
+#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x38
+#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x3
+#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x1c0
+#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x6
+#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0xe00
+#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x9
+#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x7000
+#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0xc
+#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x38000
+#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0xf
+#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
+#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x12
+#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0xe00000
+#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x15
+#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x1000000
+#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x18
+#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL_MASK 0x2000000
+#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL__SHIFT 0x19
+#define MC_RD_CB__ENABLE_MASK 0x1
+#define MC_RD_CB__ENABLE__SHIFT 0x0
+#define MC_RD_CB__PRESCALE_MASK 0x6
+#define MC_RD_CB__PRESCALE__SHIFT 0x1
+#define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_RD_CB__STALL_MODE_MASK 0x30
+#define MC_RD_CB__STALL_MODE__SHIFT 0x4
+#define MC_RD_CB__STALL_OVERRIDE_MASK 0x40
+#define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_RD_CB__MAX_BURST_MASK 0x780
+#define MC_RD_CB__MAX_BURST__SHIFT 0x7
+#define MC_RD_CB__LAZY_TIMER_MASK 0x7800
+#define MC_RD_CB__LAZY_TIMER__SHIFT 0xb
+#define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_RD_DB__ENABLE_MASK 0x1
+#define MC_RD_DB__ENABLE__SHIFT 0x0
+#define MC_RD_DB__PRESCALE_MASK 0x6
+#define MC_RD_DB__PRESCALE__SHIFT 0x1
+#define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_RD_DB__STALL_MODE_MASK 0x30
+#define MC_RD_DB__STALL_MODE__SHIFT 0x4
+#define MC_RD_DB__STALL_OVERRIDE_MASK 0x40
+#define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_RD_DB__MAX_BURST_MASK 0x780
+#define MC_RD_DB__MAX_BURST__SHIFT 0x7
+#define MC_RD_DB__LAZY_TIMER_MASK 0x7800
+#define MC_RD_DB__LAZY_TIMER__SHIFT 0xb
+#define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_RD_TC0__ENABLE_MASK 0x1
+#define MC_RD_TC0__ENABLE__SHIFT 0x0
+#define MC_RD_TC0__PRESCALE_MASK 0x6
+#define MC_RD_TC0__PRESCALE__SHIFT 0x1
+#define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_RD_TC0__STALL_MODE_MASK 0x30
+#define MC_RD_TC0__STALL_MODE__SHIFT 0x4
+#define MC_RD_TC0__STALL_OVERRIDE_MASK 0x40
+#define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_RD_TC0__MAX_BURST_MASK 0x780
+#define MC_RD_TC0__MAX_BURST__SHIFT 0x7
+#define MC_RD_TC0__LAZY_TIMER_MASK 0x7800
+#define MC_RD_TC0__LAZY_TIMER__SHIFT 0xb
+#define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_RD_TC1__ENABLE_MASK 0x1
+#define MC_RD_TC1__ENABLE__SHIFT 0x0
+#define MC_RD_TC1__PRESCALE_MASK 0x6
+#define MC_RD_TC1__PRESCALE__SHIFT 0x1
+#define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_RD_TC1__STALL_MODE_MASK 0x30
+#define MC_RD_TC1__STALL_MODE__SHIFT 0x4
+#define MC_RD_TC1__STALL_OVERRIDE_MASK 0x40
+#define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_RD_TC1__MAX_BURST_MASK 0x780
+#define MC_RD_TC1__MAX_BURST__SHIFT 0x7
+#define MC_RD_TC1__LAZY_TIMER_MASK 0x7800
+#define MC_RD_TC1__LAZY_TIMER__SHIFT 0xb
+#define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_RD_HUB__ENABLE_MASK 0x1
+#define MC_RD_HUB__ENABLE__SHIFT 0x0
+#define MC_RD_HUB__PRESCALE_MASK 0x6
+#define MC_RD_HUB__PRESCALE__SHIFT 0x1
+#define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_RD_HUB__STALL_MODE_MASK 0x30
+#define MC_RD_HUB__STALL_MODE__SHIFT 0x4
+#define MC_RD_HUB__STALL_OVERRIDE_MASK 0x40
+#define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_RD_HUB__MAX_BURST_MASK 0x780
+#define MC_RD_HUB__MAX_BURST__SHIFT 0x7
+#define MC_RD_HUB__LAZY_TIMER_MASK 0x7800
+#define MC_RD_HUB__LAZY_TIMER__SHIFT 0xb
+#define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_WR_CB__ENABLE_MASK 0x1
+#define MC_WR_CB__ENABLE__SHIFT 0x0
+#define MC_WR_CB__PRESCALE_MASK 0x6
+#define MC_WR_CB__PRESCALE__SHIFT 0x1
+#define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_WR_CB__STALL_MODE_MASK 0x30
+#define MC_WR_CB__STALL_MODE__SHIFT 0x4
+#define MC_WR_CB__STALL_OVERRIDE_MASK 0x40
+#define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_WR_CB__MAX_BURST_MASK 0x780
+#define MC_WR_CB__MAX_BURST__SHIFT 0x7
+#define MC_WR_CB__LAZY_TIMER_MASK 0x7800
+#define MC_WR_CB__LAZY_TIMER__SHIFT 0xb
+#define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_WR_DB__ENABLE_MASK 0x1
+#define MC_WR_DB__ENABLE__SHIFT 0x0
+#define MC_WR_DB__PRESCALE_MASK 0x6
+#define MC_WR_DB__PRESCALE__SHIFT 0x1
+#define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_WR_DB__STALL_MODE_MASK 0x30
+#define MC_WR_DB__STALL_MODE__SHIFT 0x4
+#define MC_WR_DB__STALL_OVERRIDE_MASK 0x40
+#define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_WR_DB__MAX_BURST_MASK 0x780
+#define MC_WR_DB__MAX_BURST__SHIFT 0x7
+#define MC_WR_DB__LAZY_TIMER_MASK 0x7800
+#define MC_WR_DB__LAZY_TIMER__SHIFT 0xb
+#define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_WR_HUB__ENABLE_MASK 0x1
+#define MC_WR_HUB__ENABLE__SHIFT 0x0
+#define MC_WR_HUB__PRESCALE_MASK 0x6
+#define MC_WR_HUB__PRESCALE__SHIFT 0x1
+#define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_WR_HUB__STALL_MODE_MASK 0x30
+#define MC_WR_HUB__STALL_MODE__SHIFT 0x4
+#define MC_WR_HUB__STALL_OVERRIDE_MASK 0x40
+#define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_WR_HUB__MAX_BURST_MASK 0x780
+#define MC_WR_HUB__MAX_BURST__SHIFT 0x7
+#define MC_WR_HUB__LAZY_TIMER_MASK 0x7800
+#define MC_WR_HUB__LAZY_TIMER__SHIFT 0xb
+#define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0xff
+#define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x0
+#define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0xff00
+#define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x8
+#define MC_RD_GRP_LCL__CB0_MASK 0xf000
+#define MC_RD_GRP_LCL__CB0__SHIFT 0xc
+#define MC_RD_GRP_LCL__CBCMASK0_MASK 0xf0000
+#define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x10
+#define MC_RD_GRP_LCL__CBFMASK0_MASK 0xf00000
+#define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x14
+#define MC_RD_GRP_LCL__DB0_MASK 0xf000000
+#define MC_RD_GRP_LCL__DB0__SHIFT 0x18
+#define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000
+#define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x1c
+#define MC_WR_GRP_LCL__CB0_MASK 0xf
+#define MC_WR_GRP_LCL__CB0__SHIFT 0x0
+#define MC_WR_GRP_LCL__CBCMASK0_MASK 0xf0
+#define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x4
+#define MC_WR_GRP_LCL__CBFMASK0_MASK 0xf00
+#define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x8
+#define MC_WR_GRP_LCL__DB0_MASK 0xf000
+#define MC_WR_GRP_LCL__DB0__SHIFT 0xc
+#define MC_WR_GRP_LCL__DBHTILE0_MASK 0xf0000
+#define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x10
+#define MC_WR_GRP_LCL__SX0_MASK 0xf00000
+#define MC_WR_GRP_LCL__SX0__SHIFT 0x14
+#define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000
+#define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x1c
+#define MC_CITF_PERF_MON_CNTL2__CID_MASK 0xff
+#define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x0
+#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x2
+#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x1
+#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x4
+#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x2
+#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x8
+#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x3
+#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x10
+#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x4
+#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x20
+#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0x5
+#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x40
+#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0x6
+#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x80
+#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0x7
+#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x100
+#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0x8
+#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x200
+#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0x9
+#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x400
+#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0xa
+#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x800
+#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0xb
+#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x1000
+#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0xc
+#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x2000
+#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0xd
+#define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY_MASK 0x4000
+#define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY__SHIFT 0xe
+#define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY_MASK 0x8000
+#define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY__SHIFT 0xf
+#define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY_MASK 0x10000
+#define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY__SHIFT 0x10
+#define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY_MASK 0x20000
+#define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY__SHIFT 0x11
+#define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY_MASK 0x40000
+#define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY__SHIFT 0x12
+#define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x3f
+#define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x0
+#define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0xfc0
+#define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x6
+#define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x3f000
+#define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0xc
+#define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x40000
+#define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x12
+#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x3f
+#define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x0
+#define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0xfc0
+#define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x6
+#define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x3f000
+#define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0xc
+#define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x40000
+#define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x12
+#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x3f
+#define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x0
+#define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0xfc0
+#define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x6
+#define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x3f000
+#define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0xc
+#define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x40000
+#define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x12
+#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x4
+#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x2
+#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x18
+#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x3
+#define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x3f
+#define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x0
+#define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0xfc0
+#define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x6
+#define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x3f000
+#define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0xc
+#define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x40000
+#define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x12
+#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x3f
+#define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x0
+#define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0xfc0
+#define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x6
+#define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x3f000
+#define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0xc
+#define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x40000
+#define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x12
+#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x3f
+#define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x0
+#define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0xfc0
+#define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x6
+#define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x3f000
+#define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0xc
+#define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x40000
+#define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x12
+#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x1
+#define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x0
+#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x2
+#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x1
+#define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC_MASK 0x4
+#define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC__SHIFT 0x2
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x8
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x3
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x10
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x4
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x20
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x5
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x40
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x6
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ_MASK 0x80
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ__SHIFT 0x7
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET_MASK 0x100
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET__SHIFT 0x8
+#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x200
+#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x9
+#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x400
+#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0xa
+#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC_MASK 0x800
+#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC__SHIFT 0xb
+#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x1000
+#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0xc
+#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x2000
+#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0xd
+#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC_MASK 0x4000
+#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC__SHIFT 0xe
+#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x8000
+#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0xf
+#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x10000
+#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0x10
+#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x20000
+#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0x11
+#define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING_MASK 0x40000
+#define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING__SHIFT 0x12
+#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x80000
+#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0x13
+#define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x3
+#define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x0
+#define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffff
+#define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x0
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x2
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x1
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x4
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x2
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x8
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x3
+#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
+#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
+#define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x1fe0
+#define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x5
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x2000
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0xd
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x4000
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0xe
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x8000
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0xf
+#define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x10000
+#define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x10
+#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x20000
+#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x11
+#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x40000
+#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x12
+#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x80000
+#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x13
+#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x100000
+#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x14
+#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN_MASK 0x200000
+#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN__SHIFT 0x15
+#define MC_HUB_WDP_CNTL__WRITE_PRI_EN_MASK 0x400000
+#define MC_HUB_WDP_CNTL__WRITE_PRI_EN__SHIFT 0x16
+#define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE_MASK 0x800000
+#define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE__SHIFT 0x17
+#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x1
+#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x0
+#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x2
+#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x1
+#define MC_HUB_WDP_BP__ENABLE_MASK 0x1
+#define MC_HUB_WDP_BP__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_BP__RDRET_MASK 0x3fffe
+#define MC_HUB_WDP_BP__RDRET__SHIFT 0x1
+#define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000
+#define MC_HUB_WDP_BP__WRREQ__SHIFT 0x12
+#define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x1
+#define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x0
+#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x2
+#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
+#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x4
+#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
+#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x8
+#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
+#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x10
+#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
+#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL_MASK 0x20
+#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL__SHIFT 0x5
+#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL_MASK 0x40
+#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL__SHIFT 0x6
+#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL_MASK 0x80
+#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL__SHIFT 0x7
+#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL_MASK 0x100
+#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL__SHIFT 0x8
+#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK 0x200
+#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT 0x9
+#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK 0x400
+#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT 0xa
+#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK 0x800
+#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT 0xb
+#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK 0x1000
+#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT 0xc
+#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL_MASK 0x2000
+#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL__SHIFT 0xd
+#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL_MASK 0x4000
+#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL__SHIFT 0xe
+#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL_MASK 0x8000
+#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL__SHIFT 0xf
+#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL_MASK 0x10000
+#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL__SHIFT 0x10
+#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x20000
+#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x11
+#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x40000
+#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x12
+#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80000
+#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x13
+#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x100000
+#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x14
+#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x200000
+#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x15
+#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400000
+#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x16
+#define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x1
+#define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x0
+#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x2
+#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
+#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x4
+#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
+#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x8
+#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
+#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x10
+#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
+#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL_MASK 0x20
+#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL__SHIFT 0x5
+#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL_MASK 0x40
+#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL__SHIFT 0x6
+#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL_MASK 0x80
+#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL__SHIFT 0x7
+#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL_MASK 0x100
+#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL__SHIFT 0x8
+#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x200
+#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x9
+#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x400
+#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0xa
+#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x800
+#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0xb
+#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x1000
+#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0xc
+#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x2000
+#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0xd
+#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x4000
+#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xe
+#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x8000
+#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0xf
+#define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x1
+#define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x0
+#define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x2
+#define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x1
+#define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x4
+#define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x2
+#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x8
+#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x3
+#define MC_HUB_WRRET_STATUS__MCDS_AVAIL_MASK 0x10
+#define MC_HUB_WRRET_STATUS__MCDS_AVAIL__SHIFT 0x4
+#define MC_HUB_WRRET_STATUS__MCDT_AVAIL_MASK 0x20
+#define MC_HUB_WRRET_STATUS__MCDT_AVAIL__SHIFT 0x5
+#define MC_HUB_WRRET_STATUS__MCDU_AVAIL_MASK 0x40
+#define MC_HUB_WRRET_STATUS__MCDU_AVAIL__SHIFT 0x6
+#define MC_HUB_WRRET_STATUS__MCDV_AVAIL_MASK 0x80
+#define MC_HUB_WRRET_STATUS__MCDV_AVAIL__SHIFT 0x7
+#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x1
+#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x0
+#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x4
+#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x2
+#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x8
+#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x3
+#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
+#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
+#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x20
+#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x5
+#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x40
+#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x6
+#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x80
+#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x7
+#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x100
+#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x8
+#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE_MASK 0x200
+#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE__SHIFT 0x9
+#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE_MASK 0x400
+#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE__SHIFT 0xa
+#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE_MASK 0x800
+#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE__SHIFT 0xb
+#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE_MASK 0x1000
+#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE__SHIFT 0xc
+#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x2000
+#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0xd
+#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x1fc000
+#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0xe
+#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x200000
+#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x15
+#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x400000
+#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x16
+#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x800000
+#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x17
+#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE_MASK 0x1000000
+#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE__SHIFT 0x18
+#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE_MASK 0x2000000
+#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE__SHIFT 0x19
+#define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE_MASK 0x4000000
+#define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE__SHIFT 0x1a
+#define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD_MASK 0x78000000
+#define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD__SHIFT 0x1b
+#define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x1
+#define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x0
+#define MC_HUB_WRRET_CNTL__BP_MASK 0x1ffffe
+#define MC_HUB_WRRET_CNTL__BP__SHIFT 0x1
+#define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x200000
+#define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x15
+#define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000
+#define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x16
+#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000
+#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x1e
+#define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000
+#define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x1f
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
+#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
+#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
+#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
+#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
+#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
+#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
+#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
+#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
+#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
+#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
+#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
+#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
+#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
+#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
+#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
+#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
+#define MC_HUB_WDP_CREDITS__VM0_MASK 0xff
+#define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS__VM1_MASK 0xff00
+#define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x8
+#define MC_HUB_WDP_CREDITS__STOR0_MASK 0xff0000
+#define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x10
+#define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000
+#define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x18
+#define MC_HUB_WDP_CREDITS2__STOR0_PRI_MASK 0xff
+#define MC_HUB_WDP_CREDITS2__STOR0_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS2__STOR1_PRI_MASK 0xff00
+#define MC_HUB_WDP_CREDITS2__STOR1_PRI__SHIFT 0x8
+#define MC_HUB_WDP_CREDITS2__VM2_MASK 0xff0000
+#define MC_HUB_WDP_CREDITS2__VM2__SHIFT 0x10
+#define MC_HUB_WDP_CREDITS2__VM3_MASK 0xff000000
+#define MC_HUB_WDP_CREDITS2__VM3__SHIFT 0x18
+#define MC_HUB_WDP_GBL0__MAXBURST_MASK 0xf
+#define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x0
+#define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0xf0
+#define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x4
+#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0xff00
+#define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x8
+#define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x10000
+#define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x10
+#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI_MASK 0x1fe0000
+#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x11
+#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_URG_MASK 0xfe000000
+#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_URG__SHIFT 0x19
+#define MC_HUB_WDP_GBL1__MAXBURST_MASK 0xf
+#define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x0
+#define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0xf0
+#define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x4
+#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0xff00
+#define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x8
+#define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x10000
+#define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x10
+#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI_MASK 0x1fe0000
+#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x11
+#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_URG_MASK 0xfe000000
+#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_URG__SHIFT 0x19
+#define MC_HUB_WDP_CREDITS3__STOR0_URG_MASK 0xff
+#define MC_HUB_WDP_CREDITS3__STOR0_URG__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS3__STOR1_URG_MASK 0xff00
+#define MC_HUB_WDP_CREDITS3__STOR1_URG__SHIFT 0x8
+#define MC_HUB_RDREQ_CREDITS__VM0_MASK 0xff
+#define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x0
+#define MC_HUB_RDREQ_CREDITS__VM1_MASK 0xff00
+#define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x8
+#define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0xff0000
+#define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x10
+#define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000
+#define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x18
+#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI_MASK 0xff
+#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI__SHIFT 0x0
+#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0xff00
+#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x8
+#define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x3f
+#define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x0
+#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x3f0000
+#define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x10
+#define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000
+#define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x18
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x1
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x0
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x2
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x1
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x4
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x2
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x8
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x3
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ_MASK 0x10
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ__SHIFT 0x4
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE_MASK 0x20
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE__SHIFT 0x5
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ_MASK 0x40
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ__SHIFT 0x6
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE_MASK 0x80
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE__SHIFT 0x7
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x100
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x8
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x200
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x9
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x400
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0xa
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x800
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0xb
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x1000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0xc
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x2000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0xd
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x4000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0xe
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x8000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0xf
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x10000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x10
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x20000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x11
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x40000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x12
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x80000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x13
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x100000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x14
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x200000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x15
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ_MASK 0x400000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ__SHIFT 0x16
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE_MASK 0x800000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE__SHIFT 0x17
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ_MASK 0x1000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ__SHIFT 0x18
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE_MASK 0x2000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE__SHIFT 0x19
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ_MASK 0x4000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ__SHIFT 0x1a
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE_MASK 0x8000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT 0x1b
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ_MASK 0x10000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ__SHIFT 0x1c
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE_MASK 0x20000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE__SHIFT 0x1d
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ_MASK 0x40000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ__SHIFT 0x1e
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE_MASK 0x80000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE__SHIFT 0x1f
+#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x3
+#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x7c
+#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x2
+#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE_MASK 0x3
+#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT_MASK 0x7c
+#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT__SHIFT 0x2
+#define MC_HUB_WDP_BYPASS_GBL0__ENABLE_MASK 0x1
+#define MC_HUB_WDP_BYPASS_GBL0__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_BYPASS_GBL0__CID1_MASK 0x1fe
+#define MC_HUB_WDP_BYPASS_GBL0__CID1__SHIFT 0x1
+#define MC_HUB_WDP_BYPASS_GBL0__CID2_MASK 0x1fe00
+#define MC_HUB_WDP_BYPASS_GBL0__CID2__SHIFT 0x9
+#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME_MASK 0xfe0000
+#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME__SHIFT 0x11
+#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME_MASK 0x7f000000
+#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME__SHIFT 0x18
+#define MC_HUB_WDP_BYPASS_GBL1__ENABLE_MASK 0x1
+#define MC_HUB_WDP_BYPASS_GBL1__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_BYPASS_GBL1__CID1_MASK 0x1fe
+#define MC_HUB_WDP_BYPASS_GBL1__CID1__SHIFT 0x1
+#define MC_HUB_WDP_BYPASS_GBL1__CID2_MASK 0x1fe00
+#define MC_HUB_WDP_BYPASS_GBL1__CID2__SHIFT 0x9
+#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME_MASK 0xfe0000
+#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME__SHIFT 0x11
+#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME_MASK 0x7f000000
+#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME__SHIFT 0x18
+#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_BYPASS_GBL0__CID1_MASK 0x1fe
+#define MC_HUB_RDREQ_BYPASS_GBL0__CID1__SHIFT 0x1
+#define MC_HUB_RDREQ_BYPASS_GBL0__CID2_MASK 0x1fe00
+#define MC_HUB_RDREQ_BYPASS_GBL0__CID2__SHIFT 0x9
+#define MC_HUB_WDP_SH2__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SH2__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SH2__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SH2__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SH2__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SH2__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SH2__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SH2__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SH2__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SH2__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SH2__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SH2__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_SH2__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_SH2__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_SH3__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SH3__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SH3__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SH3__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SH3__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SH3__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SH3__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SH3__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SH3__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SH3__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SH3__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SH3__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_SH3__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_SH3__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC_MASK 0x1
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC__SHIFT 0x0
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC_MASK 0x2
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC__SHIFT 0x1
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC_MASK 0x4
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC__SHIFT 0x2
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC_MASK 0x8
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC__SHIFT 0x3
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC_MASK 0x10
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC__SHIFT 0x4
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC_MASK 0x20
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC__SHIFT 0x5
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC_MASK 0x40
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC__SHIFT 0x6
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC_MASK 0x80
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC__SHIFT 0x7
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC_MASK 0x100
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC__SHIFT 0x8
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC_MASK 0x200
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC__SHIFT 0x9
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC_MASK 0x400
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC__SHIFT 0xa
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC_MASK 0x800
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC__SHIFT 0xb
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC_MASK 0x1000
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC__SHIFT 0xc
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC_MASK 0x2000
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC__SHIFT 0xd
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC_MASK 0x4000
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC__SHIFT 0xe
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC_MASK 0x8000
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC__SHIFT 0xf
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_READ_MASK 0x10000
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_READ__SHIFT 0x10
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_WRITE_MASK 0x20000
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_WRITE__SHIFT 0x11
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_ATOMIC_MASK 0x40000
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_ATOMIC__SHIFT 0x12
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_READ_MASK 0x80000
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_READ__SHIFT 0x13
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_WRITE_MASK 0x100000
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_WRITE__SHIFT 0x14
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_ATOMIC_MASK 0x200000
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_ATOMIC__SHIFT 0x15
+#define MC_HUB_WDP_VIN0__ENABLE_MASK 0x1
+#define MC_HUB_WDP_VIN0__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_VIN0__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_VIN0__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_VIN0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_VIN0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_VIN0__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_VIN0__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_VIN0__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_VIN0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_VIN0__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_VIN0__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_VIN0__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_VIN0__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_VIN0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_VIN0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_VIN0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_VIN0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_VIN0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_VIN0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDW__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDW__MED_CREDITS_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDW__MED_CREDITS__SHIFT 0x19
+#define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDX__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDX__MED_CREDITS_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDX__MED_CREDITS__SHIFT 0x19
+#define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDY__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDY__MED_CREDITS_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDY__MED_CREDITS__SHIFT 0x19
+#define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDZ__MED_CREDITS_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDZ__MED_CREDITS__SHIFT 0x19
+#define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x7f
+#define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x0
+#define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL_MASK 0x80
+#define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL__SHIFT 0x7
+#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x7f00
+#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x8
+#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0xff
+#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x0
+#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI_MASK 0xff00
+#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x8
+#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0xff
+#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x0
+#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI_MASK 0xff00
+#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x8
+#define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_SDMA0__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_SDMA0__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_SDMA0__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_SDMA0__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_SDMA0__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_SDMA0__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_SDMA0__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_SDMA0__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_SDMA1__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_SDMA1__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_SDMA1__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_SDMA1__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_SDMA1__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_SDMA1__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_SDMA1__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_SDMA1__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_VCE0__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_VCE0__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_VCE0__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_VCE0__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_VCE0__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_VCE0__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_VCE0__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_VCE0__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_VCE0__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_VCE0__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_VCE0__VM_BYPASS_MASK 0x10000
+#define MC_HUB_RDREQ_VCE0__VM_BYPASS__SHIFT 0x10
+#define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_UMC__VM_BYPASS_MASK 0x10000
+#define MC_HUB_RDREQ_UMC__VM_BYPASS__SHIFT 0x10
+#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x10000
+#define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x10
+#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_RDREQ_TLS__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_TLS__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_TLS__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_TLS__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_TLS__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_TLS__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_TLS__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_TLS__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_TLS__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_TLS__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_TLS__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_TLS__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_TLS__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_TLS__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_TLS__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_TLS__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_TLS__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_TLS__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_VCEU0__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_VCEU0__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_VCEU0__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_VCEU0__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_VCEU0__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_VCEU0__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_VCEU0__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_VCEU0__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_VCEU0__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_VCEU0__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_MCDW__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_MCDX__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_MCDY__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x3
+#define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x1fc
+#define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x2
+#define MC_HUB_WDP_SDMA1__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SDMA1__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SDMA1__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SDMA1__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SDMA1__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SDMA1__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SDMA1__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SDMA1__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SDMA1__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SDMA1__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_SDMA1__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_SDMA1__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_SH0__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SH0__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SH0__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_SH0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_SH0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_MCIF__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_MCIF__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_MCIF__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_VCE0__ENABLE_MASK 0x1
+#define MC_HUB_WDP_VCE0__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_VCE0__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_VCE0__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_VCE0__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_VCE0__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_VCE0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_VCE0__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_VCE0__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_VCE0__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_VCE0__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_VCE0__VM_BYPASS_MASK 0x10000
+#define MC_HUB_WDP_VCE0__VM_BYPASS__SHIFT 0x10
+#define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_VCE0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x40000
+#define MC_HUB_WDP_VCE0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x12
+#define MC_HUB_WDP_XDP__ENABLE_MASK 0x1
+#define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_XDP__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_XDP__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_XDP__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_XDP__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_IH__ENABLE_MASK 0x1
+#define MC_HUB_WDP_IH__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_IH__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_IH__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_IH__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_IH__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_IH__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_RLC__ENABLE_MASK 0x1
+#define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_RLC__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_RLC__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_RLC__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_RLC__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_SEM__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SEM__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SEM__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_SEM__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_SEM__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_SMU__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SMU__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SMU__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_SMU__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_SMU__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_SH1__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SH1__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SH1__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_SH1__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_SH1__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_UMC__ENABLE_MASK 0x1
+#define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_UMC__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_UMC__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_UMC__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_UMC__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_UVD__ENABLE_MASK 0x1
+#define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_UVD__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_UVD__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x10000
+#define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x10
+#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_UVD__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x40000
+#define MC_HUB_WDP_UVD__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x12
+#define MC_HUB_WDP_HDP__ENABLE_MASK 0x1
+#define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_HDP__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_HDP__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_HDP__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_HDP__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_SDMA0__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SDMA0__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SDMA0__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SDMA0__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SDMA0__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SDMA0__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SDMA0__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SDMA0__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SDMA0__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SDMA0__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_SDMA0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_SDMA0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WDP_VCEU0__ENABLE_MASK 0x1
+#define MC_HUB_WDP_VCEU0__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_VCEU0__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_VCEU0__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_VCEU0__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_VCEU0__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_VCEU0__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_VCEU0__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_VCEU0__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_VCEU0__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_VCEU0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_VCEU0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x1
+#define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_XDMAM__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_XDMAM__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_XDMA__ENABLE_MASK 0x1
+#define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_XDMA__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_XDMA__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_ACPG__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_ACPG__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_ACPG__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_ACPG__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_ACPG__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_ACPG__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_ACPG__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_ACPG__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_ACPG__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_ACPG__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_RDREQ_ACPO__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_ACPO__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_ACPO__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_ACPO__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_ACPO__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_ACPO__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_ACPO__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_ACPO__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_ACPO__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_ACPO__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_RDREQ_SAMMSP__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_SAMMSP__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_SAMMSP__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_SAMMSP__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_SAMMSP__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_SAMMSP__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_SAMMSP__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_SAMMSP__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_VP8__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_VP8__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_VP8__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_VP8__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_VP8__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_VP8__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_VP8__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_VP8__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_VP8__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_VP8__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_VP8U__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_VP8U__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_VP8U__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_VP8U__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_VP8U__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_VP8U__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_VP8U__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_VP8U__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_VP8U__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_VP8U__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_VP8U__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_VP8U__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_VP8U__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_VP8U__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_ACPG__ENABLE_MASK 0x1
+#define MC_HUB_WDP_ACPG__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_ACPG__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_ACPG__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_ACPG__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_ACPG__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_ACPG__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_ACPG__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_ACPG__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_ACPG__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_ACPG__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_ACPG__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_ACPG__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE_MASK 0x40000
+#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE__SHIFT 0x12
+#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE_MASK 0x80000
+#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE__SHIFT 0x13
+#define MC_HUB_WDP_ACPG__STALL_THRESHOLD_MASK 0x3f00000
+#define MC_HUB_WDP_ACPG__STALL_THRESHOLD__SHIFT 0x14
+#define MC_HUB_WDP_ACPO__ENABLE_MASK 0x1
+#define MC_HUB_WDP_ACPO__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_ACPO__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_ACPO__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_ACPO__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_ACPO__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_ACPO__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_ACPO__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_ACPO__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_ACPO__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_ACPO__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_ACPO__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_ACPO__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE_MASK 0x40000
+#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE__SHIFT 0x12
+#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE_MASK 0x80000
+#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE__SHIFT 0x13
+#define MC_HUB_WDP_ACPO__STALL_THRESHOLD_MASK 0x3f00000
+#define MC_HUB_WDP_ACPO__STALL_THRESHOLD__SHIFT 0x14
+#define MC_HUB_WDP_SAMMSP__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SAMMSP__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SAMMSP__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SAMMSP__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SAMMSP__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SAMMSP__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SAMMSP__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SAMMSP__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SAMMSP__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SAMMSP__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_SAMMSP__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_SAMMSP__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_VP8__ENABLE_MASK 0x1
+#define MC_HUB_WDP_VP8__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_VP8__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_VP8__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_VP8__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_VP8__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_VP8__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_VP8__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_VP8__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_VP8__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_VP8__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_VP8__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_VP8__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_VP8__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_VP8U__ENABLE_MASK 0x1
+#define MC_HUB_WDP_VP8U__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_VP8U__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_VP8U__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_VP8U__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_VP8U__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_VP8U__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_VP8U__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_VP8U__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_VP8U__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_VP8U__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_VP8U__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_VP8U__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_VP8U__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_VP8U__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_VP8U__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_VP8U__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_RDREQ_ISP_SPM__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_ISP_SPM__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_ISP_SPM__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_ISP_SPM__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_ISP_SPM__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_ISP_SPM__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_RDREQ_ISP_MPM__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_ISP_MPM__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_ISP_MPM__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_ISP_MPM__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_ISP_MPM__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_ISP_MPM__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_RDREQ_ISP_CCPU__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_ISP_CCPU__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_WDP_ISP_SPM__ENABLE_MASK 0x1
+#define MC_HUB_WDP_ISP_SPM__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_ISP_SPM__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_ISP_SPM__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_ISP_SPM__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_ISP_SPM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_ISP_SPM__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_ISP_SPM__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_ISP_SPM__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_ISP_SPM__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE_MASK 0x40000
+#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x12
+#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x80000
+#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x13
+#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD_MASK 0x3f00000
+#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD__SHIFT 0x14
+#define MC_HUB_WDP_ISP_MPS__ENABLE_MASK 0x1
+#define MC_HUB_WDP_ISP_MPS__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_ISP_MPS__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_ISP_MPS__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_ISP_MPS__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_ISP_MPS__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_ISP_MPS__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_ISP_MPS__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_ISP_MPS__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_ISP_MPS__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE_MASK 0x40000
+#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE__SHIFT 0x12
+#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE_MASK 0x80000
+#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE__SHIFT 0x13
+#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD_MASK 0x3f00000
+#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD__SHIFT 0x14
+#define MC_HUB_WDP_ISP_MPM__ENABLE_MASK 0x1
+#define MC_HUB_WDP_ISP_MPM__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_ISP_MPM__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_ISP_MPM__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_ISP_MPM__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_ISP_MPM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_ISP_MPM__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_ISP_MPM__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_ISP_MPM__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_ISP_MPM__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE_MASK 0x40000
+#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x12
+#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x80000
+#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x13
+#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD_MASK 0x3f00000
+#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD__SHIFT 0x14
+#define MC_HUB_WDP_ISP_CCPU__ENABLE_MASK 0x1
+#define MC_HUB_WDP_ISP_CCPU__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_ISP_CCPU__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_ISP_CCPU__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_ISP_CCPU__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_ISP_CCPU__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_ISP_CCPU__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_ISP_CCPU__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_ISP_CCPU__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_ISP_CCPU__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE_MASK 0x40000
+#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x12
+#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x80000
+#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x13
+#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD_MASK 0x3f00000
+#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x14
+#define MC_HUB_RDREQ_MCDS__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDS__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDS__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDS__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDS__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDS__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDS__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDS__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDS__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDS__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDS__MED_CREDITS_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDS__MED_CREDITS__SHIFT 0x19
+#define MC_HUB_RDREQ_MCDT__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDT__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDT__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDT__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDT__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDT__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDT__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDT__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDT__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDT__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDT__MED_CREDITS_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDT__MED_CREDITS__SHIFT 0x19
+#define MC_HUB_RDREQ_MCDU__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDU__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDU__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDU__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDU__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDU__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDU__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDU__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDU__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDU__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDU__MED_CREDITS_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDU__MED_CREDITS__SHIFT 0x19
+#define MC_HUB_RDREQ_MCDV__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDV__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDV__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDV__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDV__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDV__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDV__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDV__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDV__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDV__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDV__MED_CREDITS_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDV__MED_CREDITS__SHIFT 0x19
+#define MC_HUB_WDP_MCDS__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDS__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDS__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDS__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDS__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDS__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDS__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDS__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDS__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDS__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDS__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDS__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDS__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDS__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_MCDT__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDT__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDT__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDT__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDT__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDT__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDT__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDT__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDT__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDT__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDT__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDT__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDT__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDT__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_MCDU__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDU__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDU__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDU__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDU__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDU__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDU__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDU__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDU__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDU__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDU__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDU__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDU__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDU__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_MCDV__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDV__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDV__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDV__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDV__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDV__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDV__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDV__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDV__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDV__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDV__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDV__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDV__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDV__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WRRET_MCDS__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDS__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDS__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDS__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WRRET_MCDT__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDT__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDT__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDT__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WRRET_MCDU__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDU__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDU__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDU__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WRRET_MCDV__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDV__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDV__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDV__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_CREDITS_MCDW__WR_URG_MASK 0x1fc000
+#define MC_HUB_WDP_CREDITS_MCDW__WR_URG__SHIFT 0xe
+#define MC_HUB_WDP_CREDITS_MCDW__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
+#define MC_HUB_WDP_CREDITS_MCDW__WR_URG_STALL_THRESHOLD__SHIFT 0x15
+#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_CREDITS_MCDX__WR_URG_MASK 0x1fc000
+#define MC_HUB_WDP_CREDITS_MCDX__WR_URG__SHIFT 0xe
+#define MC_HUB_WDP_CREDITS_MCDX__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
+#define MC_HUB_WDP_CREDITS_MCDX__WR_URG_STALL_THRESHOLD__SHIFT 0x15
+#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_CREDITS_MCDY__WR_URG_MASK 0x1fc000
+#define MC_HUB_WDP_CREDITS_MCDY__WR_URG__SHIFT 0xe
+#define MC_HUB_WDP_CREDITS_MCDY__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
+#define MC_HUB_WDP_CREDITS_MCDY__WR_URG_STALL_THRESHOLD__SHIFT 0x15
+#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_CREDITS_MCDZ__WR_URG_MASK 0x1fc000
+#define MC_HUB_WDP_CREDITS_MCDZ__WR_URG__SHIFT 0xe
+#define MC_HUB_WDP_CREDITS_MCDZ__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
+#define MC_HUB_WDP_CREDITS_MCDZ__WR_URG_STALL_THRESHOLD__SHIFT 0x15
+#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_CREDITS_MCDS__WR_URG_MASK 0x1fc000
+#define MC_HUB_WDP_CREDITS_MCDS__WR_URG__SHIFT 0xe
+#define MC_HUB_WDP_CREDITS_MCDS__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
+#define MC_HUB_WDP_CREDITS_MCDS__WR_URG_STALL_THRESHOLD__SHIFT 0x15
+#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_CREDITS_MCDT__WR_URG_MASK 0x1fc000
+#define MC_HUB_WDP_CREDITS_MCDT__WR_URG__SHIFT 0xe
+#define MC_HUB_WDP_CREDITS_MCDT__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
+#define MC_HUB_WDP_CREDITS_MCDT__WR_URG_STALL_THRESHOLD__SHIFT 0x15
+#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_CREDITS_MCDU__WR_URG_MASK 0x1fc000
+#define MC_HUB_WDP_CREDITS_MCDU__WR_URG__SHIFT 0xe
+#define MC_HUB_WDP_CREDITS_MCDU__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
+#define MC_HUB_WDP_CREDITS_MCDU__WR_URG_STALL_THRESHOLD__SHIFT 0x15
+#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_CREDITS_MCDV__WR_URG_MASK 0x1fc000
+#define MC_HUB_WDP_CREDITS_MCDV__WR_URG__SHIFT 0xe
+#define MC_HUB_WDP_CREDITS_MCDV__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
+#define MC_HUB_WDP_CREDITS_MCDV__WR_URG_STALL_THRESHOLD__SHIFT 0x15
+#define MC_HUB_WDP_BP2__RDRET_MASK 0xffff
+#define MC_HUB_WDP_BP2__RDRET__SHIFT 0x0
+#define MC_HUB_RDREQ_VCE1__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_VCE1__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_VCE1__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_VCE1__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_VCE1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_VCE1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_VCE1__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_VCE1__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_VCE1__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_VCE1__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_VCE1__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_VCE1__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_VCE1__VM_BYPASS_MASK 0x10000
+#define MC_HUB_RDREQ_VCE1__VM_BYPASS__SHIFT 0x10
+#define MC_HUB_RDREQ_VCE1__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_RDREQ_VCE1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_RDREQ_VCEU1__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_VCEU1__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_VCEU1__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_VCEU1__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_VCEU1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_VCEU1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_VCEU1__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_VCEU1__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_VCEU1__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_VCEU1__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_VCEU1__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_VCEU1__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_VCEU1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_VCEU1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_VCE1__ENABLE_MASK 0x1
+#define MC_HUB_WDP_VCE1__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_VCE1__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_VCE1__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_VCE1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_VCE1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_VCE1__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_VCE1__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_VCE1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_VCE1__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_VCE1__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_VCE1__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_VCE1__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_VCE1__VM_BYPASS_MASK 0x10000
+#define MC_HUB_WDP_VCE1__VM_BYPASS__SHIFT 0x10
+#define MC_HUB_WDP_VCE1__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_VCE1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_VCE1__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x40000
+#define MC_HUB_WDP_VCE1__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x12
+#define MC_HUB_WDP_VCEU1__ENABLE_MASK 0x1
+#define MC_HUB_WDP_VCEU1__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_VCEU1__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_VCEU1__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_VCEU1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_VCEU1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_VCEU1__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_VCEU1__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_VCEU1__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_VCEU1__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_VCEU1__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_VCEU1__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_VCEU1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_VCEU1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_VCEU1__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_VCEU1__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x8000
+#define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0xf
+#define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x10000
+#define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x10
+#define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x20000
+#define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x11
+#define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0xff
+#define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x0
+#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0xff00
+#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x8
+#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0xff
+#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x0
+#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0xfff00
+#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x8
+#define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000
+#define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x14
+#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0xff
+#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0
+#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0xff00
+#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8
+#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0xff
+#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x0
+#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0xff00
+#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x8
+#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0xff0000
+#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x10
+#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0xff
+#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x0
+#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0xff00
+#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x8
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
+#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x1
+#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x0
+#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x6
+#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x1
+#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x78
+#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x3
+#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x80
+#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x7
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
+#define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0xff
+#define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x0
+#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x100
+#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x8
+#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x600
+#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x9
+#define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x1800
+#define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xb
+#define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x2000
+#define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd
+#define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0xff
+#define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x0
+#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x300
+#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x8
+#define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0xc00
+#define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xa
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x3
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x4
+#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2
+#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x8
+#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3
+#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x10
+#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4
+#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x1e0
+#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x3e00
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x7c000
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0xf80000
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18
+#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffff
+#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0
+#define MC_RPB_CID_QUEUE_EX__START_MASK 0x1
+#define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x0
+#define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x3e
+#define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1
+#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0xffff
+#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0
+#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000
+#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10
+#define MC_RPB_TCI_CNTL__TCI_ENABLE_MASK 0x1
+#define MC_RPB_TCI_CNTL__TCI_ENABLE__SHIFT 0x0
+#define MC_RPB_TCI_CNTL__TCI_POLICY_MASK 0x6
+#define MC_RPB_TCI_CNTL__TCI_POLICY__SHIFT 0x1
+#define MC_RPB_TCI_CNTL__TCI_VOL_MASK 0x8
+#define MC_RPB_TCI_CNTL__TCI_VOL__SHIFT 0x3
+#define MC_RPB_TCI_CNTL__TCI_VMID_MASK 0xf0
+#define MC_RPB_TCI_CNTL__TCI_VMID__SHIFT 0x4
+#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS_MASK 0xff00
+#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS__SHIFT 0x8
+#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES_MASK 0xff0000
+#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES__SHIFT 0x10
+#define MC_RPB_TCI_CNTL__TCI_MAX_READS_MASK 0xff000000
+#define MC_RPB_TCI_CNTL__TCI_MAX_READS__SHIFT 0x18
+#define MC_RPB_TCI_CNTL2__TCI_POLICY_MASK 0x1
+#define MC_RPB_TCI_CNTL2__TCI_POLICY__SHIFT 0x0
+#define MC_RPB_TCI_CNTL2__TCI_MTYPE_MASK 0x6
+#define MC_RPB_TCI_CNTL2__TCI_MTYPE__SHIFT 0x1
+#define MC_RPB_TCI_CNTL2__TCI_SNOOP_MASK 0x8
+#define MC_RPB_TCI_CNTL2__TCI_SNOOP__SHIFT 0x3
+#define MC_RPB_TCI_CNTL2__TCI_PHYSICAL_MASK 0x10
+#define MC_RPB_TCI_CNTL2__TCI_PHYSICAL__SHIFT 0x4
+#define MC_RPB_TCI_CNTL2__TCI_PERF_CNTR_EN_MASK 0x20
+#define MC_RPB_TCI_CNTL2__TCI_PERF_CNTR_EN__SHIFT 0x5
+#define MC_RPB_TCI_CNTL2__TCI_EXE_MASK 0x40
+#define MC_RPB_TCI_CNTL2__TCI_EXE__SHIFT 0x6
+#define MC_SHARED_CHMAP__CHAN0_MASK 0xf
+#define MC_SHARED_CHMAP__CHAN0__SHIFT 0x0
+#define MC_SHARED_CHMAP__CHAN1_MASK 0xf0
+#define MC_SHARED_CHMAP__CHAN1__SHIFT 0x4
+#define MC_SHARED_CHMAP__CHAN2_MASK 0xf00
+#define MC_SHARED_CHMAP__CHAN2__SHIFT 0x8
+#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000
+#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc
+#define MC_SHARED_CHMAP__CHAN3_MASK 0xf0000
+#define MC_SHARED_CHMAP__CHAN3__SHIFT 0x10
+#define MC_SHARED_CHMAP__CHAN4_MASK 0xf00000
+#define MC_SHARED_CHMAP__CHAN4__SHIFT 0x14
+#define MC_SHARED_CHREMAP__CHAN0_MASK 0xf
+#define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x0
+#define MC_SHARED_CHREMAP__CHAN1_MASK 0xf0
+#define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x4
+#define MC_SHARED_CHREMAP__CHAN2_MASK 0xf00
+#define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x8
+#define MC_SHARED_CHREMAP__CHAN3_MASK 0xf000
+#define MC_SHARED_CHREMAP__CHAN3__SHIFT 0xc
+#define MC_SHARED_CHREMAP__CHAN4_MASK 0xf0000
+#define MC_SHARED_CHREMAP__CHAN4__SHIFT 0x10
+#define MC_SHARED_CHREMAP__CHAN5_MASK 0xf00000
+#define MC_SHARED_CHREMAP__CHAN5__SHIFT 0x14
+#define MC_SHARED_CHREMAP__CHAN6_MASK 0xf000000
+#define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x18
+#define MC_SHARED_CHREMAP__CHAN7_MASK 0xf0000000
+#define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x1c
+#define MC_RD_GRP_GFX__CP_MASK 0xf
+#define MC_RD_GRP_GFX__CP__SHIFT 0x0
+#define MC_RD_GRP_GFX__SH_MASK 0xf0
+#define MC_RD_GRP_GFX__SH__SHIFT 0x4
+#define MC_RD_GRP_GFX__TLS_MASK 0xf00
+#define MC_RD_GRP_GFX__TLS__SHIFT 0x8
+#define MC_RD_GRP_GFX__ACPG_MASK 0xf000
+#define MC_RD_GRP_GFX__ACPG__SHIFT 0xc
+#define MC_RD_GRP_GFX__ACPO_MASK 0xf0000
+#define MC_RD_GRP_GFX__ACPO__SHIFT 0x10
+#define MC_RD_GRP_GFX__XDMAM_MASK 0xf00000
+#define MC_RD_GRP_GFX__XDMAM__SHIFT 0x14
+#define MC_RD_GRP_GFX__ISP_MASK 0xf000000
+#define MC_RD_GRP_GFX__ISP__SHIFT 0x18
+#define MC_RD_GRP_GFX__VP8_MASK 0xf0000000
+#define MC_RD_GRP_GFX__VP8__SHIFT 0x1c
+#define MC_WR_GRP_GFX__VIN0_MASK 0xf
+#define MC_WR_GRP_GFX__VIN0__SHIFT 0x0
+#define MC_WR_GRP_GFX__SH_MASK 0xf0
+#define MC_WR_GRP_GFX__SH__SHIFT 0x4
+#define MC_WR_GRP_GFX__ACPG_MASK 0xf00
+#define MC_WR_GRP_GFX__ACPG__SHIFT 0x8
+#define MC_WR_GRP_GFX__ACPO_MASK 0xf000
+#define MC_WR_GRP_GFX__ACPO__SHIFT 0xc
+#define MC_WR_GRP_GFX__ISP_MASK 0xf0000
+#define MC_WR_GRP_GFX__ISP__SHIFT 0x10
+#define MC_WR_GRP_GFX__VP8_MASK 0xf00000
+#define MC_WR_GRP_GFX__VP8__SHIFT 0x14
+#define MC_WR_GRP_GFX__XDMA_MASK 0xf000000
+#define MC_WR_GRP_GFX__XDMA__SHIFT 0x18
+#define MC_WR_GRP_GFX__XDMAM_MASK 0xf0000000
+#define MC_WR_GRP_GFX__XDMAM__SHIFT 0x1c
+#define MC_RD_GRP_SYS__RLC_MASK 0xf
+#define MC_RD_GRP_SYS__RLC__SHIFT 0x0
+#define MC_RD_GRP_SYS__VMC_MASK 0xf0
+#define MC_RD_GRP_SYS__VMC__SHIFT 0x4
+#define MC_RD_GRP_SYS__SDMA1_MASK 0xf00
+#define MC_RD_GRP_SYS__SDMA1__SHIFT 0x8
+#define MC_RD_GRP_SYS__DMIF_MASK 0xf000
+#define MC_RD_GRP_SYS__DMIF__SHIFT 0xc
+#define MC_RD_GRP_SYS__MCIF_MASK 0xf0000
+#define MC_RD_GRP_SYS__MCIF__SHIFT 0x10
+#define MC_RD_GRP_SYS__SMU_MASK 0xf00000
+#define MC_RD_GRP_SYS__SMU__SHIFT 0x14
+#define MC_RD_GRP_SYS__VCE0_MASK 0xf000000
+#define MC_RD_GRP_SYS__VCE0__SHIFT 0x18
+#define MC_RD_GRP_SYS__VCE1_MASK 0xf0000000
+#define MC_RD_GRP_SYS__VCE1__SHIFT 0x1c
+#define MC_WR_GRP_SYS__IH_MASK 0xf
+#define MC_WR_GRP_SYS__IH__SHIFT 0x0
+#define MC_WR_GRP_SYS__MCIF_MASK 0xf0
+#define MC_WR_GRP_SYS__MCIF__SHIFT 0x4
+#define MC_WR_GRP_SYS__RLC_MASK 0xf00
+#define MC_WR_GRP_SYS__RLC__SHIFT 0x8
+#define MC_WR_GRP_SYS__SAMMSP_MASK 0xf000
+#define MC_WR_GRP_SYS__SAMMSP__SHIFT 0xc
+#define MC_WR_GRP_SYS__SMU_MASK 0xf0000
+#define MC_WR_GRP_SYS__SMU__SHIFT 0x10
+#define MC_WR_GRP_SYS__SDMA1_MASK 0xf00000
+#define MC_WR_GRP_SYS__SDMA1__SHIFT 0x14
+#define MC_WR_GRP_SYS__VCE0_MASK 0xf000000
+#define MC_WR_GRP_SYS__VCE0__SHIFT 0x18
+#define MC_WR_GRP_SYS__VCE1_MASK 0xf0000000
+#define MC_WR_GRP_SYS__VCE1__SHIFT 0x1c
+#define MC_RD_GRP_OTH__UVD_EXT0_MASK 0xf
+#define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x0
+#define MC_RD_GRP_OTH__SDMA0_MASK 0xf0
+#define MC_RD_GRP_OTH__SDMA0__SHIFT 0x4
+#define MC_RD_GRP_OTH__HDP_MASK 0xf00
+#define MC_RD_GRP_OTH__HDP__SHIFT 0x8
+#define MC_RD_GRP_OTH__SEM_MASK 0xf000
+#define MC_RD_GRP_OTH__SEM__SHIFT 0xc
+#define MC_RD_GRP_OTH__UMC_MASK 0xf0000
+#define MC_RD_GRP_OTH__UMC__SHIFT 0x10
+#define MC_RD_GRP_OTH__UVD_MASK 0xf00000
+#define MC_RD_GRP_OTH__UVD__SHIFT 0x14
+#define MC_RD_GRP_OTH__UVD_EXT1_MASK 0xf000000
+#define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x18
+#define MC_RD_GRP_OTH__SAMMSP_MASK 0xf0000000
+#define MC_RD_GRP_OTH__SAMMSP__SHIFT 0x1c
+#define MC_WR_GRP_OTH__UVD_EXT0_MASK 0xf
+#define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x0
+#define MC_WR_GRP_OTH__SDMA0_MASK 0xf0
+#define MC_WR_GRP_OTH__SDMA0__SHIFT 0x4
+#define MC_WR_GRP_OTH__HDP_MASK 0xf00
+#define MC_WR_GRP_OTH__HDP__SHIFT 0x8
+#define MC_WR_GRP_OTH__SEM_MASK 0xf000
+#define MC_WR_GRP_OTH__SEM__SHIFT 0xc
+#define MC_WR_GRP_OTH__UMC_MASK 0xf0000
+#define MC_WR_GRP_OTH__UMC__SHIFT 0x10
+#define MC_WR_GRP_OTH__UVD_MASK 0xf00000
+#define MC_WR_GRP_OTH__UVD__SHIFT 0x14
+#define MC_WR_GRP_OTH__XDP_MASK 0xf000000
+#define MC_WR_GRP_OTH__XDP__SHIFT 0x18
+#define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000
+#define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x1c
+#define MC_VM_FB_LOCATION__FB_BASE_MASK 0xffff
+#define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x0
+#define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000
+#define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x10
+#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x3ffff
+#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
+#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x3ffff
+#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
+#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x3ffff
+#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x3
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x0
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0xc
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x2
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x30
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x4
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0xc0
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x6
+#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x100
+#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x8
+#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x200
+#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x9
+#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x1
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x2
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x1
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x18
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x20
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x40
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
+#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x780
+#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
+#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x3ffff
+#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
+#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x3
+#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
+#define MC_SHARED_CHREMAP2__CHAN8_MASK 0xf
+#define MC_SHARED_CHREMAP2__CHAN8__SHIFT 0x0
+#define MC_SHARED_CHREMAP2__CHAN9_MASK 0xf0
+#define MC_SHARED_CHREMAP2__CHAN9__SHIFT 0x4
+#define MC_SHARED_CHREMAP2__CHAN10_MASK 0xf00
+#define MC_SHARED_CHREMAP2__CHAN10__SHIFT 0x8
+#define MC_SHARED_CHREMAP2__CHAN11_MASK 0xf000
+#define MC_SHARED_CHREMAP2__CHAN11__SHIFT 0xc
+#define MC_SHARED_CHREMAP2__CHAN12_MASK 0xf0000
+#define MC_SHARED_CHREMAP2__CHAN12__SHIFT 0x10
+#define MC_SHARED_CHREMAP2__CHAN13_MASK 0xf00000
+#define MC_SHARED_CHREMAP2__CHAN13__SHIFT 0x14
+#define MC_SHARED_CHREMAP2__CHAN14_MASK 0xf000000
+#define MC_SHARED_CHREMAP2__CHAN14__SHIFT 0x18
+#define MC_SHARED_CHREMAP2__CHAN15_MASK 0xf0000000
+#define MC_SHARED_CHREMAP2__CHAN15__SHIFT 0x1c
+#define MC_SHARED_VF_ENABLE__VF_ENABLE_MASK 0x1
+#define MC_SHARED_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0xffff
+#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000
+#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0xf
+#define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000
+#define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
+#define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
+#define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
+#define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
+#define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
+#define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
+#define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
+#define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
+#define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
+#define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
+#define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
+#define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
+#define MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40
+#define MC_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6
+#define MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80
+#define MC_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7
+#define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
+#define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
+#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800
+#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb
+#define MC_CONFIG_MCD__ARB0_WR_ENABLE_MASK 0x1000
+#define MC_CONFIG_MCD__ARB0_WR_ENABLE__SHIFT 0xc
+#define MC_CONFIG_MCD__ARB1_WR_ENABLE_MASK 0x2000
+#define MC_CONFIG_MCD__ARB1_WR_ENABLE__SHIFT 0xd
+#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000
+#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x1f
+#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
+#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
+#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
+#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
+#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
+#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
+#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
+#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
+#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
+#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
+#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
+#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
+#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40
+#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6
+#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80
+#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7
+#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
+#define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
+#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800
+#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb
+#define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000
+#define MC_CG_CONFIG_MCD__INDEX__SHIFT 0xd
+#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x3f
+#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
+#define MC_MEM_POWER_LS__LS_HOLD_MASK 0xfc0
+#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
+#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x7
+#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x0
+#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_SEQ_FREE_MASK 0x8
+#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_SEQ_FREE__SHIFT 0x3
+#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MCD_NUM_MASK 0xff0
+#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MCD_NUM__SHIFT 0x4
+#define MC_SHARED_BLACKOUT_CNTL__FREE_TIE_HIGH_MASK 0x1000
+#define MC_SHARED_BLACKOUT_CNTL__FREE_TIE_HIGH__SHIFT 0xc
+#define MC_SHARED_BLACKOUT_CNTL__SRBM_DUMMY_READ_RETURN_MASK 0x2000
+#define MC_SHARED_BLACKOUT_CNTL__SRBM_DUMMY_READ_RETURN__SHIFT 0xd
+#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MB_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MB_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MB_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MB_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x1
+#define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x1
+#define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x1
+#define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
+#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
+#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x1
+#define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x1
+#define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x1
+#define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x1
+#define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
+#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
+#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x1
+#define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
+#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
+#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
+#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
+#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
+#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
+#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
+#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
+#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_EXTRA__CMP0_MASK 0xff
+#define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x0
+#define MC_XPB_CLG_EXTRA__MSK0_MASK 0xff00
+#define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x8
+#define MC_XPB_CLG_EXTRA__VLD0_MASK 0x10000
+#define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x10
+#define MC_XPB_CLG_EXTRA__CMP1_MASK 0x1fe0000
+#define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x11
+#define MC_XPB_CLG_EXTRA__VLD1_MASK 0x2000000
+#define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x19
+#define MC_XPB_LB_ADDR__CMP0_MASK 0x3ff
+#define MC_XPB_LB_ADDR__CMP0__SHIFT 0x0
+#define MC_XPB_LB_ADDR__MASK0_MASK 0xffc00
+#define MC_XPB_LB_ADDR__MASK0__SHIFT 0xa
+#define MC_XPB_LB_ADDR__CMP1_MASK 0x3f00000
+#define MC_XPB_LB_ADDR__CMP1__SHIFT 0x14
+#define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000
+#define MC_XPB_LB_ADDR__MASK1__SHIFT 0x1a
+#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x3f
+#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x0
+#define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0xfc0
+#define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x6
+#define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x3f000
+#define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0xc
+#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x3f
+#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x0
+#define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0xfc0
+#define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x6
+#define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x3f000
+#define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0xc
+#define MC_XPB_WCB_STS__PBUF_VLD_MASK 0xffff
+#define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x0
+#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x7f0000
+#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10
+#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000
+#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17
+#define MC_XPB_WCB_CFG__TIMEOUT_MASK 0xffff
+#define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x0
+#define MC_XPB_WCB_CFG__HST_MAX_MASK 0x30000
+#define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x10
+#define MC_XPB_WCB_CFG__SID_MAX_MASK 0xc0000
+#define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x12
+#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0xf
+#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0
+#define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x30
+#define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x40
+#define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6
+#define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x80
+#define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7
+#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x100
+#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8
+#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x200
+#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9
+#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x400
+#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa
+#define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x800
+#define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb
+#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x1000
+#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc
+#define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR0__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR0__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR0__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR1__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR1__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR1__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR2__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR2__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR2__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR3__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR3__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR3__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR4__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR4__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR4__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR5__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR5__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR5__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR6__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR6__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR6__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR7__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR7__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR7__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0xff
+#define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0
+#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0xff
+#define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x0
+#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0xf00
+#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x8
+#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0xf000
+#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0xc
+#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0xff
+#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0
+#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0xfffff00
+#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8
+#define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0xff
+#define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0
+#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0xfffff00
+#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8
+#define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0
+#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
+#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0
+#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
+#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0
+#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
+#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0
+#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
+#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x2
+#define MC_XPB_CLK_GAT__ONDLY_MASK 0x3f
+#define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x0
+#define MC_XPB_CLK_GAT__OFFDLY_MASK 0xfc0
+#define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x6
+#define MC_XPB_CLK_GAT__RDYDLY_MASK 0x3f000
+#define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0xc
+#define MC_XPB_CLK_GAT__ENABLE_MASK 0x40000
+#define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x12
+#define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x80000
+#define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0xff
+#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0
+#define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0xff00
+#define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8
+#define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x7f0000
+#define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10
+#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x800000
+#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17
+#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x1000000
+#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18
+#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x2000000
+#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19
+#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x4000000
+#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a
+#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000
+#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b
+#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000
+#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d
+#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000
+#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e
+#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000
+#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f
+#define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0xff
+#define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0
+#define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x7f00
+#define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8
+#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x8000
+#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf
+#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x10000
+#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10
+#define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x20000
+#define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11
+#define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x40000
+#define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12
+#define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x7f80000
+#define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13
+#define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x1
+#define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0
+#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0xfe
+#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1
+#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x7f00
+#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8
+#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x8000
+#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf
+#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x10000
+#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10
+#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x20000
+#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11
+#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x40000
+#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12
+#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x80000
+#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13
+#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x100000
+#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14
+#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x200000
+#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15
+#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x400000
+#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16
+#define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x800000
+#define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17
+#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000
+#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18
+#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x1
+#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0
+#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x2
+#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1
+#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x4
+#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2
+#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x8
+#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3
+#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x10
+#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4
+#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x20
+#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5
+#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x40
+#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6
+#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x80
+#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7
+#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x100
+#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8
+#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x200
+#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9
+#define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x400
+#define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa
+#define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x800
+#define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb
+#define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x1000
+#define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0xc
+#define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x2000
+#define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd
+#define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x4000
+#define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe
+#define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x8000
+#define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0xf
+#define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x10000
+#define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10
+#define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x20000
+#define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x11
+#define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x40000
+#define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12
+#define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x80000
+#define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13
+#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0xffff
+#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0
+#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x3f
+#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0
+#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0xfc0
+#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6
+#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x3f000
+#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc
+#define MC_XPB_STICKY__BITS_MASK 0xffffffff
+#define MC_XPB_STICKY__BITS__SHIFT 0x0
+#define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffff
+#define MC_XPB_STICKY_W1C__BITS__SHIFT 0x0
+#define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0xff
+#define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0
+#define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0xff00
+#define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8
+#define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0xff0000
+#define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10
+#define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000
+#define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18
+#define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000
+#define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f
+#define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0xff
+#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0
+#define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0xff
+#define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x0
+#define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0xff00
+#define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x8
+#define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x10000
+#define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x10
+#define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x1fe0000
+#define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x11
+#define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x2000000
+#define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x19
+#define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0xe
+#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x1
+#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3__SHIFT 0x0
+#define MC_XBAR_ADDR_DEC__GECC_MASK 0x2
+#define MC_XBAR_ADDR_DEC__GECC__SHIFT 0x1
+#define MC_XBAR_ADDR_DEC__RB_SPLIT_MASK 0x4
+#define MC_XBAR_ADDR_DEC__RB_SPLIT__SHIFT 0x2
+#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI_MASK 0x8
+#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI__SHIFT 0x3
+#define MC_XBAR_REMOTE__WRREQ_EN_GOQ_MASK 0x1
+#define MC_XBAR_REMOTE__WRREQ_EN_GOQ__SHIFT 0x0
+#define MC_XBAR_REMOTE__RDREQ_EN_GOQ_MASK 0x2
+#define MC_XBAR_REMOTE__RDREQ_EN_GOQ__SHIFT 0x1
+#define MC_XBAR_WRREQ_CREDIT__OUT0_MASK 0xff
+#define MC_XBAR_WRREQ_CREDIT__OUT0__SHIFT 0x0
+#define MC_XBAR_WRREQ_CREDIT__OUT1_MASK 0xff00
+#define MC_XBAR_WRREQ_CREDIT__OUT1__SHIFT 0x8
+#define MC_XBAR_WRREQ_CREDIT__OUT2_MASK 0xff0000
+#define MC_XBAR_WRREQ_CREDIT__OUT2__SHIFT 0x10
+#define MC_XBAR_WRREQ_CREDIT__OUT3_MASK 0xff000000
+#define MC_XBAR_WRREQ_CREDIT__OUT3__SHIFT 0x18
+#define MC_XBAR_RDREQ_CREDIT__OUT0_MASK 0xff
+#define MC_XBAR_RDREQ_CREDIT__OUT0__SHIFT 0x0
+#define MC_XBAR_RDREQ_CREDIT__OUT1_MASK 0xff00
+#define MC_XBAR_RDREQ_CREDIT__OUT1__SHIFT 0x8
+#define MC_XBAR_RDREQ_CREDIT__OUT2_MASK 0xff0000
+#define MC_XBAR_RDREQ_CREDIT__OUT2__SHIFT 0x10
+#define MC_XBAR_RDREQ_CREDIT__OUT3_MASK 0xff000000
+#define MC_XBAR_RDREQ_CREDIT__OUT3__SHIFT 0x18
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0_MASK 0xff
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0__SHIFT 0x0
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1_MASK 0xff00
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1__SHIFT 0x8
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2_MASK 0xff0000
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2__SHIFT 0x10
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3_MASK 0xff000000
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3__SHIFT 0x18
+#define MC_XBAR_WRRET_CREDIT1__OUT0_MASK 0xff
+#define MC_XBAR_WRRET_CREDIT1__OUT0__SHIFT 0x0
+#define MC_XBAR_WRRET_CREDIT1__OUT1_MASK 0xff00
+#define MC_XBAR_WRRET_CREDIT1__OUT1__SHIFT 0x8
+#define MC_XBAR_WRRET_CREDIT1__OUT2_MASK 0xff0000
+#define MC_XBAR_WRRET_CREDIT1__OUT2__SHIFT 0x10
+#define MC_XBAR_WRRET_CREDIT1__OUT3_MASK 0xff000000
+#define MC_XBAR_WRRET_CREDIT1__OUT3__SHIFT 0x18
+#define MC_XBAR_WRRET_CREDIT2__OUT4_MASK 0xff
+#define MC_XBAR_WRRET_CREDIT2__OUT4__SHIFT 0x0
+#define MC_XBAR_WRRET_CREDIT2__OUT5_MASK 0xff00
+#define MC_XBAR_WRRET_CREDIT2__OUT5__SHIFT 0x8
+#define MC_XBAR_RDRET_CREDIT1__OUT0_MASK 0xff
+#define MC_XBAR_RDRET_CREDIT1__OUT0__SHIFT 0x0
+#define MC_XBAR_RDRET_CREDIT1__OUT1_MASK 0xff00
+#define MC_XBAR_RDRET_CREDIT1__OUT1__SHIFT 0x8
+#define MC_XBAR_RDRET_CREDIT1__OUT2_MASK 0xff0000
+#define MC_XBAR_RDRET_CREDIT1__OUT2__SHIFT 0x10
+#define MC_XBAR_RDRET_CREDIT1__OUT3_MASK 0xff000000
+#define MC_XBAR_RDRET_CREDIT1__OUT3__SHIFT 0x18
+#define MC_XBAR_RDRET_CREDIT2__OUT4_MASK 0xff
+#define MC_XBAR_RDRET_CREDIT2__OUT4__SHIFT 0x0
+#define MC_XBAR_RDRET_CREDIT2__OUT5_MASK 0xff00
+#define MC_XBAR_RDRET_CREDIT2__OUT5__SHIFT 0x8
+#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID_MASK 0xff0000
+#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID__SHIFT 0x10
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0_MASK 0xff
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0__SHIFT 0x0
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1_MASK 0xff00
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1__SHIFT 0x8
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2_MASK 0xff0000
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2__SHIFT 0x10
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3_MASK 0xff000000
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3__SHIFT 0x18
+#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4_MASK 0xff
+#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4__SHIFT 0x0
+#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5_MASK 0xff00
+#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5__SHIFT 0x8
+#define MC_XBAR_CHTRIREMAP__CH0_MASK 0x3
+#define MC_XBAR_CHTRIREMAP__CH0__SHIFT 0x0
+#define MC_XBAR_CHTRIREMAP__CH1_MASK 0xc
+#define MC_XBAR_CHTRIREMAP__CH1__SHIFT 0x2
+#define MC_XBAR_CHTRIREMAP__CH2_MASK 0x30
+#define MC_XBAR_CHTRIREMAP__CH2__SHIFT 0x4
+#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT_MASK 0x1
+#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT__SHIFT 0x0
+#define MC_XBAR_TWOCHAN__CH0_MASK 0x6
+#define MC_XBAR_TWOCHAN__CH0__SHIFT 0x1
+#define MC_XBAR_TWOCHAN__CH1_MASK 0x18
+#define MC_XBAR_TWOCHAN__CH1__SHIFT 0x3
+#define MC_XBAR_ARB__HUBRD_HIGHEST_MASK 0x1
+#define MC_XBAR_ARB__HUBRD_HIGHEST__SHIFT 0x0
+#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST_MASK 0x2
+#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST__SHIFT 0x1
+#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE_MASK 0x4
+#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE__SHIFT 0x2
+#define MC_XBAR_ARB__ACP_RDRET_URG_MASK 0x8
+#define MC_XBAR_ARB__ACP_RDRET_URG__SHIFT 0x3
+#define MC_XBAR_ARB__HDP_RDRET_URG_MASK 0x10
+#define MC_XBAR_ARB__HDP_RDRET_URG__SHIFT 0x4
+#define MC_XBAR_ARB__BREAK_BURST_BY_URG_MASK 0x20
+#define MC_XBAR_ARB__BREAK_BURST_BY_URG__SHIFT 0x5
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT0_MASK 0xf
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT0__SHIFT 0x0
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT1_MASK 0xf0
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT1__SHIFT 0x4
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT2_MASK 0xf00
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT2__SHIFT 0x8
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT3_MASK 0xf000
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT3__SHIFT 0xc
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT0_MASK 0xf0000
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT0__SHIFT 0x10
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT1_MASK 0xf00000
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT1__SHIFT 0x14
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT2_MASK 0xf000000
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT2__SHIFT 0x18
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT3_MASK 0xf0000000
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT3__SHIFT 0x1c
+#define MC_XBAR_FIFO_MON_CNTL0__START_THRESH_MASK 0xfff
+#define MC_XBAR_FIFO_MON_CNTL0__START_THRESH__SHIFT 0x0
+#define MC_XBAR_FIFO_MON_CNTL0__STOP_THRESH_MASK 0xfff000
+#define MC_XBAR_FIFO_MON_CNTL0__STOP_THRESH__SHIFT 0xc
+#define MC_XBAR_FIFO_MON_CNTL0__START_MODE_MASK 0x3000000
+#define MC_XBAR_FIFO_MON_CNTL0__START_MODE__SHIFT 0x18
+#define MC_XBAR_FIFO_MON_CNTL0__STOP_MODE_MASK 0xc000000
+#define MC_XBAR_FIFO_MON_CNTL0__STOP_MODE__SHIFT 0x1a
+#define MC_XBAR_FIFO_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000
+#define MC_XBAR_FIFO_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c
+#define MC_XBAR_FIFO_MON_CNTL1__THRESH_CNTR_ID_MASK 0xff
+#define MC_XBAR_FIFO_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0
+#define MC_XBAR_FIFO_MON_CNTL1__START_TRIG_ID_MASK 0xff00
+#define MC_XBAR_FIFO_MON_CNTL1__START_TRIG_ID__SHIFT 0x8
+#define MC_XBAR_FIFO_MON_CNTL1__STOP_TRIG_ID_MASK 0xff0000
+#define MC_XBAR_FIFO_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x10
+#define MC_XBAR_FIFO_MON_CNTL2__MON0_ID_MASK 0xff
+#define MC_XBAR_FIFO_MON_CNTL2__MON0_ID__SHIFT 0x0
+#define MC_XBAR_FIFO_MON_CNTL2__MON1_ID_MASK 0xff00
+#define MC_XBAR_FIFO_MON_CNTL2__MON1_ID__SHIFT 0x8
+#define MC_XBAR_FIFO_MON_CNTL2__MON2_ID_MASK 0xff0000
+#define MC_XBAR_FIFO_MON_CNTL2__MON2_ID__SHIFT 0x10
+#define MC_XBAR_FIFO_MON_CNTL2__MON3_ID_MASK 0xff000000
+#define MC_XBAR_FIFO_MON_CNTL2__MON3_ID__SHIFT 0x18
+#define MC_XBAR_FIFO_MON_RSLT0__COUNT_MASK 0xffffffff
+#define MC_XBAR_FIFO_MON_RSLT0__COUNT__SHIFT 0x0
+#define MC_XBAR_FIFO_MON_RSLT1__COUNT_MASK 0xffffffff
+#define MC_XBAR_FIFO_MON_RSLT1__COUNT__SHIFT 0x0
+#define MC_XBAR_FIFO_MON_RSLT2__COUNT_MASK 0xffffffff
+#define MC_XBAR_FIFO_MON_RSLT2__COUNT__SHIFT 0x0
+#define MC_XBAR_FIFO_MON_RSLT3__COUNT_MASK 0xffffffff
+#define MC_XBAR_FIFO_MON_RSLT3__COUNT__SHIFT 0x0
+#define MC_XBAR_FIFO_MON_MAX_THSH__MON0_MASK 0xff
+#define MC_XBAR_FIFO_MON_MAX_THSH__MON0__SHIFT 0x0
+#define MC_XBAR_FIFO_MON_MAX_THSH__MON1_MASK 0xff00
+#define MC_XBAR_FIFO_MON_MAX_THSH__MON1__SHIFT 0x8
+#define MC_XBAR_FIFO_MON_MAX_THSH__MON2_MASK 0xff0000
+#define MC_XBAR_FIFO_MON_MAX_THSH__MON2__SHIFT 0x10
+#define MC_XBAR_FIFO_MON_MAX_THSH__MON3_MASK 0xff000000
+#define MC_XBAR_FIFO_MON_MAX_THSH__MON3__SHIFT 0x18
+#define MC_XBAR_SPARE0__BIT_MASK 0xffffffff
+#define MC_XBAR_SPARE0__BIT__SHIFT 0x0
+#define MC_XBAR_SPARE1__BIT_MASK 0xffffffff
+#define MC_XBAR_SPARE1__BIT__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_CITF_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_CITF_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_CITF_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_CITF_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_CITF_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_CITF_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_CITF_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_CITF_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_CITF_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_CITF_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_CITF_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_CITF_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_CITF_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_CITF_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_CITF_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_CITF_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_HUB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_HUB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_HUB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_HUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_HUB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_HUB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_HUB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_HUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_HUB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_HUB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_HUB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_HUB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_HUB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_HUB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_HUB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_HUB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_ARB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_ARB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_ARB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_ARB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_ARB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_ARB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_ARB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_ARB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_ARB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_ARB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_ARB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_ARB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_ARB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_ARB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_ARB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_ARB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
+#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
+#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
+#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
+#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
+#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
+#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
+#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
+#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x3
+#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x0
+#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x3
+#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x0
+#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0xffff
+#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0
+#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0xffff
+#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0
+#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x1
+#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0
+#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x2
+#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1
+#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x4
+#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2
+#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x3f00
+#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
+#define ATC_ATS_CNTL__DEBUG_ECO_MASK 0xf0000
+#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x10
+#define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x1
+#define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x0
+#define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x2
+#define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x1
+#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x4
+#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x2
+#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x20
+#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x5
+#define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x40
+#define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x6
+#define ATC_ATS_DEBUG__EXE_BIT_MASK 0x80
+#define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x7
+#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x100
+#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x8
+#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x200
+#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x9
+#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x3c00
+#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0xa
+#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x4000
+#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0xe
+#define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x8000
+#define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0xf
+#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x10000
+#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x10
+#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT_MASK 0x20000
+#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT__SHIFT 0x11
+#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x40000
+#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x12
+#define ATC_ATS_DEBUG__DISABLE_VMID0_PASID_MAPPING_MASK 0x80000
+#define ATC_ATS_DEBUG__DISABLE_VMID0_PASID_MAPPING__SHIFT 0x13
+#define ATC_ATS_DEBUG__DISABLE_INVALIDATION_ON_WORLD_SWITCH_MASK 0x100000
+#define ATC_ATS_DEBUG__DISABLE_INVALIDATION_ON_WORLD_SWITCH__SHIFT 0x14
+#define ATC_ATS_DEBUG__ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT_MASK 0x200000
+#define ATC_ATS_DEBUG__ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT__SHIFT 0x15
+#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x1f
+#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x0
+#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x100
+#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x8
+#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x10000
+#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x10
+#define ATC_ATS_STATUS__BUSY_MASK 0x1
+#define ATC_ATS_STATUS__BUSY__SHIFT 0x0
+#define ATC_ATS_STATUS__CRASHED_MASK 0x2
+#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1
+#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x4
+#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2
+#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x1ff
+#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0
+#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x7fc00
+#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa
+#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1ff00000
+#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14
+#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x1ff
+#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0
+#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x7c00
+#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x8000
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x10000
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10
+#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x20000
+#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x40000
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12
+#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0xf80000
+#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0xf000000
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18
+#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffff
+#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0
+#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xfffffff
+#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0
+#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x1
+#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x0
+#define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x1
+#define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0
+#define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x3e
+#define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1
+#define ATC_ATS_FAULT_STATUS_INFO2__L1_ID_MASK 0x1fe00
+#define ATC_ATS_FAULT_STATUS_INFO2__L1_ID__SHIFT 0x9
+#define ATC_MISC_CG__OFFDLY_MASK 0xfc0
+#define ATC_MISC_CG__OFFDLY__SHIFT 0x6
+#define ATC_MISC_CG__ENABLE_MASK 0x40000
+#define ATC_MISC_CG__ENABLE__SHIFT 0x12
+#define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x80000
+#define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x3
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x30
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x4
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x100
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x8
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x200
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x9
+#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x3f
+#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0xc0
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6
+#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x100
+#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8
+#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0xe00
+#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9
+#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x7000
+#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f8000
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf
+#define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x3f
+#define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x0
+#define ATC_L2_DEBUG__L2_MEM_SELECT_MASK 0x80
+#define ATC_L2_DEBUG__L2_MEM_SELECT__SHIFT 0x7
+#define ATC_L2_DEBUG__CACHE_INDEX_MASK 0xfff00
+#define ATC_L2_DEBUG__CACHE_INDEX__SHIFT 0x8
+#define ATC_L2_DEBUG__CACHE_SELECT_MASK 0x1000000
+#define ATC_L2_DEBUG__CACHE_SELECT__SHIFT 0x18
+#define ATC_L2_DEBUG__CACHE_BANK_SELECT_MASK 0x2000000
+#define ATC_L2_DEBUG__CACHE_BANK_SELECT__SHIFT 0x19
+#define ATC_L2_DEBUG__CACHE_WAY_SELECT_MASK 0x8000000
+#define ATC_L2_DEBUG__CACHE_WAY_SELECT__SHIFT 0x1b
+#define ATC_L2_DEBUG__CACHE_READ_MASK 0x20000000
+#define ATC_L2_DEBUG__CACHE_READ__SHIFT 0x1d
+#define ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR_MASK 0x40000000
+#define ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR__SHIFT 0x1e
+#define ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR_MASK 0x80000000
+#define ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR__SHIFT 0x1f
+#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE_MASK 0x1f
+#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE__SHIFT 0x0
+#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0xe0
+#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x5
+#define ATC_L2_DEBUG2__FORCE_CACHE_MISS_MASK 0x100
+#define ATC_L2_DEBUG2__FORCE_CACHE_MISS__SHIFT 0x8
+#define ATC_L2_DEBUG2__INVALIDATE_ALL_MASK 0x200
+#define ATC_L2_DEBUG2__INVALIDATE_ALL__SHIFT 0x9
+#define ATC_L2_DEBUG2__DISABLE_2M_CACHE_MASK 0x400
+#define ATC_L2_DEBUG2__DISABLE_2M_CACHE__SHIFT 0xa
+#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS_MASK 0x800
+#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS__SHIFT 0xb
+#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS_MASK 0x4000
+#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0xe
+#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT_MASK 0x18000
+#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT__SHIFT 0xf
+#define ATC_L2_DEBUG2__DEBUG_ECO_MASK 0x60000
+#define ATC_L2_DEBUG2__DEBUG_ECO__SHIFT 0x11
+#define ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE_MASK 0x780000
+#define ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE__SHIFT 0x13
+#define ATC_L2_DEBUG2__CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD_MASK 0x7f800000
+#define ATC_L2_DEBUG2__CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD__SHIFT 0x17
+#define ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO_MASK 0x80000000
+#define ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO__SHIFT 0x1f
+#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x1
+#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0
+#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x2
+#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1
+#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x1fffffc
+#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2
+#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x1e000000
+#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x19
+#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xffffffff
+#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0
+#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_LOW_MASK 0xfffffff
+#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_LOW__SHIFT 0x0
+#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x3
+#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x0
+#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x4
+#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x2
+#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x10
+#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x4
+#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffff
+#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x0
+#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
+#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
+#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
+#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
+#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
+#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
+#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
+#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
+#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
+#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
+#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
+#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
+#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
+#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
+#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
+#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
+#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000
+#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f
+#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
+#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
+#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
+#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
+#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
+#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
+#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
+#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
+#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
+#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
+#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
+#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
+#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
+#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
+#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
+#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
+#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000
+#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f
+#define ATC_L1RD_STATUS__BUSY_MASK 0x1
+#define ATC_L1RD_STATUS__BUSY__SHIFT 0x0
+#define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x2
+#define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
+#define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x100
+#define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x8
+#define ATC_L1RD_STATUS__CAM_PARITY_ERRORS_MASK 0x1f000
+#define ATC_L1RD_STATUS__CAM_PARITY_ERRORS__SHIFT 0xc
+#define ATC_L1RD_STATUS__CAM_INDEX_MASK 0x3e0000
+#define ATC_L1RD_STATUS__CAM_INDEX__SHIFT 0x11
+#define ATC_L1WR_STATUS__BUSY_MASK 0x1
+#define ATC_L1WR_STATUS__BUSY__SHIFT 0x0
+#define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x2
+#define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
+#define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x100
+#define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x8
+#define ATC_L1WR_STATUS__CAM_PARITY_ERRORS_MASK 0x1f000
+#define ATC_L1WR_STATUS__CAM_PARITY_ERRORS__SHIFT 0xc
+#define ATC_L1WR_STATUS__CAM_INDEX_MASK 0x3e0000
+#define ATC_L1WR_STATUS__CAM_INDEX__SHIFT 0x11
+#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_PERIOD_MASK 0xfff
+#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_PERIOD__SHIFT 0x0
+#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_MODE_MASK 0xc000
+#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_MODE__SHIFT 0xe
+#define ATC_L1RD_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR_MASK 0x10000
+#define ATC_L1RD_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR__SHIFT 0x10
+#define ATC_L1RD_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR_MASK 0x20000
+#define ATC_L1RD_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR__SHIFT 0x11
+#define ATC_L1RD_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR_MASK 0x40000
+#define ATC_L1RD_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR__SHIFT 0x12
+#define ATC_L1RD_DEBUG2_TLB__CAM_INDEX_MASK 0xf80000
+#define ATC_L1RD_DEBUG2_TLB__CAM_INDEX__SHIFT 0x13
+#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_PERIOD_MASK 0xfff
+#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_PERIOD__SHIFT 0x0
+#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_MODE_MASK 0xc000
+#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_MODE__SHIFT 0xe
+#define ATC_L1WR_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR_MASK 0x10000
+#define ATC_L1WR_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR__SHIFT 0x10
+#define ATC_L1WR_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR_MASK 0x20000
+#define ATC_L1WR_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR__SHIFT 0x11
+#define ATC_L1WR_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR_MASK 0x40000
+#define ATC_L1WR_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR__SHIFT 0x12
+#define ATC_L1WR_DEBUG2_TLB__CAM_INDEX_MASK 0xf80000
+#define ATC_L1WR_DEBUG2_TLB__CAM_INDEX__SHIFT 0x13
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x1
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x2
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x4
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x8
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x10
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x20
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x40
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x80
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x100
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x200
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x400
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x800
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x1000
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x2000
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x4000
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x8000
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf
+#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x1
+#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0
+#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x2
+#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1
+#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x4
+#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2
+#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x8
+#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3
+#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x10
+#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4
+#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x20
+#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5
+#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x40
+#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6
+#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x80
+#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7
+#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x100
+#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8
+#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x200
+#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9
+#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x400
+#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa
+#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x800
+#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb
+#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x1000
+#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc
+#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x2000
+#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd
+#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x4000
+#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe
+#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x8000
+#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf
+#define ATC_ATS_SMU_STATUS__VDDGFX_POWERED_DOWN_MASK 0x1
+#define ATC_ATS_SMU_STATUS__VDDGFX_POWERED_DOWN__SHIFT 0x0
+#define ATC_L2_CNTL3__ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING_MASK 0x7f
+#define ATC_L2_CNTL3__ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING__SHIFT 0x0
+#define ATC_L2_CNTL3__ENABLE_FREE_COUNTER_MASK 0x80
+#define ATC_L2_CNTL3__ENABLE_FREE_COUNTER__SHIFT 0x7
+#define ATC_L2_CNTL3__L2_CACHE_EVICTION_THRESHOLD_MASK 0x1f00
+#define ATC_L2_CNTL3__L2_CACHE_EVICTION_THRESHOLD__SHIFT 0x8
+#define ATC_L2_CNTL3__DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION_MASK 0x2000
+#define ATC_L2_CNTL3__DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION__SHIFT 0xd
+#define ATC_L2_CNTL3__L2_DELAY_SEND_INVALIDATION_REQUEST_MASK 0x1c000
+#define ATC_L2_CNTL3__L2_DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0xe
+#define ATC_L2_STATUS__BUSY_MASK 0x1
+#define ATC_L2_STATUS__BUSY__SHIFT 0x0
+#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3ffffffe
+#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1
+#define ATC_L2_STATUS2__CACHE_ADDRESS_MODE_MASK 0x7
+#define ATC_L2_STATUS2__CACHE_ADDRESS_MODE__SHIFT 0x0
+#define ATC_L2_STATUS2__PARITY_ERROR_INFO_MASK 0x7f8
+#define ATC_L2_STATUS2__PARITY_ERROR_INFO__SHIFT 0x3
+#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x3ff
+#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0
+#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffff
+#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x1
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x2
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0xffc
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x3ff000
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0xc
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc00000
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x16
+#define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x400
+#define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0xa
+#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x800
+#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0xb
+#define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0xf000
+#define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0xc
+#define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x10000
+#define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x10
+#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x60000
+#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x11
+#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x180000
+#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x13
+#define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x200000
+#define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x15
+#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x400000
+#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x16
+#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x800000
+#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x17
+#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x1000000
+#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x18
+#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x2000000
+#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x19
+#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x4000000
+#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x1a
+#define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x8000000
+#define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x1b
+#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x70000000
+#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1c
+#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x80000000
+#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x1f
+#define GMCON_MISC2__GMCON_MISC2_RESERVED0_MASK 0x3f
+#define GMCON_MISC2__GMCON_MISC2_RESERVED0__SHIFT 0x0
+#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD_MASK 0x7c0
+#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD__SHIFT 0x6
+#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x1f800
+#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0xb
+#define GMCON_MISC2__GMCON_MISC2_RESERVED1_MASK 0x1ffe0000
+#define GMCON_MISC2__GMCON_MISC2_RESERVED1__SHIFT 0x11
+#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x20000000
+#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x1d
+#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x40000000
+#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x1e
+#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE_MASK 0x80000000
+#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE__SHIFT 0x1f
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0xffff
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x0
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff0000
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x10
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0xffff
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x0
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff0000
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x10
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0xffff
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x0
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff0000
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x10
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0xffff
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff0000
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0xffff
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff0000
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10
+#define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0xfff
+#define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0
+#define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000
+#define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc
+#define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x3000000
+#define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x18
+#define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000
+#define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a
+#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000
+#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c
+#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT_MASK 0x20000000
+#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT__SHIFT 0x1d
+#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT_MASK 0x40000000
+#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT__SHIFT 0x1e
+#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT_MASK 0x80000000
+#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT__SHIFT 0x1f
+#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x3f
+#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0
+#define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xfc0
+#define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x6
+#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x3f000
+#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0xc
+#define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0x1fc0000
+#define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x12
+#define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0xfe000000
+#define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x19
+#define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffff
+#define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x0
+#define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffff
+#define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x0
+#define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0xff
+#define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
+#define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x100
+#define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
+#define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x200
+#define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
+#define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x400
+#define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
+#define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x800
+#define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
+#define GMCON_PGFSM_CONFIG__WRITE_MASK 0x1000
+#define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0xc
+#define GMCON_PGFSM_CONFIG__READ_MASK 0x2000
+#define GMCON_PGFSM_CONFIG__READ__SHIFT 0xd
+#define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x7ffc000
+#define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0xe
+#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000
+#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
+#define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000
+#define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
+#define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffff
+#define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x0
+#define GMCON_PGFSM_READ__READ_VALUE_MASK 0xffffff
+#define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x0
+#define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0xf000000
+#define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x18
+#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x10000000
+#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x1c
+#define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0xff
+#define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x0
+#define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0xff00
+#define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x8
+#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0xfff0000
+#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10
+#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER_MASK 0x10000000
+#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER__SHIFT 0x1c
+#define GMCON_MISC3__RENG_MEM_LS_ENABLE_MASK 0x20000000
+#define GMCON_MISC3__RENG_MEM_LS_ENABLE__SHIFT 0x1d
+#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS_MASK 0x40000000
+#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS__SHIFT 0x1e
+#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD_MASK 0x1
+#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD__SHIFT 0x0
+#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR_MASK 0x2
+#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR__SHIFT 0x1
+#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD_MASK 0x4
+#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD__SHIFT 0x2
+#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR_MASK 0x8
+#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR__SHIFT 0x3
+#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK_MASK 0xff0
+#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK__SHIFT 0x4
+#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET_MASK 0xffffffff
+#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET__SHIFT 0x0
+#define GMCON_DEBUG__GFX_STALL_MASK 0x1
+#define GMCON_DEBUG__GFX_STALL__SHIFT 0x0
+#define GMCON_DEBUG__GFX_CLEAR_MASK 0x2
+#define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x1
+#define GMCON_DEBUG__GMCON_DEBUG_RESERVED0_MASK 0x4
+#define GMCON_DEBUG__GMCON_DEBUG_RESERVED0__SHIFT 0x2
+#define GMCON_DEBUG__SR_COMMIT_STATE_MASK 0x8
+#define GMCON_DEBUG__SR_COMMIT_STATE__SHIFT 0x3
+#define GMCON_DEBUG__STCTRL_ST_MASK 0xf0
+#define GMCON_DEBUG__STCTRL_ST__SHIFT 0x4
+#define GMCON_DEBUG__MISC_FLAGS_MASK 0xffffff00
+#define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x8
+#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x1
+#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
+#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x2
+#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
+#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0xc
+#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
+#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x30
+#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
+#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x100
+#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
+#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x200
+#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
+#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400
+#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
+#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x800
+#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
+#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x7000
+#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
+#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x38000
+#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
+#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x40000
+#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
+#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x180000
+#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
+#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x3e00000
+#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
+#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0xc000000
+#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a
+#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000
+#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c
+#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x1
+#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
+#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x2
+#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
+#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x200000
+#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
+#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x400000
+#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
+#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x3800000
+#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17
+#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0xc000000
+#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
+#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000
+#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
+#define VM_L2_CNTL3__BANK_SELECT_MASK 0x3f
+#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0xc0
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f00
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0xf8000
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
+#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x100000
+#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
+#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0xe00000
+#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
+#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0xf000000
+#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
+#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000
+#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
+#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000
+#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
+#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000
+#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f
+#define VM_L2_STATUS__L2_BUSY_MASK 0x1
+#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0
+#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x1fffe
+#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
+#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x1
+#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x6
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18
+#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x1
+#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x6
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x1
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x2
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK 0xc
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT 0x2
+#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK 0xfffffff
+#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT 0x0
+#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1
+#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
+#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2
+#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1
+#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4
+#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2
+#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8
+#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3
+#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10
+#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4
+#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1
+#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
+#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2
+#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1
+#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4
+#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2
+#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8
+#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3
+#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10
+#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK 0x1
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT 0x0
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK 0x2
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT 0x1
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK 0x4
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT 0x2
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK 0x8
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT 0x3
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK 0x10
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT 0x4
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK 0x20
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT 0x5
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK 0x40
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT 0x6
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK 0x80
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT 0x7
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK 0x100
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT 0x8
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK 0x200
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT 0x9
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK 0x400
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT 0xa
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK 0x800
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT 0xb
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK 0x1000
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT 0xc
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK 0x2000
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT 0xd
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK 0x4000
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT 0xe
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK 0x8000
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT 0xf
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK 0x1
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT 0x0
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK 0x2
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT 0x1
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK 0x4
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT 0x2
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK 0x8
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT 0x3
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK 0x10
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT 0x4
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK 0x20
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT 0x5
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK 0x40
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT 0x6
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK 0x80
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT 0x7
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK 0x100
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT 0x8
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK 0x200
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT 0x9
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK 0x400
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT 0xa
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK 0x800
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT 0xb
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK 0x1000
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT 0xc
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK 0x2000
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT 0xd
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK 0x4000
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT 0xe
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK 0x8000
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT 0xf
+#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x1
+#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x0
+#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x2
+#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x1
+#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x4
+#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x2
+#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK 0x8
+#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x3
+#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x10
+#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x4
+#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x20
+#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x5
+#define VM_PRT_CNTL__MASK_PDE0_FAULT_MASK 0x40
+#define VM_PRT_CNTL__MASK_PDE0_FAULT__SHIFT 0x6
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x1
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x2
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x4
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x8
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x10
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x20
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x40
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x80
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x100
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x200
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x400
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x800
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x1000
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x2000
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x4000
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x8000
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d
+#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff
+#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0
+#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff
+#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0
+#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
+#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
+#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
+#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
+#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff
+#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0
+#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff
+#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK 0x1ff
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT 0x0
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK 0x3fe00
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT 0x9
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MSB_MASK 0x40000
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MSB__SHIFT 0x12
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MASK_MSB_MASK 0x80000
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MASK_MSB__SHIFT 0x13
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_DEBUG__FLAGS_MASK 0xffffffff
+#define VM_DEBUG__FLAGS__SHIFT 0x0
+#define VM_L2_CG__OFFDLY_MASK 0xfc0
+#define VM_L2_CG__OFFDLY__SHIFT 0x6
+#define VM_L2_CG__ENABLE_MASK 0x40000
+#define VM_L2_CG__ENABLE__SHIFT 0x12
+#define VM_L2_CG__MEM_LS_ENABLE_MASK 0x80000
+#define VM_L2_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define VM_L2_CG__OVERRIDE_MASK 0x100000
+#define VM_L2_CG__OVERRIDE__SHIFT 0x14
+#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK 0xfffffff
+#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT 0x0
+#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK 0xff
+#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK 0xfffffff
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT 0x0
+#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x3f
+#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK 0x40
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT 0x6
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK 0x80
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT 0x7
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK 0x100
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT 0x8
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK 0x200
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT 0x9
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK 0x400
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT 0xa
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK 0x800
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT 0xb
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK 0x1000
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT 0xc
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK 0x2000
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT 0xd
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK 0x4000
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT 0xe
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK 0x8000
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT 0xf
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK 0x10000
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT 0x10
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK 0x20000
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT 0x11
+#define VM_L2_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING_MASK 0x40000
+#define VM_L2_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING__SHIFT 0x12
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x1ff
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x7fc00
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
+#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x100000
+#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x1000000
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x2000000
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x1ff
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x7fc00
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
+#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x100000
+#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x1000000
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x2000000
+#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xffffffff
+#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0
+#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xffffffff
+#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0
+#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x800000
+#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17
+#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x8
+#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3
+#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xff800000
+#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17
+#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x1
+#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0
+#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xff800000
+#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17
+#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0xff
+#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0
+#define MC_VM_NB_TOP_OF_DRAM3__TOM3_LIMIT_MASK 0x3fffffff
+#define MC_VM_NB_TOP_OF_DRAM3__TOM3_LIMIT__SHIFT 0x0
+#define MC_VM_NB_TOP_OF_DRAM3__TOM3_ENABLE_MASK 0x80000000
+#define MC_VM_NB_TOP_OF_DRAM3__TOM3_ENABLE__SHIFT 0x1f
+#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xfffff000
+#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc
+#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xfffff000
+#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc
+#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xfffff000
+#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc
+#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xfffff000
+#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc
+#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0xfffff
+#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0
+#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0xfffff
+#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0
+#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0xfffff
+#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0
+#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0xfffff
+#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x1
+#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x2
+#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xfffff000
+#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc
+#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x1
+#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x2
+#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xfffff000
+#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc
+#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x1
+#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x2
+#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xfffff000
+#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc
+#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x1
+#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x2
+#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xfffff000
+#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc
+#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0xfffff
+#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0
+#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0xfffff
+#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0
+#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0xfffff
+#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0
+#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0xfffff
+#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0
+#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xfffff000
+#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc
+#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xfffff000
+#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc
+#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xfffff000
+#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc
+#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xfffff000
+#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc
+#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0xfffff
+#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0
+#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0xfffff
+#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0
+#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0xfffff
+#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0
+#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0xfffff
+#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0
+#define MC_VM_MARC_CNTL__ENABLE_ALL_CLIENTS_MASK 0x1
+#define MC_VM_MARC_CNTL__ENABLE_ALL_CLIENTS__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_CNTL0__REQ_STREAM_ID_MASK 0x1ff
+#define MC_VM_MB_L1_TLS0_CNTL0__REQ_STREAM_ID__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_CNTL0__EN_MASK 0x1000
+#define MC_VM_MB_L1_TLS0_CNTL0__EN__SHIFT 0xc
+#define MC_VM_MB_L1_TLS0_CNTL0__PREFETCH_DONE_MASK 0x2000
+#define MC_VM_MB_L1_TLS0_CNTL0__PREFETCH_DONE__SHIFT 0xd
+#define MC_VM_MB_L1_TLS0_CNTL1__REQ_STREAM_ID_MASK 0x1ff
+#define MC_VM_MB_L1_TLS0_CNTL1__REQ_STREAM_ID__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_CNTL1__EN_MASK 0x1000
+#define MC_VM_MB_L1_TLS0_CNTL1__EN__SHIFT 0xc
+#define MC_VM_MB_L1_TLS0_CNTL1__PREFETCH_DONE_MASK 0x2000
+#define MC_VM_MB_L1_TLS0_CNTL1__PREFETCH_DONE__SHIFT 0xd
+#define MC_VM_MB_L1_TLS0_CNTL2__REQ_STREAM_ID_MASK 0x1ff
+#define MC_VM_MB_L1_TLS0_CNTL2__REQ_STREAM_ID__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_CNTL2__EN_MASK 0x1000
+#define MC_VM_MB_L1_TLS0_CNTL2__EN__SHIFT 0xc
+#define MC_VM_MB_L1_TLS0_CNTL2__PREFETCH_DONE_MASK 0x2000
+#define MC_VM_MB_L1_TLS0_CNTL2__PREFETCH_DONE__SHIFT 0xd
+#define MC_VM_MB_L1_TLS0_CNTL3__REQ_STREAM_ID_MASK 0x1ff
+#define MC_VM_MB_L1_TLS0_CNTL3__REQ_STREAM_ID__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_CNTL3__EN_MASK 0x1000
+#define MC_VM_MB_L1_TLS0_CNTL3__EN__SHIFT 0xc
+#define MC_VM_MB_L1_TLS0_CNTL3__PREFETCH_DONE_MASK 0x2000
+#define MC_VM_MB_L1_TLS0_CNTL3__PREFETCH_DONE__SHIFT 0xd
+#define MC_VM_MB_L1_TLS0_CNTL4__REQ_STREAM_ID_MASK 0x1ff
+#define MC_VM_MB_L1_TLS0_CNTL4__REQ_STREAM_ID__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_CNTL4__EN_MASK 0x1000
+#define MC_VM_MB_L1_TLS0_CNTL4__EN__SHIFT 0xc
+#define MC_VM_MB_L1_TLS0_CNTL4__PREFETCH_DONE_MASK 0x2000
+#define MC_VM_MB_L1_TLS0_CNTL4__PREFETCH_DONE__SHIFT 0xd
+#define MC_VM_MB_L1_TLS0_CNTL5__REQ_STREAM_ID_MASK 0x1ff
+#define MC_VM_MB_L1_TLS0_CNTL5__REQ_STREAM_ID__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_CNTL5__EN_MASK 0x1000
+#define MC_VM_MB_L1_TLS0_CNTL5__EN__SHIFT 0xc
+#define MC_VM_MB_L1_TLS0_CNTL5__PREFETCH_DONE_MASK 0x2000
+#define MC_VM_MB_L1_TLS0_CNTL5__PREFETCH_DONE__SHIFT 0xd
+#define MC_VM_MB_L1_TLS0_CNTL6__REQ_STREAM_ID_MASK 0x1ff
+#define MC_VM_MB_L1_TLS0_CNTL6__REQ_STREAM_ID__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_CNTL6__EN_MASK 0x1000
+#define MC_VM_MB_L1_TLS0_CNTL6__EN__SHIFT 0xc
+#define MC_VM_MB_L1_TLS0_CNTL6__PREFETCH_DONE_MASK 0x2000
+#define MC_VM_MB_L1_TLS0_CNTL6__PREFETCH_DONE__SHIFT 0xd
+#define MC_VM_MB_L1_TLS0_CNTL7__REQ_STREAM_ID_MASK 0x1ff
+#define MC_VM_MB_L1_TLS0_CNTL7__REQ_STREAM_ID__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_CNTL7__EN_MASK 0x1000
+#define MC_VM_MB_L1_TLS0_CNTL7__EN__SHIFT 0xc
+#define MC_VM_MB_L1_TLS0_CNTL7__PREFETCH_DONE_MASK 0x2000
+#define MC_VM_MB_L1_TLS0_CNTL7__PREFETCH_DONE__SHIFT 0xd
+#define MC_VM_MB_L1_TLS0_CNTL8__REQ_STREAM_ID_MASK 0x1ff
+#define MC_VM_MB_L1_TLS0_CNTL8__REQ_STREAM_ID__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_CNTL8__EN_MASK 0x1000
+#define MC_VM_MB_L1_TLS0_CNTL8__EN__SHIFT 0xc
+#define MC_VM_MB_L1_TLS0_CNTL8__PREFETCH_DONE_MASK 0x2000
+#define MC_VM_MB_L1_TLS0_CNTL8__PREFETCH_DONE__SHIFT 0xd
+#define MC_VM_MB_L1_TLS0_START_ADDR0__START_ADDR_MASK 0xfffffff
+#define MC_VM_MB_L1_TLS0_START_ADDR0__START_ADDR__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_START_ADDR1__START_ADDR_MASK 0xfffffff
+#define MC_VM_MB_L1_TLS0_START_ADDR1__START_ADDR__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_START_ADDR2__START_ADDR_MASK 0xfffffff
+#define MC_VM_MB_L1_TLS0_START_ADDR2__START_ADDR__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_START_ADDR3__START_ADDR_MASK 0xfffffff
+#define MC_VM_MB_L1_TLS0_START_ADDR3__START_ADDR__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_START_ADDR4__START_ADDR_MASK 0xfffffff
+#define MC_VM_MB_L1_TLS0_START_ADDR4__START_ADDR__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_START_ADDR5__START_ADDR_MASK 0xfffffff
+#define MC_VM_MB_L1_TLS0_START_ADDR5__START_ADDR__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_START_ADDR6__START_ADDR_MASK 0xfffffff
+#define MC_VM_MB_L1_TLS0_START_ADDR6__START_ADDR__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_START_ADDR7__START_ADDR_MASK 0xfffffff
+#define MC_VM_MB_L1_TLS0_START_ADDR7__START_ADDR__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_START_ADDR8__START_ADDR_MASK 0xfffffff
+#define MC_VM_MB_L1_TLS0_START_ADDR8__START_ADDR__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_END_ADDR0__END_ADDR_MASK 0xfffffff
+#define MC_VM_MB_L1_TLS0_END_ADDR0__END_ADDR__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_END_ADDR1__END_ADDR_MASK 0xfffffff
+#define MC_VM_MB_L1_TLS0_END_ADDR1__END_ADDR__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_END_ADDR2__END_ADDR_MASK 0xfffffff
+#define MC_VM_MB_L1_TLS0_END_ADDR2__END_ADDR__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_END_ADDR3__END_ADDR_MASK 0xfffffff
+#define MC_VM_MB_L1_TLS0_END_ADDR3__END_ADDR__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_END_ADDR4__END_ADDR_MASK 0xfffffff
+#define MC_VM_MB_L1_TLS0_END_ADDR4__END_ADDR__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_END_ADDR5__END_ADDR_MASK 0xfffffff
+#define MC_VM_MB_L1_TLS0_END_ADDR5__END_ADDR__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_END_ADDR6__END_ADDR_MASK 0xfffffff
+#define MC_VM_MB_L1_TLS0_END_ADDR6__END_ADDR__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_END_ADDR7__END_ADDR_MASK 0xfffffff
+#define MC_VM_MB_L1_TLS0_END_ADDR7__END_ADDR__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_END_ADDR8__END_ADDR_MASK 0xfffffff
+#define MC_VM_MB_L1_TLS0_END_ADDR8__END_ADDR__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
+#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
+#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000
+#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
+#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
+#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
+#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
+#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
+#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000
+#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d
+#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
+#define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
+#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS_MASK 0x3
+#define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS__SHIFT 0x0
+#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK_MASK 0xc
+#define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK__SHIFT 0x2
+#define MC_SEQ_CNTL__SAFE_MODE_MASK 0x30
+#define MC_SEQ_CNTL__SAFE_MODE__SHIFT 0x4
+#define MC_SEQ_CNTL__DAT_INV_MASK 0x40
+#define MC_SEQ_CNTL__DAT_INV__SHIFT 0x6
+#define MC_SEQ_CNTL__MSK_DF1_MASK 0x80
+#define MC_SEQ_CNTL__MSK_DF1__SHIFT 0x7
+#define MC_SEQ_CNTL__CHANNEL_DISABLE_MASK 0x300
+#define MC_SEQ_CNTL__CHANNEL_DISABLE__SHIFT 0x8
+#define MC_SEQ_CNTL__MSKOFF_DAT_TL_MASK 0x4000
+#define MC_SEQ_CNTL__MSKOFF_DAT_TL__SHIFT 0xe
+#define MC_SEQ_CNTL__MSKOFF_DAT_TH_MASK 0x8000
+#define MC_SEQ_CNTL__MSKOFF_DAT_TH__SHIFT 0xf
+#define MC_SEQ_CNTL__RET_HOLD_EOP_MASK 0x10000
+#define MC_SEQ_CNTL__RET_HOLD_EOP__SHIFT 0x10
+#define MC_SEQ_CNTL__BANKGROUP_SIZE_MASK 0x20000
+#define MC_SEQ_CNTL__BANKGROUP_SIZE__SHIFT 0x11
+#define MC_SEQ_CNTL__BANKGROUP_ENB_MASK 0x40000
+#define MC_SEQ_CNTL__BANKGROUP_ENB__SHIFT 0x12
+#define MC_SEQ_CNTL__RTR_OVERRIDE_MASK 0x80000
+#define MC_SEQ_CNTL__RTR_OVERRIDE__SHIFT 0x13
+#define MC_SEQ_CNTL__ARB_REQCMD_WMK_MASK 0xf00000
+#define MC_SEQ_CNTL__ARB_REQCMD_WMK__SHIFT 0x14
+#define MC_SEQ_CNTL__ARB_REQDAT_WMK_MASK 0xf000000
+#define MC_SEQ_CNTL__ARB_REQDAT_WMK__SHIFT 0x18
+#define MC_SEQ_CNTL__ARB_RTDAT_WMK_MASK 0xf0000000
+#define MC_SEQ_CNTL__ARB_RTDAT_WMK__SHIFT 0x1c
+#define MC_SEQ_CNTL_2__DRST_PDRV_MASK 0xf
+#define MC_SEQ_CNTL_2__DRST_PDRV__SHIFT 0x0
+#define MC_SEQ_CNTL_2__DRST_PU_MASK 0x10
+#define MC_SEQ_CNTL_2__DRST_PU__SHIFT 0x4
+#define MC_SEQ_CNTL_2__DRST_PD_MASK 0x20
+#define MC_SEQ_CNTL_2__DRST_PD__SHIFT 0x5
+#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB_MASK 0x300
+#define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB__SHIFT 0x8
+#define MC_SEQ_CNTL_2__DRST_NSTR_MASK 0xfc00
+#define MC_SEQ_CNTL_2__DRST_NSTR__SHIFT 0xa
+#define MC_SEQ_CNTL_2__DRST_PSTR_MASK 0x3f0000
+#define MC_SEQ_CNTL_2__DRST_PSTR__SHIFT 0x10
+#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0_MASK 0x400000
+#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0__SHIFT 0x16
+#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1_MASK 0x800000
+#define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1__SHIFT 0x17
+#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0_MASK 0xf000000
+#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0__SHIFT 0x18
+#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1_MASK 0xf0000000
+#define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1__SHIFT 0x1c
+#define MC_SEQ_DRAM__ADR_2CK_MASK 0x1
+#define MC_SEQ_DRAM__ADR_2CK__SHIFT 0x0
+#define MC_SEQ_DRAM__ADR_MUX_MASK 0x2
+#define MC_SEQ_DRAM__ADR_MUX__SHIFT 0x1
+#define MC_SEQ_DRAM__ADR_DF1_MASK 0x4
+#define MC_SEQ_DRAM__ADR_DF1__SHIFT 0x2
+#define MC_SEQ_DRAM__AP8_MASK 0x8
+#define MC_SEQ_DRAM__AP8__SHIFT 0x3
+#define MC_SEQ_DRAM__DAT_DF1_MASK 0x10
+#define MC_SEQ_DRAM__DAT_DF1__SHIFT 0x4
+#define MC_SEQ_DRAM__DQS_DF1_MASK 0x20
+#define MC_SEQ_DRAM__DQS_DF1__SHIFT 0x5
+#define MC_SEQ_DRAM__DQM_DF1_MASK 0x40
+#define MC_SEQ_DRAM__DQM_DF1__SHIFT 0x6
+#define MC_SEQ_DRAM__DQM_ACT_MASK 0x80
+#define MC_SEQ_DRAM__DQM_ACT__SHIFT 0x7
+#define MC_SEQ_DRAM__STB_CNT_MASK 0xf00
+#define MC_SEQ_DRAM__STB_CNT__SHIFT 0x8
+#define MC_SEQ_DRAM__CKE_DYN_MASK 0x1000
+#define MC_SEQ_DRAM__CKE_DYN__SHIFT 0xc
+#define MC_SEQ_DRAM__CKE_ACT_MASK 0x2000
+#define MC_SEQ_DRAM__CKE_ACT__SHIFT 0xd
+#define MC_SEQ_DRAM__BO4_MASK 0x4000
+#define MC_SEQ_DRAM__BO4__SHIFT 0xe
+#define MC_SEQ_DRAM__DLL_CLR_MASK 0x8000
+#define MC_SEQ_DRAM__DLL_CLR__SHIFT 0xf
+#define MC_SEQ_DRAM__DLL_CNT_MASK 0xff0000
+#define MC_SEQ_DRAM__DLL_CNT__SHIFT 0x10
+#define MC_SEQ_DRAM__DAT_INV_MASK 0x1000000
+#define MC_SEQ_DRAM__DAT_INV__SHIFT 0x18
+#define MC_SEQ_DRAM__INV_ACM_MASK 0x2000000
+#define MC_SEQ_DRAM__INV_ACM__SHIFT 0x19
+#define MC_SEQ_DRAM__ODT_ENB_MASK 0x4000000
+#define MC_SEQ_DRAM__ODT_ENB__SHIFT 0x1a
+#define MC_SEQ_DRAM__ODT_ACT_MASK 0x8000000
+#define MC_SEQ_DRAM__ODT_ACT__SHIFT 0x1b
+#define MC_SEQ_DRAM__RST_CTL_MASK 0x10000000
+#define MC_SEQ_DRAM__RST_CTL__SHIFT 0x1c
+#define MC_SEQ_DRAM__TRI_MIO_DYN_MASK 0x20000000
+#define MC_SEQ_DRAM__TRI_MIO_DYN__SHIFT 0x1d
+#define MC_SEQ_DRAM__TRI_CKE_MASK 0x40000000
+#define MC_SEQ_DRAM__TRI_CKE__SHIFT 0x1e
+#define MC_SEQ_DRAM__RDSTRB_RSYC_DIS_MASK 0x80000000
+#define MC_SEQ_DRAM__RDSTRB_RSYC_DIS__SHIFT 0x1f
+#define MC_SEQ_DRAM_2__ADR_DDR_MASK 0x1
+#define MC_SEQ_DRAM_2__ADR_DDR__SHIFT 0x0
+#define MC_SEQ_DRAM_2__ADR_DBI_MASK 0x2
+#define MC_SEQ_DRAM_2__ADR_DBI__SHIFT 0x1
+#define MC_SEQ_DRAM_2__ADR_DBI_ACM_MASK 0x4
+#define MC_SEQ_DRAM_2__ADR_DBI_ACM__SHIFT 0x2
+#define MC_SEQ_DRAM_2__CMD_QDR_MASK 0x8
+#define MC_SEQ_DRAM_2__CMD_QDR__SHIFT 0x3
+#define MC_SEQ_DRAM_2__DAT_QDR_MASK 0x10
+#define MC_SEQ_DRAM_2__DAT_QDR__SHIFT 0x4
+#define MC_SEQ_DRAM_2__WDAT_EDC_MASK 0x20
+#define MC_SEQ_DRAM_2__WDAT_EDC__SHIFT 0x5
+#define MC_SEQ_DRAM_2__RDAT_EDC_MASK 0x40
+#define MC_SEQ_DRAM_2__RDAT_EDC__SHIFT 0x6
+#define MC_SEQ_DRAM_2__DQM_EST_MASK 0x80
+#define MC_SEQ_DRAM_2__DQM_EST__SHIFT 0x7
+#define MC_SEQ_DRAM_2__RD_DQS_MASK 0x100
+#define MC_SEQ_DRAM_2__RD_DQS__SHIFT 0x8
+#define MC_SEQ_DRAM_2__WR_DQS_MASK 0x200
+#define MC_SEQ_DRAM_2__WR_DQS__SHIFT 0x9
+#define MC_SEQ_DRAM_2__PLL_EST_MASK 0x400
+#define MC_SEQ_DRAM_2__PLL_EST__SHIFT 0xa
+#define MC_SEQ_DRAM_2__PLL_CLR_MASK 0x800
+#define MC_SEQ_DRAM_2__PLL_CLR__SHIFT 0xb
+#define MC_SEQ_DRAM_2__DLL_EST_MASK 0x1000
+#define MC_SEQ_DRAM_2__DLL_EST__SHIFT 0xc
+#define MC_SEQ_DRAM_2__BNK_MRS_MASK 0x2000
+#define MC_SEQ_DRAM_2__BNK_MRS__SHIFT 0xd
+#define MC_SEQ_DRAM_2__DBI_OVR_MASK 0x4000
+#define MC_SEQ_DRAM_2__DBI_OVR__SHIFT 0xe
+#define MC_SEQ_DRAM_2__TRI_CLK_MASK 0x8000
+#define MC_SEQ_DRAM_2__TRI_CLK__SHIFT 0xf
+#define MC_SEQ_DRAM_2__PLL_CNT_MASK 0xff0000
+#define MC_SEQ_DRAM_2__PLL_CNT__SHIFT 0x10
+#define MC_SEQ_DRAM_2__PCH_BNK_MASK 0x1000000
+#define MC_SEQ_DRAM_2__PCH_BNK__SHIFT 0x18
+#define MC_SEQ_DRAM_2__ADBI_DF1_MASK 0x2000000
+#define MC_SEQ_DRAM_2__ADBI_DF1__SHIFT 0x19
+#define MC_SEQ_DRAM_2__ADBI_ACT_MASK 0x4000000
+#define MC_SEQ_DRAM_2__ADBI_ACT__SHIFT 0x1a
+#define MC_SEQ_DRAM_2__DBI_DF1_MASK 0x8000000
+#define MC_SEQ_DRAM_2__DBI_DF1__SHIFT 0x1b
+#define MC_SEQ_DRAM_2__DBI_ACT_MASK 0x10000000
+#define MC_SEQ_DRAM_2__DBI_ACT__SHIFT 0x1c
+#define MC_SEQ_DRAM_2__DBI_EDC_DF1_MASK 0x20000000
+#define MC_SEQ_DRAM_2__DBI_EDC_DF1__SHIFT 0x1d
+#define MC_SEQ_DRAM_2__TESTCHIP_EN_MASK 0x40000000
+#define MC_SEQ_DRAM_2__TESTCHIP_EN__SHIFT 0x1e
+#define MC_SEQ_DRAM_2__CS_BY16_MASK 0x80000000
+#define MC_SEQ_DRAM_2__CS_BY16__SHIFT 0x1f
+#define MC_SEQ_RAS_TIMING__TRCDW_MASK 0x1f
+#define MC_SEQ_RAS_TIMING__TRCDW__SHIFT 0x0
+#define MC_SEQ_RAS_TIMING__TRCDWA_MASK 0x3e0
+#define MC_SEQ_RAS_TIMING__TRCDWA__SHIFT 0x5
+#define MC_SEQ_RAS_TIMING__TRCDR_MASK 0x7c00
+#define MC_SEQ_RAS_TIMING__TRCDR__SHIFT 0xa
+#define MC_SEQ_RAS_TIMING__TRCDRA_MASK 0xf8000
+#define MC_SEQ_RAS_TIMING__TRCDRA__SHIFT 0xf
+#define MC_SEQ_RAS_TIMING__TRRD_MASK 0xf00000
+#define MC_SEQ_RAS_TIMING__TRRD__SHIFT 0x14
+#define MC_SEQ_RAS_TIMING__TRC_MASK 0x7f000000
+#define MC_SEQ_RAS_TIMING__TRC__SHIFT 0x18
+#define MC_SEQ_CAS_TIMING__TNOPW_MASK 0x3
+#define MC_SEQ_CAS_TIMING__TNOPW__SHIFT 0x0
+#define MC_SEQ_CAS_TIMING__TNOPR_MASK 0xc
+#define MC_SEQ_CAS_TIMING__TNOPR__SHIFT 0x2
+#define MC_SEQ_CAS_TIMING__TR2W_MASK 0x1f0
+#define MC_SEQ_CAS_TIMING__TR2W__SHIFT 0x4
+#define MC_SEQ_CAS_TIMING__TCCDL_MASK 0xe00
+#define MC_SEQ_CAS_TIMING__TCCDL__SHIFT 0x9
+#define MC_SEQ_CAS_TIMING__TR2R_MASK 0xf000
+#define MC_SEQ_CAS_TIMING__TR2R__SHIFT 0xc
+#define MC_SEQ_CAS_TIMING__TW2R_MASK 0x1f0000
+#define MC_SEQ_CAS_TIMING__TW2R__SHIFT 0x10
+#define MC_SEQ_CAS_TIMING__TCL_MASK 0x1f000000
+#define MC_SEQ_CAS_TIMING__TCL__SHIFT 0x18
+#define MC_SEQ_MISC_TIMING__TRP_WRA_MASK 0x3f
+#define MC_SEQ_MISC_TIMING__TRP_WRA__SHIFT 0x0
+#define MC_SEQ_MISC_TIMING__TRP_RDA_MASK 0x3f00
+#define MC_SEQ_MISC_TIMING__TRP_RDA__SHIFT 0x8
+#define MC_SEQ_MISC_TIMING__TRP_MASK 0xf8000
+#define MC_SEQ_MISC_TIMING__TRP__SHIFT 0xf
+#define MC_SEQ_MISC_TIMING__TRFC_MASK 0x1ff00000
+#define MC_SEQ_MISC_TIMING__TRFC__SHIFT 0x14
+#define MC_SEQ_MISC_TIMING2__PA2RDATA_MASK 0x7
+#define MC_SEQ_MISC_TIMING2__PA2RDATA__SHIFT 0x0
+#define MC_SEQ_MISC_TIMING2__PA2WDATA_MASK 0x70
+#define MC_SEQ_MISC_TIMING2__PA2WDATA__SHIFT 0x4
+#define MC_SEQ_MISC_TIMING2__FAW_MASK 0x1f00
+#define MC_SEQ_MISC_TIMING2__FAW__SHIFT 0x8
+#define MC_SEQ_MISC_TIMING2__TREDC_MASK 0xe000
+#define MC_SEQ_MISC_TIMING2__TREDC__SHIFT 0xd
+#define MC_SEQ_MISC_TIMING2__TWEDC_MASK 0x1f0000
+#define MC_SEQ_MISC_TIMING2__TWEDC__SHIFT 0x10
+#define MC_SEQ_MISC_TIMING2__T32AW_MASK 0x1e00000
+#define MC_SEQ_MISC_TIMING2__T32AW__SHIFT 0x15
+#define MC_SEQ_MISC_TIMING2__TWDATATR_MASK 0xf0000000
+#define MC_SEQ_MISC_TIMING2__TWDATATR__SHIFT 0x1c
+#define MC_SEQ_PMG_TIMING__TCKSRE_MASK 0x7
+#define MC_SEQ_PMG_TIMING__TCKSRE__SHIFT 0x0
+#define MC_SEQ_PMG_TIMING__TCKSRX_MASK 0x70
+#define MC_SEQ_PMG_TIMING__TCKSRX__SHIFT 0x4
+#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MASK 0xf00
+#define MC_SEQ_PMG_TIMING__TCKE_PULSE__SHIFT 0x8
+#define MC_SEQ_PMG_TIMING__TCKE_MASK 0x3f000
+#define MC_SEQ_PMG_TIMING__TCKE__SHIFT 0xc
+#define MC_SEQ_PMG_TIMING__SEQ_IDLE_MASK 0x1c0000
+#define MC_SEQ_PMG_TIMING__SEQ_IDLE__SHIFT 0x12
+#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB_MASK 0x800000
+#define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB__SHIFT 0x17
+#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS_MASK 0xff000000
+#define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS__SHIFT 0x18
+#define MC_SEQ_RD_CTL_D0__RCV_DLY_MASK 0x7
+#define MC_SEQ_RD_CTL_D0__RCV_DLY__SHIFT 0x0
+#define MC_SEQ_RD_CTL_D0__RCV_EXT_MASK 0xf8
+#define MC_SEQ_RD_CTL_D0__RCV_EXT__SHIFT 0x3
+#define MC_SEQ_RD_CTL_D0__RST_SEL_MASK 0x300
+#define MC_SEQ_RD_CTL_D0__RST_SEL__SHIFT 0x8
+#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY_MASK 0xc00
+#define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY__SHIFT 0xa
+#define MC_SEQ_RD_CTL_D0__RST_HLD_MASK 0xf000
+#define MC_SEQ_RD_CTL_D0__RST_HLD__SHIFT 0xc
+#define MC_SEQ_RD_CTL_D0__STR_PRE_MASK 0x10000
+#define MC_SEQ_RD_CTL_D0__STR_PRE__SHIFT 0x10
+#define MC_SEQ_RD_CTL_D0__STR_PST_MASK 0x20000
+#define MC_SEQ_RD_CTL_D0__STR_PST__SHIFT 0x11
+#define MC_SEQ_RD_CTL_D0__RBS_DLY_MASK 0x1f00000
+#define MC_SEQ_RD_CTL_D0__RBS_DLY__SHIFT 0x14
+#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY_MASK 0x3e000000
+#define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY__SHIFT 0x19
+#define MC_SEQ_RD_CTL_D1__RCV_DLY_MASK 0x7
+#define MC_SEQ_RD_CTL_D1__RCV_DLY__SHIFT 0x0
+#define MC_SEQ_RD_CTL_D1__RCV_EXT_MASK 0xf8
+#define MC_SEQ_RD_CTL_D1__RCV_EXT__SHIFT 0x3
+#define MC_SEQ_RD_CTL_D1__RST_SEL_MASK 0x300
+#define MC_SEQ_RD_CTL_D1__RST_SEL__SHIFT 0x8
+#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY_MASK 0xc00
+#define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY__SHIFT 0xa
+#define MC_SEQ_RD_CTL_D1__RST_HLD_MASK 0xf000
+#define MC_SEQ_RD_CTL_D1__RST_HLD__SHIFT 0xc
+#define MC_SEQ_RD_CTL_D1__STR_PRE_MASK 0x10000
+#define MC_SEQ_RD_CTL_D1__STR_PRE__SHIFT 0x10
+#define MC_SEQ_RD_CTL_D1__STR_PST_MASK 0x20000
+#define MC_SEQ_RD_CTL_D1__STR_PST__SHIFT 0x11
+#define MC_SEQ_RD_CTL_D1__RBS_DLY_MASK 0x1f00000
+#define MC_SEQ_RD_CTL_D1__RBS_DLY__SHIFT 0x14
+#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY_MASK 0x3e000000
+#define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY__SHIFT 0x19
+#define MC_SEQ_WR_CTL_D0__DAT_DLY_MASK 0xf
+#define MC_SEQ_WR_CTL_D0__DAT_DLY__SHIFT 0x0
+#define MC_SEQ_WR_CTL_D0__DQS_DLY_MASK 0xf0
+#define MC_SEQ_WR_CTL_D0__DQS_DLY__SHIFT 0x4
+#define MC_SEQ_WR_CTL_D0__DQS_XTR_MASK 0x100
+#define MC_SEQ_WR_CTL_D0__DQS_XTR__SHIFT 0x8
+#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY_MASK 0x200
+#define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY__SHIFT 0x9
+#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY_MASK 0x400
+#define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY__SHIFT 0xa
+#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY_MASK 0x800
+#define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY__SHIFT 0xb
+#define MC_SEQ_WR_CTL_D0__OEN_DLY_MASK 0xf000
+#define MC_SEQ_WR_CTL_D0__OEN_DLY__SHIFT 0xc
+#define MC_SEQ_WR_CTL_D0__OEN_EXT_MASK 0xf0000
+#define MC_SEQ_WR_CTL_D0__OEN_EXT__SHIFT 0x10
+#define MC_SEQ_WR_CTL_D0__OEN_SEL_MASK 0x300000
+#define MC_SEQ_WR_CTL_D0__OEN_SEL__SHIFT 0x14
+#define MC_SEQ_WR_CTL_D0__ODT_DLY_MASK 0xf000000
+#define MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT 0x18
+#define MC_SEQ_WR_CTL_D0__ODT_EXT_MASK 0x10000000
+#define MC_SEQ_WR_CTL_D0__ODT_EXT__SHIFT 0x1c
+#define MC_SEQ_WR_CTL_D0__ADR_DLY_MASK 0x20000000
+#define MC_SEQ_WR_CTL_D0__ADR_DLY__SHIFT 0x1d
+#define MC_SEQ_WR_CTL_D0__CMD_DLY_MASK 0x40000000
+#define MC_SEQ_WR_CTL_D0__CMD_DLY__SHIFT 0x1e
+#define MC_SEQ_WR_CTL_D1__DAT_DLY_MASK 0xf
+#define MC_SEQ_WR_CTL_D1__DAT_DLY__SHIFT 0x0
+#define MC_SEQ_WR_CTL_D1__DQS_DLY_MASK 0xf0
+#define MC_SEQ_WR_CTL_D1__DQS_DLY__SHIFT 0x4
+#define MC_SEQ_WR_CTL_D1__DQS_XTR_MASK 0x100
+#define MC_SEQ_WR_CTL_D1__DQS_XTR__SHIFT 0x8
+#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY_MASK 0x200
+#define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY__SHIFT 0x9
+#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY_MASK 0x400
+#define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY__SHIFT 0xa
+#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY_MASK 0x800
+#define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY__SHIFT 0xb
+#define MC_SEQ_WR_CTL_D1__OEN_DLY_MASK 0xf000
+#define MC_SEQ_WR_CTL_D1__OEN_DLY__SHIFT 0xc
+#define MC_SEQ_WR_CTL_D1__OEN_EXT_MASK 0xf0000
+#define MC_SEQ_WR_CTL_D1__OEN_EXT__SHIFT 0x10
+#define MC_SEQ_WR_CTL_D1__OEN_SEL_MASK 0x300000
+#define MC_SEQ_WR_CTL_D1__OEN_SEL__SHIFT 0x14
+#define MC_SEQ_WR_CTL_D1__ODT_DLY_MASK 0xf000000
+#define MC_SEQ_WR_CTL_D1__ODT_DLY__SHIFT 0x18
+#define MC_SEQ_WR_CTL_D1__ODT_EXT_MASK 0x10000000
+#define MC_SEQ_WR_CTL_D1__ODT_EXT__SHIFT 0x1c
+#define MC_SEQ_WR_CTL_D1__ADR_DLY_MASK 0x20000000
+#define MC_SEQ_WR_CTL_D1__ADR_DLY__SHIFT 0x1d
+#define MC_SEQ_WR_CTL_D1__CMD_DLY_MASK 0x40000000
+#define MC_SEQ_WR_CTL_D1__CMD_DLY__SHIFT 0x1e
+#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0_MASK 0x1
+#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0__SHIFT 0x0
+#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0_MASK 0x2
+#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0__SHIFT 0x1
+#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0_MASK 0x4
+#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0__SHIFT 0x2
+#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1_MASK 0x8
+#define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1__SHIFT 0x3
+#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1_MASK 0x10
+#define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1__SHIFT 0x4
+#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1_MASK 0x20
+#define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1__SHIFT 0x5
+#define MC_SEQ_WR_CTL_2__WCDR_EN_MASK 0x40
+#define MC_SEQ_WR_CTL_2__WCDR_EN__SHIFT 0x6
+#define MC_SEQ_CMD__ADR_MASK 0xffff
+#define MC_SEQ_CMD__ADR__SHIFT 0x0
+#define MC_SEQ_CMD__MOP_MASK 0xf0000
+#define MC_SEQ_CMD__MOP__SHIFT 0x10
+#define MC_SEQ_CMD__END_MASK 0x100000
+#define MC_SEQ_CMD__END__SHIFT 0x14
+#define MC_SEQ_CMD__CSB_MASK 0x600000
+#define MC_SEQ_CMD__CSB__SHIFT 0x15
+#define MC_SEQ_CMD__CHAN0_MASK 0x1000000
+#define MC_SEQ_CMD__CHAN0__SHIFT 0x18
+#define MC_SEQ_CMD__CHAN1_MASK 0x2000000
+#define MC_SEQ_CMD__CHAN1__SHIFT 0x19
+#define MC_SEQ_CMD__ADR_MSB1_MASK 0x10000000
+#define MC_SEQ_CMD__ADR_MSB1__SHIFT 0x1c
+#define MC_SEQ_CMD__ADR_MSB0_MASK 0x20000000
+#define MC_SEQ_CMD__ADR_MSB0__SHIFT 0x1d
+#define MC_PMG_CMD_EMRS__ADR_MASK 0xffff
+#define MC_PMG_CMD_EMRS__ADR__SHIFT 0x0
+#define MC_PMG_CMD_EMRS__MOP_MASK 0x70000
+#define MC_PMG_CMD_EMRS__MOP__SHIFT 0x10
+#define MC_PMG_CMD_EMRS__BNK_MSB_MASK 0x80000
+#define MC_PMG_CMD_EMRS__BNK_MSB__SHIFT 0x13
+#define MC_PMG_CMD_EMRS__END_MASK 0x100000
+#define MC_PMG_CMD_EMRS__END__SHIFT 0x14
+#define MC_PMG_CMD_EMRS__CSB_MASK 0x600000
+#define MC_PMG_CMD_EMRS__CSB__SHIFT 0x15
+#define MC_PMG_CMD_EMRS__ADR_MSB1_MASK 0x10000000
+#define MC_PMG_CMD_EMRS__ADR_MSB1__SHIFT 0x1c
+#define MC_PMG_CMD_EMRS__ADR_MSB0_MASK 0x20000000
+#define MC_PMG_CMD_EMRS__ADR_MSB0__SHIFT 0x1d
+#define MC_PMG_CMD_MRS__ADR_MASK 0xffff
+#define MC_PMG_CMD_MRS__ADR__SHIFT 0x0
+#define MC_PMG_CMD_MRS__MOP_MASK 0x70000
+#define MC_PMG_CMD_MRS__MOP__SHIFT 0x10
+#define MC_PMG_CMD_MRS__BNK_MSB_MASK 0x80000
+#define MC_PMG_CMD_MRS__BNK_MSB__SHIFT 0x13
+#define MC_PMG_CMD_MRS__END_MASK 0x100000
+#define MC_PMG_CMD_MRS__END__SHIFT 0x14
+#define MC_PMG_CMD_MRS__CSB_MASK 0x600000
+#define MC_PMG_CMD_MRS__CSB__SHIFT 0x15
+#define MC_PMG_CMD_MRS__ADR_MSB1_MASK 0x10000000
+#define MC_PMG_CMD_MRS__ADR_MSB1__SHIFT 0x1c
+#define MC_PMG_CMD_MRS__ADR_MSB0_MASK 0x20000000
+#define MC_PMG_CMD_MRS__ADR_MSB0__SHIFT 0x1d
+#define MC_PMG_CMD_MRS1__ADR_MASK 0xffff
+#define MC_PMG_CMD_MRS1__ADR__SHIFT 0x0
+#define MC_PMG_CMD_MRS1__MOP_MASK 0x70000
+#define MC_PMG_CMD_MRS1__MOP__SHIFT 0x10
+#define MC_PMG_CMD_MRS1__BNK_MSB_MASK 0x80000
+#define MC_PMG_CMD_MRS1__BNK_MSB__SHIFT 0x13
+#define MC_PMG_CMD_MRS1__END_MASK 0x100000
+#define MC_PMG_CMD_MRS1__END__SHIFT 0x14
+#define MC_PMG_CMD_MRS1__CSB_MASK 0x600000
+#define MC_PMG_CMD_MRS1__CSB__SHIFT 0x15
+#define MC_PMG_CMD_MRS1__ADR_MSB1_MASK 0x10000000
+#define MC_PMG_CMD_MRS1__ADR_MSB1__SHIFT 0x1c
+#define MC_PMG_CMD_MRS1__ADR_MSB0_MASK 0x20000000
+#define MC_PMG_CMD_MRS1__ADR_MSB0__SHIFT 0x1d
+#define MC_PMG_CMD_MRS2__ADR_MASK 0xffff
+#define MC_PMG_CMD_MRS2__ADR__SHIFT 0x0
+#define MC_PMG_CMD_MRS2__MOP_MASK 0x70000
+#define MC_PMG_CMD_MRS2__MOP__SHIFT 0x10
+#define MC_PMG_CMD_MRS2__BNK_MSB_MASK 0x80000
+#define MC_PMG_CMD_MRS2__BNK_MSB__SHIFT 0x13
+#define MC_PMG_CMD_MRS2__END_MASK 0x100000
+#define MC_PMG_CMD_MRS2__END__SHIFT 0x14
+#define MC_PMG_CMD_MRS2__CSB_MASK 0x600000
+#define MC_PMG_CMD_MRS2__CSB__SHIFT 0x15
+#define MC_PMG_CMD_MRS2__ADR_MSB1_MASK 0x10000000
+#define MC_PMG_CMD_MRS2__ADR_MSB1__SHIFT 0x1c
+#define MC_PMG_CMD_MRS2__ADR_MSB0_MASK 0x20000000
+#define MC_PMG_CMD_MRS2__ADR_MSB0__SHIFT 0x1d
+#define MC_PMG_CFG__SYC_CLK_MASK 0x1
+#define MC_PMG_CFG__SYC_CLK__SHIFT 0x0
+#define MC_PMG_CFG__RST_MRS_MASK 0x2
+#define MC_PMG_CFG__RST_MRS__SHIFT 0x1
+#define MC_PMG_CFG__RST_EMRS_MASK 0x4
+#define MC_PMG_CFG__RST_EMRS__SHIFT 0x2
+#define MC_PMG_CFG__TRI_MIO_MASK 0x8
+#define MC_PMG_CFG__TRI_MIO__SHIFT 0x3
+#define MC_PMG_CFG__XSR_TMR_MASK 0xf0
+#define MC_PMG_CFG__XSR_TMR__SHIFT 0x4
+#define MC_PMG_CFG__RST_MRS1_MASK 0x100
+#define MC_PMG_CFG__RST_MRS1__SHIFT 0x8
+#define MC_PMG_CFG__RST_MRS2_MASK 0x200
+#define MC_PMG_CFG__RST_MRS2__SHIFT 0x9
+#define MC_PMG_CFG__DPM_WAKE_MASK 0x400
+#define MC_PMG_CFG__DPM_WAKE__SHIFT 0xa
+#define MC_PMG_CFG__RFS_SRX_MASK 0x1000
+#define MC_PMG_CFG__RFS_SRX__SHIFT 0xc
+#define MC_PMG_CFG__PREA_SRX_MASK 0x2000
+#define MC_PMG_CFG__PREA_SRX__SHIFT 0xd
+#define MC_PMG_CFG__MRS_WAIT_CNT_MASK 0xf0000
+#define MC_PMG_CFG__MRS_WAIT_CNT__SHIFT 0x10
+#define MC_PMG_CFG__WRITE_DURING_DLOCK_MASK 0x100000
+#define MC_PMG_CFG__WRITE_DURING_DLOCK__SHIFT 0x14
+#define MC_PMG_CFG__YCLK_ON_MASK 0x200000
+#define MC_PMG_CFG__YCLK_ON__SHIFT 0x15
+#define MC_PMG_CFG__EARLY_ACK_ACPI_MASK 0x400000
+#define MC_PMG_CFG__EARLY_ACK_ACPI__SHIFT 0x16
+#define MC_PMG_CFG__RXPDNB_MASK 0x2000000
+#define MC_PMG_CFG__RXPDNB__SHIFT 0x19
+#define MC_PMG_CFG__ZQCL_SEND_MASK 0xc000000
+#define MC_PMG_CFG__ZQCL_SEND__SHIFT 0x1a
+#define MC_PMG_AUTO_CMD__ADR_MASK 0x1ffff
+#define MC_PMG_AUTO_CMD__ADR__SHIFT 0x0
+#define MC_PMG_AUTO_CMD__ADR_MSB1_MASK 0x10000000
+#define MC_PMG_AUTO_CMD__ADR_MSB1__SHIFT 0x1c
+#define MC_PMG_AUTO_CMD__ADR_MSB0_MASK 0x20000000
+#define MC_PMG_AUTO_CMD__ADR_MSB0__SHIFT 0x1d
+#define MC_PMG_AUTO_CFG__SYC_CLK_MASK 0x1
+#define MC_PMG_AUTO_CFG__SYC_CLK__SHIFT 0x0
+#define MC_PMG_AUTO_CFG__RST_MRS_MASK 0x2
+#define MC_PMG_AUTO_CFG__RST_MRS__SHIFT 0x1
+#define MC_PMG_AUTO_CFG__TRI_MIO_MASK 0x4
+#define MC_PMG_AUTO_CFG__TRI_MIO__SHIFT 0x2
+#define MC_PMG_AUTO_CFG__XSR_TMR_MASK 0xf0
+#define MC_PMG_AUTO_CFG__XSR_TMR__SHIFT 0x4
+#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF_MASK 0x100
+#define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF__SHIFT 0x8
+#define MC_PMG_AUTO_CFG__SS_S_SLF_MASK 0x200
+#define MC_PMG_AUTO_CFG__SS_S_SLF__SHIFT 0x9
+#define MC_PMG_AUTO_CFG__SCDS_MODE_MASK 0x400
+#define MC_PMG_AUTO_CFG__SCDS_MODE__SHIFT 0xa
+#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP_MASK 0x800
+#define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP__SHIFT 0xb
+#define MC_PMG_AUTO_CFG__RFS_SRX_MASK 0x1000
+#define MC_PMG_AUTO_CFG__RFS_SRX__SHIFT 0xc
+#define MC_PMG_AUTO_CFG__PREA_SRX_MASK 0x2000
+#define MC_PMG_AUTO_CFG__PREA_SRX__SHIFT 0xd
+#define MC_PMG_AUTO_CFG__STUTTER_EN_MASK 0x4000
+#define MC_PMG_AUTO_CFG__STUTTER_EN__SHIFT 0xe
+#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0_MASK 0x8000
+#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0__SHIFT 0xf
+#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT_MASK 0xf0000
+#define MC_PMG_AUTO_CFG__MRS_WAIT_CNT__SHIFT 0x10
+#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK_MASK 0x100000
+#define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK__SHIFT 0x14
+#define MC_PMG_AUTO_CFG__YCLK_ON_MASK 0x200000
+#define MC_PMG_AUTO_CFG__YCLK_ON__SHIFT 0x15
+#define MC_PMG_AUTO_CFG__RXPDNB_MASK 0x400000
+#define MC_PMG_AUTO_CFG__RXPDNB__SHIFT 0x16
+#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1_MASK 0x800000
+#define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1__SHIFT 0x17
+#define MC_PMG_AUTO_CFG__DLL_CNT_MASK 0xff000000
+#define MC_PMG_AUTO_CFG__DLL_CNT__SHIFT 0x18
+#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE_MASK 0x1f
+#define MC_IMP_CNTL__MEM_IO_UPDATE_RATE__SHIFT 0x0
+#define MC_IMP_CNTL__CAL_VREF_SEL_MASK 0x20
+#define MC_IMP_CNTL__CAL_VREF_SEL__SHIFT 0x5
+#define MC_IMP_CNTL__CAL_VREFMODE_MASK 0x40
+#define MC_IMP_CNTL__CAL_VREFMODE__SHIFT 0x6
+#define MC_IMP_CNTL__TIMEOUT_ERR_MASK 0x100
+#define MC_IMP_CNTL__TIMEOUT_ERR__SHIFT 0x8
+#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR_MASK 0x200
+#define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR__SHIFT 0x9
+#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT_MASK 0xe000
+#define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT__SHIFT 0xd
+#define MC_IMP_CNTL__CAL_VREF_MASK 0x7f0000
+#define MC_IMP_CNTL__CAL_VREF__SHIFT 0x10
+#define MC_IMP_CNTL__CAL_WHEN_IDLE_MASK 0x20000000
+#define MC_IMP_CNTL__CAL_WHEN_IDLE__SHIFT 0x1d
+#define MC_IMP_CNTL__CAL_WHEN_REFRESH_MASK 0x40000000
+#define MC_IMP_CNTL__CAL_WHEN_REFRESH__SHIFT 0x1e
+#define MC_IMP_CNTL__CAL_PWRON_MASK 0x80000000
+#define MC_IMP_CNTL__CAL_PWRON__SHIFT 0x1f
+#define MC_IMP_DEBUG__TSTARTUP_CNTR_MASK 0xff
+#define MC_IMP_DEBUG__TSTARTUP_CNTR__SHIFT 0x0
+#define MC_IMP_DEBUG__TIMEOUT_CNTR_MASK 0xff00
+#define MC_IMP_DEBUG__TIMEOUT_CNTR__SHIFT 0x8
+#define MC_IMP_DEBUG__PMVCAL_RESERVED_MASK 0xfff0000
+#define MC_IMP_DEBUG__PMVCAL_RESERVED__SHIFT 0x10
+#define MC_IMP_DEBUG__DEBUG_CAL_EN_MASK 0x10000000
+#define MC_IMP_DEBUG__DEBUG_CAL_EN__SHIFT 0x1c
+#define MC_IMP_DEBUG__DEBUG_CAL_START_MASK 0x20000000
+#define MC_IMP_DEBUG__DEBUG_CAL_START__SHIFT 0x1d
+#define MC_IMP_DEBUG__DEBUG_CAL_INTR_MASK 0x40000000
+#define MC_IMP_DEBUG__DEBUG_CAL_INTR__SHIFT 0x1e
+#define MC_IMP_DEBUG__DEBUG_CAL_DONE_MASK 0x80000000
+#define MC_IMP_DEBUG__DEBUG_CAL_DONE__SHIFT 0x1f
+#define MC_IMP_STATUS__PSTR_CAL_MASK 0xff
+#define MC_IMP_STATUS__PSTR_CAL__SHIFT 0x0
+#define MC_IMP_STATUS__PSTR_ACCUM_VAL_MASK 0xff00
+#define MC_IMP_STATUS__PSTR_ACCUM_VAL__SHIFT 0x8
+#define MC_IMP_STATUS__NSTR_CAL_MASK 0xff0000
+#define MC_IMP_STATUS__NSTR_CAL__SHIFT 0x10
+#define MC_IMP_STATUS__NSTR_ACCUM_VAL_MASK 0xff000000
+#define MC_IMP_STATUS__NSTR_ACCUM_VAL__SHIFT 0x18
+#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR_MASK 0xff
+#define MC_IMP_DQ_STATUS__CH0_DQ_PSTR__SHIFT 0x0
+#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR_MASK 0xff00
+#define MC_IMP_DQ_STATUS__CH0_DQ_NSTR__SHIFT 0x8
+#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR_MASK 0xff0000
+#define MC_IMP_DQ_STATUS__CH1_DQ_PSTR__SHIFT 0x10
+#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR_MASK 0xff000000
+#define MC_IMP_DQ_STATUS__CH1_DQ_NSTR__SHIFT 0x18
+#define MC_SEQ_WCDR_CTRL__WCDR_PRE_MASK 0xff
+#define MC_SEQ_WCDR_CTRL__WCDR_PRE__SHIFT 0x0
+#define MC_SEQ_WCDR_CTRL__WCDR_TIM_MASK 0xf00
+#define MC_SEQ_WCDR_CTRL__WCDR_TIM__SHIFT 0x8
+#define MC_SEQ_WCDR_CTRL__WR_EN_MASK 0x1000
+#define MC_SEQ_WCDR_CTRL__WR_EN__SHIFT 0xc
+#define MC_SEQ_WCDR_CTRL__RD_EN_MASK 0x2000
+#define MC_SEQ_WCDR_CTRL__RD_EN__SHIFT 0xd
+#define MC_SEQ_WCDR_CTRL__AREF_EN_MASK 0x4000
+#define MC_SEQ_WCDR_CTRL__AREF_EN__SHIFT 0xe
+#define MC_SEQ_WCDR_CTRL__TRAIN_EN_MASK 0x8000
+#define MC_SEQ_WCDR_CTRL__TRAIN_EN__SHIFT 0xf
+#define MC_SEQ_WCDR_CTRL__TWCDRL_MASK 0xf0000
+#define MC_SEQ_WCDR_CTRL__TWCDRL__SHIFT 0x10
+#define MC_SEQ_WCDR_CTRL__PRBS_EN_MASK 0x100000
+#define MC_SEQ_WCDR_CTRL__PRBS_EN__SHIFT 0x14
+#define MC_SEQ_WCDR_CTRL__PRBS_RST_MASK 0x200000
+#define MC_SEQ_WCDR_CTRL__PRBS_RST__SHIFT 0x15
+#define MC_SEQ_WCDR_CTRL__PREAMBLE_MASK 0xf000000
+#define MC_SEQ_WCDR_CTRL__PREAMBLE__SHIFT 0x18
+#define MC_SEQ_WCDR_CTRL__PRE_MASK_MASK 0xf0000000
+#define MC_SEQ_WCDR_CTRL__PRE_MASK__SHIFT 0x1c
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN_MASK 0x1
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN__SHIFT 0x0
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN_MASK 0x2
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN__SHIFT 0x1
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN_MASK 0x4
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN__SHIFT 0x2
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN_MASK 0x8
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN__SHIFT 0x3
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN_MASK 0x10
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN__SHIFT 0x4
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN_MASK 0x20
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN__SHIFT 0x5
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN_MASK 0x40
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN__SHIFT 0x6
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN_MASK 0x80
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN__SHIFT 0x7
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN_MASK 0x100
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN__SHIFT 0x8
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN_MASK 0x200
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN__SHIFT 0x9
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN_MASK 0x400
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN__SHIFT 0xa
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN_MASK 0x800
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN__SHIFT 0xb
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN_MASK 0x1000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN__SHIFT 0xc
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN_MASK 0x2000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN__SHIFT 0xd
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN_MASK 0x4000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN__SHIFT 0xe
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN_MASK 0x8000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN__SHIFT 0xf
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN_MASK 0x10000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN__SHIFT 0x10
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN_MASK 0x20000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN__SHIFT 0x11
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN_MASK 0x40000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN__SHIFT 0x12
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN_MASK 0x80000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN__SHIFT 0x13
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY_MASK 0x100000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY__SHIFT 0x14
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0_MASK 0x200000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0__SHIFT 0x15
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1_MASK 0x400000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1__SHIFT 0x16
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0_MASK 0x1000000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0__SHIFT 0x18
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0_MASK 0x2000000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0__SHIFT 0x19
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1_MASK 0x4000000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1__SHIFT 0x1a
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1_MASK 0x8000000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1__SHIFT 0x1b
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP_MASK 0x10000000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP__SHIFT 0x1c
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP_MASK 0x20000000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP__SHIFT 0x1d
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK 0x40000000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0__SHIFT 0x1e
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK 0x80000000
+#define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1__SHIFT 0x1f
+#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD_MASK 0xffff
+#define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD__SHIFT 0x0
+#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD_MASK 0xffff0000
+#define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD__SHIFT 0x10
+#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD_MASK 0xffffffff
+#define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD__SHIFT 0x0
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS_MASK 0x1
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS__SHIFT 0x0
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS_MASK 0x2
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS__SHIFT 0x1
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS_MASK 0x4
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS__SHIFT 0x2
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI_MASK 0x8
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI__SHIFT 0x3
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR_MASK 0x30
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR__SHIFT 0x4
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS_MASK 0x100
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x8
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS_MASK 0x200
+#define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x9
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP_MASK 0x1
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP__SHIFT 0x0
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP_MASK 0x2
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP__SHIFT 0x1
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP_MASK 0x4
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP__SHIFT 0x2
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP_MASK 0x8
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP__SHIFT 0x3
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP_MASK 0x10
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP__SHIFT 0x4
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP_MASK 0x20
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP__SHIFT 0x5
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP_MASK 0x80
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP_MASK 0x2000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP__SHIFT 0xd
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP_MASK 0x4000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP__SHIFT 0xe
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP_MASK 0x8000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP__SHIFT 0xf
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP_MASK 0x20000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP__SHIFT 0x11
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP_MASK 0x40000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP__SHIFT 0x12
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP_MASK 0x80000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP__SHIFT 0x13
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP_MASK 0x100000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP__SHIFT 0x14
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP_MASK 0x200000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP_MASK 0x400000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP_MASK 0x800000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP__SHIFT 0x17
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP_MASK 0x1000000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP__SHIFT 0x18
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP_MASK 0x2000000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP__SHIFT 0x19
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP_MASK 0x4000000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP__SHIFT 0x1a
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__SREG_WAKEUP_MASK 0x8000000
+#define MC_SEQ_TRAIN_WAKEUP_EDGE__SREG_WAKEUP__SHIFT 0x1b
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP_MASK 0x1
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP__SHIFT 0x0
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP_MASK 0x2
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP__SHIFT 0x1
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP_MASK 0x4
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP__SHIFT 0x2
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP_MASK 0x8
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP__SHIFT 0x3
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP_MASK 0x10
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP__SHIFT 0x4
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP_MASK 0x20
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP__SHIFT 0x5
+#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
+#define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
+#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP_MASK 0x80
+#define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
+#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
+#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP_MASK 0x2000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP__SHIFT 0xd
+#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP_MASK 0x4000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP__SHIFT 0xe
+#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP_MASK 0x8000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP__SHIFT 0xf
+#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP_MASK 0x20000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP__SHIFT 0x11
+#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP_MASK 0x40000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP__SHIFT 0x12
+#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP_MASK 0x80000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP__SHIFT 0x13
+#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP_MASK 0x100000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP__SHIFT 0x14
+#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP_MASK 0x200000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
+#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP_MASK 0x400000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
+#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP_MASK 0x800000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP__SHIFT 0x17
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP_MASK 0x1000000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP__SHIFT 0x18
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP_MASK 0x2000000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP__SHIFT 0x19
+#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP_MASK 0x4000000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP__SHIFT 0x1a
+#define MC_SEQ_TRAIN_WAKEUP_MASK__SREG_WAKEUP_MASK 0x8000000
+#define MC_SEQ_TRAIN_WAKEUP_MASK__SREG_WAKEUP__SHIFT 0x1b
+#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP_MASK 0x1
+#define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP__SHIFT 0x0
+#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP_MASK 0x2
+#define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP__SHIFT 0x1
+#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP_MASK 0x4
+#define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP__SHIFT 0x2
+#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP_MASK 0x8
+#define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP__SHIFT 0x3
+#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP_MASK 0x10
+#define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP__SHIFT 0x4
+#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP_MASK 0x20
+#define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP__SHIFT 0x5
+#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
+#define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
+#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP_MASK 0x80
+#define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
+#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
+#define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
+#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
+#define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
+#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
+#define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
+#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
+#define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
+#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
+#define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
+#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP_MASK 0x2000
+#define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP__SHIFT 0xd
+#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP_MASK 0x4000
+#define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP__SHIFT 0xe
+#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP_MASK 0x8000
+#define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP__SHIFT 0xf
+#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP_MASK 0x20000
+#define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP__SHIFT 0x11
+#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP_MASK 0x40000
+#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP__SHIFT 0x12
+#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP_MASK 0x80000
+#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP__SHIFT 0x13
+#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP_MASK 0x100000
+#define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP__SHIFT 0x14
+#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP_MASK 0x200000
+#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
+#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP_MASK 0x400000
+#define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
+#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP_MASK 0x800000
+#define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP__SHIFT 0x17
+#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP_MASK 0x1000000
+#define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP__SHIFT 0x18
+#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP_MASK 0x2000000
+#define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP__SHIFT 0x19
+#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP_MASK 0x4000000
+#define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP__SHIFT 0x1a
+#define MC_SEQ_TRAIN_CAPTURE__SREG_WAKEUP_MASK 0x8000000
+#define MC_SEQ_TRAIN_CAPTURE__SREG_WAKEUP__SHIFT 0x1b
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP_MASK 0x1
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP__SHIFT 0x0
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP_MASK 0x2
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP__SHIFT 0x1
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP_MASK 0x4
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP__SHIFT 0x2
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP_MASK 0x8
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP__SHIFT 0x3
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP_MASK 0x10
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP__SHIFT 0x4
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP_MASK 0x20
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP__SHIFT 0x5
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP_MASK 0x80
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP_MASK 0x2000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP__SHIFT 0xd
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP_MASK 0x4000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP__SHIFT 0xe
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP_MASK 0x8000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP__SHIFT 0xf
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL_MASK 0x10000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL__SHIFT 0x10
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP_MASK 0x20000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP__SHIFT 0x11
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP_MASK 0x40000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP__SHIFT 0x12
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP_MASK 0x80000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP__SHIFT 0x13
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP_MASK 0x100000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP__SHIFT 0x14
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP_MASK 0x200000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP_MASK 0x400000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP_MASK 0x800000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP__SHIFT 0x17
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP_MASK 0x1000000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP__SHIFT 0x18
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP_MASK 0x2000000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP__SHIFT 0x19
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP_MASK 0x4000000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP__SHIFT 0x1a
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SREG_WAKEUP_MASK 0x8000000
+#define MC_SEQ_TRAIN_WAKEUP_CLEAR__SREG_WAKEUP__SHIFT 0x1b
+#define MC_SEQ_TRAIN_TIMING__TWT2RT_MASK 0x1f
+#define MC_SEQ_TRAIN_TIMING__TWT2RT__SHIFT 0x0
+#define MC_SEQ_TRAIN_TIMING__TARF2T_MASK 0x3e0
+#define MC_SEQ_TRAIN_TIMING__TARF2T__SHIFT 0x5
+#define MC_SEQ_TRAIN_TIMING__TT2ROW_MASK 0x7c00
+#define MC_SEQ_TRAIN_TIMING__TT2ROW__SHIFT 0xa
+#define MC_SEQ_TRAIN_TIMING__TLD2LD_MASK 0xf8000
+#define MC_SEQ_TRAIN_TIMING__TLD2LD__SHIFT 0xf
+#define MC_TRAIN_EDCCDR_R_D0__EDC0_MASK 0xff
+#define MC_TRAIN_EDCCDR_R_D0__EDC0__SHIFT 0x0
+#define MC_TRAIN_EDCCDR_R_D0__EDC1_MASK 0xff00
+#define MC_TRAIN_EDCCDR_R_D0__EDC1__SHIFT 0x8
+#define MC_TRAIN_EDCCDR_R_D0__EDC2_MASK 0xff0000
+#define MC_TRAIN_EDCCDR_R_D0__EDC2__SHIFT 0x10
+#define MC_TRAIN_EDCCDR_R_D0__EDC3_MASK 0xff000000
+#define MC_TRAIN_EDCCDR_R_D0__EDC3__SHIFT 0x18
+#define MC_TRAIN_EDCCDR_R_D1__EDC0_MASK 0xff
+#define MC_TRAIN_EDCCDR_R_D1__EDC0__SHIFT 0x0
+#define MC_TRAIN_EDCCDR_R_D1__EDC1_MASK 0xff00
+#define MC_TRAIN_EDCCDR_R_D1__EDC1__SHIFT 0x8
+#define MC_TRAIN_EDCCDR_R_D1__EDC2_MASK 0xff0000
+#define MC_TRAIN_EDCCDR_R_D1__EDC2__SHIFT 0x10
+#define MC_TRAIN_EDCCDR_R_D1__EDC3_MASK 0xff000000
+#define MC_TRAIN_EDCCDR_R_D1__EDC3__SHIFT 0x18
+#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS_MASK 0xffffffff
+#define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS__SHIFT 0x0
+#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS_MASK 0xf
+#define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS__SHIFT 0x0
+#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS_MASK 0xf0
+#define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS__SHIFT 0x4
+#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS_MASK 0xf00
+#define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS__SHIFT 0x8
+#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS_MASK 0xf000
+#define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS__SHIFT 0xc
+#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR_MASK 0x10000000
+#define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR__SHIFT 0x1c
+#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR_MASK 0x20000000
+#define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR__SHIFT 0x1d
+#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR_MASK 0x40000000
+#define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR__SHIFT 0x1e
+#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS_MASK 0x1
+#define MC_TRAIN_PRBSERR_2_D0__CK_STATUS__SHIFT 0x0
+#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS_MASK 0x2
+#define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS__SHIFT 0x1
+#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS_MASK 0x30
+#define MC_TRAIN_PRBSERR_2_D0__CS_STATUS__SHIFT 0x4
+#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS_MASK 0x100
+#define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS__SHIFT 0x8
+#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS_MASK 0x200
+#define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS__SHIFT 0x9
+#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS_MASK 0x400
+#define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS__SHIFT 0xa
+#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS_MASK 0x800
+#define MC_TRAIN_PRBSERR_2_D0__WE_STATUS__SHIFT 0xb
+#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS_MASK 0x3ff0000
+#define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS__SHIFT 0x10
+#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS_MASK 0x10000000
+#define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS__SHIFT 0x1c
+#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT_MASK 0xffff
+#define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT__SHIFT 0x0
+#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT_MASK 0xffff0000
+#define MC_TRAIN_EDC_STATUS_D0__REDC_CNT__SHIFT 0x10
+#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS_MASK 0xffffffff
+#define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS__SHIFT 0x0
+#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS_MASK 0xf
+#define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS__SHIFT 0x0
+#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS_MASK 0xf0
+#define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS__SHIFT 0x4
+#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS_MASK 0xf00
+#define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS__SHIFT 0x8
+#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS_MASK 0xf000
+#define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS__SHIFT 0xc
+#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR_MASK 0x10000000
+#define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR__SHIFT 0x1c
+#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR_MASK 0x20000000
+#define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR__SHIFT 0x1d
+#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR_MASK 0x40000000
+#define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR__SHIFT 0x1e
+#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS_MASK 0x1
+#define MC_TRAIN_PRBSERR_2_D1__CK_STATUS__SHIFT 0x0
+#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS_MASK 0x2
+#define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS__SHIFT 0x1
+#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS_MASK 0x30
+#define MC_TRAIN_PRBSERR_2_D1__CS_STATUS__SHIFT 0x4
+#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS_MASK 0x100
+#define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS__SHIFT 0x8
+#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS_MASK 0x200
+#define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS__SHIFT 0x9
+#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS_MASK 0x400
+#define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS__SHIFT 0xa
+#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS_MASK 0x800
+#define MC_TRAIN_PRBSERR_2_D1__WE_STATUS__SHIFT 0xb
+#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS_MASK 0x3ff0000
+#define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS__SHIFT 0x10
+#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS_MASK 0x10000000
+#define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS__SHIFT 0x1c
+#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT_MASK 0xffff
+#define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT__SHIFT 0x0
+#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT_MASK 0xffff0000
+#define MC_TRAIN_EDC_STATUS_D1__REDC_CNT__SHIFT 0x10
+#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL_MASK 0x3
+#define MC_IO_TXCNTL_DPHY0_D0__BIASSEL__SHIFT 0x0
+#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY_MASK 0xc
+#define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY__SHIFT 0x2
+#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN_MASK 0x10
+#define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN__SHIFT 0x4
+#define MC_IO_TXCNTL_DPHY0_D0__QDR_MASK 0x20
+#define MC_IO_TXCNTL_DPHY0_D0__QDR__SHIFT 0x5
+#define MC_IO_TXCNTL_DPHY0_D0__EMPH_MASK 0x40
+#define MC_IO_TXCNTL_DPHY0_D0__EMPH__SHIFT 0x6
+#define MC_IO_TXCNTL_DPHY0_D0__TXPD_MASK 0x80
+#define MC_IO_TXCNTL_DPHY0_D0__TXPD__SHIFT 0x7
+#define MC_IO_TXCNTL_DPHY0_D0__PTERM_MASK 0xf00
+#define MC_IO_TXCNTL_DPHY0_D0__PTERM__SHIFT 0x8
+#define MC_IO_TXCNTL_DPHY0_D0__NTERM_MASK 0xf000
+#define MC_IO_TXCNTL_DPHY0_D0__NTERM__SHIFT 0xc
+#define MC_IO_TXCNTL_DPHY0_D0__PDRV_MASK 0xf0000
+#define MC_IO_TXCNTL_DPHY0_D0__PDRV__SHIFT 0x10
+#define MC_IO_TXCNTL_DPHY0_D0__NDRV_MASK 0xf00000
+#define MC_IO_TXCNTL_DPHY0_D0__NDRV__SHIFT 0x14
+#define MC_IO_TXCNTL_DPHY0_D0__TSTEN_MASK 0x1000000
+#define MC_IO_TXCNTL_DPHY0_D0__TSTEN__SHIFT 0x18
+#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN_MASK 0x2000000
+#define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN__SHIFT 0x19
+#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_MASK 0x4000000
+#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS__SHIFT 0x1a
+#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK_MASK 0x8000000
+#define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK__SHIFT 0x1b
+#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA_MASK 0xf0000000
+#define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA__SHIFT 0x1c
+#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL_MASK 0x3
+#define MC_IO_TXCNTL_DPHY1_D0__BIASSEL__SHIFT 0x0
+#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY_MASK 0xc
+#define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY__SHIFT 0x2
+#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN_MASK 0x10
+#define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN__SHIFT 0x4
+#define MC_IO_TXCNTL_DPHY1_D0__QDR_MASK 0x20
+#define MC_IO_TXCNTL_DPHY1_D0__QDR__SHIFT 0x5
+#define MC_IO_TXCNTL_DPHY1_D0__EMPH_MASK 0x40
+#define MC_IO_TXCNTL_DPHY1_D0__EMPH__SHIFT 0x6
+#define MC_IO_TXCNTL_DPHY1_D0__TXPD_MASK 0x80
+#define MC_IO_TXCNTL_DPHY1_D0__TXPD__SHIFT 0x7
+#define MC_IO_TXCNTL_DPHY1_D0__PTERM_MASK 0xf00
+#define MC_IO_TXCNTL_DPHY1_D0__PTERM__SHIFT 0x8
+#define MC_IO_TXCNTL_DPHY1_D0__NTERM_MASK 0xf000
+#define MC_IO_TXCNTL_DPHY1_D0__NTERM__SHIFT 0xc
+#define MC_IO_TXCNTL_DPHY1_D0__PDRV_MASK 0xf0000
+#define MC_IO_TXCNTL_DPHY1_D0__PDRV__SHIFT 0x10
+#define MC_IO_TXCNTL_DPHY1_D0__NDRV_MASK 0xf00000
+#define MC_IO_TXCNTL_DPHY1_D0__NDRV__SHIFT 0x14
+#define MC_IO_TXCNTL_DPHY1_D0__TSTEN_MASK 0x1000000
+#define MC_IO_TXCNTL_DPHY1_D0__TSTEN__SHIFT 0x18
+#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN_MASK 0x2000000
+#define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN__SHIFT 0x19
+#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_MASK 0x4000000
+#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS__SHIFT 0x1a
+#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK_MASK 0x8000000
+#define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK__SHIFT 0x1b
+#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA_MASK 0xf0000000
+#define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA__SHIFT 0x1c
+#define MC_IO_TXCNTL_APHY_D0__BIASSEL_MASK 0x3
+#define MC_IO_TXCNTL_APHY_D0__BIASSEL__SHIFT 0x0
+#define MC_IO_TXCNTL_APHY_D0__DRVDUTY_MASK 0xc
+#define MC_IO_TXCNTL_APHY_D0__DRVDUTY__SHIFT 0x2
+#define MC_IO_TXCNTL_APHY_D0__LOWCMEN_MASK 0x10
+#define MC_IO_TXCNTL_APHY_D0__LOWCMEN__SHIFT 0x4
+#define MC_IO_TXCNTL_APHY_D0__QDR_MASK 0x20
+#define MC_IO_TXCNTL_APHY_D0__QDR__SHIFT 0x5
+#define MC_IO_TXCNTL_APHY_D0__EMPH_MASK 0x40
+#define MC_IO_TXCNTL_APHY_D0__EMPH__SHIFT 0x6
+#define MC_IO_TXCNTL_APHY_D0__TXPD_MASK 0x80
+#define MC_IO_TXCNTL_APHY_D0__TXPD__SHIFT 0x7
+#define MC_IO_TXCNTL_APHY_D0__PTERM_MASK 0xf00
+#define MC_IO_TXCNTL_APHY_D0__PTERM__SHIFT 0x8
+#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL_MASK 0x1000
+#define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL__SHIFT 0xc
+#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK_MASK 0xe000
+#define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK__SHIFT 0xd
+#define MC_IO_TXCNTL_APHY_D0__PDRV_MASK 0xf0000
+#define MC_IO_TXCNTL_APHY_D0__PDRV__SHIFT 0x10
+#define MC_IO_TXCNTL_APHY_D0__NDRV_MASK 0x700000
+#define MC_IO_TXCNTL_APHY_D0__NDRV__SHIFT 0x14
+#define MC_IO_TXCNTL_APHY_D0__YCLKON_MASK 0x800000
+#define MC_IO_TXCNTL_APHY_D0__YCLKON__SHIFT 0x17
+#define MC_IO_TXCNTL_APHY_D0__TSTEN_MASK 0x1000000
+#define MC_IO_TXCNTL_APHY_D0__TSTEN__SHIFT 0x18
+#define MC_IO_TXCNTL_APHY_D0__TXRESET_MASK 0x2000000
+#define MC_IO_TXCNTL_APHY_D0__TXRESET__SHIFT 0x19
+#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_MASK 0x4000000
+#define MC_IO_TXCNTL_APHY_D0__TXBYPASS__SHIFT 0x1a
+#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA_MASK 0x38000000
+#define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA__SHIFT 0x1b
+#define MC_IO_TXCNTL_APHY_D0__CKE_BIT_MASK 0x40000000
+#define MC_IO_TXCNTL_APHY_D0__CKE_BIT__SHIFT 0x1e
+#define MC_IO_TXCNTL_APHY_D0__CKE_SEL_MASK 0x80000000
+#define MC_IO_TXCNTL_APHY_D0__CKE_SEL__SHIFT 0x1f
+#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL_MASK 0x3
+#define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL__SHIFT 0x0
+#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL_MASK 0x4
+#define MC_IO_RXCNTL_DPHY0_D0__RCVSEL__SHIFT 0x2
+#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB_MASK 0x8
+#define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB__SHIFT 0x3
+#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY_MASK 0x30
+#define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY__SHIFT 0x4
+#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB_MASK 0x40
+#define MC_IO_RXCNTL_DPHY0_D0__RXPDNB__SHIFT 0x6
+#define MC_IO_RXCNTL_DPHY0_D0__RXLP_MASK 0x80
+#define MC_IO_RXCNTL_DPHY0_D0__RXLP__SHIFT 0x7
+#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_MASK 0xf00
+#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL__SHIFT 0x8
+#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR_MASK 0xf000
+#define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR__SHIFT 0xc
+#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL_MASK 0x10000
+#define MC_IO_RXCNTL_DPHY0_D0__VREFSEL__SHIFT 0x10
+#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL_MASK 0xc0000
+#define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL__SHIFT 0x12
+#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0_MASK 0x700000
+#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0__SHIFT 0x14
+#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1_MASK 0x7000000
+#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1__SHIFT 0x18
+#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M_MASK 0x10000000
+#define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M__SHIFT 0x1c
+#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON_MASK 0x20000000
+#define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON__SHIFT 0x1d
+#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL_MASK 0xc0000000
+#define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL__SHIFT 0x1e
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB_MASK 0xf
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB__SHIFT 0x0
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB_MASK 0xf0
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB__SHIFT 0x4
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3_MASK 0xff00
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3__SHIFT 0x8
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2_MASK 0x10000
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2__SHIFT 0x10
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3_MASK 0x20000
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3__SHIFT 0x11
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1_MASK 0x40000
+#define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1__SHIFT 0x12
+#define MC_IO_RXCNTL1_DPHY0_D0__DLL_PWRGOOD_OVR_MASK 0x80000
+#define MC_IO_RXCNTL1_DPHY0_D0__DLL_PWRGOOD_OVR__SHIFT 0x13
+#define MC_IO_RXCNTL1_DPHY0_D0__DLL_VCTRLADC_EN_MASK 0x100000
+#define MC_IO_RXCNTL1_DPHY0_D0__DLL_VCTRLADC_EN__SHIFT 0x14
+#define MC_IO_RXCNTL1_DPHY0_D0__DLL_MSTR_STBY_MASK 0x200000
+#define MC_IO_RXCNTL1_DPHY0_D0__DLL_MSTR_STBY__SHIFT 0x15
+#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_EN_MASK 0x400000
+#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_EN__SHIFT 0x16
+#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_NXT_MASK 0x800000
+#define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_NXT__SHIFT 0x17
+#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK_MASK 0xe000000
+#define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK__SHIFT 0x19
+#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV_MASK 0xf0000000
+#define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV__SHIFT 0x1c
+#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL_MASK 0x3
+#define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL__SHIFT 0x0
+#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL_MASK 0x4
+#define MC_IO_RXCNTL_DPHY1_D0__RCVSEL__SHIFT 0x2
+#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB_MASK 0x8
+#define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB__SHIFT 0x3
+#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY_MASK 0x30
+#define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY__SHIFT 0x4
+#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB_MASK 0x40
+#define MC_IO_RXCNTL_DPHY1_D0__RXPDNB__SHIFT 0x6
+#define MC_IO_RXCNTL_DPHY1_D0__RXLP_MASK 0x80
+#define MC_IO_RXCNTL_DPHY1_D0__RXLP__SHIFT 0x7
+#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_MASK 0xf00
+#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL__SHIFT 0x8
+#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR_MASK 0xf000
+#define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR__SHIFT 0xc
+#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL_MASK 0x10000
+#define MC_IO_RXCNTL_DPHY1_D0__VREFSEL__SHIFT 0x10
+#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL_MASK 0xc0000
+#define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL__SHIFT 0x12
+#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0_MASK 0x700000
+#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0__SHIFT 0x14
+#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1_MASK 0x7000000
+#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1__SHIFT 0x18
+#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M_MASK 0x10000000
+#define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M__SHIFT 0x1c
+#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON_MASK 0x20000000
+#define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON__SHIFT 0x1d
+#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL_MASK 0xc0000000
+#define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL__SHIFT 0x1e
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB_MASK 0xf
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB__SHIFT 0x0
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB_MASK 0xf0
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB__SHIFT 0x4
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3_MASK 0xff00
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3__SHIFT 0x8
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2_MASK 0x10000
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2__SHIFT 0x10
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3_MASK 0x20000
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3__SHIFT 0x11
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1_MASK 0x40000
+#define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1__SHIFT 0x12
+#define MC_IO_RXCNTL1_DPHY1_D0__DLL_PWRGOOD_OVR_MASK 0x80000
+#define MC_IO_RXCNTL1_DPHY1_D0__DLL_PWRGOOD_OVR__SHIFT 0x13
+#define MC_IO_RXCNTL1_DPHY1_D0__DLL_VCTRLADC_EN_MASK 0x100000
+#define MC_IO_RXCNTL1_DPHY1_D0__DLL_VCTRLADC_EN__SHIFT 0x14
+#define MC_IO_RXCNTL1_DPHY1_D0__DLL_MSTR_STBY_MASK 0x200000
+#define MC_IO_RXCNTL1_DPHY1_D0__DLL_MSTR_STBY__SHIFT 0x15
+#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_EN_MASK 0x400000
+#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_EN__SHIFT 0x16
+#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_NXT_MASK 0x800000
+#define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_NXT__SHIFT 0x17
+#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK_MASK 0xe000000
+#define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK__SHIFT 0x19
+#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV_MASK 0xf0000000
+#define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV__SHIFT 0x1c
+#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D_MASK 0x3f
+#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D__SHIFT 0x0
+#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D_MASK 0xfc0
+#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D__SHIFT 0x6
+#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S_MASK 0x3f000
+#define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S__SHIFT 0xc
+#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S_MASK 0xfc0000
+#define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S__SHIFT 0x12
+#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL_MASK 0x1000000
+#define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL__SHIFT 0x18
+#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL_MASK 0x2000000
+#define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL__SHIFT 0x19
+#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL_MASK 0xc000000
+#define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x1a
+#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR_MASK 0x10000000
+#define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR__SHIFT 0x1c
+#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR_MASK 0x20000000
+#define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR__SHIFT 0x1d
+#define MC_IO_DPHY_STR_CNTL_D0__AUTO_LD_STR_MASK 0x40000000
+#define MC_IO_DPHY_STR_CNTL_D0__AUTO_LD_STR__SHIFT 0x1e
+#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A_MASK 0x3f
+#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A__SHIFT 0x0
+#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A_MASK 0xfc0
+#define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A__SHIFT 0x6
+#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD_MASK 0x3f000
+#define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD__SHIFT 0xc
+#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL_MASK 0x1000000
+#define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL__SHIFT 0x18
+#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL_MASK 0x2000000
+#define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL__SHIFT 0x19
+#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL_MASK 0xc000000
+#define MC_IO_APHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x1a
+#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR_MASK 0x10000000
+#define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR__SHIFT 0x1c
+#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR_MASK 0x20000000
+#define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR__SHIFT 0x1d
+#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL_MASK 0x3
+#define MC_IO_TXCNTL_DPHY0_D1__BIASSEL__SHIFT 0x0
+#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY_MASK 0xc
+#define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY__SHIFT 0x2
+#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN_MASK 0x10
+#define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN__SHIFT 0x4
+#define MC_IO_TXCNTL_DPHY0_D1__QDR_MASK 0x20
+#define MC_IO_TXCNTL_DPHY0_D1__QDR__SHIFT 0x5
+#define MC_IO_TXCNTL_DPHY0_D1__EMPH_MASK 0x40
+#define MC_IO_TXCNTL_DPHY0_D1__EMPH__SHIFT 0x6
+#define MC_IO_TXCNTL_DPHY0_D1__TXPD_MASK 0x80
+#define MC_IO_TXCNTL_DPHY0_D1__TXPD__SHIFT 0x7
+#define MC_IO_TXCNTL_DPHY0_D1__PTERM_MASK 0xf00
+#define MC_IO_TXCNTL_DPHY0_D1__PTERM__SHIFT 0x8
+#define MC_IO_TXCNTL_DPHY0_D1__NTERM_MASK 0xf000
+#define MC_IO_TXCNTL_DPHY0_D1__NTERM__SHIFT 0xc
+#define MC_IO_TXCNTL_DPHY0_D1__PDRV_MASK 0xf0000
+#define MC_IO_TXCNTL_DPHY0_D1__PDRV__SHIFT 0x10
+#define MC_IO_TXCNTL_DPHY0_D1__NDRV_MASK 0xf00000
+#define MC_IO_TXCNTL_DPHY0_D1__NDRV__SHIFT 0x14
+#define MC_IO_TXCNTL_DPHY0_D1__TSTEN_MASK 0x1000000
+#define MC_IO_TXCNTL_DPHY0_D1__TSTEN__SHIFT 0x18
+#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN_MASK 0x2000000
+#define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN__SHIFT 0x19
+#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_MASK 0x4000000
+#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS__SHIFT 0x1a
+#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK_MASK 0x8000000
+#define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK__SHIFT 0x1b
+#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA_MASK 0xf0000000
+#define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA__SHIFT 0x1c
+#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL_MASK 0x3
+#define MC_IO_TXCNTL_DPHY1_D1__BIASSEL__SHIFT 0x0
+#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY_MASK 0xc
+#define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY__SHIFT 0x2
+#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN_MASK 0x10
+#define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN__SHIFT 0x4
+#define MC_IO_TXCNTL_DPHY1_D1__QDR_MASK 0x20
+#define MC_IO_TXCNTL_DPHY1_D1__QDR__SHIFT 0x5
+#define MC_IO_TXCNTL_DPHY1_D1__EMPH_MASK 0x40
+#define MC_IO_TXCNTL_DPHY1_D1__EMPH__SHIFT 0x6
+#define MC_IO_TXCNTL_DPHY1_D1__TXPD_MASK 0x80
+#define MC_IO_TXCNTL_DPHY1_D1__TXPD__SHIFT 0x7
+#define MC_IO_TXCNTL_DPHY1_D1__PTERM_MASK 0xf00
+#define MC_IO_TXCNTL_DPHY1_D1__PTERM__SHIFT 0x8
+#define MC_IO_TXCNTL_DPHY1_D1__NTERM_MASK 0xf000
+#define MC_IO_TXCNTL_DPHY1_D1__NTERM__SHIFT 0xc
+#define MC_IO_TXCNTL_DPHY1_D1__PDRV_MASK 0xf0000
+#define MC_IO_TXCNTL_DPHY1_D1__PDRV__SHIFT 0x10
+#define MC_IO_TXCNTL_DPHY1_D1__NDRV_MASK 0xf00000
+#define MC_IO_TXCNTL_DPHY1_D1__NDRV__SHIFT 0x14
+#define MC_IO_TXCNTL_DPHY1_D1__TSTEN_MASK 0x1000000
+#define MC_IO_TXCNTL_DPHY1_D1__TSTEN__SHIFT 0x18
+#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN_MASK 0x2000000
+#define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN__SHIFT 0x19
+#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_MASK 0x4000000
+#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS__SHIFT 0x1a
+#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK_MASK 0x8000000
+#define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK__SHIFT 0x1b
+#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA_MASK 0xf0000000
+#define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA__SHIFT 0x1c
+#define MC_IO_TXCNTL_APHY_D1__BIASSEL_MASK 0x3
+#define MC_IO_TXCNTL_APHY_D1__BIASSEL__SHIFT 0x0
+#define MC_IO_TXCNTL_APHY_D1__DRVDUTY_MASK 0xc
+#define MC_IO_TXCNTL_APHY_D1__DRVDUTY__SHIFT 0x2
+#define MC_IO_TXCNTL_APHY_D1__LOWCMEN_MASK 0x10
+#define MC_IO_TXCNTL_APHY_D1__LOWCMEN__SHIFT 0x4
+#define MC_IO_TXCNTL_APHY_D1__QDR_MASK 0x20
+#define MC_IO_TXCNTL_APHY_D1__QDR__SHIFT 0x5
+#define MC_IO_TXCNTL_APHY_D1__EMPH_MASK 0x40
+#define MC_IO_TXCNTL_APHY_D1__EMPH__SHIFT 0x6
+#define MC_IO_TXCNTL_APHY_D1__TXPD_MASK 0x80
+#define MC_IO_TXCNTL_APHY_D1__TXPD__SHIFT 0x7
+#define MC_IO_TXCNTL_APHY_D1__PTERM_MASK 0xf00
+#define MC_IO_TXCNTL_APHY_D1__PTERM__SHIFT 0x8
+#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL_MASK 0x1000
+#define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL__SHIFT 0xc
+#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK_MASK 0xe000
+#define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK__SHIFT 0xd
+#define MC_IO_TXCNTL_APHY_D1__PDRV_MASK 0xf0000
+#define MC_IO_TXCNTL_APHY_D1__PDRV__SHIFT 0x10
+#define MC_IO_TXCNTL_APHY_D1__NDRV_MASK 0x700000
+#define MC_IO_TXCNTL_APHY_D1__NDRV__SHIFT 0x14
+#define MC_IO_TXCNTL_APHY_D1__YCLKON_MASK 0x800000
+#define MC_IO_TXCNTL_APHY_D1__YCLKON__SHIFT 0x17
+#define MC_IO_TXCNTL_APHY_D1__TSTEN_MASK 0x1000000
+#define MC_IO_TXCNTL_APHY_D1__TSTEN__SHIFT 0x18
+#define MC_IO_TXCNTL_APHY_D1__TXRESET_MASK 0x2000000
+#define MC_IO_TXCNTL_APHY_D1__TXRESET__SHIFT 0x19
+#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_MASK 0x4000000
+#define MC_IO_TXCNTL_APHY_D1__TXBYPASS__SHIFT 0x1a
+#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA_MASK 0x38000000
+#define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA__SHIFT 0x1b
+#define MC_IO_TXCNTL_APHY_D1__CKE_BIT_MASK 0x40000000
+#define MC_IO_TXCNTL_APHY_D1__CKE_BIT__SHIFT 0x1e
+#define MC_IO_TXCNTL_APHY_D1__CKE_SEL_MASK 0x80000000
+#define MC_IO_TXCNTL_APHY_D1__CKE_SEL__SHIFT 0x1f
+#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL_MASK 0x3
+#define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL__SHIFT 0x0
+#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL_MASK 0x4
+#define MC_IO_RXCNTL_DPHY0_D1__RCVSEL__SHIFT 0x2
+#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB_MASK 0x8
+#define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB__SHIFT 0x3
+#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY_MASK 0x30
+#define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY__SHIFT 0x4
+#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB_MASK 0x40
+#define MC_IO_RXCNTL_DPHY0_D1__RXPDNB__SHIFT 0x6
+#define MC_IO_RXCNTL_DPHY0_D1__RXLP_MASK 0x80
+#define MC_IO_RXCNTL_DPHY0_D1__RXLP__SHIFT 0x7
+#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_MASK 0xf00
+#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL__SHIFT 0x8
+#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR_MASK 0xf000
+#define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR__SHIFT 0xc
+#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL_MASK 0x10000
+#define MC_IO_RXCNTL_DPHY0_D1__VREFSEL__SHIFT 0x10
+#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL_MASK 0xc0000
+#define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL__SHIFT 0x12
+#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0_MASK 0x700000
+#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0__SHIFT 0x14
+#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1_MASK 0x7000000
+#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1__SHIFT 0x18
+#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M_MASK 0x10000000
+#define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M__SHIFT 0x1c
+#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON_MASK 0x20000000
+#define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON__SHIFT 0x1d
+#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL_MASK 0xc0000000
+#define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL__SHIFT 0x1e
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB_MASK 0xf
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB__SHIFT 0x0
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB_MASK 0xf0
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB__SHIFT 0x4
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3_MASK 0xff00
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3__SHIFT 0x8
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2_MASK 0x10000
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2__SHIFT 0x10
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3_MASK 0x20000
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3__SHIFT 0x11
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1_MASK 0x40000
+#define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1__SHIFT 0x12
+#define MC_IO_RXCNTL1_DPHY0_D1__DLL_PWRGOOD_OVR_MASK 0x80000
+#define MC_IO_RXCNTL1_DPHY0_D1__DLL_PWRGOOD_OVR__SHIFT 0x13
+#define MC_IO_RXCNTL1_DPHY0_D1__DLL_VCTRLADC_EN_MASK 0x100000
+#define MC_IO_RXCNTL1_DPHY0_D1__DLL_VCTRLADC_EN__SHIFT 0x14
+#define MC_IO_RXCNTL1_DPHY0_D1__DLL_MSTR_STBY_MASK 0x200000
+#define MC_IO_RXCNTL1_DPHY0_D1__DLL_MSTR_STBY__SHIFT 0x15
+#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_EN_MASK 0x400000
+#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_EN__SHIFT 0x16
+#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_NXT_MASK 0x800000
+#define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_NXT__SHIFT 0x17
+#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK_MASK 0xe000000
+#define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK__SHIFT 0x19
+#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV_MASK 0xf0000000
+#define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV__SHIFT 0x1c
+#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL_MASK 0x3
+#define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL__SHIFT 0x0
+#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL_MASK 0x4
+#define MC_IO_RXCNTL_DPHY1_D1__RCVSEL__SHIFT 0x2
+#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB_MASK 0x8
+#define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB__SHIFT 0x3
+#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY_MASK 0x30
+#define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY__SHIFT 0x4
+#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB_MASK 0x40
+#define MC_IO_RXCNTL_DPHY1_D1__RXPDNB__SHIFT 0x6
+#define MC_IO_RXCNTL_DPHY1_D1__RXLP_MASK 0x80
+#define MC_IO_RXCNTL_DPHY1_D1__RXLP__SHIFT 0x7
+#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_MASK 0xf00
+#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL__SHIFT 0x8
+#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR_MASK 0xf000
+#define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR__SHIFT 0xc
+#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL_MASK 0x10000
+#define MC_IO_RXCNTL_DPHY1_D1__VREFSEL__SHIFT 0x10
+#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL_MASK 0xc0000
+#define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL__SHIFT 0x12
+#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0_MASK 0x700000
+#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0__SHIFT 0x14
+#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1_MASK 0x7000000
+#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1__SHIFT 0x18
+#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M_MASK 0x10000000
+#define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M__SHIFT 0x1c
+#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON_MASK 0x20000000
+#define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON__SHIFT 0x1d
+#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL_MASK 0xc0000000
+#define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL__SHIFT 0x1e
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB_MASK 0xf
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB__SHIFT 0x0
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB_MASK 0xf0
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB__SHIFT 0x4
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3_MASK 0xff00
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3__SHIFT 0x8
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2_MASK 0x10000
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2__SHIFT 0x10
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3_MASK 0x20000
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3__SHIFT 0x11
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1_MASK 0x40000
+#define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1__SHIFT 0x12
+#define MC_IO_RXCNTL1_DPHY1_D1__DLL_PWRGOOD_OVR_MASK 0x80000
+#define MC_IO_RXCNTL1_DPHY1_D1__DLL_PWRGOOD_OVR__SHIFT 0x13
+#define MC_IO_RXCNTL1_DPHY1_D1__DLL_VCTRLADC_EN_MASK 0x100000
+#define MC_IO_RXCNTL1_DPHY1_D1__DLL_VCTRLADC_EN__SHIFT 0x14
+#define MC_IO_RXCNTL1_DPHY1_D1__DLL_MSTR_STBY_MASK 0x200000
+#define MC_IO_RXCNTL1_DPHY1_D1__DLL_MSTR_STBY__SHIFT 0x15
+#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_EN_MASK 0x400000
+#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_EN__SHIFT 0x16
+#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_NXT_MASK 0x800000
+#define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_NXT__SHIFT 0x17
+#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK_MASK 0xe000000
+#define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK__SHIFT 0x19
+#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV_MASK 0xf0000000
+#define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV__SHIFT 0x1c
+#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D_MASK 0x3f
+#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D__SHIFT 0x0
+#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D_MASK 0xfc0
+#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D__SHIFT 0x6
+#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S_MASK 0x3f000
+#define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S__SHIFT 0xc
+#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S_MASK 0xfc0000
+#define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S__SHIFT 0x12
+#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL_MASK 0x1000000
+#define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL__SHIFT 0x18
+#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL_MASK 0x2000000
+#define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL__SHIFT 0x19
+#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL_MASK 0xc000000
+#define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x1a
+#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR_MASK 0x10000000
+#define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR__SHIFT 0x1c
+#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR_MASK 0x20000000
+#define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR__SHIFT 0x1d
+#define MC_IO_DPHY_STR_CNTL_D1__AUTO_LD_STR_MASK 0x40000000
+#define MC_IO_DPHY_STR_CNTL_D1__AUTO_LD_STR__SHIFT 0x1e
+#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A_MASK 0x3f
+#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A__SHIFT 0x0
+#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A_MASK 0xfc0
+#define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A__SHIFT 0x6
+#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD_MASK 0x3f000
+#define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD__SHIFT 0xc
+#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL_MASK 0x1000000
+#define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL__SHIFT 0x18
+#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL_MASK 0x2000000
+#define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL__SHIFT 0x19
+#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL_MASK 0xc000000
+#define MC_IO_APHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x1a
+#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR_MASK 0x10000000
+#define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR__SHIFT 0x1c
+#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR_MASK 0x20000000
+#define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR__SHIFT 0x1d
+#define MC_IO_CDRCNTL_D0__RXPHASE_B01_MASK 0xf
+#define MC_IO_CDRCNTL_D0__RXPHASE_B01__SHIFT 0x0
+#define MC_IO_CDRCNTL_D0__RXPHASE_B23_MASK 0xf0
+#define MC_IO_CDRCNTL_D0__RXPHASE_B23__SHIFT 0x4
+#define MC_IO_CDRCNTL_D0__RXCDREN_B01_MASK 0x100
+#define MC_IO_CDRCNTL_D0__RXCDREN_B01__SHIFT 0x8
+#define MC_IO_CDRCNTL_D0__RXCDREN_B23_MASK 0x200
+#define MC_IO_CDRCNTL_D0__RXCDREN_B23__SHIFT 0x9
+#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01_MASK 0x400
+#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01__SHIFT 0xa
+#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23_MASK 0x800
+#define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23__SHIFT 0xb
+#define MC_IO_CDRCNTL_D0__RXPHASE1_B01_MASK 0xf000
+#define MC_IO_CDRCNTL_D0__RXPHASE1_B01__SHIFT 0xc
+#define MC_IO_CDRCNTL_D0__RXPHASE1_B23_MASK 0xf0000
+#define MC_IO_CDRCNTL_D0__RXPHASE1_B23__SHIFT 0x10
+#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0_MASK 0x100000
+#define MC_IO_CDRCNTL_D0__DQTXCDREN_B0__SHIFT 0x14
+#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1_MASK 0x200000
+#define MC_IO_CDRCNTL_D0__DQTXCDREN_B1__SHIFT 0x15
+#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0_MASK 0x400000
+#define MC_IO_CDRCNTL_D0__DQRXCDREN_B0__SHIFT 0x16
+#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1_MASK 0x800000
+#define MC_IO_CDRCNTL_D0__DQRXCDREN_B1__SHIFT 0x17
+#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0_MASK 0x1000000
+#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0__SHIFT 0x18
+#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1_MASK 0x2000000
+#define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1__SHIFT 0x19
+#define MC_IO_CDRCNTL_D0__WCDREDC_B0_MASK 0x4000000
+#define MC_IO_CDRCNTL_D0__WCDREDC_B0__SHIFT 0x1a
+#define MC_IO_CDRCNTL_D0__WCDREDC_B1_MASK 0x8000000
+#define MC_IO_CDRCNTL_D0__WCDREDC_B1__SHIFT 0x1b
+#define MC_IO_CDRCNTL_D0__DQRXSEL_B0_MASK 0x10000000
+#define MC_IO_CDRCNTL_D0__DQRXSEL_B0__SHIFT 0x1c
+#define MC_IO_CDRCNTL_D0__DQRXSEL_B1_MASK 0x20000000
+#define MC_IO_CDRCNTL_D0__DQRXSEL_B1__SHIFT 0x1d
+#define MC_IO_CDRCNTL_D0__DQTXSEL_B0_MASK 0x40000000
+#define MC_IO_CDRCNTL_D0__DQTXSEL_B0__SHIFT 0x1e
+#define MC_IO_CDRCNTL_D0__DQTXSEL_B1_MASK 0x80000000
+#define MC_IO_CDRCNTL_D0__DQTXSEL_B1__SHIFT 0x1f
+#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0_MASK 0xff
+#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0__SHIFT 0x0
+#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1_MASK 0xff00
+#define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1__SHIFT 0x8
+#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0_MASK 0xff0000
+#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0__SHIFT 0x10
+#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1_MASK 0xff000000
+#define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1__SHIFT 0x18
+#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0_MASK 0x1
+#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0__SHIFT 0x0
+#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1_MASK 0x2
+#define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1__SHIFT 0x1
+#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0_MASK 0x4
+#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0__SHIFT 0x2
+#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1_MASK 0x8
+#define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1__SHIFT 0x3
+#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0_MASK 0x10
+#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0__SHIFT 0x4
+#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1_MASK 0x20
+#define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1__SHIFT 0x5
+#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0_MASK 0x40
+#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0__SHIFT 0x6
+#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1_MASK 0x80
+#define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1__SHIFT 0x7
+#define MC_IO_CDRCNTL2_D0__WCDRTXPWRON_MASK 0xf00
+#define MC_IO_CDRCNTL2_D0__WCDRTXPWRON__SHIFT 0x8
+#define MC_IO_CDRCNTL2_D0__WCDRTXSEL_MASK 0xf000
+#define MC_IO_CDRCNTL2_D0__WCDRTXSEL__SHIFT 0xc
+#define MC_IO_CDRCNTL2_D0__WCDRTRACK01_MASK 0xf0000
+#define MC_IO_CDRCNTL2_D0__WCDRTRACK01__SHIFT 0x10
+#define MC_IO_CDRCNTL_D1__RXPHASE_B01_MASK 0xf
+#define MC_IO_CDRCNTL_D1__RXPHASE_B01__SHIFT 0x0
+#define MC_IO_CDRCNTL_D1__RXPHASE_B23_MASK 0xf0
+#define MC_IO_CDRCNTL_D1__RXPHASE_B23__SHIFT 0x4
+#define MC_IO_CDRCNTL_D1__RXCDREN_B01_MASK 0x100
+#define MC_IO_CDRCNTL_D1__RXCDREN_B01__SHIFT 0x8
+#define MC_IO_CDRCNTL_D1__RXCDREN_B23_MASK 0x200
+#define MC_IO_CDRCNTL_D1__RXCDREN_B23__SHIFT 0x9
+#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01_MASK 0x400
+#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01__SHIFT 0xa
+#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23_MASK 0x800
+#define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23__SHIFT 0xb
+#define MC_IO_CDRCNTL_D1__RXPHASE1_B01_MASK 0xf000
+#define MC_IO_CDRCNTL_D1__RXPHASE1_B01__SHIFT 0xc
+#define MC_IO_CDRCNTL_D1__RXPHASE1_B23_MASK 0xf0000
+#define MC_IO_CDRCNTL_D1__RXPHASE1_B23__SHIFT 0x10
+#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0_MASK 0x100000
+#define MC_IO_CDRCNTL_D1__DQTXCDREN_B0__SHIFT 0x14
+#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1_MASK 0x200000
+#define MC_IO_CDRCNTL_D1__DQTXCDREN_B1__SHIFT 0x15
+#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0_MASK 0x400000
+#define MC_IO_CDRCNTL_D1__DQRXCDREN_B0__SHIFT 0x16
+#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1_MASK 0x800000
+#define MC_IO_CDRCNTL_D1__DQRXCDREN_B1__SHIFT 0x17
+#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0_MASK 0x1000000
+#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0__SHIFT 0x18
+#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1_MASK 0x2000000
+#define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1__SHIFT 0x19
+#define MC_IO_CDRCNTL_D1__WCDREDC_B0_MASK 0x4000000
+#define MC_IO_CDRCNTL_D1__WCDREDC_B0__SHIFT 0x1a
+#define MC_IO_CDRCNTL_D1__WCDREDC_B1_MASK 0x8000000
+#define MC_IO_CDRCNTL_D1__WCDREDC_B1__SHIFT 0x1b
+#define MC_IO_CDRCNTL_D1__DQRXSEL_B0_MASK 0x10000000
+#define MC_IO_CDRCNTL_D1__DQRXSEL_B0__SHIFT 0x1c
+#define MC_IO_CDRCNTL_D1__DQRXSEL_B1_MASK 0x20000000
+#define MC_IO_CDRCNTL_D1__DQRXSEL_B1__SHIFT 0x1d
+#define MC_IO_CDRCNTL_D1__DQTXSEL_B0_MASK 0x40000000
+#define MC_IO_CDRCNTL_D1__DQTXSEL_B0__SHIFT 0x1e
+#define MC_IO_CDRCNTL_D1__DQTXSEL_B1_MASK 0x80000000
+#define MC_IO_CDRCNTL_D1__DQTXSEL_B1__SHIFT 0x1f
+#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0_MASK 0xff
+#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0__SHIFT 0x0
+#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1_MASK 0xff00
+#define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1__SHIFT 0x8
+#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0_MASK 0xff0000
+#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0__SHIFT 0x10
+#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1_MASK 0xff000000
+#define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1__SHIFT 0x18
+#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0_MASK 0x1
+#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0__SHIFT 0x0
+#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1_MASK 0x2
+#define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1__SHIFT 0x1
+#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0_MASK 0x4
+#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0__SHIFT 0x2
+#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1_MASK 0x8
+#define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1__SHIFT 0x3
+#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0_MASK 0x10
+#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0__SHIFT 0x4
+#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1_MASK 0x20
+#define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1__SHIFT 0x5
+#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0_MASK 0x40
+#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0__SHIFT 0x6
+#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1_MASK 0x80
+#define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1__SHIFT 0x7
+#define MC_IO_CDRCNTL2_D1__WCDRTXPWRON_MASK 0xf00
+#define MC_IO_CDRCNTL2_D1__WCDRTXPWRON__SHIFT 0x8
+#define MC_IO_CDRCNTL2_D1__WCDRTXSEL_MASK 0xf000
+#define MC_IO_CDRCNTL2_D1__WCDRTXSEL__SHIFT 0xc
+#define MC_IO_CDRCNTL2_D1__WCDRTRACK01_MASK 0xf0000
+#define MC_IO_CDRCNTL2_D1__WCDRTRACK01__SHIFT 0x10
+#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0_MASK 0x3
+#define MC_SEQ_FIFO_CTL__W_LD_INIT_D0__SHIFT 0x0
+#define MC_SEQ_FIFO_CTL__W_SYC_SEL_MASK 0xc
+#define MC_SEQ_FIFO_CTL__W_SYC_SEL__SHIFT 0x2
+#define MC_SEQ_FIFO_CTL__R_LD_INIT_MASK 0x30
+#define MC_SEQ_FIFO_CTL__R_LD_INIT__SHIFT 0x4
+#define MC_SEQ_FIFO_CTL__R_SYC_SEL_MASK 0xc0
+#define MC_SEQ_FIFO_CTL__R_SYC_SEL__SHIFT 0x6
+#define MC_SEQ_FIFO_CTL__CG_DIS_D0_MASK 0x100
+#define MC_SEQ_FIFO_CTL__CG_DIS_D0__SHIFT 0x8
+#define MC_SEQ_FIFO_CTL__CG_DIS_D1_MASK 0x200
+#define MC_SEQ_FIFO_CTL__CG_DIS_D1__SHIFT 0x9
+#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1_MASK 0xc00
+#define MC_SEQ_FIFO_CTL__W_LD_INIT_D1__SHIFT 0xa
+#define MC_SEQ_FIFO_CTL__SYC_DLY_MASK 0x7000
+#define MC_SEQ_FIFO_CTL__SYC_DLY__SHIFT 0xc
+#define MC_SEQ_FIFO_CTL__W_ASYC_EXT_MASK 0x30000
+#define MC_SEQ_FIFO_CTL__W_ASYC_EXT__SHIFT 0x10
+#define MC_SEQ_FIFO_CTL__W_DSYC_EXT_MASK 0xc0000
+#define MC_SEQ_FIFO_CTL__W_DSYC_EXT__SHIFT 0x12
+#define MC_SEQ_FIFO_CTL__R_DQS_LD_INIT_MASK 0xf00000
+#define MC_SEQ_FIFO_CTL__R_DQS_LD_INIT__SHIFT 0x14
+#define MC_SEQ_FIFO_CTL__R_DQS_STEP_MASK 0xf000000
+#define MC_SEQ_FIFO_CTL__R_DQS_STEP__SHIFT 0x18
+#define MC_SEQ_FIFO_CTL__R_DQS_FRC_MASK 0x10000000
+#define MC_SEQ_FIFO_CTL__R_DQS_FRC__SHIFT 0x1c
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0_MASK 0xf
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4_MASK 0xf0000
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4__SHIFT 0x10
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5_MASK 0xf00000
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5__SHIFT 0x14
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6_MASK 0xf000000
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6__SHIFT 0x18
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000
+#define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7__SHIFT 0x1c
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0_MASK 0xf
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4_MASK 0xf0000
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4__SHIFT 0x10
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5_MASK 0xf00000
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5__SHIFT 0x14
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6_MASK 0xf000000
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6__SHIFT 0x18
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000
+#define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7__SHIFT 0x1c
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0_MASK 0xf
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4_MASK 0xf0000
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4__SHIFT 0x10
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5_MASK 0xf00000
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5__SHIFT 0x14
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6_MASK 0xf000000
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6__SHIFT 0x18
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000
+#define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7__SHIFT 0x1c
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0_MASK 0xf
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4_MASK 0xf0000
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4__SHIFT 0x10
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5_MASK 0xf00000
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5__SHIFT 0x14
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6_MASK 0xf000000
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6__SHIFT 0x18
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000
+#define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7__SHIFT 0x1c
+#define MC_SEQ_TXFRAMING_DBI_D0__DBI0_MASK 0xf
+#define MC_SEQ_TXFRAMING_DBI_D0__DBI0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_DBI_D0__DBI1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_DBI_D0__DBI1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_DBI_D0__DBI2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_DBI_D0__DBI2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_DBI_D0__DBI3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_DBI_D0__DBI3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_EDC_D0__EDC0_MASK 0xf
+#define MC_SEQ_TXFRAMING_EDC_D0__EDC0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_EDC_D0__EDC1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_EDC_D0__EDC1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_EDC_D0__EDC2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_EDC_D0__EDC2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_EDC_D0__EDC3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_EDC_D0__EDC3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0_MASK 0xf0000
+#define MC_SEQ_TXFRAMING_EDC_D0__WCDR0__SHIFT 0x10
+#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1_MASK 0xf00000
+#define MC_SEQ_TXFRAMING_EDC_D0__WCDR1__SHIFT 0x14
+#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2_MASK 0xf000000
+#define MC_SEQ_TXFRAMING_EDC_D0__WCDR2__SHIFT 0x18
+#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000
+#define MC_SEQ_TXFRAMING_EDC_D0__WCDR3__SHIFT 0x1c
+#define MC_SEQ_TXFRAMING_FCK_D0__FCK0_MASK 0xf
+#define MC_SEQ_TXFRAMING_FCK_D0__FCK0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_FCK_D0__FCK1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_FCK_D0__FCK1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_FCK_D0__FCK2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_FCK_D0__FCK2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_FCK_D0__FCK3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_FCK_D0__FCK3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0_MASK 0xf
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4_MASK 0xf0000
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4__SHIFT 0x10
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5_MASK 0xf00000
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5__SHIFT 0x14
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6_MASK 0xf000000
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6__SHIFT 0x18
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000
+#define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7__SHIFT 0x1c
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0_MASK 0xf
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4_MASK 0xf0000
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4__SHIFT 0x10
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5_MASK 0xf00000
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5__SHIFT 0x14
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6_MASK 0xf000000
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6__SHIFT 0x18
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000
+#define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7__SHIFT 0x1c
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0_MASK 0xf
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4_MASK 0xf0000
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4__SHIFT 0x10
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5_MASK 0xf00000
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5__SHIFT 0x14
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6_MASK 0xf000000
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6__SHIFT 0x18
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000
+#define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7__SHIFT 0x1c
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0_MASK 0xf
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4_MASK 0xf0000
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4__SHIFT 0x10
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5_MASK 0xf00000
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5__SHIFT 0x14
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6_MASK 0xf000000
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6__SHIFT 0x18
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000
+#define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7__SHIFT 0x1c
+#define MC_SEQ_TXFRAMING_DBI_D1__DBI0_MASK 0xf
+#define MC_SEQ_TXFRAMING_DBI_D1__DBI0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_DBI_D1__DBI1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_DBI_D1__DBI1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_DBI_D1__DBI2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_DBI_D1__DBI2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_DBI_D1__DBI3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_DBI_D1__DBI3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_EDC_D1__EDC0_MASK 0xf
+#define MC_SEQ_TXFRAMING_EDC_D1__EDC0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_EDC_D1__EDC1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_EDC_D1__EDC1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_EDC_D1__EDC2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_EDC_D1__EDC2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_EDC_D1__EDC3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_EDC_D1__EDC3__SHIFT 0xc
+#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0_MASK 0xf0000
+#define MC_SEQ_TXFRAMING_EDC_D1__WCDR0__SHIFT 0x10
+#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1_MASK 0xf00000
+#define MC_SEQ_TXFRAMING_EDC_D1__WCDR1__SHIFT 0x14
+#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2_MASK 0xf000000
+#define MC_SEQ_TXFRAMING_EDC_D1__WCDR2__SHIFT 0x18
+#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000
+#define MC_SEQ_TXFRAMING_EDC_D1__WCDR3__SHIFT 0x1c
+#define MC_SEQ_TXFRAMING_FCK_D1__FCK0_MASK 0xf
+#define MC_SEQ_TXFRAMING_FCK_D1__FCK0__SHIFT 0x0
+#define MC_SEQ_TXFRAMING_FCK_D1__FCK1_MASK 0xf0
+#define MC_SEQ_TXFRAMING_FCK_D1__FCK1__SHIFT 0x4
+#define MC_SEQ_TXFRAMING_FCK_D1__FCK2_MASK 0xf00
+#define MC_SEQ_TXFRAMING_FCK_D1__FCK2__SHIFT 0x8
+#define MC_SEQ_TXFRAMING_FCK_D1__FCK3_MASK 0xf000
+#define MC_SEQ_TXFRAMING_FCK_D1__FCK3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0_MASK 0xf
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4_MASK 0xf0000
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4__SHIFT 0x10
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5_MASK 0xf00000
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5__SHIFT 0x14
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6_MASK 0xf000000
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6__SHIFT 0x18
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000
+#define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7__SHIFT 0x1c
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0_MASK 0xf
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4_MASK 0xf0000
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4__SHIFT 0x10
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5_MASK 0xf00000
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5__SHIFT 0x14
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6_MASK 0xf000000
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6__SHIFT 0x18
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000
+#define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7__SHIFT 0x1c
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0_MASK 0xf
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4_MASK 0xf0000
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4__SHIFT 0x10
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5_MASK 0xf00000
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5__SHIFT 0x14
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6_MASK 0xf000000
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6__SHIFT 0x18
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000
+#define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7__SHIFT 0x1c
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0_MASK 0xf
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4_MASK 0xf0000
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4__SHIFT 0x10
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5_MASK 0xf00000
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5__SHIFT 0x14
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6_MASK 0xf000000
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6__SHIFT 0x18
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000
+#define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7__SHIFT 0x1c
+#define MC_SEQ_RXFRAMING_DBI_D0__DBI0_MASK 0xf
+#define MC_SEQ_RXFRAMING_DBI_D0__DBI0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_DBI_D0__DBI1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_DBI_D0__DBI1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_DBI_D0__DBI2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_DBI_D0__DBI2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_DBI_D0__DBI3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_DBI_D0__DBI3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_EDC_D0__EDC0_MASK 0xf
+#define MC_SEQ_RXFRAMING_EDC_D0__EDC0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_EDC_D0__EDC1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_EDC_D0__EDC1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_EDC_D0__EDC2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_EDC_D0__EDC2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_EDC_D0__EDC3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_EDC_D0__EDC3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0_MASK 0xf0000
+#define MC_SEQ_RXFRAMING_EDC_D0__WCDR0__SHIFT 0x10
+#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1_MASK 0xf00000
+#define MC_SEQ_RXFRAMING_EDC_D0__WCDR1__SHIFT 0x14
+#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2_MASK 0xf000000
+#define MC_SEQ_RXFRAMING_EDC_D0__WCDR2__SHIFT 0x18
+#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000
+#define MC_SEQ_RXFRAMING_EDC_D0__WCDR3__SHIFT 0x1c
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0_MASK 0xf
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4_MASK 0xf0000
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4__SHIFT 0x10
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5_MASK 0xf00000
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5__SHIFT 0x14
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6_MASK 0xf000000
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6__SHIFT 0x18
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000
+#define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7__SHIFT 0x1c
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0_MASK 0xf
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4_MASK 0xf0000
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4__SHIFT 0x10
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5_MASK 0xf00000
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5__SHIFT 0x14
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6_MASK 0xf000000
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6__SHIFT 0x18
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000
+#define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7__SHIFT 0x1c
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0_MASK 0xf
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4_MASK 0xf0000
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4__SHIFT 0x10
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5_MASK 0xf00000
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5__SHIFT 0x14
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6_MASK 0xf000000
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6__SHIFT 0x18
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000
+#define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7__SHIFT 0x1c
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0_MASK 0xf
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4_MASK 0xf0000
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4__SHIFT 0x10
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5_MASK 0xf00000
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5__SHIFT 0x14
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6_MASK 0xf000000
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6__SHIFT 0x18
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000
+#define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7__SHIFT 0x1c
+#define MC_SEQ_RXFRAMING_DBI_D1__DBI0_MASK 0xf
+#define MC_SEQ_RXFRAMING_DBI_D1__DBI0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_DBI_D1__DBI1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_DBI_D1__DBI1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_DBI_D1__DBI2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_DBI_D1__DBI2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_DBI_D1__DBI3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_DBI_D1__DBI3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_EDC_D1__EDC0_MASK 0xf
+#define MC_SEQ_RXFRAMING_EDC_D1__EDC0__SHIFT 0x0
+#define MC_SEQ_RXFRAMING_EDC_D1__EDC1_MASK 0xf0
+#define MC_SEQ_RXFRAMING_EDC_D1__EDC1__SHIFT 0x4
+#define MC_SEQ_RXFRAMING_EDC_D1__EDC2_MASK 0xf00
+#define MC_SEQ_RXFRAMING_EDC_D1__EDC2__SHIFT 0x8
+#define MC_SEQ_RXFRAMING_EDC_D1__EDC3_MASK 0xf000
+#define MC_SEQ_RXFRAMING_EDC_D1__EDC3__SHIFT 0xc
+#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0_MASK 0xf0000
+#define MC_SEQ_RXFRAMING_EDC_D1__WCDR0__SHIFT 0x10
+#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1_MASK 0xf00000
+#define MC_SEQ_RXFRAMING_EDC_D1__WCDR1__SHIFT 0x14
+#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2_MASK 0xf000000
+#define MC_SEQ_RXFRAMING_EDC_D1__WCDR2__SHIFT 0x18
+#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000
+#define MC_SEQ_RXFRAMING_EDC_D1__WCDR3__SHIFT 0x1c
+#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN_MASK 0xff
+#define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN__SHIFT 0x0
+#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX_MASK 0xff00
+#define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX__SHIFT 0x8
+#define MC_IO_PAD_CNTL__TXPHASE_GRAY_MASK 0x10000
+#define MC_IO_PAD_CNTL__TXPHASE_GRAY__SHIFT 0x10
+#define MC_IO_PAD_CNTL__RXPHASE_GRAY_MASK 0x20000
+#define MC_IO_PAD_CNTL__RXPHASE_GRAY__SHIFT 0x11
+#define MC_IO_PAD_CNTL__OVL_YCLKON_D0_MASK 0x40000
+#define MC_IO_PAD_CNTL__OVL_YCLKON_D0__SHIFT 0x12
+#define MC_IO_PAD_CNTL__OVL_YCLKON_D1_MASK 0x80000
+#define MC_IO_PAD_CNTL__OVL_YCLKON_D1__SHIFT 0x13
+#define MC_IO_PAD_CNTL__ATBSEL_MASK 0xf00000
+#define MC_IO_PAD_CNTL__ATBSEL__SHIFT 0x14
+#define MC_IO_PAD_CNTL__ATBEN_MASK 0x3f000000
+#define MC_IO_PAD_CNTL__ATBEN__SHIFT 0x18
+#define MC_IO_PAD_CNTL__ATBSEL_D1_MASK 0x40000000
+#define MC_IO_PAD_CNTL__ATBSEL_D1__SHIFT 0x1e
+#define MC_IO_PAD_CNTL__ATBSEL_D0_MASK 0x80000000
+#define MC_IO_PAD_CNTL__ATBSEL_D0__SHIFT 0x1f
+#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC_MASK 0x4
+#define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC__SHIFT 0x2
+#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC_MASK 0x8
+#define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC__SHIFT 0x3
+#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC_MASK 0x10
+#define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC__SHIFT 0x4
+#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK_MASK 0x80
+#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK__SHIFT 0x7
+#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD_MASK 0x100
+#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD__SHIFT 0x8
+#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR_MASK 0x200
+#define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR__SHIFT 0x9
+#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR_MASK 0x400
+#define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR__SHIFT 0xa
+#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY_MASK 0x800
+#define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY__SHIFT 0xb
+#define MC_IO_PAD_CNTL_D0__DISABLE_CMD_MASK 0x1000
+#define MC_IO_PAD_CNTL_D0__DISABLE_CMD__SHIFT 0xc
+#define MC_IO_PAD_CNTL_D0__DISABLE_ADR_MASK 0x2000
+#define MC_IO_PAD_CNTL_D0__DISABLE_ADR__SHIFT 0xd
+#define MC_IO_PAD_CNTL_D0__VREFI_EN_MASK 0x4000
+#define MC_IO_PAD_CNTL_D0__VREFI_EN__SHIFT 0xe
+#define MC_IO_PAD_CNTL_D0__VREFI_SEL_MASK 0xf8000
+#define MC_IO_PAD_CNTL_D0__VREFI_SEL__SHIFT 0xf
+#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN_MASK 0x100000
+#define MC_IO_PAD_CNTL_D0__CK_AUTO_EN__SHIFT 0x14
+#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL_MASK 0x200000
+#define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL__SHIFT 0x15
+#define MC_IO_PAD_CNTL_D0__CK_DELAY_N_MASK 0xc00000
+#define MC_IO_PAD_CNTL_D0__CK_DELAY_N__SHIFT 0x16
+#define MC_IO_PAD_CNTL_D0__CK_DELAY_P_MASK 0x3000000
+#define MC_IO_PAD_CNTL_D0__CK_DELAY_P__SHIFT 0x18
+#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE_MASK 0x8000000
+#define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE__SHIFT 0x1b
+#define MC_IO_PAD_CNTL_D0__UNI_STR_MASK 0x10000000
+#define MC_IO_PAD_CNTL_D0__UNI_STR__SHIFT 0x1c
+#define MC_IO_PAD_CNTL_D0__DIFF_STR_MASK 0x20000000
+#define MC_IO_PAD_CNTL_D0__DIFF_STR__SHIFT 0x1d
+#define MC_IO_PAD_CNTL_D0__GDDR_PWRON_MASK 0x40000000
+#define MC_IO_PAD_CNTL_D0__GDDR_PWRON__SHIFT 0x1e
+#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK_MASK 0x80000000
+#define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK__SHIFT 0x1f
+#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC_MASK 0x1
+#define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC__SHIFT 0x0
+#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC_MASK 0x2
+#define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC__SHIFT 0x1
+#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC_MASK 0x4
+#define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC__SHIFT 0x2
+#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC_MASK 0x8
+#define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC__SHIFT 0x3
+#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC_MASK 0x10
+#define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC__SHIFT 0x4
+#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA_MASK 0x20
+#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA__SHIFT 0x5
+#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR_MASK 0x40
+#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR__SHIFT 0x6
+#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK_MASK 0x80
+#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK__SHIFT 0x7
+#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD_MASK 0x100
+#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD__SHIFT 0x8
+#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR_MASK 0x200
+#define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR__SHIFT 0x9
+#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR_MASK 0x400
+#define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR__SHIFT 0xa
+#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY_MASK 0x800
+#define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY__SHIFT 0xb
+#define MC_IO_PAD_CNTL_D1__DISABLE_CMD_MASK 0x1000
+#define MC_IO_PAD_CNTL_D1__DISABLE_CMD__SHIFT 0xc
+#define MC_IO_PAD_CNTL_D1__DISABLE_ADR_MASK 0x2000
+#define MC_IO_PAD_CNTL_D1__DISABLE_ADR__SHIFT 0xd
+#define MC_IO_PAD_CNTL_D1__VREFI_EN_MASK 0x4000
+#define MC_IO_PAD_CNTL_D1__VREFI_EN__SHIFT 0xe
+#define MC_IO_PAD_CNTL_D1__VREFI_SEL_MASK 0xf8000
+#define MC_IO_PAD_CNTL_D1__VREFI_SEL__SHIFT 0xf
+#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN_MASK 0x100000
+#define MC_IO_PAD_CNTL_D1__CK_AUTO_EN__SHIFT 0x14
+#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL_MASK 0x200000
+#define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL__SHIFT 0x15
+#define MC_IO_PAD_CNTL_D1__CK_DELAY_N_MASK 0xc00000
+#define MC_IO_PAD_CNTL_D1__CK_DELAY_N__SHIFT 0x16
+#define MC_IO_PAD_CNTL_D1__CK_DELAY_P_MASK 0x3000000
+#define MC_IO_PAD_CNTL_D1__CK_DELAY_P__SHIFT 0x18
+#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE_MASK 0x8000000
+#define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE__SHIFT 0x1b
+#define MC_IO_PAD_CNTL_D1__UNI_STR_MASK 0x10000000
+#define MC_IO_PAD_CNTL_D1__UNI_STR__SHIFT 0x1c
+#define MC_IO_PAD_CNTL_D1__DIFF_STR_MASK 0x20000000
+#define MC_IO_PAD_CNTL_D1__DIFF_STR__SHIFT 0x1d
+#define MC_IO_PAD_CNTL_D1__GDDR_PWRON_MASK 0x40000000
+#define MC_IO_PAD_CNTL_D1__GDDR_PWRON__SHIFT 0x1e
+#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK_MASK 0x80000000
+#define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK__SHIFT 0x1f
+#define MC_NPL_STATUS__D0_PDELAY_MASK 0x3
+#define MC_NPL_STATUS__D0_PDELAY__SHIFT 0x0
+#define MC_NPL_STATUS__D0_NDELAY_MASK 0xc
+#define MC_NPL_STATUS__D0_NDELAY__SHIFT 0x2
+#define MC_NPL_STATUS__D0_PEARLY_MASK 0x10
+#define MC_NPL_STATUS__D0_PEARLY__SHIFT 0x4
+#define MC_NPL_STATUS__D0_NEARLY_MASK 0x20
+#define MC_NPL_STATUS__D0_NEARLY__SHIFT 0x5
+#define MC_NPL_STATUS__D1_PDELAY_MASK 0xc0
+#define MC_NPL_STATUS__D1_PDELAY__SHIFT 0x6
+#define MC_NPL_STATUS__D1_NDELAY_MASK 0x300
+#define MC_NPL_STATUS__D1_NDELAY__SHIFT 0x8
+#define MC_NPL_STATUS__D1_PEARLY_MASK 0x400
+#define MC_NPL_STATUS__D1_PEARLY__SHIFT 0xa
+#define MC_NPL_STATUS__D1_NEARLY_MASK 0x800
+#define MC_NPL_STATUS__D1_NEARLY__SHIFT 0xb
+#define MC_BIST_CMD_CNTL__RESET_MASK 0x1
+#define MC_BIST_CMD_CNTL__RESET__SHIFT 0x0
+#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_MASK 0x2
+#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE__SHIFT 0x1
+#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP_MASK 0x4
+#define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP__SHIFT 0x2
+#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION_MASK 0x8
+#define MC_BIST_CMD_CNTL__LOOP_END_CONDITION__SHIFT 0x3
+#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX_MASK 0xfff0
+#define MC_BIST_CMD_CNTL__LOOP_CNT_MAX__SHIFT 0x4
+#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U_MASK 0x10000
+#define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U__SHIFT 0x10
+#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN_MASK 0x20000
+#define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN__SHIFT 0x11
+#define MC_BIST_CMD_CNTL__LOOP_CNT_RD_MASK 0xffc0000
+#define MC_BIST_CMD_CNTL__LOOP_CNT_RD__SHIFT 0x12
+#define MC_BIST_CMD_CNTL__ENABLE_D0_MASK 0x10000000
+#define MC_BIST_CMD_CNTL__ENABLE_D0__SHIFT 0x1c
+#define MC_BIST_CMD_CNTL__ENABLE_D1_MASK 0x20000000
+#define MC_BIST_CMD_CNTL__ENABLE_D1__SHIFT 0x1d
+#define MC_BIST_CMD_CNTL__STATUS_CH_MASK 0x40000000
+#define MC_BIST_CMD_CNTL__STATUS_CH__SHIFT 0x1e
+#define MC_BIST_CMD_CNTL__DONE_MASK 0x80000000
+#define MC_BIST_CMD_CNTL__DONE__SHIFT 0x1f
+#define MC_BIST_CNTL__RESET_MASK 0x1
+#define MC_BIST_CNTL__RESET__SHIFT 0x0
+#define MC_BIST_CNTL__RUN_MASK 0x2
+#define MC_BIST_CNTL__RUN__SHIFT 0x1
+#define MC_BIST_CNTL__PTR_RST_D0_MASK 0x4
+#define MC_BIST_CNTL__PTR_RST_D0__SHIFT 0x2
+#define MC_BIST_CNTL__PTR_RST_D1_MASK 0x8
+#define MC_BIST_CNTL__PTR_RST_D1__SHIFT 0x3
+#define MC_BIST_CNTL__MOP_MODE_MASK 0x10
+#define MC_BIST_CNTL__MOP_MODE__SHIFT 0x4
+#define MC_BIST_CNTL__ADR_MODE_MASK 0x20
+#define MC_BIST_CNTL__ADR_MODE__SHIFT 0x5
+#define MC_BIST_CNTL__DAT_MODE_MASK 0x40
+#define MC_BIST_CNTL__DAT_MODE__SHIFT 0x6
+#define MC_BIST_CNTL__LOOP_MASK 0xc00
+#define MC_BIST_CNTL__LOOP__SHIFT 0xa
+#define MC_BIST_CNTL__ENABLE_D0_MASK 0x1000
+#define MC_BIST_CNTL__ENABLE_D0__SHIFT 0xc
+#define MC_BIST_CNTL__ENABLE_D1_MASK 0x2000
+#define MC_BIST_CNTL__ENABLE_D1__SHIFT 0xd
+#define MC_BIST_CNTL__LOAD_RTDATA_CH_MASK 0x4000
+#define MC_BIST_CNTL__LOAD_RTDATA_CH__SHIFT 0xe
+#define MC_BIST_CNTL__LOOP_CNT_MASK 0xfff0000
+#define MC_BIST_CNTL__LOOP_CNT__SHIFT 0x10
+#define MC_BIST_CNTL__DONE_MASK 0x40000000
+#define MC_BIST_CNTL__DONE__SHIFT 0x1e
+#define MC_BIST_CNTL__LOAD_RTDATA_MASK 0x80000000
+#define MC_BIST_CNTL__LOAD_RTDATA__SHIFT 0x1f
+#define MC_BIST_AUTO_CNTL__MOP_MASK 0x3
+#define MC_BIST_AUTO_CNTL__MOP__SHIFT 0x0
+#define MC_BIST_AUTO_CNTL__ADR_GEN_MASK 0xf0
+#define MC_BIST_AUTO_CNTL__ADR_GEN__SHIFT 0x4
+#define MC_BIST_AUTO_CNTL__LFSR_KEY_MASK 0xffff00
+#define MC_BIST_AUTO_CNTL__LFSR_KEY__SHIFT 0x8
+#define MC_BIST_AUTO_CNTL__LFSR_RESET_MASK 0x1000000
+#define MC_BIST_AUTO_CNTL__LFSR_RESET__SHIFT 0x18
+#define MC_BIST_AUTO_CNTL__ADR_RESET_MASK 0x2000000
+#define MC_BIST_AUTO_CNTL__ADR_RESET__SHIFT 0x19
+#define MC_BIST_DIR_CNTL__MOP_MASK 0x7
+#define MC_BIST_DIR_CNTL__MOP__SHIFT 0x0
+#define MC_BIST_DIR_CNTL__EOB_MASK 0x8
+#define MC_BIST_DIR_CNTL__EOB__SHIFT 0x3
+#define MC_BIST_DIR_CNTL__MOP_LOAD_MASK 0x10
+#define MC_BIST_DIR_CNTL__MOP_LOAD__SHIFT 0x4
+#define MC_BIST_DIR_CNTL__DATA_LOAD_MASK 0x20
+#define MC_BIST_DIR_CNTL__DATA_LOAD__SHIFT 0x5
+#define MC_BIST_DIR_CNTL__CMD_RTR_D0_MASK 0x40
+#define MC_BIST_DIR_CNTL__CMD_RTR_D0__SHIFT 0x6
+#define MC_BIST_DIR_CNTL__DAT_RTR_D0_MASK 0x80
+#define MC_BIST_DIR_CNTL__DAT_RTR_D0__SHIFT 0x7
+#define MC_BIST_DIR_CNTL__CMD_RTR_D1_MASK 0x100
+#define MC_BIST_DIR_CNTL__CMD_RTR_D1__SHIFT 0x8
+#define MC_BIST_DIR_CNTL__DAT_RTR_D1_MASK 0x200
+#define MC_BIST_DIR_CNTL__DAT_RTR_D1__SHIFT 0x9
+#define MC_BIST_DIR_CNTL__MOP3_MASK 0x400
+#define MC_BIST_DIR_CNTL__MOP3__SHIFT 0xa
+#define MC_BIST_SADDR__COL_MASK 0x3ff
+#define MC_BIST_SADDR__COL__SHIFT 0x0
+#define MC_BIST_SADDR__ROW_MASK 0xfffc00
+#define MC_BIST_SADDR__ROW__SHIFT 0xa
+#define MC_BIST_SADDR__BANK_MASK 0xf000000
+#define MC_BIST_SADDR__BANK__SHIFT 0x18
+#define MC_BIST_SADDR__RANK_MASK 0x10000000
+#define MC_BIST_SADDR__RANK__SHIFT 0x1c
+#define MC_BIST_SADDR__COLH_MASK 0x20000000
+#define MC_BIST_SADDR__COLH__SHIFT 0x1d
+#define MC_BIST_SADDR__ROWH_MASK 0xc0000000
+#define MC_BIST_SADDR__ROWH__SHIFT 0x1e
+#define MC_BIST_EADDR__COL_MASK 0x3ff
+#define MC_BIST_EADDR__COL__SHIFT 0x0
+#define MC_BIST_EADDR__ROW_MASK 0xfffc00
+#define MC_BIST_EADDR__ROW__SHIFT 0xa
+#define MC_BIST_EADDR__BANK_MASK 0xf000000
+#define MC_BIST_EADDR__BANK__SHIFT 0x18
+#define MC_BIST_EADDR__RANK_MASK 0x10000000
+#define MC_BIST_EADDR__RANK__SHIFT 0x1c
+#define MC_BIST_EADDR__COLH_MASK 0x20000000
+#define MC_BIST_EADDR__COLH__SHIFT 0x1d
+#define MC_BIST_EADDR__ROWH_MASK 0xc0000000
+#define MC_BIST_EADDR__ROWH__SHIFT 0x1e
+#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE_MASK 0xf
+#define MC_BIST_CMP_CNTL__CMP_MASK_BYTE__SHIFT 0x0
+#define MC_BIST_CMP_CNTL__CMP_MASK_BIT_MASK 0xff0
+#define MC_BIST_CMP_CNTL__CMP_MASK_BIT__SHIFT 0x4
+#define MC_BIST_CMP_CNTL__LOAD_RTEDC_MASK 0x1000
+#define MC_BIST_CMP_CNTL__LOAD_RTEDC__SHIFT 0xc
+#define MC_BIST_CMP_CNTL__DATA_STORE_SEL_MASK 0x2000
+#define MC_BIST_CMP_CNTL__DATA_STORE_SEL__SHIFT 0xd
+#define MC_BIST_CMP_CNTL__EDC_STORE_SEL_MASK 0x4000
+#define MC_BIST_CMP_CNTL__EDC_STORE_SEL__SHIFT 0xe
+#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO_MASK 0x8000
+#define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO__SHIFT 0xf
+#define MC_BIST_CMP_CNTL__CMP_MASK 0x30000
+#define MC_BIST_CMP_CNTL__CMP__SHIFT 0x10
+#define MC_BIST_CMP_CNTL__DAT_MODE_MASK 0x40000
+#define MC_BIST_CMP_CNTL__DAT_MODE__SHIFT 0x12
+#define MC_BIST_CMP_CNTL__EDC_STORE_MODE_MASK 0x80000
+#define MC_BIST_CMP_CNTL__EDC_STORE_MODE__SHIFT 0x13
+#define MC_BIST_CMP_CNTL__DATA_STORE_MODE_MASK 0x300000
+#define MC_BIST_CMP_CNTL__DATA_STORE_MODE__SHIFT 0x14
+#define MC_BIST_CMP_CNTL__MISMATCH_CNT_MASK 0xffc00000
+#define MC_BIST_CMP_CNTL__MISMATCH_CNT__SHIFT 0x16
+#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_MASK 0x1f
+#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT__SHIFT 0x0
+#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST_MASK 0x100
+#define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST__SHIFT 0x8
+#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_MASK 0x1f000
+#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT__SHIFT 0xc
+#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST_MASK 0x100000
+#define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST__SHIFT 0x14
+#define MC_BIST_DATA_WORD0__DATA_MASK 0xffffffff
+#define MC_BIST_DATA_WORD0__DATA__SHIFT 0x0
+#define MC_BIST_DATA_WORD1__DATA_MASK 0xffffffff
+#define MC_BIST_DATA_WORD1__DATA__SHIFT 0x0
+#define MC_BIST_DATA_WORD2__DATA_MASK 0xffffffff
+#define MC_BIST_DATA_WORD2__DATA__SHIFT 0x0
+#define MC_BIST_DATA_WORD3__DATA_MASK 0xffffffff
+#define MC_BIST_DATA_WORD3__DATA__SHIFT 0x0
+#define MC_BIST_DATA_WORD4__DATA_MASK 0xffffffff
+#define MC_BIST_DATA_WORD4__DATA__SHIFT 0x0
+#define MC_BIST_DATA_WORD5__DATA_MASK 0xffffffff
+#define MC_BIST_DATA_WORD5__DATA__SHIFT 0x0
+#define MC_BIST_DATA_WORD6__DATA_MASK 0xffffffff
+#define MC_BIST_DATA_WORD6__DATA__SHIFT 0x0
+#define MC_BIST_DATA_WORD7__DATA_MASK 0xffffffff
+#define MC_BIST_DATA_WORD7__DATA__SHIFT 0x0
+#define MC_BIST_DATA_MASK__MASK_MASK 0xffffffff
+#define MC_BIST_DATA_MASK__MASK__SHIFT 0x0
+#define MC_BIST_MISMATCH_ADDR__COL_MASK 0x3ff
+#define MC_BIST_MISMATCH_ADDR__COL__SHIFT 0x0
+#define MC_BIST_MISMATCH_ADDR__ROW_MASK 0xfffc00
+#define MC_BIST_MISMATCH_ADDR__ROW__SHIFT 0xa
+#define MC_BIST_MISMATCH_ADDR__BANK_MASK 0xf000000
+#define MC_BIST_MISMATCH_ADDR__BANK__SHIFT 0x18
+#define MC_BIST_MISMATCH_ADDR__RANK_MASK 0x10000000
+#define MC_BIST_MISMATCH_ADDR__RANK__SHIFT 0x1c
+#define MC_BIST_MISMATCH_ADDR__COLH_MASK 0x20000000
+#define MC_BIST_MISMATCH_ADDR__COLH__SHIFT 0x1d
+#define MC_BIST_MISMATCH_ADDR__ROWH_MASK 0xc0000000
+#define MC_BIST_MISMATCH_ADDR__ROWH__SHIFT 0x1e
+#define MC_BIST_RDATA_WORD0__RDATA_MASK 0xffffffff
+#define MC_BIST_RDATA_WORD0__RDATA__SHIFT 0x0
+#define MC_BIST_RDATA_WORD1__RDATA_MASK 0xffffffff
+#define MC_BIST_RDATA_WORD1__RDATA__SHIFT 0x0
+#define MC_BIST_RDATA_WORD2__RDATA_MASK 0xffffffff
+#define MC_BIST_RDATA_WORD2__RDATA__SHIFT 0x0
+#define MC_BIST_RDATA_WORD3__RDATA_MASK 0xffffffff
+#define MC_BIST_RDATA_WORD3__RDATA__SHIFT 0x0
+#define MC_BIST_RDATA_WORD4__RDATA_MASK 0xffffffff
+#define MC_BIST_RDATA_WORD4__RDATA__SHIFT 0x0
+#define MC_BIST_RDATA_WORD5__RDATA_MASK 0xffffffff
+#define MC_BIST_RDATA_WORD5__RDATA__SHIFT 0x0
+#define MC_BIST_RDATA_WORD6__RDATA_MASK 0xffffffff
+#define MC_BIST_RDATA_WORD6__RDATA__SHIFT 0x0
+#define MC_BIST_RDATA_WORD7__RDATA_MASK 0xffffffff
+#define MC_BIST_RDATA_WORD7__RDATA__SHIFT 0x0
+#define MC_BIST_RDATA_MASK__MASK_MASK 0xffffffff
+#define MC_BIST_RDATA_MASK__MASK__SHIFT 0x0
+#define MC_BIST_RDATA_EDC__EDC_MASK 0xffffffff
+#define MC_BIST_RDATA_EDC__EDC__SHIFT 0x0
+#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD_MASK 0x3fffffff
+#define MC_SEQ_PERF_CNTL__MONITOR_PERIOD__SHIFT 0x0
+#define MC_SEQ_PERF_CNTL__CNTL_MASK 0xc0000000
+#define MC_SEQ_PERF_CNTL__CNTL__SHIFT 0x1e
+#define MC_SEQ_PERF_CNTL_1__PAUSE_MASK 0x1
+#define MC_SEQ_PERF_CNTL_1__PAUSE__SHIFT 0x0
+#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB_MASK 0x100
+#define MC_SEQ_PERF_CNTL_1__SEL_A_MSB__SHIFT 0x8
+#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB_MASK 0x200
+#define MC_SEQ_PERF_CNTL_1__SEL_B_MSB__SHIFT 0x9
+#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB_MASK 0x400
+#define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB__SHIFT 0xa
+#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB_MASK 0x800
+#define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB__SHIFT 0xb
+#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB_MASK 0x1000
+#define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB__SHIFT 0xc
+#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB_MASK 0x2000
+#define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB__SHIFT 0xd
+#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB_MASK 0x4000
+#define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB__SHIFT 0xe
+#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB_MASK 0x8000
+#define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB__SHIFT 0xf
+#define MC_SEQ_PERF_SEQ_CTL__SEL_A_MASK 0xf
+#define MC_SEQ_PERF_SEQ_CTL__SEL_A__SHIFT 0x0
+#define MC_SEQ_PERF_SEQ_CTL__SEL_B_MASK 0xf0
+#define MC_SEQ_PERF_SEQ_CTL__SEL_B__SHIFT 0x4
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C_MASK 0xf00
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C__SHIFT 0x8
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D_MASK 0xf000
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D__SHIFT 0xc
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A_MASK 0xf0000
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A__SHIFT 0x10
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B_MASK 0xf00000
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B__SHIFT 0x14
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C_MASK 0xf000000
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C__SHIFT 0x18
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D_MASK 0xf0000000
+#define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D__SHIFT 0x1c
+#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE_MASK 0xffffffff
+#define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE__SHIFT 0x0
+#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE_MASK 0xffffffff
+#define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE__SHIFT 0x0
+#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE_MASK 0xffffffff
+#define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE__SHIFT 0x0
+#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE_MASK 0xffffffff
+#define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE__SHIFT 0x0
+#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE_MASK 0xffffffff
+#define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE__SHIFT 0x0
+#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE_MASK 0xffffffff
+#define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE__SHIFT 0x0
+#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE_MASK 0xffffffff
+#define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE__SHIFT 0x0
+#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE_MASK 0xffffffff
+#define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE__SHIFT 0x0
+#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0_MASK 0x1
+#define MC_SEQ_STATUS_M__PWRUP_COMPL_D0__SHIFT 0x0
+#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1_MASK 0x2
+#define MC_SEQ_STATUS_M__PWRUP_COMPL_D1__SHIFT 0x1
+#define MC_SEQ_STATUS_M__CMD_RDY_D0_MASK 0x4
+#define MC_SEQ_STATUS_M__CMD_RDY_D0__SHIFT 0x2
+#define MC_SEQ_STATUS_M__CMD_RDY_D1_MASK 0x8
+#define MC_SEQ_STATUS_M__CMD_RDY_D1__SHIFT 0x3
+#define MC_SEQ_STATUS_M__SLF_D0_MASK 0x10
+#define MC_SEQ_STATUS_M__SLF_D0__SHIFT 0x4
+#define MC_SEQ_STATUS_M__SLF_D1_MASK 0x20
+#define MC_SEQ_STATUS_M__SLF_D1__SHIFT 0x5
+#define MC_SEQ_STATUS_M__SS_SLF_D0_MASK 0x40
+#define MC_SEQ_STATUS_M__SS_SLF_D0__SHIFT 0x6
+#define MC_SEQ_STATUS_M__SS_SLF_D1_MASK 0x80
+#define MC_SEQ_STATUS_M__SS_SLF_D1__SHIFT 0x7
+#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY_MASK 0x100
+#define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY__SHIFT 0x8
+#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY_MASK 0x200
+#define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY__SHIFT 0x9
+#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL_MASK 0x1000
+#define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL__SHIFT 0xc
+#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL_MASK 0x2000
+#define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL__SHIFT 0xd
+#define MC_SEQ_STATUS_M__SEQ0_BUSY_MASK 0x4000
+#define MC_SEQ_STATUS_M__SEQ0_BUSY__SHIFT 0xe
+#define MC_SEQ_STATUS_M__SEQ1_BUSY_MASK 0x8000
+#define MC_SEQ_STATUS_M__SEQ1_BUSY__SHIFT 0xf
+#define MC_SEQ_STATUS_M__PMG_PWRSTATE_MASK 0x10000
+#define MC_SEQ_STATUS_M__PMG_PWRSTATE__SHIFT 0x10
+#define MC_SEQ_STATUS_M__PMG_FSMSTATE_MASK 0x1f00000
+#define MC_SEQ_STATUS_M__PMG_FSMSTATE__SHIFT 0x14
+#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS_MASK 0x2000000
+#define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS__SHIFT 0x19
+#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS_MASK 0x4000000
+#define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS__SHIFT 0x1a
+#define MC_SEQ_STATUS_M__SEQ0_ALLOWSTOP_MASK 0x8000000
+#define MC_SEQ_STATUS_M__SEQ0_ALLOWSTOP__SHIFT 0x1b
+#define MC_SEQ_STATUS_M__SEQ1_ALLOWSTOP_MASK 0x10000000
+#define MC_SEQ_STATUS_M__SEQ1_ALLOWSTOP__SHIFT 0x1c
+#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL_MASK 0x1
+#define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL__SHIFT 0x0
+#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL_MASK 0x2
+#define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL__SHIFT 0x1
+#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL_MASK 0x10
+#define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL__SHIFT 0x4
+#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL_MASK 0x20
+#define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL__SHIFT 0x5
+#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY_MASK 0x100
+#define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY__SHIFT 0x8
+#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY_MASK 0x200
+#define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY__SHIFT 0x9
+#define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffff
+#define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x0
+#define MC_SEQ_VENDOR_ID_I0__VALUE_MASK 0xffffffff
+#define MC_SEQ_VENDOR_ID_I0__VALUE__SHIFT 0x0
+#define MC_SEQ_VENDOR_ID_I1__VALUE_MASK 0xffffffff
+#define MC_SEQ_VENDOR_ID_I1__VALUE__SHIFT 0x0
+#define MC_SEQ_MISC0__VALUE_MASK 0xffffffff
+#define MC_SEQ_MISC0__VALUE__SHIFT 0x0
+#define MC_SEQ_MISC1__VALUE_MASK 0xffffffff
+#define MC_SEQ_MISC1__VALUE__SHIFT 0x0
+#define MC_SEQ_RESERVE_0_S__SCLK_FIELD_MASK 0xffffffff
+#define MC_SEQ_RESERVE_0_S__SCLK_FIELD__SHIFT 0x0
+#define MC_SEQ_RESERVE_1_S__SCLK_FIELD_MASK 0xffffffff
+#define MC_SEQ_RESERVE_1_S__SCLK_FIELD__SHIFT 0x0
+#define MC_SEQ_RESERVE_M__MCLK_FIELD_MASK 0xffffffff
+#define MC_SEQ_RESERVE_M__MCLK_FIELD__SHIFT 0x0
+#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV_MASK 0xfff
+#define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV__SHIFT 0x0
+#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV_MASK 0xfff000
+#define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV__SHIFT 0xc
+#define MC_SEQ_IO_RESERVE_D0__APHY_RSV_MASK 0xff000000
+#define MC_SEQ_IO_RESERVE_D0__APHY_RSV__SHIFT 0x18
+#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV_MASK 0xfff
+#define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV__SHIFT 0x0
+#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV_MASK 0xfff000
+#define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV__SHIFT 0xc
+#define MC_SEQ_IO_RESERVE_D1__APHY_RSV_MASK 0xff000000
+#define MC_SEQ_IO_RESERVE_D1__APHY_RSV__SHIFT 0x18
+#define MC_SEQ_SUP_CNTL__RUN_MASK 0x1
+#define MC_SEQ_SUP_CNTL__RUN__SHIFT 0x0
+#define MC_SEQ_SUP_CNTL__SINGLE_STEP_MASK 0x2
+#define MC_SEQ_SUP_CNTL__SINGLE_STEP__SHIFT 0x1
+#define MC_SEQ_SUP_CNTL__SW_WAKE_MASK 0x4
+#define MC_SEQ_SUP_CNTL__SW_WAKE__SHIFT 0x2
+#define MC_SEQ_SUP_CNTL__RESET_PC_MASK 0x8
+#define MC_SEQ_SUP_CNTL__RESET_PC__SHIFT 0x3
+#define MC_SEQ_SUP_CNTL__PGM_WRITE_MASK 0x10
+#define MC_SEQ_SUP_CNTL__PGM_WRITE__SHIFT 0x4
+#define MC_SEQ_SUP_CNTL__PGM_READ_MASK 0x20
+#define MC_SEQ_SUP_CNTL__PGM_READ__SHIFT 0x5
+#define MC_SEQ_SUP_CNTL__FAST_WRITE_MASK 0x40
+#define MC_SEQ_SUP_CNTL__FAST_WRITE__SHIFT 0x6
+#define MC_SEQ_SUP_CNTL__BKPT_CLEAR_MASK 0x80
+#define MC_SEQ_SUP_CNTL__BKPT_CLEAR__SHIFT 0x7
+#define MC_SEQ_SUP_CNTL__PGM_CHKSUM_MASK 0xff800000
+#define MC_SEQ_SUP_CNTL__PGM_CHKSUM__SHIFT 0x17
+#define MC_SEQ_SUP_PGM__CNTL_MASK 0xffffffff
+#define MC_SEQ_SUP_PGM__CNTL__SHIFT 0x0
+#define MC_SEQ_SUP_GP0_STAT__STATUS_MASK 0xffffffff
+#define MC_SEQ_SUP_GP0_STAT__STATUS__SHIFT 0x0
+#define MC_SEQ_SUP_GP1_STAT__STATUS_MASK 0xffffffff
+#define MC_SEQ_SUP_GP1_STAT__STATUS__SHIFT 0x0
+#define MC_SEQ_SUP_GP2_STAT__STATUS_MASK 0xffffffff
+#define MC_SEQ_SUP_GP2_STAT__STATUS__SHIFT 0x0
+#define MC_SEQ_SUP_GP3_STAT__STATUS_MASK 0xffffffff
+#define MC_SEQ_SUP_GP3_STAT__STATUS__SHIFT 0x0
+#define MC_SEQ_SUP_IR_STAT__STATUS_MASK 0xffffffff
+#define MC_SEQ_SUP_IR_STAT__STATUS__SHIFT 0x0
+#define MC_SEQ_SUP_DEC_STAT__STATUS_MASK 0xffffffff
+#define MC_SEQ_SUP_DEC_STAT__STATUS__SHIFT 0x0
+#define MC_SEQ_SUP_PGM_STAT__STATUS_MASK 0xffffffff
+#define MC_SEQ_SUP_PGM_STAT__STATUS__SHIFT 0x0
+#define MC_SEQ_SUP_R_PGM__PGM_MASK 0xffffffff
+#define MC_SEQ_SUP_R_PGM__PGM__SHIFT 0x0
+#define MC_SEQ_MISC3__VALUE_MASK 0xffffffff
+#define MC_SEQ_MISC3__VALUE__SHIFT 0x0
+#define MC_SEQ_MISC4__VALUE_MASK 0xffffffff
+#define MC_SEQ_MISC4__VALUE__SHIFT 0x0
+#define MC_SEQ_MISC5__VALUE_MASK 0xffffffff
+#define MC_SEQ_MISC5__VALUE__SHIFT 0x0
+#define MC_SEQ_MISC6__VALUE_MASK 0xffffffff
+#define MC_SEQ_MISC6__VALUE__SHIFT 0x0
+#define MC_SEQ_MISC7__VALUE_MASK 0xffffffff
+#define MC_SEQ_MISC7__VALUE__SHIFT 0x0
+#define MC_SEQ_MISC8__VALUE_MASK 0xffffffff
+#define MC_SEQ_MISC8__VALUE__SHIFT 0x0
+#define MC_SEQ_MISC9__VALUE_MASK 0xffffffff
+#define MC_SEQ_MISC9__VALUE__SHIFT 0x0
+#define MC_SEQ_CG__CG_SEQ_REQ_MASK 0xff
+#define MC_SEQ_CG__CG_SEQ_REQ__SHIFT 0x0
+#define MC_SEQ_CG__CG_SEQ_RESP_MASK 0xff00
+#define MC_SEQ_CG__CG_SEQ_RESP__SHIFT 0x8
+#define MC_SEQ_CG__SEQ_CG_REQ_MASK 0xff0000
+#define MC_SEQ_CG__SEQ_CG_REQ__SHIFT 0x10
+#define MC_SEQ_CG__SEQ_CG_RESP_MASK 0xff000000
+#define MC_SEQ_CG__SEQ_CG_RESP__SHIFT 0x18
+#define MC_SEQ_BYTE_REMAP_D0__BYTE0_MASK 0x3
+#define MC_SEQ_BYTE_REMAP_D0__BYTE0__SHIFT 0x0
+#define MC_SEQ_BYTE_REMAP_D0__BYTE1_MASK 0xc
+#define MC_SEQ_BYTE_REMAP_D0__BYTE1__SHIFT 0x2
+#define MC_SEQ_BYTE_REMAP_D0__BYTE2_MASK 0x30
+#define MC_SEQ_BYTE_REMAP_D0__BYTE2__SHIFT 0x4
+#define MC_SEQ_BYTE_REMAP_D0__BYTE3_MASK 0xc0
+#define MC_SEQ_BYTE_REMAP_D0__BYTE3__SHIFT 0x6
+#define MC_SEQ_BYTE_REMAP_D1__BYTE0_MASK 0x3
+#define MC_SEQ_BYTE_REMAP_D1__BYTE0__SHIFT 0x0
+#define MC_SEQ_BYTE_REMAP_D1__BYTE1_MASK 0xc
+#define MC_SEQ_BYTE_REMAP_D1__BYTE1__SHIFT 0x2
+#define MC_SEQ_BYTE_REMAP_D1__BYTE2_MASK 0x30
+#define MC_SEQ_BYTE_REMAP_D1__BYTE2__SHIFT 0x4
+#define MC_SEQ_BYTE_REMAP_D1__BYTE3_MASK 0xc0
+#define MC_SEQ_BYTE_REMAP_D1__BYTE3__SHIFT 0x6
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT0_MASK 0x7
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT0__SHIFT 0x0
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT1_MASK 0x38
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT1__SHIFT 0x3
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT2_MASK 0x1c0
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT2__SHIFT 0x6
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT3_MASK 0xe00
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT3__SHIFT 0x9
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT4_MASK 0x7000
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT4__SHIFT 0xc
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT5_MASK 0x38000
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT5__SHIFT 0xf
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT6_MASK 0x1c0000
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT6__SHIFT 0x12
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT7_MASK 0xe00000
+#define MC_SEQ_BIT_REMAP_B0_D0__BIT7__SHIFT 0x15
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT0_MASK 0x7
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT0__SHIFT 0x0
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT1_MASK 0x38
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT1__SHIFT 0x3
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT2_MASK 0x1c0
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT2__SHIFT 0x6
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT3_MASK 0xe00
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT3__SHIFT 0x9
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT4_MASK 0x7000
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT4__SHIFT 0xc
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT5_MASK 0x38000
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT5__SHIFT 0xf
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT6_MASK 0x1c0000
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT6__SHIFT 0x12
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT7_MASK 0xe00000
+#define MC_SEQ_BIT_REMAP_B1_D0__BIT7__SHIFT 0x15
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT0_MASK 0x7
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT0__SHIFT 0x0
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT1_MASK 0x38
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT1__SHIFT 0x3
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT2_MASK 0x1c0
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT2__SHIFT 0x6
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT3_MASK 0xe00
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT3__SHIFT 0x9
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT4_MASK 0x7000
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT4__SHIFT 0xc
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT5_MASK 0x38000
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT5__SHIFT 0xf
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT6_MASK 0x1c0000
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT6__SHIFT 0x12
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT7_MASK 0xe00000
+#define MC_SEQ_BIT_REMAP_B2_D0__BIT7__SHIFT 0x15
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT0_MASK 0x7
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT0__SHIFT 0x0
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT1_MASK 0x38
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT1__SHIFT 0x3
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT2_MASK 0x1c0
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT2__SHIFT 0x6
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT3_MASK 0xe00
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT3__SHIFT 0x9
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT4_MASK 0x7000
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT4__SHIFT 0xc
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT5_MASK 0x38000
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT5__SHIFT 0xf
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT6_MASK 0x1c0000
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT6__SHIFT 0x12
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT7_MASK 0xe00000
+#define MC_SEQ_BIT_REMAP_B3_D0__BIT7__SHIFT 0x15
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT0_MASK 0x7
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT0__SHIFT 0x0
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT1_MASK 0x38
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT1__SHIFT 0x3
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT2_MASK 0x1c0
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT2__SHIFT 0x6
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT3_MASK 0xe00
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT3__SHIFT 0x9
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT4_MASK 0x7000
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT4__SHIFT 0xc
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT5_MASK 0x38000
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT5__SHIFT 0xf
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT6_MASK 0x1c0000
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT6__SHIFT 0x12
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT7_MASK 0xe00000
+#define MC_SEQ_BIT_REMAP_B0_D1__BIT7__SHIFT 0x15
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT0_MASK 0x7
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT0__SHIFT 0x0
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT1_MASK 0x38
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT1__SHIFT 0x3
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT2_MASK 0x1c0
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT2__SHIFT 0x6
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT3_MASK 0xe00
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT3__SHIFT 0x9
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT4_MASK 0x7000
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT4__SHIFT 0xc
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT5_MASK 0x38000
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT5__SHIFT 0xf
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT6_MASK 0x1c0000
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT6__SHIFT 0x12
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT7_MASK 0xe00000
+#define MC_SEQ_BIT_REMAP_B1_D1__BIT7__SHIFT 0x15
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT0_MASK 0x7
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT0__SHIFT 0x0
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT1_MASK 0x38
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT1__SHIFT 0x3
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT2_MASK 0x1c0
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT2__SHIFT 0x6
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT3_MASK 0xe00
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT3__SHIFT 0x9
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT4_MASK 0x7000
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT4__SHIFT 0xc
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT5_MASK 0x38000
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT5__SHIFT 0xf
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT6_MASK 0x1c0000
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT6__SHIFT 0x12
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT7_MASK 0xe00000
+#define MC_SEQ_BIT_REMAP_B2_D1__BIT7__SHIFT 0x15
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT0_MASK 0x7
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT0__SHIFT 0x0
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT1_MASK 0x38
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT1__SHIFT 0x3
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT2_MASK 0x1c0
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT2__SHIFT 0x6
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT3_MASK 0xe00
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT3__SHIFT 0x9
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT4_MASK 0x7000
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT4__SHIFT 0xc
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT5_MASK 0x38000
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT5__SHIFT 0xf
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT6_MASK 0x1c0000
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT6__SHIFT 0x12
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT7_MASK 0xe00000
+#define MC_SEQ_BIT_REMAP_B3_D1__BIT7__SHIFT 0x15
+#define MC_SEQ_RAS_TIMING_LP__TRCDW_MASK 0x1f
+#define MC_SEQ_RAS_TIMING_LP__TRCDW__SHIFT 0x0
+#define MC_SEQ_RAS_TIMING_LP__TRCDWA_MASK 0x3e0
+#define MC_SEQ_RAS_TIMING_LP__TRCDWA__SHIFT 0x5
+#define MC_SEQ_RAS_TIMING_LP__TRCDR_MASK 0x7c00
+#define MC_SEQ_RAS_TIMING_LP__TRCDR__SHIFT 0xa
+#define MC_SEQ_RAS_TIMING_LP__TRCDRA_MASK 0xf8000
+#define MC_SEQ_RAS_TIMING_LP__TRCDRA__SHIFT 0xf
+#define MC_SEQ_RAS_TIMING_LP__TRRD_MASK 0xf00000
+#define MC_SEQ_RAS_TIMING_LP__TRRD__SHIFT 0x14
+#define MC_SEQ_RAS_TIMING_LP__TRC_MASK 0x7f000000
+#define MC_SEQ_RAS_TIMING_LP__TRC__SHIFT 0x18
+#define MC_SEQ_CAS_TIMING_LP__TNOPW_MASK 0x3
+#define MC_SEQ_CAS_TIMING_LP__TNOPW__SHIFT 0x0
+#define MC_SEQ_CAS_TIMING_LP__TNOPR_MASK 0xc
+#define MC_SEQ_CAS_TIMING_LP__TNOPR__SHIFT 0x2
+#define MC_SEQ_CAS_TIMING_LP__TR2W_MASK 0x1f0
+#define MC_SEQ_CAS_TIMING_LP__TR2W__SHIFT 0x4
+#define MC_SEQ_CAS_TIMING_LP__TCCDL_MASK 0xe00
+#define MC_SEQ_CAS_TIMING_LP__TCCDL__SHIFT 0x9
+#define MC_SEQ_CAS_TIMING_LP__TR2R_MASK 0xf000
+#define MC_SEQ_CAS_TIMING_LP__TR2R__SHIFT 0xc
+#define MC_SEQ_CAS_TIMING_LP__TW2R_MASK 0x1f0000
+#define MC_SEQ_CAS_TIMING_LP__TW2R__SHIFT 0x10
+#define MC_SEQ_CAS_TIMING_LP__TCL_MASK 0x1f000000
+#define MC_SEQ_CAS_TIMING_LP__TCL__SHIFT 0x18
+#define MC_SEQ_MISC_TIMING_LP__TRP_WRA_MASK 0x3f
+#define MC_SEQ_MISC_TIMING_LP__TRP_WRA__SHIFT 0x0
+#define MC_SEQ_MISC_TIMING_LP__TRP_RDA_MASK 0x3f00
+#define MC_SEQ_MISC_TIMING_LP__TRP_RDA__SHIFT 0x8
+#define MC_SEQ_MISC_TIMING_LP__TRP_MASK 0xf8000
+#define MC_SEQ_MISC_TIMING_LP__TRP__SHIFT 0xf
+#define MC_SEQ_MISC_TIMING_LP__TRFC_MASK 0x1ff00000
+#define MC_SEQ_MISC_TIMING_LP__TRFC__SHIFT 0x14
+#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA_MASK 0x7
+#define MC_SEQ_MISC_TIMING2_LP__PA2RDATA__SHIFT 0x0
+#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA_MASK 0x70
+#define MC_SEQ_MISC_TIMING2_LP__PA2WDATA__SHIFT 0x4
+#define MC_SEQ_MISC_TIMING2_LP__FAW_MASK 0x1f00
+#define MC_SEQ_MISC_TIMING2_LP__FAW__SHIFT 0x8
+#define MC_SEQ_MISC_TIMING2_LP__TREDC_MASK 0xe000
+#define MC_SEQ_MISC_TIMING2_LP__TREDC__SHIFT 0xd
+#define MC_SEQ_MISC_TIMING2_LP__TWEDC_MASK 0x1f0000
+#define MC_SEQ_MISC_TIMING2_LP__TWEDC__SHIFT 0x10
+#define MC_SEQ_MISC_TIMING2_LP__TADR_MASK 0xe00000
+#define MC_SEQ_MISC_TIMING2_LP__TADR__SHIFT 0x15
+#define MC_SEQ_MISC_TIMING2_LP__TFCKTR_MASK 0xf000000
+#define MC_SEQ_MISC_TIMING2_LP__TFCKTR__SHIFT 0x18
+#define MC_SEQ_MISC_TIMING2_LP__TWDATATR_MASK 0xf0000000
+#define MC_SEQ_MISC_TIMING2_LP__TWDATATR__SHIFT 0x1c
+#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY_MASK 0x7
+#define MC_SEQ_RD_CTL_D0_LP__RCV_DLY__SHIFT 0x0
+#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT_MASK 0xf8
+#define MC_SEQ_RD_CTL_D0_LP__RCV_EXT__SHIFT 0x3
+#define MC_SEQ_RD_CTL_D0_LP__RST_SEL_MASK 0x300
+#define MC_SEQ_RD_CTL_D0_LP__RST_SEL__SHIFT 0x8
+#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY_MASK 0xc00
+#define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY__SHIFT 0xa
+#define MC_SEQ_RD_CTL_D0_LP__RST_HLD_MASK 0xf000
+#define MC_SEQ_RD_CTL_D0_LP__RST_HLD__SHIFT 0xc
+#define MC_SEQ_RD_CTL_D0_LP__STR_PRE_MASK 0x10000
+#define MC_SEQ_RD_CTL_D0_LP__STR_PRE__SHIFT 0x10
+#define MC_SEQ_RD_CTL_D0_LP__STR_PST_MASK 0x20000
+#define MC_SEQ_RD_CTL_D0_LP__STR_PST__SHIFT 0x11
+#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY_MASK 0x1f00000
+#define MC_SEQ_RD_CTL_D0_LP__RBS_DLY__SHIFT 0x14
+#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY_MASK 0x3e000000
+#define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY__SHIFT 0x19
+#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY_MASK 0x7
+#define MC_SEQ_RD_CTL_D1_LP__RCV_DLY__SHIFT 0x0
+#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT_MASK 0xf8
+#define MC_SEQ_RD_CTL_D1_LP__RCV_EXT__SHIFT 0x3
+#define MC_SEQ_RD_CTL_D1_LP__RST_SEL_MASK 0x300
+#define MC_SEQ_RD_CTL_D1_LP__RST_SEL__SHIFT 0x8
+#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY_MASK 0xc00
+#define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY__SHIFT 0xa
+#define MC_SEQ_RD_CTL_D1_LP__RST_HLD_MASK 0xf000
+#define MC_SEQ_RD_CTL_D1_LP__RST_HLD__SHIFT 0xc
+#define MC_SEQ_RD_CTL_D1_LP__STR_PRE_MASK 0x10000
+#define MC_SEQ_RD_CTL_D1_LP__STR_PRE__SHIFT 0x10
+#define MC_SEQ_RD_CTL_D1_LP__STR_PST_MASK 0x20000
+#define MC_SEQ_RD_CTL_D1_LP__STR_PST__SHIFT 0x11
+#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY_MASK 0x1f00000
+#define MC_SEQ_RD_CTL_D1_LP__RBS_DLY__SHIFT 0x14
+#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY_MASK 0x3e000000
+#define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY__SHIFT 0x19
+#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY_MASK 0xf
+#define MC_SEQ_WR_CTL_D0_LP__DAT_DLY__SHIFT 0x0
+#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY_MASK 0xf0
+#define MC_SEQ_WR_CTL_D0_LP__DQS_DLY__SHIFT 0x4
+#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR_MASK 0x100
+#define MC_SEQ_WR_CTL_D0_LP__DQS_XTR__SHIFT 0x8
+#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY_MASK 0x200
+#define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY__SHIFT 0x9
+#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY_MASK 0x400
+#define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY__SHIFT 0xa
+#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY_MASK 0x800
+#define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY__SHIFT 0xb
+#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY_MASK 0xf000
+#define MC_SEQ_WR_CTL_D0_LP__OEN_DLY__SHIFT 0xc
+#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT_MASK 0xf0000
+#define MC_SEQ_WR_CTL_D0_LP__OEN_EXT__SHIFT 0x10
+#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL_MASK 0x300000
+#define MC_SEQ_WR_CTL_D0_LP__OEN_SEL__SHIFT 0x14
+#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY_MASK 0xf000000
+#define MC_SEQ_WR_CTL_D0_LP__ODT_DLY__SHIFT 0x18
+#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT_MASK 0x10000000
+#define MC_SEQ_WR_CTL_D0_LP__ODT_EXT__SHIFT 0x1c
+#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY_MASK 0x20000000
+#define MC_SEQ_WR_CTL_D0_LP__ADR_DLY__SHIFT 0x1d
+#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY_MASK 0x40000000
+#define MC_SEQ_WR_CTL_D0_LP__CMD_DLY__SHIFT 0x1e
+#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY_MASK 0xf
+#define MC_SEQ_WR_CTL_D1_LP__DAT_DLY__SHIFT 0x0
+#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY_MASK 0xf0
+#define MC_SEQ_WR_CTL_D1_LP__DQS_DLY__SHIFT 0x4
+#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR_MASK 0x100
+#define MC_SEQ_WR_CTL_D1_LP__DQS_XTR__SHIFT 0x8
+#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY_MASK 0x200
+#define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY__SHIFT 0x9
+#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY_MASK 0x400
+#define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY__SHIFT 0xa
+#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY_MASK 0x800
+#define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY__SHIFT 0xb
+#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY_MASK 0xf000
+#define MC_SEQ_WR_CTL_D1_LP__OEN_DLY__SHIFT 0xc
+#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT_MASK 0xf0000
+#define MC_SEQ_WR_CTL_D1_LP__OEN_EXT__SHIFT 0x10
+#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL_MASK 0x300000
+#define MC_SEQ_WR_CTL_D1_LP__OEN_SEL__SHIFT 0x14
+#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY_MASK 0xf000000
+#define MC_SEQ_WR_CTL_D1_LP__ODT_DLY__SHIFT 0x18
+#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT_MASK 0x10000000
+#define MC_SEQ_WR_CTL_D1_LP__ODT_EXT__SHIFT 0x1c
+#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY_MASK 0x20000000
+#define MC_SEQ_WR_CTL_D1_LP__ADR_DLY__SHIFT 0x1d
+#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY_MASK 0x40000000
+#define MC_SEQ_WR_CTL_D1_LP__CMD_DLY__SHIFT 0x1e
+#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0_MASK 0x1
+#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0__SHIFT 0x0
+#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0_MASK 0x2
+#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0__SHIFT 0x1
+#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0_MASK 0x4
+#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0__SHIFT 0x2
+#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1_MASK 0x8
+#define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1__SHIFT 0x3
+#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1_MASK 0x10
+#define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1__SHIFT 0x4
+#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1_MASK 0x20
+#define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1__SHIFT 0x5
+#define MC_SEQ_WR_CTL_2_LP__WCDR_EN_MASK 0x40
+#define MC_SEQ_WR_CTL_2_LP__WCDR_EN__SHIFT 0x6
+#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MASK 0xffff
+#define MC_SEQ_PMG_CMD_EMRS_LP__ADR__SHIFT 0x0
+#define MC_SEQ_PMG_CMD_EMRS_LP__MOP_MASK 0x70000
+#define MC_SEQ_PMG_CMD_EMRS_LP__MOP__SHIFT 0x10
+#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB_MASK 0x80000
+#define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB__SHIFT 0x13
+#define MC_SEQ_PMG_CMD_EMRS_LP__END_MASK 0x100000
+#define MC_SEQ_PMG_CMD_EMRS_LP__END__SHIFT 0x14
+#define MC_SEQ_PMG_CMD_EMRS_LP__CSB_MASK 0x600000
+#define MC_SEQ_PMG_CMD_EMRS_LP__CSB__SHIFT 0x15
+#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1_MASK 0x10000000
+#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1__SHIFT 0x1c
+#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0_MASK 0x20000000
+#define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0__SHIFT 0x1d
+#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MASK 0xffff
+#define MC_SEQ_PMG_CMD_MRS_LP__ADR__SHIFT 0x0
+#define MC_SEQ_PMG_CMD_MRS_LP__MOP_MASK 0x70000
+#define MC_SEQ_PMG_CMD_MRS_LP__MOP__SHIFT 0x10
+#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB_MASK 0x80000
+#define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB__SHIFT 0x13
+#define MC_SEQ_PMG_CMD_MRS_LP__END_MASK 0x100000
+#define MC_SEQ_PMG_CMD_MRS_LP__END__SHIFT 0x14
+#define MC_SEQ_PMG_CMD_MRS_LP__CSB_MASK 0x600000
+#define MC_SEQ_PMG_CMD_MRS_LP__CSB__SHIFT 0x15
+#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1_MASK 0x10000000
+#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1__SHIFT 0x1c
+#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0_MASK 0x20000000
+#define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0__SHIFT 0x1d
+#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MASK 0xffff
+#define MC_SEQ_PMG_CMD_MRS1_LP__ADR__SHIFT 0x0
+#define MC_SEQ_PMG_CMD_MRS1_LP__MOP_MASK 0x70000
+#define MC_SEQ_PMG_CMD_MRS1_LP__MOP__SHIFT 0x10
+#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB_MASK 0x80000
+#define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB__SHIFT 0x13
+#define MC_SEQ_PMG_CMD_MRS1_LP__END_MASK 0x100000
+#define MC_SEQ_PMG_CMD_MRS1_LP__END__SHIFT 0x14
+#define MC_SEQ_PMG_CMD_MRS1_LP__CSB_MASK 0x600000
+#define MC_SEQ_PMG_CMD_MRS1_LP__CSB__SHIFT 0x15
+#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1_MASK 0x10000000
+#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1__SHIFT 0x1c
+#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0_MASK 0x20000000
+#define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0__SHIFT 0x1d
+#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MASK 0xffff
+#define MC_SEQ_PMG_CMD_MRS2_LP__ADR__SHIFT 0x0
+#define MC_SEQ_PMG_CMD_MRS2_LP__MOP_MASK 0x70000
+#define MC_SEQ_PMG_CMD_MRS2_LP__MOP__SHIFT 0x10
+#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB_MASK 0x80000
+#define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB__SHIFT 0x13
+#define MC_SEQ_PMG_CMD_MRS2_LP__END_MASK 0x100000
+#define MC_SEQ_PMG_CMD_MRS2_LP__END__SHIFT 0x14
+#define MC_SEQ_PMG_CMD_MRS2_LP__CSB_MASK 0x600000
+#define MC_SEQ_PMG_CMD_MRS2_LP__CSB__SHIFT 0x15
+#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1_MASK 0x10000000
+#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1__SHIFT 0x1c
+#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0_MASK 0x20000000
+#define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0__SHIFT 0x1d
+#define MC_SEQ_PMG_TIMING_LP__TCKSRE_MASK 0x7
+#define MC_SEQ_PMG_TIMING_LP__TCKSRE__SHIFT 0x0
+#define MC_SEQ_PMG_TIMING_LP__TCKSRX_MASK 0x70
+#define MC_SEQ_PMG_TIMING_LP__TCKSRX__SHIFT 0x4
+#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MASK 0xf00
+#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE__SHIFT 0x8
+#define MC_SEQ_PMG_TIMING_LP__TCKE_MASK 0x3f000
+#define MC_SEQ_PMG_TIMING_LP__TCKE__SHIFT 0xc
+#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_MASK 0x1c0000
+#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE__SHIFT 0x12
+#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB_MASK 0x800000
+#define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB__SHIFT 0x17
+#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS_MASK 0xff000000
+#define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS__SHIFT 0x18
+#define MC_SEQ_IO_RWORD0__RDATA_MASK 0xffffffff
+#define MC_SEQ_IO_RWORD0__RDATA__SHIFT 0x0
+#define MC_SEQ_IO_RWORD1__RDATA_MASK 0xffffffff
+#define MC_SEQ_IO_RWORD1__RDATA__SHIFT 0x0
+#define MC_SEQ_IO_RWORD2__RDATA_MASK 0xffffffff
+#define MC_SEQ_IO_RWORD2__RDATA__SHIFT 0x0
+#define MC_SEQ_IO_RWORD3__RDATA_MASK 0xffffffff
+#define MC_SEQ_IO_RWORD3__RDATA__SHIFT 0x0
+#define MC_SEQ_IO_RWORD4__RDATA_MASK 0xffffffff
+#define MC_SEQ_IO_RWORD4__RDATA__SHIFT 0x0
+#define MC_SEQ_IO_RWORD5__RDATA_MASK 0xffffffff
+#define MC_SEQ_IO_RWORD5__RDATA__SHIFT 0x0
+#define MC_SEQ_IO_RWORD6__RDATA_MASK 0xffffffff
+#define MC_SEQ_IO_RWORD6__RDATA__SHIFT 0x0
+#define MC_SEQ_IO_RWORD7__RDATA_MASK 0xffffffff
+#define MC_SEQ_IO_RWORD7__RDATA__SHIFT 0x0
+#define MC_SEQ_IO_RDBI__MASK_MASK 0xffffffff
+#define MC_SEQ_IO_RDBI__MASK__SHIFT 0x0
+#define MC_SEQ_IO_REDC__EDC_MASK 0xffffffff
+#define MC_SEQ_IO_REDC__EDC__SHIFT 0x0
+#define MC_SEQ_TCG_CNTL__RESET_MASK 0x1
+#define MC_SEQ_TCG_CNTL__RESET__SHIFT 0x0
+#define MC_SEQ_TCG_CNTL__ENABLE_D0_MASK 0x2
+#define MC_SEQ_TCG_CNTL__ENABLE_D0__SHIFT 0x1
+#define MC_SEQ_TCG_CNTL__ENABLE_D1_MASK 0x4
+#define MC_SEQ_TCG_CNTL__ENABLE_D1__SHIFT 0x2
+#define MC_SEQ_TCG_CNTL__START_MASK 0x8
+#define MC_SEQ_TCG_CNTL__START__SHIFT 0x3
+#define MC_SEQ_TCG_CNTL__NFIFO_MASK 0x70
+#define MC_SEQ_TCG_CNTL__NFIFO__SHIFT 0x4
+#define MC_SEQ_TCG_CNTL__INFINITE_CMD_MASK 0x80
+#define MC_SEQ_TCG_CNTL__INFINITE_CMD__SHIFT 0x7
+#define MC_SEQ_TCG_CNTL__MOP_MASK 0xf00
+#define MC_SEQ_TCG_CNTL__MOP__SHIFT 0x8
+#define MC_SEQ_TCG_CNTL__DATA_CNT_MASK 0xf000
+#define MC_SEQ_TCG_CNTL__DATA_CNT__SHIFT 0xc
+#define MC_SEQ_TCG_CNTL__LOAD_FIFO_MASK 0x10000
+#define MC_SEQ_TCG_CNTL__LOAD_FIFO__SHIFT 0x10
+#define MC_SEQ_TCG_CNTL__SHORT_LDFF_MASK 0x20000
+#define MC_SEQ_TCG_CNTL__SHORT_LDFF__SHIFT 0x11
+#define MC_SEQ_TCG_CNTL__FRAME_TRAIN_MASK 0x40000
+#define MC_SEQ_TCG_CNTL__FRAME_TRAIN__SHIFT 0x12
+#define MC_SEQ_TCG_CNTL__BURST_NUM_MASK 0x380000
+#define MC_SEQ_TCG_CNTL__BURST_NUM__SHIFT 0x13
+#define MC_SEQ_TCG_CNTL__ISSUE_AREF_MASK 0x400000
+#define MC_SEQ_TCG_CNTL__ISSUE_AREF__SHIFT 0x16
+#define MC_SEQ_TCG_CNTL__TXDBI_CNTL_MASK 0x800000
+#define MC_SEQ_TCG_CNTL__TXDBI_CNTL__SHIFT 0x17
+#define MC_SEQ_TCG_CNTL__VPTR_MASK_MASK 0x1000000
+#define MC_SEQ_TCG_CNTL__VPTR_MASK__SHIFT 0x18
+#define MC_SEQ_TCG_CNTL__AREF_LAST_MASK 0x2000000
+#define MC_SEQ_TCG_CNTL__AREF_LAST__SHIFT 0x19
+#define MC_SEQ_TCG_CNTL__AREF_BOTH_MASK 0x4000000
+#define MC_SEQ_TCG_CNTL__AREF_BOTH__SHIFT 0x1a
+#define MC_SEQ_TCG_CNTL__LD_RTDATA_OVR_MASK 0x10000000
+#define MC_SEQ_TCG_CNTL__LD_RTDATA_OVR__SHIFT 0x1c
+#define MC_SEQ_TCG_CNTL__LD_RTDATA_CH_MASK 0x20000000
+#define MC_SEQ_TCG_CNTL__LD_RTDATA_CH__SHIFT 0x1d
+#define MC_SEQ_TCG_CNTL__DONE_MASK 0x80000000
+#define MC_SEQ_TCG_CNTL__DONE__SHIFT 0x1f
+#define MC_SEQ_TSM_CTRL__START_MASK 0x1
+#define MC_SEQ_TSM_CTRL__START__SHIFT 0x0
+#define MC_SEQ_TSM_CTRL__CAPTURE_START_MASK 0x2
+#define MC_SEQ_TSM_CTRL__CAPTURE_START__SHIFT 0x1
+#define MC_SEQ_TSM_CTRL__DONE_MASK 0x4
+#define MC_SEQ_TSM_CTRL__DONE__SHIFT 0x2
+#define MC_SEQ_TSM_CTRL__ERR_MASK 0x8
+#define MC_SEQ_TSM_CTRL__ERR__SHIFT 0x3
+#define MC_SEQ_TSM_CTRL__STEP_MASK 0x10
+#define MC_SEQ_TSM_CTRL__STEP__SHIFT 0x4
+#define MC_SEQ_TSM_CTRL__DIRECTION_MASK 0x20
+#define MC_SEQ_TSM_CTRL__DIRECTION__SHIFT 0x5
+#define MC_SEQ_TSM_CTRL__INVERT_MASK 0x40
+#define MC_SEQ_TSM_CTRL__INVERT__SHIFT 0x6
+#define MC_SEQ_TSM_CTRL__MASK_BITS_MASK 0x80
+#define MC_SEQ_TSM_CTRL__MASK_BITS__SHIFT 0x7
+#define MC_SEQ_TSM_CTRL__UPDATE_LOOP_MASK 0x300
+#define MC_SEQ_TSM_CTRL__UPDATE_LOOP__SHIFT 0x8
+#define MC_SEQ_TSM_CTRL__ROT_INV_MASK 0x400
+#define MC_SEQ_TSM_CTRL__ROT_INV__SHIFT 0xa
+#define MC_SEQ_TSM_CTRL__DUAL_CH_EN_MASK 0x800
+#define MC_SEQ_TSM_CTRL__DUAL_CH_EN__SHIFT 0xb
+#define MC_SEQ_TSM_CTRL__DONE0_MASK 0x1000
+#define MC_SEQ_TSM_CTRL__DONE0__SHIFT 0xc
+#define MC_SEQ_TSM_CTRL__DONE1_MASK 0x2000
+#define MC_SEQ_TSM_CTRL__DONE1__SHIFT 0xd
+#define MC_SEQ_TSM_CTRL__POINTER_MASK 0xffff0000
+#define MC_SEQ_TSM_CTRL__POINTER__SHIFT 0x10
+#define MC_SEQ_TSM_GCNT__TRUE_ACT_MASK 0xf
+#define MC_SEQ_TSM_GCNT__TRUE_ACT__SHIFT 0x0
+#define MC_SEQ_TSM_GCNT__FALSE_ACT_MASK 0xf0
+#define MC_SEQ_TSM_GCNT__FALSE_ACT__SHIFT 0x4
+#define MC_SEQ_TSM_GCNT__TESTS_MASK 0xff00
+#define MC_SEQ_TSM_GCNT__TESTS__SHIFT 0x8
+#define MC_SEQ_TSM_GCNT__COMP_VALUE_MASK 0xffff0000
+#define MC_SEQ_TSM_GCNT__COMP_VALUE__SHIFT 0x10
+#define MC_SEQ_TSM_OCNT__TRUE_ACT_MASK 0xf
+#define MC_SEQ_TSM_OCNT__TRUE_ACT__SHIFT 0x0
+#define MC_SEQ_TSM_OCNT__FALSE_ACT_MASK 0xf0
+#define MC_SEQ_TSM_OCNT__FALSE_ACT__SHIFT 0x4
+#define MC_SEQ_TSM_OCNT__TESTS_MASK 0xff00
+#define MC_SEQ_TSM_OCNT__TESTS__SHIFT 0x8
+#define MC_SEQ_TSM_OCNT__CMP_VALUE_MASK 0xffff0000
+#define MC_SEQ_TSM_OCNT__CMP_VALUE__SHIFT 0x10
+#define MC_SEQ_TSM_NCNT__TRUE_ACT_MASK 0xf
+#define MC_SEQ_TSM_NCNT__TRUE_ACT__SHIFT 0x0
+#define MC_SEQ_TSM_NCNT__FALSE_ACT_MASK 0xf0
+#define MC_SEQ_TSM_NCNT__FALSE_ACT__SHIFT 0x4
+#define MC_SEQ_TSM_NCNT__TESTS_MASK 0xff00
+#define MC_SEQ_TSM_NCNT__TESTS__SHIFT 0x8
+#define MC_SEQ_TSM_NCNT__RANGE_LOW_MASK 0xf0000
+#define MC_SEQ_TSM_NCNT__RANGE_LOW__SHIFT 0x10
+#define MC_SEQ_TSM_NCNT__RANGE_HIGH_MASK 0xf00000
+#define MC_SEQ_TSM_NCNT__RANGE_HIGH__SHIFT 0x14
+#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP_MASK 0xf000000
+#define MC_SEQ_TSM_NCNT__NIBBLE_SKIP__SHIFT 0x18
+#define MC_SEQ_TSM_BCNT__TRUE_ACT_MASK 0xf
+#define MC_SEQ_TSM_BCNT__TRUE_ACT__SHIFT 0x0
+#define MC_SEQ_TSM_BCNT__FALSE_ACT_MASK 0xf0
+#define MC_SEQ_TSM_BCNT__FALSE_ACT__SHIFT 0x4
+#define MC_SEQ_TSM_BCNT__BCNT_TESTS_MASK 0xff00
+#define MC_SEQ_TSM_BCNT__BCNT_TESTS__SHIFT 0x8
+#define MC_SEQ_TSM_BCNT__COMP_VALUE_MASK 0xff0000
+#define MC_SEQ_TSM_BCNT__COMP_VALUE__SHIFT 0x10
+#define MC_SEQ_TSM_BCNT__DONE_TESTS_MASK 0xff000000
+#define MC_SEQ_TSM_BCNT__DONE_TESTS__SHIFT 0x18
+#define MC_SEQ_TSM_FLAG__TRUE_ACT_MASK 0xf
+#define MC_SEQ_TSM_FLAG__TRUE_ACT__SHIFT 0x0
+#define MC_SEQ_TSM_FLAG__FALSE_ACT_MASK 0xf0
+#define MC_SEQ_TSM_FLAG__FALSE_ACT__SHIFT 0x4
+#define MC_SEQ_TSM_FLAG__FLAG_TESTS_MASK 0xff00
+#define MC_SEQ_TSM_FLAG__FLAG_TESTS__SHIFT 0x8
+#define MC_SEQ_TSM_FLAG__NBBL_MASK_MASK 0xf0000
+#define MC_SEQ_TSM_FLAG__NBBL_MASK__SHIFT 0x10
+#define MC_SEQ_TSM_FLAG__ERROR_TESTS_MASK 0xff000000
+#define MC_SEQ_TSM_FLAG__ERROR_TESTS__SHIFT 0x18
+#define MC_SEQ_TSM_UPDATE__TRUE_ACT_MASK 0xf
+#define MC_SEQ_TSM_UPDATE__TRUE_ACT__SHIFT 0x0
+#define MC_SEQ_TSM_UPDATE__FALSE_ACT_MASK 0xf0
+#define MC_SEQ_TSM_UPDATE__FALSE_ACT__SHIFT 0x4
+#define MC_SEQ_TSM_UPDATE__UPDT_TESTS_MASK 0xff00
+#define MC_SEQ_TSM_UPDATE__UPDT_TESTS__SHIFT 0x8
+#define MC_SEQ_TSM_UPDATE__AREF_COUNT_MASK 0xff0000
+#define MC_SEQ_TSM_UPDATE__AREF_COUNT__SHIFT 0x10
+#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS_MASK 0xff000000
+#define MC_SEQ_TSM_UPDATE__CAPTR_TESTS__SHIFT 0x18
+#define MC_SEQ_TSM_EDC__EDC_MASK 0xffffffff
+#define MC_SEQ_TSM_EDC__EDC__SHIFT 0x0
+#define MC_SEQ_TSM_DBI__DBI_MASK 0xffffffff
+#define MC_SEQ_TSM_DBI__DBI__SHIFT 0x0
+#define MC_SEQ_TSM_WCDR__WCDR_MASK 0xffffffff
+#define MC_SEQ_TSM_WCDR__WCDR__SHIFT 0x0
+#define MC_SEQ_TSM_MISC__WCDR_PTR_MASK 0xffff
+#define MC_SEQ_TSM_MISC__WCDR_PTR__SHIFT 0x0
+#define MC_SEQ_TSM_MISC__WCDR_MASK_MASK 0xf0000
+#define MC_SEQ_TSM_MISC__WCDR_MASK__SHIFT 0x10
+#define MC_SEQ_TSM_MISC__CH1_OFFSET_MASK 0x3f00000
+#define MC_SEQ_TSM_MISC__CH1_OFFSET__SHIFT 0x14
+#define MC_SEQ_TSM_MISC__CH1_WCDR_OFFSET_MASK 0xfc000000
+#define MC_SEQ_TSM_MISC__CH1_WCDR_OFFSET__SHIFT 0x1a
+#define MC_SEQ_TIMER_WR__COUNTER_MASK 0xffffffff
+#define MC_SEQ_TIMER_WR__COUNTER__SHIFT 0x0
+#define MC_SEQ_TIMER_RD__COUNTER_MASK 0xffffffff
+#define MC_SEQ_TIMER_RD__COUNTER__SHIFT 0x0
+#define MC_SEQ_DRAM_ERROR_INSERTION__TX_MASK 0xffff
+#define MC_SEQ_DRAM_ERROR_INSERTION__TX__SHIFT 0x0
+#define MC_SEQ_DRAM_ERROR_INSERTION__RX_MASK 0xffff0000
+#define MC_SEQ_DRAM_ERROR_INSERTION__RX__SHIFT 0x10
+#define MC_PHY_TIMING_D0__RXC0_DLY_MASK 0xf
+#define MC_PHY_TIMING_D0__RXC0_DLY__SHIFT 0x0
+#define MC_PHY_TIMING_D0__RXC0_EXT_MASK 0xf0
+#define MC_PHY_TIMING_D0__RXC0_EXT__SHIFT 0x4
+#define MC_PHY_TIMING_D0__RXC1_DLY_MASK 0xf00
+#define MC_PHY_TIMING_D0__RXC1_DLY__SHIFT 0x8
+#define MC_PHY_TIMING_D0__RXC1_EXT_MASK 0xf000
+#define MC_PHY_TIMING_D0__RXC1_EXT__SHIFT 0xc
+#define MC_PHY_TIMING_D0__TXC0_DLY_MASK 0x70000
+#define MC_PHY_TIMING_D0__TXC0_DLY__SHIFT 0x10
+#define MC_PHY_TIMING_D0__TXC0_EXT_MASK 0xf00000
+#define MC_PHY_TIMING_D0__TXC0_EXT__SHIFT 0x14
+#define MC_PHY_TIMING_D0__TXC1_DLY_MASK 0x7000000
+#define MC_PHY_TIMING_D0__TXC1_DLY__SHIFT 0x18
+#define MC_PHY_TIMING_D0__TXC1_EXT_MASK 0xf0000000
+#define MC_PHY_TIMING_D0__TXC1_EXT__SHIFT 0x1c
+#define MC_PHY_TIMING_D1__RXC0_DLY_MASK 0xf
+#define MC_PHY_TIMING_D1__RXC0_DLY__SHIFT 0x0
+#define MC_PHY_TIMING_D1__RXC0_EXT_MASK 0xf0
+#define MC_PHY_TIMING_D1__RXC0_EXT__SHIFT 0x4
+#define MC_PHY_TIMING_D1__RXC1_DLY_MASK 0xf00
+#define MC_PHY_TIMING_D1__RXC1_DLY__SHIFT 0x8
+#define MC_PHY_TIMING_D1__RXC1_EXT_MASK 0xf000
+#define MC_PHY_TIMING_D1__RXC1_EXT__SHIFT 0xc
+#define MC_PHY_TIMING_D1__TXC0_DLY_MASK 0x70000
+#define MC_PHY_TIMING_D1__TXC0_DLY__SHIFT 0x10
+#define MC_PHY_TIMING_D1__TXC0_EXT_MASK 0xf00000
+#define MC_PHY_TIMING_D1__TXC0_EXT__SHIFT 0x14
+#define MC_PHY_TIMING_D1__TXC1_DLY_MASK 0x7000000
+#define MC_PHY_TIMING_D1__TXC1_DLY__SHIFT 0x18
+#define MC_PHY_TIMING_D1__TXC1_EXT_MASK 0xf0000000
+#define MC_PHY_TIMING_D1__TXC1_EXT__SHIFT 0x1c
+#define MC_PHY_TIMING_2__IND_LD_CNT_MASK 0x7f
+#define MC_PHY_TIMING_2__IND_LD_CNT__SHIFT 0x0
+#define MC_PHY_TIMING_2__RXC0_INV_MASK 0x100
+#define MC_PHY_TIMING_2__RXC0_INV__SHIFT 0x8
+#define MC_PHY_TIMING_2__RXC1_INV_MASK 0x200
+#define MC_PHY_TIMING_2__RXC1_INV__SHIFT 0x9
+#define MC_PHY_TIMING_2__TXC0_INV_MASK 0x400
+#define MC_PHY_TIMING_2__TXC0_INV__SHIFT 0xa
+#define MC_PHY_TIMING_2__TXC1_INV_MASK 0x800
+#define MC_PHY_TIMING_2__TXC1_INV__SHIFT 0xb
+#define MC_PHY_TIMING_2__RXC0_FRC_MASK 0x1000
+#define MC_PHY_TIMING_2__RXC0_FRC__SHIFT 0xc
+#define MC_PHY_TIMING_2__RXC1_FRC_MASK 0x2000
+#define MC_PHY_TIMING_2__RXC1_FRC__SHIFT 0xd
+#define MC_PHY_TIMING_2__TXC0_FRC_MASK 0x4000
+#define MC_PHY_TIMING_2__TXC0_FRC__SHIFT 0xe
+#define MC_PHY_TIMING_2__TXC1_FRC_MASK 0x8000
+#define MC_PHY_TIMING_2__TXC1_FRC__SHIFT 0xf
+#define MC_PHY_TIMING_2__TX_CDREN_D0_MASK 0x10000
+#define MC_PHY_TIMING_2__TX_CDREN_D0__SHIFT 0x10
+#define MC_PHY_TIMING_2__TX_CDREN_D1_MASK 0x20000
+#define MC_PHY_TIMING_2__TX_CDREN_D1__SHIFT 0x11
+#define MC_PHY_TIMING_2__ADR_CLKEN_D0_MASK 0x40000
+#define MC_PHY_TIMING_2__ADR_CLKEN_D0__SHIFT 0x12
+#define MC_PHY_TIMING_2__ADR_CLKEN_D1_MASK 0x80000
+#define MC_PHY_TIMING_2__ADR_CLKEN_D1__SHIFT 0x13
+#define MC_PHY_TIMING_2__WR_DLY_MASK 0xf00000
+#define MC_PHY_TIMING_2__WR_DLY__SHIFT 0x14
+#define MC_PHY_TIMING_2__RXDPWRONC0_FRC_MASK 0x1000000
+#define MC_PHY_TIMING_2__RXDPWRONC0_FRC__SHIFT 0x18
+#define MC_PHY_TIMING_2__RXDPWRONC1_FRC_MASK 0x2000000
+#define MC_PHY_TIMING_2__RXDPWRONC1_FRC__SHIFT 0x19
+#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE_MASK 0x1
+#define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE__SHIFT 0x0
+#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE_MASK 0x2
+#define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE__SHIFT 0x1
+#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE_MASK 0x4
+#define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE__SHIFT 0x2
+#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE_MASK 0x8
+#define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE__SHIFT 0x3
+#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE_MASK 0x10
+#define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE__SHIFT 0x4
+#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE_MASK 0x20
+#define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE__SHIFT 0x5
+#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE_MASK 0x40
+#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE__SHIFT 0x6
+#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE_MASK 0x80
+#define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE__SHIFT 0x7
+#define MCLK_PWRMGT_CNTL__DLL_SPEED_MASK 0x1f
+#define MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT 0x0
+#define MCLK_PWRMGT_CNTL__DLL_READY_MASK 0x40
+#define MCLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x6
+#define MCLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x80
+#define MCLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x7
+#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK 0x100
+#define MCLK_PWRMGT_CNTL__MRDCK0_PDNB__SHIFT 0x8
+#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK 0x200
+#define MCLK_PWRMGT_CNTL__MRDCK1_PDNB__SHIFT 0x9
+#define MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK 0x10000
+#define MCLK_PWRMGT_CNTL__MRDCK0_RESET__SHIFT 0x10
+#define MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK 0x20000
+#define MCLK_PWRMGT_CNTL__MRDCK1_RESET__SHIFT 0x11
+#define MCLK_PWRMGT_CNTL__DLL_READY_READ_MASK 0x1000000
+#define MCLK_PWRMGT_CNTL__DLL_READY_READ__SHIFT 0x18
+#define DLL_CNTL__DLL_RESET_TIME_MASK 0x3ff
+#define DLL_CNTL__DLL_RESET_TIME__SHIFT 0x0
+#define DLL_CNTL__DLL_LOCK_TIME_MASK 0x3ff000
+#define DLL_CNTL__DLL_LOCK_TIME__SHIFT 0xc
+#define DLL_CNTL__MRDCK0_BYPASS_MASK 0x1000000
+#define DLL_CNTL__MRDCK0_BYPASS__SHIFT 0x18
+#define DLL_CNTL__MRDCK1_BYPASS_MASK 0x2000000
+#define DLL_CNTL__MRDCK1_BYPASS__SHIFT 0x19
+#define DLL_CNTL__PWR2_MODE_MASK 0x4000000
+#define DLL_CNTL__PWR2_MODE__SHIFT 0x1a
+#define MPLL_SEQ_UCODE_1__INSTR0_MASK 0xf
+#define MPLL_SEQ_UCODE_1__INSTR0__SHIFT 0x0
+#define MPLL_SEQ_UCODE_1__INSTR1_MASK 0xf0
+#define MPLL_SEQ_UCODE_1__INSTR1__SHIFT 0x4
+#define MPLL_SEQ_UCODE_1__INSTR2_MASK 0xf00
+#define MPLL_SEQ_UCODE_1__INSTR2__SHIFT 0x8
+#define MPLL_SEQ_UCODE_1__INSTR3_MASK 0xf000
+#define MPLL_SEQ_UCODE_1__INSTR3__SHIFT 0xc
+#define MPLL_SEQ_UCODE_1__INSTR4_MASK 0xf0000
+#define MPLL_SEQ_UCODE_1__INSTR4__SHIFT 0x10
+#define MPLL_SEQ_UCODE_1__INSTR5_MASK 0xf00000
+#define MPLL_SEQ_UCODE_1__INSTR5__SHIFT 0x14
+#define MPLL_SEQ_UCODE_1__INSTR6_MASK 0xf000000
+#define MPLL_SEQ_UCODE_1__INSTR6__SHIFT 0x18
+#define MPLL_SEQ_UCODE_1__INSTR7_MASK 0xf0000000
+#define MPLL_SEQ_UCODE_1__INSTR7__SHIFT 0x1c
+#define MPLL_SEQ_UCODE_2__INSTR8_MASK 0xf
+#define MPLL_SEQ_UCODE_2__INSTR8__SHIFT 0x0
+#define MPLL_SEQ_UCODE_2__INSTR9_MASK 0xf0
+#define MPLL_SEQ_UCODE_2__INSTR9__SHIFT 0x4
+#define MPLL_SEQ_UCODE_2__INSTR10_MASK 0xf00
+#define MPLL_SEQ_UCODE_2__INSTR10__SHIFT 0x8
+#define MPLL_SEQ_UCODE_2__INSTR11_MASK 0xf000
+#define MPLL_SEQ_UCODE_2__INSTR11__SHIFT 0xc
+#define MPLL_SEQ_UCODE_2__INSTR12_MASK 0xf0000
+#define MPLL_SEQ_UCODE_2__INSTR12__SHIFT 0x10
+#define MPLL_SEQ_UCODE_2__INSTR13_MASK 0xf00000
+#define MPLL_SEQ_UCODE_2__INSTR13__SHIFT 0x14
+#define MPLL_SEQ_UCODE_2__INSTR14_MASK 0xf000000
+#define MPLL_SEQ_UCODE_2__INSTR14__SHIFT 0x18
+#define MPLL_SEQ_UCODE_2__INSTR15_MASK 0xf0000000
+#define MPLL_SEQ_UCODE_2__INSTR15__SHIFT 0x1c
+#define MPLL_CNTL_MODE__INSTR_DELAY_MASK 0xff
+#define MPLL_CNTL_MODE__INSTR_DELAY__SHIFT 0x0
+#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK 0x100
+#define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT 0x8
+#define MPLL_CNTL_MODE__GDDR_PWRON_OVR_MASK 0x200
+#define MPLL_CNTL_MODE__GDDR_PWRON_OVR__SHIFT 0x9
+#define MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK 0x800
+#define MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT 0xb
+#define MPLL_CNTL_MODE__SPARE_1_MASK 0x1000
+#define MPLL_CNTL_MODE__SPARE_1__SHIFT 0xc
+#define MPLL_CNTL_MODE__QDR_MASK 0x2000
+#define MPLL_CNTL_MODE__QDR__SHIFT 0xd
+#define MPLL_CNTL_MODE__MPLL_CTLREQ_MASK 0x4000
+#define MPLL_CNTL_MODE__MPLL_CTLREQ__SHIFT 0xe
+#define MPLL_CNTL_MODE__MPLL_CHG_STATUS_MASK 0x10000
+#define MPLL_CNTL_MODE__MPLL_CHG_STATUS__SHIFT 0x10
+#define MPLL_CNTL_MODE__FORCE_TESTMODE_MASK 0x20000
+#define MPLL_CNTL_MODE__FORCE_TESTMODE__SHIFT 0x11
+#define MPLL_CNTL_MODE__FAST_LOCK_EN_MASK 0x100000
+#define MPLL_CNTL_MODE__FAST_LOCK_EN__SHIFT 0x14
+#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL_MASK 0x600000
+#define MPLL_CNTL_MODE__FAST_LOCK_CNTRL__SHIFT 0x15
+#define MPLL_CNTL_MODE__SPARE_2_MASK 0x800000
+#define MPLL_CNTL_MODE__SPARE_2__SHIFT 0x17
+#define MPLL_CNTL_MODE__SS_SSEN_MASK 0x3000000
+#define MPLL_CNTL_MODE__SS_SSEN__SHIFT 0x18
+#define MPLL_CNTL_MODE__SS_DSMODE_EN_MASK 0x4000000
+#define MPLL_CNTL_MODE__SS_DSMODE_EN__SHIFT 0x1a
+#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL_MASK 0x8000000
+#define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL__SHIFT 0x1b
+#define MPLL_CNTL_MODE__SPARE_3_MASK 0x70000000
+#define MPLL_CNTL_MODE__SPARE_3__SHIFT 0x1c
+#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET_MASK 0x80000000
+#define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET__SHIFT 0x1f
+#define MPLL_FUNC_CNTL__SPARE_0_MASK 0x20
+#define MPLL_FUNC_CNTL__SPARE_0__SHIFT 0x5
+#define MPLL_FUNC_CNTL__BG_100ADJ_MASK 0xf00
+#define MPLL_FUNC_CNTL__BG_100ADJ__SHIFT 0x8
+#define MPLL_FUNC_CNTL__BG_135ADJ_MASK 0xf0000
+#define MPLL_FUNC_CNTL__BG_135ADJ__SHIFT 0x10
+#define MPLL_FUNC_CNTL__BWCTRL_MASK 0xff00000
+#define MPLL_FUNC_CNTL__BWCTRL__SHIFT 0x14
+#define MPLL_FUNC_CNTL__REG_BIAS_MASK 0xc0000000
+#define MPLL_FUNC_CNTL__REG_BIAS__SHIFT 0x1e
+#define MPLL_FUNC_CNTL_1__VCO_MODE_MASK 0x3
+#define MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT 0x0
+#define MPLL_FUNC_CNTL_1__SPARE_0_MASK 0xc
+#define MPLL_FUNC_CNTL_1__SPARE_0__SHIFT 0x2
+#define MPLL_FUNC_CNTL_1__CLKFRAC_MASK 0xfff0
+#define MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT 0x4
+#define MPLL_FUNC_CNTL_1__CLKF_MASK 0xfff0000
+#define MPLL_FUNC_CNTL_1__CLKF__SHIFT 0x10
+#define MPLL_FUNC_CNTL_1__SPARE_1_MASK 0xf0000000
+#define MPLL_FUNC_CNTL_1__SPARE_1__SHIFT 0x1c
+#define MPLL_FUNC_CNTL_2__VCTRLADC_EN_MASK 0x1
+#define MPLL_FUNC_CNTL_2__VCTRLADC_EN__SHIFT 0x0
+#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN_MASK 0x2
+#define MPLL_FUNC_CNTL_2__TEST_VCTL_EN__SHIFT 0x1
+#define MPLL_FUNC_CNTL_2__RESET_EN_MASK 0x4
+#define MPLL_FUNC_CNTL_2__RESET_EN__SHIFT 0x2
+#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN_MASK 0x8
+#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN__SHIFT 0x3
+#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC_MASK 0x10
+#define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC__SHIFT 0x4
+#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS_MASK 0x20
+#define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS__SHIFT 0x5
+#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK_MASK 0x40
+#define MPLL_FUNC_CNTL_2__TEST_BYPMCLK__SHIFT 0x6
+#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR_MASK 0x80
+#define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR__SHIFT 0x7
+#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL_MASK 0x100
+#define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL__SHIFT 0x8
+#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS_MASK 0x200
+#define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS__SHIFT 0x9
+#define MPLL_FUNC_CNTL_2__RESET_TIMER_MASK 0xc00
+#define MPLL_FUNC_CNTL_2__RESET_TIMER__SHIFT 0xa
+#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL_MASK 0x3000
+#define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL__SHIFT 0xc
+#define MPLL_FUNC_CNTL_2__RISEFBVCO_EN_MASK 0x4000
+#define MPLL_FUNC_CNTL_2__RISEFBVCO_EN__SHIFT 0xe
+#define MPLL_FUNC_CNTL_2__PWRGOOD_OVR_MASK 0x8000
+#define MPLL_FUNC_CNTL_2__PWRGOOD_OVR__SHIFT 0xf
+#define MPLL_FUNC_CNTL_2__ISO_DIS_P_MASK 0x10000
+#define MPLL_FUNC_CNTL_2__ISO_DIS_P__SHIFT 0x10
+#define MPLL_FUNC_CNTL_2__BACKUP_2_MASK 0xe0000
+#define MPLL_FUNC_CNTL_2__BACKUP_2__SHIFT 0x11
+#define MPLL_FUNC_CNTL_2__LF_CNTRL_MASK 0x7f00000
+#define MPLL_FUNC_CNTL_2__LF_CNTRL__SHIFT 0x14
+#define MPLL_FUNC_CNTL_2__BACKUP_MASK 0xf8000000
+#define MPLL_FUNC_CNTL_2__BACKUP__SHIFT 0x1b
+#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK 0x7
+#define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x0
+#define MPLL_AD_FUNC_CNTL__SPARE_MASK 0xfffffff8
+#define MPLL_AD_FUNC_CNTL__SPARE__SHIFT 0x3
+#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV_MASK 0x7
+#define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x0
+#define MPLL_DQ_FUNC_CNTL__SPARE_0_MASK 0x8
+#define MPLL_DQ_FUNC_CNTL__SPARE_0__SHIFT 0x3
+#define MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK 0x10
+#define MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT 0x4
+#define MPLL_DQ_FUNC_CNTL__SPARE_MASK 0xffffffe0
+#define MPLL_DQ_FUNC_CNTL__SPARE__SHIFT 0x5
+#define MPLL_TIME__MPLL_LOCK_TIME_MASK 0xffff
+#define MPLL_TIME__MPLL_LOCK_TIME__SHIFT 0x0
+#define MPLL_TIME__MPLL_RESET_TIME_MASK 0xffff0000
+#define MPLL_TIME__MPLL_RESET_TIME__SHIFT 0x10
+#define MPLL_SS1__CLKV_MASK 0x3ffffff
+#define MPLL_SS1__CLKV__SHIFT 0x0
+#define MPLL_SS1__SPARE_MASK 0xfc000000
+#define MPLL_SS1__SPARE__SHIFT 0x1a
+#define MPLL_SS2__CLKS_MASK 0xfff
+#define MPLL_SS2__CLKS__SHIFT 0x0
+#define MPLL_SS2__SPARE_MASK 0xfffff000
+#define MPLL_SS2__SPARE__SHIFT 0xc
+#define MPLL_CONTROL__GDDR_PWRON_MASK 0x1
+#define MPLL_CONTROL__GDDR_PWRON__SHIFT 0x0
+#define MPLL_CONTROL__REFCLK_PWRON_MASK 0x2
+#define MPLL_CONTROL__REFCLK_PWRON__SHIFT 0x1
+#define MPLL_CONTROL__PLL_BUF_PWRON_TX_MASK 0x4
+#define MPLL_CONTROL__PLL_BUF_PWRON_TX__SHIFT 0x2
+#define MPLL_CONTROL__AD_BG_PWRON_MASK 0x1000
+#define MPLL_CONTROL__AD_BG_PWRON__SHIFT 0xc
+#define MPLL_CONTROL__AD_PLL_PWRON_MASK 0x2000
+#define MPLL_CONTROL__AD_PLL_PWRON__SHIFT 0xd
+#define MPLL_CONTROL__AD_PLL_RESET_MASK 0x4000
+#define MPLL_CONTROL__AD_PLL_RESET__SHIFT 0xe
+#define MPLL_CONTROL__SPARE_AD_0_MASK 0x8000
+#define MPLL_CONTROL__SPARE_AD_0__SHIFT 0xf
+#define MPLL_CONTROL__DQ_0_0_BG_PWRON_MASK 0x10000
+#define MPLL_CONTROL__DQ_0_0_BG_PWRON__SHIFT 0x10
+#define MPLL_CONTROL__DQ_0_0_PLL_PWRON_MASK 0x20000
+#define MPLL_CONTROL__DQ_0_0_PLL_PWRON__SHIFT 0x11
+#define MPLL_CONTROL__DQ_0_0_PLL_RESET_MASK 0x40000
+#define MPLL_CONTROL__DQ_0_0_PLL_RESET__SHIFT 0x12
+#define MPLL_CONTROL__SPARE_DQ_0_0_MASK 0x80000
+#define MPLL_CONTROL__SPARE_DQ_0_0__SHIFT 0x13
+#define MPLL_CONTROL__DQ_0_1_BG_PWRON_MASK 0x100000
+#define MPLL_CONTROL__DQ_0_1_BG_PWRON__SHIFT 0x14
+#define MPLL_CONTROL__DQ_0_1_PLL_PWRON_MASK 0x200000
+#define MPLL_CONTROL__DQ_0_1_PLL_PWRON__SHIFT 0x15
+#define MPLL_CONTROL__DQ_0_1_PLL_RESET_MASK 0x400000
+#define MPLL_CONTROL__DQ_0_1_PLL_RESET__SHIFT 0x16
+#define MPLL_CONTROL__SPARE_DQ_0_1_MASK 0x800000
+#define MPLL_CONTROL__SPARE_DQ_0_1__SHIFT 0x17
+#define MPLL_CONTROL__DQ_1_0_BG_PWRON_MASK 0x1000000
+#define MPLL_CONTROL__DQ_1_0_BG_PWRON__SHIFT 0x18
+#define MPLL_CONTROL__DQ_1_0_PLL_PWRON_MASK 0x2000000
+#define MPLL_CONTROL__DQ_1_0_PLL_PWRON__SHIFT 0x19
+#define MPLL_CONTROL__DQ_1_0_PLL_RESET_MASK 0x4000000
+#define MPLL_CONTROL__DQ_1_0_PLL_RESET__SHIFT 0x1a
+#define MPLL_CONTROL__SPARE_DQ_1_0_MASK 0x8000000
+#define MPLL_CONTROL__SPARE_DQ_1_0__SHIFT 0x1b
+#define MPLL_CONTROL__DQ_1_1_BG_PWRON_MASK 0x10000000
+#define MPLL_CONTROL__DQ_1_1_BG_PWRON__SHIFT 0x1c
+#define MPLL_CONTROL__DQ_1_1_PLL_PWRON_MASK 0x20000000
+#define MPLL_CONTROL__DQ_1_1_PLL_PWRON__SHIFT 0x1d
+#define MPLL_CONTROL__DQ_1_1_PLL_RESET_MASK 0x40000000
+#define MPLL_CONTROL__DQ_1_1_PLL_RESET__SHIFT 0x1e
+#define MPLL_CONTROL__SPARE_DQ_1_1_MASK 0x80000000
+#define MPLL_CONTROL__SPARE_DQ_1_1__SHIFT 0x1f
+#define MPLL_AD_STATUS__VCTRLADC_MASK 0x7
+#define MPLL_AD_STATUS__VCTRLADC__SHIFT 0x0
+#define MPLL_AD_STATUS__TEST_FBDIV_FRAC_MASK 0x70
+#define MPLL_AD_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
+#define MPLL_AD_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
+#define MPLL_AD_STATUS__TEST_FBDIV_INT__SHIFT 0x7
+#define MPLL_AD_STATUS__OINT_RESET_MASK 0x20000
+#define MPLL_AD_STATUS__OINT_RESET__SHIFT 0x11
+#define MPLL_AD_STATUS__FREQ_LOCK_MASK 0x40000
+#define MPLL_AD_STATUS__FREQ_LOCK__SHIFT 0x12
+#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
+#define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
+#define MPLL_DQ_0_0_STATUS__VCTRLADC_MASK 0x7
+#define MPLL_DQ_0_0_STATUS__VCTRLADC__SHIFT 0x0
+#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC_MASK 0x70
+#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
+#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
+#define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT__SHIFT 0x7
+#define MPLL_DQ_0_0_STATUS__OINT_RESET_MASK 0x20000
+#define MPLL_DQ_0_0_STATUS__OINT_RESET__SHIFT 0x11
+#define MPLL_DQ_0_0_STATUS__FREQ_LOCK_MASK 0x40000
+#define MPLL_DQ_0_0_STATUS__FREQ_LOCK__SHIFT 0x12
+#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
+#define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
+#define MPLL_DQ_0_1_STATUS__VCTRLADC_MASK 0x7
+#define MPLL_DQ_0_1_STATUS__VCTRLADC__SHIFT 0x0
+#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC_MASK 0x70
+#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
+#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
+#define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT__SHIFT 0x7
+#define MPLL_DQ_0_1_STATUS__OINT_RESET_MASK 0x20000
+#define MPLL_DQ_0_1_STATUS__OINT_RESET__SHIFT 0x11
+#define MPLL_DQ_0_1_STATUS__FREQ_LOCK_MASK 0x40000
+#define MPLL_DQ_0_1_STATUS__FREQ_LOCK__SHIFT 0x12
+#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
+#define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
+#define MPLL_DQ_1_0_STATUS__VCTRLADC_MASK 0x7
+#define MPLL_DQ_1_0_STATUS__VCTRLADC__SHIFT 0x0
+#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC_MASK 0x70
+#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
+#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
+#define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT__SHIFT 0x7
+#define MPLL_DQ_1_0_STATUS__OINT_RESET_MASK 0x20000
+#define MPLL_DQ_1_0_STATUS__OINT_RESET__SHIFT 0x11
+#define MPLL_DQ_1_0_STATUS__FREQ_LOCK_MASK 0x40000
+#define MPLL_DQ_1_0_STATUS__FREQ_LOCK__SHIFT 0x12
+#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
+#define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
+#define MPLL_DQ_1_1_STATUS__VCTRLADC_MASK 0x7
+#define MPLL_DQ_1_1_STATUS__VCTRLADC__SHIFT 0x0
+#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC_MASK 0x70
+#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
+#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
+#define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT__SHIFT 0x7
+#define MPLL_DQ_1_1_STATUS__OINT_RESET_MASK 0x20000
+#define MPLL_DQ_1_1_STATUS__OINT_RESET__SHIFT 0x11
+#define MPLL_DQ_1_1_STATUS__FREQ_LOCK_MASK 0x40000
+#define MPLL_DQ_1_1_STATUS__FREQ_LOCK__SHIFT 0x12
+#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
+#define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
+#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN_MASK 0x1
+#define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN__SHIFT 0x0
+#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN_MASK 0x2
+#define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN__SHIFT 0x1
+#define MC_SEQ_PMG_PG_HWCNTL__TPGCG_MASK 0x3c
+#define MC_SEQ_PMG_PG_HWCNTL__TPGCG__SHIFT 0x2
+#define MC_SEQ_PMG_PG_HWCNTL__D_DLY_MASK 0xc0
+#define MC_SEQ_PMG_PG_HWCNTL__D_DLY__SHIFT 0x6
+#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY_MASK 0x300
+#define MC_SEQ_PMG_PG_HWCNTL__AC_DLY__SHIFT 0x8
+#define MC_SEQ_PMG_PG_HWCNTL__G_DLY_MASK 0x3c00
+#define MC_SEQ_PMG_PG_HWCNTL__G_DLY__SHIFT 0xa
+#define MC_SEQ_PMG_PG_HWCNTL__TXAO_MASK 0x10000
+#define MC_SEQ_PMG_PG_HWCNTL__TXAO__SHIFT 0x10
+#define MC_SEQ_PMG_PG_HWCNTL__RXAO_MASK 0x20000
+#define MC_SEQ_PMG_PG_HWCNTL__RXAO__SHIFT 0x11
+#define MC_SEQ_PMG_PG_HWCNTL__ACAO_MASK 0x40000
+#define MC_SEQ_PMG_PG_HWCNTL__ACAO__SHIFT 0x12
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB_MASK 0x1
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB__SHIFT 0x0
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB_MASK 0x2
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB__SHIFT 0x1
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB_MASK 0x4
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB__SHIFT 0x2
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB_MASK 0x8
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB__SHIFT 0x3
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB_MASK 0x10
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB__SHIFT 0x4
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB_MASK 0x20
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB__SHIFT 0x5
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB_MASK 0x40
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB__SHIFT 0x6
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB_MASK 0x80
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB__SHIFT 0x7
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB_MASK 0x100
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB__SHIFT 0x8
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB_MASK 0x200
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB__SHIFT 0x9
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB_MASK 0x400
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB__SHIFT 0xa
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB_MASK 0x800
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB__SHIFT 0xb
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB_MASK 0x1000
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB__SHIFT 0xc
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB_MASK 0x2000
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB__SHIFT 0xd
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB_MASK 0x4000
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB__SHIFT 0xe
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB_MASK 0x8000
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB__SHIFT 0xf
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB_MASK 0x10000
+#define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB__SHIFT 0x10
+#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT_MASK 0x80000000
+#define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT__SHIFT 0x1f
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB_MASK 0x1
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB__SHIFT 0x0
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB_MASK 0x2
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB__SHIFT 0x1
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB_MASK 0x4
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB__SHIFT 0x2
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB_MASK 0x8
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB__SHIFT 0x3
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB_MASK 0x10
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB__SHIFT 0x4
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB_MASK 0x20
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB__SHIFT 0x5
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB_MASK 0x40
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB__SHIFT 0x6
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB_MASK 0x80
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB__SHIFT 0x7
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB_MASK 0x100
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB__SHIFT 0x8
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB_MASK 0x200
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB__SHIFT 0x9
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB_MASK 0x400
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB__SHIFT 0xa
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB_MASK 0x800
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB__SHIFT 0xb
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB_MASK 0x1000
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB__SHIFT 0xc
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB_MASK 0x2000
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB__SHIFT 0xd
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB_MASK 0x4000
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB__SHIFT 0xe
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB_MASK 0x8000
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB__SHIFT 0xf
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB_MASK 0x10000
+#define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB__SHIFT 0x10
+#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT_MASK 0x80000000
+#define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT__SHIFT 0x1f
+#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX_MASK 0x1f
+#define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX__SHIFT 0x0
+#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA_MASK 0xffffffff
+#define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA__SHIFT 0x0
+#define MC_TSM_DEBUG_GCNT__DATA_MASK 0xffffffff
+#define MC_TSM_DEBUG_GCNT__DATA__SHIFT 0x0
+#define MC_TSM_DEBUG_FLAG__DATA_MASK 0xffffffff
+#define MC_TSM_DEBUG_FLAG__DATA__SHIFT 0x0
+#define MC_TSM_DEBUG_MISC__FLAG_MASK 0xff
+#define MC_TSM_DEBUG_MISC__FLAG__SHIFT 0x0
+#define MC_TSM_DEBUG_MISC__NCNT_RD_MASK 0xf00
+#define MC_TSM_DEBUG_MISC__NCNT_RD__SHIFT 0x8
+#define MC_TSM_DEBUG_MISC__NCNT_WR_MASK 0xf000
+#define MC_TSM_DEBUG_MISC__NCNT_WR__SHIFT 0xc
+#define MC_TSM_DEBUG_BCNT0__BYTE0_MASK 0xff
+#define MC_TSM_DEBUG_BCNT0__BYTE0__SHIFT 0x0
+#define MC_TSM_DEBUG_BCNT0__BYTE1_MASK 0xff00
+#define MC_TSM_DEBUG_BCNT0__BYTE1__SHIFT 0x8
+#define MC_TSM_DEBUG_BCNT0__BYTE2_MASK 0xff0000
+#define MC_TSM_DEBUG_BCNT0__BYTE2__SHIFT 0x10
+#define MC_TSM_DEBUG_BCNT0__BYTE3_MASK 0xff000000
+#define MC_TSM_DEBUG_BCNT0__BYTE3__SHIFT 0x18
+#define MC_TSM_DEBUG_BCNT1__BYTE0_MASK 0xff
+#define MC_TSM_DEBUG_BCNT1__BYTE0__SHIFT 0x0
+#define MC_TSM_DEBUG_BCNT1__BYTE1_MASK 0xff00
+#define MC_TSM_DEBUG_BCNT1__BYTE1__SHIFT 0x8
+#define MC_TSM_DEBUG_BCNT1__BYTE2_MASK 0xff0000
+#define MC_TSM_DEBUG_BCNT1__BYTE2__SHIFT 0x10
+#define MC_TSM_DEBUG_BCNT1__BYTE3_MASK 0xff000000
+#define MC_TSM_DEBUG_BCNT1__BYTE3__SHIFT 0x18
+#define MC_TSM_DEBUG_BCNT2__BYTE0_MASK 0xff
+#define MC_TSM_DEBUG_BCNT2__BYTE0__SHIFT 0x0
+#define MC_TSM_DEBUG_BCNT2__BYTE1_MASK 0xff00
+#define MC_TSM_DEBUG_BCNT2__BYTE1__SHIFT 0x8
+#define MC_TSM_DEBUG_BCNT2__BYTE2_MASK 0xff0000
+#define MC_TSM_DEBUG_BCNT2__BYTE2__SHIFT 0x10
+#define MC_TSM_DEBUG_BCNT2__BYTE3_MASK 0xff000000
+#define MC_TSM_DEBUG_BCNT2__BYTE3__SHIFT 0x18
+#define MC_TSM_DEBUG_BCNT3__BYTE0_MASK 0xff
+#define MC_TSM_DEBUG_BCNT3__BYTE0__SHIFT 0x0
+#define MC_TSM_DEBUG_BCNT3__BYTE1_MASK 0xff00
+#define MC_TSM_DEBUG_BCNT3__BYTE1__SHIFT 0x8
+#define MC_TSM_DEBUG_BCNT3__BYTE2_MASK 0xff0000
+#define MC_TSM_DEBUG_BCNT3__BYTE2__SHIFT 0x10
+#define MC_TSM_DEBUG_BCNT3__BYTE3_MASK 0xff000000
+#define MC_TSM_DEBUG_BCNT3__BYTE3__SHIFT 0x18
+#define MC_TSM_DEBUG_BCNT4__BYTE0_MASK 0xff
+#define MC_TSM_DEBUG_BCNT4__BYTE0__SHIFT 0x0
+#define MC_TSM_DEBUG_BCNT4__BYTE1_MASK 0xff00
+#define MC_TSM_DEBUG_BCNT4__BYTE1__SHIFT 0x8
+#define MC_TSM_DEBUG_BCNT4__BYTE2_MASK 0xff0000
+#define MC_TSM_DEBUG_BCNT4__BYTE2__SHIFT 0x10
+#define MC_TSM_DEBUG_BCNT4__BYTE3_MASK 0xff000000
+#define MC_TSM_DEBUG_BCNT4__BYTE3__SHIFT 0x18
+#define MC_TSM_DEBUG_BCNT5__BYTE0_MASK 0xff
+#define MC_TSM_DEBUG_BCNT5__BYTE0__SHIFT 0x0
+#define MC_TSM_DEBUG_BCNT5__BYTE1_MASK 0xff00
+#define MC_TSM_DEBUG_BCNT5__BYTE1__SHIFT 0x8
+#define MC_TSM_DEBUG_BCNT5__BYTE2_MASK 0xff0000
+#define MC_TSM_DEBUG_BCNT5__BYTE2__SHIFT 0x10
+#define MC_TSM_DEBUG_BCNT5__BYTE3_MASK 0xff000000
+#define MC_TSM_DEBUG_BCNT5__BYTE3__SHIFT 0x18
+#define MC_TSM_DEBUG_BCNT6__BYTE0_MASK 0xff
+#define MC_TSM_DEBUG_BCNT6__BYTE0__SHIFT 0x0
+#define MC_TSM_DEBUG_BCNT6__BYTE1_MASK 0xff00
+#define MC_TSM_DEBUG_BCNT6__BYTE1__SHIFT 0x8
+#define MC_TSM_DEBUG_BCNT6__BYTE2_MASK 0xff0000
+#define MC_TSM_DEBUG_BCNT6__BYTE2__SHIFT 0x10
+#define MC_TSM_DEBUG_BCNT6__BYTE3_MASK 0xff000000
+#define MC_TSM_DEBUG_BCNT6__BYTE3__SHIFT 0x18
+#define MC_TSM_DEBUG_BCNT7__BYTE0_MASK 0xff
+#define MC_TSM_DEBUG_BCNT7__BYTE0__SHIFT 0x0
+#define MC_TSM_DEBUG_BCNT7__BYTE1_MASK 0xff00
+#define MC_TSM_DEBUG_BCNT7__BYTE1__SHIFT 0x8
+#define MC_TSM_DEBUG_BCNT7__BYTE2_MASK 0xff0000
+#define MC_TSM_DEBUG_BCNT7__BYTE2__SHIFT 0x10
+#define MC_TSM_DEBUG_BCNT7__BYTE3_MASK 0xff000000
+#define MC_TSM_DEBUG_BCNT7__BYTE3__SHIFT 0x18
+#define MC_TSM_DEBUG_BCNT8__BYTE0_MASK 0xff
+#define MC_TSM_DEBUG_BCNT8__BYTE0__SHIFT 0x0
+#define MC_TSM_DEBUG_BCNT8__BYTE1_MASK 0xff00
+#define MC_TSM_DEBUG_BCNT8__BYTE1__SHIFT 0x8
+#define MC_TSM_DEBUG_BCNT8__BYTE2_MASK 0xff0000
+#define MC_TSM_DEBUG_BCNT8__BYTE2__SHIFT 0x10
+#define MC_TSM_DEBUG_BCNT8__BYTE3_MASK 0xff000000
+#define MC_TSM_DEBUG_BCNT8__BYTE3__SHIFT 0x18
+#define MC_TSM_DEBUG_BCNT9__BYTE0_MASK 0xff
+#define MC_TSM_DEBUG_BCNT9__BYTE0__SHIFT 0x0
+#define MC_TSM_DEBUG_BCNT9__BYTE1_MASK 0xff00
+#define MC_TSM_DEBUG_BCNT9__BYTE1__SHIFT 0x8
+#define MC_TSM_DEBUG_BCNT9__BYTE2_MASK 0xff0000
+#define MC_TSM_DEBUG_BCNT9__BYTE2__SHIFT 0x10
+#define MC_TSM_DEBUG_BCNT9__BYTE3_MASK 0xff000000
+#define MC_TSM_DEBUG_BCNT9__BYTE3__SHIFT 0x18
+#define MC_TSM_DEBUG_BCNT10__BYTE0_MASK 0xff
+#define MC_TSM_DEBUG_BCNT10__BYTE0__SHIFT 0x0
+#define MC_TSM_DEBUG_BCNT10__BYTE1_MASK 0xff00
+#define MC_TSM_DEBUG_BCNT10__BYTE1__SHIFT 0x8
+#define MC_TSM_DEBUG_BCNT10__BYTE2_MASK 0xff0000
+#define MC_TSM_DEBUG_BCNT10__BYTE2__SHIFT 0x10
+#define MC_TSM_DEBUG_BCNT10__BYTE3_MASK 0xff000000
+#define MC_TSM_DEBUG_BCNT10__BYTE3__SHIFT 0x18
+#define MC_TSM_DEBUG_ST01__DATA_MASK 0xffffffff
+#define MC_TSM_DEBUG_ST01__DATA__SHIFT 0x0
+#define MC_TSM_DEBUG_ST23__DATA_MASK 0xffffffff
+#define MC_TSM_DEBUG_ST23__DATA__SHIFT 0x0
+#define MC_TSM_DEBUG_ST45__DATA_MASK 0xffffffff
+#define MC_TSM_DEBUG_ST45__DATA__SHIFT 0x0
+#define MC_TSM_DEBUG_BKPT__DATA_MASK 0xffffffff
+#define MC_TSM_DEBUG_BKPT__DATA__SHIFT 0x0
+#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX_MASK 0x1ff
+#define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX__SHIFT 0x0
+#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA_MASK 0xffffffff
+#define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA__SHIFT 0x0
+#define MC_IO_DEBUG_UP_0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_2__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_2__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_2__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_2__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_2__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_2__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_2__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_2__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_3__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_3__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_3__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_3__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_3__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_3__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_3__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_3__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_4__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_4__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_4__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_4__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_4__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_4__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_4__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_4__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_5__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_5__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_5__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_5__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_5__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_5__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_5__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_5__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_6__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_6__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_6__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_6__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_6__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_6__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_6__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_6__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_7__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_7__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_7__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_7__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_7__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_7__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_7__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_7__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_8__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_8__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_8__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_8__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_8__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_8__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_8__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_8__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_9__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_9__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_9__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_9__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_9__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_9__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_9__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_9__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_10__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_10__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_10__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_10__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_10__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_10__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_10__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_10__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_11__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_11__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_11__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_11__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_11__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_11__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_11__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_11__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_12__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_12__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_12__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_12__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_12__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_12__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_12__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_12__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_13__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_13__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_13__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_13__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_13__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_13__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_13__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_13__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_14__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_14__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_14__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_14__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_14__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_14__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_14__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_14__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_15__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_15__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_15__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_15__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_15__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_15__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_15__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_15__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_16__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_16__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_16__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_16__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_16__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_16__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_16__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_16__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_17__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_17__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_17__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_17__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_17__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_17__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_17__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_17__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_18__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_18__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_18__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_18__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_18__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_18__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_18__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_18__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_19__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_19__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_19__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_19__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_19__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_19__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_19__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_19__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_20__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_20__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_20__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_20__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_20__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_20__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_20__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_20__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_21__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_21__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_21__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_21__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_21__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_21__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_21__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_21__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_22__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_22__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_22__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_22__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_22__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_22__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_22__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_22__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_23__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_23__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_23__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_23__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_23__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_23__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_23__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_23__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_24__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_24__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_24__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_24__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_24__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_24__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_24__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_24__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_25__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_25__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_25__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_25__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_25__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_25__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_25__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_25__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_26__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_26__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_26__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_26__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_26__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_26__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_26__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_26__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_27__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_27__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_27__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_27__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_27__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_27__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_27__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_27__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_28__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_28__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_28__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_28__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_28__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_28__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_28__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_28__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_29__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_29__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_29__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_29__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_29__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_29__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_29__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_29__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_30__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_30__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_30__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_30__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_30__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_30__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_30__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_30__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_31__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_31__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_31__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_31__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_31__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_31__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_31__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_31__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_32__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_32__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_32__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_32__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_32__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_32__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_32__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_32__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_33__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_33__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_33__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_33__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_33__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_33__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_33__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_33__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_34__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_34__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_34__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_34__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_34__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_34__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_34__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_34__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_35__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_35__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_35__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_35__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_35__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_35__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_35__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_35__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_36__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_36__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_36__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_36__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_36__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_36__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_36__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_36__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_37__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_37__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_37__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_37__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_37__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_37__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_37__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_37__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_38__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_38__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_38__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_38__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_38__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_38__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_38__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_38__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_39__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_39__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_39__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_39__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_39__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_39__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_39__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_39__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_40__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_40__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_40__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_40__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_40__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_40__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_40__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_40__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_41__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_41__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_41__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_41__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_41__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_41__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_41__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_41__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_42__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_42__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_42__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_42__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_42__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_42__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_42__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_42__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_43__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_43__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_43__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_43__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_43__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_43__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_43__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_43__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_44__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_44__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_44__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_44__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_44__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_44__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_44__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_44__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_45__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_45__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_45__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_45__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_45__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_45__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_45__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_45__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_46__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_46__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_46__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_46__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_46__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_46__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_46__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_46__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_47__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_47__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_47__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_47__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_47__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_47__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_47__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_47__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_48__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_48__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_48__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_48__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_48__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_48__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_48__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_48__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_49__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_49__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_49__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_49__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_49__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_49__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_49__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_49__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_50__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_50__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_50__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_50__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_50__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_50__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_50__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_50__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_51__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_51__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_51__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_51__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_51__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_51__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_51__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_51__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_52__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_52__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_52__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_52__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_52__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_52__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_52__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_52__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_53__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_53__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_53__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_53__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_53__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_53__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_53__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_53__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_54__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_54__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_54__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_54__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_54__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_54__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_54__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_54__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_55__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_55__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_55__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_55__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_55__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_55__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_55__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_55__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_56__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_56__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_56__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_56__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_56__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_56__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_56__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_56__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_57__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_57__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_57__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_57__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_57__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_57__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_57__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_57__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_58__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_58__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_58__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_58__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_58__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_58__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_58__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_58__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_59__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_59__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_59__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_59__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_59__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_59__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_59__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_59__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_60__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_60__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_60__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_60__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_60__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_60__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_60__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_60__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_61__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_61__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_61__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_61__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_61__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_61__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_61__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_61__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_62__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_62__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_62__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_62__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_62__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_62__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_62__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_62__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_63__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_63__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_63__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_63__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_63__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_63__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_63__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_63__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_64__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_64__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_64__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_64__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_64__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_64__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_64__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_64__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_65__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_65__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_65__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_65__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_65__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_65__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_65__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_65__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_66__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_66__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_66__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_66__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_66__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_66__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_66__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_66__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_67__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_67__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_67__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_67__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_67__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_67__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_67__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_67__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_68__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_68__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_68__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_68__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_68__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_68__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_68__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_68__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_69__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_69__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_69__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_69__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_69__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_69__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_69__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_69__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_70__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_70__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_70__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_70__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_70__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_70__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_70__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_70__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_71__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_71__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_71__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_71__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_71__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_71__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_71__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_71__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_72__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_72__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_72__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_72__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_72__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_72__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_72__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_72__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_73__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_73__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_73__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_73__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_73__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_73__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_73__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_73__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_74__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_74__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_74__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_74__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_74__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_74__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_74__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_74__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_75__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_75__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_75__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_75__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_75__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_75__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_75__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_75__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_76__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_76__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_76__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_76__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_76__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_76__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_76__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_76__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_77__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_77__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_77__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_77__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_77__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_77__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_77__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_77__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_78__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_78__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_78__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_78__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_78__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_78__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_78__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_78__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_79__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_79__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_79__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_79__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_79__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_79__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_79__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_79__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_80__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_80__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_80__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_80__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_80__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_80__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_80__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_80__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_81__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_81__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_81__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_81__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_81__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_81__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_81__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_81__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_82__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_82__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_82__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_82__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_82__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_82__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_82__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_82__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_83__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_83__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_83__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_83__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_83__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_83__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_83__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_83__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_84__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_84__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_84__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_84__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_84__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_84__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_84__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_84__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_85__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_85__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_85__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_85__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_85__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_85__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_85__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_85__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_86__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_86__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_86__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_86__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_86__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_86__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_86__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_86__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_87__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_87__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_87__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_87__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_87__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_87__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_87__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_87__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_88__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_88__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_88__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_88__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_88__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_88__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_88__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_88__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_89__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_89__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_89__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_89__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_89__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_89__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_89__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_89__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_90__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_90__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_90__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_90__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_90__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_90__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_90__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_90__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_91__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_91__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_91__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_91__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_91__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_91__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_91__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_91__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_92__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_92__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_92__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_92__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_92__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_92__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_92__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_92__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_93__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_93__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_93__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_93__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_93__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_93__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_93__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_93__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_94__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_94__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_94__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_94__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_94__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_94__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_94__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_94__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_95__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_95__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_95__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_95__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_95__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_95__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_95__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_95__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_96__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_96__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_96__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_96__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_96__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_96__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_96__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_96__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_97__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_97__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_97__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_97__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_97__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_97__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_97__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_97__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_98__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_98__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_98__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_98__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_98__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_98__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_98__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_98__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_99__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_99__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_99__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_99__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_99__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_99__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_99__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_99__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_100__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_100__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_100__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_100__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_100__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_100__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_100__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_100__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_101__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_101__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_101__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_101__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_101__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_101__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_101__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_101__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_102__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_102__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_102__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_102__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_102__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_102__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_102__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_102__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_103__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_103__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_103__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_103__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_103__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_103__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_103__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_103__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_104__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_104__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_104__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_104__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_104__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_104__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_104__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_104__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_105__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_105__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_105__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_105__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_105__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_105__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_105__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_105__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_106__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_106__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_106__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_106__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_106__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_106__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_106__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_106__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_107__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_107__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_107__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_107__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_107__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_107__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_107__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_107__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_108__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_108__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_108__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_108__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_108__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_108__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_108__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_108__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_109__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_109__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_109__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_109__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_109__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_109__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_109__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_109__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_110__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_110__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_110__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_110__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_110__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_110__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_110__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_110__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_111__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_111__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_111__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_111__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_111__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_111__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_111__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_111__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_112__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_112__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_112__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_112__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_112__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_112__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_112__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_112__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_113__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_113__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_113__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_113__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_113__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_113__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_113__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_113__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_114__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_114__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_114__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_114__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_114__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_114__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_114__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_114__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_115__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_115__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_115__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_115__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_115__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_115__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_115__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_115__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_116__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_116__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_116__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_116__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_116__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_116__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_116__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_116__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_117__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_117__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_117__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_117__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_117__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_117__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_117__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_117__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_118__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_118__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_118__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_118__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_118__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_118__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_118__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_118__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_119__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_119__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_119__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_119__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_119__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_119__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_119__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_119__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_120__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_120__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_120__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_120__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_120__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_120__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_120__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_120__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_121__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_121__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_121__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_121__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_121__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_121__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_121__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_121__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_122__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_122__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_122__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_122__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_122__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_122__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_122__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_122__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_123__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_123__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_123__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_123__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_123__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_123__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_123__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_123__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_124__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_124__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_124__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_124__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_124__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_124__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_124__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_124__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_125__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_125__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_125__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_125__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_125__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_125__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_125__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_125__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_126__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_126__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_126__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_126__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_126__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_126__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_126__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_126__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_127__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_127__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_127__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_127__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_127__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_127__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_127__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_127__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_128__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_128__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_128__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_128__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_128__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_128__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_128__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_128__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_129__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_129__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_129__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_129__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_129__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_129__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_129__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_129__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_130__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_130__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_130__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_130__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_130__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_130__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_130__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_130__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_131__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_131__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_131__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_131__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_131__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_131__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_131__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_131__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_132__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_132__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_132__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_132__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_132__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_132__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_132__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_132__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_133__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_133__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_133__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_133__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_133__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_133__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_133__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_133__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_134__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_134__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_134__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_134__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_134__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_134__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_134__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_134__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_135__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_135__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_135__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_135__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_135__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_135__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_135__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_135__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_136__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_136__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_136__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_136__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_136__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_136__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_136__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_136__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_137__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_137__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_137__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_137__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_137__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_137__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_137__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_137__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_138__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_138__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_138__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_138__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_138__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_138__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_138__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_138__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_139__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_139__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_139__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_139__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_139__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_139__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_139__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_139__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_140__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_140__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_140__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_140__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_140__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_140__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_140__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_140__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_141__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_141__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_141__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_141__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_141__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_141__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_141__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_141__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_142__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_142__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_142__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_142__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_142__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_142__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_142__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_142__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_143__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_143__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_143__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_143__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_143__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_143__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_143__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_143__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_144__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_144__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_144__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_144__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_144__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_144__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_144__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_144__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_145__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_145__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_145__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_145__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_145__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_145__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_145__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_145__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_146__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_146__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_146__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_146__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_146__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_146__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_146__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_146__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_147__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_147__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_147__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_147__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_147__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_147__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_147__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_147__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_148__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_148__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_148__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_148__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_148__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_148__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_148__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_148__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_149__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_149__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_149__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_149__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_149__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_149__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_149__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_149__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_150__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_150__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_150__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_150__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_150__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_150__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_150__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_150__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_151__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_151__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_151__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_151__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_151__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_151__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_151__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_151__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_152__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_152__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_152__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_152__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_152__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_152__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_152__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_152__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_153__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_153__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_153__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_153__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_153__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_153__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_153__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_153__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_154__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_154__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_154__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_154__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_154__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_154__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_154__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_154__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_155__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_155__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_155__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_155__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_155__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_155__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_155__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_155__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_156__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_156__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_156__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_156__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_156__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_156__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_156__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_156__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_157__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_157__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_157__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_157__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_157__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_157__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_157__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_157__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_158__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_158__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_158__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_158__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_158__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_158__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_158__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_158__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_UP_159__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_UP_159__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_UP_159__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_UP_159__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_UP_159__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_UP_159__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_UP_159__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_UP_159__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0_MASK 0xff
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1_MASK 0xff00
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
+#define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
+#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D0_MASK 0x7
+#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D0__SHIFT 0x0
+#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D0_MASK 0x38
+#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D0__SHIFT 0x3
+#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D1_MASK 0x1c0
+#define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D1__SHIFT 0x6
+#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D1_MASK 0xe00
+#define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D1__SHIFT 0x9
+#define MC_SEQ_CNTL_3__REPCG_EN_D0_MASK 0x1000
+#define MC_SEQ_CNTL_3__REPCG_EN_D0__SHIFT 0xc
+#define MC_SEQ_CNTL_3__REPCG_EN_D1_MASK 0x2000
+#define MC_SEQ_CNTL_3__REPCG_EN_D1__SHIFT 0xd
+#define MC_SEQ_CNTL_3__REPCG_OFF_DLY_MASK 0xf0000
+#define MC_SEQ_CNTL_3__REPCG_OFF_DLY__SHIFT 0x10
+#define MC_SEQ_CNTL_3__FCK_FRC_MASK 0x100000
+#define MC_SEQ_CNTL_3__FCK_FRC__SHIFT 0x14
+#define MC_SEQ_CNTL_3__DBI_FRC_MASK 0x200000
+#define MC_SEQ_CNTL_3__DBI_FRC__SHIFT 0x15
+#define MC_SEQ_CNTL_3__PRGRM_CDC_MASK 0x400000
+#define MC_SEQ_CNTL_3__PRGRM_CDC__SHIFT 0x16
+#define MC_SEQ_CNTL_3__DQS_FRC_MASK 0x800000
+#define MC_SEQ_CNTL_3__DQS_FRC__SHIFT 0x17
+#define MC_SEQ_CNTL_3__DQS_FRC_PAT_MASK 0xf000000
+#define MC_SEQ_CNTL_3__DQS_FRC_PAT__SHIFT 0x18
+#define MC_SEQ_CNTL_3__IDSC_EN_MASK 0x40000000
+#define MC_SEQ_CNTL_3__IDSC_EN__SHIFT 0x1e
+#define MC_SEQ_CNTL_3__CAC_EN_MASK 0x80000000
+#define MC_SEQ_CNTL_3__CAC_EN__SHIFT 0x1f
+#define MC_SEQ_G5PDX_CTRL__CH0_ENABLE_MASK 0x1
+#define MC_SEQ_G5PDX_CTRL__CH0_ENABLE__SHIFT 0x0
+#define MC_SEQ_G5PDX_CTRL__CH1_ENABLE_MASK 0x2
+#define MC_SEQ_G5PDX_CTRL__CH1_ENABLE__SHIFT 0x1
+#define MC_SEQ_G5PDX_CTRL__WCKOFF_EARLY_MASK 0x4
+#define MC_SEQ_G5PDX_CTRL__WCKOFF_EARLY__SHIFT 0x2
+#define MC_SEQ_G5PDX_CTRL__WCKOFF_LATE_MASK 0x8
+#define MC_SEQ_G5PDX_CTRL__WCKOFF_LATE__SHIFT 0x3
+#define MC_SEQ_G5PDX_CTRL__TPD2MRS_MASK 0x3f0
+#define MC_SEQ_G5PDX_CTRL__TPD2MRS__SHIFT 0x4
+#define MC_SEQ_G5PDX_CTRL__TMRS2WCK_MASK 0xf000
+#define MC_SEQ_G5PDX_CTRL__TMRS2WCK__SHIFT 0xc
+#define MC_SEQ_G5PDX_CTRL__TWCK2MRS_MASK 0xf0000
+#define MC_SEQ_G5PDX_CTRL__TWCK2MRS__SHIFT 0x10
+#define MC_SEQ_G5PDX_CTRL__TMRD_MASK 0xf00000
+#define MC_SEQ_G5PDX_CTRL__TMRD__SHIFT 0x14
+#define MC_SEQ_G5PDX_CTRL_LP__CH0_ENABLE_MASK 0x1
+#define MC_SEQ_G5PDX_CTRL_LP__CH0_ENABLE__SHIFT 0x0
+#define MC_SEQ_G5PDX_CTRL_LP__CH1_ENABLE_MASK 0x2
+#define MC_SEQ_G5PDX_CTRL_LP__CH1_ENABLE__SHIFT 0x1
+#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_EARLY_MASK 0x4
+#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_EARLY__SHIFT 0x2
+#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_LATE_MASK 0x8
+#define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_LATE__SHIFT 0x3
+#define MC_SEQ_G5PDX_CTRL_LP__TPD2MRS_MASK 0x3f0
+#define MC_SEQ_G5PDX_CTRL_LP__TPD2MRS__SHIFT 0x4
+#define MC_SEQ_G5PDX_CTRL_LP__TMRS2WCK_MASK 0xf000
+#define MC_SEQ_G5PDX_CTRL_LP__TMRS2WCK__SHIFT 0xc
+#define MC_SEQ_G5PDX_CTRL_LP__TWCK2MRS_MASK 0xf0000
+#define MC_SEQ_G5PDX_CTRL_LP__TWCK2MRS__SHIFT 0x10
+#define MC_SEQ_G5PDX_CTRL_LP__TMRD_MASK 0xf00000
+#define MC_SEQ_G5PDX_CTRL_LP__TMRD__SHIFT 0x14
+#define MC_SEQ_G5PDX_CMD0__CMD_MASK 0xffffffff
+#define MC_SEQ_G5PDX_CMD0__CMD__SHIFT 0x0
+#define MC_SEQ_G5PDX_CMD0_LP__CMD_MASK 0xffffffff
+#define MC_SEQ_G5PDX_CMD0_LP__CMD__SHIFT 0x0
+#define MC_SEQ_G5PDX_CMD1__CMD_MASK 0xffffffff
+#define MC_SEQ_G5PDX_CMD1__CMD__SHIFT 0x0
+#define MC_SEQ_G5PDX_CMD1_LP__CMD_MASK 0xffffffff
+#define MC_SEQ_G5PDX_CMD1_LP__CMD__SHIFT 0x0
+#define MC_SEQ_SREG_READ__DATA_MASK 0xffffffff
+#define MC_SEQ_SREG_READ__DATA__SHIFT 0x0
+#define MC_SEQ_SREG_STATUS__AVAIL_RTN_MASK 0xf
+#define MC_SEQ_SREG_STATUS__AVAIL_RTN__SHIFT 0x0
+#define MC_SEQ_SREG_STATUS__PND_RD_MASK 0xf00
+#define MC_SEQ_SREG_STATUS__PND_RD__SHIFT 0x8
+#define MC_SEQ_SREG_STATUS__PND_WR_MASK 0xf000
+#define MC_SEQ_SREG_STATUS__PND_WR__SHIFT 0xc
+#define MC_SEQ_PHYREG_BCAST__CH0_EN_MASK 0x1
+#define MC_SEQ_PHYREG_BCAST__CH0_EN__SHIFT 0x0
+#define MC_SEQ_PHYREG_BCAST__CH1_EN_MASK 0x2
+#define MC_SEQ_PHYREG_BCAST__CH1_EN__SHIFT 0x1
+#define MC_SEQ_PHYREG_BCAST__CKE_MASK_MASK 0x80
+#define MC_SEQ_PHYREG_BCAST__CKE_MASK__SHIFT 0x7
+#define MC_SEQ_PHYREG_BCAST__DQ_MASK_MASK 0x100
+#define MC_SEQ_PHYREG_BCAST__DQ_MASK__SHIFT 0x8
+#define MC_SEQ_PHYREG_BCAST__DBI_MASK_MASK 0x200
+#define MC_SEQ_PHYREG_BCAST__DBI_MASK__SHIFT 0x9
+#define MC_SEQ_PHYREG_BCAST__EDC_MASK_MASK 0x400
+#define MC_SEQ_PHYREG_BCAST__EDC_MASK__SHIFT 0xa
+#define MC_SEQ_PHYREG_BCAST__WCK_MASK_MASK 0x800
+#define MC_SEQ_PHYREG_BCAST__WCK_MASK__SHIFT 0xb
+#define MC_SEQ_PHYREG_BCAST__WCDR_MASK_MASK 0x1000
+#define MC_SEQ_PHYREG_BCAST__WCDR_MASK__SHIFT 0xc
+#define MC_SEQ_PHYREG_BCAST__CLK_MASK_MASK 0x2000
+#define MC_SEQ_PHYREG_BCAST__CLK_MASK__SHIFT 0xd
+#define MC_SEQ_PHYREG_BCAST__CMD_MASK_MASK 0x4000
+#define MC_SEQ_PHYREG_BCAST__CMD_MASK__SHIFT 0xe
+#define MC_SEQ_PHYREG_BCAST__ADR_MASK_MASK 0x8000
+#define MC_SEQ_PHYREG_BCAST__ADR_MASK__SHIFT 0xf
+#define MC_SEQ_PMG_DVS_CTL__ENABLE_MASK 0x1
+#define MC_SEQ_PMG_DVS_CTL__ENABLE__SHIFT 0x0
+#define MC_SEQ_PMG_DVS_CTL__TDVS_MASK 0x3e
+#define MC_SEQ_PMG_DVS_CTL__TDVS__SHIFT 0x1
+#define MC_SEQ_PMG_DVS_CTL_LP__ENABLE_MASK 0x1
+#define MC_SEQ_PMG_DVS_CTL_LP__ENABLE__SHIFT 0x0
+#define MC_SEQ_PMG_DVS_CTL_LP__TDVS_MASK 0x3e
+#define MC_SEQ_PMG_DVS_CTL_LP__TDVS__SHIFT 0x1
+#define MC_SEQ_PMG_DVS_CMD__ADR_MASK 0xffff
+#define MC_SEQ_PMG_DVS_CMD__ADR__SHIFT 0x0
+#define MC_SEQ_PMG_DVS_CMD__MOP_MASK 0x70000
+#define MC_SEQ_PMG_DVS_CMD__MOP__SHIFT 0x10
+#define MC_SEQ_PMG_DVS_CMD__BNK_MSB_MASK 0x80000
+#define MC_SEQ_PMG_DVS_CMD__BNK_MSB__SHIFT 0x13
+#define MC_SEQ_PMG_DVS_CMD__END_MASK 0x100000
+#define MC_SEQ_PMG_DVS_CMD__END__SHIFT 0x14
+#define MC_SEQ_PMG_DVS_CMD__CSB_MASK 0x600000
+#define MC_SEQ_PMG_DVS_CMD__CSB__SHIFT 0x15
+#define MC_SEQ_PMG_DVS_CMD__ADR_MSB1_MASK 0x800000
+#define MC_SEQ_PMG_DVS_CMD__ADR_MSB1__SHIFT 0x17
+#define MC_SEQ_PMG_DVS_CMD__ADR_MSB0_MASK 0x1000000
+#define MC_SEQ_PMG_DVS_CMD__ADR_MSB0__SHIFT 0x18
+#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MASK 0xffff
+#define MC_SEQ_PMG_DVS_CMD_LP__ADR__SHIFT 0x0
+#define MC_SEQ_PMG_DVS_CMD_LP__MOP_MASK 0x70000
+#define MC_SEQ_PMG_DVS_CMD_LP__MOP__SHIFT 0x10
+#define MC_SEQ_PMG_DVS_CMD_LP__BNK_MSB_MASK 0x80000
+#define MC_SEQ_PMG_DVS_CMD_LP__BNK_MSB__SHIFT 0x13
+#define MC_SEQ_PMG_DVS_CMD_LP__END_MASK 0x100000
+#define MC_SEQ_PMG_DVS_CMD_LP__END__SHIFT 0x14
+#define MC_SEQ_PMG_DVS_CMD_LP__CSB_MASK 0x600000
+#define MC_SEQ_PMG_DVS_CMD_LP__CSB__SHIFT 0x15
+#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB1_MASK 0x800000
+#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB1__SHIFT 0x17
+#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB0_MASK 0x1000000
+#define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB0__SHIFT 0x18
+#define MC_SEQ_DLL_STBY__EN_MASK 0x1
+#define MC_SEQ_DLL_STBY__EN__SHIFT 0x0
+#define MC_SEQ_DLL_STBY__VCTRLADC_FRC_MASK 0x2
+#define MC_SEQ_DLL_STBY__VCTRLADC_FRC__SHIFT 0x1
+#define MC_SEQ_DLL_STBY__VCTRLADC_VAL_MASK 0x4
+#define MC_SEQ_DLL_STBY__VCTRLADC_VAL__SHIFT 0x2
+#define MC_SEQ_DLL_STBY__MSTRSTBY_FRC_MASK 0x8
+#define MC_SEQ_DLL_STBY__MSTRSTBY_FRC__SHIFT 0x3
+#define MC_SEQ_DLL_STBY__MSTRSTBY_VAL_MASK 0x10
+#define MC_SEQ_DLL_STBY__MSTRSTBY_VAL__SHIFT 0x4
+#define MC_SEQ_DLL_STBY__ENTR_DLY_MASK 0xe0
+#define MC_SEQ_DLL_STBY__ENTR_DLY__SHIFT 0x5
+#define MC_SEQ_DLL_STBY__STBY_DLY_MASK 0xf00
+#define MC_SEQ_DLL_STBY__STBY_DLY__SHIFT 0x8
+#define MC_SEQ_DLL_STBY__TCKE_PULSE_EXTN_MASK 0xf000
+#define MC_SEQ_DLL_STBY__TCKE_PULSE_EXTN__SHIFT 0xc
+#define MC_SEQ_DLL_STBY__TCKE_EXTN_MASK 0xff0000
+#define MC_SEQ_DLL_STBY__TCKE_EXTN__SHIFT 0x10
+#define MC_SEQ_DLL_STBY__EXIT_DLY_MASK 0x3f000000
+#define MC_SEQ_DLL_STBY__EXIT_DLY__SHIFT 0x18
+#define MC_SEQ_DLL_STBY_LP__EN_MASK 0x1
+#define MC_SEQ_DLL_STBY_LP__EN__SHIFT 0x0
+#define MC_SEQ_DLL_STBY_LP__VCTRLADC_FRC_MASK 0x2
+#define MC_SEQ_DLL_STBY_LP__VCTRLADC_FRC__SHIFT 0x1
+#define MC_SEQ_DLL_STBY_LP__VCTRLADC_VAL_MASK 0x4
+#define MC_SEQ_DLL_STBY_LP__VCTRLADC_VAL__SHIFT 0x2
+#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_FRC_MASK 0x8
+#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_FRC__SHIFT 0x3
+#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_VAL_MASK 0x10
+#define MC_SEQ_DLL_STBY_LP__MSTRSTBY_VAL__SHIFT 0x4
+#define MC_SEQ_DLL_STBY_LP__ENTR_DLY_MASK 0xe0
+#define MC_SEQ_DLL_STBY_LP__ENTR_DLY__SHIFT 0x5
+#define MC_SEQ_DLL_STBY_LP__STBY_DLY_MASK 0xf00
+#define MC_SEQ_DLL_STBY_LP__STBY_DLY__SHIFT 0x8
+#define MC_SEQ_DLL_STBY_LP__TCKE_PULSE_EXTN_MASK 0xf000
+#define MC_SEQ_DLL_STBY_LP__TCKE_PULSE_EXTN__SHIFT 0xc
+#define MC_SEQ_DLL_STBY_LP__TCKE_EXTN_MASK 0xff0000
+#define MC_SEQ_DLL_STBY_LP__TCKE_EXTN__SHIFT 0x10
+#define MC_SEQ_DLL_STBY_LP__EXIT_DLY_MASK 0x3f000000
+#define MC_SEQ_DLL_STBY_LP__EXIT_DLY__SHIFT 0x18
+#define MC_DLB_MISCCTRL0__UDD_ON_STATUS_BITS_MASK 0x1
+#define MC_DLB_MISCCTRL0__UDD_ON_STATUS_BITS__SHIFT 0x0
+#define MC_DLB_MISCCTRL0__LOAD_DATA_SEL_MASK 0x2
+#define MC_DLB_MISCCTRL0__LOAD_DATA_SEL__SHIFT 0x1
+#define MC_DLB_MISCCTRL0__LOAD_UDD_MASK 0x4
+#define MC_DLB_MISCCTRL0__LOAD_UDD__SHIFT 0x2
+#define MC_DLB_MISCCTRL0__ADR_STATUS_SEL_MASK 0x8
+#define MC_DLB_MISCCTRL0__ADR_STATUS_SEL__SHIFT 0x3
+#define MC_DLB_MISCCTRL0__DATA_SEL_MASK 0xf0
+#define MC_DLB_MISCCTRL0__DATA_SEL__SHIFT 0x4
+#define MC_DLB_MISCCTRL0__PRBS_CHK_LOAD_CNT_MASK 0x7f00
+#define MC_DLB_MISCCTRL0__PRBS_CHK_LOAD_CNT__SHIFT 0x8
+#define MC_DLB_MISCCTRL0__UDD_MASK 0xffff0000
+#define MC_DLB_MISCCTRL0__UDD__SHIFT 0x10
+#define MC_DLB_MISCCTRL1__PRBS_ERR_CNT_LIMIT_MASK 0xffffffff
+#define MC_DLB_MISCCTRL1__PRBS_ERR_CNT_LIMIT__SHIFT 0x0
+#define MC_DLB_MISCCTRL2__PRBS_RUN_LENGTH_MASK 0x1ffff
+#define MC_DLB_MISCCTRL2__PRBS_RUN_LENGTH__SHIFT 0x0
+#define MC_DLB_MISCCTRL2__PRBS_FREERUN_MASK 0x20000
+#define MC_DLB_MISCCTRL2__PRBS_FREERUN__SHIFT 0x11
+#define MC_DLB_MISCCTRL2__PRBS15_MODE_MASK 0x40000
+#define MC_DLB_MISCCTRL2__PRBS15_MODE__SHIFT 0x12
+#define MC_DLB_MISCCTRL2__PRBS23_MODE_MASK 0x80000
+#define MC_DLB_MISCCTRL2__PRBS23_MODE__SHIFT 0x13
+#define MC_DLB_MISCCTRL2__STOP_ON_NEXT_ERR_MASK 0x100000
+#define MC_DLB_MISCCTRL2__STOP_ON_NEXT_ERR__SHIFT 0x14
+#define MC_DLB_MISCCTRL2__STOP_CLK_MASK 0x200000
+#define MC_DLB_MISCCTRL2__STOP_CLK__SHIFT 0x15
+#define MC_DLB_MISCCTRL2__SWEEP_DLY_MASK 0x3000000
+#define MC_DLB_MISCCTRL2__SWEEP_DLY__SHIFT 0x18
+#define MC_DLB_MISCCTRL2__GRAY_CODE_EN_MASK 0x4000000
+#define MC_DLB_MISCCTRL2__GRAY_CODE_EN__SHIFT 0x1a
+#define MC_DLB_MISCCTRL2__SEL_PHY_PRBS_CHK_MASK 0x10000000
+#define MC_DLB_MISCCTRL2__SEL_PHY_PRBS_CHK__SHIFT 0x1c
+#define MC_DLB_MISCCTRL2__SEL_AC_PRBS_CHK_MASK 0x20000000
+#define MC_DLB_MISCCTRL2__SEL_AC_PRBS_CHK__SHIFT 0x1d
+#define MC_DLB_MISCCTRL2__STATUS_SEL_MASK 0x40000000
+#define MC_DLB_MISCCTRL2__STATUS_SEL__SHIFT 0x1e
+#define MC_DLB_CONFIG0__CONF_EN_CH0_MASK 0x1
+#define MC_DLB_CONFIG0__CONF_EN_CH0__SHIFT 0x0
+#define MC_DLB_CONFIG0__CONF_EN_CH1_MASK 0x2
+#define MC_DLB_CONFIG0__CONF_EN_CH1__SHIFT 0x1
+#define MC_DLB_CONFIG0__CONF_AUTO_EN_MASK 0x4
+#define MC_DLB_CONFIG0__CONF_AUTO_EN__SHIFT 0x2
+#define MC_DLB_CONFIG0__MASK_MASK 0xf0
+#define MC_DLB_CONFIG0__MASK__SHIFT 0x4
+#define MC_DLB_CONFIG0__PTR_MASK 0x3ff00
+#define MC_DLB_CONFIG0__PTR__SHIFT 0x8
+#define MC_DLB_CONFIG1__DATA_MASK 0xffffffff
+#define MC_DLB_CONFIG1__DATA__SHIFT 0x0
+#define MC_DLB_SETUP__DLB_EN_MASK 0x1
+#define MC_DLB_SETUP__DLB_EN__SHIFT 0x0
+#define MC_DLB_SETUP__DLB_FIFO_EN_MASK 0x2
+#define MC_DLB_SETUP__DLB_FIFO_EN__SHIFT 0x1
+#define MC_DLB_SETUP__DLB_STATUS_EN_MASK 0x4
+#define MC_DLB_SETUP__DLB_STATUS_EN__SHIFT 0x2
+#define MC_DLB_SETUP__DLB_CONFIG_EN_MASK 0x8
+#define MC_DLB_SETUP__DLB_CONFIG_EN__SHIFT 0x3
+#define MC_DLB_SETUP__DLB_PRBS_EN_MASK 0x10
+#define MC_DLB_SETUP__DLB_PRBS_EN__SHIFT 0x4
+#define MC_DLB_SETUP__PRBS_GEN_RST_MASK 0x20
+#define MC_DLB_SETUP__PRBS_GEN_RST__SHIFT 0x5
+#define MC_DLB_SETUP__PRBS_CHK_RST_MASK 0x40
+#define MC_DLB_SETUP__PRBS_CHK_RST__SHIFT 0x6
+#define MC_DLB_SETUP__PRBS_PHY_RST_MASK 0x80
+#define MC_DLB_SETUP__PRBS_PHY_RST__SHIFT 0x7
+#define MC_DLB_SETUP__QDR_MODE_MASK 0x100
+#define MC_DLB_SETUP__QDR_MODE__SHIFT 0x8
+#define MC_DLB_SETUP__CHK_DATA_BITS_MASK 0xff0000
+#define MC_DLB_SETUP__CHK_DATA_BITS__SHIFT 0x10
+#define MC_DLB_SETUP__MEM_BIT_SEL_MASK 0x1f000000
+#define MC_DLB_SETUP__MEM_BIT_SEL__SHIFT 0x18
+#define MC_DLB_SETUP__RXTXLP_EN_MASK 0x80000000
+#define MC_DLB_SETUP__RXTXLP_EN__SHIFT 0x1f
+#define MC_DLB_SETUPSWEEP__DLL_RST_MASK 0x1
+#define MC_DLB_SETUPSWEEP__DLL_RST__SHIFT 0x0
+#define MC_DLB_SETUPSWEEP__CONFIG_MASK 0x2
+#define MC_DLB_SETUPSWEEP__CONFIG__SHIFT 0x1
+#define MC_DLB_SETUPSWEEP__MASTER_MASK 0x4
+#define MC_DLB_SETUPSWEEP__MASTER__SHIFT 0x2
+#define MC_DLB_SETUPSWEEP__DLLDLY_MASK 0xf0
+#define MC_DLB_SETUPSWEEP__DLLDLY__SHIFT 0x4
+#define MC_DLB_SETUPSWEEP__DLLSTEPS_MASK 0x1f00
+#define MC_DLB_SETUPSWEEP__DLLSTEPS__SHIFT 0x8
+#define MC_DLB_SETUPFIFO__WRITE_FIFO_RST_MASK 0x1
+#define MC_DLB_SETUPFIFO__WRITE_FIFO_RST__SHIFT 0x0
+#define MC_DLB_SETUPFIFO__READ_FIFO_RST_MASK 0x2
+#define MC_DLB_SETUPFIFO__READ_FIFO_RST__SHIFT 0x1
+#define MC_DLB_SETUPFIFO__BOTH_FIFO_RST_MASK 0x4
+#define MC_DLB_SETUPFIFO__BOTH_FIFO_RST__SHIFT 0x2
+#define MC_DLB_SETUPFIFO__SYNC_RST_MASK 0x8
+#define MC_DLB_SETUPFIFO__SYNC_RST__SHIFT 0x3
+#define MC_DLB_SETUPFIFO__SYNC_RST_MASK_MASK 0x30
+#define MC_DLB_SETUPFIFO__SYNC_RST_MASK__SHIFT 0x4
+#define MC_DLB_SETUPFIFO__OUTPUT_EN_RST_MASK 0x40
+#define MC_DLB_SETUPFIFO__OUTPUT_EN_RST__SHIFT 0x6
+#define MC_DLB_SETUPFIFO__SHIFT_WR_FIFO_PTR_MASK 0x300
+#define MC_DLB_SETUPFIFO__SHIFT_WR_FIFO_PTR__SHIFT 0x8
+#define MC_DLB_SETUPFIFO__DELAY_RD_FIFO_PTR_MASK 0x1c00
+#define MC_DLB_SETUPFIFO__DELAY_RD_FIFO_PTR__SHIFT 0xa
+#define MC_DLB_SETUPFIFO__STROBE_MASK 0xf0000
+#define MC_DLB_SETUPFIFO__STROBE__SHIFT 0x10
+#define MC_DLB_WRITE_MASK__BIT_MASK_MASK 0x3fffff
+#define MC_DLB_WRITE_MASK__BIT_MASK__SHIFT 0x0
+#define MC_DLB_WRITE_MASK__CH_MASK_MASK 0xf000000
+#define MC_DLB_WRITE_MASK__CH_MASK__SHIFT 0x18
+#define MC_DLB_STATUS__STICK_ERROR_MASK 0xf
+#define MC_DLB_STATUS__STICK_ERROR__SHIFT 0x0
+#define MC_DLB_STATUS__LOCK_MASK 0xf0
+#define MC_DLB_STATUS__LOCK__SHIFT 0x4
+#define MC_DLB_STATUS__SWEEP_DONE_MASK 0xf00
+#define MC_DLB_STATUS__SWEEP_DONE__SHIFT 0x8
+#define MC_DLB_STATUS_MISC0__DATA_MASK 0xffffffff
+#define MC_DLB_STATUS_MISC0__DATA__SHIFT 0x0
+#define MC_DLB_STATUS_MISC1__DATA_MASK 0xffffffff
+#define MC_DLB_STATUS_MISC1__DATA__SHIFT 0x0
+#define MC_DLB_STATUS_MISC2__DATA_MASK 0xffffffff
+#define MC_DLB_STATUS_MISC2__DATA__SHIFT 0x0
+#define MC_DLB_STATUS_MISC3__DATA_MASK 0xffffffff
+#define MC_DLB_STATUS_MISC3__DATA__SHIFT 0x0
+#define MC_DLB_STATUS_MISC4__DATA_MASK 0xffffffff
+#define MC_DLB_STATUS_MISC4__DATA__SHIFT 0x0
+#define MC_DLB_STATUS_MISC5__DATA_MASK 0xffffffff
+#define MC_DLB_STATUS_MISC5__DATA__SHIFT 0x0
+#define MC_DLB_STATUS_MISC6__DATA_MASK 0xffffffff
+#define MC_DLB_STATUS_MISC6__DATA__SHIFT 0x0
+#define MC_DLB_STATUS_MISC7__DATA_MASK 0xffffffff
+#define MC_DLB_STATUS_MISC7__DATA__SHIFT 0x0
+#define MC_ARB_HARSH_EN_RD__TX_PRI_MASK 0xff
+#define MC_ARB_HARSH_EN_RD__TX_PRI__SHIFT 0x0
+#define MC_ARB_HARSH_EN_RD__BW_PRI_MASK 0xff00
+#define MC_ARB_HARSH_EN_RD__BW_PRI__SHIFT 0x8
+#define MC_ARB_HARSH_EN_RD__FIX_PRI_MASK 0xff0000
+#define MC_ARB_HARSH_EN_RD__FIX_PRI__SHIFT 0x10
+#define MC_ARB_HARSH_EN_RD__ST_PRI_MASK 0xff000000
+#define MC_ARB_HARSH_EN_RD__ST_PRI__SHIFT 0x18
+#define MC_ARB_HARSH_EN_WR__TX_PRI_MASK 0xff
+#define MC_ARB_HARSH_EN_WR__TX_PRI__SHIFT 0x0
+#define MC_ARB_HARSH_EN_WR__BW_PRI_MASK 0xff00
+#define MC_ARB_HARSH_EN_WR__BW_PRI__SHIFT 0x8
+#define MC_ARB_HARSH_EN_WR__FIX_PRI_MASK 0xff0000
+#define MC_ARB_HARSH_EN_WR__FIX_PRI__SHIFT 0x10
+#define MC_ARB_HARSH_EN_WR__ST_PRI_MASK 0xff000000
+#define MC_ARB_HARSH_EN_WR__ST_PRI__SHIFT 0x18
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_SAT0_RD__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_SAT0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_SAT0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_SAT0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_SAT0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_SAT0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_SAT0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_SAT0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_SAT0_WR__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_SAT0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_SAT0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_SAT0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_SAT0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_SAT0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_SAT0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_SAT0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_SAT1_RD__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_SAT1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_SAT1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_SAT1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_SAT1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_SAT1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_SAT1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_SAT1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_SAT1_WR__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_SAT1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_SAT1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_SAT1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_SAT1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_SAT1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_SAT1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_SAT1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST_MASK 0xff
+#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST__SHIFT 0x0
+#define MC_ARB_HARSH_CTL_RD__HARSH_RR_MASK 0x100
+#define MC_ARB_HARSH_CTL_RD__HARSH_RR__SHIFT 0x8
+#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY_MASK 0x200
+#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY__SHIFT 0x9
+#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH_MASK 0x400
+#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH__SHIFT 0xa
+#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP_MASK 0x800
+#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP__SHIFT 0xb
+#define MC_ARB_HARSH_CTL_RD__ST_MODE_MASK 0x3000
+#define MC_ARB_HARSH_CTL_RD__ST_MODE__SHIFT 0xc
+#define MC_ARB_HARSH_CTL_RD__FORCE_STALL_MASK 0x3fc000
+#define MC_ARB_HARSH_CTL_RD__FORCE_STALL__SHIFT 0xe
+#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL_MASK 0x1c00000
+#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL__SHIFT 0x16
+#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST_MASK 0xff
+#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST__SHIFT 0x0
+#define MC_ARB_HARSH_CTL_WR__HARSH_RR_MASK 0x100
+#define MC_ARB_HARSH_CTL_WR__HARSH_RR__SHIFT 0x8
+#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY_MASK 0x200
+#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY__SHIFT 0x9
+#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH_MASK 0x400
+#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH__SHIFT 0xa
+#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP_MASK 0x800
+#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP__SHIFT 0xb
+#define MC_ARB_HARSH_CTL_WR__ST_MODE_MASK 0x3000
+#define MC_ARB_HARSH_CTL_WR__ST_MODE__SHIFT 0xc
+#define MC_ARB_HARSH_CTL_WR__FORCE_STALL_MASK 0x3fc000
+#define MC_ARB_HARSH_CTL_WR__FORCE_STALL__SHIFT 0xe
+#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL_MASK 0x1c00000
+#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL__SHIFT 0x16
+#define MC_ARB_GRUB_PRIORITY1_RD__CB0_MASK 0x3
+#define MC_ARB_GRUB_PRIORITY1_RD__CB0__SHIFT 0x0
+#define MC_ARB_GRUB_PRIORITY1_RD__CBCMASK0_MASK 0xc
+#define MC_ARB_GRUB_PRIORITY1_RD__CBCMASK0__SHIFT 0x2
+#define MC_ARB_GRUB_PRIORITY1_RD__CBFMASK0_MASK 0x30
+#define MC_ARB_GRUB_PRIORITY1_RD__CBFMASK0__SHIFT 0x4
+#define MC_ARB_GRUB_PRIORITY1_RD__DB0_MASK 0xc0
+#define MC_ARB_GRUB_PRIORITY1_RD__DB0__SHIFT 0x6
+#define MC_ARB_GRUB_PRIORITY1_RD__DBHTILE0_MASK 0x300
+#define MC_ARB_GRUB_PRIORITY1_RD__DBHTILE0__SHIFT 0x8
+#define MC_ARB_GRUB_PRIORITY1_RD__DBSTEN0_MASK 0xc00
+#define MC_ARB_GRUB_PRIORITY1_RD__DBSTEN0__SHIFT 0xa
+#define MC_ARB_GRUB_PRIORITY1_RD__TC0_MASK 0x3000
+#define MC_ARB_GRUB_PRIORITY1_RD__TC0__SHIFT 0xc
+#define MC_ARB_GRUB_PRIORITY1_RD__ACPG_MASK 0xc000
+#define MC_ARB_GRUB_PRIORITY1_RD__ACPG__SHIFT 0xe
+#define MC_ARB_GRUB_PRIORITY1_RD__ACPO_MASK 0x30000
+#define MC_ARB_GRUB_PRIORITY1_RD__ACPO__SHIFT 0x10
+#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_MASK 0xc0000
+#define MC_ARB_GRUB_PRIORITY1_RD__DMIF__SHIFT 0x12
+#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT0_MASK 0x300000
+#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT0__SHIFT 0x14
+#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT1_MASK 0xc00000
+#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT1__SHIFT 0x16
+#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_TW_MASK 0x3000000
+#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_TW__SHIFT 0x18
+#define MC_ARB_GRUB_PRIORITY1_RD__MCIF_MASK 0xc000000
+#define MC_ARB_GRUB_PRIORITY1_RD__MCIF__SHIFT 0x1a
+#define MC_ARB_GRUB_PRIORITY1_RD__RLC_MASK 0x30000000
+#define MC_ARB_GRUB_PRIORITY1_RD__RLC__SHIFT 0x1c
+#define MC_ARB_GRUB_PRIORITY1_RD__VMC_MASK 0xc0000000
+#define MC_ARB_GRUB_PRIORITY1_RD__VMC__SHIFT 0x1e
+#define MC_ARB_GRUB_PRIORITY1_WR__CB0_MASK 0x3
+#define MC_ARB_GRUB_PRIORITY1_WR__CB0__SHIFT 0x0
+#define MC_ARB_GRUB_PRIORITY1_WR__CBCMASK0_MASK 0xc
+#define MC_ARB_GRUB_PRIORITY1_WR__CBCMASK0__SHIFT 0x2
+#define MC_ARB_GRUB_PRIORITY1_WR__CBFMASK0_MASK 0x30
+#define MC_ARB_GRUB_PRIORITY1_WR__CBFMASK0__SHIFT 0x4
+#define MC_ARB_GRUB_PRIORITY1_WR__CBIMMED0_MASK 0xc0
+#define MC_ARB_GRUB_PRIORITY1_WR__CBIMMED0__SHIFT 0x6
+#define MC_ARB_GRUB_PRIORITY1_WR__DB0_MASK 0x300
+#define MC_ARB_GRUB_PRIORITY1_WR__DB0__SHIFT 0x8
+#define MC_ARB_GRUB_PRIORITY1_WR__DBHTILE0_MASK 0xc00
+#define MC_ARB_GRUB_PRIORITY1_WR__DBHTILE0__SHIFT 0xa
+#define MC_ARB_GRUB_PRIORITY1_WR__DBSTEN0_MASK 0x3000
+#define MC_ARB_GRUB_PRIORITY1_WR__DBSTEN0__SHIFT 0xc
+#define MC_ARB_GRUB_PRIORITY1_WR__TC0_MASK 0xc000
+#define MC_ARB_GRUB_PRIORITY1_WR__TC0__SHIFT 0xe
+#define MC_ARB_GRUB_PRIORITY1_WR__SH_MASK 0x30000
+#define MC_ARB_GRUB_PRIORITY1_WR__SH__SHIFT 0x10
+#define MC_ARB_GRUB_PRIORITY1_WR__ACPG_MASK 0xc0000
+#define MC_ARB_GRUB_PRIORITY1_WR__ACPG__SHIFT 0x12
+#define MC_ARB_GRUB_PRIORITY1_WR__ACPO_MASK 0x300000
+#define MC_ARB_GRUB_PRIORITY1_WR__ACPO__SHIFT 0x14
+#define MC_ARB_GRUB_PRIORITY1_WR__MCIF_MASK 0xc00000
+#define MC_ARB_GRUB_PRIORITY1_WR__MCIF__SHIFT 0x16
+#define MC_ARB_GRUB_PRIORITY1_WR__RLC_MASK 0x3000000
+#define MC_ARB_GRUB_PRIORITY1_WR__RLC__SHIFT 0x18
+#define MC_ARB_GRUB_PRIORITY1_WR__SDMA1_MASK 0xc000000
+#define MC_ARB_GRUB_PRIORITY1_WR__SDMA1__SHIFT 0x1a
+#define MC_ARB_GRUB_PRIORITY1_WR__SMU_MASK 0x30000000
+#define MC_ARB_GRUB_PRIORITY1_WR__SMU__SHIFT 0x1c
+#define MC_ARB_GRUB_PRIORITY1_WR__VCE0_MASK 0xc0000000
+#define MC_ARB_GRUB_PRIORITY1_WR__VCE0__SHIFT 0x1e
+#define MC_ARB_GRUB_PRIORITY2_RD__SDMA1_MASK 0x3
+#define MC_ARB_GRUB_PRIORITY2_RD__SDMA1__SHIFT 0x0
+#define MC_ARB_GRUB_PRIORITY2_RD__SMU_MASK 0xc
+#define MC_ARB_GRUB_PRIORITY2_RD__SMU__SHIFT 0x2
+#define MC_ARB_GRUB_PRIORITY2_RD__VCE0_MASK 0x30
+#define MC_ARB_GRUB_PRIORITY2_RD__VCE0__SHIFT 0x4
+#define MC_ARB_GRUB_PRIORITY2_RD__VCE1_MASK 0xc0
+#define MC_ARB_GRUB_PRIORITY2_RD__VCE1__SHIFT 0x6
+#define MC_ARB_GRUB_PRIORITY2_RD__XDMAM_MASK 0x300
+#define MC_ARB_GRUB_PRIORITY2_RD__XDMAM__SHIFT 0x8
+#define MC_ARB_GRUB_PRIORITY2_RD__SDMA0_MASK 0xc00
+#define MC_ARB_GRUB_PRIORITY2_RD__SDMA0__SHIFT 0xa
+#define MC_ARB_GRUB_PRIORITY2_RD__HDP_MASK 0x3000
+#define MC_ARB_GRUB_PRIORITY2_RD__HDP__SHIFT 0xc
+#define MC_ARB_GRUB_PRIORITY2_RD__UMC_MASK 0xc000
+#define MC_ARB_GRUB_PRIORITY2_RD__UMC__SHIFT 0xe
+#define MC_ARB_GRUB_PRIORITY2_RD__UVD_MASK 0x30000
+#define MC_ARB_GRUB_PRIORITY2_RD__UVD__SHIFT 0x10
+#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT0_MASK 0xc0000
+#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT0__SHIFT 0x12
+#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT1_MASK 0x300000
+#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT1__SHIFT 0x14
+#define MC_ARB_GRUB_PRIORITY2_RD__SEM_MASK 0xc00000
+#define MC_ARB_GRUB_PRIORITY2_RD__SEM__SHIFT 0x16
+#define MC_ARB_GRUB_PRIORITY2_RD__SAMMSP_MASK 0x3000000
+#define MC_ARB_GRUB_PRIORITY2_RD__SAMMSP__SHIFT 0x18
+#define MC_ARB_GRUB_PRIORITY2_RD__VP8_MASK 0xc000000
+#define MC_ARB_GRUB_PRIORITY2_RD__VP8__SHIFT 0x1a
+#define MC_ARB_GRUB_PRIORITY2_RD__ISP_MASK 0x30000000
+#define MC_ARB_GRUB_PRIORITY2_RD__ISP__SHIFT 0x1c
+#define MC_ARB_GRUB_PRIORITY2_RD__RSV2_MASK 0xc0000000
+#define MC_ARB_GRUB_PRIORITY2_RD__RSV2__SHIFT 0x1e
+#define MC_ARB_GRUB_PRIORITY2_WR__VCE1_MASK 0x3
+#define MC_ARB_GRUB_PRIORITY2_WR__VCE1__SHIFT 0x0
+#define MC_ARB_GRUB_PRIORITY2_WR__SAMMSP_MASK 0xc
+#define MC_ARB_GRUB_PRIORITY2_WR__SAMMSP__SHIFT 0x2
+#define MC_ARB_GRUB_PRIORITY2_WR__XDMA_MASK 0x30
+#define MC_ARB_GRUB_PRIORITY2_WR__XDMA__SHIFT 0x4
+#define MC_ARB_GRUB_PRIORITY2_WR__XDMAM_MASK 0xc0
+#define MC_ARB_GRUB_PRIORITY2_WR__XDMAM__SHIFT 0x6
+#define MC_ARB_GRUB_PRIORITY2_WR__SDMA0_MASK 0x300
+#define MC_ARB_GRUB_PRIORITY2_WR__SDMA0__SHIFT 0x8
+#define MC_ARB_GRUB_PRIORITY2_WR__HDP_MASK 0xc00
+#define MC_ARB_GRUB_PRIORITY2_WR__HDP__SHIFT 0xa
+#define MC_ARB_GRUB_PRIORITY2_WR__UMC_MASK 0x3000
+#define MC_ARB_GRUB_PRIORITY2_WR__UMC__SHIFT 0xc
+#define MC_ARB_GRUB_PRIORITY2_WR__UVD_MASK 0xc000
+#define MC_ARB_GRUB_PRIORITY2_WR__UVD__SHIFT 0xe
+#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT0_MASK 0x30000
+#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT0__SHIFT 0x10
+#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT1_MASK 0xc0000
+#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT1__SHIFT 0x12
+#define MC_ARB_GRUB_PRIORITY2_WR__XDP_MASK 0x300000
+#define MC_ARB_GRUB_PRIORITY2_WR__XDP__SHIFT 0x14
+#define MC_ARB_GRUB_PRIORITY2_WR__SEM_MASK 0xc00000
+#define MC_ARB_GRUB_PRIORITY2_WR__SEM__SHIFT 0x16
+#define MC_ARB_GRUB_PRIORITY2_WR__IH_MASK 0x3000000
+#define MC_ARB_GRUB_PRIORITY2_WR__IH__SHIFT 0x18
+#define MC_ARB_GRUB_PRIORITY2_WR__VP8_MASK 0xc000000
+#define MC_ARB_GRUB_PRIORITY2_WR__VP8__SHIFT 0x1a
+#define MC_ARB_GRUB_PRIORITY2_WR__ISP_MASK 0x30000000
+#define MC_ARB_GRUB_PRIORITY2_WR__ISP__SHIFT 0x1c
+#define MC_ARB_GRUB_PRIORITY2_WR__VIN0_MASK 0xc0000000
+#define MC_ARB_GRUB_PRIORITY2_WR__VIN0__SHIFT 0x1e
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x1
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x2
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x10
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x20
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x40
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0xf00
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0xf0000
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10
+#define MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x1fff
+#define MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x1
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x2
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x70
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x80
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0xf00
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x1fff000
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0xff00
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xff000000
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x1
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x2
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x4
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x8
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x10
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0xe0
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0xf00
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x7000
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x8000
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1fff0000
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x1fff
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x2000
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x4000
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x1
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x2
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x4
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x8
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x10
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0xe0
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0xf00
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x7000
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x8000
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1fff0000
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x1fff
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x2000
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x4000
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x1
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x2
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x4
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x8
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x10
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0xe0
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0xf00
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x7000
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x8000
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1fff0000
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x1fff
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x2000
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x4000
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x1
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x2
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x4
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x8
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x10
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0xe0
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0xf00
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x7000
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x8000
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1fff0000
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x1fff
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x2000
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x4000
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x3
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xfc000000
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x1a
+#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT0_URGENCY_WATERMARK_MASK 0xffff
+#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT0_URGENCY_WATERMARK__SHIFT 0x0
+#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT1_URGENCY_WATERMARK_MASK 0xffff0000
+#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT1_URGENCY_WATERMARK__SHIFT 0x10
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK 0xff
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT 0x0
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK 0xffffffff
+#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT 0x0
+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xffffffff
+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0
+#define MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x3ffff
+#define MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xffffffff
+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0
+#define MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x3ffff
+#define MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xffffffff
+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0
+#define MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x3ffff
+#define MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xffffffff
+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0
+#define MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x3ffff
+#define MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xffffffff
+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0
+#define MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x3ffff
+#define MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xffffffff
+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0
+#define MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x3ffff
+#define MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xffffffff
+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0
+#define MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x3ffff
+#define MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xffffffff
+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0
+#define MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x3ffff
+#define MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x1
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x10
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x20
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x40
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0xf00
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1fff0000
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10
+#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_DEFAULT_VMID_MASK 0xf00
+#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_DEFAULT_VMID__SHIFT 0x8
+#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_ALLOWED_VMID_MASK_MASK 0xffff0000
+#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_ALLOWED_VMID_MASK__SHIFT 0x10
+
+#endif /* GMC_8_1_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_d.h
new file mode 100644
index 000000000000..06ef7d9b0cb3
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_d.h
@@ -0,0 +1,910 @@
+/*
+ * GMC_8_2 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GMC_8_2_D_H
+#define GMC_8_2_D_H
+
+#define mmMC_CONFIG 0x800
+#define mmMC_ARB_ATOMIC 0x9be
+#define mmMC_ARB_AGE_CNTL 0x9bf
+#define mmMC_ARB_RET_CREDITS2 0x9c0
+#define mmMC_ARB_FED_CNTL 0x9c1
+#define mmMC_ARB_GECC2_STATUS 0x9c2
+#define mmMC_ARB_GECC2_MISC 0x9c3
+#define mmMC_ARB_GECC2_DEBUG 0x9c4
+#define mmMC_ARB_GECC2_DEBUG2 0x9c5
+#define mmMC_ARB_PERF_CID 0x9c6
+#define mmMC_ARB_SNOOP 0x9c7
+#define mmMC_ARB_GRUB 0x9c8
+#define mmMC_ARB_GECC2 0x9c9
+#define mmMC_ARB_GECC2_CLI 0x9ca
+#define mmMC_ARB_ADDR_SWIZ0 0x9cb
+#define mmMC_ARB_ADDR_SWIZ1 0x9cc
+#define mmMC_ARB_MISC3 0x9cd
+#define mmMC_ARB_GRUB_PROMOTE 0x9ce
+#define mmMC_ARB_RTT_DATA 0x9cf
+#define mmMC_ARB_RTT_CNTL0 0x9d0
+#define mmMC_ARB_RTT_CNTL1 0x9d1
+#define mmMC_ARB_RTT_CNTL2 0x9d2
+#define mmMC_ARB_RTT_DEBUG 0x9d3
+#define mmMC_ARB_CAC_CNTL 0x9d4
+#define mmMC_ARB_MISC2 0x9d5
+#define mmMC_ARB_MISC 0x9d6
+#define mmMC_ARB_BANKMAP 0x9d7
+#define mmMC_ARB_RAMCFG 0x9d8
+#define mmMC_ARB_POP 0x9d9
+#define mmMC_ARB_MINCLKS 0x9da
+#define mmMC_ARB_SQM_CNTL 0x9db
+#define mmMC_ARB_ADDR_HASH 0x9dc
+#define mmMC_ARB_DRAM_TIMING 0x9dd
+#define mmMC_ARB_DRAM_TIMING2 0x9de
+#define mmMC_ARB_WTM_CNTL_RD 0x9df
+#define mmMC_ARB_WTM_CNTL_WR 0x9e0
+#define mmMC_ARB_WTM_GRPWT_RD 0x9e1
+#define mmMC_ARB_WTM_GRPWT_WR 0x9e2
+#define mmMC_ARB_TM_CNTL_RD 0x9e3
+#define mmMC_ARB_TM_CNTL_WR 0x9e4
+#define mmMC_ARB_LAZY0_RD 0x9e5
+#define mmMC_ARB_LAZY0_WR 0x9e6
+#define mmMC_ARB_LAZY1_RD 0x9e7
+#define mmMC_ARB_LAZY1_WR 0x9e8
+#define mmMC_ARB_AGE_RD 0x9e9
+#define mmMC_ARB_AGE_WR 0x9ea
+#define mmMC_ARB_RFSH_CNTL 0x9eb
+#define mmMC_ARB_RFSH_RATE 0x9ec
+#define mmMC_ARB_PM_CNTL 0x9ed
+#define mmMC_ARB_GDEC_RD_CNTL 0x9ee
+#define mmMC_ARB_GDEC_WR_CNTL 0x9ef
+#define mmMC_ARB_LM_RD 0x9f0
+#define mmMC_ARB_LM_WR 0x9f1
+#define mmMC_ARB_REMREQ 0x9f2
+#define mmMC_ARB_REPLAY 0x9f3
+#define mmMC_ARB_RET_CREDITS_RD 0x9f4
+#define mmMC_ARB_RET_CREDITS_WR 0x9f5
+#define mmMC_ARB_MAX_LAT_CID 0x9f6
+#define mmMC_ARB_MAX_LAT_RSLT0 0x9f7
+#define mmMC_ARB_MAX_LAT_RSLT1 0x9f8
+#define mmMC_ARB_GRUB_REALTIME_RD 0x9f9
+#define mmMC_ARB_CG 0x9fa
+#define mmMC_ARB_GRUB_REALTIME_WR 0x9fb
+#define mmMC_ARB_DRAM_TIMING_1 0x9fc
+#define mmMC_ARB_BUSY_STATUS 0x9fd
+#define mmMC_ARB_DRAM_TIMING2_1 0x9ff
+#define mmMC_ARB_GRUB2 0xa01
+#define mmMC_ARB_BURST_TIME 0xa02
+#define mmMC_CITF_XTRA_ENABLE 0x96d
+#define mmCC_MC_MAX_CHANNEL 0x96e
+#define mmMC_CG_CONFIG 0x96f
+#define mmMC_CITF_CNTL 0x970
+#define mmMC_CITF_CREDITS_VM 0x971
+#define mmMC_CITF_CREDITS_ARB_RD 0x972
+#define mmMC_CITF_CREDITS_ARB_WR 0x973
+#define mmMC_CITF_DAGB_CNTL 0x974
+#define mmMC_CITF_INT_CREDITS 0x975
+#define mmMC_CITF_RET_MODE 0x976
+#define mmMC_CITF_DAGB_DLY 0x977
+#define mmMC_RD_GRP_EXT 0x978
+#define mmMC_WR_GRP_EXT 0x979
+#define mmMC_CITF_REMREQ 0x97a
+#define mmMC_WR_TC0 0x97b
+#define mmMC_WR_TC1 0x97c
+#define mmMC_CITF_INT_CREDITS_WR 0x97d
+#define mmMC_CITF_CREDITS_ARB_RD2 0x97e
+#define mmMC_CITF_WTM_RD_CNTL 0x97f
+#define mmMC_CITF_WTM_WR_CNTL 0x980
+#define mmMC_RD_CB 0x981
+#define mmMC_RD_DB 0x982
+#define mmMC_RD_TC0 0x983
+#define mmMC_RD_TC1 0x984
+#define mmMC_RD_HUB 0x985
+#define mmMC_WR_CB 0x986
+#define mmMC_WR_DB 0x987
+#define mmMC_WR_HUB 0x988
+#define mmMC_CITF_CREDITS_XBAR 0x989
+#define mmMC_RD_GRP_LCL 0x98a
+#define mmMC_WR_GRP_LCL 0x98b
+#define mmMC_CITF_PERF_MON_CNTL2 0x98e
+#define mmMC_CITF_PERF_MON_RSLT2 0x991
+#define mmMC_CITF_MISC_RD_CG 0x992
+#define mmMC_CITF_MISC_WR_CG 0x993
+#define mmMC_CITF_MISC_VM_CG 0x994
+#define mmMC_HUB_MISC_POWER 0x82d
+#define mmMC_HUB_MISC_HUB_CG 0x82e
+#define mmMC_HUB_MISC_VM_CG 0x82f
+#define mmMC_HUB_MISC_SIP_CG 0x830
+#define mmMC_HUB_MISC_STATUS 0x832
+#define mmMC_HUB_MISC_OVERRIDE 0x833
+#define mmMC_HUB_MISC_FRAMING 0x834
+#define mmMC_HUB_WDP_CNTL 0x835
+#define mmMC_HUB_WDP_ERR 0x836
+#define mmMC_HUB_WDP_BP 0x837
+#define mmMC_HUB_WDP_STATUS 0x838
+#define mmMC_HUB_RDREQ_STATUS 0x839
+#define mmMC_HUB_WRRET_STATUS 0x83a
+#define mmMC_HUB_RDREQ_CNTL 0x83b
+#define mmMC_HUB_WRRET_CNTL 0x83c
+#define mmMC_HUB_RDREQ_WTM_CNTL 0x83d
+#define mmMC_HUB_WDP_WTM_CNTL 0x83e
+#define mmMC_HUB_WDP_CREDITS 0x83f
+#define mmMC_HUB_WDP_CREDITS2 0x840
+#define mmMC_HUB_WDP_GBL0 0x841
+#define mmMC_HUB_WDP_GBL1 0x842
+#define mmMC_HUB_RDREQ_CREDITS 0x844
+#define mmMC_HUB_RDREQ_CREDITS2 0x845
+#define mmMC_HUB_SHARED_DAGB_DLY 0x846
+#define mmMC_HUB_MISC_IDLE_STATUS 0x847
+#define mmMC_HUB_RDREQ_DMIF_LIMIT 0x848
+#define mmMC_HUB_RDREQ_ACPG_LIMIT 0x849
+#define mmMC_HUB_WDP_BYPASS_GBL0 0x84a
+#define mmMC_HUB_WDP_BYPASS_GBL1 0x84b
+#define mmMC_HUB_RDREQ_BYPASS_GBL0 0x84c
+#define mmMC_HUB_WDP_SH2 0x84d
+#define mmMC_HUB_WDP_SH3 0x84e
+#define mmMC_HUB_MISC_ATOMIC_IDLE_STATUS 0x84f
+#define mmMC_HUB_RDREQ_MCDW 0x851
+#define mmMC_HUB_RDREQ_MCDX 0x852
+#define mmMC_HUB_RDREQ_MCDY 0x853
+#define mmMC_HUB_RDREQ_MCDZ 0x854
+#define mmMC_HUB_RDREQ_SIP 0x855
+#define mmMC_HUB_RDREQ_GBL0 0x856
+#define mmMC_HUB_RDREQ_GBL1 0x857
+#define mmMC_HUB_RDREQ_SMU 0x858
+#define mmMC_HUB_RDREQ_SDMA0 0x859
+#define mmMC_HUB_RDREQ_HDP 0x85a
+#define mmMC_HUB_RDREQ_SDMA1 0x85b
+#define mmMC_HUB_RDREQ_RLC 0x85c
+#define mmMC_HUB_RDREQ_SEM 0x85d
+#define mmMC_HUB_RDREQ_VCE0 0x85e
+#define mmMC_HUB_RDREQ_UMC 0x85f
+#define mmMC_HUB_RDREQ_UVD 0x860
+#define mmMC_HUB_RDREQ_DMIF 0x862
+#define mmMC_HUB_RDREQ_MCIF 0x863
+#define mmMC_HUB_RDREQ_VMC 0x864
+#define mmMC_HUB_RDREQ_VCEU0 0x865
+#define mmMC_HUB_WDP_MCDW 0x866
+#define mmMC_HUB_WDP_MCDX 0x867
+#define mmMC_HUB_WDP_MCDY 0x868
+#define mmMC_HUB_WDP_MCDZ 0x869
+#define mmMC_HUB_WDP_SIP 0x86a
+#define mmMC_HUB_WDP_SDMA1 0x86b
+#define mmMC_HUB_WDP_SH0 0x86c
+#define mmMC_HUB_WDP_MCIF 0x86d
+#define mmMC_HUB_WDP_VCE0 0x86e
+#define mmMC_HUB_WDP_XDP 0x86f
+#define mmMC_HUB_WDP_IH 0x870
+#define mmMC_HUB_WDP_RLC 0x871
+#define mmMC_HUB_WDP_SEM 0x872
+#define mmMC_HUB_WDP_SMU 0x873
+#define mmMC_HUB_WDP_SH1 0x874
+#define mmMC_HUB_WDP_UMC 0x875
+#define mmMC_HUB_WDP_UVD 0x876
+#define mmMC_HUB_WDP_HDP 0x877
+#define mmMC_HUB_WDP_SDMA0 0x878
+#define mmMC_HUB_WRRET_MCDW 0x879
+#define mmMC_HUB_WRRET_MCDX 0x87a
+#define mmMC_HUB_WRRET_MCDY 0x87b
+#define mmMC_HUB_WRRET_MCDZ 0x87c
+#define mmMC_HUB_WDP_VCEU0 0x87d
+#define mmMC_HUB_WDP_XDMAM 0x87e
+#define mmMC_HUB_WDP_XDMA 0x87f
+#define mmMC_HUB_RDREQ_XDMAM 0x880
+#define mmMC_HUB_RDREQ_ACPG 0x881
+#define mmMC_HUB_RDREQ_ACPO 0x882
+#define mmMC_HUB_RDREQ_SAMMSP 0x883
+#define mmMC_HUB_RDREQ_VP8 0x884
+#define mmMC_HUB_RDREQ_VP8U 0x885
+#define mmMC_HUB_WDP_ACPG 0x886
+#define mmMC_HUB_WDP_ACPO 0x887
+#define mmMC_HUB_WDP_SAMMSP 0x888
+#define mmMC_HUB_WDP_VP8 0x889
+#define mmMC_HUB_WDP_VP8U 0x88a
+#define mmMC_HUB_RDREQ_ISP_SPM 0xde0
+#define mmMC_HUB_RDREQ_ISP_MPM 0xde1
+#define mmMC_HUB_RDREQ_ISP_CCPU 0xde2
+#define mmMC_HUB_WDP_ISP_SPM 0xde3
+#define mmMC_HUB_WDP_ISP_MPS 0xde4
+#define mmMC_HUB_WDP_ISP_MPM 0xde5
+#define mmMC_HUB_WDP_ISP_CCPU 0xde6
+#define mmMC_HUB_RDREQ_MCDS 0xde7
+#define mmMC_HUB_RDREQ_MCDT 0xde8
+#define mmMC_HUB_RDREQ_MCDU 0xde9
+#define mmMC_HUB_RDREQ_MCDV 0xdea
+#define mmMC_HUB_WDP_MCDS 0xdeb
+#define mmMC_HUB_WDP_MCDT 0xdec
+#define mmMC_HUB_WDP_MCDU 0xded
+#define mmMC_HUB_WDP_MCDV 0xdee
+#define mmMC_HUB_WRRET_MCDS 0xdef
+#define mmMC_HUB_WRRET_MCDT 0xdf0
+#define mmMC_HUB_WRRET_MCDU 0xdf1
+#define mmMC_HUB_WRRET_MCDV 0xdf2
+#define mmMC_HUB_WDP_CREDITS_MCDW 0xdf3
+#define mmMC_HUB_WDP_CREDITS_MCDX 0xdf4
+#define mmMC_HUB_WDP_CREDITS_MCDY 0xdf5
+#define mmMC_HUB_WDP_CREDITS_MCDZ 0xdf6
+#define mmMC_HUB_WDP_CREDITS_MCDS 0xdf7
+#define mmMC_HUB_WDP_CREDITS_MCDT 0xdf8
+#define mmMC_HUB_WDP_CREDITS_MCDU 0xdf9
+#define mmMC_HUB_WDP_CREDITS_MCDV 0xdfa
+#define mmMC_HUB_WDP_BP2 0xdfb
+#define mmMC_HUB_RDREQ_VCE1 0xdfc
+#define mmMC_HUB_RDREQ_VCEU1 0xdfd
+#define mmMC_HUB_WDP_VCE1 0xdfe
+#define mmMC_HUB_WDP_VCEU1 0xdff
+#define mmMC_RPB_CONF 0x94d
+#define mmMC_RPB_IF_CONF 0x94e
+#define mmMC_RPB_DBG1 0x94f
+#define mmMC_RPB_EFF_CNTL 0x950
+#define mmMC_RPB_ARB_CNTL 0x951
+#define mmMC_RPB_BIF_CNTL 0x952
+#define mmMC_RPB_WR_SWITCH_CNTL 0x953
+#define mmMC_RPB_WR_COMBINE_CNTL 0x954
+#define mmMC_RPB_RD_SWITCH_CNTL 0x955
+#define mmMC_RPB_CID_QUEUE_WR 0x956
+#define mmMC_RPB_CID_QUEUE_RD 0x957
+#define mmMC_RPB_PERF_COUNTER_CNTL 0x958
+#define mmMC_RPB_PERF_COUNTER_STATUS 0x959
+#define mmMC_RPB_CID_QUEUE_EX 0x95a
+#define mmMC_RPB_CID_QUEUE_EX_DATA 0x95b
+#define mmMC_RPB_TCI_CNTL 0x95c
+#define mmMC_RPB_TCI_CNTL2 0x95d
+#define mmMC_SHARED_CHMAP 0x801
+#define mmMC_SHARED_CHREMAP 0x802
+#define mmMC_RD_GRP_GFX 0x803
+#define mmMC_WR_GRP_GFX 0x804
+#define mmMC_RD_GRP_SYS 0x805
+#define mmMC_WR_GRP_SYS 0x806
+#define mmMC_RD_GRP_OTH 0x807
+#define mmMC_WR_GRP_OTH 0x808
+#define mmMC_VM_FB_LOCATION 0x809
+#define mmMC_VM_AGP_TOP 0x80a
+#define mmMC_VM_AGP_BOT 0x80b
+#define mmMC_VM_AGP_BASE 0x80c
+#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80d
+#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80e
+#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80f
+#define mmMC_VM_DC_WRITE_CNTL 0x810
+#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0x811
+#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0x812
+#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0x813
+#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0x814
+#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0x815
+#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0x816
+#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0x817
+#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0x818
+#define mmMC_VM_MX_L1_TLB_CNTL 0x819
+#define mmMC_VM_FB_OFFSET 0x81a
+#define mmMC_VM_STEERING 0x81b
+#define mmMC_SHARED_CHREMAP2 0x81c
+#define mmMC_SHARED_VF_ENABLE 0x81d
+#define mmMC_SHARED_VIRT_RESET_REQ 0x81e
+#define mmMC_SHARED_ACTIVE_FCN_ID 0x81f
+#define mmMC_CONFIG_MCD 0x828
+#define mmMC_CG_CONFIG_MCD 0x829
+#define mmMC_MEM_POWER_LS 0x82a
+#define mmMC_SHARED_BLACKOUT_CNTL 0x82b
+#define mmMC_VM_MB_L1_TLB0_DEBUG 0x891
+#define mmMC_VM_MB_L1_TLB1_DEBUG 0x892
+#define mmMC_VM_MB_L1_TLB2_DEBUG 0x893
+#define mmMC_VM_MB_L1_TLB0_STATUS 0x895
+#define mmMC_VM_MB_L1_TLB1_STATUS 0x896
+#define mmMC_VM_MB_L1_TLB2_STATUS 0x897
+#define mmMC_VM_MB_L2ARBITER_L2_CREDITS 0x8a1
+#define mmMC_VM_MB_L1_TLB3_DEBUG 0x8a5
+#define mmMC_VM_MB_L1_TLB3_STATUS 0x8a6
+#define mmMC_VM_MD_L1_TLB0_DEBUG 0x998
+#define mmMC_VM_MD_L1_TLB1_DEBUG 0x999
+#define mmMC_VM_MD_L1_TLB2_DEBUG 0x99a
+#define mmMC_VM_MD_L1_TLB0_STATUS 0x99b
+#define mmMC_VM_MD_L1_TLB1_STATUS 0x99c
+#define mmMC_VM_MD_L1_TLB2_STATUS 0x99d
+#define mmMC_VM_MD_L2ARBITER_L2_CREDITS 0x9a4
+#define mmMC_VM_MD_L1_TLB3_DEBUG 0x9a7
+#define mmMC_VM_MD_L1_TLB3_STATUS 0x9a8
+#define mmMC_XPB_RTR_SRC_APRTR0 0x8cd
+#define mmMC_XPB_RTR_SRC_APRTR1 0x8ce
+#define mmMC_XPB_RTR_SRC_APRTR2 0x8cf
+#define mmMC_XPB_RTR_SRC_APRTR3 0x8d0
+#define mmMC_XPB_RTR_SRC_APRTR4 0x8d1
+#define mmMC_XPB_RTR_SRC_APRTR5 0x8d2
+#define mmMC_XPB_RTR_SRC_APRTR6 0x8d3
+#define mmMC_XPB_RTR_SRC_APRTR7 0x8d4
+#define mmMC_XPB_RTR_SRC_APRTR8 0x8d5
+#define mmMC_XPB_RTR_SRC_APRTR9 0x8d6
+#define mmMC_XPB_XDMA_RTR_SRC_APRTR0 0x8d7
+#define mmMC_XPB_XDMA_RTR_SRC_APRTR1 0x8d8
+#define mmMC_XPB_XDMA_RTR_SRC_APRTR2 0x8d9
+#define mmMC_XPB_XDMA_RTR_SRC_APRTR3 0x8da
+#define mmMC_XPB_RTR_DEST_MAP0 0x8db
+#define mmMC_XPB_RTR_DEST_MAP1 0x8dc
+#define mmMC_XPB_RTR_DEST_MAP2 0x8dd
+#define mmMC_XPB_RTR_DEST_MAP3 0x8de
+#define mmMC_XPB_RTR_DEST_MAP4 0x8df
+#define mmMC_XPB_RTR_DEST_MAP5 0x8e0
+#define mmMC_XPB_RTR_DEST_MAP6 0x8e1
+#define mmMC_XPB_RTR_DEST_MAP7 0x8e2
+#define mmMC_XPB_RTR_DEST_MAP8 0x8e3
+#define mmMC_XPB_RTR_DEST_MAP9 0x8e4
+#define mmMC_XPB_XDMA_RTR_DEST_MAP0 0x8e5
+#define mmMC_XPB_XDMA_RTR_DEST_MAP1 0x8e6
+#define mmMC_XPB_XDMA_RTR_DEST_MAP2 0x8e7
+#define mmMC_XPB_XDMA_RTR_DEST_MAP3 0x8e8
+#define mmMC_XPB_CLG_CFG0 0x8e9
+#define mmMC_XPB_CLG_CFG1 0x8ea
+#define mmMC_XPB_CLG_CFG2 0x8eb
+#define mmMC_XPB_CLG_CFG3 0x8ec
+#define mmMC_XPB_CLG_CFG4 0x8ed
+#define mmMC_XPB_CLG_CFG5 0x8ee
+#define mmMC_XPB_CLG_CFG6 0x8ef
+#define mmMC_XPB_CLG_CFG7 0x8f0
+#define mmMC_XPB_CLG_CFG8 0x8f1
+#define mmMC_XPB_CLG_CFG9 0x8f2
+#define mmMC_XPB_CLG_CFG10 0x8f3
+#define mmMC_XPB_CLG_CFG11 0x8f4
+#define mmMC_XPB_CLG_CFG12 0x8f5
+#define mmMC_XPB_CLG_CFG13 0x8f6
+#define mmMC_XPB_CLG_CFG14 0x8f7
+#define mmMC_XPB_CLG_CFG15 0x8f8
+#define mmMC_XPB_CLG_CFG16 0x8f9
+#define mmMC_XPB_CLG_CFG17 0x8fa
+#define mmMC_XPB_CLG_CFG18 0x8fb
+#define mmMC_XPB_CLG_CFG19 0x8fc
+#define mmMC_XPB_CLG_EXTRA 0x8fd
+#define mmMC_XPB_LB_ADDR 0x8fe
+#define mmMC_XPB_UNC_THRESH_HST 0x8ff
+#define mmMC_XPB_UNC_THRESH_SID 0x900
+#define mmMC_XPB_WCB_STS 0x901
+#define mmMC_XPB_WCB_CFG 0x902
+#define mmMC_XPB_P2P_BAR_CFG 0x903
+#define mmMC_XPB_P2P_BAR0 0x904
+#define mmMC_XPB_P2P_BAR1 0x905
+#define mmMC_XPB_P2P_BAR2 0x906
+#define mmMC_XPB_P2P_BAR3 0x907
+#define mmMC_XPB_P2P_BAR4 0x908
+#define mmMC_XPB_P2P_BAR5 0x909
+#define mmMC_XPB_P2P_BAR6 0x90a
+#define mmMC_XPB_P2P_BAR7 0x90b
+#define mmMC_XPB_P2P_BAR_SETUP 0x90c
+#define mmMC_XPB_P2P_BAR_DEBUG 0x90d
+#define mmMC_XPB_P2P_BAR_DELTA_ABOVE 0x90e
+#define mmMC_XPB_P2P_BAR_DELTA_BELOW 0x90f
+#define mmMC_XPB_PEER_SYS_BAR0 0x910
+#define mmMC_XPB_PEER_SYS_BAR1 0x911
+#define mmMC_XPB_PEER_SYS_BAR2 0x912
+#define mmMC_XPB_PEER_SYS_BAR3 0x913
+#define mmMC_XPB_PEER_SYS_BAR4 0x914
+#define mmMC_XPB_PEER_SYS_BAR5 0x915
+#define mmMC_XPB_PEER_SYS_BAR6 0x916
+#define mmMC_XPB_PEER_SYS_BAR7 0x917
+#define mmMC_XPB_PEER_SYS_BAR8 0x918
+#define mmMC_XPB_PEER_SYS_BAR9 0x919
+#define mmMC_XPB_XDMA_PEER_SYS_BAR0 0x91a
+#define mmMC_XPB_XDMA_PEER_SYS_BAR1 0x91b
+#define mmMC_XPB_XDMA_PEER_SYS_BAR2 0x91c
+#define mmMC_XPB_XDMA_PEER_SYS_BAR3 0x91d
+#define mmMC_XPB_CLK_GAT 0x91e
+#define mmMC_XPB_INTF_CFG 0x91f
+#define mmMC_XPB_INTF_STS 0x920
+#define mmMC_XPB_PIPE_STS 0x921
+#define mmMC_XPB_SUB_CTRL 0x922
+#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0x923
+#define mmMC_XPB_PERF_KNOBS 0x924
+#define mmMC_XPB_STICKY 0x925
+#define mmMC_XPB_STICKY_W1C 0x926
+#define mmMC_XPB_MISC_CFG 0x927
+#define mmMC_XPB_CLG_CFG20 0x928
+#define mmMC_XPB_CLG_CFG21 0x929
+#define mmMC_XPB_CLG_CFG22 0x92a
+#define mmMC_XPB_CLG_CFG23 0x92b
+#define mmMC_XPB_CLG_CFG24 0x92c
+#define mmMC_XPB_CLG_CFG25 0x92d
+#define mmMC_XPB_CLG_CFG26 0x92e
+#define mmMC_XPB_CLG_CFG27 0x92f
+#define mmMC_XPB_CLG_CFG28 0x930
+#define mmMC_XPB_CLG_CFG29 0x931
+#define mmMC_XPB_CLG_CFG30 0x932
+#define mmMC_XPB_CLG_CFG31 0x933
+#define mmMC_XPB_INTF_CFG2 0x934
+#define mmMC_XPB_CLG_EXTRA_RD 0x935
+#define mmMC_XPB_CLG_CFG32 0x936
+#define mmMC_XPB_CLG_CFG33 0x937
+#define mmMC_XPB_CLG_CFG34 0x938
+#define mmMC_XPB_CLG_CFG35 0x939
+#define mmMC_XPB_CLG_CFG36 0x93a
+#define mmMC_XBAR_ADDR_DEC 0xc80
+#define mmMC_XBAR_REMOTE 0xc81
+#define mmMC_XBAR_WRREQ_CREDIT 0xc82
+#define mmMC_XBAR_RDREQ_CREDIT 0xc83
+#define mmMC_XBAR_RDREQ_PRI_CREDIT 0xc84
+#define mmMC_XBAR_WRRET_CREDIT1 0xc85
+#define mmMC_XBAR_WRRET_CREDIT2 0xc86
+#define mmMC_XBAR_RDRET_CREDIT1 0xc87
+#define mmMC_XBAR_RDRET_CREDIT2 0xc88
+#define mmMC_XBAR_RDRET_PRI_CREDIT1 0xc89
+#define mmMC_XBAR_RDRET_PRI_CREDIT2 0xc8a
+#define mmMC_XBAR_CHTRIREMAP 0xc8b
+#define mmMC_XBAR_TWOCHAN 0xc8c
+#define mmMC_XBAR_ARB 0xc8d
+#define mmMC_XBAR_ARB_MAX_BURST 0xc8e
+#define mmMC_XBAR_FIFO_MON_CNTL0 0xc8f
+#define mmMC_XBAR_FIFO_MON_CNTL1 0xc90
+#define mmMC_XBAR_FIFO_MON_CNTL2 0xc91
+#define mmMC_XBAR_FIFO_MON_RSLT0 0xc92
+#define mmMC_XBAR_FIFO_MON_RSLT1 0xc93
+#define mmMC_XBAR_FIFO_MON_RSLT2 0xc94
+#define mmMC_XBAR_FIFO_MON_RSLT3 0xc95
+#define mmMC_XBAR_FIFO_MON_MAX_THSH 0xc96
+#define mmMC_XBAR_SPARE0 0xc97
+#define mmMC_XBAR_SPARE1 0xc98
+#define mmMC_CITF_PERFCOUNTER_LO 0x7a0
+#define mmMC_HUB_PERFCOUNTER_LO 0x7a1
+#define mmMC_RPB_PERFCOUNTER_LO 0x7a2
+#define mmMC_MCBVM_PERFCOUNTER_LO 0x7a3
+#define mmMC_MCDVM_PERFCOUNTER_LO 0x7a4
+#define mmMC_VM_L2_PERFCOUNTER_LO 0x7a5
+#define mmMC_ARB_PERFCOUNTER_LO 0x7a6
+#define mmATC_PERFCOUNTER_LO 0x7a7
+#define mmMC_CITF_PERFCOUNTER_HI 0x7a8
+#define mmMC_HUB_PERFCOUNTER_HI 0x7a9
+#define mmMC_MCBVM_PERFCOUNTER_HI 0x7aa
+#define mmMC_MCDVM_PERFCOUNTER_HI 0x7ab
+#define mmMC_RPB_PERFCOUNTER_HI 0x7ac
+#define mmMC_VM_L2_PERFCOUNTER_HI 0x7ad
+#define mmMC_ARB_PERFCOUNTER_HI 0x7ae
+#define mmATC_PERFCOUNTER_HI 0x7af
+#define mmMC_CITF_PERFCOUNTER0_CFG 0x7b0
+#define mmMC_CITF_PERFCOUNTER1_CFG 0x7b1
+#define mmMC_CITF_PERFCOUNTER2_CFG 0x7b2
+#define mmMC_CITF_PERFCOUNTER3_CFG 0x7b3
+#define mmMC_HUB_PERFCOUNTER0_CFG 0x7b4
+#define mmMC_HUB_PERFCOUNTER1_CFG 0x7b5
+#define mmMC_HUB_PERFCOUNTER2_CFG 0x7b6
+#define mmMC_HUB_PERFCOUNTER3_CFG 0x7b7
+#define mmMC_RPB_PERFCOUNTER0_CFG 0x7b8
+#define mmMC_RPB_PERFCOUNTER1_CFG 0x7b9
+#define mmMC_RPB_PERFCOUNTER2_CFG 0x7ba
+#define mmMC_RPB_PERFCOUNTER3_CFG 0x7bb
+#define mmMC_ARB_PERFCOUNTER0_CFG 0x7bc
+#define mmMC_ARB_PERFCOUNTER1_CFG 0x7bd
+#define mmMC_ARB_PERFCOUNTER2_CFG 0x7be
+#define mmMC_ARB_PERFCOUNTER3_CFG 0x7bf
+#define mmMC_MCBVM_PERFCOUNTER0_CFG 0x7c0
+#define mmMC_MCBVM_PERFCOUNTER1_CFG 0x7c1
+#define mmMC_MCBVM_PERFCOUNTER2_CFG 0x7c2
+#define mmMC_MCBVM_PERFCOUNTER3_CFG 0x7c3
+#define mmMC_MCDVM_PERFCOUNTER0_CFG 0x7c4
+#define mmMC_MCDVM_PERFCOUNTER1_CFG 0x7c5
+#define mmMC_MCDVM_PERFCOUNTER2_CFG 0x7c6
+#define mmMC_MCDVM_PERFCOUNTER3_CFG 0x7c7
+#define mmATC_PERFCOUNTER0_CFG 0x7c8
+#define mmATC_PERFCOUNTER1_CFG 0x7c9
+#define mmATC_PERFCOUNTER2_CFG 0x7ca
+#define mmATC_PERFCOUNTER3_CFG 0x7cb
+#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x7cc
+#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x7cd
+#define mmMC_CITF_PERFCOUNTER_RSLT_CNTL 0x7ce
+#define mmMC_HUB_PERFCOUNTER_RSLT_CNTL 0x7cf
+#define mmMC_RPB_PERFCOUNTER_RSLT_CNTL 0x7d0
+#define mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL 0x7d1
+#define mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL 0x7d2
+#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x7d3
+#define mmMC_ARB_PERFCOUNTER_RSLT_CNTL 0x7d4
+#define mmATC_PERFCOUNTER_RSLT_CNTL 0x7d5
+#define mmCHUB_ATC_PERFCOUNTER_LO 0x7d6
+#define mmCHUB_ATC_PERFCOUNTER_HI 0x7d7
+#define mmCHUB_ATC_PERFCOUNTER0_CFG 0x7d8
+#define mmCHUB_ATC_PERFCOUNTER1_CFG 0x7d9
+#define mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL 0x7da
+#define mmMC_GRUB_PERFCOUNTER_LO 0x7e4
+#define mmMC_GRUB_PERFCOUNTER_HI 0x7e5
+#define mmMC_GRUB_PERFCOUNTER0_CFG 0x7e6
+#define mmMC_GRUB_PERFCOUNTER1_CFG 0x7e7
+#define mmMC_GRUB_PERFCOUNTER_RSLT_CNTL 0x7e8
+#define mmATC_VM_APERTURE0_LOW_ADDR 0xcc0
+#define mmATC_VM_APERTURE1_LOW_ADDR 0xcc1
+#define mmATC_VM_APERTURE0_HIGH_ADDR 0xcc2
+#define mmATC_VM_APERTURE1_HIGH_ADDR 0xcc3
+#define mmATC_VM_APERTURE0_CNTL 0xcc4
+#define mmATC_VM_APERTURE1_CNTL 0xcc5
+#define mmATC_VM_APERTURE0_CNTL2 0xcc6
+#define mmATC_VM_APERTURE1_CNTL2 0xcc7
+#define mmATC_ATS_CNTL 0xcc9
+#define mmATC_ATS_DEBUG 0xcca
+#define mmATC_ATS_FAULT_DEBUG 0xccb
+#define mmATC_ATS_STATUS 0xccc
+#define mmATC_ATS_FAULT_CNTL 0xccd
+#define mmATC_ATS_FAULT_STATUS_INFO 0xcce
+#define mmATC_ATS_FAULT_STATUS_ADDR 0xccf
+#define mmATC_ATS_DEFAULT_PAGE_LOW 0xcd0
+#define mmATC_ATS_DEFAULT_PAGE_CNTL 0xcd1
+#define mmATC_ATS_FAULT_STATUS_INFO2 0xcd2
+#define mmATC_MISC_CG 0xcd4
+#define mmATC_L2_CNTL 0xcd5
+#define mmATC_L2_CNTL2 0xcd6
+#define mmATC_L2_DEBUG 0xcd7
+#define mmATC_L2_DEBUG2 0xcd8
+#define mmATC_L2_CACHE_DATA0 0xcd9
+#define mmATC_L2_CACHE_DATA1 0xcda
+#define mmATC_L2_CACHE_DATA2 0xcdb
+#define mmATC_L1_CNTL 0xcdc
+#define mmATC_L1_ADDRESS_OFFSET 0xcdd
+#define mmATC_L1RD_DEBUG_TLB 0xcde
+#define mmATC_L1WR_DEBUG_TLB 0xcdf
+#define mmATC_L1RD_STATUS 0xce0
+#define mmATC_L1WR_STATUS 0xce1
+#define mmATC_L1RD_DEBUG2_TLB 0xce2
+#define mmATC_L1WR_DEBUG2_TLB 0xce3
+#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0xce6
+#define mmATC_VMID0_PASID_MAPPING 0xce7
+#define mmATC_VMID1_PASID_MAPPING 0xce8
+#define mmATC_VMID2_PASID_MAPPING 0xce9
+#define mmATC_VMID3_PASID_MAPPING 0xcea
+#define mmATC_VMID4_PASID_MAPPING 0xceb
+#define mmATC_VMID5_PASID_MAPPING 0xcec
+#define mmATC_VMID6_PASID_MAPPING 0xced
+#define mmATC_VMID7_PASID_MAPPING 0xcee
+#define mmATC_VMID8_PASID_MAPPING 0xcef
+#define mmATC_VMID9_PASID_MAPPING 0xcf0
+#define mmATC_VMID10_PASID_MAPPING 0xcf1
+#define mmATC_VMID11_PASID_MAPPING 0xcf2
+#define mmATC_VMID12_PASID_MAPPING 0xcf3
+#define mmATC_VMID13_PASID_MAPPING 0xcf4
+#define mmATC_VMID14_PASID_MAPPING 0xcf5
+#define mmATC_VMID15_PASID_MAPPING 0xcf6
+#define mmATC_ATS_VMID_STATUS 0xd07
+#define mmATC_ATS_SMU_STATUS 0xd08
+#define mmATC_L2_CNTL3 0xd09
+#define mmATC_L2_STATUS 0xd0a
+#define mmATC_L2_STATUS2 0xd0b
+#define mmGMCON_RENG_RAM_INDEX 0xd40
+#define mmGMCON_RENG_RAM_DATA 0xd41
+#define mmGMCON_RENG_EXECUTE 0xd42
+#define mmGMCON_MISC 0xd43
+#define mmGMCON_MISC2 0xd44
+#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 0xd45
+#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 0xd46
+#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 0xd47
+#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 0xd48
+#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 0xd49
+#define mmGMCON_PERF_MON_CNTL0 0xd4a
+#define mmGMCON_PERF_MON_CNTL1 0xd4b
+#define mmGMCON_PERF_MON_RSLT0 0xd4c
+#define mmGMCON_PERF_MON_RSLT1 0xd4d
+#define mmGMCON_PGFSM_CONFIG 0xd4e
+#define mmGMCON_PGFSM_WRITE 0xd4f
+#define mmGMCON_PGFSM_READ 0xd50
+#define mmGMCON_MISC3 0xd51
+#define mmGMCON_MASK 0xd52
+#define mmGMCON_LPT_TARGET 0xd53
+#define mmGMCON_DEBUG 0xd5f
+#define mmVM_L2_CNTL 0x500
+#define mmVM_L2_CNTL2 0x501
+#define mmVM_L2_CNTL3 0x502
+#define mmVM_L2_STATUS 0x503
+#define mmVM_CONTEXT0_CNTL 0x504
+#define mmVM_CONTEXT1_CNTL 0x505
+#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x506
+#define mmVM_DUMMY_PAGE_FAULT_ADDR 0x507
+#define mmVM_CONTEXT0_CNTL2 0x50c
+#define mmVM_CONTEXT1_CNTL2 0x50d
+#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x50e
+#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x50f
+#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x510
+#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x511
+#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x512
+#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x513
+#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x514
+#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x515
+#define mmVM_INVALIDATE_REQUEST 0x51e
+#define mmVM_INVALIDATE_RESPONSE 0x51f
+#define mmVM_PRT_APERTURE0_LOW_ADDR 0x52c
+#define mmVM_PRT_APERTURE1_LOW_ADDR 0x52d
+#define mmVM_PRT_APERTURE2_LOW_ADDR 0x52e
+#define mmVM_PRT_APERTURE3_LOW_ADDR 0x52f
+#define mmVM_PRT_APERTURE0_HIGH_ADDR 0x530
+#define mmVM_PRT_APERTURE1_HIGH_ADDR 0x531
+#define mmVM_PRT_APERTURE2_HIGH_ADDR 0x532
+#define mmVM_PRT_APERTURE3_HIGH_ADDR 0x533
+#define mmVM_PRT_CNTL 0x534
+#define mmVM_CONTEXTS_DISABLE 0x535
+#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0x536
+#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0x537
+#define mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT 0x538
+#define mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x539
+#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0x53e
+#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0x53f
+#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x546
+#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x547
+#define mmVM_FAULT_CLIENT_ID 0x54e
+#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f
+#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x550
+#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x551
+#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x552
+#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x553
+#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x554
+#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x555
+#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x556
+#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0x557
+#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0x558
+#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0x55f
+#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0x560
+#define mmVM_DEBUG 0x56f
+#define mmVM_L2_CG 0x570
+#define mmVM_L2_BANK_SELECT_MASKA 0x572
+#define mmVM_L2_BANK_SELECT_MASKB 0x573
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0x575
+#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0x576
+#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0x577
+#define mmVM_L2_CNTL4 0x578
+#define mmVM_L2_BANK_SELECT_RESERVED_CID 0x579
+#define mmMC_VM_FB_SIZE_OFFSET_VF0 0xf980
+#define mmMC_VM_FB_SIZE_OFFSET_VF1 0xf981
+#define mmMC_VM_FB_SIZE_OFFSET_VF2 0xf982
+#define mmMC_VM_FB_SIZE_OFFSET_VF3 0xf983
+#define mmMC_VM_FB_SIZE_OFFSET_VF4 0xf984
+#define mmMC_VM_FB_SIZE_OFFSET_VF5 0xf985
+#define mmMC_VM_FB_SIZE_OFFSET_VF6 0xf986
+#define mmMC_VM_FB_SIZE_OFFSET_VF7 0xf987
+#define mmMC_VM_FB_SIZE_OFFSET_VF8 0xf988
+#define mmMC_VM_FB_SIZE_OFFSET_VF9 0xf989
+#define mmMC_VM_FB_SIZE_OFFSET_VF10 0xf98a
+#define mmMC_VM_FB_SIZE_OFFSET_VF11 0xf98b
+#define mmMC_VM_FB_SIZE_OFFSET_VF12 0xf98c
+#define mmMC_VM_FB_SIZE_OFFSET_VF13 0xf98d
+#define mmMC_VM_FB_SIZE_OFFSET_VF14 0xf98e
+#define mmMC_VM_FB_SIZE_OFFSET_VF15 0xf98f
+#define mmMC_VM_NB_MMIOBASE 0xf990
+#define mmMC_VM_NB_MMIOLIMIT 0xf991
+#define mmMC_VM_NB_PCI_CTRL 0xf992
+#define mmMC_VM_NB_PCI_ARB 0xf993
+#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0xf994
+#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0xf995
+#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0xf996
+#define mmMC_VM_NB_TOP_OF_DRAM3 0xf997
+#define mmMC_VM_MARC_BASE_LO_0 0xf998
+#define mmMC_VM_MARC_BASE_LO_1 0xf99e
+#define mmMC_VM_MARC_BASE_LO_2 0xf9a4
+#define mmMC_VM_MARC_BASE_LO_3 0xf9aa
+#define mmMC_VM_MARC_BASE_HI_0 0xf999
+#define mmMC_VM_MARC_BASE_HI_1 0xf99f
+#define mmMC_VM_MARC_BASE_HI_2 0xf9a5
+#define mmMC_VM_MARC_BASE_HI_3 0xf9ab
+#define mmMC_VM_MARC_RELOC_LO_0 0xf99a
+#define mmMC_VM_MARC_RELOC_LO_1 0xf9a0
+#define mmMC_VM_MARC_RELOC_LO_2 0xf9a6
+#define mmMC_VM_MARC_RELOC_LO_3 0xf9ac
+#define mmMC_VM_MARC_RELOC_HI_0 0xf99b
+#define mmMC_VM_MARC_RELOC_HI_1 0xf9a1
+#define mmMC_VM_MARC_RELOC_HI_2 0xf9a7
+#define mmMC_VM_MARC_RELOC_HI_3 0xf9ad
+#define mmMC_VM_MARC_LEN_LO_0 0xf99c
+#define mmMC_VM_MARC_LEN_LO_1 0xf9a2
+#define mmMC_VM_MARC_LEN_LO_2 0xf9a8
+#define mmMC_VM_MARC_LEN_LO_3 0xf9ae
+#define mmMC_VM_MARC_LEN_HI_0 0xf99d
+#define mmMC_VM_MARC_LEN_HI_1 0xf9a3
+#define mmMC_VM_MARC_LEN_HI_2 0xf9a9
+#define mmMC_VM_MARC_LEN_HI_3 0xf9af
+#define mmMC_VM_MARC_CNTL 0xf9b0
+#define mmMC_ARB_HARSH_EN_RD 0xdc0
+#define mmMC_ARB_HARSH_EN_WR 0xdc1
+#define mmMC_ARB_HARSH_TX_HI0_RD 0xdc2
+#define mmMC_ARB_HARSH_TX_HI0_WR 0xdc3
+#define mmMC_ARB_HARSH_TX_HI1_RD 0xdc4
+#define mmMC_ARB_HARSH_TX_HI1_WR 0xdc5
+#define mmMC_ARB_HARSH_TX_LO0_RD 0xdc6
+#define mmMC_ARB_HARSH_TX_LO0_WR 0xdc7
+#define mmMC_ARB_HARSH_TX_LO1_RD 0xdc8
+#define mmMC_ARB_HARSH_TX_LO1_WR 0xdc9
+#define mmMC_ARB_HARSH_BWPERIOD0_RD 0xdca
+#define mmMC_ARB_HARSH_BWPERIOD0_WR 0xdcb
+#define mmMC_ARB_HARSH_BWPERIOD1_RD 0xdcc
+#define mmMC_ARB_HARSH_BWPERIOD1_WR 0xdcd
+#define mmMC_ARB_HARSH_BWCNT0_RD 0xdce
+#define mmMC_ARB_HARSH_BWCNT0_WR 0xdcf
+#define mmMC_ARB_HARSH_BWCNT1_RD 0xdd0
+#define mmMC_ARB_HARSH_BWCNT1_WR 0xdd1
+#define mmMC_ARB_HARSH_SAT0_RD 0xdd2
+#define mmMC_ARB_HARSH_SAT0_WR 0xdd3
+#define mmMC_ARB_HARSH_SAT1_RD 0xdd4
+#define mmMC_ARB_HARSH_SAT1_WR 0xdd5
+#define mmMC_ARB_HARSH_CTL_RD 0xdd6
+#define mmMC_ARB_HARSH_CTL_WR 0xdd7
+#define mmMC_ARB_GRUB_PRIORITY1_RD 0xdd8
+#define mmMC_ARB_GRUB_PRIORITY1_WR 0xdd9
+#define mmMC_ARB_GRUB_PRIORITY2_RD 0xdda
+#define mmMC_ARB_GRUB_PRIORITY2_WR 0xddb
+#define mmMC_FUS_DRAM0_CS0_BASE 0xa05
+#define mmMC_FUS_DRAM1_CS0_BASE 0xa06
+#define mmMC_FUS_DRAM0_CS1_BASE 0xa07
+#define mmMC_FUS_DRAM1_CS1_BASE 0xa08
+#define mmMC_FUS_DRAM0_CS2_BASE 0xa09
+#define mmMC_FUS_DRAM1_CS2_BASE 0xa0a
+#define mmMC_FUS_DRAM0_CS3_BASE 0xa0b
+#define mmMC_FUS_DRAM1_CS3_BASE 0xa0c
+#define mmMC_FUS_DRAM0_CS01_MASK 0xa0d
+#define mmMC_FUS_DRAM1_CS01_MASK 0xa0e
+#define mmMC_FUS_DRAM0_CS23_MASK 0xa0f
+#define mmMC_FUS_DRAM1_CS23_MASK 0xa10
+#define mmMC_FUS_DRAM0_BANK_ADDR_MAPPING 0xa11
+#define mmMC_FUS_DRAM1_BANK_ADDR_MAPPING 0xa12
+#define mmMC_FUS_DRAM0_CTL_BASE 0xa13
+#define mmMC_FUS_DRAM1_CTL_BASE 0xa14
+#define mmMC_FUS_DRAM0_CTL_LIMIT 0xa15
+#define mmMC_FUS_DRAM1_CTL_LIMIT 0xa16
+#define mmMC_FUS_DRAM_CTL_HIGH_01 0xa17
+#define mmMC_FUS_DRAM_CTL_HIGH_23 0xa18
+#define mmMC_FUS_DRAM_MODE 0xa19
+#define mmMC_FUS_DRAM_APER_BASE 0xa1a
+#define mmMC_FUS_DRAM_APER_TOP 0xa1b
+#define mmMC_FUS_DRAM_APER_DEF 0xa1e
+#define mmMC_FUS_ARB_GARLIC_ISOC_PRI 0xa1f
+#define mmMC_FUS_ARB_GARLIC_CNTL 0xa20
+#define mmMC_FUS_ARB_GARLIC_WR_PRI 0xa21
+#define mmMC_FUS_ARB_GARLIC_WR_PRI2 0xa22
+#define mmMC_CG_DATAPORT 0xa32
+#define mmMC_GRUB_PROBE_MAP 0xa33
+#define mmMC_GRUB_POST_PROBE_DELAY 0xa34
+#define mmMC_GRUB_PROBE_CREDITS 0xa35
+#define mmMC_GRUB_FEATURES 0xa36
+#define mmMC_GRUB_TX_CREDITS 0xa37
+#define mmMC_GRUB_TCB_INDEX 0xa38
+#define mmMC_GRUB_TCB_DATA_LO 0xa39
+#define mmMC_GRUB_TCB_DATA_HI 0xa3a
+#define mmMCIF_WB_BUFMGR_SW_CONTROL 0x5e78
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x5e78
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x5eb8
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0x5ef8
+#define mmMCIF_WB_BUFMGR_CUR_LINE_R 0x5e79
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x5e79
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x5eb9
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0x5ef9
+#define mmMCIF_WB_BUFMGR_STATUS 0x5e7a
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x5e7a
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x5eba
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0x5efa
+#define mmMCIF_WB_BUF_PITCH 0x5e7b
+#define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x5e7b
+#define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x5ebb
+#define mmMCIF_WB2_MCIF_WB_BUF_PITCH 0x5efb
+#define mmMCIF_WB_BUF_1_STATUS 0x5e7c
+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x5e7c
+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x5ebc
+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0x5efc
+#define mmMCIF_WB_BUF_1_STATUS2 0x5e7d
+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x5e7d
+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x5ebd
+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0x5efd
+#define mmMCIF_WB_BUF_2_STATUS 0x5e7e
+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x5e7e
+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x5ebe
+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0x5efe
+#define mmMCIF_WB_BUF_2_STATUS2 0x5e7f
+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x5e7f
+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x5ebf
+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0x5eff
+#define mmMCIF_WB_BUF_3_STATUS 0x5e80
+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x5e80
+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x5ec0
+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0x5f00
+#define mmMCIF_WB_BUF_3_STATUS2 0x5e81
+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x5e81
+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x5ec1
+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0x5f01
+#define mmMCIF_WB_BUF_4_STATUS 0x5e82
+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x5e82
+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x5ec2
+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0x5f02
+#define mmMCIF_WB_BUF_4_STATUS2 0x5e83
+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x5e83
+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x5ec3
+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0x5f03
+#define mmMCIF_WB_ARBITRATION_CONTROL 0x5e84
+#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x5e84
+#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x5ec4
+#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0x5f04
+#define mmMCIF_WB_URGENCY_WATERMARK 0x5e85
+#define mmMCIF_WB0_MCIF_WB_URGENCY_WATERMARK 0x5e85
+#define mmMCIF_WB1_MCIF_WB_URGENCY_WATERMARK 0x5ec5
+#define mmMCIF_WB2_MCIF_WB_URGENCY_WATERMARK 0x5f05
+#define mmMCIF_WB_TEST_DEBUG_INDEX 0x5e86
+#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX 0x5e86
+#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX 0x5ec6
+#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX 0x5f06
+#define mmMCIF_WB_TEST_DEBUG_DATA 0x5e87
+#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA 0x5e87
+#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA 0x5ec7
+#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA 0x5f07
+#define mmMCIF_WB_BUF_1_ADDR_Y 0x5e88
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x5e88
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x5ec8
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0x5f08
+#define mmMCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5e89
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5e89
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5ec9
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5f09
+#define mmMCIF_WB_BUF_1_ADDR_C 0x5e8a
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x5e8a
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x5eca
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0x5f0a
+#define mmMCIF_WB_BUF_1_ADDR_C_OFFSET 0x5e8b
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5e8b
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5ecb
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5f0b
+#define mmMCIF_WB_BUF_2_ADDR_Y 0x5e8c
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x5e8c
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x5ecc
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0x5f0c
+#define mmMCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5e8d
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5e8d
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5ecd
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5f0d
+#define mmMCIF_WB_BUF_2_ADDR_C 0x5e8e
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x5e8e
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x5ece
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0x5f0e
+#define mmMCIF_WB_BUF_2_ADDR_C_OFFSET 0x5e8f
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5e8f
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5ecf
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5f0f
+#define mmMCIF_WB_BUF_3_ADDR_Y 0x5e90
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x5e90
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x5ed0
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0x5f10
+#define mmMCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5e91
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5e91
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5ed1
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5f11
+#define mmMCIF_WB_BUF_3_ADDR_C 0x5e92
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x5e92
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x5ed2
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0x5f12
+#define mmMCIF_WB_BUF_3_ADDR_C_OFFSET 0x5e93
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5e93
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5ed3
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5f13
+#define mmMCIF_WB_BUF_4_ADDR_Y 0x5e94
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x5e94
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x5ed4
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0x5f14
+#define mmMCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5e95
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5e95
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5ed5
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5f15
+#define mmMCIF_WB_BUF_4_ADDR_C 0x5e96
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x5e96
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x5ed6
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0x5f16
+#define mmMCIF_WB_BUF_4_ADDR_C_OFFSET 0x5e97
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5e97
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5ed7
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5f17
+#define mmMCIF_WB_BUFMGR_VCE_CONTROL 0x5e98
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x5e98
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x5ed8
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0x5f18
+#define mmMCIF_WB_HVVMID_CONTROL 0x5e99
+#define mmMCIF_WB0_MCIF_WB_HVVMID_CONTROL 0x5e99
+#define mmMCIF_WB1_MCIF_WB_HVVMID_CONTROL 0x5ed9
+#define mmMCIF_WB2_MCIF_WB_HVVMID_CONTROL 0x5f19
+
+#endif /* GMC_8_2_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_enum.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_enum.h
new file mode 100644
index 000000000000..bc18e4d1f20e
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_enum.h
@@ -0,0 +1,1068 @@
+/*
+ * GMC_8_2 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GMC_8_2_ENUM_H
+#define GMC_8_2_ENUM_H
+
+typedef enum DebugBlockId {
+ DBG_BLOCK_ID_RESERVED = 0x0,
+ DBG_BLOCK_ID_DBG = 0x1,
+ DBG_BLOCK_ID_VMC = 0x2,
+ DBG_BLOCK_ID_PDMA = 0x3,
+ DBG_BLOCK_ID_CG = 0x4,
+ DBG_BLOCK_ID_SRBM = 0x5,
+ DBG_BLOCK_ID_GRBM = 0x6,
+ DBG_BLOCK_ID_RLC = 0x7,
+ DBG_BLOCK_ID_CSC = 0x8,
+ DBG_BLOCK_ID_SEM = 0x9,
+ DBG_BLOCK_ID_IH = 0xa,
+ DBG_BLOCK_ID_SC = 0xb,
+ DBG_BLOCK_ID_SQ = 0xc,
+ DBG_BLOCK_ID_UVDU = 0xd,
+ DBG_BLOCK_ID_SQA = 0xe,
+ DBG_BLOCK_ID_SDMA0 = 0xf,
+ DBG_BLOCK_ID_SDMA1 = 0x10,
+ DBG_BLOCK_ID_SPIM = 0x11,
+ DBG_BLOCK_ID_GDS = 0x12,
+ DBG_BLOCK_ID_VC0 = 0x13,
+ DBG_BLOCK_ID_VC1 = 0x14,
+ DBG_BLOCK_ID_PA0 = 0x15,
+ DBG_BLOCK_ID_PA1 = 0x16,
+ DBG_BLOCK_ID_CP0 = 0x17,
+ DBG_BLOCK_ID_CP1 = 0x18,
+ DBG_BLOCK_ID_CP2 = 0x19,
+ DBG_BLOCK_ID_XBR = 0x1a,
+ DBG_BLOCK_ID_UVDM = 0x1b,
+ DBG_BLOCK_ID_VGT0 = 0x1c,
+ DBG_BLOCK_ID_VGT1 = 0x1d,
+ DBG_BLOCK_ID_IA = 0x1e,
+ DBG_BLOCK_ID_SXM0 = 0x1f,
+ DBG_BLOCK_ID_SXM1 = 0x20,
+ DBG_BLOCK_ID_SCT0 = 0x21,
+ DBG_BLOCK_ID_SCT1 = 0x22,
+ DBG_BLOCK_ID_SPM0 = 0x23,
+ DBG_BLOCK_ID_SPM1 = 0x24,
+ DBG_BLOCK_ID_UNUSED0 = 0x25,
+ DBG_BLOCK_ID_UNUSED1 = 0x26,
+ DBG_BLOCK_ID_TCAA = 0x27,
+ DBG_BLOCK_ID_TCAB = 0x28,
+ DBG_BLOCK_ID_TCCA = 0x29,
+ DBG_BLOCK_ID_TCCB = 0x2a,
+ DBG_BLOCK_ID_MCC0 = 0x2b,
+ DBG_BLOCK_ID_MCC1 = 0x2c,
+ DBG_BLOCK_ID_MCC2 = 0x2d,
+ DBG_BLOCK_ID_MCC3 = 0x2e,
+ DBG_BLOCK_ID_SXS0 = 0x2f,
+ DBG_BLOCK_ID_SXS1 = 0x30,
+ DBG_BLOCK_ID_SXS2 = 0x31,
+ DBG_BLOCK_ID_SXS3 = 0x32,
+ DBG_BLOCK_ID_SXS4 = 0x33,
+ DBG_BLOCK_ID_SXS5 = 0x34,
+ DBG_BLOCK_ID_SXS6 = 0x35,
+ DBG_BLOCK_ID_SXS7 = 0x36,
+ DBG_BLOCK_ID_SXS8 = 0x37,
+ DBG_BLOCK_ID_SXS9 = 0x38,
+ DBG_BLOCK_ID_BCI0 = 0x39,
+ DBG_BLOCK_ID_BCI1 = 0x3a,
+ DBG_BLOCK_ID_BCI2 = 0x3b,
+ DBG_BLOCK_ID_BCI3 = 0x3c,
+ DBG_BLOCK_ID_MCB = 0x3d,
+ DBG_BLOCK_ID_UNUSED6 = 0x3e,
+ DBG_BLOCK_ID_SQA00 = 0x3f,
+ DBG_BLOCK_ID_SQA01 = 0x40,
+ DBG_BLOCK_ID_SQA02 = 0x41,
+ DBG_BLOCK_ID_SQA10 = 0x42,
+ DBG_BLOCK_ID_SQA11 = 0x43,
+ DBG_BLOCK_ID_SQA12 = 0x44,
+ DBG_BLOCK_ID_UNUSED7 = 0x45,
+ DBG_BLOCK_ID_UNUSED8 = 0x46,
+ DBG_BLOCK_ID_SQB00 = 0x47,
+ DBG_BLOCK_ID_SQB01 = 0x48,
+ DBG_BLOCK_ID_SQB10 = 0x49,
+ DBG_BLOCK_ID_SQB11 = 0x4a,
+ DBG_BLOCK_ID_SQ00 = 0x4b,
+ DBG_BLOCK_ID_SQ01 = 0x4c,
+ DBG_BLOCK_ID_SQ10 = 0x4d,
+ DBG_BLOCK_ID_SQ11 = 0x4e,
+ DBG_BLOCK_ID_CB00 = 0x4f,
+ DBG_BLOCK_ID_CB01 = 0x50,
+ DBG_BLOCK_ID_CB02 = 0x51,
+ DBG_BLOCK_ID_CB03 = 0x52,
+ DBG_BLOCK_ID_CB04 = 0x53,
+ DBG_BLOCK_ID_UNUSED9 = 0x54,
+ DBG_BLOCK_ID_UNUSED10 = 0x55,
+ DBG_BLOCK_ID_UNUSED11 = 0x56,
+ DBG_BLOCK_ID_CB10 = 0x57,
+ DBG_BLOCK_ID_CB11 = 0x58,
+ DBG_BLOCK_ID_CB12 = 0x59,
+ DBG_BLOCK_ID_CB13 = 0x5a,
+ DBG_BLOCK_ID_CB14 = 0x5b,
+ DBG_BLOCK_ID_UNUSED12 = 0x5c,
+ DBG_BLOCK_ID_UNUSED13 = 0x5d,
+ DBG_BLOCK_ID_UNUSED14 = 0x5e,
+ DBG_BLOCK_ID_TCP0 = 0x5f,
+ DBG_BLOCK_ID_TCP1 = 0x60,
+ DBG_BLOCK_ID_TCP2 = 0x61,
+ DBG_BLOCK_ID_TCP3 = 0x62,
+ DBG_BLOCK_ID_TCP4 = 0x63,
+ DBG_BLOCK_ID_TCP5 = 0x64,
+ DBG_BLOCK_ID_TCP6 = 0x65,
+ DBG_BLOCK_ID_TCP7 = 0x66,
+ DBG_BLOCK_ID_TCP8 = 0x67,
+ DBG_BLOCK_ID_TCP9 = 0x68,
+ DBG_BLOCK_ID_TCP10 = 0x69,
+ DBG_BLOCK_ID_TCP11 = 0x6a,
+ DBG_BLOCK_ID_TCP12 = 0x6b,
+ DBG_BLOCK_ID_TCP13 = 0x6c,
+ DBG_BLOCK_ID_TCP14 = 0x6d,
+ DBG_BLOCK_ID_TCP15 = 0x6e,
+ DBG_BLOCK_ID_TCP16 = 0x6f,
+ DBG_BLOCK_ID_TCP17 = 0x70,
+ DBG_BLOCK_ID_TCP18 = 0x71,
+ DBG_BLOCK_ID_TCP19 = 0x72,
+ DBG_BLOCK_ID_TCP20 = 0x73,
+ DBG_BLOCK_ID_TCP21 = 0x74,
+ DBG_BLOCK_ID_TCP22 = 0x75,
+ DBG_BLOCK_ID_TCP23 = 0x76,
+ DBG_BLOCK_ID_TCP_RESERVED0 = 0x77,
+ DBG_BLOCK_ID_TCP_RESERVED1 = 0x78,
+ DBG_BLOCK_ID_TCP_RESERVED2 = 0x79,
+ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a,
+ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b,
+ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c,
+ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d,
+ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e,
+ DBG_BLOCK_ID_DB00 = 0x7f,
+ DBG_BLOCK_ID_DB01 = 0x80,
+ DBG_BLOCK_ID_DB02 = 0x81,
+ DBG_BLOCK_ID_DB03 = 0x82,
+ DBG_BLOCK_ID_DB04 = 0x83,
+ DBG_BLOCK_ID_UNUSED15 = 0x84,
+ DBG_BLOCK_ID_UNUSED16 = 0x85,
+ DBG_BLOCK_ID_UNUSED17 = 0x86,
+ DBG_BLOCK_ID_DB10 = 0x87,
+ DBG_BLOCK_ID_DB11 = 0x88,
+ DBG_BLOCK_ID_DB12 = 0x89,
+ DBG_BLOCK_ID_DB13 = 0x8a,
+ DBG_BLOCK_ID_DB14 = 0x8b,
+ DBG_BLOCK_ID_UNUSED18 = 0x8c,
+ DBG_BLOCK_ID_UNUSED19 = 0x8d,
+ DBG_BLOCK_ID_UNUSED20 = 0x8e,
+ DBG_BLOCK_ID_TCC0 = 0x8f,
+ DBG_BLOCK_ID_TCC1 = 0x90,
+ DBG_BLOCK_ID_TCC2 = 0x91,
+ DBG_BLOCK_ID_TCC3 = 0x92,
+ DBG_BLOCK_ID_TCC4 = 0x93,
+ DBG_BLOCK_ID_TCC5 = 0x94,
+ DBG_BLOCK_ID_TCC6 = 0x95,
+ DBG_BLOCK_ID_TCC7 = 0x96,
+ DBG_BLOCK_ID_SPS00 = 0x97,
+ DBG_BLOCK_ID_SPS01 = 0x98,
+ DBG_BLOCK_ID_SPS02 = 0x99,
+ DBG_BLOCK_ID_SPS10 = 0x9a,
+ DBG_BLOCK_ID_SPS11 = 0x9b,
+ DBG_BLOCK_ID_SPS12 = 0x9c,
+ DBG_BLOCK_ID_UNUSED21 = 0x9d,
+ DBG_BLOCK_ID_UNUSED22 = 0x9e,
+ DBG_BLOCK_ID_TA00 = 0x9f,
+ DBG_BLOCK_ID_TA01 = 0xa0,
+ DBG_BLOCK_ID_TA02 = 0xa1,
+ DBG_BLOCK_ID_TA03 = 0xa2,
+ DBG_BLOCK_ID_TA04 = 0xa3,
+ DBG_BLOCK_ID_TA05 = 0xa4,
+ DBG_BLOCK_ID_TA06 = 0xa5,
+ DBG_BLOCK_ID_TA07 = 0xa6,
+ DBG_BLOCK_ID_TA08 = 0xa7,
+ DBG_BLOCK_ID_TA09 = 0xa8,
+ DBG_BLOCK_ID_TA0A = 0xa9,
+ DBG_BLOCK_ID_TA0B = 0xaa,
+ DBG_BLOCK_ID_UNUSED23 = 0xab,
+ DBG_BLOCK_ID_UNUSED24 = 0xac,
+ DBG_BLOCK_ID_UNUSED25 = 0xad,
+ DBG_BLOCK_ID_UNUSED26 = 0xae,
+ DBG_BLOCK_ID_TA10 = 0xaf,
+ DBG_BLOCK_ID_TA11 = 0xb0,
+ DBG_BLOCK_ID_TA12 = 0xb1,
+ DBG_BLOCK_ID_TA13 = 0xb2,
+ DBG_BLOCK_ID_TA14 = 0xb3,
+ DBG_BLOCK_ID_TA15 = 0xb4,
+ DBG_BLOCK_ID_TA16 = 0xb5,
+ DBG_BLOCK_ID_TA17 = 0xb6,
+ DBG_BLOCK_ID_TA18 = 0xb7,
+ DBG_BLOCK_ID_TA19 = 0xb8,
+ DBG_BLOCK_ID_TA1A = 0xb9,
+ DBG_BLOCK_ID_TA1B = 0xba,
+ DBG_BLOCK_ID_UNUSED27 = 0xbb,
+ DBG_BLOCK_ID_UNUSED28 = 0xbc,
+ DBG_BLOCK_ID_UNUSED29 = 0xbd,
+ DBG_BLOCK_ID_UNUSED30 = 0xbe,
+ DBG_BLOCK_ID_TD00 = 0xbf,
+ DBG_BLOCK_ID_TD01 = 0xc0,
+ DBG_BLOCK_ID_TD02 = 0xc1,
+ DBG_BLOCK_ID_TD03 = 0xc2,
+ DBG_BLOCK_ID_TD04 = 0xc3,
+ DBG_BLOCK_ID_TD05 = 0xc4,
+ DBG_BLOCK_ID_TD06 = 0xc5,
+ DBG_BLOCK_ID_TD07 = 0xc6,
+ DBG_BLOCK_ID_TD08 = 0xc7,
+ DBG_BLOCK_ID_TD09 = 0xc8,
+ DBG_BLOCK_ID_TD0A = 0xc9,
+ DBG_BLOCK_ID_TD0B = 0xca,
+ DBG_BLOCK_ID_UNUSED31 = 0xcb,
+ DBG_BLOCK_ID_UNUSED32 = 0xcc,
+ DBG_BLOCK_ID_UNUSED33 = 0xcd,
+ DBG_BLOCK_ID_UNUSED34 = 0xce,
+ DBG_BLOCK_ID_TD10 = 0xcf,
+ DBG_BLOCK_ID_TD11 = 0xd0,
+ DBG_BLOCK_ID_TD12 = 0xd1,
+ DBG_BLOCK_ID_TD13 = 0xd2,
+ DBG_BLOCK_ID_TD14 = 0xd3,
+ DBG_BLOCK_ID_TD15 = 0xd4,
+ DBG_BLOCK_ID_TD16 = 0xd5,
+ DBG_BLOCK_ID_TD17 = 0xd6,
+ DBG_BLOCK_ID_TD18 = 0xd7,
+ DBG_BLOCK_ID_TD19 = 0xd8,
+ DBG_BLOCK_ID_TD1A = 0xd9,
+ DBG_BLOCK_ID_TD1B = 0xda,
+ DBG_BLOCK_ID_UNUSED35 = 0xdb,
+ DBG_BLOCK_ID_UNUSED36 = 0xdc,
+ DBG_BLOCK_ID_UNUSED37 = 0xdd,
+ DBG_BLOCK_ID_UNUSED38 = 0xde,
+ DBG_BLOCK_ID_LDS00 = 0xdf,
+ DBG_BLOCK_ID_LDS01 = 0xe0,
+ DBG_BLOCK_ID_LDS02 = 0xe1,
+ DBG_BLOCK_ID_LDS03 = 0xe2,
+ DBG_BLOCK_ID_LDS04 = 0xe3,
+ DBG_BLOCK_ID_LDS05 = 0xe4,
+ DBG_BLOCK_ID_LDS06 = 0xe5,
+ DBG_BLOCK_ID_LDS07 = 0xe6,
+ DBG_BLOCK_ID_LDS08 = 0xe7,
+ DBG_BLOCK_ID_LDS09 = 0xe8,
+ DBG_BLOCK_ID_LDS0A = 0xe9,
+ DBG_BLOCK_ID_LDS0B = 0xea,
+ DBG_BLOCK_ID_UNUSED39 = 0xeb,
+ DBG_BLOCK_ID_UNUSED40 = 0xec,
+ DBG_BLOCK_ID_UNUSED41 = 0xed,
+ DBG_BLOCK_ID_UNUSED42 = 0xee,
+ DBG_BLOCK_ID_LDS10 = 0xef,
+ DBG_BLOCK_ID_LDS11 = 0xf0,
+ DBG_BLOCK_ID_LDS12 = 0xf1,
+ DBG_BLOCK_ID_LDS13 = 0xf2,
+ DBG_BLOCK_ID_LDS14 = 0xf3,
+ DBG_BLOCK_ID_LDS15 = 0xf4,
+ DBG_BLOCK_ID_LDS16 = 0xf5,
+ DBG_BLOCK_ID_LDS17 = 0xf6,
+ DBG_BLOCK_ID_LDS18 = 0xf7,
+ DBG_BLOCK_ID_LDS19 = 0xf8,
+ DBG_BLOCK_ID_LDS1A = 0xf9,
+ DBG_BLOCK_ID_LDS1B = 0xfa,
+ DBG_BLOCK_ID_UNUSED43 = 0xfb,
+ DBG_BLOCK_ID_UNUSED44 = 0xfc,
+ DBG_BLOCK_ID_UNUSED45 = 0xfd,
+ DBG_BLOCK_ID_UNUSED46 = 0xfe,
+} DebugBlockId;
+typedef enum DebugBlockId_BY2 {
+ DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
+ DBG_BLOCK_ID_VMC_BY2 = 0x1,
+ DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
+ DBG_BLOCK_ID_GRBM_BY2 = 0x3,
+ DBG_BLOCK_ID_CSC_BY2 = 0x4,
+ DBG_BLOCK_ID_IH_BY2 = 0x5,
+ DBG_BLOCK_ID_SQ_BY2 = 0x6,
+ DBG_BLOCK_ID_UVD_BY2 = 0x7,
+ DBG_BLOCK_ID_SDMA0_BY2 = 0x8,
+ DBG_BLOCK_ID_SPIM_BY2 = 0x9,
+ DBG_BLOCK_ID_VC0_BY2 = 0xa,
+ DBG_BLOCK_ID_PA_BY2 = 0xb,
+ DBG_BLOCK_ID_CP0_BY2 = 0xc,
+ DBG_BLOCK_ID_CP2_BY2 = 0xd,
+ DBG_BLOCK_ID_PC0_BY2 = 0xe,
+ DBG_BLOCK_ID_BCI0_BY2 = 0xf,
+ DBG_BLOCK_ID_SXM0_BY2 = 0x10,
+ DBG_BLOCK_ID_SCT0_BY2 = 0x11,
+ DBG_BLOCK_ID_SPM0_BY2 = 0x12,
+ DBG_BLOCK_ID_BCI2_BY2 = 0x13,
+ DBG_BLOCK_ID_TCA_BY2 = 0x14,
+ DBG_BLOCK_ID_TCCA_BY2 = 0x15,
+ DBG_BLOCK_ID_MCC_BY2 = 0x16,
+ DBG_BLOCK_ID_MCC2_BY2 = 0x17,
+ DBG_BLOCK_ID_MCD_BY2 = 0x18,
+ DBG_BLOCK_ID_MCD2_BY2 = 0x19,
+ DBG_BLOCK_ID_MCD4_BY2 = 0x1a,
+ DBG_BLOCK_ID_MCB_BY2 = 0x1b,
+ DBG_BLOCK_ID_SQA_BY2 = 0x1c,
+ DBG_BLOCK_ID_SQA02_BY2 = 0x1d,
+ DBG_BLOCK_ID_SQA11_BY2 = 0x1e,
+ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f,
+ DBG_BLOCK_ID_SQB_BY2 = 0x20,
+ DBG_BLOCK_ID_SQB10_BY2 = 0x21,
+ DBG_BLOCK_ID_UNUSED10_BY2 = 0x22,
+ DBG_BLOCK_ID_UNUSED12_BY2 = 0x23,
+ DBG_BLOCK_ID_CB_BY2 = 0x24,
+ DBG_BLOCK_ID_CB02_BY2 = 0x25,
+ DBG_BLOCK_ID_CB10_BY2 = 0x26,
+ DBG_BLOCK_ID_CB12_BY2 = 0x27,
+ DBG_BLOCK_ID_SXS_BY2 = 0x28,
+ DBG_BLOCK_ID_SXS2_BY2 = 0x29,
+ DBG_BLOCK_ID_SXS4_BY2 = 0x2a,
+ DBG_BLOCK_ID_SXS6_BY2 = 0x2b,
+ DBG_BLOCK_ID_DB_BY2 = 0x2c,
+ DBG_BLOCK_ID_DB02_BY2 = 0x2d,
+ DBG_BLOCK_ID_DB10_BY2 = 0x2e,
+ DBG_BLOCK_ID_DB12_BY2 = 0x2f,
+ DBG_BLOCK_ID_TCP_BY2 = 0x30,
+ DBG_BLOCK_ID_TCP2_BY2 = 0x31,
+ DBG_BLOCK_ID_TCP4_BY2 = 0x32,
+ DBG_BLOCK_ID_TCP6_BY2 = 0x33,
+ DBG_BLOCK_ID_TCP8_BY2 = 0x34,
+ DBG_BLOCK_ID_TCP10_BY2 = 0x35,
+ DBG_BLOCK_ID_TCP12_BY2 = 0x36,
+ DBG_BLOCK_ID_TCP14_BY2 = 0x37,
+ DBG_BLOCK_ID_TCP16_BY2 = 0x38,
+ DBG_BLOCK_ID_TCP18_BY2 = 0x39,
+ DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
+ DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
+ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
+ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
+ DBG_BLOCK_ID_TCC_BY2 = 0x40,
+ DBG_BLOCK_ID_TCC2_BY2 = 0x41,
+ DBG_BLOCK_ID_TCC4_BY2 = 0x42,
+ DBG_BLOCK_ID_TCC6_BY2 = 0x43,
+ DBG_BLOCK_ID_SPS_BY2 = 0x44,
+ DBG_BLOCK_ID_SPS02_BY2 = 0x45,
+ DBG_BLOCK_ID_SPS11_BY2 = 0x46,
+ DBG_BLOCK_ID_UNUSED14_BY2 = 0x47,
+ DBG_BLOCK_ID_TA_BY2 = 0x48,
+ DBG_BLOCK_ID_TA02_BY2 = 0x49,
+ DBG_BLOCK_ID_TA04_BY2 = 0x4a,
+ DBG_BLOCK_ID_TA06_BY2 = 0x4b,
+ DBG_BLOCK_ID_TA08_BY2 = 0x4c,
+ DBG_BLOCK_ID_TA0A_BY2 = 0x4d,
+ DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e,
+ DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f,
+ DBG_BLOCK_ID_TA10_BY2 = 0x50,
+ DBG_BLOCK_ID_TA12_BY2 = 0x51,
+ DBG_BLOCK_ID_TA14_BY2 = 0x52,
+ DBG_BLOCK_ID_TA16_BY2 = 0x53,
+ DBG_BLOCK_ID_TA18_BY2 = 0x54,
+ DBG_BLOCK_ID_TA1A_BY2 = 0x55,
+ DBG_BLOCK_ID_UNUSED24_BY2 = 0x56,
+ DBG_BLOCK_ID_UNUSED26_BY2 = 0x57,
+ DBG_BLOCK_ID_TD_BY2 = 0x58,
+ DBG_BLOCK_ID_TD02_BY2 = 0x59,
+ DBG_BLOCK_ID_TD04_BY2 = 0x5a,
+ DBG_BLOCK_ID_TD06_BY2 = 0x5b,
+ DBG_BLOCK_ID_TD08_BY2 = 0x5c,
+ DBG_BLOCK_ID_TD0A_BY2 = 0x5d,
+ DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e,
+ DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f,
+ DBG_BLOCK_ID_TD10_BY2 = 0x60,
+ DBG_BLOCK_ID_TD12_BY2 = 0x61,
+ DBG_BLOCK_ID_TD14_BY2 = 0x62,
+ DBG_BLOCK_ID_TD16_BY2 = 0x63,
+ DBG_BLOCK_ID_TD18_BY2 = 0x64,
+ DBG_BLOCK_ID_TD1A_BY2 = 0x65,
+ DBG_BLOCK_ID_UNUSED32_BY2 = 0x66,
+ DBG_BLOCK_ID_UNUSED34_BY2 = 0x67,
+ DBG_BLOCK_ID_LDS_BY2 = 0x68,
+ DBG_BLOCK_ID_LDS02_BY2 = 0x69,
+ DBG_BLOCK_ID_LDS04_BY2 = 0x6a,
+ DBG_BLOCK_ID_LDS06_BY2 = 0x6b,
+ DBG_BLOCK_ID_LDS08_BY2 = 0x6c,
+ DBG_BLOCK_ID_LDS0A_BY2 = 0x6d,
+ DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e,
+ DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f,
+ DBG_BLOCK_ID_LDS10_BY2 = 0x70,
+ DBG_BLOCK_ID_LDS12_BY2 = 0x71,
+ DBG_BLOCK_ID_LDS14_BY2 = 0x72,
+ DBG_BLOCK_ID_LDS16_BY2 = 0x73,
+ DBG_BLOCK_ID_LDS18_BY2 = 0x74,
+ DBG_BLOCK_ID_LDS1A_BY2 = 0x75,
+ DBG_BLOCK_ID_UNUSED40_BY2 = 0x76,
+ DBG_BLOCK_ID_UNUSED42_BY2 = 0x77,
+} DebugBlockId_BY2;
+typedef enum DebugBlockId_BY4 {
+ DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
+ DBG_BLOCK_ID_UNUSED0_BY4 = 0x1,
+ DBG_BLOCK_ID_CSC_BY4 = 0x2,
+ DBG_BLOCK_ID_SQ_BY4 = 0x3,
+ DBG_BLOCK_ID_SDMA0_BY4 = 0x4,
+ DBG_BLOCK_ID_VC0_BY4 = 0x5,
+ DBG_BLOCK_ID_CP0_BY4 = 0x6,
+ DBG_BLOCK_ID_UNUSED1_BY4 = 0x7,
+ DBG_BLOCK_ID_SXM0_BY4 = 0x8,
+ DBG_BLOCK_ID_SPM0_BY4 = 0x9,
+ DBG_BLOCK_ID_TCAA_BY4 = 0xa,
+ DBG_BLOCK_ID_MCC_BY4 = 0xb,
+ DBG_BLOCK_ID_MCD_BY4 = 0xc,
+ DBG_BLOCK_ID_MCD4_BY4 = 0xd,
+ DBG_BLOCK_ID_SQA_BY4 = 0xe,
+ DBG_BLOCK_ID_SQA11_BY4 = 0xf,
+ DBG_BLOCK_ID_SQB_BY4 = 0x10,
+ DBG_BLOCK_ID_UNUSED10_BY4 = 0x11,
+ DBG_BLOCK_ID_CB_BY4 = 0x12,
+ DBG_BLOCK_ID_CB10_BY4 = 0x13,
+ DBG_BLOCK_ID_SXS_BY4 = 0x14,
+ DBG_BLOCK_ID_SXS4_BY4 = 0x15,
+ DBG_BLOCK_ID_DB_BY4 = 0x16,
+ DBG_BLOCK_ID_DB10_BY4 = 0x17,
+ DBG_BLOCK_ID_TCP_BY4 = 0x18,
+ DBG_BLOCK_ID_TCP4_BY4 = 0x19,
+ DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
+ DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
+ DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
+ DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
+ DBG_BLOCK_ID_TCC_BY4 = 0x20,
+ DBG_BLOCK_ID_TCC4_BY4 = 0x21,
+ DBG_BLOCK_ID_SPS_BY4 = 0x22,
+ DBG_BLOCK_ID_SPS11_BY4 = 0x23,
+ DBG_BLOCK_ID_TA_BY4 = 0x24,
+ DBG_BLOCK_ID_TA04_BY4 = 0x25,
+ DBG_BLOCK_ID_TA08_BY4 = 0x26,
+ DBG_BLOCK_ID_UNUSED20_BY4 = 0x27,
+ DBG_BLOCK_ID_TA10_BY4 = 0x28,
+ DBG_BLOCK_ID_TA14_BY4 = 0x29,
+ DBG_BLOCK_ID_TA18_BY4 = 0x2a,
+ DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b,
+ DBG_BLOCK_ID_TD_BY4 = 0x2c,
+ DBG_BLOCK_ID_TD04_BY4 = 0x2d,
+ DBG_BLOCK_ID_TD08_BY4 = 0x2e,
+ DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f,
+ DBG_BLOCK_ID_TD10_BY4 = 0x30,
+ DBG_BLOCK_ID_TD14_BY4 = 0x31,
+ DBG_BLOCK_ID_TD18_BY4 = 0x32,
+ DBG_BLOCK_ID_UNUSED32_BY4 = 0x33,
+ DBG_BLOCK_ID_LDS_BY4 = 0x34,
+ DBG_BLOCK_ID_LDS04_BY4 = 0x35,
+ DBG_BLOCK_ID_LDS08_BY4 = 0x36,
+ DBG_BLOCK_ID_UNUSED36_BY4 = 0x37,
+ DBG_BLOCK_ID_LDS10_BY4 = 0x38,
+ DBG_BLOCK_ID_LDS14_BY4 = 0x39,
+ DBG_BLOCK_ID_LDS18_BY4 = 0x3a,
+ DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b,
+} DebugBlockId_BY4;
+typedef enum DebugBlockId_BY8 {
+ DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
+ DBG_BLOCK_ID_CSC_BY8 = 0x1,
+ DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
+ DBG_BLOCK_ID_CP0_BY8 = 0x3,
+ DBG_BLOCK_ID_SXM0_BY8 = 0x4,
+ DBG_BLOCK_ID_TCA_BY8 = 0x5,
+ DBG_BLOCK_ID_MCD_BY8 = 0x6,
+ DBG_BLOCK_ID_SQA_BY8 = 0x7,
+ DBG_BLOCK_ID_SQB_BY8 = 0x8,
+ DBG_BLOCK_ID_CB_BY8 = 0x9,
+ DBG_BLOCK_ID_SXS_BY8 = 0xa,
+ DBG_BLOCK_ID_DB_BY8 = 0xb,
+ DBG_BLOCK_ID_TCP_BY8 = 0xc,
+ DBG_BLOCK_ID_TCP8_BY8 = 0xd,
+ DBG_BLOCK_ID_TCP16_BY8 = 0xe,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
+ DBG_BLOCK_ID_TCC_BY8 = 0x10,
+ DBG_BLOCK_ID_SPS_BY8 = 0x11,
+ DBG_BLOCK_ID_TA_BY8 = 0x12,
+ DBG_BLOCK_ID_TA08_BY8 = 0x13,
+ DBG_BLOCK_ID_TA10_BY8 = 0x14,
+ DBG_BLOCK_ID_TA18_BY8 = 0x15,
+ DBG_BLOCK_ID_TD_BY8 = 0x16,
+ DBG_BLOCK_ID_TD08_BY8 = 0x17,
+ DBG_BLOCK_ID_TD10_BY8 = 0x18,
+ DBG_BLOCK_ID_TD18_BY8 = 0x19,
+ DBG_BLOCK_ID_LDS_BY8 = 0x1a,
+ DBG_BLOCK_ID_LDS08_BY8 = 0x1b,
+ DBG_BLOCK_ID_LDS10_BY8 = 0x1c,
+ DBG_BLOCK_ID_LDS18_BY8 = 0x1d,
+} DebugBlockId_BY8;
+typedef enum DebugBlockId_BY16 {
+ DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
+ DBG_BLOCK_ID_SDMA0_BY16 = 0x1,
+ DBG_BLOCK_ID_SXM_BY16 = 0x2,
+ DBG_BLOCK_ID_MCD_BY16 = 0x3,
+ DBG_BLOCK_ID_SQB_BY16 = 0x4,
+ DBG_BLOCK_ID_SXS_BY16 = 0x5,
+ DBG_BLOCK_ID_TCP_BY16 = 0x6,
+ DBG_BLOCK_ID_TCP16_BY16 = 0x7,
+ DBG_BLOCK_ID_TCC_BY16 = 0x8,
+ DBG_BLOCK_ID_TA_BY16 = 0x9,
+ DBG_BLOCK_ID_TA10_BY16 = 0xa,
+ DBG_BLOCK_ID_TD_BY16 = 0xb,
+ DBG_BLOCK_ID_TD10_BY16 = 0xc,
+ DBG_BLOCK_ID_LDS_BY16 = 0xd,
+ DBG_BLOCK_ID_LDS10_BY16 = 0xe,
+} DebugBlockId_BY16;
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0x0,
+ ENDIAN_8IN16 = 0x1,
+ ENDIAN_8IN32 = 0x2,
+ ENDIAN_8IN64 = 0x3,
+} SurfaceEndian;
+typedef enum ArrayMode {
+ ARRAY_LINEAR_GENERAL = 0x0,
+ ARRAY_LINEAR_ALIGNED = 0x1,
+ ARRAY_1D_TILED_THIN1 = 0x2,
+ ARRAY_1D_TILED_THICK = 0x3,
+ ARRAY_2D_TILED_THIN1 = 0x4,
+ ARRAY_PRT_TILED_THIN1 = 0x5,
+ ARRAY_PRT_2D_TILED_THIN1 = 0x6,
+ ARRAY_2D_TILED_THICK = 0x7,
+ ARRAY_2D_TILED_XTHICK = 0x8,
+ ARRAY_PRT_TILED_THICK = 0x9,
+ ARRAY_PRT_2D_TILED_THICK = 0xa,
+ ARRAY_PRT_3D_TILED_THIN1 = 0xb,
+ ARRAY_3D_TILED_THIN1 = 0xc,
+ ARRAY_3D_TILED_THICK = 0xd,
+ ARRAY_3D_TILED_XTHICK = 0xe,
+ ARRAY_PRT_3D_TILED_THICK = 0xf,
+} ArrayMode;
+typedef enum PipeTiling {
+ CONFIG_1_PIPE = 0x0,
+ CONFIG_2_PIPE = 0x1,
+ CONFIG_4_PIPE = 0x2,
+ CONFIG_8_PIPE = 0x3,
+} PipeTiling;
+typedef enum BankTiling {
+ CONFIG_4_BANK = 0x0,
+ CONFIG_8_BANK = 0x1,
+} BankTiling;
+typedef enum GroupInterleave {
+ CONFIG_256B_GROUP = 0x0,
+ CONFIG_512B_GROUP = 0x1,
+} GroupInterleave;
+typedef enum RowTiling {
+ CONFIG_1KB_ROW = 0x0,
+ CONFIG_2KB_ROW = 0x1,
+ CONFIG_4KB_ROW = 0x2,
+ CONFIG_8KB_ROW = 0x3,
+ CONFIG_1KB_ROW_OPT = 0x4,
+ CONFIG_2KB_ROW_OPT = 0x5,
+ CONFIG_4KB_ROW_OPT = 0x6,
+ CONFIG_8KB_ROW_OPT = 0x7,
+} RowTiling;
+typedef enum BankSwapBytes {
+ CONFIG_128B_SWAPS = 0x0,
+ CONFIG_256B_SWAPS = 0x1,
+ CONFIG_512B_SWAPS = 0x2,
+ CONFIG_1KB_SWAPS = 0x3,
+} BankSwapBytes;
+typedef enum SampleSplitBytes {
+ CONFIG_1KB_SPLIT = 0x0,
+ CONFIG_2KB_SPLIT = 0x1,
+ CONFIG_4KB_SPLIT = 0x2,
+ CONFIG_8KB_SPLIT = 0x3,
+} SampleSplitBytes;
+typedef enum NumPipes {
+ ADDR_CONFIG_1_PIPE = 0x0,
+ ADDR_CONFIG_2_PIPE = 0x1,
+ ADDR_CONFIG_4_PIPE = 0x2,
+ ADDR_CONFIG_8_PIPE = 0x3,
+} NumPipes;
+typedef enum PipeInterleaveSize {
+ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
+ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
+} PipeInterleaveSize;
+typedef enum BankInterleaveSize {
+ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
+ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
+ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
+ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
+} BankInterleaveSize;
+typedef enum NumShaderEngines {
+ ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
+ ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
+} NumShaderEngines;
+typedef enum ShaderEngineTileSize {
+ ADDR_CONFIG_SE_TILE_16 = 0x0,
+ ADDR_CONFIG_SE_TILE_32 = 0x1,
+} ShaderEngineTileSize;
+typedef enum NumGPUs {
+ ADDR_CONFIG_1_GPU = 0x0,
+ ADDR_CONFIG_2_GPU = 0x1,
+ ADDR_CONFIG_4_GPU = 0x2,
+} NumGPUs;
+typedef enum MultiGPUTileSize {
+ ADDR_CONFIG_GPU_TILE_16 = 0x0,
+ ADDR_CONFIG_GPU_TILE_32 = 0x1,
+ ADDR_CONFIG_GPU_TILE_64 = 0x2,
+ ADDR_CONFIG_GPU_TILE_128 = 0x3,
+} MultiGPUTileSize;
+typedef enum RowSize {
+ ADDR_CONFIG_1KB_ROW = 0x0,
+ ADDR_CONFIG_2KB_ROW = 0x1,
+ ADDR_CONFIG_4KB_ROW = 0x2,
+} RowSize;
+typedef enum NumLowerPipes {
+ ADDR_CONFIG_1_LOWER_PIPES = 0x0,
+ ADDR_CONFIG_2_LOWER_PIPES = 0x1,
+} NumLowerPipes;
+typedef enum ColorTransform {
+ DCC_CT_AUTO = 0x0,
+ DCC_CT_NONE = 0x1,
+ ABGR_TO_A_BG_G_RB = 0x2,
+ BGRA_TO_BG_G_RB_A = 0x3,
+} ColorTransform;
+typedef enum CompareRef {
+ REF_NEVER = 0x0,
+ REF_LESS = 0x1,
+ REF_EQUAL = 0x2,
+ REF_LEQUAL = 0x3,
+ REF_GREATER = 0x4,
+ REF_NOTEQUAL = 0x5,
+ REF_GEQUAL = 0x6,
+ REF_ALWAYS = 0x7,
+} CompareRef;
+typedef enum ReadSize {
+ READ_256_BITS = 0x0,
+ READ_512_BITS = 0x1,
+} ReadSize;
+typedef enum DepthFormat {
+ DEPTH_INVALID = 0x0,
+ DEPTH_16 = 0x1,
+ DEPTH_X8_24 = 0x2,
+ DEPTH_8_24 = 0x3,
+ DEPTH_X8_24_FLOAT = 0x4,
+ DEPTH_8_24_FLOAT = 0x5,
+ DEPTH_32_FLOAT = 0x6,
+ DEPTH_X24_8_32_FLOAT = 0x7,
+} DepthFormat;
+typedef enum ZFormat {
+ Z_INVALID = 0x0,
+ Z_16 = 0x1,
+ Z_24 = 0x2,
+ Z_32_FLOAT = 0x3,
+} ZFormat;
+typedef enum StencilFormat {
+ STENCIL_INVALID = 0x0,
+ STENCIL_8 = 0x1,
+} StencilFormat;
+typedef enum CmaskMode {
+ CMASK_CLEAR_NONE = 0x0,
+ CMASK_CLEAR_ONE = 0x1,
+ CMASK_CLEAR_ALL = 0x2,
+ CMASK_ANY_EXPANDED = 0x3,
+ CMASK_ALPHA0_FRAG1 = 0x4,
+ CMASK_ALPHA0_FRAG2 = 0x5,
+ CMASK_ALPHA0_FRAG4 = 0x6,
+ CMASK_ALPHA0_FRAGS = 0x7,
+ CMASK_ALPHA1_FRAG1 = 0x8,
+ CMASK_ALPHA1_FRAG2 = 0x9,
+ CMASK_ALPHA1_FRAG4 = 0xa,
+ CMASK_ALPHA1_FRAGS = 0xb,
+ CMASK_ALPHAX_FRAG1 = 0xc,
+ CMASK_ALPHAX_FRAG2 = 0xd,
+ CMASK_ALPHAX_FRAG4 = 0xe,
+ CMASK_ALPHAX_FRAGS = 0xf,
+} CmaskMode;
+typedef enum QuadExportFormat {
+ EXPORT_UNUSED = 0x0,
+ EXPORT_32_R = 0x1,
+ EXPORT_32_GR = 0x2,
+ EXPORT_32_AR = 0x3,
+ EXPORT_FP16_ABGR = 0x4,
+ EXPORT_UNSIGNED16_ABGR = 0x5,
+ EXPORT_SIGNED16_ABGR = 0x6,
+ EXPORT_32_ABGR = 0x7,
+} QuadExportFormat;
+typedef enum QuadExportFormatOld {
+ EXPORT_4P_32BPC_ABGR = 0x0,
+ EXPORT_4P_16BPC_ABGR = 0x1,
+ EXPORT_4P_32BPC_GR = 0x2,
+ EXPORT_4P_32BPC_AR = 0x3,
+ EXPORT_2P_32BPC_ABGR = 0x4,
+ EXPORT_8P_32BPC_R = 0x5,
+} QuadExportFormatOld;
+typedef enum ColorFormat {
+ COLOR_INVALID = 0x0,
+ COLOR_8 = 0x1,
+ COLOR_16 = 0x2,
+ COLOR_8_8 = 0x3,
+ COLOR_32 = 0x4,
+ COLOR_16_16 = 0x5,
+ COLOR_10_11_11 = 0x6,
+ COLOR_11_11_10 = 0x7,
+ COLOR_10_10_10_2 = 0x8,
+ COLOR_2_10_10_10 = 0x9,
+ COLOR_8_8_8_8 = 0xa,
+ COLOR_32_32 = 0xb,
+ COLOR_16_16_16_16 = 0xc,
+ COLOR_RESERVED_13 = 0xd,
+ COLOR_32_32_32_32 = 0xe,
+ COLOR_RESERVED_15 = 0xf,
+ COLOR_5_6_5 = 0x10,
+ COLOR_1_5_5_5 = 0x11,
+ COLOR_5_5_5_1 = 0x12,
+ COLOR_4_4_4_4 = 0x13,
+ COLOR_8_24 = 0x14,
+ COLOR_24_8 = 0x15,
+ COLOR_X24_8_32_FLOAT = 0x16,
+ COLOR_RESERVED_23 = 0x17,
+} ColorFormat;
+typedef enum SurfaceFormat {
+ FMT_INVALID = 0x0,
+ FMT_8 = 0x1,
+ FMT_16 = 0x2,
+ FMT_8_8 = 0x3,
+ FMT_32 = 0x4,
+ FMT_16_16 = 0x5,
+ FMT_10_11_11 = 0x6,
+ FMT_11_11_10 = 0x7,
+ FMT_10_10_10_2 = 0x8,
+ FMT_2_10_10_10 = 0x9,
+ FMT_8_8_8_8 = 0xa,
+ FMT_32_32 = 0xb,
+ FMT_16_16_16_16 = 0xc,
+ FMT_32_32_32 = 0xd,
+ FMT_32_32_32_32 = 0xe,
+ FMT_RESERVED_4 = 0xf,
+ FMT_5_6_5 = 0x10,
+ FMT_1_5_5_5 = 0x11,
+ FMT_5_5_5_1 = 0x12,
+ FMT_4_4_4_4 = 0x13,
+ FMT_8_24 = 0x14,
+ FMT_24_8 = 0x15,
+ FMT_X24_8_32_FLOAT = 0x16,
+ FMT_RESERVED_33 = 0x17,
+ FMT_11_11_10_FLOAT = 0x18,
+ FMT_16_FLOAT = 0x19,
+ FMT_32_FLOAT = 0x1a,
+ FMT_16_16_FLOAT = 0x1b,
+ FMT_8_24_FLOAT = 0x1c,
+ FMT_24_8_FLOAT = 0x1d,
+ FMT_32_32_FLOAT = 0x1e,
+ FMT_10_11_11_FLOAT = 0x1f,
+ FMT_16_16_16_16_FLOAT = 0x20,
+ FMT_3_3_2 = 0x21,
+ FMT_6_5_5 = 0x22,
+ FMT_32_32_32_32_FLOAT = 0x23,
+ FMT_RESERVED_36 = 0x24,
+ FMT_1 = 0x25,
+ FMT_1_REVERSED = 0x26,
+ FMT_GB_GR = 0x27,
+ FMT_BG_RG = 0x28,
+ FMT_32_AS_8 = 0x29,
+ FMT_32_AS_8_8 = 0x2a,
+ FMT_5_9_9_9_SHAREDEXP = 0x2b,
+ FMT_8_8_8 = 0x2c,
+ FMT_16_16_16 = 0x2d,
+ FMT_16_16_16_FLOAT = 0x2e,
+ FMT_4_4 = 0x2f,
+ FMT_32_32_32_FLOAT = 0x30,
+ FMT_BC1 = 0x31,
+ FMT_BC2 = 0x32,
+ FMT_BC3 = 0x33,
+ FMT_BC4 = 0x34,
+ FMT_BC5 = 0x35,
+ FMT_BC6 = 0x36,
+ FMT_BC7 = 0x37,
+ FMT_32_AS_32_32_32_32 = 0x38,
+ FMT_APC3 = 0x39,
+ FMT_APC4 = 0x3a,
+ FMT_APC5 = 0x3b,
+ FMT_APC6 = 0x3c,
+ FMT_APC7 = 0x3d,
+ FMT_CTX1 = 0x3e,
+ FMT_RESERVED_63 = 0x3f,
+} SurfaceFormat;
+typedef enum BUF_DATA_FORMAT {
+ BUF_DATA_FORMAT_INVALID = 0x0,
+ BUF_DATA_FORMAT_8 = 0x1,
+ BUF_DATA_FORMAT_16 = 0x2,
+ BUF_DATA_FORMAT_8_8 = 0x3,
+ BUF_DATA_FORMAT_32 = 0x4,
+ BUF_DATA_FORMAT_16_16 = 0x5,
+ BUF_DATA_FORMAT_10_11_11 = 0x6,
+ BUF_DATA_FORMAT_11_11_10 = 0x7,
+ BUF_DATA_FORMAT_10_10_10_2 = 0x8,
+ BUF_DATA_FORMAT_2_10_10_10 = 0x9,
+ BUF_DATA_FORMAT_8_8_8_8 = 0xa,
+ BUF_DATA_FORMAT_32_32 = 0xb,
+ BUF_DATA_FORMAT_16_16_16_16 = 0xc,
+ BUF_DATA_FORMAT_32_32_32 = 0xd,
+ BUF_DATA_FORMAT_32_32_32_32 = 0xe,
+ BUF_DATA_FORMAT_RESERVED_15 = 0xf,
+} BUF_DATA_FORMAT;
+typedef enum IMG_DATA_FORMAT {
+ IMG_DATA_FORMAT_INVALID = 0x0,
+ IMG_DATA_FORMAT_8 = 0x1,
+ IMG_DATA_FORMAT_16 = 0x2,
+ IMG_DATA_FORMAT_8_8 = 0x3,
+ IMG_DATA_FORMAT_32 = 0x4,
+ IMG_DATA_FORMAT_16_16 = 0x5,
+ IMG_DATA_FORMAT_10_11_11 = 0x6,
+ IMG_DATA_FORMAT_11_11_10 = 0x7,
+ IMG_DATA_FORMAT_10_10_10_2 = 0x8,
+ IMG_DATA_FORMAT_2_10_10_10 = 0x9,
+ IMG_DATA_FORMAT_8_8_8_8 = 0xa,
+ IMG_DATA_FORMAT_32_32 = 0xb,
+ IMG_DATA_FORMAT_16_16_16_16 = 0xc,
+ IMG_DATA_FORMAT_32_32_32 = 0xd,
+ IMG_DATA_FORMAT_32_32_32_32 = 0xe,
+ IMG_DATA_FORMAT_RESERVED_15 = 0xf,
+ IMG_DATA_FORMAT_5_6_5 = 0x10,
+ IMG_DATA_FORMAT_1_5_5_5 = 0x11,
+ IMG_DATA_FORMAT_5_5_5_1 = 0x12,
+ IMG_DATA_FORMAT_4_4_4_4 = 0x13,
+ IMG_DATA_FORMAT_8_24 = 0x14,
+ IMG_DATA_FORMAT_24_8 = 0x15,
+ IMG_DATA_FORMAT_X24_8_32 = 0x16,
+ IMG_DATA_FORMAT_RESERVED_23 = 0x17,
+ IMG_DATA_FORMAT_RESERVED_24 = 0x18,
+ IMG_DATA_FORMAT_RESERVED_25 = 0x19,
+ IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
+ IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
+ IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
+ IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
+ IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
+ IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
+ IMG_DATA_FORMAT_GB_GR = 0x20,
+ IMG_DATA_FORMAT_BG_RG = 0x21,
+ IMG_DATA_FORMAT_5_9_9_9 = 0x22,
+ IMG_DATA_FORMAT_BC1 = 0x23,
+ IMG_DATA_FORMAT_BC2 = 0x24,
+ IMG_DATA_FORMAT_BC3 = 0x25,
+ IMG_DATA_FORMAT_BC4 = 0x26,
+ IMG_DATA_FORMAT_BC5 = 0x27,
+ IMG_DATA_FORMAT_BC6 = 0x28,
+ IMG_DATA_FORMAT_BC7 = 0x29,
+ IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
+ IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
+ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
+ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
+ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
+ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
+ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
+ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
+ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
+ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
+ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
+ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
+ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
+ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
+ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
+ IMG_DATA_FORMAT_4_4 = 0x39,
+ IMG_DATA_FORMAT_6_5_5 = 0x3a,
+ IMG_DATA_FORMAT_1 = 0x3b,
+ IMG_DATA_FORMAT_1_REVERSED = 0x3c,
+ IMG_DATA_FORMAT_32_AS_8 = 0x3d,
+ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
+ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
+} IMG_DATA_FORMAT;
+typedef enum BUF_NUM_FORMAT {
+ BUF_NUM_FORMAT_UNORM = 0x0,
+ BUF_NUM_FORMAT_SNORM = 0x1,
+ BUF_NUM_FORMAT_USCALED = 0x2,
+ BUF_NUM_FORMAT_SSCALED = 0x3,
+ BUF_NUM_FORMAT_UINT = 0x4,
+ BUF_NUM_FORMAT_SINT = 0x5,
+ BUF_NUM_FORMAT_RESERVED_6 = 0x6,
+ BUF_NUM_FORMAT_FLOAT = 0x7,
+} BUF_NUM_FORMAT;
+typedef enum IMG_NUM_FORMAT {
+ IMG_NUM_FORMAT_UNORM = 0x0,
+ IMG_NUM_FORMAT_SNORM = 0x1,
+ IMG_NUM_FORMAT_USCALED = 0x2,
+ IMG_NUM_FORMAT_SSCALED = 0x3,
+ IMG_NUM_FORMAT_UINT = 0x4,
+ IMG_NUM_FORMAT_SINT = 0x5,
+ IMG_NUM_FORMAT_RESERVED_6 = 0x6,
+ IMG_NUM_FORMAT_FLOAT = 0x7,
+ IMG_NUM_FORMAT_RESERVED_8 = 0x8,
+ IMG_NUM_FORMAT_SRGB = 0x9,
+ IMG_NUM_FORMAT_RESERVED_10 = 0xa,
+ IMG_NUM_FORMAT_RESERVED_11 = 0xb,
+ IMG_NUM_FORMAT_RESERVED_12 = 0xc,
+ IMG_NUM_FORMAT_RESERVED_13 = 0xd,
+ IMG_NUM_FORMAT_RESERVED_14 = 0xe,
+ IMG_NUM_FORMAT_RESERVED_15 = 0xf,
+} IMG_NUM_FORMAT;
+typedef enum TileType {
+ ARRAY_COLOR_TILE = 0x0,
+ ARRAY_DEPTH_TILE = 0x1,
+} TileType;
+typedef enum NonDispTilingOrder {
+ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
+ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
+} NonDispTilingOrder;
+typedef enum MicroTileMode {
+ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
+ ADDR_SURF_THIN_MICRO_TILING = 0x1,
+ ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
+ ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
+ ADDR_SURF_THICK_MICRO_TILING = 0x4,
+} MicroTileMode;
+typedef enum TileSplit {
+ ADDR_SURF_TILE_SPLIT_64B = 0x0,
+ ADDR_SURF_TILE_SPLIT_128B = 0x1,
+ ADDR_SURF_TILE_SPLIT_256B = 0x2,
+ ADDR_SURF_TILE_SPLIT_512B = 0x3,
+ ADDR_SURF_TILE_SPLIT_1KB = 0x4,
+ ADDR_SURF_TILE_SPLIT_2KB = 0x5,
+ ADDR_SURF_TILE_SPLIT_4KB = 0x6,
+} TileSplit;
+typedef enum SampleSplit {
+ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
+ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
+ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
+ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
+} SampleSplit;
+typedef enum PipeConfig {
+ ADDR_SURF_P2 = 0x0,
+ ADDR_SURF_P2_RESERVED0 = 0x1,
+ ADDR_SURF_P2_RESERVED1 = 0x2,
+ ADDR_SURF_P2_RESERVED2 = 0x3,
+ ADDR_SURF_P4_8x16 = 0x4,
+ ADDR_SURF_P4_16x16 = 0x5,
+ ADDR_SURF_P4_16x32 = 0x6,
+ ADDR_SURF_P4_32x32 = 0x7,
+ ADDR_SURF_P8_16x16_8x16 = 0x8,
+ ADDR_SURF_P8_16x32_8x16 = 0x9,
+ ADDR_SURF_P8_32x32_8x16 = 0xa,
+ ADDR_SURF_P8_16x32_16x16 = 0xb,
+ ADDR_SURF_P8_32x32_16x16 = 0xc,
+ ADDR_SURF_P8_32x32_16x32 = 0xd,
+ ADDR_SURF_P8_32x64_32x32 = 0xe,
+ ADDR_SURF_P8_RESERVED0 = 0xf,
+ ADDR_SURF_P16_32x32_8x16 = 0x10,
+ ADDR_SURF_P16_32x32_16x16 = 0x11,
+} PipeConfig;
+typedef enum NumBanks {
+ ADDR_SURF_2_BANK = 0x0,
+ ADDR_SURF_4_BANK = 0x1,
+ ADDR_SURF_8_BANK = 0x2,
+ ADDR_SURF_16_BANK = 0x3,
+} NumBanks;
+typedef enum BankWidth {
+ ADDR_SURF_BANK_WIDTH_1 = 0x0,
+ ADDR_SURF_BANK_WIDTH_2 = 0x1,
+ ADDR_SURF_BANK_WIDTH_4 = 0x2,
+ ADDR_SURF_BANK_WIDTH_8 = 0x3,
+} BankWidth;
+typedef enum BankHeight {
+ ADDR_SURF_BANK_HEIGHT_1 = 0x0,
+ ADDR_SURF_BANK_HEIGHT_2 = 0x1,
+ ADDR_SURF_BANK_HEIGHT_4 = 0x2,
+ ADDR_SURF_BANK_HEIGHT_8 = 0x3,
+} BankHeight;
+typedef enum BankWidthHeight {
+ ADDR_SURF_BANK_WH_1 = 0x0,
+ ADDR_SURF_BANK_WH_2 = 0x1,
+ ADDR_SURF_BANK_WH_4 = 0x2,
+ ADDR_SURF_BANK_WH_8 = 0x3,
+} BankWidthHeight;
+typedef enum MacroTileAspect {
+ ADDR_SURF_MACRO_ASPECT_1 = 0x0,
+ ADDR_SURF_MACRO_ASPECT_2 = 0x1,
+ ADDR_SURF_MACRO_ASPECT_4 = 0x2,
+ ADDR_SURF_MACRO_ASPECT_8 = 0x3,
+} MacroTileAspect;
+typedef enum GATCL1RequestType {
+ GATCL1_TYPE_NORMAL = 0x0,
+ GATCL1_TYPE_SHOOTDOWN = 0x1,
+ GATCL1_TYPE_BYPASS = 0x2,
+} GATCL1RequestType;
+typedef enum TCC_CACHE_POLICIES {
+ TCC_CACHE_POLICY_LRU = 0x0,
+ TCC_CACHE_POLICY_STREAM = 0x1,
+} TCC_CACHE_POLICIES;
+typedef enum MTYPE {
+ MTYPE_NC_NV = 0x0,
+ MTYPE_NC = 0x1,
+ MTYPE_CC = 0x2,
+ MTYPE_UC = 0x3,
+} MTYPE;
+typedef enum PERFMON_COUNTER_MODE {
+ PERFMON_COUNTER_MODE_ACCUM = 0x0,
+ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
+ PERFMON_COUNTER_MODE_MAX = 0x2,
+ PERFMON_COUNTER_MODE_DIRTY = 0x3,
+ PERFMON_COUNTER_MODE_SAMPLE = 0x4,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
+ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
+ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
+ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
+ PERFMON_COUNTER_MODE_RESERVED = 0xf,
+} PERFMON_COUNTER_MODE;
+typedef enum PERFMON_SPM_MODE {
+ PERFMON_SPM_MODE_OFF = 0x0,
+ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
+ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
+ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
+ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
+ PERFMON_SPM_MODE_RESERVED_5 = 0x5,
+ PERFMON_SPM_MODE_RESERVED_6 = 0x6,
+ PERFMON_SPM_MODE_RESERVED_7 = 0x7,
+ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
+ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
+ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
+} PERFMON_SPM_MODE;
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0x0,
+ ARRAY_TILED = 0x1,
+} SurfaceTiling;
+typedef enum SurfaceArray {
+ ARRAY_1D = 0x0,
+ ARRAY_2D = 0x1,
+ ARRAY_3D = 0x2,
+ ARRAY_3D_SLICE = 0x3,
+} SurfaceArray;
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0x0,
+ ARRAY_2D_COLOR = 0x1,
+ ARRAY_3D_SLICE_COLOR = 0x3,
+} ColorArray;
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0x0,
+ ARRAY_2D_DEPTH = 0x1,
+} DepthArray;
+typedef enum ENUM_NUM_SIMD_PER_CU {
+ NUM_SIMD_PER_CU = 0x4,
+} ENUM_NUM_SIMD_PER_CU;
+typedef enum MEM_PWR_FORCE_CTRL {
+ NO_FORCE_REQUEST = 0x0,
+ FORCE_LIGHT_SLEEP_REQUEST = 0x1,
+ FORCE_DEEP_SLEEP_REQUEST = 0x2,
+ FORCE_SHUT_DOWN_REQUEST = 0x3,
+} MEM_PWR_FORCE_CTRL;
+typedef enum MEM_PWR_FORCE_CTRL2 {
+ NO_FORCE_REQ = 0x0,
+ FORCE_LIGHT_SLEEP_REQ = 0x1,
+} MEM_PWR_FORCE_CTRL2;
+typedef enum MEM_PWR_DIS_CTRL {
+ ENABLE_MEM_PWR_CTRL = 0x0,
+ DISABLE_MEM_PWR_CTRL = 0x1,
+} MEM_PWR_DIS_CTRL;
+typedef enum MEM_PWR_SEL_CTRL {
+ DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
+ DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
+ DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
+} MEM_PWR_SEL_CTRL;
+typedef enum MEM_PWR_SEL_CTRL2 {
+ DYNAMIC_DEEP_SLEEP_EN = 0x0,
+ DYNAMIC_LIGHT_SLEEP_EN = 0x1,
+} MEM_PWR_SEL_CTRL2;
+
+#endif /* GMC_8_2_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h
new file mode 100644
index 000000000000..c5dd8ecdd3e1
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h
@@ -0,0 +1,7850 @@
+/*
+ * GMC_8_2 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GMC_8_2_SH_MASK_H
+#define GMC_8_2_SH_MASK_H
+
+#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
+#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
+#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
+#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
+#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
+#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
+#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
+#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
+#define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
+#define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
+#define MC_CONFIG__MCDT_WR_ENABLE_MASK 0x20
+#define MC_CONFIG__MCDT_WR_ENABLE__SHIFT 0x5
+#define MC_CONFIG__MCDU_WR_ENABLE_MASK 0x40
+#define MC_CONFIG__MCDU_WR_ENABLE__SHIFT 0x6
+#define MC_CONFIG__MCDV_WR_ENABLE_MASK 0x80
+#define MC_CONFIG__MCDV_WR_ENABLE__SHIFT 0x7
+#define MC_CONFIG__MC_RD_ENABLE_MASK 0x700
+#define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x8
+#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000
+#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x1f
+#define MC_ARB_ATOMIC__TC_GRP_MASK 0x7
+#define MC_ARB_ATOMIC__TC_GRP__SHIFT 0x0
+#define MC_ARB_ATOMIC__TC_GRP_EN_MASK 0x8
+#define MC_ARB_ATOMIC__TC_GRP_EN__SHIFT 0x3
+#define MC_ARB_ATOMIC__SDMA_GRP_MASK 0x70
+#define MC_ARB_ATOMIC__SDMA_GRP__SHIFT 0x4
+#define MC_ARB_ATOMIC__SDMA_GRP_EN_MASK 0x80
+#define MC_ARB_ATOMIC__SDMA_GRP_EN__SHIFT 0x7
+#define MC_ARB_ATOMIC__OUTSTANDING_MASK 0xff00
+#define MC_ARB_ATOMIC__OUTSTANDING__SHIFT 0x8
+#define MC_ARB_ATOMIC__ATOMIC_RTN_GRP_MASK 0xff0000
+#define MC_ARB_ATOMIC__ATOMIC_RTN_GRP__SHIFT 0x10
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0_MASK 0x1
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0__SHIFT 0x0
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1_MASK 0x2
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1__SHIFT 0x1
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2_MASK 0x4
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2__SHIFT 0x2
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3__SHIFT 0x3
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4__SHIFT 0x4
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5_MASK 0x20
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5__SHIFT 0x5
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6_MASK 0x40
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6__SHIFT 0x6
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7_MASK 0x80
+#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7__SHIFT 0x7
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0_MASK 0x100
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1_MASK 0x200
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1__SHIFT 0x9
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2_MASK 0x400
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x800
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3__SHIFT 0xb
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4_MASK 0x1000
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4__SHIFT 0xc
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5_MASK 0x2000
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5__SHIFT 0xd
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6_MASK 0x4000
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT 0xe
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7_MASK 0x8000
+#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7__SHIFT 0xf
+#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD_MASK 0x70000
+#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10
+#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR_MASK 0x380000
+#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR__SHIFT 0x13
+#define MC_ARB_AGE_CNTL__TIMER_STALL_RD_MASK 0x400000
+#define MC_ARB_AGE_CNTL__TIMER_STALL_RD__SHIFT 0x16
+#define MC_ARB_AGE_CNTL__TIMER_STALL_WR_MASK 0x800000
+#define MC_ARB_AGE_CNTL__TIMER_STALL_WR__SHIFT 0x17
+#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD_MASK 0x1000000
+#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD__SHIFT 0x18
+#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR_MASK 0x2000000
+#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR__SHIFT 0x19
+#define MC_ARB_RET_CREDITS2__ACP_WR_MASK 0xff
+#define MC_ARB_RET_CREDITS2__ACP_WR__SHIFT 0x0
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD_MASK 0x100
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT 0x8
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR_MASK 0x200
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR__SHIFT 0x9
+#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG_MASK 0x400
+#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG__SHIFT 0xa
+#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG_MASK 0x800
+#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG__SHIFT 0xb
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD_MASK 0x1000
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD__SHIFT 0xc
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR_MASK 0x2000
+#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR__SHIFT 0xd
+#define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD_MASK 0x4000
+#define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD__SHIFT 0xe
+#define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR_MASK 0x8000
+#define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR__SHIFT 0xf
+#define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED_MASK 0xff0000
+#define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED__SHIFT 0x10
+#define MC_ARB_FED_CNTL__MODE_MASK 0x3
+#define MC_ARB_FED_CNTL__MODE__SHIFT 0x0
+#define MC_ARB_FED_CNTL__WR_ERR_MASK 0xc
+#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x2
+#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10
+#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x4
+#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK_MASK 0x20
+#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK__SHIFT 0x5
+#define MC_ARB_FED_CNTL__USE_LEGACY_NACK_MASK 0x40
+#define MC_ARB_FED_CNTL__USE_LEGACY_NACK__SHIFT 0x6
+#define MC_ARB_FED_CNTL__DEBUG_RSV_MASK 0xffffff80
+#define MC_ARB_FED_CNTL__DEBUG_RSV__SHIFT 0x7
+#define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x1
+#define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x0
+#define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x2
+#define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x1
+#define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x4
+#define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x2
+#define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8
+#define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x3
+#define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10
+#define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x4
+#define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x20
+#define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x5
+#define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x40
+#define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x6
+#define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x80
+#define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x7
+#define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x100
+#define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8
+#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x200
+#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x9
+#define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x400
+#define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa
+#define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x800
+#define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0xb
+#define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x1000
+#define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0xc
+#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x2000
+#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0xd
+#define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x4000
+#define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0xe
+#define MC_ARB_GECC2_STATUS__RSVD3_MASK 0x8000
+#define MC_ARB_GECC2_STATUS__RSVD3__SHIFT 0xf
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0_MASK 0x10000
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0_MASK 0x20000
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0__SHIFT 0x11
+#define MC_ARB_GECC2_STATUS__RSVD4_MASK 0xc0000
+#define MC_ARB_GECC2_STATUS__RSVD4__SHIFT 0x12
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1_MASK 0x100000
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1__SHIFT 0x14
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1_MASK 0x200000
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1__SHIFT 0x15
+#define MC_ARB_GECC2_STATUS__RSVD5_MASK 0xc00000
+#define MC_ARB_GECC2_STATUS__RSVD5__SHIFT 0x16
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0_MASK 0x1000000
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0__SHIFT 0x18
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0_MASK 0x2000000
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0__SHIFT 0x19
+#define MC_ARB_GECC2_STATUS__RSVD6_MASK 0xc000000
+#define MC_ARB_GECC2_STATUS__RSVD6__SHIFT 0x1a
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1_MASK 0x10000000
+#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1__SHIFT 0x1c
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1_MASK 0x20000000
+#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d
+#define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0xf
+#define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x0
+#define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10
+#define MC_ARB_GECC2_MISC__COL10_HACK__SHIFT 0x4
+#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY_MASK 0x20
+#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY__SHIFT 0x5
+#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY_MASK 0x40
+#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY__SHIFT 0x6
+#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL_MASK 0x80
+#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL__SHIFT 0x7
+#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE_MASK 0x100
+#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE__SHIFT 0x8
+#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY_MASK 0x200
+#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY__SHIFT 0x9
+#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN_MASK 0x400
+#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN__SHIFT 0xa
+#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN_MASK 0x800
+#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN__SHIFT 0xb
+#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY_MASK 0x1000
+#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY__SHIFT 0xc
+#define MC_ARB_GECC2_MISC__DEBUG_RSV_MASK 0xffffe000
+#define MC_ARB_GECC2_MISC__DEBUG_RSV__SHIFT 0xd
+#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x3
+#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x0
+#define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x4
+#define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x2
+#define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x18
+#define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x3
+#define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x20
+#define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x5
+#define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0xff
+#define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x0
+#define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0xff00
+#define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8
+#define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0xff0000
+#define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10
+#define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000
+#define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x18
+#define MC_ARB_PERF_CID__CH0_MASK 0xff
+#define MC_ARB_PERF_CID__CH0__SHIFT 0x0
+#define MC_ARB_PERF_CID__CH1_MASK 0xff00
+#define MC_ARB_PERF_CID__CH1__SHIFT 0x8
+#define MC_ARB_PERF_CID__CH0_EN_MASK 0x10000
+#define MC_ARB_PERF_CID__CH0_EN__SHIFT 0x10
+#define MC_ARB_PERF_CID__CH1_EN_MASK 0x20000
+#define MC_ARB_PERF_CID__CH1_EN__SHIFT 0x11
+#define MC_ARB_SNOOP__TC_GRP_RD_MASK 0x7
+#define MC_ARB_SNOOP__TC_GRP_RD__SHIFT 0x0
+#define MC_ARB_SNOOP__TC_GRP_RD_EN_MASK 0x8
+#define MC_ARB_SNOOP__TC_GRP_RD_EN__SHIFT 0x3
+#define MC_ARB_SNOOP__TC_GRP_WR_MASK 0x70
+#define MC_ARB_SNOOP__TC_GRP_WR__SHIFT 0x4
+#define MC_ARB_SNOOP__TC_GRP_WR_EN_MASK 0x80
+#define MC_ARB_SNOOP__TC_GRP_WR_EN__SHIFT 0x7
+#define MC_ARB_SNOOP__SDMA_GRP_RD_MASK 0x700
+#define MC_ARB_SNOOP__SDMA_GRP_RD__SHIFT 0x8
+#define MC_ARB_SNOOP__SDMA_GRP_RD_EN_MASK 0x800
+#define MC_ARB_SNOOP__SDMA_GRP_RD_EN__SHIFT 0xb
+#define MC_ARB_SNOOP__SDMA_GRP_WR_MASK 0x7000
+#define MC_ARB_SNOOP__SDMA_GRP_WR__SHIFT 0xc
+#define MC_ARB_SNOOP__SDMA_GRP_WR_EN_MASK 0x8000
+#define MC_ARB_SNOOP__SDMA_GRP_WR_EN__SHIFT 0xf
+#define MC_ARB_SNOOP__OUTSTANDING_RD_MASK 0xff0000
+#define MC_ARB_SNOOP__OUTSTANDING_RD__SHIFT 0x10
+#define MC_ARB_SNOOP__OUTSTANDING_WR_MASK 0xff000000
+#define MC_ARB_SNOOP__OUTSTANDING_WR__SHIFT 0x18
+#define MC_ARB_GRUB__GRUB_WATERMARK_MASK 0xff
+#define MC_ARB_GRUB__GRUB_WATERMARK__SHIFT 0x0
+#define MC_ARB_GRUB__GRUB_WATERMARK_PRI_MASK 0xff00
+#define MC_ARB_GRUB__GRUB_WATERMARK_PRI__SHIFT 0x8
+#define MC_ARB_GRUB__GRUB_WATERMARK_MED_MASK 0xff0000
+#define MC_ARB_GRUB__GRUB_WATERMARK_MED__SHIFT 0x10
+#define MC_ARB_GRUB__REG_WR_EN_MASK 0x3000000
+#define MC_ARB_GRUB__REG_WR_EN__SHIFT 0x18
+#define MC_ARB_GRUB__REG_RD_SEL_MASK 0x4000000
+#define MC_ARB_GRUB__REG_RD_SEL__SHIFT 0x1a
+#define MC_ARB_GECC2__ENABLE_MASK 0x1
+#define MC_ARB_GECC2__ENABLE__SHIFT 0x0
+#define MC_ARB_GECC2__ECC_MODE_MASK 0x6
+#define MC_ARB_GECC2__ECC_MODE__SHIFT 0x1
+#define MC_ARB_GECC2__PAGE_BIT0_MASK 0x18
+#define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x3
+#define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x60
+#define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x5
+#define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x780
+#define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x7
+#define MC_ARB_GECC2__READ_ERR_MASK 0x3800
+#define MC_ARB_GECC2__READ_ERR__SHIFT 0xb
+#define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x4000
+#define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0xe
+#define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x1f8000
+#define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0xf
+#define MC_ARB_GECC2__WRADDR_CONV_MASK 0x200000
+#define MC_ARB_GECC2__WRADDR_CONV__SHIFT 0x15
+#define MC_ARB_GECC2__RMWRD_UNCOR_POISON_MASK 0x400000
+#define MC_ARB_GECC2__RMWRD_UNCOR_POISON__SHIFT 0x16
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0xff
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x0
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0xff00
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x8
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0xff0000
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x10
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000
+#define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x18
+#define MC_ARB_ADDR_SWIZ0__A8_MASK 0xf
+#define MC_ARB_ADDR_SWIZ0__A8__SHIFT 0x0
+#define MC_ARB_ADDR_SWIZ0__A9_MASK 0xf0
+#define MC_ARB_ADDR_SWIZ0__A9__SHIFT 0x4
+#define MC_ARB_ADDR_SWIZ0__A10_MASK 0xf00
+#define MC_ARB_ADDR_SWIZ0__A10__SHIFT 0x8
+#define MC_ARB_ADDR_SWIZ0__A11_MASK 0xf000
+#define MC_ARB_ADDR_SWIZ0__A11__SHIFT 0xc
+#define MC_ARB_ADDR_SWIZ0__A12_MASK 0xf0000
+#define MC_ARB_ADDR_SWIZ0__A12__SHIFT 0x10
+#define MC_ARB_ADDR_SWIZ0__A13_MASK 0xf00000
+#define MC_ARB_ADDR_SWIZ0__A13__SHIFT 0x14
+#define MC_ARB_ADDR_SWIZ0__A14_MASK 0xf000000
+#define MC_ARB_ADDR_SWIZ0__A14__SHIFT 0x18
+#define MC_ARB_ADDR_SWIZ0__A15_MASK 0xf0000000
+#define MC_ARB_ADDR_SWIZ0__A15__SHIFT 0x1c
+#define MC_ARB_ADDR_SWIZ1__A16_MASK 0xf
+#define MC_ARB_ADDR_SWIZ1__A16__SHIFT 0x0
+#define MC_ARB_ADDR_SWIZ1__A17_MASK 0xf0
+#define MC_ARB_ADDR_SWIZ1__A17__SHIFT 0x4
+#define MC_ARB_ADDR_SWIZ1__A18_MASK 0xf00
+#define MC_ARB_ADDR_SWIZ1__A18__SHIFT 0x8
+#define MC_ARB_ADDR_SWIZ1__A19_MASK 0xf000
+#define MC_ARB_ADDR_SWIZ1__A19__SHIFT 0xc
+#define MC_ARB_MISC3__NO_GECC_EXT_EOB_MASK 0x1
+#define MC_ARB_MISC3__NO_GECC_EXT_EOB__SHIFT 0x0
+#define MC_ARB_MISC3__CHAN4_EN_MASK 0x2
+#define MC_ARB_MISC3__CHAN4_EN__SHIFT 0x1
+#define MC_ARB_MISC3__CHAN4_ARB_SEL_MASK 0x4
+#define MC_ARB_MISC3__CHAN4_ARB_SEL__SHIFT 0x2
+#define MC_ARB_MISC3__UVD_URG_MODE_MASK 0x8
+#define MC_ARB_MISC3__UVD_URG_MODE__SHIFT 0x3
+#define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN_MASK 0x10
+#define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN__SHIFT 0x4
+#define MC_ARB_MISC3__TBD_FIELD_MASK 0xffffffe0
+#define MC_ARB_MISC3__TBD_FIELD__SHIFT 0x5
+#define MC_ARB_GRUB_PROMOTE__URGENT_RD_MASK 0xff
+#define MC_ARB_GRUB_PROMOTE__URGENT_RD__SHIFT 0x0
+#define MC_ARB_GRUB_PROMOTE__URGENT_WR_MASK 0xff00
+#define MC_ARB_GRUB_PROMOTE__URGENT_WR__SHIFT 0x8
+#define MC_ARB_GRUB_PROMOTE__PROMOTE_RD_MASK 0xff0000
+#define MC_ARB_GRUB_PROMOTE__PROMOTE_RD__SHIFT 0x10
+#define MC_ARB_GRUB_PROMOTE__PROMOTE_WR_MASK 0xff000000
+#define MC_ARB_GRUB_PROMOTE__PROMOTE_WR__SHIFT 0x18
+#define MC_ARB_RTT_DATA__PATTERN_MASK 0xff
+#define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x0
+#define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x1
+#define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x0
+#define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x2
+#define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x1
+#define MC_ARB_RTT_CNTL0__START_R2W_MASK 0xc
+#define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x2
+#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x10
+#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x4
+#define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x20
+#define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x5
+#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x40
+#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x6
+#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x80
+#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x7
+#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x100
+#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x8
+#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x200
+#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x9
+#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x400
+#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa
+#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x3800
+#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0xb
+#define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x4000
+#define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0xe
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x8000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0xf
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x10000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x10
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x20000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x11
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x40000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x12
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x80000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x13
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x100000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x14
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x200000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x15
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x400000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x16
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x800000
+#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x17
+#define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x1000000
+#define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x18
+#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x2000000
+#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x19
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x1f
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x0
+#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x20
+#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x5
+#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x1fc0
+#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x6
+#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0xfe000
+#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0xd
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x1f00000
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x14
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000
+#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x19
+#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000
+#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x1e
+#define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x3f
+#define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x0
+#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0xfc0
+#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x6
+#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x1000
+#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0xc
+#define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x2000
+#define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0xd
+#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x3
+#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x0
+#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0xc
+#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x2
+#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0xff0
+#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x4
+#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x1f000
+#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0xc
+#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x1fe0000
+#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x11
+#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000
+#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x19
+#define MC_ARB_CAC_CNTL__ENABLE_MASK 0x1
+#define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x0
+#define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x7e
+#define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x1
+#define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x1f80
+#define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x7
+#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x2000
+#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0xd
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x20
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x5
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x40
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x6
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x80
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x7
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x100
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x8
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x200
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x9
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x400
+#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa
+#define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x800
+#define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0xb
+#define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x1000
+#define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0xc
+#define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x2000
+#define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0xd
+#define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x3c000
+#define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0xe
+#define MC_ARB_MISC2__GECC_MASK 0x40000
+#define MC_ARB_MISC2__GECC__SHIFT 0x12
+#define MC_ARB_MISC2__GECC_RST_MASK 0x80000
+#define MC_ARB_MISC2__GECC_RST__SHIFT 0x13
+#define MC_ARB_MISC2__GECC_STATUS_MASK 0x100000
+#define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x14
+#define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x1e00000
+#define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x15
+#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0xe000000
+#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x19
+#define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000
+#define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x1c
+#define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000
+#define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d
+#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000
+#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x1e
+#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000
+#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x1f
+#define MC_ARB_MISC__STICKY_RFSH_MASK 0x1
+#define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x0
+#define MC_ARB_MISC__IDLE_RFSH_MASK 0x2
+#define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x1
+#define MC_ARB_MISC__STUTTER_RFSH_MASK 0x4
+#define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x2
+#define MC_ARB_MISC__CHAN_COUPLE_MASK 0x7f8
+#define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x3
+#define MC_ARB_MISC__HARSHNESS_MASK 0x7f800
+#define MC_ARB_MISC__HARSHNESS__SHIFT 0xb
+#define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x80000
+#define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x13
+#define MC_ARB_MISC__CALI_ENABLE_MASK 0x100000
+#define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x14
+#define MC_ARB_MISC__CALI_RATES_MASK 0x600000
+#define MC_ARB_MISC__CALI_RATES__SHIFT 0x15
+#define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x800000
+#define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x17
+#define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x1000000
+#define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x18
+#define MC_ARB_MISC__DISPURG_STALL_MASK 0x2000000
+#define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x19
+#define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000
+#define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x1a
+#define MC_ARB_MISC__EXTEND_WEIGHT_MASK 0x40000000
+#define MC_ARB_MISC__EXTEND_WEIGHT__SHIFT 0x1e
+#define MC_ARB_MISC__ACPURG_STALL_MASK 0x80000000
+#define MC_ARB_MISC__ACPURG_STALL__SHIFT 0x1f
+#define MC_ARB_BANKMAP__BANK0_MASK 0xf
+#define MC_ARB_BANKMAP__BANK0__SHIFT 0x0
+#define MC_ARB_BANKMAP__BANK1_MASK 0xf0
+#define MC_ARB_BANKMAP__BANK1__SHIFT 0x4
+#define MC_ARB_BANKMAP__BANK2_MASK 0xf00
+#define MC_ARB_BANKMAP__BANK2__SHIFT 0x8
+#define MC_ARB_BANKMAP__BANK3_MASK 0xf000
+#define MC_ARB_BANKMAP__BANK3__SHIFT 0xc
+#define MC_ARB_BANKMAP__RANK_MASK 0xf0000
+#define MC_ARB_BANKMAP__RANK__SHIFT 0x10
+#define MC_ARB_RAMCFG__NOOFBANK_MASK 0x3
+#define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x0
+#define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x4
+#define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x2
+#define MC_ARB_RAMCFG__NOOFROWS_MASK 0x38
+#define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x3
+#define MC_ARB_RAMCFG__NOOFCOLS_MASK 0xc0
+#define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x6
+#define MC_ARB_RAMCFG__CHANSIZE_MASK 0x100
+#define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x8
+#define MC_ARB_RAMCFG__RSV_1_MASK 0x200
+#define MC_ARB_RAMCFG__RSV_1__SHIFT 0x9
+#define MC_ARB_RAMCFG__RSV_2_MASK 0x400
+#define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa
+#define MC_ARB_RAMCFG__RSV_3_MASK 0x800
+#define MC_ARB_RAMCFG__RSV_3__SHIFT 0xb
+#define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x1000
+#define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0xc
+#define MC_ARB_RAMCFG__RSV_4_MASK 0x3e000
+#define MC_ARB_RAMCFG__RSV_4__SHIFT 0xd
+#define MC_ARB_POP__ENABLE_ARB_MASK 0x1
+#define MC_ARB_POP__ENABLE_ARB__SHIFT 0x0
+#define MC_ARB_POP__SPEC_OPEN_MASK 0x2
+#define MC_ARB_POP__SPEC_OPEN__SHIFT 0x1
+#define MC_ARB_POP__POP_DEPTH_MASK 0x3c
+#define MC_ARB_POP__POP_DEPTH__SHIFT 0x2
+#define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0xfc0
+#define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x6
+#define MC_ARB_POP__SKID_DEPTH_MASK 0x7000
+#define MC_ARB_POP__SKID_DEPTH__SHIFT 0xc
+#define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x18000
+#define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0xf
+#define MC_ARB_POP__QUICK_STOP_MASK 0x20000
+#define MC_ARB_POP__QUICK_STOP__SHIFT 0x11
+#define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x40000
+#define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x12
+#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x80000
+#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x13
+#define MC_ARB_MINCLKS__READ_CLKS_MASK 0xff
+#define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x0
+#define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0xff00
+#define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x8
+#define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x10000
+#define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x10
+#define MC_ARB_MINCLKS__RW_SWITCH_HARSH_MASK 0x60000
+#define MC_ARB_MINCLKS__RW_SWITCH_HARSH__SHIFT 0x11
+#define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0xff
+#define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x0
+#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x100
+#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x8
+#define MC_ARB_SQM_CNTL__SQM_RDY16_MASK 0x200
+#define MC_ARB_SQM_CNTL__SQM_RDY16__SHIFT 0x9
+#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0xfc00
+#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa
+#define MC_ARB_SQM_CNTL__RATIO_MASK 0xff0000
+#define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x10
+#define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000
+#define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x18
+#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0xf
+#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x0
+#define MC_ARB_ADDR_HASH__COL_XOR_MASK 0xff0
+#define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x4
+#define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0xffff000
+#define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0xc
+#define MC_ARB_DRAM_TIMING__ACTRD_MASK 0xff
+#define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x0
+#define MC_ARB_DRAM_TIMING__ACTWR_MASK 0xff00
+#define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x8
+#define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0xff0000
+#define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x10
+#define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000
+#define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x18
+#define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0xff
+#define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x0
+#define MC_ARB_DRAM_TIMING2__RP_MASK 0xff00
+#define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x8
+#define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0xff0000
+#define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x10
+#define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000
+#define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x18
+#define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x3
+#define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x0
+#define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x4
+#define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x2
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x8
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x3
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x10
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x4
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x20
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x5
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x40
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x6
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x80
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x7
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x100
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x8
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x200
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x9
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x400
+#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa
+#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK 0x800
+#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI__SHIFT 0xb
+#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP_MASK 0x1000
+#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP__SHIFT 0xc
+#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG_MASK 0x2000
+#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG__SHIFT 0xd
+#define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x3
+#define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x0
+#define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x4
+#define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x2
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x8
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x3
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x10
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x4
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x20
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x5
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x40
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x6
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x80
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x7
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x100
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x8
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x200
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x9
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x400
+#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa
+#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK 0x800
+#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI__SHIFT 0xb
+#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP_MASK 0x1000
+#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP__SHIFT 0xc
+#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG_MASK 0x2000
+#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG__SHIFT 0xd
+#define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x3
+#define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x0
+#define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0xc
+#define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x2
+#define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x30
+#define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x4
+#define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0xc0
+#define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x6
+#define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x300
+#define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x8
+#define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0xc00
+#define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0xa
+#define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x3000
+#define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0xc
+#define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0xc000
+#define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0xe
+#define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0xff0000
+#define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x10
+#define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x3
+#define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x0
+#define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0xc
+#define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x2
+#define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x30
+#define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x4
+#define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0xc0
+#define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x6
+#define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x300
+#define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x8
+#define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0xc00
+#define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0xa
+#define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x3000
+#define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0xc
+#define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0xc000
+#define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0xe
+#define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0xff0000
+#define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x10
+#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x1
+#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x0
+#define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x6
+#define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x1
+#define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x8
+#define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x3
+#define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x10
+#define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x4
+#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x1
+#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x0
+#define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x6
+#define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x1
+#define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x8
+#define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x3
+#define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x10
+#define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x4
+#define MC_ARB_LAZY0_RD__GROUP0_MASK 0xff
+#define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_LAZY0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_LAZY0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_LAZY0_WR__GROUP0_MASK 0xff
+#define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_LAZY0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_LAZY0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_LAZY1_RD__GROUP4_MASK 0xff
+#define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_LAZY1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_LAZY1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_LAZY1_WR__GROUP4_MASK 0xff
+#define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_LAZY1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_LAZY1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x3
+#define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x0
+#define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0xc
+#define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x2
+#define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x30
+#define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x4
+#define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0xc0
+#define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x6
+#define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x300
+#define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x8
+#define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0xc00
+#define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0xa
+#define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x3000
+#define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0xc
+#define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0xc000
+#define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0xe
+#define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x10000
+#define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x10
+#define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x20000
+#define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x11
+#define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x40000
+#define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x12
+#define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x80000
+#define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x13
+#define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x100000
+#define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x14
+#define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x200000
+#define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x15
+#define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x400000
+#define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x16
+#define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x800000
+#define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x17
+#define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x1000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x18
+#define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x2000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x19
+#define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x4000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x1a
+#define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x8000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x1b
+#define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x1c
+#define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d
+#define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x1e
+#define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000
+#define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x1f
+#define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x3
+#define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x0
+#define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0xc
+#define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x2
+#define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x30
+#define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x4
+#define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0xc0
+#define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x6
+#define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x300
+#define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x8
+#define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0xc00
+#define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0xa
+#define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x3000
+#define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0xc
+#define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0xc000
+#define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0xe
+#define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x10000
+#define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x10
+#define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x20000
+#define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x11
+#define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x40000
+#define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x12
+#define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x80000
+#define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x13
+#define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x100000
+#define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x14
+#define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x200000
+#define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x15
+#define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x400000
+#define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x16
+#define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x800000
+#define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x17
+#define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x1000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x18
+#define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x2000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x19
+#define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x4000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x1a
+#define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x8000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x1b
+#define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x1c
+#define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d
+#define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x1e
+#define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000
+#define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x1f
+#define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x1
+#define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x0
+#define MC_ARB_RFSH_CNTL__URG0_MASK 0x3e
+#define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x1
+#define MC_ARB_RFSH_CNTL__URG1_MASK 0x7c0
+#define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x6
+#define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x800
+#define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0xb
+#define MC_ARB_RFSH_CNTL__SINGLE_BANK_MASK 0x1000
+#define MC_ARB_RFSH_CNTL__SINGLE_BANK__SHIFT 0xc
+#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH_MASK 0x2000
+#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH__SHIFT 0xd
+#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL_MASK 0x1c000
+#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL__SHIFT 0xe
+#define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0xff
+#define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x0
+#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x3
+#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x0
+#define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x4
+#define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x2
+#define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x8
+#define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x3
+#define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x10
+#define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x4
+#define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x20
+#define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x5
+#define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x40
+#define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x6
+#define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x80
+#define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x7
+#define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x300
+#define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x8
+#define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x400
+#define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0xa
+#define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x800
+#define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb
+#define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x1000
+#define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0xc
+#define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x2000
+#define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd
+#define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x4000
+#define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0xe
+#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000
+#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf
+#define MC_ARB_PM_CNTL__OVRR_RD0_BUSY_MASK 0x10000
+#define MC_ARB_PM_CNTL__OVRR_RD0_BUSY__SHIFT 0x10
+#define MC_ARB_PM_CNTL__OVRR_RD1_BUSY_MASK 0x20000
+#define MC_ARB_PM_CNTL__OVRR_RD1_BUSY__SHIFT 0x11
+#define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x40000
+#define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x12
+#define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x80000
+#define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x13
+#define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0xf00000
+#define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x14
+#define MC_ARB_PM_CNTL__OVRR_WR0_BUSY_MASK 0x1000000
+#define MC_ARB_PM_CNTL__OVRR_WR0_BUSY__SHIFT 0x18
+#define MC_ARB_PM_CNTL__OVRR_WR1_BUSY_MASK 0x2000000
+#define MC_ARB_PM_CNTL__OVRR_WR1_BUSY__SHIFT 0x19
+#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0xf
+#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x0
+#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0xf0
+#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x4
+#define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x100
+#define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x8
+#define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x200
+#define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x9
+#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
+#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
+#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0xf
+#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x0
+#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0xf0
+#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x4
+#define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x100
+#define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x8
+#define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x200
+#define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x9
+#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
+#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
+#define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0xff
+#define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x0
+#define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0xff00
+#define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x8
+#define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x10000
+#define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x10
+#define MC_ARB_LM_RD__STREAK_UBER_MASK 0x20000
+#define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x11
+#define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x40000
+#define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x12
+#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x80000
+#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x13
+#define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x100000
+#define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x14
+#define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0xe00000
+#define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x15
+#define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0xff
+#define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x0
+#define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0xff00
+#define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x8
+#define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x10000
+#define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x10
+#define MC_ARB_LM_WR__STREAK_UBER_MASK 0x20000
+#define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x11
+#define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x40000
+#define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x12
+#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x80000
+#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x13
+#define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x100000
+#define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x14
+#define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0xe00000
+#define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x15
+#define MC_ARB_LM_WR__MASKWR_LM_EOB_MASK 0x1000000
+#define MC_ARB_LM_WR__MASKWR_LM_EOB__SHIFT 0x18
+#define MC_ARB_LM_WR__ATOMIC_LM_EOB_MASK 0x2000000
+#define MC_ARB_LM_WR__ATOMIC_LM_EOB__SHIFT 0x19
+#define MC_ARB_LM_WR__ATOMIC_RTN_LM_EOB_MASK 0x4000000
+#define MC_ARB_LM_WR__ATOMIC_RTN_LM_EOB__SHIFT 0x1a
+#define MC_ARB_REMREQ__RD_WATER_MASK 0xff
+#define MC_ARB_REMREQ__RD_WATER__SHIFT 0x0
+#define MC_ARB_REMREQ__WR_WATER_MASK 0xff00
+#define MC_ARB_REMREQ__WR_WATER__SHIFT 0x8
+#define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0xf0000
+#define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x10
+#define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0xf00000
+#define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x14
+#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ_MASK 0x1000000
+#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ__SHIFT 0x18
+#define MC_ARB_REPLAY__ENABLE_RD_MASK 0x1
+#define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x0
+#define MC_ARB_REPLAY__ENABLE_WR_MASK 0x2
+#define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x1
+#define MC_ARB_REPLAY__WRACK_MODE_MASK 0x4
+#define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x2
+#define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x8
+#define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x3
+#define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x10
+#define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x4
+#define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x20
+#define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x5
+#define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x40
+#define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x6
+#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x80
+#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x7
+#define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x7f00
+#define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x8
+#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START_MASK 0x8000
+#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START__SHIFT 0xf
+#define MC_ARB_RET_CREDITS_RD__LCL_MASK 0xff
+#define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x0
+#define MC_ARB_RET_CREDITS_RD__HUB_MASK 0xff00
+#define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x8
+#define MC_ARB_RET_CREDITS_RD__DISP_MASK 0xff0000
+#define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x10
+#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000
+#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x18
+#define MC_ARB_RET_CREDITS_WR__LCL_MASK 0xff
+#define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x0
+#define MC_ARB_RET_CREDITS_WR__HUB_MASK 0xff00
+#define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x8
+#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0xff0000
+#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x10
+#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0xf000000
+#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x18
+#define MC_ARB_RET_CREDITS_WR__WRRET_BP_MASK 0x10000000
+#define MC_ARB_RET_CREDITS_WR__WRRET_BP__SHIFT 0x1c
+#define MC_ARB_MAX_LAT_CID__CID_CH0_MASK 0xff
+#define MC_ARB_MAX_LAT_CID__CID_CH0__SHIFT 0x0
+#define MC_ARB_MAX_LAT_CID__CID_CH1_MASK 0xff00
+#define MC_ARB_MAX_LAT_CID__CID_CH1__SHIFT 0x8
+#define MC_ARB_MAX_LAT_CID__WRITE_CH0_MASK 0x10000
+#define MC_ARB_MAX_LAT_CID__WRITE_CH0__SHIFT 0x10
+#define MC_ARB_MAX_LAT_CID__WRITE_CH1_MASK 0x20000
+#define MC_ARB_MAX_LAT_CID__WRITE_CH1__SHIFT 0x11
+#define MC_ARB_MAX_LAT_CID__REALTIME_CH0_MASK 0x40000
+#define MC_ARB_MAX_LAT_CID__REALTIME_CH0__SHIFT 0x12
+#define MC_ARB_MAX_LAT_CID__REALTIME_CH1_MASK 0x80000
+#define MC_ARB_MAX_LAT_CID__REALTIME_CH1__SHIFT 0x13
+#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY_MASK 0xffffffff
+#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY__SHIFT 0x0
+#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY_MASK 0xffffffff
+#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY__SHIFT 0x0
+#define MC_ARB_GRUB_REALTIME_RD__CB0_MASK 0x1
+#define MC_ARB_GRUB_REALTIME_RD__CB0__SHIFT 0x0
+#define MC_ARB_GRUB_REALTIME_RD__CBCMASK0_MASK 0x2
+#define MC_ARB_GRUB_REALTIME_RD__CBCMASK0__SHIFT 0x1
+#define MC_ARB_GRUB_REALTIME_RD__CBFMASK0_MASK 0x4
+#define MC_ARB_GRUB_REALTIME_RD__CBFMASK0__SHIFT 0x2
+#define MC_ARB_GRUB_REALTIME_RD__DB0_MASK 0x8
+#define MC_ARB_GRUB_REALTIME_RD__DB0__SHIFT 0x3
+#define MC_ARB_GRUB_REALTIME_RD__DBHTILE0_MASK 0x10
+#define MC_ARB_GRUB_REALTIME_RD__DBHTILE0__SHIFT 0x4
+#define MC_ARB_GRUB_REALTIME_RD__DBSTEN0_MASK 0x20
+#define MC_ARB_GRUB_REALTIME_RD__DBSTEN0__SHIFT 0x5
+#define MC_ARB_GRUB_REALTIME_RD__TC0_MASK 0x40
+#define MC_ARB_GRUB_REALTIME_RD__TC0__SHIFT 0x6
+#define MC_ARB_GRUB_REALTIME_RD__IA_MASK 0x80
+#define MC_ARB_GRUB_REALTIME_RD__IA__SHIFT 0x7
+#define MC_ARB_GRUB_REALTIME_RD__ACPG_MASK 0x100
+#define MC_ARB_GRUB_REALTIME_RD__ACPG__SHIFT 0x8
+#define MC_ARB_GRUB_REALTIME_RD__ACPO_MASK 0x200
+#define MC_ARB_GRUB_REALTIME_RD__ACPO__SHIFT 0x9
+#define MC_ARB_GRUB_REALTIME_RD__DMIF_MASK 0x400
+#define MC_ARB_GRUB_REALTIME_RD__DMIF__SHIFT 0xa
+#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0_MASK 0x800
+#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0__SHIFT 0xb
+#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1_MASK 0x1000
+#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1__SHIFT 0xc
+#define MC_ARB_GRUB_REALTIME_RD__DMIF_TW_MASK 0x2000
+#define MC_ARB_GRUB_REALTIME_RD__DMIF_TW__SHIFT 0xd
+#define MC_ARB_GRUB_REALTIME_RD__MCIF_MASK 0x4000
+#define MC_ARB_GRUB_REALTIME_RD__MCIF__SHIFT 0xe
+#define MC_ARB_GRUB_REALTIME_RD__RLC_MASK 0x8000
+#define MC_ARB_GRUB_REALTIME_RD__RLC__SHIFT 0xf
+#define MC_ARB_GRUB_REALTIME_RD__VMC_MASK 0x10000
+#define MC_ARB_GRUB_REALTIME_RD__VMC__SHIFT 0x10
+#define MC_ARB_GRUB_REALTIME_RD__SDMA1_MASK 0x20000
+#define MC_ARB_GRUB_REALTIME_RD__SDMA1__SHIFT 0x11
+#define MC_ARB_GRUB_REALTIME_RD__SMU_MASK 0x40000
+#define MC_ARB_GRUB_REALTIME_RD__SMU__SHIFT 0x12
+#define MC_ARB_GRUB_REALTIME_RD__VCE0_MASK 0x80000
+#define MC_ARB_GRUB_REALTIME_RD__VCE0__SHIFT 0x13
+#define MC_ARB_GRUB_REALTIME_RD__VCE1_MASK 0x100000
+#define MC_ARB_GRUB_REALTIME_RD__VCE1__SHIFT 0x14
+#define MC_ARB_GRUB_REALTIME_RD__XDMAM_MASK 0x200000
+#define MC_ARB_GRUB_REALTIME_RD__XDMAM__SHIFT 0x15
+#define MC_ARB_GRUB_REALTIME_RD__SDMA0_MASK 0x400000
+#define MC_ARB_GRUB_REALTIME_RD__SDMA0__SHIFT 0x16
+#define MC_ARB_GRUB_REALTIME_RD__HDP_MASK 0x800000
+#define MC_ARB_GRUB_REALTIME_RD__HDP__SHIFT 0x17
+#define MC_ARB_GRUB_REALTIME_RD__UMC_MASK 0x1000000
+#define MC_ARB_GRUB_REALTIME_RD__UMC__SHIFT 0x18
+#define MC_ARB_GRUB_REALTIME_RD__UVD_MASK 0x2000000
+#define MC_ARB_GRUB_REALTIME_RD__UVD__SHIFT 0x19
+#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0_MASK 0x4000000
+#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0__SHIFT 0x1a
+#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1_MASK 0x8000000
+#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1__SHIFT 0x1b
+#define MC_ARB_GRUB_REALTIME_RD__SEM_MASK 0x10000000
+#define MC_ARB_GRUB_REALTIME_RD__SEM__SHIFT 0x1c
+#define MC_ARB_GRUB_REALTIME_RD__SAMMSP_MASK 0x20000000
+#define MC_ARB_GRUB_REALTIME_RD__SAMMSP__SHIFT 0x1d
+#define MC_ARB_GRUB_REALTIME_RD__VP8_MASK 0x40000000
+#define MC_ARB_GRUB_REALTIME_RD__VP8__SHIFT 0x1e
+#define MC_ARB_GRUB_REALTIME_RD__ISP_MASK 0x80000000
+#define MC_ARB_GRUB_REALTIME_RD__ISP__SHIFT 0x1f
+#define MC_ARB_CG__CG_ARB_REQ_MASK 0xff
+#define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x0
+#define MC_ARB_CG__CG_ARB_RESP_MASK 0xff00
+#define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x8
+#define MC_ARB_CG__RSV_0_MASK 0xff0000
+#define MC_ARB_CG__RSV_0__SHIFT 0x10
+#define MC_ARB_CG__RSV_1_MASK 0xff000000
+#define MC_ARB_CG__RSV_1__SHIFT 0x18
+#define MC_ARB_GRUB_REALTIME_WR__CB0_MASK 0x1
+#define MC_ARB_GRUB_REALTIME_WR__CB0__SHIFT 0x0
+#define MC_ARB_GRUB_REALTIME_WR__CBCMASK0_MASK 0x2
+#define MC_ARB_GRUB_REALTIME_WR__CBCMASK0__SHIFT 0x1
+#define MC_ARB_GRUB_REALTIME_WR__CBFMASK0_MASK 0x4
+#define MC_ARB_GRUB_REALTIME_WR__CBFMASK0__SHIFT 0x2
+#define MC_ARB_GRUB_REALTIME_WR__CBIMMED0_MASK 0x8
+#define MC_ARB_GRUB_REALTIME_WR__CBIMMED0__SHIFT 0x3
+#define MC_ARB_GRUB_REALTIME_WR__DB0_MASK 0x10
+#define MC_ARB_GRUB_REALTIME_WR__DB0__SHIFT 0x4
+#define MC_ARB_GRUB_REALTIME_WR__DBHTILE0_MASK 0x20
+#define MC_ARB_GRUB_REALTIME_WR__DBHTILE0__SHIFT 0x5
+#define MC_ARB_GRUB_REALTIME_WR__DBSTEN0_MASK 0x40
+#define MC_ARB_GRUB_REALTIME_WR__DBSTEN0__SHIFT 0x6
+#define MC_ARB_GRUB_REALTIME_WR__TC0_MASK 0x80
+#define MC_ARB_GRUB_REALTIME_WR__TC0__SHIFT 0x7
+#define MC_ARB_GRUB_REALTIME_WR__SH_MASK 0x100
+#define MC_ARB_GRUB_REALTIME_WR__SH__SHIFT 0x8
+#define MC_ARB_GRUB_REALTIME_WR__ACPG_MASK 0x200
+#define MC_ARB_GRUB_REALTIME_WR__ACPG__SHIFT 0x9
+#define MC_ARB_GRUB_REALTIME_WR__ACPO_MASK 0x400
+#define MC_ARB_GRUB_REALTIME_WR__ACPO__SHIFT 0xa
+#define MC_ARB_GRUB_REALTIME_WR__MCIF_MASK 0x800
+#define MC_ARB_GRUB_REALTIME_WR__MCIF__SHIFT 0xb
+#define MC_ARB_GRUB_REALTIME_WR__RLC_MASK 0x1000
+#define MC_ARB_GRUB_REALTIME_WR__RLC__SHIFT 0xc
+#define MC_ARB_GRUB_REALTIME_WR__SDMA1_MASK 0x2000
+#define MC_ARB_GRUB_REALTIME_WR__SDMA1__SHIFT 0xd
+#define MC_ARB_GRUB_REALTIME_WR__SMU_MASK 0x4000
+#define MC_ARB_GRUB_REALTIME_WR__SMU__SHIFT 0xe
+#define MC_ARB_GRUB_REALTIME_WR__VCE0_MASK 0x8000
+#define MC_ARB_GRUB_REALTIME_WR__VCE0__SHIFT 0xf
+#define MC_ARB_GRUB_REALTIME_WR__VCE1_MASK 0x10000
+#define MC_ARB_GRUB_REALTIME_WR__VCE1__SHIFT 0x10
+#define MC_ARB_GRUB_REALTIME_WR__SAMMSP_MASK 0x20000
+#define MC_ARB_GRUB_REALTIME_WR__SAMMSP__SHIFT 0x11
+#define MC_ARB_GRUB_REALTIME_WR__XDMA_MASK 0x40000
+#define MC_ARB_GRUB_REALTIME_WR__XDMA__SHIFT 0x12
+#define MC_ARB_GRUB_REALTIME_WR__XDMAM_MASK 0x80000
+#define MC_ARB_GRUB_REALTIME_WR__XDMAM__SHIFT 0x13
+#define MC_ARB_GRUB_REALTIME_WR__SDMA0_MASK 0x100000
+#define MC_ARB_GRUB_REALTIME_WR__SDMA0__SHIFT 0x14
+#define MC_ARB_GRUB_REALTIME_WR__HDP_MASK 0x200000
+#define MC_ARB_GRUB_REALTIME_WR__HDP__SHIFT 0x15
+#define MC_ARB_GRUB_REALTIME_WR__UMC_MASK 0x400000
+#define MC_ARB_GRUB_REALTIME_WR__UMC__SHIFT 0x16
+#define MC_ARB_GRUB_REALTIME_WR__UVD_MASK 0x800000
+#define MC_ARB_GRUB_REALTIME_WR__UVD__SHIFT 0x17
+#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0_MASK 0x1000000
+#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0__SHIFT 0x18
+#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1_MASK 0x2000000
+#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1__SHIFT 0x19
+#define MC_ARB_GRUB_REALTIME_WR__XDP_MASK 0x4000000
+#define MC_ARB_GRUB_REALTIME_WR__XDP__SHIFT 0x1a
+#define MC_ARB_GRUB_REALTIME_WR__SEM_MASK 0x8000000
+#define MC_ARB_GRUB_REALTIME_WR__SEM__SHIFT 0x1b
+#define MC_ARB_GRUB_REALTIME_WR__IH_MASK 0x10000000
+#define MC_ARB_GRUB_REALTIME_WR__IH__SHIFT 0x1c
+#define MC_ARB_GRUB_REALTIME_WR__VP8_MASK 0x20000000
+#define MC_ARB_GRUB_REALTIME_WR__VP8__SHIFT 0x1d
+#define MC_ARB_GRUB_REALTIME_WR__ISP_MASK 0x40000000
+#define MC_ARB_GRUB_REALTIME_WR__ISP__SHIFT 0x1e
+#define MC_ARB_GRUB_REALTIME_WR__VIN0_MASK 0x80000000
+#define MC_ARB_GRUB_REALTIME_WR__VIN0__SHIFT 0x1f
+#define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0xff
+#define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x0
+#define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0xff00
+#define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x8
+#define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0xff0000
+#define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x10
+#define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000
+#define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x18
+#define MC_ARB_BUSY_STATUS__LM_RD0_MASK 0x1
+#define MC_ARB_BUSY_STATUS__LM_RD0__SHIFT 0x0
+#define MC_ARB_BUSY_STATUS__LM_RD1_MASK 0x2
+#define MC_ARB_BUSY_STATUS__LM_RD1__SHIFT 0x1
+#define MC_ARB_BUSY_STATUS__LM_WR0_MASK 0x4
+#define MC_ARB_BUSY_STATUS__LM_WR0__SHIFT 0x2
+#define MC_ARB_BUSY_STATUS__LM_WR1_MASK 0x8
+#define MC_ARB_BUSY_STATUS__LM_WR1__SHIFT 0x3
+#define MC_ARB_BUSY_STATUS__HM_RD0_MASK 0x10
+#define MC_ARB_BUSY_STATUS__HM_RD0__SHIFT 0x4
+#define MC_ARB_BUSY_STATUS__HM_RD1_MASK 0x20
+#define MC_ARB_BUSY_STATUS__HM_RD1__SHIFT 0x5
+#define MC_ARB_BUSY_STATUS__HM_WR0_MASK 0x40
+#define MC_ARB_BUSY_STATUS__HM_WR0__SHIFT 0x6
+#define MC_ARB_BUSY_STATUS__HM_WR1_MASK 0x80
+#define MC_ARB_BUSY_STATUS__HM_WR1__SHIFT 0x7
+#define MC_ARB_BUSY_STATUS__WDE_RD0_MASK 0x100
+#define MC_ARB_BUSY_STATUS__WDE_RD0__SHIFT 0x8
+#define MC_ARB_BUSY_STATUS__WDE_RD1_MASK 0x200
+#define MC_ARB_BUSY_STATUS__WDE_RD1__SHIFT 0x9
+#define MC_ARB_BUSY_STATUS__WDE_WR0_MASK 0x400
+#define MC_ARB_BUSY_STATUS__WDE_WR0__SHIFT 0xa
+#define MC_ARB_BUSY_STATUS__WDE_WR1_MASK 0x800
+#define MC_ARB_BUSY_STATUS__WDE_WR1__SHIFT 0xb
+#define MC_ARB_BUSY_STATUS__POP0_MASK 0x1000
+#define MC_ARB_BUSY_STATUS__POP0__SHIFT 0xc
+#define MC_ARB_BUSY_STATUS__POP1_MASK 0x2000
+#define MC_ARB_BUSY_STATUS__POP1__SHIFT 0xd
+#define MC_ARB_BUSY_STATUS__TAGFIFO0_MASK 0x4000
+#define MC_ARB_BUSY_STATUS__TAGFIFO0__SHIFT 0xe
+#define MC_ARB_BUSY_STATUS__TAGFIFO1_MASK 0x8000
+#define MC_ARB_BUSY_STATUS__TAGFIFO1__SHIFT 0xf
+#define MC_ARB_BUSY_STATUS__REPLAY0_MASK 0x10000
+#define MC_ARB_BUSY_STATUS__REPLAY0__SHIFT 0x10
+#define MC_ARB_BUSY_STATUS__REPLAY1_MASK 0x20000
+#define MC_ARB_BUSY_STATUS__REPLAY1__SHIFT 0x11
+#define MC_ARB_BUSY_STATUS__RDRET0_MASK 0x40000
+#define MC_ARB_BUSY_STATUS__RDRET0__SHIFT 0x12
+#define MC_ARB_BUSY_STATUS__RDRET1_MASK 0x80000
+#define MC_ARB_BUSY_STATUS__RDRET1__SHIFT 0x13
+#define MC_ARB_BUSY_STATUS__GECC2_RD0_MASK 0x100000
+#define MC_ARB_BUSY_STATUS__GECC2_RD0__SHIFT 0x14
+#define MC_ARB_BUSY_STATUS__GECC2_RD1_MASK 0x200000
+#define MC_ARB_BUSY_STATUS__GECC2_RD1__SHIFT 0x15
+#define MC_ARB_BUSY_STATUS__GECC2_WR0_MASK 0x400000
+#define MC_ARB_BUSY_STATUS__GECC2_WR0__SHIFT 0x16
+#define MC_ARB_BUSY_STATUS__GECC2_WR1_MASK 0x800000
+#define MC_ARB_BUSY_STATUS__GECC2_WR1__SHIFT 0x17
+#define MC_ARB_BUSY_STATUS__WRRET0_MASK 0x1000000
+#define MC_ARB_BUSY_STATUS__WRRET0__SHIFT 0x18
+#define MC_ARB_BUSY_STATUS__WRRET1_MASK 0x2000000
+#define MC_ARB_BUSY_STATUS__WRRET1__SHIFT 0x19
+#define MC_ARB_BUSY_STATUS__RTT0_MASK 0x4000000
+#define MC_ARB_BUSY_STATUS__RTT0__SHIFT 0x1a
+#define MC_ARB_BUSY_STATUS__RTT1_MASK 0x8000000
+#define MC_ARB_BUSY_STATUS__RTT1__SHIFT 0x1b
+#define MC_ARB_BUSY_STATUS__REM_RD0_MASK 0x10000000
+#define MC_ARB_BUSY_STATUS__REM_RD0__SHIFT 0x1c
+#define MC_ARB_BUSY_STATUS__REM_RD1_MASK 0x20000000
+#define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d
+#define MC_ARB_BUSY_STATUS__REM_WR0_MASK 0x40000000
+#define MC_ARB_BUSY_STATUS__REM_WR0__SHIFT 0x1e
+#define MC_ARB_BUSY_STATUS__REM_WR1_MASK 0x80000000
+#define MC_ARB_BUSY_STATUS__REM_WR1__SHIFT 0x1f
+#define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0xff
+#define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x0
+#define MC_ARB_DRAM_TIMING2_1__RP_MASK 0xff00
+#define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x8
+#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0xff0000
+#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x10
+#define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000
+#define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x18
+#define MC_ARB_GRUB2__REALTIME_GRP_RD_MASK 0xff
+#define MC_ARB_GRUB2__REALTIME_GRP_RD__SHIFT 0x0
+#define MC_ARB_GRUB2__REALTIME_GRP_WR_MASK 0xff00
+#define MC_ARB_GRUB2__REALTIME_GRP_WR__SHIFT 0x8
+#define MC_ARB_GRUB2__DISP_RD_STALL_EN_MASK 0x10000
+#define MC_ARB_GRUB2__DISP_RD_STALL_EN__SHIFT 0x10
+#define MC_ARB_GRUB2__ACP_RD_STALL_EN_MASK 0x20000
+#define MC_ARB_GRUB2__ACP_RD_STALL_EN__SHIFT 0x11
+#define MC_ARB_GRUB2__UVD_RD_STALL_EN_MASK 0x40000
+#define MC_ARB_GRUB2__UVD_RD_STALL_EN__SHIFT 0x12
+#define MC_ARB_GRUB2__VCE0_RD_STALL_EN_MASK 0x80000
+#define MC_ARB_GRUB2__VCE0_RD_STALL_EN__SHIFT 0x13
+#define MC_ARB_GRUB2__VCE1_RD_STALL_EN_MASK 0x100000
+#define MC_ARB_GRUB2__VCE1_RD_STALL_EN__SHIFT 0x14
+#define MC_ARB_GRUB2__REALTIME_RD_WTS_MASK 0x200000
+#define MC_ARB_GRUB2__REALTIME_RD_WTS__SHIFT 0x15
+#define MC_ARB_GRUB2__REALTIME_WR_WTS_MASK 0x400000
+#define MC_ARB_GRUB2__REALTIME_WR_WTS__SHIFT 0x16
+#define MC_ARB_GRUB2__URGENT_BY_DISP_STALL_MASK 0x800000
+#define MC_ARB_GRUB2__URGENT_BY_DISP_STALL__SHIFT 0x17
+#define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG_MASK 0x1000000
+#define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG__SHIFT 0x18
+#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_RD_MASK 0x2000000
+#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_RD__SHIFT 0x19
+#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD_MASK 0x4000000
+#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD__SHIFT 0x1a
+#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_WR_MASK 0x8000000
+#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_WR__SHIFT 0x1b
+#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR_MASK 0x10000000
+#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR__SHIFT 0x1c
+#define MC_ARB_BURST_TIME__STATE0_MASK 0x1f
+#define MC_ARB_BURST_TIME__STATE0__SHIFT 0x0
+#define MC_ARB_BURST_TIME__STATE1_MASK 0x3e0
+#define MC_ARB_BURST_TIME__STATE1__SHIFT 0x5
+#define MC_ARB_BURST_TIME__STATE2_MASK 0x7c00
+#define MC_ARB_BURST_TIME__STATE2__SHIFT 0xa
+#define MC_ARB_BURST_TIME__STATE3_MASK 0xf8000
+#define MC_ARB_BURST_TIME__STATE3__SHIFT 0xf
+#define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x1
+#define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x0
+#define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x2
+#define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x1
+#define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x4
+#define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x2
+#define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x8
+#define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x3
+#define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x10
+#define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x4
+#define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0xf00
+#define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x8
+#define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x1000
+#define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0xc
+#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL_MASK 0x6000
+#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL__SHIFT 0xd
+#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL_MASK 0x18000
+#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL__SHIFT 0xf
+#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL_MASK 0x60000
+#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL__SHIFT 0x11
+#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL_MASK 0x180000
+#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL__SHIFT 0x13
+#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL_MASK 0x600000
+#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL__SHIFT 0x15
+#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL_MASK 0x1800000
+#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL__SHIFT 0x17
+#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE_MASK 0x2000000
+#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE__SHIFT 0x19
+#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE_MASK 0x4000000
+#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE__SHIFT 0x1a
+#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE_MASK 0x8000000
+#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE__SHIFT 0x1b
+#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE_MASK 0x10000000
+#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE__SHIFT 0x1c
+#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE_MASK 0x60000000
+#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d
+#define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x1e
+#define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x1
+#define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x1
+#define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
+#define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x2
+#define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
+#define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x4
+#define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
+#define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
+#define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
+#define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x30
+#define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x4
+#define MC_CG_CONFIG__INDEX_MASK 0x3fffc0
+#define MC_CG_CONFIG__INDEX__SHIFT 0x6
+#define MC_CITF_CNTL__IGNOREPM_MASK 0x4
+#define MC_CITF_CNTL__IGNOREPM__SHIFT 0x2
+#define MC_CITF_CNTL__EXEMPTPM_MASK 0x8
+#define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x3
+#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x30
+#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x4
+#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x40
+#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x6
+#define MC_CITF_CNTL__CNTR_CHMAP_MODE_MASK 0x180
+#define MC_CITF_CNTL__CNTR_CHMAP_MODE__SHIFT 0x7
+#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE_MASK 0x200
+#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE__SHIFT 0x9
+#define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x3f
+#define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x0
+#define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0xfc0
+#define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x6
+#define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0xff
+#define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x0
+#define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0xff00
+#define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x8
+#define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0xff0000
+#define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x10
+#define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x1000000
+#define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x18
+#define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x2000000
+#define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x19
+#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0xff
+#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x0
+#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0xff00
+#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x8
+#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI_MASK 0xff0000
+#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI__SHIFT 0x10
+#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x1000000
+#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x18
+#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x2000000
+#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x19
+#define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x1
+#define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x0
+#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x1e
+#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x1
+#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x20
+#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x5
+#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x3c0
+#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x6
+#define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x3f
+#define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x0
+#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x3f000
+#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0xc
+#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0xfc0000
+#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x12
+#define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000
+#define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x18
+#define MC_CITF_RET_MODE__INORDER_RD_MASK 0x1
+#define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x0
+#define MC_CITF_RET_MODE__INORDER_WR_MASK 0x2
+#define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x1
+#define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x4
+#define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x2
+#define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x8
+#define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x3
+#define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x10
+#define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x4
+#define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x20
+#define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x5
+#define MC_CITF_RET_MODE__RDRET_STALL_EN_MASK 0x40
+#define MC_CITF_RET_MODE__RDRET_STALL_EN__SHIFT 0x6
+#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD_MASK 0x7f80
+#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD__SHIFT 0x7
+#define MC_CITF_DAGB_DLY__DLY_MASK 0x1f
+#define MC_CITF_DAGB_DLY__DLY__SHIFT 0x0
+#define MC_CITF_DAGB_DLY__CLI_MASK 0x3f0000
+#define MC_CITF_DAGB_DLY__CLI__SHIFT 0x10
+#define MC_CITF_DAGB_DLY__POS_MASK 0x3f000000
+#define MC_CITF_DAGB_DLY__POS__SHIFT 0x18
+#define MC_RD_GRP_EXT__DBSTEN0_MASK 0xf
+#define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x0
+#define MC_RD_GRP_EXT__TC0_MASK 0xf0
+#define MC_RD_GRP_EXT__TC0__SHIFT 0x4
+#define MC_WR_GRP_EXT__DBSTEN0_MASK 0xf
+#define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x0
+#define MC_WR_GRP_EXT__TC0_MASK 0xf0
+#define MC_WR_GRP_EXT__TC0__SHIFT 0x4
+#define MC_CITF_REMREQ__READ_CREDITS_MASK 0x7f
+#define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x0
+#define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x3f80
+#define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x7
+#define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x4000
+#define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0xe
+#define MC_WR_TC0__ENABLE_MASK 0x1
+#define MC_WR_TC0__ENABLE__SHIFT 0x0
+#define MC_WR_TC0__PRESCALE_MASK 0x6
+#define MC_WR_TC0__PRESCALE__SHIFT 0x1
+#define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_WR_TC0__STALL_MODE_MASK 0x30
+#define MC_WR_TC0__STALL_MODE__SHIFT 0x4
+#define MC_WR_TC0__STALL_OVERRIDE_MASK 0x40
+#define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_WR_TC0__MAX_BURST_MASK 0x780
+#define MC_WR_TC0__MAX_BURST__SHIFT 0x7
+#define MC_WR_TC0__LAZY_TIMER_MASK 0x7800
+#define MC_WR_TC0__LAZY_TIMER__SHIFT 0xb
+#define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_WR_TC1__ENABLE_MASK 0x1
+#define MC_WR_TC1__ENABLE__SHIFT 0x0
+#define MC_WR_TC1__PRESCALE_MASK 0x6
+#define MC_WR_TC1__PRESCALE__SHIFT 0x1
+#define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_WR_TC1__STALL_MODE_MASK 0x30
+#define MC_WR_TC1__STALL_MODE__SHIFT 0x4
+#define MC_WR_TC1__STALL_OVERRIDE_MASK 0x40
+#define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_WR_TC1__MAX_BURST_MASK 0x780
+#define MC_WR_TC1__MAX_BURST__SHIFT 0x7
+#define MC_WR_TC1__LAZY_TIMER_MASK 0x7800
+#define MC_WR_TC1__LAZY_TIMER__SHIFT 0xb
+#define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x3f
+#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x0
+#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0xfc0
+#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x6
+#define MC_CITF_CREDITS_ARB_RD2__READ_MED_MASK 0xff
+#define MC_CITF_CREDITS_ARB_RD2__READ_MED__SHIFT 0x0
+#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x7
+#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x0
+#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x38
+#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x3
+#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x1c0
+#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x6
+#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0xe00
+#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x9
+#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x7000
+#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0xc
+#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x38000
+#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0xf
+#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
+#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x12
+#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0xe00000
+#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x15
+#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x1000000
+#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x18
+#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL_MASK 0x2000000
+#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL__SHIFT 0x19
+#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x7
+#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x0
+#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x38
+#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x3
+#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x1c0
+#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x6
+#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0xe00
+#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x9
+#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x7000
+#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0xc
+#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x38000
+#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0xf
+#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
+#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x12
+#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0xe00000
+#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x15
+#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x1000000
+#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x18
+#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL_MASK 0x2000000
+#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL__SHIFT 0x19
+#define MC_RD_CB__ENABLE_MASK 0x1
+#define MC_RD_CB__ENABLE__SHIFT 0x0
+#define MC_RD_CB__PRESCALE_MASK 0x6
+#define MC_RD_CB__PRESCALE__SHIFT 0x1
+#define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_RD_CB__STALL_MODE_MASK 0x30
+#define MC_RD_CB__STALL_MODE__SHIFT 0x4
+#define MC_RD_CB__STALL_OVERRIDE_MASK 0x40
+#define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_RD_CB__MAX_BURST_MASK 0x780
+#define MC_RD_CB__MAX_BURST__SHIFT 0x7
+#define MC_RD_CB__LAZY_TIMER_MASK 0x7800
+#define MC_RD_CB__LAZY_TIMER__SHIFT 0xb
+#define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_RD_DB__ENABLE_MASK 0x1
+#define MC_RD_DB__ENABLE__SHIFT 0x0
+#define MC_RD_DB__PRESCALE_MASK 0x6
+#define MC_RD_DB__PRESCALE__SHIFT 0x1
+#define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_RD_DB__STALL_MODE_MASK 0x30
+#define MC_RD_DB__STALL_MODE__SHIFT 0x4
+#define MC_RD_DB__STALL_OVERRIDE_MASK 0x40
+#define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_RD_DB__MAX_BURST_MASK 0x780
+#define MC_RD_DB__MAX_BURST__SHIFT 0x7
+#define MC_RD_DB__LAZY_TIMER_MASK 0x7800
+#define MC_RD_DB__LAZY_TIMER__SHIFT 0xb
+#define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_RD_TC0__ENABLE_MASK 0x1
+#define MC_RD_TC0__ENABLE__SHIFT 0x0
+#define MC_RD_TC0__PRESCALE_MASK 0x6
+#define MC_RD_TC0__PRESCALE__SHIFT 0x1
+#define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_RD_TC0__STALL_MODE_MASK 0x30
+#define MC_RD_TC0__STALL_MODE__SHIFT 0x4
+#define MC_RD_TC0__STALL_OVERRIDE_MASK 0x40
+#define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_RD_TC0__MAX_BURST_MASK 0x780
+#define MC_RD_TC0__MAX_BURST__SHIFT 0x7
+#define MC_RD_TC0__LAZY_TIMER_MASK 0x7800
+#define MC_RD_TC0__LAZY_TIMER__SHIFT 0xb
+#define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_RD_TC1__ENABLE_MASK 0x1
+#define MC_RD_TC1__ENABLE__SHIFT 0x0
+#define MC_RD_TC1__PRESCALE_MASK 0x6
+#define MC_RD_TC1__PRESCALE__SHIFT 0x1
+#define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_RD_TC1__STALL_MODE_MASK 0x30
+#define MC_RD_TC1__STALL_MODE__SHIFT 0x4
+#define MC_RD_TC1__STALL_OVERRIDE_MASK 0x40
+#define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_RD_TC1__MAX_BURST_MASK 0x780
+#define MC_RD_TC1__MAX_BURST__SHIFT 0x7
+#define MC_RD_TC1__LAZY_TIMER_MASK 0x7800
+#define MC_RD_TC1__LAZY_TIMER__SHIFT 0xb
+#define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_RD_HUB__ENABLE_MASK 0x1
+#define MC_RD_HUB__ENABLE__SHIFT 0x0
+#define MC_RD_HUB__PRESCALE_MASK 0x6
+#define MC_RD_HUB__PRESCALE__SHIFT 0x1
+#define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_RD_HUB__STALL_MODE_MASK 0x30
+#define MC_RD_HUB__STALL_MODE__SHIFT 0x4
+#define MC_RD_HUB__STALL_OVERRIDE_MASK 0x40
+#define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_RD_HUB__MAX_BURST_MASK 0x780
+#define MC_RD_HUB__MAX_BURST__SHIFT 0x7
+#define MC_RD_HUB__LAZY_TIMER_MASK 0x7800
+#define MC_RD_HUB__LAZY_TIMER__SHIFT 0xb
+#define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_WR_CB__ENABLE_MASK 0x1
+#define MC_WR_CB__ENABLE__SHIFT 0x0
+#define MC_WR_CB__PRESCALE_MASK 0x6
+#define MC_WR_CB__PRESCALE__SHIFT 0x1
+#define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_WR_CB__STALL_MODE_MASK 0x30
+#define MC_WR_CB__STALL_MODE__SHIFT 0x4
+#define MC_WR_CB__STALL_OVERRIDE_MASK 0x40
+#define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_WR_CB__MAX_BURST_MASK 0x780
+#define MC_WR_CB__MAX_BURST__SHIFT 0x7
+#define MC_WR_CB__LAZY_TIMER_MASK 0x7800
+#define MC_WR_CB__LAZY_TIMER__SHIFT 0xb
+#define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_WR_DB__ENABLE_MASK 0x1
+#define MC_WR_DB__ENABLE__SHIFT 0x0
+#define MC_WR_DB__PRESCALE_MASK 0x6
+#define MC_WR_DB__PRESCALE__SHIFT 0x1
+#define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_WR_DB__STALL_MODE_MASK 0x30
+#define MC_WR_DB__STALL_MODE__SHIFT 0x4
+#define MC_WR_DB__STALL_OVERRIDE_MASK 0x40
+#define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_WR_DB__MAX_BURST_MASK 0x780
+#define MC_WR_DB__MAX_BURST__SHIFT 0x7
+#define MC_WR_DB__LAZY_TIMER_MASK 0x7800
+#define MC_WR_DB__LAZY_TIMER__SHIFT 0xb
+#define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_WR_HUB__ENABLE_MASK 0x1
+#define MC_WR_HUB__ENABLE__SHIFT 0x0
+#define MC_WR_HUB__PRESCALE_MASK 0x6
+#define MC_WR_HUB__PRESCALE__SHIFT 0x1
+#define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_WR_HUB__STALL_MODE_MASK 0x30
+#define MC_WR_HUB__STALL_MODE__SHIFT 0x4
+#define MC_WR_HUB__STALL_OVERRIDE_MASK 0x40
+#define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x6
+#define MC_WR_HUB__MAX_BURST_MASK 0x780
+#define MC_WR_HUB__MAX_BURST__SHIFT 0x7
+#define MC_WR_HUB__LAZY_TIMER_MASK 0x7800
+#define MC_WR_HUB__LAZY_TIMER__SHIFT 0xb
+#define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0xff
+#define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x0
+#define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0xff00
+#define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x8
+#define MC_RD_GRP_LCL__CB0_MASK 0xf000
+#define MC_RD_GRP_LCL__CB0__SHIFT 0xc
+#define MC_RD_GRP_LCL__CBCMASK0_MASK 0xf0000
+#define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x10
+#define MC_RD_GRP_LCL__CBFMASK0_MASK 0xf00000
+#define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x14
+#define MC_RD_GRP_LCL__DB0_MASK 0xf000000
+#define MC_RD_GRP_LCL__DB0__SHIFT 0x18
+#define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000
+#define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x1c
+#define MC_WR_GRP_LCL__CB0_MASK 0xf
+#define MC_WR_GRP_LCL__CB0__SHIFT 0x0
+#define MC_WR_GRP_LCL__CBCMASK0_MASK 0xf0
+#define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x4
+#define MC_WR_GRP_LCL__CBFMASK0_MASK 0xf00
+#define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x8
+#define MC_WR_GRP_LCL__DB0_MASK 0xf000
+#define MC_WR_GRP_LCL__DB0__SHIFT 0xc
+#define MC_WR_GRP_LCL__DBHTILE0_MASK 0xf0000
+#define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x10
+#define MC_WR_GRP_LCL__SX0_MASK 0xf00000
+#define MC_WR_GRP_LCL__SX0__SHIFT 0x14
+#define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000
+#define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x1c
+#define MC_CITF_PERF_MON_CNTL2__CID_MASK 0xff
+#define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x0
+#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x2
+#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x1
+#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x4
+#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x2
+#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x8
+#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x3
+#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x10
+#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x4
+#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x20
+#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0x5
+#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x40
+#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0x6
+#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x80
+#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0x7
+#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x100
+#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0x8
+#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x200
+#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0x9
+#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x400
+#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0xa
+#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x800
+#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0xb
+#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x1000
+#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0xc
+#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x2000
+#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0xd
+#define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY_MASK 0x4000
+#define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY__SHIFT 0xe
+#define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY_MASK 0x8000
+#define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY__SHIFT 0xf
+#define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY_MASK 0x10000
+#define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY__SHIFT 0x10
+#define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY_MASK 0x20000
+#define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY__SHIFT 0x11
+#define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY_MASK 0x40000
+#define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY__SHIFT 0x12
+#define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x3f
+#define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x0
+#define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0xfc0
+#define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x6
+#define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x3f000
+#define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0xc
+#define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x40000
+#define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x12
+#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x3f
+#define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x0
+#define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0xfc0
+#define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x6
+#define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x3f000
+#define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0xc
+#define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x40000
+#define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x12
+#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x3f
+#define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x0
+#define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0xfc0
+#define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x6
+#define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x3f000
+#define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0xc
+#define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x40000
+#define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x12
+#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x4
+#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x2
+#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x18
+#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x3
+#define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x3f
+#define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x0
+#define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0xfc0
+#define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x6
+#define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x3f000
+#define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0xc
+#define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x40000
+#define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x12
+#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x3f
+#define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x0
+#define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0xfc0
+#define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x6
+#define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x3f000
+#define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0xc
+#define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x40000
+#define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x12
+#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x3f
+#define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x0
+#define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0xfc0
+#define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x6
+#define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x3f000
+#define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0xc
+#define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x40000
+#define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x12
+#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x80000
+#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x1
+#define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x0
+#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x2
+#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x1
+#define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC_MASK 0x4
+#define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC__SHIFT 0x2
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x8
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x3
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x10
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x4
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x20
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x5
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x40
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x6
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ_MASK 0x80
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ__SHIFT 0x7
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET_MASK 0x100
+#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET__SHIFT 0x8
+#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x200
+#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x9
+#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x400
+#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0xa
+#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC_MASK 0x800
+#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC__SHIFT 0xb
+#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x1000
+#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0xc
+#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x2000
+#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0xd
+#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC_MASK 0x4000
+#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC__SHIFT 0xe
+#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x8000
+#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0xf
+#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x10000
+#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0x10
+#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x20000
+#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0x11
+#define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING_MASK 0x40000
+#define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING__SHIFT 0x12
+#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x80000
+#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0x13
+#define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x3
+#define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x0
+#define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffff
+#define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x0
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x2
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x1
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x4
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x2
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x8
+#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x3
+#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
+#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
+#define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x1fe0
+#define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x5
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x2000
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0xd
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x4000
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0xe
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x8000
+#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0xf
+#define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x10000
+#define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x10
+#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x20000
+#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x11
+#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x40000
+#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x12
+#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x80000
+#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x13
+#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x100000
+#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x14
+#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN_MASK 0x200000
+#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN__SHIFT 0x15
+#define MC_HUB_WDP_CNTL__WRITE_PRI_EN_MASK 0x400000
+#define MC_HUB_WDP_CNTL__WRITE_PRI_EN__SHIFT 0x16
+#define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE_MASK 0x800000
+#define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE__SHIFT 0x17
+#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x1
+#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x0
+#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x2
+#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x1
+#define MC_HUB_WDP_BP__ENABLE_MASK 0x1
+#define MC_HUB_WDP_BP__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_BP__RDRET_MASK 0x3fffe
+#define MC_HUB_WDP_BP__RDRET__SHIFT 0x1
+#define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000
+#define MC_HUB_WDP_BP__WRREQ__SHIFT 0x12
+#define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x1
+#define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x0
+#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x2
+#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
+#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x4
+#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
+#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x8
+#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
+#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x10
+#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
+#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL_MASK 0x20
+#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL__SHIFT 0x5
+#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL_MASK 0x40
+#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL__SHIFT 0x6
+#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL_MASK 0x80
+#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL__SHIFT 0x7
+#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL_MASK 0x100
+#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL__SHIFT 0x8
+#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK 0x200
+#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT 0x9
+#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK 0x400
+#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT 0xa
+#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK 0x800
+#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT 0xb
+#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK 0x1000
+#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT 0xc
+#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL_MASK 0x2000
+#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL__SHIFT 0xd
+#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL_MASK 0x4000
+#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL__SHIFT 0xe
+#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL_MASK 0x8000
+#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL__SHIFT 0xf
+#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL_MASK 0x10000
+#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL__SHIFT 0x10
+#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x20000
+#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x11
+#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x40000
+#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x12
+#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80000
+#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x13
+#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x100000
+#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x14
+#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x200000
+#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x15
+#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400000
+#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x16
+#define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x1
+#define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x0
+#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x2
+#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
+#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x4
+#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
+#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x8
+#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
+#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x10
+#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
+#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL_MASK 0x20
+#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL__SHIFT 0x5
+#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL_MASK 0x40
+#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL__SHIFT 0x6
+#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL_MASK 0x80
+#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL__SHIFT 0x7
+#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL_MASK 0x100
+#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL__SHIFT 0x8
+#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x200
+#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x9
+#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x400
+#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0xa
+#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x800
+#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0xb
+#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x1000
+#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0xc
+#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x2000
+#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0xd
+#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x4000
+#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xe
+#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x8000
+#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0xf
+#define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x1
+#define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x0
+#define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x2
+#define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x1
+#define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x4
+#define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x2
+#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x8
+#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x3
+#define MC_HUB_WRRET_STATUS__MCDS_AVAIL_MASK 0x10
+#define MC_HUB_WRRET_STATUS__MCDS_AVAIL__SHIFT 0x4
+#define MC_HUB_WRRET_STATUS__MCDT_AVAIL_MASK 0x20
+#define MC_HUB_WRRET_STATUS__MCDT_AVAIL__SHIFT 0x5
+#define MC_HUB_WRRET_STATUS__MCDU_AVAIL_MASK 0x40
+#define MC_HUB_WRRET_STATUS__MCDU_AVAIL__SHIFT 0x6
+#define MC_HUB_WRRET_STATUS__MCDV_AVAIL_MASK 0x80
+#define MC_HUB_WRRET_STATUS__MCDV_AVAIL__SHIFT 0x7
+#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x1
+#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x0
+#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x4
+#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x2
+#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x8
+#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x3
+#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
+#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
+#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x20
+#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x5
+#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x40
+#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x6
+#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x80
+#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x7
+#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x100
+#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x8
+#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE_MASK 0x200
+#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE__SHIFT 0x9
+#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE_MASK 0x400
+#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE__SHIFT 0xa
+#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE_MASK 0x800
+#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE__SHIFT 0xb
+#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE_MASK 0x1000
+#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE__SHIFT 0xc
+#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x2000
+#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0xd
+#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x1fc000
+#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0xe
+#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x200000
+#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x15
+#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x400000
+#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x16
+#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x800000
+#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x17
+#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE_MASK 0x1000000
+#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE__SHIFT 0x18
+#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE_MASK 0x2000000
+#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE__SHIFT 0x19
+#define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE_MASK 0x4000000
+#define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE__SHIFT 0x1a
+#define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD_MASK 0x78000000
+#define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD__SHIFT 0x1b
+#define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x1
+#define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x0
+#define MC_HUB_WRRET_CNTL__BP_MASK 0x1ffffe
+#define MC_HUB_WRRET_CNTL__BP__SHIFT 0x1
+#define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x200000
+#define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x15
+#define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000
+#define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x16
+#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000
+#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x1e
+#define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000
+#define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x1f
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
+#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
+#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
+#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
+#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
+#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
+#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
+#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
+#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
+#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
+#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
+#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
+#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
+#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
+#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
+#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
+#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
+#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
+#define MC_HUB_WDP_CREDITS__VM0_MASK 0xff
+#define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS__VM1_MASK 0xff00
+#define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x8
+#define MC_HUB_WDP_CREDITS__STOR0_MASK 0xff0000
+#define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x10
+#define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000
+#define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x18
+#define MC_HUB_WDP_CREDITS2__STOR0_PRI_MASK 0xff
+#define MC_HUB_WDP_CREDITS2__STOR0_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS2__STOR1_PRI_MASK 0xff00
+#define MC_HUB_WDP_CREDITS2__STOR1_PRI__SHIFT 0x8
+#define MC_HUB_WDP_CREDITS2__VM2_MASK 0xff0000
+#define MC_HUB_WDP_CREDITS2__VM2__SHIFT 0x10
+#define MC_HUB_WDP_GBL0__MAXBURST_MASK 0xf
+#define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x0
+#define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0xf0
+#define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x4
+#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0xff00
+#define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x8
+#define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x10000
+#define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x10
+#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI_MASK 0x1fe0000
+#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x11
+#define MC_HUB_WDP_GBL1__MAXBURST_MASK 0xf
+#define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x0
+#define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0xf0
+#define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x4
+#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0xff00
+#define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x8
+#define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x10000
+#define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x10
+#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI_MASK 0x1fe0000
+#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x11
+#define MC_HUB_RDREQ_CREDITS__VM0_MASK 0xff
+#define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x0
+#define MC_HUB_RDREQ_CREDITS__VM1_MASK 0xff00
+#define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x8
+#define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0xff0000
+#define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x10
+#define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000
+#define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x18
+#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI_MASK 0xff
+#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI__SHIFT 0x0
+#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0xff00
+#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x8
+#define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x3f
+#define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x0
+#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x3f0000
+#define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x10
+#define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000
+#define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x18
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x1
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x0
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x2
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x1
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x4
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x2
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x8
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x3
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ_MASK 0x10
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ__SHIFT 0x4
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE_MASK 0x20
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE__SHIFT 0x5
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ_MASK 0x40
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ__SHIFT 0x6
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE_MASK 0x80
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE__SHIFT 0x7
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x100
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x8
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x200
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x9
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x400
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0xa
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x800
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0xb
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x1000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0xc
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x2000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0xd
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x4000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0xe
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x8000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0xf
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x10000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x10
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x20000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x11
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x40000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x12
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x80000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x13
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x100000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x14
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x200000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x15
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ_MASK 0x400000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ__SHIFT 0x16
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE_MASK 0x800000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE__SHIFT 0x17
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ_MASK 0x1000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ__SHIFT 0x18
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE_MASK 0x2000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE__SHIFT 0x19
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ_MASK 0x4000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ__SHIFT 0x1a
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE_MASK 0x8000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT 0x1b
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ_MASK 0x10000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ__SHIFT 0x1c
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE_MASK 0x20000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE__SHIFT 0x1d
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ_MASK 0x40000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ__SHIFT 0x1e
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE_MASK 0x80000000
+#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE__SHIFT 0x1f
+#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x3
+#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x7c
+#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x2
+#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE_MASK 0x3
+#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT_MASK 0x7c
+#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT__SHIFT 0x2
+#define MC_HUB_WDP_BYPASS_GBL0__ENABLE_MASK 0x1
+#define MC_HUB_WDP_BYPASS_GBL0__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_BYPASS_GBL0__CID1_MASK 0x1fe
+#define MC_HUB_WDP_BYPASS_GBL0__CID1__SHIFT 0x1
+#define MC_HUB_WDP_BYPASS_GBL0__CID2_MASK 0x1fe00
+#define MC_HUB_WDP_BYPASS_GBL0__CID2__SHIFT 0x9
+#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME_MASK 0xfe0000
+#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME__SHIFT 0x11
+#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME_MASK 0x7f000000
+#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME__SHIFT 0x18
+#define MC_HUB_WDP_BYPASS_GBL1__ENABLE_MASK 0x1
+#define MC_HUB_WDP_BYPASS_GBL1__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_BYPASS_GBL1__CID1_MASK 0x1fe
+#define MC_HUB_WDP_BYPASS_GBL1__CID1__SHIFT 0x1
+#define MC_HUB_WDP_BYPASS_GBL1__CID2_MASK 0x1fe00
+#define MC_HUB_WDP_BYPASS_GBL1__CID2__SHIFT 0x9
+#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME_MASK 0xfe0000
+#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME__SHIFT 0x11
+#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME_MASK 0x7f000000
+#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME__SHIFT 0x18
+#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_BYPASS_GBL0__CID1_MASK 0x1fe
+#define MC_HUB_RDREQ_BYPASS_GBL0__CID1__SHIFT 0x1
+#define MC_HUB_RDREQ_BYPASS_GBL0__CID2_MASK 0x1fe00
+#define MC_HUB_RDREQ_BYPASS_GBL0__CID2__SHIFT 0x9
+#define MC_HUB_WDP_SH2__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SH2__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SH2__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SH2__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SH2__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SH2__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SH2__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SH2__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SH2__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SH2__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SH2__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SH2__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_SH3__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SH3__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SH3__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SH3__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SH3__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SH3__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SH3__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SH3__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SH3__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SH3__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SH3__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SH3__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC_MASK 0x1
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC__SHIFT 0x0
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC_MASK 0x2
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC__SHIFT 0x1
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC_MASK 0x4
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC__SHIFT 0x2
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC_MASK 0x8
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC__SHIFT 0x3
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC_MASK 0x10
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC__SHIFT 0x4
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC_MASK 0x20
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC__SHIFT 0x5
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC_MASK 0x40
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC__SHIFT 0x6
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC_MASK 0x80
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC__SHIFT 0x7
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC_MASK 0x100
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC__SHIFT 0x8
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC_MASK 0x200
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC__SHIFT 0x9
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC_MASK 0x400
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC__SHIFT 0xa
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC_MASK 0x800
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC__SHIFT 0xb
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC_MASK 0x1000
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC__SHIFT 0xc
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC_MASK 0x2000
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC__SHIFT 0xd
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC_MASK 0x4000
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC__SHIFT 0xe
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC_MASK 0x8000
+#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC__SHIFT 0xf
+#define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDW__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDW__MED_CREDITS_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDW__MED_CREDITS__SHIFT 0x19
+#define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDX__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDX__MED_CREDITS_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDX__MED_CREDITS__SHIFT 0x19
+#define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDY__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDY__MED_CREDITS_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDY__MED_CREDITS__SHIFT 0x19
+#define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDZ__MED_CREDITS_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDZ__MED_CREDITS__SHIFT 0x19
+#define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x7f
+#define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x0
+#define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL_MASK 0x80
+#define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL__SHIFT 0x7
+#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x7f00
+#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x8
+#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0xff
+#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x0
+#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI_MASK 0xff00
+#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x8
+#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0xff
+#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x0
+#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI_MASK 0xff00
+#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x8
+#define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_SDMA0__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_SDMA0__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_SDMA0__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_SDMA0__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_SDMA0__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_SDMA0__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_SDMA0__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_SDMA0__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_SDMA1__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_SDMA1__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_SDMA1__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_SDMA1__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_SDMA1__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_SDMA1__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_SDMA1__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_SDMA1__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_VCE0__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_VCE0__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_VCE0__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_VCE0__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_VCE0__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_VCE0__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_VCE0__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_VCE0__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_VCE0__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_VCE0__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_VCE0__VM_BYPASS_MASK 0x10000
+#define MC_HUB_RDREQ_VCE0__VM_BYPASS__SHIFT 0x10
+#define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_UMC__VM_BYPASS_MASK 0x10000
+#define MC_HUB_RDREQ_UMC__VM_BYPASS__SHIFT 0x10
+#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x10000
+#define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x10
+#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_VCEU0__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_VCEU0__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_VCEU0__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_VCEU0__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_VCEU0__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_VCEU0__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_VCEU0__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_VCEU0__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_VCEU0__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_VCEU0__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_MCDW__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_MCDX__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_MCDY__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x3
+#define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x1fc
+#define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x2
+#define MC_HUB_WDP_SDMA1__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SDMA1__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SDMA1__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SDMA1__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SDMA1__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SDMA1__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SDMA1__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SDMA1__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SDMA1__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SDMA1__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_SH0__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SH0__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SH0__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_MCIF__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_VCE0__ENABLE_MASK 0x1
+#define MC_HUB_WDP_VCE0__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_VCE0__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_VCE0__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_VCE0__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_VCE0__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_VCE0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_VCE0__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_VCE0__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_VCE0__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_VCE0__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_VCE0__VM_BYPASS_MASK 0x10000
+#define MC_HUB_WDP_VCE0__VM_BYPASS__SHIFT 0x10
+#define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_XDP__ENABLE_MASK 0x1
+#define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_XDP__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_XDP__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_IH__ENABLE_MASK 0x1
+#define MC_HUB_WDP_IH__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_IH__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_IH__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_IH__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_RLC__ENABLE_MASK 0x1
+#define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_RLC__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_RLC__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_SEM__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SEM__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SEM__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_SMU__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SMU__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SMU__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_SH1__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SH1__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SH1__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_UMC__ENABLE_MASK 0x1
+#define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_UMC__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_UMC__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_UVD__ENABLE_MASK 0x1
+#define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_UVD__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_UVD__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x10000
+#define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x10
+#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_HDP__ENABLE_MASK 0x1
+#define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_HDP__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_HDP__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_SDMA0__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SDMA0__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SDMA0__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SDMA0__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SDMA0__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SDMA0__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SDMA0__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SDMA0__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SDMA0__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SDMA0__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WDP_VCEU0__ENABLE_MASK 0x1
+#define MC_HUB_WDP_VCEU0__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_VCEU0__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_VCEU0__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_VCEU0__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_VCEU0__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_VCEU0__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_VCEU0__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_VCEU0__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_VCEU0__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x1
+#define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_XDMA__ENABLE_MASK 0x1
+#define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_ACPG__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_ACPG__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_ACPG__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_ACPG__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_ACPG__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_ACPG__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_ACPG__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_ACPG__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_ACPG__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_ACPG__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_RDREQ_ACPO__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_ACPO__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_ACPO__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_ACPO__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_ACPO__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_ACPO__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_ACPO__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_ACPO__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_ACPO__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_ACPO__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_RDREQ_SAMMSP__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_SAMMSP__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_SAMMSP__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_SAMMSP__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_SAMMSP__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_SAMMSP__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_SAMMSP__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_SAMMSP__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_VP8__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_VP8__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_VP8__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_VP8__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_VP8__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_VP8__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_VP8__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_VP8__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_VP8__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_VP8__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_VP8U__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_VP8U__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_VP8U__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_VP8U__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_VP8U__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_VP8U__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_VP8U__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_VP8U__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_VP8U__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_VP8U__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_VP8U__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_VP8U__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_VP8U__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_VP8U__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_ACPG__ENABLE_MASK 0x1
+#define MC_HUB_WDP_ACPG__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_ACPG__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_ACPG__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_ACPG__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_ACPG__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_ACPG__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_ACPG__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_ACPG__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_ACPG__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_ACPG__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_WDP_ACPG__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_WDP_ACPG__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_WDP_ACPO__ENABLE_MASK 0x1
+#define MC_HUB_WDP_ACPO__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_ACPO__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_ACPO__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_ACPO__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_ACPO__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_ACPO__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_ACPO__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_ACPO__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_ACPO__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_ACPO__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_WDP_ACPO__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_WDP_ACPO__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_WDP_SAMMSP__ENABLE_MASK 0x1
+#define MC_HUB_WDP_SAMMSP__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_SAMMSP__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_SAMMSP__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_SAMMSP__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_SAMMSP__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_SAMMSP__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_SAMMSP__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_SAMMSP__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_SAMMSP__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_VP8__ENABLE_MASK 0x1
+#define MC_HUB_WDP_VP8__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_VP8__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_VP8__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_VP8__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_VP8__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_VP8__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_VP8__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_VP8__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_VP8__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_VP8__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_VP8__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_VP8U__ENABLE_MASK 0x1
+#define MC_HUB_WDP_VP8U__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_VP8U__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_VP8U__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_VP8U__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_VP8U__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_VP8U__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_VP8U__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_VP8U__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_VP8U__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_VP8U__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_VP8U__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_VP8U__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_VP8U__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_VP8U__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_ISP_SPM__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_ISP_SPM__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_ISP_SPM__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_ISP_SPM__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_ISP_SPM__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_ISP_SPM__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_RDREQ_ISP_MPM__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_ISP_MPM__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_ISP_MPM__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_ISP_MPM__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_ISP_MPM__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_ISP_MPM__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_RDREQ_ISP_CCPU__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_ISP_CCPU__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_WDP_ISP_SPM__ENABLE_MASK 0x1
+#define MC_HUB_WDP_ISP_SPM__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_ISP_SPM__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_ISP_SPM__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_ISP_SPM__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_ISP_SPM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_ISP_SPM__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_ISP_SPM__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_WDP_ISP_MPS__ENABLE_MASK 0x1
+#define MC_HUB_WDP_ISP_MPS__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_ISP_MPS__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_ISP_MPS__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_ISP_MPS__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_ISP_MPS__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_ISP_MPS__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_ISP_MPS__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_WDP_ISP_MPM__ENABLE_MASK 0x1
+#define MC_HUB_WDP_ISP_MPM__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_ISP_MPM__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_ISP_MPM__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_ISP_MPM__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_ISP_MPM__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_ISP_MPM__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_ISP_MPM__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_WDP_ISP_CCPU__ENABLE_MASK 0x1
+#define MC_HUB_WDP_ISP_CCPU__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_ISP_CCPU__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_ISP_CCPU__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_ISP_CCPU__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_ISP_CCPU__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_ISP_CCPU__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_ISP_CCPU__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000
+#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11
+#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000
+#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12
+#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000
+#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13
+#define MC_HUB_RDREQ_MCDS__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDS__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDS__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDS__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDS__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDS__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDS__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDS__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDS__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDS__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD__SHIFT 0x19
+#define MC_HUB_RDREQ_MCDT__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDT__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDT__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDT__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDT__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDT__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDT__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDT__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDT__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDT__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD__SHIFT 0x19
+#define MC_HUB_RDREQ_MCDU__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDU__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDU__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDU__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDU__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDU__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDU__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDU__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDU__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDU__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD__SHIFT 0x19
+#define MC_HUB_RDREQ_MCDV__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_MCDV__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_RDREQ_MCDV__BUS_MASK 0x4
+#define MC_HUB_RDREQ_MCDV__BUS__SHIFT 0x2
+#define MC_HUB_RDREQ_MCDV__MAXBURST_MASK 0x78
+#define MC_HUB_RDREQ_MCDV__MAXBURST__SHIFT 0x3
+#define MC_HUB_RDREQ_MCDV__LAZY_TIMER_MASK 0x780
+#define MC_HUB_RDREQ_MCDV__LAZY_TIMER__SHIFT 0x7
+#define MC_HUB_RDREQ_MCDV__ASK_CREDITS_MASK 0x3f800
+#define MC_HUB_RDREQ_MCDV__ASK_CREDITS__SHIFT 0xb
+#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS_MASK 0x1fc0000
+#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS__SHIFT 0x12
+#define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD_MASK 0xfe000000
+#define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD__SHIFT 0x19
+#define MC_HUB_WDP_MCDS__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDS__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDS__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDS__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDS__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDS__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDS__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDS__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDS__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDS__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDS__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDS__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDS__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDS__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_MCDT__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDT__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDT__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDT__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDT__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDT__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDT__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDT__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDT__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDT__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDT__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDT__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDT__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDT__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_MCDU__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDU__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDU__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDU__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDU__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDU__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDU__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDU__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDU__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDU__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDU__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDU__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDU__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDU__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WDP_MCDV__ENABLE_MASK 0x1
+#define MC_HUB_WDP_MCDV__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT_MASK 0x2
+#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1
+#define MC_HUB_WDP_MCDV__STALL_MODE_MASK 0x4
+#define MC_HUB_WDP_MCDV__STALL_MODE__SHIFT 0x2
+#define MC_HUB_WDP_MCDV__MAXBURST_MASK 0x78
+#define MC_HUB_WDP_MCDV__MAXBURST__SHIFT 0x3
+#define MC_HUB_WDP_MCDV__ASK_CREDITS_MASK 0x1f80
+#define MC_HUB_WDP_MCDV__ASK_CREDITS__SHIFT 0x7
+#define MC_HUB_WDP_MCDV__LAZY_TIMER_MASK 0x1e000
+#define MC_HUB_WDP_MCDV__LAZY_TIMER__SHIFT 0xd
+#define MC_HUB_WDP_MCDV__STALL_THRESHOLD_MASK 0xfe0000
+#define MC_HUB_WDP_MCDV__STALL_THRESHOLD__SHIFT 0x11
+#define MC_HUB_WDP_MCDV__ASK_CREDITS_W_MASK 0x7f000000
+#define MC_HUB_WDP_MCDV__ASK_CREDITS_W__SHIFT 0x18
+#define MC_HUB_WRRET_MCDS__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDS__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDS__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDS__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WRRET_MCDT__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDT__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDT__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDT__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WRRET_MCDU__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDU__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDU__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDU__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WRRET_MCDV__STALL_MODE_MASK 0x1
+#define MC_HUB_WRRET_MCDV__STALL_MODE__SHIFT 0x0
+#define MC_HUB_WRRET_MCDV__CREDIT_COUNT_MASK 0xfe
+#define MC_HUB_WRRET_MCDV__CREDIT_COUNT__SHIFT 0x1
+#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_MASK 0x7f
+#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI__SHIFT 0x0
+#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
+#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
+#define MC_HUB_WDP_BP2__RDRET_MASK 0xffff
+#define MC_HUB_WDP_BP2__RDRET__SHIFT 0x0
+#define MC_HUB_RDREQ_VCE1__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_VCE1__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_VCE1__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_VCE1__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_VCE1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_VCE1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_VCE1__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_VCE1__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_VCE1__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_VCE1__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_VCE1__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_VCE1__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_VCE1__VM_BYPASS_MASK 0x10000
+#define MC_HUB_RDREQ_VCE1__VM_BYPASS__SHIFT 0x10
+#define MC_HUB_RDREQ_VCE1__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_RDREQ_VCE1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_RDREQ_VCEU1__ENABLE_MASK 0x1
+#define MC_HUB_RDREQ_VCEU1__ENABLE__SHIFT 0x0
+#define MC_HUB_RDREQ_VCEU1__PRESCALE_MASK 0x6
+#define MC_HUB_RDREQ_VCEU1__PRESCALE__SHIFT 0x1
+#define MC_HUB_RDREQ_VCEU1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_RDREQ_VCEU1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_RDREQ_VCEU1__STALL_MODE_MASK 0x30
+#define MC_HUB_RDREQ_VCEU1__STALL_MODE__SHIFT 0x4
+#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_RDREQ_VCEU1__MAXBURST_MASK 0x780
+#define MC_HUB_RDREQ_VCEU1__MAXBURST__SHIFT 0x7
+#define MC_HUB_RDREQ_VCEU1__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_RDREQ_VCEU1__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_RDREQ_VCEU1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_RDREQ_VCEU1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_HUB_WDP_VCE1__ENABLE_MASK 0x1
+#define MC_HUB_WDP_VCE1__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_VCE1__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_VCE1__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_VCE1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_VCE1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_VCE1__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_VCE1__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_VCE1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_VCE1__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_VCE1__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_VCE1__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_VCE1__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_VCE1__VM_BYPASS_MASK 0x10000
+#define MC_HUB_WDP_VCE1__VM_BYPASS__SHIFT 0x10
+#define MC_HUB_WDP_VCE1__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
+#define MC_HUB_WDP_VCE1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
+#define MC_HUB_WDP_VCEU1__ENABLE_MASK 0x1
+#define MC_HUB_WDP_VCEU1__ENABLE__SHIFT 0x0
+#define MC_HUB_WDP_VCEU1__PRESCALE_MASK 0x6
+#define MC_HUB_WDP_VCEU1__PRESCALE__SHIFT 0x1
+#define MC_HUB_WDP_VCEU1__BLACKOUT_EXEMPT_MASK 0x8
+#define MC_HUB_WDP_VCEU1__BLACKOUT_EXEMPT__SHIFT 0x3
+#define MC_HUB_WDP_VCEU1__STALL_MODE_MASK 0x30
+#define MC_HUB_WDP_VCEU1__STALL_MODE__SHIFT 0x4
+#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_MASK 0x40
+#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE__SHIFT 0x6
+#define MC_HUB_WDP_VCEU1__MAXBURST_MASK 0x780
+#define MC_HUB_WDP_VCEU1__MAXBURST__SHIFT 0x7
+#define MC_HUB_WDP_VCEU1__LAZY_TIMER_MASK 0x7800
+#define MC_HUB_WDP_VCEU1__LAZY_TIMER__SHIFT 0xb
+#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_WTM_MASK 0x8000
+#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_WTM__SHIFT 0xf
+#define MC_HUB_WDP_VCEU1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
+#define MC_HUB_WDP_VCEU1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
+#define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x8000
+#define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0xf
+#define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x10000
+#define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x10
+#define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x20000
+#define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x11
+#define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0xff
+#define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x0
+#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0xff00
+#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x8
+#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0xff
+#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x0
+#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0xfff00
+#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x8
+#define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000
+#define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x14
+#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0xff
+#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0
+#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0xff00
+#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8
+#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0xff
+#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x0
+#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0xff00
+#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x8
+#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0xff0000
+#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x10
+#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0xff
+#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x0
+#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0xff00
+#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x8
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
+#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
+#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x1
+#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x0
+#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x6
+#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x1
+#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x78
+#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x3
+#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x80
+#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x7
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
+#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
+#define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0xff
+#define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x0
+#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x100
+#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x8
+#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x600
+#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x9
+#define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x1800
+#define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xb
+#define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x2000
+#define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd
+#define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0xff
+#define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x0
+#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x300
+#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x8
+#define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0xc00
+#define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xa
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x3
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x4
+#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2
+#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x8
+#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3
+#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x10
+#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4
+#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x1e0
+#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x3e00
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x7c000
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0xf80000
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000
+#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18
+#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffff
+#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0
+#define MC_RPB_CID_QUEUE_EX__START_MASK 0x1
+#define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x0
+#define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x3e
+#define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1
+#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0xffff
+#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0
+#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000
+#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10
+#define MC_RPB_TCI_CNTL__TCI_ENABLE_MASK 0x1
+#define MC_RPB_TCI_CNTL__TCI_ENABLE__SHIFT 0x0
+#define MC_RPB_TCI_CNTL__TCI_POLICY_MASK 0x6
+#define MC_RPB_TCI_CNTL__TCI_POLICY__SHIFT 0x1
+#define MC_RPB_TCI_CNTL__TCI_VOL_MASK 0x8
+#define MC_RPB_TCI_CNTL__TCI_VOL__SHIFT 0x3
+#define MC_RPB_TCI_CNTL__TCI_VMID_MASK 0xf0
+#define MC_RPB_TCI_CNTL__TCI_VMID__SHIFT 0x4
+#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS_MASK 0xff00
+#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS__SHIFT 0x8
+#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES_MASK 0xff0000
+#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES__SHIFT 0x10
+#define MC_RPB_TCI_CNTL__TCI_MAX_READS_MASK 0xff000000
+#define MC_RPB_TCI_CNTL__TCI_MAX_READS__SHIFT 0x18
+#define MC_RPB_TCI_CNTL2__TCI_POLICY_MASK 0x1
+#define MC_RPB_TCI_CNTL2__TCI_POLICY__SHIFT 0x0
+#define MC_RPB_TCI_CNTL2__TCI_MTYPE_MASK 0x6
+#define MC_RPB_TCI_CNTL2__TCI_MTYPE__SHIFT 0x1
+#define MC_RPB_TCI_CNTL2__TCI_SNOOP_MASK 0x8
+#define MC_RPB_TCI_CNTL2__TCI_SNOOP__SHIFT 0x3
+#define MC_RPB_TCI_CNTL2__TCI_PHYSICAL_MASK 0x10
+#define MC_RPB_TCI_CNTL2__TCI_PHYSICAL__SHIFT 0x4
+#define MC_RPB_TCI_CNTL2__TCI_PERF_CNTR_EN_MASK 0x20
+#define MC_RPB_TCI_CNTL2__TCI_PERF_CNTR_EN__SHIFT 0x5
+#define MC_RPB_TCI_CNTL2__TCI_EXE_MASK 0x40
+#define MC_RPB_TCI_CNTL2__TCI_EXE__SHIFT 0x6
+#define MC_SHARED_CHMAP__CHAN0_MASK 0xf
+#define MC_SHARED_CHMAP__CHAN0__SHIFT 0x0
+#define MC_SHARED_CHMAP__CHAN1_MASK 0xf0
+#define MC_SHARED_CHMAP__CHAN1__SHIFT 0x4
+#define MC_SHARED_CHMAP__CHAN2_MASK 0xf00
+#define MC_SHARED_CHMAP__CHAN2__SHIFT 0x8
+#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000
+#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc
+#define MC_SHARED_CHMAP__CHAN3_MASK 0xf0000
+#define MC_SHARED_CHMAP__CHAN3__SHIFT 0x10
+#define MC_SHARED_CHMAP__CHAN4_MASK 0xf00000
+#define MC_SHARED_CHMAP__CHAN4__SHIFT 0x14
+#define MC_SHARED_CHREMAP__CHAN0_MASK 0xf
+#define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x0
+#define MC_SHARED_CHREMAP__CHAN1_MASK 0xf0
+#define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x4
+#define MC_SHARED_CHREMAP__CHAN2_MASK 0xf00
+#define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x8
+#define MC_SHARED_CHREMAP__CHAN3_MASK 0xf000
+#define MC_SHARED_CHREMAP__CHAN3__SHIFT 0xc
+#define MC_SHARED_CHREMAP__CHAN4_MASK 0xf0000
+#define MC_SHARED_CHREMAP__CHAN4__SHIFT 0x10
+#define MC_SHARED_CHREMAP__CHAN5_MASK 0xf00000
+#define MC_SHARED_CHREMAP__CHAN5__SHIFT 0x14
+#define MC_SHARED_CHREMAP__CHAN6_MASK 0xf000000
+#define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x18
+#define MC_SHARED_CHREMAP__CHAN7_MASK 0xf0000000
+#define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x1c
+#define MC_RD_GRP_GFX__CP_MASK 0xf
+#define MC_RD_GRP_GFX__CP__SHIFT 0x0
+#define MC_RD_GRP_GFX__SH_MASK 0xf0
+#define MC_RD_GRP_GFX__SH__SHIFT 0x4
+#define MC_RD_GRP_GFX__IA_MASK 0xf00
+#define MC_RD_GRP_GFX__IA__SHIFT 0x8
+#define MC_RD_GRP_GFX__ACPG_MASK 0xf000
+#define MC_RD_GRP_GFX__ACPG__SHIFT 0xc
+#define MC_RD_GRP_GFX__ACPO_MASK 0xf0000
+#define MC_RD_GRP_GFX__ACPO__SHIFT 0x10
+#define MC_RD_GRP_GFX__XDMAM_MASK 0xf00000
+#define MC_RD_GRP_GFX__XDMAM__SHIFT 0x14
+#define MC_RD_GRP_GFX__ISP_MASK 0xf000000
+#define MC_RD_GRP_GFX__ISP__SHIFT 0x18
+#define MC_RD_GRP_GFX__VP8_MASK 0xf0000000
+#define MC_RD_GRP_GFX__VP8__SHIFT 0x1c
+#define MC_WR_GRP_GFX__CP_MASK 0xf
+#define MC_WR_GRP_GFX__CP__SHIFT 0x0
+#define MC_WR_GRP_GFX__SH_MASK 0xf0
+#define MC_WR_GRP_GFX__SH__SHIFT 0x4
+#define MC_WR_GRP_GFX__ACPG_MASK 0xf00
+#define MC_WR_GRP_GFX__ACPG__SHIFT 0x8
+#define MC_WR_GRP_GFX__ACPO_MASK 0xf000
+#define MC_WR_GRP_GFX__ACPO__SHIFT 0xc
+#define MC_WR_GRP_GFX__ISP_MASK 0xf0000
+#define MC_WR_GRP_GFX__ISP__SHIFT 0x10
+#define MC_WR_GRP_GFX__VP8_MASK 0xf00000
+#define MC_WR_GRP_GFX__VP8__SHIFT 0x14
+#define MC_WR_GRP_GFX__XDMA_MASK 0xf000000
+#define MC_WR_GRP_GFX__XDMA__SHIFT 0x18
+#define MC_WR_GRP_GFX__XDMAM_MASK 0xf0000000
+#define MC_WR_GRP_GFX__XDMAM__SHIFT 0x1c
+#define MC_RD_GRP_SYS__RLC_MASK 0xf
+#define MC_RD_GRP_SYS__RLC__SHIFT 0x0
+#define MC_RD_GRP_SYS__VMC_MASK 0xf0
+#define MC_RD_GRP_SYS__VMC__SHIFT 0x4
+#define MC_RD_GRP_SYS__SDMA1_MASK 0xf00
+#define MC_RD_GRP_SYS__SDMA1__SHIFT 0x8
+#define MC_RD_GRP_SYS__DMIF_MASK 0xf000
+#define MC_RD_GRP_SYS__DMIF__SHIFT 0xc
+#define MC_RD_GRP_SYS__MCIF_MASK 0xf0000
+#define MC_RD_GRP_SYS__MCIF__SHIFT 0x10
+#define MC_RD_GRP_SYS__SMU_MASK 0xf00000
+#define MC_RD_GRP_SYS__SMU__SHIFT 0x14
+#define MC_RD_GRP_SYS__VCE0_MASK 0xf000000
+#define MC_RD_GRP_SYS__VCE0__SHIFT 0x18
+#define MC_RD_GRP_SYS__VCE1_MASK 0xf0000000
+#define MC_RD_GRP_SYS__VCE1__SHIFT 0x1c
+#define MC_WR_GRP_SYS__IH_MASK 0xf
+#define MC_WR_GRP_SYS__IH__SHIFT 0x0
+#define MC_WR_GRP_SYS__MCIF_MASK 0xf0
+#define MC_WR_GRP_SYS__MCIF__SHIFT 0x4
+#define MC_WR_GRP_SYS__RLC_MASK 0xf00
+#define MC_WR_GRP_SYS__RLC__SHIFT 0x8
+#define MC_WR_GRP_SYS__SAMMSP_MASK 0xf000
+#define MC_WR_GRP_SYS__SAMMSP__SHIFT 0xc
+#define MC_WR_GRP_SYS__SMU_MASK 0xf0000
+#define MC_WR_GRP_SYS__SMU__SHIFT 0x10
+#define MC_WR_GRP_SYS__SDMA1_MASK 0xf00000
+#define MC_WR_GRP_SYS__SDMA1__SHIFT 0x14
+#define MC_WR_GRP_SYS__VCE0_MASK 0xf000000
+#define MC_WR_GRP_SYS__VCE0__SHIFT 0x18
+#define MC_WR_GRP_SYS__VCE1_MASK 0xf0000000
+#define MC_WR_GRP_SYS__VCE1__SHIFT 0x1c
+#define MC_RD_GRP_OTH__UVD_EXT0_MASK 0xf
+#define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x0
+#define MC_RD_GRP_OTH__SDMA0_MASK 0xf0
+#define MC_RD_GRP_OTH__SDMA0__SHIFT 0x4
+#define MC_RD_GRP_OTH__HDP_MASK 0xf00
+#define MC_RD_GRP_OTH__HDP__SHIFT 0x8
+#define MC_RD_GRP_OTH__SEM_MASK 0xf000
+#define MC_RD_GRP_OTH__SEM__SHIFT 0xc
+#define MC_RD_GRP_OTH__UMC_MASK 0xf0000
+#define MC_RD_GRP_OTH__UMC__SHIFT 0x10
+#define MC_RD_GRP_OTH__UVD_MASK 0xf00000
+#define MC_RD_GRP_OTH__UVD__SHIFT 0x14
+#define MC_RD_GRP_OTH__UVD_EXT1_MASK 0xf000000
+#define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x18
+#define MC_RD_GRP_OTH__SAMMSP_MASK 0xf0000000
+#define MC_RD_GRP_OTH__SAMMSP__SHIFT 0x1c
+#define MC_WR_GRP_OTH__UVD_EXT0_MASK 0xf
+#define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x0
+#define MC_WR_GRP_OTH__SDMA0_MASK 0xf0
+#define MC_WR_GRP_OTH__SDMA0__SHIFT 0x4
+#define MC_WR_GRP_OTH__HDP_MASK 0xf00
+#define MC_WR_GRP_OTH__HDP__SHIFT 0x8
+#define MC_WR_GRP_OTH__SEM_MASK 0xf000
+#define MC_WR_GRP_OTH__SEM__SHIFT 0xc
+#define MC_WR_GRP_OTH__UMC_MASK 0xf0000
+#define MC_WR_GRP_OTH__UMC__SHIFT 0x10
+#define MC_WR_GRP_OTH__UVD_MASK 0xf00000
+#define MC_WR_GRP_OTH__UVD__SHIFT 0x14
+#define MC_WR_GRP_OTH__XDP_MASK 0xf000000
+#define MC_WR_GRP_OTH__XDP__SHIFT 0x18
+#define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000
+#define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x1c
+#define MC_VM_FB_LOCATION__FB_BASE_MASK 0xffff
+#define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x0
+#define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000
+#define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x10
+#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x3ffff
+#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
+#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x3ffff
+#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
+#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x3ffff
+#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x3
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x0
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0xc
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x2
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x30
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x4
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0xc0
+#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x6
+#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x100
+#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x8
+#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x200
+#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x9
+#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
+#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x1
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x2
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x1
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x18
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x20
+#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x40
+#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
+#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x780
+#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
+#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x3ffff
+#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
+#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x3
+#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
+#define MC_SHARED_CHREMAP2__CHAN8_MASK 0xf
+#define MC_SHARED_CHREMAP2__CHAN8__SHIFT 0x0
+#define MC_SHARED_CHREMAP2__CHAN9_MASK 0xf0
+#define MC_SHARED_CHREMAP2__CHAN9__SHIFT 0x4
+#define MC_SHARED_CHREMAP2__CHAN10_MASK 0xf00
+#define MC_SHARED_CHREMAP2__CHAN10__SHIFT 0x8
+#define MC_SHARED_CHREMAP2__CHAN11_MASK 0xf000
+#define MC_SHARED_CHREMAP2__CHAN11__SHIFT 0xc
+#define MC_SHARED_CHREMAP2__CHAN12_MASK 0xf0000
+#define MC_SHARED_CHREMAP2__CHAN12__SHIFT 0x10
+#define MC_SHARED_CHREMAP2__CHAN13_MASK 0xf00000
+#define MC_SHARED_CHREMAP2__CHAN13__SHIFT 0x14
+#define MC_SHARED_CHREMAP2__CHAN14_MASK 0xf000000
+#define MC_SHARED_CHREMAP2__CHAN14__SHIFT 0x18
+#define MC_SHARED_CHREMAP2__CHAN15_MASK 0xf0000000
+#define MC_SHARED_CHREMAP2__CHAN15__SHIFT 0x1c
+#define MC_SHARED_VF_ENABLE__VF_ENABLE_MASK 0x1
+#define MC_SHARED_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0xffff
+#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000
+#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0xf
+#define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000
+#define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
+#define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
+#define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
+#define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
+#define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
+#define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
+#define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
+#define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
+#define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
+#define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
+#define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
+#define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
+#define MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40
+#define MC_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6
+#define MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80
+#define MC_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7
+#define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
+#define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
+#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800
+#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb
+#define MC_CONFIG_MCD__ARB0_WR_ENABLE_MASK 0x1000
+#define MC_CONFIG_MCD__ARB0_WR_ENABLE__SHIFT 0xc
+#define MC_CONFIG_MCD__ARB1_WR_ENABLE_MASK 0x2000
+#define MC_CONFIG_MCD__ARB1_WR_ENABLE__SHIFT 0xd
+#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000
+#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x1f
+#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
+#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
+#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
+#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
+#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
+#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
+#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
+#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
+#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
+#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
+#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
+#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
+#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40
+#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6
+#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80
+#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7
+#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
+#define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
+#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800
+#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb
+#define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000
+#define MC_CG_CONFIG_MCD__INDEX__SHIFT 0xd
+#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x3f
+#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
+#define MC_MEM_POWER_LS__LS_HOLD_MASK 0xfc0
+#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
+#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x7
+#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x0
+#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_SEQ_FREE_MASK 0x8
+#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_SEQ_FREE__SHIFT 0x3
+#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MCD_NUM_MASK 0xff0
+#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MCD_NUM__SHIFT 0x4
+#define MC_SHARED_BLACKOUT_CNTL__FREE_TIE_HIGH_MASK 0x1000
+#define MC_SHARED_BLACKOUT_CNTL__FREE_TIE_HIGH__SHIFT 0xc
+#define MC_SHARED_BLACKOUT_CNTL__SRBM_DUMMY_READ_RETURN_MASK 0x2000
+#define MC_SHARED_BLACKOUT_CNTL__SRBM_DUMMY_READ_RETURN__SHIFT 0xd
+#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MB_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MB_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MB_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MB_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x1
+#define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x1
+#define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x1
+#define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
+#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
+#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x1
+#define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x1
+#define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x1
+#define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x1
+#define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x0
+#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
+#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
+#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
+#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
+#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
+#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
+#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
+#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
+#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
+#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
+#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
+#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
+#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
+#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
+#define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x1
+#define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
+#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x1
+#define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0
+#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0xf00000
+#define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14
+#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x2000000
+#define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19
+#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
+#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
+#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
+#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
+#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
+#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
+#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
+#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
+#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
+#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
+#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
+#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
+#define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_EXTRA__CMP0_MASK 0xff
+#define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x0
+#define MC_XPB_CLG_EXTRA__MSK0_MASK 0xff00
+#define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x8
+#define MC_XPB_CLG_EXTRA__VLD0_MASK 0x10000
+#define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x10
+#define MC_XPB_CLG_EXTRA__CMP1_MASK 0x1fe0000
+#define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x11
+#define MC_XPB_CLG_EXTRA__VLD1_MASK 0x2000000
+#define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x19
+#define MC_XPB_LB_ADDR__CMP0_MASK 0x3ff
+#define MC_XPB_LB_ADDR__CMP0__SHIFT 0x0
+#define MC_XPB_LB_ADDR__MASK0_MASK 0xffc00
+#define MC_XPB_LB_ADDR__MASK0__SHIFT 0xa
+#define MC_XPB_LB_ADDR__CMP1_MASK 0x3f00000
+#define MC_XPB_LB_ADDR__CMP1__SHIFT 0x14
+#define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000
+#define MC_XPB_LB_ADDR__MASK1__SHIFT 0x1a
+#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x3f
+#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x0
+#define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0xfc0
+#define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x6
+#define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x3f000
+#define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0xc
+#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x3f
+#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x0
+#define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0xfc0
+#define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x6
+#define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x3f000
+#define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0xc
+#define MC_XPB_WCB_STS__PBUF_VLD_MASK 0xffff
+#define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x0
+#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x7f0000
+#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10
+#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000
+#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17
+#define MC_XPB_WCB_CFG__TIMEOUT_MASK 0xffff
+#define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x0
+#define MC_XPB_WCB_CFG__HST_MAX_MASK 0x30000
+#define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x10
+#define MC_XPB_WCB_CFG__SID_MAX_MASK 0xc0000
+#define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x12
+#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0xf
+#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0
+#define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x30
+#define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x40
+#define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6
+#define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x80
+#define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7
+#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x100
+#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8
+#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x200
+#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9
+#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x400
+#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa
+#define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x800
+#define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb
+#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x1000
+#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc
+#define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR0__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR0__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR0__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR1__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR1__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR1__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR2__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR2__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR2__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR3__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR3__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR3__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR4__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR4__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR4__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR5__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR5__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR5__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR6__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR6__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR6__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0xf
+#define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0
+#define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0xf0
+#define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4
+#define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR7__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR7__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR7__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0xff
+#define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0
+#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0xf00
+#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8
+#define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x1000
+#define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc
+#define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x2000
+#define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd
+#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x4000
+#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe
+#define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x8000
+#define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf
+#define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000
+#define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10
+#define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0xff
+#define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x0
+#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0xf00
+#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x8
+#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0xf000
+#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0xc
+#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0xff
+#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0
+#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0xfffff00
+#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8
+#define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0xff
+#define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0
+#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0xfffff00
+#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8
+#define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x2
+#define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x1
+#define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0
+#define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x2
+#define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x1
+#define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x7fffffc
+#define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0
+#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
+#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0
+#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
+#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0
+#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
+#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0
+#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
+#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
+#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
+#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x2
+#define MC_XPB_CLK_GAT__ONDLY_MASK 0x3f
+#define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x0
+#define MC_XPB_CLK_GAT__OFFDLY_MASK 0xfc0
+#define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x6
+#define MC_XPB_CLK_GAT__RDYDLY_MASK 0x3f000
+#define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0xc
+#define MC_XPB_CLK_GAT__ENABLE_MASK 0x40000
+#define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x12
+#define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x80000
+#define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13
+#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0xff
+#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0
+#define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0xff00
+#define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8
+#define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x7f0000
+#define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10
+#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x800000
+#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17
+#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x1000000
+#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18
+#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x2000000
+#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19
+#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x4000000
+#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a
+#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000
+#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b
+#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000
+#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d
+#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000
+#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e
+#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000
+#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f
+#define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0xff
+#define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0
+#define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x7f00
+#define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8
+#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x8000
+#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf
+#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x10000
+#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10
+#define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x20000
+#define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11
+#define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x40000
+#define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12
+#define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x7f80000
+#define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13
+#define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x1
+#define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0
+#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0xfe
+#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1
+#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x7f00
+#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8
+#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x8000
+#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf
+#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x10000
+#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10
+#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x20000
+#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11
+#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x40000
+#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12
+#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x80000
+#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13
+#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x100000
+#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14
+#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x200000
+#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15
+#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x400000
+#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16
+#define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x800000
+#define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17
+#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000
+#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18
+#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x1
+#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0
+#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x2
+#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1
+#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x4
+#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2
+#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x8
+#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3
+#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x10
+#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4
+#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x20
+#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5
+#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x40
+#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6
+#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x80
+#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7
+#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x100
+#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8
+#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x200
+#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9
+#define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x400
+#define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa
+#define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x800
+#define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb
+#define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x1000
+#define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0xc
+#define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x2000
+#define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd
+#define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x4000
+#define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe
+#define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x8000
+#define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0xf
+#define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x10000
+#define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10
+#define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x20000
+#define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x11
+#define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x40000
+#define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12
+#define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x80000
+#define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13
+#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0xffff
+#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0
+#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x3f
+#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0
+#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0xfc0
+#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6
+#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x3f000
+#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc
+#define MC_XPB_STICKY__BITS_MASK 0xffffffff
+#define MC_XPB_STICKY__BITS__SHIFT 0x0
+#define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffff
+#define MC_XPB_STICKY_W1C__BITS__SHIFT 0x0
+#define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0xff
+#define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0
+#define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0xff00
+#define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8
+#define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0xff0000
+#define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10
+#define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000
+#define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18
+#define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000
+#define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f
+#define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0xff
+#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0
+#define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0xff
+#define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x0
+#define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0xff00
+#define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x8
+#define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x10000
+#define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x10
+#define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x1fe0000
+#define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x11
+#define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x2000000
+#define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x19
+#define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0xe
+#define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0xf
+#define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x0
+#define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x70
+#define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x4
+#define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x380
+#define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x7
+#define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x3c00
+#define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0xa
+#define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x3c000
+#define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0xe
+#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x1
+#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3__SHIFT 0x0
+#define MC_XBAR_ADDR_DEC__GECC_MASK 0x2
+#define MC_XBAR_ADDR_DEC__GECC__SHIFT 0x1
+#define MC_XBAR_ADDR_DEC__RB_SPLIT_MASK 0x4
+#define MC_XBAR_ADDR_DEC__RB_SPLIT__SHIFT 0x2
+#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI_MASK 0x8
+#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI__SHIFT 0x3
+#define MC_XBAR_REMOTE__WRREQ_EN_GOQ_MASK 0x1
+#define MC_XBAR_REMOTE__WRREQ_EN_GOQ__SHIFT 0x0
+#define MC_XBAR_REMOTE__RDREQ_EN_GOQ_MASK 0x2
+#define MC_XBAR_REMOTE__RDREQ_EN_GOQ__SHIFT 0x1
+#define MC_XBAR_WRREQ_CREDIT__OUT0_MASK 0xff
+#define MC_XBAR_WRREQ_CREDIT__OUT0__SHIFT 0x0
+#define MC_XBAR_WRREQ_CREDIT__OUT1_MASK 0xff00
+#define MC_XBAR_WRREQ_CREDIT__OUT1__SHIFT 0x8
+#define MC_XBAR_WRREQ_CREDIT__OUT2_MASK 0xff0000
+#define MC_XBAR_WRREQ_CREDIT__OUT2__SHIFT 0x10
+#define MC_XBAR_WRREQ_CREDIT__OUT3_MASK 0xff000000
+#define MC_XBAR_WRREQ_CREDIT__OUT3__SHIFT 0x18
+#define MC_XBAR_RDREQ_CREDIT__OUT0_MASK 0xff
+#define MC_XBAR_RDREQ_CREDIT__OUT0__SHIFT 0x0
+#define MC_XBAR_RDREQ_CREDIT__OUT1_MASK 0xff00
+#define MC_XBAR_RDREQ_CREDIT__OUT1__SHIFT 0x8
+#define MC_XBAR_RDREQ_CREDIT__OUT2_MASK 0xff0000
+#define MC_XBAR_RDREQ_CREDIT__OUT2__SHIFT 0x10
+#define MC_XBAR_RDREQ_CREDIT__OUT3_MASK 0xff000000
+#define MC_XBAR_RDREQ_CREDIT__OUT3__SHIFT 0x18
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0_MASK 0xff
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0__SHIFT 0x0
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1_MASK 0xff00
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1__SHIFT 0x8
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2_MASK 0xff0000
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2__SHIFT 0x10
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3_MASK 0xff000000
+#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3__SHIFT 0x18
+#define MC_XBAR_WRRET_CREDIT1__OUT0_MASK 0xff
+#define MC_XBAR_WRRET_CREDIT1__OUT0__SHIFT 0x0
+#define MC_XBAR_WRRET_CREDIT1__OUT1_MASK 0xff00
+#define MC_XBAR_WRRET_CREDIT1__OUT1__SHIFT 0x8
+#define MC_XBAR_WRRET_CREDIT1__OUT2_MASK 0xff0000
+#define MC_XBAR_WRRET_CREDIT1__OUT2__SHIFT 0x10
+#define MC_XBAR_WRRET_CREDIT1__OUT3_MASK 0xff000000
+#define MC_XBAR_WRRET_CREDIT1__OUT3__SHIFT 0x18
+#define MC_XBAR_WRRET_CREDIT2__OUT4_MASK 0xff
+#define MC_XBAR_WRRET_CREDIT2__OUT4__SHIFT 0x0
+#define MC_XBAR_WRRET_CREDIT2__OUT5_MASK 0xff00
+#define MC_XBAR_WRRET_CREDIT2__OUT5__SHIFT 0x8
+#define MC_XBAR_RDRET_CREDIT1__OUT0_MASK 0xff
+#define MC_XBAR_RDRET_CREDIT1__OUT0__SHIFT 0x0
+#define MC_XBAR_RDRET_CREDIT1__OUT1_MASK 0xff00
+#define MC_XBAR_RDRET_CREDIT1__OUT1__SHIFT 0x8
+#define MC_XBAR_RDRET_CREDIT1__OUT2_MASK 0xff0000
+#define MC_XBAR_RDRET_CREDIT1__OUT2__SHIFT 0x10
+#define MC_XBAR_RDRET_CREDIT1__OUT3_MASK 0xff000000
+#define MC_XBAR_RDRET_CREDIT1__OUT3__SHIFT 0x18
+#define MC_XBAR_RDRET_CREDIT2__OUT4_MASK 0xff
+#define MC_XBAR_RDRET_CREDIT2__OUT4__SHIFT 0x0
+#define MC_XBAR_RDRET_CREDIT2__OUT5_MASK 0xff00
+#define MC_XBAR_RDRET_CREDIT2__OUT5__SHIFT 0x8
+#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID_MASK 0xff0000
+#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID__SHIFT 0x10
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0_MASK 0xff
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0__SHIFT 0x0
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1_MASK 0xff00
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1__SHIFT 0x8
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2_MASK 0xff0000
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2__SHIFT 0x10
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3_MASK 0xff000000
+#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3__SHIFT 0x18
+#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4_MASK 0xff
+#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4__SHIFT 0x0
+#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5_MASK 0xff00
+#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5__SHIFT 0x8
+#define MC_XBAR_CHTRIREMAP__CH0_MASK 0x3
+#define MC_XBAR_CHTRIREMAP__CH0__SHIFT 0x0
+#define MC_XBAR_CHTRIREMAP__CH1_MASK 0xc
+#define MC_XBAR_CHTRIREMAP__CH1__SHIFT 0x2
+#define MC_XBAR_CHTRIREMAP__CH2_MASK 0x30
+#define MC_XBAR_CHTRIREMAP__CH2__SHIFT 0x4
+#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT_MASK 0x1
+#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT__SHIFT 0x0
+#define MC_XBAR_TWOCHAN__CH0_MASK 0x6
+#define MC_XBAR_TWOCHAN__CH0__SHIFT 0x1
+#define MC_XBAR_TWOCHAN__CH1_MASK 0x18
+#define MC_XBAR_TWOCHAN__CH1__SHIFT 0x3
+#define MC_XBAR_ARB__HUBRD_HIGHEST_MASK 0x1
+#define MC_XBAR_ARB__HUBRD_HIGHEST__SHIFT 0x0
+#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST_MASK 0x2
+#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST__SHIFT 0x1
+#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE_MASK 0x4
+#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE__SHIFT 0x2
+#define MC_XBAR_ARB__ACP_RDRET_URG_MASK 0x8
+#define MC_XBAR_ARB__ACP_RDRET_URG__SHIFT 0x3
+#define MC_XBAR_ARB__HDP_RDRET_URG_MASK 0x10
+#define MC_XBAR_ARB__HDP_RDRET_URG__SHIFT 0x4
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT0_MASK 0xf
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT0__SHIFT 0x0
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT1_MASK 0xf0
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT1__SHIFT 0x4
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT2_MASK 0xf00
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT2__SHIFT 0x8
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT3_MASK 0xf000
+#define MC_XBAR_ARB_MAX_BURST__RD_PORT3__SHIFT 0xc
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT0_MASK 0xf0000
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT0__SHIFT 0x10
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT1_MASK 0xf00000
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT1__SHIFT 0x14
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT2_MASK 0xf000000
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT2__SHIFT 0x18
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT3_MASK 0xf0000000
+#define MC_XBAR_ARB_MAX_BURST__WR_PORT3__SHIFT 0x1c
+#define MC_XBAR_FIFO_MON_CNTL0__START_THRESH_MASK 0xfff
+#define MC_XBAR_FIFO_MON_CNTL0__START_THRESH__SHIFT 0x0
+#define MC_XBAR_FIFO_MON_CNTL0__STOP_THRESH_MASK 0xfff000
+#define MC_XBAR_FIFO_MON_CNTL0__STOP_THRESH__SHIFT 0xc
+#define MC_XBAR_FIFO_MON_CNTL0__START_MODE_MASK 0x3000000
+#define MC_XBAR_FIFO_MON_CNTL0__START_MODE__SHIFT 0x18
+#define MC_XBAR_FIFO_MON_CNTL0__STOP_MODE_MASK 0xc000000
+#define MC_XBAR_FIFO_MON_CNTL0__STOP_MODE__SHIFT 0x1a
+#define MC_XBAR_FIFO_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000
+#define MC_XBAR_FIFO_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c
+#define MC_XBAR_FIFO_MON_CNTL1__THRESH_CNTR_ID_MASK 0xff
+#define MC_XBAR_FIFO_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0
+#define MC_XBAR_FIFO_MON_CNTL1__START_TRIG_ID_MASK 0xff00
+#define MC_XBAR_FIFO_MON_CNTL1__START_TRIG_ID__SHIFT 0x8
+#define MC_XBAR_FIFO_MON_CNTL1__STOP_TRIG_ID_MASK 0xff0000
+#define MC_XBAR_FIFO_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x10
+#define MC_XBAR_FIFO_MON_CNTL2__MON0_ID_MASK 0xff
+#define MC_XBAR_FIFO_MON_CNTL2__MON0_ID__SHIFT 0x0
+#define MC_XBAR_FIFO_MON_CNTL2__MON1_ID_MASK 0xff00
+#define MC_XBAR_FIFO_MON_CNTL2__MON1_ID__SHIFT 0x8
+#define MC_XBAR_FIFO_MON_CNTL2__MON2_ID_MASK 0xff0000
+#define MC_XBAR_FIFO_MON_CNTL2__MON2_ID__SHIFT 0x10
+#define MC_XBAR_FIFO_MON_CNTL2__MON3_ID_MASK 0xff000000
+#define MC_XBAR_FIFO_MON_CNTL2__MON3_ID__SHIFT 0x18
+#define MC_XBAR_FIFO_MON_RSLT0__COUNT_MASK 0xffffffff
+#define MC_XBAR_FIFO_MON_RSLT0__COUNT__SHIFT 0x0
+#define MC_XBAR_FIFO_MON_RSLT1__COUNT_MASK 0xffffffff
+#define MC_XBAR_FIFO_MON_RSLT1__COUNT__SHIFT 0x0
+#define MC_XBAR_FIFO_MON_RSLT2__COUNT_MASK 0xffffffff
+#define MC_XBAR_FIFO_MON_RSLT2__COUNT__SHIFT 0x0
+#define MC_XBAR_FIFO_MON_RSLT3__COUNT_MASK 0xffffffff
+#define MC_XBAR_FIFO_MON_RSLT3__COUNT__SHIFT 0x0
+#define MC_XBAR_FIFO_MON_MAX_THSH__MON0_MASK 0xff
+#define MC_XBAR_FIFO_MON_MAX_THSH__MON0__SHIFT 0x0
+#define MC_XBAR_FIFO_MON_MAX_THSH__MON1_MASK 0xff00
+#define MC_XBAR_FIFO_MON_MAX_THSH__MON1__SHIFT 0x8
+#define MC_XBAR_FIFO_MON_MAX_THSH__MON2_MASK 0xff0000
+#define MC_XBAR_FIFO_MON_MAX_THSH__MON2__SHIFT 0x10
+#define MC_XBAR_FIFO_MON_MAX_THSH__MON3_MASK 0xff000000
+#define MC_XBAR_FIFO_MON_MAX_THSH__MON3__SHIFT 0x18
+#define MC_XBAR_SPARE0__BIT_MASK 0xffffffff
+#define MC_XBAR_SPARE0__BIT__SHIFT 0x0
+#define MC_XBAR_SPARE1__BIT_MASK 0xffffffff
+#define MC_XBAR_SPARE1__BIT__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_CITF_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_CITF_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_CITF_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_CITF_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_CITF_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_CITF_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_CITF_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_CITF_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_CITF_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_CITF_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_CITF_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_CITF_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_CITF_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_CITF_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_CITF_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_CITF_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_HUB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_HUB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_HUB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_HUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_HUB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_HUB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_HUB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_HUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_HUB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_HUB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_HUB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_HUB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_HUB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_HUB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_HUB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_HUB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_ARB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_ARB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_ARB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_ARB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_ARB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_ARB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_ARB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_ARB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_ARB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_ARB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_ARB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_ARB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_ARB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_ARB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_ARB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_ARB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
+#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
+#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
+#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
+#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
+#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
+#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
+#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
+#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
+#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
+#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
+#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define MC_GRUB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
+#define MC_GRUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
+#define MC_GRUB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
+#define MC_GRUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
+#define MC_GRUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
+#define MC_GRUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
+#define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
+#define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
+#define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_GRUB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
+#define MC_GRUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
+#define MC_GRUB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
+#define MC_GRUB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
+#define MC_GRUB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
+#define MC_GRUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
+#define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
+#define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
+#define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
+#define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
+#define MC_GRUB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
+#define MC_GRUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
+#define MC_GRUB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
+#define MC_GRUB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
+#define MC_GRUB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
+#define MC_GRUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
+#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
+#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
+#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
+#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
+#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
+#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
+#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
+#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
+#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
+#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
+#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
+#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
+#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
+#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
+#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
+#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
+#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
+#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
+#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
+#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
+#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x3
+#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x0
+#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x3
+#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x0
+#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0xffff
+#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0
+#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0xffff
+#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0
+#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x1
+#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0
+#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x2
+#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1
+#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x4
+#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2
+#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x3f00
+#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
+#define ATC_ATS_CNTL__DEBUG_ECO_MASK 0xf0000
+#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x10
+#define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x1
+#define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x0
+#define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x2
+#define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x1
+#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x4
+#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x2
+#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x20
+#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x5
+#define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x40
+#define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x6
+#define ATC_ATS_DEBUG__EXE_BIT_MASK 0x80
+#define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x7
+#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x100
+#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x8
+#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x200
+#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x9
+#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x3c00
+#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0xa
+#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x4000
+#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0xe
+#define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x8000
+#define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0xf
+#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x10000
+#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x10
+#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT_MASK 0x20000
+#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT__SHIFT 0x11
+#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x40000
+#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x12
+#define ATC_ATS_DEBUG__DISABLE_VMID0_PASID_MAPPING_MASK 0x80000
+#define ATC_ATS_DEBUG__DISABLE_VMID0_PASID_MAPPING__SHIFT 0x13
+#define ATC_ATS_DEBUG__DISABLE_INVALIDATION_ON_WORLD_SWITCH_MASK 0x100000
+#define ATC_ATS_DEBUG__DISABLE_INVALIDATION_ON_WORLD_SWITCH__SHIFT 0x14
+#define ATC_ATS_DEBUG__ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT_MASK 0x200000
+#define ATC_ATS_DEBUG__ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT__SHIFT 0x15
+#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x1f
+#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x0
+#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x100
+#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x8
+#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x10000
+#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x10
+#define ATC_ATS_STATUS__BUSY_MASK 0x1
+#define ATC_ATS_STATUS__BUSY__SHIFT 0x0
+#define ATC_ATS_STATUS__CRASHED_MASK 0x2
+#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1
+#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x4
+#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2
+#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x1ff
+#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0
+#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x7fc00
+#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa
+#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1ff00000
+#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14
+#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x1ff
+#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0
+#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x7c00
+#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x8000
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x10000
+#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10
+#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x20000
+#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x40000
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12
+#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0xf80000
+#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0xf000000
+#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18
+#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffff
+#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0
+#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xfffffff
+#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0
+#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x1
+#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x0
+#define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x1
+#define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0
+#define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x3e
+#define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1
+#define ATC_ATS_FAULT_STATUS_INFO2__L1_ID_MASK 0x1fe00
+#define ATC_ATS_FAULT_STATUS_INFO2__L1_ID__SHIFT 0x9
+#define ATC_MISC_CG__OFFDLY_MASK 0xfc0
+#define ATC_MISC_CG__OFFDLY__SHIFT 0x6
+#define ATC_MISC_CG__ENABLE_MASK 0x40000
+#define ATC_MISC_CG__ENABLE__SHIFT 0x12
+#define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x80000
+#define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x3
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x30
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x4
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x100
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x8
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x200
+#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x9
+#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x3f
+#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0xc0
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6
+#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x100
+#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8
+#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0xe00
+#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9
+#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x7000
+#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f8000
+#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf
+#define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x3f
+#define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x0
+#define ATC_L2_DEBUG__L2_MEM_SELECT_MASK 0x80
+#define ATC_L2_DEBUG__L2_MEM_SELECT__SHIFT 0x7
+#define ATC_L2_DEBUG__CACHE_INDEX_MASK 0xfff00
+#define ATC_L2_DEBUG__CACHE_INDEX__SHIFT 0x8
+#define ATC_L2_DEBUG__CACHE_SELECT_MASK 0x1000000
+#define ATC_L2_DEBUG__CACHE_SELECT__SHIFT 0x18
+#define ATC_L2_DEBUG__CACHE_BANK_SELECT_MASK 0x2000000
+#define ATC_L2_DEBUG__CACHE_BANK_SELECT__SHIFT 0x19
+#define ATC_L2_DEBUG__CACHE_WAY_SELECT_MASK 0x8000000
+#define ATC_L2_DEBUG__CACHE_WAY_SELECT__SHIFT 0x1b
+#define ATC_L2_DEBUG__CACHE_READ_MASK 0x20000000
+#define ATC_L2_DEBUG__CACHE_READ__SHIFT 0x1d
+#define ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR_MASK 0x40000000
+#define ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR__SHIFT 0x1e
+#define ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR_MASK 0x80000000
+#define ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR__SHIFT 0x1f
+#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE_MASK 0x1f
+#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE__SHIFT 0x0
+#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0xe0
+#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x5
+#define ATC_L2_DEBUG2__FORCE_CACHE_MISS_MASK 0x100
+#define ATC_L2_DEBUG2__FORCE_CACHE_MISS__SHIFT 0x8
+#define ATC_L2_DEBUG2__INVALIDATE_ALL_MASK 0x200
+#define ATC_L2_DEBUG2__INVALIDATE_ALL__SHIFT 0x9
+#define ATC_L2_DEBUG2__DISABLE_2M_CACHE_MASK 0x400
+#define ATC_L2_DEBUG2__DISABLE_2M_CACHE__SHIFT 0xa
+#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS_MASK 0x800
+#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS__SHIFT 0xb
+#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS_MASK 0x4000
+#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0xe
+#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT_MASK 0x18000
+#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT__SHIFT 0xf
+#define ATC_L2_DEBUG2__DEBUG_ECO_MASK 0x60000
+#define ATC_L2_DEBUG2__DEBUG_ECO__SHIFT 0x11
+#define ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE_MASK 0x780000
+#define ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE__SHIFT 0x13
+#define ATC_L2_DEBUG2__CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD_MASK 0x7f800000
+#define ATC_L2_DEBUG2__CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD__SHIFT 0x17
+#define ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO_MASK 0x80000000
+#define ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO__SHIFT 0x1f
+#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x1
+#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0
+#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x2
+#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1
+#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x1fffffc
+#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2
+#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x1e000000
+#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x19
+#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xffffffff
+#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0
+#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_LOW_MASK 0xfffffff
+#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_LOW__SHIFT 0x0
+#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x3
+#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x0
+#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x4
+#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x2
+#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x10
+#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x4
+#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffff
+#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x0
+#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
+#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
+#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
+#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
+#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
+#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
+#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
+#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
+#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
+#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
+#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
+#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
+#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
+#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
+#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
+#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
+#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000
+#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f
+#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
+#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
+#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
+#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
+#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
+#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
+#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
+#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
+#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
+#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
+#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
+#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
+#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
+#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
+#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
+#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
+#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000
+#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f
+#define ATC_L1RD_STATUS__BUSY_MASK 0x1
+#define ATC_L1RD_STATUS__BUSY__SHIFT 0x0
+#define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x2
+#define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
+#define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x100
+#define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x8
+#define ATC_L1RD_STATUS__CAM_PARITY_ERRORS_MASK 0x1f000
+#define ATC_L1RD_STATUS__CAM_PARITY_ERRORS__SHIFT 0xc
+#define ATC_L1RD_STATUS__CAM_INDEX_MASK 0x3e0000
+#define ATC_L1RD_STATUS__CAM_INDEX__SHIFT 0x11
+#define ATC_L1WR_STATUS__BUSY_MASK 0x1
+#define ATC_L1WR_STATUS__BUSY__SHIFT 0x0
+#define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x2
+#define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
+#define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x100
+#define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x8
+#define ATC_L1WR_STATUS__CAM_PARITY_ERRORS_MASK 0x1f000
+#define ATC_L1WR_STATUS__CAM_PARITY_ERRORS__SHIFT 0xc
+#define ATC_L1WR_STATUS__CAM_INDEX_MASK 0x3e0000
+#define ATC_L1WR_STATUS__CAM_INDEX__SHIFT 0x11
+#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_PERIOD_MASK 0xfff
+#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_PERIOD__SHIFT 0x0
+#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_MODE_MASK 0xc000
+#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_MODE__SHIFT 0xe
+#define ATC_L1RD_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR_MASK 0x10000
+#define ATC_L1RD_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR__SHIFT 0x10
+#define ATC_L1RD_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR_MASK 0x20000
+#define ATC_L1RD_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR__SHIFT 0x11
+#define ATC_L1RD_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR_MASK 0x40000
+#define ATC_L1RD_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR__SHIFT 0x12
+#define ATC_L1RD_DEBUG2_TLB__CAM_INDEX_MASK 0xf80000
+#define ATC_L1RD_DEBUG2_TLB__CAM_INDEX__SHIFT 0x13
+#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_PERIOD_MASK 0xfff
+#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_PERIOD__SHIFT 0x0
+#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_MODE_MASK 0xc000
+#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_MODE__SHIFT 0xe
+#define ATC_L1WR_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR_MASK 0x10000
+#define ATC_L1WR_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR__SHIFT 0x10
+#define ATC_L1WR_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR_MASK 0x20000
+#define ATC_L1WR_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR__SHIFT 0x11
+#define ATC_L1WR_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR_MASK 0x40000
+#define ATC_L1WR_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR__SHIFT 0x12
+#define ATC_L1WR_DEBUG2_TLB__CAM_INDEX_MASK 0xf80000
+#define ATC_L1WR_DEBUG2_TLB__CAM_INDEX__SHIFT 0x13
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x1
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x2
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x4
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x8
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x10
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x20
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x40
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x80
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x100
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x200
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x400
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x800
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x1000
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x2000
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x4000
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x8000
+#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf
+#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0xffff
+#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0
+#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
+#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
+#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000
+#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f
+#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x1
+#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0
+#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x2
+#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1
+#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x4
+#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2
+#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x8
+#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3
+#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x10
+#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4
+#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x20
+#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5
+#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x40
+#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6
+#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x80
+#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7
+#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x100
+#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8
+#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x200
+#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9
+#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x400
+#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa
+#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x800
+#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb
+#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x1000
+#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc
+#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x2000
+#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd
+#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x4000
+#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe
+#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x8000
+#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf
+#define ATC_ATS_SMU_STATUS__VDDGFX_POWERED_DOWN_MASK 0x1
+#define ATC_ATS_SMU_STATUS__VDDGFX_POWERED_DOWN__SHIFT 0x0
+#define ATC_L2_CNTL3__ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING_MASK 0x7f
+#define ATC_L2_CNTL3__ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING__SHIFT 0x0
+#define ATC_L2_CNTL3__ENABLE_FREE_COUNTER_MASK 0x80
+#define ATC_L2_CNTL3__ENABLE_FREE_COUNTER__SHIFT 0x7
+#define ATC_L2_CNTL3__L2_CACHE_EVICTION_THRESHOLD_MASK 0x1f00
+#define ATC_L2_CNTL3__L2_CACHE_EVICTION_THRESHOLD__SHIFT 0x8
+#define ATC_L2_CNTL3__DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION_MASK 0x2000
+#define ATC_L2_CNTL3__DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION__SHIFT 0xd
+#define ATC_L2_CNTL3__L2_DELAY_SEND_INVALIDATION_REQUEST_MASK 0x1c000
+#define ATC_L2_CNTL3__L2_DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0xe
+#define ATC_L2_STATUS__BUSY_MASK 0x1
+#define ATC_L2_STATUS__BUSY__SHIFT 0x0
+#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3ffffffe
+#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1
+#define ATC_L2_STATUS2__CACHE_ADDRESS_MODE_MASK 0x7
+#define ATC_L2_STATUS2__CACHE_ADDRESS_MODE__SHIFT 0x0
+#define ATC_L2_STATUS2__PARITY_ERROR_INFO_MASK 0x7f8
+#define ATC_L2_STATUS2__PARITY_ERROR_INFO__SHIFT 0x3
+#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x3ff
+#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0
+#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffff
+#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x1
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x2
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0xffc
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x3ff000
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0xc
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc00000
+#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x16
+#define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x400
+#define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0xa
+#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x800
+#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0xb
+#define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0xf000
+#define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0xc
+#define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x10000
+#define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x10
+#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x60000
+#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x11
+#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x180000
+#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x13
+#define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x200000
+#define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x15
+#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x400000
+#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x16
+#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x800000
+#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x17
+#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x1000000
+#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x18
+#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x2000000
+#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x19
+#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x4000000
+#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x1a
+#define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x8000000
+#define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x1b
+#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x70000000
+#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1c
+#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x80000000
+#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x1f
+#define GMCON_MISC2__GMCON_MISC2_RESERVED0_MASK 0x3f
+#define GMCON_MISC2__GMCON_MISC2_RESERVED0__SHIFT 0x0
+#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD_MASK 0x7c0
+#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD__SHIFT 0x6
+#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x1f800
+#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0xb
+#define GMCON_MISC2__GMCON_MISC2_RESERVED1_MASK 0x1ffe0000
+#define GMCON_MISC2__GMCON_MISC2_RESERVED1__SHIFT 0x11
+#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x20000000
+#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x1d
+#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x40000000
+#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x1e
+#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE_MASK 0x80000000
+#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE__SHIFT 0x1f
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0xffff
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x0
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff0000
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x10
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0xffff
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x0
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff0000
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x10
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0xffff
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x0
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff0000
+#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x10
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0xffff
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff0000
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0xffff
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff0000
+#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10
+#define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0xfff
+#define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0
+#define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000
+#define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc
+#define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x3000000
+#define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x18
+#define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000
+#define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a
+#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000
+#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c
+#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT_MASK 0x20000000
+#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT__SHIFT 0x1d
+#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT_MASK 0x40000000
+#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT__SHIFT 0x1e
+#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT_MASK 0x80000000
+#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT__SHIFT 0x1f
+#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x3f
+#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0
+#define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xfc0
+#define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x6
+#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x3f000
+#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0xc
+#define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0x1fc0000
+#define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x12
+#define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0xfe000000
+#define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x19
+#define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffff
+#define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x0
+#define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffff
+#define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x0
+#define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0xff
+#define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
+#define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x100
+#define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
+#define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x200
+#define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
+#define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x400
+#define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
+#define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x800
+#define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
+#define GMCON_PGFSM_CONFIG__WRITE_MASK 0x1000
+#define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0xc
+#define GMCON_PGFSM_CONFIG__READ_MASK 0x2000
+#define GMCON_PGFSM_CONFIG__READ__SHIFT 0xd
+#define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x7ffc000
+#define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0xe
+#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000
+#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
+#define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000
+#define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
+#define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffff
+#define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x0
+#define GMCON_PGFSM_READ__READ_VALUE_MASK 0xffffff
+#define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x0
+#define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0xf000000
+#define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x18
+#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x10000000
+#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x1c
+#define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0xff
+#define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x0
+#define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0xff00
+#define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x8
+#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0xfff0000
+#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10
+#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER_MASK 0x10000000
+#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER__SHIFT 0x1c
+#define GMCON_MISC3__RENG_MEM_LS_ENABLE_MASK 0x20000000
+#define GMCON_MISC3__RENG_MEM_LS_ENABLE__SHIFT 0x1d
+#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS_MASK 0x40000000
+#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS__SHIFT 0x1e
+#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD_MASK 0x1
+#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD__SHIFT 0x0
+#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR_MASK 0x2
+#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR__SHIFT 0x1
+#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD_MASK 0x4
+#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD__SHIFT 0x2
+#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR_MASK 0x8
+#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR__SHIFT 0x3
+#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK_MASK 0xff0
+#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK__SHIFT 0x4
+#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET_MASK 0xffffffff
+#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET__SHIFT 0x0
+#define GMCON_DEBUG__GFX_STALL_MASK 0x1
+#define GMCON_DEBUG__GFX_STALL__SHIFT 0x0
+#define GMCON_DEBUG__GFX_CLEAR_MASK 0x2
+#define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x1
+#define GMCON_DEBUG__GMCON_DEBUG_RESERVED0_MASK 0x4
+#define GMCON_DEBUG__GMCON_DEBUG_RESERVED0__SHIFT 0x2
+#define GMCON_DEBUG__SR_COMMIT_STATE_MASK 0x8
+#define GMCON_DEBUG__SR_COMMIT_STATE__SHIFT 0x3
+#define GMCON_DEBUG__STCTRL_ST_MASK 0xf0
+#define GMCON_DEBUG__STCTRL_ST__SHIFT 0x4
+#define GMCON_DEBUG__MISC_FLAGS_MASK 0xffffff00
+#define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x8
+#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x1
+#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
+#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x2
+#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
+#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0xc
+#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
+#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x30
+#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
+#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x100
+#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
+#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x200
+#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
+#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400
+#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
+#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x800
+#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
+#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x7000
+#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
+#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x38000
+#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
+#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x40000
+#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
+#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x180000
+#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
+#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x3e00000
+#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
+#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0xc000000
+#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a
+#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000
+#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c
+#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x1
+#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
+#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x2
+#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
+#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x200000
+#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
+#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x400000
+#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
+#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x3800000
+#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17
+#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0xc000000
+#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
+#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000
+#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
+#define VM_L2_CNTL3__BANK_SELECT_MASK 0x3f
+#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0xc0
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f00
+#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0xf8000
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
+#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x100000
+#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
+#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0xe00000
+#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
+#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0xf000000
+#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
+#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000
+#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000
+#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
+#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000
+#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
+#define VM_L2_STATUS__L2_BUSY_MASK 0x1
+#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0
+#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x1fffe
+#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
+#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x1
+#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x6
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
+#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
+#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800
+#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000
+#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000
+#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000
+#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000
+#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000
+#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18
+#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x1
+#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x6
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
+#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
+#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800
+#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000
+#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000
+#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000
+#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000
+#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000
+#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x1
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x2
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK 0xc
+#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT 0x2
+#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK 0xfffffff
+#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT 0x0
+#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1
+#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
+#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2
+#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1
+#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4
+#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2
+#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8
+#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3
+#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10
+#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4
+#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1
+#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
+#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2
+#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1
+#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4
+#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2
+#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8
+#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3
+#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10
+#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK 0x1
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT 0x0
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK 0x2
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT 0x1
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK 0x4
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT 0x2
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK 0x8
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT 0x3
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK 0x10
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT 0x4
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK 0x20
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT 0x5
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK 0x40
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT 0x6
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK 0x80
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT 0x7
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK 0x100
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT 0x8
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK 0x200
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT 0x9
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK 0x400
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT 0xa
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK 0x800
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT 0xb
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK 0x1000
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT 0xc
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK 0x2000
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT 0xd
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK 0x4000
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT 0xe
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK 0x8000
+#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT 0xf
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK 0x1
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT 0x0
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK 0x2
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT 0x1
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK 0x4
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT 0x2
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK 0x8
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT 0x3
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK 0x10
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT 0x4
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK 0x20
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT 0x5
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK 0x40
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT 0x6
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK 0x80
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT 0x7
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK 0x100
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT 0x8
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK 0x200
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT 0x9
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK 0x400
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT 0xa
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK 0x800
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT 0xb
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK 0x1000
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT 0xc
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK 0x2000
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT 0xd
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK 0x4000
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT 0xe
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK 0x8000
+#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT 0xf
+#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x1
+#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x0
+#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x2
+#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x1
+#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x4
+#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x2
+#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK 0x8
+#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x3
+#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x10
+#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x4
+#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x20
+#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x5
+#define VM_PRT_CNTL__MASK_PDE0_FAULT_MASK 0x40
+#define VM_PRT_CNTL__MASK_PDE0_FAULT__SHIFT 0x6
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x1
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x2
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x4
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x8
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x10
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x20
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x40
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x80
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x100
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x200
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x400
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x800
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x1000
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x2000
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x4000
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x8000
+#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000
+#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000
+#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d
+#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff
+#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0
+#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff
+#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0
+#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
+#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
+#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
+#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
+#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff
+#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0
+#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff
+#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK 0x1ff
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT 0x0
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK 0x3fe00
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT 0x9
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MSB_MASK 0x40000
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MSB__SHIFT 0x12
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MASK_MSB_MASK 0x80000
+#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MASK_MSB__SHIFT 0x13
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_DEBUG__FLAGS_MASK 0xffffffff
+#define VM_DEBUG__FLAGS__SHIFT 0x0
+#define VM_L2_CG__OFFDLY_MASK 0xfc0
+#define VM_L2_CG__OFFDLY__SHIFT 0x6
+#define VM_L2_CG__ENABLE_MASK 0x40000
+#define VM_L2_CG__ENABLE__SHIFT 0x12
+#define VM_L2_CG__MEM_LS_ENABLE_MASK 0x80000
+#define VM_L2_CG__MEM_LS_ENABLE__SHIFT 0x13
+#define VM_L2_CG__OVERRIDE_MASK 0x100000
+#define VM_L2_CG__OVERRIDE__SHIFT 0x14
+#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK 0xfffffff
+#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT 0x0
+#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK 0x7f
+#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
+#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK 0xfffffff
+#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT 0x0
+#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x3f
+#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK 0x40
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT 0x6
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK 0x80
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT 0x7
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK 0x100
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT 0x8
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK 0x200
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT 0x9
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK 0x400
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT 0xa
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK 0x800
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT 0xb
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK 0x1000
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT 0xc
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK 0x2000
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT 0xd
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK 0x4000
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT 0xe
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK 0x8000
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT 0xf
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK 0x10000
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT 0x10
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK 0x20000
+#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT 0x11
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x1ff
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x7fc00
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
+#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x100000
+#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x1000000
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x2000000
+#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0xffff
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xffff0000
+#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10
+#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xffffffff
+#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0
+#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xffffffff
+#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0
+#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x800000
+#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17
+#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x8
+#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3
+#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xff800000
+#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17
+#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x1
+#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0
+#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xff800000
+#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17
+#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0xff
+#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0
+#define MC_VM_NB_TOP_OF_DRAM3__TOM3_LIMIT_MASK 0x3fffffff
+#define MC_VM_NB_TOP_OF_DRAM3__TOM3_LIMIT__SHIFT 0x0
+#define MC_VM_NB_TOP_OF_DRAM3__TOM3_ENABLE_MASK 0x80000000
+#define MC_VM_NB_TOP_OF_DRAM3__TOM3_ENABLE__SHIFT 0x1f
+#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xfffff000
+#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc
+#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xfffff000
+#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc
+#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xfffff000
+#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc
+#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xfffff000
+#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc
+#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0xfffff
+#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0
+#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0xfffff
+#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0
+#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0xfffff
+#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0
+#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0xfffff
+#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x1
+#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x2
+#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xfffff000
+#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc
+#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x1
+#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x2
+#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xfffff000
+#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc
+#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x1
+#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x2
+#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xfffff000
+#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc
+#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x1
+#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0
+#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x2
+#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1
+#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xfffff000
+#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc
+#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0xfffff
+#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0
+#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0xfffff
+#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0
+#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0xfffff
+#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0
+#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0xfffff
+#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0
+#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xfffff000
+#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc
+#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xfffff000
+#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc
+#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xfffff000
+#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc
+#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xfffff000
+#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc
+#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0xfffff
+#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0
+#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0xfffff
+#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0
+#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0xfffff
+#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0
+#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0xfffff
+#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0
+#define MC_VM_MARC_CNTL__ENABLE_ALL_CLIENTS_MASK 0x1
+#define MC_VM_MARC_CNTL__ENABLE_ALL_CLIENTS__SHIFT 0x0
+#define MC_ARB_HARSH_EN_RD__TX_PRI_MASK 0xff
+#define MC_ARB_HARSH_EN_RD__TX_PRI__SHIFT 0x0
+#define MC_ARB_HARSH_EN_RD__BW_PRI_MASK 0xff00
+#define MC_ARB_HARSH_EN_RD__BW_PRI__SHIFT 0x8
+#define MC_ARB_HARSH_EN_RD__FIX_PRI_MASK 0xff0000
+#define MC_ARB_HARSH_EN_RD__FIX_PRI__SHIFT 0x10
+#define MC_ARB_HARSH_EN_RD__ST_PRI_MASK 0xff000000
+#define MC_ARB_HARSH_EN_RD__ST_PRI__SHIFT 0x18
+#define MC_ARB_HARSH_EN_WR__TX_PRI_MASK 0xff
+#define MC_ARB_HARSH_EN_WR__TX_PRI__SHIFT 0x0
+#define MC_ARB_HARSH_EN_WR__BW_PRI_MASK 0xff00
+#define MC_ARB_HARSH_EN_WR__BW_PRI__SHIFT 0x8
+#define MC_ARB_HARSH_EN_WR__FIX_PRI_MASK 0xff0000
+#define MC_ARB_HARSH_EN_WR__FIX_PRI__SHIFT 0x10
+#define MC_ARB_HARSH_EN_WR__ST_PRI_MASK 0xff000000
+#define MC_ARB_HARSH_EN_WR__ST_PRI__SHIFT 0x18
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_TX_HI0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_TX_HI0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_TX_HI1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_TX_HI1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_TX_LO0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_TX_LO0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_TX_LO1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_TX_LO1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_BWCNT0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_BWCNT0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_BWCNT1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_BWCNT1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_SAT0_RD__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_SAT0_RD__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_SAT0_RD__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_SAT0_RD__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_SAT0_RD__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_SAT0_RD__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_SAT0_RD__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_SAT0_RD__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_SAT0_WR__GROUP0_MASK 0xff
+#define MC_ARB_HARSH_SAT0_WR__GROUP0__SHIFT 0x0
+#define MC_ARB_HARSH_SAT0_WR__GROUP1_MASK 0xff00
+#define MC_ARB_HARSH_SAT0_WR__GROUP1__SHIFT 0x8
+#define MC_ARB_HARSH_SAT0_WR__GROUP2_MASK 0xff0000
+#define MC_ARB_HARSH_SAT0_WR__GROUP2__SHIFT 0x10
+#define MC_ARB_HARSH_SAT0_WR__GROUP3_MASK 0xff000000
+#define MC_ARB_HARSH_SAT0_WR__GROUP3__SHIFT 0x18
+#define MC_ARB_HARSH_SAT1_RD__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_SAT1_RD__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_SAT1_RD__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_SAT1_RD__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_SAT1_RD__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_SAT1_RD__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_SAT1_RD__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_SAT1_RD__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_SAT1_WR__GROUP4_MASK 0xff
+#define MC_ARB_HARSH_SAT1_WR__GROUP4__SHIFT 0x0
+#define MC_ARB_HARSH_SAT1_WR__GROUP5_MASK 0xff00
+#define MC_ARB_HARSH_SAT1_WR__GROUP5__SHIFT 0x8
+#define MC_ARB_HARSH_SAT1_WR__GROUP6_MASK 0xff0000
+#define MC_ARB_HARSH_SAT1_WR__GROUP6__SHIFT 0x10
+#define MC_ARB_HARSH_SAT1_WR__GROUP7_MASK 0xff000000
+#define MC_ARB_HARSH_SAT1_WR__GROUP7__SHIFT 0x18
+#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST_MASK 0xff
+#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST__SHIFT 0x0
+#define MC_ARB_HARSH_CTL_RD__HARSH_RR_MASK 0x100
+#define MC_ARB_HARSH_CTL_RD__HARSH_RR__SHIFT 0x8
+#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY_MASK 0x200
+#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY__SHIFT 0x9
+#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH_MASK 0x400
+#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH__SHIFT 0xa
+#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP_MASK 0x800
+#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP__SHIFT 0xb
+#define MC_ARB_HARSH_CTL_RD__ST_MODE_MASK 0x3000
+#define MC_ARB_HARSH_CTL_RD__ST_MODE__SHIFT 0xc
+#define MC_ARB_HARSH_CTL_RD__FORCE_STALL_MASK 0x3fc000
+#define MC_ARB_HARSH_CTL_RD__FORCE_STALL__SHIFT 0xe
+#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL_MASK 0x1c00000
+#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL__SHIFT 0x16
+#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST_MASK 0xff
+#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST__SHIFT 0x0
+#define MC_ARB_HARSH_CTL_WR__HARSH_RR_MASK 0x100
+#define MC_ARB_HARSH_CTL_WR__HARSH_RR__SHIFT 0x8
+#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY_MASK 0x200
+#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY__SHIFT 0x9
+#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH_MASK 0x400
+#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH__SHIFT 0xa
+#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP_MASK 0x800
+#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP__SHIFT 0xb
+#define MC_ARB_HARSH_CTL_WR__ST_MODE_MASK 0x3000
+#define MC_ARB_HARSH_CTL_WR__ST_MODE__SHIFT 0xc
+#define MC_ARB_HARSH_CTL_WR__FORCE_STALL_MASK 0x3fc000
+#define MC_ARB_HARSH_CTL_WR__FORCE_STALL__SHIFT 0xe
+#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL_MASK 0x1c00000
+#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL__SHIFT 0x16
+#define MC_ARB_GRUB_PRIORITY1_RD__CB0_MASK 0x3
+#define MC_ARB_GRUB_PRIORITY1_RD__CB0__SHIFT 0x0
+#define MC_ARB_GRUB_PRIORITY1_RD__CBCMASK0_MASK 0xc
+#define MC_ARB_GRUB_PRIORITY1_RD__CBCMASK0__SHIFT 0x2
+#define MC_ARB_GRUB_PRIORITY1_RD__CBFMASK0_MASK 0x30
+#define MC_ARB_GRUB_PRIORITY1_RD__CBFMASK0__SHIFT 0x4
+#define MC_ARB_GRUB_PRIORITY1_RD__DB0_MASK 0xc0
+#define MC_ARB_GRUB_PRIORITY1_RD__DB0__SHIFT 0x6
+#define MC_ARB_GRUB_PRIORITY1_RD__DBHTILE0_MASK 0x300
+#define MC_ARB_GRUB_PRIORITY1_RD__DBHTILE0__SHIFT 0x8
+#define MC_ARB_GRUB_PRIORITY1_RD__DBSTEN0_MASK 0xc00
+#define MC_ARB_GRUB_PRIORITY1_RD__DBSTEN0__SHIFT 0xa
+#define MC_ARB_GRUB_PRIORITY1_RD__TC0_MASK 0x3000
+#define MC_ARB_GRUB_PRIORITY1_RD__TC0__SHIFT 0xc
+#define MC_ARB_GRUB_PRIORITY1_RD__ACPG_MASK 0xc000
+#define MC_ARB_GRUB_PRIORITY1_RD__ACPG__SHIFT 0xe
+#define MC_ARB_GRUB_PRIORITY1_RD__ACPO_MASK 0x30000
+#define MC_ARB_GRUB_PRIORITY1_RD__ACPO__SHIFT 0x10
+#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_MASK 0xc0000
+#define MC_ARB_GRUB_PRIORITY1_RD__DMIF__SHIFT 0x12
+#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT0_MASK 0x300000
+#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT0__SHIFT 0x14
+#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT1_MASK 0xc00000
+#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT1__SHIFT 0x16
+#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_TW_MASK 0x3000000
+#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_TW__SHIFT 0x18
+#define MC_ARB_GRUB_PRIORITY1_RD__MCIF_MASK 0xc000000
+#define MC_ARB_GRUB_PRIORITY1_RD__MCIF__SHIFT 0x1a
+#define MC_ARB_GRUB_PRIORITY1_RD__RLC_MASK 0x30000000
+#define MC_ARB_GRUB_PRIORITY1_RD__RLC__SHIFT 0x1c
+#define MC_ARB_GRUB_PRIORITY1_RD__VMC_MASK 0xc0000000
+#define MC_ARB_GRUB_PRIORITY1_RD__VMC__SHIFT 0x1e
+#define MC_ARB_GRUB_PRIORITY1_WR__CB0_MASK 0x3
+#define MC_ARB_GRUB_PRIORITY1_WR__CB0__SHIFT 0x0
+#define MC_ARB_GRUB_PRIORITY1_WR__CBCMASK0_MASK 0xc
+#define MC_ARB_GRUB_PRIORITY1_WR__CBCMASK0__SHIFT 0x2
+#define MC_ARB_GRUB_PRIORITY1_WR__CBFMASK0_MASK 0x30
+#define MC_ARB_GRUB_PRIORITY1_WR__CBFMASK0__SHIFT 0x4
+#define MC_ARB_GRUB_PRIORITY1_WR__CBIMMED0_MASK 0xc0
+#define MC_ARB_GRUB_PRIORITY1_WR__CBIMMED0__SHIFT 0x6
+#define MC_ARB_GRUB_PRIORITY1_WR__DB0_MASK 0x300
+#define MC_ARB_GRUB_PRIORITY1_WR__DB0__SHIFT 0x8
+#define MC_ARB_GRUB_PRIORITY1_WR__DBHTILE0_MASK 0xc00
+#define MC_ARB_GRUB_PRIORITY1_WR__DBHTILE0__SHIFT 0xa
+#define MC_ARB_GRUB_PRIORITY1_WR__DBSTEN0_MASK 0x3000
+#define MC_ARB_GRUB_PRIORITY1_WR__DBSTEN0__SHIFT 0xc
+#define MC_ARB_GRUB_PRIORITY1_WR__TC0_MASK 0xc000
+#define MC_ARB_GRUB_PRIORITY1_WR__TC0__SHIFT 0xe
+#define MC_ARB_GRUB_PRIORITY1_WR__SH_MASK 0x30000
+#define MC_ARB_GRUB_PRIORITY1_WR__SH__SHIFT 0x10
+#define MC_ARB_GRUB_PRIORITY1_WR__ACPG_MASK 0xc0000
+#define MC_ARB_GRUB_PRIORITY1_WR__ACPG__SHIFT 0x12
+#define MC_ARB_GRUB_PRIORITY1_WR__ACPO_MASK 0x300000
+#define MC_ARB_GRUB_PRIORITY1_WR__ACPO__SHIFT 0x14
+#define MC_ARB_GRUB_PRIORITY1_WR__MCIF_MASK 0xc00000
+#define MC_ARB_GRUB_PRIORITY1_WR__MCIF__SHIFT 0x16
+#define MC_ARB_GRUB_PRIORITY1_WR__RLC_MASK 0x3000000
+#define MC_ARB_GRUB_PRIORITY1_WR__RLC__SHIFT 0x18
+#define MC_ARB_GRUB_PRIORITY1_WR__SDMA1_MASK 0xc000000
+#define MC_ARB_GRUB_PRIORITY1_WR__SDMA1__SHIFT 0x1a
+#define MC_ARB_GRUB_PRIORITY1_WR__SMU_MASK 0x30000000
+#define MC_ARB_GRUB_PRIORITY1_WR__SMU__SHIFT 0x1c
+#define MC_ARB_GRUB_PRIORITY1_WR__VCE0_MASK 0xc0000000
+#define MC_ARB_GRUB_PRIORITY1_WR__VCE0__SHIFT 0x1e
+#define MC_ARB_GRUB_PRIORITY2_RD__SDMA1_MASK 0x3
+#define MC_ARB_GRUB_PRIORITY2_RD__SDMA1__SHIFT 0x0
+#define MC_ARB_GRUB_PRIORITY2_RD__SMU_MASK 0xc
+#define MC_ARB_GRUB_PRIORITY2_RD__SMU__SHIFT 0x2
+#define MC_ARB_GRUB_PRIORITY2_RD__VCE0_MASK 0x30
+#define MC_ARB_GRUB_PRIORITY2_RD__VCE0__SHIFT 0x4
+#define MC_ARB_GRUB_PRIORITY2_RD__VCE1_MASK 0xc0
+#define MC_ARB_GRUB_PRIORITY2_RD__VCE1__SHIFT 0x6
+#define MC_ARB_GRUB_PRIORITY2_RD__XDMAM_MASK 0x300
+#define MC_ARB_GRUB_PRIORITY2_RD__XDMAM__SHIFT 0x8
+#define MC_ARB_GRUB_PRIORITY2_RD__SDMA0_MASK 0xc00
+#define MC_ARB_GRUB_PRIORITY2_RD__SDMA0__SHIFT 0xa
+#define MC_ARB_GRUB_PRIORITY2_RD__HDP_MASK 0x3000
+#define MC_ARB_GRUB_PRIORITY2_RD__HDP__SHIFT 0xc
+#define MC_ARB_GRUB_PRIORITY2_RD__UMC_MASK 0xc000
+#define MC_ARB_GRUB_PRIORITY2_RD__UMC__SHIFT 0xe
+#define MC_ARB_GRUB_PRIORITY2_RD__UVD_MASK 0x30000
+#define MC_ARB_GRUB_PRIORITY2_RD__UVD__SHIFT 0x10
+#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT0_MASK 0xc0000
+#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT0__SHIFT 0x12
+#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT1_MASK 0x300000
+#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT1__SHIFT 0x14
+#define MC_ARB_GRUB_PRIORITY2_RD__SEM_MASK 0xc00000
+#define MC_ARB_GRUB_PRIORITY2_RD__SEM__SHIFT 0x16
+#define MC_ARB_GRUB_PRIORITY2_RD__SAMMSP_MASK 0x3000000
+#define MC_ARB_GRUB_PRIORITY2_RD__SAMMSP__SHIFT 0x18
+#define MC_ARB_GRUB_PRIORITY2_RD__VP8_MASK 0xc000000
+#define MC_ARB_GRUB_PRIORITY2_RD__VP8__SHIFT 0x1a
+#define MC_ARB_GRUB_PRIORITY2_RD__ISP_MASK 0x30000000
+#define MC_ARB_GRUB_PRIORITY2_RD__ISP__SHIFT 0x1c
+#define MC_ARB_GRUB_PRIORITY2_RD__RSV2_MASK 0xc0000000
+#define MC_ARB_GRUB_PRIORITY2_RD__RSV2__SHIFT 0x1e
+#define MC_ARB_GRUB_PRIORITY2_WR__VCE1_MASK 0x3
+#define MC_ARB_GRUB_PRIORITY2_WR__VCE1__SHIFT 0x0
+#define MC_ARB_GRUB_PRIORITY2_WR__SAMMSP_MASK 0xc
+#define MC_ARB_GRUB_PRIORITY2_WR__SAMMSP__SHIFT 0x2
+#define MC_ARB_GRUB_PRIORITY2_WR__XDMA_MASK 0x30
+#define MC_ARB_GRUB_PRIORITY2_WR__XDMA__SHIFT 0x4
+#define MC_ARB_GRUB_PRIORITY2_WR__XDMAM_MASK 0xc0
+#define MC_ARB_GRUB_PRIORITY2_WR__XDMAM__SHIFT 0x6
+#define MC_ARB_GRUB_PRIORITY2_WR__SDMA0_MASK 0x300
+#define MC_ARB_GRUB_PRIORITY2_WR__SDMA0__SHIFT 0x8
+#define MC_ARB_GRUB_PRIORITY2_WR__HDP_MASK 0xc00
+#define MC_ARB_GRUB_PRIORITY2_WR__HDP__SHIFT 0xa
+#define MC_ARB_GRUB_PRIORITY2_WR__UMC_MASK 0x3000
+#define MC_ARB_GRUB_PRIORITY2_WR__UMC__SHIFT 0xc
+#define MC_ARB_GRUB_PRIORITY2_WR__UVD_MASK 0xc000
+#define MC_ARB_GRUB_PRIORITY2_WR__UVD__SHIFT 0xe
+#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT0_MASK 0x30000
+#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT0__SHIFT 0x10
+#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT1_MASK 0xc0000
+#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT1__SHIFT 0x12
+#define MC_ARB_GRUB_PRIORITY2_WR__XDP_MASK 0x300000
+#define MC_ARB_GRUB_PRIORITY2_WR__XDP__SHIFT 0x14
+#define MC_ARB_GRUB_PRIORITY2_WR__SEM_MASK 0xc00000
+#define MC_ARB_GRUB_PRIORITY2_WR__SEM__SHIFT 0x16
+#define MC_ARB_GRUB_PRIORITY2_WR__IH_MASK 0x3000000
+#define MC_ARB_GRUB_PRIORITY2_WR__IH__SHIFT 0x18
+#define MC_ARB_GRUB_PRIORITY2_WR__VP8_MASK 0xc000000
+#define MC_ARB_GRUB_PRIORITY2_WR__VP8__SHIFT 0x1a
+#define MC_ARB_GRUB_PRIORITY2_WR__ISP_MASK 0x30000000
+#define MC_ARB_GRUB_PRIORITY2_WR__ISP__SHIFT 0x1c
+#define MC_ARB_GRUB_PRIORITY2_WR__VIN0_MASK 0xc0000000
+#define MC_ARB_GRUB_PRIORITY2_WR__VIN0__SHIFT 0x1e
+#define MC_FUS_DRAM0_CS0_BASE__CSENABLE_MASK 0x1
+#define MC_FUS_DRAM0_CS0_BASE__CSENABLE__SHIFT 0x0
+#define MC_FUS_DRAM0_CS0_BASE__BASEADDR21_11_MASK 0xffe0
+#define MC_FUS_DRAM0_CS0_BASE__BASEADDR21_11__SHIFT 0x5
+#define MC_FUS_DRAM0_CS0_BASE__BASEADDR38_27_MASK 0x7ff80000
+#define MC_FUS_DRAM0_CS0_BASE__BASEADDR38_27__SHIFT 0x13
+#define MC_FUS_DRAM1_CS0_BASE__CSENABLE_MASK 0x1
+#define MC_FUS_DRAM1_CS0_BASE__CSENABLE__SHIFT 0x0
+#define MC_FUS_DRAM1_CS0_BASE__BASEADDR21_11_MASK 0xffe0
+#define MC_FUS_DRAM1_CS0_BASE__BASEADDR21_11__SHIFT 0x5
+#define MC_FUS_DRAM1_CS0_BASE__BASEADDR38_27_MASK 0x7ff80000
+#define MC_FUS_DRAM1_CS0_BASE__BASEADDR38_27__SHIFT 0x13
+#define MC_FUS_DRAM0_CS1_BASE__CSENABLE_MASK 0x1
+#define MC_FUS_DRAM0_CS1_BASE__CSENABLE__SHIFT 0x0
+#define MC_FUS_DRAM0_CS1_BASE__BASEADDR21_11_MASK 0xffe0
+#define MC_FUS_DRAM0_CS1_BASE__BASEADDR21_11__SHIFT 0x5
+#define MC_FUS_DRAM0_CS1_BASE__BASEADDR38_27_MASK 0x7ff80000
+#define MC_FUS_DRAM0_CS1_BASE__BASEADDR38_27__SHIFT 0x13
+#define MC_FUS_DRAM1_CS1_BASE__CSENABLE_MASK 0x1
+#define MC_FUS_DRAM1_CS1_BASE__CSENABLE__SHIFT 0x0
+#define MC_FUS_DRAM1_CS1_BASE__BASEADDR21_11_MASK 0xffe0
+#define MC_FUS_DRAM1_CS1_BASE__BASEADDR21_11__SHIFT 0x5
+#define MC_FUS_DRAM1_CS1_BASE__BASEADDR38_27_MASK 0x7ff80000
+#define MC_FUS_DRAM1_CS1_BASE__BASEADDR38_27__SHIFT 0x13
+#define MC_FUS_DRAM0_CS2_BASE__CSENABLE_MASK 0x1
+#define MC_FUS_DRAM0_CS2_BASE__CSENABLE__SHIFT 0x0
+#define MC_FUS_DRAM0_CS2_BASE__BASEADDR21_11_MASK 0xffe0
+#define MC_FUS_DRAM0_CS2_BASE__BASEADDR21_11__SHIFT 0x5
+#define MC_FUS_DRAM0_CS2_BASE__BASEADDR38_27_MASK 0x7ff80000
+#define MC_FUS_DRAM0_CS2_BASE__BASEADDR38_27__SHIFT 0x13
+#define MC_FUS_DRAM1_CS2_BASE__CSENABLE_MASK 0x1
+#define MC_FUS_DRAM1_CS2_BASE__CSENABLE__SHIFT 0x0
+#define MC_FUS_DRAM1_CS2_BASE__BASEADDR21_11_MASK 0xffe0
+#define MC_FUS_DRAM1_CS2_BASE__BASEADDR21_11__SHIFT 0x5
+#define MC_FUS_DRAM1_CS2_BASE__BASEADDR38_27_MASK 0x7ff80000
+#define MC_FUS_DRAM1_CS2_BASE__BASEADDR38_27__SHIFT 0x13
+#define MC_FUS_DRAM0_CS3_BASE__CSENABLE_MASK 0x1
+#define MC_FUS_DRAM0_CS3_BASE__CSENABLE__SHIFT 0x0
+#define MC_FUS_DRAM0_CS3_BASE__BASEADDR21_11_MASK 0xffe0
+#define MC_FUS_DRAM0_CS3_BASE__BASEADDR21_11__SHIFT 0x5
+#define MC_FUS_DRAM0_CS3_BASE__BASEADDR38_27_MASK 0x7ff80000
+#define MC_FUS_DRAM0_CS3_BASE__BASEADDR38_27__SHIFT 0x13
+#define MC_FUS_DRAM1_CS3_BASE__CSENABLE_MASK 0x1
+#define MC_FUS_DRAM1_CS3_BASE__CSENABLE__SHIFT 0x0
+#define MC_FUS_DRAM1_CS3_BASE__BASEADDR21_11_MASK 0xffe0
+#define MC_FUS_DRAM1_CS3_BASE__BASEADDR21_11__SHIFT 0x5
+#define MC_FUS_DRAM1_CS3_BASE__BASEADDR38_27_MASK 0x7ff80000
+#define MC_FUS_DRAM1_CS3_BASE__BASEADDR38_27__SHIFT 0x13
+#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM0ADDRMAP_MASK 0xf
+#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM0ADDRMAP__SHIFT 0x0
+#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM1ADDRMAP_MASK 0xf0
+#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM1ADDRMAP__SHIFT 0x4
+#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWIZZLEMODE_MASK 0x100
+#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWIZZLEMODE__SHIFT 0x8
+#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWAP_MASK 0x200
+#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWAP__SHIFT 0x9
+#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM0ADDRMAP_MASK 0xf
+#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM0ADDRMAP__SHIFT 0x0
+#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM1ADDRMAP_MASK 0xf0
+#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM1ADDRMAP__SHIFT 0x4
+#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWIZZLEMODE_MASK 0x100
+#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWIZZLEMODE__SHIFT 0x8
+#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWAP_MASK 0x200
+#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWAP__SHIFT 0x9
+#define MC_FUS_DRAM0_CTL_BASE__DCTSEL_MASK 0x7
+#define MC_FUS_DRAM0_CTL_BASE__DCTSEL__SHIFT 0x0
+#define MC_FUS_DRAM0_CTL_BASE__DCTINTLVEN_MASK 0x78
+#define MC_FUS_DRAM0_CTL_BASE__DCTINTLVEN__SHIFT 0x3
+#define MC_FUS_DRAM0_CTL_BASE__DCTBASEADDR_MASK 0xfffff80
+#define MC_FUS_DRAM0_CTL_BASE__DCTBASEADDR__SHIFT 0x7
+#define MC_FUS_DRAM0_CTL_BASE__DCTOFFSETEN_MASK 0x10000000
+#define MC_FUS_DRAM0_CTL_BASE__DCTOFFSETEN__SHIFT 0x1c
+#define MC_FUS_DRAM1_CTL_BASE__DCTSEL_MASK 0x7
+#define MC_FUS_DRAM1_CTL_BASE__DCTSEL__SHIFT 0x0
+#define MC_FUS_DRAM1_CTL_BASE__DCTINTLVEN_MASK 0x78
+#define MC_FUS_DRAM1_CTL_BASE__DCTINTLVEN__SHIFT 0x3
+#define MC_FUS_DRAM1_CTL_BASE__DCTBASEADDR_MASK 0xfffff80
+#define MC_FUS_DRAM1_CTL_BASE__DCTBASEADDR__SHIFT 0x7
+#define MC_FUS_DRAM1_CTL_BASE__DCTOFFSETEN_MASK 0x10000000
+#define MC_FUS_DRAM1_CTL_BASE__DCTOFFSETEN__SHIFT 0x1c
+#define MC_FUS_DRAM0_CTL_LIMIT__DCTLIMITADDR_MASK 0x1fffff
+#define MC_FUS_DRAM0_CTL_LIMIT__DCTLIMITADDR__SHIFT 0x0
+#define MC_FUS_DRAM0_CTL_LIMIT__DRAMHOLEVALID_MASK 0x200000
+#define MC_FUS_DRAM0_CTL_LIMIT__DRAMHOLEVALID__SHIFT 0x15
+#define MC_FUS_DRAM1_CTL_LIMIT__DCTLIMITADDR_MASK 0x1fffff
+#define MC_FUS_DRAM1_CTL_LIMIT__DCTLIMITADDR__SHIFT 0x0
+#define MC_FUS_DRAM1_CTL_LIMIT__DRAMHOLEVALID_MASK 0x200000
+#define MC_FUS_DRAM1_CTL_LIMIT__DRAMHOLEVALID__SHIFT 0x15
+#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF0_MASK 0xfff
+#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF0__SHIFT 0x0
+#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF1_MASK 0xfff000
+#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF1__SHIFT 0xc
+#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF2_MASK 0xfff
+#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF2__SHIFT 0x0
+#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF3_MASK 0xfff000
+#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF3__SHIFT 0xc
+#define MC_FUS_DRAM_MODE__DCTSELINTLVADDR_MASK 0x7
+#define MC_FUS_DRAM_MODE__DCTSELINTLVADDR__SHIFT 0x0
+#define MC_FUS_DRAM_MODE__DRAMTYPE_MASK 0x38
+#define MC_FUS_DRAM_MODE__DRAMTYPE__SHIFT 0x3
+#define MC_FUS_DRAM_MODE__DRAMHOLEOFFSET_MASK 0x7fc0
+#define MC_FUS_DRAM_MODE__DRAMHOLEOFFSET__SHIFT 0x6
+#define MC_FUS_DRAM_MODE__DDR3LPX32_MASK 0x8000
+#define MC_FUS_DRAM_MODE__DDR3LPX32__SHIFT 0xf
+#define MC_FUS_DRAM_MODE__BANKGROUPSWAP_MASK 0x10000
+#define MC_FUS_DRAM_MODE__BANKGROUPSWAP__SHIFT 0x10
+#define MC_FUS_DRAM_APER_BASE__BASE_MASK 0xfffff
+#define MC_FUS_DRAM_APER_BASE__BASE__SHIFT 0x0
+#define MC_FUS_DRAM_APER_TOP__TOP_MASK 0xfffff
+#define MC_FUS_DRAM_APER_TOP__TOP__SHIFT 0x0
+#define MC_FUS_DRAM_APER_DEF__DEF_MASK 0xfffffff
+#define MC_FUS_DRAM_APER_DEF__DEF__SHIFT 0x0
+#define MC_FUS_DRAM_APER_DEF__LOCK_MC_FUS_DRAM_REGS_MASK 0x10000000
+#define MC_FUS_DRAM_APER_DEF__LOCK_MC_FUS_DRAM_REGS__SHIFT 0x1c
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_TOKURG_EN_MASK 0x1
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_TOKURG_EN__SHIFT 0x0
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_TOKURG_EN_MASK 0x2
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_TOKURG_EN__SHIFT 0x1
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_TOKURG_EN_MASK 0x4
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_TOKURG_EN__SHIFT 0x2
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_TOKURG_EN_MASK 0x8
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_TOKURG_EN__SHIFT 0x3
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_PRIURG_EN_MASK 0x10
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_PRIURG_EN__SHIFT 0x4
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_PRIURG_EN_MASK 0x20
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_PRIURG_EN__SHIFT 0x5
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_PRIURG_EN_MASK 0x40
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_PRIURG_EN__SHIFT 0x6
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_PRIURG_EN_MASK 0x80
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_PRIURG_EN__SHIFT 0x7
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_ISOC_EN_MASK 0x100
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_ISOC_EN__SHIFT 0x8
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_ISOC_EN_MASK 0x200
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_ISOC_EN__SHIFT 0x9
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_ISOC_EN_MASK 0x400
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_ISOC_EN__SHIFT 0xa
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__MCIF_RD_ISOC_EN_MASK 0x800
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__MCIF_RD_ISOC_EN__SHIFT 0xb
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__UMC_RD_ISOC_EN_MASK 0x1000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__UMC_RD_ISOC_EN__SHIFT 0xc
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCEU_RD_ISOC_EN_MASK 0x2000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCEU_RD_ISOC_EN__SHIFT 0xd
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_ISOC_EN_MASK 0x4000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_ISOC_EN__SHIFT 0xe
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_EN_MASK 0x8000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_EN__SHIFT 0xf
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_VAL_MASK 0x30000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_VAL__SHIFT 0x10
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_EN_MASK 0x40000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_EN__SHIFT 0x12
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_EN_MASK 0x80000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_EN__SHIFT 0x13
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_EN_MASK 0x100000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_EN__SHIFT 0x14
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_VAL_MASK 0x200000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_VAL__SHIFT 0x15
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_VAL_MASK 0x400000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_VAL__SHIFT 0x16
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_VAL_MASK 0x800000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_VAL__SHIFT 0x17
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__GARLIC_REQ_CREDITS_MASK 0x1f000000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__GARLIC_REQ_CREDITS__SHIFT 0x18
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__MM_REL_LATE_MASK 0x20000000
+#define MC_FUS_ARB_GARLIC_ISOC_PRI__MM_REL_LATE__SHIFT 0x1d
+#define MC_FUS_ARB_GARLIC_CNTL__RX_RDRESP_FIFO_PTR_INIT_VALUE_MASK 0xff
+#define MC_FUS_ARB_GARLIC_CNTL__RX_RDRESP_FIFO_PTR_INIT_VALUE__SHIFT 0x0
+#define MC_FUS_ARB_GARLIC_CNTL__RX_WRRESP_FIFO_PTR_INIT_VALUE_MASK 0x7f00
+#define MC_FUS_ARB_GARLIC_CNTL__RX_WRRESP_FIFO_PTR_INIT_VALUE__SHIFT 0x8
+#define MC_FUS_ARB_GARLIC_CNTL__EN_64_BYTE_WRITE_MASK 0x8000
+#define MC_FUS_ARB_GARLIC_CNTL__EN_64_BYTE_WRITE__SHIFT 0xf
+#define MC_FUS_ARB_GARLIC_CNTL__EDC_RESPONSE_ENABLE_MASK 0x10000
+#define MC_FUS_ARB_GARLIC_CNTL__EDC_RESPONSE_ENABLE__SHIFT 0x10
+#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_RDRESP_LIMIT_MASK 0x3fe0000
+#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_RDRESP_LIMIT__SHIFT 0x11
+#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_WRRESP_LIMIT_MASK 0xfc000000
+#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_WRRESP_LIMIT__SHIFT 0x1a
+#define MC_FUS_ARB_GARLIC_WR_PRI__CB_WR_PRI_MASK 0x3
+#define MC_FUS_ARB_GARLIC_WR_PRI__CB_WR_PRI__SHIFT 0x0
+#define MC_FUS_ARB_GARLIC_WR_PRI__DB_WR_PRI_MASK 0xc
+#define MC_FUS_ARB_GARLIC_WR_PRI__DB_WR_PRI__SHIFT 0x2
+#define MC_FUS_ARB_GARLIC_WR_PRI__TC_WR_PRI_MASK 0x30
+#define MC_FUS_ARB_GARLIC_WR_PRI__TC_WR_PRI__SHIFT 0x4
+#define MC_FUS_ARB_GARLIC_WR_PRI__CP_WR_PRI_MASK 0xc0
+#define MC_FUS_ARB_GARLIC_WR_PRI__CP_WR_PRI__SHIFT 0x6
+#define MC_FUS_ARB_GARLIC_WR_PRI__HDP_WR_PRI_MASK 0x300
+#define MC_FUS_ARB_GARLIC_WR_PRI__HDP_WR_PRI__SHIFT 0x8
+#define MC_FUS_ARB_GARLIC_WR_PRI__XDP_WR_PRI_MASK 0xc00
+#define MC_FUS_ARB_GARLIC_WR_PRI__XDP_WR_PRI__SHIFT 0xa
+#define MC_FUS_ARB_GARLIC_WR_PRI__UMC_WR_PRI_MASK 0x3000
+#define MC_FUS_ARB_GARLIC_WR_PRI__UMC_WR_PRI__SHIFT 0xc
+#define MC_FUS_ARB_GARLIC_WR_PRI__UVD_WR_PRI_MASK 0xc000
+#define MC_FUS_ARB_GARLIC_WR_PRI__UVD_WR_PRI__SHIFT 0xe
+#define MC_FUS_ARB_GARLIC_WR_PRI__RLC_WR_PRI_MASK 0x30000
+#define MC_FUS_ARB_GARLIC_WR_PRI__RLC_WR_PRI__SHIFT 0x10
+#define MC_FUS_ARB_GARLIC_WR_PRI__IH_WR_PRI_MASK 0xc0000
+#define MC_FUS_ARB_GARLIC_WR_PRI__IH_WR_PRI__SHIFT 0x12
+#define MC_FUS_ARB_GARLIC_WR_PRI__SDMA_WR_PRI_MASK 0x300000
+#define MC_FUS_ARB_GARLIC_WR_PRI__SDMA_WR_PRI__SHIFT 0x14
+#define MC_FUS_ARB_GARLIC_WR_PRI__SEM_WR_PRI_MASK 0xc00000
+#define MC_FUS_ARB_GARLIC_WR_PRI__SEM_WR_PRI__SHIFT 0x16
+#define MC_FUS_ARB_GARLIC_WR_PRI__SH_WR_PRI_MASK 0x3000000
+#define MC_FUS_ARB_GARLIC_WR_PRI__SH_WR_PRI__SHIFT 0x18
+#define MC_FUS_ARB_GARLIC_WR_PRI__MCIF_WR_PRI_MASK 0xc000000
+#define MC_FUS_ARB_GARLIC_WR_PRI__MCIF_WR_PRI__SHIFT 0x1a
+#define MC_FUS_ARB_GARLIC_WR_PRI__VCE_WR_PRI_MASK 0x30000000
+#define MC_FUS_ARB_GARLIC_WR_PRI__VCE_WR_PRI__SHIFT 0x1c
+#define MC_FUS_ARB_GARLIC_WR_PRI__VCEU_WR_PRI_MASK 0xc0000000
+#define MC_FUS_ARB_GARLIC_WR_PRI__VCEU_WR_PRI__SHIFT 0x1e
+#define MC_FUS_ARB_GARLIC_WR_PRI2__SMU_WR_PRI_MASK 0x3
+#define MC_FUS_ARB_GARLIC_WR_PRI2__SMU_WR_PRI__SHIFT 0x0
+#define MC_FUS_ARB_GARLIC_WR_PRI2__SAM_WR_PRI_MASK 0xc
+#define MC_FUS_ARB_GARLIC_WR_PRI2__SAM_WR_PRI__SHIFT 0x2
+#define MC_FUS_ARB_GARLIC_WR_PRI2__ACP_WR_PRI_MASK 0x30
+#define MC_FUS_ARB_GARLIC_WR_PRI2__ACP_WR_PRI__SHIFT 0x4
+#define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffff
+#define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x0
+#define MC_GRUB_PROBE_MAP__ADDR0_TO_TC_MAP_MASK 0x3
+#define MC_GRUB_PROBE_MAP__ADDR0_TO_TC_MAP__SHIFT 0x0
+#define MC_GRUB_PROBE_MAP__ADDR1_TO_TC_MAP_MASK 0xc
+#define MC_GRUB_PROBE_MAP__ADDR1_TO_TC_MAP__SHIFT 0x2
+#define MC_GRUB_PROBE_MAP__ADDR2_TO_TC_MAP_MASK 0x30
+#define MC_GRUB_PROBE_MAP__ADDR2_TO_TC_MAP__SHIFT 0x4
+#define MC_GRUB_PROBE_MAP__ADDR3_TO_TC_MAP_MASK 0xc0
+#define MC_GRUB_PROBE_MAP__ADDR3_TO_TC_MAP__SHIFT 0x6
+#define MC_GRUB_PROBE_MAP__ADDR0_TO_GRUB_MAP_MASK 0x100
+#define MC_GRUB_PROBE_MAP__ADDR0_TO_GRUB_MAP__SHIFT 0x8
+#define MC_GRUB_PROBE_MAP__ADDR1_TO_GRUB_MAP_MASK 0x200
+#define MC_GRUB_PROBE_MAP__ADDR1_TO_GRUB_MAP__SHIFT 0x9
+#define MC_GRUB_PROBE_MAP__ADDR2_TO_GRUB_MAP_MASK 0x400
+#define MC_GRUB_PROBE_MAP__ADDR2_TO_GRUB_MAP__SHIFT 0xa
+#define MC_GRUB_PROBE_MAP__ADDR3_TO_GRUB_MAP_MASK 0x800
+#define MC_GRUB_PROBE_MAP__ADDR3_TO_GRUB_MAP__SHIFT 0xb
+#define MC_GRUB_POST_PROBE_DELAY__REQ_TO_RSP_DELAY_MASK 0x1f
+#define MC_GRUB_POST_PROBE_DELAY__REQ_TO_RSP_DELAY__SHIFT 0x0
+#define MC_GRUB_POST_PROBE_DELAY__REQLCL_TO_RET_DELAY_MASK 0x1f00
+#define MC_GRUB_POST_PROBE_DELAY__REQLCL_TO_RET_DELAY__SHIFT 0x8
+#define MC_GRUB_POST_PROBE_DELAY__REQREM_TO_RET_DELAY_MASK 0x1f0000
+#define MC_GRUB_POST_PROBE_DELAY__REQREM_TO_RET_DELAY__SHIFT 0x10
+#define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_LO_MASK 0x3f
+#define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_LO__SHIFT 0x0
+#define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_HI_MASK 0x3f00
+#define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_HI__SHIFT 0x8
+#define MC_GRUB_PROBE_CREDITS__INTPRB_FIFO_LEVEL_MASK 0x8000
+#define MC_GRUB_PROBE_CREDITS__INTPRB_FIFO_LEVEL__SHIFT 0xf
+#define MC_GRUB_PROBE_CREDITS__INTPRB_TIMEOUT_THRESH_MASK 0x70000
+#define MC_GRUB_PROBE_CREDITS__INTPRB_TIMEOUT_THRESH__SHIFT 0x10
+#define MC_GRUB_PROBE_CREDITS__MEM_TIMEOUT_THRESH_MASK 0x700000
+#define MC_GRUB_PROBE_CREDITS__MEM_TIMEOUT_THRESH__SHIFT 0x14
+#define MC_GRUB_FEATURES__WR_COMBINE_OFF_MASK 0x1
+#define MC_GRUB_FEATURES__WR_COMBINE_OFF__SHIFT 0x0
+#define MC_GRUB_FEATURES__SCLK_CG_DISABLE_MASK 0x2
+#define MC_GRUB_FEATURES__SCLK_CG_DISABLE__SHIFT 0x1
+#define MC_GRUB_FEATURES__PRB_FILTER_DISABLE_MASK 0x4
+#define MC_GRUB_FEATURES__PRB_FILTER_DISABLE__SHIFT 0x2
+#define MC_GRUB_FEATURES__ARB_NRT_STACK_DISABLE_MASK 0x8
+#define MC_GRUB_FEATURES__ARB_NRT_STACK_DISABLE__SHIFT 0x3
+#define MC_GRUB_FEATURES__ARB_FIXED_PRIORITY_MASK 0x10
+#define MC_GRUB_FEATURES__ARB_FIXED_PRIORITY__SHIFT 0x4
+#define MC_GRUB_FEATURES__PRIORITY_UPDATE_DISABLE_MASK 0x20
+#define MC_GRUB_FEATURES__PRIORITY_UPDATE_DISABLE__SHIFT 0x5
+#define MC_GRUB_FEATURES__RT_BYPASS_OFF_MASK 0x40
+#define MC_GRUB_FEATURES__RT_BYPASS_OFF__SHIFT 0x6
+#define MC_GRUB_FEATURES__SYNC_ON_ERROR_DISABLE_MASK 0x80
+#define MC_GRUB_FEATURES__SYNC_ON_ERROR_DISABLE__SHIFT 0x7
+#define MC_GRUB_FEATURES__SYNC_REFLECT_DISABLE_MASK 0x100
+#define MC_GRUB_FEATURES__SYNC_REFLECT_DISABLE__SHIFT 0x8
+#define MC_GRUB_FEATURES__ARB_STALL_EN_MASK 0x400
+#define MC_GRUB_FEATURES__ARB_STALL_EN__SHIFT 0xa
+#define MC_GRUB_FEATURES__CREDIT_STALL_EN_MASK 0x800
+#define MC_GRUB_FEATURES__CREDIT_STALL_EN__SHIFT 0xb
+#define MC_GRUB_FEATURES__ARB_STALL_SET_SEL_MASK 0x3000
+#define MC_GRUB_FEATURES__ARB_STALL_SET_SEL__SHIFT 0xc
+#define MC_GRUB_FEATURES__ARB_STALL_CLR_SEL_MASK 0xc000
+#define MC_GRUB_FEATURES__ARB_STALL_CLR_SEL__SHIFT 0xe
+#define MC_GRUB_FEATURES__CREDIT_STALL_SET_SEL_MASK 0x30000
+#define MC_GRUB_FEATURES__CREDIT_STALL_SET_SEL__SHIFT 0x10
+#define MC_GRUB_FEATURES__CREDIT_STALL_CLR_SEL_MASK 0xc0000
+#define MC_GRUB_FEATURES__CREDIT_STALL_CLR_SEL__SHIFT 0x12
+#define MC_GRUB_FEATURES__WR_REORDER_OFF_MASK 0x100000
+#define MC_GRUB_FEATURES__WR_REORDER_OFF__SHIFT 0x14
+#define MC_GRUB_TX_CREDITS__SRCTAG_LIMIT_MASK 0x3f
+#define MC_GRUB_TX_CREDITS__SRCTAG_LIMIT__SHIFT 0x0
+#define MC_GRUB_TX_CREDITS__SRCTAG_RT_RESERVE_MASK 0xf00
+#define MC_GRUB_TX_CREDITS__SRCTAG_RT_RESERVE__SHIFT 0x8
+#define MC_GRUB_TX_CREDITS__NPC_RT_RESERVE_MASK 0xf000
+#define MC_GRUB_TX_CREDITS__NPC_RT_RESERVE__SHIFT 0xc
+#define MC_GRUB_TX_CREDITS__NPD_RT_RESERVE_MASK 0xf0000
+#define MC_GRUB_TX_CREDITS__NPD_RT_RESERVE__SHIFT 0x10
+#define MC_GRUB_TX_CREDITS__TX_FIFO_DEPTH_MASK 0x1f00000
+#define MC_GRUB_TX_CREDITS__TX_FIFO_DEPTH__SHIFT 0x14
+#define MC_GRUB_TCB_INDEX__INDEX_MASK 0x7f
+#define MC_GRUB_TCB_INDEX__INDEX__SHIFT 0x0
+#define MC_GRUB_TCB_INDEX__TCB0_WR_EN_MASK 0x100
+#define MC_GRUB_TCB_INDEX__TCB0_WR_EN__SHIFT 0x8
+#define MC_GRUB_TCB_INDEX__TCB1_WR_EN_MASK 0x200
+#define MC_GRUB_TCB_INDEX__TCB1_WR_EN__SHIFT 0x9
+#define MC_GRUB_TCB_INDEX__RD_EN_MASK 0x400
+#define MC_GRUB_TCB_INDEX__RD_EN__SHIFT 0xa
+#define MC_GRUB_TCB_INDEX__TCB_SEL_MASK 0x800
+#define MC_GRUB_TCB_INDEX__TCB_SEL__SHIFT 0xb
+#define MC_GRUB_TCB_DATA_LO__DATA_MASK 0xffffffff
+#define MC_GRUB_TCB_DATA_LO__DATA__SHIFT 0x0
+#define MC_GRUB_TCB_DATA_HI__DATA_MASK 0xffffffff
+#define MC_GRUB_TCB_DATA_HI__DATA__SHIFT 0x0
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x1
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x2
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x10
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x20
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x40
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0xf00
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0xf0000
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10
+#define MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x1fff
+#define MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x1
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x2
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x70
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x80
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0xf00
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x1fff000
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0xff00
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xff000000
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x1
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x2
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x4
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x8
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x10
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0xe0
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0xf00
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x7000
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x8000
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1fff0000
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x1fff
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x2000
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x4000
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x1
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x2
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x4
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x8
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x10
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0xe0
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0xf00
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x7000
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x8000
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1fff0000
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x1fff
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x2000
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x4000
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x1
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x2
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x4
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x8
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x10
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0xe0
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0xf00
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x7000
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x8000
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1fff0000
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x1fff
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x2000
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x4000
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x1
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x2
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x4
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x8
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x10
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0xe0
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0xf00
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x7000
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x8000
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1fff0000
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x1fff
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x2000
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x4000
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x3
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xfc000000
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x1a
+#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT0_URGENCY_WATERMARK_MASK 0xffff
+#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT0_URGENCY_WATERMARK__SHIFT 0x0
+#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT1_URGENCY_WATERMARK_MASK 0xffff0000
+#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT1_URGENCY_WATERMARK__SHIFT 0x10
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK 0xff
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT 0x0
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK 0xffffffff
+#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT 0x0
+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xffffffff
+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0
+#define MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x3ffff
+#define MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xffffffff
+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0
+#define MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x3ffff
+#define MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xffffffff
+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0
+#define MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x3ffff
+#define MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xffffffff
+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0
+#define MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x3ffff
+#define MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xffffffff
+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0
+#define MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x3ffff
+#define MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xffffffff
+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0
+#define MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x3ffff
+#define MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xffffffff
+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0
+#define MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x3ffff
+#define MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0
+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xffffffff
+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0
+#define MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x3ffff
+#define MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x1
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x10
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x20
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x40
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0xf00
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1fff0000
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10
+#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_DEFAULT_VMID_MASK 0xf00
+#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_DEFAULT_VMID__SHIFT 0x8
+#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_ALLOWED_VMID_MASK_MASK 0xffff0000
+#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_ALLOWED_VMID_MASK__SHIFT 0x10
+
+#endif /* GMC_8_2_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h
new file mode 100644
index 000000000000..34ab258fd35e
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_d.h
@@ -0,0 +1,642 @@
+/*
+ * OSS_2_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef OSS_2_0_D_H
+#define OSS_2_0_D_H
+
+#define mmIH_VMID_0_LUT 0xf50
+#define mmIH_VMID_1_LUT 0xf51
+#define mmIH_VMID_2_LUT 0xf52
+#define mmIH_VMID_3_LUT 0xf53
+#define mmIH_VMID_4_LUT 0xf54
+#define mmIH_VMID_5_LUT 0xf55
+#define mmIH_VMID_6_LUT 0xf56
+#define mmIH_VMID_7_LUT 0xf57
+#define mmIH_VMID_8_LUT 0xf58
+#define mmIH_VMID_9_LUT 0xf59
+#define mmIH_VMID_10_LUT 0xf5a
+#define mmIH_VMID_11_LUT 0xf5b
+#define mmIH_VMID_12_LUT 0xf5c
+#define mmIH_VMID_13_LUT 0xf5d
+#define mmIH_VMID_14_LUT 0xf5e
+#define mmIH_VMID_15_LUT 0xf5f
+#define mmIH_RB_CNTL 0xf80
+#define mmIH_RB_BASE 0xf81
+#define mmIH_RB_RPTR 0xf82
+#define mmIH_RB_WPTR 0xf83
+#define mmIH_RB_WPTR_ADDR_HI 0xf84
+#define mmIH_RB_WPTR_ADDR_LO 0xf85
+#define mmIH_CNTL 0xf86
+#define mmIH_LEVEL_STATUS 0xf87
+#define mmIH_STATUS 0xf88
+#define mmIH_PERFMON_CNTL 0xf89
+#define mmIH_PERFCOUNTER0_RESULT 0xf8a
+#define mmIH_PERFCOUNTER1_RESULT 0xf8b
+#define mmIH_ADVFAULT_CNTL 0xf8c
+#define mmSEM_MCIF_CONFIG 0xf90
+#define mmSDMA_CONFIG 0xf91
+#define mmSDMA1_CONFIG 0xf92
+#define mmUVD_CONFIG 0xf93
+#define mmVCE_CONFIG 0xf94
+#define mmACP_CONFIG 0xf95
+#define mmCPG_CONFIG 0xf96
+#define mmCPC1_CONFIG 0xf97
+#define mmCPC2_CONFIG 0xf98
+#define mmSEM_STATUS 0xf99
+#define mmSEM_EDC_CONFIG 0xf9a
+#define mmSEM_MAILBOX_CLIENTCONFIG 0xf9b
+#define mmSEM_MAILBOX 0xf9c
+#define mmSEM_MAILBOX_CONTROL 0xf9d
+#define mmSEM_CHICKEN_BITS 0xf9e
+#define mmSRBM_CNTL 0x390
+#define mmSRBM_GFX_CNTL 0x391
+#define mmSRBM_STATUS2 0x393
+#define mmSRBM_STATUS 0x394
+#define mmSRBM_CAM_INDEX 0x396
+#define mmSRBM_CAM_DATA 0x397
+#define mmSRBM_SOFT_RESET 0x398
+#define mmSRBM_DEBUG_CNTL 0x399
+#define mmSRBM_DEBUG_DATA 0x39a
+#define mmSRBM_CHIP_REVISION 0x39b
+#define mmCC_SYS_RB_REDUNDANCY 0x39f
+#define mmCC_SYS_RB_BACKEND_DISABLE 0x3a0
+#define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x3a1
+#define mmSRBM_MC_CLKEN_CNTL 0x3b3
+#define mmSRBM_SYS_CLKEN_CNTL 0x3b4
+#define mmSRBM_VCE_CLKEN_CNTL 0x3b5
+#define mmSRBM_UVD_CLKEN_CNTL 0x3b6
+#define mmSRBM_SDMA_CLKEN_CNTL 0x3b7
+#define mmSRBM_SAM_CLKEN_CNTL 0x3b8
+#define mmSRBM_DEBUG 0x3a4
+#define mmSRBM_DEBUG_SNAPSHOT 0x3a5
+#define mmSRBM_READ_ERROR 0x3a6
+#define mmSRBM_INT_CNTL 0x3a8
+#define mmSRBM_INT_STATUS 0x3a9
+#define mmSRBM_INT_ACK 0x3aa
+#define mmSRBM_PERFMON_CNTL 0x700
+#define mmSRBM_PERFCOUNTER0_SELECT 0x701
+#define mmSRBM_PERFCOUNTER1_SELECT 0x702
+#define mmSRBM_PERFCOUNTER0_LO 0x703
+#define mmSRBM_PERFCOUNTER0_HI 0x704
+#define mmSRBM_PERFCOUNTER1_LO 0x705
+#define mmSRBM_PERFCOUNTER1_HI 0x706
+#define mmCC_DRM_ID_STRAPS 0x1559
+#define mmCGTT_DRM_CLK_CTRL0 0x1579
+#define ixDH_TEST 0x0
+#define ixKHFS0 0x4
+#define ixKHFS1 0x8
+#define ixKHFS2 0xc
+#define ixKHFS3 0x10
+#define ixKSESSION0 0x14
+#define ixKSESSION1 0x18
+#define ixKSESSION2 0x1c
+#define ixKSESSION3 0x20
+#define ixKSIG0 0x24
+#define ixKSIG1 0x28
+#define ixKSIG2 0x2c
+#define ixKSIG3 0x30
+#define ixEXP0 0x34
+#define ixEXP1 0x38
+#define ixEXP2 0x3c
+#define ixEXP3 0x40
+#define ixEXP4 0x44
+#define ixEXP5 0x48
+#define ixEXP6 0x4c
+#define ixEXP7 0x50
+#define ixLX0 0x54
+#define ixLX1 0x58
+#define ixLX2 0x5c
+#define ixLX3 0x60
+#define ixCLIENT2_K0 0x1b4
+#define ixCLIENT2_K1 0x1b8
+#define ixCLIENT2_K2 0x1bc
+#define ixCLIENT2_K3 0x1c0
+#define ixCLIENT2_CK0 0x1c4
+#define ixCLIENT2_CK1 0x1c8
+#define ixCLIENT2_CK2 0x1cc
+#define ixCLIENT2_CK3 0x1d0
+#define ixCLIENT2_CD0 0x1d4
+#define ixCLIENT2_CD1 0x1d8
+#define ixCLIENT2_CD2 0x1dc
+#define ixCLIENT2_CD3 0x1e0
+#define ixCLIENT2_BM 0x1e4
+#define ixCLIENT2_OFFSET 0x1e8
+#define ixCLIENT2_STATUS 0x1ec
+#define ixCLIENT0_K0 0x1f0
+#define ixCLIENT0_K1 0x1f4
+#define ixCLIENT0_K2 0x1f8
+#define ixCLIENT0_K3 0x1fc
+#define ixCLIENT0_CK0 0x200
+#define ixCLIENT0_CK1 0x204
+#define ixCLIENT0_CK2 0x208
+#define ixCLIENT0_CK3 0x20c
+#define ixCLIENT0_CD0 0x210
+#define ixCLIENT0_CD1 0x214
+#define ixCLIENT0_CD2 0x218
+#define ixCLIENT0_CD3 0x21c
+#define ixCLIENT0_BM 0x220
+#define ixCLIENT0_OFFSET 0x224
+#define ixCLIENT0_STATUS 0x228
+#define ixCLIENT1_K0 0x22c
+#define ixCLIENT1_K1 0x230
+#define ixCLIENT1_K2 0x234
+#define ixCLIENT1_K3 0x238
+#define ixCLIENT1_CK0 0x23c
+#define ixCLIENT1_CK1 0x240
+#define ixCLIENT1_CK2 0x244
+#define ixCLIENT1_CK3 0x248
+#define ixCLIENT1_CD0 0x24c
+#define ixCLIENT1_CD1 0x250
+#define ixCLIENT1_CD2 0x254
+#define ixCLIENT1_CD3 0x258
+#define ixCLIENT1_BM 0x25c
+#define ixCLIENT1_OFFSET 0x260
+#define ixCLIENT1_PORT_STATUS 0x264
+#define ixKEFUSE0 0x268
+#define ixKEFUSE1 0x26c
+#define ixKEFUSE2 0x270
+#define ixKEFUSE3 0x274
+#define ixHFS_SEED0 0x278
+#define ixHFS_SEED1 0x27c
+#define ixHFS_SEED2 0x280
+#define ixHFS_SEED3 0x284
+#define ixRINGOSC_MASK 0x288
+#define ixCLIENT0_OFFSET_HI 0x290
+#define ixCLIENT1_OFFSET_HI 0x294
+#define ixCLIENT2_OFFSET_HI 0x298
+#define ixSPU_PORT_STATUS 0x29c
+#define ixCLIENT3_OFFSET_HI 0x2a0
+#define ixCLIENT3_K0 0x2a4
+#define ixCLIENT3_K1 0x2a8
+#define ixCLIENT3_K2 0x2ac
+#define ixCLIENT3_K3 0x2b0
+#define ixCLIENT3_CK0 0x2b4
+#define ixCLIENT3_CK1 0x2b8
+#define ixCLIENT3_CK2 0x2bc
+#define ixCLIENT3_CK3 0x2c0
+#define ixCLIENT3_CD0 0x2c4
+#define ixCLIENT3_CD1 0x2c8
+#define ixCLIENT3_CD2 0x2cc
+#define ixCLIENT3_CD3 0x2d0
+#define ixCLIENT3_BM 0x2d4
+#define ixCLIENT3_OFFSET 0x2d8
+#define ixCLIENT3_STATUS 0x2dc
+#define mmDC_TEST_DEBUG_INDEX 0x157c
+#define mmDC_TEST_DEBUG_DATA 0x157d
+#define mmXDMA_SLV_CNTL 0x460
+#define mmXDMA_SLV_MEM_CLIENT_CONFIG 0x461
+#define mmXDMA_SLV_SLS_PITCH 0x462
+#define mmXDMA_SLV_READ_URGENT_CNTL 0x463
+#define mmXDMA_SLV_WRITE_URGENT_CNTL 0x464
+#define mmXDMA_SLV_WB_RATE_CNTL 0x465
+#define mmXDMA_SLV_READ_LATENCY_MINMAX 0x466
+#define mmXDMA_SLV_READ_LATENCY_AVE 0x467
+#define mmXDMA_SLV_PCIE_NACK_STATUS 0x468
+#define mmXDMA_SLV_MEM_NACK_STATUS 0x469
+#define mmXDMA_SLV_RDRET_BUF_STATUS 0x46a
+#define mmXDMA_SLV_READ_LATENCY_TIMER 0x46b
+#define mmXDMA_SLV_FLIP_PENDING 0x46c
+#define mmSDMA0_UCODE_ADDR 0x3400
+#define mmSDMA0_UCODE_DATA 0x3401
+#define mmSDMA0_POWER_CNTL 0x3402
+#define mmSDMA0_CLK_CTRL 0x3403
+#define mmSDMA0_CNTL 0x3404
+#define mmSDMA0_CHICKEN_BITS 0x3405
+#define mmSDMA0_TILING_CONFIG 0x3406
+#define mmSDMA0_HASH 0x3407
+#define mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL 0x3408
+#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409
+#define mmSDMA0_RB_RPTR_FETCH 0x340a
+#define mmSDMA0_IB_OFFSET_FETCH 0x340b
+#define mmSDMA0_PROGRAM 0x340c
+#define mmSDMA0_STATUS_REG 0x340d
+#define mmSDMA0_STATUS1_REG 0x340e
+#define mmSDMA0_PERFMON_CNTL 0x340f
+#define mmSDMA0_PERFCOUNTER0_RESULT 0x3410
+#define mmSDMA0_PERFCOUNTER1_RESULT 0x3411
+#define mmSDMA0_F32_CNTL 0x3412
+#define mmSDMA0_FREEZE 0x3413
+#define mmSDMA0_PHASE0_QUANTUM 0x3414
+#define mmSDMA0_PHASE1_QUANTUM 0x3415
+#define mmSDMA_POWER_GATING 0x3416
+#define mmSDMA_PGFSM_CONFIG 0x3417
+#define mmSDMA_PGFSM_WRITE 0x3418
+#define mmSDMA_PGFSM_READ 0x3419
+#define mmSDMA0_EDC_CONFIG 0x341a
+#define mmSDMA0_GFX_RB_CNTL 0x3480
+#define mmSDMA0_GFX_RB_BASE 0x3481
+#define mmSDMA0_GFX_RB_BASE_HI 0x3482
+#define mmSDMA0_GFX_RB_RPTR 0x3483
+#define mmSDMA0_GFX_RB_WPTR 0x3484
+#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487
+#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x3488
+#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x3489
+#define mmSDMA0_GFX_IB_CNTL 0x348a
+#define mmSDMA0_GFX_IB_RPTR 0x348b
+#define mmSDMA0_GFX_IB_OFFSET 0x348c
+#define mmSDMA0_GFX_IB_BASE_LO 0x348d
+#define mmSDMA0_GFX_IB_BASE_HI 0x348e
+#define mmSDMA0_GFX_IB_SIZE 0x348f
+#define mmSDMA0_GFX_SKIP_CNTL 0x3490
+#define mmSDMA0_GFX_CONTEXT_STATUS 0x3491
+#define mmSDMA0_GFX_CONTEXT_CNTL 0x3493
+#define mmSDMA0_GFX_VIRTUAL_ADDR 0x34a7
+#define mmSDMA0_GFX_APE1_CNTL 0x34a8
+#define mmSDMA0_GFX_WATERMARK 0x34aa
+#define mmSDMA0_RLC0_RB_CNTL 0x3500
+#define mmSDMA0_RLC0_RB_BASE 0x3501
+#define mmSDMA0_RLC0_RB_BASE_HI 0x3502
+#define mmSDMA0_RLC0_RB_RPTR 0x3503
+#define mmSDMA0_RLC0_RB_WPTR 0x3504
+#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x3506
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x3507
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x3508
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x3509
+#define mmSDMA0_RLC0_IB_CNTL 0x350a
+#define mmSDMA0_RLC0_IB_RPTR 0x350b
+#define mmSDMA0_RLC0_IB_OFFSET 0x350c
+#define mmSDMA0_RLC0_IB_BASE_LO 0x350d
+#define mmSDMA0_RLC0_IB_BASE_HI 0x350e
+#define mmSDMA0_RLC0_IB_SIZE 0x350f
+#define mmSDMA0_RLC0_SKIP_CNTL 0x3510
+#define mmSDMA0_RLC0_CONTEXT_STATUS 0x3511
+#define mmSDMA0_RLC0_DOORBELL 0x3512
+#define mmSDMA0_RLC0_VIRTUAL_ADDR 0x3527
+#define mmSDMA0_RLC0_APE1_CNTL 0x3528
+#define mmSDMA0_RLC0_DOORBELL_LOG 0x3529
+#define mmSDMA0_RLC0_WATERMARK 0x352a
+#define mmSDMA0_RLC1_RB_CNTL 0x3580
+#define mmSDMA0_RLC1_RB_BASE 0x3581
+#define mmSDMA0_RLC1_RB_BASE_HI 0x3582
+#define mmSDMA0_RLC1_RB_RPTR 0x3583
+#define mmSDMA0_RLC1_RB_WPTR 0x3584
+#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x3585
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x3586
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x3587
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x3588
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x3589
+#define mmSDMA0_RLC1_IB_CNTL 0x358a
+#define mmSDMA0_RLC1_IB_RPTR 0x358b
+#define mmSDMA0_RLC1_IB_OFFSET 0x358c
+#define mmSDMA0_RLC1_IB_BASE_LO 0x358d
+#define mmSDMA0_RLC1_IB_BASE_HI 0x358e
+#define mmSDMA0_RLC1_IB_SIZE 0x358f
+#define mmSDMA0_RLC1_SKIP_CNTL 0x3590
+#define mmSDMA0_RLC1_CONTEXT_STATUS 0x3591
+#define mmSDMA0_RLC1_DOORBELL 0x3592
+#define mmSDMA0_RLC1_VIRTUAL_ADDR 0x35a7
+#define mmSDMA0_RLC1_APE1_CNTL 0x35a8
+#define mmSDMA0_RLC1_DOORBELL_LOG 0x35a9
+#define mmSDMA0_RLC1_WATERMARK 0x35aa
+#define mmSDMA1_UCODE_ADDR 0x3600
+#define mmSDMA1_UCODE_DATA 0x3601
+#define mmSDMA1_POWER_CNTL 0x3602
+#define mmSDMA1_CLK_CTRL 0x3603
+#define mmSDMA1_CNTL 0x3604
+#define mmSDMA1_CHICKEN_BITS 0x3605
+#define mmSDMA1_TILING_CONFIG 0x3606
+#define mmSDMA1_HASH 0x3607
+#define mmSDMA1_SEM_INCOMPLETE_TIMER_CNTL 0x3608
+#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x3609
+#define mmSDMA1_RB_RPTR_FETCH 0x360a
+#define mmSDMA1_IB_OFFSET_FETCH 0x360b
+#define mmSDMA1_PROGRAM 0x360c
+#define mmSDMA1_STATUS_REG 0x360d
+#define mmSDMA1_STATUS1_REG 0x360e
+#define mmSDMA1_PERFMON_CNTL 0x360f
+#define mmSDMA1_PERFCOUNTER0_RESULT 0x3610
+#define mmSDMA1_PERFCOUNTER1_RESULT 0x3611
+#define mmSDMA1_F32_CNTL 0x3612
+#define mmSDMA1_FREEZE 0x3613
+#define mmSDMA1_PHASE0_QUANTUM 0x3614
+#define mmSDMA1_PHASE1_QUANTUM 0x3615
+#define mmSDMA1_EDC_CONFIG 0x361a
+#define mmSDMA1_GFX_RB_CNTL 0x3680
+#define mmSDMA1_GFX_RB_BASE 0x3681
+#define mmSDMA1_GFX_RB_BASE_HI 0x3682
+#define mmSDMA1_GFX_RB_RPTR 0x3683
+#define mmSDMA1_GFX_RB_WPTR 0x3684
+#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x3686
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x3687
+#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x3688
+#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x3689
+#define mmSDMA1_GFX_IB_CNTL 0x368a
+#define mmSDMA1_GFX_IB_RPTR 0x368b
+#define mmSDMA1_GFX_IB_OFFSET 0x368c
+#define mmSDMA1_GFX_IB_BASE_LO 0x368d
+#define mmSDMA1_GFX_IB_BASE_HI 0x368e
+#define mmSDMA1_GFX_IB_SIZE 0x368f
+#define mmSDMA1_GFX_SKIP_CNTL 0x3690
+#define mmSDMA1_GFX_CONTEXT_STATUS 0x3691
+#define mmSDMA1_GFX_CONTEXT_CNTL 0x3693
+#define mmSDMA1_GFX_VIRTUAL_ADDR 0x36a7
+#define mmSDMA1_GFX_APE1_CNTL 0x36a8
+#define mmSDMA1_GFX_WATERMARK 0x36aa
+#define mmSDMA1_RLC0_RB_CNTL 0x3700
+#define mmSDMA1_RLC0_RB_BASE 0x3701
+#define mmSDMA1_RLC0_RB_BASE_HI 0x3702
+#define mmSDMA1_RLC0_RB_RPTR 0x3703
+#define mmSDMA1_RLC0_RB_WPTR 0x3704
+#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x3706
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x3707
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x3708
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x3709
+#define mmSDMA1_RLC0_IB_CNTL 0x370a
+#define mmSDMA1_RLC0_IB_RPTR 0x370b
+#define mmSDMA1_RLC0_IB_OFFSET 0x370c
+#define mmSDMA1_RLC0_IB_BASE_LO 0x370d
+#define mmSDMA1_RLC0_IB_BASE_HI 0x370e
+#define mmSDMA1_RLC0_IB_SIZE 0x370f
+#define mmSDMA1_RLC0_SKIP_CNTL 0x3710
+#define mmSDMA1_RLC0_CONTEXT_STATUS 0x3711
+#define mmSDMA1_RLC0_DOORBELL 0x3712
+#define mmSDMA1_RLC0_VIRTUAL_ADDR 0x3727
+#define mmSDMA1_RLC0_APE1_CNTL 0x3728
+#define mmSDMA1_RLC0_DOORBELL_LOG 0x3729
+#define mmSDMA1_RLC0_WATERMARK 0x372a
+#define mmSDMA1_RLC1_RB_CNTL 0x3780
+#define mmSDMA1_RLC1_RB_BASE 0x3781
+#define mmSDMA1_RLC1_RB_BASE_HI 0x3782
+#define mmSDMA1_RLC1_RB_RPTR 0x3783
+#define mmSDMA1_RLC1_RB_WPTR 0x3784
+#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x3785
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x3786
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x3787
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x3788
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x3789
+#define mmSDMA1_RLC1_IB_CNTL 0x378a
+#define mmSDMA1_RLC1_IB_RPTR 0x378b
+#define mmSDMA1_RLC1_IB_OFFSET 0x378c
+#define mmSDMA1_RLC1_IB_BASE_LO 0x378d
+#define mmSDMA1_RLC1_IB_BASE_HI 0x378e
+#define mmSDMA1_RLC1_IB_SIZE 0x378f
+#define mmSDMA1_RLC1_SKIP_CNTL 0x3790
+#define mmSDMA1_RLC1_CONTEXT_STATUS 0x3791
+#define mmSDMA1_RLC1_DOORBELL 0x3792
+#define mmSDMA1_RLC1_VIRTUAL_ADDR 0x37a7
+#define mmSDMA1_RLC1_APE1_CNTL 0x37a8
+#define mmSDMA1_RLC1_DOORBELL_LOG 0x37a9
+#define mmSDMA1_RLC1_WATERMARK 0x37aa
+#define mmXDMA_SLV_CHANNEL_CNTL 0x470
+#define mmSDMA_CHANNEL0_XDMA_SLV_CHANNEL_CNTL 0x470
+#define mmSDMA_CHANNEL1_XDMA_SLV_CHANNEL_CNTL 0x478
+#define mmSDMA_CHANNEL2_XDMA_SLV_CHANNEL_CNTL 0x480
+#define mmSDMA_CHANNEL3_XDMA_SLV_CHANNEL_CNTL 0x488
+#define mmSDMA_CHANNEL4_XDMA_SLV_CHANNEL_CNTL 0x490
+#define mmSDMA_CHANNEL5_XDMA_SLV_CHANNEL_CNTL 0x498
+#define mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x471
+#define mmSDMA_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS 0x471
+#define mmSDMA_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS 0x479
+#define mmSDMA_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS 0x481
+#define mmSDMA_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS 0x489
+#define mmSDMA_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS 0x491
+#define mmSDMA_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS 0x499
+#define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472
+#define mmSDMA_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472
+#define mmSDMA_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x47a
+#define mmSDMA_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x482
+#define mmSDMA_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x48a
+#define mmSDMA_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x492
+#define mmSDMA_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x49a
+#define mmXDMA_MSTR_PIPE_CNTL 0x400
+#define mmMDMA_PIPE0_XDMA_MSTR_PIPE_CNTL 0x400
+#define mmMDMA_PIPE1_XDMA_MSTR_PIPE_CNTL 0x410
+#define mmMDMA_PIPE2_XDMA_MSTR_PIPE_CNTL 0x420
+#define mmMDMA_PIPE3_XDMA_MSTR_PIPE_CNTL 0x430
+#define mmMDMA_PIPE4_XDMA_MSTR_PIPE_CNTL 0x440
+#define mmMDMA_PIPE5_XDMA_MSTR_PIPE_CNTL 0x450
+#define mmXDMA_MSTR_READ_COMMAND 0x401
+#define mmMDMA_PIPE0_XDMA_MSTR_READ_COMMAND 0x401
+#define mmMDMA_PIPE1_XDMA_MSTR_READ_COMMAND 0x411
+#define mmMDMA_PIPE2_XDMA_MSTR_READ_COMMAND 0x421
+#define mmMDMA_PIPE3_XDMA_MSTR_READ_COMMAND 0x431
+#define mmMDMA_PIPE4_XDMA_MSTR_READ_COMMAND 0x441
+#define mmMDMA_PIPE5_XDMA_MSTR_READ_COMMAND 0x451
+#define mmXDMA_MSTR_CHANNEL_DIM 0x402
+#define mmMDMA_PIPE0_XDMA_MSTR_CHANNEL_DIM 0x402
+#define mmMDMA_PIPE1_XDMA_MSTR_CHANNEL_DIM 0x412
+#define mmMDMA_PIPE2_XDMA_MSTR_CHANNEL_DIM 0x422
+#define mmMDMA_PIPE3_XDMA_MSTR_CHANNEL_DIM 0x432
+#define mmMDMA_PIPE4_XDMA_MSTR_CHANNEL_DIM 0x442
+#define mmMDMA_PIPE5_XDMA_MSTR_CHANNEL_DIM 0x452
+#define mmXDMA_MSTR_HEIGHT 0x403
+#define mmMDMA_PIPE0_XDMA_MSTR_HEIGHT 0x403
+#define mmMDMA_PIPE1_XDMA_MSTR_HEIGHT 0x413
+#define mmMDMA_PIPE2_XDMA_MSTR_HEIGHT 0x423
+#define mmMDMA_PIPE3_XDMA_MSTR_HEIGHT 0x433
+#define mmMDMA_PIPE4_XDMA_MSTR_HEIGHT 0x443
+#define mmMDMA_PIPE5_XDMA_MSTR_HEIGHT 0x453
+#define mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x404
+#define mmMDMA_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE 0x404
+#define mmMDMA_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE 0x414
+#define mmMDMA_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE 0x424
+#define mmMDMA_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE 0x434
+#define mmMDMA_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE 0x444
+#define mmMDMA_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE 0x454
+#define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405
+#define mmMDMA_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405
+#define mmMDMA_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x415
+#define mmMDMA_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x425
+#define mmMDMA_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x435
+#define mmMDMA_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x445
+#define mmMDMA_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x455
+#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x406
+#define mmMDMA_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x406
+#define mmMDMA_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x416
+#define mmMDMA_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x426
+#define mmMDMA_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x436
+#define mmMDMA_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x446
+#define mmMDMA_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x456
+#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407
+#define mmMDMA_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407
+#define mmMDMA_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x417
+#define mmMDMA_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x427
+#define mmMDMA_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x437
+#define mmMDMA_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x447
+#define mmMDMA_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x457
+#define mmXDMA_MSTR_CACHE_BASE_ADDR 0x408
+#define mmMDMA_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR 0x408
+#define mmMDMA_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR 0x418
+#define mmMDMA_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR 0x428
+#define mmMDMA_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR 0x438
+#define mmMDMA_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR 0x448
+#define mmMDMA_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR 0x458
+#define mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409
+#define mmMDMA_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409
+#define mmMDMA_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x419
+#define mmMDMA_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x429
+#define mmMDMA_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x439
+#define mmMDMA_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x449
+#define mmMDMA_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x459
+#define mmXDMA_MSTR_CACHE_PITCH 0x40a
+#define mmMDMA_PIPE0_XDMA_MSTR_CACHE_PITCH 0x40a
+#define mmMDMA_PIPE1_XDMA_MSTR_CACHE_PITCH 0x41a
+#define mmMDMA_PIPE2_XDMA_MSTR_CACHE_PITCH 0x42a
+#define mmMDMA_PIPE3_XDMA_MSTR_CACHE_PITCH 0x43a
+#define mmMDMA_PIPE4_XDMA_MSTR_CACHE_PITCH 0x44a
+#define mmMDMA_PIPE5_XDMA_MSTR_CACHE_PITCH 0x45a
+#define mmXDMA_MSTR_CHANNEL_START 0x40b
+#define mmMDMA_PIPE0_XDMA_MSTR_CHANNEL_START 0x40b
+#define mmMDMA_PIPE1_XDMA_MSTR_CHANNEL_START 0x41b
+#define mmMDMA_PIPE2_XDMA_MSTR_CHANNEL_START 0x42b
+#define mmMDMA_PIPE3_XDMA_MSTR_CHANNEL_START 0x43b
+#define mmMDMA_PIPE4_XDMA_MSTR_CHANNEL_START 0x44b
+#define mmMDMA_PIPE5_XDMA_MSTR_CHANNEL_START 0x45b
+#define mmXDMA_MSTR_MEM_OVERFLOW_CNTL 0x40c
+#define mmMDMA_PIPE0_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x40c
+#define mmMDMA_PIPE1_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x41c
+#define mmMDMA_PIPE2_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x42c
+#define mmMDMA_PIPE3_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x43c
+#define mmMDMA_PIPE4_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x44c
+#define mmMDMA_PIPE5_XDMA_MSTR_MEM_OVERFLOW_CNTL 0x45c
+#define mmXDMA_MSTR_MEM_UNDERFLOW_CNTL 0x40d
+#define mmMDMA_PIPE0_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x40d
+#define mmMDMA_PIPE1_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x41d
+#define mmMDMA_PIPE2_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x42d
+#define mmMDMA_PIPE3_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x43d
+#define mmMDMA_PIPE4_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x44d
+#define mmMDMA_PIPE5_XDMA_MSTR_MEM_UNDERFLOW_CNTL 0x45d
+#define mmXDMA_MSTR_PERFMEAS_STATUS 0x40e
+#define mmMDMA_PIPE0_XDMA_MSTR_PERFMEAS_STATUS 0x40e
+#define mmMDMA_PIPE1_XDMA_MSTR_PERFMEAS_STATUS 0x41e
+#define mmMDMA_PIPE2_XDMA_MSTR_PERFMEAS_STATUS 0x42e
+#define mmMDMA_PIPE3_XDMA_MSTR_PERFMEAS_STATUS 0x43e
+#define mmMDMA_PIPE4_XDMA_MSTR_PERFMEAS_STATUS 0x44e
+#define mmMDMA_PIPE5_XDMA_MSTR_PERFMEAS_STATUS 0x45e
+#define mmXDMA_MSTR_PERFMEAS_CNTL 0x40f
+#define mmMDMA_PIPE0_XDMA_MSTR_PERFMEAS_CNTL 0x40f
+#define mmMDMA_PIPE1_XDMA_MSTR_PERFMEAS_CNTL 0x41f
+#define mmMDMA_PIPE2_XDMA_MSTR_PERFMEAS_CNTL 0x42f
+#define mmMDMA_PIPE3_XDMA_MSTR_PERFMEAS_CNTL 0x43f
+#define mmMDMA_PIPE4_XDMA_MSTR_PERFMEAS_CNTL 0x44f
+#define mmMDMA_PIPE5_XDMA_MSTR_PERFMEAS_CNTL 0x45f
+#define mmXDMA_MSTR_CNTL 0x3ec
+#define mmXDMA_MSTR_STATUS 0x3ed
+#define mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x3ee
+#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x3ef
+#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x3f0
+#define mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x3f1
+#define mmXDMA_MSTR_CMD_URGENT_CNTL 0x3f2
+#define mmXDMA_MSTR_MEM_URGENT_CNTL 0x3f3
+#define mmXDMA_MSTR_MEM_UNDERFLOW_CONFIG 0x3f4
+#define mmXDMA_MSTR_PCIE_NACK_STATUS 0x3f5
+#define mmXDMA_MSTR_MEM_NACK_STATUS 0x3f6
+#define mmXDMA_MSTR_VSYNC_GSL_CHECK 0x3f7
+#define mmHDP_HOST_PATH_CNTL 0xb00
+#define mmHDP_NONSURFACE_BASE 0xb01
+#define mmHDP_NONSURFACE_INFO 0xb02
+#define mmHDP_NONSURFACE_SIZE 0xb03
+#define mmHDP_NONSURF_FLAGS 0xbc9
+#define mmHDP_NONSURF_FLAGS_CLR 0xbca
+#define mmHDP_SW_SEMAPHORE 0xbcb
+#define mmHDP_DEBUG0 0xbcc
+#define mmHDP_DEBUG1 0xbcd
+#define mmHDP_LAST_SURFACE_HIT 0xbce
+#define mmHDP_TILING_CONFIG 0xbcf
+#define mmHDP_SC_MULTI_CHIP_CNTL 0xbd0
+#define mmHDP_OUTSTANDING_REQ 0xbd1
+#define mmHDP_ADDR_CONFIG 0xbd2
+#define mmHDP_MISC_CNTL 0xbd3
+#define mmHDP_MEM_POWER_LS 0xbd4
+#define mmHDP_NONSURFACE_PREFETCH 0xbd5
+#define mmHDP_MEMIO_CNTL 0xbf6
+#define mmHDP_MEMIO_ADDR 0xbf7
+#define mmHDP_MEMIO_STATUS 0xbf8
+#define mmHDP_MEMIO_WR_DATA 0xbf9
+#define mmHDP_MEMIO_RD_DATA 0xbfa
+#define mmHDP_XDP_DIRECT2HDP_FIRST 0xc00
+#define mmHDP_XDP_D2H_FLUSH 0xc01
+#define mmHDP_XDP_D2H_BAR_UPDATE 0xc02
+#define mmHDP_XDP_D2H_RSVD_3 0xc03
+#define mmHDP_XDP_D2H_RSVD_4 0xc04
+#define mmHDP_XDP_D2H_RSVD_5 0xc05
+#define mmHDP_XDP_D2H_RSVD_6 0xc06
+#define mmHDP_XDP_D2H_RSVD_7 0xc07
+#define mmHDP_XDP_D2H_RSVD_8 0xc08
+#define mmHDP_XDP_D2H_RSVD_9 0xc09
+#define mmHDP_XDP_D2H_RSVD_10 0xc0a
+#define mmHDP_XDP_D2H_RSVD_11 0xc0b
+#define mmHDP_XDP_D2H_RSVD_12 0xc0c
+#define mmHDP_XDP_D2H_RSVD_13 0xc0d
+#define mmHDP_XDP_D2H_RSVD_14 0xc0e
+#define mmHDP_XDP_D2H_RSVD_15 0xc0f
+#define mmHDP_XDP_D2H_RSVD_16 0xc10
+#define mmHDP_XDP_D2H_RSVD_17 0xc11
+#define mmHDP_XDP_D2H_RSVD_18 0xc12
+#define mmHDP_XDP_D2H_RSVD_19 0xc13
+#define mmHDP_XDP_D2H_RSVD_20 0xc14
+#define mmHDP_XDP_D2H_RSVD_21 0xc15
+#define mmHDP_XDP_D2H_RSVD_22 0xc16
+#define mmHDP_XDP_D2H_RSVD_23 0xc17
+#define mmHDP_XDP_D2H_RSVD_24 0xc18
+#define mmHDP_XDP_D2H_RSVD_25 0xc19
+#define mmHDP_XDP_D2H_RSVD_26 0xc1a
+#define mmHDP_XDP_D2H_RSVD_27 0xc1b
+#define mmHDP_XDP_D2H_RSVD_28 0xc1c
+#define mmHDP_XDP_D2H_RSVD_29 0xc1d
+#define mmHDP_XDP_D2H_RSVD_30 0xc1e
+#define mmHDP_XDP_D2H_RSVD_31 0xc1f
+#define mmHDP_XDP_D2H_RSVD_32 0xc20
+#define mmHDP_XDP_D2H_RSVD_33 0xc21
+#define mmHDP_XDP_D2H_RSVD_34 0xc22
+#define mmHDP_XDP_DIRECT2HDP_LAST 0xc23
+#define mmHDP_XDP_P2P_BAR_CFG 0xc24
+#define mmHDP_XDP_P2P_MBX_OFFSET 0xc25
+#define mmHDP_XDP_P2P_MBX_ADDR0 0xc26
+#define mmHDP_XDP_P2P_MBX_ADDR1 0xc27
+#define mmHDP_XDP_P2P_MBX_ADDR2 0xc28
+#define mmHDP_XDP_P2P_MBX_ADDR3 0xc29
+#define mmHDP_XDP_P2P_MBX_ADDR4 0xc2a
+#define mmHDP_XDP_P2P_MBX_ADDR5 0xc2b
+#define mmHDP_XDP_P2P_MBX_ADDR6 0xc2c
+#define mmHDP_XDP_HDP_MBX_MC_CFG 0xc2d
+#define mmHDP_XDP_HDP_MC_CFG 0xc2e
+#define mmHDP_XDP_HST_CFG 0xc2f
+#define mmHDP_XDP_SID_CFG 0xc30
+#define mmHDP_XDP_HDP_IPH_CFG 0xc31
+#define mmHDP_XDP_SRBM_CFG 0xc32
+#define mmHDP_XDP_CGTT_BLK_CTRL 0xc33
+#define mmHDP_XDP_P2P_BAR0 0xc34
+#define mmHDP_XDP_P2P_BAR1 0xc35
+#define mmHDP_XDP_P2P_BAR2 0xc36
+#define mmHDP_XDP_P2P_BAR3 0xc37
+#define mmHDP_XDP_P2P_BAR4 0xc38
+#define mmHDP_XDP_P2P_BAR5 0xc39
+#define mmHDP_XDP_P2P_BAR6 0xc3a
+#define mmHDP_XDP_P2P_BAR7 0xc3b
+#define mmHDP_XDP_FLUSH_ARMED_STS 0xc3c
+#define mmHDP_XDP_FLUSH_CNTR0_STS 0xc3d
+#define mmHDP_XDP_BUSY_STS 0xc3e
+#define mmHDP_XDP_STICKY 0xc3f
+#define mmHDP_XDP_CHKN 0xc40
+#define mmHDP_XDP_DBG_ADDR 0xc41
+#define mmHDP_XDP_DBG_DATA 0xc42
+#define mmHDP_XDP_DBG_MASK 0xc43
+#define mmHDP_XDP_BARS_ADDR_39_36 0xc44
+
+#endif /* OSS_2_0_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h
new file mode 100644
index 000000000000..99e0b2dced04
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h
@@ -0,0 +1,2476 @@
+/*
+ * OSS_2_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef OSS_2_0_SH_MASK_H
+#define OSS_2_0_SH_MASK_H
+
+#define IH_VMID_0_LUT__PASID_MASK 0xffff
+#define IH_VMID_0_LUT__PASID__SHIFT 0x0
+#define IH_VMID_1_LUT__PASID_MASK 0xffff
+#define IH_VMID_1_LUT__PASID__SHIFT 0x0
+#define IH_VMID_2_LUT__PASID_MASK 0xffff
+#define IH_VMID_2_LUT__PASID__SHIFT 0x0
+#define IH_VMID_3_LUT__PASID_MASK 0xffff
+#define IH_VMID_3_LUT__PASID__SHIFT 0x0
+#define IH_VMID_4_LUT__PASID_MASK 0xffff
+#define IH_VMID_4_LUT__PASID__SHIFT 0x0
+#define IH_VMID_5_LUT__PASID_MASK 0xffff
+#define IH_VMID_5_LUT__PASID__SHIFT 0x0
+#define IH_VMID_6_LUT__PASID_MASK 0xffff
+#define IH_VMID_6_LUT__PASID__SHIFT 0x0
+#define IH_VMID_7_LUT__PASID_MASK 0xffff
+#define IH_VMID_7_LUT__PASID__SHIFT 0x0
+#define IH_VMID_8_LUT__PASID_MASK 0xffff
+#define IH_VMID_8_LUT__PASID__SHIFT 0x0
+#define IH_VMID_9_LUT__PASID_MASK 0xffff
+#define IH_VMID_9_LUT__PASID__SHIFT 0x0
+#define IH_VMID_10_LUT__PASID_MASK 0xffff
+#define IH_VMID_10_LUT__PASID__SHIFT 0x0
+#define IH_VMID_11_LUT__PASID_MASK 0xffff
+#define IH_VMID_11_LUT__PASID__SHIFT 0x0
+#define IH_VMID_12_LUT__PASID_MASK 0xffff
+#define IH_VMID_12_LUT__PASID__SHIFT 0x0
+#define IH_VMID_13_LUT__PASID_MASK 0xffff
+#define IH_VMID_13_LUT__PASID__SHIFT 0x0
+#define IH_VMID_14_LUT__PASID_MASK 0xffff
+#define IH_VMID_14_LUT__PASID__SHIFT 0x0
+#define IH_VMID_15_LUT__PASID_MASK 0xffff
+#define IH_VMID_15_LUT__PASID__SHIFT 0x0
+#define IH_RB_CNTL__RB_ENABLE_MASK 0x1
+#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define IH_RB_CNTL__RB_SIZE_MASK 0x3e
+#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x40
+#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x6
+#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x80
+#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7
+#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100
+#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
+#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00
+#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
+#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x10000
+#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10
+#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
+#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define IH_RB_BASE__ADDR_MASK 0xffffffff
+#define IH_RB_BASE__ADDR__SHIFT 0x0
+#define IH_RB_RPTR__OFFSET_MASK 0x3fffc
+#define IH_RB_RPTR__OFFSET__SHIFT 0x2
+#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1
+#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0
+#define IH_RB_WPTR__OFFSET_MASK 0x3fffc
+#define IH_RB_WPTR__OFFSET__SHIFT 0x2
+#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0xff
+#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define IH_CNTL__ENABLE_INTR_MASK 0x1
+#define IH_CNTL__ENABLE_INTR__SHIFT 0x0
+#define IH_CNTL__MC_SWAP_MASK 0x6
+#define IH_CNTL__MC_SWAP__SHIFT 0x1
+#define IH_CNTL__MC_TRAN_MASK 0x8
+#define IH_CNTL__MC_TRAN__SHIFT 0x3
+#define IH_CNTL__RPTR_REARM_MASK 0x10
+#define IH_CNTL__RPTR_REARM__SHIFT 0x4
+#define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x300
+#define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x8
+#define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x7c00
+#define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa
+#define IH_CNTL__MC_WRREQ_CREDIT_MASK 0xf8000
+#define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0xf
+#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x1f00000
+#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14
+#define IH_CNTL__MC_VMID_MASK 0x1e000000
+#define IH_CNTL__MC_VMID__SHIFT 0x19
+#define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1
+#define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x0
+#define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x4
+#define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2
+#define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x8
+#define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x3
+#define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x10
+#define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x4
+#define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x20
+#define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x5
+#define IH_STATUS__IDLE_MASK 0x1
+#define IH_STATUS__IDLE__SHIFT 0x0
+#define IH_STATUS__INPUT_IDLE_MASK 0x2
+#define IH_STATUS__INPUT_IDLE__SHIFT 0x1
+#define IH_STATUS__RB_IDLE_MASK 0x4
+#define IH_STATUS__RB_IDLE__SHIFT 0x2
+#define IH_STATUS__RB_FULL_MASK 0x8
+#define IH_STATUS__RB_FULL__SHIFT 0x3
+#define IH_STATUS__RB_FULL_DRAIN_MASK 0x10
+#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4
+#define IH_STATUS__RB_OVERFLOW_MASK 0x20
+#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5
+#define IH_STATUS__MC_WR_IDLE_MASK 0x40
+#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6
+#define IH_STATUS__MC_WR_STALL_MASK 0x80
+#define IH_STATUS__MC_WR_STALL__SHIFT 0x7
+#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x100
+#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8
+#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x200
+#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9
+#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x400
+#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa
+#define IH_PERFMON_CNTL__ENABLE0_MASK 0x1
+#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0
+#define IH_PERFMON_CNTL__CLEAR0_MASK 0x2
+#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1
+#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
+#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
+#define IH_PERFMON_CNTL__ENABLE1_MASK 0x100
+#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x8
+#define IH_PERFMON_CNTL__CLEAR1_MASK 0x200
+#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x9
+#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
+#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
+#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
+#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
+#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
+#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
+#define IH_ADVFAULT_CNTL__WATERMARK_MASK 0x7
+#define IH_ADVFAULT_CNTL__WATERMARK__SHIFT 0x0
+#define IH_ADVFAULT_CNTL__WATERMARK_ENABLE_MASK 0x8
+#define IH_ADVFAULT_CNTL__WATERMARK_ENABLE__SHIFT 0x3
+#define IH_ADVFAULT_CNTL__WATERMARK_REACHED_MASK 0x10
+#define IH_ADVFAULT_CNTL__WATERMARK_REACHED__SHIFT 0x4
+#define IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED_MASK 0xff00
+#define IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED__SHIFT 0x8
+#define IH_ADVFAULT_CNTL__WAIT_TIMER_MASK 0x3fff0000
+#define IH_ADVFAULT_CNTL__WAIT_TIMER__SHIFT 0x10
+#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x3
+#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0
+#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0xfc
+#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2
+#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x3f00
+#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8
+#define SDMA_CONFIG__SDMA_RDREQ_URG_MASK 0xf00
+#define SDMA_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8
+#define SDMA_CONFIG__SDMA_REQ_TRAN_MASK 0x10000
+#define SDMA_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10
+#define SDMA1_CONFIG__SDMA_RDREQ_URG_MASK 0xf00
+#define SDMA1_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8
+#define SDMA1_CONFIG__SDMA_REQ_TRAN_MASK 0x10000
+#define SDMA1_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10
+#define UVD_CONFIG__UVD_RDREQ_URG_MASK 0xf00
+#define UVD_CONFIG__UVD_RDREQ_URG__SHIFT 0x8
+#define UVD_CONFIG__UVD_REQ_TRAN_MASK 0x10000
+#define UVD_CONFIG__UVD_REQ_TRAN__SHIFT 0x10
+#define VCE_CONFIG__VCE_RDREQ_URG_MASK 0xf00
+#define VCE_CONFIG__VCE_RDREQ_URG__SHIFT 0x8
+#define VCE_CONFIG__VCE_REQ_TRAN_MASK 0x10000
+#define VCE_CONFIG__VCE_REQ_TRAN__SHIFT 0x10
+#define ACP_CONFIG__ACP_RDREQ_URG_MASK 0xf00
+#define ACP_CONFIG__ACP_RDREQ_URG__SHIFT 0x8
+#define ACP_CONFIG__ACP_REQ_TRAN_MASK 0x10000
+#define ACP_CONFIG__ACP_REQ_TRAN__SHIFT 0x10
+#define CPG_CONFIG__CPG_RDREQ_URG_MASK 0xf00
+#define CPG_CONFIG__CPG_RDREQ_URG__SHIFT 0x8
+#define CPG_CONFIG__CPG_REQ_TRAN_MASK 0x10000
+#define CPG_CONFIG__CPG_REQ_TRAN__SHIFT 0x10
+#define CPC1_CONFIG__CPC1_RDREQ_URG_MASK 0xf00
+#define CPC1_CONFIG__CPC1_RDREQ_URG__SHIFT 0x8
+#define CPC1_CONFIG__CPC1_REQ_TRAN_MASK 0x10000
+#define CPC1_CONFIG__CPC1_REQ_TRAN__SHIFT 0x10
+#define CPC2_CONFIG__CPC2_RDREQ_URG_MASK 0xf00
+#define CPC2_CONFIG__CPC2_RDREQ_URG__SHIFT 0x8
+#define CPC2_CONFIG__CPC2_REQ_TRAN_MASK 0x10000
+#define CPC2_CONFIG__CPC2_REQ_TRAN__SHIFT 0x10
+#define SEM_STATUS__SEM_IDLE_MASK 0x1
+#define SEM_STATUS__SEM_IDLE__SHIFT 0x0
+#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x2
+#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1
+#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x4
+#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2
+#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x8
+#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3
+#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x10
+#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4
+#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x20
+#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5
+#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x40
+#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6
+#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x80
+#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7
+#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x100
+#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8
+#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x200
+#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9
+#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x400
+#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa
+#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x800
+#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb
+#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x1000
+#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc
+#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x2000
+#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd
+#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x2
+#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x7
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x38
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x1c0
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0xe00
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x7000
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc
+#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x38000
+#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x1c0000
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12
+#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0xe00000
+#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15
+#define SEM_MAILBOX__SIDEPORT_MASK 0xff
+#define SEM_MAILBOX__SIDEPORT__SHIFT 0x0
+#define SEM_MAILBOX__HOSTPORT_MASK 0xff00
+#define SEM_MAILBOX__HOSTPORT__SHIFT 0x8
+#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0xff
+#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x0
+#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0xff00
+#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x8
+#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x1
+#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0
+#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x2
+#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1
+#define SRBM_CNTL__READ_TIMEOUT_MASK 0x1fff
+#define SRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
+#define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x10000
+#define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x10
+#define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x20000
+#define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x11
+#define SRBM_GFX_CNTL__PIPEID_MASK 0x3
+#define SRBM_GFX_CNTL__PIPEID__SHIFT 0x0
+#define SRBM_GFX_CNTL__MEID_MASK 0xc
+#define SRBM_GFX_CNTL__MEID__SHIFT 0x2
+#define SRBM_GFX_CNTL__VMID_MASK 0xf0
+#define SRBM_GFX_CNTL__VMID__SHIFT 0x4
+#define SRBM_GFX_CNTL__QUEUEID_MASK 0x700
+#define SRBM_GFX_CNTL__QUEUEID__SHIFT 0x8
+#define SRBM_STATUS2__SDMA_RQ_PENDING_MASK 0x1
+#define SRBM_STATUS2__SDMA_RQ_PENDING__SHIFT 0x0
+#define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x2
+#define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x1
+#define SRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x4
+#define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x2
+#define SRBM_STATUS2__VCE_RQ_PENDING_MASK 0x8
+#define SRBM_STATUS2__VCE_RQ_PENDING__SHIFT 0x3
+#define SRBM_STATUS2__XSP_BUSY_MASK 0x10
+#define SRBM_STATUS2__XSP_BUSY__SHIFT 0x4
+#define SRBM_STATUS2__SDMA_BUSY_MASK 0x20
+#define SRBM_STATUS2__SDMA_BUSY__SHIFT 0x5
+#define SRBM_STATUS2__SDMA1_BUSY_MASK 0x40
+#define SRBM_STATUS2__SDMA1_BUSY__SHIFT 0x6
+#define SRBM_STATUS2__VCE_BUSY_MASK 0x80
+#define SRBM_STATUS2__VCE_BUSY__SHIFT 0x7
+#define SRBM_STATUS2__XDMA_BUSY_MASK 0x100
+#define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x8
+#define SRBM_STATUS2__CHUB_BUSY_MASK 0x200
+#define SRBM_STATUS2__CHUB_BUSY__SHIFT 0x9
+#define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x2
+#define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x1
+#define SRBM_STATUS__SAM_RQ_PENDING_MASK 0x4
+#define SRBM_STATUS__SAM_RQ_PENDING__SHIFT 0x2
+#define SRBM_STATUS__ACP_RQ_PENDING_MASK 0x8
+#define SRBM_STATUS__ACP_RQ_PENDING__SHIFT 0x3
+#define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x10
+#define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x4
+#define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x20
+#define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x5
+#define SRBM_STATUS__HI_RQ_PENDING_MASK 0x40
+#define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x6
+#define SRBM_STATUS__IO_EXTERN_SIGNAL_MASK 0x80
+#define SRBM_STATUS__IO_EXTERN_SIGNAL__SHIFT 0x7
+#define SRBM_STATUS__VMC_BUSY_MASK 0x100
+#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8
+#define SRBM_STATUS__MCB_BUSY_MASK 0x200
+#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9
+#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400
+#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa
+#define SRBM_STATUS__MCC_BUSY_MASK 0x800
+#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb
+#define SRBM_STATUS__MCD_BUSY_MASK 0x1000
+#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc
+#define SRBM_STATUS__SEM_BUSY_MASK 0x4000
+#define SRBM_STATUS__SEM_BUSY__SHIFT 0xe
+#define SRBM_STATUS__ACP_BUSY_MASK 0x10000
+#define SRBM_STATUS__ACP_BUSY__SHIFT 0x10
+#define SRBM_STATUS__IH_BUSY_MASK 0x20000
+#define SRBM_STATUS__IH_BUSY__SHIFT 0x11
+#define SRBM_STATUS__UVD_BUSY_MASK 0x80000
+#define SRBM_STATUS__UVD_BUSY__SHIFT 0x13
+#define SRBM_STATUS__SAM_BUSY_MASK 0x100000
+#define SRBM_STATUS__SAM_BUSY__SHIFT 0x14
+#define SRBM_STATUS__BIF_BUSY_MASK 0x20000000
+#define SRBM_STATUS__BIF_BUSY__SHIFT 0x1d
+#define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x7
+#define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
+#define SRBM_CAM_DATA__CAM_ADDR_MASK 0xffff
+#define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
+#define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
+#define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
+#define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x2
+#define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x1
+#define SRBM_SOFT_RESET__SOFT_RESET_ROPLL_MASK 0x10
+#define SRBM_SOFT_RESET__SOFT_RESET_ROPLL__SHIFT 0x4
+#define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x20
+#define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x5
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x40
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x6
+#define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x100
+#define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x8
+#define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x200
+#define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x9
+#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400
+#define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa
+#define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x800
+#define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0xb
+#define SRBM_SOFT_RESET__SOFT_RESET_CHUB_MASK 0x1000
+#define SRBM_SOFT_RESET__SOFT_RESET_CHUB__SHIFT 0xc
+#define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x4000
+#define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0xe
+#define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x8000
+#define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0xf
+#define SRBM_SOFT_RESET__SOFT_RESET_SMU_MASK 0x10000
+#define SRBM_SOFT_RESET__SOFT_RESET_SMU__SHIFT 0x10
+#define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x20000
+#define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x11
+#define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x40000
+#define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x12
+#define SRBM_SOFT_RESET__SOFT_RESET_XSP_MASK 0x80000
+#define SRBM_SOFT_RESET__SOFT_RESET_XSP__SHIFT 0x13
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK 0x100000
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA__SHIFT 0x14
+#define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x200000
+#define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x15
+#define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x400000
+#define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x16
+#define SRBM_SOFT_RESET__SOFT_RESET_ORB_MASK 0x800000
+#define SRBM_SOFT_RESET__SOFT_RESET_ORB__SHIFT 0x17
+#define SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK 0x1000000
+#define SRBM_SOFT_RESET__SOFT_RESET_VCE__SHIFT 0x18
+#define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x2000000
+#define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x19
+#define SRBM_SOFT_RESET__SOFT_RESET_ACP_MASK 0x4000000
+#define SRBM_SOFT_RESET__SOFT_RESET_ACP__SHIFT 0x1a
+#define SRBM_SOFT_RESET__SOFT_RESET_SAM_MASK 0x8000000
+#define SRBM_SOFT_RESET__SOFT_RESET_SAM__SHIFT 0x1b
+#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x3f
+#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x0
+#define SRBM_DEBUG_DATA__DATA_MASK 0xffffffff
+#define SRBM_DEBUG_DATA__DATA__SHIFT 0x0
+#define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0xff
+#define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0
+#define CC_SYS_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
+#define CC_SYS_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
+#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
+#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
+#define CC_SYS_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
+#define CC_SYS_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
+#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
+#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
+#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
+#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
+#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
+#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
+#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_DEBUG__IGNORE_RDY_MASK 0x1
+#define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x0
+#define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x2
+#define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x1
+#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x4
+#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x2
+#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x10
+#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x4
+#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x20
+#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x5
+#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x40
+#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x6
+#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE_MASK 0x80
+#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x7
+#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x100
+#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x8
+#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE_MASK 0x200
+#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x9
+#define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x1
+#define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x0
+#define SRBM_DEBUG_SNAPSHOT__ROPLL_RDY_MASK 0x2
+#define SRBM_DEBUG_SNAPSHOT__ROPLL_RDY__SHIFT 0x1
+#define SRBM_DEBUG_SNAPSHOT__SMU_RDY_MASK 0x4
+#define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT 0x2
+#define SRBM_DEBUG_SNAPSHOT__SAM_RDY_MASK 0x8
+#define SRBM_DEBUG_SNAPSHOT__SAM_RDY__SHIFT 0x3
+#define SRBM_DEBUG_SNAPSHOT__ACP_RDY_MASK 0x10
+#define SRBM_DEBUG_SNAPSHOT__ACP_RDY__SHIFT 0x4
+#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x20
+#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x5
+#define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x40
+#define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x6
+#define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x80
+#define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x7
+#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x100
+#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x8
+#define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x200
+#define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x9
+#define SRBM_DEBUG_SNAPSHOT__XSP_RDY_MASK 0x400
+#define SRBM_DEBUG_SNAPSHOT__XSP_RDY__SHIFT 0xa
+#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x800
+#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0xb
+#define SRBM_DEBUG_SNAPSHOT__ORB_RDY_MASK 0x1000
+#define SRBM_DEBUG_SNAPSHOT__ORB_RDY__SHIFT 0xc
+#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x2000
+#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0xd
+#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x4000
+#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0xe
+#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x8000
+#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0xf
+#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x10000
+#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x10
+#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x20000
+#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x11
+#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x40000
+#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x12
+#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x80000
+#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x13
+#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x100000
+#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x14
+#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x200000
+#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x15
+#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x400000
+#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x16
+#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x800000
+#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x17
+#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x1000000
+#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x18
+#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x2000000
+#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x19
+#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x4000000
+#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x1a
+#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x8000000
+#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x1b
+#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000
+#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x1c
+#define SRBM_DEBUG_SNAPSHOT__VCE_RDY_MASK 0x20000000
+#define SRBM_DEBUG_SNAPSHOT__VCE_RDY__SHIFT 0x1d
+#define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc
+#define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
+#define SRBM_READ_ERROR__READ_REQUESTER_VCE_MASK 0x100000
+#define SRBM_READ_ERROR__READ_REQUESTER_VCE__SHIFT 0x14
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1_MASK 0x200000
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1__SHIFT 0x15
+#define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x400000
+#define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x16
+#define SRBM_READ_ERROR__READ_REQUESTER_SAM_MASK 0x800000
+#define SRBM_READ_ERROR__READ_REQUESTER_SAM__SHIFT 0x17
+#define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x1000000
+#define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x18
+#define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x2000000
+#define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x19
+#define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x4000000
+#define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x1a
+#define SRBM_READ_ERROR__READ_REQUESTER_ACP_MASK 0x8000000
+#define SRBM_READ_ERROR__READ_REQUESTER_ACP__SHIFT 0x1b
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA_MASK 0x10000000
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA__SHIFT 0x1c
+#define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000
+#define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x1d
+#define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000
+#define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
+#define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x1
+#define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x0
+#define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x1
+#define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x0
+#define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x1
+#define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x0
+#define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0xf
+#define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300
+#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
+#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
+#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
+#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
+#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
+#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffff
+#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x0
+#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffff
+#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x0
+#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffff
+#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x0
+#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffff
+#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x0
+#define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0xffff0
+#define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x4
+#define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000
+#define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14
+#define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000
+#define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18
+#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000
+#define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c
+#define DH_TEST__DH_TEST_MASK 0x1
+#define DH_TEST__DH_TEST__SHIFT 0x0
+#define KHFS0__RESERVED_MASK 0xffffffff
+#define KHFS0__RESERVED__SHIFT 0x0
+#define KHFS1__RESERVED_MASK 0xffffffff
+#define KHFS1__RESERVED__SHIFT 0x0
+#define KHFS2__RESERVED_MASK 0xffffffff
+#define KHFS2__RESERVED__SHIFT 0x0
+#define KHFS3__RESERVED_MASK 0xffffffff
+#define KHFS3__RESERVED__SHIFT 0x0
+#define KSESSION0__RESERVED_MASK 0xffffffff
+#define KSESSION0__RESERVED__SHIFT 0x0
+#define KSESSION1__RESERVED_MASK 0xffffffff
+#define KSESSION1__RESERVED__SHIFT 0x0
+#define KSESSION2__RESERVED_MASK 0xffffffff
+#define KSESSION2__RESERVED__SHIFT 0x0
+#define KSESSION3__RESERVED_MASK 0xffffffff
+#define KSESSION3__RESERVED__SHIFT 0x0
+#define KSIG0__RESERVED_MASK 0xffffffff
+#define KSIG0__RESERVED__SHIFT 0x0
+#define KSIG1__RESERVED_MASK 0xffffffff
+#define KSIG1__RESERVED__SHIFT 0x0
+#define KSIG2__RESERVED_MASK 0xffffffff
+#define KSIG2__RESERVED__SHIFT 0x0
+#define KSIG3__RESERVED_MASK 0xffffffff
+#define KSIG3__RESERVED__SHIFT 0x0
+#define EXP0__RESERVED_MASK 0xffffffff
+#define EXP0__RESERVED__SHIFT 0x0
+#define EXP1__RESERVED_MASK 0xffffffff
+#define EXP1__RESERVED__SHIFT 0x0
+#define EXP2__RESERVED_MASK 0xffffffff
+#define EXP2__RESERVED__SHIFT 0x0
+#define EXP3__RESERVED_MASK 0xffffffff
+#define EXP3__RESERVED__SHIFT 0x0
+#define EXP4__RESERVED_MASK 0xffffffff
+#define EXP4__RESERVED__SHIFT 0x0
+#define EXP5__RESERVED_MASK 0xffffffff
+#define EXP5__RESERVED__SHIFT 0x0
+#define EXP6__RESERVED_MASK 0xffffffff
+#define EXP6__RESERVED__SHIFT 0x0
+#define EXP7__RESERVED_MASK 0xffffffff
+#define EXP7__RESERVED__SHIFT 0x0
+#define LX0__RESERVED_MASK 0xffffffff
+#define LX0__RESERVED__SHIFT 0x0
+#define LX1__RESERVED_MASK 0xffffffff
+#define LX1__RESERVED__SHIFT 0x0
+#define LX2__RESERVED_MASK 0xffffffff
+#define LX2__RESERVED__SHIFT 0x0
+#define LX3__RESERVED_MASK 0xffffffff
+#define LX3__RESERVED__SHIFT 0x0
+#define CLIENT2_K0__RESERVED_MASK 0xffffffff
+#define CLIENT2_K0__RESERVED__SHIFT 0x0
+#define CLIENT2_K1__RESERVED_MASK 0xffffffff
+#define CLIENT2_K1__RESERVED__SHIFT 0x0
+#define CLIENT2_K2__RESERVED_MASK 0xffffffff
+#define CLIENT2_K2__RESERVED__SHIFT 0x0
+#define CLIENT2_K3__RESERVED_MASK 0xffffffff
+#define CLIENT2_K3__RESERVED__SHIFT 0x0
+#define CLIENT2_CK0__RESERVED_MASK 0xffffffff
+#define CLIENT2_CK0__RESERVED__SHIFT 0x0
+#define CLIENT2_CK1__RESERVED_MASK 0xffffffff
+#define CLIENT2_CK1__RESERVED__SHIFT 0x0
+#define CLIENT2_CK2__RESERVED_MASK 0xffffffff
+#define CLIENT2_CK2__RESERVED__SHIFT 0x0
+#define CLIENT2_CK3__RESERVED_MASK 0xffffffff
+#define CLIENT2_CK3__RESERVED__SHIFT 0x0
+#define CLIENT2_CD0__RESERVED_MASK 0xffffffff
+#define CLIENT2_CD0__RESERVED__SHIFT 0x0
+#define CLIENT2_CD1__RESERVED_MASK 0xffffffff
+#define CLIENT2_CD1__RESERVED__SHIFT 0x0
+#define CLIENT2_CD2__RESERVED_MASK 0xffffffff
+#define CLIENT2_CD2__RESERVED__SHIFT 0x0
+#define CLIENT2_CD3__RESERVED_MASK 0xffffffff
+#define CLIENT2_CD3__RESERVED__SHIFT 0x0
+#define CLIENT2_BM__RESERVED_MASK 0xffffffff
+#define CLIENT2_BM__RESERVED__SHIFT 0x0
+#define CLIENT2_OFFSET__RESERVED_MASK 0xffffffff
+#define CLIENT2_OFFSET__RESERVED__SHIFT 0x0
+#define CLIENT2_STATUS__RESERVED_MASK 0xffffffff
+#define CLIENT2_STATUS__RESERVED__SHIFT 0x0
+#define CLIENT0_K0__RESERVED_MASK 0xffffffff
+#define CLIENT0_K0__RESERVED__SHIFT 0x0
+#define CLIENT0_K1__RESERVED_MASK 0xffffffff
+#define CLIENT0_K1__RESERVED__SHIFT 0x0
+#define CLIENT0_K2__RESERVED_MASK 0xffffffff
+#define CLIENT0_K2__RESERVED__SHIFT 0x0
+#define CLIENT0_K3__RESERVED_MASK 0xffffffff
+#define CLIENT0_K3__RESERVED__SHIFT 0x0
+#define CLIENT0_CK0__RESERVED_MASK 0xffffffff
+#define CLIENT0_CK0__RESERVED__SHIFT 0x0
+#define CLIENT0_CK1__RESERVED_MASK 0xffffffff
+#define CLIENT0_CK1__RESERVED__SHIFT 0x0
+#define CLIENT0_CK2__RESERVED_MASK 0xffffffff
+#define CLIENT0_CK2__RESERVED__SHIFT 0x0
+#define CLIENT0_CK3__RESERVED_MASK 0xffffffff
+#define CLIENT0_CK3__RESERVED__SHIFT 0x0
+#define CLIENT0_CD0__RESERVED_MASK 0xffffffff
+#define CLIENT0_CD0__RESERVED__SHIFT 0x0
+#define CLIENT0_CD1__RESERVED_MASK 0xffffffff
+#define CLIENT0_CD1__RESERVED__SHIFT 0x0
+#define CLIENT0_CD2__RESERVED_MASK 0xffffffff
+#define CLIENT0_CD2__RESERVED__SHIFT 0x0
+#define CLIENT0_CD3__RESERVED_MASK 0xffffffff
+#define CLIENT0_CD3__RESERVED__SHIFT 0x0
+#define CLIENT0_BM__RESERVED_MASK 0xffffffff
+#define CLIENT0_BM__RESERVED__SHIFT 0x0
+#define CLIENT0_OFFSET__RESERVED_MASK 0xffffffff
+#define CLIENT0_OFFSET__RESERVED__SHIFT 0x0
+#define CLIENT0_STATUS__RESERVED_MASK 0xffffffff
+#define CLIENT0_STATUS__RESERVED__SHIFT 0x0
+#define CLIENT1_K0__RESERVED_MASK 0xffffffff
+#define CLIENT1_K0__RESERVED__SHIFT 0x0
+#define CLIENT1_K1__RESERVED_MASK 0xffffffff
+#define CLIENT1_K1__RESERVED__SHIFT 0x0
+#define CLIENT1_K2__RESERVED_MASK 0xffffffff
+#define CLIENT1_K2__RESERVED__SHIFT 0x0
+#define CLIENT1_K3__RESERVED_MASK 0xffffffff
+#define CLIENT1_K3__RESERVED__SHIFT 0x0
+#define CLIENT1_CK0__RESERVED_MASK 0xffffffff
+#define CLIENT1_CK0__RESERVED__SHIFT 0x0
+#define CLIENT1_CK1__RESERVED_MASK 0xffffffff
+#define CLIENT1_CK1__RESERVED__SHIFT 0x0
+#define CLIENT1_CK2__RESERVED_MASK 0xffffffff
+#define CLIENT1_CK2__RESERVED__SHIFT 0x0
+#define CLIENT1_CK3__RESERVED_MASK 0xffffffff
+#define CLIENT1_CK3__RESERVED__SHIFT 0x0
+#define CLIENT1_CD0__RESERVED_MASK 0xffffffff
+#define CLIENT1_CD0__RESERVED__SHIFT 0x0
+#define CLIENT1_CD1__RESERVED_MASK 0xffffffff
+#define CLIENT1_CD1__RESERVED__SHIFT 0x0
+#define CLIENT1_CD2__RESERVED_MASK 0xffffffff
+#define CLIENT1_CD2__RESERVED__SHIFT 0x0
+#define CLIENT1_CD3__RESERVED_MASK 0xffffffff
+#define CLIENT1_CD3__RESERVED__SHIFT 0x0
+#define CLIENT1_BM__RESERVED_MASK 0xffffffff
+#define CLIENT1_BM__RESERVED__SHIFT 0x0
+#define CLIENT1_OFFSET__RESERVED_MASK 0xffffffff
+#define CLIENT1_OFFSET__RESERVED__SHIFT 0x0
+#define CLIENT1_PORT_STATUS__RESERVED_MASK 0xffffffff
+#define CLIENT1_PORT_STATUS__RESERVED__SHIFT 0x0
+#define KEFUSE0__RESERVED_MASK 0xffffffff
+#define KEFUSE0__RESERVED__SHIFT 0x0
+#define KEFUSE1__RESERVED_MASK 0xffffffff
+#define KEFUSE1__RESERVED__SHIFT 0x0
+#define KEFUSE2__RESERVED_MASK 0xffffffff
+#define KEFUSE2__RESERVED__SHIFT 0x0
+#define KEFUSE3__RESERVED_MASK 0xffffffff
+#define KEFUSE3__RESERVED__SHIFT 0x0
+#define HFS_SEED0__RESERVED_MASK 0xffffffff
+#define HFS_SEED0__RESERVED__SHIFT 0x0
+#define HFS_SEED1__RESERVED_MASK 0xffffffff
+#define HFS_SEED1__RESERVED__SHIFT 0x0
+#define HFS_SEED2__RESERVED_MASK 0xffffffff
+#define HFS_SEED2__RESERVED__SHIFT 0x0
+#define HFS_SEED3__RESERVED_MASK 0xffffffff
+#define HFS_SEED3__RESERVED__SHIFT 0x0
+#define RINGOSC_MASK__MASK_MASK 0xffff
+#define RINGOSC_MASK__MASK__SHIFT 0x0
+#define CLIENT0_OFFSET_HI__RESERVED_MASK 0xffffffff
+#define CLIENT0_OFFSET_HI__RESERVED__SHIFT 0x0
+#define CLIENT1_OFFSET_HI__RESERVED_MASK 0xffffffff
+#define CLIENT1_OFFSET_HI__RESERVED__SHIFT 0x0
+#define CLIENT2_OFFSET_HI__RESERVED_MASK 0xffffffff
+#define CLIENT2_OFFSET_HI__RESERVED__SHIFT 0x0
+#define SPU_PORT_STATUS__RESERVED_MASK 0xffffffff
+#define SPU_PORT_STATUS__RESERVED__SHIFT 0x0
+#define CLIENT3_OFFSET_HI__RESERVED_MASK 0xffffffff
+#define CLIENT3_OFFSET_HI__RESERVED__SHIFT 0x0
+#define CLIENT3_K0__RESERVED_MASK 0xffffffff
+#define CLIENT3_K0__RESERVED__SHIFT 0x0
+#define CLIENT3_K1__RESERVED_MASK 0xffffffff
+#define CLIENT3_K1__RESERVED__SHIFT 0x0
+#define CLIENT3_K2__RESERVED_MASK 0xffffffff
+#define CLIENT3_K2__RESERVED__SHIFT 0x0
+#define CLIENT3_K3__RESERVED_MASK 0xffffffff
+#define CLIENT3_K3__RESERVED__SHIFT 0x0
+#define CLIENT3_CK0__RESERVED_MASK 0xffffffff
+#define CLIENT3_CK0__RESERVED__SHIFT 0x0
+#define CLIENT3_CK1__RESERVED_MASK 0xffffffff
+#define CLIENT3_CK1__RESERVED__SHIFT 0x0
+#define CLIENT3_CK2__RESERVED_MASK 0xffffffff
+#define CLIENT3_CK2__RESERVED__SHIFT 0x0
+#define CLIENT3_CK3__RESERVED_MASK 0xffffffff
+#define CLIENT3_CK3__RESERVED__SHIFT 0x0
+#define CLIENT3_CD0__RESERVED_MASK 0xffffffff
+#define CLIENT3_CD0__RESERVED__SHIFT 0x0
+#define CLIENT3_CD1__RESERVED_MASK 0xffffffff
+#define CLIENT3_CD1__RESERVED__SHIFT 0x0
+#define CLIENT3_CD2__RESERVED_MASK 0xffffffff
+#define CLIENT3_CD2__RESERVED__SHIFT 0x0
+#define CLIENT3_CD3__RESERVED_MASK 0xffffffff
+#define CLIENT3_CD3__RESERVED__SHIFT 0x0
+#define CLIENT3_BM__RESERVED_MASK 0xffffffff
+#define CLIENT3_BM__RESERVED__SHIFT 0x0
+#define CLIENT3_OFFSET__RESERVED_MASK 0xffffffff
+#define CLIENT3_OFFSET__RESERVED__SHIFT 0x0
+#define CLIENT3_STATUS__RESERVED_MASK 0xffffffff
+#define CLIENT3_STATUS__RESERVED__SHIFT 0x0
+#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX_MASK 0xff
+#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA__SHIFT 0x0
+#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES_MASK 0x1
+#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES__SHIFT 0x0
+#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK 0x200
+#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY__SHIFT 0x9
+#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE_MASK 0x400
+#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE__SHIFT 0xa
+#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION_MASK 0x3000
+#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION__SHIFT 0xc
+#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE_MASK 0x10000
+#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE__SHIFT 0x10
+#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN_MASK 0x80000
+#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN__SHIFT 0x13
+#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET_MASK 0x100000
+#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET__SHIFT 0x14
+#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT_MASK 0x1000000
+#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT__SHIFT 0x18
+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP_MASK 0x300
+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP__SHIFT 0x8
+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID_MASK 0xf000
+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID__SHIFT 0xc
+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV_MASK 0x10000
+#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV__SHIFT 0x10
+#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH_MASK 0x3fff
+#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH__SHIFT 0x0
+#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH_MASK 0x3fff0000
+#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH__SHIFT 0x10
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL_MASK 0x1
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL__SHIFT 0x0
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT_MASK 0xf0
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT__SHIFT 0x4
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL_MASK 0xf00
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL__SHIFT 0x8
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY_MASK 0xf000
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY__SHIFT 0xc
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER_MASK 0xffff0000
+#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER__SHIFT 0x10
+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_MASK 0x1
+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL__SHIFT 0x0
+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL_MASK 0xf00
+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL__SHIFT 0x8
+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY_MASK 0xf000
+#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY__SHIFT 0xc
+#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE_MASK 0x1ff
+#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE__SHIFT 0x0
+#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD_MASK 0xffff0000
+#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD__SHIFT 0x10
+#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN_MASK 0xffff
+#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN__SHIFT 0x0
+#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX_MASK 0xffff0000
+#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX__SHIFT 0x10
+#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC_MASK 0xfffff
+#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC__SHIFT 0x0
+#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT_MASK 0xfff00000
+#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT__SHIFT 0x14
+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG_MASK 0x3ff
+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG__SHIFT 0x0
+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_MASK 0x3000
+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK__SHIFT 0xc
+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR_MASK 0x10000
+#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR__SHIFT 0x10
+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG_MASK 0xffff
+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG__SHIFT 0x0
+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_MASK 0x30000
+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK__SHIFT 0x10
+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR_MASK 0x80000000
+#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR__SHIFT 0x1f
+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES_MASK 0x3ff
+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES__SHIFT 0x0
+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE_MASK 0x3ff000
+#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE__SHIFT 0xc
+#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER_MASK 0xffff
+#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER__SHIFT 0x0
+#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING_MASK 0x1
+#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING__SHIFT 0x0
+#define SDMA0_UCODE_ADDR__VALUE_MASK 0x7ff
+#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0
+#define SDMA0_UCODE_DATA__VALUE_MASK 0xffffffff
+#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0
+#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100
+#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
+#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0xf
+#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x1
+#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0
+#define SDMA0_CNTL__SEM_INCOMPLETE_INT_ENABLE_MASK 0x2
+#define SDMA0_CNTL__SEM_INCOMPLETE_INT_ENABLE__SHIFT 0x1
+#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4
+#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
+#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x8
+#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
+#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x10
+#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800
+#define SDMA0_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb
+#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000
+#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
+#define SDMA0_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000
+#define SDMA0_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16
+#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000
+#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
+#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000
+#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
+#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
+#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
+#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000
+#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
+#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000
+#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
+#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000
+#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
+#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define SDMA0_HASH__CHANNEL_BITS_MASK 0x7
+#define SDMA0_HASH__CHANNEL_BITS__SHIFT 0x0
+#define SDMA0_HASH__BANK_BITS_MASK 0x70
+#define SDMA0_HASH__BANK_BITS__SHIFT 0x4
+#define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK 0x700
+#define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
+#define SDMA0_HASH__BANK_XOR_COUNT_MASK 0x7000
+#define SDMA0_HASH__BANK_XOR_COUNT__SHIFT 0xc
+#define SDMA0_SEM_INCOMPLETE_TIMER_CNTL__TIMER_MASK 0xffff
+#define SDMA0_SEM_INCOMPLETE_TIMER_CNTL__TIMER__SHIFT 0x0
+#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff
+#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
+#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc
+#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
+#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc
+#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
+#define SDMA0_PROGRAM__STREAM_MASK 0xffffffff
+#define SDMA0_PROGRAM__STREAM__SHIFT 0x0
+#define SDMA0_STATUS_REG__IDLE_MASK 0x1
+#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0
+#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x2
+#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
+#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x4
+#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2
+#define SDMA0_STATUS_REG__RB_FULL_MASK 0x8
+#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3
+#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x10
+#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
+#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x20
+#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
+#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x40
+#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
+#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x80
+#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
+#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x100
+#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
+#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x200
+#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9
+#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x400
+#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
+#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
+#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
+#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x1000
+#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc
+#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x2000
+#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
+#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x4000
+#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe
+#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000
+#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
+#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000
+#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
+#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000
+#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
+#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x80000
+#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
+#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000
+#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
+#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000
+#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
+#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000
+#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
+#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x4000000
+#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a
+#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000
+#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
+#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000
+#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
+#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000
+#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e
+#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000
+#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
+#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
+#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
+#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x2
+#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
+#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4
+#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
+#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8
+#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
+#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x10
+#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
+#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x20
+#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
+#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x40
+#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
+#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400
+#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
+#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x2000
+#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
+#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000
+#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
+#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x20000
+#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
+#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x40000
+#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
+#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
+#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9
+#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
+#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
+#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
+#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
+#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA0_F32_CNTL__HALT_MASK 0x1
+#define SDMA0_F32_CNTL__HALT__SHIFT 0x0
+#define SDMA0_F32_CNTL__STEP_MASK 0x2
+#define SDMA0_F32_CNTL__STEP__SHIFT 0x1
+#define SDMA0_FREEZE__FREEZE_MASK 0x10
+#define SDMA0_FREEZE__FREEZE__SHIFT 0x4
+#define SDMA0_FREEZE__FROZEN_MASK 0x20
+#define SDMA0_FREEZE__FROZEN__SHIFT 0x5
+#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0xf
+#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00
+#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000
+#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0xf
+#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00
+#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000
+#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA_POWER_GATING__PG_CNTL_ENABLE_MASK 0x1
+#define SDMA_POWER_GATING__PG_CNTL_ENABLE__SHIFT 0x0
+#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK 0x2
+#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE__SHIFT 0x1
+#define SDMA_POWER_GATING__PG_STATE_VALID_MASK 0x4
+#define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT 0x2
+#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x30
+#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4
+#define SDMA_POWER_GATING__SDMA0_ON_CONDITION_MASK 0x40
+#define SDMA_POWER_GATING__SDMA0_ON_CONDITION__SHIFT 0x6
+#define SDMA_POWER_GATING__SDMA1_ON_CONDITION_MASK 0x80
+#define SDMA_POWER_GATING__SDMA1_ON_CONDITION__SHIFT 0x7
+#define SDMA_POWER_GATING__POWER_OFF_DELAY_MASK 0xfff00
+#define SDMA_POWER_GATING__POWER_OFF_DELAY__SHIFT 0x8
+#define SDMA_POWER_GATING__POWER_ON_DELAY_MASK 0xfff00000
+#define SDMA_POWER_GATING__POWER_ON_DELAY__SHIFT 0x14
+#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0xff
+#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
+#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x100
+#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
+#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x200
+#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
+#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x400
+#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
+#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x800
+#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
+#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x1000
+#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc
+#define SDMA_PGFSM_CONFIG__READ_MASK 0x2000
+#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd
+#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000
+#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
+#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000
+#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
+#define SDMA_PGFSM_WRITE__VALUE_MASK 0xffffffff
+#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0
+#define SDMA_PGFSM_READ__VALUE_MASK 0xffffff
+#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0
+#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x2
+#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4
+#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
+#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000
+#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
+#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000
+#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
+#define SDMA0_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA0_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA0_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA0_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA0_GFX_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA0_GFX_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA0_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA0_GFX_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC0_DOORBELL__OFFSET_MASK 0x1fffff
+#define SDMA0_RLC0_DOORBELL__OFFSET__SHIFT 0x0
+#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000
+#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000
+#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA0_RLC0_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA0_RLC0_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA0_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
+#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc
+#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC1_DOORBELL__OFFSET_MASK 0x1fffff
+#define SDMA0_RLC1_DOORBELL__OFFSET__SHIFT 0x0
+#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000
+#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000
+#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA0_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA0_RLC1_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA0_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
+#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc
+#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_UCODE_ADDR__VALUE_MASK 0x7ff
+#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0
+#define SDMA1_UCODE_DATA__VALUE_MASK 0xffffffff
+#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0
+#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100
+#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
+#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0xf
+#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x1
+#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0
+#define SDMA1_CNTL__SEM_INCOMPLETE_INT_ENABLE_MASK 0x2
+#define SDMA1_CNTL__SEM_INCOMPLETE_INT_ENABLE__SHIFT 0x1
+#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4
+#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
+#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x8
+#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
+#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x10
+#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800
+#define SDMA1_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb
+#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000
+#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
+#define SDMA1_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000
+#define SDMA1_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16
+#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000
+#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
+#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000
+#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
+#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
+#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
+#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000
+#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
+#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000
+#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
+#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000
+#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
+#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define SDMA1_HASH__CHANNEL_BITS_MASK 0x7
+#define SDMA1_HASH__CHANNEL_BITS__SHIFT 0x0
+#define SDMA1_HASH__BANK_BITS_MASK 0x70
+#define SDMA1_HASH__BANK_BITS__SHIFT 0x4
+#define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK 0x700
+#define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
+#define SDMA1_HASH__BANK_XOR_COUNT_MASK 0x7000
+#define SDMA1_HASH__BANK_XOR_COUNT__SHIFT 0xc
+#define SDMA1_SEM_INCOMPLETE_TIMER_CNTL__TIMER_MASK 0xffff
+#define SDMA1_SEM_INCOMPLETE_TIMER_CNTL__TIMER__SHIFT 0x0
+#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff
+#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
+#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc
+#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
+#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc
+#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
+#define SDMA1_PROGRAM__STREAM_MASK 0xffffffff
+#define SDMA1_PROGRAM__STREAM__SHIFT 0x0
+#define SDMA1_STATUS_REG__IDLE_MASK 0x1
+#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0
+#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x2
+#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1
+#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x4
+#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2
+#define SDMA1_STATUS_REG__RB_FULL_MASK 0x8
+#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3
+#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x10
+#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
+#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x20
+#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
+#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x40
+#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
+#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x80
+#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
+#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x100
+#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
+#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x200
+#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9
+#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x400
+#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa
+#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
+#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
+#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x1000
+#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc
+#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x2000
+#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
+#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x4000
+#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe
+#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000
+#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
+#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000
+#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
+#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000
+#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
+#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x80000
+#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
+#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000
+#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
+#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000
+#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
+#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000
+#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
+#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x4000000
+#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a
+#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000
+#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
+#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000
+#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
+#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000
+#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e
+#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000
+#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
+#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
+#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
+#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2
+#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
+#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4
+#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
+#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8
+#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
+#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x10
+#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
+#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x20
+#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
+#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x40
+#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
+#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400
+#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
+#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x2000
+#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
+#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000
+#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
+#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x20000
+#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
+#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x40000
+#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
+#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
+#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9
+#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
+#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
+#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
+#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
+#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA1_F32_CNTL__HALT_MASK 0x1
+#define SDMA1_F32_CNTL__HALT__SHIFT 0x0
+#define SDMA1_F32_CNTL__STEP_MASK 0x2
+#define SDMA1_F32_CNTL__STEP__SHIFT 0x1
+#define SDMA1_FREEZE__FREEZE_MASK 0x10
+#define SDMA1_FREEZE__FREEZE__SHIFT 0x4
+#define SDMA1_FREEZE__FROZEN_MASK 0x20
+#define SDMA1_FREEZE__FROZEN__SHIFT 0x5
+#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0xf
+#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0xffff00
+#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000
+#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0xf
+#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0xffff00
+#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000
+#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x2
+#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4
+#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
+#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000
+#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
+#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000
+#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
+#define SDMA1_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA1_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA1_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA1_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA1_GFX_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA1_GFX_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA1_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA1_GFX_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC0_DOORBELL__OFFSET_MASK 0x1fffff
+#define SDMA1_RLC0_DOORBELL__OFFSET__SHIFT 0x0
+#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000
+#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000
+#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA1_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA1_RLC0_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA1_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA1_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
+#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc
+#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC1_DOORBELL__OFFSET_MASK 0x1fffff
+#define SDMA1_RLC1_DOORBELL__OFFSET__SHIFT 0x0
+#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000
+#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000
+#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA1_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA1_RLC1_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA1_RLC1_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA1_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA1_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
+#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc
+#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT_MASK 0x1ff
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT__SHIFT 0x0
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER_MASK 0x10000
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER__SHIFT 0x10
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET_MASK 0x20000
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET__SHIFT 0x11
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE_MASK 0x1000000
+#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE__SHIFT 0x18
+#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS_MASK 0xffffffff
+#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS__SHIFT 0x0
+#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff
+#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES_MASK 0xff
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES__SHIFT 0x0
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST_MASK 0x100
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST__SHIFT 0x8
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE_MASK 0x200
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE__SHIFT 0x9
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET_MASK 0x400
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET__SHIFT 0xa
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE_MASK 0x800
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE__SHIFT 0xb
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID_MASK 0x7000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID__SHIFT 0xc
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE_MASK 0x8000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE__SHIFT 0xf
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN_MASK 0xff0000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN__SHIFT 0x10
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE_MASK 0x1000000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE__SHIFT 0x18
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING_MASK 0x2000000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING__SHIFT 0x19
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING_MASK 0x4000000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING__SHIFT 0x1a
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE_MASK 0x8000000
+#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE__SHIFT 0x1b
+#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE_MASK 0x3fff
+#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE__SHIFT 0x0
+#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH_MASK 0x3fff0000
+#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH__SHIFT 0x10
+#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH_MASK 0x3fff
+#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH__SHIFT 0x0
+#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT_MASK 0x3fff0000
+#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT__SHIFT 0x10
+#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT_MASK 0x3fff
+#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT__SHIFT 0x0
+#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT_MASK 0x3fff0000
+#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT__SHIFT 0x10
+#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE_MASK 0xffffffff
+#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE__SHIFT 0x0
+#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH_MASK 0xff
+#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__SHIFT 0x0
+#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS_MASK 0xffffffff
+#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS__SHIFT 0x0
+#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff
+#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0
+#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR_MASK 0xffffffff
+#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR__SHIFT 0x0
+#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH_MASK 0xff
+#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH__SHIFT 0x0
+#define XDMA_MSTR_CACHE_PITCH__XDMA_MSTR_CACHE_PITCH_MASK 0x3fff
+#define XDMA_MSTR_CACHE_PITCH__XDMA_MSTR_CACHE_PITCH__SHIFT 0x0
+#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X_MASK 0x3fff
+#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X__SHIFT 0x0
+#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y_MASK 0x3fff0000
+#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y__SHIFT 0x10
+#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_MASK 0xffff
+#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT__SHIFT 0x0
+#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_THRESHOLD_MASK 0x3fff0000
+#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_THRESHOLD__SHIFT 0x10
+#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_BP_ENABLE_MASK 0x40000000
+#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_BP_ENABLE__SHIFT 0x1e
+#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_ENABLE_MASK 0x80000000
+#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_ENABLE__SHIFT 0x1f
+#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_COUNT_MASK 0xffff
+#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_COUNT__SHIFT 0x0
+#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_THRESHOLD_MASK 0x3fff0000
+#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_THRESHOLD__SHIFT 0x10
+#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_DETECT_ENABLE_MASK 0x80000000
+#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_DETECT_ENABLE__SHIFT 0x1f
+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA_MASK 0xffffff
+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA__SHIFT 0x0
+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MASK 0x7000000
+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX__SHIFT 0x18
+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE_MASK 0xc0000000
+#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE__SHIFT 0x1e
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER_MASK 0xfff
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER__SHIFT 0x0
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL_MASK 0x1f000
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL__SHIFT 0xc
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST_MASK 0x20000
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST__SHIFT 0x11
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER_MASK 0x7ff80000
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER__SHIFT 0x13
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST_MASK 0x80000000
+#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST__SHIFT 0x1f
+#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION_MASK 0x3000
+#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION__SHIFT 0xc
+#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY_MASK 0x4000
+#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY__SHIFT 0xe
+#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE_MASK 0x10000
+#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE__SHIFT 0x10
+#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE_MASK 0x40000
+#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE__SHIFT 0x12
+#define XDMA_MSTR_CNTL__XDMA_MSTR_LAT_TEST_EN_MASK 0x80000
+#define XDMA_MSTR_CNTL__XDMA_MSTR_LAT_TEST_EN__SHIFT 0x13
+#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET_MASK 0x100000
+#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET__SHIFT 0x14
+#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN_MASK 0x200000
+#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN__SHIFT 0x15
+#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT_MASK 0x3fff
+#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT__SHIFT 0x0
+#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT_MASK 0xfff0000
+#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT__SHIFT 0x10
+#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT_MASK 0x70000000
+#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT__SHIFT 0x1c
+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP_MASK 0x300
+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP__SHIFT 0x8
+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID_MASK 0xf000
+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID__SHIFT 0xc
+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV_MASK 0x10000
+#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV__SHIFT 0x10
+#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_MASK 0xffffffff
+#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__SHIFT 0x0
+#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH_MASK 0xff
+#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__SHIFT 0x0
+#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH_MASK 0x3fff
+#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH__SHIFT 0x0
+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL_MASK 0x1
+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL__SHIFT 0x0
+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL_MASK 0xf00
+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL__SHIFT 0x8
+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY_MASK 0xf000
+#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY__SHIFT 0xc
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL_MASK 0x1
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL__SHIFT 0x0
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT_MASK 0xf0
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT__SHIFT 0x4
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL_MASK 0xf00
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL__SHIFT 0x8
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY_MASK 0xf000
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY__SHIFT 0xc
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER_MASK 0xffff0000
+#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER__SHIFT 0x10
+#define XDMA_MSTR_MEM_UNDERFLOW_CONFIG__XDMA_MSTR_UNDERFLOW_LIMIT_MASK 0xffff
+#define XDMA_MSTR_MEM_UNDERFLOW_CONFIG__XDMA_MSTR_UNDERFLOW_LIMIT__SHIFT 0x0
+#define XDMA_MSTR_MEM_UNDERFLOW_CONFIG__XDMA_MSTR_UNDERFLOW_TIMER_MASK 0xffff0000
+#define XDMA_MSTR_MEM_UNDERFLOW_CONFIG__XDMA_MSTR_UNDERFLOW_TIMER__SHIFT 0x10
+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG_MASK 0x3ff
+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG__SHIFT 0x0
+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_MASK 0x3000
+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK__SHIFT 0xc
+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR_MASK 0x10000
+#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR__SHIFT 0x10
+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG_MASK 0x3ff
+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG__SHIFT 0x0
+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_MASK 0x3000
+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK__SHIFT 0xc
+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR_MASK 0x10000
+#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR__SHIFT 0x10
+#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL_MASK 0x7
+#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL__SHIFT 0x0
+#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT_MASK 0x3fff00
+#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT__SHIFT 0x8
+#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x7
+#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x0
+#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x1f8
+#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x3
+#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x600
+#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9
+#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x1800
+#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x180000
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x200000
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15
+#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x400000
+#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x16
+#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x800000
+#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x17
+#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0xf000000
+#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x18
+#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000
+#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d
+#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000
+#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e
+#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000
+#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f
+#define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffff
+#define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x0
+#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x1
+#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x0
+#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x1e
+#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x1
+#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x60
+#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x5
+#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x380
+#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x7
+#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x1c00
+#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0xa
+#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x6000
+#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0xd
+#define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x8000
+#define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0xf
+#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x10000
+#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x10
+#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0xe0000
+#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x11
+#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x300000
+#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x14
+#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0xc00000
+#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x16
+#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x3000000
+#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x18
+#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0xc000000
+#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x1a
+#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x70000000
+#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x1c
+#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x80000000
+#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x1f
+#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x7ff
+#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x0
+#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800
+#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0xb
+#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x1
+#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0
+#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x2
+#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x1
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x2
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1
+#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffff
+#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0
+#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0
+#define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x0
+#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x3f
+#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0
+#define HDP_TILING_CONFIG__PIPE_TILING_MASK 0xe
+#define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x1
+#define HDP_TILING_CONFIG__BANK_TILING_MASK 0x30
+#define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x4
+#define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0xc0
+#define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x6
+#define HDP_TILING_CONFIG__ROW_TILING_MASK 0x700
+#define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x8
+#define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x3800
+#define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0xb
+#define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0xc000
+#define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0xe
+#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x7
+#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x0
+#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x18
+#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x3
+#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0xff
+#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0
+#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0xff00
+#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8
+#define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x1
+#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0
+#define HDP_MISC_CNTL__VM_ID_MASK 0x1e
+#define HDP_MISC_CNTL__VM_ID__SHIFT 0x1
+#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x20
+#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5
+#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x40
+#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6
+#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x780
+#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x7
+#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x800
+#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb
+#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x1000
+#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0xc
+#define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x7e000
+#define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
+#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x80000
+#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x13
+#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x100000
+#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x14
+#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x200000
+#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15
+#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x1
+#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0
+#define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x7e
+#define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x1
+#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x1f80
+#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x7
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x0
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x38
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x3
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x1c0
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x6
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0xffe00
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x9
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x1b
+#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x1
+#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0
+#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x2
+#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1
+#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x3c
+#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2
+#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x40
+#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6
+#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x80
+#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7
+#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x3f00
+#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8
+#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x4000
+#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe
+#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x8000
+#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf
+#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffff
+#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0
+#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x1
+#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0
+#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x2
+#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1
+#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x4
+#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2
+#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x8
+#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3
+#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffff
+#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0
+#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffff
+#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0
+#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffff
+#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0xf
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0xf0
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x700
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0xf800
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x10000
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x20000
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x11
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x40000
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x80000
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x100000
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0xffff
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0xf0000
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x700000
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
+#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0
+#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffff
+#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0xf
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x30
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4
+#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x3fff
+#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x1
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x0
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x6
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x1
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x8
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x3
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0xf0
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x4
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x1
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x0
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x6
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x1
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x8
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x3
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x10
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x4
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x60
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x5
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x80
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x7
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x3f00
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x8
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0xfc000
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x700000
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x14
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x7800000
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x17
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x1b
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x1
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x6
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1
+#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x1
+#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x0
+#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x6
+#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x1
+#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x18
+#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x3
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x3f
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0xfc0
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x1000
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x2000
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x3f
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x0
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x40
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x6
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x80
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x7
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0xf
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x0
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0xff0
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x4
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0xc
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x1e
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x1f
+#define HDP_XDP_P2P_BAR0__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR0__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR1__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR1__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR2__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR2__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR3__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR3__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR4__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR4__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR5__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR5__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR6__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR6__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR7__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR7__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14
+#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffff
+#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0
+#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x3ffffff
+#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0
+#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x3ffff
+#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0
+#define HDP_XDP_STICKY__STICKY_STS_MASK 0xffff
+#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0
+#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000
+#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10
+#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0xff
+#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0
+#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0xff00
+#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8
+#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0xff0000
+#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10
+#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000
+#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18
+#define HDP_XDP_DBG_ADDR__STS_MASK 0xffff
+#define HDP_XDP_DBG_ADDR__STS__SHIFT 0x0
+#define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000
+#define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x10
+#define HDP_XDP_DBG_DATA__STS_MASK 0xffff
+#define HDP_XDP_DBG_DATA__STS__SHIFT 0x0
+#define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000
+#define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x10
+#define HDP_XDP_DBG_MASK__STS_MASK 0xffff
+#define HDP_XDP_DBG_MASK__STS__SHIFT 0x0
+#define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000
+#define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x10
+#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0xf
+#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0
+#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0xf0
+#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4
+#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0xf00
+#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8
+#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0xf000
+#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc
+#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0xf0000
+#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10
+#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0xf00000
+#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0xf000000
+#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18
+#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000
+#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c
+
+#endif /* OSS_2_0_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h
new file mode 100644
index 000000000000..ca833d3cc128
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_d.h
@@ -0,0 +1,471 @@
+/*
+ * OSS_2_4 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef OSS_2_4_D_H
+#define OSS_2_4_D_H
+
+#define mmIH_VMID_0_LUT 0xe00
+#define mmIH_VMID_1_LUT 0xe01
+#define mmIH_VMID_2_LUT 0xe02
+#define mmIH_VMID_3_LUT 0xe03
+#define mmIH_VMID_4_LUT 0xe04
+#define mmIH_VMID_5_LUT 0xe05
+#define mmIH_VMID_6_LUT 0xe06
+#define mmIH_VMID_7_LUT 0xe07
+#define mmIH_VMID_8_LUT 0xe08
+#define mmIH_VMID_9_LUT 0xe09
+#define mmIH_VMID_10_LUT 0xe0a
+#define mmIH_VMID_11_LUT 0xe0b
+#define mmIH_VMID_12_LUT 0xe0c
+#define mmIH_VMID_13_LUT 0xe0d
+#define mmIH_VMID_14_LUT 0xe0e
+#define mmIH_VMID_15_LUT 0xe0f
+#define mmIH_RB_CNTL 0xe30
+#define mmIH_RB_BASE 0xe31
+#define mmIH_RB_RPTR 0xe32
+#define mmIH_RB_WPTR 0xe33
+#define mmIH_RB_WPTR_ADDR_HI 0xe34
+#define mmIH_RB_WPTR_ADDR_LO 0xe35
+#define mmIH_CNTL 0xe36
+#define mmIH_LEVEL_STATUS 0xe37
+#define mmIH_STATUS 0xe38
+#define mmIH_PERFMON_CNTL 0xe39
+#define mmIH_PERFCOUNTER0_RESULT 0xe3a
+#define mmIH_PERFCOUNTER1_RESULT 0xe3b
+#define mmIH_DSM_MATCH_VALUE_BIT_31_0 0xe3d
+#define mmIH_DSM_MATCH_VALUE_BIT_63_32 0xe3e
+#define mmIH_DSM_MATCH_VALUE_BIT_95_64 0xe3f
+#define mmIH_DSM_MATCH_FIELD_CONTROL 0xe40
+#define mmIH_DSM_MATCH_DATA_CONTROL 0xe41
+#define mmIH_VERSION 0xe42
+#define mmSEM_MCIF_CONFIG 0xf90
+#define mmSDMA_CONFIG 0xf91
+#define mmSDMA1_CONFIG 0xf92
+#define mmUVD_CONFIG 0xf93
+#define mmVCE_CONFIG 0xf94
+#define mmACP_CONFIG 0xf95
+#define mmCPG_CONFIG 0xf96
+#define mmCPC1_CONFIG 0xf97
+#define mmCPC2_CONFIG 0xf98
+#define mmSEM_STATUS 0xf99
+#define mmSEM_EDC_CONFIG 0xf9a
+#define mmSEM_MAILBOX_CLIENTCONFIG 0xf9b
+#define mmSEM_MAILBOX 0xf9c
+#define mmSEM_MAILBOX_CONTROL 0xf9d
+#define mmSEM_CHICKEN_BITS 0xf9e
+#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0xf9f
+#define mmSRBM_CNTL 0x390
+#define mmSRBM_GFX_CNTL 0x391
+#define mmSRBM_READ_CNTL 0x392
+#define mmSRBM_STATUS2 0x393
+#define mmSRBM_STATUS 0x394
+#define mmSRBM_STATUS3 0x395
+#define mmSRBM_SOFT_RESET 0x398
+#define mmSRBM_DEBUG_CNTL 0x399
+#define mmSRBM_DEBUG_DATA 0x39a
+#define mmSRBM_CHIP_REVISION 0x39b
+#define mmCC_SYS_RB_REDUNDANCY 0x39f
+#define mmCC_SYS_RB_BACKEND_DISABLE 0x3a0
+#define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x3a1
+#define mmSRBM_MC_CLKEN_CNTL 0x3b3
+#define mmSRBM_SYS_CLKEN_CNTL 0x3b4
+#define mmSRBM_VCE_CLKEN_CNTL 0x3b5
+#define mmSRBM_UVD_CLKEN_CNTL 0x3b6
+#define mmSRBM_SDMA_CLKEN_CNTL 0x3b7
+#define mmSRBM_SAM_CLKEN_CNTL 0x3b8
+#define mmSRBM_ISP_CLKEN_CNTL 0x3b9
+#define mmSRBM_DEBUG 0x3a4
+#define mmSRBM_DEBUG_SNAPSHOT 0x3a5
+#define mmSRBM_DEBUG_SNAPSHOT2 0x3ad
+#define mmSRBM_READ_ERROR 0x3a6
+#define mmSRBM_READ_ERROR2 0x3ae
+#define mmSRBM_INT_CNTL 0x3a8
+#define mmSRBM_INT_STATUS 0x3a9
+#define mmSRBM_INT_ACK 0x3aa
+#define mmSRBM_FIREWALL_ERROR_SRC 0x3ab
+#define mmSRBM_FIREWALL_ERROR_ADDR 0x3ac
+#define mmSRBM_DSM_TRIG_CNTL0 0x3af
+#define mmSRBM_DSM_TRIG_CNTL1 0x3b0
+#define mmSRBM_DSM_TRIG_MASK0 0x3b1
+#define mmSRBM_DSM_TRIG_MASK1 0x3b2
+#define mmSRBM_PERFMON_CNTL 0x7c00
+#define mmSRBM_PERFCOUNTER0_SELECT 0x7c01
+#define mmSRBM_PERFCOUNTER1_SELECT 0x7c02
+#define mmSRBM_PERFCOUNTER0_LO 0x7c03
+#define mmSRBM_PERFCOUNTER0_HI 0x7c04
+#define mmSRBM_PERFCOUNTER1_LO 0x7c05
+#define mmSRBM_PERFCOUNTER1_HI 0x7c06
+#define mmSRBM_CAM_INDEX 0xfe34
+#define mmSRBM_CAM_DATA 0xfe35
+#define mmSRBM_MC_DOMAIN_ADDR0 0xfa00
+#define mmSRBM_MC_DOMAIN_ADDR1 0xfa01
+#define mmSRBM_MC_DOMAIN_ADDR2 0xfa02
+#define mmSRBM_MC_DOMAIN_ADDR3 0xfa03
+#define mmSRBM_MC_DOMAIN_ADDR4 0xfa04
+#define mmSRBM_MC_DOMAIN_ADDR5 0xfa05
+#define mmSRBM_MC_DOMAIN_ADDR6 0xfa06
+#define mmSRBM_SYS_DOMAIN_ADDR0 0xfa08
+#define mmSRBM_SYS_DOMAIN_ADDR1 0xfa09
+#define mmSRBM_SYS_DOMAIN_ADDR2 0xfa0a
+#define mmSRBM_SYS_DOMAIN_ADDR3 0xfa0b
+#define mmSRBM_SYS_DOMAIN_ADDR4 0xfa0c
+#define mmSRBM_SYS_DOMAIN_ADDR5 0xfa0d
+#define mmSRBM_SYS_DOMAIN_ADDR6 0xfa0e
+#define mmSRBM_SDMA_DOMAIN_ADDR0 0xfa10
+#define mmSRBM_SDMA_DOMAIN_ADDR1 0xfa11
+#define mmSRBM_SDMA_DOMAIN_ADDR2 0xfa12
+#define mmSRBM_SDMA_DOMAIN_ADDR3 0xfa13
+#define mmSRBM_UVD_DOMAIN_ADDR0 0xfa14
+#define mmSRBM_UVD_DOMAIN_ADDR1 0xfa15
+#define mmSRBM_UVD_DOMAIN_ADDR2 0xfa16
+#define mmSRBM_VCE_DOMAIN_ADDR0 0xfa18
+#define mmSRBM_VCE_DOMAIN_ADDR1 0xfa19
+#define mmSRBM_VCE_DOMAIN_ADDR2 0xfa1a
+#define mmSRBM_SAM_DOMAIN_ADDR0 0xfa1c
+#define mmSRBM_SAM_DOMAIN_ADDR1 0xfa1d
+#define mmSRBM_SAM_DOMAIN_ADDR2 0xfa1e
+#define mmSRBM_ISP_DOMAIN_ADDR0 0xfa20
+#define mmSRBM_ISP_DOMAIN_ADDR1 0xfa21
+#define mmSRBM_ISP_DOMAIN_ADDR2 0xfa22
+#define mmSYS_GRBM_GFX_INDEX_SELECT 0xfa2c
+#define mmSYS_GRBM_GFX_INDEX_DATA 0xfa2d
+#define mmSRBM_GFX_CNTL_SELECT 0xfa2e
+#define mmSRBM_GFX_CNTL_DATA 0xfa2f
+#define mmSRBM_VF_ENABLE 0xfa30
+#define mmSRBM_VIRT_CNTL 0xfa31
+#define mmSRBM_VIRT_RESET_REQ 0xfa32
+#define mmSDMA0_UCODE_ADDR 0x3400
+#define mmSDMA0_UCODE_DATA 0x3401
+#define mmSDMA0_POWER_CNTL 0x3402
+#define mmSDMA0_CLK_CTRL 0x3403
+#define mmSDMA0_CNTL 0x3404
+#define mmSDMA0_CHICKEN_BITS 0x3405
+#define mmSDMA0_TILING_CONFIG 0x3406
+#define mmSDMA0_HASH 0x3407
+#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409
+#define mmSDMA0_RB_RPTR_FETCH 0x340a
+#define mmSDMA0_IB_OFFSET_FETCH 0x340b
+#define mmSDMA0_PROGRAM 0x340c
+#define mmSDMA0_STATUS_REG 0x340d
+#define mmSDMA0_STATUS1_REG 0x340e
+#define mmSDMA0_PERFMON_CNTL 0x9000
+#define mmSDMA0_PERFCOUNTER0_RESULT 0x9001
+#define mmSDMA0_PERFCOUNTER1_RESULT 0x9002
+#define mmSDMA0_F32_CNTL 0x3412
+#define mmSDMA0_FREEZE 0x3413
+#define mmSDMA0_PHASE0_QUANTUM 0x3414
+#define mmSDMA0_PHASE1_QUANTUM 0x3415
+#define mmSDMA_POWER_GATING 0x3416
+#define mmSDMA_PGFSM_CONFIG 0x3417
+#define mmSDMA_PGFSM_WRITE 0x3418
+#define mmSDMA_PGFSM_READ 0x3419
+#define mmSDMA0_EDC_CONFIG 0x341a
+#define mmSDMA0_BA_THRESHOLD 0x341b
+#define mmSDMA0_ID 0x341c
+#define mmSDMA0_VERSION 0x341d
+#define mmSDMA0_STATUS2_REG 0x341e
+#define mmSDMA0_GFX_RB_CNTL 0x3480
+#define mmSDMA0_GFX_RB_BASE 0x3481
+#define mmSDMA0_GFX_RB_BASE_HI 0x3482
+#define mmSDMA0_GFX_RB_RPTR 0x3483
+#define mmSDMA0_GFX_RB_WPTR 0x3484
+#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487
+#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x3488
+#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x3489
+#define mmSDMA0_GFX_IB_CNTL 0x348a
+#define mmSDMA0_GFX_IB_RPTR 0x348b
+#define mmSDMA0_GFX_IB_OFFSET 0x348c
+#define mmSDMA0_GFX_IB_BASE_LO 0x348d
+#define mmSDMA0_GFX_IB_BASE_HI 0x348e
+#define mmSDMA0_GFX_IB_SIZE 0x348f
+#define mmSDMA0_GFX_SKIP_CNTL 0x3490
+#define mmSDMA0_GFX_CONTEXT_STATUS 0x3491
+#define mmSDMA0_GFX_CONTEXT_CNTL 0x3493
+#define mmSDMA0_GFX_VIRTUAL_ADDR 0x34a7
+#define mmSDMA0_GFX_APE1_CNTL 0x34a8
+#define mmSDMA0_GFX_WATERMARK 0x34aa
+#define mmSDMA0_GFX_CSA_ADDR_LO 0x34ac
+#define mmSDMA0_GFX_CSA_ADDR_HI 0x34ad
+#define mmSDMA0_GFX_DUMMY_REG 0x34ae
+#define mmSDMA0_GFX_IB_SUB_REMAIN 0x34af
+#define mmSDMA0_GFX_PREEMPT 0x34b0
+#define mmSDMA0_RLC0_RB_CNTL 0x3500
+#define mmSDMA0_RLC0_RB_BASE 0x3501
+#define mmSDMA0_RLC0_RB_BASE_HI 0x3502
+#define mmSDMA0_RLC0_RB_RPTR 0x3503
+#define mmSDMA0_RLC0_RB_WPTR 0x3504
+#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x3506
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x3507
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x3508
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x3509
+#define mmSDMA0_RLC0_IB_CNTL 0x350a
+#define mmSDMA0_RLC0_IB_RPTR 0x350b
+#define mmSDMA0_RLC0_IB_OFFSET 0x350c
+#define mmSDMA0_RLC0_IB_BASE_LO 0x350d
+#define mmSDMA0_RLC0_IB_BASE_HI 0x350e
+#define mmSDMA0_RLC0_IB_SIZE 0x350f
+#define mmSDMA0_RLC0_SKIP_CNTL 0x3510
+#define mmSDMA0_RLC0_CONTEXT_STATUS 0x3511
+#define mmSDMA0_RLC0_DOORBELL 0x3512
+#define mmSDMA0_RLC0_VIRTUAL_ADDR 0x3527
+#define mmSDMA0_RLC0_APE1_CNTL 0x3528
+#define mmSDMA0_RLC0_DOORBELL_LOG 0x3529
+#define mmSDMA0_RLC0_WATERMARK 0x352a
+#define mmSDMA0_RLC0_CSA_ADDR_LO 0x352c
+#define mmSDMA0_RLC0_CSA_ADDR_HI 0x352d
+#define mmSDMA0_RLC0_DUMMY_REG 0x352e
+#define mmSDMA0_RLC0_IB_SUB_REMAIN 0x352f
+#define mmSDMA0_RLC0_PREEMPT 0x3530
+#define mmSDMA0_RLC1_RB_CNTL 0x3580
+#define mmSDMA0_RLC1_RB_BASE 0x3581
+#define mmSDMA0_RLC1_RB_BASE_HI 0x3582
+#define mmSDMA0_RLC1_RB_RPTR 0x3583
+#define mmSDMA0_RLC1_RB_WPTR 0x3584
+#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x3585
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x3586
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x3587
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x3588
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x3589
+#define mmSDMA0_RLC1_IB_CNTL 0x358a
+#define mmSDMA0_RLC1_IB_RPTR 0x358b
+#define mmSDMA0_RLC1_IB_OFFSET 0x358c
+#define mmSDMA0_RLC1_IB_BASE_LO 0x358d
+#define mmSDMA0_RLC1_IB_BASE_HI 0x358e
+#define mmSDMA0_RLC1_IB_SIZE 0x358f
+#define mmSDMA0_RLC1_SKIP_CNTL 0x3590
+#define mmSDMA0_RLC1_CONTEXT_STATUS 0x3591
+#define mmSDMA0_RLC1_DOORBELL 0x3592
+#define mmSDMA0_RLC1_VIRTUAL_ADDR 0x35a7
+#define mmSDMA0_RLC1_APE1_CNTL 0x35a8
+#define mmSDMA0_RLC1_DOORBELL_LOG 0x35a9
+#define mmSDMA0_RLC1_WATERMARK 0x35aa
+#define mmSDMA0_RLC1_CSA_ADDR_LO 0x35ac
+#define mmSDMA0_RLC1_CSA_ADDR_HI 0x35ad
+#define mmSDMA0_RLC1_DUMMY_REG 0x35ae
+#define mmSDMA0_RLC1_IB_SUB_REMAIN 0x35af
+#define mmSDMA0_RLC1_PREEMPT 0x35b0
+#define mmSDMA1_UCODE_ADDR 0x3600
+#define mmSDMA1_UCODE_DATA 0x3601
+#define mmSDMA1_POWER_CNTL 0x3602
+#define mmSDMA1_CLK_CTRL 0x3603
+#define mmSDMA1_CNTL 0x3604
+#define mmSDMA1_CHICKEN_BITS 0x3605
+#define mmSDMA1_TILING_CONFIG 0x3606
+#define mmSDMA1_HASH 0x3607
+#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x3609
+#define mmSDMA1_RB_RPTR_FETCH 0x360a
+#define mmSDMA1_IB_OFFSET_FETCH 0x360b
+#define mmSDMA1_PROGRAM 0x360c
+#define mmSDMA1_STATUS_REG 0x360d
+#define mmSDMA1_STATUS1_REG 0x360e
+#define mmSDMA1_PERFMON_CNTL 0x9010
+#define mmSDMA1_PERFCOUNTER0_RESULT 0x9011
+#define mmSDMA1_PERFCOUNTER1_RESULT 0x9012
+#define mmSDMA1_F32_CNTL 0x3612
+#define mmSDMA1_FREEZE 0x3613
+#define mmSDMA1_PHASE0_QUANTUM 0x3614
+#define mmSDMA1_PHASE1_QUANTUM 0x3615
+#define mmSDMA1_EDC_CONFIG 0x361a
+#define mmSDMA1_BA_THRESHOLD 0x361b
+#define mmSDMA1_ID 0x361c
+#define mmSDMA1_VERSION 0x361d
+#define mmSDMA1_STATUS2_REG 0x361e
+#define mmSDMA1_GFX_RB_CNTL 0x3680
+#define mmSDMA1_GFX_RB_BASE 0x3681
+#define mmSDMA1_GFX_RB_BASE_HI 0x3682
+#define mmSDMA1_GFX_RB_RPTR 0x3683
+#define mmSDMA1_GFX_RB_WPTR 0x3684
+#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x3686
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x3687
+#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x3688
+#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x3689
+#define mmSDMA1_GFX_IB_CNTL 0x368a
+#define mmSDMA1_GFX_IB_RPTR 0x368b
+#define mmSDMA1_GFX_IB_OFFSET 0x368c
+#define mmSDMA1_GFX_IB_BASE_LO 0x368d
+#define mmSDMA1_GFX_IB_BASE_HI 0x368e
+#define mmSDMA1_GFX_IB_SIZE 0x368f
+#define mmSDMA1_GFX_SKIP_CNTL 0x3690
+#define mmSDMA1_GFX_CONTEXT_STATUS 0x3691
+#define mmSDMA1_GFX_CONTEXT_CNTL 0x3693
+#define mmSDMA1_GFX_VIRTUAL_ADDR 0x36a7
+#define mmSDMA1_GFX_APE1_CNTL 0x36a8
+#define mmSDMA1_GFX_WATERMARK 0x36aa
+#define mmSDMA1_GFX_CSA_ADDR_LO 0x36ac
+#define mmSDMA1_GFX_CSA_ADDR_HI 0x36ad
+#define mmSDMA1_GFX_DUMMY_REG 0x36ae
+#define mmSDMA1_GFX_IB_SUB_REMAIN 0x36af
+#define mmSDMA1_GFX_PREEMPT 0x36b0
+#define mmSDMA1_RLC0_RB_CNTL 0x3700
+#define mmSDMA1_RLC0_RB_BASE 0x3701
+#define mmSDMA1_RLC0_RB_BASE_HI 0x3702
+#define mmSDMA1_RLC0_RB_RPTR 0x3703
+#define mmSDMA1_RLC0_RB_WPTR 0x3704
+#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x3706
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x3707
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x3708
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x3709
+#define mmSDMA1_RLC0_IB_CNTL 0x370a
+#define mmSDMA1_RLC0_IB_RPTR 0x370b
+#define mmSDMA1_RLC0_IB_OFFSET 0x370c
+#define mmSDMA1_RLC0_IB_BASE_LO 0x370d
+#define mmSDMA1_RLC0_IB_BASE_HI 0x370e
+#define mmSDMA1_RLC0_IB_SIZE 0x370f
+#define mmSDMA1_RLC0_SKIP_CNTL 0x3710
+#define mmSDMA1_RLC0_CONTEXT_STATUS 0x3711
+#define mmSDMA1_RLC0_DOORBELL 0x3712
+#define mmSDMA1_RLC0_VIRTUAL_ADDR 0x3727
+#define mmSDMA1_RLC0_APE1_CNTL 0x3728
+#define mmSDMA1_RLC0_DOORBELL_LOG 0x3729
+#define mmSDMA1_RLC0_WATERMARK 0x372a
+#define mmSDMA1_RLC0_CSA_ADDR_LO 0x372c
+#define mmSDMA1_RLC0_CSA_ADDR_HI 0x372d
+#define mmSDMA1_RLC0_DUMMY_REG 0x372e
+#define mmSDMA1_RLC0_IB_SUB_REMAIN 0x372f
+#define mmSDMA1_RLC0_PREEMPT 0x3730
+#define mmSDMA1_RLC1_RB_CNTL 0x3780
+#define mmSDMA1_RLC1_RB_BASE 0x3781
+#define mmSDMA1_RLC1_RB_BASE_HI 0x3782
+#define mmSDMA1_RLC1_RB_RPTR 0x3783
+#define mmSDMA1_RLC1_RB_WPTR 0x3784
+#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x3785
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x3786
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x3787
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x3788
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x3789
+#define mmSDMA1_RLC1_IB_CNTL 0x378a
+#define mmSDMA1_RLC1_IB_RPTR 0x378b
+#define mmSDMA1_RLC1_IB_OFFSET 0x378c
+#define mmSDMA1_RLC1_IB_BASE_LO 0x378d
+#define mmSDMA1_RLC1_IB_BASE_HI 0x378e
+#define mmSDMA1_RLC1_IB_SIZE 0x378f
+#define mmSDMA1_RLC1_SKIP_CNTL 0x3790
+#define mmSDMA1_RLC1_CONTEXT_STATUS 0x3791
+#define mmSDMA1_RLC1_DOORBELL 0x3792
+#define mmSDMA1_RLC1_VIRTUAL_ADDR 0x37a7
+#define mmSDMA1_RLC1_APE1_CNTL 0x37a8
+#define mmSDMA1_RLC1_DOORBELL_LOG 0x37a9
+#define mmSDMA1_RLC1_WATERMARK 0x37aa
+#define mmSDMA1_RLC1_CSA_ADDR_LO 0x37ac
+#define mmSDMA1_RLC1_CSA_ADDR_HI 0x37ad
+#define mmSDMA1_RLC1_DUMMY_REG 0x37ae
+#define mmSDMA1_RLC1_IB_SUB_REMAIN 0x37af
+#define mmSDMA1_RLC1_PREEMPT 0x37b0
+#define mmHDP_HOST_PATH_CNTL 0xb00
+#define mmHDP_NONSURFACE_BASE 0xb01
+#define mmHDP_NONSURFACE_INFO 0xb02
+#define mmHDP_NONSURFACE_SIZE 0xb03
+#define mmHDP_NONSURF_FLAGS 0xbc9
+#define mmHDP_NONSURF_FLAGS_CLR 0xbca
+#define mmHDP_SW_SEMAPHORE 0xbcb
+#define mmHDP_DEBUG0 0xbcc
+#define mmHDP_DEBUG1 0xbcd
+#define mmHDP_LAST_SURFACE_HIT 0xbce
+#define mmHDP_TILING_CONFIG 0xbcf
+#define mmHDP_SC_MULTI_CHIP_CNTL 0xbd0
+#define mmHDP_OUTSTANDING_REQ 0xbd1
+#define mmHDP_ADDR_CONFIG 0xbd2
+#define mmHDP_MISC_CNTL 0xbd3
+#define mmHDP_MEM_POWER_LS 0xbd4
+#define mmHDP_NONSURFACE_PREFETCH 0xbd5
+#define mmHDP_MEMIO_CNTL 0xbf6
+#define mmHDP_MEMIO_ADDR 0xbf7
+#define mmHDP_MEMIO_STATUS 0xbf8
+#define mmHDP_MEMIO_WR_DATA 0xbf9
+#define mmHDP_MEMIO_RD_DATA 0xbfa
+#define mmHDP_XDP_DIRECT2HDP_FIRST 0xc00
+#define mmHDP_XDP_D2H_FLUSH 0xc01
+#define mmHDP_XDP_D2H_BAR_UPDATE 0xc02
+#define mmHDP_XDP_D2H_RSVD_3 0xc03
+#define mmHDP_XDP_D2H_RSVD_4 0xc04
+#define mmHDP_XDP_D2H_RSVD_5 0xc05
+#define mmHDP_XDP_D2H_RSVD_6 0xc06
+#define mmHDP_XDP_D2H_RSVD_7 0xc07
+#define mmHDP_XDP_D2H_RSVD_8 0xc08
+#define mmHDP_XDP_D2H_RSVD_9 0xc09
+#define mmHDP_XDP_D2H_RSVD_10 0xc0a
+#define mmHDP_XDP_D2H_RSVD_11 0xc0b
+#define mmHDP_XDP_D2H_RSVD_12 0xc0c
+#define mmHDP_XDP_D2H_RSVD_13 0xc0d
+#define mmHDP_XDP_D2H_RSVD_14 0xc0e
+#define mmHDP_XDP_D2H_RSVD_15 0xc0f
+#define mmHDP_XDP_D2H_RSVD_16 0xc10
+#define mmHDP_XDP_D2H_RSVD_17 0xc11
+#define mmHDP_XDP_D2H_RSVD_18 0xc12
+#define mmHDP_XDP_D2H_RSVD_19 0xc13
+#define mmHDP_XDP_D2H_RSVD_20 0xc14
+#define mmHDP_XDP_D2H_RSVD_21 0xc15
+#define mmHDP_XDP_D2H_RSVD_22 0xc16
+#define mmHDP_XDP_D2H_RSVD_23 0xc17
+#define mmHDP_XDP_D2H_RSVD_24 0xc18
+#define mmHDP_XDP_D2H_RSVD_25 0xc19
+#define mmHDP_XDP_D2H_RSVD_26 0xc1a
+#define mmHDP_XDP_D2H_RSVD_27 0xc1b
+#define mmHDP_XDP_D2H_RSVD_28 0xc1c
+#define mmHDP_XDP_D2H_RSVD_29 0xc1d
+#define mmHDP_XDP_D2H_RSVD_30 0xc1e
+#define mmHDP_XDP_D2H_RSVD_31 0xc1f
+#define mmHDP_XDP_D2H_RSVD_32 0xc20
+#define mmHDP_XDP_D2H_RSVD_33 0xc21
+#define mmHDP_XDP_D2H_RSVD_34 0xc22
+#define mmHDP_XDP_DIRECT2HDP_LAST 0xc23
+#define mmHDP_XDP_P2P_BAR_CFG 0xc24
+#define mmHDP_XDP_P2P_MBX_OFFSET 0xc25
+#define mmHDP_XDP_P2P_MBX_ADDR0 0xc26
+#define mmHDP_XDP_P2P_MBX_ADDR1 0xc27
+#define mmHDP_XDP_P2P_MBX_ADDR2 0xc28
+#define mmHDP_XDP_P2P_MBX_ADDR3 0xc29
+#define mmHDP_XDP_P2P_MBX_ADDR4 0xc2a
+#define mmHDP_XDP_P2P_MBX_ADDR5 0xc2b
+#define mmHDP_XDP_P2P_MBX_ADDR6 0xc2c
+#define mmHDP_XDP_HDP_MBX_MC_CFG 0xc2d
+#define mmHDP_XDP_HDP_MC_CFG 0xc2e
+#define mmHDP_XDP_HST_CFG 0xc2f
+#define mmHDP_XDP_SID_CFG 0xc30
+#define mmHDP_XDP_HDP_IPH_CFG 0xc31
+#define mmHDP_XDP_SRBM_CFG 0xc32
+#define mmHDP_XDP_CGTT_BLK_CTRL 0xc33
+#define mmHDP_XDP_P2P_BAR0 0xc34
+#define mmHDP_XDP_P2P_BAR1 0xc35
+#define mmHDP_XDP_P2P_BAR2 0xc36
+#define mmHDP_XDP_P2P_BAR3 0xc37
+#define mmHDP_XDP_P2P_BAR4 0xc38
+#define mmHDP_XDP_P2P_BAR5 0xc39
+#define mmHDP_XDP_P2P_BAR6 0xc3a
+#define mmHDP_XDP_P2P_BAR7 0xc3b
+#define mmHDP_XDP_FLUSH_ARMED_STS 0xc3c
+#define mmHDP_XDP_FLUSH_CNTR0_STS 0xc3d
+#define mmHDP_XDP_BUSY_STS 0xc3e
+#define mmHDP_XDP_STICKY 0xc3f
+#define mmHDP_XDP_CHKN 0xc40
+#define mmHDP_XDP_DBG_ADDR 0xc41
+#define mmHDP_XDP_DBG_DATA 0xc42
+#define mmHDP_XDP_DBG_MASK 0xc43
+#define mmHDP_XDP_BARS_ADDR_39_36 0xc44
+
+#endif /* OSS_2_4_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_enum.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_enum.h
new file mode 100644
index 000000000000..37adf0df0fd3
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_enum.h
@@ -0,0 +1,1340 @@
+/*
+ * OSS_2_4 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef OSS_2_4_ENUM_H
+#define OSS_2_4_ENUM_H
+
+typedef enum IH_CLIENT_ID {
+ DC_IH_SRC_ID_START = 0x1,
+ DC_IH_SRC_ID_END = 0x1f,
+ VGA_IH_SRC_ID_START = 0x20,
+ VGA_IH_SRC_ID_END = 0x27,
+ CAP_IH_SRC_ID_START = 0x28,
+ CAP_IH_SRC_ID_END = 0x2f,
+ VIP_IH_SRC_ID_START = 0x30,
+ VIP_IH_SRC_ID_END = 0x3f,
+ ROM_IH_SRC_ID_START = 0x40,
+ ROM_IH_SRC_ID_END = 0x5d,
+ BIF_IH_SRC_ID_START = 0x5e,
+ SAM_IH_SRC_ID_START = 0x5f,
+ SRBM_IH_SRC_ID_START = 0x60,
+ SRBM_IH_SRC_ID_END = 0x67,
+ UVD_IH_SRC_ID_START = 0x72,
+ UVD_IH_SRC_ID_END = 0x85,
+ VMC_IH_SRC_ID_START = 0x86,
+ VMC_IH_SRC_ID_END = 0x8f,
+ RLC_IH_SRC_ID_START = 0x90,
+ RLC_IH_SRC_ID_END = 0xf3,
+ PDMA_IH_SRC_ID_START = 0xf4,
+ PDMA_IH_SRC_ID_END = 0xf7,
+ CG_IH_SRC_ID_START = 0xf8,
+ CG_IH_SRC_ID_END = 0xff,
+} IH_CLIENT_ID;
+typedef enum IH_PERF_SEL {
+ IH_PERF_SEL_CYCLE = 0x0,
+ IH_PERF_SEL_IDLE = 0x1,
+ IH_PERF_SEL_INPUT_IDLE = 0x2,
+ IH_PERF_SEL_CLIENT0_IH_STALL = 0x3,
+ IH_PERF_SEL_CLIENT1_IH_STALL = 0x4,
+ IH_PERF_SEL_CLIENT2_IH_STALL = 0x5,
+ IH_PERF_SEL_CLIENT3_IH_STALL = 0x6,
+ IH_PERF_SEL_CLIENT4_IH_STALL = 0x7,
+ IH_PERF_SEL_CLIENT5_IH_STALL = 0x8,
+ IH_PERF_SEL_CLIENT6_IH_STALL = 0x9,
+ IH_PERF_SEL_CLIENT7_IH_STALL = 0xa,
+ IH_PERF_SEL_RB_IDLE = 0xb,
+ IH_PERF_SEL_RB_FULL = 0xc,
+ IH_PERF_SEL_RB_OVERFLOW = 0xd,
+ IH_PERF_SEL_RB_WPTR_WRITEBACK = 0xe,
+ IH_PERF_SEL_RB_WPTR_WRAP = 0xf,
+ IH_PERF_SEL_RB_RPTR_WRAP = 0x10,
+ IH_PERF_SEL_MC_WR_IDLE = 0x11,
+ IH_PERF_SEL_MC_WR_COUNT = 0x12,
+ IH_PERF_SEL_MC_WR_STALL = 0x13,
+ IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x14,
+ IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x15,
+ IH_PERF_SEL_BIF_RISING = 0x16,
+ IH_PERF_SEL_BIF_FALLING = 0x17,
+ IH_PERF_SEL_CLIENT8_IH_STALL = 0x18,
+ IH_PERF_SEL_CLIENT9_IH_STALL = 0x19,
+ IH_PERF_SEL_CLIENT10_IH_STALL = 0x1a,
+ IH_PERF_SEL_CLIENT11_IH_STALL = 0x1b,
+ IH_PERF_SEL_CLIENT12_IH_STALL = 0x1c,
+ IH_PERF_SEL_CLIENT13_IH_STALL = 0x1d,
+ IH_PERF_SEL_CLIENT14_IH_STALL = 0x1e,
+ IH_PERF_SEL_CLIENT15_IH_STALL = 0x1f,
+ IH_PERF_SEL_CLIENT16_IH_STALL = 0x20,
+ IH_PERF_SEL_CLIENT17_IH_STALL = 0x21,
+ IH_PERF_SEL_CLIENT18_IH_STALL = 0x22,
+ IH_PERF_SEL_CLIENT19_IH_STALL = 0x23,
+ IH_PERF_SEL_CLIENT20_IH_STALL = 0x24,
+ IH_PERF_SEL_CLIENT21_IH_STALL = 0x25,
+} IH_PERF_SEL;
+typedef enum SRBM_PERFCOUNT1_SEL {
+ SRBM_PERF_SEL_COUNT = 0x0,
+ SRBM_PERF_SEL_BIF_BUSY = 0x1,
+ SRBM_PERF_SEL_SDMA0_BUSY = 0x3,
+ SRBM_PERF_SEL_IH_BUSY = 0x4,
+ SRBM_PERF_SEL_MCB_BUSY = 0x5,
+ SRBM_PERF_SEL_MCB_NON_DISPLAY_BUSY = 0x6,
+ SRBM_PERF_SEL_MCC_BUSY = 0x7,
+ SRBM_PERF_SEL_MCD_BUSY = 0x8,
+ SRBM_PERF_SEL_CHUB_BUSY = 0x9,
+ SRBM_PERF_SEL_SEM_BUSY = 0xa,
+ SRBM_PERF_SEL_UVD_BUSY = 0xb,
+ SRBM_PERF_SEL_VMC_BUSY = 0xc,
+ SRBM_PERF_SEL_XSP_BUSY = 0xd,
+ SRBM_PERF_SEL_SDMA1_BUSY = 0xe,
+ SRBM_PERF_SEL_SAMMSP_BUSY = 0xf,
+ SRBM_PERF_SEL_VCE0_BUSY = 0x10,
+ SRBM_PERF_SEL_XDMA_BUSY = 0x11,
+ SRBM_PERF_SEL_ACP_BUSY = 0x12,
+ SRBM_PERF_SEL_SDMA2_BUSY = 0x13,
+ SRBM_PERF_SEL_SDMA3_BUSY = 0x14,
+ SRBM_PERF_SEL_SAMSCP_BUSY = 0x15,
+ SRBM_PERF_SEL_VMC1_BUSY = 0x16,
+ SRBM_PERF_SEL_ISP_BUSY = 0x17,
+ SRBM_PERF_SEL_VCE1_BUSY = 0x18,
+ SRBM_PERF_SEL_GCATCL2_BUSY = 0x19,
+ SRBM_PERF_SEL_OSATCL2_BUSY = 0x1a,
+} SRBM_PERFCOUNT1_SEL;
+typedef enum SYS_GRBM_GFX_INDEX_SEL {
+ GRBM_GFX_INDEX_BIF = 0x0,
+ GRBM_GFX_INDEX_SDMA0 = 0x1,
+ GRBM_GFX_INDEX_SDMA1 = 0x2,
+ RESEVERED0 = 0x3,
+ GRBM_GFX_INDEX_UVD = 0x4,
+ GRBM_GFX_INDEX_VCE0 = 0x5,
+ GRBM_GFX_INDEX_VCE1 = 0x6,
+ GRBM_GFX_INDEX_ACP = 0x7,
+ GRBM_GFX_INDEX_SMU = 0x8,
+ GRBM_GFX_INDEX_SAMMSP = 0x9,
+ GRBM_GFX_INDEX_SAMSCP = 0xa,
+ GRBM_GFX_INDEX_ISP = 0xb,
+ GRBM_GFX_INDEX_TST = 0xc,
+ GRBM_GFX_INDEX_SDMA2 = 0xd,
+ GRBM_GFX_INDEX_SDMA3 = 0xe,
+} SYS_GRBM_GFX_INDEX_SEL;
+typedef enum SRBM_GFX_CNTL_SEL {
+ SRBM_GFX_CNTL_BIF = 0x0,
+ SRBM_GFX_CNTL_SDMA0 = 0x1,
+ SRBM_GFX_CNTL_SDMA1 = 0x2,
+ SRBM_GFX_CNTL_GRBM = 0x3,
+ SRBM_GFX_CNTL_UVD = 0x4,
+ SRBM_GFX_CNTL_VCE0 = 0x5,
+ SRBM_GFX_CNTL_VCE1 = 0x6,
+ SRBM_GFX_CNTL_ACP = 0x7,
+ SRBM_GFX_CNTL_SMU = 0x8,
+ SRBM_GFX_CNTL_SAMMSP = 0x9,
+ SRBM_GFX_CNTL_SAMSCP = 0xa,
+ SRBM_GFX_CNTL_ISP = 0xb,
+ SRBM_GFX_CNTL_TST = 0xc,
+ SRBM_GFX_CNTL_SDMA2 = 0xd,
+ SRBM_GFX_CNTL_SDMA3 = 0xe,
+} SRBM_GFX_CNTL_SEL;
+typedef enum SDMA_PERF_SEL {
+ SDMA_PERF_SEL_CYCLE = 0x0,
+ SDMA_PERF_SEL_IDLE = 0x1,
+ SDMA_PERF_SEL_REG_IDLE = 0x2,
+ SDMA_PERF_SEL_RB_EMPTY = 0x3,
+ SDMA_PERF_SEL_RB_FULL = 0x4,
+ SDMA_PERF_SEL_RB_WPTR_WRAP = 0x5,
+ SDMA_PERF_SEL_RB_RPTR_WRAP = 0x6,
+ SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x7,
+ SDMA_PERF_SEL_RB_RPTR_WB = 0x8,
+ SDMA_PERF_SEL_RB_CMD_IDLE = 0x9,
+ SDMA_PERF_SEL_RB_CMD_FULL = 0xa,
+ SDMA_PERF_SEL_IB_CMD_IDLE = 0xb,
+ SDMA_PERF_SEL_IB_CMD_FULL = 0xc,
+ SDMA_PERF_SEL_EX_IDLE = 0xd,
+ SDMA_PERF_SEL_SRBM_REG_SEND = 0xe,
+ SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0xf,
+ SDMA_PERF_SEL_MC_WR_IDLE = 0x10,
+ SDMA_PERF_SEL_MC_WR_COUNT = 0x11,
+ SDMA_PERF_SEL_MC_RD_IDLE = 0x12,
+ SDMA_PERF_SEL_MC_RD_COUNT = 0x13,
+ SDMA_PERF_SEL_MC_RD_RET_STALL = 0x14,
+ SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x15,
+ SDMA_PERF_SEL_SEM_IDLE = 0x18,
+ SDMA_PERF_SEL_SEM_REQ_STALL = 0x19,
+ SDMA_PERF_SEL_SEM_REQ_COUNT = 0x1a,
+ SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x1b,
+ SDMA_PERF_SEL_SEM_RESP_FAIL = 0x1c,
+ SDMA_PERF_SEL_SEM_RESP_PASS = 0x1d,
+ SDMA_PERF_SEL_INT_IDLE = 0x1e,
+ SDMA_PERF_SEL_INT_REQ_STALL = 0x1f,
+ SDMA_PERF_SEL_INT_REQ_COUNT = 0x20,
+ SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x21,
+ SDMA_PERF_SEL_INT_RESP_RETRY = 0x22,
+ SDMA_PERF_SEL_NUM_PACKET = 0x23,
+ SDMA_PERF_SEL_CE_WREQ_IDLE = 0x25,
+ SDMA_PERF_SEL_CE_WR_IDLE = 0x26,
+ SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x27,
+ SDMA_PERF_SEL_CE_RREQ_IDLE = 0x28,
+ SDMA_PERF_SEL_CE_OUT_IDLE = 0x29,
+ SDMA_PERF_SEL_CE_IN_IDLE = 0x2a,
+ SDMA_PERF_SEL_CE_DST_IDLE = 0x2b,
+ SDMA_PERF_SEL_CE_AFIFO_FULL = 0x2e,
+ SDMA_PERF_SEL_CE_INFO_FULL = 0x31,
+ SDMA_PERF_SEL_CE_INFO1_FULL = 0x32,
+ SDMA_PERF_SEL_CE_RD_STALL = 0x33,
+ SDMA_PERF_SEL_CE_WR_STALL = 0x34,
+ SDMA_PERF_SEL_GFX_SELECT = 0x35,
+ SDMA_PERF_SEL_RLC0_SELECT = 0x36,
+ SDMA_PERF_SEL_RLC1_SELECT = 0x37,
+ SDMA_PERF_SEL_CTX_CHANGE = 0x38,
+ SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x39,
+ SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x3a,
+ SDMA_PERF_SEL_DOORBELL = 0x3b,
+ SDMA_PERF_SEL_RD_BA_RTR = 0x3c,
+ SDMA_PERF_SEL_WR_BA_RTR = 0x3d,
+} SDMA_PERF_SEL;
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0x0,
+ ENDIAN_8IN16 = 0x1,
+ ENDIAN_8IN32 = 0x2,
+ ENDIAN_8IN64 = 0x3,
+} SurfaceEndian;
+typedef enum ArrayMode {
+ ARRAY_LINEAR_GENERAL = 0x0,
+ ARRAY_LINEAR_ALIGNED = 0x1,
+ ARRAY_1D_TILED_THIN1 = 0x2,
+ ARRAY_1D_TILED_THICK = 0x3,
+ ARRAY_2D_TILED_THIN1 = 0x4,
+ ARRAY_PRT_TILED_THIN1 = 0x5,
+ ARRAY_PRT_2D_TILED_THIN1 = 0x6,
+ ARRAY_2D_TILED_THICK = 0x7,
+ ARRAY_2D_TILED_XTHICK = 0x8,
+ ARRAY_PRT_TILED_THICK = 0x9,
+ ARRAY_PRT_2D_TILED_THICK = 0xa,
+ ARRAY_PRT_3D_TILED_THIN1 = 0xb,
+ ARRAY_3D_TILED_THIN1 = 0xc,
+ ARRAY_3D_TILED_THICK = 0xd,
+ ARRAY_3D_TILED_XTHICK = 0xe,
+ ARRAY_PRT_3D_TILED_THICK = 0xf,
+} ArrayMode;
+typedef enum PipeTiling {
+ CONFIG_1_PIPE = 0x0,
+ CONFIG_2_PIPE = 0x1,
+ CONFIG_4_PIPE = 0x2,
+ CONFIG_8_PIPE = 0x3,
+} PipeTiling;
+typedef enum BankTiling {
+ CONFIG_4_BANK = 0x0,
+ CONFIG_8_BANK = 0x1,
+} BankTiling;
+typedef enum GroupInterleave {
+ CONFIG_256B_GROUP = 0x0,
+ CONFIG_512B_GROUP = 0x1,
+} GroupInterleave;
+typedef enum RowTiling {
+ CONFIG_1KB_ROW = 0x0,
+ CONFIG_2KB_ROW = 0x1,
+ CONFIG_4KB_ROW = 0x2,
+ CONFIG_8KB_ROW = 0x3,
+ CONFIG_1KB_ROW_OPT = 0x4,
+ CONFIG_2KB_ROW_OPT = 0x5,
+ CONFIG_4KB_ROW_OPT = 0x6,
+ CONFIG_8KB_ROW_OPT = 0x7,
+} RowTiling;
+typedef enum BankSwapBytes {
+ CONFIG_128B_SWAPS = 0x0,
+ CONFIG_256B_SWAPS = 0x1,
+ CONFIG_512B_SWAPS = 0x2,
+ CONFIG_1KB_SWAPS = 0x3,
+} BankSwapBytes;
+typedef enum SampleSplitBytes {
+ CONFIG_1KB_SPLIT = 0x0,
+ CONFIG_2KB_SPLIT = 0x1,
+ CONFIG_4KB_SPLIT = 0x2,
+ CONFIG_8KB_SPLIT = 0x3,
+} SampleSplitBytes;
+typedef enum NumPipes {
+ ADDR_CONFIG_1_PIPE = 0x0,
+ ADDR_CONFIG_2_PIPE = 0x1,
+ ADDR_CONFIG_4_PIPE = 0x2,
+ ADDR_CONFIG_8_PIPE = 0x3,
+} NumPipes;
+typedef enum PipeInterleaveSize {
+ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
+ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
+} PipeInterleaveSize;
+typedef enum BankInterleaveSize {
+ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
+ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
+ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
+ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
+} BankInterleaveSize;
+typedef enum NumShaderEngines {
+ ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
+ ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
+} NumShaderEngines;
+typedef enum ShaderEngineTileSize {
+ ADDR_CONFIG_SE_TILE_16 = 0x0,
+ ADDR_CONFIG_SE_TILE_32 = 0x1,
+} ShaderEngineTileSize;
+typedef enum NumGPUs {
+ ADDR_CONFIG_1_GPU = 0x0,
+ ADDR_CONFIG_2_GPU = 0x1,
+ ADDR_CONFIG_4_GPU = 0x2,
+} NumGPUs;
+typedef enum MultiGPUTileSize {
+ ADDR_CONFIG_GPU_TILE_16 = 0x0,
+ ADDR_CONFIG_GPU_TILE_32 = 0x1,
+ ADDR_CONFIG_GPU_TILE_64 = 0x2,
+ ADDR_CONFIG_GPU_TILE_128 = 0x3,
+} MultiGPUTileSize;
+typedef enum RowSize {
+ ADDR_CONFIG_1KB_ROW = 0x0,
+ ADDR_CONFIG_2KB_ROW = 0x1,
+ ADDR_CONFIG_4KB_ROW = 0x2,
+} RowSize;
+typedef enum NumLowerPipes {
+ ADDR_CONFIG_1_LOWER_PIPES = 0x0,
+ ADDR_CONFIG_2_LOWER_PIPES = 0x1,
+} NumLowerPipes;
+typedef enum DebugBlockId {
+ DBG_CLIENT_BLKID_RESERVED = 0x0,
+ DBG_CLIENT_BLKID_dbg = 0x1,
+ DBG_CLIENT_BLKID_uvdu_0 = 0x2,
+ DBG_CLIENT_BLKID_uvdu_1 = 0x3,
+ DBG_CLIENT_BLKID_uvdu_2 = 0x4,
+ DBG_CLIENT_BLKID_uvdu_3 = 0x5,
+ DBG_CLIENT_BLKID_uvdu_4 = 0x6,
+ DBG_CLIENT_BLKID_uvdu_5 = 0x7,
+ DBG_CLIENT_BLKID_uvdu_6 = 0x8,
+ DBG_CLIENT_BLKID_uvdb_0 = 0x9,
+ DBG_CLIENT_BLKID_uvdc_0 = 0xa,
+ DBG_CLIENT_BLKID_uvdc_1 = 0xb,
+ DBG_CLIENT_BLKID_uvdf_0 = 0xc,
+ DBG_CLIENT_BLKID_uvdf_1 = 0xd,
+ DBG_CLIENT_BLKID_uvdm_0 = 0xe,
+ DBG_CLIENT_BLKID_uvdm_1 = 0xf,
+ DBG_CLIENT_BLKID_uvdm_2 = 0x10,
+ DBG_CLIENT_BLKID_uvdm_3 = 0x11,
+ DBG_CLIENT_BLKID_vcea_0 = 0x12,
+ DBG_CLIENT_BLKID_vcea_1 = 0x13,
+ DBG_CLIENT_BLKID_vcea_2 = 0x14,
+ DBG_CLIENT_BLKID_vcea_3 = 0x15,
+ DBG_CLIENT_BLKID_vceb_0 = 0x16,
+ DBG_CLIENT_BLKID_vcec_0 = 0x17,
+ DBG_CLIENT_BLKID_dco = 0x18,
+ DBG_CLIENT_BLKID_xdma = 0x19,
+ DBG_CLIENT_BLKID_dci_pg = 0x1a,
+ DBG_CLIENT_BLKID_smu_0 = 0x1b,
+ DBG_CLIENT_BLKID_smu_1 = 0x1c,
+ DBG_CLIENT_BLKID_smu_2 = 0x1d,
+ DBG_CLIENT_BLKID_gck = 0x1e,
+ DBG_CLIENT_BLKID_tmonw0 = 0x1f,
+ DBG_CLIENT_BLKID_tmonw1 = 0x20,
+ DBG_CLIENT_BLKID_grbm = 0x21,
+ DBG_CLIENT_BLKID_rlc = 0x22,
+ DBG_CLIENT_BLKID_ds0 = 0x23,
+ DBG_CLIENT_BLKID_cpg_0 = 0x24,
+ DBG_CLIENT_BLKID_cpg_1 = 0x25,
+ DBG_CLIENT_BLKID_cpc_0 = 0x26,
+ DBG_CLIENT_BLKID_cpc_1 = 0x27,
+ DBG_CLIENT_BLKID_cpf_0 = 0x28,
+ DBG_CLIENT_BLKID_cpf_1 = 0x29,
+ DBG_CLIENT_BLKID_scf0 = 0x2a,
+ DBG_CLIENT_BLKID_scf1 = 0x2b,
+ DBG_CLIENT_BLKID_scf2 = 0x2c,
+ DBG_CLIENT_BLKID_scf3 = 0x2d,
+ DBG_CLIENT_BLKID_pc0 = 0x2e,
+ DBG_CLIENT_BLKID_pc1 = 0x2f,
+ DBG_CLIENT_BLKID_pc2 = 0x30,
+ DBG_CLIENT_BLKID_pc3 = 0x31,
+ DBG_CLIENT_BLKID_vgt0 = 0x32,
+ DBG_CLIENT_BLKID_vgt1 = 0x33,
+ DBG_CLIENT_BLKID_vgt2 = 0x34,
+ DBG_CLIENT_BLKID_vgt3 = 0x35,
+ DBG_CLIENT_BLKID_sx00 = 0x36,
+ DBG_CLIENT_BLKID_sx10 = 0x37,
+ DBG_CLIENT_BLKID_sx20 = 0x38,
+ DBG_CLIENT_BLKID_sx30 = 0x39,
+ DBG_CLIENT_BLKID_cb001 = 0x3a,
+ DBG_CLIENT_BLKID_cb200 = 0x3b,
+ DBG_CLIENT_BLKID_cb201 = 0x3c,
+ DBG_CLIENT_BLKID_cbr0 = 0x3d,
+ DBG_CLIENT_BLKID_cb000 = 0x3e,
+ DBG_CLIENT_BLKID_cb101 = 0x3f,
+ DBG_CLIENT_BLKID_cb300 = 0x40,
+ DBG_CLIENT_BLKID_cb301 = 0x41,
+ DBG_CLIENT_BLKID_cbr1 = 0x42,
+ DBG_CLIENT_BLKID_cb100 = 0x43,
+ DBG_CLIENT_BLKID_ia0 = 0x44,
+ DBG_CLIENT_BLKID_ia1 = 0x45,
+ DBG_CLIENT_BLKID_bci0 = 0x46,
+ DBG_CLIENT_BLKID_bci1 = 0x47,
+ DBG_CLIENT_BLKID_bci2 = 0x48,
+ DBG_CLIENT_BLKID_bci3 = 0x49,
+ DBG_CLIENT_BLKID_pa0 = 0x4a,
+ DBG_CLIENT_BLKID_pa1 = 0x4b,
+ DBG_CLIENT_BLKID_spim0 = 0x4c,
+ DBG_CLIENT_BLKID_spim1 = 0x4d,
+ DBG_CLIENT_BLKID_spim2 = 0x4e,
+ DBG_CLIENT_BLKID_spim3 = 0x4f,
+ DBG_CLIENT_BLKID_sdma = 0x50,
+ DBG_CLIENT_BLKID_ih = 0x51,
+ DBG_CLIENT_BLKID_sem = 0x52,
+ DBG_CLIENT_BLKID_srbm = 0x53,
+ DBG_CLIENT_BLKID_hdp = 0x54,
+ DBG_CLIENT_BLKID_acp_0 = 0x55,
+ DBG_CLIENT_BLKID_acp_1 = 0x56,
+ DBG_CLIENT_BLKID_sam = 0x57,
+ DBG_CLIENT_BLKID_mcc0 = 0x58,
+ DBG_CLIENT_BLKID_mcc1 = 0x59,
+ DBG_CLIENT_BLKID_mcc2 = 0x5a,
+ DBG_CLIENT_BLKID_mcc3 = 0x5b,
+ DBG_CLIENT_BLKID_mcd0 = 0x5c,
+ DBG_CLIENT_BLKID_mcd1 = 0x5d,
+ DBG_CLIENT_BLKID_mcd2 = 0x5e,
+ DBG_CLIENT_BLKID_mcd3 = 0x5f,
+ DBG_CLIENT_BLKID_mcb = 0x60,
+ DBG_CLIENT_BLKID_vmc = 0x61,
+ DBG_CLIENT_BLKID_gmcon = 0x62,
+ DBG_CLIENT_BLKID_gdc_0 = 0x63,
+ DBG_CLIENT_BLKID_gdc_1 = 0x64,
+ DBG_CLIENT_BLKID_gdc_2 = 0x65,
+ DBG_CLIENT_BLKID_gdc_3 = 0x66,
+ DBG_CLIENT_BLKID_gdc_4 = 0x67,
+ DBG_CLIENT_BLKID_gdc_5 = 0x68,
+ DBG_CLIENT_BLKID_gdc_6 = 0x69,
+ DBG_CLIENT_BLKID_gdc_7 = 0x6a,
+ DBG_CLIENT_BLKID_gdc_8 = 0x6b,
+ DBG_CLIENT_BLKID_gdc_9 = 0x6c,
+ DBG_CLIENT_BLKID_gdc_10 = 0x6d,
+ DBG_CLIENT_BLKID_gdc_11 = 0x6e,
+ DBG_CLIENT_BLKID_gdc_12 = 0x6f,
+ DBG_CLIENT_BLKID_gdc_13 = 0x70,
+ DBG_CLIENT_BLKID_gdc_14 = 0x71,
+ DBG_CLIENT_BLKID_gdc_15 = 0x72,
+ DBG_CLIENT_BLKID_gdc_16 = 0x73,
+ DBG_CLIENT_BLKID_gdc_17 = 0x74,
+ DBG_CLIENT_BLKID_gdc_18 = 0x75,
+ DBG_CLIENT_BLKID_gdc_19 = 0x76,
+ DBG_CLIENT_BLKID_gdc_20 = 0x77,
+ DBG_CLIENT_BLKID_gdc_21 = 0x78,
+ DBG_CLIENT_BLKID_gdc_22 = 0x79,
+ DBG_CLIENT_BLKID_gdc_23 = 0x7a,
+ DBG_CLIENT_BLKID_gdc_24 = 0x7b,
+ DBG_CLIENT_BLKID_gdc_25 = 0x7c,
+ DBG_CLIENT_BLKID_gdc_26 = 0x7d,
+ DBG_CLIENT_BLKID_gdc_27 = 0x7e,
+ DBG_CLIENT_BLKID_gdc_28 = 0x7f,
+ DBG_CLIENT_BLKID_wd = 0x80,
+ DBG_CLIENT_BLKID_sdma_0 = 0x81,
+ DBG_CLIENT_BLKID_sdma_1 = 0x82,
+ DBG_CLIENT_BLKID_sammsp = 0x83,
+ DBG_CLIENT_BLKID_dci_0 = 0x84,
+ DBG_CLIENT_BLKID_dccg0_0 = 0x85,
+ DBG_CLIENT_BLKID_dcfe01_0 = 0x86,
+ DBG_CLIENT_BLKID_dcfe02_0 = 0x87,
+ DBG_CLIENT_BLKID_dcfe03_0 = 0x88,
+ DBG_CLIENT_BLKID_dccg0_1 = 0x89,
+} DebugBlockId;
+typedef enum DebugBlockId_OLD {
+ DBG_BLOCK_ID_RESERVED = 0x0,
+ DBG_BLOCK_ID_DBG = 0x1,
+ DBG_BLOCK_ID_VMC = 0x2,
+ DBG_BLOCK_ID_PDMA = 0x3,
+ DBG_BLOCK_ID_CG = 0x4,
+ DBG_BLOCK_ID_SRBM = 0x5,
+ DBG_BLOCK_ID_GRBM = 0x6,
+ DBG_BLOCK_ID_RLC = 0x7,
+ DBG_BLOCK_ID_CSC = 0x8,
+ DBG_BLOCK_ID_SEM = 0x9,
+ DBG_BLOCK_ID_IH = 0xa,
+ DBG_BLOCK_ID_SC = 0xb,
+ DBG_BLOCK_ID_SQ = 0xc,
+ DBG_BLOCK_ID_AVP = 0xd,
+ DBG_BLOCK_ID_GMCON = 0xe,
+ DBG_BLOCK_ID_SMU = 0xf,
+ DBG_BLOCK_ID_DMA0 = 0x10,
+ DBG_BLOCK_ID_DMA1 = 0x11,
+ DBG_BLOCK_ID_SPIM = 0x12,
+ DBG_BLOCK_ID_GDS = 0x13,
+ DBG_BLOCK_ID_SPIS = 0x14,
+ DBG_BLOCK_ID_UNUSED0 = 0x15,
+ DBG_BLOCK_ID_PA0 = 0x16,
+ DBG_BLOCK_ID_PA1 = 0x17,
+ DBG_BLOCK_ID_CP0 = 0x18,
+ DBG_BLOCK_ID_CP1 = 0x19,
+ DBG_BLOCK_ID_CP2 = 0x1a,
+ DBG_BLOCK_ID_UNUSED1 = 0x1b,
+ DBG_BLOCK_ID_UVDU = 0x1c,
+ DBG_BLOCK_ID_UVDM = 0x1d,
+ DBG_BLOCK_ID_VCE = 0x1e,
+ DBG_BLOCK_ID_UNUSED2 = 0x1f,
+ DBG_BLOCK_ID_VGT0 = 0x20,
+ DBG_BLOCK_ID_VGT1 = 0x21,
+ DBG_BLOCK_ID_IA = 0x22,
+ DBG_BLOCK_ID_UNUSED3 = 0x23,
+ DBG_BLOCK_ID_SCT0 = 0x24,
+ DBG_BLOCK_ID_SCT1 = 0x25,
+ DBG_BLOCK_ID_SPM0 = 0x26,
+ DBG_BLOCK_ID_SPM1 = 0x27,
+ DBG_BLOCK_ID_TCAA = 0x28,
+ DBG_BLOCK_ID_TCAB = 0x29,
+ DBG_BLOCK_ID_TCCA = 0x2a,
+ DBG_BLOCK_ID_TCCB = 0x2b,
+ DBG_BLOCK_ID_MCC0 = 0x2c,
+ DBG_BLOCK_ID_MCC1 = 0x2d,
+ DBG_BLOCK_ID_MCC2 = 0x2e,
+ DBG_BLOCK_ID_MCC3 = 0x2f,
+ DBG_BLOCK_ID_SX0 = 0x30,
+ DBG_BLOCK_ID_SX1 = 0x31,
+ DBG_BLOCK_ID_SX2 = 0x32,
+ DBG_BLOCK_ID_SX3 = 0x33,
+ DBG_BLOCK_ID_UNUSED4 = 0x34,
+ DBG_BLOCK_ID_UNUSED5 = 0x35,
+ DBG_BLOCK_ID_UNUSED6 = 0x36,
+ DBG_BLOCK_ID_UNUSED7 = 0x37,
+ DBG_BLOCK_ID_PC0 = 0x38,
+ DBG_BLOCK_ID_PC1 = 0x39,
+ DBG_BLOCK_ID_UNUSED8 = 0x3a,
+ DBG_BLOCK_ID_UNUSED9 = 0x3b,
+ DBG_BLOCK_ID_UNUSED10 = 0x3c,
+ DBG_BLOCK_ID_UNUSED11 = 0x3d,
+ DBG_BLOCK_ID_MCB = 0x3e,
+ DBG_BLOCK_ID_UNUSED12 = 0x3f,
+ DBG_BLOCK_ID_SCB0 = 0x40,
+ DBG_BLOCK_ID_SCB1 = 0x41,
+ DBG_BLOCK_ID_UNUSED13 = 0x42,
+ DBG_BLOCK_ID_UNUSED14 = 0x43,
+ DBG_BLOCK_ID_SCF0 = 0x44,
+ DBG_BLOCK_ID_SCF1 = 0x45,
+ DBG_BLOCK_ID_UNUSED15 = 0x46,
+ DBG_BLOCK_ID_UNUSED16 = 0x47,
+ DBG_BLOCK_ID_BCI0 = 0x48,
+ DBG_BLOCK_ID_BCI1 = 0x49,
+ DBG_BLOCK_ID_BCI2 = 0x4a,
+ DBG_BLOCK_ID_BCI3 = 0x4b,
+ DBG_BLOCK_ID_UNUSED17 = 0x4c,
+ DBG_BLOCK_ID_UNUSED18 = 0x4d,
+ DBG_BLOCK_ID_UNUSED19 = 0x4e,
+ DBG_BLOCK_ID_UNUSED20 = 0x4f,
+ DBG_BLOCK_ID_CB00 = 0x50,
+ DBG_BLOCK_ID_CB01 = 0x51,
+ DBG_BLOCK_ID_CB02 = 0x52,
+ DBG_BLOCK_ID_CB03 = 0x53,
+ DBG_BLOCK_ID_CB04 = 0x54,
+ DBG_BLOCK_ID_UNUSED21 = 0x55,
+ DBG_BLOCK_ID_UNUSED22 = 0x56,
+ DBG_BLOCK_ID_UNUSED23 = 0x57,
+ DBG_BLOCK_ID_CB10 = 0x58,
+ DBG_BLOCK_ID_CB11 = 0x59,
+ DBG_BLOCK_ID_CB12 = 0x5a,
+ DBG_BLOCK_ID_CB13 = 0x5b,
+ DBG_BLOCK_ID_CB14 = 0x5c,
+ DBG_BLOCK_ID_UNUSED24 = 0x5d,
+ DBG_BLOCK_ID_UNUSED25 = 0x5e,
+ DBG_BLOCK_ID_UNUSED26 = 0x5f,
+ DBG_BLOCK_ID_TCP0 = 0x60,
+ DBG_BLOCK_ID_TCP1 = 0x61,
+ DBG_BLOCK_ID_TCP2 = 0x62,
+ DBG_BLOCK_ID_TCP3 = 0x63,
+ DBG_BLOCK_ID_TCP4 = 0x64,
+ DBG_BLOCK_ID_TCP5 = 0x65,
+ DBG_BLOCK_ID_TCP6 = 0x66,
+ DBG_BLOCK_ID_TCP7 = 0x67,
+ DBG_BLOCK_ID_TCP8 = 0x68,
+ DBG_BLOCK_ID_TCP9 = 0x69,
+ DBG_BLOCK_ID_TCP10 = 0x6a,
+ DBG_BLOCK_ID_TCP11 = 0x6b,
+ DBG_BLOCK_ID_TCP12 = 0x6c,
+ DBG_BLOCK_ID_TCP13 = 0x6d,
+ DBG_BLOCK_ID_TCP14 = 0x6e,
+ DBG_BLOCK_ID_TCP15 = 0x6f,
+ DBG_BLOCK_ID_TCP16 = 0x70,
+ DBG_BLOCK_ID_TCP17 = 0x71,
+ DBG_BLOCK_ID_TCP18 = 0x72,
+ DBG_BLOCK_ID_TCP19 = 0x73,
+ DBG_BLOCK_ID_TCP20 = 0x74,
+ DBG_BLOCK_ID_TCP21 = 0x75,
+ DBG_BLOCK_ID_TCP22 = 0x76,
+ DBG_BLOCK_ID_TCP23 = 0x77,
+ DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
+ DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
+ DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
+ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
+ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
+ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
+ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
+ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
+ DBG_BLOCK_ID_DB00 = 0x80,
+ DBG_BLOCK_ID_DB01 = 0x81,
+ DBG_BLOCK_ID_DB02 = 0x82,
+ DBG_BLOCK_ID_DB03 = 0x83,
+ DBG_BLOCK_ID_DB04 = 0x84,
+ DBG_BLOCK_ID_UNUSED27 = 0x85,
+ DBG_BLOCK_ID_UNUSED28 = 0x86,
+ DBG_BLOCK_ID_UNUSED29 = 0x87,
+ DBG_BLOCK_ID_DB10 = 0x88,
+ DBG_BLOCK_ID_DB11 = 0x89,
+ DBG_BLOCK_ID_DB12 = 0x8a,
+ DBG_BLOCK_ID_DB13 = 0x8b,
+ DBG_BLOCK_ID_DB14 = 0x8c,
+ DBG_BLOCK_ID_UNUSED30 = 0x8d,
+ DBG_BLOCK_ID_UNUSED31 = 0x8e,
+ DBG_BLOCK_ID_UNUSED32 = 0x8f,
+ DBG_BLOCK_ID_TCC0 = 0x90,
+ DBG_BLOCK_ID_TCC1 = 0x91,
+ DBG_BLOCK_ID_TCC2 = 0x92,
+ DBG_BLOCK_ID_TCC3 = 0x93,
+ DBG_BLOCK_ID_TCC4 = 0x94,
+ DBG_BLOCK_ID_TCC5 = 0x95,
+ DBG_BLOCK_ID_TCC6 = 0x96,
+ DBG_BLOCK_ID_TCC7 = 0x97,
+ DBG_BLOCK_ID_SPS00 = 0x98,
+ DBG_BLOCK_ID_SPS01 = 0x99,
+ DBG_BLOCK_ID_SPS02 = 0x9a,
+ DBG_BLOCK_ID_SPS10 = 0x9b,
+ DBG_BLOCK_ID_SPS11 = 0x9c,
+ DBG_BLOCK_ID_SPS12 = 0x9d,
+ DBG_BLOCK_ID_UNUSED33 = 0x9e,
+ DBG_BLOCK_ID_UNUSED34 = 0x9f,
+ DBG_BLOCK_ID_TA00 = 0xa0,
+ DBG_BLOCK_ID_TA01 = 0xa1,
+ DBG_BLOCK_ID_TA02 = 0xa2,
+ DBG_BLOCK_ID_TA03 = 0xa3,
+ DBG_BLOCK_ID_TA04 = 0xa4,
+ DBG_BLOCK_ID_TA05 = 0xa5,
+ DBG_BLOCK_ID_TA06 = 0xa6,
+ DBG_BLOCK_ID_TA07 = 0xa7,
+ DBG_BLOCK_ID_TA08 = 0xa8,
+ DBG_BLOCK_ID_TA09 = 0xa9,
+ DBG_BLOCK_ID_TA0A = 0xaa,
+ DBG_BLOCK_ID_TA0B = 0xab,
+ DBG_BLOCK_ID_UNUSED35 = 0xac,
+ DBG_BLOCK_ID_UNUSED36 = 0xad,
+ DBG_BLOCK_ID_UNUSED37 = 0xae,
+ DBG_BLOCK_ID_UNUSED38 = 0xaf,
+ DBG_BLOCK_ID_TA10 = 0xb0,
+ DBG_BLOCK_ID_TA11 = 0xb1,
+ DBG_BLOCK_ID_TA12 = 0xb2,
+ DBG_BLOCK_ID_TA13 = 0xb3,
+ DBG_BLOCK_ID_TA14 = 0xb4,
+ DBG_BLOCK_ID_TA15 = 0xb5,
+ DBG_BLOCK_ID_TA16 = 0xb6,
+ DBG_BLOCK_ID_TA17 = 0xb7,
+ DBG_BLOCK_ID_TA18 = 0xb8,
+ DBG_BLOCK_ID_TA19 = 0xb9,
+ DBG_BLOCK_ID_TA1A = 0xba,
+ DBG_BLOCK_ID_TA1B = 0xbb,
+ DBG_BLOCK_ID_UNUSED39 = 0xbc,
+ DBG_BLOCK_ID_UNUSED40 = 0xbd,
+ DBG_BLOCK_ID_UNUSED41 = 0xbe,
+ DBG_BLOCK_ID_UNUSED42 = 0xbf,
+ DBG_BLOCK_ID_TD00 = 0xc0,
+ DBG_BLOCK_ID_TD01 = 0xc1,
+ DBG_BLOCK_ID_TD02 = 0xc2,
+ DBG_BLOCK_ID_TD03 = 0xc3,
+ DBG_BLOCK_ID_TD04 = 0xc4,
+ DBG_BLOCK_ID_TD05 = 0xc5,
+ DBG_BLOCK_ID_TD06 = 0xc6,
+ DBG_BLOCK_ID_TD07 = 0xc7,
+ DBG_BLOCK_ID_TD08 = 0xc8,
+ DBG_BLOCK_ID_TD09 = 0xc9,
+ DBG_BLOCK_ID_TD0A = 0xca,
+ DBG_BLOCK_ID_TD0B = 0xcb,
+ DBG_BLOCK_ID_UNUSED43 = 0xcc,
+ DBG_BLOCK_ID_UNUSED44 = 0xcd,
+ DBG_BLOCK_ID_UNUSED45 = 0xce,
+ DBG_BLOCK_ID_UNUSED46 = 0xcf,
+ DBG_BLOCK_ID_TD10 = 0xd0,
+ DBG_BLOCK_ID_TD11 = 0xd1,
+ DBG_BLOCK_ID_TD12 = 0xd2,
+ DBG_BLOCK_ID_TD13 = 0xd3,
+ DBG_BLOCK_ID_TD14 = 0xd4,
+ DBG_BLOCK_ID_TD15 = 0xd5,
+ DBG_BLOCK_ID_TD16 = 0xd6,
+ DBG_BLOCK_ID_TD17 = 0xd7,
+ DBG_BLOCK_ID_TD18 = 0xd8,
+ DBG_BLOCK_ID_TD19 = 0xd9,
+ DBG_BLOCK_ID_TD1A = 0xda,
+ DBG_BLOCK_ID_TD1B = 0xdb,
+ DBG_BLOCK_ID_UNUSED47 = 0xdc,
+ DBG_BLOCK_ID_UNUSED48 = 0xdd,
+ DBG_BLOCK_ID_UNUSED49 = 0xde,
+ DBG_BLOCK_ID_UNUSED50 = 0xdf,
+ DBG_BLOCK_ID_MCD0 = 0xe0,
+ DBG_BLOCK_ID_MCD1 = 0xe1,
+ DBG_BLOCK_ID_MCD2 = 0xe2,
+ DBG_BLOCK_ID_MCD3 = 0xe3,
+ DBG_BLOCK_ID_MCD4 = 0xe4,
+ DBG_BLOCK_ID_MCD5 = 0xe5,
+ DBG_BLOCK_ID_UNUSED51 = 0xe6,
+ DBG_BLOCK_ID_UNUSED52 = 0xe7,
+} DebugBlockId_OLD;
+typedef enum DebugBlockId_BY2 {
+ DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
+ DBG_BLOCK_ID_VMC_BY2 = 0x1,
+ DBG_BLOCK_ID_CG_BY2 = 0x2,
+ DBG_BLOCK_ID_GRBM_BY2 = 0x3,
+ DBG_BLOCK_ID_CSC_BY2 = 0x4,
+ DBG_BLOCK_ID_IH_BY2 = 0x5,
+ DBG_BLOCK_ID_SQ_BY2 = 0x6,
+ DBG_BLOCK_ID_GMCON_BY2 = 0x7,
+ DBG_BLOCK_ID_DMA0_BY2 = 0x8,
+ DBG_BLOCK_ID_SPIM_BY2 = 0x9,
+ DBG_BLOCK_ID_SPIS_BY2 = 0xa,
+ DBG_BLOCK_ID_PA0_BY2 = 0xb,
+ DBG_BLOCK_ID_CP0_BY2 = 0xc,
+ DBG_BLOCK_ID_CP2_BY2 = 0xd,
+ DBG_BLOCK_ID_UVDU_BY2 = 0xe,
+ DBG_BLOCK_ID_VCE_BY2 = 0xf,
+ DBG_BLOCK_ID_VGT0_BY2 = 0x10,
+ DBG_BLOCK_ID_IA_BY2 = 0x11,
+ DBG_BLOCK_ID_SCT0_BY2 = 0x12,
+ DBG_BLOCK_ID_SPM0_BY2 = 0x13,
+ DBG_BLOCK_ID_TCAA_BY2 = 0x14,
+ DBG_BLOCK_ID_TCCA_BY2 = 0x15,
+ DBG_BLOCK_ID_MCC0_BY2 = 0x16,
+ DBG_BLOCK_ID_MCC2_BY2 = 0x17,
+ DBG_BLOCK_ID_SX0_BY2 = 0x18,
+ DBG_BLOCK_ID_SX2_BY2 = 0x19,
+ DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
+ DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
+ DBG_BLOCK_ID_PC0_BY2 = 0x1c,
+ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
+ DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
+ DBG_BLOCK_ID_MCB_BY2 = 0x1f,
+ DBG_BLOCK_ID_SCB0_BY2 = 0x20,
+ DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
+ DBG_BLOCK_ID_SCF0_BY2 = 0x22,
+ DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
+ DBG_BLOCK_ID_BCI0_BY2 = 0x24,
+ DBG_BLOCK_ID_BCI2_BY2 = 0x25,
+ DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
+ DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
+ DBG_BLOCK_ID_CB00_BY2 = 0x28,
+ DBG_BLOCK_ID_CB02_BY2 = 0x29,
+ DBG_BLOCK_ID_CB04_BY2 = 0x2a,
+ DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
+ DBG_BLOCK_ID_CB10_BY2 = 0x2c,
+ DBG_BLOCK_ID_CB12_BY2 = 0x2d,
+ DBG_BLOCK_ID_CB14_BY2 = 0x2e,
+ DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
+ DBG_BLOCK_ID_TCP0_BY2 = 0x30,
+ DBG_BLOCK_ID_TCP2_BY2 = 0x31,
+ DBG_BLOCK_ID_TCP4_BY2 = 0x32,
+ DBG_BLOCK_ID_TCP6_BY2 = 0x33,
+ DBG_BLOCK_ID_TCP8_BY2 = 0x34,
+ DBG_BLOCK_ID_TCP10_BY2 = 0x35,
+ DBG_BLOCK_ID_TCP12_BY2 = 0x36,
+ DBG_BLOCK_ID_TCP14_BY2 = 0x37,
+ DBG_BLOCK_ID_TCP16_BY2 = 0x38,
+ DBG_BLOCK_ID_TCP18_BY2 = 0x39,
+ DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
+ DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
+ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
+ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
+ DBG_BLOCK_ID_DB00_BY2 = 0x40,
+ DBG_BLOCK_ID_DB02_BY2 = 0x41,
+ DBG_BLOCK_ID_DB04_BY2 = 0x42,
+ DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
+ DBG_BLOCK_ID_DB10_BY2 = 0x44,
+ DBG_BLOCK_ID_DB12_BY2 = 0x45,
+ DBG_BLOCK_ID_DB14_BY2 = 0x46,
+ DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
+ DBG_BLOCK_ID_TCC0_BY2 = 0x48,
+ DBG_BLOCK_ID_TCC2_BY2 = 0x49,
+ DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
+ DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
+ DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
+ DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
+ DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
+ DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
+ DBG_BLOCK_ID_TA00_BY2 = 0x50,
+ DBG_BLOCK_ID_TA02_BY2 = 0x51,
+ DBG_BLOCK_ID_TA04_BY2 = 0x52,
+ DBG_BLOCK_ID_TA06_BY2 = 0x53,
+ DBG_BLOCK_ID_TA08_BY2 = 0x54,
+ DBG_BLOCK_ID_TA0A_BY2 = 0x55,
+ DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
+ DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
+ DBG_BLOCK_ID_TA10_BY2 = 0x58,
+ DBG_BLOCK_ID_TA12_BY2 = 0x59,
+ DBG_BLOCK_ID_TA14_BY2 = 0x5a,
+ DBG_BLOCK_ID_TA16_BY2 = 0x5b,
+ DBG_BLOCK_ID_TA18_BY2 = 0x5c,
+ DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
+ DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
+ DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
+ DBG_BLOCK_ID_TD00_BY2 = 0x60,
+ DBG_BLOCK_ID_TD02_BY2 = 0x61,
+ DBG_BLOCK_ID_TD04_BY2 = 0x62,
+ DBG_BLOCK_ID_TD06_BY2 = 0x63,
+ DBG_BLOCK_ID_TD08_BY2 = 0x64,
+ DBG_BLOCK_ID_TD0A_BY2 = 0x65,
+ DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
+ DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
+ DBG_BLOCK_ID_TD10_BY2 = 0x68,
+ DBG_BLOCK_ID_TD12_BY2 = 0x69,
+ DBG_BLOCK_ID_TD14_BY2 = 0x6a,
+ DBG_BLOCK_ID_TD16_BY2 = 0x6b,
+ DBG_BLOCK_ID_TD18_BY2 = 0x6c,
+ DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
+ DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
+ DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
+ DBG_BLOCK_ID_MCD0_BY2 = 0x70,
+ DBG_BLOCK_ID_MCD2_BY2 = 0x71,
+ DBG_BLOCK_ID_MCD4_BY2 = 0x72,
+ DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
+} DebugBlockId_BY2;
+typedef enum DebugBlockId_BY4 {
+ DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
+ DBG_BLOCK_ID_CG_BY4 = 0x1,
+ DBG_BLOCK_ID_CSC_BY4 = 0x2,
+ DBG_BLOCK_ID_SQ_BY4 = 0x3,
+ DBG_BLOCK_ID_DMA0_BY4 = 0x4,
+ DBG_BLOCK_ID_SPIS_BY4 = 0x5,
+ DBG_BLOCK_ID_CP0_BY4 = 0x6,
+ DBG_BLOCK_ID_UVDU_BY4 = 0x7,
+ DBG_BLOCK_ID_VGT0_BY4 = 0x8,
+ DBG_BLOCK_ID_SCT0_BY4 = 0x9,
+ DBG_BLOCK_ID_TCAA_BY4 = 0xa,
+ DBG_BLOCK_ID_MCC0_BY4 = 0xb,
+ DBG_BLOCK_ID_SX0_BY4 = 0xc,
+ DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
+ DBG_BLOCK_ID_PC0_BY4 = 0xe,
+ DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
+ DBG_BLOCK_ID_SCB0_BY4 = 0x10,
+ DBG_BLOCK_ID_SCF0_BY4 = 0x11,
+ DBG_BLOCK_ID_BCI0_BY4 = 0x12,
+ DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
+ DBG_BLOCK_ID_CB00_BY4 = 0x14,
+ DBG_BLOCK_ID_CB04_BY4 = 0x15,
+ DBG_BLOCK_ID_CB10_BY4 = 0x16,
+ DBG_BLOCK_ID_CB14_BY4 = 0x17,
+ DBG_BLOCK_ID_TCP0_BY4 = 0x18,
+ DBG_BLOCK_ID_TCP4_BY4 = 0x19,
+ DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
+ DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
+ DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
+ DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
+ DBG_BLOCK_ID_DB_BY4 = 0x20,
+ DBG_BLOCK_ID_DB04_BY4 = 0x21,
+ DBG_BLOCK_ID_DB10_BY4 = 0x22,
+ DBG_BLOCK_ID_DB14_BY4 = 0x23,
+ DBG_BLOCK_ID_TCC0_BY4 = 0x24,
+ DBG_BLOCK_ID_TCC4_BY4 = 0x25,
+ DBG_BLOCK_ID_SPS00_BY4 = 0x26,
+ DBG_BLOCK_ID_SPS11_BY4 = 0x27,
+ DBG_BLOCK_ID_TA00_BY4 = 0x28,
+ DBG_BLOCK_ID_TA04_BY4 = 0x29,
+ DBG_BLOCK_ID_TA08_BY4 = 0x2a,
+ DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
+ DBG_BLOCK_ID_TA10_BY4 = 0x2c,
+ DBG_BLOCK_ID_TA14_BY4 = 0x2d,
+ DBG_BLOCK_ID_TA18_BY4 = 0x2e,
+ DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
+ DBG_BLOCK_ID_TD00_BY4 = 0x30,
+ DBG_BLOCK_ID_TD04_BY4 = 0x31,
+ DBG_BLOCK_ID_TD08_BY4 = 0x32,
+ DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
+ DBG_BLOCK_ID_TD10_BY4 = 0x34,
+ DBG_BLOCK_ID_TD14_BY4 = 0x35,
+ DBG_BLOCK_ID_TD18_BY4 = 0x36,
+ DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
+ DBG_BLOCK_ID_MCD0_BY4 = 0x38,
+ DBG_BLOCK_ID_MCD4_BY4 = 0x39,
+} DebugBlockId_BY4;
+typedef enum DebugBlockId_BY8 {
+ DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
+ DBG_BLOCK_ID_CSC_BY8 = 0x1,
+ DBG_BLOCK_ID_DMA0_BY8 = 0x2,
+ DBG_BLOCK_ID_CP0_BY8 = 0x3,
+ DBG_BLOCK_ID_VGT0_BY8 = 0x4,
+ DBG_BLOCK_ID_TCAA_BY8 = 0x5,
+ DBG_BLOCK_ID_SX0_BY8 = 0x6,
+ DBG_BLOCK_ID_PC0_BY8 = 0x7,
+ DBG_BLOCK_ID_SCB0_BY8 = 0x8,
+ DBG_BLOCK_ID_BCI0_BY8 = 0x9,
+ DBG_BLOCK_ID_CB00_BY8 = 0xa,
+ DBG_BLOCK_ID_CB10_BY8 = 0xb,
+ DBG_BLOCK_ID_TCP0_BY8 = 0xc,
+ DBG_BLOCK_ID_TCP8_BY8 = 0xd,
+ DBG_BLOCK_ID_TCP16_BY8 = 0xe,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
+ DBG_BLOCK_ID_DB00_BY8 = 0x10,
+ DBG_BLOCK_ID_DB10_BY8 = 0x11,
+ DBG_BLOCK_ID_TCC0_BY8 = 0x12,
+ DBG_BLOCK_ID_SPS00_BY8 = 0x13,
+ DBG_BLOCK_ID_TA00_BY8 = 0x14,
+ DBG_BLOCK_ID_TA08_BY8 = 0x15,
+ DBG_BLOCK_ID_TA10_BY8 = 0x16,
+ DBG_BLOCK_ID_TA18_BY8 = 0x17,
+ DBG_BLOCK_ID_TD00_BY8 = 0x18,
+ DBG_BLOCK_ID_TD08_BY8 = 0x19,
+ DBG_BLOCK_ID_TD10_BY8 = 0x1a,
+ DBG_BLOCK_ID_TD18_BY8 = 0x1b,
+ DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
+} DebugBlockId_BY8;
+typedef enum DebugBlockId_BY16 {
+ DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
+ DBG_BLOCK_ID_DMA0_BY16 = 0x1,
+ DBG_BLOCK_ID_VGT0_BY16 = 0x2,
+ DBG_BLOCK_ID_SX0_BY16 = 0x3,
+ DBG_BLOCK_ID_SCB0_BY16 = 0x4,
+ DBG_BLOCK_ID_CB00_BY16 = 0x5,
+ DBG_BLOCK_ID_TCP0_BY16 = 0x6,
+ DBG_BLOCK_ID_TCP16_BY16 = 0x7,
+ DBG_BLOCK_ID_DB00_BY16 = 0x8,
+ DBG_BLOCK_ID_TCC0_BY16 = 0x9,
+ DBG_BLOCK_ID_TA00_BY16 = 0xa,
+ DBG_BLOCK_ID_TA10_BY16 = 0xb,
+ DBG_BLOCK_ID_TD00_BY16 = 0xc,
+ DBG_BLOCK_ID_TD10_BY16 = 0xd,
+ DBG_BLOCK_ID_MCD0_BY16 = 0xe,
+} DebugBlockId_BY16;
+typedef enum ColorTransform {
+ DCC_CT_AUTO = 0x0,
+ DCC_CT_NONE = 0x1,
+ ABGR_TO_A_BG_G_RB = 0x2,
+ BGRA_TO_BG_G_RB_A = 0x3,
+} ColorTransform;
+typedef enum CompareRef {
+ REF_NEVER = 0x0,
+ REF_LESS = 0x1,
+ REF_EQUAL = 0x2,
+ REF_LEQUAL = 0x3,
+ REF_GREATER = 0x4,
+ REF_NOTEQUAL = 0x5,
+ REF_GEQUAL = 0x6,
+ REF_ALWAYS = 0x7,
+} CompareRef;
+typedef enum ReadSize {
+ READ_256_BITS = 0x0,
+ READ_512_BITS = 0x1,
+} ReadSize;
+typedef enum DepthFormat {
+ DEPTH_INVALID = 0x0,
+ DEPTH_16 = 0x1,
+ DEPTH_X8_24 = 0x2,
+ DEPTH_8_24 = 0x3,
+ DEPTH_X8_24_FLOAT = 0x4,
+ DEPTH_8_24_FLOAT = 0x5,
+ DEPTH_32_FLOAT = 0x6,
+ DEPTH_X24_8_32_FLOAT = 0x7,
+} DepthFormat;
+typedef enum ZFormat {
+ Z_INVALID = 0x0,
+ Z_16 = 0x1,
+ Z_24 = 0x2,
+ Z_32_FLOAT = 0x3,
+} ZFormat;
+typedef enum StencilFormat {
+ STENCIL_INVALID = 0x0,
+ STENCIL_8 = 0x1,
+} StencilFormat;
+typedef enum CmaskMode {
+ CMASK_CLEAR_NONE = 0x0,
+ CMASK_CLEAR_ONE = 0x1,
+ CMASK_CLEAR_ALL = 0x2,
+ CMASK_ANY_EXPANDED = 0x3,
+ CMASK_ALPHA0_FRAG1 = 0x4,
+ CMASK_ALPHA0_FRAG2 = 0x5,
+ CMASK_ALPHA0_FRAG4 = 0x6,
+ CMASK_ALPHA0_FRAGS = 0x7,
+ CMASK_ALPHA1_FRAG1 = 0x8,
+ CMASK_ALPHA1_FRAG2 = 0x9,
+ CMASK_ALPHA1_FRAG4 = 0xa,
+ CMASK_ALPHA1_FRAGS = 0xb,
+ CMASK_ALPHAX_FRAG1 = 0xc,
+ CMASK_ALPHAX_FRAG2 = 0xd,
+ CMASK_ALPHAX_FRAG4 = 0xe,
+ CMASK_ALPHAX_FRAGS = 0xf,
+} CmaskMode;
+typedef enum QuadExportFormat {
+ EXPORT_UNUSED = 0x0,
+ EXPORT_32_R = 0x1,
+ EXPORT_32_GR = 0x2,
+ EXPORT_32_AR = 0x3,
+ EXPORT_FP16_ABGR = 0x4,
+ EXPORT_UNSIGNED16_ABGR = 0x5,
+ EXPORT_SIGNED16_ABGR = 0x6,
+ EXPORT_32_ABGR = 0x7,
+} QuadExportFormat;
+typedef enum QuadExportFormatOld {
+ EXPORT_4P_32BPC_ABGR = 0x0,
+ EXPORT_4P_16BPC_ABGR = 0x1,
+ EXPORT_4P_32BPC_GR = 0x2,
+ EXPORT_4P_32BPC_AR = 0x3,
+ EXPORT_2P_32BPC_ABGR = 0x4,
+ EXPORT_8P_32BPC_R = 0x5,
+} QuadExportFormatOld;
+typedef enum ColorFormat {
+ COLOR_INVALID = 0x0,
+ COLOR_8 = 0x1,
+ COLOR_16 = 0x2,
+ COLOR_8_8 = 0x3,
+ COLOR_32 = 0x4,
+ COLOR_16_16 = 0x5,
+ COLOR_10_11_11 = 0x6,
+ COLOR_11_11_10 = 0x7,
+ COLOR_10_10_10_2 = 0x8,
+ COLOR_2_10_10_10 = 0x9,
+ COLOR_8_8_8_8 = 0xa,
+ COLOR_32_32 = 0xb,
+ COLOR_16_16_16_16 = 0xc,
+ COLOR_RESERVED_13 = 0xd,
+ COLOR_32_32_32_32 = 0xe,
+ COLOR_RESERVED_15 = 0xf,
+ COLOR_5_6_5 = 0x10,
+ COLOR_1_5_5_5 = 0x11,
+ COLOR_5_5_5_1 = 0x12,
+ COLOR_4_4_4_4 = 0x13,
+ COLOR_8_24 = 0x14,
+ COLOR_24_8 = 0x15,
+ COLOR_X24_8_32_FLOAT = 0x16,
+ COLOR_RESERVED_23 = 0x17,
+} ColorFormat;
+typedef enum SurfaceFormat {
+ FMT_INVALID = 0x0,
+ FMT_8 = 0x1,
+ FMT_16 = 0x2,
+ FMT_8_8 = 0x3,
+ FMT_32 = 0x4,
+ FMT_16_16 = 0x5,
+ FMT_10_11_11 = 0x6,
+ FMT_11_11_10 = 0x7,
+ FMT_10_10_10_2 = 0x8,
+ FMT_2_10_10_10 = 0x9,
+ FMT_8_8_8_8 = 0xa,
+ FMT_32_32 = 0xb,
+ FMT_16_16_16_16 = 0xc,
+ FMT_32_32_32 = 0xd,
+ FMT_32_32_32_32 = 0xe,
+ FMT_RESERVED_4 = 0xf,
+ FMT_5_6_5 = 0x10,
+ FMT_1_5_5_5 = 0x11,
+ FMT_5_5_5_1 = 0x12,
+ FMT_4_4_4_4 = 0x13,
+ FMT_8_24 = 0x14,
+ FMT_24_8 = 0x15,
+ FMT_X24_8_32_FLOAT = 0x16,
+ FMT_RESERVED_33 = 0x17,
+ FMT_11_11_10_FLOAT = 0x18,
+ FMT_16_FLOAT = 0x19,
+ FMT_32_FLOAT = 0x1a,
+ FMT_16_16_FLOAT = 0x1b,
+ FMT_8_24_FLOAT = 0x1c,
+ FMT_24_8_FLOAT = 0x1d,
+ FMT_32_32_FLOAT = 0x1e,
+ FMT_10_11_11_FLOAT = 0x1f,
+ FMT_16_16_16_16_FLOAT = 0x20,
+ FMT_3_3_2 = 0x21,
+ FMT_6_5_5 = 0x22,
+ FMT_32_32_32_32_FLOAT = 0x23,
+ FMT_RESERVED_36 = 0x24,
+ FMT_1 = 0x25,
+ FMT_1_REVERSED = 0x26,
+ FMT_GB_GR = 0x27,
+ FMT_BG_RG = 0x28,
+ FMT_32_AS_8 = 0x29,
+ FMT_32_AS_8_8 = 0x2a,
+ FMT_5_9_9_9_SHAREDEXP = 0x2b,
+ FMT_8_8_8 = 0x2c,
+ FMT_16_16_16 = 0x2d,
+ FMT_16_16_16_FLOAT = 0x2e,
+ FMT_4_4 = 0x2f,
+ FMT_32_32_32_FLOAT = 0x30,
+ FMT_BC1 = 0x31,
+ FMT_BC2 = 0x32,
+ FMT_BC3 = 0x33,
+ FMT_BC4 = 0x34,
+ FMT_BC5 = 0x35,
+ FMT_BC6 = 0x36,
+ FMT_BC7 = 0x37,
+ FMT_32_AS_32_32_32_32 = 0x38,
+ FMT_APC3 = 0x39,
+ FMT_APC4 = 0x3a,
+ FMT_APC5 = 0x3b,
+ FMT_APC6 = 0x3c,
+ FMT_APC7 = 0x3d,
+ FMT_CTX1 = 0x3e,
+ FMT_RESERVED_63 = 0x3f,
+} SurfaceFormat;
+typedef enum BUF_DATA_FORMAT {
+ BUF_DATA_FORMAT_INVALID = 0x0,
+ BUF_DATA_FORMAT_8 = 0x1,
+ BUF_DATA_FORMAT_16 = 0x2,
+ BUF_DATA_FORMAT_8_8 = 0x3,
+ BUF_DATA_FORMAT_32 = 0x4,
+ BUF_DATA_FORMAT_16_16 = 0x5,
+ BUF_DATA_FORMAT_10_11_11 = 0x6,
+ BUF_DATA_FORMAT_11_11_10 = 0x7,
+ BUF_DATA_FORMAT_10_10_10_2 = 0x8,
+ BUF_DATA_FORMAT_2_10_10_10 = 0x9,
+ BUF_DATA_FORMAT_8_8_8_8 = 0xa,
+ BUF_DATA_FORMAT_32_32 = 0xb,
+ BUF_DATA_FORMAT_16_16_16_16 = 0xc,
+ BUF_DATA_FORMAT_32_32_32 = 0xd,
+ BUF_DATA_FORMAT_32_32_32_32 = 0xe,
+ BUF_DATA_FORMAT_RESERVED_15 = 0xf,
+} BUF_DATA_FORMAT;
+typedef enum IMG_DATA_FORMAT {
+ IMG_DATA_FORMAT_INVALID = 0x0,
+ IMG_DATA_FORMAT_8 = 0x1,
+ IMG_DATA_FORMAT_16 = 0x2,
+ IMG_DATA_FORMAT_8_8 = 0x3,
+ IMG_DATA_FORMAT_32 = 0x4,
+ IMG_DATA_FORMAT_16_16 = 0x5,
+ IMG_DATA_FORMAT_10_11_11 = 0x6,
+ IMG_DATA_FORMAT_11_11_10 = 0x7,
+ IMG_DATA_FORMAT_10_10_10_2 = 0x8,
+ IMG_DATA_FORMAT_2_10_10_10 = 0x9,
+ IMG_DATA_FORMAT_8_8_8_8 = 0xa,
+ IMG_DATA_FORMAT_32_32 = 0xb,
+ IMG_DATA_FORMAT_16_16_16_16 = 0xc,
+ IMG_DATA_FORMAT_32_32_32 = 0xd,
+ IMG_DATA_FORMAT_32_32_32_32 = 0xe,
+ IMG_DATA_FORMAT_RESERVED_15 = 0xf,
+ IMG_DATA_FORMAT_5_6_5 = 0x10,
+ IMG_DATA_FORMAT_1_5_5_5 = 0x11,
+ IMG_DATA_FORMAT_5_5_5_1 = 0x12,
+ IMG_DATA_FORMAT_4_4_4_4 = 0x13,
+ IMG_DATA_FORMAT_8_24 = 0x14,
+ IMG_DATA_FORMAT_24_8 = 0x15,
+ IMG_DATA_FORMAT_X24_8_32 = 0x16,
+ IMG_DATA_FORMAT_RESERVED_23 = 0x17,
+ IMG_DATA_FORMAT_RESERVED_24 = 0x18,
+ IMG_DATA_FORMAT_RESERVED_25 = 0x19,
+ IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
+ IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
+ IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
+ IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
+ IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
+ IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
+ IMG_DATA_FORMAT_GB_GR = 0x20,
+ IMG_DATA_FORMAT_BG_RG = 0x21,
+ IMG_DATA_FORMAT_5_9_9_9 = 0x22,
+ IMG_DATA_FORMAT_BC1 = 0x23,
+ IMG_DATA_FORMAT_BC2 = 0x24,
+ IMG_DATA_FORMAT_BC3 = 0x25,
+ IMG_DATA_FORMAT_BC4 = 0x26,
+ IMG_DATA_FORMAT_BC5 = 0x27,
+ IMG_DATA_FORMAT_BC6 = 0x28,
+ IMG_DATA_FORMAT_BC7 = 0x29,
+ IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
+ IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
+ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
+ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
+ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
+ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
+ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
+ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
+ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
+ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
+ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
+ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
+ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
+ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
+ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
+ IMG_DATA_FORMAT_4_4 = 0x39,
+ IMG_DATA_FORMAT_6_5_5 = 0x3a,
+ IMG_DATA_FORMAT_1 = 0x3b,
+ IMG_DATA_FORMAT_1_REVERSED = 0x3c,
+ IMG_DATA_FORMAT_32_AS_8 = 0x3d,
+ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
+ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
+} IMG_DATA_FORMAT;
+typedef enum BUF_NUM_FORMAT {
+ BUF_NUM_FORMAT_UNORM = 0x0,
+ BUF_NUM_FORMAT_SNORM = 0x1,
+ BUF_NUM_FORMAT_USCALED = 0x2,
+ BUF_NUM_FORMAT_SSCALED = 0x3,
+ BUF_NUM_FORMAT_UINT = 0x4,
+ BUF_NUM_FORMAT_SINT = 0x5,
+ BUF_NUM_FORMAT_RESERVED_6 = 0x6,
+ BUF_NUM_FORMAT_FLOAT = 0x7,
+} BUF_NUM_FORMAT;
+typedef enum IMG_NUM_FORMAT {
+ IMG_NUM_FORMAT_UNORM = 0x0,
+ IMG_NUM_FORMAT_SNORM = 0x1,
+ IMG_NUM_FORMAT_USCALED = 0x2,
+ IMG_NUM_FORMAT_SSCALED = 0x3,
+ IMG_NUM_FORMAT_UINT = 0x4,
+ IMG_NUM_FORMAT_SINT = 0x5,
+ IMG_NUM_FORMAT_RESERVED_6 = 0x6,
+ IMG_NUM_FORMAT_FLOAT = 0x7,
+ IMG_NUM_FORMAT_RESERVED_8 = 0x8,
+ IMG_NUM_FORMAT_SRGB = 0x9,
+ IMG_NUM_FORMAT_RESERVED_10 = 0xa,
+ IMG_NUM_FORMAT_RESERVED_11 = 0xb,
+ IMG_NUM_FORMAT_RESERVED_12 = 0xc,
+ IMG_NUM_FORMAT_RESERVED_13 = 0xd,
+ IMG_NUM_FORMAT_RESERVED_14 = 0xe,
+ IMG_NUM_FORMAT_RESERVED_15 = 0xf,
+} IMG_NUM_FORMAT;
+typedef enum TileType {
+ ARRAY_COLOR_TILE = 0x0,
+ ARRAY_DEPTH_TILE = 0x1,
+} TileType;
+typedef enum NonDispTilingOrder {
+ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
+ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
+} NonDispTilingOrder;
+typedef enum MicroTileMode {
+ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
+ ADDR_SURF_THIN_MICRO_TILING = 0x1,
+ ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
+ ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
+ ADDR_SURF_THICK_MICRO_TILING = 0x4,
+} MicroTileMode;
+typedef enum TileSplit {
+ ADDR_SURF_TILE_SPLIT_64B = 0x0,
+ ADDR_SURF_TILE_SPLIT_128B = 0x1,
+ ADDR_SURF_TILE_SPLIT_256B = 0x2,
+ ADDR_SURF_TILE_SPLIT_512B = 0x3,
+ ADDR_SURF_TILE_SPLIT_1KB = 0x4,
+ ADDR_SURF_TILE_SPLIT_2KB = 0x5,
+ ADDR_SURF_TILE_SPLIT_4KB = 0x6,
+} TileSplit;
+typedef enum SampleSplit {
+ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
+ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
+ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
+ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
+} SampleSplit;
+typedef enum PipeConfig {
+ ADDR_SURF_P2 = 0x0,
+ ADDR_SURF_P2_RESERVED0 = 0x1,
+ ADDR_SURF_P2_RESERVED1 = 0x2,
+ ADDR_SURF_P2_RESERVED2 = 0x3,
+ ADDR_SURF_P4_8x16 = 0x4,
+ ADDR_SURF_P4_16x16 = 0x5,
+ ADDR_SURF_P4_16x32 = 0x6,
+ ADDR_SURF_P4_32x32 = 0x7,
+ ADDR_SURF_P8_16x16_8x16 = 0x8,
+ ADDR_SURF_P8_16x32_8x16 = 0x9,
+ ADDR_SURF_P8_32x32_8x16 = 0xa,
+ ADDR_SURF_P8_16x32_16x16 = 0xb,
+ ADDR_SURF_P8_32x32_16x16 = 0xc,
+ ADDR_SURF_P8_32x32_16x32 = 0xd,
+ ADDR_SURF_P8_32x64_32x32 = 0xe,
+ ADDR_SURF_P8_RESERVED0 = 0xf,
+ ADDR_SURF_P16_32x32_8x16 = 0x10,
+ ADDR_SURF_P16_32x32_16x16 = 0x11,
+} PipeConfig;
+typedef enum NumBanks {
+ ADDR_SURF_2_BANK = 0x0,
+ ADDR_SURF_4_BANK = 0x1,
+ ADDR_SURF_8_BANK = 0x2,
+ ADDR_SURF_16_BANK = 0x3,
+} NumBanks;
+typedef enum BankWidth {
+ ADDR_SURF_BANK_WIDTH_1 = 0x0,
+ ADDR_SURF_BANK_WIDTH_2 = 0x1,
+ ADDR_SURF_BANK_WIDTH_4 = 0x2,
+ ADDR_SURF_BANK_WIDTH_8 = 0x3,
+} BankWidth;
+typedef enum BankHeight {
+ ADDR_SURF_BANK_HEIGHT_1 = 0x0,
+ ADDR_SURF_BANK_HEIGHT_2 = 0x1,
+ ADDR_SURF_BANK_HEIGHT_4 = 0x2,
+ ADDR_SURF_BANK_HEIGHT_8 = 0x3,
+} BankHeight;
+typedef enum BankWidthHeight {
+ ADDR_SURF_BANK_WH_1 = 0x0,
+ ADDR_SURF_BANK_WH_2 = 0x1,
+ ADDR_SURF_BANK_WH_4 = 0x2,
+ ADDR_SURF_BANK_WH_8 = 0x3,
+} BankWidthHeight;
+typedef enum MacroTileAspect {
+ ADDR_SURF_MACRO_ASPECT_1 = 0x0,
+ ADDR_SURF_MACRO_ASPECT_2 = 0x1,
+ ADDR_SURF_MACRO_ASPECT_4 = 0x2,
+ ADDR_SURF_MACRO_ASPECT_8 = 0x3,
+} MacroTileAspect;
+typedef enum GATCL1RequestType {
+ GATCL1_TYPE_NORMAL = 0x0,
+ GATCL1_TYPE_SHOOTDOWN = 0x1,
+ GATCL1_TYPE_BYPASS = 0x2,
+} GATCL1RequestType;
+typedef enum TCC_CACHE_POLICIES {
+ TCC_CACHE_POLICY_LRU = 0x0,
+ TCC_CACHE_POLICY_STREAM = 0x1,
+} TCC_CACHE_POLICIES;
+typedef enum MTYPE {
+ MTYPE_NC_NV = 0x0,
+ MTYPE_NC = 0x1,
+ MTYPE_CC = 0x2,
+ MTYPE_UC = 0x3,
+} MTYPE;
+typedef enum PERFMON_COUNTER_MODE {
+ PERFMON_COUNTER_MODE_ACCUM = 0x0,
+ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
+ PERFMON_COUNTER_MODE_MAX = 0x2,
+ PERFMON_COUNTER_MODE_DIRTY = 0x3,
+ PERFMON_COUNTER_MODE_SAMPLE = 0x4,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
+ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
+ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
+ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
+ PERFMON_COUNTER_MODE_RESERVED = 0xf,
+} PERFMON_COUNTER_MODE;
+typedef enum PERFMON_SPM_MODE {
+ PERFMON_SPM_MODE_OFF = 0x0,
+ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
+ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
+ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
+ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
+ PERFMON_SPM_MODE_RESERVED_5 = 0x5,
+ PERFMON_SPM_MODE_RESERVED_6 = 0x6,
+ PERFMON_SPM_MODE_RESERVED_7 = 0x7,
+ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
+ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
+ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
+} PERFMON_SPM_MODE;
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0x0,
+ ARRAY_TILED = 0x1,
+} SurfaceTiling;
+typedef enum SurfaceArray {
+ ARRAY_1D = 0x0,
+ ARRAY_2D = 0x1,
+ ARRAY_3D = 0x2,
+ ARRAY_3D_SLICE = 0x3,
+} SurfaceArray;
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0x0,
+ ARRAY_2D_COLOR = 0x1,
+ ARRAY_3D_SLICE_COLOR = 0x3,
+} ColorArray;
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0x0,
+ ARRAY_2D_DEPTH = 0x1,
+} DepthArray;
+typedef enum ENUM_NUM_SIMD_PER_CU {
+ NUM_SIMD_PER_CU = 0x4,
+} ENUM_NUM_SIMD_PER_CU;
+
+#endif /* OSS_2_4_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h
new file mode 100644
index 000000000000..413af7d9a21a
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h
@@ -0,0 +1,2544 @@
+/*
+ * OSS_2_4 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef OSS_2_4_SH_MASK_H
+#define OSS_2_4_SH_MASK_H
+
+#define IH_VMID_0_LUT__PASID_MASK 0xffff
+#define IH_VMID_0_LUT__PASID__SHIFT 0x0
+#define IH_VMID_1_LUT__PASID_MASK 0xffff
+#define IH_VMID_1_LUT__PASID__SHIFT 0x0
+#define IH_VMID_2_LUT__PASID_MASK 0xffff
+#define IH_VMID_2_LUT__PASID__SHIFT 0x0
+#define IH_VMID_3_LUT__PASID_MASK 0xffff
+#define IH_VMID_3_LUT__PASID__SHIFT 0x0
+#define IH_VMID_4_LUT__PASID_MASK 0xffff
+#define IH_VMID_4_LUT__PASID__SHIFT 0x0
+#define IH_VMID_5_LUT__PASID_MASK 0xffff
+#define IH_VMID_5_LUT__PASID__SHIFT 0x0
+#define IH_VMID_6_LUT__PASID_MASK 0xffff
+#define IH_VMID_6_LUT__PASID__SHIFT 0x0
+#define IH_VMID_7_LUT__PASID_MASK 0xffff
+#define IH_VMID_7_LUT__PASID__SHIFT 0x0
+#define IH_VMID_8_LUT__PASID_MASK 0xffff
+#define IH_VMID_8_LUT__PASID__SHIFT 0x0
+#define IH_VMID_9_LUT__PASID_MASK 0xffff
+#define IH_VMID_9_LUT__PASID__SHIFT 0x0
+#define IH_VMID_10_LUT__PASID_MASK 0xffff
+#define IH_VMID_10_LUT__PASID__SHIFT 0x0
+#define IH_VMID_11_LUT__PASID_MASK 0xffff
+#define IH_VMID_11_LUT__PASID__SHIFT 0x0
+#define IH_VMID_12_LUT__PASID_MASK 0xffff
+#define IH_VMID_12_LUT__PASID__SHIFT 0x0
+#define IH_VMID_13_LUT__PASID_MASK 0xffff
+#define IH_VMID_13_LUT__PASID__SHIFT 0x0
+#define IH_VMID_14_LUT__PASID_MASK 0xffff
+#define IH_VMID_14_LUT__PASID__SHIFT 0x0
+#define IH_VMID_15_LUT__PASID_MASK 0xffff
+#define IH_VMID_15_LUT__PASID__SHIFT 0x0
+#define IH_RB_CNTL__RB_ENABLE_MASK 0x1
+#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define IH_RB_CNTL__RB_SIZE_MASK 0x3e
+#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x40
+#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x6
+#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x80
+#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7
+#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100
+#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
+#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00
+#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
+#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x10000
+#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10
+#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
+#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define IH_RB_BASE__ADDR_MASK 0xffffffff
+#define IH_RB_BASE__ADDR__SHIFT 0x0
+#define IH_RB_RPTR__OFFSET_MASK 0x3fffc
+#define IH_RB_RPTR__OFFSET__SHIFT 0x2
+#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1
+#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0
+#define IH_RB_WPTR__OFFSET_MASK 0x3fffc
+#define IH_RB_WPTR__OFFSET__SHIFT 0x2
+#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x40000
+#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12
+#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x80000
+#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13
+#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0xff
+#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define IH_CNTL__ENABLE_INTR_MASK 0x1
+#define IH_CNTL__ENABLE_INTR__SHIFT 0x0
+#define IH_CNTL__MC_SWAP_MASK 0x6
+#define IH_CNTL__MC_SWAP__SHIFT 0x1
+#define IH_CNTL__RPTR_REARM_MASK 0x10
+#define IH_CNTL__RPTR_REARM__SHIFT 0x4
+#define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x300
+#define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x8
+#define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x7c00
+#define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa
+#define IH_CNTL__MC_WRREQ_CREDIT_MASK 0xf8000
+#define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0xf
+#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x1f00000
+#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14
+#define IH_CNTL__MC_VMID_MASK 0x1e000000
+#define IH_CNTL__MC_VMID__SHIFT 0x19
+#define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1
+#define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x0
+#define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x4
+#define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2
+#define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x8
+#define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x3
+#define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x10
+#define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x4
+#define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x20
+#define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x5
+#define IH_STATUS__IDLE_MASK 0x1
+#define IH_STATUS__IDLE__SHIFT 0x0
+#define IH_STATUS__INPUT_IDLE_MASK 0x2
+#define IH_STATUS__INPUT_IDLE__SHIFT 0x1
+#define IH_STATUS__RB_IDLE_MASK 0x4
+#define IH_STATUS__RB_IDLE__SHIFT 0x2
+#define IH_STATUS__RB_FULL_MASK 0x8
+#define IH_STATUS__RB_FULL__SHIFT 0x3
+#define IH_STATUS__RB_FULL_DRAIN_MASK 0x10
+#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4
+#define IH_STATUS__RB_OVERFLOW_MASK 0x20
+#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5
+#define IH_STATUS__MC_WR_IDLE_MASK 0x40
+#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6
+#define IH_STATUS__MC_WR_STALL_MASK 0x80
+#define IH_STATUS__MC_WR_STALL__SHIFT 0x7
+#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x100
+#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8
+#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x200
+#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9
+#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x400
+#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa
+#define IH_PERFMON_CNTL__ENABLE0_MASK 0x1
+#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0
+#define IH_PERFMON_CNTL__CLEAR0_MASK 0x2
+#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1
+#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
+#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
+#define IH_PERFMON_CNTL__ENABLE1_MASK 0x100
+#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x8
+#define IH_PERFMON_CNTL__CLEAR1_MASK 0x200
+#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x9
+#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
+#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
+#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
+#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
+#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
+#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
+#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xffffffff
+#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0
+#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xffffffff
+#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0
+#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xffffffff
+#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0
+#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x1
+#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0
+#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x4
+#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2
+#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x8
+#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3
+#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x10
+#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4
+#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x20
+#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5
+#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0xfffffff
+#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0
+#define IH_VERSION__VALUE_MASK 0xfff
+#define IH_VERSION__VALUE__SHIFT 0x0
+#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x3
+#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0
+#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0xfc
+#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2
+#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x3f00
+#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8
+#define SDMA_CONFIG__SDMA_RDREQ_URG_MASK 0xf00
+#define SDMA_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8
+#define SDMA_CONFIG__SDMA_REQ_TRAN_MASK 0x10000
+#define SDMA_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10
+#define SDMA1_CONFIG__SDMA_RDREQ_URG_MASK 0xf00
+#define SDMA1_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8
+#define SDMA1_CONFIG__SDMA_REQ_TRAN_MASK 0x10000
+#define SDMA1_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10
+#define UVD_CONFIG__UVD_RDREQ_URG_MASK 0xf00
+#define UVD_CONFIG__UVD_RDREQ_URG__SHIFT 0x8
+#define UVD_CONFIG__UVD_REQ_TRAN_MASK 0x10000
+#define UVD_CONFIG__UVD_REQ_TRAN__SHIFT 0x10
+#define VCE_CONFIG__VCE_RDREQ_URG_MASK 0xf00
+#define VCE_CONFIG__VCE_RDREQ_URG__SHIFT 0x8
+#define VCE_CONFIG__VCE_REQ_TRAN_MASK 0x10000
+#define VCE_CONFIG__VCE_REQ_TRAN__SHIFT 0x10
+#define ACP_CONFIG__ACP_RDREQ_URG_MASK 0xf00
+#define ACP_CONFIG__ACP_RDREQ_URG__SHIFT 0x8
+#define ACP_CONFIG__ACP_REQ_TRAN_MASK 0x10000
+#define ACP_CONFIG__ACP_REQ_TRAN__SHIFT 0x10
+#define CPG_CONFIG__CPG_RDREQ_URG_MASK 0xf00
+#define CPG_CONFIG__CPG_RDREQ_URG__SHIFT 0x8
+#define CPG_CONFIG__CPG_REQ_TRAN_MASK 0x10000
+#define CPG_CONFIG__CPG_REQ_TRAN__SHIFT 0x10
+#define CPC1_CONFIG__CPC1_RDREQ_URG_MASK 0xf00
+#define CPC1_CONFIG__CPC1_RDREQ_URG__SHIFT 0x8
+#define CPC1_CONFIG__CPC1_REQ_TRAN_MASK 0x10000
+#define CPC1_CONFIG__CPC1_REQ_TRAN__SHIFT 0x10
+#define CPC2_CONFIG__CPC2_RDREQ_URG_MASK 0xf00
+#define CPC2_CONFIG__CPC2_RDREQ_URG__SHIFT 0x8
+#define CPC2_CONFIG__CPC2_REQ_TRAN_MASK 0x10000
+#define CPC2_CONFIG__CPC2_REQ_TRAN__SHIFT 0x10
+#define SEM_STATUS__SEM_IDLE_MASK 0x1
+#define SEM_STATUS__SEM_IDLE__SHIFT 0x0
+#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x2
+#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1
+#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x4
+#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2
+#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x8
+#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3
+#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x10
+#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4
+#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x20
+#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5
+#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x40
+#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6
+#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x80
+#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7
+#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x100
+#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8
+#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x200
+#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9
+#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x400
+#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa
+#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x800
+#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb
+#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x1000
+#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc
+#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x2000
+#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd
+#define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x4000
+#define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0xe
+#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x2
+#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x7
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x38
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x1c0
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0xe00
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x7000
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc
+#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x38000
+#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x1c0000
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12
+#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0xe00000
+#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15
+#define SEM_MAILBOX__SIDEPORT_MASK 0xff
+#define SEM_MAILBOX__SIDEPORT__SHIFT 0x0
+#define SEM_MAILBOX__HOSTPORT_MASK 0xff00
+#define SEM_MAILBOX__HOSTPORT__SHIFT 0x8
+#define SEM_MAILBOX__SIDEPORT_EXTRA_MASK 0xff0000
+#define SEM_MAILBOX__SIDEPORT_EXTRA__SHIFT 0x10
+#define SEM_MAILBOX__HOSTPORT_EXTRA_MASK 0xff000000
+#define SEM_MAILBOX__HOSTPORT_EXTRA__SHIFT 0x18
+#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0xff
+#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x0
+#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0xff00
+#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x8
+#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA_MASK 0xff0000
+#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA__SHIFT 0x10
+#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA_MASK 0xff000000
+#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA__SHIFT 0x18
+#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x1
+#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0
+#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x2
+#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1
+#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x4
+#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2
+#define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x18
+#define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x3
+#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0xf00
+#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x8
+#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x1f
+#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x0
+#define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x10000
+#define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x10
+#define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x20000
+#define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x11
+#define SRBM_CNTL__REPORT_LAST_RDERR_MASK 0x40000
+#define SRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x12
+#define SRBM_GFX_CNTL__PIPEID_MASK 0x3
+#define SRBM_GFX_CNTL__PIPEID__SHIFT 0x0
+#define SRBM_GFX_CNTL__MEID_MASK 0xc
+#define SRBM_GFX_CNTL__MEID__SHIFT 0x2
+#define SRBM_GFX_CNTL__VMID_MASK 0xf0
+#define SRBM_GFX_CNTL__VMID__SHIFT 0x4
+#define SRBM_GFX_CNTL__QUEUEID_MASK 0x700
+#define SRBM_GFX_CNTL__QUEUEID__SHIFT 0x8
+#define SRBM_READ_CNTL__READ_TIMEOUT_MASK 0xffffff
+#define SRBM_READ_CNTL__READ_TIMEOUT__SHIFT 0x0
+#define SRBM_STATUS2__SDMA_RQ_PENDING_MASK 0x1
+#define SRBM_STATUS2__SDMA_RQ_PENDING__SHIFT 0x0
+#define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x2
+#define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x1
+#define SRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x4
+#define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x2
+#define SRBM_STATUS2__VCE0_RQ_PENDING_MASK 0x8
+#define SRBM_STATUS2__VCE0_RQ_PENDING__SHIFT 0x3
+#define SRBM_STATUS2__XSP_BUSY_MASK 0x10
+#define SRBM_STATUS2__XSP_BUSY__SHIFT 0x4
+#define SRBM_STATUS2__SDMA_BUSY_MASK 0x20
+#define SRBM_STATUS2__SDMA_BUSY__SHIFT 0x5
+#define SRBM_STATUS2__SDMA1_BUSY_MASK 0x40
+#define SRBM_STATUS2__SDMA1_BUSY__SHIFT 0x6
+#define SRBM_STATUS2__VCE0_BUSY_MASK 0x80
+#define SRBM_STATUS2__VCE0_BUSY__SHIFT 0x7
+#define SRBM_STATUS2__XDMA_BUSY_MASK 0x100
+#define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x8
+#define SRBM_STATUS2__CHUB_BUSY_MASK 0x200
+#define SRBM_STATUS2__CHUB_BUSY__SHIFT 0x9
+#define SRBM_STATUS2__SDMA2_BUSY_MASK 0x400
+#define SRBM_STATUS2__SDMA2_BUSY__SHIFT 0xa
+#define SRBM_STATUS2__SDMA3_BUSY_MASK 0x800
+#define SRBM_STATUS2__SDMA3_BUSY__SHIFT 0xb
+#define SRBM_STATUS2__SAMSCP_BUSY_MASK 0x1000
+#define SRBM_STATUS2__SAMSCP_BUSY__SHIFT 0xc
+#define SRBM_STATUS2__ISP_BUSY_MASK 0x2000
+#define SRBM_STATUS2__ISP_BUSY__SHIFT 0xd
+#define SRBM_STATUS2__VCE1_BUSY_MASK 0x4000
+#define SRBM_STATUS2__VCE1_BUSY__SHIFT 0xe
+#define SRBM_STATUS2__SDMA2_RQ_PENDING_MASK 0x10000
+#define SRBM_STATUS2__SDMA2_RQ_PENDING__SHIFT 0x10
+#define SRBM_STATUS2__SDMA3_RQ_PENDING_MASK 0x20000
+#define SRBM_STATUS2__SDMA3_RQ_PENDING__SHIFT 0x11
+#define SRBM_STATUS2__SAMSCP_RQ_PENDING_MASK 0x40000
+#define SRBM_STATUS2__SAMSCP_RQ_PENDING__SHIFT 0x12
+#define SRBM_STATUS2__ISP_RQ_PENDING_MASK 0x80000
+#define SRBM_STATUS2__ISP_RQ_PENDING__SHIFT 0x13
+#define SRBM_STATUS2__VCE1_RQ_PENDING_MASK 0x100000
+#define SRBM_STATUS2__VCE1_RQ_PENDING__SHIFT 0x14
+#define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x2
+#define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x1
+#define SRBM_STATUS__SAMMSP_RQ_PENDING_MASK 0x4
+#define SRBM_STATUS__SAMMSP_RQ_PENDING__SHIFT 0x2
+#define SRBM_STATUS__ACP_RQ_PENDING_MASK 0x8
+#define SRBM_STATUS__ACP_RQ_PENDING__SHIFT 0x3
+#define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x10
+#define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x4
+#define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x20
+#define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x5
+#define SRBM_STATUS__HI_RQ_PENDING_MASK 0x40
+#define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x6
+#define SRBM_STATUS__VMC_BUSY_MASK 0x100
+#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8
+#define SRBM_STATUS__MCB_BUSY_MASK 0x200
+#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9
+#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400
+#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa
+#define SRBM_STATUS__MCC_BUSY_MASK 0x800
+#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb
+#define SRBM_STATUS__MCD_BUSY_MASK 0x1000
+#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc
+#define SRBM_STATUS__VMC1_BUSY_MASK 0x2000
+#define SRBM_STATUS__VMC1_BUSY__SHIFT 0xd
+#define SRBM_STATUS__SEM_BUSY_MASK 0x4000
+#define SRBM_STATUS__SEM_BUSY__SHIFT 0xe
+#define SRBM_STATUS__ACP_BUSY_MASK 0x10000
+#define SRBM_STATUS__ACP_BUSY__SHIFT 0x10
+#define SRBM_STATUS__IH_BUSY_MASK 0x20000
+#define SRBM_STATUS__IH_BUSY__SHIFT 0x11
+#define SRBM_STATUS__UVD_BUSY_MASK 0x80000
+#define SRBM_STATUS__UVD_BUSY__SHIFT 0x13
+#define SRBM_STATUS__SAMMSP_BUSY_MASK 0x100000
+#define SRBM_STATUS__SAMMSP_BUSY__SHIFT 0x14
+#define SRBM_STATUS__GCATCL2_BUSY_MASK 0x200000
+#define SRBM_STATUS__GCATCL2_BUSY__SHIFT 0x15
+#define SRBM_STATUS__OSATCL2_BUSY_MASK 0x400000
+#define SRBM_STATUS__OSATCL2_BUSY__SHIFT 0x16
+#define SRBM_STATUS__BIF_BUSY_MASK 0x20000000
+#define SRBM_STATUS__BIF_BUSY__SHIFT 0x1d
+#define SRBM_STATUS3__MCC0_BUSY_MASK 0x1
+#define SRBM_STATUS3__MCC0_BUSY__SHIFT 0x0
+#define SRBM_STATUS3__MCC1_BUSY_MASK 0x2
+#define SRBM_STATUS3__MCC1_BUSY__SHIFT 0x1
+#define SRBM_STATUS3__MCC2_BUSY_MASK 0x4
+#define SRBM_STATUS3__MCC2_BUSY__SHIFT 0x2
+#define SRBM_STATUS3__MCC3_BUSY_MASK 0x8
+#define SRBM_STATUS3__MCC3_BUSY__SHIFT 0x3
+#define SRBM_STATUS3__MCC4_BUSY_MASK 0x10
+#define SRBM_STATUS3__MCC4_BUSY__SHIFT 0x4
+#define SRBM_STATUS3__MCC5_BUSY_MASK 0x20
+#define SRBM_STATUS3__MCC5_BUSY__SHIFT 0x5
+#define SRBM_STATUS3__MCC6_BUSY_MASK 0x40
+#define SRBM_STATUS3__MCC6_BUSY__SHIFT 0x6
+#define SRBM_STATUS3__MCC7_BUSY_MASK 0x80
+#define SRBM_STATUS3__MCC7_BUSY__SHIFT 0x7
+#define SRBM_STATUS3__MCD0_BUSY_MASK 0x100
+#define SRBM_STATUS3__MCD0_BUSY__SHIFT 0x8
+#define SRBM_STATUS3__MCD1_BUSY_MASK 0x200
+#define SRBM_STATUS3__MCD1_BUSY__SHIFT 0x9
+#define SRBM_STATUS3__MCD2_BUSY_MASK 0x400
+#define SRBM_STATUS3__MCD2_BUSY__SHIFT 0xa
+#define SRBM_STATUS3__MCD3_BUSY_MASK 0x800
+#define SRBM_STATUS3__MCD3_BUSY__SHIFT 0xb
+#define SRBM_STATUS3__MCD4_BUSY_MASK 0x1000
+#define SRBM_STATUS3__MCD4_BUSY__SHIFT 0xc
+#define SRBM_STATUS3__MCD5_BUSY_MASK 0x2000
+#define SRBM_STATUS3__MCD5_BUSY__SHIFT 0xd
+#define SRBM_STATUS3__MCD6_BUSY_MASK 0x4000
+#define SRBM_STATUS3__MCD6_BUSY__SHIFT 0xe
+#define SRBM_STATUS3__MCD7_BUSY_MASK 0x8000
+#define SRBM_STATUS3__MCD7_BUSY__SHIFT 0xf
+#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2_MASK 0x1
+#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2__SHIFT 0x0
+#define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x2
+#define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x1
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3_MASK 0x4
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3__SHIFT 0x2
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2_MASK 0x8
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2__SHIFT 0x3
+#define SRBM_SOFT_RESET__SOFT_RESET_ROPLL_MASK 0x10
+#define SRBM_SOFT_RESET__SOFT_RESET_ROPLL__SHIFT 0x4
+#define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x20
+#define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x5
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x40
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x6
+#define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x100
+#define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x8
+#define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x200
+#define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x9
+#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400
+#define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa
+#define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x800
+#define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0xb
+#define SRBM_SOFT_RESET__SOFT_RESET_CHUB_MASK 0x1000
+#define SRBM_SOFT_RESET__SOFT_RESET_CHUB__SHIFT 0xc
+#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM_MASK 0x2000
+#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM__SHIFT 0xd
+#define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x4000
+#define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0xe
+#define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x8000
+#define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0xf
+#define SRBM_SOFT_RESET__SOFT_RESET_SMU_MASK 0x10000
+#define SRBM_SOFT_RESET__SOFT_RESET_SMU__SHIFT 0x10
+#define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x20000
+#define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x11
+#define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x40000
+#define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x12
+#define SRBM_SOFT_RESET__SOFT_RESET_XSP_MASK 0x80000
+#define SRBM_SOFT_RESET__SOFT_RESET_XSP__SHIFT 0x13
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK 0x100000
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA__SHIFT 0x14
+#define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x200000
+#define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x15
+#define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x400000
+#define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x16
+#define SRBM_SOFT_RESET__SOFT_RESET_ORB_MASK 0x800000
+#define SRBM_SOFT_RESET__SOFT_RESET_ORB__SHIFT 0x17
+#define SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK 0x1000000
+#define SRBM_SOFT_RESET__SOFT_RESET_VCE0__SHIFT 0x18
+#define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x2000000
+#define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x19
+#define SRBM_SOFT_RESET__SOFT_RESET_ACP_MASK 0x4000000
+#define SRBM_SOFT_RESET__SOFT_RESET_ACP__SHIFT 0x1a
+#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP_MASK 0x8000000
+#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP__SHIFT 0x1b
+#define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP_MASK 0x10000000
+#define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP__SHIFT 0x1c
+#define SRBM_SOFT_RESET__SOFT_RESET_GRN_MASK 0x20000000
+#define SRBM_SOFT_RESET__SOFT_RESET_GRN__SHIFT 0x1d
+#define SRBM_SOFT_RESET__SOFT_RESET_ISP_MASK 0x40000000
+#define SRBM_SOFT_RESET__SOFT_RESET_ISP__SHIFT 0x1e
+#define SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK 0x80000000
+#define SRBM_SOFT_RESET__SOFT_RESET_VCE1__SHIFT 0x1f
+#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x3f
+#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x0
+#define SRBM_DEBUG_DATA__DATA_MASK 0xffffffff
+#define SRBM_DEBUG_DATA__DATA__SHIFT 0x0
+#define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0xff
+#define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0
+#define CC_SYS_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
+#define CC_SYS_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
+#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
+#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
+#define CC_SYS_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
+#define CC_SYS_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
+#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
+#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
+#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
+#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
+#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
+#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
+#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_DEBUG__IGNORE_RDY_MASK 0x1
+#define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x0
+#define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x2
+#define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x1
+#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x4
+#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x2
+#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x10
+#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x4
+#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x20
+#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x5
+#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x40
+#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x6
+#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE_MASK 0x80
+#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x7
+#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x100
+#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x8
+#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE_MASK 0x200
+#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x9
+#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE_MASK 0x400
+#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xa
+#define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x1
+#define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x0
+#define SRBM_DEBUG_SNAPSHOT__ROPLL_RDY_MASK 0x2
+#define SRBM_DEBUG_SNAPSHOT__ROPLL_RDY__SHIFT 0x1
+#define SRBM_DEBUG_SNAPSHOT__SMU_RDY_MASK 0x4
+#define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT 0x2
+#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY_MASK 0x8
+#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY__SHIFT 0x3
+#define SRBM_DEBUG_SNAPSHOT__ACP_RDY_MASK 0x10
+#define SRBM_DEBUG_SNAPSHOT__ACP_RDY__SHIFT 0x4
+#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x20
+#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x5
+#define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x40
+#define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x6
+#define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x80
+#define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x7
+#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x100
+#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x8
+#define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x200
+#define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x9
+#define SRBM_DEBUG_SNAPSHOT__XSP_RDY_MASK 0x400
+#define SRBM_DEBUG_SNAPSHOT__XSP_RDY__SHIFT 0xa
+#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x800
+#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0xb
+#define SRBM_DEBUG_SNAPSHOT__ORB_RDY_MASK 0x1000
+#define SRBM_DEBUG_SNAPSHOT__ORB_RDY__SHIFT 0xc
+#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x2000
+#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0xd
+#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x4000
+#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0xe
+#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x8000
+#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0xf
+#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x10000
+#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x10
+#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x20000
+#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x11
+#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x40000
+#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x12
+#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x80000
+#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x13
+#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x100000
+#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x14
+#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x200000
+#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x15
+#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x400000
+#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x16
+#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x800000
+#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x17
+#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x1000000
+#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x18
+#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x2000000
+#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x19
+#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x4000000
+#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x1a
+#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x8000000
+#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x1b
+#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000
+#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x1c
+#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY_MASK 0x20000000
+#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY__SHIFT 0x1d
+#define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY_MASK 0x40000000
+#define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY__SHIFT 0x1e
+#define SRBM_DEBUG_SNAPSHOT__ISP_RDY_MASK 0x80000000
+#define SRBM_DEBUG_SNAPSHOT__ISP_RDY__SHIFT 0x1f
+#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY_MASK 0x1
+#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY__SHIFT 0x0
+#define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc
+#define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3_MASK 0x40000
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3__SHIFT 0x12
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2_MASK 0x80000
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2__SHIFT 0x13
+#define SRBM_READ_ERROR__READ_REQUESTER_VCE0_MASK 0x100000
+#define SRBM_READ_ERROR__READ_REQUESTER_VCE0__SHIFT 0x14
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1_MASK 0x200000
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1__SHIFT 0x15
+#define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x400000
+#define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x16
+#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP_MASK 0x800000
+#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP__SHIFT 0x17
+#define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x1000000
+#define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x18
+#define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x2000000
+#define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x19
+#define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x4000000
+#define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x1a
+#define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP_MASK 0x8000000
+#define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP__SHIFT 0x1b
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA_MASK 0x10000000
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA__SHIFT 0x1c
+#define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000
+#define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x1d
+#define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000
+#define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
+#define SRBM_READ_ERROR2__READ_REQUESTER_ACP_MASK 0x1
+#define SRBM_READ_ERROR2__READ_REQUESTER_ACP__SHIFT 0x0
+#define SRBM_READ_ERROR2__READ_REQUESTER_ISP_MASK 0x2
+#define SRBM_READ_ERROR2__READ_REQUESTER_ISP__SHIFT 0x1
+#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1_MASK 0x4
+#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1__SHIFT 0x2
+#define SRBM_READ_ERROR2__READ_VF_MASK 0x800000
+#define SRBM_READ_ERROR2__READ_VF__SHIFT 0x17
+#define SRBM_READ_ERROR2__READ_VFID_MASK 0xf000000
+#define SRBM_READ_ERROR2__READ_VFID__SHIFT 0x18
+#define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x1
+#define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x0
+#define SRBM_INT_CNTL__RAERR_INT_MASK_MASK 0x2
+#define SRBM_INT_CNTL__RAERR_INT_MASK__SHIFT 0x1
+#define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x1
+#define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x0
+#define SRBM_INT_STATUS__RAERR_INT_STAT_MASK 0x2
+#define SRBM_INT_STATUS__RAERR_INT_STAT__SHIFT 0x1
+#define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x1
+#define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x0
+#define SRBM_INT_ACK__RAERR_INT_ACK_MASK 0x2
+#define SRBM_INT_ACK__RAERR_INT_ACK__SHIFT 0x1
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF_MASK 0x1
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF__SHIFT 0x0
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP_MASK 0x2
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP__SHIFT 0x1
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP_MASK 0x4
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP__SHIFT 0x2
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP_MASK 0x8
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP__SHIFT 0x3
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST_MASK 0x20
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST__SHIFT 0x5
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3_MASK 0x40
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3__SHIFT 0x6
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2_MASK 0x80
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2__SHIFT 0x7
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1_MASK 0x100
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1__SHIFT 0x8
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0_MASK 0x200
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0__SHIFT 0x9
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD_MASK 0x400
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD__SHIFT 0xa
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0_MASK 0x800
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0__SHIFT 0xb
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM_MASK 0x1000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM__SHIFT 0xc
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU_MASK 0x2000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU__SHIFT 0xd
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER_MASK 0x4000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER__SHIFT 0xe
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU_MASK 0x8000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU__SHIFT 0xf
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP_MASK 0x10000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP__SHIFT 0x10
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1_MASK 0x20000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1__SHIFT 0x11
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP_MASK 0x40000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP__SHIFT 0x12
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP_MASK 0x80000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP__SHIFT 0x13
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP_MASK 0x100000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP__SHIFT 0x14
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION_MASK 0x1000000
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION__SHIFT 0x18
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW_MASK 0x2000000
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW__SHIFT 0x19
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW_MASK 0x4000000
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW__SHIFT 0x1a
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW_MASK 0x8000000
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW__SHIFT 0x1b
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION_MASK 0x10000000
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION__SHIFT 0x1c
+#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS_MASK 0x3fffc
+#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS__SHIFT 0x2
+#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF_MASK 0x80000
+#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF__SHIFT 0x13
+#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID_MASK 0xf00000
+#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID__SHIFT 0x14
+#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION_MASK 0x80000000
+#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION__SHIFT 0x1f
+#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR_MASK 0xffff
+#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR__SHIFT 0x0
+#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP_MASK 0x10000
+#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP__SHIFT 0x10
+#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD_MASK 0xffffffff
+#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD__SHIFT 0x0
+#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK_MASK 0xffff
+#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK__SHIFT 0x0
+#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK_MASK 0x10000
+#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK__SHIFT 0x10
+#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK_MASK 0xffffffff
+#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK__SHIFT 0x0
+#define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0xf
+#define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300
+#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
+#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
+#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
+#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
+#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
+#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffff
+#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x0
+#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffff
+#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x0
+#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffff
+#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x0
+#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffff
+#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x0
+#define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x3
+#define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
+#define SRBM_CAM_DATA__CAM_ADDR_MASK 0xffff
+#define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
+#define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
+#define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
+#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
+#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
+#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
+#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
+#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
+#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
+#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
+#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
+#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
+#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
+#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
+#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
+#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff
+#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0
+#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000
+#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10
+#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff
+#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0
+#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000
+#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10
+#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff
+#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0
+#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000
+#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10
+#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff
+#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0
+#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000
+#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10
+#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
+#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
+#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
+#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
+#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
+#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
+#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
+#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
+#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
+#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
+#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
+#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
+#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff
+#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0
+#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000
+#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10
+#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff
+#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0
+#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000
+#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10
+#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff
+#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0
+#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000
+#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10
+#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff
+#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0
+#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000
+#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10
+#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
+#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
+#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
+#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
+#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
+#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
+#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
+#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
+#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
+#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
+#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
+#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
+#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff
+#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0
+#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000
+#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10
+#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
+#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
+#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
+#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
+#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
+#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
+#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
+#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
+#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
+#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
+#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
+#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
+#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
+#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
+#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
+#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
+#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
+#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
+#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
+#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
+#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
+#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
+#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
+#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
+#define SRBM_SAM_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
+#define SRBM_SAM_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
+#define SRBM_SAM_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
+#define SRBM_SAM_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
+#define SRBM_SAM_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
+#define SRBM_SAM_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
+#define SRBM_SAM_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
+#define SRBM_SAM_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
+#define SRBM_SAM_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
+#define SRBM_SAM_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
+#define SRBM_SAM_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
+#define SRBM_SAM_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
+#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
+#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
+#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
+#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
+#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
+#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
+#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
+#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
+#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
+#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
+#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
+#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
+#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL_MASK 0xf
+#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL__SHIFT 0x0
+#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX_MASK 0xff
+#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX__SHIFT 0x0
+#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX_MASK 0xff00
+#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX__SHIFT 0x8
+#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX_MASK 0xff0000
+#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT 0x10
+#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK 0x20000000
+#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d
+#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000
+#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
+#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES_MASK 0x80000000
+#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f
+#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL_MASK 0xf
+#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL__SHIFT 0x0
+#define SRBM_GFX_CNTL_DATA__PIPEID_MASK 0x3
+#define SRBM_GFX_CNTL_DATA__PIPEID__SHIFT 0x0
+#define SRBM_GFX_CNTL_DATA__MEID_MASK 0xc
+#define SRBM_GFX_CNTL_DATA__MEID__SHIFT 0x2
+#define SRBM_GFX_CNTL_DATA__VMID_MASK 0xf0
+#define SRBM_GFX_CNTL_DATA__VMID__SHIFT 0x4
+#define SRBM_GFX_CNTL_DATA__QUEUEID_MASK 0x700
+#define SRBM_GFX_CNTL_DATA__QUEUEID__SHIFT 0x8
+#define SRBM_VF_ENABLE__VF_ENABLE_MASK 0x1
+#define SRBM_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE_MASK 0x1
+#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE__SHIFT 0x0
+#define SRBM_VIRT_RESET_REQ__VF_MASK 0xffff
+#define SRBM_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define SRBM_VIRT_RESET_REQ__PF_MASK 0x80000000
+#define SRBM_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define SDMA0_UCODE_ADDR__VALUE_MASK 0xfff
+#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0
+#define SDMA0_UCODE_DATA__VALUE_MASK 0xffffffff
+#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0
+#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100
+#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
+#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0xf
+#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x1
+#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0
+#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4
+#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
+#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x8
+#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
+#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x10
+#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800
+#define SDMA0_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb
+#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000
+#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
+#define SDMA0_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000
+#define SDMA0_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16
+#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000
+#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
+#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000
+#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
+#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000
+#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
+#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
+#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
+#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2
+#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
+#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4
+#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
+#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000
+#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
+#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000
+#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
+#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000
+#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
+#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000
+#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
+#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000
+#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
+#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000
+#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
+#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define SDMA0_HASH__CHANNEL_BITS_MASK 0x7
+#define SDMA0_HASH__CHANNEL_BITS__SHIFT 0x0
+#define SDMA0_HASH__BANK_BITS_MASK 0x70
+#define SDMA0_HASH__BANK_BITS__SHIFT 0x4
+#define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK 0x700
+#define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
+#define SDMA0_HASH__BANK_XOR_COUNT_MASK 0x7000
+#define SDMA0_HASH__BANK_XOR_COUNT__SHIFT 0xc
+#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff
+#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
+#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc
+#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
+#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc
+#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
+#define SDMA0_PROGRAM__STREAM_MASK 0xffffffff
+#define SDMA0_PROGRAM__STREAM__SHIFT 0x0
+#define SDMA0_STATUS_REG__IDLE_MASK 0x1
+#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0
+#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x2
+#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
+#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x4
+#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2
+#define SDMA0_STATUS_REG__RB_FULL_MASK 0x8
+#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3
+#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x10
+#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
+#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x20
+#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
+#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x40
+#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
+#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x80
+#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
+#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x100
+#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
+#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x200
+#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9
+#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x400
+#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
+#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
+#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
+#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x1000
+#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc
+#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x2000
+#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
+#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x4000
+#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe
+#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000
+#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
+#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000
+#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
+#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000
+#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
+#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000
+#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
+#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x80000
+#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
+#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000
+#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
+#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000
+#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
+#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000
+#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
+#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000
+#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
+#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x4000000
+#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a
+#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000
+#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
+#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000
+#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
+#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000
+#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e
+#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000
+#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
+#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
+#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
+#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x2
+#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
+#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4
+#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
+#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8
+#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
+#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x10
+#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
+#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x20
+#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
+#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x40
+#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
+#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x200
+#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
+#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400
+#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
+#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x2000
+#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
+#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000
+#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
+#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x20000
+#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
+#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x40000
+#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
+#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
+#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9
+#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
+#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
+#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
+#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
+#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA0_F32_CNTL__HALT_MASK 0x1
+#define SDMA0_F32_CNTL__HALT__SHIFT 0x0
+#define SDMA0_F32_CNTL__STEP_MASK 0x2
+#define SDMA0_F32_CNTL__STEP__SHIFT 0x1
+#define SDMA0_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc
+#define SDMA0_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2
+#define SDMA0_FREEZE__FREEZE_MASK 0x10
+#define SDMA0_FREEZE__FREEZE__SHIFT 0x4
+#define SDMA0_FREEZE__FROZEN_MASK 0x20
+#define SDMA0_FREEZE__FROZEN__SHIFT 0x5
+#define SDMA0_FREEZE__F32_FREEZE_MASK 0x40
+#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6
+#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0xf
+#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00
+#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000
+#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0xf
+#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00
+#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000
+#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA_POWER_GATING__PG_CNTL_ENABLE_MASK 0x1
+#define SDMA_POWER_GATING__PG_CNTL_ENABLE__SHIFT 0x0
+#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK 0x2
+#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE__SHIFT 0x1
+#define SDMA_POWER_GATING__PG_STATE_VALID_MASK 0x4
+#define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT 0x2
+#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x30
+#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4
+#define SDMA_POWER_GATING__SDMA0_ON_CONDITION_MASK 0x40
+#define SDMA_POWER_GATING__SDMA0_ON_CONDITION__SHIFT 0x6
+#define SDMA_POWER_GATING__SDMA1_ON_CONDITION_MASK 0x80
+#define SDMA_POWER_GATING__SDMA1_ON_CONDITION__SHIFT 0x7
+#define SDMA_POWER_GATING__POWER_OFF_DELAY_MASK 0xfff00
+#define SDMA_POWER_GATING__POWER_OFF_DELAY__SHIFT 0x8
+#define SDMA_POWER_GATING__POWER_ON_DELAY_MASK 0xfff00000
+#define SDMA_POWER_GATING__POWER_ON_DELAY__SHIFT 0x14
+#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0xff
+#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
+#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x100
+#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
+#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x200
+#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
+#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x400
+#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
+#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x800
+#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
+#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x1000
+#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc
+#define SDMA_PGFSM_CONFIG__READ_MASK 0x2000
+#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd
+#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000
+#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
+#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000
+#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
+#define SDMA_PGFSM_WRITE__VALUE_MASK 0xffffffff
+#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0
+#define SDMA_PGFSM_READ__VALUE_MASK 0xffffff
+#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0
+#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x2
+#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4
+#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
+#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x3ff
+#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0
+#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000
+#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
+#define SDMA0_ID__DEVICE_ID_MASK 0xff
+#define SDMA0_ID__DEVICE_ID__SHIFT 0x0
+#define SDMA0_VERSION__VALUE_MASK 0xffff
+#define SDMA0_VERSION__VALUE__SHIFT 0x0
+#define SDMA0_STATUS2_REG__ID_MASK 0x3
+#define SDMA0_STATUS2_REG__ID__SHIFT 0x0
+#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0xfffc
+#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
+#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xffff0000
+#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10
+#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_GFX_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
+#define SDMA0_GFX_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1
+#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000
+#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
+#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000
+#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
+#define SDMA0_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA0_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA0_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA0_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA0_GFX_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA0_GFX_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA0_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA0_GFX_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff
+#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff
+#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x1
+#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
+#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1
+#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC0_DOORBELL__OFFSET_MASK 0x1fffff
+#define SDMA0_RLC0_DOORBELL__OFFSET__SHIFT 0x0
+#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000
+#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000
+#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA0_RLC0_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA0_RLC0_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA0_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
+#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc
+#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff
+#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff
+#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1
+#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
+#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1
+#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC1_DOORBELL__OFFSET_MASK 0x1fffff
+#define SDMA0_RLC1_DOORBELL__OFFSET__SHIFT 0x0
+#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000
+#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000
+#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA0_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA0_RLC1_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA0_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
+#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc
+#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff
+#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff
+#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1
+#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_UCODE_ADDR__VALUE_MASK 0xfff
+#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0
+#define SDMA1_UCODE_DATA__VALUE_MASK 0xffffffff
+#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0
+#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100
+#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
+#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0xf
+#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x1
+#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0
+#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4
+#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
+#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x8
+#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
+#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x10
+#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800
+#define SDMA1_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb
+#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000
+#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
+#define SDMA1_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000
+#define SDMA1_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16
+#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000
+#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
+#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000
+#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
+#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000
+#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
+#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
+#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
+#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2
+#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
+#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4
+#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
+#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000
+#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
+#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000
+#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
+#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000
+#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
+#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000
+#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
+#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000
+#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
+#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000
+#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
+#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define SDMA1_HASH__CHANNEL_BITS_MASK 0x7
+#define SDMA1_HASH__CHANNEL_BITS__SHIFT 0x0
+#define SDMA1_HASH__BANK_BITS_MASK 0x70
+#define SDMA1_HASH__BANK_BITS__SHIFT 0x4
+#define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK 0x700
+#define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
+#define SDMA1_HASH__BANK_XOR_COUNT_MASK 0x7000
+#define SDMA1_HASH__BANK_XOR_COUNT__SHIFT 0xc
+#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff
+#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
+#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc
+#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
+#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc
+#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
+#define SDMA1_PROGRAM__STREAM_MASK 0xffffffff
+#define SDMA1_PROGRAM__STREAM__SHIFT 0x0
+#define SDMA1_STATUS_REG__IDLE_MASK 0x1
+#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0
+#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x2
+#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1
+#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x4
+#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2
+#define SDMA1_STATUS_REG__RB_FULL_MASK 0x8
+#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3
+#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x10
+#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
+#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x20
+#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
+#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x40
+#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
+#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x80
+#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
+#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x100
+#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
+#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x200
+#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9
+#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x400
+#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa
+#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
+#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
+#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x1000
+#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc
+#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x2000
+#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
+#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x4000
+#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe
+#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000
+#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
+#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000
+#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
+#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000
+#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
+#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000
+#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
+#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x80000
+#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
+#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000
+#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
+#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000
+#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
+#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000
+#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
+#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000
+#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
+#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x4000000
+#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a
+#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000
+#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
+#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000
+#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
+#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000
+#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e
+#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000
+#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
+#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
+#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
+#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2
+#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
+#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4
+#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
+#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8
+#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
+#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x10
+#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
+#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x20
+#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
+#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x40
+#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
+#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x200
+#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
+#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400
+#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
+#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x2000
+#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
+#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000
+#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
+#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x20000
+#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
+#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x40000
+#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
+#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
+#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9
+#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
+#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
+#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
+#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
+#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA1_F32_CNTL__HALT_MASK 0x1
+#define SDMA1_F32_CNTL__HALT__SHIFT 0x0
+#define SDMA1_F32_CNTL__STEP_MASK 0x2
+#define SDMA1_F32_CNTL__STEP__SHIFT 0x1
+#define SDMA1_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc
+#define SDMA1_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2
+#define SDMA1_FREEZE__FREEZE_MASK 0x10
+#define SDMA1_FREEZE__FREEZE__SHIFT 0x4
+#define SDMA1_FREEZE__FROZEN_MASK 0x20
+#define SDMA1_FREEZE__FROZEN__SHIFT 0x5
+#define SDMA1_FREEZE__F32_FREEZE_MASK 0x40
+#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6
+#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0xf
+#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0xffff00
+#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000
+#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0xf
+#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0xffff00
+#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000
+#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x2
+#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4
+#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
+#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x3ff
+#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0
+#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000
+#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
+#define SDMA1_ID__DEVICE_ID_MASK 0xff
+#define SDMA1_ID__DEVICE_ID__SHIFT 0x0
+#define SDMA1_VERSION__VALUE_MASK 0xffff
+#define SDMA1_VERSION__VALUE__SHIFT 0x0
+#define SDMA1_STATUS2_REG__ID_MASK 0x3
+#define SDMA1_STATUS2_REG__ID__SHIFT 0x0
+#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0xfffc
+#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
+#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xffff0000
+#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10
+#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_GFX_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
+#define SDMA1_GFX_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1
+#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000
+#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
+#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000
+#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
+#define SDMA1_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA1_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA1_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA1_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA1_GFX_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA1_GFX_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA1_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA1_GFX_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff
+#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff
+#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x1
+#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
+#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1
+#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC0_DOORBELL__OFFSET_MASK 0x1fffff
+#define SDMA1_RLC0_DOORBELL__OFFSET__SHIFT 0x0
+#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000
+#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000
+#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA1_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA1_RLC0_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA1_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA1_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
+#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc
+#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff
+#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff
+#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1
+#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
+#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1
+#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC1_DOORBELL__OFFSET_MASK 0x1fffff
+#define SDMA1_RLC1_DOORBELL__OFFSET__SHIFT 0x0
+#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000
+#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000
+#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA1_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA1_RLC1_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA1_RLC1_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA1_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA1_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
+#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc
+#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff
+#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff
+#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1
+#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x7
+#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x0
+#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x1f8
+#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x3
+#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x600
+#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9
+#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x1800
+#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x180000
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x200000
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15
+#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x400000
+#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x16
+#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x800000
+#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x17
+#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0xf000000
+#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x18
+#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000
+#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d
+#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000
+#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e
+#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000
+#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f
+#define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffff
+#define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x0
+#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x1
+#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x0
+#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x1e
+#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x1
+#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x60
+#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x5
+#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x380
+#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x7
+#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x1c00
+#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0xa
+#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x6000
+#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0xd
+#define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x8000
+#define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0xf
+#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x10000
+#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x10
+#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0xe0000
+#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x11
+#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x300000
+#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x14
+#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0xc00000
+#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x16
+#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x3000000
+#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x18
+#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0xc000000
+#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x1a
+#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x70000000
+#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x1c
+#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x80000000
+#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x1f
+#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x7ff
+#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x0
+#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800
+#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0xb
+#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x1
+#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0
+#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x2
+#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x1
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x2
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1
+#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffff
+#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0
+#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0
+#define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x0
+#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x3f
+#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0
+#define HDP_TILING_CONFIG__PIPE_TILING_MASK 0xe
+#define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x1
+#define HDP_TILING_CONFIG__BANK_TILING_MASK 0x30
+#define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x4
+#define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0xc0
+#define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x6
+#define HDP_TILING_CONFIG__ROW_TILING_MASK 0x700
+#define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x8
+#define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x3800
+#define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0xb
+#define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0xc000
+#define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0xe
+#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x7
+#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x0
+#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x18
+#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x3
+#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0xff
+#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0
+#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0xff00
+#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8
+#define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x1
+#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0
+#define HDP_MISC_CNTL__VM_ID_MASK 0x1e
+#define HDP_MISC_CNTL__VM_ID__SHIFT 0x1
+#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x20
+#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5
+#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x40
+#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6
+#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x780
+#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x7
+#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x800
+#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb
+#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x1000
+#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0xc
+#define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x7e000
+#define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
+#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x80000
+#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x13
+#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x100000
+#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x14
+#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x200000
+#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15
+#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x1
+#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0
+#define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x7e
+#define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x1
+#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x1f80
+#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x7
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x0
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x38
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x3
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x1c0
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x6
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0xffe00
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x9
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x1b
+#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x1
+#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0
+#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x2
+#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1
+#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x3c
+#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2
+#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x40
+#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6
+#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x80
+#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7
+#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x3f00
+#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8
+#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x4000
+#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe
+#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x8000
+#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf
+#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffff
+#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0
+#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x1
+#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0
+#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x2
+#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1
+#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x4
+#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2
+#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x8
+#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3
+#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffff
+#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0
+#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffff
+#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0
+#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffff
+#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0xf
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0xf0
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x700
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0xf800
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x10000
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x20000
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x11
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x40000
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x80000
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x100000
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0xffff
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0xf0000
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x700000
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
+#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0
+#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffff
+#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0xf
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x30
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4
+#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x3fff
+#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x1
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x0
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x6
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x1
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x8
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x3
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0xf0
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x4
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x1
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x0
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x6
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x1
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x8
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x3
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x10
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x4
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x60
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x5
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x80
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x7
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x3f00
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x8
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0xfc000
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x700000
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x14
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x7800000
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x17
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x1b
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x1
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x6
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1
+#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x1
+#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x0
+#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x6
+#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x1
+#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x18
+#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x3
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x3f
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0xfc0
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x1000
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x2000
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x3f
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x0
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x40
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x6
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x80
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x7
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0xf
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x0
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0xff0
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x4
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0xc
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x1e
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x1f
+#define HDP_XDP_P2P_BAR0__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR0__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR1__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR1__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR2__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR2__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR3__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR3__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR4__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR4__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR5__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR5__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR6__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR6__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR7__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR7__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14
+#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffff
+#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0
+#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x3ffffff
+#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0
+#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x3ffff
+#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0
+#define HDP_XDP_STICKY__STICKY_STS_MASK 0xffff
+#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0
+#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000
+#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10
+#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0xff
+#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0
+#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0xff00
+#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8
+#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0xff0000
+#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10
+#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000
+#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18
+#define HDP_XDP_DBG_ADDR__STS_MASK 0xffff
+#define HDP_XDP_DBG_ADDR__STS__SHIFT 0x0
+#define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000
+#define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x10
+#define HDP_XDP_DBG_DATA__STS_MASK 0xffff
+#define HDP_XDP_DBG_DATA__STS__SHIFT 0x0
+#define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000
+#define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x10
+#define HDP_XDP_DBG_MASK__STS_MASK 0xffff
+#define HDP_XDP_DBG_MASK__STS__SHIFT 0x0
+#define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000
+#define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x10
+#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0xf
+#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0
+#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0xf0
+#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4
+#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0xf00
+#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8
+#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0xf000
+#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc
+#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0xf0000
+#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10
+#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0xf00000
+#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0xf000000
+#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18
+#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000
+#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c
+
+#endif /* OSS_2_4_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_d.h
new file mode 100644
index 000000000000..bdbb829c64fc
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_d.h
@@ -0,0 +1,593 @@
+/*
+ * OSS_3_0_1 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef OSS_3_0_1_D_H
+#define OSS_3_0_1_D_H
+
+#define mmIH_VMID_0_LUT 0xe00
+#define mmIH_VMID_1_LUT 0xe01
+#define mmIH_VMID_2_LUT 0xe02
+#define mmIH_VMID_3_LUT 0xe03
+#define mmIH_VMID_4_LUT 0xe04
+#define mmIH_VMID_5_LUT 0xe05
+#define mmIH_VMID_6_LUT 0xe06
+#define mmIH_VMID_7_LUT 0xe07
+#define mmIH_VMID_8_LUT 0xe08
+#define mmIH_VMID_9_LUT 0xe09
+#define mmIH_VMID_10_LUT 0xe0a
+#define mmIH_VMID_11_LUT 0xe0b
+#define mmIH_VMID_12_LUT 0xe0c
+#define mmIH_VMID_13_LUT 0xe0d
+#define mmIH_VMID_14_LUT 0xe0e
+#define mmIH_VMID_15_LUT 0xe0f
+#define mmIH_RB_CNTL 0xe30
+#define mmIH_RB_BASE 0xe31
+#define mmIH_RB_RPTR 0xe32
+#define mmIH_RB_WPTR 0xe33
+#define mmIH_RB_WPTR_ADDR_HI 0xe34
+#define mmIH_RB_WPTR_ADDR_LO 0xe35
+#define mmIH_CNTL 0xe36
+#define mmIH_LEVEL_STATUS 0xe37
+#define mmIH_STATUS 0xe38
+#define mmIH_PERFMON_CNTL 0xe39
+#define mmIH_PERFCOUNTER0_RESULT 0xe3a
+#define mmIH_PERFCOUNTER1_RESULT 0xe3b
+#define mmIH_DSM_MATCH_VALUE_BIT_31_0 0xe3d
+#define mmIH_DSM_MATCH_VALUE_BIT_63_32 0xe3e
+#define mmIH_DSM_MATCH_VALUE_BIT_95_64 0xe3f
+#define mmIH_DSM_MATCH_FIELD_CONTROL 0xe40
+#define mmIH_DSM_MATCH_DATA_CONTROL 0xe41
+#define mmIH_VERSION 0xe48
+#define mmSEM_MCIF_CONFIG 0xf90
+#define mmSEM_PERFMON_CNTL 0xf91
+#define mmSEM_PERFCOUNTER0_RESULT 0xf92
+#define mmSEM_PERFCOUNTER1_RESULT 0xf93
+#define mmSEM_VF_ENABLE 0xf95
+#define mmSEM_ACTIVE_FCN_ID 0xf97
+#define mmSEM_VIRT_RESET_REQ 0xf98
+#define mmSEM_STATUS 0xf99
+#define mmSEM_EDC_CONFIG 0xf9a
+#define mmSEM_MAILBOX_CLIENTCONFIG 0xf9b
+#define mmSEM_MAILBOX 0xf9c
+#define mmSEM_MAILBOX_CONTROL 0xf9d
+#define mmSEM_CHICKEN_BITS 0xf9e
+#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0xf9f
+#define mmSRBM_CNTL 0x390
+#define mmSRBM_GFX_CNTL 0x391
+#define mmSRBM_READ_CNTL 0x392
+#define mmSRBM_STATUS2 0x393
+#define mmSRBM_STATUS 0x394
+#define mmSRBM_STATUS3 0x395
+#define mmSRBM_SOFT_RESET 0x398
+#define mmSRBM_DEBUG_CNTL 0x399
+#define mmSRBM_DEBUG_DATA 0x39a
+#define mmSRBM_CHIP_REVISION 0x39b
+#define mmCC_SYS_RB_REDUNDANCY 0x39f
+#define mmCC_SYS_RB_BACKEND_DISABLE 0x3a0
+#define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x3a1
+#define mmSRBM_MC_CLKEN_CNTL 0x3b3
+#define mmSRBM_SYS_CLKEN_CNTL 0x3b4
+#define mmSRBM_VCE_CLKEN_CNTL 0x3b5
+#define mmSRBM_UVD_CLKEN_CNTL 0x3b6
+#define mmSRBM_SDMA_CLKEN_CNTL 0x3b7
+#define mmSRBM_SAM_CLKEN_CNTL 0x3b8
+#define mmSRBM_ISP_CLKEN_CNTL 0x3b9
+#define mmSRBM_VP8_CLKEN_CNTL 0x3ba
+#define mmSRBM_DEBUG 0x3a4
+#define mmSRBM_DEBUG_SNAPSHOT 0x3a5
+#define mmSRBM_DEBUG_SNAPSHOT2 0x3ad
+#define mmSRBM_READ_ERROR 0x3a6
+#define mmSRBM_READ_ERROR2 0x3ae
+#define mmSRBM_INT_CNTL 0x3a8
+#define mmSRBM_INT_STATUS 0x3a9
+#define mmSRBM_INT_ACK 0x3aa
+#define mmSRBM_FIREWALL_ERROR_SRC 0x3ab
+#define mmSRBM_FIREWALL_ERROR_ADDR 0x3ac
+#define mmSRBM_DSM_TRIG_CNTL0 0x3af
+#define mmSRBM_DSM_TRIG_CNTL1 0x3b0
+#define mmSRBM_DSM_TRIG_MASK0 0x3b1
+#define mmSRBM_DSM_TRIG_MASK1 0x3b2
+#define mmSRBM_PERFMON_CNTL 0x7c00
+#define mmSRBM_PERFCOUNTER0_SELECT 0x7c01
+#define mmSRBM_PERFCOUNTER1_SELECT 0x7c02
+#define mmSRBM_PERFCOUNTER0_LO 0x7c03
+#define mmSRBM_PERFCOUNTER0_HI 0x7c04
+#define mmSRBM_PERFCOUNTER1_LO 0x7c05
+#define mmSRBM_PERFCOUNTER1_HI 0x7c06
+#define mmSRBM_CAM_INDEX 0xfe34
+#define mmSRBM_CAM_DATA 0xfe35
+#define mmSRBM_MC_DOMAIN_ADDR0 0xfa00
+#define mmSRBM_MC_DOMAIN_ADDR1 0xfa01
+#define mmSRBM_MC_DOMAIN_ADDR2 0xfa02
+#define mmSRBM_MC_DOMAIN_ADDR3 0xfa03
+#define mmSRBM_MC_DOMAIN_ADDR4 0xfa04
+#define mmSRBM_MC_DOMAIN_ADDR5 0xfa05
+#define mmSRBM_MC_DOMAIN_ADDR6 0xfa06
+#define mmSRBM_SYS_DOMAIN_ADDR0 0xfa08
+#define mmSRBM_SYS_DOMAIN_ADDR1 0xfa09
+#define mmSRBM_SYS_DOMAIN_ADDR2 0xfa0a
+#define mmSRBM_SYS_DOMAIN_ADDR3 0xfa0b
+#define mmSRBM_SYS_DOMAIN_ADDR4 0xfa0c
+#define mmSRBM_SYS_DOMAIN_ADDR5 0xfa0d
+#define mmSRBM_SYS_DOMAIN_ADDR6 0xfa0e
+#define mmSRBM_SDMA_DOMAIN_ADDR0 0xfa10
+#define mmSRBM_SDMA_DOMAIN_ADDR1 0xfa11
+#define mmSRBM_SDMA_DOMAIN_ADDR2 0xfa12
+#define mmSRBM_SDMA_DOMAIN_ADDR3 0xfa13
+#define mmSRBM_UVD_DOMAIN_ADDR0 0xfa14
+#define mmSRBM_UVD_DOMAIN_ADDR1 0xfa15
+#define mmSRBM_UVD_DOMAIN_ADDR2 0xfa16
+#define mmSRBM_VCE_DOMAIN_ADDR0 0xfa18
+#define mmSRBM_VCE_DOMAIN_ADDR1 0xfa19
+#define mmSRBM_VCE_DOMAIN_ADDR2 0xfa1a
+#define mmSRBM_ISP_DOMAIN_ADDR0 0xfa20
+#define mmSRBM_ISP_DOMAIN_ADDR1 0xfa21
+#define mmSRBM_ISP_DOMAIN_ADDR2 0xfa22
+#define mmSRBM_VP8_DOMAIN_ADDR0 0xfa24
+#define mmSYS_GRBM_GFX_INDEX_SELECT 0xfa2c
+#define mmSYS_GRBM_GFX_INDEX_DATA 0xfa2d
+#define mmSRBM_GFX_CNTL_SELECT 0xfa2e
+#define mmSRBM_GFX_CNTL_DATA 0xfa2f
+#define mmSRBM_VF_ENABLE 0xfa30
+#define mmSRBM_VIRT_CNTL 0xfa31
+#define mmSRBM_VIRT_RESET_REQ 0xfa32
+#define mmSDMA0_UCODE_ADDR 0x3400
+#define mmSDMA0_UCODE_DATA 0x3401
+#define mmSDMA0_POWER_CNTL 0x3402
+#define mmSDMA0_CLK_CTRL 0x3403
+#define mmSDMA0_CNTL 0x3404
+#define mmSDMA0_CHICKEN_BITS 0x3405
+#define mmSDMA0_TILING_CONFIG 0x3406
+#define mmSDMA0_HASH 0x3407
+#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409
+#define mmSDMA0_RB_RPTR_FETCH 0x340a
+#define mmSDMA0_IB_OFFSET_FETCH 0x340b
+#define mmSDMA0_PROGRAM 0x340c
+#define mmSDMA0_STATUS_REG 0x340d
+#define mmSDMA0_STATUS1_REG 0x340e
+#define mmSDMA0_RD_BURST_CNTL 0x340f
+#define mmSDMA0_PERFMON_CNTL 0x9000
+#define mmSDMA0_PERFCOUNTER0_RESULT 0x9001
+#define mmSDMA0_PERFCOUNTER1_RESULT 0x9002
+#define mmSDMA0_F32_CNTL 0x3412
+#define mmSDMA0_FREEZE 0x3413
+#define mmSDMA0_PHASE0_QUANTUM 0x3414
+#define mmSDMA0_PHASE1_QUANTUM 0x3415
+#define mmSDMA_POWER_GATING 0x3416
+#define mmSDMA_PGFSM_CONFIG 0x3417
+#define mmSDMA_PGFSM_WRITE 0x3418
+#define mmSDMA_PGFSM_READ 0x3419
+#define mmSDMA0_EDC_CONFIG 0x341a
+#define mmSDMA0_BA_THRESHOLD 0x341b
+#define mmSDMA0_ID 0x341c
+#define mmSDMA0_VERSION 0x341d
+#define mmSDMA0_VM_CNTL 0x3420
+#define mmSDMA0_VM_CTX_LO 0x3421
+#define mmSDMA0_VM_CTX_HI 0x3422
+#define mmSDMA0_STATUS2_REG 0x3423
+#define mmSDMA0_ACTIVE_FCN_ID 0x3424
+#define mmSDMA0_VM_CTX_CNTL 0x3425
+#define mmSDMA0_VIRT_RESET_REQ 0x3426
+#define mmSDMA0_VF_ENABLE 0x3427
+#define mmSDMA0_ATOMIC_CNTL 0x3428
+#define mmSDMA0_ATOMIC_PREOP_LO 0x3429
+#define mmSDMA0_ATOMIC_PREOP_HI 0x342a
+#define mmSDMA0_ATCL1_CNTL 0x342b
+#define mmSDMA0_ATCL1_WATERMK 0x342c
+#define mmSDMA0_ATCL1_RD_STATUS 0x342d
+#define mmSDMA0_ATCL1_WR_STATUS 0x342e
+#define mmSDMA0_ATCL1_INV0 0x342f
+#define mmSDMA0_ATCL1_INV1 0x3430
+#define mmSDMA0_ATCL1_INV2 0x3431
+#define mmSDMA0_ATCL1_RD_XNACK0 0x3432
+#define mmSDMA0_ATCL1_RD_XNACK1 0x3433
+#define mmSDMA0_ATCL1_WR_XNACK0 0x3434
+#define mmSDMA0_ATCL1_WR_XNACK1 0x3435
+#define mmSDMA0_ATCL1_TIMEOUT 0x3436
+#define mmSDMA0_POWER_CNTL_IDLE 0x3438
+#define mmSDMA0_PERF_REG_TYPE0 0x3477
+#define mmSDMA0_CONTEXT_REG_TYPE0 0x3478
+#define mmSDMA0_CONTEXT_REG_TYPE1 0x3479
+#define mmSDMA0_CONTEXT_REG_TYPE2 0x347a
+#define mmSDMA0_PUB_REG_TYPE0 0x347c
+#define mmSDMA0_PUB_REG_TYPE1 0x347d
+#define mmSDMA0_GFX_RB_CNTL 0x3480
+#define mmSDMA0_GFX_RB_BASE 0x3481
+#define mmSDMA0_GFX_RB_BASE_HI 0x3482
+#define mmSDMA0_GFX_RB_RPTR 0x3483
+#define mmSDMA0_GFX_RB_WPTR 0x3484
+#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487
+#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x3488
+#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x3489
+#define mmSDMA0_GFX_IB_CNTL 0x348a
+#define mmSDMA0_GFX_IB_RPTR 0x348b
+#define mmSDMA0_GFX_IB_OFFSET 0x348c
+#define mmSDMA0_GFX_IB_BASE_LO 0x348d
+#define mmSDMA0_GFX_IB_BASE_HI 0x348e
+#define mmSDMA0_GFX_IB_SIZE 0x348f
+#define mmSDMA0_GFX_SKIP_CNTL 0x3490
+#define mmSDMA0_GFX_CONTEXT_STATUS 0x3491
+#define mmSDMA0_GFX_DOORBELL 0x3492
+#define mmSDMA0_GFX_CONTEXT_CNTL 0x3493
+#define mmSDMA0_GFX_VIRTUAL_ADDR 0x34a7
+#define mmSDMA0_GFX_APE1_CNTL 0x34a8
+#define mmSDMA0_GFX_DOORBELL_LOG 0x34a9
+#define mmSDMA0_GFX_WATERMARK 0x34aa
+#define mmSDMA0_GFX_CSA_ADDR_LO 0x34ac
+#define mmSDMA0_GFX_CSA_ADDR_HI 0x34ad
+#define mmSDMA0_GFX_IB_SUB_REMAIN 0x34af
+#define mmSDMA0_GFX_PREEMPT 0x34b0
+#define mmSDMA0_GFX_DUMMY_REG 0x34b1
+#define mmSDMA0_GFX_MIDCMD_DATA0 0x34c1
+#define mmSDMA0_GFX_MIDCMD_DATA1 0x34c2
+#define mmSDMA0_GFX_MIDCMD_DATA2 0x34c3
+#define mmSDMA0_GFX_MIDCMD_DATA3 0x34c4
+#define mmSDMA0_GFX_MIDCMD_DATA4 0x34c5
+#define mmSDMA0_GFX_MIDCMD_DATA5 0x34c6
+#define mmSDMA0_GFX_MIDCMD_DATA6 0x34c7
+#define mmSDMA0_GFX_MIDCMD_DATA7 0x34c8
+#define mmSDMA0_GFX_MIDCMD_DATA8 0x34c9
+#define mmSDMA0_GFX_MIDCMD_CNTL 0x34ca
+#define mmSDMA0_RLC0_RB_CNTL 0x3500
+#define mmSDMA0_RLC0_RB_BASE 0x3501
+#define mmSDMA0_RLC0_RB_BASE_HI 0x3502
+#define mmSDMA0_RLC0_RB_RPTR 0x3503
+#define mmSDMA0_RLC0_RB_WPTR 0x3504
+#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x3506
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x3507
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x3508
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x3509
+#define mmSDMA0_RLC0_IB_CNTL 0x350a
+#define mmSDMA0_RLC0_IB_RPTR 0x350b
+#define mmSDMA0_RLC0_IB_OFFSET 0x350c
+#define mmSDMA0_RLC0_IB_BASE_LO 0x350d
+#define mmSDMA0_RLC0_IB_BASE_HI 0x350e
+#define mmSDMA0_RLC0_IB_SIZE 0x350f
+#define mmSDMA0_RLC0_SKIP_CNTL 0x3510
+#define mmSDMA0_RLC0_CONTEXT_STATUS 0x3511
+#define mmSDMA0_RLC0_DOORBELL 0x3512
+#define mmSDMA0_RLC0_VIRTUAL_ADDR 0x3527
+#define mmSDMA0_RLC0_APE1_CNTL 0x3528
+#define mmSDMA0_RLC0_DOORBELL_LOG 0x3529
+#define mmSDMA0_RLC0_WATERMARK 0x352a
+#define mmSDMA0_RLC0_CSA_ADDR_LO 0x352c
+#define mmSDMA0_RLC0_CSA_ADDR_HI 0x352d
+#define mmSDMA0_RLC0_IB_SUB_REMAIN 0x352f
+#define mmSDMA0_RLC0_PREEMPT 0x3530
+#define mmSDMA0_RLC0_DUMMY_REG 0x3531
+#define mmSDMA0_RLC0_MIDCMD_DATA0 0x3541
+#define mmSDMA0_RLC0_MIDCMD_DATA1 0x3542
+#define mmSDMA0_RLC0_MIDCMD_DATA2 0x3543
+#define mmSDMA0_RLC0_MIDCMD_DATA3 0x3544
+#define mmSDMA0_RLC0_MIDCMD_DATA4 0x3545
+#define mmSDMA0_RLC0_MIDCMD_DATA5 0x3546
+#define mmSDMA0_RLC0_MIDCMD_DATA6 0x3547
+#define mmSDMA0_RLC0_MIDCMD_DATA7 0x3548
+#define mmSDMA0_RLC0_MIDCMD_DATA8 0x3549
+#define mmSDMA0_RLC0_MIDCMD_CNTL 0x354a
+#define mmSDMA0_RLC1_RB_CNTL 0x3580
+#define mmSDMA0_RLC1_RB_BASE 0x3581
+#define mmSDMA0_RLC1_RB_BASE_HI 0x3582
+#define mmSDMA0_RLC1_RB_RPTR 0x3583
+#define mmSDMA0_RLC1_RB_WPTR 0x3584
+#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x3585
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x3586
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x3587
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x3588
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x3589
+#define mmSDMA0_RLC1_IB_CNTL 0x358a
+#define mmSDMA0_RLC1_IB_RPTR 0x358b
+#define mmSDMA0_RLC1_IB_OFFSET 0x358c
+#define mmSDMA0_RLC1_IB_BASE_LO 0x358d
+#define mmSDMA0_RLC1_IB_BASE_HI 0x358e
+#define mmSDMA0_RLC1_IB_SIZE 0x358f
+#define mmSDMA0_RLC1_SKIP_CNTL 0x3590
+#define mmSDMA0_RLC1_CONTEXT_STATUS 0x3591
+#define mmSDMA0_RLC1_DOORBELL 0x3592
+#define mmSDMA0_RLC1_VIRTUAL_ADDR 0x35a7
+#define mmSDMA0_RLC1_APE1_CNTL 0x35a8
+#define mmSDMA0_RLC1_DOORBELL_LOG 0x35a9
+#define mmSDMA0_RLC1_WATERMARK 0x35aa
+#define mmSDMA0_RLC1_CSA_ADDR_LO 0x35ac
+#define mmSDMA0_RLC1_CSA_ADDR_HI 0x35ad
+#define mmSDMA0_RLC1_IB_SUB_REMAIN 0x35af
+#define mmSDMA0_RLC1_PREEMPT 0x35b0
+#define mmSDMA0_RLC1_DUMMY_REG 0x35b1
+#define mmSDMA0_RLC1_MIDCMD_DATA0 0x35c1
+#define mmSDMA0_RLC1_MIDCMD_DATA1 0x35c2
+#define mmSDMA0_RLC1_MIDCMD_DATA2 0x35c3
+#define mmSDMA0_RLC1_MIDCMD_DATA3 0x35c4
+#define mmSDMA0_RLC1_MIDCMD_DATA4 0x35c5
+#define mmSDMA0_RLC1_MIDCMD_DATA5 0x35c6
+#define mmSDMA0_RLC1_MIDCMD_DATA6 0x35c7
+#define mmSDMA0_RLC1_MIDCMD_DATA7 0x35c8
+#define mmSDMA0_RLC1_MIDCMD_DATA8 0x35c9
+#define mmSDMA0_RLC1_MIDCMD_CNTL 0x35ca
+#define mmSDMA1_UCODE_ADDR 0x3600
+#define mmSDMA1_UCODE_DATA 0x3601
+#define mmSDMA1_POWER_CNTL 0x3602
+#define mmSDMA1_CLK_CTRL 0x3603
+#define mmSDMA1_CNTL 0x3604
+#define mmSDMA1_CHICKEN_BITS 0x3605
+#define mmSDMA1_TILING_CONFIG 0x3606
+#define mmSDMA1_HASH 0x3607
+#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x3609
+#define mmSDMA1_RB_RPTR_FETCH 0x360a
+#define mmSDMA1_IB_OFFSET_FETCH 0x360b
+#define mmSDMA1_PROGRAM 0x360c
+#define mmSDMA1_STATUS_REG 0x360d
+#define mmSDMA1_STATUS1_REG 0x360e
+#define mmSDMA1_RD_BURST_CNTL 0x360f
+#define mmSDMA1_PERFMON_CNTL 0x9010
+#define mmSDMA1_PERFCOUNTER0_RESULT 0x9011
+#define mmSDMA1_PERFCOUNTER1_RESULT 0x9012
+#define mmSDMA1_F32_CNTL 0x3612
+#define mmSDMA1_FREEZE 0x3613
+#define mmSDMA1_PHASE0_QUANTUM 0x3614
+#define mmSDMA1_PHASE1_QUANTUM 0x3615
+#define mmSDMA1_EDC_CONFIG 0x361a
+#define mmSDMA1_BA_THRESHOLD 0x361b
+#define mmSDMA1_ID 0x361c
+#define mmSDMA1_VERSION 0x361d
+#define mmSDMA1_VM_CNTL 0x3620
+#define mmSDMA1_VM_CTX_LO 0x3621
+#define mmSDMA1_VM_CTX_HI 0x3622
+#define mmSDMA1_STATUS2_REG 0x3623
+#define mmSDMA1_ACTIVE_FCN_ID 0x3624
+#define mmSDMA1_VM_CTX_CNTL 0x3625
+#define mmSDMA1_VIRT_RESET_REQ 0x3626
+#define mmSDMA1_VF_ENABLE 0x3627
+#define mmSDMA1_ATOMIC_CNTL 0x3628
+#define mmSDMA1_ATOMIC_PREOP_LO 0x3629
+#define mmSDMA1_ATOMIC_PREOP_HI 0x362a
+#define mmSDMA1_ATCL1_CNTL 0x362b
+#define mmSDMA1_ATCL1_WATERMK 0x362c
+#define mmSDMA1_ATCL1_RD_STATUS 0x362d
+#define mmSDMA1_ATCL1_WR_STATUS 0x362e
+#define mmSDMA1_ATCL1_INV0 0x362f
+#define mmSDMA1_ATCL1_INV1 0x3630
+#define mmSDMA1_ATCL1_INV2 0x3631
+#define mmSDMA1_ATCL1_RD_XNACK0 0x3632
+#define mmSDMA1_ATCL1_RD_XNACK1 0x3633
+#define mmSDMA1_ATCL1_WR_XNACK0 0x3634
+#define mmSDMA1_ATCL1_WR_XNACK1 0x3635
+#define mmSDMA1_ATCL1_TIMEOUT 0x3636
+#define mmSDMA1_POWER_CNTL_IDLE 0x3638
+#define mmSDMA1_PERF_REG_TYPE0 0x3677
+#define mmSDMA1_CONTEXT_REG_TYPE0 0x3678
+#define mmSDMA1_CONTEXT_REG_TYPE1 0x3679
+#define mmSDMA1_CONTEXT_REG_TYPE2 0x367a
+#define mmSDMA1_PUB_REG_TYPE0 0x367c
+#define mmSDMA1_PUB_REG_TYPE1 0x367d
+#define mmSDMA1_GFX_RB_CNTL 0x3680
+#define mmSDMA1_GFX_RB_BASE 0x3681
+#define mmSDMA1_GFX_RB_BASE_HI 0x3682
+#define mmSDMA1_GFX_RB_RPTR 0x3683
+#define mmSDMA1_GFX_RB_WPTR 0x3684
+#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x3686
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x3687
+#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x3688
+#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x3689
+#define mmSDMA1_GFX_IB_CNTL 0x368a
+#define mmSDMA1_GFX_IB_RPTR 0x368b
+#define mmSDMA1_GFX_IB_OFFSET 0x368c
+#define mmSDMA1_GFX_IB_BASE_LO 0x368d
+#define mmSDMA1_GFX_IB_BASE_HI 0x368e
+#define mmSDMA1_GFX_IB_SIZE 0x368f
+#define mmSDMA1_GFX_SKIP_CNTL 0x3690
+#define mmSDMA1_GFX_CONTEXT_STATUS 0x3691
+#define mmSDMA1_GFX_DOORBELL 0x3692
+#define mmSDMA1_GFX_CONTEXT_CNTL 0x3693
+#define mmSDMA1_GFX_VIRTUAL_ADDR 0x36a7
+#define mmSDMA1_GFX_APE1_CNTL 0x36a8
+#define mmSDMA1_GFX_DOORBELL_LOG 0x36a9
+#define mmSDMA1_GFX_WATERMARK 0x36aa
+#define mmSDMA1_GFX_CSA_ADDR_LO 0x36ac
+#define mmSDMA1_GFX_CSA_ADDR_HI 0x36ad
+#define mmSDMA1_GFX_IB_SUB_REMAIN 0x36af
+#define mmSDMA1_GFX_PREEMPT 0x36b0
+#define mmSDMA1_GFX_DUMMY_REG 0x36b1
+#define mmSDMA1_GFX_MIDCMD_DATA0 0x36c1
+#define mmSDMA1_GFX_MIDCMD_DATA1 0x36c2
+#define mmSDMA1_GFX_MIDCMD_DATA2 0x36c3
+#define mmSDMA1_GFX_MIDCMD_DATA3 0x36c4
+#define mmSDMA1_GFX_MIDCMD_DATA4 0x36c5
+#define mmSDMA1_GFX_MIDCMD_DATA5 0x36c6
+#define mmSDMA1_GFX_MIDCMD_DATA6 0x36c7
+#define mmSDMA1_GFX_MIDCMD_DATA7 0x36c8
+#define mmSDMA1_GFX_MIDCMD_DATA8 0x36c9
+#define mmSDMA1_GFX_MIDCMD_CNTL 0x36ca
+#define mmSDMA1_RLC0_RB_CNTL 0x3700
+#define mmSDMA1_RLC0_RB_BASE 0x3701
+#define mmSDMA1_RLC0_RB_BASE_HI 0x3702
+#define mmSDMA1_RLC0_RB_RPTR 0x3703
+#define mmSDMA1_RLC0_RB_WPTR 0x3704
+#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x3706
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x3707
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x3708
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x3709
+#define mmSDMA1_RLC0_IB_CNTL 0x370a
+#define mmSDMA1_RLC0_IB_RPTR 0x370b
+#define mmSDMA1_RLC0_IB_OFFSET 0x370c
+#define mmSDMA1_RLC0_IB_BASE_LO 0x370d
+#define mmSDMA1_RLC0_IB_BASE_HI 0x370e
+#define mmSDMA1_RLC0_IB_SIZE 0x370f
+#define mmSDMA1_RLC0_SKIP_CNTL 0x3710
+#define mmSDMA1_RLC0_CONTEXT_STATUS 0x3711
+#define mmSDMA1_RLC0_DOORBELL 0x3712
+#define mmSDMA1_RLC0_VIRTUAL_ADDR 0x3727
+#define mmSDMA1_RLC0_APE1_CNTL 0x3728
+#define mmSDMA1_RLC0_DOORBELL_LOG 0x3729
+#define mmSDMA1_RLC0_WATERMARK 0x372a
+#define mmSDMA1_RLC0_CSA_ADDR_LO 0x372c
+#define mmSDMA1_RLC0_CSA_ADDR_HI 0x372d
+#define mmSDMA1_RLC0_IB_SUB_REMAIN 0x372f
+#define mmSDMA1_RLC0_PREEMPT 0x3730
+#define mmSDMA1_RLC0_DUMMY_REG 0x3731
+#define mmSDMA1_RLC0_MIDCMD_DATA0 0x3741
+#define mmSDMA1_RLC0_MIDCMD_DATA1 0x3742
+#define mmSDMA1_RLC0_MIDCMD_DATA2 0x3743
+#define mmSDMA1_RLC0_MIDCMD_DATA3 0x3744
+#define mmSDMA1_RLC0_MIDCMD_DATA4 0x3745
+#define mmSDMA1_RLC0_MIDCMD_DATA5 0x3746
+#define mmSDMA1_RLC0_MIDCMD_DATA6 0x3747
+#define mmSDMA1_RLC0_MIDCMD_DATA7 0x3748
+#define mmSDMA1_RLC0_MIDCMD_DATA8 0x3749
+#define mmSDMA1_RLC0_MIDCMD_CNTL 0x374a
+#define mmSDMA1_RLC1_RB_CNTL 0x3780
+#define mmSDMA1_RLC1_RB_BASE 0x3781
+#define mmSDMA1_RLC1_RB_BASE_HI 0x3782
+#define mmSDMA1_RLC1_RB_RPTR 0x3783
+#define mmSDMA1_RLC1_RB_WPTR 0x3784
+#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x3785
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x3786
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x3787
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x3788
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x3789
+#define mmSDMA1_RLC1_IB_CNTL 0x378a
+#define mmSDMA1_RLC1_IB_RPTR 0x378b
+#define mmSDMA1_RLC1_IB_OFFSET 0x378c
+#define mmSDMA1_RLC1_IB_BASE_LO 0x378d
+#define mmSDMA1_RLC1_IB_BASE_HI 0x378e
+#define mmSDMA1_RLC1_IB_SIZE 0x378f
+#define mmSDMA1_RLC1_SKIP_CNTL 0x3790
+#define mmSDMA1_RLC1_CONTEXT_STATUS 0x3791
+#define mmSDMA1_RLC1_DOORBELL 0x3792
+#define mmSDMA1_RLC1_VIRTUAL_ADDR 0x37a7
+#define mmSDMA1_RLC1_APE1_CNTL 0x37a8
+#define mmSDMA1_RLC1_DOORBELL_LOG 0x37a9
+#define mmSDMA1_RLC1_WATERMARK 0x37aa
+#define mmSDMA1_RLC1_CSA_ADDR_LO 0x37ac
+#define mmSDMA1_RLC1_CSA_ADDR_HI 0x37ad
+#define mmSDMA1_RLC1_IB_SUB_REMAIN 0x37af
+#define mmSDMA1_RLC1_PREEMPT 0x37b0
+#define mmSDMA1_RLC1_DUMMY_REG 0x37b1
+#define mmSDMA1_RLC1_MIDCMD_DATA0 0x37c1
+#define mmSDMA1_RLC1_MIDCMD_DATA1 0x37c2
+#define mmSDMA1_RLC1_MIDCMD_DATA2 0x37c3
+#define mmSDMA1_RLC1_MIDCMD_DATA3 0x37c4
+#define mmSDMA1_RLC1_MIDCMD_DATA4 0x37c5
+#define mmSDMA1_RLC1_MIDCMD_DATA5 0x37c6
+#define mmSDMA1_RLC1_MIDCMD_DATA6 0x37c7
+#define mmSDMA1_RLC1_MIDCMD_DATA7 0x37c8
+#define mmSDMA1_RLC1_MIDCMD_DATA8 0x37c9
+#define mmSDMA1_RLC1_MIDCMD_CNTL 0x37ca
+#define mmHDP_HOST_PATH_CNTL 0xb00
+#define mmHDP_NONSURFACE_BASE 0xb01
+#define mmHDP_NONSURFACE_INFO 0xb02
+#define mmHDP_NONSURFACE_SIZE 0xb03
+#define mmHDP_NONSURF_FLAGS 0xbc9
+#define mmHDP_NONSURF_FLAGS_CLR 0xbca
+#define mmHDP_SW_SEMAPHORE 0xbcb
+#define mmHDP_DEBUG0 0xbcc
+#define mmHDP_DEBUG1 0xbcd
+#define mmHDP_LAST_SURFACE_HIT 0xbce
+#define mmHDP_TILING_CONFIG 0xbcf
+#define mmHDP_SC_MULTI_CHIP_CNTL 0xbd0
+#define mmHDP_OUTSTANDING_REQ 0xbd1
+#define mmHDP_ADDR_CONFIG 0xbd2
+#define mmHDP_MISC_CNTL 0xbd3
+#define mmHDP_MEM_POWER_LS 0xbd4
+#define mmHDP_NONSURFACE_PREFETCH 0xbd5
+#define mmHDP_MEMIO_CNTL 0xbf6
+#define mmHDP_MEMIO_ADDR 0xbf7
+#define mmHDP_MEMIO_STATUS 0xbf8
+#define mmHDP_MEMIO_WR_DATA 0xbf9
+#define mmHDP_MEMIO_RD_DATA 0xbfa
+#define mmHDP_VF_ENABLE 0xbfb
+#define mmHDP_XDP_DIRECT2HDP_FIRST 0xc00
+#define mmHDP_XDP_D2H_FLUSH 0xc01
+#define mmHDP_XDP_D2H_BAR_UPDATE 0xc02
+#define mmHDP_XDP_D2H_RSVD_3 0xc03
+#define mmHDP_XDP_D2H_RSVD_4 0xc04
+#define mmHDP_XDP_D2H_RSVD_5 0xc05
+#define mmHDP_XDP_D2H_RSVD_6 0xc06
+#define mmHDP_XDP_D2H_RSVD_7 0xc07
+#define mmHDP_XDP_D2H_RSVD_8 0xc08
+#define mmHDP_XDP_D2H_RSVD_9 0xc09
+#define mmHDP_XDP_D2H_RSVD_10 0xc0a
+#define mmHDP_XDP_D2H_RSVD_11 0xc0b
+#define mmHDP_XDP_D2H_RSVD_12 0xc0c
+#define mmHDP_XDP_D2H_RSVD_13 0xc0d
+#define mmHDP_XDP_D2H_RSVD_14 0xc0e
+#define mmHDP_XDP_D2H_RSVD_15 0xc0f
+#define mmHDP_XDP_D2H_RSVD_16 0xc10
+#define mmHDP_XDP_D2H_RSVD_17 0xc11
+#define mmHDP_XDP_D2H_RSVD_18 0xc12
+#define mmHDP_XDP_D2H_RSVD_19 0xc13
+#define mmHDP_XDP_D2H_RSVD_20 0xc14
+#define mmHDP_XDP_D2H_RSVD_21 0xc15
+#define mmHDP_XDP_D2H_RSVD_22 0xc16
+#define mmHDP_XDP_D2H_RSVD_23 0xc17
+#define mmHDP_XDP_D2H_RSVD_24 0xc18
+#define mmHDP_XDP_D2H_RSVD_25 0xc19
+#define mmHDP_XDP_D2H_RSVD_26 0xc1a
+#define mmHDP_XDP_D2H_RSVD_27 0xc1b
+#define mmHDP_XDP_D2H_RSVD_28 0xc1c
+#define mmHDP_XDP_D2H_RSVD_29 0xc1d
+#define mmHDP_XDP_D2H_RSVD_30 0xc1e
+#define mmHDP_XDP_D2H_RSVD_31 0xc1f
+#define mmHDP_XDP_D2H_RSVD_32 0xc20
+#define mmHDP_XDP_D2H_RSVD_33 0xc21
+#define mmHDP_XDP_D2H_RSVD_34 0xc22
+#define mmHDP_XDP_DIRECT2HDP_LAST 0xc23
+#define mmHDP_XDP_P2P_BAR_CFG 0xc24
+#define mmHDP_XDP_P2P_MBX_OFFSET 0xc25
+#define mmHDP_XDP_P2P_MBX_ADDR0 0xc26
+#define mmHDP_XDP_P2P_MBX_ADDR1 0xc27
+#define mmHDP_XDP_P2P_MBX_ADDR2 0xc28
+#define mmHDP_XDP_P2P_MBX_ADDR3 0xc29
+#define mmHDP_XDP_P2P_MBX_ADDR4 0xc2a
+#define mmHDP_XDP_P2P_MBX_ADDR5 0xc2b
+#define mmHDP_XDP_P2P_MBX_ADDR6 0xc2c
+#define mmHDP_XDP_HDP_MBX_MC_CFG 0xc2d
+#define mmHDP_XDP_HDP_MC_CFG 0xc2e
+#define mmHDP_XDP_HST_CFG 0xc2f
+#define mmHDP_XDP_SID_CFG 0xc30
+#define mmHDP_XDP_HDP_IPH_CFG 0xc31
+#define mmHDP_XDP_SRBM_CFG 0xc32
+#define mmHDP_XDP_CGTT_BLK_CTRL 0xc33
+#define mmHDP_XDP_P2P_BAR0 0xc34
+#define mmHDP_XDP_P2P_BAR1 0xc35
+#define mmHDP_XDP_P2P_BAR2 0xc36
+#define mmHDP_XDP_P2P_BAR3 0xc37
+#define mmHDP_XDP_P2P_BAR4 0xc38
+#define mmHDP_XDP_P2P_BAR5 0xc39
+#define mmHDP_XDP_P2P_BAR6 0xc3a
+#define mmHDP_XDP_P2P_BAR7 0xc3b
+#define mmHDP_XDP_FLUSH_ARMED_STS 0xc3c
+#define mmHDP_XDP_FLUSH_CNTR0_STS 0xc3d
+#define mmHDP_XDP_BUSY_STS 0xc3e
+#define mmHDP_XDP_STICKY 0xc3f
+#define mmHDP_XDP_CHKN 0xc40
+#define mmHDP_XDP_DBG_ADDR 0xc41
+#define mmHDP_XDP_DBG_DATA 0xc42
+#define mmHDP_XDP_DBG_MASK 0xc43
+#define mmHDP_XDP_BARS_ADDR_39_36 0xc44
+
+#endif /* OSS_3_0_1_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_enum.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_enum.h
new file mode 100644
index 000000000000..627cff10fcce
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_enum.h
@@ -0,0 +1,1464 @@
+/*
+ * OSS_3_0_1 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef OSS_3_0_1_ENUM_H
+#define OSS_3_0_1_ENUM_H
+
+typedef enum IH_CLIENT_ID {
+ DC_IH_SRC_ID_START = 0x1,
+ DC_IH_SRC_ID_END = 0x1f,
+ VGA_IH_SRC_ID_START = 0x20,
+ VGA_IH_SRC_ID_END = 0x27,
+ CAP_IH_SRC_ID_START = 0x28,
+ CAP_IH_SRC_ID_END = 0x2f,
+ VIP_IH_SRC_ID_START = 0x30,
+ VIP_IH_SRC_ID_END = 0x3f,
+ ROM_IH_SRC_ID_START = 0x40,
+ ROM_IH_SRC_ID_END = 0x5d,
+ BIF_IH_SRC_ID_START = 0x5e,
+ SAM_IH_SRC_ID_START = 0x5f,
+ SRBM_IH_SRC_ID_START = 0x60,
+ SRBM_IH_SRC_ID_END = 0x67,
+ UVD_IH_SRC_ID_START = 0x72,
+ UVD_IH_SRC_ID_END = 0x85,
+ VMC_IH_SRC_ID_START = 0x86,
+ VMC_IH_SRC_ID_END = 0x8f,
+ RLC_IH_SRC_ID_START = 0x90,
+ RLC_IH_SRC_ID_END = 0xf3,
+ PDMA_IH_SRC_ID_START = 0xf4,
+ PDMA_IH_SRC_ID_END = 0xf7,
+ CG_IH_SRC_ID_START = 0xf8,
+ CG_IH_SRC_ID_END = 0xff,
+} IH_CLIENT_ID;
+typedef enum IH_PERF_SEL {
+ IH_PERF_SEL_CYCLE = 0x0,
+ IH_PERF_SEL_IDLE = 0x1,
+ IH_PERF_SEL_INPUT_IDLE = 0x2,
+ IH_PERF_SEL_CLIENT0_IH_STALL = 0x3,
+ IH_PERF_SEL_CLIENT1_IH_STALL = 0x4,
+ IH_PERF_SEL_CLIENT2_IH_STALL = 0x5,
+ IH_PERF_SEL_CLIENT3_IH_STALL = 0x6,
+ IH_PERF_SEL_CLIENT4_IH_STALL = 0x7,
+ IH_PERF_SEL_CLIENT5_IH_STALL = 0x8,
+ IH_PERF_SEL_CLIENT6_IH_STALL = 0x9,
+ IH_PERF_SEL_CLIENT7_IH_STALL = 0xa,
+ IH_PERF_SEL_RB_IDLE = 0xb,
+ IH_PERF_SEL_RB_FULL = 0xc,
+ IH_PERF_SEL_RB_OVERFLOW = 0xd,
+ IH_PERF_SEL_RB_WPTR_WRITEBACK = 0xe,
+ IH_PERF_SEL_RB_WPTR_WRAP = 0xf,
+ IH_PERF_SEL_RB_RPTR_WRAP = 0x10,
+ IH_PERF_SEL_MC_WR_IDLE = 0x11,
+ IH_PERF_SEL_MC_WR_COUNT = 0x12,
+ IH_PERF_SEL_MC_WR_STALL = 0x13,
+ IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x14,
+ IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x15,
+ IH_PERF_SEL_BIF_RISING = 0x16,
+ IH_PERF_SEL_BIF_FALLING = 0x17,
+ IH_PERF_SEL_CLIENT8_IH_STALL = 0x18,
+ IH_PERF_SEL_CLIENT9_IH_STALL = 0x19,
+ IH_PERF_SEL_CLIENT10_IH_STALL = 0x1a,
+ IH_PERF_SEL_CLIENT11_IH_STALL = 0x1b,
+ IH_PERF_SEL_CLIENT12_IH_STALL = 0x1c,
+ IH_PERF_SEL_CLIENT13_IH_STALL = 0x1d,
+ IH_PERF_SEL_CLIENT14_IH_STALL = 0x1e,
+ IH_PERF_SEL_CLIENT15_IH_STALL = 0x1f,
+ IH_PERF_SEL_CLIENT16_IH_STALL = 0x20,
+ IH_PERF_SEL_CLIENT17_IH_STALL = 0x21,
+ IH_PERF_SEL_CLIENT18_IH_STALL = 0x22,
+ IH_PERF_SEL_CLIENT19_IH_STALL = 0x23,
+ IH_PERF_SEL_CLIENT20_IH_STALL = 0x24,
+ IH_PERF_SEL_CLIENT21_IH_STALL = 0x25,
+ IH_PERF_SEL_CLIENT22_IH_STALL = 0x26,
+ IH_PERF_SEL_CLIENT23_IH_STALL = 0x27,
+} IH_PERF_SEL;
+typedef enum SEM_PERF_SEL {
+ SEM_PERF_SEL_CYCLE = 0x0,
+ SEM_PERF_SEL_IDLE = 0x1,
+ SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 0x2,
+ SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 0x3,
+ SEM_PERF_SEL_UVD_REQ_SIGNAL = 0x4,
+ SEM_PERF_SEL_VCE0_REQ_SIGNAL = 0x5,
+ SEM_PERF_SEL_ACP_REQ_SIGNAL = 0x6,
+ SEM_PERF_SEL_ISP_REQ_SIGNAL = 0x7,
+ SEM_PERF_SEL_VCE1_REQ_SIGNAL = 0x8,
+ SEM_PERF_SEL_VP8_REQ_SIGNAL = 0x9,
+ SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 0xa,
+ SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 0xb,
+ SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 0xc,
+ SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 0xd,
+ SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 0xe,
+ SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 0xf,
+ SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 0x10,
+ SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 0x11,
+ SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 0x12,
+ SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 0x13,
+ SEM_PERF_SEL_SDMA0_REQ_WAIT = 0x14,
+ SEM_PERF_SEL_SDMA1_REQ_WAIT = 0x15,
+ SEM_PERF_SEL_UVD_REQ_WAIT = 0x16,
+ SEM_PERF_SEL_VCE0_REQ_WAIT = 0x17,
+ SEM_PERF_SEL_ACP_REQ_WAIT = 0x18,
+ SEM_PERF_SEL_ISP_REQ_WAIT = 0x19,
+ SEM_PERF_SEL_VCE1_REQ_WAIT = 0x1a,
+ SEM_PERF_SEL_VP8_REQ_WAIT = 0x1b,
+ SEM_PERF_SEL_CPG_E0_REQ_WAIT = 0x1c,
+ SEM_PERF_SEL_CPG_E1_REQ_WAIT = 0x1d,
+ SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 0x1e,
+ SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 0x1f,
+ SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 0x20,
+ SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 0x21,
+ SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 0x22,
+ SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 0x23,
+ SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 0x24,
+ SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 0x25,
+ SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 0x26,
+ SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 0x27,
+ SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 0x28,
+ SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 0x29,
+ SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 0x2a,
+ SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 0x2b,
+ SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 0x2c,
+ SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 0x2d,
+ SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 0x2e,
+ SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 0x2f,
+ SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 0x30,
+ SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 0x31,
+ SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 0x32,
+ SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 0x33,
+ SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 0x34,
+ SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 0x35,
+ SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 0x36,
+ SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 0x37,
+ SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 0x38,
+ SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 0x39,
+ SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 0x3a,
+ SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 0x3b,
+ SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 0x3c,
+ SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 0x3d,
+ SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 0x3e,
+ SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 0x3f,
+ SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 0x40,
+ SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 0x41,
+ SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 0x42,
+ SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 0x43,
+ SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 0x44,
+ SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 0x45,
+ SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 0x46,
+ SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 0x47,
+ SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 0x48,
+ SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 0x49,
+ SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 0x4a,
+ SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 0x4b,
+ SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 0x4c,
+ SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 0x4d,
+ SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 0x4e,
+ SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 0x4f,
+ SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 0x50,
+ SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 0x51,
+ SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 0x52,
+ SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 0x53,
+ SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 0x54,
+ SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 0x55,
+ SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 0x56,
+ SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 0x57,
+ SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 0x58,
+ SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 0x59,
+ SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 0x5a,
+ SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 0x5b,
+ SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 0x5c,
+ SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 0x5d,
+ SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 0x5e,
+ SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 0x5f,
+ SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 0x60,
+ SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 0x61,
+ SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 0x62,
+ SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 0x63,
+ SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 0x64,
+ SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 0x65,
+ SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 0x66,
+ SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 0x67,
+ SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 0x68,
+ SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 0x69,
+ SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 0x6a,
+ SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 0x6b,
+ SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 0x6c,
+ SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 0x6d,
+ SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 0x6e,
+ SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 0x6f,
+ SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 0x70,
+ SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 0x71,
+ SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 0x72,
+ SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 0x73,
+ SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 0x74,
+ SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 0x75,
+ SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 0x76,
+ SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 0x77,
+ SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 0x78,
+ SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 0x79,
+ SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 0x7a,
+ SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 0x7b,
+ SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 0x7c,
+ SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 0x7d,
+ SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 0x7e,
+ SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 0x7f,
+ SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 0x80,
+ SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 0x81,
+ SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 0x82,
+ SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 0x83,
+ SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 0x84,
+ SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 0x85,
+ SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 0x86,
+ SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 0x87,
+ SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 0x88,
+ SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 0x89,
+ SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 0x8a,
+ SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 0x8b,
+ SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 0x8c,
+ SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 0x8d,
+ SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 0x8e,
+ SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 0x8f,
+ SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 0x90,
+ SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 0x91,
+ SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 0x92,
+ SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 0x93,
+ SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 0x94,
+ SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 0x95,
+ SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 0x96,
+ SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 0x97,
+ SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 0x98,
+ SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 0x99,
+ SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 0x9a,
+ SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 0x9b,
+ SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 0x9c,
+ SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 0x9d,
+ SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 0x9e,
+ SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 0x9f,
+ SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 0xa0,
+ SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 0xa1,
+ SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 0xa2,
+ SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 0xa3,
+ SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 0xa4,
+ SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 0xa5,
+ SEM_PERF_SEL_MC_RD_REQ = 0xa6,
+ SEM_PERF_SEL_MC_RD_RET = 0xa7,
+ SEM_PERF_SEL_MC_WR_REQ = 0xa8,
+ SEM_PERF_SEL_MC_WR_RET = 0xa9,
+ SEM_PERF_SEL_ATC_REQ = 0xaa,
+ SEM_PERF_SEL_ATC_RET = 0xab,
+ SEM_PERF_SEL_ATC_XNACK = 0xac,
+ SEM_PERF_SEL_ATC_INVALIDATION = 0xad,
+} SEM_PERF_SEL;
+typedef enum SRBM_PERFCOUNT1_SEL {
+ SRBM_PERF_SEL_COUNT = 0x0,
+ SRBM_PERF_SEL_BIF_BUSY = 0x1,
+ SRBM_PERF_SEL_SDMA0_BUSY = 0x3,
+ SRBM_PERF_SEL_IH_BUSY = 0x4,
+ SRBM_PERF_SEL_MCB_BUSY = 0x5,
+ SRBM_PERF_SEL_MCB_NON_DISPLAY_BUSY = 0x6,
+ SRBM_PERF_SEL_MCC_BUSY = 0x7,
+ SRBM_PERF_SEL_MCD_BUSY = 0x8,
+ SRBM_PERF_SEL_CHUB_BUSY = 0x9,
+ SRBM_PERF_SEL_SEM_BUSY = 0xa,
+ SRBM_PERF_SEL_UVD_BUSY = 0xb,
+ SRBM_PERF_SEL_VMC_BUSY = 0xc,
+ SRBM_PERF_SEL_ODE_BUSY = 0xd,
+ SRBM_PERF_SEL_SDMA1_BUSY = 0xe,
+ SRBM_PERF_SEL_SAMMSP_BUSY = 0xf,
+ SRBM_PERF_SEL_VCE0_BUSY = 0x10,
+ SRBM_PERF_SEL_XDMA_BUSY = 0x11,
+ SRBM_PERF_SEL_ACP_BUSY = 0x12,
+ SRBM_PERF_SEL_SDMA2_BUSY = 0x13,
+ SRBM_PERF_SEL_SDMA3_BUSY = 0x14,
+ RESERVED0 = 0x15,
+ SRBM_PERF_SEL_VMC1_BUSY = 0x16,
+ SRBM_PERF_SEL_ISP_BUSY = 0x17,
+ SRBM_PERF_SEL_VCE1_BUSY = 0x18,
+ SRBM_PERF_SEL_GCATCL2_BUSY = 0x19,
+ SRBM_PERF_SEL_OSATCL2_BUSY = 0x1a,
+ SRBM_PERF_SEL_VP8_BUSY = 0x1b,
+} SRBM_PERFCOUNT1_SEL;
+typedef enum SYS_GRBM_GFX_INDEX_SEL {
+ GRBM_GFX_INDEX_BIF = 0x0,
+ GRBM_GFX_INDEX_SDMA0 = 0x1,
+ GRBM_GFX_INDEX_SDMA1 = 0x2,
+ RESEVERED0 = 0x3,
+ GRBM_GFX_INDEX_UVD = 0x4,
+ GRBM_GFX_INDEX_VCE0 = 0x5,
+ GRBM_GFX_INDEX_VCE1 = 0x6,
+ GRBM_GFX_INDEX_ACP = 0x7,
+ GRBM_GFX_INDEX_SMU = 0x8,
+ GRBM_GFX_INDEX_SAMMSP = 0x9,
+ GRBM_GFX_INDEX_VP8 = 0xa,
+ GRBM_GFX_INDEX_ISP = 0xb,
+ GRBM_GFX_INDEX_TST = 0xc,
+ GRBM_GFX_INDEX_SDMA2 = 0xd,
+ GRBM_GFX_INDEX_SDMA3 = 0xe,
+} SYS_GRBM_GFX_INDEX_SEL;
+typedef enum SRBM_GFX_CNTL_SEL {
+ SRBM_GFX_CNTL_BIF = 0x0,
+ SRBM_GFX_CNTL_SDMA0 = 0x1,
+ SRBM_GFX_CNTL_SDMA1 = 0x2,
+ SRBM_GFX_CNTL_GRBM = 0x3,
+ SRBM_GFX_CNTL_UVD = 0x4,
+ SRBM_GFX_CNTL_VCE0 = 0x5,
+ SRBM_GFX_CNTL_VCE1 = 0x6,
+ SRBM_GFX_CNTL_ACP = 0x7,
+ SRBM_GFX_CNTL_SMU = 0x8,
+ SRBM_GFX_CNTL_SAMMSP = 0x9,
+ SRBM_GFX_CNTL_VP8 = 0xa,
+ SRBM_GFX_CNTL_ISP = 0xb,
+ SRBM_GFX_CNTL_TST = 0xc,
+ SRBM_GFX_CNTL_SDMA2 = 0xd,
+ SRBM_GFX_CNTL_SDMA3 = 0xe,
+} SRBM_GFX_CNTL_SEL;
+typedef enum SDMA_PERF_SEL {
+ SDMA_PERF_SEL_CYCLE = 0x0,
+ SDMA_PERF_SEL_IDLE = 0x1,
+ SDMA_PERF_SEL_REG_IDLE = 0x2,
+ SDMA_PERF_SEL_RB_EMPTY = 0x3,
+ SDMA_PERF_SEL_RB_FULL = 0x4,
+ SDMA_PERF_SEL_RB_WPTR_WRAP = 0x5,
+ SDMA_PERF_SEL_RB_RPTR_WRAP = 0x6,
+ SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x7,
+ SDMA_PERF_SEL_RB_RPTR_WB = 0x8,
+ SDMA_PERF_SEL_RB_CMD_IDLE = 0x9,
+ SDMA_PERF_SEL_RB_CMD_FULL = 0xa,
+ SDMA_PERF_SEL_IB_CMD_IDLE = 0xb,
+ SDMA_PERF_SEL_IB_CMD_FULL = 0xc,
+ SDMA_PERF_SEL_EX_IDLE = 0xd,
+ SDMA_PERF_SEL_SRBM_REG_SEND = 0xe,
+ SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0xf,
+ SDMA_PERF_SEL_MC_WR_IDLE = 0x10,
+ SDMA_PERF_SEL_MC_WR_COUNT = 0x11,
+ SDMA_PERF_SEL_MC_RD_IDLE = 0x12,
+ SDMA_PERF_SEL_MC_RD_COUNT = 0x13,
+ SDMA_PERF_SEL_MC_RD_RET_STALL = 0x14,
+ SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x15,
+ SDMA_PERF_SEL_SEM_IDLE = 0x18,
+ SDMA_PERF_SEL_SEM_REQ_STALL = 0x19,
+ SDMA_PERF_SEL_SEM_REQ_COUNT = 0x1a,
+ SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x1b,
+ SDMA_PERF_SEL_SEM_RESP_FAIL = 0x1c,
+ SDMA_PERF_SEL_SEM_RESP_PASS = 0x1d,
+ SDMA_PERF_SEL_INT_IDLE = 0x1e,
+ SDMA_PERF_SEL_INT_REQ_STALL = 0x1f,
+ SDMA_PERF_SEL_INT_REQ_COUNT = 0x20,
+ SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x21,
+ SDMA_PERF_SEL_INT_RESP_RETRY = 0x22,
+ SDMA_PERF_SEL_NUM_PACKET = 0x23,
+ SDMA_PERF_SEL_CE_WREQ_IDLE = 0x25,
+ SDMA_PERF_SEL_CE_WR_IDLE = 0x26,
+ SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x27,
+ SDMA_PERF_SEL_CE_RREQ_IDLE = 0x28,
+ SDMA_PERF_SEL_CE_OUT_IDLE = 0x29,
+ SDMA_PERF_SEL_CE_IN_IDLE = 0x2a,
+ SDMA_PERF_SEL_CE_DST_IDLE = 0x2b,
+ SDMA_PERF_SEL_CE_AFIFO_FULL = 0x2e,
+ SDMA_PERF_SEL_CE_INFO_FULL = 0x31,
+ SDMA_PERF_SEL_CE_INFO1_FULL = 0x32,
+ SDMA_PERF_SEL_CE_RD_STALL = 0x33,
+ SDMA_PERF_SEL_CE_WR_STALL = 0x34,
+ SDMA_PERF_SEL_GFX_SELECT = 0x35,
+ SDMA_PERF_SEL_RLC0_SELECT = 0x36,
+ SDMA_PERF_SEL_RLC1_SELECT = 0x37,
+ SDMA_PERF_SEL_CTX_CHANGE = 0x38,
+ SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x39,
+ SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x3a,
+ SDMA_PERF_SEL_DOORBELL = 0x3b,
+ SDMA_PERF_SEL_RD_BA_RTR = 0x3c,
+ SDMA_PERF_SEL_WR_BA_RTR = 0x3d,
+ SDMA_PERF_SEL_F32_L1_WR_VLD = 0x3e,
+ SDMA_PERF_SEL_CE_L1_WR_VLD = 0x3f,
+ SDMA_PERF_SEL_CE_L1_STALL = 0x40,
+ SDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 0x41,
+ SDMA_PERF_SEL_SDMA_INVACK_FLUSH = 0x42,
+ SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 0x43,
+ SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 0x44,
+ SDMA_PERF_SEL_ATCL2_RET_XNACK = 0x45,
+ SDMA_PERF_SEL_ATCL2_RET_ACK = 0x46,
+ SDMA_PERF_SEL_ATCL2_FREE = 0x47,
+ SDMA_PERF_SEL_SDMA_ATCL2_SEND = 0x48,
+ SDMA_PERF_SEL_DMA_L1_WR_SEND = 0x49,
+ SDMA_PERF_SEL_DMA_L1_RD_SEND = 0x4a,
+ SDMA_PERF_SEL_DMA_MC_WR_SEND = 0x4b,
+ SDMA_PERF_SEL_DMA_MC_RD_SEND = 0x4c,
+ SDMA_PERF_SEL_L1_WR_FIFO_IDLE = 0x4d,
+ SDMA_PERF_SEL_L1_RD_FIFO_IDLE = 0x4e,
+ SDMA_PERF_SEL_L1_WRL2_IDLE = 0x4f,
+ SDMA_PERF_SEL_L1_RDL2_IDLE = 0x50,
+ SDMA_PERF_SEL_L1_WRMC_IDLE = 0x51,
+ SDMA_PERF_SEL_L1_RDMC_IDLE = 0x52,
+ SDMA_PERF_SEL_L1_WR_INV_IDLE = 0x53,
+ SDMA_PERF_SEL_L1_RD_INV_IDLE = 0x54,
+ SDMA_PERF_SEL_L1_WR_INV_EN = 0x55,
+ SDMA_PERF_SEL_L1_RD_INV_EN = 0x56,
+ SDMA_PERF_SEL_L1_WR_WAIT_INVADR = 0x57,
+ SDMA_PERF_SEL_L1_RD_WAIT_INVADR = 0x58,
+ SDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 0x59,
+ SDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 0x5a,
+ SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 0x5b,
+ SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 0x5c,
+ SDMA_PERF_SEL_L1_INV_MIDDLE = 0x5d,
+} SDMA_PERF_SEL;
+typedef enum DebugBlockId {
+ DBG_BLOCK_ID_RESERVED = 0x0,
+ DBG_BLOCK_ID_DBG = 0x1,
+ DBG_BLOCK_ID_VMC = 0x2,
+ DBG_BLOCK_ID_PDMA = 0x3,
+ DBG_BLOCK_ID_CG = 0x4,
+ DBG_BLOCK_ID_SRBM = 0x5,
+ DBG_BLOCK_ID_GRBM = 0x6,
+ DBG_BLOCK_ID_RLC = 0x7,
+ DBG_BLOCK_ID_CSC = 0x8,
+ DBG_BLOCK_ID_SEM = 0x9,
+ DBG_BLOCK_ID_IH = 0xa,
+ DBG_BLOCK_ID_SC = 0xb,
+ DBG_BLOCK_ID_SQ = 0xc,
+ DBG_BLOCK_ID_UVDU = 0xd,
+ DBG_BLOCK_ID_SQA = 0xe,
+ DBG_BLOCK_ID_SDMA0 = 0xf,
+ DBG_BLOCK_ID_SDMA1 = 0x10,
+ DBG_BLOCK_ID_SPIM = 0x11,
+ DBG_BLOCK_ID_GDS = 0x12,
+ DBG_BLOCK_ID_VC0 = 0x13,
+ DBG_BLOCK_ID_VC1 = 0x14,
+ DBG_BLOCK_ID_PA0 = 0x15,
+ DBG_BLOCK_ID_PA1 = 0x16,
+ DBG_BLOCK_ID_CP0 = 0x17,
+ DBG_BLOCK_ID_CP1 = 0x18,
+ DBG_BLOCK_ID_CP2 = 0x19,
+ DBG_BLOCK_ID_XBR = 0x1a,
+ DBG_BLOCK_ID_UVDM = 0x1b,
+ DBG_BLOCK_ID_VGT0 = 0x1c,
+ DBG_BLOCK_ID_VGT1 = 0x1d,
+ DBG_BLOCK_ID_IA = 0x1e,
+ DBG_BLOCK_ID_SXM0 = 0x1f,
+ DBG_BLOCK_ID_SXM1 = 0x20,
+ DBG_BLOCK_ID_SCT0 = 0x21,
+ DBG_BLOCK_ID_SCT1 = 0x22,
+ DBG_BLOCK_ID_SPM0 = 0x23,
+ DBG_BLOCK_ID_SPM1 = 0x24,
+ DBG_BLOCK_ID_UNUSED0 = 0x25,
+ DBG_BLOCK_ID_UNUSED1 = 0x26,
+ DBG_BLOCK_ID_TCAA = 0x27,
+ DBG_BLOCK_ID_TCAB = 0x28,
+ DBG_BLOCK_ID_TCCA = 0x29,
+ DBG_BLOCK_ID_TCCB = 0x2a,
+ DBG_BLOCK_ID_MCC0 = 0x2b,
+ DBG_BLOCK_ID_MCC1 = 0x2c,
+ DBG_BLOCK_ID_MCC2 = 0x2d,
+ DBG_BLOCK_ID_MCC3 = 0x2e,
+ DBG_BLOCK_ID_SXS0 = 0x2f,
+ DBG_BLOCK_ID_SXS1 = 0x30,
+ DBG_BLOCK_ID_SXS2 = 0x31,
+ DBG_BLOCK_ID_SXS3 = 0x32,
+ DBG_BLOCK_ID_SXS4 = 0x33,
+ DBG_BLOCK_ID_SXS5 = 0x34,
+ DBG_BLOCK_ID_SXS6 = 0x35,
+ DBG_BLOCK_ID_SXS7 = 0x36,
+ DBG_BLOCK_ID_SXS8 = 0x37,
+ DBG_BLOCK_ID_SXS9 = 0x38,
+ DBG_BLOCK_ID_BCI0 = 0x39,
+ DBG_BLOCK_ID_BCI1 = 0x3a,
+ DBG_BLOCK_ID_BCI2 = 0x3b,
+ DBG_BLOCK_ID_BCI3 = 0x3c,
+ DBG_BLOCK_ID_MCB = 0x3d,
+ DBG_BLOCK_ID_UNUSED6 = 0x3e,
+ DBG_BLOCK_ID_SQA00 = 0x3f,
+ DBG_BLOCK_ID_SQA01 = 0x40,
+ DBG_BLOCK_ID_SQA02 = 0x41,
+ DBG_BLOCK_ID_SQA10 = 0x42,
+ DBG_BLOCK_ID_SQA11 = 0x43,
+ DBG_BLOCK_ID_SQA12 = 0x44,
+ DBG_BLOCK_ID_UNUSED7 = 0x45,
+ DBG_BLOCK_ID_UNUSED8 = 0x46,
+ DBG_BLOCK_ID_SQB00 = 0x47,
+ DBG_BLOCK_ID_SQB01 = 0x48,
+ DBG_BLOCK_ID_SQB10 = 0x49,
+ DBG_BLOCK_ID_SQB11 = 0x4a,
+ DBG_BLOCK_ID_SQ00 = 0x4b,
+ DBG_BLOCK_ID_SQ01 = 0x4c,
+ DBG_BLOCK_ID_SQ10 = 0x4d,
+ DBG_BLOCK_ID_SQ11 = 0x4e,
+ DBG_BLOCK_ID_CB00 = 0x4f,
+ DBG_BLOCK_ID_CB01 = 0x50,
+ DBG_BLOCK_ID_CB02 = 0x51,
+ DBG_BLOCK_ID_CB03 = 0x52,
+ DBG_BLOCK_ID_CB04 = 0x53,
+ DBG_BLOCK_ID_UNUSED9 = 0x54,
+ DBG_BLOCK_ID_UNUSED10 = 0x55,
+ DBG_BLOCK_ID_UNUSED11 = 0x56,
+ DBG_BLOCK_ID_CB10 = 0x57,
+ DBG_BLOCK_ID_CB11 = 0x58,
+ DBG_BLOCK_ID_CB12 = 0x59,
+ DBG_BLOCK_ID_CB13 = 0x5a,
+ DBG_BLOCK_ID_CB14 = 0x5b,
+ DBG_BLOCK_ID_UNUSED12 = 0x5c,
+ DBG_BLOCK_ID_UNUSED13 = 0x5d,
+ DBG_BLOCK_ID_UNUSED14 = 0x5e,
+ DBG_BLOCK_ID_TCP0 = 0x5f,
+ DBG_BLOCK_ID_TCP1 = 0x60,
+ DBG_BLOCK_ID_TCP2 = 0x61,
+ DBG_BLOCK_ID_TCP3 = 0x62,
+ DBG_BLOCK_ID_TCP4 = 0x63,
+ DBG_BLOCK_ID_TCP5 = 0x64,
+ DBG_BLOCK_ID_TCP6 = 0x65,
+ DBG_BLOCK_ID_TCP7 = 0x66,
+ DBG_BLOCK_ID_TCP8 = 0x67,
+ DBG_BLOCK_ID_TCP9 = 0x68,
+ DBG_BLOCK_ID_TCP10 = 0x69,
+ DBG_BLOCK_ID_TCP11 = 0x6a,
+ DBG_BLOCK_ID_TCP12 = 0x6b,
+ DBG_BLOCK_ID_TCP13 = 0x6c,
+ DBG_BLOCK_ID_TCP14 = 0x6d,
+ DBG_BLOCK_ID_TCP15 = 0x6e,
+ DBG_BLOCK_ID_TCP16 = 0x6f,
+ DBG_BLOCK_ID_TCP17 = 0x70,
+ DBG_BLOCK_ID_TCP18 = 0x71,
+ DBG_BLOCK_ID_TCP19 = 0x72,
+ DBG_BLOCK_ID_TCP20 = 0x73,
+ DBG_BLOCK_ID_TCP21 = 0x74,
+ DBG_BLOCK_ID_TCP22 = 0x75,
+ DBG_BLOCK_ID_TCP23 = 0x76,
+ DBG_BLOCK_ID_TCP_RESERVED0 = 0x77,
+ DBG_BLOCK_ID_TCP_RESERVED1 = 0x78,
+ DBG_BLOCK_ID_TCP_RESERVED2 = 0x79,
+ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a,
+ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b,
+ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c,
+ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d,
+ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e,
+ DBG_BLOCK_ID_DB00 = 0x7f,
+ DBG_BLOCK_ID_DB01 = 0x80,
+ DBG_BLOCK_ID_DB02 = 0x81,
+ DBG_BLOCK_ID_DB03 = 0x82,
+ DBG_BLOCK_ID_DB04 = 0x83,
+ DBG_BLOCK_ID_UNUSED15 = 0x84,
+ DBG_BLOCK_ID_UNUSED16 = 0x85,
+ DBG_BLOCK_ID_UNUSED17 = 0x86,
+ DBG_BLOCK_ID_DB10 = 0x87,
+ DBG_BLOCK_ID_DB11 = 0x88,
+ DBG_BLOCK_ID_DB12 = 0x89,
+ DBG_BLOCK_ID_DB13 = 0x8a,
+ DBG_BLOCK_ID_DB14 = 0x8b,
+ DBG_BLOCK_ID_UNUSED18 = 0x8c,
+ DBG_BLOCK_ID_UNUSED19 = 0x8d,
+ DBG_BLOCK_ID_UNUSED20 = 0x8e,
+ DBG_BLOCK_ID_TCC0 = 0x8f,
+ DBG_BLOCK_ID_TCC1 = 0x90,
+ DBG_BLOCK_ID_TCC2 = 0x91,
+ DBG_BLOCK_ID_TCC3 = 0x92,
+ DBG_BLOCK_ID_TCC4 = 0x93,
+ DBG_BLOCK_ID_TCC5 = 0x94,
+ DBG_BLOCK_ID_TCC6 = 0x95,
+ DBG_BLOCK_ID_TCC7 = 0x96,
+ DBG_BLOCK_ID_SPS00 = 0x97,
+ DBG_BLOCK_ID_SPS01 = 0x98,
+ DBG_BLOCK_ID_SPS02 = 0x99,
+ DBG_BLOCK_ID_SPS10 = 0x9a,
+ DBG_BLOCK_ID_SPS11 = 0x9b,
+ DBG_BLOCK_ID_SPS12 = 0x9c,
+ DBG_BLOCK_ID_UNUSED21 = 0x9d,
+ DBG_BLOCK_ID_UNUSED22 = 0x9e,
+ DBG_BLOCK_ID_TA00 = 0x9f,
+ DBG_BLOCK_ID_TA01 = 0xa0,
+ DBG_BLOCK_ID_TA02 = 0xa1,
+ DBG_BLOCK_ID_TA03 = 0xa2,
+ DBG_BLOCK_ID_TA04 = 0xa3,
+ DBG_BLOCK_ID_TA05 = 0xa4,
+ DBG_BLOCK_ID_TA06 = 0xa5,
+ DBG_BLOCK_ID_TA07 = 0xa6,
+ DBG_BLOCK_ID_TA08 = 0xa7,
+ DBG_BLOCK_ID_TA09 = 0xa8,
+ DBG_BLOCK_ID_TA0A = 0xa9,
+ DBG_BLOCK_ID_TA0B = 0xaa,
+ DBG_BLOCK_ID_UNUSED23 = 0xab,
+ DBG_BLOCK_ID_UNUSED24 = 0xac,
+ DBG_BLOCK_ID_UNUSED25 = 0xad,
+ DBG_BLOCK_ID_UNUSED26 = 0xae,
+ DBG_BLOCK_ID_TA10 = 0xaf,
+ DBG_BLOCK_ID_TA11 = 0xb0,
+ DBG_BLOCK_ID_TA12 = 0xb1,
+ DBG_BLOCK_ID_TA13 = 0xb2,
+ DBG_BLOCK_ID_TA14 = 0xb3,
+ DBG_BLOCK_ID_TA15 = 0xb4,
+ DBG_BLOCK_ID_TA16 = 0xb5,
+ DBG_BLOCK_ID_TA17 = 0xb6,
+ DBG_BLOCK_ID_TA18 = 0xb7,
+ DBG_BLOCK_ID_TA19 = 0xb8,
+ DBG_BLOCK_ID_TA1A = 0xb9,
+ DBG_BLOCK_ID_TA1B = 0xba,
+ DBG_BLOCK_ID_UNUSED27 = 0xbb,
+ DBG_BLOCK_ID_UNUSED28 = 0xbc,
+ DBG_BLOCK_ID_UNUSED29 = 0xbd,
+ DBG_BLOCK_ID_UNUSED30 = 0xbe,
+ DBG_BLOCK_ID_TD00 = 0xbf,
+ DBG_BLOCK_ID_TD01 = 0xc0,
+ DBG_BLOCK_ID_TD02 = 0xc1,
+ DBG_BLOCK_ID_TD03 = 0xc2,
+ DBG_BLOCK_ID_TD04 = 0xc3,
+ DBG_BLOCK_ID_TD05 = 0xc4,
+ DBG_BLOCK_ID_TD06 = 0xc5,
+ DBG_BLOCK_ID_TD07 = 0xc6,
+ DBG_BLOCK_ID_TD08 = 0xc7,
+ DBG_BLOCK_ID_TD09 = 0xc8,
+ DBG_BLOCK_ID_TD0A = 0xc9,
+ DBG_BLOCK_ID_TD0B = 0xca,
+ DBG_BLOCK_ID_UNUSED31 = 0xcb,
+ DBG_BLOCK_ID_UNUSED32 = 0xcc,
+ DBG_BLOCK_ID_UNUSED33 = 0xcd,
+ DBG_BLOCK_ID_UNUSED34 = 0xce,
+ DBG_BLOCK_ID_TD10 = 0xcf,
+ DBG_BLOCK_ID_TD11 = 0xd0,
+ DBG_BLOCK_ID_TD12 = 0xd1,
+ DBG_BLOCK_ID_TD13 = 0xd2,
+ DBG_BLOCK_ID_TD14 = 0xd3,
+ DBG_BLOCK_ID_TD15 = 0xd4,
+ DBG_BLOCK_ID_TD16 = 0xd5,
+ DBG_BLOCK_ID_TD17 = 0xd6,
+ DBG_BLOCK_ID_TD18 = 0xd7,
+ DBG_BLOCK_ID_TD19 = 0xd8,
+ DBG_BLOCK_ID_TD1A = 0xd9,
+ DBG_BLOCK_ID_TD1B = 0xda,
+ DBG_BLOCK_ID_UNUSED35 = 0xdb,
+ DBG_BLOCK_ID_UNUSED36 = 0xdc,
+ DBG_BLOCK_ID_UNUSED37 = 0xdd,
+ DBG_BLOCK_ID_UNUSED38 = 0xde,
+ DBG_BLOCK_ID_LDS00 = 0xdf,
+ DBG_BLOCK_ID_LDS01 = 0xe0,
+ DBG_BLOCK_ID_LDS02 = 0xe1,
+ DBG_BLOCK_ID_LDS03 = 0xe2,
+ DBG_BLOCK_ID_LDS04 = 0xe3,
+ DBG_BLOCK_ID_LDS05 = 0xe4,
+ DBG_BLOCK_ID_LDS06 = 0xe5,
+ DBG_BLOCK_ID_LDS07 = 0xe6,
+ DBG_BLOCK_ID_LDS08 = 0xe7,
+ DBG_BLOCK_ID_LDS09 = 0xe8,
+ DBG_BLOCK_ID_LDS0A = 0xe9,
+ DBG_BLOCK_ID_LDS0B = 0xea,
+ DBG_BLOCK_ID_UNUSED39 = 0xeb,
+ DBG_BLOCK_ID_UNUSED40 = 0xec,
+ DBG_BLOCK_ID_UNUSED41 = 0xed,
+ DBG_BLOCK_ID_UNUSED42 = 0xee,
+ DBG_BLOCK_ID_LDS10 = 0xef,
+ DBG_BLOCK_ID_LDS11 = 0xf0,
+ DBG_BLOCK_ID_LDS12 = 0xf1,
+ DBG_BLOCK_ID_LDS13 = 0xf2,
+ DBG_BLOCK_ID_LDS14 = 0xf3,
+ DBG_BLOCK_ID_LDS15 = 0xf4,
+ DBG_BLOCK_ID_LDS16 = 0xf5,
+ DBG_BLOCK_ID_LDS17 = 0xf6,
+ DBG_BLOCK_ID_LDS18 = 0xf7,
+ DBG_BLOCK_ID_LDS19 = 0xf8,
+ DBG_BLOCK_ID_LDS1A = 0xf9,
+ DBG_BLOCK_ID_LDS1B = 0xfa,
+ DBG_BLOCK_ID_UNUSED43 = 0xfb,
+ DBG_BLOCK_ID_UNUSED44 = 0xfc,
+ DBG_BLOCK_ID_UNUSED45 = 0xfd,
+ DBG_BLOCK_ID_UNUSED46 = 0xfe,
+} DebugBlockId;
+typedef enum DebugBlockId_BY2 {
+ DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
+ DBG_BLOCK_ID_VMC_BY2 = 0x1,
+ DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
+ DBG_BLOCK_ID_GRBM_BY2 = 0x3,
+ DBG_BLOCK_ID_CSC_BY2 = 0x4,
+ DBG_BLOCK_ID_IH_BY2 = 0x5,
+ DBG_BLOCK_ID_SQ_BY2 = 0x6,
+ DBG_BLOCK_ID_UVD_BY2 = 0x7,
+ DBG_BLOCK_ID_SDMA0_BY2 = 0x8,
+ DBG_BLOCK_ID_SPIM_BY2 = 0x9,
+ DBG_BLOCK_ID_VC0_BY2 = 0xa,
+ DBG_BLOCK_ID_PA_BY2 = 0xb,
+ DBG_BLOCK_ID_CP0_BY2 = 0xc,
+ DBG_BLOCK_ID_CP2_BY2 = 0xd,
+ DBG_BLOCK_ID_PC0_BY2 = 0xe,
+ DBG_BLOCK_ID_BCI0_BY2 = 0xf,
+ DBG_BLOCK_ID_SXM0_BY2 = 0x10,
+ DBG_BLOCK_ID_SCT0_BY2 = 0x11,
+ DBG_BLOCK_ID_SPM0_BY2 = 0x12,
+ DBG_BLOCK_ID_BCI2_BY2 = 0x13,
+ DBG_BLOCK_ID_TCA_BY2 = 0x14,
+ DBG_BLOCK_ID_TCCA_BY2 = 0x15,
+ DBG_BLOCK_ID_MCC_BY2 = 0x16,
+ DBG_BLOCK_ID_MCC2_BY2 = 0x17,
+ DBG_BLOCK_ID_MCD_BY2 = 0x18,
+ DBG_BLOCK_ID_MCD2_BY2 = 0x19,
+ DBG_BLOCK_ID_MCD4_BY2 = 0x1a,
+ DBG_BLOCK_ID_MCB_BY2 = 0x1b,
+ DBG_BLOCK_ID_SQA_BY2 = 0x1c,
+ DBG_BLOCK_ID_SQA02_BY2 = 0x1d,
+ DBG_BLOCK_ID_SQA11_BY2 = 0x1e,
+ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f,
+ DBG_BLOCK_ID_SQB_BY2 = 0x20,
+ DBG_BLOCK_ID_SQB10_BY2 = 0x21,
+ DBG_BLOCK_ID_UNUSED10_BY2 = 0x22,
+ DBG_BLOCK_ID_UNUSED12_BY2 = 0x23,
+ DBG_BLOCK_ID_CB_BY2 = 0x24,
+ DBG_BLOCK_ID_CB02_BY2 = 0x25,
+ DBG_BLOCK_ID_CB10_BY2 = 0x26,
+ DBG_BLOCK_ID_CB12_BY2 = 0x27,
+ DBG_BLOCK_ID_SXS_BY2 = 0x28,
+ DBG_BLOCK_ID_SXS2_BY2 = 0x29,
+ DBG_BLOCK_ID_SXS4_BY2 = 0x2a,
+ DBG_BLOCK_ID_SXS6_BY2 = 0x2b,
+ DBG_BLOCK_ID_DB_BY2 = 0x2c,
+ DBG_BLOCK_ID_DB02_BY2 = 0x2d,
+ DBG_BLOCK_ID_DB10_BY2 = 0x2e,
+ DBG_BLOCK_ID_DB12_BY2 = 0x2f,
+ DBG_BLOCK_ID_TCP_BY2 = 0x30,
+ DBG_BLOCK_ID_TCP2_BY2 = 0x31,
+ DBG_BLOCK_ID_TCP4_BY2 = 0x32,
+ DBG_BLOCK_ID_TCP6_BY2 = 0x33,
+ DBG_BLOCK_ID_TCP8_BY2 = 0x34,
+ DBG_BLOCK_ID_TCP10_BY2 = 0x35,
+ DBG_BLOCK_ID_TCP12_BY2 = 0x36,
+ DBG_BLOCK_ID_TCP14_BY2 = 0x37,
+ DBG_BLOCK_ID_TCP16_BY2 = 0x38,
+ DBG_BLOCK_ID_TCP18_BY2 = 0x39,
+ DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
+ DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
+ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
+ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
+ DBG_BLOCK_ID_TCC_BY2 = 0x40,
+ DBG_BLOCK_ID_TCC2_BY2 = 0x41,
+ DBG_BLOCK_ID_TCC4_BY2 = 0x42,
+ DBG_BLOCK_ID_TCC6_BY2 = 0x43,
+ DBG_BLOCK_ID_SPS_BY2 = 0x44,
+ DBG_BLOCK_ID_SPS02_BY2 = 0x45,
+ DBG_BLOCK_ID_SPS11_BY2 = 0x46,
+ DBG_BLOCK_ID_UNUSED14_BY2 = 0x47,
+ DBG_BLOCK_ID_TA_BY2 = 0x48,
+ DBG_BLOCK_ID_TA02_BY2 = 0x49,
+ DBG_BLOCK_ID_TA04_BY2 = 0x4a,
+ DBG_BLOCK_ID_TA06_BY2 = 0x4b,
+ DBG_BLOCK_ID_TA08_BY2 = 0x4c,
+ DBG_BLOCK_ID_TA0A_BY2 = 0x4d,
+ DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e,
+ DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f,
+ DBG_BLOCK_ID_TA10_BY2 = 0x50,
+ DBG_BLOCK_ID_TA12_BY2 = 0x51,
+ DBG_BLOCK_ID_TA14_BY2 = 0x52,
+ DBG_BLOCK_ID_TA16_BY2 = 0x53,
+ DBG_BLOCK_ID_TA18_BY2 = 0x54,
+ DBG_BLOCK_ID_TA1A_BY2 = 0x55,
+ DBG_BLOCK_ID_UNUSED24_BY2 = 0x56,
+ DBG_BLOCK_ID_UNUSED26_BY2 = 0x57,
+ DBG_BLOCK_ID_TD_BY2 = 0x58,
+ DBG_BLOCK_ID_TD02_BY2 = 0x59,
+ DBG_BLOCK_ID_TD04_BY2 = 0x5a,
+ DBG_BLOCK_ID_TD06_BY2 = 0x5b,
+ DBG_BLOCK_ID_TD08_BY2 = 0x5c,
+ DBG_BLOCK_ID_TD0A_BY2 = 0x5d,
+ DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e,
+ DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f,
+ DBG_BLOCK_ID_TD10_BY2 = 0x60,
+ DBG_BLOCK_ID_TD12_BY2 = 0x61,
+ DBG_BLOCK_ID_TD14_BY2 = 0x62,
+ DBG_BLOCK_ID_TD16_BY2 = 0x63,
+ DBG_BLOCK_ID_TD18_BY2 = 0x64,
+ DBG_BLOCK_ID_TD1A_BY2 = 0x65,
+ DBG_BLOCK_ID_UNUSED32_BY2 = 0x66,
+ DBG_BLOCK_ID_UNUSED34_BY2 = 0x67,
+ DBG_BLOCK_ID_LDS_BY2 = 0x68,
+ DBG_BLOCK_ID_LDS02_BY2 = 0x69,
+ DBG_BLOCK_ID_LDS04_BY2 = 0x6a,
+ DBG_BLOCK_ID_LDS06_BY2 = 0x6b,
+ DBG_BLOCK_ID_LDS08_BY2 = 0x6c,
+ DBG_BLOCK_ID_LDS0A_BY2 = 0x6d,
+ DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e,
+ DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f,
+ DBG_BLOCK_ID_LDS10_BY2 = 0x70,
+ DBG_BLOCK_ID_LDS12_BY2 = 0x71,
+ DBG_BLOCK_ID_LDS14_BY2 = 0x72,
+ DBG_BLOCK_ID_LDS16_BY2 = 0x73,
+ DBG_BLOCK_ID_LDS18_BY2 = 0x74,
+ DBG_BLOCK_ID_LDS1A_BY2 = 0x75,
+ DBG_BLOCK_ID_UNUSED40_BY2 = 0x76,
+ DBG_BLOCK_ID_UNUSED42_BY2 = 0x77,
+} DebugBlockId_BY2;
+typedef enum DebugBlockId_BY4 {
+ DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
+ DBG_BLOCK_ID_UNUSED0_BY4 = 0x1,
+ DBG_BLOCK_ID_CSC_BY4 = 0x2,
+ DBG_BLOCK_ID_SQ_BY4 = 0x3,
+ DBG_BLOCK_ID_SDMA0_BY4 = 0x4,
+ DBG_BLOCK_ID_VC0_BY4 = 0x5,
+ DBG_BLOCK_ID_CP0_BY4 = 0x6,
+ DBG_BLOCK_ID_UNUSED1_BY4 = 0x7,
+ DBG_BLOCK_ID_SXM0_BY4 = 0x8,
+ DBG_BLOCK_ID_SPM0_BY4 = 0x9,
+ DBG_BLOCK_ID_TCAA_BY4 = 0xa,
+ DBG_BLOCK_ID_MCC_BY4 = 0xb,
+ DBG_BLOCK_ID_MCD_BY4 = 0xc,
+ DBG_BLOCK_ID_MCD4_BY4 = 0xd,
+ DBG_BLOCK_ID_SQA_BY4 = 0xe,
+ DBG_BLOCK_ID_SQA11_BY4 = 0xf,
+ DBG_BLOCK_ID_SQB_BY4 = 0x10,
+ DBG_BLOCK_ID_UNUSED10_BY4 = 0x11,
+ DBG_BLOCK_ID_CB_BY4 = 0x12,
+ DBG_BLOCK_ID_CB10_BY4 = 0x13,
+ DBG_BLOCK_ID_SXS_BY4 = 0x14,
+ DBG_BLOCK_ID_SXS4_BY4 = 0x15,
+ DBG_BLOCK_ID_DB_BY4 = 0x16,
+ DBG_BLOCK_ID_DB10_BY4 = 0x17,
+ DBG_BLOCK_ID_TCP_BY4 = 0x18,
+ DBG_BLOCK_ID_TCP4_BY4 = 0x19,
+ DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
+ DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
+ DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
+ DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
+ DBG_BLOCK_ID_TCC_BY4 = 0x20,
+ DBG_BLOCK_ID_TCC4_BY4 = 0x21,
+ DBG_BLOCK_ID_SPS_BY4 = 0x22,
+ DBG_BLOCK_ID_SPS11_BY4 = 0x23,
+ DBG_BLOCK_ID_TA_BY4 = 0x24,
+ DBG_BLOCK_ID_TA04_BY4 = 0x25,
+ DBG_BLOCK_ID_TA08_BY4 = 0x26,
+ DBG_BLOCK_ID_UNUSED20_BY4 = 0x27,
+ DBG_BLOCK_ID_TA10_BY4 = 0x28,
+ DBG_BLOCK_ID_TA14_BY4 = 0x29,
+ DBG_BLOCK_ID_TA18_BY4 = 0x2a,
+ DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b,
+ DBG_BLOCK_ID_TD_BY4 = 0x2c,
+ DBG_BLOCK_ID_TD04_BY4 = 0x2d,
+ DBG_BLOCK_ID_TD08_BY4 = 0x2e,
+ DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f,
+ DBG_BLOCK_ID_TD10_BY4 = 0x30,
+ DBG_BLOCK_ID_TD14_BY4 = 0x31,
+ DBG_BLOCK_ID_TD18_BY4 = 0x32,
+ DBG_BLOCK_ID_UNUSED32_BY4 = 0x33,
+ DBG_BLOCK_ID_LDS_BY4 = 0x34,
+ DBG_BLOCK_ID_LDS04_BY4 = 0x35,
+ DBG_BLOCK_ID_LDS08_BY4 = 0x36,
+ DBG_BLOCK_ID_UNUSED36_BY4 = 0x37,
+ DBG_BLOCK_ID_LDS10_BY4 = 0x38,
+ DBG_BLOCK_ID_LDS14_BY4 = 0x39,
+ DBG_BLOCK_ID_LDS18_BY4 = 0x3a,
+ DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b,
+} DebugBlockId_BY4;
+typedef enum DebugBlockId_BY8 {
+ DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
+ DBG_BLOCK_ID_CSC_BY8 = 0x1,
+ DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
+ DBG_BLOCK_ID_CP0_BY8 = 0x3,
+ DBG_BLOCK_ID_SXM0_BY8 = 0x4,
+ DBG_BLOCK_ID_TCA_BY8 = 0x5,
+ DBG_BLOCK_ID_MCD_BY8 = 0x6,
+ DBG_BLOCK_ID_SQA_BY8 = 0x7,
+ DBG_BLOCK_ID_SQB_BY8 = 0x8,
+ DBG_BLOCK_ID_CB_BY8 = 0x9,
+ DBG_BLOCK_ID_SXS_BY8 = 0xa,
+ DBG_BLOCK_ID_DB_BY8 = 0xb,
+ DBG_BLOCK_ID_TCP_BY8 = 0xc,
+ DBG_BLOCK_ID_TCP8_BY8 = 0xd,
+ DBG_BLOCK_ID_TCP16_BY8 = 0xe,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
+ DBG_BLOCK_ID_TCC_BY8 = 0x10,
+ DBG_BLOCK_ID_SPS_BY8 = 0x11,
+ DBG_BLOCK_ID_TA_BY8 = 0x12,
+ DBG_BLOCK_ID_TA08_BY8 = 0x13,
+ DBG_BLOCK_ID_TA10_BY8 = 0x14,
+ DBG_BLOCK_ID_TA18_BY8 = 0x15,
+ DBG_BLOCK_ID_TD_BY8 = 0x16,
+ DBG_BLOCK_ID_TD08_BY8 = 0x17,
+ DBG_BLOCK_ID_TD10_BY8 = 0x18,
+ DBG_BLOCK_ID_TD18_BY8 = 0x19,
+ DBG_BLOCK_ID_LDS_BY8 = 0x1a,
+ DBG_BLOCK_ID_LDS08_BY8 = 0x1b,
+ DBG_BLOCK_ID_LDS10_BY8 = 0x1c,
+ DBG_BLOCK_ID_LDS18_BY8 = 0x1d,
+} DebugBlockId_BY8;
+typedef enum DebugBlockId_BY16 {
+ DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
+ DBG_BLOCK_ID_SDMA0_BY16 = 0x1,
+ DBG_BLOCK_ID_SXM_BY16 = 0x2,
+ DBG_BLOCK_ID_MCD_BY16 = 0x3,
+ DBG_BLOCK_ID_SQB_BY16 = 0x4,
+ DBG_BLOCK_ID_SXS_BY16 = 0x5,
+ DBG_BLOCK_ID_TCP_BY16 = 0x6,
+ DBG_BLOCK_ID_TCP16_BY16 = 0x7,
+ DBG_BLOCK_ID_TCC_BY16 = 0x8,
+ DBG_BLOCK_ID_TA_BY16 = 0x9,
+ DBG_BLOCK_ID_TA10_BY16 = 0xa,
+ DBG_BLOCK_ID_TD_BY16 = 0xb,
+ DBG_BLOCK_ID_TD10_BY16 = 0xc,
+ DBG_BLOCK_ID_LDS_BY16 = 0xd,
+ DBG_BLOCK_ID_LDS10_BY16 = 0xe,
+} DebugBlockId_BY16;
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0x0,
+ ENDIAN_8IN16 = 0x1,
+ ENDIAN_8IN32 = 0x2,
+ ENDIAN_8IN64 = 0x3,
+} SurfaceEndian;
+typedef enum ArrayMode {
+ ARRAY_LINEAR_GENERAL = 0x0,
+ ARRAY_LINEAR_ALIGNED = 0x1,
+ ARRAY_1D_TILED_THIN1 = 0x2,
+ ARRAY_1D_TILED_THICK = 0x3,
+ ARRAY_2D_TILED_THIN1 = 0x4,
+ ARRAY_PRT_TILED_THIN1 = 0x5,
+ ARRAY_PRT_2D_TILED_THIN1 = 0x6,
+ ARRAY_2D_TILED_THICK = 0x7,
+ ARRAY_2D_TILED_XTHICK = 0x8,
+ ARRAY_PRT_TILED_THICK = 0x9,
+ ARRAY_PRT_2D_TILED_THICK = 0xa,
+ ARRAY_PRT_3D_TILED_THIN1 = 0xb,
+ ARRAY_3D_TILED_THIN1 = 0xc,
+ ARRAY_3D_TILED_THICK = 0xd,
+ ARRAY_3D_TILED_XTHICK = 0xe,
+ ARRAY_PRT_3D_TILED_THICK = 0xf,
+} ArrayMode;
+typedef enum PipeTiling {
+ CONFIG_1_PIPE = 0x0,
+ CONFIG_2_PIPE = 0x1,
+ CONFIG_4_PIPE = 0x2,
+ CONFIG_8_PIPE = 0x3,
+} PipeTiling;
+typedef enum BankTiling {
+ CONFIG_4_BANK = 0x0,
+ CONFIG_8_BANK = 0x1,
+} BankTiling;
+typedef enum GroupInterleave {
+ CONFIG_256B_GROUP = 0x0,
+ CONFIG_512B_GROUP = 0x1,
+} GroupInterleave;
+typedef enum RowTiling {
+ CONFIG_1KB_ROW = 0x0,
+ CONFIG_2KB_ROW = 0x1,
+ CONFIG_4KB_ROW = 0x2,
+ CONFIG_8KB_ROW = 0x3,
+ CONFIG_1KB_ROW_OPT = 0x4,
+ CONFIG_2KB_ROW_OPT = 0x5,
+ CONFIG_4KB_ROW_OPT = 0x6,
+ CONFIG_8KB_ROW_OPT = 0x7,
+} RowTiling;
+typedef enum BankSwapBytes {
+ CONFIG_128B_SWAPS = 0x0,
+ CONFIG_256B_SWAPS = 0x1,
+ CONFIG_512B_SWAPS = 0x2,
+ CONFIG_1KB_SWAPS = 0x3,
+} BankSwapBytes;
+typedef enum SampleSplitBytes {
+ CONFIG_1KB_SPLIT = 0x0,
+ CONFIG_2KB_SPLIT = 0x1,
+ CONFIG_4KB_SPLIT = 0x2,
+ CONFIG_8KB_SPLIT = 0x3,
+} SampleSplitBytes;
+typedef enum NumPipes {
+ ADDR_CONFIG_1_PIPE = 0x0,
+ ADDR_CONFIG_2_PIPE = 0x1,
+ ADDR_CONFIG_4_PIPE = 0x2,
+ ADDR_CONFIG_8_PIPE = 0x3,
+} NumPipes;
+typedef enum PipeInterleaveSize {
+ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
+ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
+} PipeInterleaveSize;
+typedef enum BankInterleaveSize {
+ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
+ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
+ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
+ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
+} BankInterleaveSize;
+typedef enum NumShaderEngines {
+ ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
+ ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
+} NumShaderEngines;
+typedef enum ShaderEngineTileSize {
+ ADDR_CONFIG_SE_TILE_16 = 0x0,
+ ADDR_CONFIG_SE_TILE_32 = 0x1,
+} ShaderEngineTileSize;
+typedef enum NumGPUs {
+ ADDR_CONFIG_1_GPU = 0x0,
+ ADDR_CONFIG_2_GPU = 0x1,
+ ADDR_CONFIG_4_GPU = 0x2,
+} NumGPUs;
+typedef enum MultiGPUTileSize {
+ ADDR_CONFIG_GPU_TILE_16 = 0x0,
+ ADDR_CONFIG_GPU_TILE_32 = 0x1,
+ ADDR_CONFIG_GPU_TILE_64 = 0x2,
+ ADDR_CONFIG_GPU_TILE_128 = 0x3,
+} MultiGPUTileSize;
+typedef enum RowSize {
+ ADDR_CONFIG_1KB_ROW = 0x0,
+ ADDR_CONFIG_2KB_ROW = 0x1,
+ ADDR_CONFIG_4KB_ROW = 0x2,
+} RowSize;
+typedef enum NumLowerPipes {
+ ADDR_CONFIG_1_LOWER_PIPES = 0x0,
+ ADDR_CONFIG_2_LOWER_PIPES = 0x1,
+} NumLowerPipes;
+typedef enum ColorTransform {
+ DCC_CT_AUTO = 0x0,
+ DCC_CT_NONE = 0x1,
+ ABGR_TO_A_BG_G_RB = 0x2,
+ BGRA_TO_BG_G_RB_A = 0x3,
+} ColorTransform;
+typedef enum CompareRef {
+ REF_NEVER = 0x0,
+ REF_LESS = 0x1,
+ REF_EQUAL = 0x2,
+ REF_LEQUAL = 0x3,
+ REF_GREATER = 0x4,
+ REF_NOTEQUAL = 0x5,
+ REF_GEQUAL = 0x6,
+ REF_ALWAYS = 0x7,
+} CompareRef;
+typedef enum ReadSize {
+ READ_256_BITS = 0x0,
+ READ_512_BITS = 0x1,
+} ReadSize;
+typedef enum DepthFormat {
+ DEPTH_INVALID = 0x0,
+ DEPTH_16 = 0x1,
+ DEPTH_X8_24 = 0x2,
+ DEPTH_8_24 = 0x3,
+ DEPTH_X8_24_FLOAT = 0x4,
+ DEPTH_8_24_FLOAT = 0x5,
+ DEPTH_32_FLOAT = 0x6,
+ DEPTH_X24_8_32_FLOAT = 0x7,
+} DepthFormat;
+typedef enum ZFormat {
+ Z_INVALID = 0x0,
+ Z_16 = 0x1,
+ Z_24 = 0x2,
+ Z_32_FLOAT = 0x3,
+} ZFormat;
+typedef enum StencilFormat {
+ STENCIL_INVALID = 0x0,
+ STENCIL_8 = 0x1,
+} StencilFormat;
+typedef enum CmaskMode {
+ CMASK_CLEAR_NONE = 0x0,
+ CMASK_CLEAR_ONE = 0x1,
+ CMASK_CLEAR_ALL = 0x2,
+ CMASK_ANY_EXPANDED = 0x3,
+ CMASK_ALPHA0_FRAG1 = 0x4,
+ CMASK_ALPHA0_FRAG2 = 0x5,
+ CMASK_ALPHA0_FRAG4 = 0x6,
+ CMASK_ALPHA0_FRAGS = 0x7,
+ CMASK_ALPHA1_FRAG1 = 0x8,
+ CMASK_ALPHA1_FRAG2 = 0x9,
+ CMASK_ALPHA1_FRAG4 = 0xa,
+ CMASK_ALPHA1_FRAGS = 0xb,
+ CMASK_ALPHAX_FRAG1 = 0xc,
+ CMASK_ALPHAX_FRAG2 = 0xd,
+ CMASK_ALPHAX_FRAG4 = 0xe,
+ CMASK_ALPHAX_FRAGS = 0xf,
+} CmaskMode;
+typedef enum QuadExportFormat {
+ EXPORT_UNUSED = 0x0,
+ EXPORT_32_R = 0x1,
+ EXPORT_32_GR = 0x2,
+ EXPORT_32_AR = 0x3,
+ EXPORT_FP16_ABGR = 0x4,
+ EXPORT_UNSIGNED16_ABGR = 0x5,
+ EXPORT_SIGNED16_ABGR = 0x6,
+ EXPORT_32_ABGR = 0x7,
+} QuadExportFormat;
+typedef enum QuadExportFormatOld {
+ EXPORT_4P_32BPC_ABGR = 0x0,
+ EXPORT_4P_16BPC_ABGR = 0x1,
+ EXPORT_4P_32BPC_GR = 0x2,
+ EXPORT_4P_32BPC_AR = 0x3,
+ EXPORT_2P_32BPC_ABGR = 0x4,
+ EXPORT_8P_32BPC_R = 0x5,
+} QuadExportFormatOld;
+typedef enum ColorFormat {
+ COLOR_INVALID = 0x0,
+ COLOR_8 = 0x1,
+ COLOR_16 = 0x2,
+ COLOR_8_8 = 0x3,
+ COLOR_32 = 0x4,
+ COLOR_16_16 = 0x5,
+ COLOR_10_11_11 = 0x6,
+ COLOR_11_11_10 = 0x7,
+ COLOR_10_10_10_2 = 0x8,
+ COLOR_2_10_10_10 = 0x9,
+ COLOR_8_8_8_8 = 0xa,
+ COLOR_32_32 = 0xb,
+ COLOR_16_16_16_16 = 0xc,
+ COLOR_RESERVED_13 = 0xd,
+ COLOR_32_32_32_32 = 0xe,
+ COLOR_RESERVED_15 = 0xf,
+ COLOR_5_6_5 = 0x10,
+ COLOR_1_5_5_5 = 0x11,
+ COLOR_5_5_5_1 = 0x12,
+ COLOR_4_4_4_4 = 0x13,
+ COLOR_8_24 = 0x14,
+ COLOR_24_8 = 0x15,
+ COLOR_X24_8_32_FLOAT = 0x16,
+ COLOR_RESERVED_23 = 0x17,
+} ColorFormat;
+typedef enum SurfaceFormat {
+ FMT_INVALID = 0x0,
+ FMT_8 = 0x1,
+ FMT_16 = 0x2,
+ FMT_8_8 = 0x3,
+ FMT_32 = 0x4,
+ FMT_16_16 = 0x5,
+ FMT_10_11_11 = 0x6,
+ FMT_11_11_10 = 0x7,
+ FMT_10_10_10_2 = 0x8,
+ FMT_2_10_10_10 = 0x9,
+ FMT_8_8_8_8 = 0xa,
+ FMT_32_32 = 0xb,
+ FMT_16_16_16_16 = 0xc,
+ FMT_32_32_32 = 0xd,
+ FMT_32_32_32_32 = 0xe,
+ FMT_RESERVED_4 = 0xf,
+ FMT_5_6_5 = 0x10,
+ FMT_1_5_5_5 = 0x11,
+ FMT_5_5_5_1 = 0x12,
+ FMT_4_4_4_4 = 0x13,
+ FMT_8_24 = 0x14,
+ FMT_24_8 = 0x15,
+ FMT_X24_8_32_FLOAT = 0x16,
+ FMT_RESERVED_33 = 0x17,
+ FMT_11_11_10_FLOAT = 0x18,
+ FMT_16_FLOAT = 0x19,
+ FMT_32_FLOAT = 0x1a,
+ FMT_16_16_FLOAT = 0x1b,
+ FMT_8_24_FLOAT = 0x1c,
+ FMT_24_8_FLOAT = 0x1d,
+ FMT_32_32_FLOAT = 0x1e,
+ FMT_10_11_11_FLOAT = 0x1f,
+ FMT_16_16_16_16_FLOAT = 0x20,
+ FMT_3_3_2 = 0x21,
+ FMT_6_5_5 = 0x22,
+ FMT_32_32_32_32_FLOAT = 0x23,
+ FMT_RESERVED_36 = 0x24,
+ FMT_1 = 0x25,
+ FMT_1_REVERSED = 0x26,
+ FMT_GB_GR = 0x27,
+ FMT_BG_RG = 0x28,
+ FMT_32_AS_8 = 0x29,
+ FMT_32_AS_8_8 = 0x2a,
+ FMT_5_9_9_9_SHAREDEXP = 0x2b,
+ FMT_8_8_8 = 0x2c,
+ FMT_16_16_16 = 0x2d,
+ FMT_16_16_16_FLOAT = 0x2e,
+ FMT_4_4 = 0x2f,
+ FMT_32_32_32_FLOAT = 0x30,
+ FMT_BC1 = 0x31,
+ FMT_BC2 = 0x32,
+ FMT_BC3 = 0x33,
+ FMT_BC4 = 0x34,
+ FMT_BC5 = 0x35,
+ FMT_BC6 = 0x36,
+ FMT_BC7 = 0x37,
+ FMT_32_AS_32_32_32_32 = 0x38,
+ FMT_APC3 = 0x39,
+ FMT_APC4 = 0x3a,
+ FMT_APC5 = 0x3b,
+ FMT_APC6 = 0x3c,
+ FMT_APC7 = 0x3d,
+ FMT_CTX1 = 0x3e,
+ FMT_RESERVED_63 = 0x3f,
+} SurfaceFormat;
+typedef enum BUF_DATA_FORMAT {
+ BUF_DATA_FORMAT_INVALID = 0x0,
+ BUF_DATA_FORMAT_8 = 0x1,
+ BUF_DATA_FORMAT_16 = 0x2,
+ BUF_DATA_FORMAT_8_8 = 0x3,
+ BUF_DATA_FORMAT_32 = 0x4,
+ BUF_DATA_FORMAT_16_16 = 0x5,
+ BUF_DATA_FORMAT_10_11_11 = 0x6,
+ BUF_DATA_FORMAT_11_11_10 = 0x7,
+ BUF_DATA_FORMAT_10_10_10_2 = 0x8,
+ BUF_DATA_FORMAT_2_10_10_10 = 0x9,
+ BUF_DATA_FORMAT_8_8_8_8 = 0xa,
+ BUF_DATA_FORMAT_32_32 = 0xb,
+ BUF_DATA_FORMAT_16_16_16_16 = 0xc,
+ BUF_DATA_FORMAT_32_32_32 = 0xd,
+ BUF_DATA_FORMAT_32_32_32_32 = 0xe,
+ BUF_DATA_FORMAT_RESERVED_15 = 0xf,
+} BUF_DATA_FORMAT;
+typedef enum IMG_DATA_FORMAT {
+ IMG_DATA_FORMAT_INVALID = 0x0,
+ IMG_DATA_FORMAT_8 = 0x1,
+ IMG_DATA_FORMAT_16 = 0x2,
+ IMG_DATA_FORMAT_8_8 = 0x3,
+ IMG_DATA_FORMAT_32 = 0x4,
+ IMG_DATA_FORMAT_16_16 = 0x5,
+ IMG_DATA_FORMAT_10_11_11 = 0x6,
+ IMG_DATA_FORMAT_11_11_10 = 0x7,
+ IMG_DATA_FORMAT_10_10_10_2 = 0x8,
+ IMG_DATA_FORMAT_2_10_10_10 = 0x9,
+ IMG_DATA_FORMAT_8_8_8_8 = 0xa,
+ IMG_DATA_FORMAT_32_32 = 0xb,
+ IMG_DATA_FORMAT_16_16_16_16 = 0xc,
+ IMG_DATA_FORMAT_32_32_32 = 0xd,
+ IMG_DATA_FORMAT_32_32_32_32 = 0xe,
+ IMG_DATA_FORMAT_RESERVED_15 = 0xf,
+ IMG_DATA_FORMAT_5_6_5 = 0x10,
+ IMG_DATA_FORMAT_1_5_5_5 = 0x11,
+ IMG_DATA_FORMAT_5_5_5_1 = 0x12,
+ IMG_DATA_FORMAT_4_4_4_4 = 0x13,
+ IMG_DATA_FORMAT_8_24 = 0x14,
+ IMG_DATA_FORMAT_24_8 = 0x15,
+ IMG_DATA_FORMAT_X24_8_32 = 0x16,
+ IMG_DATA_FORMAT_RESERVED_23 = 0x17,
+ IMG_DATA_FORMAT_RESERVED_24 = 0x18,
+ IMG_DATA_FORMAT_RESERVED_25 = 0x19,
+ IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
+ IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
+ IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
+ IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
+ IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
+ IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
+ IMG_DATA_FORMAT_GB_GR = 0x20,
+ IMG_DATA_FORMAT_BG_RG = 0x21,
+ IMG_DATA_FORMAT_5_9_9_9 = 0x22,
+ IMG_DATA_FORMAT_BC1 = 0x23,
+ IMG_DATA_FORMAT_BC2 = 0x24,
+ IMG_DATA_FORMAT_BC3 = 0x25,
+ IMG_DATA_FORMAT_BC4 = 0x26,
+ IMG_DATA_FORMAT_BC5 = 0x27,
+ IMG_DATA_FORMAT_BC6 = 0x28,
+ IMG_DATA_FORMAT_BC7 = 0x29,
+ IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
+ IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
+ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
+ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
+ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
+ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
+ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
+ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
+ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
+ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
+ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
+ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
+ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
+ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
+ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
+ IMG_DATA_FORMAT_4_4 = 0x39,
+ IMG_DATA_FORMAT_6_5_5 = 0x3a,
+ IMG_DATA_FORMAT_1 = 0x3b,
+ IMG_DATA_FORMAT_1_REVERSED = 0x3c,
+ IMG_DATA_FORMAT_32_AS_8 = 0x3d,
+ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
+ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
+} IMG_DATA_FORMAT;
+typedef enum BUF_NUM_FORMAT {
+ BUF_NUM_FORMAT_UNORM = 0x0,
+ BUF_NUM_FORMAT_SNORM = 0x1,
+ BUF_NUM_FORMAT_USCALED = 0x2,
+ BUF_NUM_FORMAT_SSCALED = 0x3,
+ BUF_NUM_FORMAT_UINT = 0x4,
+ BUF_NUM_FORMAT_SINT = 0x5,
+ BUF_NUM_FORMAT_RESERVED_6 = 0x6,
+ BUF_NUM_FORMAT_FLOAT = 0x7,
+} BUF_NUM_FORMAT;
+typedef enum IMG_NUM_FORMAT {
+ IMG_NUM_FORMAT_UNORM = 0x0,
+ IMG_NUM_FORMAT_SNORM = 0x1,
+ IMG_NUM_FORMAT_USCALED = 0x2,
+ IMG_NUM_FORMAT_SSCALED = 0x3,
+ IMG_NUM_FORMAT_UINT = 0x4,
+ IMG_NUM_FORMAT_SINT = 0x5,
+ IMG_NUM_FORMAT_RESERVED_6 = 0x6,
+ IMG_NUM_FORMAT_FLOAT = 0x7,
+ IMG_NUM_FORMAT_RESERVED_8 = 0x8,
+ IMG_NUM_FORMAT_SRGB = 0x9,
+ IMG_NUM_FORMAT_RESERVED_10 = 0xa,
+ IMG_NUM_FORMAT_RESERVED_11 = 0xb,
+ IMG_NUM_FORMAT_RESERVED_12 = 0xc,
+ IMG_NUM_FORMAT_RESERVED_13 = 0xd,
+ IMG_NUM_FORMAT_RESERVED_14 = 0xe,
+ IMG_NUM_FORMAT_RESERVED_15 = 0xf,
+} IMG_NUM_FORMAT;
+typedef enum TileType {
+ ARRAY_COLOR_TILE = 0x0,
+ ARRAY_DEPTH_TILE = 0x1,
+} TileType;
+typedef enum NonDispTilingOrder {
+ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
+ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
+} NonDispTilingOrder;
+typedef enum MicroTileMode {
+ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
+ ADDR_SURF_THIN_MICRO_TILING = 0x1,
+ ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
+ ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
+ ADDR_SURF_THICK_MICRO_TILING = 0x4,
+} MicroTileMode;
+typedef enum TileSplit {
+ ADDR_SURF_TILE_SPLIT_64B = 0x0,
+ ADDR_SURF_TILE_SPLIT_128B = 0x1,
+ ADDR_SURF_TILE_SPLIT_256B = 0x2,
+ ADDR_SURF_TILE_SPLIT_512B = 0x3,
+ ADDR_SURF_TILE_SPLIT_1KB = 0x4,
+ ADDR_SURF_TILE_SPLIT_2KB = 0x5,
+ ADDR_SURF_TILE_SPLIT_4KB = 0x6,
+} TileSplit;
+typedef enum SampleSplit {
+ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
+ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
+ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
+ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
+} SampleSplit;
+typedef enum PipeConfig {
+ ADDR_SURF_P2 = 0x0,
+ ADDR_SURF_P2_RESERVED0 = 0x1,
+ ADDR_SURF_P2_RESERVED1 = 0x2,
+ ADDR_SURF_P2_RESERVED2 = 0x3,
+ ADDR_SURF_P4_8x16 = 0x4,
+ ADDR_SURF_P4_16x16 = 0x5,
+ ADDR_SURF_P4_16x32 = 0x6,
+ ADDR_SURF_P4_32x32 = 0x7,
+ ADDR_SURF_P8_16x16_8x16 = 0x8,
+ ADDR_SURF_P8_16x32_8x16 = 0x9,
+ ADDR_SURF_P8_32x32_8x16 = 0xa,
+ ADDR_SURF_P8_16x32_16x16 = 0xb,
+ ADDR_SURF_P8_32x32_16x16 = 0xc,
+ ADDR_SURF_P8_32x32_16x32 = 0xd,
+ ADDR_SURF_P8_32x64_32x32 = 0xe,
+ ADDR_SURF_P8_RESERVED0 = 0xf,
+ ADDR_SURF_P16_32x32_8x16 = 0x10,
+ ADDR_SURF_P16_32x32_16x16 = 0x11,
+} PipeConfig;
+typedef enum NumBanks {
+ ADDR_SURF_2_BANK = 0x0,
+ ADDR_SURF_4_BANK = 0x1,
+ ADDR_SURF_8_BANK = 0x2,
+ ADDR_SURF_16_BANK = 0x3,
+} NumBanks;
+typedef enum BankWidth {
+ ADDR_SURF_BANK_WIDTH_1 = 0x0,
+ ADDR_SURF_BANK_WIDTH_2 = 0x1,
+ ADDR_SURF_BANK_WIDTH_4 = 0x2,
+ ADDR_SURF_BANK_WIDTH_8 = 0x3,
+} BankWidth;
+typedef enum BankHeight {
+ ADDR_SURF_BANK_HEIGHT_1 = 0x0,
+ ADDR_SURF_BANK_HEIGHT_2 = 0x1,
+ ADDR_SURF_BANK_HEIGHT_4 = 0x2,
+ ADDR_SURF_BANK_HEIGHT_8 = 0x3,
+} BankHeight;
+typedef enum BankWidthHeight {
+ ADDR_SURF_BANK_WH_1 = 0x0,
+ ADDR_SURF_BANK_WH_2 = 0x1,
+ ADDR_SURF_BANK_WH_4 = 0x2,
+ ADDR_SURF_BANK_WH_8 = 0x3,
+} BankWidthHeight;
+typedef enum MacroTileAspect {
+ ADDR_SURF_MACRO_ASPECT_1 = 0x0,
+ ADDR_SURF_MACRO_ASPECT_2 = 0x1,
+ ADDR_SURF_MACRO_ASPECT_4 = 0x2,
+ ADDR_SURF_MACRO_ASPECT_8 = 0x3,
+} MacroTileAspect;
+typedef enum GATCL1RequestType {
+ GATCL1_TYPE_NORMAL = 0x0,
+ GATCL1_TYPE_SHOOTDOWN = 0x1,
+ GATCL1_TYPE_BYPASS = 0x2,
+} GATCL1RequestType;
+typedef enum TCC_CACHE_POLICIES {
+ TCC_CACHE_POLICY_LRU = 0x0,
+ TCC_CACHE_POLICY_STREAM = 0x1,
+} TCC_CACHE_POLICIES;
+typedef enum MTYPE {
+ MTYPE_NC_NV = 0x0,
+ MTYPE_NC = 0x1,
+ MTYPE_CC = 0x2,
+ MTYPE_UC = 0x3,
+} MTYPE;
+typedef enum PERFMON_COUNTER_MODE {
+ PERFMON_COUNTER_MODE_ACCUM = 0x0,
+ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
+ PERFMON_COUNTER_MODE_MAX = 0x2,
+ PERFMON_COUNTER_MODE_DIRTY = 0x3,
+ PERFMON_COUNTER_MODE_SAMPLE = 0x4,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
+ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
+ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
+ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
+ PERFMON_COUNTER_MODE_RESERVED = 0xf,
+} PERFMON_COUNTER_MODE;
+typedef enum PERFMON_SPM_MODE {
+ PERFMON_SPM_MODE_OFF = 0x0,
+ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
+ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
+ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
+ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
+ PERFMON_SPM_MODE_RESERVED_5 = 0x5,
+ PERFMON_SPM_MODE_RESERVED_6 = 0x6,
+ PERFMON_SPM_MODE_RESERVED_7 = 0x7,
+ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
+ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
+ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
+} PERFMON_SPM_MODE;
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0x0,
+ ARRAY_TILED = 0x1,
+} SurfaceTiling;
+typedef enum SurfaceArray {
+ ARRAY_1D = 0x0,
+ ARRAY_2D = 0x1,
+ ARRAY_3D = 0x2,
+ ARRAY_3D_SLICE = 0x3,
+} SurfaceArray;
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0x0,
+ ARRAY_2D_COLOR = 0x1,
+ ARRAY_3D_SLICE_COLOR = 0x3,
+} ColorArray;
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0x0,
+ ARRAY_2D_DEPTH = 0x1,
+} DepthArray;
+typedef enum ENUM_NUM_SIMD_PER_CU {
+ NUM_SIMD_PER_CU = 0x4,
+} ENUM_NUM_SIMD_PER_CU;
+typedef enum MEM_PWR_FORCE_CTRL {
+ NO_FORCE_REQUEST = 0x0,
+ FORCE_LIGHT_SLEEP_REQUEST = 0x1,
+ FORCE_DEEP_SLEEP_REQUEST = 0x2,
+ FORCE_SHUT_DOWN_REQUEST = 0x3,
+} MEM_PWR_FORCE_CTRL;
+typedef enum MEM_PWR_FORCE_CTRL2 {
+ NO_FORCE_REQ = 0x0,
+ FORCE_LIGHT_SLEEP_REQ = 0x1,
+} MEM_PWR_FORCE_CTRL2;
+typedef enum MEM_PWR_DIS_CTRL {
+ ENABLE_MEM_PWR_CTRL = 0x0,
+ DISABLE_MEM_PWR_CTRL = 0x1,
+} MEM_PWR_DIS_CTRL;
+typedef enum MEM_PWR_SEL_CTRL {
+ DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
+ DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
+ DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
+} MEM_PWR_SEL_CTRL;
+typedef enum MEM_PWR_SEL_CTRL2 {
+ DYNAMIC_DEEP_SLEEP_EN = 0x0,
+ DYNAMIC_LIGHT_SLEEP_EN = 0x1,
+} MEM_PWR_SEL_CTRL2;
+
+#endif /* OSS_3_0_1_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h
new file mode 100644
index 000000000000..cfacd8509bbb
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h
@@ -0,0 +1,3558 @@
+/*
+ * OSS_3_0_1 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef OSS_3_0_1_SH_MASK_H
+#define OSS_3_0_1_SH_MASK_H
+
+#define IH_VMID_0_LUT__PASID_MASK 0xffff
+#define IH_VMID_0_LUT__PASID__SHIFT 0x0
+#define IH_VMID_1_LUT__PASID_MASK 0xffff
+#define IH_VMID_1_LUT__PASID__SHIFT 0x0
+#define IH_VMID_2_LUT__PASID_MASK 0xffff
+#define IH_VMID_2_LUT__PASID__SHIFT 0x0
+#define IH_VMID_3_LUT__PASID_MASK 0xffff
+#define IH_VMID_3_LUT__PASID__SHIFT 0x0
+#define IH_VMID_4_LUT__PASID_MASK 0xffff
+#define IH_VMID_4_LUT__PASID__SHIFT 0x0
+#define IH_VMID_5_LUT__PASID_MASK 0xffff
+#define IH_VMID_5_LUT__PASID__SHIFT 0x0
+#define IH_VMID_6_LUT__PASID_MASK 0xffff
+#define IH_VMID_6_LUT__PASID__SHIFT 0x0
+#define IH_VMID_7_LUT__PASID_MASK 0xffff
+#define IH_VMID_7_LUT__PASID__SHIFT 0x0
+#define IH_VMID_8_LUT__PASID_MASK 0xffff
+#define IH_VMID_8_LUT__PASID__SHIFT 0x0
+#define IH_VMID_9_LUT__PASID_MASK 0xffff
+#define IH_VMID_9_LUT__PASID__SHIFT 0x0
+#define IH_VMID_10_LUT__PASID_MASK 0xffff
+#define IH_VMID_10_LUT__PASID__SHIFT 0x0
+#define IH_VMID_11_LUT__PASID_MASK 0xffff
+#define IH_VMID_11_LUT__PASID__SHIFT 0x0
+#define IH_VMID_12_LUT__PASID_MASK 0xffff
+#define IH_VMID_12_LUT__PASID__SHIFT 0x0
+#define IH_VMID_13_LUT__PASID_MASK 0xffff
+#define IH_VMID_13_LUT__PASID__SHIFT 0x0
+#define IH_VMID_14_LUT__PASID_MASK 0xffff
+#define IH_VMID_14_LUT__PASID__SHIFT 0x0
+#define IH_VMID_15_LUT__PASID_MASK 0xffff
+#define IH_VMID_15_LUT__PASID__SHIFT 0x0
+#define IH_RB_CNTL__RB_ENABLE_MASK 0x1
+#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define IH_RB_CNTL__RB_SIZE_MASK 0x3e
+#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x40
+#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x6
+#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x80
+#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7
+#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100
+#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
+#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00
+#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
+#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x10000
+#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10
+#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
+#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define IH_RB_BASE__ADDR_MASK 0xffffffff
+#define IH_RB_BASE__ADDR__SHIFT 0x0
+#define IH_RB_RPTR__OFFSET_MASK 0x3fffc
+#define IH_RB_RPTR__OFFSET__SHIFT 0x2
+#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1
+#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0
+#define IH_RB_WPTR__OFFSET_MASK 0x3fffc
+#define IH_RB_WPTR__OFFSET__SHIFT 0x2
+#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x40000
+#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12
+#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x80000
+#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13
+#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0xff
+#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define IH_CNTL__ENABLE_INTR_MASK 0x1
+#define IH_CNTL__ENABLE_INTR__SHIFT 0x0
+#define IH_CNTL__MC_SWAP_MASK 0x6
+#define IH_CNTL__MC_SWAP__SHIFT 0x1
+#define IH_CNTL__RPTR_REARM_MASK 0x10
+#define IH_CNTL__RPTR_REARM__SHIFT 0x4
+#define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x300
+#define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x8
+#define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x7c00
+#define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa
+#define IH_CNTL__MC_WRREQ_CREDIT_MASK 0xf8000
+#define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0xf
+#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x1f00000
+#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14
+#define IH_CNTL__MC_VMID_MASK 0x1e000000
+#define IH_CNTL__MC_VMID__SHIFT 0x19
+#define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1
+#define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x0
+#define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x4
+#define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2
+#define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x8
+#define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x3
+#define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x10
+#define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x4
+#define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x20
+#define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x5
+#define IH_STATUS__IDLE_MASK 0x1
+#define IH_STATUS__IDLE__SHIFT 0x0
+#define IH_STATUS__INPUT_IDLE_MASK 0x2
+#define IH_STATUS__INPUT_IDLE__SHIFT 0x1
+#define IH_STATUS__RB_IDLE_MASK 0x4
+#define IH_STATUS__RB_IDLE__SHIFT 0x2
+#define IH_STATUS__RB_FULL_MASK 0x8
+#define IH_STATUS__RB_FULL__SHIFT 0x3
+#define IH_STATUS__RB_FULL_DRAIN_MASK 0x10
+#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4
+#define IH_STATUS__RB_OVERFLOW_MASK 0x20
+#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5
+#define IH_STATUS__MC_WR_IDLE_MASK 0x40
+#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6
+#define IH_STATUS__MC_WR_STALL_MASK 0x80
+#define IH_STATUS__MC_WR_STALL__SHIFT 0x7
+#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x100
+#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8
+#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x200
+#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9
+#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x400
+#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa
+#define IH_PERFMON_CNTL__ENABLE0_MASK 0x1
+#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0
+#define IH_PERFMON_CNTL__CLEAR0_MASK 0x2
+#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1
+#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
+#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
+#define IH_PERFMON_CNTL__ENABLE1_MASK 0x100
+#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x8
+#define IH_PERFMON_CNTL__CLEAR1_MASK 0x200
+#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x9
+#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
+#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
+#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
+#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
+#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
+#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
+#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xffffffff
+#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0
+#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xffffffff
+#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0
+#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xffffffff
+#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0
+#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x1
+#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0
+#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x4
+#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2
+#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x8
+#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3
+#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x10
+#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4
+#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x20
+#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5
+#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0xfffffff
+#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0
+#define IH_VERSION__VALUE_MASK 0xfff
+#define IH_VERSION__VALUE__SHIFT 0x0
+#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x3
+#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0
+#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0xfc
+#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2
+#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x3f00
+#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8
+#define SEM_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
+#define SEM_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
+#define SEM_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
+#define SEM_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
+#define SEM_PERFMON_CNTL__PERF_SEL0_MASK 0x3fc
+#define SEM_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
+#define SEM_PERFMON_CNTL__PERF_ENABLE1_MASK 0x400
+#define SEM_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
+#define SEM_PERFMON_CNTL__PERF_CLEAR1_MASK 0x800
+#define SEM_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb
+#define SEM_PERFMON_CNTL__PERF_SEL1_MASK 0xff000
+#define SEM_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc
+#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
+#define SEM_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
+#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
+#define SEM_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
+#define SEM_VF_ENABLE__VALUE_MASK 0x1
+#define SEM_VF_ENABLE__VALUE__SHIFT 0x0
+#define SEM_ACTIVE_FCN_ID__VFID_MASK 0xf
+#define SEM_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define SEM_ACTIVE_FCN_ID__VF_MASK 0x80000000
+#define SEM_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define SEM_VIRT_RESET_REQ__VF_MASK 0xffff
+#define SEM_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define SEM_VIRT_RESET_REQ__PF_MASK 0x80000000
+#define SEM_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define SEM_STATUS__SEM_IDLE_MASK 0x1
+#define SEM_STATUS__SEM_IDLE__SHIFT 0x0
+#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x2
+#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1
+#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x4
+#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2
+#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x8
+#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3
+#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x10
+#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4
+#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x20
+#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5
+#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x40
+#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6
+#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x80
+#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7
+#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x100
+#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8
+#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x200
+#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9
+#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x400
+#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa
+#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x800
+#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb
+#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x1000
+#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc
+#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x2000
+#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd
+#define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x4000
+#define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0xe
+#define SEM_STATUS__ATC_REQ_PENDING_MASK 0x8000
+#define SEM_STATUS__ATC_REQ_PENDING__SHIFT 0xf
+#define SEM_STATUS__SWITCH_READY_MASK 0x80000000
+#define SEM_STATUS__SWITCH_READY__SHIFT 0x1f
+#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x2
+#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x7
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x38
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x1c0
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0xe00
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x7000
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc
+#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x38000
+#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x1c0000
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12
+#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0xe00000
+#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15
+#define SEM_MAILBOX__SIDEPORT_MASK 0xff
+#define SEM_MAILBOX__SIDEPORT__SHIFT 0x0
+#define SEM_MAILBOX__HOSTPORT_MASK 0xff00
+#define SEM_MAILBOX__HOSTPORT__SHIFT 0x8
+#define SEM_MAILBOX__SIDEPORT_EXTRA_MASK 0xff0000
+#define SEM_MAILBOX__SIDEPORT_EXTRA__SHIFT 0x10
+#define SEM_MAILBOX__HOSTPORT_EXTRA_MASK 0xff000000
+#define SEM_MAILBOX__HOSTPORT_EXTRA__SHIFT 0x18
+#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0xff
+#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x0
+#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0xff00
+#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x8
+#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA_MASK 0xff0000
+#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA__SHIFT 0x10
+#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA_MASK 0xff000000
+#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA__SHIFT 0x18
+#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x1
+#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0
+#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x2
+#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1
+#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x4
+#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2
+#define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x18
+#define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x3
+#define SEM_CHICKEN_BITS__SIGNAL_FAIL_MASK 0x20
+#define SEM_CHICKEN_BITS__SIGNAL_FAIL__SHIFT 0x5
+#define SEM_CHICKEN_BITS__PHY_TRAN_EN_MASK 0x40
+#define SEM_CHICKEN_BITS__PHY_TRAN_EN__SHIFT 0x6
+#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN_MASK 0x80
+#define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN__SHIFT 0x7
+#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0xf00
+#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x8
+#define SEM_CHICKEN_BITS__ATCL2_BUS_ID_MASK 0x3000
+#define SEM_CHICKEN_BITS__ATCL2_BUS_ID__SHIFT 0xc
+#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x1f
+#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x0
+#define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x10000
+#define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x10
+#define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x20000
+#define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x11
+#define SRBM_CNTL__REPORT_LAST_RDERR_MASK 0x40000
+#define SRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x12
+#define SRBM_CNTL__PWR_GFX3D_REQUEST_HALT_MASK 0x80000
+#define SRBM_CNTL__PWR_GFX3D_REQUEST_HALT__SHIFT 0x13
+#define SRBM_GFX_CNTL__PIPEID_MASK 0x3
+#define SRBM_GFX_CNTL__PIPEID__SHIFT 0x0
+#define SRBM_GFX_CNTL__MEID_MASK 0xc
+#define SRBM_GFX_CNTL__MEID__SHIFT 0x2
+#define SRBM_GFX_CNTL__VMID_MASK 0xf0
+#define SRBM_GFX_CNTL__VMID__SHIFT 0x4
+#define SRBM_GFX_CNTL__QUEUEID_MASK 0x700
+#define SRBM_GFX_CNTL__QUEUEID__SHIFT 0x8
+#define SRBM_READ_CNTL__READ_TIMEOUT_MASK 0xffffff
+#define SRBM_READ_CNTL__READ_TIMEOUT__SHIFT 0x0
+#define SRBM_STATUS2__SDMA_RQ_PENDING_MASK 0x1
+#define SRBM_STATUS2__SDMA_RQ_PENDING__SHIFT 0x0
+#define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x2
+#define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x1
+#define SRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x4
+#define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x2
+#define SRBM_STATUS2__VCE0_RQ_PENDING_MASK 0x8
+#define SRBM_STATUS2__VCE0_RQ_PENDING__SHIFT 0x3
+#define SRBM_STATUS2__VP8_BUSY_MASK 0x10
+#define SRBM_STATUS2__VP8_BUSY__SHIFT 0x4
+#define SRBM_STATUS2__SDMA_BUSY_MASK 0x20
+#define SRBM_STATUS2__SDMA_BUSY__SHIFT 0x5
+#define SRBM_STATUS2__SDMA1_BUSY_MASK 0x40
+#define SRBM_STATUS2__SDMA1_BUSY__SHIFT 0x6
+#define SRBM_STATUS2__VCE0_BUSY_MASK 0x80
+#define SRBM_STATUS2__VCE0_BUSY__SHIFT 0x7
+#define SRBM_STATUS2__XDMA_BUSY_MASK 0x100
+#define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x8
+#define SRBM_STATUS2__CHUB_BUSY_MASK 0x200
+#define SRBM_STATUS2__CHUB_BUSY__SHIFT 0x9
+#define SRBM_STATUS2__SDMA2_BUSY_MASK 0x400
+#define SRBM_STATUS2__SDMA2_BUSY__SHIFT 0xa
+#define SRBM_STATUS2__SDMA3_BUSY_MASK 0x800
+#define SRBM_STATUS2__SDMA3_BUSY__SHIFT 0xb
+#define SRBM_STATUS2__ISP_BUSY_MASK 0x2000
+#define SRBM_STATUS2__ISP_BUSY__SHIFT 0xd
+#define SRBM_STATUS2__VCE1_BUSY_MASK 0x4000
+#define SRBM_STATUS2__VCE1_BUSY__SHIFT 0xe
+#define SRBM_STATUS2__ODE_BUSY_MASK 0x8000
+#define SRBM_STATUS2__ODE_BUSY__SHIFT 0xf
+#define SRBM_STATUS2__SDMA2_RQ_PENDING_MASK 0x10000
+#define SRBM_STATUS2__SDMA2_RQ_PENDING__SHIFT 0x10
+#define SRBM_STATUS2__SDMA3_RQ_PENDING_MASK 0x20000
+#define SRBM_STATUS2__SDMA3_RQ_PENDING__SHIFT 0x11
+#define SRBM_STATUS2__VP8_RQ_PENDING_MASK 0x40000
+#define SRBM_STATUS2__VP8_RQ_PENDING__SHIFT 0x12
+#define SRBM_STATUS2__ISP_RQ_PENDING_MASK 0x80000
+#define SRBM_STATUS2__ISP_RQ_PENDING__SHIFT 0x13
+#define SRBM_STATUS2__VCE1_RQ_PENDING_MASK 0x100000
+#define SRBM_STATUS2__VCE1_RQ_PENDING__SHIFT 0x14
+#define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x2
+#define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x1
+#define SRBM_STATUS__SAMMSP_RQ_PENDING_MASK 0x4
+#define SRBM_STATUS__SAMMSP_RQ_PENDING__SHIFT 0x2
+#define SRBM_STATUS__ACP_RQ_PENDING_MASK 0x8
+#define SRBM_STATUS__ACP_RQ_PENDING__SHIFT 0x3
+#define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x10
+#define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x4
+#define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x20
+#define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x5
+#define SRBM_STATUS__HI_RQ_PENDING_MASK 0x40
+#define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x6
+#define SRBM_STATUS__VMC_BUSY_MASK 0x100
+#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8
+#define SRBM_STATUS__MCB_BUSY_MASK 0x200
+#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9
+#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400
+#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa
+#define SRBM_STATUS__MCC_BUSY_MASK 0x800
+#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb
+#define SRBM_STATUS__MCD_BUSY_MASK 0x1000
+#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc
+#define SRBM_STATUS__VMC1_BUSY_MASK 0x2000
+#define SRBM_STATUS__VMC1_BUSY__SHIFT 0xd
+#define SRBM_STATUS__SEM_BUSY_MASK 0x4000
+#define SRBM_STATUS__SEM_BUSY__SHIFT 0xe
+#define SRBM_STATUS__ACP_BUSY_MASK 0x10000
+#define SRBM_STATUS__ACP_BUSY__SHIFT 0x10
+#define SRBM_STATUS__IH_BUSY_MASK 0x20000
+#define SRBM_STATUS__IH_BUSY__SHIFT 0x11
+#define SRBM_STATUS__UVD_BUSY_MASK 0x80000
+#define SRBM_STATUS__UVD_BUSY__SHIFT 0x13
+#define SRBM_STATUS__SAMMSP_BUSY_MASK 0x100000
+#define SRBM_STATUS__SAMMSP_BUSY__SHIFT 0x14
+#define SRBM_STATUS__GCATCL2_BUSY_MASK 0x200000
+#define SRBM_STATUS__GCATCL2_BUSY__SHIFT 0x15
+#define SRBM_STATUS__OSATCL2_BUSY_MASK 0x400000
+#define SRBM_STATUS__OSATCL2_BUSY__SHIFT 0x16
+#define SRBM_STATUS__BIF_BUSY_MASK 0x20000000
+#define SRBM_STATUS__BIF_BUSY__SHIFT 0x1d
+#define SRBM_STATUS3__MCC0_BUSY_MASK 0x1
+#define SRBM_STATUS3__MCC0_BUSY__SHIFT 0x0
+#define SRBM_STATUS3__MCC1_BUSY_MASK 0x2
+#define SRBM_STATUS3__MCC1_BUSY__SHIFT 0x1
+#define SRBM_STATUS3__MCC2_BUSY_MASK 0x4
+#define SRBM_STATUS3__MCC2_BUSY__SHIFT 0x2
+#define SRBM_STATUS3__MCC3_BUSY_MASK 0x8
+#define SRBM_STATUS3__MCC3_BUSY__SHIFT 0x3
+#define SRBM_STATUS3__MCC4_BUSY_MASK 0x10
+#define SRBM_STATUS3__MCC4_BUSY__SHIFT 0x4
+#define SRBM_STATUS3__MCC5_BUSY_MASK 0x20
+#define SRBM_STATUS3__MCC5_BUSY__SHIFT 0x5
+#define SRBM_STATUS3__MCC6_BUSY_MASK 0x40
+#define SRBM_STATUS3__MCC6_BUSY__SHIFT 0x6
+#define SRBM_STATUS3__MCC7_BUSY_MASK 0x80
+#define SRBM_STATUS3__MCC7_BUSY__SHIFT 0x7
+#define SRBM_STATUS3__MCD0_BUSY_MASK 0x100
+#define SRBM_STATUS3__MCD0_BUSY__SHIFT 0x8
+#define SRBM_STATUS3__MCD1_BUSY_MASK 0x200
+#define SRBM_STATUS3__MCD1_BUSY__SHIFT 0x9
+#define SRBM_STATUS3__MCD2_BUSY_MASK 0x400
+#define SRBM_STATUS3__MCD2_BUSY__SHIFT 0xa
+#define SRBM_STATUS3__MCD3_BUSY_MASK 0x800
+#define SRBM_STATUS3__MCD3_BUSY__SHIFT 0xb
+#define SRBM_STATUS3__MCD4_BUSY_MASK 0x1000
+#define SRBM_STATUS3__MCD4_BUSY__SHIFT 0xc
+#define SRBM_STATUS3__MCD5_BUSY_MASK 0x2000
+#define SRBM_STATUS3__MCD5_BUSY__SHIFT 0xd
+#define SRBM_STATUS3__MCD6_BUSY_MASK 0x4000
+#define SRBM_STATUS3__MCD6_BUSY__SHIFT 0xe
+#define SRBM_STATUS3__MCD7_BUSY_MASK 0x8000
+#define SRBM_STATUS3__MCD7_BUSY__SHIFT 0xf
+#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2_MASK 0x1
+#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2__SHIFT 0x0
+#define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x2
+#define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x1
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3_MASK 0x4
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3__SHIFT 0x2
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2_MASK 0x8
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2__SHIFT 0x3
+#define SRBM_SOFT_RESET__SOFT_RESET_GIONB_MASK 0x10
+#define SRBM_SOFT_RESET__SOFT_RESET_GIONB__SHIFT 0x4
+#define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x20
+#define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x5
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x40
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x6
+#define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x100
+#define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x8
+#define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x200
+#define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x9
+#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400
+#define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa
+#define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x800
+#define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0xb
+#define SRBM_SOFT_RESET__SOFT_RESET_CHUB_MASK 0x1000
+#define SRBM_SOFT_RESET__SOFT_RESET_CHUB__SHIFT 0xc
+#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM_MASK 0x2000
+#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM__SHIFT 0xd
+#define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x4000
+#define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0xe
+#define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x8000
+#define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0xf
+#define SRBM_SOFT_RESET__SOFT_RESET_SMU_MASK 0x10000
+#define SRBM_SOFT_RESET__SOFT_RESET_SMU__SHIFT 0x10
+#define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x20000
+#define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x11
+#define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x40000
+#define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x12
+#define SRBM_SOFT_RESET__SOFT_RESET_VP8_MASK 0x80000
+#define SRBM_SOFT_RESET__SOFT_RESET_VP8__SHIFT 0x13
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK 0x100000
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA__SHIFT 0x14
+#define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x200000
+#define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x15
+#define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x400000
+#define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x16
+#define SRBM_SOFT_RESET__SOFT_RESET_ODE_MASK 0x800000
+#define SRBM_SOFT_RESET__SOFT_RESET_ODE__SHIFT 0x17
+#define SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK 0x1000000
+#define SRBM_SOFT_RESET__SOFT_RESET_VCE0__SHIFT 0x18
+#define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x2000000
+#define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x19
+#define SRBM_SOFT_RESET__SOFT_RESET_ACP_MASK 0x4000000
+#define SRBM_SOFT_RESET__SOFT_RESET_ACP__SHIFT 0x1a
+#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP_MASK 0x8000000
+#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP__SHIFT 0x1b
+#define SRBM_SOFT_RESET__SOFT_RESET_GRN_MASK 0x20000000
+#define SRBM_SOFT_RESET__SOFT_RESET_GRN__SHIFT 0x1d
+#define SRBM_SOFT_RESET__SOFT_RESET_ISP_MASK 0x40000000
+#define SRBM_SOFT_RESET__SOFT_RESET_ISP__SHIFT 0x1e
+#define SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK 0x80000000
+#define SRBM_SOFT_RESET__SOFT_RESET_VCE1__SHIFT 0x1f
+#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x3f
+#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x0
+#define SRBM_DEBUG_DATA__DATA_MASK 0xffffffff
+#define SRBM_DEBUG_DATA__DATA__SHIFT 0x0
+#define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0xff
+#define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0
+#define CC_SYS_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
+#define CC_SYS_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
+#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
+#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
+#define CC_SYS_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
+#define CC_SYS_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
+#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
+#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
+#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
+#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
+#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
+#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
+#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_VP8_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_VP8_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_VP8_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_VP8_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_DEBUG__IGNORE_RDY_MASK 0x1
+#define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x0
+#define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x2
+#define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x1
+#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x4
+#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x2
+#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x10
+#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x4
+#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x20
+#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x5
+#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x40
+#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x6
+#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE_MASK 0x80
+#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x7
+#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x100
+#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x8
+#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE_MASK 0x200
+#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x9
+#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE_MASK 0x400
+#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xa
+#define SRBM_DEBUG__VP8_CLOCK_DOMAIN_OVERRIDE_MASK 0x800
+#define SRBM_DEBUG__VP8_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xb
+#define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x1
+#define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x0
+#define SRBM_DEBUG_SNAPSHOT__GIONB_RDY_MASK 0x2
+#define SRBM_DEBUG_SNAPSHOT__GIONB_RDY__SHIFT 0x1
+#define SRBM_DEBUG_SNAPSHOT__SMU_RDY_MASK 0x4
+#define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT 0x2
+#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY_MASK 0x8
+#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY__SHIFT 0x3
+#define SRBM_DEBUG_SNAPSHOT__ACP_RDY_MASK 0x10
+#define SRBM_DEBUG_SNAPSHOT__ACP_RDY__SHIFT 0x4
+#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x20
+#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x5
+#define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x40
+#define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x6
+#define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x80
+#define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x7
+#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x100
+#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x8
+#define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x200
+#define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x9
+#define SRBM_DEBUG_SNAPSHOT__VP8_RDY_MASK 0x400
+#define SRBM_DEBUG_SNAPSHOT__VP8_RDY__SHIFT 0xa
+#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x800
+#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0xb
+#define SRBM_DEBUG_SNAPSHOT__ODE_RDY_MASK 0x1000
+#define SRBM_DEBUG_SNAPSHOT__ODE_RDY__SHIFT 0xc
+#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x2000
+#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0xd
+#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x4000
+#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0xe
+#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x8000
+#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0xf
+#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x10000
+#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x10
+#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x20000
+#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x11
+#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x40000
+#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x12
+#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x80000
+#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x13
+#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x100000
+#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x14
+#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x200000
+#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x15
+#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x400000
+#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x16
+#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x800000
+#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x17
+#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x1000000
+#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x18
+#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x2000000
+#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x19
+#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x4000000
+#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x1a
+#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x8000000
+#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x1b
+#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000
+#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x1c
+#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY_MASK 0x20000000
+#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY__SHIFT 0x1d
+#define SRBM_DEBUG_SNAPSHOT__RESERVED_MASK 0x40000000
+#define SRBM_DEBUG_SNAPSHOT__RESERVED__SHIFT 0x1e
+#define SRBM_DEBUG_SNAPSHOT__ISP_RDY_MASK 0x80000000
+#define SRBM_DEBUG_SNAPSHOT__ISP_RDY__SHIFT 0x1f
+#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY_MASK 0x1
+#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY__SHIFT 0x0
+#define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc
+#define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3_MASK 0x40000
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3__SHIFT 0x12
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2_MASK 0x80000
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2__SHIFT 0x13
+#define SRBM_READ_ERROR__READ_REQUESTER_VCE0_MASK 0x100000
+#define SRBM_READ_ERROR__READ_REQUESTER_VCE0__SHIFT 0x14
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1_MASK 0x200000
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1__SHIFT 0x15
+#define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x400000
+#define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x16
+#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP_MASK 0x800000
+#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP__SHIFT 0x17
+#define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x1000000
+#define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x18
+#define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x2000000
+#define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x19
+#define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x4000000
+#define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x1a
+#define SRBM_READ_ERROR__READ_REQUESTER_VP8_MASK 0x8000000
+#define SRBM_READ_ERROR__READ_REQUESTER_VP8__SHIFT 0x1b
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA_MASK 0x10000000
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA__SHIFT 0x1c
+#define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000
+#define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x1d
+#define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000
+#define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
+#define SRBM_READ_ERROR2__READ_REQUESTER_ACP_MASK 0x1
+#define SRBM_READ_ERROR2__READ_REQUESTER_ACP__SHIFT 0x0
+#define SRBM_READ_ERROR2__READ_REQUESTER_ISP_MASK 0x2
+#define SRBM_READ_ERROR2__READ_REQUESTER_ISP__SHIFT 0x1
+#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1_MASK 0x4
+#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1__SHIFT 0x2
+#define SRBM_READ_ERROR2__READ_VF_MASK 0x800000
+#define SRBM_READ_ERROR2__READ_VF__SHIFT 0x17
+#define SRBM_READ_ERROR2__READ_VFID_MASK 0xf000000
+#define SRBM_READ_ERROR2__READ_VFID__SHIFT 0x18
+#define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x1
+#define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x0
+#define SRBM_INT_CNTL__RAERR_INT_MASK_MASK 0x2
+#define SRBM_INT_CNTL__RAERR_INT_MASK__SHIFT 0x1
+#define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x1
+#define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x0
+#define SRBM_INT_STATUS__RAERR_INT_STAT_MASK 0x2
+#define SRBM_INT_STATUS__RAERR_INT_STAT__SHIFT 0x1
+#define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x1
+#define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x0
+#define SRBM_INT_ACK__RAERR_INT_ACK_MASK 0x2
+#define SRBM_INT_ACK__RAERR_INT_ACK__SHIFT 0x1
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF_MASK 0x1
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF__SHIFT 0x0
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP_MASK 0x2
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP__SHIFT 0x1
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VP8_MASK 0x4
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VP8__SHIFT 0x2
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP_MASK 0x8
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP__SHIFT 0x3
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST_MASK 0x20
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST__SHIFT 0x5
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3_MASK 0x40
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3__SHIFT 0x6
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2_MASK 0x80
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2__SHIFT 0x7
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1_MASK 0x100
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1__SHIFT 0x8
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0_MASK 0x200
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0__SHIFT 0x9
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD_MASK 0x400
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD__SHIFT 0xa
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0_MASK 0x800
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0__SHIFT 0xb
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM_MASK 0x1000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM__SHIFT 0xc
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU_MASK 0x2000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU__SHIFT 0xd
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER_MASK 0x4000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER__SHIFT 0xe
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU_MASK 0x8000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU__SHIFT 0xf
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP_MASK 0x10000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP__SHIFT 0x10
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1_MASK 0x20000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1__SHIFT 0x11
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP_MASK 0x40000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP__SHIFT 0x12
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP_MASK 0x80000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP__SHIFT 0x13
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP_MASK 0x100000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP__SHIFT 0x14
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION_MASK 0x1000000
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION__SHIFT 0x18
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW_MASK 0x2000000
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW__SHIFT 0x19
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW_MASK 0x4000000
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW__SHIFT 0x1a
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW_MASK 0x8000000
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW__SHIFT 0x1b
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION_MASK 0x10000000
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION__SHIFT 0x1c
+#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS_MASK 0x3fffc
+#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS__SHIFT 0x2
+#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF_MASK 0x80000
+#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF__SHIFT 0x13
+#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID_MASK 0xf00000
+#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID__SHIFT 0x14
+#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION_MASK 0x80000000
+#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION__SHIFT 0x1f
+#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR_MASK 0xffff
+#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR__SHIFT 0x0
+#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP_MASK 0x10000
+#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP__SHIFT 0x10
+#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD_MASK 0xffffffff
+#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD__SHIFT 0x0
+#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK_MASK 0xffff
+#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK__SHIFT 0x0
+#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK_MASK 0x10000
+#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK__SHIFT 0x10
+#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK_MASK 0xffffffff
+#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK__SHIFT 0x0
+#define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0xf
+#define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300
+#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
+#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
+#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
+#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
+#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
+#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffff
+#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x0
+#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffff
+#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x0
+#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffff
+#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x0
+#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffff
+#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x0
+#define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x3
+#define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
+#define SRBM_CAM_DATA__CAM_ADDR_MASK 0xffff
+#define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
+#define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
+#define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
+#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
+#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
+#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
+#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
+#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
+#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
+#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
+#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
+#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
+#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
+#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
+#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
+#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff
+#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0
+#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000
+#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10
+#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff
+#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0
+#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000
+#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10
+#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff
+#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0
+#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000
+#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10
+#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff
+#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0
+#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000
+#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10
+#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
+#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
+#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
+#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
+#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
+#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
+#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
+#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
+#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
+#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
+#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
+#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
+#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff
+#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0
+#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000
+#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10
+#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff
+#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0
+#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000
+#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10
+#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff
+#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0
+#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000
+#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10
+#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff
+#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0
+#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000
+#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10
+#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
+#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
+#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
+#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
+#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
+#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
+#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
+#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
+#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
+#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
+#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
+#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
+#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff
+#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0
+#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000
+#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10
+#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
+#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
+#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
+#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
+#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
+#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
+#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
+#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
+#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
+#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
+#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
+#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
+#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
+#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
+#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
+#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
+#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
+#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
+#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
+#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
+#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
+#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
+#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
+#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
+#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
+#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
+#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
+#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
+#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
+#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
+#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
+#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
+#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
+#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
+#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
+#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
+#define SRBM_VP8_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
+#define SRBM_VP8_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
+#define SRBM_VP8_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
+#define SRBM_VP8_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
+#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL_MASK 0xf
+#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL__SHIFT 0x0
+#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX_MASK 0xff
+#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX__SHIFT 0x0
+#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX_MASK 0xff00
+#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX__SHIFT 0x8
+#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX_MASK 0xff0000
+#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT 0x10
+#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK 0x20000000
+#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d
+#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000
+#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
+#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES_MASK 0x80000000
+#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f
+#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL_MASK 0xf
+#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL__SHIFT 0x0
+#define SRBM_GFX_CNTL_DATA__PIPEID_MASK 0x3
+#define SRBM_GFX_CNTL_DATA__PIPEID__SHIFT 0x0
+#define SRBM_GFX_CNTL_DATA__MEID_MASK 0xc
+#define SRBM_GFX_CNTL_DATA__MEID__SHIFT 0x2
+#define SRBM_GFX_CNTL_DATA__VMID_MASK 0xf0
+#define SRBM_GFX_CNTL_DATA__VMID__SHIFT 0x4
+#define SRBM_GFX_CNTL_DATA__QUEUEID_MASK 0x700
+#define SRBM_GFX_CNTL_DATA__QUEUEID__SHIFT 0x8
+#define SRBM_VF_ENABLE__VF_ENABLE_MASK 0x1
+#define SRBM_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE_MASK 0x1
+#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE__SHIFT 0x0
+#define SRBM_VIRT_RESET_REQ__VF_MASK 0xffff
+#define SRBM_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define SRBM_VIRT_RESET_REQ__PF_MASK 0x80000000
+#define SRBM_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define SDMA0_UCODE_ADDR__VALUE_MASK 0x1fff
+#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0
+#define SDMA0_UCODE_DATA__VALUE_MASK 0xffffffff
+#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0
+#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100
+#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
+#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x200
+#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
+#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x400
+#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
+#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x800
+#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
+#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x3ff000
+#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
+#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0xf
+#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x1
+#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0
+#define SDMA0_CNTL__ATC_L1_ENABLE_MASK 0x2
+#define SDMA0_CNTL__ATC_L1_ENABLE__SHIFT 0x1
+#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4
+#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
+#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x8
+#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
+#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x10
+#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x20
+#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
+#define SDMA0_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800
+#define SDMA0_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb
+#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x20000
+#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
+#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000
+#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
+#define SDMA0_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000
+#define SDMA0_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16
+#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000
+#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
+#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000
+#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
+#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000
+#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
+#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
+#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
+#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2
+#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
+#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4
+#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
+#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000
+#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
+#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000
+#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
+#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000
+#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
+#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000
+#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
+#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000
+#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
+#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000
+#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
+#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define SDMA0_HASH__CHANNEL_BITS_MASK 0x7
+#define SDMA0_HASH__CHANNEL_BITS__SHIFT 0x0
+#define SDMA0_HASH__BANK_BITS_MASK 0x70
+#define SDMA0_HASH__BANK_BITS__SHIFT 0x4
+#define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK 0x700
+#define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
+#define SDMA0_HASH__BANK_XOR_COUNT_MASK 0x7000
+#define SDMA0_HASH__BANK_XOR_COUNT__SHIFT 0xc
+#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff
+#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
+#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc
+#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
+#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc
+#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
+#define SDMA0_PROGRAM__STREAM_MASK 0xffffffff
+#define SDMA0_PROGRAM__STREAM__SHIFT 0x0
+#define SDMA0_STATUS_REG__IDLE_MASK 0x1
+#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0
+#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x2
+#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
+#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x4
+#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2
+#define SDMA0_STATUS_REG__RB_FULL_MASK 0x8
+#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3
+#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x10
+#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
+#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x20
+#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
+#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x40
+#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
+#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x80
+#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
+#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x100
+#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
+#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x200
+#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9
+#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x400
+#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
+#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
+#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
+#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x1000
+#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc
+#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x2000
+#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
+#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x4000
+#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe
+#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000
+#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
+#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000
+#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
+#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000
+#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
+#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000
+#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
+#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x80000
+#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
+#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000
+#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
+#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000
+#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
+#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000
+#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
+#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000
+#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
+#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x4000000
+#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a
+#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000
+#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
+#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000
+#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
+#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000
+#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e
+#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000
+#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
+#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
+#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
+#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x2
+#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
+#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4
+#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
+#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8
+#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
+#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x10
+#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
+#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x20
+#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
+#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x40
+#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
+#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x200
+#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
+#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400
+#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
+#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x2000
+#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
+#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000
+#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
+#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x20000
+#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
+#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x40000
+#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
+#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x3
+#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
+#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x3fc
+#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x400
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x800
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb
+#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0xff000
+#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc
+#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
+#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
+#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA0_F32_CNTL__HALT_MASK 0x1
+#define SDMA0_F32_CNTL__HALT__SHIFT 0x0
+#define SDMA0_F32_CNTL__STEP_MASK 0x2
+#define SDMA0_F32_CNTL__STEP__SHIFT 0x1
+#define SDMA0_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc
+#define SDMA0_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2
+#define SDMA0_FREEZE__FREEZE_MASK 0x10
+#define SDMA0_FREEZE__FREEZE__SHIFT 0x4
+#define SDMA0_FREEZE__FROZEN_MASK 0x20
+#define SDMA0_FREEZE__FROZEN__SHIFT 0x5
+#define SDMA0_FREEZE__F32_FREEZE_MASK 0x40
+#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6
+#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0xf
+#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00
+#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000
+#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0xf
+#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00
+#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000
+#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA_POWER_GATING__PG_CNTL_ENABLE_MASK 0x1
+#define SDMA_POWER_GATING__PG_CNTL_ENABLE__SHIFT 0x0
+#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK 0x2
+#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE__SHIFT 0x1
+#define SDMA_POWER_GATING__PG_STATE_VALID_MASK 0x4
+#define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT 0x2
+#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x30
+#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4
+#define SDMA_POWER_GATING__SDMA0_ON_CONDITION_MASK 0x40
+#define SDMA_POWER_GATING__SDMA0_ON_CONDITION__SHIFT 0x6
+#define SDMA_POWER_GATING__SDMA1_ON_CONDITION_MASK 0x80
+#define SDMA_POWER_GATING__SDMA1_ON_CONDITION__SHIFT 0x7
+#define SDMA_POWER_GATING__POWER_OFF_DELAY_MASK 0xfff00
+#define SDMA_POWER_GATING__POWER_OFF_DELAY__SHIFT 0x8
+#define SDMA_POWER_GATING__POWER_ON_DELAY_MASK 0xfff00000
+#define SDMA_POWER_GATING__POWER_ON_DELAY__SHIFT 0x14
+#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0xff
+#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
+#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x100
+#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
+#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x200
+#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
+#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x400
+#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
+#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x800
+#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
+#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x1000
+#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc
+#define SDMA_PGFSM_CONFIG__READ_MASK 0x2000
+#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd
+#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000
+#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
+#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000
+#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
+#define SDMA_PGFSM_WRITE__VALUE_MASK 0xffffffff
+#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0
+#define SDMA_PGFSM_READ__VALUE_MASK 0xffffff
+#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0
+#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x2
+#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4
+#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
+#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x3ff
+#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0
+#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000
+#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
+#define SDMA0_ID__DEVICE_ID_MASK 0xff
+#define SDMA0_ID__DEVICE_ID__SHIFT 0x0
+#define SDMA0_VERSION__VALUE_MASK 0xffff
+#define SDMA0_VERSION__VALUE__SHIFT 0x0
+#define SDMA0_VM_CNTL__CMD_MASK 0xf
+#define SDMA0_VM_CNTL__CMD__SHIFT 0x0
+#define SDMA0_VM_CTX_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2
+#define SDMA0_VM_CTX_HI__ADDR_MASK 0xffffffff
+#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0
+#define SDMA0_STATUS2_REG__ID_MASK 0x3
+#define SDMA0_STATUS2_REG__ID__SHIFT 0x0
+#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0xfffc
+#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
+#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xffff0000
+#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10
+#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0xf
+#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000
+#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x1
+#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0
+#define SDMA0_VM_CTX_CNTL__VMID_MASK 0xf0
+#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4
+#define SDMA0_VIRT_RESET_REQ__VF_MASK 0xffff
+#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000
+#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x1
+#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7fffffff
+#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
+#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000
+#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
+#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xffffffff
+#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
+#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xffffffff
+#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
+#define SDMA0_ATCL1_CNTL__REDO_ENABLE_MASK 0x1
+#define SDMA0_ATCL1_CNTL__REDO_ENABLE__SHIFT 0x0
+#define SDMA0_ATCL1_CNTL__REDO_DELAY_MASK 0x7fe
+#define SDMA0_ATCL1_CNTL__REDO_DELAY__SHIFT 0x1
+#define SDMA0_ATCL1_CNTL__REDO_WATERMK_MASK 0x3800
+#define SDMA0_ATCL1_CNTL__REDO_WATERMK__SHIFT 0xb
+#define SDMA0_ATCL1_CNTL__INVACK_DELAY_MASK 0xffc000
+#define SDMA0_ATCL1_CNTL__INVACK_DELAY__SHIFT 0xe
+#define SDMA0_ATCL1_CNTL__REQL2_CREDIT_MASK 0xf000000
+#define SDMA0_ATCL1_CNTL__REQL2_CREDIT__SHIFT 0x18
+#define SDMA0_ATCL1_CNTL__VADDR_WATERMK_MASK 0x70000000
+#define SDMA0_ATCL1_CNTL__VADDR_WATERMK__SHIFT 0x1c
+#define SDMA0_ATCL1_WATERMK__REQMC_WATERMK_MASK 0x3ff
+#define SDMA0_ATCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0
+#define SDMA0_ATCL1_WATERMK__REQPG_WATERMK_MASK 0x3fc00
+#define SDMA0_ATCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa
+#define SDMA0_ATCL1_WATERMK__INVREQ_WATERMK_MASK 0xfc0000
+#define SDMA0_ATCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12
+#define SDMA0_ATCL1_WATERMK__XNACK_WATERMK_MASK 0x7f000000
+#define SDMA0_ATCL1_WATERMK__XNACK_WATERMK__SHIFT 0x18
+#define SDMA0_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x1
+#define SDMA0_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA0_ATCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x2
+#define SDMA0_ATCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
+#define SDMA0_ATCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x4
+#define SDMA0_ATCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
+#define SDMA0_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x8
+#define SDMA0_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
+#define SDMA0_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x10
+#define SDMA0_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
+#define SDMA0_ATCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x20
+#define SDMA0_ATCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
+#define SDMA0_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x40
+#define SDMA0_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
+#define SDMA0_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x80
+#define SDMA0_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
+#define SDMA0_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x100
+#define SDMA0_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
+#define SDMA0_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x200
+#define SDMA0_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
+#define SDMA0_ATCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x400
+#define SDMA0_ATCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
+#define SDMA0_ATCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x800
+#define SDMA0_ATCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
+#define SDMA0_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x1000
+#define SDMA0_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
+#define SDMA0_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x2000
+#define SDMA0_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
+#define SDMA0_ATCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x4000
+#define SDMA0_ATCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
+#define SDMA0_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x8000
+#define SDMA0_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
+#define SDMA0_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x10000
+#define SDMA0_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
+#define SDMA0_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x20000
+#define SDMA0_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
+#define SDMA0_ATCL1_RD_STATUS__ALL_IDLE_MASK 0x40000
+#define SDMA0_ATCL1_RD_STATUS__ALL_IDLE__SHIFT 0x12
+#define SDMA0_ATCL1_RD_STATUS__REQL2_IDLE_MASK 0x80000
+#define SDMA0_ATCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x13
+#define SDMA0_ATCL1_RD_STATUS__REQMC_IDLE_MASK 0x100000
+#define SDMA0_ATCL1_RD_STATUS__REQMC_IDLE__SHIFT 0x14
+#define SDMA0_ATCL1_RD_STATUS__CE_L1_STALL_MASK 0x200000
+#define SDMA0_ATCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15
+#define SDMA0_ATCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x3c00000
+#define SDMA0_ATCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16
+#define SDMA0_ATCL1_RD_STATUS__MERGE_STATE_MASK 0x1c000000
+#define SDMA0_ATCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a
+#define SDMA0_ATCL1_RD_STATUS__RESERVED_MASK 0xe0000000
+#define SDMA0_ATCL1_RD_STATUS__RESERVED__SHIFT 0x1d
+#define SDMA0_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x1
+#define SDMA0_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA0_ATCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x2
+#define SDMA0_ATCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
+#define SDMA0_ATCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x4
+#define SDMA0_ATCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
+#define SDMA0_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x8
+#define SDMA0_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
+#define SDMA0_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x10
+#define SDMA0_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
+#define SDMA0_ATCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x20
+#define SDMA0_ATCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
+#define SDMA0_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x40
+#define SDMA0_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
+#define SDMA0_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x80
+#define SDMA0_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
+#define SDMA0_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x100
+#define SDMA0_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
+#define SDMA0_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x200
+#define SDMA0_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
+#define SDMA0_ATCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x400
+#define SDMA0_ATCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
+#define SDMA0_ATCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x800
+#define SDMA0_ATCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
+#define SDMA0_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x1000
+#define SDMA0_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
+#define SDMA0_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x2000
+#define SDMA0_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
+#define SDMA0_ATCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x4000
+#define SDMA0_ATCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
+#define SDMA0_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x8000
+#define SDMA0_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
+#define SDMA0_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x10000
+#define SDMA0_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
+#define SDMA0_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x20000
+#define SDMA0_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
+#define SDMA0_ATCL1_WR_STATUS__ALL_IDLE_MASK 0x40000
+#define SDMA0_ATCL1_WR_STATUS__ALL_IDLE__SHIFT 0x12
+#define SDMA0_ATCL1_WR_STATUS__REQL2_IDLE_MASK 0x80000
+#define SDMA0_ATCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x13
+#define SDMA0_ATCL1_WR_STATUS__REQMC_IDLE_MASK 0x100000
+#define SDMA0_ATCL1_WR_STATUS__REQMC_IDLE__SHIFT 0x14
+#define SDMA0_ATCL1_WR_STATUS__F32_WR_RTR_MASK 0x200000
+#define SDMA0_ATCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15
+#define SDMA0_ATCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x3c00000
+#define SDMA0_ATCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16
+#define SDMA0_ATCL1_WR_STATUS__MERGE_STATE_MASK 0x1c000000
+#define SDMA0_ATCL1_WR_STATUS__MERGE_STATE__SHIFT 0x1a
+#define SDMA0_ATCL1_WR_STATUS__RESERVED_MASK 0xe0000000
+#define SDMA0_ATCL1_WR_STATUS__RESERVED__SHIFT 0x1d
+#define SDMA0_ATCL1_INV0__INV_MIDDLE_MASK 0x1
+#define SDMA0_ATCL1_INV0__INV_MIDDLE__SHIFT 0x0
+#define SDMA0_ATCL1_INV0__RD_TIMEOUT_MASK 0x2
+#define SDMA0_ATCL1_INV0__RD_TIMEOUT__SHIFT 0x1
+#define SDMA0_ATCL1_INV0__WR_TIMEOUT_MASK 0x4
+#define SDMA0_ATCL1_INV0__WR_TIMEOUT__SHIFT 0x2
+#define SDMA0_ATCL1_INV0__RD_IN_INVADR_MASK 0x8
+#define SDMA0_ATCL1_INV0__RD_IN_INVADR__SHIFT 0x3
+#define SDMA0_ATCL1_INV0__WR_IN_INVADR_MASK 0x10
+#define SDMA0_ATCL1_INV0__WR_IN_INVADR__SHIFT 0x4
+#define SDMA0_ATCL1_INV0__RD_WT_INVADR_MASK 0x20
+#define SDMA0_ATCL1_INV0__RD_WT_INVADR__SHIFT 0x5
+#define SDMA0_ATCL1_INV0__WR_WT_INVADR_MASK 0x40
+#define SDMA0_ATCL1_INV0__WR_WT_INVADR__SHIFT 0x6
+#define SDMA0_ATCL1_INV0__RD_INV_EN_MASK 0x80
+#define SDMA0_ATCL1_INV0__RD_INV_EN__SHIFT 0x7
+#define SDMA0_ATCL1_INV0__WR_INV_EN_MASK 0x100
+#define SDMA0_ATCL1_INV0__WR_INV_EN__SHIFT 0x8
+#define SDMA0_ATCL1_INV0__RD_INV_IDLE_MASK 0x200
+#define SDMA0_ATCL1_INV0__RD_INV_IDLE__SHIFT 0x9
+#define SDMA0_ATCL1_INV0__WR_INV_IDLE_MASK 0x400
+#define SDMA0_ATCL1_INV0__WR_INV_IDLE__SHIFT 0xa
+#define SDMA0_ATCL1_INV0__INV_FLUSHTYPE_MASK 0x800
+#define SDMA0_ATCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb
+#define SDMA0_ATCL1_INV0__INV_VMID_VEC_MASK 0xffff000
+#define SDMA0_ATCL1_INV0__INV_VMID_VEC__SHIFT 0xc
+#define SDMA0_ATCL1_INV0__INV_ADDR_HI_MASK 0xf0000000
+#define SDMA0_ATCL1_INV0__INV_ADDR_HI__SHIFT 0x1c
+#define SDMA0_ATCL1_INV1__INV_ADDR_LO_MASK 0xffffffff
+#define SDMA0_ATCL1_INV1__INV_ADDR_LO__SHIFT 0x0
+#define SDMA0_ATCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xffff
+#define SDMA0_ATCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0
+#define SDMA0_ATCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xffffffff
+#define SDMA0_ATCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA0_ATCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0xf
+#define SDMA0_ATCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA0_ATCL1_RD_XNACK1__XNACK_VMID_MASK 0xf0
+#define SDMA0_ATCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA0_ATCL1_RD_XNACK1__IS_XNACK_MASK 0x100
+#define SDMA0_ATCL1_RD_XNACK1__IS_XNACK__SHIFT 0x8
+#define SDMA0_ATCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xffffffff
+#define SDMA0_ATCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA0_ATCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0xf
+#define SDMA0_ATCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA0_ATCL1_WR_XNACK1__XNACK_VMID_MASK 0xf0
+#define SDMA0_ATCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA0_ATCL1_WR_XNACK1__IS_XNACK_MASK 0x100
+#define SDMA0_ATCL1_WR_XNACK1__IS_XNACK__SHIFT 0x8
+#define SDMA0_ATCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0xffff
+#define SDMA0_ATCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0
+#define SDMA0_ATCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xffff0000
+#define SDMA0_ATCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10
+#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0xffff
+#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0
+#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0xff0000
+#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10
+#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xff000000
+#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18
+#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL_MASK 0x1
+#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL__SHIFT 0x0
+#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT_MASK 0x2
+#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x1
+#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT_MASK 0x4
+#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x2
+#define SDMA0_PERF_REG_TYPE0__RESERVED_31_3_MASK 0xfffffff8
+#define SDMA0_PERF_REG_TYPE0__RESERVED_31_3__SHIFT 0x3
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x1
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x2
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x4
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x8
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x10
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x4
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x20
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x5
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x40
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x6
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x80
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x7
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x100
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x200
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x400
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x800
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x1000
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x2000
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x4000
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x8000
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x10000
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x20000
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x40000
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x80000
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_VIRTUAL_ADDR_MASK 0x80
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_VIRTUAL_ADDR__SHIFT 0x7
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_APE1_CNTL_MASK 0x100
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_APE1_CNTL__SHIFT 0x8
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x200
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x400
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa
+#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG1_MASK 0x800
+#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG1__SHIFT 0xb
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x1000
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x2000
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd
+#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x4000
+#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x8000
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x10000
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x20000
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11
+#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xfffc0000
+#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x12
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x1
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x2
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x4
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x8
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x10
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x20
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x40
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x80
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x100
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x200
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9
+#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xfffffc00
+#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x1
+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0
+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x2
+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1
+#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x4
+#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x2
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x8
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x3
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x4
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x5
+#define SDMA0_PUB_REG_TYPE0__SDMA0_TILING_CONFIG_MASK 0x40
+#define SDMA0_PUB_REG_TYPE0__SDMA0_TILING_CONFIG__SHIFT 0x6
+#define SDMA0_PUB_REG_TYPE0__SDMA0_HASH_MASK 0x80
+#define SDMA0_PUB_REG_TYPE0__SDMA0_HASH__SHIFT 0x7
+#define SDMA0_PUB_REG_TYPE0__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x200
+#define SDMA0_PUB_REG_TYPE0__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x9
+#define SDMA0_PUB_REG_TYPE0__SDMA0_RB_RPTR_FETCH_MASK 0x400
+#define SDMA0_PUB_REG_TYPE0__SDMA0_RB_RPTR_FETCH__SHIFT 0xa
+#define SDMA0_PUB_REG_TYPE0__SDMA0_IB_OFFSET_FETCH_MASK 0x800
+#define SDMA0_PUB_REG_TYPE0__SDMA0_IB_OFFSET_FETCH__SHIFT 0xb
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PROGRAM_MASK 0x1000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PROGRAM__SHIFT 0xc
+#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS_REG_MASK 0x2000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS_REG__SHIFT 0xd
+#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS1_REG_MASK 0x4000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS1_REG__SHIFT 0xe
+#define SDMA0_PUB_REG_TYPE0__SDMA0_RD_BURST_CNTL_MASK 0x8000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_RD_BURST_CNTL__SHIFT 0xf
+#define SDMA0_PUB_REG_TYPE0__RESERVED_16_MASK 0x10000
+#define SDMA0_PUB_REG_TYPE0__RESERVED_16__SHIFT 0x10
+#define SDMA0_PUB_REG_TYPE0__RESERVED_17_MASK 0x20000
+#define SDMA0_PUB_REG_TYPE0__RESERVED_17__SHIFT 0x11
+#define SDMA0_PUB_REG_TYPE0__SDMA0_F32_CNTL_MASK 0x40000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_F32_CNTL__SHIFT 0x12
+#define SDMA0_PUB_REG_TYPE0__SDMA0_FREEZE_MASK 0x80000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_FREEZE__SHIFT 0x13
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE0_QUANTUM_MASK 0x100000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE0_QUANTUM__SHIFT 0x14
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE1_QUANTUM_MASK 0x200000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE1_QUANTUM__SHIFT 0x15
+#define SDMA0_PUB_REG_TYPE0__SDMA_POWER_GATING_MASK 0x400000
+#define SDMA0_PUB_REG_TYPE0__SDMA_POWER_GATING__SHIFT 0x16
+#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_CONFIG_MASK 0x800000
+#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_CONFIG__SHIFT 0x17
+#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_WRITE_MASK 0x1000000
+#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_WRITE__SHIFT 0x18
+#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_READ_MASK 0x2000000
+#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_READ__SHIFT 0x19
+#define SDMA0_PUB_REG_TYPE0__SDMA0_EDC_CONFIG_MASK 0x4000000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_EDC_CONFIG__SHIFT 0x1a
+#define SDMA0_PUB_REG_TYPE0__SDMA0_BA_THRESHOLD_MASK 0x8000000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_BA_THRESHOLD__SHIFT 0x1b
+#define SDMA0_PUB_REG_TYPE0__SDMA0_DEVICE_ID_MASK 0x10000000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_DEVICE_ID__SHIFT 0x1c
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VERSION_MASK 0x20000000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VERSION__SHIFT 0x1d
+#define SDMA0_PUB_REG_TYPE0__RESERVED_MASK 0xc0000000
+#define SDMA0_PUB_REG_TYPE0__RESERVED__SHIFT 0x1e
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL_MASK 0x1
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL__SHIFT 0x0
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO_MASK 0x2
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO__SHIFT 0x1
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI_MASK 0x4
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI__SHIFT 0x2
+#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x8
+#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x3
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ACTIVE_FCN_ID_MASK 0x10
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ACTIVE_FCN_ID__SHIFT 0x4
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_CNTL_MASK 0x20
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_CNTL__SHIFT 0x5
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VIRT_RESET_REQ_MASK 0x40
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VIRT_RESET_REQ__SHIFT 0x6
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VF_ENABLE_MASK 0x80
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VF_ENABLE__SHIFT 0x7
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x100
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x8
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x200
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x9
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x400
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0xa
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_CNTL_MASK 0x800
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_CNTL__SHIFT 0xb
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_WATERMK_MASK 0x1000
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_WATERMK__SHIFT 0xc
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_TIMEOUT_MASK 0x2000
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATCL1_TIMEOUT__SHIFT 0xd
+#define SDMA0_PUB_REG_TYPE1__RESERVED_MASK 0xffffc000
+#define SDMA0_PUB_REG_TYPE1__RESERVED__SHIFT 0xe
+#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_GFX_DOORBELL__OFFSET_MASK 0x1fffff
+#define SDMA0_GFX_DOORBELL__OFFSET__SHIFT 0x0
+#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000
+#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000
+#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000
+#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
+#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000
+#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
+#define SDMA0_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA0_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA0_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2
+#define SDMA0_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1
+#define SDMA0_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA0_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA0_GFX_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA0_GFX_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA0_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA0_GFX_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1
+#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xfffffffc
+#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff
+#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x1
+#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff
+#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xffffffff
+#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xffffffff
+#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xffffffff
+#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xffffffff
+#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xffffffff
+#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xffffffff
+#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xffffffff
+#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xffffffff
+#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xffffffff
+#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1
+#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2
+#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
+#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
+#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC0_DOORBELL__OFFSET_MASK 0x1fffff
+#define SDMA0_RLC0_DOORBELL__OFFSET__SHIFT 0x0
+#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000
+#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000
+#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA0_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2
+#define SDMA0_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1
+#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA0_RLC0_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA0_RLC0_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA0_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
+#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc
+#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff
+#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1
+#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff
+#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xffffffff
+#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xffffffff
+#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xffffffff
+#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xffffffff
+#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xffffffff
+#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xffffffff
+#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xffffffff
+#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xffffffff
+#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xffffffff
+#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1
+#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2
+#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
+#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
+#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC1_DOORBELL__OFFSET_MASK 0x1fffff
+#define SDMA0_RLC1_DOORBELL__OFFSET__SHIFT 0x0
+#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000
+#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000
+#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA0_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA0_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2
+#define SDMA0_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1
+#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA0_RLC1_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA0_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
+#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc
+#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff
+#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1
+#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff
+#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xffffffff
+#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xffffffff
+#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xffffffff
+#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xffffffff
+#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xffffffff
+#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xffffffff
+#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xffffffff
+#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xffffffff
+#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xffffffff
+#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1
+#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2
+#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
+#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
+#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_UCODE_ADDR__VALUE_MASK 0x1fff
+#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0
+#define SDMA1_UCODE_DATA__VALUE_MASK 0xffffffff
+#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0
+#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100
+#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
+#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x200
+#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
+#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x400
+#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
+#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x800
+#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
+#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x3ff000
+#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
+#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0xf
+#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x1
+#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0
+#define SDMA1_CNTL__ATC_L1_ENABLE_MASK 0x2
+#define SDMA1_CNTL__ATC_L1_ENABLE__SHIFT 0x1
+#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4
+#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
+#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x8
+#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
+#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x10
+#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x20
+#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
+#define SDMA1_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800
+#define SDMA1_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb
+#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x20000
+#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
+#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000
+#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
+#define SDMA1_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000
+#define SDMA1_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16
+#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000
+#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
+#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000
+#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
+#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000
+#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
+#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
+#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
+#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2
+#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
+#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4
+#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
+#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000
+#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
+#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000
+#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
+#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000
+#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
+#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000
+#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
+#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000
+#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
+#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000
+#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
+#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define SDMA1_HASH__CHANNEL_BITS_MASK 0x7
+#define SDMA1_HASH__CHANNEL_BITS__SHIFT 0x0
+#define SDMA1_HASH__BANK_BITS_MASK 0x70
+#define SDMA1_HASH__BANK_BITS__SHIFT 0x4
+#define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK 0x700
+#define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
+#define SDMA1_HASH__BANK_XOR_COUNT_MASK 0x7000
+#define SDMA1_HASH__BANK_XOR_COUNT__SHIFT 0xc
+#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff
+#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
+#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc
+#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
+#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc
+#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
+#define SDMA1_PROGRAM__STREAM_MASK 0xffffffff
+#define SDMA1_PROGRAM__STREAM__SHIFT 0x0
+#define SDMA1_STATUS_REG__IDLE_MASK 0x1
+#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0
+#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x2
+#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1
+#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x4
+#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2
+#define SDMA1_STATUS_REG__RB_FULL_MASK 0x8
+#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3
+#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x10
+#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
+#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x20
+#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
+#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x40
+#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
+#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x80
+#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
+#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x100
+#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
+#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x200
+#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9
+#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x400
+#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa
+#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
+#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
+#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x1000
+#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc
+#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x2000
+#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
+#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x4000
+#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe
+#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000
+#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
+#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000
+#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
+#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000
+#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
+#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000
+#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
+#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x80000
+#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
+#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000
+#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
+#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000
+#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
+#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000
+#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
+#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000
+#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
+#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x4000000
+#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a
+#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000
+#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
+#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000
+#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
+#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000
+#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e
+#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000
+#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
+#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
+#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
+#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2
+#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
+#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4
+#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
+#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8
+#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
+#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x10
+#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
+#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x20
+#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
+#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x40
+#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
+#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x200
+#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
+#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400
+#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
+#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x2000
+#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
+#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000
+#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
+#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x20000
+#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
+#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x40000
+#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
+#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x3
+#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
+#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x3fc
+#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x400
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x800
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb
+#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0xff000
+#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc
+#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
+#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
+#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA1_F32_CNTL__HALT_MASK 0x1
+#define SDMA1_F32_CNTL__HALT__SHIFT 0x0
+#define SDMA1_F32_CNTL__STEP_MASK 0x2
+#define SDMA1_F32_CNTL__STEP__SHIFT 0x1
+#define SDMA1_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc
+#define SDMA1_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2
+#define SDMA1_FREEZE__FREEZE_MASK 0x10
+#define SDMA1_FREEZE__FREEZE__SHIFT 0x4
+#define SDMA1_FREEZE__FROZEN_MASK 0x20
+#define SDMA1_FREEZE__FROZEN__SHIFT 0x5
+#define SDMA1_FREEZE__F32_FREEZE_MASK 0x40
+#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6
+#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0xf
+#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0xffff00
+#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000
+#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0xf
+#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0xffff00
+#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000
+#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x2
+#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4
+#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
+#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x3ff
+#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0
+#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000
+#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
+#define SDMA1_ID__DEVICE_ID_MASK 0xff
+#define SDMA1_ID__DEVICE_ID__SHIFT 0x0
+#define SDMA1_VERSION__VALUE_MASK 0xffff
+#define SDMA1_VERSION__VALUE__SHIFT 0x0
+#define SDMA1_VM_CNTL__CMD_MASK 0xf
+#define SDMA1_VM_CNTL__CMD__SHIFT 0x0
+#define SDMA1_VM_CTX_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2
+#define SDMA1_VM_CTX_HI__ADDR_MASK 0xffffffff
+#define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0
+#define SDMA1_STATUS2_REG__ID_MASK 0x3
+#define SDMA1_STATUS2_REG__ID__SHIFT 0x0
+#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0xfffc
+#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
+#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xffff0000
+#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10
+#define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0xf
+#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000
+#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x1
+#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0
+#define SDMA1_VM_CTX_CNTL__VMID_MASK 0xf0
+#define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4
+#define SDMA1_VIRT_RESET_REQ__VF_MASK 0xffff
+#define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000
+#define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x1
+#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7fffffff
+#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
+#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000
+#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
+#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xffffffff
+#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
+#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xffffffff
+#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
+#define SDMA1_ATCL1_CNTL__REDO_ENABLE_MASK 0x1
+#define SDMA1_ATCL1_CNTL__REDO_ENABLE__SHIFT 0x0
+#define SDMA1_ATCL1_CNTL__REDO_DELAY_MASK 0x7fe
+#define SDMA1_ATCL1_CNTL__REDO_DELAY__SHIFT 0x1
+#define SDMA1_ATCL1_CNTL__REDO_WATERMK_MASK 0x3800
+#define SDMA1_ATCL1_CNTL__REDO_WATERMK__SHIFT 0xb
+#define SDMA1_ATCL1_CNTL__INVACK_DELAY_MASK 0xffc000
+#define SDMA1_ATCL1_CNTL__INVACK_DELAY__SHIFT 0xe
+#define SDMA1_ATCL1_CNTL__REQL2_CREDIT_MASK 0xf000000
+#define SDMA1_ATCL1_CNTL__REQL2_CREDIT__SHIFT 0x18
+#define SDMA1_ATCL1_CNTL__VADDR_WATERMK_MASK 0x70000000
+#define SDMA1_ATCL1_CNTL__VADDR_WATERMK__SHIFT 0x1c
+#define SDMA1_ATCL1_WATERMK__REQMC_WATERMK_MASK 0x3ff
+#define SDMA1_ATCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0
+#define SDMA1_ATCL1_WATERMK__REQPG_WATERMK_MASK 0x3fc00
+#define SDMA1_ATCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa
+#define SDMA1_ATCL1_WATERMK__INVREQ_WATERMK_MASK 0xfc0000
+#define SDMA1_ATCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12
+#define SDMA1_ATCL1_WATERMK__XNACK_WATERMK_MASK 0x7f000000
+#define SDMA1_ATCL1_WATERMK__XNACK_WATERMK__SHIFT 0x18
+#define SDMA1_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x1
+#define SDMA1_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA1_ATCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x2
+#define SDMA1_ATCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
+#define SDMA1_ATCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x4
+#define SDMA1_ATCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
+#define SDMA1_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x8
+#define SDMA1_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
+#define SDMA1_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x10
+#define SDMA1_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
+#define SDMA1_ATCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x20
+#define SDMA1_ATCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
+#define SDMA1_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x40
+#define SDMA1_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
+#define SDMA1_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x80
+#define SDMA1_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
+#define SDMA1_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x100
+#define SDMA1_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
+#define SDMA1_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x200
+#define SDMA1_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
+#define SDMA1_ATCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x400
+#define SDMA1_ATCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
+#define SDMA1_ATCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x800
+#define SDMA1_ATCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
+#define SDMA1_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x1000
+#define SDMA1_ATCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
+#define SDMA1_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x2000
+#define SDMA1_ATCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
+#define SDMA1_ATCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x4000
+#define SDMA1_ATCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
+#define SDMA1_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x8000
+#define SDMA1_ATCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
+#define SDMA1_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x10000
+#define SDMA1_ATCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
+#define SDMA1_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x20000
+#define SDMA1_ATCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
+#define SDMA1_ATCL1_RD_STATUS__ALL_IDLE_MASK 0x40000
+#define SDMA1_ATCL1_RD_STATUS__ALL_IDLE__SHIFT 0x12
+#define SDMA1_ATCL1_RD_STATUS__REQL2_IDLE_MASK 0x80000
+#define SDMA1_ATCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x13
+#define SDMA1_ATCL1_RD_STATUS__REQMC_IDLE_MASK 0x100000
+#define SDMA1_ATCL1_RD_STATUS__REQMC_IDLE__SHIFT 0x14
+#define SDMA1_ATCL1_RD_STATUS__CE_L1_STALL_MASK 0x200000
+#define SDMA1_ATCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15
+#define SDMA1_ATCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x3c00000
+#define SDMA1_ATCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16
+#define SDMA1_ATCL1_RD_STATUS__MERGE_STATE_MASK 0x1c000000
+#define SDMA1_ATCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a
+#define SDMA1_ATCL1_RD_STATUS__RESERVED_MASK 0xe0000000
+#define SDMA1_ATCL1_RD_STATUS__RESERVED__SHIFT 0x1d
+#define SDMA1_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x1
+#define SDMA1_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0
+#define SDMA1_ATCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x2
+#define SDMA1_ATCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
+#define SDMA1_ATCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x4
+#define SDMA1_ATCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2
+#define SDMA1_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x8
+#define SDMA1_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3
+#define SDMA1_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x10
+#define SDMA1_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4
+#define SDMA1_ATCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x20
+#define SDMA1_ATCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5
+#define SDMA1_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x40
+#define SDMA1_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6
+#define SDMA1_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x80
+#define SDMA1_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7
+#define SDMA1_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x100
+#define SDMA1_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8
+#define SDMA1_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x200
+#define SDMA1_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9
+#define SDMA1_ATCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x400
+#define SDMA1_ATCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa
+#define SDMA1_ATCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x800
+#define SDMA1_ATCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb
+#define SDMA1_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x1000
+#define SDMA1_ATCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc
+#define SDMA1_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x2000
+#define SDMA1_ATCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd
+#define SDMA1_ATCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x4000
+#define SDMA1_ATCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe
+#define SDMA1_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x8000
+#define SDMA1_ATCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf
+#define SDMA1_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x10000
+#define SDMA1_ATCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10
+#define SDMA1_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x20000
+#define SDMA1_ATCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11
+#define SDMA1_ATCL1_WR_STATUS__ALL_IDLE_MASK 0x40000
+#define SDMA1_ATCL1_WR_STATUS__ALL_IDLE__SHIFT 0x12
+#define SDMA1_ATCL1_WR_STATUS__REQL2_IDLE_MASK 0x80000
+#define SDMA1_ATCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x13
+#define SDMA1_ATCL1_WR_STATUS__REQMC_IDLE_MASK 0x100000
+#define SDMA1_ATCL1_WR_STATUS__REQMC_IDLE__SHIFT 0x14
+#define SDMA1_ATCL1_WR_STATUS__F32_WR_RTR_MASK 0x200000
+#define SDMA1_ATCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15
+#define SDMA1_ATCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x3c00000
+#define SDMA1_ATCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16
+#define SDMA1_ATCL1_WR_STATUS__MERGE_STATE_MASK 0x1c000000
+#define SDMA1_ATCL1_WR_STATUS__MERGE_STATE__SHIFT 0x1a
+#define SDMA1_ATCL1_WR_STATUS__RESERVED_MASK 0xe0000000
+#define SDMA1_ATCL1_WR_STATUS__RESERVED__SHIFT 0x1d
+#define SDMA1_ATCL1_INV0__INV_MIDDLE_MASK 0x1
+#define SDMA1_ATCL1_INV0__INV_MIDDLE__SHIFT 0x0
+#define SDMA1_ATCL1_INV0__RD_TIMEOUT_MASK 0x2
+#define SDMA1_ATCL1_INV0__RD_TIMEOUT__SHIFT 0x1
+#define SDMA1_ATCL1_INV0__WR_TIMEOUT_MASK 0x4
+#define SDMA1_ATCL1_INV0__WR_TIMEOUT__SHIFT 0x2
+#define SDMA1_ATCL1_INV0__RD_IN_INVADR_MASK 0x8
+#define SDMA1_ATCL1_INV0__RD_IN_INVADR__SHIFT 0x3
+#define SDMA1_ATCL1_INV0__WR_IN_INVADR_MASK 0x10
+#define SDMA1_ATCL1_INV0__WR_IN_INVADR__SHIFT 0x4
+#define SDMA1_ATCL1_INV0__RD_WT_INVADR_MASK 0x20
+#define SDMA1_ATCL1_INV0__RD_WT_INVADR__SHIFT 0x5
+#define SDMA1_ATCL1_INV0__WR_WT_INVADR_MASK 0x40
+#define SDMA1_ATCL1_INV0__WR_WT_INVADR__SHIFT 0x6
+#define SDMA1_ATCL1_INV0__RD_INV_EN_MASK 0x80
+#define SDMA1_ATCL1_INV0__RD_INV_EN__SHIFT 0x7
+#define SDMA1_ATCL1_INV0__WR_INV_EN_MASK 0x100
+#define SDMA1_ATCL1_INV0__WR_INV_EN__SHIFT 0x8
+#define SDMA1_ATCL1_INV0__RD_INV_IDLE_MASK 0x200
+#define SDMA1_ATCL1_INV0__RD_INV_IDLE__SHIFT 0x9
+#define SDMA1_ATCL1_INV0__WR_INV_IDLE_MASK 0x400
+#define SDMA1_ATCL1_INV0__WR_INV_IDLE__SHIFT 0xa
+#define SDMA1_ATCL1_INV0__INV_FLUSHTYPE_MASK 0x800
+#define SDMA1_ATCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb
+#define SDMA1_ATCL1_INV0__INV_VMID_VEC_MASK 0xffff000
+#define SDMA1_ATCL1_INV0__INV_VMID_VEC__SHIFT 0xc
+#define SDMA1_ATCL1_INV0__INV_ADDR_HI_MASK 0xf0000000
+#define SDMA1_ATCL1_INV0__INV_ADDR_HI__SHIFT 0x1c
+#define SDMA1_ATCL1_INV1__INV_ADDR_LO_MASK 0xffffffff
+#define SDMA1_ATCL1_INV1__INV_ADDR_LO__SHIFT 0x0
+#define SDMA1_ATCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xffff
+#define SDMA1_ATCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0
+#define SDMA1_ATCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xffffffff
+#define SDMA1_ATCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA1_ATCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0xf
+#define SDMA1_ATCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA1_ATCL1_RD_XNACK1__XNACK_VMID_MASK 0xf0
+#define SDMA1_ATCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA1_ATCL1_RD_XNACK1__IS_XNACK_MASK 0x100
+#define SDMA1_ATCL1_RD_XNACK1__IS_XNACK__SHIFT 0x8
+#define SDMA1_ATCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xffffffff
+#define SDMA1_ATCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0
+#define SDMA1_ATCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0xf
+#define SDMA1_ATCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0
+#define SDMA1_ATCL1_WR_XNACK1__XNACK_VMID_MASK 0xf0
+#define SDMA1_ATCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4
+#define SDMA1_ATCL1_WR_XNACK1__IS_XNACK_MASK 0x100
+#define SDMA1_ATCL1_WR_XNACK1__IS_XNACK__SHIFT 0x8
+#define SDMA1_ATCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0xffff
+#define SDMA1_ATCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0
+#define SDMA1_ATCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xffff0000
+#define SDMA1_ATCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10
+#define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0xffff
+#define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0
+#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0xff0000
+#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10
+#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xff000000
+#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18
+#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL_MASK 0x1
+#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL__SHIFT 0x0
+#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT_MASK 0x2
+#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x1
+#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT_MASK 0x4
+#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x2
+#define SDMA1_PERF_REG_TYPE0__RESERVED_31_3_MASK 0xfffffff8
+#define SDMA1_PERF_REG_TYPE0__RESERVED_31_3__SHIFT 0x3
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x1
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x2
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x4
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x8
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x10
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x4
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x20
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x5
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x40
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x6
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x80
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x7
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x100
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x200
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x400
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x800
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x1000
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x2000
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x4000
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x8000
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x10000
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x20000
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x40000
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x80000
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13
+#define SDMA1_CONTEXT_REG_TYPE0__RESERVED_MASK 0xfff00000
+#define SDMA1_CONTEXT_REG_TYPE0__RESERVED__SHIFT 0x14
+#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG0_MASK 0x7f
+#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG0__SHIFT 0x0
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_VIRTUAL_ADDR_MASK 0x80
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_VIRTUAL_ADDR__SHIFT 0x7
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_APE1_CNTL_MASK 0x100
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_APE1_CNTL__SHIFT 0x8
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x200
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x400
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa
+#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x800
+#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xb
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x1000
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x2000
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd
+#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG3_MASK 0x4000
+#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG3__SHIFT 0xe
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x8000
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x10000
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x20000
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11
+#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xfffc0000
+#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x12
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x1
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x2
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x4
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x8
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x10
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x20
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x40
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x80
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x100
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x200
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x9
+#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xfffffc00
+#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x1
+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0
+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x2
+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1
+#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x4
+#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x2
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x8
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x3
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x4
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x5
+#define SDMA1_PUB_REG_TYPE0__SDMA1_TILING_CONFIG_MASK 0x40
+#define SDMA1_PUB_REG_TYPE0__SDMA1_TILING_CONFIG__SHIFT 0x6
+#define SDMA1_PUB_REG_TYPE0__SDMA1_HASH_MASK 0x80
+#define SDMA1_PUB_REG_TYPE0__SDMA1_HASH__SHIFT 0x7
+#define SDMA1_PUB_REG_TYPE0__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x200
+#define SDMA1_PUB_REG_TYPE0__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x9
+#define SDMA1_PUB_REG_TYPE0__SDMA1_RB_RPTR_FETCH_MASK 0x400
+#define SDMA1_PUB_REG_TYPE0__SDMA1_RB_RPTR_FETCH__SHIFT 0xa
+#define SDMA1_PUB_REG_TYPE0__SDMA1_IB_OFFSET_FETCH_MASK 0x800
+#define SDMA1_PUB_REG_TYPE0__SDMA1_IB_OFFSET_FETCH__SHIFT 0xb
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PROGRAM_MASK 0x1000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PROGRAM__SHIFT 0xc
+#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS_REG_MASK 0x2000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS_REG__SHIFT 0xd
+#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS1_REG_MASK 0x4000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS1_REG__SHIFT 0xe
+#define SDMA1_PUB_REG_TYPE0__SDMA1_RD_BURST_CNTL_MASK 0x8000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_RD_BURST_CNTL__SHIFT 0xf
+#define SDMA1_PUB_REG_TYPE0__RESERVED_16_MASK 0x10000
+#define SDMA1_PUB_REG_TYPE0__RESERVED_16__SHIFT 0x10
+#define SDMA1_PUB_REG_TYPE0__RESERVED_17_MASK 0x20000
+#define SDMA1_PUB_REG_TYPE0__RESERVED_17__SHIFT 0x11
+#define SDMA1_PUB_REG_TYPE0__SDMA1_F32_CNTL_MASK 0x40000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_F32_CNTL__SHIFT 0x12
+#define SDMA1_PUB_REG_TYPE0__SDMA1_FREEZE_MASK 0x80000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_FREEZE__SHIFT 0x13
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE0_QUANTUM_MASK 0x100000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE0_QUANTUM__SHIFT 0x14
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE1_QUANTUM_MASK 0x200000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE1_QUANTUM__SHIFT 0x15
+#define SDMA1_PUB_REG_TYPE0__VOID_REG0_MASK 0x3c00000
+#define SDMA1_PUB_REG_TYPE0__VOID_REG0__SHIFT 0x16
+#define SDMA1_PUB_REG_TYPE0__SDMA1_EDC_CONFIG_MASK 0x4000000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_EDC_CONFIG__SHIFT 0x1a
+#define SDMA1_PUB_REG_TYPE0__SDMA1_BA_THRESHOLD_MASK 0x8000000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_BA_THRESHOLD__SHIFT 0x1b
+#define SDMA1_PUB_REG_TYPE0__SDMA1_DEVICE_ID_MASK 0x10000000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_DEVICE_ID__SHIFT 0x1c
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VERSION_MASK 0x20000000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VERSION__SHIFT 0x1d
+#define SDMA1_PUB_REG_TYPE0__RESERVED_MASK 0xc0000000
+#define SDMA1_PUB_REG_TYPE0__RESERVED__SHIFT 0x1e
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL_MASK 0x1
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL__SHIFT 0x0
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO_MASK 0x2
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO__SHIFT 0x1
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI_MASK 0x4
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI__SHIFT 0x2
+#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x8
+#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x3
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ACTIVE_FCN_ID_MASK 0x10
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ACTIVE_FCN_ID__SHIFT 0x4
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_CNTL_MASK 0x20
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_CNTL__SHIFT 0x5
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VIRT_RESET_REQ_MASK 0x40
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VIRT_RESET_REQ__SHIFT 0x6
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VF_ENABLE_MASK 0x80
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VF_ENABLE__SHIFT 0x7
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x100
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x8
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x200
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x9
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x400
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0xa
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_CNTL_MASK 0x800
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_CNTL__SHIFT 0xb
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_WATERMK_MASK 0x1000
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_WATERMK__SHIFT 0xc
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_TIMEOUT_MASK 0x2000
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATCL1_TIMEOUT__SHIFT 0xd
+#define SDMA1_PUB_REG_TYPE1__RESERVED_MASK 0xffffc000
+#define SDMA1_PUB_REG_TYPE1__RESERVED__SHIFT 0xe
+#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_GFX_DOORBELL__OFFSET_MASK 0x1fffff
+#define SDMA1_GFX_DOORBELL__OFFSET__SHIFT 0x0
+#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000
+#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000
+#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000
+#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
+#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000
+#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
+#define SDMA1_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA1_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA1_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2
+#define SDMA1_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1
+#define SDMA1_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA1_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA1_GFX_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA1_GFX_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA1_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA1_GFX_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1
+#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xfffffffc
+#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff
+#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x1
+#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff
+#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xffffffff
+#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xffffffff
+#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xffffffff
+#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xffffffff
+#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xffffffff
+#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xffffffff
+#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xffffffff
+#define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xffffffff
+#define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xffffffff
+#define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1
+#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2
+#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
+#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
+#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC0_DOORBELL__OFFSET_MASK 0x1fffff
+#define SDMA1_RLC0_DOORBELL__OFFSET__SHIFT 0x0
+#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000
+#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000
+#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA1_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA1_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2
+#define SDMA1_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1
+#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA1_RLC0_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA1_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA1_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
+#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc
+#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff
+#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1
+#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff
+#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xffffffff
+#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xffffffff
+#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xffffffff
+#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xffffffff
+#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xffffffff
+#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xffffffff
+#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xffffffff
+#define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xffffffff
+#define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xffffffff
+#define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1
+#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2
+#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
+#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
+#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC1_DOORBELL__OFFSET_MASK 0x1fffff
+#define SDMA1_RLC1_DOORBELL__OFFSET__SHIFT 0x0
+#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000
+#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000
+#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA1_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA1_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2
+#define SDMA1_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1
+#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA1_RLC1_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA1_RLC1_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA1_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA1_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
+#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc
+#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff
+#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1
+#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff
+#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xffffffff
+#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xffffffff
+#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xffffffff
+#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xffffffff
+#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xffffffff
+#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xffffffff
+#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xffffffff
+#define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xffffffff
+#define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xffffffff
+#define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1
+#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2
+#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
+#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
+#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x7
+#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x0
+#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x1f8
+#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x3
+#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x600
+#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9
+#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x1800
+#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x180000
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x200000
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15
+#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x400000
+#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x16
+#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x800000
+#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x17
+#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0xf000000
+#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x18
+#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000
+#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d
+#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000
+#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e
+#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000
+#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f
+#define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffff
+#define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x0
+#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x1
+#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x0
+#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x1e
+#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x1
+#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x60
+#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x5
+#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x380
+#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x7
+#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x1c00
+#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0xa
+#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x6000
+#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0xd
+#define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x8000
+#define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0xf
+#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x10000
+#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x10
+#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0xe0000
+#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x11
+#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x300000
+#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x14
+#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0xc00000
+#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x16
+#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x3000000
+#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x18
+#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0xc000000
+#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x1a
+#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x70000000
+#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x1c
+#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x80000000
+#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x1f
+#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x7ff
+#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x0
+#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800
+#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0xb
+#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x1
+#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0
+#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x2
+#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x1
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x2
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1
+#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffff
+#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0
+#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0
+#define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x0
+#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x3f
+#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0
+#define HDP_TILING_CONFIG__PIPE_TILING_MASK 0xe
+#define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x1
+#define HDP_TILING_CONFIG__BANK_TILING_MASK 0x30
+#define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x4
+#define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0xc0
+#define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x6
+#define HDP_TILING_CONFIG__ROW_TILING_MASK 0x700
+#define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x8
+#define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x3800
+#define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0xb
+#define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0xc000
+#define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0xe
+#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x7
+#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x0
+#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x18
+#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x3
+#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0xff
+#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0
+#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0xff00
+#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8
+#define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x1
+#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0
+#define HDP_MISC_CNTL__VM_ID_MASK 0x1e
+#define HDP_MISC_CNTL__VM_ID__SHIFT 0x1
+#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x20
+#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5
+#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x40
+#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6
+#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x780
+#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x7
+#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x800
+#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb
+#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x1000
+#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0xc
+#define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x7e000
+#define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
+#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x80000
+#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x13
+#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x100000
+#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x14
+#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x200000
+#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15
+#define HDP_MISC_CNTL__LEGACY_TILING_ENABLE_MASK 0x400000
+#define HDP_MISC_CNTL__LEGACY_TILING_ENABLE__SHIFT 0x16
+#define HDP_MISC_CNTL__LEGACY_SURFACES_ENABLE_MASK 0x800000
+#define HDP_MISC_CNTL__LEGACY_SURFACES_ENABLE__SHIFT 0x17
+#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x1
+#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0
+#define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x7e
+#define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x1
+#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x1f80
+#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x7
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x0
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x38
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x3
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x1c0
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x6
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0xffe00
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x9
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x1b
+#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x1
+#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0
+#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x2
+#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1
+#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x3c
+#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2
+#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x40
+#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6
+#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x80
+#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7
+#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x3f00
+#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8
+#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x4000
+#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe
+#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x8000
+#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf
+#define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x10000
+#define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10
+#define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x1e0000
+#define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11
+#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffff
+#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0
+#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x1
+#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0
+#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x2
+#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1
+#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x4
+#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2
+#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x8
+#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3
+#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffff
+#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0
+#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffff
+#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0
+#define HDP_VF_ENABLE__VF_EN_MASK 0x1
+#define HDP_VF_ENABLE__VF_EN__SHIFT 0x0
+#define HDP_VF_ENABLE__VF_NUM_MASK 0xffff0000
+#define HDP_VF_ENABLE__VF_NUM__SHIFT 0x10
+#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffff
+#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0xf
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0xf0
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x700
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0xf800
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x10000
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x20000
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x11
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x40000
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x80000
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x100000
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0xffff
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0xf0000
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x700000
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
+#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0
+#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffff
+#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0xf
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x30
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4
+#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x3fff
+#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x1
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x0
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x6
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x1
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x8
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x3
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0xf0
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x4
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x1
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x0
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x6
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x1
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x8
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x3
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x10
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x4
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x60
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x5
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x80
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x7
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x3f00
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x8
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0xfc000
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x700000
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x14
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x7800000
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x17
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x1b
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x1
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x6
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1
+#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x1
+#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x0
+#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x6
+#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x1
+#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x18
+#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x3
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x3f
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0xfc0
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x1000
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x2000
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x3f
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x0
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x40
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x6
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x80
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x7
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0xf
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x0
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0xff0
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x4
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0xc
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x1e
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x1f
+#define HDP_XDP_P2P_BAR0__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR0__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR1__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR1__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR2__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR2__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR3__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR3__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR4__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR4__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR5__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR5__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR6__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR6__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR7__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR7__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14
+#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffff
+#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0
+#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x3ffffff
+#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0
+#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x3ffff
+#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0
+#define HDP_XDP_STICKY__STICKY_STS_MASK 0xffff
+#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0
+#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000
+#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10
+#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0xff
+#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0
+#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0xff00
+#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8
+#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0xff0000
+#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10
+#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000
+#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18
+#define HDP_XDP_DBG_ADDR__STS_MASK 0xffff
+#define HDP_XDP_DBG_ADDR__STS__SHIFT 0x0
+#define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000
+#define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x10
+#define HDP_XDP_DBG_DATA__STS_MASK 0xffff
+#define HDP_XDP_DBG_DATA__STS__SHIFT 0x0
+#define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000
+#define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x10
+#define HDP_XDP_DBG_MASK__STS_MASK 0xffff
+#define HDP_XDP_DBG_MASK__STS__SHIFT 0x0
+#define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000
+#define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x10
+#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0xf
+#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0
+#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0xf0
+#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4
+#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0xf00
+#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8
+#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0xf000
+#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc
+#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0xf0000
+#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10
+#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0xf00000
+#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0xf000000
+#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18
+#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000
+#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c
+
+#endif /* OSS_3_0_1_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h
new file mode 100644
index 000000000000..f56c68bb0b91
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h
@@ -0,0 +1,688 @@
+/*
+ * OSS_3_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef OSS_3_0_D_H
+#define OSS_3_0_D_H
+
+#define mmIH_VMID_0_LUT 0xe00
+#define mmIH_VMID_1_LUT 0xe01
+#define mmIH_VMID_2_LUT 0xe02
+#define mmIH_VMID_3_LUT 0xe03
+#define mmIH_VMID_4_LUT 0xe04
+#define mmIH_VMID_5_LUT 0xe05
+#define mmIH_VMID_6_LUT 0xe06
+#define mmIH_VMID_7_LUT 0xe07
+#define mmIH_VMID_8_LUT 0xe08
+#define mmIH_VMID_9_LUT 0xe09
+#define mmIH_VMID_10_LUT 0xe0a
+#define mmIH_VMID_11_LUT 0xe0b
+#define mmIH_VMID_12_LUT 0xe0c
+#define mmIH_VMID_13_LUT 0xe0d
+#define mmIH_VMID_14_LUT 0xe0e
+#define mmIH_VMID_15_LUT 0xe0f
+#define mmIH_RB_CNTL 0xe30
+#define mmIH_RB_BASE 0xe31
+#define mmIH_RB_RPTR 0xe32
+#define mmIH_RB_WPTR 0xe33
+#define mmIH_RB_WPTR_ADDR_HI 0xe34
+#define mmIH_RB_WPTR_ADDR_LO 0xe35
+#define mmIH_CNTL 0xe36
+#define mmIH_LEVEL_STATUS 0xe37
+#define mmIH_STATUS 0xe38
+#define mmIH_PERFMON_CNTL 0xe39
+#define mmIH_PERFCOUNTER0_RESULT 0xe3a
+#define mmIH_PERFCOUNTER1_RESULT 0xe3b
+#define mmIH_DEBUG 0xe3c
+#define mmIH_DSM_MATCH_VALUE_BIT_31_0 0xe3d
+#define mmIH_DSM_MATCH_VALUE_BIT_63_32 0xe3e
+#define mmIH_DSM_MATCH_VALUE_BIT_95_64 0xe3f
+#define mmIH_DSM_MATCH_FIELD_CONTROL 0xe40
+#define mmIH_DSM_MATCH_DATA_CONTROL 0xe41
+#define mmIH_DOORBELL_RPTR 0xe42
+#define mmIH_ACTIVE_FCN_ID 0xe43
+#define mmIH_VF_RB_STATUS 0xe44
+#define mmIH_VF_ENABLE 0xe45
+#define mmIH_VIRT_RESET_REQ 0xe46
+#define mmIH_VF_RB_BIF_STATUS 0xe47
+#define mmIH_VERSION 0xe48
+#define mmIH_LEVEL_INTR_MASK 0xe49
+#define mmIH_RESET_INCOMPLETE_INT_CNTL 0xe4a
+#define mmIH_CLIENT_MAY_SEND_INCOMPLETE_INT 0xe4b
+#define mmSEM_MCIF_CONFIG 0xf90
+#define mmSDMA_CONFIG 0xf91
+#define mmSDMA1_CONFIG 0xf92
+#define mmUVD_CONFIG 0xf93
+#define mmVCE_CONFIG 0xf94
+#define mmSEM_VF_ENABLE 0xf95
+#define mmCP_CONFIG 0xf96
+#define mmSEM_ACTIVE_FCN_ID 0xf97
+#define mmSEM_VIRT_RESET_REQ 0xf98
+#define mmSEM_STATUS 0xf99
+#define mmSEM_EDC_CONFIG 0xf9a
+#define mmSEM_MAILBOX_CLIENTCONFIG 0xf9b
+#define mmSEM_MAILBOX 0xf9c
+#define mmSEM_MAILBOX_CONTROL 0xf9d
+#define mmSEM_CHICKEN_BITS 0xf9e
+#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0xf9f
+#define mmSRBM_CNTL 0x390
+#define mmSRBM_GFX_CNTL 0x391
+#define mmSRBM_READ_CNTL 0x392
+#define mmSRBM_STATUS2 0x393
+#define mmSRBM_STATUS 0x394
+#define mmSRBM_STATUS3 0x395
+#define mmSRBM_SOFT_RESET 0x398
+#define mmSRBM_DEBUG_CNTL 0x399
+#define mmSRBM_DEBUG_DATA 0x39a
+#define mmSRBM_CHIP_REVISION 0x39b
+#define mmSRBM_CREDIT_RECOVER_CNTL 0x39c
+#define mmSRBM_CREDIT_RECOVER 0x39d
+#define mmSRBM_CREDIT_RESET 0x39e
+#define mmCC_SYS_RB_REDUNDANCY 0x39f
+#define mmCC_SYS_RB_BACKEND_DISABLE 0x3a0
+#define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x3a1
+#define mmSRBM_MC_CLKEN_CNTL 0x3b3
+#define mmSRBM_SYS_CLKEN_CNTL 0x3b4
+#define mmSRBM_VCE_CLKEN_CNTL 0x3b5
+#define mmSRBM_UVD_CLKEN_CNTL 0x3b6
+#define mmSRBM_SDMA_CLKEN_CNTL 0x3b7
+#define mmSRBM_SAM_CLKEN_CNTL 0x3b8
+#define mmSRBM_ISP_CLKEN_CNTL 0x3b9
+#define mmSRBM_VP8_CLKEN_CNTL 0x3ba
+#define mmSRBM_DEBUG 0x3a4
+#define mmSRBM_DEBUG_SNAPSHOT 0x3a5
+#define mmSRBM_DEBUG_SNAPSHOT2 0x3ad
+#define mmSRBM_READ_ERROR 0x3a6
+#define mmSRBM_READ_ERROR2 0x3ae
+#define mmSRBM_INT_CNTL 0x3a8
+#define mmSRBM_INT_STATUS 0x3a9
+#define mmSRBM_INT_ACK 0x3aa
+#define mmSRBM_FIREWALL_ERROR_SRC 0x3ab
+#define mmSRBM_FIREWALL_ERROR_ADDR 0x3ac
+#define mmSRBM_DSM_TRIG_CNTL0 0x3af
+#define mmSRBM_DSM_TRIG_CNTL1 0x3b0
+#define mmSRBM_DSM_TRIG_MASK0 0x3b1
+#define mmSRBM_DSM_TRIG_MASK1 0x3b2
+#define mmSRBM_PERFMON_CNTL 0x7c00
+#define mmSRBM_PERFCOUNTER0_SELECT 0x7c01
+#define mmSRBM_PERFCOUNTER1_SELECT 0x7c02
+#define mmSRBM_PERFCOUNTER0_LO 0x7c03
+#define mmSRBM_PERFCOUNTER0_HI 0x7c04
+#define mmSRBM_PERFCOUNTER1_LO 0x7c05
+#define mmSRBM_PERFCOUNTER1_HI 0x7c06
+#define mmSRBM_CAM_INDEX 0xfe34
+#define mmSRBM_CAM_DATA 0xfe35
+#define mmSRBM_MC_DOMAIN_ADDR0 0xfa00
+#define mmSRBM_MC_DOMAIN_ADDR1 0xfa01
+#define mmSRBM_MC_DOMAIN_ADDR2 0xfa02
+#define mmSRBM_MC_DOMAIN_ADDR3 0xfa03
+#define mmSRBM_MC_DOMAIN_ADDR4 0xfa04
+#define mmSRBM_MC_DOMAIN_ADDR5 0xfa05
+#define mmSRBM_MC_DOMAIN_ADDR6 0xfa06
+#define mmSRBM_SYS_DOMAIN_ADDR0 0xfa08
+#define mmSRBM_SYS_DOMAIN_ADDR1 0xfa09
+#define mmSRBM_SYS_DOMAIN_ADDR2 0xfa0a
+#define mmSRBM_SYS_DOMAIN_ADDR3 0xfa0b
+#define mmSRBM_SYS_DOMAIN_ADDR4 0xfa0c
+#define mmSRBM_SYS_DOMAIN_ADDR5 0xfa0d
+#define mmSRBM_SYS_DOMAIN_ADDR6 0xfa0e
+#define mmSRBM_SDMA_DOMAIN_ADDR0 0xfa10
+#define mmSRBM_SDMA_DOMAIN_ADDR1 0xfa11
+#define mmSRBM_SDMA_DOMAIN_ADDR2 0xfa12
+#define mmSRBM_SDMA_DOMAIN_ADDR3 0xfa13
+#define mmSRBM_UVD_DOMAIN_ADDR0 0xfa14
+#define mmSRBM_UVD_DOMAIN_ADDR1 0xfa15
+#define mmSRBM_UVD_DOMAIN_ADDR2 0xfa16
+#define mmSRBM_VCE_DOMAIN_ADDR0 0xfa18
+#define mmSRBM_VCE_DOMAIN_ADDR1 0xfa19
+#define mmSRBM_VCE_DOMAIN_ADDR2 0xfa1a
+#define mmSRBM_SAM_DOMAIN_ADDR0 0xfa1c
+#define mmSRBM_SAM_DOMAIN_ADDR1 0xfa1d
+#define mmSRBM_SAM_DOMAIN_ADDR2 0xfa1e
+#define mmSRBM_ISP_DOMAIN_ADDR0 0xfa20
+#define mmSRBM_ISP_DOMAIN_ADDR1 0xfa21
+#define mmSRBM_ISP_DOMAIN_ADDR2 0xfa22
+#define mmSRBM_VP8_DOMAIN_ADDR0 0xfa24
+#define mmSYS_GRBM_GFX_INDEX_SELECT 0xfa2c
+#define mmSYS_GRBM_GFX_INDEX_DATA 0xfa2d
+#define mmSRBM_GFX_CNTL_SELECT 0xfa2e
+#define mmSRBM_GFX_CNTL_DATA 0xfa2f
+#define mmSRBM_VF_ENABLE 0xfa30
+#define mmSRBM_VIRT_CNTL 0xfa31
+#define mmSRBM_VIRT_RESET_REQ 0xfa32
+#define mmCC_DRM_ID_STRAPS 0x1559
+#define mmCGTT_DRM_CLK_CTRL0 0x1579
+#define ixDH_TEST 0x0
+#define ixKHFS0 0x4
+#define ixKHFS1 0x8
+#define ixKHFS2 0xc
+#define ixKHFS3 0x10
+#define ixKSESSION0 0x14
+#define ixKSESSION1 0x18
+#define ixKSESSION2 0x1c
+#define ixKSESSION3 0x20
+#define ixKSIG0 0x24
+#define ixKSIG1 0x28
+#define ixKSIG2 0x2c
+#define ixKSIG3 0x30
+#define ixEXP0 0x34
+#define ixEXP1 0x38
+#define ixEXP2 0x3c
+#define ixEXP3 0x40
+#define ixEXP4 0x44
+#define ixEXP5 0x48
+#define ixEXP6 0x4c
+#define ixEXP7 0x50
+#define ixLX0 0x54
+#define ixLX1 0x58
+#define ixLX2 0x5c
+#define ixLX3 0x60
+#define ixCLIENT2_K0 0x1b4
+#define ixCLIENT2_K1 0x1b8
+#define ixCLIENT2_K2 0x1bc
+#define ixCLIENT2_K3 0x1c0
+#define ixCLIENT2_CK0 0x1c4
+#define ixCLIENT2_CK1 0x1c8
+#define ixCLIENT2_CK2 0x1cc
+#define ixCLIENT2_CK3 0x1d0
+#define ixCLIENT2_CD0 0x1d4
+#define ixCLIENT2_CD1 0x1d8
+#define ixCLIENT2_CD2 0x1dc
+#define ixCLIENT2_CD3 0x1e0
+#define ixCLIENT2_BM 0x1e4
+#define ixCLIENT2_OFFSET 0x1e8
+#define ixCLIENT2_STATUS 0x1ec
+#define ixCLIENT0_K0 0x1f0
+#define ixCLIENT0_K1 0x1f4
+#define ixCLIENT0_K2 0x1f8
+#define ixCLIENT0_K3 0x1fc
+#define ixCLIENT0_CK0 0x200
+#define ixCLIENT0_CK1 0x204
+#define ixCLIENT0_CK2 0x208
+#define ixCLIENT0_CK3 0x20c
+#define ixCLIENT0_CD0 0x210
+#define ixCLIENT0_CD1 0x214
+#define ixCLIENT0_CD2 0x218
+#define ixCLIENT0_CD3 0x21c
+#define ixCLIENT0_BM 0x220
+#define ixCLIENT0_OFFSET 0x224
+#define ixCLIENT0_STATUS 0x228
+#define ixCLIENT1_K0 0x22c
+#define ixCLIENT1_K1 0x230
+#define ixCLIENT1_K2 0x234
+#define ixCLIENT1_K3 0x238
+#define ixCLIENT1_CK0 0x23c
+#define ixCLIENT1_CK1 0x240
+#define ixCLIENT1_CK2 0x244
+#define ixCLIENT1_CK3 0x248
+#define ixCLIENT1_CD0 0x24c
+#define ixCLIENT1_CD1 0x250
+#define ixCLIENT1_CD2 0x254
+#define ixCLIENT1_CD3 0x258
+#define ixCLIENT1_BM 0x25c
+#define ixCLIENT1_OFFSET 0x260
+#define ixCLIENT1_PORT_STATUS 0x264
+#define ixKEFUSE0 0x268
+#define ixKEFUSE1 0x26c
+#define ixKEFUSE2 0x270
+#define ixKEFUSE3 0x274
+#define ixHFS_SEED0 0x278
+#define ixHFS_SEED1 0x27c
+#define ixHFS_SEED2 0x280
+#define ixHFS_SEED3 0x284
+#define ixRINGOSC_MASK 0x288
+#define ixCLIENT0_OFFSET_HI 0x290
+#define ixCLIENT1_OFFSET_HI 0x294
+#define ixCLIENT2_OFFSET_HI 0x298
+#define ixSPU_PORT_STATUS 0x29c
+#define ixCLIENT3_OFFSET_HI 0x2a0
+#define ixCLIENT3_K0 0x2a4
+#define ixCLIENT3_K1 0x2a8
+#define ixCLIENT3_K2 0x2ac
+#define ixCLIENT3_K3 0x2b0
+#define ixCLIENT3_CK0 0x2b4
+#define ixCLIENT3_CK1 0x2b8
+#define ixCLIENT3_CK2 0x2bc
+#define ixCLIENT3_CK3 0x2c0
+#define ixCLIENT3_CD0 0x2c4
+#define ixCLIENT3_CD1 0x2c8
+#define ixCLIENT3_CD2 0x2cc
+#define ixCLIENT3_CD3 0x2d0
+#define ixCLIENT3_BM 0x2d4
+#define ixCLIENT3_OFFSET 0x2d8
+#define ixCLIENT3_STATUS 0x2dc
+#define ixCLIENT4_OFFSET_HI 0x2e0
+#define ixCLIENT4_K0 0x2e4
+#define ixCLIENT4_K1 0x2e8
+#define ixCLIENT4_K2 0x2ec
+#define ixCLIENT4_K3 0x2f0
+#define ixCLIENT4_CK0 0x2f4
+#define ixCLIENT4_CK1 0x2f8
+#define ixCLIENT4_CK2 0x2fc
+#define ixCLIENT4_CK3 0x300
+#define ixCLIENT4_CD0 0x304
+#define ixCLIENT4_CD1 0x308
+#define ixCLIENT4_CD2 0x30c
+#define ixCLIENT4_CD3 0x310
+#define ixCLIENT4_BM 0x314
+#define ixCLIENT4_OFFSET 0x318
+#define ixCLIENT4_STATUS 0x31c
+#define mmDC_TEST_DEBUG_INDEX 0x157c
+#define mmDC_TEST_DEBUG_DATA 0x157d
+#define mmSDMA0_UCODE_ADDR 0x3400
+#define mmSDMA0_UCODE_DATA 0x3401
+#define mmSDMA0_POWER_CNTL 0x3402
+#define mmSDMA0_CLK_CTRL 0x3403
+#define mmSDMA0_CNTL 0x3404
+#define mmSDMA0_CHICKEN_BITS 0x3405
+#define mmSDMA0_TILING_CONFIG 0x3406
+#define mmSDMA0_HASH 0x3407
+#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409
+#define mmSDMA0_RB_RPTR_FETCH 0x340a
+#define mmSDMA0_IB_OFFSET_FETCH 0x340b
+#define mmSDMA0_PROGRAM 0x340c
+#define mmSDMA0_STATUS_REG 0x340d
+#define mmSDMA0_STATUS1_REG 0x340e
+#define mmSDMA0_RD_BURST_CNTL 0x340f
+#define mmSDMA0_PERFMON_CNTL 0x9000
+#define mmSDMA0_PERFCOUNTER0_RESULT 0x9001
+#define mmSDMA0_PERFCOUNTER1_RESULT 0x9002
+#define mmSDMA0_F32_CNTL 0x3412
+#define mmSDMA0_FREEZE 0x3413
+#define mmSDMA0_PHASE0_QUANTUM 0x3414
+#define mmSDMA0_PHASE1_QUANTUM 0x3415
+#define mmSDMA_POWER_GATING 0x3416
+#define mmSDMA_PGFSM_CONFIG 0x3417
+#define mmSDMA_PGFSM_WRITE 0x3418
+#define mmSDMA_PGFSM_READ 0x3419
+#define mmSDMA0_EDC_CONFIG 0x341a
+#define mmSDMA0_VM_CNTL 0x3420
+#define mmSDMA0_VM_CTX_LO 0x3421
+#define mmSDMA0_VM_CTX_HI 0x3422
+#define mmSDMA0_STATUS2_REG 0x3423
+#define mmSDMA0_ACTIVE_FCN_ID 0x3424
+#define mmSDMA0_VM_CTX_CNTL 0x3425
+#define mmSDMA0_VIRT_RESET_REQ 0x3426
+#define mmSDMA0_VF_ENABLE 0x3427
+#define mmSDMA0_BA_THRESHOLD 0x341b
+#define mmSDMA0_ID 0x341c
+#define mmSDMA0_VERSION 0x341d
+#define mmSDMA0_ATOMIC_CNTL 0x3428
+#define mmSDMA0_ATOMIC_PREOP_LO 0x3429
+#define mmSDMA0_ATOMIC_PREOP_HI 0x342a
+#define mmSDMA0_POWER_CNTL_IDLE 0x342c
+#define mmSDMA0_PERF_REG_TYPE0 0x3477
+#define mmSDMA0_CONTEXT_REG_TYPE0 0x3478
+#define mmSDMA0_CONTEXT_REG_TYPE1 0x3479
+#define mmSDMA0_CONTEXT_REG_TYPE2 0x347a
+#define mmSDMA0_PUB_REG_TYPE0 0x347c
+#define mmSDMA0_PUB_REG_TYPE1 0x347d
+#define mmSDMA0_GFX_RB_CNTL 0x3480
+#define mmSDMA0_GFX_RB_BASE 0x3481
+#define mmSDMA0_GFX_RB_BASE_HI 0x3482
+#define mmSDMA0_GFX_RB_RPTR 0x3483
+#define mmSDMA0_GFX_RB_WPTR 0x3484
+#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486
+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487
+#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x3488
+#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x3489
+#define mmSDMA0_GFX_IB_CNTL 0x348a
+#define mmSDMA0_GFX_IB_RPTR 0x348b
+#define mmSDMA0_GFX_IB_OFFSET 0x348c
+#define mmSDMA0_GFX_IB_BASE_LO 0x348d
+#define mmSDMA0_GFX_IB_BASE_HI 0x348e
+#define mmSDMA0_GFX_IB_SIZE 0x348f
+#define mmSDMA0_GFX_SKIP_CNTL 0x3490
+#define mmSDMA0_GFX_CONTEXT_STATUS 0x3491
+#define mmSDMA0_GFX_DOORBELL 0x3492
+#define mmSDMA0_GFX_CONTEXT_CNTL 0x3493
+#define mmSDMA0_GFX_VIRTUAL_ADDR 0x34a7
+#define mmSDMA0_GFX_APE1_CNTL 0x34a8
+#define mmSDMA0_GFX_DOORBELL_LOG 0x34a9
+#define mmSDMA0_GFX_WATERMARK 0x34aa
+#define mmSDMA0_GFX_CSA_ADDR_LO 0x34ac
+#define mmSDMA0_GFX_CSA_ADDR_HI 0x34ad
+#define mmSDMA0_GFX_IB_SUB_REMAIN 0x34af
+#define mmSDMA0_GFX_PREEMPT 0x34b0
+#define mmSDMA0_GFX_DUMMY_REG 0x34b1
+#define mmSDMA0_GFX_MIDCMD_DATA0 0x34c1
+#define mmSDMA0_GFX_MIDCMD_DATA1 0x34c2
+#define mmSDMA0_GFX_MIDCMD_DATA2 0x34c3
+#define mmSDMA0_GFX_MIDCMD_DATA3 0x34c4
+#define mmSDMA0_GFX_MIDCMD_DATA4 0x34c5
+#define mmSDMA0_GFX_MIDCMD_DATA5 0x34c6
+#define mmSDMA0_GFX_MIDCMD_CNTL 0x34c7
+#define mmSDMA0_RLC0_RB_CNTL 0x3500
+#define mmSDMA0_RLC0_RB_BASE 0x3501
+#define mmSDMA0_RLC0_RB_BASE_HI 0x3502
+#define mmSDMA0_RLC0_RB_RPTR 0x3503
+#define mmSDMA0_RLC0_RB_WPTR 0x3504
+#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x3506
+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x3507
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x3508
+#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x3509
+#define mmSDMA0_RLC0_IB_CNTL 0x350a
+#define mmSDMA0_RLC0_IB_RPTR 0x350b
+#define mmSDMA0_RLC0_IB_OFFSET 0x350c
+#define mmSDMA0_RLC0_IB_BASE_LO 0x350d
+#define mmSDMA0_RLC0_IB_BASE_HI 0x350e
+#define mmSDMA0_RLC0_IB_SIZE 0x350f
+#define mmSDMA0_RLC0_SKIP_CNTL 0x3510
+#define mmSDMA0_RLC0_CONTEXT_STATUS 0x3511
+#define mmSDMA0_RLC0_DOORBELL 0x3512
+#define mmSDMA0_RLC0_VIRTUAL_ADDR 0x3527
+#define mmSDMA0_RLC0_APE1_CNTL 0x3528
+#define mmSDMA0_RLC0_DOORBELL_LOG 0x3529
+#define mmSDMA0_RLC0_WATERMARK 0x352a
+#define mmSDMA0_RLC0_CSA_ADDR_LO 0x352c
+#define mmSDMA0_RLC0_CSA_ADDR_HI 0x352d
+#define mmSDMA0_RLC0_IB_SUB_REMAIN 0x352f
+#define mmSDMA0_RLC0_PREEMPT 0x3530
+#define mmSDMA0_RLC0_DUMMY_REG 0x3531
+#define mmSDMA0_RLC0_MIDCMD_DATA0 0x3541
+#define mmSDMA0_RLC0_MIDCMD_DATA1 0x3542
+#define mmSDMA0_RLC0_MIDCMD_DATA2 0x3543
+#define mmSDMA0_RLC0_MIDCMD_DATA3 0x3544
+#define mmSDMA0_RLC0_MIDCMD_DATA4 0x3545
+#define mmSDMA0_RLC0_MIDCMD_DATA5 0x3546
+#define mmSDMA0_RLC0_MIDCMD_CNTL 0x3547
+#define mmSDMA0_RLC1_RB_CNTL 0x3580
+#define mmSDMA0_RLC1_RB_BASE 0x3581
+#define mmSDMA0_RLC1_RB_BASE_HI 0x3582
+#define mmSDMA0_RLC1_RB_RPTR 0x3583
+#define mmSDMA0_RLC1_RB_WPTR 0x3584
+#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x3585
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x3586
+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x3587
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x3588
+#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x3589
+#define mmSDMA0_RLC1_IB_CNTL 0x358a
+#define mmSDMA0_RLC1_IB_RPTR 0x358b
+#define mmSDMA0_RLC1_IB_OFFSET 0x358c
+#define mmSDMA0_RLC1_IB_BASE_LO 0x358d
+#define mmSDMA0_RLC1_IB_BASE_HI 0x358e
+#define mmSDMA0_RLC1_IB_SIZE 0x358f
+#define mmSDMA0_RLC1_SKIP_CNTL 0x3590
+#define mmSDMA0_RLC1_CONTEXT_STATUS 0x3591
+#define mmSDMA0_RLC1_DOORBELL 0x3592
+#define mmSDMA0_RLC1_VIRTUAL_ADDR 0x35a7
+#define mmSDMA0_RLC1_APE1_CNTL 0x35a8
+#define mmSDMA0_RLC1_DOORBELL_LOG 0x35a9
+#define mmSDMA0_RLC1_WATERMARK 0x35aa
+#define mmSDMA0_RLC1_CSA_ADDR_LO 0x35ac
+#define mmSDMA0_RLC1_CSA_ADDR_HI 0x35ad
+#define mmSDMA0_RLC1_IB_SUB_REMAIN 0x35af
+#define mmSDMA0_RLC1_PREEMPT 0x35b0
+#define mmSDMA0_RLC1_DUMMY_REG 0x35b1
+#define mmSDMA0_RLC1_MIDCMD_DATA0 0x35c1
+#define mmSDMA0_RLC1_MIDCMD_DATA1 0x35c2
+#define mmSDMA0_RLC1_MIDCMD_DATA2 0x35c3
+#define mmSDMA0_RLC1_MIDCMD_DATA3 0x35c4
+#define mmSDMA0_RLC1_MIDCMD_DATA4 0x35c5
+#define mmSDMA0_RLC1_MIDCMD_DATA5 0x35c6
+#define mmSDMA0_RLC1_MIDCMD_CNTL 0x35c7
+#define mmSDMA1_UCODE_ADDR 0x3600
+#define mmSDMA1_UCODE_DATA 0x3601
+#define mmSDMA1_POWER_CNTL 0x3602
+#define mmSDMA1_CLK_CTRL 0x3603
+#define mmSDMA1_CNTL 0x3604
+#define mmSDMA1_CHICKEN_BITS 0x3605
+#define mmSDMA1_TILING_CONFIG 0x3606
+#define mmSDMA1_HASH 0x3607
+#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x3609
+#define mmSDMA1_RB_RPTR_FETCH 0x360a
+#define mmSDMA1_IB_OFFSET_FETCH 0x360b
+#define mmSDMA1_PROGRAM 0x360c
+#define mmSDMA1_STATUS_REG 0x360d
+#define mmSDMA1_STATUS1_REG 0x360e
+#define mmSDMA1_RD_BURST_CNTL 0x360f
+#define mmSDMA1_PERFMON_CNTL 0x9010
+#define mmSDMA1_PERFCOUNTER0_RESULT 0x9011
+#define mmSDMA1_PERFCOUNTER1_RESULT 0x9012
+#define mmSDMA1_F32_CNTL 0x3612
+#define mmSDMA1_FREEZE 0x3613
+#define mmSDMA1_PHASE0_QUANTUM 0x3614
+#define mmSDMA1_PHASE1_QUANTUM 0x3615
+#define mmSDMA1_EDC_CONFIG 0x361a
+#define mmSDMA1_VM_CNTL 0x3620
+#define mmSDMA1_VM_CTX_LO 0x3621
+#define mmSDMA1_VM_CTX_HI 0x3622
+#define mmSDMA1_STATUS2_REG 0x3623
+#define mmSDMA1_ACTIVE_FCN_ID 0x3624
+#define mmSDMA1_VM_CTX_CNTL 0x3625
+#define mmSDMA1_VIRT_RESET_REQ 0x3626
+#define mmSDMA1_VF_ENABLE 0x3627
+#define mmSDMA1_BA_THRESHOLD 0x361b
+#define mmSDMA1_ID 0x361c
+#define mmSDMA1_VERSION 0x361d
+#define mmSDMA1_ATOMIC_CNTL 0x3628
+#define mmSDMA1_ATOMIC_PREOP_LO 0x3629
+#define mmSDMA1_ATOMIC_PREOP_HI 0x362a
+#define mmSDMA1_POWER_CNTL_IDLE 0x362c
+#define mmSDMA1_PERF_REG_TYPE0 0x3677
+#define mmSDMA1_CONTEXT_REG_TYPE0 0x3678
+#define mmSDMA1_CONTEXT_REG_TYPE1 0x3679
+#define mmSDMA1_CONTEXT_REG_TYPE2 0x367a
+#define mmSDMA1_PUB_REG_TYPE0 0x367c
+#define mmSDMA1_PUB_REG_TYPE1 0x367d
+#define mmSDMA1_GFX_RB_CNTL 0x3680
+#define mmSDMA1_GFX_RB_BASE 0x3681
+#define mmSDMA1_GFX_RB_BASE_HI 0x3682
+#define mmSDMA1_GFX_RB_RPTR 0x3683
+#define mmSDMA1_GFX_RB_WPTR 0x3684
+#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x3686
+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x3687
+#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x3688
+#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x3689
+#define mmSDMA1_GFX_IB_CNTL 0x368a
+#define mmSDMA1_GFX_IB_RPTR 0x368b
+#define mmSDMA1_GFX_IB_OFFSET 0x368c
+#define mmSDMA1_GFX_IB_BASE_LO 0x368d
+#define mmSDMA1_GFX_IB_BASE_HI 0x368e
+#define mmSDMA1_GFX_IB_SIZE 0x368f
+#define mmSDMA1_GFX_SKIP_CNTL 0x3690
+#define mmSDMA1_GFX_CONTEXT_STATUS 0x3691
+#define mmSDMA1_GFX_DOORBELL 0x3692
+#define mmSDMA1_GFX_CONTEXT_CNTL 0x3693
+#define mmSDMA1_GFX_VIRTUAL_ADDR 0x36a7
+#define mmSDMA1_GFX_APE1_CNTL 0x36a8
+#define mmSDMA1_GFX_DOORBELL_LOG 0x36a9
+#define mmSDMA1_GFX_WATERMARK 0x36aa
+#define mmSDMA1_GFX_CSA_ADDR_LO 0x36ac
+#define mmSDMA1_GFX_CSA_ADDR_HI 0x36ad
+#define mmSDMA1_GFX_IB_SUB_REMAIN 0x36af
+#define mmSDMA1_GFX_PREEMPT 0x36b0
+#define mmSDMA1_GFX_DUMMY_REG 0x36b1
+#define mmSDMA1_GFX_MIDCMD_DATA0 0x36c1
+#define mmSDMA1_GFX_MIDCMD_DATA1 0x36c2
+#define mmSDMA1_GFX_MIDCMD_DATA2 0x36c3
+#define mmSDMA1_GFX_MIDCMD_DATA3 0x36c4
+#define mmSDMA1_GFX_MIDCMD_DATA4 0x36c5
+#define mmSDMA1_GFX_MIDCMD_DATA5 0x36c6
+#define mmSDMA1_GFX_MIDCMD_CNTL 0x36c7
+#define mmSDMA1_RLC0_RB_CNTL 0x3700
+#define mmSDMA1_RLC0_RB_BASE 0x3701
+#define mmSDMA1_RLC0_RB_BASE_HI 0x3702
+#define mmSDMA1_RLC0_RB_RPTR 0x3703
+#define mmSDMA1_RLC0_RB_WPTR 0x3704
+#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x3706
+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x3707
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x3708
+#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x3709
+#define mmSDMA1_RLC0_IB_CNTL 0x370a
+#define mmSDMA1_RLC0_IB_RPTR 0x370b
+#define mmSDMA1_RLC0_IB_OFFSET 0x370c
+#define mmSDMA1_RLC0_IB_BASE_LO 0x370d
+#define mmSDMA1_RLC0_IB_BASE_HI 0x370e
+#define mmSDMA1_RLC0_IB_SIZE 0x370f
+#define mmSDMA1_RLC0_SKIP_CNTL 0x3710
+#define mmSDMA1_RLC0_CONTEXT_STATUS 0x3711
+#define mmSDMA1_RLC0_DOORBELL 0x3712
+#define mmSDMA1_RLC0_VIRTUAL_ADDR 0x3727
+#define mmSDMA1_RLC0_APE1_CNTL 0x3728
+#define mmSDMA1_RLC0_DOORBELL_LOG 0x3729
+#define mmSDMA1_RLC0_WATERMARK 0x372a
+#define mmSDMA1_RLC0_CSA_ADDR_LO 0x372c
+#define mmSDMA1_RLC0_CSA_ADDR_HI 0x372d
+#define mmSDMA1_RLC0_IB_SUB_REMAIN 0x372f
+#define mmSDMA1_RLC0_PREEMPT 0x3730
+#define mmSDMA1_RLC0_DUMMY_REG 0x3731
+#define mmSDMA1_RLC0_MIDCMD_DATA0 0x3741
+#define mmSDMA1_RLC0_MIDCMD_DATA1 0x3742
+#define mmSDMA1_RLC0_MIDCMD_DATA2 0x3743
+#define mmSDMA1_RLC0_MIDCMD_DATA3 0x3744
+#define mmSDMA1_RLC0_MIDCMD_DATA4 0x3745
+#define mmSDMA1_RLC0_MIDCMD_DATA5 0x3746
+#define mmSDMA1_RLC0_MIDCMD_CNTL 0x3747
+#define mmSDMA1_RLC1_RB_CNTL 0x3780
+#define mmSDMA1_RLC1_RB_BASE 0x3781
+#define mmSDMA1_RLC1_RB_BASE_HI 0x3782
+#define mmSDMA1_RLC1_RB_RPTR 0x3783
+#define mmSDMA1_RLC1_RB_WPTR 0x3784
+#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x3785
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x3786
+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x3787
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x3788
+#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x3789
+#define mmSDMA1_RLC1_IB_CNTL 0x378a
+#define mmSDMA1_RLC1_IB_RPTR 0x378b
+#define mmSDMA1_RLC1_IB_OFFSET 0x378c
+#define mmSDMA1_RLC1_IB_BASE_LO 0x378d
+#define mmSDMA1_RLC1_IB_BASE_HI 0x378e
+#define mmSDMA1_RLC1_IB_SIZE 0x378f
+#define mmSDMA1_RLC1_SKIP_CNTL 0x3790
+#define mmSDMA1_RLC1_CONTEXT_STATUS 0x3791
+#define mmSDMA1_RLC1_DOORBELL 0x3792
+#define mmSDMA1_RLC1_VIRTUAL_ADDR 0x37a7
+#define mmSDMA1_RLC1_APE1_CNTL 0x37a8
+#define mmSDMA1_RLC1_DOORBELL_LOG 0x37a9
+#define mmSDMA1_RLC1_WATERMARK 0x37aa
+#define mmSDMA1_RLC1_CSA_ADDR_LO 0x37ac
+#define mmSDMA1_RLC1_CSA_ADDR_HI 0x37ad
+#define mmSDMA1_RLC1_IB_SUB_REMAIN 0x37af
+#define mmSDMA1_RLC1_PREEMPT 0x37b0
+#define mmSDMA1_RLC1_DUMMY_REG 0x37b1
+#define mmSDMA1_RLC1_MIDCMD_DATA0 0x37c1
+#define mmSDMA1_RLC1_MIDCMD_DATA1 0x37c2
+#define mmSDMA1_RLC1_MIDCMD_DATA2 0x37c3
+#define mmSDMA1_RLC1_MIDCMD_DATA3 0x37c4
+#define mmSDMA1_RLC1_MIDCMD_DATA4 0x37c5
+#define mmSDMA1_RLC1_MIDCMD_DATA5 0x37c6
+#define mmSDMA1_RLC1_MIDCMD_CNTL 0x37c7
+#define mmHDP_HOST_PATH_CNTL 0xb00
+#define mmHDP_NONSURFACE_BASE 0xb01
+#define mmHDP_NONSURFACE_INFO 0xb02
+#define mmHDP_NONSURFACE_SIZE 0xb03
+#define mmHDP_NONSURF_FLAGS 0xbc9
+#define mmHDP_NONSURF_FLAGS_CLR 0xbca
+#define mmHDP_SW_SEMAPHORE 0xbcb
+#define mmHDP_DEBUG0 0xbcc
+#define mmHDP_DEBUG1 0xbcd
+#define mmHDP_LAST_SURFACE_HIT 0xbce
+#define mmHDP_TILING_CONFIG 0xbcf
+#define mmHDP_SC_MULTI_CHIP_CNTL 0xbd0
+#define mmHDP_OUTSTANDING_REQ 0xbd1
+#define mmHDP_ADDR_CONFIG 0xbd2
+#define mmHDP_MISC_CNTL 0xbd3
+#define mmHDP_MEM_POWER_LS 0xbd4
+#define mmHDP_NONSURFACE_PREFETCH 0xbd5
+#define mmHDP_MEMIO_CNTL 0xbf6
+#define mmHDP_MEMIO_ADDR 0xbf7
+#define mmHDP_MEMIO_STATUS 0xbf8
+#define mmHDP_MEMIO_WR_DATA 0xbf9
+#define mmHDP_MEMIO_RD_DATA 0xbfa
+#define mmHDP_VF_ENABLE 0xbfb
+#define mmHDP_XDP_DIRECT2HDP_FIRST 0xc00
+#define mmHDP_XDP_D2H_FLUSH 0xc01
+#define mmHDP_XDP_D2H_BAR_UPDATE 0xc02
+#define mmHDP_XDP_D2H_RSVD_3 0xc03
+#define mmHDP_XDP_D2H_RSVD_4 0xc04
+#define mmHDP_XDP_D2H_RSVD_5 0xc05
+#define mmHDP_XDP_D2H_RSVD_6 0xc06
+#define mmHDP_XDP_D2H_RSVD_7 0xc07
+#define mmHDP_XDP_D2H_RSVD_8 0xc08
+#define mmHDP_XDP_D2H_RSVD_9 0xc09
+#define mmHDP_XDP_D2H_RSVD_10 0xc0a
+#define mmHDP_XDP_D2H_RSVD_11 0xc0b
+#define mmHDP_XDP_D2H_RSVD_12 0xc0c
+#define mmHDP_XDP_D2H_RSVD_13 0xc0d
+#define mmHDP_XDP_D2H_RSVD_14 0xc0e
+#define mmHDP_XDP_D2H_RSVD_15 0xc0f
+#define mmHDP_XDP_D2H_RSVD_16 0xc10
+#define mmHDP_XDP_D2H_RSVD_17 0xc11
+#define mmHDP_XDP_D2H_RSVD_18 0xc12
+#define mmHDP_XDP_D2H_RSVD_19 0xc13
+#define mmHDP_XDP_D2H_RSVD_20 0xc14
+#define mmHDP_XDP_D2H_RSVD_21 0xc15
+#define mmHDP_XDP_D2H_RSVD_22 0xc16
+#define mmHDP_XDP_D2H_RSVD_23 0xc17
+#define mmHDP_XDP_D2H_RSVD_24 0xc18
+#define mmHDP_XDP_D2H_RSVD_25 0xc19
+#define mmHDP_XDP_D2H_RSVD_26 0xc1a
+#define mmHDP_XDP_D2H_RSVD_27 0xc1b
+#define mmHDP_XDP_D2H_RSVD_28 0xc1c
+#define mmHDP_XDP_D2H_RSVD_29 0xc1d
+#define mmHDP_XDP_D2H_RSVD_30 0xc1e
+#define mmHDP_XDP_D2H_RSVD_31 0xc1f
+#define mmHDP_XDP_D2H_RSVD_32 0xc20
+#define mmHDP_XDP_D2H_RSVD_33 0xc21
+#define mmHDP_XDP_D2H_RSVD_34 0xc22
+#define mmHDP_XDP_DIRECT2HDP_LAST 0xc23
+#define mmHDP_XDP_P2P_BAR_CFG 0xc24
+#define mmHDP_XDP_P2P_MBX_OFFSET 0xc25
+#define mmHDP_XDP_P2P_MBX_ADDR0 0xc26
+#define mmHDP_XDP_P2P_MBX_ADDR1 0xc27
+#define mmHDP_XDP_P2P_MBX_ADDR2 0xc28
+#define mmHDP_XDP_P2P_MBX_ADDR3 0xc29
+#define mmHDP_XDP_P2P_MBX_ADDR4 0xc2a
+#define mmHDP_XDP_P2P_MBX_ADDR5 0xc2b
+#define mmHDP_XDP_P2P_MBX_ADDR6 0xc2c
+#define mmHDP_XDP_HDP_MBX_MC_CFG 0xc2d
+#define mmHDP_XDP_HDP_MC_CFG 0xc2e
+#define mmHDP_XDP_HST_CFG 0xc2f
+#define mmHDP_XDP_SID_CFG 0xc30
+#define mmHDP_XDP_HDP_IPH_CFG 0xc31
+#define mmHDP_XDP_SRBM_CFG 0xc32
+#define mmHDP_XDP_CGTT_BLK_CTRL 0xc33
+#define mmHDP_XDP_P2P_BAR0 0xc34
+#define mmHDP_XDP_P2P_BAR1 0xc35
+#define mmHDP_XDP_P2P_BAR2 0xc36
+#define mmHDP_XDP_P2P_BAR3 0xc37
+#define mmHDP_XDP_P2P_BAR4 0xc38
+#define mmHDP_XDP_P2P_BAR5 0xc39
+#define mmHDP_XDP_P2P_BAR6 0xc3a
+#define mmHDP_XDP_P2P_BAR7 0xc3b
+#define mmHDP_XDP_FLUSH_ARMED_STS 0xc3c
+#define mmHDP_XDP_FLUSH_CNTR0_STS 0xc3d
+#define mmHDP_XDP_BUSY_STS 0xc3e
+#define mmHDP_XDP_STICKY 0xc3f
+#define mmHDP_XDP_CHKN 0xc40
+#define mmHDP_XDP_DBG_ADDR 0xc41
+#define mmHDP_XDP_DBG_DATA 0xc42
+#define mmHDP_XDP_DBG_MASK 0xc43
+#define mmHDP_XDP_BARS_ADDR_39_36 0xc44
+
+#endif /* OSS_3_0_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_enum.h
new file mode 100644
index 000000000000..09338d82afba
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_enum.h
@@ -0,0 +1,1497 @@
+/*
+ * OSS_3_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef OSS_3_0_ENUM_H
+#define OSS_3_0_ENUM_H
+
+typedef enum IH_CLIENT_ID {
+ DC_IH_SRC_ID_START = 0x1,
+ DC_IH_SRC_ID_END = 0x1f,
+ VGA_IH_SRC_ID_START = 0x20,
+ VGA_IH_SRC_ID_END = 0x27,
+ CAP_IH_SRC_ID_START = 0x28,
+ CAP_IH_SRC_ID_END = 0x2f,
+ VIP_IH_SRC_ID_START = 0x30,
+ VIP_IH_SRC_ID_END = 0x3f,
+ ROM_IH_SRC_ID_START = 0x40,
+ ROM_IH_SRC_ID_END = 0x5d,
+ BIF_IH_SRC_ID_START = 0x5e,
+ SAM_IH_SRC_ID_START = 0x5f,
+ SRBM_IH_SRC_ID_START = 0x60,
+ SRBM_IH_SRC_ID_END = 0x67,
+ UVD_IH_SRC_ID_START = 0x72,
+ UVD_IH_SRC_ID_END = 0x85,
+ VMC_IH_SRC_ID_START = 0x86,
+ VMC_IH_SRC_ID_END = 0x8f,
+ RLC_IH_SRC_ID_START = 0x90,
+ RLC_IH_SRC_ID_END = 0xf3,
+ PDMA_IH_SRC_ID_START = 0xf4,
+ PDMA_IH_SRC_ID_END = 0xf7,
+ CG_IH_SRC_ID_START = 0xf8,
+ CG_IH_SRC_ID_END = 0xff,
+} IH_CLIENT_ID;
+typedef enum IH_PERF_SEL {
+ IH_PERF_SEL_CYCLE = 0x0,
+ IH_PERF_SEL_IDLE = 0x1,
+ IH_PERF_SEL_INPUT_IDLE = 0x2,
+ IH_PERF_SEL_CLIENT0_IH_STALL = 0x3,
+ IH_PERF_SEL_CLIENT1_IH_STALL = 0x4,
+ IH_PERF_SEL_CLIENT2_IH_STALL = 0x5,
+ IH_PERF_SEL_CLIENT3_IH_STALL = 0x6,
+ IH_PERF_SEL_CLIENT4_IH_STALL = 0x7,
+ IH_PERF_SEL_CLIENT5_IH_STALL = 0x8,
+ IH_PERF_SEL_CLIENT6_IH_STALL = 0x9,
+ IH_PERF_SEL_CLIENT7_IH_STALL = 0xa,
+ IH_PERF_SEL_RB_IDLE = 0xb,
+ IH_PERF_SEL_RB_FULL = 0xc,
+ IH_PERF_SEL_RB_OVERFLOW = 0xd,
+ IH_PERF_SEL_RB_WPTR_WRITEBACK = 0xe,
+ IH_PERF_SEL_RB_WPTR_WRAP = 0xf,
+ IH_PERF_SEL_RB_RPTR_WRAP = 0x10,
+ IH_PERF_SEL_MC_WR_IDLE = 0x11,
+ IH_PERF_SEL_MC_WR_COUNT = 0x12,
+ IH_PERF_SEL_MC_WR_STALL = 0x13,
+ IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x14,
+ IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x15,
+ IH_PERF_SEL_BIF_RISING = 0x16,
+ IH_PERF_SEL_BIF_FALLING = 0x17,
+ IH_PERF_SEL_CLIENT8_IH_STALL = 0x18,
+ IH_PERF_SEL_CLIENT9_IH_STALL = 0x19,
+ IH_PERF_SEL_CLIENT10_IH_STALL = 0x1a,
+ IH_PERF_SEL_CLIENT11_IH_STALL = 0x1b,
+ IH_PERF_SEL_CLIENT12_IH_STALL = 0x1c,
+ IH_PERF_SEL_CLIENT13_IH_STALL = 0x1d,
+ IH_PERF_SEL_CLIENT14_IH_STALL = 0x1e,
+ IH_PERF_SEL_CLIENT15_IH_STALL = 0x1f,
+ IH_PERF_SEL_CLIENT16_IH_STALL = 0x20,
+ IH_PERF_SEL_CLIENT17_IH_STALL = 0x21,
+ IH_PERF_SEL_CLIENT18_IH_STALL = 0x22,
+ IH_PERF_SEL_CLIENT19_IH_STALL = 0x23,
+ IH_PERF_SEL_CLIENT20_IH_STALL = 0x24,
+ IH_PERF_SEL_CLIENT21_IH_STALL = 0x25,
+ IH_PERF_SEL_CLIENT22_IH_STALL = 0x26,
+ IH_PERF_SEL_RB_FULL_VF0 = 0x27,
+ IH_PERF_SEL_RB_FULL_VF1 = 0x28,
+ IH_PERF_SEL_RB_FULL_VF2 = 0x29,
+ IH_PERF_SEL_RB_FULL_VF3 = 0x2a,
+ IH_PERF_SEL_RB_FULL_VF4 = 0x2b,
+ IH_PERF_SEL_RB_FULL_VF5 = 0x2c,
+ IH_PERF_SEL_RB_FULL_VF6 = 0x2d,
+ IH_PERF_SEL_RB_FULL_VF7 = 0x2e,
+ IH_PERF_SEL_RB_FULL_VF8 = 0x2f,
+ IH_PERF_SEL_RB_FULL_VF9 = 0x30,
+ IH_PERF_SEL_RB_FULL_VF10 = 0x31,
+ IH_PERF_SEL_RB_FULL_VF11 = 0x32,
+ IH_PERF_SEL_RB_FULL_VF12 = 0x33,
+ IH_PERF_SEL_RB_FULL_VF13 = 0x34,
+ IH_PERF_SEL_RB_FULL_VF14 = 0x35,
+ IH_PERF_SEL_RB_FULL_VF15 = 0x36,
+ IH_PERF_SEL_RB_OVERFLOW_VF0 = 0x37,
+ IH_PERF_SEL_RB_OVERFLOW_VF1 = 0x38,
+ IH_PERF_SEL_RB_OVERFLOW_VF2 = 0x39,
+ IH_PERF_SEL_RB_OVERFLOW_VF3 = 0x3a,
+ IH_PERF_SEL_RB_OVERFLOW_VF4 = 0x3b,
+ IH_PERF_SEL_RB_OVERFLOW_VF5 = 0x3c,
+ IH_PERF_SEL_RB_OVERFLOW_VF6 = 0x3d,
+ IH_PERF_SEL_RB_OVERFLOW_VF7 = 0x3e,
+ IH_PERF_SEL_RB_OVERFLOW_VF8 = 0x3f,
+ IH_PERF_SEL_RB_OVERFLOW_VF9 = 0x40,
+ IH_PERF_SEL_RB_OVERFLOW_VF10 = 0x41,
+ IH_PERF_SEL_RB_OVERFLOW_VF11 = 0x42,
+ IH_PERF_SEL_RB_OVERFLOW_VF12 = 0x43,
+ IH_PERF_SEL_RB_OVERFLOW_VF13 = 0x44,
+ IH_PERF_SEL_RB_OVERFLOW_VF14 = 0x45,
+ IH_PERF_SEL_RB_OVERFLOW_VF15 = 0x46,
+ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF0 = 0x47,
+ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF1 = 0x48,
+ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF2 = 0x49,
+ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF3 = 0x4a,
+ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF4 = 0x4b,
+ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF5 = 0x4c,
+ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF6 = 0x4d,
+ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF7 = 0x4e,
+ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF8 = 0x4f,
+ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF9 = 0x50,
+ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF10 = 0x51,
+ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF11 = 0x52,
+ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF12 = 0x53,
+ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF13 = 0x54,
+ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF14 = 0x55,
+ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF15 = 0x56,
+ IH_PERF_SEL_RB_WPTR_WRAP_VF0 = 0x57,
+ IH_PERF_SEL_RB_WPTR_WRAP_VF1 = 0x58,
+ IH_PERF_SEL_RB_WPTR_WRAP_VF2 = 0x59,
+ IH_PERF_SEL_RB_WPTR_WRAP_VF3 = 0x5a,
+ IH_PERF_SEL_RB_WPTR_WRAP_VF4 = 0x5b,
+ IH_PERF_SEL_RB_WPTR_WRAP_VF5 = 0x5c,
+ IH_PERF_SEL_RB_WPTR_WRAP_VF6 = 0x5d,
+ IH_PERF_SEL_RB_WPTR_WRAP_VF7 = 0x5e,
+ IH_PERF_SEL_RB_WPTR_WRAP_VF8 = 0x5f,
+ IH_PERF_SEL_RB_WPTR_WRAP_VF9 = 0x60,
+ IH_PERF_SEL_RB_WPTR_WRAP_VF10 = 0x61,
+ IH_PERF_SEL_RB_WPTR_WRAP_VF11 = 0x62,
+ IH_PERF_SEL_RB_WPTR_WRAP_VF12 = 0x63,
+ IH_PERF_SEL_RB_WPTR_WRAP_VF13 = 0x64,
+ IH_PERF_SEL_RB_WPTR_WRAP_VF14 = 0x65,
+ IH_PERF_SEL_RB_WPTR_WRAP_VF15 = 0x66,
+ IH_PERF_SEL_RB_RPTR_WRAP_VF0 = 0x67,
+ IH_PERF_SEL_RB_RPTR_WRAP_VF1 = 0x68,
+ IH_PERF_SEL_RB_RPTR_WRAP_VF2 = 0x69,
+ IH_PERF_SEL_RB_RPTR_WRAP_VF3 = 0x6a,
+ IH_PERF_SEL_RB_RPTR_WRAP_VF4 = 0x6b,
+ IH_PERF_SEL_RB_RPTR_WRAP_VF5 = 0x6c,
+ IH_PERF_SEL_RB_RPTR_WRAP_VF6 = 0x6d,
+ IH_PERF_SEL_RB_RPTR_WRAP_VF7 = 0x6e,
+ IH_PERF_SEL_RB_RPTR_WRAP_VF8 = 0x6f,
+ IH_PERF_SEL_RB_RPTR_WRAP_VF9 = 0x70,
+ IH_PERF_SEL_RB_RPTR_WRAP_VF10 = 0x71,
+ IH_PERF_SEL_RB_RPTR_WRAP_VF11 = 0x72,
+ IH_PERF_SEL_RB_RPTR_WRAP_VF12 = 0x73,
+ IH_PERF_SEL_RB_RPTR_WRAP_VF13 = 0x74,
+ IH_PERF_SEL_RB_RPTR_WRAP_VF14 = 0x75,
+ IH_PERF_SEL_RB_RPTR_WRAP_VF15 = 0x76,
+ IH_PERF_SEL_BIF_RISING_VF0 = 0x77,
+ IH_PERF_SEL_BIF_RISING_VF1 = 0x78,
+ IH_PERF_SEL_BIF_RISING_VF2 = 0x79,
+ IH_PERF_SEL_BIF_RISING_VF3 = 0x7a,
+ IH_PERF_SEL_BIF_RISING_VF4 = 0x7b,
+ IH_PERF_SEL_BIF_RISING_VF5 = 0x7c,
+ IH_PERF_SEL_BIF_RISING_VF6 = 0x7d,
+ IH_PERF_SEL_BIF_RISING_VF7 = 0x7e,
+ IH_PERF_SEL_BIF_RISING_VF8 = 0x7f,
+ IH_PERF_SEL_BIF_RISING_VF9 = 0x80,
+ IH_PERF_SEL_BIF_RISING_VF10 = 0x81,
+ IH_PERF_SEL_BIF_RISING_VF11 = 0x82,
+ IH_PERF_SEL_BIF_RISING_VF12 = 0x83,
+ IH_PERF_SEL_BIF_RISING_VF13 = 0x84,
+ IH_PERF_SEL_BIF_RISING_VF14 = 0x85,
+ IH_PERF_SEL_BIF_RISING_VF15 = 0x86,
+ IH_PERF_SEL_BIF_FALLING_VF0 = 0x87,
+ IH_PERF_SEL_BIF_FALLING_VF1 = 0x88,
+ IH_PERF_SEL_BIF_FALLING_VF2 = 0x89,
+ IH_PERF_SEL_BIF_FALLING_VF3 = 0x8a,
+ IH_PERF_SEL_BIF_FALLING_VF4 = 0x8b,
+ IH_PERF_SEL_BIF_FALLING_VF5 = 0x8c,
+ IH_PERF_SEL_BIF_FALLING_VF6 = 0x8d,
+ IH_PERF_SEL_BIF_FALLING_VF7 = 0x8e,
+ IH_PERF_SEL_BIF_FALLING_VF8 = 0x8f,
+ IH_PERF_SEL_BIF_FALLING_VF9 = 0x90,
+ IH_PERF_SEL_BIF_FALLING_VF10 = 0x91,
+ IH_PERF_SEL_BIF_FALLING_VF11 = 0x92,
+ IH_PERF_SEL_BIF_FALLING_VF12 = 0x93,
+ IH_PERF_SEL_BIF_FALLING_VF13 = 0x94,
+ IH_PERF_SEL_BIF_FALLING_VF14 = 0x95,
+ IH_PERF_SEL_BIF_FALLING_VF15 = 0x96,
+} IH_PERF_SEL;
+typedef enum SRBM_PERFCOUNT1_SEL {
+ SRBM_PERF_SEL_COUNT = 0x0,
+ SRBM_PERF_SEL_BIF_BUSY = 0x1,
+ SRBM_PERF_SEL_SDMA0_BUSY = 0x3,
+ SRBM_PERF_SEL_IH_BUSY = 0x4,
+ SRBM_PERF_SEL_MCB_BUSY = 0x5,
+ SRBM_PERF_SEL_MCB_NON_DISPLAY_BUSY = 0x6,
+ SRBM_PERF_SEL_MCC_BUSY = 0x7,
+ SRBM_PERF_SEL_MCD_BUSY = 0x8,
+ SRBM_PERF_SEL_CHUB_BUSY = 0x9,
+ SRBM_PERF_SEL_SEM_BUSY = 0xa,
+ SRBM_PERF_SEL_UVD_BUSY = 0xb,
+ SRBM_PERF_SEL_VMC_BUSY = 0xc,
+ SRBM_PERF_SEL_ODE_BUSY = 0xd,
+ SRBM_PERF_SEL_SDMA1_BUSY = 0xe,
+ SRBM_PERF_SEL_SAMMSP_BUSY = 0xf,
+ SRBM_PERF_SEL_VCE0_BUSY = 0x10,
+ SRBM_PERF_SEL_XDMA_BUSY = 0x11,
+ SRBM_PERF_SEL_ACP_BUSY = 0x12,
+ SRBM_PERF_SEL_SDMA2_BUSY = 0x13,
+ SRBM_PERF_SEL_SDMA3_BUSY = 0x14,
+ SRBM_PERF_SEL_SAMSCP_BUSY = 0x15,
+ SRBM_PERF_SEL_VMC1_BUSY = 0x16,
+ SRBM_PERF_SEL_ISP_BUSY = 0x17,
+ SRBM_PERF_SEL_VCE1_BUSY = 0x18,
+ SRBM_PERF_SEL_GCATCL2_BUSY = 0x19,
+ SRBM_PERF_SEL_OSATCL2_BUSY = 0x1a,
+ SRBM_PERF_SEL_VP8_BUSY = 0x1b,
+} SRBM_PERFCOUNT1_SEL;
+typedef enum SYS_GRBM_GFX_INDEX_SEL {
+ GRBM_GFX_INDEX_BIF = 0x0,
+ GRBM_GFX_INDEX_SDMA0 = 0x1,
+ GRBM_GFX_INDEX_SDMA1 = 0x2,
+ RESEVERED0 = 0x3,
+ GRBM_GFX_INDEX_UVD = 0x4,
+ GRBM_GFX_INDEX_VCE0 = 0x5,
+ GRBM_GFX_INDEX_VCE1 = 0x6,
+ GRBM_GFX_INDEX_ACP = 0x7,
+ GRBM_GFX_INDEX_SMU = 0x8,
+ GRBM_GFX_INDEX_SAMMSP = 0x9,
+ GRBM_GFX_INDEX_SAMSCP = 0xa,
+ GRBM_GFX_INDEX_ISP = 0xb,
+ GRBM_GFX_INDEX_TST = 0xc,
+ GRBM_GFX_INDEX_SDMA2 = 0xd,
+ GRBM_GFX_INDEX_SDMA3 = 0xe,
+} SYS_GRBM_GFX_INDEX_SEL;
+typedef enum SRBM_GFX_CNTL_SEL {
+ SRBM_GFX_CNTL_BIF = 0x0,
+ SRBM_GFX_CNTL_SDMA0 = 0x1,
+ SRBM_GFX_CNTL_SDMA1 = 0x2,
+ SRBM_GFX_CNTL_GRBM = 0x3,
+ SRBM_GFX_CNTL_UVD = 0x4,
+ SRBM_GFX_CNTL_VCE0 = 0x5,
+ SRBM_GFX_CNTL_VCE1 = 0x6,
+ SRBM_GFX_CNTL_ACP = 0x7,
+ SRBM_GFX_CNTL_SMU = 0x8,
+ SRBM_GFX_CNTL_SAMMSP = 0x9,
+ SRBM_GFX_CNTL_SAMSCP = 0xa,
+ SRBM_GFX_CNTL_ISP = 0xb,
+ SRBM_GFX_CNTL_TST = 0xc,
+ SRBM_GFX_CNTL_SDMA2 = 0xd,
+ SRBM_GFX_CNTL_SDMA3 = 0xe,
+} SRBM_GFX_CNTL_SEL;
+typedef enum SDMA_PERF_SEL {
+ SDMA_PERF_SEL_CYCLE = 0x0,
+ SDMA_PERF_SEL_IDLE = 0x1,
+ SDMA_PERF_SEL_REG_IDLE = 0x2,
+ SDMA_PERF_SEL_RB_EMPTY = 0x3,
+ SDMA_PERF_SEL_RB_FULL = 0x4,
+ SDMA_PERF_SEL_RB_WPTR_WRAP = 0x5,
+ SDMA_PERF_SEL_RB_RPTR_WRAP = 0x6,
+ SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x7,
+ SDMA_PERF_SEL_RB_RPTR_WB = 0x8,
+ SDMA_PERF_SEL_RB_CMD_IDLE = 0x9,
+ SDMA_PERF_SEL_RB_CMD_FULL = 0xa,
+ SDMA_PERF_SEL_IB_CMD_IDLE = 0xb,
+ SDMA_PERF_SEL_IB_CMD_FULL = 0xc,
+ SDMA_PERF_SEL_EX_IDLE = 0xd,
+ SDMA_PERF_SEL_SRBM_REG_SEND = 0xe,
+ SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0xf,
+ SDMA_PERF_SEL_MC_WR_IDLE = 0x10,
+ SDMA_PERF_SEL_MC_WR_COUNT = 0x11,
+ SDMA_PERF_SEL_MC_RD_IDLE = 0x12,
+ SDMA_PERF_SEL_MC_RD_COUNT = 0x13,
+ SDMA_PERF_SEL_MC_RD_RET_STALL = 0x14,
+ SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x15,
+ SDMA_PERF_SEL_SEM_IDLE = 0x18,
+ SDMA_PERF_SEL_SEM_REQ_STALL = 0x19,
+ SDMA_PERF_SEL_SEM_REQ_COUNT = 0x1a,
+ SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x1b,
+ SDMA_PERF_SEL_SEM_RESP_FAIL = 0x1c,
+ SDMA_PERF_SEL_SEM_RESP_PASS = 0x1d,
+ SDMA_PERF_SEL_INT_IDLE = 0x1e,
+ SDMA_PERF_SEL_INT_REQ_STALL = 0x1f,
+ SDMA_PERF_SEL_INT_REQ_COUNT = 0x20,
+ SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x21,
+ SDMA_PERF_SEL_INT_RESP_RETRY = 0x22,
+ SDMA_PERF_SEL_NUM_PACKET = 0x23,
+ SDMA_PERF_SEL_CE_WREQ_IDLE = 0x25,
+ SDMA_PERF_SEL_CE_WR_IDLE = 0x26,
+ SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x27,
+ SDMA_PERF_SEL_CE_RREQ_IDLE = 0x28,
+ SDMA_PERF_SEL_CE_OUT_IDLE = 0x29,
+ SDMA_PERF_SEL_CE_IN_IDLE = 0x2a,
+ SDMA_PERF_SEL_CE_DST_IDLE = 0x2b,
+ SDMA_PERF_SEL_CE_AFIFO_FULL = 0x2e,
+ SDMA_PERF_SEL_CE_INFO_FULL = 0x31,
+ SDMA_PERF_SEL_CE_INFO1_FULL = 0x32,
+ SDMA_PERF_SEL_CE_RD_STALL = 0x33,
+ SDMA_PERF_SEL_CE_WR_STALL = 0x34,
+ SDMA_PERF_SEL_GFX_SELECT = 0x35,
+ SDMA_PERF_SEL_RLC0_SELECT = 0x36,
+ SDMA_PERF_SEL_RLC1_SELECT = 0x37,
+ SDMA_PERF_SEL_CTX_CHANGE = 0x38,
+ SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x39,
+ SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x3a,
+ SDMA_PERF_SEL_DOORBELL = 0x3b,
+ SDMA_PERF_SEL_RD_BA_RTR = 0x3c,
+ SDMA_PERF_SEL_WR_BA_RTR = 0x3d,
+} SDMA_PERF_SEL;
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0x0,
+ ENDIAN_8IN16 = 0x1,
+ ENDIAN_8IN32 = 0x2,
+ ENDIAN_8IN64 = 0x3,
+} SurfaceEndian;
+typedef enum ArrayMode {
+ ARRAY_LINEAR_GENERAL = 0x0,
+ ARRAY_LINEAR_ALIGNED = 0x1,
+ ARRAY_1D_TILED_THIN1 = 0x2,
+ ARRAY_1D_TILED_THICK = 0x3,
+ ARRAY_2D_TILED_THIN1 = 0x4,
+ ARRAY_PRT_TILED_THIN1 = 0x5,
+ ARRAY_PRT_2D_TILED_THIN1 = 0x6,
+ ARRAY_2D_TILED_THICK = 0x7,
+ ARRAY_2D_TILED_XTHICK = 0x8,
+ ARRAY_PRT_TILED_THICK = 0x9,
+ ARRAY_PRT_2D_TILED_THICK = 0xa,
+ ARRAY_PRT_3D_TILED_THIN1 = 0xb,
+ ARRAY_3D_TILED_THIN1 = 0xc,
+ ARRAY_3D_TILED_THICK = 0xd,
+ ARRAY_3D_TILED_XTHICK = 0xe,
+ ARRAY_PRT_3D_TILED_THICK = 0xf,
+} ArrayMode;
+typedef enum PipeTiling {
+ CONFIG_1_PIPE = 0x0,
+ CONFIG_2_PIPE = 0x1,
+ CONFIG_4_PIPE = 0x2,
+ CONFIG_8_PIPE = 0x3,
+} PipeTiling;
+typedef enum BankTiling {
+ CONFIG_4_BANK = 0x0,
+ CONFIG_8_BANK = 0x1,
+} BankTiling;
+typedef enum GroupInterleave {
+ CONFIG_256B_GROUP = 0x0,
+ CONFIG_512B_GROUP = 0x1,
+} GroupInterleave;
+typedef enum RowTiling {
+ CONFIG_1KB_ROW = 0x0,
+ CONFIG_2KB_ROW = 0x1,
+ CONFIG_4KB_ROW = 0x2,
+ CONFIG_8KB_ROW = 0x3,
+ CONFIG_1KB_ROW_OPT = 0x4,
+ CONFIG_2KB_ROW_OPT = 0x5,
+ CONFIG_4KB_ROW_OPT = 0x6,
+ CONFIG_8KB_ROW_OPT = 0x7,
+} RowTiling;
+typedef enum BankSwapBytes {
+ CONFIG_128B_SWAPS = 0x0,
+ CONFIG_256B_SWAPS = 0x1,
+ CONFIG_512B_SWAPS = 0x2,
+ CONFIG_1KB_SWAPS = 0x3,
+} BankSwapBytes;
+typedef enum SampleSplitBytes {
+ CONFIG_1KB_SPLIT = 0x0,
+ CONFIG_2KB_SPLIT = 0x1,
+ CONFIG_4KB_SPLIT = 0x2,
+ CONFIG_8KB_SPLIT = 0x3,
+} SampleSplitBytes;
+typedef enum NumPipes {
+ ADDR_CONFIG_1_PIPE = 0x0,
+ ADDR_CONFIG_2_PIPE = 0x1,
+ ADDR_CONFIG_4_PIPE = 0x2,
+ ADDR_CONFIG_8_PIPE = 0x3,
+} NumPipes;
+typedef enum PipeInterleaveSize {
+ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
+ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
+} PipeInterleaveSize;
+typedef enum BankInterleaveSize {
+ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
+ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
+ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
+ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
+} BankInterleaveSize;
+typedef enum NumShaderEngines {
+ ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
+ ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
+} NumShaderEngines;
+typedef enum ShaderEngineTileSize {
+ ADDR_CONFIG_SE_TILE_16 = 0x0,
+ ADDR_CONFIG_SE_TILE_32 = 0x1,
+} ShaderEngineTileSize;
+typedef enum NumGPUs {
+ ADDR_CONFIG_1_GPU = 0x0,
+ ADDR_CONFIG_2_GPU = 0x1,
+ ADDR_CONFIG_4_GPU = 0x2,
+} NumGPUs;
+typedef enum MultiGPUTileSize {
+ ADDR_CONFIG_GPU_TILE_16 = 0x0,
+ ADDR_CONFIG_GPU_TILE_32 = 0x1,
+ ADDR_CONFIG_GPU_TILE_64 = 0x2,
+ ADDR_CONFIG_GPU_TILE_128 = 0x3,
+} MultiGPUTileSize;
+typedef enum RowSize {
+ ADDR_CONFIG_1KB_ROW = 0x0,
+ ADDR_CONFIG_2KB_ROW = 0x1,
+ ADDR_CONFIG_4KB_ROW = 0x2,
+} RowSize;
+typedef enum NumLowerPipes {
+ ADDR_CONFIG_1_LOWER_PIPES = 0x0,
+ ADDR_CONFIG_2_LOWER_PIPES = 0x1,
+} NumLowerPipes;
+typedef enum DebugBlockId {
+ DBG_CLIENT_BLKID_RESERVED = 0x0,
+ DBG_CLIENT_BLKID_dbg = 0x1,
+ DBG_CLIENT_BLKID_scf2 = 0x2,
+ DBG_CLIENT_BLKID_mcd5 = 0x3,
+ DBG_CLIENT_BLKID_vmc = 0x4,
+ DBG_CLIENT_BLKID_sx30 = 0x5,
+ DBG_CLIENT_BLKID_mcd2 = 0x6,
+ DBG_CLIENT_BLKID_bci1 = 0x7,
+ DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8,
+ DBG_CLIENT_BLKID_mcc0 = 0x9,
+ DBG_CLIENT_BLKID_uvdf_0 = 0xa,
+ DBG_CLIENT_BLKID_uvdf_1 = 0xb,
+ DBG_CLIENT_BLKID_uvdf_2 = 0xc,
+ DBG_CLIENT_BLKID_uvdi_0 = 0xd,
+ DBG_CLIENT_BLKID_bci0 = 0xe,
+ DBG_CLIENT_BLKID_vcec0_0 = 0xf,
+ DBG_CLIENT_BLKID_cb100 = 0x10,
+ DBG_CLIENT_BLKID_cb001 = 0x11,
+ DBG_CLIENT_BLKID_mcd4 = 0x12,
+ DBG_CLIENT_BLKID_tmonw00 = 0x13,
+ DBG_CLIENT_BLKID_cb101 = 0x14,
+ DBG_CLIENT_BLKID_sx10 = 0x15,
+ DBG_CLIENT_BLKID_cb301 = 0x16,
+ DBG_CLIENT_BLKID_tmonw01 = 0x17,
+ DBG_CLIENT_BLKID_vcea0_0 = 0x18,
+ DBG_CLIENT_BLKID_vcea0_1 = 0x19,
+ DBG_CLIENT_BLKID_vcea0_2 = 0x1a,
+ DBG_CLIENT_BLKID_vcea0_3 = 0x1b,
+ DBG_CLIENT_BLKID_scf1 = 0x1c,
+ DBG_CLIENT_BLKID_sx20 = 0x1d,
+ DBG_CLIENT_BLKID_spim1 = 0x1e,
+ DBG_CLIENT_BLKID_pa10 = 0x1f,
+ DBG_CLIENT_BLKID_pa00 = 0x20,
+ DBG_CLIENT_BLKID_gmcon = 0x21,
+ DBG_CLIENT_BLKID_mcb = 0x22,
+ DBG_CLIENT_BLKID_vgt0 = 0x23,
+ DBG_CLIENT_BLKID_pc0 = 0x24,
+ DBG_CLIENT_BLKID_bci2 = 0x25,
+ DBG_CLIENT_BLKID_uvdb_0 = 0x26,
+ DBG_CLIENT_BLKID_spim3 = 0x27,
+ DBG_CLIENT_BLKID_cpc_0 = 0x28,
+ DBG_CLIENT_BLKID_cpc_1 = 0x29,
+ DBG_CLIENT_BLKID_uvdm_0 = 0x2a,
+ DBG_CLIENT_BLKID_uvdm_1 = 0x2b,
+ DBG_CLIENT_BLKID_uvdm_2 = 0x2c,
+ DBG_CLIENT_BLKID_uvdm_3 = 0x2d,
+ DBG_CLIENT_BLKID_cb000 = 0x2e,
+ DBG_CLIENT_BLKID_spim0 = 0x2f,
+ DBG_CLIENT_BLKID_mcc2 = 0x30,
+ DBG_CLIENT_BLKID_ds0 = 0x31,
+ DBG_CLIENT_BLKID_srbm = 0x32,
+ DBG_CLIENT_BLKID_ih = 0x33,
+ DBG_CLIENT_BLKID_sem = 0x34,
+ DBG_CLIENT_BLKID_sdma_0 = 0x35,
+ DBG_CLIENT_BLKID_sdma_1 = 0x36,
+ DBG_CLIENT_BLKID_hdp = 0x37,
+ DBG_CLIENT_BLKID_acp_0 = 0x38,
+ DBG_CLIENT_BLKID_acp_1 = 0x39,
+ DBG_CLIENT_BLKID_cb200 = 0x3a,
+ DBG_CLIENT_BLKID_scf3 = 0x3b,
+ DBG_CLIENT_BLKID_vceb1_0 = 0x3c,
+ DBG_CLIENT_BLKID_vcea1_0 = 0x3d,
+ DBG_CLIENT_BLKID_vcea1_1 = 0x3e,
+ DBG_CLIENT_BLKID_vcea1_2 = 0x3f,
+ DBG_CLIENT_BLKID_vcea1_3 = 0x40,
+ DBG_CLIENT_BLKID_bci3 = 0x41,
+ DBG_CLIENT_BLKID_mcd0 = 0x42,
+ DBG_CLIENT_BLKID_pa11 = 0x43,
+ DBG_CLIENT_BLKID_pa01 = 0x44,
+ DBG_CLIENT_BLKID_cb201 = 0x45,
+ DBG_CLIENT_BLKID_spim2 = 0x46,
+ DBG_CLIENT_BLKID_vgt2 = 0x47,
+ DBG_CLIENT_BLKID_pc2 = 0x48,
+ DBG_CLIENT_BLKID_smu_0 = 0x49,
+ DBG_CLIENT_BLKID_smu_1 = 0x4a,
+ DBG_CLIENT_BLKID_smu_2 = 0x4b,
+ DBG_CLIENT_BLKID_cb1 = 0x4c,
+ DBG_CLIENT_BLKID_ia0 = 0x4d,
+ DBG_CLIENT_BLKID_wd = 0x4e,
+ DBG_CLIENT_BLKID_ia1 = 0x4f,
+ DBG_CLIENT_BLKID_vcec1_0 = 0x50,
+ DBG_CLIENT_BLKID_scf0 = 0x51,
+ DBG_CLIENT_BLKID_vgt1 = 0x52,
+ DBG_CLIENT_BLKID_pc1 = 0x53,
+ DBG_CLIENT_BLKID_cb0 = 0x54,
+ DBG_CLIENT_BLKID_gdc_one_0 = 0x55,
+ DBG_CLIENT_BLKID_gdc_one_1 = 0x56,
+ DBG_CLIENT_BLKID_gdc_one_2 = 0x57,
+ DBG_CLIENT_BLKID_gdc_one_3 = 0x58,
+ DBG_CLIENT_BLKID_gdc_one_4 = 0x59,
+ DBG_CLIENT_BLKID_gdc_one_5 = 0x5a,
+ DBG_CLIENT_BLKID_gdc_one_6 = 0x5b,
+ DBG_CLIENT_BLKID_gdc_one_7 = 0x5c,
+ DBG_CLIENT_BLKID_gdc_one_8 = 0x5d,
+ DBG_CLIENT_BLKID_gdc_one_9 = 0x5e,
+ DBG_CLIENT_BLKID_gdc_one_10 = 0x5f,
+ DBG_CLIENT_BLKID_gdc_one_11 = 0x60,
+ DBG_CLIENT_BLKID_gdc_one_12 = 0x61,
+ DBG_CLIENT_BLKID_gdc_one_13 = 0x62,
+ DBG_CLIENT_BLKID_gdc_one_14 = 0x63,
+ DBG_CLIENT_BLKID_gdc_one_15 = 0x64,
+ DBG_CLIENT_BLKID_gdc_one_16 = 0x65,
+ DBG_CLIENT_BLKID_gdc_one_17 = 0x66,
+ DBG_CLIENT_BLKID_gdc_one_18 = 0x67,
+ DBG_CLIENT_BLKID_gdc_one_19 = 0x68,
+ DBG_CLIENT_BLKID_gdc_one_20 = 0x69,
+ DBG_CLIENT_BLKID_gdc_one_21 = 0x6a,
+ DBG_CLIENT_BLKID_gdc_one_22 = 0x6b,
+ DBG_CLIENT_BLKID_gdc_one_23 = 0x6c,
+ DBG_CLIENT_BLKID_gdc_one_24 = 0x6d,
+ DBG_CLIENT_BLKID_gdc_one_25 = 0x6e,
+ DBG_CLIENT_BLKID_gdc_one_26 = 0x6f,
+ DBG_CLIENT_BLKID_gdc_one_27 = 0x70,
+ DBG_CLIENT_BLKID_gdc_one_28 = 0x71,
+ DBG_CLIENT_BLKID_gdc_one_29 = 0x72,
+ DBG_CLIENT_BLKID_gdc_one_30 = 0x73,
+ DBG_CLIENT_BLKID_gdc_one_31 = 0x74,
+ DBG_CLIENT_BLKID_gdc_one_32 = 0x75,
+ DBG_CLIENT_BLKID_gdc_one_33 = 0x76,
+ DBG_CLIENT_BLKID_gdc_one_34 = 0x77,
+ DBG_CLIENT_BLKID_gdc_one_35 = 0x78,
+ DBG_CLIENT_BLKID_vceb0_0 = 0x79,
+ DBG_CLIENT_BLKID_vgt3 = 0x7a,
+ DBG_CLIENT_BLKID_pc3 = 0x7b,
+ DBG_CLIENT_BLKID_mcd3 = 0x7c,
+ DBG_CLIENT_BLKID_uvdu_0 = 0x7d,
+ DBG_CLIENT_BLKID_uvdu_1 = 0x7e,
+ DBG_CLIENT_BLKID_uvdu_2 = 0x7f,
+ DBG_CLIENT_BLKID_uvdu_3 = 0x80,
+ DBG_CLIENT_BLKID_uvdu_4 = 0x81,
+ DBG_CLIENT_BLKID_uvdu_5 = 0x82,
+ DBG_CLIENT_BLKID_uvdu_6 = 0x83,
+ DBG_CLIENT_BLKID_cb300 = 0x84,
+ DBG_CLIENT_BLKID_mcd1 = 0x85,
+ DBG_CLIENT_BLKID_sx00 = 0x86,
+ DBG_CLIENT_BLKID_uvdc_0 = 0x87,
+ DBG_CLIENT_BLKID_uvdc_1 = 0x88,
+ DBG_CLIENT_BLKID_mcc3 = 0x89,
+ DBG_CLIENT_BLKID_cpg_0 = 0x8a,
+ DBG_CLIENT_BLKID_cpg_1 = 0x8b,
+ DBG_CLIENT_BLKID_gck = 0x8c,
+ DBG_CLIENT_BLKID_mcc1 = 0x8d,
+ DBG_CLIENT_BLKID_cpf_0 = 0x8e,
+ DBG_CLIENT_BLKID_cpf_1 = 0x8f,
+ DBG_CLIENT_BLKID_rlc = 0x90,
+ DBG_CLIENT_BLKID_grbm = 0x91,
+ DBG_CLIENT_BLKID_sammsp = 0x92,
+ DBG_CLIENT_BLKID_dci_pg = 0x93,
+ DBG_CLIENT_BLKID_dci_0 = 0x94,
+ DBG_CLIENT_BLKID_dccg0_0 = 0x95,
+ DBG_CLIENT_BLKID_dccg0_1 = 0x96,
+ DBG_CLIENT_BLKID_dcfe01_0 = 0x97,
+ DBG_CLIENT_BLKID_dcfe02_0 = 0x98,
+ DBG_CLIENT_BLKID_dcfe03_0 = 0x99,
+ DBG_CLIENT_BLKID_dcfe04_0 = 0x9a,
+ DBG_CLIENT_BLKID_dcfe05_0 = 0x9b,
+ DBG_CLIENT_BLKID_dcfe06_0 = 0x9c,
+ DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d,
+} DebugBlockId;
+typedef enum DebugBlockId_OLD {
+ DBG_BLOCK_ID_RESERVED = 0x0,
+ DBG_BLOCK_ID_DBG = 0x1,
+ DBG_BLOCK_ID_VMC = 0x2,
+ DBG_BLOCK_ID_PDMA = 0x3,
+ DBG_BLOCK_ID_CG = 0x4,
+ DBG_BLOCK_ID_SRBM = 0x5,
+ DBG_BLOCK_ID_GRBM = 0x6,
+ DBG_BLOCK_ID_RLC = 0x7,
+ DBG_BLOCK_ID_CSC = 0x8,
+ DBG_BLOCK_ID_SEM = 0x9,
+ DBG_BLOCK_ID_IH = 0xa,
+ DBG_BLOCK_ID_SC = 0xb,
+ DBG_BLOCK_ID_SQ = 0xc,
+ DBG_BLOCK_ID_AVP = 0xd,
+ DBG_BLOCK_ID_GMCON = 0xe,
+ DBG_BLOCK_ID_SMU = 0xf,
+ DBG_BLOCK_ID_DMA0 = 0x10,
+ DBG_BLOCK_ID_DMA1 = 0x11,
+ DBG_BLOCK_ID_SPIM = 0x12,
+ DBG_BLOCK_ID_GDS = 0x13,
+ DBG_BLOCK_ID_SPIS = 0x14,
+ DBG_BLOCK_ID_UNUSED0 = 0x15,
+ DBG_BLOCK_ID_PA0 = 0x16,
+ DBG_BLOCK_ID_PA1 = 0x17,
+ DBG_BLOCK_ID_CP0 = 0x18,
+ DBG_BLOCK_ID_CP1 = 0x19,
+ DBG_BLOCK_ID_CP2 = 0x1a,
+ DBG_BLOCK_ID_UNUSED1 = 0x1b,
+ DBG_BLOCK_ID_UVDU = 0x1c,
+ DBG_BLOCK_ID_UVDM = 0x1d,
+ DBG_BLOCK_ID_VCE = 0x1e,
+ DBG_BLOCK_ID_UNUSED2 = 0x1f,
+ DBG_BLOCK_ID_VGT0 = 0x20,
+ DBG_BLOCK_ID_VGT1 = 0x21,
+ DBG_BLOCK_ID_IA = 0x22,
+ DBG_BLOCK_ID_UNUSED3 = 0x23,
+ DBG_BLOCK_ID_SCT0 = 0x24,
+ DBG_BLOCK_ID_SCT1 = 0x25,
+ DBG_BLOCK_ID_SPM0 = 0x26,
+ DBG_BLOCK_ID_SPM1 = 0x27,
+ DBG_BLOCK_ID_TCAA = 0x28,
+ DBG_BLOCK_ID_TCAB = 0x29,
+ DBG_BLOCK_ID_TCCA = 0x2a,
+ DBG_BLOCK_ID_TCCB = 0x2b,
+ DBG_BLOCK_ID_MCC0 = 0x2c,
+ DBG_BLOCK_ID_MCC1 = 0x2d,
+ DBG_BLOCK_ID_MCC2 = 0x2e,
+ DBG_BLOCK_ID_MCC3 = 0x2f,
+ DBG_BLOCK_ID_SX0 = 0x30,
+ DBG_BLOCK_ID_SX1 = 0x31,
+ DBG_BLOCK_ID_SX2 = 0x32,
+ DBG_BLOCK_ID_SX3 = 0x33,
+ DBG_BLOCK_ID_UNUSED4 = 0x34,
+ DBG_BLOCK_ID_UNUSED5 = 0x35,
+ DBG_BLOCK_ID_UNUSED6 = 0x36,
+ DBG_BLOCK_ID_UNUSED7 = 0x37,
+ DBG_BLOCK_ID_PC0 = 0x38,
+ DBG_BLOCK_ID_PC1 = 0x39,
+ DBG_BLOCK_ID_UNUSED8 = 0x3a,
+ DBG_BLOCK_ID_UNUSED9 = 0x3b,
+ DBG_BLOCK_ID_UNUSED10 = 0x3c,
+ DBG_BLOCK_ID_UNUSED11 = 0x3d,
+ DBG_BLOCK_ID_MCB = 0x3e,
+ DBG_BLOCK_ID_UNUSED12 = 0x3f,
+ DBG_BLOCK_ID_SCB0 = 0x40,
+ DBG_BLOCK_ID_SCB1 = 0x41,
+ DBG_BLOCK_ID_UNUSED13 = 0x42,
+ DBG_BLOCK_ID_UNUSED14 = 0x43,
+ DBG_BLOCK_ID_SCF0 = 0x44,
+ DBG_BLOCK_ID_SCF1 = 0x45,
+ DBG_BLOCK_ID_UNUSED15 = 0x46,
+ DBG_BLOCK_ID_UNUSED16 = 0x47,
+ DBG_BLOCK_ID_BCI0 = 0x48,
+ DBG_BLOCK_ID_BCI1 = 0x49,
+ DBG_BLOCK_ID_BCI2 = 0x4a,
+ DBG_BLOCK_ID_BCI3 = 0x4b,
+ DBG_BLOCK_ID_UNUSED17 = 0x4c,
+ DBG_BLOCK_ID_UNUSED18 = 0x4d,
+ DBG_BLOCK_ID_UNUSED19 = 0x4e,
+ DBG_BLOCK_ID_UNUSED20 = 0x4f,
+ DBG_BLOCK_ID_CB00 = 0x50,
+ DBG_BLOCK_ID_CB01 = 0x51,
+ DBG_BLOCK_ID_CB02 = 0x52,
+ DBG_BLOCK_ID_CB03 = 0x53,
+ DBG_BLOCK_ID_CB04 = 0x54,
+ DBG_BLOCK_ID_UNUSED21 = 0x55,
+ DBG_BLOCK_ID_UNUSED22 = 0x56,
+ DBG_BLOCK_ID_UNUSED23 = 0x57,
+ DBG_BLOCK_ID_CB10 = 0x58,
+ DBG_BLOCK_ID_CB11 = 0x59,
+ DBG_BLOCK_ID_CB12 = 0x5a,
+ DBG_BLOCK_ID_CB13 = 0x5b,
+ DBG_BLOCK_ID_CB14 = 0x5c,
+ DBG_BLOCK_ID_UNUSED24 = 0x5d,
+ DBG_BLOCK_ID_UNUSED25 = 0x5e,
+ DBG_BLOCK_ID_UNUSED26 = 0x5f,
+ DBG_BLOCK_ID_TCP0 = 0x60,
+ DBG_BLOCK_ID_TCP1 = 0x61,
+ DBG_BLOCK_ID_TCP2 = 0x62,
+ DBG_BLOCK_ID_TCP3 = 0x63,
+ DBG_BLOCK_ID_TCP4 = 0x64,
+ DBG_BLOCK_ID_TCP5 = 0x65,
+ DBG_BLOCK_ID_TCP6 = 0x66,
+ DBG_BLOCK_ID_TCP7 = 0x67,
+ DBG_BLOCK_ID_TCP8 = 0x68,
+ DBG_BLOCK_ID_TCP9 = 0x69,
+ DBG_BLOCK_ID_TCP10 = 0x6a,
+ DBG_BLOCK_ID_TCP11 = 0x6b,
+ DBG_BLOCK_ID_TCP12 = 0x6c,
+ DBG_BLOCK_ID_TCP13 = 0x6d,
+ DBG_BLOCK_ID_TCP14 = 0x6e,
+ DBG_BLOCK_ID_TCP15 = 0x6f,
+ DBG_BLOCK_ID_TCP16 = 0x70,
+ DBG_BLOCK_ID_TCP17 = 0x71,
+ DBG_BLOCK_ID_TCP18 = 0x72,
+ DBG_BLOCK_ID_TCP19 = 0x73,
+ DBG_BLOCK_ID_TCP20 = 0x74,
+ DBG_BLOCK_ID_TCP21 = 0x75,
+ DBG_BLOCK_ID_TCP22 = 0x76,
+ DBG_BLOCK_ID_TCP23 = 0x77,
+ DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
+ DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
+ DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
+ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
+ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
+ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
+ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
+ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
+ DBG_BLOCK_ID_DB00 = 0x80,
+ DBG_BLOCK_ID_DB01 = 0x81,
+ DBG_BLOCK_ID_DB02 = 0x82,
+ DBG_BLOCK_ID_DB03 = 0x83,
+ DBG_BLOCK_ID_DB04 = 0x84,
+ DBG_BLOCK_ID_UNUSED27 = 0x85,
+ DBG_BLOCK_ID_UNUSED28 = 0x86,
+ DBG_BLOCK_ID_UNUSED29 = 0x87,
+ DBG_BLOCK_ID_DB10 = 0x88,
+ DBG_BLOCK_ID_DB11 = 0x89,
+ DBG_BLOCK_ID_DB12 = 0x8a,
+ DBG_BLOCK_ID_DB13 = 0x8b,
+ DBG_BLOCK_ID_DB14 = 0x8c,
+ DBG_BLOCK_ID_UNUSED30 = 0x8d,
+ DBG_BLOCK_ID_UNUSED31 = 0x8e,
+ DBG_BLOCK_ID_UNUSED32 = 0x8f,
+ DBG_BLOCK_ID_TCC0 = 0x90,
+ DBG_BLOCK_ID_TCC1 = 0x91,
+ DBG_BLOCK_ID_TCC2 = 0x92,
+ DBG_BLOCK_ID_TCC3 = 0x93,
+ DBG_BLOCK_ID_TCC4 = 0x94,
+ DBG_BLOCK_ID_TCC5 = 0x95,
+ DBG_BLOCK_ID_TCC6 = 0x96,
+ DBG_BLOCK_ID_TCC7 = 0x97,
+ DBG_BLOCK_ID_SPS00 = 0x98,
+ DBG_BLOCK_ID_SPS01 = 0x99,
+ DBG_BLOCK_ID_SPS02 = 0x9a,
+ DBG_BLOCK_ID_SPS10 = 0x9b,
+ DBG_BLOCK_ID_SPS11 = 0x9c,
+ DBG_BLOCK_ID_SPS12 = 0x9d,
+ DBG_BLOCK_ID_UNUSED33 = 0x9e,
+ DBG_BLOCK_ID_UNUSED34 = 0x9f,
+ DBG_BLOCK_ID_TA00 = 0xa0,
+ DBG_BLOCK_ID_TA01 = 0xa1,
+ DBG_BLOCK_ID_TA02 = 0xa2,
+ DBG_BLOCK_ID_TA03 = 0xa3,
+ DBG_BLOCK_ID_TA04 = 0xa4,
+ DBG_BLOCK_ID_TA05 = 0xa5,
+ DBG_BLOCK_ID_TA06 = 0xa6,
+ DBG_BLOCK_ID_TA07 = 0xa7,
+ DBG_BLOCK_ID_TA08 = 0xa8,
+ DBG_BLOCK_ID_TA09 = 0xa9,
+ DBG_BLOCK_ID_TA0A = 0xaa,
+ DBG_BLOCK_ID_TA0B = 0xab,
+ DBG_BLOCK_ID_UNUSED35 = 0xac,
+ DBG_BLOCK_ID_UNUSED36 = 0xad,
+ DBG_BLOCK_ID_UNUSED37 = 0xae,
+ DBG_BLOCK_ID_UNUSED38 = 0xaf,
+ DBG_BLOCK_ID_TA10 = 0xb0,
+ DBG_BLOCK_ID_TA11 = 0xb1,
+ DBG_BLOCK_ID_TA12 = 0xb2,
+ DBG_BLOCK_ID_TA13 = 0xb3,
+ DBG_BLOCK_ID_TA14 = 0xb4,
+ DBG_BLOCK_ID_TA15 = 0xb5,
+ DBG_BLOCK_ID_TA16 = 0xb6,
+ DBG_BLOCK_ID_TA17 = 0xb7,
+ DBG_BLOCK_ID_TA18 = 0xb8,
+ DBG_BLOCK_ID_TA19 = 0xb9,
+ DBG_BLOCK_ID_TA1A = 0xba,
+ DBG_BLOCK_ID_TA1B = 0xbb,
+ DBG_BLOCK_ID_UNUSED39 = 0xbc,
+ DBG_BLOCK_ID_UNUSED40 = 0xbd,
+ DBG_BLOCK_ID_UNUSED41 = 0xbe,
+ DBG_BLOCK_ID_UNUSED42 = 0xbf,
+ DBG_BLOCK_ID_TD00 = 0xc0,
+ DBG_BLOCK_ID_TD01 = 0xc1,
+ DBG_BLOCK_ID_TD02 = 0xc2,
+ DBG_BLOCK_ID_TD03 = 0xc3,
+ DBG_BLOCK_ID_TD04 = 0xc4,
+ DBG_BLOCK_ID_TD05 = 0xc5,
+ DBG_BLOCK_ID_TD06 = 0xc6,
+ DBG_BLOCK_ID_TD07 = 0xc7,
+ DBG_BLOCK_ID_TD08 = 0xc8,
+ DBG_BLOCK_ID_TD09 = 0xc9,
+ DBG_BLOCK_ID_TD0A = 0xca,
+ DBG_BLOCK_ID_TD0B = 0xcb,
+ DBG_BLOCK_ID_UNUSED43 = 0xcc,
+ DBG_BLOCK_ID_UNUSED44 = 0xcd,
+ DBG_BLOCK_ID_UNUSED45 = 0xce,
+ DBG_BLOCK_ID_UNUSED46 = 0xcf,
+ DBG_BLOCK_ID_TD10 = 0xd0,
+ DBG_BLOCK_ID_TD11 = 0xd1,
+ DBG_BLOCK_ID_TD12 = 0xd2,
+ DBG_BLOCK_ID_TD13 = 0xd3,
+ DBG_BLOCK_ID_TD14 = 0xd4,
+ DBG_BLOCK_ID_TD15 = 0xd5,
+ DBG_BLOCK_ID_TD16 = 0xd6,
+ DBG_BLOCK_ID_TD17 = 0xd7,
+ DBG_BLOCK_ID_TD18 = 0xd8,
+ DBG_BLOCK_ID_TD19 = 0xd9,
+ DBG_BLOCK_ID_TD1A = 0xda,
+ DBG_BLOCK_ID_TD1B = 0xdb,
+ DBG_BLOCK_ID_UNUSED47 = 0xdc,
+ DBG_BLOCK_ID_UNUSED48 = 0xdd,
+ DBG_BLOCK_ID_UNUSED49 = 0xde,
+ DBG_BLOCK_ID_UNUSED50 = 0xdf,
+ DBG_BLOCK_ID_MCD0 = 0xe0,
+ DBG_BLOCK_ID_MCD1 = 0xe1,
+ DBG_BLOCK_ID_MCD2 = 0xe2,
+ DBG_BLOCK_ID_MCD3 = 0xe3,
+ DBG_BLOCK_ID_MCD4 = 0xe4,
+ DBG_BLOCK_ID_MCD5 = 0xe5,
+ DBG_BLOCK_ID_UNUSED51 = 0xe6,
+ DBG_BLOCK_ID_UNUSED52 = 0xe7,
+} DebugBlockId_OLD;
+typedef enum DebugBlockId_BY2 {
+ DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
+ DBG_BLOCK_ID_VMC_BY2 = 0x1,
+ DBG_BLOCK_ID_CG_BY2 = 0x2,
+ DBG_BLOCK_ID_GRBM_BY2 = 0x3,
+ DBG_BLOCK_ID_CSC_BY2 = 0x4,
+ DBG_BLOCK_ID_IH_BY2 = 0x5,
+ DBG_BLOCK_ID_SQ_BY2 = 0x6,
+ DBG_BLOCK_ID_GMCON_BY2 = 0x7,
+ DBG_BLOCK_ID_DMA0_BY2 = 0x8,
+ DBG_BLOCK_ID_SPIM_BY2 = 0x9,
+ DBG_BLOCK_ID_SPIS_BY2 = 0xa,
+ DBG_BLOCK_ID_PA0_BY2 = 0xb,
+ DBG_BLOCK_ID_CP0_BY2 = 0xc,
+ DBG_BLOCK_ID_CP2_BY2 = 0xd,
+ DBG_BLOCK_ID_UVDU_BY2 = 0xe,
+ DBG_BLOCK_ID_VCE_BY2 = 0xf,
+ DBG_BLOCK_ID_VGT0_BY2 = 0x10,
+ DBG_BLOCK_ID_IA_BY2 = 0x11,
+ DBG_BLOCK_ID_SCT0_BY2 = 0x12,
+ DBG_BLOCK_ID_SPM0_BY2 = 0x13,
+ DBG_BLOCK_ID_TCAA_BY2 = 0x14,
+ DBG_BLOCK_ID_TCCA_BY2 = 0x15,
+ DBG_BLOCK_ID_MCC0_BY2 = 0x16,
+ DBG_BLOCK_ID_MCC2_BY2 = 0x17,
+ DBG_BLOCK_ID_SX0_BY2 = 0x18,
+ DBG_BLOCK_ID_SX2_BY2 = 0x19,
+ DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
+ DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
+ DBG_BLOCK_ID_PC0_BY2 = 0x1c,
+ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
+ DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
+ DBG_BLOCK_ID_MCB_BY2 = 0x1f,
+ DBG_BLOCK_ID_SCB0_BY2 = 0x20,
+ DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
+ DBG_BLOCK_ID_SCF0_BY2 = 0x22,
+ DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
+ DBG_BLOCK_ID_BCI0_BY2 = 0x24,
+ DBG_BLOCK_ID_BCI2_BY2 = 0x25,
+ DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
+ DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
+ DBG_BLOCK_ID_CB00_BY2 = 0x28,
+ DBG_BLOCK_ID_CB02_BY2 = 0x29,
+ DBG_BLOCK_ID_CB04_BY2 = 0x2a,
+ DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
+ DBG_BLOCK_ID_CB10_BY2 = 0x2c,
+ DBG_BLOCK_ID_CB12_BY2 = 0x2d,
+ DBG_BLOCK_ID_CB14_BY2 = 0x2e,
+ DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
+ DBG_BLOCK_ID_TCP0_BY2 = 0x30,
+ DBG_BLOCK_ID_TCP2_BY2 = 0x31,
+ DBG_BLOCK_ID_TCP4_BY2 = 0x32,
+ DBG_BLOCK_ID_TCP6_BY2 = 0x33,
+ DBG_BLOCK_ID_TCP8_BY2 = 0x34,
+ DBG_BLOCK_ID_TCP10_BY2 = 0x35,
+ DBG_BLOCK_ID_TCP12_BY2 = 0x36,
+ DBG_BLOCK_ID_TCP14_BY2 = 0x37,
+ DBG_BLOCK_ID_TCP16_BY2 = 0x38,
+ DBG_BLOCK_ID_TCP18_BY2 = 0x39,
+ DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
+ DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
+ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
+ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
+ DBG_BLOCK_ID_DB00_BY2 = 0x40,
+ DBG_BLOCK_ID_DB02_BY2 = 0x41,
+ DBG_BLOCK_ID_DB04_BY2 = 0x42,
+ DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
+ DBG_BLOCK_ID_DB10_BY2 = 0x44,
+ DBG_BLOCK_ID_DB12_BY2 = 0x45,
+ DBG_BLOCK_ID_DB14_BY2 = 0x46,
+ DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
+ DBG_BLOCK_ID_TCC0_BY2 = 0x48,
+ DBG_BLOCK_ID_TCC2_BY2 = 0x49,
+ DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
+ DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
+ DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
+ DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
+ DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
+ DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
+ DBG_BLOCK_ID_TA00_BY2 = 0x50,
+ DBG_BLOCK_ID_TA02_BY2 = 0x51,
+ DBG_BLOCK_ID_TA04_BY2 = 0x52,
+ DBG_BLOCK_ID_TA06_BY2 = 0x53,
+ DBG_BLOCK_ID_TA08_BY2 = 0x54,
+ DBG_BLOCK_ID_TA0A_BY2 = 0x55,
+ DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
+ DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
+ DBG_BLOCK_ID_TA10_BY2 = 0x58,
+ DBG_BLOCK_ID_TA12_BY2 = 0x59,
+ DBG_BLOCK_ID_TA14_BY2 = 0x5a,
+ DBG_BLOCK_ID_TA16_BY2 = 0x5b,
+ DBG_BLOCK_ID_TA18_BY2 = 0x5c,
+ DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
+ DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
+ DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
+ DBG_BLOCK_ID_TD00_BY2 = 0x60,
+ DBG_BLOCK_ID_TD02_BY2 = 0x61,
+ DBG_BLOCK_ID_TD04_BY2 = 0x62,
+ DBG_BLOCK_ID_TD06_BY2 = 0x63,
+ DBG_BLOCK_ID_TD08_BY2 = 0x64,
+ DBG_BLOCK_ID_TD0A_BY2 = 0x65,
+ DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
+ DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
+ DBG_BLOCK_ID_TD10_BY2 = 0x68,
+ DBG_BLOCK_ID_TD12_BY2 = 0x69,
+ DBG_BLOCK_ID_TD14_BY2 = 0x6a,
+ DBG_BLOCK_ID_TD16_BY2 = 0x6b,
+ DBG_BLOCK_ID_TD18_BY2 = 0x6c,
+ DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
+ DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
+ DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
+ DBG_BLOCK_ID_MCD0_BY2 = 0x70,
+ DBG_BLOCK_ID_MCD2_BY2 = 0x71,
+ DBG_BLOCK_ID_MCD4_BY2 = 0x72,
+ DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
+} DebugBlockId_BY2;
+typedef enum DebugBlockId_BY4 {
+ DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
+ DBG_BLOCK_ID_CG_BY4 = 0x1,
+ DBG_BLOCK_ID_CSC_BY4 = 0x2,
+ DBG_BLOCK_ID_SQ_BY4 = 0x3,
+ DBG_BLOCK_ID_DMA0_BY4 = 0x4,
+ DBG_BLOCK_ID_SPIS_BY4 = 0x5,
+ DBG_BLOCK_ID_CP0_BY4 = 0x6,
+ DBG_BLOCK_ID_UVDU_BY4 = 0x7,
+ DBG_BLOCK_ID_VGT0_BY4 = 0x8,
+ DBG_BLOCK_ID_SCT0_BY4 = 0x9,
+ DBG_BLOCK_ID_TCAA_BY4 = 0xa,
+ DBG_BLOCK_ID_MCC0_BY4 = 0xb,
+ DBG_BLOCK_ID_SX0_BY4 = 0xc,
+ DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
+ DBG_BLOCK_ID_PC0_BY4 = 0xe,
+ DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
+ DBG_BLOCK_ID_SCB0_BY4 = 0x10,
+ DBG_BLOCK_ID_SCF0_BY4 = 0x11,
+ DBG_BLOCK_ID_BCI0_BY4 = 0x12,
+ DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
+ DBG_BLOCK_ID_CB00_BY4 = 0x14,
+ DBG_BLOCK_ID_CB04_BY4 = 0x15,
+ DBG_BLOCK_ID_CB10_BY4 = 0x16,
+ DBG_BLOCK_ID_CB14_BY4 = 0x17,
+ DBG_BLOCK_ID_TCP0_BY4 = 0x18,
+ DBG_BLOCK_ID_TCP4_BY4 = 0x19,
+ DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
+ DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
+ DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
+ DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
+ DBG_BLOCK_ID_DB_BY4 = 0x20,
+ DBG_BLOCK_ID_DB04_BY4 = 0x21,
+ DBG_BLOCK_ID_DB10_BY4 = 0x22,
+ DBG_BLOCK_ID_DB14_BY4 = 0x23,
+ DBG_BLOCK_ID_TCC0_BY4 = 0x24,
+ DBG_BLOCK_ID_TCC4_BY4 = 0x25,
+ DBG_BLOCK_ID_SPS00_BY4 = 0x26,
+ DBG_BLOCK_ID_SPS11_BY4 = 0x27,
+ DBG_BLOCK_ID_TA00_BY4 = 0x28,
+ DBG_BLOCK_ID_TA04_BY4 = 0x29,
+ DBG_BLOCK_ID_TA08_BY4 = 0x2a,
+ DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
+ DBG_BLOCK_ID_TA10_BY4 = 0x2c,
+ DBG_BLOCK_ID_TA14_BY4 = 0x2d,
+ DBG_BLOCK_ID_TA18_BY4 = 0x2e,
+ DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
+ DBG_BLOCK_ID_TD00_BY4 = 0x30,
+ DBG_BLOCK_ID_TD04_BY4 = 0x31,
+ DBG_BLOCK_ID_TD08_BY4 = 0x32,
+ DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
+ DBG_BLOCK_ID_TD10_BY4 = 0x34,
+ DBG_BLOCK_ID_TD14_BY4 = 0x35,
+ DBG_BLOCK_ID_TD18_BY4 = 0x36,
+ DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
+ DBG_BLOCK_ID_MCD0_BY4 = 0x38,
+ DBG_BLOCK_ID_MCD4_BY4 = 0x39,
+} DebugBlockId_BY4;
+typedef enum DebugBlockId_BY8 {
+ DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
+ DBG_BLOCK_ID_CSC_BY8 = 0x1,
+ DBG_BLOCK_ID_DMA0_BY8 = 0x2,
+ DBG_BLOCK_ID_CP0_BY8 = 0x3,
+ DBG_BLOCK_ID_VGT0_BY8 = 0x4,
+ DBG_BLOCK_ID_TCAA_BY8 = 0x5,
+ DBG_BLOCK_ID_SX0_BY8 = 0x6,
+ DBG_BLOCK_ID_PC0_BY8 = 0x7,
+ DBG_BLOCK_ID_SCB0_BY8 = 0x8,
+ DBG_BLOCK_ID_BCI0_BY8 = 0x9,
+ DBG_BLOCK_ID_CB00_BY8 = 0xa,
+ DBG_BLOCK_ID_CB10_BY8 = 0xb,
+ DBG_BLOCK_ID_TCP0_BY8 = 0xc,
+ DBG_BLOCK_ID_TCP8_BY8 = 0xd,
+ DBG_BLOCK_ID_TCP16_BY8 = 0xe,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
+ DBG_BLOCK_ID_DB00_BY8 = 0x10,
+ DBG_BLOCK_ID_DB10_BY8 = 0x11,
+ DBG_BLOCK_ID_TCC0_BY8 = 0x12,
+ DBG_BLOCK_ID_SPS00_BY8 = 0x13,
+ DBG_BLOCK_ID_TA00_BY8 = 0x14,
+ DBG_BLOCK_ID_TA08_BY8 = 0x15,
+ DBG_BLOCK_ID_TA10_BY8 = 0x16,
+ DBG_BLOCK_ID_TA18_BY8 = 0x17,
+ DBG_BLOCK_ID_TD00_BY8 = 0x18,
+ DBG_BLOCK_ID_TD08_BY8 = 0x19,
+ DBG_BLOCK_ID_TD10_BY8 = 0x1a,
+ DBG_BLOCK_ID_TD18_BY8 = 0x1b,
+ DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
+} DebugBlockId_BY8;
+typedef enum DebugBlockId_BY16 {
+ DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
+ DBG_BLOCK_ID_DMA0_BY16 = 0x1,
+ DBG_BLOCK_ID_VGT0_BY16 = 0x2,
+ DBG_BLOCK_ID_SX0_BY16 = 0x3,
+ DBG_BLOCK_ID_SCB0_BY16 = 0x4,
+ DBG_BLOCK_ID_CB00_BY16 = 0x5,
+ DBG_BLOCK_ID_TCP0_BY16 = 0x6,
+ DBG_BLOCK_ID_TCP16_BY16 = 0x7,
+ DBG_BLOCK_ID_DB00_BY16 = 0x8,
+ DBG_BLOCK_ID_TCC0_BY16 = 0x9,
+ DBG_BLOCK_ID_TA00_BY16 = 0xa,
+ DBG_BLOCK_ID_TA10_BY16 = 0xb,
+ DBG_BLOCK_ID_TD00_BY16 = 0xc,
+ DBG_BLOCK_ID_TD10_BY16 = 0xd,
+ DBG_BLOCK_ID_MCD0_BY16 = 0xe,
+} DebugBlockId_BY16;
+typedef enum ColorTransform {
+ DCC_CT_AUTO = 0x0,
+ DCC_CT_NONE = 0x1,
+ ABGR_TO_A_BG_G_RB = 0x2,
+ BGRA_TO_BG_G_RB_A = 0x3,
+} ColorTransform;
+typedef enum CompareRef {
+ REF_NEVER = 0x0,
+ REF_LESS = 0x1,
+ REF_EQUAL = 0x2,
+ REF_LEQUAL = 0x3,
+ REF_GREATER = 0x4,
+ REF_NOTEQUAL = 0x5,
+ REF_GEQUAL = 0x6,
+ REF_ALWAYS = 0x7,
+} CompareRef;
+typedef enum ReadSize {
+ READ_256_BITS = 0x0,
+ READ_512_BITS = 0x1,
+} ReadSize;
+typedef enum DepthFormat {
+ DEPTH_INVALID = 0x0,
+ DEPTH_16 = 0x1,
+ DEPTH_X8_24 = 0x2,
+ DEPTH_8_24 = 0x3,
+ DEPTH_X8_24_FLOAT = 0x4,
+ DEPTH_8_24_FLOAT = 0x5,
+ DEPTH_32_FLOAT = 0x6,
+ DEPTH_X24_8_32_FLOAT = 0x7,
+} DepthFormat;
+typedef enum ZFormat {
+ Z_INVALID = 0x0,
+ Z_16 = 0x1,
+ Z_24 = 0x2,
+ Z_32_FLOAT = 0x3,
+} ZFormat;
+typedef enum StencilFormat {
+ STENCIL_INVALID = 0x0,
+ STENCIL_8 = 0x1,
+} StencilFormat;
+typedef enum CmaskMode {
+ CMASK_CLEAR_NONE = 0x0,
+ CMASK_CLEAR_ONE = 0x1,
+ CMASK_CLEAR_ALL = 0x2,
+ CMASK_ANY_EXPANDED = 0x3,
+ CMASK_ALPHA0_FRAG1 = 0x4,
+ CMASK_ALPHA0_FRAG2 = 0x5,
+ CMASK_ALPHA0_FRAG4 = 0x6,
+ CMASK_ALPHA0_FRAGS = 0x7,
+ CMASK_ALPHA1_FRAG1 = 0x8,
+ CMASK_ALPHA1_FRAG2 = 0x9,
+ CMASK_ALPHA1_FRAG4 = 0xa,
+ CMASK_ALPHA1_FRAGS = 0xb,
+ CMASK_ALPHAX_FRAG1 = 0xc,
+ CMASK_ALPHAX_FRAG2 = 0xd,
+ CMASK_ALPHAX_FRAG4 = 0xe,
+ CMASK_ALPHAX_FRAGS = 0xf,
+} CmaskMode;
+typedef enum QuadExportFormat {
+ EXPORT_UNUSED = 0x0,
+ EXPORT_32_R = 0x1,
+ EXPORT_32_GR = 0x2,
+ EXPORT_32_AR = 0x3,
+ EXPORT_FP16_ABGR = 0x4,
+ EXPORT_UNSIGNED16_ABGR = 0x5,
+ EXPORT_SIGNED16_ABGR = 0x6,
+ EXPORT_32_ABGR = 0x7,
+} QuadExportFormat;
+typedef enum QuadExportFormatOld {
+ EXPORT_4P_32BPC_ABGR = 0x0,
+ EXPORT_4P_16BPC_ABGR = 0x1,
+ EXPORT_4P_32BPC_GR = 0x2,
+ EXPORT_4P_32BPC_AR = 0x3,
+ EXPORT_2P_32BPC_ABGR = 0x4,
+ EXPORT_8P_32BPC_R = 0x5,
+} QuadExportFormatOld;
+typedef enum ColorFormat {
+ COLOR_INVALID = 0x0,
+ COLOR_8 = 0x1,
+ COLOR_16 = 0x2,
+ COLOR_8_8 = 0x3,
+ COLOR_32 = 0x4,
+ COLOR_16_16 = 0x5,
+ COLOR_10_11_11 = 0x6,
+ COLOR_11_11_10 = 0x7,
+ COLOR_10_10_10_2 = 0x8,
+ COLOR_2_10_10_10 = 0x9,
+ COLOR_8_8_8_8 = 0xa,
+ COLOR_32_32 = 0xb,
+ COLOR_16_16_16_16 = 0xc,
+ COLOR_RESERVED_13 = 0xd,
+ COLOR_32_32_32_32 = 0xe,
+ COLOR_RESERVED_15 = 0xf,
+ COLOR_5_6_5 = 0x10,
+ COLOR_1_5_5_5 = 0x11,
+ COLOR_5_5_5_1 = 0x12,
+ COLOR_4_4_4_4 = 0x13,
+ COLOR_8_24 = 0x14,
+ COLOR_24_8 = 0x15,
+ COLOR_X24_8_32_FLOAT = 0x16,
+ COLOR_RESERVED_23 = 0x17,
+} ColorFormat;
+typedef enum SurfaceFormat {
+ FMT_INVALID = 0x0,
+ FMT_8 = 0x1,
+ FMT_16 = 0x2,
+ FMT_8_8 = 0x3,
+ FMT_32 = 0x4,
+ FMT_16_16 = 0x5,
+ FMT_10_11_11 = 0x6,
+ FMT_11_11_10 = 0x7,
+ FMT_10_10_10_2 = 0x8,
+ FMT_2_10_10_10 = 0x9,
+ FMT_8_8_8_8 = 0xa,
+ FMT_32_32 = 0xb,
+ FMT_16_16_16_16 = 0xc,
+ FMT_32_32_32 = 0xd,
+ FMT_32_32_32_32 = 0xe,
+ FMT_RESERVED_4 = 0xf,
+ FMT_5_6_5 = 0x10,
+ FMT_1_5_5_5 = 0x11,
+ FMT_5_5_5_1 = 0x12,
+ FMT_4_4_4_4 = 0x13,
+ FMT_8_24 = 0x14,
+ FMT_24_8 = 0x15,
+ FMT_X24_8_32_FLOAT = 0x16,
+ FMT_RESERVED_33 = 0x17,
+ FMT_11_11_10_FLOAT = 0x18,
+ FMT_16_FLOAT = 0x19,
+ FMT_32_FLOAT = 0x1a,
+ FMT_16_16_FLOAT = 0x1b,
+ FMT_8_24_FLOAT = 0x1c,
+ FMT_24_8_FLOAT = 0x1d,
+ FMT_32_32_FLOAT = 0x1e,
+ FMT_10_11_11_FLOAT = 0x1f,
+ FMT_16_16_16_16_FLOAT = 0x20,
+ FMT_3_3_2 = 0x21,
+ FMT_6_5_5 = 0x22,
+ FMT_32_32_32_32_FLOAT = 0x23,
+ FMT_RESERVED_36 = 0x24,
+ FMT_1 = 0x25,
+ FMT_1_REVERSED = 0x26,
+ FMT_GB_GR = 0x27,
+ FMT_BG_RG = 0x28,
+ FMT_32_AS_8 = 0x29,
+ FMT_32_AS_8_8 = 0x2a,
+ FMT_5_9_9_9_SHAREDEXP = 0x2b,
+ FMT_8_8_8 = 0x2c,
+ FMT_16_16_16 = 0x2d,
+ FMT_16_16_16_FLOAT = 0x2e,
+ FMT_4_4 = 0x2f,
+ FMT_32_32_32_FLOAT = 0x30,
+ FMT_BC1 = 0x31,
+ FMT_BC2 = 0x32,
+ FMT_BC3 = 0x33,
+ FMT_BC4 = 0x34,
+ FMT_BC5 = 0x35,
+ FMT_BC6 = 0x36,
+ FMT_BC7 = 0x37,
+ FMT_32_AS_32_32_32_32 = 0x38,
+ FMT_APC3 = 0x39,
+ FMT_APC4 = 0x3a,
+ FMT_APC5 = 0x3b,
+ FMT_APC6 = 0x3c,
+ FMT_APC7 = 0x3d,
+ FMT_CTX1 = 0x3e,
+ FMT_RESERVED_63 = 0x3f,
+} SurfaceFormat;
+typedef enum BUF_DATA_FORMAT {
+ BUF_DATA_FORMAT_INVALID = 0x0,
+ BUF_DATA_FORMAT_8 = 0x1,
+ BUF_DATA_FORMAT_16 = 0x2,
+ BUF_DATA_FORMAT_8_8 = 0x3,
+ BUF_DATA_FORMAT_32 = 0x4,
+ BUF_DATA_FORMAT_16_16 = 0x5,
+ BUF_DATA_FORMAT_10_11_11 = 0x6,
+ BUF_DATA_FORMAT_11_11_10 = 0x7,
+ BUF_DATA_FORMAT_10_10_10_2 = 0x8,
+ BUF_DATA_FORMAT_2_10_10_10 = 0x9,
+ BUF_DATA_FORMAT_8_8_8_8 = 0xa,
+ BUF_DATA_FORMAT_32_32 = 0xb,
+ BUF_DATA_FORMAT_16_16_16_16 = 0xc,
+ BUF_DATA_FORMAT_32_32_32 = 0xd,
+ BUF_DATA_FORMAT_32_32_32_32 = 0xe,
+ BUF_DATA_FORMAT_RESERVED_15 = 0xf,
+} BUF_DATA_FORMAT;
+typedef enum IMG_DATA_FORMAT {
+ IMG_DATA_FORMAT_INVALID = 0x0,
+ IMG_DATA_FORMAT_8 = 0x1,
+ IMG_DATA_FORMAT_16 = 0x2,
+ IMG_DATA_FORMAT_8_8 = 0x3,
+ IMG_DATA_FORMAT_32 = 0x4,
+ IMG_DATA_FORMAT_16_16 = 0x5,
+ IMG_DATA_FORMAT_10_11_11 = 0x6,
+ IMG_DATA_FORMAT_11_11_10 = 0x7,
+ IMG_DATA_FORMAT_10_10_10_2 = 0x8,
+ IMG_DATA_FORMAT_2_10_10_10 = 0x9,
+ IMG_DATA_FORMAT_8_8_8_8 = 0xa,
+ IMG_DATA_FORMAT_32_32 = 0xb,
+ IMG_DATA_FORMAT_16_16_16_16 = 0xc,
+ IMG_DATA_FORMAT_32_32_32 = 0xd,
+ IMG_DATA_FORMAT_32_32_32_32 = 0xe,
+ IMG_DATA_FORMAT_RESERVED_15 = 0xf,
+ IMG_DATA_FORMAT_5_6_5 = 0x10,
+ IMG_DATA_FORMAT_1_5_5_5 = 0x11,
+ IMG_DATA_FORMAT_5_5_5_1 = 0x12,
+ IMG_DATA_FORMAT_4_4_4_4 = 0x13,
+ IMG_DATA_FORMAT_8_24 = 0x14,
+ IMG_DATA_FORMAT_24_8 = 0x15,
+ IMG_DATA_FORMAT_X24_8_32 = 0x16,
+ IMG_DATA_FORMAT_RESERVED_23 = 0x17,
+ IMG_DATA_FORMAT_RESERVED_24 = 0x18,
+ IMG_DATA_FORMAT_RESERVED_25 = 0x19,
+ IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
+ IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
+ IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
+ IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
+ IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
+ IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
+ IMG_DATA_FORMAT_GB_GR = 0x20,
+ IMG_DATA_FORMAT_BG_RG = 0x21,
+ IMG_DATA_FORMAT_5_9_9_9 = 0x22,
+ IMG_DATA_FORMAT_BC1 = 0x23,
+ IMG_DATA_FORMAT_BC2 = 0x24,
+ IMG_DATA_FORMAT_BC3 = 0x25,
+ IMG_DATA_FORMAT_BC4 = 0x26,
+ IMG_DATA_FORMAT_BC5 = 0x27,
+ IMG_DATA_FORMAT_BC6 = 0x28,
+ IMG_DATA_FORMAT_BC7 = 0x29,
+ IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
+ IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
+ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
+ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
+ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
+ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
+ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
+ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
+ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
+ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
+ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
+ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
+ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
+ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
+ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
+ IMG_DATA_FORMAT_4_4 = 0x39,
+ IMG_DATA_FORMAT_6_5_5 = 0x3a,
+ IMG_DATA_FORMAT_1 = 0x3b,
+ IMG_DATA_FORMAT_1_REVERSED = 0x3c,
+ IMG_DATA_FORMAT_32_AS_8 = 0x3d,
+ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
+ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
+} IMG_DATA_FORMAT;
+typedef enum BUF_NUM_FORMAT {
+ BUF_NUM_FORMAT_UNORM = 0x0,
+ BUF_NUM_FORMAT_SNORM = 0x1,
+ BUF_NUM_FORMAT_USCALED = 0x2,
+ BUF_NUM_FORMAT_SSCALED = 0x3,
+ BUF_NUM_FORMAT_UINT = 0x4,
+ BUF_NUM_FORMAT_SINT = 0x5,
+ BUF_NUM_FORMAT_RESERVED_6 = 0x6,
+ BUF_NUM_FORMAT_FLOAT = 0x7,
+} BUF_NUM_FORMAT;
+typedef enum IMG_NUM_FORMAT {
+ IMG_NUM_FORMAT_UNORM = 0x0,
+ IMG_NUM_FORMAT_SNORM = 0x1,
+ IMG_NUM_FORMAT_USCALED = 0x2,
+ IMG_NUM_FORMAT_SSCALED = 0x3,
+ IMG_NUM_FORMAT_UINT = 0x4,
+ IMG_NUM_FORMAT_SINT = 0x5,
+ IMG_NUM_FORMAT_RESERVED_6 = 0x6,
+ IMG_NUM_FORMAT_FLOAT = 0x7,
+ IMG_NUM_FORMAT_RESERVED_8 = 0x8,
+ IMG_NUM_FORMAT_SRGB = 0x9,
+ IMG_NUM_FORMAT_RESERVED_10 = 0xa,
+ IMG_NUM_FORMAT_RESERVED_11 = 0xb,
+ IMG_NUM_FORMAT_RESERVED_12 = 0xc,
+ IMG_NUM_FORMAT_RESERVED_13 = 0xd,
+ IMG_NUM_FORMAT_RESERVED_14 = 0xe,
+ IMG_NUM_FORMAT_RESERVED_15 = 0xf,
+} IMG_NUM_FORMAT;
+typedef enum TileType {
+ ARRAY_COLOR_TILE = 0x0,
+ ARRAY_DEPTH_TILE = 0x1,
+} TileType;
+typedef enum NonDispTilingOrder {
+ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
+ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
+} NonDispTilingOrder;
+typedef enum MicroTileMode {
+ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
+ ADDR_SURF_THIN_MICRO_TILING = 0x1,
+ ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
+ ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
+ ADDR_SURF_THICK_MICRO_TILING = 0x4,
+} MicroTileMode;
+typedef enum TileSplit {
+ ADDR_SURF_TILE_SPLIT_64B = 0x0,
+ ADDR_SURF_TILE_SPLIT_128B = 0x1,
+ ADDR_SURF_TILE_SPLIT_256B = 0x2,
+ ADDR_SURF_TILE_SPLIT_512B = 0x3,
+ ADDR_SURF_TILE_SPLIT_1KB = 0x4,
+ ADDR_SURF_TILE_SPLIT_2KB = 0x5,
+ ADDR_SURF_TILE_SPLIT_4KB = 0x6,
+} TileSplit;
+typedef enum SampleSplit {
+ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
+ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
+ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
+ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
+} SampleSplit;
+typedef enum PipeConfig {
+ ADDR_SURF_P2 = 0x0,
+ ADDR_SURF_P2_RESERVED0 = 0x1,
+ ADDR_SURF_P2_RESERVED1 = 0x2,
+ ADDR_SURF_P2_RESERVED2 = 0x3,
+ ADDR_SURF_P4_8x16 = 0x4,
+ ADDR_SURF_P4_16x16 = 0x5,
+ ADDR_SURF_P4_16x32 = 0x6,
+ ADDR_SURF_P4_32x32 = 0x7,
+ ADDR_SURF_P8_16x16_8x16 = 0x8,
+ ADDR_SURF_P8_16x32_8x16 = 0x9,
+ ADDR_SURF_P8_32x32_8x16 = 0xa,
+ ADDR_SURF_P8_16x32_16x16 = 0xb,
+ ADDR_SURF_P8_32x32_16x16 = 0xc,
+ ADDR_SURF_P8_32x32_16x32 = 0xd,
+ ADDR_SURF_P8_32x64_32x32 = 0xe,
+ ADDR_SURF_P8_RESERVED0 = 0xf,
+ ADDR_SURF_P16_32x32_8x16 = 0x10,
+ ADDR_SURF_P16_32x32_16x16 = 0x11,
+} PipeConfig;
+typedef enum NumBanks {
+ ADDR_SURF_2_BANK = 0x0,
+ ADDR_SURF_4_BANK = 0x1,
+ ADDR_SURF_8_BANK = 0x2,
+ ADDR_SURF_16_BANK = 0x3,
+} NumBanks;
+typedef enum BankWidth {
+ ADDR_SURF_BANK_WIDTH_1 = 0x0,
+ ADDR_SURF_BANK_WIDTH_2 = 0x1,
+ ADDR_SURF_BANK_WIDTH_4 = 0x2,
+ ADDR_SURF_BANK_WIDTH_8 = 0x3,
+} BankWidth;
+typedef enum BankHeight {
+ ADDR_SURF_BANK_HEIGHT_1 = 0x0,
+ ADDR_SURF_BANK_HEIGHT_2 = 0x1,
+ ADDR_SURF_BANK_HEIGHT_4 = 0x2,
+ ADDR_SURF_BANK_HEIGHT_8 = 0x3,
+} BankHeight;
+typedef enum BankWidthHeight {
+ ADDR_SURF_BANK_WH_1 = 0x0,
+ ADDR_SURF_BANK_WH_2 = 0x1,
+ ADDR_SURF_BANK_WH_4 = 0x2,
+ ADDR_SURF_BANK_WH_8 = 0x3,
+} BankWidthHeight;
+typedef enum MacroTileAspect {
+ ADDR_SURF_MACRO_ASPECT_1 = 0x0,
+ ADDR_SURF_MACRO_ASPECT_2 = 0x1,
+ ADDR_SURF_MACRO_ASPECT_4 = 0x2,
+ ADDR_SURF_MACRO_ASPECT_8 = 0x3,
+} MacroTileAspect;
+typedef enum GATCL1RequestType {
+ GATCL1_TYPE_NORMAL = 0x0,
+ GATCL1_TYPE_SHOOTDOWN = 0x1,
+ GATCL1_TYPE_BYPASS = 0x2,
+} GATCL1RequestType;
+typedef enum TCC_CACHE_POLICIES {
+ TCC_CACHE_POLICY_LRU = 0x0,
+ TCC_CACHE_POLICY_STREAM = 0x1,
+} TCC_CACHE_POLICIES;
+typedef enum MTYPE {
+ MTYPE_NC_NV = 0x0,
+ MTYPE_NC = 0x1,
+ MTYPE_CC = 0x2,
+ MTYPE_UC = 0x3,
+} MTYPE;
+typedef enum PERFMON_COUNTER_MODE {
+ PERFMON_COUNTER_MODE_ACCUM = 0x0,
+ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
+ PERFMON_COUNTER_MODE_MAX = 0x2,
+ PERFMON_COUNTER_MODE_DIRTY = 0x3,
+ PERFMON_COUNTER_MODE_SAMPLE = 0x4,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
+ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
+ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
+ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
+ PERFMON_COUNTER_MODE_RESERVED = 0xf,
+} PERFMON_COUNTER_MODE;
+typedef enum PERFMON_SPM_MODE {
+ PERFMON_SPM_MODE_OFF = 0x0,
+ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
+ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
+ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
+ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
+ PERFMON_SPM_MODE_RESERVED_5 = 0x5,
+ PERFMON_SPM_MODE_RESERVED_6 = 0x6,
+ PERFMON_SPM_MODE_RESERVED_7 = 0x7,
+ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
+ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
+ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
+} PERFMON_SPM_MODE;
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0x0,
+ ARRAY_TILED = 0x1,
+} SurfaceTiling;
+typedef enum SurfaceArray {
+ ARRAY_1D = 0x0,
+ ARRAY_2D = 0x1,
+ ARRAY_3D = 0x2,
+ ARRAY_3D_SLICE = 0x3,
+} SurfaceArray;
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0x0,
+ ARRAY_2D_COLOR = 0x1,
+ ARRAY_3D_SLICE_COLOR = 0x3,
+} ColorArray;
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0x0,
+ ARRAY_2D_DEPTH = 0x1,
+} DepthArray;
+typedef enum ENUM_NUM_SIMD_PER_CU {
+ NUM_SIMD_PER_CU = 0x4,
+} ENUM_NUM_SIMD_PER_CU;
+typedef enum MEM_PWR_FORCE_CTRL {
+ NO_FORCE_REQUEST = 0x0,
+ FORCE_LIGHT_SLEEP_REQUEST = 0x1,
+ FORCE_DEEP_SLEEP_REQUEST = 0x2,
+ FORCE_SHUT_DOWN_REQUEST = 0x3,
+} MEM_PWR_FORCE_CTRL;
+typedef enum MEM_PWR_FORCE_CTRL2 {
+ NO_FORCE_REQ = 0x0,
+ FORCE_LIGHT_SLEEP_REQ = 0x1,
+} MEM_PWR_FORCE_CTRL2;
+typedef enum MEM_PWR_DIS_CTRL {
+ ENABLE_MEM_PWR_CTRL = 0x0,
+ DISABLE_MEM_PWR_CTRL = 0x1,
+} MEM_PWR_DIS_CTRL;
+typedef enum MEM_PWR_SEL_CTRL {
+ DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
+ DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
+ DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
+} MEM_PWR_SEL_CTRL;
+typedef enum MEM_PWR_SEL_CTRL2 {
+ DYNAMIC_DEEP_SLEEP_EN = 0x0,
+ DYNAMIC_LIGHT_SLEEP_EN = 0x1,
+} MEM_PWR_SEL_CTRL2;
+
+#endif /* OSS_3_0_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h
new file mode 100644
index 000000000000..7e2cca5fed87
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h
@@ -0,0 +1,3660 @@
+/*
+ * OSS_3_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef OSS_3_0_SH_MASK_H
+#define OSS_3_0_SH_MASK_H
+
+#define IH_VMID_0_LUT__PASID_MASK 0xffff
+#define IH_VMID_0_LUT__PASID__SHIFT 0x0
+#define IH_VMID_1_LUT__PASID_MASK 0xffff
+#define IH_VMID_1_LUT__PASID__SHIFT 0x0
+#define IH_VMID_2_LUT__PASID_MASK 0xffff
+#define IH_VMID_2_LUT__PASID__SHIFT 0x0
+#define IH_VMID_3_LUT__PASID_MASK 0xffff
+#define IH_VMID_3_LUT__PASID__SHIFT 0x0
+#define IH_VMID_4_LUT__PASID_MASK 0xffff
+#define IH_VMID_4_LUT__PASID__SHIFT 0x0
+#define IH_VMID_5_LUT__PASID_MASK 0xffff
+#define IH_VMID_5_LUT__PASID__SHIFT 0x0
+#define IH_VMID_6_LUT__PASID_MASK 0xffff
+#define IH_VMID_6_LUT__PASID__SHIFT 0x0
+#define IH_VMID_7_LUT__PASID_MASK 0xffff
+#define IH_VMID_7_LUT__PASID__SHIFT 0x0
+#define IH_VMID_8_LUT__PASID_MASK 0xffff
+#define IH_VMID_8_LUT__PASID__SHIFT 0x0
+#define IH_VMID_9_LUT__PASID_MASK 0xffff
+#define IH_VMID_9_LUT__PASID__SHIFT 0x0
+#define IH_VMID_10_LUT__PASID_MASK 0xffff
+#define IH_VMID_10_LUT__PASID__SHIFT 0x0
+#define IH_VMID_11_LUT__PASID_MASK 0xffff
+#define IH_VMID_11_LUT__PASID__SHIFT 0x0
+#define IH_VMID_12_LUT__PASID_MASK 0xffff
+#define IH_VMID_12_LUT__PASID__SHIFT 0x0
+#define IH_VMID_13_LUT__PASID_MASK 0xffff
+#define IH_VMID_13_LUT__PASID__SHIFT 0x0
+#define IH_VMID_14_LUT__PASID_MASK 0xffff
+#define IH_VMID_14_LUT__PASID__SHIFT 0x0
+#define IH_VMID_15_LUT__PASID_MASK 0xffff
+#define IH_VMID_15_LUT__PASID__SHIFT 0x0
+#define IH_RB_CNTL__RB_ENABLE_MASK 0x1
+#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define IH_RB_CNTL__RB_SIZE_MASK 0x3e
+#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x80
+#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7
+#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100
+#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
+#define IH_RB_CNTL__ENABLE_INTR_MASK 0x20000
+#define IH_RB_CNTL__ENABLE_INTR__SHIFT 0x11
+#define IH_RB_CNTL__MC_SWAP_MASK 0xc0000
+#define IH_RB_CNTL__MC_SWAP__SHIFT 0x12
+#define IH_RB_CNTL__RPTR_REARM_MASK 0x200000
+#define IH_RB_CNTL__RPTR_REARM__SHIFT 0x15
+#define IH_RB_CNTL__MC_VMID_MASK 0xf000000
+#define IH_RB_CNTL__MC_VMID__SHIFT 0x18
+#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
+#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define IH_RB_BASE__ADDR_MASK 0xffffffff
+#define IH_RB_BASE__ADDR__SHIFT 0x0
+#define IH_RB_RPTR__OFFSET_MASK 0x3fffc
+#define IH_RB_RPTR__OFFSET__SHIFT 0x2
+#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1
+#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0
+#define IH_RB_WPTR__OFFSET_MASK 0x3fffc
+#define IH_RB_WPTR__OFFSET__SHIFT 0x2
+#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x40000
+#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12
+#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x80000
+#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13
+#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0xff
+#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define IH_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x1f
+#define IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x0
+#define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x300
+#define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x8
+#define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x7c00
+#define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa
+#define IH_CNTL__MC_WRREQ_CREDIT_MASK 0xf8000
+#define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0xf
+#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x1f00000
+#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14
+#define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1
+#define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x0
+#define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x4
+#define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2
+#define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x8
+#define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x3
+#define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x10
+#define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x4
+#define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x20
+#define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x5
+#define IH_STATUS__IDLE_MASK 0x1
+#define IH_STATUS__IDLE__SHIFT 0x0
+#define IH_STATUS__INPUT_IDLE_MASK 0x2
+#define IH_STATUS__INPUT_IDLE__SHIFT 0x1
+#define IH_STATUS__RB_IDLE_MASK 0x4
+#define IH_STATUS__RB_IDLE__SHIFT 0x2
+#define IH_STATUS__RB_FULL_MASK 0x8
+#define IH_STATUS__RB_FULL__SHIFT 0x3
+#define IH_STATUS__RB_FULL_DRAIN_MASK 0x10
+#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4
+#define IH_STATUS__RB_OVERFLOW_MASK 0x20
+#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5
+#define IH_STATUS__MC_WR_IDLE_MASK 0x40
+#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6
+#define IH_STATUS__MC_WR_STALL_MASK 0x80
+#define IH_STATUS__MC_WR_STALL__SHIFT 0x7
+#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x100
+#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8
+#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x200
+#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9
+#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x400
+#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa
+#define IH_STATUS__SWITCH_READY_MASK 0x800
+#define IH_STATUS__SWITCH_READY__SHIFT 0xb
+#define IH_PERFMON_CNTL__ENABLE0_MASK 0x1
+#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0
+#define IH_PERFMON_CNTL__CLEAR0_MASK 0x2
+#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1
+#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x3fc
+#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
+#define IH_PERFMON_CNTL__ENABLE1_MASK 0x400
+#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0xa
+#define IH_PERFMON_CNTL__CLEAR1_MASK 0x800
+#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0xb
+#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0xff000
+#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc
+#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
+#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
+#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
+#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
+#define IH_DEBUG__RB_FULL_DRAIN_ENABLE_MASK 0x1
+#define IH_DEBUG__RB_FULL_DRAIN_ENABLE__SHIFT 0x0
+#define IH_DEBUG__WPTR_OVERFLOW_ENABLE_MASK 0x2
+#define IH_DEBUG__WPTR_OVERFLOW_ENABLE__SHIFT 0x1
+#define IH_DEBUG__MC_WR_FIFO_BLOCK_ENABLE_MASK 0x4
+#define IH_DEBUG__MC_WR_FIFO_BLOCK_ENABLE__SHIFT 0x2
+#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xffffffff
+#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0
+#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xffffffff
+#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0
+#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xffffffff
+#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0
+#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x1
+#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0
+#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK 0x2
+#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT 0x1
+#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x4
+#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2
+#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x8
+#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3
+#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x10
+#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4
+#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x20
+#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5
+#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0xfffffff
+#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0
+#define IH_DOORBELL_RPTR__OFFSET_MASK 0x1fffff
+#define IH_DOORBELL_RPTR__OFFSET__SHIFT 0x0
+#define IH_DOORBELL_RPTR__ENABLE_MASK 0x10000000
+#define IH_DOORBELL_RPTR__ENABLE__SHIFT 0x1c
+#define IH_DOORBELL_RPTR__CAPTURED_MASK 0x40000000
+#define IH_DOORBELL_RPTR__CAPTURED__SHIFT 0x1e
+#define IH_ACTIVE_FCN_ID__VF_ID_MASK 0xf
+#define IH_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0
+#define IH_ACTIVE_FCN_ID__RESERVED_MASK 0x7ffffff0
+#define IH_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
+#define IH_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000
+#define IH_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f
+#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK 0xffff
+#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0
+#define IH_VF_RB_STATUS__RB_OVERFLOW_VF_MASK 0xffff0000
+#define IH_VF_RB_STATUS__RB_OVERFLOW_VF__SHIFT 0x10
+#define IH_VF_ENABLE__VALUE_MASK 0x1
+#define IH_VF_ENABLE__VALUE__SHIFT 0x0
+#define IH_VIRT_RESET_REQ__VF_MASK 0xffff
+#define IH_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define IH_VIRT_RESET_REQ__PF_MASK 0x80000000
+#define IH_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define IH_VF_RB_BIF_STATUS__RB_FULL_VF_MASK 0xffff
+#define IH_VF_RB_BIF_STATUS__RB_FULL_VF__SHIFT 0x0
+#define IH_VF_RB_BIF_STATUS__BIF_INTERRUPT_LINE_VF_MASK 0xffff0000
+#define IH_VF_RB_BIF_STATUS__BIF_INTERRUPT_LINE_VF__SHIFT 0x10
+#define IH_VERSION__VALUE_MASK 0xfff
+#define IH_VERSION__VALUE__SHIFT 0x0
+#define IH_LEVEL_INTR_MASK__MASK_MASK 0x1
+#define IH_LEVEL_INTR_MASK__MASK__SHIFT 0x0
+#define IH_RESET_INCOMPLETE_INT_CNTL__CG_MASK 0x1
+#define IH_RESET_INCOMPLETE_INT_CNTL__CG__SHIFT 0x0
+#define IH_RESET_INCOMPLETE_INT_CNTL__DC_MASK 0x2
+#define IH_RESET_INCOMPLETE_INT_CNTL__DC__SHIFT 0x1
+#define IH_RESET_INCOMPLETE_INT_CNTL__SAMMSP_MASK 0x8
+#define IH_RESET_INCOMPLETE_INT_CNTL__SAMMSP__SHIFT 0x3
+#define IH_RESET_INCOMPLETE_INT_CNTL__RLC_MASK 0x10
+#define IH_RESET_INCOMPLETE_INT_CNTL__RLC__SHIFT 0x4
+#define IH_RESET_INCOMPLETE_INT_CNTL__ROM_MASK 0x20
+#define IH_RESET_INCOMPLETE_INT_CNTL__ROM__SHIFT 0x5
+#define IH_RESET_INCOMPLETE_INT_CNTL__SRBM_MASK 0x40
+#define IH_RESET_INCOMPLETE_INT_CNTL__SRBM__SHIFT 0x6
+#define IH_RESET_INCOMPLETE_INT_CNTL__VMC_MASK 0x80
+#define IH_RESET_INCOMPLETE_INT_CNTL__VMC__SHIFT 0x7
+#define IH_RESET_INCOMPLETE_INT_CNTL__UVD_MASK 0x100
+#define IH_RESET_INCOMPLETE_INT_CNTL__UVD__SHIFT 0x8
+#define IH_RESET_INCOMPLETE_INT_CNTL__BIF_MASK 0x200
+#define IH_RESET_INCOMPLETE_INT_CNTL__BIF__SHIFT 0x9
+#define IH_RESET_INCOMPLETE_INT_CNTL__SDMA0_MASK 0x400
+#define IH_RESET_INCOMPLETE_INT_CNTL__SDMA0__SHIFT 0xa
+#define IH_RESET_INCOMPLETE_INT_CNTL__SDMA1_MASK 0x800
+#define IH_RESET_INCOMPLETE_INT_CNTL__SDMA1__SHIFT 0xb
+#define IH_RESET_INCOMPLETE_INT_CNTL__ISP_MASK 0x1000
+#define IH_RESET_INCOMPLETE_INT_CNTL__ISP__SHIFT 0xc
+#define IH_RESET_INCOMPLETE_INT_CNTL__VCE0_MASK 0x2000
+#define IH_RESET_INCOMPLETE_INT_CNTL__VCE0__SHIFT 0xd
+#define IH_RESET_INCOMPLETE_INT_CNTL__VCE1_MASK 0x4000
+#define IH_RESET_INCOMPLETE_INT_CNTL__VCE1__SHIFT 0xe
+#define IH_RESET_INCOMPLETE_INT_CNTL__ATC_MASK 0x8000
+#define IH_RESET_INCOMPLETE_INT_CNTL__ATC__SHIFT 0xf
+#define IH_RESET_INCOMPLETE_INT_CNTL__XDMA_MASK 0x10000
+#define IH_RESET_INCOMPLETE_INT_CNTL__XDMA__SHIFT 0x10
+#define IH_RESET_INCOMPLETE_INT_CNTL__ACP_MASK 0x20000
+#define IH_RESET_INCOMPLETE_INT_CNTL__ACP__SHIFT 0x11
+#define IH_RESET_INCOMPLETE_INT_CNTL__SH_MASK 0x40000
+#define IH_RESET_INCOMPLETE_INT_CNTL__SH__SHIFT 0x12
+#define IH_RESET_INCOMPLETE_INT_CNTL__SH1_MASK 0x80000
+#define IH_RESET_INCOMPLETE_INT_CNTL__SH1__SHIFT 0x13
+#define IH_RESET_INCOMPLETE_INT_CNTL__SH2_MASK 0x100000
+#define IH_RESET_INCOMPLETE_INT_CNTL__SH2__SHIFT 0x14
+#define IH_RESET_INCOMPLETE_INT_CNTL__SH3_MASK 0x200000
+#define IH_RESET_INCOMPLETE_INT_CNTL__SH3__SHIFT 0x15
+#define IH_RESET_INCOMPLETE_INT_CNTL__RESET_ENABLE_MASK 0x400000
+#define IH_RESET_INCOMPLETE_INT_CNTL__RESET_ENABLE__SHIFT 0x16
+#define IH_RESET_INCOMPLETE_INT_CNTL__INCOMPLETE_CNT_MASK 0xf000000
+#define IH_RESET_INCOMPLETE_INT_CNTL__INCOMPLETE_CNT__SHIFT 0x18
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__CG_MASK 0x1
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__CG__SHIFT 0x0
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__DC_MASK 0x2
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__DC__SHIFT 0x1
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SAMMSP_MASK 0x8
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SAMMSP__SHIFT 0x3
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__RLC_MASK 0x10
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__RLC__SHIFT 0x4
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ROM_MASK 0x20
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ROM__SHIFT 0x5
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SRBM_MASK 0x40
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SRBM__SHIFT 0x6
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VMC_MASK 0x80
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VMC__SHIFT 0x7
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__UVD_MASK 0x100
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__UVD__SHIFT 0x8
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__BIF_MASK 0x200
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__BIF__SHIFT 0x9
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA0_MASK 0x400
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA0__SHIFT 0xa
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA1_MASK 0x800
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA1__SHIFT 0xb
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ISP_MASK 0x1000
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ISP__SHIFT 0xc
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE0_MASK 0x2000
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE0__SHIFT 0xd
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE1_MASK 0x4000
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE1__SHIFT 0xe
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ATC_MASK 0x8000
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ATC__SHIFT 0xf
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__XDMA_MASK 0x10000
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__XDMA__SHIFT 0x10
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ACP_MASK 0x20000
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ACP__SHIFT 0x11
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH_MASK 0x40000
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH__SHIFT 0x12
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH1_MASK 0x80000
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH1__SHIFT 0x13
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH2_MASK 0x100000
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH2__SHIFT 0x14
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH3_MASK 0x200000
+#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH3__SHIFT 0x15
+#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x3
+#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0
+#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0xfc
+#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2
+#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x3f00
+#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8
+#define SDMA_CONFIG__SDMA_RDREQ_URG_MASK 0xf00
+#define SDMA_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8
+#define SDMA_CONFIG__SDMA_REQ_TRAN_MASK 0x10000
+#define SDMA_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10
+#define SDMA1_CONFIG__SDMA_RDREQ_URG_MASK 0xf00
+#define SDMA1_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8
+#define SDMA1_CONFIG__SDMA_REQ_TRAN_MASK 0x10000
+#define SDMA1_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10
+#define UVD_CONFIG__UVD_RDREQ_URG_MASK 0xf00
+#define UVD_CONFIG__UVD_RDREQ_URG__SHIFT 0x8
+#define UVD_CONFIG__UVD_REQ_TRAN_MASK 0x10000
+#define UVD_CONFIG__UVD_REQ_TRAN__SHIFT 0x10
+#define VCE_CONFIG__VCE_RDREQ_URG_MASK 0xf00
+#define VCE_CONFIG__VCE_RDREQ_URG__SHIFT 0x8
+#define VCE_CONFIG__VCE_REQ_TRAN_MASK 0x10000
+#define VCE_CONFIG__VCE_REQ_TRAN__SHIFT 0x10
+#define SEM_VF_ENABLE__VALUE_MASK 0x1
+#define SEM_VF_ENABLE__VALUE__SHIFT 0x0
+#define CP_CONFIG__CP_RDREQ_URG_MASK 0xf00
+#define CP_CONFIG__CP_RDREQ_URG__SHIFT 0x8
+#define CP_CONFIG__CP_REQ_TRAN_MASK 0x10000
+#define CP_CONFIG__CP_REQ_TRAN__SHIFT 0x10
+#define SEM_ACTIVE_FCN_ID__VFID_MASK 0xf
+#define SEM_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define SEM_ACTIVE_FCN_ID__VF_MASK 0x80000000
+#define SEM_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define SEM_VIRT_RESET_REQ__VF_MASK 0xffff
+#define SEM_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define SEM_VIRT_RESET_REQ__PF_MASK 0x80000000
+#define SEM_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define SEM_STATUS__SEM_IDLE_MASK 0x1
+#define SEM_STATUS__SEM_IDLE__SHIFT 0x0
+#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x2
+#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1
+#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x4
+#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2
+#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x8
+#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3
+#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x10
+#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4
+#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x20
+#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5
+#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x40
+#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6
+#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x80
+#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7
+#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x100
+#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8
+#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x200
+#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9
+#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x400
+#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa
+#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x800
+#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb
+#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x1000
+#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc
+#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x2000
+#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd
+#define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x4000
+#define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0xe
+#define SEM_STATUS__SWITCH_READY_MASK 0x80000000
+#define SEM_STATUS__SWITCH_READY__SHIFT 0x1f
+#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x2
+#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x7
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x38
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x1c0
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0xe00
+#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x7000
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc
+#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x38000
+#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x1c0000
+#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12
+#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0xe00000
+#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15
+#define SEM_MAILBOX__SIDEPORT_MASK 0xff
+#define SEM_MAILBOX__SIDEPORT__SHIFT 0x0
+#define SEM_MAILBOX__HOSTPORT_MASK 0xff00
+#define SEM_MAILBOX__HOSTPORT__SHIFT 0x8
+#define SEM_MAILBOX__SIDEPORT_EXTRA_MASK 0xff0000
+#define SEM_MAILBOX__SIDEPORT_EXTRA__SHIFT 0x10
+#define SEM_MAILBOX__HOSTPORT_EXTRA_MASK 0xff000000
+#define SEM_MAILBOX__HOSTPORT_EXTRA__SHIFT 0x18
+#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0xff
+#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x0
+#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0xff00
+#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x8
+#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA_MASK 0xff0000
+#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA__SHIFT 0x10
+#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA_MASK 0xff000000
+#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA__SHIFT 0x18
+#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x1
+#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0
+#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x2
+#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1
+#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x4
+#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2
+#define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x18
+#define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x3
+#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0xf00
+#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x8
+#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x1f
+#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x0
+#define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x10000
+#define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x10
+#define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x20000
+#define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x11
+#define SRBM_CNTL__REPORT_LAST_RDERR_MASK 0x40000
+#define SRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x12
+#define SRBM_GFX_CNTL__PIPEID_MASK 0x3
+#define SRBM_GFX_CNTL__PIPEID__SHIFT 0x0
+#define SRBM_GFX_CNTL__MEID_MASK 0xc
+#define SRBM_GFX_CNTL__MEID__SHIFT 0x2
+#define SRBM_GFX_CNTL__VMID_MASK 0xf0
+#define SRBM_GFX_CNTL__VMID__SHIFT 0x4
+#define SRBM_GFX_CNTL__QUEUEID_MASK 0x700
+#define SRBM_GFX_CNTL__QUEUEID__SHIFT 0x8
+#define SRBM_READ_CNTL__READ_TIMEOUT_MASK 0xffffff
+#define SRBM_READ_CNTL__READ_TIMEOUT__SHIFT 0x0
+#define SRBM_STATUS2__SDMA_RQ_PENDING_MASK 0x1
+#define SRBM_STATUS2__SDMA_RQ_PENDING__SHIFT 0x0
+#define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x2
+#define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x1
+#define SRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x4
+#define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x2
+#define SRBM_STATUS2__VCE0_RQ_PENDING_MASK 0x8
+#define SRBM_STATUS2__VCE0_RQ_PENDING__SHIFT 0x3
+#define SRBM_STATUS2__VP8_BUSY_MASK 0x10
+#define SRBM_STATUS2__VP8_BUSY__SHIFT 0x4
+#define SRBM_STATUS2__SDMA_BUSY_MASK 0x20
+#define SRBM_STATUS2__SDMA_BUSY__SHIFT 0x5
+#define SRBM_STATUS2__SDMA1_BUSY_MASK 0x40
+#define SRBM_STATUS2__SDMA1_BUSY__SHIFT 0x6
+#define SRBM_STATUS2__VCE0_BUSY_MASK 0x80
+#define SRBM_STATUS2__VCE0_BUSY__SHIFT 0x7
+#define SRBM_STATUS2__XDMA_BUSY_MASK 0x100
+#define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x8
+#define SRBM_STATUS2__CHUB_BUSY_MASK 0x200
+#define SRBM_STATUS2__CHUB_BUSY__SHIFT 0x9
+#define SRBM_STATUS2__SDMA2_BUSY_MASK 0x400
+#define SRBM_STATUS2__SDMA2_BUSY__SHIFT 0xa
+#define SRBM_STATUS2__SDMA3_BUSY_MASK 0x800
+#define SRBM_STATUS2__SDMA3_BUSY__SHIFT 0xb
+#define SRBM_STATUS2__SAMSCP_BUSY_MASK 0x1000
+#define SRBM_STATUS2__SAMSCP_BUSY__SHIFT 0xc
+#define SRBM_STATUS2__ISP_BUSY_MASK 0x2000
+#define SRBM_STATUS2__ISP_BUSY__SHIFT 0xd
+#define SRBM_STATUS2__VCE1_BUSY_MASK 0x4000
+#define SRBM_STATUS2__VCE1_BUSY__SHIFT 0xe
+#define SRBM_STATUS2__ODE_BUSY_MASK 0x8000
+#define SRBM_STATUS2__ODE_BUSY__SHIFT 0xf
+#define SRBM_STATUS2__SDMA2_RQ_PENDING_MASK 0x10000
+#define SRBM_STATUS2__SDMA2_RQ_PENDING__SHIFT 0x10
+#define SRBM_STATUS2__SDMA3_RQ_PENDING_MASK 0x20000
+#define SRBM_STATUS2__SDMA3_RQ_PENDING__SHIFT 0x11
+#define SRBM_STATUS2__SAMSCP_RQ_PENDING_MASK 0x40000
+#define SRBM_STATUS2__SAMSCP_RQ_PENDING__SHIFT 0x12
+#define SRBM_STATUS2__ISP_RQ_PENDING_MASK 0x80000
+#define SRBM_STATUS2__ISP_RQ_PENDING__SHIFT 0x13
+#define SRBM_STATUS2__VCE1_RQ_PENDING_MASK 0x100000
+#define SRBM_STATUS2__VCE1_RQ_PENDING__SHIFT 0x14
+#define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x2
+#define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x1
+#define SRBM_STATUS__SAMMSP_RQ_PENDING_MASK 0x4
+#define SRBM_STATUS__SAMMSP_RQ_PENDING__SHIFT 0x2
+#define SRBM_STATUS__ACP_RQ_PENDING_MASK 0x8
+#define SRBM_STATUS__ACP_RQ_PENDING__SHIFT 0x3
+#define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x10
+#define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x4
+#define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x20
+#define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x5
+#define SRBM_STATUS__HI_RQ_PENDING_MASK 0x40
+#define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x6
+#define SRBM_STATUS__VMC_BUSY_MASK 0x100
+#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8
+#define SRBM_STATUS__MCB_BUSY_MASK 0x200
+#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9
+#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400
+#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa
+#define SRBM_STATUS__MCC_BUSY_MASK 0x800
+#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb
+#define SRBM_STATUS__MCD_BUSY_MASK 0x1000
+#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc
+#define SRBM_STATUS__VMC1_BUSY_MASK 0x2000
+#define SRBM_STATUS__VMC1_BUSY__SHIFT 0xd
+#define SRBM_STATUS__SEM_BUSY_MASK 0x4000
+#define SRBM_STATUS__SEM_BUSY__SHIFT 0xe
+#define SRBM_STATUS__ACP_BUSY_MASK 0x10000
+#define SRBM_STATUS__ACP_BUSY__SHIFT 0x10
+#define SRBM_STATUS__IH_BUSY_MASK 0x20000
+#define SRBM_STATUS__IH_BUSY__SHIFT 0x11
+#define SRBM_STATUS__UVD_BUSY_MASK 0x80000
+#define SRBM_STATUS__UVD_BUSY__SHIFT 0x13
+#define SRBM_STATUS__SAMMSP_BUSY_MASK 0x100000
+#define SRBM_STATUS__SAMMSP_BUSY__SHIFT 0x14
+#define SRBM_STATUS__GCATCL2_BUSY_MASK 0x200000
+#define SRBM_STATUS__GCATCL2_BUSY__SHIFT 0x15
+#define SRBM_STATUS__OSATCL2_BUSY_MASK 0x400000
+#define SRBM_STATUS__OSATCL2_BUSY__SHIFT 0x16
+#define SRBM_STATUS__BIF_BUSY_MASK 0x20000000
+#define SRBM_STATUS__BIF_BUSY__SHIFT 0x1d
+#define SRBM_STATUS3__MCC0_BUSY_MASK 0x1
+#define SRBM_STATUS3__MCC0_BUSY__SHIFT 0x0
+#define SRBM_STATUS3__MCC1_BUSY_MASK 0x2
+#define SRBM_STATUS3__MCC1_BUSY__SHIFT 0x1
+#define SRBM_STATUS3__MCC2_BUSY_MASK 0x4
+#define SRBM_STATUS3__MCC2_BUSY__SHIFT 0x2
+#define SRBM_STATUS3__MCC3_BUSY_MASK 0x8
+#define SRBM_STATUS3__MCC3_BUSY__SHIFT 0x3
+#define SRBM_STATUS3__MCC4_BUSY_MASK 0x10
+#define SRBM_STATUS3__MCC4_BUSY__SHIFT 0x4
+#define SRBM_STATUS3__MCC5_BUSY_MASK 0x20
+#define SRBM_STATUS3__MCC5_BUSY__SHIFT 0x5
+#define SRBM_STATUS3__MCC6_BUSY_MASK 0x40
+#define SRBM_STATUS3__MCC6_BUSY__SHIFT 0x6
+#define SRBM_STATUS3__MCC7_BUSY_MASK 0x80
+#define SRBM_STATUS3__MCC7_BUSY__SHIFT 0x7
+#define SRBM_STATUS3__MCD0_BUSY_MASK 0x100
+#define SRBM_STATUS3__MCD0_BUSY__SHIFT 0x8
+#define SRBM_STATUS3__MCD1_BUSY_MASK 0x200
+#define SRBM_STATUS3__MCD1_BUSY__SHIFT 0x9
+#define SRBM_STATUS3__MCD2_BUSY_MASK 0x400
+#define SRBM_STATUS3__MCD2_BUSY__SHIFT 0xa
+#define SRBM_STATUS3__MCD3_BUSY_MASK 0x800
+#define SRBM_STATUS3__MCD3_BUSY__SHIFT 0xb
+#define SRBM_STATUS3__MCD4_BUSY_MASK 0x1000
+#define SRBM_STATUS3__MCD4_BUSY__SHIFT 0xc
+#define SRBM_STATUS3__MCD5_BUSY_MASK 0x2000
+#define SRBM_STATUS3__MCD5_BUSY__SHIFT 0xd
+#define SRBM_STATUS3__MCD6_BUSY_MASK 0x4000
+#define SRBM_STATUS3__MCD6_BUSY__SHIFT 0xe
+#define SRBM_STATUS3__MCD7_BUSY_MASK 0x8000
+#define SRBM_STATUS3__MCD7_BUSY__SHIFT 0xf
+#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2_MASK 0x1
+#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2__SHIFT 0x0
+#define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x2
+#define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x1
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3_MASK 0x4
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3__SHIFT 0x2
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2_MASK 0x8
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2__SHIFT 0x3
+#define SRBM_SOFT_RESET__SOFT_RESET_GIONB_MASK 0x10
+#define SRBM_SOFT_RESET__SOFT_RESET_GIONB__SHIFT 0x4
+#define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x20
+#define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x5
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x40
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x6
+#define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x100
+#define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x8
+#define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x200
+#define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x9
+#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400
+#define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa
+#define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x800
+#define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0xb
+#define SRBM_SOFT_RESET__SOFT_RESET_CHUB_MASK 0x1000
+#define SRBM_SOFT_RESET__SOFT_RESET_CHUB__SHIFT 0xc
+#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM_MASK 0x2000
+#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM__SHIFT 0xd
+#define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x4000
+#define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0xe
+#define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x8000
+#define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0xf
+#define SRBM_SOFT_RESET__SOFT_RESET_SMU_MASK 0x10000
+#define SRBM_SOFT_RESET__SOFT_RESET_SMU__SHIFT 0x10
+#define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x20000
+#define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x11
+#define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x40000
+#define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x12
+#define SRBM_SOFT_RESET__SOFT_RESET_VP8_MASK 0x80000
+#define SRBM_SOFT_RESET__SOFT_RESET_VP8__SHIFT 0x13
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK 0x100000
+#define SRBM_SOFT_RESET__SOFT_RESET_SDMA__SHIFT 0x14
+#define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x200000
+#define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x15
+#define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x400000
+#define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x16
+#define SRBM_SOFT_RESET__SOFT_RESET_ODE_MASK 0x800000
+#define SRBM_SOFT_RESET__SOFT_RESET_ODE__SHIFT 0x17
+#define SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK 0x1000000
+#define SRBM_SOFT_RESET__SOFT_RESET_VCE0__SHIFT 0x18
+#define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x2000000
+#define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x19
+#define SRBM_SOFT_RESET__SOFT_RESET_ACP_MASK 0x4000000
+#define SRBM_SOFT_RESET__SOFT_RESET_ACP__SHIFT 0x1a
+#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP_MASK 0x8000000
+#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP__SHIFT 0x1b
+#define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP_MASK 0x10000000
+#define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP__SHIFT 0x1c
+#define SRBM_SOFT_RESET__SOFT_RESET_GRN_MASK 0x20000000
+#define SRBM_SOFT_RESET__SOFT_RESET_GRN__SHIFT 0x1d
+#define SRBM_SOFT_RESET__SOFT_RESET_ISP_MASK 0x40000000
+#define SRBM_SOFT_RESET__SOFT_RESET_ISP__SHIFT 0x1e
+#define SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK 0x80000000
+#define SRBM_SOFT_RESET__SOFT_RESET_VCE1__SHIFT 0x1f
+#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x3f
+#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x0
+#define SRBM_DEBUG_DATA__DATA_MASK 0xffffffff
+#define SRBM_DEBUG_DATA__DATA__SHIFT 0x0
+#define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0xff
+#define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0
+#define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_TIME_MASK 0xfff
+#define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_TIME__SHIFT 0x0
+#define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_ENABLE_MASK 0x80000000
+#define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_ENABLE__SHIFT 0x1f
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_BIF_MASK 0x1
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_BIF__SHIFT 0x0
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SMU_MASK 0x2
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SMU__SHIFT 0x1
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_DC_MASK 0x4
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_DC__SHIFT 0x2
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GIONB_MASK 0x8
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GIONB__SHIFT 0x3
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ACP_MASK 0x10
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ACP__SHIFT 0x4
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_XDMA_MASK 0x20
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_XDMA__SHIFT 0x5
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ODE_MASK 0x40
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ODE__SHIFT 0x6
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_REGBB_MASK 0x80
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_REGBB__SHIFT 0x7
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VP8_MASK 0x100
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VP8__SHIFT 0x8
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GRBM_MASK 0x200
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GRBM__SHIFT 0x9
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_UVD_MASK 0x400
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_UVD__SHIFT 0xa
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE0_MASK 0x800
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE0__SHIFT 0xb
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE1_MASK 0x1000
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE1__SHIFT 0xc
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ISP_MASK 0x2000
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ISP__SHIFT 0xd
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SAM_MASK 0x4000
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SAM__SHIFT 0xe
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCB_MASK 0x8000
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCB__SHIFT 0xf
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC0_MASK 0x10000
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC0__SHIFT 0x10
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC1_MASK 0x20000
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC1__SHIFT 0x11
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC2_MASK 0x40000
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC2__SHIFT 0x12
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC3_MASK 0x80000
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC3__SHIFT 0x13
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC4_MASK 0x100000
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC4__SHIFT 0x14
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC5_MASK 0x200000
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC5__SHIFT 0x15
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC6_MASK 0x400000
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC6__SHIFT 0x16
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC7_MASK 0x800000
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC7__SHIFT 0x17
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD0_MASK 0x1000000
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD0__SHIFT 0x18
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD1_MASK 0x2000000
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD1__SHIFT 0x19
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD2_MASK 0x4000000
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD2__SHIFT 0x1a
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD3_MASK 0x8000000
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD3__SHIFT 0x1b
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD4_MASK 0x10000000
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD4__SHIFT 0x1c
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD5_MASK 0x20000000
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD5__SHIFT 0x1d
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD6_MASK 0x40000000
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD6__SHIFT 0x1e
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD7_MASK 0x80000000
+#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD7__SHIFT 0x1f
+#define SRBM_CREDIT_RESET__CREDIT_RESET_BIF_MASK 0x1
+#define SRBM_CREDIT_RESET__CREDIT_RESET_BIF__SHIFT 0x0
+#define SRBM_CREDIT_RESET__CREDIT_RESET_SMU_MASK 0x2
+#define SRBM_CREDIT_RESET__CREDIT_RESET_SMU__SHIFT 0x1
+#define SRBM_CREDIT_RESET__CREDIT_RESET_DC_MASK 0x4
+#define SRBM_CREDIT_RESET__CREDIT_RESET_DC__SHIFT 0x2
+#define SRBM_CREDIT_RESET__CREDIT_RESET_GIONB_MASK 0x8
+#define SRBM_CREDIT_RESET__CREDIT_RESET_GIONB__SHIFT 0x3
+#define SRBM_CREDIT_RESET__CREDIT_RESET_ACP_MASK 0x10
+#define SRBM_CREDIT_RESET__CREDIT_RESET_ACP__SHIFT 0x4
+#define SRBM_CREDIT_RESET__CREDIT_RESET_XDMA_MASK 0x20
+#define SRBM_CREDIT_RESET__CREDIT_RESET_XDMA__SHIFT 0x5
+#define SRBM_CREDIT_RESET__CREDIT_RESET_ODE_MASK 0x40
+#define SRBM_CREDIT_RESET__CREDIT_RESET_ODE__SHIFT 0x6
+#define SRBM_CREDIT_RESET__CREDIT_RESET_REGBB_MASK 0x80
+#define SRBM_CREDIT_RESET__CREDIT_RESET_REGBB__SHIFT 0x7
+#define SRBM_CREDIT_RESET__CREDIT_RESET_VP8_MASK 0x100
+#define SRBM_CREDIT_RESET__CREDIT_RESET_VP8__SHIFT 0x8
+#define SRBM_CREDIT_RESET__CREDIT_RESET_GRBM_MASK 0x200
+#define SRBM_CREDIT_RESET__CREDIT_RESET_GRBM__SHIFT 0x9
+#define SRBM_CREDIT_RESET__CREDIT_RESET_UVD_MASK 0x400
+#define SRBM_CREDIT_RESET__CREDIT_RESET_UVD__SHIFT 0xa
+#define SRBM_CREDIT_RESET__CREDIT_RESET_VCE0_MASK 0x800
+#define SRBM_CREDIT_RESET__CREDIT_RESET_VCE0__SHIFT 0xb
+#define SRBM_CREDIT_RESET__CREDIT_RESET_VCE1_MASK 0x1000
+#define SRBM_CREDIT_RESET__CREDIT_RESET_VCE1__SHIFT 0xc
+#define SRBM_CREDIT_RESET__CREDIT_RESET_ISP_MASK 0x2000
+#define SRBM_CREDIT_RESET__CREDIT_RESET_ISP__SHIFT 0xd
+#define SRBM_CREDIT_RESET__CREDIT_RESET_SAM_MASK 0x4000
+#define SRBM_CREDIT_RESET__CREDIT_RESET_SAM__SHIFT 0xe
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCB_MASK 0x8000
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCB__SHIFT 0xf
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC0_MASK 0x10000
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC0__SHIFT 0x10
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC1_MASK 0x20000
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC1__SHIFT 0x11
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC2_MASK 0x40000
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC2__SHIFT 0x12
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC3_MASK 0x80000
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC3__SHIFT 0x13
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC4_MASK 0x100000
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC4__SHIFT 0x14
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC5_MASK 0x200000
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC5__SHIFT 0x15
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC6_MASK 0x400000
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC6__SHIFT 0x16
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC7_MASK 0x800000
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC7__SHIFT 0x17
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD0_MASK 0x1000000
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD0__SHIFT 0x18
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD1_MASK 0x2000000
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD1__SHIFT 0x19
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD2_MASK 0x4000000
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD2__SHIFT 0x1a
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD3_MASK 0x8000000
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD3__SHIFT 0x1b
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD4_MASK 0x10000000
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD4__SHIFT 0x1c
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD5_MASK 0x20000000
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD5__SHIFT 0x1d
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD6_MASK 0x40000000
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD6__SHIFT 0x1e
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD7_MASK 0x80000000
+#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD7__SHIFT 0x1f
+#define CC_SYS_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
+#define CC_SYS_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
+#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
+#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
+#define CC_SYS_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
+#define CC_SYS_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
+#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
+#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
+#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
+#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
+#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
+#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
+#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_VP8_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define SRBM_VP8_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define SRBM_VP8_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define SRBM_VP8_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define SRBM_DEBUG__IGNORE_RDY_MASK 0x1
+#define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x0
+#define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x2
+#define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x1
+#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x4
+#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x2
+#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x10
+#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x4
+#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x20
+#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x5
+#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x40
+#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x6
+#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE_MASK 0x80
+#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x7
+#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x100
+#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x8
+#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE_MASK 0x200
+#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x9
+#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE_MASK 0x400
+#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xa
+#define SRBM_DEBUG__VP8_CLOCK_DOMAIN_OVERRIDE_MASK 0x800
+#define SRBM_DEBUG__VP8_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xb
+#define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x1
+#define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x0
+#define SRBM_DEBUG_SNAPSHOT__GIONB_RDY_MASK 0x2
+#define SRBM_DEBUG_SNAPSHOT__GIONB_RDY__SHIFT 0x1
+#define SRBM_DEBUG_SNAPSHOT__SMU_RDY_MASK 0x4
+#define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT 0x2
+#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY_MASK 0x8
+#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY__SHIFT 0x3
+#define SRBM_DEBUG_SNAPSHOT__ACP_RDY_MASK 0x10
+#define SRBM_DEBUG_SNAPSHOT__ACP_RDY__SHIFT 0x4
+#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x20
+#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x5
+#define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x40
+#define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x6
+#define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x80
+#define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x7
+#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x100
+#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x8
+#define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x200
+#define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x9
+#define SRBM_DEBUG_SNAPSHOT__VP8_RDY_MASK 0x400
+#define SRBM_DEBUG_SNAPSHOT__VP8_RDY__SHIFT 0xa
+#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x800
+#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0xb
+#define SRBM_DEBUG_SNAPSHOT__ODE_RDY_MASK 0x1000
+#define SRBM_DEBUG_SNAPSHOT__ODE_RDY__SHIFT 0xc
+#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x2000
+#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0xd
+#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x4000
+#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0xe
+#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x8000
+#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0xf
+#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x10000
+#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x10
+#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x20000
+#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x11
+#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x40000
+#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x12
+#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x80000
+#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x13
+#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x100000
+#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x14
+#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x200000
+#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x15
+#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x400000
+#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x16
+#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x800000
+#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x17
+#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x1000000
+#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x18
+#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x2000000
+#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x19
+#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x4000000
+#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x1a
+#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x8000000
+#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x1b
+#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000
+#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x1c
+#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY_MASK 0x20000000
+#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY__SHIFT 0x1d
+#define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY_MASK 0x40000000
+#define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY__SHIFT 0x1e
+#define SRBM_DEBUG_SNAPSHOT__ISP_RDY_MASK 0x80000000
+#define SRBM_DEBUG_SNAPSHOT__ISP_RDY__SHIFT 0x1f
+#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY_MASK 0x1
+#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY__SHIFT 0x0
+#define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc
+#define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3_MASK 0x40000
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3__SHIFT 0x12
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2_MASK 0x80000
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2__SHIFT 0x13
+#define SRBM_READ_ERROR__READ_REQUESTER_VCE0_MASK 0x100000
+#define SRBM_READ_ERROR__READ_REQUESTER_VCE0__SHIFT 0x14
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1_MASK 0x200000
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1__SHIFT 0x15
+#define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x400000
+#define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x16
+#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP_MASK 0x800000
+#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP__SHIFT 0x17
+#define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x1000000
+#define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x18
+#define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x2000000
+#define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x19
+#define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x4000000
+#define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x1a
+#define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP_MASK 0x8000000
+#define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP__SHIFT 0x1b
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA_MASK 0x10000000
+#define SRBM_READ_ERROR__READ_REQUESTER_SDMA__SHIFT 0x1c
+#define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000
+#define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x1d
+#define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000
+#define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
+#define SRBM_READ_ERROR2__READ_REQUESTER_ACP_MASK 0x1
+#define SRBM_READ_ERROR2__READ_REQUESTER_ACP__SHIFT 0x0
+#define SRBM_READ_ERROR2__READ_REQUESTER_ISP_MASK 0x2
+#define SRBM_READ_ERROR2__READ_REQUESTER_ISP__SHIFT 0x1
+#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1_MASK 0x4
+#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1__SHIFT 0x2
+#define SRBM_READ_ERROR2__READ_VF_MASK 0x800000
+#define SRBM_READ_ERROR2__READ_VF__SHIFT 0x17
+#define SRBM_READ_ERROR2__READ_VFID_MASK 0xf000000
+#define SRBM_READ_ERROR2__READ_VFID__SHIFT 0x18
+#define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x1
+#define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x0
+#define SRBM_INT_CNTL__RAERR_INT_MASK_MASK 0x2
+#define SRBM_INT_CNTL__RAERR_INT_MASK__SHIFT 0x1
+#define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x1
+#define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x0
+#define SRBM_INT_STATUS__RAERR_INT_STAT_MASK 0x2
+#define SRBM_INT_STATUS__RAERR_INT_STAT__SHIFT 0x1
+#define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x1
+#define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x0
+#define SRBM_INT_ACK__RAERR_INT_ACK_MASK 0x2
+#define SRBM_INT_ACK__RAERR_INT_ACK__SHIFT 0x1
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF_MASK 0x1
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF__SHIFT 0x0
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP_MASK 0x2
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP__SHIFT 0x1
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP_MASK 0x4
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP__SHIFT 0x2
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP_MASK 0x8
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP__SHIFT 0x3
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST_MASK 0x20
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST__SHIFT 0x5
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3_MASK 0x40
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3__SHIFT 0x6
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2_MASK 0x80
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2__SHIFT 0x7
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1_MASK 0x100
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1__SHIFT 0x8
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0_MASK 0x200
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0__SHIFT 0x9
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD_MASK 0x400
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD__SHIFT 0xa
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0_MASK 0x800
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0__SHIFT 0xb
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM_MASK 0x1000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM__SHIFT 0xc
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU_MASK 0x2000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU__SHIFT 0xd
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER_MASK 0x4000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER__SHIFT 0xe
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU_MASK 0x8000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU__SHIFT 0xf
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP_MASK 0x10000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP__SHIFT 0x10
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1_MASK 0x20000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1__SHIFT 0x11
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP_MASK 0x40000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP__SHIFT 0x12
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP_MASK 0x80000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP__SHIFT 0x13
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP_MASK 0x100000
+#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP__SHIFT 0x14
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION_MASK 0x1000000
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION__SHIFT 0x18
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW_MASK 0x2000000
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW__SHIFT 0x19
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW_MASK 0x4000000
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW__SHIFT 0x1a
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW_MASK 0x8000000
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW__SHIFT 0x1b
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION_MASK 0x10000000
+#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION__SHIFT 0x1c
+#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS_MASK 0x3fffc
+#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS__SHIFT 0x2
+#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF_MASK 0x80000
+#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF__SHIFT 0x13
+#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID_MASK 0xf00000
+#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID__SHIFT 0x14
+#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION_MASK 0x80000000
+#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION__SHIFT 0x1f
+#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR_MASK 0xffff
+#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR__SHIFT 0x0
+#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP_MASK 0x10000
+#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP__SHIFT 0x10
+#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD_MASK 0xffffffff
+#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD__SHIFT 0x0
+#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK_MASK 0xffff
+#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK__SHIFT 0x0
+#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK_MASK 0x10000
+#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK__SHIFT 0x10
+#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK_MASK 0xffffffff
+#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK__SHIFT 0x0
+#define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0xf
+#define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300
+#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
+#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
+#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
+#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
+#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
+#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffff
+#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x0
+#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffff
+#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x0
+#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffff
+#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x0
+#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffff
+#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x0
+#define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x3
+#define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
+#define SRBM_CAM_DATA__CAM_ADDR_MASK 0xffff
+#define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
+#define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
+#define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
+#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
+#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
+#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
+#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
+#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
+#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
+#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
+#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
+#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
+#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
+#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
+#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
+#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff
+#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0
+#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000
+#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10
+#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff
+#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0
+#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000
+#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10
+#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff
+#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0
+#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000
+#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10
+#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff
+#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0
+#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000
+#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10
+#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
+#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
+#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
+#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
+#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
+#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
+#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
+#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
+#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
+#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
+#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
+#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
+#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff
+#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0
+#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000
+#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10
+#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff
+#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0
+#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000
+#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10
+#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff
+#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0
+#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000
+#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10
+#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff
+#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0
+#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000
+#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10
+#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
+#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
+#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
+#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
+#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
+#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
+#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
+#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
+#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
+#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
+#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
+#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
+#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff
+#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0
+#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000
+#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10
+#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
+#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
+#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
+#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
+#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
+#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
+#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
+#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
+#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
+#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
+#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
+#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
+#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
+#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
+#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
+#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
+#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
+#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
+#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
+#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
+#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
+#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
+#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
+#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
+#define SRBM_SAM_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
+#define SRBM_SAM_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
+#define SRBM_SAM_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
+#define SRBM_SAM_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
+#define SRBM_SAM_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
+#define SRBM_SAM_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
+#define SRBM_SAM_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
+#define SRBM_SAM_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
+#define SRBM_SAM_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
+#define SRBM_SAM_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
+#define SRBM_SAM_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
+#define SRBM_SAM_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
+#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
+#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
+#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
+#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
+#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
+#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
+#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
+#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
+#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
+#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
+#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
+#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
+#define SRBM_VP8_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
+#define SRBM_VP8_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
+#define SRBM_VP8_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
+#define SRBM_VP8_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
+#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL_MASK 0xf
+#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL__SHIFT 0x0
+#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX_MASK 0xff
+#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX__SHIFT 0x0
+#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX_MASK 0xff00
+#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX__SHIFT 0x8
+#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX_MASK 0xff0000
+#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT 0x10
+#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK 0x20000000
+#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d
+#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000
+#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
+#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES_MASK 0x80000000
+#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f
+#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL_MASK 0xf
+#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL__SHIFT 0x0
+#define SRBM_GFX_CNTL_DATA__PIPEID_MASK 0x3
+#define SRBM_GFX_CNTL_DATA__PIPEID__SHIFT 0x0
+#define SRBM_GFX_CNTL_DATA__MEID_MASK 0xc
+#define SRBM_GFX_CNTL_DATA__MEID__SHIFT 0x2
+#define SRBM_GFX_CNTL_DATA__VMID_MASK 0xf0
+#define SRBM_GFX_CNTL_DATA__VMID__SHIFT 0x4
+#define SRBM_GFX_CNTL_DATA__QUEUEID_MASK 0x700
+#define SRBM_GFX_CNTL_DATA__QUEUEID__SHIFT 0x8
+#define SRBM_VF_ENABLE__VF_ENABLE_MASK 0x1
+#define SRBM_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE_MASK 0x1
+#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE__SHIFT 0x0
+#define SRBM_VIRT_RESET_REQ__VF_MASK 0xffff
+#define SRBM_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define SRBM_VIRT_RESET_REQ__PF_MASK 0x80000000
+#define SRBM_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0xffff0
+#define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x4
+#define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000
+#define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14
+#define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000
+#define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18
+#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000
+#define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c
+#define DH_TEST__DH_TEST_MASK 0x1
+#define DH_TEST__DH_TEST__SHIFT 0x0
+#define KHFS0__RESERVED_MASK 0xffffffff
+#define KHFS0__RESERVED__SHIFT 0x0
+#define KHFS1__RESERVED_MASK 0xffffffff
+#define KHFS1__RESERVED__SHIFT 0x0
+#define KHFS2__RESERVED_MASK 0xffffffff
+#define KHFS2__RESERVED__SHIFT 0x0
+#define KHFS3__RESERVED_MASK 0xffffffff
+#define KHFS3__RESERVED__SHIFT 0x0
+#define KSESSION0__RESERVED_MASK 0xffffffff
+#define KSESSION0__RESERVED__SHIFT 0x0
+#define KSESSION1__RESERVED_MASK 0xffffffff
+#define KSESSION1__RESERVED__SHIFT 0x0
+#define KSESSION2__RESERVED_MASK 0xffffffff
+#define KSESSION2__RESERVED__SHIFT 0x0
+#define KSESSION3__RESERVED_MASK 0xffffffff
+#define KSESSION3__RESERVED__SHIFT 0x0
+#define KSIG0__RESERVED_MASK 0xffffffff
+#define KSIG0__RESERVED__SHIFT 0x0
+#define KSIG1__RESERVED_MASK 0xffffffff
+#define KSIG1__RESERVED__SHIFT 0x0
+#define KSIG2__RESERVED_MASK 0xffffffff
+#define KSIG2__RESERVED__SHIFT 0x0
+#define KSIG3__RESERVED_MASK 0xffffffff
+#define KSIG3__RESERVED__SHIFT 0x0
+#define EXP0__RESERVED_MASK 0xffffffff
+#define EXP0__RESERVED__SHIFT 0x0
+#define EXP1__RESERVED_MASK 0xffffffff
+#define EXP1__RESERVED__SHIFT 0x0
+#define EXP2__RESERVED_MASK 0xffffffff
+#define EXP2__RESERVED__SHIFT 0x0
+#define EXP3__RESERVED_MASK 0xffffffff
+#define EXP3__RESERVED__SHIFT 0x0
+#define EXP4__RESERVED_MASK 0xffffffff
+#define EXP4__RESERVED__SHIFT 0x0
+#define EXP5__RESERVED_MASK 0xffffffff
+#define EXP5__RESERVED__SHIFT 0x0
+#define EXP6__RESERVED_MASK 0xffffffff
+#define EXP6__RESERVED__SHIFT 0x0
+#define EXP7__RESERVED_MASK 0xffffffff
+#define EXP7__RESERVED__SHIFT 0x0
+#define LX0__RESERVED_MASK 0xffffffff
+#define LX0__RESERVED__SHIFT 0x0
+#define LX1__RESERVED_MASK 0xffffffff
+#define LX1__RESERVED__SHIFT 0x0
+#define LX2__RESERVED_MASK 0xffffffff
+#define LX2__RESERVED__SHIFT 0x0
+#define LX3__RESERVED_MASK 0xffffffff
+#define LX3__RESERVED__SHIFT 0x0
+#define CLIENT2_K0__RESERVED_MASK 0xffffffff
+#define CLIENT2_K0__RESERVED__SHIFT 0x0
+#define CLIENT2_K1__RESERVED_MASK 0xffffffff
+#define CLIENT2_K1__RESERVED__SHIFT 0x0
+#define CLIENT2_K2__RESERVED_MASK 0xffffffff
+#define CLIENT2_K2__RESERVED__SHIFT 0x0
+#define CLIENT2_K3__RESERVED_MASK 0xffffffff
+#define CLIENT2_K3__RESERVED__SHIFT 0x0
+#define CLIENT2_CK0__RESERVED_MASK 0xffffffff
+#define CLIENT2_CK0__RESERVED__SHIFT 0x0
+#define CLIENT2_CK1__RESERVED_MASK 0xffffffff
+#define CLIENT2_CK1__RESERVED__SHIFT 0x0
+#define CLIENT2_CK2__RESERVED_MASK 0xffffffff
+#define CLIENT2_CK2__RESERVED__SHIFT 0x0
+#define CLIENT2_CK3__RESERVED_MASK 0xffffffff
+#define CLIENT2_CK3__RESERVED__SHIFT 0x0
+#define CLIENT2_CD0__RESERVED_MASK 0xffffffff
+#define CLIENT2_CD0__RESERVED__SHIFT 0x0
+#define CLIENT2_CD1__RESERVED_MASK 0xffffffff
+#define CLIENT2_CD1__RESERVED__SHIFT 0x0
+#define CLIENT2_CD2__RESERVED_MASK 0xffffffff
+#define CLIENT2_CD2__RESERVED__SHIFT 0x0
+#define CLIENT2_CD3__RESERVED_MASK 0xffffffff
+#define CLIENT2_CD3__RESERVED__SHIFT 0x0
+#define CLIENT2_BM__RESERVED_MASK 0xffffffff
+#define CLIENT2_BM__RESERVED__SHIFT 0x0
+#define CLIENT2_OFFSET__RESERVED_MASK 0xffffffff
+#define CLIENT2_OFFSET__RESERVED__SHIFT 0x0
+#define CLIENT2_STATUS__RESERVED_MASK 0xffffffff
+#define CLIENT2_STATUS__RESERVED__SHIFT 0x0
+#define CLIENT0_K0__RESERVED_MASK 0xffffffff
+#define CLIENT0_K0__RESERVED__SHIFT 0x0
+#define CLIENT0_K1__RESERVED_MASK 0xffffffff
+#define CLIENT0_K1__RESERVED__SHIFT 0x0
+#define CLIENT0_K2__RESERVED_MASK 0xffffffff
+#define CLIENT0_K2__RESERVED__SHIFT 0x0
+#define CLIENT0_K3__RESERVED_MASK 0xffffffff
+#define CLIENT0_K3__RESERVED__SHIFT 0x0
+#define CLIENT0_CK0__RESERVED_MASK 0xffffffff
+#define CLIENT0_CK0__RESERVED__SHIFT 0x0
+#define CLIENT0_CK1__RESERVED_MASK 0xffffffff
+#define CLIENT0_CK1__RESERVED__SHIFT 0x0
+#define CLIENT0_CK2__RESERVED_MASK 0xffffffff
+#define CLIENT0_CK2__RESERVED__SHIFT 0x0
+#define CLIENT0_CK3__RESERVED_MASK 0xffffffff
+#define CLIENT0_CK3__RESERVED__SHIFT 0x0
+#define CLIENT0_CD0__RESERVED_MASK 0xffffffff
+#define CLIENT0_CD0__RESERVED__SHIFT 0x0
+#define CLIENT0_CD1__RESERVED_MASK 0xffffffff
+#define CLIENT0_CD1__RESERVED__SHIFT 0x0
+#define CLIENT0_CD2__RESERVED_MASK 0xffffffff
+#define CLIENT0_CD2__RESERVED__SHIFT 0x0
+#define CLIENT0_CD3__RESERVED_MASK 0xffffffff
+#define CLIENT0_CD3__RESERVED__SHIFT 0x0
+#define CLIENT0_BM__RESERVED_MASK 0xffffffff
+#define CLIENT0_BM__RESERVED__SHIFT 0x0
+#define CLIENT0_OFFSET__RESERVED_MASK 0xffffffff
+#define CLIENT0_OFFSET__RESERVED__SHIFT 0x0
+#define CLIENT0_STATUS__RESERVED_MASK 0xffffffff
+#define CLIENT0_STATUS__RESERVED__SHIFT 0x0
+#define CLIENT1_K0__RESERVED_MASK 0xffffffff
+#define CLIENT1_K0__RESERVED__SHIFT 0x0
+#define CLIENT1_K1__RESERVED_MASK 0xffffffff
+#define CLIENT1_K1__RESERVED__SHIFT 0x0
+#define CLIENT1_K2__RESERVED_MASK 0xffffffff
+#define CLIENT1_K2__RESERVED__SHIFT 0x0
+#define CLIENT1_K3__RESERVED_MASK 0xffffffff
+#define CLIENT1_K3__RESERVED__SHIFT 0x0
+#define CLIENT1_CK0__RESERVED_MASK 0xffffffff
+#define CLIENT1_CK0__RESERVED__SHIFT 0x0
+#define CLIENT1_CK1__RESERVED_MASK 0xffffffff
+#define CLIENT1_CK1__RESERVED__SHIFT 0x0
+#define CLIENT1_CK2__RESERVED_MASK 0xffffffff
+#define CLIENT1_CK2__RESERVED__SHIFT 0x0
+#define CLIENT1_CK3__RESERVED_MASK 0xffffffff
+#define CLIENT1_CK3__RESERVED__SHIFT 0x0
+#define CLIENT1_CD0__RESERVED_MASK 0xffffffff
+#define CLIENT1_CD0__RESERVED__SHIFT 0x0
+#define CLIENT1_CD1__RESERVED_MASK 0xffffffff
+#define CLIENT1_CD1__RESERVED__SHIFT 0x0
+#define CLIENT1_CD2__RESERVED_MASK 0xffffffff
+#define CLIENT1_CD2__RESERVED__SHIFT 0x0
+#define CLIENT1_CD3__RESERVED_MASK 0xffffffff
+#define CLIENT1_CD3__RESERVED__SHIFT 0x0
+#define CLIENT1_BM__RESERVED_MASK 0xffffffff
+#define CLIENT1_BM__RESERVED__SHIFT 0x0
+#define CLIENT1_OFFSET__RESERVED_MASK 0xffffffff
+#define CLIENT1_OFFSET__RESERVED__SHIFT 0x0
+#define CLIENT1_PORT_STATUS__RESERVED_MASK 0xffffffff
+#define CLIENT1_PORT_STATUS__RESERVED__SHIFT 0x0
+#define KEFUSE0__RESERVED_MASK 0xffffffff
+#define KEFUSE0__RESERVED__SHIFT 0x0
+#define KEFUSE1__RESERVED_MASK 0xffffffff
+#define KEFUSE1__RESERVED__SHIFT 0x0
+#define KEFUSE2__RESERVED_MASK 0xffffffff
+#define KEFUSE2__RESERVED__SHIFT 0x0
+#define KEFUSE3__RESERVED_MASK 0xffffffff
+#define KEFUSE3__RESERVED__SHIFT 0x0
+#define HFS_SEED0__RESERVED_MASK 0xffffffff
+#define HFS_SEED0__RESERVED__SHIFT 0x0
+#define HFS_SEED1__RESERVED_MASK 0xffffffff
+#define HFS_SEED1__RESERVED__SHIFT 0x0
+#define HFS_SEED2__RESERVED_MASK 0xffffffff
+#define HFS_SEED2__RESERVED__SHIFT 0x0
+#define HFS_SEED3__RESERVED_MASK 0xffffffff
+#define HFS_SEED3__RESERVED__SHIFT 0x0
+#define RINGOSC_MASK__MASK_MASK 0xffff
+#define RINGOSC_MASK__MASK__SHIFT 0x0
+#define CLIENT0_OFFSET_HI__RESERVED_MASK 0xffffffff
+#define CLIENT0_OFFSET_HI__RESERVED__SHIFT 0x0
+#define CLIENT1_OFFSET_HI__RESERVED_MASK 0xffffffff
+#define CLIENT1_OFFSET_HI__RESERVED__SHIFT 0x0
+#define CLIENT2_OFFSET_HI__RESERVED_MASK 0xffffffff
+#define CLIENT2_OFFSET_HI__RESERVED__SHIFT 0x0
+#define SPU_PORT_STATUS__RESERVED_MASK 0xffffffff
+#define SPU_PORT_STATUS__RESERVED__SHIFT 0x0
+#define CLIENT3_OFFSET_HI__RESERVED_MASK 0xffffffff
+#define CLIENT3_OFFSET_HI__RESERVED__SHIFT 0x0
+#define CLIENT3_K0__RESERVED_MASK 0xffffffff
+#define CLIENT3_K0__RESERVED__SHIFT 0x0
+#define CLIENT3_K1__RESERVED_MASK 0xffffffff
+#define CLIENT3_K1__RESERVED__SHIFT 0x0
+#define CLIENT3_K2__RESERVED_MASK 0xffffffff
+#define CLIENT3_K2__RESERVED__SHIFT 0x0
+#define CLIENT3_K3__RESERVED_MASK 0xffffffff
+#define CLIENT3_K3__RESERVED__SHIFT 0x0
+#define CLIENT3_CK0__RESERVED_MASK 0xffffffff
+#define CLIENT3_CK0__RESERVED__SHIFT 0x0
+#define CLIENT3_CK1__RESERVED_MASK 0xffffffff
+#define CLIENT3_CK1__RESERVED__SHIFT 0x0
+#define CLIENT3_CK2__RESERVED_MASK 0xffffffff
+#define CLIENT3_CK2__RESERVED__SHIFT 0x0
+#define CLIENT3_CK3__RESERVED_MASK 0xffffffff
+#define CLIENT3_CK3__RESERVED__SHIFT 0x0
+#define CLIENT3_CD0__RESERVED_MASK 0xffffffff
+#define CLIENT3_CD0__RESERVED__SHIFT 0x0
+#define CLIENT3_CD1__RESERVED_MASK 0xffffffff
+#define CLIENT3_CD1__RESERVED__SHIFT 0x0
+#define CLIENT3_CD2__RESERVED_MASK 0xffffffff
+#define CLIENT3_CD2__RESERVED__SHIFT 0x0
+#define CLIENT3_CD3__RESERVED_MASK 0xffffffff
+#define CLIENT3_CD3__RESERVED__SHIFT 0x0
+#define CLIENT3_BM__RESERVED_MASK 0xffffffff
+#define CLIENT3_BM__RESERVED__SHIFT 0x0
+#define CLIENT3_OFFSET__RESERVED_MASK 0xffffffff
+#define CLIENT3_OFFSET__RESERVED__SHIFT 0x0
+#define CLIENT3_STATUS__RESERVED_MASK 0xffffffff
+#define CLIENT3_STATUS__RESERVED__SHIFT 0x0
+#define CLIENT4_OFFSET_HI__RESERVED_MASK 0xffffffff
+#define CLIENT4_OFFSET_HI__RESERVED__SHIFT 0x0
+#define CLIENT4_K0__RESERVED_MASK 0xffffffff
+#define CLIENT4_K0__RESERVED__SHIFT 0x0
+#define CLIENT4_K1__RESERVED_MASK 0xffffffff
+#define CLIENT4_K1__RESERVED__SHIFT 0x0
+#define CLIENT4_K2__RESERVED_MASK 0xffffffff
+#define CLIENT4_K2__RESERVED__SHIFT 0x0
+#define CLIENT4_K3__RESERVED_MASK 0xffffffff
+#define CLIENT4_K3__RESERVED__SHIFT 0x0
+#define CLIENT4_CK0__RESERVED_MASK 0xffffffff
+#define CLIENT4_CK0__RESERVED__SHIFT 0x0
+#define CLIENT4_CK1__RESERVED_MASK 0xffffffff
+#define CLIENT4_CK1__RESERVED__SHIFT 0x0
+#define CLIENT4_CK2__RESERVED_MASK 0xffffffff
+#define CLIENT4_CK2__RESERVED__SHIFT 0x0
+#define CLIENT4_CK3__RESERVED_MASK 0xffffffff
+#define CLIENT4_CK3__RESERVED__SHIFT 0x0
+#define CLIENT4_CD0__RESERVED_MASK 0xffffffff
+#define CLIENT4_CD0__RESERVED__SHIFT 0x0
+#define CLIENT4_CD1__RESERVED_MASK 0xffffffff
+#define CLIENT4_CD1__RESERVED__SHIFT 0x0
+#define CLIENT4_CD2__RESERVED_MASK 0xffffffff
+#define CLIENT4_CD2__RESERVED__SHIFT 0x0
+#define CLIENT4_CD3__RESERVED_MASK 0xffffffff
+#define CLIENT4_CD3__RESERVED__SHIFT 0x0
+#define CLIENT4_BM__RESERVED_MASK 0xffffffff
+#define CLIENT4_BM__RESERVED__SHIFT 0x0
+#define CLIENT4_OFFSET__RESERVED_MASK 0xffffffff
+#define CLIENT4_OFFSET__RESERVED__SHIFT 0x0
+#define CLIENT4_STATUS__RESERVED_MASK 0xffffffff
+#define CLIENT4_STATUS__RESERVED__SHIFT 0x0
+#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX_MASK 0xff
+#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX__SHIFT 0x0
+#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN_MASK 0x100
+#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
+#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA_MASK 0xffffffff
+#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA__SHIFT 0x0
+#define SDMA0_UCODE_ADDR__VALUE_MASK 0x1fff
+#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0
+#define SDMA0_UCODE_DATA__VALUE_MASK 0xffffffff
+#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0
+#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100
+#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
+#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x200
+#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
+#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x400
+#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
+#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x800
+#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
+#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x3ff000
+#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
+#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0xf
+#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x1
+#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0
+#define SDMA0_CNTL__ATC_L1_ENABLE_MASK 0x2
+#define SDMA0_CNTL__ATC_L1_ENABLE__SHIFT 0x1
+#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4
+#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
+#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x8
+#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
+#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x10
+#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x20
+#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
+#define SDMA0_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800
+#define SDMA0_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb
+#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x20000
+#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
+#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000
+#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
+#define SDMA0_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000
+#define SDMA0_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16
+#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000
+#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
+#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000
+#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
+#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000
+#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
+#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
+#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
+#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2
+#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
+#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4
+#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
+#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000
+#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
+#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000
+#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
+#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000
+#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
+#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000
+#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
+#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000
+#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
+#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000
+#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
+#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define SDMA0_HASH__CHANNEL_BITS_MASK 0x7
+#define SDMA0_HASH__CHANNEL_BITS__SHIFT 0x0
+#define SDMA0_HASH__BANK_BITS_MASK 0x70
+#define SDMA0_HASH__BANK_BITS__SHIFT 0x4
+#define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK 0x700
+#define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
+#define SDMA0_HASH__BANK_XOR_COUNT_MASK 0x7000
+#define SDMA0_HASH__BANK_XOR_COUNT__SHIFT 0xc
+#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff
+#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
+#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc
+#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
+#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc
+#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
+#define SDMA0_PROGRAM__STREAM_MASK 0xffffffff
+#define SDMA0_PROGRAM__STREAM__SHIFT 0x0
+#define SDMA0_STATUS_REG__IDLE_MASK 0x1
+#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0
+#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x2
+#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
+#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x4
+#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2
+#define SDMA0_STATUS_REG__RB_FULL_MASK 0x8
+#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3
+#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x10
+#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
+#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x20
+#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
+#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x40
+#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
+#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x80
+#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
+#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x100
+#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
+#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x200
+#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9
+#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x400
+#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
+#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
+#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
+#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x1000
+#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc
+#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x2000
+#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
+#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x4000
+#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe
+#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000
+#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
+#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000
+#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
+#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000
+#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
+#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000
+#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
+#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x80000
+#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
+#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000
+#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
+#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000
+#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
+#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000
+#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
+#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000
+#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
+#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x4000000
+#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a
+#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000
+#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
+#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000
+#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
+#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000
+#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e
+#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000
+#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
+#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
+#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
+#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x2
+#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
+#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4
+#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
+#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8
+#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
+#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x10
+#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
+#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x20
+#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
+#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x40
+#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
+#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x200
+#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
+#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400
+#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
+#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x2000
+#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
+#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000
+#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
+#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x20000
+#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
+#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x40000
+#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
+#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x3
+#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
+#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
+#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100
+#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200
+#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9
+#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
+#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
+#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
+#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
+#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA0_F32_CNTL__HALT_MASK 0x1
+#define SDMA0_F32_CNTL__HALT__SHIFT 0x0
+#define SDMA0_F32_CNTL__STEP_MASK 0x2
+#define SDMA0_F32_CNTL__STEP__SHIFT 0x1
+#define SDMA0_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc
+#define SDMA0_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2
+#define SDMA0_FREEZE__FREEZE_MASK 0x10
+#define SDMA0_FREEZE__FREEZE__SHIFT 0x4
+#define SDMA0_FREEZE__FROZEN_MASK 0x20
+#define SDMA0_FREEZE__FROZEN__SHIFT 0x5
+#define SDMA0_FREEZE__F32_FREEZE_MASK 0x40
+#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6
+#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0xf
+#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00
+#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000
+#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0xf
+#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00
+#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000
+#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA_POWER_GATING__PG_CNTL_ENABLE_MASK 0x1
+#define SDMA_POWER_GATING__PG_CNTL_ENABLE__SHIFT 0x0
+#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK 0x2
+#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE__SHIFT 0x1
+#define SDMA_POWER_GATING__PG_STATE_VALID_MASK 0x4
+#define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT 0x2
+#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x30
+#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4
+#define SDMA_POWER_GATING__SDMA0_ON_CONDITION_MASK 0x40
+#define SDMA_POWER_GATING__SDMA0_ON_CONDITION__SHIFT 0x6
+#define SDMA_POWER_GATING__SDMA1_ON_CONDITION_MASK 0x80
+#define SDMA_POWER_GATING__SDMA1_ON_CONDITION__SHIFT 0x7
+#define SDMA_POWER_GATING__POWER_OFF_DELAY_MASK 0xfff00
+#define SDMA_POWER_GATING__POWER_OFF_DELAY__SHIFT 0x8
+#define SDMA_POWER_GATING__POWER_ON_DELAY_MASK 0xfff00000
+#define SDMA_POWER_GATING__POWER_ON_DELAY__SHIFT 0x14
+#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0xff
+#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
+#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x100
+#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
+#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x200
+#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
+#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x400
+#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
+#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x800
+#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
+#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x1000
+#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc
+#define SDMA_PGFSM_CONFIG__READ_MASK 0x2000
+#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd
+#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000
+#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
+#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000
+#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
+#define SDMA_PGFSM_WRITE__VALUE_MASK 0xffffffff
+#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0
+#define SDMA_PGFSM_READ__VALUE_MASK 0xffffff
+#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0
+#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x2
+#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4
+#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
+#define SDMA0_VM_CNTL__CMD_MASK 0xf
+#define SDMA0_VM_CNTL__CMD__SHIFT 0x0
+#define SDMA0_VM_CTX_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2
+#define SDMA0_VM_CTX_HI__ADDR_MASK 0xffffffff
+#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0
+#define SDMA0_STATUS2_REG__ID_MASK 0x3
+#define SDMA0_STATUS2_REG__ID__SHIFT 0x0
+#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0xffc
+#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
+#define SDMA0_STATUS2_REG__CURRENT_FCN_IDLE_MASK 0xc000
+#define SDMA0_STATUS2_REG__CURRENT_FCN_IDLE__SHIFT 0xe
+#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xffff0000
+#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10
+#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0xf
+#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000
+#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x1
+#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0
+#define SDMA0_VM_CTX_CNTL__VMID_MASK 0xf0
+#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4
+#define SDMA0_VIRT_RESET_REQ__VF_MASK 0xffff
+#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000
+#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x1
+#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x3ff
+#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0
+#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000
+#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
+#define SDMA0_ID__DEVICE_ID_MASK 0xff
+#define SDMA0_ID__DEVICE_ID__SHIFT 0x0
+#define SDMA0_VERSION__VALUE_MASK 0xffff
+#define SDMA0_VERSION__VALUE__SHIFT 0x0
+#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7fffffff
+#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
+#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000
+#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
+#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xffffffff
+#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
+#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xffffffff
+#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
+#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0xffff
+#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x0
+#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xffff0000
+#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x10
+#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL_MASK 0x1
+#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL__SHIFT 0x0
+#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT_MASK 0x2
+#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x1
+#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT_MASK 0x4
+#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x2
+#define SDMA0_PERF_REG_TYPE0__RESERVED_31_3_MASK 0xfffffff8
+#define SDMA0_PERF_REG_TYPE0__RESERVED_31_3__SHIFT 0x3
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x1
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x2
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x4
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x8
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x10
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x4
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x20
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x5
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x40
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x6
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x80
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x7
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x100
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x200
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x400
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x800
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x1000
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x2000
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x4000
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x8000
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x10000
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x20000
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x40000
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x80000
+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_VIRTUAL_ADDR_MASK 0x80
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_VIRTUAL_ADDR__SHIFT 0x7
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_APE1_CNTL_MASK 0x100
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_APE1_CNTL__SHIFT 0x8
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x200
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x400
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa
+#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG1_MASK 0x800
+#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG1__SHIFT 0xb
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x1000
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x2000
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd
+#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x4000
+#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x8000
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x10000
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x20000
+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11
+#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xfffc0000
+#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x12
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x1
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x2
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x4
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x8
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x10
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x20
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x40
+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x6
+#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xffffff80
+#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0x7
+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x1
+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0
+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x2
+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1
+#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x4
+#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x2
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x8
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x3
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x4
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20
+#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x5
+#define SDMA0_PUB_REG_TYPE0__SDMA0_TILING_CONFIG_MASK 0x40
+#define SDMA0_PUB_REG_TYPE0__SDMA0_TILING_CONFIG__SHIFT 0x6
+#define SDMA0_PUB_REG_TYPE0__SDMA0_HASH_MASK 0x80
+#define SDMA0_PUB_REG_TYPE0__SDMA0_HASH__SHIFT 0x7
+#define SDMA0_PUB_REG_TYPE0__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x200
+#define SDMA0_PUB_REG_TYPE0__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x9
+#define SDMA0_PUB_REG_TYPE0__SDMA0_RB_RPTR_FETCH_MASK 0x400
+#define SDMA0_PUB_REG_TYPE0__SDMA0_RB_RPTR_FETCH__SHIFT 0xa
+#define SDMA0_PUB_REG_TYPE0__SDMA0_IB_OFFSET_FETCH_MASK 0x800
+#define SDMA0_PUB_REG_TYPE0__SDMA0_IB_OFFSET_FETCH__SHIFT 0xb
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PROGRAM_MASK 0x1000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PROGRAM__SHIFT 0xc
+#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS_REG_MASK 0x2000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS_REG__SHIFT 0xd
+#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS1_REG_MASK 0x4000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS1_REG__SHIFT 0xe
+#define SDMA0_PUB_REG_TYPE0__SDMA0_RD_BURST_CNTL_MASK 0x8000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_RD_BURST_CNTL__SHIFT 0xf
+#define SDMA0_PUB_REG_TYPE0__RESERVED_16_MASK 0x10000
+#define SDMA0_PUB_REG_TYPE0__RESERVED_16__SHIFT 0x10
+#define SDMA0_PUB_REG_TYPE0__RESERVED_17_MASK 0x20000
+#define SDMA0_PUB_REG_TYPE0__RESERVED_17__SHIFT 0x11
+#define SDMA0_PUB_REG_TYPE0__SDMA0_F32_CNTL_MASK 0x40000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_F32_CNTL__SHIFT 0x12
+#define SDMA0_PUB_REG_TYPE0__SDMA0_FREEZE_MASK 0x80000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_FREEZE__SHIFT 0x13
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE0_QUANTUM_MASK 0x100000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE0_QUANTUM__SHIFT 0x14
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE1_QUANTUM_MASK 0x200000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE1_QUANTUM__SHIFT 0x15
+#define SDMA0_PUB_REG_TYPE0__SDMA_POWER_GATING_MASK 0x400000
+#define SDMA0_PUB_REG_TYPE0__SDMA_POWER_GATING__SHIFT 0x16
+#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_CONFIG_MASK 0x800000
+#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_CONFIG__SHIFT 0x17
+#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_WRITE_MASK 0x1000000
+#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_WRITE__SHIFT 0x18
+#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_READ_MASK 0x2000000
+#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_READ__SHIFT 0x19
+#define SDMA0_PUB_REG_TYPE0__SDMA0_EDC_CONFIG_MASK 0x4000000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_EDC_CONFIG__SHIFT 0x1a
+#define SDMA0_PUB_REG_TYPE0__SDMA0_BA_THRESHOLD_MASK 0x8000000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_BA_THRESHOLD__SHIFT 0x1b
+#define SDMA0_PUB_REG_TYPE0__SDMA0_DEVICE_ID_MASK 0x10000000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_DEVICE_ID__SHIFT 0x1c
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VERSION_MASK 0x20000000
+#define SDMA0_PUB_REG_TYPE0__SDMA0_VERSION__SHIFT 0x1d
+#define SDMA0_PUB_REG_TYPE0__RESERVED_MASK 0xc0000000
+#define SDMA0_PUB_REG_TYPE0__RESERVED__SHIFT 0x1e
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL_MASK 0x1
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL__SHIFT 0x0
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO_MASK 0x2
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO__SHIFT 0x1
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI_MASK 0x4
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI__SHIFT 0x2
+#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x8
+#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x3
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ACTIVE_FCN_ID_MASK 0x10
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ACTIVE_FCN_ID__SHIFT 0x4
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_CNTL_MASK 0x20
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_CNTL__SHIFT 0x5
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VIRT_RESET_REQ_MASK 0x40
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VIRT_RESET_REQ__SHIFT 0x6
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VF_ENABLE_MASK 0x80
+#define SDMA0_PUB_REG_TYPE1__SDMA0_VF_ENABLE__SHIFT 0x7
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x100
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x8
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x200
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x9
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x400
+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0xa
+#define SDMA0_PUB_REG_TYPE1__RESERVED_MASK 0xfffff800
+#define SDMA0_PUB_REG_TYPE1__RESERVED__SHIFT 0xb
+#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_GFX_DOORBELL__OFFSET_MASK 0x1fffff
+#define SDMA0_GFX_DOORBELL__OFFSET__SHIFT 0x0
+#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000
+#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000
+#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000
+#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
+#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000
+#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
+#define SDMA0_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA0_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA0_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2
+#define SDMA0_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1
+#define SDMA0_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA0_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA0_GFX_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA0_GFX_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA0_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA0_GFX_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1
+#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xfffffffc
+#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff
+#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x1
+#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff
+#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xffffffff
+#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xffffffff
+#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xffffffff
+#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xffffffff
+#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xffffffff
+#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xffffffff
+#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1
+#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2
+#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
+#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
+#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC0_DOORBELL__OFFSET_MASK 0x1fffff
+#define SDMA0_RLC0_DOORBELL__OFFSET__SHIFT 0x0
+#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000
+#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000
+#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA0_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2
+#define SDMA0_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1
+#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA0_RLC0_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA0_RLC0_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA0_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
+#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc
+#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff
+#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1
+#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff
+#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xffffffff
+#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xffffffff
+#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xffffffff
+#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xffffffff
+#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xffffffff
+#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xffffffff
+#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1
+#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2
+#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
+#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
+#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA0_RLC1_DOORBELL__OFFSET_MASK 0x1fffff
+#define SDMA0_RLC1_DOORBELL__OFFSET__SHIFT 0x0
+#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000
+#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000
+#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA0_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA0_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA0_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2
+#define SDMA0_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1
+#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA0_RLC1_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA0_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
+#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc
+#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff
+#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1
+#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff
+#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xffffffff
+#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xffffffff
+#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xffffffff
+#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xffffffff
+#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xffffffff
+#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xffffffff
+#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1
+#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2
+#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
+#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
+#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_UCODE_ADDR__VALUE_MASK 0x1fff
+#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0
+#define SDMA1_UCODE_DATA__VALUE_MASK 0xffffffff
+#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0
+#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100
+#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
+#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x200
+#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
+#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x400
+#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
+#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x800
+#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
+#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x3ff000
+#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
+#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0xf
+#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x1
+#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0
+#define SDMA1_CNTL__ATC_L1_ENABLE_MASK 0x2
+#define SDMA1_CNTL__ATC_L1_ENABLE__SHIFT 0x1
+#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4
+#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
+#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x8
+#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
+#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x10
+#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x20
+#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
+#define SDMA1_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800
+#define SDMA1_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb
+#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x20000
+#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
+#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000
+#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
+#define SDMA1_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000
+#define SDMA1_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16
+#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000
+#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
+#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000
+#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
+#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000
+#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
+#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
+#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
+#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2
+#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
+#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4
+#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
+#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000
+#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
+#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000
+#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
+#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000
+#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
+#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000
+#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
+#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000
+#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
+#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000
+#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
+#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define SDMA1_HASH__CHANNEL_BITS_MASK 0x7
+#define SDMA1_HASH__CHANNEL_BITS__SHIFT 0x0
+#define SDMA1_HASH__BANK_BITS_MASK 0x70
+#define SDMA1_HASH__BANK_BITS__SHIFT 0x4
+#define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK 0x700
+#define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
+#define SDMA1_HASH__BANK_XOR_COUNT_MASK 0x7000
+#define SDMA1_HASH__BANK_XOR_COUNT__SHIFT 0xc
+#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff
+#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
+#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc
+#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
+#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc
+#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
+#define SDMA1_PROGRAM__STREAM_MASK 0xffffffff
+#define SDMA1_PROGRAM__STREAM__SHIFT 0x0
+#define SDMA1_STATUS_REG__IDLE_MASK 0x1
+#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0
+#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x2
+#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1
+#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x4
+#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2
+#define SDMA1_STATUS_REG__RB_FULL_MASK 0x8
+#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3
+#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x10
+#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
+#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x20
+#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
+#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x40
+#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
+#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x80
+#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
+#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x100
+#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
+#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x200
+#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9
+#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x400
+#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa
+#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
+#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
+#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x1000
+#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc
+#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x2000
+#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
+#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x4000
+#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe
+#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000
+#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
+#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000
+#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
+#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000
+#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
+#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000
+#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
+#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x80000
+#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
+#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000
+#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
+#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000
+#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
+#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000
+#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
+#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000
+#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
+#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x4000000
+#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a
+#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000
+#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
+#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000
+#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
+#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000
+#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e
+#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000
+#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
+#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
+#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
+#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2
+#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
+#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4
+#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
+#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8
+#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
+#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x10
+#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
+#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x20
+#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
+#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x40
+#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
+#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x200
+#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
+#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400
+#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
+#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x2000
+#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
+#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000
+#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
+#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x20000
+#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
+#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x40000
+#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
+#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x3
+#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
+#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
+#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100
+#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200
+#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9
+#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
+#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
+#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
+#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
+#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
+#define SDMA1_F32_CNTL__HALT_MASK 0x1
+#define SDMA1_F32_CNTL__HALT__SHIFT 0x0
+#define SDMA1_F32_CNTL__STEP_MASK 0x2
+#define SDMA1_F32_CNTL__STEP__SHIFT 0x1
+#define SDMA1_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc
+#define SDMA1_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2
+#define SDMA1_FREEZE__FREEZE_MASK 0x10
+#define SDMA1_FREEZE__FREEZE__SHIFT 0x4
+#define SDMA1_FREEZE__FROZEN_MASK 0x20
+#define SDMA1_FREEZE__FROZEN__SHIFT 0x5
+#define SDMA1_FREEZE__F32_FREEZE_MASK 0x40
+#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6
+#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0xf
+#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0xffff00
+#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000
+#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0xf
+#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0
+#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0xffff00
+#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8
+#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000
+#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
+#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x2
+#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4
+#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
+#define SDMA1_VM_CNTL__CMD_MASK 0xf
+#define SDMA1_VM_CNTL__CMD__SHIFT 0x0
+#define SDMA1_VM_CTX_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2
+#define SDMA1_VM_CTX_HI__ADDR_MASK 0xffffffff
+#define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0
+#define SDMA1_STATUS2_REG__ID_MASK 0x3
+#define SDMA1_STATUS2_REG__ID__SHIFT 0x0
+#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0xffc
+#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
+#define SDMA1_STATUS2_REG__CURRENT_FCN_IDLE_MASK 0xc000
+#define SDMA1_STATUS2_REG__CURRENT_FCN_IDLE__SHIFT 0xe
+#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xffff0000
+#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10
+#define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0xf
+#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0
+#define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000
+#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f
+#define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x1
+#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0
+#define SDMA1_VM_CTX_CNTL__VMID_MASK 0xf0
+#define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4
+#define SDMA1_VIRT_RESET_REQ__VF_MASK 0xffff
+#define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000
+#define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x1
+#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x3ff
+#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0
+#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000
+#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
+#define SDMA1_ID__DEVICE_ID_MASK 0xff
+#define SDMA1_ID__DEVICE_ID__SHIFT 0x0
+#define SDMA1_VERSION__VALUE_MASK 0xffff
+#define SDMA1_VERSION__VALUE__SHIFT 0x0
+#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7fffffff
+#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0
+#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000
+#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f
+#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xffffffff
+#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0
+#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xffffffff
+#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0
+#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0xffff
+#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x0
+#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xffff0000
+#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x10
+#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL_MASK 0x1
+#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL__SHIFT 0x0
+#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT_MASK 0x2
+#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x1
+#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT_MASK 0x4
+#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x2
+#define SDMA1_PERF_REG_TYPE0__RESERVED_31_3_MASK 0xfffffff8
+#define SDMA1_PERF_REG_TYPE0__RESERVED_31_3__SHIFT 0x3
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x1
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x2
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x4
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x8
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x10
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x4
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x20
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x5
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x40
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x6
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x80
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x7
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x100
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x200
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x400
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x800
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x1000
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x2000
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x4000
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x8000
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x10000
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x20000
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x40000
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x80000
+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13
+#define SDMA1_CONTEXT_REG_TYPE0__RESERVED_MASK 0xfff00000
+#define SDMA1_CONTEXT_REG_TYPE0__RESERVED__SHIFT 0x14
+#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG0_MASK 0x7f
+#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG0__SHIFT 0x0
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_VIRTUAL_ADDR_MASK 0x80
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_VIRTUAL_ADDR__SHIFT 0x7
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_APE1_CNTL_MASK 0x100
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_APE1_CNTL__SHIFT 0x8
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x200
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x400
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa
+#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x800
+#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xb
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x1000
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x2000
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd
+#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG3_MASK 0x4000
+#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG3__SHIFT 0xe
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x8000
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x10000
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x20000
+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11
+#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xfffc0000
+#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x12
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x1
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x2
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x4
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x8
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x10
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x20
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x40
+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x6
+#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xffffff80
+#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0x7
+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x1
+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0
+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x2
+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1
+#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x4
+#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x2
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x8
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x3
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x4
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20
+#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x5
+#define SDMA1_PUB_REG_TYPE0__SDMA1_TILING_CONFIG_MASK 0x40
+#define SDMA1_PUB_REG_TYPE0__SDMA1_TILING_CONFIG__SHIFT 0x6
+#define SDMA1_PUB_REG_TYPE0__SDMA1_HASH_MASK 0x80
+#define SDMA1_PUB_REG_TYPE0__SDMA1_HASH__SHIFT 0x7
+#define SDMA1_PUB_REG_TYPE0__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x200
+#define SDMA1_PUB_REG_TYPE0__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x9
+#define SDMA1_PUB_REG_TYPE0__SDMA1_RB_RPTR_FETCH_MASK 0x400
+#define SDMA1_PUB_REG_TYPE0__SDMA1_RB_RPTR_FETCH__SHIFT 0xa
+#define SDMA1_PUB_REG_TYPE0__SDMA1_IB_OFFSET_FETCH_MASK 0x800
+#define SDMA1_PUB_REG_TYPE0__SDMA1_IB_OFFSET_FETCH__SHIFT 0xb
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PROGRAM_MASK 0x1000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PROGRAM__SHIFT 0xc
+#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS_REG_MASK 0x2000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS_REG__SHIFT 0xd
+#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS1_REG_MASK 0x4000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS1_REG__SHIFT 0xe
+#define SDMA1_PUB_REG_TYPE0__SDMA1_RD_BURST_CNTL_MASK 0x8000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_RD_BURST_CNTL__SHIFT 0xf
+#define SDMA1_PUB_REG_TYPE0__RESERVED_16_MASK 0x10000
+#define SDMA1_PUB_REG_TYPE0__RESERVED_16__SHIFT 0x10
+#define SDMA1_PUB_REG_TYPE0__RESERVED_17_MASK 0x20000
+#define SDMA1_PUB_REG_TYPE0__RESERVED_17__SHIFT 0x11
+#define SDMA1_PUB_REG_TYPE0__SDMA1_F32_CNTL_MASK 0x40000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_F32_CNTL__SHIFT 0x12
+#define SDMA1_PUB_REG_TYPE0__SDMA1_FREEZE_MASK 0x80000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_FREEZE__SHIFT 0x13
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE0_QUANTUM_MASK 0x100000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE0_QUANTUM__SHIFT 0x14
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE1_QUANTUM_MASK 0x200000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE1_QUANTUM__SHIFT 0x15
+#define SDMA1_PUB_REG_TYPE0__VOID_REG0_MASK 0x3c00000
+#define SDMA1_PUB_REG_TYPE0__VOID_REG0__SHIFT 0x16
+#define SDMA1_PUB_REG_TYPE0__SDMA1_EDC_CONFIG_MASK 0x4000000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_EDC_CONFIG__SHIFT 0x1a
+#define SDMA1_PUB_REG_TYPE0__SDMA1_BA_THRESHOLD_MASK 0x8000000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_BA_THRESHOLD__SHIFT 0x1b
+#define SDMA1_PUB_REG_TYPE0__SDMA1_DEVICE_ID_MASK 0x10000000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_DEVICE_ID__SHIFT 0x1c
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VERSION_MASK 0x20000000
+#define SDMA1_PUB_REG_TYPE0__SDMA1_VERSION__SHIFT 0x1d
+#define SDMA1_PUB_REG_TYPE0__RESERVED_MASK 0xc0000000
+#define SDMA1_PUB_REG_TYPE0__RESERVED__SHIFT 0x1e
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL_MASK 0x1
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL__SHIFT 0x0
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO_MASK 0x2
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO__SHIFT 0x1
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI_MASK 0x4
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI__SHIFT 0x2
+#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x8
+#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x3
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ACTIVE_FCN_ID_MASK 0x10
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ACTIVE_FCN_ID__SHIFT 0x4
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_CNTL_MASK 0x20
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_CNTL__SHIFT 0x5
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VIRT_RESET_REQ_MASK 0x40
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VIRT_RESET_REQ__SHIFT 0x6
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VF_ENABLE_MASK 0x80
+#define SDMA1_PUB_REG_TYPE1__SDMA1_VF_ENABLE__SHIFT 0x7
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x100
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x8
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x200
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x9
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x400
+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0xa
+#define SDMA1_PUB_REG_TYPE1__RESERVED_MASK 0xfffff800
+#define SDMA1_PUB_REG_TYPE1__RESERVED__SHIFT 0xb
+#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_GFX_DOORBELL__OFFSET_MASK 0x1fffff
+#define SDMA1_GFX_DOORBELL__OFFSET__SHIFT 0x0
+#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000
+#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000
+#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000
+#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
+#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000
+#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
+#define SDMA1_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA1_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA1_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2
+#define SDMA1_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1
+#define SDMA1_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA1_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA1_GFX_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA1_GFX_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA1_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA1_GFX_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1
+#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xfffffffc
+#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff
+#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x1
+#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff
+#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xffffffff
+#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xffffffff
+#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xffffffff
+#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xffffffff
+#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xffffffff
+#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xffffffff
+#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1
+#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2
+#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
+#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
+#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC0_DOORBELL__OFFSET_MASK 0x1fffff
+#define SDMA1_RLC0_DOORBELL__OFFSET__SHIFT 0x0
+#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000
+#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000
+#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA1_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA1_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2
+#define SDMA1_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1
+#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA1_RLC0_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA1_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA1_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
+#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc
+#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff
+#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1
+#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff
+#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xffffffff
+#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xffffffff
+#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xffffffff
+#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xffffffff
+#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xffffffff
+#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xffffffff
+#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1
+#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2
+#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
+#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
+#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
+#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e
+#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
+#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
+#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000
+#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
+#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000
+#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
+#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xffffffff
+#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff
+#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc
+#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
+#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
+#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
+#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
+#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
+#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
+#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000
+#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
+#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc
+#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc
+#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
+#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0
+#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
+#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0xfffff
+#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0
+#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
+#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
+#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
+#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
+#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4
+#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
+#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8
+#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
+#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70
+#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
+#define SDMA1_RLC1_DOORBELL__OFFSET_MASK 0x1fffff
+#define SDMA1_RLC1_DOORBELL__OFFSET__SHIFT 0x0
+#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000
+#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
+#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000
+#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
+#define SDMA1_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
+#define SDMA1_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0
+#define SDMA1_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2
+#define SDMA1_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1
+#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10
+#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4
+#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
+#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
+#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
+#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
+#define SDMA1_RLC1_APE1_CNTL__BASE_MASK 0xffff
+#define SDMA1_RLC1_APE1_CNTL__BASE__SHIFT 0x0
+#define SDMA1_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000
+#define SDMA1_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10
+#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
+#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
+#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc
+#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
+#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff
+#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
+#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
+#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
+#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
+#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
+#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff
+#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
+#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff
+#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
+#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1
+#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
+#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff
+#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xffffffff
+#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xffffffff
+#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xffffffff
+#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xffffffff
+#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xffffffff
+#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xffffffff
+#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1
+#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0
+#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2
+#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
+#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0
+#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
+#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100
+#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8
+#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x7
+#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x0
+#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x1f8
+#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x3
+#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x600
+#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9
+#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x1800
+#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x180000
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x200000
+#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15
+#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x400000
+#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x16
+#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x800000
+#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x17
+#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0xf000000
+#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x18
+#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000
+#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d
+#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000
+#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e
+#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000
+#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f
+#define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffff
+#define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x0
+#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x1
+#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x0
+#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x1e
+#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x1
+#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x60
+#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x5
+#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x380
+#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x7
+#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x1c00
+#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0xa
+#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x6000
+#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0xd
+#define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x8000
+#define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0xf
+#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x10000
+#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x10
+#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0xe0000
+#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x11
+#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x300000
+#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x14
+#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0xc00000
+#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x16
+#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x3000000
+#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x18
+#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0xc000000
+#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x1a
+#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x70000000
+#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x1c
+#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x80000000
+#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x1f
+#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x7ff
+#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x0
+#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800
+#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0xb
+#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x1
+#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0
+#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x2
+#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x1
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x2
+#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1
+#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffff
+#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0
+#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0
+#define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x0
+#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x3f
+#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0
+#define HDP_TILING_CONFIG__PIPE_TILING_MASK 0xe
+#define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x1
+#define HDP_TILING_CONFIG__BANK_TILING_MASK 0x30
+#define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x4
+#define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0xc0
+#define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x6
+#define HDP_TILING_CONFIG__ROW_TILING_MASK 0x700
+#define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x8
+#define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x3800
+#define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0xb
+#define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0xc000
+#define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0xe
+#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x7
+#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x0
+#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x18
+#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x3
+#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0xff
+#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0
+#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0xff00
+#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8
+#define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x1
+#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0
+#define HDP_MISC_CNTL__VM_ID_MASK 0x1e
+#define HDP_MISC_CNTL__VM_ID__SHIFT 0x1
+#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x20
+#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5
+#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x40
+#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6
+#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x780
+#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x7
+#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x800
+#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb
+#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x1000
+#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0xc
+#define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x7e000
+#define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
+#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x80000
+#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x13
+#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x100000
+#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x14
+#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x200000
+#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15
+#define HDP_MISC_CNTL__LEGACY_TILING_ENABLE_MASK 0x400000
+#define HDP_MISC_CNTL__LEGACY_TILING_ENABLE__SHIFT 0x16
+#define HDP_MISC_CNTL__LEGACY_SURFACES_ENABLE_MASK 0x800000
+#define HDP_MISC_CNTL__LEGACY_SURFACES_ENABLE__SHIFT 0x17
+#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x1
+#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0
+#define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x7e
+#define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x1
+#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x1f80
+#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x7
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x0
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x38
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x3
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x1c0
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x6
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0xffe00
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x9
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000
+#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x1b
+#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x1
+#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0
+#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x2
+#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1
+#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x3c
+#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2
+#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x40
+#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6
+#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x80
+#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7
+#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x3f00
+#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8
+#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x4000
+#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe
+#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x8000
+#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf
+#define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x10000
+#define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10
+#define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x1e0000
+#define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11
+#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffff
+#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0
+#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x1
+#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0
+#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x2
+#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1
+#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x4
+#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2
+#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x8
+#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3
+#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffff
+#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0
+#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffff
+#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0
+#define HDP_VF_ENABLE__VF_EN_MASK 0x1
+#define HDP_VF_ENABLE__VF_EN__SHIFT 0x0
+#define HDP_VF_ENABLE__VF_NUM_MASK 0xffff0000
+#define HDP_VF_ENABLE__VF_NUM__SHIFT 0x10
+#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffff
+#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0xf
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0xf0
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x700
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0xf800
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x10000
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x20000
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x11
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x40000
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x80000
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x100000
+#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0xffff
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0xf0000
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x700000
+#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
+#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0
+#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffff
+#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0
+#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffff
+#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0xf
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x30
+#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4
+#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x3fff
+#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x1
+#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x1ffffe
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x1
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x1e00000
+#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x15
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x1
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x0
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x6
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x1
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x8
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x3
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0xf0
+#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x4
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x1
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x0
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x6
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x1
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x8
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x3
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x10
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x4
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x60
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x5
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x80
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x7
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x3f00
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x8
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0xfc000
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x700000
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x14
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x7800000
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x17
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000
+#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x1b
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x1
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x6
+#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1
+#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x1
+#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x0
+#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x6
+#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x1
+#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x18
+#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x3
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x3f
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0xfc0
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x1000
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x2000
+#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x3f
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x0
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x40
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x6
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x80
+#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x7
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0xf
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x0
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0xff0
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x4
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0xc
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x1e
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000
+#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x1f
+#define HDP_XDP_P2P_BAR0__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR0__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR1__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR1__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR2__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR2__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR3__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR3__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR4__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR4__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR5__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR5__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR6__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR6__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14
+#define HDP_XDP_P2P_BAR7__ADDR_MASK 0xffff
+#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0
+#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0xf0000
+#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10
+#define HDP_XDP_P2P_BAR7__VALID_MASK 0x100000
+#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14
+#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffff
+#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0
+#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x3ffffff
+#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0
+#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x3ffff
+#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0
+#define HDP_XDP_STICKY__STICKY_STS_MASK 0xffff
+#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0
+#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000
+#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10
+#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0xff
+#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0
+#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0xff00
+#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8
+#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0xff0000
+#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10
+#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000
+#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18
+#define HDP_XDP_DBG_ADDR__STS_MASK 0xffff
+#define HDP_XDP_DBG_ADDR__STS__SHIFT 0x0
+#define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000
+#define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x10
+#define HDP_XDP_DBG_DATA__STS_MASK 0xffff
+#define HDP_XDP_DBG_DATA__STS__SHIFT 0x0
+#define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000
+#define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x10
+#define HDP_XDP_DBG_MASK__STS_MASK 0xffff
+#define HDP_XDP_DBG_MASK__STS__SHIFT 0x0
+#define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000
+#define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x10
+#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0xf
+#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0
+#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0xf0
+#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4
+#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0xf00
+#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8
+#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0xf000
+#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc
+#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0xf0000
+#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10
+#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0xf00000
+#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14
+#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0xf000000
+#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18
+#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000
+#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c
+
+#endif /* OSS_3_0_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_d.h
new file mode 100644
index 000000000000..f67560b82fe9
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_d.h
@@ -0,0 +1,741 @@
+/*
+ * SMU_7_0_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef SMU_7_0_0_D_H
+#define SMU_7_0_0_D_H
+
+#define mmGCK_SMC_IND_INDEX 0x80
+#define mmGCK0_GCK_SMC_IND_INDEX 0x80
+#define mmGCK1_GCK_SMC_IND_INDEX 0x82
+#define mmGCK2_GCK_SMC_IND_INDEX 0x84
+#define mmGCK3_GCK_SMC_IND_INDEX 0x86
+#define mmGCK_SMC_IND_DATA 0x81
+#define mmGCK0_GCK_SMC_IND_DATA 0x81
+#define mmGCK1_GCK_SMC_IND_DATA 0x83
+#define mmGCK2_GCK_SMC_IND_DATA 0x85
+#define mmGCK3_GCK_SMC_IND_DATA 0x87
+#define ixCG_DCLK_CNTL 0xc050009c
+#define ixCG_DCLK_STATUS 0xc05000a0
+#define ixCG_VCLK_CNTL 0xc05000a4
+#define ixCG_VCLK_STATUS 0xc05000a8
+#define ixCG_ECLK_CNTL 0xc05000ac
+#define ixCG_ECLK_STATUS 0xc05000b0
+#define ixCG_ACLK_CNTL 0xc05000dc
+#define ixGCK_DFS_BYPASS_CNTL 0xc0500118
+#define ixCG_SPLL_FUNC_CNTL 0xc0500140
+#define ixCG_SPLL_FUNC_CNTL_2 0xc0500144
+#define ixCG_SPLL_FUNC_CNTL_3 0xc0500148
+#define ixCG_SPLL_FUNC_CNTL_4 0xc050014c
+#define ixCG_SPLL_FUNC_CNTL_5 0xc0500150
+#define ixCG_SPLL_FUNC_CNTL_6 0xc0500154
+#define ixCG_SPLL_FUNC_CNTL_7 0xc0500158
+#define ixSPLL_CNTL_MODE 0xc0500160
+#define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164
+#define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168
+#define ixMPLL_BYPASSCLK_SEL 0xc050019c
+#define ixCG_CLKPIN_CNTL 0xc05001a0
+#define ixCG_CLKPIN_CNTL_2 0xc05001a4
+#define ixTHM_CLK_CNTL 0xc05001a8
+#define ixMISC_CLK_CTRL 0xc05001ac
+#define ixGCK_PLL_TEST_CNTL 0xc05001c0
+#define ixGCK_PLL_TEST_CNTL_2 0xc05001c4
+#define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8
+#define mmSMC_IND_INDEX 0x80
+#define mmSMC0_SMC_IND_INDEX 0x80
+#define mmSMC1_SMC_IND_INDEX 0x82
+#define mmSMC2_SMC_IND_INDEX 0x84
+#define mmSMC3_SMC_IND_INDEX 0x86
+#define mmSMC_IND_DATA 0x81
+#define mmSMC0_SMC_IND_DATA 0x81
+#define mmSMC1_SMC_IND_DATA 0x83
+#define mmSMC2_SMC_IND_DATA 0x85
+#define mmSMC3_SMC_IND_DATA 0x87
+#define mmSMC_IND_INDEX_0 0x80
+#define mmSMC_IND_DATA_0 0x81
+#define mmSMC_IND_INDEX_1 0x82
+#define mmSMC_IND_DATA_1 0x83
+#define mmSMC_IND_INDEX_2 0x84
+#define mmSMC_IND_DATA_2 0x85
+#define mmSMC_IND_INDEX_3 0x86
+#define mmSMC_IND_DATA_3 0x87
+#define mmSMC_IND_INDEX_4 0x88
+#define mmSMC_IND_DATA_4 0x89
+#define mmSMC_IND_INDEX_5 0x8a
+#define mmSMC_IND_DATA_5 0x8b
+#define mmSMC_IND_INDEX_6 0x8c
+#define mmSMC_IND_DATA_6 0x8d
+#define mmSMC_IND_INDEX_7 0x8e
+#define mmSMC_IND_DATA_7 0x8f
+#define mmSMC_IND_ACCESS_CNTL 0x90
+#define mmSMC_MESSAGE_0 0x94
+#define mmSMC_RESP_0 0x95
+#define mmSMC_MESSAGE_1 0x96
+#define mmSMC_RESP_1 0x97
+#define mmSMC_MESSAGE_2 0x98
+#define mmSMC_RESP_2 0x99
+#define mmSMC_MESSAGE_3 0x9a
+#define mmSMC_RESP_3 0x9b
+#define mmSMC_MESSAGE_4 0x9c
+#define mmSMC_RESP_4 0x9d
+#define mmSMC_MESSAGE_5 0x9e
+#define mmSMC_RESP_5 0x9f
+#define mmSMC_MESSAGE_6 0xa0
+#define mmSMC_RESP_6 0xa1
+#define mmSMC_MESSAGE_7 0xa2
+#define mmSMC_RESP_7 0xa3
+#define mmSMC_MSG_ARG_0 0xa4
+#define mmSMC_MSG_ARG_1 0xa5
+#define mmSMC_MSG_ARG_2 0xa6
+#define mmSMC_MSG_ARG_3 0xa7
+#define mmSMC_MSG_ARG_4 0xa8
+#define mmSMC_MSG_ARG_5 0xa9
+#define mmSMC_MSG_ARG_6 0xaa
+#define mmSMC_MSG_ARG_7 0xab
+#define mmSMC_MESSAGE_8 0xb5
+#define mmSMC_RESP_8 0xb6
+#define mmSMC_MESSAGE_9 0xb7
+#define mmSMC_RESP_9 0xb8
+#define mmSMC_MESSAGE_10 0xb9
+#define mmSMC_RESP_10 0xba
+#define mmSMC_MESSAGE_11 0xbb
+#define mmSMC_RESP_11 0xbc
+#define mmSMC_MSG_ARG_8 0xbd
+#define mmSMC_MSG_ARG_9 0xbe
+#define mmSMC_MSG_ARG_10 0xbf
+#define mmSMC_MSG_ARG_11 0x91
+#define ixSMC_SYSCON_RESET_CNTL 0x80000000
+#define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004
+#define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008
+#define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c
+#define ixSMC_SYSCON_MISC_CNTL 0x80000010
+#define ixSMC_SYSCON_MSG_ARG_0 0x80000068
+#define ixSMC_PC_C 0x80000370
+#define ixSMC_SCRATCH9 0x80000424
+#define mmCG_FPS_CNT 0x1a4
+#define mmSMU_SMC_IND_INDEX 0x80
+#define mmSMU0_SMU_SMC_IND_INDEX 0x80
+#define mmSMU1_SMU_SMC_IND_INDEX 0x82
+#define mmSMU2_SMU_SMC_IND_INDEX 0x84
+#define mmSMU3_SMU_SMC_IND_INDEX 0x86
+#define mmSMU_SMC_IND_DATA 0x81
+#define mmSMU0_SMU_SMC_IND_DATA 0x81
+#define mmSMU1_SMU_SMC_IND_DATA 0x83
+#define mmSMU2_SMU_SMC_IND_DATA 0x85
+#define mmSMU3_SMU_SMC_IND_DATA 0x87
+#define ixRCU_UC_EVENTS 0xc0000004
+#define ixRCU_MISC_CTRL 0xc0000010
+#define ixCC_RCU_FUSES 0xc00c0000
+#define ixCC_SMU_MISC_FUSES 0xc00c0004
+#define ixCC_SCLK_VID_FUSES 0xc00c0008
+#define ixCC_GIO_IOCCFG_FUSES 0xc00c000c
+#define ixCC_GIO_IOC_FUSES 0xc00c0010
+#define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c
+#define ixCC_TST_ID_STRAPS 0xc00c0020
+#define ixCC_FCTRL_FUSES 0xc00c0024
+#define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020
+#define ixSMU_STATUS 0xe0003088
+#define ixSMU_FIRMWARE 0xe00030a4
+#define ixSMU_INPUT_DATA 0xe00030b8
+#define ixSMU_EFUSE_0 0xc0100000
+#define ixDPM_TABLE_1 0x3f000
+#define ixDPM_TABLE_2 0x3f004
+#define ixDPM_TABLE_3 0x3f008
+#define ixDPM_TABLE_4 0x3f00c
+#define ixDPM_TABLE_5 0x3f010
+#define ixDPM_TABLE_6 0x3f014
+#define ixDPM_TABLE_7 0x3f018
+#define ixDPM_TABLE_8 0x3f01c
+#define ixDPM_TABLE_9 0x3f020
+#define ixDPM_TABLE_10 0x3f024
+#define ixDPM_TABLE_11 0x3f028
+#define ixDPM_TABLE_12 0x3f02c
+#define ixDPM_TABLE_13 0x3f030
+#define ixDPM_TABLE_14 0x3f034
+#define ixDPM_TABLE_15 0x3f038
+#define ixDPM_TABLE_16 0x3f03c
+#define ixDPM_TABLE_17 0x3f040
+#define ixDPM_TABLE_18 0x3f044
+#define ixDPM_TABLE_19 0x3f048
+#define ixDPM_TABLE_20 0x3f04c
+#define ixDPM_TABLE_21 0x3f050
+#define ixDPM_TABLE_22 0x3f054
+#define ixDPM_TABLE_23 0x3f058
+#define ixDPM_TABLE_24 0x3f05c
+#define ixDPM_TABLE_25 0x3f060
+#define ixDPM_TABLE_26 0x3f064
+#define ixDPM_TABLE_27 0x3f068
+#define ixDPM_TABLE_28 0x3f06c
+#define ixDPM_TABLE_29 0x3f070
+#define ixDPM_TABLE_30 0x3f074
+#define ixDPM_TABLE_31 0x3f078
+#define ixDPM_TABLE_32 0x3f07c
+#define ixDPM_TABLE_33 0x3f080
+#define ixDPM_TABLE_34 0x3f084
+#define ixDPM_TABLE_35 0x3f088
+#define ixDPM_TABLE_36 0x3f08c
+#define ixDPM_TABLE_37 0x3f090
+#define ixDPM_TABLE_38 0x3f094
+#define ixDPM_TABLE_39 0x3f098
+#define ixDPM_TABLE_40 0x3f09c
+#define ixDPM_TABLE_41 0x3f0a0
+#define ixDPM_TABLE_42 0x3f0a4
+#define ixDPM_TABLE_43 0x3f0a8
+#define ixDPM_TABLE_44 0x3f0ac
+#define ixDPM_TABLE_45 0x3f0b0
+#define ixDPM_TABLE_46 0x3f0b4
+#define ixDPM_TABLE_47 0x3f0b8
+#define ixDPM_TABLE_48 0x3f0bc
+#define ixDPM_TABLE_49 0x3f0c0
+#define ixDPM_TABLE_50 0x3f0c4
+#define ixDPM_TABLE_51 0x3f0c8
+#define ixDPM_TABLE_52 0x3f0cc
+#define ixDPM_TABLE_53 0x3f0d0
+#define ixDPM_TABLE_54 0x3f0d4
+#define ixDPM_TABLE_55 0x3f0d8
+#define ixDPM_TABLE_56 0x3f0dc
+#define ixDPM_TABLE_57 0x3f0e0
+#define ixDPM_TABLE_58 0x3f0e4
+#define ixDPM_TABLE_59 0x3f0e8
+#define ixDPM_TABLE_60 0x3f0ec
+#define ixDPM_TABLE_61 0x3f0f0
+#define ixDPM_TABLE_62 0x3f0f4
+#define ixDPM_TABLE_63 0x3f0f8
+#define ixDPM_TABLE_64 0x3f0fc
+#define ixDPM_TABLE_65 0x3f100
+#define ixDPM_TABLE_66 0x3f104
+#define ixDPM_TABLE_67 0x3f108
+#define ixDPM_TABLE_68 0x3f10c
+#define ixDPM_TABLE_69 0x3f110
+#define ixDPM_TABLE_70 0x3f114
+#define ixDPM_TABLE_71 0x3f118
+#define ixDPM_TABLE_72 0x3f11c
+#define ixDPM_TABLE_73 0x3f120
+#define ixDPM_TABLE_74 0x3f124
+#define ixDPM_TABLE_75 0x3f128
+#define ixDPM_TABLE_76 0x3f12c
+#define ixDPM_TABLE_77 0x3f130
+#define ixDPM_TABLE_78 0x3f134
+#define ixDPM_TABLE_79 0x3f138
+#define ixDPM_TABLE_80 0x3f13c
+#define ixDPM_TABLE_81 0x3f140
+#define ixDPM_TABLE_82 0x3f144
+#define ixDPM_TABLE_83 0x3f148
+#define ixDPM_TABLE_84 0x3f14c
+#define ixDPM_TABLE_85 0x3f150
+#define ixDPM_TABLE_86 0x3f154
+#define ixDPM_TABLE_87 0x3f158
+#define ixDPM_TABLE_88 0x3f15c
+#define ixDPM_TABLE_89 0x3f160
+#define ixDPM_TABLE_90 0x3f164
+#define ixDPM_TABLE_91 0x3f168
+#define ixDPM_TABLE_92 0x3f16c
+#define ixDPM_TABLE_93 0x3f170
+#define ixDPM_TABLE_94 0x3f174
+#define ixDPM_TABLE_95 0x3f178
+#define ixDPM_TABLE_96 0x3f17c
+#define ixDPM_TABLE_97 0x3f180
+#define ixDPM_TABLE_98 0x3f184
+#define ixDPM_TABLE_99 0x3f188
+#define ixDPM_TABLE_100 0x3f18c
+#define ixDPM_TABLE_101 0x3f190
+#define ixDPM_TABLE_102 0x3f194
+#define ixDPM_TABLE_103 0x3f198
+#define ixDPM_TABLE_104 0x3f19c
+#define ixDPM_TABLE_105 0x3f1a0
+#define ixDPM_TABLE_106 0x3f1a4
+#define ixDPM_TABLE_107 0x3f1a8
+#define ixDPM_TABLE_108 0x3f1ac
+#define ixDPM_TABLE_109 0x3f1b0
+#define ixDPM_TABLE_110 0x3f1b4
+#define ixDPM_TABLE_111 0x3f1b8
+#define ixDPM_TABLE_112 0x3f1bc
+#define ixDPM_TABLE_113 0x3f1c0
+#define ixDPM_TABLE_114 0x3f1c4
+#define ixDPM_TABLE_115 0x3f1c8
+#define ixDPM_TABLE_116 0x3f1cc
+#define ixDPM_TABLE_117 0x3f1d0
+#define ixDPM_TABLE_118 0x3f1d4
+#define ixDPM_TABLE_119 0x3f1d8
+#define ixDPM_TABLE_120 0x3f1dc
+#define ixDPM_TABLE_121 0x3f1e0
+#define ixDPM_TABLE_122 0x3f1e4
+#define ixDPM_TABLE_123 0x3f1e8
+#define ixDPM_TABLE_124 0x3f1ec
+#define ixDPM_TABLE_125 0x3f1f0
+#define ixDPM_TABLE_126 0x3f1f4
+#define ixDPM_TABLE_127 0x3f1f8
+#define ixDPM_TABLE_128 0x3f1fc
+#define ixDPM_TABLE_129 0x3f200
+#define ixDPM_TABLE_130 0x3f204
+#define ixDPM_TABLE_131 0x3f208
+#define ixDPM_TABLE_132 0x3f20c
+#define ixDPM_TABLE_133 0x3f210
+#define ixDPM_TABLE_134 0x3f214
+#define ixDPM_TABLE_135 0x3f218
+#define ixDPM_TABLE_136 0x3f21c
+#define ixDPM_TABLE_137 0x3f220
+#define ixDPM_TABLE_138 0x3f224
+#define ixDPM_TABLE_139 0x3f228
+#define ixDPM_TABLE_140 0x3f22c
+#define ixDPM_TABLE_141 0x3f230
+#define ixDPM_TABLE_142 0x3f234
+#define ixDPM_TABLE_143 0x3f238
+#define ixDPM_TABLE_144 0x3f23c
+#define ixDPM_TABLE_145 0x3f240
+#define ixDPM_TABLE_146 0x3f244
+#define ixDPM_TABLE_147 0x3f248
+#define ixDPM_TABLE_148 0x3f24c
+#define ixDPM_TABLE_149 0x3f250
+#define ixDPM_TABLE_150 0x3f254
+#define ixDPM_TABLE_151 0x3f258
+#define ixDPM_TABLE_152 0x3f25c
+#define ixDPM_TABLE_153 0x3f260
+#define ixDPM_TABLE_154 0x3f264
+#define ixDPM_TABLE_155 0x3f268
+#define ixDPM_TABLE_156 0x3f26c
+#define ixDPM_TABLE_157 0x3f270
+#define ixDPM_TABLE_158 0x3f274
+#define ixDPM_TABLE_159 0x3f278
+#define ixDPM_TABLE_160 0x3f27c
+#define ixDPM_TABLE_161 0x3f280
+#define ixDPM_TABLE_162 0x3f284
+#define ixDPM_TABLE_163 0x3f288
+#define ixDPM_TABLE_164 0x3f28c
+#define ixDPM_TABLE_165 0x3f290
+#define ixDPM_TABLE_166 0x3f294
+#define ixDPM_TABLE_167 0x3f298
+#define ixDPM_TABLE_168 0x3f29c
+#define ixDPM_TABLE_169 0x3f2a0
+#define ixDPM_TABLE_170 0x3f2a4
+#define ixDPM_TABLE_171 0x3f2a8
+#define ixDPM_TABLE_172 0x3f2ac
+#define ixDPM_TABLE_173 0x3f2b0
+#define ixDPM_TABLE_174 0x3f2b4
+#define ixDPM_TABLE_175 0x3f2b8
+#define ixDPM_TABLE_176 0x3f2bc
+#define ixDPM_TABLE_177 0x3f2c0
+#define ixDPM_TABLE_178 0x3f2c4
+#define ixDPM_TABLE_179 0x3f2c8
+#define ixDPM_TABLE_180 0x3f2cc
+#define ixDPM_TABLE_181 0x3f2d0
+#define ixDPM_TABLE_182 0x3f2d4
+#define ixDPM_TABLE_183 0x3f2d8
+#define ixDPM_TABLE_184 0x3f2dc
+#define ixDPM_TABLE_185 0x3f2e0
+#define ixDPM_TABLE_186 0x3f2e4
+#define ixDPM_TABLE_187 0x3f2e8
+#define ixDPM_TABLE_188 0x3f2ec
+#define ixDPM_TABLE_189 0x3f2f0
+#define ixDPM_TABLE_190 0x3f2f4
+#define ixDPM_TABLE_191 0x3f2f8
+#define ixSOFT_REGISTERS_TABLE_1 0x3f900
+#define ixSOFT_REGISTERS_TABLE_2 0x3f904
+#define ixSOFT_REGISTERS_TABLE_3 0x3f908
+#define ixSOFT_REGISTERS_TABLE_4 0x3f90c
+#define ixSOFT_REGISTERS_TABLE_5 0x3f910
+#define ixSOFT_REGISTERS_TABLE_6 0x3f914
+#define ixSOFT_REGISTERS_TABLE_7 0x3f918
+#define ixSOFT_REGISTERS_TABLE_8 0x3f91c
+#define ixSOFT_REGISTERS_TABLE_9 0x3f920
+#define ixSOFT_REGISTERS_TABLE_10 0x3f924
+#define ixSOFT_REGISTERS_TABLE_11 0x3f928
+#define ixSOFT_REGISTERS_TABLE_12 0x3f92c
+#define ixSOFT_REGISTERS_TABLE_13 0x3f930
+#define ixSOFT_REGISTERS_TABLE_14 0x3f934
+#define ixSOFT_REGISTERS_TABLE_15 0x3f938
+#define ixSOFT_REGISTERS_TABLE_16 0x3f93c
+#define ixSOFT_REGISTERS_TABLE_17 0x3f940
+#define ixSOFT_REGISTERS_TABLE_18 0x3f944
+#define ixSOFT_REGISTERS_TABLE_19 0x3f948
+#define ixSOFT_REGISTERS_TABLE_20 0x3f94c
+#define ixSOFT_REGISTERS_TABLE_21 0x3f950
+#define ixSMU_LCLK_DPM_STATE_0_CNTL_0 0x3fd00
+#define ixSMU_LCLK_DPM_STATE_1_CNTL_0 0x3fd14
+#define ixSMU_LCLK_DPM_STATE_2_CNTL_0 0x3fd28
+#define ixSMU_LCLK_DPM_STATE_3_CNTL_0 0x3fd3c
+#define ixSMU_LCLK_DPM_STATE_4_CNTL_0 0x3fd50
+#define ixSMU_LCLK_DPM_STATE_5_CNTL_0 0x3fd64
+#define ixSMU_LCLK_DPM_STATE_6_CNTL_0 0x3fd78
+#define ixSMU_LCLK_DPM_STATE_7_CNTL_0 0x3fd8c
+#define ixSMU_LCLK_DPM_STATE_0_CNTL_1 0x3fd04
+#define ixSMU_LCLK_DPM_STATE_1_CNTL_1 0x3fd18
+#define ixSMU_LCLK_DPM_STATE_2_CNTL_1 0x3fd2c
+#define ixSMU_LCLK_DPM_STATE_3_CNTL_1 0x3fd40
+#define ixSMU_LCLK_DPM_STATE_4_CNTL_1 0x3fd54
+#define ixSMU_LCLK_DPM_STATE_5_CNTL_1 0x3fd68
+#define ixSMU_LCLK_DPM_STATE_6_CNTL_1 0x3fd7c
+#define ixSMU_LCLK_DPM_STATE_7_CNTL_1 0x3fd90
+#define ixSMU_LCLK_DPM_STATE_0_CNTL_2 0x3fd08
+#define ixSMU_LCLK_DPM_STATE_1_CNTL_2 0x3fd1c
+#define ixSMU_LCLK_DPM_STATE_2_CNTL_2 0x3fd30
+#define ixSMU_LCLK_DPM_STATE_3_CNTL_2 0x3fd44
+#define ixSMU_LCLK_DPM_STATE_4_CNTL_2 0x3fd58
+#define ixSMU_LCLK_DPM_STATE_5_CNTL_2 0x3fd6c
+#define ixSMU_LCLK_DPM_STATE_6_CNTL_2 0x3fd80
+#define ixSMU_LCLK_DPM_STATE_7_CNTL_2 0x3fd94
+#define ixSMU_LCLK_DPM_STATE_0_CNTL_3 0x3fd0c
+#define ixSMU_LCLK_DPM_STATE_1_CNTL_3 0x3fd20
+#define ixSMU_LCLK_DPM_STATE_2_CNTL_3 0x3fd34
+#define ixSMU_LCLK_DPM_STATE_3_CNTL_3 0x3fd48
+#define ixSMU_LCLK_DPM_STATE_4_CNTL_3 0x3fd5c
+#define ixSMU_LCLK_DPM_STATE_5_CNTL_3 0x3fd70
+#define ixSMU_LCLK_DPM_STATE_6_CNTL_3 0x3fd84
+#define ixSMU_LCLK_DPM_STATE_7_CNTL_3 0x3fd98
+#define ixSMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD 0x3fd10
+#define ixSMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD 0x3fd24
+#define ixSMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD 0x3fd38
+#define ixSMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD 0x3fd4c
+#define ixSMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD 0x3fd60
+#define ixSMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD 0x3fd74
+#define ixSMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD 0x3fd88
+#define ixSMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD 0x3fd9c
+#define ixGIO_PID_CONTROLLER_CNTL_0 0x3fda0
+#define ixGIO_PID_CONTROLLER_CNTL_1 0x3fda4
+#define ixGIO_PID_CONTROLLER_CNTL_2 0x3fda8
+#define ixGIO_PID_CONTROLLER_CNTL_3 0x3fdac
+#define ixGIO_PID_CONTROLLER_CNTL_4 0x3fdb0
+#define ixGIO_PID_CONTROLLER_CNTL_5 0x3fdb4
+#define ixGIO_PID_CONTROLLER_CNTL_6 0x3fdb8
+#define ixGIO_PID_CONTROLLER_CNTL_7 0x3fdbc
+#define ixGIO_PID_CONTROLLER_CNTL_8 0x3fdc0
+#define ixSMU_LCLK_DPM_LEVEL_COUNT 0x3fdc4
+#define ixSMU_LCLK_DPM_CNTL 0x3fdc8
+#define ixSMU_LCLK_DPM_CURRENT_AND_TARGET_STATE 0x3fdcc
+#define ixSMU_LCLK_DPM_THERMAL_THROTTLING_CNTL 0x3fdd0
+#define ixSMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS 0x3fdd4
+#define ixPM_FUSES_1 0x3fa80
+#define ixPM_FUSES_2 0x3fa84
+#define ixPM_FUSES_3 0x3fa88
+#define ixPM_FUSES_4 0x3fa8c
+#define ixPM_FUSES_5 0x3fa90
+#define ixPM_FUSES_6 0x3fa94
+#define ixPM_FUSES_7 0x3fa98
+#define ixPM_FUSES_8 0x3fa9c
+#define ixPM_FUSES_9 0x3faa0
+#define ixPM_FUSES_10 0x3faa4
+#define ixPM_FUSES_11 0x3faa8
+#define ixPM_FUSES_12 0x3faac
+#define ixPM_FUSES_13 0x3fab0
+#define ixPM_FUSES_14 0x3fab4
+#define ixPM_FUSES_15 0x3fab8
+#define ixPM_FUSES_16 0x3fabc
+#define ixPM_FUSES_17 0x3fac0
+#define ixPM_FUSES_18 0x3fac4
+#define ixPM_FUSES_19 0x3fac8
+#define ixPM_FUSES_20 0x3facc
+#define ixPM_FUSES_21 0x3fad0
+#define ixPM_FUSES_22 0x3fad4
+#define ixPM_FUSES_23 0x3fad8
+#define ixPM_FUSES_24 0x3fadc
+#define ixPM_FUSES_25 0x3fae0
+#define ixPM_FUSES_26 0x3fae4
+#define ixPM_FUSES_27 0x3fae8
+#define ixPM_FUSES_28 0x3faec
+#define ixPM_FUSES_29 0x3faf0
+#define ixPM_FUSES_30 0x3faf4
+#define ixPM_FUSES_31 0x3faf8
+#define ixPM_FUSES_32 0x3fafc
+#define ixPM_FUSES_33 0x3fb00
+#define ixPM_FUSES_34 0x3fb04
+#define ixPM_FUSES_35 0x3fb08
+#define ixPM_FUSES_36 0x3fb0c
+#define ixPM_FUSES_37 0x3fb10
+#define ixPM_FUSES_38 0x3fb14
+#define ixPM_FUSES_39 0x3fb18
+#define ixPM_FUSES_40 0x3fb1c
+#define ixPM_FUSES_41 0x3fb20
+#define ixPM_FUSES_42 0x3fb24
+#define ixPM_FUSES_43 0x3fb28
+#define ixPM_FUSES_44 0x3fb2c
+#define ixPM_FUSES_45 0x3fb30
+#define ixPM_FUSES_46 0x3fb34
+#define ixPM_FUSES_47 0x3fb38
+#define ixPM_FUSES_48 0x3fb3c
+#define ixPM_FUSES_49 0x3fb40
+#define ixPM_FUSES_50 0x3fb44
+#define ixPM_FUSES_51 0x3fb48
+#define ixPM_FUSES_52 0x3fb4c
+#define ixPM_FUSES_53 0x3fb50
+#define ixPM_FUSES_54 0x3fb54
+#define ixPM_FUSES_55 0x3fb58
+#define ixPM_FUSES_56 0x3fb5c
+#define ixPM_FUSES_57 0x3fb60
+#define ixPM_FUSES_58 0x3fb64
+#define ixPM_FUSES_59 0x3fb68
+#define ixPM_FUSES_60 0x3fb6c
+#define ixPM_FUSES_61 0x3fb70
+#define ixPM_FUSES_62 0x3fb74
+#define ixPM_FUSES_63 0x3fb78
+#define ixPM_FUSES_64 0x3fb7c
+#define ixPM_FUSES_65 0x3fb80
+#define ixFIRMWARE_FLAGS 0x3f800
+#define ixTEMPERATURE_READ_ADDR 0x3f808
+#define ixCURRENT_GNB_TEMP 0x3f810
+#define ixCURRENT_GLOBAL_TEMP 0x3f814
+#define ixFEATURE_STATUS 0x3f818
+#define ixPCIE_PLL_RECONF 0x3f81c
+#define ixPM_INTERVAL_CNTL_0 0x3f820
+#define ixPM_INTERVAL_CNTL_1 0x3f824
+#define ixPM_INTERVAL_CNTL_2 0x3f82c
+#define ixVPC_INTERVAL_CNTL 0x3f830
+#define ixDISP_PHY_TDP_LIMIT 0x3f834
+#define ixFCH_PWR_CREDIT 0x3f838
+#define ixPKGPWR_MV_AVG 0x3f83c
+#define ixPACKAGE_POWER 0x3f840
+#define ixPKG_PWR_CNTL 0x3f844
+#define ixPKG_PWR_STATUS 0x3f848
+#define ixDISP_PHY_CONFIG 0x3f84c
+#define ixGPU_TDP_LIMIT 0x3f850
+#define ixEXT_API_IN_DATA_0_0 0x3f858
+#define ixEXT_API_IN_DATA_0_1 0x3f85c
+#define ixEXT_API_IN_DATA_0_2 0x3f860
+#define ixEXT_API_IN_DATA_0_3 0x3f864
+#define ixEXT_API_OUT_DATA_0_0 0x3f868
+#define ixEXT_API_OUT_DATA_0_1 0x3f86c
+#define ixEXT_API_OUT_DATA_0_2 0x3f870
+#define ixEXT_API_OUT_DATA_0_3 0x3f874
+#define ixBAPM_PARAMETERS 0x3f984
+#define ixBAPM_PARAMETERS_2 0x3f988
+#define ixBAPM_PARAMETERS_3 0x3f98c
+#define ixBAPM_PARAMETERS_4 0x3f990
+#define ixSMU_SVI_TELEMETRY 0x3f994
+#define ixBAPM_STATUS 0x3f998
+#define ixSMU_HTC_STATUS 0x3f99c
+#define ixSMU_VPC_STATUS 0x3f9a0
+#define ixENTITY_TEMPERATURES_1 0x3f9a4
+#define ixENTITY_TEMPERATURES_2 0x3f9a8
+#define ixENTITY_TEMPERATURES_3 0x3f9ac
+#define ixCU_POWER 0x3f9b0
+#define ixGPU_POWER 0x3f9b4
+#define ixNTE_POWER 0x3f9b8
+#define ixTDC_STATUS 0x3f9d0
+#define ixTDC_MV_AVERAGE 0x3f9d4
+#define ixPM_CONFIG 0x3f9d8
+#define ixTE0_TEMPERATURE_READ_ADDR 0x3f9dc
+#define ixTE1_TEMPERATURE_READ_ADDR 0x3f9e0
+#define ixTE2_TEMPERATURE_READ_ADDR 0x3f9e4
+#define ixNB_DPM_CONFIG_1 0x3f9e8
+#define ixNB_DPM_CONFIG_2 0x3f9ec
+#define ixNB_DPM_CONFIG_3 0x3f9f0
+#define ixSMU_IDD_OVERRIDE 0x3f9fc
+#define ixAVS_CONFIG 0x3fa00
+#define ixTDC_VRM_LIMIT 0x3fa04
+#define ixCU0_PSM_CONFIG 0x3fa08
+#define ixCU1_PSM_CONFIG 0x3fa0c
+#define ixSPMI_CONFIG 0x3fa10
+#define ixSPMI_SMC_CHAIN_ADDR 0x3fa14
+#define ixSPMI_STATUS 0x3fa30
+#define ixAVSNB_CONFIG 0x3fa34
+#define ixHTC_CONFIG 0x3fa38
+#define ixAVS_CU0_TEMPERATURE_SENSOR 0x3fa3c
+#define ixAVS_CU1_TEMPERATURE_SENSOR 0x3fa40
+#define ixAVS_GNB_TEMPERATURE_SENSOR 0x3fa44
+#define ixAVS_UNB_TEMPERATURE_SENSOR 0x3fa48
+#define ixSMU_MONITOR_PORT80_MMIO_ADDR 0x3fa4c
+#define ixSMU_MONITOR_PORT80_MEMBASE_HI 0x3fa50
+#define ixSMU_MONITOR_PORT80_MEMBASE_LO 0x3fa54
+#define ixSMU_MONITOR_PORT80_MEMSETUP 0x3fa58
+#define ixSMU_MONITOR_PORT80_CTRL 0x3fa5c
+#define ixSMU_TCEN_ALIVE 0x3fa60
+#define ixPDM_STATUS 0x3fa64
+#define ixPDM_CNTL_1 0x3fa68
+#define ixPDM_CNTL_2 0x3fa6c
+#define ixPDM_CNTL_3 0x3fa70
+#define ixSMU_PM_STATUS_0 0x3fe00
+#define ixSMU_PM_STATUS_1 0x3fe04
+#define ixSMU_PM_STATUS_2 0x3fe08
+#define ixSMU_PM_STATUS_3 0x3fe0c
+#define ixSMU_PM_STATUS_4 0x3fe10
+#define ixSMU_PM_STATUS_5 0x3fe14
+#define ixSMU_PM_STATUS_6 0x3fe18
+#define ixSMU_PM_STATUS_7 0x3fe1c
+#define ixSMU_PM_STATUS_8 0x3fe20
+#define ixSMU_PM_STATUS_9 0x3fe24
+#define ixSMU_PM_STATUS_10 0x3fe28
+#define ixSMU_PM_STATUS_11 0x3fe2c
+#define ixSMU_PM_STATUS_12 0x3fe30
+#define ixSMU_PM_STATUS_13 0x3fe34
+#define ixSMU_PM_STATUS_14 0x3fe38
+#define ixSMU_PM_STATUS_15 0x3fe3c
+#define ixSMU_PM_STATUS_16 0x3fe40
+#define ixSMU_PM_STATUS_17 0x3fe44
+#define ixSMU_PM_STATUS_18 0x3fe48
+#define ixSMU_PM_STATUS_19 0x3fe4c
+#define ixSMU_PM_STATUS_20 0x3fe50
+#define ixSMU_PM_STATUS_21 0x3fe54
+#define ixSMU_PM_STATUS_22 0x3fe58
+#define ixSMU_PM_STATUS_23 0x3fe5c
+#define ixSMU_PM_STATUS_24 0x3fe60
+#define ixSMU_PM_STATUS_25 0x3fe64
+#define ixSMU_PM_STATUS_26 0x3fe68
+#define ixSMU_PM_STATUS_27 0x3fe6c
+#define ixSMU_PM_STATUS_28 0x3fe70
+#define ixSMU_PM_STATUS_29 0x3fe74
+#define ixSMU_PM_STATUS_30 0x3fe78
+#define ixSMU_PM_STATUS_31 0x3fe7c
+#define ixSMU_PM_STATUS_32 0x3fe80
+#define ixSMU_PM_STATUS_33 0x3fe84
+#define ixSMU_PM_STATUS_34 0x3fe88
+#define ixSMU_PM_STATUS_35 0x3fe8c
+#define ixSMU_PM_STATUS_36 0x3fe90
+#define ixSMU_PM_STATUS_37 0x3fe94
+#define ixSMU_PM_STATUS_38 0x3fe98
+#define ixSMU_PM_STATUS_39 0x3fe9c
+#define ixSMU_PM_STATUS_40 0x3fea0
+#define ixSMU_PM_STATUS_41 0x3fea4
+#define ixSMU_PM_STATUS_42 0x3fea8
+#define ixSMU_PM_STATUS_43 0x3feac
+#define ixSMU_PM_STATUS_44 0x3feb0
+#define ixSMU_PM_STATUS_45 0x3feb4
+#define ixSMU_PM_STATUS_46 0x3feb8
+#define ixSMU_PM_STATUS_47 0x3febc
+#define ixSMU_PM_STATUS_48 0x3fec0
+#define ixSMU_PM_STATUS_49 0x3fec4
+#define ixSMU_PM_STATUS_50 0x3fec8
+#define ixSMU_PM_STATUS_51 0x3fecc
+#define ixSMU_PM_STATUS_52 0x3fed0
+#define ixSMU_PM_STATUS_53 0x3fed4
+#define ixSMU_PM_STATUS_54 0x3fed8
+#define ixSMU_PM_STATUS_55 0x3fedc
+#define ixSMU_PM_STATUS_56 0x3fee0
+#define ixSMU_PM_STATUS_57 0x3fee4
+#define ixSMU_PM_STATUS_58 0x3fee8
+#define ixSMU_PM_STATUS_59 0x3feec
+#define ixSMU_PM_STATUS_60 0x3fef0
+#define ixSMU_PM_STATUS_61 0x3fef4
+#define ixSMU_PM_STATUS_62 0x3fef8
+#define ixSMU_PM_STATUS_63 0x3fefc
+#define ixSMU_PM_STATUS_64 0x3ff00
+#define ixSMU_PM_STATUS_65 0x3ff04
+#define ixSMU_PM_STATUS_66 0x3ff08
+#define ixSMU_PM_STATUS_67 0x3ff0c
+#define ixSMU_PM_STATUS_68 0x3ff10
+#define ixSMU_PM_STATUS_69 0x3ff14
+#define ixSMU_PM_STATUS_70 0x3ff18
+#define ixSMU_PM_STATUS_71 0x3ff1c
+#define ixSMU_PM_STATUS_72 0x3ff20
+#define ixSMU_PM_STATUS_73 0x3ff24
+#define ixSMU_PM_STATUS_74 0x3ff28
+#define ixSMU_PM_STATUS_75 0x3ff2c
+#define ixSMU_PM_STATUS_76 0x3ff30
+#define ixSMU_PM_STATUS_77 0x3ff34
+#define ixSMU_PM_STATUS_78 0x3ff38
+#define ixSMU_PM_STATUS_79 0x3ff3c
+#define ixSMU_PM_STATUS_80 0x3ff40
+#define ixSMU_PM_STATUS_81 0x3ff44
+#define ixSMU_PM_STATUS_82 0x3ff48
+#define ixSMU_PM_STATUS_83 0x3ff4c
+#define ixSMU_PM_STATUS_84 0x3ff50
+#define ixSMU_PM_STATUS_85 0x3ff54
+#define ixSMU_PM_STATUS_86 0x3ff58
+#define ixSMU_PM_STATUS_87 0x3ff5c
+#define ixSMU_PM_STATUS_88 0x3ff60
+#define ixSMU_PM_STATUS_89 0x3ff64
+#define ixSMU_PM_STATUS_90 0x3ff68
+#define ixSMU_PM_STATUS_91 0x3ff6c
+#define ixSMU_PM_STATUS_92 0x3ff70
+#define ixSMU_PM_STATUS_93 0x3ff74
+#define ixSMU_PM_STATUS_94 0x3ff78
+#define ixSMU_PM_STATUS_95 0x3ff7c
+#define ixSMU_PM_STATUS_96 0x3ff80
+#define ixSMU_PM_STATUS_97 0x3ff84
+#define ixSMU_PM_STATUS_98 0x3ff88
+#define ixSMU_PM_STATUS_99 0x3ff8c
+#define ixSMU_PM_STATUS_100 0x3ff90
+#define ixSMU_PM_STATUS_101 0x3ff94
+#define ixSMU_PM_STATUS_102 0x3ff98
+#define ixSMU_PM_STATUS_103 0x3ff9c
+#define ixSMU_PM_STATUS_104 0x3ffa0
+#define ixSMU_PM_STATUS_105 0x3ffa4
+#define ixSMU_PM_STATUS_106 0x3ffa8
+#define ixSMU_PM_STATUS_107 0x3ffac
+#define ixSMU_PM_STATUS_108 0x3ffb0
+#define ixSMU_PM_STATUS_109 0x3ffb4
+#define ixSMU_PM_STATUS_110 0x3ffb8
+#define ixSMU_PM_STATUS_111 0x3ffbc
+#define ixSMU_PM_STATUS_112 0x3ffc0
+#define ixSMU_PM_STATUS_113 0x3ffc4
+#define ixSMU_PM_STATUS_114 0x3ffc8
+#define ixSMU_PM_STATUS_115 0x3ffcc
+#define ixSMU_PM_STATUS_116 0x3ffd0
+#define ixSMU_PM_STATUS_117 0x3ffd4
+#define ixSMU_PM_STATUS_118 0x3ffd8
+#define ixSMU_PM_STATUS_119 0x3ffdc
+#define ixSMU_PM_STATUS_120 0x3ffe0
+#define ixSMU_PM_STATUS_121 0x3ffe4
+#define ixSMU_PM_STATUS_122 0x3ffe8
+#define ixSMU_PM_STATUS_123 0x3ffec
+#define ixSMU_PM_STATUS_124 0x3fff0
+#define ixSMU_PM_STATUS_125 0x3fff4
+#define ixSMU_PM_STATUS_126 0x3fff8
+#define ixSMU_PM_STATUS_127 0x3fffc
+#define ixCG_THERMAL_INT_ENA 0xc2100024
+#define ixCG_THERMAL_INT_CTRL 0xc2100028
+#define ixCG_THERMAL_INT_STATUS 0xc210002c
+#define ixGENERAL_PWRMGT 0xc0200000
+#define ixCNB_PWRMGT_CNTL 0xc0200004
+#define ixSCLK_PWRMGT_CNTL 0xc0200008
+#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014
+#define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8
+#define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac
+#define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0
+#define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4
+#define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8
+#define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc
+#define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0
+#define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4
+#define ixPLL_TEST_CNTL 0xc020003c
+#define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044
+#define ixCG_DISPLAY_GAP_CNTL 0xc0200060
+#define ixCG_DISPLAY_GAP_CNTL2 0xc0200230
+#define ixCG_ACPI_CNTL 0xc0200064
+#define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080
+#define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084
+#define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c
+#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088
+#define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c
+#define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310
+#define ixSMU_VOLTAGE_STATUS 0xc0200094
+#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0
+#define ixCG_ULV_PARAMETER 0xc020015c
+#define ixSCLK_MIN_DIV 0xc0200308
+#define ixLCAC_SX0_CNTL 0xc0400d00
+#define ixLCAC_SX0_OVR_SEL 0xc0400d04
+#define ixLCAC_SX0_OVR_VAL 0xc0400d08
+#define ixLCAC_MC0_CNTL 0xc0400d30
+#define ixLCAC_MC0_OVR_SEL 0xc0400d34
+#define ixLCAC_MC0_OVR_VAL 0xc0400d38
+#define ixLCAC_MC1_CNTL 0xc0400d3c
+#define ixLCAC_MC1_OVR_SEL 0xc0400d40
+#define ixLCAC_MC1_OVR_VAL 0xc0400d44
+#define ixLCAC_MC2_CNTL 0xc0400d48
+#define ixLCAC_MC2_OVR_SEL 0xc0400d4c
+#define ixLCAC_MC2_OVR_VAL 0xc0400d50
+#define ixLCAC_MC3_CNTL 0xc0400d54
+#define ixLCAC_MC3_OVR_SEL 0xc0400d58
+#define ixLCAC_MC3_OVR_VAL 0xc0400d5c
+#define ixLCAC_CPL_CNTL 0xc0400d80
+#define ixLCAC_CPL_OVR_SEL 0xc0400d84
+#define ixLCAC_CPL_OVR_VAL 0xc0400d88
+
+#endif /* SMU_7_0_0_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h
new file mode 100644
index 000000000000..54e0e4c3f1bc
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h
@@ -0,0 +1,3842 @@
+/*
+ * SMU_7_0_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef SMU_7_0_0_SH_MASK_H
+#define SMU_7_0_0_SH_MASK_H
+
+#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
+#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1
+#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0
+#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2
+#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1
+#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f
+#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1
+#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0
+#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2
+#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1
+#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f
+#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1
+#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0
+#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2
+#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1
+#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f
+#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1
+#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0
+#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2
+#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1
+#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4
+#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2
+#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
+#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3
+#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10
+#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4
+#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20
+#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5
+#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40
+#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6
+#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80
+#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7
+#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100
+#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
+#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200
+#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9
+#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400
+#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa
+#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800
+#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb
+#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000
+#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc
+#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1
+#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2
+#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1
+#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4
+#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4
+#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0
+#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc
+#define CG_SPLL_FUNC_CNTL__SPLL_BG_PWRON_MASK 0x2000
+#define CG_SPLL_FUNC_CNTL__SPLL_BG_PWRON__SHIFT 0xd
+#define CG_SPLL_FUNC_CNTL__SPLL_BGADJ_MASK 0x3c000
+#define CG_SPLL_FUNC_CNTL__SPLL_BGADJ__SHIFT 0xe
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x1fc0000
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x12
+#define CG_SPLL_FUNC_CNTL__SPLL_REG_BIAS_MASK 0xe000000
+#define CG_SPLL_FUNC_CNTL__SPLL_REG_BIAS__SHIFT 0x19
+#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000
+#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17
+#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a
+#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e
+#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff
+#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000
+#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SSAMP_EN_MASK 0x200
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SSAMP_EN__SHIFT 0x9
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fc00
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0xa
+#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000
+#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15
+#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17
+#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f
+#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1
+#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2
+#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1
+#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc
+#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2
+#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30
+#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8
+#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200
+#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9
+#define CG_SPLL_FUNC_CNTL_5__REFCLK_BYPASS_EN_MASK 0x400
+#define CG_SPLL_FUNC_CNTL_5__REFCLK_BYPASS_EN__SHIFT 0xa
+#define CG_SPLL_FUNC_CNTL_5__PLLBYPASS_MASK 0x800
+#define CG_SPLL_FUNC_CNTL_5__PLLBYPASS__SHIFT 0xb
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15
+#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
+#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
+#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
+#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
+#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
+#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2
+#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1
+#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4
+#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2
+#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8
+#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3
+#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10
+#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4
+#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00
+#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa
+#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000
+#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc
+#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000
+#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c
+#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000
+#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d
+#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1
+#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0
+#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0
+#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4
+#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff
+#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0
+#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00
+#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8
+#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2
+#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1
+#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4
+#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2
+#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1
+#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0
+#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8
+#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3
+#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100
+#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8
+#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000
+#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe
+#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000
+#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf
+#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000
+#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10
+#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000
+#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11
+#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000
+#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12
+#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000
+#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13
+#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000
+#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14
+#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000
+#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15
+#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000
+#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16
+#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000
+#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18
+#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff
+#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0
+#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00
+#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8
+#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000
+#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10
+#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff
+#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0
+#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00
+#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8
+#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000
+#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10
+#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f
+#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
+#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0
+#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5
+#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00
+#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa
+#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000
+#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11
+#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000
+#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12
+#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000
+#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3
+#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0
+#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9
+#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b
+#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7
+#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_0__SMC_RESP_MASK 0xffff
+#define SMC_RESP_0__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_1__SMC_RESP_MASK 0xffff
+#define SMC_RESP_1__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_2__SMC_RESP_MASK 0xffff
+#define SMC_RESP_2__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_3__SMC_RESP_MASK 0xffff
+#define SMC_RESP_3__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_4__SMC_RESP_MASK 0xffff
+#define SMC_RESP_4__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_5__SMC_RESP_MASK 0xffff
+#define SMC_RESP_5__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_6__SMC_RESP_MASK 0xffff
+#define SMC_RESP_6__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_7__SMC_RESP_MASK 0xffff
+#define SMC_RESP_7__SMC_RESP__SHIFT 0x0
+#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_8__SMC_RESP_MASK 0xffff
+#define SMC_RESP_8__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_9__SMC_RESP_MASK 0xffff
+#define SMC_RESP_9__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_10__SMC_RESP_MASK 0xffff
+#define SMC_RESP_10__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_11__SMC_RESP_MASK 0xffff
+#define SMC_RESP_11__SMC_RESP__SHIFT 0x0
+#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1
+#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0
+#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2
+#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1
+#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000
+#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e
+#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1
+#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8
+#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000
+#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18
+#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1
+#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0
+#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff
+#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0
+#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff
+#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0
+#define SMC_PC_C__smc_pc_c_MASK 0xffffffff
+#define SMC_PC_C__smc_pc_c__SHIFT 0x0
+#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff
+#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0
+#define CG_FPS_CNT__FPS_CNT_MASK 0xff
+#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0
+#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1
+#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0
+#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2
+#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1
+#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4
+#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2
+#define RCU_UC_EVENTS__TP_Tester_MASK 0x40
+#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6
+#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80
+#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7
+#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100
+#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8
+#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200
+#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9
+#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400
+#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa
+#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800
+#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb
+#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000
+#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd
+#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000
+#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10
+#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000
+#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11
+#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000
+#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12
+#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000
+#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13
+#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000
+#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18
+#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2
+#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1
+#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8
+#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3
+#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10
+#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4
+#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20
+#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5
+#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100
+#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8
+#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000
+#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10
+#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000
+#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11
+#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000
+#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16
+#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000
+#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17
+#define CC_RCU_FUSES__GPU_DIS_MASK 0x2
+#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1
+#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4
+#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2
+#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10
+#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4
+#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20
+#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5
+#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40
+#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6
+#define CC_RCU_FUSES__ROM_DIS_MASK 0x80
+#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7
+#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100
+#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8
+#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200
+#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9
+#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400
+#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa
+#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x4000
+#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0xe
+#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x8000
+#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xf
+#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x10000
+#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0x10
+#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x20000
+#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x11
+#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x40000
+#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x12
+#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x80000
+#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x13
+#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x100000
+#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x14
+#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x400000
+#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x16
+#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x800000
+#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x17
+#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x1000000
+#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x18
+#define CC_RCU_FUSES__RCU_SPARE_MASK 0x7e000000
+#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x19
+#define CC_RCU_FUSES__PSP_ENABLE_MASK 0x80000000
+#define CC_RCU_FUSES__PSP_ENABLE__SHIFT 0x1f
+#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2
+#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1
+#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc
+#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2
+#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600
+#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9
+#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800
+#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17
+#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000
+#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b
+#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000
+#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c
+#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000
+#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d
+#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff
+#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0
+#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00
+#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8
+#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000
+#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10
+#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000
+#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18
+#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe
+#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1
+#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3fffe
+#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1
+#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e
+#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1
+#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40
+#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6
+#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80
+#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7
+#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100
+#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8
+#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200
+#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9
+#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400
+#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa
+#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800
+#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd
+#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000
+#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18
+#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000
+#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19
+#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000
+#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a
+#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0
+#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4
+#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000
+#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14
+#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000
+#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18
+#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2
+#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1
+#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff
+#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0
+#define SMU_STATUS__SMU_DONE_MASK 0x1
+#define SMU_STATUS__SMU_DONE__SHIFT 0x0
+#define SMU_STATUS__SMU_PASS_MASK 0x2
+#define SMU_STATUS__SMU_PASS__SHIFT 0x1
+#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1
+#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0
+#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6
+#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1
+#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8
+#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3
+#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10
+#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4
+#define SMU_FIRMWARE__SMU_counter_MASK 0xf00
+#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8
+#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000
+#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10
+#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000
+#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11
+#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff
+#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0
+#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000
+#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f
+#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff
+#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0
+#define DPM_TABLE_1__SystemFlags_MASK 0xffffffff
+#define DPM_TABLE_1__SystemFlags__SHIFT 0x0
+#define DPM_TABLE_2__GraphicsPIDController_Ki_MASK 0xffffffff
+#define DPM_TABLE_2__GraphicsPIDController_Ki__SHIFT 0x0
+#define DPM_TABLE_3__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff
+#define DPM_TABLE_3__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0
+#define DPM_TABLE_4__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff
+#define DPM_TABLE_4__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0
+#define DPM_TABLE_5__GraphicsPIDController_StatePrecision_MASK 0xffffffff
+#define DPM_TABLE_5__GraphicsPIDController_StatePrecision__SHIFT 0x0
+#define DPM_TABLE_6__GraphicsPIDController_LfPrecision_MASK 0xffffffff
+#define DPM_TABLE_6__GraphicsPIDController_LfPrecision__SHIFT 0x0
+#define DPM_TABLE_7__GraphicsPIDController_LfOffset_MASK 0xffffffff
+#define DPM_TABLE_7__GraphicsPIDController_LfOffset__SHIFT 0x0
+#define DPM_TABLE_8__GraphicsPIDController_MaxState_MASK 0xffffffff
+#define DPM_TABLE_8__GraphicsPIDController_MaxState__SHIFT 0x0
+#define DPM_TABLE_9__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff
+#define DPM_TABLE_9__GraphicsPIDController_MaxLfFraction__SHIFT 0x0
+#define DPM_TABLE_10__GraphicsPIDController_StateShift_MASK 0xffffffff
+#define DPM_TABLE_10__GraphicsPIDController_StateShift__SHIFT 0x0
+#define DPM_TABLE_11__GioPIDController_Ki_MASK 0xffffffff
+#define DPM_TABLE_11__GioPIDController_Ki__SHIFT 0x0
+#define DPM_TABLE_12__GioPIDController_LFWindupUpperLim_MASK 0xffffffff
+#define DPM_TABLE_12__GioPIDController_LFWindupUpperLim__SHIFT 0x0
+#define DPM_TABLE_13__GioPIDController_LFWindupLowerLim_MASK 0xffffffff
+#define DPM_TABLE_13__GioPIDController_LFWindupLowerLim__SHIFT 0x0
+#define DPM_TABLE_14__GioPIDController_StatePrecision_MASK 0xffffffff
+#define DPM_TABLE_14__GioPIDController_StatePrecision__SHIFT 0x0
+#define DPM_TABLE_15__GioPIDController_LfPrecision_MASK 0xffffffff
+#define DPM_TABLE_15__GioPIDController_LfPrecision__SHIFT 0x0
+#define DPM_TABLE_16__GioPIDController_LfOffset_MASK 0xffffffff
+#define DPM_TABLE_16__GioPIDController_LfOffset__SHIFT 0x0
+#define DPM_TABLE_17__GioPIDController_MaxState_MASK 0xffffffff
+#define DPM_TABLE_17__GioPIDController_MaxState__SHIFT 0x0
+#define DPM_TABLE_18__GioPIDController_MaxLfFraction_MASK 0xffffffff
+#define DPM_TABLE_18__GioPIDController_MaxLfFraction__SHIFT 0x0
+#define DPM_TABLE_19__GioPIDController_StateShift_MASK 0xffffffff
+#define DPM_TABLE_19__GioPIDController_StateShift__SHIFT 0x0
+#define DPM_TABLE_20__VceLevelCount_MASK 0xff
+#define DPM_TABLE_20__VceLevelCount__SHIFT 0x0
+#define DPM_TABLE_20__UvdLevelCount_MASK 0xff00
+#define DPM_TABLE_20__UvdLevelCount__SHIFT 0x8
+#define DPM_TABLE_20__GIOLevelCount_MASK 0xff0000
+#define DPM_TABLE_20__GIOLevelCount__SHIFT 0x10
+#define DPM_TABLE_20__GraphicsDpmLevelCount_MASK 0xff000000
+#define DPM_TABLE_20__GraphicsDpmLevelCount__SHIFT 0x18
+#define DPM_TABLE_21__FpsHighThreshold_MASK 0xffff
+#define DPM_TABLE_21__FpsHighThreshold__SHIFT 0x0
+#define DPM_TABLE_21__SamuLevelCount_MASK 0xff0000
+#define DPM_TABLE_21__SamuLevelCount__SHIFT 0x10
+#define DPM_TABLE_21__AcpLevelCount_MASK 0xff000000
+#define DPM_TABLE_21__AcpLevelCount__SHIFT 0x18
+#define DPM_TABLE_22__GraphicsLevel_0_MinVddNb_MASK 0xffffffff
+#define DPM_TABLE_22__GraphicsLevel_0_MinVddNb__SHIFT 0x0
+#define DPM_TABLE_23__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_23__GraphicsLevel_0_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_24__GraphicsLevel_0_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_24__GraphicsLevel_0_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_24__GraphicsLevel_0_VidOffset_MASK 0xff0000
+#define DPM_TABLE_24__GraphicsLevel_0_VidOffset__SHIFT 0x10
+#define DPM_TABLE_24__GraphicsLevel_0_Vid_MASK 0xff000000
+#define DPM_TABLE_24__GraphicsLevel_0_Vid__SHIFT 0x18
+#define DPM_TABLE_25__GraphicsLevel_0_SclkDid_MASK 0xff
+#define DPM_TABLE_25__GraphicsLevel_0_SclkDid__SHIFT 0x0
+#define DPM_TABLE_25__GraphicsLevel_0_ForceNbPs1_MASK 0xff00
+#define DPM_TABLE_25__GraphicsLevel_0_ForceNbPs1__SHIFT 0x8
+#define DPM_TABLE_25__GraphicsLevel_0_GnbSlow_MASK 0xff0000
+#define DPM_TABLE_25__GraphicsLevel_0_GnbSlow__SHIFT 0x10
+#define DPM_TABLE_25__GraphicsLevel_0_PowerThrottle_MASK 0xff000000
+#define DPM_TABLE_25__GraphicsLevel_0_PowerThrottle__SHIFT 0x18
+#define DPM_TABLE_26__GraphicsLevel_0_UpHyst_MASK 0xff
+#define DPM_TABLE_26__GraphicsLevel_0_UpHyst__SHIFT 0x0
+#define DPM_TABLE_26__GraphicsLevel_0_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_26__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_26__GraphicsLevel_0_EnabledForActivity_MASK 0xff0000
+#define DPM_TABLE_26__GraphicsLevel_0_EnabledForActivity__SHIFT 0x10
+#define DPM_TABLE_26__GraphicsLevel_0_DisplayWatermark_MASK 0xff000000
+#define DPM_TABLE_26__GraphicsLevel_0_DisplayWatermark__SHIFT 0x18
+#define DPM_TABLE_27__GraphicsLevel_0_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_27__GraphicsLevel_0_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_27__GraphicsLevel_0_DeepSleepDivId_MASK 0xff00
+#define DPM_TABLE_27__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x8
+#define DPM_TABLE_27__GraphicsLevel_0_VoltageDownHyst_MASK 0xff0000
+#define DPM_TABLE_27__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x10
+#define DPM_TABLE_27__GraphicsLevel_0_DownHyst_MASK 0xff000000
+#define DPM_TABLE_27__GraphicsLevel_0_DownHyst__SHIFT 0x18
+#define DPM_TABLE_28__GraphicsLevel_0_reserved_MASK 0xffffffff
+#define DPM_TABLE_28__GraphicsLevel_0_reserved__SHIFT 0x0
+#define DPM_TABLE_29__GraphicsLevel_1_MinVddNb_MASK 0xffffffff
+#define DPM_TABLE_29__GraphicsLevel_1_MinVddNb__SHIFT 0x0
+#define DPM_TABLE_30__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_30__GraphicsLevel_1_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_31__GraphicsLevel_1_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_31__GraphicsLevel_1_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_31__GraphicsLevel_1_VidOffset_MASK 0xff0000
+#define DPM_TABLE_31__GraphicsLevel_1_VidOffset__SHIFT 0x10
+#define DPM_TABLE_31__GraphicsLevel_1_Vid_MASK 0xff000000
+#define DPM_TABLE_31__GraphicsLevel_1_Vid__SHIFT 0x18
+#define DPM_TABLE_32__GraphicsLevel_1_SclkDid_MASK 0xff
+#define DPM_TABLE_32__GraphicsLevel_1_SclkDid__SHIFT 0x0
+#define DPM_TABLE_32__GraphicsLevel_1_ForceNbPs1_MASK 0xff00
+#define DPM_TABLE_32__GraphicsLevel_1_ForceNbPs1__SHIFT 0x8
+#define DPM_TABLE_32__GraphicsLevel_1_GnbSlow_MASK 0xff0000
+#define DPM_TABLE_32__GraphicsLevel_1_GnbSlow__SHIFT 0x10
+#define DPM_TABLE_32__GraphicsLevel_1_PowerThrottle_MASK 0xff000000
+#define DPM_TABLE_32__GraphicsLevel_1_PowerThrottle__SHIFT 0x18
+#define DPM_TABLE_33__GraphicsLevel_1_UpHyst_MASK 0xff
+#define DPM_TABLE_33__GraphicsLevel_1_UpHyst__SHIFT 0x0
+#define DPM_TABLE_33__GraphicsLevel_1_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_33__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_33__GraphicsLevel_1_EnabledForActivity_MASK 0xff0000
+#define DPM_TABLE_33__GraphicsLevel_1_EnabledForActivity__SHIFT 0x10
+#define DPM_TABLE_33__GraphicsLevel_1_DisplayWatermark_MASK 0xff000000
+#define DPM_TABLE_33__GraphicsLevel_1_DisplayWatermark__SHIFT 0x18
+#define DPM_TABLE_34__GraphicsLevel_1_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_34__GraphicsLevel_1_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_34__GraphicsLevel_1_DeepSleepDivId_MASK 0xff00
+#define DPM_TABLE_34__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x8
+#define DPM_TABLE_34__GraphicsLevel_1_VoltageDownHyst_MASK 0xff0000
+#define DPM_TABLE_34__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x10
+#define DPM_TABLE_34__GraphicsLevel_1_DownHyst_MASK 0xff000000
+#define DPM_TABLE_34__GraphicsLevel_1_DownHyst__SHIFT 0x18
+#define DPM_TABLE_35__GraphicsLevel_1_reserved_MASK 0xffffffff
+#define DPM_TABLE_35__GraphicsLevel_1_reserved__SHIFT 0x0
+#define DPM_TABLE_36__GraphicsLevel_2_MinVddNb_MASK 0xffffffff
+#define DPM_TABLE_36__GraphicsLevel_2_MinVddNb__SHIFT 0x0
+#define DPM_TABLE_37__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_37__GraphicsLevel_2_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_38__GraphicsLevel_2_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_38__GraphicsLevel_2_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_38__GraphicsLevel_2_VidOffset_MASK 0xff0000
+#define DPM_TABLE_38__GraphicsLevel_2_VidOffset__SHIFT 0x10
+#define DPM_TABLE_38__GraphicsLevel_2_Vid_MASK 0xff000000
+#define DPM_TABLE_38__GraphicsLevel_2_Vid__SHIFT 0x18
+#define DPM_TABLE_39__GraphicsLevel_2_SclkDid_MASK 0xff
+#define DPM_TABLE_39__GraphicsLevel_2_SclkDid__SHIFT 0x0
+#define DPM_TABLE_39__GraphicsLevel_2_ForceNbPs1_MASK 0xff00
+#define DPM_TABLE_39__GraphicsLevel_2_ForceNbPs1__SHIFT 0x8
+#define DPM_TABLE_39__GraphicsLevel_2_GnbSlow_MASK 0xff0000
+#define DPM_TABLE_39__GraphicsLevel_2_GnbSlow__SHIFT 0x10
+#define DPM_TABLE_39__GraphicsLevel_2_PowerThrottle_MASK 0xff000000
+#define DPM_TABLE_39__GraphicsLevel_2_PowerThrottle__SHIFT 0x18
+#define DPM_TABLE_40__GraphicsLevel_2_UpHyst_MASK 0xff
+#define DPM_TABLE_40__GraphicsLevel_2_UpHyst__SHIFT 0x0
+#define DPM_TABLE_40__GraphicsLevel_2_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_40__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_40__GraphicsLevel_2_EnabledForActivity_MASK 0xff0000
+#define DPM_TABLE_40__GraphicsLevel_2_EnabledForActivity__SHIFT 0x10
+#define DPM_TABLE_40__GraphicsLevel_2_DisplayWatermark_MASK 0xff000000
+#define DPM_TABLE_40__GraphicsLevel_2_DisplayWatermark__SHIFT 0x18
+#define DPM_TABLE_41__GraphicsLevel_2_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_41__GraphicsLevel_2_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_41__GraphicsLevel_2_DeepSleepDivId_MASK 0xff00
+#define DPM_TABLE_41__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x8
+#define DPM_TABLE_41__GraphicsLevel_2_VoltageDownHyst_MASK 0xff0000
+#define DPM_TABLE_41__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x10
+#define DPM_TABLE_41__GraphicsLevel_2_DownHyst_MASK 0xff000000
+#define DPM_TABLE_41__GraphicsLevel_2_DownHyst__SHIFT 0x18
+#define DPM_TABLE_42__GraphicsLevel_2_reserved_MASK 0xffffffff
+#define DPM_TABLE_42__GraphicsLevel_2_reserved__SHIFT 0x0
+#define DPM_TABLE_43__GraphicsLevel_3_MinVddNb_MASK 0xffffffff
+#define DPM_TABLE_43__GraphicsLevel_3_MinVddNb__SHIFT 0x0
+#define DPM_TABLE_44__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_44__GraphicsLevel_3_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_45__GraphicsLevel_3_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_45__GraphicsLevel_3_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_45__GraphicsLevel_3_VidOffset_MASK 0xff0000
+#define DPM_TABLE_45__GraphicsLevel_3_VidOffset__SHIFT 0x10
+#define DPM_TABLE_45__GraphicsLevel_3_Vid_MASK 0xff000000
+#define DPM_TABLE_45__GraphicsLevel_3_Vid__SHIFT 0x18
+#define DPM_TABLE_46__GraphicsLevel_3_SclkDid_MASK 0xff
+#define DPM_TABLE_46__GraphicsLevel_3_SclkDid__SHIFT 0x0
+#define DPM_TABLE_46__GraphicsLevel_3_ForceNbPs1_MASK 0xff00
+#define DPM_TABLE_46__GraphicsLevel_3_ForceNbPs1__SHIFT 0x8
+#define DPM_TABLE_46__GraphicsLevel_3_GnbSlow_MASK 0xff0000
+#define DPM_TABLE_46__GraphicsLevel_3_GnbSlow__SHIFT 0x10
+#define DPM_TABLE_46__GraphicsLevel_3_PowerThrottle_MASK 0xff000000
+#define DPM_TABLE_46__GraphicsLevel_3_PowerThrottle__SHIFT 0x18
+#define DPM_TABLE_47__GraphicsLevel_3_UpHyst_MASK 0xff
+#define DPM_TABLE_47__GraphicsLevel_3_UpHyst__SHIFT 0x0
+#define DPM_TABLE_47__GraphicsLevel_3_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_47__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_47__GraphicsLevel_3_EnabledForActivity_MASK 0xff0000
+#define DPM_TABLE_47__GraphicsLevel_3_EnabledForActivity__SHIFT 0x10
+#define DPM_TABLE_47__GraphicsLevel_3_DisplayWatermark_MASK 0xff000000
+#define DPM_TABLE_47__GraphicsLevel_3_DisplayWatermark__SHIFT 0x18
+#define DPM_TABLE_48__GraphicsLevel_3_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_48__GraphicsLevel_3_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_48__GraphicsLevel_3_DeepSleepDivId_MASK 0xff00
+#define DPM_TABLE_48__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x8
+#define DPM_TABLE_48__GraphicsLevel_3_VoltageDownHyst_MASK 0xff0000
+#define DPM_TABLE_48__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x10
+#define DPM_TABLE_48__GraphicsLevel_3_DownHyst_MASK 0xff000000
+#define DPM_TABLE_48__GraphicsLevel_3_DownHyst__SHIFT 0x18
+#define DPM_TABLE_49__GraphicsLevel_3_reserved_MASK 0xffffffff
+#define DPM_TABLE_49__GraphicsLevel_3_reserved__SHIFT 0x0
+#define DPM_TABLE_50__GraphicsLevel_4_MinVddNb_MASK 0xffffffff
+#define DPM_TABLE_50__GraphicsLevel_4_MinVddNb__SHIFT 0x0
+#define DPM_TABLE_51__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_51__GraphicsLevel_4_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_52__GraphicsLevel_4_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_52__GraphicsLevel_4_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_52__GraphicsLevel_4_VidOffset_MASK 0xff0000
+#define DPM_TABLE_52__GraphicsLevel_4_VidOffset__SHIFT 0x10
+#define DPM_TABLE_52__GraphicsLevel_4_Vid_MASK 0xff000000
+#define DPM_TABLE_52__GraphicsLevel_4_Vid__SHIFT 0x18
+#define DPM_TABLE_53__GraphicsLevel_4_SclkDid_MASK 0xff
+#define DPM_TABLE_53__GraphicsLevel_4_SclkDid__SHIFT 0x0
+#define DPM_TABLE_53__GraphicsLevel_4_ForceNbPs1_MASK 0xff00
+#define DPM_TABLE_53__GraphicsLevel_4_ForceNbPs1__SHIFT 0x8
+#define DPM_TABLE_53__GraphicsLevel_4_GnbSlow_MASK 0xff0000
+#define DPM_TABLE_53__GraphicsLevel_4_GnbSlow__SHIFT 0x10
+#define DPM_TABLE_53__GraphicsLevel_4_PowerThrottle_MASK 0xff000000
+#define DPM_TABLE_53__GraphicsLevel_4_PowerThrottle__SHIFT 0x18
+#define DPM_TABLE_54__GraphicsLevel_4_UpHyst_MASK 0xff
+#define DPM_TABLE_54__GraphicsLevel_4_UpHyst__SHIFT 0x0
+#define DPM_TABLE_54__GraphicsLevel_4_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_54__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_54__GraphicsLevel_4_EnabledForActivity_MASK 0xff0000
+#define DPM_TABLE_54__GraphicsLevel_4_EnabledForActivity__SHIFT 0x10
+#define DPM_TABLE_54__GraphicsLevel_4_DisplayWatermark_MASK 0xff000000
+#define DPM_TABLE_54__GraphicsLevel_4_DisplayWatermark__SHIFT 0x18
+#define DPM_TABLE_55__GraphicsLevel_4_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_55__GraphicsLevel_4_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_55__GraphicsLevel_4_DeepSleepDivId_MASK 0xff00
+#define DPM_TABLE_55__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x8
+#define DPM_TABLE_55__GraphicsLevel_4_VoltageDownHyst_MASK 0xff0000
+#define DPM_TABLE_55__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x10
+#define DPM_TABLE_55__GraphicsLevel_4_DownHyst_MASK 0xff000000
+#define DPM_TABLE_55__GraphicsLevel_4_DownHyst__SHIFT 0x18
+#define DPM_TABLE_56__GraphicsLevel_4_reserved_MASK 0xffffffff
+#define DPM_TABLE_56__GraphicsLevel_4_reserved__SHIFT 0x0
+#define DPM_TABLE_57__GraphicsLevel_5_MinVddNb_MASK 0xffffffff
+#define DPM_TABLE_57__GraphicsLevel_5_MinVddNb__SHIFT 0x0
+#define DPM_TABLE_58__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_58__GraphicsLevel_5_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_59__GraphicsLevel_5_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_59__GraphicsLevel_5_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_59__GraphicsLevel_5_VidOffset_MASK 0xff0000
+#define DPM_TABLE_59__GraphicsLevel_5_VidOffset__SHIFT 0x10
+#define DPM_TABLE_59__GraphicsLevel_5_Vid_MASK 0xff000000
+#define DPM_TABLE_59__GraphicsLevel_5_Vid__SHIFT 0x18
+#define DPM_TABLE_60__GraphicsLevel_5_SclkDid_MASK 0xff
+#define DPM_TABLE_60__GraphicsLevel_5_SclkDid__SHIFT 0x0
+#define DPM_TABLE_60__GraphicsLevel_5_ForceNbPs1_MASK 0xff00
+#define DPM_TABLE_60__GraphicsLevel_5_ForceNbPs1__SHIFT 0x8
+#define DPM_TABLE_60__GraphicsLevel_5_GnbSlow_MASK 0xff0000
+#define DPM_TABLE_60__GraphicsLevel_5_GnbSlow__SHIFT 0x10
+#define DPM_TABLE_60__GraphicsLevel_5_PowerThrottle_MASK 0xff000000
+#define DPM_TABLE_60__GraphicsLevel_5_PowerThrottle__SHIFT 0x18
+#define DPM_TABLE_61__GraphicsLevel_5_UpHyst_MASK 0xff
+#define DPM_TABLE_61__GraphicsLevel_5_UpHyst__SHIFT 0x0
+#define DPM_TABLE_61__GraphicsLevel_5_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_61__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_61__GraphicsLevel_5_EnabledForActivity_MASK 0xff0000
+#define DPM_TABLE_61__GraphicsLevel_5_EnabledForActivity__SHIFT 0x10
+#define DPM_TABLE_61__GraphicsLevel_5_DisplayWatermark_MASK 0xff000000
+#define DPM_TABLE_61__GraphicsLevel_5_DisplayWatermark__SHIFT 0x18
+#define DPM_TABLE_62__GraphicsLevel_5_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_62__GraphicsLevel_5_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_62__GraphicsLevel_5_DeepSleepDivId_MASK 0xff00
+#define DPM_TABLE_62__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x8
+#define DPM_TABLE_62__GraphicsLevel_5_VoltageDownHyst_MASK 0xff0000
+#define DPM_TABLE_62__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x10
+#define DPM_TABLE_62__GraphicsLevel_5_DownHyst_MASK 0xff000000
+#define DPM_TABLE_62__GraphicsLevel_5_DownHyst__SHIFT 0x18
+#define DPM_TABLE_63__GraphicsLevel_5_reserved_MASK 0xffffffff
+#define DPM_TABLE_63__GraphicsLevel_5_reserved__SHIFT 0x0
+#define DPM_TABLE_64__GraphicsLevel_6_MinVddNb_MASK 0xffffffff
+#define DPM_TABLE_64__GraphicsLevel_6_MinVddNb__SHIFT 0x0
+#define DPM_TABLE_65__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_65__GraphicsLevel_6_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_66__GraphicsLevel_6_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_66__GraphicsLevel_6_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_66__GraphicsLevel_6_VidOffset_MASK 0xff0000
+#define DPM_TABLE_66__GraphicsLevel_6_VidOffset__SHIFT 0x10
+#define DPM_TABLE_66__GraphicsLevel_6_Vid_MASK 0xff000000
+#define DPM_TABLE_66__GraphicsLevel_6_Vid__SHIFT 0x18
+#define DPM_TABLE_67__GraphicsLevel_6_SclkDid_MASK 0xff
+#define DPM_TABLE_67__GraphicsLevel_6_SclkDid__SHIFT 0x0
+#define DPM_TABLE_67__GraphicsLevel_6_ForceNbPs1_MASK 0xff00
+#define DPM_TABLE_67__GraphicsLevel_6_ForceNbPs1__SHIFT 0x8
+#define DPM_TABLE_67__GraphicsLevel_6_GnbSlow_MASK 0xff0000
+#define DPM_TABLE_67__GraphicsLevel_6_GnbSlow__SHIFT 0x10
+#define DPM_TABLE_67__GraphicsLevel_6_PowerThrottle_MASK 0xff000000
+#define DPM_TABLE_67__GraphicsLevel_6_PowerThrottle__SHIFT 0x18
+#define DPM_TABLE_68__GraphicsLevel_6_UpHyst_MASK 0xff
+#define DPM_TABLE_68__GraphicsLevel_6_UpHyst__SHIFT 0x0
+#define DPM_TABLE_68__GraphicsLevel_6_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_68__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_68__GraphicsLevel_6_EnabledForActivity_MASK 0xff0000
+#define DPM_TABLE_68__GraphicsLevel_6_EnabledForActivity__SHIFT 0x10
+#define DPM_TABLE_68__GraphicsLevel_6_DisplayWatermark_MASK 0xff000000
+#define DPM_TABLE_68__GraphicsLevel_6_DisplayWatermark__SHIFT 0x18
+#define DPM_TABLE_69__GraphicsLevel_6_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_69__GraphicsLevel_6_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_69__GraphicsLevel_6_DeepSleepDivId_MASK 0xff00
+#define DPM_TABLE_69__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x8
+#define DPM_TABLE_69__GraphicsLevel_6_VoltageDownHyst_MASK 0xff0000
+#define DPM_TABLE_69__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x10
+#define DPM_TABLE_69__GraphicsLevel_6_DownHyst_MASK 0xff000000
+#define DPM_TABLE_69__GraphicsLevel_6_DownHyst__SHIFT 0x18
+#define DPM_TABLE_70__GraphicsLevel_6_reserved_MASK 0xffffffff
+#define DPM_TABLE_70__GraphicsLevel_6_reserved__SHIFT 0x0
+#define DPM_TABLE_71__GraphicsLevel_7_MinVddNb_MASK 0xffffffff
+#define DPM_TABLE_71__GraphicsLevel_7_MinVddNb__SHIFT 0x0
+#define DPM_TABLE_72__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_72__GraphicsLevel_7_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_73__GraphicsLevel_7_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_73__GraphicsLevel_7_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_73__GraphicsLevel_7_VidOffset_MASK 0xff0000
+#define DPM_TABLE_73__GraphicsLevel_7_VidOffset__SHIFT 0x10
+#define DPM_TABLE_73__GraphicsLevel_7_Vid_MASK 0xff000000
+#define DPM_TABLE_73__GraphicsLevel_7_Vid__SHIFT 0x18
+#define DPM_TABLE_74__GraphicsLevel_7_SclkDid_MASK 0xff
+#define DPM_TABLE_74__GraphicsLevel_7_SclkDid__SHIFT 0x0
+#define DPM_TABLE_74__GraphicsLevel_7_ForceNbPs1_MASK 0xff00
+#define DPM_TABLE_74__GraphicsLevel_7_ForceNbPs1__SHIFT 0x8
+#define DPM_TABLE_74__GraphicsLevel_7_GnbSlow_MASK 0xff0000
+#define DPM_TABLE_74__GraphicsLevel_7_GnbSlow__SHIFT 0x10
+#define DPM_TABLE_74__GraphicsLevel_7_PowerThrottle_MASK 0xff000000
+#define DPM_TABLE_74__GraphicsLevel_7_PowerThrottle__SHIFT 0x18
+#define DPM_TABLE_75__GraphicsLevel_7_UpHyst_MASK 0xff
+#define DPM_TABLE_75__GraphicsLevel_7_UpHyst__SHIFT 0x0
+#define DPM_TABLE_75__GraphicsLevel_7_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_75__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_75__GraphicsLevel_7_EnabledForActivity_MASK 0xff0000
+#define DPM_TABLE_75__GraphicsLevel_7_EnabledForActivity__SHIFT 0x10
+#define DPM_TABLE_75__GraphicsLevel_7_DisplayWatermark_MASK 0xff000000
+#define DPM_TABLE_75__GraphicsLevel_7_DisplayWatermark__SHIFT 0x18
+#define DPM_TABLE_76__GraphicsLevel_7_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_76__GraphicsLevel_7_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_76__GraphicsLevel_7_DeepSleepDivId_MASK 0xff00
+#define DPM_TABLE_76__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x8
+#define DPM_TABLE_76__GraphicsLevel_7_VoltageDownHyst_MASK 0xff0000
+#define DPM_TABLE_76__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x10
+#define DPM_TABLE_76__GraphicsLevel_7_DownHyst_MASK 0xff000000
+#define DPM_TABLE_76__GraphicsLevel_7_DownHyst__SHIFT 0x18
+#define DPM_TABLE_77__GraphicsLevel_7_reserved_MASK 0xffffffff
+#define DPM_TABLE_77__GraphicsLevel_7_reserved__SHIFT 0x0
+#define DPM_TABLE_78__ACPILevel_Flags_MASK 0xffffffff
+#define DPM_TABLE_78__ACPILevel_Flags__SHIFT 0x0
+#define DPM_TABLE_79__ACPILevel_MinVddNb_MASK 0xffffffff
+#define DPM_TABLE_79__ACPILevel_MinVddNb__SHIFT 0x0
+#define DPM_TABLE_80__ACPILevel_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_80__ACPILevel_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_81__ACPILevel_DisplayWatermark_MASK 0xff
+#define DPM_TABLE_81__ACPILevel_DisplayWatermark__SHIFT 0x0
+#define DPM_TABLE_81__ACPILevel_ForceNbPs1_MASK 0xff00
+#define DPM_TABLE_81__ACPILevel_ForceNbPs1__SHIFT 0x8
+#define DPM_TABLE_81__ACPILevel_GnbSlow_MASK 0xff0000
+#define DPM_TABLE_81__ACPILevel_GnbSlow__SHIFT 0x10
+#define DPM_TABLE_81__ACPILevel_SclkDid_MASK 0xff000000
+#define DPM_TABLE_81__ACPILevel_SclkDid__SHIFT 0x18
+#define DPM_TABLE_82__ACPILevel_padding_2_MASK 0xff
+#define DPM_TABLE_82__ACPILevel_padding_2__SHIFT 0x0
+#define DPM_TABLE_82__ACPILevel_padding_1_MASK 0xff00
+#define DPM_TABLE_82__ACPILevel_padding_1__SHIFT 0x8
+#define DPM_TABLE_82__ACPILevel_padding_0_MASK 0xff0000
+#define DPM_TABLE_82__ACPILevel_padding_0__SHIFT 0x10
+#define DPM_TABLE_82__ACPILevel_DeepSleepDivId_MASK 0xff000000
+#define DPM_TABLE_82__ACPILevel_DeepSleepDivId__SHIFT 0x18
+#define DPM_TABLE_83__UvdLevel_0_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_83__UvdLevel_0_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_84__UvdLevel_0_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_84__UvdLevel_0_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_85__UvdLevel_0_DclkDivider_MASK 0xff
+#define DPM_TABLE_85__UvdLevel_0_DclkDivider__SHIFT 0x0
+#define DPM_TABLE_85__UvdLevel_0_VclkDivider_MASK 0xff00
+#define DPM_TABLE_85__UvdLevel_0_VclkDivider__SHIFT 0x8
+#define DPM_TABLE_85__UvdLevel_0_MinVddNb_MASK 0xffff0000
+#define DPM_TABLE_85__UvdLevel_0_MinVddNb__SHIFT 0x10
+#define DPM_TABLE_86__UvdLevel_0_padding_1_MASK 0xff
+#define DPM_TABLE_86__UvdLevel_0_padding_1__SHIFT 0x0
+#define DPM_TABLE_86__UvdLevel_0_padding_0_MASK 0xff00
+#define DPM_TABLE_86__UvdLevel_0_padding_0__SHIFT 0x8
+#define DPM_TABLE_86__UvdLevel_0_DClkBypassCntl_MASK 0xff0000
+#define DPM_TABLE_86__UvdLevel_0_DClkBypassCntl__SHIFT 0x10
+#define DPM_TABLE_86__UvdLevel_0_VClkBypassCntl_MASK 0xff000000
+#define DPM_TABLE_86__UvdLevel_0_VClkBypassCntl__SHIFT 0x18
+#define DPM_TABLE_87__UvdLevel_1_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_87__UvdLevel_1_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_88__UvdLevel_1_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_88__UvdLevel_1_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_89__UvdLevel_1_DclkDivider_MASK 0xff
+#define DPM_TABLE_89__UvdLevel_1_DclkDivider__SHIFT 0x0
+#define DPM_TABLE_89__UvdLevel_1_VclkDivider_MASK 0xff00
+#define DPM_TABLE_89__UvdLevel_1_VclkDivider__SHIFT 0x8
+#define DPM_TABLE_89__UvdLevel_1_MinVddNb_MASK 0xffff0000
+#define DPM_TABLE_89__UvdLevel_1_MinVddNb__SHIFT 0x10
+#define DPM_TABLE_90__UvdLevel_1_padding_1_MASK 0xff
+#define DPM_TABLE_90__UvdLevel_1_padding_1__SHIFT 0x0
+#define DPM_TABLE_90__UvdLevel_1_padding_0_MASK 0xff00
+#define DPM_TABLE_90__UvdLevel_1_padding_0__SHIFT 0x8
+#define DPM_TABLE_90__UvdLevel_1_DClkBypassCntl_MASK 0xff0000
+#define DPM_TABLE_90__UvdLevel_1_DClkBypassCntl__SHIFT 0x10
+#define DPM_TABLE_90__UvdLevel_1_VClkBypassCntl_MASK 0xff000000
+#define DPM_TABLE_90__UvdLevel_1_VClkBypassCntl__SHIFT 0x18
+#define DPM_TABLE_91__UvdLevel_2_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_91__UvdLevel_2_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_92__UvdLevel_2_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_92__UvdLevel_2_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_93__UvdLevel_2_DclkDivider_MASK 0xff
+#define DPM_TABLE_93__UvdLevel_2_DclkDivider__SHIFT 0x0
+#define DPM_TABLE_93__UvdLevel_2_VclkDivider_MASK 0xff00
+#define DPM_TABLE_93__UvdLevel_2_VclkDivider__SHIFT 0x8
+#define DPM_TABLE_93__UvdLevel_2_MinVddNb_MASK 0xffff0000
+#define DPM_TABLE_93__UvdLevel_2_MinVddNb__SHIFT 0x10
+#define DPM_TABLE_94__UvdLevel_2_padding_1_MASK 0xff
+#define DPM_TABLE_94__UvdLevel_2_padding_1__SHIFT 0x0
+#define DPM_TABLE_94__UvdLevel_2_padding_0_MASK 0xff00
+#define DPM_TABLE_94__UvdLevel_2_padding_0__SHIFT 0x8
+#define DPM_TABLE_94__UvdLevel_2_DClkBypassCntl_MASK 0xff0000
+#define DPM_TABLE_94__UvdLevel_2_DClkBypassCntl__SHIFT 0x10
+#define DPM_TABLE_94__UvdLevel_2_VClkBypassCntl_MASK 0xff000000
+#define DPM_TABLE_94__UvdLevel_2_VClkBypassCntl__SHIFT 0x18
+#define DPM_TABLE_95__UvdLevel_3_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_95__UvdLevel_3_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_96__UvdLevel_3_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_96__UvdLevel_3_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_97__UvdLevel_3_DclkDivider_MASK 0xff
+#define DPM_TABLE_97__UvdLevel_3_DclkDivider__SHIFT 0x0
+#define DPM_TABLE_97__UvdLevel_3_VclkDivider_MASK 0xff00
+#define DPM_TABLE_97__UvdLevel_3_VclkDivider__SHIFT 0x8
+#define DPM_TABLE_97__UvdLevel_3_MinVddNb_MASK 0xffff0000
+#define DPM_TABLE_97__UvdLevel_3_MinVddNb__SHIFT 0x10
+#define DPM_TABLE_98__UvdLevel_3_padding_1_MASK 0xff
+#define DPM_TABLE_98__UvdLevel_3_padding_1__SHIFT 0x0
+#define DPM_TABLE_98__UvdLevel_3_padding_0_MASK 0xff00
+#define DPM_TABLE_98__UvdLevel_3_padding_0__SHIFT 0x8
+#define DPM_TABLE_98__UvdLevel_3_DClkBypassCntl_MASK 0xff0000
+#define DPM_TABLE_98__UvdLevel_3_DClkBypassCntl__SHIFT 0x10
+#define DPM_TABLE_98__UvdLevel_3_VClkBypassCntl_MASK 0xff000000
+#define DPM_TABLE_98__UvdLevel_3_VClkBypassCntl__SHIFT 0x18
+#define DPM_TABLE_99__UvdLevel_4_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_99__UvdLevel_4_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_100__UvdLevel_4_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_100__UvdLevel_4_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_101__UvdLevel_4_DclkDivider_MASK 0xff
+#define DPM_TABLE_101__UvdLevel_4_DclkDivider__SHIFT 0x0
+#define DPM_TABLE_101__UvdLevel_4_VclkDivider_MASK 0xff00
+#define DPM_TABLE_101__UvdLevel_4_VclkDivider__SHIFT 0x8
+#define DPM_TABLE_101__UvdLevel_4_MinVddNb_MASK 0xffff0000
+#define DPM_TABLE_101__UvdLevel_4_MinVddNb__SHIFT 0x10
+#define DPM_TABLE_102__UvdLevel_4_padding_1_MASK 0xff
+#define DPM_TABLE_102__UvdLevel_4_padding_1__SHIFT 0x0
+#define DPM_TABLE_102__UvdLevel_4_padding_0_MASK 0xff00
+#define DPM_TABLE_102__UvdLevel_4_padding_0__SHIFT 0x8
+#define DPM_TABLE_102__UvdLevel_4_DClkBypassCntl_MASK 0xff0000
+#define DPM_TABLE_102__UvdLevel_4_DClkBypassCntl__SHIFT 0x10
+#define DPM_TABLE_102__UvdLevel_4_VClkBypassCntl_MASK 0xff000000
+#define DPM_TABLE_102__UvdLevel_4_VClkBypassCntl__SHIFT 0x18
+#define DPM_TABLE_103__UvdLevel_5_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_103__UvdLevel_5_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_104__UvdLevel_5_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_104__UvdLevel_5_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_105__UvdLevel_5_DclkDivider_MASK 0xff
+#define DPM_TABLE_105__UvdLevel_5_DclkDivider__SHIFT 0x0
+#define DPM_TABLE_105__UvdLevel_5_VclkDivider_MASK 0xff00
+#define DPM_TABLE_105__UvdLevel_5_VclkDivider__SHIFT 0x8
+#define DPM_TABLE_105__UvdLevel_5_MinVddNb_MASK 0xffff0000
+#define DPM_TABLE_105__UvdLevel_5_MinVddNb__SHIFT 0x10
+#define DPM_TABLE_106__UvdLevel_5_padding_1_MASK 0xff
+#define DPM_TABLE_106__UvdLevel_5_padding_1__SHIFT 0x0
+#define DPM_TABLE_106__UvdLevel_5_padding_0_MASK 0xff00
+#define DPM_TABLE_106__UvdLevel_5_padding_0__SHIFT 0x8
+#define DPM_TABLE_106__UvdLevel_5_DClkBypassCntl_MASK 0xff0000
+#define DPM_TABLE_106__UvdLevel_5_DClkBypassCntl__SHIFT 0x10
+#define DPM_TABLE_106__UvdLevel_5_VClkBypassCntl_MASK 0xff000000
+#define DPM_TABLE_106__UvdLevel_5_VClkBypassCntl__SHIFT 0x18
+#define DPM_TABLE_107__UvdLevel_6_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_107__UvdLevel_6_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_108__UvdLevel_6_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_108__UvdLevel_6_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_109__UvdLevel_6_DclkDivider_MASK 0xff
+#define DPM_TABLE_109__UvdLevel_6_DclkDivider__SHIFT 0x0
+#define DPM_TABLE_109__UvdLevel_6_VclkDivider_MASK 0xff00
+#define DPM_TABLE_109__UvdLevel_6_VclkDivider__SHIFT 0x8
+#define DPM_TABLE_109__UvdLevel_6_MinVddNb_MASK 0xffff0000
+#define DPM_TABLE_109__UvdLevel_6_MinVddNb__SHIFT 0x10
+#define DPM_TABLE_110__UvdLevel_6_padding_1_MASK 0xff
+#define DPM_TABLE_110__UvdLevel_6_padding_1__SHIFT 0x0
+#define DPM_TABLE_110__UvdLevel_6_padding_0_MASK 0xff00
+#define DPM_TABLE_110__UvdLevel_6_padding_0__SHIFT 0x8
+#define DPM_TABLE_110__UvdLevel_6_DClkBypassCntl_MASK 0xff0000
+#define DPM_TABLE_110__UvdLevel_6_DClkBypassCntl__SHIFT 0x10
+#define DPM_TABLE_110__UvdLevel_6_VClkBypassCntl_MASK 0xff000000
+#define DPM_TABLE_110__UvdLevel_6_VClkBypassCntl__SHIFT 0x18
+#define DPM_TABLE_111__UvdLevel_7_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_111__UvdLevel_7_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_112__UvdLevel_7_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_112__UvdLevel_7_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_113__UvdLevel_7_DclkDivider_MASK 0xff
+#define DPM_TABLE_113__UvdLevel_7_DclkDivider__SHIFT 0x0
+#define DPM_TABLE_113__UvdLevel_7_VclkDivider_MASK 0xff00
+#define DPM_TABLE_113__UvdLevel_7_VclkDivider__SHIFT 0x8
+#define DPM_TABLE_113__UvdLevel_7_MinVddNb_MASK 0xffff0000
+#define DPM_TABLE_113__UvdLevel_7_MinVddNb__SHIFT 0x10
+#define DPM_TABLE_114__UvdLevel_7_padding_1_MASK 0xff
+#define DPM_TABLE_114__UvdLevel_7_padding_1__SHIFT 0x0
+#define DPM_TABLE_114__UvdLevel_7_padding_0_MASK 0xff00
+#define DPM_TABLE_114__UvdLevel_7_padding_0__SHIFT 0x8
+#define DPM_TABLE_114__UvdLevel_7_DClkBypassCntl_MASK 0xff0000
+#define DPM_TABLE_114__UvdLevel_7_DClkBypassCntl__SHIFT 0x10
+#define DPM_TABLE_114__UvdLevel_7_VClkBypassCntl_MASK 0xff000000
+#define DPM_TABLE_114__UvdLevel_7_VClkBypassCntl__SHIFT 0x18
+#define DPM_TABLE_115__VceLevel_0_Frequency_MASK 0xffffffff
+#define DPM_TABLE_115__VceLevel_0_Frequency__SHIFT 0x0
+#define DPM_TABLE_116__VceLevel_0_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_116__VceLevel_0_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_116__VceLevel_0_Divider_MASK 0xff00
+#define DPM_TABLE_116__VceLevel_0_Divider__SHIFT 0x8
+#define DPM_TABLE_116__VceLevel_0_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_116__VceLevel_0_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_117__VceLevel_0_Reserved_MASK 0xffffffff
+#define DPM_TABLE_117__VceLevel_0_Reserved__SHIFT 0x0
+#define DPM_TABLE_118__VceLevel_1_Frequency_MASK 0xffffffff
+#define DPM_TABLE_118__VceLevel_1_Frequency__SHIFT 0x0
+#define DPM_TABLE_119__VceLevel_1_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_119__VceLevel_1_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_119__VceLevel_1_Divider_MASK 0xff00
+#define DPM_TABLE_119__VceLevel_1_Divider__SHIFT 0x8
+#define DPM_TABLE_119__VceLevel_1_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_119__VceLevel_1_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_120__VceLevel_1_Reserved_MASK 0xffffffff
+#define DPM_TABLE_120__VceLevel_1_Reserved__SHIFT 0x0
+#define DPM_TABLE_121__VceLevel_2_Frequency_MASK 0xffffffff
+#define DPM_TABLE_121__VceLevel_2_Frequency__SHIFT 0x0
+#define DPM_TABLE_122__VceLevel_2_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_122__VceLevel_2_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_122__VceLevel_2_Divider_MASK 0xff00
+#define DPM_TABLE_122__VceLevel_2_Divider__SHIFT 0x8
+#define DPM_TABLE_122__VceLevel_2_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_122__VceLevel_2_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_123__VceLevel_2_Reserved_MASK 0xffffffff
+#define DPM_TABLE_123__VceLevel_2_Reserved__SHIFT 0x0
+#define DPM_TABLE_124__VceLevel_3_Frequency_MASK 0xffffffff
+#define DPM_TABLE_124__VceLevel_3_Frequency__SHIFT 0x0
+#define DPM_TABLE_125__VceLevel_3_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_125__VceLevel_3_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_125__VceLevel_3_Divider_MASK 0xff00
+#define DPM_TABLE_125__VceLevel_3_Divider__SHIFT 0x8
+#define DPM_TABLE_125__VceLevel_3_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_125__VceLevel_3_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_126__VceLevel_3_Reserved_MASK 0xffffffff
+#define DPM_TABLE_126__VceLevel_3_Reserved__SHIFT 0x0
+#define DPM_TABLE_127__VceLevel_4_Frequency_MASK 0xffffffff
+#define DPM_TABLE_127__VceLevel_4_Frequency__SHIFT 0x0
+#define DPM_TABLE_128__VceLevel_4_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_128__VceLevel_4_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_128__VceLevel_4_Divider_MASK 0xff00
+#define DPM_TABLE_128__VceLevel_4_Divider__SHIFT 0x8
+#define DPM_TABLE_128__VceLevel_4_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_128__VceLevel_4_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_129__VceLevel_4_Reserved_MASK 0xffffffff
+#define DPM_TABLE_129__VceLevel_4_Reserved__SHIFT 0x0
+#define DPM_TABLE_130__VceLevel_5_Frequency_MASK 0xffffffff
+#define DPM_TABLE_130__VceLevel_5_Frequency__SHIFT 0x0
+#define DPM_TABLE_131__VceLevel_5_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_131__VceLevel_5_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_131__VceLevel_5_Divider_MASK 0xff00
+#define DPM_TABLE_131__VceLevel_5_Divider__SHIFT 0x8
+#define DPM_TABLE_131__VceLevel_5_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_131__VceLevel_5_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_132__VceLevel_5_Reserved_MASK 0xffffffff
+#define DPM_TABLE_132__VceLevel_5_Reserved__SHIFT 0x0
+#define DPM_TABLE_133__VceLevel_6_Frequency_MASK 0xffffffff
+#define DPM_TABLE_133__VceLevel_6_Frequency__SHIFT 0x0
+#define DPM_TABLE_134__VceLevel_6_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_134__VceLevel_6_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_134__VceLevel_6_Divider_MASK 0xff00
+#define DPM_TABLE_134__VceLevel_6_Divider__SHIFT 0x8
+#define DPM_TABLE_134__VceLevel_6_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_134__VceLevel_6_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_135__VceLevel_6_Reserved_MASK 0xffffffff
+#define DPM_TABLE_135__VceLevel_6_Reserved__SHIFT 0x0
+#define DPM_TABLE_136__VceLevel_7_Frequency_MASK 0xffffffff
+#define DPM_TABLE_136__VceLevel_7_Frequency__SHIFT 0x0
+#define DPM_TABLE_137__VceLevel_7_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_137__VceLevel_7_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_137__VceLevel_7_Divider_MASK 0xff00
+#define DPM_TABLE_137__VceLevel_7_Divider__SHIFT 0x8
+#define DPM_TABLE_137__VceLevel_7_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_137__VceLevel_7_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_138__VceLevel_7_Reserved_MASK 0xffffffff
+#define DPM_TABLE_138__VceLevel_7_Reserved__SHIFT 0x0
+#define DPM_TABLE_139__AcpLevel_0_Frequency_MASK 0xffffffff
+#define DPM_TABLE_139__AcpLevel_0_Frequency__SHIFT 0x0
+#define DPM_TABLE_140__AcpLevel_0_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_140__AcpLevel_0_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_140__AcpLevel_0_Divider_MASK 0xff00
+#define DPM_TABLE_140__AcpLevel_0_Divider__SHIFT 0x8
+#define DPM_TABLE_140__AcpLevel_0_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_140__AcpLevel_0_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_141__AcpLevel_0_Reserved_MASK 0xffffffff
+#define DPM_TABLE_141__AcpLevel_0_Reserved__SHIFT 0x0
+#define DPM_TABLE_142__AcpLevel_1_Frequency_MASK 0xffffffff
+#define DPM_TABLE_142__AcpLevel_1_Frequency__SHIFT 0x0
+#define DPM_TABLE_143__AcpLevel_1_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_143__AcpLevel_1_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_143__AcpLevel_1_Divider_MASK 0xff00
+#define DPM_TABLE_143__AcpLevel_1_Divider__SHIFT 0x8
+#define DPM_TABLE_143__AcpLevel_1_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_143__AcpLevel_1_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_144__AcpLevel_1_Reserved_MASK 0xffffffff
+#define DPM_TABLE_144__AcpLevel_1_Reserved__SHIFT 0x0
+#define DPM_TABLE_145__AcpLevel_2_Frequency_MASK 0xffffffff
+#define DPM_TABLE_145__AcpLevel_2_Frequency__SHIFT 0x0
+#define DPM_TABLE_146__AcpLevel_2_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_146__AcpLevel_2_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_146__AcpLevel_2_Divider_MASK 0xff00
+#define DPM_TABLE_146__AcpLevel_2_Divider__SHIFT 0x8
+#define DPM_TABLE_146__AcpLevel_2_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_146__AcpLevel_2_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_147__AcpLevel_2_Reserved_MASK 0xffffffff
+#define DPM_TABLE_147__AcpLevel_2_Reserved__SHIFT 0x0
+#define DPM_TABLE_148__AcpLevel_3_Frequency_MASK 0xffffffff
+#define DPM_TABLE_148__AcpLevel_3_Frequency__SHIFT 0x0
+#define DPM_TABLE_149__AcpLevel_3_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_149__AcpLevel_3_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_149__AcpLevel_3_Divider_MASK 0xff00
+#define DPM_TABLE_149__AcpLevel_3_Divider__SHIFT 0x8
+#define DPM_TABLE_149__AcpLevel_3_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_149__AcpLevel_3_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_150__AcpLevel_3_Reserved_MASK 0xffffffff
+#define DPM_TABLE_150__AcpLevel_3_Reserved__SHIFT 0x0
+#define DPM_TABLE_151__AcpLevel_4_Frequency_MASK 0xffffffff
+#define DPM_TABLE_151__AcpLevel_4_Frequency__SHIFT 0x0
+#define DPM_TABLE_152__AcpLevel_4_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_152__AcpLevel_4_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_152__AcpLevel_4_Divider_MASK 0xff00
+#define DPM_TABLE_152__AcpLevel_4_Divider__SHIFT 0x8
+#define DPM_TABLE_152__AcpLevel_4_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_152__AcpLevel_4_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_153__AcpLevel_4_Reserved_MASK 0xffffffff
+#define DPM_TABLE_153__AcpLevel_4_Reserved__SHIFT 0x0
+#define DPM_TABLE_154__AcpLevel_5_Frequency_MASK 0xffffffff
+#define DPM_TABLE_154__AcpLevel_5_Frequency__SHIFT 0x0
+#define DPM_TABLE_155__AcpLevel_5_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_155__AcpLevel_5_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_155__AcpLevel_5_Divider_MASK 0xff00
+#define DPM_TABLE_155__AcpLevel_5_Divider__SHIFT 0x8
+#define DPM_TABLE_155__AcpLevel_5_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_155__AcpLevel_5_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_156__AcpLevel_5_Reserved_MASK 0xffffffff
+#define DPM_TABLE_156__AcpLevel_5_Reserved__SHIFT 0x0
+#define DPM_TABLE_157__AcpLevel_6_Frequency_MASK 0xffffffff
+#define DPM_TABLE_157__AcpLevel_6_Frequency__SHIFT 0x0
+#define DPM_TABLE_158__AcpLevel_6_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_158__AcpLevel_6_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_158__AcpLevel_6_Divider_MASK 0xff00
+#define DPM_TABLE_158__AcpLevel_6_Divider__SHIFT 0x8
+#define DPM_TABLE_158__AcpLevel_6_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_158__AcpLevel_6_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_159__AcpLevel_6_Reserved_MASK 0xffffffff
+#define DPM_TABLE_159__AcpLevel_6_Reserved__SHIFT 0x0
+#define DPM_TABLE_160__AcpLevel_7_Frequency_MASK 0xffffffff
+#define DPM_TABLE_160__AcpLevel_7_Frequency__SHIFT 0x0
+#define DPM_TABLE_161__AcpLevel_7_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_161__AcpLevel_7_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_161__AcpLevel_7_Divider_MASK 0xff00
+#define DPM_TABLE_161__AcpLevel_7_Divider__SHIFT 0x8
+#define DPM_TABLE_161__AcpLevel_7_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_161__AcpLevel_7_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_162__AcpLevel_7_Reserved_MASK 0xffffffff
+#define DPM_TABLE_162__AcpLevel_7_Reserved__SHIFT 0x0
+#define DPM_TABLE_163__SamuLevel_0_Frequency_MASK 0xffffffff
+#define DPM_TABLE_163__SamuLevel_0_Frequency__SHIFT 0x0
+#define DPM_TABLE_164__SamuLevel_0_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_164__SamuLevel_0_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_164__SamuLevel_0_Divider_MASK 0xff00
+#define DPM_TABLE_164__SamuLevel_0_Divider__SHIFT 0x8
+#define DPM_TABLE_164__SamuLevel_0_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_164__SamuLevel_0_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_165__SamuLevel_0_Reserved_MASK 0xffffffff
+#define DPM_TABLE_165__SamuLevel_0_Reserved__SHIFT 0x0
+#define DPM_TABLE_166__SamuLevel_1_Frequency_MASK 0xffffffff
+#define DPM_TABLE_166__SamuLevel_1_Frequency__SHIFT 0x0
+#define DPM_TABLE_167__SamuLevel_1_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_167__SamuLevel_1_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_167__SamuLevel_1_Divider_MASK 0xff00
+#define DPM_TABLE_167__SamuLevel_1_Divider__SHIFT 0x8
+#define DPM_TABLE_167__SamuLevel_1_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_167__SamuLevel_1_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_168__SamuLevel_1_Reserved_MASK 0xffffffff
+#define DPM_TABLE_168__SamuLevel_1_Reserved__SHIFT 0x0
+#define DPM_TABLE_169__SamuLevel_2_Frequency_MASK 0xffffffff
+#define DPM_TABLE_169__SamuLevel_2_Frequency__SHIFT 0x0
+#define DPM_TABLE_170__SamuLevel_2_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_170__SamuLevel_2_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_170__SamuLevel_2_Divider_MASK 0xff00
+#define DPM_TABLE_170__SamuLevel_2_Divider__SHIFT 0x8
+#define DPM_TABLE_170__SamuLevel_2_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_170__SamuLevel_2_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_171__SamuLevel_2_Reserved_MASK 0xffffffff
+#define DPM_TABLE_171__SamuLevel_2_Reserved__SHIFT 0x0
+#define DPM_TABLE_172__SamuLevel_3_Frequency_MASK 0xffffffff
+#define DPM_TABLE_172__SamuLevel_3_Frequency__SHIFT 0x0
+#define DPM_TABLE_173__SamuLevel_3_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_173__SamuLevel_3_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_173__SamuLevel_3_Divider_MASK 0xff00
+#define DPM_TABLE_173__SamuLevel_3_Divider__SHIFT 0x8
+#define DPM_TABLE_173__SamuLevel_3_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_173__SamuLevel_3_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_174__SamuLevel_3_Reserved_MASK 0xffffffff
+#define DPM_TABLE_174__SamuLevel_3_Reserved__SHIFT 0x0
+#define DPM_TABLE_175__SamuLevel_4_Frequency_MASK 0xffffffff
+#define DPM_TABLE_175__SamuLevel_4_Frequency__SHIFT 0x0
+#define DPM_TABLE_176__SamuLevel_4_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_176__SamuLevel_4_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_176__SamuLevel_4_Divider_MASK 0xff00
+#define DPM_TABLE_176__SamuLevel_4_Divider__SHIFT 0x8
+#define DPM_TABLE_176__SamuLevel_4_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_176__SamuLevel_4_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_177__SamuLevel_4_Reserved_MASK 0xffffffff
+#define DPM_TABLE_177__SamuLevel_4_Reserved__SHIFT 0x0
+#define DPM_TABLE_178__SamuLevel_5_Frequency_MASK 0xffffffff
+#define DPM_TABLE_178__SamuLevel_5_Frequency__SHIFT 0x0
+#define DPM_TABLE_179__SamuLevel_5_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_179__SamuLevel_5_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_179__SamuLevel_5_Divider_MASK 0xff00
+#define DPM_TABLE_179__SamuLevel_5_Divider__SHIFT 0x8
+#define DPM_TABLE_179__SamuLevel_5_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_179__SamuLevel_5_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_180__SamuLevel_5_Reserved_MASK 0xffffffff
+#define DPM_TABLE_180__SamuLevel_5_Reserved__SHIFT 0x0
+#define DPM_TABLE_181__SamuLevel_6_Frequency_MASK 0xffffffff
+#define DPM_TABLE_181__SamuLevel_6_Frequency__SHIFT 0x0
+#define DPM_TABLE_182__SamuLevel_6_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_182__SamuLevel_6_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_182__SamuLevel_6_Divider_MASK 0xff00
+#define DPM_TABLE_182__SamuLevel_6_Divider__SHIFT 0x8
+#define DPM_TABLE_182__SamuLevel_6_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_182__SamuLevel_6_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_183__SamuLevel_6_Reserved_MASK 0xffffffff
+#define DPM_TABLE_183__SamuLevel_6_Reserved__SHIFT 0x0
+#define DPM_TABLE_184__SamuLevel_7_Frequency_MASK 0xffffffff
+#define DPM_TABLE_184__SamuLevel_7_Frequency__SHIFT 0x0
+#define DPM_TABLE_185__SamuLevel_7_ClkBypassCntl_MASK 0xff
+#define DPM_TABLE_185__SamuLevel_7_ClkBypassCntl__SHIFT 0x0
+#define DPM_TABLE_185__SamuLevel_7_Divider_MASK 0xff00
+#define DPM_TABLE_185__SamuLevel_7_Divider__SHIFT 0x8
+#define DPM_TABLE_185__SamuLevel_7_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_185__SamuLevel_7_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_186__SamuLevel_7_Reserved_MASK 0xffffffff
+#define DPM_TABLE_186__SamuLevel_7_Reserved__SHIFT 0x0
+#define DPM_TABLE_187__SamuBootLevel_MASK 0xff
+#define DPM_TABLE_187__SamuBootLevel__SHIFT 0x0
+#define DPM_TABLE_187__AcpBootLevel_MASK 0xff00
+#define DPM_TABLE_187__AcpBootLevel__SHIFT 0x8
+#define DPM_TABLE_187__VceBootLevel_MASK 0xff0000
+#define DPM_TABLE_187__VceBootLevel__SHIFT 0x10
+#define DPM_TABLE_187__UvdBootLevel_MASK 0xff000000
+#define DPM_TABLE_187__UvdBootLevel__SHIFT 0x18
+#define DPM_TABLE_188__SAMUInterval_MASK 0xff
+#define DPM_TABLE_188__SAMUInterval__SHIFT 0x0
+#define DPM_TABLE_188__ACPInterval_MASK 0xff00
+#define DPM_TABLE_188__ACPInterval__SHIFT 0x8
+#define DPM_TABLE_188__VCEInterval_MASK 0xff0000
+#define DPM_TABLE_188__VCEInterval__SHIFT 0x10
+#define DPM_TABLE_188__UVDInterval_MASK 0xff000000
+#define DPM_TABLE_188__UVDInterval__SHIFT 0x18
+#define DPM_TABLE_189__GraphicsVoltageChangeEnable_MASK 0xff
+#define DPM_TABLE_189__GraphicsVoltageChangeEnable__SHIFT 0x0
+#define DPM_TABLE_189__GraphicsThermThrottleEnable_MASK 0xff00
+#define DPM_TABLE_189__GraphicsThermThrottleEnable__SHIFT 0x8
+#define DPM_TABLE_189__GraphicsInterval_MASK 0xff0000
+#define DPM_TABLE_189__GraphicsInterval__SHIFT 0x10
+#define DPM_TABLE_189__GraphicsBootLevel_MASK 0xff000000
+#define DPM_TABLE_189__GraphicsBootLevel__SHIFT 0x18
+#define DPM_TABLE_190__FpsLowThreshold_MASK 0xffff
+#define DPM_TABLE_190__FpsLowThreshold__SHIFT 0x0
+#define DPM_TABLE_190__GraphicsClkSlowDivider_MASK 0xff0000
+#define DPM_TABLE_190__GraphicsClkSlowDivider__SHIFT 0x10
+#define DPM_TABLE_190__GraphicsClkSlowEnable_MASK 0xff000000
+#define DPM_TABLE_190__GraphicsClkSlowEnable__SHIFT 0x18
+#define DPM_TABLE_191__DisplayCac_MASK 0xffffffff
+#define DPM_TABLE_191__DisplayCac__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_4__HandshakeDisables_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_4__HandshakeDisables__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_5__DisplayPhy4Config_MASK 0xff
+#define SOFT_REGISTERS_TABLE_5__DisplayPhy4Config__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_5__DisplayPhy3Config_MASK 0xff00
+#define SOFT_REGISTERS_TABLE_5__DisplayPhy3Config__SHIFT 0x8
+#define SOFT_REGISTERS_TABLE_5__DisplayPhy2Config_MASK 0xff0000
+#define SOFT_REGISTERS_TABLE_5__DisplayPhy2Config__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_5__DisplayPhy1Config_MASK 0xff000000
+#define SOFT_REGISTERS_TABLE_5__DisplayPhy1Config__SHIFT 0x18
+#define SOFT_REGISTERS_TABLE_6__DisplayPhy8Config_MASK 0xff
+#define SOFT_REGISTERS_TABLE_6__DisplayPhy8Config__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_6__DisplayPhy7Config_MASK 0xff00
+#define SOFT_REGISTERS_TABLE_6__DisplayPhy7Config__SHIFT 0x8
+#define SOFT_REGISTERS_TABLE_6__DisplayPhy6Config_MASK 0xff0000
+#define SOFT_REGISTERS_TABLE_6__DisplayPhy6Config__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_6__DisplayPhy5Config_MASK 0xff000000
+#define SOFT_REGISTERS_TABLE_6__DisplayPhy5Config__SHIFT 0x18
+#define SOFT_REGISTERS_TABLE_7__AverageGraphicsActivity_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_7__AverageGraphicsActivity__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_8__AverageMemoryActivity_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_8__AverageMemoryActivity__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_9__AverageGioActivity_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_9__AverageGioActivity__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_10__PCIeDpmEnabledLevels_MASK 0xff
+#define SOFT_REGISTERS_TABLE_10__PCIeDpmEnabledLevels__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_10__LClkDpmEnabledLevels_MASK 0xff00
+#define SOFT_REGISTERS_TABLE_10__LClkDpmEnabledLevels__SHIFT 0x8
+#define SOFT_REGISTERS_TABLE_10__MClkDpmEnabledLevels_MASK 0xff0000
+#define SOFT_REGISTERS_TABLE_10__MClkDpmEnabledLevels__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_10__SClkDpmEnabledLevels_MASK 0xff000000
+#define SOFT_REGISTERS_TABLE_10__SClkDpmEnabledLevels__SHIFT 0x18
+#define SOFT_REGISTERS_TABLE_11__VCEDpmEnabledLevels_MASK 0xff
+#define SOFT_REGISTERS_TABLE_11__VCEDpmEnabledLevels__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_11__ACPDpmEnabledLevels_MASK 0xff00
+#define SOFT_REGISTERS_TABLE_11__ACPDpmEnabledLevels__SHIFT 0x8
+#define SOFT_REGISTERS_TABLE_11__SAMUDpmEnabledLevels_MASK 0xff0000
+#define SOFT_REGISTERS_TABLE_11__SAMUDpmEnabledLevels__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_11__UVDDpmEnabledLevels_MASK 0xff000000
+#define SOFT_REGISTERS_TABLE_11__UVDDpmEnabledLevels__SHIFT 0x18
+#define SOFT_REGISTERS_TABLE_12__Reserved_0_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_12__Reserved_0__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_13__Reserved_1_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_13__Reserved_1__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_14__Reserved_2_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_14__Reserved_2__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_15__Reserved_3_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_15__Reserved_3__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_16__Reserved_4_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_16__Reserved_4__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_17__Reserved_5_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_17__Reserved_5__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_18__Reserved_6_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_18__Reserved_6__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_19__Reserved_7_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_19__Reserved_7__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_20__Reserved_8_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_20__Reserved_8__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_21__Reserved_9_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_21__Reserved_9__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_0_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
+#define SMU_LCLK_DPM_STATE_0_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_0_CNTL_0__VID_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_0_CNTL_0__VID__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_0_CNTL_0__CLK_DIVIDER_MASK 0xff0000
+#define SMU_LCLK_DPM_STATE_0_CNTL_0__CLK_DIVIDER__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_0_CNTL_0__STATE_VALID_MASK 0xff000000
+#define SMU_LCLK_DPM_STATE_0_CNTL_0__STATE_VALID__SHIFT 0x18
+#define SMU_LCLK_DPM_STATE_1_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
+#define SMU_LCLK_DPM_STATE_1_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_1_CNTL_0__VID_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_1_CNTL_0__VID__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_1_CNTL_0__CLK_DIVIDER_MASK 0xff0000
+#define SMU_LCLK_DPM_STATE_1_CNTL_0__CLK_DIVIDER__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_1_CNTL_0__STATE_VALID_MASK 0xff000000
+#define SMU_LCLK_DPM_STATE_1_CNTL_0__STATE_VALID__SHIFT 0x18
+#define SMU_LCLK_DPM_STATE_2_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
+#define SMU_LCLK_DPM_STATE_2_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_2_CNTL_0__VID_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_2_CNTL_0__VID__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_2_CNTL_0__CLK_DIVIDER_MASK 0xff0000
+#define SMU_LCLK_DPM_STATE_2_CNTL_0__CLK_DIVIDER__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_2_CNTL_0__STATE_VALID_MASK 0xff000000
+#define SMU_LCLK_DPM_STATE_2_CNTL_0__STATE_VALID__SHIFT 0x18
+#define SMU_LCLK_DPM_STATE_3_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
+#define SMU_LCLK_DPM_STATE_3_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_3_CNTL_0__VID_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_3_CNTL_0__VID__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_3_CNTL_0__CLK_DIVIDER_MASK 0xff0000
+#define SMU_LCLK_DPM_STATE_3_CNTL_0__CLK_DIVIDER__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_3_CNTL_0__STATE_VALID_MASK 0xff000000
+#define SMU_LCLK_DPM_STATE_3_CNTL_0__STATE_VALID__SHIFT 0x18
+#define SMU_LCLK_DPM_STATE_4_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
+#define SMU_LCLK_DPM_STATE_4_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_4_CNTL_0__VID_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_4_CNTL_0__VID__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_4_CNTL_0__CLK_DIVIDER_MASK 0xff0000
+#define SMU_LCLK_DPM_STATE_4_CNTL_0__CLK_DIVIDER__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_4_CNTL_0__STATE_VALID_MASK 0xff000000
+#define SMU_LCLK_DPM_STATE_4_CNTL_0__STATE_VALID__SHIFT 0x18
+#define SMU_LCLK_DPM_STATE_5_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
+#define SMU_LCLK_DPM_STATE_5_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_5_CNTL_0__VID_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_5_CNTL_0__VID__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_5_CNTL_0__CLK_DIVIDER_MASK 0xff0000
+#define SMU_LCLK_DPM_STATE_5_CNTL_0__CLK_DIVIDER__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_5_CNTL_0__STATE_VALID_MASK 0xff000000
+#define SMU_LCLK_DPM_STATE_5_CNTL_0__STATE_VALID__SHIFT 0x18
+#define SMU_LCLK_DPM_STATE_6_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
+#define SMU_LCLK_DPM_STATE_6_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_6_CNTL_0__VID_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_6_CNTL_0__VID__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_6_CNTL_0__CLK_DIVIDER_MASK 0xff0000
+#define SMU_LCLK_DPM_STATE_6_CNTL_0__CLK_DIVIDER__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_6_CNTL_0__STATE_VALID_MASK 0xff000000
+#define SMU_LCLK_DPM_STATE_6_CNTL_0__STATE_VALID__SHIFT 0x18
+#define SMU_LCLK_DPM_STATE_7_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
+#define SMU_LCLK_DPM_STATE_7_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_7_CNTL_0__VID_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_7_CNTL_0__VID__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_7_CNTL_0__CLK_DIVIDER_MASK 0xff0000
+#define SMU_LCLK_DPM_STATE_7_CNTL_0__CLK_DIVIDER__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_7_CNTL_0__STATE_VALID_MASK 0xff000000
+#define SMU_LCLK_DPM_STATE_7_CNTL_0__STATE_VALID__SHIFT 0x18
+#define SMU_LCLK_DPM_STATE_0_CNTL_1__MIN_VDDNB_MASK 0xffffffff
+#define SMU_LCLK_DPM_STATE_0_CNTL_1__MIN_VDDNB__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_1_CNTL_1__MIN_VDDNB_MASK 0xffffffff
+#define SMU_LCLK_DPM_STATE_1_CNTL_1__MIN_VDDNB__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_2_CNTL_1__MIN_VDDNB_MASK 0xffffffff
+#define SMU_LCLK_DPM_STATE_2_CNTL_1__MIN_VDDNB__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_3_CNTL_1__MIN_VDDNB_MASK 0xffffffff
+#define SMU_LCLK_DPM_STATE_3_CNTL_1__MIN_VDDNB__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_4_CNTL_1__MIN_VDDNB_MASK 0xffffffff
+#define SMU_LCLK_DPM_STATE_4_CNTL_1__MIN_VDDNB__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_5_CNTL_1__MIN_VDDNB_MASK 0xffffffff
+#define SMU_LCLK_DPM_STATE_5_CNTL_1__MIN_VDDNB__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_6_CNTL_1__MIN_VDDNB_MASK 0xffffffff
+#define SMU_LCLK_DPM_STATE_6_CNTL_1__MIN_VDDNB__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_7_CNTL_1__MIN_VDDNB_MASK 0xffffffff
+#define SMU_LCLK_DPM_STATE_7_CNTL_1__MIN_VDDNB__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_0_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
+#define SMU_LCLK_DPM_STATE_0_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_0_CNTL_2__HYSTERESIS_UP_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_0_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_0_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
+#define SMU_LCLK_DPM_STATE_0_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_1_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
+#define SMU_LCLK_DPM_STATE_1_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_1_CNTL_2__HYSTERESIS_UP_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_1_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_1_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
+#define SMU_LCLK_DPM_STATE_1_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_2_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
+#define SMU_LCLK_DPM_STATE_2_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_2_CNTL_2__HYSTERESIS_UP_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_2_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_2_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
+#define SMU_LCLK_DPM_STATE_2_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_3_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
+#define SMU_LCLK_DPM_STATE_3_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_3_CNTL_2__HYSTERESIS_UP_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_3_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_3_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
+#define SMU_LCLK_DPM_STATE_3_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_4_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
+#define SMU_LCLK_DPM_STATE_4_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_4_CNTL_2__HYSTERESIS_UP_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_4_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_4_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
+#define SMU_LCLK_DPM_STATE_4_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_5_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
+#define SMU_LCLK_DPM_STATE_5_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_5_CNTL_2__HYSTERESIS_UP_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_5_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_5_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
+#define SMU_LCLK_DPM_STATE_5_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_6_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
+#define SMU_LCLK_DPM_STATE_6_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_6_CNTL_2__HYSTERESIS_UP_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_6_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_6_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
+#define SMU_LCLK_DPM_STATE_6_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_7_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
+#define SMU_LCLK_DPM_STATE_7_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_7_CNTL_2__HYSTERESIS_UP_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_7_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_7_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
+#define SMU_LCLK_DPM_STATE_7_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_0_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
+#define SMU_LCLK_DPM_STATE_0_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_1_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
+#define SMU_LCLK_DPM_STATE_1_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_2_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
+#define SMU_LCLK_DPM_STATE_2_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_3_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
+#define SMU_LCLK_DPM_STATE_3_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_4_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
+#define SMU_LCLK_DPM_STATE_4_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_5_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
+#define SMU_LCLK_DPM_STATE_5_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_6_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
+#define SMU_LCLK_DPM_STATE_6_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_7_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
+#define SMU_LCLK_DPM_STATE_7_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
+#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
+#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
+#define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
+#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
+#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
+#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
+#define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
+#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
+#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
+#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
+#define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
+#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
+#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
+#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
+#define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
+#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
+#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
+#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
+#define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
+#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
+#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
+#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
+#define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
+#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
+#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
+#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
+#define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
+#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
+#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
+#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
+#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
+#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
+#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
+#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
+#define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
+#define GIO_PID_CONTROLLER_CNTL_0__K_I_MASK 0xffffffff
+#define GIO_PID_CONTROLLER_CNTL_0__K_I__SHIFT 0x0
+#define GIO_PID_CONTROLLER_CNTL_1__LF_WINDUP_UPPER_LIM_MASK 0xffffffff
+#define GIO_PID_CONTROLLER_CNTL_1__LF_WINDUP_UPPER_LIM__SHIFT 0x0
+#define GIO_PID_CONTROLLER_CNTL_2__LF_WINDUP_LOWER_LIM_MASK 0xffffffff
+#define GIO_PID_CONTROLLER_CNTL_2__LF_WINDUP_LOWER_LIM__SHIFT 0x0
+#define GIO_PID_CONTROLLER_CNTL_3__STATE_PRECISION_MASK 0xffffffff
+#define GIO_PID_CONTROLLER_CNTL_3__STATE_PRECISION__SHIFT 0x0
+#define GIO_PID_CONTROLLER_CNTL_4__LF_PRECISION_MASK 0xffffffff
+#define GIO_PID_CONTROLLER_CNTL_4__LF_PRECISION__SHIFT 0x0
+#define GIO_PID_CONTROLLER_CNTL_5__LF_OFFSET_MASK 0xffffffff
+#define GIO_PID_CONTROLLER_CNTL_5__LF_OFFSET__SHIFT 0x0
+#define GIO_PID_CONTROLLER_CNTL_6__MAX_STATE_MASK 0xffffffff
+#define GIO_PID_CONTROLLER_CNTL_6__MAX_STATE__SHIFT 0x0
+#define GIO_PID_CONTROLLER_CNTL_7__MAX_LF_FRACTION_MASK 0xffffffff
+#define GIO_PID_CONTROLLER_CNTL_7__MAX_LF_FRACTION__SHIFT 0x0
+#define GIO_PID_CONTROLLER_CNTL_8__STATE_SHIFT_MASK 0xffffffff
+#define GIO_PID_CONTROLLER_CNTL_8__STATE_SHIFT__SHIFT 0x0
+#define SMU_LCLK_DPM_LEVEL_COUNT__LCLK_DPM_LEVEL_COUNT_MASK 0xffffffff
+#define SMU_LCLK_DPM_LEVEL_COUNT__LCLK_DPM_LEVEL_COUNT__SHIFT 0x0
+#define SMU_LCLK_DPM_CNTL__RESERVED_MASK 0xff
+#define SMU_LCLK_DPM_CNTL__RESERVED__SHIFT 0x0
+#define SMU_LCLK_DPM_CNTL__LCLK_DPM_BOOT_STATE_MASK 0xff00
+#define SMU_LCLK_DPM_CNTL__LCLK_DPM_BOOT_STATE__SHIFT 0x8
+#define SMU_LCLK_DPM_CNTL__VOLTAGE_CHG_EN_MASK 0xff0000
+#define SMU_LCLK_DPM_CNTL__VOLTAGE_CHG_EN__SHIFT 0x10
+#define SMU_LCLK_DPM_CNTL__LCLK_DPM_EN_MASK 0xff000000
+#define SMU_LCLK_DPM_CNTL__LCLK_DPM_EN__SHIFT 0x18
+#define SMU_LCLK_DPM_CURRENT_AND_TARGET_STATE__CURRENT_STATE_MASK 0xff
+#define SMU_LCLK_DPM_CURRENT_AND_TARGET_STATE__CURRENT_STATE__SHIFT 0x0
+#define SMU_LCLK_DPM_CURRENT_AND_TARGET_STATE__TARGET_STATE_MASK 0xff00
+#define SMU_LCLK_DPM_CURRENT_AND_TARGET_STATE__TARGET_STATE__SHIFT 0x8
+#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__LCLK_THERMAL_THROTTLING_EN_MASK 0xff
+#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__LCLK_THERMAL_THROTTLING_EN__SHIFT 0x0
+#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__TEMPERATURE_SEL_MASK 0xff00
+#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__TEMPERATURE_SEL__SHIFT 0x8
+#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__LCLK_TT_MODE_MASK 0xff0000
+#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__LCLK_TT_MODE__SHIFT 0x10
+#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__TT_HTC_ACTIVE_MASK 0xff000000
+#define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__TT_HTC_ACTIVE__SHIFT 0x18
+#define SMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS__LOW_THRESHOLD_MASK 0xffff
+#define SMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS__LOW_THRESHOLD__SHIFT 0x0
+#define SMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS__HIGH_THRESHOLD_MASK 0xffff0000
+#define SMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS__HIGH_THRESHOLD__SHIFT 0x10
+#define PM_FUSES_1__BapmPstateVid_3_MASK 0xff
+#define PM_FUSES_1__BapmPstateVid_3__SHIFT 0x0
+#define PM_FUSES_1__BapmPstateVid_2_MASK 0xff00
+#define PM_FUSES_1__BapmPstateVid_2__SHIFT 0x8
+#define PM_FUSES_1__BapmPstateVid_1_MASK 0xff0000
+#define PM_FUSES_1__BapmPstateVid_1__SHIFT 0x10
+#define PM_FUSES_1__BapmPstateVid_0_MASK 0xff000000
+#define PM_FUSES_1__BapmPstateVid_0__SHIFT 0x18
+#define PM_FUSES_2__BapmPstateVid_7_MASK 0xff
+#define PM_FUSES_2__BapmPstateVid_7__SHIFT 0x0
+#define PM_FUSES_2__BapmPstateVid_6_MASK 0xff00
+#define PM_FUSES_2__BapmPstateVid_6__SHIFT 0x8
+#define PM_FUSES_2__BapmPstateVid_5_MASK 0xff0000
+#define PM_FUSES_2__BapmPstateVid_5__SHIFT 0x10
+#define PM_FUSES_2__BapmPstateVid_4_MASK 0xff000000
+#define PM_FUSES_2__BapmPstateVid_4__SHIFT 0x18
+#define PM_FUSES_3__BapmVddNbVidHiSidd_3_MASK 0xff
+#define PM_FUSES_3__BapmVddNbVidHiSidd_3__SHIFT 0x0
+#define PM_FUSES_3__BapmVddNbVidHiSidd_2_MASK 0xff00
+#define PM_FUSES_3__BapmVddNbVidHiSidd_2__SHIFT 0x8
+#define PM_FUSES_3__BapmVddNbVidHiSidd_1_MASK 0xff0000
+#define PM_FUSES_3__BapmVddNbVidHiSidd_1__SHIFT 0x10
+#define PM_FUSES_3__BapmVddNbVidHiSidd_0_MASK 0xff000000
+#define PM_FUSES_3__BapmVddNbVidHiSidd_0__SHIFT 0x18
+#define PM_FUSES_4__BapmVddNbVidLoSidd_2_MASK 0xff
+#define PM_FUSES_4__BapmVddNbVidLoSidd_2__SHIFT 0x0
+#define PM_FUSES_4__BapmVddNbVidLoSidd_1_MASK 0xff00
+#define PM_FUSES_4__BapmVddNbVidLoSidd_1__SHIFT 0x8
+#define PM_FUSES_4__BapmVddNbVidLoSidd_0_MASK 0xff0000
+#define PM_FUSES_4__BapmVddNbVidLoSidd_0__SHIFT 0x10
+#define PM_FUSES_4__BapmVddNbVidHiSidd_4_MASK 0xff000000
+#define PM_FUSES_4__BapmVddNbVidHiSidd_4__SHIFT 0x18
+#define PM_FUSES_5__CpuIdModel_MASK 0xff
+#define PM_FUSES_5__CpuIdModel__SHIFT 0x0
+#define PM_FUSES_5__SviLoadLineEn_MASK 0xff00
+#define PM_FUSES_5__SviLoadLineEn__SHIFT 0x8
+#define PM_FUSES_5__BapmVddNbVidLoSidd_4_MASK 0xff0000
+#define PM_FUSES_5__BapmVddNbVidLoSidd_4__SHIFT 0x10
+#define PM_FUSES_5__BapmVddNbVidLoSidd_3_MASK 0xff000000
+#define PM_FUSES_5__BapmVddNbVidLoSidd_3__SHIFT 0x18
+#define PM_FUSES_6__SviLoadLineTrimVddNb_MASK 0xff
+#define PM_FUSES_6__SviLoadLineTrimVddNb__SHIFT 0x0
+#define PM_FUSES_6__SviLoadLineTrimVdd_MASK 0xff00
+#define PM_FUSES_6__SviLoadLineTrimVdd__SHIFT 0x8
+#define PM_FUSES_6__SviLoadLineVddNb_MASK 0xff0000
+#define PM_FUSES_6__SviLoadLineVddNb__SHIFT 0x10
+#define PM_FUSES_6__SviLoadLineVdd_MASK 0xff000000
+#define PM_FUSES_6__SviLoadLineVdd__SHIFT 0x18
+#define PM_FUSES_7__BAPMTI_TjOffset_0_MASK 0xffff
+#define PM_FUSES_7__BAPMTI_TjOffset_0__SHIFT 0x0
+#define PM_FUSES_7__SviLoadLineOffsetVddNb_MASK 0xff0000
+#define PM_FUSES_7__SviLoadLineOffsetVddNb__SHIFT 0x10
+#define PM_FUSES_7__SviLoadLineOffsetVdd_MASK 0xff000000
+#define PM_FUSES_7__SviLoadLineOffsetVdd__SHIFT 0x18
+#define PM_FUSES_8__BAPMTI_TjOffset_2_MASK 0xffff
+#define PM_FUSES_8__BAPMTI_TjOffset_2__SHIFT 0x0
+#define PM_FUSES_8__BAPMTI_TjOffset_1_MASK 0xffff0000
+#define PM_FUSES_8__BAPMTI_TjOffset_1__SHIFT 0x10
+#define PM_FUSES_9__BAPMTI_TjHyst_1_MASK 0xffff
+#define PM_FUSES_9__BAPMTI_TjHyst_1__SHIFT 0x0
+#define PM_FUSES_9__BAPMTI_TjHyst_0_MASK 0xffff0000
+#define PM_FUSES_9__BAPMTI_TjHyst_0__SHIFT 0x10
+#define PM_FUSES_10__BAPMTI_TjMax_1_MASK 0xff
+#define PM_FUSES_10__BAPMTI_TjMax_1__SHIFT 0x0
+#define PM_FUSES_10__BAPMTI_TjMax_0_MASK 0xff00
+#define PM_FUSES_10__BAPMTI_TjMax_0__SHIFT 0x8
+#define PM_FUSES_10__BAPMTI_GpuTjHyst_MASK 0xffff0000
+#define PM_FUSES_10__BAPMTI_GpuTjHyst__SHIFT 0x10
+#define PM_FUSES_11__LhtcTmpLmt_MASK 0xff
+#define PM_FUSES_11__LhtcTmpLmt__SHIFT 0x0
+#define PM_FUSES_11__LhtcPstateLimit_MASK 0xff00
+#define PM_FUSES_11__LhtcPstateLimit__SHIFT 0x8
+#define PM_FUSES_11__LhtcHystLmt_MASK 0xff0000
+#define PM_FUSES_11__LhtcHystLmt__SHIFT 0x10
+#define PM_FUSES_11__BAPMTI_GpuTjMax_MASK 0xff000000
+#define PM_FUSES_11__BAPMTI_GpuTjMax__SHIFT 0x18
+#define PM_FUSES_12__MaxPwrCpu_1_MASK 0xff
+#define PM_FUSES_12__MaxPwrCpu_1__SHIFT 0x0
+#define PM_FUSES_12__MaxPwrCpu_0_MASK 0xff00
+#define PM_FUSES_12__MaxPwrCpu_0__SHIFT 0x8
+#define PM_FUSES_12__NomPwrCpu_1_MASK 0xff0000
+#define PM_FUSES_12__NomPwrCpu_1__SHIFT 0x10
+#define PM_FUSES_12__NomPwrCpu_0_MASK 0xff000000
+#define PM_FUSES_12__NomPwrCpu_0__SHIFT 0x18
+#define PM_FUSES_13__NomPwrGpu_MASK 0xffff
+#define PM_FUSES_13__NomPwrGpu__SHIFT 0x0
+#define PM_FUSES_13__MidPwrCpu_1_MASK 0xff0000
+#define PM_FUSES_13__MidPwrCpu_1__SHIFT 0x10
+#define PM_FUSES_13__MidPwrCpu_0_MASK 0xff000000
+#define PM_FUSES_13__MidPwrCpu_0__SHIFT 0x18
+#define PM_FUSES_14__MinPwrGpu_MASK 0xffff
+#define PM_FUSES_14__MinPwrGpu__SHIFT 0x0
+#define PM_FUSES_14__MaxPwrGpu_MASK 0xffff0000
+#define PM_FUSES_14__MaxPwrGpu__SHIFT 0x10
+#define PM_FUSES_15__PCIe3PhyOffset_MASK 0xff
+#define PM_FUSES_15__PCIe3PhyOffset__SHIFT 0x0
+#define PM_FUSES_15__PCIe2PhyOffset_MASK 0xff00
+#define PM_FUSES_15__PCIe2PhyOffset__SHIFT 0x8
+#define PM_FUSES_15__PCIe1PhyOffset_MASK 0xff0000
+#define PM_FUSES_15__PCIe1PhyOffset__SHIFT 0x10
+#define PM_FUSES_15__MidPwrTempHyst_MASK 0xff000000
+#define PM_FUSES_15__MidPwrTempHyst__SHIFT 0x18
+#define PM_FUSES_16__TDC_VDD_PkgLimit_MASK 0xffff
+#define PM_FUSES_16__TDC_VDD_PkgLimit__SHIFT 0x0
+#define PM_FUSES_16__DCE2PhyOffset_MASK 0xff0000
+#define PM_FUSES_16__DCE2PhyOffset__SHIFT 0x10
+#define PM_FUSES_16__DCE1PhyOffset_MASK 0xff000000
+#define PM_FUSES_16__DCE1PhyOffset__SHIFT 0x18
+#define PM_FUSES_17__TDC_VDDNB_ThrottleReleaseLimitPerc_MASK 0xff
+#define PM_FUSES_17__TDC_VDDNB_ThrottleReleaseLimitPerc__SHIFT 0x0
+#define PM_FUSES_17__TDC_VDD_ThrottleReleaseLimitPerc_MASK 0xff00
+#define PM_FUSES_17__TDC_VDD_ThrottleReleaseLimitPerc__SHIFT 0x8
+#define PM_FUSES_17__TDC_VDDNB_PkgLimit_MASK 0xffff0000
+#define PM_FUSES_17__TDC_VDDNB_PkgLimit__SHIFT 0x10
+#define PM_FUSES_18__TdcWaterfallCtl_MASK 0xff
+#define PM_FUSES_18__TdcWaterfallCtl__SHIFT 0x0
+#define PM_FUSES_18__TdpAgeRate_MASK 0xff00
+#define PM_FUSES_18__TdpAgeRate__SHIFT 0x8
+#define PM_FUSES_18__TdpAgeValue_MASK 0xff0000
+#define PM_FUSES_18__TdpAgeValue__SHIFT 0x10
+#define PM_FUSES_18__TDC_MAWt_MASK 0xff000000
+#define PM_FUSES_18__TDC_MAWt__SHIFT 0x18
+#define PM_FUSES_19__BapmLhtcCap_MASK 0xff
+#define PM_FUSES_19__BapmLhtcCap__SHIFT 0x0
+#define PM_FUSES_19__BapmFuseOverride_MASK 0xff00
+#define PM_FUSES_19__BapmFuseOverride__SHIFT 0x8
+#define PM_FUSES_19__SmuCoolingIndex_MASK 0xff0000
+#define PM_FUSES_19__SmuCoolingIndex__SHIFT 0x10
+#define PM_FUSES_19__SmuSocIndex_MASK 0xff000000
+#define PM_FUSES_19__SmuSocIndex__SHIFT 0x18
+#define PM_FUSES_20__SamClkDid_3_MASK 0xff
+#define PM_FUSES_20__SamClkDid_3__SHIFT 0x0
+#define PM_FUSES_20__SamClkDid_2_MASK 0xff00
+#define PM_FUSES_20__SamClkDid_2__SHIFT 0x8
+#define PM_FUSES_20__SamClkDid_1_MASK 0xff0000
+#define PM_FUSES_20__SamClkDid_1__SHIFT 0x10
+#define PM_FUSES_20__SamClkDid_0_MASK 0xff000000
+#define PM_FUSES_20__SamClkDid_0__SHIFT 0x18
+#define PM_FUSES_21__AmbientTempBase_MASK 0xff
+#define PM_FUSES_21__AmbientTempBase__SHIFT 0x0
+#define PM_FUSES_21__LPMLTemperatureMax_MASK 0xff00
+#define PM_FUSES_21__LPMLTemperatureMax__SHIFT 0x8
+#define PM_FUSES_21__LPMLTemperatureMin_MASK 0xff0000
+#define PM_FUSES_21__LPMLTemperatureMin__SHIFT 0x10
+#define PM_FUSES_21__SamClkDid_4_MASK 0xff000000
+#define PM_FUSES_21__SamClkDid_4__SHIFT 0x18
+#define PM_FUSES_22__LPMLTemperatureScaler_3_MASK 0xff
+#define PM_FUSES_22__LPMLTemperatureScaler_3__SHIFT 0x0
+#define PM_FUSES_22__LPMLTemperatureScaler_2_MASK 0xff00
+#define PM_FUSES_22__LPMLTemperatureScaler_2__SHIFT 0x8
+#define PM_FUSES_22__LPMLTemperatureScaler_1_MASK 0xff0000
+#define PM_FUSES_22__LPMLTemperatureScaler_1__SHIFT 0x10
+#define PM_FUSES_22__LPMLTemperatureScaler_0_MASK 0xff000000
+#define PM_FUSES_22__LPMLTemperatureScaler_0__SHIFT 0x18
+#define PM_FUSES_23__LPMLTemperatureScaler_7_MASK 0xff
+#define PM_FUSES_23__LPMLTemperatureScaler_7__SHIFT 0x0
+#define PM_FUSES_23__LPMLTemperatureScaler_6_MASK 0xff00
+#define PM_FUSES_23__LPMLTemperatureScaler_6__SHIFT 0x8
+#define PM_FUSES_23__LPMLTemperatureScaler_5_MASK 0xff0000
+#define PM_FUSES_23__LPMLTemperatureScaler_5__SHIFT 0x10
+#define PM_FUSES_23__LPMLTemperatureScaler_4_MASK 0xff000000
+#define PM_FUSES_23__LPMLTemperatureScaler_4__SHIFT 0x18
+#define PM_FUSES_24__LPMLTemperatureScaler_11_MASK 0xff
+#define PM_FUSES_24__LPMLTemperatureScaler_11__SHIFT 0x0
+#define PM_FUSES_24__LPMLTemperatureScaler_10_MASK 0xff00
+#define PM_FUSES_24__LPMLTemperatureScaler_10__SHIFT 0x8
+#define PM_FUSES_24__LPMLTemperatureScaler_9_MASK 0xff0000
+#define PM_FUSES_24__LPMLTemperatureScaler_9__SHIFT 0x10
+#define PM_FUSES_24__LPMLTemperatureScaler_8_MASK 0xff000000
+#define PM_FUSES_24__LPMLTemperatureScaler_8__SHIFT 0x18
+#define PM_FUSES_25__LPMLTemperatureScaler_15_MASK 0xff
+#define PM_FUSES_25__LPMLTemperatureScaler_15__SHIFT 0x0
+#define PM_FUSES_25__LPMLTemperatureScaler_14_MASK 0xff00
+#define PM_FUSES_25__LPMLTemperatureScaler_14__SHIFT 0x8
+#define PM_FUSES_25__LPMLTemperatureScaler_13_MASK 0xff0000
+#define PM_FUSES_25__LPMLTemperatureScaler_13__SHIFT 0x10
+#define PM_FUSES_25__LPMLTemperatureScaler_12_MASK 0xff000000
+#define PM_FUSES_25__LPMLTemperatureScaler_12__SHIFT 0x18
+#define PM_FUSES_26__GnbLPML_3_MASK 0xff
+#define PM_FUSES_26__GnbLPML_3__SHIFT 0x0
+#define PM_FUSES_26__GnbLPML_2_MASK 0xff00
+#define PM_FUSES_26__GnbLPML_2__SHIFT 0x8
+#define PM_FUSES_26__GnbLPML_1_MASK 0xff0000
+#define PM_FUSES_26__GnbLPML_1__SHIFT 0x10
+#define PM_FUSES_26__GnbLPML_0_MASK 0xff000000
+#define PM_FUSES_26__GnbLPML_0__SHIFT 0x18
+#define PM_FUSES_27__GnbLPML_7_MASK 0xff
+#define PM_FUSES_27__GnbLPML_7__SHIFT 0x0
+#define PM_FUSES_27__GnbLPML_6_MASK 0xff00
+#define PM_FUSES_27__GnbLPML_6__SHIFT 0x8
+#define PM_FUSES_27__GnbLPML_5_MASK 0xff0000
+#define PM_FUSES_27__GnbLPML_5__SHIFT 0x10
+#define PM_FUSES_27__GnbLPML_4_MASK 0xff000000
+#define PM_FUSES_27__GnbLPML_4__SHIFT 0x18
+#define PM_FUSES_28__GnbLPML_11_MASK 0xff
+#define PM_FUSES_28__GnbLPML_11__SHIFT 0x0
+#define PM_FUSES_28__GnbLPML_10_MASK 0xff00
+#define PM_FUSES_28__GnbLPML_10__SHIFT 0x8
+#define PM_FUSES_28__GnbLPML_9_MASK 0xff0000
+#define PM_FUSES_28__GnbLPML_9__SHIFT 0x10
+#define PM_FUSES_28__GnbLPML_8_MASK 0xff000000
+#define PM_FUSES_28__GnbLPML_8__SHIFT 0x18
+#define PM_FUSES_29__GnbLPML_15_MASK 0xff
+#define PM_FUSES_29__GnbLPML_15__SHIFT 0x0
+#define PM_FUSES_29__GnbLPML_14_MASK 0xff00
+#define PM_FUSES_29__GnbLPML_14__SHIFT 0x8
+#define PM_FUSES_29__GnbLPML_13_MASK 0xff0000
+#define PM_FUSES_29__GnbLPML_13__SHIFT 0x10
+#define PM_FUSES_29__GnbLPML_12_MASK 0xff000000
+#define PM_FUSES_29__GnbLPML_12__SHIFT 0x18
+#define PM_FUSES_30__NbVid_3_MASK 0xff
+#define PM_FUSES_30__NbVid_3__SHIFT 0x0
+#define PM_FUSES_30__NbVid_2_MASK 0xff00
+#define PM_FUSES_30__NbVid_2__SHIFT 0x8
+#define PM_FUSES_30__NbVid_1_MASK 0xff0000
+#define PM_FUSES_30__NbVid_1__SHIFT 0x10
+#define PM_FUSES_30__NbVid_0_MASK 0xff000000
+#define PM_FUSES_30__NbVid_0__SHIFT 0x18
+#define PM_FUSES_31__CpuVid_3_MASK 0xff
+#define PM_FUSES_31__CpuVid_3__SHIFT 0x0
+#define PM_FUSES_31__CpuVid_2_MASK 0xff00
+#define PM_FUSES_31__CpuVid_2__SHIFT 0x8
+#define PM_FUSES_31__CpuVid_1_MASK 0xff0000
+#define PM_FUSES_31__CpuVid_1__SHIFT 0x10
+#define PM_FUSES_31__CpuVid_0_MASK 0xff000000
+#define PM_FUSES_31__CpuVid_0__SHIFT 0x18
+#define PM_FUSES_32__CpuVid_7_MASK 0xff
+#define PM_FUSES_32__CpuVid_7__SHIFT 0x0
+#define PM_FUSES_32__CpuVid_6_MASK 0xff00
+#define PM_FUSES_32__CpuVid_6__SHIFT 0x8
+#define PM_FUSES_32__CpuVid_5_MASK 0xff0000
+#define PM_FUSES_32__CpuVid_5__SHIFT 0x10
+#define PM_FUSES_32__CpuVid_4_MASK 0xff000000
+#define PM_FUSES_32__CpuVid_4__SHIFT 0x18
+#define PM_FUSES_33__Tdp2Watt_MASK 0xffff
+#define PM_FUSES_33__Tdp2Watt__SHIFT 0x0
+#define PM_FUSES_33__GnbLPMLMinVid_MASK 0xff0000
+#define PM_FUSES_33__GnbLPMLMinVid__SHIFT 0x10
+#define PM_FUSES_33__GnbLPMLMaxVid_MASK 0xff000000
+#define PM_FUSES_33__GnbLPMLMaxVid__SHIFT 0x18
+#define PM_FUSES_34__Lpml_3_MASK 0xff
+#define PM_FUSES_34__Lpml_3__SHIFT 0x0
+#define PM_FUSES_34__Lpml_2_MASK 0xff00
+#define PM_FUSES_34__Lpml_2__SHIFT 0x8
+#define PM_FUSES_34__Lpml_1_MASK 0xff0000
+#define PM_FUSES_34__Lpml_1__SHIFT 0x10
+#define PM_FUSES_34__Lpml_0_MASK 0xff000000
+#define PM_FUSES_34__Lpml_0__SHIFT 0x18
+#define PM_FUSES_35__Lpml_7_MASK 0xff
+#define PM_FUSES_35__Lpml_7__SHIFT 0x0
+#define PM_FUSES_35__Lpml_6_MASK 0xff00
+#define PM_FUSES_35__Lpml_6__SHIFT 0x8
+#define PM_FUSES_35__Lpml_5_MASK 0xff0000
+#define PM_FUSES_35__Lpml_5__SHIFT 0x10
+#define PM_FUSES_35__Lpml_4_MASK 0xff000000
+#define PM_FUSES_35__Lpml_4__SHIFT 0x18
+#define PM_FUSES_36__Lpmv_3_MASK 0xff
+#define PM_FUSES_36__Lpmv_3__SHIFT 0x0
+#define PM_FUSES_36__Lpmv_2_MASK 0xff00
+#define PM_FUSES_36__Lpmv_2__SHIFT 0x8
+#define PM_FUSES_36__Lpmv_1_MASK 0xff0000
+#define PM_FUSES_36__Lpmv_1__SHIFT 0x10
+#define PM_FUSES_36__Lpmv_0_MASK 0xff000000
+#define PM_FUSES_36__Lpmv_0__SHIFT 0x18
+#define PM_FUSES_37__Lpmv_7_MASK 0xff
+#define PM_FUSES_37__Lpmv_7__SHIFT 0x0
+#define PM_FUSES_37__Lpmv_6_MASK 0xff00
+#define PM_FUSES_37__Lpmv_6__SHIFT 0x8
+#define PM_FUSES_37__Lpmv_5_MASK 0xff0000
+#define PM_FUSES_37__Lpmv_5__SHIFT 0x10
+#define PM_FUSES_37__Lpmv_4_MASK 0xff000000
+#define PM_FUSES_37__Lpmv_4__SHIFT 0x18
+#define PM_FUSES_38__EClkDid_3_MASK 0xff
+#define PM_FUSES_38__EClkDid_3__SHIFT 0x0
+#define PM_FUSES_38__EClkDid_2_MASK 0xff00
+#define PM_FUSES_38__EClkDid_2__SHIFT 0x8
+#define PM_FUSES_38__EClkDid_1_MASK 0xff0000
+#define PM_FUSES_38__EClkDid_1__SHIFT 0x10
+#define PM_FUSES_38__EClkDid_0_MASK 0xff000000
+#define PM_FUSES_38__EClkDid_0__SHIFT 0x18
+#define PM_FUSES_39__CoreDis_MASK 0xff
+#define PM_FUSES_39__CoreDis__SHIFT 0x0
+#define PM_FUSES_39__C6CstatePower_MASK 0xff00
+#define PM_FUSES_39__C6CstatePower__SHIFT 0x8
+#define PM_FUSES_39__BoostLock_MASK 0xff0000
+#define PM_FUSES_39__BoostLock__SHIFT 0x10
+#define PM_FUSES_39__EClkDid_4_MASK 0xff000000
+#define PM_FUSES_39__EClkDid_4__SHIFT 0x18
+#define PM_FUSES_40__BapmVddNbBaseLeakageLoSidd_MASK 0xffff
+#define PM_FUSES_40__BapmVddNbBaseLeakageLoSidd__SHIFT 0x0
+#define PM_FUSES_40__BapmVddNbBaseLeakageHiSidd_MASK 0xffff0000
+#define PM_FUSES_40__BapmVddNbBaseLeakageHiSidd__SHIFT 0x10
+#define PM_FUSES_41__VddNbVid_3_MASK 0xff
+#define PM_FUSES_41__VddNbVid_3__SHIFT 0x0
+#define PM_FUSES_41__VddNbVid_2_MASK 0xff00
+#define PM_FUSES_41__VddNbVid_2__SHIFT 0x8
+#define PM_FUSES_41__VddNbVid_1_MASK 0xff0000
+#define PM_FUSES_41__VddNbVid_1__SHIFT 0x10
+#define PM_FUSES_41__VddNbVid_0_MASK 0xff000000
+#define PM_FUSES_41__VddNbVid_0__SHIFT 0x18
+#define PM_FUSES_42__VddNbVidOffset_2_MASK 0xff
+#define PM_FUSES_42__VddNbVidOffset_2__SHIFT 0x0
+#define PM_FUSES_42__VddNbVidOffset_1_MASK 0xff00
+#define PM_FUSES_42__VddNbVidOffset_1__SHIFT 0x8
+#define PM_FUSES_42__VddNbVidOffset_0_MASK 0xff0000
+#define PM_FUSES_42__VddNbVidOffset_0__SHIFT 0x10
+#define PM_FUSES_42__VddNbVid_4_MASK 0xff000000
+#define PM_FUSES_42__VddNbVid_4__SHIFT 0x18
+#define PM_FUSES_43__BapmDisable_MASK 0xff
+#define PM_FUSES_43__BapmDisable__SHIFT 0x0
+#define PM_FUSES_43__CoreTdpLimit0_MASK 0xff00
+#define PM_FUSES_43__CoreTdpLimit0__SHIFT 0x8
+#define PM_FUSES_43__VddNbVidOffset_4_MASK 0xff0000
+#define PM_FUSES_43__VddNbVidOffset_4__SHIFT 0x10
+#define PM_FUSES_43__VddNbVidOffset_3_MASK 0xff000000
+#define PM_FUSES_43__VddNbVidOffset_3__SHIFT 0x18
+#define PM_FUSES_44__LpmlL2_3_MASK 0xff
+#define PM_FUSES_44__LpmlL2_3__SHIFT 0x0
+#define PM_FUSES_44__LpmlL2_2_MASK 0xff00
+#define PM_FUSES_44__LpmlL2_2__SHIFT 0x8
+#define PM_FUSES_44__LpmlL2_1_MASK 0xff0000
+#define PM_FUSES_44__LpmlL2_1__SHIFT 0x10
+#define PM_FUSES_44__LpmlL2_0_MASK 0xff000000
+#define PM_FUSES_44__LpmlL2_0__SHIFT 0x18
+#define PM_FUSES_45__LpmlL2_7_MASK 0xff
+#define PM_FUSES_45__LpmlL2_7__SHIFT 0x0
+#define PM_FUSES_45__LpmlL2_6_MASK 0xff00
+#define PM_FUSES_45__LpmlL2_6__SHIFT 0x8
+#define PM_FUSES_45__LpmlL2_5_MASK 0xff0000
+#define PM_FUSES_45__LpmlL2_5__SHIFT 0x10
+#define PM_FUSES_45__LpmlL2_4_MASK 0xff000000
+#define PM_FUSES_45__LpmlL2_4__SHIFT 0x18
+#define PM_FUSES_46__CoolPdmTc_MASK 0xff
+#define PM_FUSES_46__CoolPdmTc__SHIFT 0x0
+#define PM_FUSES_46__BaseCpcTdpLimit2_MASK 0xff00
+#define PM_FUSES_46__BaseCpcTdpLimit2__SHIFT 0x8
+#define PM_FUSES_46__BaseCpcTdpLimit1_MASK 0xff0000
+#define PM_FUSES_46__BaseCpcTdpLimit1__SHIFT 0x10
+#define PM_FUSES_46__BaseCpcTdpLimit_MASK 0xff000000
+#define PM_FUSES_46__BaseCpcTdpLimit__SHIFT 0x18
+#define PM_FUSES_47__CoolPdmThr2_MASK 0xff
+#define PM_FUSES_47__CoolPdmThr2__SHIFT 0x0
+#define PM_FUSES_47__CoolPdmThr1_MASK 0xff00
+#define PM_FUSES_47__CoolPdmThr1__SHIFT 0x8
+#define PM_FUSES_47__GpuPdmTc_MASK 0xff0000
+#define PM_FUSES_47__GpuPdmTc__SHIFT 0x10
+#define PM_FUSES_47__HeatPdmTc_MASK 0xff000000
+#define PM_FUSES_47__HeatPdmTc__SHIFT 0x18
+#define PM_FUSES_48__PkgPwr_MAWt_MASK 0xff
+#define PM_FUSES_48__PkgPwr_MAWt__SHIFT 0x0
+#define PM_FUSES_48__GpuActThr_MASK 0xff00
+#define PM_FUSES_48__GpuActThr__SHIFT 0x8
+#define PM_FUSES_48__HeatPdmThr2_MASK 0xff0000
+#define PM_FUSES_48__HeatPdmThr2__SHIFT 0x10
+#define PM_FUSES_48__HeatPdmThr1_MASK 0xff000000
+#define PM_FUSES_48__HeatPdmThr1__SHIFT 0x18
+#define PM_FUSES_49__SocketTdp_MASK 0xffff
+#define PM_FUSES_49__SocketTdp__SHIFT 0x0
+#define PM_FUSES_49__GpuPdmMult_MASK 0xffff0000
+#define PM_FUSES_49__GpuPdmMult__SHIFT 0x10
+#define PM_FUSES_50__Reserved2_MASK 0xffff
+#define PM_FUSES_50__Reserved2__SHIFT 0x0
+#define PM_FUSES_50__Reserved1_MASK 0xff0000
+#define PM_FUSES_50__Reserved1__SHIFT 0x10
+#define PM_FUSES_50__NumBoostStates_MASK 0xff000000
+#define PM_FUSES_50__NumBoostStates__SHIFT 0x18
+#define PM_FUSES_51__FUSE_DATA_MASK 0xffffffff
+#define PM_FUSES_51__FUSE_DATA__SHIFT 0x0
+#define PM_FUSES_52__FUSE_DATA_MASK 0xffffffff
+#define PM_FUSES_52__FUSE_DATA__SHIFT 0x0
+#define PM_FUSES_53__FUSE_DATA_MASK 0xffffffff
+#define PM_FUSES_53__FUSE_DATA__SHIFT 0x0
+#define PM_FUSES_54__FUSE_DATA_MASK 0xffffffff
+#define PM_FUSES_54__FUSE_DATA__SHIFT 0x0
+#define PM_FUSES_55__FUSE_DATA_MASK 0xffffffff
+#define PM_FUSES_55__FUSE_DATA__SHIFT 0x0
+#define PM_FUSES_56__FUSE_DATA_MASK 0xffffffff
+#define PM_FUSES_56__FUSE_DATA__SHIFT 0x0
+#define PM_FUSES_57__FUSE_DATA_MASK 0xffffffff
+#define PM_FUSES_57__FUSE_DATA__SHIFT 0x0
+#define PM_FUSES_58__FUSE_DATA_MASK 0xffffffff
+#define PM_FUSES_58__FUSE_DATA__SHIFT 0x0
+#define PM_FUSES_59__FUSE_DATA_MASK 0xffffffff
+#define PM_FUSES_59__FUSE_DATA__SHIFT 0x0
+#define PM_FUSES_60__FUSE_DATA_MASK 0xffffffff
+#define PM_FUSES_60__FUSE_DATA__SHIFT 0x0
+#define PM_FUSES_61__FUSE_DATA_MASK 0xffffffff
+#define PM_FUSES_61__FUSE_DATA__SHIFT 0x0
+#define PM_FUSES_62__FUSE_DATA_MASK 0xffffffff
+#define PM_FUSES_62__FUSE_DATA__SHIFT 0x0
+#define PM_FUSES_63__FUSE_DATA_MASK 0xffffffff
+#define PM_FUSES_63__FUSE_DATA__SHIFT 0x0
+#define PM_FUSES_64__FUSE_DATA_MASK 0xffffffff
+#define PM_FUSES_64__FUSE_DATA__SHIFT 0x0
+#define PM_FUSES_65__FUSE_DATA_MASK 0xffffffff
+#define PM_FUSES_65__FUSE_DATA__SHIFT 0x0
+#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1
+#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
+#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe
+#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
+#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000
+#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18
+#define TEMPERATURE_READ_ADDR__CSR_ADDR_MASK 0x3f
+#define TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT 0x0
+#define TEMPERATURE_READ_ADDR__TCEN_ID_MASK 0x3c0
+#define TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT 0x6
+#define TEMPERATURE_READ_ADDR__RESERVED_MASK 0xfffffc00
+#define TEMPERATURE_READ_ADDR__RESERVED__SHIFT 0xa
+#define CURRENT_GNB_TEMP__TEMP_MASK 0x7ff
+#define CURRENT_GNB_TEMP__TEMP__SHIFT 0x0
+#define CURRENT_GLOBAL_TEMP__TEMP_MASK 0x7ff
+#define CURRENT_GLOBAL_TEMP__TEMP__SHIFT 0x0
+#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1
+#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0
+#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2
+#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1
+#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4
+#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2
+#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8
+#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3
+#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10
+#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4
+#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x20
+#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x5
+#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x40
+#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x6
+#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80
+#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7
+#define FEATURE_STATUS__BAPM_ON_MASK 0x100
+#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8
+#define FEATURE_STATUS__LPMX_ON_MASK 0x200
+#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9
+#define FEATURE_STATUS__NBDPM_ON_MASK 0x400
+#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa
+#define FEATURE_STATUS__LHTC_ON_MASK 0x800
+#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb
+#define FEATURE_STATUS__VPC_ON_MASK 0x1000
+#define FEATURE_STATUS__VPC_ON__SHIFT 0xc
+#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000
+#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd
+#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000
+#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe
+#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000
+#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf
+#define FEATURE_STATUS__AVS_ON_MASK 0x10000
+#define FEATURE_STATUS__AVS_ON__SHIFT 0x10
+#define FEATURE_STATUS__SPMI_ON_MASK 0x20000
+#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11
+#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000
+#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12
+#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000
+#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13
+#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000
+#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14
+#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000
+#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15
+#define FEATURE_STATUS__CLK_MON_ON_MASK 0x400000
+#define FEATURE_STATUS__CLK_MON_ON__SHIFT 0x16
+#define FEATURE_STATUS__RESERVED_MASK 0xff800000
+#define FEATURE_STATUS__RESERVED__SHIFT 0x17
+#define PCIE_PLL_RECONF__RECONF_WAIT_MASK 0xff
+#define PCIE_PLL_RECONF__RECONF_WAIT__SHIFT 0x0
+#define PCIE_PLL_RECONF__RECONF_WRAPPER_MASK 0xff00
+#define PCIE_PLL_RECONF__RECONF_WRAPPER__SHIFT 0x8
+#define PCIE_PLL_RECONF__SB_RELOCATE_EN_MASK 0xff0000
+#define PCIE_PLL_RECONF__SB_RELOCATE_EN__SHIFT 0x10
+#define PCIE_PLL_RECONF__SB_NEW_PORT_MASK 0xff000000
+#define PCIE_PLL_RECONF__SB_NEW_PORT__SHIFT 0x18
+#define PM_INTERVAL_CNTL_0__LCLK_DPM_MASK 0xff
+#define PM_INTERVAL_CNTL_0__LCLK_DPM__SHIFT 0x0
+#define PM_INTERVAL_CNTL_0__THERMAL_CNTL_MASK 0xff00
+#define PM_INTERVAL_CNTL_0__THERMAL_CNTL__SHIFT 0x8
+#define PM_INTERVAL_CNTL_0__VOLTAGE_CNTL_MASK 0xff0000
+#define PM_INTERVAL_CNTL_0__VOLTAGE_CNTL__SHIFT 0x10
+#define PM_INTERVAL_CNTL_0__LOADLINE_MASK 0xff000000
+#define PM_INTERVAL_CNTL_0__LOADLINE__SHIFT 0x18
+#define PM_INTERVAL_CNTL_1__NB_DPM_MASK 0xff
+#define PM_INTERVAL_CNTL_1__NB_DPM__SHIFT 0x0
+#define PM_INTERVAL_CNTL_1__AVS_PERIOD_MASK 0xff00
+#define PM_INTERVAL_CNTL_1__AVS_PERIOD__SHIFT 0x8
+#define PM_INTERVAL_CNTL_1__PKGPWR_PERIOD_MASK 0xff0000
+#define PM_INTERVAL_CNTL_1__PKGPWR_PERIOD__SHIFT 0x10
+#define PM_INTERVAL_CNTL_1__TDP_CNTL_MASK 0xff000000
+#define PM_INTERVAL_CNTL_1__TDP_CNTL__SHIFT 0x18
+#define PM_INTERVAL_CNTL_2__BAPM_PERIOD_MASK 0xff
+#define PM_INTERVAL_CNTL_2__BAPM_PERIOD__SHIFT 0x0
+#define PM_INTERVAL_CNTL_2__HTC_PERIOD_MASK 0xff00
+#define PM_INTERVAL_CNTL_2__HTC_PERIOD__SHIFT 0x8
+#define PM_INTERVAL_CNTL_2__TDC_PERIOD_MASK 0xff0000
+#define PM_INTERVAL_CNTL_2__TDC_PERIOD__SHIFT 0x10
+#define PM_INTERVAL_CNTL_2__LPMX_PERIOD_MASK 0xff000000
+#define PM_INTERVAL_CNTL_2__LPMX_PERIOD__SHIFT 0x18
+#define VPC_INTERVAL_CNTL__VPC_PERIOD_MASK 0xffffffff
+#define VPC_INTERVAL_CNTL__VPC_PERIOD__SHIFT 0x0
+#define DISP_PHY_TDP_LIMIT__DisplayPhyTdpLimit_MASK 0xffffffff
+#define DISP_PHY_TDP_LIMIT__DisplayPhyTdpLimit__SHIFT 0x0
+#define FCH_PWR_CREDIT__FchPwrCredit_MASK 0xffffffff
+#define FCH_PWR_CREDIT__FchPwrCredit__SHIFT 0x0
+#define PKGPWR_MV_AVG__Avg_Pkg_Pwr_MASK 0xffffffff
+#define PKGPWR_MV_AVG__Avg_Pkg_Pwr__SHIFT 0x0
+#define PACKAGE_POWER__Pkg_power_MASK 0xffffffff
+#define PACKAGE_POWER__Pkg_power__SHIFT 0x0
+#define PKG_PWR_CNTL__CpcGpuPerfPri_MASK 0x1
+#define PKG_PWR_CNTL__CpcGpuPerfPri__SHIFT 0x0
+#define PKG_PWR_CNTL__PkgPwrLimit_MASK 0x1fffe
+#define PKG_PWR_CNTL__PkgPwrLimit__SHIFT 0x1
+#define PKG_PWR_CNTL__FchPwrCreditScale_MASK 0x7e0000
+#define PKG_PWR_CNTL__FchPwrCreditScale__SHIFT 0x11
+#define PKG_PWR_CNTL__PkgHystCoeff_MASK 0x1f800000
+#define PKG_PWR_CNTL__PkgHystCoeff__SHIFT 0x17
+#define PKG_PWR_CNTL__RESERVED_MASK 0xe0000000
+#define PKG_PWR_CNTL__RESERVED__SHIFT 0x1d
+#define PKG_PWR_STATUS__GnbMinLimitSetFlag_MASK 0x1
+#define PKG_PWR_STATUS__GnbMinLimitSetFlag__SHIFT 0x0
+#define PKG_PWR_STATUS__PstateLimitSetFlag_MASK 0x2
+#define PKG_PWR_STATUS__PstateLimitSetFlag__SHIFT 0x1
+#define PKG_PWR_STATUS__PkgPwrLimit_base_MASK 0x3fffc
+#define PKG_PWR_STATUS__PkgPwrLimit_base__SHIFT 0x2
+#define PKG_PWR_STATUS__RESERVED_MASK 0xfc0000
+#define PKG_PWR_STATUS__RESERVED__SHIFT 0x12
+#define PKG_PWR_STATUS__PkgPwr_MAWt_MASK 0xff000000
+#define PKG_PWR_STATUS__PkgPwr_MAWt__SHIFT 0x18
+#define DISP_PHY_CONFIG__Corner_MASK 0xff
+#define DISP_PHY_CONFIG__Corner__SHIFT 0x0
+#define DISP_PHY_CONFIG__DispPHYConfig_MASK 0xff00
+#define DISP_PHY_CONFIG__DispPHYConfig__SHIFT 0x8
+#define GPU_TDP_LIMIT__Gpu_Tdp_Limit_MASK 0xffff
+#define GPU_TDP_LIMIT__Gpu_Tdp_Limit__SHIFT 0x0
+#define GPU_TDP_LIMIT__Reserved_MASK 0xffff0000
+#define GPU_TDP_LIMIT__Reserved__SHIFT 0x10
+#define EXT_API_IN_DATA_0_0__byte0_MASK 0xff
+#define EXT_API_IN_DATA_0_0__byte0__SHIFT 0x0
+#define EXT_API_IN_DATA_0_0__byte1_MASK 0xff00
+#define EXT_API_IN_DATA_0_0__byte1__SHIFT 0x8
+#define EXT_API_IN_DATA_0_0__byte2_MASK 0xff0000
+#define EXT_API_IN_DATA_0_0__byte2__SHIFT 0x10
+#define EXT_API_IN_DATA_0_0__byte3_MASK 0xff000000
+#define EXT_API_IN_DATA_0_0__byte3__SHIFT 0x18
+#define EXT_API_IN_DATA_0_1__byte0_MASK 0xff
+#define EXT_API_IN_DATA_0_1__byte0__SHIFT 0x0
+#define EXT_API_IN_DATA_0_1__byte1_MASK 0xff00
+#define EXT_API_IN_DATA_0_1__byte1__SHIFT 0x8
+#define EXT_API_IN_DATA_0_1__byte2_MASK 0xff0000
+#define EXT_API_IN_DATA_0_1__byte2__SHIFT 0x10
+#define EXT_API_IN_DATA_0_1__byte3_MASK 0xff000000
+#define EXT_API_IN_DATA_0_1__byte3__SHIFT 0x18
+#define EXT_API_IN_DATA_0_2__byte0_MASK 0xff
+#define EXT_API_IN_DATA_0_2__byte0__SHIFT 0x0
+#define EXT_API_IN_DATA_0_2__byte1_MASK 0xff00
+#define EXT_API_IN_DATA_0_2__byte1__SHIFT 0x8
+#define EXT_API_IN_DATA_0_2__byte2_MASK 0xff0000
+#define EXT_API_IN_DATA_0_2__byte2__SHIFT 0x10
+#define EXT_API_IN_DATA_0_2__byte3_MASK 0xff000000
+#define EXT_API_IN_DATA_0_2__byte3__SHIFT 0x18
+#define EXT_API_IN_DATA_0_3__byte0_MASK 0xff
+#define EXT_API_IN_DATA_0_3__byte0__SHIFT 0x0
+#define EXT_API_IN_DATA_0_3__byte1_MASK 0xff00
+#define EXT_API_IN_DATA_0_3__byte1__SHIFT 0x8
+#define EXT_API_IN_DATA_0_3__byte2_MASK 0xff0000
+#define EXT_API_IN_DATA_0_3__byte2__SHIFT 0x10
+#define EXT_API_IN_DATA_0_3__byte3_MASK 0xff000000
+#define EXT_API_IN_DATA_0_3__byte3__SHIFT 0x18
+#define EXT_API_OUT_DATA_0_0__byte0_MASK 0xff
+#define EXT_API_OUT_DATA_0_0__byte0__SHIFT 0x0
+#define EXT_API_OUT_DATA_0_0__byte1_MASK 0xff00
+#define EXT_API_OUT_DATA_0_0__byte1__SHIFT 0x8
+#define EXT_API_OUT_DATA_0_0__byte2_MASK 0xff0000
+#define EXT_API_OUT_DATA_0_0__byte2__SHIFT 0x10
+#define EXT_API_OUT_DATA_0_0__byte3_MASK 0xff000000
+#define EXT_API_OUT_DATA_0_0__byte3__SHIFT 0x18
+#define EXT_API_OUT_DATA_0_1__byte0_MASK 0xff
+#define EXT_API_OUT_DATA_0_1__byte0__SHIFT 0x0
+#define EXT_API_OUT_DATA_0_1__byte1_MASK 0xff00
+#define EXT_API_OUT_DATA_0_1__byte1__SHIFT 0x8
+#define EXT_API_OUT_DATA_0_1__byte2_MASK 0xff0000
+#define EXT_API_OUT_DATA_0_1__byte2__SHIFT 0x10
+#define EXT_API_OUT_DATA_0_1__byte3_MASK 0xff000000
+#define EXT_API_OUT_DATA_0_1__byte3__SHIFT 0x18
+#define EXT_API_OUT_DATA_0_2__byte0_MASK 0xff
+#define EXT_API_OUT_DATA_0_2__byte0__SHIFT 0x0
+#define EXT_API_OUT_DATA_0_2__byte1_MASK 0xff00
+#define EXT_API_OUT_DATA_0_2__byte1__SHIFT 0x8
+#define EXT_API_OUT_DATA_0_2__byte2_MASK 0xff0000
+#define EXT_API_OUT_DATA_0_2__byte2__SHIFT 0x10
+#define EXT_API_OUT_DATA_0_2__byte3_MASK 0xff000000
+#define EXT_API_OUT_DATA_0_2__byte3__SHIFT 0x18
+#define EXT_API_OUT_DATA_0_3__byte0_MASK 0xff
+#define EXT_API_OUT_DATA_0_3__byte0__SHIFT 0x0
+#define EXT_API_OUT_DATA_0_3__byte1_MASK 0xff00
+#define EXT_API_OUT_DATA_0_3__byte1__SHIFT 0x8
+#define EXT_API_OUT_DATA_0_3__byte2_MASK 0xff0000
+#define EXT_API_OUT_DATA_0_3__byte2__SHIFT 0x10
+#define EXT_API_OUT_DATA_0_3__byte3_MASK 0xff000000
+#define EXT_API_OUT_DATA_0_3__byte3__SHIFT 0x18
+#define BAPM_PARAMETERS__MaxPwrCpu_1_MASK 0xff
+#define BAPM_PARAMETERS__MaxPwrCpu_1__SHIFT 0x0
+#define BAPM_PARAMETERS__NomPwrCpu_1_MASK 0xff00
+#define BAPM_PARAMETERS__NomPwrCpu_1__SHIFT 0x8
+#define BAPM_PARAMETERS__MaxPwrCpu_0_MASK 0xff0000
+#define BAPM_PARAMETERS__MaxPwrCpu_0__SHIFT 0x10
+#define BAPM_PARAMETERS__NomPwrCpu_0_MASK 0xff000000
+#define BAPM_PARAMETERS__NomPwrCpu_0__SHIFT 0x18
+#define BAPM_PARAMETERS_2__MaxPwrGpu_MASK 0xffff
+#define BAPM_PARAMETERS_2__MaxPwrGpu__SHIFT 0x0
+#define BAPM_PARAMETERS_2__NomPwrGpu_MASK 0xffff0000
+#define BAPM_PARAMETERS_2__NomPwrGpu__SHIFT 0x10
+#define BAPM_PARAMETERS_3__TjOffset_MASK 0xff
+#define BAPM_PARAMETERS_3__TjOffset__SHIFT 0x0
+#define BAPM_PARAMETERS_3__EnergyCntNorm_MASK 0x3ff00
+#define BAPM_PARAMETERS_3__EnergyCntNorm__SHIFT 0x8
+#define BAPM_PARAMETERS_3__Reserved_MASK 0xfffc0000
+#define BAPM_PARAMETERS_3__Reserved__SHIFT 0x12
+#define BAPM_PARAMETERS_4__MinPwrGpu_MASK 0xffff
+#define BAPM_PARAMETERS_4__MinPwrGpu__SHIFT 0x0
+#define BAPM_PARAMETERS_4__MidPwrCpu_1_MASK 0xff0000
+#define BAPM_PARAMETERS_4__MidPwrCpu_1__SHIFT 0x10
+#define BAPM_PARAMETERS_4__MidPwrCpu_0_MASK 0xff000000
+#define BAPM_PARAMETERS_4__MidPwrCpu_0__SHIFT 0x18
+#define SMU_SVI_TELEMETRY__Iddspike_OCP_MASK 0xffff
+#define SMU_SVI_TELEMETRY__Iddspike_OCP__SHIFT 0x0
+#define SMU_SVI_TELEMETRY__IddNbspike_OCP_MASK 0xffff0000
+#define SMU_SVI_TELEMETRY__IddNbspike_OCP__SHIFT 0x10
+#define BAPM_STATUS__THROTTLE_MASK 0xff
+#define BAPM_STATUS__THROTTLE__SHIFT 0x0
+#define BAPM_STATUS__THROTTLE_LAST_MASK 0xff00
+#define BAPM_STATUS__THROTTLE_LAST__SHIFT 0x8
+#define BAPM_STATUS__COUNT_CORE1_MASK 0xff0000
+#define BAPM_STATUS__COUNT_CORE1__SHIFT 0x10
+#define BAPM_STATUS__COUNT_CORE0_MASK 0xff000000
+#define BAPM_STATUS__COUNT_CORE0__SHIFT 0x18
+#define SMU_HTC_STATUS__HTC_ACTIVE_MASK 0x1
+#define SMU_HTC_STATUS__HTC_ACTIVE__SHIFT 0x0
+#define SMU_HTC_STATUS__Reserved_MASK 0xfffffffe
+#define SMU_HTC_STATUS__Reserved__SHIFT 0x1
+#define SMU_VPC_STATUS__AllCpuIdleLast_MASK 0x1
+#define SMU_VPC_STATUS__AllCpuIdleLast__SHIFT 0x0
+#define SMU_VPC_STATUS__Reserved_MASK 0xfffffffe
+#define SMU_VPC_STATUS__Reserved__SHIFT 0x1
+#define ENTITY_TEMPERATURES_1__CORE0_MASK 0xffffffff
+#define ENTITY_TEMPERATURES_1__CORE0__SHIFT 0x0
+#define ENTITY_TEMPERATURES_2__CORE1_MASK 0xffffffff
+#define ENTITY_TEMPERATURES_2__CORE1__SHIFT 0x0
+#define ENTITY_TEMPERATURES_3__GPU_MASK 0xffffffff
+#define ENTITY_TEMPERATURES_3__GPU__SHIFT 0x0
+#define CU_POWER__CU0_POWER_MASK 0xffff
+#define CU_POWER__CU0_POWER__SHIFT 0x0
+#define CU_POWER__CU1_POWER_MASK 0xffff0000
+#define CU_POWER__CU1_POWER__SHIFT 0x10
+#define GPU_POWER__IGPU_POWER_MASK 0xffff
+#define GPU_POWER__IGPU_POWER__SHIFT 0x0
+#define GPU_POWER__DGPU_POWER_MASK 0xffff0000
+#define GPU_POWER__DGPU_POWER__SHIFT 0x10
+#define NTE_POWER__NTE0_POWER_MASK 0xffff
+#define NTE_POWER__NTE0_POWER__SHIFT 0x0
+#define NTE_POWER__NTE1_POWER_MASK 0xffff0000
+#define NTE_POWER__NTE1_POWER__SHIFT 0x10
+#define TDC_STATUS__VDD_Boost_MASK 0xff
+#define TDC_STATUS__VDD_Boost__SHIFT 0x0
+#define TDC_STATUS__VDD_Throttle_MASK 0xff00
+#define TDC_STATUS__VDD_Throttle__SHIFT 0x8
+#define TDC_STATUS__VDDNB_Boost_MASK 0xff0000
+#define TDC_STATUS__VDDNB_Boost__SHIFT 0x10
+#define TDC_STATUS__VDDNB_Throttle_MASK 0xff000000
+#define TDC_STATUS__VDDNB_Throttle__SHIFT 0x18
+#define TDC_MV_AVERAGE__IDD_MASK 0xffff
+#define TDC_MV_AVERAGE__IDD__SHIFT 0x0
+#define TDC_MV_AVERAGE__IDDNB_MASK 0xffff0000
+#define TDC_MV_AVERAGE__IDDNB__SHIFT 0x10
+#define PM_CONFIG__Enable_VPC_Accumulators_MASK 0x1
+#define PM_CONFIG__Enable_VPC_Accumulators__SHIFT 0x0
+#define PM_CONFIG__Enable_BAPM_MASK 0x2
+#define PM_CONFIG__Enable_BAPM__SHIFT 0x1
+#define PM_CONFIG__Enable_TDC_Limit_MASK 0x4
+#define PM_CONFIG__Enable_TDC_Limit__SHIFT 0x2
+#define PM_CONFIG__Enable_LPMx_MASK 0x8
+#define PM_CONFIG__Enable_LPMx__SHIFT 0x3
+#define PM_CONFIG__Enable_HTC_Limit_MASK 0x10
+#define PM_CONFIG__Enable_HTC_Limit__SHIFT 0x4
+#define PM_CONFIG__Enable_NBDPM_MASK 0x20
+#define PM_CONFIG__Enable_NBDPM__SHIFT 0x5
+#define PM_CONFIG__Enable_LoadLine_MASK 0x40
+#define PM_CONFIG__Enable_LoadLine__SHIFT 0x6
+#define PM_CONFIG__Reserved_MASK 0xff80
+#define PM_CONFIG__Reserved__SHIFT 0x7
+#define PM_CONFIG__Override_VPC_Current_MASK 0x10000
+#define PM_CONFIG__Override_VPC_Current__SHIFT 0x10
+#define PM_CONFIG__Reserved1_MASK 0x60000
+#define PM_CONFIG__Reserved1__SHIFT 0x11
+#define PM_CONFIG__Override_Calc_Temp_MASK 0x80000
+#define PM_CONFIG__Override_Calc_Temp__SHIFT 0x13
+#define PM_CONFIG__Enable_Hybrid_Boost_MASK 0x100000
+#define PM_CONFIG__Enable_Hybrid_Boost__SHIFT 0x14
+#define PM_CONFIG__Reserved2_MASK 0xe00000
+#define PM_CONFIG__Reserved2__SHIFT 0x15
+#define PM_CONFIG__PSTATE_AllCpusIdle_MASK 0x7000000
+#define PM_CONFIG__PSTATE_AllCpusIdle__SHIFT 0x18
+#define PM_CONFIG__NBPSTATE_AllCpusIdle_MASK 0x8000000
+#define PM_CONFIG__NBPSTATE_AllCpusIdle__SHIFT 0x1b
+#define PM_CONFIG__Reserved3_MASK 0x10000000
+#define PM_CONFIG__Reserved3__SHIFT 0x1c
+#define PM_CONFIG__SVI_Mode_MASK 0x20000000
+#define PM_CONFIG__SVI_Mode__SHIFT 0x1d
+#define PM_CONFIG__Enable_PDM_MASK 0x40000000
+#define PM_CONFIG__Enable_PDM__SHIFT 0x1e
+#define PM_CONFIG__Enable_PKG_PWR_LIMIT_MASK 0x80000000
+#define PM_CONFIG__Enable_PKG_PWR_LIMIT__SHIFT 0x1f
+#define TE0_TEMPERATURE_READ_ADDR__CSR_ADDR_MASK 0x3f
+#define TE0_TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT 0x0
+#define TE0_TEMPERATURE_READ_ADDR__TCEN_ID_MASK 0x3c0
+#define TE0_TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT 0x6
+#define TE0_TEMPERATURE_READ_ADDR__RESERVED_MASK 0xfffffc00
+#define TE0_TEMPERATURE_READ_ADDR__RESERVED__SHIFT 0xa
+#define TE1_TEMPERATURE_READ_ADDR__CSR_ADDR_MASK 0x3f
+#define TE1_TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT 0x0
+#define TE1_TEMPERATURE_READ_ADDR__TCEN_ID_MASK 0x3c0
+#define TE1_TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT 0x6
+#define TE1_TEMPERATURE_READ_ADDR__RESERVED_MASK 0xfffffc00
+#define TE1_TEMPERATURE_READ_ADDR__RESERVED__SHIFT 0xa
+#define TE2_TEMPERATURE_READ_ADDR__CSR_ADDR_MASK 0x3f
+#define TE2_TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT 0x0
+#define TE2_TEMPERATURE_READ_ADDR__TCEN_ID_MASK 0x3c0
+#define TE2_TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT 0x6
+#define TE2_TEMPERATURE_READ_ADDR__RESERVED_MASK 0xfffffc00
+#define TE2_TEMPERATURE_READ_ADDR__RESERVED__SHIFT 0xa
+#define NB_DPM_CONFIG_1__Dpm0PgNbPsLo_MASK 0xff
+#define NB_DPM_CONFIG_1__Dpm0PgNbPsLo__SHIFT 0x0
+#define NB_DPM_CONFIG_1__Dpm0PgNbPsHi_MASK 0xff00
+#define NB_DPM_CONFIG_1__Dpm0PgNbPsHi__SHIFT 0x8
+#define NB_DPM_CONFIG_1__DpmXNbPsLo_MASK 0xff0000
+#define NB_DPM_CONFIG_1__DpmXNbPsLo__SHIFT 0x10
+#define NB_DPM_CONFIG_1__DpmXNbPsHi_MASK 0xff000000
+#define NB_DPM_CONFIG_1__DpmXNbPsHi__SHIFT 0x18
+#define NB_DPM_CONFIG_2__Hysteresis_MASK 0xff
+#define NB_DPM_CONFIG_2__Hysteresis__SHIFT 0x0
+#define NB_DPM_CONFIG_2__SkipPG_MASK 0xff00
+#define NB_DPM_CONFIG_2__SkipPG__SHIFT 0x8
+#define NB_DPM_CONFIG_2__SkipDPM0_MASK 0xff0000
+#define NB_DPM_CONFIG_2__SkipDPM0__SHIFT 0x10
+#define NB_DPM_CONFIG_2__EnablePSI1_MASK 0xff000000
+#define NB_DPM_CONFIG_2__EnablePSI1__SHIFT 0x18
+#define NB_DPM_CONFIG_3__RESERVED_MASK 0xffffff
+#define NB_DPM_CONFIG_3__RESERVED__SHIFT 0x0
+#define NB_DPM_CONFIG_3__EnableDpmPstatePoll_MASK 0xff000000
+#define NB_DPM_CONFIG_3__EnableDpmPstatePoll__SHIFT 0x18
+#define SMU_IDD_OVERRIDE__IDD_MASK 0xffff
+#define SMU_IDD_OVERRIDE__IDD__SHIFT 0x0
+#define SMU_IDD_OVERRIDE__IDDNB_MASK 0xffff0000
+#define SMU_IDD_OVERRIDE__IDDNB__SHIFT 0x10
+#define AVS_CONFIG__AvsEnabledForPstates_MASK 0xff
+#define AVS_CONFIG__AvsEnabledForPstates__SHIFT 0x0
+#define AVS_CONFIG__AvsOverrideEnabled_MASK 0x100
+#define AVS_CONFIG__AvsOverrideEnabled__SHIFT 0x8
+#define AVS_CONFIG__AvsPsmTempCompensation_MASK 0x200
+#define AVS_CONFIG__AvsPsmTempCompensation__SHIFT 0x9
+#define AVS_CONFIG__RESERVED1_MASK 0xfc00
+#define AVS_CONFIG__RESERVED1__SHIFT 0xa
+#define AVS_CONFIG__AvsOverrideOffset_MASK 0xff0000
+#define AVS_CONFIG__AvsOverrideOffset__SHIFT 0x10
+#define AVS_CONFIG__RESERVED_MASK 0xff000000
+#define AVS_CONFIG__RESERVED__SHIFT 0x18
+#define TDC_VRM_LIMIT__IDD_MASK 0xffff
+#define TDC_VRM_LIMIT__IDD__SHIFT 0x0
+#define TDC_VRM_LIMIT__IDDNB_MASK 0xffff0000
+#define TDC_VRM_LIMIT__IDDNB__SHIFT 0x10
+#define CU0_PSM_CONFIG__Psm4_MASK 0xff
+#define CU0_PSM_CONFIG__Psm4__SHIFT 0x0
+#define CU0_PSM_CONFIG__Psm3_MASK 0xff00
+#define CU0_PSM_CONFIG__Psm3__SHIFT 0x8
+#define CU0_PSM_CONFIG__Psm2_MASK 0xff0000
+#define CU0_PSM_CONFIG__Psm2__SHIFT 0x10
+#define CU0_PSM_CONFIG__Psm1_MASK 0xff000000
+#define CU0_PSM_CONFIG__Psm1__SHIFT 0x18
+#define CU1_PSM_CONFIG__Psm4_MASK 0xff
+#define CU1_PSM_CONFIG__Psm4__SHIFT 0x0
+#define CU1_PSM_CONFIG__Psm3_MASK 0xff00
+#define CU1_PSM_CONFIG__Psm3__SHIFT 0x8
+#define CU1_PSM_CONFIG__Psm2_MASK 0xff0000
+#define CU1_PSM_CONFIG__Psm2__SHIFT 0x10
+#define CU1_PSM_CONFIG__Psm1_MASK 0xff000000
+#define CU1_PSM_CONFIG__Psm1__SHIFT 0x18
+#define SPMI_CONFIG__SpmiTestCode_MASK 0xff
+#define SPMI_CONFIG__SpmiTestCode__SHIFT 0x0
+#define SPMI_CONFIG__SpmiTestData_MASK 0xff00
+#define SPMI_CONFIG__SpmiTestData__SHIFT 0x8
+#define SPMI_CONFIG__RESERVED_MASK 0xffff0000
+#define SPMI_CONFIG__RESERVED__SHIFT 0x10
+#define SPMI_SMC_CHAIN_ADDR__Addr_MASK 0xffffffff
+#define SPMI_SMC_CHAIN_ADDR__Addr__SHIFT 0x0
+#define SPMI_STATUS__OpDone_MASK 0xff
+#define SPMI_STATUS__OpDone__SHIFT 0x0
+#define SPMI_STATUS__OpFailed_MASK 0xff00
+#define SPMI_STATUS__OpFailed__SHIFT 0x8
+#define AVSNB_CONFIG__AvsEnabledForPstates_MASK 0xf
+#define AVSNB_CONFIG__AvsEnabledForPstates__SHIFT 0x0
+#define AVSNB_CONFIG__RESERVED0_MASK 0xf0
+#define AVSNB_CONFIG__RESERVED0__SHIFT 0x4
+#define AVSNB_CONFIG__AvsOverrideEnabled_MASK 0x100
+#define AVSNB_CONFIG__AvsOverrideEnabled__SHIFT 0x8
+#define AVSNB_CONFIG__AvsPsmTempCompensation_MASK 0x200
+#define AVSNB_CONFIG__AvsPsmTempCompensation__SHIFT 0x9
+#define AVSNB_CONFIG__RESERVED1_MASK 0xfc00
+#define AVSNB_CONFIG__RESERVED1__SHIFT 0xa
+#define AVSNB_CONFIG__AvsOverrideOffset_MASK 0xff0000
+#define AVSNB_CONFIG__AvsOverrideOffset__SHIFT 0x10
+#define AVSNB_CONFIG__RESERVED_MASK 0xff000000
+#define AVSNB_CONFIG__RESERVED__SHIFT 0x18
+#define HTC_CONFIG__CSR_ADDR_MASK 0x3f
+#define HTC_CONFIG__CSR_ADDR__SHIFT 0x0
+#define HTC_CONFIG__TCEN_ID_MASK 0x3c0
+#define HTC_CONFIG__TCEN_ID__SHIFT 0x6
+#define HTC_CONFIG__HTC_ACTIVE_PSTATE_LIMIT_MASK 0xff0000
+#define HTC_CONFIG__HTC_ACTIVE_PSTATE_LIMIT__SHIFT 0x10
+#define HTC_CONFIG__Reserved_MASK 0xff000000
+#define HTC_CONFIG__Reserved__SHIFT 0x18
+#define AVS_CU0_TEMPERATURE_SENSOR__CsrAddr_MASK 0x3f
+#define AVS_CU0_TEMPERATURE_SENSOR__CsrAddr__SHIFT 0x0
+#define AVS_CU0_TEMPERATURE_SENSOR__TcenID_MASK 0x3c0
+#define AVS_CU0_TEMPERATURE_SENSOR__TcenID__SHIFT 0x6
+#define AVS_CU0_TEMPERATURE_SENSOR__RESERVED_MASK 0xfffffc00
+#define AVS_CU0_TEMPERATURE_SENSOR__RESERVED__SHIFT 0xa
+#define AVS_CU1_TEMPERATURE_SENSOR__CsrAddr_MASK 0x3f
+#define AVS_CU1_TEMPERATURE_SENSOR__CsrAddr__SHIFT 0x0
+#define AVS_CU1_TEMPERATURE_SENSOR__TcenID_MASK 0x3c0
+#define AVS_CU1_TEMPERATURE_SENSOR__TcenID__SHIFT 0x6
+#define AVS_CU1_TEMPERATURE_SENSOR__RESERVED_MASK 0xfffffc00
+#define AVS_CU1_TEMPERATURE_SENSOR__RESERVED__SHIFT 0xa
+#define AVS_GNB_TEMPERATURE_SENSOR__CsrAddr_MASK 0x3f
+#define AVS_GNB_TEMPERATURE_SENSOR__CsrAddr__SHIFT 0x0
+#define AVS_GNB_TEMPERATURE_SENSOR__TcenID_MASK 0x3c0
+#define AVS_GNB_TEMPERATURE_SENSOR__TcenID__SHIFT 0x6
+#define AVS_GNB_TEMPERATURE_SENSOR__RESERVED_MASK 0xfffffc00
+#define AVS_GNB_TEMPERATURE_SENSOR__RESERVED__SHIFT 0xa
+#define AVS_UNB_TEMPERATURE_SENSOR__CsrAddr_MASK 0x3f
+#define AVS_UNB_TEMPERATURE_SENSOR__CsrAddr__SHIFT 0x0
+#define AVS_UNB_TEMPERATURE_SENSOR__TcenID_MASK 0x3c0
+#define AVS_UNB_TEMPERATURE_SENSOR__TcenID__SHIFT 0x6
+#define AVS_UNB_TEMPERATURE_SENSOR__RESERVED_MASK 0xfffffc00
+#define AVS_UNB_TEMPERATURE_SENSOR__RESERVED__SHIFT 0xa
+#define SMU_MONITOR_PORT80_MMIO_ADDR__MMIO_ADDRESS_MASK 0xffffffff
+#define SMU_MONITOR_PORT80_MMIO_ADDR__MMIO_ADDRESS__SHIFT 0x0
+#define SMU_MONITOR_PORT80_MEMBASE_HI__MEMORY_BASE_HI_MASK 0xffffffff
+#define SMU_MONITOR_PORT80_MEMBASE_HI__MEMORY_BASE_HI__SHIFT 0x0
+#define SMU_MONITOR_PORT80_MEMBASE_LO__MEMORY_BASE_LO_MASK 0xffffffff
+#define SMU_MONITOR_PORT80_MEMBASE_LO__MEMORY_BASE_LO__SHIFT 0x0
+#define SMU_MONITOR_PORT80_MEMSETUP__MEMORY_POSITION_MASK 0xffff
+#define SMU_MONITOR_PORT80_MEMSETUP__MEMORY_POSITION__SHIFT 0x0
+#define SMU_MONITOR_PORT80_MEMSETUP__MEMORY_BUFFER_SIZE_MASK 0xffff0000
+#define SMU_MONITOR_PORT80_MEMSETUP__MEMORY_BUFFER_SIZE__SHIFT 0x10
+#define SMU_MONITOR_PORT80_CTRL__ENABLE_DRAM_SHADOW_MASK 0x1
+#define SMU_MONITOR_PORT80_CTRL__ENABLE_DRAM_SHADOW__SHIFT 0x0
+#define SMU_MONITOR_PORT80_CTRL__ENABLE_CSR_SHADOW_MASK 0x2
+#define SMU_MONITOR_PORT80_CTRL__ENABLE_CSR_SHADOW__SHIFT 0x1
+#define SMU_MONITOR_PORT80_CTRL__RESERVED_MASK 0xfffc
+#define SMU_MONITOR_PORT80_CTRL__RESERVED__SHIFT 0x2
+#define SMU_MONITOR_PORT80_CTRL__POLLING_INTERVAL_MASK 0xffff0000
+#define SMU_MONITOR_PORT80_CTRL__POLLING_INTERVAL__SHIFT 0x10
+#define SMU_TCEN_ALIVE__CORE_TCEN_ID_MASK 0xff
+#define SMU_TCEN_ALIVE__CORE_TCEN_ID__SHIFT 0x0
+#define SMU_TCEN_ALIVE__GNB_TCEN_ID_MASK 0xff00
+#define SMU_TCEN_ALIVE__GNB_TCEN_ID__SHIFT 0x8
+#define SMU_TCEN_ALIVE__RESERVED_MASK 0xffff0000
+#define SMU_TCEN_ALIVE__RESERVED__SHIFT 0x10
+#define PDM_STATUS__PDM_ENABLED_MASK 0x1
+#define PDM_STATUS__PDM_ENABLED__SHIFT 0x0
+#define PDM_STATUS__NewCpcTdpLimit_MASK 0x1fffe
+#define PDM_STATUS__NewCpcTdpLimit__SHIFT 0x1
+#define PDM_STATUS__NoofConnectedCores_MASK 0x1e0000
+#define PDM_STATUS__NoofConnectedCores__SHIFT 0x11
+#define PDM_STATUS__Reserved_MASK 0xffe00000
+#define PDM_STATUS__Reserved__SHIFT 0x15
+#define PDM_CNTL_1__BaseCoreTdpLimit0_MASK 0xff
+#define PDM_CNTL_1__BaseCoreTdpLimit0__SHIFT 0x0
+#define PDM_CNTL_1__BaseCoreTdpLimit1_MASK 0xff00
+#define PDM_CNTL_1__BaseCoreTdpLimit1__SHIFT 0x8
+#define PDM_CNTL_1__BaseCoreTdpLimit2_MASK 0xff0000
+#define PDM_CNTL_1__BaseCoreTdpLimit2__SHIFT 0x10
+#define PDM_CNTL_1__GpuPdmMult_MASK 0xff000000
+#define PDM_CNTL_1__GpuPdmMult__SHIFT 0x18
+#define PDM_CNTL_2__HeatPdmTc_MASK 0xff
+#define PDM_CNTL_2__HeatPdmTc__SHIFT 0x0
+#define PDM_CNTL_2__CoolPdmTc_MASK 0xff00
+#define PDM_CNTL_2__CoolPdmTc__SHIFT 0x8
+#define PDM_CNTL_2__GpuPdmTc_MASK 0xff0000
+#define PDM_CNTL_2__GpuPdmTc__SHIFT 0x10
+#define PDM_CNTL_2__GpuActThr_MASK 0xff000000
+#define PDM_CNTL_2__GpuActThr__SHIFT 0x18
+#define PDM_CNTL_3__HeatPdmThr1_MASK 0xff
+#define PDM_CNTL_3__HeatPdmThr1__SHIFT 0x0
+#define PDM_CNTL_3__HeatPdmThr2_MASK 0xff00
+#define PDM_CNTL_3__HeatPdmThr2__SHIFT 0x8
+#define PDM_CNTL_3__CoolPdmThr1_MASK 0xff0000
+#define PDM_CNTL_3__CoolPdmThr1__SHIFT 0x10
+#define PDM_CNTL_3__CoolPdmThr2_MASK 0xff000000
+#define PDM_CNTL_3__CoolPdmThr2__SHIFT 0x18
+#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_0__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_1__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_2__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_3__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_4__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_5__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_6__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_7__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_8__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_9__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_10__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_11__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_12__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_13__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_14__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_15__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_16__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_17__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_18__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_19__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_20__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_21__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_22__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_23__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_24__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_25__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_26__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_27__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_28__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_29__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_30__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_31__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_32__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_33__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_34__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_35__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_36__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_37__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_38__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_39__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_40__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_41__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_42__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_43__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_44__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_45__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_46__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_47__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_48__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_49__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_50__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_51__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_52__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_53__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_54__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_55__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_56__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_57__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_58__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_59__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_60__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_61__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_62__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_63__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_64__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_65__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_66__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_67__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_68__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_69__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_70__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_71__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_72__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_73__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_74__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_75__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_76__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_77__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_78__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_79__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_80__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_81__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_82__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_83__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_84__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_85__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_86__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_87__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_88__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_89__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_90__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_91__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_92__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_93__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_94__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_95__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_96__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_97__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_98__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_99__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_100__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_101__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_102__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_103__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_104__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_105__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_106__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_107__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_108__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_109__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_110__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_111__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_112__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_113__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_114__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_115__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_116__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_117__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_118__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_119__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_120__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_121__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_122__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_123__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_124__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_125__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_126__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_127__DATA__SHIFT 0x0
+#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1
+#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0
+#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2
+#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2
+#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8
+#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3
+#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10
+#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8
+#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000
+#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10
+#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000
+#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18
+#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000
+#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b
+#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000
+#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c
+#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1
+#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0
+#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2
+#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3
+#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1
+#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0
+#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2
+#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3
+#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40
+#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6
+#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100
+#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8
+#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200
+#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9
+#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400
+#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa
+#define GENERAL_PWRMGT__SPARE11_MASK 0x800
+#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb
+#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000
+#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe
+#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000
+#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf
+#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000
+#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10
+#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000
+#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11
+#define GENERAL_PWRMGT__SPARE18_MASK 0x40000
+#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12
+#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000
+#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13
+#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000
+#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17
+#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000
+#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b
+#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000
+#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c
+#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3
+#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0
+#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4
+#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2
+#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8
+#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3
+#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10
+#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4
+#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0
+#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5
+#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1
+#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0
+#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1_MASK 0x2
+#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1__SHIFT 0x1
+#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN_MASK 0x4
+#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN__SHIFT 0x2
+#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10
+#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4
+#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20
+#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5
+#define SCLK_PWRMGT_CNTL__RESERVED_0_MASK 0x40
+#define SCLK_PWRMGT_CNTL__RESERVED_0__SHIFT 0x6
+#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN_MASK 0x80
+#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN__SHIFT 0x7
+#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON_MASK 0x100
+#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON__SHIFT 0x8
+#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF_MASK 0x200
+#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF__SHIFT 0x9
+#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF_MASK 0x400
+#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF__SHIFT 0xa
+#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1_MASK 0x800
+#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1__SHIFT 0xb
+#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2_MASK 0x1000
+#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2__SHIFT 0xc
+#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3_MASK 0x2000
+#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3__SHIFT 0xd
+#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000
+#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe
+#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000
+#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf
+#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000
+#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10
+#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000
+#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15
+#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL_MASK 0x400000
+#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL__SHIFT 0x16
+#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN_MASK 0x800000
+#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN__SHIFT 0x17
+#define SCLK_PWRMGT_CNTL__RESERVED_3_MASK 0x1000000
+#define SCLK_PWRMGT_CNTL__RESERVED_3__SHIFT 0x18
+#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN_MASK 0x2000000
+#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN__SHIFT 0x19
+#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT_MASK 0x10000000
+#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT__SHIFT 0x1c
+#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT_MASK 0x20000000
+#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT__SHIFT 0x1d
+#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN_MASK 0x40000000
+#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN__SHIFT 0x1e
+#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE_MASK 0x80000000
+#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE__SHIFT 0x1f
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf
+#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
+#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0
+#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4
+#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00
+#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8
+#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000
+#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf
+#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000
+#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c
+#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff
+#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0
+#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f
+#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0
+#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80
+#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7
+#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
+#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
+#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
+#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
+#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000
+#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11
+#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000
+#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12
+#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000
+#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13
+#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000
+#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14
+#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000
+#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15
+#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000
+#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16
+#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000
+#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17
+#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000
+#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19
+#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000
+#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a
+#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000
+#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b
+#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000
+#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c
+#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000
+#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d
+#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000
+#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e
+#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
+#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2
+#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1
+#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4
+#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2
+#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8
+#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10
+#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4
+#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40
+#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6
+#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80
+#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7
+#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100
+#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8
+#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200
+#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9
+#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400
+#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa
+#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800
+#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe
+#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000
+#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15
+#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000
+#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14
+#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
+#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
+#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
+#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
+#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
+#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
+#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000
+#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10
+#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
+#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
+#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1
+#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0
+#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2
+#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3
+#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10
+#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4
+#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20
+#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd
+#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000
+#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe
+#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000
+#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13
+#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000
+#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14
+#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000
+#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16
+#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_STATUS_MASK 0x1
+#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_STATUS__SHIFT 0x0
+#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK 0x1fe
+#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT 0x1
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c
+#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff
+#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0
+#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000
+#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10
+#define SCLK_MIN_DIV__FRACV_MASK 0xfff
+#define SCLK_MIN_DIV__FRACV__SHIFT 0x0
+#define SCLK_MIN_DIV__INTV_MASK 0x7f000
+#define SCLK_MIN_DIV__INTV__SHIFT 0xc
+#define LCAC_SX0_CNTL__SX0_ENABLE_MASK 0x1
+#define LCAC_SX0_CNTL__SX0_ENABLE__SHIFT 0x0
+#define LCAC_SX0_CNTL__SX0_THRESHOLD_MASK 0x1fffe
+#define LCAC_SX0_CNTL__SX0_THRESHOLD__SHIFT 0x1
+#define LCAC_SX0_CNTL__SX0_BLOCK_ID_MASK 0x3e0000
+#define LCAC_SX0_CNTL__SX0_BLOCK_ID__SHIFT 0x11
+#define LCAC_SX0_CNTL__SX0_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_SX0_CNTL__SX0_SIGNAL_ID__SHIFT 0x16
+#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL_MASK 0xffffffff
+#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL__SHIFT 0x0
+#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL_MASK 0xffffffff
+#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL__SHIFT 0x0
+#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1
+#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0
+#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1
+#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0
+#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0
+#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1
+#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0
+#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1
+#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0
+#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0
+#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1
+#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0
+#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1
+#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0
+#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0
+#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1
+#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0
+#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1
+#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0
+#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0
+#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1
+#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0
+#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe
+#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1
+#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000
+#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11
+#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16
+#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff
+#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0
+#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff
+#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0
+
+#endif /* SMU_7_0_0_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h
new file mode 100644
index 000000000000..f9fd2ea4625b
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_d.h
@@ -0,0 +1,1314 @@
+/*
+ * SMU_7_0_1 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef SMU_7_0_1_D_H
+#define SMU_7_0_1_D_H
+
+#define mmGCK_SMC_IND_INDEX 0x80
+#define mmGCK0_GCK_SMC_IND_INDEX 0x80
+#define mmGCK1_GCK_SMC_IND_INDEX 0x82
+#define mmGCK2_GCK_SMC_IND_INDEX 0x84
+#define mmGCK3_GCK_SMC_IND_INDEX 0x86
+#define mmGCK_SMC_IND_DATA 0x81
+#define mmGCK0_GCK_SMC_IND_DATA 0x81
+#define mmGCK1_GCK_SMC_IND_DATA 0x83
+#define mmGCK2_GCK_SMC_IND_DATA 0x85
+#define mmGCK3_GCK_SMC_IND_DATA 0x87
+#define ixCG_DCLK_CNTL 0xc050009c
+#define ixCG_DCLK_STATUS 0xc05000a0
+#define ixCG_VCLK_CNTL 0xc05000a4
+#define ixCG_VCLK_STATUS 0xc05000a8
+#define ixCG_ECLK_CNTL 0xc05000ac
+#define ixCG_ECLK_STATUS 0xc05000b0
+#define ixCG_ACLK_CNTL 0xc05000dc
+#define ixGCK_DFS_BYPASS_CNTL 0xc0500118
+#define ixCG_SPLL_FUNC_CNTL 0xc0500140
+#define ixCG_SPLL_FUNC_CNTL_2 0xc0500144
+#define ixCG_SPLL_FUNC_CNTL_3 0xc0500148
+#define ixCG_SPLL_FUNC_CNTL_4 0xc050014c
+#define ixCG_SPLL_FUNC_CNTL_5 0xc0500150
+#define ixCG_SPLL_FUNC_CNTL_6 0xc0500154
+#define ixCG_SPLL_FUNC_CNTL_7 0xc0500158
+#define ixSPLL_CNTL_MODE 0xc0500160
+#define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164
+#define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168
+#define ixMPLL_BYPASSCLK_SEL 0xc050019c
+#define ixCG_CLKPIN_CNTL 0xc05001a0
+#define ixCG_CLKPIN_CNTL_2 0xc05001a4
+#define ixCG_CLKPIN_CNTL_DC 0xc0500204
+#define ixTHM_CLK_CNTL 0xc05001a8
+#define ixMISC_CLK_CTRL 0xc05001ac
+#define ixGCK_PLL_TEST_CNTL 0xc05001c0
+#define ixGCK_PLL_TEST_CNTL_2 0xc05001c4
+#define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8
+#define mmSMC_IND_INDEX 0x80
+#define mmSMC0_SMC_IND_INDEX 0x80
+#define mmSMC1_SMC_IND_INDEX 0x82
+#define mmSMC2_SMC_IND_INDEX 0x84
+#define mmSMC3_SMC_IND_INDEX 0x86
+#define mmSMC_IND_DATA 0x81
+#define mmSMC0_SMC_IND_DATA 0x81
+#define mmSMC1_SMC_IND_DATA 0x83
+#define mmSMC2_SMC_IND_DATA 0x85
+#define mmSMC3_SMC_IND_DATA 0x87
+#define mmSMC_IND_INDEX_0 0x80
+#define mmSMC_IND_DATA_0 0x81
+#define mmSMC_IND_INDEX_1 0x82
+#define mmSMC_IND_DATA_1 0x83
+#define mmSMC_IND_INDEX_2 0x84
+#define mmSMC_IND_DATA_2 0x85
+#define mmSMC_IND_INDEX_3 0x86
+#define mmSMC_IND_DATA_3 0x87
+#define mmSMC_IND_INDEX_4 0x88
+#define mmSMC_IND_DATA_4 0x89
+#define mmSMC_IND_INDEX_5 0x8a
+#define mmSMC_IND_DATA_5 0x8b
+#define mmSMC_IND_INDEX_6 0x8c
+#define mmSMC_IND_DATA_6 0x8d
+#define mmSMC_IND_INDEX_7 0x8e
+#define mmSMC_IND_DATA_7 0x8f
+#define mmSMC_IND_ACCESS_CNTL 0x90
+#define mmSMC_MESSAGE_0 0x94
+#define mmSMC_RESP_0 0x95
+#define mmSMC_MESSAGE_1 0x96
+#define mmSMC_RESP_1 0x97
+#define mmSMC_MESSAGE_2 0x98
+#define mmSMC_RESP_2 0x99
+#define mmSMC_MESSAGE_3 0x9a
+#define mmSMC_RESP_3 0x9b
+#define mmSMC_MESSAGE_4 0x9c
+#define mmSMC_RESP_4 0x9d
+#define mmSMC_MESSAGE_5 0x9e
+#define mmSMC_RESP_5 0x9f
+#define mmSMC_MESSAGE_6 0xa0
+#define mmSMC_RESP_6 0xa1
+#define mmSMC_MESSAGE_7 0xa2
+#define mmSMC_RESP_7 0xa3
+#define mmSMC_MSG_ARG_0 0xa4
+#define mmSMC_MSG_ARG_1 0xa5
+#define mmSMC_MSG_ARG_2 0xa6
+#define mmSMC_MSG_ARG_3 0xa7
+#define mmSMC_MSG_ARG_4 0xa8
+#define mmSMC_MSG_ARG_5 0xa9
+#define mmSMC_MSG_ARG_6 0xaa
+#define mmSMC_MSG_ARG_7 0xab
+#define mmSMC_MESSAGE_8 0xb5
+#define mmSMC_RESP_8 0xb6
+#define mmSMC_MESSAGE_9 0xb7
+#define mmSMC_RESP_9 0xb8
+#define mmSMC_MESSAGE_10 0xb9
+#define mmSMC_RESP_10 0xba
+#define mmSMC_MESSAGE_11 0xbb
+#define mmSMC_RESP_11 0xbc
+#define mmSMC_MSG_ARG_8 0xbd
+#define mmSMC_MSG_ARG_9 0xbe
+#define mmSMC_MSG_ARG_10 0xbf
+#define mmSMC_MSG_ARG_11 0x91
+#define ixSMC_SYSCON_RESET_CNTL 0x80000000
+#define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004
+#define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008
+#define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c
+#define ixSMC_SYSCON_MISC_CNTL 0x80000010
+#define ixSMC_SYSCON_MSG_ARG_0 0x80000068
+#define ixSMC_PC_C 0x80000370
+#define ixSMC_SCRATCH9 0x80000424
+#define mmGPIOPAD_SW_INT_STAT 0x180
+#define mmGPIOPAD_STRENGTH 0x181
+#define mmGPIOPAD_MASK 0x182
+#define mmGPIOPAD_A 0x183
+#define mmGPIOPAD_EN 0x184
+#define mmGPIOPAD_Y 0x185
+#define mmGPIOPAD_PINSTRAPS 0x186
+#define mmGPIOPAD_INT_STAT_EN 0x187
+#define mmGPIOPAD_INT_STAT 0x188
+#define mmGPIOPAD_INT_STAT_AK 0x189
+#define mmGPIOPAD_INT_EN 0x18a
+#define mmGPIOPAD_INT_TYPE 0x18b
+#define mmGPIOPAD_INT_POLARITY 0x18c
+#define mmGPIOPAD_EXTERN_TRIG_CNTL 0x18d
+#define mmGPIOPAD_RCVR_SEL 0x191
+#define mmGPIOPAD_PU_EN 0x192
+#define mmGPIOPAD_PD_EN 0x193
+#define mmCG_FPS_CNT 0x1a4
+#define mmSMU_SMC_IND_INDEX 0x80
+#define mmSMU0_SMU_SMC_IND_INDEX 0x80
+#define mmSMU1_SMU_SMC_IND_INDEX 0x82
+#define mmSMU2_SMU_SMC_IND_INDEX 0x84
+#define mmSMU3_SMU_SMC_IND_INDEX 0x86
+#define mmSMU_SMC_IND_DATA 0x81
+#define mmSMU0_SMU_SMC_IND_DATA 0x81
+#define mmSMU1_SMU_SMC_IND_DATA 0x83
+#define mmSMU2_SMU_SMC_IND_DATA 0x85
+#define mmSMU3_SMU_SMC_IND_DATA 0x87
+#define ixRCU_UC_EVENTS 0xc0000004
+#define ixRCU_MISC_CTRL 0xc0000010
+#define ixCC_RCU_FUSES 0xc00c0000
+#define ixCC_SMU_MISC_FUSES 0xc00c0004
+#define ixCC_SCLK_VID_FUSES 0xc00c0008
+#define ixCC_GIO_IOCCFG_FUSES 0xc00c000c
+#define ixCC_GIO_IOC_FUSES 0xc00c0010
+#define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c
+#define ixCC_TST_ID_STRAPS 0xc00c0020
+#define ixCC_FCTRL_FUSES 0xc00c0024
+#define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020
+#define ixSMU_STATUS 0xe0003088
+#define ixSMU_FIRMWARE 0xe00030a4
+#define ixSMU_INPUT_DATA 0xe00030b8
+#define ixSMU_EFUSE_0 0xc0100000
+#define ixDPM_TABLE_1 0x3f000
+#define ixDPM_TABLE_2 0x3f004
+#define ixDPM_TABLE_3 0x3f008
+#define ixDPM_TABLE_4 0x3f00c
+#define ixDPM_TABLE_5 0x3f010
+#define ixDPM_TABLE_6 0x3f014
+#define ixDPM_TABLE_7 0x3f018
+#define ixDPM_TABLE_8 0x3f01c
+#define ixDPM_TABLE_9 0x3f020
+#define ixDPM_TABLE_10 0x3f024
+#define ixDPM_TABLE_11 0x3f028
+#define ixDPM_TABLE_12 0x3f02c
+#define ixDPM_TABLE_13 0x3f030
+#define ixDPM_TABLE_14 0x3f034
+#define ixDPM_TABLE_15 0x3f038
+#define ixDPM_TABLE_16 0x3f03c
+#define ixDPM_TABLE_17 0x3f040
+#define ixDPM_TABLE_18 0x3f044
+#define ixDPM_TABLE_19 0x3f048
+#define ixDPM_TABLE_20 0x3f04c
+#define ixDPM_TABLE_21 0x3f050
+#define ixDPM_TABLE_22 0x3f054
+#define ixDPM_TABLE_23 0x3f058
+#define ixDPM_TABLE_24 0x3f05c
+#define ixDPM_TABLE_25 0x3f060
+#define ixDPM_TABLE_26 0x3f064
+#define ixDPM_TABLE_27 0x3f068
+#define ixDPM_TABLE_28 0x3f06c
+#define ixDPM_TABLE_29 0x3f070
+#define ixDPM_TABLE_30 0x3f074
+#define ixDPM_TABLE_31 0x3f078
+#define ixDPM_TABLE_32 0x3f07c
+#define ixDPM_TABLE_33 0x3f080
+#define ixDPM_TABLE_34 0x3f084
+#define ixDPM_TABLE_35 0x3f088
+#define ixDPM_TABLE_36 0x3f08c
+#define ixDPM_TABLE_37 0x3f090
+#define ixDPM_TABLE_38 0x3f094
+#define ixDPM_TABLE_39 0x3f098
+#define ixDPM_TABLE_40 0x3f09c
+#define ixDPM_TABLE_41 0x3f0a0
+#define ixDPM_TABLE_42 0x3f0a4
+#define ixDPM_TABLE_43 0x3f0a8
+#define ixDPM_TABLE_44 0x3f0ac
+#define ixDPM_TABLE_45 0x3f0b0
+#define ixDPM_TABLE_46 0x3f0b4
+#define ixDPM_TABLE_47 0x3f0b8
+#define ixDPM_TABLE_48 0x3f0bc
+#define ixDPM_TABLE_49 0x3f0c0
+#define ixDPM_TABLE_50 0x3f0c4
+#define ixDPM_TABLE_51 0x3f0c8
+#define ixDPM_TABLE_52 0x3f0cc
+#define ixDPM_TABLE_53 0x3f0d0
+#define ixDPM_TABLE_54 0x3f0d4
+#define ixDPM_TABLE_55 0x3f0d8
+#define ixDPM_TABLE_56 0x3f0dc
+#define ixDPM_TABLE_57 0x3f0e0
+#define ixDPM_TABLE_58 0x3f0e4
+#define ixDPM_TABLE_59 0x3f0e8
+#define ixDPM_TABLE_60 0x3f0ec
+#define ixDPM_TABLE_61 0x3f0f0
+#define ixDPM_TABLE_62 0x3f0f4
+#define ixDPM_TABLE_63 0x3f0f8
+#define ixDPM_TABLE_64 0x3f0fc
+#define ixDPM_TABLE_65 0x3f100
+#define ixDPM_TABLE_66 0x3f104
+#define ixDPM_TABLE_67 0x3f108
+#define ixDPM_TABLE_68 0x3f10c
+#define ixDPM_TABLE_69 0x3f110
+#define ixDPM_TABLE_70 0x3f114
+#define ixDPM_TABLE_71 0x3f118
+#define ixDPM_TABLE_72 0x3f11c
+#define ixDPM_TABLE_73 0x3f120
+#define ixDPM_TABLE_74 0x3f124
+#define ixDPM_TABLE_75 0x3f128
+#define ixDPM_TABLE_76 0x3f12c
+#define ixDPM_TABLE_77 0x3f130
+#define ixDPM_TABLE_78 0x3f134
+#define ixDPM_TABLE_79 0x3f138
+#define ixDPM_TABLE_80 0x3f13c
+#define ixDPM_TABLE_81 0x3f140
+#define ixDPM_TABLE_82 0x3f144
+#define ixDPM_TABLE_83 0x3f148
+#define ixDPM_TABLE_84 0x3f14c
+#define ixDPM_TABLE_85 0x3f150
+#define ixDPM_TABLE_86 0x3f154
+#define ixDPM_TABLE_87 0x3f158
+#define ixDPM_TABLE_88 0x3f15c
+#define ixDPM_TABLE_89 0x3f160
+#define ixDPM_TABLE_90 0x3f164
+#define ixDPM_TABLE_91 0x3f168
+#define ixDPM_TABLE_92 0x3f16c
+#define ixDPM_TABLE_93 0x3f170
+#define ixDPM_TABLE_94 0x3f174
+#define ixDPM_TABLE_95 0x3f178
+#define ixDPM_TABLE_96 0x3f17c
+#define ixDPM_TABLE_97 0x3f180
+#define ixDPM_TABLE_98 0x3f184
+#define ixDPM_TABLE_99 0x3f188
+#define ixDPM_TABLE_100 0x3f18c
+#define ixDPM_TABLE_101 0x3f190
+#define ixDPM_TABLE_102 0x3f194
+#define ixDPM_TABLE_103 0x3f198
+#define ixDPM_TABLE_104 0x3f19c
+#define ixDPM_TABLE_105 0x3f1a0
+#define ixDPM_TABLE_106 0x3f1a4
+#define ixDPM_TABLE_107 0x3f1a8
+#define ixDPM_TABLE_108 0x3f1ac
+#define ixDPM_TABLE_109 0x3f1b0
+#define ixDPM_TABLE_110 0x3f1b4
+#define ixDPM_TABLE_111 0x3f1b8
+#define ixDPM_TABLE_112 0x3f1bc
+#define ixDPM_TABLE_113 0x3f1c0
+#define ixDPM_TABLE_114 0x3f1c4
+#define ixDPM_TABLE_115 0x3f1c8
+#define ixDPM_TABLE_116 0x3f1cc
+#define ixDPM_TABLE_117 0x3f1d0
+#define ixDPM_TABLE_118 0x3f1d4
+#define ixDPM_TABLE_119 0x3f1d8
+#define ixDPM_TABLE_120 0x3f1dc
+#define ixDPM_TABLE_121 0x3f1e0
+#define ixDPM_TABLE_122 0x3f1e4
+#define ixDPM_TABLE_123 0x3f1e8
+#define ixDPM_TABLE_124 0x3f1ec
+#define ixDPM_TABLE_125 0x3f1f0
+#define ixDPM_TABLE_126 0x3f1f4
+#define ixDPM_TABLE_127 0x3f1f8
+#define ixDPM_TABLE_128 0x3f1fc
+#define ixDPM_TABLE_129 0x3f200
+#define ixDPM_TABLE_130 0x3f204
+#define ixDPM_TABLE_131 0x3f208
+#define ixDPM_TABLE_132 0x3f20c
+#define ixDPM_TABLE_133 0x3f210
+#define ixDPM_TABLE_134 0x3f214
+#define ixDPM_TABLE_135 0x3f218
+#define ixDPM_TABLE_136 0x3f21c
+#define ixDPM_TABLE_137 0x3f220
+#define ixDPM_TABLE_138 0x3f224
+#define ixDPM_TABLE_139 0x3f228
+#define ixDPM_TABLE_140 0x3f22c
+#define ixDPM_TABLE_141 0x3f230
+#define ixDPM_TABLE_142 0x3f234
+#define ixDPM_TABLE_143 0x3f238
+#define ixDPM_TABLE_144 0x3f23c
+#define ixDPM_TABLE_145 0x3f240
+#define ixDPM_TABLE_146 0x3f244
+#define ixDPM_TABLE_147 0x3f248
+#define ixDPM_TABLE_148 0x3f24c
+#define ixDPM_TABLE_149 0x3f250
+#define ixDPM_TABLE_150 0x3f254
+#define ixDPM_TABLE_151 0x3f258
+#define ixDPM_TABLE_152 0x3f25c
+#define ixDPM_TABLE_153 0x3f260
+#define ixDPM_TABLE_154 0x3f264
+#define ixDPM_TABLE_155 0x3f268
+#define ixDPM_TABLE_156 0x3f26c
+#define ixDPM_TABLE_157 0x3f270
+#define ixDPM_TABLE_158 0x3f274
+#define ixDPM_TABLE_159 0x3f278
+#define ixDPM_TABLE_160 0x3f27c
+#define ixDPM_TABLE_161 0x3f280
+#define ixDPM_TABLE_162 0x3f284
+#define ixDPM_TABLE_163 0x3f288
+#define ixDPM_TABLE_164 0x3f28c
+#define ixDPM_TABLE_165 0x3f290
+#define ixDPM_TABLE_166 0x3f294
+#define ixDPM_TABLE_167 0x3f298
+#define ixDPM_TABLE_168 0x3f29c
+#define ixDPM_TABLE_169 0x3f2a0
+#define ixDPM_TABLE_170 0x3f2a4
+#define ixDPM_TABLE_171 0x3f2a8
+#define ixDPM_TABLE_172 0x3f2ac
+#define ixDPM_TABLE_173 0x3f2b0
+#define ixDPM_TABLE_174 0x3f2b4
+#define ixDPM_TABLE_175 0x3f2b8
+#define ixDPM_TABLE_176 0x3f2bc
+#define ixDPM_TABLE_177 0x3f2c0
+#define ixDPM_TABLE_178 0x3f2c4
+#define ixDPM_TABLE_179 0x3f2c8
+#define ixDPM_TABLE_180 0x3f2cc
+#define ixDPM_TABLE_181 0x3f2d0
+#define ixDPM_TABLE_182 0x3f2d4
+#define ixDPM_TABLE_183 0x3f2d8
+#define ixDPM_TABLE_184 0x3f2dc
+#define ixDPM_TABLE_185 0x3f2e0
+#define ixDPM_TABLE_186 0x3f2e4
+#define ixDPM_TABLE_187 0x3f2e8
+#define ixDPM_TABLE_188 0x3f2ec
+#define ixDPM_TABLE_189 0x3f2f0
+#define ixDPM_TABLE_190 0x3f2f4
+#define ixDPM_TABLE_191 0x3f2f8
+#define ixDPM_TABLE_192 0x3f2fc
+#define ixDPM_TABLE_193 0x3f300
+#define ixDPM_TABLE_194 0x3f304
+#define ixDPM_TABLE_195 0x3f308
+#define ixDPM_TABLE_196 0x3f30c
+#define ixDPM_TABLE_197 0x3f310
+#define ixDPM_TABLE_198 0x3f314
+#define ixDPM_TABLE_199 0x3f318
+#define ixDPM_TABLE_200 0x3f31c
+#define ixDPM_TABLE_201 0x3f320
+#define ixDPM_TABLE_202 0x3f324
+#define ixDPM_TABLE_203 0x3f328
+#define ixDPM_TABLE_204 0x3f32c
+#define ixDPM_TABLE_205 0x3f330
+#define ixDPM_TABLE_206 0x3f334
+#define ixDPM_TABLE_207 0x3f338
+#define ixDPM_TABLE_208 0x3f33c
+#define ixDPM_TABLE_209 0x3f340
+#define ixDPM_TABLE_210 0x3f344
+#define ixDPM_TABLE_211 0x3f348
+#define ixDPM_TABLE_212 0x3f34c
+#define ixDPM_TABLE_213 0x3f350
+#define ixDPM_TABLE_214 0x3f354
+#define ixDPM_TABLE_215 0x3f358
+#define ixDPM_TABLE_216 0x3f35c
+#define ixDPM_TABLE_217 0x3f360
+#define ixDPM_TABLE_218 0x3f364
+#define ixDPM_TABLE_219 0x3f368
+#define ixDPM_TABLE_220 0x3f36c
+#define ixDPM_TABLE_221 0x3f370
+#define ixDPM_TABLE_222 0x3f374
+#define ixDPM_TABLE_223 0x3f378
+#define ixDPM_TABLE_224 0x3f37c
+#define ixDPM_TABLE_225 0x3f380
+#define ixDPM_TABLE_226 0x3f384
+#define ixDPM_TABLE_227 0x3f388
+#define ixDPM_TABLE_228 0x3f38c
+#define ixDPM_TABLE_229 0x3f390
+#define ixDPM_TABLE_230 0x3f394
+#define ixDPM_TABLE_231 0x3f398
+#define ixDPM_TABLE_232 0x3f39c
+#define ixDPM_TABLE_233 0x3f3a0
+#define ixDPM_TABLE_234 0x3f3a4
+#define ixDPM_TABLE_235 0x3f3a8
+#define ixDPM_TABLE_236 0x3f3ac
+#define ixDPM_TABLE_237 0x3f3b0
+#define ixDPM_TABLE_238 0x3f3b4
+#define ixDPM_TABLE_239 0x3f3b8
+#define ixDPM_TABLE_240 0x3f3bc
+#define ixDPM_TABLE_241 0x3f3c0
+#define ixDPM_TABLE_242 0x3f3c4
+#define ixDPM_TABLE_243 0x3f3c8
+#define ixDPM_TABLE_244 0x3f3cc
+#define ixDPM_TABLE_245 0x3f3d0
+#define ixDPM_TABLE_246 0x3f3d4
+#define ixDPM_TABLE_247 0x3f3d8
+#define ixDPM_TABLE_248 0x3f3dc
+#define ixDPM_TABLE_249 0x3f3e0
+#define ixDPM_TABLE_250 0x3f3e4
+#define ixDPM_TABLE_251 0x3f3e8
+#define ixDPM_TABLE_252 0x3f3ec
+#define ixDPM_TABLE_253 0x3f3f0
+#define ixDPM_TABLE_254 0x3f3f4
+#define ixDPM_TABLE_255 0x3f3f8
+#define ixDPM_TABLE_256 0x3f3fc
+#define ixDPM_TABLE_257 0x3f400
+#define ixDPM_TABLE_258 0x3f404
+#define ixDPM_TABLE_259 0x3f408
+#define ixDPM_TABLE_260 0x3f40c
+#define ixDPM_TABLE_261 0x3f410
+#define ixDPM_TABLE_262 0x3f414
+#define ixDPM_TABLE_263 0x3f418
+#define ixDPM_TABLE_264 0x3f41c
+#define ixDPM_TABLE_265 0x3f420
+#define ixDPM_TABLE_266 0x3f424
+#define ixDPM_TABLE_267 0x3f428
+#define ixDPM_TABLE_268 0x3f42c
+#define ixDPM_TABLE_269 0x3f430
+#define ixDPM_TABLE_270 0x3f434
+#define ixDPM_TABLE_271 0x3f438
+#define ixDPM_TABLE_272 0x3f43c
+#define ixDPM_TABLE_273 0x3f440
+#define ixDPM_TABLE_274 0x3f444
+#define ixDPM_TABLE_275 0x3f448
+#define ixDPM_TABLE_276 0x3f44c
+#define ixDPM_TABLE_277 0x3f450
+#define ixDPM_TABLE_278 0x3f454
+#define ixDPM_TABLE_279 0x3f458
+#define ixDPM_TABLE_280 0x3f45c
+#define ixDPM_TABLE_281 0x3f460
+#define ixDPM_TABLE_282 0x3f464
+#define ixDPM_TABLE_283 0x3f468
+#define ixDPM_TABLE_284 0x3f46c
+#define ixDPM_TABLE_285 0x3f470
+#define ixDPM_TABLE_286 0x3f474
+#define ixDPM_TABLE_287 0x3f478
+#define ixDPM_TABLE_288 0x3f47c
+#define ixDPM_TABLE_289 0x3f480
+#define ixDPM_TABLE_290 0x3f484
+#define ixDPM_TABLE_291 0x3f488
+#define ixDPM_TABLE_292 0x3f48c
+#define ixDPM_TABLE_293 0x3f490
+#define ixDPM_TABLE_294 0x3f494
+#define ixDPM_TABLE_295 0x3f498
+#define ixDPM_TABLE_296 0x3f49c
+#define ixDPM_TABLE_297 0x3f4a0
+#define ixDPM_TABLE_298 0x3f4a4
+#define ixDPM_TABLE_299 0x3f4a8
+#define ixDPM_TABLE_300 0x3f4ac
+#define ixDPM_TABLE_301 0x3f4b0
+#define ixDPM_TABLE_302 0x3f4b4
+#define ixDPM_TABLE_303 0x3f4b8
+#define ixDPM_TABLE_304 0x3f4bc
+#define ixDPM_TABLE_305 0x3f4c0
+#define ixDPM_TABLE_306 0x3f4c4
+#define ixDPM_TABLE_307 0x3f4c8
+#define ixDPM_TABLE_308 0x3f4cc
+#define ixDPM_TABLE_309 0x3f4d0
+#define ixDPM_TABLE_310 0x3f4d4
+#define ixDPM_TABLE_311 0x3f4d8
+#define ixDPM_TABLE_312 0x3f4dc
+#define ixDPM_TABLE_313 0x3f4e0
+#define ixDPM_TABLE_314 0x3f4e4
+#define ixDPM_TABLE_315 0x3f4e8
+#define ixDPM_TABLE_316 0x3f4ec
+#define ixDPM_TABLE_317 0x3f4f0
+#define ixDPM_TABLE_318 0x3f4f4
+#define ixDPM_TABLE_319 0x3f4f8
+#define ixDPM_TABLE_320 0x3f4fc
+#define ixDPM_TABLE_321 0x3f500
+#define ixDPM_TABLE_322 0x3f504
+#define ixDPM_TABLE_323 0x3f508
+#define ixDPM_TABLE_324 0x3f50c
+#define ixDPM_TABLE_325 0x3f510
+#define ixDPM_TABLE_326 0x3f514
+#define ixDPM_TABLE_327 0x3f518
+#define ixDPM_TABLE_328 0x3f51c
+#define ixDPM_TABLE_329 0x3f520
+#define ixDPM_TABLE_330 0x3f524
+#define ixDPM_TABLE_331 0x3f528
+#define ixDPM_TABLE_332 0x3f52c
+#define ixDPM_TABLE_333 0x3f530
+#define ixDPM_TABLE_334 0x3f534
+#define ixDPM_TABLE_335 0x3f538
+#define ixDPM_TABLE_336 0x3f53c
+#define ixDPM_TABLE_337 0x3f540
+#define ixDPM_TABLE_338 0x3f544
+#define ixDPM_TABLE_339 0x3f548
+#define ixDPM_TABLE_340 0x3f54c
+#define ixDPM_TABLE_341 0x3f550
+#define ixDPM_TABLE_342 0x3f554
+#define ixDPM_TABLE_343 0x3f558
+#define ixDPM_TABLE_344 0x3f55c
+#define ixDPM_TABLE_345 0x3f560
+#define ixDPM_TABLE_346 0x3f564
+#define ixDPM_TABLE_347 0x3f568
+#define ixDPM_TABLE_348 0x3f56c
+#define ixDPM_TABLE_349 0x3f570
+#define ixDPM_TABLE_350 0x3f574
+#define ixDPM_TABLE_351 0x3f578
+#define ixDPM_TABLE_352 0x3f57c
+#define ixDPM_TABLE_353 0x3f580
+#define ixDPM_TABLE_354 0x3f584
+#define ixDPM_TABLE_355 0x3f588
+#define ixDPM_TABLE_356 0x3f58c
+#define ixDPM_TABLE_357 0x3f590
+#define ixDPM_TABLE_358 0x3f594
+#define ixDPM_TABLE_359 0x3f598
+#define ixDPM_TABLE_360 0x3f59c
+#define ixDPM_TABLE_361 0x3f5a0
+#define ixDPM_TABLE_362 0x3f5a4
+#define ixDPM_TABLE_363 0x3f5a8
+#define ixDPM_TABLE_364 0x3f5ac
+#define ixDPM_TABLE_365 0x3f5b0
+#define ixDPM_TABLE_366 0x3f5b4
+#define ixDPM_TABLE_367 0x3f5b8
+#define ixDPM_TABLE_368 0x3f5bc
+#define ixDPM_TABLE_369 0x3f5c0
+#define ixDPM_TABLE_370 0x3f5c4
+#define ixDPM_TABLE_371 0x3f5c8
+#define ixDPM_TABLE_372 0x3f5cc
+#define ixDPM_TABLE_373 0x3f5d0
+#define ixDPM_TABLE_374 0x3f5d4
+#define ixDPM_TABLE_375 0x3f5d8
+#define ixDPM_TABLE_376 0x3f5dc
+#define ixDPM_TABLE_377 0x3f5e0
+#define ixDPM_TABLE_378 0x3f5e4
+#define ixDPM_TABLE_379 0x3f5e8
+#define ixDPM_TABLE_380 0x3f5ec
+#define ixDPM_TABLE_381 0x3f5f0
+#define ixDPM_TABLE_382 0x3f5f4
+#define ixDPM_TABLE_383 0x3f5f8
+#define ixDPM_TABLE_384 0x3f5fc
+#define ixDPM_TABLE_385 0x3f600
+#define ixDPM_TABLE_386 0x3f604
+#define ixDPM_TABLE_387 0x3f608
+#define ixDPM_TABLE_388 0x3f60c
+#define ixDPM_TABLE_389 0x3f610
+#define ixDPM_TABLE_390 0x3f614
+#define ixDPM_TABLE_391 0x3f618
+#define ixDPM_TABLE_392 0x3f61c
+#define ixDPM_TABLE_393 0x3f620
+#define ixDPM_TABLE_394 0x3f624
+#define ixDPM_TABLE_395 0x3f628
+#define ixDPM_TABLE_396 0x3f62c
+#define ixDPM_TABLE_397 0x3f630
+#define ixDPM_TABLE_398 0x3f634
+#define ixDPM_TABLE_399 0x3f638
+#define ixDPM_TABLE_400 0x3f63c
+#define ixDPM_TABLE_401 0x3f640
+#define ixDPM_TABLE_402 0x3f644
+#define ixDPM_TABLE_403 0x3f648
+#define ixDPM_TABLE_404 0x3f64c
+#define ixDPM_TABLE_405 0x3f650
+#define ixDPM_TABLE_406 0x3f654
+#define ixDPM_TABLE_407 0x3f658
+#define ixDPM_TABLE_408 0x3f65c
+#define ixDPM_TABLE_409 0x3f660
+#define ixDPM_TABLE_410 0x3f664
+#define ixDPM_TABLE_411 0x3f668
+#define ixDPM_TABLE_412 0x3f66c
+#define ixDPM_TABLE_413 0x3f670
+#define ixDPM_TABLE_414 0x3f674
+#define ixDPM_TABLE_415 0x3f678
+#define ixDPM_TABLE_416 0x3f67c
+#define ixDPM_TABLE_417 0x3f680
+#define ixDPM_TABLE_418 0x3f684
+#define ixDPM_TABLE_419 0x3f688
+#define ixDPM_TABLE_420 0x3f68c
+#define ixDPM_TABLE_421 0x3f690
+#define ixDPM_TABLE_422 0x3f694
+#define ixDPM_TABLE_423 0x3f698
+#define ixDPM_TABLE_424 0x3f69c
+#define ixDPM_TABLE_425 0x3f6a0
+#define ixDPM_TABLE_426 0x3f6a4
+#define ixDPM_TABLE_427 0x3f6a8
+#define ixDPM_TABLE_428 0x3f6ac
+#define ixDPM_TABLE_429 0x3f6b0
+#define ixDPM_TABLE_430 0x3f6b4
+#define ixDPM_TABLE_431 0x3f6b8
+#define ixDPM_TABLE_432 0x3f6bc
+#define ixDPM_TABLE_433 0x3f6c0
+#define ixDPM_TABLE_434 0x3f6c4
+#define ixDPM_TABLE_435 0x3f6c8
+#define ixDPM_TABLE_436 0x3f6cc
+#define ixDPM_TABLE_437 0x3f6d0
+#define ixDPM_TABLE_438 0x3f6d4
+#define ixDPM_TABLE_439 0x3f6d8
+#define ixDPM_TABLE_440 0x3f6dc
+#define ixDPM_TABLE_441 0x3f6e0
+#define ixDPM_TABLE_442 0x3f6e4
+#define ixDPM_TABLE_443 0x3f6e8
+#define ixDPM_TABLE_444 0x3f6ec
+#define ixDPM_TABLE_445 0x3f6f0
+#define ixDPM_TABLE_446 0x3f6f4
+#define ixDPM_TABLE_447 0x3f6f8
+#define ixDPM_TABLE_448 0x3f6fc
+#define ixDPM_TABLE_449 0x3f700
+#define ixDPM_TABLE_450 0x3f704
+#define ixDPM_TABLE_451 0x3f708
+#define ixDPM_TABLE_452 0x3f70c
+#define ixDPM_TABLE_453 0x3f710
+#define ixDPM_TABLE_454 0x3f714
+#define ixDPM_TABLE_455 0x3f718
+#define ixDPM_TABLE_456 0x3f71c
+#define ixDPM_TABLE_457 0x3f720
+#define ixDPM_TABLE_458 0x3f724
+#define ixDPM_TABLE_459 0x3f728
+#define ixDPM_TABLE_460 0x3f72c
+#define ixDPM_TABLE_461 0x3f730
+#define ixDPM_TABLE_462 0x3f734
+#define ixDPM_TABLE_463 0x3f738
+#define ixDPM_TABLE_464 0x3f73c
+#define ixDPM_TABLE_465 0x3f740
+#define ixDPM_TABLE_466 0x3f744
+#define ixDPM_TABLE_467 0x3f748
+#define ixDPM_TABLE_468 0x3f74c
+#define ixDPM_TABLE_469 0x3f750
+#define ixDPM_TABLE_470 0x3f754
+#define ixDPM_TABLE_471 0x3f758
+#define ixDPM_TABLE_472 0x3f75c
+#define ixDPM_TABLE_473 0x3f760
+#define ixDPM_TABLE_474 0x3f764
+#define ixDPM_TABLE_475 0x3f768
+#define ixDPM_TABLE_476 0x3f76c
+#define ixDPM_TABLE_477 0x3f770
+#define ixDPM_TABLE_478 0x3f774
+#define ixDPM_TABLE_479 0x3f778
+#define ixDPM_TABLE_480 0x3f77c
+#define ixDPM_TABLE_481 0x3f780
+#define ixDPM_TABLE_482 0x3f784
+#define ixDPM_TABLE_483 0x3f788
+#define ixDPM_TABLE_484 0x3f78c
+#define ixDPM_TABLE_485 0x3f790
+#define ixDPM_TABLE_486 0x3f794
+#define ixDPM_TABLE_487 0x3f798
+#define ixDPM_TABLE_488 0x3f79c
+#define ixDPM_TABLE_489 0x3f7a0
+#define ixDPM_TABLE_490 0x3f7a4
+#define ixDPM_TABLE_491 0x3f7a8
+#define ixDPM_TABLE_492 0x3f7ac
+#define ixDPM_TABLE_493 0x3f7b0
+#define ixDPM_TABLE_494 0x3f7b4
+#define ixDPM_TABLE_495 0x3f7b8
+#define ixDPM_TABLE_496 0x3f7bc
+#define ixDPM_TABLE_497 0x3f7c0
+#define ixDPM_TABLE_498 0x3f7c4
+#define ixDPM_TABLE_499 0x3f7c8
+#define ixDPM_TABLE_500 0x3f7cc
+#define ixDPM_TABLE_501 0x3f7d0
+#define ixDPM_TABLE_502 0x3f7d4
+#define ixDPM_TABLE_503 0x3f7d8
+#define ixDPM_TABLE_504 0x3f7dc
+#define ixDPM_TABLE_505 0x3f7e0
+#define ixDPM_TABLE_506 0x3f7e4
+#define ixDPM_TABLE_507 0x3f7e8
+#define ixDPM_TABLE_508 0x3f7ec
+#define ixDPM_TABLE_509 0x3f7f0
+#define ixDPM_TABLE_510 0x3f7f4
+#define ixFIRMWARE_FLAGS 0x3f800
+#define ixTDC_STATUS 0x3f808
+#define ixTDC_MV_AVERAGE 0x3f80c
+#define ixTDC_VRM_LIMIT 0x3f810
+#define ixFEATURE_STATUS 0x3f818
+#define ixENTITY_TEMPERATURES_1 0x3f81c
+#define ixMCARB_DRAM_TIMING_TABLE_1 0x3f900
+#define ixMCARB_DRAM_TIMING_TABLE_2 0x3f904
+#define ixMCARB_DRAM_TIMING_TABLE_3 0x3f908
+#define ixMCARB_DRAM_TIMING_TABLE_4 0x3f90c
+#define ixMCARB_DRAM_TIMING_TABLE_5 0x3f910
+#define ixMCARB_DRAM_TIMING_TABLE_6 0x3f914
+#define ixMCARB_DRAM_TIMING_TABLE_7 0x3f918
+#define ixMCARB_DRAM_TIMING_TABLE_8 0x3f91c
+#define ixMCARB_DRAM_TIMING_TABLE_9 0x3f920
+#define ixMCARB_DRAM_TIMING_TABLE_10 0x3f924
+#define ixMCARB_DRAM_TIMING_TABLE_11 0x3f928
+#define ixMCARB_DRAM_TIMING_TABLE_12 0x3f92c
+#define ixMCARB_DRAM_TIMING_TABLE_13 0x3f930
+#define ixMCARB_DRAM_TIMING_TABLE_14 0x3f934
+#define ixMCARB_DRAM_TIMING_TABLE_15 0x3f938
+#define ixMCARB_DRAM_TIMING_TABLE_16 0x3f93c
+#define ixMCARB_DRAM_TIMING_TABLE_17 0x3f940
+#define ixMCARB_DRAM_TIMING_TABLE_18 0x3f944
+#define ixMCARB_DRAM_TIMING_TABLE_19 0x3f948
+#define ixMCARB_DRAM_TIMING_TABLE_20 0x3f94c
+#define ixMCARB_DRAM_TIMING_TABLE_21 0x3f950
+#define ixMCARB_DRAM_TIMING_TABLE_22 0x3f954
+#define ixMCARB_DRAM_TIMING_TABLE_23 0x3f958
+#define ixMCARB_DRAM_TIMING_TABLE_24 0x3f95c
+#define ixMCARB_DRAM_TIMING_TABLE_25 0x3f960
+#define ixMCARB_DRAM_TIMING_TABLE_26 0x3f964
+#define ixMCARB_DRAM_TIMING_TABLE_27 0x3f968
+#define ixMCARB_DRAM_TIMING_TABLE_28 0x3f96c
+#define ixMCARB_DRAM_TIMING_TABLE_29 0x3f970
+#define ixMCARB_DRAM_TIMING_TABLE_30 0x3f974
+#define ixMCARB_DRAM_TIMING_TABLE_31 0x3f978
+#define ixMCARB_DRAM_TIMING_TABLE_32 0x3f97c
+#define ixMCARB_DRAM_TIMING_TABLE_33 0x3f980
+#define ixMCARB_DRAM_TIMING_TABLE_34 0x3f984
+#define ixMCARB_DRAM_TIMING_TABLE_35 0x3f988
+#define ixMCARB_DRAM_TIMING_TABLE_36 0x3f98c
+#define ixMCARB_DRAM_TIMING_TABLE_37 0x3f990
+#define ixMCARB_DRAM_TIMING_TABLE_38 0x3f994
+#define ixMCARB_DRAM_TIMING_TABLE_39 0x3f998
+#define ixMCARB_DRAM_TIMING_TABLE_40 0x3f99c
+#define ixMCARB_DRAM_TIMING_TABLE_41 0x3f9a0
+#define ixMCARB_DRAM_TIMING_TABLE_42 0x3f9a4
+#define ixMCARB_DRAM_TIMING_TABLE_43 0x3f9a8
+#define ixMCARB_DRAM_TIMING_TABLE_44 0x3f9ac
+#define ixMCARB_DRAM_TIMING_TABLE_45 0x3f9b0
+#define ixMCARB_DRAM_TIMING_TABLE_46 0x3f9b4
+#define ixMCARB_DRAM_TIMING_TABLE_47 0x3f9b8
+#define ixMCARB_DRAM_TIMING_TABLE_48 0x3f9bc
+#define ixMCARB_DRAM_TIMING_TABLE_49 0x3f9c0
+#define ixMCARB_DRAM_TIMING_TABLE_50 0x3f9c4
+#define ixMCARB_DRAM_TIMING_TABLE_51 0x3f9c8
+#define ixMCARB_DRAM_TIMING_TABLE_52 0x3f9cc
+#define ixMCARB_DRAM_TIMING_TABLE_53 0x3f9d0
+#define ixMCARB_DRAM_TIMING_TABLE_54 0x3f9d4
+#define ixMCARB_DRAM_TIMING_TABLE_55 0x3f9d8
+#define ixMCARB_DRAM_TIMING_TABLE_56 0x3f9dc
+#define ixMCARB_DRAM_TIMING_TABLE_57 0x3f9e0
+#define ixMCARB_DRAM_TIMING_TABLE_58 0x3f9e4
+#define ixMCARB_DRAM_TIMING_TABLE_59 0x3f9e8
+#define ixMCARB_DRAM_TIMING_TABLE_60 0x3f9ec
+#define ixMCARB_DRAM_TIMING_TABLE_61 0x3f9f0
+#define ixMCARB_DRAM_TIMING_TABLE_62 0x3f9f4
+#define ixMCARB_DRAM_TIMING_TABLE_63 0x3f9f8
+#define ixMCARB_DRAM_TIMING_TABLE_64 0x3f9fc
+#define ixMCARB_DRAM_TIMING_TABLE_65 0x3fa00
+#define ixMCARB_DRAM_TIMING_TABLE_66 0x3fa04
+#define ixMCARB_DRAM_TIMING_TABLE_67 0x3fa08
+#define ixMCARB_DRAM_TIMING_TABLE_68 0x3fa0c
+#define ixMCARB_DRAM_TIMING_TABLE_69 0x3fa10
+#define ixMCARB_DRAM_TIMING_TABLE_70 0x3fa14
+#define ixMCARB_DRAM_TIMING_TABLE_71 0x3fa18
+#define ixMCARB_DRAM_TIMING_TABLE_72 0x3fa1c
+#define ixMCARB_DRAM_TIMING_TABLE_73 0x3fa20
+#define ixMCARB_DRAM_TIMING_TABLE_74 0x3fa24
+#define ixMCARB_DRAM_TIMING_TABLE_75 0x3fa28
+#define ixMCARB_DRAM_TIMING_TABLE_76 0x3fa2c
+#define ixMCARB_DRAM_TIMING_TABLE_77 0x3fa30
+#define ixMCARB_DRAM_TIMING_TABLE_78 0x3fa34
+#define ixMCARB_DRAM_TIMING_TABLE_79 0x3fa38
+#define ixMCARB_DRAM_TIMING_TABLE_80 0x3fa3c
+#define ixMCARB_DRAM_TIMING_TABLE_81 0x3fa40
+#define ixMCARB_DRAM_TIMING_TABLE_82 0x3fa44
+#define ixMCARB_DRAM_TIMING_TABLE_83 0x3fa48
+#define ixMCARB_DRAM_TIMING_TABLE_84 0x3fa4c
+#define ixMCARB_DRAM_TIMING_TABLE_85 0x3fa50
+#define ixMCARB_DRAM_TIMING_TABLE_86 0x3fa54
+#define ixMCARB_DRAM_TIMING_TABLE_87 0x3fa58
+#define ixMCARB_DRAM_TIMING_TABLE_88 0x3fa5c
+#define ixMCARB_DRAM_TIMING_TABLE_89 0x3fa60
+#define ixMCARB_DRAM_TIMING_TABLE_90 0x3fa64
+#define ixMCARB_DRAM_TIMING_TABLE_91 0x3fa68
+#define ixMCARB_DRAM_TIMING_TABLE_92 0x3fa6c
+#define ixMCARB_DRAM_TIMING_TABLE_93 0x3fa70
+#define ixMCARB_DRAM_TIMING_TABLE_94 0x3fa74
+#define ixMCARB_DRAM_TIMING_TABLE_95 0x3fa78
+#define ixMCARB_DRAM_TIMING_TABLE_96 0x3fa7c
+#define ixMCARB_DRAM_TIMING_TABLE_97 0x3fa80
+#define ixMCARB_DRAM_TIMING_TABLE_98 0x3fa84
+#define ixMCARB_DRAM_TIMING_TABLE_99 0x3fa88
+#define ixMCARB_DRAM_TIMING_TABLE_100 0x3fa8c
+#define ixMCARB_DRAM_TIMING_TABLE_101 0x3fa90
+#define ixMCARB_DRAM_TIMING_TABLE_102 0x3fa94
+#define ixMCARB_DRAM_TIMING_TABLE_103 0x3fa98
+#define ixMCARB_DRAM_TIMING_TABLE_104 0x3fa9c
+#define ixMCARB_DRAM_TIMING_TABLE_105 0x3faa0
+#define ixMCARB_DRAM_TIMING_TABLE_106 0x3faa4
+#define ixMCARB_DRAM_TIMING_TABLE_107 0x3faa8
+#define ixMCARB_DRAM_TIMING_TABLE_108 0x3faac
+#define ixMCARB_DRAM_TIMING_TABLE_109 0x3fab0
+#define ixMCARB_DRAM_TIMING_TABLE_110 0x3fab4
+#define ixMCARB_DRAM_TIMING_TABLE_111 0x3fab8
+#define ixMCARB_DRAM_TIMING_TABLE_112 0x3fabc
+#define ixMCARB_DRAM_TIMING_TABLE_113 0x3fac0
+#define ixMCARB_DRAM_TIMING_TABLE_114 0x3fac4
+#define ixMCARB_DRAM_TIMING_TABLE_115 0x3fac8
+#define ixMCARB_DRAM_TIMING_TABLE_116 0x3facc
+#define ixMCARB_DRAM_TIMING_TABLE_117 0x3fad0
+#define ixMCARB_DRAM_TIMING_TABLE_118 0x3fad4
+#define ixMCARB_DRAM_TIMING_TABLE_119 0x3fad8
+#define ixMCARB_DRAM_TIMING_TABLE_120 0x3fadc
+#define ixMCARB_DRAM_TIMING_TABLE_121 0x3fae0
+#define ixMCARB_DRAM_TIMING_TABLE_122 0x3fae4
+#define ixMCARB_DRAM_TIMING_TABLE_123 0x3fae8
+#define ixMCARB_DRAM_TIMING_TABLE_124 0x3faec
+#define ixMCARB_DRAM_TIMING_TABLE_125 0x3faf0
+#define ixMCARB_DRAM_TIMING_TABLE_126 0x3faf4
+#define ixMCARB_DRAM_TIMING_TABLE_127 0x3faf8
+#define ixMCARB_DRAM_TIMING_TABLE_128 0x3fafc
+#define ixMCARB_DRAM_TIMING_TABLE_129 0x3fb00
+#define ixMCARB_DRAM_TIMING_TABLE_130 0x3fb04
+#define ixMCARB_DRAM_TIMING_TABLE_131 0x3fb08
+#define ixMCARB_DRAM_TIMING_TABLE_132 0x3fb0c
+#define ixMCARB_DRAM_TIMING_TABLE_133 0x3fb10
+#define ixMCARB_DRAM_TIMING_TABLE_134 0x3fb14
+#define ixMCARB_DRAM_TIMING_TABLE_135 0x3fb18
+#define ixMCARB_DRAM_TIMING_TABLE_136 0x3fb1c
+#define ixMCARB_DRAM_TIMING_TABLE_137 0x3fb20
+#define ixMCARB_DRAM_TIMING_TABLE_138 0x3fb24
+#define ixMCARB_DRAM_TIMING_TABLE_139 0x3fb28
+#define ixMCARB_DRAM_TIMING_TABLE_140 0x3fb2c
+#define ixMCARB_DRAM_TIMING_TABLE_141 0x3fb30
+#define ixMCARB_DRAM_TIMING_TABLE_142 0x3fb34
+#define ixMCARB_DRAM_TIMING_TABLE_143 0x3fb38
+#define ixMCARB_DRAM_TIMING_TABLE_144 0x3fb3c
+#define ixMC_REGISTERS_TABLE_1 0x3fb40
+#define ixMC_REGISTERS_TABLE_2 0x3fb44
+#define ixMC_REGISTERS_TABLE_3 0x3fb48
+#define ixMC_REGISTERS_TABLE_4 0x3fb4c
+#define ixMC_REGISTERS_TABLE_5 0x3fb50
+#define ixMC_REGISTERS_TABLE_6 0x3fb54
+#define ixMC_REGISTERS_TABLE_7 0x3fb58
+#define ixMC_REGISTERS_TABLE_8 0x3fb5c
+#define ixMC_REGISTERS_TABLE_9 0x3fb60
+#define ixMC_REGISTERS_TABLE_10 0x3fb64
+#define ixMC_REGISTERS_TABLE_11 0x3fb68
+#define ixMC_REGISTERS_TABLE_12 0x3fb6c
+#define ixMC_REGISTERS_TABLE_13 0x3fb70
+#define ixMC_REGISTERS_TABLE_14 0x3fb74
+#define ixMC_REGISTERS_TABLE_15 0x3fb78
+#define ixMC_REGISTERS_TABLE_16 0x3fb7c
+#define ixMC_REGISTERS_TABLE_17 0x3fb80
+#define ixMC_REGISTERS_TABLE_18 0x3fb84
+#define ixMC_REGISTERS_TABLE_19 0x3fb88
+#define ixMC_REGISTERS_TABLE_20 0x3fb8c
+#define ixMC_REGISTERS_TABLE_21 0x3fb90
+#define ixMC_REGISTERS_TABLE_22 0x3fb94
+#define ixMC_REGISTERS_TABLE_23 0x3fb98
+#define ixMC_REGISTERS_TABLE_24 0x3fb9c
+#define ixMC_REGISTERS_TABLE_25 0x3fba0
+#define ixMC_REGISTERS_TABLE_26 0x3fba4
+#define ixMC_REGISTERS_TABLE_27 0x3fba8
+#define ixMC_REGISTERS_TABLE_28 0x3fbac
+#define ixMC_REGISTERS_TABLE_29 0x3fbb0
+#define ixMC_REGISTERS_TABLE_30 0x3fbb4
+#define ixMC_REGISTERS_TABLE_31 0x3fbb8
+#define ixMC_REGISTERS_TABLE_32 0x3fbbc
+#define ixMC_REGISTERS_TABLE_33 0x3fbc0
+#define ixMC_REGISTERS_TABLE_34 0x3fbc4
+#define ixMC_REGISTERS_TABLE_35 0x3fbc8
+#define ixMC_REGISTERS_TABLE_36 0x3fbcc
+#define ixMC_REGISTERS_TABLE_37 0x3fbd0
+#define ixMC_REGISTERS_TABLE_38 0x3fbd4
+#define ixMC_REGISTERS_TABLE_39 0x3fbd8
+#define ixMC_REGISTERS_TABLE_40 0x3fbdc
+#define ixMC_REGISTERS_TABLE_41 0x3fbe0
+#define ixMC_REGISTERS_TABLE_42 0x3fbe4
+#define ixMC_REGISTERS_TABLE_43 0x3fbe8
+#define ixMC_REGISTERS_TABLE_44 0x3fbec
+#define ixMC_REGISTERS_TABLE_45 0x3fbf0
+#define ixMC_REGISTERS_TABLE_46 0x3fbf4
+#define ixMC_REGISTERS_TABLE_47 0x3fbf8
+#define ixMC_REGISTERS_TABLE_48 0x3fbfc
+#define ixMC_REGISTERS_TABLE_49 0x3fc00
+#define ixMC_REGISTERS_TABLE_50 0x3fc04
+#define ixMC_REGISTERS_TABLE_51 0x3fc08
+#define ixMC_REGISTERS_TABLE_52 0x3fc0c
+#define ixMC_REGISTERS_TABLE_53 0x3fc10
+#define ixMC_REGISTERS_TABLE_54 0x3fc14
+#define ixMC_REGISTERS_TABLE_55 0x3fc18
+#define ixMC_REGISTERS_TABLE_56 0x3fc1c
+#define ixMC_REGISTERS_TABLE_57 0x3fc20
+#define ixMC_REGISTERS_TABLE_58 0x3fc24
+#define ixMC_REGISTERS_TABLE_59 0x3fc28
+#define ixMC_REGISTERS_TABLE_60 0x3fc2c
+#define ixMC_REGISTERS_TABLE_61 0x3fc30
+#define ixMC_REGISTERS_TABLE_62 0x3fc34
+#define ixMC_REGISTERS_TABLE_63 0x3fc38
+#define ixMC_REGISTERS_TABLE_64 0x3fc3c
+#define ixMC_REGISTERS_TABLE_65 0x3fc40
+#define ixMC_REGISTERS_TABLE_66 0x3fc44
+#define ixMC_REGISTERS_TABLE_67 0x3fc48
+#define ixMC_REGISTERS_TABLE_68 0x3fc4c
+#define ixMC_REGISTERS_TABLE_69 0x3fc50
+#define ixMC_REGISTERS_TABLE_70 0x3fc54
+#define ixMC_REGISTERS_TABLE_71 0x3fc58
+#define ixMC_REGISTERS_TABLE_72 0x3fc5c
+#define ixMC_REGISTERS_TABLE_73 0x3fc60
+#define ixMC_REGISTERS_TABLE_74 0x3fc64
+#define ixMC_REGISTERS_TABLE_75 0x3fc68
+#define ixMC_REGISTERS_TABLE_76 0x3fc6c
+#define ixMC_REGISTERS_TABLE_77 0x3fc70
+#define ixMC_REGISTERS_TABLE_78 0x3fc74
+#define ixMC_REGISTERS_TABLE_79 0x3fc78
+#define ixMC_REGISTERS_TABLE_80 0x3fc7c
+#define ixMC_REGISTERS_TABLE_81 0x3fc80
+#define ixMC_REGISTERS_TABLE_82 0x3fc84
+#define ixMC_REGISTERS_TABLE_83 0x3fc88
+#define ixMC_REGISTERS_TABLE_84 0x3fc8c
+#define ixMC_REGISTERS_TABLE_85 0x3fc90
+#define ixMC_REGISTERS_TABLE_86 0x3fc94
+#define ixMC_REGISTERS_TABLE_87 0x3fc98
+#define ixMC_REGISTERS_TABLE_88 0x3fc9c
+#define ixMC_REGISTERS_TABLE_89 0x3fca0
+#define ixMC_REGISTERS_TABLE_90 0x3fca4
+#define ixMC_REGISTERS_TABLE_91 0x3fca8
+#define ixMC_REGISTERS_TABLE_92 0x3fcac
+#define ixMC_REGISTERS_TABLE_93 0x3fcb0
+#define ixMC_REGISTERS_TABLE_94 0x3fcb4
+#define ixMC_REGISTERS_TABLE_95 0x3fcb8
+#define ixMC_REGISTERS_TABLE_96 0x3fcbc
+#define ixMC_REGISTERS_TABLE_97 0x3fcc0
+#define ixMC_REGISTERS_TABLE_98 0x3fcc4
+#define ixMC_REGISTERS_TABLE_99 0x3fcc8
+#define ixMC_REGISTERS_TABLE_100 0x3fccc
+#define ixMC_REGISTERS_TABLE_101 0x3fcd0
+#define ixMC_REGISTERS_TABLE_102 0x3fcd4
+#define ixMC_REGISTERS_TABLE_103 0x3fcd8
+#define ixMC_REGISTERS_TABLE_104 0x3fcdc
+#define ixMC_REGISTERS_TABLE_105 0x3fce0
+#define ixMC_REGISTERS_TABLE_106 0x3fce4
+#define ixMC_REGISTERS_TABLE_107 0x3fce8
+#define ixMC_REGISTERS_TABLE_108 0x3fcec
+#define ixMC_REGISTERS_TABLE_109 0x3fcf0
+#define ixMC_REGISTERS_TABLE_110 0x3fcf4
+#define ixMC_REGISTERS_TABLE_111 0x3fcf8
+#define ixMC_REGISTERS_TABLE_112 0x3fcfc
+#define ixMC_REGISTERS_TABLE_113 0x3fd00
+#define ixFAN_TABLE_1 0x3fd04
+#define ixFAN_TABLE_2 0x3fd08
+#define ixFAN_TABLE_3 0x3fd0c
+#define ixFAN_TABLE_4 0x3fd10
+#define ixFAN_TABLE_5 0x3fd14
+#define ixFAN_TABLE_6 0x3fd18
+#define ixFAN_TABLE_7 0x3fd1c
+#define ixFAN_TABLE_8 0x3fd20
+#define ixFAN_TABLE_9 0x3fd24
+#define ixSOFT_REGISTERS_TABLE_1 0x3fd28
+#define ixSOFT_REGISTERS_TABLE_2 0x3fd2c
+#define ixSOFT_REGISTERS_TABLE_3 0x3fd30
+#define ixSOFT_REGISTERS_TABLE_4 0x3fd34
+#define ixSOFT_REGISTERS_TABLE_5 0x3fd38
+#define ixSOFT_REGISTERS_TABLE_6 0x3fd3c
+#define ixSOFT_REGISTERS_TABLE_7 0x3fd40
+#define ixSOFT_REGISTERS_TABLE_8 0x3fd44
+#define ixSOFT_REGISTERS_TABLE_9 0x3fd48
+#define ixSOFT_REGISTERS_TABLE_10 0x3fd4c
+#define ixSOFT_REGISTERS_TABLE_11 0x3fd50
+#define ixSOFT_REGISTERS_TABLE_12 0x3fd54
+#define ixSOFT_REGISTERS_TABLE_13 0x3fd58
+#define ixSOFT_REGISTERS_TABLE_14 0x3fd5c
+#define ixSOFT_REGISTERS_TABLE_15 0x3fd60
+#define ixSOFT_REGISTERS_TABLE_16 0x3fd64
+#define ixSOFT_REGISTERS_TABLE_17 0x3fd68
+#define ixSOFT_REGISTERS_TABLE_18 0x3fd6c
+#define ixSOFT_REGISTERS_TABLE_19 0x3fd70
+#define ixSOFT_REGISTERS_TABLE_20 0x3fd74
+#define ixSOFT_REGISTERS_TABLE_21 0x3fd78
+#define ixSOFT_REGISTERS_TABLE_22 0x3fd7c
+#define ixSOFT_REGISTERS_TABLE_23 0x3fd80
+#define ixSOFT_REGISTERS_TABLE_24 0x3fd84
+#define ixSOFT_REGISTERS_TABLE_25 0x3fd88
+#define ixSOFT_REGISTERS_TABLE_26 0x3fd8c
+#define ixSOFT_REGISTERS_TABLE_27 0x3fd90
+#define ixSOFT_REGISTERS_TABLE_28 0x3fd94
+#define ixSOFT_REGISTERS_TABLE_29 0x3fd98
+#define ixSOFT_REGISTERS_TABLE_30 0x3fd9c
+#define ixPM_FUSES_1 0x3fda0
+#define ixPM_FUSES_2 0x3fda4
+#define ixPM_FUSES_3 0x3fda8
+#define ixPM_FUSES_4 0x3fdac
+#define ixPM_FUSES_5 0x3fdb0
+#define ixPM_FUSES_6 0x3fdb4
+#define ixPM_FUSES_7 0x3fdb8
+#define ixPM_FUSES_8 0x3fdbc
+#define ixPM_FUSES_9 0x3fdc0
+#define ixPM_FUSES_10 0x3fdc4
+#define ixPM_FUSES_11 0x3fdc8
+#define ixPM_FUSES_12 0x3fdcc
+#define ixPM_FUSES_13 0x3fdd0
+#define ixPM_FUSES_14 0x3fdd4
+#define ixPM_FUSES_15 0x3fdd8
+#define ixPM_FUSES_16 0x3fddc
+#define ixPM_FUSES_17 0x3fde0
+#define ixPM_FUSES_18 0x3fde4
+#define ixPM_FUSES_19 0x3fde8
+#define ixSMU_PM_STATUS_0 0x3fe00
+#define ixSMU_PM_STATUS_1 0x3fe04
+#define ixSMU_PM_STATUS_2 0x3fe08
+#define ixSMU_PM_STATUS_3 0x3fe0c
+#define ixSMU_PM_STATUS_4 0x3fe10
+#define ixSMU_PM_STATUS_5 0x3fe14
+#define ixSMU_PM_STATUS_6 0x3fe18
+#define ixSMU_PM_STATUS_7 0x3fe1c
+#define ixSMU_PM_STATUS_8 0x3fe20
+#define ixSMU_PM_STATUS_9 0x3fe24
+#define ixSMU_PM_STATUS_10 0x3fe28
+#define ixSMU_PM_STATUS_11 0x3fe2c
+#define ixSMU_PM_STATUS_12 0x3fe30
+#define ixSMU_PM_STATUS_13 0x3fe34
+#define ixSMU_PM_STATUS_14 0x3fe38
+#define ixSMU_PM_STATUS_15 0x3fe3c
+#define ixSMU_PM_STATUS_16 0x3fe40
+#define ixSMU_PM_STATUS_17 0x3fe44
+#define ixSMU_PM_STATUS_18 0x3fe48
+#define ixSMU_PM_STATUS_19 0x3fe4c
+#define ixSMU_PM_STATUS_20 0x3fe50
+#define ixSMU_PM_STATUS_21 0x3fe54
+#define ixSMU_PM_STATUS_22 0x3fe58
+#define ixSMU_PM_STATUS_23 0x3fe5c
+#define ixSMU_PM_STATUS_24 0x3fe60
+#define ixSMU_PM_STATUS_25 0x3fe64
+#define ixSMU_PM_STATUS_26 0x3fe68
+#define ixSMU_PM_STATUS_27 0x3fe6c
+#define ixSMU_PM_STATUS_28 0x3fe70
+#define ixSMU_PM_STATUS_29 0x3fe74
+#define ixSMU_PM_STATUS_30 0x3fe78
+#define ixSMU_PM_STATUS_31 0x3fe7c
+#define ixSMU_PM_STATUS_32 0x3fe80
+#define ixSMU_PM_STATUS_33 0x3fe84
+#define ixSMU_PM_STATUS_34 0x3fe88
+#define ixSMU_PM_STATUS_35 0x3fe8c
+#define ixSMU_PM_STATUS_36 0x3fe90
+#define ixSMU_PM_STATUS_37 0x3fe94
+#define ixSMU_PM_STATUS_38 0x3fe98
+#define ixSMU_PM_STATUS_39 0x3fe9c
+#define ixSMU_PM_STATUS_40 0x3fea0
+#define ixSMU_PM_STATUS_41 0x3fea4
+#define ixSMU_PM_STATUS_42 0x3fea8
+#define ixSMU_PM_STATUS_43 0x3feac
+#define ixSMU_PM_STATUS_44 0x3feb0
+#define ixSMU_PM_STATUS_45 0x3feb4
+#define ixSMU_PM_STATUS_46 0x3feb8
+#define ixSMU_PM_STATUS_47 0x3febc
+#define ixSMU_PM_STATUS_48 0x3fec0
+#define ixSMU_PM_STATUS_49 0x3fec4
+#define ixSMU_PM_STATUS_50 0x3fec8
+#define ixSMU_PM_STATUS_51 0x3fecc
+#define ixSMU_PM_STATUS_52 0x3fed0
+#define ixSMU_PM_STATUS_53 0x3fed4
+#define ixSMU_PM_STATUS_54 0x3fed8
+#define ixSMU_PM_STATUS_55 0x3fedc
+#define ixSMU_PM_STATUS_56 0x3fee0
+#define ixSMU_PM_STATUS_57 0x3fee4
+#define ixSMU_PM_STATUS_58 0x3fee8
+#define ixSMU_PM_STATUS_59 0x3feec
+#define ixSMU_PM_STATUS_60 0x3fef0
+#define ixSMU_PM_STATUS_61 0x3fef4
+#define ixSMU_PM_STATUS_62 0x3fef8
+#define ixSMU_PM_STATUS_63 0x3fefc
+#define ixSMU_PM_STATUS_64 0x3ff00
+#define ixSMU_PM_STATUS_65 0x3ff04
+#define ixSMU_PM_STATUS_66 0x3ff08
+#define ixSMU_PM_STATUS_67 0x3ff0c
+#define ixSMU_PM_STATUS_68 0x3ff10
+#define ixSMU_PM_STATUS_69 0x3ff14
+#define ixSMU_PM_STATUS_70 0x3ff18
+#define ixSMU_PM_STATUS_71 0x3ff1c
+#define ixSMU_PM_STATUS_72 0x3ff20
+#define ixSMU_PM_STATUS_73 0x3ff24
+#define ixSMU_PM_STATUS_74 0x3ff28
+#define ixSMU_PM_STATUS_75 0x3ff2c
+#define ixSMU_PM_STATUS_76 0x3ff30
+#define ixSMU_PM_STATUS_77 0x3ff34
+#define ixSMU_PM_STATUS_78 0x3ff38
+#define ixSMU_PM_STATUS_79 0x3ff3c
+#define ixSMU_PM_STATUS_80 0x3ff40
+#define ixSMU_PM_STATUS_81 0x3ff44
+#define ixSMU_PM_STATUS_82 0x3ff48
+#define ixSMU_PM_STATUS_83 0x3ff4c
+#define ixSMU_PM_STATUS_84 0x3ff50
+#define ixSMU_PM_STATUS_85 0x3ff54
+#define ixSMU_PM_STATUS_86 0x3ff58
+#define ixSMU_PM_STATUS_87 0x3ff5c
+#define ixSMU_PM_STATUS_88 0x3ff60
+#define ixSMU_PM_STATUS_89 0x3ff64
+#define ixSMU_PM_STATUS_90 0x3ff68
+#define ixSMU_PM_STATUS_91 0x3ff6c
+#define ixSMU_PM_STATUS_92 0x3ff70
+#define ixSMU_PM_STATUS_93 0x3ff74
+#define ixSMU_PM_STATUS_94 0x3ff78
+#define ixSMU_PM_STATUS_95 0x3ff7c
+#define ixSMU_PM_STATUS_96 0x3ff80
+#define ixSMU_PM_STATUS_97 0x3ff84
+#define ixSMU_PM_STATUS_98 0x3ff88
+#define ixSMU_PM_STATUS_99 0x3ff8c
+#define ixSMU_PM_STATUS_100 0x3ff90
+#define ixSMU_PM_STATUS_101 0x3ff94
+#define ixSMU_PM_STATUS_102 0x3ff98
+#define ixSMU_PM_STATUS_103 0x3ff9c
+#define ixSMU_PM_STATUS_104 0x3ffa0
+#define ixSMU_PM_STATUS_105 0x3ffa4
+#define ixSMU_PM_STATUS_106 0x3ffa8
+#define ixSMU_PM_STATUS_107 0x3ffac
+#define ixSMU_PM_STATUS_108 0x3ffb0
+#define ixSMU_PM_STATUS_109 0x3ffb4
+#define ixSMU_PM_STATUS_110 0x3ffb8
+#define ixSMU_PM_STATUS_111 0x3ffbc
+#define ixSMU_PM_STATUS_112 0x3ffc0
+#define ixSMU_PM_STATUS_113 0x3ffc4
+#define ixSMU_PM_STATUS_114 0x3ffc8
+#define ixSMU_PM_STATUS_115 0x3ffcc
+#define ixSMU_PM_STATUS_116 0x3ffd0
+#define ixSMU_PM_STATUS_117 0x3ffd4
+#define ixSMU_PM_STATUS_118 0x3ffd8
+#define ixSMU_PM_STATUS_119 0x3ffdc
+#define ixSMU_PM_STATUS_120 0x3ffe0
+#define ixSMU_PM_STATUS_121 0x3ffe4
+#define ixSMU_PM_STATUS_122 0x3ffe8
+#define ixSMU_PM_STATUS_123 0x3ffec
+#define ixSMU_PM_STATUS_124 0x3fff0
+#define ixSMU_PM_STATUS_125 0x3fff4
+#define ixSMU_PM_STATUS_126 0x3fff8
+#define ixSMU_PM_STATUS_127 0x3fffc
+#define ixCG_THERMAL_INT_ENA 0xc2100024
+#define ixCG_THERMAL_INT_CTRL 0xc2100028
+#define ixCG_THERMAL_INT_STATUS 0xc210002c
+#define ixCG_THERMAL_CTRL 0xc0300004
+#define ixCG_THERMAL_STATUS 0xc0300008
+#define ixCG_THERMAL_INT 0xc030000c
+#define ixCG_MULT_THERMAL_CTRL 0xc0300010
+#define ixCG_MULT_THERMAL_STATUS 0xc0300014
+#define ixCG_FDO_CTRL0 0xc0300064
+#define ixCG_FDO_CTRL1 0xc0300068
+#define ixCG_FDO_CTRL2 0xc030006c
+#define ixCG_TACH_CTRL 0xc0300070
+#define ixCG_TACH_STATUS 0xc0300074
+#define ixCC_THM_STRAPS0 0xc0300080
+#define ixTHM_TMON0_RDIL0_DATA 0xc0300100
+#define ixTHM_TMON0_RDIL1_DATA 0xc0300104
+#define ixTHM_TMON0_RDIL2_DATA 0xc0300108
+#define ixTHM_TMON0_RDIL3_DATA 0xc030010c
+#define ixTHM_TMON0_RDIL4_DATA 0xc0300110
+#define ixTHM_TMON0_RDIL5_DATA 0xc0300114
+#define ixTHM_TMON0_RDIL6_DATA 0xc0300118
+#define ixTHM_TMON0_RDIL7_DATA 0xc030011c
+#define ixTHM_TMON0_RDIL8_DATA 0xc0300120
+#define ixTHM_TMON0_RDIL9_DATA 0xc0300124
+#define ixTHM_TMON0_RDIL10_DATA 0xc0300128
+#define ixTHM_TMON0_RDIL11_DATA 0xc030012c
+#define ixTHM_TMON0_RDIL12_DATA 0xc0300130
+#define ixTHM_TMON0_RDIL13_DATA 0xc0300134
+#define ixTHM_TMON0_RDIL14_DATA 0xc0300138
+#define ixTHM_TMON0_RDIL15_DATA 0xc030013c
+#define ixTHM_TMON0_RDIR0_DATA 0xc0300140
+#define ixTHM_TMON0_RDIR1_DATA 0xc0300144
+#define ixTHM_TMON0_RDIR2_DATA 0xc0300148
+#define ixTHM_TMON0_RDIR3_DATA 0xc030014c
+#define ixTHM_TMON0_RDIR4_DATA 0xc0300150
+#define ixTHM_TMON0_RDIR5_DATA 0xc0300154
+#define ixTHM_TMON0_RDIR6_DATA 0xc0300158
+#define ixTHM_TMON0_RDIR7_DATA 0xc030015c
+#define ixTHM_TMON0_RDIR8_DATA 0xc0300160
+#define ixTHM_TMON0_RDIR9_DATA 0xc0300164
+#define ixTHM_TMON0_RDIR10_DATA 0xc0300168
+#define ixTHM_TMON0_RDIR11_DATA 0xc030016c
+#define ixTHM_TMON0_RDIR12_DATA 0xc0300170
+#define ixTHM_TMON0_RDIR13_DATA 0xc0300174
+#define ixTHM_TMON0_RDIR14_DATA 0xc0300178
+#define ixTHM_TMON0_RDIR15_DATA 0xc030017c
+#define ixTHM_TMON0_INT_DATA 0xc0300300
+#define ixTHM_TMON0_DEBUG 0xc0300310
+#define ixGENERAL_PWRMGT 0xc0200000
+#define ixCNB_PWRMGT_CNTL 0xc0200004
+#define ixSCLK_PWRMGT_CNTL 0xc0200008
+#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014
+#define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8
+#define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac
+#define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0
+#define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4
+#define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8
+#define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc
+#define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0
+#define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4
+#define ixPLL_TEST_CNTL 0xc020003c
+#define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044
+#define ixCG_DISPLAY_GAP_CNTL 0xc0200060
+#define ixCG_DISPLAY_GAP_CNTL2 0xc0200230
+#define ixCG_ACPI_CNTL 0xc0200064
+#define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080
+#define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084
+#define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c
+#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088
+#define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c
+#define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310
+#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0
+#define ixCG_ULV_PARAMETER 0xc020015c
+#define ixSCLK_MIN_DIV 0xc0200308
+#define ixLCAC_SX0_CNTL 0xc0400d00
+#define ixLCAC_SX0_OVR_SEL 0xc0400d04
+#define ixLCAC_SX0_OVR_VAL 0xc0400d08
+#define ixLCAC_MC0_CNTL 0xc0400d30
+#define ixLCAC_MC0_OVR_SEL 0xc0400d34
+#define ixLCAC_MC0_OVR_VAL 0xc0400d38
+#define ixLCAC_MC1_CNTL 0xc0400d3c
+#define ixLCAC_MC1_OVR_SEL 0xc0400d40
+#define ixLCAC_MC1_OVR_VAL 0xc0400d44
+#define ixLCAC_MC2_CNTL 0xc0400d48
+#define ixLCAC_MC2_OVR_SEL 0xc0400d4c
+#define ixLCAC_MC2_OVR_VAL 0xc0400d50
+#define ixLCAC_MC3_CNTL 0xc0400d54
+#define ixLCAC_MC3_OVR_SEL 0xc0400d58
+#define ixLCAC_MC3_OVR_VAL 0xc0400d5c
+#define ixLCAC_CPL_CNTL 0xc0400d80
+#define ixLCAC_CPL_OVR_SEL 0xc0400d84
+#define ixLCAC_CPL_OVR_VAL 0xc0400d88
+#define mmROM_SMC_IND_INDEX 0x80
+#define mmROM0_ROM_SMC_IND_INDEX 0x80
+#define mmROM1_ROM_SMC_IND_INDEX 0x82
+#define mmROM2_ROM_SMC_IND_INDEX 0x84
+#define mmROM3_ROM_SMC_IND_INDEX 0x86
+#define mmROM_SMC_IND_DATA 0x81
+#define mmROM0_ROM_SMC_IND_DATA 0x81
+#define mmROM1_ROM_SMC_IND_DATA 0x83
+#define mmROM2_ROM_SMC_IND_DATA 0x85
+#define mmROM3_ROM_SMC_IND_DATA 0x87
+#define ixROM_CNTL 0xc0600000
+#define ixPAGE_MIRROR_CNTL 0xc0600004
+#define ixROM_STATUS 0xc0600008
+#define ixCGTT_ROM_CLK_CTRL0 0xc060000c
+#define ixROM_INDEX 0xc0600010
+#define ixROM_DATA 0xc0600014
+#define ixROM_START 0xc0600018
+#define ixROM_SW_CNTL 0xc060001c
+#define ixROM_SW_STATUS 0xc0600020
+#define ixROM_SW_COMMAND 0xc0600024
+#define ixROM_SW_DATA_1 0xc0600028
+#define ixROM_SW_DATA_2 0xc060002c
+#define ixROM_SW_DATA_3 0xc0600030
+#define ixROM_SW_DATA_4 0xc0600034
+#define ixROM_SW_DATA_5 0xc0600038
+#define ixROM_SW_DATA_6 0xc060003c
+#define ixROM_SW_DATA_7 0xc0600040
+#define ixROM_SW_DATA_8 0xc0600044
+#define ixROM_SW_DATA_9 0xc0600048
+#define ixROM_SW_DATA_10 0xc060004c
+#define ixROM_SW_DATA_11 0xc0600050
+#define ixROM_SW_DATA_12 0xc0600054
+#define ixROM_SW_DATA_13 0xc0600058
+#define ixROM_SW_DATA_14 0xc060005c
+#define ixROM_SW_DATA_15 0xc0600060
+#define ixROM_SW_DATA_16 0xc0600064
+#define ixROM_SW_DATA_17 0xc0600068
+#define ixROM_SW_DATA_18 0xc060006c
+#define ixROM_SW_DATA_19 0xc0600070
+#define ixROM_SW_DATA_20 0xc0600074
+#define ixROM_SW_DATA_21 0xc0600078
+#define ixROM_SW_DATA_22 0xc060007c
+#define ixROM_SW_DATA_23 0xc0600080
+#define ixROM_SW_DATA_24 0xc0600084
+#define ixROM_SW_DATA_25 0xc0600088
+#define ixROM_SW_DATA_26 0xc060008c
+#define ixROM_SW_DATA_27 0xc0600090
+#define ixROM_SW_DATA_28 0xc0600094
+#define ixROM_SW_DATA_29 0xc0600098
+#define ixROM_SW_DATA_30 0xc060009c
+#define ixROM_SW_DATA_31 0xc06000a0
+#define ixROM_SW_DATA_32 0xc06000a4
+#define ixROM_SW_DATA_33 0xc06000a8
+#define ixROM_SW_DATA_34 0xc06000ac
+#define ixROM_SW_DATA_35 0xc06000b0
+#define ixROM_SW_DATA_36 0xc06000b4
+#define ixROM_SW_DATA_37 0xc06000b8
+#define ixROM_SW_DATA_38 0xc06000bc
+#define ixROM_SW_DATA_39 0xc06000c0
+#define ixROM_SW_DATA_40 0xc06000c4
+#define ixROM_SW_DATA_41 0xc06000c8
+#define ixROM_SW_DATA_42 0xc06000cc
+#define ixROM_SW_DATA_43 0xc06000d0
+#define ixROM_SW_DATA_44 0xc06000d4
+#define ixROM_SW_DATA_45 0xc06000d8
+#define ixROM_SW_DATA_46 0xc06000dc
+#define ixROM_SW_DATA_47 0xc06000e0
+#define ixROM_SW_DATA_48 0xc06000e4
+#define ixROM_SW_DATA_49 0xc06000e8
+#define ixROM_SW_DATA_50 0xc06000ec
+#define ixROM_SW_DATA_51 0xc06000f0
+#define ixROM_SW_DATA_52 0xc06000f4
+#define ixROM_SW_DATA_53 0xc06000f8
+#define ixROM_SW_DATA_54 0xc06000fc
+#define ixROM_SW_DATA_55 0xc0600110
+#define ixROM_SW_DATA_56 0xc0600114
+#define ixROM_SW_DATA_57 0xc0600118
+#define ixROM_SW_DATA_58 0xc060011c
+#define ixROM_SW_DATA_59 0xc0600120
+#define ixROM_SW_DATA_60 0xc0600124
+#define ixROM_SW_DATA_61 0xc0600128
+#define ixROM_SW_DATA_62 0xc060012c
+#define ixROM_SW_DATA_63 0xc0600130
+#define ixROM_SW_DATA_64 0xc0600134
+
+#endif /* SMU_7_0_1_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h
new file mode 100644
index 000000000000..25882a4dea5d
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h
@@ -0,0 +1,5456 @@
+/*
+ * SMU_7_0_1 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef SMU_7_0_1_SH_MASK_H
+#define SMU_7_0_1_SH_MASK_H
+
+#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
+#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1
+#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0
+#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2
+#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1
+#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f
+#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1
+#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0
+#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2
+#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1
+#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f
+#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1
+#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0
+#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2
+#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1
+#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f
+#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1
+#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0
+#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2
+#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1
+#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4
+#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2
+#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
+#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3
+#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10
+#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4
+#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20
+#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5
+#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40
+#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6
+#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80
+#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7
+#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100
+#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
+#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200
+#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9
+#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400
+#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa
+#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800
+#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb
+#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000
+#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc
+#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1
+#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2
+#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1
+#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4
+#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4
+#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0
+#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14
+#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000
+#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b
+#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000
+#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17
+#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a
+#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e
+#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff
+#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000
+#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fe00
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9
+#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000
+#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15
+#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17
+#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f
+#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1
+#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2
+#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1
+#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc
+#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2
+#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30
+#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8
+#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200
+#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15
+#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
+#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
+#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
+#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
+#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
+#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2
+#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1
+#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4
+#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2
+#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8
+#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3
+#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10
+#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4
+#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00
+#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa
+#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000
+#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc
+#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000
+#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c
+#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000
+#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d
+#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1
+#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0
+#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0
+#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4
+#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff
+#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0
+#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00
+#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8
+#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2
+#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1
+#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4
+#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2
+#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1
+#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0
+#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8
+#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3
+#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100
+#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8
+#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000
+#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe
+#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000
+#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf
+#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000
+#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10
+#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000
+#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11
+#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000
+#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12
+#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000
+#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13
+#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000
+#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14
+#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000
+#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15
+#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000
+#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16
+#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000
+#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18
+#define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1
+#define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0
+#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6
+#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1
+#define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00
+#define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa
+#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff
+#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0
+#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00
+#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8
+#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000
+#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10
+#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff
+#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0
+#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00
+#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8
+#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000
+#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10
+#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f
+#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
+#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0
+#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5
+#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00
+#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa
+#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000
+#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11
+#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000
+#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12
+#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000
+#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3
+#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0
+#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9
+#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b
+#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7
+#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_0__SMC_RESP_MASK 0xffff
+#define SMC_RESP_0__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_1__SMC_RESP_MASK 0xffff
+#define SMC_RESP_1__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_2__SMC_RESP_MASK 0xffff
+#define SMC_RESP_2__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_3__SMC_RESP_MASK 0xffff
+#define SMC_RESP_3__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_4__SMC_RESP_MASK 0xffff
+#define SMC_RESP_4__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_5__SMC_RESP_MASK 0xffff
+#define SMC_RESP_5__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_6__SMC_RESP_MASK 0xffff
+#define SMC_RESP_6__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_7__SMC_RESP_MASK 0xffff
+#define SMC_RESP_7__SMC_RESP__SHIFT 0x0
+#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_8__SMC_RESP_MASK 0xffff
+#define SMC_RESP_8__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_9__SMC_RESP_MASK 0xffff
+#define SMC_RESP_9__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_10__SMC_RESP_MASK 0xffff
+#define SMC_RESP_10__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_11__SMC_RESP_MASK 0xffff
+#define SMC_RESP_11__SMC_RESP__SHIFT 0x0
+#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1
+#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0
+#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2
+#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1
+#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000
+#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e
+#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1
+#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8
+#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000
+#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18
+#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1
+#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0
+#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff
+#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0
+#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff
+#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0
+#define SMC_PC_C__smc_pc_c_MASK 0xffffffff
+#define SMC_PC_C__smc_pc_c__SHIFT 0x0
+#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff
+#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0
+#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1
+#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0
+#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf
+#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0
+#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0
+#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4
+#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff
+#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0
+#define GPIOPAD_A__GPIO_A_MASK 0x7fffffff
+#define GPIOPAD_A__GPIO_A__SHIFT 0x0
+#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff
+#define GPIOPAD_EN__GPIO_EN__SHIFT 0x0
+#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff
+#define GPIOPAD_Y__GPIO_Y__SHIFT 0x0
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e
+#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff
+#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0
+#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000
+#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f
+#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff
+#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0
+#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000
+#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c
+#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000
+#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f
+#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff
+#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0
+#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000
+#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f
+#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff
+#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0
+#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000
+#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f
+#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff
+#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0
+#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000
+#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6
+#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff
+#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0
+#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff
+#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0
+#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff
+#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0
+#define CG_FPS_CNT__FPS_CNT_MASK 0xff
+#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0
+#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1
+#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0
+#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2
+#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1
+#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4
+#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2
+#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8
+#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3
+#define RCU_UC_EVENTS__TP_Tester_MASK 0x40
+#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6
+#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80
+#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7
+#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100
+#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8
+#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200
+#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9
+#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400
+#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa
+#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800
+#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb
+#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000
+#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd
+#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000
+#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10
+#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000
+#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11
+#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000
+#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12
+#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000
+#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13
+#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000
+#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18
+#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2
+#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1
+#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8
+#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3
+#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10
+#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4
+#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20
+#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5
+#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100
+#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8
+#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000
+#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10
+#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000
+#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11
+#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000
+#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16
+#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000
+#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17
+#define CC_RCU_FUSES__GPU_DIS_MASK 0x2
+#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1
+#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4
+#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2
+#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10
+#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4
+#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20
+#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5
+#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40
+#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6
+#define CC_RCU_FUSES__ROM_DIS_MASK 0x80
+#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7
+#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100
+#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8
+#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200
+#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9
+#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400
+#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa
+#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x4000
+#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0xe
+#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x8000
+#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xf
+#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x10000
+#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0x10
+#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x20000
+#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x11
+#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x40000
+#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x12
+#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x80000
+#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x13
+#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x100000
+#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x14
+#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x400000
+#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x16
+#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x800000
+#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x17
+#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x1000000
+#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x18
+#define CC_RCU_FUSES__RCU_SPARE_MASK 0xfe000000
+#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x19
+#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2
+#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1
+#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc
+#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2
+#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600
+#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9
+#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800
+#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17
+#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000
+#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b
+#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000
+#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c
+#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000
+#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d
+#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff
+#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0
+#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00
+#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8
+#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000
+#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10
+#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000
+#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18
+#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe
+#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1
+#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e
+#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1
+#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e
+#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1
+#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40
+#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6
+#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80
+#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7
+#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100
+#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8
+#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200
+#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9
+#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400
+#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa
+#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800
+#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd
+#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000
+#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18
+#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000
+#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19
+#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000
+#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a
+#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0
+#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4
+#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000
+#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14
+#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000
+#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18
+#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2
+#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1
+#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff
+#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0
+#define SMU_STATUS__SMU_DONE_MASK 0x1
+#define SMU_STATUS__SMU_DONE__SHIFT 0x0
+#define SMU_STATUS__SMU_PASS_MASK 0x2
+#define SMU_STATUS__SMU_PASS__SHIFT 0x1
+#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1
+#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0
+#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6
+#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1
+#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8
+#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3
+#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10
+#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4
+#define SMU_FIRMWARE__SMU_counter_MASK 0xf00
+#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8
+#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000
+#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10
+#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000
+#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11
+#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff
+#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0
+#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000
+#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f
+#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff
+#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0
+#define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff
+#define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0
+#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff
+#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0
+#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff
+#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0
+#define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff
+#define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0
+#define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff
+#define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0
+#define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff
+#define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0
+#define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff
+#define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0
+#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff
+#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0
+#define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff
+#define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0
+#define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff
+#define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0
+#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff
+#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0
+#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff
+#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0
+#define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff
+#define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0
+#define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff
+#define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0
+#define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff
+#define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0
+#define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff
+#define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0
+#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff
+#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0
+#define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff
+#define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0
+#define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff
+#define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0
+#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff
+#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0
+#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff
+#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0
+#define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff
+#define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0
+#define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff
+#define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0
+#define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff
+#define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0
+#define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff
+#define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0
+#define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff
+#define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0
+#define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff
+#define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0
+#define DPM_TABLE_28__SystemFlags_MASK 0xffffffff
+#define DPM_TABLE_28__SystemFlags__SHIFT 0x0
+#define DPM_TABLE_29__SmioMaskVddcVid_MASK 0xffffffff
+#define DPM_TABLE_29__SmioMaskVddcVid__SHIFT 0x0
+#define DPM_TABLE_30__SmioMaskVddcPhase_MASK 0xffffffff
+#define DPM_TABLE_30__SmioMaskVddcPhase__SHIFT 0x0
+#define DPM_TABLE_31__SmioMaskVddciVid_MASK 0xffffffff
+#define DPM_TABLE_31__SmioMaskVddciVid__SHIFT 0x0
+#define DPM_TABLE_32__SmioMaskMvddVid_MASK 0xffffffff
+#define DPM_TABLE_32__SmioMaskMvddVid__SHIFT 0x0
+#define DPM_TABLE_33__VddcLevelCount_MASK 0xffffffff
+#define DPM_TABLE_33__VddcLevelCount__SHIFT 0x0
+#define DPM_TABLE_34__VddciLevelCount_MASK 0xffffffff
+#define DPM_TABLE_34__VddciLevelCount__SHIFT 0x0
+#define DPM_TABLE_35__MvddLevelCount_MASK 0xffffffff
+#define DPM_TABLE_35__MvddLevelCount__SHIFT 0x0
+#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_36__VddcLevel_0_Voltage_MASK 0xffff0000
+#define DPM_TABLE_36__VddcLevel_0_Voltage__SHIFT 0x10
+#define DPM_TABLE_37__VddcLevel_0_padding_MASK 0xff
+#define DPM_TABLE_37__VddcLevel_0_padding__SHIFT 0x0
+#define DPM_TABLE_37__VddcLevel_0_Smio_MASK 0xff00
+#define DPM_TABLE_37__VddcLevel_0_Smio__SHIFT 0x8
+#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_38__VddcLevel_1_Voltage_MASK 0xffff0000
+#define DPM_TABLE_38__VddcLevel_1_Voltage__SHIFT 0x10
+#define DPM_TABLE_39__VddcLevel_1_padding_MASK 0xff
+#define DPM_TABLE_39__VddcLevel_1_padding__SHIFT 0x0
+#define DPM_TABLE_39__VddcLevel_1_Smio_MASK 0xff00
+#define DPM_TABLE_39__VddcLevel_1_Smio__SHIFT 0x8
+#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_40__VddcLevel_2_Voltage_MASK 0xffff0000
+#define DPM_TABLE_40__VddcLevel_2_Voltage__SHIFT 0x10
+#define DPM_TABLE_41__VddcLevel_2_padding_MASK 0xff
+#define DPM_TABLE_41__VddcLevel_2_padding__SHIFT 0x0
+#define DPM_TABLE_41__VddcLevel_2_Smio_MASK 0xff00
+#define DPM_TABLE_41__VddcLevel_2_Smio__SHIFT 0x8
+#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_42__VddcLevel_3_Voltage_MASK 0xffff0000
+#define DPM_TABLE_42__VddcLevel_3_Voltage__SHIFT 0x10
+#define DPM_TABLE_43__VddcLevel_3_padding_MASK 0xff
+#define DPM_TABLE_43__VddcLevel_3_padding__SHIFT 0x0
+#define DPM_TABLE_43__VddcLevel_3_Smio_MASK 0xff00
+#define DPM_TABLE_43__VddcLevel_3_Smio__SHIFT 0x8
+#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_44__VddcLevel_4_Voltage_MASK 0xffff0000
+#define DPM_TABLE_44__VddcLevel_4_Voltage__SHIFT 0x10
+#define DPM_TABLE_45__VddcLevel_4_padding_MASK 0xff
+#define DPM_TABLE_45__VddcLevel_4_padding__SHIFT 0x0
+#define DPM_TABLE_45__VddcLevel_4_Smio_MASK 0xff00
+#define DPM_TABLE_45__VddcLevel_4_Smio__SHIFT 0x8
+#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_46__VddcLevel_5_Voltage_MASK 0xffff0000
+#define DPM_TABLE_46__VddcLevel_5_Voltage__SHIFT 0x10
+#define DPM_TABLE_47__VddcLevel_5_padding_MASK 0xff
+#define DPM_TABLE_47__VddcLevel_5_padding__SHIFT 0x0
+#define DPM_TABLE_47__VddcLevel_5_Smio_MASK 0xff00
+#define DPM_TABLE_47__VddcLevel_5_Smio__SHIFT 0x8
+#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_48__VddcLevel_6_Voltage_MASK 0xffff0000
+#define DPM_TABLE_48__VddcLevel_6_Voltage__SHIFT 0x10
+#define DPM_TABLE_49__VddcLevel_6_padding_MASK 0xff
+#define DPM_TABLE_49__VddcLevel_6_padding__SHIFT 0x0
+#define DPM_TABLE_49__VddcLevel_6_Smio_MASK 0xff00
+#define DPM_TABLE_49__VddcLevel_6_Smio__SHIFT 0x8
+#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_50__VddcLevel_7_Voltage_MASK 0xffff0000
+#define DPM_TABLE_50__VddcLevel_7_Voltage__SHIFT 0x10
+#define DPM_TABLE_51__VddcLevel_7_padding_MASK 0xff
+#define DPM_TABLE_51__VddcLevel_7_padding__SHIFT 0x0
+#define DPM_TABLE_51__VddcLevel_7_Smio_MASK 0xff00
+#define DPM_TABLE_51__VddcLevel_7_Smio__SHIFT 0x8
+#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_52__VddciLevel_0_Voltage_MASK 0xffff0000
+#define DPM_TABLE_52__VddciLevel_0_Voltage__SHIFT 0x10
+#define DPM_TABLE_53__VddciLevel_0_padding_MASK 0xff
+#define DPM_TABLE_53__VddciLevel_0_padding__SHIFT 0x0
+#define DPM_TABLE_53__VddciLevel_0_Smio_MASK 0xff00
+#define DPM_TABLE_53__VddciLevel_0_Smio__SHIFT 0x8
+#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_54__VddciLevel_1_Voltage_MASK 0xffff0000
+#define DPM_TABLE_54__VddciLevel_1_Voltage__SHIFT 0x10
+#define DPM_TABLE_55__VddciLevel_1_padding_MASK 0xff
+#define DPM_TABLE_55__VddciLevel_1_padding__SHIFT 0x0
+#define DPM_TABLE_55__VddciLevel_1_Smio_MASK 0xff00
+#define DPM_TABLE_55__VddciLevel_1_Smio__SHIFT 0x8
+#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_56__VddciLevel_2_Voltage_MASK 0xffff0000
+#define DPM_TABLE_56__VddciLevel_2_Voltage__SHIFT 0x10
+#define DPM_TABLE_57__VddciLevel_2_padding_MASK 0xff
+#define DPM_TABLE_57__VddciLevel_2_padding__SHIFT 0x0
+#define DPM_TABLE_57__VddciLevel_2_Smio_MASK 0xff00
+#define DPM_TABLE_57__VddciLevel_2_Smio__SHIFT 0x8
+#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_58__VddciLevel_3_Voltage_MASK 0xffff0000
+#define DPM_TABLE_58__VddciLevel_3_Voltage__SHIFT 0x10
+#define DPM_TABLE_59__VddciLevel_3_padding_MASK 0xff
+#define DPM_TABLE_59__VddciLevel_3_padding__SHIFT 0x0
+#define DPM_TABLE_59__VddciLevel_3_Smio_MASK 0xff00
+#define DPM_TABLE_59__VddciLevel_3_Smio__SHIFT 0x8
+#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_60__MvddLevel_0_Voltage_MASK 0xffff0000
+#define DPM_TABLE_60__MvddLevel_0_Voltage__SHIFT 0x10
+#define DPM_TABLE_61__MvddLevel_0_padding_MASK 0xff
+#define DPM_TABLE_61__MvddLevel_0_padding__SHIFT 0x0
+#define DPM_TABLE_61__MvddLevel_0_Smio_MASK 0xff00
+#define DPM_TABLE_61__MvddLevel_0_Smio__SHIFT 0x8
+#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_62__MvddLevel_1_Voltage_MASK 0xffff0000
+#define DPM_TABLE_62__MvddLevel_1_Voltage__SHIFT 0x10
+#define DPM_TABLE_63__MvddLevel_1_padding_MASK 0xff
+#define DPM_TABLE_63__MvddLevel_1_padding__SHIFT 0x0
+#define DPM_TABLE_63__MvddLevel_1_Smio_MASK 0xff00
+#define DPM_TABLE_63__MvddLevel_1_Smio__SHIFT 0x8
+#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_64__MvddLevel_2_Voltage_MASK 0xffff0000
+#define DPM_TABLE_64__MvddLevel_2_Voltage__SHIFT 0x10
+#define DPM_TABLE_65__MvddLevel_2_padding_MASK 0xff
+#define DPM_TABLE_65__MvddLevel_2_padding__SHIFT 0x0
+#define DPM_TABLE_65__MvddLevel_2_Smio_MASK 0xff00
+#define DPM_TABLE_65__MvddLevel_2_Smio__SHIFT 0x8
+#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_66__MvddLevel_3_Voltage_MASK 0xffff0000
+#define DPM_TABLE_66__MvddLevel_3_Voltage__SHIFT 0x10
+#define DPM_TABLE_67__MvddLevel_3_padding_MASK 0xff
+#define DPM_TABLE_67__MvddLevel_3_padding__SHIFT 0x0
+#define DPM_TABLE_67__MvddLevel_3_Smio_MASK 0xff00
+#define DPM_TABLE_67__MvddLevel_3_Smio__SHIFT 0x8
+#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_68__UvdLevelCount_MASK 0xff
+#define DPM_TABLE_68__UvdLevelCount__SHIFT 0x0
+#define DPM_TABLE_68__LinkLevelCount_MASK 0xff00
+#define DPM_TABLE_68__LinkLevelCount__SHIFT 0x8
+#define DPM_TABLE_68__MemoryDpmLevelCount_MASK 0xff0000
+#define DPM_TABLE_68__MemoryDpmLevelCount__SHIFT 0x10
+#define DPM_TABLE_68__GraphicsDpmLevelCount_MASK 0xff000000
+#define DPM_TABLE_68__GraphicsDpmLevelCount__SHIFT 0x18
+#define DPM_TABLE_69__padding2_MASK 0xff
+#define DPM_TABLE_69__padding2__SHIFT 0x0
+#define DPM_TABLE_69__SamuLevelCount_MASK 0xff00
+#define DPM_TABLE_69__SamuLevelCount__SHIFT 0x8
+#define DPM_TABLE_69__AcpLevelCount_MASK 0xff0000
+#define DPM_TABLE_69__AcpLevelCount__SHIFT 0x10
+#define DPM_TABLE_69__VceLevelCount_MASK 0xff000000
+#define DPM_TABLE_69__VceLevelCount__SHIFT 0x18
+#define DPM_TABLE_70__Reserved_0_MASK 0xffffffff
+#define DPM_TABLE_70__Reserved_0__SHIFT 0x0
+#define DPM_TABLE_71__Reserved_1_MASK 0xffffffff
+#define DPM_TABLE_71__Reserved_1__SHIFT 0x0
+#define DPM_TABLE_72__Reserved_2_MASK 0xffffffff
+#define DPM_TABLE_72__Reserved_2__SHIFT 0x0
+#define DPM_TABLE_73__Reserved_3_MASK 0xffffffff
+#define DPM_TABLE_73__Reserved_3__SHIFT 0x0
+#define DPM_TABLE_74__Reserved_4_MASK 0xffffffff
+#define DPM_TABLE_74__Reserved_4__SHIFT 0x0
+#define DPM_TABLE_75__GraphicsLevel_0_Flags_MASK 0xffffffff
+#define DPM_TABLE_75__GraphicsLevel_0_Flags__SHIFT 0x0
+#define DPM_TABLE_76__GraphicsLevel_0_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_76__GraphicsLevel_0_MinVddc__SHIFT 0x0
+#define DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_78__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_78__GraphicsLevel_0_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_79__GraphicsLevel_0_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_79__GraphicsLevel_0_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_79__GraphicsLevel_0_padding1_1_MASK 0xff0000
+#define DPM_TABLE_79__GraphicsLevel_0_padding1_1__SHIFT 0x10
+#define DPM_TABLE_79__GraphicsLevel_0_padding1_0_MASK 0xff000000
+#define DPM_TABLE_79__GraphicsLevel_0_padding1_0__SHIFT 0x18
+#define DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_86__GraphicsLevel_0_SclkDid_MASK 0xff000000
+#define DPM_TABLE_86__GraphicsLevel_0_SclkDid__SHIFT 0x18
+#define DPM_TABLE_87__GraphicsLevel_0_PowerThrottle_MASK 0xff
+#define DPM_TABLE_87__GraphicsLevel_0_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_87__GraphicsLevel_0_DownHyst_MASK 0xff0000
+#define DPM_TABLE_87__GraphicsLevel_0_DownHyst__SHIFT 0x10
+#define DPM_TABLE_87__GraphicsLevel_0_UpHyst_MASK 0xff000000
+#define DPM_TABLE_87__GraphicsLevel_0_UpHyst__SHIFT 0x18
+#define DPM_TABLE_88__GraphicsLevel_0_padding_2_MASK 0xff
+#define DPM_TABLE_88__GraphicsLevel_0_padding_2__SHIFT 0x0
+#define DPM_TABLE_88__GraphicsLevel_0_padding_1_MASK 0xff00
+#define DPM_TABLE_88__GraphicsLevel_0_padding_1__SHIFT 0x8
+#define DPM_TABLE_88__GraphicsLevel_0_padding_0_MASK 0xff0000
+#define DPM_TABLE_88__GraphicsLevel_0_padding_0__SHIFT 0x10
+#define DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId_MASK 0xff000000
+#define DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x18
+#define DPM_TABLE_89__GraphicsLevel_1_Flags_MASK 0xffffffff
+#define DPM_TABLE_89__GraphicsLevel_1_Flags__SHIFT 0x0
+#define DPM_TABLE_90__GraphicsLevel_1_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_90__GraphicsLevel_1_MinVddc__SHIFT 0x0
+#define DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_92__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_92__GraphicsLevel_1_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_93__GraphicsLevel_1_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_93__GraphicsLevel_1_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_93__GraphicsLevel_1_padding1_1_MASK 0xff0000
+#define DPM_TABLE_93__GraphicsLevel_1_padding1_1__SHIFT 0x10
+#define DPM_TABLE_93__GraphicsLevel_1_padding1_0_MASK 0xff000000
+#define DPM_TABLE_93__GraphicsLevel_1_padding1_0__SHIFT 0x18
+#define DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_100__GraphicsLevel_1_SclkDid_MASK 0xff000000
+#define DPM_TABLE_100__GraphicsLevel_1_SclkDid__SHIFT 0x18
+#define DPM_TABLE_101__GraphicsLevel_1_PowerThrottle_MASK 0xff
+#define DPM_TABLE_101__GraphicsLevel_1_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_101__GraphicsLevel_1_DownHyst_MASK 0xff0000
+#define DPM_TABLE_101__GraphicsLevel_1_DownHyst__SHIFT 0x10
+#define DPM_TABLE_101__GraphicsLevel_1_UpHyst_MASK 0xff000000
+#define DPM_TABLE_101__GraphicsLevel_1_UpHyst__SHIFT 0x18
+#define DPM_TABLE_102__GraphicsLevel_1_padding_2_MASK 0xff
+#define DPM_TABLE_102__GraphicsLevel_1_padding_2__SHIFT 0x0
+#define DPM_TABLE_102__GraphicsLevel_1_padding_1_MASK 0xff00
+#define DPM_TABLE_102__GraphicsLevel_1_padding_1__SHIFT 0x8
+#define DPM_TABLE_102__GraphicsLevel_1_padding_0_MASK 0xff0000
+#define DPM_TABLE_102__GraphicsLevel_1_padding_0__SHIFT 0x10
+#define DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId_MASK 0xff000000
+#define DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x18
+#define DPM_TABLE_103__GraphicsLevel_2_Flags_MASK 0xffffffff
+#define DPM_TABLE_103__GraphicsLevel_2_Flags__SHIFT 0x0
+#define DPM_TABLE_104__GraphicsLevel_2_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_104__GraphicsLevel_2_MinVddc__SHIFT 0x0
+#define DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_106__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_106__GraphicsLevel_2_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_107__GraphicsLevel_2_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_107__GraphicsLevel_2_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_107__GraphicsLevel_2_padding1_1_MASK 0xff0000
+#define DPM_TABLE_107__GraphicsLevel_2_padding1_1__SHIFT 0x10
+#define DPM_TABLE_107__GraphicsLevel_2_padding1_0_MASK 0xff000000
+#define DPM_TABLE_107__GraphicsLevel_2_padding1_0__SHIFT 0x18
+#define DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_114__GraphicsLevel_2_SclkDid_MASK 0xff000000
+#define DPM_TABLE_114__GraphicsLevel_2_SclkDid__SHIFT 0x18
+#define DPM_TABLE_115__GraphicsLevel_2_PowerThrottle_MASK 0xff
+#define DPM_TABLE_115__GraphicsLevel_2_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_115__GraphicsLevel_2_DownHyst_MASK 0xff0000
+#define DPM_TABLE_115__GraphicsLevel_2_DownHyst__SHIFT 0x10
+#define DPM_TABLE_115__GraphicsLevel_2_UpHyst_MASK 0xff000000
+#define DPM_TABLE_115__GraphicsLevel_2_UpHyst__SHIFT 0x18
+#define DPM_TABLE_116__GraphicsLevel_2_padding_2_MASK 0xff
+#define DPM_TABLE_116__GraphicsLevel_2_padding_2__SHIFT 0x0
+#define DPM_TABLE_116__GraphicsLevel_2_padding_1_MASK 0xff00
+#define DPM_TABLE_116__GraphicsLevel_2_padding_1__SHIFT 0x8
+#define DPM_TABLE_116__GraphicsLevel_2_padding_0_MASK 0xff0000
+#define DPM_TABLE_116__GraphicsLevel_2_padding_0__SHIFT 0x10
+#define DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId_MASK 0xff000000
+#define DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x18
+#define DPM_TABLE_117__GraphicsLevel_3_Flags_MASK 0xffffffff
+#define DPM_TABLE_117__GraphicsLevel_3_Flags__SHIFT 0x0
+#define DPM_TABLE_118__GraphicsLevel_3_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_118__GraphicsLevel_3_MinVddc__SHIFT 0x0
+#define DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_120__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_120__GraphicsLevel_3_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_121__GraphicsLevel_3_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_121__GraphicsLevel_3_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_121__GraphicsLevel_3_padding1_1_MASK 0xff0000
+#define DPM_TABLE_121__GraphicsLevel_3_padding1_1__SHIFT 0x10
+#define DPM_TABLE_121__GraphicsLevel_3_padding1_0_MASK 0xff000000
+#define DPM_TABLE_121__GraphicsLevel_3_padding1_0__SHIFT 0x18
+#define DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_128__GraphicsLevel_3_SclkDid_MASK 0xff000000
+#define DPM_TABLE_128__GraphicsLevel_3_SclkDid__SHIFT 0x18
+#define DPM_TABLE_129__GraphicsLevel_3_PowerThrottle_MASK 0xff
+#define DPM_TABLE_129__GraphicsLevel_3_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_129__GraphicsLevel_3_DownHyst_MASK 0xff0000
+#define DPM_TABLE_129__GraphicsLevel_3_DownHyst__SHIFT 0x10
+#define DPM_TABLE_129__GraphicsLevel_3_UpHyst_MASK 0xff000000
+#define DPM_TABLE_129__GraphicsLevel_3_UpHyst__SHIFT 0x18
+#define DPM_TABLE_130__GraphicsLevel_3_padding_2_MASK 0xff
+#define DPM_TABLE_130__GraphicsLevel_3_padding_2__SHIFT 0x0
+#define DPM_TABLE_130__GraphicsLevel_3_padding_1_MASK 0xff00
+#define DPM_TABLE_130__GraphicsLevel_3_padding_1__SHIFT 0x8
+#define DPM_TABLE_130__GraphicsLevel_3_padding_0_MASK 0xff0000
+#define DPM_TABLE_130__GraphicsLevel_3_padding_0__SHIFT 0x10
+#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId_MASK 0xff000000
+#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x18
+#define DPM_TABLE_131__GraphicsLevel_4_Flags_MASK 0xffffffff
+#define DPM_TABLE_131__GraphicsLevel_4_Flags__SHIFT 0x0
+#define DPM_TABLE_132__GraphicsLevel_4_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_132__GraphicsLevel_4_MinVddc__SHIFT 0x0
+#define DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_134__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_134__GraphicsLevel_4_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_135__GraphicsLevel_4_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_135__GraphicsLevel_4_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_135__GraphicsLevel_4_padding1_1_MASK 0xff0000
+#define DPM_TABLE_135__GraphicsLevel_4_padding1_1__SHIFT 0x10
+#define DPM_TABLE_135__GraphicsLevel_4_padding1_0_MASK 0xff000000
+#define DPM_TABLE_135__GraphicsLevel_4_padding1_0__SHIFT 0x18
+#define DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_142__GraphicsLevel_4_SclkDid_MASK 0xff000000
+#define DPM_TABLE_142__GraphicsLevel_4_SclkDid__SHIFT 0x18
+#define DPM_TABLE_143__GraphicsLevel_4_PowerThrottle_MASK 0xff
+#define DPM_TABLE_143__GraphicsLevel_4_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_143__GraphicsLevel_4_DownHyst_MASK 0xff0000
+#define DPM_TABLE_143__GraphicsLevel_4_DownHyst__SHIFT 0x10
+#define DPM_TABLE_143__GraphicsLevel_4_UpHyst_MASK 0xff000000
+#define DPM_TABLE_143__GraphicsLevel_4_UpHyst__SHIFT 0x18
+#define DPM_TABLE_144__GraphicsLevel_4_padding_2_MASK 0xff
+#define DPM_TABLE_144__GraphicsLevel_4_padding_2__SHIFT 0x0
+#define DPM_TABLE_144__GraphicsLevel_4_padding_1_MASK 0xff00
+#define DPM_TABLE_144__GraphicsLevel_4_padding_1__SHIFT 0x8
+#define DPM_TABLE_144__GraphicsLevel_4_padding_0_MASK 0xff0000
+#define DPM_TABLE_144__GraphicsLevel_4_padding_0__SHIFT 0x10
+#define DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId_MASK 0xff000000
+#define DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x18
+#define DPM_TABLE_145__GraphicsLevel_5_Flags_MASK 0xffffffff
+#define DPM_TABLE_145__GraphicsLevel_5_Flags__SHIFT 0x0
+#define DPM_TABLE_146__GraphicsLevel_5_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_146__GraphicsLevel_5_MinVddc__SHIFT 0x0
+#define DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_148__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_148__GraphicsLevel_5_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_149__GraphicsLevel_5_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_149__GraphicsLevel_5_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_149__GraphicsLevel_5_padding1_1_MASK 0xff0000
+#define DPM_TABLE_149__GraphicsLevel_5_padding1_1__SHIFT 0x10
+#define DPM_TABLE_149__GraphicsLevel_5_padding1_0_MASK 0xff000000
+#define DPM_TABLE_149__GraphicsLevel_5_padding1_0__SHIFT 0x18
+#define DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_156__GraphicsLevel_5_SclkDid_MASK 0xff000000
+#define DPM_TABLE_156__GraphicsLevel_5_SclkDid__SHIFT 0x18
+#define DPM_TABLE_157__GraphicsLevel_5_PowerThrottle_MASK 0xff
+#define DPM_TABLE_157__GraphicsLevel_5_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_157__GraphicsLevel_5_DownHyst_MASK 0xff0000
+#define DPM_TABLE_157__GraphicsLevel_5_DownHyst__SHIFT 0x10
+#define DPM_TABLE_157__GraphicsLevel_5_UpHyst_MASK 0xff000000
+#define DPM_TABLE_157__GraphicsLevel_5_UpHyst__SHIFT 0x18
+#define DPM_TABLE_158__GraphicsLevel_5_padding_2_MASK 0xff
+#define DPM_TABLE_158__GraphicsLevel_5_padding_2__SHIFT 0x0
+#define DPM_TABLE_158__GraphicsLevel_5_padding_1_MASK 0xff00
+#define DPM_TABLE_158__GraphicsLevel_5_padding_1__SHIFT 0x8
+#define DPM_TABLE_158__GraphicsLevel_5_padding_0_MASK 0xff0000
+#define DPM_TABLE_158__GraphicsLevel_5_padding_0__SHIFT 0x10
+#define DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId_MASK 0xff000000
+#define DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x18
+#define DPM_TABLE_159__GraphicsLevel_6_Flags_MASK 0xffffffff
+#define DPM_TABLE_159__GraphicsLevel_6_Flags__SHIFT 0x0
+#define DPM_TABLE_160__GraphicsLevel_6_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_160__GraphicsLevel_6_MinVddc__SHIFT 0x0
+#define DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_163__GraphicsLevel_6_padding1_1_MASK 0xff0000
+#define DPM_TABLE_163__GraphicsLevel_6_padding1_1__SHIFT 0x10
+#define DPM_TABLE_163__GraphicsLevel_6_padding1_0_MASK 0xff000000
+#define DPM_TABLE_163__GraphicsLevel_6_padding1_0__SHIFT 0x18
+#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_170__GraphicsLevel_6_SclkDid_MASK 0xff000000
+#define DPM_TABLE_170__GraphicsLevel_6_SclkDid__SHIFT 0x18
+#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle_MASK 0xff
+#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_171__GraphicsLevel_6_DownHyst_MASK 0xff0000
+#define DPM_TABLE_171__GraphicsLevel_6_DownHyst__SHIFT 0x10
+#define DPM_TABLE_171__GraphicsLevel_6_UpHyst_MASK 0xff000000
+#define DPM_TABLE_171__GraphicsLevel_6_UpHyst__SHIFT 0x18
+#define DPM_TABLE_172__GraphicsLevel_6_padding_2_MASK 0xff
+#define DPM_TABLE_172__GraphicsLevel_6_padding_2__SHIFT 0x0
+#define DPM_TABLE_172__GraphicsLevel_6_padding_1_MASK 0xff00
+#define DPM_TABLE_172__GraphicsLevel_6_padding_1__SHIFT 0x8
+#define DPM_TABLE_172__GraphicsLevel_6_padding_0_MASK 0xff0000
+#define DPM_TABLE_172__GraphicsLevel_6_padding_0__SHIFT 0x10
+#define DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId_MASK 0xff000000
+#define DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x18
+#define DPM_TABLE_173__GraphicsLevel_7_Flags_MASK 0xffffffff
+#define DPM_TABLE_173__GraphicsLevel_7_Flags__SHIFT 0x0
+#define DPM_TABLE_174__GraphicsLevel_7_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_174__GraphicsLevel_7_MinVddc__SHIFT 0x0
+#define DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_176__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_176__GraphicsLevel_7_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_177__GraphicsLevel_7_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_177__GraphicsLevel_7_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_177__GraphicsLevel_7_padding1_1_MASK 0xff0000
+#define DPM_TABLE_177__GraphicsLevel_7_padding1_1__SHIFT 0x10
+#define DPM_TABLE_177__GraphicsLevel_7_padding1_0_MASK 0xff000000
+#define DPM_TABLE_177__GraphicsLevel_7_padding1_0__SHIFT 0x18
+#define DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_184__GraphicsLevel_7_SclkDid_MASK 0xff000000
+#define DPM_TABLE_184__GraphicsLevel_7_SclkDid__SHIFT 0x18
+#define DPM_TABLE_185__GraphicsLevel_7_PowerThrottle_MASK 0xff
+#define DPM_TABLE_185__GraphicsLevel_7_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_185__GraphicsLevel_7_DownHyst_MASK 0xff0000
+#define DPM_TABLE_185__GraphicsLevel_7_DownHyst__SHIFT 0x10
+#define DPM_TABLE_185__GraphicsLevel_7_UpHyst_MASK 0xff000000
+#define DPM_TABLE_185__GraphicsLevel_7_UpHyst__SHIFT 0x18
+#define DPM_TABLE_186__GraphicsLevel_7_padding_2_MASK 0xff
+#define DPM_TABLE_186__GraphicsLevel_7_padding_2__SHIFT 0x0
+#define DPM_TABLE_186__GraphicsLevel_7_padding_1_MASK 0xff00
+#define DPM_TABLE_186__GraphicsLevel_7_padding_1__SHIFT 0x8
+#define DPM_TABLE_186__GraphicsLevel_7_padding_0_MASK 0xff0000
+#define DPM_TABLE_186__GraphicsLevel_7_padding_0__SHIFT 0x10
+#define DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId_MASK 0xff000000
+#define DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x18
+#define DPM_TABLE_187__MemoryACPILevel_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_187__MemoryACPILevel_MinVddc__SHIFT 0x0
+#define DPM_TABLE_188__MemoryACPILevel_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_188__MemoryACPILevel_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_189__MemoryACPILevel_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_189__MemoryACPILevel_MinVddci__SHIFT 0x0
+#define DPM_TABLE_190__MemoryACPILevel_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_190__MemoryACPILevel_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_191__MemoryACPILevel_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_191__MemoryACPILevel_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_192__MemoryACPILevel_StutterEnable_MASK 0xff
+#define DPM_TABLE_192__MemoryACPILevel_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_192__MemoryACPILevel_RttEnable_MASK 0xff00
+#define DPM_TABLE_192__MemoryACPILevel_RttEnable__SHIFT 0x8
+#define DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_192__MemoryACPILevel_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_192__MemoryACPILevel_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_193__MemoryACPILevel_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_193__MemoryACPILevel_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_193__MemoryACPILevel_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_193__MemoryACPILevel_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_193__MemoryACPILevel_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_193__MemoryACPILevel_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_194__MemoryACPILevel_padding_MASK 0xff
+#define DPM_TABLE_194__MemoryACPILevel_padding__SHIFT 0x0
+#define DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_194__MemoryACPILevel_DownHyst_MASK 0xff0000
+#define DPM_TABLE_194__MemoryACPILevel_DownHyst__SHIFT 0x10
+#define DPM_TABLE_194__MemoryACPILevel_UpHyst_MASK 0xff000000
+#define DPM_TABLE_194__MemoryACPILevel_UpHyst__SHIFT 0x18
+#define DPM_TABLE_195__MemoryACPILevel_padding1_1_MASK 0xff
+#define DPM_TABLE_195__MemoryACPILevel_padding1_1__SHIFT 0x0
+#define DPM_TABLE_195__MemoryACPILevel_padding1_0_MASK 0xff00
+#define DPM_TABLE_195__MemoryACPILevel_padding1_0__SHIFT 0x8
+#define DPM_TABLE_195__MemoryACPILevel_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_195__MemoryACPILevel_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_202__MemoryACPILevel_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_202__MemoryACPILevel_DllCntl__SHIFT 0x0
+#define DPM_TABLE_203__MemoryACPILevel_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_203__MemoryACPILevel_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_204__MemoryACPILevel_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_204__MemoryACPILevel_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_205__MemoryLevel_0_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_205__MemoryLevel_0_MinVddc__SHIFT 0x0
+#define DPM_TABLE_206__MemoryLevel_0_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_206__MemoryLevel_0_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_207__MemoryLevel_0_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_207__MemoryLevel_0_MinVddci__SHIFT 0x0
+#define DPM_TABLE_208__MemoryLevel_0_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_208__MemoryLevel_0_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_209__MemoryLevel_0_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_209__MemoryLevel_0_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_210__MemoryLevel_0_StutterEnable_MASK 0xff
+#define DPM_TABLE_210__MemoryLevel_0_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_210__MemoryLevel_0_RttEnable_MASK 0xff00
+#define DPM_TABLE_210__MemoryLevel_0_RttEnable__SHIFT 0x8
+#define DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_210__MemoryLevel_0_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_210__MemoryLevel_0_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_211__MemoryLevel_0_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_211__MemoryLevel_0_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_211__MemoryLevel_0_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_211__MemoryLevel_0_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_211__MemoryLevel_0_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_211__MemoryLevel_0_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_212__MemoryLevel_0_padding_MASK 0xff
+#define DPM_TABLE_212__MemoryLevel_0_padding__SHIFT 0x0
+#define DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_212__MemoryLevel_0_DownHyst_MASK 0xff0000
+#define DPM_TABLE_212__MemoryLevel_0_DownHyst__SHIFT 0x10
+#define DPM_TABLE_212__MemoryLevel_0_UpHyst_MASK 0xff000000
+#define DPM_TABLE_212__MemoryLevel_0_UpHyst__SHIFT 0x18
+#define DPM_TABLE_213__MemoryLevel_0_padding1_1_MASK 0xff
+#define DPM_TABLE_213__MemoryLevel_0_padding1_1__SHIFT 0x0
+#define DPM_TABLE_213__MemoryLevel_0_padding1_0_MASK 0xff00
+#define DPM_TABLE_213__MemoryLevel_0_padding1_0__SHIFT 0x8
+#define DPM_TABLE_213__MemoryLevel_0_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_213__MemoryLevel_0_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_220__MemoryLevel_0_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_220__MemoryLevel_0_DllCntl__SHIFT 0x0
+#define DPM_TABLE_221__MemoryLevel_0_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_221__MemoryLevel_0_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_222__MemoryLevel_0_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_222__MemoryLevel_0_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_223__MemoryLevel_1_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_223__MemoryLevel_1_MinVddc__SHIFT 0x0
+#define DPM_TABLE_224__MemoryLevel_1_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_224__MemoryLevel_1_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_225__MemoryLevel_1_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_225__MemoryLevel_1_MinVddci__SHIFT 0x0
+#define DPM_TABLE_226__MemoryLevel_1_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_226__MemoryLevel_1_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_227__MemoryLevel_1_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_227__MemoryLevel_1_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_228__MemoryLevel_1_StutterEnable_MASK 0xff
+#define DPM_TABLE_228__MemoryLevel_1_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_228__MemoryLevel_1_RttEnable_MASK 0xff00
+#define DPM_TABLE_228__MemoryLevel_1_RttEnable__SHIFT 0x8
+#define DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_228__MemoryLevel_1_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_228__MemoryLevel_1_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_229__MemoryLevel_1_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_229__MemoryLevel_1_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_229__MemoryLevel_1_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_229__MemoryLevel_1_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_229__MemoryLevel_1_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_229__MemoryLevel_1_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_230__MemoryLevel_1_padding_MASK 0xff
+#define DPM_TABLE_230__MemoryLevel_1_padding__SHIFT 0x0
+#define DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_230__MemoryLevel_1_DownHyst_MASK 0xff0000
+#define DPM_TABLE_230__MemoryLevel_1_DownHyst__SHIFT 0x10
+#define DPM_TABLE_230__MemoryLevel_1_UpHyst_MASK 0xff000000
+#define DPM_TABLE_230__MemoryLevel_1_UpHyst__SHIFT 0x18
+#define DPM_TABLE_231__MemoryLevel_1_padding1_1_MASK 0xff
+#define DPM_TABLE_231__MemoryLevel_1_padding1_1__SHIFT 0x0
+#define DPM_TABLE_231__MemoryLevel_1_padding1_0_MASK 0xff00
+#define DPM_TABLE_231__MemoryLevel_1_padding1_0__SHIFT 0x8
+#define DPM_TABLE_231__MemoryLevel_1_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_231__MemoryLevel_1_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_238__MemoryLevel_1_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_238__MemoryLevel_1_DllCntl__SHIFT 0x0
+#define DPM_TABLE_239__MemoryLevel_1_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_239__MemoryLevel_1_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_240__MemoryLevel_1_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_240__MemoryLevel_1_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_241__MemoryLevel_2_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_241__MemoryLevel_2_MinVddc__SHIFT 0x0
+#define DPM_TABLE_242__MemoryLevel_2_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_242__MemoryLevel_2_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_243__MemoryLevel_2_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_243__MemoryLevel_2_MinVddci__SHIFT 0x0
+#define DPM_TABLE_244__MemoryLevel_2_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_244__MemoryLevel_2_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_245__MemoryLevel_2_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_245__MemoryLevel_2_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_246__MemoryLevel_2_StutterEnable_MASK 0xff
+#define DPM_TABLE_246__MemoryLevel_2_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_246__MemoryLevel_2_RttEnable_MASK 0xff00
+#define DPM_TABLE_246__MemoryLevel_2_RttEnable__SHIFT 0x8
+#define DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_246__MemoryLevel_2_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_246__MemoryLevel_2_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_247__MemoryLevel_2_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_247__MemoryLevel_2_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_247__MemoryLevel_2_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_247__MemoryLevel_2_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_247__MemoryLevel_2_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_247__MemoryLevel_2_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_248__MemoryLevel_2_padding_MASK 0xff
+#define DPM_TABLE_248__MemoryLevel_2_padding__SHIFT 0x0
+#define DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_248__MemoryLevel_2_DownHyst_MASK 0xff0000
+#define DPM_TABLE_248__MemoryLevel_2_DownHyst__SHIFT 0x10
+#define DPM_TABLE_248__MemoryLevel_2_UpHyst_MASK 0xff000000
+#define DPM_TABLE_248__MemoryLevel_2_UpHyst__SHIFT 0x18
+#define DPM_TABLE_249__MemoryLevel_2_padding1_1_MASK 0xff
+#define DPM_TABLE_249__MemoryLevel_2_padding1_1__SHIFT 0x0
+#define DPM_TABLE_249__MemoryLevel_2_padding1_0_MASK 0xff00
+#define DPM_TABLE_249__MemoryLevel_2_padding1_0__SHIFT 0x8
+#define DPM_TABLE_249__MemoryLevel_2_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_249__MemoryLevel_2_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_256__MemoryLevel_2_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_256__MemoryLevel_2_DllCntl__SHIFT 0x0
+#define DPM_TABLE_257__MemoryLevel_2_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_257__MemoryLevel_2_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_258__MemoryLevel_2_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_258__MemoryLevel_2_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_259__MemoryLevel_3_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_259__MemoryLevel_3_MinVddc__SHIFT 0x0
+#define DPM_TABLE_260__MemoryLevel_3_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_260__MemoryLevel_3_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_261__MemoryLevel_3_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_261__MemoryLevel_3_MinVddci__SHIFT 0x0
+#define DPM_TABLE_262__MemoryLevel_3_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_262__MemoryLevel_3_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_263__MemoryLevel_3_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_263__MemoryLevel_3_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_264__MemoryLevel_3_StutterEnable_MASK 0xff
+#define DPM_TABLE_264__MemoryLevel_3_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_264__MemoryLevel_3_RttEnable_MASK 0xff00
+#define DPM_TABLE_264__MemoryLevel_3_RttEnable__SHIFT 0x8
+#define DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_264__MemoryLevel_3_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_264__MemoryLevel_3_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_265__MemoryLevel_3_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_265__MemoryLevel_3_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_265__MemoryLevel_3_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_265__MemoryLevel_3_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_265__MemoryLevel_3_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_265__MemoryLevel_3_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_266__MemoryLevel_3_padding_MASK 0xff
+#define DPM_TABLE_266__MemoryLevel_3_padding__SHIFT 0x0
+#define DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_266__MemoryLevel_3_DownHyst_MASK 0xff0000
+#define DPM_TABLE_266__MemoryLevel_3_DownHyst__SHIFT 0x10
+#define DPM_TABLE_266__MemoryLevel_3_UpHyst_MASK 0xff000000
+#define DPM_TABLE_266__MemoryLevel_3_UpHyst__SHIFT 0x18
+#define DPM_TABLE_267__MemoryLevel_3_padding1_1_MASK 0xff
+#define DPM_TABLE_267__MemoryLevel_3_padding1_1__SHIFT 0x0
+#define DPM_TABLE_267__MemoryLevel_3_padding1_0_MASK 0xff00
+#define DPM_TABLE_267__MemoryLevel_3_padding1_0__SHIFT 0x8
+#define DPM_TABLE_267__MemoryLevel_3_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_267__MemoryLevel_3_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_274__MemoryLevel_3_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_274__MemoryLevel_3_DllCntl__SHIFT 0x0
+#define DPM_TABLE_275__MemoryLevel_3_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_275__MemoryLevel_3_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_276__MemoryLevel_3_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_276__MemoryLevel_3_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_277__MemoryLevel_4_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_277__MemoryLevel_4_MinVddc__SHIFT 0x0
+#define DPM_TABLE_278__MemoryLevel_4_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_278__MemoryLevel_4_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_279__MemoryLevel_4_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_279__MemoryLevel_4_MinVddci__SHIFT 0x0
+#define DPM_TABLE_280__MemoryLevel_4_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_280__MemoryLevel_4_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_281__MemoryLevel_4_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_281__MemoryLevel_4_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_282__MemoryLevel_4_StutterEnable_MASK 0xff
+#define DPM_TABLE_282__MemoryLevel_4_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_282__MemoryLevel_4_RttEnable_MASK 0xff00
+#define DPM_TABLE_282__MemoryLevel_4_RttEnable__SHIFT 0x8
+#define DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_282__MemoryLevel_4_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_282__MemoryLevel_4_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_283__MemoryLevel_4_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_283__MemoryLevel_4_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_283__MemoryLevel_4_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_283__MemoryLevel_4_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_283__MemoryLevel_4_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_283__MemoryLevel_4_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_284__MemoryLevel_4_padding_MASK 0xff
+#define DPM_TABLE_284__MemoryLevel_4_padding__SHIFT 0x0
+#define DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_284__MemoryLevel_4_DownHyst_MASK 0xff0000
+#define DPM_TABLE_284__MemoryLevel_4_DownHyst__SHIFT 0x10
+#define DPM_TABLE_284__MemoryLevel_4_UpHyst_MASK 0xff000000
+#define DPM_TABLE_284__MemoryLevel_4_UpHyst__SHIFT 0x18
+#define DPM_TABLE_285__MemoryLevel_4_padding1_1_MASK 0xff
+#define DPM_TABLE_285__MemoryLevel_4_padding1_1__SHIFT 0x0
+#define DPM_TABLE_285__MemoryLevel_4_padding1_0_MASK 0xff00
+#define DPM_TABLE_285__MemoryLevel_4_padding1_0__SHIFT 0x8
+#define DPM_TABLE_285__MemoryLevel_4_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_285__MemoryLevel_4_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_292__MemoryLevel_4_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_292__MemoryLevel_4_DllCntl__SHIFT 0x0
+#define DPM_TABLE_293__MemoryLevel_4_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_293__MemoryLevel_4_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_294__MemoryLevel_4_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_294__MemoryLevel_4_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_295__MemoryLevel_5_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_295__MemoryLevel_5_MinVddc__SHIFT 0x0
+#define DPM_TABLE_296__MemoryLevel_5_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_296__MemoryLevel_5_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_297__MemoryLevel_5_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_297__MemoryLevel_5_MinVddci__SHIFT 0x0
+#define DPM_TABLE_298__MemoryLevel_5_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_298__MemoryLevel_5_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_299__MemoryLevel_5_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_299__MemoryLevel_5_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_300__MemoryLevel_5_StutterEnable_MASK 0xff
+#define DPM_TABLE_300__MemoryLevel_5_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_300__MemoryLevel_5_RttEnable_MASK 0xff00
+#define DPM_TABLE_300__MemoryLevel_5_RttEnable__SHIFT 0x8
+#define DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_300__MemoryLevel_5_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_300__MemoryLevel_5_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_301__MemoryLevel_5_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_301__MemoryLevel_5_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_301__MemoryLevel_5_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_301__MemoryLevel_5_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_301__MemoryLevel_5_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_301__MemoryLevel_5_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_302__MemoryLevel_5_padding_MASK 0xff
+#define DPM_TABLE_302__MemoryLevel_5_padding__SHIFT 0x0
+#define DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_302__MemoryLevel_5_DownHyst_MASK 0xff0000
+#define DPM_TABLE_302__MemoryLevel_5_DownHyst__SHIFT 0x10
+#define DPM_TABLE_302__MemoryLevel_5_UpHyst_MASK 0xff000000
+#define DPM_TABLE_302__MemoryLevel_5_UpHyst__SHIFT 0x18
+#define DPM_TABLE_303__MemoryLevel_5_padding1_1_MASK 0xff
+#define DPM_TABLE_303__MemoryLevel_5_padding1_1__SHIFT 0x0
+#define DPM_TABLE_303__MemoryLevel_5_padding1_0_MASK 0xff00
+#define DPM_TABLE_303__MemoryLevel_5_padding1_0__SHIFT 0x8
+#define DPM_TABLE_303__MemoryLevel_5_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_303__MemoryLevel_5_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_310__MemoryLevel_5_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_310__MemoryLevel_5_DllCntl__SHIFT 0x0
+#define DPM_TABLE_311__MemoryLevel_5_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_311__MemoryLevel_5_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_312__MemoryLevel_5_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_312__MemoryLevel_5_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_313__LinkLevel_0_Padding_MASK 0xff
+#define DPM_TABLE_313__LinkLevel_0_Padding__SHIFT 0x0
+#define DPM_TABLE_313__LinkLevel_0_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_313__LinkLevel_0_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_313__LinkLevel_0_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_313__LinkLevel_0_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_313__LinkLevel_0_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_313__LinkLevel_0_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_314__LinkLevel_0_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_314__LinkLevel_0_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_315__LinkLevel_0_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_315__LinkLevel_0_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_316__LinkLevel_0_Reserved_MASK 0xffffffff
+#define DPM_TABLE_316__LinkLevel_0_Reserved__SHIFT 0x0
+#define DPM_TABLE_317__LinkLevel_1_Padding_MASK 0xff
+#define DPM_TABLE_317__LinkLevel_1_Padding__SHIFT 0x0
+#define DPM_TABLE_317__LinkLevel_1_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_317__LinkLevel_1_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_317__LinkLevel_1_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_317__LinkLevel_1_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_317__LinkLevel_1_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_317__LinkLevel_1_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_318__LinkLevel_1_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_318__LinkLevel_1_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_319__LinkLevel_1_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_319__LinkLevel_1_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_320__LinkLevel_1_Reserved_MASK 0xffffffff
+#define DPM_TABLE_320__LinkLevel_1_Reserved__SHIFT 0x0
+#define DPM_TABLE_321__LinkLevel_2_Padding_MASK 0xff
+#define DPM_TABLE_321__LinkLevel_2_Padding__SHIFT 0x0
+#define DPM_TABLE_321__LinkLevel_2_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_321__LinkLevel_2_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_321__LinkLevel_2_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_321__LinkLevel_2_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_321__LinkLevel_2_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_321__LinkLevel_2_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_322__LinkLevel_2_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_322__LinkLevel_2_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_323__LinkLevel_2_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_323__LinkLevel_2_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_324__LinkLevel_2_Reserved_MASK 0xffffffff
+#define DPM_TABLE_324__LinkLevel_2_Reserved__SHIFT 0x0
+#define DPM_TABLE_325__LinkLevel_3_Padding_MASK 0xff
+#define DPM_TABLE_325__LinkLevel_3_Padding__SHIFT 0x0
+#define DPM_TABLE_325__LinkLevel_3_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_325__LinkLevel_3_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_325__LinkLevel_3_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_325__LinkLevel_3_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_325__LinkLevel_3_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_325__LinkLevel_3_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_326__LinkLevel_3_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_326__LinkLevel_3_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_327__LinkLevel_3_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_327__LinkLevel_3_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_328__LinkLevel_3_Reserved_MASK 0xffffffff
+#define DPM_TABLE_328__LinkLevel_3_Reserved__SHIFT 0x0
+#define DPM_TABLE_329__LinkLevel_4_Padding_MASK 0xff
+#define DPM_TABLE_329__LinkLevel_4_Padding__SHIFT 0x0
+#define DPM_TABLE_329__LinkLevel_4_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_329__LinkLevel_4_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_329__LinkLevel_4_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_329__LinkLevel_4_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_329__LinkLevel_4_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_329__LinkLevel_4_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_330__LinkLevel_4_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_330__LinkLevel_4_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_331__LinkLevel_4_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_331__LinkLevel_4_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_332__LinkLevel_4_Reserved_MASK 0xffffffff
+#define DPM_TABLE_332__LinkLevel_4_Reserved__SHIFT 0x0
+#define DPM_TABLE_333__LinkLevel_5_Padding_MASK 0xff
+#define DPM_TABLE_333__LinkLevel_5_Padding__SHIFT 0x0
+#define DPM_TABLE_333__LinkLevel_5_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_333__LinkLevel_5_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_333__LinkLevel_5_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_333__LinkLevel_5_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_333__LinkLevel_5_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_333__LinkLevel_5_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_334__LinkLevel_5_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_334__LinkLevel_5_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_335__LinkLevel_5_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_335__LinkLevel_5_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_336__LinkLevel_5_Reserved_MASK 0xffffffff
+#define DPM_TABLE_336__LinkLevel_5_Reserved__SHIFT 0x0
+#define DPM_TABLE_337__LinkLevel_6_Padding_MASK 0xff
+#define DPM_TABLE_337__LinkLevel_6_Padding__SHIFT 0x0
+#define DPM_TABLE_337__LinkLevel_6_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_337__LinkLevel_6_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_337__LinkLevel_6_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_337__LinkLevel_6_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_337__LinkLevel_6_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_337__LinkLevel_6_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_338__LinkLevel_6_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_338__LinkLevel_6_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_339__LinkLevel_6_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_339__LinkLevel_6_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_340__LinkLevel_6_Reserved_MASK 0xffffffff
+#define DPM_TABLE_340__LinkLevel_6_Reserved__SHIFT 0x0
+#define DPM_TABLE_341__LinkLevel_7_Padding_MASK 0xff
+#define DPM_TABLE_341__LinkLevel_7_Padding__SHIFT 0x0
+#define DPM_TABLE_341__LinkLevel_7_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_341__LinkLevel_7_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_341__LinkLevel_7_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_341__LinkLevel_7_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_341__LinkLevel_7_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_341__LinkLevel_7_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_342__LinkLevel_7_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_342__LinkLevel_7_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_343__LinkLevel_7_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_343__LinkLevel_7_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_344__LinkLevel_7_Reserved_MASK 0xffffffff
+#define DPM_TABLE_344__LinkLevel_7_Reserved__SHIFT 0x0
+#define DPM_TABLE_345__ACPILevel_Flags_MASK 0xffffffff
+#define DPM_TABLE_345__ACPILevel_Flags__SHIFT 0x0
+#define DPM_TABLE_346__ACPILevel_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_346__ACPILevel_MinVddc__SHIFT 0x0
+#define DPM_TABLE_347__ACPILevel_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_347__ACPILevel_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_348__ACPILevel_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_348__ACPILevel_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_349__ACPILevel_padding_MASK 0xff
+#define DPM_TABLE_349__ACPILevel_padding__SHIFT 0x0
+#define DPM_TABLE_349__ACPILevel_DeepSleepDivId_MASK 0xff00
+#define DPM_TABLE_349__ACPILevel_DeepSleepDivId__SHIFT 0x8
+#define DPM_TABLE_349__ACPILevel_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_349__ACPILevel_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_349__ACPILevel_SclkDid_MASK 0xff000000
+#define DPM_TABLE_349__ACPILevel_SclkDid__SHIFT 0x18
+#define DPM_TABLE_350__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_350__ACPILevel_CgSpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff
+#define DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0
+#define DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_356__ACPILevel_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_356__ACPILevel_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_357__ACPILevel_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_357__ACPILevel_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_358__UvdLevel_0_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_358__UvdLevel_0_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_359__UvdLevel_0_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_359__UvdLevel_0_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_360__UvdLevel_0_VclkDivider_MASK 0xff
+#define DPM_TABLE_360__UvdLevel_0_VclkDivider__SHIFT 0x0
+#define DPM_TABLE_360__UvdLevel_0_MinVddcPhases_MASK 0xff00
+#define DPM_TABLE_360__UvdLevel_0_MinVddcPhases__SHIFT 0x8
+#define DPM_TABLE_360__UvdLevel_0_MinVddc_MASK 0xffff0000
+#define DPM_TABLE_360__UvdLevel_0_MinVddc__SHIFT 0x10
+#define DPM_TABLE_361__UvdLevel_0_padding_2_MASK 0xff
+#define DPM_TABLE_361__UvdLevel_0_padding_2__SHIFT 0x0
+#define DPM_TABLE_361__UvdLevel_0_padding_1_MASK 0xff00
+#define DPM_TABLE_361__UvdLevel_0_padding_1__SHIFT 0x8
+#define DPM_TABLE_361__UvdLevel_0_padding_0_MASK 0xff0000
+#define DPM_TABLE_361__UvdLevel_0_padding_0__SHIFT 0x10
+#define DPM_TABLE_361__UvdLevel_0_DclkDivider_MASK 0xff000000
+#define DPM_TABLE_361__UvdLevel_0_DclkDivider__SHIFT 0x18
+#define DPM_TABLE_362__UvdLevel_1_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_362__UvdLevel_1_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_363__UvdLevel_1_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_363__UvdLevel_1_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_364__UvdLevel_1_VclkDivider_MASK 0xff
+#define DPM_TABLE_364__UvdLevel_1_VclkDivider__SHIFT 0x0
+#define DPM_TABLE_364__UvdLevel_1_MinVddcPhases_MASK 0xff00
+#define DPM_TABLE_364__UvdLevel_1_MinVddcPhases__SHIFT 0x8
+#define DPM_TABLE_364__UvdLevel_1_MinVddc_MASK 0xffff0000
+#define DPM_TABLE_364__UvdLevel_1_MinVddc__SHIFT 0x10
+#define DPM_TABLE_365__UvdLevel_1_padding_2_MASK 0xff
+#define DPM_TABLE_365__UvdLevel_1_padding_2__SHIFT 0x0
+#define DPM_TABLE_365__UvdLevel_1_padding_1_MASK 0xff00
+#define DPM_TABLE_365__UvdLevel_1_padding_1__SHIFT 0x8
+#define DPM_TABLE_365__UvdLevel_1_padding_0_MASK 0xff0000
+#define DPM_TABLE_365__UvdLevel_1_padding_0__SHIFT 0x10
+#define DPM_TABLE_365__UvdLevel_1_DclkDivider_MASK 0xff000000
+#define DPM_TABLE_365__UvdLevel_1_DclkDivider__SHIFT 0x18
+#define DPM_TABLE_366__UvdLevel_2_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_366__UvdLevel_2_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_367__UvdLevel_2_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_367__UvdLevel_2_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_368__UvdLevel_2_VclkDivider_MASK 0xff
+#define DPM_TABLE_368__UvdLevel_2_VclkDivider__SHIFT 0x0
+#define DPM_TABLE_368__UvdLevel_2_MinVddcPhases_MASK 0xff00
+#define DPM_TABLE_368__UvdLevel_2_MinVddcPhases__SHIFT 0x8
+#define DPM_TABLE_368__UvdLevel_2_MinVddc_MASK 0xffff0000
+#define DPM_TABLE_368__UvdLevel_2_MinVddc__SHIFT 0x10
+#define DPM_TABLE_369__UvdLevel_2_padding_2_MASK 0xff
+#define DPM_TABLE_369__UvdLevel_2_padding_2__SHIFT 0x0
+#define DPM_TABLE_369__UvdLevel_2_padding_1_MASK 0xff00
+#define DPM_TABLE_369__UvdLevel_2_padding_1__SHIFT 0x8
+#define DPM_TABLE_369__UvdLevel_2_padding_0_MASK 0xff0000
+#define DPM_TABLE_369__UvdLevel_2_padding_0__SHIFT 0x10
+#define DPM_TABLE_369__UvdLevel_2_DclkDivider_MASK 0xff000000
+#define DPM_TABLE_369__UvdLevel_2_DclkDivider__SHIFT 0x18
+#define DPM_TABLE_370__UvdLevel_3_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_370__UvdLevel_3_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_371__UvdLevel_3_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_371__UvdLevel_3_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_372__UvdLevel_3_VclkDivider_MASK 0xff
+#define DPM_TABLE_372__UvdLevel_3_VclkDivider__SHIFT 0x0
+#define DPM_TABLE_372__UvdLevel_3_MinVddcPhases_MASK 0xff00
+#define DPM_TABLE_372__UvdLevel_3_MinVddcPhases__SHIFT 0x8
+#define DPM_TABLE_372__UvdLevel_3_MinVddc_MASK 0xffff0000
+#define DPM_TABLE_372__UvdLevel_3_MinVddc__SHIFT 0x10
+#define DPM_TABLE_373__UvdLevel_3_padding_2_MASK 0xff
+#define DPM_TABLE_373__UvdLevel_3_padding_2__SHIFT 0x0
+#define DPM_TABLE_373__UvdLevel_3_padding_1_MASK 0xff00
+#define DPM_TABLE_373__UvdLevel_3_padding_1__SHIFT 0x8
+#define DPM_TABLE_373__UvdLevel_3_padding_0_MASK 0xff0000
+#define DPM_TABLE_373__UvdLevel_3_padding_0__SHIFT 0x10
+#define DPM_TABLE_373__UvdLevel_3_DclkDivider_MASK 0xff000000
+#define DPM_TABLE_373__UvdLevel_3_DclkDivider__SHIFT 0x18
+#define DPM_TABLE_374__UvdLevel_4_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_374__UvdLevel_4_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_375__UvdLevel_4_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_375__UvdLevel_4_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_376__UvdLevel_4_VclkDivider_MASK 0xff
+#define DPM_TABLE_376__UvdLevel_4_VclkDivider__SHIFT 0x0
+#define DPM_TABLE_376__UvdLevel_4_MinVddcPhases_MASK 0xff00
+#define DPM_TABLE_376__UvdLevel_4_MinVddcPhases__SHIFT 0x8
+#define DPM_TABLE_376__UvdLevel_4_MinVddc_MASK 0xffff0000
+#define DPM_TABLE_376__UvdLevel_4_MinVddc__SHIFT 0x10
+#define DPM_TABLE_377__UvdLevel_4_padding_2_MASK 0xff
+#define DPM_TABLE_377__UvdLevel_4_padding_2__SHIFT 0x0
+#define DPM_TABLE_377__UvdLevel_4_padding_1_MASK 0xff00
+#define DPM_TABLE_377__UvdLevel_4_padding_1__SHIFT 0x8
+#define DPM_TABLE_377__UvdLevel_4_padding_0_MASK 0xff0000
+#define DPM_TABLE_377__UvdLevel_4_padding_0__SHIFT 0x10
+#define DPM_TABLE_377__UvdLevel_4_DclkDivider_MASK 0xff000000
+#define DPM_TABLE_377__UvdLevel_4_DclkDivider__SHIFT 0x18
+#define DPM_TABLE_378__UvdLevel_5_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_378__UvdLevel_5_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_379__UvdLevel_5_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_379__UvdLevel_5_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_380__UvdLevel_5_VclkDivider_MASK 0xff
+#define DPM_TABLE_380__UvdLevel_5_VclkDivider__SHIFT 0x0
+#define DPM_TABLE_380__UvdLevel_5_MinVddcPhases_MASK 0xff00
+#define DPM_TABLE_380__UvdLevel_5_MinVddcPhases__SHIFT 0x8
+#define DPM_TABLE_380__UvdLevel_5_MinVddc_MASK 0xffff0000
+#define DPM_TABLE_380__UvdLevel_5_MinVddc__SHIFT 0x10
+#define DPM_TABLE_381__UvdLevel_5_padding_2_MASK 0xff
+#define DPM_TABLE_381__UvdLevel_5_padding_2__SHIFT 0x0
+#define DPM_TABLE_381__UvdLevel_5_padding_1_MASK 0xff00
+#define DPM_TABLE_381__UvdLevel_5_padding_1__SHIFT 0x8
+#define DPM_TABLE_381__UvdLevel_5_padding_0_MASK 0xff0000
+#define DPM_TABLE_381__UvdLevel_5_padding_0__SHIFT 0x10
+#define DPM_TABLE_381__UvdLevel_5_DclkDivider_MASK 0xff000000
+#define DPM_TABLE_381__UvdLevel_5_DclkDivider__SHIFT 0x18
+#define DPM_TABLE_382__UvdLevel_6_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_382__UvdLevel_6_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_383__UvdLevel_6_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_383__UvdLevel_6_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_384__UvdLevel_6_VclkDivider_MASK 0xff
+#define DPM_TABLE_384__UvdLevel_6_VclkDivider__SHIFT 0x0
+#define DPM_TABLE_384__UvdLevel_6_MinVddcPhases_MASK 0xff00
+#define DPM_TABLE_384__UvdLevel_6_MinVddcPhases__SHIFT 0x8
+#define DPM_TABLE_384__UvdLevel_6_MinVddc_MASK 0xffff0000
+#define DPM_TABLE_384__UvdLevel_6_MinVddc__SHIFT 0x10
+#define DPM_TABLE_385__UvdLevel_6_padding_2_MASK 0xff
+#define DPM_TABLE_385__UvdLevel_6_padding_2__SHIFT 0x0
+#define DPM_TABLE_385__UvdLevel_6_padding_1_MASK 0xff00
+#define DPM_TABLE_385__UvdLevel_6_padding_1__SHIFT 0x8
+#define DPM_TABLE_385__UvdLevel_6_padding_0_MASK 0xff0000
+#define DPM_TABLE_385__UvdLevel_6_padding_0__SHIFT 0x10
+#define DPM_TABLE_385__UvdLevel_6_DclkDivider_MASK 0xff000000
+#define DPM_TABLE_385__UvdLevel_6_DclkDivider__SHIFT 0x18
+#define DPM_TABLE_386__UvdLevel_7_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_386__UvdLevel_7_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_387__UvdLevel_7_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_387__UvdLevel_7_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_388__UvdLevel_7_VclkDivider_MASK 0xff
+#define DPM_TABLE_388__UvdLevel_7_VclkDivider__SHIFT 0x0
+#define DPM_TABLE_388__UvdLevel_7_MinVddcPhases_MASK 0xff00
+#define DPM_TABLE_388__UvdLevel_7_MinVddcPhases__SHIFT 0x8
+#define DPM_TABLE_388__UvdLevel_7_MinVddc_MASK 0xffff0000
+#define DPM_TABLE_388__UvdLevel_7_MinVddc__SHIFT 0x10
+#define DPM_TABLE_389__UvdLevel_7_padding_2_MASK 0xff
+#define DPM_TABLE_389__UvdLevel_7_padding_2__SHIFT 0x0
+#define DPM_TABLE_389__UvdLevel_7_padding_1_MASK 0xff00
+#define DPM_TABLE_389__UvdLevel_7_padding_1__SHIFT 0x8
+#define DPM_TABLE_389__UvdLevel_7_padding_0_MASK 0xff0000
+#define DPM_TABLE_389__UvdLevel_7_padding_0__SHIFT 0x10
+#define DPM_TABLE_389__UvdLevel_7_DclkDivider_MASK 0xff000000
+#define DPM_TABLE_389__UvdLevel_7_DclkDivider__SHIFT 0x18
+#define DPM_TABLE_390__VceLevel_0_Frequency_MASK 0xffffffff
+#define DPM_TABLE_390__VceLevel_0_Frequency__SHIFT 0x0
+#define DPM_TABLE_391__VceLevel_0_Divider_MASK 0xff
+#define DPM_TABLE_391__VceLevel_0_Divider__SHIFT 0x0
+#define DPM_TABLE_391__VceLevel_0_MinPhases_MASK 0xff00
+#define DPM_TABLE_391__VceLevel_0_MinPhases__SHIFT 0x8
+#define DPM_TABLE_391__VceLevel_0_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_391__VceLevel_0_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_392__VceLevel_1_Frequency_MASK 0xffffffff
+#define DPM_TABLE_392__VceLevel_1_Frequency__SHIFT 0x0
+#define DPM_TABLE_393__VceLevel_1_Divider_MASK 0xff
+#define DPM_TABLE_393__VceLevel_1_Divider__SHIFT 0x0
+#define DPM_TABLE_393__VceLevel_1_MinPhases_MASK 0xff00
+#define DPM_TABLE_393__VceLevel_1_MinPhases__SHIFT 0x8
+#define DPM_TABLE_393__VceLevel_1_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_393__VceLevel_1_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_394__VceLevel_2_Frequency_MASK 0xffffffff
+#define DPM_TABLE_394__VceLevel_2_Frequency__SHIFT 0x0
+#define DPM_TABLE_395__VceLevel_2_Divider_MASK 0xff
+#define DPM_TABLE_395__VceLevel_2_Divider__SHIFT 0x0
+#define DPM_TABLE_395__VceLevel_2_MinPhases_MASK 0xff00
+#define DPM_TABLE_395__VceLevel_2_MinPhases__SHIFT 0x8
+#define DPM_TABLE_395__VceLevel_2_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_395__VceLevel_2_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_396__VceLevel_3_Frequency_MASK 0xffffffff
+#define DPM_TABLE_396__VceLevel_3_Frequency__SHIFT 0x0
+#define DPM_TABLE_397__VceLevel_3_Divider_MASK 0xff
+#define DPM_TABLE_397__VceLevel_3_Divider__SHIFT 0x0
+#define DPM_TABLE_397__VceLevel_3_MinPhases_MASK 0xff00
+#define DPM_TABLE_397__VceLevel_3_MinPhases__SHIFT 0x8
+#define DPM_TABLE_397__VceLevel_3_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_397__VceLevel_3_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_398__VceLevel_4_Frequency_MASK 0xffffffff
+#define DPM_TABLE_398__VceLevel_4_Frequency__SHIFT 0x0
+#define DPM_TABLE_399__VceLevel_4_Divider_MASK 0xff
+#define DPM_TABLE_399__VceLevel_4_Divider__SHIFT 0x0
+#define DPM_TABLE_399__VceLevel_4_MinPhases_MASK 0xff00
+#define DPM_TABLE_399__VceLevel_4_MinPhases__SHIFT 0x8
+#define DPM_TABLE_399__VceLevel_4_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_399__VceLevel_4_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_400__VceLevel_5_Frequency_MASK 0xffffffff
+#define DPM_TABLE_400__VceLevel_5_Frequency__SHIFT 0x0
+#define DPM_TABLE_401__VceLevel_5_Divider_MASK 0xff
+#define DPM_TABLE_401__VceLevel_5_Divider__SHIFT 0x0
+#define DPM_TABLE_401__VceLevel_5_MinPhases_MASK 0xff00
+#define DPM_TABLE_401__VceLevel_5_MinPhases__SHIFT 0x8
+#define DPM_TABLE_401__VceLevel_5_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_401__VceLevel_5_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_402__VceLevel_6_Frequency_MASK 0xffffffff
+#define DPM_TABLE_402__VceLevel_6_Frequency__SHIFT 0x0
+#define DPM_TABLE_403__VceLevel_6_Divider_MASK 0xff
+#define DPM_TABLE_403__VceLevel_6_Divider__SHIFT 0x0
+#define DPM_TABLE_403__VceLevel_6_MinPhases_MASK 0xff00
+#define DPM_TABLE_403__VceLevel_6_MinPhases__SHIFT 0x8
+#define DPM_TABLE_403__VceLevel_6_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_403__VceLevel_6_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_404__VceLevel_7_Frequency_MASK 0xffffffff
+#define DPM_TABLE_404__VceLevel_7_Frequency__SHIFT 0x0
+#define DPM_TABLE_405__VceLevel_7_Divider_MASK 0xff
+#define DPM_TABLE_405__VceLevel_7_Divider__SHIFT 0x0
+#define DPM_TABLE_405__VceLevel_7_MinPhases_MASK 0xff00
+#define DPM_TABLE_405__VceLevel_7_MinPhases__SHIFT 0x8
+#define DPM_TABLE_405__VceLevel_7_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_405__VceLevel_7_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_406__AcpLevel_0_Frequency_MASK 0xffffffff
+#define DPM_TABLE_406__AcpLevel_0_Frequency__SHIFT 0x0
+#define DPM_TABLE_407__AcpLevel_0_Divider_MASK 0xff
+#define DPM_TABLE_407__AcpLevel_0_Divider__SHIFT 0x0
+#define DPM_TABLE_407__AcpLevel_0_MinPhases_MASK 0xff00
+#define DPM_TABLE_407__AcpLevel_0_MinPhases__SHIFT 0x8
+#define DPM_TABLE_407__AcpLevel_0_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_407__AcpLevel_0_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_408__AcpLevel_1_Frequency_MASK 0xffffffff
+#define DPM_TABLE_408__AcpLevel_1_Frequency__SHIFT 0x0
+#define DPM_TABLE_409__AcpLevel_1_Divider_MASK 0xff
+#define DPM_TABLE_409__AcpLevel_1_Divider__SHIFT 0x0
+#define DPM_TABLE_409__AcpLevel_1_MinPhases_MASK 0xff00
+#define DPM_TABLE_409__AcpLevel_1_MinPhases__SHIFT 0x8
+#define DPM_TABLE_409__AcpLevel_1_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_409__AcpLevel_1_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_410__AcpLevel_2_Frequency_MASK 0xffffffff
+#define DPM_TABLE_410__AcpLevel_2_Frequency__SHIFT 0x0
+#define DPM_TABLE_411__AcpLevel_2_Divider_MASK 0xff
+#define DPM_TABLE_411__AcpLevel_2_Divider__SHIFT 0x0
+#define DPM_TABLE_411__AcpLevel_2_MinPhases_MASK 0xff00
+#define DPM_TABLE_411__AcpLevel_2_MinPhases__SHIFT 0x8
+#define DPM_TABLE_411__AcpLevel_2_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_411__AcpLevel_2_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_412__AcpLevel_3_Frequency_MASK 0xffffffff
+#define DPM_TABLE_412__AcpLevel_3_Frequency__SHIFT 0x0
+#define DPM_TABLE_413__AcpLevel_3_Divider_MASK 0xff
+#define DPM_TABLE_413__AcpLevel_3_Divider__SHIFT 0x0
+#define DPM_TABLE_413__AcpLevel_3_MinPhases_MASK 0xff00
+#define DPM_TABLE_413__AcpLevel_3_MinPhases__SHIFT 0x8
+#define DPM_TABLE_413__AcpLevel_3_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_413__AcpLevel_3_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_414__AcpLevel_4_Frequency_MASK 0xffffffff
+#define DPM_TABLE_414__AcpLevel_4_Frequency__SHIFT 0x0
+#define DPM_TABLE_415__AcpLevel_4_Divider_MASK 0xff
+#define DPM_TABLE_415__AcpLevel_4_Divider__SHIFT 0x0
+#define DPM_TABLE_415__AcpLevel_4_MinPhases_MASK 0xff00
+#define DPM_TABLE_415__AcpLevel_4_MinPhases__SHIFT 0x8
+#define DPM_TABLE_415__AcpLevel_4_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_415__AcpLevel_4_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_416__AcpLevel_5_Frequency_MASK 0xffffffff
+#define DPM_TABLE_416__AcpLevel_5_Frequency__SHIFT 0x0
+#define DPM_TABLE_417__AcpLevel_5_Divider_MASK 0xff
+#define DPM_TABLE_417__AcpLevel_5_Divider__SHIFT 0x0
+#define DPM_TABLE_417__AcpLevel_5_MinPhases_MASK 0xff00
+#define DPM_TABLE_417__AcpLevel_5_MinPhases__SHIFT 0x8
+#define DPM_TABLE_417__AcpLevel_5_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_417__AcpLevel_5_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_418__AcpLevel_6_Frequency_MASK 0xffffffff
+#define DPM_TABLE_418__AcpLevel_6_Frequency__SHIFT 0x0
+#define DPM_TABLE_419__AcpLevel_6_Divider_MASK 0xff
+#define DPM_TABLE_419__AcpLevel_6_Divider__SHIFT 0x0
+#define DPM_TABLE_419__AcpLevel_6_MinPhases_MASK 0xff00
+#define DPM_TABLE_419__AcpLevel_6_MinPhases__SHIFT 0x8
+#define DPM_TABLE_419__AcpLevel_6_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_419__AcpLevel_6_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_420__AcpLevel_7_Frequency_MASK 0xffffffff
+#define DPM_TABLE_420__AcpLevel_7_Frequency__SHIFT 0x0
+#define DPM_TABLE_421__AcpLevel_7_Divider_MASK 0xff
+#define DPM_TABLE_421__AcpLevel_7_Divider__SHIFT 0x0
+#define DPM_TABLE_421__AcpLevel_7_MinPhases_MASK 0xff00
+#define DPM_TABLE_421__AcpLevel_7_MinPhases__SHIFT 0x8
+#define DPM_TABLE_421__AcpLevel_7_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_421__AcpLevel_7_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_422__SamuLevel_0_Frequency_MASK 0xffffffff
+#define DPM_TABLE_422__SamuLevel_0_Frequency__SHIFT 0x0
+#define DPM_TABLE_423__SamuLevel_0_Divider_MASK 0xff
+#define DPM_TABLE_423__SamuLevel_0_Divider__SHIFT 0x0
+#define DPM_TABLE_423__SamuLevel_0_MinPhases_MASK 0xff00
+#define DPM_TABLE_423__SamuLevel_0_MinPhases__SHIFT 0x8
+#define DPM_TABLE_423__SamuLevel_0_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_423__SamuLevel_0_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_424__SamuLevel_1_Frequency_MASK 0xffffffff
+#define DPM_TABLE_424__SamuLevel_1_Frequency__SHIFT 0x0
+#define DPM_TABLE_425__SamuLevel_1_Divider_MASK 0xff
+#define DPM_TABLE_425__SamuLevel_1_Divider__SHIFT 0x0
+#define DPM_TABLE_425__SamuLevel_1_MinPhases_MASK 0xff00
+#define DPM_TABLE_425__SamuLevel_1_MinPhases__SHIFT 0x8
+#define DPM_TABLE_425__SamuLevel_1_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_425__SamuLevel_1_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_426__SamuLevel_2_Frequency_MASK 0xffffffff
+#define DPM_TABLE_426__SamuLevel_2_Frequency__SHIFT 0x0
+#define DPM_TABLE_427__SamuLevel_2_Divider_MASK 0xff
+#define DPM_TABLE_427__SamuLevel_2_Divider__SHIFT 0x0
+#define DPM_TABLE_427__SamuLevel_2_MinPhases_MASK 0xff00
+#define DPM_TABLE_427__SamuLevel_2_MinPhases__SHIFT 0x8
+#define DPM_TABLE_427__SamuLevel_2_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_427__SamuLevel_2_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_428__SamuLevel_3_Frequency_MASK 0xffffffff
+#define DPM_TABLE_428__SamuLevel_3_Frequency__SHIFT 0x0
+#define DPM_TABLE_429__SamuLevel_3_Divider_MASK 0xff
+#define DPM_TABLE_429__SamuLevel_3_Divider__SHIFT 0x0
+#define DPM_TABLE_429__SamuLevel_3_MinPhases_MASK 0xff00
+#define DPM_TABLE_429__SamuLevel_3_MinPhases__SHIFT 0x8
+#define DPM_TABLE_429__SamuLevel_3_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_429__SamuLevel_3_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_430__SamuLevel_4_Frequency_MASK 0xffffffff
+#define DPM_TABLE_430__SamuLevel_4_Frequency__SHIFT 0x0
+#define DPM_TABLE_431__SamuLevel_4_Divider_MASK 0xff
+#define DPM_TABLE_431__SamuLevel_4_Divider__SHIFT 0x0
+#define DPM_TABLE_431__SamuLevel_4_MinPhases_MASK 0xff00
+#define DPM_TABLE_431__SamuLevel_4_MinPhases__SHIFT 0x8
+#define DPM_TABLE_431__SamuLevel_4_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_431__SamuLevel_4_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_432__SamuLevel_5_Frequency_MASK 0xffffffff
+#define DPM_TABLE_432__SamuLevel_5_Frequency__SHIFT 0x0
+#define DPM_TABLE_433__SamuLevel_5_Divider_MASK 0xff
+#define DPM_TABLE_433__SamuLevel_5_Divider__SHIFT 0x0
+#define DPM_TABLE_433__SamuLevel_5_MinPhases_MASK 0xff00
+#define DPM_TABLE_433__SamuLevel_5_MinPhases__SHIFT 0x8
+#define DPM_TABLE_433__SamuLevel_5_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_433__SamuLevel_5_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_434__SamuLevel_6_Frequency_MASK 0xffffffff
+#define DPM_TABLE_434__SamuLevel_6_Frequency__SHIFT 0x0
+#define DPM_TABLE_435__SamuLevel_6_Divider_MASK 0xff
+#define DPM_TABLE_435__SamuLevel_6_Divider__SHIFT 0x0
+#define DPM_TABLE_435__SamuLevel_6_MinPhases_MASK 0xff00
+#define DPM_TABLE_435__SamuLevel_6_MinPhases__SHIFT 0x8
+#define DPM_TABLE_435__SamuLevel_6_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_435__SamuLevel_6_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_436__SamuLevel_7_Frequency_MASK 0xffffffff
+#define DPM_TABLE_436__SamuLevel_7_Frequency__SHIFT 0x0
+#define DPM_TABLE_437__SamuLevel_7_Divider_MASK 0xff
+#define DPM_TABLE_437__SamuLevel_7_Divider__SHIFT 0x0
+#define DPM_TABLE_437__SamuLevel_7_MinPhases_MASK 0xff00
+#define DPM_TABLE_437__SamuLevel_7_MinPhases__SHIFT 0x8
+#define DPM_TABLE_437__SamuLevel_7_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_437__SamuLevel_7_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_438__Ulv_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_438__Ulv_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_439__Ulv_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_439__Ulv_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_440__Ulv_VddcPhase_MASK 0xff
+#define DPM_TABLE_440__Ulv_VddcPhase__SHIFT 0x0
+#define DPM_TABLE_440__Ulv_VddcOffsetVid_MASK 0xff00
+#define DPM_TABLE_440__Ulv_VddcOffsetVid__SHIFT 0x8
+#define DPM_TABLE_440__Ulv_VddcOffset_MASK 0xffff0000
+#define DPM_TABLE_440__Ulv_VddcOffset__SHIFT 0x10
+#define DPM_TABLE_441__Ulv_Reserved_MASK 0xffffffff
+#define DPM_TABLE_441__Ulv_Reserved__SHIFT 0x0
+#define DPM_TABLE_442__SclkStepSize_MASK 0xffffffff
+#define DPM_TABLE_442__SclkStepSize__SHIFT 0x0
+#define DPM_TABLE_443__Smio_0_MASK 0xffffffff
+#define DPM_TABLE_443__Smio_0__SHIFT 0x0
+#define DPM_TABLE_444__Smio_1_MASK 0xffffffff
+#define DPM_TABLE_444__Smio_1__SHIFT 0x0
+#define DPM_TABLE_445__Smio_2_MASK 0xffffffff
+#define DPM_TABLE_445__Smio_2__SHIFT 0x0
+#define DPM_TABLE_446__Smio_3_MASK 0xffffffff
+#define DPM_TABLE_446__Smio_3__SHIFT 0x0
+#define DPM_TABLE_447__Smio_4_MASK 0xffffffff
+#define DPM_TABLE_447__Smio_4__SHIFT 0x0
+#define DPM_TABLE_448__Smio_5_MASK 0xffffffff
+#define DPM_TABLE_448__Smio_5__SHIFT 0x0
+#define DPM_TABLE_449__Smio_6_MASK 0xffffffff
+#define DPM_TABLE_449__Smio_6__SHIFT 0x0
+#define DPM_TABLE_450__Smio_7_MASK 0xffffffff
+#define DPM_TABLE_450__Smio_7__SHIFT 0x0
+#define DPM_TABLE_451__Smio_8_MASK 0xffffffff
+#define DPM_TABLE_451__Smio_8__SHIFT 0x0
+#define DPM_TABLE_452__Smio_9_MASK 0xffffffff
+#define DPM_TABLE_452__Smio_9__SHIFT 0x0
+#define DPM_TABLE_453__Smio_10_MASK 0xffffffff
+#define DPM_TABLE_453__Smio_10__SHIFT 0x0
+#define DPM_TABLE_454__Smio_11_MASK 0xffffffff
+#define DPM_TABLE_454__Smio_11__SHIFT 0x0
+#define DPM_TABLE_455__Smio_12_MASK 0xffffffff
+#define DPM_TABLE_455__Smio_12__SHIFT 0x0
+#define DPM_TABLE_456__Smio_13_MASK 0xffffffff
+#define DPM_TABLE_456__Smio_13__SHIFT 0x0
+#define DPM_TABLE_457__Smio_14_MASK 0xffffffff
+#define DPM_TABLE_457__Smio_14__SHIFT 0x0
+#define DPM_TABLE_458__Smio_15_MASK 0xffffffff
+#define DPM_TABLE_458__Smio_15__SHIFT 0x0
+#define DPM_TABLE_459__Smio_16_MASK 0xffffffff
+#define DPM_TABLE_459__Smio_16__SHIFT 0x0
+#define DPM_TABLE_460__Smio_17_MASK 0xffffffff
+#define DPM_TABLE_460__Smio_17__SHIFT 0x0
+#define DPM_TABLE_461__Smio_18_MASK 0xffffffff
+#define DPM_TABLE_461__Smio_18__SHIFT 0x0
+#define DPM_TABLE_462__Smio_19_MASK 0xffffffff
+#define DPM_TABLE_462__Smio_19__SHIFT 0x0
+#define DPM_TABLE_463__Smio_20_MASK 0xffffffff
+#define DPM_TABLE_463__Smio_20__SHIFT 0x0
+#define DPM_TABLE_464__Smio_21_MASK 0xffffffff
+#define DPM_TABLE_464__Smio_21__SHIFT 0x0
+#define DPM_TABLE_465__Smio_22_MASK 0xffffffff
+#define DPM_TABLE_465__Smio_22__SHIFT 0x0
+#define DPM_TABLE_466__Smio_23_MASK 0xffffffff
+#define DPM_TABLE_466__Smio_23__SHIFT 0x0
+#define DPM_TABLE_467__Smio_24_MASK 0xffffffff
+#define DPM_TABLE_467__Smio_24__SHIFT 0x0
+#define DPM_TABLE_468__Smio_25_MASK 0xffffffff
+#define DPM_TABLE_468__Smio_25__SHIFT 0x0
+#define DPM_TABLE_469__Smio_26_MASK 0xffffffff
+#define DPM_TABLE_469__Smio_26__SHIFT 0x0
+#define DPM_TABLE_470__Smio_27_MASK 0xffffffff
+#define DPM_TABLE_470__Smio_27__SHIFT 0x0
+#define DPM_TABLE_471__Smio_28_MASK 0xffffffff
+#define DPM_TABLE_471__Smio_28__SHIFT 0x0
+#define DPM_TABLE_472__Smio_29_MASK 0xffffffff
+#define DPM_TABLE_472__Smio_29__SHIFT 0x0
+#define DPM_TABLE_473__Smio_30_MASK 0xffffffff
+#define DPM_TABLE_473__Smio_30__SHIFT 0x0
+#define DPM_TABLE_474__Smio_31_MASK 0xffffffff
+#define DPM_TABLE_474__Smio_31__SHIFT 0x0
+#define DPM_TABLE_475__SamuBootLevel_MASK 0xff
+#define DPM_TABLE_475__SamuBootLevel__SHIFT 0x0
+#define DPM_TABLE_475__AcpBootLevel_MASK 0xff00
+#define DPM_TABLE_475__AcpBootLevel__SHIFT 0x8
+#define DPM_TABLE_475__VceBootLevel_MASK 0xff0000
+#define DPM_TABLE_475__VceBootLevel__SHIFT 0x10
+#define DPM_TABLE_475__UvdBootLevel_MASK 0xff000000
+#define DPM_TABLE_475__UvdBootLevel__SHIFT 0x18
+#define DPM_TABLE_476__SAMUInterval_MASK 0xff
+#define DPM_TABLE_476__SAMUInterval__SHIFT 0x0
+#define DPM_TABLE_476__ACPInterval_MASK 0xff00
+#define DPM_TABLE_476__ACPInterval__SHIFT 0x8
+#define DPM_TABLE_476__VCEInterval_MASK 0xff0000
+#define DPM_TABLE_476__VCEInterval__SHIFT 0x10
+#define DPM_TABLE_476__UVDInterval_MASK 0xff000000
+#define DPM_TABLE_476__UVDInterval__SHIFT 0x18
+#define DPM_TABLE_477__GraphicsInterval_MASK 0xff
+#define DPM_TABLE_477__GraphicsInterval__SHIFT 0x0
+#define DPM_TABLE_477__GraphicsThermThrottleEnable_MASK 0xff00
+#define DPM_TABLE_477__GraphicsThermThrottleEnable__SHIFT 0x8
+#define DPM_TABLE_477__GraphicsVoltageChangeEnable_MASK 0xff0000
+#define DPM_TABLE_477__GraphicsVoltageChangeEnable__SHIFT 0x10
+#define DPM_TABLE_477__GraphicsBootLevel_MASK 0xff000000
+#define DPM_TABLE_477__GraphicsBootLevel__SHIFT 0x18
+#define DPM_TABLE_478__TemperatureLimitHigh_MASK 0xffff
+#define DPM_TABLE_478__TemperatureLimitHigh__SHIFT 0x0
+#define DPM_TABLE_478__ThermalInterval_MASK 0xff0000
+#define DPM_TABLE_478__ThermalInterval__SHIFT 0x10
+#define DPM_TABLE_478__VoltageInterval_MASK 0xff000000
+#define DPM_TABLE_478__VoltageInterval__SHIFT 0x18
+#define DPM_TABLE_479__MemoryVoltageChangeEnable_MASK 0xff
+#define DPM_TABLE_479__MemoryVoltageChangeEnable__SHIFT 0x0
+#define DPM_TABLE_479__MemoryBootLevel_MASK 0xff00
+#define DPM_TABLE_479__MemoryBootLevel__SHIFT 0x8
+#define DPM_TABLE_479__TemperatureLimitLow_MASK 0xffff0000
+#define DPM_TABLE_479__TemperatureLimitLow__SHIFT 0x10
+#define DPM_TABLE_480__VddcVddciDelta_MASK 0xffff
+#define DPM_TABLE_480__VddcVddciDelta__SHIFT 0x0
+#define DPM_TABLE_480__MemoryThermThrottleEnable_MASK 0xff0000
+#define DPM_TABLE_480__MemoryThermThrottleEnable__SHIFT 0x10
+#define DPM_TABLE_480__MemoryInterval_MASK 0xff000000
+#define DPM_TABLE_480__MemoryInterval__SHIFT 0x18
+#define DPM_TABLE_481__PhaseResponseTime_MASK 0xffff
+#define DPM_TABLE_481__PhaseResponseTime__SHIFT 0x0
+#define DPM_TABLE_481__VoltageResponseTime_MASK 0xffff0000
+#define DPM_TABLE_481__VoltageResponseTime__SHIFT 0x10
+#define DPM_TABLE_482__DTEMode_MASK 0xff
+#define DPM_TABLE_482__DTEMode__SHIFT 0x0
+#define DPM_TABLE_482__DTEInterval_MASK 0xff00
+#define DPM_TABLE_482__DTEInterval__SHIFT 0x8
+#define DPM_TABLE_482__PCIeGenInterval_MASK 0xff0000
+#define DPM_TABLE_482__PCIeGenInterval__SHIFT 0x10
+#define DPM_TABLE_482__PCIeBootLinkLevel_MASK 0xff000000
+#define DPM_TABLE_482__PCIeBootLinkLevel__SHIFT 0x18
+#define DPM_TABLE_483__ThermGpio_MASK 0xff
+#define DPM_TABLE_483__ThermGpio__SHIFT 0x0
+#define DPM_TABLE_483__AcDcGpio_MASK 0xff00
+#define DPM_TABLE_483__AcDcGpio__SHIFT 0x8
+#define DPM_TABLE_483__VRHotGpio_MASK 0xff0000
+#define DPM_TABLE_483__VRHotGpio__SHIFT 0x10
+#define DPM_TABLE_483__SVI2Enable_MASK 0xff000000
+#define DPM_TABLE_483__SVI2Enable__SHIFT 0x18
+#define DPM_TABLE_484__DisplayCac_MASK 0xffffffff
+#define DPM_TABLE_484__DisplayCac__SHIFT 0x0
+#define DPM_TABLE_485__NomPwr_MASK 0xffff
+#define DPM_TABLE_485__NomPwr__SHIFT 0x0
+#define DPM_TABLE_485__MaxPwr_MASK 0xffff0000
+#define DPM_TABLE_485__MaxPwr__SHIFT 0x10
+#define DPM_TABLE_486__FpsLowThreshold_MASK 0xffff
+#define DPM_TABLE_486__FpsLowThreshold__SHIFT 0x0
+#define DPM_TABLE_486__FpsHighThreshold_MASK 0xffff0000
+#define DPM_TABLE_486__FpsHighThreshold__SHIFT 0x10
+#define DPM_TABLE_487__BAPMTI_R_0_1_0_MASK 0xffff
+#define DPM_TABLE_487__BAPMTI_R_0_1_0__SHIFT 0x0
+#define DPM_TABLE_487__BAPMTI_R_0_0_0_MASK 0xffff0000
+#define DPM_TABLE_487__BAPMTI_R_0_0_0__SHIFT 0x10
+#define DPM_TABLE_488__BAPMTI_R_1_0_0_MASK 0xffff
+#define DPM_TABLE_488__BAPMTI_R_1_0_0__SHIFT 0x0
+#define DPM_TABLE_488__BAPMTI_R_0_2_0_MASK 0xffff0000
+#define DPM_TABLE_488__BAPMTI_R_0_2_0__SHIFT 0x10
+#define DPM_TABLE_489__BAPMTI_R_1_2_0_MASK 0xffff
+#define DPM_TABLE_489__BAPMTI_R_1_2_0__SHIFT 0x0
+#define DPM_TABLE_489__BAPMTI_R_1_1_0_MASK 0xffff0000
+#define DPM_TABLE_489__BAPMTI_R_1_1_0__SHIFT 0x10
+#define DPM_TABLE_490__BAPMTI_R_2_1_0_MASK 0xffff
+#define DPM_TABLE_490__BAPMTI_R_2_1_0__SHIFT 0x0
+#define DPM_TABLE_490__BAPMTI_R_2_0_0_MASK 0xffff0000
+#define DPM_TABLE_490__BAPMTI_R_2_0_0__SHIFT 0x10
+#define DPM_TABLE_491__BAPMTI_R_3_0_0_MASK 0xffff
+#define DPM_TABLE_491__BAPMTI_R_3_0_0__SHIFT 0x0
+#define DPM_TABLE_491__BAPMTI_R_2_2_0_MASK 0xffff0000
+#define DPM_TABLE_491__BAPMTI_R_2_2_0__SHIFT 0x10
+#define DPM_TABLE_492__BAPMTI_R_3_2_0_MASK 0xffff
+#define DPM_TABLE_492__BAPMTI_R_3_2_0__SHIFT 0x0
+#define DPM_TABLE_492__BAPMTI_R_3_1_0_MASK 0xffff0000
+#define DPM_TABLE_492__BAPMTI_R_3_1_0__SHIFT 0x10
+#define DPM_TABLE_493__BAPMTI_R_4_1_0_MASK 0xffff
+#define DPM_TABLE_493__BAPMTI_R_4_1_0__SHIFT 0x0
+#define DPM_TABLE_493__BAPMTI_R_4_0_0_MASK 0xffff0000
+#define DPM_TABLE_493__BAPMTI_R_4_0_0__SHIFT 0x10
+#define DPM_TABLE_494__BAPMTI_RC_0_0_0_MASK 0xffff
+#define DPM_TABLE_494__BAPMTI_RC_0_0_0__SHIFT 0x0
+#define DPM_TABLE_494__BAPMTI_R_4_2_0_MASK 0xffff0000
+#define DPM_TABLE_494__BAPMTI_R_4_2_0__SHIFT 0x10
+#define DPM_TABLE_495__BAPMTI_RC_0_2_0_MASK 0xffff
+#define DPM_TABLE_495__BAPMTI_RC_0_2_0__SHIFT 0x0
+#define DPM_TABLE_495__BAPMTI_RC_0_1_0_MASK 0xffff0000
+#define DPM_TABLE_495__BAPMTI_RC_0_1_0__SHIFT 0x10
+#define DPM_TABLE_496__BAPMTI_RC_1_1_0_MASK 0xffff
+#define DPM_TABLE_496__BAPMTI_RC_1_1_0__SHIFT 0x0
+#define DPM_TABLE_496__BAPMTI_RC_1_0_0_MASK 0xffff0000
+#define DPM_TABLE_496__BAPMTI_RC_1_0_0__SHIFT 0x10
+#define DPM_TABLE_497__BAPMTI_RC_2_0_0_MASK 0xffff
+#define DPM_TABLE_497__BAPMTI_RC_2_0_0__SHIFT 0x0
+#define DPM_TABLE_497__BAPMTI_RC_1_2_0_MASK 0xffff0000
+#define DPM_TABLE_497__BAPMTI_RC_1_2_0__SHIFT 0x10
+#define DPM_TABLE_498__BAPMTI_RC_2_2_0_MASK 0xffff
+#define DPM_TABLE_498__BAPMTI_RC_2_2_0__SHIFT 0x0
+#define DPM_TABLE_498__BAPMTI_RC_2_1_0_MASK 0xffff0000
+#define DPM_TABLE_498__BAPMTI_RC_2_1_0__SHIFT 0x10
+#define DPM_TABLE_499__BAPMTI_RC_3_1_0_MASK 0xffff
+#define DPM_TABLE_499__BAPMTI_RC_3_1_0__SHIFT 0x0
+#define DPM_TABLE_499__BAPMTI_RC_3_0_0_MASK 0xffff0000
+#define DPM_TABLE_499__BAPMTI_RC_3_0_0__SHIFT 0x10
+#define DPM_TABLE_500__BAPMTI_RC_4_0_0_MASK 0xffff
+#define DPM_TABLE_500__BAPMTI_RC_4_0_0__SHIFT 0x0
+#define DPM_TABLE_500__BAPMTI_RC_3_2_0_MASK 0xffff0000
+#define DPM_TABLE_500__BAPMTI_RC_3_2_0__SHIFT 0x10
+#define DPM_TABLE_501__BAPMTI_RC_4_2_0_MASK 0xffff
+#define DPM_TABLE_501__BAPMTI_RC_4_2_0__SHIFT 0x0
+#define DPM_TABLE_501__BAPMTI_RC_4_1_0_MASK 0xffff0000
+#define DPM_TABLE_501__BAPMTI_RC_4_1_0__SHIFT 0x10
+#define DPM_TABLE_502__GpuTjHyst_MASK 0xff
+#define DPM_TABLE_502__GpuTjHyst__SHIFT 0x0
+#define DPM_TABLE_502__GpuTjMax_MASK 0xff00
+#define DPM_TABLE_502__GpuTjMax__SHIFT 0x8
+#define DPM_TABLE_502__DTETjOffset_MASK 0xff0000
+#define DPM_TABLE_502__DTETjOffset__SHIFT 0x10
+#define DPM_TABLE_502__DTEAmbientTempBase_MASK 0xff000000
+#define DPM_TABLE_502__DTEAmbientTempBase__SHIFT 0x18
+#define DPM_TABLE_503__BootVddci_MASK 0xffff
+#define DPM_TABLE_503__BootVddci__SHIFT 0x0
+#define DPM_TABLE_503__BootVddc_MASK 0xffff0000
+#define DPM_TABLE_503__BootVddc__SHIFT 0x10
+#define DPM_TABLE_504__padding_MASK 0xffff
+#define DPM_TABLE_504__padding__SHIFT 0x0
+#define DPM_TABLE_504__BootMVdd_MASK 0xffff0000
+#define DPM_TABLE_504__BootMVdd__SHIFT 0x10
+#define DPM_TABLE_505__DRAM_LOG_ADDR_H_MASK 0xffffffff
+#define DPM_TABLE_505__DRAM_LOG_ADDR_H__SHIFT 0x0
+#define DPM_TABLE_506__DRAM_LOG_ADDR_L_MASK 0xffffffff
+#define DPM_TABLE_506__DRAM_LOG_ADDR_L__SHIFT 0x0
+#define DPM_TABLE_507__DRAM_LOG_PHY_ADDR_H_MASK 0xffffffff
+#define DPM_TABLE_507__DRAM_LOG_PHY_ADDR_H__SHIFT 0x0
+#define DPM_TABLE_508__DRAM_LOG_PHY_ADDR_L_MASK 0xffffffff
+#define DPM_TABLE_508__DRAM_LOG_PHY_ADDR_L__SHIFT 0x0
+#define DPM_TABLE_509__DRAM_LOG_BUFF_SIZE_MASK 0xffffffff
+#define DPM_TABLE_509__DRAM_LOG_BUFF_SIZE__SHIFT 0x0
+#define DPM_TABLE_510__BAPM_TEMP_GRADIENT_MASK 0xffffffff
+#define DPM_TABLE_510__BAPM_TEMP_GRADIENT__SHIFT 0x0
+#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1
+#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
+#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe
+#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
+#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000
+#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18
+#define TDC_STATUS__VDD_Boost_MASK 0xff
+#define TDC_STATUS__VDD_Boost__SHIFT 0x0
+#define TDC_STATUS__VDD_Throttle_MASK 0xff00
+#define TDC_STATUS__VDD_Throttle__SHIFT 0x8
+#define TDC_STATUS__VDDC_Boost_MASK 0xff0000
+#define TDC_STATUS__VDDC_Boost__SHIFT 0x10
+#define TDC_STATUS__VDDC_Throttle_MASK 0xff000000
+#define TDC_STATUS__VDDC_Throttle__SHIFT 0x18
+#define TDC_MV_AVERAGE__IDD_MASK 0xffff
+#define TDC_MV_AVERAGE__IDD__SHIFT 0x0
+#define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000
+#define TDC_MV_AVERAGE__IDDC__SHIFT 0x10
+#define TDC_VRM_LIMIT__IDD_MASK 0xffff
+#define TDC_VRM_LIMIT__IDD__SHIFT 0x0
+#define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000
+#define TDC_VRM_LIMIT__IDDC__SHIFT 0x10
+#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1
+#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0
+#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2
+#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1
+#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4
+#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2
+#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8
+#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3
+#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10
+#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4
+#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x20
+#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x5
+#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x40
+#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x6
+#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80
+#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7
+#define FEATURE_STATUS__BAPM_ON_MASK 0x100
+#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8
+#define FEATURE_STATUS__LPMX_ON_MASK 0x200
+#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9
+#define FEATURE_STATUS__NBDPM_ON_MASK 0x400
+#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa
+#define FEATURE_STATUS__LHTC_ON_MASK 0x800
+#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb
+#define FEATURE_STATUS__VPC_ON_MASK 0x1000
+#define FEATURE_STATUS__VPC_ON__SHIFT 0xc
+#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000
+#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd
+#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000
+#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe
+#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000
+#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf
+#define FEATURE_STATUS__AVS_ON_MASK 0x10000
+#define FEATURE_STATUS__AVS_ON__SHIFT 0x10
+#define FEATURE_STATUS__SPMI_ON_MASK 0x20000
+#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11
+#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000
+#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12
+#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000
+#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13
+#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000
+#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14
+#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000
+#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15
+#define FEATURE_STATUS__RESERVED_MASK 0xffc00000
+#define FEATURE_STATUS__RESERVED__SHIFT 0x16
+#define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff
+#define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_13__entries_0_4_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_13__entries_0_4_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_14__entries_0_4_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_14__entries_0_4_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_16__entries_0_5_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_16__entries_0_5_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_17__entries_0_5_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_17__entries_0_5_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_19__entries_1_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_19__entries_1_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_20__entries_1_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_20__entries_1_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_22__entries_1_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_22__entries_1_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_23__entries_1_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_23__entries_1_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_25__entries_1_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_25__entries_1_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_26__entries_1_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_26__entries_1_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_28__entries_1_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_28__entries_1_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_29__entries_1_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_29__entries_1_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_31__entries_1_4_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_31__entries_1_4_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_32__entries_1_4_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_32__entries_1_4_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_34__entries_1_5_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_34__entries_1_5_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_35__entries_1_5_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_35__entries_1_5_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_37__entries_2_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_37__entries_2_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_38__entries_2_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_38__entries_2_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_40__entries_2_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_40__entries_2_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_41__entries_2_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_41__entries_2_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_43__entries_2_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_43__entries_2_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_44__entries_2_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_44__entries_2_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_46__entries_2_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_46__entries_2_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_47__entries_2_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_47__entries_2_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_49__entries_2_4_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_49__entries_2_4_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_50__entries_2_4_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_50__entries_2_4_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_52__entries_2_5_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_52__entries_2_5_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_53__entries_2_5_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_53__entries_2_5_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_55__entries_3_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_55__entries_3_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_56__entries_3_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_56__entries_3_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_58__entries_3_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_58__entries_3_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_59__entries_3_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_59__entries_3_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_61__entries_3_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_61__entries_3_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_62__entries_3_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_62__entries_3_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_64__entries_3_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_64__entries_3_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_65__entries_3_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_65__entries_3_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_67__entries_3_4_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_67__entries_3_4_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_68__entries_3_4_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_68__entries_3_4_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_70__entries_3_5_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_70__entries_3_5_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_71__entries_3_5_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_71__entries_3_5_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_73__entries_4_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_73__entries_4_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_74__entries_4_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_74__entries_4_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_76__entries_4_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_76__entries_4_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_77__entries_4_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_77__entries_4_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_79__entries_4_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_79__entries_4_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_80__entries_4_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_80__entries_4_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_82__entries_4_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_82__entries_4_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_83__entries_4_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_83__entries_4_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_85__entries_4_4_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_85__entries_4_4_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_86__entries_4_4_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_86__entries_4_4_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_88__entries_4_5_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_88__entries_4_5_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_89__entries_4_5_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_89__entries_4_5_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_91__entries_5_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_91__entries_5_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_92__entries_5_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_92__entries_5_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_94__entries_5_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_94__entries_5_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_95__entries_5_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_95__entries_5_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_97__entries_5_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_97__entries_5_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_98__entries_5_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_98__entries_5_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_100__entries_5_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_100__entries_5_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_101__entries_5_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_101__entries_5_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_103__entries_5_4_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_103__entries_5_4_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_104__entries_5_4_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_104__entries_5_4_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_106__entries_5_5_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_106__entries_5_5_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_107__entries_5_5_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_107__entries_5_5_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_109__entries_6_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_109__entries_6_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_110__entries_6_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_110__entries_6_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_112__entries_6_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_112__entries_6_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_113__entries_6_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_113__entries_6_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_115__entries_6_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_115__entries_6_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_116__entries_6_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_116__entries_6_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_118__entries_6_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_118__entries_6_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_119__entries_6_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_119__entries_6_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_121__entries_6_4_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_121__entries_6_4_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_122__entries_6_4_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_122__entries_6_4_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_124__entries_6_5_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_124__entries_6_5_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_125__entries_6_5_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_125__entries_6_5_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_127__entries_7_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_127__entries_7_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_128__entries_7_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_128__entries_7_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_130__entries_7_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_130__entries_7_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_131__entries_7_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_131__entries_7_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_133__entries_7_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_133__entries_7_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_134__entries_7_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_134__entries_7_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_136__entries_7_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_136__entries_7_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_137__entries_7_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_137__entries_7_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_139__entries_7_4_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_139__entries_7_4_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_140__entries_7_4_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_140__entries_7_4_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_142__entries_7_5_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_142__entries_7_5_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_143__entries_7_5_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_143__entries_7_5_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_McArbBurstTime__SHIFT 0x18
+#define MC_REGISTERS_TABLE_1__reserved_2_MASK 0xff
+#define MC_REGISTERS_TABLE_1__reserved_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_1__reserved_1_MASK 0xff00
+#define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8
+#define MC_REGISTERS_TABLE_1__reserved_0_MASK 0xff0000
+#define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_1__last_MASK 0xff000000
+#define MC_REGISTERS_TABLE_1__last__SHIFT 0x18
+#define MC_REGISTERS_TABLE_2__address_0_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_2__address_0_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_2__address_0_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_3__address_1_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_3__address_1_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_3__address_1_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_4__address_2_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_4__address_2_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_4__address_2_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_4__address_2_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_5__address_3_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_5__address_3_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_5__address_3_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_6__address_4_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_6__address_4_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_6__address_4_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_7__address_5_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_7__address_5_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_7__address_5_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_8__address_6_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_8__address_6_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_8__address_6_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_8__address_6_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_9__address_7_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_9__address_7_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_9__address_7_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_10__address_8_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_10__address_8_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_10__address_8_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_11__address_9_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_11__address_9_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_11__address_9_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_12__address_10_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_12__address_10_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_12__address_10_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_12__address_10_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_13__address_11_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_13__address_11_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_13__address_11_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_13__address_11_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_14__address_12_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_14__address_12_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_14__address_12_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_15__address_13_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_15__address_13_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_15__address_13_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_15__address_13_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_16__address_14_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_16__address_14_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_16__address_14_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_17__address_15_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_17__address_15_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_17__address_15_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_18__data_0_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_18__data_0_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_19__data_0_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_20__data_0_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_20__data_0_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_21__data_0_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_22__data_0_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_22__data_0_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_23__data_0_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_23__data_0_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_24__data_0_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_24__data_0_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_25__data_0_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_25__data_0_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_26__data_0_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_26__data_0_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_27__data_0_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_27__data_0_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_28__data_0_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_29__data_0_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_29__data_0_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_30__data_0_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_30__data_0_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_31__data_0_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_31__data_0_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_32__data_0_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_33__data_0_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0
+#define MC_REGISTERS_TABLE_34__data_1_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_34__data_1_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_35__data_1_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_35__data_1_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_36__data_1_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_36__data_1_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_37__data_1_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_37__data_1_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_38__data_1_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_38__data_1_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_39__data_1_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_39__data_1_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_40__data_1_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_41__data_1_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_41__data_1_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_42__data_1_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_42__data_1_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_43__data_1_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_44__data_1_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_44__data_1_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_45__data_1_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_45__data_1_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_46__data_1_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_47__data_1_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_47__data_1_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_48__data_1_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_48__data_1_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_49__data_1_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_49__data_1_value_15__SHIFT 0x0
+#define MC_REGISTERS_TABLE_50__data_2_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_50__data_2_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_51__data_2_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_51__data_2_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_52__data_2_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_52__data_2_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_53__data_2_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_53__data_2_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_54__data_2_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_54__data_2_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_55__data_2_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_55__data_2_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_56__data_2_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_56__data_2_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_57__data_2_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_57__data_2_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_58__data_2_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_58__data_2_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_59__data_2_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_59__data_2_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_60__data_2_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_61__data_2_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_62__data_2_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_63__data_2_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_63__data_2_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_64__data_2_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_64__data_2_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_65__data_2_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_65__data_2_value_15__SHIFT 0x0
+#define MC_REGISTERS_TABLE_66__data_3_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_67__data_3_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_67__data_3_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_68__data_3_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_68__data_3_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_69__data_3_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_69__data_3_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_70__data_3_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_70__data_3_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_71__data_3_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_72__data_3_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_73__data_3_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_73__data_3_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_74__data_3_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_74__data_3_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_75__data_3_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_75__data_3_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_76__data_3_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_77__data_3_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_77__data_3_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_78__data_3_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_78__data_3_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_79__data_3_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_79__data_3_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_80__data_3_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_80__data_3_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_81__data_3_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_81__data_3_value_15__SHIFT 0x0
+#define MC_REGISTERS_TABLE_82__data_4_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_82__data_4_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_83__data_4_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_83__data_4_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_84__data_4_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_84__data_4_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_85__data_4_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_85__data_4_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_86__data_4_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_86__data_4_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_87__data_4_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_87__data_4_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_88__data_4_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_88__data_4_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_89__data_4_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_89__data_4_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_90__data_4_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_90__data_4_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_91__data_4_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_91__data_4_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_92__data_4_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_92__data_4_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_93__data_4_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_93__data_4_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_94__data_4_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_94__data_4_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_95__data_4_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_95__data_4_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_96__data_4_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_96__data_4_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_97__data_4_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_97__data_4_value_15__SHIFT 0x0
+#define MC_REGISTERS_TABLE_98__data_5_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_98__data_5_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_99__data_5_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_99__data_5_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_100__data_5_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_100__data_5_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_101__data_5_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_101__data_5_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_102__data_5_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_102__data_5_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_103__data_5_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_103__data_5_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_104__data_5_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_104__data_5_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_105__data_5_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_105__data_5_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_106__data_5_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_106__data_5_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_107__data_5_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_107__data_5_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_108__data_5_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_108__data_5_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_109__data_5_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_109__data_5_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_110__data_5_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_110__data_5_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_111__data_5_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_111__data_5_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_112__data_5_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_112__data_5_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_113__data_5_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_113__data_5_value_15__SHIFT 0x0
+#define FAN_TABLE_1__TempMin_MASK 0xffff
+#define FAN_TABLE_1__TempMin__SHIFT 0x0
+#define FAN_TABLE_1__FdoMode_MASK 0xffff0000
+#define FAN_TABLE_1__FdoMode__SHIFT 0x10
+#define FAN_TABLE_2__TempMax_MASK 0xffff
+#define FAN_TABLE_2__TempMax__SHIFT 0x0
+#define FAN_TABLE_2__TempMed_MASK 0xffff0000
+#define FAN_TABLE_2__TempMed__SHIFT 0x10
+#define FAN_TABLE_3__Slope2_MASK 0xffff
+#define FAN_TABLE_3__Slope2__SHIFT 0x0
+#define FAN_TABLE_3__Slope1_MASK 0xffff0000
+#define FAN_TABLE_3__Slope1__SHIFT 0x10
+#define FAN_TABLE_4__HystUp_MASK 0xffff
+#define FAN_TABLE_4__HystUp__SHIFT 0x0
+#define FAN_TABLE_4__FdoMin_MASK 0xffff0000
+#define FAN_TABLE_4__FdoMin__SHIFT 0x10
+#define FAN_TABLE_5__HystSlope_MASK 0xffff
+#define FAN_TABLE_5__HystSlope__SHIFT 0x0
+#define FAN_TABLE_5__HystDown_MASK 0xffff0000
+#define FAN_TABLE_5__HystDown__SHIFT 0x10
+#define FAN_TABLE_6__TempCurr_MASK 0xffff
+#define FAN_TABLE_6__TempCurr__SHIFT 0x0
+#define FAN_TABLE_6__TempRespLim_MASK 0xffff0000
+#define FAN_TABLE_6__TempRespLim__SHIFT 0x10
+#define FAN_TABLE_7__PwmCurr_MASK 0xffff
+#define FAN_TABLE_7__PwmCurr__SHIFT 0x0
+#define FAN_TABLE_7__SlopeCurr_MASK 0xffff0000
+#define FAN_TABLE_7__SlopeCurr__SHIFT 0x10
+#define FAN_TABLE_8__RefreshPeriod_MASK 0xffffffff
+#define FAN_TABLE_8__RefreshPeriod__SHIFT 0x0
+#define FAN_TABLE_9__Padding_MASK 0xff
+#define FAN_TABLE_9__Padding__SHIFT 0x0
+#define FAN_TABLE_9__TempSrc_MASK 0xff00
+#define FAN_TABLE_9__TempSrc__SHIFT 0x8
+#define FAN_TABLE_9__FdoMax_MASK 0xffff0000
+#define FAN_TABLE_9__FdoMax__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_4__PreVBlankGap_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_4__PreVBlankGap__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_5__VBlankTimeout_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_5__VBlankTimeout__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_6__TrainTimeGap_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_6__TrainTimeGap__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_9__AcpiDelay_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_9__AcpiDelay__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_10__G5TrainTime_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_10__G5TrainTime__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_13__HandshakeDisables_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_13__HandshakeDisables__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config_MASK 0xff00
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config__SHIFT 0x8
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config_MASK 0xff0000
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config_MASK 0xff000000
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config__SHIFT 0x18
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config_MASK 0xff
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config__SHIFT 0x8
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config_MASK 0xff000000
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config__SHIFT 0x18
+#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_18__AverageGioActivity_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_18__AverageGioActivity__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels_MASK 0xff
+#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels_MASK 0xff00
+#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels__SHIFT 0x8
+#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels_MASK 0xff0000
+#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels_MASK 0xff000000
+#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels__SHIFT 0x18
+#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels_MASK 0xff
+#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels_MASK 0xff00
+#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels__SHIFT 0x8
+#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels_MASK 0xff0000
+#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels_MASK 0xff000000
+#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels__SHIFT 0x18
+#define SOFT_REGISTERS_TABLE_21__Reserved_0_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_21__Reserved_0__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_22__Reserved_1_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_22__Reserved_1__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_23__Reserved_2_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_23__Reserved_2__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_24__Reserved_3_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_24__Reserved_3__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_25__Reserved_4_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_25__Reserved_4__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_26__Reserved_5_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_26__Reserved_5__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_27__Reserved_6_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_27__Reserved_6__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_28__Reserved_7_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_28__Reserved_7__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_29__Reserved_8_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_29__Reserved_8__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_30__Reserved_9_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_30__Reserved_9__SHIFT 0x0
+#define PM_FUSES_1__BapmVddCVidHiSidd_3_MASK 0xff
+#define PM_FUSES_1__BapmVddCVidHiSidd_3__SHIFT 0x0
+#define PM_FUSES_1__BapmVddCVidHiSidd_2_MASK 0xff00
+#define PM_FUSES_1__BapmVddCVidHiSidd_2__SHIFT 0x8
+#define PM_FUSES_1__BapmVddCVidHiSidd_1_MASK 0xff0000
+#define PM_FUSES_1__BapmVddCVidHiSidd_1__SHIFT 0x10
+#define PM_FUSES_1__BapmVddCVidHiSidd_0_MASK 0xff000000
+#define PM_FUSES_1__BapmVddCVidHiSidd_0__SHIFT 0x18
+#define PM_FUSES_2__BapmVddCVidHiSidd_7_MASK 0xff
+#define PM_FUSES_2__BapmVddCVidHiSidd_7__SHIFT 0x0
+#define PM_FUSES_2__BapmVddCVidHiSidd_6_MASK 0xff00
+#define PM_FUSES_2__BapmVddCVidHiSidd_6__SHIFT 0x8
+#define PM_FUSES_2__BapmVddCVidHiSidd_5_MASK 0xff0000
+#define PM_FUSES_2__BapmVddCVidHiSidd_5__SHIFT 0x10
+#define PM_FUSES_2__BapmVddCVidHiSidd_4_MASK 0xff000000
+#define PM_FUSES_2__BapmVddCVidHiSidd_4__SHIFT 0x18
+#define PM_FUSES_3__BapmVddCVidLoSidd_3_MASK 0xff
+#define PM_FUSES_3__BapmVddCVidLoSidd_3__SHIFT 0x0
+#define PM_FUSES_3__BapmVddCVidLoSidd_2_MASK 0xff00
+#define PM_FUSES_3__BapmVddCVidLoSidd_2__SHIFT 0x8
+#define PM_FUSES_3__BapmVddCVidLoSidd_1_MASK 0xff0000
+#define PM_FUSES_3__BapmVddCVidLoSidd_1__SHIFT 0x10
+#define PM_FUSES_3__BapmVddCVidLoSidd_0_MASK 0xff000000
+#define PM_FUSES_3__BapmVddCVidLoSidd_0__SHIFT 0x18
+#define PM_FUSES_4__BapmVddCVidLoSidd_7_MASK 0xff
+#define PM_FUSES_4__BapmVddCVidLoSidd_7__SHIFT 0x0
+#define PM_FUSES_4__BapmVddCVidLoSidd_6_MASK 0xff00
+#define PM_FUSES_4__BapmVddCVidLoSidd_6__SHIFT 0x8
+#define PM_FUSES_4__BapmVddCVidLoSidd_5_MASK 0xff0000
+#define PM_FUSES_4__BapmVddCVidLoSidd_5__SHIFT 0x10
+#define PM_FUSES_4__BapmVddCVidLoSidd_4_MASK 0xff000000
+#define PM_FUSES_4__BapmVddCVidLoSidd_4__SHIFT 0x18
+#define PM_FUSES_5__VddCVid_3_MASK 0xff
+#define PM_FUSES_5__VddCVid_3__SHIFT 0x0
+#define PM_FUSES_5__VddCVid_2_MASK 0xff00
+#define PM_FUSES_5__VddCVid_2__SHIFT 0x8
+#define PM_FUSES_5__VddCVid_1_MASK 0xff0000
+#define PM_FUSES_5__VddCVid_1__SHIFT 0x10
+#define PM_FUSES_5__VddCVid_0_MASK 0xff000000
+#define PM_FUSES_5__VddCVid_0__SHIFT 0x18
+#define PM_FUSES_6__VddCVid_7_MASK 0xff
+#define PM_FUSES_6__VddCVid_7__SHIFT 0x0
+#define PM_FUSES_6__VddCVid_6_MASK 0xff00
+#define PM_FUSES_6__VddCVid_6__SHIFT 0x8
+#define PM_FUSES_6__VddCVid_5_MASK 0xff0000
+#define PM_FUSES_6__VddCVid_5__SHIFT 0x10
+#define PM_FUSES_6__VddCVid_4_MASK 0xff000000
+#define PM_FUSES_6__VddCVid_4__SHIFT 0x18
+#define PM_FUSES_7__SviLoadLineOffsetVddC_MASK 0xff
+#define PM_FUSES_7__SviLoadLineOffsetVddC__SHIFT 0x0
+#define PM_FUSES_7__SviLoadLineTrimVddC_MASK 0xff00
+#define PM_FUSES_7__SviLoadLineTrimVddC__SHIFT 0x8
+#define PM_FUSES_7__SviLoadLineVddC_MASK 0xff0000
+#define PM_FUSES_7__SviLoadLineVddC__SHIFT 0x10
+#define PM_FUSES_7__SviLoadLineEn_MASK 0xff000000
+#define PM_FUSES_7__SviLoadLineEn__SHIFT 0x18
+#define PM_FUSES_8__TDC_MAWt_MASK 0xff
+#define PM_FUSES_8__TDC_MAWt__SHIFT 0x0
+#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc_MASK 0xff00
+#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT 0x8
+#define PM_FUSES_8__TDC_VDDC_PkgLimit_MASK 0xffff0000
+#define PM_FUSES_8__TDC_VDDC_PkgLimit__SHIFT 0x10
+#define PM_FUSES_9__Reserved_MASK 0xff
+#define PM_FUSES_9__Reserved__SHIFT 0x0
+#define PM_FUSES_9__LPMLTemperatureMax_MASK 0xff00
+#define PM_FUSES_9__LPMLTemperatureMax__SHIFT 0x8
+#define PM_FUSES_9__LPMLTemperatureMin_MASK 0xff0000
+#define PM_FUSES_9__LPMLTemperatureMin__SHIFT 0x10
+#define PM_FUSES_9__TdcWaterfallCtl_MASK 0xff000000
+#define PM_FUSES_9__TdcWaterfallCtl__SHIFT 0x18
+#define PM_FUSES_10__LPMLTemperatureScaler_3_MASK 0xff
+#define PM_FUSES_10__LPMLTemperatureScaler_3__SHIFT 0x0
+#define PM_FUSES_10__LPMLTemperatureScaler_2_MASK 0xff00
+#define PM_FUSES_10__LPMLTemperatureScaler_2__SHIFT 0x8
+#define PM_FUSES_10__LPMLTemperatureScaler_1_MASK 0xff0000
+#define PM_FUSES_10__LPMLTemperatureScaler_1__SHIFT 0x10
+#define PM_FUSES_10__LPMLTemperatureScaler_0_MASK 0xff000000
+#define PM_FUSES_10__LPMLTemperatureScaler_0__SHIFT 0x18
+#define PM_FUSES_11__LPMLTemperatureScaler_7_MASK 0xff
+#define PM_FUSES_11__LPMLTemperatureScaler_7__SHIFT 0x0
+#define PM_FUSES_11__LPMLTemperatureScaler_6_MASK 0xff00
+#define PM_FUSES_11__LPMLTemperatureScaler_6__SHIFT 0x8
+#define PM_FUSES_11__LPMLTemperatureScaler_5_MASK 0xff0000
+#define PM_FUSES_11__LPMLTemperatureScaler_5__SHIFT 0x10
+#define PM_FUSES_11__LPMLTemperatureScaler_4_MASK 0xff000000
+#define PM_FUSES_11__LPMLTemperatureScaler_4__SHIFT 0x18
+#define PM_FUSES_12__LPMLTemperatureScaler_11_MASK 0xff
+#define PM_FUSES_12__LPMLTemperatureScaler_11__SHIFT 0x0
+#define PM_FUSES_12__LPMLTemperatureScaler_10_MASK 0xff00
+#define PM_FUSES_12__LPMLTemperatureScaler_10__SHIFT 0x8
+#define PM_FUSES_12__LPMLTemperatureScaler_9_MASK 0xff0000
+#define PM_FUSES_12__LPMLTemperatureScaler_9__SHIFT 0x10
+#define PM_FUSES_12__LPMLTemperatureScaler_8_MASK 0xff000000
+#define PM_FUSES_12__LPMLTemperatureScaler_8__SHIFT 0x18
+#define PM_FUSES_13__LPMLTemperatureScaler_15_MASK 0xff
+#define PM_FUSES_13__LPMLTemperatureScaler_15__SHIFT 0x0
+#define PM_FUSES_13__LPMLTemperatureScaler_14_MASK 0xff00
+#define PM_FUSES_13__LPMLTemperatureScaler_14__SHIFT 0x8
+#define PM_FUSES_13__LPMLTemperatureScaler_13_MASK 0xff0000
+#define PM_FUSES_13__LPMLTemperatureScaler_13__SHIFT 0x10
+#define PM_FUSES_13__LPMLTemperatureScaler_12_MASK 0xff000000
+#define PM_FUSES_13__LPMLTemperatureScaler_12__SHIFT 0x18
+#define PM_FUSES_14__GnbLPML_3_MASK 0xff
+#define PM_FUSES_14__GnbLPML_3__SHIFT 0x0
+#define PM_FUSES_14__GnbLPML_2_MASK 0xff00
+#define PM_FUSES_14__GnbLPML_2__SHIFT 0x8
+#define PM_FUSES_14__GnbLPML_1_MASK 0xff0000
+#define PM_FUSES_14__GnbLPML_1__SHIFT 0x10
+#define PM_FUSES_14__GnbLPML_0_MASK 0xff000000
+#define PM_FUSES_14__GnbLPML_0__SHIFT 0x18
+#define PM_FUSES_15__GnbLPML_7_MASK 0xff
+#define PM_FUSES_15__GnbLPML_7__SHIFT 0x0
+#define PM_FUSES_15__GnbLPML_6_MASK 0xff00
+#define PM_FUSES_15__GnbLPML_6__SHIFT 0x8
+#define PM_FUSES_15__GnbLPML_5_MASK 0xff0000
+#define PM_FUSES_15__GnbLPML_5__SHIFT 0x10
+#define PM_FUSES_15__GnbLPML_4_MASK 0xff000000
+#define PM_FUSES_15__GnbLPML_4__SHIFT 0x18
+#define PM_FUSES_16__GnbLPML_11_MASK 0xff
+#define PM_FUSES_16__GnbLPML_11__SHIFT 0x0
+#define PM_FUSES_16__GnbLPML_10_MASK 0xff00
+#define PM_FUSES_16__GnbLPML_10__SHIFT 0x8
+#define PM_FUSES_16__GnbLPML_9_MASK 0xff0000
+#define PM_FUSES_16__GnbLPML_9__SHIFT 0x10
+#define PM_FUSES_16__GnbLPML_8_MASK 0xff000000
+#define PM_FUSES_16__GnbLPML_8__SHIFT 0x18
+#define PM_FUSES_17__GnbLPML_15_MASK 0xff
+#define PM_FUSES_17__GnbLPML_15__SHIFT 0x0
+#define PM_FUSES_17__GnbLPML_14_MASK 0xff00
+#define PM_FUSES_17__GnbLPML_14__SHIFT 0x8
+#define PM_FUSES_17__GnbLPML_13_MASK 0xff0000
+#define PM_FUSES_17__GnbLPML_13__SHIFT 0x10
+#define PM_FUSES_17__GnbLPML_12_MASK 0xff000000
+#define PM_FUSES_17__GnbLPML_12__SHIFT 0x18
+#define PM_FUSES_18__Reserved1_1_MASK 0xff
+#define PM_FUSES_18__Reserved1_1__SHIFT 0x0
+#define PM_FUSES_18__Reserved1_0_MASK 0xff00
+#define PM_FUSES_18__Reserved1_0__SHIFT 0x8
+#define PM_FUSES_18__GnbLPMLMinVid_MASK 0xff0000
+#define PM_FUSES_18__GnbLPMLMinVid__SHIFT 0x10
+#define PM_FUSES_18__GnbLPMLMaxVid_MASK 0xff000000
+#define PM_FUSES_18__GnbLPMLMaxVid__SHIFT 0x18
+#define PM_FUSES_19__BapmVddCBaseLeakageLoSidd_MASK 0xffff
+#define PM_FUSES_19__BapmVddCBaseLeakageLoSidd__SHIFT 0x0
+#define PM_FUSES_19__BapmVddCBaseLeakageHiSidd_MASK 0xffff0000
+#define PM_FUSES_19__BapmVddCBaseLeakageHiSidd__SHIFT 0x10
+#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_0__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_1__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_2__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_3__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_4__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_5__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_6__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_7__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_8__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_9__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_10__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_11__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_12__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_13__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_14__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_15__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_16__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_17__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_18__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_19__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_20__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_21__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_22__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_23__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_24__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_25__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_26__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_27__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_28__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_29__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_30__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_31__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_32__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_33__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_34__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_35__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_36__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_37__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_38__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_39__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_40__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_41__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_42__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_43__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_44__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_45__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_46__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_47__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_48__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_49__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_50__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_51__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_52__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_53__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_54__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_55__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_56__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_57__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_58__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_59__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_60__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_61__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_62__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_63__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_64__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_65__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_66__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_67__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_68__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_69__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_70__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_71__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_72__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_73__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_74__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_75__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_76__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_77__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_78__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_79__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_80__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_81__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_82__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_83__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_84__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_85__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_86__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_87__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_88__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_89__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_90__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_91__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_92__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_93__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_94__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_95__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_96__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_97__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_98__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_99__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_100__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_101__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_102__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_103__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_104__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_105__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_106__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_107__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_108__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_109__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_110__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_111__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_112__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_113__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_114__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_115__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_116__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_117__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_118__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_119__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_120__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_121__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_122__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_123__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_124__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_125__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_126__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_127__DATA__SHIFT 0x0
+#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1
+#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0
+#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2
+#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2
+#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8
+#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3
+#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10
+#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8
+#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000
+#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10
+#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000
+#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18
+#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000
+#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b
+#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000
+#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c
+#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1
+#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0
+#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2
+#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3
+#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x7
+#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x0
+#define CG_THERMAL_CTRL__THERM_INC_CLK_MASK 0x8
+#define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT 0x3
+#define CG_THERMAL_CTRL__SPARE_MASK 0x3ff0
+#define CG_THERMAL_CTRL__SPARE__SHIFT 0x4
+#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x3fc000
+#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0xe
+#define CG_THERMAL_CTRL__RESERVED_MASK 0x1c00000
+#define CG_THERMAL_CTRL__RESERVED__SHIFT 0x16
+#define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK 0x2000000
+#define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT 0x19
+#define CG_THERMAL_CTRL__CTF_PAD_EN_MASK 0x4000000
+#define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT 0x1a
+#define CG_THERMAL_STATUS__SPARE_MASK 0x1ff
+#define CG_THERMAL_STATUS__SPARE__SHIFT 0x0
+#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x1fe00
+#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9
+#define CG_THERMAL_STATUS__THERM_ALERT_MASK 0x20000
+#define CG_THERMAL_STATUS__THERM_ALERT__SHIFT 0x11
+#define CG_THERMAL_STATUS__GEN_STATUS_MASK 0x3c0000
+#define CG_THERMAL_STATUS__GEN_STATUS__SHIFT 0x12
+#define CG_THERMAL_INT__DIG_THERM_CTF_MASK 0xff
+#define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT 0x0
+#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0xff00
+#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x8
+#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0xff0000
+#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x10
+#define CG_THERMAL_INT__THERM_INT_MASK_MASK 0xf000000
+#define CG_THERMAL_INT__THERM_INT_MASK__SHIFT 0x18
+#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0xf
+#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0
+#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0xf0
+#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4
+#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x200
+#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9
+#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000
+#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14
+#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x1ff
+#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0
+#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x3fe00
+#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9
+#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0xff
+#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0
+#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0xff00
+#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8
+#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x10000
+#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10
+#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x7e0000
+#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x800000
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xff000000
+#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18
+#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0xff
+#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0
+#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00
+#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8
+#define CG_FDO_CTRL1__M_MASK 0xff0000
+#define CG_FDO_CTRL1__M__SHIFT 0x10
+#define CG_FDO_CTRL1__RESERVED_MASK 0x3f000000
+#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18
+#define CG_FDO_CTRL1__FDO_PWRDNB_MASK 0x40000000
+#define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT 0x1e
+#define CG_FDO_CTRL2__TMIN_MASK 0xff
+#define CG_FDO_CTRL2__TMIN__SHIFT 0x0
+#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x700
+#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8
+#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x3800
+#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb
+#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x1c000
+#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe
+#define CG_FDO_CTRL2__TMAX_MASK 0x1fe0000
+#define CG_FDO_CTRL2__TMAX__SHIFT 0x11
+#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xfe000000
+#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19
+#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x7
+#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0
+#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8
+#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3
+#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff
+#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0
+#define CC_THM_STRAPS0__TMON0_BGADJ_MASK 0x1fe
+#define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT 0x1
+#define CC_THM_STRAPS0__TMON1_BGADJ_MASK 0x1fe00
+#define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT 0x9
+#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK 0x20000
+#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT 0x11
+#define CC_THM_STRAPS0__NUM_ACQ_MASK 0x1c0000
+#define CC_THM_STRAPS0__NUM_ACQ__SHIFT 0x12
+#define CC_THM_STRAPS0__TMON_CLK_SEL_MASK 0xe00000
+#define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT 0x15
+#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK 0x1000000
+#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT 0x18
+#define CC_THM_STRAPS0__CTF_DISABLE_MASK 0x2000000
+#define CC_THM_STRAPS0__CTF_DISABLE__SHIFT 0x19
+#define CC_THM_STRAPS0__TMON0_DISABLE_MASK 0x4000000
+#define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT 0x1a
+#define CC_THM_STRAPS0__TMON1_DISABLE_MASK 0x8000000
+#define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT 0x1b
+#define CC_THM_STRAPS0__TMON2_DISABLE_MASK 0x10000000
+#define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT 0x1c
+#define CC_THM_STRAPS0__TMON3_DISABLE_MASK 0x20000000
+#define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d
+#define CC_THM_STRAPS0__UNUSED_MASK 0x80000000
+#define CC_THM_STRAPS0__UNUSED__SHIFT 0x1f
+#define THM_TMON0_RDIL0_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL1_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL2_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL3_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL4_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL5_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL6_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL7_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL8_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL9_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL10_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL11_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL12_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL13_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL14_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL15_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR0_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR1_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR2_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR3_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR4_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR5_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR6_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR7_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR8_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR9_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR10_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR11_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR12_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR13_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR14_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR15_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_INT_DATA__Z_MASK 0x7ff
+#define THM_TMON0_INT_DATA__Z__SHIFT 0x0
+#define THM_TMON0_INT_DATA__VALID_MASK 0x800
+#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_INT_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x1f
+#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0
+#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0xffe0
+#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5
+#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1
+#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0
+#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2
+#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3
+#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40
+#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6
+#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100
+#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8
+#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200
+#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9
+#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400
+#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa
+#define GENERAL_PWRMGT__SPARE11_MASK 0x800
+#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb
+#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000
+#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe
+#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000
+#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf
+#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000
+#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10
+#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000
+#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11
+#define GENERAL_PWRMGT__SPARE18_MASK 0x40000
+#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12
+#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000
+#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13
+#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000
+#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17
+#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000
+#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b
+#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000
+#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c
+#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3
+#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0
+#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4
+#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2
+#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8
+#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3
+#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10
+#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4
+#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0
+#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5
+#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1
+#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0
+#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1_MASK 0x2
+#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1__SHIFT 0x1
+#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN_MASK 0x4
+#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN__SHIFT 0x2
+#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10
+#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4
+#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20
+#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5
+#define SCLK_PWRMGT_CNTL__RESERVED_0_MASK 0x40
+#define SCLK_PWRMGT_CNTL__RESERVED_0__SHIFT 0x6
+#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN_MASK 0x80
+#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN__SHIFT 0x7
+#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON_MASK 0x100
+#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON__SHIFT 0x8
+#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF_MASK 0x200
+#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF__SHIFT 0x9
+#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF_MASK 0x400
+#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF__SHIFT 0xa
+#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1_MASK 0x800
+#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1__SHIFT 0xb
+#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2_MASK 0x1000
+#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2__SHIFT 0xc
+#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3_MASK 0x2000
+#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3__SHIFT 0xd
+#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000
+#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe
+#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000
+#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf
+#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000
+#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10
+#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000
+#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15
+#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL_MASK 0x400000
+#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL__SHIFT 0x16
+#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN_MASK 0x800000
+#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN__SHIFT 0x17
+#define SCLK_PWRMGT_CNTL__RESERVED_3_MASK 0x1000000
+#define SCLK_PWRMGT_CNTL__RESERVED_3__SHIFT 0x18
+#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN_MASK 0x2000000
+#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN__SHIFT 0x19
+#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT_MASK 0x10000000
+#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT__SHIFT 0x1c
+#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT_MASK 0x20000000
+#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT__SHIFT 0x1d
+#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN_MASK 0x40000000
+#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN__SHIFT 0x1e
+#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE_MASK 0x80000000
+#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE__SHIFT 0x1f
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf
+#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
+#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0
+#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4
+#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00
+#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8
+#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000
+#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf
+#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000
+#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c
+#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff
+#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0
+#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f
+#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0
+#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80
+#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7
+#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
+#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
+#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
+#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
+#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000
+#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11
+#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000
+#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12
+#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000
+#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13
+#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000
+#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14
+#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000
+#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15
+#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000
+#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16
+#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000
+#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17
+#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000
+#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19
+#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000
+#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a
+#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000
+#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b
+#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000
+#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c
+#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000
+#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d
+#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000
+#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e
+#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
+#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2
+#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1
+#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4
+#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2
+#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8
+#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10
+#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4
+#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40
+#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6
+#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80
+#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7
+#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100
+#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8
+#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200
+#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9
+#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400
+#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa
+#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800
+#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe
+#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000
+#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15
+#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000
+#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14
+#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
+#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
+#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
+#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
+#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
+#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
+#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000
+#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10
+#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
+#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
+#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1
+#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0
+#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2
+#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3
+#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10
+#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4
+#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20
+#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd
+#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000
+#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe
+#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000
+#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13
+#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000
+#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14
+#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000
+#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c
+#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff
+#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0
+#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000
+#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10
+#define SCLK_MIN_DIV__FRACV_MASK 0xfff
+#define SCLK_MIN_DIV__FRACV__SHIFT 0x0
+#define SCLK_MIN_DIV__INTV_MASK 0x7f000
+#define SCLK_MIN_DIV__INTV__SHIFT 0xc
+#define LCAC_SX0_CNTL__SX0_ENABLE_MASK 0x1
+#define LCAC_SX0_CNTL__SX0_ENABLE__SHIFT 0x0
+#define LCAC_SX0_CNTL__SX0_THRESHOLD_MASK 0x1fffe
+#define LCAC_SX0_CNTL__SX0_THRESHOLD__SHIFT 0x1
+#define LCAC_SX0_CNTL__SX0_BLOCK_ID_MASK 0x3e0000
+#define LCAC_SX0_CNTL__SX0_BLOCK_ID__SHIFT 0x11
+#define LCAC_SX0_CNTL__SX0_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_SX0_CNTL__SX0_SIGNAL_ID__SHIFT 0x16
+#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL_MASK 0xffffffff
+#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL__SHIFT 0x0
+#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL_MASK 0xffffffff
+#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL__SHIFT 0x0
+#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1
+#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0
+#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1
+#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0
+#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0
+#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1
+#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0
+#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1
+#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0
+#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0
+#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1
+#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0
+#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1
+#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0
+#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0
+#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1
+#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0
+#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1
+#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0
+#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0
+#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1
+#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0
+#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe
+#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1
+#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000
+#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11
+#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16
+#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff
+#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0
+#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff
+#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0
+#define ROM_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define ROM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define ROM_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define ROM_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define ROM_CNTL__SCK_OVERWRITE_MASK 0x2
+#define ROM_CNTL__SCK_OVERWRITE__SHIFT 0x1
+#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x4
+#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x2
+#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME_MASK 0xff00
+#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME__SHIFT 0x8
+#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME_MASK 0xff0000
+#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME__SHIFT 0x10
+#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0xf000000
+#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18
+#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK_MASK 0xf0000000
+#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK__SHIFT 0x1c
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0xffffff
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x1000000
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x2000000
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0xc000000
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a
+#define ROM_STATUS__ROM_BUSY_MASK 0x1
+#define ROM_STATUS__ROM_BUSY__SHIFT 0x0
+#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0xf
+#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0
+#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
+#define ROM_INDEX__ROM_INDEX_MASK 0xffffff
+#define ROM_INDEX__ROM_INDEX__SHIFT 0x0
+#define ROM_DATA__ROM_DATA_MASK 0xffffffff
+#define ROM_DATA__ROM_DATA__SHIFT 0x0
+#define ROM_START__ROM_START_MASK 0xffffff
+#define ROM_START__ROM_START__SHIFT 0x0
+#define ROM_SW_CNTL__DATA_SIZE_MASK 0xffff
+#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0
+#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x30000
+#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10
+#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x40000
+#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12
+#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x1
+#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0
+#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0xff
+#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0
+#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xffffff00
+#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8
+#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
+
+#endif /* SMU_7_0_1_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_d.h
new file mode 100644
index 000000000000..57588b11ff1a
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_d.h
@@ -0,0 +1,1344 @@
+/*
+ * SMU_7_1_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef SMU_7_1_0_D_H
+#define SMU_7_1_0_D_H
+
+#define mmGCK_SMC_IND_INDEX 0x80
+#define mmGCK0_GCK_SMC_IND_INDEX 0x80
+#define mmGCK1_GCK_SMC_IND_INDEX 0x82
+#define mmGCK2_GCK_SMC_IND_INDEX 0x84
+#define mmGCK3_GCK_SMC_IND_INDEX 0x86
+#define mmGCK_SMC_IND_DATA 0x81
+#define mmGCK0_GCK_SMC_IND_DATA 0x81
+#define mmGCK1_GCK_SMC_IND_DATA 0x83
+#define mmGCK2_GCK_SMC_IND_DATA 0x85
+#define mmGCK3_GCK_SMC_IND_DATA 0x87
+#define ixCG_DCLK_CNTL 0xc050009c
+#define ixCG_DCLK_STATUS 0xc05000a0
+#define ixCG_VCLK_CNTL 0xc05000a4
+#define ixCG_VCLK_STATUS 0xc05000a8
+#define ixCG_ECLK_CNTL 0xc05000ac
+#define ixCG_ECLK_STATUS 0xc05000b0
+#define ixCG_ACLK_CNTL 0xc05000dc
+#define ixGCK_DFS_BYPASS_CNTL 0xc0500118
+#define ixCG_SPLL_FUNC_CNTL 0xc0500140
+#define ixCG_SPLL_FUNC_CNTL_2 0xc0500144
+#define ixCG_SPLL_FUNC_CNTL_3 0xc0500148
+#define ixCG_SPLL_FUNC_CNTL_4 0xc050014c
+#define ixCG_SPLL_FUNC_CNTL_5 0xc0500150
+#define ixCG_SPLL_FUNC_CNTL_6 0xc0500154
+#define ixCG_SPLL_FUNC_CNTL_7 0xc0500158
+#define ixSPLL_CNTL_MODE 0xc0500160
+#define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164
+#define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168
+#define ixMPLL_BYPASSCLK_SEL 0xc050019c
+#define ixCG_CLKPIN_CNTL 0xc05001a0
+#define ixCG_CLKPIN_CNTL_2 0xc05001a4
+#define ixCG_CLKPIN_CNTL_DC 0xc0500204
+#define ixTHM_CLK_CNTL 0xc05001a8
+#define ixMISC_CLK_CTRL 0xc05001ac
+#define ixGCK_PLL_TEST_CNTL 0xc05001c0
+#define ixGCK_PLL_TEST_CNTL_2 0xc05001c4
+#define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8
+#define mmSMC_IND_INDEX 0x80
+#define mmSMC0_SMC_IND_INDEX 0x80
+#define mmSMC1_SMC_IND_INDEX 0x82
+#define mmSMC2_SMC_IND_INDEX 0x84
+#define mmSMC3_SMC_IND_INDEX 0x86
+#define mmSMC_IND_DATA 0x81
+#define mmSMC0_SMC_IND_DATA 0x81
+#define mmSMC1_SMC_IND_DATA 0x83
+#define mmSMC2_SMC_IND_DATA 0x85
+#define mmSMC3_SMC_IND_DATA 0x87
+#define mmSMC_IND_INDEX_0 0x80
+#define mmSMC_IND_DATA_0 0x81
+#define mmSMC_IND_INDEX_1 0x82
+#define mmSMC_IND_DATA_1 0x83
+#define mmSMC_IND_INDEX_2 0x84
+#define mmSMC_IND_DATA_2 0x85
+#define mmSMC_IND_INDEX_3 0x86
+#define mmSMC_IND_DATA_3 0x87
+#define mmSMC_IND_INDEX_4 0x88
+#define mmSMC_IND_DATA_4 0x89
+#define mmSMC_IND_INDEX_5 0x8a
+#define mmSMC_IND_DATA_5 0x8b
+#define mmSMC_IND_INDEX_6 0x8c
+#define mmSMC_IND_DATA_6 0x8d
+#define mmSMC_IND_INDEX_7 0x8e
+#define mmSMC_IND_DATA_7 0x8f
+#define mmSMC_IND_ACCESS_CNTL 0x90
+#define mmSMC_MESSAGE_0 0x94
+#define mmSMC_RESP_0 0x95
+#define mmSMC_MESSAGE_1 0x96
+#define mmSMC_RESP_1 0x97
+#define mmSMC_MESSAGE_2 0x98
+#define mmSMC_RESP_2 0x99
+#define mmSMC_MESSAGE_3 0x9a
+#define mmSMC_RESP_3 0x9b
+#define mmSMC_MESSAGE_4 0x9c
+#define mmSMC_RESP_4 0x9d
+#define mmSMC_MESSAGE_5 0x9e
+#define mmSMC_RESP_5 0x9f
+#define mmSMC_MESSAGE_6 0xa0
+#define mmSMC_RESP_6 0xa1
+#define mmSMC_MESSAGE_7 0xa2
+#define mmSMC_RESP_7 0xa3
+#define mmSMC_MSG_ARG_0 0xa4
+#define mmSMC_MSG_ARG_1 0xa5
+#define mmSMC_MSG_ARG_2 0xa6
+#define mmSMC_MSG_ARG_3 0xa7
+#define mmSMC_MSG_ARG_4 0xa8
+#define mmSMC_MSG_ARG_5 0xa9
+#define mmSMC_MSG_ARG_6 0xaa
+#define mmSMC_MSG_ARG_7 0xab
+#define mmSMC_MESSAGE_8 0xb5
+#define mmSMC_RESP_8 0xb6
+#define mmSMC_MESSAGE_9 0xb7
+#define mmSMC_RESP_9 0xb8
+#define mmSMC_MESSAGE_10 0xb9
+#define mmSMC_RESP_10 0xba
+#define mmSMC_MESSAGE_11 0xbb
+#define mmSMC_RESP_11 0xbc
+#define mmSMC_MSG_ARG_8 0xbd
+#define mmSMC_MSG_ARG_9 0xbe
+#define mmSMC_MSG_ARG_10 0xbf
+#define mmSMC_MSG_ARG_11 0x91
+#define ixSMC_SYSCON_RESET_CNTL 0x80000000
+#define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004
+#define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008
+#define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c
+#define ixSMC_SYSCON_MISC_CNTL 0x80000010
+#define ixSMC_SYSCON_MSG_ARG_0 0x80000068
+#define ixSMC_PC_C 0x80000370
+#define ixSMC_SCRATCH9 0x80000424
+#define mmGPIOPAD_SW_INT_STAT 0x180
+#define mmGPIOPAD_STRENGTH 0x181
+#define mmGPIOPAD_MASK 0x182
+#define mmGPIOPAD_A 0x183
+#define mmGPIOPAD_EN 0x184
+#define mmGPIOPAD_Y 0x185
+#define mmGPIOPAD_PINSTRAPS 0x186
+#define mmGPIOPAD_INT_STAT_EN 0x187
+#define mmGPIOPAD_INT_STAT 0x188
+#define mmGPIOPAD_INT_STAT_AK 0x189
+#define mmGPIOPAD_INT_EN 0x18a
+#define mmGPIOPAD_INT_TYPE 0x18b
+#define mmGPIOPAD_INT_POLARITY 0x18c
+#define mmGPIOPAD_EXTERN_TRIG_CNTL 0x18d
+#define mmGPIOPAD_RCVR_SEL 0x191
+#define mmGPIOPAD_PU_EN 0x192
+#define mmGPIOPAD_PD_EN 0x193
+#define mmCG_FPS_CNT 0x1a4
+#define mmSMU_SMC_IND_INDEX 0x80
+#define mmSMU0_SMU_SMC_IND_INDEX 0x80
+#define mmSMU1_SMU_SMC_IND_INDEX 0x82
+#define mmSMU2_SMU_SMC_IND_INDEX 0x84
+#define mmSMU3_SMU_SMC_IND_INDEX 0x86
+#define mmSMU_SMC_IND_DATA 0x81
+#define mmSMU0_SMU_SMC_IND_DATA 0x81
+#define mmSMU1_SMU_SMC_IND_DATA 0x83
+#define mmSMU2_SMU_SMC_IND_DATA 0x85
+#define mmSMU3_SMU_SMC_IND_DATA 0x87
+#define ixRCU_UC_EVENTS 0xc0000004
+#define ixRCU_MISC_CTRL 0xc0000010
+#define ixCC_RCU_FUSES 0xc00c0000
+#define ixCC_SMU_MISC_FUSES 0xc00c0004
+#define ixCC_SCLK_VID_FUSES 0xc00c0008
+#define ixCC_GIO_IOCCFG_FUSES 0xc00c000c
+#define ixCC_GIO_IOC_FUSES 0xc00c0010
+#define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c
+#define ixCC_TST_ID_STRAPS 0xc00c0020
+#define ixCC_FCTRL_FUSES 0xc00c0024
+#define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020
+#define ixSMU_STATUS 0xe0003088
+#define ixSMU_FIRMWARE 0xe00030a4
+#define ixSMU_INPUT_DATA 0xe00030b8
+#define ixSMU_EFUSE_0 0xc0100000
+#define ixDPM_TABLE_1 0x3f000
+#define ixDPM_TABLE_2 0x3f004
+#define ixDPM_TABLE_3 0x3f008
+#define ixDPM_TABLE_4 0x3f00c
+#define ixDPM_TABLE_5 0x3f010
+#define ixDPM_TABLE_6 0x3f014
+#define ixDPM_TABLE_7 0x3f018
+#define ixDPM_TABLE_8 0x3f01c
+#define ixDPM_TABLE_9 0x3f020
+#define ixDPM_TABLE_10 0x3f024
+#define ixDPM_TABLE_11 0x3f028
+#define ixDPM_TABLE_12 0x3f02c
+#define ixDPM_TABLE_13 0x3f030
+#define ixDPM_TABLE_14 0x3f034
+#define ixDPM_TABLE_15 0x3f038
+#define ixDPM_TABLE_16 0x3f03c
+#define ixDPM_TABLE_17 0x3f040
+#define ixDPM_TABLE_18 0x3f044
+#define ixDPM_TABLE_19 0x3f048
+#define ixDPM_TABLE_20 0x3f04c
+#define ixDPM_TABLE_21 0x3f050
+#define ixDPM_TABLE_22 0x3f054
+#define ixDPM_TABLE_23 0x3f058
+#define ixDPM_TABLE_24 0x3f05c
+#define ixDPM_TABLE_25 0x3f060
+#define ixDPM_TABLE_26 0x3f064
+#define ixDPM_TABLE_27 0x3f068
+#define ixDPM_TABLE_28 0x3f06c
+#define ixDPM_TABLE_29 0x3f070
+#define ixDPM_TABLE_30 0x3f074
+#define ixDPM_TABLE_31 0x3f078
+#define ixDPM_TABLE_32 0x3f07c
+#define ixDPM_TABLE_33 0x3f080
+#define ixDPM_TABLE_34 0x3f084
+#define ixDPM_TABLE_35 0x3f088
+#define ixDPM_TABLE_36 0x3f08c
+#define ixDPM_TABLE_37 0x3f090
+#define ixDPM_TABLE_38 0x3f094
+#define ixDPM_TABLE_39 0x3f098
+#define ixDPM_TABLE_40 0x3f09c
+#define ixDPM_TABLE_41 0x3f0a0
+#define ixDPM_TABLE_42 0x3f0a4
+#define ixDPM_TABLE_43 0x3f0a8
+#define ixDPM_TABLE_44 0x3f0ac
+#define ixDPM_TABLE_45 0x3f0b0
+#define ixDPM_TABLE_46 0x3f0b4
+#define ixDPM_TABLE_47 0x3f0b8
+#define ixDPM_TABLE_48 0x3f0bc
+#define ixDPM_TABLE_49 0x3f0c0
+#define ixDPM_TABLE_50 0x3f0c4
+#define ixDPM_TABLE_51 0x3f0c8
+#define ixDPM_TABLE_52 0x3f0cc
+#define ixDPM_TABLE_53 0x3f0d0
+#define ixDPM_TABLE_54 0x3f0d4
+#define ixDPM_TABLE_55 0x3f0d8
+#define ixDPM_TABLE_56 0x3f0dc
+#define ixDPM_TABLE_57 0x3f0e0
+#define ixDPM_TABLE_58 0x3f0e4
+#define ixDPM_TABLE_59 0x3f0e8
+#define ixDPM_TABLE_60 0x3f0ec
+#define ixDPM_TABLE_61 0x3f0f0
+#define ixDPM_TABLE_62 0x3f0f4
+#define ixDPM_TABLE_63 0x3f0f8
+#define ixDPM_TABLE_64 0x3f0fc
+#define ixDPM_TABLE_65 0x3f100
+#define ixDPM_TABLE_66 0x3f104
+#define ixDPM_TABLE_67 0x3f108
+#define ixDPM_TABLE_68 0x3f10c
+#define ixDPM_TABLE_69 0x3f110
+#define ixDPM_TABLE_70 0x3f114
+#define ixDPM_TABLE_71 0x3f118
+#define ixDPM_TABLE_72 0x3f11c
+#define ixDPM_TABLE_73 0x3f120
+#define ixDPM_TABLE_74 0x3f124
+#define ixDPM_TABLE_75 0x3f128
+#define ixDPM_TABLE_76 0x3f12c
+#define ixDPM_TABLE_77 0x3f130
+#define ixDPM_TABLE_78 0x3f134
+#define ixDPM_TABLE_79 0x3f138
+#define ixDPM_TABLE_80 0x3f13c
+#define ixDPM_TABLE_81 0x3f140
+#define ixDPM_TABLE_82 0x3f144
+#define ixDPM_TABLE_83 0x3f148
+#define ixDPM_TABLE_84 0x3f14c
+#define ixDPM_TABLE_85 0x3f150
+#define ixDPM_TABLE_86 0x3f154
+#define ixDPM_TABLE_87 0x3f158
+#define ixDPM_TABLE_88 0x3f15c
+#define ixDPM_TABLE_89 0x3f160
+#define ixDPM_TABLE_90 0x3f164
+#define ixDPM_TABLE_91 0x3f168
+#define ixDPM_TABLE_92 0x3f16c
+#define ixDPM_TABLE_93 0x3f170
+#define ixDPM_TABLE_94 0x3f174
+#define ixDPM_TABLE_95 0x3f178
+#define ixDPM_TABLE_96 0x3f17c
+#define ixDPM_TABLE_97 0x3f180
+#define ixDPM_TABLE_98 0x3f184
+#define ixDPM_TABLE_99 0x3f188
+#define ixDPM_TABLE_100 0x3f18c
+#define ixDPM_TABLE_101 0x3f190
+#define ixDPM_TABLE_102 0x3f194
+#define ixDPM_TABLE_103 0x3f198
+#define ixDPM_TABLE_104 0x3f19c
+#define ixDPM_TABLE_105 0x3f1a0
+#define ixDPM_TABLE_106 0x3f1a4
+#define ixDPM_TABLE_107 0x3f1a8
+#define ixDPM_TABLE_108 0x3f1ac
+#define ixDPM_TABLE_109 0x3f1b0
+#define ixDPM_TABLE_110 0x3f1b4
+#define ixDPM_TABLE_111 0x3f1b8
+#define ixDPM_TABLE_112 0x3f1bc
+#define ixDPM_TABLE_113 0x3f1c0
+#define ixDPM_TABLE_114 0x3f1c4
+#define ixDPM_TABLE_115 0x3f1c8
+#define ixDPM_TABLE_116 0x3f1cc
+#define ixDPM_TABLE_117 0x3f1d0
+#define ixDPM_TABLE_118 0x3f1d4
+#define ixDPM_TABLE_119 0x3f1d8
+#define ixDPM_TABLE_120 0x3f1dc
+#define ixDPM_TABLE_121 0x3f1e0
+#define ixDPM_TABLE_122 0x3f1e4
+#define ixDPM_TABLE_123 0x3f1e8
+#define ixDPM_TABLE_124 0x3f1ec
+#define ixDPM_TABLE_125 0x3f1f0
+#define ixDPM_TABLE_126 0x3f1f4
+#define ixDPM_TABLE_127 0x3f1f8
+#define ixDPM_TABLE_128 0x3f1fc
+#define ixDPM_TABLE_129 0x3f200
+#define ixDPM_TABLE_130 0x3f204
+#define ixDPM_TABLE_131 0x3f208
+#define ixDPM_TABLE_132 0x3f20c
+#define ixDPM_TABLE_133 0x3f210
+#define ixDPM_TABLE_134 0x3f214
+#define ixDPM_TABLE_135 0x3f218
+#define ixDPM_TABLE_136 0x3f21c
+#define ixDPM_TABLE_137 0x3f220
+#define ixDPM_TABLE_138 0x3f224
+#define ixDPM_TABLE_139 0x3f228
+#define ixDPM_TABLE_140 0x3f22c
+#define ixDPM_TABLE_141 0x3f230
+#define ixDPM_TABLE_142 0x3f234
+#define ixDPM_TABLE_143 0x3f238
+#define ixDPM_TABLE_144 0x3f23c
+#define ixDPM_TABLE_145 0x3f240
+#define ixDPM_TABLE_146 0x3f244
+#define ixDPM_TABLE_147 0x3f248
+#define ixDPM_TABLE_148 0x3f24c
+#define ixDPM_TABLE_149 0x3f250
+#define ixDPM_TABLE_150 0x3f254
+#define ixDPM_TABLE_151 0x3f258
+#define ixDPM_TABLE_152 0x3f25c
+#define ixDPM_TABLE_153 0x3f260
+#define ixDPM_TABLE_154 0x3f264
+#define ixDPM_TABLE_155 0x3f268
+#define ixDPM_TABLE_156 0x3f26c
+#define ixDPM_TABLE_157 0x3f270
+#define ixDPM_TABLE_158 0x3f274
+#define ixDPM_TABLE_159 0x3f278
+#define ixDPM_TABLE_160 0x3f27c
+#define ixDPM_TABLE_161 0x3f280
+#define ixDPM_TABLE_162 0x3f284
+#define ixDPM_TABLE_163 0x3f288
+#define ixDPM_TABLE_164 0x3f28c
+#define ixDPM_TABLE_165 0x3f290
+#define ixDPM_TABLE_166 0x3f294
+#define ixDPM_TABLE_167 0x3f298
+#define ixDPM_TABLE_168 0x3f29c
+#define ixDPM_TABLE_169 0x3f2a0
+#define ixDPM_TABLE_170 0x3f2a4
+#define ixDPM_TABLE_171 0x3f2a8
+#define ixDPM_TABLE_172 0x3f2ac
+#define ixDPM_TABLE_173 0x3f2b0
+#define ixDPM_TABLE_174 0x3f2b4
+#define ixDPM_TABLE_175 0x3f2b8
+#define ixDPM_TABLE_176 0x3f2bc
+#define ixDPM_TABLE_177 0x3f2c0
+#define ixDPM_TABLE_178 0x3f2c4
+#define ixDPM_TABLE_179 0x3f2c8
+#define ixDPM_TABLE_180 0x3f2cc
+#define ixDPM_TABLE_181 0x3f2d0
+#define ixDPM_TABLE_182 0x3f2d4
+#define ixDPM_TABLE_183 0x3f2d8
+#define ixDPM_TABLE_184 0x3f2dc
+#define ixDPM_TABLE_185 0x3f2e0
+#define ixDPM_TABLE_186 0x3f2e4
+#define ixDPM_TABLE_187 0x3f2e8
+#define ixDPM_TABLE_188 0x3f2ec
+#define ixDPM_TABLE_189 0x3f2f0
+#define ixDPM_TABLE_190 0x3f2f4
+#define ixDPM_TABLE_191 0x3f2f8
+#define ixDPM_TABLE_192 0x3f2fc
+#define ixDPM_TABLE_193 0x3f300
+#define ixDPM_TABLE_194 0x3f304
+#define ixDPM_TABLE_195 0x3f308
+#define ixDPM_TABLE_196 0x3f30c
+#define ixDPM_TABLE_197 0x3f310
+#define ixDPM_TABLE_198 0x3f314
+#define ixDPM_TABLE_199 0x3f318
+#define ixDPM_TABLE_200 0x3f31c
+#define ixDPM_TABLE_201 0x3f320
+#define ixDPM_TABLE_202 0x3f324
+#define ixDPM_TABLE_203 0x3f328
+#define ixDPM_TABLE_204 0x3f32c
+#define ixDPM_TABLE_205 0x3f330
+#define ixDPM_TABLE_206 0x3f334
+#define ixDPM_TABLE_207 0x3f338
+#define ixDPM_TABLE_208 0x3f33c
+#define ixDPM_TABLE_209 0x3f340
+#define ixDPM_TABLE_210 0x3f344
+#define ixDPM_TABLE_211 0x3f348
+#define ixDPM_TABLE_212 0x3f34c
+#define ixDPM_TABLE_213 0x3f350
+#define ixDPM_TABLE_214 0x3f354
+#define ixDPM_TABLE_215 0x3f358
+#define ixDPM_TABLE_216 0x3f35c
+#define ixDPM_TABLE_217 0x3f360
+#define ixDPM_TABLE_218 0x3f364
+#define ixDPM_TABLE_219 0x3f368
+#define ixDPM_TABLE_220 0x3f36c
+#define ixDPM_TABLE_221 0x3f370
+#define ixDPM_TABLE_222 0x3f374
+#define ixDPM_TABLE_223 0x3f378
+#define ixDPM_TABLE_224 0x3f37c
+#define ixDPM_TABLE_225 0x3f380
+#define ixDPM_TABLE_226 0x3f384
+#define ixDPM_TABLE_227 0x3f388
+#define ixDPM_TABLE_228 0x3f38c
+#define ixDPM_TABLE_229 0x3f390
+#define ixDPM_TABLE_230 0x3f394
+#define ixDPM_TABLE_231 0x3f398
+#define ixDPM_TABLE_232 0x3f39c
+#define ixDPM_TABLE_233 0x3f3a0
+#define ixDPM_TABLE_234 0x3f3a4
+#define ixDPM_TABLE_235 0x3f3a8
+#define ixDPM_TABLE_236 0x3f3ac
+#define ixDPM_TABLE_237 0x3f3b0
+#define ixDPM_TABLE_238 0x3f3b4
+#define ixDPM_TABLE_239 0x3f3b8
+#define ixDPM_TABLE_240 0x3f3bc
+#define ixDPM_TABLE_241 0x3f3c0
+#define ixDPM_TABLE_242 0x3f3c4
+#define ixDPM_TABLE_243 0x3f3c8
+#define ixDPM_TABLE_244 0x3f3cc
+#define ixDPM_TABLE_245 0x3f3d0
+#define ixDPM_TABLE_246 0x3f3d4
+#define ixDPM_TABLE_247 0x3f3d8
+#define ixDPM_TABLE_248 0x3f3dc
+#define ixDPM_TABLE_249 0x3f3e0
+#define ixDPM_TABLE_250 0x3f3e4
+#define ixDPM_TABLE_251 0x3f3e8
+#define ixDPM_TABLE_252 0x3f3ec
+#define ixDPM_TABLE_253 0x3f3f0
+#define ixDPM_TABLE_254 0x3f3f4
+#define ixDPM_TABLE_255 0x3f3f8
+#define ixDPM_TABLE_256 0x3f3fc
+#define ixDPM_TABLE_257 0x3f400
+#define ixDPM_TABLE_258 0x3f404
+#define ixDPM_TABLE_259 0x3f408
+#define ixDPM_TABLE_260 0x3f40c
+#define ixDPM_TABLE_261 0x3f410
+#define ixDPM_TABLE_262 0x3f414
+#define ixDPM_TABLE_263 0x3f418
+#define ixDPM_TABLE_264 0x3f41c
+#define ixDPM_TABLE_265 0x3f420
+#define ixDPM_TABLE_266 0x3f424
+#define ixDPM_TABLE_267 0x3f428
+#define ixDPM_TABLE_268 0x3f42c
+#define ixDPM_TABLE_269 0x3f430
+#define ixDPM_TABLE_270 0x3f434
+#define ixDPM_TABLE_271 0x3f438
+#define ixDPM_TABLE_272 0x3f43c
+#define ixDPM_TABLE_273 0x3f440
+#define ixDPM_TABLE_274 0x3f444
+#define ixDPM_TABLE_275 0x3f448
+#define ixDPM_TABLE_276 0x3f44c
+#define ixDPM_TABLE_277 0x3f450
+#define ixDPM_TABLE_278 0x3f454
+#define ixDPM_TABLE_279 0x3f458
+#define ixDPM_TABLE_280 0x3f45c
+#define ixDPM_TABLE_281 0x3f460
+#define ixDPM_TABLE_282 0x3f464
+#define ixDPM_TABLE_283 0x3f468
+#define ixDPM_TABLE_284 0x3f46c
+#define ixDPM_TABLE_285 0x3f470
+#define ixDPM_TABLE_286 0x3f474
+#define ixDPM_TABLE_287 0x3f478
+#define ixDPM_TABLE_288 0x3f47c
+#define ixDPM_TABLE_289 0x3f480
+#define ixDPM_TABLE_290 0x3f484
+#define ixDPM_TABLE_291 0x3f488
+#define ixDPM_TABLE_292 0x3f48c
+#define ixDPM_TABLE_293 0x3f490
+#define ixDPM_TABLE_294 0x3f494
+#define ixDPM_TABLE_295 0x3f498
+#define ixDPM_TABLE_296 0x3f49c
+#define ixDPM_TABLE_297 0x3f4a0
+#define ixDPM_TABLE_298 0x3f4a4
+#define ixDPM_TABLE_299 0x3f4a8
+#define ixDPM_TABLE_300 0x3f4ac
+#define ixDPM_TABLE_301 0x3f4b0
+#define ixDPM_TABLE_302 0x3f4b4
+#define ixDPM_TABLE_303 0x3f4b8
+#define ixDPM_TABLE_304 0x3f4bc
+#define ixDPM_TABLE_305 0x3f4c0
+#define ixDPM_TABLE_306 0x3f4c4
+#define ixDPM_TABLE_307 0x3f4c8
+#define ixDPM_TABLE_308 0x3f4cc
+#define ixDPM_TABLE_309 0x3f4d0
+#define ixDPM_TABLE_310 0x3f4d4
+#define ixDPM_TABLE_311 0x3f4d8
+#define ixDPM_TABLE_312 0x3f4dc
+#define ixDPM_TABLE_313 0x3f4e0
+#define ixDPM_TABLE_314 0x3f4e4
+#define ixDPM_TABLE_315 0x3f4e8
+#define ixDPM_TABLE_316 0x3f4ec
+#define ixDPM_TABLE_317 0x3f4f0
+#define ixDPM_TABLE_318 0x3f4f4
+#define ixDPM_TABLE_319 0x3f4f8
+#define ixDPM_TABLE_320 0x3f4fc
+#define ixDPM_TABLE_321 0x3f500
+#define ixDPM_TABLE_322 0x3f504
+#define ixDPM_TABLE_323 0x3f508
+#define ixDPM_TABLE_324 0x3f50c
+#define ixDPM_TABLE_325 0x3f510
+#define ixDPM_TABLE_326 0x3f514
+#define ixDPM_TABLE_327 0x3f518
+#define ixDPM_TABLE_328 0x3f51c
+#define ixDPM_TABLE_329 0x3f520
+#define ixDPM_TABLE_330 0x3f524
+#define ixDPM_TABLE_331 0x3f528
+#define ixDPM_TABLE_332 0x3f52c
+#define ixDPM_TABLE_333 0x3f530
+#define ixDPM_TABLE_334 0x3f534
+#define ixDPM_TABLE_335 0x3f538
+#define ixDPM_TABLE_336 0x3f53c
+#define ixDPM_TABLE_337 0x3f540
+#define ixDPM_TABLE_338 0x3f544
+#define ixDPM_TABLE_339 0x3f548
+#define ixDPM_TABLE_340 0x3f54c
+#define ixDPM_TABLE_341 0x3f550
+#define ixDPM_TABLE_342 0x3f554
+#define ixDPM_TABLE_343 0x3f558
+#define ixDPM_TABLE_344 0x3f55c
+#define ixDPM_TABLE_345 0x3f560
+#define ixDPM_TABLE_346 0x3f564
+#define ixDPM_TABLE_347 0x3f568
+#define ixDPM_TABLE_348 0x3f56c
+#define ixDPM_TABLE_349 0x3f570
+#define ixDPM_TABLE_350 0x3f574
+#define ixDPM_TABLE_351 0x3f578
+#define ixDPM_TABLE_352 0x3f57c
+#define ixDPM_TABLE_353 0x3f580
+#define ixDPM_TABLE_354 0x3f584
+#define ixDPM_TABLE_355 0x3f588
+#define ixDPM_TABLE_356 0x3f58c
+#define ixDPM_TABLE_357 0x3f590
+#define ixDPM_TABLE_358 0x3f594
+#define ixDPM_TABLE_359 0x3f598
+#define ixDPM_TABLE_360 0x3f59c
+#define ixDPM_TABLE_361 0x3f5a0
+#define ixDPM_TABLE_362 0x3f5a4
+#define ixDPM_TABLE_363 0x3f5a8
+#define ixDPM_TABLE_364 0x3f5ac
+#define ixDPM_TABLE_365 0x3f5b0
+#define ixDPM_TABLE_366 0x3f5b4
+#define ixDPM_TABLE_367 0x3f5b8
+#define ixDPM_TABLE_368 0x3f5bc
+#define ixDPM_TABLE_369 0x3f5c0
+#define ixDPM_TABLE_370 0x3f5c4
+#define ixDPM_TABLE_371 0x3f5c8
+#define ixDPM_TABLE_372 0x3f5cc
+#define ixDPM_TABLE_373 0x3f5d0
+#define ixDPM_TABLE_374 0x3f5d4
+#define ixDPM_TABLE_375 0x3f5d8
+#define ixDPM_TABLE_376 0x3f5dc
+#define ixDPM_TABLE_377 0x3f5e0
+#define ixDPM_TABLE_378 0x3f5e4
+#define ixDPM_TABLE_379 0x3f5e8
+#define ixDPM_TABLE_380 0x3f5ec
+#define ixDPM_TABLE_381 0x3f5f0
+#define ixDPM_TABLE_382 0x3f5f4
+#define ixDPM_TABLE_383 0x3f5f8
+#define ixDPM_TABLE_384 0x3f5fc
+#define ixDPM_TABLE_385 0x3f600
+#define ixDPM_TABLE_386 0x3f604
+#define ixDPM_TABLE_387 0x3f608
+#define ixDPM_TABLE_388 0x3f60c
+#define ixDPM_TABLE_389 0x3f610
+#define ixDPM_TABLE_390 0x3f614
+#define ixDPM_TABLE_391 0x3f618
+#define ixDPM_TABLE_392 0x3f61c
+#define ixDPM_TABLE_393 0x3f620
+#define ixDPM_TABLE_394 0x3f624
+#define ixDPM_TABLE_395 0x3f628
+#define ixDPM_TABLE_396 0x3f62c
+#define ixDPM_TABLE_397 0x3f630
+#define ixDPM_TABLE_398 0x3f634
+#define ixDPM_TABLE_399 0x3f638
+#define ixDPM_TABLE_400 0x3f63c
+#define ixDPM_TABLE_401 0x3f640
+#define ixDPM_TABLE_402 0x3f644
+#define ixDPM_TABLE_403 0x3f648
+#define ixDPM_TABLE_404 0x3f64c
+#define ixDPM_TABLE_405 0x3f650
+#define ixDPM_TABLE_406 0x3f654
+#define ixDPM_TABLE_407 0x3f658
+#define ixDPM_TABLE_408 0x3f65c
+#define ixDPM_TABLE_409 0x3f660
+#define ixDPM_TABLE_410 0x3f664
+#define ixDPM_TABLE_411 0x3f668
+#define ixDPM_TABLE_412 0x3f66c
+#define ixDPM_TABLE_413 0x3f670
+#define ixDPM_TABLE_414 0x3f674
+#define ixDPM_TABLE_415 0x3f678
+#define ixDPM_TABLE_416 0x3f67c
+#define ixDPM_TABLE_417 0x3f680
+#define ixDPM_TABLE_418 0x3f684
+#define ixDPM_TABLE_419 0x3f688
+#define ixDPM_TABLE_420 0x3f68c
+#define ixDPM_TABLE_421 0x3f690
+#define ixDPM_TABLE_422 0x3f694
+#define ixDPM_TABLE_423 0x3f698
+#define ixDPM_TABLE_424 0x3f69c
+#define ixDPM_TABLE_425 0x3f6a0
+#define ixDPM_TABLE_426 0x3f6a4
+#define ixDPM_TABLE_427 0x3f6a8
+#define ixDPM_TABLE_428 0x3f6ac
+#define ixDPM_TABLE_429 0x3f6b0
+#define ixDPM_TABLE_430 0x3f6b4
+#define ixDPM_TABLE_431 0x3f6b8
+#define ixDPM_TABLE_432 0x3f6bc
+#define ixDPM_TABLE_433 0x3f6c0
+#define ixDPM_TABLE_434 0x3f6c4
+#define ixDPM_TABLE_435 0x3f6c8
+#define ixDPM_TABLE_436 0x3f6cc
+#define ixDPM_TABLE_437 0x3f6d0
+#define ixDPM_TABLE_438 0x3f6d4
+#define ixDPM_TABLE_439 0x3f6d8
+#define ixDPM_TABLE_440 0x3f6dc
+#define ixDPM_TABLE_441 0x3f6e0
+#define ixDPM_TABLE_442 0x3f6e4
+#define ixDPM_TABLE_443 0x3f6e8
+#define ixDPM_TABLE_444 0x3f6ec
+#define ixDPM_TABLE_445 0x3f6f0
+#define ixDPM_TABLE_446 0x3f6f4
+#define ixDPM_TABLE_447 0x3f6f8
+#define ixDPM_TABLE_448 0x3f6fc
+#define ixDPM_TABLE_449 0x3f700
+#define ixDPM_TABLE_450 0x3f704
+#define ixDPM_TABLE_451 0x3f708
+#define ixDPM_TABLE_452 0x3f70c
+#define ixDPM_TABLE_453 0x3f710
+#define ixDPM_TABLE_454 0x3f714
+#define ixDPM_TABLE_455 0x3f718
+#define ixDPM_TABLE_456 0x3f71c
+#define ixDPM_TABLE_457 0x3f720
+#define ixDPM_TABLE_458 0x3f724
+#define ixDPM_TABLE_459 0x3f728
+#define ixDPM_TABLE_460 0x3f72c
+#define ixDPM_TABLE_461 0x3f730
+#define ixDPM_TABLE_462 0x3f734
+#define ixDPM_TABLE_463 0x3f738
+#define ixDPM_TABLE_464 0x3f73c
+#define ixDPM_TABLE_465 0x3f740
+#define ixDPM_TABLE_466 0x3f744
+#define ixDPM_TABLE_467 0x3f748
+#define ixDPM_TABLE_468 0x3f74c
+#define ixDPM_TABLE_469 0x3f750
+#define ixDPM_TABLE_470 0x3f754
+#define ixDPM_TABLE_471 0x3f758
+#define ixDPM_TABLE_472 0x3f75c
+#define ixDPM_TABLE_473 0x3f760
+#define ixDPM_TABLE_474 0x3f764
+#define ixDPM_TABLE_475 0x3f768
+#define ixDPM_TABLE_476 0x3f76c
+#define ixDPM_TABLE_477 0x3f770
+#define ixDPM_TABLE_478 0x3f774
+#define ixDPM_TABLE_479 0x3f778
+#define ixDPM_TABLE_480 0x3f77c
+#define ixDPM_TABLE_481 0x3f780
+#define ixDPM_TABLE_482 0x3f784
+#define ixDPM_TABLE_483 0x3f788
+#define ixDPM_TABLE_484 0x3f78c
+#define ixDPM_TABLE_485 0x3f790
+#define ixDPM_TABLE_486 0x3f794
+#define ixDPM_TABLE_487 0x3f798
+#define ixDPM_TABLE_488 0x3f79c
+#define ixDPM_TABLE_489 0x3f7a0
+#define ixDPM_TABLE_490 0x3f7a4
+#define ixDPM_TABLE_491 0x3f7a8
+#define ixDPM_TABLE_492 0x3f7ac
+#define ixDPM_TABLE_493 0x3f7b0
+#define ixDPM_TABLE_494 0x3f7b4
+#define ixDPM_TABLE_495 0x3f7b8
+#define ixDPM_TABLE_496 0x3f7bc
+#define ixDPM_TABLE_497 0x3f7c0
+#define ixDPM_TABLE_498 0x3f7c4
+#define ixDPM_TABLE_499 0x3f7c8
+#define ixDPM_TABLE_500 0x3f7cc
+#define ixDPM_TABLE_501 0x3f7d0
+#define ixDPM_TABLE_502 0x3f7d4
+#define ixDPM_TABLE_503 0x3f7d8
+#define ixDPM_TABLE_504 0x3f7dc
+#define ixDPM_TABLE_505 0x3f7e0
+#define ixDPM_TABLE_506 0x3f7e4
+#define ixFIRMWARE_FLAGS 0x3f800
+#define ixTDC_STATUS 0x3f808
+#define ixTDC_MV_AVERAGE 0x3f80c
+#define ixTDC_VRM_LIMIT 0x3f810
+#define ixFEATURE_STATUS 0x3f818
+#define ixENTITY_TEMPERATURES_1 0x3f81c
+#define ixMCARB_DRAM_TIMING_TABLE_1 0x3f900
+#define ixMCARB_DRAM_TIMING_TABLE_2 0x3f904
+#define ixMCARB_DRAM_TIMING_TABLE_3 0x3f908
+#define ixMCARB_DRAM_TIMING_TABLE_4 0x3f90c
+#define ixMCARB_DRAM_TIMING_TABLE_5 0x3f910
+#define ixMCARB_DRAM_TIMING_TABLE_6 0x3f914
+#define ixMCARB_DRAM_TIMING_TABLE_7 0x3f918
+#define ixMCARB_DRAM_TIMING_TABLE_8 0x3f91c
+#define ixMCARB_DRAM_TIMING_TABLE_9 0x3f920
+#define ixMCARB_DRAM_TIMING_TABLE_10 0x3f924
+#define ixMCARB_DRAM_TIMING_TABLE_11 0x3f928
+#define ixMCARB_DRAM_TIMING_TABLE_12 0x3f92c
+#define ixMCARB_DRAM_TIMING_TABLE_13 0x3f930
+#define ixMCARB_DRAM_TIMING_TABLE_14 0x3f934
+#define ixMCARB_DRAM_TIMING_TABLE_15 0x3f938
+#define ixMCARB_DRAM_TIMING_TABLE_16 0x3f93c
+#define ixMCARB_DRAM_TIMING_TABLE_17 0x3f940
+#define ixMCARB_DRAM_TIMING_TABLE_18 0x3f944
+#define ixMCARB_DRAM_TIMING_TABLE_19 0x3f948
+#define ixMCARB_DRAM_TIMING_TABLE_20 0x3f94c
+#define ixMCARB_DRAM_TIMING_TABLE_21 0x3f950
+#define ixMCARB_DRAM_TIMING_TABLE_22 0x3f954
+#define ixMCARB_DRAM_TIMING_TABLE_23 0x3f958
+#define ixMCARB_DRAM_TIMING_TABLE_24 0x3f95c
+#define ixMCARB_DRAM_TIMING_TABLE_25 0x3f960
+#define ixMCARB_DRAM_TIMING_TABLE_26 0x3f964
+#define ixMCARB_DRAM_TIMING_TABLE_27 0x3f968
+#define ixMCARB_DRAM_TIMING_TABLE_28 0x3f96c
+#define ixMCARB_DRAM_TIMING_TABLE_29 0x3f970
+#define ixMCARB_DRAM_TIMING_TABLE_30 0x3f974
+#define ixMCARB_DRAM_TIMING_TABLE_31 0x3f978
+#define ixMCARB_DRAM_TIMING_TABLE_32 0x3f97c
+#define ixMCARB_DRAM_TIMING_TABLE_33 0x3f980
+#define ixMCARB_DRAM_TIMING_TABLE_34 0x3f984
+#define ixMCARB_DRAM_TIMING_TABLE_35 0x3f988
+#define ixMCARB_DRAM_TIMING_TABLE_36 0x3f98c
+#define ixMCARB_DRAM_TIMING_TABLE_37 0x3f990
+#define ixMCARB_DRAM_TIMING_TABLE_38 0x3f994
+#define ixMCARB_DRAM_TIMING_TABLE_39 0x3f998
+#define ixMCARB_DRAM_TIMING_TABLE_40 0x3f99c
+#define ixMCARB_DRAM_TIMING_TABLE_41 0x3f9a0
+#define ixMCARB_DRAM_TIMING_TABLE_42 0x3f9a4
+#define ixMCARB_DRAM_TIMING_TABLE_43 0x3f9a8
+#define ixMCARB_DRAM_TIMING_TABLE_44 0x3f9ac
+#define ixMCARB_DRAM_TIMING_TABLE_45 0x3f9b0
+#define ixMCARB_DRAM_TIMING_TABLE_46 0x3f9b4
+#define ixMCARB_DRAM_TIMING_TABLE_47 0x3f9b8
+#define ixMCARB_DRAM_TIMING_TABLE_48 0x3f9bc
+#define ixMCARB_DRAM_TIMING_TABLE_49 0x3f9c0
+#define ixMCARB_DRAM_TIMING_TABLE_50 0x3f9c4
+#define ixMCARB_DRAM_TIMING_TABLE_51 0x3f9c8
+#define ixMCARB_DRAM_TIMING_TABLE_52 0x3f9cc
+#define ixMCARB_DRAM_TIMING_TABLE_53 0x3f9d0
+#define ixMCARB_DRAM_TIMING_TABLE_54 0x3f9d4
+#define ixMCARB_DRAM_TIMING_TABLE_55 0x3f9d8
+#define ixMCARB_DRAM_TIMING_TABLE_56 0x3f9dc
+#define ixMCARB_DRAM_TIMING_TABLE_57 0x3f9e0
+#define ixMCARB_DRAM_TIMING_TABLE_58 0x3f9e4
+#define ixMCARB_DRAM_TIMING_TABLE_59 0x3f9e8
+#define ixMCARB_DRAM_TIMING_TABLE_60 0x3f9ec
+#define ixMCARB_DRAM_TIMING_TABLE_61 0x3f9f0
+#define ixMCARB_DRAM_TIMING_TABLE_62 0x3f9f4
+#define ixMCARB_DRAM_TIMING_TABLE_63 0x3f9f8
+#define ixMCARB_DRAM_TIMING_TABLE_64 0x3f9fc
+#define ixMCARB_DRAM_TIMING_TABLE_65 0x3fa00
+#define ixMCARB_DRAM_TIMING_TABLE_66 0x3fa04
+#define ixMCARB_DRAM_TIMING_TABLE_67 0x3fa08
+#define ixMCARB_DRAM_TIMING_TABLE_68 0x3fa0c
+#define ixMCARB_DRAM_TIMING_TABLE_69 0x3fa10
+#define ixMCARB_DRAM_TIMING_TABLE_70 0x3fa14
+#define ixMCARB_DRAM_TIMING_TABLE_71 0x3fa18
+#define ixMCARB_DRAM_TIMING_TABLE_72 0x3fa1c
+#define ixMCARB_DRAM_TIMING_TABLE_73 0x3fa20
+#define ixMCARB_DRAM_TIMING_TABLE_74 0x3fa24
+#define ixMCARB_DRAM_TIMING_TABLE_75 0x3fa28
+#define ixMCARB_DRAM_TIMING_TABLE_76 0x3fa2c
+#define ixMCARB_DRAM_TIMING_TABLE_77 0x3fa30
+#define ixMCARB_DRAM_TIMING_TABLE_78 0x3fa34
+#define ixMCARB_DRAM_TIMING_TABLE_79 0x3fa38
+#define ixMCARB_DRAM_TIMING_TABLE_80 0x3fa3c
+#define ixMCARB_DRAM_TIMING_TABLE_81 0x3fa40
+#define ixMCARB_DRAM_TIMING_TABLE_82 0x3fa44
+#define ixMCARB_DRAM_TIMING_TABLE_83 0x3fa48
+#define ixMCARB_DRAM_TIMING_TABLE_84 0x3fa4c
+#define ixMCARB_DRAM_TIMING_TABLE_85 0x3fa50
+#define ixMCARB_DRAM_TIMING_TABLE_86 0x3fa54
+#define ixMCARB_DRAM_TIMING_TABLE_87 0x3fa58
+#define ixMCARB_DRAM_TIMING_TABLE_88 0x3fa5c
+#define ixMCARB_DRAM_TIMING_TABLE_89 0x3fa60
+#define ixMCARB_DRAM_TIMING_TABLE_90 0x3fa64
+#define ixMCARB_DRAM_TIMING_TABLE_91 0x3fa68
+#define ixMCARB_DRAM_TIMING_TABLE_92 0x3fa6c
+#define ixMCARB_DRAM_TIMING_TABLE_93 0x3fa70
+#define ixMCARB_DRAM_TIMING_TABLE_94 0x3fa74
+#define ixMCARB_DRAM_TIMING_TABLE_95 0x3fa78
+#define ixMCARB_DRAM_TIMING_TABLE_96 0x3fa7c
+#define ixMCARB_DRAM_TIMING_TABLE_97 0x3fa80
+#define ixMCARB_DRAM_TIMING_TABLE_98 0x3fa84
+#define ixMCARB_DRAM_TIMING_TABLE_99 0x3fa88
+#define ixMCARB_DRAM_TIMING_TABLE_100 0x3fa8c
+#define ixMCARB_DRAM_TIMING_TABLE_101 0x3fa90
+#define ixMCARB_DRAM_TIMING_TABLE_102 0x3fa94
+#define ixMCARB_DRAM_TIMING_TABLE_103 0x3fa98
+#define ixMCARB_DRAM_TIMING_TABLE_104 0x3fa9c
+#define ixMCARB_DRAM_TIMING_TABLE_105 0x3faa0
+#define ixMCARB_DRAM_TIMING_TABLE_106 0x3faa4
+#define ixMCARB_DRAM_TIMING_TABLE_107 0x3faa8
+#define ixMCARB_DRAM_TIMING_TABLE_108 0x3faac
+#define ixMCARB_DRAM_TIMING_TABLE_109 0x3fab0
+#define ixMCARB_DRAM_TIMING_TABLE_110 0x3fab4
+#define ixMCARB_DRAM_TIMING_TABLE_111 0x3fab8
+#define ixMCARB_DRAM_TIMING_TABLE_112 0x3fabc
+#define ixMCARB_DRAM_TIMING_TABLE_113 0x3fac0
+#define ixMCARB_DRAM_TIMING_TABLE_114 0x3fac4
+#define ixMCARB_DRAM_TIMING_TABLE_115 0x3fac8
+#define ixMCARB_DRAM_TIMING_TABLE_116 0x3facc
+#define ixMCARB_DRAM_TIMING_TABLE_117 0x3fad0
+#define ixMCARB_DRAM_TIMING_TABLE_118 0x3fad4
+#define ixMCARB_DRAM_TIMING_TABLE_119 0x3fad8
+#define ixMCARB_DRAM_TIMING_TABLE_120 0x3fadc
+#define ixMCARB_DRAM_TIMING_TABLE_121 0x3fae0
+#define ixMCARB_DRAM_TIMING_TABLE_122 0x3fae4
+#define ixMCARB_DRAM_TIMING_TABLE_123 0x3fae8
+#define ixMCARB_DRAM_TIMING_TABLE_124 0x3faec
+#define ixMCARB_DRAM_TIMING_TABLE_125 0x3faf0
+#define ixMCARB_DRAM_TIMING_TABLE_126 0x3faf4
+#define ixMCARB_DRAM_TIMING_TABLE_127 0x3faf8
+#define ixMCARB_DRAM_TIMING_TABLE_128 0x3fafc
+#define ixMCARB_DRAM_TIMING_TABLE_129 0x3fb00
+#define ixMCARB_DRAM_TIMING_TABLE_130 0x3fb04
+#define ixMCARB_DRAM_TIMING_TABLE_131 0x3fb08
+#define ixMCARB_DRAM_TIMING_TABLE_132 0x3fb0c
+#define ixMCARB_DRAM_TIMING_TABLE_133 0x3fb10
+#define ixMCARB_DRAM_TIMING_TABLE_134 0x3fb14
+#define ixMCARB_DRAM_TIMING_TABLE_135 0x3fb18
+#define ixMCARB_DRAM_TIMING_TABLE_136 0x3fb1c
+#define ixMCARB_DRAM_TIMING_TABLE_137 0x3fb20
+#define ixMCARB_DRAM_TIMING_TABLE_138 0x3fb24
+#define ixMCARB_DRAM_TIMING_TABLE_139 0x3fb28
+#define ixMCARB_DRAM_TIMING_TABLE_140 0x3fb2c
+#define ixMCARB_DRAM_TIMING_TABLE_141 0x3fb30
+#define ixMCARB_DRAM_TIMING_TABLE_142 0x3fb34
+#define ixMCARB_DRAM_TIMING_TABLE_143 0x3fb38
+#define ixMCARB_DRAM_TIMING_TABLE_144 0x3fb3c
+#define ixMC_REGISTERS_TABLE_1 0x3fb40
+#define ixMC_REGISTERS_TABLE_2 0x3fb44
+#define ixMC_REGISTERS_TABLE_3 0x3fb48
+#define ixMC_REGISTERS_TABLE_4 0x3fb4c
+#define ixMC_REGISTERS_TABLE_5 0x3fb50
+#define ixMC_REGISTERS_TABLE_6 0x3fb54
+#define ixMC_REGISTERS_TABLE_7 0x3fb58
+#define ixMC_REGISTERS_TABLE_8 0x3fb5c
+#define ixMC_REGISTERS_TABLE_9 0x3fb60
+#define ixMC_REGISTERS_TABLE_10 0x3fb64
+#define ixMC_REGISTERS_TABLE_11 0x3fb68
+#define ixMC_REGISTERS_TABLE_12 0x3fb6c
+#define ixMC_REGISTERS_TABLE_13 0x3fb70
+#define ixMC_REGISTERS_TABLE_14 0x3fb74
+#define ixMC_REGISTERS_TABLE_15 0x3fb78
+#define ixMC_REGISTERS_TABLE_16 0x3fb7c
+#define ixMC_REGISTERS_TABLE_17 0x3fb80
+#define ixMC_REGISTERS_TABLE_18 0x3fb84
+#define ixMC_REGISTERS_TABLE_19 0x3fb88
+#define ixMC_REGISTERS_TABLE_20 0x3fb8c
+#define ixMC_REGISTERS_TABLE_21 0x3fb90
+#define ixMC_REGISTERS_TABLE_22 0x3fb94
+#define ixMC_REGISTERS_TABLE_23 0x3fb98
+#define ixMC_REGISTERS_TABLE_24 0x3fb9c
+#define ixMC_REGISTERS_TABLE_25 0x3fba0
+#define ixMC_REGISTERS_TABLE_26 0x3fba4
+#define ixMC_REGISTERS_TABLE_27 0x3fba8
+#define ixMC_REGISTERS_TABLE_28 0x3fbac
+#define ixMC_REGISTERS_TABLE_29 0x3fbb0
+#define ixMC_REGISTERS_TABLE_30 0x3fbb4
+#define ixMC_REGISTERS_TABLE_31 0x3fbb8
+#define ixMC_REGISTERS_TABLE_32 0x3fbbc
+#define ixMC_REGISTERS_TABLE_33 0x3fbc0
+#define ixMC_REGISTERS_TABLE_34 0x3fbc4
+#define ixMC_REGISTERS_TABLE_35 0x3fbc8
+#define ixMC_REGISTERS_TABLE_36 0x3fbcc
+#define ixMC_REGISTERS_TABLE_37 0x3fbd0
+#define ixMC_REGISTERS_TABLE_38 0x3fbd4
+#define ixMC_REGISTERS_TABLE_39 0x3fbd8
+#define ixMC_REGISTERS_TABLE_40 0x3fbdc
+#define ixMC_REGISTERS_TABLE_41 0x3fbe0
+#define ixMC_REGISTERS_TABLE_42 0x3fbe4
+#define ixMC_REGISTERS_TABLE_43 0x3fbe8
+#define ixMC_REGISTERS_TABLE_44 0x3fbec
+#define ixMC_REGISTERS_TABLE_45 0x3fbf0
+#define ixMC_REGISTERS_TABLE_46 0x3fbf4
+#define ixMC_REGISTERS_TABLE_47 0x3fbf8
+#define ixMC_REGISTERS_TABLE_48 0x3fbfc
+#define ixMC_REGISTERS_TABLE_49 0x3fc00
+#define ixMC_REGISTERS_TABLE_50 0x3fc04
+#define ixMC_REGISTERS_TABLE_51 0x3fc08
+#define ixMC_REGISTERS_TABLE_52 0x3fc0c
+#define ixMC_REGISTERS_TABLE_53 0x3fc10
+#define ixMC_REGISTERS_TABLE_54 0x3fc14
+#define ixMC_REGISTERS_TABLE_55 0x3fc18
+#define ixMC_REGISTERS_TABLE_56 0x3fc1c
+#define ixMC_REGISTERS_TABLE_57 0x3fc20
+#define ixMC_REGISTERS_TABLE_58 0x3fc24
+#define ixMC_REGISTERS_TABLE_59 0x3fc28
+#define ixMC_REGISTERS_TABLE_60 0x3fc2c
+#define ixMC_REGISTERS_TABLE_61 0x3fc30
+#define ixMC_REGISTERS_TABLE_62 0x3fc34
+#define ixMC_REGISTERS_TABLE_63 0x3fc38
+#define ixMC_REGISTERS_TABLE_64 0x3fc3c
+#define ixMC_REGISTERS_TABLE_65 0x3fc40
+#define ixMC_REGISTERS_TABLE_66 0x3fc44
+#define ixMC_REGISTERS_TABLE_67 0x3fc48
+#define ixMC_REGISTERS_TABLE_68 0x3fc4c
+#define ixMC_REGISTERS_TABLE_69 0x3fc50
+#define ixMC_REGISTERS_TABLE_70 0x3fc54
+#define ixMC_REGISTERS_TABLE_71 0x3fc58
+#define ixMC_REGISTERS_TABLE_72 0x3fc5c
+#define ixMC_REGISTERS_TABLE_73 0x3fc60
+#define ixMC_REGISTERS_TABLE_74 0x3fc64
+#define ixMC_REGISTERS_TABLE_75 0x3fc68
+#define ixMC_REGISTERS_TABLE_76 0x3fc6c
+#define ixMC_REGISTERS_TABLE_77 0x3fc70
+#define ixMC_REGISTERS_TABLE_78 0x3fc74
+#define ixMC_REGISTERS_TABLE_79 0x3fc78
+#define ixMC_REGISTERS_TABLE_80 0x3fc7c
+#define ixMC_REGISTERS_TABLE_81 0x3fc80
+#define ixMC_REGISTERS_TABLE_82 0x3fc84
+#define ixMC_REGISTERS_TABLE_83 0x3fc88
+#define ixMC_REGISTERS_TABLE_84 0x3fc8c
+#define ixMC_REGISTERS_TABLE_85 0x3fc90
+#define ixMC_REGISTERS_TABLE_86 0x3fc94
+#define ixMC_REGISTERS_TABLE_87 0x3fc98
+#define ixMC_REGISTERS_TABLE_88 0x3fc9c
+#define ixMC_REGISTERS_TABLE_89 0x3fca0
+#define ixMC_REGISTERS_TABLE_90 0x3fca4
+#define ixMC_REGISTERS_TABLE_91 0x3fca8
+#define ixMC_REGISTERS_TABLE_92 0x3fcac
+#define ixMC_REGISTERS_TABLE_93 0x3fcb0
+#define ixMC_REGISTERS_TABLE_94 0x3fcb4
+#define ixMC_REGISTERS_TABLE_95 0x3fcb8
+#define ixMC_REGISTERS_TABLE_96 0x3fcbc
+#define ixMC_REGISTERS_TABLE_97 0x3fcc0
+#define ixMC_REGISTERS_TABLE_98 0x3fcc4
+#define ixMC_REGISTERS_TABLE_99 0x3fcc8
+#define ixMC_REGISTERS_TABLE_100 0x3fccc
+#define ixMC_REGISTERS_TABLE_101 0x3fcd0
+#define ixMC_REGISTERS_TABLE_102 0x3fcd4
+#define ixMC_REGISTERS_TABLE_103 0x3fcd8
+#define ixMC_REGISTERS_TABLE_104 0x3fcdc
+#define ixMC_REGISTERS_TABLE_105 0x3fce0
+#define ixMC_REGISTERS_TABLE_106 0x3fce4
+#define ixMC_REGISTERS_TABLE_107 0x3fce8
+#define ixMC_REGISTERS_TABLE_108 0x3fcec
+#define ixMC_REGISTERS_TABLE_109 0x3fcf0
+#define ixMC_REGISTERS_TABLE_110 0x3fcf4
+#define ixMC_REGISTERS_TABLE_111 0x3fcf8
+#define ixMC_REGISTERS_TABLE_112 0x3fcfc
+#define ixMC_REGISTERS_TABLE_113 0x3fd00
+#define ixFAN_TABLE_1 0x3fd04
+#define ixFAN_TABLE_2 0x3fd08
+#define ixFAN_TABLE_3 0x3fd0c
+#define ixFAN_TABLE_4 0x3fd10
+#define ixFAN_TABLE_5 0x3fd14
+#define ixFAN_TABLE_6 0x3fd18
+#define ixFAN_TABLE_7 0x3fd1c
+#define ixFAN_TABLE_8 0x3fd20
+#define ixFAN_TABLE_9 0x3fd24
+#define ixSOFT_REGISTERS_TABLE_1 0x3fd28
+#define ixSOFT_REGISTERS_TABLE_2 0x3fd2c
+#define ixSOFT_REGISTERS_TABLE_3 0x3fd30
+#define ixSOFT_REGISTERS_TABLE_4 0x3fd34
+#define ixSOFT_REGISTERS_TABLE_5 0x3fd38
+#define ixSOFT_REGISTERS_TABLE_6 0x3fd3c
+#define ixSOFT_REGISTERS_TABLE_7 0x3fd40
+#define ixSOFT_REGISTERS_TABLE_8 0x3fd44
+#define ixSOFT_REGISTERS_TABLE_9 0x3fd48
+#define ixSOFT_REGISTERS_TABLE_10 0x3fd4c
+#define ixSOFT_REGISTERS_TABLE_11 0x3fd50
+#define ixSOFT_REGISTERS_TABLE_12 0x3fd54
+#define ixSOFT_REGISTERS_TABLE_13 0x3fd58
+#define ixSOFT_REGISTERS_TABLE_14 0x3fd5c
+#define ixSOFT_REGISTERS_TABLE_15 0x3fd60
+#define ixSOFT_REGISTERS_TABLE_16 0x3fd64
+#define ixSOFT_REGISTERS_TABLE_17 0x3fd68
+#define ixSOFT_REGISTERS_TABLE_18 0x3fd6c
+#define ixSOFT_REGISTERS_TABLE_19 0x3fd70
+#define ixSOFT_REGISTERS_TABLE_20 0x3fd74
+#define ixSOFT_REGISTERS_TABLE_21 0x3fd78
+#define ixSOFT_REGISTERS_TABLE_22 0x3fd7c
+#define ixSOFT_REGISTERS_TABLE_23 0x3fd80
+#define ixSOFT_REGISTERS_TABLE_24 0x3fd84
+#define ixSOFT_REGISTERS_TABLE_25 0x3fd88
+#define ixSOFT_REGISTERS_TABLE_26 0x3fd8c
+#define ixSOFT_REGISTERS_TABLE_27 0x3fd90
+#define ixSOFT_REGISTERS_TABLE_28 0x3fd94
+#define ixSOFT_REGISTERS_TABLE_29 0x3fd98
+#define ixSOFT_REGISTERS_TABLE_30 0x3fd9c
+#define ixPM_FUSES_1 0x3fda0
+#define ixPM_FUSES_2 0x3fda4
+#define ixPM_FUSES_3 0x3fda8
+#define ixPM_FUSES_4 0x3fdac
+#define ixPM_FUSES_5 0x3fdb0
+#define ixPM_FUSES_6 0x3fdb4
+#define ixPM_FUSES_7 0x3fdb8
+#define ixPM_FUSES_8 0x3fdbc
+#define ixPM_FUSES_9 0x3fdc0
+#define ixPM_FUSES_10 0x3fdc4
+#define ixPM_FUSES_11 0x3fdc8
+#define ixPM_FUSES_12 0x3fdcc
+#define ixPM_FUSES_13 0x3fdd0
+#define ixPM_FUSES_14 0x3fdd4
+#define ixPM_FUSES_15 0x3fdd8
+#define ixPM_FUSES_16 0x3fddc
+#define ixPM_FUSES_17 0x3fde0
+#define ixPM_FUSES_18 0x3fde4
+#define ixPM_FUSES_19 0x3fde8
+#define ixSMU_PM_STATUS_0 0x3fe00
+#define ixSMU_PM_STATUS_1 0x3fe04
+#define ixSMU_PM_STATUS_2 0x3fe08
+#define ixSMU_PM_STATUS_3 0x3fe0c
+#define ixSMU_PM_STATUS_4 0x3fe10
+#define ixSMU_PM_STATUS_5 0x3fe14
+#define ixSMU_PM_STATUS_6 0x3fe18
+#define ixSMU_PM_STATUS_7 0x3fe1c
+#define ixSMU_PM_STATUS_8 0x3fe20
+#define ixSMU_PM_STATUS_9 0x3fe24
+#define ixSMU_PM_STATUS_10 0x3fe28
+#define ixSMU_PM_STATUS_11 0x3fe2c
+#define ixSMU_PM_STATUS_12 0x3fe30
+#define ixSMU_PM_STATUS_13 0x3fe34
+#define ixSMU_PM_STATUS_14 0x3fe38
+#define ixSMU_PM_STATUS_15 0x3fe3c
+#define ixSMU_PM_STATUS_16 0x3fe40
+#define ixSMU_PM_STATUS_17 0x3fe44
+#define ixSMU_PM_STATUS_18 0x3fe48
+#define ixSMU_PM_STATUS_19 0x3fe4c
+#define ixSMU_PM_STATUS_20 0x3fe50
+#define ixSMU_PM_STATUS_21 0x3fe54
+#define ixSMU_PM_STATUS_22 0x3fe58
+#define ixSMU_PM_STATUS_23 0x3fe5c
+#define ixSMU_PM_STATUS_24 0x3fe60
+#define ixSMU_PM_STATUS_25 0x3fe64
+#define ixSMU_PM_STATUS_26 0x3fe68
+#define ixSMU_PM_STATUS_27 0x3fe6c
+#define ixSMU_PM_STATUS_28 0x3fe70
+#define ixSMU_PM_STATUS_29 0x3fe74
+#define ixSMU_PM_STATUS_30 0x3fe78
+#define ixSMU_PM_STATUS_31 0x3fe7c
+#define ixSMU_PM_STATUS_32 0x3fe80
+#define ixSMU_PM_STATUS_33 0x3fe84
+#define ixSMU_PM_STATUS_34 0x3fe88
+#define ixSMU_PM_STATUS_35 0x3fe8c
+#define ixSMU_PM_STATUS_36 0x3fe90
+#define ixSMU_PM_STATUS_37 0x3fe94
+#define ixSMU_PM_STATUS_38 0x3fe98
+#define ixSMU_PM_STATUS_39 0x3fe9c
+#define ixSMU_PM_STATUS_40 0x3fea0
+#define ixSMU_PM_STATUS_41 0x3fea4
+#define ixSMU_PM_STATUS_42 0x3fea8
+#define ixSMU_PM_STATUS_43 0x3feac
+#define ixSMU_PM_STATUS_44 0x3feb0
+#define ixSMU_PM_STATUS_45 0x3feb4
+#define ixSMU_PM_STATUS_46 0x3feb8
+#define ixSMU_PM_STATUS_47 0x3febc
+#define ixSMU_PM_STATUS_48 0x3fec0
+#define ixSMU_PM_STATUS_49 0x3fec4
+#define ixSMU_PM_STATUS_50 0x3fec8
+#define ixSMU_PM_STATUS_51 0x3fecc
+#define ixSMU_PM_STATUS_52 0x3fed0
+#define ixSMU_PM_STATUS_53 0x3fed4
+#define ixSMU_PM_STATUS_54 0x3fed8
+#define ixSMU_PM_STATUS_55 0x3fedc
+#define ixSMU_PM_STATUS_56 0x3fee0
+#define ixSMU_PM_STATUS_57 0x3fee4
+#define ixSMU_PM_STATUS_58 0x3fee8
+#define ixSMU_PM_STATUS_59 0x3feec
+#define ixSMU_PM_STATUS_60 0x3fef0
+#define ixSMU_PM_STATUS_61 0x3fef4
+#define ixSMU_PM_STATUS_62 0x3fef8
+#define ixSMU_PM_STATUS_63 0x3fefc
+#define ixSMU_PM_STATUS_64 0x3ff00
+#define ixSMU_PM_STATUS_65 0x3ff04
+#define ixSMU_PM_STATUS_66 0x3ff08
+#define ixSMU_PM_STATUS_67 0x3ff0c
+#define ixSMU_PM_STATUS_68 0x3ff10
+#define ixSMU_PM_STATUS_69 0x3ff14
+#define ixSMU_PM_STATUS_70 0x3ff18
+#define ixSMU_PM_STATUS_71 0x3ff1c
+#define ixSMU_PM_STATUS_72 0x3ff20
+#define ixSMU_PM_STATUS_73 0x3ff24
+#define ixSMU_PM_STATUS_74 0x3ff28
+#define ixSMU_PM_STATUS_75 0x3ff2c
+#define ixSMU_PM_STATUS_76 0x3ff30
+#define ixSMU_PM_STATUS_77 0x3ff34
+#define ixSMU_PM_STATUS_78 0x3ff38
+#define ixSMU_PM_STATUS_79 0x3ff3c
+#define ixSMU_PM_STATUS_80 0x3ff40
+#define ixSMU_PM_STATUS_81 0x3ff44
+#define ixSMU_PM_STATUS_82 0x3ff48
+#define ixSMU_PM_STATUS_83 0x3ff4c
+#define ixSMU_PM_STATUS_84 0x3ff50
+#define ixSMU_PM_STATUS_85 0x3ff54
+#define ixSMU_PM_STATUS_86 0x3ff58
+#define ixSMU_PM_STATUS_87 0x3ff5c
+#define ixSMU_PM_STATUS_88 0x3ff60
+#define ixSMU_PM_STATUS_89 0x3ff64
+#define ixSMU_PM_STATUS_90 0x3ff68
+#define ixSMU_PM_STATUS_91 0x3ff6c
+#define ixSMU_PM_STATUS_92 0x3ff70
+#define ixSMU_PM_STATUS_93 0x3ff74
+#define ixSMU_PM_STATUS_94 0x3ff78
+#define ixSMU_PM_STATUS_95 0x3ff7c
+#define ixSMU_PM_STATUS_96 0x3ff80
+#define ixSMU_PM_STATUS_97 0x3ff84
+#define ixSMU_PM_STATUS_98 0x3ff88
+#define ixSMU_PM_STATUS_99 0x3ff8c
+#define ixSMU_PM_STATUS_100 0x3ff90
+#define ixSMU_PM_STATUS_101 0x3ff94
+#define ixSMU_PM_STATUS_102 0x3ff98
+#define ixSMU_PM_STATUS_103 0x3ff9c
+#define ixSMU_PM_STATUS_104 0x3ffa0
+#define ixSMU_PM_STATUS_105 0x3ffa4
+#define ixSMU_PM_STATUS_106 0x3ffa8
+#define ixSMU_PM_STATUS_107 0x3ffac
+#define ixSMU_PM_STATUS_108 0x3ffb0
+#define ixSMU_PM_STATUS_109 0x3ffb4
+#define ixSMU_PM_STATUS_110 0x3ffb8
+#define ixSMU_PM_STATUS_111 0x3ffbc
+#define ixSMU_PM_STATUS_112 0x3ffc0
+#define ixSMU_PM_STATUS_113 0x3ffc4
+#define ixSMU_PM_STATUS_114 0x3ffc8
+#define ixSMU_PM_STATUS_115 0x3ffcc
+#define ixSMU_PM_STATUS_116 0x3ffd0
+#define ixSMU_PM_STATUS_117 0x3ffd4
+#define ixSMU_PM_STATUS_118 0x3ffd8
+#define ixSMU_PM_STATUS_119 0x3ffdc
+#define ixSMU_PM_STATUS_120 0x3ffe0
+#define ixSMU_PM_STATUS_121 0x3ffe4
+#define ixSMU_PM_STATUS_122 0x3ffe8
+#define ixSMU_PM_STATUS_123 0x3ffec
+#define ixSMU_PM_STATUS_124 0x3fff0
+#define ixSMU_PM_STATUS_125 0x3fff4
+#define ixSMU_PM_STATUS_126 0x3fff8
+#define ixSMU_PM_STATUS_127 0x3fffc
+#define ixCG_THERMAL_INT_ENA 0xc2100024
+#define ixCG_THERMAL_INT_CTRL 0xc2100028
+#define ixCG_THERMAL_INT_STATUS 0xc210002c
+#define ixCG_THERMAL_CTRL 0xc0300004
+#define ixCG_THERMAL_STATUS 0xc0300008
+#define ixCG_THERMAL_INT 0xc030000c
+#define ixCG_MULT_THERMAL_CTRL 0xc0300010
+#define ixCG_MULT_THERMAL_STATUS 0xc0300014
+#define ixCG_FDO_CTRL0 0xc0300064
+#define ixCG_FDO_CTRL1 0xc0300068
+#define ixCG_FDO_CTRL2 0xc030006c
+#define ixCG_TACH_CTRL 0xc0300070
+#define ixCG_TACH_STATUS 0xc0300074
+#define ixCC_THM_STRAPS0 0xc0300080
+#define ixTHM_TMON0_RDIL0_DATA 0xc0300100
+#define ixTHM_TMON0_RDIL1_DATA 0xc0300104
+#define ixTHM_TMON0_RDIL2_DATA 0xc0300108
+#define ixTHM_TMON0_RDIL3_DATA 0xc030010c
+#define ixTHM_TMON0_RDIL4_DATA 0xc0300110
+#define ixTHM_TMON0_RDIL5_DATA 0xc0300114
+#define ixTHM_TMON0_RDIL6_DATA 0xc0300118
+#define ixTHM_TMON0_RDIL7_DATA 0xc030011c
+#define ixTHM_TMON0_RDIL8_DATA 0xc0300120
+#define ixTHM_TMON0_RDIL9_DATA 0xc0300124
+#define ixTHM_TMON0_RDIL10_DATA 0xc0300128
+#define ixTHM_TMON0_RDIL11_DATA 0xc030012c
+#define ixTHM_TMON0_RDIL12_DATA 0xc0300130
+#define ixTHM_TMON0_RDIL13_DATA 0xc0300134
+#define ixTHM_TMON0_RDIL14_DATA 0xc0300138
+#define ixTHM_TMON0_RDIL15_DATA 0xc030013c
+#define ixTHM_TMON0_RDIR0_DATA 0xc0300140
+#define ixTHM_TMON0_RDIR1_DATA 0xc0300144
+#define ixTHM_TMON0_RDIR2_DATA 0xc0300148
+#define ixTHM_TMON0_RDIR3_DATA 0xc030014c
+#define ixTHM_TMON0_RDIR4_DATA 0xc0300150
+#define ixTHM_TMON0_RDIR5_DATA 0xc0300154
+#define ixTHM_TMON0_RDIR6_DATA 0xc0300158
+#define ixTHM_TMON0_RDIR7_DATA 0xc030015c
+#define ixTHM_TMON0_RDIR8_DATA 0xc0300160
+#define ixTHM_TMON0_RDIR9_DATA 0xc0300164
+#define ixTHM_TMON0_RDIR10_DATA 0xc0300168
+#define ixTHM_TMON0_RDIR11_DATA 0xc030016c
+#define ixTHM_TMON0_RDIR12_DATA 0xc0300170
+#define ixTHM_TMON0_RDIR13_DATA 0xc0300174
+#define ixTHM_TMON0_RDIR14_DATA 0xc0300178
+#define ixTHM_TMON0_RDIR15_DATA 0xc030017c
+#define ixTHM_TMON1_RDIL0_DATA 0xc0300180
+#define ixTHM_TMON1_RDIL1_DATA 0xc0300184
+#define ixTHM_TMON1_RDIL2_DATA 0xc0300188
+#define ixTHM_TMON1_RDIL3_DATA 0xc030018c
+#define ixTHM_TMON1_RDIL4_DATA 0xc0300190
+#define ixTHM_TMON1_RDIL5_DATA 0xc0300194
+#define ixTHM_TMON1_RDIL6_DATA 0xc0300198
+#define ixTHM_TMON1_RDIL7_DATA 0xc030019c
+#define ixTHM_TMON1_RDIL8_DATA 0xc03001a0
+#define ixTHM_TMON1_RDIL9_DATA 0xc03001a4
+#define ixTHM_TMON1_RDIL10_DATA 0xc03001a8
+#define ixTHM_TMON1_RDIL11_DATA 0xc03001ac
+#define ixTHM_TMON1_RDIL12_DATA 0xc03001b0
+#define ixTHM_TMON1_RDIL13_DATA 0xc03001b4
+#define ixTHM_TMON1_RDIL14_DATA 0xc03001b8
+#define ixTHM_TMON1_RDIL15_DATA 0xc03001bc
+#define ixTHM_TMON1_RDIR0_DATA 0xc03001c0
+#define ixTHM_TMON1_RDIR1_DATA 0xc03001c4
+#define ixTHM_TMON1_RDIR2_DATA 0xc03001c8
+#define ixTHM_TMON1_RDIR3_DATA 0xc03001cc
+#define ixTHM_TMON1_RDIR4_DATA 0xc03001d0
+#define ixTHM_TMON1_RDIR5_DATA 0xc03001d4
+#define ixTHM_TMON1_RDIR6_DATA 0xc03001d8
+#define ixTHM_TMON1_RDIR7_DATA 0xc03001dc
+#define ixTHM_TMON1_RDIR8_DATA 0xc03001e0
+#define ixTHM_TMON1_RDIR9_DATA 0xc03001e4
+#define ixTHM_TMON1_RDIR10_DATA 0xc03001e8
+#define ixTHM_TMON1_RDIR11_DATA 0xc03001ec
+#define ixTHM_TMON1_RDIR12_DATA 0xc03001f0
+#define ixTHM_TMON1_RDIR13_DATA 0xc03001f4
+#define ixTHM_TMON1_RDIR14_DATA 0xc03001f8
+#define ixTHM_TMON1_RDIR15_DATA 0xc03001fc
+#define ixTHM_TMON0_INT_DATA 0xc0300300
+#define ixTHM_TMON1_INT_DATA 0xc0300304
+#define ixTHM_TMON0_DEBUG 0xc0300310
+#define ixTHM_TMON1_DEBUG 0xc0300314
+#define ixGENERAL_PWRMGT 0xc0200000
+#define ixCNB_PWRMGT_CNTL 0xc0200004
+#define ixSCLK_PWRMGT_CNTL 0xc0200008
+#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014
+#define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8
+#define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac
+#define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0
+#define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4
+#define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8
+#define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc
+#define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0
+#define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4
+#define ixPLL_TEST_CNTL 0xc020003c
+#define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044
+#define ixCG_DISPLAY_GAP_CNTL 0xc0200060
+#define ixCG_DISPLAY_GAP_CNTL2 0xc0200230
+#define ixCG_ACPI_CNTL 0xc0200064
+#define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080
+#define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084
+#define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c
+#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088
+#define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c
+#define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310
+#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0
+#define ixCG_ULV_PARAMETER 0xc020015c
+#define ixSCLK_MIN_DIV 0xc0200308
+#define ixLCAC_SX0_CNTL 0xc0400d00
+#define ixLCAC_SX0_OVR_SEL 0xc0400d04
+#define ixLCAC_SX0_OVR_VAL 0xc0400d08
+#define ixLCAC_MC0_CNTL 0xc0400d30
+#define ixLCAC_MC0_OVR_SEL 0xc0400d34
+#define ixLCAC_MC0_OVR_VAL 0xc0400d38
+#define ixLCAC_MC1_CNTL 0xc0400d3c
+#define ixLCAC_MC1_OVR_SEL 0xc0400d40
+#define ixLCAC_MC1_OVR_VAL 0xc0400d44
+#define ixLCAC_MC2_CNTL 0xc0400d48
+#define ixLCAC_MC2_OVR_SEL 0xc0400d4c
+#define ixLCAC_MC2_OVR_VAL 0xc0400d50
+#define ixLCAC_MC3_CNTL 0xc0400d54
+#define ixLCAC_MC3_OVR_SEL 0xc0400d58
+#define ixLCAC_MC3_OVR_VAL 0xc0400d5c
+#define ixLCAC_CPL_CNTL 0xc0400d80
+#define ixLCAC_CPL_OVR_SEL 0xc0400d84
+#define ixLCAC_CPL_OVR_VAL 0xc0400d88
+#define mmROM_SMC_IND_INDEX 0x80
+#define mmROM0_ROM_SMC_IND_INDEX 0x80
+#define mmROM1_ROM_SMC_IND_INDEX 0x82
+#define mmROM2_ROM_SMC_IND_INDEX 0x84
+#define mmROM3_ROM_SMC_IND_INDEX 0x86
+#define mmROM_SMC_IND_DATA 0x81
+#define mmROM0_ROM_SMC_IND_DATA 0x81
+#define mmROM1_ROM_SMC_IND_DATA 0x83
+#define mmROM2_ROM_SMC_IND_DATA 0x85
+#define mmROM3_ROM_SMC_IND_DATA 0x87
+#define ixROM_CNTL 0xc0600000
+#define ixPAGE_MIRROR_CNTL 0xc0600004
+#define ixROM_STATUS 0xc0600008
+#define ixCGTT_ROM_CLK_CTRL0 0xc060000c
+#define ixROM_INDEX 0xc0600010
+#define ixROM_DATA 0xc0600014
+#define ixROM_START 0xc0600018
+#define ixROM_SW_CNTL 0xc060001c
+#define ixROM_SW_STATUS 0xc0600020
+#define ixROM_SW_COMMAND 0xc0600024
+#define ixROM_SW_DATA_1 0xc0600028
+#define ixROM_SW_DATA_2 0xc060002c
+#define ixROM_SW_DATA_3 0xc0600030
+#define ixROM_SW_DATA_4 0xc0600034
+#define ixROM_SW_DATA_5 0xc0600038
+#define ixROM_SW_DATA_6 0xc060003c
+#define ixROM_SW_DATA_7 0xc0600040
+#define ixROM_SW_DATA_8 0xc0600044
+#define ixROM_SW_DATA_9 0xc0600048
+#define ixROM_SW_DATA_10 0xc060004c
+#define ixROM_SW_DATA_11 0xc0600050
+#define ixROM_SW_DATA_12 0xc0600054
+#define ixROM_SW_DATA_13 0xc0600058
+#define ixROM_SW_DATA_14 0xc060005c
+#define ixROM_SW_DATA_15 0xc0600060
+#define ixROM_SW_DATA_16 0xc0600064
+#define ixROM_SW_DATA_17 0xc0600068
+#define ixROM_SW_DATA_18 0xc060006c
+#define ixROM_SW_DATA_19 0xc0600070
+#define ixROM_SW_DATA_20 0xc0600074
+#define ixROM_SW_DATA_21 0xc0600078
+#define ixROM_SW_DATA_22 0xc060007c
+#define ixROM_SW_DATA_23 0xc0600080
+#define ixROM_SW_DATA_24 0xc0600084
+#define ixROM_SW_DATA_25 0xc0600088
+#define ixROM_SW_DATA_26 0xc060008c
+#define ixROM_SW_DATA_27 0xc0600090
+#define ixROM_SW_DATA_28 0xc0600094
+#define ixROM_SW_DATA_29 0xc0600098
+#define ixROM_SW_DATA_30 0xc060009c
+#define ixROM_SW_DATA_31 0xc06000a0
+#define ixROM_SW_DATA_32 0xc06000a4
+#define ixROM_SW_DATA_33 0xc06000a8
+#define ixROM_SW_DATA_34 0xc06000ac
+#define ixROM_SW_DATA_35 0xc06000b0
+#define ixROM_SW_DATA_36 0xc06000b4
+#define ixROM_SW_DATA_37 0xc06000b8
+#define ixROM_SW_DATA_38 0xc06000bc
+#define ixROM_SW_DATA_39 0xc06000c0
+#define ixROM_SW_DATA_40 0xc06000c4
+#define ixROM_SW_DATA_41 0xc06000c8
+#define ixROM_SW_DATA_42 0xc06000cc
+#define ixROM_SW_DATA_43 0xc06000d0
+#define ixROM_SW_DATA_44 0xc06000d4
+#define ixROM_SW_DATA_45 0xc06000d8
+#define ixROM_SW_DATA_46 0xc06000dc
+#define ixROM_SW_DATA_47 0xc06000e0
+#define ixROM_SW_DATA_48 0xc06000e4
+#define ixROM_SW_DATA_49 0xc06000e8
+#define ixROM_SW_DATA_50 0xc06000ec
+#define ixROM_SW_DATA_51 0xc06000f0
+#define ixROM_SW_DATA_52 0xc06000f4
+#define ixROM_SW_DATA_53 0xc06000f8
+#define ixROM_SW_DATA_54 0xc06000fc
+#define ixROM_SW_DATA_55 0xc0600100
+#define ixROM_SW_DATA_56 0xc0600104
+#define ixROM_SW_DATA_57 0xc0600108
+#define ixROM_SW_DATA_58 0xc060010c
+#define ixROM_SW_DATA_59 0xc0600110
+#define ixROM_SW_DATA_60 0xc0600114
+#define ixROM_SW_DATA_61 0xc0600118
+#define ixROM_SW_DATA_62 0xc060011c
+#define ixROM_SW_DATA_63 0xc0600120
+#define ixROM_SW_DATA_64 0xc0600124
+
+#endif /* SMU_7_1_0_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_enum.h
new file mode 100644
index 000000000000..61face1d0d8d
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_enum.h
@@ -0,0 +1,1191 @@
+/*
+ * SMU_7_1_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef SMU_7_1_0_ENUM_H
+#define SMU_7_1_0_ENUM_H
+
+#define CG_SRBM_START_ADDR 0x600
+#define CG_SRBM_END_ADDR 0x8ff
+#define RCU_CCF_DWORDS0 0x28
+#define RCU_CCF_BITS0 0x500
+#define RCU_CCF_DWORDS1 0x7f
+#define RCU_CCF_BITS1 0x1000
+#define RCU_SAM_BYTES 0x40
+#define RCU_SAM_RTL_BYTES 0x40
+#define KEYS_CHAIN_ADR 0x0
+#define SAMU_KEY_SADR 0xa0
+#define SAMU_KEY_EADR 0xdf
+#define RCU_SMU_BYTES 0x11
+#define RCU_SMU_RTL_BYTES 0x11
+#define SMC_MSG_TEST 0x1
+#define SMC_MSG_PHY_LN_OFF 0x2
+#define SMC_MSG_PHY_LN_ON 0x3
+#define SMC_MSG_DDI_PHY_OFF 0x4
+#define SMC_MSG_DDI_PHY_ON 0x5
+#define SMC_MSG_CASCADE_PLL_OFF 0x6
+#define SMC_MSG_CASCADE_PLL_ON 0x7
+#define SMC_MSG_PWR_OFF_x16 0x8
+#define SMC_MSG_CONFIG_LCLK_DPM 0x9
+#define SMC_MSG_FLUSH_DATA_CACHE 0xa
+#define SMC_MSG_FLUSH_INSTRUCTION_CACHE 0xb
+#define SMC_MSG_CONFIG_VPC_ACCUMULATOR 0xc
+#define SMC_MSG_CONFIG_BAPM 0xd
+#define SMC_MSG_CONFIG_TDC_LIMIT 0xe
+#define SMC_MSG_CONFIG_LPMx 0xf
+#define SMC_MSG_CONFIG_HTC_LIMIT 0x10
+#define SMC_MSG_CONFIG_THERMAL_CNTL 0x11
+#define SMC_MSG_CONFIG_VOLTAGE_CNTL 0x12
+#define SMC_MSG_CONFIG_TDP_CNTL 0x13
+#define SMC_MSG_EN_PM_CNTL 0x14
+#define SMC_MSG_DIS_PM_CNTL 0x15
+#define SMC_MSG_CONFIG_NBDPM 0x16
+#define SMC_MSG_CONFIG_LOADLINE 0x17
+#define SMC_MSG_ADJUST_LOADLINE 0x18
+#define SMC_MSG_RESET 0x20
+#define SMC_MSG_VOLTAGE 0x25
+#define SMC_VERSION_MAJOR 0x7
+#define SMC_VERSION_MINOR 0x0
+#define SMC_HEADER_SIZE 0x40
+#define ROM_SIGNATURE 0xaa55
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0x0,
+ ENDIAN_8IN16 = 0x1,
+ ENDIAN_8IN32 = 0x2,
+ ENDIAN_8IN64 = 0x3,
+} SurfaceEndian;
+typedef enum ArrayMode {
+ ARRAY_LINEAR_GENERAL = 0x0,
+ ARRAY_LINEAR_ALIGNED = 0x1,
+ ARRAY_1D_TILED_THIN1 = 0x2,
+ ARRAY_1D_TILED_THICK = 0x3,
+ ARRAY_2D_TILED_THIN1 = 0x4,
+ ARRAY_PRT_TILED_THIN1 = 0x5,
+ ARRAY_PRT_2D_TILED_THIN1 = 0x6,
+ ARRAY_2D_TILED_THICK = 0x7,
+ ARRAY_2D_TILED_XTHICK = 0x8,
+ ARRAY_PRT_TILED_THICK = 0x9,
+ ARRAY_PRT_2D_TILED_THICK = 0xa,
+ ARRAY_PRT_3D_TILED_THIN1 = 0xb,
+ ARRAY_3D_TILED_THIN1 = 0xc,
+ ARRAY_3D_TILED_THICK = 0xd,
+ ARRAY_3D_TILED_XTHICK = 0xe,
+ ARRAY_PRT_3D_TILED_THICK = 0xf,
+} ArrayMode;
+typedef enum PipeTiling {
+ CONFIG_1_PIPE = 0x0,
+ CONFIG_2_PIPE = 0x1,
+ CONFIG_4_PIPE = 0x2,
+ CONFIG_8_PIPE = 0x3,
+} PipeTiling;
+typedef enum BankTiling {
+ CONFIG_4_BANK = 0x0,
+ CONFIG_8_BANK = 0x1,
+} BankTiling;
+typedef enum GroupInterleave {
+ CONFIG_256B_GROUP = 0x0,
+ CONFIG_512B_GROUP = 0x1,
+} GroupInterleave;
+typedef enum RowTiling {
+ CONFIG_1KB_ROW = 0x0,
+ CONFIG_2KB_ROW = 0x1,
+ CONFIG_4KB_ROW = 0x2,
+ CONFIG_8KB_ROW = 0x3,
+ CONFIG_1KB_ROW_OPT = 0x4,
+ CONFIG_2KB_ROW_OPT = 0x5,
+ CONFIG_4KB_ROW_OPT = 0x6,
+ CONFIG_8KB_ROW_OPT = 0x7,
+} RowTiling;
+typedef enum BankSwapBytes {
+ CONFIG_128B_SWAPS = 0x0,
+ CONFIG_256B_SWAPS = 0x1,
+ CONFIG_512B_SWAPS = 0x2,
+ CONFIG_1KB_SWAPS = 0x3,
+} BankSwapBytes;
+typedef enum SampleSplitBytes {
+ CONFIG_1KB_SPLIT = 0x0,
+ CONFIG_2KB_SPLIT = 0x1,
+ CONFIG_4KB_SPLIT = 0x2,
+ CONFIG_8KB_SPLIT = 0x3,
+} SampleSplitBytes;
+typedef enum NumPipes {
+ ADDR_CONFIG_1_PIPE = 0x0,
+ ADDR_CONFIG_2_PIPE = 0x1,
+ ADDR_CONFIG_4_PIPE = 0x2,
+ ADDR_CONFIG_8_PIPE = 0x3,
+ ADDR_CONFIG_16_PIPE = 0x4,
+} NumPipes;
+typedef enum PipeInterleaveSize {
+ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
+ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
+} PipeInterleaveSize;
+typedef enum BankInterleaveSize {
+ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
+ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
+ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
+ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
+} BankInterleaveSize;
+typedef enum NumShaderEngines {
+ ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
+ ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
+} NumShaderEngines;
+typedef enum ShaderEngineTileSize {
+ ADDR_CONFIG_SE_TILE_16 = 0x0,
+ ADDR_CONFIG_SE_TILE_32 = 0x1,
+} ShaderEngineTileSize;
+typedef enum NumGPUs {
+ ADDR_CONFIG_1_GPU = 0x0,
+ ADDR_CONFIG_2_GPU = 0x1,
+ ADDR_CONFIG_4_GPU = 0x2,
+} NumGPUs;
+typedef enum MultiGPUTileSize {
+ ADDR_CONFIG_GPU_TILE_16 = 0x0,
+ ADDR_CONFIG_GPU_TILE_32 = 0x1,
+ ADDR_CONFIG_GPU_TILE_64 = 0x2,
+ ADDR_CONFIG_GPU_TILE_128 = 0x3,
+} MultiGPUTileSize;
+typedef enum RowSize {
+ ADDR_CONFIG_1KB_ROW = 0x0,
+ ADDR_CONFIG_2KB_ROW = 0x1,
+ ADDR_CONFIG_4KB_ROW = 0x2,
+} RowSize;
+typedef enum NumLowerPipes {
+ ADDR_CONFIG_1_LOWER_PIPES = 0x0,
+ ADDR_CONFIG_2_LOWER_PIPES = 0x1,
+} NumLowerPipes;
+typedef enum DebugBlockId {
+ DBG_CLIENT_BLKID_RESERVED = 0x0,
+ DBG_CLIENT_BLKID_dbg = 0x1,
+ DBG_CLIENT_BLKID_dco0 = 0x2,
+ DBG_CLIENT_BLKID_wd = 0x3,
+ DBG_CLIENT_BLKID_vmc = 0x4,
+ DBG_CLIENT_BLKID_scf2 = 0x5,
+ DBG_CLIENT_BLKID_spim3 = 0x6,
+ DBG_CLIENT_BLKID_cb3 = 0x7,
+ DBG_CLIENT_BLKID_sx0 = 0x8,
+ DBG_CLIENT_BLKID_cb2 = 0x9,
+ DBG_CLIENT_BLKID_bci1 = 0xa,
+ DBG_CLIENT_BLKID_xdma = 0xb,
+ DBG_CLIENT_BLKID_bci0 = 0xc,
+ DBG_CLIENT_BLKID_spim0 = 0xd,
+ DBG_CLIENT_BLKID_mcd0 = 0xe,
+ DBG_CLIENT_BLKID_mcc0 = 0xf,
+ DBG_CLIENT_BLKID_cb0 = 0x10,
+ DBG_CLIENT_BLKID_cb1 = 0x11,
+ DBG_CLIENT_BLKID_cpc_0 = 0x12,
+ DBG_CLIENT_BLKID_cpc_1 = 0x13,
+ DBG_CLIENT_BLKID_cpf = 0x14,
+ DBG_CLIENT_BLKID_rlc = 0x15,
+ DBG_CLIENT_BLKID_grbm = 0x16,
+ DBG_CLIENT_BLKID_bif = 0x17,
+ DBG_CLIENT_BLKID_scf1 = 0x18,
+ DBG_CLIENT_BLKID_sam = 0x19,
+ DBG_CLIENT_BLKID_mcd4 = 0x1a,
+ DBG_CLIENT_BLKID_mcc4 = 0x1b,
+ DBG_CLIENT_BLKID_gmcon = 0x1c,
+ DBG_CLIENT_BLKID_mcb = 0x1d,
+ DBG_CLIENT_BLKID_vgt0 = 0x1e,
+ DBG_CLIENT_BLKID_pc0 = 0x1f,
+ DBG_CLIENT_BLKID_spim1 = 0x20,
+ DBG_CLIENT_BLKID_bci2 = 0x21,
+ DBG_CLIENT_BLKID_mcd6 = 0x22,
+ DBG_CLIENT_BLKID_mcc6 = 0x23,
+ DBG_CLIENT_BLKID_mcd3 = 0x24,
+ DBG_CLIENT_BLKID_mcc3 = 0x25,
+ DBG_CLIENT_BLKID_uvdm_0 = 0x26,
+ DBG_CLIENT_BLKID_uvdm_1 = 0x27,
+ DBG_CLIENT_BLKID_uvdm_2 = 0x28,
+ DBG_CLIENT_BLKID_uvdm_3 = 0x29,
+ DBG_CLIENT_BLKID_spim2 = 0x2a,
+ DBG_CLIENT_BLKID_ds = 0x2b,
+ DBG_CLIENT_BLKID_srbm = 0x2c,
+ DBG_CLIENT_BLKID_ih = 0x2d,
+ DBG_CLIENT_BLKID_sem = 0x2e,
+ DBG_CLIENT_BLKID_sdma_0 = 0x2f,
+ DBG_CLIENT_BLKID_sdma_1 = 0x30,
+ DBG_CLIENT_BLKID_hdp = 0x31,
+ DBG_CLIENT_BLKID_acp_0 = 0x32,
+ DBG_CLIENT_BLKID_acp_1 = 0x33,
+ DBG_CLIENT_BLKID_vceb_0 = 0x34,
+ DBG_CLIENT_BLKID_vceb_1 = 0x35,
+ DBG_CLIENT_BLKID_vceb_2 = 0x36,
+ DBG_CLIENT_BLKID_mcd2 = 0x37,
+ DBG_CLIENT_BLKID_mcc2 = 0x38,
+ DBG_CLIENT_BLKID_scf3 = 0x39,
+ DBG_CLIENT_BLKID_bci3 = 0x3a,
+ DBG_CLIENT_BLKID_mcd5 = 0x3b,
+ DBG_CLIENT_BLKID_mcc5 = 0x3c,
+ DBG_CLIENT_BLKID_vgt2 = 0x3d,
+ DBG_CLIENT_BLKID_pc2 = 0x3e,
+ DBG_CLIENT_BLKID_smu_0 = 0x3f,
+ DBG_CLIENT_BLKID_smu_1 = 0x40,
+ DBG_CLIENT_BLKID_smu_2 = 0x41,
+ DBG_CLIENT_BLKID_vcea_0 = 0x42,
+ DBG_CLIENT_BLKID_vcea_1 = 0x43,
+ DBG_CLIENT_BLKID_vcea_2 = 0x44,
+ DBG_CLIENT_BLKID_vcea_3 = 0x45,
+ DBG_CLIENT_BLKID_vcea_4 = 0x46,
+ DBG_CLIENT_BLKID_vcea_5 = 0x47,
+ DBG_CLIENT_BLKID_vcea_6 = 0x48,
+ DBG_CLIENT_BLKID_scf0 = 0x49,
+ DBG_CLIENT_BLKID_vgt1 = 0x4a,
+ DBG_CLIENT_BLKID_pc1 = 0x4b,
+ DBG_CLIENT_BLKID_gdc_0 = 0x4c,
+ DBG_CLIENT_BLKID_gdc_1 = 0x4d,
+ DBG_CLIENT_BLKID_gdc_2 = 0x4e,
+ DBG_CLIENT_BLKID_gdc_3 = 0x4f,
+ DBG_CLIENT_BLKID_gdc_4 = 0x50,
+ DBG_CLIENT_BLKID_gdc_5 = 0x51,
+ DBG_CLIENT_BLKID_gdc_6 = 0x52,
+ DBG_CLIENT_BLKID_gdc_7 = 0x53,
+ DBG_CLIENT_BLKID_gdc_8 = 0x54,
+ DBG_CLIENT_BLKID_gdc_9 = 0x55,
+ DBG_CLIENT_BLKID_gdc_10 = 0x56,
+ DBG_CLIENT_BLKID_gdc_11 = 0x57,
+ DBG_CLIENT_BLKID_gdc_12 = 0x58,
+ DBG_CLIENT_BLKID_gdc_13 = 0x59,
+ DBG_CLIENT_BLKID_gdc_14 = 0x5a,
+ DBG_CLIENT_BLKID_gdc_15 = 0x5b,
+ DBG_CLIENT_BLKID_gdc_16 = 0x5c,
+ DBG_CLIENT_BLKID_gdc_17 = 0x5d,
+ DBG_CLIENT_BLKID_gdc_18 = 0x5e,
+ DBG_CLIENT_BLKID_gdc_19 = 0x5f,
+ DBG_CLIENT_BLKID_gdc_20 = 0x60,
+ DBG_CLIENT_BLKID_gdc_21 = 0x61,
+ DBG_CLIENT_BLKID_gdc_22 = 0x62,
+ DBG_CLIENT_BLKID_vgt3 = 0x63,
+ DBG_CLIENT_BLKID_pc3 = 0x64,
+ DBG_CLIENT_BLKID_uvdu_0 = 0x65,
+ DBG_CLIENT_BLKID_uvdu_1 = 0x66,
+ DBG_CLIENT_BLKID_uvdu_2 = 0x67,
+ DBG_CLIENT_BLKID_uvdu_3 = 0x68,
+ DBG_CLIENT_BLKID_uvdu_4 = 0x69,
+ DBG_CLIENT_BLKID_uvdu_5 = 0x6a,
+ DBG_CLIENT_BLKID_uvdu_6 = 0x6b,
+ DBG_CLIENT_BLKID_mcd7 = 0x6c,
+ DBG_CLIENT_BLKID_mcc7 = 0x6d,
+ DBG_CLIENT_BLKID_cpg_0 = 0x6e,
+ DBG_CLIENT_BLKID_cpg_1 = 0x6f,
+ DBG_CLIENT_BLKID_gck = 0x70,
+ DBG_CLIENT_BLKID_mcd1 = 0x71,
+ DBG_CLIENT_BLKID_mcc1 = 0x72,
+ DBG_CLIENT_BLKID_cb101 = 0x73,
+ DBG_CLIENT_BLKID_cb103 = 0x74,
+ DBG_CLIENT_BLKID_sx10 = 0x75,
+ DBG_CLIENT_BLKID_cb102 = 0x76,
+ DBG_CLIENT_BLKID_cb002 = 0x77,
+ DBG_CLIENT_BLKID_cb100 = 0x78,
+ DBG_CLIENT_BLKID_cb000 = 0x79,
+ DBG_CLIENT_BLKID_pa00 = 0x7a,
+ DBG_CLIENT_BLKID_pa10 = 0x7b,
+ DBG_CLIENT_BLKID_ia0 = 0x7c,
+ DBG_CLIENT_BLKID_ia1 = 0x7d,
+ DBG_CLIENT_BLKID_tmonw00 = 0x7e,
+ DBG_CLIENT_BLKID_cb001 = 0x7f,
+ DBG_CLIENT_BLKID_cb003 = 0x80,
+ DBG_CLIENT_BLKID_sx00 = 0x81,
+ DBG_CLIENT_BLKID_sx20 = 0x82,
+ DBG_CLIENT_BLKID_cb203 = 0x83,
+ DBG_CLIENT_BLKID_cb201 = 0x84,
+ DBG_CLIENT_BLKID_cb302 = 0x85,
+ DBG_CLIENT_BLKID_cb202 = 0x86,
+ DBG_CLIENT_BLKID_cb300 = 0x87,
+ DBG_CLIENT_BLKID_cb200 = 0x88,
+ DBG_CLIENT_BLKID_pa01 = 0x89,
+ DBG_CLIENT_BLKID_pa11 = 0x8a,
+ DBG_CLIENT_BLKID_sx30 = 0x8b,
+ DBG_CLIENT_BLKID_cb303 = 0x8c,
+ DBG_CLIENT_BLKID_cb301 = 0x8d,
+ DBG_CLIENT_BLKID_dco = 0x8e,
+ DBG_CLIENT_BLKID_scb0 = 0x8f,
+ DBG_CLIENT_BLKID_scb1 = 0x90,
+ DBG_CLIENT_BLKID_scb2 = 0x91,
+ DBG_CLIENT_BLKID_scb3 = 0x92,
+ DBG_CLIENT_BLKID_tmonw01 = 0x93,
+ DBG_CLIENT_BLKID_RESERVED_LAST = 0x94,
+} DebugBlockId;
+typedef enum DebugBlockId_OLD {
+ DBG_BLOCK_ID_RESERVED = 0x0,
+ DBG_BLOCK_ID_DBG = 0x1,
+ DBG_BLOCK_ID_VMC = 0x2,
+ DBG_BLOCK_ID_PDMA = 0x3,
+ DBG_BLOCK_ID_CG = 0x4,
+ DBG_BLOCK_ID_SRBM = 0x5,
+ DBG_BLOCK_ID_GRBM = 0x6,
+ DBG_BLOCK_ID_RLC = 0x7,
+ DBG_BLOCK_ID_CSC = 0x8,
+ DBG_BLOCK_ID_SEM = 0x9,
+ DBG_BLOCK_ID_IH = 0xa,
+ DBG_BLOCK_ID_SC = 0xb,
+ DBG_BLOCK_ID_SQ = 0xc,
+ DBG_BLOCK_ID_AVP = 0xd,
+ DBG_BLOCK_ID_GMCON = 0xe,
+ DBG_BLOCK_ID_SMU = 0xf,
+ DBG_BLOCK_ID_DMA0 = 0x10,
+ DBG_BLOCK_ID_DMA1 = 0x11,
+ DBG_BLOCK_ID_SPIM = 0x12,
+ DBG_BLOCK_ID_GDS = 0x13,
+ DBG_BLOCK_ID_SPIS = 0x14,
+ DBG_BLOCK_ID_UNUSED0 = 0x15,
+ DBG_BLOCK_ID_PA0 = 0x16,
+ DBG_BLOCK_ID_PA1 = 0x17,
+ DBG_BLOCK_ID_CP0 = 0x18,
+ DBG_BLOCK_ID_CP1 = 0x19,
+ DBG_BLOCK_ID_CP2 = 0x1a,
+ DBG_BLOCK_ID_UNUSED1 = 0x1b,
+ DBG_BLOCK_ID_UVDU = 0x1c,
+ DBG_BLOCK_ID_UVDM = 0x1d,
+ DBG_BLOCK_ID_VCE = 0x1e,
+ DBG_BLOCK_ID_UNUSED2 = 0x1f,
+ DBG_BLOCK_ID_VGT0 = 0x20,
+ DBG_BLOCK_ID_VGT1 = 0x21,
+ DBG_BLOCK_ID_IA = 0x22,
+ DBG_BLOCK_ID_UNUSED3 = 0x23,
+ DBG_BLOCK_ID_SCT0 = 0x24,
+ DBG_BLOCK_ID_SCT1 = 0x25,
+ DBG_BLOCK_ID_SPM0 = 0x26,
+ DBG_BLOCK_ID_SPM1 = 0x27,
+ DBG_BLOCK_ID_TCAA = 0x28,
+ DBG_BLOCK_ID_TCAB = 0x29,
+ DBG_BLOCK_ID_TCCA = 0x2a,
+ DBG_BLOCK_ID_TCCB = 0x2b,
+ DBG_BLOCK_ID_MCC0 = 0x2c,
+ DBG_BLOCK_ID_MCC1 = 0x2d,
+ DBG_BLOCK_ID_MCC2 = 0x2e,
+ DBG_BLOCK_ID_MCC3 = 0x2f,
+ DBG_BLOCK_ID_SX0 = 0x30,
+ DBG_BLOCK_ID_SX1 = 0x31,
+ DBG_BLOCK_ID_SX2 = 0x32,
+ DBG_BLOCK_ID_SX3 = 0x33,
+ DBG_BLOCK_ID_UNUSED4 = 0x34,
+ DBG_BLOCK_ID_UNUSED5 = 0x35,
+ DBG_BLOCK_ID_UNUSED6 = 0x36,
+ DBG_BLOCK_ID_UNUSED7 = 0x37,
+ DBG_BLOCK_ID_PC0 = 0x38,
+ DBG_BLOCK_ID_PC1 = 0x39,
+ DBG_BLOCK_ID_UNUSED8 = 0x3a,
+ DBG_BLOCK_ID_UNUSED9 = 0x3b,
+ DBG_BLOCK_ID_UNUSED10 = 0x3c,
+ DBG_BLOCK_ID_UNUSED11 = 0x3d,
+ DBG_BLOCK_ID_MCB = 0x3e,
+ DBG_BLOCK_ID_UNUSED12 = 0x3f,
+ DBG_BLOCK_ID_SCB0 = 0x40,
+ DBG_BLOCK_ID_SCB1 = 0x41,
+ DBG_BLOCK_ID_UNUSED13 = 0x42,
+ DBG_BLOCK_ID_UNUSED14 = 0x43,
+ DBG_BLOCK_ID_SCF0 = 0x44,
+ DBG_BLOCK_ID_SCF1 = 0x45,
+ DBG_BLOCK_ID_UNUSED15 = 0x46,
+ DBG_BLOCK_ID_UNUSED16 = 0x47,
+ DBG_BLOCK_ID_BCI0 = 0x48,
+ DBG_BLOCK_ID_BCI1 = 0x49,
+ DBG_BLOCK_ID_BCI2 = 0x4a,
+ DBG_BLOCK_ID_BCI3 = 0x4b,
+ DBG_BLOCK_ID_UNUSED17 = 0x4c,
+ DBG_BLOCK_ID_UNUSED18 = 0x4d,
+ DBG_BLOCK_ID_UNUSED19 = 0x4e,
+ DBG_BLOCK_ID_UNUSED20 = 0x4f,
+ DBG_BLOCK_ID_CB00 = 0x50,
+ DBG_BLOCK_ID_CB01 = 0x51,
+ DBG_BLOCK_ID_CB02 = 0x52,
+ DBG_BLOCK_ID_CB03 = 0x53,
+ DBG_BLOCK_ID_CB04 = 0x54,
+ DBG_BLOCK_ID_UNUSED21 = 0x55,
+ DBG_BLOCK_ID_UNUSED22 = 0x56,
+ DBG_BLOCK_ID_UNUSED23 = 0x57,
+ DBG_BLOCK_ID_CB10 = 0x58,
+ DBG_BLOCK_ID_CB11 = 0x59,
+ DBG_BLOCK_ID_CB12 = 0x5a,
+ DBG_BLOCK_ID_CB13 = 0x5b,
+ DBG_BLOCK_ID_CB14 = 0x5c,
+ DBG_BLOCK_ID_UNUSED24 = 0x5d,
+ DBG_BLOCK_ID_UNUSED25 = 0x5e,
+ DBG_BLOCK_ID_UNUSED26 = 0x5f,
+ DBG_BLOCK_ID_TCP0 = 0x60,
+ DBG_BLOCK_ID_TCP1 = 0x61,
+ DBG_BLOCK_ID_TCP2 = 0x62,
+ DBG_BLOCK_ID_TCP3 = 0x63,
+ DBG_BLOCK_ID_TCP4 = 0x64,
+ DBG_BLOCK_ID_TCP5 = 0x65,
+ DBG_BLOCK_ID_TCP6 = 0x66,
+ DBG_BLOCK_ID_TCP7 = 0x67,
+ DBG_BLOCK_ID_TCP8 = 0x68,
+ DBG_BLOCK_ID_TCP9 = 0x69,
+ DBG_BLOCK_ID_TCP10 = 0x6a,
+ DBG_BLOCK_ID_TCP11 = 0x6b,
+ DBG_BLOCK_ID_TCP12 = 0x6c,
+ DBG_BLOCK_ID_TCP13 = 0x6d,
+ DBG_BLOCK_ID_TCP14 = 0x6e,
+ DBG_BLOCK_ID_TCP15 = 0x6f,
+ DBG_BLOCK_ID_TCP16 = 0x70,
+ DBG_BLOCK_ID_TCP17 = 0x71,
+ DBG_BLOCK_ID_TCP18 = 0x72,
+ DBG_BLOCK_ID_TCP19 = 0x73,
+ DBG_BLOCK_ID_TCP20 = 0x74,
+ DBG_BLOCK_ID_TCP21 = 0x75,
+ DBG_BLOCK_ID_TCP22 = 0x76,
+ DBG_BLOCK_ID_TCP23 = 0x77,
+ DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
+ DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
+ DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
+ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
+ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
+ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
+ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
+ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
+ DBG_BLOCK_ID_DB00 = 0x80,
+ DBG_BLOCK_ID_DB01 = 0x81,
+ DBG_BLOCK_ID_DB02 = 0x82,
+ DBG_BLOCK_ID_DB03 = 0x83,
+ DBG_BLOCK_ID_DB04 = 0x84,
+ DBG_BLOCK_ID_UNUSED27 = 0x85,
+ DBG_BLOCK_ID_UNUSED28 = 0x86,
+ DBG_BLOCK_ID_UNUSED29 = 0x87,
+ DBG_BLOCK_ID_DB10 = 0x88,
+ DBG_BLOCK_ID_DB11 = 0x89,
+ DBG_BLOCK_ID_DB12 = 0x8a,
+ DBG_BLOCK_ID_DB13 = 0x8b,
+ DBG_BLOCK_ID_DB14 = 0x8c,
+ DBG_BLOCK_ID_UNUSED30 = 0x8d,
+ DBG_BLOCK_ID_UNUSED31 = 0x8e,
+ DBG_BLOCK_ID_UNUSED32 = 0x8f,
+ DBG_BLOCK_ID_TCC0 = 0x90,
+ DBG_BLOCK_ID_TCC1 = 0x91,
+ DBG_BLOCK_ID_TCC2 = 0x92,
+ DBG_BLOCK_ID_TCC3 = 0x93,
+ DBG_BLOCK_ID_TCC4 = 0x94,
+ DBG_BLOCK_ID_TCC5 = 0x95,
+ DBG_BLOCK_ID_TCC6 = 0x96,
+ DBG_BLOCK_ID_TCC7 = 0x97,
+ DBG_BLOCK_ID_SPS00 = 0x98,
+ DBG_BLOCK_ID_SPS01 = 0x99,
+ DBG_BLOCK_ID_SPS02 = 0x9a,
+ DBG_BLOCK_ID_SPS10 = 0x9b,
+ DBG_BLOCK_ID_SPS11 = 0x9c,
+ DBG_BLOCK_ID_SPS12 = 0x9d,
+ DBG_BLOCK_ID_UNUSED33 = 0x9e,
+ DBG_BLOCK_ID_UNUSED34 = 0x9f,
+ DBG_BLOCK_ID_TA00 = 0xa0,
+ DBG_BLOCK_ID_TA01 = 0xa1,
+ DBG_BLOCK_ID_TA02 = 0xa2,
+ DBG_BLOCK_ID_TA03 = 0xa3,
+ DBG_BLOCK_ID_TA04 = 0xa4,
+ DBG_BLOCK_ID_TA05 = 0xa5,
+ DBG_BLOCK_ID_TA06 = 0xa6,
+ DBG_BLOCK_ID_TA07 = 0xa7,
+ DBG_BLOCK_ID_TA08 = 0xa8,
+ DBG_BLOCK_ID_TA09 = 0xa9,
+ DBG_BLOCK_ID_TA0A = 0xaa,
+ DBG_BLOCK_ID_TA0B = 0xab,
+ DBG_BLOCK_ID_UNUSED35 = 0xac,
+ DBG_BLOCK_ID_UNUSED36 = 0xad,
+ DBG_BLOCK_ID_UNUSED37 = 0xae,
+ DBG_BLOCK_ID_UNUSED38 = 0xaf,
+ DBG_BLOCK_ID_TA10 = 0xb0,
+ DBG_BLOCK_ID_TA11 = 0xb1,
+ DBG_BLOCK_ID_TA12 = 0xb2,
+ DBG_BLOCK_ID_TA13 = 0xb3,
+ DBG_BLOCK_ID_TA14 = 0xb4,
+ DBG_BLOCK_ID_TA15 = 0xb5,
+ DBG_BLOCK_ID_TA16 = 0xb6,
+ DBG_BLOCK_ID_TA17 = 0xb7,
+ DBG_BLOCK_ID_TA18 = 0xb8,
+ DBG_BLOCK_ID_TA19 = 0xb9,
+ DBG_BLOCK_ID_TA1A = 0xba,
+ DBG_BLOCK_ID_TA1B = 0xbb,
+ DBG_BLOCK_ID_UNUSED39 = 0xbc,
+ DBG_BLOCK_ID_UNUSED40 = 0xbd,
+ DBG_BLOCK_ID_UNUSED41 = 0xbe,
+ DBG_BLOCK_ID_UNUSED42 = 0xbf,
+ DBG_BLOCK_ID_TD00 = 0xc0,
+ DBG_BLOCK_ID_TD01 = 0xc1,
+ DBG_BLOCK_ID_TD02 = 0xc2,
+ DBG_BLOCK_ID_TD03 = 0xc3,
+ DBG_BLOCK_ID_TD04 = 0xc4,
+ DBG_BLOCK_ID_TD05 = 0xc5,
+ DBG_BLOCK_ID_TD06 = 0xc6,
+ DBG_BLOCK_ID_TD07 = 0xc7,
+ DBG_BLOCK_ID_TD08 = 0xc8,
+ DBG_BLOCK_ID_TD09 = 0xc9,
+ DBG_BLOCK_ID_TD0A = 0xca,
+ DBG_BLOCK_ID_TD0B = 0xcb,
+ DBG_BLOCK_ID_UNUSED43 = 0xcc,
+ DBG_BLOCK_ID_UNUSED44 = 0xcd,
+ DBG_BLOCK_ID_UNUSED45 = 0xce,
+ DBG_BLOCK_ID_UNUSED46 = 0xcf,
+ DBG_BLOCK_ID_TD10 = 0xd0,
+ DBG_BLOCK_ID_TD11 = 0xd1,
+ DBG_BLOCK_ID_TD12 = 0xd2,
+ DBG_BLOCK_ID_TD13 = 0xd3,
+ DBG_BLOCK_ID_TD14 = 0xd4,
+ DBG_BLOCK_ID_TD15 = 0xd5,
+ DBG_BLOCK_ID_TD16 = 0xd6,
+ DBG_BLOCK_ID_TD17 = 0xd7,
+ DBG_BLOCK_ID_TD18 = 0xd8,
+ DBG_BLOCK_ID_TD19 = 0xd9,
+ DBG_BLOCK_ID_TD1A = 0xda,
+ DBG_BLOCK_ID_TD1B = 0xdb,
+ DBG_BLOCK_ID_UNUSED47 = 0xdc,
+ DBG_BLOCK_ID_UNUSED48 = 0xdd,
+ DBG_BLOCK_ID_UNUSED49 = 0xde,
+ DBG_BLOCK_ID_UNUSED50 = 0xdf,
+ DBG_BLOCK_ID_MCD0 = 0xe0,
+ DBG_BLOCK_ID_MCD1 = 0xe1,
+ DBG_BLOCK_ID_MCD2 = 0xe2,
+ DBG_BLOCK_ID_MCD3 = 0xe3,
+ DBG_BLOCK_ID_MCD4 = 0xe4,
+ DBG_BLOCK_ID_MCD5 = 0xe5,
+ DBG_BLOCK_ID_UNUSED51 = 0xe6,
+ DBG_BLOCK_ID_UNUSED52 = 0xe7,
+} DebugBlockId_OLD;
+typedef enum DebugBlockId_BY2 {
+ DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
+ DBG_BLOCK_ID_VMC_BY2 = 0x1,
+ DBG_BLOCK_ID_CG_BY2 = 0x2,
+ DBG_BLOCK_ID_GRBM_BY2 = 0x3,
+ DBG_BLOCK_ID_CSC_BY2 = 0x4,
+ DBG_BLOCK_ID_IH_BY2 = 0x5,
+ DBG_BLOCK_ID_SQ_BY2 = 0x6,
+ DBG_BLOCK_ID_GMCON_BY2 = 0x7,
+ DBG_BLOCK_ID_DMA0_BY2 = 0x8,
+ DBG_BLOCK_ID_SPIM_BY2 = 0x9,
+ DBG_BLOCK_ID_SPIS_BY2 = 0xa,
+ DBG_BLOCK_ID_PA0_BY2 = 0xb,
+ DBG_BLOCK_ID_CP0_BY2 = 0xc,
+ DBG_BLOCK_ID_CP2_BY2 = 0xd,
+ DBG_BLOCK_ID_UVDU_BY2 = 0xe,
+ DBG_BLOCK_ID_VCE_BY2 = 0xf,
+ DBG_BLOCK_ID_VGT0_BY2 = 0x10,
+ DBG_BLOCK_ID_IA_BY2 = 0x11,
+ DBG_BLOCK_ID_SCT0_BY2 = 0x12,
+ DBG_BLOCK_ID_SPM0_BY2 = 0x13,
+ DBG_BLOCK_ID_TCAA_BY2 = 0x14,
+ DBG_BLOCK_ID_TCCA_BY2 = 0x15,
+ DBG_BLOCK_ID_MCC0_BY2 = 0x16,
+ DBG_BLOCK_ID_MCC2_BY2 = 0x17,
+ DBG_BLOCK_ID_SX0_BY2 = 0x18,
+ DBG_BLOCK_ID_SX2_BY2 = 0x19,
+ DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
+ DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
+ DBG_BLOCK_ID_PC0_BY2 = 0x1c,
+ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
+ DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
+ DBG_BLOCK_ID_MCB_BY2 = 0x1f,
+ DBG_BLOCK_ID_SCB0_BY2 = 0x20,
+ DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
+ DBG_BLOCK_ID_SCF0_BY2 = 0x22,
+ DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
+ DBG_BLOCK_ID_BCI0_BY2 = 0x24,
+ DBG_BLOCK_ID_BCI2_BY2 = 0x25,
+ DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
+ DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
+ DBG_BLOCK_ID_CB00_BY2 = 0x28,
+ DBG_BLOCK_ID_CB02_BY2 = 0x29,
+ DBG_BLOCK_ID_CB04_BY2 = 0x2a,
+ DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
+ DBG_BLOCK_ID_CB10_BY2 = 0x2c,
+ DBG_BLOCK_ID_CB12_BY2 = 0x2d,
+ DBG_BLOCK_ID_CB14_BY2 = 0x2e,
+ DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
+ DBG_BLOCK_ID_TCP0_BY2 = 0x30,
+ DBG_BLOCK_ID_TCP2_BY2 = 0x31,
+ DBG_BLOCK_ID_TCP4_BY2 = 0x32,
+ DBG_BLOCK_ID_TCP6_BY2 = 0x33,
+ DBG_BLOCK_ID_TCP8_BY2 = 0x34,
+ DBG_BLOCK_ID_TCP10_BY2 = 0x35,
+ DBG_BLOCK_ID_TCP12_BY2 = 0x36,
+ DBG_BLOCK_ID_TCP14_BY2 = 0x37,
+ DBG_BLOCK_ID_TCP16_BY2 = 0x38,
+ DBG_BLOCK_ID_TCP18_BY2 = 0x39,
+ DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
+ DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
+ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
+ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
+ DBG_BLOCK_ID_DB00_BY2 = 0x40,
+ DBG_BLOCK_ID_DB02_BY2 = 0x41,
+ DBG_BLOCK_ID_DB04_BY2 = 0x42,
+ DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
+ DBG_BLOCK_ID_DB10_BY2 = 0x44,
+ DBG_BLOCK_ID_DB12_BY2 = 0x45,
+ DBG_BLOCK_ID_DB14_BY2 = 0x46,
+ DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
+ DBG_BLOCK_ID_TCC0_BY2 = 0x48,
+ DBG_BLOCK_ID_TCC2_BY2 = 0x49,
+ DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
+ DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
+ DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
+ DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
+ DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
+ DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
+ DBG_BLOCK_ID_TA00_BY2 = 0x50,
+ DBG_BLOCK_ID_TA02_BY2 = 0x51,
+ DBG_BLOCK_ID_TA04_BY2 = 0x52,
+ DBG_BLOCK_ID_TA06_BY2 = 0x53,
+ DBG_BLOCK_ID_TA08_BY2 = 0x54,
+ DBG_BLOCK_ID_TA0A_BY2 = 0x55,
+ DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
+ DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
+ DBG_BLOCK_ID_TA10_BY2 = 0x58,
+ DBG_BLOCK_ID_TA12_BY2 = 0x59,
+ DBG_BLOCK_ID_TA14_BY2 = 0x5a,
+ DBG_BLOCK_ID_TA16_BY2 = 0x5b,
+ DBG_BLOCK_ID_TA18_BY2 = 0x5c,
+ DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
+ DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
+ DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
+ DBG_BLOCK_ID_TD00_BY2 = 0x60,
+ DBG_BLOCK_ID_TD02_BY2 = 0x61,
+ DBG_BLOCK_ID_TD04_BY2 = 0x62,
+ DBG_BLOCK_ID_TD06_BY2 = 0x63,
+ DBG_BLOCK_ID_TD08_BY2 = 0x64,
+ DBG_BLOCK_ID_TD0A_BY2 = 0x65,
+ DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
+ DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
+ DBG_BLOCK_ID_TD10_BY2 = 0x68,
+ DBG_BLOCK_ID_TD12_BY2 = 0x69,
+ DBG_BLOCK_ID_TD14_BY2 = 0x6a,
+ DBG_BLOCK_ID_TD16_BY2 = 0x6b,
+ DBG_BLOCK_ID_TD18_BY2 = 0x6c,
+ DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
+ DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
+ DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
+ DBG_BLOCK_ID_MCD0_BY2 = 0x70,
+ DBG_BLOCK_ID_MCD2_BY2 = 0x71,
+ DBG_BLOCK_ID_MCD4_BY2 = 0x72,
+ DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
+} DebugBlockId_BY2;
+typedef enum DebugBlockId_BY4 {
+ DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
+ DBG_BLOCK_ID_CG_BY4 = 0x1,
+ DBG_BLOCK_ID_CSC_BY4 = 0x2,
+ DBG_BLOCK_ID_SQ_BY4 = 0x3,
+ DBG_BLOCK_ID_DMA0_BY4 = 0x4,
+ DBG_BLOCK_ID_SPIS_BY4 = 0x5,
+ DBG_BLOCK_ID_CP0_BY4 = 0x6,
+ DBG_BLOCK_ID_UVDU_BY4 = 0x7,
+ DBG_BLOCK_ID_VGT0_BY4 = 0x8,
+ DBG_BLOCK_ID_SCT0_BY4 = 0x9,
+ DBG_BLOCK_ID_TCAA_BY4 = 0xa,
+ DBG_BLOCK_ID_MCC0_BY4 = 0xb,
+ DBG_BLOCK_ID_SX0_BY4 = 0xc,
+ DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
+ DBG_BLOCK_ID_PC0_BY4 = 0xe,
+ DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
+ DBG_BLOCK_ID_SCB0_BY4 = 0x10,
+ DBG_BLOCK_ID_SCF0_BY4 = 0x11,
+ DBG_BLOCK_ID_BCI0_BY4 = 0x12,
+ DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
+ DBG_BLOCK_ID_CB00_BY4 = 0x14,
+ DBG_BLOCK_ID_CB04_BY4 = 0x15,
+ DBG_BLOCK_ID_CB10_BY4 = 0x16,
+ DBG_BLOCK_ID_CB14_BY4 = 0x17,
+ DBG_BLOCK_ID_TCP0_BY4 = 0x18,
+ DBG_BLOCK_ID_TCP4_BY4 = 0x19,
+ DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
+ DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
+ DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
+ DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
+ DBG_BLOCK_ID_DB_BY4 = 0x20,
+ DBG_BLOCK_ID_DB04_BY4 = 0x21,
+ DBG_BLOCK_ID_DB10_BY4 = 0x22,
+ DBG_BLOCK_ID_DB14_BY4 = 0x23,
+ DBG_BLOCK_ID_TCC0_BY4 = 0x24,
+ DBG_BLOCK_ID_TCC4_BY4 = 0x25,
+ DBG_BLOCK_ID_SPS00_BY4 = 0x26,
+ DBG_BLOCK_ID_SPS11_BY4 = 0x27,
+ DBG_BLOCK_ID_TA00_BY4 = 0x28,
+ DBG_BLOCK_ID_TA04_BY4 = 0x29,
+ DBG_BLOCK_ID_TA08_BY4 = 0x2a,
+ DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
+ DBG_BLOCK_ID_TA10_BY4 = 0x2c,
+ DBG_BLOCK_ID_TA14_BY4 = 0x2d,
+ DBG_BLOCK_ID_TA18_BY4 = 0x2e,
+ DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
+ DBG_BLOCK_ID_TD00_BY4 = 0x30,
+ DBG_BLOCK_ID_TD04_BY4 = 0x31,
+ DBG_BLOCK_ID_TD08_BY4 = 0x32,
+ DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
+ DBG_BLOCK_ID_TD10_BY4 = 0x34,
+ DBG_BLOCK_ID_TD14_BY4 = 0x35,
+ DBG_BLOCK_ID_TD18_BY4 = 0x36,
+ DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
+ DBG_BLOCK_ID_MCD0_BY4 = 0x38,
+ DBG_BLOCK_ID_MCD4_BY4 = 0x39,
+} DebugBlockId_BY4;
+typedef enum DebugBlockId_BY8 {
+ DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
+ DBG_BLOCK_ID_CSC_BY8 = 0x1,
+ DBG_BLOCK_ID_DMA0_BY8 = 0x2,
+ DBG_BLOCK_ID_CP0_BY8 = 0x3,
+ DBG_BLOCK_ID_VGT0_BY8 = 0x4,
+ DBG_BLOCK_ID_TCAA_BY8 = 0x5,
+ DBG_BLOCK_ID_SX0_BY8 = 0x6,
+ DBG_BLOCK_ID_PC0_BY8 = 0x7,
+ DBG_BLOCK_ID_SCB0_BY8 = 0x8,
+ DBG_BLOCK_ID_BCI0_BY8 = 0x9,
+ DBG_BLOCK_ID_CB00_BY8 = 0xa,
+ DBG_BLOCK_ID_CB10_BY8 = 0xb,
+ DBG_BLOCK_ID_TCP0_BY8 = 0xc,
+ DBG_BLOCK_ID_TCP8_BY8 = 0xd,
+ DBG_BLOCK_ID_TCP16_BY8 = 0xe,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
+ DBG_BLOCK_ID_DB00_BY8 = 0x10,
+ DBG_BLOCK_ID_DB10_BY8 = 0x11,
+ DBG_BLOCK_ID_TCC0_BY8 = 0x12,
+ DBG_BLOCK_ID_SPS00_BY8 = 0x13,
+ DBG_BLOCK_ID_TA00_BY8 = 0x14,
+ DBG_BLOCK_ID_TA08_BY8 = 0x15,
+ DBG_BLOCK_ID_TA10_BY8 = 0x16,
+ DBG_BLOCK_ID_TA18_BY8 = 0x17,
+ DBG_BLOCK_ID_TD00_BY8 = 0x18,
+ DBG_BLOCK_ID_TD08_BY8 = 0x19,
+ DBG_BLOCK_ID_TD10_BY8 = 0x1a,
+ DBG_BLOCK_ID_TD18_BY8 = 0x1b,
+ DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
+} DebugBlockId_BY8;
+typedef enum DebugBlockId_BY16 {
+ DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
+ DBG_BLOCK_ID_DMA0_BY16 = 0x1,
+ DBG_BLOCK_ID_VGT0_BY16 = 0x2,
+ DBG_BLOCK_ID_SX0_BY16 = 0x3,
+ DBG_BLOCK_ID_SCB0_BY16 = 0x4,
+ DBG_BLOCK_ID_CB00_BY16 = 0x5,
+ DBG_BLOCK_ID_TCP0_BY16 = 0x6,
+ DBG_BLOCK_ID_TCP16_BY16 = 0x7,
+ DBG_BLOCK_ID_DB00_BY16 = 0x8,
+ DBG_BLOCK_ID_TCC0_BY16 = 0x9,
+ DBG_BLOCK_ID_TA00_BY16 = 0xa,
+ DBG_BLOCK_ID_TA10_BY16 = 0xb,
+ DBG_BLOCK_ID_TD00_BY16 = 0xc,
+ DBG_BLOCK_ID_TD10_BY16 = 0xd,
+ DBG_BLOCK_ID_MCD0_BY16 = 0xe,
+} DebugBlockId_BY16;
+typedef enum CompareRef {
+ REF_NEVER = 0x0,
+ REF_LESS = 0x1,
+ REF_EQUAL = 0x2,
+ REF_LEQUAL = 0x3,
+ REF_GREATER = 0x4,
+ REF_NOTEQUAL = 0x5,
+ REF_GEQUAL = 0x6,
+ REF_ALWAYS = 0x7,
+} CompareRef;
+typedef enum ReadSize {
+ READ_256_BITS = 0x0,
+ READ_512_BITS = 0x1,
+} ReadSize;
+typedef enum DepthFormat {
+ DEPTH_INVALID = 0x0,
+ DEPTH_16 = 0x1,
+ DEPTH_X8_24 = 0x2,
+ DEPTH_8_24 = 0x3,
+ DEPTH_X8_24_FLOAT = 0x4,
+ DEPTH_8_24_FLOAT = 0x5,
+ DEPTH_32_FLOAT = 0x6,
+ DEPTH_X24_8_32_FLOAT = 0x7,
+} DepthFormat;
+typedef enum ZFormat {
+ Z_INVALID = 0x0,
+ Z_16 = 0x1,
+ Z_24 = 0x2,
+ Z_32_FLOAT = 0x3,
+} ZFormat;
+typedef enum StencilFormat {
+ STENCIL_INVALID = 0x0,
+ STENCIL_8 = 0x1,
+} StencilFormat;
+typedef enum CmaskMode {
+ CMASK_CLEAR_NONE = 0x0,
+ CMASK_CLEAR_ONE = 0x1,
+ CMASK_CLEAR_ALL = 0x2,
+ CMASK_ANY_EXPANDED = 0x3,
+ CMASK_ALPHA0_FRAG1 = 0x4,
+ CMASK_ALPHA0_FRAG2 = 0x5,
+ CMASK_ALPHA0_FRAG4 = 0x6,
+ CMASK_ALPHA0_FRAGS = 0x7,
+ CMASK_ALPHA1_FRAG1 = 0x8,
+ CMASK_ALPHA1_FRAG2 = 0x9,
+ CMASK_ALPHA1_FRAG4 = 0xa,
+ CMASK_ALPHA1_FRAGS = 0xb,
+ CMASK_ALPHAX_FRAG1 = 0xc,
+ CMASK_ALPHAX_FRAG2 = 0xd,
+ CMASK_ALPHAX_FRAG4 = 0xe,
+ CMASK_ALPHAX_FRAGS = 0xf,
+} CmaskMode;
+typedef enum QuadExportFormat {
+ EXPORT_UNUSED = 0x0,
+ EXPORT_32_R = 0x1,
+ EXPORT_32_GR = 0x2,
+ EXPORT_32_AR = 0x3,
+ EXPORT_FP16_ABGR = 0x4,
+ EXPORT_UNSIGNED16_ABGR = 0x5,
+ EXPORT_SIGNED16_ABGR = 0x6,
+ EXPORT_32_ABGR = 0x7,
+} QuadExportFormat;
+typedef enum QuadExportFormatOld {
+ EXPORT_4P_32BPC_ABGR = 0x0,
+ EXPORT_4P_16BPC_ABGR = 0x1,
+ EXPORT_4P_32BPC_GR = 0x2,
+ EXPORT_4P_32BPC_AR = 0x3,
+ EXPORT_2P_32BPC_ABGR = 0x4,
+ EXPORT_8P_32BPC_R = 0x5,
+} QuadExportFormatOld;
+typedef enum ColorFormat {
+ COLOR_INVALID = 0x0,
+ COLOR_8 = 0x1,
+ COLOR_16 = 0x2,
+ COLOR_8_8 = 0x3,
+ COLOR_32 = 0x4,
+ COLOR_16_16 = 0x5,
+ COLOR_10_11_11 = 0x6,
+ COLOR_11_11_10 = 0x7,
+ COLOR_10_10_10_2 = 0x8,
+ COLOR_2_10_10_10 = 0x9,
+ COLOR_8_8_8_8 = 0xa,
+ COLOR_32_32 = 0xb,
+ COLOR_16_16_16_16 = 0xc,
+ COLOR_RESERVED_13 = 0xd,
+ COLOR_32_32_32_32 = 0xe,
+ COLOR_RESERVED_15 = 0xf,
+ COLOR_5_6_5 = 0x10,
+ COLOR_1_5_5_5 = 0x11,
+ COLOR_5_5_5_1 = 0x12,
+ COLOR_4_4_4_4 = 0x13,
+ COLOR_8_24 = 0x14,
+ COLOR_24_8 = 0x15,
+ COLOR_X24_8_32_FLOAT = 0x16,
+ COLOR_RESERVED_23 = 0x17,
+} ColorFormat;
+typedef enum SurfaceFormat {
+ FMT_INVALID = 0x0,
+ FMT_8 = 0x1,
+ FMT_16 = 0x2,
+ FMT_8_8 = 0x3,
+ FMT_32 = 0x4,
+ FMT_16_16 = 0x5,
+ FMT_10_11_11 = 0x6,
+ FMT_11_11_10 = 0x7,
+ FMT_10_10_10_2 = 0x8,
+ FMT_2_10_10_10 = 0x9,
+ FMT_8_8_8_8 = 0xa,
+ FMT_32_32 = 0xb,
+ FMT_16_16_16_16 = 0xc,
+ FMT_32_32_32 = 0xd,
+ FMT_32_32_32_32 = 0xe,
+ FMT_RESERVED_4 = 0xf,
+ FMT_5_6_5 = 0x10,
+ FMT_1_5_5_5 = 0x11,
+ FMT_5_5_5_1 = 0x12,
+ FMT_4_4_4_4 = 0x13,
+ FMT_8_24 = 0x14,
+ FMT_24_8 = 0x15,
+ FMT_X24_8_32_FLOAT = 0x16,
+ FMT_RESERVED_33 = 0x17,
+ FMT_11_11_10_FLOAT = 0x18,
+ FMT_16_FLOAT = 0x19,
+ FMT_32_FLOAT = 0x1a,
+ FMT_16_16_FLOAT = 0x1b,
+ FMT_8_24_FLOAT = 0x1c,
+ FMT_24_8_FLOAT = 0x1d,
+ FMT_32_32_FLOAT = 0x1e,
+ FMT_10_11_11_FLOAT = 0x1f,
+ FMT_16_16_16_16_FLOAT = 0x20,
+ FMT_3_3_2 = 0x21,
+ FMT_6_5_5 = 0x22,
+ FMT_32_32_32_32_FLOAT = 0x23,
+ FMT_RESERVED_36 = 0x24,
+ FMT_1 = 0x25,
+ FMT_1_REVERSED = 0x26,
+ FMT_GB_GR = 0x27,
+ FMT_BG_RG = 0x28,
+ FMT_32_AS_8 = 0x29,
+ FMT_32_AS_8_8 = 0x2a,
+ FMT_5_9_9_9_SHAREDEXP = 0x2b,
+ FMT_8_8_8 = 0x2c,
+ FMT_16_16_16 = 0x2d,
+ FMT_16_16_16_FLOAT = 0x2e,
+ FMT_4_4 = 0x2f,
+ FMT_32_32_32_FLOAT = 0x30,
+ FMT_BC1 = 0x31,
+ FMT_BC2 = 0x32,
+ FMT_BC3 = 0x33,
+ FMT_BC4 = 0x34,
+ FMT_BC5 = 0x35,
+ FMT_BC6 = 0x36,
+ FMT_BC7 = 0x37,
+ FMT_32_AS_32_32_32_32 = 0x38,
+ FMT_APC3 = 0x39,
+ FMT_APC4 = 0x3a,
+ FMT_APC5 = 0x3b,
+ FMT_APC6 = 0x3c,
+ FMT_APC7 = 0x3d,
+ FMT_CTX1 = 0x3e,
+ FMT_RESERVED_63 = 0x3f,
+} SurfaceFormat;
+typedef enum BUF_DATA_FORMAT {
+ BUF_DATA_FORMAT_INVALID = 0x0,
+ BUF_DATA_FORMAT_8 = 0x1,
+ BUF_DATA_FORMAT_16 = 0x2,
+ BUF_DATA_FORMAT_8_8 = 0x3,
+ BUF_DATA_FORMAT_32 = 0x4,
+ BUF_DATA_FORMAT_16_16 = 0x5,
+ BUF_DATA_FORMAT_10_11_11 = 0x6,
+ BUF_DATA_FORMAT_11_11_10 = 0x7,
+ BUF_DATA_FORMAT_10_10_10_2 = 0x8,
+ BUF_DATA_FORMAT_2_10_10_10 = 0x9,
+ BUF_DATA_FORMAT_8_8_8_8 = 0xa,
+ BUF_DATA_FORMAT_32_32 = 0xb,
+ BUF_DATA_FORMAT_16_16_16_16 = 0xc,
+ BUF_DATA_FORMAT_32_32_32 = 0xd,
+ BUF_DATA_FORMAT_32_32_32_32 = 0xe,
+ BUF_DATA_FORMAT_RESERVED_15 = 0xf,
+} BUF_DATA_FORMAT;
+typedef enum IMG_DATA_FORMAT {
+ IMG_DATA_FORMAT_INVALID = 0x0,
+ IMG_DATA_FORMAT_8 = 0x1,
+ IMG_DATA_FORMAT_16 = 0x2,
+ IMG_DATA_FORMAT_8_8 = 0x3,
+ IMG_DATA_FORMAT_32 = 0x4,
+ IMG_DATA_FORMAT_16_16 = 0x5,
+ IMG_DATA_FORMAT_10_11_11 = 0x6,
+ IMG_DATA_FORMAT_11_11_10 = 0x7,
+ IMG_DATA_FORMAT_10_10_10_2 = 0x8,
+ IMG_DATA_FORMAT_2_10_10_10 = 0x9,
+ IMG_DATA_FORMAT_8_8_8_8 = 0xa,
+ IMG_DATA_FORMAT_32_32 = 0xb,
+ IMG_DATA_FORMAT_16_16_16_16 = 0xc,
+ IMG_DATA_FORMAT_32_32_32 = 0xd,
+ IMG_DATA_FORMAT_32_32_32_32 = 0xe,
+ IMG_DATA_FORMAT_RESERVED_15 = 0xf,
+ IMG_DATA_FORMAT_5_6_5 = 0x10,
+ IMG_DATA_FORMAT_1_5_5_5 = 0x11,
+ IMG_DATA_FORMAT_5_5_5_1 = 0x12,
+ IMG_DATA_FORMAT_4_4_4_4 = 0x13,
+ IMG_DATA_FORMAT_8_24 = 0x14,
+ IMG_DATA_FORMAT_24_8 = 0x15,
+ IMG_DATA_FORMAT_X24_8_32 = 0x16,
+ IMG_DATA_FORMAT_RESERVED_23 = 0x17,
+ IMG_DATA_FORMAT_RESERVED_24 = 0x18,
+ IMG_DATA_FORMAT_RESERVED_25 = 0x19,
+ IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
+ IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
+ IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
+ IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
+ IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
+ IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
+ IMG_DATA_FORMAT_GB_GR = 0x20,
+ IMG_DATA_FORMAT_BG_RG = 0x21,
+ IMG_DATA_FORMAT_5_9_9_9 = 0x22,
+ IMG_DATA_FORMAT_BC1 = 0x23,
+ IMG_DATA_FORMAT_BC2 = 0x24,
+ IMG_DATA_FORMAT_BC3 = 0x25,
+ IMG_DATA_FORMAT_BC4 = 0x26,
+ IMG_DATA_FORMAT_BC5 = 0x27,
+ IMG_DATA_FORMAT_BC6 = 0x28,
+ IMG_DATA_FORMAT_BC7 = 0x29,
+ IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
+ IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
+ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
+ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
+ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
+ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
+ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
+ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
+ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
+ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
+ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
+ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
+ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
+ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
+ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
+ IMG_DATA_FORMAT_4_4 = 0x39,
+ IMG_DATA_FORMAT_6_5_5 = 0x3a,
+ IMG_DATA_FORMAT_1 = 0x3b,
+ IMG_DATA_FORMAT_1_REVERSED = 0x3c,
+ IMG_DATA_FORMAT_32_AS_8 = 0x3d,
+ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
+ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
+} IMG_DATA_FORMAT;
+typedef enum BUF_NUM_FORMAT {
+ BUF_NUM_FORMAT_UNORM = 0x0,
+ BUF_NUM_FORMAT_SNORM = 0x1,
+ BUF_NUM_FORMAT_USCALED = 0x2,
+ BUF_NUM_FORMAT_SSCALED = 0x3,
+ BUF_NUM_FORMAT_UINT = 0x4,
+ BUF_NUM_FORMAT_SINT = 0x5,
+ BUF_NUM_FORMAT_SNORM_OGL = 0x6,
+ BUF_NUM_FORMAT_FLOAT = 0x7,
+} BUF_NUM_FORMAT;
+typedef enum IMG_NUM_FORMAT {
+ IMG_NUM_FORMAT_UNORM = 0x0,
+ IMG_NUM_FORMAT_SNORM = 0x1,
+ IMG_NUM_FORMAT_USCALED = 0x2,
+ IMG_NUM_FORMAT_SSCALED = 0x3,
+ IMG_NUM_FORMAT_UINT = 0x4,
+ IMG_NUM_FORMAT_SINT = 0x5,
+ IMG_NUM_FORMAT_SNORM_OGL = 0x6,
+ IMG_NUM_FORMAT_FLOAT = 0x7,
+ IMG_NUM_FORMAT_RESERVED_8 = 0x8,
+ IMG_NUM_FORMAT_SRGB = 0x9,
+ IMG_NUM_FORMAT_UBNORM = 0xa,
+ IMG_NUM_FORMAT_UBNORM_OGL = 0xb,
+ IMG_NUM_FORMAT_UBINT = 0xc,
+ IMG_NUM_FORMAT_UBSCALED = 0xd,
+ IMG_NUM_FORMAT_RESERVED_14 = 0xe,
+ IMG_NUM_FORMAT_RESERVED_15 = 0xf,
+} IMG_NUM_FORMAT;
+typedef enum TileType {
+ ARRAY_COLOR_TILE = 0x0,
+ ARRAY_DEPTH_TILE = 0x1,
+} TileType;
+typedef enum NonDispTilingOrder {
+ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
+ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
+} NonDispTilingOrder;
+typedef enum MicroTileMode {
+ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
+ ADDR_SURF_THIN_MICRO_TILING = 0x1,
+ ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
+ ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
+ ADDR_SURF_THICK_MICRO_TILING = 0x4,
+} MicroTileMode;
+typedef enum TileSplit {
+ ADDR_SURF_TILE_SPLIT_64B = 0x0,
+ ADDR_SURF_TILE_SPLIT_128B = 0x1,
+ ADDR_SURF_TILE_SPLIT_256B = 0x2,
+ ADDR_SURF_TILE_SPLIT_512B = 0x3,
+ ADDR_SURF_TILE_SPLIT_1KB = 0x4,
+ ADDR_SURF_TILE_SPLIT_2KB = 0x5,
+ ADDR_SURF_TILE_SPLIT_4KB = 0x6,
+} TileSplit;
+typedef enum SampleSplit {
+ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
+ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
+ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
+ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
+} SampleSplit;
+typedef enum PipeConfig {
+ ADDR_SURF_P2 = 0x0,
+ ADDR_SURF_P2_RESERVED0 = 0x1,
+ ADDR_SURF_P2_RESERVED1 = 0x2,
+ ADDR_SURF_P2_RESERVED2 = 0x3,
+ ADDR_SURF_P4_8x16 = 0x4,
+ ADDR_SURF_P4_16x16 = 0x5,
+ ADDR_SURF_P4_16x32 = 0x6,
+ ADDR_SURF_P4_32x32 = 0x7,
+ ADDR_SURF_P8_16x16_8x16 = 0x8,
+ ADDR_SURF_P8_16x32_8x16 = 0x9,
+ ADDR_SURF_P8_32x32_8x16 = 0xa,
+ ADDR_SURF_P8_16x32_16x16 = 0xb,
+ ADDR_SURF_P8_32x32_16x16 = 0xc,
+ ADDR_SURF_P8_32x32_16x32 = 0xd,
+ ADDR_SURF_P8_32x64_32x32 = 0xe,
+ ADDR_SURF_P8_RESERVED0 = 0xf,
+ ADDR_SURF_P16_32x32_8x16 = 0x10,
+ ADDR_SURF_P16_32x32_16x16 = 0x11,
+} PipeConfig;
+typedef enum NumBanks {
+ ADDR_SURF_2_BANK = 0x0,
+ ADDR_SURF_4_BANK = 0x1,
+ ADDR_SURF_8_BANK = 0x2,
+ ADDR_SURF_16_BANK = 0x3,
+} NumBanks;
+typedef enum BankWidth {
+ ADDR_SURF_BANK_WIDTH_1 = 0x0,
+ ADDR_SURF_BANK_WIDTH_2 = 0x1,
+ ADDR_SURF_BANK_WIDTH_4 = 0x2,
+ ADDR_SURF_BANK_WIDTH_8 = 0x3,
+} BankWidth;
+typedef enum BankHeight {
+ ADDR_SURF_BANK_HEIGHT_1 = 0x0,
+ ADDR_SURF_BANK_HEIGHT_2 = 0x1,
+ ADDR_SURF_BANK_HEIGHT_4 = 0x2,
+ ADDR_SURF_BANK_HEIGHT_8 = 0x3,
+} BankHeight;
+typedef enum BankWidthHeight {
+ ADDR_SURF_BANK_WH_1 = 0x0,
+ ADDR_SURF_BANK_WH_2 = 0x1,
+ ADDR_SURF_BANK_WH_4 = 0x2,
+ ADDR_SURF_BANK_WH_8 = 0x3,
+} BankWidthHeight;
+typedef enum MacroTileAspect {
+ ADDR_SURF_MACRO_ASPECT_1 = 0x0,
+ ADDR_SURF_MACRO_ASPECT_2 = 0x1,
+ ADDR_SURF_MACRO_ASPECT_4 = 0x2,
+ ADDR_SURF_MACRO_ASPECT_8 = 0x3,
+} MacroTileAspect;
+typedef enum TCC_CACHE_POLICIES {
+ TCC_CACHE_POLICY_LRU = 0x0,
+ TCC_CACHE_POLICY_STREAM = 0x1,
+ TCC_CACHE_POLICY_BYPASS = 0x2,
+} TCC_CACHE_POLICIES;
+typedef enum PERFMON_COUNTER_MODE {
+ PERFMON_COUNTER_MODE_ACCUM = 0x0,
+ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
+ PERFMON_COUNTER_MODE_MAX = 0x2,
+ PERFMON_COUNTER_MODE_DIRTY = 0x3,
+ PERFMON_COUNTER_MODE_SAMPLE = 0x4,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
+ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
+ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
+ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
+ PERFMON_COUNTER_MODE_RESERVED = 0xf,
+} PERFMON_COUNTER_MODE;
+typedef enum PERFMON_SPM_MODE {
+ PERFMON_SPM_MODE_OFF = 0x0,
+ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
+ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
+ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
+ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
+ PERFMON_SPM_MODE_RESERVED_5 = 0x5,
+ PERFMON_SPM_MODE_RESERVED_6 = 0x6,
+ PERFMON_SPM_MODE_RESERVED_7 = 0x7,
+ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
+ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
+ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
+} PERFMON_SPM_MODE;
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0x0,
+ ARRAY_TILED = 0x1,
+} SurfaceTiling;
+typedef enum SurfaceArray {
+ ARRAY_1D = 0x0,
+ ARRAY_2D = 0x1,
+ ARRAY_3D = 0x2,
+ ARRAY_3D_SLICE = 0x3,
+} SurfaceArray;
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0x0,
+ ARRAY_2D_COLOR = 0x1,
+ ARRAY_3D_SLICE_COLOR = 0x3,
+} ColorArray;
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0x0,
+ ARRAY_2D_DEPTH = 0x1,
+} DepthArray;
+
+#endif /* SMU_7_1_0_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h
new file mode 100644
index 000000000000..cd7893065a4b
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h
@@ -0,0 +1,5648 @@
+/*
+ * SMU_7_1_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef SMU_7_1_0_SH_MASK_H
+#define SMU_7_1_0_SH_MASK_H
+
+#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
+#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1
+#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0
+#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2
+#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1
+#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f
+#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1
+#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0
+#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2
+#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1
+#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f
+#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1
+#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0
+#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2
+#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1
+#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f
+#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1
+#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0
+#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2
+#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1
+#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4
+#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2
+#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
+#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3
+#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10
+#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4
+#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20
+#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5
+#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40
+#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6
+#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80
+#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7
+#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100
+#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
+#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200
+#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9
+#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400
+#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa
+#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800
+#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb
+#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000
+#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc
+#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1
+#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2
+#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1
+#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4
+#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4
+#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0
+#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14
+#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000
+#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b
+#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000
+#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17
+#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a
+#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e
+#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff
+#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000
+#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fe00
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9
+#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000
+#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15
+#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17
+#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f
+#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1
+#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2
+#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1
+#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc
+#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2
+#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30
+#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8
+#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200
+#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15
+#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
+#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
+#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
+#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
+#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
+#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2
+#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1
+#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4
+#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2
+#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8
+#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3
+#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10
+#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4
+#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00
+#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa
+#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000
+#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc
+#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000
+#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c
+#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000
+#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d
+#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1
+#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0
+#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0
+#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4
+#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff
+#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0
+#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00
+#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8
+#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2
+#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1
+#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4
+#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2
+#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1
+#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0
+#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8
+#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3
+#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100
+#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8
+#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000
+#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe
+#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000
+#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf
+#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000
+#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10
+#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000
+#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11
+#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000
+#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12
+#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000
+#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13
+#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000
+#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14
+#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000
+#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15
+#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000
+#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16
+#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000
+#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18
+#define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1
+#define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0
+#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6
+#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1
+#define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00
+#define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa
+#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff
+#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0
+#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00
+#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8
+#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000
+#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10
+#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff
+#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0
+#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00
+#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8
+#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000
+#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10
+#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f
+#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
+#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0
+#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5
+#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00
+#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa
+#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000
+#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11
+#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000
+#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12
+#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000
+#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3
+#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0
+#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9
+#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b
+#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7
+#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_0__SMC_RESP_MASK 0xffff
+#define SMC_RESP_0__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_1__SMC_RESP_MASK 0xffff
+#define SMC_RESP_1__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_2__SMC_RESP_MASK 0xffff
+#define SMC_RESP_2__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_3__SMC_RESP_MASK 0xffff
+#define SMC_RESP_3__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_4__SMC_RESP_MASK 0xffff
+#define SMC_RESP_4__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_5__SMC_RESP_MASK 0xffff
+#define SMC_RESP_5__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_6__SMC_RESP_MASK 0xffff
+#define SMC_RESP_6__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_7__SMC_RESP_MASK 0xffff
+#define SMC_RESP_7__SMC_RESP__SHIFT 0x0
+#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_8__SMC_RESP_MASK 0xffff
+#define SMC_RESP_8__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_9__SMC_RESP_MASK 0xffff
+#define SMC_RESP_9__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_10__SMC_RESP_MASK 0xffff
+#define SMC_RESP_10__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_11__SMC_RESP_MASK 0xffff
+#define SMC_RESP_11__SMC_RESP__SHIFT 0x0
+#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1
+#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0
+#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2
+#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1
+#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000
+#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e
+#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1
+#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8
+#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000
+#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18
+#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1
+#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0
+#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff
+#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0
+#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff
+#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0
+#define SMC_PC_C__smc_pc_c_MASK 0xffffffff
+#define SMC_PC_C__smc_pc_c__SHIFT 0x0
+#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff
+#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0
+#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1
+#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0
+#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf
+#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0
+#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0
+#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4
+#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff
+#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0
+#define GPIOPAD_A__GPIO_A_MASK 0x7fffffff
+#define GPIOPAD_A__GPIO_A__SHIFT 0x0
+#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff
+#define GPIOPAD_EN__GPIO_EN__SHIFT 0x0
+#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff
+#define GPIOPAD_Y__GPIO_Y__SHIFT 0x0
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e
+#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff
+#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0
+#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000
+#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f
+#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff
+#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0
+#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000
+#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c
+#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000
+#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f
+#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff
+#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0
+#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000
+#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f
+#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff
+#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0
+#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000
+#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f
+#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff
+#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0
+#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000
+#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6
+#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff
+#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0
+#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff
+#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0
+#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff
+#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0
+#define CG_FPS_CNT__FPS_CNT_MASK 0xff
+#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0
+#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1
+#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0
+#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2
+#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1
+#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4
+#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2
+#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8
+#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3
+#define RCU_UC_EVENTS__TP_Tester_MASK 0x40
+#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6
+#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80
+#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7
+#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100
+#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8
+#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200
+#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9
+#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400
+#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa
+#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800
+#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb
+#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000
+#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd
+#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000
+#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10
+#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000
+#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11
+#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000
+#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12
+#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000
+#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13
+#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000
+#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18
+#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2
+#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1
+#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8
+#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3
+#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10
+#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4
+#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20
+#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5
+#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100
+#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8
+#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000
+#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10
+#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000
+#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11
+#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000
+#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16
+#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000
+#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17
+#define CC_RCU_FUSES__GPU_DIS_MASK 0x2
+#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1
+#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4
+#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2
+#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10
+#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4
+#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20
+#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5
+#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40
+#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6
+#define CC_RCU_FUSES__ROM_DIS_MASK 0x80
+#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7
+#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100
+#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8
+#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200
+#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9
+#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400
+#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa
+#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x4000
+#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0xe
+#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x8000
+#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xf
+#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x10000
+#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0x10
+#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x20000
+#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x11
+#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x40000
+#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x12
+#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x80000
+#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x13
+#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x100000
+#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x14
+#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x400000
+#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x16
+#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x800000
+#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x17
+#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x1000000
+#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x18
+#define CC_RCU_FUSES__RCU_SPARE_MASK 0xfe000000
+#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x19
+#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2
+#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1
+#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc
+#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2
+#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600
+#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9
+#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800
+#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17
+#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000
+#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b
+#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000
+#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c
+#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000
+#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d
+#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff
+#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0
+#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00
+#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8
+#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000
+#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10
+#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000
+#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18
+#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe
+#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1
+#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e
+#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1
+#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e
+#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1
+#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40
+#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6
+#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80
+#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7
+#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100
+#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8
+#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200
+#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9
+#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400
+#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa
+#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800
+#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd
+#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000
+#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18
+#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000
+#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19
+#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000
+#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a
+#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0
+#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4
+#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000
+#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14
+#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000
+#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18
+#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2
+#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1
+#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff
+#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0
+#define SMU_STATUS__SMU_DONE_MASK 0x1
+#define SMU_STATUS__SMU_DONE__SHIFT 0x0
+#define SMU_STATUS__SMU_PASS_MASK 0x2
+#define SMU_STATUS__SMU_PASS__SHIFT 0x1
+#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1
+#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0
+#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6
+#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1
+#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8
+#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3
+#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10
+#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4
+#define SMU_FIRMWARE__SMU_counter_MASK 0xf00
+#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8
+#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000
+#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10
+#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000
+#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11
+#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff
+#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0
+#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000
+#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f
+#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff
+#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0
+#define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff
+#define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0
+#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff
+#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0
+#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff
+#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0
+#define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff
+#define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0
+#define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff
+#define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0
+#define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff
+#define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0
+#define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff
+#define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0
+#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff
+#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0
+#define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff
+#define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0
+#define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff
+#define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0
+#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff
+#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0
+#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff
+#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0
+#define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff
+#define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0
+#define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff
+#define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0
+#define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff
+#define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0
+#define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff
+#define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0
+#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff
+#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0
+#define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff
+#define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0
+#define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff
+#define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0
+#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff
+#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0
+#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff
+#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0
+#define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff
+#define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0
+#define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff
+#define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0
+#define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff
+#define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0
+#define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff
+#define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0
+#define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff
+#define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0
+#define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff
+#define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0
+#define DPM_TABLE_28__SystemFlags_MASK 0xffffffff
+#define DPM_TABLE_28__SystemFlags__SHIFT 0x0
+#define DPM_TABLE_29__SmioMaskVddcVid_MASK 0xffffffff
+#define DPM_TABLE_29__SmioMaskVddcVid__SHIFT 0x0
+#define DPM_TABLE_30__SmioMaskVddcPhase_MASK 0xffffffff
+#define DPM_TABLE_30__SmioMaskVddcPhase__SHIFT 0x0
+#define DPM_TABLE_31__SmioMaskVddciVid_MASK 0xffffffff
+#define DPM_TABLE_31__SmioMaskVddciVid__SHIFT 0x0
+#define DPM_TABLE_32__SmioMaskMvddVid_MASK 0xffffffff
+#define DPM_TABLE_32__SmioMaskMvddVid__SHIFT 0x0
+#define DPM_TABLE_33__VddcLevelCount_MASK 0xffffffff
+#define DPM_TABLE_33__VddcLevelCount__SHIFT 0x0
+#define DPM_TABLE_34__VddciLevelCount_MASK 0xffffffff
+#define DPM_TABLE_34__VddciLevelCount__SHIFT 0x0
+#define DPM_TABLE_35__MvddLevelCount_MASK 0xffffffff
+#define DPM_TABLE_35__MvddLevelCount__SHIFT 0x0
+#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_36__VddcLevel_0_Voltage_MASK 0xffff0000
+#define DPM_TABLE_36__VddcLevel_0_Voltage__SHIFT 0x10
+#define DPM_TABLE_37__VddcLevel_0_padding_MASK 0xff
+#define DPM_TABLE_37__VddcLevel_0_padding__SHIFT 0x0
+#define DPM_TABLE_37__VddcLevel_0_Smio_MASK 0xff00
+#define DPM_TABLE_37__VddcLevel_0_Smio__SHIFT 0x8
+#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_38__VddcLevel_1_Voltage_MASK 0xffff0000
+#define DPM_TABLE_38__VddcLevel_1_Voltage__SHIFT 0x10
+#define DPM_TABLE_39__VddcLevel_1_padding_MASK 0xff
+#define DPM_TABLE_39__VddcLevel_1_padding__SHIFT 0x0
+#define DPM_TABLE_39__VddcLevel_1_Smio_MASK 0xff00
+#define DPM_TABLE_39__VddcLevel_1_Smio__SHIFT 0x8
+#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_40__VddcLevel_2_Voltage_MASK 0xffff0000
+#define DPM_TABLE_40__VddcLevel_2_Voltage__SHIFT 0x10
+#define DPM_TABLE_41__VddcLevel_2_padding_MASK 0xff
+#define DPM_TABLE_41__VddcLevel_2_padding__SHIFT 0x0
+#define DPM_TABLE_41__VddcLevel_2_Smio_MASK 0xff00
+#define DPM_TABLE_41__VddcLevel_2_Smio__SHIFT 0x8
+#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_42__VddcLevel_3_Voltage_MASK 0xffff0000
+#define DPM_TABLE_42__VddcLevel_3_Voltage__SHIFT 0x10
+#define DPM_TABLE_43__VddcLevel_3_padding_MASK 0xff
+#define DPM_TABLE_43__VddcLevel_3_padding__SHIFT 0x0
+#define DPM_TABLE_43__VddcLevel_3_Smio_MASK 0xff00
+#define DPM_TABLE_43__VddcLevel_3_Smio__SHIFT 0x8
+#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_44__VddcLevel_4_Voltage_MASK 0xffff0000
+#define DPM_TABLE_44__VddcLevel_4_Voltage__SHIFT 0x10
+#define DPM_TABLE_45__VddcLevel_4_padding_MASK 0xff
+#define DPM_TABLE_45__VddcLevel_4_padding__SHIFT 0x0
+#define DPM_TABLE_45__VddcLevel_4_Smio_MASK 0xff00
+#define DPM_TABLE_45__VddcLevel_4_Smio__SHIFT 0x8
+#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_46__VddcLevel_5_Voltage_MASK 0xffff0000
+#define DPM_TABLE_46__VddcLevel_5_Voltage__SHIFT 0x10
+#define DPM_TABLE_47__VddcLevel_5_padding_MASK 0xff
+#define DPM_TABLE_47__VddcLevel_5_padding__SHIFT 0x0
+#define DPM_TABLE_47__VddcLevel_5_Smio_MASK 0xff00
+#define DPM_TABLE_47__VddcLevel_5_Smio__SHIFT 0x8
+#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_48__VddcLevel_6_Voltage_MASK 0xffff0000
+#define DPM_TABLE_48__VddcLevel_6_Voltage__SHIFT 0x10
+#define DPM_TABLE_49__VddcLevel_6_padding_MASK 0xff
+#define DPM_TABLE_49__VddcLevel_6_padding__SHIFT 0x0
+#define DPM_TABLE_49__VddcLevel_6_Smio_MASK 0xff00
+#define DPM_TABLE_49__VddcLevel_6_Smio__SHIFT 0x8
+#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_50__VddcLevel_7_Voltage_MASK 0xffff0000
+#define DPM_TABLE_50__VddcLevel_7_Voltage__SHIFT 0x10
+#define DPM_TABLE_51__VddcLevel_7_padding_MASK 0xff
+#define DPM_TABLE_51__VddcLevel_7_padding__SHIFT 0x0
+#define DPM_TABLE_51__VddcLevel_7_Smio_MASK 0xff00
+#define DPM_TABLE_51__VddcLevel_7_Smio__SHIFT 0x8
+#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_52__VddciLevel_0_Voltage_MASK 0xffff0000
+#define DPM_TABLE_52__VddciLevel_0_Voltage__SHIFT 0x10
+#define DPM_TABLE_53__VddciLevel_0_padding_MASK 0xff
+#define DPM_TABLE_53__VddciLevel_0_padding__SHIFT 0x0
+#define DPM_TABLE_53__VddciLevel_0_Smio_MASK 0xff00
+#define DPM_TABLE_53__VddciLevel_0_Smio__SHIFT 0x8
+#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_54__VddciLevel_1_Voltage_MASK 0xffff0000
+#define DPM_TABLE_54__VddciLevel_1_Voltage__SHIFT 0x10
+#define DPM_TABLE_55__VddciLevel_1_padding_MASK 0xff
+#define DPM_TABLE_55__VddciLevel_1_padding__SHIFT 0x0
+#define DPM_TABLE_55__VddciLevel_1_Smio_MASK 0xff00
+#define DPM_TABLE_55__VddciLevel_1_Smio__SHIFT 0x8
+#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_56__VddciLevel_2_Voltage_MASK 0xffff0000
+#define DPM_TABLE_56__VddciLevel_2_Voltage__SHIFT 0x10
+#define DPM_TABLE_57__VddciLevel_2_padding_MASK 0xff
+#define DPM_TABLE_57__VddciLevel_2_padding__SHIFT 0x0
+#define DPM_TABLE_57__VddciLevel_2_Smio_MASK 0xff00
+#define DPM_TABLE_57__VddciLevel_2_Smio__SHIFT 0x8
+#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_58__VddciLevel_3_Voltage_MASK 0xffff0000
+#define DPM_TABLE_58__VddciLevel_3_Voltage__SHIFT 0x10
+#define DPM_TABLE_59__VddciLevel_3_padding_MASK 0xff
+#define DPM_TABLE_59__VddciLevel_3_padding__SHIFT 0x0
+#define DPM_TABLE_59__VddciLevel_3_Smio_MASK 0xff00
+#define DPM_TABLE_59__VddciLevel_3_Smio__SHIFT 0x8
+#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_60__MvddLevel_0_Voltage_MASK 0xffff0000
+#define DPM_TABLE_60__MvddLevel_0_Voltage__SHIFT 0x10
+#define DPM_TABLE_61__MvddLevel_0_padding_MASK 0xff
+#define DPM_TABLE_61__MvddLevel_0_padding__SHIFT 0x0
+#define DPM_TABLE_61__MvddLevel_0_Smio_MASK 0xff00
+#define DPM_TABLE_61__MvddLevel_0_Smio__SHIFT 0x8
+#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_62__MvddLevel_1_Voltage_MASK 0xffff0000
+#define DPM_TABLE_62__MvddLevel_1_Voltage__SHIFT 0x10
+#define DPM_TABLE_63__MvddLevel_1_padding_MASK 0xff
+#define DPM_TABLE_63__MvddLevel_1_padding__SHIFT 0x0
+#define DPM_TABLE_63__MvddLevel_1_Smio_MASK 0xff00
+#define DPM_TABLE_63__MvddLevel_1_Smio__SHIFT 0x8
+#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_64__MvddLevel_2_Voltage_MASK 0xffff0000
+#define DPM_TABLE_64__MvddLevel_2_Voltage__SHIFT 0x10
+#define DPM_TABLE_65__MvddLevel_2_padding_MASK 0xff
+#define DPM_TABLE_65__MvddLevel_2_padding__SHIFT 0x0
+#define DPM_TABLE_65__MvddLevel_2_Smio_MASK 0xff00
+#define DPM_TABLE_65__MvddLevel_2_Smio__SHIFT 0x8
+#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_66__MvddLevel_3_Voltage_MASK 0xffff0000
+#define DPM_TABLE_66__MvddLevel_3_Voltage__SHIFT 0x10
+#define DPM_TABLE_67__MvddLevel_3_padding_MASK 0xff
+#define DPM_TABLE_67__MvddLevel_3_padding__SHIFT 0x0
+#define DPM_TABLE_67__MvddLevel_3_Smio_MASK 0xff00
+#define DPM_TABLE_67__MvddLevel_3_Smio__SHIFT 0x8
+#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_68__UvdLevelCount_MASK 0xff
+#define DPM_TABLE_68__UvdLevelCount__SHIFT 0x0
+#define DPM_TABLE_68__LinkLevelCount_MASK 0xff00
+#define DPM_TABLE_68__LinkLevelCount__SHIFT 0x8
+#define DPM_TABLE_68__MemoryDpmLevelCount_MASK 0xff0000
+#define DPM_TABLE_68__MemoryDpmLevelCount__SHIFT 0x10
+#define DPM_TABLE_68__GraphicsDpmLevelCount_MASK 0xff000000
+#define DPM_TABLE_68__GraphicsDpmLevelCount__SHIFT 0x18
+#define DPM_TABLE_69__MasterDeepSleepControl_MASK 0xff
+#define DPM_TABLE_69__MasterDeepSleepControl__SHIFT 0x0
+#define DPM_TABLE_69__SamuLevelCount_MASK 0xff00
+#define DPM_TABLE_69__SamuLevelCount__SHIFT 0x8
+#define DPM_TABLE_69__AcpLevelCount_MASK 0xff0000
+#define DPM_TABLE_69__AcpLevelCount__SHIFT 0x10
+#define DPM_TABLE_69__VceLevelCount_MASK 0xff000000
+#define DPM_TABLE_69__VceLevelCount__SHIFT 0x18
+#define DPM_TABLE_70__DefaultTdp_MASK 0xffff
+#define DPM_TABLE_70__DefaultTdp__SHIFT 0x0
+#define DPM_TABLE_70__TargetTdp_MASK 0xffff0000
+#define DPM_TABLE_70__TargetTdp__SHIFT 0x10
+#define DPM_TABLE_71__Reserved_1_MASK 0xffffffff
+#define DPM_TABLE_71__Reserved_1__SHIFT 0x0
+#define DPM_TABLE_72__Reserved_2_MASK 0xffffffff
+#define DPM_TABLE_72__Reserved_2__SHIFT 0x0
+#define DPM_TABLE_73__Reserved_3_MASK 0xffffffff
+#define DPM_TABLE_73__Reserved_3__SHIFT 0x0
+#define DPM_TABLE_74__Reserved_4_MASK 0xffffffff
+#define DPM_TABLE_74__Reserved_4__SHIFT 0x0
+#define DPM_TABLE_75__GraphicsLevel_0_Flags_MASK 0xffffffff
+#define DPM_TABLE_75__GraphicsLevel_0_Flags__SHIFT 0x0
+#define DPM_TABLE_76__GraphicsLevel_0_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_76__GraphicsLevel_0_MinVddc__SHIFT 0x0
+#define DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_78__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_78__GraphicsLevel_0_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_79__GraphicsLevel_0_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_79__GraphicsLevel_0_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_79__GraphicsLevel_0_padding1_MASK 0xff0000
+#define DPM_TABLE_79__GraphicsLevel_0_padding1__SHIFT 0x10
+#define DPM_TABLE_79__GraphicsLevel_0_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_79__GraphicsLevel_0_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_86__GraphicsLevel_0_SclkDid_MASK 0xff000000
+#define DPM_TABLE_86__GraphicsLevel_0_SclkDid__SHIFT 0x18
+#define DPM_TABLE_87__GraphicsLevel_0_PowerThrottle_MASK 0xff
+#define DPM_TABLE_87__GraphicsLevel_0_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_87__GraphicsLevel_0_DownHyst_MASK 0xff0000
+#define DPM_TABLE_87__GraphicsLevel_0_DownHyst__SHIFT 0x10
+#define DPM_TABLE_87__GraphicsLevel_0_UpHyst_MASK 0xff000000
+#define DPM_TABLE_87__GraphicsLevel_0_UpHyst__SHIFT 0x18
+#define DPM_TABLE_88__GraphicsLevel_0_padding_2_MASK 0xff
+#define DPM_TABLE_88__GraphicsLevel_0_padding_2__SHIFT 0x0
+#define DPM_TABLE_88__GraphicsLevel_0_padding_1_MASK 0xff00
+#define DPM_TABLE_88__GraphicsLevel_0_padding_1__SHIFT 0x8
+#define DPM_TABLE_88__GraphicsLevel_0_padding_0_MASK 0xff0000
+#define DPM_TABLE_88__GraphicsLevel_0_padding_0__SHIFT 0x10
+#define DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId_MASK 0xff000000
+#define DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x18
+#define DPM_TABLE_89__GraphicsLevel_1_Flags_MASK 0xffffffff
+#define DPM_TABLE_89__GraphicsLevel_1_Flags__SHIFT 0x0
+#define DPM_TABLE_90__GraphicsLevel_1_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_90__GraphicsLevel_1_MinVddc__SHIFT 0x0
+#define DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_92__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_92__GraphicsLevel_1_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_93__GraphicsLevel_1_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_93__GraphicsLevel_1_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_93__GraphicsLevel_1_padding1_MASK 0xff0000
+#define DPM_TABLE_93__GraphicsLevel_1_padding1__SHIFT 0x10
+#define DPM_TABLE_93__GraphicsLevel_1_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_93__GraphicsLevel_1_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_100__GraphicsLevel_1_SclkDid_MASK 0xff000000
+#define DPM_TABLE_100__GraphicsLevel_1_SclkDid__SHIFT 0x18
+#define DPM_TABLE_101__GraphicsLevel_1_PowerThrottle_MASK 0xff
+#define DPM_TABLE_101__GraphicsLevel_1_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_101__GraphicsLevel_1_DownHyst_MASK 0xff0000
+#define DPM_TABLE_101__GraphicsLevel_1_DownHyst__SHIFT 0x10
+#define DPM_TABLE_101__GraphicsLevel_1_UpHyst_MASK 0xff000000
+#define DPM_TABLE_101__GraphicsLevel_1_UpHyst__SHIFT 0x18
+#define DPM_TABLE_102__GraphicsLevel_1_padding_2_MASK 0xff
+#define DPM_TABLE_102__GraphicsLevel_1_padding_2__SHIFT 0x0
+#define DPM_TABLE_102__GraphicsLevel_1_padding_1_MASK 0xff00
+#define DPM_TABLE_102__GraphicsLevel_1_padding_1__SHIFT 0x8
+#define DPM_TABLE_102__GraphicsLevel_1_padding_0_MASK 0xff0000
+#define DPM_TABLE_102__GraphicsLevel_1_padding_0__SHIFT 0x10
+#define DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId_MASK 0xff000000
+#define DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x18
+#define DPM_TABLE_103__GraphicsLevel_2_Flags_MASK 0xffffffff
+#define DPM_TABLE_103__GraphicsLevel_2_Flags__SHIFT 0x0
+#define DPM_TABLE_104__GraphicsLevel_2_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_104__GraphicsLevel_2_MinVddc__SHIFT 0x0
+#define DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_106__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_106__GraphicsLevel_2_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_107__GraphicsLevel_2_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_107__GraphicsLevel_2_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_107__GraphicsLevel_2_padding1_MASK 0xff0000
+#define DPM_TABLE_107__GraphicsLevel_2_padding1__SHIFT 0x10
+#define DPM_TABLE_107__GraphicsLevel_2_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_107__GraphicsLevel_2_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_114__GraphicsLevel_2_SclkDid_MASK 0xff000000
+#define DPM_TABLE_114__GraphicsLevel_2_SclkDid__SHIFT 0x18
+#define DPM_TABLE_115__GraphicsLevel_2_PowerThrottle_MASK 0xff
+#define DPM_TABLE_115__GraphicsLevel_2_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_115__GraphicsLevel_2_DownHyst_MASK 0xff0000
+#define DPM_TABLE_115__GraphicsLevel_2_DownHyst__SHIFT 0x10
+#define DPM_TABLE_115__GraphicsLevel_2_UpHyst_MASK 0xff000000
+#define DPM_TABLE_115__GraphicsLevel_2_UpHyst__SHIFT 0x18
+#define DPM_TABLE_116__GraphicsLevel_2_padding_2_MASK 0xff
+#define DPM_TABLE_116__GraphicsLevel_2_padding_2__SHIFT 0x0
+#define DPM_TABLE_116__GraphicsLevel_2_padding_1_MASK 0xff00
+#define DPM_TABLE_116__GraphicsLevel_2_padding_1__SHIFT 0x8
+#define DPM_TABLE_116__GraphicsLevel_2_padding_0_MASK 0xff0000
+#define DPM_TABLE_116__GraphicsLevel_2_padding_0__SHIFT 0x10
+#define DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId_MASK 0xff000000
+#define DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x18
+#define DPM_TABLE_117__GraphicsLevel_3_Flags_MASK 0xffffffff
+#define DPM_TABLE_117__GraphicsLevel_3_Flags__SHIFT 0x0
+#define DPM_TABLE_118__GraphicsLevel_3_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_118__GraphicsLevel_3_MinVddc__SHIFT 0x0
+#define DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_120__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_120__GraphicsLevel_3_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_121__GraphicsLevel_3_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_121__GraphicsLevel_3_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_121__GraphicsLevel_3_padding1_MASK 0xff0000
+#define DPM_TABLE_121__GraphicsLevel_3_padding1__SHIFT 0x10
+#define DPM_TABLE_121__GraphicsLevel_3_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_121__GraphicsLevel_3_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_128__GraphicsLevel_3_SclkDid_MASK 0xff000000
+#define DPM_TABLE_128__GraphicsLevel_3_SclkDid__SHIFT 0x18
+#define DPM_TABLE_129__GraphicsLevel_3_PowerThrottle_MASK 0xff
+#define DPM_TABLE_129__GraphicsLevel_3_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_129__GraphicsLevel_3_DownHyst_MASK 0xff0000
+#define DPM_TABLE_129__GraphicsLevel_3_DownHyst__SHIFT 0x10
+#define DPM_TABLE_129__GraphicsLevel_3_UpHyst_MASK 0xff000000
+#define DPM_TABLE_129__GraphicsLevel_3_UpHyst__SHIFT 0x18
+#define DPM_TABLE_130__GraphicsLevel_3_padding_2_MASK 0xff
+#define DPM_TABLE_130__GraphicsLevel_3_padding_2__SHIFT 0x0
+#define DPM_TABLE_130__GraphicsLevel_3_padding_1_MASK 0xff00
+#define DPM_TABLE_130__GraphicsLevel_3_padding_1__SHIFT 0x8
+#define DPM_TABLE_130__GraphicsLevel_3_padding_0_MASK 0xff0000
+#define DPM_TABLE_130__GraphicsLevel_3_padding_0__SHIFT 0x10
+#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId_MASK 0xff000000
+#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x18
+#define DPM_TABLE_131__GraphicsLevel_4_Flags_MASK 0xffffffff
+#define DPM_TABLE_131__GraphicsLevel_4_Flags__SHIFT 0x0
+#define DPM_TABLE_132__GraphicsLevel_4_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_132__GraphicsLevel_4_MinVddc__SHIFT 0x0
+#define DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_134__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_134__GraphicsLevel_4_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_135__GraphicsLevel_4_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_135__GraphicsLevel_4_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_135__GraphicsLevel_4_padding1_MASK 0xff0000
+#define DPM_TABLE_135__GraphicsLevel_4_padding1__SHIFT 0x10
+#define DPM_TABLE_135__GraphicsLevel_4_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_135__GraphicsLevel_4_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_142__GraphicsLevel_4_SclkDid_MASK 0xff000000
+#define DPM_TABLE_142__GraphicsLevel_4_SclkDid__SHIFT 0x18
+#define DPM_TABLE_143__GraphicsLevel_4_PowerThrottle_MASK 0xff
+#define DPM_TABLE_143__GraphicsLevel_4_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_143__GraphicsLevel_4_DownHyst_MASK 0xff0000
+#define DPM_TABLE_143__GraphicsLevel_4_DownHyst__SHIFT 0x10
+#define DPM_TABLE_143__GraphicsLevel_4_UpHyst_MASK 0xff000000
+#define DPM_TABLE_143__GraphicsLevel_4_UpHyst__SHIFT 0x18
+#define DPM_TABLE_144__GraphicsLevel_4_padding_2_MASK 0xff
+#define DPM_TABLE_144__GraphicsLevel_4_padding_2__SHIFT 0x0
+#define DPM_TABLE_144__GraphicsLevel_4_padding_1_MASK 0xff00
+#define DPM_TABLE_144__GraphicsLevel_4_padding_1__SHIFT 0x8
+#define DPM_TABLE_144__GraphicsLevel_4_padding_0_MASK 0xff0000
+#define DPM_TABLE_144__GraphicsLevel_4_padding_0__SHIFT 0x10
+#define DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId_MASK 0xff000000
+#define DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x18
+#define DPM_TABLE_145__GraphicsLevel_5_Flags_MASK 0xffffffff
+#define DPM_TABLE_145__GraphicsLevel_5_Flags__SHIFT 0x0
+#define DPM_TABLE_146__GraphicsLevel_5_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_146__GraphicsLevel_5_MinVddc__SHIFT 0x0
+#define DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_148__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_148__GraphicsLevel_5_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_149__GraphicsLevel_5_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_149__GraphicsLevel_5_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_149__GraphicsLevel_5_padding1_MASK 0xff0000
+#define DPM_TABLE_149__GraphicsLevel_5_padding1__SHIFT 0x10
+#define DPM_TABLE_149__GraphicsLevel_5_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_149__GraphicsLevel_5_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_156__GraphicsLevel_5_SclkDid_MASK 0xff000000
+#define DPM_TABLE_156__GraphicsLevel_5_SclkDid__SHIFT 0x18
+#define DPM_TABLE_157__GraphicsLevel_5_PowerThrottle_MASK 0xff
+#define DPM_TABLE_157__GraphicsLevel_5_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_157__GraphicsLevel_5_DownHyst_MASK 0xff0000
+#define DPM_TABLE_157__GraphicsLevel_5_DownHyst__SHIFT 0x10
+#define DPM_TABLE_157__GraphicsLevel_5_UpHyst_MASK 0xff000000
+#define DPM_TABLE_157__GraphicsLevel_5_UpHyst__SHIFT 0x18
+#define DPM_TABLE_158__GraphicsLevel_5_padding_2_MASK 0xff
+#define DPM_TABLE_158__GraphicsLevel_5_padding_2__SHIFT 0x0
+#define DPM_TABLE_158__GraphicsLevel_5_padding_1_MASK 0xff00
+#define DPM_TABLE_158__GraphicsLevel_5_padding_1__SHIFT 0x8
+#define DPM_TABLE_158__GraphicsLevel_5_padding_0_MASK 0xff0000
+#define DPM_TABLE_158__GraphicsLevel_5_padding_0__SHIFT 0x10
+#define DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId_MASK 0xff000000
+#define DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x18
+#define DPM_TABLE_159__GraphicsLevel_6_Flags_MASK 0xffffffff
+#define DPM_TABLE_159__GraphicsLevel_6_Flags__SHIFT 0x0
+#define DPM_TABLE_160__GraphicsLevel_6_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_160__GraphicsLevel_6_MinVddc__SHIFT 0x0
+#define DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_163__GraphicsLevel_6_padding1_MASK 0xff0000
+#define DPM_TABLE_163__GraphicsLevel_6_padding1__SHIFT 0x10
+#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_170__GraphicsLevel_6_SclkDid_MASK 0xff000000
+#define DPM_TABLE_170__GraphicsLevel_6_SclkDid__SHIFT 0x18
+#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle_MASK 0xff
+#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_171__GraphicsLevel_6_DownHyst_MASK 0xff0000
+#define DPM_TABLE_171__GraphicsLevel_6_DownHyst__SHIFT 0x10
+#define DPM_TABLE_171__GraphicsLevel_6_UpHyst_MASK 0xff000000
+#define DPM_TABLE_171__GraphicsLevel_6_UpHyst__SHIFT 0x18
+#define DPM_TABLE_172__GraphicsLevel_6_padding_2_MASK 0xff
+#define DPM_TABLE_172__GraphicsLevel_6_padding_2__SHIFT 0x0
+#define DPM_TABLE_172__GraphicsLevel_6_padding_1_MASK 0xff00
+#define DPM_TABLE_172__GraphicsLevel_6_padding_1__SHIFT 0x8
+#define DPM_TABLE_172__GraphicsLevel_6_padding_0_MASK 0xff0000
+#define DPM_TABLE_172__GraphicsLevel_6_padding_0__SHIFT 0x10
+#define DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId_MASK 0xff000000
+#define DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x18
+#define DPM_TABLE_173__GraphicsLevel_7_Flags_MASK 0xffffffff
+#define DPM_TABLE_173__GraphicsLevel_7_Flags__SHIFT 0x0
+#define DPM_TABLE_174__GraphicsLevel_7_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_174__GraphicsLevel_7_MinVddc__SHIFT 0x0
+#define DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_176__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_176__GraphicsLevel_7_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_177__GraphicsLevel_7_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_177__GraphicsLevel_7_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_177__GraphicsLevel_7_padding1_MASK 0xff0000
+#define DPM_TABLE_177__GraphicsLevel_7_padding1__SHIFT 0x10
+#define DPM_TABLE_177__GraphicsLevel_7_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_177__GraphicsLevel_7_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_184__GraphicsLevel_7_SclkDid_MASK 0xff000000
+#define DPM_TABLE_184__GraphicsLevel_7_SclkDid__SHIFT 0x18
+#define DPM_TABLE_185__GraphicsLevel_7_PowerThrottle_MASK 0xff
+#define DPM_TABLE_185__GraphicsLevel_7_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_185__GraphicsLevel_7_DownHyst_MASK 0xff0000
+#define DPM_TABLE_185__GraphicsLevel_7_DownHyst__SHIFT 0x10
+#define DPM_TABLE_185__GraphicsLevel_7_UpHyst_MASK 0xff000000
+#define DPM_TABLE_185__GraphicsLevel_7_UpHyst__SHIFT 0x18
+#define DPM_TABLE_186__GraphicsLevel_7_padding_2_MASK 0xff
+#define DPM_TABLE_186__GraphicsLevel_7_padding_2__SHIFT 0x0
+#define DPM_TABLE_186__GraphicsLevel_7_padding_1_MASK 0xff00
+#define DPM_TABLE_186__GraphicsLevel_7_padding_1__SHIFT 0x8
+#define DPM_TABLE_186__GraphicsLevel_7_padding_0_MASK 0xff0000
+#define DPM_TABLE_186__GraphicsLevel_7_padding_0__SHIFT 0x10
+#define DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId_MASK 0xff000000
+#define DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x18
+#define DPM_TABLE_187__MemoryACPILevel_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_187__MemoryACPILevel_MinVddc__SHIFT 0x0
+#define DPM_TABLE_188__MemoryACPILevel_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_188__MemoryACPILevel_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_189__MemoryACPILevel_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_189__MemoryACPILevel_MinVddci__SHIFT 0x0
+#define DPM_TABLE_190__MemoryACPILevel_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_190__MemoryACPILevel_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_191__MemoryACPILevel_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_191__MemoryACPILevel_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_192__MemoryACPILevel_StutterEnable_MASK 0xff
+#define DPM_TABLE_192__MemoryACPILevel_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_192__MemoryACPILevel_RttEnable_MASK 0xff00
+#define DPM_TABLE_192__MemoryACPILevel_RttEnable__SHIFT 0x8
+#define DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_192__MemoryACPILevel_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_192__MemoryACPILevel_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_193__MemoryACPILevel_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_193__MemoryACPILevel_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_193__MemoryACPILevel_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_193__MemoryACPILevel_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_193__MemoryACPILevel_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_193__MemoryACPILevel_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_194__MemoryACPILevel_padding_MASK 0xff
+#define DPM_TABLE_194__MemoryACPILevel_padding__SHIFT 0x0
+#define DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_194__MemoryACPILevel_DownHyst_MASK 0xff0000
+#define DPM_TABLE_194__MemoryACPILevel_DownHyst__SHIFT 0x10
+#define DPM_TABLE_194__MemoryACPILevel_UpHyst_MASK 0xff000000
+#define DPM_TABLE_194__MemoryACPILevel_UpHyst__SHIFT 0x18
+#define DPM_TABLE_195__MemoryACPILevel_padding1_MASK 0xff
+#define DPM_TABLE_195__MemoryACPILevel_padding1__SHIFT 0x0
+#define DPM_TABLE_195__MemoryACPILevel_DisplayWatermark_MASK 0xff00
+#define DPM_TABLE_195__MemoryACPILevel_DisplayWatermark__SHIFT 0x8
+#define DPM_TABLE_195__MemoryACPILevel_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_195__MemoryACPILevel_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_202__MemoryACPILevel_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_202__MemoryACPILevel_DllCntl__SHIFT 0x0
+#define DPM_TABLE_203__MemoryACPILevel_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_203__MemoryACPILevel_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_204__MemoryACPILevel_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_204__MemoryACPILevel_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_205__MemoryLevel_0_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_205__MemoryLevel_0_MinVddc__SHIFT 0x0
+#define DPM_TABLE_206__MemoryLevel_0_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_206__MemoryLevel_0_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_207__MemoryLevel_0_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_207__MemoryLevel_0_MinVddci__SHIFT 0x0
+#define DPM_TABLE_208__MemoryLevel_0_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_208__MemoryLevel_0_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_209__MemoryLevel_0_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_209__MemoryLevel_0_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_210__MemoryLevel_0_StutterEnable_MASK 0xff
+#define DPM_TABLE_210__MemoryLevel_0_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_210__MemoryLevel_0_RttEnable_MASK 0xff00
+#define DPM_TABLE_210__MemoryLevel_0_RttEnable__SHIFT 0x8
+#define DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_210__MemoryLevel_0_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_210__MemoryLevel_0_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_211__MemoryLevel_0_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_211__MemoryLevel_0_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_211__MemoryLevel_0_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_211__MemoryLevel_0_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_211__MemoryLevel_0_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_211__MemoryLevel_0_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_212__MemoryLevel_0_padding_MASK 0xff
+#define DPM_TABLE_212__MemoryLevel_0_padding__SHIFT 0x0
+#define DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_212__MemoryLevel_0_DownHyst_MASK 0xff0000
+#define DPM_TABLE_212__MemoryLevel_0_DownHyst__SHIFT 0x10
+#define DPM_TABLE_212__MemoryLevel_0_UpHyst_MASK 0xff000000
+#define DPM_TABLE_212__MemoryLevel_0_UpHyst__SHIFT 0x18
+#define DPM_TABLE_213__MemoryLevel_0_padding1_MASK 0xff
+#define DPM_TABLE_213__MemoryLevel_0_padding1__SHIFT 0x0
+#define DPM_TABLE_213__MemoryLevel_0_DisplayWatermark_MASK 0xff00
+#define DPM_TABLE_213__MemoryLevel_0_DisplayWatermark__SHIFT 0x8
+#define DPM_TABLE_213__MemoryLevel_0_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_213__MemoryLevel_0_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_220__MemoryLevel_0_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_220__MemoryLevel_0_DllCntl__SHIFT 0x0
+#define DPM_TABLE_221__MemoryLevel_0_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_221__MemoryLevel_0_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_222__MemoryLevel_0_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_222__MemoryLevel_0_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_223__MemoryLevel_1_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_223__MemoryLevel_1_MinVddc__SHIFT 0x0
+#define DPM_TABLE_224__MemoryLevel_1_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_224__MemoryLevel_1_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_225__MemoryLevel_1_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_225__MemoryLevel_1_MinVddci__SHIFT 0x0
+#define DPM_TABLE_226__MemoryLevel_1_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_226__MemoryLevel_1_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_227__MemoryLevel_1_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_227__MemoryLevel_1_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_228__MemoryLevel_1_StutterEnable_MASK 0xff
+#define DPM_TABLE_228__MemoryLevel_1_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_228__MemoryLevel_1_RttEnable_MASK 0xff00
+#define DPM_TABLE_228__MemoryLevel_1_RttEnable__SHIFT 0x8
+#define DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_228__MemoryLevel_1_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_228__MemoryLevel_1_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_229__MemoryLevel_1_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_229__MemoryLevel_1_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_229__MemoryLevel_1_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_229__MemoryLevel_1_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_229__MemoryLevel_1_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_229__MemoryLevel_1_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_230__MemoryLevel_1_padding_MASK 0xff
+#define DPM_TABLE_230__MemoryLevel_1_padding__SHIFT 0x0
+#define DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_230__MemoryLevel_1_DownHyst_MASK 0xff0000
+#define DPM_TABLE_230__MemoryLevel_1_DownHyst__SHIFT 0x10
+#define DPM_TABLE_230__MemoryLevel_1_UpHyst_MASK 0xff000000
+#define DPM_TABLE_230__MemoryLevel_1_UpHyst__SHIFT 0x18
+#define DPM_TABLE_231__MemoryLevel_1_padding1_MASK 0xff
+#define DPM_TABLE_231__MemoryLevel_1_padding1__SHIFT 0x0
+#define DPM_TABLE_231__MemoryLevel_1_DisplayWatermark_MASK 0xff00
+#define DPM_TABLE_231__MemoryLevel_1_DisplayWatermark__SHIFT 0x8
+#define DPM_TABLE_231__MemoryLevel_1_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_231__MemoryLevel_1_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_238__MemoryLevel_1_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_238__MemoryLevel_1_DllCntl__SHIFT 0x0
+#define DPM_TABLE_239__MemoryLevel_1_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_239__MemoryLevel_1_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_240__MemoryLevel_1_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_240__MemoryLevel_1_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_241__MemoryLevel_2_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_241__MemoryLevel_2_MinVddc__SHIFT 0x0
+#define DPM_TABLE_242__MemoryLevel_2_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_242__MemoryLevel_2_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_243__MemoryLevel_2_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_243__MemoryLevel_2_MinVddci__SHIFT 0x0
+#define DPM_TABLE_244__MemoryLevel_2_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_244__MemoryLevel_2_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_245__MemoryLevel_2_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_245__MemoryLevel_2_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_246__MemoryLevel_2_StutterEnable_MASK 0xff
+#define DPM_TABLE_246__MemoryLevel_2_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_246__MemoryLevel_2_RttEnable_MASK 0xff00
+#define DPM_TABLE_246__MemoryLevel_2_RttEnable__SHIFT 0x8
+#define DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_246__MemoryLevel_2_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_246__MemoryLevel_2_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_247__MemoryLevel_2_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_247__MemoryLevel_2_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_247__MemoryLevel_2_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_247__MemoryLevel_2_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_247__MemoryLevel_2_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_247__MemoryLevel_2_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_248__MemoryLevel_2_padding_MASK 0xff
+#define DPM_TABLE_248__MemoryLevel_2_padding__SHIFT 0x0
+#define DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_248__MemoryLevel_2_DownHyst_MASK 0xff0000
+#define DPM_TABLE_248__MemoryLevel_2_DownHyst__SHIFT 0x10
+#define DPM_TABLE_248__MemoryLevel_2_UpHyst_MASK 0xff000000
+#define DPM_TABLE_248__MemoryLevel_2_UpHyst__SHIFT 0x18
+#define DPM_TABLE_249__MemoryLevel_2_padding1_MASK 0xff
+#define DPM_TABLE_249__MemoryLevel_2_padding1__SHIFT 0x0
+#define DPM_TABLE_249__MemoryLevel_2_DisplayWatermark_MASK 0xff00
+#define DPM_TABLE_249__MemoryLevel_2_DisplayWatermark__SHIFT 0x8
+#define DPM_TABLE_249__MemoryLevel_2_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_249__MemoryLevel_2_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_256__MemoryLevel_2_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_256__MemoryLevel_2_DllCntl__SHIFT 0x0
+#define DPM_TABLE_257__MemoryLevel_2_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_257__MemoryLevel_2_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_258__MemoryLevel_2_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_258__MemoryLevel_2_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_259__MemoryLevel_3_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_259__MemoryLevel_3_MinVddc__SHIFT 0x0
+#define DPM_TABLE_260__MemoryLevel_3_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_260__MemoryLevel_3_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_261__MemoryLevel_3_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_261__MemoryLevel_3_MinVddci__SHIFT 0x0
+#define DPM_TABLE_262__MemoryLevel_3_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_262__MemoryLevel_3_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_263__MemoryLevel_3_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_263__MemoryLevel_3_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_264__MemoryLevel_3_StutterEnable_MASK 0xff
+#define DPM_TABLE_264__MemoryLevel_3_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_264__MemoryLevel_3_RttEnable_MASK 0xff00
+#define DPM_TABLE_264__MemoryLevel_3_RttEnable__SHIFT 0x8
+#define DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_264__MemoryLevel_3_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_264__MemoryLevel_3_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_265__MemoryLevel_3_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_265__MemoryLevel_3_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_265__MemoryLevel_3_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_265__MemoryLevel_3_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_265__MemoryLevel_3_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_265__MemoryLevel_3_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_266__MemoryLevel_3_padding_MASK 0xff
+#define DPM_TABLE_266__MemoryLevel_3_padding__SHIFT 0x0
+#define DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_266__MemoryLevel_3_DownHyst_MASK 0xff0000
+#define DPM_TABLE_266__MemoryLevel_3_DownHyst__SHIFT 0x10
+#define DPM_TABLE_266__MemoryLevel_3_UpHyst_MASK 0xff000000
+#define DPM_TABLE_266__MemoryLevel_3_UpHyst__SHIFT 0x18
+#define DPM_TABLE_267__MemoryLevel_3_padding1_MASK 0xff
+#define DPM_TABLE_267__MemoryLevel_3_padding1__SHIFT 0x0
+#define DPM_TABLE_267__MemoryLevel_3_DisplayWatermark_MASK 0xff00
+#define DPM_TABLE_267__MemoryLevel_3_DisplayWatermark__SHIFT 0x8
+#define DPM_TABLE_267__MemoryLevel_3_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_267__MemoryLevel_3_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_274__MemoryLevel_3_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_274__MemoryLevel_3_DllCntl__SHIFT 0x0
+#define DPM_TABLE_275__MemoryLevel_3_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_275__MemoryLevel_3_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_276__MemoryLevel_3_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_276__MemoryLevel_3_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_277__MemoryLevel_4_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_277__MemoryLevel_4_MinVddc__SHIFT 0x0
+#define DPM_TABLE_278__MemoryLevel_4_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_278__MemoryLevel_4_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_279__MemoryLevel_4_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_279__MemoryLevel_4_MinVddci__SHIFT 0x0
+#define DPM_TABLE_280__MemoryLevel_4_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_280__MemoryLevel_4_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_281__MemoryLevel_4_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_281__MemoryLevel_4_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_282__MemoryLevel_4_StutterEnable_MASK 0xff
+#define DPM_TABLE_282__MemoryLevel_4_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_282__MemoryLevel_4_RttEnable_MASK 0xff00
+#define DPM_TABLE_282__MemoryLevel_4_RttEnable__SHIFT 0x8
+#define DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_282__MemoryLevel_4_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_282__MemoryLevel_4_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_283__MemoryLevel_4_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_283__MemoryLevel_4_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_283__MemoryLevel_4_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_283__MemoryLevel_4_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_283__MemoryLevel_4_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_283__MemoryLevel_4_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_284__MemoryLevel_4_padding_MASK 0xff
+#define DPM_TABLE_284__MemoryLevel_4_padding__SHIFT 0x0
+#define DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_284__MemoryLevel_4_DownHyst_MASK 0xff0000
+#define DPM_TABLE_284__MemoryLevel_4_DownHyst__SHIFT 0x10
+#define DPM_TABLE_284__MemoryLevel_4_UpHyst_MASK 0xff000000
+#define DPM_TABLE_284__MemoryLevel_4_UpHyst__SHIFT 0x18
+#define DPM_TABLE_285__MemoryLevel_4_padding1_MASK 0xff
+#define DPM_TABLE_285__MemoryLevel_4_padding1__SHIFT 0x0
+#define DPM_TABLE_285__MemoryLevel_4_DisplayWatermark_MASK 0xff00
+#define DPM_TABLE_285__MemoryLevel_4_DisplayWatermark__SHIFT 0x8
+#define DPM_TABLE_285__MemoryLevel_4_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_285__MemoryLevel_4_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_292__MemoryLevel_4_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_292__MemoryLevel_4_DllCntl__SHIFT 0x0
+#define DPM_TABLE_293__MemoryLevel_4_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_293__MemoryLevel_4_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_294__MemoryLevel_4_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_294__MemoryLevel_4_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_295__MemoryLevel_5_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_295__MemoryLevel_5_MinVddc__SHIFT 0x0
+#define DPM_TABLE_296__MemoryLevel_5_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_296__MemoryLevel_5_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_297__MemoryLevel_5_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_297__MemoryLevel_5_MinVddci__SHIFT 0x0
+#define DPM_TABLE_298__MemoryLevel_5_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_298__MemoryLevel_5_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_299__MemoryLevel_5_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_299__MemoryLevel_5_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_300__MemoryLevel_5_StutterEnable_MASK 0xff
+#define DPM_TABLE_300__MemoryLevel_5_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_300__MemoryLevel_5_RttEnable_MASK 0xff00
+#define DPM_TABLE_300__MemoryLevel_5_RttEnable__SHIFT 0x8
+#define DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_300__MemoryLevel_5_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_300__MemoryLevel_5_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_301__MemoryLevel_5_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_301__MemoryLevel_5_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_301__MemoryLevel_5_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_301__MemoryLevel_5_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_301__MemoryLevel_5_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_301__MemoryLevel_5_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_302__MemoryLevel_5_padding_MASK 0xff
+#define DPM_TABLE_302__MemoryLevel_5_padding__SHIFT 0x0
+#define DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_302__MemoryLevel_5_DownHyst_MASK 0xff0000
+#define DPM_TABLE_302__MemoryLevel_5_DownHyst__SHIFT 0x10
+#define DPM_TABLE_302__MemoryLevel_5_UpHyst_MASK 0xff000000
+#define DPM_TABLE_302__MemoryLevel_5_UpHyst__SHIFT 0x18
+#define DPM_TABLE_303__MemoryLevel_5_padding1_MASK 0xff
+#define DPM_TABLE_303__MemoryLevel_5_padding1__SHIFT 0x0
+#define DPM_TABLE_303__MemoryLevel_5_DisplayWatermark_MASK 0xff00
+#define DPM_TABLE_303__MemoryLevel_5_DisplayWatermark__SHIFT 0x8
+#define DPM_TABLE_303__MemoryLevel_5_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_303__MemoryLevel_5_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_310__MemoryLevel_5_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_310__MemoryLevel_5_DllCntl__SHIFT 0x0
+#define DPM_TABLE_311__MemoryLevel_5_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_311__MemoryLevel_5_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_312__MemoryLevel_5_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_312__MemoryLevel_5_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_313__LinkLevel_0_Padding_MASK 0xff
+#define DPM_TABLE_313__LinkLevel_0_Padding__SHIFT 0x0
+#define DPM_TABLE_313__LinkLevel_0_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_313__LinkLevel_0_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_313__LinkLevel_0_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_313__LinkLevel_0_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_313__LinkLevel_0_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_313__LinkLevel_0_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_314__LinkLevel_0_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_314__LinkLevel_0_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_315__LinkLevel_0_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_315__LinkLevel_0_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_316__LinkLevel_0_Reserved_MASK 0xffffffff
+#define DPM_TABLE_316__LinkLevel_0_Reserved__SHIFT 0x0
+#define DPM_TABLE_317__LinkLevel_1_Padding_MASK 0xff
+#define DPM_TABLE_317__LinkLevel_1_Padding__SHIFT 0x0
+#define DPM_TABLE_317__LinkLevel_1_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_317__LinkLevel_1_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_317__LinkLevel_1_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_317__LinkLevel_1_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_317__LinkLevel_1_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_317__LinkLevel_1_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_318__LinkLevel_1_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_318__LinkLevel_1_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_319__LinkLevel_1_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_319__LinkLevel_1_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_320__LinkLevel_1_Reserved_MASK 0xffffffff
+#define DPM_TABLE_320__LinkLevel_1_Reserved__SHIFT 0x0
+#define DPM_TABLE_321__LinkLevel_2_Padding_MASK 0xff
+#define DPM_TABLE_321__LinkLevel_2_Padding__SHIFT 0x0
+#define DPM_TABLE_321__LinkLevel_2_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_321__LinkLevel_2_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_321__LinkLevel_2_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_321__LinkLevel_2_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_321__LinkLevel_2_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_321__LinkLevel_2_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_322__LinkLevel_2_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_322__LinkLevel_2_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_323__LinkLevel_2_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_323__LinkLevel_2_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_324__LinkLevel_2_Reserved_MASK 0xffffffff
+#define DPM_TABLE_324__LinkLevel_2_Reserved__SHIFT 0x0
+#define DPM_TABLE_325__LinkLevel_3_Padding_MASK 0xff
+#define DPM_TABLE_325__LinkLevel_3_Padding__SHIFT 0x0
+#define DPM_TABLE_325__LinkLevel_3_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_325__LinkLevel_3_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_325__LinkLevel_3_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_325__LinkLevel_3_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_325__LinkLevel_3_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_325__LinkLevel_3_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_326__LinkLevel_3_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_326__LinkLevel_3_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_327__LinkLevel_3_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_327__LinkLevel_3_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_328__LinkLevel_3_Reserved_MASK 0xffffffff
+#define DPM_TABLE_328__LinkLevel_3_Reserved__SHIFT 0x0
+#define DPM_TABLE_329__LinkLevel_4_Padding_MASK 0xff
+#define DPM_TABLE_329__LinkLevel_4_Padding__SHIFT 0x0
+#define DPM_TABLE_329__LinkLevel_4_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_329__LinkLevel_4_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_329__LinkLevel_4_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_329__LinkLevel_4_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_329__LinkLevel_4_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_329__LinkLevel_4_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_330__LinkLevel_4_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_330__LinkLevel_4_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_331__LinkLevel_4_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_331__LinkLevel_4_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_332__LinkLevel_4_Reserved_MASK 0xffffffff
+#define DPM_TABLE_332__LinkLevel_4_Reserved__SHIFT 0x0
+#define DPM_TABLE_333__LinkLevel_5_Padding_MASK 0xff
+#define DPM_TABLE_333__LinkLevel_5_Padding__SHIFT 0x0
+#define DPM_TABLE_333__LinkLevel_5_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_333__LinkLevel_5_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_333__LinkLevel_5_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_333__LinkLevel_5_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_333__LinkLevel_5_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_333__LinkLevel_5_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_334__LinkLevel_5_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_334__LinkLevel_5_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_335__LinkLevel_5_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_335__LinkLevel_5_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_336__LinkLevel_5_Reserved_MASK 0xffffffff
+#define DPM_TABLE_336__LinkLevel_5_Reserved__SHIFT 0x0
+#define DPM_TABLE_337__LinkLevel_6_Padding_MASK 0xff
+#define DPM_TABLE_337__LinkLevel_6_Padding__SHIFT 0x0
+#define DPM_TABLE_337__LinkLevel_6_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_337__LinkLevel_6_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_337__LinkLevel_6_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_337__LinkLevel_6_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_337__LinkLevel_6_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_337__LinkLevel_6_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_338__LinkLevel_6_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_338__LinkLevel_6_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_339__LinkLevel_6_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_339__LinkLevel_6_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_340__LinkLevel_6_Reserved_MASK 0xffffffff
+#define DPM_TABLE_340__LinkLevel_6_Reserved__SHIFT 0x0
+#define DPM_TABLE_341__LinkLevel_7_Padding_MASK 0xff
+#define DPM_TABLE_341__LinkLevel_7_Padding__SHIFT 0x0
+#define DPM_TABLE_341__LinkLevel_7_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_341__LinkLevel_7_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_341__LinkLevel_7_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_341__LinkLevel_7_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_341__LinkLevel_7_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_341__LinkLevel_7_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_342__LinkLevel_7_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_342__LinkLevel_7_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_343__LinkLevel_7_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_343__LinkLevel_7_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_344__LinkLevel_7_Reserved_MASK 0xffffffff
+#define DPM_TABLE_344__LinkLevel_7_Reserved__SHIFT 0x0
+#define DPM_TABLE_345__ACPILevel_Flags_MASK 0xffffffff
+#define DPM_TABLE_345__ACPILevel_Flags__SHIFT 0x0
+#define DPM_TABLE_346__ACPILevel_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_346__ACPILevel_MinVddc__SHIFT 0x0
+#define DPM_TABLE_347__ACPILevel_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_347__ACPILevel_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_348__ACPILevel_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_348__ACPILevel_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_349__ACPILevel_padding_MASK 0xff
+#define DPM_TABLE_349__ACPILevel_padding__SHIFT 0x0
+#define DPM_TABLE_349__ACPILevel_DeepSleepDivId_MASK 0xff00
+#define DPM_TABLE_349__ACPILevel_DeepSleepDivId__SHIFT 0x8
+#define DPM_TABLE_349__ACPILevel_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_349__ACPILevel_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_349__ACPILevel_SclkDid_MASK 0xff000000
+#define DPM_TABLE_349__ACPILevel_SclkDid__SHIFT 0x18
+#define DPM_TABLE_350__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_350__ACPILevel_CgSpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff
+#define DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0
+#define DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_356__ACPILevel_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_356__ACPILevel_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_357__ACPILevel_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_357__ACPILevel_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_358__UvdLevel_0_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_358__UvdLevel_0_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_359__UvdLevel_0_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_359__UvdLevel_0_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_360__UvdLevel_0_VclkDivider_MASK 0xff
+#define DPM_TABLE_360__UvdLevel_0_VclkDivider__SHIFT 0x0
+#define DPM_TABLE_360__UvdLevel_0_MinVddcPhases_MASK 0xff00
+#define DPM_TABLE_360__UvdLevel_0_MinVddcPhases__SHIFT 0x8
+#define DPM_TABLE_360__UvdLevel_0_MinVddc_MASK 0xffff0000
+#define DPM_TABLE_360__UvdLevel_0_MinVddc__SHIFT 0x10
+#define DPM_TABLE_361__UvdLevel_0_padding_2_MASK 0xff
+#define DPM_TABLE_361__UvdLevel_0_padding_2__SHIFT 0x0
+#define DPM_TABLE_361__UvdLevel_0_padding_1_MASK 0xff00
+#define DPM_TABLE_361__UvdLevel_0_padding_1__SHIFT 0x8
+#define DPM_TABLE_361__UvdLevel_0_padding_0_MASK 0xff0000
+#define DPM_TABLE_361__UvdLevel_0_padding_0__SHIFT 0x10
+#define DPM_TABLE_361__UvdLevel_0_DclkDivider_MASK 0xff000000
+#define DPM_TABLE_361__UvdLevel_0_DclkDivider__SHIFT 0x18
+#define DPM_TABLE_362__UvdLevel_1_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_362__UvdLevel_1_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_363__UvdLevel_1_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_363__UvdLevel_1_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_364__UvdLevel_1_VclkDivider_MASK 0xff
+#define DPM_TABLE_364__UvdLevel_1_VclkDivider__SHIFT 0x0
+#define DPM_TABLE_364__UvdLevel_1_MinVddcPhases_MASK 0xff00
+#define DPM_TABLE_364__UvdLevel_1_MinVddcPhases__SHIFT 0x8
+#define DPM_TABLE_364__UvdLevel_1_MinVddc_MASK 0xffff0000
+#define DPM_TABLE_364__UvdLevel_1_MinVddc__SHIFT 0x10
+#define DPM_TABLE_365__UvdLevel_1_padding_2_MASK 0xff
+#define DPM_TABLE_365__UvdLevel_1_padding_2__SHIFT 0x0
+#define DPM_TABLE_365__UvdLevel_1_padding_1_MASK 0xff00
+#define DPM_TABLE_365__UvdLevel_1_padding_1__SHIFT 0x8
+#define DPM_TABLE_365__UvdLevel_1_padding_0_MASK 0xff0000
+#define DPM_TABLE_365__UvdLevel_1_padding_0__SHIFT 0x10
+#define DPM_TABLE_365__UvdLevel_1_DclkDivider_MASK 0xff000000
+#define DPM_TABLE_365__UvdLevel_1_DclkDivider__SHIFT 0x18
+#define DPM_TABLE_366__UvdLevel_2_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_366__UvdLevel_2_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_367__UvdLevel_2_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_367__UvdLevel_2_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_368__UvdLevel_2_VclkDivider_MASK 0xff
+#define DPM_TABLE_368__UvdLevel_2_VclkDivider__SHIFT 0x0
+#define DPM_TABLE_368__UvdLevel_2_MinVddcPhases_MASK 0xff00
+#define DPM_TABLE_368__UvdLevel_2_MinVddcPhases__SHIFT 0x8
+#define DPM_TABLE_368__UvdLevel_2_MinVddc_MASK 0xffff0000
+#define DPM_TABLE_368__UvdLevel_2_MinVddc__SHIFT 0x10
+#define DPM_TABLE_369__UvdLevel_2_padding_2_MASK 0xff
+#define DPM_TABLE_369__UvdLevel_2_padding_2__SHIFT 0x0
+#define DPM_TABLE_369__UvdLevel_2_padding_1_MASK 0xff00
+#define DPM_TABLE_369__UvdLevel_2_padding_1__SHIFT 0x8
+#define DPM_TABLE_369__UvdLevel_2_padding_0_MASK 0xff0000
+#define DPM_TABLE_369__UvdLevel_2_padding_0__SHIFT 0x10
+#define DPM_TABLE_369__UvdLevel_2_DclkDivider_MASK 0xff000000
+#define DPM_TABLE_369__UvdLevel_2_DclkDivider__SHIFT 0x18
+#define DPM_TABLE_370__UvdLevel_3_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_370__UvdLevel_3_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_371__UvdLevel_3_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_371__UvdLevel_3_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_372__UvdLevel_3_VclkDivider_MASK 0xff
+#define DPM_TABLE_372__UvdLevel_3_VclkDivider__SHIFT 0x0
+#define DPM_TABLE_372__UvdLevel_3_MinVddcPhases_MASK 0xff00
+#define DPM_TABLE_372__UvdLevel_3_MinVddcPhases__SHIFT 0x8
+#define DPM_TABLE_372__UvdLevel_3_MinVddc_MASK 0xffff0000
+#define DPM_TABLE_372__UvdLevel_3_MinVddc__SHIFT 0x10
+#define DPM_TABLE_373__UvdLevel_3_padding_2_MASK 0xff
+#define DPM_TABLE_373__UvdLevel_3_padding_2__SHIFT 0x0
+#define DPM_TABLE_373__UvdLevel_3_padding_1_MASK 0xff00
+#define DPM_TABLE_373__UvdLevel_3_padding_1__SHIFT 0x8
+#define DPM_TABLE_373__UvdLevel_3_padding_0_MASK 0xff0000
+#define DPM_TABLE_373__UvdLevel_3_padding_0__SHIFT 0x10
+#define DPM_TABLE_373__UvdLevel_3_DclkDivider_MASK 0xff000000
+#define DPM_TABLE_373__UvdLevel_3_DclkDivider__SHIFT 0x18
+#define DPM_TABLE_374__UvdLevel_4_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_374__UvdLevel_4_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_375__UvdLevel_4_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_375__UvdLevel_4_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_376__UvdLevel_4_VclkDivider_MASK 0xff
+#define DPM_TABLE_376__UvdLevel_4_VclkDivider__SHIFT 0x0
+#define DPM_TABLE_376__UvdLevel_4_MinVddcPhases_MASK 0xff00
+#define DPM_TABLE_376__UvdLevel_4_MinVddcPhases__SHIFT 0x8
+#define DPM_TABLE_376__UvdLevel_4_MinVddc_MASK 0xffff0000
+#define DPM_TABLE_376__UvdLevel_4_MinVddc__SHIFT 0x10
+#define DPM_TABLE_377__UvdLevel_4_padding_2_MASK 0xff
+#define DPM_TABLE_377__UvdLevel_4_padding_2__SHIFT 0x0
+#define DPM_TABLE_377__UvdLevel_4_padding_1_MASK 0xff00
+#define DPM_TABLE_377__UvdLevel_4_padding_1__SHIFT 0x8
+#define DPM_TABLE_377__UvdLevel_4_padding_0_MASK 0xff0000
+#define DPM_TABLE_377__UvdLevel_4_padding_0__SHIFT 0x10
+#define DPM_TABLE_377__UvdLevel_4_DclkDivider_MASK 0xff000000
+#define DPM_TABLE_377__UvdLevel_4_DclkDivider__SHIFT 0x18
+#define DPM_TABLE_378__UvdLevel_5_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_378__UvdLevel_5_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_379__UvdLevel_5_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_379__UvdLevel_5_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_380__UvdLevel_5_VclkDivider_MASK 0xff
+#define DPM_TABLE_380__UvdLevel_5_VclkDivider__SHIFT 0x0
+#define DPM_TABLE_380__UvdLevel_5_MinVddcPhases_MASK 0xff00
+#define DPM_TABLE_380__UvdLevel_5_MinVddcPhases__SHIFT 0x8
+#define DPM_TABLE_380__UvdLevel_5_MinVddc_MASK 0xffff0000
+#define DPM_TABLE_380__UvdLevel_5_MinVddc__SHIFT 0x10
+#define DPM_TABLE_381__UvdLevel_5_padding_2_MASK 0xff
+#define DPM_TABLE_381__UvdLevel_5_padding_2__SHIFT 0x0
+#define DPM_TABLE_381__UvdLevel_5_padding_1_MASK 0xff00
+#define DPM_TABLE_381__UvdLevel_5_padding_1__SHIFT 0x8
+#define DPM_TABLE_381__UvdLevel_5_padding_0_MASK 0xff0000
+#define DPM_TABLE_381__UvdLevel_5_padding_0__SHIFT 0x10
+#define DPM_TABLE_381__UvdLevel_5_DclkDivider_MASK 0xff000000
+#define DPM_TABLE_381__UvdLevel_5_DclkDivider__SHIFT 0x18
+#define DPM_TABLE_382__UvdLevel_6_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_382__UvdLevel_6_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_383__UvdLevel_6_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_383__UvdLevel_6_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_384__UvdLevel_6_VclkDivider_MASK 0xff
+#define DPM_TABLE_384__UvdLevel_6_VclkDivider__SHIFT 0x0
+#define DPM_TABLE_384__UvdLevel_6_MinVddcPhases_MASK 0xff00
+#define DPM_TABLE_384__UvdLevel_6_MinVddcPhases__SHIFT 0x8
+#define DPM_TABLE_384__UvdLevel_6_MinVddc_MASK 0xffff0000
+#define DPM_TABLE_384__UvdLevel_6_MinVddc__SHIFT 0x10
+#define DPM_TABLE_385__UvdLevel_6_padding_2_MASK 0xff
+#define DPM_TABLE_385__UvdLevel_6_padding_2__SHIFT 0x0
+#define DPM_TABLE_385__UvdLevel_6_padding_1_MASK 0xff00
+#define DPM_TABLE_385__UvdLevel_6_padding_1__SHIFT 0x8
+#define DPM_TABLE_385__UvdLevel_6_padding_0_MASK 0xff0000
+#define DPM_TABLE_385__UvdLevel_6_padding_0__SHIFT 0x10
+#define DPM_TABLE_385__UvdLevel_6_DclkDivider_MASK 0xff000000
+#define DPM_TABLE_385__UvdLevel_6_DclkDivider__SHIFT 0x18
+#define DPM_TABLE_386__UvdLevel_7_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_386__UvdLevel_7_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_387__UvdLevel_7_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_387__UvdLevel_7_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_388__UvdLevel_7_VclkDivider_MASK 0xff
+#define DPM_TABLE_388__UvdLevel_7_VclkDivider__SHIFT 0x0
+#define DPM_TABLE_388__UvdLevel_7_MinVddcPhases_MASK 0xff00
+#define DPM_TABLE_388__UvdLevel_7_MinVddcPhases__SHIFT 0x8
+#define DPM_TABLE_388__UvdLevel_7_MinVddc_MASK 0xffff0000
+#define DPM_TABLE_388__UvdLevel_7_MinVddc__SHIFT 0x10
+#define DPM_TABLE_389__UvdLevel_7_padding_2_MASK 0xff
+#define DPM_TABLE_389__UvdLevel_7_padding_2__SHIFT 0x0
+#define DPM_TABLE_389__UvdLevel_7_padding_1_MASK 0xff00
+#define DPM_TABLE_389__UvdLevel_7_padding_1__SHIFT 0x8
+#define DPM_TABLE_389__UvdLevel_7_padding_0_MASK 0xff0000
+#define DPM_TABLE_389__UvdLevel_7_padding_0__SHIFT 0x10
+#define DPM_TABLE_389__UvdLevel_7_DclkDivider_MASK 0xff000000
+#define DPM_TABLE_389__UvdLevel_7_DclkDivider__SHIFT 0x18
+#define DPM_TABLE_390__VceLevel_0_Frequency_MASK 0xffffffff
+#define DPM_TABLE_390__VceLevel_0_Frequency__SHIFT 0x0
+#define DPM_TABLE_391__VceLevel_0_Divider_MASK 0xff
+#define DPM_TABLE_391__VceLevel_0_Divider__SHIFT 0x0
+#define DPM_TABLE_391__VceLevel_0_MinPhases_MASK 0xff00
+#define DPM_TABLE_391__VceLevel_0_MinPhases__SHIFT 0x8
+#define DPM_TABLE_391__VceLevel_0_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_391__VceLevel_0_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_392__VceLevel_1_Frequency_MASK 0xffffffff
+#define DPM_TABLE_392__VceLevel_1_Frequency__SHIFT 0x0
+#define DPM_TABLE_393__VceLevel_1_Divider_MASK 0xff
+#define DPM_TABLE_393__VceLevel_1_Divider__SHIFT 0x0
+#define DPM_TABLE_393__VceLevel_1_MinPhases_MASK 0xff00
+#define DPM_TABLE_393__VceLevel_1_MinPhases__SHIFT 0x8
+#define DPM_TABLE_393__VceLevel_1_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_393__VceLevel_1_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_394__VceLevel_2_Frequency_MASK 0xffffffff
+#define DPM_TABLE_394__VceLevel_2_Frequency__SHIFT 0x0
+#define DPM_TABLE_395__VceLevel_2_Divider_MASK 0xff
+#define DPM_TABLE_395__VceLevel_2_Divider__SHIFT 0x0
+#define DPM_TABLE_395__VceLevel_2_MinPhases_MASK 0xff00
+#define DPM_TABLE_395__VceLevel_2_MinPhases__SHIFT 0x8
+#define DPM_TABLE_395__VceLevel_2_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_395__VceLevel_2_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_396__VceLevel_3_Frequency_MASK 0xffffffff
+#define DPM_TABLE_396__VceLevel_3_Frequency__SHIFT 0x0
+#define DPM_TABLE_397__VceLevel_3_Divider_MASK 0xff
+#define DPM_TABLE_397__VceLevel_3_Divider__SHIFT 0x0
+#define DPM_TABLE_397__VceLevel_3_MinPhases_MASK 0xff00
+#define DPM_TABLE_397__VceLevel_3_MinPhases__SHIFT 0x8
+#define DPM_TABLE_397__VceLevel_3_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_397__VceLevel_3_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_398__VceLevel_4_Frequency_MASK 0xffffffff
+#define DPM_TABLE_398__VceLevel_4_Frequency__SHIFT 0x0
+#define DPM_TABLE_399__VceLevel_4_Divider_MASK 0xff
+#define DPM_TABLE_399__VceLevel_4_Divider__SHIFT 0x0
+#define DPM_TABLE_399__VceLevel_4_MinPhases_MASK 0xff00
+#define DPM_TABLE_399__VceLevel_4_MinPhases__SHIFT 0x8
+#define DPM_TABLE_399__VceLevel_4_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_399__VceLevel_4_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_400__VceLevel_5_Frequency_MASK 0xffffffff
+#define DPM_TABLE_400__VceLevel_5_Frequency__SHIFT 0x0
+#define DPM_TABLE_401__VceLevel_5_Divider_MASK 0xff
+#define DPM_TABLE_401__VceLevel_5_Divider__SHIFT 0x0
+#define DPM_TABLE_401__VceLevel_5_MinPhases_MASK 0xff00
+#define DPM_TABLE_401__VceLevel_5_MinPhases__SHIFT 0x8
+#define DPM_TABLE_401__VceLevel_5_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_401__VceLevel_5_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_402__VceLevel_6_Frequency_MASK 0xffffffff
+#define DPM_TABLE_402__VceLevel_6_Frequency__SHIFT 0x0
+#define DPM_TABLE_403__VceLevel_6_Divider_MASK 0xff
+#define DPM_TABLE_403__VceLevel_6_Divider__SHIFT 0x0
+#define DPM_TABLE_403__VceLevel_6_MinPhases_MASK 0xff00
+#define DPM_TABLE_403__VceLevel_6_MinPhases__SHIFT 0x8
+#define DPM_TABLE_403__VceLevel_6_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_403__VceLevel_6_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_404__VceLevel_7_Frequency_MASK 0xffffffff
+#define DPM_TABLE_404__VceLevel_7_Frequency__SHIFT 0x0
+#define DPM_TABLE_405__VceLevel_7_Divider_MASK 0xff
+#define DPM_TABLE_405__VceLevel_7_Divider__SHIFT 0x0
+#define DPM_TABLE_405__VceLevel_7_MinPhases_MASK 0xff00
+#define DPM_TABLE_405__VceLevel_7_MinPhases__SHIFT 0x8
+#define DPM_TABLE_405__VceLevel_7_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_405__VceLevel_7_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_406__AcpLevel_0_Frequency_MASK 0xffffffff
+#define DPM_TABLE_406__AcpLevel_0_Frequency__SHIFT 0x0
+#define DPM_TABLE_407__AcpLevel_0_Divider_MASK 0xff
+#define DPM_TABLE_407__AcpLevel_0_Divider__SHIFT 0x0
+#define DPM_TABLE_407__AcpLevel_0_MinPhases_MASK 0xff00
+#define DPM_TABLE_407__AcpLevel_0_MinPhases__SHIFT 0x8
+#define DPM_TABLE_407__AcpLevel_0_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_407__AcpLevel_0_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_408__AcpLevel_1_Frequency_MASK 0xffffffff
+#define DPM_TABLE_408__AcpLevel_1_Frequency__SHIFT 0x0
+#define DPM_TABLE_409__AcpLevel_1_Divider_MASK 0xff
+#define DPM_TABLE_409__AcpLevel_1_Divider__SHIFT 0x0
+#define DPM_TABLE_409__AcpLevel_1_MinPhases_MASK 0xff00
+#define DPM_TABLE_409__AcpLevel_1_MinPhases__SHIFT 0x8
+#define DPM_TABLE_409__AcpLevel_1_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_409__AcpLevel_1_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_410__AcpLevel_2_Frequency_MASK 0xffffffff
+#define DPM_TABLE_410__AcpLevel_2_Frequency__SHIFT 0x0
+#define DPM_TABLE_411__AcpLevel_2_Divider_MASK 0xff
+#define DPM_TABLE_411__AcpLevel_2_Divider__SHIFT 0x0
+#define DPM_TABLE_411__AcpLevel_2_MinPhases_MASK 0xff00
+#define DPM_TABLE_411__AcpLevel_2_MinPhases__SHIFT 0x8
+#define DPM_TABLE_411__AcpLevel_2_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_411__AcpLevel_2_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_412__AcpLevel_3_Frequency_MASK 0xffffffff
+#define DPM_TABLE_412__AcpLevel_3_Frequency__SHIFT 0x0
+#define DPM_TABLE_413__AcpLevel_3_Divider_MASK 0xff
+#define DPM_TABLE_413__AcpLevel_3_Divider__SHIFT 0x0
+#define DPM_TABLE_413__AcpLevel_3_MinPhases_MASK 0xff00
+#define DPM_TABLE_413__AcpLevel_3_MinPhases__SHIFT 0x8
+#define DPM_TABLE_413__AcpLevel_3_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_413__AcpLevel_3_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_414__AcpLevel_4_Frequency_MASK 0xffffffff
+#define DPM_TABLE_414__AcpLevel_4_Frequency__SHIFT 0x0
+#define DPM_TABLE_415__AcpLevel_4_Divider_MASK 0xff
+#define DPM_TABLE_415__AcpLevel_4_Divider__SHIFT 0x0
+#define DPM_TABLE_415__AcpLevel_4_MinPhases_MASK 0xff00
+#define DPM_TABLE_415__AcpLevel_4_MinPhases__SHIFT 0x8
+#define DPM_TABLE_415__AcpLevel_4_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_415__AcpLevel_4_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_416__AcpLevel_5_Frequency_MASK 0xffffffff
+#define DPM_TABLE_416__AcpLevel_5_Frequency__SHIFT 0x0
+#define DPM_TABLE_417__AcpLevel_5_Divider_MASK 0xff
+#define DPM_TABLE_417__AcpLevel_5_Divider__SHIFT 0x0
+#define DPM_TABLE_417__AcpLevel_5_MinPhases_MASK 0xff00
+#define DPM_TABLE_417__AcpLevel_5_MinPhases__SHIFT 0x8
+#define DPM_TABLE_417__AcpLevel_5_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_417__AcpLevel_5_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_418__AcpLevel_6_Frequency_MASK 0xffffffff
+#define DPM_TABLE_418__AcpLevel_6_Frequency__SHIFT 0x0
+#define DPM_TABLE_419__AcpLevel_6_Divider_MASK 0xff
+#define DPM_TABLE_419__AcpLevel_6_Divider__SHIFT 0x0
+#define DPM_TABLE_419__AcpLevel_6_MinPhases_MASK 0xff00
+#define DPM_TABLE_419__AcpLevel_6_MinPhases__SHIFT 0x8
+#define DPM_TABLE_419__AcpLevel_6_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_419__AcpLevel_6_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_420__AcpLevel_7_Frequency_MASK 0xffffffff
+#define DPM_TABLE_420__AcpLevel_7_Frequency__SHIFT 0x0
+#define DPM_TABLE_421__AcpLevel_7_Divider_MASK 0xff
+#define DPM_TABLE_421__AcpLevel_7_Divider__SHIFT 0x0
+#define DPM_TABLE_421__AcpLevel_7_MinPhases_MASK 0xff00
+#define DPM_TABLE_421__AcpLevel_7_MinPhases__SHIFT 0x8
+#define DPM_TABLE_421__AcpLevel_7_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_421__AcpLevel_7_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_422__SamuLevel_0_Frequency_MASK 0xffffffff
+#define DPM_TABLE_422__SamuLevel_0_Frequency__SHIFT 0x0
+#define DPM_TABLE_423__SamuLevel_0_Divider_MASK 0xff
+#define DPM_TABLE_423__SamuLevel_0_Divider__SHIFT 0x0
+#define DPM_TABLE_423__SamuLevel_0_MinPhases_MASK 0xff00
+#define DPM_TABLE_423__SamuLevel_0_MinPhases__SHIFT 0x8
+#define DPM_TABLE_423__SamuLevel_0_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_423__SamuLevel_0_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_424__SamuLevel_1_Frequency_MASK 0xffffffff
+#define DPM_TABLE_424__SamuLevel_1_Frequency__SHIFT 0x0
+#define DPM_TABLE_425__SamuLevel_1_Divider_MASK 0xff
+#define DPM_TABLE_425__SamuLevel_1_Divider__SHIFT 0x0
+#define DPM_TABLE_425__SamuLevel_1_MinPhases_MASK 0xff00
+#define DPM_TABLE_425__SamuLevel_1_MinPhases__SHIFT 0x8
+#define DPM_TABLE_425__SamuLevel_1_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_425__SamuLevel_1_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_426__SamuLevel_2_Frequency_MASK 0xffffffff
+#define DPM_TABLE_426__SamuLevel_2_Frequency__SHIFT 0x0
+#define DPM_TABLE_427__SamuLevel_2_Divider_MASK 0xff
+#define DPM_TABLE_427__SamuLevel_2_Divider__SHIFT 0x0
+#define DPM_TABLE_427__SamuLevel_2_MinPhases_MASK 0xff00
+#define DPM_TABLE_427__SamuLevel_2_MinPhases__SHIFT 0x8
+#define DPM_TABLE_427__SamuLevel_2_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_427__SamuLevel_2_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_428__SamuLevel_3_Frequency_MASK 0xffffffff
+#define DPM_TABLE_428__SamuLevel_3_Frequency__SHIFT 0x0
+#define DPM_TABLE_429__SamuLevel_3_Divider_MASK 0xff
+#define DPM_TABLE_429__SamuLevel_3_Divider__SHIFT 0x0
+#define DPM_TABLE_429__SamuLevel_3_MinPhases_MASK 0xff00
+#define DPM_TABLE_429__SamuLevel_3_MinPhases__SHIFT 0x8
+#define DPM_TABLE_429__SamuLevel_3_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_429__SamuLevel_3_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_430__SamuLevel_4_Frequency_MASK 0xffffffff
+#define DPM_TABLE_430__SamuLevel_4_Frequency__SHIFT 0x0
+#define DPM_TABLE_431__SamuLevel_4_Divider_MASK 0xff
+#define DPM_TABLE_431__SamuLevel_4_Divider__SHIFT 0x0
+#define DPM_TABLE_431__SamuLevel_4_MinPhases_MASK 0xff00
+#define DPM_TABLE_431__SamuLevel_4_MinPhases__SHIFT 0x8
+#define DPM_TABLE_431__SamuLevel_4_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_431__SamuLevel_4_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_432__SamuLevel_5_Frequency_MASK 0xffffffff
+#define DPM_TABLE_432__SamuLevel_5_Frequency__SHIFT 0x0
+#define DPM_TABLE_433__SamuLevel_5_Divider_MASK 0xff
+#define DPM_TABLE_433__SamuLevel_5_Divider__SHIFT 0x0
+#define DPM_TABLE_433__SamuLevel_5_MinPhases_MASK 0xff00
+#define DPM_TABLE_433__SamuLevel_5_MinPhases__SHIFT 0x8
+#define DPM_TABLE_433__SamuLevel_5_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_433__SamuLevel_5_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_434__SamuLevel_6_Frequency_MASK 0xffffffff
+#define DPM_TABLE_434__SamuLevel_6_Frequency__SHIFT 0x0
+#define DPM_TABLE_435__SamuLevel_6_Divider_MASK 0xff
+#define DPM_TABLE_435__SamuLevel_6_Divider__SHIFT 0x0
+#define DPM_TABLE_435__SamuLevel_6_MinPhases_MASK 0xff00
+#define DPM_TABLE_435__SamuLevel_6_MinPhases__SHIFT 0x8
+#define DPM_TABLE_435__SamuLevel_6_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_435__SamuLevel_6_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_436__SamuLevel_7_Frequency_MASK 0xffffffff
+#define DPM_TABLE_436__SamuLevel_7_Frequency__SHIFT 0x0
+#define DPM_TABLE_437__SamuLevel_7_Divider_MASK 0xff
+#define DPM_TABLE_437__SamuLevel_7_Divider__SHIFT 0x0
+#define DPM_TABLE_437__SamuLevel_7_MinPhases_MASK 0xff00
+#define DPM_TABLE_437__SamuLevel_7_MinPhases__SHIFT 0x8
+#define DPM_TABLE_437__SamuLevel_7_MinVoltage_MASK 0xffff0000
+#define DPM_TABLE_437__SamuLevel_7_MinVoltage__SHIFT 0x10
+#define DPM_TABLE_438__Ulv_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_438__Ulv_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_439__Ulv_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_439__Ulv_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_440__Ulv_VddcPhase_MASK 0xff
+#define DPM_TABLE_440__Ulv_VddcPhase__SHIFT 0x0
+#define DPM_TABLE_440__Ulv_VddcOffsetVid_MASK 0xff00
+#define DPM_TABLE_440__Ulv_VddcOffsetVid__SHIFT 0x8
+#define DPM_TABLE_440__Ulv_VddcOffset_MASK 0xffff0000
+#define DPM_TABLE_440__Ulv_VddcOffset__SHIFT 0x10
+#define DPM_TABLE_441__Ulv_Reserved_MASK 0xffffffff
+#define DPM_TABLE_441__Ulv_Reserved__SHIFT 0x0
+#define DPM_TABLE_442__SclkStepSize_MASK 0xffffffff
+#define DPM_TABLE_442__SclkStepSize__SHIFT 0x0
+#define DPM_TABLE_443__Smio_0_MASK 0xffffffff
+#define DPM_TABLE_443__Smio_0__SHIFT 0x0
+#define DPM_TABLE_444__Smio_1_MASK 0xffffffff
+#define DPM_TABLE_444__Smio_1__SHIFT 0x0
+#define DPM_TABLE_445__Smio_2_MASK 0xffffffff
+#define DPM_TABLE_445__Smio_2__SHIFT 0x0
+#define DPM_TABLE_446__Smio_3_MASK 0xffffffff
+#define DPM_TABLE_446__Smio_3__SHIFT 0x0
+#define DPM_TABLE_447__Smio_4_MASK 0xffffffff
+#define DPM_TABLE_447__Smio_4__SHIFT 0x0
+#define DPM_TABLE_448__Smio_5_MASK 0xffffffff
+#define DPM_TABLE_448__Smio_5__SHIFT 0x0
+#define DPM_TABLE_449__Smio_6_MASK 0xffffffff
+#define DPM_TABLE_449__Smio_6__SHIFT 0x0
+#define DPM_TABLE_450__Smio_7_MASK 0xffffffff
+#define DPM_TABLE_450__Smio_7__SHIFT 0x0
+#define DPM_TABLE_451__Smio_8_MASK 0xffffffff
+#define DPM_TABLE_451__Smio_8__SHIFT 0x0
+#define DPM_TABLE_452__Smio_9_MASK 0xffffffff
+#define DPM_TABLE_452__Smio_9__SHIFT 0x0
+#define DPM_TABLE_453__Smio_10_MASK 0xffffffff
+#define DPM_TABLE_453__Smio_10__SHIFT 0x0
+#define DPM_TABLE_454__Smio_11_MASK 0xffffffff
+#define DPM_TABLE_454__Smio_11__SHIFT 0x0
+#define DPM_TABLE_455__Smio_12_MASK 0xffffffff
+#define DPM_TABLE_455__Smio_12__SHIFT 0x0
+#define DPM_TABLE_456__Smio_13_MASK 0xffffffff
+#define DPM_TABLE_456__Smio_13__SHIFT 0x0
+#define DPM_TABLE_457__Smio_14_MASK 0xffffffff
+#define DPM_TABLE_457__Smio_14__SHIFT 0x0
+#define DPM_TABLE_458__Smio_15_MASK 0xffffffff
+#define DPM_TABLE_458__Smio_15__SHIFT 0x0
+#define DPM_TABLE_459__Smio_16_MASK 0xffffffff
+#define DPM_TABLE_459__Smio_16__SHIFT 0x0
+#define DPM_TABLE_460__Smio_17_MASK 0xffffffff
+#define DPM_TABLE_460__Smio_17__SHIFT 0x0
+#define DPM_TABLE_461__Smio_18_MASK 0xffffffff
+#define DPM_TABLE_461__Smio_18__SHIFT 0x0
+#define DPM_TABLE_462__Smio_19_MASK 0xffffffff
+#define DPM_TABLE_462__Smio_19__SHIFT 0x0
+#define DPM_TABLE_463__Smio_20_MASK 0xffffffff
+#define DPM_TABLE_463__Smio_20__SHIFT 0x0
+#define DPM_TABLE_464__Smio_21_MASK 0xffffffff
+#define DPM_TABLE_464__Smio_21__SHIFT 0x0
+#define DPM_TABLE_465__Smio_22_MASK 0xffffffff
+#define DPM_TABLE_465__Smio_22__SHIFT 0x0
+#define DPM_TABLE_466__Smio_23_MASK 0xffffffff
+#define DPM_TABLE_466__Smio_23__SHIFT 0x0
+#define DPM_TABLE_467__Smio_24_MASK 0xffffffff
+#define DPM_TABLE_467__Smio_24__SHIFT 0x0
+#define DPM_TABLE_468__Smio_25_MASK 0xffffffff
+#define DPM_TABLE_468__Smio_25__SHIFT 0x0
+#define DPM_TABLE_469__Smio_26_MASK 0xffffffff
+#define DPM_TABLE_469__Smio_26__SHIFT 0x0
+#define DPM_TABLE_470__Smio_27_MASK 0xffffffff
+#define DPM_TABLE_470__Smio_27__SHIFT 0x0
+#define DPM_TABLE_471__Smio_28_MASK 0xffffffff
+#define DPM_TABLE_471__Smio_28__SHIFT 0x0
+#define DPM_TABLE_472__Smio_29_MASK 0xffffffff
+#define DPM_TABLE_472__Smio_29__SHIFT 0x0
+#define DPM_TABLE_473__Smio_30_MASK 0xffffffff
+#define DPM_TABLE_473__Smio_30__SHIFT 0x0
+#define DPM_TABLE_474__Smio_31_MASK 0xffffffff
+#define DPM_TABLE_474__Smio_31__SHIFT 0x0
+#define DPM_TABLE_475__SamuBootLevel_MASK 0xff
+#define DPM_TABLE_475__SamuBootLevel__SHIFT 0x0
+#define DPM_TABLE_475__AcpBootLevel_MASK 0xff00
+#define DPM_TABLE_475__AcpBootLevel__SHIFT 0x8
+#define DPM_TABLE_475__VceBootLevel_MASK 0xff0000
+#define DPM_TABLE_475__VceBootLevel__SHIFT 0x10
+#define DPM_TABLE_475__UvdBootLevel_MASK 0xff000000
+#define DPM_TABLE_475__UvdBootLevel__SHIFT 0x18
+#define DPM_TABLE_476__SAMUInterval_MASK 0xff
+#define DPM_TABLE_476__SAMUInterval__SHIFT 0x0
+#define DPM_TABLE_476__ACPInterval_MASK 0xff00
+#define DPM_TABLE_476__ACPInterval__SHIFT 0x8
+#define DPM_TABLE_476__VCEInterval_MASK 0xff0000
+#define DPM_TABLE_476__VCEInterval__SHIFT 0x10
+#define DPM_TABLE_476__UVDInterval_MASK 0xff000000
+#define DPM_TABLE_476__UVDInterval__SHIFT 0x18
+#define DPM_TABLE_477__GraphicsInterval_MASK 0xff
+#define DPM_TABLE_477__GraphicsInterval__SHIFT 0x0
+#define DPM_TABLE_477__GraphicsThermThrottleEnable_MASK 0xff00
+#define DPM_TABLE_477__GraphicsThermThrottleEnable__SHIFT 0x8
+#define DPM_TABLE_477__GraphicsVoltageChangeEnable_MASK 0xff0000
+#define DPM_TABLE_477__GraphicsVoltageChangeEnable__SHIFT 0x10
+#define DPM_TABLE_477__GraphicsBootLevel_MASK 0xff000000
+#define DPM_TABLE_477__GraphicsBootLevel__SHIFT 0x18
+#define DPM_TABLE_478__TemperatureLimitHigh_MASK 0xffff
+#define DPM_TABLE_478__TemperatureLimitHigh__SHIFT 0x0
+#define DPM_TABLE_478__ThermalInterval_MASK 0xff0000
+#define DPM_TABLE_478__ThermalInterval__SHIFT 0x10
+#define DPM_TABLE_478__VoltageInterval_MASK 0xff000000
+#define DPM_TABLE_478__VoltageInterval__SHIFT 0x18
+#define DPM_TABLE_479__MemoryVoltageChangeEnable_MASK 0xff
+#define DPM_TABLE_479__MemoryVoltageChangeEnable__SHIFT 0x0
+#define DPM_TABLE_479__MemoryBootLevel_MASK 0xff00
+#define DPM_TABLE_479__MemoryBootLevel__SHIFT 0x8
+#define DPM_TABLE_479__TemperatureLimitLow_MASK 0xffff0000
+#define DPM_TABLE_479__TemperatureLimitLow__SHIFT 0x10
+#define DPM_TABLE_480__VddcVddciDelta_MASK 0xffff
+#define DPM_TABLE_480__VddcVddciDelta__SHIFT 0x0
+#define DPM_TABLE_480__MemoryThermThrottleEnable_MASK 0xff0000
+#define DPM_TABLE_480__MemoryThermThrottleEnable__SHIFT 0x10
+#define DPM_TABLE_480__MemoryInterval_MASK 0xff000000
+#define DPM_TABLE_480__MemoryInterval__SHIFT 0x18
+#define DPM_TABLE_481__PhaseResponseTime_MASK 0xffff
+#define DPM_TABLE_481__PhaseResponseTime__SHIFT 0x0
+#define DPM_TABLE_481__VoltageResponseTime_MASK 0xffff0000
+#define DPM_TABLE_481__VoltageResponseTime__SHIFT 0x10
+#define DPM_TABLE_482__DTEMode_MASK 0xff
+#define DPM_TABLE_482__DTEMode__SHIFT 0x0
+#define DPM_TABLE_482__DTEInterval_MASK 0xff00
+#define DPM_TABLE_482__DTEInterval__SHIFT 0x8
+#define DPM_TABLE_482__PCIeGenInterval_MASK 0xff0000
+#define DPM_TABLE_482__PCIeGenInterval__SHIFT 0x10
+#define DPM_TABLE_482__PCIeBootLinkLevel_MASK 0xff000000
+#define DPM_TABLE_482__PCIeBootLinkLevel__SHIFT 0x18
+#define DPM_TABLE_483__ThermGpio_MASK 0xff
+#define DPM_TABLE_483__ThermGpio__SHIFT 0x0
+#define DPM_TABLE_483__AcDcGpio_MASK 0xff00
+#define DPM_TABLE_483__AcDcGpio__SHIFT 0x8
+#define DPM_TABLE_483__VRHotGpio_MASK 0xff0000
+#define DPM_TABLE_483__VRHotGpio__SHIFT 0x10
+#define DPM_TABLE_483__SVI2Enable_MASK 0xff000000
+#define DPM_TABLE_483__SVI2Enable__SHIFT 0x18
+#define DPM_TABLE_484__PPM_TemperatureLimit_MASK 0xffff
+#define DPM_TABLE_484__PPM_TemperatureLimit__SHIFT 0x0
+#define DPM_TABLE_484__PPM_PkgPwrLimit_MASK 0xffff0000
+#define DPM_TABLE_484__PPM_PkgPwrLimit__SHIFT 0x10
+#define DPM_TABLE_485__TargetTdp_MASK 0xffff
+#define DPM_TABLE_485__TargetTdp__SHIFT 0x0
+#define DPM_TABLE_485__DefaultTdp_MASK 0xffff0000
+#define DPM_TABLE_485__DefaultTdp__SHIFT 0x10
+#define DPM_TABLE_486__FpsLowThreshold_MASK 0xffff
+#define DPM_TABLE_486__FpsLowThreshold__SHIFT 0x0
+#define DPM_TABLE_486__FpsHighThreshold_MASK 0xffff0000
+#define DPM_TABLE_486__FpsHighThreshold__SHIFT 0x10
+#define DPM_TABLE_487__BAPMTI_R_0_1_0_MASK 0xffff
+#define DPM_TABLE_487__BAPMTI_R_0_1_0__SHIFT 0x0
+#define DPM_TABLE_487__BAPMTI_R_0_0_0_MASK 0xffff0000
+#define DPM_TABLE_487__BAPMTI_R_0_0_0__SHIFT 0x10
+#define DPM_TABLE_488__BAPMTI_R_1_0_0_MASK 0xffff
+#define DPM_TABLE_488__BAPMTI_R_1_0_0__SHIFT 0x0
+#define DPM_TABLE_488__BAPMTI_R_0_2_0_MASK 0xffff0000
+#define DPM_TABLE_488__BAPMTI_R_0_2_0__SHIFT 0x10
+#define DPM_TABLE_489__BAPMTI_R_1_2_0_MASK 0xffff
+#define DPM_TABLE_489__BAPMTI_R_1_2_0__SHIFT 0x0
+#define DPM_TABLE_489__BAPMTI_R_1_1_0_MASK 0xffff0000
+#define DPM_TABLE_489__BAPMTI_R_1_1_0__SHIFT 0x10
+#define DPM_TABLE_490__BAPMTI_R_2_1_0_MASK 0xffff
+#define DPM_TABLE_490__BAPMTI_R_2_1_0__SHIFT 0x0
+#define DPM_TABLE_490__BAPMTI_R_2_0_0_MASK 0xffff0000
+#define DPM_TABLE_490__BAPMTI_R_2_0_0__SHIFT 0x10
+#define DPM_TABLE_491__BAPMTI_R_3_0_0_MASK 0xffff
+#define DPM_TABLE_491__BAPMTI_R_3_0_0__SHIFT 0x0
+#define DPM_TABLE_491__BAPMTI_R_2_2_0_MASK 0xffff0000
+#define DPM_TABLE_491__BAPMTI_R_2_2_0__SHIFT 0x10
+#define DPM_TABLE_492__BAPMTI_R_3_2_0_MASK 0xffff
+#define DPM_TABLE_492__BAPMTI_R_3_2_0__SHIFT 0x0
+#define DPM_TABLE_492__BAPMTI_R_3_1_0_MASK 0xffff0000
+#define DPM_TABLE_492__BAPMTI_R_3_1_0__SHIFT 0x10
+#define DPM_TABLE_493__BAPMTI_R_4_1_0_MASK 0xffff
+#define DPM_TABLE_493__BAPMTI_R_4_1_0__SHIFT 0x0
+#define DPM_TABLE_493__BAPMTI_R_4_0_0_MASK 0xffff0000
+#define DPM_TABLE_493__BAPMTI_R_4_0_0__SHIFT 0x10
+#define DPM_TABLE_494__BAPMTI_RC_0_0_0_MASK 0xffff
+#define DPM_TABLE_494__BAPMTI_RC_0_0_0__SHIFT 0x0
+#define DPM_TABLE_494__BAPMTI_R_4_2_0_MASK 0xffff0000
+#define DPM_TABLE_494__BAPMTI_R_4_2_0__SHIFT 0x10
+#define DPM_TABLE_495__BAPMTI_RC_0_2_0_MASK 0xffff
+#define DPM_TABLE_495__BAPMTI_RC_0_2_0__SHIFT 0x0
+#define DPM_TABLE_495__BAPMTI_RC_0_1_0_MASK 0xffff0000
+#define DPM_TABLE_495__BAPMTI_RC_0_1_0__SHIFT 0x10
+#define DPM_TABLE_496__BAPMTI_RC_1_1_0_MASK 0xffff
+#define DPM_TABLE_496__BAPMTI_RC_1_1_0__SHIFT 0x0
+#define DPM_TABLE_496__BAPMTI_RC_1_0_0_MASK 0xffff0000
+#define DPM_TABLE_496__BAPMTI_RC_1_0_0__SHIFT 0x10
+#define DPM_TABLE_497__BAPMTI_RC_2_0_0_MASK 0xffff
+#define DPM_TABLE_497__BAPMTI_RC_2_0_0__SHIFT 0x0
+#define DPM_TABLE_497__BAPMTI_RC_1_2_0_MASK 0xffff0000
+#define DPM_TABLE_497__BAPMTI_RC_1_2_0__SHIFT 0x10
+#define DPM_TABLE_498__BAPMTI_RC_2_2_0_MASK 0xffff
+#define DPM_TABLE_498__BAPMTI_RC_2_2_0__SHIFT 0x0
+#define DPM_TABLE_498__BAPMTI_RC_2_1_0_MASK 0xffff0000
+#define DPM_TABLE_498__BAPMTI_RC_2_1_0__SHIFT 0x10
+#define DPM_TABLE_499__BAPMTI_RC_3_1_0_MASK 0xffff
+#define DPM_TABLE_499__BAPMTI_RC_3_1_0__SHIFT 0x0
+#define DPM_TABLE_499__BAPMTI_RC_3_0_0_MASK 0xffff0000
+#define DPM_TABLE_499__BAPMTI_RC_3_0_0__SHIFT 0x10
+#define DPM_TABLE_500__BAPMTI_RC_4_0_0_MASK 0xffff
+#define DPM_TABLE_500__BAPMTI_RC_4_0_0__SHIFT 0x0
+#define DPM_TABLE_500__BAPMTI_RC_3_2_0_MASK 0xffff0000
+#define DPM_TABLE_500__BAPMTI_RC_3_2_0__SHIFT 0x10
+#define DPM_TABLE_501__BAPMTI_RC_4_2_0_MASK 0xffff
+#define DPM_TABLE_501__BAPMTI_RC_4_2_0__SHIFT 0x0
+#define DPM_TABLE_501__BAPMTI_RC_4_1_0_MASK 0xffff0000
+#define DPM_TABLE_501__BAPMTI_RC_4_1_0__SHIFT 0x10
+#define DPM_TABLE_502__GpuTjHyst_MASK 0xff
+#define DPM_TABLE_502__GpuTjHyst__SHIFT 0x0
+#define DPM_TABLE_502__GpuTjMax_MASK 0xff00
+#define DPM_TABLE_502__GpuTjMax__SHIFT 0x8
+#define DPM_TABLE_502__DTETjOffset_MASK 0xff0000
+#define DPM_TABLE_502__DTETjOffset__SHIFT 0x10
+#define DPM_TABLE_502__DTEAmbientTempBase_MASK 0xff000000
+#define DPM_TABLE_502__DTEAmbientTempBase__SHIFT 0x18
+#define DPM_TABLE_503__BootVddci_MASK 0xffff
+#define DPM_TABLE_503__BootVddci__SHIFT 0x0
+#define DPM_TABLE_503__BootVddc_MASK 0xffff0000
+#define DPM_TABLE_503__BootVddc__SHIFT 0x10
+#define DPM_TABLE_504__padding_MASK 0xff
+#define DPM_TABLE_504__padding__SHIFT 0x0
+#define DPM_TABLE_504__PccGpio_MASK 0xff00
+#define DPM_TABLE_504__PccGpio__SHIFT 0x8
+#define DPM_TABLE_504__BootMVdd_MASK 0xffff0000
+#define DPM_TABLE_504__BootMVdd__SHIFT 0x10
+#define DPM_TABLE_505__BAPM_TEMP_GRADIENT_MASK 0xffffffff
+#define DPM_TABLE_505__BAPM_TEMP_GRADIENT__SHIFT 0x0
+#define DPM_TABLE_506__LowSclkInterruptThreshold_MASK 0xffffffff
+#define DPM_TABLE_506__LowSclkInterruptThreshold__SHIFT 0x0
+#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1
+#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
+#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe
+#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
+#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000
+#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18
+#define TDC_STATUS__VDD_Boost_MASK 0xff
+#define TDC_STATUS__VDD_Boost__SHIFT 0x0
+#define TDC_STATUS__VDD_Throttle_MASK 0xff00
+#define TDC_STATUS__VDD_Throttle__SHIFT 0x8
+#define TDC_STATUS__VDDC_Boost_MASK 0xff0000
+#define TDC_STATUS__VDDC_Boost__SHIFT 0x10
+#define TDC_STATUS__VDDC_Throttle_MASK 0xff000000
+#define TDC_STATUS__VDDC_Throttle__SHIFT 0x18
+#define TDC_MV_AVERAGE__IDD_MASK 0xffff
+#define TDC_MV_AVERAGE__IDD__SHIFT 0x0
+#define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000
+#define TDC_MV_AVERAGE__IDDC__SHIFT 0x10
+#define TDC_VRM_LIMIT__IDD_MASK 0xffff
+#define TDC_VRM_LIMIT__IDD__SHIFT 0x0
+#define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000
+#define TDC_VRM_LIMIT__IDDC__SHIFT 0x10
+#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1
+#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0
+#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2
+#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1
+#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4
+#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2
+#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8
+#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3
+#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10
+#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4
+#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x20
+#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x5
+#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x40
+#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x6
+#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80
+#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7
+#define FEATURE_STATUS__BAPM_ON_MASK 0x100
+#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8
+#define FEATURE_STATUS__LPMX_ON_MASK 0x200
+#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9
+#define FEATURE_STATUS__NBDPM_ON_MASK 0x400
+#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa
+#define FEATURE_STATUS__LHTC_ON_MASK 0x800
+#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb
+#define FEATURE_STATUS__VPC_ON_MASK 0x1000
+#define FEATURE_STATUS__VPC_ON__SHIFT 0xc
+#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000
+#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd
+#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000
+#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe
+#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000
+#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf
+#define FEATURE_STATUS__AVS_ON_MASK 0x10000
+#define FEATURE_STATUS__AVS_ON__SHIFT 0x10
+#define FEATURE_STATUS__SPMI_ON_MASK 0x20000
+#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11
+#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000
+#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12
+#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000
+#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13
+#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000
+#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14
+#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000
+#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15
+#define FEATURE_STATUS__RESERVED_MASK 0xffc00000
+#define FEATURE_STATUS__RESERVED__SHIFT 0x16
+#define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff
+#define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_13__entries_0_4_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_13__entries_0_4_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_14__entries_0_4_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_14__entries_0_4_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_16__entries_0_5_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_16__entries_0_5_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_17__entries_0_5_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_17__entries_0_5_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_19__entries_1_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_19__entries_1_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_20__entries_1_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_20__entries_1_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_22__entries_1_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_22__entries_1_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_23__entries_1_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_23__entries_1_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_25__entries_1_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_25__entries_1_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_26__entries_1_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_26__entries_1_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_28__entries_1_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_28__entries_1_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_29__entries_1_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_29__entries_1_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_31__entries_1_4_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_31__entries_1_4_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_32__entries_1_4_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_32__entries_1_4_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_34__entries_1_5_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_34__entries_1_5_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_35__entries_1_5_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_35__entries_1_5_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_37__entries_2_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_37__entries_2_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_38__entries_2_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_38__entries_2_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_40__entries_2_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_40__entries_2_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_41__entries_2_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_41__entries_2_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_43__entries_2_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_43__entries_2_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_44__entries_2_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_44__entries_2_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_46__entries_2_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_46__entries_2_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_47__entries_2_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_47__entries_2_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_49__entries_2_4_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_49__entries_2_4_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_50__entries_2_4_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_50__entries_2_4_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_52__entries_2_5_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_52__entries_2_5_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_53__entries_2_5_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_53__entries_2_5_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_55__entries_3_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_55__entries_3_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_56__entries_3_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_56__entries_3_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_58__entries_3_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_58__entries_3_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_59__entries_3_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_59__entries_3_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_61__entries_3_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_61__entries_3_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_62__entries_3_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_62__entries_3_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_64__entries_3_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_64__entries_3_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_65__entries_3_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_65__entries_3_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_67__entries_3_4_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_67__entries_3_4_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_68__entries_3_4_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_68__entries_3_4_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_70__entries_3_5_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_70__entries_3_5_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_71__entries_3_5_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_71__entries_3_5_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_73__entries_4_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_73__entries_4_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_74__entries_4_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_74__entries_4_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_76__entries_4_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_76__entries_4_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_77__entries_4_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_77__entries_4_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_79__entries_4_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_79__entries_4_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_80__entries_4_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_80__entries_4_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_82__entries_4_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_82__entries_4_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_83__entries_4_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_83__entries_4_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_85__entries_4_4_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_85__entries_4_4_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_86__entries_4_4_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_86__entries_4_4_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_88__entries_4_5_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_88__entries_4_5_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_89__entries_4_5_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_89__entries_4_5_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_91__entries_5_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_91__entries_5_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_92__entries_5_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_92__entries_5_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_94__entries_5_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_94__entries_5_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_95__entries_5_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_95__entries_5_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_97__entries_5_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_97__entries_5_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_98__entries_5_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_98__entries_5_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_100__entries_5_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_100__entries_5_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_101__entries_5_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_101__entries_5_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_103__entries_5_4_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_103__entries_5_4_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_104__entries_5_4_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_104__entries_5_4_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_106__entries_5_5_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_106__entries_5_5_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_107__entries_5_5_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_107__entries_5_5_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_109__entries_6_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_109__entries_6_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_110__entries_6_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_110__entries_6_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_112__entries_6_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_112__entries_6_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_113__entries_6_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_113__entries_6_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_115__entries_6_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_115__entries_6_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_116__entries_6_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_116__entries_6_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_118__entries_6_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_118__entries_6_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_119__entries_6_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_119__entries_6_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_121__entries_6_4_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_121__entries_6_4_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_122__entries_6_4_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_122__entries_6_4_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_124__entries_6_5_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_124__entries_6_5_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_125__entries_6_5_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_125__entries_6_5_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_127__entries_7_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_127__entries_7_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_128__entries_7_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_128__entries_7_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_130__entries_7_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_130__entries_7_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_131__entries_7_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_131__entries_7_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_133__entries_7_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_133__entries_7_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_134__entries_7_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_134__entries_7_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_136__entries_7_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_136__entries_7_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_137__entries_7_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_137__entries_7_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_139__entries_7_4_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_139__entries_7_4_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_140__entries_7_4_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_140__entries_7_4_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_142__entries_7_5_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_142__entries_7_5_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_143__entries_7_5_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_143__entries_7_5_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_McArbBurstTime__SHIFT 0x18
+#define MC_REGISTERS_TABLE_1__reserved_2_MASK 0xff
+#define MC_REGISTERS_TABLE_1__reserved_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_1__reserved_1_MASK 0xff00
+#define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8
+#define MC_REGISTERS_TABLE_1__reserved_0_MASK 0xff0000
+#define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_1__last_MASK 0xff000000
+#define MC_REGISTERS_TABLE_1__last__SHIFT 0x18
+#define MC_REGISTERS_TABLE_2__address_0_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_2__address_0_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_2__address_0_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_3__address_1_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_3__address_1_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_3__address_1_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_4__address_2_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_4__address_2_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_4__address_2_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_4__address_2_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_5__address_3_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_5__address_3_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_5__address_3_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_6__address_4_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_6__address_4_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_6__address_4_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_7__address_5_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_7__address_5_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_7__address_5_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_8__address_6_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_8__address_6_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_8__address_6_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_8__address_6_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_9__address_7_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_9__address_7_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_9__address_7_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_10__address_8_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_10__address_8_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_10__address_8_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_11__address_9_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_11__address_9_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_11__address_9_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_12__address_10_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_12__address_10_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_12__address_10_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_12__address_10_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_13__address_11_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_13__address_11_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_13__address_11_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_13__address_11_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_14__address_12_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_14__address_12_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_14__address_12_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_15__address_13_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_15__address_13_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_15__address_13_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_15__address_13_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_16__address_14_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_16__address_14_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_16__address_14_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_17__address_15_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_17__address_15_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_17__address_15_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_18__data_0_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_18__data_0_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_19__data_0_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_20__data_0_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_20__data_0_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_21__data_0_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_22__data_0_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_22__data_0_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_23__data_0_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_23__data_0_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_24__data_0_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_24__data_0_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_25__data_0_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_25__data_0_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_26__data_0_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_26__data_0_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_27__data_0_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_27__data_0_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_28__data_0_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_29__data_0_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_29__data_0_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_30__data_0_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_30__data_0_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_31__data_0_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_31__data_0_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_32__data_0_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_33__data_0_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0
+#define MC_REGISTERS_TABLE_34__data_1_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_34__data_1_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_35__data_1_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_35__data_1_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_36__data_1_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_36__data_1_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_37__data_1_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_37__data_1_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_38__data_1_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_38__data_1_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_39__data_1_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_39__data_1_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_40__data_1_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_41__data_1_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_41__data_1_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_42__data_1_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_42__data_1_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_43__data_1_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_44__data_1_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_44__data_1_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_45__data_1_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_45__data_1_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_46__data_1_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_47__data_1_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_47__data_1_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_48__data_1_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_48__data_1_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_49__data_1_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_49__data_1_value_15__SHIFT 0x0
+#define MC_REGISTERS_TABLE_50__data_2_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_50__data_2_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_51__data_2_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_51__data_2_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_52__data_2_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_52__data_2_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_53__data_2_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_53__data_2_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_54__data_2_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_54__data_2_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_55__data_2_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_55__data_2_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_56__data_2_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_56__data_2_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_57__data_2_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_57__data_2_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_58__data_2_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_58__data_2_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_59__data_2_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_59__data_2_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_60__data_2_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_61__data_2_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_62__data_2_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_63__data_2_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_63__data_2_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_64__data_2_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_64__data_2_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_65__data_2_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_65__data_2_value_15__SHIFT 0x0
+#define MC_REGISTERS_TABLE_66__data_3_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_67__data_3_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_67__data_3_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_68__data_3_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_68__data_3_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_69__data_3_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_69__data_3_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_70__data_3_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_70__data_3_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_71__data_3_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_72__data_3_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_73__data_3_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_73__data_3_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_74__data_3_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_74__data_3_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_75__data_3_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_75__data_3_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_76__data_3_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_77__data_3_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_77__data_3_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_78__data_3_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_78__data_3_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_79__data_3_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_79__data_3_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_80__data_3_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_80__data_3_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_81__data_3_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_81__data_3_value_15__SHIFT 0x0
+#define MC_REGISTERS_TABLE_82__data_4_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_82__data_4_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_83__data_4_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_83__data_4_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_84__data_4_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_84__data_4_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_85__data_4_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_85__data_4_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_86__data_4_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_86__data_4_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_87__data_4_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_87__data_4_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_88__data_4_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_88__data_4_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_89__data_4_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_89__data_4_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_90__data_4_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_90__data_4_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_91__data_4_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_91__data_4_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_92__data_4_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_92__data_4_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_93__data_4_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_93__data_4_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_94__data_4_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_94__data_4_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_95__data_4_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_95__data_4_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_96__data_4_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_96__data_4_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_97__data_4_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_97__data_4_value_15__SHIFT 0x0
+#define MC_REGISTERS_TABLE_98__data_5_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_98__data_5_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_99__data_5_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_99__data_5_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_100__data_5_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_100__data_5_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_101__data_5_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_101__data_5_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_102__data_5_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_102__data_5_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_103__data_5_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_103__data_5_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_104__data_5_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_104__data_5_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_105__data_5_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_105__data_5_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_106__data_5_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_106__data_5_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_107__data_5_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_107__data_5_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_108__data_5_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_108__data_5_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_109__data_5_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_109__data_5_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_110__data_5_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_110__data_5_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_111__data_5_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_111__data_5_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_112__data_5_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_112__data_5_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_113__data_5_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_113__data_5_value_15__SHIFT 0x0
+#define FAN_TABLE_1__TempMin_MASK 0xffff
+#define FAN_TABLE_1__TempMin__SHIFT 0x0
+#define FAN_TABLE_1__FdoMode_MASK 0xffff0000
+#define FAN_TABLE_1__FdoMode__SHIFT 0x10
+#define FAN_TABLE_2__TempMax_MASK 0xffff
+#define FAN_TABLE_2__TempMax__SHIFT 0x0
+#define FAN_TABLE_2__TempMed_MASK 0xffff0000
+#define FAN_TABLE_2__TempMed__SHIFT 0x10
+#define FAN_TABLE_3__Slope2_MASK 0xffff
+#define FAN_TABLE_3__Slope2__SHIFT 0x0
+#define FAN_TABLE_3__Slope1_MASK 0xffff0000
+#define FAN_TABLE_3__Slope1__SHIFT 0x10
+#define FAN_TABLE_4__HystUp_MASK 0xffff
+#define FAN_TABLE_4__HystUp__SHIFT 0x0
+#define FAN_TABLE_4__FdoMin_MASK 0xffff0000
+#define FAN_TABLE_4__FdoMin__SHIFT 0x10
+#define FAN_TABLE_5__HystSlope_MASK 0xffff
+#define FAN_TABLE_5__HystSlope__SHIFT 0x0
+#define FAN_TABLE_5__HystDown_MASK 0xffff0000
+#define FAN_TABLE_5__HystDown__SHIFT 0x10
+#define FAN_TABLE_6__TempCurr_MASK 0xffff
+#define FAN_TABLE_6__TempCurr__SHIFT 0x0
+#define FAN_TABLE_6__TempRespLim_MASK 0xffff0000
+#define FAN_TABLE_6__TempRespLim__SHIFT 0x10
+#define FAN_TABLE_7__PwmCurr_MASK 0xffff
+#define FAN_TABLE_7__PwmCurr__SHIFT 0x0
+#define FAN_TABLE_7__SlopeCurr_MASK 0xffff0000
+#define FAN_TABLE_7__SlopeCurr__SHIFT 0x10
+#define FAN_TABLE_8__RefreshPeriod_MASK 0xffffffff
+#define FAN_TABLE_8__RefreshPeriod__SHIFT 0x0
+#define FAN_TABLE_9__Padding_MASK 0xff
+#define FAN_TABLE_9__Padding__SHIFT 0x0
+#define FAN_TABLE_9__TempSrc_MASK 0xff00
+#define FAN_TABLE_9__TempSrc__SHIFT 0x8
+#define FAN_TABLE_9__FdoMax_MASK 0xffff0000
+#define FAN_TABLE_9__FdoMax__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_4__PreVBlankGap_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_4__PreVBlankGap__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_5__VBlankTimeout_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_5__VBlankTimeout__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_6__TrainTimeGap_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_6__TrainTimeGap__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_9__AcpiDelay_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_9__AcpiDelay__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_10__G5TrainTime_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_10__G5TrainTime__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_13__HandshakeDisables_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_13__HandshakeDisables__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config_MASK 0xff00
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config__SHIFT 0x8
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config_MASK 0xff0000
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config_MASK 0xff000000
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config__SHIFT 0x18
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config_MASK 0xff
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config__SHIFT 0x8
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config_MASK 0xff000000
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config__SHIFT 0x18
+#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_18__AverageGioActivity_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_18__AverageGioActivity__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels_MASK 0xff
+#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels_MASK 0xff00
+#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels__SHIFT 0x8
+#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels_MASK 0xff0000
+#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels_MASK 0xff000000
+#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels__SHIFT 0x18
+#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels_MASK 0xff
+#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels_MASK 0xff00
+#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels__SHIFT 0x8
+#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels_MASK 0xff0000
+#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels_MASK 0xff000000
+#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels__SHIFT 0x18
+#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_26__UlvEnterCount_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_26__UlvEnterCount__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_27__UlvTime_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_27__UlvTime__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_28__Reserved_0_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_28__Reserved_0__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_29__Reserved_1_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_29__Reserved_1__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_30__Reserved_2_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_30__Reserved_2__SHIFT 0x0
+#define PM_FUSES_1__BapmVddCVidHiSidd_3_MASK 0xff
+#define PM_FUSES_1__BapmVddCVidHiSidd_3__SHIFT 0x0
+#define PM_FUSES_1__BapmVddCVidHiSidd_2_MASK 0xff00
+#define PM_FUSES_1__BapmVddCVidHiSidd_2__SHIFT 0x8
+#define PM_FUSES_1__BapmVddCVidHiSidd_1_MASK 0xff0000
+#define PM_FUSES_1__BapmVddCVidHiSidd_1__SHIFT 0x10
+#define PM_FUSES_1__BapmVddCVidHiSidd_0_MASK 0xff000000
+#define PM_FUSES_1__BapmVddCVidHiSidd_0__SHIFT 0x18
+#define PM_FUSES_2__BapmVddCVidHiSidd_7_MASK 0xff
+#define PM_FUSES_2__BapmVddCVidHiSidd_7__SHIFT 0x0
+#define PM_FUSES_2__BapmVddCVidHiSidd_6_MASK 0xff00
+#define PM_FUSES_2__BapmVddCVidHiSidd_6__SHIFT 0x8
+#define PM_FUSES_2__BapmVddCVidHiSidd_5_MASK 0xff0000
+#define PM_FUSES_2__BapmVddCVidHiSidd_5__SHIFT 0x10
+#define PM_FUSES_2__BapmVddCVidHiSidd_4_MASK 0xff000000
+#define PM_FUSES_2__BapmVddCVidHiSidd_4__SHIFT 0x18
+#define PM_FUSES_3__BapmVddCVidLoSidd_3_MASK 0xff
+#define PM_FUSES_3__BapmVddCVidLoSidd_3__SHIFT 0x0
+#define PM_FUSES_3__BapmVddCVidLoSidd_2_MASK 0xff00
+#define PM_FUSES_3__BapmVddCVidLoSidd_2__SHIFT 0x8
+#define PM_FUSES_3__BapmVddCVidLoSidd_1_MASK 0xff0000
+#define PM_FUSES_3__BapmVddCVidLoSidd_1__SHIFT 0x10
+#define PM_FUSES_3__BapmVddCVidLoSidd_0_MASK 0xff000000
+#define PM_FUSES_3__BapmVddCVidLoSidd_0__SHIFT 0x18
+#define PM_FUSES_4__BapmVddCVidLoSidd_7_MASK 0xff
+#define PM_FUSES_4__BapmVddCVidLoSidd_7__SHIFT 0x0
+#define PM_FUSES_4__BapmVddCVidLoSidd_6_MASK 0xff00
+#define PM_FUSES_4__BapmVddCVidLoSidd_6__SHIFT 0x8
+#define PM_FUSES_4__BapmVddCVidLoSidd_5_MASK 0xff0000
+#define PM_FUSES_4__BapmVddCVidLoSidd_5__SHIFT 0x10
+#define PM_FUSES_4__BapmVddCVidLoSidd_4_MASK 0xff000000
+#define PM_FUSES_4__BapmVddCVidLoSidd_4__SHIFT 0x18
+#define PM_FUSES_5__VddCVid_3_MASK 0xff
+#define PM_FUSES_5__VddCVid_3__SHIFT 0x0
+#define PM_FUSES_5__VddCVid_2_MASK 0xff00
+#define PM_FUSES_5__VddCVid_2__SHIFT 0x8
+#define PM_FUSES_5__VddCVid_1_MASK 0xff0000
+#define PM_FUSES_5__VddCVid_1__SHIFT 0x10
+#define PM_FUSES_5__VddCVid_0_MASK 0xff000000
+#define PM_FUSES_5__VddCVid_0__SHIFT 0x18
+#define PM_FUSES_6__VddCVid_7_MASK 0xff
+#define PM_FUSES_6__VddCVid_7__SHIFT 0x0
+#define PM_FUSES_6__VddCVid_6_MASK 0xff00
+#define PM_FUSES_6__VddCVid_6__SHIFT 0x8
+#define PM_FUSES_6__VddCVid_5_MASK 0xff0000
+#define PM_FUSES_6__VddCVid_5__SHIFT 0x10
+#define PM_FUSES_6__VddCVid_4_MASK 0xff000000
+#define PM_FUSES_6__VddCVid_4__SHIFT 0x18
+#define PM_FUSES_7__SviLoadLineOffsetVddC_MASK 0xff
+#define PM_FUSES_7__SviLoadLineOffsetVddC__SHIFT 0x0
+#define PM_FUSES_7__SviLoadLineTrimVddC_MASK 0xff00
+#define PM_FUSES_7__SviLoadLineTrimVddC__SHIFT 0x8
+#define PM_FUSES_7__SviLoadLineVddC_MASK 0xff0000
+#define PM_FUSES_7__SviLoadLineVddC__SHIFT 0x10
+#define PM_FUSES_7__SviLoadLineEn_MASK 0xff000000
+#define PM_FUSES_7__SviLoadLineEn__SHIFT 0x18
+#define PM_FUSES_8__TDC_MAWt_MASK 0xff
+#define PM_FUSES_8__TDC_MAWt__SHIFT 0x0
+#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc_MASK 0xff00
+#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT 0x8
+#define PM_FUSES_8__TDC_VDDC_PkgLimit_MASK 0xffff0000
+#define PM_FUSES_8__TDC_VDDC_PkgLimit__SHIFT 0x10
+#define PM_FUSES_9__Reserved_MASK 0xff
+#define PM_FUSES_9__Reserved__SHIFT 0x0
+#define PM_FUSES_9__LPMLTemperatureMax_MASK 0xff00
+#define PM_FUSES_9__LPMLTemperatureMax__SHIFT 0x8
+#define PM_FUSES_9__LPMLTemperatureMin_MASK 0xff0000
+#define PM_FUSES_9__LPMLTemperatureMin__SHIFT 0x10
+#define PM_FUSES_9__TdcWaterfallCtl_MASK 0xff000000
+#define PM_FUSES_9__TdcWaterfallCtl__SHIFT 0x18
+#define PM_FUSES_10__BapmVddCVidHiSidd2_3_MASK 0xff
+#define PM_FUSES_10__BapmVddCVidHiSidd2_3__SHIFT 0x0
+#define PM_FUSES_10__BapmVddCVidHiSidd2_2_MASK 0xff00
+#define PM_FUSES_10__BapmVddCVidHiSidd2_2__SHIFT 0x8
+#define PM_FUSES_10__BapmVddCVidHiSidd2_1_MASK 0xff0000
+#define PM_FUSES_10__BapmVddCVidHiSidd2_1__SHIFT 0x10
+#define PM_FUSES_10__BapmVddCVidHiSidd2_0_MASK 0xff000000
+#define PM_FUSES_10__BapmVddCVidHiSidd2_0__SHIFT 0x18
+#define PM_FUSES_11__BapmVddCVidHiSidd2_7_MASK 0xff
+#define PM_FUSES_11__BapmVddCVidHiSidd2_7__SHIFT 0x0
+#define PM_FUSES_11__BapmVddCVidHiSidd2_6_MASK 0xff00
+#define PM_FUSES_11__BapmVddCVidHiSidd2_6__SHIFT 0x8
+#define PM_FUSES_11__BapmVddCVidHiSidd2_5_MASK 0xff0000
+#define PM_FUSES_11__BapmVddCVidHiSidd2_5__SHIFT 0x10
+#define PM_FUSES_11__BapmVddCVidHiSidd2_4_MASK 0xff000000
+#define PM_FUSES_11__BapmVddCVidHiSidd2_4__SHIFT 0x18
+#define PM_FUSES_12__FuzzyFan_ErrorRateSetDelta_MASK 0xffff
+#define PM_FUSES_12__FuzzyFan_ErrorRateSetDelta__SHIFT 0x0
+#define PM_FUSES_12__FuzzyFan_ErrorSetDelta_MASK 0xffff0000
+#define PM_FUSES_12__FuzzyFan_ErrorSetDelta__SHIFT 0x10
+#define PM_FUSES_13__Reserved6_MASK 0xffff
+#define PM_FUSES_13__Reserved6__SHIFT 0x0
+#define PM_FUSES_13__FuzzyFan_PwmSetDelta_MASK 0xffff0000
+#define PM_FUSES_13__FuzzyFan_PwmSetDelta__SHIFT 0x10
+#define PM_FUSES_14__GnbLPML_3_MASK 0xff
+#define PM_FUSES_14__GnbLPML_3__SHIFT 0x0
+#define PM_FUSES_14__GnbLPML_2_MASK 0xff00
+#define PM_FUSES_14__GnbLPML_2__SHIFT 0x8
+#define PM_FUSES_14__GnbLPML_1_MASK 0xff0000
+#define PM_FUSES_14__GnbLPML_1__SHIFT 0x10
+#define PM_FUSES_14__GnbLPML_0_MASK 0xff000000
+#define PM_FUSES_14__GnbLPML_0__SHIFT 0x18
+#define PM_FUSES_15__GnbLPML_7_MASK 0xff
+#define PM_FUSES_15__GnbLPML_7__SHIFT 0x0
+#define PM_FUSES_15__GnbLPML_6_MASK 0xff00
+#define PM_FUSES_15__GnbLPML_6__SHIFT 0x8
+#define PM_FUSES_15__GnbLPML_5_MASK 0xff0000
+#define PM_FUSES_15__GnbLPML_5__SHIFT 0x10
+#define PM_FUSES_15__GnbLPML_4_MASK 0xff000000
+#define PM_FUSES_15__GnbLPML_4__SHIFT 0x18
+#define PM_FUSES_16__GnbLPML_11_MASK 0xff
+#define PM_FUSES_16__GnbLPML_11__SHIFT 0x0
+#define PM_FUSES_16__GnbLPML_10_MASK 0xff00
+#define PM_FUSES_16__GnbLPML_10__SHIFT 0x8
+#define PM_FUSES_16__GnbLPML_9_MASK 0xff0000
+#define PM_FUSES_16__GnbLPML_9__SHIFT 0x10
+#define PM_FUSES_16__GnbLPML_8_MASK 0xff000000
+#define PM_FUSES_16__GnbLPML_8__SHIFT 0x18
+#define PM_FUSES_17__GnbLPML_15_MASK 0xff
+#define PM_FUSES_17__GnbLPML_15__SHIFT 0x0
+#define PM_FUSES_17__GnbLPML_14_MASK 0xff00
+#define PM_FUSES_17__GnbLPML_14__SHIFT 0x8
+#define PM_FUSES_17__GnbLPML_13_MASK 0xff0000
+#define PM_FUSES_17__GnbLPML_13__SHIFT 0x10
+#define PM_FUSES_17__GnbLPML_12_MASK 0xff000000
+#define PM_FUSES_17__GnbLPML_12__SHIFT 0x18
+#define PM_FUSES_18__Reserved1_1_MASK 0xff
+#define PM_FUSES_18__Reserved1_1__SHIFT 0x0
+#define PM_FUSES_18__Reserved1_0_MASK 0xff00
+#define PM_FUSES_18__Reserved1_0__SHIFT 0x8
+#define PM_FUSES_18__GnbLPMLMinVid_MASK 0xff0000
+#define PM_FUSES_18__GnbLPMLMinVid__SHIFT 0x10
+#define PM_FUSES_18__GnbLPMLMaxVid_MASK 0xff000000
+#define PM_FUSES_18__GnbLPMLMaxVid__SHIFT 0x18
+#define PM_FUSES_19__BapmVddCBaseLeakageLoSidd_MASK 0xffff
+#define PM_FUSES_19__BapmVddCBaseLeakageLoSidd__SHIFT 0x0
+#define PM_FUSES_19__BapmVddCBaseLeakageHiSidd_MASK 0xffff0000
+#define PM_FUSES_19__BapmVddCBaseLeakageHiSidd__SHIFT 0x10
+#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_0__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_1__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_2__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_3__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_4__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_5__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_6__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_7__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_8__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_9__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_10__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_11__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_12__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_13__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_14__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_15__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_16__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_17__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_18__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_19__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_20__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_21__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_22__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_23__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_24__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_25__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_26__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_27__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_28__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_29__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_30__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_31__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_32__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_33__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_34__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_35__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_36__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_37__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_38__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_39__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_40__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_41__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_42__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_43__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_44__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_45__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_46__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_47__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_48__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_49__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_50__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_51__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_52__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_53__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_54__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_55__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_56__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_57__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_58__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_59__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_60__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_61__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_62__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_63__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_64__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_65__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_66__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_67__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_68__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_69__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_70__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_71__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_72__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_73__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_74__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_75__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_76__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_77__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_78__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_79__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_80__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_81__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_82__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_83__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_84__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_85__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_86__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_87__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_88__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_89__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_90__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_91__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_92__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_93__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_94__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_95__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_96__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_97__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_98__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_99__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_100__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_101__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_102__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_103__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_104__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_105__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_106__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_107__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_108__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_109__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_110__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_111__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_112__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_113__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_114__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_115__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_116__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_117__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_118__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_119__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_120__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_121__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_122__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_123__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_124__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_125__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_126__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_127__DATA__SHIFT 0x0
+#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1
+#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0
+#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2
+#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2
+#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8
+#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3
+#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10
+#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8
+#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000
+#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10
+#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000
+#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18
+#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000
+#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b
+#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000
+#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c
+#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1
+#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0
+#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2
+#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3
+#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x7
+#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x0
+#define CG_THERMAL_CTRL__THERM_INC_CLK_MASK 0x8
+#define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT 0x3
+#define CG_THERMAL_CTRL__SPARE_MASK 0x3ff0
+#define CG_THERMAL_CTRL__SPARE__SHIFT 0x4
+#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x3fc000
+#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0xe
+#define CG_THERMAL_CTRL__RESERVED_MASK 0x1c00000
+#define CG_THERMAL_CTRL__RESERVED__SHIFT 0x16
+#define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK 0x2000000
+#define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT 0x19
+#define CG_THERMAL_CTRL__CTF_PAD_EN_MASK 0x4000000
+#define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT 0x1a
+#define CG_THERMAL_STATUS__SPARE_MASK 0x1ff
+#define CG_THERMAL_STATUS__SPARE__SHIFT 0x0
+#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x1fe00
+#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9
+#define CG_THERMAL_STATUS__THERM_ALERT_MASK 0x20000
+#define CG_THERMAL_STATUS__THERM_ALERT__SHIFT 0x11
+#define CG_THERMAL_STATUS__GEN_STATUS_MASK 0x3c0000
+#define CG_THERMAL_STATUS__GEN_STATUS__SHIFT 0x12
+#define CG_THERMAL_INT__DIG_THERM_CTF_MASK 0xff
+#define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT 0x0
+#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0xff00
+#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x8
+#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0xff0000
+#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x10
+#define CG_THERMAL_INT__THERM_INT_MASK_MASK 0xf000000
+#define CG_THERMAL_INT__THERM_INT_MASK__SHIFT 0x18
+#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0xf
+#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0
+#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0xf0
+#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4
+#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x200
+#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9
+#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000
+#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14
+#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x1ff
+#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0
+#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x3fe00
+#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9
+#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0xff
+#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0
+#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0xff00
+#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8
+#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x10000
+#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10
+#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x7e0000
+#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x800000
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xff000000
+#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18
+#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0xff
+#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0
+#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00
+#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8
+#define CG_FDO_CTRL1__M_MASK 0xff0000
+#define CG_FDO_CTRL1__M__SHIFT 0x10
+#define CG_FDO_CTRL1__RESERVED_MASK 0x3f000000
+#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18
+#define CG_FDO_CTRL1__FDO_PWRDNB_MASK 0x40000000
+#define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT 0x1e
+#define CG_FDO_CTRL2__TMIN_MASK 0xff
+#define CG_FDO_CTRL2__TMIN__SHIFT 0x0
+#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x700
+#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8
+#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x3800
+#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb
+#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x1c000
+#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe
+#define CG_FDO_CTRL2__TMAX_MASK 0x1fe0000
+#define CG_FDO_CTRL2__TMAX__SHIFT 0x11
+#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xfe000000
+#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19
+#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x7
+#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0
+#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8
+#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3
+#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff
+#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0
+#define CC_THM_STRAPS0__TMON0_BGADJ_MASK 0x1fe
+#define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT 0x1
+#define CC_THM_STRAPS0__TMON1_BGADJ_MASK 0x1fe00
+#define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT 0x9
+#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK 0x20000
+#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT 0x11
+#define CC_THM_STRAPS0__NUM_ACQ_MASK 0x1c0000
+#define CC_THM_STRAPS0__NUM_ACQ__SHIFT 0x12
+#define CC_THM_STRAPS0__TMON_CLK_SEL_MASK 0xe00000
+#define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT 0x15
+#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK 0x1000000
+#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT 0x18
+#define CC_THM_STRAPS0__CTF_DISABLE_MASK 0x2000000
+#define CC_THM_STRAPS0__CTF_DISABLE__SHIFT 0x19
+#define CC_THM_STRAPS0__TMON0_DISABLE_MASK 0x4000000
+#define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT 0x1a
+#define CC_THM_STRAPS0__TMON1_DISABLE_MASK 0x8000000
+#define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT 0x1b
+#define CC_THM_STRAPS0__TMON2_DISABLE_MASK 0x10000000
+#define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT 0x1c
+#define CC_THM_STRAPS0__TMON3_DISABLE_MASK 0x20000000
+#define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d
+#define CC_THM_STRAPS0__UNUSED_MASK 0x80000000
+#define CC_THM_STRAPS0__UNUSED__SHIFT 0x1f
+#define THM_TMON0_RDIL0_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL1_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL2_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL3_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL4_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL5_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL6_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL7_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL8_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL9_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL10_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL11_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL12_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL13_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL14_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL15_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR0_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR1_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR2_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR3_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR4_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR5_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR6_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR7_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR8_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR9_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR10_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR11_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR12_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR13_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR14_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR15_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL0_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL0_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL0_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL1_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL1_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL1_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL2_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL2_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL2_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL3_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL3_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL3_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL4_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL4_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL4_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL5_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL5_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL5_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL6_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL6_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL6_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL7_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL7_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL7_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL8_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL8_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL8_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL9_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL9_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL9_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL10_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL10_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL10_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL11_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL11_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL11_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL12_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL12_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL12_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL13_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL13_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL13_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL14_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL14_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL14_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL15_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL15_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL15_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR0_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR0_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR0_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR1_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR1_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR1_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR2_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR2_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR2_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR3_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR3_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR3_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR4_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR4_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR4_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR5_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR5_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR5_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR6_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR6_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR6_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR7_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR7_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR7_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR8_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR8_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR8_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR9_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR9_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR9_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR10_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR10_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR10_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR11_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR11_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR11_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR12_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR12_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR12_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR13_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR13_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR13_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR14_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR14_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR14_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR15_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR15_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR15_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_INT_DATA__Z_MASK 0x7ff
+#define THM_TMON0_INT_DATA__Z__SHIFT 0x0
+#define THM_TMON0_INT_DATA__VALID_MASK 0x800
+#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_INT_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_INT_DATA__Z_MASK 0x7ff
+#define THM_TMON1_INT_DATA__Z__SHIFT 0x0
+#define THM_TMON1_INT_DATA__VALID_MASK 0x800
+#define THM_TMON1_INT_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_INT_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_INT_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x1f
+#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0
+#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0xffe0
+#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5
+#define THM_TMON1_DEBUG__DEBUG_RDI_MASK 0x1f
+#define THM_TMON1_DEBUG__DEBUG_RDI__SHIFT 0x0
+#define THM_TMON1_DEBUG__DEBUG_Z_MASK 0xffe0
+#define THM_TMON1_DEBUG__DEBUG_Z__SHIFT 0x5
+#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1
+#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0
+#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2
+#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3
+#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40
+#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6
+#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100
+#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8
+#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200
+#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9
+#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400
+#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa
+#define GENERAL_PWRMGT__SPARE11_MASK 0x800
+#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb
+#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000
+#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe
+#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000
+#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf
+#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000
+#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10
+#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000
+#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11
+#define GENERAL_PWRMGT__SPARE18_MASK 0x40000
+#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12
+#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000
+#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13
+#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000
+#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17
+#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000
+#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b
+#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000
+#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c
+#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3
+#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0
+#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4
+#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2
+#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8
+#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3
+#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10
+#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4
+#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0
+#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5
+#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1
+#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0
+#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1_MASK 0x2
+#define SCLK_PWRMGT_CNTL__SCLK_LOW_D1__SHIFT 0x1
+#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN_MASK 0x4
+#define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN__SHIFT 0x2
+#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10
+#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4
+#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20
+#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5
+#define SCLK_PWRMGT_CNTL__RESERVED_0_MASK 0x40
+#define SCLK_PWRMGT_CNTL__RESERVED_0__SHIFT 0x6
+#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN_MASK 0x80
+#define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN__SHIFT 0x7
+#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON_MASK 0x100
+#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON__SHIFT 0x8
+#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF_MASK 0x200
+#define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF__SHIFT 0x9
+#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF_MASK 0x400
+#define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF__SHIFT 0xa
+#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1_MASK 0x800
+#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1__SHIFT 0xb
+#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2_MASK 0x1000
+#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2__SHIFT 0xc
+#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3_MASK 0x2000
+#define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3__SHIFT 0xd
+#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000
+#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe
+#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000
+#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf
+#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000
+#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10
+#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000
+#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15
+#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL_MASK 0x400000
+#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL__SHIFT 0x16
+#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN_MASK 0x800000
+#define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN__SHIFT 0x17
+#define SCLK_PWRMGT_CNTL__RESERVED_3_MASK 0x1000000
+#define SCLK_PWRMGT_CNTL__RESERVED_3__SHIFT 0x18
+#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN_MASK 0x2000000
+#define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN__SHIFT 0x19
+#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT_MASK 0x10000000
+#define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT__SHIFT 0x1c
+#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT_MASK 0x20000000
+#define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT__SHIFT 0x1d
+#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN_MASK 0x40000000
+#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN__SHIFT 0x1e
+#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE_MASK 0x80000000
+#define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE__SHIFT 0x1f
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf
+#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
+#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0
+#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4
+#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00
+#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8
+#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000
+#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf
+#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000
+#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c
+#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff
+#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0
+#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f
+#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0
+#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80
+#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7
+#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
+#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
+#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
+#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
+#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000
+#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11
+#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000
+#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12
+#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000
+#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13
+#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000
+#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14
+#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000
+#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15
+#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000
+#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16
+#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000
+#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17
+#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000
+#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19
+#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000
+#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a
+#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000
+#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b
+#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000
+#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c
+#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000
+#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d
+#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000
+#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e
+#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
+#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2
+#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1
+#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4
+#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2
+#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8
+#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10
+#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4
+#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40
+#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6
+#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80
+#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7
+#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100
+#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8
+#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200
+#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9
+#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400
+#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa
+#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800
+#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe
+#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000
+#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15
+#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000
+#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14
+#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
+#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
+#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
+#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
+#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
+#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
+#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000
+#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10
+#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
+#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
+#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1
+#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0
+#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2
+#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3
+#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10
+#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4
+#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20
+#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd
+#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000
+#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe
+#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000
+#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13
+#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000
+#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14
+#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000
+#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c
+#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff
+#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0
+#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000
+#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10
+#define SCLK_MIN_DIV__FRACV_MASK 0xfff
+#define SCLK_MIN_DIV__FRACV__SHIFT 0x0
+#define SCLK_MIN_DIV__INTV_MASK 0x7f000
+#define SCLK_MIN_DIV__INTV__SHIFT 0xc
+#define LCAC_SX0_CNTL__SX0_ENABLE_MASK 0x1
+#define LCAC_SX0_CNTL__SX0_ENABLE__SHIFT 0x0
+#define LCAC_SX0_CNTL__SX0_THRESHOLD_MASK 0x1fffe
+#define LCAC_SX0_CNTL__SX0_THRESHOLD__SHIFT 0x1
+#define LCAC_SX0_CNTL__SX0_BLOCK_ID_MASK 0x3e0000
+#define LCAC_SX0_CNTL__SX0_BLOCK_ID__SHIFT 0x11
+#define LCAC_SX0_CNTL__SX0_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_SX0_CNTL__SX0_SIGNAL_ID__SHIFT 0x16
+#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL_MASK 0xffffffff
+#define LCAC_SX0_OVR_SEL__SX0_OVR_SEL__SHIFT 0x0
+#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL_MASK 0xffffffff
+#define LCAC_SX0_OVR_VAL__SX0_OVR_VAL__SHIFT 0x0
+#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1
+#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0
+#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1
+#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0
+#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0
+#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1
+#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0
+#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1
+#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0
+#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0
+#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1
+#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0
+#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1
+#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0
+#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0
+#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1
+#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0
+#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1
+#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0
+#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0
+#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1
+#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0
+#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe
+#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1
+#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000
+#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11
+#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16
+#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff
+#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0
+#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff
+#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0
+#define ROM_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define ROM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define ROM_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define ROM_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define ROM_CNTL__SCK_OVERWRITE_MASK 0x2
+#define ROM_CNTL__SCK_OVERWRITE__SHIFT 0x1
+#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x4
+#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x2
+#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME_MASK 0xff00
+#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME__SHIFT 0x8
+#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME_MASK 0xff0000
+#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME__SHIFT 0x10
+#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0xf000000
+#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18
+#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK_MASK 0xf0000000
+#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK__SHIFT 0x1c
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0xffffff
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x1000000
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x2000000
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0xc000000
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a
+#define ROM_STATUS__ROM_BUSY_MASK 0x1
+#define ROM_STATUS__ROM_BUSY__SHIFT 0x0
+#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0xf
+#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0
+#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
+#define ROM_INDEX__ROM_INDEX_MASK 0xffffff
+#define ROM_INDEX__ROM_INDEX__SHIFT 0x0
+#define ROM_DATA__ROM_DATA_MASK 0xffffffff
+#define ROM_DATA__ROM_DATA__SHIFT 0x0
+#define ROM_START__ROM_START_MASK 0xffffff
+#define ROM_START__ROM_START__SHIFT 0x0
+#define ROM_SW_CNTL__DATA_SIZE_MASK 0xffff
+#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0
+#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x30000
+#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10
+#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x40000
+#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12
+#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x1
+#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0
+#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0xff
+#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0
+#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xffffff00
+#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8
+#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
+
+#endif /* SMU_7_1_0_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h
new file mode 100644
index 000000000000..3014d4a58c43
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_d.h
@@ -0,0 +1,1123 @@
+/*
+ * SMU_7_1_1 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef SMU_7_1_1_D_H
+#define SMU_7_1_1_D_H
+
+#define mmGCK_SMC_IND_INDEX 0x80
+#define mmGCK0_GCK_SMC_IND_INDEX 0x80
+#define mmGCK1_GCK_SMC_IND_INDEX 0x82
+#define mmGCK2_GCK_SMC_IND_INDEX 0x84
+#define mmGCK3_GCK_SMC_IND_INDEX 0x86
+#define mmGCK_SMC_IND_DATA 0x81
+#define mmGCK0_GCK_SMC_IND_DATA 0x81
+#define mmGCK1_GCK_SMC_IND_DATA 0x83
+#define mmGCK2_GCK_SMC_IND_DATA 0x85
+#define mmGCK3_GCK_SMC_IND_DATA 0x87
+#define ixCG_DCLK_CNTL 0xc050009c
+#define ixCG_DCLK_STATUS 0xc05000a0
+#define ixCG_VCLK_CNTL 0xc05000a4
+#define ixCG_VCLK_STATUS 0xc05000a8
+#define ixCG_ECLK_CNTL 0xc05000ac
+#define ixCG_ECLK_STATUS 0xc05000b0
+#define ixCG_ACLK_CNTL 0xc05000dc
+#define ixGCK_DFS_BYPASS_CNTL 0xc0500118
+#define ixCG_SPLL_FUNC_CNTL 0xc0500140
+#define ixCG_SPLL_FUNC_CNTL_2 0xc0500144
+#define ixCG_SPLL_FUNC_CNTL_3 0xc0500148
+#define ixCG_SPLL_FUNC_CNTL_4 0xc050014c
+#define ixCG_SPLL_FUNC_CNTL_5 0xc0500150
+#define ixCG_SPLL_FUNC_CNTL_6 0xc0500154
+#define ixCG_SPLL_FUNC_CNTL_7 0xc0500158
+#define ixSPLL_CNTL_MODE 0xc0500160
+#define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164
+#define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168
+#define ixMPLL_BYPASSCLK_SEL 0xc050019c
+#define ixCG_CLKPIN_CNTL 0xc05001a0
+#define ixCG_CLKPIN_CNTL_2 0xc05001a4
+#define ixCG_CLKPIN_CNTL_DC 0xc0500204
+#define ixTHM_CLK_CNTL 0xc05001a8
+#define ixMISC_CLK_CTRL 0xc05001ac
+#define ixGCK_PLL_TEST_CNTL 0xc05001c0
+#define ixGCK_PLL_TEST_CNTL_2 0xc05001c4
+#define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8
+#define mmSMC_IND_INDEX 0x80
+#define mmSMC0_SMC_IND_INDEX 0x80
+#define mmSMC1_SMC_IND_INDEX 0x82
+#define mmSMC2_SMC_IND_INDEX 0x84
+#define mmSMC3_SMC_IND_INDEX 0x86
+#define mmSMC_IND_DATA 0x81
+#define mmSMC0_SMC_IND_DATA 0x81
+#define mmSMC1_SMC_IND_DATA 0x83
+#define mmSMC2_SMC_IND_DATA 0x85
+#define mmSMC3_SMC_IND_DATA 0x87
+#define mmSMC_IND_INDEX_0 0x80
+#define mmSMC_IND_DATA_0 0x81
+#define mmSMC_IND_INDEX_1 0x82
+#define mmSMC_IND_DATA_1 0x83
+#define mmSMC_IND_INDEX_2 0x84
+#define mmSMC_IND_DATA_2 0x85
+#define mmSMC_IND_INDEX_3 0x86
+#define mmSMC_IND_DATA_3 0x87
+#define mmSMC_IND_INDEX_4 0x88
+#define mmSMC_IND_DATA_4 0x89
+#define mmSMC_IND_INDEX_5 0x8a
+#define mmSMC_IND_DATA_5 0x8b
+#define mmSMC_IND_INDEX_6 0x8c
+#define mmSMC_IND_DATA_6 0x8d
+#define mmSMC_IND_INDEX_7 0x8e
+#define mmSMC_IND_DATA_7 0x8f
+#define mmSMC_IND_ACCESS_CNTL 0x92
+#define mmSMC_MESSAGE_0 0x94
+#define mmSMC_RESP_0 0x95
+#define mmSMC_MESSAGE_1 0x96
+#define mmSMC_RESP_1 0x97
+#define mmSMC_MESSAGE_2 0x98
+#define mmSMC_RESP_2 0x99
+#define mmSMC_MESSAGE_3 0x9a
+#define mmSMC_RESP_3 0x9b
+#define mmSMC_MESSAGE_4 0x9c
+#define mmSMC_RESP_4 0x9d
+#define mmSMC_MESSAGE_5 0x9e
+#define mmSMC_RESP_5 0x9f
+#define mmSMC_MESSAGE_6 0xa0
+#define mmSMC_RESP_6 0xa1
+#define mmSMC_MESSAGE_7 0xa2
+#define mmSMC_RESP_7 0xa3
+#define mmSMC_MSG_ARG_0 0xa4
+#define mmSMC_MSG_ARG_1 0xa5
+#define mmSMC_MSG_ARG_2 0xa6
+#define mmSMC_MSG_ARG_3 0xa7
+#define mmSMC_MSG_ARG_4 0xa8
+#define mmSMC_MSG_ARG_5 0xa9
+#define mmSMC_MSG_ARG_6 0xaa
+#define mmSMC_MSG_ARG_7 0xab
+#define mmSMC_MESSAGE_8 0xb5
+#define mmSMC_RESP_8 0xb6
+#define mmSMC_MESSAGE_9 0xb7
+#define mmSMC_RESP_9 0xb8
+#define mmSMC_MESSAGE_10 0xb9
+#define mmSMC_RESP_10 0xba
+#define mmSMC_MESSAGE_11 0xbb
+#define mmSMC_RESP_11 0xbc
+#define mmSMC_MSG_ARG_8 0xbd
+#define mmSMC_MSG_ARG_9 0xbe
+#define mmSMC_MSG_ARG_10 0xbf
+#define mmSMC_MSG_ARG_11 0x93
+#define ixSMC_SYSCON_RESET_CNTL 0x80000000
+#define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004
+#define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008
+#define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c
+#define ixSMC_SYSCON_MISC_CNTL 0x80000010
+#define ixSMC_SYSCON_MSG_ARG_0 0x80000068
+#define ixSMC_PC_C 0x80000370
+#define ixSMC_SCRATCH9 0x80000424
+#define mmGPIOPAD_SW_INT_STAT 0x180
+#define mmGPIOPAD_STRENGTH 0x181
+#define mmGPIOPAD_MASK 0x182
+#define mmGPIOPAD_A 0x183
+#define mmGPIOPAD_EN 0x184
+#define mmGPIOPAD_Y 0x185
+#define mmGPIOPAD_PINSTRAPS 0x186
+#define mmGPIOPAD_INT_STAT_EN 0x187
+#define mmGPIOPAD_INT_STAT 0x188
+#define mmGPIOPAD_INT_STAT_AK 0x189
+#define mmGPIOPAD_INT_EN 0x18a
+#define mmGPIOPAD_INT_TYPE 0x18b
+#define mmGPIOPAD_INT_POLARITY 0x18c
+#define mmGPIOPAD_EXTERN_TRIG_CNTL 0x18d
+#define mmGPIOPAD_RCVR_SEL 0x191
+#define mmGPIOPAD_PU_EN 0x192
+#define mmGPIOPAD_PD_EN 0x193
+#define mmCG_FPS_CNT 0x1b6
+#define mmSMU_IND_INDEX_0 0x1a6
+#define mmSMU_IND_DATA_0 0x1a7
+#define mmSMU_IND_INDEX_1 0x1a8
+#define mmSMU_IND_DATA_1 0x1a9
+#define mmSMU_IND_INDEX_2 0x1aa
+#define mmSMU_IND_DATA_2 0x1ab
+#define mmSMU_IND_INDEX_3 0x1ac
+#define mmSMU_IND_DATA_3 0x1ad
+#define mmSMU_IND_INDEX_4 0x1ae
+#define mmSMU_IND_DATA_4 0x1af
+#define mmSMU_IND_INDEX_5 0x1b0
+#define mmSMU_IND_DATA_5 0x1b1
+#define mmSMU_IND_INDEX_6 0x1b2
+#define mmSMU_IND_DATA_6 0x1b3
+#define mmSMU_IND_INDEX_7 0x1b4
+#define mmSMU_IND_DATA_7 0x1b5
+#define mmSMU_SMC_IND_INDEX 0x80
+#define mmSMU0_SMU_SMC_IND_INDEX 0x80
+#define mmSMU1_SMU_SMC_IND_INDEX 0x82
+#define mmSMU2_SMU_SMC_IND_INDEX 0x84
+#define mmSMU3_SMU_SMC_IND_INDEX 0x86
+#define mmSMU_SMC_IND_DATA 0x81
+#define mmSMU0_SMU_SMC_IND_DATA 0x81
+#define mmSMU1_SMU_SMC_IND_DATA 0x83
+#define mmSMU2_SMU_SMC_IND_DATA 0x85
+#define mmSMU3_SMU_SMC_IND_DATA 0x87
+#define ixRCU_UC_EVENTS 0xc0000004
+#define ixRCU_MISC_CTRL 0xc0000010
+#define ixCC_RCU_FUSES 0xc00c0000
+#define ixCC_SMU_MISC_FUSES 0xc00c0004
+#define ixCC_SCLK_VID_FUSES 0xc00c0008
+#define ixCC_GIO_IOCCFG_FUSES 0xc00c000c
+#define ixCC_GIO_IOC_FUSES 0xc00c0010
+#define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c
+#define ixCC_TST_ID_STRAPS 0xc00c0020
+#define ixCC_FCTRL_FUSES 0xc00c0024
+#define ixCC_HARVEST_FUSES 0xc00c0028
+#define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020
+#define ixSMU_STATUS 0xe0003088
+#define ixSMU_FIRMWARE 0xe00030a4
+#define ixSMU_INPUT_DATA 0xe00030b8
+#define ixSMU_EFUSE_0 0xc0100000
+#define ixMCARB_DRAM_TIMING_TABLE_1 0x33018
+#define ixMCARB_DRAM_TIMING_TABLE_2 0x3301c
+#define ixMCARB_DRAM_TIMING_TABLE_3 0x33020
+#define ixMCARB_DRAM_TIMING_TABLE_4 0x33024
+#define ixMCARB_DRAM_TIMING_TABLE_5 0x33028
+#define ixMCARB_DRAM_TIMING_TABLE_6 0x3302c
+#define ixMCARB_DRAM_TIMING_TABLE_7 0x33030
+#define ixMCARB_DRAM_TIMING_TABLE_8 0x33034
+#define ixMCARB_DRAM_TIMING_TABLE_9 0x33038
+#define ixMCARB_DRAM_TIMING_TABLE_10 0x3303c
+#define ixMCARB_DRAM_TIMING_TABLE_11 0x33040
+#define ixMCARB_DRAM_TIMING_TABLE_12 0x33044
+#define ixMCARB_DRAM_TIMING_TABLE_13 0x33048
+#define ixMCARB_DRAM_TIMING_TABLE_14 0x3304c
+#define ixMCARB_DRAM_TIMING_TABLE_15 0x33050
+#define ixMCARB_DRAM_TIMING_TABLE_16 0x33054
+#define ixMCARB_DRAM_TIMING_TABLE_17 0x33058
+#define ixMCARB_DRAM_TIMING_TABLE_18 0x3305c
+#define ixMCARB_DRAM_TIMING_TABLE_19 0x33060
+#define ixMCARB_DRAM_TIMING_TABLE_20 0x33064
+#define ixMCARB_DRAM_TIMING_TABLE_21 0x33068
+#define ixMCARB_DRAM_TIMING_TABLE_22 0x3306c
+#define ixMCARB_DRAM_TIMING_TABLE_23 0x33070
+#define ixMCARB_DRAM_TIMING_TABLE_24 0x33074
+#define ixMCARB_DRAM_TIMING_TABLE_25 0x33078
+#define ixMCARB_DRAM_TIMING_TABLE_26 0x3307c
+#define ixMCARB_DRAM_TIMING_TABLE_27 0x33080
+#define ixMCARB_DRAM_TIMING_TABLE_28 0x33084
+#define ixMCARB_DRAM_TIMING_TABLE_29 0x33088
+#define ixMCARB_DRAM_TIMING_TABLE_30 0x3308c
+#define ixMCARB_DRAM_TIMING_TABLE_31 0x33090
+#define ixMCARB_DRAM_TIMING_TABLE_32 0x33094
+#define ixMCARB_DRAM_TIMING_TABLE_33 0x33098
+#define ixMCARB_DRAM_TIMING_TABLE_34 0x3309c
+#define ixMCARB_DRAM_TIMING_TABLE_35 0x330a0
+#define ixMCARB_DRAM_TIMING_TABLE_36 0x330a4
+#define ixMCARB_DRAM_TIMING_TABLE_37 0x330a8
+#define ixMCARB_DRAM_TIMING_TABLE_38 0x330ac
+#define ixMCARB_DRAM_TIMING_TABLE_39 0x330b0
+#define ixMCARB_DRAM_TIMING_TABLE_40 0x330b4
+#define ixMCARB_DRAM_TIMING_TABLE_41 0x330b8
+#define ixMCARB_DRAM_TIMING_TABLE_42 0x330bc
+#define ixMCARB_DRAM_TIMING_TABLE_43 0x330c0
+#define ixMCARB_DRAM_TIMING_TABLE_44 0x330c4
+#define ixMCARB_DRAM_TIMING_TABLE_45 0x330c8
+#define ixMCARB_DRAM_TIMING_TABLE_46 0x330cc
+#define ixMCARB_DRAM_TIMING_TABLE_47 0x330d0
+#define ixMCARB_DRAM_TIMING_TABLE_48 0x330d4
+#define ixMCARB_DRAM_TIMING_TABLE_49 0x330d8
+#define ixMCARB_DRAM_TIMING_TABLE_50 0x330dc
+#define ixMCARB_DRAM_TIMING_TABLE_51 0x330e0
+#define ixMCARB_DRAM_TIMING_TABLE_52 0x330e4
+#define ixMCARB_DRAM_TIMING_TABLE_53 0x330e8
+#define ixMCARB_DRAM_TIMING_TABLE_54 0x330ec
+#define ixMCARB_DRAM_TIMING_TABLE_55 0x330f0
+#define ixMCARB_DRAM_TIMING_TABLE_56 0x330f4
+#define ixMCARB_DRAM_TIMING_TABLE_57 0x330f8
+#define ixMCARB_DRAM_TIMING_TABLE_58 0x330fc
+#define ixMCARB_DRAM_TIMING_TABLE_59 0x33100
+#define ixMCARB_DRAM_TIMING_TABLE_60 0x33104
+#define ixMCARB_DRAM_TIMING_TABLE_61 0x33108
+#define ixMCARB_DRAM_TIMING_TABLE_62 0x3310c
+#define ixMCARB_DRAM_TIMING_TABLE_63 0x33110
+#define ixMCARB_DRAM_TIMING_TABLE_64 0x33114
+#define ixMCARB_DRAM_TIMING_TABLE_65 0x33118
+#define ixMCARB_DRAM_TIMING_TABLE_66 0x3311c
+#define ixMCARB_DRAM_TIMING_TABLE_67 0x33120
+#define ixMCARB_DRAM_TIMING_TABLE_68 0x33124
+#define ixMCARB_DRAM_TIMING_TABLE_69 0x33128
+#define ixMCARB_DRAM_TIMING_TABLE_70 0x3312c
+#define ixMCARB_DRAM_TIMING_TABLE_71 0x33130
+#define ixMCARB_DRAM_TIMING_TABLE_72 0x33134
+#define ixMCARB_DRAM_TIMING_TABLE_73 0x33138
+#define ixMCARB_DRAM_TIMING_TABLE_74 0x3313c
+#define ixMCARB_DRAM_TIMING_TABLE_75 0x33140
+#define ixMCARB_DRAM_TIMING_TABLE_76 0x33144
+#define ixMCARB_DRAM_TIMING_TABLE_77 0x33148
+#define ixMCARB_DRAM_TIMING_TABLE_78 0x3314c
+#define ixMCARB_DRAM_TIMING_TABLE_79 0x33150
+#define ixMCARB_DRAM_TIMING_TABLE_80 0x33154
+#define ixMCARB_DRAM_TIMING_TABLE_81 0x33158
+#define ixMCARB_DRAM_TIMING_TABLE_82 0x3315c
+#define ixMCARB_DRAM_TIMING_TABLE_83 0x33160
+#define ixMCARB_DRAM_TIMING_TABLE_84 0x33164
+#define ixMCARB_DRAM_TIMING_TABLE_85 0x33168
+#define ixMCARB_DRAM_TIMING_TABLE_86 0x3316c
+#define ixMCARB_DRAM_TIMING_TABLE_87 0x33170
+#define ixMCARB_DRAM_TIMING_TABLE_88 0x33174
+#define ixMCARB_DRAM_TIMING_TABLE_89 0x33178
+#define ixMCARB_DRAM_TIMING_TABLE_90 0x3317c
+#define ixMCARB_DRAM_TIMING_TABLE_91 0x33180
+#define ixMCARB_DRAM_TIMING_TABLE_92 0x33184
+#define ixMCARB_DRAM_TIMING_TABLE_93 0x33188
+#define ixMCARB_DRAM_TIMING_TABLE_94 0x3318c
+#define ixMCARB_DRAM_TIMING_TABLE_95 0x33190
+#define ixMCARB_DRAM_TIMING_TABLE_96 0x33194
+#define ixMC_REGISTERS_TABLE_1 0x33198
+#define ixMC_REGISTERS_TABLE_2 0x3319c
+#define ixMC_REGISTERS_TABLE_3 0x331a0
+#define ixMC_REGISTERS_TABLE_4 0x331a4
+#define ixMC_REGISTERS_TABLE_5 0x331a8
+#define ixMC_REGISTERS_TABLE_6 0x331ac
+#define ixMC_REGISTERS_TABLE_7 0x331b0
+#define ixMC_REGISTERS_TABLE_8 0x331b4
+#define ixMC_REGISTERS_TABLE_9 0x331b8
+#define ixMC_REGISTERS_TABLE_10 0x331bc
+#define ixMC_REGISTERS_TABLE_11 0x331c0
+#define ixMC_REGISTERS_TABLE_12 0x331c4
+#define ixMC_REGISTERS_TABLE_13 0x331c8
+#define ixMC_REGISTERS_TABLE_14 0x331cc
+#define ixMC_REGISTERS_TABLE_15 0x331d0
+#define ixMC_REGISTERS_TABLE_16 0x331d4
+#define ixMC_REGISTERS_TABLE_17 0x331d8
+#define ixMC_REGISTERS_TABLE_18 0x331dc
+#define ixMC_REGISTERS_TABLE_19 0x331e0
+#define ixMC_REGISTERS_TABLE_20 0x331e4
+#define ixMC_REGISTERS_TABLE_21 0x331e8
+#define ixMC_REGISTERS_TABLE_22 0x331ec
+#define ixMC_REGISTERS_TABLE_23 0x331f0
+#define ixMC_REGISTERS_TABLE_24 0x331f4
+#define ixMC_REGISTERS_TABLE_25 0x331f8
+#define ixMC_REGISTERS_TABLE_26 0x331fc
+#define ixMC_REGISTERS_TABLE_27 0x33200
+#define ixMC_REGISTERS_TABLE_28 0x33204
+#define ixMC_REGISTERS_TABLE_29 0x33208
+#define ixMC_REGISTERS_TABLE_30 0x3320c
+#define ixMC_REGISTERS_TABLE_31 0x33210
+#define ixMC_REGISTERS_TABLE_32 0x33214
+#define ixMC_REGISTERS_TABLE_33 0x33218
+#define ixMC_REGISTERS_TABLE_34 0x3321c
+#define ixMC_REGISTERS_TABLE_35 0x33220
+#define ixMC_REGISTERS_TABLE_36 0x33224
+#define ixMC_REGISTERS_TABLE_37 0x33228
+#define ixMC_REGISTERS_TABLE_38 0x3322c
+#define ixMC_REGISTERS_TABLE_39 0x33230
+#define ixMC_REGISTERS_TABLE_40 0x33234
+#define ixMC_REGISTERS_TABLE_41 0x33238
+#define ixMC_REGISTERS_TABLE_42 0x3323c
+#define ixMC_REGISTERS_TABLE_43 0x33240
+#define ixMC_REGISTERS_TABLE_44 0x33244
+#define ixMC_REGISTERS_TABLE_45 0x33248
+#define ixMC_REGISTERS_TABLE_46 0x3324c
+#define ixMC_REGISTERS_TABLE_47 0x33250
+#define ixMC_REGISTERS_TABLE_48 0x33254
+#define ixMC_REGISTERS_TABLE_49 0x33258
+#define ixMC_REGISTERS_TABLE_50 0x3325c
+#define ixMC_REGISTERS_TABLE_51 0x33260
+#define ixMC_REGISTERS_TABLE_52 0x33264
+#define ixMC_REGISTERS_TABLE_53 0x33268
+#define ixMC_REGISTERS_TABLE_54 0x3326c
+#define ixMC_REGISTERS_TABLE_55 0x33270
+#define ixMC_REGISTERS_TABLE_56 0x33274
+#define ixMC_REGISTERS_TABLE_57 0x33278
+#define ixMC_REGISTERS_TABLE_58 0x3327c
+#define ixMC_REGISTERS_TABLE_59 0x33280
+#define ixMC_REGISTERS_TABLE_60 0x33284
+#define ixMC_REGISTERS_TABLE_61 0x33288
+#define ixMC_REGISTERS_TABLE_62 0x3328c
+#define ixMC_REGISTERS_TABLE_63 0x33290
+#define ixMC_REGISTERS_TABLE_64 0x33294
+#define ixMC_REGISTERS_TABLE_65 0x33298
+#define ixMC_REGISTERS_TABLE_66 0x3329c
+#define ixMC_REGISTERS_TABLE_67 0x332a0
+#define ixMC_REGISTERS_TABLE_68 0x332a4
+#define ixMC_REGISTERS_TABLE_69 0x332a8
+#define ixMC_REGISTERS_TABLE_70 0x332ac
+#define ixMC_REGISTERS_TABLE_71 0x332b0
+#define ixMC_REGISTERS_TABLE_72 0x332b4
+#define ixMC_REGISTERS_TABLE_73 0x332b8
+#define ixMC_REGISTERS_TABLE_74 0x332bc
+#define ixMC_REGISTERS_TABLE_75 0x332c0
+#define ixMC_REGISTERS_TABLE_76 0x332c4
+#define ixMC_REGISTERS_TABLE_77 0x332c8
+#define ixMC_REGISTERS_TABLE_78 0x332cc
+#define ixMC_REGISTERS_TABLE_79 0x332d0
+#define ixMC_REGISTERS_TABLE_80 0x332d4
+#define ixMC_REGISTERS_TABLE_81 0x332d8
+#define ixDPM_TABLE_1 0x332dc
+#define ixDPM_TABLE_2 0x332e0
+#define ixDPM_TABLE_3 0x332e4
+#define ixDPM_TABLE_4 0x332e8
+#define ixDPM_TABLE_5 0x332ec
+#define ixDPM_TABLE_6 0x332f0
+#define ixDPM_TABLE_7 0x332f4
+#define ixDPM_TABLE_8 0x332f8
+#define ixDPM_TABLE_9 0x332fc
+#define ixDPM_TABLE_10 0x33300
+#define ixDPM_TABLE_11 0x33304
+#define ixDPM_TABLE_12 0x33308
+#define ixDPM_TABLE_13 0x3330c
+#define ixDPM_TABLE_14 0x33310
+#define ixDPM_TABLE_15 0x33314
+#define ixDPM_TABLE_16 0x33318
+#define ixDPM_TABLE_17 0x3331c
+#define ixDPM_TABLE_18 0x33320
+#define ixDPM_TABLE_19 0x33324
+#define ixDPM_TABLE_20 0x33328
+#define ixDPM_TABLE_21 0x3332c
+#define ixDPM_TABLE_22 0x33330
+#define ixDPM_TABLE_23 0x33334
+#define ixDPM_TABLE_24 0x33338
+#define ixDPM_TABLE_25 0x3333c
+#define ixDPM_TABLE_26 0x33340
+#define ixDPM_TABLE_27 0x33344
+#define ixDPM_TABLE_28 0x33348
+#define ixDPM_TABLE_29 0x3334c
+#define ixDPM_TABLE_30 0x33350
+#define ixDPM_TABLE_31 0x33354
+#define ixDPM_TABLE_32 0x33358
+#define ixDPM_TABLE_33 0x3335c
+#define ixDPM_TABLE_34 0x33360
+#define ixDPM_TABLE_35 0x33364
+#define ixDPM_TABLE_36 0x33368
+#define ixDPM_TABLE_37 0x3336c
+#define ixDPM_TABLE_38 0x33370
+#define ixDPM_TABLE_39 0x33374
+#define ixDPM_TABLE_40 0x33378
+#define ixDPM_TABLE_41 0x3337c
+#define ixDPM_TABLE_42 0x33380
+#define ixDPM_TABLE_43 0x33384
+#define ixDPM_TABLE_44 0x33388
+#define ixDPM_TABLE_45 0x3338c
+#define ixDPM_TABLE_46 0x33390
+#define ixDPM_TABLE_47 0x33394
+#define ixDPM_TABLE_48 0x33398
+#define ixDPM_TABLE_49 0x3339c
+#define ixDPM_TABLE_50 0x333a0
+#define ixDPM_TABLE_51 0x333a4
+#define ixDPM_TABLE_52 0x333a8
+#define ixDPM_TABLE_53 0x333ac
+#define ixDPM_TABLE_54 0x333b0
+#define ixDPM_TABLE_55 0x333b4
+#define ixDPM_TABLE_56 0x333b8
+#define ixDPM_TABLE_57 0x333bc
+#define ixDPM_TABLE_58 0x333c0
+#define ixDPM_TABLE_59 0x333c4
+#define ixDPM_TABLE_60 0x333c8
+#define ixDPM_TABLE_61 0x333cc
+#define ixDPM_TABLE_62 0x333d0
+#define ixDPM_TABLE_63 0x333d4
+#define ixDPM_TABLE_64 0x333d8
+#define ixDPM_TABLE_65 0x333dc
+#define ixDPM_TABLE_66 0x333e0
+#define ixDPM_TABLE_67 0x333e4
+#define ixDPM_TABLE_68 0x333e8
+#define ixDPM_TABLE_69 0x333ec
+#define ixDPM_TABLE_70 0x333f0
+#define ixDPM_TABLE_71 0x333f4
+#define ixDPM_TABLE_72 0x333f8
+#define ixDPM_TABLE_73 0x333fc
+#define ixDPM_TABLE_74 0x33400
+#define ixDPM_TABLE_75 0x33404
+#define ixDPM_TABLE_76 0x33408
+#define ixDPM_TABLE_77 0x3340c
+#define ixDPM_TABLE_78 0x33410
+#define ixDPM_TABLE_79 0x33414
+#define ixDPM_TABLE_80 0x33418
+#define ixDPM_TABLE_81 0x3341c
+#define ixDPM_TABLE_82 0x33420
+#define ixDPM_TABLE_83 0x33424
+#define ixDPM_TABLE_84 0x33428
+#define ixDPM_TABLE_85 0x3342c
+#define ixDPM_TABLE_86 0x33430
+#define ixDPM_TABLE_87 0x33434
+#define ixDPM_TABLE_88 0x33438
+#define ixDPM_TABLE_89 0x3343c
+#define ixDPM_TABLE_90 0x33440
+#define ixDPM_TABLE_91 0x33444
+#define ixDPM_TABLE_92 0x33448
+#define ixDPM_TABLE_93 0x3344c
+#define ixDPM_TABLE_94 0x33450
+#define ixDPM_TABLE_95 0x33454
+#define ixDPM_TABLE_96 0x33458
+#define ixDPM_TABLE_97 0x3345c
+#define ixDPM_TABLE_98 0x33460
+#define ixDPM_TABLE_99 0x33464
+#define ixDPM_TABLE_100 0x33468
+#define ixDPM_TABLE_101 0x3346c
+#define ixDPM_TABLE_102 0x33470
+#define ixDPM_TABLE_103 0x33474
+#define ixDPM_TABLE_104 0x33478
+#define ixDPM_TABLE_105 0x3347c
+#define ixDPM_TABLE_106 0x33480
+#define ixDPM_TABLE_107 0x33484
+#define ixDPM_TABLE_108 0x33488
+#define ixDPM_TABLE_109 0x3348c
+#define ixDPM_TABLE_110 0x33490
+#define ixDPM_TABLE_111 0x33494
+#define ixDPM_TABLE_112 0x33498
+#define ixDPM_TABLE_113 0x3349c
+#define ixDPM_TABLE_114 0x334a0
+#define ixDPM_TABLE_115 0x334a4
+#define ixDPM_TABLE_116 0x334a8
+#define ixDPM_TABLE_117 0x334ac
+#define ixDPM_TABLE_118 0x334b0
+#define ixDPM_TABLE_119 0x334b4
+#define ixDPM_TABLE_120 0x334b8
+#define ixDPM_TABLE_121 0x334bc
+#define ixDPM_TABLE_122 0x334c0
+#define ixDPM_TABLE_123 0x334c4
+#define ixDPM_TABLE_124 0x334c8
+#define ixDPM_TABLE_125 0x334cc
+#define ixDPM_TABLE_126 0x334d0
+#define ixDPM_TABLE_127 0x334d4
+#define ixDPM_TABLE_128 0x334d8
+#define ixDPM_TABLE_129 0x334dc
+#define ixDPM_TABLE_130 0x334e0
+#define ixDPM_TABLE_131 0x334e4
+#define ixDPM_TABLE_132 0x334e8
+#define ixDPM_TABLE_133 0x334ec
+#define ixDPM_TABLE_134 0x334f0
+#define ixDPM_TABLE_135 0x334f4
+#define ixDPM_TABLE_136 0x334f8
+#define ixDPM_TABLE_137 0x334fc
+#define ixDPM_TABLE_138 0x33500
+#define ixDPM_TABLE_139 0x33504
+#define ixDPM_TABLE_140 0x33508
+#define ixDPM_TABLE_141 0x3350c
+#define ixDPM_TABLE_142 0x33510
+#define ixDPM_TABLE_143 0x33514
+#define ixDPM_TABLE_144 0x33518
+#define ixDPM_TABLE_145 0x3351c
+#define ixDPM_TABLE_146 0x33520
+#define ixDPM_TABLE_147 0x33524
+#define ixDPM_TABLE_148 0x33528
+#define ixDPM_TABLE_149 0x3352c
+#define ixDPM_TABLE_150 0x33530
+#define ixDPM_TABLE_151 0x33534
+#define ixDPM_TABLE_152 0x33538
+#define ixDPM_TABLE_153 0x3353c
+#define ixDPM_TABLE_154 0x33540
+#define ixDPM_TABLE_155 0x33544
+#define ixDPM_TABLE_156 0x33548
+#define ixDPM_TABLE_157 0x3354c
+#define ixDPM_TABLE_158 0x33550
+#define ixDPM_TABLE_159 0x33554
+#define ixDPM_TABLE_160 0x33558
+#define ixDPM_TABLE_161 0x3355c
+#define ixDPM_TABLE_162 0x33560
+#define ixDPM_TABLE_163 0x33564
+#define ixDPM_TABLE_164 0x33568
+#define ixDPM_TABLE_165 0x3356c
+#define ixDPM_TABLE_166 0x33570
+#define ixDPM_TABLE_167 0x33574
+#define ixDPM_TABLE_168 0x33578
+#define ixDPM_TABLE_169 0x3357c
+#define ixDPM_TABLE_170 0x33580
+#define ixDPM_TABLE_171 0x33584
+#define ixDPM_TABLE_172 0x33588
+#define ixDPM_TABLE_173 0x3358c
+#define ixDPM_TABLE_174 0x33590
+#define ixDPM_TABLE_175 0x33594
+#define ixDPM_TABLE_176 0x33598
+#define ixDPM_TABLE_177 0x3359c
+#define ixDPM_TABLE_178 0x335a0
+#define ixDPM_TABLE_179 0x335a4
+#define ixDPM_TABLE_180 0x335a8
+#define ixDPM_TABLE_181 0x335ac
+#define ixDPM_TABLE_182 0x335b0
+#define ixDPM_TABLE_183 0x335b4
+#define ixDPM_TABLE_184 0x335b8
+#define ixDPM_TABLE_185 0x335bc
+#define ixDPM_TABLE_186 0x335c0
+#define ixDPM_TABLE_187 0x335c4
+#define ixDPM_TABLE_188 0x335c8
+#define ixDPM_TABLE_189 0x335cc
+#define ixDPM_TABLE_190 0x335d0
+#define ixDPM_TABLE_191 0x335d4
+#define ixDPM_TABLE_192 0x335d8
+#define ixDPM_TABLE_193 0x335dc
+#define ixDPM_TABLE_194 0x335e0
+#define ixDPM_TABLE_195 0x335e4
+#define ixDPM_TABLE_196 0x335e8
+#define ixDPM_TABLE_197 0x335ec
+#define ixDPM_TABLE_198 0x335f0
+#define ixDPM_TABLE_199 0x335f4
+#define ixDPM_TABLE_200 0x335f8
+#define ixDPM_TABLE_201 0x335fc
+#define ixDPM_TABLE_202 0x33600
+#define ixDPM_TABLE_203 0x33604
+#define ixDPM_TABLE_204 0x33608
+#define ixDPM_TABLE_205 0x3360c
+#define ixDPM_TABLE_206 0x33610
+#define ixDPM_TABLE_207 0x33614
+#define ixDPM_TABLE_208 0x33618
+#define ixDPM_TABLE_209 0x3361c
+#define ixDPM_TABLE_210 0x33620
+#define ixDPM_TABLE_211 0x33624
+#define ixDPM_TABLE_212 0x33628
+#define ixDPM_TABLE_213 0x3362c
+#define ixDPM_TABLE_214 0x33630
+#define ixDPM_TABLE_215 0x33634
+#define ixDPM_TABLE_216 0x33638
+#define ixDPM_TABLE_217 0x3363c
+#define ixDPM_TABLE_218 0x33640
+#define ixDPM_TABLE_219 0x33644
+#define ixDPM_TABLE_220 0x33648
+#define ixDPM_TABLE_221 0x3364c
+#define ixDPM_TABLE_222 0x33650
+#define ixDPM_TABLE_223 0x33654
+#define ixDPM_TABLE_224 0x33658
+#define ixDPM_TABLE_225 0x3365c
+#define ixDPM_TABLE_226 0x33660
+#define ixDPM_TABLE_227 0x33664
+#define ixDPM_TABLE_228 0x33668
+#define ixDPM_TABLE_229 0x3366c
+#define ixDPM_TABLE_230 0x33670
+#define ixDPM_TABLE_231 0x33674
+#define ixDPM_TABLE_232 0x33678
+#define ixDPM_TABLE_233 0x3367c
+#define ixDPM_TABLE_234 0x33680
+#define ixDPM_TABLE_235 0x33684
+#define ixDPM_TABLE_236 0x33688
+#define ixDPM_TABLE_237 0x3368c
+#define ixDPM_TABLE_238 0x33690
+#define ixDPM_TABLE_239 0x33694
+#define ixDPM_TABLE_240 0x33698
+#define ixDPM_TABLE_241 0x3369c
+#define ixDPM_TABLE_242 0x336a0
+#define ixDPM_TABLE_243 0x336a4
+#define ixDPM_TABLE_244 0x336a8
+#define ixDPM_TABLE_245 0x336ac
+#define ixDPM_TABLE_246 0x336b0
+#define ixDPM_TABLE_247 0x336b4
+#define ixDPM_TABLE_248 0x336b8
+#define ixDPM_TABLE_249 0x336bc
+#define ixDPM_TABLE_250 0x336c0
+#define ixDPM_TABLE_251 0x336c4
+#define ixDPM_TABLE_252 0x336c8
+#define ixDPM_TABLE_253 0x336cc
+#define ixDPM_TABLE_254 0x336d0
+#define ixDPM_TABLE_255 0x336d4
+#define ixDPM_TABLE_256 0x336d8
+#define ixDPM_TABLE_257 0x336dc
+#define ixDPM_TABLE_258 0x336e0
+#define ixDPM_TABLE_259 0x336e4
+#define ixDPM_TABLE_260 0x336e8
+#define ixDPM_TABLE_261 0x336ec
+#define ixDPM_TABLE_262 0x336f0
+#define ixDPM_TABLE_263 0x336f4
+#define ixDPM_TABLE_264 0x336f8
+#define ixDPM_TABLE_265 0x336fc
+#define ixDPM_TABLE_266 0x33700
+#define ixDPM_TABLE_267 0x33704
+#define ixDPM_TABLE_268 0x33708
+#define ixDPM_TABLE_269 0x3370c
+#define ixDPM_TABLE_270 0x33710
+#define ixDPM_TABLE_271 0x33714
+#define ixDPM_TABLE_272 0x33718
+#define ixDPM_TABLE_273 0x3371c
+#define ixDPM_TABLE_274 0x33720
+#define ixDPM_TABLE_275 0x33724
+#define ixDPM_TABLE_276 0x33728
+#define ixDPM_TABLE_277 0x3372c
+#define ixDPM_TABLE_278 0x33730
+#define ixDPM_TABLE_279 0x33734
+#define ixDPM_TABLE_280 0x33738
+#define ixDPM_TABLE_281 0x3373c
+#define ixDPM_TABLE_282 0x33740
+#define ixDPM_TABLE_283 0x33744
+#define ixDPM_TABLE_284 0x33748
+#define ixDPM_TABLE_285 0x3374c
+#define ixDPM_TABLE_286 0x33750
+#define ixDPM_TABLE_287 0x33754
+#define ixDPM_TABLE_288 0x33758
+#define ixDPM_TABLE_289 0x3375c
+#define ixDPM_TABLE_290 0x33760
+#define ixDPM_TABLE_291 0x33764
+#define ixDPM_TABLE_292 0x33768
+#define ixDPM_TABLE_293 0x3376c
+#define ixDPM_TABLE_294 0x33770
+#define ixDPM_TABLE_295 0x33774
+#define ixDPM_TABLE_296 0x33778
+#define ixDPM_TABLE_297 0x3377c
+#define ixDPM_TABLE_298 0x33780
+#define ixDPM_TABLE_299 0x33784
+#define ixDPM_TABLE_300 0x33788
+#define ixDPM_TABLE_301 0x3378c
+#define ixDPM_TABLE_302 0x33790
+#define ixDPM_TABLE_303 0x33794
+#define ixDPM_TABLE_304 0x33798
+#define ixDPM_TABLE_305 0x3379c
+#define ixDPM_TABLE_306 0x337a0
+#define ixDPM_TABLE_307 0x337a4
+#define ixDPM_TABLE_308 0x337a8
+#define ixDPM_TABLE_309 0x337ac
+#define ixDPM_TABLE_310 0x337b0
+#define ixDPM_TABLE_311 0x337b4
+#define ixDPM_TABLE_312 0x337b8
+#define ixDPM_TABLE_313 0x337bc
+#define ixDPM_TABLE_314 0x337c0
+#define ixDPM_TABLE_315 0x337c4
+#define ixDPM_TABLE_316 0x337c8
+#define ixDPM_TABLE_317 0x337cc
+#define ixDPM_TABLE_318 0x337d0
+#define ixDPM_TABLE_319 0x337d4
+#define ixDPM_TABLE_320 0x337d8
+#define ixDPM_TABLE_321 0x337dc
+#define ixDPM_TABLE_322 0x337e0
+#define ixDPM_TABLE_323 0x337e4
+#define ixDPM_TABLE_324 0x337e8
+#define ixDPM_TABLE_325 0x337ec
+#define ixDPM_TABLE_326 0x337f0
+#define ixDPM_TABLE_327 0x337f4
+#define ixDPM_TABLE_328 0x337f8
+#define ixDPM_TABLE_329 0x337fc
+#define ixDPM_TABLE_330 0x33800
+#define ixDPM_TABLE_331 0x33804
+#define ixDPM_TABLE_332 0x33808
+#define ixDPM_TABLE_333 0x3380c
+#define ixDPM_TABLE_334 0x33810
+#define ixDPM_TABLE_335 0x33814
+#define ixDPM_TABLE_336 0x33818
+#define ixDPM_TABLE_337 0x3381c
+#define ixDPM_TABLE_338 0x33820
+#define ixDPM_TABLE_339 0x33824
+#define ixDPM_TABLE_340 0x33828
+#define ixDPM_TABLE_341 0x3382c
+#define ixDPM_TABLE_342 0x33830
+#define ixDPM_TABLE_343 0x33834
+#define ixDPM_TABLE_344 0x33838
+#define ixDPM_TABLE_345 0x3383c
+#define ixDPM_TABLE_346 0x33840
+#define ixDPM_TABLE_347 0x33844
+#define ixDPM_TABLE_348 0x33848
+#define ixDPM_TABLE_349 0x3384c
+#define ixDPM_TABLE_350 0x33850
+#define ixDPM_TABLE_351 0x33854
+#define ixDPM_TABLE_352 0x33858
+#define ixDPM_TABLE_353 0x3385c
+#define ixDPM_TABLE_354 0x33860
+#define ixDPM_TABLE_355 0x33864
+#define ixDPM_TABLE_356 0x33868
+#define ixDPM_TABLE_357 0x3386c
+#define ixDPM_TABLE_358 0x33870
+#define ixDPM_TABLE_359 0x33874
+#define ixDPM_TABLE_360 0x33878
+#define ixDPM_TABLE_361 0x3387c
+#define ixDPM_TABLE_362 0x33880
+#define ixDPM_TABLE_363 0x33884
+#define ixDPM_TABLE_364 0x33888
+#define ixDPM_TABLE_365 0x3388c
+#define ixDPM_TABLE_366 0x33890
+#define ixDPM_TABLE_367 0x33894
+#define ixDPM_TABLE_368 0x33898
+#define ixDPM_TABLE_369 0x3389c
+#define ixDPM_TABLE_370 0x338a0
+#define ixSOFT_REGISTERS_TABLE_1 0x338c8
+#define ixSOFT_REGISTERS_TABLE_2 0x338cc
+#define ixSOFT_REGISTERS_TABLE_3 0x338d0
+#define ixSOFT_REGISTERS_TABLE_4 0x338d4
+#define ixSOFT_REGISTERS_TABLE_5 0x338d8
+#define ixSOFT_REGISTERS_TABLE_6 0x338dc
+#define ixSOFT_REGISTERS_TABLE_7 0x338e0
+#define ixSOFT_REGISTERS_TABLE_8 0x338e4
+#define ixSOFT_REGISTERS_TABLE_9 0x338e8
+#define ixSOFT_REGISTERS_TABLE_10 0x338ec
+#define ixSOFT_REGISTERS_TABLE_11 0x338f0
+#define ixSOFT_REGISTERS_TABLE_12 0x338f4
+#define ixSOFT_REGISTERS_TABLE_13 0x338f8
+#define ixSOFT_REGISTERS_TABLE_14 0x338fc
+#define ixSOFT_REGISTERS_TABLE_15 0x33900
+#define ixSOFT_REGISTERS_TABLE_16 0x33904
+#define ixSOFT_REGISTERS_TABLE_17 0x33908
+#define ixSOFT_REGISTERS_TABLE_18 0x3390c
+#define ixSOFT_REGISTERS_TABLE_19 0x33910
+#define ixSOFT_REGISTERS_TABLE_20 0x33914
+#define ixSOFT_REGISTERS_TABLE_21 0x33918
+#define ixSOFT_REGISTERS_TABLE_22 0x3391c
+#define ixSOFT_REGISTERS_TABLE_23 0x33920
+#define ixSOFT_REGISTERS_TABLE_24 0x33924
+#define ixSOFT_REGISTERS_TABLE_25 0x33928
+#define ixSOFT_REGISTERS_TABLE_26 0x3392c
+#define ixSOFT_REGISTERS_TABLE_27 0x33930
+#define ixSOFT_REGISTERS_TABLE_28 0x33934
+#define ixSOFT_REGISTERS_TABLE_29 0x33938
+#define ixFIRMWARE_FLAGS 0x33000
+#define ixTDC_STATUS 0x33004
+#define ixTDC_MV_AVERAGE 0x33008
+#define ixTDC_VRM_LIMIT 0x3300c
+#define ixFEATURE_STATUS 0x33010
+#define ixENTITY_TEMPERATURES_1 0x33014
+#define ixPM_FUSES_1 0x3394c
+#define ixPM_FUSES_2 0x33950
+#define ixPM_FUSES_3 0x33954
+#define ixPM_FUSES_4 0x33958
+#define ixPM_FUSES_5 0x3395c
+#define ixPM_FUSES_6 0x33960
+#define ixPM_FUSES_7 0x33964
+#define ixPM_FUSES_8 0x33968
+#define ixPM_FUSES_9 0x3396c
+#define ixPM_FUSES_10 0x33970
+#define ixPM_FUSES_11 0x33974
+#define ixPM_FUSES_12 0x33978
+#define ixPM_FUSES_13 0x3397c
+#define ixPM_FUSES_14 0x33980
+#define ixPM_FUSES_15 0x33984
+#define ixPM_FUSES_16 0x33988
+#define ixPM_FUSES_17 0x3398c
+#define ixPM_FUSES_18 0x33990
+#define ixPM_FUSES_19 0x33994
+#define ixPM_FUSES_20 0x33998
+#define ixPM_FUSES_21 0x3399c
+#define ixSMU_PM_STATUS_0 0x33e00
+#define ixSMU_PM_STATUS_1 0x33e04
+#define ixSMU_PM_STATUS_2 0x33e08
+#define ixSMU_PM_STATUS_3 0x33e0c
+#define ixSMU_PM_STATUS_4 0x33e10
+#define ixSMU_PM_STATUS_5 0x33e14
+#define ixSMU_PM_STATUS_6 0x33e18
+#define ixSMU_PM_STATUS_7 0x33e1c
+#define ixSMU_PM_STATUS_8 0x33e20
+#define ixSMU_PM_STATUS_9 0x33e24
+#define ixSMU_PM_STATUS_10 0x33e28
+#define ixSMU_PM_STATUS_11 0x33e2c
+#define ixSMU_PM_STATUS_12 0x33e30
+#define ixSMU_PM_STATUS_13 0x33e34
+#define ixSMU_PM_STATUS_14 0x33e38
+#define ixSMU_PM_STATUS_15 0x33e3c
+#define ixSMU_PM_STATUS_16 0x33e40
+#define ixSMU_PM_STATUS_17 0x33e44
+#define ixSMU_PM_STATUS_18 0x33e48
+#define ixSMU_PM_STATUS_19 0x33e4c
+#define ixSMU_PM_STATUS_20 0x33e50
+#define ixSMU_PM_STATUS_21 0x33e54
+#define ixSMU_PM_STATUS_22 0x33e58
+#define ixSMU_PM_STATUS_23 0x33e5c
+#define ixSMU_PM_STATUS_24 0x33e60
+#define ixSMU_PM_STATUS_25 0x33e64
+#define ixSMU_PM_STATUS_26 0x33e68
+#define ixSMU_PM_STATUS_27 0x33e6c
+#define ixSMU_PM_STATUS_28 0x33e70
+#define ixSMU_PM_STATUS_29 0x33e74
+#define ixSMU_PM_STATUS_30 0x33e78
+#define ixSMU_PM_STATUS_31 0x33e7c
+#define ixSMU_PM_STATUS_32 0x33e80
+#define ixSMU_PM_STATUS_33 0x33e84
+#define ixSMU_PM_STATUS_34 0x33e88
+#define ixSMU_PM_STATUS_35 0x33e8c
+#define ixSMU_PM_STATUS_36 0x33e90
+#define ixSMU_PM_STATUS_37 0x33e94
+#define ixSMU_PM_STATUS_38 0x33e98
+#define ixSMU_PM_STATUS_39 0x33e9c
+#define ixSMU_PM_STATUS_40 0x33ea0
+#define ixSMU_PM_STATUS_41 0x33ea4
+#define ixSMU_PM_STATUS_42 0x33ea8
+#define ixSMU_PM_STATUS_43 0x33eac
+#define ixSMU_PM_STATUS_44 0x33eb0
+#define ixSMU_PM_STATUS_45 0x33eb4
+#define ixSMU_PM_STATUS_46 0x33eb8
+#define ixSMU_PM_STATUS_47 0x33ebc
+#define ixSMU_PM_STATUS_48 0x33ec0
+#define ixSMU_PM_STATUS_49 0x33ec4
+#define ixSMU_PM_STATUS_50 0x33ec8
+#define ixSMU_PM_STATUS_51 0x33ecc
+#define ixSMU_PM_STATUS_52 0x33ed0
+#define ixSMU_PM_STATUS_53 0x33ed4
+#define ixSMU_PM_STATUS_54 0x33ed8
+#define ixSMU_PM_STATUS_55 0x33edc
+#define ixSMU_PM_STATUS_56 0x33ee0
+#define ixSMU_PM_STATUS_57 0x33ee4
+#define ixSMU_PM_STATUS_58 0x33ee8
+#define ixSMU_PM_STATUS_59 0x33eec
+#define ixSMU_PM_STATUS_60 0x33ef0
+#define ixSMU_PM_STATUS_61 0x33ef4
+#define ixSMU_PM_STATUS_62 0x33ef8
+#define ixSMU_PM_STATUS_63 0x33efc
+#define ixSMU_PM_STATUS_64 0x33f00
+#define ixSMU_PM_STATUS_65 0x33f04
+#define ixSMU_PM_STATUS_66 0x33f08
+#define ixSMU_PM_STATUS_67 0x33f0c
+#define ixSMU_PM_STATUS_68 0x33f10
+#define ixSMU_PM_STATUS_69 0x33f14
+#define ixSMU_PM_STATUS_70 0x33f18
+#define ixSMU_PM_STATUS_71 0x33f1c
+#define ixSMU_PM_STATUS_72 0x33f20
+#define ixSMU_PM_STATUS_73 0x33f24
+#define ixSMU_PM_STATUS_74 0x33f28
+#define ixSMU_PM_STATUS_75 0x33f2c
+#define ixSMU_PM_STATUS_76 0x33f30
+#define ixSMU_PM_STATUS_77 0x33f34
+#define ixSMU_PM_STATUS_78 0x33f38
+#define ixSMU_PM_STATUS_79 0x33f3c
+#define ixSMU_PM_STATUS_80 0x33f40
+#define ixSMU_PM_STATUS_81 0x33f44
+#define ixSMU_PM_STATUS_82 0x33f48
+#define ixSMU_PM_STATUS_83 0x33f4c
+#define ixSMU_PM_STATUS_84 0x33f50
+#define ixSMU_PM_STATUS_85 0x33f54
+#define ixSMU_PM_STATUS_86 0x33f58
+#define ixSMU_PM_STATUS_87 0x33f5c
+#define ixSMU_PM_STATUS_88 0x33f60
+#define ixSMU_PM_STATUS_89 0x33f64
+#define ixSMU_PM_STATUS_90 0x33f68
+#define ixSMU_PM_STATUS_91 0x33f6c
+#define ixSMU_PM_STATUS_92 0x33f70
+#define ixSMU_PM_STATUS_93 0x33f74
+#define ixSMU_PM_STATUS_94 0x33f78
+#define ixSMU_PM_STATUS_95 0x33f7c
+#define ixSMU_PM_STATUS_96 0x33f80
+#define ixSMU_PM_STATUS_97 0x33f84
+#define ixSMU_PM_STATUS_98 0x33f88
+#define ixSMU_PM_STATUS_99 0x33f8c
+#define ixSMU_PM_STATUS_100 0x33f90
+#define ixSMU_PM_STATUS_101 0x33f94
+#define ixSMU_PM_STATUS_102 0x33f98
+#define ixSMU_PM_STATUS_103 0x33f9c
+#define ixSMU_PM_STATUS_104 0x33fa0
+#define ixSMU_PM_STATUS_105 0x33fa4
+#define ixSMU_PM_STATUS_106 0x33fa8
+#define ixSMU_PM_STATUS_107 0x33fac
+#define ixSMU_PM_STATUS_108 0x33fb0
+#define ixSMU_PM_STATUS_109 0x33fb4
+#define ixSMU_PM_STATUS_110 0x33fb8
+#define ixSMU_PM_STATUS_111 0x33fbc
+#define ixSMU_PM_STATUS_112 0x33fc0
+#define ixSMU_PM_STATUS_113 0x33fc4
+#define ixSMU_PM_STATUS_114 0x33fc8
+#define ixSMU_PM_STATUS_115 0x33fcc
+#define ixSMU_PM_STATUS_116 0x33fd0
+#define ixSMU_PM_STATUS_117 0x33fd4
+#define ixSMU_PM_STATUS_118 0x33fd8
+#define ixSMU_PM_STATUS_119 0x33fdc
+#define ixSMU_PM_STATUS_120 0x33fe0
+#define ixSMU_PM_STATUS_121 0x33fe4
+#define ixSMU_PM_STATUS_122 0x33fe8
+#define ixSMU_PM_STATUS_123 0x33fec
+#define ixSMU_PM_STATUS_124 0x33ff0
+#define ixSMU_PM_STATUS_125 0x33ff4
+#define ixSMU_PM_STATUS_126 0x33ff8
+#define ixSMU_PM_STATUS_127 0x33ffc
+#define ixCG_THERMAL_INT_ENA 0xc2100024
+#define ixCG_THERMAL_INT_CTRL 0xc2100028
+#define ixCG_THERMAL_INT_STATUS 0xc210002c
+#define ixCG_THERMAL_CTRL 0xc0300004
+#define ixCG_THERMAL_STATUS 0xc0300008
+#define ixCG_THERMAL_INT 0xc030000c
+#define ixCG_MULT_THERMAL_CTRL 0xc0300010
+#define ixCG_MULT_THERMAL_STATUS 0xc0300014
+#define ixCG_FDO_CTRL0 0xc0300064
+#define ixCG_FDO_CTRL1 0xc0300068
+#define ixCG_FDO_CTRL2 0xc030006c
+#define ixCG_TACH_CTRL 0xc0300070
+#define ixCG_TACH_STATUS 0xc0300074
+#define ixCC_THM_STRAPS0 0xc0300080
+#define ixTHM_TMON0_RDIL0_DATA 0xc0300100
+#define ixTHM_TMON0_RDIL1_DATA 0xc0300104
+#define ixTHM_TMON0_RDIL2_DATA 0xc0300108
+#define ixTHM_TMON0_RDIL3_DATA 0xc030010c
+#define ixTHM_TMON0_RDIL4_DATA 0xc0300110
+#define ixTHM_TMON0_RDIL5_DATA 0xc0300114
+#define ixTHM_TMON0_RDIL6_DATA 0xc0300118
+#define ixTHM_TMON0_RDIL7_DATA 0xc030011c
+#define ixTHM_TMON0_RDIL8_DATA 0xc0300120
+#define ixTHM_TMON0_RDIL9_DATA 0xc0300124
+#define ixTHM_TMON0_RDIL10_DATA 0xc0300128
+#define ixTHM_TMON0_RDIL11_DATA 0xc030012c
+#define ixTHM_TMON0_RDIL12_DATA 0xc0300130
+#define ixTHM_TMON0_RDIL13_DATA 0xc0300134
+#define ixTHM_TMON0_RDIL14_DATA 0xc0300138
+#define ixTHM_TMON0_RDIL15_DATA 0xc030013c
+#define ixTHM_TMON0_RDIR0_DATA 0xc0300140
+#define ixTHM_TMON0_RDIR1_DATA 0xc0300144
+#define ixTHM_TMON0_RDIR2_DATA 0xc0300148
+#define ixTHM_TMON0_RDIR3_DATA 0xc030014c
+#define ixTHM_TMON0_RDIR4_DATA 0xc0300150
+#define ixTHM_TMON0_RDIR5_DATA 0xc0300154
+#define ixTHM_TMON0_RDIR6_DATA 0xc0300158
+#define ixTHM_TMON0_RDIR7_DATA 0xc030015c
+#define ixTHM_TMON0_RDIR8_DATA 0xc0300160
+#define ixTHM_TMON0_RDIR9_DATA 0xc0300164
+#define ixTHM_TMON0_RDIR10_DATA 0xc0300168
+#define ixTHM_TMON0_RDIR11_DATA 0xc030016c
+#define ixTHM_TMON0_RDIR12_DATA 0xc0300170
+#define ixTHM_TMON0_RDIR13_DATA 0xc0300174
+#define ixTHM_TMON0_RDIR14_DATA 0xc0300178
+#define ixTHM_TMON0_RDIR15_DATA 0xc030017c
+#define ixTHM_TMON0_INT_DATA 0xc0300300
+#define ixTHM_TMON0_DEBUG 0xc0300310
+#define ixTHM_TMON0_STATUS 0xc0300320
+#define ixGENERAL_PWRMGT 0xc0200000
+#define ixCNB_PWRMGT_CNTL 0xc0200004
+#define ixSCLK_PWRMGT_CNTL 0xc0200008
+#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014
+#define ixPWR_PCC_CONTROL 0xc0200018
+#define ixPWR_PCC_GPIO_SELECT 0xc020001c
+#define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8
+#define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac
+#define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0
+#define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4
+#define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8
+#define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc
+#define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0
+#define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4
+#define ixPLL_TEST_CNTL 0xc020003c
+#define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044
+#define ixCG_DISPLAY_GAP_CNTL 0xc0200060
+#define ixCG_DISPLAY_GAP_CNTL2 0xc0200230
+#define ixCG_ACPI_CNTL 0xc0200064
+#define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080
+#define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084
+#define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c
+#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088
+#define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c
+#define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310
+#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0
+#define ixCG_ULV_PARAMETER 0xc020015c
+#define ixSCLK_MIN_DIV 0xc02003ac
+#define ixPWR_DISP_TIMER_0_CONTROL 0xc0200390
+#define ixPWR_DISP_TIMER_1_CONTROL 0xc020037c
+#define ixPWR_DISP_TIMER_2_CONTROL 0xc02003d0
+#define ixPWR_DISP_TIMER_3_CONTROL 0xc02003d4
+#define ixPWR_DISP_TIMER_4_CONTROL 0xc02003d8
+#define ixPWR_DISP_TIMER_5_CONTROL 0xc02003dc
+#define ixPWR_DISP_TIMER_6_CONTROL 0xc02003e0
+#define ixPWR_DISP_TIMER_7_CONTROL 0xc02003e4
+#define ixPWR_DISP_TIMER_8_CONTROL 0xc02003e8
+#define ixPWR_DISP_TIMER_9_CONTROL 0xc02003ec
+#define ixPWR_DISP_TIMER_10_CONTROL 0xc02003f0
+#define ixPWR_DISP_TIMER_11_CONTROL 0xc02003f4
+#define ixPWR_DISP_TIMER_12_CONTROL 0xc02003f8
+#define ixPWR_DISP_TIMER_13_CONTROL 0xc02003fc
+#define ixPWR_DISP_TIMER_14_CONTROL 0xc0200074
+#define ixPWR_DISP_TIMER_15_CONTROL 0xc0200078
+#define ixPWR_DISP_TIMER_CONTROL2 0xc0200378
+#define ixVDDGFX_IDLE_PARAMETER 0xc020036c
+#define ixVDDGFX_IDLE_CONTROL 0xc0200370
+#define ixVDDGFX_IDLE_EXIT 0xc0200374
+#define ixLCAC_MC0_CNTL 0xc0400130
+#define ixLCAC_MC0_OVR_SEL 0xc0400134
+#define ixLCAC_MC0_OVR_VAL 0xc0400138
+#define ixLCAC_MC1_CNTL 0xc040013c
+#define ixLCAC_MC1_OVR_SEL 0xc0400140
+#define ixLCAC_MC1_OVR_VAL 0xc0400144
+#define ixLCAC_MC2_CNTL 0xc0400148
+#define ixLCAC_MC2_OVR_SEL 0xc040014c
+#define ixLCAC_MC2_OVR_VAL 0xc0400150
+#define ixLCAC_MC3_CNTL 0xc0400154
+#define ixLCAC_MC3_OVR_SEL 0xc0400158
+#define ixLCAC_MC3_OVR_VAL 0xc040015c
+#define ixLCAC_CPL_CNTL 0xc0400160
+#define ixLCAC_CPL_OVR_SEL 0xc0400164
+#define ixLCAC_CPL_OVR_VAL 0xc0400168
+#define mmROM_SMC_IND_INDEX 0x80
+#define mmROM0_ROM_SMC_IND_INDEX 0x80
+#define mmROM1_ROM_SMC_IND_INDEX 0x82
+#define mmROM2_ROM_SMC_IND_INDEX 0x84
+#define mmROM3_ROM_SMC_IND_INDEX 0x86
+#define mmROM_SMC_IND_DATA 0x81
+#define mmROM0_ROM_SMC_IND_DATA 0x81
+#define mmROM1_ROM_SMC_IND_DATA 0x83
+#define mmROM2_ROM_SMC_IND_DATA 0x85
+#define mmROM3_ROM_SMC_IND_DATA 0x87
+#define ixROM_CNTL 0xc0600000
+#define ixPAGE_MIRROR_CNTL 0xc0600004
+#define ixROM_STATUS 0xc0600008
+#define ixCGTT_ROM_CLK_CTRL0 0xc060000c
+#define ixROM_INDEX 0xc0600010
+#define ixROM_DATA 0xc0600014
+#define ixROM_START 0xc0600018
+#define ixROM_SW_CNTL 0xc060001c
+#define ixROM_SW_STATUS 0xc0600020
+#define ixROM_SW_COMMAND 0xc0600024
+#define ixROM_SW_DATA_1 0xc0600028
+#define ixROM_SW_DATA_2 0xc060002c
+#define ixROM_SW_DATA_3 0xc0600030
+#define ixROM_SW_DATA_4 0xc0600034
+#define ixROM_SW_DATA_5 0xc0600038
+#define ixROM_SW_DATA_6 0xc060003c
+#define ixROM_SW_DATA_7 0xc0600040
+#define ixROM_SW_DATA_8 0xc0600044
+#define ixROM_SW_DATA_9 0xc0600048
+#define ixROM_SW_DATA_10 0xc060004c
+#define ixROM_SW_DATA_11 0xc0600050
+#define ixROM_SW_DATA_12 0xc0600054
+#define ixROM_SW_DATA_13 0xc0600058
+#define ixROM_SW_DATA_14 0xc060005c
+#define ixROM_SW_DATA_15 0xc0600060
+#define ixROM_SW_DATA_16 0xc0600064
+#define ixROM_SW_DATA_17 0xc0600068
+#define ixROM_SW_DATA_18 0xc060006c
+#define ixROM_SW_DATA_19 0xc0600070
+#define ixROM_SW_DATA_20 0xc0600074
+#define ixROM_SW_DATA_21 0xc0600078
+#define ixROM_SW_DATA_22 0xc060007c
+#define ixROM_SW_DATA_23 0xc0600080
+#define ixROM_SW_DATA_24 0xc0600084
+#define ixROM_SW_DATA_25 0xc0600088
+#define ixROM_SW_DATA_26 0xc060008c
+#define ixROM_SW_DATA_27 0xc0600090
+#define ixROM_SW_DATA_28 0xc0600094
+#define ixROM_SW_DATA_29 0xc0600098
+#define ixROM_SW_DATA_30 0xc060009c
+#define ixROM_SW_DATA_31 0xc06000a0
+#define ixROM_SW_DATA_32 0xc06000a4
+#define ixROM_SW_DATA_33 0xc06000a8
+#define ixROM_SW_DATA_34 0xc06000ac
+#define ixROM_SW_DATA_35 0xc06000b0
+#define ixROM_SW_DATA_36 0xc06000b4
+#define ixROM_SW_DATA_37 0xc06000b8
+#define ixROM_SW_DATA_38 0xc06000bc
+#define ixROM_SW_DATA_39 0xc06000c0
+#define ixROM_SW_DATA_40 0xc06000c4
+#define ixROM_SW_DATA_41 0xc06000c8
+#define ixROM_SW_DATA_42 0xc06000cc
+#define ixROM_SW_DATA_43 0xc06000d0
+#define ixROM_SW_DATA_44 0xc06000d4
+#define ixROM_SW_DATA_45 0xc06000d8
+#define ixROM_SW_DATA_46 0xc06000dc
+#define ixROM_SW_DATA_47 0xc06000e0
+#define ixROM_SW_DATA_48 0xc06000e4
+#define ixROM_SW_DATA_49 0xc06000e8
+#define ixROM_SW_DATA_50 0xc06000ec
+#define ixROM_SW_DATA_51 0xc06000f0
+#define ixROM_SW_DATA_52 0xc06000f4
+#define ixROM_SW_DATA_53 0xc06000f8
+#define ixROM_SW_DATA_54 0xc06000fc
+#define ixROM_SW_DATA_55 0xc0600100
+#define ixROM_SW_DATA_56 0xc0600104
+#define ixROM_SW_DATA_57 0xc0600108
+#define ixROM_SW_DATA_58 0xc060010c
+#define ixROM_SW_DATA_59 0xc0600110
+#define ixROM_SW_DATA_60 0xc0600114
+#define ixROM_SW_DATA_61 0xc0600118
+#define ixROM_SW_DATA_62 0xc060011c
+#define ixROM_SW_DATA_63 0xc0600120
+#define ixROM_SW_DATA_64 0xc0600124
+
+#endif /* SMU_7_1_1_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_enum.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_enum.h
new file mode 100644
index 000000000000..c1a7aba19223
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_enum.h
@@ -0,0 +1,1205 @@
+/*
+ * SMU_7_1_1 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef SMU_7_1_1_ENUM_H
+#define SMU_7_1_1_ENUM_H
+
+#define CG_SRBM_START_ADDR 0x600
+#define CG_SRBM_END_ADDR 0x8ff
+#define RCU_CCF_DWORDS0 0x80
+#define RCU_CCF_BITS0 0x1000
+#define RCU_CCF_DWORDS1 0x0
+#define RCU_CCF_BITS1 0x0
+#define RCU_SAM_BYTES 0x0
+#define RCU_SAM_RTL_BYTES 0x0
+#define RCU_SMU_BYTES 0x0
+#define RCU_SMU_RTL_BYTES 0x0
+#define SFP_CHAIN_ADDR 0x0
+#define SFP_BYTES 0x80
+#define SFP_SADR 0x180
+#define SFP_EADR 0x1ff
+#define SAMU_KEY_CHAIN_ADR 0x0
+#define SAMU_KEY_SADR 0x0
+#define SAMU_KEY_EADR 0x0
+#define SMU_KEY_CHAIN_ADR 0x0
+#define SMU_KEY_SADR 0x0
+#define SMU_KEY_EADR 0x0
+#define SMC_MSG_TEST 0x1
+#define SMC_MSG_PHY_LN_OFF 0x2
+#define SMC_MSG_PHY_LN_ON 0x3
+#define SMC_MSG_DDI_PHY_OFF 0x4
+#define SMC_MSG_DDI_PHY_ON 0x5
+#define SMC_MSG_CASCADE_PLL_OFF 0x6
+#define SMC_MSG_CASCADE_PLL_ON 0x7
+#define SMC_MSG_PWR_OFF_x16 0x8
+#define SMC_MSG_CONFIG_LCLK_DPM 0x9
+#define SMC_MSG_FLUSH_DATA_CACHE 0xa
+#define SMC_MSG_FLUSH_INSTRUCTION_CACHE 0xb
+#define SMC_MSG_CONFIG_VPC_ACCUMULATOR 0xc
+#define SMC_MSG_CONFIG_BAPM 0xd
+#define SMC_MSG_CONFIG_TDC_LIMIT 0xe
+#define SMC_MSG_CONFIG_LPMx 0xf
+#define SMC_MSG_CONFIG_HTC_LIMIT 0x10
+#define SMC_MSG_CONFIG_THERMAL_CNTL 0x11
+#define SMC_MSG_CONFIG_VOLTAGE_CNTL 0x12
+#define SMC_MSG_CONFIG_TDP_CNTL 0x13
+#define SMC_MSG_EN_PM_CNTL 0x14
+#define SMC_MSG_DIS_PM_CNTL 0x15
+#define SMC_MSG_CONFIG_NBDPM 0x16
+#define SMC_MSG_CONFIG_LOADLINE 0x17
+#define SMC_MSG_ADJUST_LOADLINE 0x18
+#define SMC_MSG_RESET 0x20
+#define SMC_MSG_VOLTAGE 0x25
+#define SMC_VERSION_MAJOR 0x7
+#define SMC_VERSION_MINOR 0x0
+#define SMC_HEADER_SIZE 0x40
+#define ROM_SIGNATURE 0xaa55
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0x0,
+ ENDIAN_8IN16 = 0x1,
+ ENDIAN_8IN32 = 0x2,
+ ENDIAN_8IN64 = 0x3,
+} SurfaceEndian;
+typedef enum ArrayMode {
+ ARRAY_LINEAR_GENERAL = 0x0,
+ ARRAY_LINEAR_ALIGNED = 0x1,
+ ARRAY_1D_TILED_THIN1 = 0x2,
+ ARRAY_1D_TILED_THICK = 0x3,
+ ARRAY_2D_TILED_THIN1 = 0x4,
+ ARRAY_PRT_TILED_THIN1 = 0x5,
+ ARRAY_PRT_2D_TILED_THIN1 = 0x6,
+ ARRAY_2D_TILED_THICK = 0x7,
+ ARRAY_2D_TILED_XTHICK = 0x8,
+ ARRAY_PRT_TILED_THICK = 0x9,
+ ARRAY_PRT_2D_TILED_THICK = 0xa,
+ ARRAY_PRT_3D_TILED_THIN1 = 0xb,
+ ARRAY_3D_TILED_THIN1 = 0xc,
+ ARRAY_3D_TILED_THICK = 0xd,
+ ARRAY_3D_TILED_XTHICK = 0xe,
+ ARRAY_PRT_3D_TILED_THICK = 0xf,
+} ArrayMode;
+typedef enum PipeTiling {
+ CONFIG_1_PIPE = 0x0,
+ CONFIG_2_PIPE = 0x1,
+ CONFIG_4_PIPE = 0x2,
+ CONFIG_8_PIPE = 0x3,
+} PipeTiling;
+typedef enum BankTiling {
+ CONFIG_4_BANK = 0x0,
+ CONFIG_8_BANK = 0x1,
+} BankTiling;
+typedef enum GroupInterleave {
+ CONFIG_256B_GROUP = 0x0,
+ CONFIG_512B_GROUP = 0x1,
+} GroupInterleave;
+typedef enum RowTiling {
+ CONFIG_1KB_ROW = 0x0,
+ CONFIG_2KB_ROW = 0x1,
+ CONFIG_4KB_ROW = 0x2,
+ CONFIG_8KB_ROW = 0x3,
+ CONFIG_1KB_ROW_OPT = 0x4,
+ CONFIG_2KB_ROW_OPT = 0x5,
+ CONFIG_4KB_ROW_OPT = 0x6,
+ CONFIG_8KB_ROW_OPT = 0x7,
+} RowTiling;
+typedef enum BankSwapBytes {
+ CONFIG_128B_SWAPS = 0x0,
+ CONFIG_256B_SWAPS = 0x1,
+ CONFIG_512B_SWAPS = 0x2,
+ CONFIG_1KB_SWAPS = 0x3,
+} BankSwapBytes;
+typedef enum SampleSplitBytes {
+ CONFIG_1KB_SPLIT = 0x0,
+ CONFIG_2KB_SPLIT = 0x1,
+ CONFIG_4KB_SPLIT = 0x2,
+ CONFIG_8KB_SPLIT = 0x3,
+} SampleSplitBytes;
+typedef enum NumPipes {
+ ADDR_CONFIG_1_PIPE = 0x0,
+ ADDR_CONFIG_2_PIPE = 0x1,
+ ADDR_CONFIG_4_PIPE = 0x2,
+ ADDR_CONFIG_8_PIPE = 0x3,
+} NumPipes;
+typedef enum PipeInterleaveSize {
+ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
+ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
+} PipeInterleaveSize;
+typedef enum BankInterleaveSize {
+ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
+ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
+ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
+ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
+} BankInterleaveSize;
+typedef enum NumShaderEngines {
+ ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
+ ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
+} NumShaderEngines;
+typedef enum ShaderEngineTileSize {
+ ADDR_CONFIG_SE_TILE_16 = 0x0,
+ ADDR_CONFIG_SE_TILE_32 = 0x1,
+} ShaderEngineTileSize;
+typedef enum NumGPUs {
+ ADDR_CONFIG_1_GPU = 0x0,
+ ADDR_CONFIG_2_GPU = 0x1,
+ ADDR_CONFIG_4_GPU = 0x2,
+} NumGPUs;
+typedef enum MultiGPUTileSize {
+ ADDR_CONFIG_GPU_TILE_16 = 0x0,
+ ADDR_CONFIG_GPU_TILE_32 = 0x1,
+ ADDR_CONFIG_GPU_TILE_64 = 0x2,
+ ADDR_CONFIG_GPU_TILE_128 = 0x3,
+} MultiGPUTileSize;
+typedef enum RowSize {
+ ADDR_CONFIG_1KB_ROW = 0x0,
+ ADDR_CONFIG_2KB_ROW = 0x1,
+ ADDR_CONFIG_4KB_ROW = 0x2,
+} RowSize;
+typedef enum NumLowerPipes {
+ ADDR_CONFIG_1_LOWER_PIPES = 0x0,
+ ADDR_CONFIG_2_LOWER_PIPES = 0x1,
+} NumLowerPipes;
+typedef enum DebugBlockId {
+ DBG_CLIENT_BLKID_RESERVED = 0x0,
+ DBG_CLIENT_BLKID_dbg = 0x1,
+ DBG_CLIENT_BLKID_uvdu_0 = 0x2,
+ DBG_CLIENT_BLKID_uvdu_1 = 0x3,
+ DBG_CLIENT_BLKID_uvdu_2 = 0x4,
+ DBG_CLIENT_BLKID_uvdu_3 = 0x5,
+ DBG_CLIENT_BLKID_uvdu_4 = 0x6,
+ DBG_CLIENT_BLKID_uvdu_5 = 0x7,
+ DBG_CLIENT_BLKID_uvdu_6 = 0x8,
+ DBG_CLIENT_BLKID_uvdb_0 = 0x9,
+ DBG_CLIENT_BLKID_uvdc_0 = 0xa,
+ DBG_CLIENT_BLKID_uvdc_1 = 0xb,
+ DBG_CLIENT_BLKID_uvdf_0 = 0xc,
+ DBG_CLIENT_BLKID_uvdf_1 = 0xd,
+ DBG_CLIENT_BLKID_uvdm_0 = 0xe,
+ DBG_CLIENT_BLKID_uvdm_1 = 0xf,
+ DBG_CLIENT_BLKID_uvdm_2 = 0x10,
+ DBG_CLIENT_BLKID_uvdm_3 = 0x11,
+ DBG_CLIENT_BLKID_vcea_0 = 0x12,
+ DBG_CLIENT_BLKID_vcea_1 = 0x13,
+ DBG_CLIENT_BLKID_vcea_2 = 0x14,
+ DBG_CLIENT_BLKID_vcea_3 = 0x15,
+ DBG_CLIENT_BLKID_vceb_0 = 0x16,
+ DBG_CLIENT_BLKID_vcec_0 = 0x17,
+ DBG_CLIENT_BLKID_dco = 0x18,
+ DBG_CLIENT_BLKID_xdma = 0x19,
+ DBG_CLIENT_BLKID_dci_pg = 0x1a,
+ DBG_CLIENT_BLKID_smu_0 = 0x1b,
+ DBG_CLIENT_BLKID_smu_1 = 0x1c,
+ DBG_CLIENT_BLKID_smu_2 = 0x1d,
+ DBG_CLIENT_BLKID_gck = 0x1e,
+ DBG_CLIENT_BLKID_tmonw0 = 0x1f,
+ DBG_CLIENT_BLKID_tmonw1 = 0x20,
+ DBG_CLIENT_BLKID_grbm = 0x21,
+ DBG_CLIENT_BLKID_rlc = 0x22,
+ DBG_CLIENT_BLKID_ds0 = 0x23,
+ DBG_CLIENT_BLKID_cpg_0 = 0x24,
+ DBG_CLIENT_BLKID_cpg_1 = 0x25,
+ DBG_CLIENT_BLKID_cpc_0 = 0x26,
+ DBG_CLIENT_BLKID_cpc_1 = 0x27,
+ DBG_CLIENT_BLKID_cpf_0 = 0x28,
+ DBG_CLIENT_BLKID_cpf_1 = 0x29,
+ DBG_CLIENT_BLKID_scf0 = 0x2a,
+ DBG_CLIENT_BLKID_scf1 = 0x2b,
+ DBG_CLIENT_BLKID_scf2 = 0x2c,
+ DBG_CLIENT_BLKID_scf3 = 0x2d,
+ DBG_CLIENT_BLKID_pc0 = 0x2e,
+ DBG_CLIENT_BLKID_pc1 = 0x2f,
+ DBG_CLIENT_BLKID_pc2 = 0x30,
+ DBG_CLIENT_BLKID_pc3 = 0x31,
+ DBG_CLIENT_BLKID_vgt0 = 0x32,
+ DBG_CLIENT_BLKID_vgt1 = 0x33,
+ DBG_CLIENT_BLKID_vgt2 = 0x34,
+ DBG_CLIENT_BLKID_vgt3 = 0x35,
+ DBG_CLIENT_BLKID_sx00 = 0x36,
+ DBG_CLIENT_BLKID_sx10 = 0x37,
+ DBG_CLIENT_BLKID_sx20 = 0x38,
+ DBG_CLIENT_BLKID_sx30 = 0x39,
+ DBG_CLIENT_BLKID_cb001 = 0x3a,
+ DBG_CLIENT_BLKID_cb200 = 0x3b,
+ DBG_CLIENT_BLKID_cb201 = 0x3c,
+ DBG_CLIENT_BLKID_cbr0 = 0x3d,
+ DBG_CLIENT_BLKID_cb000 = 0x3e,
+ DBG_CLIENT_BLKID_cb101 = 0x3f,
+ DBG_CLIENT_BLKID_cb300 = 0x40,
+ DBG_CLIENT_BLKID_cb301 = 0x41,
+ DBG_CLIENT_BLKID_cbr1 = 0x42,
+ DBG_CLIENT_BLKID_cb100 = 0x43,
+ DBG_CLIENT_BLKID_ia0 = 0x44,
+ DBG_CLIENT_BLKID_ia1 = 0x45,
+ DBG_CLIENT_BLKID_bci0 = 0x46,
+ DBG_CLIENT_BLKID_bci1 = 0x47,
+ DBG_CLIENT_BLKID_bci2 = 0x48,
+ DBG_CLIENT_BLKID_bci3 = 0x49,
+ DBG_CLIENT_BLKID_pa0 = 0x4a,
+ DBG_CLIENT_BLKID_pa1 = 0x4b,
+ DBG_CLIENT_BLKID_spim0 = 0x4c,
+ DBG_CLIENT_BLKID_spim1 = 0x4d,
+ DBG_CLIENT_BLKID_spim2 = 0x4e,
+ DBG_CLIENT_BLKID_spim3 = 0x4f,
+ DBG_CLIENT_BLKID_sdma = 0x50,
+ DBG_CLIENT_BLKID_ih = 0x51,
+ DBG_CLIENT_BLKID_sem = 0x52,
+ DBG_CLIENT_BLKID_srbm = 0x53,
+ DBG_CLIENT_BLKID_hdp = 0x54,
+ DBG_CLIENT_BLKID_acp_0 = 0x55,
+ DBG_CLIENT_BLKID_acp_1 = 0x56,
+ DBG_CLIENT_BLKID_sam = 0x57,
+ DBG_CLIENT_BLKID_mcc0 = 0x58,
+ DBG_CLIENT_BLKID_mcc1 = 0x59,
+ DBG_CLIENT_BLKID_mcc2 = 0x5a,
+ DBG_CLIENT_BLKID_mcc3 = 0x5b,
+ DBG_CLIENT_BLKID_mcd0 = 0x5c,
+ DBG_CLIENT_BLKID_mcd1 = 0x5d,
+ DBG_CLIENT_BLKID_mcd2 = 0x5e,
+ DBG_CLIENT_BLKID_mcd3 = 0x5f,
+ DBG_CLIENT_BLKID_mcb = 0x60,
+ DBG_CLIENT_BLKID_vmc = 0x61,
+ DBG_CLIENT_BLKID_gmcon = 0x62,
+ DBG_CLIENT_BLKID_gdc_0 = 0x63,
+ DBG_CLIENT_BLKID_gdc_1 = 0x64,
+ DBG_CLIENT_BLKID_gdc_2 = 0x65,
+ DBG_CLIENT_BLKID_gdc_3 = 0x66,
+ DBG_CLIENT_BLKID_gdc_4 = 0x67,
+ DBG_CLIENT_BLKID_gdc_5 = 0x68,
+ DBG_CLIENT_BLKID_gdc_6 = 0x69,
+ DBG_CLIENT_BLKID_gdc_7 = 0x6a,
+ DBG_CLIENT_BLKID_gdc_8 = 0x6b,
+ DBG_CLIENT_BLKID_gdc_9 = 0x6c,
+ DBG_CLIENT_BLKID_gdc_10 = 0x6d,
+ DBG_CLIENT_BLKID_gdc_11 = 0x6e,
+ DBG_CLIENT_BLKID_gdc_12 = 0x6f,
+ DBG_CLIENT_BLKID_gdc_13 = 0x70,
+ DBG_CLIENT_BLKID_gdc_14 = 0x71,
+ DBG_CLIENT_BLKID_gdc_15 = 0x72,
+ DBG_CLIENT_BLKID_gdc_16 = 0x73,
+ DBG_CLIENT_BLKID_gdc_17 = 0x74,
+ DBG_CLIENT_BLKID_gdc_18 = 0x75,
+ DBG_CLIENT_BLKID_gdc_19 = 0x76,
+ DBG_CLIENT_BLKID_gdc_20 = 0x77,
+ DBG_CLIENT_BLKID_gdc_21 = 0x78,
+ DBG_CLIENT_BLKID_gdc_22 = 0x79,
+ DBG_CLIENT_BLKID_gdc_23 = 0x7a,
+ DBG_CLIENT_BLKID_gdc_24 = 0x7b,
+ DBG_CLIENT_BLKID_gdc_25 = 0x7c,
+ DBG_CLIENT_BLKID_gdc_26 = 0x7d,
+ DBG_CLIENT_BLKID_gdc_27 = 0x7e,
+ DBG_CLIENT_BLKID_gdc_28 = 0x7f,
+ DBG_CLIENT_BLKID_wd = 0x80,
+ DBG_CLIENT_BLKID_sdma_0 = 0x81,
+ DBG_CLIENT_BLKID_sdma_1 = 0x82,
+ DBG_CLIENT_BLKID_sammsp = 0x83,
+ DBG_CLIENT_BLKID_dci_0 = 0x84,
+ DBG_CLIENT_BLKID_dccg0_0 = 0x85,
+ DBG_CLIENT_BLKID_dcfe01_0 = 0x86,
+ DBG_CLIENT_BLKID_dcfe02_0 = 0x87,
+ DBG_CLIENT_BLKID_dcfe03_0 = 0x88,
+ DBG_CLIENT_BLKID_dccg0_1 = 0x89,
+} DebugBlockId;
+typedef enum DebugBlockId_OLD {
+ DBG_BLOCK_ID_RESERVED = 0x0,
+ DBG_BLOCK_ID_DBG = 0x1,
+ DBG_BLOCK_ID_VMC = 0x2,
+ DBG_BLOCK_ID_PDMA = 0x3,
+ DBG_BLOCK_ID_CG = 0x4,
+ DBG_BLOCK_ID_SRBM = 0x5,
+ DBG_BLOCK_ID_GRBM = 0x6,
+ DBG_BLOCK_ID_RLC = 0x7,
+ DBG_BLOCK_ID_CSC = 0x8,
+ DBG_BLOCK_ID_SEM = 0x9,
+ DBG_BLOCK_ID_IH = 0xa,
+ DBG_BLOCK_ID_SC = 0xb,
+ DBG_BLOCK_ID_SQ = 0xc,
+ DBG_BLOCK_ID_AVP = 0xd,
+ DBG_BLOCK_ID_GMCON = 0xe,
+ DBG_BLOCK_ID_SMU = 0xf,
+ DBG_BLOCK_ID_DMA0 = 0x10,
+ DBG_BLOCK_ID_DMA1 = 0x11,
+ DBG_BLOCK_ID_SPIM = 0x12,
+ DBG_BLOCK_ID_GDS = 0x13,
+ DBG_BLOCK_ID_SPIS = 0x14,
+ DBG_BLOCK_ID_UNUSED0 = 0x15,
+ DBG_BLOCK_ID_PA0 = 0x16,
+ DBG_BLOCK_ID_PA1 = 0x17,
+ DBG_BLOCK_ID_CP0 = 0x18,
+ DBG_BLOCK_ID_CP1 = 0x19,
+ DBG_BLOCK_ID_CP2 = 0x1a,
+ DBG_BLOCK_ID_UNUSED1 = 0x1b,
+ DBG_BLOCK_ID_UVDU = 0x1c,
+ DBG_BLOCK_ID_UVDM = 0x1d,
+ DBG_BLOCK_ID_VCE = 0x1e,
+ DBG_BLOCK_ID_UNUSED2 = 0x1f,
+ DBG_BLOCK_ID_VGT0 = 0x20,
+ DBG_BLOCK_ID_VGT1 = 0x21,
+ DBG_BLOCK_ID_IA = 0x22,
+ DBG_BLOCK_ID_UNUSED3 = 0x23,
+ DBG_BLOCK_ID_SCT0 = 0x24,
+ DBG_BLOCK_ID_SCT1 = 0x25,
+ DBG_BLOCK_ID_SPM0 = 0x26,
+ DBG_BLOCK_ID_SPM1 = 0x27,
+ DBG_BLOCK_ID_TCAA = 0x28,
+ DBG_BLOCK_ID_TCAB = 0x29,
+ DBG_BLOCK_ID_TCCA = 0x2a,
+ DBG_BLOCK_ID_TCCB = 0x2b,
+ DBG_BLOCK_ID_MCC0 = 0x2c,
+ DBG_BLOCK_ID_MCC1 = 0x2d,
+ DBG_BLOCK_ID_MCC2 = 0x2e,
+ DBG_BLOCK_ID_MCC3 = 0x2f,
+ DBG_BLOCK_ID_SX0 = 0x30,
+ DBG_BLOCK_ID_SX1 = 0x31,
+ DBG_BLOCK_ID_SX2 = 0x32,
+ DBG_BLOCK_ID_SX3 = 0x33,
+ DBG_BLOCK_ID_UNUSED4 = 0x34,
+ DBG_BLOCK_ID_UNUSED5 = 0x35,
+ DBG_BLOCK_ID_UNUSED6 = 0x36,
+ DBG_BLOCK_ID_UNUSED7 = 0x37,
+ DBG_BLOCK_ID_PC0 = 0x38,
+ DBG_BLOCK_ID_PC1 = 0x39,
+ DBG_BLOCK_ID_UNUSED8 = 0x3a,
+ DBG_BLOCK_ID_UNUSED9 = 0x3b,
+ DBG_BLOCK_ID_UNUSED10 = 0x3c,
+ DBG_BLOCK_ID_UNUSED11 = 0x3d,
+ DBG_BLOCK_ID_MCB = 0x3e,
+ DBG_BLOCK_ID_UNUSED12 = 0x3f,
+ DBG_BLOCK_ID_SCB0 = 0x40,
+ DBG_BLOCK_ID_SCB1 = 0x41,
+ DBG_BLOCK_ID_UNUSED13 = 0x42,
+ DBG_BLOCK_ID_UNUSED14 = 0x43,
+ DBG_BLOCK_ID_SCF0 = 0x44,
+ DBG_BLOCK_ID_SCF1 = 0x45,
+ DBG_BLOCK_ID_UNUSED15 = 0x46,
+ DBG_BLOCK_ID_UNUSED16 = 0x47,
+ DBG_BLOCK_ID_BCI0 = 0x48,
+ DBG_BLOCK_ID_BCI1 = 0x49,
+ DBG_BLOCK_ID_BCI2 = 0x4a,
+ DBG_BLOCK_ID_BCI3 = 0x4b,
+ DBG_BLOCK_ID_UNUSED17 = 0x4c,
+ DBG_BLOCK_ID_UNUSED18 = 0x4d,
+ DBG_BLOCK_ID_UNUSED19 = 0x4e,
+ DBG_BLOCK_ID_UNUSED20 = 0x4f,
+ DBG_BLOCK_ID_CB00 = 0x50,
+ DBG_BLOCK_ID_CB01 = 0x51,
+ DBG_BLOCK_ID_CB02 = 0x52,
+ DBG_BLOCK_ID_CB03 = 0x53,
+ DBG_BLOCK_ID_CB04 = 0x54,
+ DBG_BLOCK_ID_UNUSED21 = 0x55,
+ DBG_BLOCK_ID_UNUSED22 = 0x56,
+ DBG_BLOCK_ID_UNUSED23 = 0x57,
+ DBG_BLOCK_ID_CB10 = 0x58,
+ DBG_BLOCK_ID_CB11 = 0x59,
+ DBG_BLOCK_ID_CB12 = 0x5a,
+ DBG_BLOCK_ID_CB13 = 0x5b,
+ DBG_BLOCK_ID_CB14 = 0x5c,
+ DBG_BLOCK_ID_UNUSED24 = 0x5d,
+ DBG_BLOCK_ID_UNUSED25 = 0x5e,
+ DBG_BLOCK_ID_UNUSED26 = 0x5f,
+ DBG_BLOCK_ID_TCP0 = 0x60,
+ DBG_BLOCK_ID_TCP1 = 0x61,
+ DBG_BLOCK_ID_TCP2 = 0x62,
+ DBG_BLOCK_ID_TCP3 = 0x63,
+ DBG_BLOCK_ID_TCP4 = 0x64,
+ DBG_BLOCK_ID_TCP5 = 0x65,
+ DBG_BLOCK_ID_TCP6 = 0x66,
+ DBG_BLOCK_ID_TCP7 = 0x67,
+ DBG_BLOCK_ID_TCP8 = 0x68,
+ DBG_BLOCK_ID_TCP9 = 0x69,
+ DBG_BLOCK_ID_TCP10 = 0x6a,
+ DBG_BLOCK_ID_TCP11 = 0x6b,
+ DBG_BLOCK_ID_TCP12 = 0x6c,
+ DBG_BLOCK_ID_TCP13 = 0x6d,
+ DBG_BLOCK_ID_TCP14 = 0x6e,
+ DBG_BLOCK_ID_TCP15 = 0x6f,
+ DBG_BLOCK_ID_TCP16 = 0x70,
+ DBG_BLOCK_ID_TCP17 = 0x71,
+ DBG_BLOCK_ID_TCP18 = 0x72,
+ DBG_BLOCK_ID_TCP19 = 0x73,
+ DBG_BLOCK_ID_TCP20 = 0x74,
+ DBG_BLOCK_ID_TCP21 = 0x75,
+ DBG_BLOCK_ID_TCP22 = 0x76,
+ DBG_BLOCK_ID_TCP23 = 0x77,
+ DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
+ DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
+ DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
+ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
+ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
+ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
+ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
+ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
+ DBG_BLOCK_ID_DB00 = 0x80,
+ DBG_BLOCK_ID_DB01 = 0x81,
+ DBG_BLOCK_ID_DB02 = 0x82,
+ DBG_BLOCK_ID_DB03 = 0x83,
+ DBG_BLOCK_ID_DB04 = 0x84,
+ DBG_BLOCK_ID_UNUSED27 = 0x85,
+ DBG_BLOCK_ID_UNUSED28 = 0x86,
+ DBG_BLOCK_ID_UNUSED29 = 0x87,
+ DBG_BLOCK_ID_DB10 = 0x88,
+ DBG_BLOCK_ID_DB11 = 0x89,
+ DBG_BLOCK_ID_DB12 = 0x8a,
+ DBG_BLOCK_ID_DB13 = 0x8b,
+ DBG_BLOCK_ID_DB14 = 0x8c,
+ DBG_BLOCK_ID_UNUSED30 = 0x8d,
+ DBG_BLOCK_ID_UNUSED31 = 0x8e,
+ DBG_BLOCK_ID_UNUSED32 = 0x8f,
+ DBG_BLOCK_ID_TCC0 = 0x90,
+ DBG_BLOCK_ID_TCC1 = 0x91,
+ DBG_BLOCK_ID_TCC2 = 0x92,
+ DBG_BLOCK_ID_TCC3 = 0x93,
+ DBG_BLOCK_ID_TCC4 = 0x94,
+ DBG_BLOCK_ID_TCC5 = 0x95,
+ DBG_BLOCK_ID_TCC6 = 0x96,
+ DBG_BLOCK_ID_TCC7 = 0x97,
+ DBG_BLOCK_ID_SPS00 = 0x98,
+ DBG_BLOCK_ID_SPS01 = 0x99,
+ DBG_BLOCK_ID_SPS02 = 0x9a,
+ DBG_BLOCK_ID_SPS10 = 0x9b,
+ DBG_BLOCK_ID_SPS11 = 0x9c,
+ DBG_BLOCK_ID_SPS12 = 0x9d,
+ DBG_BLOCK_ID_UNUSED33 = 0x9e,
+ DBG_BLOCK_ID_UNUSED34 = 0x9f,
+ DBG_BLOCK_ID_TA00 = 0xa0,
+ DBG_BLOCK_ID_TA01 = 0xa1,
+ DBG_BLOCK_ID_TA02 = 0xa2,
+ DBG_BLOCK_ID_TA03 = 0xa3,
+ DBG_BLOCK_ID_TA04 = 0xa4,
+ DBG_BLOCK_ID_TA05 = 0xa5,
+ DBG_BLOCK_ID_TA06 = 0xa6,
+ DBG_BLOCK_ID_TA07 = 0xa7,
+ DBG_BLOCK_ID_TA08 = 0xa8,
+ DBG_BLOCK_ID_TA09 = 0xa9,
+ DBG_BLOCK_ID_TA0A = 0xaa,
+ DBG_BLOCK_ID_TA0B = 0xab,
+ DBG_BLOCK_ID_UNUSED35 = 0xac,
+ DBG_BLOCK_ID_UNUSED36 = 0xad,
+ DBG_BLOCK_ID_UNUSED37 = 0xae,
+ DBG_BLOCK_ID_UNUSED38 = 0xaf,
+ DBG_BLOCK_ID_TA10 = 0xb0,
+ DBG_BLOCK_ID_TA11 = 0xb1,
+ DBG_BLOCK_ID_TA12 = 0xb2,
+ DBG_BLOCK_ID_TA13 = 0xb3,
+ DBG_BLOCK_ID_TA14 = 0xb4,
+ DBG_BLOCK_ID_TA15 = 0xb5,
+ DBG_BLOCK_ID_TA16 = 0xb6,
+ DBG_BLOCK_ID_TA17 = 0xb7,
+ DBG_BLOCK_ID_TA18 = 0xb8,
+ DBG_BLOCK_ID_TA19 = 0xb9,
+ DBG_BLOCK_ID_TA1A = 0xba,
+ DBG_BLOCK_ID_TA1B = 0xbb,
+ DBG_BLOCK_ID_UNUSED39 = 0xbc,
+ DBG_BLOCK_ID_UNUSED40 = 0xbd,
+ DBG_BLOCK_ID_UNUSED41 = 0xbe,
+ DBG_BLOCK_ID_UNUSED42 = 0xbf,
+ DBG_BLOCK_ID_TD00 = 0xc0,
+ DBG_BLOCK_ID_TD01 = 0xc1,
+ DBG_BLOCK_ID_TD02 = 0xc2,
+ DBG_BLOCK_ID_TD03 = 0xc3,
+ DBG_BLOCK_ID_TD04 = 0xc4,
+ DBG_BLOCK_ID_TD05 = 0xc5,
+ DBG_BLOCK_ID_TD06 = 0xc6,
+ DBG_BLOCK_ID_TD07 = 0xc7,
+ DBG_BLOCK_ID_TD08 = 0xc8,
+ DBG_BLOCK_ID_TD09 = 0xc9,
+ DBG_BLOCK_ID_TD0A = 0xca,
+ DBG_BLOCK_ID_TD0B = 0xcb,
+ DBG_BLOCK_ID_UNUSED43 = 0xcc,
+ DBG_BLOCK_ID_UNUSED44 = 0xcd,
+ DBG_BLOCK_ID_UNUSED45 = 0xce,
+ DBG_BLOCK_ID_UNUSED46 = 0xcf,
+ DBG_BLOCK_ID_TD10 = 0xd0,
+ DBG_BLOCK_ID_TD11 = 0xd1,
+ DBG_BLOCK_ID_TD12 = 0xd2,
+ DBG_BLOCK_ID_TD13 = 0xd3,
+ DBG_BLOCK_ID_TD14 = 0xd4,
+ DBG_BLOCK_ID_TD15 = 0xd5,
+ DBG_BLOCK_ID_TD16 = 0xd6,
+ DBG_BLOCK_ID_TD17 = 0xd7,
+ DBG_BLOCK_ID_TD18 = 0xd8,
+ DBG_BLOCK_ID_TD19 = 0xd9,
+ DBG_BLOCK_ID_TD1A = 0xda,
+ DBG_BLOCK_ID_TD1B = 0xdb,
+ DBG_BLOCK_ID_UNUSED47 = 0xdc,
+ DBG_BLOCK_ID_UNUSED48 = 0xdd,
+ DBG_BLOCK_ID_UNUSED49 = 0xde,
+ DBG_BLOCK_ID_UNUSED50 = 0xdf,
+ DBG_BLOCK_ID_MCD0 = 0xe0,
+ DBG_BLOCK_ID_MCD1 = 0xe1,
+ DBG_BLOCK_ID_MCD2 = 0xe2,
+ DBG_BLOCK_ID_MCD3 = 0xe3,
+ DBG_BLOCK_ID_MCD4 = 0xe4,
+ DBG_BLOCK_ID_MCD5 = 0xe5,
+ DBG_BLOCK_ID_UNUSED51 = 0xe6,
+ DBG_BLOCK_ID_UNUSED52 = 0xe7,
+} DebugBlockId_OLD;
+typedef enum DebugBlockId_BY2 {
+ DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
+ DBG_BLOCK_ID_VMC_BY2 = 0x1,
+ DBG_BLOCK_ID_CG_BY2 = 0x2,
+ DBG_BLOCK_ID_GRBM_BY2 = 0x3,
+ DBG_BLOCK_ID_CSC_BY2 = 0x4,
+ DBG_BLOCK_ID_IH_BY2 = 0x5,
+ DBG_BLOCK_ID_SQ_BY2 = 0x6,
+ DBG_BLOCK_ID_GMCON_BY2 = 0x7,
+ DBG_BLOCK_ID_DMA0_BY2 = 0x8,
+ DBG_BLOCK_ID_SPIM_BY2 = 0x9,
+ DBG_BLOCK_ID_SPIS_BY2 = 0xa,
+ DBG_BLOCK_ID_PA0_BY2 = 0xb,
+ DBG_BLOCK_ID_CP0_BY2 = 0xc,
+ DBG_BLOCK_ID_CP2_BY2 = 0xd,
+ DBG_BLOCK_ID_UVDU_BY2 = 0xe,
+ DBG_BLOCK_ID_VCE_BY2 = 0xf,
+ DBG_BLOCK_ID_VGT0_BY2 = 0x10,
+ DBG_BLOCK_ID_IA_BY2 = 0x11,
+ DBG_BLOCK_ID_SCT0_BY2 = 0x12,
+ DBG_BLOCK_ID_SPM0_BY2 = 0x13,
+ DBG_BLOCK_ID_TCAA_BY2 = 0x14,
+ DBG_BLOCK_ID_TCCA_BY2 = 0x15,
+ DBG_BLOCK_ID_MCC0_BY2 = 0x16,
+ DBG_BLOCK_ID_MCC2_BY2 = 0x17,
+ DBG_BLOCK_ID_SX0_BY2 = 0x18,
+ DBG_BLOCK_ID_SX2_BY2 = 0x19,
+ DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
+ DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
+ DBG_BLOCK_ID_PC0_BY2 = 0x1c,
+ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
+ DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
+ DBG_BLOCK_ID_MCB_BY2 = 0x1f,
+ DBG_BLOCK_ID_SCB0_BY2 = 0x20,
+ DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
+ DBG_BLOCK_ID_SCF0_BY2 = 0x22,
+ DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
+ DBG_BLOCK_ID_BCI0_BY2 = 0x24,
+ DBG_BLOCK_ID_BCI2_BY2 = 0x25,
+ DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
+ DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
+ DBG_BLOCK_ID_CB00_BY2 = 0x28,
+ DBG_BLOCK_ID_CB02_BY2 = 0x29,
+ DBG_BLOCK_ID_CB04_BY2 = 0x2a,
+ DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
+ DBG_BLOCK_ID_CB10_BY2 = 0x2c,
+ DBG_BLOCK_ID_CB12_BY2 = 0x2d,
+ DBG_BLOCK_ID_CB14_BY2 = 0x2e,
+ DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
+ DBG_BLOCK_ID_TCP0_BY2 = 0x30,
+ DBG_BLOCK_ID_TCP2_BY2 = 0x31,
+ DBG_BLOCK_ID_TCP4_BY2 = 0x32,
+ DBG_BLOCK_ID_TCP6_BY2 = 0x33,
+ DBG_BLOCK_ID_TCP8_BY2 = 0x34,
+ DBG_BLOCK_ID_TCP10_BY2 = 0x35,
+ DBG_BLOCK_ID_TCP12_BY2 = 0x36,
+ DBG_BLOCK_ID_TCP14_BY2 = 0x37,
+ DBG_BLOCK_ID_TCP16_BY2 = 0x38,
+ DBG_BLOCK_ID_TCP18_BY2 = 0x39,
+ DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
+ DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
+ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
+ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
+ DBG_BLOCK_ID_DB00_BY2 = 0x40,
+ DBG_BLOCK_ID_DB02_BY2 = 0x41,
+ DBG_BLOCK_ID_DB04_BY2 = 0x42,
+ DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
+ DBG_BLOCK_ID_DB10_BY2 = 0x44,
+ DBG_BLOCK_ID_DB12_BY2 = 0x45,
+ DBG_BLOCK_ID_DB14_BY2 = 0x46,
+ DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
+ DBG_BLOCK_ID_TCC0_BY2 = 0x48,
+ DBG_BLOCK_ID_TCC2_BY2 = 0x49,
+ DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
+ DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
+ DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
+ DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
+ DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
+ DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
+ DBG_BLOCK_ID_TA00_BY2 = 0x50,
+ DBG_BLOCK_ID_TA02_BY2 = 0x51,
+ DBG_BLOCK_ID_TA04_BY2 = 0x52,
+ DBG_BLOCK_ID_TA06_BY2 = 0x53,
+ DBG_BLOCK_ID_TA08_BY2 = 0x54,
+ DBG_BLOCK_ID_TA0A_BY2 = 0x55,
+ DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
+ DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
+ DBG_BLOCK_ID_TA10_BY2 = 0x58,
+ DBG_BLOCK_ID_TA12_BY2 = 0x59,
+ DBG_BLOCK_ID_TA14_BY2 = 0x5a,
+ DBG_BLOCK_ID_TA16_BY2 = 0x5b,
+ DBG_BLOCK_ID_TA18_BY2 = 0x5c,
+ DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
+ DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
+ DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
+ DBG_BLOCK_ID_TD00_BY2 = 0x60,
+ DBG_BLOCK_ID_TD02_BY2 = 0x61,
+ DBG_BLOCK_ID_TD04_BY2 = 0x62,
+ DBG_BLOCK_ID_TD06_BY2 = 0x63,
+ DBG_BLOCK_ID_TD08_BY2 = 0x64,
+ DBG_BLOCK_ID_TD0A_BY2 = 0x65,
+ DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
+ DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
+ DBG_BLOCK_ID_TD10_BY2 = 0x68,
+ DBG_BLOCK_ID_TD12_BY2 = 0x69,
+ DBG_BLOCK_ID_TD14_BY2 = 0x6a,
+ DBG_BLOCK_ID_TD16_BY2 = 0x6b,
+ DBG_BLOCK_ID_TD18_BY2 = 0x6c,
+ DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
+ DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
+ DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
+ DBG_BLOCK_ID_MCD0_BY2 = 0x70,
+ DBG_BLOCK_ID_MCD2_BY2 = 0x71,
+ DBG_BLOCK_ID_MCD4_BY2 = 0x72,
+ DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
+} DebugBlockId_BY2;
+typedef enum DebugBlockId_BY4 {
+ DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
+ DBG_BLOCK_ID_CG_BY4 = 0x1,
+ DBG_BLOCK_ID_CSC_BY4 = 0x2,
+ DBG_BLOCK_ID_SQ_BY4 = 0x3,
+ DBG_BLOCK_ID_DMA0_BY4 = 0x4,
+ DBG_BLOCK_ID_SPIS_BY4 = 0x5,
+ DBG_BLOCK_ID_CP0_BY4 = 0x6,
+ DBG_BLOCK_ID_UVDU_BY4 = 0x7,
+ DBG_BLOCK_ID_VGT0_BY4 = 0x8,
+ DBG_BLOCK_ID_SCT0_BY4 = 0x9,
+ DBG_BLOCK_ID_TCAA_BY4 = 0xa,
+ DBG_BLOCK_ID_MCC0_BY4 = 0xb,
+ DBG_BLOCK_ID_SX0_BY4 = 0xc,
+ DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
+ DBG_BLOCK_ID_PC0_BY4 = 0xe,
+ DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
+ DBG_BLOCK_ID_SCB0_BY4 = 0x10,
+ DBG_BLOCK_ID_SCF0_BY4 = 0x11,
+ DBG_BLOCK_ID_BCI0_BY4 = 0x12,
+ DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
+ DBG_BLOCK_ID_CB00_BY4 = 0x14,
+ DBG_BLOCK_ID_CB04_BY4 = 0x15,
+ DBG_BLOCK_ID_CB10_BY4 = 0x16,
+ DBG_BLOCK_ID_CB14_BY4 = 0x17,
+ DBG_BLOCK_ID_TCP0_BY4 = 0x18,
+ DBG_BLOCK_ID_TCP4_BY4 = 0x19,
+ DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
+ DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
+ DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
+ DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
+ DBG_BLOCK_ID_DB_BY4 = 0x20,
+ DBG_BLOCK_ID_DB04_BY4 = 0x21,
+ DBG_BLOCK_ID_DB10_BY4 = 0x22,
+ DBG_BLOCK_ID_DB14_BY4 = 0x23,
+ DBG_BLOCK_ID_TCC0_BY4 = 0x24,
+ DBG_BLOCK_ID_TCC4_BY4 = 0x25,
+ DBG_BLOCK_ID_SPS00_BY4 = 0x26,
+ DBG_BLOCK_ID_SPS11_BY4 = 0x27,
+ DBG_BLOCK_ID_TA00_BY4 = 0x28,
+ DBG_BLOCK_ID_TA04_BY4 = 0x29,
+ DBG_BLOCK_ID_TA08_BY4 = 0x2a,
+ DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
+ DBG_BLOCK_ID_TA10_BY4 = 0x2c,
+ DBG_BLOCK_ID_TA14_BY4 = 0x2d,
+ DBG_BLOCK_ID_TA18_BY4 = 0x2e,
+ DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
+ DBG_BLOCK_ID_TD00_BY4 = 0x30,
+ DBG_BLOCK_ID_TD04_BY4 = 0x31,
+ DBG_BLOCK_ID_TD08_BY4 = 0x32,
+ DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
+ DBG_BLOCK_ID_TD10_BY4 = 0x34,
+ DBG_BLOCK_ID_TD14_BY4 = 0x35,
+ DBG_BLOCK_ID_TD18_BY4 = 0x36,
+ DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
+ DBG_BLOCK_ID_MCD0_BY4 = 0x38,
+ DBG_BLOCK_ID_MCD4_BY4 = 0x39,
+} DebugBlockId_BY4;
+typedef enum DebugBlockId_BY8 {
+ DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
+ DBG_BLOCK_ID_CSC_BY8 = 0x1,
+ DBG_BLOCK_ID_DMA0_BY8 = 0x2,
+ DBG_BLOCK_ID_CP0_BY8 = 0x3,
+ DBG_BLOCK_ID_VGT0_BY8 = 0x4,
+ DBG_BLOCK_ID_TCAA_BY8 = 0x5,
+ DBG_BLOCK_ID_SX0_BY8 = 0x6,
+ DBG_BLOCK_ID_PC0_BY8 = 0x7,
+ DBG_BLOCK_ID_SCB0_BY8 = 0x8,
+ DBG_BLOCK_ID_BCI0_BY8 = 0x9,
+ DBG_BLOCK_ID_CB00_BY8 = 0xa,
+ DBG_BLOCK_ID_CB10_BY8 = 0xb,
+ DBG_BLOCK_ID_TCP0_BY8 = 0xc,
+ DBG_BLOCK_ID_TCP8_BY8 = 0xd,
+ DBG_BLOCK_ID_TCP16_BY8 = 0xe,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
+ DBG_BLOCK_ID_DB00_BY8 = 0x10,
+ DBG_BLOCK_ID_DB10_BY8 = 0x11,
+ DBG_BLOCK_ID_TCC0_BY8 = 0x12,
+ DBG_BLOCK_ID_SPS00_BY8 = 0x13,
+ DBG_BLOCK_ID_TA00_BY8 = 0x14,
+ DBG_BLOCK_ID_TA08_BY8 = 0x15,
+ DBG_BLOCK_ID_TA10_BY8 = 0x16,
+ DBG_BLOCK_ID_TA18_BY8 = 0x17,
+ DBG_BLOCK_ID_TD00_BY8 = 0x18,
+ DBG_BLOCK_ID_TD08_BY8 = 0x19,
+ DBG_BLOCK_ID_TD10_BY8 = 0x1a,
+ DBG_BLOCK_ID_TD18_BY8 = 0x1b,
+ DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
+} DebugBlockId_BY8;
+typedef enum DebugBlockId_BY16 {
+ DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
+ DBG_BLOCK_ID_DMA0_BY16 = 0x1,
+ DBG_BLOCK_ID_VGT0_BY16 = 0x2,
+ DBG_BLOCK_ID_SX0_BY16 = 0x3,
+ DBG_BLOCK_ID_SCB0_BY16 = 0x4,
+ DBG_BLOCK_ID_CB00_BY16 = 0x5,
+ DBG_BLOCK_ID_TCP0_BY16 = 0x6,
+ DBG_BLOCK_ID_TCP16_BY16 = 0x7,
+ DBG_BLOCK_ID_DB00_BY16 = 0x8,
+ DBG_BLOCK_ID_TCC0_BY16 = 0x9,
+ DBG_BLOCK_ID_TA00_BY16 = 0xa,
+ DBG_BLOCK_ID_TA10_BY16 = 0xb,
+ DBG_BLOCK_ID_TD00_BY16 = 0xc,
+ DBG_BLOCK_ID_TD10_BY16 = 0xd,
+ DBG_BLOCK_ID_MCD0_BY16 = 0xe,
+} DebugBlockId_BY16;
+typedef enum ColorTransform {
+ DCC_CT_AUTO = 0x0,
+ DCC_CT_NONE = 0x1,
+ ABGR_TO_A_BG_G_RB = 0x2,
+ BGRA_TO_BG_G_RB_A = 0x3,
+} ColorTransform;
+typedef enum CompareRef {
+ REF_NEVER = 0x0,
+ REF_LESS = 0x1,
+ REF_EQUAL = 0x2,
+ REF_LEQUAL = 0x3,
+ REF_GREATER = 0x4,
+ REF_NOTEQUAL = 0x5,
+ REF_GEQUAL = 0x6,
+ REF_ALWAYS = 0x7,
+} CompareRef;
+typedef enum ReadSize {
+ READ_256_BITS = 0x0,
+ READ_512_BITS = 0x1,
+} ReadSize;
+typedef enum DepthFormat {
+ DEPTH_INVALID = 0x0,
+ DEPTH_16 = 0x1,
+ DEPTH_X8_24 = 0x2,
+ DEPTH_8_24 = 0x3,
+ DEPTH_X8_24_FLOAT = 0x4,
+ DEPTH_8_24_FLOAT = 0x5,
+ DEPTH_32_FLOAT = 0x6,
+ DEPTH_X24_8_32_FLOAT = 0x7,
+} DepthFormat;
+typedef enum ZFormat {
+ Z_INVALID = 0x0,
+ Z_16 = 0x1,
+ Z_24 = 0x2,
+ Z_32_FLOAT = 0x3,
+} ZFormat;
+typedef enum StencilFormat {
+ STENCIL_INVALID = 0x0,
+ STENCIL_8 = 0x1,
+} StencilFormat;
+typedef enum CmaskMode {
+ CMASK_CLEAR_NONE = 0x0,
+ CMASK_CLEAR_ONE = 0x1,
+ CMASK_CLEAR_ALL = 0x2,
+ CMASK_ANY_EXPANDED = 0x3,
+ CMASK_ALPHA0_FRAG1 = 0x4,
+ CMASK_ALPHA0_FRAG2 = 0x5,
+ CMASK_ALPHA0_FRAG4 = 0x6,
+ CMASK_ALPHA0_FRAGS = 0x7,
+ CMASK_ALPHA1_FRAG1 = 0x8,
+ CMASK_ALPHA1_FRAG2 = 0x9,
+ CMASK_ALPHA1_FRAG4 = 0xa,
+ CMASK_ALPHA1_FRAGS = 0xb,
+ CMASK_ALPHAX_FRAG1 = 0xc,
+ CMASK_ALPHAX_FRAG2 = 0xd,
+ CMASK_ALPHAX_FRAG4 = 0xe,
+ CMASK_ALPHAX_FRAGS = 0xf,
+} CmaskMode;
+typedef enum QuadExportFormat {
+ EXPORT_UNUSED = 0x0,
+ EXPORT_32_R = 0x1,
+ EXPORT_32_GR = 0x2,
+ EXPORT_32_AR = 0x3,
+ EXPORT_FP16_ABGR = 0x4,
+ EXPORT_UNSIGNED16_ABGR = 0x5,
+ EXPORT_SIGNED16_ABGR = 0x6,
+ EXPORT_32_ABGR = 0x7,
+} QuadExportFormat;
+typedef enum QuadExportFormatOld {
+ EXPORT_4P_32BPC_ABGR = 0x0,
+ EXPORT_4P_16BPC_ABGR = 0x1,
+ EXPORT_4P_32BPC_GR = 0x2,
+ EXPORT_4P_32BPC_AR = 0x3,
+ EXPORT_2P_32BPC_ABGR = 0x4,
+ EXPORT_8P_32BPC_R = 0x5,
+} QuadExportFormatOld;
+typedef enum ColorFormat {
+ COLOR_INVALID = 0x0,
+ COLOR_8 = 0x1,
+ COLOR_16 = 0x2,
+ COLOR_8_8 = 0x3,
+ COLOR_32 = 0x4,
+ COLOR_16_16 = 0x5,
+ COLOR_10_11_11 = 0x6,
+ COLOR_11_11_10 = 0x7,
+ COLOR_10_10_10_2 = 0x8,
+ COLOR_2_10_10_10 = 0x9,
+ COLOR_8_8_8_8 = 0xa,
+ COLOR_32_32 = 0xb,
+ COLOR_16_16_16_16 = 0xc,
+ COLOR_RESERVED_13 = 0xd,
+ COLOR_32_32_32_32 = 0xe,
+ COLOR_RESERVED_15 = 0xf,
+ COLOR_5_6_5 = 0x10,
+ COLOR_1_5_5_5 = 0x11,
+ COLOR_5_5_5_1 = 0x12,
+ COLOR_4_4_4_4 = 0x13,
+ COLOR_8_24 = 0x14,
+ COLOR_24_8 = 0x15,
+ COLOR_X24_8_32_FLOAT = 0x16,
+ COLOR_RESERVED_23 = 0x17,
+} ColorFormat;
+typedef enum SurfaceFormat {
+ FMT_INVALID = 0x0,
+ FMT_8 = 0x1,
+ FMT_16 = 0x2,
+ FMT_8_8 = 0x3,
+ FMT_32 = 0x4,
+ FMT_16_16 = 0x5,
+ FMT_10_11_11 = 0x6,
+ FMT_11_11_10 = 0x7,
+ FMT_10_10_10_2 = 0x8,
+ FMT_2_10_10_10 = 0x9,
+ FMT_8_8_8_8 = 0xa,
+ FMT_32_32 = 0xb,
+ FMT_16_16_16_16 = 0xc,
+ FMT_32_32_32 = 0xd,
+ FMT_32_32_32_32 = 0xe,
+ FMT_RESERVED_4 = 0xf,
+ FMT_5_6_5 = 0x10,
+ FMT_1_5_5_5 = 0x11,
+ FMT_5_5_5_1 = 0x12,
+ FMT_4_4_4_4 = 0x13,
+ FMT_8_24 = 0x14,
+ FMT_24_8 = 0x15,
+ FMT_X24_8_32_FLOAT = 0x16,
+ FMT_RESERVED_33 = 0x17,
+ FMT_11_11_10_FLOAT = 0x18,
+ FMT_16_FLOAT = 0x19,
+ FMT_32_FLOAT = 0x1a,
+ FMT_16_16_FLOAT = 0x1b,
+ FMT_8_24_FLOAT = 0x1c,
+ FMT_24_8_FLOAT = 0x1d,
+ FMT_32_32_FLOAT = 0x1e,
+ FMT_10_11_11_FLOAT = 0x1f,
+ FMT_16_16_16_16_FLOAT = 0x20,
+ FMT_3_3_2 = 0x21,
+ FMT_6_5_5 = 0x22,
+ FMT_32_32_32_32_FLOAT = 0x23,
+ FMT_RESERVED_36 = 0x24,
+ FMT_1 = 0x25,
+ FMT_1_REVERSED = 0x26,
+ FMT_GB_GR = 0x27,
+ FMT_BG_RG = 0x28,
+ FMT_32_AS_8 = 0x29,
+ FMT_32_AS_8_8 = 0x2a,
+ FMT_5_9_9_9_SHAREDEXP = 0x2b,
+ FMT_8_8_8 = 0x2c,
+ FMT_16_16_16 = 0x2d,
+ FMT_16_16_16_FLOAT = 0x2e,
+ FMT_4_4 = 0x2f,
+ FMT_32_32_32_FLOAT = 0x30,
+ FMT_BC1 = 0x31,
+ FMT_BC2 = 0x32,
+ FMT_BC3 = 0x33,
+ FMT_BC4 = 0x34,
+ FMT_BC5 = 0x35,
+ FMT_BC6 = 0x36,
+ FMT_BC7 = 0x37,
+ FMT_32_AS_32_32_32_32 = 0x38,
+ FMT_APC3 = 0x39,
+ FMT_APC4 = 0x3a,
+ FMT_APC5 = 0x3b,
+ FMT_APC6 = 0x3c,
+ FMT_APC7 = 0x3d,
+ FMT_CTX1 = 0x3e,
+ FMT_RESERVED_63 = 0x3f,
+} SurfaceFormat;
+typedef enum BUF_DATA_FORMAT {
+ BUF_DATA_FORMAT_INVALID = 0x0,
+ BUF_DATA_FORMAT_8 = 0x1,
+ BUF_DATA_FORMAT_16 = 0x2,
+ BUF_DATA_FORMAT_8_8 = 0x3,
+ BUF_DATA_FORMAT_32 = 0x4,
+ BUF_DATA_FORMAT_16_16 = 0x5,
+ BUF_DATA_FORMAT_10_11_11 = 0x6,
+ BUF_DATA_FORMAT_11_11_10 = 0x7,
+ BUF_DATA_FORMAT_10_10_10_2 = 0x8,
+ BUF_DATA_FORMAT_2_10_10_10 = 0x9,
+ BUF_DATA_FORMAT_8_8_8_8 = 0xa,
+ BUF_DATA_FORMAT_32_32 = 0xb,
+ BUF_DATA_FORMAT_16_16_16_16 = 0xc,
+ BUF_DATA_FORMAT_32_32_32 = 0xd,
+ BUF_DATA_FORMAT_32_32_32_32 = 0xe,
+ BUF_DATA_FORMAT_RESERVED_15 = 0xf,
+} BUF_DATA_FORMAT;
+typedef enum IMG_DATA_FORMAT {
+ IMG_DATA_FORMAT_INVALID = 0x0,
+ IMG_DATA_FORMAT_8 = 0x1,
+ IMG_DATA_FORMAT_16 = 0x2,
+ IMG_DATA_FORMAT_8_8 = 0x3,
+ IMG_DATA_FORMAT_32 = 0x4,
+ IMG_DATA_FORMAT_16_16 = 0x5,
+ IMG_DATA_FORMAT_10_11_11 = 0x6,
+ IMG_DATA_FORMAT_11_11_10 = 0x7,
+ IMG_DATA_FORMAT_10_10_10_2 = 0x8,
+ IMG_DATA_FORMAT_2_10_10_10 = 0x9,
+ IMG_DATA_FORMAT_8_8_8_8 = 0xa,
+ IMG_DATA_FORMAT_32_32 = 0xb,
+ IMG_DATA_FORMAT_16_16_16_16 = 0xc,
+ IMG_DATA_FORMAT_32_32_32 = 0xd,
+ IMG_DATA_FORMAT_32_32_32_32 = 0xe,
+ IMG_DATA_FORMAT_RESERVED_15 = 0xf,
+ IMG_DATA_FORMAT_5_6_5 = 0x10,
+ IMG_DATA_FORMAT_1_5_5_5 = 0x11,
+ IMG_DATA_FORMAT_5_5_5_1 = 0x12,
+ IMG_DATA_FORMAT_4_4_4_4 = 0x13,
+ IMG_DATA_FORMAT_8_24 = 0x14,
+ IMG_DATA_FORMAT_24_8 = 0x15,
+ IMG_DATA_FORMAT_X24_8_32 = 0x16,
+ IMG_DATA_FORMAT_RESERVED_23 = 0x17,
+ IMG_DATA_FORMAT_RESERVED_24 = 0x18,
+ IMG_DATA_FORMAT_RESERVED_25 = 0x19,
+ IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
+ IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
+ IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
+ IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
+ IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
+ IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
+ IMG_DATA_FORMAT_GB_GR = 0x20,
+ IMG_DATA_FORMAT_BG_RG = 0x21,
+ IMG_DATA_FORMAT_5_9_9_9 = 0x22,
+ IMG_DATA_FORMAT_BC1 = 0x23,
+ IMG_DATA_FORMAT_BC2 = 0x24,
+ IMG_DATA_FORMAT_BC3 = 0x25,
+ IMG_DATA_FORMAT_BC4 = 0x26,
+ IMG_DATA_FORMAT_BC5 = 0x27,
+ IMG_DATA_FORMAT_BC6 = 0x28,
+ IMG_DATA_FORMAT_BC7 = 0x29,
+ IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
+ IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
+ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
+ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
+ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
+ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
+ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
+ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
+ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
+ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
+ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
+ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
+ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
+ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
+ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
+ IMG_DATA_FORMAT_4_4 = 0x39,
+ IMG_DATA_FORMAT_6_5_5 = 0x3a,
+ IMG_DATA_FORMAT_1 = 0x3b,
+ IMG_DATA_FORMAT_1_REVERSED = 0x3c,
+ IMG_DATA_FORMAT_32_AS_8 = 0x3d,
+ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
+ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
+} IMG_DATA_FORMAT;
+typedef enum BUF_NUM_FORMAT {
+ BUF_NUM_FORMAT_UNORM = 0x0,
+ BUF_NUM_FORMAT_SNORM = 0x1,
+ BUF_NUM_FORMAT_USCALED = 0x2,
+ BUF_NUM_FORMAT_SSCALED = 0x3,
+ BUF_NUM_FORMAT_UINT = 0x4,
+ BUF_NUM_FORMAT_SINT = 0x5,
+ BUF_NUM_FORMAT_RESERVED_6 = 0x6,
+ BUF_NUM_FORMAT_FLOAT = 0x7,
+} BUF_NUM_FORMAT;
+typedef enum IMG_NUM_FORMAT {
+ IMG_NUM_FORMAT_UNORM = 0x0,
+ IMG_NUM_FORMAT_SNORM = 0x1,
+ IMG_NUM_FORMAT_USCALED = 0x2,
+ IMG_NUM_FORMAT_SSCALED = 0x3,
+ IMG_NUM_FORMAT_UINT = 0x4,
+ IMG_NUM_FORMAT_SINT = 0x5,
+ IMG_NUM_FORMAT_RESERVED_6 = 0x6,
+ IMG_NUM_FORMAT_FLOAT = 0x7,
+ IMG_NUM_FORMAT_RESERVED_8 = 0x8,
+ IMG_NUM_FORMAT_SRGB = 0x9,
+ IMG_NUM_FORMAT_RESERVED_10 = 0xa,
+ IMG_NUM_FORMAT_RESERVED_11 = 0xb,
+ IMG_NUM_FORMAT_RESERVED_12 = 0xc,
+ IMG_NUM_FORMAT_RESERVED_13 = 0xd,
+ IMG_NUM_FORMAT_RESERVED_14 = 0xe,
+ IMG_NUM_FORMAT_RESERVED_15 = 0xf,
+} IMG_NUM_FORMAT;
+typedef enum TileType {
+ ARRAY_COLOR_TILE = 0x0,
+ ARRAY_DEPTH_TILE = 0x1,
+} TileType;
+typedef enum NonDispTilingOrder {
+ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
+ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
+} NonDispTilingOrder;
+typedef enum MicroTileMode {
+ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
+ ADDR_SURF_THIN_MICRO_TILING = 0x1,
+ ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
+ ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
+ ADDR_SURF_THICK_MICRO_TILING = 0x4,
+} MicroTileMode;
+typedef enum TileSplit {
+ ADDR_SURF_TILE_SPLIT_64B = 0x0,
+ ADDR_SURF_TILE_SPLIT_128B = 0x1,
+ ADDR_SURF_TILE_SPLIT_256B = 0x2,
+ ADDR_SURF_TILE_SPLIT_512B = 0x3,
+ ADDR_SURF_TILE_SPLIT_1KB = 0x4,
+ ADDR_SURF_TILE_SPLIT_2KB = 0x5,
+ ADDR_SURF_TILE_SPLIT_4KB = 0x6,
+} TileSplit;
+typedef enum SampleSplit {
+ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
+ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
+ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
+ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
+} SampleSplit;
+typedef enum PipeConfig {
+ ADDR_SURF_P2 = 0x0,
+ ADDR_SURF_P2_RESERVED0 = 0x1,
+ ADDR_SURF_P2_RESERVED1 = 0x2,
+ ADDR_SURF_P2_RESERVED2 = 0x3,
+ ADDR_SURF_P4_8x16 = 0x4,
+ ADDR_SURF_P4_16x16 = 0x5,
+ ADDR_SURF_P4_16x32 = 0x6,
+ ADDR_SURF_P4_32x32 = 0x7,
+ ADDR_SURF_P8_16x16_8x16 = 0x8,
+ ADDR_SURF_P8_16x32_8x16 = 0x9,
+ ADDR_SURF_P8_32x32_8x16 = 0xa,
+ ADDR_SURF_P8_16x32_16x16 = 0xb,
+ ADDR_SURF_P8_32x32_16x16 = 0xc,
+ ADDR_SURF_P8_32x32_16x32 = 0xd,
+ ADDR_SURF_P8_32x64_32x32 = 0xe,
+ ADDR_SURF_P8_RESERVED0 = 0xf,
+ ADDR_SURF_P16_32x32_8x16 = 0x10,
+ ADDR_SURF_P16_32x32_16x16 = 0x11,
+} PipeConfig;
+typedef enum NumBanks {
+ ADDR_SURF_2_BANK = 0x0,
+ ADDR_SURF_4_BANK = 0x1,
+ ADDR_SURF_8_BANK = 0x2,
+ ADDR_SURF_16_BANK = 0x3,
+} NumBanks;
+typedef enum BankWidth {
+ ADDR_SURF_BANK_WIDTH_1 = 0x0,
+ ADDR_SURF_BANK_WIDTH_2 = 0x1,
+ ADDR_SURF_BANK_WIDTH_4 = 0x2,
+ ADDR_SURF_BANK_WIDTH_8 = 0x3,
+} BankWidth;
+typedef enum BankHeight {
+ ADDR_SURF_BANK_HEIGHT_1 = 0x0,
+ ADDR_SURF_BANK_HEIGHT_2 = 0x1,
+ ADDR_SURF_BANK_HEIGHT_4 = 0x2,
+ ADDR_SURF_BANK_HEIGHT_8 = 0x3,
+} BankHeight;
+typedef enum BankWidthHeight {
+ ADDR_SURF_BANK_WH_1 = 0x0,
+ ADDR_SURF_BANK_WH_2 = 0x1,
+ ADDR_SURF_BANK_WH_4 = 0x2,
+ ADDR_SURF_BANK_WH_8 = 0x3,
+} BankWidthHeight;
+typedef enum MacroTileAspect {
+ ADDR_SURF_MACRO_ASPECT_1 = 0x0,
+ ADDR_SURF_MACRO_ASPECT_2 = 0x1,
+ ADDR_SURF_MACRO_ASPECT_4 = 0x2,
+ ADDR_SURF_MACRO_ASPECT_8 = 0x3,
+} MacroTileAspect;
+typedef enum GATCL1RequestType {
+ GATCL1_TYPE_NORMAL = 0x0,
+ GATCL1_TYPE_SHOOTDOWN = 0x1,
+ GATCL1_TYPE_BYPASS = 0x2,
+} GATCL1RequestType;
+typedef enum TCC_CACHE_POLICIES {
+ TCC_CACHE_POLICY_LRU = 0x0,
+ TCC_CACHE_POLICY_STREAM = 0x1,
+} TCC_CACHE_POLICIES;
+typedef enum MTYPE {
+ MTYPE_NC_NV = 0x0,
+ MTYPE_NC = 0x1,
+ MTYPE_CC = 0x2,
+ MTYPE_UC = 0x3,
+} MTYPE;
+typedef enum PERFMON_COUNTER_MODE {
+ PERFMON_COUNTER_MODE_ACCUM = 0x0,
+ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
+ PERFMON_COUNTER_MODE_MAX = 0x2,
+ PERFMON_COUNTER_MODE_DIRTY = 0x3,
+ PERFMON_COUNTER_MODE_SAMPLE = 0x4,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
+ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
+ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
+ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
+ PERFMON_COUNTER_MODE_RESERVED = 0xf,
+} PERFMON_COUNTER_MODE;
+typedef enum PERFMON_SPM_MODE {
+ PERFMON_SPM_MODE_OFF = 0x0,
+ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
+ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
+ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
+ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
+ PERFMON_SPM_MODE_RESERVED_5 = 0x5,
+ PERFMON_SPM_MODE_RESERVED_6 = 0x6,
+ PERFMON_SPM_MODE_RESERVED_7 = 0x7,
+ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
+ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
+ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
+} PERFMON_SPM_MODE;
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0x0,
+ ARRAY_TILED = 0x1,
+} SurfaceTiling;
+typedef enum SurfaceArray {
+ ARRAY_1D = 0x0,
+ ARRAY_2D = 0x1,
+ ARRAY_3D = 0x2,
+ ARRAY_3D_SLICE = 0x3,
+} SurfaceArray;
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0x0,
+ ARRAY_2D_COLOR = 0x1,
+ ARRAY_3D_SLICE_COLOR = 0x3,
+} ColorArray;
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0x0,
+ ARRAY_2D_DEPTH = 0x1,
+} DepthArray;
+typedef enum ENUM_NUM_SIMD_PER_CU {
+ NUM_SIMD_PER_CU = 0x4,
+} ENUM_NUM_SIMD_PER_CU;
+
+#endif /* SMU_7_1_1_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h
new file mode 100644
index 000000000000..2c997f7b5d13
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h
@@ -0,0 +1,4864 @@
+/*
+ * SMU_7_1_1 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef SMU_7_1_1_SH_MASK_H
+#define SMU_7_1_1_SH_MASK_H
+
+#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
+#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1
+#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0
+#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2
+#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1
+#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f
+#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1
+#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0
+#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2
+#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1
+#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f
+#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1
+#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0
+#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2
+#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1
+#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f
+#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1
+#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0
+#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2
+#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1
+#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4
+#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2
+#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
+#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3
+#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10
+#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4
+#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20
+#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5
+#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40
+#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6
+#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80
+#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7
+#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100
+#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
+#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200
+#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9
+#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400
+#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa
+#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800
+#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb
+#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000
+#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc
+#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1
+#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2
+#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1
+#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4
+#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4
+#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0
+#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14
+#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000
+#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b
+#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000
+#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17
+#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a
+#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e
+#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff
+#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000
+#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fe00
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9
+#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000
+#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15
+#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17
+#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f
+#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1
+#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2
+#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1
+#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc
+#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2
+#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30
+#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8
+#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200
+#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15
+#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
+#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
+#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
+#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
+#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
+#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2
+#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1
+#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4
+#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2
+#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8
+#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3
+#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10
+#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4
+#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00
+#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa
+#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000
+#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc
+#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000
+#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c
+#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000
+#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d
+#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1
+#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0
+#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0
+#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4
+#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff
+#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0
+#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00
+#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8
+#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2
+#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1
+#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4
+#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2
+#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1
+#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0
+#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8
+#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3
+#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100
+#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8
+#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000
+#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe
+#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000
+#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf
+#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000
+#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10
+#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000
+#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11
+#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000
+#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12
+#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000
+#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13
+#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000
+#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14
+#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000
+#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15
+#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000
+#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16
+#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000
+#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18
+#define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1
+#define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0
+#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6
+#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1
+#define CG_CLKPIN_CNTL_DC__XTL_XOCLK_DRV_R_EN_MASK 0x200
+#define CG_CLKPIN_CNTL_DC__XTL_XOCLK_DRV_R_EN__SHIFT 0x9
+#define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00
+#define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa
+#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff
+#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0
+#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00
+#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8
+#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000
+#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10
+#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff
+#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0
+#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00
+#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8
+#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000
+#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10
+#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f
+#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
+#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0
+#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5
+#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00
+#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa
+#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000
+#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11
+#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000
+#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12
+#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000
+#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3
+#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0
+#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9
+#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b
+#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8_MASK 0x100
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8__SHIFT 0x8
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9_MASK 0x200
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9__SHIFT 0x9
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10_MASK 0x400
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10__SHIFT 0xa
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11_MASK 0x800
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11__SHIFT 0xb
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12_MASK 0x1000
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12__SHIFT 0xc
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13_MASK 0x2000
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13__SHIFT 0xd
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14_MASK 0x4000
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14__SHIFT 0xe
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15_MASK 0x8000
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15__SHIFT 0xf
+#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_0__SMC_RESP_MASK 0xffff
+#define SMC_RESP_0__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_1__SMC_RESP_MASK 0xffff
+#define SMC_RESP_1__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_2__SMC_RESP_MASK 0xffff
+#define SMC_RESP_2__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_3__SMC_RESP_MASK 0xffff
+#define SMC_RESP_3__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_4__SMC_RESP_MASK 0xffff
+#define SMC_RESP_4__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_5__SMC_RESP_MASK 0xffff
+#define SMC_RESP_5__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_6__SMC_RESP_MASK 0xffff
+#define SMC_RESP_6__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_7__SMC_RESP_MASK 0xffff
+#define SMC_RESP_7__SMC_RESP__SHIFT 0x0
+#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_8__SMC_RESP_MASK 0xffff
+#define SMC_RESP_8__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_9__SMC_RESP_MASK 0xffff
+#define SMC_RESP_9__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_10__SMC_RESP_MASK 0xffff
+#define SMC_RESP_10__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_11__SMC_RESP_MASK 0xffff
+#define SMC_RESP_11__SMC_RESP__SHIFT 0x0
+#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1
+#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0
+#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2
+#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1
+#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000
+#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e
+#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1
+#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8
+#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000
+#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18
+#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1
+#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0
+#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff
+#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0
+#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff
+#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0
+#define SMC_PC_C__smc_pc_c_MASK 0xffffffff
+#define SMC_PC_C__smc_pc_c__SHIFT 0x0
+#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff
+#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0
+#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1
+#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0
+#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf
+#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0
+#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0
+#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4
+#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff
+#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0
+#define GPIOPAD_A__GPIO_A_MASK 0x7fffffff
+#define GPIOPAD_A__GPIO_A__SHIFT 0x0
+#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff
+#define GPIOPAD_EN__GPIO_EN__SHIFT 0x0
+#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff
+#define GPIOPAD_Y__GPIO_Y__SHIFT 0x0
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e
+#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff
+#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0
+#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000
+#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f
+#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff
+#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0
+#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000
+#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c
+#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000
+#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f
+#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff
+#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0
+#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000
+#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f
+#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff
+#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0
+#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000
+#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f
+#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff
+#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0
+#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000
+#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6
+#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff
+#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0
+#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff
+#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0
+#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff
+#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0
+#define CG_FPS_CNT__FPS_CNT_MASK 0xffffffff
+#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0
+#define SMU_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0
+#define SMU_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0
+#define SMU_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0
+#define SMU_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0
+#define SMU_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0
+#define SMU_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0
+#define SMU_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0
+#define SMU_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0
+#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1
+#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0
+#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2
+#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1
+#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4
+#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2
+#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8
+#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3
+#define RCU_UC_EVENTS__TP_Tester_MASK 0x40
+#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6
+#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80
+#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7
+#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100
+#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8
+#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200
+#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9
+#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400
+#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa
+#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800
+#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb
+#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000
+#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd
+#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000
+#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10
+#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000
+#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11
+#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000
+#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12
+#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000
+#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13
+#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000
+#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18
+#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2
+#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1
+#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8
+#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3
+#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10
+#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4
+#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20
+#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5
+#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100
+#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8
+#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000
+#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10
+#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000
+#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11
+#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000
+#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16
+#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000
+#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17
+#define CC_RCU_FUSES__GPU_DIS_MASK 0x2
+#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1
+#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4
+#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2
+#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10
+#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4
+#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20
+#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5
+#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40
+#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6
+#define CC_RCU_FUSES__ROM_DIS_MASK 0x80
+#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7
+#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100
+#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8
+#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200
+#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9
+#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400
+#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa
+#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x4000
+#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xe
+#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x8000
+#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0xf
+#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x10000
+#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x10
+#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x20000
+#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x11
+#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x40000
+#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x12
+#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x80000
+#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x13
+#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x200000
+#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x15
+#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x400000
+#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x16
+#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x800000
+#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x17
+#define CC_RCU_FUSES__WRP_FUSE_VALID_MASK 0x1000000
+#define CC_RCU_FUSES__WRP_FUSE_VALID__SHIFT 0x18
+#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x2000000
+#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0x19
+#define CC_RCU_FUSES__RCU_SPARE_MASK 0xfc000000
+#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x1a
+#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2
+#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1
+#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc
+#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2
+#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600
+#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9
+#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800
+#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17
+#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000
+#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b
+#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000
+#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c
+#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000
+#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d
+#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff
+#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0
+#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00
+#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8
+#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000
+#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10
+#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000
+#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18
+#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe
+#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1
+#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e
+#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1
+#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e
+#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1
+#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40
+#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6
+#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80
+#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7
+#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100
+#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8
+#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200
+#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9
+#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400
+#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa
+#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800
+#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd
+#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000
+#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18
+#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000
+#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19
+#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000
+#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a
+#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0
+#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4
+#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000
+#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14
+#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000
+#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18
+#define CC_TST_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000
+#define CC_TST_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c
+#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2
+#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1
+#define CC_HARVEST_FUSES__VCE_DISABLE_MASK 0x6
+#define CC_HARVEST_FUSES__VCE_DISABLE__SHIFT 0x1
+#define CC_HARVEST_FUSES__UVD_DISABLE_MASK 0x10
+#define CC_HARVEST_FUSES__UVD_DISABLE__SHIFT 0x4
+#define CC_HARVEST_FUSES__ACP_EXISTS_MASK 0x40
+#define CC_HARVEST_FUSES__ACP_EXISTS__SHIFT 0x6
+#define CC_HARVEST_FUSES__DC_DISABLE_MASK 0x3f00
+#define CC_HARVEST_FUSES__DC_DISABLE__SHIFT 0x8
+#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff
+#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0
+#define SMU_STATUS__SMU_DONE_MASK 0x1
+#define SMU_STATUS__SMU_DONE__SHIFT 0x0
+#define SMU_STATUS__SMU_PASS_MASK 0x2
+#define SMU_STATUS__SMU_PASS__SHIFT 0x1
+#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1
+#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0
+#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6
+#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1
+#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8
+#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3
+#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10
+#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4
+#define SMU_FIRMWARE__SMU_counter_MASK 0xf00
+#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8
+#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000
+#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10
+#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000
+#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11
+#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff
+#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0
+#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000
+#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f
+#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff
+#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime__SHIFT 0x18
+#define MC_REGISTERS_TABLE_1__reserved_2_MASK 0xff
+#define MC_REGISTERS_TABLE_1__reserved_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_1__reserved_1_MASK 0xff00
+#define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8
+#define MC_REGISTERS_TABLE_1__reserved_0_MASK 0xff0000
+#define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_1__last_MASK 0xff000000
+#define MC_REGISTERS_TABLE_1__last__SHIFT 0x18
+#define MC_REGISTERS_TABLE_2__address_0_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_2__address_0_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_2__address_0_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_3__address_1_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_3__address_1_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_3__address_1_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_4__address_2_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_4__address_2_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_4__address_2_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_4__address_2_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_5__address_3_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_5__address_3_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_5__address_3_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_6__address_4_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_6__address_4_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_6__address_4_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_7__address_5_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_7__address_5_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_7__address_5_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_8__address_6_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_8__address_6_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_8__address_6_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_8__address_6_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_9__address_7_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_9__address_7_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_9__address_7_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_10__address_8_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_10__address_8_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_10__address_8_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_11__address_9_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_11__address_9_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_11__address_9_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_12__address_10_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_12__address_10_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_12__address_10_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_12__address_10_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_13__address_11_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_13__address_11_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_13__address_11_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_13__address_11_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_14__address_12_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_14__address_12_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_14__address_12_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_15__address_13_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_15__address_13_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_15__address_13_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_15__address_13_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_16__address_14_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_16__address_14_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_16__address_14_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_17__address_15_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_17__address_15_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_17__address_15_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_18__data_0_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_18__data_0_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_19__data_0_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_20__data_0_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_20__data_0_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_21__data_0_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_22__data_0_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_22__data_0_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_23__data_0_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_23__data_0_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_24__data_0_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_24__data_0_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_25__data_0_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_25__data_0_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_26__data_0_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_26__data_0_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_27__data_0_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_27__data_0_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_28__data_0_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_29__data_0_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_29__data_0_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_30__data_0_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_30__data_0_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_31__data_0_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_31__data_0_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_32__data_0_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_33__data_0_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0
+#define MC_REGISTERS_TABLE_34__data_1_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_34__data_1_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_35__data_1_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_35__data_1_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_36__data_1_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_36__data_1_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_37__data_1_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_37__data_1_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_38__data_1_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_38__data_1_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_39__data_1_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_39__data_1_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_40__data_1_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_41__data_1_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_41__data_1_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_42__data_1_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_42__data_1_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_43__data_1_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_44__data_1_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_44__data_1_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_45__data_1_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_45__data_1_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_46__data_1_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_47__data_1_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_47__data_1_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_48__data_1_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_48__data_1_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_49__data_1_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_49__data_1_value_15__SHIFT 0x0
+#define MC_REGISTERS_TABLE_50__data_2_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_50__data_2_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_51__data_2_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_51__data_2_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_52__data_2_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_52__data_2_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_53__data_2_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_53__data_2_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_54__data_2_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_54__data_2_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_55__data_2_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_55__data_2_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_56__data_2_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_56__data_2_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_57__data_2_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_57__data_2_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_58__data_2_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_58__data_2_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_59__data_2_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_59__data_2_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_60__data_2_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_61__data_2_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_62__data_2_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_63__data_2_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_63__data_2_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_64__data_2_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_64__data_2_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_65__data_2_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_65__data_2_value_15__SHIFT 0x0
+#define MC_REGISTERS_TABLE_66__data_3_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_67__data_3_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_67__data_3_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_68__data_3_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_68__data_3_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_69__data_3_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_69__data_3_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_70__data_3_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_70__data_3_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_71__data_3_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_72__data_3_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_73__data_3_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_73__data_3_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_74__data_3_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_74__data_3_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_75__data_3_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_75__data_3_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_76__data_3_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_77__data_3_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_77__data_3_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_78__data_3_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_78__data_3_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_79__data_3_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_79__data_3_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_80__data_3_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_80__data_3_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_81__data_3_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_81__data_3_value_15__SHIFT 0x0
+#define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff
+#define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0
+#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff
+#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0
+#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff
+#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0
+#define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff
+#define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0
+#define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff
+#define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0
+#define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff
+#define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0
+#define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff
+#define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0
+#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff
+#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0
+#define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff
+#define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0
+#define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff
+#define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0
+#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff
+#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0
+#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff
+#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0
+#define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff
+#define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0
+#define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff
+#define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0
+#define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff
+#define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0
+#define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff
+#define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0
+#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff
+#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0
+#define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff
+#define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0
+#define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff
+#define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0
+#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff
+#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0
+#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff
+#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0
+#define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff
+#define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0
+#define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff
+#define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0
+#define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff
+#define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0
+#define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff
+#define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0
+#define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff
+#define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0
+#define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff
+#define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0
+#define DPM_TABLE_28__SystemFlags_MASK 0xffffffff
+#define DPM_TABLE_28__SystemFlags__SHIFT 0x0
+#define DPM_TABLE_29__SmioMaskVddcVid_MASK 0xffffffff
+#define DPM_TABLE_29__SmioMaskVddcVid__SHIFT 0x0
+#define DPM_TABLE_30__SmioMaskVddcPhase_MASK 0xffffffff
+#define DPM_TABLE_30__SmioMaskVddcPhase__SHIFT 0x0
+#define DPM_TABLE_31__SmioMaskVddciVid_MASK 0xffffffff
+#define DPM_TABLE_31__SmioMaskVddciVid__SHIFT 0x0
+#define DPM_TABLE_32__SmioMaskMvddVid_MASK 0xffffffff
+#define DPM_TABLE_32__SmioMaskMvddVid__SHIFT 0x0
+#define DPM_TABLE_33__VddcLevelCount_MASK 0xffffffff
+#define DPM_TABLE_33__VddcLevelCount__SHIFT 0x0
+#define DPM_TABLE_34__VddciLevelCount_MASK 0xffffffff
+#define DPM_TABLE_34__VddciLevelCount__SHIFT 0x0
+#define DPM_TABLE_35__MvddLevelCount_MASK 0xffffffff
+#define DPM_TABLE_35__MvddLevelCount__SHIFT 0x0
+#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_36__VddcLevel_0_Voltage_MASK 0xffff0000
+#define DPM_TABLE_36__VddcLevel_0_Voltage__SHIFT 0x10
+#define DPM_TABLE_37__VddcLevel_0_padding_MASK 0xff
+#define DPM_TABLE_37__VddcLevel_0_padding__SHIFT 0x0
+#define DPM_TABLE_37__VddcLevel_0_Smio_MASK 0xff00
+#define DPM_TABLE_37__VddcLevel_0_Smio__SHIFT 0x8
+#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_38__VddcLevel_1_Voltage_MASK 0xffff0000
+#define DPM_TABLE_38__VddcLevel_1_Voltage__SHIFT 0x10
+#define DPM_TABLE_39__VddcLevel_1_padding_MASK 0xff
+#define DPM_TABLE_39__VddcLevel_1_padding__SHIFT 0x0
+#define DPM_TABLE_39__VddcLevel_1_Smio_MASK 0xff00
+#define DPM_TABLE_39__VddcLevel_1_Smio__SHIFT 0x8
+#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_40__VddcLevel_2_Voltage_MASK 0xffff0000
+#define DPM_TABLE_40__VddcLevel_2_Voltage__SHIFT 0x10
+#define DPM_TABLE_41__VddcLevel_2_padding_MASK 0xff
+#define DPM_TABLE_41__VddcLevel_2_padding__SHIFT 0x0
+#define DPM_TABLE_41__VddcLevel_2_Smio_MASK 0xff00
+#define DPM_TABLE_41__VddcLevel_2_Smio__SHIFT 0x8
+#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_42__VddcLevel_3_Voltage_MASK 0xffff0000
+#define DPM_TABLE_42__VddcLevel_3_Voltage__SHIFT 0x10
+#define DPM_TABLE_43__VddcLevel_3_padding_MASK 0xff
+#define DPM_TABLE_43__VddcLevel_3_padding__SHIFT 0x0
+#define DPM_TABLE_43__VddcLevel_3_Smio_MASK 0xff00
+#define DPM_TABLE_43__VddcLevel_3_Smio__SHIFT 0x8
+#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_44__VddcLevel_4_Voltage_MASK 0xffff0000
+#define DPM_TABLE_44__VddcLevel_4_Voltage__SHIFT 0x10
+#define DPM_TABLE_45__VddcLevel_4_padding_MASK 0xff
+#define DPM_TABLE_45__VddcLevel_4_padding__SHIFT 0x0
+#define DPM_TABLE_45__VddcLevel_4_Smio_MASK 0xff00
+#define DPM_TABLE_45__VddcLevel_4_Smio__SHIFT 0x8
+#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_46__VddcLevel_5_Voltage_MASK 0xffff0000
+#define DPM_TABLE_46__VddcLevel_5_Voltage__SHIFT 0x10
+#define DPM_TABLE_47__VddcLevel_5_padding_MASK 0xff
+#define DPM_TABLE_47__VddcLevel_5_padding__SHIFT 0x0
+#define DPM_TABLE_47__VddcLevel_5_Smio_MASK 0xff00
+#define DPM_TABLE_47__VddcLevel_5_Smio__SHIFT 0x8
+#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_48__VddcLevel_6_Voltage_MASK 0xffff0000
+#define DPM_TABLE_48__VddcLevel_6_Voltage__SHIFT 0x10
+#define DPM_TABLE_49__VddcLevel_6_padding_MASK 0xff
+#define DPM_TABLE_49__VddcLevel_6_padding__SHIFT 0x0
+#define DPM_TABLE_49__VddcLevel_6_Smio_MASK 0xff00
+#define DPM_TABLE_49__VddcLevel_6_Smio__SHIFT 0x8
+#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_50__VddcLevel_7_Voltage_MASK 0xffff0000
+#define DPM_TABLE_50__VddcLevel_7_Voltage__SHIFT 0x10
+#define DPM_TABLE_51__VddcLevel_7_padding_MASK 0xff
+#define DPM_TABLE_51__VddcLevel_7_padding__SHIFT 0x0
+#define DPM_TABLE_51__VddcLevel_7_Smio_MASK 0xff00
+#define DPM_TABLE_51__VddcLevel_7_Smio__SHIFT 0x8
+#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_52__VddciLevel_0_Voltage_MASK 0xffff0000
+#define DPM_TABLE_52__VddciLevel_0_Voltage__SHIFT 0x10
+#define DPM_TABLE_53__VddciLevel_0_padding_MASK 0xff
+#define DPM_TABLE_53__VddciLevel_0_padding__SHIFT 0x0
+#define DPM_TABLE_53__VddciLevel_0_Smio_MASK 0xff00
+#define DPM_TABLE_53__VddciLevel_0_Smio__SHIFT 0x8
+#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_54__VddciLevel_1_Voltage_MASK 0xffff0000
+#define DPM_TABLE_54__VddciLevel_1_Voltage__SHIFT 0x10
+#define DPM_TABLE_55__VddciLevel_1_padding_MASK 0xff
+#define DPM_TABLE_55__VddciLevel_1_padding__SHIFT 0x0
+#define DPM_TABLE_55__VddciLevel_1_Smio_MASK 0xff00
+#define DPM_TABLE_55__VddciLevel_1_Smio__SHIFT 0x8
+#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_56__VddciLevel_2_Voltage_MASK 0xffff0000
+#define DPM_TABLE_56__VddciLevel_2_Voltage__SHIFT 0x10
+#define DPM_TABLE_57__VddciLevel_2_padding_MASK 0xff
+#define DPM_TABLE_57__VddciLevel_2_padding__SHIFT 0x0
+#define DPM_TABLE_57__VddciLevel_2_Smio_MASK 0xff00
+#define DPM_TABLE_57__VddciLevel_2_Smio__SHIFT 0x8
+#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_58__VddciLevel_3_Voltage_MASK 0xffff0000
+#define DPM_TABLE_58__VddciLevel_3_Voltage__SHIFT 0x10
+#define DPM_TABLE_59__VddciLevel_3_padding_MASK 0xff
+#define DPM_TABLE_59__VddciLevel_3_padding__SHIFT 0x0
+#define DPM_TABLE_59__VddciLevel_3_Smio_MASK 0xff00
+#define DPM_TABLE_59__VddciLevel_3_Smio__SHIFT 0x8
+#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_60__MvddLevel_0_Voltage_MASK 0xffff0000
+#define DPM_TABLE_60__MvddLevel_0_Voltage__SHIFT 0x10
+#define DPM_TABLE_61__MvddLevel_0_padding_MASK 0xff
+#define DPM_TABLE_61__MvddLevel_0_padding__SHIFT 0x0
+#define DPM_TABLE_61__MvddLevel_0_Smio_MASK 0xff00
+#define DPM_TABLE_61__MvddLevel_0_Smio__SHIFT 0x8
+#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_62__MvddLevel_1_Voltage_MASK 0xffff0000
+#define DPM_TABLE_62__MvddLevel_1_Voltage__SHIFT 0x10
+#define DPM_TABLE_63__MvddLevel_1_padding_MASK 0xff
+#define DPM_TABLE_63__MvddLevel_1_padding__SHIFT 0x0
+#define DPM_TABLE_63__MvddLevel_1_Smio_MASK 0xff00
+#define DPM_TABLE_63__MvddLevel_1_Smio__SHIFT 0x8
+#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_64__MvddLevel_2_Voltage_MASK 0xffff0000
+#define DPM_TABLE_64__MvddLevel_2_Voltage__SHIFT 0x10
+#define DPM_TABLE_65__MvddLevel_2_padding_MASK 0xff
+#define DPM_TABLE_65__MvddLevel_2_padding__SHIFT 0x0
+#define DPM_TABLE_65__MvddLevel_2_Smio_MASK 0xff00
+#define DPM_TABLE_65__MvddLevel_2_Smio__SHIFT 0x8
+#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd_MASK 0xffff
+#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd__SHIFT 0x0
+#define DPM_TABLE_66__MvddLevel_3_Voltage_MASK 0xffff0000
+#define DPM_TABLE_66__MvddLevel_3_Voltage__SHIFT 0x10
+#define DPM_TABLE_67__MvddLevel_3_padding_MASK 0xff
+#define DPM_TABLE_67__MvddLevel_3_padding__SHIFT 0x0
+#define DPM_TABLE_67__MvddLevel_3_Smio_MASK 0xff00
+#define DPM_TABLE_67__MvddLevel_3_Smio__SHIFT 0x8
+#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd_MASK 0xffff0000
+#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd__SHIFT 0x10
+#define DPM_TABLE_68__MasterDeepSleepControl_MASK 0xff
+#define DPM_TABLE_68__MasterDeepSleepControl__SHIFT 0x0
+#define DPM_TABLE_68__LinkLevelCount_MASK 0xff00
+#define DPM_TABLE_68__LinkLevelCount__SHIFT 0x8
+#define DPM_TABLE_68__MemoryDpmLevelCount_MASK 0xff0000
+#define DPM_TABLE_68__MemoryDpmLevelCount__SHIFT 0x10
+#define DPM_TABLE_68__GraphicsDpmLevelCount_MASK 0xff000000
+#define DPM_TABLE_68__GraphicsDpmLevelCount__SHIFT 0x18
+#define DPM_TABLE_69__Reserved_0_MASK 0xffffffff
+#define DPM_TABLE_69__Reserved_0__SHIFT 0x0
+#define DPM_TABLE_70__Reserved_1_MASK 0xffffffff
+#define DPM_TABLE_70__Reserved_1__SHIFT 0x0
+#define DPM_TABLE_71__Reserved_2_MASK 0xffffffff
+#define DPM_TABLE_71__Reserved_2__SHIFT 0x0
+#define DPM_TABLE_72__Reserved_3_MASK 0xffffffff
+#define DPM_TABLE_72__Reserved_3__SHIFT 0x0
+#define DPM_TABLE_73__Reserved_4_MASK 0xffffffff
+#define DPM_TABLE_73__Reserved_4__SHIFT 0x0
+#define DPM_TABLE_74__GraphicsLevel_0_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_74__GraphicsLevel_0_MinVddc__SHIFT 0x0
+#define DPM_TABLE_75__GraphicsLevel_0_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_75__GraphicsLevel_0_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_76__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_76__GraphicsLevel_0_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_77__GraphicsLevel_0_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_77__GraphicsLevel_0_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_77__GraphicsLevel_0_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_77__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_77__GraphicsLevel_0_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_77__GraphicsLevel_0_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_78__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_78__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_79__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_79__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_80__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_80__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_81__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_81__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_82__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_82__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_83__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_83__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_84__GraphicsLevel_0_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_84__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_84__GraphicsLevel_0_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_84__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_84__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_84__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_84__GraphicsLevel_0_SclkDid_MASK 0xff000000
+#define DPM_TABLE_84__GraphicsLevel_0_SclkDid__SHIFT 0x18
+#define DPM_TABLE_85__GraphicsLevel_0_PowerThrottle_MASK 0xff
+#define DPM_TABLE_85__GraphicsLevel_0_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_85__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_85__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_85__GraphicsLevel_0_DownHyst_MASK 0xff0000
+#define DPM_TABLE_85__GraphicsLevel_0_DownHyst__SHIFT 0x10
+#define DPM_TABLE_85__GraphicsLevel_0_UpHyst_MASK 0xff000000
+#define DPM_TABLE_85__GraphicsLevel_0_UpHyst__SHIFT 0x18
+#define DPM_TABLE_86__GraphicsLevel_1_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_86__GraphicsLevel_1_MinVddc__SHIFT 0x0
+#define DPM_TABLE_87__GraphicsLevel_1_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_87__GraphicsLevel_1_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_88__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_88__GraphicsLevel_1_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_89__GraphicsLevel_1_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_89__GraphicsLevel_1_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_89__GraphicsLevel_1_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_89__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_89__GraphicsLevel_1_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_89__GraphicsLevel_1_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_90__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_90__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_91__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_91__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_92__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_92__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_93__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_93__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_94__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_94__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_95__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_95__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_96__GraphicsLevel_1_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_96__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_96__GraphicsLevel_1_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_96__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_96__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_96__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_96__GraphicsLevel_1_SclkDid_MASK 0xff000000
+#define DPM_TABLE_96__GraphicsLevel_1_SclkDid__SHIFT 0x18
+#define DPM_TABLE_97__GraphicsLevel_1_PowerThrottle_MASK 0xff
+#define DPM_TABLE_97__GraphicsLevel_1_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_97__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_97__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_97__GraphicsLevel_1_DownHyst_MASK 0xff0000
+#define DPM_TABLE_97__GraphicsLevel_1_DownHyst__SHIFT 0x10
+#define DPM_TABLE_97__GraphicsLevel_1_UpHyst_MASK 0xff000000
+#define DPM_TABLE_97__GraphicsLevel_1_UpHyst__SHIFT 0x18
+#define DPM_TABLE_98__GraphicsLevel_2_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_98__GraphicsLevel_2_MinVddc__SHIFT 0x0
+#define DPM_TABLE_99__GraphicsLevel_2_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_99__GraphicsLevel_2_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_100__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_100__GraphicsLevel_2_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_101__GraphicsLevel_2_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_101__GraphicsLevel_2_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_101__GraphicsLevel_2_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_101__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_101__GraphicsLevel_2_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_101__GraphicsLevel_2_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_102__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_102__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_103__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_103__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_104__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_104__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_105__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_105__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_106__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_106__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_107__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_107__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_108__GraphicsLevel_2_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_108__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_108__GraphicsLevel_2_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_108__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_108__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_108__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_108__GraphicsLevel_2_SclkDid_MASK 0xff000000
+#define DPM_TABLE_108__GraphicsLevel_2_SclkDid__SHIFT 0x18
+#define DPM_TABLE_109__GraphicsLevel_2_PowerThrottle_MASK 0xff
+#define DPM_TABLE_109__GraphicsLevel_2_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_109__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_109__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_109__GraphicsLevel_2_DownHyst_MASK 0xff0000
+#define DPM_TABLE_109__GraphicsLevel_2_DownHyst__SHIFT 0x10
+#define DPM_TABLE_109__GraphicsLevel_2_UpHyst_MASK 0xff000000
+#define DPM_TABLE_109__GraphicsLevel_2_UpHyst__SHIFT 0x18
+#define DPM_TABLE_110__GraphicsLevel_3_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_110__GraphicsLevel_3_MinVddc__SHIFT 0x0
+#define DPM_TABLE_111__GraphicsLevel_3_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_111__GraphicsLevel_3_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_112__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_112__GraphicsLevel_3_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_113__GraphicsLevel_3_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_113__GraphicsLevel_3_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_113__GraphicsLevel_3_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_113__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_113__GraphicsLevel_3_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_113__GraphicsLevel_3_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_114__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_114__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_115__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_115__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_116__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_116__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_117__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_117__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_118__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_118__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_119__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_119__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_120__GraphicsLevel_3_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_120__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_120__GraphicsLevel_3_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_120__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_120__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_120__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_120__GraphicsLevel_3_SclkDid_MASK 0xff000000
+#define DPM_TABLE_120__GraphicsLevel_3_SclkDid__SHIFT 0x18
+#define DPM_TABLE_121__GraphicsLevel_3_PowerThrottle_MASK 0xff
+#define DPM_TABLE_121__GraphicsLevel_3_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_121__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_121__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_121__GraphicsLevel_3_DownHyst_MASK 0xff0000
+#define DPM_TABLE_121__GraphicsLevel_3_DownHyst__SHIFT 0x10
+#define DPM_TABLE_121__GraphicsLevel_3_UpHyst_MASK 0xff000000
+#define DPM_TABLE_121__GraphicsLevel_3_UpHyst__SHIFT 0x18
+#define DPM_TABLE_122__GraphicsLevel_4_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_122__GraphicsLevel_4_MinVddc__SHIFT 0x0
+#define DPM_TABLE_123__GraphicsLevel_4_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_123__GraphicsLevel_4_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_124__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_124__GraphicsLevel_4_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_125__GraphicsLevel_4_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_125__GraphicsLevel_4_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_125__GraphicsLevel_4_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_125__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_125__GraphicsLevel_4_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_125__GraphicsLevel_4_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_126__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_126__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_127__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_127__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_128__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_128__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_129__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_129__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_130__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_130__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_131__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_131__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_132__GraphicsLevel_4_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_132__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_132__GraphicsLevel_4_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_132__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_132__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_132__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_132__GraphicsLevel_4_SclkDid_MASK 0xff000000
+#define DPM_TABLE_132__GraphicsLevel_4_SclkDid__SHIFT 0x18
+#define DPM_TABLE_133__GraphicsLevel_4_PowerThrottle_MASK 0xff
+#define DPM_TABLE_133__GraphicsLevel_4_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_133__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_133__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_133__GraphicsLevel_4_DownHyst_MASK 0xff0000
+#define DPM_TABLE_133__GraphicsLevel_4_DownHyst__SHIFT 0x10
+#define DPM_TABLE_133__GraphicsLevel_4_UpHyst_MASK 0xff000000
+#define DPM_TABLE_133__GraphicsLevel_4_UpHyst__SHIFT 0x18
+#define DPM_TABLE_134__GraphicsLevel_5_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_134__GraphicsLevel_5_MinVddc__SHIFT 0x0
+#define DPM_TABLE_135__GraphicsLevel_5_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_135__GraphicsLevel_5_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_136__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_136__GraphicsLevel_5_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_137__GraphicsLevel_5_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_137__GraphicsLevel_5_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_137__GraphicsLevel_5_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_137__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_137__GraphicsLevel_5_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_137__GraphicsLevel_5_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_138__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_138__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_139__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_139__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_140__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_140__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_141__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_141__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_142__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_142__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_143__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_143__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_144__GraphicsLevel_5_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_144__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_144__GraphicsLevel_5_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_144__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_144__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_144__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_144__GraphicsLevel_5_SclkDid_MASK 0xff000000
+#define DPM_TABLE_144__GraphicsLevel_5_SclkDid__SHIFT 0x18
+#define DPM_TABLE_145__GraphicsLevel_5_PowerThrottle_MASK 0xff
+#define DPM_TABLE_145__GraphicsLevel_5_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_145__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_145__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_145__GraphicsLevel_5_DownHyst_MASK 0xff0000
+#define DPM_TABLE_145__GraphicsLevel_5_DownHyst__SHIFT 0x10
+#define DPM_TABLE_145__GraphicsLevel_5_UpHyst_MASK 0xff000000
+#define DPM_TABLE_145__GraphicsLevel_5_UpHyst__SHIFT 0x18
+#define DPM_TABLE_146__GraphicsLevel_6_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_146__GraphicsLevel_6_MinVddc__SHIFT 0x0
+#define DPM_TABLE_147__GraphicsLevel_6_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_147__GraphicsLevel_6_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_148__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_148__GraphicsLevel_6_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_149__GraphicsLevel_6_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_149__GraphicsLevel_6_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_149__GraphicsLevel_6_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_149__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_149__GraphicsLevel_6_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_149__GraphicsLevel_6_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_150__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_150__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_151__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_151__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_152__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_152__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_153__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_153__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_154__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_154__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_155__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_155__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_156__GraphicsLevel_6_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_156__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_156__GraphicsLevel_6_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_156__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_156__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_156__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_156__GraphicsLevel_6_SclkDid_MASK 0xff000000
+#define DPM_TABLE_156__GraphicsLevel_6_SclkDid__SHIFT 0x18
+#define DPM_TABLE_157__GraphicsLevel_6_PowerThrottle_MASK 0xff
+#define DPM_TABLE_157__GraphicsLevel_6_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_157__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_157__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_157__GraphicsLevel_6_DownHyst_MASK 0xff0000
+#define DPM_TABLE_157__GraphicsLevel_6_DownHyst__SHIFT 0x10
+#define DPM_TABLE_157__GraphicsLevel_6_UpHyst_MASK 0xff000000
+#define DPM_TABLE_157__GraphicsLevel_6_UpHyst__SHIFT 0x18
+#define DPM_TABLE_158__GraphicsLevel_7_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_158__GraphicsLevel_7_MinVddc__SHIFT 0x0
+#define DPM_TABLE_159__GraphicsLevel_7_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_159__GraphicsLevel_7_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_160__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_160__GraphicsLevel_7_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_161__GraphicsLevel_7_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_161__GraphicsLevel_7_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_161__GraphicsLevel_7_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_161__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_161__GraphicsLevel_7_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_161__GraphicsLevel_7_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_162__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_162__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_163__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_163__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_164__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_164__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_165__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_165__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_166__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_166__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_167__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_167__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_168__GraphicsLevel_7_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_168__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_168__GraphicsLevel_7_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_168__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_168__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_168__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_168__GraphicsLevel_7_SclkDid_MASK 0xff000000
+#define DPM_TABLE_168__GraphicsLevel_7_SclkDid__SHIFT 0x18
+#define DPM_TABLE_169__GraphicsLevel_7_PowerThrottle_MASK 0xff
+#define DPM_TABLE_169__GraphicsLevel_7_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_169__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_169__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_169__GraphicsLevel_7_DownHyst_MASK 0xff0000
+#define DPM_TABLE_169__GraphicsLevel_7_DownHyst__SHIFT 0x10
+#define DPM_TABLE_169__GraphicsLevel_7_UpHyst_MASK 0xff000000
+#define DPM_TABLE_169__GraphicsLevel_7_UpHyst__SHIFT 0x18
+#define DPM_TABLE_170__MemoryACPILevel_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_170__MemoryACPILevel_MinVddc__SHIFT 0x0
+#define DPM_TABLE_171__MemoryACPILevel_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_171__MemoryACPILevel_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_172__MemoryACPILevel_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_172__MemoryACPILevel_MinVddci__SHIFT 0x0
+#define DPM_TABLE_173__MemoryACPILevel_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_173__MemoryACPILevel_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_174__MemoryACPILevel_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_174__MemoryACPILevel_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_175__MemoryACPILevel_StutterEnable_MASK 0xff
+#define DPM_TABLE_175__MemoryACPILevel_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_175__MemoryACPILevel_RttEnable_MASK 0xff00
+#define DPM_TABLE_175__MemoryACPILevel_RttEnable__SHIFT 0x8
+#define DPM_TABLE_175__MemoryACPILevel_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_175__MemoryACPILevel_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_175__MemoryACPILevel_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_175__MemoryACPILevel_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_176__MemoryACPILevel_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_176__MemoryACPILevel_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_176__MemoryACPILevel_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_176__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_176__MemoryACPILevel_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_176__MemoryACPILevel_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_176__MemoryACPILevel_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_176__MemoryACPILevel_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_177__MemoryACPILevel_padding_MASK 0xff
+#define DPM_TABLE_177__MemoryACPILevel_padding__SHIFT 0x0
+#define DPM_TABLE_177__MemoryACPILevel_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_177__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_177__MemoryACPILevel_DownHyst_MASK 0xff0000
+#define DPM_TABLE_177__MemoryACPILevel_DownHyst__SHIFT 0x10
+#define DPM_TABLE_177__MemoryACPILevel_UpHyst_MASK 0xff000000
+#define DPM_TABLE_177__MemoryACPILevel_UpHyst__SHIFT 0x18
+#define DPM_TABLE_178__MemoryACPILevel_padding1_MASK 0xff
+#define DPM_TABLE_178__MemoryACPILevel_padding1__SHIFT 0x0
+#define DPM_TABLE_178__MemoryACPILevel_DisplayWatermark_MASK 0xff00
+#define DPM_TABLE_178__MemoryACPILevel_DisplayWatermark__SHIFT 0x8
+#define DPM_TABLE_178__MemoryACPILevel_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_178__MemoryACPILevel_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_179__MemoryACPILevel_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_179__MemoryACPILevel_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_180__MemoryACPILevel_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_180__MemoryACPILevel_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_181__MemoryACPILevel_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_181__MemoryACPILevel_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_182__MemoryACPILevel_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_182__MemoryACPILevel_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_183__MemoryACPILevel_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_183__MemoryACPILevel_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_184__MemoryACPILevel_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_184__MemoryACPILevel_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_185__MemoryACPILevel_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_185__MemoryACPILevel_DllCntl__SHIFT 0x0
+#define DPM_TABLE_186__MemoryACPILevel_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_186__MemoryACPILevel_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_187__MemoryACPILevel_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_187__MemoryACPILevel_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_188__MemoryLevel_0_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_188__MemoryLevel_0_MinVddc__SHIFT 0x0
+#define DPM_TABLE_189__MemoryLevel_0_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_189__MemoryLevel_0_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_190__MemoryLevel_0_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_190__MemoryLevel_0_MinVddci__SHIFT 0x0
+#define DPM_TABLE_191__MemoryLevel_0_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_191__MemoryLevel_0_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_192__MemoryLevel_0_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_192__MemoryLevel_0_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_193__MemoryLevel_0_StutterEnable_MASK 0xff
+#define DPM_TABLE_193__MemoryLevel_0_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_193__MemoryLevel_0_RttEnable_MASK 0xff00
+#define DPM_TABLE_193__MemoryLevel_0_RttEnable__SHIFT 0x8
+#define DPM_TABLE_193__MemoryLevel_0_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_193__MemoryLevel_0_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_193__MemoryLevel_0_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_193__MemoryLevel_0_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_194__MemoryLevel_0_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_194__MemoryLevel_0_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_194__MemoryLevel_0_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_194__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_194__MemoryLevel_0_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_194__MemoryLevel_0_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_194__MemoryLevel_0_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_194__MemoryLevel_0_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_195__MemoryLevel_0_padding_MASK 0xff
+#define DPM_TABLE_195__MemoryLevel_0_padding__SHIFT 0x0
+#define DPM_TABLE_195__MemoryLevel_0_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_195__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_195__MemoryLevel_0_DownHyst_MASK 0xff0000
+#define DPM_TABLE_195__MemoryLevel_0_DownHyst__SHIFT 0x10
+#define DPM_TABLE_195__MemoryLevel_0_UpHyst_MASK 0xff000000
+#define DPM_TABLE_195__MemoryLevel_0_UpHyst__SHIFT 0x18
+#define DPM_TABLE_196__MemoryLevel_0_padding1_MASK 0xff
+#define DPM_TABLE_196__MemoryLevel_0_padding1__SHIFT 0x0
+#define DPM_TABLE_196__MemoryLevel_0_DisplayWatermark_MASK 0xff00
+#define DPM_TABLE_196__MemoryLevel_0_DisplayWatermark__SHIFT 0x8
+#define DPM_TABLE_196__MemoryLevel_0_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_196__MemoryLevel_0_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_197__MemoryLevel_0_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_197__MemoryLevel_0_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_198__MemoryLevel_0_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_198__MemoryLevel_0_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_199__MemoryLevel_0_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_199__MemoryLevel_0_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_200__MemoryLevel_0_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_200__MemoryLevel_0_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_201__MemoryLevel_0_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_201__MemoryLevel_0_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_202__MemoryLevel_0_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_202__MemoryLevel_0_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_203__MemoryLevel_0_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_203__MemoryLevel_0_DllCntl__SHIFT 0x0
+#define DPM_TABLE_204__MemoryLevel_0_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_204__MemoryLevel_0_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_205__MemoryLevel_0_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_205__MemoryLevel_0_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_206__MemoryLevel_1_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_206__MemoryLevel_1_MinVddc__SHIFT 0x0
+#define DPM_TABLE_207__MemoryLevel_1_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_207__MemoryLevel_1_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_208__MemoryLevel_1_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_208__MemoryLevel_1_MinVddci__SHIFT 0x0
+#define DPM_TABLE_209__MemoryLevel_1_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_209__MemoryLevel_1_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_210__MemoryLevel_1_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_210__MemoryLevel_1_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_211__MemoryLevel_1_StutterEnable_MASK 0xff
+#define DPM_TABLE_211__MemoryLevel_1_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_211__MemoryLevel_1_RttEnable_MASK 0xff00
+#define DPM_TABLE_211__MemoryLevel_1_RttEnable__SHIFT 0x8
+#define DPM_TABLE_211__MemoryLevel_1_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_211__MemoryLevel_1_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_211__MemoryLevel_1_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_211__MemoryLevel_1_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_212__MemoryLevel_1_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_212__MemoryLevel_1_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_212__MemoryLevel_1_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_212__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_212__MemoryLevel_1_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_212__MemoryLevel_1_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_212__MemoryLevel_1_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_212__MemoryLevel_1_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_213__MemoryLevel_1_padding_MASK 0xff
+#define DPM_TABLE_213__MemoryLevel_1_padding__SHIFT 0x0
+#define DPM_TABLE_213__MemoryLevel_1_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_213__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_213__MemoryLevel_1_DownHyst_MASK 0xff0000
+#define DPM_TABLE_213__MemoryLevel_1_DownHyst__SHIFT 0x10
+#define DPM_TABLE_213__MemoryLevel_1_UpHyst_MASK 0xff000000
+#define DPM_TABLE_213__MemoryLevel_1_UpHyst__SHIFT 0x18
+#define DPM_TABLE_214__MemoryLevel_1_padding1_MASK 0xff
+#define DPM_TABLE_214__MemoryLevel_1_padding1__SHIFT 0x0
+#define DPM_TABLE_214__MemoryLevel_1_DisplayWatermark_MASK 0xff00
+#define DPM_TABLE_214__MemoryLevel_1_DisplayWatermark__SHIFT 0x8
+#define DPM_TABLE_214__MemoryLevel_1_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_214__MemoryLevel_1_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_215__MemoryLevel_1_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_215__MemoryLevel_1_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_216__MemoryLevel_1_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_216__MemoryLevel_1_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_217__MemoryLevel_1_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_217__MemoryLevel_1_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_218__MemoryLevel_1_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_218__MemoryLevel_1_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_219__MemoryLevel_1_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_219__MemoryLevel_1_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_220__MemoryLevel_1_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_220__MemoryLevel_1_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_221__MemoryLevel_1_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_221__MemoryLevel_1_DllCntl__SHIFT 0x0
+#define DPM_TABLE_222__MemoryLevel_1_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_222__MemoryLevel_1_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_223__MemoryLevel_1_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_223__MemoryLevel_1_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_224__MemoryLevel_2_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_224__MemoryLevel_2_MinVddc__SHIFT 0x0
+#define DPM_TABLE_225__MemoryLevel_2_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_225__MemoryLevel_2_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_226__MemoryLevel_2_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_226__MemoryLevel_2_MinVddci__SHIFT 0x0
+#define DPM_TABLE_227__MemoryLevel_2_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_227__MemoryLevel_2_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_228__MemoryLevel_2_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_228__MemoryLevel_2_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_229__MemoryLevel_2_StutterEnable_MASK 0xff
+#define DPM_TABLE_229__MemoryLevel_2_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_229__MemoryLevel_2_RttEnable_MASK 0xff00
+#define DPM_TABLE_229__MemoryLevel_2_RttEnable__SHIFT 0x8
+#define DPM_TABLE_229__MemoryLevel_2_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_229__MemoryLevel_2_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_229__MemoryLevel_2_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_229__MemoryLevel_2_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_230__MemoryLevel_2_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_230__MemoryLevel_2_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_230__MemoryLevel_2_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_230__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_230__MemoryLevel_2_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_230__MemoryLevel_2_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_230__MemoryLevel_2_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_230__MemoryLevel_2_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_231__MemoryLevel_2_padding_MASK 0xff
+#define DPM_TABLE_231__MemoryLevel_2_padding__SHIFT 0x0
+#define DPM_TABLE_231__MemoryLevel_2_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_231__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_231__MemoryLevel_2_DownHyst_MASK 0xff0000
+#define DPM_TABLE_231__MemoryLevel_2_DownHyst__SHIFT 0x10
+#define DPM_TABLE_231__MemoryLevel_2_UpHyst_MASK 0xff000000
+#define DPM_TABLE_231__MemoryLevel_2_UpHyst__SHIFT 0x18
+#define DPM_TABLE_232__MemoryLevel_2_padding1_MASK 0xff
+#define DPM_TABLE_232__MemoryLevel_2_padding1__SHIFT 0x0
+#define DPM_TABLE_232__MemoryLevel_2_DisplayWatermark_MASK 0xff00
+#define DPM_TABLE_232__MemoryLevel_2_DisplayWatermark__SHIFT 0x8
+#define DPM_TABLE_232__MemoryLevel_2_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_232__MemoryLevel_2_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_233__MemoryLevel_2_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_233__MemoryLevel_2_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_234__MemoryLevel_2_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_234__MemoryLevel_2_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_235__MemoryLevel_2_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_235__MemoryLevel_2_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_236__MemoryLevel_2_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_236__MemoryLevel_2_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_237__MemoryLevel_2_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_237__MemoryLevel_2_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_238__MemoryLevel_2_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_238__MemoryLevel_2_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_239__MemoryLevel_2_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_239__MemoryLevel_2_DllCntl__SHIFT 0x0
+#define DPM_TABLE_240__MemoryLevel_2_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_240__MemoryLevel_2_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_241__MemoryLevel_2_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_241__MemoryLevel_2_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_242__MemoryLevel_3_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_242__MemoryLevel_3_MinVddc__SHIFT 0x0
+#define DPM_TABLE_243__MemoryLevel_3_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_243__MemoryLevel_3_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_244__MemoryLevel_3_MinVddci_MASK 0xffffffff
+#define DPM_TABLE_244__MemoryLevel_3_MinVddci__SHIFT 0x0
+#define DPM_TABLE_245__MemoryLevel_3_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_245__MemoryLevel_3_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_246__MemoryLevel_3_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_246__MemoryLevel_3_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_247__MemoryLevel_3_StutterEnable_MASK 0xff
+#define DPM_TABLE_247__MemoryLevel_3_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_247__MemoryLevel_3_RttEnable_MASK 0xff00
+#define DPM_TABLE_247__MemoryLevel_3_RttEnable__SHIFT 0x8
+#define DPM_TABLE_247__MemoryLevel_3_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_247__MemoryLevel_3_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_247__MemoryLevel_3_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_247__MemoryLevel_3_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_248__MemoryLevel_3_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_248__MemoryLevel_3_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_248__MemoryLevel_3_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_248__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_248__MemoryLevel_3_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_248__MemoryLevel_3_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_248__MemoryLevel_3_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_248__MemoryLevel_3_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_249__MemoryLevel_3_padding_MASK 0xff
+#define DPM_TABLE_249__MemoryLevel_3_padding__SHIFT 0x0
+#define DPM_TABLE_249__MemoryLevel_3_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_249__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_249__MemoryLevel_3_DownHyst_MASK 0xff0000
+#define DPM_TABLE_249__MemoryLevel_3_DownHyst__SHIFT 0x10
+#define DPM_TABLE_249__MemoryLevel_3_UpHyst_MASK 0xff000000
+#define DPM_TABLE_249__MemoryLevel_3_UpHyst__SHIFT 0x18
+#define DPM_TABLE_250__MemoryLevel_3_padding1_MASK 0xff
+#define DPM_TABLE_250__MemoryLevel_3_padding1__SHIFT 0x0
+#define DPM_TABLE_250__MemoryLevel_3_DisplayWatermark_MASK 0xff00
+#define DPM_TABLE_250__MemoryLevel_3_DisplayWatermark__SHIFT 0x8
+#define DPM_TABLE_250__MemoryLevel_3_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_250__MemoryLevel_3_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_251__MemoryLevel_3_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_251__MemoryLevel_3_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_252__MemoryLevel_3_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_252__MemoryLevel_3_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_253__MemoryLevel_3_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_253__MemoryLevel_3_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_254__MemoryLevel_3_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_254__MemoryLevel_3_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_255__MemoryLevel_3_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_255__MemoryLevel_3_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_256__MemoryLevel_3_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_256__MemoryLevel_3_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_257__MemoryLevel_3_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_257__MemoryLevel_3_DllCntl__SHIFT 0x0
+#define DPM_TABLE_258__MemoryLevel_3_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_258__MemoryLevel_3_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_259__MemoryLevel_3_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_259__MemoryLevel_3_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_260__LinkLevel_0_SPC_MASK 0xff
+#define DPM_TABLE_260__LinkLevel_0_SPC__SHIFT 0x0
+#define DPM_TABLE_260__LinkLevel_0_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_260__LinkLevel_0_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_260__LinkLevel_0_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_260__LinkLevel_0_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_260__LinkLevel_0_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_260__LinkLevel_0_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_261__LinkLevel_0_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_261__LinkLevel_0_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_262__LinkLevel_0_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_262__LinkLevel_0_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_263__LinkLevel_0_Reserved_MASK 0xffffffff
+#define DPM_TABLE_263__LinkLevel_0_Reserved__SHIFT 0x0
+#define DPM_TABLE_264__LinkLevel_1_SPC_MASK 0xff
+#define DPM_TABLE_264__LinkLevel_1_SPC__SHIFT 0x0
+#define DPM_TABLE_264__LinkLevel_1_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_264__LinkLevel_1_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_264__LinkLevel_1_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_264__LinkLevel_1_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_264__LinkLevel_1_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_264__LinkLevel_1_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_265__LinkLevel_1_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_265__LinkLevel_1_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_266__LinkLevel_1_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_266__LinkLevel_1_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_267__LinkLevel_1_Reserved_MASK 0xffffffff
+#define DPM_TABLE_267__LinkLevel_1_Reserved__SHIFT 0x0
+#define DPM_TABLE_268__LinkLevel_2_SPC_MASK 0xff
+#define DPM_TABLE_268__LinkLevel_2_SPC__SHIFT 0x0
+#define DPM_TABLE_268__LinkLevel_2_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_268__LinkLevel_2_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_268__LinkLevel_2_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_268__LinkLevel_2_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_268__LinkLevel_2_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_268__LinkLevel_2_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_269__LinkLevel_2_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_269__LinkLevel_2_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_270__LinkLevel_2_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_270__LinkLevel_2_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_271__LinkLevel_2_Reserved_MASK 0xffffffff
+#define DPM_TABLE_271__LinkLevel_2_Reserved__SHIFT 0x0
+#define DPM_TABLE_272__LinkLevel_3_SPC_MASK 0xff
+#define DPM_TABLE_272__LinkLevel_3_SPC__SHIFT 0x0
+#define DPM_TABLE_272__LinkLevel_3_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_272__LinkLevel_3_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_272__LinkLevel_3_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_272__LinkLevel_3_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_272__LinkLevel_3_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_272__LinkLevel_3_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_273__LinkLevel_3_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_273__LinkLevel_3_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_274__LinkLevel_3_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_274__LinkLevel_3_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_275__LinkLevel_3_Reserved_MASK 0xffffffff
+#define DPM_TABLE_275__LinkLevel_3_Reserved__SHIFT 0x0
+#define DPM_TABLE_276__LinkLevel_4_SPC_MASK 0xff
+#define DPM_TABLE_276__LinkLevel_4_SPC__SHIFT 0x0
+#define DPM_TABLE_276__LinkLevel_4_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_276__LinkLevel_4_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_276__LinkLevel_4_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_276__LinkLevel_4_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_276__LinkLevel_4_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_276__LinkLevel_4_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_277__LinkLevel_4_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_277__LinkLevel_4_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_278__LinkLevel_4_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_278__LinkLevel_4_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_279__LinkLevel_4_Reserved_MASK 0xffffffff
+#define DPM_TABLE_279__LinkLevel_4_Reserved__SHIFT 0x0
+#define DPM_TABLE_280__LinkLevel_5_SPC_MASK 0xff
+#define DPM_TABLE_280__LinkLevel_5_SPC__SHIFT 0x0
+#define DPM_TABLE_280__LinkLevel_5_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_280__LinkLevel_5_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_280__LinkLevel_5_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_280__LinkLevel_5_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_280__LinkLevel_5_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_280__LinkLevel_5_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_281__LinkLevel_5_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_281__LinkLevel_5_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_282__LinkLevel_5_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_282__LinkLevel_5_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_283__LinkLevel_5_Reserved_MASK 0xffffffff
+#define DPM_TABLE_283__LinkLevel_5_Reserved__SHIFT 0x0
+#define DPM_TABLE_284__LinkLevel_6_SPC_MASK 0xff
+#define DPM_TABLE_284__LinkLevel_6_SPC__SHIFT 0x0
+#define DPM_TABLE_284__LinkLevel_6_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_284__LinkLevel_6_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_284__LinkLevel_6_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_284__LinkLevel_6_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_284__LinkLevel_6_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_284__LinkLevel_6_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_285__LinkLevel_6_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_285__LinkLevel_6_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_286__LinkLevel_6_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_286__LinkLevel_6_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_287__LinkLevel_6_Reserved_MASK 0xffffffff
+#define DPM_TABLE_287__LinkLevel_6_Reserved__SHIFT 0x0
+#define DPM_TABLE_288__LinkLevel_7_SPC_MASK 0xff
+#define DPM_TABLE_288__LinkLevel_7_SPC__SHIFT 0x0
+#define DPM_TABLE_288__LinkLevel_7_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_288__LinkLevel_7_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_288__LinkLevel_7_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_288__LinkLevel_7_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_288__LinkLevel_7_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_288__LinkLevel_7_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_289__LinkLevel_7_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_289__LinkLevel_7_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_290__LinkLevel_7_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_290__LinkLevel_7_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_291__LinkLevel_7_Reserved_MASK 0xffffffff
+#define DPM_TABLE_291__LinkLevel_7_Reserved__SHIFT 0x0
+#define DPM_TABLE_292__ACPILevel_Flags_MASK 0xffffffff
+#define DPM_TABLE_292__ACPILevel_Flags__SHIFT 0x0
+#define DPM_TABLE_293__ACPILevel_MinVddc_MASK 0xffffffff
+#define DPM_TABLE_293__ACPILevel_MinVddc__SHIFT 0x0
+#define DPM_TABLE_294__ACPILevel_MinVddcPhases_MASK 0xffffffff
+#define DPM_TABLE_294__ACPILevel_MinVddcPhases__SHIFT 0x0
+#define DPM_TABLE_295__ACPILevel_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_295__ACPILevel_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_296__ACPILevel_padding_MASK 0xff
+#define DPM_TABLE_296__ACPILevel_padding__SHIFT 0x0
+#define DPM_TABLE_296__ACPILevel_DeepSleepDivId_MASK 0xff00
+#define DPM_TABLE_296__ACPILevel_DeepSleepDivId__SHIFT 0x8
+#define DPM_TABLE_296__ACPILevel_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_296__ACPILevel_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_296__ACPILevel_SclkDid_MASK 0xff000000
+#define DPM_TABLE_296__ACPILevel_SclkDid__SHIFT 0x18
+#define DPM_TABLE_297__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_297__ACPILevel_CgSpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_298__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff
+#define DPM_TABLE_298__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0
+#define DPM_TABLE_299__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_299__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_300__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_300__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_301__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_301__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_302__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_302__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_303__ACPILevel_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_303__ACPILevel_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_304__ACPILevel_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_304__ACPILevel_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_305__SclkStepSize_MASK 0xffffffff
+#define DPM_TABLE_305__SclkStepSize__SHIFT 0x0
+#define DPM_TABLE_306__Smio_0_MASK 0xffffffff
+#define DPM_TABLE_306__Smio_0__SHIFT 0x0
+#define DPM_TABLE_307__Smio_1_MASK 0xffffffff
+#define DPM_TABLE_307__Smio_1__SHIFT 0x0
+#define DPM_TABLE_308__Smio_2_MASK 0xffffffff
+#define DPM_TABLE_308__Smio_2__SHIFT 0x0
+#define DPM_TABLE_309__Smio_3_MASK 0xffffffff
+#define DPM_TABLE_309__Smio_3__SHIFT 0x0
+#define DPM_TABLE_310__Smio_4_MASK 0xffffffff
+#define DPM_TABLE_310__Smio_4__SHIFT 0x0
+#define DPM_TABLE_311__Smio_5_MASK 0xffffffff
+#define DPM_TABLE_311__Smio_5__SHIFT 0x0
+#define DPM_TABLE_312__Smio_6_MASK 0xffffffff
+#define DPM_TABLE_312__Smio_6__SHIFT 0x0
+#define DPM_TABLE_313__Smio_7_MASK 0xffffffff
+#define DPM_TABLE_313__Smio_7__SHIFT 0x0
+#define DPM_TABLE_314__Smio_8_MASK 0xffffffff
+#define DPM_TABLE_314__Smio_8__SHIFT 0x0
+#define DPM_TABLE_315__Smio_9_MASK 0xffffffff
+#define DPM_TABLE_315__Smio_9__SHIFT 0x0
+#define DPM_TABLE_316__Smio_10_MASK 0xffffffff
+#define DPM_TABLE_316__Smio_10__SHIFT 0x0
+#define DPM_TABLE_317__Smio_11_MASK 0xffffffff
+#define DPM_TABLE_317__Smio_11__SHIFT 0x0
+#define DPM_TABLE_318__Smio_12_MASK 0xffffffff
+#define DPM_TABLE_318__Smio_12__SHIFT 0x0
+#define DPM_TABLE_319__Smio_13_MASK 0xffffffff
+#define DPM_TABLE_319__Smio_13__SHIFT 0x0
+#define DPM_TABLE_320__Smio_14_MASK 0xffffffff
+#define DPM_TABLE_320__Smio_14__SHIFT 0x0
+#define DPM_TABLE_321__Smio_15_MASK 0xffffffff
+#define DPM_TABLE_321__Smio_15__SHIFT 0x0
+#define DPM_TABLE_322__Smio_16_MASK 0xffffffff
+#define DPM_TABLE_322__Smio_16__SHIFT 0x0
+#define DPM_TABLE_323__Smio_17_MASK 0xffffffff
+#define DPM_TABLE_323__Smio_17__SHIFT 0x0
+#define DPM_TABLE_324__Smio_18_MASK 0xffffffff
+#define DPM_TABLE_324__Smio_18__SHIFT 0x0
+#define DPM_TABLE_325__Smio_19_MASK 0xffffffff
+#define DPM_TABLE_325__Smio_19__SHIFT 0x0
+#define DPM_TABLE_326__Smio_20_MASK 0xffffffff
+#define DPM_TABLE_326__Smio_20__SHIFT 0x0
+#define DPM_TABLE_327__Smio_21_MASK 0xffffffff
+#define DPM_TABLE_327__Smio_21__SHIFT 0x0
+#define DPM_TABLE_328__Smio_22_MASK 0xffffffff
+#define DPM_TABLE_328__Smio_22__SHIFT 0x0
+#define DPM_TABLE_329__Smio_23_MASK 0xffffffff
+#define DPM_TABLE_329__Smio_23__SHIFT 0x0
+#define DPM_TABLE_330__Smio_24_MASK 0xffffffff
+#define DPM_TABLE_330__Smio_24__SHIFT 0x0
+#define DPM_TABLE_331__Smio_25_MASK 0xffffffff
+#define DPM_TABLE_331__Smio_25__SHIFT 0x0
+#define DPM_TABLE_332__Smio_26_MASK 0xffffffff
+#define DPM_TABLE_332__Smio_26__SHIFT 0x0
+#define DPM_TABLE_333__Smio_27_MASK 0xffffffff
+#define DPM_TABLE_333__Smio_27__SHIFT 0x0
+#define DPM_TABLE_334__Smio_28_MASK 0xffffffff
+#define DPM_TABLE_334__Smio_28__SHIFT 0x0
+#define DPM_TABLE_335__Smio_29_MASK 0xffffffff
+#define DPM_TABLE_335__Smio_29__SHIFT 0x0
+#define DPM_TABLE_336__Smio_30_MASK 0xffffffff
+#define DPM_TABLE_336__Smio_30__SHIFT 0x0
+#define DPM_TABLE_337__Smio_31_MASK 0xffffffff
+#define DPM_TABLE_337__Smio_31__SHIFT 0x0
+#define DPM_TABLE_338__GraphicsInterval_MASK 0xff
+#define DPM_TABLE_338__GraphicsInterval__SHIFT 0x0
+#define DPM_TABLE_338__GraphicsThermThrottleEnable_MASK 0xff00
+#define DPM_TABLE_338__GraphicsThermThrottleEnable__SHIFT 0x8
+#define DPM_TABLE_338__GraphicsVoltageChangeEnable_MASK 0xff0000
+#define DPM_TABLE_338__GraphicsVoltageChangeEnable__SHIFT 0x10
+#define DPM_TABLE_338__GraphicsBootLevel_MASK 0xff000000
+#define DPM_TABLE_338__GraphicsBootLevel__SHIFT 0x18
+#define DPM_TABLE_339__TemperatureLimitHigh_MASK 0xffff
+#define DPM_TABLE_339__TemperatureLimitHigh__SHIFT 0x0
+#define DPM_TABLE_339__ThermalInterval_MASK 0xff0000
+#define DPM_TABLE_339__ThermalInterval__SHIFT 0x10
+#define DPM_TABLE_339__VoltageInterval_MASK 0xff000000
+#define DPM_TABLE_339__VoltageInterval__SHIFT 0x18
+#define DPM_TABLE_340__MemoryVoltageChangeEnable_MASK 0xff
+#define DPM_TABLE_340__MemoryVoltageChangeEnable__SHIFT 0x0
+#define DPM_TABLE_340__MemoryBootLevel_MASK 0xff00
+#define DPM_TABLE_340__MemoryBootLevel__SHIFT 0x8
+#define DPM_TABLE_340__TemperatureLimitLow_MASK 0xffff0000
+#define DPM_TABLE_340__TemperatureLimitLow__SHIFT 0x10
+#define DPM_TABLE_341__padding2_MASK 0xff
+#define DPM_TABLE_341__padding2__SHIFT 0x0
+#define DPM_TABLE_341__MergedVddci_MASK 0xff00
+#define DPM_TABLE_341__MergedVddci__SHIFT 0x8
+#define DPM_TABLE_341__MemoryThermThrottleEnable_MASK 0xff0000
+#define DPM_TABLE_341__MemoryThermThrottleEnable__SHIFT 0x10
+#define DPM_TABLE_341__MemoryInterval_MASK 0xff000000
+#define DPM_TABLE_341__MemoryInterval__SHIFT 0x18
+#define DPM_TABLE_342__PhaseResponseTime_MASK 0xffff
+#define DPM_TABLE_342__PhaseResponseTime__SHIFT 0x0
+#define DPM_TABLE_342__VoltageResponseTime_MASK 0xffff0000
+#define DPM_TABLE_342__VoltageResponseTime__SHIFT 0x10
+#define DPM_TABLE_343__DTEMode_MASK 0xff
+#define DPM_TABLE_343__DTEMode__SHIFT 0x0
+#define DPM_TABLE_343__DTEInterval_MASK 0xff00
+#define DPM_TABLE_343__DTEInterval__SHIFT 0x8
+#define DPM_TABLE_343__PCIeGenInterval_MASK 0xff0000
+#define DPM_TABLE_343__PCIeGenInterval__SHIFT 0x10
+#define DPM_TABLE_343__PCIeBootLinkLevel_MASK 0xff000000
+#define DPM_TABLE_343__PCIeBootLinkLevel__SHIFT 0x18
+#define DPM_TABLE_344__ThermGpio_MASK 0xff
+#define DPM_TABLE_344__ThermGpio__SHIFT 0x0
+#define DPM_TABLE_344__AcDcGpio_MASK 0xff00
+#define DPM_TABLE_344__AcDcGpio__SHIFT 0x8
+#define DPM_TABLE_344__VRHotGpio_MASK 0xff0000
+#define DPM_TABLE_344__VRHotGpio__SHIFT 0x10
+#define DPM_TABLE_344__SVI2Enable_MASK 0xff000000
+#define DPM_TABLE_344__SVI2Enable__SHIFT 0x18
+#define DPM_TABLE_345__DisplayCac_MASK 0xffffffff
+#define DPM_TABLE_345__DisplayCac__SHIFT 0x0
+#define DPM_TABLE_346__NomPwr_MASK 0xffff
+#define DPM_TABLE_346__NomPwr__SHIFT 0x0
+#define DPM_TABLE_346__MaxPwr_MASK 0xffff0000
+#define DPM_TABLE_346__MaxPwr__SHIFT 0x10
+#define DPM_TABLE_347__FpsLowThreshold_MASK 0xffff
+#define DPM_TABLE_347__FpsLowThreshold__SHIFT 0x0
+#define DPM_TABLE_347__FpsHighThreshold_MASK 0xffff0000
+#define DPM_TABLE_347__FpsHighThreshold__SHIFT 0x10
+#define DPM_TABLE_348__BAPMTI_R_0_1_0_MASK 0xffff
+#define DPM_TABLE_348__BAPMTI_R_0_1_0__SHIFT 0x0
+#define DPM_TABLE_348__BAPMTI_R_0_0_0_MASK 0xffff0000
+#define DPM_TABLE_348__BAPMTI_R_0_0_0__SHIFT 0x10
+#define DPM_TABLE_349__BAPMTI_R_1_0_0_MASK 0xffff
+#define DPM_TABLE_349__BAPMTI_R_1_0_0__SHIFT 0x0
+#define DPM_TABLE_349__BAPMTI_R_0_2_0_MASK 0xffff0000
+#define DPM_TABLE_349__BAPMTI_R_0_2_0__SHIFT 0x10
+#define DPM_TABLE_350__BAPMTI_R_1_2_0_MASK 0xffff
+#define DPM_TABLE_350__BAPMTI_R_1_2_0__SHIFT 0x0
+#define DPM_TABLE_350__BAPMTI_R_1_1_0_MASK 0xffff0000
+#define DPM_TABLE_350__BAPMTI_R_1_1_0__SHIFT 0x10
+#define DPM_TABLE_351__BAPMTI_R_2_1_0_MASK 0xffff
+#define DPM_TABLE_351__BAPMTI_R_2_1_0__SHIFT 0x0
+#define DPM_TABLE_351__BAPMTI_R_2_0_0_MASK 0xffff0000
+#define DPM_TABLE_351__BAPMTI_R_2_0_0__SHIFT 0x10
+#define DPM_TABLE_352__BAPMTI_R_3_0_0_MASK 0xffff
+#define DPM_TABLE_352__BAPMTI_R_3_0_0__SHIFT 0x0
+#define DPM_TABLE_352__BAPMTI_R_2_2_0_MASK 0xffff0000
+#define DPM_TABLE_352__BAPMTI_R_2_2_0__SHIFT 0x10
+#define DPM_TABLE_353__BAPMTI_R_3_2_0_MASK 0xffff
+#define DPM_TABLE_353__BAPMTI_R_3_2_0__SHIFT 0x0
+#define DPM_TABLE_353__BAPMTI_R_3_1_0_MASK 0xffff0000
+#define DPM_TABLE_353__BAPMTI_R_3_1_0__SHIFT 0x10
+#define DPM_TABLE_354__BAPMTI_R_4_1_0_MASK 0xffff
+#define DPM_TABLE_354__BAPMTI_R_4_1_0__SHIFT 0x0
+#define DPM_TABLE_354__BAPMTI_R_4_0_0_MASK 0xffff0000
+#define DPM_TABLE_354__BAPMTI_R_4_0_0__SHIFT 0x10
+#define DPM_TABLE_355__BAPMTI_RC_0_0_0_MASK 0xffff
+#define DPM_TABLE_355__BAPMTI_RC_0_0_0__SHIFT 0x0
+#define DPM_TABLE_355__BAPMTI_R_4_2_0_MASK 0xffff0000
+#define DPM_TABLE_355__BAPMTI_R_4_2_0__SHIFT 0x10
+#define DPM_TABLE_356__BAPMTI_RC_0_2_0_MASK 0xffff
+#define DPM_TABLE_356__BAPMTI_RC_0_2_0__SHIFT 0x0
+#define DPM_TABLE_356__BAPMTI_RC_0_1_0_MASK 0xffff0000
+#define DPM_TABLE_356__BAPMTI_RC_0_1_0__SHIFT 0x10
+#define DPM_TABLE_357__BAPMTI_RC_1_1_0_MASK 0xffff
+#define DPM_TABLE_357__BAPMTI_RC_1_1_0__SHIFT 0x0
+#define DPM_TABLE_357__BAPMTI_RC_1_0_0_MASK 0xffff0000
+#define DPM_TABLE_357__BAPMTI_RC_1_0_0__SHIFT 0x10
+#define DPM_TABLE_358__BAPMTI_RC_2_0_0_MASK 0xffff
+#define DPM_TABLE_358__BAPMTI_RC_2_0_0__SHIFT 0x0
+#define DPM_TABLE_358__BAPMTI_RC_1_2_0_MASK 0xffff0000
+#define DPM_TABLE_358__BAPMTI_RC_1_2_0__SHIFT 0x10
+#define DPM_TABLE_359__BAPMTI_RC_2_2_0_MASK 0xffff
+#define DPM_TABLE_359__BAPMTI_RC_2_2_0__SHIFT 0x0
+#define DPM_TABLE_359__BAPMTI_RC_2_1_0_MASK 0xffff0000
+#define DPM_TABLE_359__BAPMTI_RC_2_1_0__SHIFT 0x10
+#define DPM_TABLE_360__BAPMTI_RC_3_1_0_MASK 0xffff
+#define DPM_TABLE_360__BAPMTI_RC_3_1_0__SHIFT 0x0
+#define DPM_TABLE_360__BAPMTI_RC_3_0_0_MASK 0xffff0000
+#define DPM_TABLE_360__BAPMTI_RC_3_0_0__SHIFT 0x10
+#define DPM_TABLE_361__BAPMTI_RC_4_0_0_MASK 0xffff
+#define DPM_TABLE_361__BAPMTI_RC_4_0_0__SHIFT 0x0
+#define DPM_TABLE_361__BAPMTI_RC_3_2_0_MASK 0xffff0000
+#define DPM_TABLE_361__BAPMTI_RC_3_2_0__SHIFT 0x10
+#define DPM_TABLE_362__BAPMTI_RC_4_2_0_MASK 0xffff
+#define DPM_TABLE_362__BAPMTI_RC_4_2_0__SHIFT 0x0
+#define DPM_TABLE_362__BAPMTI_RC_4_1_0_MASK 0xffff0000
+#define DPM_TABLE_362__BAPMTI_RC_4_1_0__SHIFT 0x10
+#define DPM_TABLE_363__GpuTjHyst_MASK 0xff
+#define DPM_TABLE_363__GpuTjHyst__SHIFT 0x0
+#define DPM_TABLE_363__GpuTjMax_MASK 0xff00
+#define DPM_TABLE_363__GpuTjMax__SHIFT 0x8
+#define DPM_TABLE_363__DTETjOffset_MASK 0xff0000
+#define DPM_TABLE_363__DTETjOffset__SHIFT 0x10
+#define DPM_TABLE_363__DTEAmbientTempBase_MASK 0xff000000
+#define DPM_TABLE_363__DTEAmbientTempBase__SHIFT 0x18
+#define DPM_TABLE_364__BootVddci_MASK 0xffff
+#define DPM_TABLE_364__BootVddci__SHIFT 0x0
+#define DPM_TABLE_364__BootVddc_MASK 0xffff0000
+#define DPM_TABLE_364__BootVddc__SHIFT 0x10
+#define DPM_TABLE_365__padding_MASK 0xffff
+#define DPM_TABLE_365__padding__SHIFT 0x0
+#define DPM_TABLE_365__BootMVdd_MASK 0xffff0000
+#define DPM_TABLE_365__BootMVdd__SHIFT 0x10
+#define DPM_TABLE_366__BAPM_TEMP_GRADIENT_MASK 0xffffffff
+#define DPM_TABLE_366__BAPM_TEMP_GRADIENT__SHIFT 0x0
+#define DPM_TABLE_367__LowSclkInterruptThreshold_MASK 0xffffffff
+#define DPM_TABLE_367__LowSclkInterruptThreshold__SHIFT 0x0
+#define DPM_TABLE_368__VddGfxReChkWait_MASK 0xffffffff
+#define DPM_TABLE_368__VddGfxReChkWait__SHIFT 0x0
+#define DPM_TABLE_369__PPM_TemperatureLimit_MASK 0xffff
+#define DPM_TABLE_369__PPM_TemperatureLimit__SHIFT 0x0
+#define DPM_TABLE_369__PPM_PkgPwrLimit_MASK 0xffff0000
+#define DPM_TABLE_369__PPM_PkgPwrLimit__SHIFT 0x10
+#define DPM_TABLE_370__TargetTdp_MASK 0xffff
+#define DPM_TABLE_370__TargetTdp__SHIFT 0x0
+#define DPM_TABLE_370__DefaultTdp_MASK 0xffff0000
+#define DPM_TABLE_370__DefaultTdp__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_4__PreVBlankGap_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_4__PreVBlankGap__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_5__VBlankTimeout_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_5__VBlankTimeout__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_6__TrainTimeGap_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_6__TrainTimeGap__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_9__AcpiDelay_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_9__AcpiDelay__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_10__G5TrainTime_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_10__G5TrainTime__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_13__HandshakeDisables_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_13__HandshakeDisables__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config_MASK 0xff00
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config__SHIFT 0x8
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config_MASK 0xff0000
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config_MASK 0xff000000
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config__SHIFT 0x18
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config_MASK 0xff
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config__SHIFT 0x8
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config_MASK 0xff000000
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config__SHIFT 0x18
+#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_18__AverageGioActivity_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_18__AverageGioActivity__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels_MASK 0xff
+#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels_MASK 0xff00
+#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels__SHIFT 0x8
+#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels_MASK 0xff0000
+#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels_MASK 0xff000000
+#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels__SHIFT 0x18
+#define SOFT_REGISTERS_TABLE_20__DRAM_LOG_ADDR_H_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_20__DRAM_LOG_ADDR_H__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_L_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_L__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_PHY_ADDR_H_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_PHY_ADDR_H__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_L_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_L__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_BUFF_SIZE_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_BUFF_SIZE__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_25__UlvEnterCount_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_25__UlvEnterCount__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_26__UlvTime_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_26__UlvTime__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_27__UcodeLoadStatus_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_27__UcodeLoadStatus__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_28__Reserved_0_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_28__Reserved_0__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_29__Reserved_1_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_29__Reserved_1__SHIFT 0x0
+#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1
+#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
+#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe
+#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
+#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000
+#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18
+#define TDC_STATUS__VDD_Boost_MASK 0xff
+#define TDC_STATUS__VDD_Boost__SHIFT 0x0
+#define TDC_STATUS__VDD_Throttle_MASK 0xff00
+#define TDC_STATUS__VDD_Throttle__SHIFT 0x8
+#define TDC_STATUS__VDDC_Boost_MASK 0xff0000
+#define TDC_STATUS__VDDC_Boost__SHIFT 0x10
+#define TDC_STATUS__VDDC_Throttle_MASK 0xff000000
+#define TDC_STATUS__VDDC_Throttle__SHIFT 0x18
+#define TDC_MV_AVERAGE__IDD_MASK 0xffff
+#define TDC_MV_AVERAGE__IDD__SHIFT 0x0
+#define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000
+#define TDC_MV_AVERAGE__IDDC__SHIFT 0x10
+#define TDC_VRM_LIMIT__IDD_MASK 0xffff
+#define TDC_VRM_LIMIT__IDD__SHIFT 0x0
+#define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000
+#define TDC_VRM_LIMIT__IDDC__SHIFT 0x10
+#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1
+#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0
+#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2
+#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1
+#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4
+#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2
+#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8
+#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3
+#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10
+#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4
+#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x20
+#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x5
+#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x40
+#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x6
+#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80
+#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7
+#define FEATURE_STATUS__BAPM_ON_MASK 0x100
+#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8
+#define FEATURE_STATUS__LPMX_ON_MASK 0x200
+#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9
+#define FEATURE_STATUS__NBDPM_ON_MASK 0x400
+#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa
+#define FEATURE_STATUS__LHTC_ON_MASK 0x800
+#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb
+#define FEATURE_STATUS__VPC_ON_MASK 0x1000
+#define FEATURE_STATUS__VPC_ON__SHIFT 0xc
+#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000
+#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd
+#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000
+#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe
+#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000
+#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf
+#define FEATURE_STATUS__AVS_ON_MASK 0x10000
+#define FEATURE_STATUS__AVS_ON__SHIFT 0x10
+#define FEATURE_STATUS__SPMI_ON_MASK 0x20000
+#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11
+#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000
+#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12
+#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000
+#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13
+#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000
+#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14
+#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000
+#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15
+#define FEATURE_STATUS__RESERVED_MASK 0xffc00000
+#define FEATURE_STATUS__RESERVED__SHIFT 0x16
+#define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff
+#define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0
+#define PM_FUSES_1__BapmVddCVidHiSidd_3_MASK 0xff
+#define PM_FUSES_1__BapmVddCVidHiSidd_3__SHIFT 0x0
+#define PM_FUSES_1__BapmVddCVidHiSidd_2_MASK 0xff00
+#define PM_FUSES_1__BapmVddCVidHiSidd_2__SHIFT 0x8
+#define PM_FUSES_1__BapmVddCVidHiSidd_1_MASK 0xff0000
+#define PM_FUSES_1__BapmVddCVidHiSidd_1__SHIFT 0x10
+#define PM_FUSES_1__BapmVddCVidHiSidd_0_MASK 0xff000000
+#define PM_FUSES_1__BapmVddCVidHiSidd_0__SHIFT 0x18
+#define PM_FUSES_2__BapmVddCVidHiSidd_7_MASK 0xff
+#define PM_FUSES_2__BapmVddCVidHiSidd_7__SHIFT 0x0
+#define PM_FUSES_2__BapmVddCVidHiSidd_6_MASK 0xff00
+#define PM_FUSES_2__BapmVddCVidHiSidd_6__SHIFT 0x8
+#define PM_FUSES_2__BapmVddCVidHiSidd_5_MASK 0xff0000
+#define PM_FUSES_2__BapmVddCVidHiSidd_5__SHIFT 0x10
+#define PM_FUSES_2__BapmVddCVidHiSidd_4_MASK 0xff000000
+#define PM_FUSES_2__BapmVddCVidHiSidd_4__SHIFT 0x18
+#define PM_FUSES_3__BapmVddCVidLoSidd_3_MASK 0xff
+#define PM_FUSES_3__BapmVddCVidLoSidd_3__SHIFT 0x0
+#define PM_FUSES_3__BapmVddCVidLoSidd_2_MASK 0xff00
+#define PM_FUSES_3__BapmVddCVidLoSidd_2__SHIFT 0x8
+#define PM_FUSES_3__BapmVddCVidLoSidd_1_MASK 0xff0000
+#define PM_FUSES_3__BapmVddCVidLoSidd_1__SHIFT 0x10
+#define PM_FUSES_3__BapmVddCVidLoSidd_0_MASK 0xff000000
+#define PM_FUSES_3__BapmVddCVidLoSidd_0__SHIFT 0x18
+#define PM_FUSES_4__BapmVddCVidLoSidd_7_MASK 0xff
+#define PM_FUSES_4__BapmVddCVidLoSidd_7__SHIFT 0x0
+#define PM_FUSES_4__BapmVddCVidLoSidd_6_MASK 0xff00
+#define PM_FUSES_4__BapmVddCVidLoSidd_6__SHIFT 0x8
+#define PM_FUSES_4__BapmVddCVidLoSidd_5_MASK 0xff0000
+#define PM_FUSES_4__BapmVddCVidLoSidd_5__SHIFT 0x10
+#define PM_FUSES_4__BapmVddCVidLoSidd_4_MASK 0xff000000
+#define PM_FUSES_4__BapmVddCVidLoSidd_4__SHIFT 0x18
+#define PM_FUSES_5__VddCVid_3_MASK 0xff
+#define PM_FUSES_5__VddCVid_3__SHIFT 0x0
+#define PM_FUSES_5__VddCVid_2_MASK 0xff00
+#define PM_FUSES_5__VddCVid_2__SHIFT 0x8
+#define PM_FUSES_5__VddCVid_1_MASK 0xff0000
+#define PM_FUSES_5__VddCVid_1__SHIFT 0x10
+#define PM_FUSES_5__VddCVid_0_MASK 0xff000000
+#define PM_FUSES_5__VddCVid_0__SHIFT 0x18
+#define PM_FUSES_6__VddCVid_7_MASK 0xff
+#define PM_FUSES_6__VddCVid_7__SHIFT 0x0
+#define PM_FUSES_6__VddCVid_6_MASK 0xff00
+#define PM_FUSES_6__VddCVid_6__SHIFT 0x8
+#define PM_FUSES_6__VddCVid_5_MASK 0xff0000
+#define PM_FUSES_6__VddCVid_5__SHIFT 0x10
+#define PM_FUSES_6__VddCVid_4_MASK 0xff000000
+#define PM_FUSES_6__VddCVid_4__SHIFT 0x18
+#define PM_FUSES_7__SviLoadLineOffsetVddC_MASK 0xff
+#define PM_FUSES_7__SviLoadLineOffsetVddC__SHIFT 0x0
+#define PM_FUSES_7__SviLoadLineTrimVddC_MASK 0xff00
+#define PM_FUSES_7__SviLoadLineTrimVddC__SHIFT 0x8
+#define PM_FUSES_7__SviLoadLineVddC_MASK 0xff0000
+#define PM_FUSES_7__SviLoadLineVddC__SHIFT 0x10
+#define PM_FUSES_7__SviLoadLineEn_MASK 0xff000000
+#define PM_FUSES_7__SviLoadLineEn__SHIFT 0x18
+#define PM_FUSES_8__TDC_MAWt_MASK 0xff
+#define PM_FUSES_8__TDC_MAWt__SHIFT 0x0
+#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc_MASK 0xff00
+#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT 0x8
+#define PM_FUSES_8__TDC_VDDC_PkgLimit_MASK 0xffff0000
+#define PM_FUSES_8__TDC_VDDC_PkgLimit__SHIFT 0x10
+#define PM_FUSES_9__Reserved_MASK 0xff
+#define PM_FUSES_9__Reserved__SHIFT 0x0
+#define PM_FUSES_9__LPMLTemperatureMax_MASK 0xff00
+#define PM_FUSES_9__LPMLTemperatureMax__SHIFT 0x8
+#define PM_FUSES_9__LPMLTemperatureMin_MASK 0xff0000
+#define PM_FUSES_9__LPMLTemperatureMin__SHIFT 0x10
+#define PM_FUSES_9__TdcWaterfallCtl_MASK 0xff000000
+#define PM_FUSES_9__TdcWaterfallCtl__SHIFT 0x18
+#define PM_FUSES_10__LPMLTemperatureScaler_3_MASK 0xff
+#define PM_FUSES_10__LPMLTemperatureScaler_3__SHIFT 0x0
+#define PM_FUSES_10__LPMLTemperatureScaler_2_MASK 0xff00
+#define PM_FUSES_10__LPMLTemperatureScaler_2__SHIFT 0x8
+#define PM_FUSES_10__LPMLTemperatureScaler_1_MASK 0xff0000
+#define PM_FUSES_10__LPMLTemperatureScaler_1__SHIFT 0x10
+#define PM_FUSES_10__LPMLTemperatureScaler_0_MASK 0xff000000
+#define PM_FUSES_10__LPMLTemperatureScaler_0__SHIFT 0x18
+#define PM_FUSES_11__LPMLTemperatureScaler_7_MASK 0xff
+#define PM_FUSES_11__LPMLTemperatureScaler_7__SHIFT 0x0
+#define PM_FUSES_11__LPMLTemperatureScaler_6_MASK 0xff00
+#define PM_FUSES_11__LPMLTemperatureScaler_6__SHIFT 0x8
+#define PM_FUSES_11__LPMLTemperatureScaler_5_MASK 0xff0000
+#define PM_FUSES_11__LPMLTemperatureScaler_5__SHIFT 0x10
+#define PM_FUSES_11__LPMLTemperatureScaler_4_MASK 0xff000000
+#define PM_FUSES_11__LPMLTemperatureScaler_4__SHIFT 0x18
+#define PM_FUSES_12__LPMLTemperatureScaler_11_MASK 0xff
+#define PM_FUSES_12__LPMLTemperatureScaler_11__SHIFT 0x0
+#define PM_FUSES_12__LPMLTemperatureScaler_10_MASK 0xff00
+#define PM_FUSES_12__LPMLTemperatureScaler_10__SHIFT 0x8
+#define PM_FUSES_12__LPMLTemperatureScaler_9_MASK 0xff0000
+#define PM_FUSES_12__LPMLTemperatureScaler_9__SHIFT 0x10
+#define PM_FUSES_12__LPMLTemperatureScaler_8_MASK 0xff000000
+#define PM_FUSES_12__LPMLTemperatureScaler_8__SHIFT 0x18
+#define PM_FUSES_13__LPMLTemperatureScaler_15_MASK 0xff
+#define PM_FUSES_13__LPMLTemperatureScaler_15__SHIFT 0x0
+#define PM_FUSES_13__LPMLTemperatureScaler_14_MASK 0xff00
+#define PM_FUSES_13__LPMLTemperatureScaler_14__SHIFT 0x8
+#define PM_FUSES_13__LPMLTemperatureScaler_13_MASK 0xff0000
+#define PM_FUSES_13__LPMLTemperatureScaler_13__SHIFT 0x10
+#define PM_FUSES_13__LPMLTemperatureScaler_12_MASK 0xff000000
+#define PM_FUSES_13__LPMLTemperatureScaler_12__SHIFT 0x18
+#define PM_FUSES_14__FuzzyFan_ErrorRateSetDelta_MASK 0xffff
+#define PM_FUSES_14__FuzzyFan_ErrorRateSetDelta__SHIFT 0x0
+#define PM_FUSES_14__FuzzyFan_ErrorSetDelta_MASK 0xffff0000
+#define PM_FUSES_14__FuzzyFan_ErrorSetDelta__SHIFT 0x10
+#define PM_FUSES_15__Reserved6_MASK 0xffff
+#define PM_FUSES_15__Reserved6__SHIFT 0x0
+#define PM_FUSES_15__FuzzyFan_PwmSetDelta_MASK 0xffff0000
+#define PM_FUSES_15__FuzzyFan_PwmSetDelta__SHIFT 0x10
+#define PM_FUSES_16__GnbLPML_3_MASK 0xff
+#define PM_FUSES_16__GnbLPML_3__SHIFT 0x0
+#define PM_FUSES_16__GnbLPML_2_MASK 0xff00
+#define PM_FUSES_16__GnbLPML_2__SHIFT 0x8
+#define PM_FUSES_16__GnbLPML_1_MASK 0xff0000
+#define PM_FUSES_16__GnbLPML_1__SHIFT 0x10
+#define PM_FUSES_16__GnbLPML_0_MASK 0xff000000
+#define PM_FUSES_16__GnbLPML_0__SHIFT 0x18
+#define PM_FUSES_17__GnbLPML_7_MASK 0xff
+#define PM_FUSES_17__GnbLPML_7__SHIFT 0x0
+#define PM_FUSES_17__GnbLPML_6_MASK 0xff00
+#define PM_FUSES_17__GnbLPML_6__SHIFT 0x8
+#define PM_FUSES_17__GnbLPML_5_MASK 0xff0000
+#define PM_FUSES_17__GnbLPML_5__SHIFT 0x10
+#define PM_FUSES_17__GnbLPML_4_MASK 0xff000000
+#define PM_FUSES_17__GnbLPML_4__SHIFT 0x18
+#define PM_FUSES_18__GnbLPML_11_MASK 0xff
+#define PM_FUSES_18__GnbLPML_11__SHIFT 0x0
+#define PM_FUSES_18__GnbLPML_10_MASK 0xff00
+#define PM_FUSES_18__GnbLPML_10__SHIFT 0x8
+#define PM_FUSES_18__GnbLPML_9_MASK 0xff0000
+#define PM_FUSES_18__GnbLPML_9__SHIFT 0x10
+#define PM_FUSES_18__GnbLPML_8_MASK 0xff000000
+#define PM_FUSES_18__GnbLPML_8__SHIFT 0x18
+#define PM_FUSES_19__GnbLPML_15_MASK 0xff
+#define PM_FUSES_19__GnbLPML_15__SHIFT 0x0
+#define PM_FUSES_19__GnbLPML_14_MASK 0xff00
+#define PM_FUSES_19__GnbLPML_14__SHIFT 0x8
+#define PM_FUSES_19__GnbLPML_13_MASK 0xff0000
+#define PM_FUSES_19__GnbLPML_13__SHIFT 0x10
+#define PM_FUSES_19__GnbLPML_12_MASK 0xff000000
+#define PM_FUSES_19__GnbLPML_12__SHIFT 0x18
+#define PM_FUSES_20__Reserved1_1_MASK 0xff
+#define PM_FUSES_20__Reserved1_1__SHIFT 0x0
+#define PM_FUSES_20__Reserved1_0_MASK 0xff00
+#define PM_FUSES_20__Reserved1_0__SHIFT 0x8
+#define PM_FUSES_20__GnbLPMLMinVid_MASK 0xff0000
+#define PM_FUSES_20__GnbLPMLMinVid__SHIFT 0x10
+#define PM_FUSES_20__GnbLPMLMaxVid_MASK 0xff000000
+#define PM_FUSES_20__GnbLPMLMaxVid__SHIFT 0x18
+#define PM_FUSES_21__BapmVddCBaseLeakageLoSidd_MASK 0xffff
+#define PM_FUSES_21__BapmVddCBaseLeakageLoSidd__SHIFT 0x0
+#define PM_FUSES_21__BapmVddCBaseLeakageHiSidd_MASK 0xffff0000
+#define PM_FUSES_21__BapmVddCBaseLeakageHiSidd__SHIFT 0x10
+#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_0__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_1__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_2__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_3__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_4__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_5__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_6__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_7__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_8__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_9__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_10__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_11__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_12__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_13__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_14__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_15__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_16__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_17__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_18__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_19__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_20__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_21__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_22__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_23__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_24__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_25__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_26__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_27__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_28__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_29__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_30__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_31__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_32__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_33__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_34__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_35__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_36__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_37__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_38__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_39__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_40__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_41__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_42__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_43__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_44__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_45__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_46__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_47__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_48__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_49__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_50__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_51__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_52__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_53__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_54__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_55__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_56__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_57__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_58__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_59__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_60__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_61__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_62__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_63__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_64__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_65__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_66__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_67__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_68__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_69__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_70__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_71__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_72__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_73__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_74__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_75__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_76__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_77__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_78__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_79__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_80__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_81__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_82__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_83__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_84__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_85__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_86__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_87__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_88__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_89__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_90__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_91__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_92__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_93__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_94__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_95__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_96__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_97__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_98__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_99__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_100__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_101__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_102__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_103__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_104__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_105__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_106__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_107__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_108__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_109__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_110__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_111__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_112__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_113__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_114__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_115__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_116__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_117__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_118__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_119__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_120__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_121__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_122__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_123__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_124__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_125__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_126__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_127__DATA__SHIFT 0x0
+#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1
+#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0
+#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2
+#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2
+#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8
+#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3
+#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10
+#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8
+#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000
+#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10
+#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000
+#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18
+#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000
+#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b
+#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000
+#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c
+#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1
+#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0
+#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2
+#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3
+#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x7
+#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x0
+#define CG_THERMAL_CTRL__THERM_INC_CLK_MASK 0x8
+#define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT 0x3
+#define CG_THERMAL_CTRL__SPARE_MASK 0x3ff0
+#define CG_THERMAL_CTRL__SPARE__SHIFT 0x4
+#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x3fc000
+#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0xe
+#define CG_THERMAL_CTRL__RESERVED_MASK 0x1c00000
+#define CG_THERMAL_CTRL__RESERVED__SHIFT 0x16
+#define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK 0x2000000
+#define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT 0x19
+#define CG_THERMAL_CTRL__CTF_PAD_EN_MASK 0x4000000
+#define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT 0x1a
+#define CG_THERMAL_STATUS__SPARE_MASK 0x1ff
+#define CG_THERMAL_STATUS__SPARE__SHIFT 0x0
+#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x1fe00
+#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9
+#define CG_THERMAL_STATUS__THERM_ALERT_MASK 0x20000
+#define CG_THERMAL_STATUS__THERM_ALERT__SHIFT 0x11
+#define CG_THERMAL_STATUS__GEN_STATUS_MASK 0x3c0000
+#define CG_THERMAL_STATUS__GEN_STATUS__SHIFT 0x12
+#define CG_THERMAL_INT__DIG_THERM_CTF_MASK 0xff
+#define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT 0x0
+#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0xff00
+#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x8
+#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0xff0000
+#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x10
+#define CG_THERMAL_INT__THERM_INT_MASK_MASK 0xf000000
+#define CG_THERMAL_INT__THERM_INT_MASK__SHIFT 0x18
+#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0xf
+#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0
+#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0xf0
+#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4
+#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x200
+#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9
+#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000
+#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14
+#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR_MASK 0x10000000
+#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR__SHIFT 0x1c
+#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x1ff
+#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0
+#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x3fe00
+#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9
+#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0xff
+#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0
+#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0xff00
+#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8
+#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x10000
+#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10
+#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x7e0000
+#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x800000
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xff000000
+#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18
+#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0xff
+#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0
+#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00
+#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8
+#define CG_FDO_CTRL1__M_MASK 0xff0000
+#define CG_FDO_CTRL1__M__SHIFT 0x10
+#define CG_FDO_CTRL1__RESERVED_MASK 0x3f000000
+#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18
+#define CG_FDO_CTRL1__FDO_PWRDNB_MASK 0x40000000
+#define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT 0x1e
+#define CG_FDO_CTRL2__TMIN_MASK 0xff
+#define CG_FDO_CTRL2__TMIN__SHIFT 0x0
+#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x700
+#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8
+#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x3800
+#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb
+#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x1c000
+#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe
+#define CG_FDO_CTRL2__TMAX_MASK 0x1fe0000
+#define CG_FDO_CTRL2__TMAX__SHIFT 0x11
+#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xfe000000
+#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19
+#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x7
+#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0
+#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8
+#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3
+#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff
+#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0
+#define CC_THM_STRAPS0__TMON0_BGADJ_MASK 0x1fe
+#define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT 0x1
+#define CC_THM_STRAPS0__TMON1_BGADJ_MASK 0x1fe00
+#define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT 0x9
+#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK 0x20000
+#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT 0x11
+#define CC_THM_STRAPS0__NUM_ACQ_MASK 0x1c0000
+#define CC_THM_STRAPS0__NUM_ACQ__SHIFT 0x12
+#define CC_THM_STRAPS0__TMON_CLK_SEL_MASK 0xe00000
+#define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT 0x15
+#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK 0x1000000
+#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT 0x18
+#define CC_THM_STRAPS0__CTF_DISABLE_MASK 0x2000000
+#define CC_THM_STRAPS0__CTF_DISABLE__SHIFT 0x19
+#define CC_THM_STRAPS0__TMON0_DISABLE_MASK 0x4000000
+#define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT 0x1a
+#define CC_THM_STRAPS0__TMON1_DISABLE_MASK 0x8000000
+#define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT 0x1b
+#define CC_THM_STRAPS0__TMON2_DISABLE_MASK 0x10000000
+#define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT 0x1c
+#define CC_THM_STRAPS0__TMON3_DISABLE_MASK 0x20000000
+#define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d
+#define CC_THM_STRAPS0__UNUSED_MASK 0x80000000
+#define CC_THM_STRAPS0__UNUSED__SHIFT 0x1f
+#define THM_TMON0_RDIL0_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL1_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL2_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL3_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL4_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL5_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL6_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL7_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL8_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL9_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL10_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL11_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL12_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL13_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL14_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL15_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR0_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR1_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR2_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR3_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR4_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR5_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR6_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR7_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR8_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR9_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR10_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR11_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR12_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR13_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR14_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR15_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_INT_DATA__Z_MASK 0x7ff
+#define THM_TMON0_INT_DATA__Z__SHIFT 0x0
+#define THM_TMON0_INT_DATA__VALID_MASK 0x800
+#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_INT_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x1f
+#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0
+#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0xffe0
+#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5
+#define THM_TMON0_STATUS__CURRENT_RDI_MASK 0x1f
+#define THM_TMON0_STATUS__CURRENT_RDI__SHIFT 0x0
+#define THM_TMON0_STATUS__MEAS_DONE_MASK 0x20
+#define THM_TMON0_STATUS__MEAS_DONE__SHIFT 0x5
+#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1
+#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0
+#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2
+#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3
+#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40
+#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6
+#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100
+#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8
+#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200
+#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9
+#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400
+#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa
+#define GENERAL_PWRMGT__SPARE11_MASK 0x800
+#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb
+#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000
+#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe
+#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000
+#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf
+#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000
+#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10
+#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000
+#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11
+#define GENERAL_PWRMGT__SPARE18_MASK 0x40000
+#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12
+#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000
+#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13
+#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000
+#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17
+#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000
+#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b
+#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000
+#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c
+#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3
+#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0
+#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4
+#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2
+#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8
+#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3
+#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10
+#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4
+#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0
+#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5
+#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1
+#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0
+#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10
+#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4
+#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20
+#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5
+#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000
+#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe
+#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000
+#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf
+#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000
+#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10
+#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000
+#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d
+#define PWR_PCC_CONTROL__PCC_POLARITY_MASK 0x1
+#define PWR_PCC_CONTROL__PCC_POLARITY__SHIFT 0x0
+#define PWR_PCC_GPIO_SELECT__GPIO_MASK 0xffffffff
+#define PWR_PCC_GPIO_SELECT__GPIO__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf
+#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
+#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0
+#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4
+#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00
+#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8
+#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000
+#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf
+#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000
+#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c
+#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff
+#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0
+#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f
+#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0
+#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80
+#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7
+#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
+#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
+#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
+#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
+#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000
+#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11
+#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000
+#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12
+#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000
+#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13
+#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000
+#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14
+#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000
+#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15
+#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000
+#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16
+#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000
+#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17
+#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000
+#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19
+#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000
+#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a
+#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000
+#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b
+#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000
+#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c
+#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000
+#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d
+#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000
+#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e
+#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
+#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2
+#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1
+#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4
+#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2
+#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8
+#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10
+#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4
+#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40
+#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6
+#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80
+#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7
+#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100
+#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8
+#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200
+#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9
+#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400
+#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa
+#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800
+#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe
+#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000
+#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15
+#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000
+#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14
+#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
+#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
+#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
+#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
+#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
+#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
+#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000
+#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10
+#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
+#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
+#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1
+#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0
+#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2
+#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3
+#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10
+#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4
+#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20
+#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd
+#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000
+#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe
+#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000
+#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13
+#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000
+#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14
+#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000
+#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c
+#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff
+#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0
+#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000
+#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10
+#define SCLK_MIN_DIV__FRACV_MASK 0xfff
+#define SCLK_MIN_DIV__FRACV__SHIFT 0x0
+#define SCLK_MIN_DIV__INTV_MASK 0x7f000
+#define SCLK_MIN_DIV__INTV__SHIFT 0xc
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_MASK 0x40000000
+#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT__SHIFT 0x1e
+#define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH_MASK 0x3ff
+#define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0
+#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_MASK 0xffff
+#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD__SHIFT 0x0
+#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT_MASK 0xf0000
+#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT__SHIFT 0x10
+#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN_MASK 0x1
+#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN__SHIFT 0x0
+#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT_MASK 0x2
+#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT__SHIFT 0x1
+#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT_MASK 0x4
+#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT__SHIFT 0x2
+#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE_MASK 0x8
+#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE__SHIFT 0x3
+#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ_MASK 0x1
+#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ__SHIFT 0x0
+#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1
+#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0
+#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1
+#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0
+#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0
+#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1
+#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0
+#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1
+#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0
+#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0
+#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1
+#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0
+#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1
+#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0
+#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0
+#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1
+#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0
+#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1
+#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0
+#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0
+#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1
+#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0
+#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe
+#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1
+#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000
+#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11
+#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16
+#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff
+#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0
+#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff
+#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0
+#define ROM_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define ROM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define ROM_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define ROM_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define ROM_CNTL__SCK_OVERWRITE_MASK 0x2
+#define ROM_CNTL__SCK_OVERWRITE__SHIFT 0x1
+#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x4
+#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x2
+#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME_MASK 0xff00
+#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME__SHIFT 0x8
+#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME_MASK 0xff0000
+#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME__SHIFT 0x10
+#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0xf000000
+#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18
+#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK_MASK 0xf0000000
+#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK__SHIFT 0x1c
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0xffffff
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x1000000
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x2000000
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0xc000000
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a
+#define ROM_STATUS__ROM_BUSY_MASK 0x1
+#define ROM_STATUS__ROM_BUSY__SHIFT 0x0
+#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0xf
+#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0
+#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
+#define ROM_INDEX__ROM_INDEX_MASK 0xffffff
+#define ROM_INDEX__ROM_INDEX__SHIFT 0x0
+#define ROM_DATA__ROM_DATA_MASK 0xffffffff
+#define ROM_DATA__ROM_DATA__SHIFT 0x0
+#define ROM_START__ROM_START_MASK 0xffffff
+#define ROM_START__ROM_START__SHIFT 0x0
+#define ROM_SW_CNTL__DATA_SIZE_MASK 0xffff
+#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0
+#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x30000
+#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10
+#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x40000
+#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12
+#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x1
+#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0
+#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0xff
+#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0
+#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xffffff00
+#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8
+#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
+
+#endif /* SMU_7_1_1_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h
new file mode 100644
index 000000000000..933917479985
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h
@@ -0,0 +1,1273 @@
+/*
+ * SMU_7_1_2 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef SMU_7_1_2_D_H
+#define SMU_7_1_2_D_H
+
+#define mmGCK_SMC_IND_INDEX 0x80
+#define mmGCK0_GCK_SMC_IND_INDEX 0x80
+#define mmGCK1_GCK_SMC_IND_INDEX 0x82
+#define mmGCK2_GCK_SMC_IND_INDEX 0x84
+#define mmGCK3_GCK_SMC_IND_INDEX 0x86
+#define mmGCK_SMC_IND_DATA 0x81
+#define mmGCK0_GCK_SMC_IND_DATA 0x81
+#define mmGCK1_GCK_SMC_IND_DATA 0x83
+#define mmGCK2_GCK_SMC_IND_DATA 0x85
+#define mmGCK3_GCK_SMC_IND_DATA 0x87
+#define ixCG_DCLK_CNTL 0xc050009c
+#define ixCG_DCLK_STATUS 0xc05000a0
+#define ixCG_VCLK_CNTL 0xc05000a4
+#define ixCG_VCLK_STATUS 0xc05000a8
+#define ixCG_ECLK_CNTL 0xc05000ac
+#define ixCG_ECLK_STATUS 0xc05000b0
+#define ixCG_ACLK_CNTL 0xc05000dc
+#define ixGCK_DFS_BYPASS_CNTL 0xc0500118
+#define ixCG_SPLL_FUNC_CNTL 0xc0500140
+#define ixCG_SPLL_FUNC_CNTL_2 0xc0500144
+#define ixCG_SPLL_FUNC_CNTL_3 0xc0500148
+#define ixCG_SPLL_FUNC_CNTL_4 0xc050014c
+#define ixCG_SPLL_FUNC_CNTL_5 0xc0500150
+#define ixCG_SPLL_FUNC_CNTL_6 0xc0500154
+#define ixCG_SPLL_FUNC_CNTL_7 0xc0500158
+#define ixSPLL_CNTL_MODE 0xc0500160
+#define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164
+#define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168
+#define ixMPLL_BYPASSCLK_SEL 0xc050019c
+#define ixCG_CLKPIN_CNTL 0xc05001a0
+#define ixCG_CLKPIN_CNTL_2 0xc05001a4
+#define ixCG_CLKPIN_CNTL_DC 0xc0500204
+#define ixTHM_CLK_CNTL 0xc05001a8
+#define ixMISC_CLK_CTRL 0xc05001ac
+#define ixGCK_PLL_TEST_CNTL 0xc05001c0
+#define ixGCK_PLL_TEST_CNTL_2 0xc05001c4
+#define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8
+#define mmSMC_IND_INDEX 0x80
+#define mmSMC0_SMC_IND_INDEX 0x80
+#define mmSMC1_SMC_IND_INDEX 0x82
+#define mmSMC2_SMC_IND_INDEX 0x84
+#define mmSMC3_SMC_IND_INDEX 0x86
+#define mmSMC_IND_DATA 0x81
+#define mmSMC0_SMC_IND_DATA 0x81
+#define mmSMC1_SMC_IND_DATA 0x83
+#define mmSMC2_SMC_IND_DATA 0x85
+#define mmSMC3_SMC_IND_DATA 0x87
+#define mmSMC_IND_INDEX_0 0x80
+#define mmSMC_IND_DATA_0 0x81
+#define mmSMC_IND_INDEX_1 0x82
+#define mmSMC_IND_DATA_1 0x83
+#define mmSMC_IND_INDEX_2 0x84
+#define mmSMC_IND_DATA_2 0x85
+#define mmSMC_IND_INDEX_3 0x86
+#define mmSMC_IND_DATA_3 0x87
+#define mmSMC_IND_INDEX_4 0x88
+#define mmSMC_IND_DATA_4 0x89
+#define mmSMC_IND_INDEX_5 0x8a
+#define mmSMC_IND_DATA_5 0x8b
+#define mmSMC_IND_INDEX_6 0x8c
+#define mmSMC_IND_DATA_6 0x8d
+#define mmSMC_IND_INDEX_7 0x8e
+#define mmSMC_IND_DATA_7 0x8f
+#define mmSMC_IND_ACCESS_CNTL 0x92
+#define mmSMC_MESSAGE_0 0x94
+#define mmSMC_RESP_0 0x95
+#define mmSMC_MESSAGE_1 0x96
+#define mmSMC_RESP_1 0x97
+#define mmSMC_MESSAGE_2 0x98
+#define mmSMC_RESP_2 0x99
+#define mmSMC_MESSAGE_3 0x9a
+#define mmSMC_RESP_3 0x9b
+#define mmSMC_MESSAGE_4 0x9c
+#define mmSMC_RESP_4 0x9d
+#define mmSMC_MESSAGE_5 0x9e
+#define mmSMC_RESP_5 0x9f
+#define mmSMC_MESSAGE_6 0xa0
+#define mmSMC_RESP_6 0xa1
+#define mmSMC_MESSAGE_7 0xa2
+#define mmSMC_RESP_7 0xa3
+#define mmSMC_MSG_ARG_0 0xa4
+#define mmSMC_MSG_ARG_1 0xa5
+#define mmSMC_MSG_ARG_2 0xa6
+#define mmSMC_MSG_ARG_3 0xa7
+#define mmSMC_MSG_ARG_4 0xa8
+#define mmSMC_MSG_ARG_5 0xa9
+#define mmSMC_MSG_ARG_6 0xaa
+#define mmSMC_MSG_ARG_7 0xab
+#define mmSMC_MESSAGE_8 0xb5
+#define mmSMC_RESP_8 0xb6
+#define mmSMC_MESSAGE_9 0xb7
+#define mmSMC_RESP_9 0xb8
+#define mmSMC_MESSAGE_10 0xb9
+#define mmSMC_RESP_10 0xba
+#define mmSMC_MESSAGE_11 0xbb
+#define mmSMC_RESP_11 0xbc
+#define mmSMC_MSG_ARG_8 0xbd
+#define mmSMC_MSG_ARG_9 0xbe
+#define mmSMC_MSG_ARG_10 0xbf
+#define mmSMC_MSG_ARG_11 0x93
+#define ixSMC_SYSCON_RESET_CNTL 0x80000000
+#define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004
+#define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008
+#define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c
+#define ixSMC_SYSCON_MISC_CNTL 0x80000010
+#define ixSMC_SYSCON_MSG_ARG_0 0x80000068
+#define ixSMC_PC_C 0x80000370
+#define ixSMC_SCRATCH9 0x80000424
+#define mmGPIOPAD_SW_INT_STAT 0x180
+#define mmGPIOPAD_STRENGTH 0x181
+#define mmGPIOPAD_MASK 0x182
+#define mmGPIOPAD_A 0x183
+#define mmGPIOPAD_EN 0x184
+#define mmGPIOPAD_Y 0x185
+#define mmGPIOPAD_PINSTRAPS 0x186
+#define mmGPIOPAD_INT_STAT_EN 0x187
+#define mmGPIOPAD_INT_STAT 0x188
+#define mmGPIOPAD_INT_STAT_AK 0x189
+#define mmGPIOPAD_INT_EN 0x18a
+#define mmGPIOPAD_INT_TYPE 0x18b
+#define mmGPIOPAD_INT_POLARITY 0x18c
+#define mmGPIOPAD_EXTERN_TRIG_CNTL 0x18d
+#define mmGPIOPAD_RCVR_SEL 0x191
+#define mmGPIOPAD_PU_EN 0x192
+#define mmGPIOPAD_PD_EN 0x193
+#define mmCG_FPS_CNT 0x1b6
+#define mmSMU_IND_INDEX_0 0x1a6
+#define mmSMU_IND_DATA_0 0x1a7
+#define mmSMU_IND_INDEX_1 0x1a8
+#define mmSMU_IND_DATA_1 0x1a9
+#define mmSMU_IND_INDEX_2 0x1aa
+#define mmSMU_IND_DATA_2 0x1ab
+#define mmSMU_IND_INDEX_3 0x1ac
+#define mmSMU_IND_DATA_3 0x1ad
+#define mmSMU_IND_INDEX_4 0x1ae
+#define mmSMU_IND_DATA_4 0x1af
+#define mmSMU_IND_INDEX_5 0x1b0
+#define mmSMU_IND_DATA_5 0x1b1
+#define mmSMU_IND_INDEX_6 0x1b2
+#define mmSMU_IND_DATA_6 0x1b3
+#define mmSMU_IND_INDEX_7 0x1b4
+#define mmSMU_IND_DATA_7 0x1b5
+#define mmSMU_SMC_IND_INDEX 0x80
+#define mmSMU0_SMU_SMC_IND_INDEX 0x80
+#define mmSMU1_SMU_SMC_IND_INDEX 0x82
+#define mmSMU2_SMU_SMC_IND_INDEX 0x84
+#define mmSMU3_SMU_SMC_IND_INDEX 0x86
+#define mmSMU_SMC_IND_DATA 0x81
+#define mmSMU0_SMU_SMC_IND_DATA 0x81
+#define mmSMU1_SMU_SMC_IND_DATA 0x83
+#define mmSMU2_SMU_SMC_IND_DATA 0x85
+#define mmSMU3_SMU_SMC_IND_DATA 0x87
+#define ixRCU_UC_EVENTS 0xc0000004
+#define ixRCU_MISC_CTRL 0xc0000010
+#define ixRCU_VIRT_RESET_REQ 0xc0000024
+#define ixCC_RCU_FUSES 0xc00c0000
+#define ixCC_SMU_MISC_FUSES 0xc00c0004
+#define ixCC_SCLK_VID_FUSES 0xc00c0008
+#define ixCC_GIO_IOCCFG_FUSES 0xc00c000c
+#define ixCC_GIO_IOC_FUSES 0xc00c0010
+#define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c
+#define ixCC_TST_ID_STRAPS 0xc00c0020
+#define ixCC_FCTRL_FUSES 0xc00c0024
+#define ixCC_HARVEST_FUSES 0xc00c0028
+#define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020
+#define ixSMU_STATUS 0xe0003088
+#define ixSMU_FIRMWARE 0xe00030a4
+#define ixSMU_INPUT_DATA 0xe00030b8
+#define ixSMU_EFUSE_0 0xc0100000
+#define ixFIRMWARE_FLAGS 0x3f800
+#define ixTDC_STATUS 0x3f804
+#define ixTDC_MV_AVERAGE 0x3f808
+#define ixTDC_VRM_LIMIT 0x3f80c
+#define ixFEATURE_STATUS 0x3f810
+#define ixENTITY_TEMPERATURES_1 0x3f814
+#define ixDPM_TABLE_1 0x3f000
+#define ixDPM_TABLE_2 0x3f004
+#define ixDPM_TABLE_3 0x3f008
+#define ixDPM_TABLE_4 0x3f00c
+#define ixDPM_TABLE_5 0x3f010
+#define ixDPM_TABLE_6 0x3f014
+#define ixDPM_TABLE_7 0x3f018
+#define ixDPM_TABLE_8 0x3f01c
+#define ixDPM_TABLE_9 0x3f020
+#define ixDPM_TABLE_10 0x3f024
+#define ixDPM_TABLE_11 0x3f028
+#define ixDPM_TABLE_12 0x3f02c
+#define ixDPM_TABLE_13 0x3f030
+#define ixDPM_TABLE_14 0x3f034
+#define ixDPM_TABLE_15 0x3f038
+#define ixDPM_TABLE_16 0x3f03c
+#define ixDPM_TABLE_17 0x3f040
+#define ixDPM_TABLE_18 0x3f044
+#define ixDPM_TABLE_19 0x3f048
+#define ixDPM_TABLE_20 0x3f04c
+#define ixDPM_TABLE_21 0x3f050
+#define ixDPM_TABLE_22 0x3f054
+#define ixDPM_TABLE_23 0x3f058
+#define ixDPM_TABLE_24 0x3f05c
+#define ixDPM_TABLE_25 0x3f060
+#define ixDPM_TABLE_26 0x3f064
+#define ixDPM_TABLE_27 0x3f068
+#define ixDPM_TABLE_28 0x3f06c
+#define ixDPM_TABLE_29 0x3f070
+#define ixDPM_TABLE_30 0x3f074
+#define ixDPM_TABLE_31 0x3f078
+#define ixDPM_TABLE_32 0x3f07c
+#define ixDPM_TABLE_33 0x3f080
+#define ixDPM_TABLE_34 0x3f084
+#define ixDPM_TABLE_35 0x3f088
+#define ixDPM_TABLE_36 0x3f08c
+#define ixDPM_TABLE_37 0x3f090
+#define ixDPM_TABLE_38 0x3f094
+#define ixDPM_TABLE_39 0x3f098
+#define ixDPM_TABLE_40 0x3f09c
+#define ixDPM_TABLE_41 0x3f0a0
+#define ixDPM_TABLE_42 0x3f0a4
+#define ixDPM_TABLE_43 0x3f0a8
+#define ixDPM_TABLE_44 0x3f0ac
+#define ixDPM_TABLE_45 0x3f0b0
+#define ixDPM_TABLE_46 0x3f0b4
+#define ixDPM_TABLE_47 0x3f0b8
+#define ixDPM_TABLE_48 0x3f0bc
+#define ixDPM_TABLE_49 0x3f0c0
+#define ixDPM_TABLE_50 0x3f0c4
+#define ixDPM_TABLE_51 0x3f0c8
+#define ixDPM_TABLE_52 0x3f0cc
+#define ixDPM_TABLE_53 0x3f0d0
+#define ixDPM_TABLE_54 0x3f0d4
+#define ixDPM_TABLE_55 0x3f0d8
+#define ixDPM_TABLE_56 0x3f0dc
+#define ixDPM_TABLE_57 0x3f0e0
+#define ixDPM_TABLE_58 0x3f0e4
+#define ixDPM_TABLE_59 0x3f0e8
+#define ixDPM_TABLE_60 0x3f0ec
+#define ixDPM_TABLE_61 0x3f0f0
+#define ixDPM_TABLE_62 0x3f0f4
+#define ixDPM_TABLE_63 0x3f0f8
+#define ixDPM_TABLE_64 0x3f0fc
+#define ixDPM_TABLE_65 0x3f100
+#define ixDPM_TABLE_66 0x3f104
+#define ixDPM_TABLE_67 0x3f108
+#define ixDPM_TABLE_68 0x3f10c
+#define ixDPM_TABLE_69 0x3f110
+#define ixDPM_TABLE_70 0x3f114
+#define ixDPM_TABLE_71 0x3f118
+#define ixDPM_TABLE_72 0x3f11c
+#define ixDPM_TABLE_73 0x3f120
+#define ixDPM_TABLE_74 0x3f124
+#define ixDPM_TABLE_75 0x3f128
+#define ixDPM_TABLE_76 0x3f12c
+#define ixDPM_TABLE_77 0x3f130
+#define ixDPM_TABLE_78 0x3f134
+#define ixDPM_TABLE_79 0x3f138
+#define ixDPM_TABLE_80 0x3f13c
+#define ixDPM_TABLE_81 0x3f140
+#define ixDPM_TABLE_82 0x3f144
+#define ixDPM_TABLE_83 0x3f148
+#define ixDPM_TABLE_84 0x3f14c
+#define ixDPM_TABLE_85 0x3f150
+#define ixDPM_TABLE_86 0x3f154
+#define ixDPM_TABLE_87 0x3f158
+#define ixDPM_TABLE_88 0x3f15c
+#define ixDPM_TABLE_89 0x3f160
+#define ixDPM_TABLE_90 0x3f164
+#define ixDPM_TABLE_91 0x3f168
+#define ixDPM_TABLE_92 0x3f16c
+#define ixDPM_TABLE_93 0x3f170
+#define ixDPM_TABLE_94 0x3f174
+#define ixDPM_TABLE_95 0x3f178
+#define ixDPM_TABLE_96 0x3f17c
+#define ixDPM_TABLE_97 0x3f180
+#define ixDPM_TABLE_98 0x3f184
+#define ixDPM_TABLE_99 0x3f188
+#define ixDPM_TABLE_100 0x3f18c
+#define ixDPM_TABLE_101 0x3f190
+#define ixDPM_TABLE_102 0x3f194
+#define ixDPM_TABLE_103 0x3f198
+#define ixDPM_TABLE_104 0x3f19c
+#define ixDPM_TABLE_105 0x3f1a0
+#define ixDPM_TABLE_106 0x3f1a4
+#define ixDPM_TABLE_107 0x3f1a8
+#define ixDPM_TABLE_108 0x3f1ac
+#define ixDPM_TABLE_109 0x3f1b0
+#define ixDPM_TABLE_110 0x3f1b4
+#define ixDPM_TABLE_111 0x3f1b8
+#define ixDPM_TABLE_112 0x3f1bc
+#define ixDPM_TABLE_113 0x3f1c0
+#define ixDPM_TABLE_114 0x3f1c4
+#define ixDPM_TABLE_115 0x3f1c8
+#define ixDPM_TABLE_116 0x3f1cc
+#define ixDPM_TABLE_117 0x3f1d0
+#define ixDPM_TABLE_118 0x3f1d4
+#define ixDPM_TABLE_119 0x3f1d8
+#define ixDPM_TABLE_120 0x3f1dc
+#define ixDPM_TABLE_121 0x3f1e0
+#define ixDPM_TABLE_122 0x3f1e4
+#define ixDPM_TABLE_123 0x3f1e8
+#define ixDPM_TABLE_124 0x3f1ec
+#define ixDPM_TABLE_125 0x3f1f0
+#define ixDPM_TABLE_126 0x3f1f4
+#define ixDPM_TABLE_127 0x3f1f8
+#define ixDPM_TABLE_128 0x3f1fc
+#define ixDPM_TABLE_129 0x3f200
+#define ixDPM_TABLE_130 0x3f204
+#define ixDPM_TABLE_131 0x3f208
+#define ixDPM_TABLE_132 0x3f20c
+#define ixDPM_TABLE_133 0x3f210
+#define ixDPM_TABLE_134 0x3f214
+#define ixDPM_TABLE_135 0x3f218
+#define ixDPM_TABLE_136 0x3f21c
+#define ixDPM_TABLE_137 0x3f220
+#define ixDPM_TABLE_138 0x3f224
+#define ixDPM_TABLE_139 0x3f228
+#define ixDPM_TABLE_140 0x3f22c
+#define ixDPM_TABLE_141 0x3f230
+#define ixDPM_TABLE_142 0x3f234
+#define ixDPM_TABLE_143 0x3f238
+#define ixDPM_TABLE_144 0x3f23c
+#define ixDPM_TABLE_145 0x3f240
+#define ixDPM_TABLE_146 0x3f244
+#define ixDPM_TABLE_147 0x3f248
+#define ixDPM_TABLE_148 0x3f24c
+#define ixDPM_TABLE_149 0x3f250
+#define ixDPM_TABLE_150 0x3f254
+#define ixDPM_TABLE_151 0x3f258
+#define ixDPM_TABLE_152 0x3f25c
+#define ixDPM_TABLE_153 0x3f260
+#define ixDPM_TABLE_154 0x3f264
+#define ixDPM_TABLE_155 0x3f268
+#define ixDPM_TABLE_156 0x3f26c
+#define ixDPM_TABLE_157 0x3f270
+#define ixDPM_TABLE_158 0x3f274
+#define ixDPM_TABLE_159 0x3f278
+#define ixDPM_TABLE_160 0x3f27c
+#define ixDPM_TABLE_161 0x3f280
+#define ixDPM_TABLE_162 0x3f284
+#define ixDPM_TABLE_163 0x3f288
+#define ixDPM_TABLE_164 0x3f28c
+#define ixDPM_TABLE_165 0x3f290
+#define ixDPM_TABLE_166 0x3f294
+#define ixDPM_TABLE_167 0x3f298
+#define ixDPM_TABLE_168 0x3f29c
+#define ixDPM_TABLE_169 0x3f2a0
+#define ixDPM_TABLE_170 0x3f2a4
+#define ixDPM_TABLE_171 0x3f2a8
+#define ixDPM_TABLE_172 0x3f2ac
+#define ixDPM_TABLE_173 0x3f2b0
+#define ixDPM_TABLE_174 0x3f2b4
+#define ixDPM_TABLE_175 0x3f2b8
+#define ixDPM_TABLE_176 0x3f2bc
+#define ixDPM_TABLE_177 0x3f2c0
+#define ixDPM_TABLE_178 0x3f2c4
+#define ixDPM_TABLE_179 0x3f2c8
+#define ixDPM_TABLE_180 0x3f2cc
+#define ixDPM_TABLE_181 0x3f2d0
+#define ixDPM_TABLE_182 0x3f2d4
+#define ixDPM_TABLE_183 0x3f2d8
+#define ixDPM_TABLE_184 0x3f2dc
+#define ixDPM_TABLE_185 0x3f2e0
+#define ixDPM_TABLE_186 0x3f2e4
+#define ixDPM_TABLE_187 0x3f2e8
+#define ixDPM_TABLE_188 0x3f2ec
+#define ixDPM_TABLE_189 0x3f2f0
+#define ixDPM_TABLE_190 0x3f2f4
+#define ixDPM_TABLE_191 0x3f2f8
+#define ixDPM_TABLE_192 0x3f2fc
+#define ixDPM_TABLE_193 0x3f300
+#define ixDPM_TABLE_194 0x3f304
+#define ixDPM_TABLE_195 0x3f308
+#define ixDPM_TABLE_196 0x3f30c
+#define ixDPM_TABLE_197 0x3f310
+#define ixDPM_TABLE_198 0x3f314
+#define ixDPM_TABLE_199 0x3f318
+#define ixDPM_TABLE_200 0x3f31c
+#define ixDPM_TABLE_201 0x3f320
+#define ixDPM_TABLE_202 0x3f324
+#define ixDPM_TABLE_203 0x3f328
+#define ixDPM_TABLE_204 0x3f32c
+#define ixDPM_TABLE_205 0x3f330
+#define ixDPM_TABLE_206 0x3f334
+#define ixDPM_TABLE_207 0x3f338
+#define ixDPM_TABLE_208 0x3f33c
+#define ixDPM_TABLE_209 0x3f340
+#define ixDPM_TABLE_210 0x3f344
+#define ixDPM_TABLE_211 0x3f348
+#define ixDPM_TABLE_212 0x3f34c
+#define ixDPM_TABLE_213 0x3f350
+#define ixDPM_TABLE_214 0x3f354
+#define ixDPM_TABLE_215 0x3f358
+#define ixDPM_TABLE_216 0x3f35c
+#define ixDPM_TABLE_217 0x3f360
+#define ixDPM_TABLE_218 0x3f364
+#define ixDPM_TABLE_219 0x3f368
+#define ixDPM_TABLE_220 0x3f36c
+#define ixDPM_TABLE_221 0x3f370
+#define ixDPM_TABLE_222 0x3f374
+#define ixDPM_TABLE_223 0x3f378
+#define ixDPM_TABLE_224 0x3f37c
+#define ixDPM_TABLE_225 0x3f380
+#define ixDPM_TABLE_226 0x3f384
+#define ixDPM_TABLE_227 0x3f388
+#define ixDPM_TABLE_228 0x3f38c
+#define ixDPM_TABLE_229 0x3f390
+#define ixDPM_TABLE_230 0x3f394
+#define ixDPM_TABLE_231 0x3f398
+#define ixDPM_TABLE_232 0x3f39c
+#define ixDPM_TABLE_233 0x3f3a0
+#define ixDPM_TABLE_234 0x3f3a4
+#define ixDPM_TABLE_235 0x3f3a8
+#define ixDPM_TABLE_236 0x3f3ac
+#define ixDPM_TABLE_237 0x3f3b0
+#define ixDPM_TABLE_238 0x3f3b4
+#define ixDPM_TABLE_239 0x3f3b8
+#define ixDPM_TABLE_240 0x3f3bc
+#define ixDPM_TABLE_241 0x3f3c0
+#define ixDPM_TABLE_242 0x3f3c4
+#define ixDPM_TABLE_243 0x3f3c8
+#define ixDPM_TABLE_244 0x3f3cc
+#define ixDPM_TABLE_245 0x3f3d0
+#define ixDPM_TABLE_246 0x3f3d4
+#define ixDPM_TABLE_247 0x3f3d8
+#define ixDPM_TABLE_248 0x3f3dc
+#define ixDPM_TABLE_249 0x3f3e0
+#define ixDPM_TABLE_250 0x3f3e4
+#define ixDPM_TABLE_251 0x3f3e8
+#define ixDPM_TABLE_252 0x3f3ec
+#define ixDPM_TABLE_253 0x3f3f0
+#define ixDPM_TABLE_254 0x3f3f4
+#define ixDPM_TABLE_255 0x3f3f8
+#define ixDPM_TABLE_256 0x3f3fc
+#define ixDPM_TABLE_257 0x3f400
+#define ixDPM_TABLE_258 0x3f404
+#define ixDPM_TABLE_259 0x3f408
+#define ixDPM_TABLE_260 0x3f40c
+#define ixDPM_TABLE_261 0x3f410
+#define ixDPM_TABLE_262 0x3f414
+#define ixDPM_TABLE_263 0x3f418
+#define ixDPM_TABLE_264 0x3f41c
+#define ixDPM_TABLE_265 0x3f420
+#define ixDPM_TABLE_266 0x3f424
+#define ixDPM_TABLE_267 0x3f428
+#define ixDPM_TABLE_268 0x3f42c
+#define ixDPM_TABLE_269 0x3f430
+#define ixDPM_TABLE_270 0x3f434
+#define ixDPM_TABLE_271 0x3f438
+#define ixDPM_TABLE_272 0x3f43c
+#define ixDPM_TABLE_273 0x3f440
+#define ixDPM_TABLE_274 0x3f444
+#define ixDPM_TABLE_275 0x3f448
+#define ixDPM_TABLE_276 0x3f44c
+#define ixDPM_TABLE_277 0x3f450
+#define ixDPM_TABLE_278 0x3f454
+#define ixDPM_TABLE_279 0x3f458
+#define ixDPM_TABLE_280 0x3f45c
+#define ixDPM_TABLE_281 0x3f460
+#define ixDPM_TABLE_282 0x3f464
+#define ixDPM_TABLE_283 0x3f468
+#define ixDPM_TABLE_284 0x3f46c
+#define ixDPM_TABLE_285 0x3f470
+#define ixDPM_TABLE_286 0x3f474
+#define ixDPM_TABLE_287 0x3f478
+#define ixDPM_TABLE_288 0x3f47c
+#define ixDPM_TABLE_289 0x3f480
+#define ixDPM_TABLE_290 0x3f484
+#define ixDPM_TABLE_291 0x3f488
+#define ixDPM_TABLE_292 0x3f48c
+#define ixDPM_TABLE_293 0x3f490
+#define ixDPM_TABLE_294 0x3f494
+#define ixDPM_TABLE_295 0x3f498
+#define ixDPM_TABLE_296 0x3f49c
+#define ixDPM_TABLE_297 0x3f4a0
+#define ixDPM_TABLE_298 0x3f4a4
+#define ixDPM_TABLE_299 0x3f4a8
+#define ixDPM_TABLE_300 0x3f4ac
+#define ixDPM_TABLE_301 0x3f4b0
+#define ixDPM_TABLE_302 0x3f4b4
+#define ixDPM_TABLE_303 0x3f4b8
+#define ixDPM_TABLE_304 0x3f4bc
+#define ixDPM_TABLE_305 0x3f4c0
+#define ixDPM_TABLE_306 0x3f4c4
+#define ixDPM_TABLE_307 0x3f4c8
+#define ixDPM_TABLE_308 0x3f4cc
+#define ixDPM_TABLE_309 0x3f4d0
+#define ixDPM_TABLE_310 0x3f4d4
+#define ixDPM_TABLE_311 0x3f4d8
+#define ixDPM_TABLE_312 0x3f4dc
+#define ixDPM_TABLE_313 0x3f4e0
+#define ixDPM_TABLE_314 0x3f4e4
+#define ixDPM_TABLE_315 0x3f4e8
+#define ixDPM_TABLE_316 0x3f4ec
+#define ixDPM_TABLE_317 0x3f4f0
+#define ixDPM_TABLE_318 0x3f4f4
+#define ixDPM_TABLE_319 0x3f4f8
+#define ixDPM_TABLE_320 0x3f4fc
+#define ixDPM_TABLE_321 0x3f500
+#define ixDPM_TABLE_322 0x3f504
+#define ixDPM_TABLE_323 0x3f508
+#define ixDPM_TABLE_324 0x3f50c
+#define ixDPM_TABLE_325 0x3f510
+#define ixDPM_TABLE_326 0x3f514
+#define ixDPM_TABLE_327 0x3f518
+#define ixDPM_TABLE_328 0x3f51c
+#define ixDPM_TABLE_329 0x3f520
+#define ixDPM_TABLE_330 0x3f524
+#define ixDPM_TABLE_331 0x3f528
+#define ixDPM_TABLE_332 0x3f52c
+#define ixDPM_TABLE_333 0x3f530
+#define ixDPM_TABLE_334 0x3f534
+#define ixDPM_TABLE_335 0x3f538
+#define ixDPM_TABLE_336 0x3f53c
+#define ixDPM_TABLE_337 0x3f540
+#define ixDPM_TABLE_338 0x3f544
+#define ixDPM_TABLE_339 0x3f548
+#define ixDPM_TABLE_340 0x3f54c
+#define ixDPM_TABLE_341 0x3f550
+#define ixDPM_TABLE_342 0x3f554
+#define ixDPM_TABLE_343 0x3f558
+#define ixDPM_TABLE_344 0x3f55c
+#define ixDPM_TABLE_345 0x3f560
+#define ixDPM_TABLE_346 0x3f564
+#define ixDPM_TABLE_347 0x3f568
+#define ixDPM_TABLE_348 0x3f56c
+#define ixDPM_TABLE_349 0x3f570
+#define ixDPM_TABLE_350 0x3f574
+#define ixDPM_TABLE_351 0x3f578
+#define ixDPM_TABLE_352 0x3f57c
+#define ixDPM_TABLE_353 0x3f580
+#define ixDPM_TABLE_354 0x3f584
+#define ixDPM_TABLE_355 0x3f588
+#define ixDPM_TABLE_356 0x3f58c
+#define ixDPM_TABLE_357 0x3f590
+#define ixDPM_TABLE_358 0x3f594
+#define ixDPM_TABLE_359 0x3f598
+#define ixDPM_TABLE_360 0x3f59c
+#define ixDPM_TABLE_361 0x3f5a0
+#define ixDPM_TABLE_362 0x3f5a4
+#define ixDPM_TABLE_363 0x3f5a8
+#define ixDPM_TABLE_364 0x3f5ac
+#define ixDPM_TABLE_365 0x3f5b0
+#define ixDPM_TABLE_366 0x3f5b4
+#define ixDPM_TABLE_367 0x3f5b8
+#define ixDPM_TABLE_368 0x3f5bc
+#define ixDPM_TABLE_369 0x3f5c0
+#define ixDPM_TABLE_370 0x3f5c4
+#define ixDPM_TABLE_371 0x3f5c8
+#define ixDPM_TABLE_372 0x3f5cc
+#define ixDPM_TABLE_373 0x3f5d0
+#define ixDPM_TABLE_374 0x3f5d4
+#define ixDPM_TABLE_375 0x3f5d8
+#define ixDPM_TABLE_376 0x3f5dc
+#define ixDPM_TABLE_377 0x3f5e0
+#define ixDPM_TABLE_378 0x3f5e4
+#define ixDPM_TABLE_379 0x3f5e8
+#define ixDPM_TABLE_380 0x3f5ec
+#define ixDPM_TABLE_381 0x3f5f0
+#define ixDPM_TABLE_382 0x3f5f4
+#define ixDPM_TABLE_383 0x3f5f8
+#define ixDPM_TABLE_384 0x3f5fc
+#define ixDPM_TABLE_385 0x3f600
+#define ixDPM_TABLE_386 0x3f604
+#define ixDPM_TABLE_387 0x3f608
+#define ixDPM_TABLE_388 0x3f60c
+#define ixDPM_TABLE_389 0x3f610
+#define ixDPM_TABLE_390 0x3f614
+#define ixDPM_TABLE_391 0x3f618
+#define ixDPM_TABLE_392 0x3f61c
+#define ixDPM_TABLE_393 0x3f620
+#define ixDPM_TABLE_394 0x3f624
+#define ixDPM_TABLE_395 0x3f628
+#define ixDPM_TABLE_396 0x3f62c
+#define ixDPM_TABLE_397 0x3f630
+#define ixDPM_TABLE_398 0x3f634
+#define ixDPM_TABLE_399 0x3f638
+#define ixDPM_TABLE_400 0x3f63c
+#define ixDPM_TABLE_401 0x3f640
+#define ixDPM_TABLE_402 0x3f644
+#define ixDPM_TABLE_403 0x3f648
+#define ixDPM_TABLE_404 0x3f64c
+#define ixDPM_TABLE_405 0x3f650
+#define ixDPM_TABLE_406 0x3f654
+#define ixDPM_TABLE_407 0x3f658
+#define ixDPM_TABLE_408 0x3f65c
+#define ixDPM_TABLE_409 0x3f660
+#define ixDPM_TABLE_410 0x3f664
+#define ixDPM_TABLE_411 0x3f668
+#define ixDPM_TABLE_412 0x3f66c
+#define ixDPM_TABLE_413 0x3f670
+#define ixDPM_TABLE_414 0x3f674
+#define ixDPM_TABLE_415 0x3f678
+#define ixDPM_TABLE_416 0x3f67c
+#define ixDPM_TABLE_417 0x3f680
+#define ixDPM_TABLE_418 0x3f684
+#define ixDPM_TABLE_419 0x3f688
+#define ixDPM_TABLE_420 0x3f68c
+#define ixDPM_TABLE_421 0x3f690
+#define ixDPM_TABLE_422 0x3f694
+#define ixDPM_TABLE_423 0x3f698
+#define ixDPM_TABLE_424 0x3f69c
+#define ixDPM_TABLE_425 0x3f6a0
+#define ixDPM_TABLE_426 0x3f6a4
+#define ixDPM_TABLE_427 0x3f6a8
+#define ixDPM_TABLE_428 0x3f6ac
+#define ixDPM_TABLE_429 0x3f6b0
+#define ixDPM_TABLE_430 0x3f6b4
+#define ixDPM_TABLE_431 0x3f6b8
+#define ixDPM_TABLE_432 0x3f6bc
+#define ixDPM_TABLE_433 0x3f6c0
+#define ixDPM_TABLE_434 0x3f6c4
+#define ixDPM_TABLE_435 0x3f6c8
+#define ixDPM_TABLE_436 0x3f6cc
+#define ixDPM_TABLE_437 0x3f6d0
+#define ixDPM_TABLE_438 0x3f6d4
+#define ixDPM_TABLE_439 0x3f6d8
+#define ixDPM_TABLE_440 0x3f6dc
+#define ixDPM_TABLE_441 0x3f6e0
+#define ixDPM_TABLE_442 0x3f6e4
+#define ixDPM_TABLE_443 0x3f6e8
+#define ixDPM_TABLE_444 0x3f6ec
+#define ixDPM_TABLE_445 0x3f6f0
+#define ixDPM_TABLE_446 0x3f6f4
+#define ixDPM_TABLE_447 0x3f6f8
+#define ixDPM_TABLE_448 0x3f6fc
+#define ixDPM_TABLE_449 0x3f700
+#define ixDPM_TABLE_450 0x3f704
+#define ixDPM_TABLE_451 0x3f708
+#define ixDPM_TABLE_452 0x3f70c
+#define ixDPM_TABLE_453 0x3f710
+#define ixDPM_TABLE_454 0x3f714
+#define ixDPM_TABLE_455 0x3f718
+#define ixDPM_TABLE_456 0x3f71c
+#define ixDPM_TABLE_457 0x3f720
+#define ixDPM_TABLE_458 0x3f724
+#define ixDPM_TABLE_459 0x3f728
+#define ixDPM_TABLE_460 0x3f72c
+#define ixDPM_TABLE_461 0x3f730
+#define ixDPM_TABLE_462 0x3f734
+#define ixDPM_TABLE_463 0x3f738
+#define ixDPM_TABLE_464 0x3f73c
+#define ixDPM_TABLE_465 0x3f740
+#define ixDPM_TABLE_466 0x3f744
+#define ixDPM_TABLE_467 0x3f748
+#define ixDPM_TABLE_468 0x3f74c
+#define ixDPM_TABLE_469 0x3f750
+#define ixDPM_TABLE_470 0x3f754
+#define ixDPM_TABLE_471 0x3f758
+#define ixDPM_TABLE_472 0x3f75c
+#define ixDPM_TABLE_473 0x3f760
+#define ixDPM_TABLE_474 0x3f764
+#define ixDPM_TABLE_475 0x3f768
+#define ixDPM_TABLE_476 0x3f76c
+#define ixDPM_TABLE_477 0x3f770
+#define ixDPM_TABLE_478 0x3f774
+#define ixDPM_TABLE_479 0x3f778
+#define ixDPM_TABLE_480 0x3f77c
+#define ixDPM_TABLE_481 0x3f780
+#define ixDPM_TABLE_482 0x3f784
+#define ixDPM_TABLE_483 0x3f788
+#define ixDPM_TABLE_484 0x3f78c
+#define ixDPM_TABLE_485 0x3f790
+#define ixDPM_TABLE_486 0x3f794
+#define ixDPM_TABLE_487 0x3f798
+#define ixDPM_TABLE_488 0x3f79c
+#define ixDPM_TABLE_489 0x3f7a0
+#define ixDPM_TABLE_490 0x3f7a4
+#define ixMCARB_DRAM_TIMING_TABLE_1 0x3f900
+#define ixMCARB_DRAM_TIMING_TABLE_2 0x3f904
+#define ixMCARB_DRAM_TIMING_TABLE_3 0x3f908
+#define ixMCARB_DRAM_TIMING_TABLE_4 0x3f90c
+#define ixMCARB_DRAM_TIMING_TABLE_5 0x3f910
+#define ixMCARB_DRAM_TIMING_TABLE_6 0x3f914
+#define ixMCARB_DRAM_TIMING_TABLE_7 0x3f918
+#define ixMCARB_DRAM_TIMING_TABLE_8 0x3f91c
+#define ixMCARB_DRAM_TIMING_TABLE_9 0x3f920
+#define ixMCARB_DRAM_TIMING_TABLE_10 0x3f924
+#define ixMCARB_DRAM_TIMING_TABLE_11 0x3f928
+#define ixMCARB_DRAM_TIMING_TABLE_12 0x3f92c
+#define ixMCARB_DRAM_TIMING_TABLE_13 0x3f930
+#define ixMCARB_DRAM_TIMING_TABLE_14 0x3f934
+#define ixMCARB_DRAM_TIMING_TABLE_15 0x3f938
+#define ixMCARB_DRAM_TIMING_TABLE_16 0x3f93c
+#define ixMCARB_DRAM_TIMING_TABLE_17 0x3f940
+#define ixMCARB_DRAM_TIMING_TABLE_18 0x3f944
+#define ixMCARB_DRAM_TIMING_TABLE_19 0x3f948
+#define ixMCARB_DRAM_TIMING_TABLE_20 0x3f94c
+#define ixMCARB_DRAM_TIMING_TABLE_21 0x3f950
+#define ixMCARB_DRAM_TIMING_TABLE_22 0x3f954
+#define ixMCARB_DRAM_TIMING_TABLE_23 0x3f958
+#define ixMCARB_DRAM_TIMING_TABLE_24 0x3f95c
+#define ixMCARB_DRAM_TIMING_TABLE_25 0x3f960
+#define ixMCARB_DRAM_TIMING_TABLE_26 0x3f964
+#define ixMCARB_DRAM_TIMING_TABLE_27 0x3f968
+#define ixMCARB_DRAM_TIMING_TABLE_28 0x3f96c
+#define ixMCARB_DRAM_TIMING_TABLE_29 0x3f970
+#define ixMCARB_DRAM_TIMING_TABLE_30 0x3f974
+#define ixMCARB_DRAM_TIMING_TABLE_31 0x3f978
+#define ixMCARB_DRAM_TIMING_TABLE_32 0x3f97c
+#define ixMCARB_DRAM_TIMING_TABLE_33 0x3f980
+#define ixMCARB_DRAM_TIMING_TABLE_34 0x3f984
+#define ixMCARB_DRAM_TIMING_TABLE_35 0x3f988
+#define ixMCARB_DRAM_TIMING_TABLE_36 0x3f98c
+#define ixMCARB_DRAM_TIMING_TABLE_37 0x3f990
+#define ixMCARB_DRAM_TIMING_TABLE_38 0x3f994
+#define ixMCARB_DRAM_TIMING_TABLE_39 0x3f998
+#define ixMCARB_DRAM_TIMING_TABLE_40 0x3f99c
+#define ixMCARB_DRAM_TIMING_TABLE_41 0x3f9a0
+#define ixMCARB_DRAM_TIMING_TABLE_42 0x3f9a4
+#define ixMCARB_DRAM_TIMING_TABLE_43 0x3f9a8
+#define ixMCARB_DRAM_TIMING_TABLE_44 0x3f9ac
+#define ixMCARB_DRAM_TIMING_TABLE_45 0x3f9b0
+#define ixMCARB_DRAM_TIMING_TABLE_46 0x3f9b4
+#define ixMCARB_DRAM_TIMING_TABLE_47 0x3f9b8
+#define ixMCARB_DRAM_TIMING_TABLE_48 0x3f9bc
+#define ixMCARB_DRAM_TIMING_TABLE_49 0x3f9c0
+#define ixMCARB_DRAM_TIMING_TABLE_50 0x3f9c4
+#define ixMCARB_DRAM_TIMING_TABLE_51 0x3f9c8
+#define ixMCARB_DRAM_TIMING_TABLE_52 0x3f9cc
+#define ixMCARB_DRAM_TIMING_TABLE_53 0x3f9d0
+#define ixMCARB_DRAM_TIMING_TABLE_54 0x3f9d4
+#define ixMCARB_DRAM_TIMING_TABLE_55 0x3f9d8
+#define ixMCARB_DRAM_TIMING_TABLE_56 0x3f9dc
+#define ixMCARB_DRAM_TIMING_TABLE_57 0x3f9e0
+#define ixMCARB_DRAM_TIMING_TABLE_58 0x3f9e4
+#define ixMCARB_DRAM_TIMING_TABLE_59 0x3f9e8
+#define ixMCARB_DRAM_TIMING_TABLE_60 0x3f9ec
+#define ixMCARB_DRAM_TIMING_TABLE_61 0x3f9f0
+#define ixMCARB_DRAM_TIMING_TABLE_62 0x3f9f4
+#define ixMCARB_DRAM_TIMING_TABLE_63 0x3f9f8
+#define ixMCARB_DRAM_TIMING_TABLE_64 0x3f9fc
+#define ixMCARB_DRAM_TIMING_TABLE_65 0x3fa00
+#define ixMCARB_DRAM_TIMING_TABLE_66 0x3fa04
+#define ixMCARB_DRAM_TIMING_TABLE_67 0x3fa08
+#define ixMCARB_DRAM_TIMING_TABLE_68 0x3fa0c
+#define ixMCARB_DRAM_TIMING_TABLE_69 0x3fa10
+#define ixMCARB_DRAM_TIMING_TABLE_70 0x3fa14
+#define ixMCARB_DRAM_TIMING_TABLE_71 0x3fa18
+#define ixMCARB_DRAM_TIMING_TABLE_72 0x3fa1c
+#define ixMCARB_DRAM_TIMING_TABLE_73 0x3fa20
+#define ixMCARB_DRAM_TIMING_TABLE_74 0x3fa24
+#define ixMCARB_DRAM_TIMING_TABLE_75 0x3fa28
+#define ixMCARB_DRAM_TIMING_TABLE_76 0x3fa2c
+#define ixMCARB_DRAM_TIMING_TABLE_77 0x3fa30
+#define ixMCARB_DRAM_TIMING_TABLE_78 0x3fa34
+#define ixMCARB_DRAM_TIMING_TABLE_79 0x3fa38
+#define ixMCARB_DRAM_TIMING_TABLE_80 0x3fa3c
+#define ixMCARB_DRAM_TIMING_TABLE_81 0x3fa40
+#define ixMCARB_DRAM_TIMING_TABLE_82 0x3fa44
+#define ixMCARB_DRAM_TIMING_TABLE_83 0x3fa48
+#define ixMCARB_DRAM_TIMING_TABLE_84 0x3fa4c
+#define ixMCARB_DRAM_TIMING_TABLE_85 0x3fa50
+#define ixMCARB_DRAM_TIMING_TABLE_86 0x3fa54
+#define ixMCARB_DRAM_TIMING_TABLE_87 0x3fa58
+#define ixMCARB_DRAM_TIMING_TABLE_88 0x3fa5c
+#define ixMCARB_DRAM_TIMING_TABLE_89 0x3fa60
+#define ixMCARB_DRAM_TIMING_TABLE_90 0x3fa64
+#define ixMCARB_DRAM_TIMING_TABLE_91 0x3fa68
+#define ixMCARB_DRAM_TIMING_TABLE_92 0x3fa6c
+#define ixMCARB_DRAM_TIMING_TABLE_93 0x3fa70
+#define ixMCARB_DRAM_TIMING_TABLE_94 0x3fa74
+#define ixMCARB_DRAM_TIMING_TABLE_95 0x3fa78
+#define ixMCARB_DRAM_TIMING_TABLE_96 0x3fa7c
+#define ixMC_REGISTERS_TABLE_1 0x3fa80
+#define ixMC_REGISTERS_TABLE_2 0x3fa84
+#define ixMC_REGISTERS_TABLE_3 0x3fa88
+#define ixMC_REGISTERS_TABLE_4 0x3fa8c
+#define ixMC_REGISTERS_TABLE_5 0x3fa90
+#define ixMC_REGISTERS_TABLE_6 0x3fa94
+#define ixMC_REGISTERS_TABLE_7 0x3fa98
+#define ixMC_REGISTERS_TABLE_8 0x3fa9c
+#define ixMC_REGISTERS_TABLE_9 0x3faa0
+#define ixMC_REGISTERS_TABLE_10 0x3faa4
+#define ixMC_REGISTERS_TABLE_11 0x3faa8
+#define ixMC_REGISTERS_TABLE_12 0x3faac
+#define ixMC_REGISTERS_TABLE_13 0x3fab0
+#define ixMC_REGISTERS_TABLE_14 0x3fab4
+#define ixMC_REGISTERS_TABLE_15 0x3fab8
+#define ixMC_REGISTERS_TABLE_16 0x3fabc
+#define ixMC_REGISTERS_TABLE_17 0x3fac0
+#define ixMC_REGISTERS_TABLE_18 0x3fac4
+#define ixMC_REGISTERS_TABLE_19 0x3fac8
+#define ixMC_REGISTERS_TABLE_20 0x3facc
+#define ixMC_REGISTERS_TABLE_21 0x3fad0
+#define ixMC_REGISTERS_TABLE_22 0x3fad4
+#define ixMC_REGISTERS_TABLE_23 0x3fad8
+#define ixMC_REGISTERS_TABLE_24 0x3fadc
+#define ixMC_REGISTERS_TABLE_25 0x3fae0
+#define ixMC_REGISTERS_TABLE_26 0x3fae4
+#define ixMC_REGISTERS_TABLE_27 0x3fae8
+#define ixMC_REGISTERS_TABLE_28 0x3faec
+#define ixMC_REGISTERS_TABLE_29 0x3faf0
+#define ixMC_REGISTERS_TABLE_30 0x3faf4
+#define ixMC_REGISTERS_TABLE_31 0x3faf8
+#define ixMC_REGISTERS_TABLE_32 0x3fafc
+#define ixMC_REGISTERS_TABLE_33 0x3fb00
+#define ixMC_REGISTERS_TABLE_34 0x3fb04
+#define ixMC_REGISTERS_TABLE_35 0x3fb08
+#define ixMC_REGISTERS_TABLE_36 0x3fb0c
+#define ixMC_REGISTERS_TABLE_37 0x3fb10
+#define ixMC_REGISTERS_TABLE_38 0x3fb14
+#define ixMC_REGISTERS_TABLE_39 0x3fb18
+#define ixMC_REGISTERS_TABLE_40 0x3fb1c
+#define ixMC_REGISTERS_TABLE_41 0x3fb20
+#define ixMC_REGISTERS_TABLE_42 0x3fb24
+#define ixMC_REGISTERS_TABLE_43 0x3fb28
+#define ixMC_REGISTERS_TABLE_44 0x3fb2c
+#define ixMC_REGISTERS_TABLE_45 0x3fb30
+#define ixMC_REGISTERS_TABLE_46 0x3fb34
+#define ixMC_REGISTERS_TABLE_47 0x3fb38
+#define ixMC_REGISTERS_TABLE_48 0x3fb3c
+#define ixMC_REGISTERS_TABLE_49 0x3fb40
+#define ixMC_REGISTERS_TABLE_50 0x3fb44
+#define ixMC_REGISTERS_TABLE_51 0x3fb48
+#define ixMC_REGISTERS_TABLE_52 0x3fb4c
+#define ixMC_REGISTERS_TABLE_53 0x3fb50
+#define ixMC_REGISTERS_TABLE_54 0x3fb54
+#define ixMC_REGISTERS_TABLE_55 0x3fb58
+#define ixMC_REGISTERS_TABLE_56 0x3fb5c
+#define ixMC_REGISTERS_TABLE_57 0x3fb60
+#define ixMC_REGISTERS_TABLE_58 0x3fb64
+#define ixMC_REGISTERS_TABLE_59 0x3fb68
+#define ixMC_REGISTERS_TABLE_60 0x3fb6c
+#define ixMC_REGISTERS_TABLE_61 0x3fb70
+#define ixMC_REGISTERS_TABLE_62 0x3fb74
+#define ixMC_REGISTERS_TABLE_63 0x3fb78
+#define ixMC_REGISTERS_TABLE_64 0x3fb7c
+#define ixMC_REGISTERS_TABLE_65 0x3fb80
+#define ixMC_REGISTERS_TABLE_66 0x3fb84
+#define ixMC_REGISTERS_TABLE_67 0x3fb88
+#define ixMC_REGISTERS_TABLE_68 0x3fb8c
+#define ixMC_REGISTERS_TABLE_69 0x3fb90
+#define ixMC_REGISTERS_TABLE_70 0x3fb94
+#define ixMC_REGISTERS_TABLE_71 0x3fb98
+#define ixMC_REGISTERS_TABLE_72 0x3fb9c
+#define ixMC_REGISTERS_TABLE_73 0x3fba0
+#define ixMC_REGISTERS_TABLE_74 0x3fba4
+#define ixMC_REGISTERS_TABLE_75 0x3fba8
+#define ixMC_REGISTERS_TABLE_76 0x3fbac
+#define ixMC_REGISTERS_TABLE_77 0x3fbb0
+#define ixMC_REGISTERS_TABLE_78 0x3fbb4
+#define ixMC_REGISTERS_TABLE_79 0x3fbb8
+#define ixMC_REGISTERS_TABLE_80 0x3fbbc
+#define ixMC_REGISTERS_TABLE_81 0x3fbc0
+#define ixFAN_TABLE_1 0x3fbc4
+#define ixFAN_TABLE_2 0x3fbc8
+#define ixFAN_TABLE_3 0x3fbcc
+#define ixFAN_TABLE_4 0x3fbd0
+#define ixFAN_TABLE_5 0x3fbd4
+#define ixFAN_TABLE_6 0x3fbd8
+#define ixFAN_TABLE_7 0x3fbdc
+#define ixFAN_TABLE_8 0x3fbe0
+#define ixFAN_TABLE_9 0x3fbe4
+#define ixSOFT_REGISTERS_TABLE_1 0x3fbe8
+#define ixSOFT_REGISTERS_TABLE_2 0x3fbec
+#define ixSOFT_REGISTERS_TABLE_3 0x3fbf0
+#define ixSOFT_REGISTERS_TABLE_4 0x3fbf4
+#define ixSOFT_REGISTERS_TABLE_5 0x3fbf8
+#define ixSOFT_REGISTERS_TABLE_6 0x3fbfc
+#define ixSOFT_REGISTERS_TABLE_7 0x3fc00
+#define ixSOFT_REGISTERS_TABLE_8 0x3fc04
+#define ixSOFT_REGISTERS_TABLE_9 0x3fc08
+#define ixSOFT_REGISTERS_TABLE_10 0x3fc0c
+#define ixSOFT_REGISTERS_TABLE_11 0x3fc10
+#define ixSOFT_REGISTERS_TABLE_12 0x3fc14
+#define ixSOFT_REGISTERS_TABLE_13 0x3fc18
+#define ixSOFT_REGISTERS_TABLE_14 0x3fc1c
+#define ixSOFT_REGISTERS_TABLE_15 0x3fc20
+#define ixSOFT_REGISTERS_TABLE_16 0x3fc24
+#define ixSOFT_REGISTERS_TABLE_17 0x3fc28
+#define ixSOFT_REGISTERS_TABLE_18 0x3fc2c
+#define ixSOFT_REGISTERS_TABLE_19 0x3fc30
+#define ixSOFT_REGISTERS_TABLE_20 0x3fc34
+#define ixSOFT_REGISTERS_TABLE_21 0x3fc38
+#define ixSOFT_REGISTERS_TABLE_22 0x3fc3c
+#define ixSOFT_REGISTERS_TABLE_23 0x3fc40
+#define ixSOFT_REGISTERS_TABLE_24 0x3fc44
+#define ixSOFT_REGISTERS_TABLE_25 0x3fc48
+#define ixSOFT_REGISTERS_TABLE_26 0x3fc4c
+#define ixSOFT_REGISTERS_TABLE_27 0x3fc50
+#define ixSOFT_REGISTERS_TABLE_28 0x3fc54
+#define ixSOFT_REGISTERS_TABLE_29 0x3fc58
+#define ixSOFT_REGISTERS_TABLE_30 0x3fc5c
+#define ixPM_FUSES_1 0x3fc60
+#define ixPM_FUSES_2 0x3fc64
+#define ixPM_FUSES_3 0x3fc68
+#define ixPM_FUSES_4 0x3fc6c
+#define ixPM_FUSES_5 0x3fc70
+#define ixPM_FUSES_6 0x3fc74
+#define ixPM_FUSES_7 0x3fc78
+#define ixPM_FUSES_8 0x3fc7c
+#define ixPM_FUSES_9 0x3fc80
+#define ixPM_FUSES_10 0x3fc84
+#define ixPM_FUSES_11 0x3fc88
+#define ixPM_FUSES_12 0x3fc8c
+#define ixPM_FUSES_13 0x3fc90
+#define ixPM_FUSES_14 0x3fc94
+#define ixPM_FUSES_15 0x3fc98
+#define ixSMU_PM_STATUS_0 0x3fe00
+#define ixSMU_PM_STATUS_1 0x3fe04
+#define ixSMU_PM_STATUS_2 0x3fe08
+#define ixSMU_PM_STATUS_3 0x3fe0c
+#define ixSMU_PM_STATUS_4 0x3fe10
+#define ixSMU_PM_STATUS_5 0x3fe14
+#define ixSMU_PM_STATUS_6 0x3fe18
+#define ixSMU_PM_STATUS_7 0x3fe1c
+#define ixSMU_PM_STATUS_8 0x3fe20
+#define ixSMU_PM_STATUS_9 0x3fe24
+#define ixSMU_PM_STATUS_10 0x3fe28
+#define ixSMU_PM_STATUS_11 0x3fe2c
+#define ixSMU_PM_STATUS_12 0x3fe30
+#define ixSMU_PM_STATUS_13 0x3fe34
+#define ixSMU_PM_STATUS_14 0x3fe38
+#define ixSMU_PM_STATUS_15 0x3fe3c
+#define ixSMU_PM_STATUS_16 0x3fe40
+#define ixSMU_PM_STATUS_17 0x3fe44
+#define ixSMU_PM_STATUS_18 0x3fe48
+#define ixSMU_PM_STATUS_19 0x3fe4c
+#define ixSMU_PM_STATUS_20 0x3fe50
+#define ixSMU_PM_STATUS_21 0x3fe54
+#define ixSMU_PM_STATUS_22 0x3fe58
+#define ixSMU_PM_STATUS_23 0x3fe5c
+#define ixSMU_PM_STATUS_24 0x3fe60
+#define ixSMU_PM_STATUS_25 0x3fe64
+#define ixSMU_PM_STATUS_26 0x3fe68
+#define ixSMU_PM_STATUS_27 0x3fe6c
+#define ixSMU_PM_STATUS_28 0x3fe70
+#define ixSMU_PM_STATUS_29 0x3fe74
+#define ixSMU_PM_STATUS_30 0x3fe78
+#define ixSMU_PM_STATUS_31 0x3fe7c
+#define ixSMU_PM_STATUS_32 0x3fe80
+#define ixSMU_PM_STATUS_33 0x3fe84
+#define ixSMU_PM_STATUS_34 0x3fe88
+#define ixSMU_PM_STATUS_35 0x3fe8c
+#define ixSMU_PM_STATUS_36 0x3fe90
+#define ixSMU_PM_STATUS_37 0x3fe94
+#define ixSMU_PM_STATUS_38 0x3fe98
+#define ixSMU_PM_STATUS_39 0x3fe9c
+#define ixSMU_PM_STATUS_40 0x3fea0
+#define ixSMU_PM_STATUS_41 0x3fea4
+#define ixSMU_PM_STATUS_42 0x3fea8
+#define ixSMU_PM_STATUS_43 0x3feac
+#define ixSMU_PM_STATUS_44 0x3feb0
+#define ixSMU_PM_STATUS_45 0x3feb4
+#define ixSMU_PM_STATUS_46 0x3feb8
+#define ixSMU_PM_STATUS_47 0x3febc
+#define ixSMU_PM_STATUS_48 0x3fec0
+#define ixSMU_PM_STATUS_49 0x3fec4
+#define ixSMU_PM_STATUS_50 0x3fec8
+#define ixSMU_PM_STATUS_51 0x3fecc
+#define ixSMU_PM_STATUS_52 0x3fed0
+#define ixSMU_PM_STATUS_53 0x3fed4
+#define ixSMU_PM_STATUS_54 0x3fed8
+#define ixSMU_PM_STATUS_55 0x3fedc
+#define ixSMU_PM_STATUS_56 0x3fee0
+#define ixSMU_PM_STATUS_57 0x3fee4
+#define ixSMU_PM_STATUS_58 0x3fee8
+#define ixSMU_PM_STATUS_59 0x3feec
+#define ixSMU_PM_STATUS_60 0x3fef0
+#define ixSMU_PM_STATUS_61 0x3fef4
+#define ixSMU_PM_STATUS_62 0x3fef8
+#define ixSMU_PM_STATUS_63 0x3fefc
+#define ixSMU_PM_STATUS_64 0x3ff00
+#define ixSMU_PM_STATUS_65 0x3ff04
+#define ixSMU_PM_STATUS_66 0x3ff08
+#define ixSMU_PM_STATUS_67 0x3ff0c
+#define ixSMU_PM_STATUS_68 0x3ff10
+#define ixSMU_PM_STATUS_69 0x3ff14
+#define ixSMU_PM_STATUS_70 0x3ff18
+#define ixSMU_PM_STATUS_71 0x3ff1c
+#define ixSMU_PM_STATUS_72 0x3ff20
+#define ixSMU_PM_STATUS_73 0x3ff24
+#define ixSMU_PM_STATUS_74 0x3ff28
+#define ixSMU_PM_STATUS_75 0x3ff2c
+#define ixSMU_PM_STATUS_76 0x3ff30
+#define ixSMU_PM_STATUS_77 0x3ff34
+#define ixSMU_PM_STATUS_78 0x3ff38
+#define ixSMU_PM_STATUS_79 0x3ff3c
+#define ixSMU_PM_STATUS_80 0x3ff40
+#define ixSMU_PM_STATUS_81 0x3ff44
+#define ixSMU_PM_STATUS_82 0x3ff48
+#define ixSMU_PM_STATUS_83 0x3ff4c
+#define ixSMU_PM_STATUS_84 0x3ff50
+#define ixSMU_PM_STATUS_85 0x3ff54
+#define ixSMU_PM_STATUS_86 0x3ff58
+#define ixSMU_PM_STATUS_87 0x3ff5c
+#define ixSMU_PM_STATUS_88 0x3ff60
+#define ixSMU_PM_STATUS_89 0x3ff64
+#define ixSMU_PM_STATUS_90 0x3ff68
+#define ixSMU_PM_STATUS_91 0x3ff6c
+#define ixSMU_PM_STATUS_92 0x3ff70
+#define ixSMU_PM_STATUS_93 0x3ff74
+#define ixSMU_PM_STATUS_94 0x3ff78
+#define ixSMU_PM_STATUS_95 0x3ff7c
+#define ixSMU_PM_STATUS_96 0x3ff80
+#define ixSMU_PM_STATUS_97 0x3ff84
+#define ixSMU_PM_STATUS_98 0x3ff88
+#define ixSMU_PM_STATUS_99 0x3ff8c
+#define ixSMU_PM_STATUS_100 0x3ff90
+#define ixSMU_PM_STATUS_101 0x3ff94
+#define ixSMU_PM_STATUS_102 0x3ff98
+#define ixSMU_PM_STATUS_103 0x3ff9c
+#define ixSMU_PM_STATUS_104 0x3ffa0
+#define ixSMU_PM_STATUS_105 0x3ffa4
+#define ixSMU_PM_STATUS_106 0x3ffa8
+#define ixSMU_PM_STATUS_107 0x3ffac
+#define ixSMU_PM_STATUS_108 0x3ffb0
+#define ixSMU_PM_STATUS_109 0x3ffb4
+#define ixSMU_PM_STATUS_110 0x3ffb8
+#define ixSMU_PM_STATUS_111 0x3ffbc
+#define ixSMU_PM_STATUS_112 0x3ffc0
+#define ixSMU_PM_STATUS_113 0x3ffc4
+#define ixSMU_PM_STATUS_114 0x3ffc8
+#define ixSMU_PM_STATUS_115 0x3ffcc
+#define ixSMU_PM_STATUS_116 0x3ffd0
+#define ixSMU_PM_STATUS_117 0x3ffd4
+#define ixSMU_PM_STATUS_118 0x3ffd8
+#define ixSMU_PM_STATUS_119 0x3ffdc
+#define ixSMU_PM_STATUS_120 0x3ffe0
+#define ixSMU_PM_STATUS_121 0x3ffe4
+#define ixSMU_PM_STATUS_122 0x3ffe8
+#define ixSMU_PM_STATUS_123 0x3ffec
+#define ixSMU_PM_STATUS_124 0x3fff0
+#define ixSMU_PM_STATUS_125 0x3fff4
+#define ixSMU_PM_STATUS_126 0x3fff8
+#define ixSMU_PM_STATUS_127 0x3fffc
+#define ixCG_THERMAL_INT_ENA 0xc2100024
+#define ixCG_THERMAL_INT_CTRL 0xc2100028
+#define ixCG_THERMAL_INT_STATUS 0xc210002c
+#define ixCG_THERMAL_CTRL 0xc0300004
+#define ixCG_THERMAL_STATUS 0xc0300008
+#define ixCG_THERMAL_INT 0xc030000c
+#define ixCG_MULT_THERMAL_CTRL 0xc0300010
+#define ixCG_MULT_THERMAL_STATUS 0xc0300014
+#define ixCG_FDO_CTRL0 0xc0300064
+#define ixCG_FDO_CTRL1 0xc0300068
+#define ixCG_FDO_CTRL2 0xc030006c
+#define ixCG_TACH_CTRL 0xc0300070
+#define ixCG_TACH_STATUS 0xc0300074
+#define ixCC_THM_STRAPS0 0xc0300080
+#define ixTHM_TMON0_RDIL0_DATA 0xc0300100
+#define ixTHM_TMON0_RDIL1_DATA 0xc0300104
+#define ixTHM_TMON0_RDIL2_DATA 0xc0300108
+#define ixTHM_TMON0_RDIL3_DATA 0xc030010c
+#define ixTHM_TMON0_RDIL4_DATA 0xc0300110
+#define ixTHM_TMON0_RDIL5_DATA 0xc0300114
+#define ixTHM_TMON0_RDIL6_DATA 0xc0300118
+#define ixTHM_TMON0_RDIL7_DATA 0xc030011c
+#define ixTHM_TMON0_RDIL8_DATA 0xc0300120
+#define ixTHM_TMON0_RDIL9_DATA 0xc0300124
+#define ixTHM_TMON0_RDIL10_DATA 0xc0300128
+#define ixTHM_TMON0_RDIL11_DATA 0xc030012c
+#define ixTHM_TMON0_RDIL12_DATA 0xc0300130
+#define ixTHM_TMON0_RDIL13_DATA 0xc0300134
+#define ixTHM_TMON0_RDIL14_DATA 0xc0300138
+#define ixTHM_TMON0_RDIL15_DATA 0xc030013c
+#define ixTHM_TMON0_RDIR0_DATA 0xc0300140
+#define ixTHM_TMON0_RDIR1_DATA 0xc0300144
+#define ixTHM_TMON0_RDIR2_DATA 0xc0300148
+#define ixTHM_TMON0_RDIR3_DATA 0xc030014c
+#define ixTHM_TMON0_RDIR4_DATA 0xc0300150
+#define ixTHM_TMON0_RDIR5_DATA 0xc0300154
+#define ixTHM_TMON0_RDIR6_DATA 0xc0300158
+#define ixTHM_TMON0_RDIR7_DATA 0xc030015c
+#define ixTHM_TMON0_RDIR8_DATA 0xc0300160
+#define ixTHM_TMON0_RDIR9_DATA 0xc0300164
+#define ixTHM_TMON0_RDIR10_DATA 0xc0300168
+#define ixTHM_TMON0_RDIR11_DATA 0xc030016c
+#define ixTHM_TMON0_RDIR12_DATA 0xc0300170
+#define ixTHM_TMON0_RDIR13_DATA 0xc0300174
+#define ixTHM_TMON0_RDIR14_DATA 0xc0300178
+#define ixTHM_TMON0_RDIR15_DATA 0xc030017c
+#define ixTHM_TMON1_RDIL0_DATA 0xc0300180
+#define ixTHM_TMON1_RDIL1_DATA 0xc0300184
+#define ixTHM_TMON1_RDIL2_DATA 0xc0300188
+#define ixTHM_TMON1_RDIL3_DATA 0xc030018c
+#define ixTHM_TMON1_RDIL4_DATA 0xc0300190
+#define ixTHM_TMON1_RDIL5_DATA 0xc0300194
+#define ixTHM_TMON1_RDIL6_DATA 0xc0300198
+#define ixTHM_TMON1_RDIL7_DATA 0xc030019c
+#define ixTHM_TMON1_RDIL8_DATA 0xc03001a0
+#define ixTHM_TMON1_RDIL9_DATA 0xc03001a4
+#define ixTHM_TMON1_RDIL10_DATA 0xc03001a8
+#define ixTHM_TMON1_RDIL11_DATA 0xc03001ac
+#define ixTHM_TMON1_RDIL12_DATA 0xc03001b0
+#define ixTHM_TMON1_RDIL13_DATA 0xc03001b4
+#define ixTHM_TMON1_RDIL14_DATA 0xc03001b8
+#define ixTHM_TMON1_RDIL15_DATA 0xc03001bc
+#define ixTHM_TMON1_RDIR0_DATA 0xc03001c0
+#define ixTHM_TMON1_RDIR1_DATA 0xc03001c4
+#define ixTHM_TMON1_RDIR2_DATA 0xc03001c8
+#define ixTHM_TMON1_RDIR3_DATA 0xc03001cc
+#define ixTHM_TMON1_RDIR4_DATA 0xc03001d0
+#define ixTHM_TMON1_RDIR5_DATA 0xc03001d4
+#define ixTHM_TMON1_RDIR6_DATA 0xc03001d8
+#define ixTHM_TMON1_RDIR7_DATA 0xc03001dc
+#define ixTHM_TMON1_RDIR8_DATA 0xc03001e0
+#define ixTHM_TMON1_RDIR9_DATA 0xc03001e4
+#define ixTHM_TMON1_RDIR10_DATA 0xc03001e8
+#define ixTHM_TMON1_RDIR11_DATA 0xc03001ec
+#define ixTHM_TMON1_RDIR12_DATA 0xc03001f0
+#define ixTHM_TMON1_RDIR13_DATA 0xc03001f4
+#define ixTHM_TMON1_RDIR14_DATA 0xc03001f8
+#define ixTHM_TMON1_RDIR15_DATA 0xc03001fc
+#define ixTHM_TMON0_INT_DATA 0xc0300300
+#define ixTHM_TMON1_INT_DATA 0xc0300304
+#define ixTHM_TMON0_DEBUG 0xc0300310
+#define ixTHM_TMON1_DEBUG 0xc0300314
+#define ixTHM_TMON0_STATUS 0xc0300320
+#define ixTHM_TMON1_STATUS 0xc0300324
+#define ixGENERAL_PWRMGT 0xc0200000
+#define ixCNB_PWRMGT_CNTL 0xc0200004
+#define ixSCLK_PWRMGT_CNTL 0xc0200008
+#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014
+#define ixPWR_PCC_CONTROL 0xc0200018
+#define ixPWR_PCC_GPIO_SELECT 0xc020001c
+#define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8
+#define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac
+#define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0
+#define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4
+#define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8
+#define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc
+#define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0
+#define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4
+#define ixPLL_TEST_CNTL 0xc020003c
+#define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044
+#define ixCG_DISPLAY_GAP_CNTL 0xc0200060
+#define ixCG_DISPLAY_GAP_CNTL2 0xc0200230
+#define ixCG_ACPI_CNTL 0xc0200064
+#define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080
+#define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084
+#define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c
+#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088
+#define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c
+#define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310
+#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0
+#define ixCG_ULV_PARAMETER 0xc020015c
+#define ixSCLK_MIN_DIV 0xc02003ac
+#define ixPWR_CKS_ENABLE 0xc020034c
+#define ixPWR_CKS_CNTL 0xc0200350
+#define ixPWR_DISP_TIMER_CONTROL 0xc02003c0
+#define ixPWR_DISP_TIMER_DEBUG 0xc02003c4
+#define ixPWR_DISP_TIMER2_CONTROL 0xc02003c8
+#define ixPWR_DISP_TIMER2_DEBUG 0xc02003cc
+#define ixPWR_DISP_TIMER_CONTROL2 0xc0200378
+#define ixVDDGFX_IDLE_PARAMETER 0xc020036c
+#define ixVDDGFX_IDLE_CONTROL 0xc0200370
+#define ixVDDGFX_IDLE_EXIT 0xc0200374
+#define ixLCAC_MC0_CNTL 0xc0400130
+#define ixLCAC_MC0_OVR_SEL 0xc0400134
+#define ixLCAC_MC0_OVR_VAL 0xc0400138
+#define ixLCAC_MC1_CNTL 0xc040013c
+#define ixLCAC_MC1_OVR_SEL 0xc0400140
+#define ixLCAC_MC1_OVR_VAL 0xc0400144
+#define ixLCAC_MC2_CNTL 0xc0400148
+#define ixLCAC_MC2_OVR_SEL 0xc040014c
+#define ixLCAC_MC2_OVR_VAL 0xc0400150
+#define ixLCAC_MC3_CNTL 0xc0400154
+#define ixLCAC_MC3_OVR_SEL 0xc0400158
+#define ixLCAC_MC3_OVR_VAL 0xc040015c
+#define ixLCAC_CPL_CNTL 0xc0400160
+#define ixLCAC_CPL_OVR_SEL 0xc0400164
+#define ixLCAC_CPL_OVR_VAL 0xc0400168
+#define mmROM_SMC_IND_INDEX 0x80
+#define mmROM0_ROM_SMC_IND_INDEX 0x80
+#define mmROM1_ROM_SMC_IND_INDEX 0x82
+#define mmROM2_ROM_SMC_IND_INDEX 0x84
+#define mmROM3_ROM_SMC_IND_INDEX 0x86
+#define mmROM_SMC_IND_DATA 0x81
+#define mmROM0_ROM_SMC_IND_DATA 0x81
+#define mmROM1_ROM_SMC_IND_DATA 0x83
+#define mmROM2_ROM_SMC_IND_DATA 0x85
+#define mmROM3_ROM_SMC_IND_DATA 0x87
+#define ixROM_CNTL 0xc0600000
+#define ixPAGE_MIRROR_CNTL 0xc0600004
+#define ixROM_STATUS 0xc0600008
+#define ixCGTT_ROM_CLK_CTRL0 0xc060000c
+#define ixROM_INDEX 0xc0600010
+#define ixROM_DATA 0xc0600014
+#define ixROM_START 0xc0600018
+#define ixROM_SW_CNTL 0xc060001c
+#define ixROM_SW_STATUS 0xc0600020
+#define ixROM_SW_COMMAND 0xc0600024
+#define ixROM_SW_DATA_1 0xc0600028
+#define ixROM_SW_DATA_2 0xc060002c
+#define ixROM_SW_DATA_3 0xc0600030
+#define ixROM_SW_DATA_4 0xc0600034
+#define ixROM_SW_DATA_5 0xc0600038
+#define ixROM_SW_DATA_6 0xc060003c
+#define ixROM_SW_DATA_7 0xc0600040
+#define ixROM_SW_DATA_8 0xc0600044
+#define ixROM_SW_DATA_9 0xc0600048
+#define ixROM_SW_DATA_10 0xc060004c
+#define ixROM_SW_DATA_11 0xc0600050
+#define ixROM_SW_DATA_12 0xc0600054
+#define ixROM_SW_DATA_13 0xc0600058
+#define ixROM_SW_DATA_14 0xc060005c
+#define ixROM_SW_DATA_15 0xc0600060
+#define ixROM_SW_DATA_16 0xc0600064
+#define ixROM_SW_DATA_17 0xc0600068
+#define ixROM_SW_DATA_18 0xc060006c
+#define ixROM_SW_DATA_19 0xc0600070
+#define ixROM_SW_DATA_20 0xc0600074
+#define ixROM_SW_DATA_21 0xc0600078
+#define ixROM_SW_DATA_22 0xc060007c
+#define ixROM_SW_DATA_23 0xc0600080
+#define ixROM_SW_DATA_24 0xc0600084
+#define ixROM_SW_DATA_25 0xc0600088
+#define ixROM_SW_DATA_26 0xc060008c
+#define ixROM_SW_DATA_27 0xc0600090
+#define ixROM_SW_DATA_28 0xc0600094
+#define ixROM_SW_DATA_29 0xc0600098
+#define ixROM_SW_DATA_30 0xc060009c
+#define ixROM_SW_DATA_31 0xc06000a0
+#define ixROM_SW_DATA_32 0xc06000a4
+#define ixROM_SW_DATA_33 0xc06000a8
+#define ixROM_SW_DATA_34 0xc06000ac
+#define ixROM_SW_DATA_35 0xc06000b0
+#define ixROM_SW_DATA_36 0xc06000b4
+#define ixROM_SW_DATA_37 0xc06000b8
+#define ixROM_SW_DATA_38 0xc06000bc
+#define ixROM_SW_DATA_39 0xc06000c0
+#define ixROM_SW_DATA_40 0xc06000c4
+#define ixROM_SW_DATA_41 0xc06000c8
+#define ixROM_SW_DATA_42 0xc06000cc
+#define ixROM_SW_DATA_43 0xc06000d0
+#define ixROM_SW_DATA_44 0xc06000d4
+#define ixROM_SW_DATA_45 0xc06000d8
+#define ixROM_SW_DATA_46 0xc06000dc
+#define ixROM_SW_DATA_47 0xc06000e0
+#define ixROM_SW_DATA_48 0xc06000e4
+#define ixROM_SW_DATA_49 0xc06000e8
+#define ixROM_SW_DATA_50 0xc06000ec
+#define ixROM_SW_DATA_51 0xc06000f0
+#define ixROM_SW_DATA_52 0xc06000f4
+#define ixROM_SW_DATA_53 0xc06000f8
+#define ixROM_SW_DATA_54 0xc06000fc
+#define ixROM_SW_DATA_55 0xc0600100
+#define ixROM_SW_DATA_56 0xc0600104
+#define ixROM_SW_DATA_57 0xc0600108
+#define ixROM_SW_DATA_58 0xc060010c
+#define ixROM_SW_DATA_59 0xc0600110
+#define ixROM_SW_DATA_60 0xc0600114
+#define ixROM_SW_DATA_61 0xc0600118
+#define ixROM_SW_DATA_62 0xc060011c
+#define ixROM_SW_DATA_63 0xc0600120
+#define ixROM_SW_DATA_64 0xc0600124
+
+#endif /* SMU_7_1_2_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_enum.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_enum.h
new file mode 100644
index 000000000000..73bbf506b1c9
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_enum.h
@@ -0,0 +1,1246 @@
+/*
+ * SMU_7_1_2 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef SMU_7_1_2_ENUM_H
+#define SMU_7_1_2_ENUM_H
+
+#define CG_SRBM_START_ADDR 0x600
+#define CG_SRBM_END_ADDR 0x8ff
+#define RCU_CCF_DWORDS0 0xa0
+#define RCU_CCF_BITS0 0x1400
+#define RCU_CCF_DWORDS1 0x0
+#define RCU_CCF_BITS1 0x0
+#define RCU_SAM_BYTES 0x2c
+#define RCU_SAM_RTL_BYTES 0x2c
+#define RCU_SMU_BYTES 0x14
+#define RCU_SMU_RTL_BYTES 0x14
+#define SFP_CHAIN_ADDR 0x0
+#define SFP_BYTES 0x140
+#define SFP_SADR 0xc0
+#define SFP_EADR 0x1ff
+#define SAMU_KEY_CHAIN_ADR 0x0
+#define SAMU_KEY_SADR 0x2a0
+#define SAMU_KEY_EADR 0x2cb
+#define SMU_KEY_CHAIN_ADR 0x0
+#define SMU_KEY_SADR 0x2cc
+#define SMU_KEY_EADR 0x2df
+#define SMC_MSG_TEST 0x1
+#define SMC_MSG_PHY_LN_OFF 0x2
+#define SMC_MSG_PHY_LN_ON 0x3
+#define SMC_MSG_DDI_PHY_OFF 0x4
+#define SMC_MSG_DDI_PHY_ON 0x5
+#define SMC_MSG_CASCADE_PLL_OFF 0x6
+#define SMC_MSG_CASCADE_PLL_ON 0x7
+#define SMC_MSG_PWR_OFF_x16 0x8
+#define SMC_MSG_CONFIG_LCLK_DPM 0x9
+#define SMC_MSG_FLUSH_DATA_CACHE 0xa
+#define SMC_MSG_FLUSH_INSTRUCTION_CACHE 0xb
+#define SMC_MSG_CONFIG_VPC_ACCUMULATOR 0xc
+#define SMC_MSG_CONFIG_BAPM 0xd
+#define SMC_MSG_CONFIG_TDC_LIMIT 0xe
+#define SMC_MSG_CONFIG_LPMx 0xf
+#define SMC_MSG_CONFIG_HTC_LIMIT 0x10
+#define SMC_MSG_CONFIG_THERMAL_CNTL 0x11
+#define SMC_MSG_CONFIG_VOLTAGE_CNTL 0x12
+#define SMC_MSG_CONFIG_TDP_CNTL 0x13
+#define SMC_MSG_EN_PM_CNTL 0x14
+#define SMC_MSG_DIS_PM_CNTL 0x15
+#define SMC_MSG_CONFIG_NBDPM 0x16
+#define SMC_MSG_CONFIG_LOADLINE 0x17
+#define SMC_MSG_ADJUST_LOADLINE 0x18
+#define SMC_MSG_RESET 0x20
+#define SMC_MSG_VOLTAGE 0x25
+#define SMC_VERSION_MAJOR 0x7
+#define SMC_VERSION_MINOR 0x0
+#define SMC_HEADER_SIZE 0x40
+#define ROM_SIGNATURE 0xaa55
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0x0,
+ ENDIAN_8IN16 = 0x1,
+ ENDIAN_8IN32 = 0x2,
+ ENDIAN_8IN64 = 0x3,
+} SurfaceEndian;
+typedef enum ArrayMode {
+ ARRAY_LINEAR_GENERAL = 0x0,
+ ARRAY_LINEAR_ALIGNED = 0x1,
+ ARRAY_1D_TILED_THIN1 = 0x2,
+ ARRAY_1D_TILED_THICK = 0x3,
+ ARRAY_2D_TILED_THIN1 = 0x4,
+ ARRAY_PRT_TILED_THIN1 = 0x5,
+ ARRAY_PRT_2D_TILED_THIN1 = 0x6,
+ ARRAY_2D_TILED_THICK = 0x7,
+ ARRAY_2D_TILED_XTHICK = 0x8,
+ ARRAY_PRT_TILED_THICK = 0x9,
+ ARRAY_PRT_2D_TILED_THICK = 0xa,
+ ARRAY_PRT_3D_TILED_THIN1 = 0xb,
+ ARRAY_3D_TILED_THIN1 = 0xc,
+ ARRAY_3D_TILED_THICK = 0xd,
+ ARRAY_3D_TILED_XTHICK = 0xe,
+ ARRAY_PRT_3D_TILED_THICK = 0xf,
+} ArrayMode;
+typedef enum PipeTiling {
+ CONFIG_1_PIPE = 0x0,
+ CONFIG_2_PIPE = 0x1,
+ CONFIG_4_PIPE = 0x2,
+ CONFIG_8_PIPE = 0x3,
+} PipeTiling;
+typedef enum BankTiling {
+ CONFIG_4_BANK = 0x0,
+ CONFIG_8_BANK = 0x1,
+} BankTiling;
+typedef enum GroupInterleave {
+ CONFIG_256B_GROUP = 0x0,
+ CONFIG_512B_GROUP = 0x1,
+} GroupInterleave;
+typedef enum RowTiling {
+ CONFIG_1KB_ROW = 0x0,
+ CONFIG_2KB_ROW = 0x1,
+ CONFIG_4KB_ROW = 0x2,
+ CONFIG_8KB_ROW = 0x3,
+ CONFIG_1KB_ROW_OPT = 0x4,
+ CONFIG_2KB_ROW_OPT = 0x5,
+ CONFIG_4KB_ROW_OPT = 0x6,
+ CONFIG_8KB_ROW_OPT = 0x7,
+} RowTiling;
+typedef enum BankSwapBytes {
+ CONFIG_128B_SWAPS = 0x0,
+ CONFIG_256B_SWAPS = 0x1,
+ CONFIG_512B_SWAPS = 0x2,
+ CONFIG_1KB_SWAPS = 0x3,
+} BankSwapBytes;
+typedef enum SampleSplitBytes {
+ CONFIG_1KB_SPLIT = 0x0,
+ CONFIG_2KB_SPLIT = 0x1,
+ CONFIG_4KB_SPLIT = 0x2,
+ CONFIG_8KB_SPLIT = 0x3,
+} SampleSplitBytes;
+typedef enum NumPipes {
+ ADDR_CONFIG_1_PIPE = 0x0,
+ ADDR_CONFIG_2_PIPE = 0x1,
+ ADDR_CONFIG_4_PIPE = 0x2,
+ ADDR_CONFIG_8_PIPE = 0x3,
+} NumPipes;
+typedef enum PipeInterleaveSize {
+ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
+ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
+} PipeInterleaveSize;
+typedef enum BankInterleaveSize {
+ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
+ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
+ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
+ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
+} BankInterleaveSize;
+typedef enum NumShaderEngines {
+ ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
+ ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
+} NumShaderEngines;
+typedef enum ShaderEngineTileSize {
+ ADDR_CONFIG_SE_TILE_16 = 0x0,
+ ADDR_CONFIG_SE_TILE_32 = 0x1,
+} ShaderEngineTileSize;
+typedef enum NumGPUs {
+ ADDR_CONFIG_1_GPU = 0x0,
+ ADDR_CONFIG_2_GPU = 0x1,
+ ADDR_CONFIG_4_GPU = 0x2,
+} NumGPUs;
+typedef enum MultiGPUTileSize {
+ ADDR_CONFIG_GPU_TILE_16 = 0x0,
+ ADDR_CONFIG_GPU_TILE_32 = 0x1,
+ ADDR_CONFIG_GPU_TILE_64 = 0x2,
+ ADDR_CONFIG_GPU_TILE_128 = 0x3,
+} MultiGPUTileSize;
+typedef enum RowSize {
+ ADDR_CONFIG_1KB_ROW = 0x0,
+ ADDR_CONFIG_2KB_ROW = 0x1,
+ ADDR_CONFIG_4KB_ROW = 0x2,
+} RowSize;
+typedef enum NumLowerPipes {
+ ADDR_CONFIG_1_LOWER_PIPES = 0x0,
+ ADDR_CONFIG_2_LOWER_PIPES = 0x1,
+} NumLowerPipes;
+typedef enum DebugBlockId {
+ DBG_CLIENT_BLKID_RESERVED = 0x0,
+ DBG_CLIENT_BLKID_dbg = 0x1,
+ DBG_CLIENT_BLKID_scf2 = 0x2,
+ DBG_CLIENT_BLKID_mcd5 = 0x3,
+ DBG_CLIENT_BLKID_vmc = 0x4,
+ DBG_CLIENT_BLKID_sx30 = 0x5,
+ DBG_CLIENT_BLKID_mcd2 = 0x6,
+ DBG_CLIENT_BLKID_bci1 = 0x7,
+ DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8,
+ DBG_CLIENT_BLKID_mcc0 = 0x9,
+ DBG_CLIENT_BLKID_uvdf_0 = 0xa,
+ DBG_CLIENT_BLKID_uvdf_1 = 0xb,
+ DBG_CLIENT_BLKID_bci0 = 0xc,
+ DBG_CLIENT_BLKID_vcec0_0 = 0xd,
+ DBG_CLIENT_BLKID_cb100 = 0xe,
+ DBG_CLIENT_BLKID_cb001 = 0xf,
+ DBG_CLIENT_BLKID_mcd4 = 0x10,
+ DBG_CLIENT_BLKID_tmonw00 = 0x11,
+ DBG_CLIENT_BLKID_cb101 = 0x12,
+ DBG_CLIENT_BLKID_sx10 = 0x13,
+ DBG_CLIENT_BLKID_cb301 = 0x14,
+ DBG_CLIENT_BLKID_tmonw01 = 0x15,
+ DBG_CLIENT_BLKID_vcea0_0 = 0x16,
+ DBG_CLIENT_BLKID_vcea0_1 = 0x17,
+ DBG_CLIENT_BLKID_vcea0_2 = 0x18,
+ DBG_CLIENT_BLKID_vcea0_3 = 0x19,
+ DBG_CLIENT_BLKID_scf1 = 0x1a,
+ DBG_CLIENT_BLKID_sx20 = 0x1b,
+ DBG_CLIENT_BLKID_spim1 = 0x1c,
+ DBG_CLIENT_BLKID_pa10 = 0x1d,
+ DBG_CLIENT_BLKID_pa00 = 0x1e,
+ DBG_CLIENT_BLKID_gmcon = 0x1f,
+ DBG_CLIENT_BLKID_mcb = 0x20,
+ DBG_CLIENT_BLKID_vgt0 = 0x21,
+ DBG_CLIENT_BLKID_pc0 = 0x22,
+ DBG_CLIENT_BLKID_bci2 = 0x23,
+ DBG_CLIENT_BLKID_uvdb_0 = 0x24,
+ DBG_CLIENT_BLKID_spim3 = 0x25,
+ DBG_CLIENT_BLKID_cpc_0 = 0x26,
+ DBG_CLIENT_BLKID_cpc_1 = 0x27,
+ DBG_CLIENT_BLKID_uvdm_0 = 0x28,
+ DBG_CLIENT_BLKID_uvdm_1 = 0x29,
+ DBG_CLIENT_BLKID_uvdm_2 = 0x2a,
+ DBG_CLIENT_BLKID_uvdm_3 = 0x2b,
+ DBG_CLIENT_BLKID_cb000 = 0x2c,
+ DBG_CLIENT_BLKID_spim0 = 0x2d,
+ DBG_CLIENT_BLKID_mcc2 = 0x2e,
+ DBG_CLIENT_BLKID_ds0 = 0x2f,
+ DBG_CLIENT_BLKID_srbm = 0x30,
+ DBG_CLIENT_BLKID_ih = 0x31,
+ DBG_CLIENT_BLKID_sem = 0x32,
+ DBG_CLIENT_BLKID_sdma_0 = 0x33,
+ DBG_CLIENT_BLKID_sdma_1 = 0x34,
+ DBG_CLIENT_BLKID_hdp = 0x35,
+ DBG_CLIENT_BLKID_acp_0 = 0x36,
+ DBG_CLIENT_BLKID_acp_1 = 0x37,
+ DBG_CLIENT_BLKID_cb200 = 0x38,
+ DBG_CLIENT_BLKID_scf3 = 0x39,
+ DBG_CLIENT_BLKID_vceb1_0 = 0x3a,
+ DBG_CLIENT_BLKID_vcea1_0 = 0x3b,
+ DBG_CLIENT_BLKID_vcea1_1 = 0x3c,
+ DBG_CLIENT_BLKID_vcea1_2 = 0x3d,
+ DBG_CLIENT_BLKID_vcea1_3 = 0x3e,
+ DBG_CLIENT_BLKID_bci3 = 0x3f,
+ DBG_CLIENT_BLKID_mcd0 = 0x40,
+ DBG_CLIENT_BLKID_pa11 = 0x41,
+ DBG_CLIENT_BLKID_pa01 = 0x42,
+ DBG_CLIENT_BLKID_cb201 = 0x43,
+ DBG_CLIENT_BLKID_spim2 = 0x44,
+ DBG_CLIENT_BLKID_vgt2 = 0x45,
+ DBG_CLIENT_BLKID_pc2 = 0x46,
+ DBG_CLIENT_BLKID_smu_0 = 0x47,
+ DBG_CLIENT_BLKID_smu_1 = 0x48,
+ DBG_CLIENT_BLKID_smu_2 = 0x49,
+ DBG_CLIENT_BLKID_cb1 = 0x4a,
+ DBG_CLIENT_BLKID_ia0 = 0x4b,
+ DBG_CLIENT_BLKID_wd = 0x4c,
+ DBG_CLIENT_BLKID_ia1 = 0x4d,
+ DBG_CLIENT_BLKID_vcec1_0 = 0x4e,
+ DBG_CLIENT_BLKID_scf0 = 0x4f,
+ DBG_CLIENT_BLKID_vgt1 = 0x50,
+ DBG_CLIENT_BLKID_pc1 = 0x51,
+ DBG_CLIENT_BLKID_cb0 = 0x52,
+ DBG_CLIENT_BLKID_gdc_one_0 = 0x53,
+ DBG_CLIENT_BLKID_gdc_one_1 = 0x54,
+ DBG_CLIENT_BLKID_gdc_one_2 = 0x55,
+ DBG_CLIENT_BLKID_gdc_one_3 = 0x56,
+ DBG_CLIENT_BLKID_gdc_one_4 = 0x57,
+ DBG_CLIENT_BLKID_gdc_one_5 = 0x58,
+ DBG_CLIENT_BLKID_gdc_one_6 = 0x59,
+ DBG_CLIENT_BLKID_gdc_one_7 = 0x5a,
+ DBG_CLIENT_BLKID_gdc_one_8 = 0x5b,
+ DBG_CLIENT_BLKID_gdc_one_9 = 0x5c,
+ DBG_CLIENT_BLKID_gdc_one_10 = 0x5d,
+ DBG_CLIENT_BLKID_gdc_one_11 = 0x5e,
+ DBG_CLIENT_BLKID_gdc_one_12 = 0x5f,
+ DBG_CLIENT_BLKID_gdc_one_13 = 0x60,
+ DBG_CLIENT_BLKID_gdc_one_14 = 0x61,
+ DBG_CLIENT_BLKID_gdc_one_15 = 0x62,
+ DBG_CLIENT_BLKID_gdc_one_16 = 0x63,
+ DBG_CLIENT_BLKID_gdc_one_17 = 0x64,
+ DBG_CLIENT_BLKID_gdc_one_18 = 0x65,
+ DBG_CLIENT_BLKID_gdc_one_19 = 0x66,
+ DBG_CLIENT_BLKID_gdc_one_20 = 0x67,
+ DBG_CLIENT_BLKID_gdc_one_21 = 0x68,
+ DBG_CLIENT_BLKID_gdc_one_22 = 0x69,
+ DBG_CLIENT_BLKID_gdc_one_23 = 0x6a,
+ DBG_CLIENT_BLKID_gdc_one_24 = 0x6b,
+ DBG_CLIENT_BLKID_gdc_one_25 = 0x6c,
+ DBG_CLIENT_BLKID_gdc_one_26 = 0x6d,
+ DBG_CLIENT_BLKID_gdc_one_27 = 0x6e,
+ DBG_CLIENT_BLKID_gdc_one_28 = 0x6f,
+ DBG_CLIENT_BLKID_gdc_one_29 = 0x70,
+ DBG_CLIENT_BLKID_gdc_one_30 = 0x71,
+ DBG_CLIENT_BLKID_gdc_one_31 = 0x72,
+ DBG_CLIENT_BLKID_gdc_one_32 = 0x73,
+ DBG_CLIENT_BLKID_gdc_one_33 = 0x74,
+ DBG_CLIENT_BLKID_gdc_one_34 = 0x75,
+ DBG_CLIENT_BLKID_gdc_one_35 = 0x76,
+ DBG_CLIENT_BLKID_vceb0_0 = 0x77,
+ DBG_CLIENT_BLKID_vgt3 = 0x78,
+ DBG_CLIENT_BLKID_pc3 = 0x79,
+ DBG_CLIENT_BLKID_mcd3 = 0x7a,
+ DBG_CLIENT_BLKID_uvdu_0 = 0x7b,
+ DBG_CLIENT_BLKID_uvdu_1 = 0x7c,
+ DBG_CLIENT_BLKID_uvdu_2 = 0x7d,
+ DBG_CLIENT_BLKID_uvdu_3 = 0x7e,
+ DBG_CLIENT_BLKID_uvdu_4 = 0x7f,
+ DBG_CLIENT_BLKID_uvdu_5 = 0x80,
+ DBG_CLIENT_BLKID_uvdu_6 = 0x81,
+ DBG_CLIENT_BLKID_cb300 = 0x82,
+ DBG_CLIENT_BLKID_mcd1 = 0x83,
+ DBG_CLIENT_BLKID_sx00 = 0x84,
+ DBG_CLIENT_BLKID_uvdc_0 = 0x85,
+ DBG_CLIENT_BLKID_uvdc_1 = 0x86,
+ DBG_CLIENT_BLKID_mcc3 = 0x87,
+ DBG_CLIENT_BLKID_cpg_0 = 0x88,
+ DBG_CLIENT_BLKID_cpg_1 = 0x89,
+ DBG_CLIENT_BLKID_gck = 0x8a,
+ DBG_CLIENT_BLKID_mcc1 = 0x8b,
+ DBG_CLIENT_BLKID_cpf_0 = 0x8c,
+ DBG_CLIENT_BLKID_cpf_1 = 0x8d,
+ DBG_CLIENT_BLKID_rlc = 0x8e,
+ DBG_CLIENT_BLKID_grbm = 0x8f,
+ DBG_CLIENT_BLKID_sammsp = 0x90,
+ DBG_CLIENT_BLKID_dci_pg = 0x91,
+ DBG_CLIENT_BLKID_dci_0 = 0x92,
+ DBG_CLIENT_BLKID_dccg0_0 = 0x93,
+ DBG_CLIENT_BLKID_dccg0_1 = 0x94,
+ DBG_CLIENT_BLKID_dcfe01_0 = 0x95,
+ DBG_CLIENT_BLKID_dcfe02_0 = 0x96,
+ DBG_CLIENT_BLKID_dcfe03_0 = 0x97,
+ DBG_CLIENT_BLKID_dcfe04_0 = 0x98,
+ DBG_CLIENT_BLKID_dcfe05_0 = 0x99,
+ DBG_CLIENT_BLKID_dcfe06_0 = 0x9a,
+ DBG_CLIENT_BLKID_RESERVED_LAST = 0x9b,
+} DebugBlockId;
+typedef enum DebugBlockId_OLD {
+ DBG_BLOCK_ID_RESERVED = 0x0,
+ DBG_BLOCK_ID_DBG = 0x1,
+ DBG_BLOCK_ID_VMC = 0x2,
+ DBG_BLOCK_ID_PDMA = 0x3,
+ DBG_BLOCK_ID_CG = 0x4,
+ DBG_BLOCK_ID_SRBM = 0x5,
+ DBG_BLOCK_ID_GRBM = 0x6,
+ DBG_BLOCK_ID_RLC = 0x7,
+ DBG_BLOCK_ID_CSC = 0x8,
+ DBG_BLOCK_ID_SEM = 0x9,
+ DBG_BLOCK_ID_IH = 0xa,
+ DBG_BLOCK_ID_SC = 0xb,
+ DBG_BLOCK_ID_SQ = 0xc,
+ DBG_BLOCK_ID_AVP = 0xd,
+ DBG_BLOCK_ID_GMCON = 0xe,
+ DBG_BLOCK_ID_SMU = 0xf,
+ DBG_BLOCK_ID_DMA0 = 0x10,
+ DBG_BLOCK_ID_DMA1 = 0x11,
+ DBG_BLOCK_ID_SPIM = 0x12,
+ DBG_BLOCK_ID_GDS = 0x13,
+ DBG_BLOCK_ID_SPIS = 0x14,
+ DBG_BLOCK_ID_UNUSED0 = 0x15,
+ DBG_BLOCK_ID_PA0 = 0x16,
+ DBG_BLOCK_ID_PA1 = 0x17,
+ DBG_BLOCK_ID_CP0 = 0x18,
+ DBG_BLOCK_ID_CP1 = 0x19,
+ DBG_BLOCK_ID_CP2 = 0x1a,
+ DBG_BLOCK_ID_UNUSED1 = 0x1b,
+ DBG_BLOCK_ID_UVDU = 0x1c,
+ DBG_BLOCK_ID_UVDM = 0x1d,
+ DBG_BLOCK_ID_VCE = 0x1e,
+ DBG_BLOCK_ID_UNUSED2 = 0x1f,
+ DBG_BLOCK_ID_VGT0 = 0x20,
+ DBG_BLOCK_ID_VGT1 = 0x21,
+ DBG_BLOCK_ID_IA = 0x22,
+ DBG_BLOCK_ID_UNUSED3 = 0x23,
+ DBG_BLOCK_ID_SCT0 = 0x24,
+ DBG_BLOCK_ID_SCT1 = 0x25,
+ DBG_BLOCK_ID_SPM0 = 0x26,
+ DBG_BLOCK_ID_SPM1 = 0x27,
+ DBG_BLOCK_ID_TCAA = 0x28,
+ DBG_BLOCK_ID_TCAB = 0x29,
+ DBG_BLOCK_ID_TCCA = 0x2a,
+ DBG_BLOCK_ID_TCCB = 0x2b,
+ DBG_BLOCK_ID_MCC0 = 0x2c,
+ DBG_BLOCK_ID_MCC1 = 0x2d,
+ DBG_BLOCK_ID_MCC2 = 0x2e,
+ DBG_BLOCK_ID_MCC3 = 0x2f,
+ DBG_BLOCK_ID_SX0 = 0x30,
+ DBG_BLOCK_ID_SX1 = 0x31,
+ DBG_BLOCK_ID_SX2 = 0x32,
+ DBG_BLOCK_ID_SX3 = 0x33,
+ DBG_BLOCK_ID_UNUSED4 = 0x34,
+ DBG_BLOCK_ID_UNUSED5 = 0x35,
+ DBG_BLOCK_ID_UNUSED6 = 0x36,
+ DBG_BLOCK_ID_UNUSED7 = 0x37,
+ DBG_BLOCK_ID_PC0 = 0x38,
+ DBG_BLOCK_ID_PC1 = 0x39,
+ DBG_BLOCK_ID_UNUSED8 = 0x3a,
+ DBG_BLOCK_ID_UNUSED9 = 0x3b,
+ DBG_BLOCK_ID_UNUSED10 = 0x3c,
+ DBG_BLOCK_ID_UNUSED11 = 0x3d,
+ DBG_BLOCK_ID_MCB = 0x3e,
+ DBG_BLOCK_ID_UNUSED12 = 0x3f,
+ DBG_BLOCK_ID_SCB0 = 0x40,
+ DBG_BLOCK_ID_SCB1 = 0x41,
+ DBG_BLOCK_ID_UNUSED13 = 0x42,
+ DBG_BLOCK_ID_UNUSED14 = 0x43,
+ DBG_BLOCK_ID_SCF0 = 0x44,
+ DBG_BLOCK_ID_SCF1 = 0x45,
+ DBG_BLOCK_ID_UNUSED15 = 0x46,
+ DBG_BLOCK_ID_UNUSED16 = 0x47,
+ DBG_BLOCK_ID_BCI0 = 0x48,
+ DBG_BLOCK_ID_BCI1 = 0x49,
+ DBG_BLOCK_ID_BCI2 = 0x4a,
+ DBG_BLOCK_ID_BCI3 = 0x4b,
+ DBG_BLOCK_ID_UNUSED17 = 0x4c,
+ DBG_BLOCK_ID_UNUSED18 = 0x4d,
+ DBG_BLOCK_ID_UNUSED19 = 0x4e,
+ DBG_BLOCK_ID_UNUSED20 = 0x4f,
+ DBG_BLOCK_ID_CB00 = 0x50,
+ DBG_BLOCK_ID_CB01 = 0x51,
+ DBG_BLOCK_ID_CB02 = 0x52,
+ DBG_BLOCK_ID_CB03 = 0x53,
+ DBG_BLOCK_ID_CB04 = 0x54,
+ DBG_BLOCK_ID_UNUSED21 = 0x55,
+ DBG_BLOCK_ID_UNUSED22 = 0x56,
+ DBG_BLOCK_ID_UNUSED23 = 0x57,
+ DBG_BLOCK_ID_CB10 = 0x58,
+ DBG_BLOCK_ID_CB11 = 0x59,
+ DBG_BLOCK_ID_CB12 = 0x5a,
+ DBG_BLOCK_ID_CB13 = 0x5b,
+ DBG_BLOCK_ID_CB14 = 0x5c,
+ DBG_BLOCK_ID_UNUSED24 = 0x5d,
+ DBG_BLOCK_ID_UNUSED25 = 0x5e,
+ DBG_BLOCK_ID_UNUSED26 = 0x5f,
+ DBG_BLOCK_ID_TCP0 = 0x60,
+ DBG_BLOCK_ID_TCP1 = 0x61,
+ DBG_BLOCK_ID_TCP2 = 0x62,
+ DBG_BLOCK_ID_TCP3 = 0x63,
+ DBG_BLOCK_ID_TCP4 = 0x64,
+ DBG_BLOCK_ID_TCP5 = 0x65,
+ DBG_BLOCK_ID_TCP6 = 0x66,
+ DBG_BLOCK_ID_TCP7 = 0x67,
+ DBG_BLOCK_ID_TCP8 = 0x68,
+ DBG_BLOCK_ID_TCP9 = 0x69,
+ DBG_BLOCK_ID_TCP10 = 0x6a,
+ DBG_BLOCK_ID_TCP11 = 0x6b,
+ DBG_BLOCK_ID_TCP12 = 0x6c,
+ DBG_BLOCK_ID_TCP13 = 0x6d,
+ DBG_BLOCK_ID_TCP14 = 0x6e,
+ DBG_BLOCK_ID_TCP15 = 0x6f,
+ DBG_BLOCK_ID_TCP16 = 0x70,
+ DBG_BLOCK_ID_TCP17 = 0x71,
+ DBG_BLOCK_ID_TCP18 = 0x72,
+ DBG_BLOCK_ID_TCP19 = 0x73,
+ DBG_BLOCK_ID_TCP20 = 0x74,
+ DBG_BLOCK_ID_TCP21 = 0x75,
+ DBG_BLOCK_ID_TCP22 = 0x76,
+ DBG_BLOCK_ID_TCP23 = 0x77,
+ DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
+ DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
+ DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
+ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
+ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
+ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
+ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
+ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
+ DBG_BLOCK_ID_DB00 = 0x80,
+ DBG_BLOCK_ID_DB01 = 0x81,
+ DBG_BLOCK_ID_DB02 = 0x82,
+ DBG_BLOCK_ID_DB03 = 0x83,
+ DBG_BLOCK_ID_DB04 = 0x84,
+ DBG_BLOCK_ID_UNUSED27 = 0x85,
+ DBG_BLOCK_ID_UNUSED28 = 0x86,
+ DBG_BLOCK_ID_UNUSED29 = 0x87,
+ DBG_BLOCK_ID_DB10 = 0x88,
+ DBG_BLOCK_ID_DB11 = 0x89,
+ DBG_BLOCK_ID_DB12 = 0x8a,
+ DBG_BLOCK_ID_DB13 = 0x8b,
+ DBG_BLOCK_ID_DB14 = 0x8c,
+ DBG_BLOCK_ID_UNUSED30 = 0x8d,
+ DBG_BLOCK_ID_UNUSED31 = 0x8e,
+ DBG_BLOCK_ID_UNUSED32 = 0x8f,
+ DBG_BLOCK_ID_TCC0 = 0x90,
+ DBG_BLOCK_ID_TCC1 = 0x91,
+ DBG_BLOCK_ID_TCC2 = 0x92,
+ DBG_BLOCK_ID_TCC3 = 0x93,
+ DBG_BLOCK_ID_TCC4 = 0x94,
+ DBG_BLOCK_ID_TCC5 = 0x95,
+ DBG_BLOCK_ID_TCC6 = 0x96,
+ DBG_BLOCK_ID_TCC7 = 0x97,
+ DBG_BLOCK_ID_SPS00 = 0x98,
+ DBG_BLOCK_ID_SPS01 = 0x99,
+ DBG_BLOCK_ID_SPS02 = 0x9a,
+ DBG_BLOCK_ID_SPS10 = 0x9b,
+ DBG_BLOCK_ID_SPS11 = 0x9c,
+ DBG_BLOCK_ID_SPS12 = 0x9d,
+ DBG_BLOCK_ID_UNUSED33 = 0x9e,
+ DBG_BLOCK_ID_UNUSED34 = 0x9f,
+ DBG_BLOCK_ID_TA00 = 0xa0,
+ DBG_BLOCK_ID_TA01 = 0xa1,
+ DBG_BLOCK_ID_TA02 = 0xa2,
+ DBG_BLOCK_ID_TA03 = 0xa3,
+ DBG_BLOCK_ID_TA04 = 0xa4,
+ DBG_BLOCK_ID_TA05 = 0xa5,
+ DBG_BLOCK_ID_TA06 = 0xa6,
+ DBG_BLOCK_ID_TA07 = 0xa7,
+ DBG_BLOCK_ID_TA08 = 0xa8,
+ DBG_BLOCK_ID_TA09 = 0xa9,
+ DBG_BLOCK_ID_TA0A = 0xaa,
+ DBG_BLOCK_ID_TA0B = 0xab,
+ DBG_BLOCK_ID_UNUSED35 = 0xac,
+ DBG_BLOCK_ID_UNUSED36 = 0xad,
+ DBG_BLOCK_ID_UNUSED37 = 0xae,
+ DBG_BLOCK_ID_UNUSED38 = 0xaf,
+ DBG_BLOCK_ID_TA10 = 0xb0,
+ DBG_BLOCK_ID_TA11 = 0xb1,
+ DBG_BLOCK_ID_TA12 = 0xb2,
+ DBG_BLOCK_ID_TA13 = 0xb3,
+ DBG_BLOCK_ID_TA14 = 0xb4,
+ DBG_BLOCK_ID_TA15 = 0xb5,
+ DBG_BLOCK_ID_TA16 = 0xb6,
+ DBG_BLOCK_ID_TA17 = 0xb7,
+ DBG_BLOCK_ID_TA18 = 0xb8,
+ DBG_BLOCK_ID_TA19 = 0xb9,
+ DBG_BLOCK_ID_TA1A = 0xba,
+ DBG_BLOCK_ID_TA1B = 0xbb,
+ DBG_BLOCK_ID_UNUSED39 = 0xbc,
+ DBG_BLOCK_ID_UNUSED40 = 0xbd,
+ DBG_BLOCK_ID_UNUSED41 = 0xbe,
+ DBG_BLOCK_ID_UNUSED42 = 0xbf,
+ DBG_BLOCK_ID_TD00 = 0xc0,
+ DBG_BLOCK_ID_TD01 = 0xc1,
+ DBG_BLOCK_ID_TD02 = 0xc2,
+ DBG_BLOCK_ID_TD03 = 0xc3,
+ DBG_BLOCK_ID_TD04 = 0xc4,
+ DBG_BLOCK_ID_TD05 = 0xc5,
+ DBG_BLOCK_ID_TD06 = 0xc6,
+ DBG_BLOCK_ID_TD07 = 0xc7,
+ DBG_BLOCK_ID_TD08 = 0xc8,
+ DBG_BLOCK_ID_TD09 = 0xc9,
+ DBG_BLOCK_ID_TD0A = 0xca,
+ DBG_BLOCK_ID_TD0B = 0xcb,
+ DBG_BLOCK_ID_UNUSED43 = 0xcc,
+ DBG_BLOCK_ID_UNUSED44 = 0xcd,
+ DBG_BLOCK_ID_UNUSED45 = 0xce,
+ DBG_BLOCK_ID_UNUSED46 = 0xcf,
+ DBG_BLOCK_ID_TD10 = 0xd0,
+ DBG_BLOCK_ID_TD11 = 0xd1,
+ DBG_BLOCK_ID_TD12 = 0xd2,
+ DBG_BLOCK_ID_TD13 = 0xd3,
+ DBG_BLOCK_ID_TD14 = 0xd4,
+ DBG_BLOCK_ID_TD15 = 0xd5,
+ DBG_BLOCK_ID_TD16 = 0xd6,
+ DBG_BLOCK_ID_TD17 = 0xd7,
+ DBG_BLOCK_ID_TD18 = 0xd8,
+ DBG_BLOCK_ID_TD19 = 0xd9,
+ DBG_BLOCK_ID_TD1A = 0xda,
+ DBG_BLOCK_ID_TD1B = 0xdb,
+ DBG_BLOCK_ID_UNUSED47 = 0xdc,
+ DBG_BLOCK_ID_UNUSED48 = 0xdd,
+ DBG_BLOCK_ID_UNUSED49 = 0xde,
+ DBG_BLOCK_ID_UNUSED50 = 0xdf,
+ DBG_BLOCK_ID_MCD0 = 0xe0,
+ DBG_BLOCK_ID_MCD1 = 0xe1,
+ DBG_BLOCK_ID_MCD2 = 0xe2,
+ DBG_BLOCK_ID_MCD3 = 0xe3,
+ DBG_BLOCK_ID_MCD4 = 0xe4,
+ DBG_BLOCK_ID_MCD5 = 0xe5,
+ DBG_BLOCK_ID_UNUSED51 = 0xe6,
+ DBG_BLOCK_ID_UNUSED52 = 0xe7,
+} DebugBlockId_OLD;
+typedef enum DebugBlockId_BY2 {
+ DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
+ DBG_BLOCK_ID_VMC_BY2 = 0x1,
+ DBG_BLOCK_ID_CG_BY2 = 0x2,
+ DBG_BLOCK_ID_GRBM_BY2 = 0x3,
+ DBG_BLOCK_ID_CSC_BY2 = 0x4,
+ DBG_BLOCK_ID_IH_BY2 = 0x5,
+ DBG_BLOCK_ID_SQ_BY2 = 0x6,
+ DBG_BLOCK_ID_GMCON_BY2 = 0x7,
+ DBG_BLOCK_ID_DMA0_BY2 = 0x8,
+ DBG_BLOCK_ID_SPIM_BY2 = 0x9,
+ DBG_BLOCK_ID_SPIS_BY2 = 0xa,
+ DBG_BLOCK_ID_PA0_BY2 = 0xb,
+ DBG_BLOCK_ID_CP0_BY2 = 0xc,
+ DBG_BLOCK_ID_CP2_BY2 = 0xd,
+ DBG_BLOCK_ID_UVDU_BY2 = 0xe,
+ DBG_BLOCK_ID_VCE_BY2 = 0xf,
+ DBG_BLOCK_ID_VGT0_BY2 = 0x10,
+ DBG_BLOCK_ID_IA_BY2 = 0x11,
+ DBG_BLOCK_ID_SCT0_BY2 = 0x12,
+ DBG_BLOCK_ID_SPM0_BY2 = 0x13,
+ DBG_BLOCK_ID_TCAA_BY2 = 0x14,
+ DBG_BLOCK_ID_TCCA_BY2 = 0x15,
+ DBG_BLOCK_ID_MCC0_BY2 = 0x16,
+ DBG_BLOCK_ID_MCC2_BY2 = 0x17,
+ DBG_BLOCK_ID_SX0_BY2 = 0x18,
+ DBG_BLOCK_ID_SX2_BY2 = 0x19,
+ DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
+ DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
+ DBG_BLOCK_ID_PC0_BY2 = 0x1c,
+ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
+ DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
+ DBG_BLOCK_ID_MCB_BY2 = 0x1f,
+ DBG_BLOCK_ID_SCB0_BY2 = 0x20,
+ DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
+ DBG_BLOCK_ID_SCF0_BY2 = 0x22,
+ DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
+ DBG_BLOCK_ID_BCI0_BY2 = 0x24,
+ DBG_BLOCK_ID_BCI2_BY2 = 0x25,
+ DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
+ DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
+ DBG_BLOCK_ID_CB00_BY2 = 0x28,
+ DBG_BLOCK_ID_CB02_BY2 = 0x29,
+ DBG_BLOCK_ID_CB04_BY2 = 0x2a,
+ DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
+ DBG_BLOCK_ID_CB10_BY2 = 0x2c,
+ DBG_BLOCK_ID_CB12_BY2 = 0x2d,
+ DBG_BLOCK_ID_CB14_BY2 = 0x2e,
+ DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
+ DBG_BLOCK_ID_TCP0_BY2 = 0x30,
+ DBG_BLOCK_ID_TCP2_BY2 = 0x31,
+ DBG_BLOCK_ID_TCP4_BY2 = 0x32,
+ DBG_BLOCK_ID_TCP6_BY2 = 0x33,
+ DBG_BLOCK_ID_TCP8_BY2 = 0x34,
+ DBG_BLOCK_ID_TCP10_BY2 = 0x35,
+ DBG_BLOCK_ID_TCP12_BY2 = 0x36,
+ DBG_BLOCK_ID_TCP14_BY2 = 0x37,
+ DBG_BLOCK_ID_TCP16_BY2 = 0x38,
+ DBG_BLOCK_ID_TCP18_BY2 = 0x39,
+ DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
+ DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
+ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
+ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
+ DBG_BLOCK_ID_DB00_BY2 = 0x40,
+ DBG_BLOCK_ID_DB02_BY2 = 0x41,
+ DBG_BLOCK_ID_DB04_BY2 = 0x42,
+ DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
+ DBG_BLOCK_ID_DB10_BY2 = 0x44,
+ DBG_BLOCK_ID_DB12_BY2 = 0x45,
+ DBG_BLOCK_ID_DB14_BY2 = 0x46,
+ DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
+ DBG_BLOCK_ID_TCC0_BY2 = 0x48,
+ DBG_BLOCK_ID_TCC2_BY2 = 0x49,
+ DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
+ DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
+ DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
+ DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
+ DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
+ DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
+ DBG_BLOCK_ID_TA00_BY2 = 0x50,
+ DBG_BLOCK_ID_TA02_BY2 = 0x51,
+ DBG_BLOCK_ID_TA04_BY2 = 0x52,
+ DBG_BLOCK_ID_TA06_BY2 = 0x53,
+ DBG_BLOCK_ID_TA08_BY2 = 0x54,
+ DBG_BLOCK_ID_TA0A_BY2 = 0x55,
+ DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
+ DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
+ DBG_BLOCK_ID_TA10_BY2 = 0x58,
+ DBG_BLOCK_ID_TA12_BY2 = 0x59,
+ DBG_BLOCK_ID_TA14_BY2 = 0x5a,
+ DBG_BLOCK_ID_TA16_BY2 = 0x5b,
+ DBG_BLOCK_ID_TA18_BY2 = 0x5c,
+ DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
+ DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
+ DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
+ DBG_BLOCK_ID_TD00_BY2 = 0x60,
+ DBG_BLOCK_ID_TD02_BY2 = 0x61,
+ DBG_BLOCK_ID_TD04_BY2 = 0x62,
+ DBG_BLOCK_ID_TD06_BY2 = 0x63,
+ DBG_BLOCK_ID_TD08_BY2 = 0x64,
+ DBG_BLOCK_ID_TD0A_BY2 = 0x65,
+ DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
+ DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
+ DBG_BLOCK_ID_TD10_BY2 = 0x68,
+ DBG_BLOCK_ID_TD12_BY2 = 0x69,
+ DBG_BLOCK_ID_TD14_BY2 = 0x6a,
+ DBG_BLOCK_ID_TD16_BY2 = 0x6b,
+ DBG_BLOCK_ID_TD18_BY2 = 0x6c,
+ DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
+ DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
+ DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
+ DBG_BLOCK_ID_MCD0_BY2 = 0x70,
+ DBG_BLOCK_ID_MCD2_BY2 = 0x71,
+ DBG_BLOCK_ID_MCD4_BY2 = 0x72,
+ DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
+} DebugBlockId_BY2;
+typedef enum DebugBlockId_BY4 {
+ DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
+ DBG_BLOCK_ID_CG_BY4 = 0x1,
+ DBG_BLOCK_ID_CSC_BY4 = 0x2,
+ DBG_BLOCK_ID_SQ_BY4 = 0x3,
+ DBG_BLOCK_ID_DMA0_BY4 = 0x4,
+ DBG_BLOCK_ID_SPIS_BY4 = 0x5,
+ DBG_BLOCK_ID_CP0_BY4 = 0x6,
+ DBG_BLOCK_ID_UVDU_BY4 = 0x7,
+ DBG_BLOCK_ID_VGT0_BY4 = 0x8,
+ DBG_BLOCK_ID_SCT0_BY4 = 0x9,
+ DBG_BLOCK_ID_TCAA_BY4 = 0xa,
+ DBG_BLOCK_ID_MCC0_BY4 = 0xb,
+ DBG_BLOCK_ID_SX0_BY4 = 0xc,
+ DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
+ DBG_BLOCK_ID_PC0_BY4 = 0xe,
+ DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
+ DBG_BLOCK_ID_SCB0_BY4 = 0x10,
+ DBG_BLOCK_ID_SCF0_BY4 = 0x11,
+ DBG_BLOCK_ID_BCI0_BY4 = 0x12,
+ DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
+ DBG_BLOCK_ID_CB00_BY4 = 0x14,
+ DBG_BLOCK_ID_CB04_BY4 = 0x15,
+ DBG_BLOCK_ID_CB10_BY4 = 0x16,
+ DBG_BLOCK_ID_CB14_BY4 = 0x17,
+ DBG_BLOCK_ID_TCP0_BY4 = 0x18,
+ DBG_BLOCK_ID_TCP4_BY4 = 0x19,
+ DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
+ DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
+ DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
+ DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
+ DBG_BLOCK_ID_DB_BY4 = 0x20,
+ DBG_BLOCK_ID_DB04_BY4 = 0x21,
+ DBG_BLOCK_ID_DB10_BY4 = 0x22,
+ DBG_BLOCK_ID_DB14_BY4 = 0x23,
+ DBG_BLOCK_ID_TCC0_BY4 = 0x24,
+ DBG_BLOCK_ID_TCC4_BY4 = 0x25,
+ DBG_BLOCK_ID_SPS00_BY4 = 0x26,
+ DBG_BLOCK_ID_SPS11_BY4 = 0x27,
+ DBG_BLOCK_ID_TA00_BY4 = 0x28,
+ DBG_BLOCK_ID_TA04_BY4 = 0x29,
+ DBG_BLOCK_ID_TA08_BY4 = 0x2a,
+ DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
+ DBG_BLOCK_ID_TA10_BY4 = 0x2c,
+ DBG_BLOCK_ID_TA14_BY4 = 0x2d,
+ DBG_BLOCK_ID_TA18_BY4 = 0x2e,
+ DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
+ DBG_BLOCK_ID_TD00_BY4 = 0x30,
+ DBG_BLOCK_ID_TD04_BY4 = 0x31,
+ DBG_BLOCK_ID_TD08_BY4 = 0x32,
+ DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
+ DBG_BLOCK_ID_TD10_BY4 = 0x34,
+ DBG_BLOCK_ID_TD14_BY4 = 0x35,
+ DBG_BLOCK_ID_TD18_BY4 = 0x36,
+ DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
+ DBG_BLOCK_ID_MCD0_BY4 = 0x38,
+ DBG_BLOCK_ID_MCD4_BY4 = 0x39,
+} DebugBlockId_BY4;
+typedef enum DebugBlockId_BY8 {
+ DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
+ DBG_BLOCK_ID_CSC_BY8 = 0x1,
+ DBG_BLOCK_ID_DMA0_BY8 = 0x2,
+ DBG_BLOCK_ID_CP0_BY8 = 0x3,
+ DBG_BLOCK_ID_VGT0_BY8 = 0x4,
+ DBG_BLOCK_ID_TCAA_BY8 = 0x5,
+ DBG_BLOCK_ID_SX0_BY8 = 0x6,
+ DBG_BLOCK_ID_PC0_BY8 = 0x7,
+ DBG_BLOCK_ID_SCB0_BY8 = 0x8,
+ DBG_BLOCK_ID_BCI0_BY8 = 0x9,
+ DBG_BLOCK_ID_CB00_BY8 = 0xa,
+ DBG_BLOCK_ID_CB10_BY8 = 0xb,
+ DBG_BLOCK_ID_TCP0_BY8 = 0xc,
+ DBG_BLOCK_ID_TCP8_BY8 = 0xd,
+ DBG_BLOCK_ID_TCP16_BY8 = 0xe,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
+ DBG_BLOCK_ID_DB00_BY8 = 0x10,
+ DBG_BLOCK_ID_DB10_BY8 = 0x11,
+ DBG_BLOCK_ID_TCC0_BY8 = 0x12,
+ DBG_BLOCK_ID_SPS00_BY8 = 0x13,
+ DBG_BLOCK_ID_TA00_BY8 = 0x14,
+ DBG_BLOCK_ID_TA08_BY8 = 0x15,
+ DBG_BLOCK_ID_TA10_BY8 = 0x16,
+ DBG_BLOCK_ID_TA18_BY8 = 0x17,
+ DBG_BLOCK_ID_TD00_BY8 = 0x18,
+ DBG_BLOCK_ID_TD08_BY8 = 0x19,
+ DBG_BLOCK_ID_TD10_BY8 = 0x1a,
+ DBG_BLOCK_ID_TD18_BY8 = 0x1b,
+ DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
+} DebugBlockId_BY8;
+typedef enum DebugBlockId_BY16 {
+ DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
+ DBG_BLOCK_ID_DMA0_BY16 = 0x1,
+ DBG_BLOCK_ID_VGT0_BY16 = 0x2,
+ DBG_BLOCK_ID_SX0_BY16 = 0x3,
+ DBG_BLOCK_ID_SCB0_BY16 = 0x4,
+ DBG_BLOCK_ID_CB00_BY16 = 0x5,
+ DBG_BLOCK_ID_TCP0_BY16 = 0x6,
+ DBG_BLOCK_ID_TCP16_BY16 = 0x7,
+ DBG_BLOCK_ID_DB00_BY16 = 0x8,
+ DBG_BLOCK_ID_TCC0_BY16 = 0x9,
+ DBG_BLOCK_ID_TA00_BY16 = 0xa,
+ DBG_BLOCK_ID_TA10_BY16 = 0xb,
+ DBG_BLOCK_ID_TD00_BY16 = 0xc,
+ DBG_BLOCK_ID_TD10_BY16 = 0xd,
+ DBG_BLOCK_ID_MCD0_BY16 = 0xe,
+} DebugBlockId_BY16;
+typedef enum ColorTransform {
+ DCC_CT_AUTO = 0x0,
+ DCC_CT_NONE = 0x1,
+ ABGR_TO_A_BG_G_RB = 0x2,
+ BGRA_TO_BG_G_RB_A = 0x3,
+} ColorTransform;
+typedef enum CompareRef {
+ REF_NEVER = 0x0,
+ REF_LESS = 0x1,
+ REF_EQUAL = 0x2,
+ REF_LEQUAL = 0x3,
+ REF_GREATER = 0x4,
+ REF_NOTEQUAL = 0x5,
+ REF_GEQUAL = 0x6,
+ REF_ALWAYS = 0x7,
+} CompareRef;
+typedef enum ReadSize {
+ READ_256_BITS = 0x0,
+ READ_512_BITS = 0x1,
+} ReadSize;
+typedef enum DepthFormat {
+ DEPTH_INVALID = 0x0,
+ DEPTH_16 = 0x1,
+ DEPTH_X8_24 = 0x2,
+ DEPTH_8_24 = 0x3,
+ DEPTH_X8_24_FLOAT = 0x4,
+ DEPTH_8_24_FLOAT = 0x5,
+ DEPTH_32_FLOAT = 0x6,
+ DEPTH_X24_8_32_FLOAT = 0x7,
+} DepthFormat;
+typedef enum ZFormat {
+ Z_INVALID = 0x0,
+ Z_16 = 0x1,
+ Z_24 = 0x2,
+ Z_32_FLOAT = 0x3,
+} ZFormat;
+typedef enum StencilFormat {
+ STENCIL_INVALID = 0x0,
+ STENCIL_8 = 0x1,
+} StencilFormat;
+typedef enum CmaskMode {
+ CMASK_CLEAR_NONE = 0x0,
+ CMASK_CLEAR_ONE = 0x1,
+ CMASK_CLEAR_ALL = 0x2,
+ CMASK_ANY_EXPANDED = 0x3,
+ CMASK_ALPHA0_FRAG1 = 0x4,
+ CMASK_ALPHA0_FRAG2 = 0x5,
+ CMASK_ALPHA0_FRAG4 = 0x6,
+ CMASK_ALPHA0_FRAGS = 0x7,
+ CMASK_ALPHA1_FRAG1 = 0x8,
+ CMASK_ALPHA1_FRAG2 = 0x9,
+ CMASK_ALPHA1_FRAG4 = 0xa,
+ CMASK_ALPHA1_FRAGS = 0xb,
+ CMASK_ALPHAX_FRAG1 = 0xc,
+ CMASK_ALPHAX_FRAG2 = 0xd,
+ CMASK_ALPHAX_FRAG4 = 0xe,
+ CMASK_ALPHAX_FRAGS = 0xf,
+} CmaskMode;
+typedef enum QuadExportFormat {
+ EXPORT_UNUSED = 0x0,
+ EXPORT_32_R = 0x1,
+ EXPORT_32_GR = 0x2,
+ EXPORT_32_AR = 0x3,
+ EXPORT_FP16_ABGR = 0x4,
+ EXPORT_UNSIGNED16_ABGR = 0x5,
+ EXPORT_SIGNED16_ABGR = 0x6,
+ EXPORT_32_ABGR = 0x7,
+} QuadExportFormat;
+typedef enum QuadExportFormatOld {
+ EXPORT_4P_32BPC_ABGR = 0x0,
+ EXPORT_4P_16BPC_ABGR = 0x1,
+ EXPORT_4P_32BPC_GR = 0x2,
+ EXPORT_4P_32BPC_AR = 0x3,
+ EXPORT_2P_32BPC_ABGR = 0x4,
+ EXPORT_8P_32BPC_R = 0x5,
+} QuadExportFormatOld;
+typedef enum ColorFormat {
+ COLOR_INVALID = 0x0,
+ COLOR_8 = 0x1,
+ COLOR_16 = 0x2,
+ COLOR_8_8 = 0x3,
+ COLOR_32 = 0x4,
+ COLOR_16_16 = 0x5,
+ COLOR_10_11_11 = 0x6,
+ COLOR_11_11_10 = 0x7,
+ COLOR_10_10_10_2 = 0x8,
+ COLOR_2_10_10_10 = 0x9,
+ COLOR_8_8_8_8 = 0xa,
+ COLOR_32_32 = 0xb,
+ COLOR_16_16_16_16 = 0xc,
+ COLOR_RESERVED_13 = 0xd,
+ COLOR_32_32_32_32 = 0xe,
+ COLOR_RESERVED_15 = 0xf,
+ COLOR_5_6_5 = 0x10,
+ COLOR_1_5_5_5 = 0x11,
+ COLOR_5_5_5_1 = 0x12,
+ COLOR_4_4_4_4 = 0x13,
+ COLOR_8_24 = 0x14,
+ COLOR_24_8 = 0x15,
+ COLOR_X24_8_32_FLOAT = 0x16,
+ COLOR_RESERVED_23 = 0x17,
+} ColorFormat;
+typedef enum SurfaceFormat {
+ FMT_INVALID = 0x0,
+ FMT_8 = 0x1,
+ FMT_16 = 0x2,
+ FMT_8_8 = 0x3,
+ FMT_32 = 0x4,
+ FMT_16_16 = 0x5,
+ FMT_10_11_11 = 0x6,
+ FMT_11_11_10 = 0x7,
+ FMT_10_10_10_2 = 0x8,
+ FMT_2_10_10_10 = 0x9,
+ FMT_8_8_8_8 = 0xa,
+ FMT_32_32 = 0xb,
+ FMT_16_16_16_16 = 0xc,
+ FMT_32_32_32 = 0xd,
+ FMT_32_32_32_32 = 0xe,
+ FMT_RESERVED_4 = 0xf,
+ FMT_5_6_5 = 0x10,
+ FMT_1_5_5_5 = 0x11,
+ FMT_5_5_5_1 = 0x12,
+ FMT_4_4_4_4 = 0x13,
+ FMT_8_24 = 0x14,
+ FMT_24_8 = 0x15,
+ FMT_X24_8_32_FLOAT = 0x16,
+ FMT_RESERVED_33 = 0x17,
+ FMT_11_11_10_FLOAT = 0x18,
+ FMT_16_FLOAT = 0x19,
+ FMT_32_FLOAT = 0x1a,
+ FMT_16_16_FLOAT = 0x1b,
+ FMT_8_24_FLOAT = 0x1c,
+ FMT_24_8_FLOAT = 0x1d,
+ FMT_32_32_FLOAT = 0x1e,
+ FMT_10_11_11_FLOAT = 0x1f,
+ FMT_16_16_16_16_FLOAT = 0x20,
+ FMT_3_3_2 = 0x21,
+ FMT_6_5_5 = 0x22,
+ FMT_32_32_32_32_FLOAT = 0x23,
+ FMT_RESERVED_36 = 0x24,
+ FMT_1 = 0x25,
+ FMT_1_REVERSED = 0x26,
+ FMT_GB_GR = 0x27,
+ FMT_BG_RG = 0x28,
+ FMT_32_AS_8 = 0x29,
+ FMT_32_AS_8_8 = 0x2a,
+ FMT_5_9_9_9_SHAREDEXP = 0x2b,
+ FMT_8_8_8 = 0x2c,
+ FMT_16_16_16 = 0x2d,
+ FMT_16_16_16_FLOAT = 0x2e,
+ FMT_4_4 = 0x2f,
+ FMT_32_32_32_FLOAT = 0x30,
+ FMT_BC1 = 0x31,
+ FMT_BC2 = 0x32,
+ FMT_BC3 = 0x33,
+ FMT_BC4 = 0x34,
+ FMT_BC5 = 0x35,
+ FMT_BC6 = 0x36,
+ FMT_BC7 = 0x37,
+ FMT_32_AS_32_32_32_32 = 0x38,
+ FMT_APC3 = 0x39,
+ FMT_APC4 = 0x3a,
+ FMT_APC5 = 0x3b,
+ FMT_APC6 = 0x3c,
+ FMT_APC7 = 0x3d,
+ FMT_CTX1 = 0x3e,
+ FMT_RESERVED_63 = 0x3f,
+} SurfaceFormat;
+typedef enum BUF_DATA_FORMAT {
+ BUF_DATA_FORMAT_INVALID = 0x0,
+ BUF_DATA_FORMAT_8 = 0x1,
+ BUF_DATA_FORMAT_16 = 0x2,
+ BUF_DATA_FORMAT_8_8 = 0x3,
+ BUF_DATA_FORMAT_32 = 0x4,
+ BUF_DATA_FORMAT_16_16 = 0x5,
+ BUF_DATA_FORMAT_10_11_11 = 0x6,
+ BUF_DATA_FORMAT_11_11_10 = 0x7,
+ BUF_DATA_FORMAT_10_10_10_2 = 0x8,
+ BUF_DATA_FORMAT_2_10_10_10 = 0x9,
+ BUF_DATA_FORMAT_8_8_8_8 = 0xa,
+ BUF_DATA_FORMAT_32_32 = 0xb,
+ BUF_DATA_FORMAT_16_16_16_16 = 0xc,
+ BUF_DATA_FORMAT_32_32_32 = 0xd,
+ BUF_DATA_FORMAT_32_32_32_32 = 0xe,
+ BUF_DATA_FORMAT_RESERVED_15 = 0xf,
+} BUF_DATA_FORMAT;
+typedef enum IMG_DATA_FORMAT {
+ IMG_DATA_FORMAT_INVALID = 0x0,
+ IMG_DATA_FORMAT_8 = 0x1,
+ IMG_DATA_FORMAT_16 = 0x2,
+ IMG_DATA_FORMAT_8_8 = 0x3,
+ IMG_DATA_FORMAT_32 = 0x4,
+ IMG_DATA_FORMAT_16_16 = 0x5,
+ IMG_DATA_FORMAT_10_11_11 = 0x6,
+ IMG_DATA_FORMAT_11_11_10 = 0x7,
+ IMG_DATA_FORMAT_10_10_10_2 = 0x8,
+ IMG_DATA_FORMAT_2_10_10_10 = 0x9,
+ IMG_DATA_FORMAT_8_8_8_8 = 0xa,
+ IMG_DATA_FORMAT_32_32 = 0xb,
+ IMG_DATA_FORMAT_16_16_16_16 = 0xc,
+ IMG_DATA_FORMAT_32_32_32 = 0xd,
+ IMG_DATA_FORMAT_32_32_32_32 = 0xe,
+ IMG_DATA_FORMAT_RESERVED_15 = 0xf,
+ IMG_DATA_FORMAT_5_6_5 = 0x10,
+ IMG_DATA_FORMAT_1_5_5_5 = 0x11,
+ IMG_DATA_FORMAT_5_5_5_1 = 0x12,
+ IMG_DATA_FORMAT_4_4_4_4 = 0x13,
+ IMG_DATA_FORMAT_8_24 = 0x14,
+ IMG_DATA_FORMAT_24_8 = 0x15,
+ IMG_DATA_FORMAT_X24_8_32 = 0x16,
+ IMG_DATA_FORMAT_RESERVED_23 = 0x17,
+ IMG_DATA_FORMAT_RESERVED_24 = 0x18,
+ IMG_DATA_FORMAT_RESERVED_25 = 0x19,
+ IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
+ IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
+ IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
+ IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
+ IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
+ IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
+ IMG_DATA_FORMAT_GB_GR = 0x20,
+ IMG_DATA_FORMAT_BG_RG = 0x21,
+ IMG_DATA_FORMAT_5_9_9_9 = 0x22,
+ IMG_DATA_FORMAT_BC1 = 0x23,
+ IMG_DATA_FORMAT_BC2 = 0x24,
+ IMG_DATA_FORMAT_BC3 = 0x25,
+ IMG_DATA_FORMAT_BC4 = 0x26,
+ IMG_DATA_FORMAT_BC5 = 0x27,
+ IMG_DATA_FORMAT_BC6 = 0x28,
+ IMG_DATA_FORMAT_BC7 = 0x29,
+ IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
+ IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
+ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
+ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
+ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
+ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
+ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
+ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
+ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
+ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
+ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
+ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
+ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
+ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
+ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
+ IMG_DATA_FORMAT_4_4 = 0x39,
+ IMG_DATA_FORMAT_6_5_5 = 0x3a,
+ IMG_DATA_FORMAT_1 = 0x3b,
+ IMG_DATA_FORMAT_1_REVERSED = 0x3c,
+ IMG_DATA_FORMAT_32_AS_8 = 0x3d,
+ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
+ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
+} IMG_DATA_FORMAT;
+typedef enum BUF_NUM_FORMAT {
+ BUF_NUM_FORMAT_UNORM = 0x0,
+ BUF_NUM_FORMAT_SNORM = 0x1,
+ BUF_NUM_FORMAT_USCALED = 0x2,
+ BUF_NUM_FORMAT_SSCALED = 0x3,
+ BUF_NUM_FORMAT_UINT = 0x4,
+ BUF_NUM_FORMAT_SINT = 0x5,
+ BUF_NUM_FORMAT_RESERVED_6 = 0x6,
+ BUF_NUM_FORMAT_FLOAT = 0x7,
+} BUF_NUM_FORMAT;
+typedef enum IMG_NUM_FORMAT {
+ IMG_NUM_FORMAT_UNORM = 0x0,
+ IMG_NUM_FORMAT_SNORM = 0x1,
+ IMG_NUM_FORMAT_USCALED = 0x2,
+ IMG_NUM_FORMAT_SSCALED = 0x3,
+ IMG_NUM_FORMAT_UINT = 0x4,
+ IMG_NUM_FORMAT_SINT = 0x5,
+ IMG_NUM_FORMAT_RESERVED_6 = 0x6,
+ IMG_NUM_FORMAT_FLOAT = 0x7,
+ IMG_NUM_FORMAT_RESERVED_8 = 0x8,
+ IMG_NUM_FORMAT_SRGB = 0x9,
+ IMG_NUM_FORMAT_RESERVED_10 = 0xa,
+ IMG_NUM_FORMAT_RESERVED_11 = 0xb,
+ IMG_NUM_FORMAT_RESERVED_12 = 0xc,
+ IMG_NUM_FORMAT_RESERVED_13 = 0xd,
+ IMG_NUM_FORMAT_RESERVED_14 = 0xe,
+ IMG_NUM_FORMAT_RESERVED_15 = 0xf,
+} IMG_NUM_FORMAT;
+typedef enum TileType {
+ ARRAY_COLOR_TILE = 0x0,
+ ARRAY_DEPTH_TILE = 0x1,
+} TileType;
+typedef enum NonDispTilingOrder {
+ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
+ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
+} NonDispTilingOrder;
+typedef enum MicroTileMode {
+ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
+ ADDR_SURF_THIN_MICRO_TILING = 0x1,
+ ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
+ ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
+ ADDR_SURF_THICK_MICRO_TILING = 0x4,
+} MicroTileMode;
+typedef enum TileSplit {
+ ADDR_SURF_TILE_SPLIT_64B = 0x0,
+ ADDR_SURF_TILE_SPLIT_128B = 0x1,
+ ADDR_SURF_TILE_SPLIT_256B = 0x2,
+ ADDR_SURF_TILE_SPLIT_512B = 0x3,
+ ADDR_SURF_TILE_SPLIT_1KB = 0x4,
+ ADDR_SURF_TILE_SPLIT_2KB = 0x5,
+ ADDR_SURF_TILE_SPLIT_4KB = 0x6,
+} TileSplit;
+typedef enum SampleSplit {
+ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
+ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
+ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
+ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
+} SampleSplit;
+typedef enum PipeConfig {
+ ADDR_SURF_P2 = 0x0,
+ ADDR_SURF_P2_RESERVED0 = 0x1,
+ ADDR_SURF_P2_RESERVED1 = 0x2,
+ ADDR_SURF_P2_RESERVED2 = 0x3,
+ ADDR_SURF_P4_8x16 = 0x4,
+ ADDR_SURF_P4_16x16 = 0x5,
+ ADDR_SURF_P4_16x32 = 0x6,
+ ADDR_SURF_P4_32x32 = 0x7,
+ ADDR_SURF_P8_16x16_8x16 = 0x8,
+ ADDR_SURF_P8_16x32_8x16 = 0x9,
+ ADDR_SURF_P8_32x32_8x16 = 0xa,
+ ADDR_SURF_P8_16x32_16x16 = 0xb,
+ ADDR_SURF_P8_32x32_16x16 = 0xc,
+ ADDR_SURF_P8_32x32_16x32 = 0xd,
+ ADDR_SURF_P8_32x64_32x32 = 0xe,
+ ADDR_SURF_P8_RESERVED0 = 0xf,
+ ADDR_SURF_P16_32x32_8x16 = 0x10,
+ ADDR_SURF_P16_32x32_16x16 = 0x11,
+} PipeConfig;
+typedef enum NumBanks {
+ ADDR_SURF_2_BANK = 0x0,
+ ADDR_SURF_4_BANK = 0x1,
+ ADDR_SURF_8_BANK = 0x2,
+ ADDR_SURF_16_BANK = 0x3,
+} NumBanks;
+typedef enum BankWidth {
+ ADDR_SURF_BANK_WIDTH_1 = 0x0,
+ ADDR_SURF_BANK_WIDTH_2 = 0x1,
+ ADDR_SURF_BANK_WIDTH_4 = 0x2,
+ ADDR_SURF_BANK_WIDTH_8 = 0x3,
+} BankWidth;
+typedef enum BankHeight {
+ ADDR_SURF_BANK_HEIGHT_1 = 0x0,
+ ADDR_SURF_BANK_HEIGHT_2 = 0x1,
+ ADDR_SURF_BANK_HEIGHT_4 = 0x2,
+ ADDR_SURF_BANK_HEIGHT_8 = 0x3,
+} BankHeight;
+typedef enum BankWidthHeight {
+ ADDR_SURF_BANK_WH_1 = 0x0,
+ ADDR_SURF_BANK_WH_2 = 0x1,
+ ADDR_SURF_BANK_WH_4 = 0x2,
+ ADDR_SURF_BANK_WH_8 = 0x3,
+} BankWidthHeight;
+typedef enum MacroTileAspect {
+ ADDR_SURF_MACRO_ASPECT_1 = 0x0,
+ ADDR_SURF_MACRO_ASPECT_2 = 0x1,
+ ADDR_SURF_MACRO_ASPECT_4 = 0x2,
+ ADDR_SURF_MACRO_ASPECT_8 = 0x3,
+} MacroTileAspect;
+typedef enum GATCL1RequestType {
+ GATCL1_TYPE_NORMAL = 0x0,
+ GATCL1_TYPE_SHOOTDOWN = 0x1,
+ GATCL1_TYPE_BYPASS = 0x2,
+} GATCL1RequestType;
+typedef enum TCC_CACHE_POLICIES {
+ TCC_CACHE_POLICY_LRU = 0x0,
+ TCC_CACHE_POLICY_STREAM = 0x1,
+} TCC_CACHE_POLICIES;
+typedef enum MTYPE {
+ MTYPE_NC_NV = 0x0,
+ MTYPE_NC = 0x1,
+ MTYPE_CC = 0x2,
+ MTYPE_UC = 0x3,
+} MTYPE;
+typedef enum PERFMON_COUNTER_MODE {
+ PERFMON_COUNTER_MODE_ACCUM = 0x0,
+ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
+ PERFMON_COUNTER_MODE_MAX = 0x2,
+ PERFMON_COUNTER_MODE_DIRTY = 0x3,
+ PERFMON_COUNTER_MODE_SAMPLE = 0x4,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
+ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
+ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
+ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
+ PERFMON_COUNTER_MODE_RESERVED = 0xf,
+} PERFMON_COUNTER_MODE;
+typedef enum PERFMON_SPM_MODE {
+ PERFMON_SPM_MODE_OFF = 0x0,
+ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
+ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
+ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
+ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
+ PERFMON_SPM_MODE_RESERVED_5 = 0x5,
+ PERFMON_SPM_MODE_RESERVED_6 = 0x6,
+ PERFMON_SPM_MODE_RESERVED_7 = 0x7,
+ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
+ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
+ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
+} PERFMON_SPM_MODE;
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0x0,
+ ARRAY_TILED = 0x1,
+} SurfaceTiling;
+typedef enum SurfaceArray {
+ ARRAY_1D = 0x0,
+ ARRAY_2D = 0x1,
+ ARRAY_3D = 0x2,
+ ARRAY_3D_SLICE = 0x3,
+} SurfaceArray;
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0x0,
+ ARRAY_2D_COLOR = 0x1,
+ ARRAY_3D_SLICE_COLOR = 0x3,
+} ColorArray;
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0x0,
+ ARRAY_2D_DEPTH = 0x1,
+} DepthArray;
+typedef enum ENUM_NUM_SIMD_PER_CU {
+ NUM_SIMD_PER_CU = 0x4,
+} ENUM_NUM_SIMD_PER_CU;
+typedef enum MEM_PWR_FORCE_CTRL {
+ NO_FORCE_REQUEST = 0x0,
+ FORCE_LIGHT_SLEEP_REQUEST = 0x1,
+ FORCE_DEEP_SLEEP_REQUEST = 0x2,
+ FORCE_SHUT_DOWN_REQUEST = 0x3,
+} MEM_PWR_FORCE_CTRL;
+typedef enum MEM_PWR_FORCE_CTRL2 {
+ NO_FORCE_REQ = 0x0,
+ FORCE_LIGHT_SLEEP_REQ = 0x1,
+} MEM_PWR_FORCE_CTRL2;
+typedef enum MEM_PWR_DIS_CTRL {
+ ENABLE_MEM_PWR_CTRL = 0x0,
+ DISABLE_MEM_PWR_CTRL = 0x1,
+} MEM_PWR_DIS_CTRL;
+typedef enum MEM_PWR_SEL_CTRL {
+ DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
+ DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
+ DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
+} MEM_PWR_SEL_CTRL;
+typedef enum MEM_PWR_SEL_CTRL2 {
+ DYNAMIC_DEEP_SLEEP_EN = 0x0,
+ DYNAMIC_LIGHT_SLEEP_EN = 0x1,
+} MEM_PWR_SEL_CTRL2;
+
+#endif /* SMU_7_1_2_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h
new file mode 100644
index 000000000000..518fd02e9d35
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h
@@ -0,0 +1,5834 @@
+/*
+ * SMU_7_1_2 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef SMU_7_1_2_SH_MASK_H
+#define SMU_7_1_2_SH_MASK_H
+
+#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
+#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1
+#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0
+#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2
+#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1
+#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f
+#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1
+#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0
+#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2
+#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1
+#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f
+#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1
+#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0
+#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2
+#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1
+#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f
+#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
+#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa
+#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1
+#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0
+#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2
+#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1
+#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4
+#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2
+#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
+#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3
+#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10
+#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4
+#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20
+#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5
+#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40
+#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6
+#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80
+#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7
+#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100
+#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
+#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200
+#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9
+#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400
+#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa
+#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800
+#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb
+#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000
+#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc
+#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1
+#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2
+#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1
+#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4
+#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10
+#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4
+#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0
+#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000
+#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14
+#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000
+#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b
+#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000
+#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17
+#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000
+#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a
+#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000
+#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e
+#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff
+#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000
+#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fe00
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9
+#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000
+#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15
+#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17
+#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000
+#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f
+#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1
+#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2
+#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1
+#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc
+#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2
+#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30
+#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100
+#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8
+#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200
+#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00
+#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15
+#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000
+#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
+#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
+#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
+#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
+#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
+#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2
+#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1
+#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4
+#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2
+#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8
+#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3
+#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10
+#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4
+#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00
+#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa
+#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000
+#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc
+#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000
+#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c
+#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000
+#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d
+#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1
+#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0
+#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0
+#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4
+#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff
+#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0
+#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00
+#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8
+#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2
+#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1
+#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4
+#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2
+#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1
+#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0
+#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8
+#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3
+#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100
+#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8
+#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000
+#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe
+#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000
+#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf
+#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000
+#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10
+#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000
+#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11
+#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000
+#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12
+#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000
+#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13
+#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000
+#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14
+#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000
+#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15
+#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000
+#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16
+#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000
+#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18
+#define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1
+#define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0
+#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6
+#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1
+#define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00
+#define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa
+#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff
+#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0
+#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00
+#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8
+#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000
+#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10
+#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff
+#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0
+#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00
+#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8
+#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000
+#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10
+#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f
+#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
+#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0
+#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5
+#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00
+#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa
+#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000
+#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11
+#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000
+#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12
+#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000
+#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3
+#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0
+#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9
+#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000
+#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b
+#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff
+#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0
+#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff
+#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8_MASK 0x100
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8__SHIFT 0x8
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9_MASK 0x200
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9__SHIFT 0x9
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10_MASK 0x400
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10__SHIFT 0xa
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11_MASK 0x800
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11__SHIFT 0xb
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12_MASK 0x1000
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12__SHIFT 0xc
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13_MASK 0x2000
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13__SHIFT 0xd
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14_MASK 0x4000
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14__SHIFT 0xe
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15_MASK 0x8000
+#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15__SHIFT 0xf
+#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_0__SMC_RESP_MASK 0xffff
+#define SMC_RESP_0__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_1__SMC_RESP_MASK 0xffff
+#define SMC_RESP_1__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_2__SMC_RESP_MASK 0xffff
+#define SMC_RESP_2__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_3__SMC_RESP_MASK 0xffff
+#define SMC_RESP_3__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_4__SMC_RESP_MASK 0xffff
+#define SMC_RESP_4__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_5__SMC_RESP_MASK 0xffff
+#define SMC_RESP_5__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_6__SMC_RESP_MASK 0xffff
+#define SMC_RESP_6__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_7__SMC_RESP_MASK 0xffff
+#define SMC_RESP_7__SMC_RESP__SHIFT 0x0
+#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_8__SMC_RESP_MASK 0xffff
+#define SMC_RESP_8__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_9__SMC_RESP_MASK 0xffff
+#define SMC_RESP_9__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_10__SMC_RESP_MASK 0xffff
+#define SMC_RESP_10__SMC_RESP__SHIFT 0x0
+#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff
+#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0
+#define SMC_RESP_11__SMC_RESP_MASK 0xffff
+#define SMC_RESP_11__SMC_RESP__SHIFT 0x0
+#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff
+#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0
+#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1
+#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0
+#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2
+#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1
+#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000
+#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e
+#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1
+#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00
+#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8
+#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000
+#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18
+#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1
+#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0
+#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff
+#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0
+#define SMC_SYSCON_MISC_CNTL__dma_no_outstanding_MASK 0x2
+#define SMC_SYSCON_MISC_CNTL__dma_no_outstanding__SHIFT 0x1
+#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff
+#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0
+#define SMC_PC_C__smc_pc_c_MASK 0xffffffff
+#define SMC_PC_C__smc_pc_c__SHIFT 0x0
+#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff
+#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0
+#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1
+#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0
+#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf
+#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0
+#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0
+#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4
+#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff
+#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0
+#define GPIOPAD_A__GPIO_A_MASK 0x7fffffff
+#define GPIOPAD_A__GPIO_A__SHIFT 0x0
+#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff
+#define GPIOPAD_EN__GPIO_EN__SHIFT 0x0
+#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff
+#define GPIOPAD_Y__GPIO_Y__SHIFT 0x0
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000
+#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e
+#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff
+#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0
+#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000
+#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f
+#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff
+#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0
+#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000
+#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000
+#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c
+#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000
+#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f
+#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff
+#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0
+#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000
+#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f
+#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff
+#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0
+#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000
+#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f
+#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff
+#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0
+#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000
+#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40
+#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6
+#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff
+#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0
+#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff
+#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0
+#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff
+#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0
+#define CG_FPS_CNT__FPS_CNT_MASK 0xffffffff
+#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0
+#define SMU_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0
+#define SMU_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0
+#define SMU_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0
+#define SMU_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0
+#define SMU_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0
+#define SMU_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0
+#define SMU_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0
+#define SMU_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0
+#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1
+#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0
+#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2
+#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1
+#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4
+#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2
+#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8
+#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3
+#define RCU_UC_EVENTS__TP_Tester_MASK 0x40
+#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6
+#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80
+#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7
+#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100
+#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8
+#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200
+#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9
+#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400
+#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa
+#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800
+#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb
+#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000
+#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd
+#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000
+#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10
+#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000
+#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11
+#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000
+#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12
+#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000
+#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13
+#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000
+#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18
+#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2
+#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1
+#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8
+#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3
+#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10
+#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4
+#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20
+#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5
+#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100
+#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8
+#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000
+#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10
+#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000
+#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11
+#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000
+#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16
+#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000
+#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17
+#define RCU_VIRT_RESET_REQ__VF_MASK 0xffff
+#define RCU_VIRT_RESET_REQ__VF__SHIFT 0x0
+#define RCU_VIRT_RESET_REQ__PF_MASK 0x80000000
+#define RCU_VIRT_RESET_REQ__PF__SHIFT 0x1f
+#define CC_RCU_FUSES__GPU_DIS_MASK 0x2
+#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1
+#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4
+#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2
+#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10
+#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4
+#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20
+#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5
+#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40
+#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6
+#define CC_RCU_FUSES__ROM_DIS_MASK 0x80
+#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7
+#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100
+#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8
+#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200
+#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9
+#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400
+#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa
+#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x4000
+#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xe
+#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x8000
+#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0xf
+#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x10000
+#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x10
+#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x20000
+#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x11
+#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x40000
+#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x12
+#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x80000
+#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x13
+#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x200000
+#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x15
+#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x400000
+#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x16
+#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x800000
+#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x17
+#define CC_RCU_FUSES__WRP_FUSE_VALID_MASK 0x1000000
+#define CC_RCU_FUSES__WRP_FUSE_VALID__SHIFT 0x18
+#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x2000000
+#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0x19
+#define CC_RCU_FUSES__RCU_SPARE_MASK 0xfc000000
+#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x1a
+#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2
+#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1
+#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc
+#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2
+#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600
+#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9
+#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800
+#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000
+#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17
+#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000
+#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b
+#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000
+#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c
+#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000
+#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d
+#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff
+#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0
+#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00
+#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8
+#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000
+#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10
+#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000
+#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18
+#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe
+#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1
+#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e
+#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1
+#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e
+#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1
+#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40
+#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6
+#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80
+#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7
+#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100
+#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8
+#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200
+#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9
+#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400
+#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa
+#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800
+#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000
+#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd
+#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000
+#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000
+#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18
+#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000
+#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19
+#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000
+#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a
+#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0
+#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4
+#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000
+#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14
+#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000
+#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18
+#define CC_TST_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000
+#define CC_TST_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c
+#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2
+#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1
+#define CC_HARVEST_FUSES__VCE_DISABLE_MASK 0x6
+#define CC_HARVEST_FUSES__VCE_DISABLE__SHIFT 0x1
+#define CC_HARVEST_FUSES__UVD_DISABLE_MASK 0x10
+#define CC_HARVEST_FUSES__UVD_DISABLE__SHIFT 0x4
+#define CC_HARVEST_FUSES__ACP_DISABLE_MASK 0x40
+#define CC_HARVEST_FUSES__ACP_DISABLE__SHIFT 0x6
+#define CC_HARVEST_FUSES__DC_DISABLE_MASK 0x3f00
+#define CC_HARVEST_FUSES__DC_DISABLE__SHIFT 0x8
+#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff
+#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0
+#define SMU_STATUS__SMU_DONE_MASK 0x1
+#define SMU_STATUS__SMU_DONE__SHIFT 0x0
+#define SMU_STATUS__SMU_PASS_MASK 0x2
+#define SMU_STATUS__SMU_PASS__SHIFT 0x1
+#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1
+#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0
+#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6
+#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1
+#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8
+#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3
+#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10
+#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4
+#define SMU_FIRMWARE__SMU_counter_MASK 0xf00
+#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8
+#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000
+#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10
+#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000
+#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11
+#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff
+#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0
+#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000
+#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f
+#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff
+#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0
+#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1
+#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
+#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe
+#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
+#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000
+#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18
+#define TDC_STATUS__VDD_Boost_MASK 0xff
+#define TDC_STATUS__VDD_Boost__SHIFT 0x0
+#define TDC_STATUS__VDD_Throttle_MASK 0xff00
+#define TDC_STATUS__VDD_Throttle__SHIFT 0x8
+#define TDC_STATUS__VDDC_Boost_MASK 0xff0000
+#define TDC_STATUS__VDDC_Boost__SHIFT 0x10
+#define TDC_STATUS__VDDC_Throttle_MASK 0xff000000
+#define TDC_STATUS__VDDC_Throttle__SHIFT 0x18
+#define TDC_MV_AVERAGE__IDD_MASK 0xffff
+#define TDC_MV_AVERAGE__IDD__SHIFT 0x0
+#define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000
+#define TDC_MV_AVERAGE__IDDC__SHIFT 0x10
+#define TDC_VRM_LIMIT__IDD_MASK 0xffff
+#define TDC_VRM_LIMIT__IDD__SHIFT 0x0
+#define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000
+#define TDC_VRM_LIMIT__IDDC__SHIFT 0x10
+#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1
+#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0
+#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2
+#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1
+#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4
+#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2
+#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8
+#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3
+#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10
+#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4
+#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x20
+#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x5
+#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x40
+#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x6
+#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80
+#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7
+#define FEATURE_STATUS__BAPM_ON_MASK 0x100
+#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8
+#define FEATURE_STATUS__LPMX_ON_MASK 0x200
+#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9
+#define FEATURE_STATUS__NBDPM_ON_MASK 0x400
+#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa
+#define FEATURE_STATUS__LHTC_ON_MASK 0x800
+#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb
+#define FEATURE_STATUS__VPC_ON_MASK 0x1000
+#define FEATURE_STATUS__VPC_ON__SHIFT 0xc
+#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000
+#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd
+#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000
+#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe
+#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000
+#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf
+#define FEATURE_STATUS__AVS_ON_MASK 0x10000
+#define FEATURE_STATUS__AVS_ON__SHIFT 0x10
+#define FEATURE_STATUS__SPMI_ON_MASK 0x20000
+#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11
+#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000
+#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12
+#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000
+#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13
+#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000
+#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14
+#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000
+#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15
+#define FEATURE_STATUS__RESERVED_MASK 0xffc00000
+#define FEATURE_STATUS__RESERVED__SHIFT 0x16
+#define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff
+#define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0
+#define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff
+#define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0
+#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff
+#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0
+#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff
+#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0
+#define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff
+#define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0
+#define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff
+#define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0
+#define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff
+#define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0
+#define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff
+#define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0
+#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff
+#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0
+#define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff
+#define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0
+#define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff
+#define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0
+#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff
+#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0
+#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff
+#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0
+#define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff
+#define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0
+#define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff
+#define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0
+#define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff
+#define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0
+#define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff
+#define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0
+#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff
+#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0
+#define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff
+#define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0
+#define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff
+#define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0
+#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff
+#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0
+#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff
+#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0
+#define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff
+#define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0
+#define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff
+#define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0
+#define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff
+#define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0
+#define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff
+#define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0
+#define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff
+#define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0
+#define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff
+#define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0
+#define DPM_TABLE_28__SystemFlags_MASK 0xffffffff
+#define DPM_TABLE_28__SystemFlags__SHIFT 0x0
+#define DPM_TABLE_29__VRConfig_MASK 0xffffffff
+#define DPM_TABLE_29__VRConfig__SHIFT 0x0
+#define DPM_TABLE_30__SmioMask1_MASK 0xffffffff
+#define DPM_TABLE_30__SmioMask1__SHIFT 0x0
+#define DPM_TABLE_31__SmioMask2_MASK 0xffffffff
+#define DPM_TABLE_31__SmioMask2__SHIFT 0x0
+#define DPM_TABLE_32__SmioTable1_Pattern_0_padding_MASK 0xff
+#define DPM_TABLE_32__SmioTable1_Pattern_0_padding__SHIFT 0x0
+#define DPM_TABLE_32__SmioTable1_Pattern_0_Smio_MASK 0xff00
+#define DPM_TABLE_32__SmioTable1_Pattern_0_Smio__SHIFT 0x8
+#define DPM_TABLE_32__SmioTable1_Pattern_0_Voltage_MASK 0xffff0000
+#define DPM_TABLE_32__SmioTable1_Pattern_0_Voltage__SHIFT 0x10
+#define DPM_TABLE_33__SmioTable1_Pattern_1_padding_MASK 0xff
+#define DPM_TABLE_33__SmioTable1_Pattern_1_padding__SHIFT 0x0
+#define DPM_TABLE_33__SmioTable1_Pattern_1_Smio_MASK 0xff00
+#define DPM_TABLE_33__SmioTable1_Pattern_1_Smio__SHIFT 0x8
+#define DPM_TABLE_33__SmioTable1_Pattern_1_Voltage_MASK 0xffff0000
+#define DPM_TABLE_33__SmioTable1_Pattern_1_Voltage__SHIFT 0x10
+#define DPM_TABLE_34__SmioTable1_Pattern_2_padding_MASK 0xff
+#define DPM_TABLE_34__SmioTable1_Pattern_2_padding__SHIFT 0x0
+#define DPM_TABLE_34__SmioTable1_Pattern_2_Smio_MASK 0xff00
+#define DPM_TABLE_34__SmioTable1_Pattern_2_Smio__SHIFT 0x8
+#define DPM_TABLE_34__SmioTable1_Pattern_2_Voltage_MASK 0xffff0000
+#define DPM_TABLE_34__SmioTable1_Pattern_2_Voltage__SHIFT 0x10
+#define DPM_TABLE_35__SmioTable1_Pattern_3_padding_MASK 0xff
+#define DPM_TABLE_35__SmioTable1_Pattern_3_padding__SHIFT 0x0
+#define DPM_TABLE_35__SmioTable1_Pattern_3_Smio_MASK 0xff00
+#define DPM_TABLE_35__SmioTable1_Pattern_3_Smio__SHIFT 0x8
+#define DPM_TABLE_35__SmioTable1_Pattern_3_Voltage_MASK 0xffff0000
+#define DPM_TABLE_35__SmioTable1_Pattern_3_Voltage__SHIFT 0x10
+#define DPM_TABLE_36__SmioTable2_Pattern_0_padding_MASK 0xff
+#define DPM_TABLE_36__SmioTable2_Pattern_0_padding__SHIFT 0x0
+#define DPM_TABLE_36__SmioTable2_Pattern_0_Smio_MASK 0xff00
+#define DPM_TABLE_36__SmioTable2_Pattern_0_Smio__SHIFT 0x8
+#define DPM_TABLE_36__SmioTable2_Pattern_0_Voltage_MASK 0xffff0000
+#define DPM_TABLE_36__SmioTable2_Pattern_0_Voltage__SHIFT 0x10
+#define DPM_TABLE_37__SmioTable2_Pattern_1_padding_MASK 0xff
+#define DPM_TABLE_37__SmioTable2_Pattern_1_padding__SHIFT 0x0
+#define DPM_TABLE_37__SmioTable2_Pattern_1_Smio_MASK 0xff00
+#define DPM_TABLE_37__SmioTable2_Pattern_1_Smio__SHIFT 0x8
+#define DPM_TABLE_37__SmioTable2_Pattern_1_Voltage_MASK 0xffff0000
+#define DPM_TABLE_37__SmioTable2_Pattern_1_Voltage__SHIFT 0x10
+#define DPM_TABLE_38__SmioTable2_Pattern_2_padding_MASK 0xff
+#define DPM_TABLE_38__SmioTable2_Pattern_2_padding__SHIFT 0x0
+#define DPM_TABLE_38__SmioTable2_Pattern_2_Smio_MASK 0xff00
+#define DPM_TABLE_38__SmioTable2_Pattern_2_Smio__SHIFT 0x8
+#define DPM_TABLE_38__SmioTable2_Pattern_2_Voltage_MASK 0xffff0000
+#define DPM_TABLE_38__SmioTable2_Pattern_2_Voltage__SHIFT 0x10
+#define DPM_TABLE_39__SmioTable2_Pattern_3_padding_MASK 0xff
+#define DPM_TABLE_39__SmioTable2_Pattern_3_padding__SHIFT 0x0
+#define DPM_TABLE_39__SmioTable2_Pattern_3_Smio_MASK 0xff00
+#define DPM_TABLE_39__SmioTable2_Pattern_3_Smio__SHIFT 0x8
+#define DPM_TABLE_39__SmioTable2_Pattern_3_Voltage_MASK 0xffff0000
+#define DPM_TABLE_39__SmioTable2_Pattern_3_Voltage__SHIFT 0x10
+#define DPM_TABLE_40__VddcLevelCount_MASK 0xffffffff
+#define DPM_TABLE_40__VddcLevelCount__SHIFT 0x0
+#define DPM_TABLE_41__VddciLevelCount_MASK 0xffffffff
+#define DPM_TABLE_41__VddciLevelCount__SHIFT 0x0
+#define DPM_TABLE_42__VddGfxLevelCount_MASK 0xffffffff
+#define DPM_TABLE_42__VddGfxLevelCount__SHIFT 0x0
+#define DPM_TABLE_43__MvddLevelCount_MASK 0xffffffff
+#define DPM_TABLE_43__MvddLevelCount__SHIFT 0x0
+#define DPM_TABLE_44__VddcTable_1_MASK 0xffff
+#define DPM_TABLE_44__VddcTable_1__SHIFT 0x0
+#define DPM_TABLE_44__VddcTable_0_MASK 0xffff0000
+#define DPM_TABLE_44__VddcTable_0__SHIFT 0x10
+#define DPM_TABLE_45__VddcTable_3_MASK 0xffff
+#define DPM_TABLE_45__VddcTable_3__SHIFT 0x0
+#define DPM_TABLE_45__VddcTable_2_MASK 0xffff0000
+#define DPM_TABLE_45__VddcTable_2__SHIFT 0x10
+#define DPM_TABLE_46__VddcTable_5_MASK 0xffff
+#define DPM_TABLE_46__VddcTable_5__SHIFT 0x0
+#define DPM_TABLE_46__VddcTable_4_MASK 0xffff0000
+#define DPM_TABLE_46__VddcTable_4__SHIFT 0x10
+#define DPM_TABLE_47__VddcTable_7_MASK 0xffff
+#define DPM_TABLE_47__VddcTable_7__SHIFT 0x0
+#define DPM_TABLE_47__VddcTable_6_MASK 0xffff0000
+#define DPM_TABLE_47__VddcTable_6__SHIFT 0x10
+#define DPM_TABLE_48__VddcTable_9_MASK 0xffff
+#define DPM_TABLE_48__VddcTable_9__SHIFT 0x0
+#define DPM_TABLE_48__VddcTable_8_MASK 0xffff0000
+#define DPM_TABLE_48__VddcTable_8__SHIFT 0x10
+#define DPM_TABLE_49__VddcTable_11_MASK 0xffff
+#define DPM_TABLE_49__VddcTable_11__SHIFT 0x0
+#define DPM_TABLE_49__VddcTable_10_MASK 0xffff0000
+#define DPM_TABLE_49__VddcTable_10__SHIFT 0x10
+#define DPM_TABLE_50__VddcTable_13_MASK 0xffff
+#define DPM_TABLE_50__VddcTable_13__SHIFT 0x0
+#define DPM_TABLE_50__VddcTable_12_MASK 0xffff0000
+#define DPM_TABLE_50__VddcTable_12__SHIFT 0x10
+#define DPM_TABLE_51__VddcTable_15_MASK 0xffff
+#define DPM_TABLE_51__VddcTable_15__SHIFT 0x0
+#define DPM_TABLE_51__VddcTable_14_MASK 0xffff0000
+#define DPM_TABLE_51__VddcTable_14__SHIFT 0x10
+#define DPM_TABLE_52__VddGfxTable_1_MASK 0xffff
+#define DPM_TABLE_52__VddGfxTable_1__SHIFT 0x0
+#define DPM_TABLE_52__VddGfxTable_0_MASK 0xffff0000
+#define DPM_TABLE_52__VddGfxTable_0__SHIFT 0x10
+#define DPM_TABLE_53__VddGfxTable_3_MASK 0xffff
+#define DPM_TABLE_53__VddGfxTable_3__SHIFT 0x0
+#define DPM_TABLE_53__VddGfxTable_2_MASK 0xffff0000
+#define DPM_TABLE_53__VddGfxTable_2__SHIFT 0x10
+#define DPM_TABLE_54__VddGfxTable_5_MASK 0xffff
+#define DPM_TABLE_54__VddGfxTable_5__SHIFT 0x0
+#define DPM_TABLE_54__VddGfxTable_4_MASK 0xffff0000
+#define DPM_TABLE_54__VddGfxTable_4__SHIFT 0x10
+#define DPM_TABLE_55__VddGfxTable_7_MASK 0xffff
+#define DPM_TABLE_55__VddGfxTable_7__SHIFT 0x0
+#define DPM_TABLE_55__VddGfxTable_6_MASK 0xffff0000
+#define DPM_TABLE_55__VddGfxTable_6__SHIFT 0x10
+#define DPM_TABLE_56__VddGfxTable_9_MASK 0xffff
+#define DPM_TABLE_56__VddGfxTable_9__SHIFT 0x0
+#define DPM_TABLE_56__VddGfxTable_8_MASK 0xffff0000
+#define DPM_TABLE_56__VddGfxTable_8__SHIFT 0x10
+#define DPM_TABLE_57__VddGfxTable_11_MASK 0xffff
+#define DPM_TABLE_57__VddGfxTable_11__SHIFT 0x0
+#define DPM_TABLE_57__VddGfxTable_10_MASK 0xffff0000
+#define DPM_TABLE_57__VddGfxTable_10__SHIFT 0x10
+#define DPM_TABLE_58__VddGfxTable_13_MASK 0xffff
+#define DPM_TABLE_58__VddGfxTable_13__SHIFT 0x0
+#define DPM_TABLE_58__VddGfxTable_12_MASK 0xffff0000
+#define DPM_TABLE_58__VddGfxTable_12__SHIFT 0x10
+#define DPM_TABLE_59__VddGfxTable_15_MASK 0xffff
+#define DPM_TABLE_59__VddGfxTable_15__SHIFT 0x0
+#define DPM_TABLE_59__VddGfxTable_14_MASK 0xffff0000
+#define DPM_TABLE_59__VddGfxTable_14__SHIFT 0x10
+#define DPM_TABLE_60__VddciTable_1_MASK 0xffff
+#define DPM_TABLE_60__VddciTable_1__SHIFT 0x0
+#define DPM_TABLE_60__VddciTable_0_MASK 0xffff0000
+#define DPM_TABLE_60__VddciTable_0__SHIFT 0x10
+#define DPM_TABLE_61__VddciTable_3_MASK 0xffff
+#define DPM_TABLE_61__VddciTable_3__SHIFT 0x0
+#define DPM_TABLE_61__VddciTable_2_MASK 0xffff0000
+#define DPM_TABLE_61__VddciTable_2__SHIFT 0x10
+#define DPM_TABLE_62__VddciTable_5_MASK 0xffff
+#define DPM_TABLE_62__VddciTable_5__SHIFT 0x0
+#define DPM_TABLE_62__VddciTable_4_MASK 0xffff0000
+#define DPM_TABLE_62__VddciTable_4__SHIFT 0x10
+#define DPM_TABLE_63__VddciTable_7_MASK 0xffff
+#define DPM_TABLE_63__VddciTable_7__SHIFT 0x0
+#define DPM_TABLE_63__VddciTable_6_MASK 0xffff0000
+#define DPM_TABLE_63__VddciTable_6__SHIFT 0x10
+#define DPM_TABLE_64__BapmVddGfxVidHiSidd_3_MASK 0xff
+#define DPM_TABLE_64__BapmVddGfxVidHiSidd_3__SHIFT 0x0
+#define DPM_TABLE_64__BapmVddGfxVidHiSidd_2_MASK 0xff00
+#define DPM_TABLE_64__BapmVddGfxVidHiSidd_2__SHIFT 0x8
+#define DPM_TABLE_64__BapmVddGfxVidHiSidd_1_MASK 0xff0000
+#define DPM_TABLE_64__BapmVddGfxVidHiSidd_1__SHIFT 0x10
+#define DPM_TABLE_64__BapmVddGfxVidHiSidd_0_MASK 0xff000000
+#define DPM_TABLE_64__BapmVddGfxVidHiSidd_0__SHIFT 0x18
+#define DPM_TABLE_65__BapmVddGfxVidHiSidd_7_MASK 0xff
+#define DPM_TABLE_65__BapmVddGfxVidHiSidd_7__SHIFT 0x0
+#define DPM_TABLE_65__BapmVddGfxVidHiSidd_6_MASK 0xff00
+#define DPM_TABLE_65__BapmVddGfxVidHiSidd_6__SHIFT 0x8
+#define DPM_TABLE_65__BapmVddGfxVidHiSidd_5_MASK 0xff0000
+#define DPM_TABLE_65__BapmVddGfxVidHiSidd_5__SHIFT 0x10
+#define DPM_TABLE_65__BapmVddGfxVidHiSidd_4_MASK 0xff000000
+#define DPM_TABLE_65__BapmVddGfxVidHiSidd_4__SHIFT 0x18
+#define DPM_TABLE_66__BapmVddGfxVidHiSidd_11_MASK 0xff
+#define DPM_TABLE_66__BapmVddGfxVidHiSidd_11__SHIFT 0x0
+#define DPM_TABLE_66__BapmVddGfxVidHiSidd_10_MASK 0xff00
+#define DPM_TABLE_66__BapmVddGfxVidHiSidd_10__SHIFT 0x8
+#define DPM_TABLE_66__BapmVddGfxVidHiSidd_9_MASK 0xff0000
+#define DPM_TABLE_66__BapmVddGfxVidHiSidd_9__SHIFT 0x10
+#define DPM_TABLE_66__BapmVddGfxVidHiSidd_8_MASK 0xff000000
+#define DPM_TABLE_66__BapmVddGfxVidHiSidd_8__SHIFT 0x18
+#define DPM_TABLE_67__BapmVddGfxVidHiSidd_15_MASK 0xff
+#define DPM_TABLE_67__BapmVddGfxVidHiSidd_15__SHIFT 0x0
+#define DPM_TABLE_67__BapmVddGfxVidHiSidd_14_MASK 0xff00
+#define DPM_TABLE_67__BapmVddGfxVidHiSidd_14__SHIFT 0x8
+#define DPM_TABLE_67__BapmVddGfxVidHiSidd_13_MASK 0xff0000
+#define DPM_TABLE_67__BapmVddGfxVidHiSidd_13__SHIFT 0x10
+#define DPM_TABLE_67__BapmVddGfxVidHiSidd_12_MASK 0xff000000
+#define DPM_TABLE_67__BapmVddGfxVidHiSidd_12__SHIFT 0x18
+#define DPM_TABLE_68__BapmVddGfxVidLoSidd_3_MASK 0xff
+#define DPM_TABLE_68__BapmVddGfxVidLoSidd_3__SHIFT 0x0
+#define DPM_TABLE_68__BapmVddGfxVidLoSidd_2_MASK 0xff00
+#define DPM_TABLE_68__BapmVddGfxVidLoSidd_2__SHIFT 0x8
+#define DPM_TABLE_68__BapmVddGfxVidLoSidd_1_MASK 0xff0000
+#define DPM_TABLE_68__BapmVddGfxVidLoSidd_1__SHIFT 0x10
+#define DPM_TABLE_68__BapmVddGfxVidLoSidd_0_MASK 0xff000000
+#define DPM_TABLE_68__BapmVddGfxVidLoSidd_0__SHIFT 0x18
+#define DPM_TABLE_69__BapmVddGfxVidLoSidd_7_MASK 0xff
+#define DPM_TABLE_69__BapmVddGfxVidLoSidd_7__SHIFT 0x0
+#define DPM_TABLE_69__BapmVddGfxVidLoSidd_6_MASK 0xff00
+#define DPM_TABLE_69__BapmVddGfxVidLoSidd_6__SHIFT 0x8
+#define DPM_TABLE_69__BapmVddGfxVidLoSidd_5_MASK 0xff0000
+#define DPM_TABLE_69__BapmVddGfxVidLoSidd_5__SHIFT 0x10
+#define DPM_TABLE_69__BapmVddGfxVidLoSidd_4_MASK 0xff000000
+#define DPM_TABLE_69__BapmVddGfxVidLoSidd_4__SHIFT 0x18
+#define DPM_TABLE_70__BapmVddGfxVidLoSidd_11_MASK 0xff
+#define DPM_TABLE_70__BapmVddGfxVidLoSidd_11__SHIFT 0x0
+#define DPM_TABLE_70__BapmVddGfxVidLoSidd_10_MASK 0xff00
+#define DPM_TABLE_70__BapmVddGfxVidLoSidd_10__SHIFT 0x8
+#define DPM_TABLE_70__BapmVddGfxVidLoSidd_9_MASK 0xff0000
+#define DPM_TABLE_70__BapmVddGfxVidLoSidd_9__SHIFT 0x10
+#define DPM_TABLE_70__BapmVddGfxVidLoSidd_8_MASK 0xff000000
+#define DPM_TABLE_70__BapmVddGfxVidLoSidd_8__SHIFT 0x18
+#define DPM_TABLE_71__BapmVddGfxVidLoSidd_15_MASK 0xff
+#define DPM_TABLE_71__BapmVddGfxVidLoSidd_15__SHIFT 0x0
+#define DPM_TABLE_71__BapmVddGfxVidLoSidd_14_MASK 0xff00
+#define DPM_TABLE_71__BapmVddGfxVidLoSidd_14__SHIFT 0x8
+#define DPM_TABLE_71__BapmVddGfxVidLoSidd_13_MASK 0xff0000
+#define DPM_TABLE_71__BapmVddGfxVidLoSidd_13__SHIFT 0x10
+#define DPM_TABLE_71__BapmVddGfxVidLoSidd_12_MASK 0xff000000
+#define DPM_TABLE_71__BapmVddGfxVidLoSidd_12__SHIFT 0x18
+#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_3_MASK 0xff
+#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_3__SHIFT 0x0
+#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_2_MASK 0xff00
+#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_2__SHIFT 0x8
+#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_1_MASK 0xff0000
+#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_1__SHIFT 0x10
+#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_0_MASK 0xff000000
+#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_0__SHIFT 0x18
+#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_7_MASK 0xff
+#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_7__SHIFT 0x0
+#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_6_MASK 0xff00
+#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_6__SHIFT 0x8
+#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_5_MASK 0xff0000
+#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_5__SHIFT 0x10
+#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_4_MASK 0xff000000
+#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_4__SHIFT 0x18
+#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_11_MASK 0xff
+#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_11__SHIFT 0x0
+#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_10_MASK 0xff00
+#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_10__SHIFT 0x8
+#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_9_MASK 0xff0000
+#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_9__SHIFT 0x10
+#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_8_MASK 0xff000000
+#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_8__SHIFT 0x18
+#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_15_MASK 0xff
+#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_15__SHIFT 0x0
+#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_14_MASK 0xff00
+#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_14__SHIFT 0x8
+#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_13_MASK 0xff0000
+#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_13__SHIFT 0x10
+#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_12_MASK 0xff000000
+#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_12__SHIFT 0x18
+#define DPM_TABLE_76__BapmVddcVidHiSidd_3_MASK 0xff
+#define DPM_TABLE_76__BapmVddcVidHiSidd_3__SHIFT 0x0
+#define DPM_TABLE_76__BapmVddcVidHiSidd_2_MASK 0xff00
+#define DPM_TABLE_76__BapmVddcVidHiSidd_2__SHIFT 0x8
+#define DPM_TABLE_76__BapmVddcVidHiSidd_1_MASK 0xff0000
+#define DPM_TABLE_76__BapmVddcVidHiSidd_1__SHIFT 0x10
+#define DPM_TABLE_76__BapmVddcVidHiSidd_0_MASK 0xff000000
+#define DPM_TABLE_76__BapmVddcVidHiSidd_0__SHIFT 0x18
+#define DPM_TABLE_77__BapmVddcVidHiSidd_7_MASK 0xff
+#define DPM_TABLE_77__BapmVddcVidHiSidd_7__SHIFT 0x0
+#define DPM_TABLE_77__BapmVddcVidHiSidd_6_MASK 0xff00
+#define DPM_TABLE_77__BapmVddcVidHiSidd_6__SHIFT 0x8
+#define DPM_TABLE_77__BapmVddcVidHiSidd_5_MASK 0xff0000
+#define DPM_TABLE_77__BapmVddcVidHiSidd_5__SHIFT 0x10
+#define DPM_TABLE_77__BapmVddcVidHiSidd_4_MASK 0xff000000
+#define DPM_TABLE_77__BapmVddcVidHiSidd_4__SHIFT 0x18
+#define DPM_TABLE_78__BapmVddcVidHiSidd_11_MASK 0xff
+#define DPM_TABLE_78__BapmVddcVidHiSidd_11__SHIFT 0x0
+#define DPM_TABLE_78__BapmVddcVidHiSidd_10_MASK 0xff00
+#define DPM_TABLE_78__BapmVddcVidHiSidd_10__SHIFT 0x8
+#define DPM_TABLE_78__BapmVddcVidHiSidd_9_MASK 0xff0000
+#define DPM_TABLE_78__BapmVddcVidHiSidd_9__SHIFT 0x10
+#define DPM_TABLE_78__BapmVddcVidHiSidd_8_MASK 0xff000000
+#define DPM_TABLE_78__BapmVddcVidHiSidd_8__SHIFT 0x18
+#define DPM_TABLE_79__BapmVddcVidHiSidd_15_MASK 0xff
+#define DPM_TABLE_79__BapmVddcVidHiSidd_15__SHIFT 0x0
+#define DPM_TABLE_79__BapmVddcVidHiSidd_14_MASK 0xff00
+#define DPM_TABLE_79__BapmVddcVidHiSidd_14__SHIFT 0x8
+#define DPM_TABLE_79__BapmVddcVidHiSidd_13_MASK 0xff0000
+#define DPM_TABLE_79__BapmVddcVidHiSidd_13__SHIFT 0x10
+#define DPM_TABLE_79__BapmVddcVidHiSidd_12_MASK 0xff000000
+#define DPM_TABLE_79__BapmVddcVidHiSidd_12__SHIFT 0x18
+#define DPM_TABLE_80__BapmVddcVidLoSidd_3_MASK 0xff
+#define DPM_TABLE_80__BapmVddcVidLoSidd_3__SHIFT 0x0
+#define DPM_TABLE_80__BapmVddcVidLoSidd_2_MASK 0xff00
+#define DPM_TABLE_80__BapmVddcVidLoSidd_2__SHIFT 0x8
+#define DPM_TABLE_80__BapmVddcVidLoSidd_1_MASK 0xff0000
+#define DPM_TABLE_80__BapmVddcVidLoSidd_1__SHIFT 0x10
+#define DPM_TABLE_80__BapmVddcVidLoSidd_0_MASK 0xff000000
+#define DPM_TABLE_80__BapmVddcVidLoSidd_0__SHIFT 0x18
+#define DPM_TABLE_81__BapmVddcVidLoSidd_7_MASK 0xff
+#define DPM_TABLE_81__BapmVddcVidLoSidd_7__SHIFT 0x0
+#define DPM_TABLE_81__BapmVddcVidLoSidd_6_MASK 0xff00
+#define DPM_TABLE_81__BapmVddcVidLoSidd_6__SHIFT 0x8
+#define DPM_TABLE_81__BapmVddcVidLoSidd_5_MASK 0xff0000
+#define DPM_TABLE_81__BapmVddcVidLoSidd_5__SHIFT 0x10
+#define DPM_TABLE_81__BapmVddcVidLoSidd_4_MASK 0xff000000
+#define DPM_TABLE_81__BapmVddcVidLoSidd_4__SHIFT 0x18
+#define DPM_TABLE_82__BapmVddcVidLoSidd_11_MASK 0xff
+#define DPM_TABLE_82__BapmVddcVidLoSidd_11__SHIFT 0x0
+#define DPM_TABLE_82__BapmVddcVidLoSidd_10_MASK 0xff00
+#define DPM_TABLE_82__BapmVddcVidLoSidd_10__SHIFT 0x8
+#define DPM_TABLE_82__BapmVddcVidLoSidd_9_MASK 0xff0000
+#define DPM_TABLE_82__BapmVddcVidLoSidd_9__SHIFT 0x10
+#define DPM_TABLE_82__BapmVddcVidLoSidd_8_MASK 0xff000000
+#define DPM_TABLE_82__BapmVddcVidLoSidd_8__SHIFT 0x18
+#define DPM_TABLE_83__BapmVddcVidLoSidd_15_MASK 0xff
+#define DPM_TABLE_83__BapmVddcVidLoSidd_15__SHIFT 0x0
+#define DPM_TABLE_83__BapmVddcVidLoSidd_14_MASK 0xff00
+#define DPM_TABLE_83__BapmVddcVidLoSidd_14__SHIFT 0x8
+#define DPM_TABLE_83__BapmVddcVidLoSidd_13_MASK 0xff0000
+#define DPM_TABLE_83__BapmVddcVidLoSidd_13__SHIFT 0x10
+#define DPM_TABLE_83__BapmVddcVidLoSidd_12_MASK 0xff000000
+#define DPM_TABLE_83__BapmVddcVidLoSidd_12__SHIFT 0x18
+#define DPM_TABLE_84__BapmVddcVidHiSidd2_3_MASK 0xff
+#define DPM_TABLE_84__BapmVddcVidHiSidd2_3__SHIFT 0x0
+#define DPM_TABLE_84__BapmVddcVidHiSidd2_2_MASK 0xff00
+#define DPM_TABLE_84__BapmVddcVidHiSidd2_2__SHIFT 0x8
+#define DPM_TABLE_84__BapmVddcVidHiSidd2_1_MASK 0xff0000
+#define DPM_TABLE_84__BapmVddcVidHiSidd2_1__SHIFT 0x10
+#define DPM_TABLE_84__BapmVddcVidHiSidd2_0_MASK 0xff000000
+#define DPM_TABLE_84__BapmVddcVidHiSidd2_0__SHIFT 0x18
+#define DPM_TABLE_85__BapmVddcVidHiSidd2_7_MASK 0xff
+#define DPM_TABLE_85__BapmVddcVidHiSidd2_7__SHIFT 0x0
+#define DPM_TABLE_85__BapmVddcVidHiSidd2_6_MASK 0xff00
+#define DPM_TABLE_85__BapmVddcVidHiSidd2_6__SHIFT 0x8
+#define DPM_TABLE_85__BapmVddcVidHiSidd2_5_MASK 0xff0000
+#define DPM_TABLE_85__BapmVddcVidHiSidd2_5__SHIFT 0x10
+#define DPM_TABLE_85__BapmVddcVidHiSidd2_4_MASK 0xff000000
+#define DPM_TABLE_85__BapmVddcVidHiSidd2_4__SHIFT 0x18
+#define DPM_TABLE_86__BapmVddcVidHiSidd2_11_MASK 0xff
+#define DPM_TABLE_86__BapmVddcVidHiSidd2_11__SHIFT 0x0
+#define DPM_TABLE_86__BapmVddcVidHiSidd2_10_MASK 0xff00
+#define DPM_TABLE_86__BapmVddcVidHiSidd2_10__SHIFT 0x8
+#define DPM_TABLE_86__BapmVddcVidHiSidd2_9_MASK 0xff0000
+#define DPM_TABLE_86__BapmVddcVidHiSidd2_9__SHIFT 0x10
+#define DPM_TABLE_86__BapmVddcVidHiSidd2_8_MASK 0xff000000
+#define DPM_TABLE_86__BapmVddcVidHiSidd2_8__SHIFT 0x18
+#define DPM_TABLE_87__BapmVddcVidHiSidd2_15_MASK 0xff
+#define DPM_TABLE_87__BapmVddcVidHiSidd2_15__SHIFT 0x0
+#define DPM_TABLE_87__BapmVddcVidHiSidd2_14_MASK 0xff00
+#define DPM_TABLE_87__BapmVddcVidHiSidd2_14__SHIFT 0x8
+#define DPM_TABLE_87__BapmVddcVidHiSidd2_13_MASK 0xff0000
+#define DPM_TABLE_87__BapmVddcVidHiSidd2_13__SHIFT 0x10
+#define DPM_TABLE_87__BapmVddcVidHiSidd2_12_MASK 0xff000000
+#define DPM_TABLE_87__BapmVddcVidHiSidd2_12__SHIFT 0x18
+#define DPM_TABLE_88__MasterDeepSleepControl_MASK 0xff
+#define DPM_TABLE_88__MasterDeepSleepControl__SHIFT 0x0
+#define DPM_TABLE_88__LinkLevelCount_MASK 0xff00
+#define DPM_TABLE_88__LinkLevelCount__SHIFT 0x8
+#define DPM_TABLE_88__MemoryDpmLevelCount_MASK 0xff0000
+#define DPM_TABLE_88__MemoryDpmLevelCount__SHIFT 0x10
+#define DPM_TABLE_88__GraphicsDpmLevelCount_MASK 0xff000000
+#define DPM_TABLE_88__GraphicsDpmLevelCount__SHIFT 0x18
+#define DPM_TABLE_89__SamuLevelCount_MASK 0xff
+#define DPM_TABLE_89__SamuLevelCount__SHIFT 0x0
+#define DPM_TABLE_89__AcpLevelCount_MASK 0xff00
+#define DPM_TABLE_89__AcpLevelCount__SHIFT 0x8
+#define DPM_TABLE_89__VceLevelCount_MASK 0xff0000
+#define DPM_TABLE_89__VceLevelCount__SHIFT 0x10
+#define DPM_TABLE_89__UvdLevelCount_MASK 0xff000000
+#define DPM_TABLE_89__UvdLevelCount__SHIFT 0x18
+#define DPM_TABLE_90__Reserved_0_MASK 0xffffffff
+#define DPM_TABLE_90__Reserved_0__SHIFT 0x0
+#define DPM_TABLE_91__Reserved_1_MASK 0xffffffff
+#define DPM_TABLE_91__Reserved_1__SHIFT 0x0
+#define DPM_TABLE_92__Reserved_2_MASK 0xffffffff
+#define DPM_TABLE_92__Reserved_2__SHIFT 0x0
+#define DPM_TABLE_93__Reserved_3_MASK 0xffffffff
+#define DPM_TABLE_93__Reserved_3__SHIFT 0x0
+#define DPM_TABLE_94__Reserved_4_MASK 0xffffffff
+#define DPM_TABLE_94__Reserved_4__SHIFT 0x0
+#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_96__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_96__GraphicsLevel_0_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_97__GraphicsLevel_0_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_97__GraphicsLevel_0_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_97__GraphicsLevel_0_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_97__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_97__GraphicsLevel_0_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_97__GraphicsLevel_0_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_98__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_98__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_99__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_99__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_100__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_100__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_101__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_101__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_102__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_102__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_103__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_103__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_104__GraphicsLevel_0_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_104__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_104__GraphicsLevel_0_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_104__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_104__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_104__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_104__GraphicsLevel_0_SclkDid_MASK 0xff000000
+#define DPM_TABLE_104__GraphicsLevel_0_SclkDid__SHIFT 0x18
+#define DPM_TABLE_105__GraphicsLevel_0_PowerThrottle_MASK 0xff
+#define DPM_TABLE_105__GraphicsLevel_0_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_105__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_105__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_105__GraphicsLevel_0_DownHyst_MASK 0xff0000
+#define DPM_TABLE_105__GraphicsLevel_0_DownHyst__SHIFT 0x10
+#define DPM_TABLE_105__GraphicsLevel_0_UpHyst_MASK 0xff000000
+#define DPM_TABLE_105__GraphicsLevel_0_UpHyst__SHIFT 0x18
+#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_107__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_107__GraphicsLevel_1_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_108__GraphicsLevel_1_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_108__GraphicsLevel_1_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_108__GraphicsLevel_1_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_108__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_108__GraphicsLevel_1_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_108__GraphicsLevel_1_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_109__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_109__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_110__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_110__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_111__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_111__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_112__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_112__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_113__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_113__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_114__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_114__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_115__GraphicsLevel_1_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_115__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_115__GraphicsLevel_1_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_115__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_115__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_115__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_115__GraphicsLevel_1_SclkDid_MASK 0xff000000
+#define DPM_TABLE_115__GraphicsLevel_1_SclkDid__SHIFT 0x18
+#define DPM_TABLE_116__GraphicsLevel_1_PowerThrottle_MASK 0xff
+#define DPM_TABLE_116__GraphicsLevel_1_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_116__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_116__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_116__GraphicsLevel_1_DownHyst_MASK 0xff0000
+#define DPM_TABLE_116__GraphicsLevel_1_DownHyst__SHIFT 0x10
+#define DPM_TABLE_116__GraphicsLevel_1_UpHyst_MASK 0xff000000
+#define DPM_TABLE_116__GraphicsLevel_1_UpHyst__SHIFT 0x18
+#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_118__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_118__GraphicsLevel_2_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_119__GraphicsLevel_2_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_119__GraphicsLevel_2_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_119__GraphicsLevel_2_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_119__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_119__GraphicsLevel_2_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_119__GraphicsLevel_2_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_120__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_120__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_121__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_121__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_122__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_122__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_123__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_123__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_124__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_124__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_125__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_125__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_126__GraphicsLevel_2_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_126__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_126__GraphicsLevel_2_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_126__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_126__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_126__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_126__GraphicsLevel_2_SclkDid_MASK 0xff000000
+#define DPM_TABLE_126__GraphicsLevel_2_SclkDid__SHIFT 0x18
+#define DPM_TABLE_127__GraphicsLevel_2_PowerThrottle_MASK 0xff
+#define DPM_TABLE_127__GraphicsLevel_2_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_127__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_127__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_127__GraphicsLevel_2_DownHyst_MASK 0xff0000
+#define DPM_TABLE_127__GraphicsLevel_2_DownHyst__SHIFT 0x10
+#define DPM_TABLE_127__GraphicsLevel_2_UpHyst_MASK 0xff000000
+#define DPM_TABLE_127__GraphicsLevel_2_UpHyst__SHIFT 0x18
+#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_129__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_129__GraphicsLevel_3_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_130__GraphicsLevel_3_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_130__GraphicsLevel_3_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_130__GraphicsLevel_3_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_130__GraphicsLevel_3_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_131__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_131__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_132__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_132__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_133__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_133__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_134__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_134__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_135__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_135__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_136__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_136__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_137__GraphicsLevel_3_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_137__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_137__GraphicsLevel_3_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_137__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_137__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_137__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_137__GraphicsLevel_3_SclkDid_MASK 0xff000000
+#define DPM_TABLE_137__GraphicsLevel_3_SclkDid__SHIFT 0x18
+#define DPM_TABLE_138__GraphicsLevel_3_PowerThrottle_MASK 0xff
+#define DPM_TABLE_138__GraphicsLevel_3_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_138__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_138__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_138__GraphicsLevel_3_DownHyst_MASK 0xff0000
+#define DPM_TABLE_138__GraphicsLevel_3_DownHyst__SHIFT 0x10
+#define DPM_TABLE_138__GraphicsLevel_3_UpHyst_MASK 0xff000000
+#define DPM_TABLE_138__GraphicsLevel_3_UpHyst__SHIFT 0x18
+#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_140__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_140__GraphicsLevel_4_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_141__GraphicsLevel_4_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_141__GraphicsLevel_4_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_141__GraphicsLevel_4_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_141__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_141__GraphicsLevel_4_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_141__GraphicsLevel_4_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_142__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_142__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_143__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_143__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_144__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_144__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_145__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_145__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_146__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_146__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_147__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_147__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_148__GraphicsLevel_4_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_148__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_148__GraphicsLevel_4_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_148__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_148__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_148__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_148__GraphicsLevel_4_SclkDid_MASK 0xff000000
+#define DPM_TABLE_148__GraphicsLevel_4_SclkDid__SHIFT 0x18
+#define DPM_TABLE_149__GraphicsLevel_4_PowerThrottle_MASK 0xff
+#define DPM_TABLE_149__GraphicsLevel_4_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_149__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_149__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_149__GraphicsLevel_4_DownHyst_MASK 0xff0000
+#define DPM_TABLE_149__GraphicsLevel_4_DownHyst__SHIFT 0x10
+#define DPM_TABLE_149__GraphicsLevel_4_UpHyst_MASK 0xff000000
+#define DPM_TABLE_149__GraphicsLevel_4_UpHyst__SHIFT 0x18
+#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_151__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_151__GraphicsLevel_5_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_152__GraphicsLevel_5_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_152__GraphicsLevel_5_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_152__GraphicsLevel_5_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_152__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_152__GraphicsLevel_5_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_152__GraphicsLevel_5_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_153__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_153__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_154__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_154__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_155__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_155__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_156__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_156__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_157__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_157__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_158__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_158__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_159__GraphicsLevel_5_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_159__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_159__GraphicsLevel_5_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_159__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_159__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_159__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_159__GraphicsLevel_5_SclkDid_MASK 0xff000000
+#define DPM_TABLE_159__GraphicsLevel_5_SclkDid__SHIFT 0x18
+#define DPM_TABLE_160__GraphicsLevel_5_PowerThrottle_MASK 0xff
+#define DPM_TABLE_160__GraphicsLevel_5_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_160__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_160__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_160__GraphicsLevel_5_DownHyst_MASK 0xff0000
+#define DPM_TABLE_160__GraphicsLevel_5_DownHyst__SHIFT 0x10
+#define DPM_TABLE_160__GraphicsLevel_5_UpHyst_MASK 0xff000000
+#define DPM_TABLE_160__GraphicsLevel_5_UpHyst__SHIFT 0x18
+#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_163__GraphicsLevel_6_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_163__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_170__GraphicsLevel_6_SclkDid_MASK 0xff000000
+#define DPM_TABLE_170__GraphicsLevel_6_SclkDid__SHIFT 0x18
+#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle_MASK 0xff
+#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_171__GraphicsLevel_6_DownHyst_MASK 0xff0000
+#define DPM_TABLE_171__GraphicsLevel_6_DownHyst__SHIFT 0x10
+#define DPM_TABLE_171__GraphicsLevel_6_UpHyst_MASK 0xff000000
+#define DPM_TABLE_171__GraphicsLevel_6_UpHyst__SHIFT 0x18
+#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_173__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_173__GraphicsLevel_7_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_174__GraphicsLevel_7_ActivityLevel_MASK 0xffff
+#define DPM_TABLE_174__GraphicsLevel_7_ActivityLevel__SHIFT 0x0
+#define DPM_TABLE_174__GraphicsLevel_7_DeepSleepDivId_MASK 0xff0000
+#define DPM_TABLE_174__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x10
+#define DPM_TABLE_174__GraphicsLevel_7_pcieDpmLevel_MASK 0xff000000
+#define DPM_TABLE_174__GraphicsLevel_7_pcieDpmLevel__SHIFT 0x18
+#define DPM_TABLE_175__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_175__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_176__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_176__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_177__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_177__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_178__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_178__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_179__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_179__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_180__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_180__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_181__GraphicsLevel_7_EnabledForThrottle_MASK 0xff
+#define DPM_TABLE_181__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0
+#define DPM_TABLE_181__GraphicsLevel_7_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_181__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_181__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_181__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_181__GraphicsLevel_7_SclkDid_MASK 0xff000000
+#define DPM_TABLE_181__GraphicsLevel_7_SclkDid__SHIFT 0x18
+#define DPM_TABLE_182__GraphicsLevel_7_PowerThrottle_MASK 0xff
+#define DPM_TABLE_182__GraphicsLevel_7_PowerThrottle__SHIFT 0x0
+#define DPM_TABLE_182__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_182__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_182__GraphicsLevel_7_DownHyst_MASK 0xff0000
+#define DPM_TABLE_182__GraphicsLevel_7_DownHyst__SHIFT 0x10
+#define DPM_TABLE_182__GraphicsLevel_7_UpHyst_MASK 0xff000000
+#define DPM_TABLE_182__GraphicsLevel_7_UpHyst__SHIFT 0x18
+#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_184__MemoryACPILevel_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_184__MemoryACPILevel_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_185__MemoryACPILevel_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_185__MemoryACPILevel_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_186__MemoryACPILevel_StutterEnable_MASK 0xff
+#define DPM_TABLE_186__MemoryACPILevel_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_186__MemoryACPILevel_RttEnable_MASK 0xff00
+#define DPM_TABLE_186__MemoryACPILevel_RttEnable__SHIFT 0x8
+#define DPM_TABLE_186__MemoryACPILevel_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_186__MemoryACPILevel_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_186__MemoryACPILevel_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_186__MemoryACPILevel_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_187__MemoryACPILevel_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_187__MemoryACPILevel_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_187__MemoryACPILevel_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_187__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_187__MemoryACPILevel_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_187__MemoryACPILevel_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_187__MemoryACPILevel_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_187__MemoryACPILevel_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_188__MemoryACPILevel_padding_MASK 0xff
+#define DPM_TABLE_188__MemoryACPILevel_padding__SHIFT 0x0
+#define DPM_TABLE_188__MemoryACPILevel_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_188__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_188__MemoryACPILevel_DownHyst_MASK 0xff0000
+#define DPM_TABLE_188__MemoryACPILevel_DownHyst__SHIFT 0x10
+#define DPM_TABLE_188__MemoryACPILevel_UpHyst_MASK 0xff000000
+#define DPM_TABLE_188__MemoryACPILevel_UpHyst__SHIFT 0x18
+#define DPM_TABLE_189__MemoryACPILevel_padding1_MASK 0xff
+#define DPM_TABLE_189__MemoryACPILevel_padding1__SHIFT 0x0
+#define DPM_TABLE_189__MemoryACPILevel_DisplayWatermark_MASK 0xff00
+#define DPM_TABLE_189__MemoryACPILevel_DisplayWatermark__SHIFT 0x8
+#define DPM_TABLE_189__MemoryACPILevel_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_189__MemoryACPILevel_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_190__MemoryACPILevel_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_190__MemoryACPILevel_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_191__MemoryACPILevel_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_191__MemoryACPILevel_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_192__MemoryACPILevel_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_192__MemoryACPILevel_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_193__MemoryACPILevel_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_193__MemoryACPILevel_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_194__MemoryACPILevel_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_194__MemoryACPILevel_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_195__MemoryACPILevel_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_195__MemoryACPILevel_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_196__MemoryACPILevel_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_196__MemoryACPILevel_DllCntl__SHIFT 0x0
+#define DPM_TABLE_197__MemoryACPILevel_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_197__MemoryACPILevel_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_198__MemoryACPILevel_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_198__MemoryACPILevel_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_199__MemoryLevel_0_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_200__MemoryLevel_0_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_200__MemoryLevel_0_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_201__MemoryLevel_0_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_201__MemoryLevel_0_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_202__MemoryLevel_0_StutterEnable_MASK 0xff
+#define DPM_TABLE_202__MemoryLevel_0_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_202__MemoryLevel_0_RttEnable_MASK 0xff00
+#define DPM_TABLE_202__MemoryLevel_0_RttEnable__SHIFT 0x8
+#define DPM_TABLE_202__MemoryLevel_0_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_202__MemoryLevel_0_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_202__MemoryLevel_0_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_202__MemoryLevel_0_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_203__MemoryLevel_0_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_203__MemoryLevel_0_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_203__MemoryLevel_0_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_203__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_203__MemoryLevel_0_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_203__MemoryLevel_0_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_203__MemoryLevel_0_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_203__MemoryLevel_0_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_204__MemoryLevel_0_padding_MASK 0xff
+#define DPM_TABLE_204__MemoryLevel_0_padding__SHIFT 0x0
+#define DPM_TABLE_204__MemoryLevel_0_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_204__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_204__MemoryLevel_0_DownHyst_MASK 0xff0000
+#define DPM_TABLE_204__MemoryLevel_0_DownHyst__SHIFT 0x10
+#define DPM_TABLE_204__MemoryLevel_0_UpHyst_MASK 0xff000000
+#define DPM_TABLE_204__MemoryLevel_0_UpHyst__SHIFT 0x18
+#define DPM_TABLE_205__MemoryLevel_0_padding1_MASK 0xff
+#define DPM_TABLE_205__MemoryLevel_0_padding1__SHIFT 0x0
+#define DPM_TABLE_205__MemoryLevel_0_DisplayWatermark_MASK 0xff00
+#define DPM_TABLE_205__MemoryLevel_0_DisplayWatermark__SHIFT 0x8
+#define DPM_TABLE_205__MemoryLevel_0_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_205__MemoryLevel_0_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_206__MemoryLevel_0_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_206__MemoryLevel_0_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_207__MemoryLevel_0_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_207__MemoryLevel_0_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_208__MemoryLevel_0_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_208__MemoryLevel_0_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_209__MemoryLevel_0_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_209__MemoryLevel_0_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_210__MemoryLevel_0_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_210__MemoryLevel_0_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_211__MemoryLevel_0_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_211__MemoryLevel_0_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_212__MemoryLevel_0_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_212__MemoryLevel_0_DllCntl__SHIFT 0x0
+#define DPM_TABLE_213__MemoryLevel_0_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_213__MemoryLevel_0_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_214__MemoryLevel_0_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_214__MemoryLevel_0_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_215__MemoryLevel_1_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_216__MemoryLevel_1_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_216__MemoryLevel_1_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_217__MemoryLevel_1_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_217__MemoryLevel_1_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_218__MemoryLevel_1_StutterEnable_MASK 0xff
+#define DPM_TABLE_218__MemoryLevel_1_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_218__MemoryLevel_1_RttEnable_MASK 0xff00
+#define DPM_TABLE_218__MemoryLevel_1_RttEnable__SHIFT 0x8
+#define DPM_TABLE_218__MemoryLevel_1_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_218__MemoryLevel_1_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_218__MemoryLevel_1_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_218__MemoryLevel_1_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_219__MemoryLevel_1_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_219__MemoryLevel_1_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_219__MemoryLevel_1_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_219__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_219__MemoryLevel_1_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_219__MemoryLevel_1_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_219__MemoryLevel_1_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_219__MemoryLevel_1_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_220__MemoryLevel_1_padding_MASK 0xff
+#define DPM_TABLE_220__MemoryLevel_1_padding__SHIFT 0x0
+#define DPM_TABLE_220__MemoryLevel_1_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_220__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_220__MemoryLevel_1_DownHyst_MASK 0xff0000
+#define DPM_TABLE_220__MemoryLevel_1_DownHyst__SHIFT 0x10
+#define DPM_TABLE_220__MemoryLevel_1_UpHyst_MASK 0xff000000
+#define DPM_TABLE_220__MemoryLevel_1_UpHyst__SHIFT 0x18
+#define DPM_TABLE_221__MemoryLevel_1_padding1_MASK 0xff
+#define DPM_TABLE_221__MemoryLevel_1_padding1__SHIFT 0x0
+#define DPM_TABLE_221__MemoryLevel_1_DisplayWatermark_MASK 0xff00
+#define DPM_TABLE_221__MemoryLevel_1_DisplayWatermark__SHIFT 0x8
+#define DPM_TABLE_221__MemoryLevel_1_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_221__MemoryLevel_1_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_222__MemoryLevel_1_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_222__MemoryLevel_1_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_223__MemoryLevel_1_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_223__MemoryLevel_1_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_224__MemoryLevel_1_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_224__MemoryLevel_1_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_225__MemoryLevel_1_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_225__MemoryLevel_1_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_226__MemoryLevel_1_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_226__MemoryLevel_1_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_227__MemoryLevel_1_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_227__MemoryLevel_1_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_228__MemoryLevel_1_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_228__MemoryLevel_1_DllCntl__SHIFT 0x0
+#define DPM_TABLE_229__MemoryLevel_1_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_229__MemoryLevel_1_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_230__MemoryLevel_1_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_230__MemoryLevel_1_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_231__MemoryLevel_2_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_232__MemoryLevel_2_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_232__MemoryLevel_2_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_233__MemoryLevel_2_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_233__MemoryLevel_2_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_234__MemoryLevel_2_StutterEnable_MASK 0xff
+#define DPM_TABLE_234__MemoryLevel_2_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_234__MemoryLevel_2_RttEnable_MASK 0xff00
+#define DPM_TABLE_234__MemoryLevel_2_RttEnable__SHIFT 0x8
+#define DPM_TABLE_234__MemoryLevel_2_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_234__MemoryLevel_2_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_234__MemoryLevel_2_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_234__MemoryLevel_2_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_235__MemoryLevel_2_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_235__MemoryLevel_2_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_235__MemoryLevel_2_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_235__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_235__MemoryLevel_2_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_235__MemoryLevel_2_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_235__MemoryLevel_2_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_235__MemoryLevel_2_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_236__MemoryLevel_2_padding_MASK 0xff
+#define DPM_TABLE_236__MemoryLevel_2_padding__SHIFT 0x0
+#define DPM_TABLE_236__MemoryLevel_2_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_236__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_236__MemoryLevel_2_DownHyst_MASK 0xff0000
+#define DPM_TABLE_236__MemoryLevel_2_DownHyst__SHIFT 0x10
+#define DPM_TABLE_236__MemoryLevel_2_UpHyst_MASK 0xff000000
+#define DPM_TABLE_236__MemoryLevel_2_UpHyst__SHIFT 0x18
+#define DPM_TABLE_237__MemoryLevel_2_padding1_MASK 0xff
+#define DPM_TABLE_237__MemoryLevel_2_padding1__SHIFT 0x0
+#define DPM_TABLE_237__MemoryLevel_2_DisplayWatermark_MASK 0xff00
+#define DPM_TABLE_237__MemoryLevel_2_DisplayWatermark__SHIFT 0x8
+#define DPM_TABLE_237__MemoryLevel_2_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_237__MemoryLevel_2_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_238__MemoryLevel_2_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_238__MemoryLevel_2_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_239__MemoryLevel_2_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_239__MemoryLevel_2_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_240__MemoryLevel_2_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_240__MemoryLevel_2_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_241__MemoryLevel_2_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_241__MemoryLevel_2_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_242__MemoryLevel_2_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_242__MemoryLevel_2_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_243__MemoryLevel_2_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_243__MemoryLevel_2_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_244__MemoryLevel_2_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_244__MemoryLevel_2_DllCntl__SHIFT 0x0
+#define DPM_TABLE_245__MemoryLevel_2_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_245__MemoryLevel_2_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_246__MemoryLevel_2_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_246__MemoryLevel_2_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_247__MemoryLevel_3_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_248__MemoryLevel_3_MinMvdd_MASK 0xffffffff
+#define DPM_TABLE_248__MemoryLevel_3_MinMvdd__SHIFT 0x0
+#define DPM_TABLE_249__MemoryLevel_3_MclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_249__MemoryLevel_3_MclkFrequency__SHIFT 0x0
+#define DPM_TABLE_250__MemoryLevel_3_StutterEnable_MASK 0xff
+#define DPM_TABLE_250__MemoryLevel_3_StutterEnable__SHIFT 0x0
+#define DPM_TABLE_250__MemoryLevel_3_RttEnable_MASK 0xff00
+#define DPM_TABLE_250__MemoryLevel_3_RttEnable__SHIFT 0x8
+#define DPM_TABLE_250__MemoryLevel_3_EdcWriteEnable_MASK 0xff0000
+#define DPM_TABLE_250__MemoryLevel_3_EdcWriteEnable__SHIFT 0x10
+#define DPM_TABLE_250__MemoryLevel_3_EdcReadEnable_MASK 0xff000000
+#define DPM_TABLE_250__MemoryLevel_3_EdcReadEnable__SHIFT 0x18
+#define DPM_TABLE_251__MemoryLevel_3_EnabledForActivity_MASK 0xff
+#define DPM_TABLE_251__MemoryLevel_3_EnabledForActivity__SHIFT 0x0
+#define DPM_TABLE_251__MemoryLevel_3_EnabledForThrottle_MASK 0xff00
+#define DPM_TABLE_251__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8
+#define DPM_TABLE_251__MemoryLevel_3_StrobeRatio_MASK 0xff0000
+#define DPM_TABLE_251__MemoryLevel_3_StrobeRatio__SHIFT 0x10
+#define DPM_TABLE_251__MemoryLevel_3_StrobeEnable_MASK 0xff000000
+#define DPM_TABLE_251__MemoryLevel_3_StrobeEnable__SHIFT 0x18
+#define DPM_TABLE_252__MemoryLevel_3_padding_MASK 0xff
+#define DPM_TABLE_252__MemoryLevel_3_padding__SHIFT 0x0
+#define DPM_TABLE_252__MemoryLevel_3_VoltageDownHyst_MASK 0xff00
+#define DPM_TABLE_252__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8
+#define DPM_TABLE_252__MemoryLevel_3_DownHyst_MASK 0xff0000
+#define DPM_TABLE_252__MemoryLevel_3_DownHyst__SHIFT 0x10
+#define DPM_TABLE_252__MemoryLevel_3_UpHyst_MASK 0xff000000
+#define DPM_TABLE_252__MemoryLevel_3_UpHyst__SHIFT 0x18
+#define DPM_TABLE_253__MemoryLevel_3_padding1_MASK 0xff
+#define DPM_TABLE_253__MemoryLevel_3_padding1__SHIFT 0x0
+#define DPM_TABLE_253__MemoryLevel_3_DisplayWatermark_MASK 0xff00
+#define DPM_TABLE_253__MemoryLevel_3_DisplayWatermark__SHIFT 0x8
+#define DPM_TABLE_253__MemoryLevel_3_ActivityLevel_MASK 0xffff0000
+#define DPM_TABLE_253__MemoryLevel_3_ActivityLevel__SHIFT 0x10
+#define DPM_TABLE_254__MemoryLevel_3_MpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_254__MemoryLevel_3_MpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_255__MemoryLevel_3_MpllFuncCntl_1_MASK 0xffffffff
+#define DPM_TABLE_255__MemoryLevel_3_MpllFuncCntl_1__SHIFT 0x0
+#define DPM_TABLE_256__MemoryLevel_3_MpllFuncCntl_2_MASK 0xffffffff
+#define DPM_TABLE_256__MemoryLevel_3_MpllFuncCntl_2__SHIFT 0x0
+#define DPM_TABLE_257__MemoryLevel_3_MpllAdFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_257__MemoryLevel_3_MpllAdFuncCntl__SHIFT 0x0
+#define DPM_TABLE_258__MemoryLevel_3_MpllDqFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_258__MemoryLevel_3_MpllDqFuncCntl__SHIFT 0x0
+#define DPM_TABLE_259__MemoryLevel_3_MclkPwrmgtCntl_MASK 0xffffffff
+#define DPM_TABLE_259__MemoryLevel_3_MclkPwrmgtCntl__SHIFT 0x0
+#define DPM_TABLE_260__MemoryLevel_3_DllCntl_MASK 0xffffffff
+#define DPM_TABLE_260__MemoryLevel_3_DllCntl__SHIFT 0x0
+#define DPM_TABLE_261__MemoryLevel_3_MpllSs1_MASK 0xffffffff
+#define DPM_TABLE_261__MemoryLevel_3_MpllSs1__SHIFT 0x0
+#define DPM_TABLE_262__MemoryLevel_3_MpllSs2_MASK 0xffffffff
+#define DPM_TABLE_262__MemoryLevel_3_MpllSs2__SHIFT 0x0
+#define DPM_TABLE_263__LinkLevel_0_SPC_MASK 0xff
+#define DPM_TABLE_263__LinkLevel_0_SPC__SHIFT 0x0
+#define DPM_TABLE_263__LinkLevel_0_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_263__LinkLevel_0_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_263__LinkLevel_0_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_263__LinkLevel_0_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_263__LinkLevel_0_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_263__LinkLevel_0_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_264__LinkLevel_0_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_264__LinkLevel_0_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_265__LinkLevel_0_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_265__LinkLevel_0_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_266__LinkLevel_0_Reserved_MASK 0xffffffff
+#define DPM_TABLE_266__LinkLevel_0_Reserved__SHIFT 0x0
+#define DPM_TABLE_267__LinkLevel_1_SPC_MASK 0xff
+#define DPM_TABLE_267__LinkLevel_1_SPC__SHIFT 0x0
+#define DPM_TABLE_267__LinkLevel_1_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_267__LinkLevel_1_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_267__LinkLevel_1_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_267__LinkLevel_1_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_267__LinkLevel_1_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_267__LinkLevel_1_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_268__LinkLevel_1_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_268__LinkLevel_1_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_269__LinkLevel_1_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_269__LinkLevel_1_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_270__LinkLevel_1_Reserved_MASK 0xffffffff
+#define DPM_TABLE_270__LinkLevel_1_Reserved__SHIFT 0x0
+#define DPM_TABLE_271__LinkLevel_2_SPC_MASK 0xff
+#define DPM_TABLE_271__LinkLevel_2_SPC__SHIFT 0x0
+#define DPM_TABLE_271__LinkLevel_2_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_271__LinkLevel_2_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_271__LinkLevel_2_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_271__LinkLevel_2_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_271__LinkLevel_2_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_271__LinkLevel_2_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_272__LinkLevel_2_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_272__LinkLevel_2_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_273__LinkLevel_2_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_273__LinkLevel_2_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_274__LinkLevel_2_Reserved_MASK 0xffffffff
+#define DPM_TABLE_274__LinkLevel_2_Reserved__SHIFT 0x0
+#define DPM_TABLE_275__LinkLevel_3_SPC_MASK 0xff
+#define DPM_TABLE_275__LinkLevel_3_SPC__SHIFT 0x0
+#define DPM_TABLE_275__LinkLevel_3_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_275__LinkLevel_3_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_275__LinkLevel_3_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_275__LinkLevel_3_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_275__LinkLevel_3_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_275__LinkLevel_3_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_276__LinkLevel_3_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_276__LinkLevel_3_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_277__LinkLevel_3_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_277__LinkLevel_3_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_278__LinkLevel_3_Reserved_MASK 0xffffffff
+#define DPM_TABLE_278__LinkLevel_3_Reserved__SHIFT 0x0
+#define DPM_TABLE_279__LinkLevel_4_SPC_MASK 0xff
+#define DPM_TABLE_279__LinkLevel_4_SPC__SHIFT 0x0
+#define DPM_TABLE_279__LinkLevel_4_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_279__LinkLevel_4_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_279__LinkLevel_4_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_279__LinkLevel_4_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_279__LinkLevel_4_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_279__LinkLevel_4_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_280__LinkLevel_4_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_280__LinkLevel_4_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_281__LinkLevel_4_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_281__LinkLevel_4_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_282__LinkLevel_4_Reserved_MASK 0xffffffff
+#define DPM_TABLE_282__LinkLevel_4_Reserved__SHIFT 0x0
+#define DPM_TABLE_283__LinkLevel_5_SPC_MASK 0xff
+#define DPM_TABLE_283__LinkLevel_5_SPC__SHIFT 0x0
+#define DPM_TABLE_283__LinkLevel_5_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_283__LinkLevel_5_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_283__LinkLevel_5_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_283__LinkLevel_5_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_283__LinkLevel_5_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_283__LinkLevel_5_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_284__LinkLevel_5_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_284__LinkLevel_5_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_285__LinkLevel_5_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_285__LinkLevel_5_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_286__LinkLevel_5_Reserved_MASK 0xffffffff
+#define DPM_TABLE_286__LinkLevel_5_Reserved__SHIFT 0x0
+#define DPM_TABLE_287__LinkLevel_6_SPC_MASK 0xff
+#define DPM_TABLE_287__LinkLevel_6_SPC__SHIFT 0x0
+#define DPM_TABLE_287__LinkLevel_6_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_287__LinkLevel_6_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_287__LinkLevel_6_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_287__LinkLevel_6_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_287__LinkLevel_6_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_287__LinkLevel_6_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_288__LinkLevel_6_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_288__LinkLevel_6_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_289__LinkLevel_6_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_289__LinkLevel_6_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_290__LinkLevel_6_Reserved_MASK 0xffffffff
+#define DPM_TABLE_290__LinkLevel_6_Reserved__SHIFT 0x0
+#define DPM_TABLE_291__LinkLevel_7_SPC_MASK 0xff
+#define DPM_TABLE_291__LinkLevel_7_SPC__SHIFT 0x0
+#define DPM_TABLE_291__LinkLevel_7_EnabledForActivity_MASK 0xff00
+#define DPM_TABLE_291__LinkLevel_7_EnabledForActivity__SHIFT 0x8
+#define DPM_TABLE_291__LinkLevel_7_PcieLaneCount_MASK 0xff0000
+#define DPM_TABLE_291__LinkLevel_7_PcieLaneCount__SHIFT 0x10
+#define DPM_TABLE_291__LinkLevel_7_PcieGenSpeed_MASK 0xff000000
+#define DPM_TABLE_291__LinkLevel_7_PcieGenSpeed__SHIFT 0x18
+#define DPM_TABLE_292__LinkLevel_7_DownThreshold_MASK 0xffffffff
+#define DPM_TABLE_292__LinkLevel_7_DownThreshold__SHIFT 0x0
+#define DPM_TABLE_293__LinkLevel_7_UpThreshold_MASK 0xffffffff
+#define DPM_TABLE_293__LinkLevel_7_UpThreshold__SHIFT 0x0
+#define DPM_TABLE_294__LinkLevel_7_Reserved_MASK 0xffffffff
+#define DPM_TABLE_294__LinkLevel_7_Reserved__SHIFT 0x0
+#define DPM_TABLE_295__ACPILevel_Flags_MASK 0xffffffff
+#define DPM_TABLE_295__ACPILevel_Flags__SHIFT 0x0
+#define DPM_TABLE_296__ACPILevel_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_296__ACPILevel_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_296__ACPILevel_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_296__ACPILevel_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_296__ACPILevel_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_296__ACPILevel_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_296__ACPILevel_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_296__ACPILevel_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_297__ACPILevel_SclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_297__ACPILevel_SclkFrequency__SHIFT 0x0
+#define DPM_TABLE_298__ACPILevel_padding_MASK 0xff
+#define DPM_TABLE_298__ACPILevel_padding__SHIFT 0x0
+#define DPM_TABLE_298__ACPILevel_DeepSleepDivId_MASK 0xff00
+#define DPM_TABLE_298__ACPILevel_DeepSleepDivId__SHIFT 0x8
+#define DPM_TABLE_298__ACPILevel_DisplayWatermark_MASK 0xff0000
+#define DPM_TABLE_298__ACPILevel_DisplayWatermark__SHIFT 0x10
+#define DPM_TABLE_298__ACPILevel_SclkDid_MASK 0xff000000
+#define DPM_TABLE_298__ACPILevel_SclkDid__SHIFT 0x18
+#define DPM_TABLE_299__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff
+#define DPM_TABLE_299__ACPILevel_CgSpllFuncCntl__SHIFT 0x0
+#define DPM_TABLE_300__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff
+#define DPM_TABLE_300__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0
+#define DPM_TABLE_301__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff
+#define DPM_TABLE_301__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0
+#define DPM_TABLE_302__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff
+#define DPM_TABLE_302__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0
+#define DPM_TABLE_303__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff
+#define DPM_TABLE_303__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0
+#define DPM_TABLE_304__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff
+#define DPM_TABLE_304__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0
+#define DPM_TABLE_305__ACPILevel_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_305__ACPILevel_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_306__ACPILevel_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_306__ACPILevel_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_307__UvdLevel_0_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_307__UvdLevel_0_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_308__UvdLevel_0_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_308__UvdLevel_0_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_309__UvdLevel_0_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_309__UvdLevel_0_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_309__UvdLevel_0_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_310__UvdLevel_0_padding_1_MASK 0xff
+#define DPM_TABLE_310__UvdLevel_0_padding_1__SHIFT 0x0
+#define DPM_TABLE_310__UvdLevel_0_padding_0_MASK 0xff00
+#define DPM_TABLE_310__UvdLevel_0_padding_0__SHIFT 0x8
+#define DPM_TABLE_310__UvdLevel_0_DclkDivider_MASK 0xff0000
+#define DPM_TABLE_310__UvdLevel_0_DclkDivider__SHIFT 0x10
+#define DPM_TABLE_310__UvdLevel_0_VclkDivider_MASK 0xff000000
+#define DPM_TABLE_310__UvdLevel_0_VclkDivider__SHIFT 0x18
+#define DPM_TABLE_311__UvdLevel_1_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_311__UvdLevel_1_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_312__UvdLevel_1_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_312__UvdLevel_1_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_313__UvdLevel_1_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_313__UvdLevel_1_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_313__UvdLevel_1_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_314__UvdLevel_1_padding_1_MASK 0xff
+#define DPM_TABLE_314__UvdLevel_1_padding_1__SHIFT 0x0
+#define DPM_TABLE_314__UvdLevel_1_padding_0_MASK 0xff00
+#define DPM_TABLE_314__UvdLevel_1_padding_0__SHIFT 0x8
+#define DPM_TABLE_314__UvdLevel_1_DclkDivider_MASK 0xff0000
+#define DPM_TABLE_314__UvdLevel_1_DclkDivider__SHIFT 0x10
+#define DPM_TABLE_314__UvdLevel_1_VclkDivider_MASK 0xff000000
+#define DPM_TABLE_314__UvdLevel_1_VclkDivider__SHIFT 0x18
+#define DPM_TABLE_315__UvdLevel_2_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_315__UvdLevel_2_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_316__UvdLevel_2_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_316__UvdLevel_2_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_317__UvdLevel_2_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_317__UvdLevel_2_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_317__UvdLevel_2_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_318__UvdLevel_2_padding_1_MASK 0xff
+#define DPM_TABLE_318__UvdLevel_2_padding_1__SHIFT 0x0
+#define DPM_TABLE_318__UvdLevel_2_padding_0_MASK 0xff00
+#define DPM_TABLE_318__UvdLevel_2_padding_0__SHIFT 0x8
+#define DPM_TABLE_318__UvdLevel_2_DclkDivider_MASK 0xff0000
+#define DPM_TABLE_318__UvdLevel_2_DclkDivider__SHIFT 0x10
+#define DPM_TABLE_318__UvdLevel_2_VclkDivider_MASK 0xff000000
+#define DPM_TABLE_318__UvdLevel_2_VclkDivider__SHIFT 0x18
+#define DPM_TABLE_319__UvdLevel_3_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_319__UvdLevel_3_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_320__UvdLevel_3_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_320__UvdLevel_3_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_321__UvdLevel_3_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_321__UvdLevel_3_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_321__UvdLevel_3_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_322__UvdLevel_3_padding_1_MASK 0xff
+#define DPM_TABLE_322__UvdLevel_3_padding_1__SHIFT 0x0
+#define DPM_TABLE_322__UvdLevel_3_padding_0_MASK 0xff00
+#define DPM_TABLE_322__UvdLevel_3_padding_0__SHIFT 0x8
+#define DPM_TABLE_322__UvdLevel_3_DclkDivider_MASK 0xff0000
+#define DPM_TABLE_322__UvdLevel_3_DclkDivider__SHIFT 0x10
+#define DPM_TABLE_322__UvdLevel_3_VclkDivider_MASK 0xff000000
+#define DPM_TABLE_322__UvdLevel_3_VclkDivider__SHIFT 0x18
+#define DPM_TABLE_323__UvdLevel_4_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_323__UvdLevel_4_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_324__UvdLevel_4_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_324__UvdLevel_4_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_325__UvdLevel_4_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_325__UvdLevel_4_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_325__UvdLevel_4_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_326__UvdLevel_4_padding_1_MASK 0xff
+#define DPM_TABLE_326__UvdLevel_4_padding_1__SHIFT 0x0
+#define DPM_TABLE_326__UvdLevel_4_padding_0_MASK 0xff00
+#define DPM_TABLE_326__UvdLevel_4_padding_0__SHIFT 0x8
+#define DPM_TABLE_326__UvdLevel_4_DclkDivider_MASK 0xff0000
+#define DPM_TABLE_326__UvdLevel_4_DclkDivider__SHIFT 0x10
+#define DPM_TABLE_326__UvdLevel_4_VclkDivider_MASK 0xff000000
+#define DPM_TABLE_326__UvdLevel_4_VclkDivider__SHIFT 0x18
+#define DPM_TABLE_327__UvdLevel_5_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_327__UvdLevel_5_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_328__UvdLevel_5_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_328__UvdLevel_5_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_329__UvdLevel_5_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_329__UvdLevel_5_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_329__UvdLevel_5_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_330__UvdLevel_5_padding_1_MASK 0xff
+#define DPM_TABLE_330__UvdLevel_5_padding_1__SHIFT 0x0
+#define DPM_TABLE_330__UvdLevel_5_padding_0_MASK 0xff00
+#define DPM_TABLE_330__UvdLevel_5_padding_0__SHIFT 0x8
+#define DPM_TABLE_330__UvdLevel_5_DclkDivider_MASK 0xff0000
+#define DPM_TABLE_330__UvdLevel_5_DclkDivider__SHIFT 0x10
+#define DPM_TABLE_330__UvdLevel_5_VclkDivider_MASK 0xff000000
+#define DPM_TABLE_330__UvdLevel_5_VclkDivider__SHIFT 0x18
+#define DPM_TABLE_331__UvdLevel_6_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_331__UvdLevel_6_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_332__UvdLevel_6_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_332__UvdLevel_6_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_333__UvdLevel_6_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_333__UvdLevel_6_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_333__UvdLevel_6_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_334__UvdLevel_6_padding_1_MASK 0xff
+#define DPM_TABLE_334__UvdLevel_6_padding_1__SHIFT 0x0
+#define DPM_TABLE_334__UvdLevel_6_padding_0_MASK 0xff00
+#define DPM_TABLE_334__UvdLevel_6_padding_0__SHIFT 0x8
+#define DPM_TABLE_334__UvdLevel_6_DclkDivider_MASK 0xff0000
+#define DPM_TABLE_334__UvdLevel_6_DclkDivider__SHIFT 0x10
+#define DPM_TABLE_334__UvdLevel_6_VclkDivider_MASK 0xff000000
+#define DPM_TABLE_334__UvdLevel_6_VclkDivider__SHIFT 0x18
+#define DPM_TABLE_335__UvdLevel_7_VclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_335__UvdLevel_7_VclkFrequency__SHIFT 0x0
+#define DPM_TABLE_336__UvdLevel_7_DclkFrequency_MASK 0xffffffff
+#define DPM_TABLE_336__UvdLevel_7_DclkFrequency__SHIFT 0x0
+#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_337__UvdLevel_7_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_337__UvdLevel_7_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_337__UvdLevel_7_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_338__UvdLevel_7_padding_1_MASK 0xff
+#define DPM_TABLE_338__UvdLevel_7_padding_1__SHIFT 0x0
+#define DPM_TABLE_338__UvdLevel_7_padding_0_MASK 0xff00
+#define DPM_TABLE_338__UvdLevel_7_padding_0__SHIFT 0x8
+#define DPM_TABLE_338__UvdLevel_7_DclkDivider_MASK 0xff0000
+#define DPM_TABLE_338__UvdLevel_7_DclkDivider__SHIFT 0x10
+#define DPM_TABLE_338__UvdLevel_7_VclkDivider_MASK 0xff000000
+#define DPM_TABLE_338__UvdLevel_7_VclkDivider__SHIFT 0x18
+#define DPM_TABLE_339__VceLevel_0_Frequency_MASK 0xffffffff
+#define DPM_TABLE_339__VceLevel_0_Frequency__SHIFT 0x0
+#define DPM_TABLE_340__VceLevel_0_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_340__VceLevel_0_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_340__VceLevel_0_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_340__VceLevel_0_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_340__VceLevel_0_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_340__VceLevel_0_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_340__VceLevel_0_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_340__VceLevel_0_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_341__VceLevel_0_padding_2_MASK 0xff
+#define DPM_TABLE_341__VceLevel_0_padding_2__SHIFT 0x0
+#define DPM_TABLE_341__VceLevel_0_padding_1_MASK 0xff00
+#define DPM_TABLE_341__VceLevel_0_padding_1__SHIFT 0x8
+#define DPM_TABLE_341__VceLevel_0_padding_0_MASK 0xff0000
+#define DPM_TABLE_341__VceLevel_0_padding_0__SHIFT 0x10
+#define DPM_TABLE_341__VceLevel_0_Divider_MASK 0xff000000
+#define DPM_TABLE_341__VceLevel_0_Divider__SHIFT 0x18
+#define DPM_TABLE_342__VceLevel_1_Frequency_MASK 0xffffffff
+#define DPM_TABLE_342__VceLevel_1_Frequency__SHIFT 0x0
+#define DPM_TABLE_343__VceLevel_1_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_343__VceLevel_1_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_343__VceLevel_1_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_343__VceLevel_1_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_343__VceLevel_1_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_343__VceLevel_1_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_343__VceLevel_1_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_343__VceLevel_1_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_344__VceLevel_1_padding_2_MASK 0xff
+#define DPM_TABLE_344__VceLevel_1_padding_2__SHIFT 0x0
+#define DPM_TABLE_344__VceLevel_1_padding_1_MASK 0xff00
+#define DPM_TABLE_344__VceLevel_1_padding_1__SHIFT 0x8
+#define DPM_TABLE_344__VceLevel_1_padding_0_MASK 0xff0000
+#define DPM_TABLE_344__VceLevel_1_padding_0__SHIFT 0x10
+#define DPM_TABLE_344__VceLevel_1_Divider_MASK 0xff000000
+#define DPM_TABLE_344__VceLevel_1_Divider__SHIFT 0x18
+#define DPM_TABLE_345__VceLevel_2_Frequency_MASK 0xffffffff
+#define DPM_TABLE_345__VceLevel_2_Frequency__SHIFT 0x0
+#define DPM_TABLE_346__VceLevel_2_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_346__VceLevel_2_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_346__VceLevel_2_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_346__VceLevel_2_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_346__VceLevel_2_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_346__VceLevel_2_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_346__VceLevel_2_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_346__VceLevel_2_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_347__VceLevel_2_padding_2_MASK 0xff
+#define DPM_TABLE_347__VceLevel_2_padding_2__SHIFT 0x0
+#define DPM_TABLE_347__VceLevel_2_padding_1_MASK 0xff00
+#define DPM_TABLE_347__VceLevel_2_padding_1__SHIFT 0x8
+#define DPM_TABLE_347__VceLevel_2_padding_0_MASK 0xff0000
+#define DPM_TABLE_347__VceLevel_2_padding_0__SHIFT 0x10
+#define DPM_TABLE_347__VceLevel_2_Divider_MASK 0xff000000
+#define DPM_TABLE_347__VceLevel_2_Divider__SHIFT 0x18
+#define DPM_TABLE_348__VceLevel_3_Frequency_MASK 0xffffffff
+#define DPM_TABLE_348__VceLevel_3_Frequency__SHIFT 0x0
+#define DPM_TABLE_349__VceLevel_3_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_349__VceLevel_3_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_349__VceLevel_3_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_349__VceLevel_3_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_349__VceLevel_3_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_349__VceLevel_3_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_349__VceLevel_3_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_349__VceLevel_3_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_350__VceLevel_3_padding_2_MASK 0xff
+#define DPM_TABLE_350__VceLevel_3_padding_2__SHIFT 0x0
+#define DPM_TABLE_350__VceLevel_3_padding_1_MASK 0xff00
+#define DPM_TABLE_350__VceLevel_3_padding_1__SHIFT 0x8
+#define DPM_TABLE_350__VceLevel_3_padding_0_MASK 0xff0000
+#define DPM_TABLE_350__VceLevel_3_padding_0__SHIFT 0x10
+#define DPM_TABLE_350__VceLevel_3_Divider_MASK 0xff000000
+#define DPM_TABLE_350__VceLevel_3_Divider__SHIFT 0x18
+#define DPM_TABLE_351__VceLevel_4_Frequency_MASK 0xffffffff
+#define DPM_TABLE_351__VceLevel_4_Frequency__SHIFT 0x0
+#define DPM_TABLE_352__VceLevel_4_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_352__VceLevel_4_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_352__VceLevel_4_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_352__VceLevel_4_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_352__VceLevel_4_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_352__VceLevel_4_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_352__VceLevel_4_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_352__VceLevel_4_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_353__VceLevel_4_padding_2_MASK 0xff
+#define DPM_TABLE_353__VceLevel_4_padding_2__SHIFT 0x0
+#define DPM_TABLE_353__VceLevel_4_padding_1_MASK 0xff00
+#define DPM_TABLE_353__VceLevel_4_padding_1__SHIFT 0x8
+#define DPM_TABLE_353__VceLevel_4_padding_0_MASK 0xff0000
+#define DPM_TABLE_353__VceLevel_4_padding_0__SHIFT 0x10
+#define DPM_TABLE_353__VceLevel_4_Divider_MASK 0xff000000
+#define DPM_TABLE_353__VceLevel_4_Divider__SHIFT 0x18
+#define DPM_TABLE_354__VceLevel_5_Frequency_MASK 0xffffffff
+#define DPM_TABLE_354__VceLevel_5_Frequency__SHIFT 0x0
+#define DPM_TABLE_355__VceLevel_5_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_355__VceLevel_5_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_355__VceLevel_5_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_355__VceLevel_5_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_355__VceLevel_5_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_355__VceLevel_5_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_355__VceLevel_5_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_355__VceLevel_5_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_356__VceLevel_5_padding_2_MASK 0xff
+#define DPM_TABLE_356__VceLevel_5_padding_2__SHIFT 0x0
+#define DPM_TABLE_356__VceLevel_5_padding_1_MASK 0xff00
+#define DPM_TABLE_356__VceLevel_5_padding_1__SHIFT 0x8
+#define DPM_TABLE_356__VceLevel_5_padding_0_MASK 0xff0000
+#define DPM_TABLE_356__VceLevel_5_padding_0__SHIFT 0x10
+#define DPM_TABLE_356__VceLevel_5_Divider_MASK 0xff000000
+#define DPM_TABLE_356__VceLevel_5_Divider__SHIFT 0x18
+#define DPM_TABLE_357__VceLevel_6_Frequency_MASK 0xffffffff
+#define DPM_TABLE_357__VceLevel_6_Frequency__SHIFT 0x0
+#define DPM_TABLE_358__VceLevel_6_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_358__VceLevel_6_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_358__VceLevel_6_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_358__VceLevel_6_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_358__VceLevel_6_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_358__VceLevel_6_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_358__VceLevel_6_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_358__VceLevel_6_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_359__VceLevel_6_padding_2_MASK 0xff
+#define DPM_TABLE_359__VceLevel_6_padding_2__SHIFT 0x0
+#define DPM_TABLE_359__VceLevel_6_padding_1_MASK 0xff00
+#define DPM_TABLE_359__VceLevel_6_padding_1__SHIFT 0x8
+#define DPM_TABLE_359__VceLevel_6_padding_0_MASK 0xff0000
+#define DPM_TABLE_359__VceLevel_6_padding_0__SHIFT 0x10
+#define DPM_TABLE_359__VceLevel_6_Divider_MASK 0xff000000
+#define DPM_TABLE_359__VceLevel_6_Divider__SHIFT 0x18
+#define DPM_TABLE_360__VceLevel_7_Frequency_MASK 0xffffffff
+#define DPM_TABLE_360__VceLevel_7_Frequency__SHIFT 0x0
+#define DPM_TABLE_361__VceLevel_7_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_361__VceLevel_7_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_361__VceLevel_7_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_361__VceLevel_7_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_361__VceLevel_7_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_361__VceLevel_7_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_361__VceLevel_7_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_361__VceLevel_7_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_362__VceLevel_7_padding_2_MASK 0xff
+#define DPM_TABLE_362__VceLevel_7_padding_2__SHIFT 0x0
+#define DPM_TABLE_362__VceLevel_7_padding_1_MASK 0xff00
+#define DPM_TABLE_362__VceLevel_7_padding_1__SHIFT 0x8
+#define DPM_TABLE_362__VceLevel_7_padding_0_MASK 0xff0000
+#define DPM_TABLE_362__VceLevel_7_padding_0__SHIFT 0x10
+#define DPM_TABLE_362__VceLevel_7_Divider_MASK 0xff000000
+#define DPM_TABLE_362__VceLevel_7_Divider__SHIFT 0x18
+#define DPM_TABLE_363__AcpLevel_0_Frequency_MASK 0xffffffff
+#define DPM_TABLE_363__AcpLevel_0_Frequency__SHIFT 0x0
+#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_364__AcpLevel_0_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_364__AcpLevel_0_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_364__AcpLevel_0_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_365__AcpLevel_0_padding_2_MASK 0xff
+#define DPM_TABLE_365__AcpLevel_0_padding_2__SHIFT 0x0
+#define DPM_TABLE_365__AcpLevel_0_padding_1_MASK 0xff00
+#define DPM_TABLE_365__AcpLevel_0_padding_1__SHIFT 0x8
+#define DPM_TABLE_365__AcpLevel_0_padding_0_MASK 0xff0000
+#define DPM_TABLE_365__AcpLevel_0_padding_0__SHIFT 0x10
+#define DPM_TABLE_365__AcpLevel_0_Divider_MASK 0xff000000
+#define DPM_TABLE_365__AcpLevel_0_Divider__SHIFT 0x18
+#define DPM_TABLE_366__AcpLevel_1_Frequency_MASK 0xffffffff
+#define DPM_TABLE_366__AcpLevel_1_Frequency__SHIFT 0x0
+#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_367__AcpLevel_1_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_367__AcpLevel_1_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_367__AcpLevel_1_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_368__AcpLevel_1_padding_2_MASK 0xff
+#define DPM_TABLE_368__AcpLevel_1_padding_2__SHIFT 0x0
+#define DPM_TABLE_368__AcpLevel_1_padding_1_MASK 0xff00
+#define DPM_TABLE_368__AcpLevel_1_padding_1__SHIFT 0x8
+#define DPM_TABLE_368__AcpLevel_1_padding_0_MASK 0xff0000
+#define DPM_TABLE_368__AcpLevel_1_padding_0__SHIFT 0x10
+#define DPM_TABLE_368__AcpLevel_1_Divider_MASK 0xff000000
+#define DPM_TABLE_368__AcpLevel_1_Divider__SHIFT 0x18
+#define DPM_TABLE_369__AcpLevel_2_Frequency_MASK 0xffffffff
+#define DPM_TABLE_369__AcpLevel_2_Frequency__SHIFT 0x0
+#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_370__AcpLevel_2_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_370__AcpLevel_2_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_370__AcpLevel_2_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_371__AcpLevel_2_padding_2_MASK 0xff
+#define DPM_TABLE_371__AcpLevel_2_padding_2__SHIFT 0x0
+#define DPM_TABLE_371__AcpLevel_2_padding_1_MASK 0xff00
+#define DPM_TABLE_371__AcpLevel_2_padding_1__SHIFT 0x8
+#define DPM_TABLE_371__AcpLevel_2_padding_0_MASK 0xff0000
+#define DPM_TABLE_371__AcpLevel_2_padding_0__SHIFT 0x10
+#define DPM_TABLE_371__AcpLevel_2_Divider_MASK 0xff000000
+#define DPM_TABLE_371__AcpLevel_2_Divider__SHIFT 0x18
+#define DPM_TABLE_372__AcpLevel_3_Frequency_MASK 0xffffffff
+#define DPM_TABLE_372__AcpLevel_3_Frequency__SHIFT 0x0
+#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_373__AcpLevel_3_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_373__AcpLevel_3_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_373__AcpLevel_3_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_374__AcpLevel_3_padding_2_MASK 0xff
+#define DPM_TABLE_374__AcpLevel_3_padding_2__SHIFT 0x0
+#define DPM_TABLE_374__AcpLevel_3_padding_1_MASK 0xff00
+#define DPM_TABLE_374__AcpLevel_3_padding_1__SHIFT 0x8
+#define DPM_TABLE_374__AcpLevel_3_padding_0_MASK 0xff0000
+#define DPM_TABLE_374__AcpLevel_3_padding_0__SHIFT 0x10
+#define DPM_TABLE_374__AcpLevel_3_Divider_MASK 0xff000000
+#define DPM_TABLE_374__AcpLevel_3_Divider__SHIFT 0x18
+#define DPM_TABLE_375__AcpLevel_4_Frequency_MASK 0xffffffff
+#define DPM_TABLE_375__AcpLevel_4_Frequency__SHIFT 0x0
+#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_376__AcpLevel_4_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_376__AcpLevel_4_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_376__AcpLevel_4_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_377__AcpLevel_4_padding_2_MASK 0xff
+#define DPM_TABLE_377__AcpLevel_4_padding_2__SHIFT 0x0
+#define DPM_TABLE_377__AcpLevel_4_padding_1_MASK 0xff00
+#define DPM_TABLE_377__AcpLevel_4_padding_1__SHIFT 0x8
+#define DPM_TABLE_377__AcpLevel_4_padding_0_MASK 0xff0000
+#define DPM_TABLE_377__AcpLevel_4_padding_0__SHIFT 0x10
+#define DPM_TABLE_377__AcpLevel_4_Divider_MASK 0xff000000
+#define DPM_TABLE_377__AcpLevel_4_Divider__SHIFT 0x18
+#define DPM_TABLE_378__AcpLevel_5_Frequency_MASK 0xffffffff
+#define DPM_TABLE_378__AcpLevel_5_Frequency__SHIFT 0x0
+#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_379__AcpLevel_5_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_379__AcpLevel_5_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_379__AcpLevel_5_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_380__AcpLevel_5_padding_2_MASK 0xff
+#define DPM_TABLE_380__AcpLevel_5_padding_2__SHIFT 0x0
+#define DPM_TABLE_380__AcpLevel_5_padding_1_MASK 0xff00
+#define DPM_TABLE_380__AcpLevel_5_padding_1__SHIFT 0x8
+#define DPM_TABLE_380__AcpLevel_5_padding_0_MASK 0xff0000
+#define DPM_TABLE_380__AcpLevel_5_padding_0__SHIFT 0x10
+#define DPM_TABLE_380__AcpLevel_5_Divider_MASK 0xff000000
+#define DPM_TABLE_380__AcpLevel_5_Divider__SHIFT 0x18
+#define DPM_TABLE_381__AcpLevel_6_Frequency_MASK 0xffffffff
+#define DPM_TABLE_381__AcpLevel_6_Frequency__SHIFT 0x0
+#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_382__AcpLevel_6_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_382__AcpLevel_6_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_382__AcpLevel_6_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_383__AcpLevel_6_padding_2_MASK 0xff
+#define DPM_TABLE_383__AcpLevel_6_padding_2__SHIFT 0x0
+#define DPM_TABLE_383__AcpLevel_6_padding_1_MASK 0xff00
+#define DPM_TABLE_383__AcpLevel_6_padding_1__SHIFT 0x8
+#define DPM_TABLE_383__AcpLevel_6_padding_0_MASK 0xff0000
+#define DPM_TABLE_383__AcpLevel_6_padding_0__SHIFT 0x10
+#define DPM_TABLE_383__AcpLevel_6_Divider_MASK 0xff000000
+#define DPM_TABLE_383__AcpLevel_6_Divider__SHIFT 0x18
+#define DPM_TABLE_384__AcpLevel_7_Frequency_MASK 0xffffffff
+#define DPM_TABLE_384__AcpLevel_7_Frequency__SHIFT 0x0
+#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_385__AcpLevel_7_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_385__AcpLevel_7_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_385__AcpLevel_7_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_386__AcpLevel_7_padding_2_MASK 0xff
+#define DPM_TABLE_386__AcpLevel_7_padding_2__SHIFT 0x0
+#define DPM_TABLE_386__AcpLevel_7_padding_1_MASK 0xff00
+#define DPM_TABLE_386__AcpLevel_7_padding_1__SHIFT 0x8
+#define DPM_TABLE_386__AcpLevel_7_padding_0_MASK 0xff0000
+#define DPM_TABLE_386__AcpLevel_7_padding_0__SHIFT 0x10
+#define DPM_TABLE_386__AcpLevel_7_Divider_MASK 0xff000000
+#define DPM_TABLE_386__AcpLevel_7_Divider__SHIFT 0x18
+#define DPM_TABLE_387__SamuLevel_0_Frequency_MASK 0xffffffff
+#define DPM_TABLE_387__SamuLevel_0_Frequency__SHIFT 0x0
+#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_388__SamuLevel_0_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_388__SamuLevel_0_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_388__SamuLevel_0_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_389__SamuLevel_0_padding_2_MASK 0xff
+#define DPM_TABLE_389__SamuLevel_0_padding_2__SHIFT 0x0
+#define DPM_TABLE_389__SamuLevel_0_padding_1_MASK 0xff00
+#define DPM_TABLE_389__SamuLevel_0_padding_1__SHIFT 0x8
+#define DPM_TABLE_389__SamuLevel_0_padding_0_MASK 0xff0000
+#define DPM_TABLE_389__SamuLevel_0_padding_0__SHIFT 0x10
+#define DPM_TABLE_389__SamuLevel_0_Divider_MASK 0xff000000
+#define DPM_TABLE_389__SamuLevel_0_Divider__SHIFT 0x18
+#define DPM_TABLE_390__SamuLevel_1_Frequency_MASK 0xffffffff
+#define DPM_TABLE_390__SamuLevel_1_Frequency__SHIFT 0x0
+#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_391__SamuLevel_1_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_391__SamuLevel_1_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_391__SamuLevel_1_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_392__SamuLevel_1_padding_2_MASK 0xff
+#define DPM_TABLE_392__SamuLevel_1_padding_2__SHIFT 0x0
+#define DPM_TABLE_392__SamuLevel_1_padding_1_MASK 0xff00
+#define DPM_TABLE_392__SamuLevel_1_padding_1__SHIFT 0x8
+#define DPM_TABLE_392__SamuLevel_1_padding_0_MASK 0xff0000
+#define DPM_TABLE_392__SamuLevel_1_padding_0__SHIFT 0x10
+#define DPM_TABLE_392__SamuLevel_1_Divider_MASK 0xff000000
+#define DPM_TABLE_392__SamuLevel_1_Divider__SHIFT 0x18
+#define DPM_TABLE_393__SamuLevel_2_Frequency_MASK 0xffffffff
+#define DPM_TABLE_393__SamuLevel_2_Frequency__SHIFT 0x0
+#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_394__SamuLevel_2_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_394__SamuLevel_2_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_394__SamuLevel_2_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_395__SamuLevel_2_padding_2_MASK 0xff
+#define DPM_TABLE_395__SamuLevel_2_padding_2__SHIFT 0x0
+#define DPM_TABLE_395__SamuLevel_2_padding_1_MASK 0xff00
+#define DPM_TABLE_395__SamuLevel_2_padding_1__SHIFT 0x8
+#define DPM_TABLE_395__SamuLevel_2_padding_0_MASK 0xff0000
+#define DPM_TABLE_395__SamuLevel_2_padding_0__SHIFT 0x10
+#define DPM_TABLE_395__SamuLevel_2_Divider_MASK 0xff000000
+#define DPM_TABLE_395__SamuLevel_2_Divider__SHIFT 0x18
+#define DPM_TABLE_396__SamuLevel_3_Frequency_MASK 0xffffffff
+#define DPM_TABLE_396__SamuLevel_3_Frequency__SHIFT 0x0
+#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_397__SamuLevel_3_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_397__SamuLevel_3_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_397__SamuLevel_3_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_398__SamuLevel_3_padding_2_MASK 0xff
+#define DPM_TABLE_398__SamuLevel_3_padding_2__SHIFT 0x0
+#define DPM_TABLE_398__SamuLevel_3_padding_1_MASK 0xff00
+#define DPM_TABLE_398__SamuLevel_3_padding_1__SHIFT 0x8
+#define DPM_TABLE_398__SamuLevel_3_padding_0_MASK 0xff0000
+#define DPM_TABLE_398__SamuLevel_3_padding_0__SHIFT 0x10
+#define DPM_TABLE_398__SamuLevel_3_Divider_MASK 0xff000000
+#define DPM_TABLE_398__SamuLevel_3_Divider__SHIFT 0x18
+#define DPM_TABLE_399__SamuLevel_4_Frequency_MASK 0xffffffff
+#define DPM_TABLE_399__SamuLevel_4_Frequency__SHIFT 0x0
+#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_400__SamuLevel_4_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_400__SamuLevel_4_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_400__SamuLevel_4_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_401__SamuLevel_4_padding_2_MASK 0xff
+#define DPM_TABLE_401__SamuLevel_4_padding_2__SHIFT 0x0
+#define DPM_TABLE_401__SamuLevel_4_padding_1_MASK 0xff00
+#define DPM_TABLE_401__SamuLevel_4_padding_1__SHIFT 0x8
+#define DPM_TABLE_401__SamuLevel_4_padding_0_MASK 0xff0000
+#define DPM_TABLE_401__SamuLevel_4_padding_0__SHIFT 0x10
+#define DPM_TABLE_401__SamuLevel_4_Divider_MASK 0xff000000
+#define DPM_TABLE_401__SamuLevel_4_Divider__SHIFT 0x18
+#define DPM_TABLE_402__SamuLevel_5_Frequency_MASK 0xffffffff
+#define DPM_TABLE_402__SamuLevel_5_Frequency__SHIFT 0x0
+#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_403__SamuLevel_5_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_403__SamuLevel_5_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_403__SamuLevel_5_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_404__SamuLevel_5_padding_2_MASK 0xff
+#define DPM_TABLE_404__SamuLevel_5_padding_2__SHIFT 0x0
+#define DPM_TABLE_404__SamuLevel_5_padding_1_MASK 0xff00
+#define DPM_TABLE_404__SamuLevel_5_padding_1__SHIFT 0x8
+#define DPM_TABLE_404__SamuLevel_5_padding_0_MASK 0xff0000
+#define DPM_TABLE_404__SamuLevel_5_padding_0__SHIFT 0x10
+#define DPM_TABLE_404__SamuLevel_5_Divider_MASK 0xff000000
+#define DPM_TABLE_404__SamuLevel_5_Divider__SHIFT 0x18
+#define DPM_TABLE_405__SamuLevel_6_Frequency_MASK 0xffffffff
+#define DPM_TABLE_405__SamuLevel_6_Frequency__SHIFT 0x0
+#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_406__SamuLevel_6_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_406__SamuLevel_6_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_406__SamuLevel_6_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_407__SamuLevel_6_padding_2_MASK 0xff
+#define DPM_TABLE_407__SamuLevel_6_padding_2__SHIFT 0x0
+#define DPM_TABLE_407__SamuLevel_6_padding_1_MASK 0xff00
+#define DPM_TABLE_407__SamuLevel_6_padding_1__SHIFT 0x8
+#define DPM_TABLE_407__SamuLevel_6_padding_0_MASK 0xff0000
+#define DPM_TABLE_407__SamuLevel_6_padding_0__SHIFT 0x10
+#define DPM_TABLE_407__SamuLevel_6_Divider_MASK 0xff000000
+#define DPM_TABLE_407__SamuLevel_6_Divider__SHIFT 0x18
+#define DPM_TABLE_408__SamuLevel_7_Frequency_MASK 0xffffffff
+#define DPM_TABLE_408__SamuLevel_7_Frequency__SHIFT 0x0
+#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Phases_MASK 0xff
+#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_409__SamuLevel_7_MinVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_409__SamuLevel_7_MinVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_409__SamuLevel_7_MinVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_410__SamuLevel_7_padding_2_MASK 0xff
+#define DPM_TABLE_410__SamuLevel_7_padding_2__SHIFT 0x0
+#define DPM_TABLE_410__SamuLevel_7_padding_1_MASK 0xff00
+#define DPM_TABLE_410__SamuLevel_7_padding_1__SHIFT 0x8
+#define DPM_TABLE_410__SamuLevel_7_padding_0_MASK 0xff0000
+#define DPM_TABLE_410__SamuLevel_7_padding_0__SHIFT 0x10
+#define DPM_TABLE_410__SamuLevel_7_Divider_MASK 0xff000000
+#define DPM_TABLE_410__SamuLevel_7_Divider__SHIFT 0x18
+#define DPM_TABLE_411__Ulv_CcPwrDynRm_MASK 0xffffffff
+#define DPM_TABLE_411__Ulv_CcPwrDynRm__SHIFT 0x0
+#define DPM_TABLE_412__Ulv_CcPwrDynRm1_MASK 0xffffffff
+#define DPM_TABLE_412__Ulv_CcPwrDynRm1__SHIFT 0x0
+#define DPM_TABLE_413__Ulv_VddcPhase_MASK 0xff
+#define DPM_TABLE_413__Ulv_VddcPhase__SHIFT 0x0
+#define DPM_TABLE_413__Ulv_VddcOffsetVid_MASK 0xff00
+#define DPM_TABLE_413__Ulv_VddcOffsetVid__SHIFT 0x8
+#define DPM_TABLE_413__Ulv_VddcOffset_MASK 0xffff0000
+#define DPM_TABLE_413__Ulv_VddcOffset__SHIFT 0x10
+#define DPM_TABLE_414__Ulv_Reserved_MASK 0xffffffff
+#define DPM_TABLE_414__Ulv_Reserved__SHIFT 0x0
+#define DPM_TABLE_415__SclkStepSize_MASK 0xffffffff
+#define DPM_TABLE_415__SclkStepSize__SHIFT 0x0
+#define DPM_TABLE_416__Smio_0_MASK 0xffffffff
+#define DPM_TABLE_416__Smio_0__SHIFT 0x0
+#define DPM_TABLE_417__Smio_1_MASK 0xffffffff
+#define DPM_TABLE_417__Smio_1__SHIFT 0x0
+#define DPM_TABLE_418__Smio_2_MASK 0xffffffff
+#define DPM_TABLE_418__Smio_2__SHIFT 0x0
+#define DPM_TABLE_419__Smio_3_MASK 0xffffffff
+#define DPM_TABLE_419__Smio_3__SHIFT 0x0
+#define DPM_TABLE_420__Smio_4_MASK 0xffffffff
+#define DPM_TABLE_420__Smio_4__SHIFT 0x0
+#define DPM_TABLE_421__Smio_5_MASK 0xffffffff
+#define DPM_TABLE_421__Smio_5__SHIFT 0x0
+#define DPM_TABLE_422__Smio_6_MASK 0xffffffff
+#define DPM_TABLE_422__Smio_6__SHIFT 0x0
+#define DPM_TABLE_423__Smio_7_MASK 0xffffffff
+#define DPM_TABLE_423__Smio_7__SHIFT 0x0
+#define DPM_TABLE_424__Smio_8_MASK 0xffffffff
+#define DPM_TABLE_424__Smio_8__SHIFT 0x0
+#define DPM_TABLE_425__Smio_9_MASK 0xffffffff
+#define DPM_TABLE_425__Smio_9__SHIFT 0x0
+#define DPM_TABLE_426__Smio_10_MASK 0xffffffff
+#define DPM_TABLE_426__Smio_10__SHIFT 0x0
+#define DPM_TABLE_427__Smio_11_MASK 0xffffffff
+#define DPM_TABLE_427__Smio_11__SHIFT 0x0
+#define DPM_TABLE_428__Smio_12_MASK 0xffffffff
+#define DPM_TABLE_428__Smio_12__SHIFT 0x0
+#define DPM_TABLE_429__Smio_13_MASK 0xffffffff
+#define DPM_TABLE_429__Smio_13__SHIFT 0x0
+#define DPM_TABLE_430__Smio_14_MASK 0xffffffff
+#define DPM_TABLE_430__Smio_14__SHIFT 0x0
+#define DPM_TABLE_431__Smio_15_MASK 0xffffffff
+#define DPM_TABLE_431__Smio_15__SHIFT 0x0
+#define DPM_TABLE_432__Smio_16_MASK 0xffffffff
+#define DPM_TABLE_432__Smio_16__SHIFT 0x0
+#define DPM_TABLE_433__Smio_17_MASK 0xffffffff
+#define DPM_TABLE_433__Smio_17__SHIFT 0x0
+#define DPM_TABLE_434__Smio_18_MASK 0xffffffff
+#define DPM_TABLE_434__Smio_18__SHIFT 0x0
+#define DPM_TABLE_435__Smio_19_MASK 0xffffffff
+#define DPM_TABLE_435__Smio_19__SHIFT 0x0
+#define DPM_TABLE_436__Smio_20_MASK 0xffffffff
+#define DPM_TABLE_436__Smio_20__SHIFT 0x0
+#define DPM_TABLE_437__Smio_21_MASK 0xffffffff
+#define DPM_TABLE_437__Smio_21__SHIFT 0x0
+#define DPM_TABLE_438__Smio_22_MASK 0xffffffff
+#define DPM_TABLE_438__Smio_22__SHIFT 0x0
+#define DPM_TABLE_439__Smio_23_MASK 0xffffffff
+#define DPM_TABLE_439__Smio_23__SHIFT 0x0
+#define DPM_TABLE_440__Smio_24_MASK 0xffffffff
+#define DPM_TABLE_440__Smio_24__SHIFT 0x0
+#define DPM_TABLE_441__Smio_25_MASK 0xffffffff
+#define DPM_TABLE_441__Smio_25__SHIFT 0x0
+#define DPM_TABLE_442__Smio_26_MASK 0xffffffff
+#define DPM_TABLE_442__Smio_26__SHIFT 0x0
+#define DPM_TABLE_443__Smio_27_MASK 0xffffffff
+#define DPM_TABLE_443__Smio_27__SHIFT 0x0
+#define DPM_TABLE_444__Smio_28_MASK 0xffffffff
+#define DPM_TABLE_444__Smio_28__SHIFT 0x0
+#define DPM_TABLE_445__Smio_29_MASK 0xffffffff
+#define DPM_TABLE_445__Smio_29__SHIFT 0x0
+#define DPM_TABLE_446__Smio_30_MASK 0xffffffff
+#define DPM_TABLE_446__Smio_30__SHIFT 0x0
+#define DPM_TABLE_447__Smio_31_MASK 0xffffffff
+#define DPM_TABLE_447__Smio_31__SHIFT 0x0
+#define DPM_TABLE_448__SamuBootLevel_MASK 0xff
+#define DPM_TABLE_448__SamuBootLevel__SHIFT 0x0
+#define DPM_TABLE_448__AcpBootLevel_MASK 0xff00
+#define DPM_TABLE_448__AcpBootLevel__SHIFT 0x8
+#define DPM_TABLE_448__VceBootLevel_MASK 0xff0000
+#define DPM_TABLE_448__VceBootLevel__SHIFT 0x10
+#define DPM_TABLE_448__UvdBootLevel_MASK 0xff000000
+#define DPM_TABLE_448__UvdBootLevel__SHIFT 0x18
+#define DPM_TABLE_449__GraphicsInterval_MASK 0xff
+#define DPM_TABLE_449__GraphicsInterval__SHIFT 0x0
+#define DPM_TABLE_449__GraphicsThermThrottleEnable_MASK 0xff00
+#define DPM_TABLE_449__GraphicsThermThrottleEnable__SHIFT 0x8
+#define DPM_TABLE_449__GraphicsVoltageChangeEnable_MASK 0xff0000
+#define DPM_TABLE_449__GraphicsVoltageChangeEnable__SHIFT 0x10
+#define DPM_TABLE_449__GraphicsBootLevel_MASK 0xff000000
+#define DPM_TABLE_449__GraphicsBootLevel__SHIFT 0x18
+#define DPM_TABLE_450__TemperatureLimitHigh_MASK 0xffff
+#define DPM_TABLE_450__TemperatureLimitHigh__SHIFT 0x0
+#define DPM_TABLE_450__ThermalInterval_MASK 0xff0000
+#define DPM_TABLE_450__ThermalInterval__SHIFT 0x10
+#define DPM_TABLE_450__VoltageInterval_MASK 0xff000000
+#define DPM_TABLE_450__VoltageInterval__SHIFT 0x18
+#define DPM_TABLE_451__MemoryVoltageChangeEnable_MASK 0xff
+#define DPM_TABLE_451__MemoryVoltageChangeEnable__SHIFT 0x0
+#define DPM_TABLE_451__MemoryBootLevel_MASK 0xff00
+#define DPM_TABLE_451__MemoryBootLevel__SHIFT 0x8
+#define DPM_TABLE_451__TemperatureLimitLow_MASK 0xffff0000
+#define DPM_TABLE_451__TemperatureLimitLow__SHIFT 0x10
+#define DPM_TABLE_452__MemoryThermThrottleEnable_MASK 0xff
+#define DPM_TABLE_452__MemoryThermThrottleEnable__SHIFT 0x0
+#define DPM_TABLE_452__MemoryInterval_MASK 0xff00
+#define DPM_TABLE_452__MemoryInterval__SHIFT 0x8
+#define DPM_TABLE_452__BootMVdd_MASK 0xffff0000
+#define DPM_TABLE_452__BootMVdd__SHIFT 0x10
+#define DPM_TABLE_453__PhaseResponseTime_MASK 0xffff
+#define DPM_TABLE_453__PhaseResponseTime__SHIFT 0x0
+#define DPM_TABLE_453__VoltageResponseTime_MASK 0xffff0000
+#define DPM_TABLE_453__VoltageResponseTime__SHIFT 0x10
+#define DPM_TABLE_454__DTEMode_MASK 0xff
+#define DPM_TABLE_454__DTEMode__SHIFT 0x0
+#define DPM_TABLE_454__DTEInterval_MASK 0xff00
+#define DPM_TABLE_454__DTEInterval__SHIFT 0x8
+#define DPM_TABLE_454__PCIeGenInterval_MASK 0xff0000
+#define DPM_TABLE_454__PCIeGenInterval__SHIFT 0x10
+#define DPM_TABLE_454__PCIeBootLinkLevel_MASK 0xff000000
+#define DPM_TABLE_454__PCIeBootLinkLevel__SHIFT 0x18
+#define DPM_TABLE_455__ThermGpio_MASK 0xff
+#define DPM_TABLE_455__ThermGpio__SHIFT 0x0
+#define DPM_TABLE_455__AcDcGpio_MASK 0xff00
+#define DPM_TABLE_455__AcDcGpio__SHIFT 0x8
+#define DPM_TABLE_455__VRHotGpio_MASK 0xff0000
+#define DPM_TABLE_455__VRHotGpio__SHIFT 0x10
+#define DPM_TABLE_455__SVI2Enable_MASK 0xff000000
+#define DPM_TABLE_455__SVI2Enable__SHIFT 0x18
+#define DPM_TABLE_456__PPM_TemperatureLimit_MASK 0xffff
+#define DPM_TABLE_456__PPM_TemperatureLimit__SHIFT 0x0
+#define DPM_TABLE_456__PPM_PkgPwrLimit_MASK 0xffff0000
+#define DPM_TABLE_456__PPM_PkgPwrLimit__SHIFT 0x10
+#define DPM_TABLE_457__TargetTdp_MASK 0xffff
+#define DPM_TABLE_457__TargetTdp__SHIFT 0x0
+#define DPM_TABLE_457__DefaultTdp_MASK 0xffff0000
+#define DPM_TABLE_457__DefaultTdp__SHIFT 0x10
+#define DPM_TABLE_458__FpsLowThreshold_MASK 0xffff
+#define DPM_TABLE_458__FpsLowThreshold__SHIFT 0x0
+#define DPM_TABLE_458__FpsHighThreshold_MASK 0xffff0000
+#define DPM_TABLE_458__FpsHighThreshold__SHIFT 0x10
+#define DPM_TABLE_459__BAPMTI_R_0_1_0_MASK 0xffff
+#define DPM_TABLE_459__BAPMTI_R_0_1_0__SHIFT 0x0
+#define DPM_TABLE_459__BAPMTI_R_0_0_0_MASK 0xffff0000
+#define DPM_TABLE_459__BAPMTI_R_0_0_0__SHIFT 0x10
+#define DPM_TABLE_460__BAPMTI_R_1_0_0_MASK 0xffff
+#define DPM_TABLE_460__BAPMTI_R_1_0_0__SHIFT 0x0
+#define DPM_TABLE_460__BAPMTI_R_0_2_0_MASK 0xffff0000
+#define DPM_TABLE_460__BAPMTI_R_0_2_0__SHIFT 0x10
+#define DPM_TABLE_461__BAPMTI_R_1_2_0_MASK 0xffff
+#define DPM_TABLE_461__BAPMTI_R_1_2_0__SHIFT 0x0
+#define DPM_TABLE_461__BAPMTI_R_1_1_0_MASK 0xffff0000
+#define DPM_TABLE_461__BAPMTI_R_1_1_0__SHIFT 0x10
+#define DPM_TABLE_462__BAPMTI_R_2_1_0_MASK 0xffff
+#define DPM_TABLE_462__BAPMTI_R_2_1_0__SHIFT 0x0
+#define DPM_TABLE_462__BAPMTI_R_2_0_0_MASK 0xffff0000
+#define DPM_TABLE_462__BAPMTI_R_2_0_0__SHIFT 0x10
+#define DPM_TABLE_463__BAPMTI_R_3_0_0_MASK 0xffff
+#define DPM_TABLE_463__BAPMTI_R_3_0_0__SHIFT 0x0
+#define DPM_TABLE_463__BAPMTI_R_2_2_0_MASK 0xffff0000
+#define DPM_TABLE_463__BAPMTI_R_2_2_0__SHIFT 0x10
+#define DPM_TABLE_464__BAPMTI_R_3_2_0_MASK 0xffff
+#define DPM_TABLE_464__BAPMTI_R_3_2_0__SHIFT 0x0
+#define DPM_TABLE_464__BAPMTI_R_3_1_0_MASK 0xffff0000
+#define DPM_TABLE_464__BAPMTI_R_3_1_0__SHIFT 0x10
+#define DPM_TABLE_465__BAPMTI_R_4_1_0_MASK 0xffff
+#define DPM_TABLE_465__BAPMTI_R_4_1_0__SHIFT 0x0
+#define DPM_TABLE_465__BAPMTI_R_4_0_0_MASK 0xffff0000
+#define DPM_TABLE_465__BAPMTI_R_4_0_0__SHIFT 0x10
+#define DPM_TABLE_466__BAPMTI_RC_0_0_0_MASK 0xffff
+#define DPM_TABLE_466__BAPMTI_RC_0_0_0__SHIFT 0x0
+#define DPM_TABLE_466__BAPMTI_R_4_2_0_MASK 0xffff0000
+#define DPM_TABLE_466__BAPMTI_R_4_2_0__SHIFT 0x10
+#define DPM_TABLE_467__BAPMTI_RC_0_2_0_MASK 0xffff
+#define DPM_TABLE_467__BAPMTI_RC_0_2_0__SHIFT 0x0
+#define DPM_TABLE_467__BAPMTI_RC_0_1_0_MASK 0xffff0000
+#define DPM_TABLE_467__BAPMTI_RC_0_1_0__SHIFT 0x10
+#define DPM_TABLE_468__BAPMTI_RC_1_1_0_MASK 0xffff
+#define DPM_TABLE_468__BAPMTI_RC_1_1_0__SHIFT 0x0
+#define DPM_TABLE_468__BAPMTI_RC_1_0_0_MASK 0xffff0000
+#define DPM_TABLE_468__BAPMTI_RC_1_0_0__SHIFT 0x10
+#define DPM_TABLE_469__BAPMTI_RC_2_0_0_MASK 0xffff
+#define DPM_TABLE_469__BAPMTI_RC_2_0_0__SHIFT 0x0
+#define DPM_TABLE_469__BAPMTI_RC_1_2_0_MASK 0xffff0000
+#define DPM_TABLE_469__BAPMTI_RC_1_2_0__SHIFT 0x10
+#define DPM_TABLE_470__BAPMTI_RC_2_2_0_MASK 0xffff
+#define DPM_TABLE_470__BAPMTI_RC_2_2_0__SHIFT 0x0
+#define DPM_TABLE_470__BAPMTI_RC_2_1_0_MASK 0xffff0000
+#define DPM_TABLE_470__BAPMTI_RC_2_1_0__SHIFT 0x10
+#define DPM_TABLE_471__BAPMTI_RC_3_1_0_MASK 0xffff
+#define DPM_TABLE_471__BAPMTI_RC_3_1_0__SHIFT 0x0
+#define DPM_TABLE_471__BAPMTI_RC_3_0_0_MASK 0xffff0000
+#define DPM_TABLE_471__BAPMTI_RC_3_0_0__SHIFT 0x10
+#define DPM_TABLE_472__BAPMTI_RC_4_0_0_MASK 0xffff
+#define DPM_TABLE_472__BAPMTI_RC_4_0_0__SHIFT 0x0
+#define DPM_TABLE_472__BAPMTI_RC_3_2_0_MASK 0xffff0000
+#define DPM_TABLE_472__BAPMTI_RC_3_2_0__SHIFT 0x10
+#define DPM_TABLE_473__BAPMTI_RC_4_2_0_MASK 0xffff
+#define DPM_TABLE_473__BAPMTI_RC_4_2_0__SHIFT 0x0
+#define DPM_TABLE_473__BAPMTI_RC_4_1_0_MASK 0xffff0000
+#define DPM_TABLE_473__BAPMTI_RC_4_1_0__SHIFT 0x10
+#define DPM_TABLE_474__GpuTjHyst_MASK 0xff
+#define DPM_TABLE_474__GpuTjHyst__SHIFT 0x0
+#define DPM_TABLE_474__GpuTjMax_MASK 0xff00
+#define DPM_TABLE_474__GpuTjMax__SHIFT 0x8
+#define DPM_TABLE_474__DTETjOffset_MASK 0xff0000
+#define DPM_TABLE_474__DTETjOffset__SHIFT 0x10
+#define DPM_TABLE_474__DTEAmbientTempBase_MASK 0xff000000
+#define DPM_TABLE_474__DTEAmbientTempBase__SHIFT 0x18
+#define DPM_TABLE_475__BootVoltage_Phases_MASK 0xff
+#define DPM_TABLE_475__BootVoltage_Phases__SHIFT 0x0
+#define DPM_TABLE_475__BootVoltage_VddGfx_MASK 0xff00
+#define DPM_TABLE_475__BootVoltage_VddGfx__SHIFT 0x8
+#define DPM_TABLE_475__BootVoltage_Vddci_MASK 0xff0000
+#define DPM_TABLE_475__BootVoltage_Vddci__SHIFT 0x10
+#define DPM_TABLE_475__BootVoltage_Vddc_MASK 0xff000000
+#define DPM_TABLE_475__BootVoltage_Vddc__SHIFT 0x18
+#define DPM_TABLE_476__BAPM_TEMP_GRADIENT_MASK 0xffffffff
+#define DPM_TABLE_476__BAPM_TEMP_GRADIENT__SHIFT 0x0
+#define DPM_TABLE_477__LowSclkInterruptThreshold_MASK 0xffffffff
+#define DPM_TABLE_477__LowSclkInterruptThreshold__SHIFT 0x0
+#define DPM_TABLE_478__VddGfxReChkWait_MASK 0xffffffff
+#define DPM_TABLE_478__VddGfxReChkWait__SHIFT 0x0
+#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1_MASK 0xff
+#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1__SHIFT 0x0
+#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0_MASK 0xff00
+#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0__SHIFT 0x8
+#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID_MASK 0xff0000
+#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID__SHIFT 0x10
+#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID_MASK 0xff000000
+#define DPM_TABLE_479__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID__SHIFT 0x18
+#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3_MASK 0xff
+#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3__SHIFT 0x0
+#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2_MASK 0xff00
+#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2__SHIFT 0x8
+#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1_MASK 0xff0000
+#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1__SHIFT 0x10
+#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0_MASK 0xff000000
+#define DPM_TABLE_480__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0__SHIFT 0x18
+#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7_MASK 0xff
+#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7__SHIFT 0x0
+#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6_MASK 0xff00
+#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6__SHIFT 0x8
+#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5_MASK 0xff0000
+#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5__SHIFT 0x10
+#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4_MASK 0xff000000
+#define DPM_TABLE_481__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4__SHIFT 0x18
+#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1_MASK 0xff
+#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1__SHIFT 0x0
+#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0_MASK 0xff00
+#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0__SHIFT 0x8
+#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID_MASK 0xff0000
+#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID__SHIFT 0x10
+#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID_MASK 0xff000000
+#define DPM_TABLE_482__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID__SHIFT 0x18
+#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3_MASK 0xff
+#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3__SHIFT 0x0
+#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2_MASK 0xff00
+#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2__SHIFT 0x8
+#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1_MASK 0xff0000
+#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1__SHIFT 0x10
+#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0_MASK 0xff000000
+#define DPM_TABLE_483__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0__SHIFT 0x18
+#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7_MASK 0xff
+#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7__SHIFT 0x0
+#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6_MASK 0xff00
+#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6__SHIFT 0x8
+#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5_MASK 0xff0000
+#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5__SHIFT 0x10
+#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4_MASK 0xff000000
+#define DPM_TABLE_484__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4__SHIFT 0x18
+#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1_MASK 0xff
+#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1__SHIFT 0x0
+#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0_MASK 0xff00
+#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0__SHIFT 0x8
+#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID_MASK 0xff0000
+#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID__SHIFT 0x10
+#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID_MASK 0xff000000
+#define DPM_TABLE_485__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID__SHIFT 0x18
+#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3_MASK 0xff
+#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3__SHIFT 0x0
+#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2_MASK 0xff00
+#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2__SHIFT 0x8
+#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1_MASK 0xff0000
+#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1__SHIFT 0x10
+#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0_MASK 0xff000000
+#define DPM_TABLE_486__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0__SHIFT 0x18
+#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7_MASK 0xff
+#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7__SHIFT 0x0
+#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6_MASK 0xff00
+#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6__SHIFT 0x8
+#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5_MASK 0xff0000
+#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5__SHIFT 0x10
+#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4_MASK 0xff000000
+#define DPM_TABLE_487__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4__SHIFT 0x18
+#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1_MASK 0xff
+#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1__SHIFT 0x0
+#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0_MASK 0xff00
+#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0__SHIFT 0x8
+#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID_MASK 0xff0000
+#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID__SHIFT 0x10
+#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID_MASK 0xff000000
+#define DPM_TABLE_488__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID__SHIFT 0x18
+#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3_MASK 0xff
+#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3__SHIFT 0x0
+#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2_MASK 0xff00
+#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2__SHIFT 0x8
+#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1_MASK 0xff0000
+#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1__SHIFT 0x10
+#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0_MASK 0xff000000
+#define DPM_TABLE_489__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0__SHIFT 0x18
+#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7_MASK 0xff
+#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7__SHIFT 0x0
+#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6_MASK 0xff00
+#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6__SHIFT 0x8
+#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5_MASK 0xff0000
+#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5__SHIFT 0x10
+#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4_MASK 0xff000000
+#define DPM_TABLE_490__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime__SHIFT 0x18
+#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2_MASK 0xffffffff
+#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2_MASK 0xff
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2__SHIFT 0x0
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1_MASK 0xff00
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1__SHIFT 0x8
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0_MASK 0xff0000
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0__SHIFT 0x10
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime_MASK 0xff000000
+#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime__SHIFT 0x18
+#define MC_REGISTERS_TABLE_1__reserved_2_MASK 0xff
+#define MC_REGISTERS_TABLE_1__reserved_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_1__reserved_1_MASK 0xff00
+#define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8
+#define MC_REGISTERS_TABLE_1__reserved_0_MASK 0xff0000
+#define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_1__last_MASK 0xff000000
+#define MC_REGISTERS_TABLE_1__last__SHIFT 0x18
+#define MC_REGISTERS_TABLE_2__address_0_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_2__address_0_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_2__address_0_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_3__address_1_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_3__address_1_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_3__address_1_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_4__address_2_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_4__address_2_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_4__address_2_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_4__address_2_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_5__address_3_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_5__address_3_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_5__address_3_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_6__address_4_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_6__address_4_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_6__address_4_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_7__address_5_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_7__address_5_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_7__address_5_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_8__address_6_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_8__address_6_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_8__address_6_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_8__address_6_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_9__address_7_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_9__address_7_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_9__address_7_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_10__address_8_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_10__address_8_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_10__address_8_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_11__address_9_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_11__address_9_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_11__address_9_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_12__address_10_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_12__address_10_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_12__address_10_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_12__address_10_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_13__address_11_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_13__address_11_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_13__address_11_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_13__address_11_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_14__address_12_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_14__address_12_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_14__address_12_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_15__address_13_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_15__address_13_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_15__address_13_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_15__address_13_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_16__address_14_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_16__address_14_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_16__address_14_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_17__address_15_s1_MASK 0xffff
+#define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_17__address_15_s0_MASK 0xffff0000
+#define MC_REGISTERS_TABLE_17__address_15_s0__SHIFT 0x10
+#define MC_REGISTERS_TABLE_18__data_0_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_18__data_0_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_19__data_0_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_20__data_0_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_20__data_0_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_21__data_0_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_22__data_0_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_22__data_0_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_23__data_0_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_23__data_0_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_24__data_0_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_24__data_0_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_25__data_0_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_25__data_0_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_26__data_0_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_26__data_0_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_27__data_0_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_27__data_0_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_28__data_0_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_29__data_0_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_29__data_0_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_30__data_0_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_30__data_0_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_31__data_0_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_31__data_0_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_32__data_0_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_33__data_0_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0
+#define MC_REGISTERS_TABLE_34__data_1_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_34__data_1_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_35__data_1_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_35__data_1_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_36__data_1_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_36__data_1_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_37__data_1_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_37__data_1_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_38__data_1_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_38__data_1_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_39__data_1_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_39__data_1_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_40__data_1_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_41__data_1_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_41__data_1_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_42__data_1_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_42__data_1_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_43__data_1_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_44__data_1_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_44__data_1_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_45__data_1_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_45__data_1_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_46__data_1_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_47__data_1_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_47__data_1_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_48__data_1_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_48__data_1_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_49__data_1_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_49__data_1_value_15__SHIFT 0x0
+#define MC_REGISTERS_TABLE_50__data_2_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_50__data_2_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_51__data_2_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_51__data_2_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_52__data_2_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_52__data_2_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_53__data_2_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_53__data_2_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_54__data_2_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_54__data_2_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_55__data_2_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_55__data_2_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_56__data_2_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_56__data_2_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_57__data_2_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_57__data_2_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_58__data_2_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_58__data_2_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_59__data_2_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_59__data_2_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_60__data_2_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_61__data_2_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_62__data_2_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_63__data_2_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_63__data_2_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_64__data_2_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_64__data_2_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_65__data_2_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_65__data_2_value_15__SHIFT 0x0
+#define MC_REGISTERS_TABLE_66__data_3_value_0_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0
+#define MC_REGISTERS_TABLE_67__data_3_value_1_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_67__data_3_value_1__SHIFT 0x0
+#define MC_REGISTERS_TABLE_68__data_3_value_2_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_68__data_3_value_2__SHIFT 0x0
+#define MC_REGISTERS_TABLE_69__data_3_value_3_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_69__data_3_value_3__SHIFT 0x0
+#define MC_REGISTERS_TABLE_70__data_3_value_4_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_70__data_3_value_4__SHIFT 0x0
+#define MC_REGISTERS_TABLE_71__data_3_value_5_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0
+#define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_72__data_3_value_6__SHIFT 0x0
+#define MC_REGISTERS_TABLE_73__data_3_value_7_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_73__data_3_value_7__SHIFT 0x0
+#define MC_REGISTERS_TABLE_74__data_3_value_8_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_74__data_3_value_8__SHIFT 0x0
+#define MC_REGISTERS_TABLE_75__data_3_value_9_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_75__data_3_value_9__SHIFT 0x0
+#define MC_REGISTERS_TABLE_76__data_3_value_10_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0
+#define MC_REGISTERS_TABLE_77__data_3_value_11_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_77__data_3_value_11__SHIFT 0x0
+#define MC_REGISTERS_TABLE_78__data_3_value_12_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_78__data_3_value_12__SHIFT 0x0
+#define MC_REGISTERS_TABLE_79__data_3_value_13_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_79__data_3_value_13__SHIFT 0x0
+#define MC_REGISTERS_TABLE_80__data_3_value_14_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_80__data_3_value_14__SHIFT 0x0
+#define MC_REGISTERS_TABLE_81__data_3_value_15_MASK 0xffffffff
+#define MC_REGISTERS_TABLE_81__data_3_value_15__SHIFT 0x0
+#define FAN_TABLE_1__TempMin_MASK 0xffff
+#define FAN_TABLE_1__TempMin__SHIFT 0x0
+#define FAN_TABLE_1__FdoMode_MASK 0xffff0000
+#define FAN_TABLE_1__FdoMode__SHIFT 0x10
+#define FAN_TABLE_2__TempMax_MASK 0xffff
+#define FAN_TABLE_2__TempMax__SHIFT 0x0
+#define FAN_TABLE_2__TempMed_MASK 0xffff0000
+#define FAN_TABLE_2__TempMed__SHIFT 0x10
+#define FAN_TABLE_3__Slope2_MASK 0xffff
+#define FAN_TABLE_3__Slope2__SHIFT 0x0
+#define FAN_TABLE_3__Slope1_MASK 0xffff0000
+#define FAN_TABLE_3__Slope1__SHIFT 0x10
+#define FAN_TABLE_4__HystUp_MASK 0xffff
+#define FAN_TABLE_4__HystUp__SHIFT 0x0
+#define FAN_TABLE_4__FdoMin_MASK 0xffff0000
+#define FAN_TABLE_4__FdoMin__SHIFT 0x10
+#define FAN_TABLE_5__HystSlope_MASK 0xffff
+#define FAN_TABLE_5__HystSlope__SHIFT 0x0
+#define FAN_TABLE_5__HystDown_MASK 0xffff0000
+#define FAN_TABLE_5__HystDown__SHIFT 0x10
+#define FAN_TABLE_6__TempCurr_MASK 0xffff
+#define FAN_TABLE_6__TempCurr__SHIFT 0x0
+#define FAN_TABLE_6__TempRespLim_MASK 0xffff0000
+#define FAN_TABLE_6__TempRespLim__SHIFT 0x10
+#define FAN_TABLE_7__PwmCurr_MASK 0xffff
+#define FAN_TABLE_7__PwmCurr__SHIFT 0x0
+#define FAN_TABLE_7__SlopeCurr_MASK 0xffff0000
+#define FAN_TABLE_7__SlopeCurr__SHIFT 0x10
+#define FAN_TABLE_8__RefreshPeriod_MASK 0xffffffff
+#define FAN_TABLE_8__RefreshPeriod__SHIFT 0x0
+#define FAN_TABLE_9__Padding_MASK 0xff
+#define FAN_TABLE_9__Padding__SHIFT 0x0
+#define FAN_TABLE_9__TempSrc_MASK 0xff00
+#define FAN_TABLE_9__TempSrc__SHIFT 0x8
+#define FAN_TABLE_9__FdoMax_MASK 0xffff0000
+#define FAN_TABLE_9__FdoMax__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_4__PreVBlankGap_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_4__PreVBlankGap__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_5__VBlankTimeout_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_5__VBlankTimeout__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_6__TrainTimeGap_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_6__TrainTimeGap__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_9__AcpiDelay_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_9__AcpiDelay__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_10__G5TrainTime_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_10__G5TrainTime__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_13__HandshakeDisables_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_13__HandshakeDisables__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config_MASK 0xff00
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config__SHIFT 0x8
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config_MASK 0xff0000
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config_MASK 0xff000000
+#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config__SHIFT 0x18
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config_MASK 0xff
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config__SHIFT 0x8
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config_MASK 0xff000000
+#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config__SHIFT 0x18
+#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_18__AverageGioActivity_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_18__AverageGioActivity__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels_MASK 0xff
+#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels_MASK 0xff00
+#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels__SHIFT 0x8
+#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels_MASK 0xff0000
+#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels_MASK 0xff000000
+#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels__SHIFT 0x18
+#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels_MASK 0xff
+#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels_MASK 0xff00
+#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels__SHIFT 0x8
+#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels_MASK 0xff0000
+#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels__SHIFT 0x10
+#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels_MASK 0xff000000
+#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels__SHIFT 0x18
+#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_26__UlvEnterCount_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_26__UlvEnterCount__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_27__UlvTime_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_27__UlvTime__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_28__UcodeLoadStatus_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_28__UcodeLoadStatus__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_29__Reserved_0_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_29__Reserved_0__SHIFT 0x0
+#define SOFT_REGISTERS_TABLE_30__Reserved_1_MASK 0xffffffff
+#define SOFT_REGISTERS_TABLE_30__Reserved_1__SHIFT 0x0
+#define PM_FUSES_1__SviLoadLineOffsetVddC_MASK 0xff
+#define PM_FUSES_1__SviLoadLineOffsetVddC__SHIFT 0x0
+#define PM_FUSES_1__SviLoadLineTrimVddC_MASK 0xff00
+#define PM_FUSES_1__SviLoadLineTrimVddC__SHIFT 0x8
+#define PM_FUSES_1__SviLoadLineVddC_MASK 0xff0000
+#define PM_FUSES_1__SviLoadLineVddC__SHIFT 0x10
+#define PM_FUSES_1__SviLoadLineEn_MASK 0xff000000
+#define PM_FUSES_1__SviLoadLineEn__SHIFT 0x18
+#define PM_FUSES_2__TDC_MAWt_MASK 0xff
+#define PM_FUSES_2__TDC_MAWt__SHIFT 0x0
+#define PM_FUSES_2__TDC_VDDC_ThrottleReleaseLimitPerc_MASK 0xff00
+#define PM_FUSES_2__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT 0x8
+#define PM_FUSES_2__TDC_VDDC_PkgLimit_MASK 0xffff0000
+#define PM_FUSES_2__TDC_VDDC_PkgLimit__SHIFT 0x10
+#define PM_FUSES_3__Reserved_MASK 0xff
+#define PM_FUSES_3__Reserved__SHIFT 0x0
+#define PM_FUSES_3__LPMLTemperatureMax_MASK 0xff00
+#define PM_FUSES_3__LPMLTemperatureMax__SHIFT 0x8
+#define PM_FUSES_3__LPMLTemperatureMin_MASK 0xff0000
+#define PM_FUSES_3__LPMLTemperatureMin__SHIFT 0x10
+#define PM_FUSES_3__TdcWaterfallCtl_MASK 0xff000000
+#define PM_FUSES_3__TdcWaterfallCtl__SHIFT 0x18
+#define PM_FUSES_4__LPMLTemperatureScaler_3_MASK 0xff
+#define PM_FUSES_4__LPMLTemperatureScaler_3__SHIFT 0x0
+#define PM_FUSES_4__LPMLTemperatureScaler_2_MASK 0xff00
+#define PM_FUSES_4__LPMLTemperatureScaler_2__SHIFT 0x8
+#define PM_FUSES_4__LPMLTemperatureScaler_1_MASK 0xff0000
+#define PM_FUSES_4__LPMLTemperatureScaler_1__SHIFT 0x10
+#define PM_FUSES_4__LPMLTemperatureScaler_0_MASK 0xff000000
+#define PM_FUSES_4__LPMLTemperatureScaler_0__SHIFT 0x18
+#define PM_FUSES_5__LPMLTemperatureScaler_7_MASK 0xff
+#define PM_FUSES_5__LPMLTemperatureScaler_7__SHIFT 0x0
+#define PM_FUSES_5__LPMLTemperatureScaler_6_MASK 0xff00
+#define PM_FUSES_5__LPMLTemperatureScaler_6__SHIFT 0x8
+#define PM_FUSES_5__LPMLTemperatureScaler_5_MASK 0xff0000
+#define PM_FUSES_5__LPMLTemperatureScaler_5__SHIFT 0x10
+#define PM_FUSES_5__LPMLTemperatureScaler_4_MASK 0xff000000
+#define PM_FUSES_5__LPMLTemperatureScaler_4__SHIFT 0x18
+#define PM_FUSES_6__LPMLTemperatureScaler_11_MASK 0xff
+#define PM_FUSES_6__LPMLTemperatureScaler_11__SHIFT 0x0
+#define PM_FUSES_6__LPMLTemperatureScaler_10_MASK 0xff00
+#define PM_FUSES_6__LPMLTemperatureScaler_10__SHIFT 0x8
+#define PM_FUSES_6__LPMLTemperatureScaler_9_MASK 0xff0000
+#define PM_FUSES_6__LPMLTemperatureScaler_9__SHIFT 0x10
+#define PM_FUSES_6__LPMLTemperatureScaler_8_MASK 0xff000000
+#define PM_FUSES_6__LPMLTemperatureScaler_8__SHIFT 0x18
+#define PM_FUSES_7__LPMLTemperatureScaler_15_MASK 0xff
+#define PM_FUSES_7__LPMLTemperatureScaler_15__SHIFT 0x0
+#define PM_FUSES_7__LPMLTemperatureScaler_14_MASK 0xff00
+#define PM_FUSES_7__LPMLTemperatureScaler_14__SHIFT 0x8
+#define PM_FUSES_7__LPMLTemperatureScaler_13_MASK 0xff0000
+#define PM_FUSES_7__LPMLTemperatureScaler_13__SHIFT 0x10
+#define PM_FUSES_7__LPMLTemperatureScaler_12_MASK 0xff000000
+#define PM_FUSES_7__LPMLTemperatureScaler_12__SHIFT 0x18
+#define PM_FUSES_8__FuzzyFan_ErrorRateSetDelta_MASK 0xffff
+#define PM_FUSES_8__FuzzyFan_ErrorRateSetDelta__SHIFT 0x0
+#define PM_FUSES_8__FuzzyFan_ErrorSetDelta_MASK 0xffff0000
+#define PM_FUSES_8__FuzzyFan_ErrorSetDelta__SHIFT 0x10
+#define PM_FUSES_9__Reserved6_MASK 0xffff
+#define PM_FUSES_9__Reserved6__SHIFT 0x0
+#define PM_FUSES_9__FuzzyFan_PwmSetDelta_MASK 0xffff0000
+#define PM_FUSES_9__FuzzyFan_PwmSetDelta__SHIFT 0x10
+#define PM_FUSES_10__GnbLPML_3_MASK 0xff
+#define PM_FUSES_10__GnbLPML_3__SHIFT 0x0
+#define PM_FUSES_10__GnbLPML_2_MASK 0xff00
+#define PM_FUSES_10__GnbLPML_2__SHIFT 0x8
+#define PM_FUSES_10__GnbLPML_1_MASK 0xff0000
+#define PM_FUSES_10__GnbLPML_1__SHIFT 0x10
+#define PM_FUSES_10__GnbLPML_0_MASK 0xff000000
+#define PM_FUSES_10__GnbLPML_0__SHIFT 0x18
+#define PM_FUSES_11__GnbLPML_7_MASK 0xff
+#define PM_FUSES_11__GnbLPML_7__SHIFT 0x0
+#define PM_FUSES_11__GnbLPML_6_MASK 0xff00
+#define PM_FUSES_11__GnbLPML_6__SHIFT 0x8
+#define PM_FUSES_11__GnbLPML_5_MASK 0xff0000
+#define PM_FUSES_11__GnbLPML_5__SHIFT 0x10
+#define PM_FUSES_11__GnbLPML_4_MASK 0xff000000
+#define PM_FUSES_11__GnbLPML_4__SHIFT 0x18
+#define PM_FUSES_12__GnbLPML_11_MASK 0xff
+#define PM_FUSES_12__GnbLPML_11__SHIFT 0x0
+#define PM_FUSES_12__GnbLPML_10_MASK 0xff00
+#define PM_FUSES_12__GnbLPML_10__SHIFT 0x8
+#define PM_FUSES_12__GnbLPML_9_MASK 0xff0000
+#define PM_FUSES_12__GnbLPML_9__SHIFT 0x10
+#define PM_FUSES_12__GnbLPML_8_MASK 0xff000000
+#define PM_FUSES_12__GnbLPML_8__SHIFT 0x18
+#define PM_FUSES_13__GnbLPML_15_MASK 0xff
+#define PM_FUSES_13__GnbLPML_15__SHIFT 0x0
+#define PM_FUSES_13__GnbLPML_14_MASK 0xff00
+#define PM_FUSES_13__GnbLPML_14__SHIFT 0x8
+#define PM_FUSES_13__GnbLPML_13_MASK 0xff0000
+#define PM_FUSES_13__GnbLPML_13__SHIFT 0x10
+#define PM_FUSES_13__GnbLPML_12_MASK 0xff000000
+#define PM_FUSES_13__GnbLPML_12__SHIFT 0x18
+#define PM_FUSES_14__Reserved1_1_MASK 0xff
+#define PM_FUSES_14__Reserved1_1__SHIFT 0x0
+#define PM_FUSES_14__Reserved1_0_MASK 0xff00
+#define PM_FUSES_14__Reserved1_0__SHIFT 0x8
+#define PM_FUSES_14__GnbLPMLMinVid_MASK 0xff0000
+#define PM_FUSES_14__GnbLPMLMinVid__SHIFT 0x10
+#define PM_FUSES_14__GnbLPMLMaxVid_MASK 0xff000000
+#define PM_FUSES_14__GnbLPMLMaxVid__SHIFT 0x18
+#define PM_FUSES_15__BapmVddCBaseLeakageLoSidd_MASK 0xffff
+#define PM_FUSES_15__BapmVddCBaseLeakageLoSidd__SHIFT 0x0
+#define PM_FUSES_15__BapmVddCBaseLeakageHiSidd_MASK 0xffff0000
+#define PM_FUSES_15__BapmVddCBaseLeakageHiSidd__SHIFT 0x10
+#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_0__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_1__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_2__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_3__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_4__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_5__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_6__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_7__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_8__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_9__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_10__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_11__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_12__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_13__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_14__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_15__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_16__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_17__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_18__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_19__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_20__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_21__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_22__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_23__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_24__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_25__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_26__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_27__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_28__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_29__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_30__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_31__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_32__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_33__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_34__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_35__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_36__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_37__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_38__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_39__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_40__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_41__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_42__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_43__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_44__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_45__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_46__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_47__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_48__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_49__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_50__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_51__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_52__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_53__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_54__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_55__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_56__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_57__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_58__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_59__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_60__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_61__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_62__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_63__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_64__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_65__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_66__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_67__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_68__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_69__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_70__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_71__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_72__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_73__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_74__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_75__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_76__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_77__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_78__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_79__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_80__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_81__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_82__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_83__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_84__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_85__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_86__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_87__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_88__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_89__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_90__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_91__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_92__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_93__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_94__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_95__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_96__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_97__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_98__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_99__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_100__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_101__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_102__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_103__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_104__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_105__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_106__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_107__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_108__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_109__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_110__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_111__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_112__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_113__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_114__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_115__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_116__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_117__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_118__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_119__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_120__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_121__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_122__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_123__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_124__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_125__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_126__DATA__SHIFT 0x0
+#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff
+#define SMU_PM_STATUS_127__DATA__SHIFT 0x0
+#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1
+#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0
+#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2
+#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2
+#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8
+#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3
+#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10
+#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20
+#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00
+#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8
+#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000
+#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10
+#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000
+#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18
+#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000
+#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000
+#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b
+#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000
+#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c
+#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1
+#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0
+#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2
+#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8
+#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3
+#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x7
+#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x0
+#define CG_THERMAL_CTRL__THERM_INC_CLK_MASK 0x8
+#define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT 0x3
+#define CG_THERMAL_CTRL__SPARE_MASK 0x3ff0
+#define CG_THERMAL_CTRL__SPARE__SHIFT 0x4
+#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x3fc000
+#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0xe
+#define CG_THERMAL_CTRL__RESERVED_MASK 0x1c00000
+#define CG_THERMAL_CTRL__RESERVED__SHIFT 0x16
+#define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK 0x2000000
+#define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT 0x19
+#define CG_THERMAL_CTRL__CTF_PAD_EN_MASK 0x4000000
+#define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT 0x1a
+#define CG_THERMAL_STATUS__SPARE_MASK 0x1ff
+#define CG_THERMAL_STATUS__SPARE__SHIFT 0x0
+#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x1fe00
+#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9
+#define CG_THERMAL_STATUS__THERM_ALERT_MASK 0x20000
+#define CG_THERMAL_STATUS__THERM_ALERT__SHIFT 0x11
+#define CG_THERMAL_STATUS__GEN_STATUS_MASK 0x3c0000
+#define CG_THERMAL_STATUS__GEN_STATUS__SHIFT 0x12
+#define CG_THERMAL_INT__DIG_THERM_CTF_MASK 0xff
+#define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT 0x0
+#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0xff00
+#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x8
+#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0xff0000
+#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x10
+#define CG_THERMAL_INT__THERM_INT_MASK_MASK 0xf000000
+#define CG_THERMAL_INT__THERM_INT_MASK__SHIFT 0x18
+#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0xf
+#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0
+#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0x1f0
+#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4
+#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x200
+#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9
+#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000
+#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14
+#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR_MASK 0x10000000
+#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR__SHIFT 0x1c
+#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x1ff
+#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0
+#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x3fe00
+#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9
+#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0xff
+#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0
+#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0xff00
+#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8
+#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x10000
+#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10
+#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x7e0000
+#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x800000
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17
+#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xff000000
+#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18
+#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0xff
+#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0
+#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00
+#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8
+#define CG_FDO_CTRL1__M_MASK 0xff0000
+#define CG_FDO_CTRL1__M__SHIFT 0x10
+#define CG_FDO_CTRL1__RESERVED_MASK 0x3f000000
+#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18
+#define CG_FDO_CTRL1__FDO_PWRDNB_MASK 0x40000000
+#define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT 0x1e
+#define CG_FDO_CTRL2__TMIN_MASK 0xff
+#define CG_FDO_CTRL2__TMIN__SHIFT 0x0
+#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x700
+#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8
+#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x3800
+#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb
+#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x1c000
+#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe
+#define CG_FDO_CTRL2__TMAX_MASK 0x1fe0000
+#define CG_FDO_CTRL2__TMAX__SHIFT 0x11
+#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xfe000000
+#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19
+#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x7
+#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0
+#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8
+#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3
+#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff
+#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0
+#define CC_THM_STRAPS0__TMON0_BGADJ_MASK 0x1fe
+#define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT 0x1
+#define CC_THM_STRAPS0__TMON1_BGADJ_MASK 0x1fe00
+#define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT 0x9
+#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK 0x20000
+#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT 0x11
+#define CC_THM_STRAPS0__NUM_ACQ_MASK 0x1c0000
+#define CC_THM_STRAPS0__NUM_ACQ__SHIFT 0x12
+#define CC_THM_STRAPS0__TMON_CLK_SEL_MASK 0xe00000
+#define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT 0x15
+#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK 0x1000000
+#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT 0x18
+#define CC_THM_STRAPS0__CTF_DISABLE_MASK 0x2000000
+#define CC_THM_STRAPS0__CTF_DISABLE__SHIFT 0x19
+#define CC_THM_STRAPS0__TMON0_DISABLE_MASK 0x4000000
+#define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT 0x1a
+#define CC_THM_STRAPS0__TMON1_DISABLE_MASK 0x8000000
+#define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT 0x1b
+#define CC_THM_STRAPS0__TMON2_DISABLE_MASK 0x10000000
+#define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT 0x1c
+#define CC_THM_STRAPS0__TMON3_DISABLE_MASK 0x20000000
+#define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d
+#define CC_THM_STRAPS0__UNUSED_MASK 0x80000000
+#define CC_THM_STRAPS0__UNUSED__SHIFT 0x1f
+#define THM_TMON0_RDIL0_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL1_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL2_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL3_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL4_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL5_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL6_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL7_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL8_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL9_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL10_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL11_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL12_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL13_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL14_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIL15_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR0_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR1_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR2_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR3_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR4_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR5_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR6_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR7_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR8_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR9_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR10_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR11_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR12_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR13_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR14_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_RDIR15_DATA__Z_MASK 0x7ff
+#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0
+#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x800
+#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL0_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL0_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL0_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL1_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL1_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL1_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL2_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL2_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL2_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL3_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL3_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL3_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL4_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL4_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL4_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL5_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL5_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL5_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL6_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL6_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL6_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL7_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL7_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL7_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL8_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL8_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL8_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL9_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL9_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL9_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL10_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL10_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL10_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL11_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL11_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL11_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL12_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL12_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL12_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL13_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL13_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL13_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL14_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL14_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL14_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIL15_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIL15_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIL15_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR0_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR0_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR0_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR1_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR1_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR1_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR2_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR2_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR2_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR3_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR3_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR3_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR4_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR4_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR4_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR5_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR5_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR5_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR6_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR6_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR6_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR7_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR7_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR7_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR8_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR8_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR8_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR9_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR9_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR9_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR10_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR10_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR10_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR11_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR11_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR11_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR12_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR12_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR12_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR13_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR13_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR13_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR14_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR14_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR14_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_RDIR15_DATA__Z_MASK 0x7ff
+#define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x0
+#define THM_TMON1_RDIR15_DATA__VALID_MASK 0x800
+#define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_RDIR15_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_INT_DATA__Z_MASK 0x7ff
+#define THM_TMON0_INT_DATA__Z__SHIFT 0x0
+#define THM_TMON0_INT_DATA__VALID_MASK 0x800
+#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb
+#define THM_TMON0_INT_DATA__TEMP_MASK 0xfff000
+#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc
+#define THM_TMON1_INT_DATA__Z_MASK 0x7ff
+#define THM_TMON1_INT_DATA__Z__SHIFT 0x0
+#define THM_TMON1_INT_DATA__VALID_MASK 0x800
+#define THM_TMON1_INT_DATA__VALID__SHIFT 0xb
+#define THM_TMON1_INT_DATA__TEMP_MASK 0xfff000
+#define THM_TMON1_INT_DATA__TEMP__SHIFT 0xc
+#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x1f
+#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0
+#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0xffe0
+#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5
+#define THM_TMON1_DEBUG__DEBUG_RDI_MASK 0x1f
+#define THM_TMON1_DEBUG__DEBUG_RDI__SHIFT 0x0
+#define THM_TMON1_DEBUG__DEBUG_Z_MASK 0xffe0
+#define THM_TMON1_DEBUG__DEBUG_Z__SHIFT 0x5
+#define THM_TMON0_STATUS__CURRENT_RDI_MASK 0x1f
+#define THM_TMON0_STATUS__CURRENT_RDI__SHIFT 0x0
+#define THM_TMON0_STATUS__MEAS_DONE_MASK 0x20
+#define THM_TMON0_STATUS__MEAS_DONE__SHIFT 0x5
+#define THM_TMON1_STATUS__CURRENT_RDI_MASK 0x1f
+#define THM_TMON1_STATUS__CURRENT_RDI__SHIFT 0x0
+#define THM_TMON1_STATUS__MEAS_DONE_MASK 0x20
+#define THM_TMON1_STATUS__MEAS_DONE__SHIFT 0x5
+#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1
+#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0
+#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2
+#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3
+#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40
+#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6
+#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100
+#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8
+#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200
+#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9
+#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400
+#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa
+#define GENERAL_PWRMGT__SPARE11_MASK 0x800
+#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb
+#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000
+#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe
+#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000
+#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf
+#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000
+#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10
+#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000
+#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11
+#define GENERAL_PWRMGT__SPARE18_MASK 0x40000
+#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12
+#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000
+#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13
+#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000
+#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17
+#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000
+#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b
+#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000
+#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c
+#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3
+#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0
+#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4
+#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2
+#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8
+#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3
+#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10
+#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4
+#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0
+#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5
+#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1
+#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0
+#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10
+#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4
+#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20
+#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5
+#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000
+#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe
+#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000
+#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf
+#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000
+#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10
+#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000
+#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d
+#define PWR_PCC_CONTROL__PCC_POLARITY_MASK 0x1
+#define PWR_PCC_CONTROL__PCC_POLARITY__SHIFT 0x0
+#define PWR_PCC_GPIO_SELECT__GPIO_MASK 0xffffffff
+#define PWR_PCC_GPIO_SELECT__GPIO__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
+#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
+#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf
+#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
+#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0
+#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4
+#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00
+#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8
+#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000
+#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf
+#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000
+#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000
+#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000
+#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c
+#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff
+#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0
+#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f
+#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0
+#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80
+#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7
+#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
+#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
+#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
+#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
+#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000
+#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11
+#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000
+#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12
+#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000
+#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13
+#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000
+#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14
+#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000
+#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15
+#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000
+#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16
+#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000
+#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17
+#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000
+#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19
+#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000
+#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a
+#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000
+#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b
+#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000
+#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c
+#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000
+#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d
+#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000
+#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e
+#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
+#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2
+#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1
+#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4
+#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2
+#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8
+#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10
+#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4
+#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40
+#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6
+#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80
+#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7
+#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100
+#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8
+#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200
+#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9
+#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400
+#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa
+#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800
+#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000
+#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe
+#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000
+#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15
+#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000
+#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14
+#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
+#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
+#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
+#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
+#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
+#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
+#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000
+#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10
+#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
+#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
+#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1
+#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0
+#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2
+#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3
+#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10
+#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4
+#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20
+#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd
+#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000
+#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe
+#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000
+#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13
+#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000
+#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14
+#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000
+#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c
+#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff
+#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0
+#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000
+#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10
+#define SCLK_MIN_DIV__FRACV_MASK 0xfff
+#define SCLK_MIN_DIV__FRACV__SHIFT 0x0
+#define SCLK_MIN_DIV__INTV_MASK 0x7f000
+#define SCLK_MIN_DIV__INTV__SHIFT 0xc
+#define PWR_CKS_ENABLE__STRETCH_ENABLE_MASK 0x1
+#define PWR_CKS_ENABLE__STRETCH_ENABLE__SHIFT 0x0
+#define PWR_CKS_ENABLE__masterReset_MASK 0x2
+#define PWR_CKS_ENABLE__masterReset__SHIFT 0x1
+#define PWR_CKS_ENABLE__staticEnable_MASK 0x4
+#define PWR_CKS_ENABLE__staticEnable__SHIFT 0x2
+#define PWR_CKS_CNTL__CKS_BYPASS_MASK 0x1
+#define PWR_CKS_CNTL__CKS_BYPASS__SHIFT 0x0
+#define PWR_CKS_CNTL__CKS_PCCEnable_MASK 0x2
+#define PWR_CKS_CNTL__CKS_PCCEnable__SHIFT 0x1
+#define PWR_CKS_CNTL__CKS_TEMP_COMP_MASK 0x4
+#define PWR_CKS_CNTL__CKS_TEMP_COMP__SHIFT 0x2
+#define PWR_CKS_CNTL__CKS_STRETCH_AMOUNT_MASK 0x78
+#define PWR_CKS_CNTL__CKS_STRETCH_AMOUNT__SHIFT 0x3
+#define PWR_CKS_CNTL__CKS_SKIP_PHASE_BYPASS_MASK 0x80
+#define PWR_CKS_CNTL__CKS_SKIP_PHASE_BYPASS__SHIFT 0x7
+#define PWR_CKS_CNTL__CKS_SAMPLE_SIZE_MASK 0xf00
+#define PWR_CKS_CNTL__CKS_SAMPLE_SIZE__SHIFT 0x8
+#define PWR_CKS_CNTL__CKS_FSM_WAIT_CYCLES_MASK 0xf000
+#define PWR_CKS_CNTL__CKS_FSM_WAIT_CYCLES__SHIFT 0xc
+#define PWR_CKS_CNTL__CKS_USE_FOR_LOW_FREQ_MASK 0x10000
+#define PWR_CKS_CNTL__CKS_USE_FOR_LOW_FREQ__SHIFT 0x10
+#define PWR_CKS_CNTL__CKS_NO_EXTRA_COARSE_STEP_MASK 0x20000
+#define PWR_CKS_CNTL__CKS_NO_EXTRA_COARSE_STEP__SHIFT 0x11
+#define PWR_CKS_CNTL__CKS_LDO_REFSEL_MASK 0x3c0000
+#define PWR_CKS_CNTL__CKS_LDO_REFSEL__SHIFT 0x12
+#define PWR_CKS_CNTL__DDT_DEBUS_SEL_MASK 0x400000
+#define PWR_CKS_CNTL__DDT_DEBUS_SEL__SHIFT 0x16
+#define PWR_CKS_CNTL__CKS_LDO_READY_COUNT_VAL_MASK 0x7f800000
+#define PWR_CKS_CNTL__CKS_LDO_READY_COUNT_VAL__SHIFT 0x17
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x4000000
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000
+#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e
+#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x1
+#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0
+#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT_MASK 0x2
+#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1
+#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_MASK 0x4
+#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT__SHIFT 0x2
+#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xffffff80
+#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x4000000
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000
+#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e
+#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x1
+#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0
+#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT_MASK 0x2
+#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1
+#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_MASK 0x4
+#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT__SHIFT 0x2
+#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xffffff80
+#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7
+#define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH_MASK 0x3ff
+#define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0
+#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_MASK 0xffff
+#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD__SHIFT 0x0
+#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT_MASK 0xf0000
+#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT__SHIFT 0x10
+#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN_MASK 0x1
+#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN__SHIFT 0x0
+#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT_MASK 0x2
+#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT__SHIFT 0x1
+#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT_MASK 0x4
+#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT__SHIFT 0x2
+#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE_MASK 0x8
+#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE__SHIFT 0x3
+#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ_MASK 0x1
+#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ__SHIFT 0x0
+#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1
+#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0
+#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1
+#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0
+#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0
+#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1
+#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0
+#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1
+#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0
+#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0
+#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1
+#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0
+#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1
+#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0
+#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0
+#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1
+#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0
+#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1
+#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0
+#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0
+#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1
+#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0
+#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe
+#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1
+#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000
+#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11
+#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16
+#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff
+#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0
+#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff
+#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0
+#define ROM_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define ROM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define ROM_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define ROM_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define ROM_CNTL__SCK_OVERWRITE_MASK 0x2
+#define ROM_CNTL__SCK_OVERWRITE__SHIFT 0x1
+#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x4
+#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x2
+#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME_MASK 0xff00
+#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME__SHIFT 0x8
+#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME_MASK 0xff0000
+#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME__SHIFT 0x10
+#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0xf000000
+#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18
+#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK_MASK 0xf0000000
+#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK__SHIFT 0x1c
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0xffffff
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x1000000
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x2000000
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0xc000000
+#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a
+#define ROM_STATUS__ROM_BUSY_MASK 0x1
+#define ROM_STATUS__ROM_BUSY__SHIFT 0x0
+#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0xf
+#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0
+#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
+#define ROM_INDEX__ROM_INDEX_MASK 0xffffff
+#define ROM_INDEX__ROM_INDEX__SHIFT 0x0
+#define ROM_DATA__ROM_DATA_MASK 0xffffffff
+#define ROM_DATA__ROM_DATA__SHIFT 0x0
+#define ROM_START__ROM_START_MASK 0xffffff
+#define ROM_START__ROM_START__SHIFT 0x0
+#define ROM_SW_CNTL__DATA_SIZE_MASK 0xffff
+#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0
+#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x30000
+#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10
+#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x40000
+#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12
+#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x1
+#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0
+#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0xff
+#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0
+#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xffffff00
+#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8
+#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0
+#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff
+#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
+
+#endif /* SMU_7_1_2_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_d.h
new file mode 100644
index 000000000000..b404815ab2c4
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_d.h
@@ -0,0 +1,671 @@
+/*
+ * SMU_8_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef SMU_8_0_D_H
+#define SMU_8_0_D_H
+
+#define ixTHM_TCON_CSR_CONFIG 0xd82014a4
+#define ixTHM_TCON_CSR_DATA 0xd82014a8
+#define ixTHM_TCON_HTC 0xd8200c64
+#define ixTHM_TCON_CUR_TMP 0xd8200ca4
+#define ixTHM_TCON_THERM_TRIP 0xd8200ce4
+#define ixTHM_GPIO_PROCHOT_CTRL 0xd8200d00
+#define ixTHM_GPIO_THERMTRIP_CTRL 0xd8200d04
+#define ixTHM_THERMAL_INT_ENA 0xd8200d10
+#define ixTHM_THERMAL_INT_CTRL 0xd8200d14
+#define ixTHM_THERMAL_INT_STATUS 0xd8200d18
+#define ixTMON0_RDIL0_DATA 0xd8202000
+#define ixTMON0_RDIL1_DATA 0xd8202004
+#define ixTMON0_RDIL2_DATA 0xd8202008
+#define ixTMON0_RDIL3_DATA 0xd820200c
+#define ixTMON0_RDIL4_DATA 0xd8202010
+#define ixTMON0_RDIL5_DATA 0xd8202014
+#define ixTMON0_RDIL6_DATA 0xd8202018
+#define ixTMON0_RDIL7_DATA 0xd820201c
+#define ixTMON0_RDIL8_DATA 0xd8202020
+#define ixTMON0_RDIL9_DATA 0xd8202024
+#define ixTMON0_RDIL10_DATA 0xd8202028
+#define ixTMON0_RDIL11_DATA 0xd820202c
+#define ixTMON0_RDIL12_DATA 0xd8202030
+#define ixTMON0_RDIL13_DATA 0xd8202034
+#define ixTMON0_RDIL14_DATA 0xd8202038
+#define ixTMON0_RDIL15_DATA 0xd820203c
+#define ixTMON0_RDIR0_DATA 0xd8202040
+#define ixTMON0_RDIR1_DATA 0xd8202044
+#define ixTMON0_RDIR2_DATA 0xd8202048
+#define ixTMON0_RDIR3_DATA 0xd820204c
+#define ixTMON0_RDIR4_DATA 0xd8202050
+#define ixTMON0_RDIR5_DATA 0xd8202054
+#define ixTMON0_RDIR6_DATA 0xd8202058
+#define ixTMON0_RDIR7_DATA 0xd820205c
+#define ixTMON0_RDIR8_DATA 0xd8202060
+#define ixTMON0_RDIR9_DATA 0xd8202064
+#define ixTMON0_RDIR10_DATA 0xd8202068
+#define ixTMON0_RDIR11_DATA 0xd820206c
+#define ixTMON0_RDIR12_DATA 0xd8202070
+#define ixTMON0_RDIR13_DATA 0xd8202074
+#define ixTMON0_RDIR14_DATA 0xd8202078
+#define ixTMON0_RDIR15_DATA 0xd820207c
+#define ixTMON0_INT_DATA 0xd8202080
+#define ixTMON0_RDIL_PRESENT0 0xd8202084
+#define ixTMON0_RDIL_PRESENT1 0xd8202088
+#define ixTMON0_RDIR_PRESENT0 0xd820208c
+#define ixTMON0_RDIR_PRESENT1 0xd8202090
+#define ixTMON0_CONFIG 0xd8202098
+#define ixTMON0_TEMP_CALC_COEFF0 0xd82020a0
+#define ixTMON0_TEMP_CALC_COEFF1 0xd82020a4
+#define ixTMON0_TEMP_CALC_COEFF2 0xd82020a8
+#define ixTMON0_TEMP_CALC_COEFF3 0xd82020ac
+#define ixTMON0_TEMP_CALC_COEFF4 0xd82020b0
+#define ixTMON0_DEBUG0 0xd82020b4
+#define ixTMON0_DEBUG1 0xd82020b8
+#define ixTMON1_RDIL0_DATA 0xd8202100
+#define ixTMON1_RDIL1_DATA 0xd8202104
+#define ixTMON1_RDIL2_DATA 0xd8202108
+#define ixTMON1_RDIL3_DATA 0xd820210c
+#define ixTMON1_RDIL4_DATA 0xd8202110
+#define ixTMON1_RDIL5_DATA 0xd8202114
+#define ixTMON1_RDIL6_DATA 0xd8202118
+#define ixTMON1_RDIL7_DATA 0xd820211c
+#define ixTMON1_RDIL8_DATA 0xd8202120
+#define ixTMON1_RDIL9_DATA 0xd8202124
+#define ixTMON1_RDIL10_DATA 0xd8202128
+#define ixTMON1_RDIL11_DATA 0xd820212c
+#define ixTMON1_RDIL12_DATA 0xd8202130
+#define ixTMON1_RDIL13_DATA 0xd8202134
+#define ixTMON1_RDIL14_DATA 0xd8202138
+#define ixTMON1_RDIL15_DATA 0xd820213c
+#define ixTMON1_RDIR0_DATA 0xd8202140
+#define ixTMON1_RDIR1_DATA 0xd8202144
+#define ixTMON1_RDIR2_DATA 0xd8202148
+#define ixTMON1_RDIR3_DATA 0xd820214c
+#define ixTMON1_RDIR4_DATA 0xd8202150
+#define ixTMON1_RDIR5_DATA 0xd8202154
+#define ixTMON1_RDIR6_DATA 0xd8202158
+#define ixTMON1_RDIR7_DATA 0xd820215c
+#define ixTMON1_RDIR8_DATA 0xd8202160
+#define ixTMON1_RDIR9_DATA 0xd8202164
+#define ixTMON1_RDIR10_DATA 0xd8202168
+#define ixTMON1_RDIR11_DATA 0xd820216c
+#define ixTMON1_RDIR12_DATA 0xd8202170
+#define ixTMON1_RDIR13_DATA 0xd8202174
+#define ixTMON1_RDIR14_DATA 0xd8202178
+#define ixTMON1_RDIR15_DATA 0xd820217c
+#define ixTMON1_INT_DATA 0xd8202180
+#define ixTMON1_RDIL_PRESENT0 0xd8202184
+#define ixTMON1_RDIL_PRESENT1 0xd8202188
+#define ixTMON1_RDIR_PRESENT0 0xd820218c
+#define ixTMON1_RDIR_PRESENT1 0xd8202190
+#define ixTMON1_CONFIG 0xd8202198
+#define ixTMON1_TEMP_CALC_COEFF0 0xd82021a0
+#define ixTMON1_TEMP_CALC_COEFF1 0xd82021a4
+#define ixTMON1_TEMP_CALC_COEFF2 0xd82021a8
+#define ixTMON1_TEMP_CALC_COEFF3 0xd82021ac
+#define ixTMON1_TEMP_CALC_COEFF4 0xd82021b0
+#define ixTMON1_DEBUG0 0xd82021b4
+#define ixTMON1_DEBUG1 0xd82021b8
+#define ixTHM_TMON0_REMOTE_START 0xd8202800
+#define ixTHM_TMON0_REMOTE_END 0xd82028fc
+#define ixTHM_TMON1_REMOTE_START 0xd8202900
+#define ixTHM_TMON1_REMOTE_END 0xd82029fc
+#define ixTHM_TCON_LOCAL0 0xd8202e00
+#define ixTHM_TCON_LOCAL1 0xd8202e04
+#define ixTHM_TCON_LOCAL2 0xd8202e08
+#define ixTHM_TCON_LOCAL3 0xd8202e0c
+#define ixTHM_TCON_LOCAL4 0xd8202e10
+#define ixTHM_TCON_LOCAL5 0xd8202e14
+#define ixTHM_TCON_LOCAL6 0xd8202e18
+#define ixTHM_TCON_LOCAL7 0xd8202e1c
+#define ixTHM_TCON_LOCAL8 0xd8202e20
+#define ixTHM_TCON_LOCAL9 0xd8202e24
+#define ixTHM_TCON_LOCAL10 0xd8202e28
+#define ixTHM_TCON_LOCAL11 0xd8202e2c
+#define ixTHM_TCON_LOCAL12 0xd8202e30
+#define ixTHM_TCON_LOCAL13 0xd8202ef8
+#define ixTHM_TCON_LOCAL14 0xd8202efc
+#define ixTHM_FUSE0 0xd8210000
+#define ixTHM_FUSE1 0xd8210004
+#define ixTHM_FUSE2 0xd8210008
+#define ixTHM_FUSE3 0xd821000c
+#define ixTHM_FUSE4 0xd8210010
+#define ixTHM_FUSE5 0xd8210014
+#define ixTHM_FUSE6 0xd8210018
+#define ixTHM_FUSE7 0xd821001c
+#define ixTHM_FUSE8 0xd8210020
+#define ixTHM_FUSE9 0xd8210024
+#define ixTHM_FUSE10 0xd8210028
+#define ixTHM_FUSE11 0xd821002c
+#define ixTHM_FUSE12 0xd8210030
+#define mmMP0PUB_IND_INDEX 0x180
+#define mmMP_SMUIF0_MP0PUB_IND_INDEX 0x180
+#define mmMP_SMUIF1_MP0PUB_IND_INDEX 0x182
+#define mmMP_SMUIF2_MP0PUB_IND_INDEX 0x184
+#define mmMP_SMUIF3_MP0PUB_IND_INDEX 0x186
+#define mmMP_SMUIF4_MP0PUB_IND_INDEX 0x188
+#define mmMP_SMUIF5_MP0PUB_IND_INDEX 0x18a
+#define mmMP_SMUIF6_MP0PUB_IND_INDEX 0x18c
+#define mmMP_SMUIF7_MP0PUB_IND_INDEX 0x18e
+#define mmMP_SMUIF8_MP0PUB_IND_INDEX 0x190
+#define mmMP_SMUIF9_MP0PUB_IND_INDEX 0x192
+#define mmMP_SMUIF10_MP0PUB_IND_INDEX 0x194
+#define mmMP_SMUIF11_MP0PUB_IND_INDEX 0x196
+#define mmMP_SMUIF12_MP0PUB_IND_INDEX 0x198
+#define mmMP_SMUIF13_MP0PUB_IND_INDEX 0x19a
+#define mmMP_SMUIF14_MP0PUB_IND_INDEX 0x19c
+#define mmMP_SMUIF15_MP0PUB_IND_INDEX 0x19e
+#define mmMP0PUB_IND_DATA 0x181
+#define mmMP_SMUIF0_MP0PUB_IND_DATA 0x181
+#define mmMP_SMUIF1_MP0PUB_IND_DATA 0x183
+#define mmMP_SMUIF2_MP0PUB_IND_DATA 0x185
+#define mmMP_SMUIF3_MP0PUB_IND_DATA 0x187
+#define mmMP_SMUIF4_MP0PUB_IND_DATA 0x189
+#define mmMP_SMUIF5_MP0PUB_IND_DATA 0x18b
+#define mmMP_SMUIF6_MP0PUB_IND_DATA 0x18d
+#define mmMP_SMUIF7_MP0PUB_IND_DATA 0x18f
+#define mmMP_SMUIF8_MP0PUB_IND_DATA 0x191
+#define mmMP_SMUIF9_MP0PUB_IND_DATA 0x193
+#define mmMP_SMUIF10_MP0PUB_IND_DATA 0x195
+#define mmMP_SMUIF11_MP0PUB_IND_DATA 0x197
+#define mmMP_SMUIF12_MP0PUB_IND_DATA 0x199
+#define mmMP_SMUIF13_MP0PUB_IND_DATA 0x19b
+#define mmMP_SMUIF14_MP0PUB_IND_DATA 0x19d
+#define mmMP_SMUIF15_MP0PUB_IND_DATA 0x19f
+#define mmMP0PUB_IND_INDEX_0 0x180
+#define mmMP0PUB_IND_DATA_0 0x181
+#define mmMP0PUB_IND_INDEX_1 0x182
+#define mmMP0PUB_IND_DATA_1 0x183
+#define mmMP0PUB_IND_INDEX_2 0x184
+#define mmMP0PUB_IND_DATA_2 0x185
+#define mmMP0PUB_IND_INDEX_3 0x186
+#define mmMP0PUB_IND_DATA_3 0x187
+#define mmMP0PUB_IND_INDEX_4 0x188
+#define mmMP0PUB_IND_DATA_4 0x189
+#define mmMP0PUB_IND_INDEX_5 0x18a
+#define mmMP0PUB_IND_DATA_5 0x18b
+#define mmMP0PUB_IND_INDEX_6 0x18c
+#define mmMP0PUB_IND_DATA_6 0x18d
+#define mmMP0PUB_IND_INDEX_7 0x18e
+#define mmMP0PUB_IND_DATA_7 0x18f
+#define mmMP0PUB_IND_INDEX_8 0x190
+#define mmMP0PUB_IND_DATA_8 0x191
+#define mmMP0PUB_IND_INDEX_9 0x192
+#define mmMP0PUB_IND_DATA_9 0x193
+#define mmMP0PUB_IND_INDEX_10 0x194
+#define mmMP0PUB_IND_DATA_10 0x195
+#define mmMP0PUB_IND_INDEX_11 0x196
+#define mmMP0PUB_IND_DATA_11 0x197
+#define mmMP0PUB_IND_INDEX_12 0x198
+#define mmMP0PUB_IND_DATA_12 0x199
+#define mmMP0PUB_IND_INDEX_13 0x19a
+#define mmMP0PUB_IND_DATA_13 0x19b
+#define mmMP0PUB_IND_INDEX_14 0x19c
+#define mmMP0PUB_IND_DATA_14 0x19d
+#define mmMP0PUB_IND_INDEX_15 0x19e
+#define mmMP0PUB_IND_DATA_15 0x19f
+#define mmMP0_IND_ACCESS_CNTL 0x1a0
+#define mmMP0_MSP_MESSAGE_0 0x1a1
+#define mmMP0_MSP_MESSAGE_1 0x1a2
+#define mmMP0_MSP_MESSAGE_2 0x1a3
+#define mmMP0_MSP_MESSAGE_3 0x1a4
+#define mmMP0_MSP_MESSAGE_4 0x1a5
+#define mmMP0_MSP_MESSAGE_5 0x1a6
+#define mmMP0_MSP_MESSAGE_6 0x1a7
+#define mmMP0_MSP_MESSAGE_7 0x1a8
+#define mmSAM_IH_EXT_ERR_INTR 0x1a9
+#define mmSAM_IH_EXT_ERR_INTR_STATUS 0x1aa
+#define mmMP0_DISP_TIMER0_CTRL0 0x1ab
+#define mmMP0_DISP_TIMER0_CTRL1 0x1ac
+#define mmMP0_DISP_TIMER0_CMP_AUTOINC 0x1ad
+#define mmMP0_DISP_TIMER0_INTEN 0x1ae
+#define mmMP0_DISP_TIMER0_OCMP_0_0 0x1af
+#define mmMP0_DISP_TIMER0_OCMP_0_1 0x1b0
+#define mmMP0_DISP_TIMER0_CNT 0x1b1
+#define mmMP0_DISP_TIMER1_CTRL0 0x1b2
+#define mmMP0_DISP_TIMER1_CTRL1 0x1b3
+#define mmMP0_DISP_TIMER1_CMP_AUTOINC 0x1b4
+#define mmMP0_DISP_TIMER1_INTEN 0x1b5
+#define mmMP0_DISP_TIMER1_OCMP_0_0 0x1b6
+#define mmMP0_DISP_TIMER1_OCMP_0_1 0x1b7
+#define mmMP0_DISP_TIMER1_CNT 0x1b8
+#define mmSMU_MP1_SRBM2P_MSG_0 0x1c0
+#define mmSMU_MP1_SRBM2P_MSG_1 0x1c1
+#define mmSMU_MP1_SRBM2P_MSG_2 0x1c2
+#define mmSMU_MP1_SRBM2P_MSG_3 0x1c3
+#define mmSMU_MP1_SRBM2P_MSG_4 0x1c4
+#define mmSMU_MP1_SRBM2P_MSG_5 0x1c5
+#define mmSMU_MP1_SRBM2P_MSG_6 0x1c6
+#define mmSMU_MP1_SRBM2P_MSG_7 0x1c7
+#define mmSMU_MP1_SRBM2P_MSG_8 0x1c8
+#define mmSMU_MP1_SRBM2P_MSG_9 0x1c9
+#define mmSMU_MP1_SRBM2P_MSG_10 0x1ca
+#define mmSMU_MP1_SRBM2P_MSG_11 0x1cb
+#define mmSMU_MP1_SRBM2P_MSG_12 0x1cc
+#define mmSMU_MP1_SRBM2P_MSG_13 0x1cd
+#define mmSMU_MP1_SRBM2P_MSG_14 0x1ce
+#define mmSMU_MP1_SRBM2P_MSG_15 0x1cf
+#define mmSMU_MP1_SRBM2P_RESP_0 0x1d0
+#define mmSMU_MP1_SRBM2P_RESP_1 0x1d1
+#define mmSMU_MP1_SRBM2P_RESP_2 0x1d2
+#define mmSMU_MP1_SRBM2P_RESP_3 0x1d3
+#define mmSMU_MP1_SRBM2P_RESP_4 0x1d4
+#define mmSMU_MP1_SRBM2P_RESP_5 0x1d5
+#define mmSMU_MP1_SRBM2P_RESP_6 0x1d6
+#define mmSMU_MP1_SRBM2P_RESP_7 0x1d7
+#define mmSMU_MP1_SRBM2P_RESP_8 0x1d8
+#define mmSMU_MP1_SRBM2P_RESP_9 0x1d9
+#define mmSMU_MP1_SRBM2P_RESP_10 0x1da
+#define mmSMU_MP1_SRBM2P_RESP_11 0x1db
+#define mmSMU_MP1_SRBM2P_RESP_12 0x1dc
+#define mmSMU_MP1_SRBM2P_RESP_13 0x1dd
+#define mmSMU_MP1_SRBM2P_RESP_14 0x1de
+#define mmSMU_MP1_SRBM2P_RESP_15 0x1df
+#define mmSMU_MP1_SRBM2P_ARG_0 0x1e0
+#define mmSMU_MP1_SRBM2P_ARG_1 0x1e1
+#define mmSMU_MP1_SRBM2P_ARG_2 0x1e2
+#define mmSMU_MP1_SRBM2P_ARG_3 0x1e3
+#define mmSMU_MP1_SRBM2P_ARG_4 0x1e4
+#define mmSMU_MP1_SRBM2P_ARG_5 0x1e5
+#define mmSMU_MP1_SRBM2P_ARG_6 0x1e6
+#define mmSMU_MP1_SRBM2P_ARG_7 0x1e7
+#define mmSMU_MP1_SRBM2P_ARG_8 0x1e8
+#define mmSMU_MP1_SRBM2P_ARG_9 0x1e9
+#define mmSMU_MP1_SRBM2P_ARG_10 0x1ea
+#define mmSMU_MP1_SRBM2P_ARG_11 0x1eb
+#define mmSMU_MP1_SRBM2P_ARG_12 0x1ec
+#define mmSMU_MP1_SRBM2P_ARG_13 0x1ed
+#define mmSMU_MP1_SRBM2P_ARG_14 0x1ee
+#define mmSMU_MP1_SRBM2P_ARG_15 0x1ef
+#define mmSMU_MP1_ACP2MP_RESP 0x1f0
+#define mmSMU_MP1_DC2MP_RESP 0x1f1
+#define mmSMU_MP1_UVD2MP_RESP 0x1f2
+#define mmSMU_MP1_VCE2MP_RESP 0x1f3
+#define mmSMU_MP1_RLC2MP_RESP 0x1f4
+#define mmMP_FPS_CNT 0x1f5
+#define mmSMU_DISP0_TIMER_INT_CONTROL 0x1f6
+#define mmSMU_DISP1_TIMER_INT_CONTROL 0x1f7
+#define mmSMU_SRBM_CONFIG 0x1f8
+#define ixMP_FPS_CNT_XBAR 0xcf200800
+#define ixMP_SRBM_CONFIG_XBAR 0xcf200804
+#define ixMP_SRBM_CONTROL 0xcf200c00
+#define ixMP_SRBM_ACCVIO_LOG 0xcf200c04
+#define ixMP_SRBM_ACCVIO_ADDR 0xcf200c08
+#define ixMP_CRBBM_CONTROL 0xcf200c0c
+#define ixMP_CRBBM_ACCVIO_LOG 0xcf200c10
+#define ixMP_CRBBM_ACCVIO_ADDR 0xcf200c14
+#define ixMP_DRAM_CNTL_WRREQ_CNTL 0xcf200000
+#define ixMP_DRAM_CNTL_WRREQ_CNTL_1 0xcf200004
+#define ixMP_DRAM_CNTL_WRREQ_LOW_ADDR 0xcf200008
+#define ixMP_DRAM_CNTL_WRREQ_HIGH_ADDR 0xcf20000c
+#define ixMP_DRAM_CNTL_WRREQ_MASK 0xcf200010
+#define ixMP_DRAM_CNTL_WRREQ_DATA_0 0xcf200014
+#define ixMP_DRAM_CNTL_WRREQ_DATA_1 0xcf200018
+#define ixMP_DRAM_CNTL_WRREQ_DATA_2 0xcf20001c
+#define ixMP_DRAM_CNTL_WRREQ_DATA_3 0xcf200020
+#define ixMP_DRAM_CNTL_WRREQ_DATA_4 0xcf200024
+#define ixMP_DRAM_CNTL_WRREQ_DATA_5 0xcf200028
+#define ixMP_DRAM_CNTL_WRREQ_DATA_6 0xcf20002c
+#define ixMP_DRAM_CNTL_WRREQ_DATA_7 0xcf200030
+#define ixMP_DRAM_CNTL_WRREQ_STATUS 0xcf200038
+#define ixMP_DRAM_CNTL_WRRET_STATUS_0 0xcf20003c
+#define ixMP_DRAM_CNTL_RDREQ_ADDR 0xcf200040
+#define ixMP_DRAM_CNTL_RDREQ_CNTL 0xcf200044
+#define ixMP_DRAM_CNTL_RDREQ_CNTL_1 0xcf200048
+#define ixMP_DRAM_CNTL_RDRET_VALID 0xcf20004c
+#define ixMP_DRAM_CNTL_RDRET_NACK 0xcf200050
+#define ixMP_DRAM_CNTL_RDRET_DATA_0 0xcf200054
+#define ixMP_DRAM_CNTL_RDRET_DATA_1 0xcf200058
+#define ixMP_DRAM_CNTL_RDRET_DATA_2 0xcf20005c
+#define ixMP_DRAM_CNTL_RDRET_DATA_3 0xcf200060
+#define ixMP_DRAM_CNTL_RDRET_DATA_4 0xcf200064
+#define ixMP_DRAM_CNTL_RDRET_DATA_5 0xcf200068
+#define ixMP_DRAM_CNTL_RDRET_DATA_6 0xcf20006c
+#define ixMP_DRAM_CNTL_RDRET_DATA_7 0xcf200070
+#define ixMP_DRAM_CNTL_RDRET_DATA_8 0xcf200074
+#define ixMP_DRAM_CNTL_RDRET_DATA_9 0xcf200078
+#define ixMP_DRAM_CNTL_RDRET_DATA_10 0xcf20007c
+#define ixMP_DRAM_CNTL_RDRET_DATA_11 0xcf200080
+#define ixMP_DRAM_CNTL_RDRET_DATA_12 0xcf200084
+#define ixMP_DRAM_CNTL_RDRET_DATA_13 0xcf200088
+#define ixMP_DRAM_CNTL_RDRET_DATA_14 0xcf20008c
+#define ixMP_DRAM_CNTL_RDRET_DATA_15 0xcf200090
+#define ixMP_DRAM_CNTL_RDRET_DATA_16 0xcf200094
+#define ixMP_DRAM_CNTL_RDRET_DATA_17 0xcf200098
+#define ixMP_DRAM_CNTL_RDRET_DATA_18 0xcf20009c
+#define ixMP_DRAM_CNTL_RDRET_DATA_19 0xcf2000a0
+#define ixMP_DRAM_CNTL_RDRET_DATA_20 0xcf2000a4
+#define ixMP_DRAM_CNTL_RDRET_DATA_21 0xcf2000a8
+#define ixMP_DRAM_CNTL_RDRET_DATA_22 0xcf2000ac
+#define ixMP_DRAM_CNTL_RDRET_DATA_23 0xcf2000b0
+#define ixMP_DRAM_CNTL_RDRET_DATA_24 0xcf2000b4
+#define ixMP_DRAM_CNTL_RDRET_DATA_25 0xcf2000b8
+#define ixMP_DRAM_CNTL_RDRET_DATA_26 0xcf2000bc
+#define ixMP_DRAM_CNTL_RDRET_DATA_27 0xcf2000c0
+#define ixMP_DRAM_CNTL_RDRET_DATA_28 0xcf2000c4
+#define ixMP_DRAM_CNTL_RDRET_DATA_29 0xcf2000c8
+#define ixMP_DRAM_CNTL_RDRET_DATA_30 0xcf2000cc
+#define ixMP_DRAM_CNTL_RDRET_DATA_31 0xcf2000d0
+#define ixMP_DRAM_CNTL_RDRET_DATA_32 0xcf2000d4
+#define ixMP_DRAM_CNTL_RDRET_DATA_33 0xcf2000d8
+#define ixMP_DRAM_CNTL_RDRET_DATA_34 0xcf2000dc
+#define ixMP_DRAM_CNTL_RDRET_DATA_35 0xcf2000e0
+#define ixMP_DRAM_CNTL_RDRET_DATA_36 0xcf2000e4
+#define ixMP_DRAM_CNTL_RDRET_DATA_37 0xcf2000e8
+#define ixMP_DRAM_CNTL_RDRET_DATA_38 0xcf2000ec
+#define ixMP_DRAM_CNTL_RDRET_DATA_39 0xcf2000f0
+#define ixMP_DRAM_CNTL_RDRET_DATA_40 0xcf2000f4
+#define ixMP_DRAM_CNTL_RDRET_DATA_41 0xcf2000f8
+#define ixMP_DRAM_CNTL_RDRET_DATA_42 0xcf2000fc
+#define ixMP_DRAM_CNTL_RDRET_DATA_43 0xcf200100
+#define ixMP_DRAM_CNTL_RDRET_DATA_44 0xcf200104
+#define ixMP_DRAM_CNTL_RDRET_DATA_45 0xcf200108
+#define ixMP_DRAM_CNTL_RDRET_DATA_46 0xcf20010c
+#define ixMP_DRAM_CNTL_RDRET_DATA_47 0xcf200110
+#define ixMP_DRAM_CNTL_RDRET_DATA_48 0xcf200114
+#define ixMP_DRAM_CNTL_RDRET_DATA_49 0xcf200118
+#define ixMP_DRAM_CNTL_RDRET_DATA_50 0xcf20011c
+#define ixMP_DRAM_CNTL_RDRET_DATA_51 0xcf200120
+#define ixMP_DRAM_CNTL_RDRET_DATA_52 0xcf200124
+#define ixMP_DRAM_CNTL_RDRET_DATA_53 0xcf200128
+#define ixMP_DRAM_CNTL_RDRET_DATA_54 0xcf20012c
+#define ixMP_DRAM_CNTL_RDRET_DATA_55 0xcf200130
+#define ixMP_DRAM_CNTL_RDRET_DATA_56 0xcf200134
+#define ixMP_DRAM_CNTL_RDRET_DATA_57 0xcf200138
+#define ixMP_DRAM_CNTL_RDRET_DATA_58 0xcf20013c
+#define ixMP_DRAM_CNTL_RDRET_DATA_59 0xcf200140
+#define ixMP_DRAM_CNTL_RDRET_DATA_60 0xcf200144
+#define ixMP_DRAM_CNTL_RDRET_DATA_61 0xcf200148
+#define ixMP_DRAM_CNTL_RDRET_DATA_62 0xcf20014c
+#define ixMP_DRAM_CNTL_RDRET_DATA_63 0xcf200150
+#define ixMP_IOC_CTRL 0xcf100000
+#define ixMP_IOC_RDDATA 0xcf100004
+#define ixMP_IOC_PHASE1 0xcf100008
+#define ixMP_IOC_PHASE2 0xcf10000c
+#define ixMP_IOC_PHASE3 0xcf100010
+#define ixMP_IOC_READ_0 0xcf100024
+#define ixMP_IOC_READ_1 0xcf100028
+#define ixMP_IOC_READ_2 0xcf10002c
+#define ixMP_IOC_READ_3 0xcf100030
+#define ixMP_IOC_READ_4 0xcf100034
+#define ixMP_IOC_READ_5 0xcf100038
+#define ixMP_IOC_READ_6 0xcf10003c
+#define ixMP_IOC_READ_7 0xcf100040
+#define ixMP_IOC_READ_8 0xcf100044
+#define ixMP_IOC_READ_9 0xcf100048
+#define ixMP_IOC_READ_10 0xcf10004c
+#define ixMP_IOC_READ_11 0xcf100050
+#define ixMP_IOC_READ_12 0xcf100054
+#define ixMP_IOC_READ_13 0xcf100058
+#define ixMP_IOC_READ_14 0xcf10005c
+#define ixMP_IOC_READ_15 0xcf100060
+#define ixMP_IOC_WRITE_0 0xcf100064
+#define ixMP_IOC_WRITE_1 0xcf100068
+#define ixMP_IOC_WRITE_2 0xcf10006c
+#define ixMP_IOC_WRITE_3 0xcf100070
+#define ixMP_IOC_WRITE_4 0xcf100074
+#define ixMP_IOC_WRITE_5 0xcf100078
+#define ixMP_IOC_WRITE_6 0xcf10007c
+#define ixMP_IOC_WRITE_7 0xcf100080
+#define ixMP_IOC_WRITE_8 0xcf100084
+#define ixMP_IOC_WRITE_9 0xcf100088
+#define ixMP_IOC_WRITE_10 0xcf10008c
+#define ixMP_IOC_WRITE_11 0xcf100090
+#define ixMP_IOC_WRITE_12 0xcf100094
+#define ixMP_IOC_WRITE_13 0xcf100098
+#define ixMP_IOC_WRITE_14 0xcf10009c
+#define ixMP_IOC_WRITE_15 0xcf1000a0
+#define ixMP_INTERRUPT_CONTROL 0xcf200400
+#define ixMP0_SW_INT 0xcf200404
+#define ixMP0_SW_INT_CTXID 0xcf200408
+#define ixMP1_SW_INT 0xcf20040c
+#define ixMP1_SW_INT_CTXID 0xcf200410
+#define ixDISP_TIMER_ID 0xcf200414
+#define mmPWRHW_SMC_IND_INDEX 0x180
+#define mmPWRHW0_PWRHW_SMC_IND_INDEX 0x180
+#define mmPWRHW1_PWRHW_SMC_IND_INDEX 0x182
+#define mmPWRHW2_PWRHW_SMC_IND_INDEX 0x184
+#define mmPWRHW3_PWRHW_SMC_IND_INDEX 0x186
+#define mmPWRHW_SMC_IND_DATA 0x181
+#define mmPWRHW0_PWRHW_SMC_IND_DATA 0x181
+#define mmPWRHW1_PWRHW_SMC_IND_DATA 0x183
+#define mmPWRHW2_PWRHW_SMC_IND_DATA 0x185
+#define mmPWRHW3_PWRHW_SMC_IND_DATA 0x187
+#define ixCURRENT_STATE_CPU0 0xd0210000
+#define ixCURRENT_STATE_CPU1 0xd0210010
+#define ixCPU_REDUN_DONE0 0xd0210004
+#define ixCPU_REDUN_DONE1 0xd0210014
+#define ixCURRENT_VID_CPU0 0xd0210008
+#define ixCURRENT_VID_CPU1 0xd0210018
+#define ixUNBPM_PWRMGT_ACK 0xd0211000
+#define ixCURRENT_FREQ_STATE_NB 0xd0211004
+#define ixCURRENT_PSTATE_NB 0xd0211008
+#define ixUNBPM_MSG_INT_CONFIG 0xd021100c
+#define ixUNBPM_NBPWRMGT_CMD 0xd0211010
+#define ixUNBPM_NBPWRMGT_FSM_CFG 0xd0211014
+#define ixDDR0_FUSE_SSB_XFER 0xd0211018
+#define ixDDR0_FUSE_SSB_XFER_CFG 0xd021101c
+#define ixDDR1_FUSE_SSB_XFER 0xd0211020
+#define ixDDR1_FUSE_SSB_XFER_CFG 0xd0211024
+#define ixUNBPM_FUSES_VAL_PWROK 0xd0211028
+#define ixSYNFIFO_CLK_RATIO 0xd021102c
+#define ixMISC_SMU_PWRMGT_CFG0 0xd0211030
+#define ixMISC_GNB_PWRMGT_CFG1 0xd0211034
+#define ixMISC_SMU_PWRMGT_CFG1 0xd0211038
+#define ixMISC_GNB_PWRMGT_DATA 0xd021103c
+#define ixGN_GNB_SLOW 0xd0211040
+#define ixGN_FORCE_NBPS1 0xd0211044
+#define ixMISC_SMU_PWRMGT_DATA 0xd0211048
+#define ixNB_COF 0xd021104c
+#define ixUNBPM_CK_IRESET 0xd0211050
+#define ixCURRENT_VID_NB 0xd0211054
+#define ixSPR_FUSE_PSTATEPWR1 0xd0211058
+#define ixSPR_FUSE_PSTATEPWR2 0xd021105c
+#define ixSPR_FUSE_PSTATEPWR3 0xd0211060
+#define ixSPR_FUSE_THERMAL_SCRATCH 0xd0211064
+#define ixSPR_PRODUCT_INFO0 0xd0211068
+#define ixSPR_SERIALNUM_REG1 0xd021106c
+#define ixSPR_SERIALNUM_REG2 0xd0211070
+#define ixSPR_PRODUCT_INFO1 0xd0211074
+#define ixSPR_EXT_PRODUCT_INFO 0xd021107c
+#define ixSPR_MSIDFUSE 0xd0211080
+#define ixSPR_LINK_PRODUCT_INFO 0xd0211084
+#define ixSPR_BRAND_NAME_ADDR 0xd0211088
+#define ixSPR_BRAND_NAME_DATA 0xd021108c
+#define ixSPR_COMBO_PHY_PRODUCT_INFO 0xd0211090
+#define ixMISC_GNB_PWRMGT_CFG0 0xd0211094
+#define ixUNBPM_EXIT_TO_PSTATE 0xd0211098
+#define ixUNBPM_WARM_RESET_HS_STATUS 0xd021109c
+#define ixUNBPM_VOLTAGE_CNTL 0xd02110a0
+#define ixUNBPM_VOLTAGE_STATUS 0xd02110a4
+#define ixNUM_BOOST_STATES 0xd02110a8
+#define ixWARM_RESET_NB_CONTROL 0xd02110ac
+#define ixONION_NO_STREAMS_PEND 0xd02110b0
+#define ixSPR_PROGRAMMABLE_CTRL 0xd02110b4
+#define ixPHN_FUSERX_MISC_FUSES 0xd02110b8
+#define ixUNBPM_PWRCTRL_MISC 0xd02110bc
+#define ixCSTATE_ACTIVE_SAMPLER 0xd02110c0
+#define ixUNBPM_DEBUG_CONFIG_STATUS 0xd02110c4
+#define ixUNBPM_AXIMST_LAST_CMD 0xd02110c8
+#define ixUNB_IF_INTRGEN_LAST_SENT 0xd02110cc
+#define ixUNBPM_DEBUG_BUS_CNTL 0xd02110d0
+#define ixUNBPM_PWRMGT_REQ_DBG_STATUS 0xd02110d4
+#define ixUNBPM_VIDCHG_REQ_DBG_STATUS 0xd02110d8
+#define ixUNBPM_SCRATCH_0 0xd021e000
+#define ixUNBPM_SCRATCH_1 0xd021e004
+#define ixPOWERON_CPU_0 0xd0220000
+#define ixPOWERREADY_CPU_0 0xd0220004
+#define ixPGRUNFEEDBACK_CPU_0 0xd0220008
+#define ixRCC3ON_CPU_0 0xd022000c
+#define ixRCC3EXITDONE_CPU_0 0xd0220010
+#define ixCORE_FUNC_LATE_SSB_XFER_0 0xd0220014
+#define ixCORE_FUNC_LATE_SSB_XFER_CFG_0 0xd0220018
+#define ixCORE_REDUN_SSB_XFER_0 0xd022001c
+#define ixCORE_REDUN_SSB_XFER_CFG_0 0xd0220020
+#define ixCORE_APM_SSB_XFER_0 0xd0220024
+#define ixCORE_APM_SSB_XFER_CFG_0 0xd0220028
+#define ixCOREPM_PWRCTRL_MISC_0 0xd022002c
+#define ixLDOIVRON_CPU_0 0xd0220030
+#define ixLDOIVREXITDONE_CPU_0 0xd0220034
+#define ixRCC3_TARGETPSMREF_CPU_0 0xd0220038
+#define ixIVR_TARGETPSMREF_CPU_0 0xd022003c
+#define ixCK_JTCOOLRESET_LATCHED_CPU_0 0xd0220044
+#define ixCK_DISABLECORE_CPU_0 0xd0220048
+#define ixCOREPM_ID_0 0xd022004c
+#define ixCOREPM_SCRATCH_0 0xd0220050
+#define ixRCC3_WAKEMIN_CPU_0 0xd0220054
+#define ixSPMI_CONFIG0_0 0xd0221000
+#define ixSPMI_CONFIG1_0 0xd0221004
+#define ixSPMI_FSM_READ_TRIGGER_0 0xd0221008
+#define ixSPMI_FSM_WRITE_TRIGGER_0 0xd022100c
+#define ixSPMI_FSM_RESET_TRIGGER_0 0xd0221010
+#define ixSPMI_FSM_BUSY_0 0xd0221014
+#define ixSPMI_PATH_0 0xd0221018
+#define ixSPMI_C6_STATE_0 0xd022101c
+#define ixSPMI_JTAG_OVER_0 0xd0221020
+#define ixSPMI_SRAM_ADDRESS_0 0xd0221024
+#define ixSPMI_SRAM_DATA_0 0xd0221028
+#define ixSPMI_RESET_0 0xd022102c
+#define ixSPMI_FORCE_CLOCK_GATERS_0 0xd0221030
+#define ixSPMI_SPARE_0 0xd0221034
+#define ixSPMI_SPARE_EX_0 0xd0221038
+#define ixSPMI_SRAM_CLK_GATER_0 0xd022103c
+#define ixPOWERON_CPU_1 0xd0230000
+#define ixPOWERREADY_CPU_1 0xd0230004
+#define ixPGRUNFEEDBACK_CPU_1 0xd0230008
+#define ixRCC3ON_CPU_1 0xd023000c
+#define ixRCC3EXITDONE_CPU_1 0xd0230010
+#define ixCORE_FUNC_LATE_SSB_XFER_1 0xd0230014
+#define ixCORE_FUNC_LATE_SSB_XFER_CFG_1 0xd0230018
+#define ixCORE_REDUN_SSB_XFER_1 0xd023001c
+#define ixCORE_REDUN_SSB_XFER_CFG_1 0xd0230020
+#define ixCORE_APM_SSB_XFER_1 0xd0230024
+#define ixCORE_APM_SSB_XFER_CFG_1 0xd0230028
+#define ixCOREPM_PWRCTRL_MISC_1 0xd023002c
+#define ixLDOIVRON_CPU_1 0xd0230030
+#define ixLDOIVREXITDONE_CPU_1 0xd0230034
+#define ixRCC3_TARGETPSMREF_CPU_1 0xd0230038
+#define ixIVR_TARGETPSMREF_CPU_1 0xd023003c
+#define ixCK_JTCOOLRESET_LATCHED_CPU_1 0xd0230044
+#define ixCK_DISABLECORE_CPU_1 0xd0230048
+#define ixCOREPM_ID_1 0xd023004c
+#define ixCOREPM_SCRATCH_1 0xd0230050
+#define ixRCC3_WAKEMIN_CPU_1 0xd0230054
+#define ixSPMI_CONFIG0_1 0xd0231000
+#define ixSPMI_CONFIG1_1 0xd0231004
+#define ixSPMI_FSM_READ_TRIGGER_1 0xd0231008
+#define ixSPMI_FSM_WRITE_TRIGGER_1 0xd023100c
+#define ixSPMI_FSM_RESET_TRIGGER_1 0xd0231010
+#define ixSPMI_FSM_BUSY_1 0xd0231014
+#define ixSPMI_PATH_1 0xd0231018
+#define ixSPMI_C6_STATE_1 0xd023101c
+#define ixSPMI_JTAG_OVER_1 0xd0231020
+#define ixSPMI_SRAM_ADDRESS_1 0xd0231024
+#define ixSPMI_SRAM_DATA_1 0xd0231028
+#define ixSPMI_RESET_1 0xd023102c
+#define ixSPMI_FORCE_CLOCK_GATERS_1 0xd0231030
+#define ixSPMI_SPARE_1 0xd0231034
+#define ixSPMI_SPARE_EX_1 0xd0231038
+#define ixSPMI_SRAM_CLK_GATER_1 0xd023103c
+#define ixGENERAL_PWRMGT 0xd0200000
+#define ixCNB_PWRMGT_CNTL 0xd0200004
+#define ixSCLK_PWRMGT_CNTL 0xd0200008
+#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xd0200014
+#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xd02000f0
+#define ixTARGET_AND_CURRENT_PROFILE_INDEX_2 0xd02000f4
+#define ixCG_FREQ_TRAN_VOTING_0 0xd02001a8
+#define ixCG_FREQ_TRAN_VOTING_1 0xd02001ac
+#define ixCG_FREQ_TRAN_VOTING_2 0xd02001b0
+#define ixCG_FREQ_TRAN_VOTING_3 0xd02001b4
+#define ixCG_FREQ_TRAN_VOTING_4 0xd02001b8
+#define ixCG_FREQ_TRAN_VOTING_5 0xd02001bc
+#define ixCG_FREQ_TRAN_VOTING_6 0xd02001c0
+#define ixCG_FREQ_TRAN_VOTING_7 0xd02001c4
+#define ixCG_STATIC_SCREEN_PARAMETER 0xd0200044
+#define ixCG_ACPI_CNTL 0xd0200064
+#define ixSCLK_DEEP_SLEEP_CNTL 0xd0200080
+#define ixSCLK_DEEP_SLEEP_CNTL2 0xd0200084
+#define ixSCLK_DEEP_SLEEP_CNTL3 0xd020009c
+#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xd0200088
+#define ixLCLK_DEEP_SLEEP_CNTL 0xd020008c
+#define ixLCLK_DEEP_SLEEP_CNTL2 0xd0200310
+#define ixSMU_VOLTAGE_STATUS 0xd0200094
+#define ixCG_ULV_PARAMETER 0xd020015c
+#define ixPWR_DC_RESP 0xd0200300
+#define ixPWR_VCE_RESP 0xd0200304
+#define ixPWR_UVD_RESP 0xd0200308
+#define ixPWR_ACP_RESP 0xd020030c
+#define ixPWR_DC_REQ 0xd020031c
+#define ixSCLK_MIN_DIV 0xd02003ac
+#define ixPCIE_PGFSM_CONFIG 0xd02002d0
+#define ixPCIE_PGFSM_WRITE 0xd02002d4
+#define ixSERDES_BUSY 0xd02002d8
+#define ixPCIE_PGFSM2_CONFIG 0xd02002dc
+#define ixPCIE_PGFSM2_WRITE 0xd02002e0
+#define ixSERDES2_BUSY 0xd02002e4
+#define ixPCIE_PGFSM_0_READ 0xd02002e8
+#define ixPCIE_PGFSM_1_READ 0xd02002ec
+#define ixPWR_ACPI_INTERRUPT 0xd0200318
+#define ixVDDGFX_IDLE_PARAMETER 0xd020036c
+#define ixVDDGFX_IDLE_CONTROL 0xd0200370
+#define ixVDDGFX_IDLE_EXIT 0xd0200374
+#define ixREG_SCLK_DEEP_SLEEP_EXIT 0xd0200378
+#define ixCAC_WEIGHT_LKG_DC_3 0xd020803c
+#define ixLCAC_MC0_CNTL 0xd0208130
+#define ixLCAC_MC0_OVR_SEL 0xd0208134
+#define ixLCAC_MC0_OVR_VAL 0xd0208138
+#define ixLCAC_MC1_CNTL 0xd020813c
+#define ixLCAC_MC1_OVR_SEL 0xd0208140
+#define ixLCAC_MC1_OVR_VAL 0xd0208144
+#define ixLCAC_MC2_CNTL 0xd0208148
+#define ixLCAC_MC2_OVR_SEL 0xd020814c
+#define ixLCAC_MC2_OVR_VAL 0xd0208150
+#define ixLCAC_MC3_CNTL 0xd0208154
+#define ixLCAC_MC3_OVR_SEL 0xd0208158
+#define ixLCAC_MC3_OVR_VAL 0xd020815c
+#define ixLCAC_CPL_CNTL 0xd0208160
+#define ixLCAC_CPL_OVR_SEL 0xd0208164
+#define ixLCAC_CPL_OVR_VAL 0xd0208168
+#define ixMISC_UNB_PWRMGT_CFG0 0xd020c000
+#define ixMISC_UNB_PWRMGT_CFG1 0xd020c004
+#define ixMISC_UNB_PWRMGT_DATA 0xd020c00c
+#define ixGNBPM_SMU_PWRMGT_DATA 0xd020c010
+#define ixDMA_ACTIVE_SAMPLER_CFG 0xd020c014
+#define ixSOUTHBRIDGE_TYPE 0xd020c01c
+#define ixGNBPM_SMU_PWRMGT_STATUS 0xd020c020
+#define ixALLOW_SR_INTR_CTRL 0xd020c024
+#define mmGC_CAC_LKG_AGGR_LOWER 0x3294
+#define mmGC_CAC_LKG_AGGR_UPPER 0x3295
+#define ixGC_CAC_WEIGHT_CU_0 0x32
+#define ixGC_CAC_WEIGHT_CU_1 0x33
+#define ixGC_CAC_WEIGHT_CU_2 0x34
+#define ixGC_CAC_WEIGHT_CU_3 0x35
+#define ixGC_CAC_ACC_CU0 0xba
+#define ixGC_CAC_ACC_CU1 0xbb
+#define ixGC_CAC_ACC_CU2 0xbc
+#define ixGC_CAC_ACC_CU3 0xbd
+#define ixGC_CAC_ACC_CU4 0xbe
+#define ixGC_CAC_ACC_CU5 0xbf
+#define ixGC_CAC_ACC_CU6 0xc0
+#define ixGC_CAC_ACC_CU7 0xc1
+#define ixGC_CAC_OVRD_CU 0xe7
+
+#endif /* SMU_8_0_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_enum.h
new file mode 100644
index 000000000000..e1540c181bf8
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_enum.h
@@ -0,0 +1,1072 @@
+/*
+ * SMU_8_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef SMU_8_0_ENUM_H
+#define SMU_8_0_ENUM_H
+
+typedef enum DebugBlockId {
+ DBG_BLOCK_ID_RESERVED = 0x0,
+ DBG_BLOCK_ID_DBG = 0x1,
+ DBG_BLOCK_ID_VMC = 0x2,
+ DBG_BLOCK_ID_PDMA = 0x3,
+ DBG_BLOCK_ID_CG = 0x4,
+ DBG_BLOCK_ID_SRBM = 0x5,
+ DBG_BLOCK_ID_GRBM = 0x6,
+ DBG_BLOCK_ID_RLC = 0x7,
+ DBG_BLOCK_ID_CSC = 0x8,
+ DBG_BLOCK_ID_SEM = 0x9,
+ DBG_BLOCK_ID_IH = 0xa,
+ DBG_BLOCK_ID_SC = 0xb,
+ DBG_BLOCK_ID_SQ = 0xc,
+ DBG_BLOCK_ID_UVDU = 0xd,
+ DBG_BLOCK_ID_SQA = 0xe,
+ DBG_BLOCK_ID_SDMA0 = 0xf,
+ DBG_BLOCK_ID_SDMA1 = 0x10,
+ DBG_BLOCK_ID_SPIM = 0x11,
+ DBG_BLOCK_ID_GDS = 0x12,
+ DBG_BLOCK_ID_VC0 = 0x13,
+ DBG_BLOCK_ID_VC1 = 0x14,
+ DBG_BLOCK_ID_PA0 = 0x15,
+ DBG_BLOCK_ID_PA1 = 0x16,
+ DBG_BLOCK_ID_CP0 = 0x17,
+ DBG_BLOCK_ID_CP1 = 0x18,
+ DBG_BLOCK_ID_CP2 = 0x19,
+ DBG_BLOCK_ID_XBR = 0x1a,
+ DBG_BLOCK_ID_UVDM = 0x1b,
+ DBG_BLOCK_ID_VGT0 = 0x1c,
+ DBG_BLOCK_ID_VGT1 = 0x1d,
+ DBG_BLOCK_ID_IA = 0x1e,
+ DBG_BLOCK_ID_SXM0 = 0x1f,
+ DBG_BLOCK_ID_SXM1 = 0x20,
+ DBG_BLOCK_ID_SCT0 = 0x21,
+ DBG_BLOCK_ID_SCT1 = 0x22,
+ DBG_BLOCK_ID_SPM0 = 0x23,
+ DBG_BLOCK_ID_SPM1 = 0x24,
+ DBG_BLOCK_ID_UNUSED0 = 0x25,
+ DBG_BLOCK_ID_UNUSED1 = 0x26,
+ DBG_BLOCK_ID_TCAA = 0x27,
+ DBG_BLOCK_ID_TCAB = 0x28,
+ DBG_BLOCK_ID_TCCA = 0x29,
+ DBG_BLOCK_ID_TCCB = 0x2a,
+ DBG_BLOCK_ID_MCC0 = 0x2b,
+ DBG_BLOCK_ID_MCC1 = 0x2c,
+ DBG_BLOCK_ID_MCC2 = 0x2d,
+ DBG_BLOCK_ID_MCC3 = 0x2e,
+ DBG_BLOCK_ID_SXS0 = 0x2f,
+ DBG_BLOCK_ID_SXS1 = 0x30,
+ DBG_BLOCK_ID_SXS2 = 0x31,
+ DBG_BLOCK_ID_SXS3 = 0x32,
+ DBG_BLOCK_ID_SXS4 = 0x33,
+ DBG_BLOCK_ID_SXS5 = 0x34,
+ DBG_BLOCK_ID_SXS6 = 0x35,
+ DBG_BLOCK_ID_SXS7 = 0x36,
+ DBG_BLOCK_ID_SXS8 = 0x37,
+ DBG_BLOCK_ID_SXS9 = 0x38,
+ DBG_BLOCK_ID_BCI0 = 0x39,
+ DBG_BLOCK_ID_BCI1 = 0x3a,
+ DBG_BLOCK_ID_BCI2 = 0x3b,
+ DBG_BLOCK_ID_BCI3 = 0x3c,
+ DBG_BLOCK_ID_MCB = 0x3d,
+ DBG_BLOCK_ID_UNUSED6 = 0x3e,
+ DBG_BLOCK_ID_SQA00 = 0x3f,
+ DBG_BLOCK_ID_SQA01 = 0x40,
+ DBG_BLOCK_ID_SQA02 = 0x41,
+ DBG_BLOCK_ID_SQA10 = 0x42,
+ DBG_BLOCK_ID_SQA11 = 0x43,
+ DBG_BLOCK_ID_SQA12 = 0x44,
+ DBG_BLOCK_ID_UNUSED7 = 0x45,
+ DBG_BLOCK_ID_UNUSED8 = 0x46,
+ DBG_BLOCK_ID_SQB00 = 0x47,
+ DBG_BLOCK_ID_SQB01 = 0x48,
+ DBG_BLOCK_ID_SQB10 = 0x49,
+ DBG_BLOCK_ID_SQB11 = 0x4a,
+ DBG_BLOCK_ID_SQ00 = 0x4b,
+ DBG_BLOCK_ID_SQ01 = 0x4c,
+ DBG_BLOCK_ID_SQ10 = 0x4d,
+ DBG_BLOCK_ID_SQ11 = 0x4e,
+ DBG_BLOCK_ID_CB00 = 0x4f,
+ DBG_BLOCK_ID_CB01 = 0x50,
+ DBG_BLOCK_ID_CB02 = 0x51,
+ DBG_BLOCK_ID_CB03 = 0x52,
+ DBG_BLOCK_ID_CB04 = 0x53,
+ DBG_BLOCK_ID_UNUSED9 = 0x54,
+ DBG_BLOCK_ID_UNUSED10 = 0x55,
+ DBG_BLOCK_ID_UNUSED11 = 0x56,
+ DBG_BLOCK_ID_CB10 = 0x57,
+ DBG_BLOCK_ID_CB11 = 0x58,
+ DBG_BLOCK_ID_CB12 = 0x59,
+ DBG_BLOCK_ID_CB13 = 0x5a,
+ DBG_BLOCK_ID_CB14 = 0x5b,
+ DBG_BLOCK_ID_UNUSED12 = 0x5c,
+ DBG_BLOCK_ID_UNUSED13 = 0x5d,
+ DBG_BLOCK_ID_UNUSED14 = 0x5e,
+ DBG_BLOCK_ID_TCP0 = 0x5f,
+ DBG_BLOCK_ID_TCP1 = 0x60,
+ DBG_BLOCK_ID_TCP2 = 0x61,
+ DBG_BLOCK_ID_TCP3 = 0x62,
+ DBG_BLOCK_ID_TCP4 = 0x63,
+ DBG_BLOCK_ID_TCP5 = 0x64,
+ DBG_BLOCK_ID_TCP6 = 0x65,
+ DBG_BLOCK_ID_TCP7 = 0x66,
+ DBG_BLOCK_ID_TCP8 = 0x67,
+ DBG_BLOCK_ID_TCP9 = 0x68,
+ DBG_BLOCK_ID_TCP10 = 0x69,
+ DBG_BLOCK_ID_TCP11 = 0x6a,
+ DBG_BLOCK_ID_TCP12 = 0x6b,
+ DBG_BLOCK_ID_TCP13 = 0x6c,
+ DBG_BLOCK_ID_TCP14 = 0x6d,
+ DBG_BLOCK_ID_TCP15 = 0x6e,
+ DBG_BLOCK_ID_TCP16 = 0x6f,
+ DBG_BLOCK_ID_TCP17 = 0x70,
+ DBG_BLOCK_ID_TCP18 = 0x71,
+ DBG_BLOCK_ID_TCP19 = 0x72,
+ DBG_BLOCK_ID_TCP20 = 0x73,
+ DBG_BLOCK_ID_TCP21 = 0x74,
+ DBG_BLOCK_ID_TCP22 = 0x75,
+ DBG_BLOCK_ID_TCP23 = 0x76,
+ DBG_BLOCK_ID_TCP_RESERVED0 = 0x77,
+ DBG_BLOCK_ID_TCP_RESERVED1 = 0x78,
+ DBG_BLOCK_ID_TCP_RESERVED2 = 0x79,
+ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a,
+ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b,
+ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c,
+ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d,
+ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e,
+ DBG_BLOCK_ID_DB00 = 0x7f,
+ DBG_BLOCK_ID_DB01 = 0x80,
+ DBG_BLOCK_ID_DB02 = 0x81,
+ DBG_BLOCK_ID_DB03 = 0x82,
+ DBG_BLOCK_ID_DB04 = 0x83,
+ DBG_BLOCK_ID_UNUSED15 = 0x84,
+ DBG_BLOCK_ID_UNUSED16 = 0x85,
+ DBG_BLOCK_ID_UNUSED17 = 0x86,
+ DBG_BLOCK_ID_DB10 = 0x87,
+ DBG_BLOCK_ID_DB11 = 0x88,
+ DBG_BLOCK_ID_DB12 = 0x89,
+ DBG_BLOCK_ID_DB13 = 0x8a,
+ DBG_BLOCK_ID_DB14 = 0x8b,
+ DBG_BLOCK_ID_UNUSED18 = 0x8c,
+ DBG_BLOCK_ID_UNUSED19 = 0x8d,
+ DBG_BLOCK_ID_UNUSED20 = 0x8e,
+ DBG_BLOCK_ID_TCC0 = 0x8f,
+ DBG_BLOCK_ID_TCC1 = 0x90,
+ DBG_BLOCK_ID_TCC2 = 0x91,
+ DBG_BLOCK_ID_TCC3 = 0x92,
+ DBG_BLOCK_ID_TCC4 = 0x93,
+ DBG_BLOCK_ID_TCC5 = 0x94,
+ DBG_BLOCK_ID_TCC6 = 0x95,
+ DBG_BLOCK_ID_TCC7 = 0x96,
+ DBG_BLOCK_ID_SPS00 = 0x97,
+ DBG_BLOCK_ID_SPS01 = 0x98,
+ DBG_BLOCK_ID_SPS02 = 0x99,
+ DBG_BLOCK_ID_SPS10 = 0x9a,
+ DBG_BLOCK_ID_SPS11 = 0x9b,
+ DBG_BLOCK_ID_SPS12 = 0x9c,
+ DBG_BLOCK_ID_UNUSED21 = 0x9d,
+ DBG_BLOCK_ID_UNUSED22 = 0x9e,
+ DBG_BLOCK_ID_TA00 = 0x9f,
+ DBG_BLOCK_ID_TA01 = 0xa0,
+ DBG_BLOCK_ID_TA02 = 0xa1,
+ DBG_BLOCK_ID_TA03 = 0xa2,
+ DBG_BLOCK_ID_TA04 = 0xa3,
+ DBG_BLOCK_ID_TA05 = 0xa4,
+ DBG_BLOCK_ID_TA06 = 0xa5,
+ DBG_BLOCK_ID_TA07 = 0xa6,
+ DBG_BLOCK_ID_TA08 = 0xa7,
+ DBG_BLOCK_ID_TA09 = 0xa8,
+ DBG_BLOCK_ID_TA0A = 0xa9,
+ DBG_BLOCK_ID_TA0B = 0xaa,
+ DBG_BLOCK_ID_UNUSED23 = 0xab,
+ DBG_BLOCK_ID_UNUSED24 = 0xac,
+ DBG_BLOCK_ID_UNUSED25 = 0xad,
+ DBG_BLOCK_ID_UNUSED26 = 0xae,
+ DBG_BLOCK_ID_TA10 = 0xaf,
+ DBG_BLOCK_ID_TA11 = 0xb0,
+ DBG_BLOCK_ID_TA12 = 0xb1,
+ DBG_BLOCK_ID_TA13 = 0xb2,
+ DBG_BLOCK_ID_TA14 = 0xb3,
+ DBG_BLOCK_ID_TA15 = 0xb4,
+ DBG_BLOCK_ID_TA16 = 0xb5,
+ DBG_BLOCK_ID_TA17 = 0xb6,
+ DBG_BLOCK_ID_TA18 = 0xb7,
+ DBG_BLOCK_ID_TA19 = 0xb8,
+ DBG_BLOCK_ID_TA1A = 0xb9,
+ DBG_BLOCK_ID_TA1B = 0xba,
+ DBG_BLOCK_ID_UNUSED27 = 0xbb,
+ DBG_BLOCK_ID_UNUSED28 = 0xbc,
+ DBG_BLOCK_ID_UNUSED29 = 0xbd,
+ DBG_BLOCK_ID_UNUSED30 = 0xbe,
+ DBG_BLOCK_ID_TD00 = 0xbf,
+ DBG_BLOCK_ID_TD01 = 0xc0,
+ DBG_BLOCK_ID_TD02 = 0xc1,
+ DBG_BLOCK_ID_TD03 = 0xc2,
+ DBG_BLOCK_ID_TD04 = 0xc3,
+ DBG_BLOCK_ID_TD05 = 0xc4,
+ DBG_BLOCK_ID_TD06 = 0xc5,
+ DBG_BLOCK_ID_TD07 = 0xc6,
+ DBG_BLOCK_ID_TD08 = 0xc7,
+ DBG_BLOCK_ID_TD09 = 0xc8,
+ DBG_BLOCK_ID_TD0A = 0xc9,
+ DBG_BLOCK_ID_TD0B = 0xca,
+ DBG_BLOCK_ID_UNUSED31 = 0xcb,
+ DBG_BLOCK_ID_UNUSED32 = 0xcc,
+ DBG_BLOCK_ID_UNUSED33 = 0xcd,
+ DBG_BLOCK_ID_UNUSED34 = 0xce,
+ DBG_BLOCK_ID_TD10 = 0xcf,
+ DBG_BLOCK_ID_TD11 = 0xd0,
+ DBG_BLOCK_ID_TD12 = 0xd1,
+ DBG_BLOCK_ID_TD13 = 0xd2,
+ DBG_BLOCK_ID_TD14 = 0xd3,
+ DBG_BLOCK_ID_TD15 = 0xd4,
+ DBG_BLOCK_ID_TD16 = 0xd5,
+ DBG_BLOCK_ID_TD17 = 0xd6,
+ DBG_BLOCK_ID_TD18 = 0xd7,
+ DBG_BLOCK_ID_TD19 = 0xd8,
+ DBG_BLOCK_ID_TD1A = 0xd9,
+ DBG_BLOCK_ID_TD1B = 0xda,
+ DBG_BLOCK_ID_UNUSED35 = 0xdb,
+ DBG_BLOCK_ID_UNUSED36 = 0xdc,
+ DBG_BLOCK_ID_UNUSED37 = 0xdd,
+ DBG_BLOCK_ID_UNUSED38 = 0xde,
+ DBG_BLOCK_ID_LDS00 = 0xdf,
+ DBG_BLOCK_ID_LDS01 = 0xe0,
+ DBG_BLOCK_ID_LDS02 = 0xe1,
+ DBG_BLOCK_ID_LDS03 = 0xe2,
+ DBG_BLOCK_ID_LDS04 = 0xe3,
+ DBG_BLOCK_ID_LDS05 = 0xe4,
+ DBG_BLOCK_ID_LDS06 = 0xe5,
+ DBG_BLOCK_ID_LDS07 = 0xe6,
+ DBG_BLOCK_ID_LDS08 = 0xe7,
+ DBG_BLOCK_ID_LDS09 = 0xe8,
+ DBG_BLOCK_ID_LDS0A = 0xe9,
+ DBG_BLOCK_ID_LDS0B = 0xea,
+ DBG_BLOCK_ID_UNUSED39 = 0xeb,
+ DBG_BLOCK_ID_UNUSED40 = 0xec,
+ DBG_BLOCK_ID_UNUSED41 = 0xed,
+ DBG_BLOCK_ID_UNUSED42 = 0xee,
+ DBG_BLOCK_ID_LDS10 = 0xef,
+ DBG_BLOCK_ID_LDS11 = 0xf0,
+ DBG_BLOCK_ID_LDS12 = 0xf1,
+ DBG_BLOCK_ID_LDS13 = 0xf2,
+ DBG_BLOCK_ID_LDS14 = 0xf3,
+ DBG_BLOCK_ID_LDS15 = 0xf4,
+ DBG_BLOCK_ID_LDS16 = 0xf5,
+ DBG_BLOCK_ID_LDS17 = 0xf6,
+ DBG_BLOCK_ID_LDS18 = 0xf7,
+ DBG_BLOCK_ID_LDS19 = 0xf8,
+ DBG_BLOCK_ID_LDS1A = 0xf9,
+ DBG_BLOCK_ID_LDS1B = 0xfa,
+ DBG_BLOCK_ID_UNUSED43 = 0xfb,
+ DBG_BLOCK_ID_UNUSED44 = 0xfc,
+ DBG_BLOCK_ID_UNUSED45 = 0xfd,
+ DBG_BLOCK_ID_UNUSED46 = 0xfe,
+} DebugBlockId;
+typedef enum DebugBlockId_BY2 {
+ DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
+ DBG_BLOCK_ID_VMC_BY2 = 0x1,
+ DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
+ DBG_BLOCK_ID_GRBM_BY2 = 0x3,
+ DBG_BLOCK_ID_CSC_BY2 = 0x4,
+ DBG_BLOCK_ID_IH_BY2 = 0x5,
+ DBG_BLOCK_ID_SQ_BY2 = 0x6,
+ DBG_BLOCK_ID_UVD_BY2 = 0x7,
+ DBG_BLOCK_ID_SDMA0_BY2 = 0x8,
+ DBG_BLOCK_ID_SPIM_BY2 = 0x9,
+ DBG_BLOCK_ID_VC0_BY2 = 0xa,
+ DBG_BLOCK_ID_PA_BY2 = 0xb,
+ DBG_BLOCK_ID_CP0_BY2 = 0xc,
+ DBG_BLOCK_ID_CP2_BY2 = 0xd,
+ DBG_BLOCK_ID_PC0_BY2 = 0xe,
+ DBG_BLOCK_ID_BCI0_BY2 = 0xf,
+ DBG_BLOCK_ID_SXM0_BY2 = 0x10,
+ DBG_BLOCK_ID_SCT0_BY2 = 0x11,
+ DBG_BLOCK_ID_SPM0_BY2 = 0x12,
+ DBG_BLOCK_ID_BCI2_BY2 = 0x13,
+ DBG_BLOCK_ID_TCA_BY2 = 0x14,
+ DBG_BLOCK_ID_TCCA_BY2 = 0x15,
+ DBG_BLOCK_ID_MCC_BY2 = 0x16,
+ DBG_BLOCK_ID_MCC2_BY2 = 0x17,
+ DBG_BLOCK_ID_MCD_BY2 = 0x18,
+ DBG_BLOCK_ID_MCD2_BY2 = 0x19,
+ DBG_BLOCK_ID_MCD4_BY2 = 0x1a,
+ DBG_BLOCK_ID_MCB_BY2 = 0x1b,
+ DBG_BLOCK_ID_SQA_BY2 = 0x1c,
+ DBG_BLOCK_ID_SQA02_BY2 = 0x1d,
+ DBG_BLOCK_ID_SQA11_BY2 = 0x1e,
+ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f,
+ DBG_BLOCK_ID_SQB_BY2 = 0x20,
+ DBG_BLOCK_ID_SQB10_BY2 = 0x21,
+ DBG_BLOCK_ID_UNUSED10_BY2 = 0x22,
+ DBG_BLOCK_ID_UNUSED12_BY2 = 0x23,
+ DBG_BLOCK_ID_CB_BY2 = 0x24,
+ DBG_BLOCK_ID_CB02_BY2 = 0x25,
+ DBG_BLOCK_ID_CB10_BY2 = 0x26,
+ DBG_BLOCK_ID_CB12_BY2 = 0x27,
+ DBG_BLOCK_ID_SXS_BY2 = 0x28,
+ DBG_BLOCK_ID_SXS2_BY2 = 0x29,
+ DBG_BLOCK_ID_SXS4_BY2 = 0x2a,
+ DBG_BLOCK_ID_SXS6_BY2 = 0x2b,
+ DBG_BLOCK_ID_DB_BY2 = 0x2c,
+ DBG_BLOCK_ID_DB02_BY2 = 0x2d,
+ DBG_BLOCK_ID_DB10_BY2 = 0x2e,
+ DBG_BLOCK_ID_DB12_BY2 = 0x2f,
+ DBG_BLOCK_ID_TCP_BY2 = 0x30,
+ DBG_BLOCK_ID_TCP2_BY2 = 0x31,
+ DBG_BLOCK_ID_TCP4_BY2 = 0x32,
+ DBG_BLOCK_ID_TCP6_BY2 = 0x33,
+ DBG_BLOCK_ID_TCP8_BY2 = 0x34,
+ DBG_BLOCK_ID_TCP10_BY2 = 0x35,
+ DBG_BLOCK_ID_TCP12_BY2 = 0x36,
+ DBG_BLOCK_ID_TCP14_BY2 = 0x37,
+ DBG_BLOCK_ID_TCP16_BY2 = 0x38,
+ DBG_BLOCK_ID_TCP18_BY2 = 0x39,
+ DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
+ DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
+ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
+ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
+ DBG_BLOCK_ID_TCC_BY2 = 0x40,
+ DBG_BLOCK_ID_TCC2_BY2 = 0x41,
+ DBG_BLOCK_ID_TCC4_BY2 = 0x42,
+ DBG_BLOCK_ID_TCC6_BY2 = 0x43,
+ DBG_BLOCK_ID_SPS_BY2 = 0x44,
+ DBG_BLOCK_ID_SPS02_BY2 = 0x45,
+ DBG_BLOCK_ID_SPS11_BY2 = 0x46,
+ DBG_BLOCK_ID_UNUSED14_BY2 = 0x47,
+ DBG_BLOCK_ID_TA_BY2 = 0x48,
+ DBG_BLOCK_ID_TA02_BY2 = 0x49,
+ DBG_BLOCK_ID_TA04_BY2 = 0x4a,
+ DBG_BLOCK_ID_TA06_BY2 = 0x4b,
+ DBG_BLOCK_ID_TA08_BY2 = 0x4c,
+ DBG_BLOCK_ID_TA0A_BY2 = 0x4d,
+ DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e,
+ DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f,
+ DBG_BLOCK_ID_TA10_BY2 = 0x50,
+ DBG_BLOCK_ID_TA12_BY2 = 0x51,
+ DBG_BLOCK_ID_TA14_BY2 = 0x52,
+ DBG_BLOCK_ID_TA16_BY2 = 0x53,
+ DBG_BLOCK_ID_TA18_BY2 = 0x54,
+ DBG_BLOCK_ID_TA1A_BY2 = 0x55,
+ DBG_BLOCK_ID_UNUSED24_BY2 = 0x56,
+ DBG_BLOCK_ID_UNUSED26_BY2 = 0x57,
+ DBG_BLOCK_ID_TD_BY2 = 0x58,
+ DBG_BLOCK_ID_TD02_BY2 = 0x59,
+ DBG_BLOCK_ID_TD04_BY2 = 0x5a,
+ DBG_BLOCK_ID_TD06_BY2 = 0x5b,
+ DBG_BLOCK_ID_TD08_BY2 = 0x5c,
+ DBG_BLOCK_ID_TD0A_BY2 = 0x5d,
+ DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e,
+ DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f,
+ DBG_BLOCK_ID_TD10_BY2 = 0x60,
+ DBG_BLOCK_ID_TD12_BY2 = 0x61,
+ DBG_BLOCK_ID_TD14_BY2 = 0x62,
+ DBG_BLOCK_ID_TD16_BY2 = 0x63,
+ DBG_BLOCK_ID_TD18_BY2 = 0x64,
+ DBG_BLOCK_ID_TD1A_BY2 = 0x65,
+ DBG_BLOCK_ID_UNUSED32_BY2 = 0x66,
+ DBG_BLOCK_ID_UNUSED34_BY2 = 0x67,
+ DBG_BLOCK_ID_LDS_BY2 = 0x68,
+ DBG_BLOCK_ID_LDS02_BY2 = 0x69,
+ DBG_BLOCK_ID_LDS04_BY2 = 0x6a,
+ DBG_BLOCK_ID_LDS06_BY2 = 0x6b,
+ DBG_BLOCK_ID_LDS08_BY2 = 0x6c,
+ DBG_BLOCK_ID_LDS0A_BY2 = 0x6d,
+ DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e,
+ DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f,
+ DBG_BLOCK_ID_LDS10_BY2 = 0x70,
+ DBG_BLOCK_ID_LDS12_BY2 = 0x71,
+ DBG_BLOCK_ID_LDS14_BY2 = 0x72,
+ DBG_BLOCK_ID_LDS16_BY2 = 0x73,
+ DBG_BLOCK_ID_LDS18_BY2 = 0x74,
+ DBG_BLOCK_ID_LDS1A_BY2 = 0x75,
+ DBG_BLOCK_ID_UNUSED40_BY2 = 0x76,
+ DBG_BLOCK_ID_UNUSED42_BY2 = 0x77,
+} DebugBlockId_BY2;
+typedef enum DebugBlockId_BY4 {
+ DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
+ DBG_BLOCK_ID_UNUSED0_BY4 = 0x1,
+ DBG_BLOCK_ID_CSC_BY4 = 0x2,
+ DBG_BLOCK_ID_SQ_BY4 = 0x3,
+ DBG_BLOCK_ID_SDMA0_BY4 = 0x4,
+ DBG_BLOCK_ID_VC0_BY4 = 0x5,
+ DBG_BLOCK_ID_CP0_BY4 = 0x6,
+ DBG_BLOCK_ID_UNUSED1_BY4 = 0x7,
+ DBG_BLOCK_ID_SXM0_BY4 = 0x8,
+ DBG_BLOCK_ID_SPM0_BY4 = 0x9,
+ DBG_BLOCK_ID_TCAA_BY4 = 0xa,
+ DBG_BLOCK_ID_MCC_BY4 = 0xb,
+ DBG_BLOCK_ID_MCD_BY4 = 0xc,
+ DBG_BLOCK_ID_MCD4_BY4 = 0xd,
+ DBG_BLOCK_ID_SQA_BY4 = 0xe,
+ DBG_BLOCK_ID_SQA11_BY4 = 0xf,
+ DBG_BLOCK_ID_SQB_BY4 = 0x10,
+ DBG_BLOCK_ID_UNUSED10_BY4 = 0x11,
+ DBG_BLOCK_ID_CB_BY4 = 0x12,
+ DBG_BLOCK_ID_CB10_BY4 = 0x13,
+ DBG_BLOCK_ID_SXS_BY4 = 0x14,
+ DBG_BLOCK_ID_SXS4_BY4 = 0x15,
+ DBG_BLOCK_ID_DB_BY4 = 0x16,
+ DBG_BLOCK_ID_DB10_BY4 = 0x17,
+ DBG_BLOCK_ID_TCP_BY4 = 0x18,
+ DBG_BLOCK_ID_TCP4_BY4 = 0x19,
+ DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
+ DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
+ DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
+ DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
+ DBG_BLOCK_ID_TCC_BY4 = 0x20,
+ DBG_BLOCK_ID_TCC4_BY4 = 0x21,
+ DBG_BLOCK_ID_SPS_BY4 = 0x22,
+ DBG_BLOCK_ID_SPS11_BY4 = 0x23,
+ DBG_BLOCK_ID_TA_BY4 = 0x24,
+ DBG_BLOCK_ID_TA04_BY4 = 0x25,
+ DBG_BLOCK_ID_TA08_BY4 = 0x26,
+ DBG_BLOCK_ID_UNUSED20_BY4 = 0x27,
+ DBG_BLOCK_ID_TA10_BY4 = 0x28,
+ DBG_BLOCK_ID_TA14_BY4 = 0x29,
+ DBG_BLOCK_ID_TA18_BY4 = 0x2a,
+ DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b,
+ DBG_BLOCK_ID_TD_BY4 = 0x2c,
+ DBG_BLOCK_ID_TD04_BY4 = 0x2d,
+ DBG_BLOCK_ID_TD08_BY4 = 0x2e,
+ DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f,
+ DBG_BLOCK_ID_TD10_BY4 = 0x30,
+ DBG_BLOCK_ID_TD14_BY4 = 0x31,
+ DBG_BLOCK_ID_TD18_BY4 = 0x32,
+ DBG_BLOCK_ID_UNUSED32_BY4 = 0x33,
+ DBG_BLOCK_ID_LDS_BY4 = 0x34,
+ DBG_BLOCK_ID_LDS04_BY4 = 0x35,
+ DBG_BLOCK_ID_LDS08_BY4 = 0x36,
+ DBG_BLOCK_ID_UNUSED36_BY4 = 0x37,
+ DBG_BLOCK_ID_LDS10_BY4 = 0x38,
+ DBG_BLOCK_ID_LDS14_BY4 = 0x39,
+ DBG_BLOCK_ID_LDS18_BY4 = 0x3a,
+ DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b,
+} DebugBlockId_BY4;
+typedef enum DebugBlockId_BY8 {
+ DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
+ DBG_BLOCK_ID_CSC_BY8 = 0x1,
+ DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
+ DBG_BLOCK_ID_CP0_BY8 = 0x3,
+ DBG_BLOCK_ID_SXM0_BY8 = 0x4,
+ DBG_BLOCK_ID_TCA_BY8 = 0x5,
+ DBG_BLOCK_ID_MCD_BY8 = 0x6,
+ DBG_BLOCK_ID_SQA_BY8 = 0x7,
+ DBG_BLOCK_ID_SQB_BY8 = 0x8,
+ DBG_BLOCK_ID_CB_BY8 = 0x9,
+ DBG_BLOCK_ID_SXS_BY8 = 0xa,
+ DBG_BLOCK_ID_DB_BY8 = 0xb,
+ DBG_BLOCK_ID_TCP_BY8 = 0xc,
+ DBG_BLOCK_ID_TCP8_BY8 = 0xd,
+ DBG_BLOCK_ID_TCP16_BY8 = 0xe,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
+ DBG_BLOCK_ID_TCC_BY8 = 0x10,
+ DBG_BLOCK_ID_SPS_BY8 = 0x11,
+ DBG_BLOCK_ID_TA_BY8 = 0x12,
+ DBG_BLOCK_ID_TA08_BY8 = 0x13,
+ DBG_BLOCK_ID_TA10_BY8 = 0x14,
+ DBG_BLOCK_ID_TA18_BY8 = 0x15,
+ DBG_BLOCK_ID_TD_BY8 = 0x16,
+ DBG_BLOCK_ID_TD08_BY8 = 0x17,
+ DBG_BLOCK_ID_TD10_BY8 = 0x18,
+ DBG_BLOCK_ID_TD18_BY8 = 0x19,
+ DBG_BLOCK_ID_LDS_BY8 = 0x1a,
+ DBG_BLOCK_ID_LDS08_BY8 = 0x1b,
+ DBG_BLOCK_ID_LDS10_BY8 = 0x1c,
+ DBG_BLOCK_ID_LDS18_BY8 = 0x1d,
+} DebugBlockId_BY8;
+typedef enum DebugBlockId_BY16 {
+ DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
+ DBG_BLOCK_ID_SDMA0_BY16 = 0x1,
+ DBG_BLOCK_ID_SXM_BY16 = 0x2,
+ DBG_BLOCK_ID_MCD_BY16 = 0x3,
+ DBG_BLOCK_ID_SQB_BY16 = 0x4,
+ DBG_BLOCK_ID_SXS_BY16 = 0x5,
+ DBG_BLOCK_ID_TCP_BY16 = 0x6,
+ DBG_BLOCK_ID_TCP16_BY16 = 0x7,
+ DBG_BLOCK_ID_TCC_BY16 = 0x8,
+ DBG_BLOCK_ID_TA_BY16 = 0x9,
+ DBG_BLOCK_ID_TA10_BY16 = 0xa,
+ DBG_BLOCK_ID_TD_BY16 = 0xb,
+ DBG_BLOCK_ID_TD10_BY16 = 0xc,
+ DBG_BLOCK_ID_LDS_BY16 = 0xd,
+ DBG_BLOCK_ID_LDS10_BY16 = 0xe,
+} DebugBlockId_BY16;
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0x0,
+ ENDIAN_8IN16 = 0x1,
+ ENDIAN_8IN32 = 0x2,
+ ENDIAN_8IN64 = 0x3,
+} SurfaceEndian;
+typedef enum ArrayMode {
+ ARRAY_LINEAR_GENERAL = 0x0,
+ ARRAY_LINEAR_ALIGNED = 0x1,
+ ARRAY_1D_TILED_THIN1 = 0x2,
+ ARRAY_1D_TILED_THICK = 0x3,
+ ARRAY_2D_TILED_THIN1 = 0x4,
+ ARRAY_PRT_TILED_THIN1 = 0x5,
+ ARRAY_PRT_2D_TILED_THIN1 = 0x6,
+ ARRAY_2D_TILED_THICK = 0x7,
+ ARRAY_2D_TILED_XTHICK = 0x8,
+ ARRAY_PRT_TILED_THICK = 0x9,
+ ARRAY_PRT_2D_TILED_THICK = 0xa,
+ ARRAY_PRT_3D_TILED_THIN1 = 0xb,
+ ARRAY_3D_TILED_THIN1 = 0xc,
+ ARRAY_3D_TILED_THICK = 0xd,
+ ARRAY_3D_TILED_XTHICK = 0xe,
+ ARRAY_PRT_3D_TILED_THICK = 0xf,
+} ArrayMode;
+typedef enum PipeTiling {
+ CONFIG_1_PIPE = 0x0,
+ CONFIG_2_PIPE = 0x1,
+ CONFIG_4_PIPE = 0x2,
+ CONFIG_8_PIPE = 0x3,
+} PipeTiling;
+typedef enum BankTiling {
+ CONFIG_4_BANK = 0x0,
+ CONFIG_8_BANK = 0x1,
+} BankTiling;
+typedef enum GroupInterleave {
+ CONFIG_256B_GROUP = 0x0,
+ CONFIG_512B_GROUP = 0x1,
+} GroupInterleave;
+typedef enum RowTiling {
+ CONFIG_1KB_ROW = 0x0,
+ CONFIG_2KB_ROW = 0x1,
+ CONFIG_4KB_ROW = 0x2,
+ CONFIG_8KB_ROW = 0x3,
+ CONFIG_1KB_ROW_OPT = 0x4,
+ CONFIG_2KB_ROW_OPT = 0x5,
+ CONFIG_4KB_ROW_OPT = 0x6,
+ CONFIG_8KB_ROW_OPT = 0x7,
+} RowTiling;
+typedef enum BankSwapBytes {
+ CONFIG_128B_SWAPS = 0x0,
+ CONFIG_256B_SWAPS = 0x1,
+ CONFIG_512B_SWAPS = 0x2,
+ CONFIG_1KB_SWAPS = 0x3,
+} BankSwapBytes;
+typedef enum SampleSplitBytes {
+ CONFIG_1KB_SPLIT = 0x0,
+ CONFIG_2KB_SPLIT = 0x1,
+ CONFIG_4KB_SPLIT = 0x2,
+ CONFIG_8KB_SPLIT = 0x3,
+} SampleSplitBytes;
+typedef enum NumPipes {
+ ADDR_CONFIG_1_PIPE = 0x0,
+ ADDR_CONFIG_2_PIPE = 0x1,
+ ADDR_CONFIG_4_PIPE = 0x2,
+ ADDR_CONFIG_8_PIPE = 0x3,
+} NumPipes;
+typedef enum PipeInterleaveSize {
+ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
+ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
+} PipeInterleaveSize;
+typedef enum BankInterleaveSize {
+ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
+ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
+ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
+ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
+} BankInterleaveSize;
+typedef enum NumShaderEngines {
+ ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
+ ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
+} NumShaderEngines;
+typedef enum ShaderEngineTileSize {
+ ADDR_CONFIG_SE_TILE_16 = 0x0,
+ ADDR_CONFIG_SE_TILE_32 = 0x1,
+} ShaderEngineTileSize;
+typedef enum NumGPUs {
+ ADDR_CONFIG_1_GPU = 0x0,
+ ADDR_CONFIG_2_GPU = 0x1,
+ ADDR_CONFIG_4_GPU = 0x2,
+} NumGPUs;
+typedef enum MultiGPUTileSize {
+ ADDR_CONFIG_GPU_TILE_16 = 0x0,
+ ADDR_CONFIG_GPU_TILE_32 = 0x1,
+ ADDR_CONFIG_GPU_TILE_64 = 0x2,
+ ADDR_CONFIG_GPU_TILE_128 = 0x3,
+} MultiGPUTileSize;
+typedef enum RowSize {
+ ADDR_CONFIG_1KB_ROW = 0x0,
+ ADDR_CONFIG_2KB_ROW = 0x1,
+ ADDR_CONFIG_4KB_ROW = 0x2,
+} RowSize;
+typedef enum NumLowerPipes {
+ ADDR_CONFIG_1_LOWER_PIPES = 0x0,
+ ADDR_CONFIG_2_LOWER_PIPES = 0x1,
+} NumLowerPipes;
+typedef enum ColorTransform {
+ DCC_CT_AUTO = 0x0,
+ DCC_CT_NONE = 0x1,
+ ABGR_TO_A_BG_G_RB = 0x2,
+ BGRA_TO_BG_G_RB_A = 0x3,
+} ColorTransform;
+typedef enum CompareRef {
+ REF_NEVER = 0x0,
+ REF_LESS = 0x1,
+ REF_EQUAL = 0x2,
+ REF_LEQUAL = 0x3,
+ REF_GREATER = 0x4,
+ REF_NOTEQUAL = 0x5,
+ REF_GEQUAL = 0x6,
+ REF_ALWAYS = 0x7,
+} CompareRef;
+typedef enum ReadSize {
+ READ_256_BITS = 0x0,
+ READ_512_BITS = 0x1,
+} ReadSize;
+typedef enum DepthFormat {
+ DEPTH_INVALID = 0x0,
+ DEPTH_16 = 0x1,
+ DEPTH_X8_24 = 0x2,
+ DEPTH_8_24 = 0x3,
+ DEPTH_X8_24_FLOAT = 0x4,
+ DEPTH_8_24_FLOAT = 0x5,
+ DEPTH_32_FLOAT = 0x6,
+ DEPTH_X24_8_32_FLOAT = 0x7,
+} DepthFormat;
+typedef enum ZFormat {
+ Z_INVALID = 0x0,
+ Z_16 = 0x1,
+ Z_24 = 0x2,
+ Z_32_FLOAT = 0x3,
+} ZFormat;
+typedef enum StencilFormat {
+ STENCIL_INVALID = 0x0,
+ STENCIL_8 = 0x1,
+} StencilFormat;
+typedef enum CmaskMode {
+ CMASK_CLEAR_NONE = 0x0,
+ CMASK_CLEAR_ONE = 0x1,
+ CMASK_CLEAR_ALL = 0x2,
+ CMASK_ANY_EXPANDED = 0x3,
+ CMASK_ALPHA0_FRAG1 = 0x4,
+ CMASK_ALPHA0_FRAG2 = 0x5,
+ CMASK_ALPHA0_FRAG4 = 0x6,
+ CMASK_ALPHA0_FRAGS = 0x7,
+ CMASK_ALPHA1_FRAG1 = 0x8,
+ CMASK_ALPHA1_FRAG2 = 0x9,
+ CMASK_ALPHA1_FRAG4 = 0xa,
+ CMASK_ALPHA1_FRAGS = 0xb,
+ CMASK_ALPHAX_FRAG1 = 0xc,
+ CMASK_ALPHAX_FRAG2 = 0xd,
+ CMASK_ALPHAX_FRAG4 = 0xe,
+ CMASK_ALPHAX_FRAGS = 0xf,
+} CmaskMode;
+typedef enum QuadExportFormat {
+ EXPORT_UNUSED = 0x0,
+ EXPORT_32_R = 0x1,
+ EXPORT_32_GR = 0x2,
+ EXPORT_32_AR = 0x3,
+ EXPORT_FP16_ABGR = 0x4,
+ EXPORT_UNSIGNED16_ABGR = 0x5,
+ EXPORT_SIGNED16_ABGR = 0x6,
+ EXPORT_32_ABGR = 0x7,
+} QuadExportFormat;
+typedef enum QuadExportFormatOld {
+ EXPORT_4P_32BPC_ABGR = 0x0,
+ EXPORT_4P_16BPC_ABGR = 0x1,
+ EXPORT_4P_32BPC_GR = 0x2,
+ EXPORT_4P_32BPC_AR = 0x3,
+ EXPORT_2P_32BPC_ABGR = 0x4,
+ EXPORT_8P_32BPC_R = 0x5,
+} QuadExportFormatOld;
+typedef enum ColorFormat {
+ COLOR_INVALID = 0x0,
+ COLOR_8 = 0x1,
+ COLOR_16 = 0x2,
+ COLOR_8_8 = 0x3,
+ COLOR_32 = 0x4,
+ COLOR_16_16 = 0x5,
+ COLOR_10_11_11 = 0x6,
+ COLOR_11_11_10 = 0x7,
+ COLOR_10_10_10_2 = 0x8,
+ COLOR_2_10_10_10 = 0x9,
+ COLOR_8_8_8_8 = 0xa,
+ COLOR_32_32 = 0xb,
+ COLOR_16_16_16_16 = 0xc,
+ COLOR_RESERVED_13 = 0xd,
+ COLOR_32_32_32_32 = 0xe,
+ COLOR_RESERVED_15 = 0xf,
+ COLOR_5_6_5 = 0x10,
+ COLOR_1_5_5_5 = 0x11,
+ COLOR_5_5_5_1 = 0x12,
+ COLOR_4_4_4_4 = 0x13,
+ COLOR_8_24 = 0x14,
+ COLOR_24_8 = 0x15,
+ COLOR_X24_8_32_FLOAT = 0x16,
+ COLOR_RESERVED_23 = 0x17,
+} ColorFormat;
+typedef enum SurfaceFormat {
+ FMT_INVALID = 0x0,
+ FMT_8 = 0x1,
+ FMT_16 = 0x2,
+ FMT_8_8 = 0x3,
+ FMT_32 = 0x4,
+ FMT_16_16 = 0x5,
+ FMT_10_11_11 = 0x6,
+ FMT_11_11_10 = 0x7,
+ FMT_10_10_10_2 = 0x8,
+ FMT_2_10_10_10 = 0x9,
+ FMT_8_8_8_8 = 0xa,
+ FMT_32_32 = 0xb,
+ FMT_16_16_16_16 = 0xc,
+ FMT_32_32_32 = 0xd,
+ FMT_32_32_32_32 = 0xe,
+ FMT_RESERVED_4 = 0xf,
+ FMT_5_6_5 = 0x10,
+ FMT_1_5_5_5 = 0x11,
+ FMT_5_5_5_1 = 0x12,
+ FMT_4_4_4_4 = 0x13,
+ FMT_8_24 = 0x14,
+ FMT_24_8 = 0x15,
+ FMT_X24_8_32_FLOAT = 0x16,
+ FMT_RESERVED_33 = 0x17,
+ FMT_11_11_10_FLOAT = 0x18,
+ FMT_16_FLOAT = 0x19,
+ FMT_32_FLOAT = 0x1a,
+ FMT_16_16_FLOAT = 0x1b,
+ FMT_8_24_FLOAT = 0x1c,
+ FMT_24_8_FLOAT = 0x1d,
+ FMT_32_32_FLOAT = 0x1e,
+ FMT_10_11_11_FLOAT = 0x1f,
+ FMT_16_16_16_16_FLOAT = 0x20,
+ FMT_3_3_2 = 0x21,
+ FMT_6_5_5 = 0x22,
+ FMT_32_32_32_32_FLOAT = 0x23,
+ FMT_RESERVED_36 = 0x24,
+ FMT_1 = 0x25,
+ FMT_1_REVERSED = 0x26,
+ FMT_GB_GR = 0x27,
+ FMT_BG_RG = 0x28,
+ FMT_32_AS_8 = 0x29,
+ FMT_32_AS_8_8 = 0x2a,
+ FMT_5_9_9_9_SHAREDEXP = 0x2b,
+ FMT_8_8_8 = 0x2c,
+ FMT_16_16_16 = 0x2d,
+ FMT_16_16_16_FLOAT = 0x2e,
+ FMT_4_4 = 0x2f,
+ FMT_32_32_32_FLOAT = 0x30,
+ FMT_BC1 = 0x31,
+ FMT_BC2 = 0x32,
+ FMT_BC3 = 0x33,
+ FMT_BC4 = 0x34,
+ FMT_BC5 = 0x35,
+ FMT_BC6 = 0x36,
+ FMT_BC7 = 0x37,
+ FMT_32_AS_32_32_32_32 = 0x38,
+ FMT_APC3 = 0x39,
+ FMT_APC4 = 0x3a,
+ FMT_APC5 = 0x3b,
+ FMT_APC6 = 0x3c,
+ FMT_APC7 = 0x3d,
+ FMT_CTX1 = 0x3e,
+ FMT_RESERVED_63 = 0x3f,
+} SurfaceFormat;
+typedef enum BUF_DATA_FORMAT {
+ BUF_DATA_FORMAT_INVALID = 0x0,
+ BUF_DATA_FORMAT_8 = 0x1,
+ BUF_DATA_FORMAT_16 = 0x2,
+ BUF_DATA_FORMAT_8_8 = 0x3,
+ BUF_DATA_FORMAT_32 = 0x4,
+ BUF_DATA_FORMAT_16_16 = 0x5,
+ BUF_DATA_FORMAT_10_11_11 = 0x6,
+ BUF_DATA_FORMAT_11_11_10 = 0x7,
+ BUF_DATA_FORMAT_10_10_10_2 = 0x8,
+ BUF_DATA_FORMAT_2_10_10_10 = 0x9,
+ BUF_DATA_FORMAT_8_8_8_8 = 0xa,
+ BUF_DATA_FORMAT_32_32 = 0xb,
+ BUF_DATA_FORMAT_16_16_16_16 = 0xc,
+ BUF_DATA_FORMAT_32_32_32 = 0xd,
+ BUF_DATA_FORMAT_32_32_32_32 = 0xe,
+ BUF_DATA_FORMAT_RESERVED_15 = 0xf,
+} BUF_DATA_FORMAT;
+typedef enum IMG_DATA_FORMAT {
+ IMG_DATA_FORMAT_INVALID = 0x0,
+ IMG_DATA_FORMAT_8 = 0x1,
+ IMG_DATA_FORMAT_16 = 0x2,
+ IMG_DATA_FORMAT_8_8 = 0x3,
+ IMG_DATA_FORMAT_32 = 0x4,
+ IMG_DATA_FORMAT_16_16 = 0x5,
+ IMG_DATA_FORMAT_10_11_11 = 0x6,
+ IMG_DATA_FORMAT_11_11_10 = 0x7,
+ IMG_DATA_FORMAT_10_10_10_2 = 0x8,
+ IMG_DATA_FORMAT_2_10_10_10 = 0x9,
+ IMG_DATA_FORMAT_8_8_8_8 = 0xa,
+ IMG_DATA_FORMAT_32_32 = 0xb,
+ IMG_DATA_FORMAT_16_16_16_16 = 0xc,
+ IMG_DATA_FORMAT_32_32_32 = 0xd,
+ IMG_DATA_FORMAT_32_32_32_32 = 0xe,
+ IMG_DATA_FORMAT_RESERVED_15 = 0xf,
+ IMG_DATA_FORMAT_5_6_5 = 0x10,
+ IMG_DATA_FORMAT_1_5_5_5 = 0x11,
+ IMG_DATA_FORMAT_5_5_5_1 = 0x12,
+ IMG_DATA_FORMAT_4_4_4_4 = 0x13,
+ IMG_DATA_FORMAT_8_24 = 0x14,
+ IMG_DATA_FORMAT_24_8 = 0x15,
+ IMG_DATA_FORMAT_X24_8_32 = 0x16,
+ IMG_DATA_FORMAT_RESERVED_23 = 0x17,
+ IMG_DATA_FORMAT_RESERVED_24 = 0x18,
+ IMG_DATA_FORMAT_RESERVED_25 = 0x19,
+ IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
+ IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
+ IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
+ IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
+ IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
+ IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
+ IMG_DATA_FORMAT_GB_GR = 0x20,
+ IMG_DATA_FORMAT_BG_RG = 0x21,
+ IMG_DATA_FORMAT_5_9_9_9 = 0x22,
+ IMG_DATA_FORMAT_BC1 = 0x23,
+ IMG_DATA_FORMAT_BC2 = 0x24,
+ IMG_DATA_FORMAT_BC3 = 0x25,
+ IMG_DATA_FORMAT_BC4 = 0x26,
+ IMG_DATA_FORMAT_BC5 = 0x27,
+ IMG_DATA_FORMAT_BC6 = 0x28,
+ IMG_DATA_FORMAT_BC7 = 0x29,
+ IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
+ IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
+ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
+ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
+ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
+ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
+ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
+ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
+ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
+ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
+ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
+ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
+ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
+ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
+ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
+ IMG_DATA_FORMAT_4_4 = 0x39,
+ IMG_DATA_FORMAT_6_5_5 = 0x3a,
+ IMG_DATA_FORMAT_1 = 0x3b,
+ IMG_DATA_FORMAT_1_REVERSED = 0x3c,
+ IMG_DATA_FORMAT_32_AS_8 = 0x3d,
+ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
+ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
+} IMG_DATA_FORMAT;
+typedef enum BUF_NUM_FORMAT {
+ BUF_NUM_FORMAT_UNORM = 0x0,
+ BUF_NUM_FORMAT_SNORM = 0x1,
+ BUF_NUM_FORMAT_USCALED = 0x2,
+ BUF_NUM_FORMAT_SSCALED = 0x3,
+ BUF_NUM_FORMAT_UINT = 0x4,
+ BUF_NUM_FORMAT_SINT = 0x5,
+ BUF_NUM_FORMAT_RESERVED_6 = 0x6,
+ BUF_NUM_FORMAT_FLOAT = 0x7,
+} BUF_NUM_FORMAT;
+typedef enum IMG_NUM_FORMAT {
+ IMG_NUM_FORMAT_UNORM = 0x0,
+ IMG_NUM_FORMAT_SNORM = 0x1,
+ IMG_NUM_FORMAT_USCALED = 0x2,
+ IMG_NUM_FORMAT_SSCALED = 0x3,
+ IMG_NUM_FORMAT_UINT = 0x4,
+ IMG_NUM_FORMAT_SINT = 0x5,
+ IMG_NUM_FORMAT_RESERVED_6 = 0x6,
+ IMG_NUM_FORMAT_FLOAT = 0x7,
+ IMG_NUM_FORMAT_RESERVED_8 = 0x8,
+ IMG_NUM_FORMAT_SRGB = 0x9,
+ IMG_NUM_FORMAT_RESERVED_10 = 0xa,
+ IMG_NUM_FORMAT_RESERVED_11 = 0xb,
+ IMG_NUM_FORMAT_RESERVED_12 = 0xc,
+ IMG_NUM_FORMAT_RESERVED_13 = 0xd,
+ IMG_NUM_FORMAT_RESERVED_14 = 0xe,
+ IMG_NUM_FORMAT_RESERVED_15 = 0xf,
+} IMG_NUM_FORMAT;
+typedef enum TileType {
+ ARRAY_COLOR_TILE = 0x0,
+ ARRAY_DEPTH_TILE = 0x1,
+} TileType;
+typedef enum NonDispTilingOrder {
+ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
+ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
+} NonDispTilingOrder;
+typedef enum MicroTileMode {
+ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
+ ADDR_SURF_THIN_MICRO_TILING = 0x1,
+ ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
+ ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
+ ADDR_SURF_THICK_MICRO_TILING = 0x4,
+} MicroTileMode;
+typedef enum TileSplit {
+ ADDR_SURF_TILE_SPLIT_64B = 0x0,
+ ADDR_SURF_TILE_SPLIT_128B = 0x1,
+ ADDR_SURF_TILE_SPLIT_256B = 0x2,
+ ADDR_SURF_TILE_SPLIT_512B = 0x3,
+ ADDR_SURF_TILE_SPLIT_1KB = 0x4,
+ ADDR_SURF_TILE_SPLIT_2KB = 0x5,
+ ADDR_SURF_TILE_SPLIT_4KB = 0x6,
+} TileSplit;
+typedef enum SampleSplit {
+ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
+ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
+ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
+ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
+} SampleSplit;
+typedef enum PipeConfig {
+ ADDR_SURF_P2 = 0x0,
+ ADDR_SURF_P2_RESERVED0 = 0x1,
+ ADDR_SURF_P2_RESERVED1 = 0x2,
+ ADDR_SURF_P2_RESERVED2 = 0x3,
+ ADDR_SURF_P4_8x16 = 0x4,
+ ADDR_SURF_P4_16x16 = 0x5,
+ ADDR_SURF_P4_16x32 = 0x6,
+ ADDR_SURF_P4_32x32 = 0x7,
+ ADDR_SURF_P8_16x16_8x16 = 0x8,
+ ADDR_SURF_P8_16x32_8x16 = 0x9,
+ ADDR_SURF_P8_32x32_8x16 = 0xa,
+ ADDR_SURF_P8_16x32_16x16 = 0xb,
+ ADDR_SURF_P8_32x32_16x16 = 0xc,
+ ADDR_SURF_P8_32x32_16x32 = 0xd,
+ ADDR_SURF_P8_32x64_32x32 = 0xe,
+ ADDR_SURF_P8_RESERVED0 = 0xf,
+ ADDR_SURF_P16_32x32_8x16 = 0x10,
+ ADDR_SURF_P16_32x32_16x16 = 0x11,
+} PipeConfig;
+typedef enum NumBanks {
+ ADDR_SURF_2_BANK = 0x0,
+ ADDR_SURF_4_BANK = 0x1,
+ ADDR_SURF_8_BANK = 0x2,
+ ADDR_SURF_16_BANK = 0x3,
+} NumBanks;
+typedef enum BankWidth {
+ ADDR_SURF_BANK_WIDTH_1 = 0x0,
+ ADDR_SURF_BANK_WIDTH_2 = 0x1,
+ ADDR_SURF_BANK_WIDTH_4 = 0x2,
+ ADDR_SURF_BANK_WIDTH_8 = 0x3,
+} BankWidth;
+typedef enum BankHeight {
+ ADDR_SURF_BANK_HEIGHT_1 = 0x0,
+ ADDR_SURF_BANK_HEIGHT_2 = 0x1,
+ ADDR_SURF_BANK_HEIGHT_4 = 0x2,
+ ADDR_SURF_BANK_HEIGHT_8 = 0x3,
+} BankHeight;
+typedef enum BankWidthHeight {
+ ADDR_SURF_BANK_WH_1 = 0x0,
+ ADDR_SURF_BANK_WH_2 = 0x1,
+ ADDR_SURF_BANK_WH_4 = 0x2,
+ ADDR_SURF_BANK_WH_8 = 0x3,
+} BankWidthHeight;
+typedef enum MacroTileAspect {
+ ADDR_SURF_MACRO_ASPECT_1 = 0x0,
+ ADDR_SURF_MACRO_ASPECT_2 = 0x1,
+ ADDR_SURF_MACRO_ASPECT_4 = 0x2,
+ ADDR_SURF_MACRO_ASPECT_8 = 0x3,
+} MacroTileAspect;
+typedef enum GATCL1RequestType {
+ GATCL1_TYPE_NORMAL = 0x0,
+ GATCL1_TYPE_SHOOTDOWN = 0x1,
+ GATCL1_TYPE_BYPASS = 0x2,
+} GATCL1RequestType;
+typedef enum TCC_CACHE_POLICIES {
+ TCC_CACHE_POLICY_LRU = 0x0,
+ TCC_CACHE_POLICY_STREAM = 0x1,
+} TCC_CACHE_POLICIES;
+typedef enum MTYPE {
+ MTYPE_NC_NV = 0x0,
+ MTYPE_NC = 0x1,
+ MTYPE_CC = 0x2,
+ MTYPE_UC = 0x3,
+} MTYPE;
+typedef enum PERFMON_COUNTER_MODE {
+ PERFMON_COUNTER_MODE_ACCUM = 0x0,
+ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
+ PERFMON_COUNTER_MODE_MAX = 0x2,
+ PERFMON_COUNTER_MODE_DIRTY = 0x3,
+ PERFMON_COUNTER_MODE_SAMPLE = 0x4,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
+ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
+ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
+ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
+ PERFMON_COUNTER_MODE_RESERVED = 0xf,
+} PERFMON_COUNTER_MODE;
+typedef enum PERFMON_SPM_MODE {
+ PERFMON_SPM_MODE_OFF = 0x0,
+ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
+ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
+ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
+ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
+ PERFMON_SPM_MODE_RESERVED_5 = 0x5,
+ PERFMON_SPM_MODE_RESERVED_6 = 0x6,
+ PERFMON_SPM_MODE_RESERVED_7 = 0x7,
+ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
+ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
+ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
+} PERFMON_SPM_MODE;
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0x0,
+ ARRAY_TILED = 0x1,
+} SurfaceTiling;
+typedef enum SurfaceArray {
+ ARRAY_1D = 0x0,
+ ARRAY_2D = 0x1,
+ ARRAY_3D = 0x2,
+ ARRAY_3D_SLICE = 0x3,
+} SurfaceArray;
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0x0,
+ ARRAY_2D_COLOR = 0x1,
+ ARRAY_3D_SLICE_COLOR = 0x3,
+} ColorArray;
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0x0,
+ ARRAY_2D_DEPTH = 0x1,
+} DepthArray;
+typedef enum ENUM_NUM_SIMD_PER_CU {
+ NUM_SIMD_PER_CU = 0x4,
+} ENUM_NUM_SIMD_PER_CU;
+typedef enum MEM_PWR_FORCE_CTRL {
+ NO_FORCE_REQUEST = 0x0,
+ FORCE_LIGHT_SLEEP_REQUEST = 0x1,
+ FORCE_DEEP_SLEEP_REQUEST = 0x2,
+ FORCE_SHUT_DOWN_REQUEST = 0x3,
+} MEM_PWR_FORCE_CTRL;
+typedef enum MEM_PWR_FORCE_CTRL2 {
+ NO_FORCE_REQ = 0x0,
+ FORCE_LIGHT_SLEEP_REQ = 0x1,
+} MEM_PWR_FORCE_CTRL2;
+typedef enum MEM_PWR_DIS_CTRL {
+ ENABLE_MEM_PWR_CTRL = 0x0,
+ DISABLE_MEM_PWR_CTRL = 0x1,
+} MEM_PWR_DIS_CTRL;
+typedef enum MEM_PWR_SEL_CTRL {
+ DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
+ DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
+ DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
+} MEM_PWR_SEL_CTRL;
+typedef enum MEM_PWR_SEL_CTRL2 {
+ DYNAMIC_DEEP_SLEEP_EN = 0x0,
+ DYNAMIC_LIGHT_SLEEP_EN = 0x1,
+} MEM_PWR_SEL_CTRL2;
+#define CG_SRBM_START_ADDR 0x600
+#define CG_SRBM_END_ADDR 0x8ff
+#define CG_SRBM_DEC0_START_ADDR 0x200
+#define CG_SRBM_DEC0_END_ADDR 0x2ff
+
+#endif /* SMU_8_0_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_sh_mask.h
new file mode 100644
index 000000000000..3dbe24df7e02
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_sh_mask.h
@@ -0,0 +1,2964 @@
+/*
+ * SMU_8_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef SMU_8_0_SH_MASK_H
+#define SMU_8_0_SH_MASK_H
+
+#define THM_TCON_CSR_CONFIG__TCC_ADDR_MASK 0x3ff
+#define THM_TCON_CSR_CONFIG__TCC_ADDR__SHIFT 0x0
+#define THM_TCON_CSR_CONFIG__TCC_READ_OP_MASK 0x400
+#define THM_TCON_CSR_CONFIG__TCC_READ_OP__SHIFT 0xa
+#define THM_TCON_CSR_DATA__TCC_DATA_MASK 0xfff
+#define THM_TCON_CSR_DATA__TCC_DATA__SHIFT 0x0
+#define THM_TCON_CSR_DATA__TCC_REQ_DONE_MASK 0x1000
+#define THM_TCON_CSR_DATA__TCC_REQ_DONE__SHIFT 0xc
+#define THM_TCON_HTC__HTC_EN_MASK 0x1
+#define THM_TCON_HTC__HTC_EN__SHIFT 0x0
+#define THM_TCON_HTC__RSVD0_MASK 0x2
+#define THM_TCON_HTC__RSVD0__SHIFT 0x1
+#define THM_TCON_HTC__HTC_P_STATE_EN_MASK 0x4
+#define THM_TCON_HTC__HTC_P_STATE_EN__SHIFT 0x2
+#define THM_TCON_HTC__RSVD1_MASK 0x8
+#define THM_TCON_HTC__RSVD1__SHIFT 0x3
+#define THM_TCON_HTC__HTC_ACTIVE_MASK 0x10
+#define THM_TCON_HTC__HTC_ACTIVE__SHIFT 0x4
+#define THM_TCON_HTC__HTC_ACTIVE_LOG_MASK 0x20
+#define THM_TCON_HTC__HTC_ACTIVE_LOG__SHIFT 0x5
+#define THM_TCON_HTC__HTC_APIC_HI_EN_MASK 0x40
+#define THM_TCON_HTC__HTC_APIC_HI_EN__SHIFT 0x6
+#define THM_TCON_HTC__HTC_APIC_LO_EN_MASK 0x80
+#define THM_TCON_HTC__HTC_APIC_LO_EN__SHIFT 0x7
+#define THM_TCON_HTC__HTC_DIAG_MASK 0x100
+#define THM_TCON_HTC__HTC_DIAG__SHIFT 0x8
+#define THM_TCON_HTC__DIS_PROCHOT_PIN_MASK 0x200
+#define THM_TCON_HTC__DIS_PROCHOT_PIN__SHIFT 0x9
+#define THM_TCON_HTC__HTC_TO_GNB_EN_MASK 0x400
+#define THM_TCON_HTC__HTC_TO_GNB_EN__SHIFT 0xa
+#define THM_TCON_HTC__PROCHOT_TO_GNB_EN_MASK 0x800
+#define THM_TCON_HTC__PROCHOT_TO_GNB_EN__SHIFT 0xb
+#define THM_TCON_HTC__RSVD2_MASK 0xf000
+#define THM_TCON_HTC__RSVD2__SHIFT 0xc
+#define THM_TCON_HTC__HTC_TMP_LMT_MASK 0x7f0000
+#define THM_TCON_HTC__HTC_TMP_LMT__SHIFT 0x10
+#define THM_TCON_HTC__HTC_SLEW_SEL_MASK 0x800000
+#define THM_TCON_HTC__HTC_SLEW_SEL__SHIFT 0x17
+#define THM_TCON_HTC__HTC_HYST_LMT_MASK 0xf000000
+#define THM_TCON_HTC__HTC_HYST_LMT__SHIFT 0x18
+#define THM_TCON_HTC__HTC_PSTATE_LIMIT_MASK 0x70000000
+#define THM_TCON_HTC__HTC_PSTATE_LIMIT__SHIFT 0x1c
+#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP_MASK 0x1f
+#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0
+#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP_MASK 0x60
+#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5
+#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN_MASK 0x80
+#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7
+#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN_MASK 0x1f00
+#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8
+#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL_MASK 0x30000
+#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10
+#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL_MASK 0x40000
+#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12
+#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK 0x80000
+#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13
+#define THM_TCON_CUR_TMP__CUR_TEMP_MASK 0xffe00000
+#define THM_TCON_CUR_TMP__CUR_TEMP__SHIFT 0x15
+#define THM_TCON_THERM_TRIP__RSVD0_MASK 0x1
+#define THM_TCON_THERM_TRIP__RSVD0__SHIFT 0x0
+#define THM_TCON_THERM_TRIP__THERM_TP_MASK 0x2
+#define THM_TCON_THERM_TRIP__THERM_TP__SHIFT 0x1
+#define THM_TCON_THERM_TRIP__RSVD1_MASK 0x4
+#define THM_TCON_THERM_TRIP__RSVD1__SHIFT 0x2
+#define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK 0x8
+#define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT 0x3
+#define THM_TCON_THERM_TRIP__RSVD2_MASK 0x10
+#define THM_TCON_THERM_TRIP__RSVD2__SHIFT 0x4
+#define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK 0x20
+#define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT 0x5
+#define THM_TCON_THERM_TRIP__RSVD3_MASK 0x7fffffc0
+#define THM_TCON_THERM_TRIP__RSVD3__SHIFT 0x6
+#define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK 0x80000000
+#define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT 0x1f
+#define THM_GPIO_PROCHOT_CTRL__TX12_EN_MASK 0x1
+#define THM_GPIO_PROCHOT_CTRL__TX12_EN__SHIFT 0x0
+#define THM_GPIO_PROCHOT_CTRL__PD_MASK 0x2
+#define THM_GPIO_PROCHOT_CTRL__PD__SHIFT 0x1
+#define THM_GPIO_PROCHOT_CTRL__PU_MASK 0x4
+#define THM_GPIO_PROCHOT_CTRL__PU__SHIFT 0x2
+#define THM_GPIO_PROCHOT_CTRL__SCHMEN_MASK 0x8
+#define THM_GPIO_PROCHOT_CTRL__SCHMEN__SHIFT 0x3
+#define THM_GPIO_PROCHOT_CTRL__SN_MASK 0x10
+#define THM_GPIO_PROCHOT_CTRL__SN__SHIFT 0x4
+#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE_MASK 0x100
+#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE__SHIFT 0x8
+#define THM_GPIO_PROCHOT_CTRL__OE_MASK 0x200
+#define THM_GPIO_PROCHOT_CTRL__OE__SHIFT 0x9
+#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE_MASK 0x400
+#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE__SHIFT 0xa
+#define THM_GPIO_PROCHOT_CTRL__A_MASK 0x800
+#define THM_GPIO_PROCHOT_CTRL__A__SHIFT 0xb
+#define THM_GPIO_PROCHOT_CTRL__Y_MASK 0x1000
+#define THM_GPIO_PROCHOT_CTRL__Y__SHIFT 0xc
+#define THM_GPIO_THERMTRIP_CTRL__TX12_EN_MASK 0x1
+#define THM_GPIO_THERMTRIP_CTRL__TX12_EN__SHIFT 0x0
+#define THM_GPIO_THERMTRIP_CTRL__PD_MASK 0x2
+#define THM_GPIO_THERMTRIP_CTRL__PD__SHIFT 0x1
+#define THM_GPIO_THERMTRIP_CTRL__PU_MASK 0x4
+#define THM_GPIO_THERMTRIP_CTRL__PU__SHIFT 0x2
+#define THM_GPIO_THERMTRIP_CTRL__SCHMEN_MASK 0x8
+#define THM_GPIO_THERMTRIP_CTRL__SCHMEN__SHIFT 0x3
+#define THM_GPIO_THERMTRIP_CTRL__SN_MASK 0x10
+#define THM_GPIO_THERMTRIP_CTRL__SN__SHIFT 0x4
+#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE_MASK 0x100
+#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE__SHIFT 0x8
+#define THM_GPIO_THERMTRIP_CTRL__OE_MASK 0x200
+#define THM_GPIO_THERMTRIP_CTRL__OE__SHIFT 0x9
+#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE_MASK 0x400
+#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE__SHIFT 0xa
+#define THM_GPIO_THERMTRIP_CTRL__A_MASK 0x800
+#define THM_GPIO_THERMTRIP_CTRL__A__SHIFT 0xb
+#define THM_GPIO_THERMTRIP_CTRL__Y_MASK 0x1000
+#define THM_GPIO_THERMTRIP_CTRL__Y__SHIFT 0xc
+#define THM_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1
+#define THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0
+#define THM_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2
+#define THM_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1
+#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4
+#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2
+#define THM_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8
+#define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3
+#define THM_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10
+#define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4
+#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20
+#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5
+#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff
+#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0
+#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00
+#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8
+#define THM_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000
+#define THM_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10
+#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000
+#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18
+#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000
+#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19
+#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000
+#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a
+#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000
+#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b
+#define THM_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000
+#define THM_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c
+#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1
+#define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0
+#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2
+#define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1
+#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4
+#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2
+#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8
+#define THM_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3
+#define TMON0_RDIL0_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIL0_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIL1_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIL1_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIL2_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIL2_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIL3_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIL3_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIL4_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIL4_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIL5_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIL5_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIL6_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIL6_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIL7_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIL7_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIL8_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIL8_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIL9_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIL9_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIL10_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIL10_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIL11_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIL11_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIL12_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIL12_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIL13_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIL13_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIL14_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIL14_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIL15_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIL15_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIR0_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIR0_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIR1_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIR1_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIR2_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIR2_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIR3_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIR3_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIR4_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIR4_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIR5_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIR5_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIR6_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIR6_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIR7_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIR7_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIR8_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIR8_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIR9_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIR9_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIR10_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIR10_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIR11_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIR11_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIR12_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIR12_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIR13_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIR13_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIR14_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIR14_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIR15_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_RDIR15_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_INT_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON0_INT_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON0_RDIL_PRESENT0__RDIL_PRESENT_7_0_MASK 0xff
+#define TMON0_RDIL_PRESENT0__RDIL_PRESENT_7_0__SHIFT 0x0
+#define TMON0_RDIL_PRESENT1__RDIL_PRESENT_15_8_MASK 0xff
+#define TMON0_RDIL_PRESENT1__RDIL_PRESENT_15_8__SHIFT 0x0
+#define TMON0_RDIR_PRESENT0__RDIR_PRESENT_7_0_MASK 0xff
+#define TMON0_RDIR_PRESENT0__RDIR_PRESENT_7_0__SHIFT 0x0
+#define TMON0_RDIR_PRESENT1__RDIR_PRESENT_15_8_MASK 0xff
+#define TMON0_RDIR_PRESENT1__RDIR_PRESENT_15_8__SHIFT 0x0
+#define TMON0_CONFIG__NUM_ACQ_MASK 0x7
+#define TMON0_CONFIG__NUM_ACQ__SHIFT 0x0
+#define TMON0_CONFIG__FORCE_MAX_ACQ_MASK 0x8
+#define TMON0_CONFIG__FORCE_MAX_ACQ__SHIFT 0x3
+#define TMON0_CONFIG__RDI_INTERLEAVE_MASK 0x10
+#define TMON0_CONFIG__RDI_INTERLEAVE__SHIFT 0x4
+#define TMON0_CONFIG__RE_CALIB_EN_MASK 0x40
+#define TMON0_CONFIG__RE_CALIB_EN__SHIFT 0x6
+#define TMON0_TEMP_CALC_COEFF0__Z_MASK 0x7ff
+#define TMON0_TEMP_CALC_COEFF0__Z__SHIFT 0x0
+#define TMON0_TEMP_CALC_COEFF1__A_MASK 0xfff
+#define TMON0_TEMP_CALC_COEFF1__A__SHIFT 0x0
+#define TMON0_TEMP_CALC_COEFF2__B_MASK 0x3f
+#define TMON0_TEMP_CALC_COEFF2__B__SHIFT 0x0
+#define TMON0_TEMP_CALC_COEFF3__C_MASK 0x7ff
+#define TMON0_TEMP_CALC_COEFF3__C__SHIFT 0x0
+#define TMON0_TEMP_CALC_COEFF4__K_MASK 0x1
+#define TMON0_TEMP_CALC_COEFF4__K__SHIFT 0x0
+#define TMON0_DEBUG0__DEBUG_Z_MASK 0x7ff
+#define TMON0_DEBUG0__DEBUG_Z__SHIFT 0x0
+#define TMON0_DEBUG0__DEBUG_Z_EN_MASK 0x800
+#define TMON0_DEBUG0__DEBUG_Z_EN__SHIFT 0xb
+#define TMON0_DEBUG1__DEBUG_RDI_MASK 0x1f
+#define TMON0_DEBUG1__DEBUG_RDI__SHIFT 0x0
+#define TMON1_RDIL0_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIL0_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIL1_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIL1_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIL2_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIL2_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIL3_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIL3_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIL4_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIL4_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIL5_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIL5_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIL6_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIL6_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIL7_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIL7_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIL8_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIL8_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIL9_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIL9_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIL10_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIL10_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIL11_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIL11_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIL12_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIL12_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIL13_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIL13_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIL14_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIL14_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIL15_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIL15_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIR0_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIR0_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIR1_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIR1_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIR2_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIR2_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIR3_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIR3_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIR4_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIR4_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIR5_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIR5_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIR6_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIR6_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIR7_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIR7_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIR8_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIR8_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIR9_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIR9_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIR10_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIR10_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIR11_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIR11_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIR12_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIR12_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIR13_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIR13_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIR14_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIR14_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIR15_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_RDIR15_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_INT_DATA__TEMP_Z_DATA_MASK 0xfff
+#define TMON1_INT_DATA__TEMP_Z_DATA__SHIFT 0x0
+#define TMON1_RDIL_PRESENT0__RDIL_PRESENT_7_0_MASK 0xff
+#define TMON1_RDIL_PRESENT0__RDIL_PRESENT_7_0__SHIFT 0x0
+#define TMON1_RDIL_PRESENT1__RDIL_PRESENT_15_8_MASK 0xff
+#define TMON1_RDIL_PRESENT1__RDIL_PRESENT_15_8__SHIFT 0x0
+#define TMON1_RDIR_PRESENT0__RDIR_PRESENT_7_0_MASK 0xff
+#define TMON1_RDIR_PRESENT0__RDIR_PRESENT_7_0__SHIFT 0x0
+#define TMON1_RDIR_PRESENT1__RDIR_PRESENT_15_8_MASK 0xff
+#define TMON1_RDIR_PRESENT1__RDIR_PRESENT_15_8__SHIFT 0x0
+#define TMON1_CONFIG__NUM_ACQ_MASK 0x7
+#define TMON1_CONFIG__NUM_ACQ__SHIFT 0x0
+#define TMON1_CONFIG__FORCE_MAX_ACQ_MASK 0x8
+#define TMON1_CONFIG__FORCE_MAX_ACQ__SHIFT 0x3
+#define TMON1_CONFIG__RDI_INTERLEAVE_MASK 0x10
+#define TMON1_CONFIG__RDI_INTERLEAVE__SHIFT 0x4
+#define TMON1_CONFIG__RE_CALIB_EN_MASK 0x40
+#define TMON1_CONFIG__RE_CALIB_EN__SHIFT 0x6
+#define TMON1_TEMP_CALC_COEFF0__Z_MASK 0x7ff
+#define TMON1_TEMP_CALC_COEFF0__Z__SHIFT 0x0
+#define TMON1_TEMP_CALC_COEFF1__A_MASK 0xfff
+#define TMON1_TEMP_CALC_COEFF1__A__SHIFT 0x0
+#define TMON1_TEMP_CALC_COEFF2__B_MASK 0x3f
+#define TMON1_TEMP_CALC_COEFF2__B__SHIFT 0x0
+#define TMON1_TEMP_CALC_COEFF3__C_MASK 0x7ff
+#define TMON1_TEMP_CALC_COEFF3__C__SHIFT 0x0
+#define TMON1_TEMP_CALC_COEFF4__K_MASK 0x1
+#define TMON1_TEMP_CALC_COEFF4__K__SHIFT 0x0
+#define TMON1_DEBUG0__DEBUG_Z_MASK 0x7ff
+#define TMON1_DEBUG0__DEBUG_Z__SHIFT 0x0
+#define TMON1_DEBUG0__DEBUG_Z_EN_MASK 0x800
+#define TMON1_DEBUG0__DEBUG_Z_EN__SHIFT 0xb
+#define TMON1_DEBUG1__DEBUG_RDI_MASK 0x1f
+#define TMON1_DEBUG1__DEBUG_RDI__SHIFT 0x0
+#define THM_TMON0_REMOTE_START__DATA_MASK 0xffffffff
+#define THM_TMON0_REMOTE_START__DATA__SHIFT 0x0
+#define THM_TMON0_REMOTE_END__DATA_MASK 0xffffffff
+#define THM_TMON0_REMOTE_END__DATA__SHIFT 0x0
+#define THM_TMON1_REMOTE_START__DATA_MASK 0xffffffff
+#define THM_TMON1_REMOTE_START__DATA__SHIFT 0x0
+#define THM_TMON1_REMOTE_END__DATA_MASK 0xffffffff
+#define THM_TMON1_REMOTE_END__DATA__SHIFT 0x0
+#define THM_TCON_LOCAL0__HaltPolling_MASK 0x1
+#define THM_TCON_LOCAL0__HaltPolling__SHIFT 0x0
+#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis_MASK 0x2
+#define THM_TCON_LOCAL0__TMON0_PwrDn_Dis__SHIFT 0x1
+#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis_MASK 0x4
+#define THM_TCON_LOCAL0__TMON1_PwrDn_Dis__SHIFT 0x2
+#define THM_TCON_LOCAL1__PwrDn_Limit_Temp_MASK 0x7
+#define THM_TCON_LOCAL1__PwrDn_Limit_Temp__SHIFT 0x0
+#define THM_TCON_LOCAL1__PwrDn_DelaySlope_MASK 0x38
+#define THM_TCON_LOCAL1__PwrDn_DelaySlope__SHIFT 0x3
+#define THM_TCON_LOCAL1__PwrDn_MinDelay_MASK 0x1c0
+#define THM_TCON_LOCAL1__PwrDn_MinDelay__SHIFT 0x6
+#define THM_TCON_LOCAL2__PwrDn_MaxDlyMult_MASK 0x3
+#define THM_TCON_LOCAL2__PwrDn_MaxDlyMult__SHIFT 0x0
+#define THM_TCON_LOCAL2__PwrDn_NumSensors_MASK 0xc
+#define THM_TCON_LOCAL2__PwrDn_NumSensors__SHIFT 0x2
+#define THM_TCON_LOCAL2__start_mission_polling_MASK 0x10
+#define THM_TCON_LOCAL2__start_mission_polling__SHIFT 0x4
+#define THM_TCON_LOCAL2__short_stagger_count_MASK 0x20
+#define THM_TCON_LOCAL2__short_stagger_count__SHIFT 0x5
+#define THM_TCON_LOCAL2__sbtsi_use_corrected_MASK 0x40
+#define THM_TCON_LOCAL2__sbtsi_use_corrected__SHIFT 0x6
+#define THM_TCON_LOCAL2__csrslave_use_corrected_MASK 0x80
+#define THM_TCON_LOCAL2__csrslave_use_corrected__SHIFT 0x7
+#define THM_TCON_LOCAL2__smu_use_corrected_MASK 0x100
+#define THM_TCON_LOCAL2__smu_use_corrected__SHIFT 0x8
+#define THM_TCON_LOCAL2__skip_scale_correction_MASK 0x800
+#define THM_TCON_LOCAL2__skip_scale_correction__SHIFT 0xb
+#define THM_TCON_LOCAL3__Global_TMAX_MASK 0x7ff
+#define THM_TCON_LOCAL3__Global_TMAX__SHIFT 0x0
+#define THM_TCON_LOCAL4__Global_TMAX_ID_MASK 0xff
+#define THM_TCON_LOCAL4__Global_TMAX_ID__SHIFT 0x0
+#define THM_TCON_LOCAL5__Global_TMIN_MASK 0x7ff
+#define THM_TCON_LOCAL5__Global_TMIN__SHIFT 0x0
+#define THM_TCON_LOCAL6__Global_TMIN_ID_MASK 0xff
+#define THM_TCON_LOCAL6__Global_TMIN_ID__SHIFT 0x0
+#define THM_TCON_LOCAL7__THERMID_MASK 0xff
+#define THM_TCON_LOCAL7__THERMID__SHIFT 0x0
+#define THM_TCON_LOCAL8__THERMMAX_MASK 0x7ff
+#define THM_TCON_LOCAL8__THERMMAX__SHIFT 0x0
+#define THM_TCON_LOCAL9__Tj_Max_TMON0_MASK 0x7ff
+#define THM_TCON_LOCAL9__Tj_Max_TMON0__SHIFT 0x0
+#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID_MASK 0xf
+#define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID__SHIFT 0x0
+#define THM_TCON_LOCAL11__Tj_Max_TMON1_MASK 0x7ff
+#define THM_TCON_LOCAL11__Tj_Max_TMON1__SHIFT 0x0
+#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID_MASK 0xf
+#define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID__SHIFT 0x0
+#define THM_TCON_LOCAL13__PowerDownTmon0_MASK 0x1
+#define THM_TCON_LOCAL13__PowerDownTmon0__SHIFT 0x0
+#define THM_TCON_LOCAL13__PowerDownTmon1_MASK 0x2
+#define THM_TCON_LOCAL13__PowerDownTmon1__SHIFT 0x1
+#define THM_TCON_LOCAL14__boot_done_MASK 0x1
+#define THM_TCON_LOCAL14__boot_done__SHIFT 0x0
+#define THM_FUSE0__FUSE_TmonRsInterleave_MASK 0x1
+#define THM_FUSE0__FUSE_TmonRsInterleave__SHIFT 0x0
+#define THM_FUSE0__FUSE_TmonNumAcq_MASK 0xe
+#define THM_FUSE0__FUSE_TmonNumAcq__SHIFT 0x1
+#define THM_FUSE0__FUSE_TmonForceMaxAcq_MASK 0x10
+#define THM_FUSE0__FUSE_TmonForceMaxAcq__SHIFT 0x4
+#define THM_FUSE0__FUSE_TmonClkDiv_MASK 0x60
+#define THM_FUSE0__FUSE_TmonClkDiv__SHIFT 0x5
+#define THM_FUSE0__FUSE_TmonBGAdj1_MASK 0x7f80
+#define THM_FUSE0__FUSE_TmonBGAdj1__SHIFT 0x7
+#define THM_FUSE0__FUSE_TmonBGAdj0_MASK 0x7f8000
+#define THM_FUSE0__FUSE_TmonBGAdj0__SHIFT 0xf
+#define THM_FUSE0__FUSE_TconZtValue_MASK 0xff800000
+#define THM_FUSE0__FUSE_TconZtValue__SHIFT 0x17
+#define THM_FUSE1__FUSE_TconZtValue_MASK 0x3
+#define THM_FUSE1__FUSE_TconZtValue__SHIFT 0x0
+#define THM_FUSE1__FUSE_TconUseSecondary_MASK 0xc
+#define THM_FUSE1__FUSE_TconUseSecondary__SHIFT 0x2
+#define THM_FUSE1__FUSE_TconTmpAdjLoRes_MASK 0x10
+#define THM_FUSE1__FUSE_TconTmpAdjLoRes__SHIFT 0x4
+#define THM_FUSE1__FUSE_TconPwrUpStaggerTime_MASK 0x60
+#define THM_FUSE1__FUSE_TconPwrUpStaggerTime__SHIFT 0x5
+#define THM_FUSE1__FUSE_TconPwrDnTmpLmt_MASK 0x380
+#define THM_FUSE1__FUSE_TconPwrDnTmpLmt__SHIFT 0x7
+#define THM_FUSE1__FUSE_TconPwrDnNumSensors_MASK 0xc00
+#define THM_FUSE1__FUSE_TconPwrDnNumSensors__SHIFT 0xa
+#define THM_FUSE1__FUSE_TconPwrDnMinDelay_MASK 0x7000
+#define THM_FUSE1__FUSE_TconPwrDnMinDelay__SHIFT 0xc
+#define THM_FUSE1__FUSE_TconPwrDnMaxDelayMult_MASK 0x18000
+#define THM_FUSE1__FUSE_TconPwrDnMaxDelayMult__SHIFT 0xf
+#define THM_FUSE1__FUSE_TconPwrDnDelaySlope_MASK 0xe0000
+#define THM_FUSE1__FUSE_TconPwrDnDelaySlope__SHIFT 0x11
+#define THM_FUSE1__FUSE_TconKValue_MASK 0x100000
+#define THM_FUSE1__FUSE_TconKValue__SHIFT 0x14
+#define THM_FUSE1__FUSE_TconDtValue31_MASK 0x7e00000
+#define THM_FUSE1__FUSE_TconDtValue31__SHIFT 0x15
+#define THM_FUSE1__FUSE_TconDtValue30_MASK 0xf8000000
+#define THM_FUSE1__FUSE_TconDtValue30__SHIFT 0x1b
+#define THM_FUSE2__FUSE_TconDtValue30_MASK 0x1
+#define THM_FUSE2__FUSE_TconDtValue30__SHIFT 0x0
+#define THM_FUSE2__FUSE_TconDtValue29_MASK 0x7e
+#define THM_FUSE2__FUSE_TconDtValue29__SHIFT 0x1
+#define THM_FUSE2__FUSE_TconDtValue28_MASK 0x1f80
+#define THM_FUSE2__FUSE_TconDtValue28__SHIFT 0x7
+#define THM_FUSE2__FUSE_TconDtValue27_MASK 0x7e000
+#define THM_FUSE2__FUSE_TconDtValue27__SHIFT 0xd
+#define THM_FUSE2__FUSE_TconDtValue26_MASK 0x1f80000
+#define THM_FUSE2__FUSE_TconDtValue26__SHIFT 0x13
+#define THM_FUSE2__FUSE_TconDtValue25_MASK 0x7e000000
+#define THM_FUSE2__FUSE_TconDtValue25__SHIFT 0x19
+#define THM_FUSE2__FUSE_TconDtValue24_MASK 0x80000000
+#define THM_FUSE2__FUSE_TconDtValue24__SHIFT 0x1f
+#define THM_FUSE3__FUSE_TconDtValue24_MASK 0x1f
+#define THM_FUSE3__FUSE_TconDtValue24__SHIFT 0x0
+#define THM_FUSE3__FUSE_TconDtValue23_MASK 0x7e0
+#define THM_FUSE3__FUSE_TconDtValue23__SHIFT 0x5
+#define THM_FUSE3__FUSE_TconDtValue22_MASK 0x1f800
+#define THM_FUSE3__FUSE_TconDtValue22__SHIFT 0xb
+#define THM_FUSE3__FUSE_TconDtValue21_MASK 0x7e0000
+#define THM_FUSE3__FUSE_TconDtValue21__SHIFT 0x11
+#define THM_FUSE3__FUSE_TconDtValue20_MASK 0x1f800000
+#define THM_FUSE3__FUSE_TconDtValue20__SHIFT 0x17
+#define THM_FUSE3__FUSE_TconDtValue19_MASK 0xe0000000
+#define THM_FUSE3__FUSE_TconDtValue19__SHIFT 0x1d
+#define THM_FUSE4__FUSE_TconDtValue19_MASK 0x7
+#define THM_FUSE4__FUSE_TconDtValue19__SHIFT 0x0
+#define THM_FUSE4__FUSE_TconDtValue18_MASK 0x1f8
+#define THM_FUSE4__FUSE_TconDtValue18__SHIFT 0x3
+#define THM_FUSE4__FUSE_TconDtValue17_MASK 0x7e00
+#define THM_FUSE4__FUSE_TconDtValue17__SHIFT 0x9
+#define THM_FUSE4__FUSE_TconDtValue16_MASK 0x1f8000
+#define THM_FUSE4__FUSE_TconDtValue16__SHIFT 0xf
+#define THM_FUSE4__FUSE_TconDtValue15_MASK 0x7e00000
+#define THM_FUSE4__FUSE_TconDtValue15__SHIFT 0x15
+#define THM_FUSE4__FUSE_TconDtValue14_MASK 0xf8000000
+#define THM_FUSE4__FUSE_TconDtValue14__SHIFT 0x1b
+#define THM_FUSE5__FUSE_TconDtValue14_MASK 0x1
+#define THM_FUSE5__FUSE_TconDtValue14__SHIFT 0x0
+#define THM_FUSE5__FUSE_TconDtValue13_MASK 0x7e
+#define THM_FUSE5__FUSE_TconDtValue13__SHIFT 0x1
+#define THM_FUSE5__FUSE_TconDtValue12_MASK 0x1f80
+#define THM_FUSE5__FUSE_TconDtValue12__SHIFT 0x7
+#define THM_FUSE5__FUSE_TconDtValue11_MASK 0x7e000
+#define THM_FUSE5__FUSE_TconDtValue11__SHIFT 0xd
+#define THM_FUSE5__FUSE_TconDtValue10_MASK 0x1f80000
+#define THM_FUSE5__FUSE_TconDtValue10__SHIFT 0x13
+#define THM_FUSE5__FUSE_TconDtValue9_MASK 0x7e000000
+#define THM_FUSE5__FUSE_TconDtValue9__SHIFT 0x19
+#define THM_FUSE5__FUSE_TconDtValue8_MASK 0x80000000
+#define THM_FUSE5__FUSE_TconDtValue8__SHIFT 0x1f
+#define THM_FUSE6__FUSE_TconDtValue8_MASK 0x1f
+#define THM_FUSE6__FUSE_TconDtValue8__SHIFT 0x0
+#define THM_FUSE6__FUSE_TconDtValue7_MASK 0x7e0
+#define THM_FUSE6__FUSE_TconDtValue7__SHIFT 0x5
+#define THM_FUSE6__FUSE_TconDtValue6_MASK 0x1f800
+#define THM_FUSE6__FUSE_TconDtValue6__SHIFT 0xb
+#define THM_FUSE6__FUSE_TconDtValue5_MASK 0x7e0000
+#define THM_FUSE6__FUSE_TconDtValue5__SHIFT 0x11
+#define THM_FUSE6__FUSE_TconDtValue4_MASK 0x1f800000
+#define THM_FUSE6__FUSE_TconDtValue4__SHIFT 0x17
+#define THM_FUSE6__FUSE_TconDtValue3_MASK 0xe0000000
+#define THM_FUSE6__FUSE_TconDtValue3__SHIFT 0x1d
+#define THM_FUSE7__FUSE_TconDtValue3_MASK 0x7
+#define THM_FUSE7__FUSE_TconDtValue3__SHIFT 0x0
+#define THM_FUSE7__FUSE_TconDtValue2_MASK 0x1f8
+#define THM_FUSE7__FUSE_TconDtValue2__SHIFT 0x3
+#define THM_FUSE7__FUSE_TconDtValue1_MASK 0x7e00
+#define THM_FUSE7__FUSE_TconDtValue1__SHIFT 0x9
+#define THM_FUSE7__FUSE_TconDtValue0_MASK 0x1f8000
+#define THM_FUSE7__FUSE_TconDtValue0__SHIFT 0xf
+#define THM_FUSE7__FUSE_TconCtValue1_MASK 0xffe00000
+#define THM_FUSE7__FUSE_TconCtValue1__SHIFT 0x15
+#define THM_FUSE8__FUSE_TconCtValue0_MASK 0x7ff
+#define THM_FUSE8__FUSE_TconCtValue0__SHIFT 0x0
+#define THM_FUSE8__FUSE_TconBtValue_MASK 0x1f800
+#define THM_FUSE8__FUSE_TconBtValue__SHIFT 0xb
+#define THM_FUSE8__FUSE_TconBootDelay_MASK 0x60000
+#define THM_FUSE8__FUSE_TconBootDelay__SHIFT 0x11
+#define THM_FUSE8__FUSE_TconAtValue1_MASK 0x7ff80000
+#define THM_FUSE8__FUSE_TconAtValue1__SHIFT 0x13
+#define THM_FUSE8__FUSE_TconAtValue0_MASK 0x80000000
+#define THM_FUSE8__FUSE_TconAtValue0__SHIFT 0x1f
+#define THM_FUSE9__FUSE_TconAtValue0_MASK 0x7ff
+#define THM_FUSE9__FUSE_TconAtValue0__SHIFT 0x0
+#define THM_FUSE9__FUSE_ThermTripLimit_MASK 0x7f800
+#define THM_FUSE9__FUSE_ThermTripLimit__SHIFT 0xb
+#define THM_FUSE9__FUSE_ThermTripEn_MASK 0x80000
+#define THM_FUSE9__FUSE_ThermTripEn__SHIFT 0x13
+#define THM_FUSE9__FUSE_HtcTmpLmt_MASK 0x7f00000
+#define THM_FUSE9__FUSE_HtcTmpLmt__SHIFT 0x14
+#define THM_FUSE9__FUSE_HtcMsrLock_MASK 0x8000000
+#define THM_FUSE9__FUSE_HtcMsrLock__SHIFT 0x1b
+#define THM_FUSE9__FUSE_HtcHystLmt_MASK 0xf0000000
+#define THM_FUSE9__FUSE_HtcHystLmt__SHIFT 0x1c
+#define THM_FUSE10__FUSE_HtcDis_MASK 0x1
+#define THM_FUSE10__FUSE_HtcDis__SHIFT 0x0
+#define THM_FUSE10__FUSE_HtcClkInact_MASK 0xe
+#define THM_FUSE10__FUSE_HtcClkInact__SHIFT 0x1
+#define THM_FUSE10__FUSE_HtcClkAct_MASK 0x70
+#define THM_FUSE10__FUSE_HtcClkAct__SHIFT 0x4
+#define THM_FUSE10__FUSE_UnusedBits_MASK 0xffffff80
+#define THM_FUSE10__FUSE_UnusedBits__SHIFT 0x7
+#define THM_FUSE11__PA_SPARE_MASK 0xff
+#define THM_FUSE11__PA_SPARE__SHIFT 0x0
+#define THM_FUSE12__FusesValid_MASK 0x1
+#define THM_FUSE12__FusesValid__SHIFT 0x0
+#define MP0PUB_IND_INDEX__MP0PUB_IND_ADDR_MASK 0xffffffff
+#define MP0PUB_IND_INDEX__MP0PUB_IND_ADDR__SHIFT 0x0
+#define MP0PUB_IND_DATA__MP0PUB_IND_DATA_MASK 0xffffffff
+#define MP0PUB_IND_DATA__MP0PUB_IND_DATA__SHIFT 0x0
+#define MP0PUB_IND_INDEX_0__MP0PUB_IND_ADDR_MASK 0xffffffff
+#define MP0PUB_IND_INDEX_0__MP0PUB_IND_ADDR__SHIFT 0x0
+#define MP0PUB_IND_DATA_0__MP0PUB_IND_DATA_MASK 0xffffffff
+#define MP0PUB_IND_DATA_0__MP0PUB_IND_DATA__SHIFT 0x0
+#define MP0PUB_IND_INDEX_1__MP0PUB_IND_ADDR_MASK 0xffffffff
+#define MP0PUB_IND_INDEX_1__MP0PUB_IND_ADDR__SHIFT 0x0
+#define MP0PUB_IND_DATA_1__MP0PUB_IND_DATA_MASK 0xffffffff
+#define MP0PUB_IND_DATA_1__MP0PUB_IND_DATA__SHIFT 0x0
+#define MP0PUB_IND_INDEX_2__MP0PUB_IND_ADDR_MASK 0xffffffff
+#define MP0PUB_IND_INDEX_2__MP0PUB_IND_ADDR__SHIFT 0x0
+#define MP0PUB_IND_DATA_2__MP0PUB_IND_DATA_MASK 0xffffffff
+#define MP0PUB_IND_DATA_2__MP0PUB_IND_DATA__SHIFT 0x0
+#define MP0PUB_IND_INDEX_3__MP0PUB_IND_ADDR_MASK 0xffffffff
+#define MP0PUB_IND_INDEX_3__MP0PUB_IND_ADDR__SHIFT 0x0
+#define MP0PUB_IND_DATA_3__MP0PUB_IND_DATA_MASK 0xffffffff
+#define MP0PUB_IND_DATA_3__MP0PUB_IND_DATA__SHIFT 0x0
+#define MP0PUB_IND_INDEX_4__MP0PUB_IND_ADDR_MASK 0xffffffff
+#define MP0PUB_IND_INDEX_4__MP0PUB_IND_ADDR__SHIFT 0x0
+#define MP0PUB_IND_DATA_4__MP0PUB_IND_DATA_MASK 0xffffffff
+#define MP0PUB_IND_DATA_4__MP0PUB_IND_DATA__SHIFT 0x0
+#define MP0PUB_IND_INDEX_5__MP0PUB_IND_ADDR_MASK 0xffffffff
+#define MP0PUB_IND_INDEX_5__MP0PUB_IND_ADDR__SHIFT 0x0
+#define MP0PUB_IND_DATA_5__MP0PUB_IND_DATA_MASK 0xffffffff
+#define MP0PUB_IND_DATA_5__MP0PUB_IND_DATA__SHIFT 0x0
+#define MP0PUB_IND_INDEX_6__MP0PUB_IND_ADDR_MASK 0xffffffff
+#define MP0PUB_IND_INDEX_6__MP0PUB_IND_ADDR__SHIFT 0x0
+#define MP0PUB_IND_DATA_6__MP0PUB_IND_DATA_MASK 0xffffffff
+#define MP0PUB_IND_DATA_6__MP0PUB_IND_DATA__SHIFT 0x0
+#define MP0PUB_IND_INDEX_7__MP0PUB_IND_ADDR_MASK 0xffffffff
+#define MP0PUB_IND_INDEX_7__MP0PUB_IND_ADDR__SHIFT 0x0
+#define MP0PUB_IND_DATA_7__MP0PUB_IND_DATA_MASK 0xffffffff
+#define MP0PUB_IND_DATA_7__MP0PUB_IND_DATA__SHIFT 0x0
+#define MP0PUB_IND_INDEX_8__MP0PUB_IND_ADDR_MASK 0xffffffff
+#define MP0PUB_IND_INDEX_8__MP0PUB_IND_ADDR__SHIFT 0x0
+#define MP0PUB_IND_DATA_8__MP0PUB_IND_DATA_MASK 0xffffffff
+#define MP0PUB_IND_DATA_8__MP0PUB_IND_DATA__SHIFT 0x0
+#define MP0PUB_IND_INDEX_9__MP0PUB_IND_ADDR_MASK 0xffffffff
+#define MP0PUB_IND_INDEX_9__MP0PUB_IND_ADDR__SHIFT 0x0
+#define MP0PUB_IND_DATA_9__MP0PUB_IND_DATA_MASK 0xffffffff
+#define MP0PUB_IND_DATA_9__MP0PUB_IND_DATA__SHIFT 0x0
+#define MP0PUB_IND_INDEX_10__MP0PUB_IND_ADDR_MASK 0xffffffff
+#define MP0PUB_IND_INDEX_10__MP0PUB_IND_ADDR__SHIFT 0x0
+#define MP0PUB_IND_DATA_10__MP0PUB_IND_DATA_MASK 0xffffffff
+#define MP0PUB_IND_DATA_10__MP0PUB_IND_DATA__SHIFT 0x0
+#define MP0PUB_IND_INDEX_11__MP0PUB_IND_ADDR_MASK 0xffffffff
+#define MP0PUB_IND_INDEX_11__MP0PUB_IND_ADDR__SHIFT 0x0
+#define MP0PUB_IND_DATA_11__MP0PUB_IND_DATA_MASK 0xffffffff
+#define MP0PUB_IND_DATA_11__MP0PUB_IND_DATA__SHIFT 0x0
+#define MP0PUB_IND_INDEX_12__MP0PUB_IND_ADDR_MASK 0xffffffff
+#define MP0PUB_IND_INDEX_12__MP0PUB_IND_ADDR__SHIFT 0x0
+#define MP0PUB_IND_DATA_12__MP0PUB_IND_DATA_MASK 0xffffffff
+#define MP0PUB_IND_DATA_12__MP0PUB_IND_DATA__SHIFT 0x0
+#define MP0PUB_IND_INDEX_13__MP0PUB_IND_ADDR_MASK 0xffffffff
+#define MP0PUB_IND_INDEX_13__MP0PUB_IND_ADDR__SHIFT 0x0
+#define MP0PUB_IND_DATA_13__MP0PUB_IND_DATA_MASK 0xffffffff
+#define MP0PUB_IND_DATA_13__MP0PUB_IND_DATA__SHIFT 0x0
+#define MP0PUB_IND_INDEX_14__MP0PUB_IND_ADDR_MASK 0xffffffff
+#define MP0PUB_IND_INDEX_14__MP0PUB_IND_ADDR__SHIFT 0x0
+#define MP0PUB_IND_DATA_14__MP0PUB_IND_DATA_MASK 0xffffffff
+#define MP0PUB_IND_DATA_14__MP0PUB_IND_DATA__SHIFT 0x0
+#define MP0PUB_IND_INDEX_15__MP0PUB_IND_ADDR_MASK 0xffffffff
+#define MP0PUB_IND_INDEX_15__MP0PUB_IND_ADDR__SHIFT 0x0
+#define MP0PUB_IND_DATA_15__MP0PUB_IND_DATA_MASK 0xffffffff
+#define MP0PUB_IND_DATA_15__MP0PUB_IND_DATA__SHIFT 0x0
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8_MASK 0x100
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8__SHIFT 0x8
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9_MASK 0x200
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9__SHIFT 0x9
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10_MASK 0x400
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10__SHIFT 0xa
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11_MASK 0x800
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11__SHIFT 0xb
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12_MASK 0x1000
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12__SHIFT 0xc
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13_MASK 0x2000
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13__SHIFT 0xd
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14_MASK 0x4000
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14__SHIFT 0xe
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15_MASK 0x8000
+#define MP0_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15__SHIFT 0xf
+#define MP0_MSP_MESSAGE_0__MP0_MSP_MSG_MASK 0xffffffff
+#define MP0_MSP_MESSAGE_0__MP0_MSP_MSG__SHIFT 0x0
+#define MP0_MSP_MESSAGE_1__MP0_MSP_MSG_MASK 0xffffffff
+#define MP0_MSP_MESSAGE_1__MP0_MSP_MSG__SHIFT 0x0
+#define MP0_MSP_MESSAGE_2__MP0_MSP_MSG_MASK 0xffffffff
+#define MP0_MSP_MESSAGE_2__MP0_MSP_MSG__SHIFT 0x0
+#define MP0_MSP_MESSAGE_3__MP0_MSP_MSG_MASK 0xffffffff
+#define MP0_MSP_MESSAGE_3__MP0_MSP_MSG__SHIFT 0x0
+#define MP0_MSP_MESSAGE_4__MP0_MSP_MSG_MASK 0xffffffff
+#define MP0_MSP_MESSAGE_4__MP0_MSP_MSG__SHIFT 0x0
+#define MP0_MSP_MESSAGE_5__MP0_MSP_MSG_MASK 0xffffffff
+#define MP0_MSP_MESSAGE_5__MP0_MSP_MSG__SHIFT 0x0
+#define MP0_MSP_MESSAGE_6__MP0_MSP_MSG_MASK 0xffffffff
+#define MP0_MSP_MESSAGE_6__MP0_MSP_MSG__SHIFT 0x0
+#define MP0_MSP_MESSAGE_7__MP0_MSP_MSG_MASK 0xffffffff
+#define MP0_MSP_MESSAGE_7__MP0_MSP_MSG__SHIFT 0x0
+#define SAM_IH_EXT_ERR_INTR__UVD_MASK 0x1
+#define SAM_IH_EXT_ERR_INTR__UVD__SHIFT 0x0
+#define SAM_IH_EXT_ERR_INTR__VCE_MASK 0x2
+#define SAM_IH_EXT_ERR_INTR__VCE__SHIFT 0x1
+#define SAM_IH_EXT_ERR_INTR__ISP_MASK 0x4
+#define SAM_IH_EXT_ERR_INTR__ISP__SHIFT 0x2
+#define SAM_IH_EXT_ERR_INTR__RESERVED_MASK 0xfffffff8
+#define SAM_IH_EXT_ERR_INTR__RESERVED__SHIFT 0x3
+#define SAM_IH_EXT_ERR_INTR_STATUS__UVD_MASK 0x1
+#define SAM_IH_EXT_ERR_INTR_STATUS__UVD__SHIFT 0x0
+#define SAM_IH_EXT_ERR_INTR_STATUS__VCE_MASK 0x2
+#define SAM_IH_EXT_ERR_INTR_STATUS__VCE__SHIFT 0x1
+#define SAM_IH_EXT_ERR_INTR_STATUS__ISP_MASK 0x4
+#define SAM_IH_EXT_ERR_INTR_STATUS__ISP__SHIFT 0x2
+#define SAM_IH_EXT_ERR_INTR_STATUS__RESERVED_MASK 0xfffffff8
+#define SAM_IH_EXT_ERR_INTR_STATUS__RESERVED__SHIFT 0x3
+#define MP0_DISP_TIMER0_CTRL0__START_MASK 0x1
+#define MP0_DISP_TIMER0_CTRL0__START__SHIFT 0x0
+#define MP0_DISP_TIMER0_CTRL0__CLEAR_MASK 0x100
+#define MP0_DISP_TIMER0_CTRL0__CLEAR__SHIFT 0x8
+#define MP0_DISP_TIMER0_CTRL0__DEC_MASK 0x10000
+#define MP0_DISP_TIMER0_CTRL0__DEC__SHIFT 0x10
+#define MP0_DISP_TIMER0_CTRL0__PULSE_COUNT_MODE_MASK 0x1000000
+#define MP0_DISP_TIMER0_CTRL0__PULSE_COUNT_MODE__SHIFT 0x18
+#define MP0_DISP_TIMER0_CTRL1__PWM_OUTPUT_EN_MASK 0x1
+#define MP0_DISP_TIMER0_CTRL1__PWM_OUTPUT_EN__SHIFT 0x0
+#define MP0_DISP_TIMER0_CTRL1__TIME_SLICE_MODE_EN_MASK 0x100
+#define MP0_DISP_TIMER0_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x8
+#define MP0_DISP_TIMER0_CTRL1__TIMER_SATURATION_EN_MASK 0x10000
+#define MP0_DISP_TIMER0_CTRL1__TIMER_SATURATION_EN__SHIFT 0x10
+#define MP0_DISP_TIMER0_CTRL1__RESERVED_MASK 0xff000000
+#define MP0_DISP_TIMER0_CTRL1__RESERVED__SHIFT 0x18
+#define MP0_DISP_TIMER0_CMP_AUTOINC__AUTOINC_MASK 0xf
+#define MP0_DISP_TIMER0_CMP_AUTOINC__AUTOINC__SHIFT 0x0
+#define MP0_DISP_TIMER0_CMP_AUTOINC__RESERVED_MASK 0xfffffff0
+#define MP0_DISP_TIMER0_CMP_AUTOINC__RESERVED__SHIFT 0x4
+#define MP0_DISP_TIMER0_INTEN__INTEN_MASK 0xf
+#define MP0_DISP_TIMER0_INTEN__INTEN__SHIFT 0x0
+#define MP0_DISP_TIMER0_INTEN__RESERVED_MASK 0xfffffff0
+#define MP0_DISP_TIMER0_INTEN__RESERVED__SHIFT 0x4
+#define MP0_DISP_TIMER0_OCMP_0_0__OCMP_MASK 0xffffffff
+#define MP0_DISP_TIMER0_OCMP_0_0__OCMP__SHIFT 0x0
+#define MP0_DISP_TIMER0_OCMP_0_1__OCMP_MASK 0xffffffff
+#define MP0_DISP_TIMER0_OCMP_0_1__OCMP__SHIFT 0x0
+#define MP0_DISP_TIMER0_CNT__COUNT_MASK 0xffffffff
+#define MP0_DISP_TIMER0_CNT__COUNT__SHIFT 0x0
+#define MP0_DISP_TIMER1_CTRL0__START_MASK 0x1
+#define MP0_DISP_TIMER1_CTRL0__START__SHIFT 0x0
+#define MP0_DISP_TIMER1_CTRL0__CLEAR_MASK 0x100
+#define MP0_DISP_TIMER1_CTRL0__CLEAR__SHIFT 0x8
+#define MP0_DISP_TIMER1_CTRL0__DEC_MASK 0x10000
+#define MP0_DISP_TIMER1_CTRL0__DEC__SHIFT 0x10
+#define MP0_DISP_TIMER1_CTRL0__PULSE_COUNT_MODE_MASK 0x1000000
+#define MP0_DISP_TIMER1_CTRL0__PULSE_COUNT_MODE__SHIFT 0x18
+#define MP0_DISP_TIMER1_CTRL1__PWM_OUTPUT_EN_MASK 0x1
+#define MP0_DISP_TIMER1_CTRL1__PWM_OUTPUT_EN__SHIFT 0x0
+#define MP0_DISP_TIMER1_CTRL1__TIME_SLICE_MODE_EN_MASK 0x100
+#define MP0_DISP_TIMER1_CTRL1__TIME_SLICE_MODE_EN__SHIFT 0x8
+#define MP0_DISP_TIMER1_CTRL1__TIMER_SATURATION_EN_MASK 0x10000
+#define MP0_DISP_TIMER1_CTRL1__TIMER_SATURATION_EN__SHIFT 0x10
+#define MP0_DISP_TIMER1_CTRL1__RESERVED_MASK 0xff000000
+#define MP0_DISP_TIMER1_CTRL1__RESERVED__SHIFT 0x18
+#define MP0_DISP_TIMER1_CMP_AUTOINC__AUTOINC_MASK 0xf
+#define MP0_DISP_TIMER1_CMP_AUTOINC__AUTOINC__SHIFT 0x0
+#define MP0_DISP_TIMER1_CMP_AUTOINC__RESERVED_MASK 0xfffffff0
+#define MP0_DISP_TIMER1_CMP_AUTOINC__RESERVED__SHIFT 0x4
+#define MP0_DISP_TIMER1_INTEN__INTEN_MASK 0xf
+#define MP0_DISP_TIMER1_INTEN__INTEN__SHIFT 0x0
+#define MP0_DISP_TIMER1_INTEN__RESERVED_MASK 0xfffffff0
+#define MP0_DISP_TIMER1_INTEN__RESERVED__SHIFT 0x4
+#define MP0_DISP_TIMER1_OCMP_0_0__OCMP_MASK 0xffffffff
+#define MP0_DISP_TIMER1_OCMP_0_0__OCMP__SHIFT 0x0
+#define MP0_DISP_TIMER1_OCMP_0_1__OCMP_MASK 0xffffffff
+#define MP0_DISP_TIMER1_OCMP_0_1__OCMP__SHIFT 0x0
+#define MP0_DISP_TIMER1_CNT__COUNT_MASK 0xffffffff
+#define MP0_DISP_TIMER1_CNT__COUNT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_MSG_0__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_MSG_0__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_MSG_1__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_MSG_1__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_MSG_2__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_MSG_2__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_MSG_3__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_MSG_3__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_MSG_4__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_MSG_4__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_MSG_5__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_MSG_5__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_MSG_6__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_MSG_6__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_MSG_7__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_MSG_7__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_MSG_8__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_MSG_8__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_MSG_9__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_MSG_9__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_MSG_10__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_MSG_10__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_MSG_11__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_MSG_11__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_MSG_12__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_MSG_12__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_MSG_13__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_MSG_13__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_MSG_14__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_MSG_14__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_MSG_15__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_MSG_15__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_RESP_0__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_RESP_0__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_RESP_1__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_RESP_1__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_RESP_2__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_RESP_2__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_RESP_3__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_RESP_3__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_RESP_4__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_RESP_4__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_RESP_5__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_RESP_5__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_RESP_6__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_RESP_6__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_RESP_7__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_RESP_7__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_RESP_8__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_RESP_8__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_RESP_9__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_RESP_9__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_RESP_10__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_RESP_10__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_RESP_11__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_RESP_11__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_RESP_12__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_RESP_12__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_RESP_13__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_RESP_13__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_RESP_14__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_RESP_14__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_RESP_15__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_RESP_15__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_ARG_0__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_ARG_0__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_ARG_1__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_ARG_1__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_ARG_2__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_ARG_2__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_ARG_3__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_ARG_3__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_ARG_4__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_ARG_4__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_ARG_5__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_ARG_5__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_ARG_6__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_ARG_6__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_ARG_7__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_ARG_7__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_ARG_8__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_ARG_8__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_ARG_9__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_ARG_9__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_ARG_10__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_ARG_10__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_ARG_11__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_ARG_11__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_ARG_12__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_ARG_12__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_ARG_13__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_ARG_13__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_ARG_14__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_ARG_14__CONTENT__SHIFT 0x0
+#define SMU_MP1_SRBM2P_ARG_15__CONTENT_MASK 0xffffffff
+#define SMU_MP1_SRBM2P_ARG_15__CONTENT__SHIFT 0x0
+#define SMU_MP1_ACP2MP_RESP__CONTENT_MASK 0xffffffff
+#define SMU_MP1_ACP2MP_RESP__CONTENT__SHIFT 0x0
+#define SMU_MP1_DC2MP_RESP__CONTENT_MASK 0xffffffff
+#define SMU_MP1_DC2MP_RESP__CONTENT__SHIFT 0x0
+#define SMU_MP1_UVD2MP_RESP__CONTENT_MASK 0xffffffff
+#define SMU_MP1_UVD2MP_RESP__CONTENT__SHIFT 0x0
+#define SMU_MP1_VCE2MP_RESP__CONTENT_MASK 0xffffffff
+#define SMU_MP1_VCE2MP_RESP__CONTENT__SHIFT 0x0
+#define SMU_MP1_RLC2MP_RESP__CONTENT_MASK 0xffffffff
+#define SMU_MP1_RLC2MP_RESP__CONTENT__SHIFT 0x0
+#define MP_FPS_CNT__FPS_CNT_MASK 0xffffffff
+#define MP_FPS_CNT__FPS_CNT__SHIFT 0x0
+#define SMU_DISP0_TIMER_INT_CONTROL__INT_STAT_MASK 0x1
+#define SMU_DISP0_TIMER_INT_CONTROL__INT_STAT__SHIFT 0x0
+#define SMU_DISP0_TIMER_INT_CONTROL__INT_UNMASK_MASK 0x2
+#define SMU_DISP0_TIMER_INT_CONTROL__INT_UNMASK__SHIFT 0x1
+#define SMU_DISP0_TIMER_INT_CONTROL__INT_TYPE_MASK 0x4
+#define SMU_DISP0_TIMER_INT_CONTROL__INT_TYPE__SHIFT 0x2
+#define SMU_DISP0_TIMER_INT_CONTROL__INT_ACK_MASK 0x8
+#define SMU_DISP0_TIMER_INT_CONTROL__INT_ACK__SHIFT 0x3
+#define SMU_DISP0_TIMER_INT_CONTROL__MASK_MASK 0x10
+#define SMU_DISP0_TIMER_INT_CONTROL__MASK__SHIFT 0x4
+#define SMU_DISP1_TIMER_INT_CONTROL__INT_STAT_MASK 0x1
+#define SMU_DISP1_TIMER_INT_CONTROL__INT_STAT__SHIFT 0x0
+#define SMU_DISP1_TIMER_INT_CONTROL__INT_UNMASK_MASK 0x2
+#define SMU_DISP1_TIMER_INT_CONTROL__INT_UNMASK__SHIFT 0x1
+#define SMU_DISP1_TIMER_INT_CONTROL__INT_TYPE_MASK 0x4
+#define SMU_DISP1_TIMER_INT_CONTROL__INT_TYPE__SHIFT 0x2
+#define SMU_DISP1_TIMER_INT_CONTROL__INT_ACK_MASK 0x8
+#define SMU_DISP1_TIMER_INT_CONTROL__INT_ACK__SHIFT 0x3
+#define SMU_DISP1_TIMER_INT_CONTROL__MASK_MASK 0x10
+#define SMU_DISP1_TIMER_INT_CONTROL__MASK__SHIFT 0x4
+#define SMU_SRBM_CONFIG__MSTR_CREDITS_MASK 0x1f
+#define SMU_SRBM_CONFIG__MSTR_CREDITS__SHIFT 0x0
+#define MP_FPS_CNT_XBAR__FPS_CNT_MASK 0xffffffff
+#define MP_FPS_CNT_XBAR__FPS_CNT__SHIFT 0x0
+#define MP_SRBM_CONFIG_XBAR__MSTR_CREDITS_MASK 0x1f
+#define MP_SRBM_CONFIG_XBAR__MSTR_CREDITS__SHIFT 0x0
+#define MP_SRBM_CONTROL__ACC_VIO_EN_MASK 0x1
+#define MP_SRBM_CONTROL__ACC_VIO_EN__SHIFT 0x0
+#define MP_SRBM_CONTROL__ALLOW_NS_ACC_MASK 0x2
+#define MP_SRBM_CONTROL__ALLOW_NS_ACC__SHIFT 0x1
+#define MP_SRBM_CONTROL__SOFT_RST_MASK_MASK 0x4
+#define MP_SRBM_CONTROL__SOFT_RST_MASK__SHIFT 0x2
+#define MP_SRBM_CONTROL__SOFT_RST_STS_MASK 0x8
+#define MP_SRBM_CONTROL__SOFT_RST_STS__SHIFT 0x3
+#define MP_SRBM_ACCVIO_LOG__ACC_VIO_OP_MASK 0x1
+#define MP_SRBM_ACCVIO_LOG__ACC_VIO_OP__SHIFT 0x0
+#define MP_SRBM_ACCVIO_LOG__ACC_VIO_SRCID_MASK 0xe
+#define MP_SRBM_ACCVIO_LOG__ACC_VIO_SRCID__SHIFT 0x1
+#define MP_SRBM_ACCVIO_LOG__ACC_VIO_VALID_MASK 0x80000000
+#define MP_SRBM_ACCVIO_LOG__ACC_VIO_VALID__SHIFT 0x1f
+#define MP_SRBM_ACCVIO_ADDR__ACC_VIO_ADDR_MASK 0xffffffff
+#define MP_SRBM_ACCVIO_ADDR__ACC_VIO_ADDR__SHIFT 0x0
+#define MP_CRBBM_CONTROL__ACC_VIO_EN_MASK 0x1
+#define MP_CRBBM_CONTROL__ACC_VIO_EN__SHIFT 0x0
+#define MP_CRBBM_CONTROL__MP0_ACCESS_MASK 0x2
+#define MP_CRBBM_CONTROL__MP0_ACCESS__SHIFT 0x1
+#define MP_CRBBM_CONTROL__ALLOW_NS_ACC_MASK 0x4
+#define MP_CRBBM_CONTROL__ALLOW_NS_ACC__SHIFT 0x2
+#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_OP_MASK 0x1
+#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_OP__SHIFT 0x0
+#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_INTF_MASK 0x2
+#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_INTF__SHIFT 0x1
+#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_VALID_MASK 0x80000000
+#define MP_CRBBM_ACCVIO_LOG__ACC_VIO_VALID__SHIFT 0x1f
+#define MP_CRBBM_ACCVIO_ADDR__ACC_VIO_ADDR_MASK 0xffffffff
+#define MP_CRBBM_ACCVIO_ADDR__ACC_VIO_ADDR__SHIFT 0x0
+#define MP_DRAM_CNTL_WRREQ_CNTL__tag_MASK 0x1ffff
+#define MP_DRAM_CNTL_WRREQ_CNTL__tag__SHIFT 0x0
+#define MP_DRAM_CNTL_WRREQ_CNTL__urg_MASK 0x1e0000
+#define MP_DRAM_CNTL_WRREQ_CNTL__urg__SHIFT 0x11
+#define MP_DRAM_CNTL_WRREQ_CNTL__stall_MASK 0x200000
+#define MP_DRAM_CNTL_WRREQ_CNTL__stall__SHIFT 0x15
+#define MP_DRAM_CNTL_WRREQ_CNTL__priv_MASK 0x400000
+#define MP_DRAM_CNTL_WRREQ_CNTL__priv__SHIFT 0x16
+#define MP_DRAM_CNTL_WRREQ_CNTL__cid_MASK 0xff800000
+#define MP_DRAM_CNTL_WRREQ_CNTL__cid__SHIFT 0x17
+#define MP_DRAM_CNTL_WRREQ_CNTL_1__vf_MASK 0x1
+#define MP_DRAM_CNTL_WRREQ_CNTL_1__vf__SHIFT 0x0
+#define MP_DRAM_CNTL_WRREQ_CNTL_1__vfid_MASK 0xfe
+#define MP_DRAM_CNTL_WRREQ_CNTL_1__vfid__SHIFT 0x1
+#define MP_DRAM_CNTL_WRREQ_CNTL_1__physical_MASK 0x100
+#define MP_DRAM_CNTL_WRREQ_CNTL_1__physical__SHIFT 0x8
+#define MP_DRAM_CNTL_WRREQ_CNTL_1__snoop_MASK 0x200
+#define MP_DRAM_CNTL_WRREQ_CNTL_1__snoop__SHIFT 0x9
+#define MP_DRAM_CNTL_WRREQ_CNTL_1__inval_MASK 0x400
+#define MP_DRAM_CNTL_WRREQ_CNTL_1__inval__SHIFT 0xa
+#define MP_DRAM_CNTL_WRREQ_CNTL_1__op_MASK 0x3f800
+#define MP_DRAM_CNTL_WRREQ_CNTL_1__op__SHIFT 0xb
+#define MP_DRAM_CNTL_WRREQ_CNTL_1__swap_MASK 0x300000
+#define MP_DRAM_CNTL_WRREQ_CNTL_1__swap__SHIFT 0x14
+#define MP_DRAM_CNTL_WRREQ_CNTL_1__vmid_MASK 0x3c00000
+#define MP_DRAM_CNTL_WRREQ_CNTL_1__vmid__SHIFT 0x16
+#define MP_DRAM_CNTL_WRREQ_CNTL_1__atc_MASK 0x4000000
+#define MP_DRAM_CNTL_WRREQ_CNTL_1__atc__SHIFT 0x1a
+#define MP_DRAM_CNTL_WRREQ_CNTL_1__fed_MASK 0x8000000
+#define MP_DRAM_CNTL_WRREQ_CNTL_1__fed__SHIFT 0x1b
+#define MP_DRAM_CNTL_WRREQ_LOW_ADDR__addr_MASK 0xffffffff
+#define MP_DRAM_CNTL_WRREQ_LOW_ADDR__addr__SHIFT 0x0
+#define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__addr_47_37_MASK 0x7ff
+#define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__addr_47_37__SHIFT 0x0
+#define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__reserved_MASK 0xfffff800
+#define MP_DRAM_CNTL_WRREQ_HIGH_ADDR__reserved__SHIFT 0xb
+#define MP_DRAM_CNTL_WRREQ_MASK__mask_MASK 0xffffffff
+#define MP_DRAM_CNTL_WRREQ_MASK__mask__SHIFT 0x0
+#define MP_DRAM_CNTL_WRREQ_DATA_0__data_MASK 0xffffffff
+#define MP_DRAM_CNTL_WRREQ_DATA_0__data__SHIFT 0x0
+#define MP_DRAM_CNTL_WRREQ_DATA_1__data_MASK 0xffffffff
+#define MP_DRAM_CNTL_WRREQ_DATA_1__data__SHIFT 0x0
+#define MP_DRAM_CNTL_WRREQ_DATA_2__data_MASK 0xffffffff
+#define MP_DRAM_CNTL_WRREQ_DATA_2__data__SHIFT 0x0
+#define MP_DRAM_CNTL_WRREQ_DATA_3__data_MASK 0xffffffff
+#define MP_DRAM_CNTL_WRREQ_DATA_3__data__SHIFT 0x0
+#define MP_DRAM_CNTL_WRREQ_DATA_4__data_MASK 0xffffffff
+#define MP_DRAM_CNTL_WRREQ_DATA_4__data__SHIFT 0x0
+#define MP_DRAM_CNTL_WRREQ_DATA_5__data_MASK 0xffffffff
+#define MP_DRAM_CNTL_WRREQ_DATA_5__data__SHIFT 0x0
+#define MP_DRAM_CNTL_WRREQ_DATA_6__data_MASK 0xffffffff
+#define MP_DRAM_CNTL_WRREQ_DATA_6__data__SHIFT 0x0
+#define MP_DRAM_CNTL_WRREQ_DATA_7__data_MASK 0xffffffff
+#define MP_DRAM_CNTL_WRREQ_DATA_7__data__SHIFT 0x0
+#define MP_DRAM_CNTL_WRREQ_STATUS__credit_counter_MASK 0x1f
+#define MP_DRAM_CNTL_WRREQ_STATUS__credit_counter__SHIFT 0x0
+#define MP_DRAM_CNTL_WRREQ_STATUS__reserved0_MASK 0xe0
+#define MP_DRAM_CNTL_WRREQ_STATUS__reserved0__SHIFT 0x5
+#define MP_DRAM_CNTL_WRREQ_STATUS__fifo_not_empty_MASK 0x100
+#define MP_DRAM_CNTL_WRREQ_STATUS__fifo_not_empty__SHIFT 0x8
+#define MP_DRAM_CNTL_WRREQ_STATUS__reserved1_MASK 0xfe00
+#define MP_DRAM_CNTL_WRREQ_STATUS__reserved1__SHIFT 0x9
+#define MP_DRAM_CNTL_WRREQ_STATUS__tag_pointer_MASK 0xf0000
+#define MP_DRAM_CNTL_WRREQ_STATUS__tag_pointer__SHIFT 0x10
+#define MP_DRAM_CNTL_WRREQ_STATUS__reserved2_MASK 0xfff00000
+#define MP_DRAM_CNTL_WRREQ_STATUS__reserved2__SHIFT 0x14
+#define MP_DRAM_CNTL_WRRET_STATUS_0__valid_MASK 0x1
+#define MP_DRAM_CNTL_WRRET_STATUS_0__valid__SHIFT 0x0
+#define MP_DRAM_CNTL_WRRET_STATUS_0__nack_MASK 0x6
+#define MP_DRAM_CNTL_WRRET_STATUS_0__nack__SHIFT 0x1
+#define MP_DRAM_CNTL_WRRET_STATUS_0__reserved_MASK 0xfff8
+#define MP_DRAM_CNTL_WRRET_STATUS_0__reserved__SHIFT 0x3
+#define MP_DRAM_CNTL_WRRET_STATUS_0__tag_MASK 0xffff0000
+#define MP_DRAM_CNTL_WRRET_STATUS_0__tag__SHIFT 0x10
+#define MP_DRAM_CNTL_RDREQ_ADDR__addr_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDREQ_ADDR__addr__SHIFT 0x0
+#define MP_DRAM_CNTL_RDREQ_CNTL__tag_MASK 0xffff
+#define MP_DRAM_CNTL_RDREQ_CNTL__tag__SHIFT 0x0
+#define MP_DRAM_CNTL_RDREQ_CNTL__mask_MASK 0xff0000
+#define MP_DRAM_CNTL_RDREQ_CNTL__mask__SHIFT 0x10
+#define MP_DRAM_CNTL_RDREQ_CNTL__addr_47_40_MASK 0xff000000
+#define MP_DRAM_CNTL_RDREQ_CNTL__addr_47_40__SHIFT 0x18
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__urg_MASK 0xf
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__urg__SHIFT 0x0
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__stall_MASK 0x10
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__stall__SHIFT 0x4
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__priv_MASK 0x20
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__priv__SHIFT 0x5
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__swap_MASK 0xc0
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__swap__SHIFT 0x6
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__cid_MASK 0x1ff00
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__cid__SHIFT 0x8
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__vmid_MASK 0x1e0000
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__vmid__SHIFT 0x11
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__atc_MASK 0x200000
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__atc__SHIFT 0x15
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__physical_MASK 0x400000
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__physical__SHIFT 0x16
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__exe_MASK 0x800000
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__exe__SHIFT 0x17
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__snoop_MASK 0x1000000
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__snoop__SHIFT 0x18
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__shared_MASK 0x2000000
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__shared__SHIFT 0x19
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__vf_MASK 0x4000000
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__vf__SHIFT 0x1a
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__vfid_MASK 0xf8000000
+#define MP_DRAM_CNTL_RDREQ_CNTL_1__vfid__SHIFT 0x1b
+#define MP_DRAM_CNTL_RDRET_VALID__vld_0_MASK 0x1
+#define MP_DRAM_CNTL_RDRET_VALID__vld_0__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_VALID__vld_1_MASK 0x2
+#define MP_DRAM_CNTL_RDRET_VALID__vld_1__SHIFT 0x1
+#define MP_DRAM_CNTL_RDRET_VALID__vld_2_MASK 0x4
+#define MP_DRAM_CNTL_RDRET_VALID__vld_2__SHIFT 0x2
+#define MP_DRAM_CNTL_RDRET_VALID__vld_3_MASK 0x8
+#define MP_DRAM_CNTL_RDRET_VALID__vld_3__SHIFT 0x3
+#define MP_DRAM_CNTL_RDRET_VALID__vld_4_MASK 0x10
+#define MP_DRAM_CNTL_RDRET_VALID__vld_4__SHIFT 0x4
+#define MP_DRAM_CNTL_RDRET_VALID__vld_5_MASK 0x20
+#define MP_DRAM_CNTL_RDRET_VALID__vld_5__SHIFT 0x5
+#define MP_DRAM_CNTL_RDRET_VALID__vld_6_MASK 0x40
+#define MP_DRAM_CNTL_RDRET_VALID__vld_6__SHIFT 0x6
+#define MP_DRAM_CNTL_RDRET_VALID__vld_7_MASK 0x80
+#define MP_DRAM_CNTL_RDRET_VALID__vld_7__SHIFT 0x7
+#define MP_DRAM_CNTL_RDRET_VALID__reserved_MASK 0xffff00
+#define MP_DRAM_CNTL_RDRET_VALID__reserved__SHIFT 0x8
+#define MP_DRAM_CNTL_RDRET_VALID__atomic_MASK 0xff000000
+#define MP_DRAM_CNTL_RDRET_VALID__atomic__SHIFT 0x18
+#define MP_DRAM_CNTL_RDRET_NACK__nack_0_MASK 0x3
+#define MP_DRAM_CNTL_RDRET_NACK__nack_0__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_NACK__nack_1_MASK 0xc
+#define MP_DRAM_CNTL_RDRET_NACK__nack_1__SHIFT 0x2
+#define MP_DRAM_CNTL_RDRET_NACK__nack_2_MASK 0x30
+#define MP_DRAM_CNTL_RDRET_NACK__nack_2__SHIFT 0x4
+#define MP_DRAM_CNTL_RDRET_NACK__nack_3_MASK 0xc0
+#define MP_DRAM_CNTL_RDRET_NACK__nack_3__SHIFT 0x6
+#define MP_DRAM_CNTL_RDRET_NACK__nack_4_MASK 0x300
+#define MP_DRAM_CNTL_RDRET_NACK__nack_4__SHIFT 0x8
+#define MP_DRAM_CNTL_RDRET_NACK__nack_5_MASK 0xc00
+#define MP_DRAM_CNTL_RDRET_NACK__nack_5__SHIFT 0xa
+#define MP_DRAM_CNTL_RDRET_NACK__nack_6_MASK 0x3000
+#define MP_DRAM_CNTL_RDRET_NACK__nack_6__SHIFT 0xc
+#define MP_DRAM_CNTL_RDRET_NACK__nack_7_MASK 0xc000
+#define MP_DRAM_CNTL_RDRET_NACK__nack_7__SHIFT 0xe
+#define MP_DRAM_CNTL_RDRET_NACK__reserved_MASK 0xffff0000
+#define MP_DRAM_CNTL_RDRET_NACK__reserved__SHIFT 0x10
+#define MP_DRAM_CNTL_RDRET_DATA_0__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_0__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_1__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_1__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_2__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_2__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_3__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_3__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_4__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_4__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_5__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_5__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_6__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_6__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_7__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_7__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_8__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_8__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_9__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_9__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_10__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_10__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_11__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_11__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_12__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_12__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_13__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_13__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_14__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_14__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_15__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_15__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_16__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_16__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_17__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_17__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_18__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_18__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_19__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_19__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_20__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_20__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_21__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_21__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_22__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_22__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_23__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_23__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_24__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_24__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_25__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_25__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_26__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_26__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_27__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_27__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_28__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_28__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_29__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_29__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_30__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_30__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_31__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_31__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_32__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_32__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_33__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_33__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_34__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_34__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_35__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_35__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_36__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_36__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_37__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_37__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_38__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_38__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_39__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_39__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_40__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_40__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_41__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_41__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_42__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_42__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_43__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_43__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_44__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_44__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_45__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_45__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_46__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_46__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_47__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_47__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_48__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_48__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_49__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_49__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_50__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_50__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_51__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_51__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_52__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_52__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_53__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_53__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_54__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_54__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_55__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_55__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_56__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_56__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_57__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_57__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_58__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_58__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_59__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_59__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_60__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_60__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_61__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_61__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_62__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_62__DATA__SHIFT 0x0
+#define MP_DRAM_CNTL_RDRET_DATA_63__DATA_MASK 0xffffffff
+#define MP_DRAM_CNTL_RDRET_DATA_63__DATA__SHIFT 0x0
+#define MP_IOC_CTRL__IOC_mst_send_MASK 0x1
+#define MP_IOC_CTRL__IOC_mst_send__SHIFT 0x0
+#define MP_IOC_CTRL__IOC_mst_stop_MASK 0x2
+#define MP_IOC_CTRL__IOC_mst_stop__SHIFT 0x1
+#define MP_IOC_CTRL__IOC_mst_force_active_MASK 0x4
+#define MP_IOC_CTRL__IOC_mst_force_active__SHIFT 0x2
+#define MP_IOC_CTRL__IOC_mst_rdValid_MASK 0x8
+#define MP_IOC_CTRL__IOC_mst_rdValid__SHIFT 0x3
+#define MP_IOC_CTRL__IOC_mst_busy_MASK 0x10
+#define MP_IOC_CTRL__IOC_mst_busy__SHIFT 0x4
+#define MP_IOC_CTRL__IOC_mst_disabled_MASK 0x20
+#define MP_IOC_CTRL__IOC_mst_disabled__SHIFT 0x5
+#define MP_IOC_CTRL__IOC_mst_debug_rst_MASK 0x40
+#define MP_IOC_CTRL__IOC_mst_debug_rst__SHIFT 0x6
+#define MP_IOC_CTRL__IOC_mst_stop_ack_MASK 0x80
+#define MP_IOC_CTRL__IOC_mst_stop_ack__SHIFT 0x7
+#define MP_IOC_CTRL__IOC_mst_rderr_MASK 0x300
+#define MP_IOC_CTRL__IOC_mst_rderr__SHIFT 0x8
+#define MP_IOC_RDDATA__IOC_mst_rdData_MASK 0xffffffff
+#define MP_IOC_RDDATA__IOC_mst_rdData__SHIFT 0x0
+#define MP_IOC_PHASE1__BiuCqfC_AwqReqCommit_MASK 0x2
+#define MP_IOC_PHASE1__BiuCqfC_AwqReqCommit__SHIFT 0x1
+#define MP_IOC_PHASE1__BiuCqfC_AltReqRdCmd_MASK 0x4
+#define MP_IOC_PHASE1__BiuCqfC_AltReqRdCmd__SHIFT 0x2
+#define MP_IOC_PHASE1__BiuCqfC_AltReqAddrLo_MASK 0xfffffff8
+#define MP_IOC_PHASE1__BiuCqfC_AltReqAddrLo__SHIFT 0x3
+#define MP_IOC_PHASE2__BiuCqfC_AltReqAddrMid_MASK 0xff
+#define MP_IOC_PHASE2__BiuCqfC_AltReqAddrMid__SHIFT 0x0
+#define MP_IOC_PHASE2__BiuCqfC_AltReqMask_MASK 0xff00
+#define MP_IOC_PHASE2__BiuCqfC_AltReqMask__SHIFT 0x8
+#define MP_IOC_PHASE2__BiuCqfC_AltReqSize_MASK 0x30000
+#define MP_IOC_PHASE2__BiuCqfC_AltReqSize__SHIFT 0x10
+#define MP_IOC_PHASE2__BiuCqfC_AltReqAddrHi_MASK 0xff000000
+#define MP_IOC_PHASE2__BiuCqfC_AltReqAddrHi__SHIFT 0x18
+#define MP_IOC_PHASE3__BiuDbfC_C2aDataOut_MASK 0xffffffff
+#define MP_IOC_PHASE3__BiuDbfC_C2aDataOut__SHIFT 0x0
+#define MP_IOC_READ_0__data_MASK 0xffffffff
+#define MP_IOC_READ_0__data__SHIFT 0x0
+#define MP_IOC_READ_1__data_MASK 0xffffffff
+#define MP_IOC_READ_1__data__SHIFT 0x0
+#define MP_IOC_READ_2__data_MASK 0xffffffff
+#define MP_IOC_READ_2__data__SHIFT 0x0
+#define MP_IOC_READ_3__data_MASK 0xffffffff
+#define MP_IOC_READ_3__data__SHIFT 0x0
+#define MP_IOC_READ_4__data_MASK 0xffffffff
+#define MP_IOC_READ_4__data__SHIFT 0x0
+#define MP_IOC_READ_5__data_MASK 0xffffffff
+#define MP_IOC_READ_5__data__SHIFT 0x0
+#define MP_IOC_READ_6__data_MASK 0xffffffff
+#define MP_IOC_READ_6__data__SHIFT 0x0
+#define MP_IOC_READ_7__data_MASK 0xffffffff
+#define MP_IOC_READ_7__data__SHIFT 0x0
+#define MP_IOC_READ_8__data_MASK 0xffffffff
+#define MP_IOC_READ_8__data__SHIFT 0x0
+#define MP_IOC_READ_9__data_MASK 0xffffffff
+#define MP_IOC_READ_9__data__SHIFT 0x0
+#define MP_IOC_READ_10__data_MASK 0xffffffff
+#define MP_IOC_READ_10__data__SHIFT 0x0
+#define MP_IOC_READ_11__data_MASK 0xffffffff
+#define MP_IOC_READ_11__data__SHIFT 0x0
+#define MP_IOC_READ_12__data_MASK 0xffffffff
+#define MP_IOC_READ_12__data__SHIFT 0x0
+#define MP_IOC_READ_13__data_MASK 0xffffffff
+#define MP_IOC_READ_13__data__SHIFT 0x0
+#define MP_IOC_READ_14__data_MASK 0xffffffff
+#define MP_IOC_READ_14__data__SHIFT 0x0
+#define MP_IOC_READ_15__data_MASK 0xffffffff
+#define MP_IOC_READ_15__data__SHIFT 0x0
+#define MP_IOC_WRITE_0__data_MASK 0xffffffff
+#define MP_IOC_WRITE_0__data__SHIFT 0x0
+#define MP_IOC_WRITE_1__data_MASK 0xffffffff
+#define MP_IOC_WRITE_1__data__SHIFT 0x0
+#define MP_IOC_WRITE_2__data_MASK 0xffffffff
+#define MP_IOC_WRITE_2__data__SHIFT 0x0
+#define MP_IOC_WRITE_3__data_MASK 0xffffffff
+#define MP_IOC_WRITE_3__data__SHIFT 0x0
+#define MP_IOC_WRITE_4__data_MASK 0xffffffff
+#define MP_IOC_WRITE_4__data__SHIFT 0x0
+#define MP_IOC_WRITE_5__data_MASK 0xffffffff
+#define MP_IOC_WRITE_5__data__SHIFT 0x0
+#define MP_IOC_WRITE_6__data_MASK 0xffffffff
+#define MP_IOC_WRITE_6__data__SHIFT 0x0
+#define MP_IOC_WRITE_7__data_MASK 0xffffffff
+#define MP_IOC_WRITE_7__data__SHIFT 0x0
+#define MP_IOC_WRITE_8__data_MASK 0xffffffff
+#define MP_IOC_WRITE_8__data__SHIFT 0x0
+#define MP_IOC_WRITE_9__data_MASK 0xffffffff
+#define MP_IOC_WRITE_9__data__SHIFT 0x0
+#define MP_IOC_WRITE_10__data_MASK 0xffffffff
+#define MP_IOC_WRITE_10__data__SHIFT 0x0
+#define MP_IOC_WRITE_11__data_MASK 0xffffffff
+#define MP_IOC_WRITE_11__data__SHIFT 0x0
+#define MP_IOC_WRITE_12__data_MASK 0xffffffff
+#define MP_IOC_WRITE_12__data__SHIFT 0x0
+#define MP_IOC_WRITE_13__data_MASK 0xffffffff
+#define MP_IOC_WRITE_13__data__SHIFT 0x0
+#define MP_IOC_WRITE_14__data_MASK 0xffffffff
+#define MP_IOC_WRITE_14__data__SHIFT 0x0
+#define MP_IOC_WRITE_15__data_MASK 0xffffffff
+#define MP_IOC_WRITE_15__data__SHIFT 0x0
+#define MP_INTERRUPT_CONTROL__MAX_CREDIT_VALUE_MASK 0x1f
+#define MP_INTERRUPT_CONTROL__MAX_CREDIT_VALUE__SHIFT 0x0
+#define MP_INTERRUPT_CONTROL__MP0_SW_TRIG_MASK_MASK 0x20
+#define MP_INTERRUPT_CONTROL__MP0_SW_TRIG_MASK__SHIFT 0x5
+#define MP_INTERRUPT_CONTROL__MP0_SW_INT_ACK_MASK 0x40
+#define MP_INTERRUPT_CONTROL__MP0_SW_INT_ACK__SHIFT 0x6
+#define MP_INTERRUPT_CONTROL__MP1_SW_TRIG_MASK_MASK 0x80
+#define MP_INTERRUPT_CONTROL__MP1_SW_TRIG_MASK__SHIFT 0x7
+#define MP_INTERRUPT_CONTROL__MP1_SW_INT_ACK_MASK 0x100
+#define MP_INTERRUPT_CONTROL__MP1_SW_INT_ACK__SHIFT 0x8
+#define MP0_SW_INT__VALID_MASK 0x1
+#define MP0_SW_INT__VALID__SHIFT 0x0
+#define MP0_SW_INT__INT_ID_MASK 0x1fe
+#define MP0_SW_INT__INT_ID__SHIFT 0x1
+#define MP0_SW_INT_CTXID__CTXID_MASK 0xfffffff
+#define MP0_SW_INT_CTXID__CTXID__SHIFT 0x0
+#define MP1_SW_INT__VALID_MASK 0x1
+#define MP1_SW_INT__VALID__SHIFT 0x0
+#define MP1_SW_INT__INT_ID_MASK 0x1fe
+#define MP1_SW_INT__INT_ID__SHIFT 0x1
+#define MP1_SW_INT_CTXID__CTXID_MASK 0xfffffff
+#define MP1_SW_INT_CTXID__CTXID__SHIFT 0x0
+#define DISP_TIMER_ID__DISP_T0_INT_ID_MASK 0xff
+#define DISP_TIMER_ID__DISP_T0_INT_ID__SHIFT 0x0
+#define DISP_TIMER_ID__DISP_T1_INT_ID_MASK 0xff00
+#define DISP_TIMER_ID__DISP_T1_INT_ID__SHIFT 0x8
+#define PWRHW_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
+#define PWRHW_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
+#define PWRHW_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
+#define PWRHW_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
+#define CURRENT_STATE_CPU0__CURRENT_PSTATE_ID_MASK 0x7
+#define CURRENT_STATE_CPU0__CURRENT_PSTATE_ID__SHIFT 0x0
+#define CURRENT_STATE_CPU0__CURRENT_DID_MASK 0x38
+#define CURRENT_STATE_CPU0__CURRENT_DID__SHIFT 0x3
+#define CURRENT_STATE_CPU0__CURRENT_FID_MASK 0xfc0
+#define CURRENT_STATE_CPU0__CURRENT_FID__SHIFT 0x6
+#define CURRENT_STATE_CPU0__CPU_COF_MASK 0xfff000
+#define CURRENT_STATE_CPU0__CPU_COF__SHIFT 0xc
+#define CURRENT_STATE_CPU0__CPU_COF_IND_PROG_MASK 0x7f000000
+#define CURRENT_STATE_CPU0__CPU_COF_IND_PROG__SHIFT 0x18
+#define CURRENT_STATE_CPU1__CURRENT_PSTATE_ID_MASK 0x7
+#define CURRENT_STATE_CPU1__CURRENT_PSTATE_ID__SHIFT 0x0
+#define CURRENT_STATE_CPU1__CURRENT_DID_MASK 0x38
+#define CURRENT_STATE_CPU1__CURRENT_DID__SHIFT 0x3
+#define CURRENT_STATE_CPU1__CURRENT_FID_MASK 0xfc0
+#define CURRENT_STATE_CPU1__CURRENT_FID__SHIFT 0x6
+#define CURRENT_STATE_CPU1__CPU_COF_MASK 0xfff000
+#define CURRENT_STATE_CPU1__CPU_COF__SHIFT 0xc
+#define CURRENT_STATE_CPU1__CPU_COF_IND_PROG_MASK 0x7f000000
+#define CURRENT_STATE_CPU1__CPU_COF_IND_PROG__SHIFT 0x18
+#define CPU_REDUN_DONE0__CPU_REDUN_DONE_MASK 0x1
+#define CPU_REDUN_DONE0__CPU_REDUN_DONE__SHIFT 0x0
+#define CPU_REDUN_DONE1__CPU_REDUN_DONE_MASK 0x1
+#define CPU_REDUN_DONE1__CPU_REDUN_DONE__SHIFT 0x0
+#define CURRENT_VID_CPU0__CURRENT_VID_MASK 0xff
+#define CURRENT_VID_CPU0__CURRENT_VID__SHIFT 0x0
+#define CURRENT_VID_CPU1__CURRENT_VID_MASK 0xff
+#define CURRENT_VID_CPU1__CURRENT_VID__SHIFT 0x0
+#define UNBPM_PWRMGT_ACK__REQUESTOR_CODE_MASK 0x1f
+#define UNBPM_PWRMGT_ACK__REQUESTOR_CODE__SHIFT 0x0
+#define UNBPM_PWRMGT_ACK__REQUEST_ACK_MASK 0x100
+#define UNBPM_PWRMGT_ACK__REQUEST_ACK__SHIFT 0x8
+#define UNBPM_PWRMGT_ACK__REQUEST_NACK_MASK 0x10000
+#define UNBPM_PWRMGT_ACK__REQUEST_NACK__SHIFT 0x10
+#define UNBPM_PWRMGT_ACK__ERROR_CODE_MASK 0xff000000
+#define UNBPM_PWRMGT_ACK__ERROR_CODE__SHIFT 0x18
+#define CURRENT_FREQ_STATE_NB__CURRENT_FID_MASK 0xff
+#define CURRENT_FREQ_STATE_NB__CURRENT_FID__SHIFT 0x0
+#define CURRENT_FREQ_STATE_NB__CURRENT_DID_MASK 0xff00
+#define CURRENT_FREQ_STATE_NB__CURRENT_DID__SHIFT 0x8
+#define CURRENT_FREQ_STATE_NB__NB_LOW_POWER_MASK 0xff0000
+#define CURRENT_FREQ_STATE_NB__NB_LOW_POWER__SHIFT 0x10
+#define CURRENT_FREQ_STATE_NB__NB_STUTTER_MODE_MASK 0xff000000
+#define CURRENT_FREQ_STATE_NB__NB_STUTTER_MODE__SHIFT 0x18
+#define CURRENT_PSTATE_NB__CURRENT_PSTATE_ID_MASK 0xff
+#define CURRENT_PSTATE_NB__CURRENT_PSTATE_ID__SHIFT 0x0
+#define CURRENT_PSTATE_NB__CURRENT_PSTATE_LO_MASK 0x100
+#define CURRENT_PSTATE_NB__CURRENT_PSTATE_LO__SHIFT 0x8
+#define CURRENT_PSTATE_NB__CURRENT_MEM_PSTATE_ID_MASK 0x200
+#define CURRENT_PSTATE_NB__CURRENT_MEM_PSTATE_ID__SHIFT 0x9
+#define UNBPM_MSG_INT_CONFIG__MSG_REG_TARGET_ADDR_MASK 0xffffffff
+#define UNBPM_MSG_INT_CONFIG__MSG_REG_TARGET_ADDR__SHIFT 0x0
+#define UNBPM_NBPWRMGT_CMD__TARGET_BLOCK_MASK 0x3
+#define UNBPM_NBPWRMGT_CMD__TARGET_BLOCK__SHIFT 0x0
+#define UNBPM_NBPWRMGT_CMD__TARGET_CMD_MASK 0x100
+#define UNBPM_NBPWRMGT_CMD__TARGET_CMD__SHIFT 0x8
+#define UNBPM_NBPWRMGT_CMD__DCT_SR_MAP_MASK 0xff0000
+#define UNBPM_NBPWRMGT_CMD__DCT_SR_MAP__SHIFT 0x10
+#define UNBPM_NBPWRMGT_CMD__RETURN_NB_ACK_MASK 0x1000000
+#define UNBPM_NBPWRMGT_CMD__RETURN_NB_ACK__SHIFT 0x18
+#define UNBPM_NBPWRMGT_CMD__OVERRIDE_PARAMS_MASK 0x2000000
+#define UNBPM_NBPWRMGT_CMD__OVERRIDE_PARAMS__SHIFT 0x19
+#define UNBPM_NBPWRMGT_CMD__SET_NB_LOW_POWER_MASK 0x4000000
+#define UNBPM_NBPWRMGT_CMD__SET_NB_LOW_POWER__SHIFT 0x1a
+#define UNBPM_NBPWRMGT_CMD__SET_NB_STUTTER_MODE_MASK 0x8000000
+#define UNBPM_NBPWRMGT_CMD__SET_NB_STUTTER_MODE__SHIFT 0x1b
+#define UNBPM_NBPWRMGT_FSM_CFG__DIS_AUTO_PWRGATE_ON_EXIT_MASK 0x2
+#define UNBPM_NBPWRMGT_FSM_CFG__DIS_AUTO_PWRGATE_ON_EXIT__SHIFT 0x1
+#define DDR0_FUSE_SSB_XFER__START_STATUS_XFER_MASK 0x1
+#define DDR0_FUSE_SSB_XFER__START_STATUS_XFER__SHIFT 0x0
+#define DDR0_FUSE_SSB_XFER_CFG__FUSE_DDR0_LAST_ADDR_MASK 0x7ff
+#define DDR0_FUSE_SSB_XFER_CFG__FUSE_DDR0_LAST_ADDR__SHIFT 0x0
+#define DDR1_FUSE_SSB_XFER__START_STATUS_XFER_MASK 0x1
+#define DDR1_FUSE_SSB_XFER__START_STATUS_XFER__SHIFT 0x0
+#define DDR1_FUSE_SSB_XFER_CFG__FUSE_DDR1_LAST_ADDR_MASK 0x7ff
+#define DDR1_FUSE_SSB_XFER_CFG__FUSE_DDR1_LAST_ADDR__SHIFT 0x0
+#define UNBPM_FUSES_VAL_PWROK__CK_FUSES_VAL_PWROK_MASK 0x1
+#define UNBPM_FUSES_VAL_PWROK__CK_FUSES_VAL_PWROK__SHIFT 0x0
+#define SYNFIFO_CLK_RATIO__CK_CCLK_IS_FASTER0_MASK 0x1
+#define SYNFIFO_CLK_RATIO__CK_CCLK_IS_FASTER0__SHIFT 0x0
+#define SYNFIFO_CLK_RATIO__CK_CCLK_IS_FASTER1_MASK 0x2
+#define SYNFIFO_CLK_RATIO__CK_CCLK_IS_FASTER1__SHIFT 0x1
+#define SYNFIFO_CLK_RATIO__CK_NCLK_IS_FASTER0_MASK 0x4
+#define SYNFIFO_CLK_RATIO__CK_NCLK_IS_FASTER0__SHIFT 0x2
+#define SYNFIFO_CLK_RATIO__CK_NCLK_IS_FASTER1_MASK 0x8
+#define SYNFIFO_CLK_RATIO__CK_NCLK_IS_FASTER1__SHIFT 0x3
+#define SYNFIFO_CLK_RATIO__CK_SYNFIFO_ASYNC_EN0_MASK 0x10
+#define SYNFIFO_CLK_RATIO__CK_SYNFIFO_ASYNC_EN0__SHIFT 0x4
+#define SYNFIFO_CLK_RATIO__CK_SYNFIFO_ASYNC_EN1_MASK 0x20
+#define SYNFIFO_CLK_RATIO__CK_SYNFIFO_ASYNC_EN1__SHIFT 0x5
+#define MISC_SMU_PWRMGT_CFG0__TARGET_ADDR_MASK 0xffffffff
+#define MISC_SMU_PWRMGT_CFG0__TARGET_ADDR__SHIFT 0x0
+#define MISC_GNB_PWRMGT_CFG1__TIMER_EN_MASK 0x1
+#define MISC_GNB_PWRMGT_CFG1__TIMER_EN__SHIFT 0x0
+#define MISC_GNB_PWRMGT_CFG1__TIMER_INTERVAL_MASK 0x1fffe
+#define MISC_GNB_PWRMGT_CFG1__TIMER_INTERVAL__SHIFT 0x1
+#define MISC_GNB_PWRMGT_CFG1__INT_GEN_EN_MASK 0x20000
+#define MISC_GNB_PWRMGT_CFG1__INT_GEN_EN__SHIFT 0x11
+#define MISC_SMU_PWRMGT_CFG1__TIMER_EN_MASK 0x1
+#define MISC_SMU_PWRMGT_CFG1__TIMER_EN__SHIFT 0x0
+#define MISC_SMU_PWRMGT_CFG1__TIMER_INTERVAL_MASK 0x1fffe
+#define MISC_SMU_PWRMGT_CFG1__TIMER_INTERVAL__SHIFT 0x1
+#define MISC_SMU_PWRMGT_CFG1__INT_GEN_EN_MASK 0x20000
+#define MISC_SMU_PWRMGT_CFG1__INT_GEN_EN__SHIFT 0x11
+#define MISC_GNB_PWRMGT_DATA__GN_ON_INB_WAKE_MASK 0x1
+#define MISC_GNB_PWRMGT_DATA__GN_ON_INB_WAKE__SHIFT 0x0
+#define MISC_GNB_PWRMGT_DATA__GN_ALLOW_NB_PSTATES_MASK 0x2
+#define MISC_GNB_PWRMGT_DATA__GN_ALLOW_NB_PSTATES__SHIFT 0x1
+#define MISC_GNB_PWRMGT_DATA__GN_FLUSH_REQ_TOGGLE_MASK 0x4
+#define MISC_GNB_PWRMGT_DATA__GN_FLUSH_REQ_TOGGLE__SHIFT 0x2
+#define MISC_GNB_PWRMGT_DATA__GN_CROSS_TRIGGER_MASK 0x78
+#define MISC_GNB_PWRMGT_DATA__GN_CROSS_TRIGGER__SHIFT 0x3
+#define MISC_GNB_PWRMGT_DATA__GN_STOP_CLOCKS_MASK 0x80
+#define MISC_GNB_PWRMGT_DATA__GN_STOP_CLOCKS__SHIFT 0x7
+#define MISC_GNB_PWRMGT_DATA__GN_ON3_CH0LINK_WAKE_MASK 0x100
+#define MISC_GNB_PWRMGT_DATA__GN_ON3_CH0LINK_WAKE__SHIFT 0x8
+#define MISC_GNB_PWRMGT_DATA__GN_ON3_CH1LINK_WAKE_MASK 0x200
+#define MISC_GNB_PWRMGT_DATA__GN_ON3_CH1LINK_WAKE__SHIFT 0x9
+#define GN_GNB_SLOW__GN_GNB_SLOW_DATA_MASK 0x1
+#define GN_GNB_SLOW__GN_GNB_SLOW_DATA__SHIFT 0x0
+#define GN_FORCE_NBPS1__GN_FORCE_NBPS1_DATA_MASK 0x1
+#define GN_FORCE_NBPS1__GN_FORCE_NBPS1_DATA__SHIFT 0x0
+#define MISC_SMU_PWRMGT_DATA__NB_NBPS_MASK 0x1
+#define MISC_SMU_PWRMGT_DATA__NB_NBPS__SHIFT 0x0
+#define MISC_SMU_PWRMGT_DATA__NB_MEMPS_MASK 0x2
+#define MISC_SMU_PWRMGT_DATA__NB_MEMPS__SHIFT 0x1
+#define NB_COF__NB_COF_MASK 0xffff
+#define NB_COF__NB_COF__SHIFT 0x0
+#define UNBPM_CK_IRESET__CK_IRESET_LOCAL_MASK 0x1
+#define UNBPM_CK_IRESET__CK_IRESET_LOCAL__SHIFT 0x0
+#define CURRENT_VID_NB__CURRENT_VID_MASK 0xff
+#define CURRENT_VID_NB__CURRENT_VID__SHIFT 0x0
+#define SPR_FUSE_PSTATEPWR1__PwrValue0_MASK 0xff
+#define SPR_FUSE_PSTATEPWR1__PwrValue0__SHIFT 0x0
+#define SPR_FUSE_PSTATEPWR1__PwrValue1_MASK 0xff00
+#define SPR_FUSE_PSTATEPWR1__PwrValue1__SHIFT 0x8
+#define SPR_FUSE_PSTATEPWR1__PwrValue2_MASK 0xff0000
+#define SPR_FUSE_PSTATEPWR1__PwrValue2__SHIFT 0x10
+#define SPR_FUSE_PSTATEPWR1__PwrValue3_MASK 0xff000000
+#define SPR_FUSE_PSTATEPWR1__PwrValue3__SHIFT 0x18
+#define SPR_FUSE_PSTATEPWR2__PwrValue4_MASK 0xff
+#define SPR_FUSE_PSTATEPWR2__PwrValue4__SHIFT 0x0
+#define SPR_FUSE_PSTATEPWR2__PwrDiv0_MASK 0x300
+#define SPR_FUSE_PSTATEPWR2__PwrDiv0__SHIFT 0x8
+#define SPR_FUSE_PSTATEPWR2__PwrDiv1_MASK 0xc00
+#define SPR_FUSE_PSTATEPWR2__PwrDiv1__SHIFT 0xa
+#define SPR_FUSE_PSTATEPWR2__PwrDiv2_MASK 0x3000
+#define SPR_FUSE_PSTATEPWR2__PwrDiv2__SHIFT 0xc
+#define SPR_FUSE_PSTATEPWR2__PwrDiv3_MASK 0xc000
+#define SPR_FUSE_PSTATEPWR2__PwrDiv3__SHIFT 0xe
+#define SPR_FUSE_PSTATEPWR2__PwrDiv4_MASK 0x30000
+#define SPR_FUSE_PSTATEPWR2__PwrDiv4__SHIFT 0x10
+#define SPR_FUSE_PSTATEPWR2__PwrDiv5_MASK 0xc0000
+#define SPR_FUSE_PSTATEPWR2__PwrDiv5__SHIFT 0x12
+#define SPR_FUSE_PSTATEPWR2__PwrDiv6_MASK 0x300000
+#define SPR_FUSE_PSTATEPWR2__PwrDiv6__SHIFT 0x14
+#define SPR_FUSE_PSTATEPWR2__PwrDiv7_MASK 0xc00000
+#define SPR_FUSE_PSTATEPWR2__PwrDiv7__SHIFT 0x16
+#define SPR_FUSE_PSTATEPWR2__Reserved_MASK 0xff000000
+#define SPR_FUSE_PSTATEPWR2__Reserved__SHIFT 0x18
+#define SPR_FUSE_PSTATEPWR3__PwrValue5_MASK 0xff
+#define SPR_FUSE_PSTATEPWR3__PwrValue5__SHIFT 0x0
+#define SPR_FUSE_PSTATEPWR3__PwrValue6_MASK 0xff00
+#define SPR_FUSE_PSTATEPWR3__PwrValue6__SHIFT 0x8
+#define SPR_FUSE_PSTATEPWR3__PwrValue7_MASK 0xff0000
+#define SPR_FUSE_PSTATEPWR3__PwrValue7__SHIFT 0x10
+#define SPR_FUSE_PSTATEPWR3__Reserved_MASK 0xff000000
+#define SPR_FUSE_PSTATEPWR3__Reserved__SHIFT 0x18
+#define SPR_FUSE_THERMAL_SCRATCH__ThermalScratch_MASK 0xffffffff
+#define SPR_FUSE_THERMAL_SCRATCH__ThermalScratch__SHIFT 0x0
+#define SPR_PRODUCT_INFO0__BrandId_MASK 0xffff
+#define SPR_PRODUCT_INFO0__BrandId__SHIFT 0x0
+#define SPR_PRODUCT_INFO0__Reserved0_MASK 0x70000
+#define SPR_PRODUCT_INFO0__Reserved0__SHIFT 0x10
+#define SPR_PRODUCT_INFO0__SerialNumRdDis_MASK 0x80000
+#define SPR_PRODUCT_INFO0__SerialNumRdDis__SHIFT 0x13
+#define SPR_PRODUCT_INFO0__Reserved1_MASK 0xfff00000
+#define SPR_PRODUCT_INFO0__Reserved1__SHIFT 0x14
+#define SPR_SERIALNUM_REG1__SPR_SERIALNUM_REG1_MASK 0xffffffff
+#define SPR_SERIALNUM_REG1__SPR_SERIALNUM_REG1__SHIFT 0x0
+#define SPR_SERIALNUM_REG2__SPR_SERIALNUM_REG2_MASK 0xffffffff
+#define SPR_SERIALNUM_REG2__SPR_SERIALNUM_REG2__SHIFT 0x0
+#define SPR_PRODUCT_INFO1__DiDtMode_MASK 0x1
+#define SPR_PRODUCT_INFO1__DiDtMode__SHIFT 0x0
+#define SPR_PRODUCT_INFO1__DiDtCfg0_MASK 0x3e
+#define SPR_PRODUCT_INFO1__DiDtCfg0__SHIFT 0x1
+#define SPR_PRODUCT_INFO1__DiDtCfg1_MASK 0x3fc0
+#define SPR_PRODUCT_INFO1__DiDtCfg1__SHIFT 0x6
+#define SPR_PRODUCT_INFO1__DiDtCfg2_MASK 0xc000
+#define SPR_PRODUCT_INFO1__DiDtCfg2__SHIFT 0xe
+#define SPR_PRODUCT_INFO1__DiDtCfg3_MASK 0x10000
+#define SPR_PRODUCT_INFO1__DiDtCfg3__SHIFT 0x10
+#define SPR_PRODUCT_INFO1__DiDtCfg4_MASK 0x1e0000
+#define SPR_PRODUCT_INFO1__DiDtCfg4__SHIFT 0x11
+#define SPR_PRODUCT_INFO1__Reserved_MASK 0xffe00000
+#define SPR_PRODUCT_INFO1__Reserved__SHIFT 0x15
+#define SPR_EXT_PRODUCT_INFO__Reserved_MASK 0xffffffff
+#define SPR_EXT_PRODUCT_INFO__Reserved__SHIFT 0x0
+#define SPR_MSIDFUSE__MSID_MASK 0xffffff
+#define SPR_MSIDFUSE__MSID__SHIFT 0x0
+#define SPR_MSIDFUSE__Reserved_MASK 0xff000000
+#define SPR_MSIDFUSE__Reserved__SHIFT 0x18
+#define SPR_LINK_PRODUCT_INFO__Reserved_MASK 0xffffffff
+#define SPR_LINK_PRODUCT_INFO__Reserved__SHIFT 0x0
+#define SPR_BRAND_NAME_ADDR__Index_MASK 0xf
+#define SPR_BRAND_NAME_ADDR__Index__SHIFT 0x0
+#define SPR_BRAND_NAME_ADDR__Reserved_MASK 0xfffffff0
+#define SPR_BRAND_NAME_ADDR__Reserved__SHIFT 0x4
+#define SPR_BRAND_NAME_DATA__DATA_MASK 0xffffffff
+#define SPR_BRAND_NAME_DATA__DATA__SHIFT 0x0
+#define SPR_COMBO_PHY_PRODUCT_INFO__SPR_COMBO_PHY_PRODUCT_INFO_MASK 0xffffffff
+#define SPR_COMBO_PHY_PRODUCT_INFO__SPR_COMBO_PHY_PRODUCT_INFO__SHIFT 0x0
+#define MISC_GNB_PWRMGT_CFG0__TARGET_ADDR_MASK 0xffffffff
+#define MISC_GNB_PWRMGT_CFG0__TARGET_ADDR__SHIFT 0x0
+#define UNBPM_EXIT_TO_PSTATE__EXIT_TO_PSTATE_MASK 0x1
+#define UNBPM_EXIT_TO_PSTATE__EXIT_TO_PSTATE__SHIFT 0x0
+#define UNBPM_WARM_RESET_HS_STATUS__NB_CSTATE_ACTIVE_MASK 0x1
+#define UNBPM_WARM_RESET_HS_STATUS__NB_CSTATE_ACTIVE__SHIFT 0x0
+#define UNBPM_WARM_RESET_HS_STATUS__WARM_RESET_HS_DONE_MASK 0x2
+#define UNBPM_WARM_RESET_HS_STATUS__WARM_RESET_HS_DONE__SHIFT 0x1
+#define UNBPM_VOLTAGE_CNTL__VOLTAGE_EN_MASK 0x1
+#define UNBPM_VOLTAGE_CNTL__VOLTAGE_EN__SHIFT 0x0
+#define UNBPM_VOLTAGE_CNTL__VOLTAGE_LEVEL_MASK 0x1fe
+#define UNBPM_VOLTAGE_CNTL__VOLTAGE_LEVEL__SHIFT 0x1
+#define UNBPM_VOLTAGE_STATUS__VOLTAGE_STATUS_MASK 0x1
+#define UNBPM_VOLTAGE_STATUS__VOLTAGE_STATUS__SHIFT 0x0
+#define UNBPM_VOLTAGE_STATUS__VOLTAGE_CURRENT_LEVEL_MASK 0x1fe
+#define UNBPM_VOLTAGE_STATUS__VOLTAGE_CURRENT_LEVEL__SHIFT 0x1
+#define NUM_BOOST_STATES__NUM_BOOST_STATES_MASK 0x7
+#define NUM_BOOST_STATES__NUM_BOOST_STATES__SHIFT 0x0
+#define WARM_RESET_NB_CONTROL__WARM_RESET_CPU_VID_MASK 0xff
+#define WARM_RESET_NB_CONTROL__WARM_RESET_CPU_VID__SHIFT 0x0
+#define WARM_RESET_NB_CONTROL__NB_DISABLE_CORE_MASK 0xff00
+#define WARM_RESET_NB_CONTROL__NB_DISABLE_CORE__SHIFT 0x8
+#define ONION_NO_STREAMS_PEND__ONION_NO_STREAMS_PEND_MASK 0x1
+#define ONION_NO_STREAMS_PEND__ONION_NO_STREAMS_PEND__SHIFT 0x0
+#define ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_0_MASK 0x2
+#define ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_0__SHIFT 0x1
+#define ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_1_MASK 0x4
+#define ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_1__SHIFT 0x2
+#define SPR_PROGRAMMABLE_CTRL__PllRegUpTime_MASK 0x3
+#define SPR_PROGRAMMABLE_CTRL__PllRegUpTime__SHIFT 0x0
+#define SPR_PROGRAMMABLE_CTRL__PllVddOutUpTime_MASK 0xc
+#define SPR_PROGRAMMABLE_CTRL__PllVddOutUpTime__SHIFT 0x2
+#define SPR_PROGRAMMABLE_CTRL__ResonanceTime_MASK 0x30
+#define SPR_PROGRAMMABLE_CTRL__ResonanceTime__SHIFT 0x4
+#define SPR_PROGRAMMABLE_CTRL__C6PLLPwrDnReg_MASK 0x40
+#define SPR_PROGRAMMABLE_CTRL__C6PLLPwrDnReg__SHIFT 0x6
+#define SPR_PROGRAMMABLE_CTRL__CC6PLLPwrDnVCO_MASK 0x80
+#define SPR_PROGRAMMABLE_CTRL__CC6PLLPwrDnVCO__SHIFT 0x7
+#define SPR_PROGRAMMABLE_CTRL__CC6PLLPwrDnReg_MASK 0x100
+#define SPR_PROGRAMMABLE_CTRL__CC6PLLPwrDnReg__SHIFT 0x8
+#define SPR_PROGRAMMABLE_CTRL__NbPLLPwrDnReg_MASK 0x200
+#define SPR_PROGRAMMABLE_CTRL__NbPLLPwrDnReg__SHIFT 0x9
+#define SPR_PROGRAMMABLE_CTRL__SOIWait_MASK 0x3c00
+#define SPR_PROGRAMMABLE_CTRL__SOIWait__SHIFT 0xa
+#define PHN_FUSERX_MISC_FUSES__Spare_MASK 0xff
+#define PHN_FUSERX_MISC_FUSES__Spare__SHIFT 0x0
+#define PHN_FUSERX_MISC_FUSES__OverClockRefClkDis_MASK 0x100
+#define PHN_FUSERX_MISC_FUSES__OverClockRefClkDis__SHIFT 0x8
+#define PHN_FUSERX_MISC_FUSES__MemPstate_MASK 0x1e00
+#define PHN_FUSERX_MISC_FUSES__MemPstate__SHIFT 0x9
+#define PHN_FUSERX_MISC_FUSES__NbPstateHi_MASK 0x6000
+#define PHN_FUSERX_MISC_FUSES__NbPstateHi__SHIFT 0xd
+#define PHN_FUSERX_MISC_FUSES__NbPstateLo_MASK 0x18000
+#define PHN_FUSERX_MISC_FUSES__NbPstateLo__SHIFT 0xf
+#define PHN_FUSERX_MISC_FUSES__ScanCLK400MHz_MASK 0x20000
+#define PHN_FUSERX_MISC_FUSES__ScanCLK400MHz__SHIFT 0x11
+#define PHN_FUSERX_MISC_FUSES__CoreDis_MASK 0x3c0000
+#define PHN_FUSERX_MISC_FUSES__CoreDis__SHIFT 0x12
+#define PHN_FUSERX_MISC_FUSES__PHN_FusesValid_MASK 0x80000000
+#define PHN_FUSERX_MISC_FUSES__PHN_FusesValid__SHIFT 0x1f
+#define UNBPM_PWRCTRL_MISC__PWRGATEMASTERDIS_MASK 0x1
+#define UNBPM_PWRCTRL_MISC__PWRGATEMASTERDIS__SHIFT 0x0
+#define CSTATE_ACTIVE_SAMPLER__SAMPLE_TIME_MASK 0x1f
+#define CSTATE_ACTIVE_SAMPLER__SAMPLE_TIME__SHIFT 0x0
+#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_QOS_MASK 0xf
+#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_QOS__SHIFT 0x0
+#define UNBPM_DEBUG_CONFIG_STATUS__FIFO_BUFF_FLUSH_MASK 0x10
+#define UNBPM_DEBUG_CONFIG_STATUS__FIFO_BUFF_FLUSH__SHIFT 0x4
+#define UNBPM_DEBUG_CONFIG_STATUS__MASTER_DEBUG_EN_MASK 0x20
+#define UNBPM_DEBUG_CONFIG_STATUS__MASTER_DEBUG_EN__SHIFT 0x5
+#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_ACTIVE_MASK 0x100
+#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_ACTIVE__SHIFT 0x8
+#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_BUSY_MASK 0x200
+#define UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_BUSY__SHIFT 0x9
+#define UNBPM_DEBUG_CONFIG_STATUS__FIFO_DATA_COUNT_MASK 0x3c00
+#define UNBPM_DEBUG_CONFIG_STATUS__FIFO_DATA_COUNT__SHIFT 0xa
+#define UNBPM_DEBUG_CONFIG_STATUS__MST_OUTSTANDING_TRANS_MASK 0xff0000
+#define UNBPM_DEBUG_CONFIG_STATUS__MST_OUTSTANDING_TRANS__SHIFT 0x10
+#define UNBPM_AXIMST_LAST_CMD__AXI_MASTER_LAST_CMD_MASK 0xffffffff
+#define UNBPM_AXIMST_LAST_CMD__AXI_MASTER_LAST_CMD__SHIFT 0x0
+#define UNB_IF_INTRGEN_LAST_SENT__GNBPM_LAST_DATA_SENT_MASK 0xffff
+#define UNB_IF_INTRGEN_LAST_SENT__GNBPM_LAST_DATA_SENT__SHIFT 0x0
+#define UNB_IF_INTRGEN_LAST_SENT__SMUPM_LAST_DATA_SENT_MASK 0xffff0000
+#define UNB_IF_INTRGEN_LAST_SENT__SMUPM_LAST_DATA_SENT__SHIFT 0x10
+#define UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_LOGGING_EN_MASK 0x1
+#define UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_LOGGING_EN__SHIFT 0x0
+#define UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_CYCLE_NUM_MASK 0x1fe
+#define UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_CYCLE_NUM__SHIFT 0x1
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNb_MASK 0x1
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNb__SHIFT 0x0
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDct_MASK 0x6
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDct__SHIFT 0x1
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpu_MASK 0x38
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpu__SHIFT 0x3
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPwrTog_MASK 0x40
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPwrTog__SHIFT 0x6
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbPstateLo_MASK 0x80
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbPstateLo__SHIFT 0x7
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbMemPstate_MASK 0x100
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbMemPstate__SHIFT 0x8
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuNbFid_MASK 0x7e00
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuNbFid__SHIFT 0x9
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDid_MASK 0x38000
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDid__SHIFT 0xf
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstate_MASK 0x40000
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstate__SHIFT 0x12
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstateId_MASK 0x380000
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstateId__SHIFT 0x13
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqGateEn_MASK 0x400000
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqGateEn__SHIFT 0x16
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPrbEn_MASK 0x800000
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPrbEn__SHIFT 0x17
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NbPwrMgtReqOutstanding_MASK 0x7000000
+#define UNBPM_PWRMGT_REQ_DBG_STATUS__NbPwrMgtReqOutstanding__SHIFT 0x18
+#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgZeroVid_MASK 0x1
+#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgZeroVid__SHIFT 0x0
+#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidPlane_MASK 0x6
+#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidPlane__SHIFT 0x1
+#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgRamp_MASK 0x8
+#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgRamp__SHIFT 0x3
+#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_Vid_MASK 0xff0
+#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_Vid__SHIFT 0x4
+#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VSTime_MASK 0x7000
+#define UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VSTime__SHIFT 0xc
+#define UNBPM_VIDCHG_REQ_DBG_STATUS__CK_VidChgBusy_MASK 0x10000
+#define UNBPM_VIDCHG_REQ_DBG_STATUS__CK_VidChgBusy__SHIFT 0x10
+#define UNBPM_SCRATCH_0__DATA_MASK 0xffffffff
+#define UNBPM_SCRATCH_0__DATA__SHIFT 0x0
+#define UNBPM_SCRATCH_1__DATA_MASK 0xffffffff
+#define UNBPM_SCRATCH_1__DATA__SHIFT 0x0
+#define POWERON_CPU_0__POWERON_MASK 0x1
+#define POWERON_CPU_0__POWERON__SHIFT 0x0
+#define POWERREADY_CPU_0__POWERREADY_MASK 0x1
+#define POWERREADY_CPU_0__POWERREADY__SHIFT 0x0
+#define PGRUNFEEDBACK_CPU_0__PG_RUNFEEDBACK_MASK 0x1
+#define PGRUNFEEDBACK_CPU_0__PG_RUNFEEDBACK__SHIFT 0x0
+#define RCC3ON_CPU_0__CK_RCC3ON_MASK 0x1
+#define RCC3ON_CPU_0__CK_RCC3ON__SHIFT 0x0
+#define RCC3ON_CPU_0__RCC3_PSM_EN_MASK 0x2
+#define RCC3ON_CPU_0__RCC3_PSM_EN__SHIFT 0x1
+#define RCC3ON_CPU_0__RCC3_PSM_CLK_DIV_MASK 0xc
+#define RCC3ON_CPU_0__RCC3_PSM_CLK_DIV__SHIFT 0x2
+#define RCC3ON_CPU_0__RCC3_AVG_EN_MASK 0x10
+#define RCC3ON_CPU_0__RCC3_AVG_EN__SHIFT 0x4
+#define RCC3ON_CPU_0__RCC3_AVG_DIV_MASK 0x7e0
+#define RCC3ON_CPU_0__RCC3_AVG_DIV__SHIFT 0x5
+#define RCC3ON_CPU_0__RCC3_DIDT_TIMER_MASK 0x1f800
+#define RCC3ON_CPU_0__RCC3_DIDT_TIMER__SHIFT 0xb
+#define RCC3ON_CPU_0__RCC3_WAKE_MIN_14_0_MASK 0xfffe0000
+#define RCC3ON_CPU_0__RCC3_WAKE_MIN_14_0__SHIFT 0x11
+#define RCC3EXITDONE_CPU_0__RCC3EXITDONE_MASK 0x1
+#define RCC3EXITDONE_CPU_0__RCC3EXITDONE__SHIFT 0x0
+#define CORE_FUNC_LATE_SSB_XFER_0__START_STATUS_XFER_MASK 0x1
+#define CORE_FUNC_LATE_SSB_XFER_0__START_STATUS_XFER__SHIFT 0x0
+#define CORE_FUNC_LATE_SSB_XFER_CFG_0__FUSE_FUNC_LAST_ADDR_MASK 0x7ff
+#define CORE_FUNC_LATE_SSB_XFER_CFG_0__FUSE_FUNC_LAST_ADDR__SHIFT 0x0
+#define CORE_FUNC_LATE_SSB_XFER_CFG_0__FUSE_LATE_LAST_ADDR_MASK 0x7ff0000
+#define CORE_FUNC_LATE_SSB_XFER_CFG_0__FUSE_LATE_LAST_ADDR__SHIFT 0x10
+#define CORE_REDUN_SSB_XFER_0__START_STATUS_XFER_MASK 0x1
+#define CORE_REDUN_SSB_XFER_0__START_STATUS_XFER__SHIFT 0x0
+#define CORE_REDUN_SSB_XFER_CFG_0__FUSE_REDUN_LAST_ADDR_MASK 0x7ff
+#define CORE_REDUN_SSB_XFER_CFG_0__FUSE_REDUN_LAST_ADDR__SHIFT 0x0
+#define CORE_APM_SSB_XFER_0__START_STATUS_XFER_MASK 0x1
+#define CORE_APM_SSB_XFER_0__START_STATUS_XFER__SHIFT 0x0
+#define CORE_APM_SSB_XFER_CFG_0__FUSE_APM_LAST_ADDR_MASK 0x7ff
+#define CORE_APM_SSB_XFER_CFG_0__FUSE_APM_LAST_ADDR__SHIFT 0x0
+#define COREPM_PWRCTRL_MISC_0__PWRGATEMASTERDIS_MASK 0x1
+#define COREPM_PWRCTRL_MISC_0__PWRGATEMASTERDIS__SHIFT 0x0
+#define LDOIVRON_CPU_0__CK_LDOIVRON_MASK 0x1
+#define LDOIVRON_CPU_0__CK_LDOIVRON__SHIFT 0x0
+#define LDOIVREXITDONE_CPU_0__LDOIVREXITDONE_MASK 0x1
+#define LDOIVREXITDONE_CPU_0__LDOIVREXITDONE__SHIFT 0x0
+#define RCC3_TARGETPSMREF_CPU_0__RCC3_TARGETPSMREF_MASK 0x3fff
+#define RCC3_TARGETPSMREF_CPU_0__RCC3_TARGETPSMREF__SHIFT 0x0
+#define IVR_TARGETPSMREF_CPU_0__IVR_TARGETPSMREF_MASK 0x3fff
+#define IVR_TARGETPSMREF_CPU_0__IVR_TARGETPSMREF__SHIFT 0x0
+#define CK_JTCOOLRESET_LATCHED_CPU_0__CK_JTCOOLRESET_LATCHED_MASK 0x1
+#define CK_JTCOOLRESET_LATCHED_CPU_0__CK_JTCOOLRESET_LATCHED__SHIFT 0x0
+#define CK_DISABLECORE_CPU_0__CK_DISABLECORE_MASK 0x1
+#define CK_DISABLECORE_CPU_0__CK_DISABLECORE__SHIFT 0x0
+#define COREPM_ID_0__COREPM_INDEX_MASK 0x1
+#define COREPM_ID_0__COREPM_INDEX__SHIFT 0x0
+#define COREPM_SCRATCH_0__SCRATCH_DATA_MASK 0xffffffff
+#define COREPM_SCRATCH_0__SCRATCH_DATA__SHIFT 0x0
+#define RCC3_WAKEMIN_CPU_0__RCC3_WAKE_MIN_46_15_MASK 0xffffffff
+#define RCC3_WAKEMIN_CPU_0__RCC3_WAKE_MIN_46_15__SHIFT 0x0
+#define SPMI_CONFIG0_0__SPMI_ENABLE_MASK 0x1
+#define SPMI_CONFIG0_0__SPMI_ENABLE__SHIFT 0x0
+#define SPMI_CONFIG0_0__SPMI_PATH_NUM_TIMING_FLOPS_MASK 0x7c
+#define SPMI_CONFIG0_0__SPMI_PATH_NUM_TIMING_FLOPS__SHIFT 0x2
+#define SPMI_CONFIG0_0__SPMI_SIGNALING_DELAY_CYCLES_MASK 0xf80
+#define SPMI_CONFIG0_0__SPMI_SIGNALING_DELAY_CYCLES__SHIFT 0x7
+#define SPMI_CONFIG0_0__SPMI_SIGNALING_HOLD_CYCLES_MASK 0x1f000
+#define SPMI_CONFIG0_0__SPMI_SIGNALING_HOLD_CYCLES__SHIFT 0xc
+#define SPMI_CONFIG0_0__SPMI_PATH_ENABLE_DELAY_CYCLES_MASK 0x3e0000
+#define SPMI_CONFIG0_0__SPMI_PATH_ENABLE_DELAY_CYCLES__SHIFT 0x11
+#define SPMI_CONFIG0_0__SPMI_PATH_DISABLE_DELAY_CYCLES_MASK 0x7c00000
+#define SPMI_CONFIG0_0__SPMI_PATH_DISABLE_DELAY_CYCLES__SHIFT 0x16
+#define SPMI_CONFIG1_0__SPMI_SIGNALING_RESET_HOLD_CYCLES_MASK 0x1f
+#define SPMI_CONFIG1_0__SPMI_SIGNALING_RESET_HOLD_CYCLES__SHIFT 0x0
+#define SPMI_CONFIG1_0__SPMI_CHAIN_SIZE_MASK 0xffe0
+#define SPMI_CONFIG1_0__SPMI_CHAIN_SIZE__SHIFT 0x5
+#define SPMI_FSM_READ_TRIGGER_0__FSM_READ_TRIGGER_MASK 0x1
+#define SPMI_FSM_READ_TRIGGER_0__FSM_READ_TRIGGER__SHIFT 0x0
+#define SPMI_FSM_WRITE_TRIGGER_0__FSM_WRITE_TRIGGER_MASK 0x1
+#define SPMI_FSM_WRITE_TRIGGER_0__FSM_WRITE_TRIGGER__SHIFT 0x0
+#define SPMI_FSM_RESET_TRIGGER_0__FSM_RESET_TRIGGER_MASK 0x1
+#define SPMI_FSM_RESET_TRIGGER_0__FSM_RESET_TRIGGER__SHIFT 0x0
+#define SPMI_FSM_BUSY_0__FSM_BUSY_MASK 0x1
+#define SPMI_FSM_BUSY_0__FSM_BUSY__SHIFT 0x0
+#define SPMI_PATH_0__PATH_ENABLE_REQ_MASK 0x1
+#define SPMI_PATH_0__PATH_ENABLE_REQ__SHIFT 0x0
+#define SPMI_PATH_0__PATH_ENABLE_ACK_MASK 0x2
+#define SPMI_PATH_0__PATH_ENABLE_ACK__SHIFT 0x1
+#define SPMI_PATH_0__PATH_ENABLE_REQ_auto_clear_MASK 0x10
+#define SPMI_PATH_0__PATH_ENABLE_REQ_auto_clear__SHIFT 0x4
+#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED_MASK 0x1
+#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED__SHIFT 0x0
+#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY_MASK 0x2
+#define SPMI_C6_STATE_0__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY__SHIFT 0x1
+#define SPMI_C6_STATE_0__SPMI_IF_COUNTER_ADDRESS_C6_MASK 0xfffc
+#define SPMI_C6_STATE_0__SPMI_IF_COUNTER_ADDRESS_C6__SHIFT 0x2
+#define SPMI_JTAG_OVER_0__SPMI_IF_JTAG_OVER_HAPPENED_MASK 0x1
+#define SPMI_JTAG_OVER_0__SPMI_IF_JTAG_OVER_HAPPENED__SHIFT 0x0
+#define SPMI_SRAM_ADDRESS_0__SRAM_ADDRESS_MASK 0xffffffff
+#define SPMI_SRAM_ADDRESS_0__SRAM_ADDRESS__SHIFT 0x0
+#define SPMI_SRAM_DATA_0__SRAM_DATA_MASK 0xffffffff
+#define SPMI_SRAM_DATA_0__SRAM_DATA__SHIFT 0x0
+#define SPMI_RESET_0__ASYNC_RESET_0_MASK 0x1
+#define SPMI_RESET_0__ASYNC_RESET_0__SHIFT 0x0
+#define SPMI_RESET_0__SYNC_RESET_MASK 0x80000000
+#define SPMI_RESET_0__SYNC_RESET__SHIFT 0x1f
+#define SPMI_FORCE_CLOCK_GATERS_0__CLOCK_GATER_0_FORCE_MASK 0x1
+#define SPMI_FORCE_CLOCK_GATERS_0__CLOCK_GATER_0_FORCE__SHIFT 0x0
+#define SPMI_FORCE_CLOCK_GATERS_0__SRAM_CLOCK_GATER_FORCE_MASK 0x100
+#define SPMI_FORCE_CLOCK_GATERS_0__SRAM_CLOCK_GATER_FORCE__SHIFT 0x8
+#define SPMI_SPARE_0__SPARE_DATA_MASK 0xffffffff
+#define SPMI_SPARE_0__SPARE_DATA__SHIFT 0x0
+#define SPMI_SPARE_EX_0__SPARE_DATA_EX_MASK 0xffffffff
+#define SPMI_SPARE_EX_0__SPARE_DATA_EX__SHIFT 0x0
+#define SPMI_SRAM_CLK_GATER_0__SRAM_CLK_GATER_EN_MASK 0x1
+#define SPMI_SRAM_CLK_GATER_0__SRAM_CLK_GATER_EN__SHIFT 0x0
+#define SPMI_SRAM_CLK_GATER_0__SRAM_CLK_GATER_TIMER_MASK 0x7fe
+#define SPMI_SRAM_CLK_GATER_0__SRAM_CLK_GATER_TIMER__SHIFT 0x1
+#define POWERON_CPU_1__POWERON_MASK 0x1
+#define POWERON_CPU_1__POWERON__SHIFT 0x0
+#define POWERREADY_CPU_1__POWERREADY_MASK 0x1
+#define POWERREADY_CPU_1__POWERREADY__SHIFT 0x0
+#define PGRUNFEEDBACK_CPU_1__PG_RUNFEEDBACK_MASK 0x1
+#define PGRUNFEEDBACK_CPU_1__PG_RUNFEEDBACK__SHIFT 0x0
+#define RCC3ON_CPU_1__CK_RCC3ON_MASK 0x1
+#define RCC3ON_CPU_1__CK_RCC3ON__SHIFT 0x0
+#define RCC3ON_CPU_1__RCC3_PSM_EN_MASK 0x2
+#define RCC3ON_CPU_1__RCC3_PSM_EN__SHIFT 0x1
+#define RCC3ON_CPU_1__RCC3_PSM_CLK_DIV_MASK 0xc
+#define RCC3ON_CPU_1__RCC3_PSM_CLK_DIV__SHIFT 0x2
+#define RCC3ON_CPU_1__RCC3_AVG_EN_MASK 0x10
+#define RCC3ON_CPU_1__RCC3_AVG_EN__SHIFT 0x4
+#define RCC3ON_CPU_1__RCC3_AVG_DIV_MASK 0x7e0
+#define RCC3ON_CPU_1__RCC3_AVG_DIV__SHIFT 0x5
+#define RCC3ON_CPU_1__RCC3_DIDT_TIMER_MASK 0x1f800
+#define RCC3ON_CPU_1__RCC3_DIDT_TIMER__SHIFT 0xb
+#define RCC3ON_CPU_1__RCC3_WAKE_MIN_14_0_MASK 0xfffe0000
+#define RCC3ON_CPU_1__RCC3_WAKE_MIN_14_0__SHIFT 0x11
+#define RCC3EXITDONE_CPU_1__RCC3EXITDONE_MASK 0x1
+#define RCC3EXITDONE_CPU_1__RCC3EXITDONE__SHIFT 0x0
+#define CORE_FUNC_LATE_SSB_XFER_1__START_STATUS_XFER_MASK 0x1
+#define CORE_FUNC_LATE_SSB_XFER_1__START_STATUS_XFER__SHIFT 0x0
+#define CORE_FUNC_LATE_SSB_XFER_CFG_1__FUSE_FUNC_LAST_ADDR_MASK 0x7ff
+#define CORE_FUNC_LATE_SSB_XFER_CFG_1__FUSE_FUNC_LAST_ADDR__SHIFT 0x0
+#define CORE_FUNC_LATE_SSB_XFER_CFG_1__FUSE_LATE_LAST_ADDR_MASK 0x7ff0000
+#define CORE_FUNC_LATE_SSB_XFER_CFG_1__FUSE_LATE_LAST_ADDR__SHIFT 0x10
+#define CORE_REDUN_SSB_XFER_1__START_STATUS_XFER_MASK 0x1
+#define CORE_REDUN_SSB_XFER_1__START_STATUS_XFER__SHIFT 0x0
+#define CORE_REDUN_SSB_XFER_CFG_1__FUSE_REDUN_LAST_ADDR_MASK 0x7ff
+#define CORE_REDUN_SSB_XFER_CFG_1__FUSE_REDUN_LAST_ADDR__SHIFT 0x0
+#define CORE_APM_SSB_XFER_1__START_STATUS_XFER_MASK 0x1
+#define CORE_APM_SSB_XFER_1__START_STATUS_XFER__SHIFT 0x0
+#define CORE_APM_SSB_XFER_CFG_1__FUSE_APM_LAST_ADDR_MASK 0x7ff
+#define CORE_APM_SSB_XFER_CFG_1__FUSE_APM_LAST_ADDR__SHIFT 0x0
+#define COREPM_PWRCTRL_MISC_1__PWRGATEMASTERDIS_MASK 0x1
+#define COREPM_PWRCTRL_MISC_1__PWRGATEMASTERDIS__SHIFT 0x0
+#define LDOIVRON_CPU_1__CK_LDOIVRON_MASK 0x1
+#define LDOIVRON_CPU_1__CK_LDOIVRON__SHIFT 0x0
+#define LDOIVREXITDONE_CPU_1__LDOIVREXITDONE_MASK 0x1
+#define LDOIVREXITDONE_CPU_1__LDOIVREXITDONE__SHIFT 0x0
+#define RCC3_TARGETPSMREF_CPU_1__RCC3_TARGETPSMREF_MASK 0x3fff
+#define RCC3_TARGETPSMREF_CPU_1__RCC3_TARGETPSMREF__SHIFT 0x0
+#define IVR_TARGETPSMREF_CPU_1__IVR_TARGETPSMREF_MASK 0x3fff
+#define IVR_TARGETPSMREF_CPU_1__IVR_TARGETPSMREF__SHIFT 0x0
+#define CK_JTCOOLRESET_LATCHED_CPU_1__CK_JTCOOLRESET_LATCHED_MASK 0x1
+#define CK_JTCOOLRESET_LATCHED_CPU_1__CK_JTCOOLRESET_LATCHED__SHIFT 0x0
+#define CK_DISABLECORE_CPU_1__CK_DISABLECORE_MASK 0x1
+#define CK_DISABLECORE_CPU_1__CK_DISABLECORE__SHIFT 0x0
+#define COREPM_ID_1__COREPM_INDEX_MASK 0x1
+#define COREPM_ID_1__COREPM_INDEX__SHIFT 0x0
+#define COREPM_SCRATCH_1__SCRATCH_DATA_MASK 0xffffffff
+#define COREPM_SCRATCH_1__SCRATCH_DATA__SHIFT 0x0
+#define RCC3_WAKEMIN_CPU_1__RCC3_WAKE_MIN_46_15_MASK 0xffffffff
+#define RCC3_WAKEMIN_CPU_1__RCC3_WAKE_MIN_46_15__SHIFT 0x0
+#define SPMI_CONFIG0_1__SPMI_ENABLE_MASK 0x1
+#define SPMI_CONFIG0_1__SPMI_ENABLE__SHIFT 0x0
+#define SPMI_CONFIG0_1__SPMI_PATH_NUM_TIMING_FLOPS_MASK 0x7c
+#define SPMI_CONFIG0_1__SPMI_PATH_NUM_TIMING_FLOPS__SHIFT 0x2
+#define SPMI_CONFIG0_1__SPMI_SIGNALING_DELAY_CYCLES_MASK 0xf80
+#define SPMI_CONFIG0_1__SPMI_SIGNALING_DELAY_CYCLES__SHIFT 0x7
+#define SPMI_CONFIG0_1__SPMI_SIGNALING_HOLD_CYCLES_MASK 0x1f000
+#define SPMI_CONFIG0_1__SPMI_SIGNALING_HOLD_CYCLES__SHIFT 0xc
+#define SPMI_CONFIG0_1__SPMI_PATH_ENABLE_DELAY_CYCLES_MASK 0x3e0000
+#define SPMI_CONFIG0_1__SPMI_PATH_ENABLE_DELAY_CYCLES__SHIFT 0x11
+#define SPMI_CONFIG0_1__SPMI_PATH_DISABLE_DELAY_CYCLES_MASK 0x7c00000
+#define SPMI_CONFIG0_1__SPMI_PATH_DISABLE_DELAY_CYCLES__SHIFT 0x16
+#define SPMI_CONFIG1_1__SPMI_SIGNALING_RESET_HOLD_CYCLES_MASK 0x1f
+#define SPMI_CONFIG1_1__SPMI_SIGNALING_RESET_HOLD_CYCLES__SHIFT 0x0
+#define SPMI_CONFIG1_1__SPMI_CHAIN_SIZE_MASK 0xffe0
+#define SPMI_CONFIG1_1__SPMI_CHAIN_SIZE__SHIFT 0x5
+#define SPMI_FSM_READ_TRIGGER_1__FSM_READ_TRIGGER_MASK 0x1
+#define SPMI_FSM_READ_TRIGGER_1__FSM_READ_TRIGGER__SHIFT 0x0
+#define SPMI_FSM_WRITE_TRIGGER_1__FSM_WRITE_TRIGGER_MASK 0x1
+#define SPMI_FSM_WRITE_TRIGGER_1__FSM_WRITE_TRIGGER__SHIFT 0x0
+#define SPMI_FSM_RESET_TRIGGER_1__FSM_RESET_TRIGGER_MASK 0x1
+#define SPMI_FSM_RESET_TRIGGER_1__FSM_RESET_TRIGGER__SHIFT 0x0
+#define SPMI_FSM_BUSY_1__FSM_BUSY_MASK 0x1
+#define SPMI_FSM_BUSY_1__FSM_BUSY__SHIFT 0x0
+#define SPMI_PATH_1__PATH_ENABLE_REQ_MASK 0x1
+#define SPMI_PATH_1__PATH_ENABLE_REQ__SHIFT 0x0
+#define SPMI_PATH_1__PATH_ENABLE_ACK_MASK 0x2
+#define SPMI_PATH_1__PATH_ENABLE_ACK__SHIFT 0x1
+#define SPMI_PATH_1__PATH_ENABLE_REQ_auto_clear_MASK 0x10
+#define SPMI_PATH_1__PATH_ENABLE_REQ_auto_clear__SHIFT 0x4
+#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED_MASK 0x1
+#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED__SHIFT 0x0
+#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY_MASK 0x2
+#define SPMI_C6_STATE_1__SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY__SHIFT 0x1
+#define SPMI_C6_STATE_1__SPMI_IF_COUNTER_ADDRESS_C6_MASK 0xfffc
+#define SPMI_C6_STATE_1__SPMI_IF_COUNTER_ADDRESS_C6__SHIFT 0x2
+#define SPMI_JTAG_OVER_1__SPMI_IF_JTAG_OVER_HAPPENED_MASK 0x1
+#define SPMI_JTAG_OVER_1__SPMI_IF_JTAG_OVER_HAPPENED__SHIFT 0x0
+#define SPMI_SRAM_ADDRESS_1__SRAM_ADDRESS_MASK 0xffffffff
+#define SPMI_SRAM_ADDRESS_1__SRAM_ADDRESS__SHIFT 0x0
+#define SPMI_SRAM_DATA_1__SRAM_DATA_MASK 0xffffffff
+#define SPMI_SRAM_DATA_1__SRAM_DATA__SHIFT 0x0
+#define SPMI_RESET_1__ASYNC_RESET_0_MASK 0x1
+#define SPMI_RESET_1__ASYNC_RESET_0__SHIFT 0x0
+#define SPMI_RESET_1__SYNC_RESET_MASK 0x80000000
+#define SPMI_RESET_1__SYNC_RESET__SHIFT 0x1f
+#define SPMI_FORCE_CLOCK_GATERS_1__CLOCK_GATER_0_FORCE_MASK 0x1
+#define SPMI_FORCE_CLOCK_GATERS_1__CLOCK_GATER_0_FORCE__SHIFT 0x0
+#define SPMI_FORCE_CLOCK_GATERS_1__SRAM_CLOCK_GATER_FORCE_MASK 0x100
+#define SPMI_FORCE_CLOCK_GATERS_1__SRAM_CLOCK_GATER_FORCE__SHIFT 0x8
+#define SPMI_SPARE_1__SPARE_DATA_MASK 0xffffffff
+#define SPMI_SPARE_1__SPARE_DATA__SHIFT 0x0
+#define SPMI_SPARE_EX_1__SPARE_DATA_EX_MASK 0xffffffff
+#define SPMI_SPARE_EX_1__SPARE_DATA_EX__SHIFT 0x0
+#define SPMI_SRAM_CLK_GATER_1__SRAM_CLK_GATER_EN_MASK 0x1
+#define SPMI_SRAM_CLK_GATER_1__SRAM_CLK_GATER_EN__SHIFT 0x0
+#define SPMI_SRAM_CLK_GATER_1__SRAM_CLK_GATER_TIMER_MASK 0x7fe
+#define SPMI_SRAM_CLK_GATER_1__SRAM_CLK_GATER_TIMER__SHIFT 0x1
+#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1
+#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0
+#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2
+#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8
+#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3
+#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40
+#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6
+#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100
+#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8
+#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200
+#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9
+#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400
+#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa
+#define GENERAL_PWRMGT__SPARE11_MASK 0x800
+#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb
+#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000
+#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe
+#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000
+#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf
+#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000
+#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10
+#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000
+#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11
+#define GENERAL_PWRMGT__SPARE18_MASK 0x40000
+#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12
+#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000
+#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13
+#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000
+#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17
+#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000
+#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b
+#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000
+#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c
+#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3
+#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0
+#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4
+#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2
+#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8
+#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3
+#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10
+#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4
+#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0
+#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5
+#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10
+#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4
+#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20
+#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5
+#define SCLK_PWRMGT_CNTL__RESERVED_0_MASK 0x40
+#define SCLK_PWRMGT_CNTL__RESERVED_0__SHIFT 0x6
+#define SCLK_PWRMGT_CNTL__RESERVED_3_MASK 0x1000000
+#define SCLK_PWRMGT_CNTL__RESERVED_3__SHIFT 0x18
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_ACPI_INDEX_MASK 0xf
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_ACPI_INDEX__SHIFT 0x0
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_ACPI_INDEX_MASK 0xf0
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_ACPI_INDEX__SHIFT 0x4
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c
+#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_UVD_INDEX_MASK 0xf
+#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_UVD_INDEX__SHIFT 0x0
+#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_UVD_INDEX_MASK 0xf0
+#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_UVD_INDEX__SHIFT 0x4
+#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_VCE_INDEX_MASK 0xf00
+#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_VCE_INDEX__SHIFT 0x8
+#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_VCE_INDEX_MASK 0xf000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_VCE_INDEX__SHIFT 0xc
+#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_ACP_INDEX_MASK 0xf0000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_ACP_INDEX__SHIFT 0x10
+#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_ACP_INDEX_MASK 0xf00000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_ACP_INDEX__SHIFT 0x14
+#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_SAMU_INDEX_MASK 0xf000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_SAMU_INDEX__SHIFT 0x18
+#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_SAMU_INDEX_MASK 0xf0000000
+#define TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_SAMU_INDEX__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_0__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_0__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_0__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000
+#define CG_FREQ_TRAN_VOTING_0__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f
+#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_1__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_1__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_1__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000
+#define CG_FREQ_TRAN_VOTING_1__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f
+#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_2__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_2__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_2__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000
+#define CG_FREQ_TRAN_VOTING_2__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f
+#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_3__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_3__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_3__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000
+#define CG_FREQ_TRAN_VOTING_3__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f
+#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_4__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_4__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_4__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000
+#define CG_FREQ_TRAN_VOTING_4__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f
+#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_5__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_5__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_5__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000
+#define CG_FREQ_TRAN_VOTING_5__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f
+#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_6__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_6__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_6__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000
+#define CG_FREQ_TRAN_VOTING_6__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f
+#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
+#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
+#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
+#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
+#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
+#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
+#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
+#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
+#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
+#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
+#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
+#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
+#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
+#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
+#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
+#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
+#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
+#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
+#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
+#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
+#define CG_FREQ_TRAN_VOTING_7__VCE_0_FREQ_THROTTLING_VOTE_EN_MASK 0x400
+#define CG_FREQ_TRAN_VOTING_7__VCE_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
+#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
+#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
+#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
+#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
+#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
+#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
+#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
+#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
+#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
+#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
+#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
+#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
+#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
+#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
+#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
+#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
+#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
+#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
+#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
+#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
+#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
+#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
+#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
+#define CG_FREQ_TRAN_VOTING_7__VCE_1_FREQ_THROTTLING_VOTE_EN_MASK 0x80000000
+#define CG_FREQ_TRAN_VOTING_7__VCE_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1f
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000
+#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10
+#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f
+#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0
+#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80
+#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7
+#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
+#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
+#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
+#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
+#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000
+#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11
+#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000
+#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12
+#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000
+#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13
+#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000
+#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14
+#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000
+#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15
+#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000
+#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16
+#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000
+#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17
+#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000
+#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000
+#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19
+#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000
+#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a
+#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000
+#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b
+#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000
+#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c
+#define SCLK_DEEP_SLEEP_CNTL__VCE_0_BUSY_MASK_MASK 0x20000000
+#define SCLK_DEEP_SLEEP_CNTL__VCE_0_BUSY_MASK__SHIFT 0x1d
+#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000
+#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e
+#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
+#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1
+#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2
+#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1
+#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4
+#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2
+#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8
+#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10
+#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4
+#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40
+#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6
+#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80
+#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7
+#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100
+#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8
+#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200
+#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9
+#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400
+#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa
+#define SCLK_DEEP_SLEEP_CNTL2__VCE_0_CG_MC_STAT_BUSY_MASK_MASK 0x800
+#define SCLK_DEEP_SLEEP_CNTL2__VCE_0_CG_MC_STAT_BUSY_MASK__SHIFT 0xb
+#define SCLK_DEEP_SLEEP_CNTL2__VCE_1_BUSY_MASK_MASK 0x200000
+#define SCLK_DEEP_SLEEP_CNTL2__VCE_1_BUSY_MASK__SHIFT 0x15
+#define SCLK_DEEP_SLEEP_CNTL2__VCE_1_CG_MC_STAT_BUSY_MASK_MASK 0x400000
+#define SCLK_DEEP_SLEEP_CNTL2__VCE_1_CG_MC_STAT_BUSY_MASK__SHIFT 0x16
+#define SCLK_DEEP_SLEEP_CNTL2__REG_SCLK_DEEP_SLEEP_MASK_MASK 0x800000
+#define SCLK_DEEP_SLEEP_CNTL2__REG_SCLK_DEEP_SLEEP_MASK__SHIFT 0x17
+#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000
+#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000
+#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf
+#define SCLK_DEEP_SLEEP_CNTL3__SMUIF_SLAVE_SCLK_BUSY_MASK_MASK 0x10000
+#define SCLK_DEEP_SLEEP_CNTL3__SMUIF_SLAVE_SCLK_BUSY_MASK__SHIFT 0x10
+#define SCLK_DEEP_SLEEP_CNTL3__SMUIF_MASTER_SCLK_BUSY_MASK_MASK 0x20000
+#define SCLK_DEEP_SLEEP_CNTL3__SMUIF_MASTER_SCLK_BUSY_MASK__SHIFT 0x11
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38
+#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000
+#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14
+#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
+#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
+#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
+#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
+#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
+#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
+#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000
+#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10
+#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
+#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
+#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1
+#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0
+#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2
+#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3
+#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10
+#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4
+#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20
+#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200
+#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd
+#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000
+#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe
+#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000
+#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000
+#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13
+#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000
+#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUPCIE0_IDLE_MASK_MASK 0x200000
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUPCIE0_IDLE_MASK__SHIFT 0x15
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUPCIE1_IDLE_MASK_MASK 0x400000
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUPCIE1_IDLE_MASK__SHIFT 0x16
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUIOAGR_IDLE_MASK_MASK 0x800000
+#define LCLK_DEEP_SLEEP_CNTL2__L1IMUIOAGR_IDLE_MASK__SHIFT 0x17
+#define LCLK_DEEP_SLEEP_CNTL2__SPG_SMU_IDLE_MASK_MASK 0x1000000
+#define LCLK_DEEP_SLEEP_CNTL2__SPG_SMU_IDLE_MASK__SHIFT 0x18
+#define LCLK_DEEP_SLEEP_CNTL2__APG_SMU_IDLE_MASK_MASK 0x2000000
+#define LCLK_DEEP_SLEEP_CNTL2__APG_SMU_IDLE_MASK__SHIFT 0x19
+#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE0_MASK_MASK 0x4000000
+#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE0_MASK__SHIFT 0x1a
+#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE1_MASK_MASK 0x8000000
+#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE1_MASK__SHIFT 0x1b
+#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE2_MASK_MASK 0x10000000
+#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE2_MASK__SHIFT 0x1c
+#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE3_MASK_MASK 0x20000000
+#define LCLK_DEEP_SLEEP_CNTL2__IP_SMU_IDLE3_MASK__SHIFT 0x1d
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xc0000000
+#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x1e
+#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_STATUS_MASK 0x1
+#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_STATUS__SHIFT 0x0
+#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK 0x1fe
+#define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT 0x1
+#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff
+#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0
+#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000
+#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10
+#define PWR_DC_RESP__RESPONSE_MASK 0x1
+#define PWR_DC_RESP__RESPONSE__SHIFT 0x0
+#define PWR_VCE_RESP__RESPONSE_MASK 0xffffffff
+#define PWR_VCE_RESP__RESPONSE__SHIFT 0x0
+#define PWR_UVD_RESP__RESPONSE_MASK 0xffffffff
+#define PWR_UVD_RESP__RESPONSE__SHIFT 0x0
+#define PWR_ACP_RESP__RESPONSE_MASK 0xffffffff
+#define PWR_ACP_RESP__RESPONSE__SHIFT 0x0
+#define PWR_DC_REQ__REQUEST_MASK 0x1
+#define PWR_DC_REQ__REQUEST__SHIFT 0x0
+#define SCLK_MIN_DIV__FRACV_MASK 0xfff
+#define SCLK_MIN_DIV__FRACV__SHIFT 0x0
+#define SCLK_MIN_DIV__INTV_MASK 0x7f000
+#define SCLK_MIN_DIV__INTV__SHIFT 0xc
+#define PCIE_PGFSM_CONFIG__FSM_ADDR_MASK 0xff
+#define PCIE_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
+#define PCIE_PGFSM_CONFIG__Power_Down_MASK 0x100
+#define PCIE_PGFSM_CONFIG__Power_Down__SHIFT 0x8
+#define PCIE_PGFSM_CONFIG__Power_Up_MASK 0x200
+#define PCIE_PGFSM_CONFIG__Power_Up__SHIFT 0x9
+#define PCIE_PGFSM_CONFIG__P1_Select_MASK 0x400
+#define PCIE_PGFSM_CONFIG__P1_Select__SHIFT 0xa
+#define PCIE_PGFSM_CONFIG__P2_Select_MASK 0x800
+#define PCIE_PGFSM_CONFIG__P2_Select__SHIFT 0xb
+#define PCIE_PGFSM_CONFIG__Write_Op_MASK 0x1000
+#define PCIE_PGFSM_CONFIG__Write_Op__SHIFT 0xc
+#define PCIE_PGFSM_CONFIG__Read_Op_MASK 0x2000
+#define PCIE_PGFSM_CONFIG__Read_Op__SHIFT 0xd
+#define PCIE_PGFSM_CONFIG__Reserved_MASK 0xfffc000
+#define PCIE_PGFSM_CONFIG__Reserved__SHIFT 0xe
+#define PCIE_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000
+#define PCIE_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
+#define PCIE_PGFSM_WRITE__Write_value_MASK 0xffffffff
+#define PCIE_PGFSM_WRITE__Write_value__SHIFT 0x0
+#define SERDES_BUSY__PCIE_SERDES_BUSY_MASK 0x1
+#define SERDES_BUSY__PCIE_SERDES_BUSY__SHIFT 0x0
+#define PCIE_PGFSM2_CONFIG__FSM_ADDR_MASK 0xff
+#define PCIE_PGFSM2_CONFIG__FSM_ADDR__SHIFT 0x0
+#define PCIE_PGFSM2_CONFIG__Power_Down_MASK 0x100
+#define PCIE_PGFSM2_CONFIG__Power_Down__SHIFT 0x8
+#define PCIE_PGFSM2_CONFIG__Power_Up_MASK 0x200
+#define PCIE_PGFSM2_CONFIG__Power_Up__SHIFT 0x9
+#define PCIE_PGFSM2_CONFIG__P1_Select_MASK 0x400
+#define PCIE_PGFSM2_CONFIG__P1_Select__SHIFT 0xa
+#define PCIE_PGFSM2_CONFIG__P2_Select_MASK 0x800
+#define PCIE_PGFSM2_CONFIG__P2_Select__SHIFT 0xb
+#define PCIE_PGFSM2_CONFIG__Write_Op_MASK 0x1000
+#define PCIE_PGFSM2_CONFIG__Write_Op__SHIFT 0xc
+#define PCIE_PGFSM2_CONFIG__Read_Op_MASK 0x2000
+#define PCIE_PGFSM2_CONFIG__Read_Op__SHIFT 0xd
+#define PCIE_PGFSM2_CONFIG__Reserved_MASK 0xfffc000
+#define PCIE_PGFSM2_CONFIG__Reserved__SHIFT 0xe
+#define PCIE_PGFSM2_CONFIG__REG_ADDR_MASK 0xf0000000
+#define PCIE_PGFSM2_CONFIG__REG_ADDR__SHIFT 0x1c
+#define PCIE_PGFSM2_WRITE__Write_value_MASK 0xffffffff
+#define PCIE_PGFSM2_WRITE__Write_value__SHIFT 0x0
+#define SERDES2_BUSY__PCIE_SERDES_BUSY_MASK 0x1
+#define SERDES2_BUSY__PCIE_SERDES_BUSY__SHIFT 0x0
+#define PCIE_PGFSM_0_READ__Read_value_MASK 0xffffff
+#define PCIE_PGFSM_0_READ__Read_value__SHIFT 0x0
+#define PCIE_PGFSM_0_READ__Read_valid_MASK 0x1000000
+#define PCIE_PGFSM_0_READ__Read_valid__SHIFT 0x18
+#define PCIE_PGFSM_1_READ__Read_value_MASK 0xffffff
+#define PCIE_PGFSM_1_READ__Read_value__SHIFT 0x0
+#define PCIE_PGFSM_1_READ__Read_valid_MASK 0x1000000
+#define PCIE_PGFSM_1_READ__Read_valid__SHIFT 0x18
+#define PWR_ACPI_INTERRUPT__BIF_CG_req_MASK 0x1
+#define PWR_ACPI_INTERRUPT__BIF_CG_req__SHIFT 0x0
+#define PWR_ACPI_INTERRUPT__AZ_CG_req_MASK 0x2
+#define PWR_ACPI_INTERRUPT__AZ_CG_req__SHIFT 0x1
+#define PWR_ACPI_INTERRUPT__AZ_CG_resp_MASK 0x4
+#define PWR_ACPI_INTERRUPT__AZ_CG_resp__SHIFT 0x2
+#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_MASK 0xffff
+#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD__SHIFT 0x0
+#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT_MASK 0xf0000
+#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT__SHIFT 0x10
+#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN_MASK 0x1
+#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN__SHIFT 0x0
+#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT_MASK 0x2
+#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT__SHIFT 0x1
+#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT_MASK 0x4
+#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT__SHIFT 0x2
+#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE_MASK 0x8
+#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE__SHIFT 0x3
+#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ_MASK 0x1
+#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ__SHIFT 0x0
+#define REG_SCLK_DEEP_SLEEP_EXIT__REG_sclk_deep_sleep_exit_MASK 0x1
+#define REG_SCLK_DEEP_SLEEP_EXIT__REG_sclk_deep_sleep_exit__SHIFT 0x0
+#define CAC_WEIGHT_LKG_DC_3__WEIGHT_LKG_DC_SIG4_MASK 0xffff
+#define CAC_WEIGHT_LKG_DC_3__WEIGHT_LKG_DC_SIG4__SHIFT 0x0
+#define CAC_WEIGHT_LKG_DC_3__WEIGHT_LKG_DC_SIG5_MASK 0xffff0000
+#define CAC_WEIGHT_LKG_DC_3__WEIGHT_LKG_DC_SIG5__SHIFT 0x10
+#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1
+#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0
+#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1
+#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0
+#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0
+#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1
+#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0
+#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1
+#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0
+#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0
+#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1
+#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0
+#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1
+#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0
+#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0
+#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1
+#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0
+#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe
+#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1
+#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000
+#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11
+#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16
+#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff
+#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0
+#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff
+#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0
+#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1
+#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0
+#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe
+#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1
+#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000
+#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11
+#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000
+#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16
+#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff
+#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0
+#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff
+#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0
+#define MISC_UNB_PWRMGT_CFG0__TARGET_ADDR_MASK 0xffffffff
+#define MISC_UNB_PWRMGT_CFG0__TARGET_ADDR__SHIFT 0x0
+#define MISC_UNB_PWRMGT_CFG1__TIMER_EN_MASK 0x1
+#define MISC_UNB_PWRMGT_CFG1__TIMER_EN__SHIFT 0x0
+#define MISC_UNB_PWRMGT_CFG1__TIMER_INTERVAL_MASK 0x1fffe
+#define MISC_UNB_PWRMGT_CFG1__TIMER_INTERVAL__SHIFT 0x1
+#define MISC_UNB_PWRMGT_CFG1__INT_GEN_EN_MASK 0x20000
+#define MISC_UNB_PWRMGT_CFG1__INT_GEN_EN__SHIFT 0x11
+#define MISC_UNB_PWRMGT_DATA__NB_CROSS_TRIGGER_MASK 0xf
+#define MISC_UNB_PWRMGT_DATA__NB_CROSS_TRIGGER__SHIFT 0x0
+#define MISC_UNB_PWRMGT_DATA__NB_PRE_SELF_REFRESH_MASK 0x10
+#define MISC_UNB_PWRMGT_DATA__NB_PRE_SELF_REFRESH__SHIFT 0x4
+#define MISC_UNB_PWRMGT_DATA__NB_REQ_NB_PSTATE_MASK 0x20
+#define MISC_UNB_PWRMGT_DATA__NB_REQ_NB_PSTATE__SHIFT 0x5
+#define MISC_UNB_PWRMGT_DATA__NB_FLUSH_ACK_TOGGLE_MASK 0x40
+#define MISC_UNB_PWRMGT_DATA__NB_FLUSH_ACK_TOGGLE__SHIFT 0x6
+#define MISC_UNB_PWRMGT_DATA__NB_ON_INB_WAKE_ACK_MASK 0x80
+#define MISC_UNB_PWRMGT_DATA__NB_ON_INB_WAKE_ACK__SHIFT 0x7
+#define MISC_UNB_PWRMGT_DATA__NB_ON3_CH0LINK_WAKE_ACK_MASK 0x100
+#define MISC_UNB_PWRMGT_DATA__NB_ON3_CH0LINK_WAKE_ACK__SHIFT 0x8
+#define MISC_UNB_PWRMGT_DATA__NB_ON3_CH1LINK_WAKE_ACK_MASK 0x200
+#define MISC_UNB_PWRMGT_DATA__NB_ON3_CH1LINK_WAKE_ACK__SHIFT 0x9
+#define GNBPM_SMU_PWRMGT_DATA__UNBPM_AllCpusInCC6_MASK 0x1
+#define GNBPM_SMU_PWRMGT_DATA__UNBPM_AllCpusInCC6__SHIFT 0x0
+#define GNBPM_SMU_PWRMGT_DATA__UNBPM_HtcActive_MASK 0x2
+#define GNBPM_SMU_PWRMGT_DATA__UNBPM_HtcActive__SHIFT 0x1
+#define GNBPM_SMU_PWRMGT_DATA__UNBPM_SmuInt_MASK 0x4
+#define GNBPM_SMU_PWRMGT_DATA__UNBPM_SmuInt__SHIFT 0x2
+#define GNBPM_SMU_PWRMGT_DATA__UNBPM_SPARE_MASK 0xf8
+#define GNBPM_SMU_PWRMGT_DATA__UNBPM_SPARE__SHIFT 0x3
+#define DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_EN_MASK 0x1
+#define DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_EN__SHIFT 0x0
+#define DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_PERIOD_MASK 0x1fffe
+#define DMA_ACTIVE_SAMPLER_CFG__SAMPLING_TIMER_PERIOD__SHIFT 0x1
+#define DMA_ACTIVE_SAMPLER_CFG__DMA_ACTIVE_TRANS_CNT_MASK 0x60000
+#define DMA_ACTIVE_SAMPLER_CFG__DMA_ACTIVE_TRANS_CNT__SHIFT 0x11
+#define SOUTHBRIDGE_TYPE__DISCRETE_SB_MASK 0x1
+#define SOUTHBRIDGE_TYPE__DISCRETE_SB__SHIFT 0x0
+#define GNBPM_SMU_PWRMGT_STATUS__PM_AllCpusInCC6_MASK 0x1
+#define GNBPM_SMU_PWRMGT_STATUS__PM_AllCpusInCC6__SHIFT 0x0
+#define GNBPM_SMU_PWRMGT_STATUS__PM_HtcActive_MASK 0x2
+#define GNBPM_SMU_PWRMGT_STATUS__PM_HtcActive__SHIFT 0x1
+#define GNBPM_SMU_PWRMGT_STATUS__PM_SmuInt_MASK 0x4
+#define GNBPM_SMU_PWRMGT_STATUS__PM_SmuInt__SHIFT 0x2
+#define GNBPM_SMU_PWRMGT_STATUS__PM_SmuIntSuperVminExit_MASK 0x8
+#define GNBPM_SMU_PWRMGT_STATUS__PM_SmuIntSuperVminExit__SHIFT 0x3
+#define GNBPM_SMU_PWRMGT_STATUS__PM_PreSelfRefresh_MASK 0x10
+#define GNBPM_SMU_PWRMGT_STATUS__PM_PreSelfRefresh__SHIFT 0x4
+#define GNBPM_SMU_PWRMGT_STATUS__PM_ReqNbPstate_MASK 0x20
+#define GNBPM_SMU_PWRMGT_STATUS__PM_ReqNbPstate__SHIFT 0x5
+#define GNBPM_SMU_PWRMGT_STATUS__PM_AllowNbPstate_MASK 0x40
+#define GNBPM_SMU_PWRMGT_STATUS__PM_AllowNbPstate__SHIFT 0x6
+#define GNBPM_SMU_PWRMGT_STATUS__PM_AllowSelfRefresh_MASK 0x80
+#define GNBPM_SMU_PWRMGT_STATUS__PM_AllowSelfRefresh__SHIFT 0x7
+#define GNBPM_SMU_PWRMGT_STATUS__PM_IntrWake_MASK 0x100
+#define GNBPM_SMU_PWRMGT_STATUS__PM_IntrWake__SHIFT 0x8
+#define GNBPM_SMU_PWRMGT_STATUS__SPARE_MASK 0xfe00
+#define GNBPM_SMU_PWRMGT_STATUS__SPARE__SHIFT 0x9
+#define ALLOW_SR_INTR_CTRL__ALLOW_SR_INTR_CTRL_MASK 0x3
+#define ALLOW_SR_INTR_CTRL__ALLOW_SR_INTR_CTRL__SHIFT 0x0
+#define GC_CAC_LKG_AGGR_LOWER__LKG_AGGR_31_0_MASK 0xffffffff
+#define GC_CAC_LKG_AGGR_LOWER__LKG_AGGR_31_0__SHIFT 0x0
+#define GC_CAC_LKG_AGGR_UPPER__LKG_AGGR_63_32_MASK 0xffffffff
+#define GC_CAC_LKG_AGGR_UPPER__LKG_AGGR_63_32__SHIFT 0x0
+#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0xffff
+#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0
+#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1_MASK 0xffff0000
+#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1__SHIFT 0x10
+#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2_MASK 0xffff
+#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2__SHIFT 0x0
+#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3_MASK 0xffff0000
+#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3__SHIFT 0x10
+#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4_MASK 0xffff
+#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4__SHIFT 0x0
+#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5_MASK 0xffff0000
+#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5__SHIFT 0x10
+#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6_MASK 0xffff
+#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6__SHIFT 0x0
+#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7_MASK 0xffff0000
+#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7__SHIFT 0x10
+#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK 0xffffffff
+#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK 0xffffffff
+#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK 0xffffffff
+#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK 0xffffffff
+#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0_MASK 0xffffffff
+#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0_MASK 0xffffffff
+#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0_MASK 0xffffffff
+#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0_MASK 0xffffffff
+#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0__SHIFT 0x0
+#define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK 0xffff
+#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0
+#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0xffff0000
+#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x10
+
+#endif /* SMU_8_0_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h
new file mode 100644
index 000000000000..f3e53b118361
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h
@@ -0,0 +1,95 @@
+/*
+ * UVD_4_2 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef UVD_4_2_D_H
+#define UVD_4_2_D_H
+
+#define mmUVD_SEMA_ADDR_LOW 0x3bc0
+#define mmUVD_SEMA_ADDR_HIGH 0x3bc1
+#define mmUVD_SEMA_CMD 0x3bc2
+#define mmUVD_GPCOM_VCPU_CMD 0x3bc3
+#define mmUVD_GPCOM_VCPU_DATA0 0x3bc4
+#define mmUVD_GPCOM_VCPU_DATA1 0x3bc5
+#define mmUVD_ENGINE_CNTL 0x3bc6
+#define mmUVD_UDEC_ADDR_CONFIG 0x3bd3
+#define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4
+#define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5
+#define mmUVD_SEMA_CNTL 0x3d00
+#define mmUVD_LMI_EXT40_ADDR 0x3d26
+#define mmUVD_CTX_INDEX 0x3d28
+#define mmUVD_CTX_DATA 0x3d29
+#define mmUVD_CGC_GATE 0x3d2a
+#define mmUVD_CGC_STATUS 0x3d2b
+#define mmUVD_CGC_CTRL 0x3d2c
+#define mmUVD_CGC_UDEC_STATUS 0x3d2d
+#define mmUVD_LMI_CTRL2 0x3d3d
+#define mmUVD_MASTINT_EN 0x3d40
+#define mmUVD_LMI_ADDR_EXT 0x3d65
+#define mmUVD_LMI_CTRL 0x3d66
+#define mmUVD_LMI_STATUS 0x3d67
+#define mmUVD_LMI_SWAP_CNTL 0x3d6d
+#define mmUVD_MP_SWAP_CNTL 0x3d6f
+#define mmUVD_MPC_CNTL 0x3d77
+#define mmUVD_MPC_SET_MUXA0 0x3d79
+#define mmUVD_MPC_SET_MUXA1 0x3d7a
+#define mmUVD_MPC_SET_MUXB0 0x3d7b
+#define mmUVD_MPC_SET_MUXB1 0x3d7c
+#define mmUVD_MPC_SET_MUX 0x3d7d
+#define mmUVD_MPC_SET_ALU 0x3d7e
+#define mmUVD_VCPU_CACHE_OFFSET0 0x3d82
+#define mmUVD_VCPU_CACHE_SIZE0 0x3d83
+#define mmUVD_VCPU_CACHE_OFFSET1 0x3d84
+#define mmUVD_VCPU_CACHE_SIZE1 0x3d85
+#define mmUVD_VCPU_CACHE_OFFSET2 0x3d86
+#define mmUVD_VCPU_CACHE_SIZE2 0x3d87
+#define mmUVD_VCPU_CNTL 0x3d98
+#define mmUVD_SOFT_RESET 0x3da0
+#define mmUVD_RBC_IB_BASE 0x3da1
+#define mmUVD_RBC_IB_SIZE 0x3da2
+#define mmUVD_RBC_RB_BASE 0x3da3
+#define mmUVD_RBC_RB_RPTR 0x3da4
+#define mmUVD_RBC_RB_WPTR 0x3da5
+#define mmUVD_RBC_RB_WPTR_CNTL 0x3da6
+#define mmUVD_RBC_RB_CNTL 0x3da9
+#define mmUVD_RBC_RB_RPTR_ADDR 0x3daa
+#define mmUVD_STATUS 0x3daf
+#define mmUVD_SEMA_TIMEOUT_STATUS 0x3db0
+#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x3db1
+#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x3db2
+#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3db3
+#define mmUVD_CONTEXT_ID 0x3dbd
+#define mmUVD_RBC_IB_SIZE_UPDATE 0x3df1
+#define ixUVD_LMI_CACHE_CTRL 0x9b
+#define ixUVD_LMI_SWAP_CNTL2 0xaa
+#define ixUVD_LMI_ADDR_EXT2 0xab
+#define ixUVD_CGC_MEM_CTRL 0xc0
+#define ixUVD_CGC_CTRL2 0xc1
+#define mmUVD_PGFSM_CONFIG 0x38f8
+#define mmUVD_PGFSM_READ_TILE1 0x38fa
+#define mmUVD_PGFSM_READ_TILE2 0x38fb
+#define mmUVD_POWER_STATUS 0x38fc
+#define ixUVD_MIF_CURR_ADDR_CONFIG 0x48
+#define ixUVD_MIF_REF_ADDR_CONFIG 0x4c
+#define ixUVD_MIF_RECON1_ADDR_CONFIG 0x114
+
+#endif /* UVD_4_2_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h
new file mode 100644
index 000000000000..65e8be9e9781
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h
@@ -0,0 +1,800 @@
+/*
+ * UVD_4_2 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef UVD_4_2_SH_MASK_H
+#define UVD_4_2_SH_MASK_H
+
+#define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
+#define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
+#define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
+#define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
+#define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
+#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
+#define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
+#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
+#define UVD_SEMA_CMD__MODE_MASK 0x40
+#define UVD_SEMA_CMD__MODE__SHIFT 0x6
+#define UVD_SEMA_CMD__VMID_EN_MASK 0x80
+#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7
+#define UVD_SEMA_CMD__VMID_MASK 0xf00
+#define UVD_SEMA_CMD__VMID__SHIFT 0x8
+#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1
+#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0
+#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffe
+#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1
+#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000
+#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f
+#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff
+#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0
+#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffff
+#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0
+#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1
+#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0
+#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2
+#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1
+#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1
+#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0
+#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2
+#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1
+#define UVD_LMI_EXT40_ADDR__ADDR_MASK 0xff
+#define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x0
+#define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x1f0000
+#define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x10
+#define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000
+#define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x1f
+#define UVD_CTX_INDEX__INDEX_MASK 0x1ff
+#define UVD_CTX_INDEX__INDEX__SHIFT 0x0
+#define UVD_CTX_DATA__DATA_MASK 0xffffffff
+#define UVD_CTX_DATA__DATA__SHIFT 0x0
+#define UVD_CGC_GATE__SYS_MASK 0x1
+#define UVD_CGC_GATE__SYS__SHIFT 0x0
+#define UVD_CGC_GATE__UDEC_MASK 0x2
+#define UVD_CGC_GATE__UDEC__SHIFT 0x1
+#define UVD_CGC_GATE__MPEG2_MASK 0x4
+#define UVD_CGC_GATE__MPEG2__SHIFT 0x2
+#define UVD_CGC_GATE__REGS_MASK 0x8
+#define UVD_CGC_GATE__REGS__SHIFT 0x3
+#define UVD_CGC_GATE__RBC_MASK 0x10
+#define UVD_CGC_GATE__RBC__SHIFT 0x4
+#define UVD_CGC_GATE__LMI_MC_MASK 0x20
+#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5
+#define UVD_CGC_GATE__LMI_UMC_MASK 0x40
+#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6
+#define UVD_CGC_GATE__IDCT_MASK 0x80
+#define UVD_CGC_GATE__IDCT__SHIFT 0x7
+#define UVD_CGC_GATE__MPRD_MASK 0x100
+#define UVD_CGC_GATE__MPRD__SHIFT 0x8
+#define UVD_CGC_GATE__MPC_MASK 0x200
+#define UVD_CGC_GATE__MPC__SHIFT 0x9
+#define UVD_CGC_GATE__LBSI_MASK 0x400
+#define UVD_CGC_GATE__LBSI__SHIFT 0xa
+#define UVD_CGC_GATE__LRBBM_MASK 0x800
+#define UVD_CGC_GATE__LRBBM__SHIFT 0xb
+#define UVD_CGC_GATE__UDEC_RE_MASK 0x1000
+#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc
+#define UVD_CGC_GATE__UDEC_CM_MASK 0x2000
+#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd
+#define UVD_CGC_GATE__UDEC_IT_MASK 0x4000
+#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe
+#define UVD_CGC_GATE__UDEC_DB_MASK 0x8000
+#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf
+#define UVD_CGC_GATE__UDEC_MP_MASK 0x10000
+#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10
+#define UVD_CGC_GATE__WCB_MASK 0x20000
+#define UVD_CGC_GATE__WCB__SHIFT 0x11
+#define UVD_CGC_GATE__VCPU_MASK 0x40000
+#define UVD_CGC_GATE__VCPU__SHIFT 0x12
+#define UVD_CGC_GATE__SCPU_MASK 0x80000
+#define UVD_CGC_GATE__SCPU__SHIFT 0x13
+#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1
+#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0
+#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2
+#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1
+#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x4
+#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2
+#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x8
+#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3
+#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10
+#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4
+#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x20
+#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5
+#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40
+#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6
+#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x80
+#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7
+#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100
+#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8
+#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200
+#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9
+#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400
+#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa
+#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800
+#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb
+#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000
+#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc
+#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x2000
+#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd
+#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x4000
+#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe
+#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x8000
+#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf
+#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x10000
+#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10
+#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000
+#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11
+#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000
+#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12
+#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000
+#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13
+#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000
+#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
+#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x200000
+#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15
+#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x400000
+#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16
+#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000
+#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17
+#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000
+#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18
+#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x2000000
+#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19
+#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x4000000
+#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a
+#define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x8000000
+#define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b
+#define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000
+#define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c
+#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1
+#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
+#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c
+#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2
+#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0
+#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6
+#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800
+#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb
+#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000
+#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc
+#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000
+#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
+#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000
+#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe
+#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000
+#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf
+#define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000
+#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
+#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000
+#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11
+#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000
+#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12
+#define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000
+#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13
+#define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000
+#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14
+#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000
+#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15
+#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000
+#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16
+#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000
+#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17
+#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000
+#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18
+#define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000
+#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19
+#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000
+#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a
+#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000
+#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b
+#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000
+#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c
+#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000
+#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d
+#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000
+#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e
+#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x1
+#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0
+#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2
+#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1
+#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x4
+#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2
+#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8
+#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3
+#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10
+#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4
+#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20
+#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5
+#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x40
+#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6
+#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80
+#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7
+#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100
+#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8
+#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200
+#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9
+#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x400
+#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa
+#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800
+#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb
+#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000
+#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc
+#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000
+#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd
+#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000
+#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe
+#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x1
+#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0
+#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2
+#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1
+#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x4
+#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2
+#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x8
+#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3
+#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x70
+#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x4
+#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x80
+#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7
+#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100
+#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
+#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x600
+#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9
+#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x1800
+#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb
+#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x2000
+#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd
+#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x4000
+#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe
+#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000
+#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf
+#define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x10000
+#define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10
+#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x1fe0000
+#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11
+#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x1
+#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0
+#define UVD_MASTINT_EN__VCPU_EN_MASK 0x2
+#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1
+#define UVD_MASTINT_EN__SYS_EN_MASK 0x4
+#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2
+#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x7ffff0
+#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4
+#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0xf
+#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x0
+#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0xf0
+#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x4
+#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0xf00
+#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x8
+#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0xf000
+#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0xc
+#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0xf0000
+#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x10
+#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0xf00000
+#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14
+#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0xf000000
+#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x18
+#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000
+#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x1c
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0xff
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8
+#define UVD_LMI_CTRL__REQ_MODE_MASK 0x200
+#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9
+#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800
+#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb
+#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000
+#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc
+#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x2000
+#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd
+#define UVD_LMI_CTRL__CRC_RESET_MASK 0x4000
+#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe
+#define UVD_LMI_CTRL__CRC_SEL_MASK 0xf8000
+#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf
+#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x100000
+#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14
+#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000
+#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15
+#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x400000
+#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16
+#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x800000
+#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17
+#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x1000000
+#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18
+#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x2000000
+#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19
+#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x4000000
+#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a
+#define UVD_LMI_CTRL__RFU_MASK 0xf8000000
+#define UVD_LMI_CTRL__RFU__SHIFT 0x1b
+#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x1
+#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0
+#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2
+#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1
+#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4
+#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2
+#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x8
+#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3
+#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x10
+#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4
+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x20
+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5
+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x40
+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6
+#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x80
+#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7
+#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100
+#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8
+#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200
+#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9
+#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x400
+#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa
+#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800
+#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb
+#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000
+#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc
+#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x2000
+#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd
+#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x3
+#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
+#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0xc
+#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
+#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x30
+#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4
+#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0xc0
+#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6
+#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x300
+#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8
+#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0xc00
+#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa
+#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x3000
+#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc
+#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0xc000
+#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe
+#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x30000
+#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10
+#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0xc0000
+#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12
+#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0xc00000
+#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16
+#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x3000000
+#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18
+#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0xc000000
+#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a
+#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000
+#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c
+#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000
+#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e
+#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x3
+#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0
+#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0xc
+#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2
+#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x30
+#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4
+#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0xc0
+#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6
+#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x300
+#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8
+#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0xc00
+#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa
+#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x3000
+#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc
+#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0xc000
+#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe
+#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x30000
+#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10
+#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0xc0000
+#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12
+#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x300000
+#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14
+#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0xc00000
+#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16
+#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x3000000
+#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18
+#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0xc000000
+#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a
+#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000
+#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c
+#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000
+#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e
+#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38
+#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3
+#define UVD_MPC_CNTL__PERF_RST_MASK 0x40
+#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6
+#define UVD_MPC_CNTL__DBG_MUX_MASK 0x700
+#define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x8
+#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x30000
+#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10
+#define UVD_MPC_CNTL__URGENT_EN_MASK 0x40000
+#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12
+#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f
+#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0
+#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0
+#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6
+#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000
+#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc
+#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000
+#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12
+#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000
+#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18
+#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f
+#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0
+#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0
+#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6
+#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000
+#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc
+#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x3f
+#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0
+#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0
+#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6
+#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x3f000
+#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc
+#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0xfc0000
+#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12
+#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000
+#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18
+#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f
+#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0
+#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0xfc0
+#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6
+#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000
+#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc
+#define UVD_MPC_SET_MUX__SET_0_MASK 0x7
+#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0
+#define UVD_MPC_SET_MUX__SET_1_MASK 0x38
+#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3
+#define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0
+#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6
+#define UVD_MPC_SET_ALU__FUNCT_MASK 0x7
+#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0
+#define UVD_MPC_SET_ALU__OPERAND_MASK 0xff0
+#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4
+#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff
+#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff
+#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff
+#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff
+#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x1ffffff
+#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x1fffff
+#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0
+#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0xf
+#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0
+#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x10
+#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4
+#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x20
+#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5
+#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x40
+#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6
+#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x80
+#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7
+#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100
+#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8
+#define UVD_VCPU_CNTL__CLK_EN_MASK 0x200
+#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9
+#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x400
+#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa
+#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800
+#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb
+#define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000
+#define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd
+#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x10000
+#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10
+#define UVD_VCPU_CNTL__CLK_ACTIVE_MASK 0x20000
+#define UVD_VCPU_CNTL__CLK_ACTIVE__SHIFT 0x11
+#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x40000
+#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12
+#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0xff00000
+#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14
+#define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000
+#define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c
+#define UVD_VCPU_CNTL__ECPU_AM32_EN_MASK 0x20000000
+#define UVD_VCPU_CNTL__ECPU_AM32_EN__SHIFT 0x1d
+#define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000
+#define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e
+#define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000
+#define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f
+#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x1
+#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0
+#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2
+#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1
+#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x4
+#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2
+#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x8
+#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3
+#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x10
+#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4
+#define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x20
+#define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5
+#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x40
+#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6
+#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x80
+#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7
+#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100
+#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8
+#define UVD_SOFT_RESET__FWV_SOFT_RESET_MASK 0x200
+#define UVD_SOFT_RESET__FWV_SOFT_RESET__SHIFT 0x9
+#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x400
+#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa
+#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800
+#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb
+#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000
+#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc
+#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x2000
+#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd
+#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x4000
+#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe
+#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x8000
+#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf
+#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x10000
+#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10
+#define UVD_RBC_IB_BASE__IB_BASE_MASK 0xffffffc0
+#define UVD_RBC_IB_BASE__IB_BASE__SHIFT 0x6
+#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x7ffff0
+#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4
+#define UVD_RBC_RB_BASE__RB_BASE_MASK 0xffffffc0
+#define UVD_RBC_RB_BASE__RB_BASE__SHIFT 0x6
+#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x7ffff0
+#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4
+#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x7ffff0
+#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4
+#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x1f
+#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0
+#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x1f00
+#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8
+#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000
+#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10
+#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x100000
+#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14
+#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x1000000
+#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18
+#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000
+#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c
+#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffff
+#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0
+#define UVD_STATUS__RBC_BUSY_MASK 0x1
+#define UVD_STATUS__RBC_BUSY__SHIFT 0x0
+#define UVD_STATUS__VCPU_REPORT_MASK 0xfe
+#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x1
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x4
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x8
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x1
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x1ffffe
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x1
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x1ffffe
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x1
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x1ffffe
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
+#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffff
+#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0
+#define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x1
+#define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x0
+#define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2
+#define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x1
+#define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x4
+#define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2
+#define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x8
+#define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x3
+#define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x10
+#define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x4
+#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x20
+#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x5
+#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x3
+#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0
+#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0xc
+#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2
+#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0xf
+#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x0
+#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0xf0
+#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x4
+#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0xf00
+#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x8
+#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0xf000
+#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0xc
+#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x1
+#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0
+#define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2
+#define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1
+#define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x4
+#define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2
+#define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x8
+#define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3
+#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x10
+#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4
+#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20
+#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5
+#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x40
+#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6
+#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80
+#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7
+#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100
+#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8
+#define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200
+#define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9
+#define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x400
+#define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa
+#define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800
+#define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0xb
+#define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000
+#define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc
+#define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x2000
+#define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd
+#define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0xf0000
+#define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10
+#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0xf00000
+#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14
+#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1
+#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0
+#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2
+#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1
+#define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x1c
+#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0xff
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x0
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x8
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x9
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x400
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0xb
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0xc
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x2000
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0xd
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x1c
+#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0xffffff
+#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x0
+#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0xffffff
+#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x0
+#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x1
+#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+
+#endif /* UVD_4_2_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h
new file mode 100644
index 000000000000..eb4cf53427da
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h
@@ -0,0 +1,114 @@
+/*
+ * UVD_5_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef UVD_5_0_D_H
+#define UVD_5_0_D_H
+
+#define mmUVD_SEMA_ADDR_LOW 0x3bc0
+#define mmUVD_SEMA_ADDR_HIGH 0x3bc1
+#define mmUVD_SEMA_CMD 0x3bc2
+#define mmUVD_GPCOM_VCPU_CMD 0x3bc3
+#define mmUVD_GPCOM_VCPU_DATA0 0x3bc4
+#define mmUVD_GPCOM_VCPU_DATA1 0x3bc5
+#define mmUVD_ENGINE_CNTL 0x3bc6
+#define mmUVD_UDEC_ADDR_CONFIG 0x3bd3
+#define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4
+#define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5
+#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x3c69
+#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x3c68
+#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x3c67
+#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x3c66
+#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x3c5f
+#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x3c5e
+#define mmUVD_SEMA_CNTL 0x3d00
+#define mmUVD_LMI_EXT40_ADDR 0x3d26
+#define mmUVD_CTX_INDEX 0x3d28
+#define mmUVD_CTX_DATA 0x3d29
+#define mmUVD_CGC_GATE 0x3d2a
+#define mmUVD_CGC_STATUS 0x3d2b
+#define mmUVD_CGC_CTRL 0x3d2c
+#define mmUVD_CGC_UDEC_STATUS 0x3d2d
+#define mmUVD_LMI_CTRL2 0x3d3d
+#define mmUVD_MASTINT_EN 0x3d40
+#define mmUVD_LMI_ADDR_EXT 0x3d65
+#define mmUVD_LMI_CTRL 0x3d66
+#define mmUVD_LMI_STATUS 0x3d67
+#define mmUVD_LMI_SWAP_CNTL 0x3d6d
+#define mmUVD_MP_SWAP_CNTL 0x3d6f
+#define mmUVD_MPC_CNTL 0x3d77
+#define mmUVD_MPC_SET_MUXA0 0x3d79
+#define mmUVD_MPC_SET_MUXA1 0x3d7a
+#define mmUVD_MPC_SET_MUXB0 0x3d7b
+#define mmUVD_MPC_SET_MUXB1 0x3d7c
+#define mmUVD_MPC_SET_MUX 0x3d7d
+#define mmUVD_MPC_SET_ALU 0x3d7e
+#define mmUVD_VCPU_CACHE_OFFSET0 0x3d82
+#define mmUVD_VCPU_CACHE_SIZE0 0x3d83
+#define mmUVD_VCPU_CACHE_OFFSET1 0x3d84
+#define mmUVD_VCPU_CACHE_SIZE1 0x3d85
+#define mmUVD_VCPU_CACHE_OFFSET2 0x3d86
+#define mmUVD_VCPU_CACHE_SIZE2 0x3d87
+#define mmUVD_VCPU_CNTL 0x3d98
+#define mmUVD_SOFT_RESET 0x3da0
+#define mmUVD_LMI_RBC_IB_VMID 0x3da1
+#define mmUVD_RBC_IB_SIZE 0x3da2
+#define mmUVD_LMI_RBC_RB_VMID 0x3da3
+#define mmUVD_RBC_RB_RPTR 0x3da4
+#define mmUVD_RBC_RB_WPTR 0x3da5
+#define mmUVD_RBC_RB_WPTR_CNTL 0x3da6
+#define mmUVD_RBC_RB_CNTL 0x3da9
+#define mmUVD_RBC_RB_RPTR_ADDR 0x3daa
+#define mmUVD_STATUS 0x3daf
+#define mmUVD_SEMA_TIMEOUT_STATUS 0x3db0
+#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x3db1
+#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x3db2
+#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3db3
+#define mmUVD_CONTEXT_ID 0x3dbd
+#define mmUVD_RBC_IB_SIZE_UPDATE 0x3df1
+#define mmUVD_SUVD_CGC_GATE 0x3be4
+#define mmUVD_SUVD_CGC_STATUS 0x3be5
+#define mmUVD_SUVD_CGC_CTRL 0x3be6
+#define ixUVD_LMI_VMID_INTERNAL 0x99
+#define ixUVD_LMI_VMID_INTERNAL2 0x9a
+#define ixUVD_LMI_CACHE_CTRL 0x9b
+#define ixUVD_LMI_SWAP_CNTL2 0xaa
+#define ixUVD_LMI_ADDR_EXT2 0xab
+#define ixUVD_CGC_MEM_CTRL 0xc0
+#define ixUVD_CGC_CTRL2 0xc1
+#define ixUVD_LMI_VMID_INTERNAL3 0x162
+#define mmUVD_PGFSM_CONFIG 0x38c0
+#define mmUVD_PGFSM_READ_TILE1 0x38c2
+#define mmUVD_PGFSM_READ_TILE2 0x38c3
+#define mmUVD_POWER_STATUS 0x38c4
+#define mmUVD_PGFSM_READ_TILE3 0x38c5
+#define mmUVD_PGFSM_READ_TILE4 0x38c6
+#define mmUVD_PGFSM_READ_TILE5 0x38c8
+#define mmUVD_PGFSM_READ_TILE6 0x38ee
+#define mmUVD_PGFSM_READ_TILE7 0x38ef
+#define mmUVD_MIF_CURR_ADDR_CONFIG 0x3992
+#define mmUVD_MIF_REF_ADDR_CONFIG 0x3993
+#define mmUVD_MIF_RECON1_ADDR_CONFIG 0x39c5
+#define ixUVD_MIF_SCLR_ADDR_CONFIG 0x4
+#define mmUVD_JPEG_ADDR_CONFIG 0x3a1f
+
+#endif /* UVD_5_0_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_enum.h
new file mode 100644
index 000000000000..981086f8ee4e
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_enum.h
@@ -0,0 +1,1211 @@
+/*
+ * UVD_5_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef UVD_5_0_ENUM_H
+#define UVD_5_0_ENUM_H
+
+typedef enum UVDFirmwareCommand {
+ UVDFC_FENCE = 0x0,
+ UVDFC_TRAP = 0x1,
+ UVDFC_DECODED_ADDR = 0x2,
+ UVDFC_MBLOCK_ADDR = 0x3,
+ UVDFC_ITBUF_ADDR = 0x4,
+ UVDFC_DISPLAY_ADDR = 0x5,
+ UVDFC_EOD = 0x6,
+ UVDFC_DISPLAY_PITCH = 0x7,
+ UVDFC_DISPLAY_TILING = 0x8,
+ UVDFC_BITSTREAM_ADDR = 0x9,
+ UVDFC_BITSTREAM_SIZE = 0xa,
+} UVDFirmwareCommand;
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0x0,
+ ENDIAN_8IN16 = 0x1,
+ ENDIAN_8IN32 = 0x2,
+ ENDIAN_8IN64 = 0x3,
+} SurfaceEndian;
+typedef enum ArrayMode {
+ ARRAY_LINEAR_GENERAL = 0x0,
+ ARRAY_LINEAR_ALIGNED = 0x1,
+ ARRAY_1D_TILED_THIN1 = 0x2,
+ ARRAY_1D_TILED_THICK = 0x3,
+ ARRAY_2D_TILED_THIN1 = 0x4,
+ ARRAY_PRT_TILED_THIN1 = 0x5,
+ ARRAY_PRT_2D_TILED_THIN1 = 0x6,
+ ARRAY_2D_TILED_THICK = 0x7,
+ ARRAY_2D_TILED_XTHICK = 0x8,
+ ARRAY_PRT_TILED_THICK = 0x9,
+ ARRAY_PRT_2D_TILED_THICK = 0xa,
+ ARRAY_PRT_3D_TILED_THIN1 = 0xb,
+ ARRAY_3D_TILED_THIN1 = 0xc,
+ ARRAY_3D_TILED_THICK = 0xd,
+ ARRAY_3D_TILED_XTHICK = 0xe,
+ ARRAY_PRT_3D_TILED_THICK = 0xf,
+} ArrayMode;
+typedef enum PipeTiling {
+ CONFIG_1_PIPE = 0x0,
+ CONFIG_2_PIPE = 0x1,
+ CONFIG_4_PIPE = 0x2,
+ CONFIG_8_PIPE = 0x3,
+} PipeTiling;
+typedef enum BankTiling {
+ CONFIG_4_BANK = 0x0,
+ CONFIG_8_BANK = 0x1,
+} BankTiling;
+typedef enum GroupInterleave {
+ CONFIG_256B_GROUP = 0x0,
+ CONFIG_512B_GROUP = 0x1,
+} GroupInterleave;
+typedef enum RowTiling {
+ CONFIG_1KB_ROW = 0x0,
+ CONFIG_2KB_ROW = 0x1,
+ CONFIG_4KB_ROW = 0x2,
+ CONFIG_8KB_ROW = 0x3,
+ CONFIG_1KB_ROW_OPT = 0x4,
+ CONFIG_2KB_ROW_OPT = 0x5,
+ CONFIG_4KB_ROW_OPT = 0x6,
+ CONFIG_8KB_ROW_OPT = 0x7,
+} RowTiling;
+typedef enum BankSwapBytes {
+ CONFIG_128B_SWAPS = 0x0,
+ CONFIG_256B_SWAPS = 0x1,
+ CONFIG_512B_SWAPS = 0x2,
+ CONFIG_1KB_SWAPS = 0x3,
+} BankSwapBytes;
+typedef enum SampleSplitBytes {
+ CONFIG_1KB_SPLIT = 0x0,
+ CONFIG_2KB_SPLIT = 0x1,
+ CONFIG_4KB_SPLIT = 0x2,
+ CONFIG_8KB_SPLIT = 0x3,
+} SampleSplitBytes;
+typedef enum NumPipes {
+ ADDR_CONFIG_1_PIPE = 0x0,
+ ADDR_CONFIG_2_PIPE = 0x1,
+ ADDR_CONFIG_4_PIPE = 0x2,
+ ADDR_CONFIG_8_PIPE = 0x3,
+} NumPipes;
+typedef enum PipeInterleaveSize {
+ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
+ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
+} PipeInterleaveSize;
+typedef enum BankInterleaveSize {
+ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
+ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
+ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
+ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
+} BankInterleaveSize;
+typedef enum NumShaderEngines {
+ ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
+ ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
+} NumShaderEngines;
+typedef enum ShaderEngineTileSize {
+ ADDR_CONFIG_SE_TILE_16 = 0x0,
+ ADDR_CONFIG_SE_TILE_32 = 0x1,
+} ShaderEngineTileSize;
+typedef enum NumGPUs {
+ ADDR_CONFIG_1_GPU = 0x0,
+ ADDR_CONFIG_2_GPU = 0x1,
+ ADDR_CONFIG_4_GPU = 0x2,
+} NumGPUs;
+typedef enum MultiGPUTileSize {
+ ADDR_CONFIG_GPU_TILE_16 = 0x0,
+ ADDR_CONFIG_GPU_TILE_32 = 0x1,
+ ADDR_CONFIG_GPU_TILE_64 = 0x2,
+ ADDR_CONFIG_GPU_TILE_128 = 0x3,
+} MultiGPUTileSize;
+typedef enum RowSize {
+ ADDR_CONFIG_1KB_ROW = 0x0,
+ ADDR_CONFIG_2KB_ROW = 0x1,
+ ADDR_CONFIG_4KB_ROW = 0x2,
+} RowSize;
+typedef enum NumLowerPipes {
+ ADDR_CONFIG_1_LOWER_PIPES = 0x0,
+ ADDR_CONFIG_2_LOWER_PIPES = 0x1,
+} NumLowerPipes;
+typedef enum DebugBlockId {
+ DBG_CLIENT_BLKID_RESERVED = 0x0,
+ DBG_CLIENT_BLKID_dbg = 0x1,
+ DBG_CLIENT_BLKID_scf2 = 0x2,
+ DBG_CLIENT_BLKID_mcd5 = 0x3,
+ DBG_CLIENT_BLKID_vmc = 0x4,
+ DBG_CLIENT_BLKID_sx30 = 0x5,
+ DBG_CLIENT_BLKID_mcd2 = 0x6,
+ DBG_CLIENT_BLKID_bci1 = 0x7,
+ DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8,
+ DBG_CLIENT_BLKID_mcc0 = 0x9,
+ DBG_CLIENT_BLKID_uvdf_0 = 0xa,
+ DBG_CLIENT_BLKID_uvdf_1 = 0xb,
+ DBG_CLIENT_BLKID_uvdf_2 = 0xc,
+ DBG_CLIENT_BLKID_uvdi_0 = 0xd,
+ DBG_CLIENT_BLKID_bci0 = 0xe,
+ DBG_CLIENT_BLKID_vcec0_0 = 0xf,
+ DBG_CLIENT_BLKID_cb100 = 0x10,
+ DBG_CLIENT_BLKID_cb001 = 0x11,
+ DBG_CLIENT_BLKID_mcd4 = 0x12,
+ DBG_CLIENT_BLKID_tmonw00 = 0x13,
+ DBG_CLIENT_BLKID_cb101 = 0x14,
+ DBG_CLIENT_BLKID_sx10 = 0x15,
+ DBG_CLIENT_BLKID_cb301 = 0x16,
+ DBG_CLIENT_BLKID_tmonw01 = 0x17,
+ DBG_CLIENT_BLKID_vcea0_0 = 0x18,
+ DBG_CLIENT_BLKID_vcea0_1 = 0x19,
+ DBG_CLIENT_BLKID_vcea0_2 = 0x1a,
+ DBG_CLIENT_BLKID_vcea0_3 = 0x1b,
+ DBG_CLIENT_BLKID_scf1 = 0x1c,
+ DBG_CLIENT_BLKID_sx20 = 0x1d,
+ DBG_CLIENT_BLKID_spim1 = 0x1e,
+ DBG_CLIENT_BLKID_pa10 = 0x1f,
+ DBG_CLIENT_BLKID_pa00 = 0x20,
+ DBG_CLIENT_BLKID_gmcon = 0x21,
+ DBG_CLIENT_BLKID_mcb = 0x22,
+ DBG_CLIENT_BLKID_vgt0 = 0x23,
+ DBG_CLIENT_BLKID_pc0 = 0x24,
+ DBG_CLIENT_BLKID_bci2 = 0x25,
+ DBG_CLIENT_BLKID_uvdb_0 = 0x26,
+ DBG_CLIENT_BLKID_spim3 = 0x27,
+ DBG_CLIENT_BLKID_cpc_0 = 0x28,
+ DBG_CLIENT_BLKID_cpc_1 = 0x29,
+ DBG_CLIENT_BLKID_uvdm_0 = 0x2a,
+ DBG_CLIENT_BLKID_uvdm_1 = 0x2b,
+ DBG_CLIENT_BLKID_uvdm_2 = 0x2c,
+ DBG_CLIENT_BLKID_uvdm_3 = 0x2d,
+ DBG_CLIENT_BLKID_cb000 = 0x2e,
+ DBG_CLIENT_BLKID_spim0 = 0x2f,
+ DBG_CLIENT_BLKID_mcc2 = 0x30,
+ DBG_CLIENT_BLKID_ds0 = 0x31,
+ DBG_CLIENT_BLKID_srbm = 0x32,
+ DBG_CLIENT_BLKID_ih = 0x33,
+ DBG_CLIENT_BLKID_sem = 0x34,
+ DBG_CLIENT_BLKID_sdma_0 = 0x35,
+ DBG_CLIENT_BLKID_sdma_1 = 0x36,
+ DBG_CLIENT_BLKID_hdp = 0x37,
+ DBG_CLIENT_BLKID_acp_0 = 0x38,
+ DBG_CLIENT_BLKID_acp_1 = 0x39,
+ DBG_CLIENT_BLKID_cb200 = 0x3a,
+ DBG_CLIENT_BLKID_scf3 = 0x3b,
+ DBG_CLIENT_BLKID_vceb1_0 = 0x3c,
+ DBG_CLIENT_BLKID_vcea1_0 = 0x3d,
+ DBG_CLIENT_BLKID_vcea1_1 = 0x3e,
+ DBG_CLIENT_BLKID_vcea1_2 = 0x3f,
+ DBG_CLIENT_BLKID_vcea1_3 = 0x40,
+ DBG_CLIENT_BLKID_bci3 = 0x41,
+ DBG_CLIENT_BLKID_mcd0 = 0x42,
+ DBG_CLIENT_BLKID_pa11 = 0x43,
+ DBG_CLIENT_BLKID_pa01 = 0x44,
+ DBG_CLIENT_BLKID_cb201 = 0x45,
+ DBG_CLIENT_BLKID_spim2 = 0x46,
+ DBG_CLIENT_BLKID_vgt2 = 0x47,
+ DBG_CLIENT_BLKID_pc2 = 0x48,
+ DBG_CLIENT_BLKID_smu_0 = 0x49,
+ DBG_CLIENT_BLKID_smu_1 = 0x4a,
+ DBG_CLIENT_BLKID_smu_2 = 0x4b,
+ DBG_CLIENT_BLKID_cb1 = 0x4c,
+ DBG_CLIENT_BLKID_ia0 = 0x4d,
+ DBG_CLIENT_BLKID_wd = 0x4e,
+ DBG_CLIENT_BLKID_ia1 = 0x4f,
+ DBG_CLIENT_BLKID_vcec1_0 = 0x50,
+ DBG_CLIENT_BLKID_scf0 = 0x51,
+ DBG_CLIENT_BLKID_vgt1 = 0x52,
+ DBG_CLIENT_BLKID_pc1 = 0x53,
+ DBG_CLIENT_BLKID_cb0 = 0x54,
+ DBG_CLIENT_BLKID_gdc_one_0 = 0x55,
+ DBG_CLIENT_BLKID_gdc_one_1 = 0x56,
+ DBG_CLIENT_BLKID_gdc_one_2 = 0x57,
+ DBG_CLIENT_BLKID_gdc_one_3 = 0x58,
+ DBG_CLIENT_BLKID_gdc_one_4 = 0x59,
+ DBG_CLIENT_BLKID_gdc_one_5 = 0x5a,
+ DBG_CLIENT_BLKID_gdc_one_6 = 0x5b,
+ DBG_CLIENT_BLKID_gdc_one_7 = 0x5c,
+ DBG_CLIENT_BLKID_gdc_one_8 = 0x5d,
+ DBG_CLIENT_BLKID_gdc_one_9 = 0x5e,
+ DBG_CLIENT_BLKID_gdc_one_10 = 0x5f,
+ DBG_CLIENT_BLKID_gdc_one_11 = 0x60,
+ DBG_CLIENT_BLKID_gdc_one_12 = 0x61,
+ DBG_CLIENT_BLKID_gdc_one_13 = 0x62,
+ DBG_CLIENT_BLKID_gdc_one_14 = 0x63,
+ DBG_CLIENT_BLKID_gdc_one_15 = 0x64,
+ DBG_CLIENT_BLKID_gdc_one_16 = 0x65,
+ DBG_CLIENT_BLKID_gdc_one_17 = 0x66,
+ DBG_CLIENT_BLKID_gdc_one_18 = 0x67,
+ DBG_CLIENT_BLKID_gdc_one_19 = 0x68,
+ DBG_CLIENT_BLKID_gdc_one_20 = 0x69,
+ DBG_CLIENT_BLKID_gdc_one_21 = 0x6a,
+ DBG_CLIENT_BLKID_gdc_one_22 = 0x6b,
+ DBG_CLIENT_BLKID_gdc_one_23 = 0x6c,
+ DBG_CLIENT_BLKID_gdc_one_24 = 0x6d,
+ DBG_CLIENT_BLKID_gdc_one_25 = 0x6e,
+ DBG_CLIENT_BLKID_gdc_one_26 = 0x6f,
+ DBG_CLIENT_BLKID_gdc_one_27 = 0x70,
+ DBG_CLIENT_BLKID_gdc_one_28 = 0x71,
+ DBG_CLIENT_BLKID_gdc_one_29 = 0x72,
+ DBG_CLIENT_BLKID_gdc_one_30 = 0x73,
+ DBG_CLIENT_BLKID_gdc_one_31 = 0x74,
+ DBG_CLIENT_BLKID_gdc_one_32 = 0x75,
+ DBG_CLIENT_BLKID_gdc_one_33 = 0x76,
+ DBG_CLIENT_BLKID_gdc_one_34 = 0x77,
+ DBG_CLIENT_BLKID_gdc_one_35 = 0x78,
+ DBG_CLIENT_BLKID_vceb0_0 = 0x79,
+ DBG_CLIENT_BLKID_vgt3 = 0x7a,
+ DBG_CLIENT_BLKID_pc3 = 0x7b,
+ DBG_CLIENT_BLKID_mcd3 = 0x7c,
+ DBG_CLIENT_BLKID_uvdu_0 = 0x7d,
+ DBG_CLIENT_BLKID_uvdu_1 = 0x7e,
+ DBG_CLIENT_BLKID_uvdu_2 = 0x7f,
+ DBG_CLIENT_BLKID_uvdu_3 = 0x80,
+ DBG_CLIENT_BLKID_uvdu_4 = 0x81,
+ DBG_CLIENT_BLKID_uvdu_5 = 0x82,
+ DBG_CLIENT_BLKID_uvdu_6 = 0x83,
+ DBG_CLIENT_BLKID_cb300 = 0x84,
+ DBG_CLIENT_BLKID_mcd1 = 0x85,
+ DBG_CLIENT_BLKID_sx00 = 0x86,
+ DBG_CLIENT_BLKID_uvdc_0 = 0x87,
+ DBG_CLIENT_BLKID_uvdc_1 = 0x88,
+ DBG_CLIENT_BLKID_mcc3 = 0x89,
+ DBG_CLIENT_BLKID_cpg_0 = 0x8a,
+ DBG_CLIENT_BLKID_cpg_1 = 0x8b,
+ DBG_CLIENT_BLKID_gck = 0x8c,
+ DBG_CLIENT_BLKID_mcc1 = 0x8d,
+ DBG_CLIENT_BLKID_cpf_0 = 0x8e,
+ DBG_CLIENT_BLKID_cpf_1 = 0x8f,
+ DBG_CLIENT_BLKID_rlc = 0x90,
+ DBG_CLIENT_BLKID_grbm = 0x91,
+ DBG_CLIENT_BLKID_sammsp = 0x92,
+ DBG_CLIENT_BLKID_dci_pg = 0x93,
+ DBG_CLIENT_BLKID_dci_0 = 0x94,
+ DBG_CLIENT_BLKID_dccg0_0 = 0x95,
+ DBG_CLIENT_BLKID_dccg0_1 = 0x96,
+ DBG_CLIENT_BLKID_dcfe01_0 = 0x97,
+ DBG_CLIENT_BLKID_dcfe02_0 = 0x98,
+ DBG_CLIENT_BLKID_dcfe03_0 = 0x99,
+ DBG_CLIENT_BLKID_dcfe04_0 = 0x9a,
+ DBG_CLIENT_BLKID_dcfe05_0 = 0x9b,
+ DBG_CLIENT_BLKID_dcfe06_0 = 0x9c,
+ DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d,
+} DebugBlockId;
+typedef enum DebugBlockId_OLD {
+ DBG_BLOCK_ID_RESERVED = 0x0,
+ DBG_BLOCK_ID_DBG = 0x1,
+ DBG_BLOCK_ID_VMC = 0x2,
+ DBG_BLOCK_ID_PDMA = 0x3,
+ DBG_BLOCK_ID_CG = 0x4,
+ DBG_BLOCK_ID_SRBM = 0x5,
+ DBG_BLOCK_ID_GRBM = 0x6,
+ DBG_BLOCK_ID_RLC = 0x7,
+ DBG_BLOCK_ID_CSC = 0x8,
+ DBG_BLOCK_ID_SEM = 0x9,
+ DBG_BLOCK_ID_IH = 0xa,
+ DBG_BLOCK_ID_SC = 0xb,
+ DBG_BLOCK_ID_SQ = 0xc,
+ DBG_BLOCK_ID_AVP = 0xd,
+ DBG_BLOCK_ID_GMCON = 0xe,
+ DBG_BLOCK_ID_SMU = 0xf,
+ DBG_BLOCK_ID_DMA0 = 0x10,
+ DBG_BLOCK_ID_DMA1 = 0x11,
+ DBG_BLOCK_ID_SPIM = 0x12,
+ DBG_BLOCK_ID_GDS = 0x13,
+ DBG_BLOCK_ID_SPIS = 0x14,
+ DBG_BLOCK_ID_UNUSED0 = 0x15,
+ DBG_BLOCK_ID_PA0 = 0x16,
+ DBG_BLOCK_ID_PA1 = 0x17,
+ DBG_BLOCK_ID_CP0 = 0x18,
+ DBG_BLOCK_ID_CP1 = 0x19,
+ DBG_BLOCK_ID_CP2 = 0x1a,
+ DBG_BLOCK_ID_UNUSED1 = 0x1b,
+ DBG_BLOCK_ID_UVDU = 0x1c,
+ DBG_BLOCK_ID_UVDM = 0x1d,
+ DBG_BLOCK_ID_VCE = 0x1e,
+ DBG_BLOCK_ID_UNUSED2 = 0x1f,
+ DBG_BLOCK_ID_VGT0 = 0x20,
+ DBG_BLOCK_ID_VGT1 = 0x21,
+ DBG_BLOCK_ID_IA = 0x22,
+ DBG_BLOCK_ID_UNUSED3 = 0x23,
+ DBG_BLOCK_ID_SCT0 = 0x24,
+ DBG_BLOCK_ID_SCT1 = 0x25,
+ DBG_BLOCK_ID_SPM0 = 0x26,
+ DBG_BLOCK_ID_SPM1 = 0x27,
+ DBG_BLOCK_ID_TCAA = 0x28,
+ DBG_BLOCK_ID_TCAB = 0x29,
+ DBG_BLOCK_ID_TCCA = 0x2a,
+ DBG_BLOCK_ID_TCCB = 0x2b,
+ DBG_BLOCK_ID_MCC0 = 0x2c,
+ DBG_BLOCK_ID_MCC1 = 0x2d,
+ DBG_BLOCK_ID_MCC2 = 0x2e,
+ DBG_BLOCK_ID_MCC3 = 0x2f,
+ DBG_BLOCK_ID_SX0 = 0x30,
+ DBG_BLOCK_ID_SX1 = 0x31,
+ DBG_BLOCK_ID_SX2 = 0x32,
+ DBG_BLOCK_ID_SX3 = 0x33,
+ DBG_BLOCK_ID_UNUSED4 = 0x34,
+ DBG_BLOCK_ID_UNUSED5 = 0x35,
+ DBG_BLOCK_ID_UNUSED6 = 0x36,
+ DBG_BLOCK_ID_UNUSED7 = 0x37,
+ DBG_BLOCK_ID_PC0 = 0x38,
+ DBG_BLOCK_ID_PC1 = 0x39,
+ DBG_BLOCK_ID_UNUSED8 = 0x3a,
+ DBG_BLOCK_ID_UNUSED9 = 0x3b,
+ DBG_BLOCK_ID_UNUSED10 = 0x3c,
+ DBG_BLOCK_ID_UNUSED11 = 0x3d,
+ DBG_BLOCK_ID_MCB = 0x3e,
+ DBG_BLOCK_ID_UNUSED12 = 0x3f,
+ DBG_BLOCK_ID_SCB0 = 0x40,
+ DBG_BLOCK_ID_SCB1 = 0x41,
+ DBG_BLOCK_ID_UNUSED13 = 0x42,
+ DBG_BLOCK_ID_UNUSED14 = 0x43,
+ DBG_BLOCK_ID_SCF0 = 0x44,
+ DBG_BLOCK_ID_SCF1 = 0x45,
+ DBG_BLOCK_ID_UNUSED15 = 0x46,
+ DBG_BLOCK_ID_UNUSED16 = 0x47,
+ DBG_BLOCK_ID_BCI0 = 0x48,
+ DBG_BLOCK_ID_BCI1 = 0x49,
+ DBG_BLOCK_ID_BCI2 = 0x4a,
+ DBG_BLOCK_ID_BCI3 = 0x4b,
+ DBG_BLOCK_ID_UNUSED17 = 0x4c,
+ DBG_BLOCK_ID_UNUSED18 = 0x4d,
+ DBG_BLOCK_ID_UNUSED19 = 0x4e,
+ DBG_BLOCK_ID_UNUSED20 = 0x4f,
+ DBG_BLOCK_ID_CB00 = 0x50,
+ DBG_BLOCK_ID_CB01 = 0x51,
+ DBG_BLOCK_ID_CB02 = 0x52,
+ DBG_BLOCK_ID_CB03 = 0x53,
+ DBG_BLOCK_ID_CB04 = 0x54,
+ DBG_BLOCK_ID_UNUSED21 = 0x55,
+ DBG_BLOCK_ID_UNUSED22 = 0x56,
+ DBG_BLOCK_ID_UNUSED23 = 0x57,
+ DBG_BLOCK_ID_CB10 = 0x58,
+ DBG_BLOCK_ID_CB11 = 0x59,
+ DBG_BLOCK_ID_CB12 = 0x5a,
+ DBG_BLOCK_ID_CB13 = 0x5b,
+ DBG_BLOCK_ID_CB14 = 0x5c,
+ DBG_BLOCK_ID_UNUSED24 = 0x5d,
+ DBG_BLOCK_ID_UNUSED25 = 0x5e,
+ DBG_BLOCK_ID_UNUSED26 = 0x5f,
+ DBG_BLOCK_ID_TCP0 = 0x60,
+ DBG_BLOCK_ID_TCP1 = 0x61,
+ DBG_BLOCK_ID_TCP2 = 0x62,
+ DBG_BLOCK_ID_TCP3 = 0x63,
+ DBG_BLOCK_ID_TCP4 = 0x64,
+ DBG_BLOCK_ID_TCP5 = 0x65,
+ DBG_BLOCK_ID_TCP6 = 0x66,
+ DBG_BLOCK_ID_TCP7 = 0x67,
+ DBG_BLOCK_ID_TCP8 = 0x68,
+ DBG_BLOCK_ID_TCP9 = 0x69,
+ DBG_BLOCK_ID_TCP10 = 0x6a,
+ DBG_BLOCK_ID_TCP11 = 0x6b,
+ DBG_BLOCK_ID_TCP12 = 0x6c,
+ DBG_BLOCK_ID_TCP13 = 0x6d,
+ DBG_BLOCK_ID_TCP14 = 0x6e,
+ DBG_BLOCK_ID_TCP15 = 0x6f,
+ DBG_BLOCK_ID_TCP16 = 0x70,
+ DBG_BLOCK_ID_TCP17 = 0x71,
+ DBG_BLOCK_ID_TCP18 = 0x72,
+ DBG_BLOCK_ID_TCP19 = 0x73,
+ DBG_BLOCK_ID_TCP20 = 0x74,
+ DBG_BLOCK_ID_TCP21 = 0x75,
+ DBG_BLOCK_ID_TCP22 = 0x76,
+ DBG_BLOCK_ID_TCP23 = 0x77,
+ DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
+ DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
+ DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
+ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
+ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
+ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
+ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
+ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
+ DBG_BLOCK_ID_DB00 = 0x80,
+ DBG_BLOCK_ID_DB01 = 0x81,
+ DBG_BLOCK_ID_DB02 = 0x82,
+ DBG_BLOCK_ID_DB03 = 0x83,
+ DBG_BLOCK_ID_DB04 = 0x84,
+ DBG_BLOCK_ID_UNUSED27 = 0x85,
+ DBG_BLOCK_ID_UNUSED28 = 0x86,
+ DBG_BLOCK_ID_UNUSED29 = 0x87,
+ DBG_BLOCK_ID_DB10 = 0x88,
+ DBG_BLOCK_ID_DB11 = 0x89,
+ DBG_BLOCK_ID_DB12 = 0x8a,
+ DBG_BLOCK_ID_DB13 = 0x8b,
+ DBG_BLOCK_ID_DB14 = 0x8c,
+ DBG_BLOCK_ID_UNUSED30 = 0x8d,
+ DBG_BLOCK_ID_UNUSED31 = 0x8e,
+ DBG_BLOCK_ID_UNUSED32 = 0x8f,
+ DBG_BLOCK_ID_TCC0 = 0x90,
+ DBG_BLOCK_ID_TCC1 = 0x91,
+ DBG_BLOCK_ID_TCC2 = 0x92,
+ DBG_BLOCK_ID_TCC3 = 0x93,
+ DBG_BLOCK_ID_TCC4 = 0x94,
+ DBG_BLOCK_ID_TCC5 = 0x95,
+ DBG_BLOCK_ID_TCC6 = 0x96,
+ DBG_BLOCK_ID_TCC7 = 0x97,
+ DBG_BLOCK_ID_SPS00 = 0x98,
+ DBG_BLOCK_ID_SPS01 = 0x99,
+ DBG_BLOCK_ID_SPS02 = 0x9a,
+ DBG_BLOCK_ID_SPS10 = 0x9b,
+ DBG_BLOCK_ID_SPS11 = 0x9c,
+ DBG_BLOCK_ID_SPS12 = 0x9d,
+ DBG_BLOCK_ID_UNUSED33 = 0x9e,
+ DBG_BLOCK_ID_UNUSED34 = 0x9f,
+ DBG_BLOCK_ID_TA00 = 0xa0,
+ DBG_BLOCK_ID_TA01 = 0xa1,
+ DBG_BLOCK_ID_TA02 = 0xa2,
+ DBG_BLOCK_ID_TA03 = 0xa3,
+ DBG_BLOCK_ID_TA04 = 0xa4,
+ DBG_BLOCK_ID_TA05 = 0xa5,
+ DBG_BLOCK_ID_TA06 = 0xa6,
+ DBG_BLOCK_ID_TA07 = 0xa7,
+ DBG_BLOCK_ID_TA08 = 0xa8,
+ DBG_BLOCK_ID_TA09 = 0xa9,
+ DBG_BLOCK_ID_TA0A = 0xaa,
+ DBG_BLOCK_ID_TA0B = 0xab,
+ DBG_BLOCK_ID_UNUSED35 = 0xac,
+ DBG_BLOCK_ID_UNUSED36 = 0xad,
+ DBG_BLOCK_ID_UNUSED37 = 0xae,
+ DBG_BLOCK_ID_UNUSED38 = 0xaf,
+ DBG_BLOCK_ID_TA10 = 0xb0,
+ DBG_BLOCK_ID_TA11 = 0xb1,
+ DBG_BLOCK_ID_TA12 = 0xb2,
+ DBG_BLOCK_ID_TA13 = 0xb3,
+ DBG_BLOCK_ID_TA14 = 0xb4,
+ DBG_BLOCK_ID_TA15 = 0xb5,
+ DBG_BLOCK_ID_TA16 = 0xb6,
+ DBG_BLOCK_ID_TA17 = 0xb7,
+ DBG_BLOCK_ID_TA18 = 0xb8,
+ DBG_BLOCK_ID_TA19 = 0xb9,
+ DBG_BLOCK_ID_TA1A = 0xba,
+ DBG_BLOCK_ID_TA1B = 0xbb,
+ DBG_BLOCK_ID_UNUSED39 = 0xbc,
+ DBG_BLOCK_ID_UNUSED40 = 0xbd,
+ DBG_BLOCK_ID_UNUSED41 = 0xbe,
+ DBG_BLOCK_ID_UNUSED42 = 0xbf,
+ DBG_BLOCK_ID_TD00 = 0xc0,
+ DBG_BLOCK_ID_TD01 = 0xc1,
+ DBG_BLOCK_ID_TD02 = 0xc2,
+ DBG_BLOCK_ID_TD03 = 0xc3,
+ DBG_BLOCK_ID_TD04 = 0xc4,
+ DBG_BLOCK_ID_TD05 = 0xc5,
+ DBG_BLOCK_ID_TD06 = 0xc6,
+ DBG_BLOCK_ID_TD07 = 0xc7,
+ DBG_BLOCK_ID_TD08 = 0xc8,
+ DBG_BLOCK_ID_TD09 = 0xc9,
+ DBG_BLOCK_ID_TD0A = 0xca,
+ DBG_BLOCK_ID_TD0B = 0xcb,
+ DBG_BLOCK_ID_UNUSED43 = 0xcc,
+ DBG_BLOCK_ID_UNUSED44 = 0xcd,
+ DBG_BLOCK_ID_UNUSED45 = 0xce,
+ DBG_BLOCK_ID_UNUSED46 = 0xcf,
+ DBG_BLOCK_ID_TD10 = 0xd0,
+ DBG_BLOCK_ID_TD11 = 0xd1,
+ DBG_BLOCK_ID_TD12 = 0xd2,
+ DBG_BLOCK_ID_TD13 = 0xd3,
+ DBG_BLOCK_ID_TD14 = 0xd4,
+ DBG_BLOCK_ID_TD15 = 0xd5,
+ DBG_BLOCK_ID_TD16 = 0xd6,
+ DBG_BLOCK_ID_TD17 = 0xd7,
+ DBG_BLOCK_ID_TD18 = 0xd8,
+ DBG_BLOCK_ID_TD19 = 0xd9,
+ DBG_BLOCK_ID_TD1A = 0xda,
+ DBG_BLOCK_ID_TD1B = 0xdb,
+ DBG_BLOCK_ID_UNUSED47 = 0xdc,
+ DBG_BLOCK_ID_UNUSED48 = 0xdd,
+ DBG_BLOCK_ID_UNUSED49 = 0xde,
+ DBG_BLOCK_ID_UNUSED50 = 0xdf,
+ DBG_BLOCK_ID_MCD0 = 0xe0,
+ DBG_BLOCK_ID_MCD1 = 0xe1,
+ DBG_BLOCK_ID_MCD2 = 0xe2,
+ DBG_BLOCK_ID_MCD3 = 0xe3,
+ DBG_BLOCK_ID_MCD4 = 0xe4,
+ DBG_BLOCK_ID_MCD5 = 0xe5,
+ DBG_BLOCK_ID_UNUSED51 = 0xe6,
+ DBG_BLOCK_ID_UNUSED52 = 0xe7,
+} DebugBlockId_OLD;
+typedef enum DebugBlockId_BY2 {
+ DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
+ DBG_BLOCK_ID_VMC_BY2 = 0x1,
+ DBG_BLOCK_ID_CG_BY2 = 0x2,
+ DBG_BLOCK_ID_GRBM_BY2 = 0x3,
+ DBG_BLOCK_ID_CSC_BY2 = 0x4,
+ DBG_BLOCK_ID_IH_BY2 = 0x5,
+ DBG_BLOCK_ID_SQ_BY2 = 0x6,
+ DBG_BLOCK_ID_GMCON_BY2 = 0x7,
+ DBG_BLOCK_ID_DMA0_BY2 = 0x8,
+ DBG_BLOCK_ID_SPIM_BY2 = 0x9,
+ DBG_BLOCK_ID_SPIS_BY2 = 0xa,
+ DBG_BLOCK_ID_PA0_BY2 = 0xb,
+ DBG_BLOCK_ID_CP0_BY2 = 0xc,
+ DBG_BLOCK_ID_CP2_BY2 = 0xd,
+ DBG_BLOCK_ID_UVDU_BY2 = 0xe,
+ DBG_BLOCK_ID_VCE_BY2 = 0xf,
+ DBG_BLOCK_ID_VGT0_BY2 = 0x10,
+ DBG_BLOCK_ID_IA_BY2 = 0x11,
+ DBG_BLOCK_ID_SCT0_BY2 = 0x12,
+ DBG_BLOCK_ID_SPM0_BY2 = 0x13,
+ DBG_BLOCK_ID_TCAA_BY2 = 0x14,
+ DBG_BLOCK_ID_TCCA_BY2 = 0x15,
+ DBG_BLOCK_ID_MCC0_BY2 = 0x16,
+ DBG_BLOCK_ID_MCC2_BY2 = 0x17,
+ DBG_BLOCK_ID_SX0_BY2 = 0x18,
+ DBG_BLOCK_ID_SX2_BY2 = 0x19,
+ DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
+ DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
+ DBG_BLOCK_ID_PC0_BY2 = 0x1c,
+ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
+ DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
+ DBG_BLOCK_ID_MCB_BY2 = 0x1f,
+ DBG_BLOCK_ID_SCB0_BY2 = 0x20,
+ DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
+ DBG_BLOCK_ID_SCF0_BY2 = 0x22,
+ DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
+ DBG_BLOCK_ID_BCI0_BY2 = 0x24,
+ DBG_BLOCK_ID_BCI2_BY2 = 0x25,
+ DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
+ DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
+ DBG_BLOCK_ID_CB00_BY2 = 0x28,
+ DBG_BLOCK_ID_CB02_BY2 = 0x29,
+ DBG_BLOCK_ID_CB04_BY2 = 0x2a,
+ DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
+ DBG_BLOCK_ID_CB10_BY2 = 0x2c,
+ DBG_BLOCK_ID_CB12_BY2 = 0x2d,
+ DBG_BLOCK_ID_CB14_BY2 = 0x2e,
+ DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
+ DBG_BLOCK_ID_TCP0_BY2 = 0x30,
+ DBG_BLOCK_ID_TCP2_BY2 = 0x31,
+ DBG_BLOCK_ID_TCP4_BY2 = 0x32,
+ DBG_BLOCK_ID_TCP6_BY2 = 0x33,
+ DBG_BLOCK_ID_TCP8_BY2 = 0x34,
+ DBG_BLOCK_ID_TCP10_BY2 = 0x35,
+ DBG_BLOCK_ID_TCP12_BY2 = 0x36,
+ DBG_BLOCK_ID_TCP14_BY2 = 0x37,
+ DBG_BLOCK_ID_TCP16_BY2 = 0x38,
+ DBG_BLOCK_ID_TCP18_BY2 = 0x39,
+ DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
+ DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
+ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
+ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
+ DBG_BLOCK_ID_DB00_BY2 = 0x40,
+ DBG_BLOCK_ID_DB02_BY2 = 0x41,
+ DBG_BLOCK_ID_DB04_BY2 = 0x42,
+ DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
+ DBG_BLOCK_ID_DB10_BY2 = 0x44,
+ DBG_BLOCK_ID_DB12_BY2 = 0x45,
+ DBG_BLOCK_ID_DB14_BY2 = 0x46,
+ DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
+ DBG_BLOCK_ID_TCC0_BY2 = 0x48,
+ DBG_BLOCK_ID_TCC2_BY2 = 0x49,
+ DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
+ DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
+ DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
+ DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
+ DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
+ DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
+ DBG_BLOCK_ID_TA00_BY2 = 0x50,
+ DBG_BLOCK_ID_TA02_BY2 = 0x51,
+ DBG_BLOCK_ID_TA04_BY2 = 0x52,
+ DBG_BLOCK_ID_TA06_BY2 = 0x53,
+ DBG_BLOCK_ID_TA08_BY2 = 0x54,
+ DBG_BLOCK_ID_TA0A_BY2 = 0x55,
+ DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
+ DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
+ DBG_BLOCK_ID_TA10_BY2 = 0x58,
+ DBG_BLOCK_ID_TA12_BY2 = 0x59,
+ DBG_BLOCK_ID_TA14_BY2 = 0x5a,
+ DBG_BLOCK_ID_TA16_BY2 = 0x5b,
+ DBG_BLOCK_ID_TA18_BY2 = 0x5c,
+ DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
+ DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
+ DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
+ DBG_BLOCK_ID_TD00_BY2 = 0x60,
+ DBG_BLOCK_ID_TD02_BY2 = 0x61,
+ DBG_BLOCK_ID_TD04_BY2 = 0x62,
+ DBG_BLOCK_ID_TD06_BY2 = 0x63,
+ DBG_BLOCK_ID_TD08_BY2 = 0x64,
+ DBG_BLOCK_ID_TD0A_BY2 = 0x65,
+ DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
+ DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
+ DBG_BLOCK_ID_TD10_BY2 = 0x68,
+ DBG_BLOCK_ID_TD12_BY2 = 0x69,
+ DBG_BLOCK_ID_TD14_BY2 = 0x6a,
+ DBG_BLOCK_ID_TD16_BY2 = 0x6b,
+ DBG_BLOCK_ID_TD18_BY2 = 0x6c,
+ DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
+ DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
+ DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
+ DBG_BLOCK_ID_MCD0_BY2 = 0x70,
+ DBG_BLOCK_ID_MCD2_BY2 = 0x71,
+ DBG_BLOCK_ID_MCD4_BY2 = 0x72,
+ DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
+} DebugBlockId_BY2;
+typedef enum DebugBlockId_BY4 {
+ DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
+ DBG_BLOCK_ID_CG_BY4 = 0x1,
+ DBG_BLOCK_ID_CSC_BY4 = 0x2,
+ DBG_BLOCK_ID_SQ_BY4 = 0x3,
+ DBG_BLOCK_ID_DMA0_BY4 = 0x4,
+ DBG_BLOCK_ID_SPIS_BY4 = 0x5,
+ DBG_BLOCK_ID_CP0_BY4 = 0x6,
+ DBG_BLOCK_ID_UVDU_BY4 = 0x7,
+ DBG_BLOCK_ID_VGT0_BY4 = 0x8,
+ DBG_BLOCK_ID_SCT0_BY4 = 0x9,
+ DBG_BLOCK_ID_TCAA_BY4 = 0xa,
+ DBG_BLOCK_ID_MCC0_BY4 = 0xb,
+ DBG_BLOCK_ID_SX0_BY4 = 0xc,
+ DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
+ DBG_BLOCK_ID_PC0_BY4 = 0xe,
+ DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
+ DBG_BLOCK_ID_SCB0_BY4 = 0x10,
+ DBG_BLOCK_ID_SCF0_BY4 = 0x11,
+ DBG_BLOCK_ID_BCI0_BY4 = 0x12,
+ DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
+ DBG_BLOCK_ID_CB00_BY4 = 0x14,
+ DBG_BLOCK_ID_CB04_BY4 = 0x15,
+ DBG_BLOCK_ID_CB10_BY4 = 0x16,
+ DBG_BLOCK_ID_CB14_BY4 = 0x17,
+ DBG_BLOCK_ID_TCP0_BY4 = 0x18,
+ DBG_BLOCK_ID_TCP4_BY4 = 0x19,
+ DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
+ DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
+ DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
+ DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
+ DBG_BLOCK_ID_DB_BY4 = 0x20,
+ DBG_BLOCK_ID_DB04_BY4 = 0x21,
+ DBG_BLOCK_ID_DB10_BY4 = 0x22,
+ DBG_BLOCK_ID_DB14_BY4 = 0x23,
+ DBG_BLOCK_ID_TCC0_BY4 = 0x24,
+ DBG_BLOCK_ID_TCC4_BY4 = 0x25,
+ DBG_BLOCK_ID_SPS00_BY4 = 0x26,
+ DBG_BLOCK_ID_SPS11_BY4 = 0x27,
+ DBG_BLOCK_ID_TA00_BY4 = 0x28,
+ DBG_BLOCK_ID_TA04_BY4 = 0x29,
+ DBG_BLOCK_ID_TA08_BY4 = 0x2a,
+ DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
+ DBG_BLOCK_ID_TA10_BY4 = 0x2c,
+ DBG_BLOCK_ID_TA14_BY4 = 0x2d,
+ DBG_BLOCK_ID_TA18_BY4 = 0x2e,
+ DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
+ DBG_BLOCK_ID_TD00_BY4 = 0x30,
+ DBG_BLOCK_ID_TD04_BY4 = 0x31,
+ DBG_BLOCK_ID_TD08_BY4 = 0x32,
+ DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
+ DBG_BLOCK_ID_TD10_BY4 = 0x34,
+ DBG_BLOCK_ID_TD14_BY4 = 0x35,
+ DBG_BLOCK_ID_TD18_BY4 = 0x36,
+ DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
+ DBG_BLOCK_ID_MCD0_BY4 = 0x38,
+ DBG_BLOCK_ID_MCD4_BY4 = 0x39,
+} DebugBlockId_BY4;
+typedef enum DebugBlockId_BY8 {
+ DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
+ DBG_BLOCK_ID_CSC_BY8 = 0x1,
+ DBG_BLOCK_ID_DMA0_BY8 = 0x2,
+ DBG_BLOCK_ID_CP0_BY8 = 0x3,
+ DBG_BLOCK_ID_VGT0_BY8 = 0x4,
+ DBG_BLOCK_ID_TCAA_BY8 = 0x5,
+ DBG_BLOCK_ID_SX0_BY8 = 0x6,
+ DBG_BLOCK_ID_PC0_BY8 = 0x7,
+ DBG_BLOCK_ID_SCB0_BY8 = 0x8,
+ DBG_BLOCK_ID_BCI0_BY8 = 0x9,
+ DBG_BLOCK_ID_CB00_BY8 = 0xa,
+ DBG_BLOCK_ID_CB10_BY8 = 0xb,
+ DBG_BLOCK_ID_TCP0_BY8 = 0xc,
+ DBG_BLOCK_ID_TCP8_BY8 = 0xd,
+ DBG_BLOCK_ID_TCP16_BY8 = 0xe,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
+ DBG_BLOCK_ID_DB00_BY8 = 0x10,
+ DBG_BLOCK_ID_DB10_BY8 = 0x11,
+ DBG_BLOCK_ID_TCC0_BY8 = 0x12,
+ DBG_BLOCK_ID_SPS00_BY8 = 0x13,
+ DBG_BLOCK_ID_TA00_BY8 = 0x14,
+ DBG_BLOCK_ID_TA08_BY8 = 0x15,
+ DBG_BLOCK_ID_TA10_BY8 = 0x16,
+ DBG_BLOCK_ID_TA18_BY8 = 0x17,
+ DBG_BLOCK_ID_TD00_BY8 = 0x18,
+ DBG_BLOCK_ID_TD08_BY8 = 0x19,
+ DBG_BLOCK_ID_TD10_BY8 = 0x1a,
+ DBG_BLOCK_ID_TD18_BY8 = 0x1b,
+ DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
+} DebugBlockId_BY8;
+typedef enum DebugBlockId_BY16 {
+ DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
+ DBG_BLOCK_ID_DMA0_BY16 = 0x1,
+ DBG_BLOCK_ID_VGT0_BY16 = 0x2,
+ DBG_BLOCK_ID_SX0_BY16 = 0x3,
+ DBG_BLOCK_ID_SCB0_BY16 = 0x4,
+ DBG_BLOCK_ID_CB00_BY16 = 0x5,
+ DBG_BLOCK_ID_TCP0_BY16 = 0x6,
+ DBG_BLOCK_ID_TCP16_BY16 = 0x7,
+ DBG_BLOCK_ID_DB00_BY16 = 0x8,
+ DBG_BLOCK_ID_TCC0_BY16 = 0x9,
+ DBG_BLOCK_ID_TA00_BY16 = 0xa,
+ DBG_BLOCK_ID_TA10_BY16 = 0xb,
+ DBG_BLOCK_ID_TD00_BY16 = 0xc,
+ DBG_BLOCK_ID_TD10_BY16 = 0xd,
+ DBG_BLOCK_ID_MCD0_BY16 = 0xe,
+} DebugBlockId_BY16;
+typedef enum ColorTransform {
+ DCC_CT_AUTO = 0x0,
+ DCC_CT_NONE = 0x1,
+ ABGR_TO_A_BG_G_RB = 0x2,
+ BGRA_TO_BG_G_RB_A = 0x3,
+} ColorTransform;
+typedef enum CompareRef {
+ REF_NEVER = 0x0,
+ REF_LESS = 0x1,
+ REF_EQUAL = 0x2,
+ REF_LEQUAL = 0x3,
+ REF_GREATER = 0x4,
+ REF_NOTEQUAL = 0x5,
+ REF_GEQUAL = 0x6,
+ REF_ALWAYS = 0x7,
+} CompareRef;
+typedef enum ReadSize {
+ READ_256_BITS = 0x0,
+ READ_512_BITS = 0x1,
+} ReadSize;
+typedef enum DepthFormat {
+ DEPTH_INVALID = 0x0,
+ DEPTH_16 = 0x1,
+ DEPTH_X8_24 = 0x2,
+ DEPTH_8_24 = 0x3,
+ DEPTH_X8_24_FLOAT = 0x4,
+ DEPTH_8_24_FLOAT = 0x5,
+ DEPTH_32_FLOAT = 0x6,
+ DEPTH_X24_8_32_FLOAT = 0x7,
+} DepthFormat;
+typedef enum ZFormat {
+ Z_INVALID = 0x0,
+ Z_16 = 0x1,
+ Z_24 = 0x2,
+ Z_32_FLOAT = 0x3,
+} ZFormat;
+typedef enum StencilFormat {
+ STENCIL_INVALID = 0x0,
+ STENCIL_8 = 0x1,
+} StencilFormat;
+typedef enum CmaskMode {
+ CMASK_CLEAR_NONE = 0x0,
+ CMASK_CLEAR_ONE = 0x1,
+ CMASK_CLEAR_ALL = 0x2,
+ CMASK_ANY_EXPANDED = 0x3,
+ CMASK_ALPHA0_FRAG1 = 0x4,
+ CMASK_ALPHA0_FRAG2 = 0x5,
+ CMASK_ALPHA0_FRAG4 = 0x6,
+ CMASK_ALPHA0_FRAGS = 0x7,
+ CMASK_ALPHA1_FRAG1 = 0x8,
+ CMASK_ALPHA1_FRAG2 = 0x9,
+ CMASK_ALPHA1_FRAG4 = 0xa,
+ CMASK_ALPHA1_FRAGS = 0xb,
+ CMASK_ALPHAX_FRAG1 = 0xc,
+ CMASK_ALPHAX_FRAG2 = 0xd,
+ CMASK_ALPHAX_FRAG4 = 0xe,
+ CMASK_ALPHAX_FRAGS = 0xf,
+} CmaskMode;
+typedef enum QuadExportFormat {
+ EXPORT_UNUSED = 0x0,
+ EXPORT_32_R = 0x1,
+ EXPORT_32_GR = 0x2,
+ EXPORT_32_AR = 0x3,
+ EXPORT_FP16_ABGR = 0x4,
+ EXPORT_UNSIGNED16_ABGR = 0x5,
+ EXPORT_SIGNED16_ABGR = 0x6,
+ EXPORT_32_ABGR = 0x7,
+} QuadExportFormat;
+typedef enum QuadExportFormatOld {
+ EXPORT_4P_32BPC_ABGR = 0x0,
+ EXPORT_4P_16BPC_ABGR = 0x1,
+ EXPORT_4P_32BPC_GR = 0x2,
+ EXPORT_4P_32BPC_AR = 0x3,
+ EXPORT_2P_32BPC_ABGR = 0x4,
+ EXPORT_8P_32BPC_R = 0x5,
+} QuadExportFormatOld;
+typedef enum ColorFormat {
+ COLOR_INVALID = 0x0,
+ COLOR_8 = 0x1,
+ COLOR_16 = 0x2,
+ COLOR_8_8 = 0x3,
+ COLOR_32 = 0x4,
+ COLOR_16_16 = 0x5,
+ COLOR_10_11_11 = 0x6,
+ COLOR_11_11_10 = 0x7,
+ COLOR_10_10_10_2 = 0x8,
+ COLOR_2_10_10_10 = 0x9,
+ COLOR_8_8_8_8 = 0xa,
+ COLOR_32_32 = 0xb,
+ COLOR_16_16_16_16 = 0xc,
+ COLOR_RESERVED_13 = 0xd,
+ COLOR_32_32_32_32 = 0xe,
+ COLOR_RESERVED_15 = 0xf,
+ COLOR_5_6_5 = 0x10,
+ COLOR_1_5_5_5 = 0x11,
+ COLOR_5_5_5_1 = 0x12,
+ COLOR_4_4_4_4 = 0x13,
+ COLOR_8_24 = 0x14,
+ COLOR_24_8 = 0x15,
+ COLOR_X24_8_32_FLOAT = 0x16,
+ COLOR_RESERVED_23 = 0x17,
+} ColorFormat;
+typedef enum SurfaceFormat {
+ FMT_INVALID = 0x0,
+ FMT_8 = 0x1,
+ FMT_16 = 0x2,
+ FMT_8_8 = 0x3,
+ FMT_32 = 0x4,
+ FMT_16_16 = 0x5,
+ FMT_10_11_11 = 0x6,
+ FMT_11_11_10 = 0x7,
+ FMT_10_10_10_2 = 0x8,
+ FMT_2_10_10_10 = 0x9,
+ FMT_8_8_8_8 = 0xa,
+ FMT_32_32 = 0xb,
+ FMT_16_16_16_16 = 0xc,
+ FMT_32_32_32 = 0xd,
+ FMT_32_32_32_32 = 0xe,
+ FMT_RESERVED_4 = 0xf,
+ FMT_5_6_5 = 0x10,
+ FMT_1_5_5_5 = 0x11,
+ FMT_5_5_5_1 = 0x12,
+ FMT_4_4_4_4 = 0x13,
+ FMT_8_24 = 0x14,
+ FMT_24_8 = 0x15,
+ FMT_X24_8_32_FLOAT = 0x16,
+ FMT_RESERVED_33 = 0x17,
+ FMT_11_11_10_FLOAT = 0x18,
+ FMT_16_FLOAT = 0x19,
+ FMT_32_FLOAT = 0x1a,
+ FMT_16_16_FLOAT = 0x1b,
+ FMT_8_24_FLOAT = 0x1c,
+ FMT_24_8_FLOAT = 0x1d,
+ FMT_32_32_FLOAT = 0x1e,
+ FMT_10_11_11_FLOAT = 0x1f,
+ FMT_16_16_16_16_FLOAT = 0x20,
+ FMT_3_3_2 = 0x21,
+ FMT_6_5_5 = 0x22,
+ FMT_32_32_32_32_FLOAT = 0x23,
+ FMT_RESERVED_36 = 0x24,
+ FMT_1 = 0x25,
+ FMT_1_REVERSED = 0x26,
+ FMT_GB_GR = 0x27,
+ FMT_BG_RG = 0x28,
+ FMT_32_AS_8 = 0x29,
+ FMT_32_AS_8_8 = 0x2a,
+ FMT_5_9_9_9_SHAREDEXP = 0x2b,
+ FMT_8_8_8 = 0x2c,
+ FMT_16_16_16 = 0x2d,
+ FMT_16_16_16_FLOAT = 0x2e,
+ FMT_4_4 = 0x2f,
+ FMT_32_32_32_FLOAT = 0x30,
+ FMT_BC1 = 0x31,
+ FMT_BC2 = 0x32,
+ FMT_BC3 = 0x33,
+ FMT_BC4 = 0x34,
+ FMT_BC5 = 0x35,
+ FMT_BC6 = 0x36,
+ FMT_BC7 = 0x37,
+ FMT_32_AS_32_32_32_32 = 0x38,
+ FMT_APC3 = 0x39,
+ FMT_APC4 = 0x3a,
+ FMT_APC5 = 0x3b,
+ FMT_APC6 = 0x3c,
+ FMT_APC7 = 0x3d,
+ FMT_CTX1 = 0x3e,
+ FMT_RESERVED_63 = 0x3f,
+} SurfaceFormat;
+typedef enum BUF_DATA_FORMAT {
+ BUF_DATA_FORMAT_INVALID = 0x0,
+ BUF_DATA_FORMAT_8 = 0x1,
+ BUF_DATA_FORMAT_16 = 0x2,
+ BUF_DATA_FORMAT_8_8 = 0x3,
+ BUF_DATA_FORMAT_32 = 0x4,
+ BUF_DATA_FORMAT_16_16 = 0x5,
+ BUF_DATA_FORMAT_10_11_11 = 0x6,
+ BUF_DATA_FORMAT_11_11_10 = 0x7,
+ BUF_DATA_FORMAT_10_10_10_2 = 0x8,
+ BUF_DATA_FORMAT_2_10_10_10 = 0x9,
+ BUF_DATA_FORMAT_8_8_8_8 = 0xa,
+ BUF_DATA_FORMAT_32_32 = 0xb,
+ BUF_DATA_FORMAT_16_16_16_16 = 0xc,
+ BUF_DATA_FORMAT_32_32_32 = 0xd,
+ BUF_DATA_FORMAT_32_32_32_32 = 0xe,
+ BUF_DATA_FORMAT_RESERVED_15 = 0xf,
+} BUF_DATA_FORMAT;
+typedef enum IMG_DATA_FORMAT {
+ IMG_DATA_FORMAT_INVALID = 0x0,
+ IMG_DATA_FORMAT_8 = 0x1,
+ IMG_DATA_FORMAT_16 = 0x2,
+ IMG_DATA_FORMAT_8_8 = 0x3,
+ IMG_DATA_FORMAT_32 = 0x4,
+ IMG_DATA_FORMAT_16_16 = 0x5,
+ IMG_DATA_FORMAT_10_11_11 = 0x6,
+ IMG_DATA_FORMAT_11_11_10 = 0x7,
+ IMG_DATA_FORMAT_10_10_10_2 = 0x8,
+ IMG_DATA_FORMAT_2_10_10_10 = 0x9,
+ IMG_DATA_FORMAT_8_8_8_8 = 0xa,
+ IMG_DATA_FORMAT_32_32 = 0xb,
+ IMG_DATA_FORMAT_16_16_16_16 = 0xc,
+ IMG_DATA_FORMAT_32_32_32 = 0xd,
+ IMG_DATA_FORMAT_32_32_32_32 = 0xe,
+ IMG_DATA_FORMAT_RESERVED_15 = 0xf,
+ IMG_DATA_FORMAT_5_6_5 = 0x10,
+ IMG_DATA_FORMAT_1_5_5_5 = 0x11,
+ IMG_DATA_FORMAT_5_5_5_1 = 0x12,
+ IMG_DATA_FORMAT_4_4_4_4 = 0x13,
+ IMG_DATA_FORMAT_8_24 = 0x14,
+ IMG_DATA_FORMAT_24_8 = 0x15,
+ IMG_DATA_FORMAT_X24_8_32 = 0x16,
+ IMG_DATA_FORMAT_RESERVED_23 = 0x17,
+ IMG_DATA_FORMAT_RESERVED_24 = 0x18,
+ IMG_DATA_FORMAT_RESERVED_25 = 0x19,
+ IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
+ IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
+ IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
+ IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
+ IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
+ IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
+ IMG_DATA_FORMAT_GB_GR = 0x20,
+ IMG_DATA_FORMAT_BG_RG = 0x21,
+ IMG_DATA_FORMAT_5_9_9_9 = 0x22,
+ IMG_DATA_FORMAT_BC1 = 0x23,
+ IMG_DATA_FORMAT_BC2 = 0x24,
+ IMG_DATA_FORMAT_BC3 = 0x25,
+ IMG_DATA_FORMAT_BC4 = 0x26,
+ IMG_DATA_FORMAT_BC5 = 0x27,
+ IMG_DATA_FORMAT_BC6 = 0x28,
+ IMG_DATA_FORMAT_BC7 = 0x29,
+ IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
+ IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
+ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
+ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
+ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
+ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
+ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
+ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
+ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
+ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
+ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
+ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
+ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
+ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
+ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
+ IMG_DATA_FORMAT_4_4 = 0x39,
+ IMG_DATA_FORMAT_6_5_5 = 0x3a,
+ IMG_DATA_FORMAT_1 = 0x3b,
+ IMG_DATA_FORMAT_1_REVERSED = 0x3c,
+ IMG_DATA_FORMAT_32_AS_8 = 0x3d,
+ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
+ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
+} IMG_DATA_FORMAT;
+typedef enum BUF_NUM_FORMAT {
+ BUF_NUM_FORMAT_UNORM = 0x0,
+ BUF_NUM_FORMAT_SNORM = 0x1,
+ BUF_NUM_FORMAT_USCALED = 0x2,
+ BUF_NUM_FORMAT_SSCALED = 0x3,
+ BUF_NUM_FORMAT_UINT = 0x4,
+ BUF_NUM_FORMAT_SINT = 0x5,
+ BUF_NUM_FORMAT_RESERVED_6 = 0x6,
+ BUF_NUM_FORMAT_FLOAT = 0x7,
+} BUF_NUM_FORMAT;
+typedef enum IMG_NUM_FORMAT {
+ IMG_NUM_FORMAT_UNORM = 0x0,
+ IMG_NUM_FORMAT_SNORM = 0x1,
+ IMG_NUM_FORMAT_USCALED = 0x2,
+ IMG_NUM_FORMAT_SSCALED = 0x3,
+ IMG_NUM_FORMAT_UINT = 0x4,
+ IMG_NUM_FORMAT_SINT = 0x5,
+ IMG_NUM_FORMAT_RESERVED_6 = 0x6,
+ IMG_NUM_FORMAT_FLOAT = 0x7,
+ IMG_NUM_FORMAT_RESERVED_8 = 0x8,
+ IMG_NUM_FORMAT_SRGB = 0x9,
+ IMG_NUM_FORMAT_RESERVED_10 = 0xa,
+ IMG_NUM_FORMAT_RESERVED_11 = 0xb,
+ IMG_NUM_FORMAT_RESERVED_12 = 0xc,
+ IMG_NUM_FORMAT_RESERVED_13 = 0xd,
+ IMG_NUM_FORMAT_RESERVED_14 = 0xe,
+ IMG_NUM_FORMAT_RESERVED_15 = 0xf,
+} IMG_NUM_FORMAT;
+typedef enum TileType {
+ ARRAY_COLOR_TILE = 0x0,
+ ARRAY_DEPTH_TILE = 0x1,
+} TileType;
+typedef enum NonDispTilingOrder {
+ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
+ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
+} NonDispTilingOrder;
+typedef enum MicroTileMode {
+ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
+ ADDR_SURF_THIN_MICRO_TILING = 0x1,
+ ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
+ ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
+ ADDR_SURF_THICK_MICRO_TILING = 0x4,
+} MicroTileMode;
+typedef enum TileSplit {
+ ADDR_SURF_TILE_SPLIT_64B = 0x0,
+ ADDR_SURF_TILE_SPLIT_128B = 0x1,
+ ADDR_SURF_TILE_SPLIT_256B = 0x2,
+ ADDR_SURF_TILE_SPLIT_512B = 0x3,
+ ADDR_SURF_TILE_SPLIT_1KB = 0x4,
+ ADDR_SURF_TILE_SPLIT_2KB = 0x5,
+ ADDR_SURF_TILE_SPLIT_4KB = 0x6,
+} TileSplit;
+typedef enum SampleSplit {
+ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
+ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
+ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
+ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
+} SampleSplit;
+typedef enum PipeConfig {
+ ADDR_SURF_P2 = 0x0,
+ ADDR_SURF_P2_RESERVED0 = 0x1,
+ ADDR_SURF_P2_RESERVED1 = 0x2,
+ ADDR_SURF_P2_RESERVED2 = 0x3,
+ ADDR_SURF_P4_8x16 = 0x4,
+ ADDR_SURF_P4_16x16 = 0x5,
+ ADDR_SURF_P4_16x32 = 0x6,
+ ADDR_SURF_P4_32x32 = 0x7,
+ ADDR_SURF_P8_16x16_8x16 = 0x8,
+ ADDR_SURF_P8_16x32_8x16 = 0x9,
+ ADDR_SURF_P8_32x32_8x16 = 0xa,
+ ADDR_SURF_P8_16x32_16x16 = 0xb,
+ ADDR_SURF_P8_32x32_16x16 = 0xc,
+ ADDR_SURF_P8_32x32_16x32 = 0xd,
+ ADDR_SURF_P8_32x64_32x32 = 0xe,
+ ADDR_SURF_P8_RESERVED0 = 0xf,
+ ADDR_SURF_P16_32x32_8x16 = 0x10,
+ ADDR_SURF_P16_32x32_16x16 = 0x11,
+} PipeConfig;
+typedef enum NumBanks {
+ ADDR_SURF_2_BANK = 0x0,
+ ADDR_SURF_4_BANK = 0x1,
+ ADDR_SURF_8_BANK = 0x2,
+ ADDR_SURF_16_BANK = 0x3,
+} NumBanks;
+typedef enum BankWidth {
+ ADDR_SURF_BANK_WIDTH_1 = 0x0,
+ ADDR_SURF_BANK_WIDTH_2 = 0x1,
+ ADDR_SURF_BANK_WIDTH_4 = 0x2,
+ ADDR_SURF_BANK_WIDTH_8 = 0x3,
+} BankWidth;
+typedef enum BankHeight {
+ ADDR_SURF_BANK_HEIGHT_1 = 0x0,
+ ADDR_SURF_BANK_HEIGHT_2 = 0x1,
+ ADDR_SURF_BANK_HEIGHT_4 = 0x2,
+ ADDR_SURF_BANK_HEIGHT_8 = 0x3,
+} BankHeight;
+typedef enum BankWidthHeight {
+ ADDR_SURF_BANK_WH_1 = 0x0,
+ ADDR_SURF_BANK_WH_2 = 0x1,
+ ADDR_SURF_BANK_WH_4 = 0x2,
+ ADDR_SURF_BANK_WH_8 = 0x3,
+} BankWidthHeight;
+typedef enum MacroTileAspect {
+ ADDR_SURF_MACRO_ASPECT_1 = 0x0,
+ ADDR_SURF_MACRO_ASPECT_2 = 0x1,
+ ADDR_SURF_MACRO_ASPECT_4 = 0x2,
+ ADDR_SURF_MACRO_ASPECT_8 = 0x3,
+} MacroTileAspect;
+typedef enum GATCL1RequestType {
+ GATCL1_TYPE_NORMAL = 0x0,
+ GATCL1_TYPE_SHOOTDOWN = 0x1,
+ GATCL1_TYPE_BYPASS = 0x2,
+} GATCL1RequestType;
+typedef enum TCC_CACHE_POLICIES {
+ TCC_CACHE_POLICY_LRU = 0x0,
+ TCC_CACHE_POLICY_STREAM = 0x1,
+} TCC_CACHE_POLICIES;
+typedef enum MTYPE {
+ MTYPE_NC_NV = 0x0,
+ MTYPE_NC = 0x1,
+ MTYPE_CC = 0x2,
+ MTYPE_UC = 0x3,
+} MTYPE;
+typedef enum PERFMON_COUNTER_MODE {
+ PERFMON_COUNTER_MODE_ACCUM = 0x0,
+ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
+ PERFMON_COUNTER_MODE_MAX = 0x2,
+ PERFMON_COUNTER_MODE_DIRTY = 0x3,
+ PERFMON_COUNTER_MODE_SAMPLE = 0x4,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
+ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
+ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
+ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
+ PERFMON_COUNTER_MODE_RESERVED = 0xf,
+} PERFMON_COUNTER_MODE;
+typedef enum PERFMON_SPM_MODE {
+ PERFMON_SPM_MODE_OFF = 0x0,
+ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
+ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
+ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
+ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
+ PERFMON_SPM_MODE_RESERVED_5 = 0x5,
+ PERFMON_SPM_MODE_RESERVED_6 = 0x6,
+ PERFMON_SPM_MODE_RESERVED_7 = 0x7,
+ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
+ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
+ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
+} PERFMON_SPM_MODE;
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0x0,
+ ARRAY_TILED = 0x1,
+} SurfaceTiling;
+typedef enum SurfaceArray {
+ ARRAY_1D = 0x0,
+ ARRAY_2D = 0x1,
+ ARRAY_3D = 0x2,
+ ARRAY_3D_SLICE = 0x3,
+} SurfaceArray;
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0x0,
+ ARRAY_2D_COLOR = 0x1,
+ ARRAY_3D_SLICE_COLOR = 0x3,
+} ColorArray;
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0x0,
+ ARRAY_2D_DEPTH = 0x1,
+} DepthArray;
+typedef enum ENUM_NUM_SIMD_PER_CU {
+ NUM_SIMD_PER_CU = 0x4,
+} ENUM_NUM_SIMD_PER_CU;
+typedef enum MEM_PWR_FORCE_CTRL {
+ NO_FORCE_REQUEST = 0x0,
+ FORCE_LIGHT_SLEEP_REQUEST = 0x1,
+ FORCE_DEEP_SLEEP_REQUEST = 0x2,
+ FORCE_SHUT_DOWN_REQUEST = 0x3,
+} MEM_PWR_FORCE_CTRL;
+typedef enum MEM_PWR_FORCE_CTRL2 {
+ NO_FORCE_REQ = 0x0,
+ FORCE_LIGHT_SLEEP_REQ = 0x1,
+} MEM_PWR_FORCE_CTRL2;
+typedef enum MEM_PWR_DIS_CTRL {
+ ENABLE_MEM_PWR_CTRL = 0x0,
+ DISABLE_MEM_PWR_CTRL = 0x1,
+} MEM_PWR_DIS_CTRL;
+typedef enum MEM_PWR_SEL_CTRL {
+ DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
+ DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
+ DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
+} MEM_PWR_SEL_CTRL;
+typedef enum MEM_PWR_SEL_CTRL2 {
+ DYNAMIC_DEEP_SLEEP_EN = 0x0,
+ DYNAMIC_LIGHT_SLEEP_EN = 0x1,
+} MEM_PWR_SEL_CTRL2;
+
+#endif /* UVD_5_0_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h
new file mode 100644
index 000000000000..64749b72a0a6
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h
@@ -0,0 +1,1046 @@
+/*
+ * UVD_5_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef UVD_5_0_SH_MASK_H
+#define UVD_5_0_SH_MASK_H
+
+#define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
+#define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
+#define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
+#define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
+#define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
+#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
+#define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
+#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
+#define UVD_SEMA_CMD__MODE_MASK 0x40
+#define UVD_SEMA_CMD__MODE__SHIFT 0x6
+#define UVD_SEMA_CMD__VMID_EN_MASK 0x80
+#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7
+#define UVD_SEMA_CMD__VMID_MASK 0xf00
+#define UVD_SEMA_CMD__VMID__SHIFT 0x8
+#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1
+#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0
+#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffe
+#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1
+#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000
+#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f
+#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff
+#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0
+#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffff
+#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0
+#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1
+#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0
+#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2
+#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1
+#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff
+#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff
+#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff
+#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff
+#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff
+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff
+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1
+#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0
+#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2
+#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1
+#define UVD_LMI_EXT40_ADDR__ADDR_MASK 0xff
+#define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x0
+#define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x1f0000
+#define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x10
+#define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000
+#define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x1f
+#define UVD_CTX_INDEX__INDEX_MASK 0x1ff
+#define UVD_CTX_INDEX__INDEX__SHIFT 0x0
+#define UVD_CTX_DATA__DATA_MASK 0xffffffff
+#define UVD_CTX_DATA__DATA__SHIFT 0x0
+#define UVD_CGC_GATE__SYS_MASK 0x1
+#define UVD_CGC_GATE__SYS__SHIFT 0x0
+#define UVD_CGC_GATE__UDEC_MASK 0x2
+#define UVD_CGC_GATE__UDEC__SHIFT 0x1
+#define UVD_CGC_GATE__MPEG2_MASK 0x4
+#define UVD_CGC_GATE__MPEG2__SHIFT 0x2
+#define UVD_CGC_GATE__REGS_MASK 0x8
+#define UVD_CGC_GATE__REGS__SHIFT 0x3
+#define UVD_CGC_GATE__RBC_MASK 0x10
+#define UVD_CGC_GATE__RBC__SHIFT 0x4
+#define UVD_CGC_GATE__LMI_MC_MASK 0x20
+#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5
+#define UVD_CGC_GATE__LMI_UMC_MASK 0x40
+#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6
+#define UVD_CGC_GATE__IDCT_MASK 0x80
+#define UVD_CGC_GATE__IDCT__SHIFT 0x7
+#define UVD_CGC_GATE__MPRD_MASK 0x100
+#define UVD_CGC_GATE__MPRD__SHIFT 0x8
+#define UVD_CGC_GATE__MPC_MASK 0x200
+#define UVD_CGC_GATE__MPC__SHIFT 0x9
+#define UVD_CGC_GATE__LBSI_MASK 0x400
+#define UVD_CGC_GATE__LBSI__SHIFT 0xa
+#define UVD_CGC_GATE__LRBBM_MASK 0x800
+#define UVD_CGC_GATE__LRBBM__SHIFT 0xb
+#define UVD_CGC_GATE__UDEC_RE_MASK 0x1000
+#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc
+#define UVD_CGC_GATE__UDEC_CM_MASK 0x2000
+#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd
+#define UVD_CGC_GATE__UDEC_IT_MASK 0x4000
+#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe
+#define UVD_CGC_GATE__UDEC_DB_MASK 0x8000
+#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf
+#define UVD_CGC_GATE__UDEC_MP_MASK 0x10000
+#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10
+#define UVD_CGC_GATE__WCB_MASK 0x20000
+#define UVD_CGC_GATE__WCB__SHIFT 0x11
+#define UVD_CGC_GATE__VCPU_MASK 0x40000
+#define UVD_CGC_GATE__VCPU__SHIFT 0x12
+#define UVD_CGC_GATE__SCPU_MASK 0x80000
+#define UVD_CGC_GATE__SCPU__SHIFT 0x13
+#define UVD_CGC_GATE__JPEG_MASK 0x100000
+#define UVD_CGC_GATE__JPEG__SHIFT 0x14
+#define UVD_CGC_GATE__JPEG2_MASK 0x200000
+#define UVD_CGC_GATE__JPEG2__SHIFT 0x15
+#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1
+#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0
+#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2
+#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1
+#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x4
+#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2
+#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x8
+#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3
+#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10
+#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4
+#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x20
+#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5
+#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40
+#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6
+#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x80
+#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7
+#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100
+#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8
+#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200
+#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9
+#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400
+#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa
+#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800
+#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb
+#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000
+#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc
+#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x2000
+#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd
+#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x4000
+#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe
+#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x8000
+#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf
+#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x10000
+#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10
+#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000
+#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11
+#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000
+#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12
+#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000
+#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13
+#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000
+#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
+#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x200000
+#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15
+#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x400000
+#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16
+#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000
+#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17
+#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000
+#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18
+#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x2000000
+#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19
+#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x4000000
+#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a
+#define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x8000000
+#define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b
+#define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000
+#define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c
+#define UVD_CGC_STATUS__JPEG_ACTIVE_MASK 0x40000000
+#define UVD_CGC_STATUS__JPEG_ACTIVE__SHIFT 0x1e
+#define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000
+#define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f
+#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1
+#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
+#define UVD_CGC_CTRL__JPEG2_MODE_MASK 0x2
+#define UVD_CGC_CTRL__JPEG2_MODE__SHIFT 0x1
+#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c
+#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2
+#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0
+#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6
+#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800
+#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb
+#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000
+#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc
+#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000
+#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
+#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000
+#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe
+#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000
+#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf
+#define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000
+#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
+#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000
+#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11
+#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000
+#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12
+#define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000
+#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13
+#define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000
+#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14
+#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000
+#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15
+#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000
+#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16
+#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000
+#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17
+#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000
+#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18
+#define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000
+#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19
+#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000
+#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a
+#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000
+#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b
+#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000
+#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c
+#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000
+#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d
+#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000
+#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e
+#define UVD_CGC_CTRL__JPEG_MODE_MASK 0x80000000
+#define UVD_CGC_CTRL__JPEG_MODE__SHIFT 0x1f
+#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x1
+#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0
+#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2
+#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1
+#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x4
+#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2
+#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8
+#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3
+#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10
+#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4
+#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20
+#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5
+#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x40
+#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6
+#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80
+#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7
+#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100
+#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8
+#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200
+#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9
+#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x400
+#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa
+#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800
+#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb
+#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000
+#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc
+#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000
+#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd
+#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000
+#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe
+#define UVD_CGC_UDEC_STATUS__JPEG_VCLK_MASK 0x8000
+#define UVD_CGC_UDEC_STATUS__JPEG_VCLK__SHIFT 0xf
+#define UVD_CGC_UDEC_STATUS__JPEG_SCLK_MASK 0x10000
+#define UVD_CGC_UDEC_STATUS__JPEG_SCLK__SHIFT 0x10
+#define UVD_CGC_UDEC_STATUS__JPEG2_VCLK_MASK 0x20000
+#define UVD_CGC_UDEC_STATUS__JPEG2_VCLK__SHIFT 0x11
+#define UVD_CGC_UDEC_STATUS__JPEG2_SCLK_MASK 0x40000
+#define UVD_CGC_UDEC_STATUS__JPEG2_SCLK__SHIFT 0x12
+#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x1
+#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0
+#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2
+#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1
+#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x4
+#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2
+#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x8
+#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3
+#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x70
+#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x4
+#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x80
+#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7
+#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100
+#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
+#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x600
+#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9
+#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x1800
+#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb
+#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x2000
+#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd
+#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x4000
+#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe
+#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000
+#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf
+#define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x10000
+#define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10
+#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x1fe0000
+#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11
+#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x1
+#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0
+#define UVD_MASTINT_EN__VCPU_EN_MASK 0x2
+#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1
+#define UVD_MASTINT_EN__SYS_EN_MASK 0x4
+#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2
+#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x7ffff0
+#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4
+#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0xf
+#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x0
+#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0xf0
+#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x4
+#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0xf00
+#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x8
+#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0xf000
+#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0xc
+#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0xf0000
+#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x10
+#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0xf00000
+#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14
+#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0xf000000
+#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x18
+#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000
+#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x1c
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0xff
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8
+#define UVD_LMI_CTRL__REQ_MODE_MASK 0x200
+#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9
+#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800
+#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb
+#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000
+#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc
+#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x2000
+#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd
+#define UVD_LMI_CTRL__CRC_RESET_MASK 0x4000
+#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe
+#define UVD_LMI_CTRL__CRC_SEL_MASK 0xf8000
+#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf
+#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x100000
+#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14
+#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000
+#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15
+#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x400000
+#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16
+#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x800000
+#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17
+#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x1000000
+#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18
+#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x2000000
+#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19
+#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x4000000
+#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a
+#define UVD_LMI_CTRL__RFU_MASK 0xf8000000
+#define UVD_LMI_CTRL__RFU__SHIFT 0x1b
+#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x1
+#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0
+#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2
+#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1
+#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4
+#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2
+#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x8
+#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3
+#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x10
+#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4
+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x20
+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5
+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x40
+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6
+#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x80
+#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7
+#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100
+#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8
+#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200
+#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9
+#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x400
+#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa
+#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800
+#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb
+#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000
+#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc
+#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x2000
+#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd
+#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x3
+#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
+#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0xc
+#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
+#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x30
+#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4
+#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0xc0
+#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6
+#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x300
+#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8
+#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0xc00
+#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa
+#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x3000
+#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc
+#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0xc000
+#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe
+#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x30000
+#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10
+#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0xc0000
+#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12
+#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0xc00000
+#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16
+#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x3000000
+#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18
+#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0xc000000
+#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a
+#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000
+#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c
+#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000
+#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e
+#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x3
+#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0
+#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0xc
+#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2
+#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x30
+#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4
+#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0xc0
+#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6
+#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x300
+#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8
+#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0xc00
+#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa
+#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x3000
+#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc
+#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0xc000
+#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe
+#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x30000
+#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10
+#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0xc0000
+#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12
+#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x300000
+#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14
+#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0xc00000
+#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16
+#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x3000000
+#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18
+#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0xc000000
+#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a
+#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000
+#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c
+#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000
+#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e
+#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38
+#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3
+#define UVD_MPC_CNTL__PERF_RST_MASK 0x40
+#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6
+#define UVD_MPC_CNTL__DBG_MUX_MASK 0xf00
+#define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x8
+#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x30000
+#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10
+#define UVD_MPC_CNTL__URGENT_EN_MASK 0x40000
+#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12
+#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f
+#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0
+#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0
+#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6
+#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000
+#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc
+#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000
+#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12
+#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000
+#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18
+#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f
+#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0
+#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0
+#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6
+#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000
+#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc
+#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x3f
+#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0
+#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0
+#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6
+#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x3f000
+#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc
+#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0xfc0000
+#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12
+#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000
+#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18
+#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f
+#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0
+#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0xfc0
+#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6
+#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000
+#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc
+#define UVD_MPC_SET_MUX__SET_0_MASK 0x7
+#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0
+#define UVD_MPC_SET_MUX__SET_1_MASK 0x38
+#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3
+#define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0
+#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6
+#define UVD_MPC_SET_ALU__FUNCT_MASK 0x7
+#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0
+#define UVD_MPC_SET_ALU__OPERAND_MASK 0xff0
+#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4
+#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff
+#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff
+#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff
+#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff
+#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x1ffffff
+#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x1fffff
+#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0
+#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0xf
+#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0
+#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x10
+#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4
+#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x20
+#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5
+#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x40
+#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6
+#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x80
+#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7
+#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100
+#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8
+#define UVD_VCPU_CNTL__CLK_EN_MASK 0x200
+#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9
+#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x400
+#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa
+#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800
+#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb
+#define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000
+#define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd
+#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x10000
+#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10
+#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x20000
+#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11
+#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x40000
+#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12
+#define UVD_VCPU_CNTL__SUVD_EN_MASK 0x80000
+#define UVD_VCPU_CNTL__SUVD_EN__SHIFT 0x13
+#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0xff00000
+#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14
+#define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000
+#define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c
+#define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000
+#define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e
+#define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000
+#define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f
+#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x1
+#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0
+#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2
+#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1
+#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x4
+#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2
+#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x8
+#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3
+#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x10
+#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4
+#define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x20
+#define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5
+#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x40
+#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6
+#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x80
+#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7
+#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100
+#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8
+#define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS_MASK 0x200
+#define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS__SHIFT 0x9
+#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x400
+#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa
+#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800
+#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb
+#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000
+#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc
+#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x2000
+#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd
+#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x4000
+#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe
+#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x8000
+#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf
+#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x10000
+#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10
+#define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x20000
+#define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11
+#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x40000
+#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12
+#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x80000
+#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13
+#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x100000
+#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14
+#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x200000
+#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15
+#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x400000
+#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16
+#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x800000
+#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17
+#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x1000000
+#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18
+#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x2000000
+#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19
+#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x4000000
+#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a
+#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x8000000
+#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b
+#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000
+#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c
+#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000
+#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d
+#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000
+#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e
+#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000
+#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f
+#define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0xf
+#define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0
+#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x7ffff0
+#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4
+#define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0xf
+#define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0
+#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x7ffff0
+#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4
+#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x7ffff0
+#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4
+#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x1f
+#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0
+#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x1f00
+#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8
+#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000
+#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10
+#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x100000
+#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14
+#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x1000000
+#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18
+#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000
+#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c
+#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffff
+#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0
+#define UVD_STATUS__RBC_BUSY_MASK 0x1
+#define UVD_STATUS__RBC_BUSY__SHIFT 0x0
+#define UVD_STATUS__VCPU_REPORT_MASK 0xfe
+#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x1
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x4
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x8
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x1
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x1ffffe
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x1
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x1ffffe
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x1
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x1ffffe
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
+#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffff
+#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0
+#define UVD_SUVD_CGC_GATE__SRE_MASK 0x1
+#define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0
+#define UVD_SUVD_CGC_GATE__SIT_MASK 0x2
+#define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1
+#define UVD_SUVD_CGC_GATE__SMP_MASK 0x4
+#define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2
+#define UVD_SUVD_CGC_GATE__SCM_MASK 0x8
+#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3
+#define UVD_SUVD_CGC_GATE__SDB_MASK 0x10
+#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4
+#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x20
+#define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
+#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x40
+#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6
+#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x80
+#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7
+#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x100
+#define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8
+#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x200
+#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9
+#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x400
+#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
+#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x800
+#define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb
+#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000
+#define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc
+#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x2000
+#define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd
+#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x4000
+#define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
+#define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x1
+#define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0
+#define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x2
+#define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1
+#define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x4
+#define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2
+#define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x8
+#define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3
+#define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x10
+#define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4
+#define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x20
+#define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5
+#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x40
+#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6
+#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x80
+#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7
+#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x100
+#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8
+#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x200
+#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9
+#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x400
+#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa
+#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x800
+#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb
+#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x1000
+#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc
+#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x2000
+#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd
+#define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x4000
+#define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe
+#define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x8000
+#define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf
+#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1
+#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0
+#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x2
+#define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1
+#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x4
+#define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2
+#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x8
+#define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3
+#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x10
+#define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4
+#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x20
+#define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
+#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x40
+#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6
+#define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID_MASK 0xf
+#define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID__SHIFT 0x0
+#define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID_MASK 0xf0
+#define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID__SHIFT 0x4
+#define UVD_LMI_VMID_INTERNAL__DPB_VMID_MASK 0xf00
+#define UVD_LMI_VMID_INTERNAL__DPB_VMID__SHIFT 0x8
+#define UVD_LMI_VMID_INTERNAL__DBW_VMID_MASK 0xf000
+#define UVD_LMI_VMID_INTERNAL__DBW_VMID__SHIFT 0xc
+#define UVD_LMI_VMID_INTERNAL__LBSI_VMID_MASK 0xf0000
+#define UVD_LMI_VMID_INTERNAL__LBSI_VMID__SHIFT 0x10
+#define UVD_LMI_VMID_INTERNAL__IDCT_VMID_MASK 0xf00000
+#define UVD_LMI_VMID_INTERNAL__IDCT_VMID__SHIFT 0x14
+#define UVD_LMI_VMID_INTERNAL__JPEG_VMID_MASK 0xf000000
+#define UVD_LMI_VMID_INTERNAL__JPEG_VMID__SHIFT 0x18
+#define UVD_LMI_VMID_INTERNAL__JPEG2_VMID_MASK 0xf0000000
+#define UVD_LMI_VMID_INTERNAL__JPEG2_VMID__SHIFT 0x1c
+#define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID_MASK 0xf
+#define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID__SHIFT 0x0
+#define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID_MASK 0xf0
+#define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID__SHIFT 0x4
+#define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID_MASK 0xf00
+#define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID__SHIFT 0x8
+#define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID_MASK 0xf000
+#define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID__SHIFT 0xc
+#define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID_MASK 0xf0000
+#define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID__SHIFT 0x10
+#define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID_MASK 0xf00000
+#define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID__SHIFT 0x14
+#define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID_MASK 0xf000000
+#define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID__SHIFT 0x18
+#define UVD_LMI_VMID_INTERNAL2__VDMA_VMID_MASK 0xf0000000
+#define UVD_LMI_VMID_INTERNAL2__VDMA_VMID__SHIFT 0x1c
+#define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x1
+#define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x0
+#define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2
+#define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x1
+#define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x4
+#define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2
+#define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x8
+#define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x3
+#define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x10
+#define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x4
+#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x20
+#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x5
+#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x3
+#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0
+#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0xc
+#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2
+#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0xf
+#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x0
+#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0xf0
+#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x4
+#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0xf00
+#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x8
+#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0xf000
+#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0xc
+#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x1
+#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0
+#define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2
+#define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1
+#define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x4
+#define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2
+#define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x8
+#define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3
+#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x10
+#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4
+#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20
+#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5
+#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x40
+#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6
+#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80
+#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7
+#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100
+#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8
+#define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200
+#define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9
+#define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x400
+#define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa
+#define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800
+#define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0xb
+#define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000
+#define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc
+#define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x2000
+#define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd
+#define UVD_CGC_MEM_CTRL__JPEG_LS_EN_MASK 0x4000
+#define UVD_CGC_MEM_CTRL__JPEG_LS_EN__SHIFT 0xe
+#define UVD_CGC_MEM_CTRL__JPEG2_LS_EN_MASK 0x8000
+#define UVD_CGC_MEM_CTRL__JPEG2_LS_EN__SHIFT 0xf
+#define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0xf0000
+#define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10
+#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0xf00000
+#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14
+#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1
+#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0
+#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2
+#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1
+#define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x1c
+#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2
+#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID_MASK 0xf
+#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID__SHIFT 0x0
+#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID_MASK 0xf0
+#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID__SHIFT 0x4
+#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID_MASK 0xf00
+#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID__SHIFT 0x8
+#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID_MASK 0xf000
+#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID__SHIFT 0xc
+#define UVD_LMI_VMID_INTERNAL3__MIF_SCLR_VMID_MASK 0xf0000
+#define UVD_LMI_VMID_INTERNAL3__MIF_SCLR_VMID__SHIFT 0x10
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0xff
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x0
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x8
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x9
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x400
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0xb
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0xc
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x2000
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0xd
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x1c
+#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0xffffff
+#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x0
+#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0xffffff
+#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x0
+#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x3
+#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0
+#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4
+#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2
+#define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT_MASK 0x8
+#define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT__SHIFT 0x3
+#define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT_MASK 0x10
+#define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT__SHIFT 0x4
+#define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT_MASK 0x20
+#define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT__SHIFT 0x5
+#define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE_MASK 0xc0
+#define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE__SHIFT 0x6
+#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100
+#define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8
+#define UVD_POWER_STATUS__PAUSE_DPG_REQ_MASK 0x200
+#define UVD_POWER_STATUS__PAUSE_DPG_REQ__SHIFT 0x9
+#define UVD_POWER_STATUS__PAUSE_DPG_ACK_MASK 0x400
+#define UVD_POWER_STATUS__PAUSE_DPG_ACK__SHIFT 0xa
+#define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE_MASK 0xffffff
+#define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE__SHIFT 0x0
+#define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE_MASK 0xffffff
+#define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE__SHIFT 0x0
+#define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE_MASK 0xffffff
+#define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE__SHIFT 0x0
+#define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE_MASK 0xffffff
+#define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE__SHIFT 0x0
+#define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE_MASK 0xffffff
+#define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE__SHIFT 0x0
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+
+#endif /* UVD_5_0_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h
new file mode 100644
index 000000000000..b2d4aaf045bc
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h
@@ -0,0 +1,115 @@
+/*
+ * UVD_6_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef UVD_6_0_D_H
+#define UVD_6_0_D_H
+
+#define mmUVD_SEMA_ADDR_LOW 0x3bc0
+#define mmUVD_SEMA_ADDR_HIGH 0x3bc1
+#define mmUVD_SEMA_CMD 0x3bc2
+#define mmUVD_GPCOM_VCPU_CMD 0x3bc3
+#define mmUVD_GPCOM_VCPU_DATA0 0x3bc4
+#define mmUVD_GPCOM_VCPU_DATA1 0x3bc5
+#define mmUVD_ENGINE_CNTL 0x3bc6
+#define mmUVD_UDEC_ADDR_CONFIG 0x3bd3
+#define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4
+#define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5
+#define mmUVD_POWER_STATUS_U 0x3bfd
+#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x3c69
+#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x3c68
+#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x3c67
+#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x3c66
+#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x3c5f
+#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x3c5e
+#define mmUVD_SEMA_CNTL 0x3d00
+#define mmUVD_LMI_EXT40_ADDR 0x3d26
+#define mmUVD_CTX_INDEX 0x3d28
+#define mmUVD_CTX_DATA 0x3d29
+#define mmUVD_CGC_GATE 0x3d2a
+#define mmUVD_CGC_STATUS 0x3d2b
+#define mmUVD_CGC_CTRL 0x3d2c
+#define mmUVD_CGC_UDEC_STATUS 0x3d2d
+#define mmUVD_LMI_CTRL2 0x3d3d
+#define mmUVD_MASTINT_EN 0x3d40
+#define mmUVD_LMI_ADDR_EXT 0x3d65
+#define mmUVD_LMI_CTRL 0x3d66
+#define mmUVD_LMI_STATUS 0x3d67
+#define mmUVD_LMI_SWAP_CNTL 0x3d6d
+#define mmUVD_MP_SWAP_CNTL 0x3d6f
+#define mmUVD_MPC_CNTL 0x3d77
+#define mmUVD_MPC_SET_MUXA0 0x3d79
+#define mmUVD_MPC_SET_MUXA1 0x3d7a
+#define mmUVD_MPC_SET_MUXB0 0x3d7b
+#define mmUVD_MPC_SET_MUXB1 0x3d7c
+#define mmUVD_MPC_SET_MUX 0x3d7d
+#define mmUVD_MPC_SET_ALU 0x3d7e
+#define mmUVD_VCPU_CACHE_OFFSET0 0x3d82
+#define mmUVD_VCPU_CACHE_SIZE0 0x3d83
+#define mmUVD_VCPU_CACHE_OFFSET1 0x3d84
+#define mmUVD_VCPU_CACHE_SIZE1 0x3d85
+#define mmUVD_VCPU_CACHE_OFFSET2 0x3d86
+#define mmUVD_VCPU_CACHE_SIZE2 0x3d87
+#define mmUVD_VCPU_CNTL 0x3d98
+#define mmUVD_SOFT_RESET 0x3da0
+#define mmUVD_LMI_RBC_IB_VMID 0x3da1
+#define mmUVD_RBC_IB_SIZE 0x3da2
+#define mmUVD_LMI_RBC_RB_VMID 0x3da3
+#define mmUVD_RBC_RB_RPTR 0x3da4
+#define mmUVD_RBC_RB_WPTR 0x3da5
+#define mmUVD_RBC_RB_WPTR_CNTL 0x3da6
+#define mmUVD_RBC_RB_CNTL 0x3da9
+#define mmUVD_RBC_RB_RPTR_ADDR 0x3daa
+#define mmUVD_STATUS 0x3daf
+#define mmUVD_SEMA_TIMEOUT_STATUS 0x3db0
+#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x3db1
+#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x3db2
+#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3db3
+#define mmUVD_CONTEXT_ID 0x3dbd
+#define mmUVD_RBC_IB_SIZE_UPDATE 0x3df1
+#define mmUVD_SUVD_CGC_GATE 0x3be4
+#define mmUVD_SUVD_CGC_STATUS 0x3be5
+#define mmUVD_SUVD_CGC_CTRL 0x3be6
+#define ixUVD_LMI_VMID_INTERNAL 0x99
+#define ixUVD_LMI_VMID_INTERNAL2 0x9a
+#define ixUVD_LMI_CACHE_CTRL 0x9b
+#define ixUVD_LMI_SWAP_CNTL2 0xaa
+#define ixUVD_LMI_ADDR_EXT2 0xab
+#define ixUVD_CGC_MEM_CTRL 0xc0
+#define ixUVD_CGC_CTRL2 0xc1
+#define ixUVD_LMI_VMID_INTERNAL3 0x162
+#define mmUVD_PGFSM_CONFIG 0x38c0
+#define mmUVD_PGFSM_READ_TILE1 0x38c2
+#define mmUVD_PGFSM_READ_TILE2 0x38c3
+#define mmUVD_POWER_STATUS 0x38c4
+#define mmUVD_PGFSM_READ_TILE3 0x38c5
+#define mmUVD_PGFSM_READ_TILE4 0x38c6
+#define mmUVD_PGFSM_READ_TILE5 0x38c8
+#define mmUVD_PGFSM_READ_TILE6 0x38ee
+#define mmUVD_PGFSM_READ_TILE7 0x38ef
+#define mmUVD_MIF_CURR_ADDR_CONFIG 0x3992
+#define mmUVD_MIF_REF_ADDR_CONFIG 0x3993
+#define mmUVD_MIF_RECON1_ADDR_CONFIG 0x39c5
+#define ixUVD_MIF_SCLR_ADDR_CONFIG 0x4
+#define mmUVD_JPEG_ADDR_CONFIG 0x3a1f
+
+#endif /* UVD_6_0_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_enum.h
new file mode 100644
index 000000000000..ecf47ba55c2d
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_enum.h
@@ -0,0 +1,1081 @@
+/*
+ * UVD_6_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef UVD_6_0_ENUM_H
+#define UVD_6_0_ENUM_H
+
+typedef enum UVDFirmwareCommand {
+ UVDFC_FENCE = 0x0,
+ UVDFC_TRAP = 0x1,
+ UVDFC_DECODED_ADDR = 0x2,
+ UVDFC_MBLOCK_ADDR = 0x3,
+ UVDFC_ITBUF_ADDR = 0x4,
+ UVDFC_DISPLAY_ADDR = 0x5,
+ UVDFC_EOD = 0x6,
+ UVDFC_DISPLAY_PITCH = 0x7,
+ UVDFC_DISPLAY_TILING = 0x8,
+ UVDFC_BITSTREAM_ADDR = 0x9,
+ UVDFC_BITSTREAM_SIZE = 0xa,
+} UVDFirmwareCommand;
+typedef enum DebugBlockId {
+ DBG_BLOCK_ID_RESERVED = 0x0,
+ DBG_BLOCK_ID_DBG = 0x1,
+ DBG_BLOCK_ID_VMC = 0x2,
+ DBG_BLOCK_ID_PDMA = 0x3,
+ DBG_BLOCK_ID_CG = 0x4,
+ DBG_BLOCK_ID_SRBM = 0x5,
+ DBG_BLOCK_ID_GRBM = 0x6,
+ DBG_BLOCK_ID_RLC = 0x7,
+ DBG_BLOCK_ID_CSC = 0x8,
+ DBG_BLOCK_ID_SEM = 0x9,
+ DBG_BLOCK_ID_IH = 0xa,
+ DBG_BLOCK_ID_SC = 0xb,
+ DBG_BLOCK_ID_SQ = 0xc,
+ DBG_BLOCK_ID_UVDU = 0xd,
+ DBG_BLOCK_ID_SQA = 0xe,
+ DBG_BLOCK_ID_SDMA0 = 0xf,
+ DBG_BLOCK_ID_SDMA1 = 0x10,
+ DBG_BLOCK_ID_SPIM = 0x11,
+ DBG_BLOCK_ID_GDS = 0x12,
+ DBG_BLOCK_ID_VC0 = 0x13,
+ DBG_BLOCK_ID_VC1 = 0x14,
+ DBG_BLOCK_ID_PA0 = 0x15,
+ DBG_BLOCK_ID_PA1 = 0x16,
+ DBG_BLOCK_ID_CP0 = 0x17,
+ DBG_BLOCK_ID_CP1 = 0x18,
+ DBG_BLOCK_ID_CP2 = 0x19,
+ DBG_BLOCK_ID_XBR = 0x1a,
+ DBG_BLOCK_ID_UVDM = 0x1b,
+ DBG_BLOCK_ID_VGT0 = 0x1c,
+ DBG_BLOCK_ID_VGT1 = 0x1d,
+ DBG_BLOCK_ID_IA = 0x1e,
+ DBG_BLOCK_ID_SXM0 = 0x1f,
+ DBG_BLOCK_ID_SXM1 = 0x20,
+ DBG_BLOCK_ID_SCT0 = 0x21,
+ DBG_BLOCK_ID_SCT1 = 0x22,
+ DBG_BLOCK_ID_SPM0 = 0x23,
+ DBG_BLOCK_ID_SPM1 = 0x24,
+ DBG_BLOCK_ID_UNUSED0 = 0x25,
+ DBG_BLOCK_ID_UNUSED1 = 0x26,
+ DBG_BLOCK_ID_TCAA = 0x27,
+ DBG_BLOCK_ID_TCAB = 0x28,
+ DBG_BLOCK_ID_TCCA = 0x29,
+ DBG_BLOCK_ID_TCCB = 0x2a,
+ DBG_BLOCK_ID_MCC0 = 0x2b,
+ DBG_BLOCK_ID_MCC1 = 0x2c,
+ DBG_BLOCK_ID_MCC2 = 0x2d,
+ DBG_BLOCK_ID_MCC3 = 0x2e,
+ DBG_BLOCK_ID_SXS0 = 0x2f,
+ DBG_BLOCK_ID_SXS1 = 0x30,
+ DBG_BLOCK_ID_SXS2 = 0x31,
+ DBG_BLOCK_ID_SXS3 = 0x32,
+ DBG_BLOCK_ID_SXS4 = 0x33,
+ DBG_BLOCK_ID_SXS5 = 0x34,
+ DBG_BLOCK_ID_SXS6 = 0x35,
+ DBG_BLOCK_ID_SXS7 = 0x36,
+ DBG_BLOCK_ID_SXS8 = 0x37,
+ DBG_BLOCK_ID_SXS9 = 0x38,
+ DBG_BLOCK_ID_BCI0 = 0x39,
+ DBG_BLOCK_ID_BCI1 = 0x3a,
+ DBG_BLOCK_ID_BCI2 = 0x3b,
+ DBG_BLOCK_ID_BCI3 = 0x3c,
+ DBG_BLOCK_ID_MCB = 0x3d,
+ DBG_BLOCK_ID_UNUSED6 = 0x3e,
+ DBG_BLOCK_ID_SQA00 = 0x3f,
+ DBG_BLOCK_ID_SQA01 = 0x40,
+ DBG_BLOCK_ID_SQA02 = 0x41,
+ DBG_BLOCK_ID_SQA10 = 0x42,
+ DBG_BLOCK_ID_SQA11 = 0x43,
+ DBG_BLOCK_ID_SQA12 = 0x44,
+ DBG_BLOCK_ID_UNUSED7 = 0x45,
+ DBG_BLOCK_ID_UNUSED8 = 0x46,
+ DBG_BLOCK_ID_SQB00 = 0x47,
+ DBG_BLOCK_ID_SQB01 = 0x48,
+ DBG_BLOCK_ID_SQB10 = 0x49,
+ DBG_BLOCK_ID_SQB11 = 0x4a,
+ DBG_BLOCK_ID_SQ00 = 0x4b,
+ DBG_BLOCK_ID_SQ01 = 0x4c,
+ DBG_BLOCK_ID_SQ10 = 0x4d,
+ DBG_BLOCK_ID_SQ11 = 0x4e,
+ DBG_BLOCK_ID_CB00 = 0x4f,
+ DBG_BLOCK_ID_CB01 = 0x50,
+ DBG_BLOCK_ID_CB02 = 0x51,
+ DBG_BLOCK_ID_CB03 = 0x52,
+ DBG_BLOCK_ID_CB04 = 0x53,
+ DBG_BLOCK_ID_UNUSED9 = 0x54,
+ DBG_BLOCK_ID_UNUSED10 = 0x55,
+ DBG_BLOCK_ID_UNUSED11 = 0x56,
+ DBG_BLOCK_ID_CB10 = 0x57,
+ DBG_BLOCK_ID_CB11 = 0x58,
+ DBG_BLOCK_ID_CB12 = 0x59,
+ DBG_BLOCK_ID_CB13 = 0x5a,
+ DBG_BLOCK_ID_CB14 = 0x5b,
+ DBG_BLOCK_ID_UNUSED12 = 0x5c,
+ DBG_BLOCK_ID_UNUSED13 = 0x5d,
+ DBG_BLOCK_ID_UNUSED14 = 0x5e,
+ DBG_BLOCK_ID_TCP0 = 0x5f,
+ DBG_BLOCK_ID_TCP1 = 0x60,
+ DBG_BLOCK_ID_TCP2 = 0x61,
+ DBG_BLOCK_ID_TCP3 = 0x62,
+ DBG_BLOCK_ID_TCP4 = 0x63,
+ DBG_BLOCK_ID_TCP5 = 0x64,
+ DBG_BLOCK_ID_TCP6 = 0x65,
+ DBG_BLOCK_ID_TCP7 = 0x66,
+ DBG_BLOCK_ID_TCP8 = 0x67,
+ DBG_BLOCK_ID_TCP9 = 0x68,
+ DBG_BLOCK_ID_TCP10 = 0x69,
+ DBG_BLOCK_ID_TCP11 = 0x6a,
+ DBG_BLOCK_ID_TCP12 = 0x6b,
+ DBG_BLOCK_ID_TCP13 = 0x6c,
+ DBG_BLOCK_ID_TCP14 = 0x6d,
+ DBG_BLOCK_ID_TCP15 = 0x6e,
+ DBG_BLOCK_ID_TCP16 = 0x6f,
+ DBG_BLOCK_ID_TCP17 = 0x70,
+ DBG_BLOCK_ID_TCP18 = 0x71,
+ DBG_BLOCK_ID_TCP19 = 0x72,
+ DBG_BLOCK_ID_TCP20 = 0x73,
+ DBG_BLOCK_ID_TCP21 = 0x74,
+ DBG_BLOCK_ID_TCP22 = 0x75,
+ DBG_BLOCK_ID_TCP23 = 0x76,
+ DBG_BLOCK_ID_TCP_RESERVED0 = 0x77,
+ DBG_BLOCK_ID_TCP_RESERVED1 = 0x78,
+ DBG_BLOCK_ID_TCP_RESERVED2 = 0x79,
+ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a,
+ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b,
+ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c,
+ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d,
+ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e,
+ DBG_BLOCK_ID_DB00 = 0x7f,
+ DBG_BLOCK_ID_DB01 = 0x80,
+ DBG_BLOCK_ID_DB02 = 0x81,
+ DBG_BLOCK_ID_DB03 = 0x82,
+ DBG_BLOCK_ID_DB04 = 0x83,
+ DBG_BLOCK_ID_UNUSED15 = 0x84,
+ DBG_BLOCK_ID_UNUSED16 = 0x85,
+ DBG_BLOCK_ID_UNUSED17 = 0x86,
+ DBG_BLOCK_ID_DB10 = 0x87,
+ DBG_BLOCK_ID_DB11 = 0x88,
+ DBG_BLOCK_ID_DB12 = 0x89,
+ DBG_BLOCK_ID_DB13 = 0x8a,
+ DBG_BLOCK_ID_DB14 = 0x8b,
+ DBG_BLOCK_ID_UNUSED18 = 0x8c,
+ DBG_BLOCK_ID_UNUSED19 = 0x8d,
+ DBG_BLOCK_ID_UNUSED20 = 0x8e,
+ DBG_BLOCK_ID_TCC0 = 0x8f,
+ DBG_BLOCK_ID_TCC1 = 0x90,
+ DBG_BLOCK_ID_TCC2 = 0x91,
+ DBG_BLOCK_ID_TCC3 = 0x92,
+ DBG_BLOCK_ID_TCC4 = 0x93,
+ DBG_BLOCK_ID_TCC5 = 0x94,
+ DBG_BLOCK_ID_TCC6 = 0x95,
+ DBG_BLOCK_ID_TCC7 = 0x96,
+ DBG_BLOCK_ID_SPS00 = 0x97,
+ DBG_BLOCK_ID_SPS01 = 0x98,
+ DBG_BLOCK_ID_SPS02 = 0x99,
+ DBG_BLOCK_ID_SPS10 = 0x9a,
+ DBG_BLOCK_ID_SPS11 = 0x9b,
+ DBG_BLOCK_ID_SPS12 = 0x9c,
+ DBG_BLOCK_ID_UNUSED21 = 0x9d,
+ DBG_BLOCK_ID_UNUSED22 = 0x9e,
+ DBG_BLOCK_ID_TA00 = 0x9f,
+ DBG_BLOCK_ID_TA01 = 0xa0,
+ DBG_BLOCK_ID_TA02 = 0xa1,
+ DBG_BLOCK_ID_TA03 = 0xa2,
+ DBG_BLOCK_ID_TA04 = 0xa3,
+ DBG_BLOCK_ID_TA05 = 0xa4,
+ DBG_BLOCK_ID_TA06 = 0xa5,
+ DBG_BLOCK_ID_TA07 = 0xa6,
+ DBG_BLOCK_ID_TA08 = 0xa7,
+ DBG_BLOCK_ID_TA09 = 0xa8,
+ DBG_BLOCK_ID_TA0A = 0xa9,
+ DBG_BLOCK_ID_TA0B = 0xaa,
+ DBG_BLOCK_ID_UNUSED23 = 0xab,
+ DBG_BLOCK_ID_UNUSED24 = 0xac,
+ DBG_BLOCK_ID_UNUSED25 = 0xad,
+ DBG_BLOCK_ID_UNUSED26 = 0xae,
+ DBG_BLOCK_ID_TA10 = 0xaf,
+ DBG_BLOCK_ID_TA11 = 0xb0,
+ DBG_BLOCK_ID_TA12 = 0xb1,
+ DBG_BLOCK_ID_TA13 = 0xb2,
+ DBG_BLOCK_ID_TA14 = 0xb3,
+ DBG_BLOCK_ID_TA15 = 0xb4,
+ DBG_BLOCK_ID_TA16 = 0xb5,
+ DBG_BLOCK_ID_TA17 = 0xb6,
+ DBG_BLOCK_ID_TA18 = 0xb7,
+ DBG_BLOCK_ID_TA19 = 0xb8,
+ DBG_BLOCK_ID_TA1A = 0xb9,
+ DBG_BLOCK_ID_TA1B = 0xba,
+ DBG_BLOCK_ID_UNUSED27 = 0xbb,
+ DBG_BLOCK_ID_UNUSED28 = 0xbc,
+ DBG_BLOCK_ID_UNUSED29 = 0xbd,
+ DBG_BLOCK_ID_UNUSED30 = 0xbe,
+ DBG_BLOCK_ID_TD00 = 0xbf,
+ DBG_BLOCK_ID_TD01 = 0xc0,
+ DBG_BLOCK_ID_TD02 = 0xc1,
+ DBG_BLOCK_ID_TD03 = 0xc2,
+ DBG_BLOCK_ID_TD04 = 0xc3,
+ DBG_BLOCK_ID_TD05 = 0xc4,
+ DBG_BLOCK_ID_TD06 = 0xc5,
+ DBG_BLOCK_ID_TD07 = 0xc6,
+ DBG_BLOCK_ID_TD08 = 0xc7,
+ DBG_BLOCK_ID_TD09 = 0xc8,
+ DBG_BLOCK_ID_TD0A = 0xc9,
+ DBG_BLOCK_ID_TD0B = 0xca,
+ DBG_BLOCK_ID_UNUSED31 = 0xcb,
+ DBG_BLOCK_ID_UNUSED32 = 0xcc,
+ DBG_BLOCK_ID_UNUSED33 = 0xcd,
+ DBG_BLOCK_ID_UNUSED34 = 0xce,
+ DBG_BLOCK_ID_TD10 = 0xcf,
+ DBG_BLOCK_ID_TD11 = 0xd0,
+ DBG_BLOCK_ID_TD12 = 0xd1,
+ DBG_BLOCK_ID_TD13 = 0xd2,
+ DBG_BLOCK_ID_TD14 = 0xd3,
+ DBG_BLOCK_ID_TD15 = 0xd4,
+ DBG_BLOCK_ID_TD16 = 0xd5,
+ DBG_BLOCK_ID_TD17 = 0xd6,
+ DBG_BLOCK_ID_TD18 = 0xd7,
+ DBG_BLOCK_ID_TD19 = 0xd8,
+ DBG_BLOCK_ID_TD1A = 0xd9,
+ DBG_BLOCK_ID_TD1B = 0xda,
+ DBG_BLOCK_ID_UNUSED35 = 0xdb,
+ DBG_BLOCK_ID_UNUSED36 = 0xdc,
+ DBG_BLOCK_ID_UNUSED37 = 0xdd,
+ DBG_BLOCK_ID_UNUSED38 = 0xde,
+ DBG_BLOCK_ID_LDS00 = 0xdf,
+ DBG_BLOCK_ID_LDS01 = 0xe0,
+ DBG_BLOCK_ID_LDS02 = 0xe1,
+ DBG_BLOCK_ID_LDS03 = 0xe2,
+ DBG_BLOCK_ID_LDS04 = 0xe3,
+ DBG_BLOCK_ID_LDS05 = 0xe4,
+ DBG_BLOCK_ID_LDS06 = 0xe5,
+ DBG_BLOCK_ID_LDS07 = 0xe6,
+ DBG_BLOCK_ID_LDS08 = 0xe7,
+ DBG_BLOCK_ID_LDS09 = 0xe8,
+ DBG_BLOCK_ID_LDS0A = 0xe9,
+ DBG_BLOCK_ID_LDS0B = 0xea,
+ DBG_BLOCK_ID_UNUSED39 = 0xeb,
+ DBG_BLOCK_ID_UNUSED40 = 0xec,
+ DBG_BLOCK_ID_UNUSED41 = 0xed,
+ DBG_BLOCK_ID_UNUSED42 = 0xee,
+ DBG_BLOCK_ID_LDS10 = 0xef,
+ DBG_BLOCK_ID_LDS11 = 0xf0,
+ DBG_BLOCK_ID_LDS12 = 0xf1,
+ DBG_BLOCK_ID_LDS13 = 0xf2,
+ DBG_BLOCK_ID_LDS14 = 0xf3,
+ DBG_BLOCK_ID_LDS15 = 0xf4,
+ DBG_BLOCK_ID_LDS16 = 0xf5,
+ DBG_BLOCK_ID_LDS17 = 0xf6,
+ DBG_BLOCK_ID_LDS18 = 0xf7,
+ DBG_BLOCK_ID_LDS19 = 0xf8,
+ DBG_BLOCK_ID_LDS1A = 0xf9,
+ DBG_BLOCK_ID_LDS1B = 0xfa,
+ DBG_BLOCK_ID_UNUSED43 = 0xfb,
+ DBG_BLOCK_ID_UNUSED44 = 0xfc,
+ DBG_BLOCK_ID_UNUSED45 = 0xfd,
+ DBG_BLOCK_ID_UNUSED46 = 0xfe,
+} DebugBlockId;
+typedef enum DebugBlockId_BY2 {
+ DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
+ DBG_BLOCK_ID_VMC_BY2 = 0x1,
+ DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
+ DBG_BLOCK_ID_GRBM_BY2 = 0x3,
+ DBG_BLOCK_ID_CSC_BY2 = 0x4,
+ DBG_BLOCK_ID_IH_BY2 = 0x5,
+ DBG_BLOCK_ID_SQ_BY2 = 0x6,
+ DBG_BLOCK_ID_UVD_BY2 = 0x7,
+ DBG_BLOCK_ID_SDMA0_BY2 = 0x8,
+ DBG_BLOCK_ID_SPIM_BY2 = 0x9,
+ DBG_BLOCK_ID_VC0_BY2 = 0xa,
+ DBG_BLOCK_ID_PA_BY2 = 0xb,
+ DBG_BLOCK_ID_CP0_BY2 = 0xc,
+ DBG_BLOCK_ID_CP2_BY2 = 0xd,
+ DBG_BLOCK_ID_PC0_BY2 = 0xe,
+ DBG_BLOCK_ID_BCI0_BY2 = 0xf,
+ DBG_BLOCK_ID_SXM0_BY2 = 0x10,
+ DBG_BLOCK_ID_SCT0_BY2 = 0x11,
+ DBG_BLOCK_ID_SPM0_BY2 = 0x12,
+ DBG_BLOCK_ID_BCI2_BY2 = 0x13,
+ DBG_BLOCK_ID_TCA_BY2 = 0x14,
+ DBG_BLOCK_ID_TCCA_BY2 = 0x15,
+ DBG_BLOCK_ID_MCC_BY2 = 0x16,
+ DBG_BLOCK_ID_MCC2_BY2 = 0x17,
+ DBG_BLOCK_ID_MCD_BY2 = 0x18,
+ DBG_BLOCK_ID_MCD2_BY2 = 0x19,
+ DBG_BLOCK_ID_MCD4_BY2 = 0x1a,
+ DBG_BLOCK_ID_MCB_BY2 = 0x1b,
+ DBG_BLOCK_ID_SQA_BY2 = 0x1c,
+ DBG_BLOCK_ID_SQA02_BY2 = 0x1d,
+ DBG_BLOCK_ID_SQA11_BY2 = 0x1e,
+ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f,
+ DBG_BLOCK_ID_SQB_BY2 = 0x20,
+ DBG_BLOCK_ID_SQB10_BY2 = 0x21,
+ DBG_BLOCK_ID_UNUSED10_BY2 = 0x22,
+ DBG_BLOCK_ID_UNUSED12_BY2 = 0x23,
+ DBG_BLOCK_ID_CB_BY2 = 0x24,
+ DBG_BLOCK_ID_CB02_BY2 = 0x25,
+ DBG_BLOCK_ID_CB10_BY2 = 0x26,
+ DBG_BLOCK_ID_CB12_BY2 = 0x27,
+ DBG_BLOCK_ID_SXS_BY2 = 0x28,
+ DBG_BLOCK_ID_SXS2_BY2 = 0x29,
+ DBG_BLOCK_ID_SXS4_BY2 = 0x2a,
+ DBG_BLOCK_ID_SXS6_BY2 = 0x2b,
+ DBG_BLOCK_ID_DB_BY2 = 0x2c,
+ DBG_BLOCK_ID_DB02_BY2 = 0x2d,
+ DBG_BLOCK_ID_DB10_BY2 = 0x2e,
+ DBG_BLOCK_ID_DB12_BY2 = 0x2f,
+ DBG_BLOCK_ID_TCP_BY2 = 0x30,
+ DBG_BLOCK_ID_TCP2_BY2 = 0x31,
+ DBG_BLOCK_ID_TCP4_BY2 = 0x32,
+ DBG_BLOCK_ID_TCP6_BY2 = 0x33,
+ DBG_BLOCK_ID_TCP8_BY2 = 0x34,
+ DBG_BLOCK_ID_TCP10_BY2 = 0x35,
+ DBG_BLOCK_ID_TCP12_BY2 = 0x36,
+ DBG_BLOCK_ID_TCP14_BY2 = 0x37,
+ DBG_BLOCK_ID_TCP16_BY2 = 0x38,
+ DBG_BLOCK_ID_TCP18_BY2 = 0x39,
+ DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
+ DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
+ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
+ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
+ DBG_BLOCK_ID_TCC_BY2 = 0x40,
+ DBG_BLOCK_ID_TCC2_BY2 = 0x41,
+ DBG_BLOCK_ID_TCC4_BY2 = 0x42,
+ DBG_BLOCK_ID_TCC6_BY2 = 0x43,
+ DBG_BLOCK_ID_SPS_BY2 = 0x44,
+ DBG_BLOCK_ID_SPS02_BY2 = 0x45,
+ DBG_BLOCK_ID_SPS11_BY2 = 0x46,
+ DBG_BLOCK_ID_UNUSED14_BY2 = 0x47,
+ DBG_BLOCK_ID_TA_BY2 = 0x48,
+ DBG_BLOCK_ID_TA02_BY2 = 0x49,
+ DBG_BLOCK_ID_TA04_BY2 = 0x4a,
+ DBG_BLOCK_ID_TA06_BY2 = 0x4b,
+ DBG_BLOCK_ID_TA08_BY2 = 0x4c,
+ DBG_BLOCK_ID_TA0A_BY2 = 0x4d,
+ DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e,
+ DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f,
+ DBG_BLOCK_ID_TA10_BY2 = 0x50,
+ DBG_BLOCK_ID_TA12_BY2 = 0x51,
+ DBG_BLOCK_ID_TA14_BY2 = 0x52,
+ DBG_BLOCK_ID_TA16_BY2 = 0x53,
+ DBG_BLOCK_ID_TA18_BY2 = 0x54,
+ DBG_BLOCK_ID_TA1A_BY2 = 0x55,
+ DBG_BLOCK_ID_UNUSED24_BY2 = 0x56,
+ DBG_BLOCK_ID_UNUSED26_BY2 = 0x57,
+ DBG_BLOCK_ID_TD_BY2 = 0x58,
+ DBG_BLOCK_ID_TD02_BY2 = 0x59,
+ DBG_BLOCK_ID_TD04_BY2 = 0x5a,
+ DBG_BLOCK_ID_TD06_BY2 = 0x5b,
+ DBG_BLOCK_ID_TD08_BY2 = 0x5c,
+ DBG_BLOCK_ID_TD0A_BY2 = 0x5d,
+ DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e,
+ DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f,
+ DBG_BLOCK_ID_TD10_BY2 = 0x60,
+ DBG_BLOCK_ID_TD12_BY2 = 0x61,
+ DBG_BLOCK_ID_TD14_BY2 = 0x62,
+ DBG_BLOCK_ID_TD16_BY2 = 0x63,
+ DBG_BLOCK_ID_TD18_BY2 = 0x64,
+ DBG_BLOCK_ID_TD1A_BY2 = 0x65,
+ DBG_BLOCK_ID_UNUSED32_BY2 = 0x66,
+ DBG_BLOCK_ID_UNUSED34_BY2 = 0x67,
+ DBG_BLOCK_ID_LDS_BY2 = 0x68,
+ DBG_BLOCK_ID_LDS02_BY2 = 0x69,
+ DBG_BLOCK_ID_LDS04_BY2 = 0x6a,
+ DBG_BLOCK_ID_LDS06_BY2 = 0x6b,
+ DBG_BLOCK_ID_LDS08_BY2 = 0x6c,
+ DBG_BLOCK_ID_LDS0A_BY2 = 0x6d,
+ DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e,
+ DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f,
+ DBG_BLOCK_ID_LDS10_BY2 = 0x70,
+ DBG_BLOCK_ID_LDS12_BY2 = 0x71,
+ DBG_BLOCK_ID_LDS14_BY2 = 0x72,
+ DBG_BLOCK_ID_LDS16_BY2 = 0x73,
+ DBG_BLOCK_ID_LDS18_BY2 = 0x74,
+ DBG_BLOCK_ID_LDS1A_BY2 = 0x75,
+ DBG_BLOCK_ID_UNUSED40_BY2 = 0x76,
+ DBG_BLOCK_ID_UNUSED42_BY2 = 0x77,
+} DebugBlockId_BY2;
+typedef enum DebugBlockId_BY4 {
+ DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
+ DBG_BLOCK_ID_UNUSED0_BY4 = 0x1,
+ DBG_BLOCK_ID_CSC_BY4 = 0x2,
+ DBG_BLOCK_ID_SQ_BY4 = 0x3,
+ DBG_BLOCK_ID_SDMA0_BY4 = 0x4,
+ DBG_BLOCK_ID_VC0_BY4 = 0x5,
+ DBG_BLOCK_ID_CP0_BY4 = 0x6,
+ DBG_BLOCK_ID_UNUSED1_BY4 = 0x7,
+ DBG_BLOCK_ID_SXM0_BY4 = 0x8,
+ DBG_BLOCK_ID_SPM0_BY4 = 0x9,
+ DBG_BLOCK_ID_TCAA_BY4 = 0xa,
+ DBG_BLOCK_ID_MCC_BY4 = 0xb,
+ DBG_BLOCK_ID_MCD_BY4 = 0xc,
+ DBG_BLOCK_ID_MCD4_BY4 = 0xd,
+ DBG_BLOCK_ID_SQA_BY4 = 0xe,
+ DBG_BLOCK_ID_SQA11_BY4 = 0xf,
+ DBG_BLOCK_ID_SQB_BY4 = 0x10,
+ DBG_BLOCK_ID_UNUSED10_BY4 = 0x11,
+ DBG_BLOCK_ID_CB_BY4 = 0x12,
+ DBG_BLOCK_ID_CB10_BY4 = 0x13,
+ DBG_BLOCK_ID_SXS_BY4 = 0x14,
+ DBG_BLOCK_ID_SXS4_BY4 = 0x15,
+ DBG_BLOCK_ID_DB_BY4 = 0x16,
+ DBG_BLOCK_ID_DB10_BY4 = 0x17,
+ DBG_BLOCK_ID_TCP_BY4 = 0x18,
+ DBG_BLOCK_ID_TCP4_BY4 = 0x19,
+ DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
+ DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
+ DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
+ DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
+ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
+ DBG_BLOCK_ID_TCC_BY4 = 0x20,
+ DBG_BLOCK_ID_TCC4_BY4 = 0x21,
+ DBG_BLOCK_ID_SPS_BY4 = 0x22,
+ DBG_BLOCK_ID_SPS11_BY4 = 0x23,
+ DBG_BLOCK_ID_TA_BY4 = 0x24,
+ DBG_BLOCK_ID_TA04_BY4 = 0x25,
+ DBG_BLOCK_ID_TA08_BY4 = 0x26,
+ DBG_BLOCK_ID_UNUSED20_BY4 = 0x27,
+ DBG_BLOCK_ID_TA10_BY4 = 0x28,
+ DBG_BLOCK_ID_TA14_BY4 = 0x29,
+ DBG_BLOCK_ID_TA18_BY4 = 0x2a,
+ DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b,
+ DBG_BLOCK_ID_TD_BY4 = 0x2c,
+ DBG_BLOCK_ID_TD04_BY4 = 0x2d,
+ DBG_BLOCK_ID_TD08_BY4 = 0x2e,
+ DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f,
+ DBG_BLOCK_ID_TD10_BY4 = 0x30,
+ DBG_BLOCK_ID_TD14_BY4 = 0x31,
+ DBG_BLOCK_ID_TD18_BY4 = 0x32,
+ DBG_BLOCK_ID_UNUSED32_BY4 = 0x33,
+ DBG_BLOCK_ID_LDS_BY4 = 0x34,
+ DBG_BLOCK_ID_LDS04_BY4 = 0x35,
+ DBG_BLOCK_ID_LDS08_BY4 = 0x36,
+ DBG_BLOCK_ID_UNUSED36_BY4 = 0x37,
+ DBG_BLOCK_ID_LDS10_BY4 = 0x38,
+ DBG_BLOCK_ID_LDS14_BY4 = 0x39,
+ DBG_BLOCK_ID_LDS18_BY4 = 0x3a,
+ DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b,
+} DebugBlockId_BY4;
+typedef enum DebugBlockId_BY8 {
+ DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
+ DBG_BLOCK_ID_CSC_BY8 = 0x1,
+ DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
+ DBG_BLOCK_ID_CP0_BY8 = 0x3,
+ DBG_BLOCK_ID_SXM0_BY8 = 0x4,
+ DBG_BLOCK_ID_TCA_BY8 = 0x5,
+ DBG_BLOCK_ID_MCD_BY8 = 0x6,
+ DBG_BLOCK_ID_SQA_BY8 = 0x7,
+ DBG_BLOCK_ID_SQB_BY8 = 0x8,
+ DBG_BLOCK_ID_CB_BY8 = 0x9,
+ DBG_BLOCK_ID_SXS_BY8 = 0xa,
+ DBG_BLOCK_ID_DB_BY8 = 0xb,
+ DBG_BLOCK_ID_TCP_BY8 = 0xc,
+ DBG_BLOCK_ID_TCP8_BY8 = 0xd,
+ DBG_BLOCK_ID_TCP16_BY8 = 0xe,
+ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
+ DBG_BLOCK_ID_TCC_BY8 = 0x10,
+ DBG_BLOCK_ID_SPS_BY8 = 0x11,
+ DBG_BLOCK_ID_TA_BY8 = 0x12,
+ DBG_BLOCK_ID_TA08_BY8 = 0x13,
+ DBG_BLOCK_ID_TA10_BY8 = 0x14,
+ DBG_BLOCK_ID_TA18_BY8 = 0x15,
+ DBG_BLOCK_ID_TD_BY8 = 0x16,
+ DBG_BLOCK_ID_TD08_BY8 = 0x17,
+ DBG_BLOCK_ID_TD10_BY8 = 0x18,
+ DBG_BLOCK_ID_TD18_BY8 = 0x19,
+ DBG_BLOCK_ID_LDS_BY8 = 0x1a,
+ DBG_BLOCK_ID_LDS08_BY8 = 0x1b,
+ DBG_BLOCK_ID_LDS10_BY8 = 0x1c,
+ DBG_BLOCK_ID_LDS18_BY8 = 0x1d,
+} DebugBlockId_BY8;
+typedef enum DebugBlockId_BY16 {
+ DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
+ DBG_BLOCK_ID_SDMA0_BY16 = 0x1,
+ DBG_BLOCK_ID_SXM_BY16 = 0x2,
+ DBG_BLOCK_ID_MCD_BY16 = 0x3,
+ DBG_BLOCK_ID_SQB_BY16 = 0x4,
+ DBG_BLOCK_ID_SXS_BY16 = 0x5,
+ DBG_BLOCK_ID_TCP_BY16 = 0x6,
+ DBG_BLOCK_ID_TCP16_BY16 = 0x7,
+ DBG_BLOCK_ID_TCC_BY16 = 0x8,
+ DBG_BLOCK_ID_TA_BY16 = 0x9,
+ DBG_BLOCK_ID_TA10_BY16 = 0xa,
+ DBG_BLOCK_ID_TD_BY16 = 0xb,
+ DBG_BLOCK_ID_TD10_BY16 = 0xc,
+ DBG_BLOCK_ID_LDS_BY16 = 0xd,
+ DBG_BLOCK_ID_LDS10_BY16 = 0xe,
+} DebugBlockId_BY16;
+typedef enum SurfaceEndian {
+ ENDIAN_NONE = 0x0,
+ ENDIAN_8IN16 = 0x1,
+ ENDIAN_8IN32 = 0x2,
+ ENDIAN_8IN64 = 0x3,
+} SurfaceEndian;
+typedef enum ArrayMode {
+ ARRAY_LINEAR_GENERAL = 0x0,
+ ARRAY_LINEAR_ALIGNED = 0x1,
+ ARRAY_1D_TILED_THIN1 = 0x2,
+ ARRAY_1D_TILED_THICK = 0x3,
+ ARRAY_2D_TILED_THIN1 = 0x4,
+ ARRAY_PRT_TILED_THIN1 = 0x5,
+ ARRAY_PRT_2D_TILED_THIN1 = 0x6,
+ ARRAY_2D_TILED_THICK = 0x7,
+ ARRAY_2D_TILED_XTHICK = 0x8,
+ ARRAY_PRT_TILED_THICK = 0x9,
+ ARRAY_PRT_2D_TILED_THICK = 0xa,
+ ARRAY_PRT_3D_TILED_THIN1 = 0xb,
+ ARRAY_3D_TILED_THIN1 = 0xc,
+ ARRAY_3D_TILED_THICK = 0xd,
+ ARRAY_3D_TILED_XTHICK = 0xe,
+ ARRAY_PRT_3D_TILED_THICK = 0xf,
+} ArrayMode;
+typedef enum PipeTiling {
+ CONFIG_1_PIPE = 0x0,
+ CONFIG_2_PIPE = 0x1,
+ CONFIG_4_PIPE = 0x2,
+ CONFIG_8_PIPE = 0x3,
+} PipeTiling;
+typedef enum BankTiling {
+ CONFIG_4_BANK = 0x0,
+ CONFIG_8_BANK = 0x1,
+} BankTiling;
+typedef enum GroupInterleave {
+ CONFIG_256B_GROUP = 0x0,
+ CONFIG_512B_GROUP = 0x1,
+} GroupInterleave;
+typedef enum RowTiling {
+ CONFIG_1KB_ROW = 0x0,
+ CONFIG_2KB_ROW = 0x1,
+ CONFIG_4KB_ROW = 0x2,
+ CONFIG_8KB_ROW = 0x3,
+ CONFIG_1KB_ROW_OPT = 0x4,
+ CONFIG_2KB_ROW_OPT = 0x5,
+ CONFIG_4KB_ROW_OPT = 0x6,
+ CONFIG_8KB_ROW_OPT = 0x7,
+} RowTiling;
+typedef enum BankSwapBytes {
+ CONFIG_128B_SWAPS = 0x0,
+ CONFIG_256B_SWAPS = 0x1,
+ CONFIG_512B_SWAPS = 0x2,
+ CONFIG_1KB_SWAPS = 0x3,
+} BankSwapBytes;
+typedef enum SampleSplitBytes {
+ CONFIG_1KB_SPLIT = 0x0,
+ CONFIG_2KB_SPLIT = 0x1,
+ CONFIG_4KB_SPLIT = 0x2,
+ CONFIG_8KB_SPLIT = 0x3,
+} SampleSplitBytes;
+typedef enum NumPipes {
+ ADDR_CONFIG_1_PIPE = 0x0,
+ ADDR_CONFIG_2_PIPE = 0x1,
+ ADDR_CONFIG_4_PIPE = 0x2,
+ ADDR_CONFIG_8_PIPE = 0x3,
+} NumPipes;
+typedef enum PipeInterleaveSize {
+ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
+ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
+} PipeInterleaveSize;
+typedef enum BankInterleaveSize {
+ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
+ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
+ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
+ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
+} BankInterleaveSize;
+typedef enum NumShaderEngines {
+ ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
+ ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
+} NumShaderEngines;
+typedef enum ShaderEngineTileSize {
+ ADDR_CONFIG_SE_TILE_16 = 0x0,
+ ADDR_CONFIG_SE_TILE_32 = 0x1,
+} ShaderEngineTileSize;
+typedef enum NumGPUs {
+ ADDR_CONFIG_1_GPU = 0x0,
+ ADDR_CONFIG_2_GPU = 0x1,
+ ADDR_CONFIG_4_GPU = 0x2,
+} NumGPUs;
+typedef enum MultiGPUTileSize {
+ ADDR_CONFIG_GPU_TILE_16 = 0x0,
+ ADDR_CONFIG_GPU_TILE_32 = 0x1,
+ ADDR_CONFIG_GPU_TILE_64 = 0x2,
+ ADDR_CONFIG_GPU_TILE_128 = 0x3,
+} MultiGPUTileSize;
+typedef enum RowSize {
+ ADDR_CONFIG_1KB_ROW = 0x0,
+ ADDR_CONFIG_2KB_ROW = 0x1,
+ ADDR_CONFIG_4KB_ROW = 0x2,
+} RowSize;
+typedef enum NumLowerPipes {
+ ADDR_CONFIG_1_LOWER_PIPES = 0x0,
+ ADDR_CONFIG_2_LOWER_PIPES = 0x1,
+} NumLowerPipes;
+typedef enum ColorTransform {
+ DCC_CT_AUTO = 0x0,
+ DCC_CT_NONE = 0x1,
+ ABGR_TO_A_BG_G_RB = 0x2,
+ BGRA_TO_BG_G_RB_A = 0x3,
+} ColorTransform;
+typedef enum CompareRef {
+ REF_NEVER = 0x0,
+ REF_LESS = 0x1,
+ REF_EQUAL = 0x2,
+ REF_LEQUAL = 0x3,
+ REF_GREATER = 0x4,
+ REF_NOTEQUAL = 0x5,
+ REF_GEQUAL = 0x6,
+ REF_ALWAYS = 0x7,
+} CompareRef;
+typedef enum ReadSize {
+ READ_256_BITS = 0x0,
+ READ_512_BITS = 0x1,
+} ReadSize;
+typedef enum DepthFormat {
+ DEPTH_INVALID = 0x0,
+ DEPTH_16 = 0x1,
+ DEPTH_X8_24 = 0x2,
+ DEPTH_8_24 = 0x3,
+ DEPTH_X8_24_FLOAT = 0x4,
+ DEPTH_8_24_FLOAT = 0x5,
+ DEPTH_32_FLOAT = 0x6,
+ DEPTH_X24_8_32_FLOAT = 0x7,
+} DepthFormat;
+typedef enum ZFormat {
+ Z_INVALID = 0x0,
+ Z_16 = 0x1,
+ Z_24 = 0x2,
+ Z_32_FLOAT = 0x3,
+} ZFormat;
+typedef enum StencilFormat {
+ STENCIL_INVALID = 0x0,
+ STENCIL_8 = 0x1,
+} StencilFormat;
+typedef enum CmaskMode {
+ CMASK_CLEAR_NONE = 0x0,
+ CMASK_CLEAR_ONE = 0x1,
+ CMASK_CLEAR_ALL = 0x2,
+ CMASK_ANY_EXPANDED = 0x3,
+ CMASK_ALPHA0_FRAG1 = 0x4,
+ CMASK_ALPHA0_FRAG2 = 0x5,
+ CMASK_ALPHA0_FRAG4 = 0x6,
+ CMASK_ALPHA0_FRAGS = 0x7,
+ CMASK_ALPHA1_FRAG1 = 0x8,
+ CMASK_ALPHA1_FRAG2 = 0x9,
+ CMASK_ALPHA1_FRAG4 = 0xa,
+ CMASK_ALPHA1_FRAGS = 0xb,
+ CMASK_ALPHAX_FRAG1 = 0xc,
+ CMASK_ALPHAX_FRAG2 = 0xd,
+ CMASK_ALPHAX_FRAG4 = 0xe,
+ CMASK_ALPHAX_FRAGS = 0xf,
+} CmaskMode;
+typedef enum QuadExportFormat {
+ EXPORT_UNUSED = 0x0,
+ EXPORT_32_R = 0x1,
+ EXPORT_32_GR = 0x2,
+ EXPORT_32_AR = 0x3,
+ EXPORT_FP16_ABGR = 0x4,
+ EXPORT_UNSIGNED16_ABGR = 0x5,
+ EXPORT_SIGNED16_ABGR = 0x6,
+ EXPORT_32_ABGR = 0x7,
+} QuadExportFormat;
+typedef enum QuadExportFormatOld {
+ EXPORT_4P_32BPC_ABGR = 0x0,
+ EXPORT_4P_16BPC_ABGR = 0x1,
+ EXPORT_4P_32BPC_GR = 0x2,
+ EXPORT_4P_32BPC_AR = 0x3,
+ EXPORT_2P_32BPC_ABGR = 0x4,
+ EXPORT_8P_32BPC_R = 0x5,
+} QuadExportFormatOld;
+typedef enum ColorFormat {
+ COLOR_INVALID = 0x0,
+ COLOR_8 = 0x1,
+ COLOR_16 = 0x2,
+ COLOR_8_8 = 0x3,
+ COLOR_32 = 0x4,
+ COLOR_16_16 = 0x5,
+ COLOR_10_11_11 = 0x6,
+ COLOR_11_11_10 = 0x7,
+ COLOR_10_10_10_2 = 0x8,
+ COLOR_2_10_10_10 = 0x9,
+ COLOR_8_8_8_8 = 0xa,
+ COLOR_32_32 = 0xb,
+ COLOR_16_16_16_16 = 0xc,
+ COLOR_RESERVED_13 = 0xd,
+ COLOR_32_32_32_32 = 0xe,
+ COLOR_RESERVED_15 = 0xf,
+ COLOR_5_6_5 = 0x10,
+ COLOR_1_5_5_5 = 0x11,
+ COLOR_5_5_5_1 = 0x12,
+ COLOR_4_4_4_4 = 0x13,
+ COLOR_8_24 = 0x14,
+ COLOR_24_8 = 0x15,
+ COLOR_X24_8_32_FLOAT = 0x16,
+ COLOR_RESERVED_23 = 0x17,
+} ColorFormat;
+typedef enum SurfaceFormat {
+ FMT_INVALID = 0x0,
+ FMT_8 = 0x1,
+ FMT_16 = 0x2,
+ FMT_8_8 = 0x3,
+ FMT_32 = 0x4,
+ FMT_16_16 = 0x5,
+ FMT_10_11_11 = 0x6,
+ FMT_11_11_10 = 0x7,
+ FMT_10_10_10_2 = 0x8,
+ FMT_2_10_10_10 = 0x9,
+ FMT_8_8_8_8 = 0xa,
+ FMT_32_32 = 0xb,
+ FMT_16_16_16_16 = 0xc,
+ FMT_32_32_32 = 0xd,
+ FMT_32_32_32_32 = 0xe,
+ FMT_RESERVED_4 = 0xf,
+ FMT_5_6_5 = 0x10,
+ FMT_1_5_5_5 = 0x11,
+ FMT_5_5_5_1 = 0x12,
+ FMT_4_4_4_4 = 0x13,
+ FMT_8_24 = 0x14,
+ FMT_24_8 = 0x15,
+ FMT_X24_8_32_FLOAT = 0x16,
+ FMT_RESERVED_33 = 0x17,
+ FMT_11_11_10_FLOAT = 0x18,
+ FMT_16_FLOAT = 0x19,
+ FMT_32_FLOAT = 0x1a,
+ FMT_16_16_FLOAT = 0x1b,
+ FMT_8_24_FLOAT = 0x1c,
+ FMT_24_8_FLOAT = 0x1d,
+ FMT_32_32_FLOAT = 0x1e,
+ FMT_10_11_11_FLOAT = 0x1f,
+ FMT_16_16_16_16_FLOAT = 0x20,
+ FMT_3_3_2 = 0x21,
+ FMT_6_5_5 = 0x22,
+ FMT_32_32_32_32_FLOAT = 0x23,
+ FMT_RESERVED_36 = 0x24,
+ FMT_1 = 0x25,
+ FMT_1_REVERSED = 0x26,
+ FMT_GB_GR = 0x27,
+ FMT_BG_RG = 0x28,
+ FMT_32_AS_8 = 0x29,
+ FMT_32_AS_8_8 = 0x2a,
+ FMT_5_9_9_9_SHAREDEXP = 0x2b,
+ FMT_8_8_8 = 0x2c,
+ FMT_16_16_16 = 0x2d,
+ FMT_16_16_16_FLOAT = 0x2e,
+ FMT_4_4 = 0x2f,
+ FMT_32_32_32_FLOAT = 0x30,
+ FMT_BC1 = 0x31,
+ FMT_BC2 = 0x32,
+ FMT_BC3 = 0x33,
+ FMT_BC4 = 0x34,
+ FMT_BC5 = 0x35,
+ FMT_BC6 = 0x36,
+ FMT_BC7 = 0x37,
+ FMT_32_AS_32_32_32_32 = 0x38,
+ FMT_APC3 = 0x39,
+ FMT_APC4 = 0x3a,
+ FMT_APC5 = 0x3b,
+ FMT_APC6 = 0x3c,
+ FMT_APC7 = 0x3d,
+ FMT_CTX1 = 0x3e,
+ FMT_RESERVED_63 = 0x3f,
+} SurfaceFormat;
+typedef enum BUF_DATA_FORMAT {
+ BUF_DATA_FORMAT_INVALID = 0x0,
+ BUF_DATA_FORMAT_8 = 0x1,
+ BUF_DATA_FORMAT_16 = 0x2,
+ BUF_DATA_FORMAT_8_8 = 0x3,
+ BUF_DATA_FORMAT_32 = 0x4,
+ BUF_DATA_FORMAT_16_16 = 0x5,
+ BUF_DATA_FORMAT_10_11_11 = 0x6,
+ BUF_DATA_FORMAT_11_11_10 = 0x7,
+ BUF_DATA_FORMAT_10_10_10_2 = 0x8,
+ BUF_DATA_FORMAT_2_10_10_10 = 0x9,
+ BUF_DATA_FORMAT_8_8_8_8 = 0xa,
+ BUF_DATA_FORMAT_32_32 = 0xb,
+ BUF_DATA_FORMAT_16_16_16_16 = 0xc,
+ BUF_DATA_FORMAT_32_32_32 = 0xd,
+ BUF_DATA_FORMAT_32_32_32_32 = 0xe,
+ BUF_DATA_FORMAT_RESERVED_15 = 0xf,
+} BUF_DATA_FORMAT;
+typedef enum IMG_DATA_FORMAT {
+ IMG_DATA_FORMAT_INVALID = 0x0,
+ IMG_DATA_FORMAT_8 = 0x1,
+ IMG_DATA_FORMAT_16 = 0x2,
+ IMG_DATA_FORMAT_8_8 = 0x3,
+ IMG_DATA_FORMAT_32 = 0x4,
+ IMG_DATA_FORMAT_16_16 = 0x5,
+ IMG_DATA_FORMAT_10_11_11 = 0x6,
+ IMG_DATA_FORMAT_11_11_10 = 0x7,
+ IMG_DATA_FORMAT_10_10_10_2 = 0x8,
+ IMG_DATA_FORMAT_2_10_10_10 = 0x9,
+ IMG_DATA_FORMAT_8_8_8_8 = 0xa,
+ IMG_DATA_FORMAT_32_32 = 0xb,
+ IMG_DATA_FORMAT_16_16_16_16 = 0xc,
+ IMG_DATA_FORMAT_32_32_32 = 0xd,
+ IMG_DATA_FORMAT_32_32_32_32 = 0xe,
+ IMG_DATA_FORMAT_RESERVED_15 = 0xf,
+ IMG_DATA_FORMAT_5_6_5 = 0x10,
+ IMG_DATA_FORMAT_1_5_5_5 = 0x11,
+ IMG_DATA_FORMAT_5_5_5_1 = 0x12,
+ IMG_DATA_FORMAT_4_4_4_4 = 0x13,
+ IMG_DATA_FORMAT_8_24 = 0x14,
+ IMG_DATA_FORMAT_24_8 = 0x15,
+ IMG_DATA_FORMAT_X24_8_32 = 0x16,
+ IMG_DATA_FORMAT_RESERVED_23 = 0x17,
+ IMG_DATA_FORMAT_RESERVED_24 = 0x18,
+ IMG_DATA_FORMAT_RESERVED_25 = 0x19,
+ IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
+ IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
+ IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
+ IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
+ IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
+ IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
+ IMG_DATA_FORMAT_GB_GR = 0x20,
+ IMG_DATA_FORMAT_BG_RG = 0x21,
+ IMG_DATA_FORMAT_5_9_9_9 = 0x22,
+ IMG_DATA_FORMAT_BC1 = 0x23,
+ IMG_DATA_FORMAT_BC2 = 0x24,
+ IMG_DATA_FORMAT_BC3 = 0x25,
+ IMG_DATA_FORMAT_BC4 = 0x26,
+ IMG_DATA_FORMAT_BC5 = 0x27,
+ IMG_DATA_FORMAT_BC6 = 0x28,
+ IMG_DATA_FORMAT_BC7 = 0x29,
+ IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
+ IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
+ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
+ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
+ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
+ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
+ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
+ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
+ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
+ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
+ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
+ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
+ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
+ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
+ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
+ IMG_DATA_FORMAT_4_4 = 0x39,
+ IMG_DATA_FORMAT_6_5_5 = 0x3a,
+ IMG_DATA_FORMAT_1 = 0x3b,
+ IMG_DATA_FORMAT_1_REVERSED = 0x3c,
+ IMG_DATA_FORMAT_32_AS_8 = 0x3d,
+ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
+ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
+} IMG_DATA_FORMAT;
+typedef enum BUF_NUM_FORMAT {
+ BUF_NUM_FORMAT_UNORM = 0x0,
+ BUF_NUM_FORMAT_SNORM = 0x1,
+ BUF_NUM_FORMAT_USCALED = 0x2,
+ BUF_NUM_FORMAT_SSCALED = 0x3,
+ BUF_NUM_FORMAT_UINT = 0x4,
+ BUF_NUM_FORMAT_SINT = 0x5,
+ BUF_NUM_FORMAT_RESERVED_6 = 0x6,
+ BUF_NUM_FORMAT_FLOAT = 0x7,
+} BUF_NUM_FORMAT;
+typedef enum IMG_NUM_FORMAT {
+ IMG_NUM_FORMAT_UNORM = 0x0,
+ IMG_NUM_FORMAT_SNORM = 0x1,
+ IMG_NUM_FORMAT_USCALED = 0x2,
+ IMG_NUM_FORMAT_SSCALED = 0x3,
+ IMG_NUM_FORMAT_UINT = 0x4,
+ IMG_NUM_FORMAT_SINT = 0x5,
+ IMG_NUM_FORMAT_RESERVED_6 = 0x6,
+ IMG_NUM_FORMAT_FLOAT = 0x7,
+ IMG_NUM_FORMAT_RESERVED_8 = 0x8,
+ IMG_NUM_FORMAT_SRGB = 0x9,
+ IMG_NUM_FORMAT_RESERVED_10 = 0xa,
+ IMG_NUM_FORMAT_RESERVED_11 = 0xb,
+ IMG_NUM_FORMAT_RESERVED_12 = 0xc,
+ IMG_NUM_FORMAT_RESERVED_13 = 0xd,
+ IMG_NUM_FORMAT_RESERVED_14 = 0xe,
+ IMG_NUM_FORMAT_RESERVED_15 = 0xf,
+} IMG_NUM_FORMAT;
+typedef enum TileType {
+ ARRAY_COLOR_TILE = 0x0,
+ ARRAY_DEPTH_TILE = 0x1,
+} TileType;
+typedef enum NonDispTilingOrder {
+ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
+ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
+} NonDispTilingOrder;
+typedef enum MicroTileMode {
+ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
+ ADDR_SURF_THIN_MICRO_TILING = 0x1,
+ ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
+ ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
+ ADDR_SURF_THICK_MICRO_TILING = 0x4,
+} MicroTileMode;
+typedef enum TileSplit {
+ ADDR_SURF_TILE_SPLIT_64B = 0x0,
+ ADDR_SURF_TILE_SPLIT_128B = 0x1,
+ ADDR_SURF_TILE_SPLIT_256B = 0x2,
+ ADDR_SURF_TILE_SPLIT_512B = 0x3,
+ ADDR_SURF_TILE_SPLIT_1KB = 0x4,
+ ADDR_SURF_TILE_SPLIT_2KB = 0x5,
+ ADDR_SURF_TILE_SPLIT_4KB = 0x6,
+} TileSplit;
+typedef enum SampleSplit {
+ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
+ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
+ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
+ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
+} SampleSplit;
+typedef enum PipeConfig {
+ ADDR_SURF_P2 = 0x0,
+ ADDR_SURF_P2_RESERVED0 = 0x1,
+ ADDR_SURF_P2_RESERVED1 = 0x2,
+ ADDR_SURF_P2_RESERVED2 = 0x3,
+ ADDR_SURF_P4_8x16 = 0x4,
+ ADDR_SURF_P4_16x16 = 0x5,
+ ADDR_SURF_P4_16x32 = 0x6,
+ ADDR_SURF_P4_32x32 = 0x7,
+ ADDR_SURF_P8_16x16_8x16 = 0x8,
+ ADDR_SURF_P8_16x32_8x16 = 0x9,
+ ADDR_SURF_P8_32x32_8x16 = 0xa,
+ ADDR_SURF_P8_16x32_16x16 = 0xb,
+ ADDR_SURF_P8_32x32_16x16 = 0xc,
+ ADDR_SURF_P8_32x32_16x32 = 0xd,
+ ADDR_SURF_P8_32x64_32x32 = 0xe,
+ ADDR_SURF_P8_RESERVED0 = 0xf,
+ ADDR_SURF_P16_32x32_8x16 = 0x10,
+ ADDR_SURF_P16_32x32_16x16 = 0x11,
+} PipeConfig;
+typedef enum NumBanks {
+ ADDR_SURF_2_BANK = 0x0,
+ ADDR_SURF_4_BANK = 0x1,
+ ADDR_SURF_8_BANK = 0x2,
+ ADDR_SURF_16_BANK = 0x3,
+} NumBanks;
+typedef enum BankWidth {
+ ADDR_SURF_BANK_WIDTH_1 = 0x0,
+ ADDR_SURF_BANK_WIDTH_2 = 0x1,
+ ADDR_SURF_BANK_WIDTH_4 = 0x2,
+ ADDR_SURF_BANK_WIDTH_8 = 0x3,
+} BankWidth;
+typedef enum BankHeight {
+ ADDR_SURF_BANK_HEIGHT_1 = 0x0,
+ ADDR_SURF_BANK_HEIGHT_2 = 0x1,
+ ADDR_SURF_BANK_HEIGHT_4 = 0x2,
+ ADDR_SURF_BANK_HEIGHT_8 = 0x3,
+} BankHeight;
+typedef enum BankWidthHeight {
+ ADDR_SURF_BANK_WH_1 = 0x0,
+ ADDR_SURF_BANK_WH_2 = 0x1,
+ ADDR_SURF_BANK_WH_4 = 0x2,
+ ADDR_SURF_BANK_WH_8 = 0x3,
+} BankWidthHeight;
+typedef enum MacroTileAspect {
+ ADDR_SURF_MACRO_ASPECT_1 = 0x0,
+ ADDR_SURF_MACRO_ASPECT_2 = 0x1,
+ ADDR_SURF_MACRO_ASPECT_4 = 0x2,
+ ADDR_SURF_MACRO_ASPECT_8 = 0x3,
+} MacroTileAspect;
+typedef enum GATCL1RequestType {
+ GATCL1_TYPE_NORMAL = 0x0,
+ GATCL1_TYPE_SHOOTDOWN = 0x1,
+ GATCL1_TYPE_BYPASS = 0x2,
+} GATCL1RequestType;
+typedef enum TCC_CACHE_POLICIES {
+ TCC_CACHE_POLICY_LRU = 0x0,
+ TCC_CACHE_POLICY_STREAM = 0x1,
+} TCC_CACHE_POLICIES;
+typedef enum MTYPE {
+ MTYPE_NC_NV = 0x0,
+ MTYPE_NC = 0x1,
+ MTYPE_CC = 0x2,
+ MTYPE_UC = 0x3,
+} MTYPE;
+typedef enum PERFMON_COUNTER_MODE {
+ PERFMON_COUNTER_MODE_ACCUM = 0x0,
+ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
+ PERFMON_COUNTER_MODE_MAX = 0x2,
+ PERFMON_COUNTER_MODE_DIRTY = 0x3,
+ PERFMON_COUNTER_MODE_SAMPLE = 0x4,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
+ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
+ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
+ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
+ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
+ PERFMON_COUNTER_MODE_RESERVED = 0xf,
+} PERFMON_COUNTER_MODE;
+typedef enum PERFMON_SPM_MODE {
+ PERFMON_SPM_MODE_OFF = 0x0,
+ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
+ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
+ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
+ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
+ PERFMON_SPM_MODE_RESERVED_5 = 0x5,
+ PERFMON_SPM_MODE_RESERVED_6 = 0x6,
+ PERFMON_SPM_MODE_RESERVED_7 = 0x7,
+ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
+ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
+ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
+} PERFMON_SPM_MODE;
+typedef enum SurfaceTiling {
+ ARRAY_LINEAR = 0x0,
+ ARRAY_TILED = 0x1,
+} SurfaceTiling;
+typedef enum SurfaceArray {
+ ARRAY_1D = 0x0,
+ ARRAY_2D = 0x1,
+ ARRAY_3D = 0x2,
+ ARRAY_3D_SLICE = 0x3,
+} SurfaceArray;
+typedef enum ColorArray {
+ ARRAY_2D_ALT_COLOR = 0x0,
+ ARRAY_2D_COLOR = 0x1,
+ ARRAY_3D_SLICE_COLOR = 0x3,
+} ColorArray;
+typedef enum DepthArray {
+ ARRAY_2D_ALT_DEPTH = 0x0,
+ ARRAY_2D_DEPTH = 0x1,
+} DepthArray;
+typedef enum ENUM_NUM_SIMD_PER_CU {
+ NUM_SIMD_PER_CU = 0x4,
+} ENUM_NUM_SIMD_PER_CU;
+typedef enum MEM_PWR_FORCE_CTRL {
+ NO_FORCE_REQUEST = 0x0,
+ FORCE_LIGHT_SLEEP_REQUEST = 0x1,
+ FORCE_DEEP_SLEEP_REQUEST = 0x2,
+ FORCE_SHUT_DOWN_REQUEST = 0x3,
+} MEM_PWR_FORCE_CTRL;
+typedef enum MEM_PWR_FORCE_CTRL2 {
+ NO_FORCE_REQ = 0x0,
+ FORCE_LIGHT_SLEEP_REQ = 0x1,
+} MEM_PWR_FORCE_CTRL2;
+typedef enum MEM_PWR_DIS_CTRL {
+ ENABLE_MEM_PWR_CTRL = 0x0,
+ DISABLE_MEM_PWR_CTRL = 0x1,
+} MEM_PWR_DIS_CTRL;
+typedef enum MEM_PWR_SEL_CTRL {
+ DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
+ DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
+ DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
+} MEM_PWR_SEL_CTRL;
+typedef enum MEM_PWR_SEL_CTRL2 {
+ DYNAMIC_DEEP_SLEEP_EN = 0x0,
+ DYNAMIC_LIGHT_SLEEP_EN = 0x1,
+} MEM_PWR_SEL_CTRL2;
+
+#endif /* UVD_6_0_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h
new file mode 100644
index 000000000000..9917c543d895
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h
@@ -0,0 +1,1034 @@
+/*
+ * UVD_6_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef UVD_6_0_SH_MASK_H
+#define UVD_6_0_SH_MASK_H
+
+#define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
+#define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
+#define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
+#define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
+#define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
+#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
+#define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
+#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
+#define UVD_SEMA_CMD__MODE_MASK 0x40
+#define UVD_SEMA_CMD__MODE__SHIFT 0x6
+#define UVD_SEMA_CMD__VMID_EN_MASK 0x80
+#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7
+#define UVD_SEMA_CMD__VMID_MASK 0xf00
+#define UVD_SEMA_CMD__VMID__SHIFT 0x8
+#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1
+#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0
+#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffe
+#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1
+#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000
+#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f
+#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff
+#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0
+#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffff
+#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0
+#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1
+#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0
+#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2
+#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1
+#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define UVD_POWER_STATUS_U__UVD_POWER_STATUS_MASK 0x3
+#define UVD_POWER_STATUS_U__UVD_POWER_STATUS__SHIFT 0x0
+#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff
+#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff
+#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff
+#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff
+#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff
+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff
+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
+#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1
+#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0
+#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2
+#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1
+#define UVD_LMI_EXT40_ADDR__ADDR_MASK 0xff
+#define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x0
+#define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x1f0000
+#define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x10
+#define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000
+#define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x1f
+#define UVD_CTX_INDEX__INDEX_MASK 0x1ff
+#define UVD_CTX_INDEX__INDEX__SHIFT 0x0
+#define UVD_CTX_DATA__DATA_MASK 0xffffffff
+#define UVD_CTX_DATA__DATA__SHIFT 0x0
+#define UVD_CGC_GATE__SYS_MASK 0x1
+#define UVD_CGC_GATE__SYS__SHIFT 0x0
+#define UVD_CGC_GATE__UDEC_MASK 0x2
+#define UVD_CGC_GATE__UDEC__SHIFT 0x1
+#define UVD_CGC_GATE__MPEG2_MASK 0x4
+#define UVD_CGC_GATE__MPEG2__SHIFT 0x2
+#define UVD_CGC_GATE__REGS_MASK 0x8
+#define UVD_CGC_GATE__REGS__SHIFT 0x3
+#define UVD_CGC_GATE__RBC_MASK 0x10
+#define UVD_CGC_GATE__RBC__SHIFT 0x4
+#define UVD_CGC_GATE__LMI_MC_MASK 0x20
+#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5
+#define UVD_CGC_GATE__LMI_UMC_MASK 0x40
+#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6
+#define UVD_CGC_GATE__IDCT_MASK 0x80
+#define UVD_CGC_GATE__IDCT__SHIFT 0x7
+#define UVD_CGC_GATE__MPRD_MASK 0x100
+#define UVD_CGC_GATE__MPRD__SHIFT 0x8
+#define UVD_CGC_GATE__MPC_MASK 0x200
+#define UVD_CGC_GATE__MPC__SHIFT 0x9
+#define UVD_CGC_GATE__LBSI_MASK 0x400
+#define UVD_CGC_GATE__LBSI__SHIFT 0xa
+#define UVD_CGC_GATE__LRBBM_MASK 0x800
+#define UVD_CGC_GATE__LRBBM__SHIFT 0xb
+#define UVD_CGC_GATE__UDEC_RE_MASK 0x1000
+#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc
+#define UVD_CGC_GATE__UDEC_CM_MASK 0x2000
+#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd
+#define UVD_CGC_GATE__UDEC_IT_MASK 0x4000
+#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe
+#define UVD_CGC_GATE__UDEC_DB_MASK 0x8000
+#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf
+#define UVD_CGC_GATE__UDEC_MP_MASK 0x10000
+#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10
+#define UVD_CGC_GATE__WCB_MASK 0x20000
+#define UVD_CGC_GATE__WCB__SHIFT 0x11
+#define UVD_CGC_GATE__VCPU_MASK 0x40000
+#define UVD_CGC_GATE__VCPU__SHIFT 0x12
+#define UVD_CGC_GATE__SCPU_MASK 0x80000
+#define UVD_CGC_GATE__SCPU__SHIFT 0x13
+#define UVD_CGC_GATE__JPEG_MASK 0x100000
+#define UVD_CGC_GATE__JPEG__SHIFT 0x14
+#define UVD_CGC_GATE__JPEG2_MASK 0x200000
+#define UVD_CGC_GATE__JPEG2__SHIFT 0x15
+#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1
+#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0
+#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2
+#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1
+#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x4
+#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2
+#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x8
+#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3
+#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10
+#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4
+#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x20
+#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5
+#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40
+#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6
+#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x80
+#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7
+#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100
+#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8
+#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200
+#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9
+#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400
+#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa
+#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800
+#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb
+#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000
+#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc
+#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x2000
+#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd
+#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x4000
+#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe
+#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x8000
+#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf
+#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x10000
+#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10
+#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000
+#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11
+#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000
+#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12
+#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000
+#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13
+#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000
+#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
+#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x200000
+#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15
+#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x400000
+#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16
+#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000
+#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17
+#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000
+#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18
+#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x2000000
+#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19
+#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x4000000
+#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a
+#define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x8000000
+#define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b
+#define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000
+#define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c
+#define UVD_CGC_STATUS__JPEG_ACTIVE_MASK 0x40000000
+#define UVD_CGC_STATUS__JPEG_ACTIVE__SHIFT 0x1e
+#define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000
+#define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f
+#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1
+#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
+#define UVD_CGC_CTRL__JPEG2_MODE_MASK 0x2
+#define UVD_CGC_CTRL__JPEG2_MODE__SHIFT 0x1
+#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c
+#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2
+#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0
+#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6
+#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800
+#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb
+#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000
+#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc
+#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000
+#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
+#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000
+#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe
+#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000
+#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf
+#define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000
+#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
+#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000
+#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11
+#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000
+#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12
+#define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000
+#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13
+#define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000
+#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14
+#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000
+#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15
+#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000
+#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16
+#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000
+#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17
+#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000
+#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18
+#define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000
+#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19
+#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000
+#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a
+#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000
+#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b
+#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000
+#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c
+#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000
+#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d
+#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000
+#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e
+#define UVD_CGC_CTRL__JPEG_MODE_MASK 0x80000000
+#define UVD_CGC_CTRL__JPEG_MODE__SHIFT 0x1f
+#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x1
+#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0
+#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2
+#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1
+#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x4
+#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2
+#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8
+#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3
+#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10
+#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4
+#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20
+#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5
+#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x40
+#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6
+#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80
+#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7
+#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100
+#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8
+#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200
+#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9
+#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x400
+#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa
+#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800
+#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb
+#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000
+#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc
+#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000
+#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd
+#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000
+#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe
+#define UVD_CGC_UDEC_STATUS__JPEG_VCLK_MASK 0x8000
+#define UVD_CGC_UDEC_STATUS__JPEG_VCLK__SHIFT 0xf
+#define UVD_CGC_UDEC_STATUS__JPEG_SCLK_MASK 0x10000
+#define UVD_CGC_UDEC_STATUS__JPEG_SCLK__SHIFT 0x10
+#define UVD_CGC_UDEC_STATUS__JPEG2_VCLK_MASK 0x20000
+#define UVD_CGC_UDEC_STATUS__JPEG2_VCLK__SHIFT 0x11
+#define UVD_CGC_UDEC_STATUS__JPEG2_SCLK_MASK 0x40000
+#define UVD_CGC_UDEC_STATUS__JPEG2_SCLK__SHIFT 0x12
+#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x1
+#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0
+#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2
+#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1
+#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x4
+#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2
+#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x8
+#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3
+#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x70
+#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x4
+#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x80
+#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7
+#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100
+#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
+#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x600
+#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9
+#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x1800
+#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb
+#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x2000
+#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd
+#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x4000
+#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe
+#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000
+#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf
+#define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x10000
+#define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10
+#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x1fe0000
+#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11
+#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x1
+#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0
+#define UVD_MASTINT_EN__VCPU_EN_MASK 0x2
+#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1
+#define UVD_MASTINT_EN__SYS_EN_MASK 0x4
+#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2
+#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x7ffff0
+#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4
+#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0xf
+#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x0
+#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0xf0
+#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x4
+#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0xf00
+#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x8
+#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0xf000
+#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0xc
+#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0xf0000
+#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x10
+#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0xf00000
+#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14
+#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0xf000000
+#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x18
+#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000
+#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x1c
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0xff
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100
+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8
+#define UVD_LMI_CTRL__REQ_MODE_MASK 0x200
+#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9
+#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800
+#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb
+#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000
+#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc
+#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x2000
+#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd
+#define UVD_LMI_CTRL__CRC_RESET_MASK 0x4000
+#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe
+#define UVD_LMI_CTRL__CRC_SEL_MASK 0xf8000
+#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf
+#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x100000
+#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14
+#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000
+#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15
+#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x400000
+#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16
+#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x800000
+#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17
+#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x1000000
+#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18
+#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x2000000
+#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19
+#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x4000000
+#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a
+#define UVD_LMI_CTRL__RFU_MASK 0xf8000000
+#define UVD_LMI_CTRL__RFU__SHIFT 0x1b
+#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x1
+#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0
+#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2
+#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1
+#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4
+#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2
+#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x8
+#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3
+#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x10
+#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4
+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x20
+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5
+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x40
+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6
+#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x80
+#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7
+#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100
+#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8
+#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200
+#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9
+#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x400
+#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa
+#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800
+#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb
+#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000
+#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc
+#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x2000
+#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd
+#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x3
+#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
+#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0xc
+#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
+#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x30
+#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4
+#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0xc0
+#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6
+#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x300
+#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8
+#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0xc00
+#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa
+#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x3000
+#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc
+#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0xc000
+#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe
+#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x30000
+#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10
+#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0xc0000
+#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12
+#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0xc00000
+#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16
+#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x3000000
+#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18
+#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0xc000000
+#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a
+#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000
+#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c
+#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000
+#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e
+#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x3
+#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0
+#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0xc
+#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2
+#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x30
+#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4
+#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0xc0
+#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6
+#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x300
+#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8
+#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0xc00
+#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa
+#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x3000
+#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc
+#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0xc000
+#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe
+#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x30000
+#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10
+#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0xc0000
+#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12
+#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x300000
+#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14
+#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0xc00000
+#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16
+#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x3000000
+#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18
+#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0xc000000
+#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a
+#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000
+#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c
+#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000
+#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e
+#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38
+#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3
+#define UVD_MPC_CNTL__PERF_RST_MASK 0x40
+#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6
+#define UVD_MPC_CNTL__DBG_MUX_MASK 0xf00
+#define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x8
+#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x30000
+#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10
+#define UVD_MPC_CNTL__URGENT_EN_MASK 0x40000
+#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12
+#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f
+#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0
+#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0
+#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6
+#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000
+#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc
+#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000
+#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12
+#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000
+#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18
+#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f
+#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0
+#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0
+#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6
+#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000
+#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc
+#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x3f
+#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0
+#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0
+#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6
+#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x3f000
+#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc
+#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0xfc0000
+#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12
+#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000
+#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18
+#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f
+#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0
+#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0xfc0
+#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6
+#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000
+#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc
+#define UVD_MPC_SET_MUX__SET_0_MASK 0x7
+#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0
+#define UVD_MPC_SET_MUX__SET_1_MASK 0x38
+#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3
+#define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0
+#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6
+#define UVD_MPC_SET_ALU__FUNCT_MASK 0x7
+#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0
+#define UVD_MPC_SET_ALU__OPERAND_MASK 0xff0
+#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4
+#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff
+#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff
+#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff
+#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff
+#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0
+#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x1ffffff
+#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0
+#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x1fffff
+#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0
+#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0xf
+#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0
+#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x10
+#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4
+#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x20
+#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5
+#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x40
+#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6
+#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x80
+#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7
+#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100
+#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8
+#define UVD_VCPU_CNTL__CLK_EN_MASK 0x200
+#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9
+#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x400
+#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa
+#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800
+#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb
+#define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000
+#define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd
+#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x10000
+#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10
+#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x20000
+#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11
+#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x40000
+#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12
+#define UVD_VCPU_CNTL__SUVD_EN_MASK 0x80000
+#define UVD_VCPU_CNTL__SUVD_EN__SHIFT 0x13
+#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0xff00000
+#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14
+#define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000
+#define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c
+#define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000
+#define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e
+#define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000
+#define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f
+#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x1
+#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0
+#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2
+#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1
+#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x4
+#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2
+#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x8
+#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3
+#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x10
+#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4
+#define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x20
+#define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5
+#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x40
+#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6
+#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x80
+#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7
+#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100
+#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8
+#define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS_MASK 0x200
+#define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS__SHIFT 0x9
+#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x400
+#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa
+#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800
+#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb
+#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000
+#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc
+#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x2000
+#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd
+#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x4000
+#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe
+#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x8000
+#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf
+#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x10000
+#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10
+#define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x20000
+#define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11
+#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x40000
+#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12
+#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x80000
+#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13
+#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x100000
+#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14
+#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x200000
+#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15
+#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x400000
+#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16
+#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x800000
+#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17
+#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x1000000
+#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18
+#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x2000000
+#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19
+#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x4000000
+#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a
+#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x8000000
+#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b
+#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000
+#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c
+#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000
+#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d
+#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000
+#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e
+#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000
+#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f
+#define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0xf
+#define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0
+#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x7ffff0
+#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4
+#define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0xf
+#define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0
+#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x7ffff0
+#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4
+#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x7ffff0
+#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4
+#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x1f
+#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0
+#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x1f00
+#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8
+#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000
+#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10
+#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x100000
+#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14
+#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x1000000
+#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18
+#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000
+#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c
+#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffff
+#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0
+#define UVD_STATUS__RBC_BUSY_MASK 0x1
+#define UVD_STATUS__RBC_BUSY__SHIFT 0x0
+#define UVD_STATUS__VCPU_REPORT_MASK 0xfe
+#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x1
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x4
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x8
+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x1
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x1ffffe
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x1
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x1ffffe
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x1
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x1ffffe
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
+#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffff
+#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0
+#define UVD_SUVD_CGC_GATE__SRE_MASK 0x1
+#define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0
+#define UVD_SUVD_CGC_GATE__SIT_MASK 0x2
+#define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1
+#define UVD_SUVD_CGC_GATE__SMP_MASK 0x4
+#define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2
+#define UVD_SUVD_CGC_GATE__SCM_MASK 0x8
+#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3
+#define UVD_SUVD_CGC_GATE__SDB_MASK 0x10
+#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4
+#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x20
+#define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
+#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x40
+#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6
+#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x80
+#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7
+#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x100
+#define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8
+#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x200
+#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9
+#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x400
+#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
+#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x800
+#define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb
+#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000
+#define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc
+#define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x1
+#define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0
+#define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x2
+#define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1
+#define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x4
+#define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2
+#define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x8
+#define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3
+#define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x10
+#define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4
+#define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x20
+#define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5
+#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x40
+#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6
+#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x80
+#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7
+#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x100
+#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8
+#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x200
+#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9
+#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x400
+#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa
+#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x800
+#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb
+#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x1000
+#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc
+#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x2000
+#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd
+#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1
+#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0
+#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x2
+#define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1
+#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x4
+#define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2
+#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x8
+#define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3
+#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x10
+#define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4
+#define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID_MASK 0xf
+#define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID__SHIFT 0x0
+#define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID_MASK 0xf0
+#define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID__SHIFT 0x4
+#define UVD_LMI_VMID_INTERNAL__DPB_VMID_MASK 0xf00
+#define UVD_LMI_VMID_INTERNAL__DPB_VMID__SHIFT 0x8
+#define UVD_LMI_VMID_INTERNAL__DBW_VMID_MASK 0xf000
+#define UVD_LMI_VMID_INTERNAL__DBW_VMID__SHIFT 0xc
+#define UVD_LMI_VMID_INTERNAL__LBSI_VMID_MASK 0xf0000
+#define UVD_LMI_VMID_INTERNAL__LBSI_VMID__SHIFT 0x10
+#define UVD_LMI_VMID_INTERNAL__IDCT_VMID_MASK 0xf00000
+#define UVD_LMI_VMID_INTERNAL__IDCT_VMID__SHIFT 0x14
+#define UVD_LMI_VMID_INTERNAL__JPEG_VMID_MASK 0xf000000
+#define UVD_LMI_VMID_INTERNAL__JPEG_VMID__SHIFT 0x18
+#define UVD_LMI_VMID_INTERNAL__JPEG2_VMID_MASK 0xf0000000
+#define UVD_LMI_VMID_INTERNAL__JPEG2_VMID__SHIFT 0x1c
+#define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID_MASK 0xf
+#define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID__SHIFT 0x0
+#define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID_MASK 0xf0
+#define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID__SHIFT 0x4
+#define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID_MASK 0xf00
+#define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID__SHIFT 0x8
+#define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID_MASK 0xf000
+#define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID__SHIFT 0xc
+#define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID_MASK 0xf0000
+#define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID__SHIFT 0x10
+#define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID_MASK 0xf00000
+#define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID__SHIFT 0x14
+#define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID_MASK 0xf000000
+#define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID__SHIFT 0x18
+#define UVD_LMI_VMID_INTERNAL2__VDMA_VMID_MASK 0xf0000000
+#define UVD_LMI_VMID_INTERNAL2__VDMA_VMID__SHIFT 0x1c
+#define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x1
+#define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x0
+#define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2
+#define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x1
+#define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x4
+#define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2
+#define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x8
+#define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x3
+#define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x10
+#define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x4
+#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x20
+#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x5
+#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x3
+#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0
+#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0xc
+#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2
+#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0xf
+#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x0
+#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0xf0
+#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x4
+#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0xf00
+#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x8
+#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0xf000
+#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0xc
+#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x1
+#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0
+#define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2
+#define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1
+#define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x4
+#define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2
+#define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x8
+#define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3
+#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x10
+#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4
+#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20
+#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5
+#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x40
+#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6
+#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80
+#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7
+#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100
+#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8
+#define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200
+#define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9
+#define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x400
+#define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa
+#define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800
+#define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0xb
+#define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000
+#define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc
+#define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x2000
+#define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd
+#define UVD_CGC_MEM_CTRL__JPEG_LS_EN_MASK 0x4000
+#define UVD_CGC_MEM_CTRL__JPEG_LS_EN__SHIFT 0xe
+#define UVD_CGC_MEM_CTRL__JPEG2_LS_EN_MASK 0x8000
+#define UVD_CGC_MEM_CTRL__JPEG2_LS_EN__SHIFT 0xf
+#define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0xf0000
+#define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10
+#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0xf00000
+#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14
+#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1
+#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0
+#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2
+#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1
+#define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x1c
+#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2
+#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID_MASK 0xf
+#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID__SHIFT 0x0
+#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID_MASK 0xf0
+#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID__SHIFT 0x4
+#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID_MASK 0xf00
+#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID__SHIFT 0x8
+#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID_MASK 0xf000
+#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID__SHIFT 0xc
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0xff
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x0
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x8
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x9
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x400
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0xb
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0xc
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x2000
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0xd
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000
+#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x1c
+#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0xffffff
+#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x0
+#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0xffffff
+#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x0
+#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x3
+#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0
+#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4
+#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2
+#define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT_MASK 0x8
+#define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT__SHIFT 0x3
+#define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT_MASK 0x10
+#define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT__SHIFT 0x4
+#define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT_MASK 0x20
+#define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT__SHIFT 0x5
+#define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE_MASK 0xc0
+#define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE__SHIFT 0x6
+#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100
+#define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8
+#define UVD_POWER_STATUS__PAUSE_DPG_REQ_MASK 0x200
+#define UVD_POWER_STATUS__PAUSE_DPG_REQ__SHIFT 0x9
+#define UVD_POWER_STATUS__PAUSE_DPG_ACK_MASK 0x400
+#define UVD_POWER_STATUS__PAUSE_DPG_ACK__SHIFT 0xa
+#define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE_MASK 0xffffff
+#define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE__SHIFT 0x0
+#define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE_MASK 0xffffff
+#define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE__SHIFT 0x0
+#define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE_MASK 0xffffff
+#define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE__SHIFT 0x0
+#define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE_MASK 0xffffff
+#define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE__SHIFT 0x0
+#define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE_MASK 0xffffff
+#define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE__SHIFT 0x0
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+
+#endif /* UVD_6_0_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_d.h
new file mode 100644
index 000000000000..906433834d01
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_d.h
@@ -0,0 +1,68 @@
+/*
+ * VCE_2_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef VCE_2_0_D_H
+#define VCE_2_0_D_H
+
+#define mmVCE_STATUS 0x8001
+#define mmVCE_VCPU_CNTL 0x8005
+#define mmVCE_VCPU_CACHE_OFFSET0 0x8009
+#define mmVCE_VCPU_CACHE_SIZE0 0x800a
+#define mmVCE_VCPU_CACHE_OFFSET1 0x800b
+#define mmVCE_VCPU_CACHE_SIZE1 0x800c
+#define mmVCE_VCPU_CACHE_OFFSET2 0x800d
+#define mmVCE_VCPU_CACHE_SIZE2 0x800e
+#define mmVCE_SOFT_RESET 0x8048
+#define mmVCE_RB_BASE_LO2 0x805b
+#define mmVCE_RB_BASE_HI2 0x805c
+#define mmVCE_RB_SIZE2 0x805d
+#define mmVCE_RB_RPTR2 0x805e
+#define mmVCE_RB_WPTR2 0x805f
+#define mmVCE_RB_BASE_LO 0x8060
+#define mmVCE_RB_BASE_HI 0x8061
+#define mmVCE_RB_SIZE 0x8062
+#define mmVCE_RB_RPTR 0x8063
+#define mmVCE_RB_WPTR 0x8064
+#define mmVCE_RB_ARB_CTRL 0x809f
+#define mmVCE_CLOCK_GATING_A 0x80be
+#define mmVCE_CLOCK_GATING_B 0x80bf
+#define mmVCE_UENC_DMA_DCLK_CTRL 0x8390
+#define mmVCE_CGTT_CLK_OVERRIDE 0x81e8
+#define mmVCE_UENC_CLOCK_GATING 0x81ef
+#define mmVCE_UENC_REG_CLOCK_GATING 0x81f0
+#define mmVCE_SYS_INT_EN 0x84c0
+#define mmVCE_SYS_INT_STATUS 0x84c1
+#define mmVCE_SYS_INT_ACK 0x84c1
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0x8517
+#define mmVCE_LMI_CTRL2 0x851d
+#define mmVCE_LMI_SWAP_CNTL3 0x851e
+#define mmVCE_LMI_CTRL 0x8526
+#define mmVCE_LMI_STATUS 0x8527
+#define mmVCE_LMI_VM_CTRL 0x8528
+#define mmVCE_LMI_SWAP_CNTL 0x852d
+#define mmVCE_LMI_SWAP_CNTL1 0x852e
+#define mmVCE_LMI_SWAP_CNTL2 0x8533
+#define mmVCE_LMI_MISC_CTRL 0x8535
+#define mmVCE_LMI_CACHE_CTRL 0x853d
+
+#endif /* VCE_2_0_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_sh_mask.h
new file mode 100644
index 000000000000..9b4b952b9830
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_sh_mask.h
@@ -0,0 +1,104 @@
+/*
+ * VCE_2_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef VCE_2_0_SH_MASK_H
+#define VCE_2_0_SH_MASK_H
+
+#define VCE_STATUS__JOB_BUSY_MASK 0x1
+#define VCE_STATUS__JOB_BUSY__SHIFT 0x0
+#define VCE_STATUS__VCPU_REPORT_MASK 0xfe
+#define VCE_STATUS__VCPU_REPORT__SHIFT 0x1
+#define VCE_STATUS__UENC_BUSY_MASK 0x100
+#define VCE_STATUS__UENC_BUSY__SHIFT 0x8
+#define VCE_VCPU_CNTL__CLK_EN_MASK 0x1
+#define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x0
+#define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x40000
+#define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x12
+#define VCE_VCPU_CACHE_OFFSET0__OFFSET_MASK 0xfffffff
+#define VCE_VCPU_CACHE_OFFSET0__OFFSET__SHIFT 0x0
+#define VCE_VCPU_CACHE_SIZE0__SIZE_MASK 0xffffff
+#define VCE_VCPU_CACHE_SIZE0__SIZE__SHIFT 0x0
+#define VCE_VCPU_CACHE_OFFSET1__OFFSET_MASK 0xfffffff
+#define VCE_VCPU_CACHE_OFFSET1__OFFSET__SHIFT 0x0
+#define VCE_VCPU_CACHE_SIZE1__SIZE_MASK 0xffffff
+#define VCE_VCPU_CACHE_SIZE1__SIZE__SHIFT 0x0
+#define VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK 0xfffffff
+#define VCE_VCPU_CACHE_OFFSET2__OFFSET__SHIFT 0x0
+#define VCE_VCPU_CACHE_SIZE2__SIZE_MASK 0xffffff
+#define VCE_VCPU_CACHE_SIZE2__SIZE__SHIFT 0x0
+#define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK 0x1
+#define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT 0x0
+#define VCE_RB_BASE_LO2__RB_BASE_LO_MASK 0xffffffc0
+#define VCE_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6
+#define VCE_RB_BASE_HI2__RB_BASE_HI_MASK 0xffffffff
+#define VCE_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0
+#define VCE_RB_SIZE2__RB_SIZE_MASK 0x7ffff0
+#define VCE_RB_SIZE2__RB_SIZE__SHIFT 0x4
+#define VCE_RB_RPTR2__RB_RPTR_MASK 0x7ffff0
+#define VCE_RB_RPTR2__RB_RPTR__SHIFT 0x4
+#define VCE_RB_WPTR2__RB_WPTR_MASK 0x7ffff0
+#define VCE_RB_WPTR2__RB_WPTR__SHIFT 0x4
+#define VCE_RB_BASE_LO__RB_BASE_LO_MASK 0xffffffc0
+#define VCE_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6
+#define VCE_RB_BASE_HI__RB_BASE_HI_MASK 0xffffffff
+#define VCE_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0
+#define VCE_RB_SIZE__RB_SIZE_MASK 0x7ffff0
+#define VCE_RB_SIZE__RB_SIZE__SHIFT 0x4
+#define VCE_RB_RPTR__RB_RPTR_MASK 0x7ffff0
+#define VCE_RB_RPTR__RB_RPTR__SHIFT 0x4
+#define VCE_RB_WPTR__RB_WPTR_MASK 0x7ffff0
+#define VCE_RB_WPTR__RB_WPTR__SHIFT 0x4
+#define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK 0x1
+#define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON__SHIFT 0x0
+#define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK 0x2
+#define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON__SHIFT 0x1
+#define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK 0x4
+#define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON__SHIFT 0x2
+#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK 0x8
+#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT 0x3
+#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK 0x8
+#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT 0x3
+#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK_MASK 0x8
+#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT 0x3
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR_MASK 0xffffffff
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR__SHIFT 0x0
+#define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100
+#define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
+#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP_MASK 0x3
+#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP__SHIFT 0x0
+#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000
+#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15
+#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x3
+#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x0
+#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP_MASK 0x3ffc
+#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT 0x2
+#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x3
+#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT 0x0
+#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK 0x3ffc
+#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x2
+#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP_MASK 0xff
+#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP__SHIFT 0x0
+#define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x1
+#define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x0
+
+#endif /* VCE_2_0_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_d.h
new file mode 100644
index 000000000000..3e698b7f42a2
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_d.h
@@ -0,0 +1,73 @@
+/*
+ * VCE_3_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef VCE_3_0_D_H
+#define VCE_3_0_D_H
+
+#define mmVCE_STATUS 0x8001
+#define mmVCE_VCPU_CNTL 0x8005
+#define mmVCE_VCPU_CACHE_OFFSET0 0x8009
+#define mmVCE_VCPU_CACHE_SIZE0 0x800a
+#define mmVCE_VCPU_CACHE_OFFSET1 0x800b
+#define mmVCE_VCPU_CACHE_SIZE1 0x800c
+#define mmVCE_VCPU_CACHE_OFFSET2 0x800d
+#define mmVCE_VCPU_CACHE_SIZE2 0x800e
+#define mmVCE_SOFT_RESET 0x8048
+#define mmVCE_RB_BASE_LO2 0x805b
+#define mmVCE_RB_BASE_HI2 0x805c
+#define mmVCE_RB_SIZE2 0x805d
+#define mmVCE_RB_RPTR2 0x805e
+#define mmVCE_RB_WPTR2 0x805f
+#define mmVCE_RB_BASE_LO 0x8060
+#define mmVCE_RB_BASE_HI 0x8061
+#define mmVCE_RB_SIZE 0x8062
+#define mmVCE_RB_RPTR 0x8063
+#define mmVCE_RB_WPTR 0x8064
+#define mmVCE_RB_ARB_CTRL 0x809f
+#define mmVCE_CLOCK_GATING_A 0x80be
+#define mmVCE_CLOCK_GATING_B 0x80bf
+#define mmVCE_RB_BASE_LO3 0x80d4
+#define mmVCE_RB_BASE_HI3 0x80d5
+#define mmVCE_RB_SIZE3 0x80d6
+#define mmVCE_RB_RPTR3 0x80d7
+#define mmVCE_RB_WPTR3 0x80d8
+#define mmVCE_UENC_DMA_DCLK_CTRL 0x8390
+#define mmVCE_UENC_CLOCK_GATING 0x81ef
+#define mmVCE_UENC_REG_CLOCK_GATING 0x81f0
+#define mmVCE_UENC_CLOCK_GATING_2 0x8210
+#define mmVCE_SYS_INT_EN 0x8540
+#define mmVCE_SYS_INT_STATUS 0x8541
+#define mmVCE_SYS_INT_ACK 0x8541
+#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0x8597
+#define mmVCE_LMI_CTRL2 0x859d
+#define mmVCE_LMI_SWAP_CNTL3 0x859e
+#define mmVCE_LMI_CTRL 0x85a6
+#define mmVCE_LMI_STATUS 0x85a7
+#define mmVCE_LMI_VM_CTRL 0x85a8
+#define mmVCE_LMI_SWAP_CNTL 0x85ad
+#define mmVCE_LMI_SWAP_CNTL1 0x85ae
+#define mmVCE_LMI_SWAP_CNTL2 0x85b3
+#define mmVCE_LMI_MISC_CTRL 0x85b5
+#define mmVCE_LMI_CACHE_CTRL 0x85bd
+
+#endif /* VCE_3_0_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_sh_mask.h
new file mode 100644
index 000000000000..235dc13561e9
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_3_0_sh_mask.h
@@ -0,0 +1,120 @@
+/*
+ * VCE_3_0 Register documentation
+ *
+ * Copyright (C) 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef VCE_3_0_SH_MASK_H
+#define VCE_3_0_SH_MASK_H
+
+#define VCE_STATUS__JOB_BUSY_MASK 0x1
+#define VCE_STATUS__JOB_BUSY__SHIFT 0x0
+#define VCE_STATUS__VCPU_REPORT_MASK 0xfe
+#define VCE_STATUS__VCPU_REPORT__SHIFT 0x1
+#define VCE_STATUS__UENC_BUSY_MASK 0x100
+#define VCE_STATUS__UENC_BUSY__SHIFT 0x8
+#define VCE_STATUS__VCE_CONFIGURATION_MASK 0xc00000
+#define VCE_STATUS__VCE_CONFIGURATION__SHIFT 0x16
+#define VCE_STATUS__VCE_INSTANCE_ID_MASK 0x3000000
+#define VCE_STATUS__VCE_INSTANCE_ID__SHIFT 0x18
+#define VCE_VCPU_CNTL__CLK_EN_MASK 0x1
+#define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x0
+#define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x40000
+#define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x12
+#define VCE_VCPU_CACHE_OFFSET0__OFFSET_MASK 0xfffffff
+#define VCE_VCPU_CACHE_OFFSET0__OFFSET__SHIFT 0x0
+#define VCE_VCPU_CACHE_SIZE0__SIZE_MASK 0xffffff
+#define VCE_VCPU_CACHE_SIZE0__SIZE__SHIFT 0x0
+#define VCE_VCPU_CACHE_OFFSET1__OFFSET_MASK 0xfffffff
+#define VCE_VCPU_CACHE_OFFSET1__OFFSET__SHIFT 0x0
+#define VCE_VCPU_CACHE_SIZE1__SIZE_MASK 0xffffff
+#define VCE_VCPU_CACHE_SIZE1__SIZE__SHIFT 0x0
+#define VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK 0xfffffff
+#define VCE_VCPU_CACHE_OFFSET2__OFFSET__SHIFT 0x0
+#define VCE_VCPU_CACHE_SIZE2__SIZE_MASK 0xffffff
+#define VCE_VCPU_CACHE_SIZE2__SIZE__SHIFT 0x0
+#define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK 0x1
+#define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT 0x0
+#define VCE_RB_BASE_LO2__RB_BASE_LO_MASK 0xffffffc0
+#define VCE_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6
+#define VCE_RB_BASE_HI2__RB_BASE_HI_MASK 0xffffffff
+#define VCE_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0
+#define VCE_RB_SIZE2__RB_SIZE_MASK 0x7ffff0
+#define VCE_RB_SIZE2__RB_SIZE__SHIFT 0x4
+#define VCE_RB_RPTR2__RB_RPTR_MASK 0x7ffff0
+#define VCE_RB_RPTR2__RB_RPTR__SHIFT 0x4
+#define VCE_RB_WPTR2__RB_WPTR_MASK 0x7ffff0
+#define VCE_RB_WPTR2__RB_WPTR__SHIFT 0x4
+#define VCE_RB_BASE_LO__RB_BASE_LO_MASK 0xffffffc0
+#define VCE_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6
+#define VCE_RB_BASE_HI__RB_BASE_HI_MASK 0xffffffff
+#define VCE_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0
+#define VCE_RB_SIZE__RB_SIZE_MASK 0x7ffff0
+#define VCE_RB_SIZE__RB_SIZE__SHIFT 0x4
+#define VCE_RB_RPTR__RB_RPTR_MASK 0x7ffff0
+#define VCE_RB_RPTR__RB_RPTR__SHIFT 0x4
+#define VCE_RB_WPTR__RB_WPTR_MASK 0x7ffff0
+#define VCE_RB_WPTR__RB_WPTR__SHIFT 0x4
+#define VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE_MASK 0x10000
+#define VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE__SHIFT 0x10
+#define VCE_RB_BASE_LO3__RB_BASE_LO_MASK 0xffffffc0
+#define VCE_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6
+#define VCE_RB_BASE_HI3__RB_BASE_HI_MASK 0xffffffff
+#define VCE_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0
+#define VCE_RB_SIZE3__RB_SIZE_MASK 0x7ffff0
+#define VCE_RB_SIZE3__RB_SIZE__SHIFT 0x4
+#define VCE_RB_RPTR3__RB_RPTR_MASK 0x7ffff0
+#define VCE_RB_RPTR3__RB_RPTR__SHIFT 0x4
+#define VCE_RB_WPTR3__RB_WPTR_MASK 0x7ffff0
+#define VCE_RB_WPTR3__RB_WPTR__SHIFT 0x4
+#define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK 0x1
+#define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON__SHIFT 0x0
+#define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK 0x2
+#define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON__SHIFT 0x1
+#define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK 0x4
+#define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON__SHIFT 0x2
+#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK 0x8
+#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT 0x3
+#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK 0x8
+#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT 0x3
+#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK_MASK 0x8
+#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT 0x3
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR_MASK 0xffffffff
+#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR__SHIFT 0x0
+#define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100
+#define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
+#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP_MASK 0x3
+#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP__SHIFT 0x0
+#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000
+#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15
+#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x3
+#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x0
+#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP_MASK 0x3ffc
+#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT 0x2
+#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x3
+#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT 0x0
+#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK 0x3ffc
+#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x2
+#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP_MASK 0xff
+#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP__SHIFT 0x0
+#define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x1
+#define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x0
+
+#endif /* VCE_3_0_SH_MASK_H */
diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
index dabd94446b7b..9080daa116b6 100644
--- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
@@ -144,6 +144,8 @@ struct kfd2kgd_calls {
int (*init_pipeline)(struct kgd_dev *kgd, uint32_t pipe_id,
uint32_t hpd_size, uint64_t hpd_gpu_addr);
+ int (*init_interrupts)(struct kgd_dev *kgd, uint32_t pipe_id);
+
int (*hqd_load)(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
uint32_t queue_id, uint32_t __user *wptr);
@@ -161,6 +163,27 @@ struct kfd2kgd_calls {
int (*hqd_sdma_destroy)(struct kgd_dev *kgd, void *mqd,
unsigned int timeout);
+ int (*address_watch_disable)(struct kgd_dev *kgd);
+ int (*address_watch_execute)(struct kgd_dev *kgd,
+ unsigned int watch_point_id,
+ uint32_t cntl_val,
+ uint32_t addr_hi,
+ uint32_t addr_lo);
+ int (*wave_control_execute)(struct kgd_dev *kgd,
+ uint32_t gfx_index_val,
+ uint32_t sq_cmd);
+ uint32_t (*address_watch_get_offset)(struct kgd_dev *kgd,
+ unsigned int watch_point_id,
+ unsigned int reg_offset);
+ bool (*get_atc_vmid_pasid_mapping_valid)(
+ struct kgd_dev *kgd,
+ uint8_t vmid);
+ uint16_t (*get_atc_vmid_pasid_mapping_pasid)(
+ struct kgd_dev *kgd,
+ uint8_t vmid);
+ void (*write_vmid_invalidate_request)(struct kgd_dev *kgd,
+ uint8_t vmid);
+
uint16_t (*get_fw_version)(struct kgd_dev *kgd,
enum kgd_engine_type type);
};
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.